1988_HD6305_Series_Handbook 1988 HD6305 Series Handbook

User Manual: 1988_HD6305_Series_Handbook

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HD630S/HD63LOS SERIES HANDBOOK
•
•
•
•
•
•
•
•

USERS MANUALS
HD630S UO
HD630S VO
HD6370S VO
HD630SX
HD630SY
HD63POSY
HD63LOS

• SOFTWARE APPLICATION NOTES:
• HARDWARE APPLICATION NOTES:
• APPENDIX: TECHNICAL Q & A
• SYSTEM APPLICATION NOTES

#U08

~HITACHI®

MEDICAL APPLICATIONS

Hitachi's products are not authorized for use in MEDICAL APPLICATIONS,
including, but not limited to, use in life support devices without the written
consent of the appropriate officer of Hitachi's sales company. Buyers of
Hitachi's products are requested to notify Hitachi's sales offices when planning
to use the products in MEDICAL APPLICATIONS.

When using this manual, the reader should keep the following in mind:
1. This manual may, wholly or partially, be subject to change without notice.
2. All rights reserved: No one is permitted to reproduce or duplicate, in any
form, the whole or part of this manual without Hitachi's permission.

3. Hitachi will not be responsible for any damage to the user that may result
from accidents or any other reasons during operation of his unit according
to this manual.
4.

This manual neither ensures the enforcement of any industrial properties
or other rights, nor sanctions the enforcement right thereof.

5. Circuitry and other examples described herein are meant merely to indicate characteristics and performance of Hitachi semiconductor-applied
products. Hitachi assumes no responsibility for any patent infringements
or other problems resulting from applications based on the examples
described herein.
6. No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.

September 1988

ii

©Copyright 1988, Hitachi America Ltd.

Printed in U.S.A.

HD630S/HD63LOS SERIES HANDBOOK
Quick Reference Guide

Addressing Modes, CPU Architecture, and Instruction Set

HD630SUO, HD630SVO, HD6370SVO User's Manual

HD630SX, HD630SY, HD63POSY User's Manual

HD63LOS User's Manual

Software Application Notes

Hardware Application Notes

APPENDIX:
1echnica1 Q and A

System Application Notes
Hitachi Sales Offices

Section 9, Page 1200

~HITACHI
iv

TABLE OF CONTENTS

Section 1

Page

HD6305/HD63L05 Series Quick Reference Guide ............................... .

Section 2
Addressing Modes, CPU Architecture, & Instruction Set

Page

1.1

Addressing Modes ................................................. .

13

1.2

CPU Registers .................................................... .

18

1.3

Instruction Set .................................................... .

20

1.4

Bit Manipulation ................................................... .

27

1.5

Symbols and Abbreviations .......................................... .

28

1.6

Executable Instructions ............................................. .

30

1.7

BIUBIH Instruction Precaution ....................................... .

95

Section 3
HD6305UO, HD6305VO, HD63705VO User's Manual
1.

OVERViEW .......................................................... .

Page
101

1.1

Features of HD6305UO, HD6305VO, HD63705VO ........................ .

101

1.2

Block Diagram. ... ............ ....... ... ..... ......... ...... .......

102

1.3

Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

103

INTERNAL HARDWARE AND OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

107

2.1

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

107

2.2

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

108

2.3

Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

110

2.4

Serial Communication Interface (SCI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

113

2.5

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

118

2.6

Internal Oscillator Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

119

2.7

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

120

2.

2.8

Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

124

2.9

Low Power Consumption Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

126

2.10

EPROM Mode (HD63705VO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

132

~HITACHI
v

3.

APPLICATION AND PRECAUTIONS ...................................... .

137

3.1

Watch-Dog Timer .................................................. .

137

3.2

Auto Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

139

3.3

Manual Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

140

3.4

AID Converter Circuit(1) ... High Speed. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .

141

3.5

AID Converter Circuit (2) ... Low Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

143
144

3.6

Precaution; - Board Design of Oscillation Circuit. . . . . . . . . . . . . . . . . . . . . . . . . .

3.7

Precaution; - Sending/Receiving Program of Serial Data. . . . . . . . . . . . . . . . .. . .

145

3.8

Precaution; - WAIT/STOP Instructions Program. . . . . . . . . . . . . . . . . . . . . . . . . . .

145

4.

PIN ARRANGEMENT AND DIMENSIONAL OUTLINE. . . . . . . . . . . . . . . . . . . . . . . . .

146

5.

ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

149

5.1

Electrical Characteristics for HD6305UO, HD6305VO. . . . . . . . . . . . . . . . . . . . . . .

149

5.2

Electrical Characteristics for HD63705VO .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

152

6.

PROGRAMMABLE ROM................................................

158

6.1

ProgrammingNerification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

158

6.2

Erasure (MCU with a window) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

159

6.3

Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

160

ROM CODE ORDER METHOD...........................................

164

APPENDIX. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

164

Design Prodcedures and Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

164

SINGLE CHIP MICROCOMPUTER ROM ORDERING PROCEDURE. . . . . . . . . . . . . . . . .

166

HD6305UO, HD6305VO ORDERING SPECIFICATIONS... . . ... . ... . . .... .... . . .. ..

168

7.

I.

Section 4
HD6305X, HD6305Y, HD63P05Y User's Manual
1.

Page

OVERViEW...........................................................

173

1.1

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

173

1.2

Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

177

2.

INTERNAL HARDWARE AND OPERATIONS ............................... .

185

2.1

Memory ......................................................... .

185

2.2

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

187

2.3

Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

189

2.4

Serial Communication Interface (SCI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

192

~HITACHI
vi

,

2.5

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

197

2.6

Internal Oscillator Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

197

2.7

Interrupts...... ..... ....... ........................... ............

199

2.8

Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

202

2.9

Low Power Dissipation Mode .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

204

3.

APPLICATION AND PRECAUTIONS. . . . . . .... . .. . . .. . . . .. . . .. . . . ... . . .. . ..

210

3.1

Memory Space Expansion of HD6305X11Y1, HD6305X2IY2, HD63P05Y1 . . . . . . . .

210

3.2

WatCh-Dog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

211

3.3

Auto Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

212

3.4

Manual Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

214

3.5

A/D Converter Circuit (1) ... High Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

215

3.6

A/D Converter Circuit (2) ... Low Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

217

3.7

Precaution; - Board Design of Oscillation Circuit. . . . . . . . . . . . . . . . . . . . . . . . . .

218

3.8

Precaution; - Program of Write Only Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

219

3.9

Precaution; - Sending/Receiving Program of Serial Data. . . . . . . . . . . . . . . . . . . .

219

3.10

Precaution; - WAIT/STOP Instructions Program. . . . . . . . . . . . . . . . . . . . . . . . . . .

220

3.11

Precaution; - To use the EPROM ON-PACKAGE
8-bit Single-chip Microcomputer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

220

4.

PIN ARRANGEMENT AND DIMENSIONAL OUTLINE ..

222

5.

ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

225

5.1

Electrical Characteristics of HD6305XO, HD6305YO, HD63P05YO . . . . . . . . . . . .

225

5.2

Electrical Characteristics of HD6305X11X2, HD6305Y11Y2, HD63P05Y1 .........

230

ROM CODE ORDER METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

237

APPENDIX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

238

6.

I.

Design Procedure and Support Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

238

II.

Ordering Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

240

SINGLE CHIP MICROCOMPUTER ROM ORDERING PROCEDURE. . . . . . . . . . . . . . . . .

240

HD6305XO/X1, HD6305YOIY1 ORDERING SPECIFICATIONS. . . . . . . . .. . . .... . . .. . .

242

Section 5
HD63L05 User's Manual
1.

Page

OVERViEW ...........................................................

251

1.1

Features of the HD63L05 MCU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

251

1.2

Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

253

~HITACHI
vii

2.

ARCHITECTURE......................................................

256

2.1

Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

256

2.2

Registers. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

257

2.3

System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

260

2.4

Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

261

2.5

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

262

2.6

Self Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

262

2.7

Internal Oscillator Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

265

2.8

Interruptions ........................._. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

268

2.9

Input/Output (Port A, B, C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

271

2.10

AID Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

271

2.11

LCD Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

276

2.12

Liquid Crystal Driver Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

277

2.13

Bit Manipulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

278

2.14

Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

279

2.15

Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

285

EXECUTABLE INSTRUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

291

3.1

Symbol and Abbreviation ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

291

3.2

Executable Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

293

3.3

Limitation of SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

355

4.

PIN ARRANGEMENT AND PACKAGE INFORMATION ........................ .

357

5.

ELECTRICAL CHARACTERISTICS ....................................... .

359

6.

3.

APPLICATION ........................................................ .

366

6.1

How to Confirm Operation Frequency .................................. .

366

6.2

Method of the OM (Decimal Adjust Accumulator) ........................ .

366

6.3

Cautions on the Programming of the Write Only Register and Control Register ..

370

6.4

Cautions on Executing BSR (Branch SubRoutine) Instruction. . . . . . . . . . . . . . . .

370

6.5

Cautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

371

EVALUATION CHIP (HD63L05EO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

373

7.
7.1

Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

373

7.2

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

379

7.3

Pin Functions and Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

380

7.4

The Comparison between the HD63L05 MCU and the HD63L05EO . . . . . . . . . . .

386

7.5

LCD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

387

7.6

Setting the mask-option data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

388

7.7

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

389

~HITACHI
viii

8.

ROM Code Order Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

396

APPENDIX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

397

I.

Design Procedure and Supporting Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

397

SINGLE CHIP MICROCOMPUTER ROM ORDERING PROCEDURE. . . . . . . . . . . . . . . . .

399

HD63L05F1 ORDERING SPECIFICATIONS ..... " . . . . . . . . . . . . . . .. . . .. .. . . . . . . . .

401

HD63L05F MASK OPTION LIST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

402

LCD PIN LOCATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

403

Section 6
Software Application Notes
1.

Page

HOW TO USE APPLICATION NOTES ..................................... .

413

Formats............................................................

413

1.1

1.1.1

Specification Format (Format 1) .................................... .

415

1.1.2

Description Format (Format 2) ..................................... .

421

1.1.3

Flowchart Format (Format 3) ...................................... .

424

1.1.4

Program Listing Format (Format 4) .................................. .

426

How to Execute Programs ............................................. .

428

1.3 Symbols ........................................................... .

430

PROGRAM APPLICATION EXAMPLES ....................................... .

431

Program Application Table .................................................. .

433

MOVING DATA ........................................................... .

434

1.

Filling Constant Values (Fill) ............................................. .

434

2.

Moving Memory Blocks (Move) ........................................... .

439

3.

Moving Strings (Moves) ................................................. .

446

BRANCHING FROM TABLE (CCASE) ........................................ .

452

4.

Branching from Table (CCASE) ........................................... .

452

HANDLING ASCII ........................................................ .

459

5.

Converting ASCII Lowercase into Uppercase (TPR) .......................... .

459

6.

Converting ASCII into 1-Byte Hexadecimal (Nibble) ........................... .

464

7.

Converting 8-Bit Binary Data into ASCII (Cobyte) ............................. .

469

BIT MANIPULATION ...................................................... .

474

8.

Counting Number of Logical "1" Bits in 8-Bit Data (HCNT) ..................... .

474

9.

Shifting 16-Bit Data (SHR) ............................................... .

479

1.2

~HITACHI
ix

COUNTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

484

10.

4-Digit BCD Counter (DECNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

484

COMPARISON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .

489

11.

489

Comparing 16-Bit Binary Data (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ARITHMETIC OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

495

12.

Adding 16-Bit Binary Data (ADD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

495

13.

Subtracting 16-Bit Binary Data (SUB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

501

14.

Multiplying 16-Bit Binary Data (MUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

507

15.

Dividing 16-Bit Binary Data (DIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

513

16.

Adding 8-Digit BCD (ADDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

519

17.

Subtracting 8-Bit BCD (SUBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

525

18.

16-Bit Square Root (SQRT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

531

CONVERTING BCD INTO HEXADECIMALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

537

19.

Converting 2-Byte Hexadecimals into 5-Digit BCD (HEX) . . . . . . . . . . . . . . . . . . . . . .

537

20.

Converting 5-Digit BCD into 2-Byte Hexadecimals (BCD) . . . . . . . . . . . . . . . . . . . . . .

542

SORTING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

549

21.

549

Sorting (SORT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 7
Hardware Application Notes

Page

APPLICATION NOTES GUIDE.. . .. . .... .. .. . ... . .. . . . . . . ... .. . . .. .. . .. . . . . . .

563

1.

HOW TO USE APPLICATION NOTES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

565

Application Example Configuration ............ . . . . . . . . . . . . . . . . . . . . . . . . . .

565

1.2 1st Section (Hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1

567

1.3 2nd Section (Software) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

571

1.4 3rd Section (Program Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

573

1.4.1

Specification Format (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

574

1.4.2

Description Format (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

580

1.4.3

Flowchart Format (Format 3) .......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

582

1.5 4th Section (Subroutine) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

584

1.6 5th Section (Program Listing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

587

1.7 Program Module Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

591

1.8 Symbols............................................................

594

~HITACHI
x

APPLICATION EXAMPLES. . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . .. .. .. . . . . . .. . . .. ..

597

I/O PORT APPLICATIONS
1.

HD61830 (LM200) Graphic Mode. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .

599

2.

Liquid Crystal Module (H2570) Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

623

TIMER APPLICATIONS
3.

Duty Control of Pulse Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

641

4.

Pulse Width Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

655

5.

Input Pulse Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

664

6.

Zero Cross. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

672

7.

Key Matrix (8 x 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

683

8.

Fluorescent Display Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

697

9.

Stepping Motor Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

709

INTERRUPT APPLICATION
10.

With a Commercially Available Keyboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

734

SCI APPLICATIONS
11.

SCI Clock Synchronous (External Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

748

12.

SCI Clock Synchronous (Internal Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

760

13.

Liquid Crystal Driver (HD61100A) Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

772

EXTERNAL EXPANSION APPLICATION
14.

External Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

784

LOW POWER DISSIPATION/FAIL SAFE APPLICATION
15.

Low Power Dissipation Mode and HA1835P Control. . . . . . . . . . . . . . . . . . . . . . . . . .

Section a-Appendix
Technical Q and A (Part I)
a-Bit Single-Chip Microcomputer
HD6305XO, HD6305X1, HD6305X2
HD6305YO, HD6305Y1, HD6305Y2
Parallel Port
I
(1) Outputting Data from Ports after a Reset
(2) Serial I/O Pin Status
(3) Using Port C when Serial I/O is Used
Serial Port
I
(1) Designating Input or Output Operation of Serial
I/O Clock Pin
(2) SCI Prescaler Initialize Timing and Clock Output
Timing

Q & A No.

816

Page

QA63S-001B
QA63S-002B
QA63S-003B

841
842
843

QA63S-004B

844

QA63S-00SB

845

~HITACHI
xi

(3) SSR7 (SCI Interrupt Request Bit) Set Timing
(4) Using SDR (SCI Data Register) when Serial I/O ~s
not Used
(5) Accessing SDR (SCI Data Register)
(6) Clearing SSR (SCI Interrupt Request Bit)
(7) Transmitting and Receiving Data Simultaneously
through Serial I/O
(8) Notes on Receiving Data through SCI in External
Clock Mode
(9) SCI Operation in External Clock Mode
(10) Initializing the Transfer Clock Generator
Prescaler
Timer/Counter ~
(1) Timer Count-down Timing when External Clock is
Input
(2) Timer 2 Interrupt Cycles
(3) Reading/Writing Data from/into the TDR during
Timer Operation
(4) Timer Clock Input Source

Q&ANo.

Page

QA635-021B
QA635-024B

846
847

QA635-025B
QA635-026B
QA635-030A

848
849
850

QA635-03lA

851

QA635-032A
QA635-033A

852
853

QA635-006B

854

QA635-022B
QA635-034A

855
856

QA635-035A

857

QA635-007B
QA635-008B
QA635-009B
QA635-0l0B
QA635-0llB

858
859
860
861
862

QA635-012B

863

QA635-013B
QA635-036A

864
865

QA635-037A

866

QA635-0l4B

867

QA635-015B
QA635-0l6B

868
869

QA635-0l7B
QA635-0l8B

870
871

QA63S-0l9B
QA63S-020B
QA635-027B
QA635-028B
QA63S-029B
QA635-038A
QA63S-039A

872
873
874
875
876
877
878

BUS Interface
Interrupt
I
(1) Schmitt Trigger Circuit of Interrupt Pin
(2) Servicing Timer Interrupt while Masked
(3) Servicing INT External Interrupt while Masked
(4) Servicing INT2 External Interrupt while Masked
(5) Servicing an Interrupt after a Reset (CCR I bit
initializing)
(6) Servicing External Interrupt after Returning
from Standby Mode
(7) Servicing Multiple Interrupts
(8) Time from Interrupt Occurrence to Interrupt
Servicing Routine Execution
(9) Servicing SCI (Serial I/O) Interrupt while
Masked
A/D Converter

I

Oscillator
(1) Timing of External Clock Input to the Oscillator
and E Clock Timing
Reset
I
(1) Port Status at a Reset
(2) Bus Status at a Reset
Low Power Consumption
I
(1) Bus Status in Low-Power-Consumption Modes
(2) Executing an Instruction when Entering Standby
Mode
(3) Standby Mode Timing
(4) Returning from Standby Mode
(5 ) Entering Low-Power-Consumption Modes
(6) Entering Wait Mode
(7) Entering Stop Mode
(8) Returning Time from Stop Mode
(9) Current Consumption in Low-Power-Consumption
Mode

xii

~HITACHI

Q & A No.

Page

QA635-040A
QA635-023B

879
880

QA635-041B

881

EPROM-on-chip
Software
(1) Accessing Not Used Areas on Memory Map
(2) Using Bit Manipulating Instruction for Output
Ports
Eva1uation__K~i~t__~
Emulator
SD
Data Buffer
(1) Statuses of Address Bus, Data Bus and Control
Line when the Internal Address Space is Accessed
Others

Section 8-Appendix
Technical Q and A (Part II)
8-Bit Single-Chip Microcomputer

HD6305UO,HD6305VO

Q & A No.

Parallel Port
1) Outputting Data from Ports after a Reset
(2) Serial I/O Pin Status
(3) Using Port D when Serial I/O is Used

c==(1)Serial
Por~
Designating Input

or Output Operation of Serial

QA635-301A
QA635-302A
QA63S-303A

889
890
891

QA635-304A

892

QA635-30SA

893

QA635-306A
QA635-307A
QA635-308A
QA635-309A

895
896
897

QA635-310A

898

QA635-311A
QA635-312A

900

QA635-313A

901

QA635-314A

902

QA635-315A

903

QA635-316A
QA63S-317A

905

I/o Clock Pin
(2) Using SDR (SCI Data Register) when Serial I/O is
not Used
(3) SSR7 (SCI Interrupt Request Bit) Set Timing
(4) Clearing SSR (SCI Interrupt Request Bit)
(5) Accessing SDR (SCI Data Register)
(6) Transmitting and Receiving Data Simultaneously
through Serial I/O
(7) Notes on Receiving Data through SCI in External
Clock Mode
(8) SCI Operation in External Clock Mode
(9) Initializing the Transfer Clock Generator
Prescaler
CiO) SCI Prescaler Initialize Timing and Clock Output
Timing
LTimer/Counter
(1) Reading/Writing Data from/into the TDR during
Timer Operation
(2) Timer Count-down Timing when External Clock is
Inpu t
(3} Timer Clock Input Source
(4) Timer 2 Interrupt Cycles

Page

894

899

904

~HITACHI
xiii
-

-

..-

----------~--.-----.-~-~--.--

Q & A. No.

Page

BUS Interface
Interrupt
(1) Time from Interrupt Occurrence to Interrupt
Servicing Routine Execution
(2) Schmitt Trigger Circuit of Interrupt Pin
(3) Servicing an Interrupt after a Reset (CCR I bit

QA635-318A

906

QA635-319A
QA635-320A

907
908

QA635-32lA
QA635-322A
QA635-323A

909
910
911

QA635-324A
QA635-325A

912
913

QA635-326A

914

QA635-327A

915

QA635-328A

916

QA635-329A
QA635-330A
QA635-331A
QA635-332A
QA635-333A
QA635-334A
QA635-335A

917
918
919
920
921
922
923

QA635-336A

924

QA635-337A

925

QA635-338A

926

initia1izi~

(4) Servicing INT External Interrupt while Masked
(5) Servicing INT2 External Interrupt while Masked
(6) Servicing SCI (Serial I/O) Interrupt while
Masked
(7) Servicing Timer Interrupt while Masked
(8) Servicing External Interrupt after Returning
from Standby Mode
(9) Servicing Multiple Interrupts
A/D Converter
Osc i lla tor
(1) Timing of External Clock Input to the Oscillator
and E Clock Timing
Reset
Port Status at a Reset

(1)

Low Power Consumption
(1) Entering Low-Power-Consumption Modes
(2) Entering Wait Mode
(3) Entering Stop Mode
(4) Returning Time from Stop Mode
(5) Standby Mode Timing
(6) Returning from Standby Mode
(7) Executing an Instruction when Entering Standby
Mode
(8) Current Consumption in Low-Power-Consumption
Mode
EPROM-on-chip
Software
I
(1) Using Bit Manipulating Instruction for Output
Ports
(2) Accessing Not Used Areas on Memory Map
Evaluation K i t ]

I

Emulator

,

SD

C

Data Buffer
Others

xiv

~HITACHI

Section 9
HD6305UO, HD6305VO, HD63705VO User's Manual
1.

Page

SYSTEM CONFIGURATION ............................................. .

937

1.1

System Configuration ............................................ .

937

1.1.1

External View .................................................. .

937

1.1.2

System Specification Outline ...................................... .

938

Operation ..................................................... .

942

1.2
1.2.1

Dialing Procedure ............................................... .

943

1.2.2

Storing Telephone Numbers ....................................... .

947

1.2.3

Displaying Information on LCD ..................................... .

952

1.2.4

Defining Information to be Displayed on LCD ......................... .

954

2.

HARDWARE DESCRIPTION ............................................ .

956

2.1

Transmitting and Receiving Control Circuit ........................... .

957

2.2

Control Circuit for Storing and Retrieving Telephone Number in External
RAM ......................................................... .

969

2.3

Driving the Liquid Crystal Display Module (H2572) ..................... .

973

2.4

8 x 8 Key Matrix ................................................ .

977

SOFTWARE DESCRIPTION ............................................. .

982

3.1

Transition Diagram .............................................. .

982

3.2

Program Module Configuration .................................... .

984

3.

3.3

"SOFTWARE DESCRIPTION" Format .............................. .

986

3.4

Program Module Description ...................................... .

988

3.5

RAM Table ..................................................... .

1068

3.6

Flag Table ..................................................... .

1070

3.7

Subroutine Table ................................................ .

1073

3.8

RAM Memory Map for Storing Telephone Numbers .................... .

1077

3.9

Ports Labels Table ............................................... .

1078

PROGRAM LISTINGS .................................................. .

1079

4.1

Program Listing ................................................. .

1079

4.2

Symbol Table Listing ............................................. .

1149

4.3

4.

5.

Cross Reference Table Listing ..................................... .

1151

CIRCUIT DIAGRAMS .................................................. .

1164

Circuit Diagrams ................................................ .

1164

5.1
5.2

Pin Location of the HD6305YO ..................................... .

1166

5.3

Pin Functions .................................................. .

1167

APPENDIX I. HD61826 Data Sheet ........................................... .

1170

APPENDIX II. HA16808NT Data Sheet ........................................ .

1178

APPENDIX III. Instruction Set of the HD6305 Family ............................. .

1191

~HITACHI
xv

HD630S/HD63LOS SERIES HANDBOOK

Section One

Ouick Reference
Guide
..........

~HITACHI

~HITACHI
2

Ouick
Reference
.........
Guide

~HITACHI
3

QUICK REFERENCE

GUIDE--------------------------------

• CMOS 8·BIT SINGLE·CHIP MICROCOMPUTER HD6305 SERIES
Type No.

Clock Frequency (MHz)
LSI

Characteristics

HD6305UO
HD63A05UO
HD63B05UO

HD6305VO
HD63A05VO
HD63B05VO

HD6305XO
HD63A05XO
HD63B05XO

HD6305Xl
HD63A05Xl
HD63B05Xl

1.0 (HD6305UO)
1.5 (HD63A05UO)
2.0 (HD63B05UOI

1.0 (HD6305VO)
1.5 (HD63A05VO)
2.0 (HD63B05VO)

1.0 (HD6305XOI
1.5 (HD63A05XO)
2.0 (HD63B05XO)

1.0 (HD6305Xl)
1.5 (HD63A05X 1)
2.0 (HD63B05Xl)

Supply Voltage (V)

ROM

(k byte)

RAM

(byte)

DP40,FP·54, CP44 DP40 FP·54 CP44
4
2
12B

I/O Port
I/O Port

Input Port
Output Port
External

Interrupt

DP·64S, Fp·64

-

31

2

2

DP·64S, FP·64

4

4

128

12B

31

-

0- +70. 1

0-+70'·

192
31

31

5.0

5.0

0-+70. 1

0-+70

Package t
Memory

5.0

5.0

Operating Temperature (oC)

~

32
55

7

31

16
2

2

Soft

1

1

1

1

Timer

2

2

2

2

Serial

1

1

1

1

-

-

12k bytes

-

Functions
Timer
SCI
External Memory Expansion

-

I

Other Features

HD63705VOC
HD637 A05VOC
HD637BOsYOC

HD63705VOC
HD637A05VOC
HD637B05VOC

-

EPROM on the Package Type

-

-

HD63P05YO
HD63PA05YO
HD63PB05YO

Evaluation Chip

-

-

-

EPROM on Chip Type

~~~~ !_e!!1~_,:,~re Range (-40 - +85° Cl version is Ivallable,

tOP; Plastic DIP. FP; Plastic Flat Package. CP; Plastic Leaded Chip Carrier (J·bend leads)

~HITACHI
4

HD63P05Yl
HD63PA05Yl
HD63PB05Yl

-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Q U I C K REFERENCE GUIDE

HD6305X2
HD63A05X2
HD63B05X2

HD6305YO
HD63A05YO
HD63B05YO

HD6305Yl
HD63A05Yl
HD63B05Yl

HD6305Y2
HD63A05Y2
HD63B05Y2

1.0 (HD6305X2)
1.5 (HD63A05X2)
2.0 (HD63B05X2)

1.0 (HD6305YO)
1.5 (HD63A05YO)
2.0 (HD63B05YO)

1.0 (HD6305Yl)
1.5 (HD63A05Y1 )
2.0 (HD63B05Yll

1.0 (HD6305Y2)
1.5 (HD63A05Y2)
2.0 (HD63B05Y2)

5.0

5.0

DP·64S, FP·64

DP·64S, Fp·64

0.125

5.0

5.0

0-+70. 1

0-+70"

HD63L05Fl

3.0

0-+70. 1

0-+70"

DP·64S, FP·64

DP·64S, FP·64

-20 - +75
DP·64S, FP·80

-

8

a

-

4

128

256

256

256

96

24
7

31

55

-

~
~

31

~
~

24
31

7

-

16

20

-

20

I

-

I

(19)

2

2

2

2

1

1

1

1

1

2

2

2

2

1

1

1

1

1

• a·bit )( 1 (with 7·bit prescaler)

1

oa·bit x 1 (with
7·bit prescaler)

o 15·bit x 1 (combined with SCI)

-

Synchronous

J

I

16k bytes

I

-

a k bytes

I

-

16k bytes

-S·bit AID converte
-LCD driver
(6 x 7 segment)
• Low power dissipation modes
(Standby and halt)

• Low power dissipation modes

(Wait, stop and standby)

-

-

-

-

-

-

HD63P05YO
HD63PA05YO
HD63PB05YO

HD63P05Yl
HD63PA05Yl
HD63PB05Yl

-

-

-

-

HD63L05E

-

-

~HITACHI
5

~HITACHI
6

HD630S/HD63LOS SERIES HANDBOOK

Section 1\vo

• Addressing Modes
• CPU Architecture
• Instruction Set

~HITACHI
7

~HITACHI
8

• Addressing Modes
• CPU Architecture
• Instruction Set

•

HITACHI
9

. 10

~HITACHI

Section 2
Addressing Modes, CPU Architecture,
and Instruction Set
Table of Contents
Page

1.1

Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13

1.2

CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18

1.3

Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

1.4

Bit Manipulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

1.5

Symbols and Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

1.6

Executable Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30

1.7

BILlBIH Instruction Precaution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

95

NOTE
This section 2 applies only to HD6305, HD63P05, and HD63705 devices. The addressing
modes, CPU architecture and instruction set for HD63L05 can be found in section 5.

~HITACHI
11

~HITACHI
12

1.1

Addressing Modes
Ten different addressing modes are available.
(1)

Immediate
Refer to Fig. 1-2.

The immediate addressing mode provides

access to a constant which does not vary during execution of the
program.
This access requires an instruction length of 2 bytes.

The

effective address (EA) is PC and the operand is fetched from the
byte that follows the operation code.
(2)

Direct
Refer to Fig. 1-3.

In the direct addressing mode, the

address of the operand is contained in the 2nd byte of the
instruction.

The user can gain direct access to memory up to the

lower 255th address.

All RAM and I/O registers are on page 0 of

address space so that the direct addressing mode may be utilized.
(3)

Extended
Refer to Fig. 1-4.

The extended addressing is used for

referencing to all addresses of memory.

The EA is the contents of

the 2 bytes that follow the operation code.

An extended address-

ing instruction requires a length of 3 bytes.
(4)

Relative
Refer to Fig. 1-5.

The relative addressing mode is used

with branch instructions only.

When a branch occurs, the program

counter is loaded with the contents of the byte following the
operation code.

EA

=

(PC) + 2 + Rel., where Rel. indicates a

signed 8-bit data following the operation code.
occurs, Rel.

=

O.

If no branch

When a branch occurs, the program jumps to any

byte in the range +129 to -127.

A branch instruction requires a

length of 2 bytes.
(5)

Indexed (No Offset)
Refer to Fig. 1-6.

The indexed addressing mode allows

access up to the lower 255th address of memory.
instruction requires a length of one byte.

In this mode, an

The EA is the concents

of the index register.

~HITACHI
13

(6)

Indexed (8-bit Offset)
Refer to Fig. 1-7.

The EA is the contents of the byte

following the operation code, plus the contents of the index
register.
memory.

This mode allows access up to the lower 51lth address of
Each instruction when used in the index addressing mode

(8-bit offset) requires a length of 2 bytes.
(7)

Indexed (16-bit Offset)
Refer to Fig. 1-8.

The contents of the 2 bytes following

the operation code are added to content of the index register to
compute the value of EA.
be accessed.

In this mode, the complete memory can

When used in the indexed addressing mode (16-bit

offset), an instruction must be 3 bytes long.
(8)

Bit Set/Clear
Refer to Fig. 1-9.

This addressing mode is applied to the

BSET and BCLR instructions that can set or clear any bit on page
O.

The lower 3 bits of the operation code specify the bit to be

set or cleared.

The byte that follows the operation code indicates

an address within page O.
(9)

Bit Test and Branch
Refer to Fig. 1-10.

This addressing mode is applied to the

BRSET and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode.

The byte

to be tested is addressed depending on the contents of the byte
following the operation code.

Individual bits within the byte to

be tested are specified by the lower 3 bits of the operation code.
The 3rd byte represents a relative value which will be added to
the program counter when a branch condition is established.
Each of these instructions should be 3 byte.s long.

The value of

the test bit is written in the carry bit of the condition code
register.
(10)

Implied
Refer to Fig. 1-11.

This mode involves no EA. All informa-

tion needed for execution of an instruction is contained in the
operation code.

Direct manipulation on the accumulator and index

register is included in the implied addressing mode.

Other

instructions such as SWI and RTI are also used in this mode.
instructions used in the implied addressing mode should have a
length of one byte.
14

~HITACHI

All

i l= i

I

A

I

Memory

I~_---cA~
F8
Index Reg

I
Stack Pomt

PROG LOA: $F8

05BEt:=4A~6=:t------~

05BFI-

Prog Counl

F8

05CO
CCR

Fig. 1-2

Example of Immediate Addressing

EA
004B
./

Add.,

~

c:~[:::~_==---~r---~==_~~:;oo~o~o--~
_____eA~~;';J
20
20

CAT FCB 32 004B ~

Index Heg

I

Stack POint

J

PROG LOA CAT 0520':j}B6t:=~_ _
052E..
4B

Prog Count

052F
CCR

§.

.

:

:
;

Fig. 1-3

I

Example of Direct AddresSing

~
:

PROG LOA CAT

EA
06E5

./

Adde,

--r-

""

'--I-~

oeioo
A

:

~:g!l--~g:-:---hL~
040BI---:;E:;.5__-I~~

~"" ~ ~"If-'__40_~
Fig. 1-4

40
Index Reg

I
Stack Point
Prog Count

040C
CCR

Example of Extended Addressing

~HITACHI
15

EA
Memory

~.

A
Index Reg

I

.
PROG BEQ PROG2 04A7
04AB

Stack Point

27
1B

~
;

I

Fig. 1-5

Example Qf Relative Addressing

EA
OOBB

Memory

".",,, ...

. .~
~.
~~ ~~~-------1========~~A~n~:;:~B~e~
•

Stack Pomt

PROG LOA X OSF4

~6

I

Prog Count

05FS
CCR

~

.

Fig. 1-6

Example of Indexed (No Offset) Addressing

:
TABL FeB
FCB
FCB
FCB

lIBF
$B6
IIDB
lieF

MeJory

BF

00B9
OOBA
OOBB
OOBe

L

DB
Cf

I
:

:
E6
B9

07se

..

.

,

I

A
CF
Index Reg

03
Stack POint

I

I
Pr2;i Count
0750
CCR

I

I

Example of Indexed (8-bit Offset) Addressing

~HITACHI
16

"'"

I

.

§

_I

-r

Add.,

-r--

86

PROG LOA TABl. X 0758

Fig. 1-7

:

EA
OOBe

~.

.
PROG LOA TABl.X 0692

EA
07BO

./

Adder

"""

~l[~A~DB
Index Reg

02
Stack

Int

I

g:;!~~~~:--~~----~

Prog Count

0695
CCR

TABl

~~: ::~ g~~~I-~::1:~F;;6[-:-:-1}_______________.--1

FCB P DB 0780
DB
FCB .CF 07Bll-....::;CF~.....j

Fig. 1-8

Example of Indexed (16-bit Offset) Addressing

EA
0001

Memory

PORT B EOU 1 00011-......;B;;.F__-f"'l
A

0000

Index Reg

I

PROG BClR 6 PORT B OSBF ,:=[10t~________~
0590 I01

Stack POInt

I
Prog Counl

0591
CCR

~

.I

Fig. 1-9

,•

Example of Bit Set/Clear Addressing
EA
0002

Memory

PORT C EQU 2. 00021--""FO'--I L.._ _ _'

I

Index Reg

I
PROG BRClR 2.PORT C. PROG 2

g~~:t::~~,f~;------I-rr--0576.,-....:..10::.......-04 <-r----;"'----.

0594
CCR

C

In this example bit C of the CC
becomes "0".

Fig. 1-10

Example of Bit Test and Branch Addressing

~HITACHI
17

EA
Memory
i

·~.
'~'~.-~

A
E .

In
Stac

x
E5
In1

Prog Count

0588
OC"

~...

··

Fig. 1-11

1.2

Example of Implied Addressing

CPU Registers
This CPU contains five registers available to the programmer.
They are shown in Fig. 1-12.

0
I Accumulator
0IIndex
RegIster
0IProgram
Counter
0

7

I
7
I

A
X

13
PC
I
6 5
13
1010101010101, 111

IS~ck

SP

Pointer

Condition
IHIIINlzICICod!t

~~glster
ig~~~

Zero
Negative
Interrupt
Mask
Half
Carry

Fig. 1-12

(1)

Programming Model

Accumulator (A)
The accumulator is an 8-bit general purpose register which
holds operands and results of the arithmetic operations or data
manipulations.

$
18

HITACHI

(2)

Index Register (X)
The index register is an 8-bit register used for the indexed
addressing mode.

It contains an 8-bit value which is added to an

offset to create an effective address.
The index register can also be used for data manipulations
with read-modify-write instructions.
When not performing addressing operations, the register can
be used as a temporary storage area.
(3)

Program Counter (PC)
The program counter is a l4-bit register which contains the
address of the next instruction to be executed.

(4)

Stack Pointer (SP)
The stack pointer is a l4-bit register containing the address
of the next free location of the stack.
pointer is set to location $OOFF.

Initially, the stack

It is decremented as a data is

pushed on to the stack and incremented as data is then pulled out
of the stack.
to 00000011.

The B high-order bits of the stack pointer are fixed
During an MCU reset or a reset stack pointer (RSP)

instruction, the pointer is set to location $OOFF.

Subroutines and

interrupts may be nested down to $00C1, which allows programmers to
use up to 31 levels of subroutine calls and 12 levels of interrupt
responses.
(5)

Condition Code Register (CCR)
The condition code register is a 5-bit register indicating the
results of the instruction just executed.

These bits can be

individually tested by conditional branch instructions.
is described in the following paragraphs.
(a)

Each bit

Half Carry (H)
When set, this bit indicates that a carry occurred between
bit 3 and 4 during an arithmetic operation (ADD, ADC).

(b)

Interrupt (I)
Setting this bit masks all interrupts except for software
ones.

If an interrupt occurs while this bit is set, the interrupt

is latched and is processed as soon as the interrupt bit (I) is
cleared.

(More precisely the interrupt enters the servicing

routine after the instruction next to the CLI is executed.)

~HITACHI
19
------- - - - - -

------------------------ ----

(c)

Negative (N)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation is negative.

(Bit 7

in the result is a logical "1".)
(d)

Zero (Z)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation is zero.

(e)

Carry/Borrow (C)
When set, this bit indicates that a carry or borrow occurred
during the last arithmetic operation.

This bit is also affected by

bit test and branch instructions, shifts and rotates.

1.3

Instruction Set
The HD630SUO, HD630SVO, and HD6370SVO MCU provide object codes
upward compatible with the HD680S family.

They are designed to save

execution time of key instructions in order to improve through put.
3 additional instructions; DAA, WAIT, STOP; are available.
The HD630SUO, and HD630SVO, HD6370SVO MCU have 62 basic instructions.

They can be classified into five categories: register/memory,

read-modify-write, branch, bit manipulation, and control.
of each instruction are shown in the following tables.

The details

All the

instructions in a given type are presented in individual tables.
(1)

Register/Memory Instruction
Most of these instructions use two operands.
either the accumulator or the index register.

One operand is

The other is obtain-

ed from memory by using one of the addressing modes.

The un-

conditional jump,JMP) and the jump to subroutine (JSR) instructions have no register operand.
(2)

Refer to Table 1-1.

Read-Modify-Write Instructions
These instructions read a memory location or a register,
modify or test its contents, and write the modified value back to
memory or to the register.

The test for zero (TST) instruction is

an exception to the read-modify-write instructions since it does
not write data.

Refer to Table 1-2.

~HITACHI
20

(3)

Branch Instructions
The branch instruction cause a branch from the program when
a certain condition is met.

(4)

Refer to Table 1-3.

Bit Manipulation Instructions
These instructions are used on any bit in the lower 255 bytes
of the memory.

Two groups are available, one either sets or

clears and the other performs the bit and test branch operations.
Refer to Table 1-4.
(5)

Control Instructions
These instructions control the MCU operation during program
execution. Refer to Table 1-5.

(6)

Alphabetical Listing
Table 1-6 lists the complete instruction set in alphabetical
order.

(7)

Operation Code Map
Table 1-7 is an operation code map for the instructions
used on the MCU.

~HITACHI
21

Table 1-1

Register/Memory Instructions
Addreaing Modo.

OporMion.

Mnemonic

Indexed

Indexed

Immediate

Extended (No Offse.) (8-Bl.

Direct

OP #

-

Load A from Memory

LOA

A6 2

2 B6 2

3 C6 3

4 F6

1

Load X from Memory

LOX

AE 2

2 BE 2

3 CE 3

4

FE

1

3 EE 2

Store A in Memory

STA

-

B7 2

3 C7 3

4 F7

1

4 E7 2

---

OP #

-

OP #

-

-

OP •

OP #

3 E6 2

Booleanl
Arithmetic
Operation

Indexed

0tIsetI

-

(16-8it0lls0tJ
OP #

-

4 06 3

5

-

H

4 OE 3

5

M-X

4 07 3

5

A-·M

STX

2

3 CF 3

Add Memory to A

AOO

AB 2

2 BB 2

3 CB 3

'oA

AOC

A9 2

2 B9 2

3 C9 3

Subtract Memory

SUB

AO 2

2

eo

2

3 CO 3

-,.....-

--

--- r-- e-

-,- -r- - - - _ .
4 00 3

5

A-M .A

A with Borrow

SBC

A2 2

2 B2 2

3 C2 3

4 F2

1

3 E2 2

4 02 3

5

A-M-C .A

AND Memory to A

ANO

A4 2

2 B4 2

3 C4 3

3 E4 2

4 04 3

5

A- M·.A

OR Memory with A

ORA

4 F4 1
3'"4 r-FA'l-

5

A+M'A

Add Memory and Carry

4

1

4 EF

2

4 OF 3

5

X-·M

1

3 EB 2

4 OB 3

5

A+M ·A

4 F9

1

3 E9 2

4 09 3

5

A+M+C·.A

4 FO

1

3 EO 2

Subtract Memory from

t;.A 2-~- faA 23 rcA

FF

4 FB

--I"-

--I- e- r-- r- I- e--

l rEA '"2 r-4" OA

---r-------.

3

--

EOR

A8 2

2 B8 2

3 C8 3

4 F8

1

3 E8 2

4 08 3

5

A+M .A

•
•
•
•
•
•
•
•
•

CMP

Al- 2

2 BI

3 CI

3

4 FI

1

3 EI

4 01

3

5

A-M

CPX

A3 2

2 B3 2

3 C3 3

4 F3

1

3 E3 2

4 03 3

5

X-M

2 B5 2

A,M

Arithmetic Compare A
with Memory

2

2

Arithmetic Compare X
with Memory
Bit

res. Memory with

A (logical

Comp.r.~

BIT

A5 2

Jump Unconditional

JMP

-

Jump to Subroutine

JSR

Symbols:

-

op· Cpsrilion

- -

-

-

3 C5 3

4

F5

1

3 E5 2

4 05 3

5

BC 2

2 CC 3

3 FC

1

2 EC 2

3 OC 3

4

BO 2

5 CO 3

6 FO 1

5 ED 2

5 DO 3

6

N

Z

C

• 1\ •
• "" 1\ •
• 1\ " •
• " 1\ •
" • 1\ 1\ 1\
"• •• -"1\ e--1\1\ -1\
_.
"

...--.-

Exclusive OR Memory
with A

I

•
•
•
•

M··A

Store X in Memory

8F

Condition
Codo

•
•--,....."1\ ---1\ -"•
1\

•

I\,

1\

•

~

•" •
"
• " 1\ 1\
• 1\ 1\
•
•
• "• "
• •
• • • •
1\

It • Number of by'.'
- • Number of cvcl••

Table 1-2

Read/Modify/Wri te Instructions
Addrelling Modes

Operations

Mnemonic

Indexed
ImpliedlAI Implied(XI

-

-

OP

a

-

INC

4C

1

2 5C 1

2 3C 2

5 7C

OP #

OP #

1

Decrement

DEC

4A

1

2 5A 1

2 3A 2

5 7A I

Clear

CLR

4F

1

2 5F

2 3F

5

Complemenl

COM

43

1

2 53 1

1

2

2 33 2

Indexed

(No Offsetl 18-Bl' Offsetl

Increment

OP

a

Direct

7F

1

5 73 1

-

a

-

5 6C 2

6

OP

Condition

H

A+l ".. A or X+l .X or M+l ·.M

--

5 6A 2 ,6

A-l-..A or X-l-..X or M-t -·M

5

2

6

00 .... A or 00 .... X or 00 .. M

5 63 2

6

A ·.A or'l( -.X

6F

or M-M

DO-A .A or DO-X ··X

Negate

(2', Complemenll

NEG

40 1

2 50 1

2 30 2

5 70 1

5 60 2

6

Rotate Left Thru Carry

ROL

49 1

2 59 1

2 39 2

5 79

1

5 69 2

6

ROllI. RighI Thru Carry

ROR

46 1

2 56 1

2 36 2

5 76 1

5 66 2

6

Logicll Shift Left

LSL

48

1

2 5B 1

2 38 2

5 78 1

5 68 2

6

Logical Shift RighI

LSR

44 1

2 54 1

2 34 2

5 74 1

5 64 2

6

or DO-M .M

I II Ibp
Lb-t I Ilori-II
LEHb.
c
1 H3 ..: I [\]
b.

D-i 1~,,:xH

b.

..

cr

..

47

1

2 57 1

2 37 2

5 77

1

5 67 2

8

Arilh_ Shift Left

ASl

48

1

2 58 1

2 3B 2

5 78

1

5 68 2

6

Equlilo LSL

TST

40 1

2 50 1

2 30 2

4 70 1

4 60 2

5

A-DO or X-DO or M-DO

~HITACHI

• •

c

0-; 1 H'~~MI I KJ • • 0
b
:1. H+·:MI 1 KJ • • "

Tilt for Negative

22

N

Z

C

• " 1\ •
• "0 "1 •
•
•
• 1\ " I
• • """
• • 1\ " 1\
1\

ASR

or Zero

I

•
•
•
•

"
..
1 1 1--" • •
M

C

Arilhmlttic Shift RighI

SVmbols: Op. Cpsralion
It - • Numbor of byt..
- • Numbor of cycles

Code

Boolean/Arithmetic Operation

C

• •
• •

1\

1\

"

1\

1\

"

"

1\

"""
1\

"•

Table 1-3

Branch Instruction

Addressing Modes

Mnemonic

Operations

Relative

OP
Branch Always
Branch Never
Branch IF Higher
Branch IF Lower or Same

._-

Branch IF Carry Clear

-

:1*

Branch IF Carry Set

2

3

None

BRN

21

2

3

None

t---

---

Branch IF Half Carry Set
IF Plus
_._Branch
_--_._-_._,._-..

Branch IF Minus

----,..

1---.

.. .

--t---._-

Branch IF Half Carry Clear

_---

Branch IF Interrupt Mask
Bit is Clear

-------------Branch IF Interrupt Mask

Bit is Set

._---------

f-:-:--------.

c-------

. f----------

----"

BMS

20

2

3

1=1

BIL

2E

2

3

INT=1
3
5-- 1------_._----_.

- - f---- ' - - - -

Branch IF Interrupt Line
is High

BIH

2F

2

Branch to Subroutine

BSR

AD

2

Z

C

•
•
•
•

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•

--

--

--

----

Branch IF Interrupt Line

is Low

N

•
•
•
•
•
• •
• •
• •
• •
• ._-• ---•
f-• • -•
• • • • r·····•
• -• 1---• • •
----

f--::-

f-------

Branch IF Not Equal

I

• •
•
•
BHI
22
2
3
C+Z=O
• •
BLS
23
2
3
C+Z=1
• •
24
BCC
2
3
C=O
•
•
(BHS)
24
2
C=O
3
•
•
-25 -2- 3 C=1
BCS
•
•
(BLO)
25
2
C=1
3
• •
'26. 2 3 Z=O
BNE
•
•
BEQ
27
2
3
Z=1
--_
_
•
•
BHCC-··
28
2 -3 H=O
•
•
BHCS
29
2
H=1
3
•
•
-----_.
3- N=O
BPL
2A
2
• •
3- N=1
BMI
2B
2
•
1----------_._----- - • 1--BMC
2C
2
1=0
3
• •
20

. - f - - - - - - - - f----

Branch IF Equal
.

H

BRA

-------~--~

(Branch IF Lower)

Branch Test

t---..- - - - I - - - .

(Branch IF Higher or Same)

----

Condition Code

1----.----

INT=O

f-----.

1--- - -

• -• 1---• 1----• -•
• • • • •

Symbols: op = Operation
# =: Number of bytes
- = Number of cycles

Table 1-4
Operations
Branch IF Bit n is set
Branch IF Bit n is clear
Set Bit n
Clear Bit n

Bit Manipulation Instructions

Addressing Modes
Booleanl
Branch
Bit Test and Branch Arithmetic
Bit Set/Clear
Test
Operation
OP
:. OP
~
BRSET n(n -0··· 7)
2·n
3 5
Mn=l
BRCLR n(n-0····7)
- 01 +2·n 3 5
Mn=O
BSET n(n-0···7)
10+2·n 2 5
- - 1-Mn
BCLR n(n =0··· 7)
11 +2·n 2 5
O-Mn
Mnemonic

-

-

-

-

-

Symbols: Op = Operation
# = Number of bytes
- = Number of cycles

-

-

Condition Code
H

I

N

Z

C

• • • •
• • • •
• • • • •
1\

/\

• • • • •

~HITACHI
23

Table 1-5
Mnemonic

Operations

#

-

1
1

SEC

9F
99

2
2

1

1

ClC
SEI

9B

1

1

9B

1

CLI
SWI

9A

1

2
2

83

1

10

RTS

81

1

5

RTI

80

1

8

TAX

Transfer X to A
Set Carry Bit

TXA

Clear Carry Bit
Clear Interrupt Mask Bit
Software Interrupt
Return from Subroutine
Return from Interrupt

Addressing Modes
Implied
OP
97

Transfer A to X

Set Interrupt Mask Bit

Control Instructions
Condition Code

Boolean Operation
A----X
X----A
1----C

O---+C
1----1
0----1

Reset Stack Pointer

RSP

9C

1

2

$FF----SP

No-Operation

NOP

90

1

1

Advance Prog. Cntr. Only

Decimal Adjust A

OAA

80

1

2

Converts binary add of BCD charcters into
BeD format

Stop
Wait

STOP

8E
8F

1
1

4
4

0-.1
0-'1

WAIT

Symbol.: Op ~ OperatIon
# a Number of bytes
- • Number of cycl••

H

I

N

Z C

•
•
•
•
•

•
•
•
•1

•
•
•
•
•
•
•

• •
• •1
•
• 0
• •
• •

•
•
•
?
•
•
•
•
•

0
1

•
• • •
? ? ?
• • •
• • •
•0
• •
0 •
•
A

Condition Code
Bit

Mnemonic

Indexed
Direct

ADC

X

X

X

ADD

X

X

X

X

X

X

Indexed
X

X

1\

X

X-

X

A

X

X

X

X

X

X

ASR

X

X

X

X

X

BCS

X

BEQ

X

!lHCC
BHCS

X

BHI

X
X

BlH
Bil

X
X
X

X

X

X

IBLO)

X

BlS

X

BMC
BMI- ,

X

BMS

X

BNE

X

BPl

X

BRA

X

X

Condition Code Symbols:
H
Half Carry IFrom Bit 3)
I
Interrupt M.k
Negative (Sign Bil)
N

Zero

•
•
•
•
•
•
•
•
•
•
•

X

IBHS)

H

•

X

BClR

24

Test.
Branch

X

X

Z

Set!
Clear

Indexed
(lB-Bit)

ASl
BCC

Bit

18-Bit)

Extended Relative INo Offset)

Immediate

BIT

.

Instruction Set (in Alphabetical Order)
Addressing Mode.

AND

"

• Are BCD characters of upper byte 10 or more? IThey are not clearad if set in advance.!

Table 1-6

Implied

'/'

•
•
?
•
•
•
•

X

X

I

N

•
•
•
•
•
• •
• •
••
••
••
• •
••
• •
• •
• •
•
• •
••

•
•
•
•
••
• •
• •
••
• •
• •

Z

C

1\

A

1\

1\

1\

1\

A

1\

f,

•

1\

1\

A

A

1\

A

•
•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
A

•

•
•
•
•
•
•
•
•
•
•
•

•
•
•
•

•
•
• • •

(to be continued)
C
A

•

?

CarrylBorrow
Test and Set if True, Cleaned Otherwise
Not Affllcllld
load CC Register From Stack

~HITACHI

Addressing Mode.

Condition Code
Bit

Indexed

Mnemonic

Implied

Direct

Immediate

Extended Relative (No Offset)

Indexed

Indexed

Set

Test &

(8-Bit)

(16-Bit)

Clear

Branch

x

BRN

x
x

BRCLR
BRSET

x

BSET

x

BSR

x
x
x

CLC
CLI
CLR

x
x
x
x

x

CMP

x

COM

x

CPX

x
x

DAA
DEC

x
x
x
x
x
x
x
x
x
x

x

EOR

x

INC
JMP

;

JSR

x
x

LOA
LOX
LSL
LSR
NEG
NOP

x
x
x
x
x

ORA
ROL
ROR
RSP
RTI
RTS

x
x
x
x
x

SEI

x
x
x

I

x

SBC
SEC

x

SUB
TAX
TST
TXA
WAIT

x

x
x
x
x
x

x

x
x
x
x

x
x
x
x

x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x

x
x
x

x
x
x

x
x

x
x
x
x
x

x

x

x

x

x

x

x

x

x

x

x

x
x

x
x

x
x

x
x

x
x

x

x

x

STX
SWI

x

x
x

STA
STOP

Bit

x
x
x
x
x

Condition Code Symbols:
H
Half Carry (From Bit 3)
Interrupt Mask
N
Negative (Sign Bit)
Z
Zero

x

C
/\

•?

H

I

N

•
•
•
•
•
•
•

•
•
•
•
•

•
•
•
•

•
•
•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
•
•

Z

C

•
•
•
•
• •
• • •
0 • •
0 1

•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
?

•

1\

A
A

"
A

A

"
1\

•
•0
•
•

""
"
"
1

~

A

A

" ••

A

-

"• A• ••
• • •
•
•
"0 " "
1\ " "
• "• "•" •""
• •? •?
?
• • •

1\

A

1\

1\

1\

1\

1\

A

1\

• 1\ A 1\
•1 • • 1
• • •
• 1\ 1\ •
• 0 • 1\• •
• • 1\ •
• • 1\
• 1 • "• "•

• • • •
• • 1\
• • • •
• 0 • •
1\

•
•
•
•

Carry /Borrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

~HITACHI
25

Table 1-7
Bit Manipulation
Test

0

&

Branch

Operation Code Map

Branch

Rei

OIR

A

X

.Xl

0

1

2

3

4

6

BRSETO

BSETO

BRA

5
NEG

1

BRCLRO

BCLRO

BRN

2

BRSETl

BSETl

BHI

-

Register/Memory

Control

Read/Modify/Write

Set!
Clear

.XO
7

IMP

IMP IMM

OIR

EXT

.X2

.Xl

8

C

0

E

.XO
F

-

8

9

RW
RTS·

-

CMP

1

-

SBC

2

-

A

SUB

HIGH

0

3

BRCLRl

BCLRi

BLS

COM

SWI·

-

CPX

3

4

BRSET2

BSET2

BCC

LSR

-

-

AND

4
5

5

BRCLR2

BCLR2

BCS

-

6
7

BRSET3

BSET3

BNE

ROR

BRCLR3

BCLR3

BEQ

ASR

8

BRSET4

BSET4

BHCC

9

BRCLR4

BCLR4

BHCS

A

BRSET5

BPL

BIT

-

LOA

6
STA(+ II 7

LSL/ASL

CLC

STA
EOR

ROL

-

SEC

AOC

9

DEC

-

CLI'
5EI'
RSp·

ORA
ADD

A

B

BRCLR5

BMI

-

BRSET6

BSET6

BMC

INC

0

BRCLR6

BCLR6

BMS

E

BRSET7

BSET7

BIL

F

BRCLR7

BCLR7

BIH

3/5

2/5

2/3

(NOTESI

-

-

TAX·

C

TST(-l)

TST

1/2

1/2

1/5

-

1/"

1/1

8

B

JMP(-l)
J5R(+2)

-

WAIT' TXA·
2/6

-

OAA· NOP B5R·

STOp·

CLR
2/5

-

-

BSET5
BCLR5

TSTI-I)

"

JSR(+l)

LOX

2/2

2/3

STX
3/4 3/5

2/4

C

JSRH2) 0
E
STX(+II F
1/3

1. "-" is an undefined operation code.

2. The lowermost numbers in each column represent a byte count and the number of cycles required (byte count/number of cyclesl.
The number of cycles for the mnemonics asterisked (01 is as follows:
ATI
8
TAX
2
ATS
5
ASP
2
SWI
10
TXA
2
DAA
2
BSA
5
STOP
4
ell
2
WAIT
4
SEI
2
3. The parenthesized numbers must be edded to the cycle count of the particular instruction.

(11)

Additional Instructions
The following new instructions are used on the HD6305,
and HD63705.
DAA

Converts the contents of the accumulator into BCD code.

WAIT

Causes the MCU to enter the wait mode.
Refer to "2.9 Low Power Consumption Mode".

STOP

Causes the MCU to enter the stop mode.
Refer to "2.9'Low Power Consumption Mode".

~HITACHI
26

L

o

W

1.4

Bit Manipulation
The HD6305, HD63705 MCU can use a single instruction (BSET or BCLR)
to set or clear one bit of the RAM or an I/O port.
Every bit of memory or I/O within page 0 ($00

~

$FF) can be

tested by the BRSET or BRCLR instruction depending on the result of
the test, the program can branch to required destinations.

Since

bits in the RAM, or I/O can be manipulated, the user may use a bit
within the RAM as a flag or handle a single I/O bit as an independent

I/O terminal.

Fig. 1-13 shows an example of bit manipulation and the

validity of test instructions.

In the example, the program is con-

figured assuming that bit 0 of port A is connected to a zero cross
detector circuit and bit 1 of the same port to the trigger of a triac.
The p.rogram shown can activate the triac within 10]1s from zerocrossing through the use of only 7 bytes on the ROM.

The internal timer

provides a required time of delay and pulse width modulation of power is
also possible.

SELF 1.

BRCLR 0, PORT A, SELF 1
BSET l, PORT A
BCLR 1, PORT A

Fig. 1-13

Example of Bit Manipulation

~HITACHI
27

1. 5

Symbols and Abbreviations

Shown below are the meanings of symbols and abbreviations.
(1)

Operation

0= contents
-+-

movement direction

.+ =

addition

/\

AND

subtraction
v

=

OR
Exclusive OR

$=

x = NOT
(2)

Register symbols in CPU
ACCA
CCR

accumulator A

condition codes register

IX

index register, 8 bits

PC

program counter, 14 bits

PCH

the six most significant bits of program counter

PCL

the eight least significant bits of program counter

SP
(3)

=

=

=

stack pointer, 6 bits

Memory and addressing codes
M=

stored address

MH

the eight most significant bits of stored address

ML

the eight least significant bits of stored address

M+l

stored address M plus 1

Msp

stored address indicated by stack pointer

Imm

immediate value

Disp

displacement value

= M - (IX)

= displacement value = M DR = displacement value the
DL = displacement value
the
ReI = relative value
IMPLIED = implied addressing

D

(IX)
eight most significant bits
eight least significant bits

RELATIVE = relative addressing
ACCUMULATOR

accumulator addressing

~HITACH.
28

INDEX REG. = index register addressing
IMMEDIATE

immediate addressing

DIRECT = direct addressing
EXTENDED

extended addressing

INDEXED 0 BYTE OFFSET

indexed addressing 0 byte offset

INDEXED 1 BYTE OFFSET

indexed addressing 1 byte offset

INDEXED 2 BYTE OFFSET

indexed addressing 2 byte offset

EA = ' effective address
(4)

Contents of bits 0 through 4 of condition codes register
C .. carry - borrow
bit 0
Z .. zero
bit 1
N

negative

bit 2

I

interrupt mask

bit 3

H = half carry from bit 3 to bit 4
(5)

bit 4

Status of each bit before execution of instruction
An .. bit n of ACCA (n = 7, 6, 5, .... , 0)

(6)

Mn

bit n of M (n = 7, 6, 5, .... , 0)

Xn

bit n of IX (n

6, 5, .... , 0)

Status of each bit on result after execution of instruction
Rn"

(7)

= 7,

bit n of result (n .. 7,6,5, .... , 0)

Symbols on instruction's format
p..

each addressing mode on Immediate, Direct, Extended and
index of 0, land 2 byte offset

Q.. each addressing mode on Direct and index of 0 and 1 byte
offset
A..

accumulator addressing mode

X

index register addressing mode

DR

direct addressing mode

dd..

relative operand (8 bits)

n= bitnofmemory (n=7, 6, 5, .•.• , 0)
(8)

Status of H06305's interrupt pin
INT = status of interrupt pin (high, low)

~HITACHI
29

1.6

Executable Instructions
Arithmetic Operation
ADC
ADC (ADd with Carry)

I

I

II

Format

Condition Codes

II

R: Set if a carry occurs from bit 3;

otherwise reset.
I: Not affected.
N: Set if the most significant bit of
the result is set; reset otherwise.
Z: Set if the result is 0; otherwise
reset.
C: Set i f a carry occurs from the
most significant bit of the result;
otherwise reset.

ADC P

I

ACCA

I

II

Operation

+

(ACCA) + (M) + (C)

Description

IJ

Adds the contents of the carry bit C to the sum of the contents of ACCA and M
and stores the result into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

I
I
I
I

Operand
type

I

IMMEDIATE
DIRECT

ADC
ADC

I
I

EXTENDED

ADC
ADC

I

INDEXED U BYTE
iOFFSET
INDEXED 1 BYTE
OFFSET
INDEXED 2 BYTE
OFFSET

I

I

0

I
I
I

Instruction code
Byte 1

t/Imm
M

A9
B9

Imm
M

M

C9

MH

O,X

F9

I

ADC

:Disp ,X

ADC

:Disp ,X

I

E9
D9

0100
0102
0105
0108
010A
010D

B6
CB
C7
B6
C9
C7

02
0006
0006
01
0005
0005

I
I

ML

D
DR

DL

I

I

I

I
I

II
LDA
ADD
STA
LDA
ADC
STA

VAL2
EXVAL6
EXVAL6
VALl
EXVAL5
EXVAL5

(EXVAL5,EXVAL6)+(VAL1,VAL2)
=(EXVAL5, EXVAL6)
*

*
*
***
*

~HITACHI
30

Byte 3

I
I
I

I
I

Example

I
I

Number
of CPU
cycles

I

I

I

Byte 2

Number
of
bytes
2
2

3

2

3

4

1

3

2

4

3

5

Arithmetic Operation
ADD
ADD (ADD without carry)

I

Format

I

IJ

ACCA

I

II

Operation

~

(ACCA) + (M)

Description

II

H: Set i f a carry occurs from bit 3
otherwise reset.
I: Not affected.
N: Set i f the significant bit of the
result is 1; otherwise reset.
Z: Set i:f the result is 0; otherwise
reset.
C: Set i f a carry occurs from the
most significant bit of the result;
otherwise reset.

ADD P

I

Condition Codes

I

Adds the Mcontents to ACCA contents, and stores the result into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

0
0

I
I

Operand
type

I

IMMEDIATE
DIRECT

ADD
ADD

EXTENDED

ADD

INDEXED u BYTE
OFFSET
INDEXED 1 BYTE
OFFSET
INDEXED Z BYTE
OFFSET

ADD
ADD
ADD

I
I

IIImm
M
oM
0
0

I

Instruction code
Byte 1 iI Byte 2
AB
BB

0

0

FB

0

Disp,X

EB

, Disp,X

DB

I

,,
I
I

Byte 3

Imm
M

O,X

I
I

0

2
2
ML

I

DL

I

0

DH

Number
of CPU
cycles
2

3

3

4

1

3

2

4

3

5

I

I

,,

,I
Example

0
0
0
0

: MH
,
, D

CB

I

I

I

Number
of
bytes

II

0110 B6 10
0112 BB FF
0114 B7 50

LOA
ADD
STA

VAll
WORK
RESULT

(VAL1)+(WORK)=(RESULT)

*
*

~HITACHI
31

Logical Operation
AND
AND (logical AND)

I

Format

I

IJ

ACCA

I

II

Operation

+-

(ACCA)

Description

II

H: Not affected.
I: Not affected.
N: Set i f the most significant bit of
the result is "1"; otherwise reset.
Z: Set i f the result is "0"; otherwise
reset.
C: Not affected.

AND P

I

Condition Codes

1\

(M)

II

Performs logical AND between the ACCA contents and the M contents, and
stores the result into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMMEDIATE

Mnemonic
AND

DIRECT
EXTENDED

AND
AND

INDEXED 0 BYTE
OFFSET
INDEXED .l BYTE
OFFSET
INDEXED 2 BYTE
OFFSET

AND
AND
AND

I
I
I
I

Operand
type

Instruction code

I

Byte 1 iI Byte 2

I

I

I

flImm

I
I

B4
C4

M
'M
,
I
I
O,X
I
I
I
I

F4

Disp,X

I

, Disp,X
I

,

A4

E4
D4

Example

0107
0108
OlOA
OlOB
OlOC

, M
I

:

MH

ML

,I
, D
I

I
I

,
I

,

I
I

DH

DL

F6
A4 OF
F7
5C
20 F2

LDA
AND
STA
INC
BRA

O,X
#$OF
O,X
X
LOOP

2

2

3

3
4

1

3

2

4
5

3

ERASE UPPER 4 BITS

*

(RESTORE)

*
*

Number
of CPU
cycles

2

II

~HITACHI
32

Imm

I
I

I
I

I

I

Byte 3

Number
of
bytes

Shift and Rotation
ASL
ASL (Arithmetic Shift Left)

I

Format

I

II
ASL Q
ASL A
ASL X

I

,

El~1
b7

I

Description

I I I I I I I I~

II

H: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result is "I"; otherwise reset.
Z: Set if the result is "a"; otherwise
reset.
C: Set if the most significant bit is
"I" before shifting; otherwise
reset.

II

Operation

Condition Codes

0

bo

I

Shifts the contents of ACCA, IX or M 1 bit to the left. The bit a is
loaded with "a". The carry bit C is loaded with the bit 7 of ACCA, IX or
M.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

I

Mnemonic

I
I

I

Operand
type

I

ACCUMULATOR

ASL

INDEX REG.
DIRECT

ASL
ASL

INDEXED 0 BYTE
OFFSET
INDEXED 1 BYTE
OFFSET

I

I
I

I
I
I

Instruction code
Byte 1 : Byte 2
I

48

A
X
M

58
38

I

I

ASL

I

ASL

I
I
I

O,X

78

Diso X

68

I

I
I
I

M

I
I
I
I

D

2

1

2

2

5

1

5

2

6

I
I

I

I

I
I

I

010E B6 FF
0110 48
0111 25 2E
0113
0113 AE 64

I

I

I

Example

1

I

,I

Number
of CPU
cycles

I

I
I

I

I

Byte 3

Number
of
bytes

II
CHECK
BITOFF

LDA
ASL
BCS
EQU
LDX

WORK
A
BITON

*

BRANCH FOLLOWING BIT
7-6-5-4-3-2-1-0

*

#100

~HITACHI
33

Shift and Rotation
ASR
ASR (Arithmetic Shift Right)

I

I

II

Format

ASR Q
ASR A
ASR X

I

•

C?I

IIIIII

I-.@]
bo

b7

I

H: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result is "1"; otherwise reset.
Z: Set if the result is "0"; otherwise reset.
C: Set if the most significant bit is
"1" before shifting; otherwise
reset.

II

Operation

II

Condition Codes

Description

I

Shifts the contents of ACCA, IX or M l-bit to the right.
not affected. The bit o is loaded into the carry bit C.

The bit 7 is

I

Addressing Mode and Number of CPU Cycles
I

Addressing
Mode

Mnemonic

ACCUMULATOR
INDEX REG.

ASR
ASR

DIRECT

ASR

INDEXED U BYTE
OFFSET
INDEXED 1 BYTE
OFFSET

ASR

I
I
I

,
I

I
I
I

.,
I
I

I

,

Operand
type

47
57

M

37

O,X

77

Disp,X

67

I

ASR

I

,
I

I

I

··
,
I

M

2

5

D

1

5

2

6

I

I

II
37
25
37
25
37
25

FF
17
FF
1B
FF
46

ASR
BCS
ASR
BCS
ASR
BCS

WORK
OPTO
WORK
OPTl
WORK
OPT2

BRANCH OPTION (KEEPING BIT 7)

~HITACHI
34

2
2

I
I
I

Number
of CPU
cycles

1
1

I

·:

Byte 3

I
I

.
0143
0145
0147
0149
014B
0140

,

Number
of
bytes

I

I

I

Example

Byte 1 :I Byte 2

A
X

I

I

Instruction code

Conditional Branch
BCC
BCC (Branch if Carry Clear)

I

Format

I

II

Condition Codes

BCC dd

I

I

Not affected.

II

Operation
PC

+

II

(pC)+OO02+Rel

Description

i f (C)=O

I

Tests the state of the C bit and causes a branch if C is "0".

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Mnemonic
BCC

Operand
type
Rel

Instruction code
Byte 1 II Byte 2
24

, Rel
,
1
I
I

I
I

I
I

1

I
I

2

3

I

1

I

Number
of CPU
cycles

1

,1

,

Example

1

1
1

I
I

Byte 3

Number
of
bytes

I

,I

I

I

I
I

I

,

I

I
I

,

,,
,
I
I

II

014F B6 20
0151 CB 0600
0154 24 11
0156 5C

*

LOA
ADD
BCC

VAL2
EXVAL6
NORMAL

KETA AGARI

INC

X

KETA AGARI

NASHI

~HITACHI
35

Bit Control
BCLR
BCLR (Bit CLeaR bit n)

I

I

Ij

Format

I

II

Operation
Mn

+

Ir

Not affected.

BCLR n, DR

I

Condition Codes

0

Description

I

Clears the bit n (n

=

° through 7)

The other bits are unaffected.

of M.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

,

Mnemonic:, Operand
type

DIRECT

BCLR

DIRECT

BCLR

DIRECT
DIRECT
DIRECT

BCLR
BCLR
BCLR

DIRECT
DIRECT
DIRECT

BCLR
BCLR
BCLR

I

Example

0157
0159
015B
0150
015F
0161
0163

B6
A4
BA
B7
11
10
1F

03
FO
FF
03
03
03
03

Number
of CPU
cycles

Byte 1 ,: Byte 2

I
I

,

M

2

5

,

M

2

5

M
M
M

2
2
2

5
5
5

2
2
2

5
5
5

O,M

,
1,M
,,
2.M
,,, 3,M
,,
I

, 4,M
,I 5,M
,
I
I

,,

6,M
7,M

CNTRL
#$FO
WORK
CONTRL
O,CNTRL
6,CNTRL
7,CNTRL

11

13
15
17
19
lB
lD
lF

I

,,

,
:
,,
,
I

,
I
I

,,

Byte 3

M

, M
M

,,

,,,

** MAKE CONTROL CODE **
*
*
*

CLEAR BIT 0,6,7 ABSOLUTELY

~HITACHI
36

N\'lmber
of
bytes

I

II
LOA
AND
ORA
STA
BCLR
BCLR
BCLR

"
Instruction
code

Conditional Branch
BCS
BCS (Branch if Carry Set)

I

I

II

Format

Condition Codes
Not affected.

BCS dd

I

I

II

Operation
PC

+

II

(PC)+OOO2+Rel

Description

if (C)=l

I

Tests the C-bit state and causes a branch if C is "1".

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Mnemonic
BCS

Operand
type
ReI

Instruction code
Byte 1 :I Byte 2
25

I
I

Byte 3

Number
of
bytes

ReI

2

Number
of CPU
cycles
3

I
I

,
I

:
I
I
I
I

I
I
I
I
I
I

I

Example

II

0165 B6 10
0167 CB 0600
016A 25 13
016C C7 0600

*

LDA
ADD
BCS

VAll
EXVAL6
ABNML

KETA AGAR!

STA

EXVAL6

KETA AGAR! NASH!

$

,

HITACHI
37

Conditional Branch
BEQ
BEQ (Branch of Equal)

I

Format

I

II

Condition Codes

BEQ dd

I

Not affected.

II

Operation

PC'--(PC)+OOO2+Rel

I

II

i f (Z)=l

]

Description

Tests the Z-bit state and causes a branch if Z is "1",

Addressing Mode and Number of CPU Cycles
I

Addressing
Mode

Mnemonic

I
I

I
I

RELATIVE

BEQ

I
I

Operand
type

Byte 1 : Byte 2

ReI

27

I
I

I

,

,I

I

I

I
I

,

I

I
I

I

I

I

I
I
I

I
I

I

I
I

,
I

I
I

I

,
,,
I

I
I

I

Example

016F
0171
0173
0175

"

B6
27
B1
27

FF
18
50
28

LOA
BEQ
CMP
BEQ

WORK
AAAA
RESULT
BBBB

~HITACHI

Number
of
bytes
2

ReI

I

I
I

I

38

Byte 3

I

I

I

Instruction code

WORK

=

0

WORK

=

RESULT

Number
of CPU
cycles
3

Conditional Branch
BHCC
BHCC (Branch if Half Carry Clear)

I

Format

I

II

Condition Codes

BHCC dd

I

I

Not affected.

II

Operation
PC

~

II

(PC)+OOO2+Rel

Description

i f (H)=O

II

Tests the H-bit state and causes a branch if H is "0".

Addressing Mode and Number of CPU Cycles

,

Addressing
Mode

Mnemonic

RELATIVE

BHCC

I
I
I
I
I
I

Operand
type
ReI

Instruction code
Byte I :I Byte 2
28

I
I

,I
I
I
I
I
I
I

I
I

I

I
I

,

I
I

I

01 ED 28 15
01EF 9F

3

,I

I

01E7 Al 09
01E9 23 02
01 EB AE 60

2

I

,I

Example

ReI

Byte 3

Number
of CPU
cycles

,

1

I

,
,,I
,
.,,
1

Number
of
bytes

II
DAAH6

*

DAALOW

CMP
BLS
LOX

#$9
DAALOW
#$60

BHCC
TXA

DAAL9

$99 ---> INPUT
HIGH NYBLE NEEDS CORRECTION

~HITACHI
39

Conditional Branch
BHCS
BHCS (Branch if Half Carry Set)

I

I Format II

I

II

Operation
PC

+

II

Not affected.

BHCS dd

I

Condition Codes

(PC) + 0002 + .Rel i f (H) = 1

II

Description

Tests the H-bit state and causes a branch if H is "1".

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

RELATIVE

BHCS

Operand
type
ReI

Instruction code
Byte 1 :I Byte 2
29

I
I

ReI

Byte 3

Number
of
bytes
2

I
I
I
I

:
I
I
I
I

I
I
I
I
I
I

I

Example

01FO A1 09
01F2 23 02
01F4 AE 60
01F6 29 16
01F8 A4 OF

"

DAAH7

*

DAALW1

CMP
BLS
LDX

#$9
DAALW1
#$60

BHCS
AND

DAAL6
#$F

$99 --- INPUT
HIGH NYBLE NEEDS CORRECTION

~HITACHI
40

Number
of CPU
cycles
3

Conditional Branch
BHI
BHI (Branch if HIgher)

I

I Format \I
Operation
PC

I

+

II

Not affected.

BHI dd

I

Condition Codes

Ir

(PC)+0002+Rel if (C V Z)=O
i.e. i f (ACCA) > (M)
(unsigned binary numbers)

Description

I

Causes a branch i f both C-bit and Z-bit are "0".
When the BHI instruction is executed immediately after either CMP or SUB
instruction has been executed, a branch occurs if the minuend represented
by the unsigned binary number (i.e. ACCA) is greater than the subtrahend
represented by unsigned binary number (i.e. M).
Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

I
I
I
I

Operand
type

I

RELATIVE

BHI

I
I

ReI

I

ReI

2

Number
of CPU
cycles
3

I
I
0

I
I
I

I

I
I
I

I
I

I
I
I

I
I

I

I

I

I

I

I
I

I

I

II

0177 B6 10
0179 Bl 20
017B 22 16
017D B7 FF

I

Byte 3

Number
of
bytes

I
I
I

I
I

Example

Byte I :I Byte 2
22

I
I

I

Instruction code

*

LDA
CMP
BHI

VAll
VAL2
ZIP25

VALl

>

STA

WORK

VAL 1

-->

VAL2 (IGNORE SIGN BIT)
WORK (LOWER OR SAME)

~HITACHI
4'1

Conditional Branch
BHS
BHS (Branch if Higher or Same)

I

Format

I

II

BHS dd

I

II

Condition Codes
Not affected.

II

Operation

PC + (PC)+OOO2+Rel i f (C)=O

I

Description

I

When the BHS instruction is executed after comparing or subtracting
unsigned binary, if causes a branch i f the register contents are greater
than or equal to the M contents.

Addressing Mode and Number of CPU Cycles
I

Addressing
Mode

Mnemonic

RELATIVE

I
I
I
I
I
I

BHS

Operand
type

Instruction code
Byte 1 :I Byte 2
24

Rei

I
I
I

I
I

:

I
I

I

I

I

I
I

I

2

I

I

I

I

I

I

I
I

I

II

0100 B6 10
0102 Bl 20
0104 24 16

*

LDA
CMP
BHS

VAll
VAL2
ZlP26

VAll

>=

STA

WORK

VAL 1

--->

~HITACHI
42

Rei

I
I

I
I

0106 B7 FF

Byte 3

Number
of CPU
cycles

I

I

Example

I

I
I

I

I

I

Number
of
bytes

VAL2

IGNORE SIGN BIT

WORK (LOWER)

3

Conditional Branch

BIH
BIH (Branch if Interrupt line is High)

I

I

II

Format

Condition Codes

BIH dd

I

Not affected.

Ij

Operation
PC

+

II

(PC)+OOO2+Rel

i f INT=l (high)

I

Description

I

Tests the external interrupt pin (INT) state and causes a branch if it is
high.

Addressing Mode and Number of CPU Cycles

,

Addressing
Mode

Mnemonic

,,
I
I

RELATIVE

BIH

I
I

Operand
type
Rel

Instruction code
Byte 1 :I Byte 2
2F

,,
I

I
I

.

I
I
I
I
I
I

2

3

I

,I

,

I
I

I
I

I

I
I

,

,I

I
I

I
I
I

,

OlC6
01C8
OlCA
OlCC
OlCE

,

I

,

Example

Rel

Byte 3

Number
of CPU
cycles

,I

,I

I

,
I

I
I
I
I
I
I
I

Number
of
bytes

II
2F
A6
20
A6
C7

04
28
02
FF
06EO

INTLl
INTHO
NEXT2

BIH
LDA
BRA
LDA
STA

INTHO
#$28
NEXT2
#$FF
PIA

INT LINE CHECK
OUTPUT DATA = $28
OUTPUT DATA = $FF
OUTPUT

~HITACHI
43

Conditional Branch
BIL
BIL (Branch if Interrupt line is Low)

I

Format

I

II

PC

I

Operation
~

II

Not affected.

BIL dd

I

Condition Codes

IJ

(pC)+OOO2+Rel i f INT=O (low)

Description

I

-Tests the external interrupt pin (INT) state and causes a branch if it is
low.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

I

Mnemonic: Operand
I
type

Instruction code
Byte I i Byte 2

I

I

I

I

I

RELATIVE

BIL

2E

ReI

I

ReI

I

.
I
I

I
I

I

I

I

I

I

I
I

I

.

I

I
I

I
I

:
I
I
I

I

I
I

Example

0101
0103
0105
0107
0109

2E
A6
20
A6
C7

I

I

'I
04
45
INTH3
02
00
INTL2
06EO NEXT4

BIL
LOA
BRA
LOA
STA

INTL2
#$45
NEXT4
#$0
PIA

INT LINE CHECK
OUTPUT DATA = $45
OUTPUT DATA
OUTPUT

~HITACHI
44

2

I
I
I
I

I
I
I

I

Byte 3

=

Number
of
bytes

$00

Number
of CPU
cycles
3

Logical Operation
BIT
BIT (BIt Test)

I

I

II

Format

II

Operation
(ACCA)!\(M)

I

Description

Ir

R: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result of the AND operand is
1; otherwise cleared.
Z: Set if all the bits of the result
of the AND operand are 0; otherwise cleared.
C: Not affected.

BIT P

I

Condition Codes

I

Performs the logical AND operation between the ACCA contents and M contents
and modifies the condition codes respectively. The ACCA contents and M
contents are not affected.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

I

Mnemonic: Operand
I
type
I

,
IMMEDIATE
DIRECT

BIT
BIT

EXTENDED

BIT

lNUI;./iliU U IHTI;

BIT

OFFSET
I~~~~~ED 1 BYTE
FF ET

~;~~~~lJ

l

BIT
BIT

BYTJ;

I
I
I

IIImm

Instruction code
Byte 1 :I Byte 2
I

M

A5
B5

M

C5

:

F5

I

O,X
Disp X
Disp,X

E5
D5

I
I
I
I
I

Byte 3

Imm
M
MH

ML

I
I
I

I
I

D
DR

DL

Number
of
bytes

Number
of CPU
cycles

2
2

2
3

3

4

1

3

2
3

4
5

I

I
I
I

I

Example

II

0400 B6 10
0402 A5 FB
0404 27 19
0406 A6 E3
CC 0432

040B

EVBIT

*

NG

LOA
BIT
BEQ

VALl
#$FB
OK

LOA
JMP

#227
ERROR

o <= BIT ASSIGN (VALl)

<=

7

SET ERROR NUMBER

~HITACHI
45

Conditional Branch
BLO
BLO (Branch if LOwer)

I

I Format II

Condition Codes

BLO dd

II

Not affected.

II

Operation

PC + (PC)+OOO2+Rel i f (C)=l

I

Description

I

,

Causes a branch when executing BLO after compare if register contents are
less than M contents.
BLO is equivalent to BCS.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

RELATIVE

Operand
type

BLO

Instruction code
Byte 1 :I Byte 2

ReI

25

I
I

Byte 3

Number
of
bytes

Number
of CPU
cycles

2

ReI

I
I
I

I

:
I
I
I
I

I
I
I

I
I
I

I

Example

II

040B B6 10
040D B1 20
040F 25 16
0411 B7 FF

*

lDA
CMP
BlO

VAll
VAl2
ZIP27

VAll

<

STA

WORK

VAll

-->

$HITACHI
46

VAl2 (IGNORE SIGN BIT)
WORK HIGHER OR SAME

3

Conditional Branch
BLS
BLS (Branch if Lower or Same)

I

I

II

Format

Condition Codes

BLS dd

I

Operation
PC

+

Not affected.

II

(PC)+0002+Rel if (C V Z)=l
Le. i f (ACCA)

I

II

Description

~

(M)

]

Causes a branch if either C-bit or Z-bit is "1". When the BHI instruction
is executed immediately after either CMP or SUB instruction has been executed,
a branch occurs if the minuend represented by the unsigned binary number
(Le. ACCA) is less than or equal to the subtrahend represented by unsigned
binary number (i.e. M).
Addressing Mode and Number of CPU Cycles
Addressing
Mode

Operand
type

Mnemonic

RELATIVE

BLS

Instruction code
Byte 1

Byte 2

23

Rel

Rel

Byte 3

Number
of
bytes

Number
of CPU
cycles

2

3

I
I
I
I

I

I
I

I

I

I
I

Example

"

0413 B6 10
0415 B1 20
0417 23 16
0419 B7 FF

*

LDA
CMP
BLS

VALl
VAL2
ZIP28

VALl

STA

WORK

VAll ---> WORK (HIGHER)

<=

VAL2 IGNORE SIGN BIT

~HITACHI
47

Conditional Branch
BMC
BMC (Branch i f interrupt Mask is Clear)

I

I

II

Format

Condition Codes

BMC dd

I

Operation
PC

I

+

II

Not affected.

IJ

(PC)+0002+Rel i f (1)=0

Description

]

Tests the I-bit state and causes a branch if I is "0".

Addressing Mode and Number of CPU Cycles

·

, Operand
Mnemonic ,,
type

Addressing
Mode

I

RELATIVE

BMC

,
ReI
,
I
I

·
I
I
I
I
I

,
I

I
I

I

·

I
I

I

,I

II 07

2C
2E
C6
B7
81

05
06EO
FF

MSKOFF

I

I

I

0217
0219
021B
021E
0220

2C

·
·,
·,
·
,I

·
Example

Byte 1 : Byte 2

I

I

I

Instruction code

I

·
BMC
BIL
LOA
STA
RTS

MSKOFF
MSKOFF
PIA
WORK

~HITACHI
48

ReI

,
I
I
I

,

Byte 3

Number
of
bytes
2

•I
I

I
I
I

I
I

·
I
I

,I

·
I

I
I
I
I

INTMSK OFF?
INT LINE LOW ?
READ DATA

Number
of CPU
cycles
3

Conditional Branch
BMI
BMI (Branch if MInus)

I

I

II

Format

Condition Codes

BMI dd

I

I

+

Not affected.

II

Operation
PC

II

(PC)+OOO2+Rel i f (N)=l

Description

]

Tests the N-bit state and causes a branch if N is "1".

Addressing Mode and Number of CPU Cycles
Addressing
Mode

,
Mnemonic

RELATIVE

I

BMI

Operand
type
ReI

Instruction code
Byte 1

Byte 2

2B

ReI

Byte 3

Number
of
bytes
2

Number
of CPU
cycles
3

,
,I
I

,I
I

,
I

[

Example

II

0425 B6 10
0427 2B 16
0429 B7 FF

*

LDA
BMI

VALl
ZIP29

VALl < 0

STA

WORK

VALl ---> WORK (PLUS)

~HITACHI
49

Conditional Branch
BMS
BMS (Branch if interrupt Mask is Set)

I

Format

I

IJ

BMS dd

I

II

Condition Codes
Not affected.

II

Operation

PC + (pC)+OOO2+Re1 i f (1)=1

I

Description

II

Tests the I-bit state and causes a branch if I is "1".

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Operand
type

Mnemonic
BMS

Re1

Instruction code
Byte 1 iI Byte 2 : Byte 3
2D

I
I

Re1

2

I
I

,
I

:
,
I

I
I
I
I

,
I

,

I

I

0221
0223
0224
0226
0229
022B

I
I

II

Example

20
81
20
C6
B7
81

01
FD
06EO
FF

MSKOF1
MSKON1

BMS
RTS
BIL
LOA
STA
RTS

MSKON1
MSKOF1
PIA
WORK

~HITACHI
50

INTMSK ON ?
NO
INT LINE LOW
DATA

Number
of
bytes

?

Number
of CPU
cycles
3

Conditional Branch
BNE
BNE (Branch if Not Equal)

I

Format

I

IJ

BNE dd

I

I

+

II

Not affected.

II

Operation
PC

Condition Codes

(pC)+0002+Rel if (Z)=O

Description

I

Tests the Z-bit state and causes a branch if Z is "0".
Following a compare or subtract instruction, BNE will cause a branch
if the arguments were different.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

,,
I
I

Operand
type

I

RELATIVE

BNE

I

I

,

Rel

Instruction code
Byte 1 :I Byte 2
26

I

I
I

2

3

,,

I

0200
020F
0211
0213

Rel

,I

,
,
,
I
,,

Example

,,
,

Byte 3

Number
of CPU
cycles

,
:

,I

I

,
I

Number
of
bytes

I
I

,

,

I

I

,I

I

,

II
B6
26
B1
26

FF
18
50
10

LOA
BNE

eMP

BNE

WORK

ecce

WORK NOT = 0
RESULT
DODD
WORK NOT = RESULT

~HITACHI
51

Conditional Branch
BPL
BPL (Branch if PLus)

I

Format

I

II

BPL dd

I

II

Condition Codes
Not affected.

II

Operation

PC +(PC)+0002+Rel if (N)=O

I

Description

II

Tests the N-bit state and causes a branch if N is "0".

Addressing Mode and Number of CPU Cycles
Addressing
Mode

,
Mnemonic:, Operand
type
I

RELATIVE

BPL

I
I

,
I
,,
,,,
,,,
,,I

ReI

Instruction code

2A

,

I
I

I

,,
,
,,

Byte 3

,
,

2

I
I
I

,,

,
I

,,
,,

,,

LOA
BPL

VALl
ZIP31

VAL

STA

WORK

VALl

I

,

II

0215 B6 10
0217 2A 16
0219 B7 FF

*

~HITACHI
52

ReI

I

Number
of CPU
cycles

,,

,I
Example

,

,

,

I

I

Byte I : Byte 2

Number
of
bytes

>=

0

--->

WORK (MINUS)

3

Unconditional Branch
BRA
BRA (BRanch Always)

I

I

II

Format

Condition Codes
Not affected.

BRA dd

I

I

II

Operation

PC

+

II

(PC)+OO02+Rel

Description

J

Causes an unconditional branch to the address gain from the operation
shown above.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte I : Byte 2
I

RELATIVE

BRA

ReI

20

I
I

ReI

Byte 3

Number
of
bytes
2

Number
of CPU
cycles
3

I
I
I

I

:
I
I

I
I

I
I
I

I
I
I

I

Example

II

0100 C6 0500
0103 B7 50
0105 20 lE
0107

*

CHECK8

LOA
STA
BRA

EXVAL5
RESULT
ENOOl

EQU

*
•

BRANCH TO ENOOl ALWAYS

HITACHI
53

Conditional Branch
BRCLR
BRCLR (BRanch if bit n is CLeaR)

I Format

I

IJ

II

Operation

II

H: Not affected.
I: Not affected.
N: Not affected.
Z: Not affected.
C: Set i f (Mn)=l; otherwise reset.

BRCLR n, DR, dd

I

Condition Codes

PC + (PC)+0003+Rel i f (Mn)=O

I

Description

]

/

Tests the bit n (n = 0 through 7) of M and causes a branch if the
contents of Mn are "0".

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 : Byte 2
I

I

RELATIVE
RELATIVE
RELATIVE

BRCLR
BRCLR
BRCLR

O,M ReI
I,M,Rel
2,M,Rel

01
03
05

RELATIVE
RELATIVE

BRCLR
BRCLR

3,M,Rel
4,M,Rel

07
09

I

RELATIVE
RELATIVE

BRCLR
BRCLR

5,M,Rel
6,M,Rel

OB
OD

I

RELATIVE

BRCLR

7,M,Rel

OF

I
I

I

II

Example

0107
0109
OlOB
0100

B6
A4
BA
B7

LOA
AND
ORA
STA

03
OF
FF
03

OlaF 09 03 17
0112 OF 03 28

*

BRCLR
BRCLR

I

I
I
I
I

:
I
I
I

I
I

I

Number
of CPU
cycles

M
M
M

ReI
ReI
ReI

3
3
3

5
5
5

M
M

ReI
ReI

3
3

5
5

M
M

ReI
ReI

3
3

5
5

M

ReI

3

5

CNTRL
** SET CONTROL CODE **
#$OF
WORK
CNTRL
** ACTION **
4,CNTRL,ENGINE
7,CNTRL,GASCHK

.HITACHI
54

Byte 3

Number
of
bytes

Unconditional Branch
BRN
BRN (BRanch Never)

I

I

II

Format

Condition Codes
Not affected.

BRN dd

I

I

II

Operation

PC

-+-

II

(PC)+OOO2

Description

I

It does not cause a branch. BRN, which requires 2-byte and 3 cycle
long, is the inverse of BRA. This instruction is sometimes available
for debugging program.
Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Mnemonic
BRN

,,
I
I
I
I
I

Operand
type
Rel

Instruction code
Byte 1 :I Byte 2
21

I

,

,I

:

2

3

,I
I
I

I

I

I
I

I

,

,

I

I

,

,

I

I

,
I

:
,,

I

I
I

I

II

0115 EF 04
0117 21
0119 21
011 B 21
0110 21

Rel

I

I
I
I
I
I
I

Example

Byte 3

Number
of CPU
cycles

I
I

I

I

,
I

Number
of
bytes

FE
FE
FE
FE

*

STX

4.X

BRN
BRN
BRN
BRN

*
*
*
*

** DELAY **

~HITACHI
55

Conditional Branch
BRSET
BRSET (BRanch if bit n is SET)

I

Format

I

11

PC

I

+

I: Not affected.
N: Not affected.
Z: Not affected.
C: Set i f (Mn)=l; otherwise reset.

II

Operation

II

H: Not affected.

BRSET n, DR, dd

I

Condition Codes

(PC)+OO03+Rel i f (Mn)=l

Description

II

Tests the bit n (n =
Mn contents are "1".

o

through 7) of M, and causes a branch if the

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code

BRSET

O,M,Rel

Byte 3

I

M

ReI

3

5

M
M

ReI
ReI

3
3

5
5

M
M

ReI
ReI

3
3

5
5

M

ReI

3

5

M
M

ReI
ReI

3
3

5
5

00

I
I
I

RELATIVE
RELATIVE

BRSET
BRSET

1,M,Rel
2,M,Rel

02
04

RELATIVE
RELATIVE

BRSET
BRSET

3,M ReI
4,M,Rel

06
08

I
I

RELATIVE

BRSET

OA

I

RELATIVE
RELATIVE

BRSET
BRSET

5,M,Rel
,
'6,M,Rel
: 7,M,Rel

OC
OE

I

I

Example

OllF
0121
0123
0125

,
I

:
I
I

I
I

I
I

II
B6
A4
BA
B7

03
8E
FF
03

*

0127 00 03 17 PROC1
012A OE 03 28 PROC2

** SET CONTROL CODE **

LDA
AND
ORA
STA

CNTRL
#$8E
WORK
CNTRL

BRSET
BRSET

O,CNTRL,OIL
7,CNTRL,GAS

~HITACHI
56

Number
of CPU
cycles

Byte 1 : Byte 2
I

RELATIVE

Number
of
bytes

** ACTION **

Bit Control
BSET
BSET (Bit SET bit n)

I Format II

Condition Codes

BSET n,DR

I

I

-+-

Not affected.

1/

Operation

Mn

II

1

Description

I

Sets the bit n (n

=

0 through 7) of M.

All other bits are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

,
Mnemonic : Operand
, type
I

I

Instruction code
Byte 1

! Byte

2 : Byte 3

Number
of
bytes

Number
of CPU
cycles

DIRECT
DIRECT

BSET
BSET

: O,M

10

M

2

5

: I,M

12

M

2

5

DIRECT

BSET

: 2,M

14

M

2

5

: 3,M

16

M

2

5

: 4,M

18

M

2

5

5,M

lA

M

2

5

'6M

lC
lE

M

2

M

2

5
5

I

DIRECT
DIRECT

BSET
BSET

DIRECT

BSET

DIRECT
DIRECT

BSET
BSET

Example

II

01 00 B6 50
0102 2A 04
0104 14 03
0106 16 FF
0108
0108 B6 20

,
,
I
I

7,M

BPL

RESULT
PLUS

BSET
BSET

2.CNTRL
3,WORK

EQU

*

LOA

*
PLUS

LOA

:

(MINUS)

VAL2

~HITACHI
57

Subroutine Control
BSR
BSR (Branch to SubRoutine)

II

II

Format

BSR dd

I

-+-+-+-+-

II

Not affected.

II

Operation
PC
Msp
Msp
PC

Condition Codes

(PC)+OOO2
(PCL) , SP -+- (SP)-OOOl
(PCR) , SP -+- (SP)-OOOl
(PC)+Re1

Description

I

The program counter is increased by "2". The less significant bites
(8-bits) of the program counter contents are pushed onto the stack.
Then, stackpointer is decreased by "1". The more significant bits
(6-bits) of the program counter contents are pushed onto the stack,
then stackpointer is decreased by "1". Then a branch occurs to the
address specified by the program counter.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

,
Mnemonic

I
I
I

Operand
type

I

RELATIVE

BSR

I
I

Re1

Instruction code
Byte 1 :I Byte 2

I

I

I
I

AD

I

I
I

2

Number
of CPU
cycles
5

I

I
I
0

I
I

I

I
I

I

I

I
I

I
I

I

I

I
I

I

I

I

I

I

I

I
I

I

II

010A A6 38
010C AD 18
alOE A6 1E
0110 AD 28

*

LOA
BSR

#$38
HAND

ACCA = INTERFACE (0011 1011 )

LOA
BSR

#$lE
FING

ACCA = INTERFACE (0001 111 0)

~HITACHI
58

Re1

Byte 3

Number
of
bytes

I

I

Example

I

I
I

I

I

I

Bit Control
CLC
CLC (CLear Carry)

I

I

II

Format

C

I

II

Operation
-<-

II

H: Not affected.
I: Not affected.
N: Not affected.
Z: Not affected.
C: Reset.

CLC

I

Condition Codes

0

Description

I

Resets the carry bit C in the condition code register.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMPLIED

,
Mnemonic
CLC

I
I
I

,

Operand
type

,,
,

Instruction code
Byte 1 II Byte 2
98

I

I
I

1

I

I

I

,

I

I

,,

,

,

,,

I

I

0100
0102
0104
0105

Number
of CPU
cycles

,

,,
,,
,

Example

1

,,

,
:
,
,

,I

I

Byte 3

,
,

Number
of
bytes

,,
,
I

:,
,,

,
I
I

II
26 F8
B7 50
98
81

BNE
STA
CLC
RTS

CHK83
RESULT

RETURN COOE SET 'OK'

*
*
~HITACHI
59

Bit Control
CLI
CLI (CLear Interrupt mask)

I

Format

I

1/

II

H: Not affected.

CLI

I

Condition Codes

I: Reset.
N: Not affected.
Z: Not affected.
C: Not affected.

II

Operation
I+-O

I

Description

H

Resets the interrupt mask bit in the processor condition code register.
This enables the microprocessor to service interrupts that occurred
through an interrupt request from peripheral equipment.
Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMPLIED

,
Mnemonic

,
I

I

CLI

Operand
type

Instruction code

I

Byte 1 :, Byte 2

,

I

I

9A

I

,

,I

:

I

I
I
I
I
I
I

I
I
I
I

I

I

I

I

,I

I

I

I

I
I

Example

OlFA
OlFB
OlFC
OlFF

I
I

II
9B
9C
CD 06FO
9A

SEI
RSP
JSR
CLI

SYSINZ

~HITACHI
60

1

I
I

I

I

I

Byte 3

Number
of
bytes

INTERRUPT DISABLE
RESET STACK POINTER
SYSTEM INITIALIZE
INTERRUPT ENABLE

Number
of
cycles
2

Arithmetic Operation
CLR
CLR (CLeaR)

I

Format

I

IJ

CLR Q
CLR A
CLR X

I

or
ACCA
or
M

I

II

H: Not affected.

I:
N:
Z:
C:

II

Operation
IX

Condition Codes

+

0

+

0

+

0

Description

Not affected.
Reset.
Set.
Not affected.

I

The contents of IX, ACCA or M are replaced with "0".

Addressing Mode and Number of CPU Cycles
Addressing
Mode
ACCUMULATOR

,
Mnemonic

I

CLR

INDEX REG.
DIRECT

CLR
CLR

INDEXED u BYTt:
OFFSET
INDEXED .L BYTE
OFFSET

I
I
I

CLR
CLR

I

I

Operand
type

4F

X

SF

I

,
I
I
I
I
I

M

oX

, Disp,X
,,I
,
I

Example

0106
0108
OlOA
OlOB

II
3F 07
3F 08
7F
4F

*

Byte 3

Number
of
bytes

,
,,
I
I

I

3F

:

M

7F
6F

,I
,,

D

Number
of CPU
cycles

1

2

1

2

2

S

1

5

2

6

I
I

,
,,
I

,I

I

Byte 1 ,: Byte 2

A

I

I

Instruction code

!

CLR
CLR
CLR
CLR

PNTR
PNTR+l
O,X
A

** INITIALIZE **

~HITACHI
61

Comparison and Test
CMP
CMP (CoMPare)

I

Format

I

IJ
II

Operation

(ACCA)-(M)

I

Description

II

R: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result of the subtraction is
"1"; otherwise reset.
Z: Set if the result of the subtractio~
is 0; otherwise reset.
C: Set if the absolute value of memory
is greater than that of the
accumulator; otherwise reset.

CMP P

I

Condition Codes

II

Compares the ACCA contents with M contents, and affects the condition
codes that can be referred to by conditional branch instructions.
Both operands are unaffected.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

Operand
type

Mnemonic

Instruction code
Byte 1 : Byte 2

,
I

IMMEDIATE

IIImm

CMP

DIRECT

CMP

EXTENDED
INDEXED U BYTE
OFFSET
lNlJllXllD 1 BYTE
OFFSET
INDEXED 2 BYTE
OFFSET

Al
Bl

M

CMP

M

Cl

CMP

0 X

Fl

CMP
CMP

DisD X
Disp,X

El
Dl

,
I

II

0110 E6 07
0112
0114
0116
0118
OllA

A1
27
A1
27
20

41
1A
42
2A
FO

*

M

I

:

,
I
I

,
I

LOA

PNTR,X

CMP
BEQ
CMP
BEQ
BRA

#'A
SECTA
#'B
SECTB
INPUT

~HITACHI
62

MH

Byte 3

I

,,
,
I

ML

Number
of
bytes

Number
of CPU
cycles

2

2

2

3

3

4

1

3

2
3

4
5

I

I

I
I

D
DR

,
I

:

DL

I
0
0

,,,

,,

0

Example

Imm

I
I

,

I

I
I
I
I

,,
,,
,,

ACCA = 'A'
ACCA

=

'B'

Logical Operation
COM
COM (COMplement)

I

Format

I

IJ

COM Q
COM A
COM X

I

IX

+- (IX) =$FF-(IX)
or
ACCA +- (ACCA) = $FF-(ACCA)
or
M +- (M) = $FF-(M)

I

Description

Ir

H: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result is "1"; otherwise
cleared.
Z: Set if the result is "0"; otherwise
reset.
C: Set.

II

Operation

Condition Codes

I

II

Replaces the contents of ACCA, IX or M with its l's complement.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
ACCUMULATOR

0

Mnemonic
COM
COM
COM

INDEX REG.
DIRECT
INDEXED 0 BYTE
OFFSET
INDEXED 1 BYTE
OFFSET

COM
COM

I
I
I
I
I

A
X
M

I
0

I
I
0

I
I
0
0

I
0

Instruction code

Operand
type

Byte 1 :0 Byte 2

I
I

I

I
I
I
I

43
53
33

O,X

73

Disp X

63

I

Example

onc
OnD
011F
0120

II
onc
5C
E6 07
43
81

*

SUBIN

0

:

M

I
I

2

5

1

5

2

6

2

I

I
0
0
0

2

I

1
1

I

0
0

Number
of CPU
cycles

D

I

I

I

0

I

Byte 3

Number
of
bytes

0
0

I

I

I

I

I

0

0

0

EQU
INC
LOA
COM
RTS

*

X
PNTR,X
A

MODIFY DATA (REVERSE)

*
~HITACHI
63

Comparison and Test
CPX
CPX (ComPare indeX register)

I

Format

I

II

CPX P

I

(IX)-(M)

I

Description

Ir

R: Not affected.
I: Not affected.
N: Set i f the most significant bit of
the result is "1"; otherwise reset.
Z: Set i f the result is "0"; otherwise
reset.
C: Set i f the absolute value of the
contents of the memory is greater
than that of the contents of IX;
otherwise reset.

II

Operation

Condition Codes

II

Compares the IX contents with M contents. The condition code can be
collated by means of the next conditional branch instruction. Both
operands are unaffected.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

I

Mnemonic: Operand
I
type

Byte 1

Byte 2

tFImm
M

A3
B3

Imm
M

M

C3

MH

oX

F3
E3

D

D3

DR

I

IMMEDIATE
DIRECT

CPX

EXTENDED
INDEXED a BYTE
OFFSRT
IN~~:D

1 BYTE

OFF T
INDEXED 2 BYTE
OFFSET

I
I

CPX

I

CPX

I

I

I

I
I

CPX
CPX

: Disp ,X

CPX

: Disp X

I
I

Instruction code

I

Byte 3

Number
of
bytes

ML

DL

Number
of CPU
cycles
2

2
2

3

3

4

1
2

3
4

3

5

I

I
I
I

I

Example

0121
0123
0125
0127
0129
0128

A6
BE
A3
27
A3
27

IICC

07
00
18
OA
28

LOA
LOX
CPX
BEQ
CPX
SEQ

#$CC
PNTR
#$00
CR
#$OA
LF
~HITACHI

64

ACCA

=

INTERFACE TO CR OR LF

CARRIAGE RETURN
LINE FEED

Arithmetic Operation
DAA
DAA (Decimal Adjust Accumulator)

I

Format

I

II

I: Not affected.
N: Set i f the most significant bit of
result is "1"; otherwise reset.
Z: Set i f the result is "0", otherwise reset.
C: Set or reset with the rule under
which DAA and its previous ABA,
ADD and ADC is converted into BCD.

II

Operation

Convert binary Add result
into Binary Coded Decimal (BCD).

I

I

H: Not affected.

DAA

I

Condition Codes

Description

I

Bi t Condi tion Lower
of bit C
4 bits
before DAA
(bit
execution
4" 7)
0
0
0
0
0
0
0
0
0

Early Lower
H bit 4 bits
(Half (bit
Carry) 0"3)

0-9
0-8
0-9
A-F
9-F
A-F
0-2
0-2
0-3

0
0
1
0
0
1
0
0
1

Value added
to ACCA by
DAA execution
(hexadecimal)

0-9
A-F
0-3
0-9
A-F
0-3
0-9
A-F
0-3

Bit condition
of bit C
before DAA
execution

00
06
06
60
66
66
60
66
66

0
0
0
1
1
1
1
1
1

Add 00, 06, 60
66 (heradecimal)
to ACCA according
to the table
shown left.
If the BCD Add
result by ADD and
ADC instruction
is in ACCA, bit
C or bit H, DAA
executes above
function.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMPLIED

Operand
type

Mnemonic
DAA

Instruction code
Byte 1 :I Byte 2
8D

I
I

Byte 3

Number
of
bytes
1

Number
of CPU
cycles
2

I
I

,

·
I

I

·
I
I

I
I
I
I
I
I

I

Example

II

,

,

~HITACHI
65

Arithmetic Operation
DEC
DEC (DECrement)

I Format

I

1/

DEC Q
DEC A
DEC X

I

Operation
IX

Condition Codes

1/

H: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result is "1"; otherwise reset.
Z: Set if the result is "0"; otherwise
reset.
C: Not affected.

1/

(IX)-Ol
or
ACCA -+- (ACCA)-Ol
or
M +- (M)-Ol

I

-+-

Description

1

Subtracts "1" from the contents of ACCA, IX or M.
Nand Z bits are set and reset according to the result of this operation.
The C-bit is not affected.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Instruction code

Operand
type

Byte 1

Byte 2

Byte 3

Number
of
bytes

Number
of CPU
cycles

ACCUMULATOR

DEC

A

4A

1

2

INDEX REG.
DIRECT

DEC
DEC

X
M

SA
3A

M

1
2

2
5

D

1
2

5
6

lN~:~J) U

OFF E
~~~!:D

I

lira;

1BUI!

Example

DEC
DEC

1/01204A
012E 2B 07
0130 FE
0131 OF 0100
0134 5C
0135 20 F6
0137

O,X
Disp,X

BMI
LOX
STX
INC
BRA

** MOVE
A
NEXT
O,X
$100,X
X
LOOP23

EQU

*

*LOOP23 DEC

*NEXT
•

66

7A
6A

HITACHI

**
*
*
*

Logical Operation
EOR
EOR (Exclusive OR)

I

I

II

Format

ACCA

I

II

Operation
-<-

(ACCA)

Description

II

R: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result is "1"; otherwise reset.
Z: Set if the result is "0"; otherwise
reset.
C: Not affected.

EOR P

I

Condition Codes

®

(M)

II

Performs the logical EXCLUSIVE OR between the ACCA contents and M
contents and stores the result into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 :I Byte 2

IMMEDIATE

EOR

flImm

A8

DIRECT
EXTENDED

EOR
EOR

M
M

B8
C8

EOR
EOR

O,X
Disp,X

F8
E8

EOR

Disp,X

D8

INDEXED 0 BYTE
OFFSET
INDEXEu .l HlT!>
OFFSET
INDEXED 2 BYTE
OFFSET

I

Byte 3

Number
of
bytes

Number
of CPU
cycles

I

Imm

2

2

I
I
I

M

2

3

I

:

MH

ML

I
I
I
I

D

I

DR

I

DL

3

4

1
2

3
4

3

5

I
I
I
I

I

Example

0137
0139
013B
0130

B6
A8
B7
20

"
03
99
03
14

*

LOA
EOR
STA
BRA

** ARRANGE CONTROL CODE **
XXXX XXXX
1001 1001

CNTRL
#$99
CNTRL
ACTOl

,
~HITACHI
67

Arithmetic Operation
INC
INC (INCrement)

I Format

I

1/

INC Q
INC A
INC X

I

1/

H: Not affected.

Operation

I: Not affected.
N: Set if the most significant bit of
the result is "1"; otherwise reset.
Z: Set if the result is "0"; otherwise
reset.
C: Not affected.

1/

IX +- (IX)+Ol
or
ACCA +- (ACCA)+Ol
or
M+- (M)+Ol

I

Condition Codes

Description

]

Adds "1" to the contents of ACCA, IX or M.
Nand Z bits are set or reset according to the result of this operation.
The C bit is not affected.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

ACCUMULATOR
INDEX REG.

INC
INC

DIRECT
~;~::D

UBYTE

~~~~~~11

J.

I

JSrr~

Example

0100
0101
0103
0105
0106
0109
010A

4C
Al
22
FE
DF
5C
20

II
64
1B
0300
F4

Operand
type

Byte 1

A
X

4C
5C

INC

M

3C

INC
INC

oX

7C
6C

LOOP3

Disp X

INC
CMP
BHI
LDX
STX
INC
BRA

A
#100
EXIT
O,X
$300,X
X
LOOP3

$
68

Instruction code

HITACHI

Byte 2

Byte 3

Number
of
bytes

Number
of CPU
cycles

1
1

2
2

M

2

5

D

1
2

5
6

*
CHECK COUNTER (100 TIMES)
MOVE

*

Conditional Branch
JMP
JMP (JuMP)

I

I

II

Format

Condition Codes
Not affected.

JMP P

I

I

II

Operation
PC

+-

II

EA

Description

I

A jump occurs to the instruction stored at the effective address. The
effective address is obtained according to the rules for EXTended, DIRect
or INDexed addressing.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
DIRECT

Mnemonic

Operand
type

JMP

EXTENDED

JMP
JMP

INDEXED 0 BYTE
_OFFSET
INDEXED 1 BYTE
OFFSET
INDEXED l IIYTJ>
OFFSET

JMP
JMP

M

Instruction code
Byte 1 :I Byte 2
BC

M

CC
FC

a,x
DisD X
Disp,X

EC
DC

I
I

.
I
I

Byte 3

Number
of
bytes

M
MH

ML

I

:
I
I
I
I

D
DR

DL

Number
of CPU
cycles

2

2

3

3

1

2

2

3

3

4

I
I
I
I
I
I

I

Example

OlOC
OlOE
0111
0113
0116

II
B6
C7
B6
C7
CC

10
0500
20
0600
0333

LDA
STA
LDA
STA
JMP

VAll
EXVAL5
VAL2
EXVAL6
END90

GO TO END-ROUTINE

~HITACHI
69

Subroutine Control
JSR
JSR (Jump to SubRoutine)

II

Format

i

II

JSR P

I

Operation
Note)
PC +
Msp +
Msp +
PC +

Condition Codes

II

Not affected.

1/

(PC)+n
(PCL) , SP
(PCR) , SP
EA

+
+

(SP)-OOOl
(SP)-OOOl

.-

I

Description

II
Note)

The program counter is increased by "n"in the addressing m0tie,
then pushed onto the 2-byte stack. And the stack point is updated.
A jump occurs to the specified address.
The effective address is obtained according to the rules for EXTended,
DIRect or INDexed addressing.
Note)

n is equal to 1, 2 or 3, according to the number of bytes in the
instruction code. Refer to the addressing code and the number of
MPU cycles shown below.
Addressing Mode and Number of CPU Cycles

Addressing
Mode
DIRECT
EXTENDED
INDEXED 0 BYTE
OFFSET
INDEXED 1 BYTE
OFFSET
INDEXED 'L. BYTE
OFFSET

I

Example

0119
011C
OllF
0122
0125

II
0119
CD 0407
CD 04E5
CD 03AD
CD 053C
CC 06CB

Mnemonic

Instruction code

Operand
type

Byte 1 ,: Byte 2

JSR
JSR

M
M

BD
CD

JSR

O,X

FD

JSR

Disp,X

ED

JSR

Disp X

DD

*

START

EQU
JSR
JSR
JSR
JSR
JMP

,,
,,,

,

:
,,
,,
,,

MH

,,,

Byte 3

,

ML

D
DR

DL

Number
of
bytes

INTRTN
KBRTN
ANARTN
PRCRTN
ENDRTN

Number
of CPU
cycles

2
3

5
6

1

5

2

5

3

6

** MAIN ROUTINE **
*

~HITACHI
70

M

,,

INITIALIZE
INPUT FROM KEY-BOARD
ANALYSE
PROCESS
END

Load & Store
LDA
LDA (LoaD Accumulator)

I

I

II

Format

Operation
ACCA

I

-<-

Codes

II

R: Not affected.
I: Not affected.
N: Set i f the most significant bit of
the result is "1"; otherwise reset.
Z: Set if the result is "0"; otherwise reset.
C: Not affected.

LDAP

I

Co~dition

1/
(M)

Description

I

Loads the contents of memory into the accumulator.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMMEDIATE

Mnemonic
LDA
LDA

DIRECT
EXTENDED

LDA

INDEXED 0 BYTE
OFFSET
INDEXED 1 BYTE
OFFSET
INDEXED 1. BYTE
OFFSET

I
I
I

,

Operand
type

Instruction code

I

Byte 1 :I Byte 2

I

I

I
I
I

,

A6
B6

f1Imm
M
M

I

LDA
LDA

O,X
Disp,X

LDA

Disp,X

I

Imm

I
I
I

M

I
I

C6

,

F6

I

E6
D6

I
I

I
I
I

Example

II

0128
012A
012C
0120
012F

B6
B7
F6
B7
A6

10
FF
50
FF

LOA
STA
LOA
STA
LOA

I

Byte 3

I
I
I

,
I

I
I

I
I

ML

Number
of
bytes

Number
of CPU
cycles
2

2
2

3

3

4

1
2

4

3

5

I

I

I
I
I

I

I

MH

,

,

I

D
DR

I
I

:

DL

3

I
I
I
I
I

I

VAll
WORK
O,X
RESULT
#$FF

~HITACHI
71

Load & Store
LDX
LDX (LoaD indeX register)

I

Format

I

1/

LDX P

I

IX

I

+-

Ij

H: Not affected.
I: Not affected.
N: Set i f the most significant bit of
IX is "1"; otherwise reset.
Z: Set i f all the bits of IX of the
result are "0"; otherwise reset.
C: Not affected.

II

Operation

Condition Codes

(M)

Description

I

Loads the M contents into IX.
to data.

The condition code is set according

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 : Byte 2
I

IMMEDIATE

LDX

IIImm

AE

DIRECT
EXTENDED

LDX
LDX

M
M

BE
CE

INDEXED 0 BYTE
OFFSET
INDEXED 1 BYTE
OFFSET
INDEXED 2 BYTE
OFFSET

LDX

O,X

FE

LDX
LDX

Disp X
Disp,X

EE
DE

I

Imm

2

2

I
I
I

M

2
3

3
4

1

3

2

4

3

5

I

:

MH

I
I

I
I

D
DH

I
I

1/
0131
0133
0135
0136
0138

BE
BF
FE
BF
AE

10
FF
50
FF

LOX
STX
LOX
STX
LOX

~HITACHI
72

ML

I
I

I

Example

Number
of CPU
cycles

I

I

I

Byte 3

Number
of
bytes

VAll
WORK
O,X
RESULT
#$FF

DL

Shift & Rotation
LSL
LSL (Logical Shift Left)

I

Format

I

II

LSL Q
LSL A
LSL X

I

Operation

IJ
•

@]~-I
b.

I

I I I I I I I 1+-

Description

0

II

Condition Codes

H: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result is "1"; otherwise reset.
Z: Set if the result is "0"; otherwise
reset.
C: Set if the least significant bit of
ACCA, IX or memory is "1" before
execution of an instruction;
otherwise reset.

bo

II

Shifts the contents of ACCA, IX or M 1-bit to the left. The bit 0 is
loaded with "0". The carry bit C is loaded with the most significant
bit of ACCA, IX or M.
Addressing Mode and Number of
Addressing
Mode

Mnemonic

Operand
type

Cycles

Instruction code
Byte 1 : Byte 2
I

ACCUMULATOR

LSL

INDEX REG.
DIRECT

LSL
LSL

INDEXED U BYTE
OFFSET
INDEXED 1 BYTE
OFFSET

48

A

58

X
M

I

1

2

I
I
I

1

2

2

5

1

5

2

6

I

:
I

O,X

78

LSL

Disp X

68

Number
of CPU
cycles

I

38

LSL

Byte 3

Number
of
bytes

M

I
I
I

D

I
I
I
I
I
I

I

Example

II

013A 38 FF
013C 38 FF
013E 38 FF

LSL
LSL
LSL

WORK
WORK
WORK

** t4UL TI PL Y

X8

**

~HITACHI
73

Shift & Rotation
LSR
LSR (Logical Shift Right)

I

I

II

Format

LSR Q
LSR A
LSR X

I

II

.
bo

b7

I

Not affected.
Not affected.
Reset.
Set if the result is "0"; otherwise
reset.
C: Set if the least significant bit of
ACCA, IX, or memory is "1" before
execution of an instruction;
otherwise reset.

I I I I I I I 1->0

~I

II

H:
I:
N:
Z:

Operation

0

Condition Codes

Description

I

Shifts the contents of ACCA, IX or M I-bit to the right. The bit 7 is
loaded with "0". The carry bit C is loaded with the least significant
bit of ACCA, IX or M.
Addressing Mode and Number of CPU Cycles
Addressing
Mode
ACCUMULATOR

Mnemonic

,
,,
I

LSR

INDEX REG.
DIRECT
INDEXED a BYTE
OFFSET
INDEXED 1 BYTE
OFFSET

Operand
type

Instruction code
Byte 1 :I Byte 2

A

44

LSR
LSR

X
M

54
34

LSR

O,X

74

LSR

Disp,X

64

,
,,
,,

1

I
I

M

,I

,,

D

,
I

,

,
,,

I

I

Example

0140
0142
0144
0146

I

II
34
34
34
34

FF
FF
FF
FF

LSR
LSR
LSR
LSR

WORK
WORK
WORK
WORK

$
74

,
:,
,
,,,

I

,I

Byte 3

I

Number
of
bytes

** DIVIDE / 16 **

HITACHI

Number
of CPU
cycles
2

1

2

2

5

1

5

2

6

Arithmetic Operation
NEG
NEG (NEGate)

I

Format

I

1/

NEG Q
NEG A
NEG X

I

Operation

II

Description

1/

H: Not affected.
I: Not affected.
N: Set i f the most significant bit of
the result is "1"; otherwise reset.
Z: Set i f the result is "0"; otherwise
reset.
C: Set i f a borrow occurs; otherwise
reset. Set if the contents of
ACCA, IX or Memory are other than

IX + (IX)=OO-(IX)
or
ACCA + (ACCA)=OO-(ACCA)
or
M+ (M)=OO-(M)

I

Condition Codes

"0 11 •

II

Replaces the contents of ACCA, IX or M with its two's complement, and
stores ACCA or IX contents into M contents. Note that $80 (-128) is
unaffected.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

,
Mnemonic

I
I
I
I

Operand
type

Byte 1 :I Byte 2

NEG

I
I

INDEX REG.

NEG

I
I

DIRECT

NEG

,I

X
M

50
30

NEG

,,

0 X

70

: Disp ,X

60

ACCUMULATOR

INDEXED 0 BYTE
OFFSET
INDEXED 1 BYTE
OFFSET

A

Example

0148
014A
014C
0140

40

I

I

NEG

,,I

II
A1 81
24 44
40
20 14

*

,I

,,
,
:
,
,,

I

Byte 3

Number
of
bytes
1

I

M

I

D

Number
of CPU
cycles
2

1

2

2

5

1

5

2

6

I
I

,

,

I

I

,

I
I

I

I

Instruction code

CMP
BCC
NEG
BRA

CHECK RANGE (RELATIVE ADDRESSING)
#129
CHECK RANGE
BERROR
*OFFSET BRANCH ERROR
A
SET

*
~HITACHI
75

Unconditional Branch
NOP
NOP (No OPeration)

I

Format

I

II

Condition Codes

II

Not affected.

NOP

I

Operation

I

Description

II

IJ

This is a single-byte instruction which only causes the program
counter to be increased. Other registers are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

"

Mnemonic

I
I
I

I

IMPLIED

NOP

I
I

Operand
type

Instruction code
Byte 1 ,: Byte 2
9D

I

I

I
I

,I

I
I
I

,

I
I

I

I

I
I

I

,

,

I

I

,

I

I

Example

II

014F 9D
0150 9D
0151 9D
0152 9D
0153 9D
0154 90

,,
,
,,
,

,I

I

,
I

I

NOP
NOP
NOP
NOP
NOP
NOP

~HITACHI
76

I

I
I
I

I
I
I

Byte 3

Number
of
bytes
1

,
I

I
I

,
I

,
I

,
I
I

:
,,I

,

I

I

** DELAY **

Number
of CPU
cycles
1

Logical Operation
ORA
ORA (inclusive OR)

I

Format

I

II

ACCA

I

IJ

Operation

IJ

R: Not affected.
I: Not affected.
N: Set i f the most significant bit of
the result is "I"; otherwise reset.
Z: Set if all the bits of the result
are "0"; otherwise reset.
C: Not affected.

ORA

I

Condition Codes

(ACCA)v(M)

+

Description

II

Performs logical OR between ACCA contents and M contents, and stores
the result into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic :I Operand
I
type
I

IMMEDIATE

ORA

I
I
I

Byte 3

Number
of CPU
cycles

AA

,I

Imm

2

2

M

BA

M

2

3

CA
FA

,,
,,

3

4

1

3

2
3

4

ORA

I

EXTENDED

ORA
ORA

,I M
O,X

ORA
ORA

Byte 1 :I Byte 2

Number
of
bytes

ffImm

DIRECT
iNDEXED U BYTE
OFFSET
INDEXED 1. llYTll
OFFSET
INDEXED 2 BYTE
OFFSET

Instruction code

Disp X
Disp,X

EA
DA

I

,

MH

ML

,I

,
I

D
DR

I
I

,
,,

DL

5

I

I

Example

II

0155 25 06
0157
0157 A6 14
0159 BA 03
015B B7 03
0150

*

ADCN

SKIP

BCS

SKIP

EQU
LOA
ORA
STA
EQU

*

#$14
CNTRL
CNTRL

** ADDITION CONTROL BIT **
0001 0100

*
~HITACHI
77

Shift & Rotation
ROL
ROL (ROtate Left)

I

Format

I

II

H:

ROL Q
ROL A
ROL X

I

I:
N:

•
b.

I

Z:

II

Operation

G~I

Condition Codes

C:

I I I I I I I I~@]

Ir

Not affected.
Not affected.
Set if the most significant bit of
the result is "1"; otherwise reset.
Set of all the bits of the result
are "0"; otherwise reset.
Set if the ACCA, IX, or the most
significant bit of the memory is
"1", before execution of an
instruction; otherwise reset.

bo

Description

II

Shifts the contents of ACCA, IX or M 1-bit to the left. The bit 0 is
loaded with the carry bit C, while the carry bit C is loaded with the
most significant bit of ACCA, IX or M.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Operand
type

Mnemonic

ACCUMULATOR

ROL

A

INDEX REG.
DIRECT

ROL
ROL

X
M

ROL
ROL

INDEXED U BYTE
OFFSET
INDEXED 1 BYTE
OFFSET

Instruction code
Byte 1 I: Byte 2

49

Byte 3

I
I
I
I

,

59
39

:

a,x

79

I
I

Disp X

69

I

I
I

M
D

Number
of
bytes ,_

Number
of CPU
cycles

1

2

1

2

2

5

1

5

2

6

I
I
I
I
I
I

I

Example

110150 98
015E
015E 39 03
0160 25 05
0162 90
0163 90
0164 90
0165 20 F7

*

CLC
REPEAT EQU
ROL
BCS
NOP
NOP
NOP
BRA

** REPEAT ACTION FOLLOWING CNTRL **
*

CN1RL
ACTION

REPEAT

~HITACHI
78

ACTION & REPEAT OR ESCAPE

*
** OELAY **
*

Shift & Rotation
ROR
ROR (ROtate Right)

I

Format

I

II

ROR Q
ROR A
ROR X

I

•

~1
b1

I

II

H: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result is "1"; otherwise reset.
Z: Set if all the bits of the result
are "0"; otherwise reset.
C: Set if the ACCA, IX, or the least
significant bit of Memory is "1";
otherwise reset.

Ij

Operation

Condition Codes

I I I I I I I I-@]
bo

Description

I

Shifts the contents of ACCA, IX or M one bit to the right. The bit 7 is
loaded with the carry bit C, while the bit a is loaded with the carry bit
C.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

ACCUMULATOR

ROR

INDEX REG.
DIRECT
INDEXED u BYTE
OFESET
INDEXED 1 BYTE
OFFSET

Instruction code

Operand
type

Byte 1 :I Byte 2

A

46

ROR
ROR

X
M

56
36

ROR

O,X

76

Disp.X

ROR

66

Byte 3

I

:

M

I
I
I
I

Number
of CPU
cycles

1

I
I
I
I
I

Number
of
bytes

D

2

1

2

2

5

1

5

2

6

I
I
I
I
I
I

I

Example

II

0167

(

0168
016A
0l6C
0160
016E
016F

** REPEAT ACTION FOLLOWING CNTRL **

*
98
0168
36 03
25 05
90
90
90
20 F7

REPTl

CLC
EQU
ROR
BCS
NOP
NOP
NOP
BRA

*

CNTRL
ACTN1

REPTl

$

ACTION & REPEAT OR ESCAPE
*
** Oi:LAY **
*

HITACHI
79

Stack Pointer Operation
RSP
RSP (Reset Stack Pointer)

I Format

I

IJ

Condition Codes

RSP

I

Not affected.

II

Operation
SP

I

Ir

+-

$FF

Description

II

Resets the stack pointer to the top ($FF) of the stack.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMPLIED

I

Mnemonic: Operand
type
I

Byte 1 :I Byte 2

I
I

I

I

I
I

I

RSP

Instruction code

9C

I

I
I
I

I
I
I

I
I

I
I

I

I
I

I

0200
0201
0202
0205

I
I

I

I
I

I

I

I

I
I

I

I

I

:
I
I
I
I

I
I

1\
9B
9C
CD 06FO
9A

SEI
RSP
JSR
CLI

SYSINZ

~HITACHI
80

I

I
I

I

1

I

I

I

I
I

Example

I
I

I

I
I

I

I
I
I
I

I

Byte 3

Number
of
bytes

INTERRUPT DISABLE
RESET STACK POINTER
SYSTEM INITIALIZE
INTERRUPT ENABLE

Number
of CPU
cycles
2

Interrupt Control
RTI
RTI (ReTurn from Interrupt)

I

I

II

Format

Operation
SP
SP
SP
SP
SP

I

-+-+-+-+-+-

II

Recovers the state saved
onto the stack.

RTI

I

Condition Codes

II

(SP)+OOOl,
(SP)+OOOl,
(SP)+OOOl,
(SP)+OOOl,
(SP)+OOOl,

Description

CCR
ACCA
IX
PCR
PCL

-+-+-+-+-+-

(SP)
(SP)
(SP)
(SP)
(SP)

I

Sets the stack contents indicated by SP to CCR, ACCA, IX, PCR, or PCL
increasing SP by "1". Note that I = o when the interrupt mask bit
of CCR saved onto the stack is "0".
Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMPLIED

Mnemonic

Operand
type

RTI

Instruction code
Byte 1 I: Byte 2
80

I
I

Byte 3

Number
of
bytes
1

Number
of CPU
cycles
8

I
I
I
I

:
I
I
I
I
I
I
I
I
I
I

I

Example

II
020C CD 0345

020F
0211
0214
0216

B7 10
CO 0400
B7 11
80

JSR
STA
JSR
STA
RTI

KEYSCN
INKEY
EXSWIN
INSW

$

KEY INPUT
STORE KEY CODE
INPUT EXTERNAL SW
STORE SW CONDITION
RETURN TO INTERRUPT

HITACHI
81

Subroutine Control
RTS
RTS (ReTurn from Subroutine)

I

I

II

Format

Condition Codes

RTS

I

Not affected.

II

Operation
SP
SP

I

II

++-

(SP)+OOOl, PCR
{SP)+OOOl, PCL

Description

++-

(SP)
(SP)

II

Increases SP by "1" and sets the address contents indicated by SP to
more significant bits (6-bits) of PC. Increases SP with "1" again,
and sets the address contents specified by SP to less significant bits
(8-bits) of PC.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

,,
Mnemonic , Operand
I
type
I

IMPLIED

RTS

I
I

Instruction code
Byte 1 ,: Byte 2
I
81 ,

,,
,
,,

,
,,
I

,
,
,
,

,
,

1

I

I

I

I

I
I

I

,

,
,,

,I

II
0171
0173
0176
0178
0179

B7 FF
C6 0500
B7 50
98
81

STA
LOA
STA
CLC
RTS

WORK
EXVALS
RESULT

RETURN CODE SET : OK

*

*
~HITACHI
82

Byte 3

I

I

Example

I
I
I
I

0

I
I

I

I
I

Number
of
bytes

Number
of CPU
cycles
5

Arithmetic Operation
SBC
SBC (SuBtract with Carry)

I

I

II

Format

ACCA

I

II

Operation

+

(ACCA)-(M)-(C)

Description

II

H: Not affected.
I: Not affected.
N: Set if the most significant bit of
the result is "1"; otherwise reset.
Z: Set i f the result is "0"; otherwise
reset.
C: Set if the absolute value of the
contents of memory plus the carry
bit C is greater than the absolute
value of the contents of ACCA;
otherwise reset.

SBC P

I

Condition Codes

IJ

Subtracts the contents of M and the carry bit C from that of ACCA,
and stores the result into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 :I Byte 2

I
I

I

I
I

IMMEDIATE

SBC

IIImm

A2

DIRECT

SBC

M

B2

EXTENDED

SBC
SBC

M
O,X

C2
F2

SBC
SBC

Disp.X
Disp,X

E2
D2

I

I
I
I

Imm

Byte 3

M

Number
of
bytes

Number
of CPU
cycles

2

2

2

3

3
1

3

2
3

5

I

INDEXED U BYTE
OFFSET
INDEXED .L BYTE
OFFSET
INDEXED L BYTE
OFFSET

:

MH

ML

I
I
I
I

I
I

D
DH

DL

4
4

I

I
I
I

I

Example

II
017A
017C
017F
0182
0184
0187

B6
CO
C7
B6
C2
C7

11
0501
0501
10
0500
0500

*
*
*

(VAll, VALl+l)-(EXVAL5, EXVAL5+1)
=(EXVAL5, EXVAL5+1)
LDA
SUB
STA
LDA
SBC
STA

'VALl+l
EXVAL5+1
EXVAL5+1
VAll
EXVAL5
EXVAL5

*
*
*
*
*
*

~HITACHI
83
---~---

-------------

Bit Control
SEC
SEC (SEt Carry)

I

Format

I

1/

Operation
C bit

I

+-

1/

H: Not affected.
I: Not affected.
N: Not affected.
Z: Not affected.
C: Set.

SEC

I

Condition Codes

1/
1

Description

II

Sets the carry bit C in the condition code register.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMPLIED

I

Mnemonic: Operand
,I type
SEC

,

Instruction code
Byte 1

Byte 2

99

"

Byte 3

Number
of
bytes
1

,
I

,,,
,
I

I
I

,,
I
I
I

I
I
I

I

Example

018A
018C
018E
018F

II
27 F8
B7 50
99
81

BEQ
STA
SEC
RTS

CHK84
RESULT

*
*
$HITACHI
84

RETURN CODE SET : NG

Number
of CPU
cycles
1

Bit Control
SEI
SEI (SEt Interrupt mask)

I

I

II

Format

+

I:
N:
Z:
C:

II

Operation

I bit

I

II

H: Not affected.

SEI

I

Condition Codes

Set.
Not affected.
Not affected.
Not affected.

1

Description

I

Sets the interrupt mask bit I in the condition code register. If this
bit is set, interrupt from peripheral equipment is disabled until the
interrupt mask bit is cleared.
Addressing Mode and Number of CPU Cycles
Addressing
Mode

··

Mnemonic • Operand
I
type
I

IMPLIED

SEI

I
I

Instruction code
Byte 1 : Byte 2

I
I

I

I
I
I

9B

I

·
·
····
·
I
I

1

2

I

I
I

I

I

,
I

·
··

I

I

I

Example

Byte 3

Number
of CPU
cycles

I

I
I

I

·
·
·,,
·
·,

Number
of
bytes

II
0206
0207
0208
020B

9B
9C
CD 06FO
9A

SEI
RSP
JSR
CLI

SYSINZ

INTERRUPT DISABLE
RESET STACK POINTER
SYSTEM INITIALIZE
INTERRUPT ENABLE

~HITACHI
85

Load & Store
STA
STA (STore Accumulator)

I

Format

I

II
II

Operation

II

R: Not affected.
I: Not affected.
N: Set if the most significant bit of
ACCA is "1"; otherwise reset.
Z: Set if the contents of ACCA are "0";
otherwise reset.
C: Not affected.

STA P

I

Condition Codes

M +- (ACCA)

I

Description

IJ

Stores the ACCA contents into M. The ACCA contents are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

I
I

I
I

Operand
type

I

DIRECT

STA

EXTENDED
INDEXED U BYTE
OFFSET
INDEXED .l BYTE
OFFSET
iNDEXED L JUTI'
OFFSET

I

M

1

Instruction code
Byte 1 :I Byte 2
B7

STA

M

C7

STA

oX

F7

STA
STA

DisD X
Disp X

E7
D7

1
I
I
I
I

Example

II

0190
0192
0194
0196
0197
0199

I
I
I

I

1
I

I
I

1

I

I

I

I

I
I

I

10
FF
50
FF
0500

LDA
STA
LDA
STA
LDA
STA

ML

1

I
I
I

B6
B7
B6
F7
A6
D7

3

3

4

1

4

2

4

3

5

I

D
DR

I

I

2

I

1

I
I

~HITACHI
86

MH

I

I

Byte 3

I
I

Number
of CPU
cycles

I

,I

I

I

M

I
I

Number
of
bytes

I
I

I
I

VAll
WORK
RESULT
O,X
#$FF
EXVAL5,X

DL

Power Control
STOP
STOP (STOP)

I

Format

I

U

Condition Codes

STOP

II

Not affected.

I

Operation

I

Description

II

I

Enters into the STOP mode by STOP instruction
(For details, refer to STOP MODE in "2.9. Low
Power Consumption Mode".)
Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMPLIED

Mnemonic
STOP

Operand
type

Instruction code
Byte 1 :I Byte 2

I
I

I

I
I

8E

I

Byte 3

Number
of
bytes
1

Number
of CPU
cycles
4

I
I
0

I

!
I
0

I
I

I
I
I

I
I
I

I

I

I

Example

"
~HITACHI
87

Load & Store
STX
STX (STore indeX register)

I

Ij

Format

I
II

Operation

II

R: Not affected.
I: Not affected.
N: Set if the most significant bit
of IX is "1"; otherwise reset.
Z: Set if the contents of IX are "0";
otherwise reset.
C: Not affected.

STX P

I

Condition Codes

M To (IX)

I

Description

II

Stores the IX contents into memory.

IX contents are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
DIRECT
EXTENDED

OFF~F.T

'L.

Operand
type

STX
STX

INDEXED u ByTE
OFFSET
INDEXED 1 BYTE
INDEXED
OFFSET

Mnemonic

llYl'1l

M
M

Instruction code
Byte 1 :I Byte 2

I
I

I

I
I

BF
CF

I
I
I

,

M
MH

I

STX
STX

O,X
Disp,X

STX

Disp X

FF
EF
DF

I
I
I

I

I
I
I

ML

I
I

:
I

Byte 3

D
DR

DL

I
I
I

I
I
I

I

Example

II
019C
019E
01AO
OlA2
01A3
01A5

BE
BF
BE
FF
AE
OF

10
FF
50
FF
0500

LOX
STX
LOX
STX
LOX
STX

~HITACHI
88

VAll
WORK
RESULT
O,X
#$FF
EXVAL5,X

Number
of
bytes

Number
of CPU
cycles

2

3

3

4

1

4

2

4

3

5

Arithmetic Operation
SUB
SUB (SUBtract)

I

I

II

Format

ACCA

I

II

Operation

+

(ACCA)-(M)

Description

II

R: Not affected:
I: Not affected.
N: Set if the most significant bit of
the result is "1"; otherwise reset.
Z: Set if the contents of the result
are "0"; otherwise reset.
C: Set if the absolute value of the
contents of memory is greater than
the absolute value of the contents
of ACCA; otherwise reset.

SUB P

I

Condition Codes

I

Subtracts M contents from ACCA contents, and stores the result
into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

IMMEDIATE

SUB

DIRECT

SUB

EXTENDED

SUB

INDEXED U BYTE
OFFSET
INDEXED .L BYTE
OFFSET
INDEXED 2 BYTE
OFFSET

Operand
type
IIImm

Instruction code
Byte 1 :I Byte 2
AO

M

BO

M

CO

SUB
SUB

O,X
Disp,X

FO
EO

SUB

Disp,X

DO

I
I
I
I

··

Byte 3

2

2

M

2

3

MH

ML

I
I

I
I

Number
of CPU
cycles

Imm

I

I
I

Number
of
bytes

D
DR

DL

3

4

1
2

3

3

5

4

I

I
I
I

I

Example

II
OlAS B6 10
OlAA BO FF
OlAe B7 50

VAll
WORK
RESULT

LOA
SUB
STA

$

(VAL1)-(WORK)=(RESULT)

HITACHI
89

Interrupt Control
SWI
SWI (SoftWare Interrupt)

I Format II

I
II PC +- (PC)+OOOI

Operation

Map+- (PCL) ,
SP +Msp +- (PCH) ,
SP +Msp +- (IX),
SP +Map+- (ACCA), SP +Msp +- (CCR) ,
SP +I bit +- 1
PC +- (SWI interrUPt

I

Description

II

H: Not affected.
I: Set.
N: Not affected.
Z: Not affected.
C: Not affected.

SWI

I

Condition Codes

(SP)-OOOI
(SP)-OOOI
(SP)-OOOI
(SP)-OOOI
(SP)-OOOI
vector address)

II

All the registers other than the stack pointer (SP) are pushed onto
the stack. The interrupt mask bit is then set. Performs vectoring
to the address indicated by the contents of the SWI interrupt vector
address.
Addressing Mode and Number of
Addressing
Mode
IMPLIED

Mnemonic

Operand
type

SWI

Cycles

Instruction code
Byte 1

t

Byte 2

Byte 3

Number
of
bytes
1

83

t
I
I
I
I
I

[

Example

OlOC
01DE
OlEO
01E2
01E4
01E6

A6
87
A6
87
A6
83

II

FF
36
3F
35
03

#$FF
TIMER+l
#$3F
TIMER
#3

LDA
STA
LDA
STA
LDA
SWI

$
90

HITACHI

*
* TIMER COUNTER SET
*
*

TIr4ER CODE SET
MONITOR SERVICE CALL

Number
of CPU
cycles
10

Transfer
TAX
TAX (Transfer Accumulator to indeX register)

I

I

II

Format

Condition Codes

TAX

I

I

Not affected.

II

Operation
IX

+-

II

(ACCA)

Description

I

Transfers the ACCA contents to IX.

The ACCA contents are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

I
I
I
I

Operand
type

I

IMPLIED

TAX

Instruction code
Byte 1 i Byte 2
97

I

2

I

I
I
I
I

I
I

I

I
I

I
I

I

I

I
I

I

I

OlAE
OlAF
OlBl
01B3
01B5

1

I

:

I

Example

I

Number
of CPU
cycles

I
I
I

I

I

Byte 3

I

I
I

Number
of
bytes

I

I

I

I
I

I
I

,
I

I
I

II
97
A6 04
BB 50
B7 50
9F

TAX
LDA
ADD
STA
TXA

#4
RESULT
RESULT

SAVE ACCUMULATOR

*
** ADD (RESULT+4)
*

REVIVE ACCUMULATOR

~HITACHI
91

Comparison & Test
TST
TST (TeST)

I

Format

I

IJ

TST Q
TST A
TST X

I

(IX)

-

00
or
(ACCA) - 00
or
(M) - 00

I

Description

If

H: Not affected.
I: Not affected.
N: Set if the most significant bit of
ACCA, IX or M is "1"; otherwise
reset.
Z: Set if the contents of ACCA, IX or
M are "0"; otherwise reset.
C: Not affected.

II

Operation

Condition Codes

I

Sets Nand Z bits of the condition code register according to the
contents of ACCA, IX or M.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

I
I
I

I
I

ACCUMULATOR
INDEX REG.

TST
TST

I
I

DIRECT

TST

I

INDEXED U BYTE
OFFSET
INDEXED .L BYTE
OFFSET

TST

Operand
type

I

I

I
I
I
I

Instruction code
Byte 1 : Byte 2
I

4D
5D

A
X

TST

I
I

,

7D

I

: Disp.X

6D

I
I

I

I

I

I

I
I

OlBE 3D 03
OlCO 27 18

2

*

2

4
4

2

5

CNTRL
INITOO

CNTRL=$OO

TST
BMI

WORK
MINSOO

WORK=(lXXX XXXX)

~HITACHI

2

1

TST
BEQ

*

92

D

1
1

I

I

01C2 3D FF
01C4 2B 28

M

I

Number
of CPU
cycles

I

I

II

I
I
I

3D

I

Example

I

M

I
I

I

I

O,X

I

Byte 3

Number
of
bytes

Transfer
TXA
TXA (Transfer indeX register to Accumulator)

I

Format

I

II

Condition Codes

TXA

I

I

II

Not affected.

Operation

II

ACCA

(IX)

+-

]

Description

Transfers the IX contents to ACCA.

IX contents are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

IMPLIED

Operand
type

TXA

Instruction code
Byte 1 :I Byte 2

I
I

I

I

9F

I
I
I

,

Byte 3

Number
of
bytes

I

I
I

1

Number
of CPU
cycles
2

I
I

I

:
I
I
I
I

I
I
I

I
I
I

I

Example

"

01B6
01B7
01B9
01BB
01BO

97
A6 04
BB 50
B7 50
9F

TAX
LOA
ADD
STA
TXA

#4
RESULT
RESULT

SAVE ACCUMULATOR

*
** ADD (RESULT+4)
*REVIVE ACCUMULATOR

~HITACHI
93

Power Control
WAIT
WAIT (WAIT)

I

Format

I

II

Condition Codes

WAIT

Ij

Not affected.

I

Operation

I

Description

II

I

Enters into WAIT mode by WAIT instruction
(Refer to WAIT MODE in "2.9 Low Power Consumption Mode" for details).

Addressing Mode and Number of CPU Cycles
Addressing
Mode
IMPLIED

Mnemonic
WAIT

Operand
type

Instruction code
Byte 1 :I Byte 2

I
I

,I

I
I
I
I
I
I
I
I

8F

,,I
,,
,
,I
,,

,
,,
,,
I

I

Example

II

~HITACHI
94

,
,,
I

I

,,
,
,,

,,,
I

Byte 3

Number
of
bytes
1

Number
of CPU
cycles
4

1.7

BIL/BIH Instruction Precaution
(1)

Execute Instruction after the INT voltage level has stabilized above
V,H of below V,L •

(2)

INT voltage level need to be stabilized while BIL/BIH Instruction
Execution.

There may be a malfunction by glitch on control signal if BIL/BIH Instruction
Execution has exercised in unstabilized INT signal level.

INT

VIH

T

A

v_~ -:-~~t.~:~------------~~~\:---

__________ __

--<

BIL/BIH

>--0--< BIL/BIH)

0

Avoid BIL/BIH Insruction Excution.

~HITACHI
95

~HITACHI
96

HD630S/HD63LOS SERIES HANDBOOK

Section Three

• HD630S UO
• HD630S VO
• HD6370S VO

User's Manual

~HITACHI
97

~HITACHI
98

Section 3
HD6305UO, HD6305VO, HD63705VO User's Manual
Table of Contents
Page
1.

OVERViEW ................................................... .

101

1.1

Features of HD6305UO, HD6305VO, HD63705VO .................. .

101

1.2

Block Diagram .............................................. .

102

1.3

Terminal Functions .........................•.................

103

INTERNAL HARDWARE AND OPERATIONS ........................ .

107

2.1

Memory ................................................... .

107

2.2

Registers .................................................. .

108

2.3

Timer ..................................................... .

110

2.4

Serial Communication Interface (SCI) ........................... .

113

2.5

Reset ..................................................... .

118

2.6

Internal Oscillator Options ..................................... .

119

2.7

Interrupts .................................................. .

120

2.8

Input/Output. ............................................... .

124

2.9

Low Power Consumption Mode ................................. .

126

2.10

EPROM Mode (HD63705VO) ................................... .

132

APPLICATION AND PRECAUTIONS ............................... .

137

3.1

Watch-Dog Timer ............................................ .

137

3.2

Auto Reset Circuit ........................................... .

139

3.3

Manual Reset Circuit ......................................... .

140

3.4

AID Converter Circuit (1) ... High Speed ......................... .

141

3.5

AID Converter Circuit (2) ... Low Speed .......................... .

143

3.6

Precaution; - Board Design of Oscillation Circuit ................... .

144

3.7

Precaution; - Sending/Receiving Program of Serial Data ............ .

145

3.8

Precaution; - WAIT/STOP Instructions Program .................... .

145

4.

PIN ARRANGEMENT AND DIMENSIONAL OUTLINE ................. .

146

5.

ELECTRICAL CHARACTERISTICS ................................ .

149

5.1

Electrical Characteristics for HD6305UO, HD6305VO ............... .

149

5.2

Electrical Characteristics for HD63705VO ........................ .

152

2.

3.

~HITACHI
99
-----

~-,---------

6.

PROGRAMMABLE ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

158

6.1

ProgrammingNerification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

158

6.2

Erasure (MCU with a window). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

159

6.3

Application Notes ............................................

160

ROM CODE ORDER METHOD.....................................

164

APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

164

7.

I.

Design Prodcedures and Support Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

164

SINGLE CHIP MICROCOMPUTER ROM ORDERING PROCEDURE .........

166

HD6305UO, HD6305VO ORDERING SPECIFICATIONS. . . . . . . . . . . . . . . . . . . . .

168

~HITACHI
100

1.
1.1

OVERVIEW
Features of HD6305UO, HD6305VO, HD63705VO
Hitachi's HD6305UO, HD6305VO are CMOS 8-bit single-chip microcomputers containing CPU, RAM, I/O on a single chip.
Features of this series are as follows;
(1) Powerful Bit Manipulation Instructions
Dew to upward compatibility with HD6805 family instruction set,
powerful bit manipulation instructions are provided so that bit set,

I

bit reset, bit test, and branch would be executed with a single
instruction.

These bit manipulation instructions are available to

I/O and internal RAM as well.
(2) Low Power Consumption
To exploit the CMOS process technology fully, three low power
consumption modes; STOP, WAIT and STANDBY; are incorporated.
Table 1-1
Type No.

DP-40,FP-54,CP-44

ROM (k byte)

DC-40
4

4

128

192

31

31

31

external

2

2

2

soft

1

1

1

timer

2

2

2

serial

1

1

1

8-bit Timer

1

1

1

15-bit Timer

1

1

1

RAM (byte)

I/O Port

Interrupt

Timer
SCI

1 (clock synchronous)
lMHz

Operating
Voltage

DP-40,FP-54,CP-44

HD63705VO

2

Memory

(SV ± 10%)

HD6305VO

HD6305UO

Package

Speed Version

Features of HD6305UO, HD6305VO and HD63705VO

1 (clock synchronous)

192

1

HD6305VO

HD63705VO

HD63A05UO

HD63A05VO

HD637AOSVO

HD63B05UO

HD63B05VO

HD637BOSVO

3 '" 6.0V

4.5 '" S.SV

HD6305UO

1.5MHz
2MHz
0.1 '" 0.5 MHz

3 '" 6.0V

~HITACHI
101

Table 1-2

Feature of EPROM ON CHIP TYPE FAMILY

Type
Package

HD63705VOC
DC-40,
(with window)

Equivalent Device

HD6305UO, HD6305VO

Process

CMOS

Erasure

possible

r

HD63705VO is fully compatible with HD6305VO.
It is possible to program with EPROM programmers that are
commercially available (e.g 27256 type) since HD63705VO contains
4k bytes of EPROM. And this makes it possible to use them for
debugging as well as evaluating the program.

1.2

Block Diagram
A block diagram of HD6305UO, HD6305VO is given in Fig. 1-1,
HD63705V in Fig. 1-2, respectively.
XTAL EXTAL

RES

NUM

iiiiT SfBv"

•
TIMER

Port A
I/O
Terminals

B

Index
Register

Condition Code
RegisterCCR
Stack
Pointer SP

D./INT,
Ds/CK
D./Rx
D,/Tx
0,

CPU
Control

X

0,

CPU

D.

. Program
Counter

Port B
I/O
Terminals

"High"PCH

ALU

Serial
Control

K~~~_R;eg:ist:e~ri

Program
Counter

~~~~

"Low" PCL

Serial
Data
Registar

Register

Port C
I/O
Terminals

"HD8306UO ROM 2048xB, RAM 128xB
"HD8301iVO ROM 4OII8xB, RAM 192x8

Fig, 1-1 HD6305UO, HD6305VO Block Diagram

•
102

HITACHI

Port 0
I/O
Terminals

r-=EPROMM_

~

rMCUrMo_de_.L-'-,--:;::-=-,

Vpp/TIMER

7 Pre..810,

I

.

Port A

1/0Pini

8

6::;':;~, I/L .....

Time, Control

IV-V
8

A

Regi ...,

X

I/0Pini

B.
B,
B,
B,

.

5

Reg;"·'CCA

6

Pointer Sp

6

"High"PCH
Program

1/0Pini

H
~ ei'r
~C[

CPU

~':~.:=

EAutB..

EA1O/B,
B.
EA,/S,

porte

.2

Condition Code

Stack

Port B

CPU
Control

Index

,8

ALU

I

\r--v

II

4096 • 8
L-_E_P_R_O_M__~

Fig. 1-2

t/OPins

1m

Serial

"Low"PCL

11

f::F' I
1-8'

PortO

Control

~:~~~

Register

Register

IL

EA./C,
EA,/C,
EA,/C,
EA,/C J
EA./C.
EA./C.
EA./C.
EA,/C,

0 .liNT1
~r-D. ICK
0; ../Rx
I:.i
~8 ,IT. eE
011'
I
0.0:

",A.~__""""l-_R_eg_i"_._'-I ~;:I

Counter

8

EA,

.

Accumulator

EO./A
EO,/A ,
EO,/A,
EO,/A)
EO .. /A.
EO,/A,
EO. lA,
EO.,/A7

II

I

I

192 • 8
~___R_A_M__~

HD6370SVO Block Diagram

Precaution for using the MCU in the ceramic package with a window
(1)

The data stored in EPROM may be lost or the MCU may be malfunctioned by photocurrent if the MCU is exposed to strong light like
a fluorescent lamp or the sunlight.

Therefore, it is recommended

to cover the window with an opaque label.
(2)

Users should be particularly careful of static charge on the
window, as it affects the MCU function to malfunction the LSI.
The charge will be caused by rubbing the window with plastics or
dry cloths, or touching a charged body on it.

The opaque label

that we recommended in (1) will be effective to distribute the
charge evenly, if it is conductive.
1.3

Terminal Functions
(1) Terminal functions of HD630SUO and HD630SVO are described below.
•

VCC' Vss
Terminals for applying voltage.

VCC provides S.OV±lO%

power supply, while VSS is grounded.
•

INT,

lNT2;

INPUT, INPUT/OUTPUT

Terminals for external interrupt input to HD630SUO and HD630SVO.
Refer to "2.7 Interrupt" for details. INT2 is multiplexed

with the D6'

~HITACHI
103

•

XTAL, EXTAL
Input terminals to the internal clock circuit.

Connect a

crystal oscillator (AT cut, 2.0 "'S.OMHz) or ceramic filter to these
terminals.
•

Refer to "2.6

TIMER; INPUT
An external input terminal for contro1ing event counter.
Refer to "2.3

•

Timer" for details.

Irn'S; INPUT
Resets the MCU.

•

Internal Oscillator Options" for details.

NUM

Refer t6 "2. S Reset" for details.

NUM is not for user application.

It can be used by connect-

ing to VSS'
•

PORT A, B, C, D; INPUT/OUTPUT
31 terminals consist of three S-bit I/O ports (A, B, C) and
one 7-bit I/O port (D).

Each bit of these terminals function as input

or output terminals by programming the Data Direction Register.
Refer to "2.S Input/Output" for details.
D6 of port D is multiplexed with INT2.

\fuen D6 functions as

a port, set MR6 in Miscellaneous Register to "I" in order to mask INT2
interrupt.
•

STBY; INPUT
A terminal for permitting the MCU to enter into the Standby
Mode.

When STBY goes to "Low" level, the oscillation stops and the

MCU enters into the Reset Mode.

Refer to "Standby Mode" in "2.9 Low

Power Consumption Mode" for details.
•

CK (DS); INPUT/OUTPUT
Terminal to transmit or receive SCI clock for serial data transfer.
Refer to "2.4 Serial Communication Interface" for details.

•

Tx (D3); INPUT/OUTPUT
This terminal used to transmit serial data.
Serial Communication Interface" for details.

~HITACHI
104

Refer to "2.4

• Rx

(D4); INPUT/OUTPUT
This terminal is used to receive serial data.

Refer to "2.4

Serial Communication Interface" for details.
(2)

•

The followings describs HD63705VO MCU input and output terminals.

VCC' Vss
These are the power supply inputs.

VCC

5.0V ± 10%, VSS

OV

(ground) •
•

l1f.F/EA9 , INT2; INPUT, INPUT/OUTPUT
The MCU receives an external interrupt through these terminals.
For details, refer to "2.7 Interrupts".
Port D6'

•

INT2 is mUltiplexed with

In the EPROM mode, INT is used as input of EA9.

XTAL, EXTAL
These pins are inputs of the internal oscillator circuit.
Connect crystal (AT cut, 2.0 ",S.O UHz) or ceramic resonator
to them.

Refer to "2.6 Internal Oscillator Options" for using

these inputs.
•

TIMER/Vpp; INPUT
This is an external input to control the internal timer
circuit.

Refer to "2.3 Timer" for details.

In the EPROM mode, this terminal is used when programming EPROM.
The programming voltage Vpp is applied to this terminal.
When the voltage of l2.5V ± 0.3V is applied to this terminal and
CE and OE are set "Low" and "High" respectively, datas are written into
EPROM through Port A (EOO '" E07)'

EPROM addresses are input

through the Port C (EAo '" EA7)' Port B (EAs, EAro '" EAll) and
INT (EA9)'

• m;

•

NUM

INPUT
This is used to reset the MCU.

Refer to "2.5 Reset" for details.

This is not for user application.

Connect this pin to the

VSS in the MCU mode and to the Vce in the EPROM mode.

~HITACHI
105

•

PORT A, B, C, D; INPUT/OUTPUT
These 31 terminals consist of three 8-bit I/O ports (A, B, C)
and a 7-bit I/O port (D).

Each bit of these pins can be programmed

as an input or output by programming the Data Direction Register.
D6 is multiplexed with the INT2'

When using the D6 as a port,

set the INT2 interrupt mask bit in the miscellaneous register to
"1" to prevent the INT2 interrupt.

Refer to "2.8 Input/Output"

for details.
•

STBY; INPUT
This is used to put the MCU into the standby mode.

Setting

this pin to "low" level stops the internal oscillator and resets
the MCU internal state.

Refer to "Standby Mode" in "2.9 Low Power

Consumption Mode" for details.
The followings are input/output pins for serial communication
interface (SCI).

These are multiplexed with 03, 04, or 0S,

Refer to "2.4 Serial Communication Interface" for details.
•

CK (05); INPUT/OUTPUT
This is used to input or output clocks when receiving or
transmitting serial data.

• Rx
•

(04); INPUT/OUTPUT
This is used to receive serial data.

Tx (03); INPUT/OUTPUT
This is used to transmit serial data •

•
106

HITACHI

2.

INTERNAL HARDWARE AND OPERATIONS

2.1

Memory
Fig. 2-1 shows the memory map of HD630SUO, HD630SVO and HD6370SVO.
During the processing of the interrupt, the register contents are
pushed onto the stack in the order shown in Fig. 2-2.

The stack

The low order byte (PCL) of the program counter

pointer decrements.

is stacked first and the high order byte (PCR) of the program, the
index register (X), the accumulator (A) and the condition code
register (CCR) are stacked in that order.

For subroutine calls,

program counter (PCR, PCL) contents are pushed onto the stack.

a

soooo

I/O Ports
Timer

12 7
128

25 5
25 8

0
1
2

SCI

S007F

3

RAM
~0080
(1288ytes)

4
5
6
7

'~OFF

Stack

S 100

\
S17FF

Not Usad
6143
614 4

8
9
10

o •••••• _••

m
1

A
B
C

0

PORT A ODR

PORT BOOR

PORT C ODR
PORT DOOR
Timer Data Reg
T.mer CTRL Reg

MIse Hag

$1800
ROM
(2.048Byte.)

818

POR
PORT
PORT
PORT

Interrupt

Vectors

0
500
1'li0000
I '0 Ports
SOl
Timer
502
SCI
503
63
S003F
504
64
~0040
RAM
505
(192Bytes)
506
Stack
S07
25 5
SOB
25 6
$ ,00
Not Used
509
SOFFF
SOA 409 6
$1000
409 8

I~OFF

2
3

P
PORT B
PORT C
PORT 0

4

PORT A DDR

5
6

PORT BOOR
PORT C ODR

1

7 PORT DOOR
8 Imer Date •
9 TilMr CTRL Reg
10 MIse Heg

Intern.1
EPROM

Not Used

501
502
S03
504
505
S06
507
S06
$09
lOA

51FF4
$1FFF
$2000

18 SCI CTFIL Reg 510 818
0
17 SCI STS "eg $11
18 SCI Oltl Reg $12
I

m

SCI

63

64

2

S003F

3
4

~FF

5
6

~0040
RAM
(192Byt••)

Stack

25 5

25 6

S ,00

Not Used

50FFF
51000

409 6
409 6

7

8
9
10

Intern.1
EPROM

---------

18 SCI CTRL Reg $10
I
SCI STs "10 $11
lB SCI Dill Re9 $12

51FF4

~terruPI

Ictor.

SIFFF
52000

818

o •••• _-_ ••

m
1

~t.rruPt

actors

'2

1838

1838

S3FFF

543 2 1 0

I

C~ndition
n-4 1 1 1 Code
Register n+1

n-3

Accumulator

n+2

n-2

Index Register

n+3

n

MIse .g

51FF4
SIFFF
52000

16
17
18

SCI CTRL AI,
SCI STS
SCI O.t. Reg

83

HD6305VO MCU
Fig. 2-1 Memory Map

n-1 1 1

S04
$06
S06
S07
$08
S09
SOA

Not Used

53F

63

e

PORT A DDR
PORT BOOR
PORT C DDR
PORT DOOR
TUMr .t. "-II
Timer CTRL. ....

$01
502
S03

$10
SII
$12

Not Usod

$7F

7

SOO

Not Used

Not Usod

HD6305UO MCU

PORl A
PORT B
PORTC
PORT 0

(4.096Byt.s)

Not Us.d

Not Usod

S3FFF

1

Timer

Not Used

2

127

$0000

10 Ports

(4.098Bytes)

Not Usad

1638

0

SOO

I

PCW
PCl"

PUlh

53F

S3FFF

HD63705VO MCU

Pull

n+4

n+5

• In a subroutine cell, only PCL and PCH .reltacked.

Fig. 2-2

Sequence of Interrupt Stacking

~HITACHI
107

2.2

Registers
This CPU contains five registers available to the programmer.
They are shown in Fig. 2-3.

0
I Accumulator
0Ilndl!x
Register
0IProgram
Counter
0ISteck

7

I
7
I

A
X

13
PC
13
6 5
I 0101010101011 111
I

SP

Pointer

Condition
I H I I I N I z I C ICod~
1sur

LS9

~~:x"

Zero
Negative
Interrupt
Mask
Half
Carry

Fig. 2-3

(1)

Programming Model

Accumulator (A)
The accumulator is an a-bit general purpose register which
holds operands and results of the arithmetic operations or data
manipulations.

(2)

Index Register (X)
The index register is an a-bit register used for the indexed
addressing mode.

It contains an a-bit value which is added to an

offset to create an effective address.
The index register can also be used for data manipulations
with read-modify-write instructions.
When not performing addressing operations. the register can
be used as a temporary storage area.
(3)

Program Counter (PC)
The program counter is a 14-bit register which contains the
address of the next instruction to be executed.

(4)

Stack Pointer (SP)
The stack pointer is a 14-bit register containing the address
of the next free location of the stack.

~HITACHI
108

Initially, the stack

pointer is set to location $OOFF.

It is decremented as a data is

pushed on to the stack and incremented as data is then pulled out
of the stack.
to 00000011.

The 8 high-order bits of the stack pointer are fixed
During an MCU reset or a reset stack pointer (RSP)

instruction, the pointer is set to location $OOFF.

Subroutines and

interrupts may be nested down to $OOCl, which allows programmers to
use up to 31 levels of subroutine calls and 12 levels of interrupt
responses.
(5)

Condition Code Register (CCR)
The condition code register is a 5-bit register indicating the
results of the instruction just executed.

These bits can be

individually tested by conditional branch instructions.

Each bit

is described in the following paragraphs.
(a)

Half Carry (H)
When set, this bit indicates that a carry occurred between
bit 3 and 4 during an arithmetic operation (ADD, ADC).

(b)

Interrupt (I)
Setting this bit masks all interrupts except for software
ones.

If an interrupt occurs while this bit is set, the interrupt

is latched and is processed as soon as the interrupt bit (I) is
cleared.

(More precisely the interrupt enters the servicing

routine after the instruction next to the CLI is executed.)
(c)

Negative (N)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation is negative.

(Bit 7

in the result is a logical "1".)
(d)

Zero (Z)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation is zero.

(e)

Carry/Borrow (C)
When set, this bit indicates that a carry or borrow occurred
during the last arithmetic operation.

This bit is also affected by

bit test and branch instructions, shifts and rotates.

~HITACHI
109

2.3

Timer
Fig. 2-4 contains a block diagram of the timer.

The 8-bit

counter may be loaded under program control and is decremented towards
zero by the clock input.

When the

~ounter,

that is, the timer data

register (TDR) reaches zero, the timer interrupt request bit (bit 7)
of the timer control register is set.

When recognizing the interrupt

request, the MCU proceeds to store the current CPU state on the stack,
and then fetches the timer vector address from locations $lFF8 and
$lFF9 (or $lFF6 and $lFF7 if in the wait mode) in order to execute the
interrupt service routine.

The timer interrupt can be masked by

setting the interrupt mask bit (bit 6) of the timer control register.
The mask bit (I) of the condition code register can also disable
the timer interrupt.
The clock input to the timer can be from an external source
applied to the TIMER input pin, or it can be the internal E signal
(which is a clock obtained by dividing the oscillator clock by four).
When the E signal is used as the source, it can be gated by an input
applied to the TIMER pin.
The counter start counting down from "$FF" after it reaches zero.
The counter may be monitored at any time by reading the contents of the
timer data register.

This allows a program to determine the length of

the time since the occurrence of a timer interrupt without distarbing
the counter contents.
At reset, the prescaler and counter are initialized to "$7F" and
"$FO", respectively.

The timer interrupt request bit (bit 7) is cleared

and the timer interrupt request mask (bit 6) is set.
The timer interrupt request bit must be cleared by software.

~HITACHI
110

Initialize

IInternal
Clock)

E--+-i

3

....--,----"'T""--..J Timer Interrupt
Write

Fig. 2-4

Read

Timer Block Diagram
Table 2-1

(1)

TCR7

Timer interrupt request

0

Absent

1

Present

TCR6

Timer interrupt mask

o

Enabled

1

Disabled

Timer Control Register (TCR; $0009)
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled by
the timer control register (TCR; $0009).

(Refer to Fig. 2-5).

For the selection of a clock source, anyone of the four modes
(Refer to Table 2-2) can be selected by bits 5 and 4 of the timer
control register (TCR).

' - - - - - - - - - - - - Timer interrupt mask
' - - - - - - - - - - - - - - T i m e r interrupt requllt

Fig. 2-5

Timer Control Register (TCR; $0009)

~HITACHI
111

After reset, the TCR is initialized to E under timer terminal
control (bit 5

= 0,

bit 4

= 1).

If the timer terminal is "1",

the counter starts counting down with "$FO" inunediate1y after reset.
When "1" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (Refer to
Table 2-3).

There are eight different division ratios:

+8, +16, +32, +64 and +128.
mode.

+1, +2, +4,

After reset, the TCR is set to the +1

A timer interrupt is enabled when the timer interrupt mask bit
is "0", and disabled when the bit is "1".

When a timer interrupt

occurs, "1" is set in the timer interrupt request bit.

This bit

can be cleared by writing "0" in that bit.

Table 2-2

Clock Source Selection

TCR

Clock input source

Bit 5

Bit 4

0

0

Internal clock E

0

1

E under timer terminal control

1

0

No clock input (counting stopped)

1

1

Event input from timer terminal

Table 2-3

Prescaler Division Ratio Selection

Bit 2

TCR
Bit 1

Bit 0

0

0

0

H

0

0

1

+2

Prescaler division ratio

0

1

0

+4

0

1

1

+8

1

0

0

+16

1

0

1

+32

1

1

0

+64

1

1

1

+128

~HITACHI
112

2.4

Serial Communication Interface (SCI)
The SCI is used for transferring 8-bit data in serial.

The transfer

clock width ranges from 1 ~s to about 32 ms (with a 4 MHz oscillator),
and sixteen types of transfer clock widths are available.

The SCI

consists of three registers, an octal counter and a prescaler as shown
in Fig. 2-6.

It communicates with CPU through the data bus lines and

with peripherals through bits 3, 4 and 5 of Port D.

The followings

describe the registers and the data transfer operations.

I

SCI Control Registers (SCR; 0010)

E
Transfer
Clock

Generator

Initialize

SCI Status Registers
(SSR :$0011)

Not Used

SCI/TIMER2

Fig. 2-6

(1)

SCI Block Diagram

SCI Control Register (SCR: $0010)
Fig. 2-7 shows SCI Control Register configulation.

Bit 7 (SCR7)
When this bit is set to "1 If, the DDR corresponding to D3 is
set to 1t1 tt and D3 functions as output of SCI data.
the bit is in it ial ized to "0".

After reset,

~HITACHI
113

Bit 6 (SCR6)
When this bit is set to "1", the DDR corresponding to D4 is
set to "0" and D4 functions as input of SCI data. After reset, the
bit is initialized to "0".
Bits 5 and 4 (SCR5, SCR4)
These bits select a clock source.
initialized to "0".
Bits 3

~

0 (SCR3

~

After reset, the bits are

SCRO)

These bits select a transfer clock rate.
are initialized to "0".

Fig. 2-7

After reset, the bits

SCI Control Register

Transfer clock rate
SCR3

SCR2

SCRl

SCRO
4.00 MHz

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

I

I

I

I

1

1

1

1

1
2
4
8

us
us
).1s
us
I

32768 us

0.95
1. 91
3.82
7.64
I

1/32s

SCR7

03 terminal

0

Used as I/O terminal (by DOR).

1

Serial data output (DDR output)

SCR6

D4 terminal

0

Used as I/O terminal (by DDR).

1

Serial data input (DOR input)

~HITACHI
114

4.194 MHz
us
us
us
us

SCRS

SCR4

Clock source

0

0

-

0

1

-

1

0

Internal

Clock output (DDR output)

1

1

External

Clock input (DDR input)

DS terminal
Used as I/O terminal (by DDR).

(2) SCI Data Register (SDR: $0012)
A serial-parallel conversion register used for data transfer.
(3) SCI Status Register (SSR: $0011)

Bit 7 (SSR7)
This is the SCI interrupt request bit which is set on the
completion of transmitting or receiving 8-bit data.

It is cleared

when the MCU is reset or data is written to or read from the SCI
data register with the SCRS

"1".

This bit can also be cleared

by writing "0" into it.
Bit 6(SSR6)
This is the TIMER2 interrupt request bit.

The TIMER2 is also

used as the serial clock generator, and this bit is set on the
every negative edge of the internal transfer clock.
is reset, the bit is cleared.
"0" into it.

When the MCU

It can also be cleared by writing

(Refer to "2.3 Timer" for details).

Bit 5 (SSRS)
This is the SCI interrupt mask bit which can be set or cleared
by software.
masked.

When this bit is "1", the SCI interrupt (SSR7) is

Resetting the MCU sets this bit to "1".

Bit 4 (SSR4)
This is the TIMER2 interrupt mask bit which can be set or
cleared by software.
(SSR6) is masked.

When this bit is "1", the TIMER2 interrupt

Resetting the MCU sets this bit to "1".

Bit 3 (SSR3)
Writing "1" into this bit initializes the prescaler of the
transfer clock generator.

A read of this bit always indicates "0".

~HITACHI
115

Bit 2 tV Bit 0
Not used.
SSR7

SCI Interrupt Request

0

Not Requested
Requested

1

SSR6
1

TlMER2 Interrupt Request
Not Requested
Requested

SSR5

SCI Interrupt Mask

0

0

Interrupt Allowed

1

Interrupt Inhibited

SSR4

TIMER2 Interrupt Mask
Interrupt Allowed
Interrupt Inhibited

0
I

(4)

Transmit Operations
The transfer clock width and the clock source are determined
by setting the corresponding SCI control register bits, and then
D3 and D5 are set to serial data output pin and serial clock
pin respectively.

The transmit data should be moved from the

accumulator or the index register into the SCI data register.
Then, the data moved into the SCI data register is output through
the D3/Tx pin, starting with the LSB, synchronously with the
negative edge of the serial clock. Refer to Fig. 2-8. When
8 bits of data have been transmitted, the bit 7 of the SCI status
register (interrupt request bit) is set on the positive edge of the
last serial clock.

This interrupt request can be masked by setting

bit 5 of the SCI status register.

After completion of the data

transmission, the 8th bit of data (MSB) stays at the D3/Tx pin.
the external clock source is selected, the transfer clock width

If

determined by bit 0 to bit 3 of the SCI control register is ignored
and the D5 / C! pin is set as input.

If the internal clock source is

selected, the D5/CK is set as output and clocks are generated with
the transfer clock width selected by bit 0 to 3 of the SCI control
register.

~HITACHI
116

Fig. 2-8
(S)

SCI Timing

Receive Operations
The transfer clock width and the clock source are determined
by setting the corresponding SCI control register bits, and the D4
pin and the DS pin are set to serial data input pin and serial clock
pin respectively.

Then the receive operation is enabled by dummy-

reading or -writing the SCI data register.
needed after a data is received.
no data is received yet.)

(This procedure is not

It is needed after reset or when

The received data through the D4/Rx pin

is input to the SCI data register synchronously with the positive
edge of the serial clock.

(Refer to Fig. 2-8.)

At completion of 8-bit

data reception, the bit 7 in the SCI status register (interrupt
request bit) is set.

This interrupt request can be masked by set-

ting bit S of the SCI status register.

If the external clock

source is selected, the transfer clock width determined by bit 0 to
bit 3 of the SCI control register is ignored and data is received
synchronously with the clock input through the DS/CK pin.

If the

internal clock source is selected, the DS/CK acts as an output and
clocks are output with the transfer clock selected by bit 0 to
bit 3 of the SCI control register.
(6)

TIMER2
The SCI transfer clock generator functions as a timer.

The

SCI clock selected by bits 3 to 0 of the SCI Control Register (4 VS
to approx -32 ms in 4 MHz operation) is transmitted to bit 6 of the
SCI Status Register, and the timer 2 interrupt request bit is set
at each falling edge of the SCI clock.

Since this interrupt occurs

periodically, Timer2 is available for a reload counter or a timer.
Timer2 is multiplexed with the SCI transfer clock generator.
When using Timer2 independently of the SCI, external clock should
be selected as SCI clock source by setting both SCS and SC4 to "1".
If Internal clock is selected as a SCI clock source, reading

from or writing to the SD! initializes the prescalor of the SCI
tranBf~t clock generator.

~HITACHI
117

 VZI + VFI

Vout

=

Vout

= GND

when Vee < VZI + VFl

Since the voltage VZ2' applied to ZD2, and the ON
level VF2 of Tr2 are constant, even if the Vee changes.
The followings describe the RES signals.

~HITACHI
139

v vee

(Threshold
voltage)

VLM~
~

'Vet x Rt

{

Vout
Vout

Vee when Vee > VZZ + VFZ
GND when Vee < VZZ + VFZ

When the Vee changes, threshold level, VLM is affected
by replacing the Zener diodes ZD 1 and ZD Z•
(iii)

The Auto-reset function will be more stabilized by feeding
back the output signal to the RES pin, tuning finely the
reference voltage, and providing hysteresis with the VLM1
and the VLMZ. (VLM1 is a voltage during the shifting from
operation to resetting, and VLMZ is the voltage in recovering:)

3.3

Manual Reset Circuit
(1)

Purpose
When the Meu is reset by an external switch, it is necessary to
prevent chattering.

The following describes a reset circuit in

which chattering prevention and power-on reset functions are
provided.
(Z)

Basic circuit
Fig. 3-3 shows the basic circuit of manual reset.
Vee

Fig. 3-3 Basic Circuit of Manual Reset

(3)

Operation principle
(i)

Power-on reset
During power-up, the capacitor e will be charged and the
Vin rising time will be delayed by the eR charge time, so
that power-on would reset normally.

~HITACHI
140

v vee

'w

~-r-'t=ut-I---+l
t -

(ii)

ex R

Manual reset
When SW is on, the Vout goes "a" and the MCU is reset. When
SW is off, the capacitor C is charged, so that the rising
time of Vin is delayed by the CR charge time.

Chattering

is prevented by the capacitor C and the Schmidt trigger

HD74LS14.

OFF-,-- ON

- - - - i_ _-

,----

SW

 1.6V

A/D Converter Circuit (1) .•• High Speed
(1)

Purpose
The following describes how to implement a simple AID conversion
(analog-digital conversion) using the resistance radder (R-2R)
system.

(2)

Basic circuit
Microcomputer

Vin + V out
VREF

An.log
Input

VREF- ( On +
21

Q!!:.!
22

+ •.. + ~ +.Q!)x V
2n·l
2n

Vout = 0 : Vin ~ VREF

R
Port
03
R

V: Voltage of the output
"1" of the port

Nec....ry numb.r of
port-Accuracy bit+l

V

2R

Vout· 1 : Vin

> VREF

I--~=----Vin

R
2R

2R
eMOS
H014060

Vout

~

':2:..J
Fig. 3-4

A/D Converter Basic Circuit

Fig. 3-5

Timing Chart

~HITACHI
141

Operation outline

(3)

The follnwings describe the operation outline of 3-bits A/D converter
circuit.
The digital outputs (D 3 • D2 • D1 ) are changed from (1. 1. 1)
to (0. o. 0) at the port. VREF is reduced from 7/8 V to 0

(i)

by every 1/8 V according to Table 3-1.
(ii)

The output Vout ' which is the result of comparison between
the analog input Yin and VREF. is reversed from "0" to "1"
when Yin is greater than VREF as shown in Fig 3-5.

(iii)

The value of (D 3 • D2 • D1 ). when Vout is reversed from "0"
to "1". is a digital value to the analog input Yin'

Table 3-1

Value of VREF

D3

D2

D1

0

0

0

0

0

0

1

0

1

0

1/8 x V
2/8 x V

0

1

1

1
1

0

0

0

1

1

1

0

1

1

1

VREF
Dl to D3 are denoted by "1" or "(I"
V: Voltage of the port output "1"

3/8 x V
4/8 x V
5/8 x V
6/8 x V
7/8 x V

~HITACHI
142

3.5

AID Converter Circuit (2) .•• Low Speed
(1)

Purpose
The following describes the A/D conversion system utilizing time
for charge/discharge to/from the CR circuit.

This conversion

system is available even if the A/D conversion tUne is slow.
(2)

Analog
Input

Basic circuit

Operation amplifier
Microcomputer
HA17902

Vln

n : Count value

R
A
C

Port

Number of
port required

T - T. x n

' - - - - - ' -2
T. : Timer Interval

Fig. 3-6
(3)

AID Converter Basic Circuit

Fig. 3-7

Timing Chart

Operation outline
(i)

Set the output terminal A of the port to "1", discharge the
external condenser C for a sufficiently long period, decline
A from "1" to "0" synchronously with the timer interrupt
and charge C.

(ii)

Check Vout for each timer interrupt and observe the time T
in which Vout declines from "1" to "0" • Vout becomes "0"
when Vin is less than VREF • T is obtained as T=TO x n,
where "n" represents the number of timer interrupts and TO
represents the timer interval.

(iii)

The obtained time T, which is voltage converted, is a digital
value of the analog input Vin'

~HITACHI
143

AID conversion
lubroutlne

":==:r---' __ .. :!'.!'!'!!'!.t.rrupt

3.6

Precautionj- Board Design of Oscillation Circuit
When connecting crystal and ceramic resonator with the XTAL and
EXTAL pins to oscillate, observe the followings in designing the
board.
(1)

Locate crystal, ceramic resonator, and load capacity Cl and C2
as near the LSI as possible.

(Induction of noise from outside

to the XTAL and EXTAL pins may cause trouble in oscillation.)
(2)

Wire the signal lines to the neighbouring XTAL and EXTAL pins as
far apart as possible.

(3)

Board design of situating signal lines or power supply lines
near the oscillator circuit as shown in Fig. 3-9, should not be
used because of trouble in oscillation by induction. The
resistor between the XTAL and EXTAL, and pins close to them
should be lOMn or more.

~HITACHI
144

-<

IQ

!

';;I
gb

~

f{l

~

or!

or!

1
1
1-_ _-'-1- 4 - _ - ; : :_ _

XTAL

XTAL r=J--~-IIt----'=-.
EXTAL Lt--""--t--"i

Fig. 3-8

3.7

Signal C

EXTAL

Design of Oscillation
Circuit Board

Fig. 3-9

Example of Circuit Causing
Trouble in Oscillation

Precautionj- Sending/Receiving Program of Serial Data
Reading from or Writing into the SCI data register (SDR: $0012)
during sending/receiving of serial data may make sending/receiving
operation of SCI out of order.

3.8

Precautionj- WAIT/STOP Instructions Program
When I bit of condition code register is "1" and an interrupt
(INT, TIMER/INT 2 , SCI/TIMER2 ) is held, the MCU does not enter into
WAIT mode by executing the WAIT instruction.
In that case, the MCU executes the corresponding interrupt processing routine after the 4 dummy cycles.
When external interrupts (INT, INT2) are held at the I bit mask, the
MCU does not enter into the STOP mode by the STOP instruction execution. The MCU executes the corresponding interrupt processing routine
after the 4 dummy cycles, in this case, either.

~HITACHI
145

4.

PIN ARRANGEMENT AND DIMENSIONAL OUTLINE

(1)

•

HD6305UO, HD6305VO
HD6305UO~

~

N~
A,

HD6305VOP (DP-40)

0

•

HD63705VOC (DC-40)

Jl'iiY

o.;lRT;
Do/CR"
D./Rx
DolT.
D.

'"

'"'""A,

D,

So

Do

e.

8,
Ib

C,
C•

...a.

S.

c.
c.
c.

a.

8,
V..

HD6305UOC~

HD6305UOF, HD6305VOF (FP-54)

Vee
ElCTAL
XTAL
nMER

At
At

•

•

C.
C,

HD6305VOCP (CP-44)

RES

o

iiif

3

At

NC

A.

D,

C,
C.

Pin Arrangement (1bp View)

~HITACHI
146

ii'fiiY
D,IINT.

D.tCK
DoIAx
Ds/T.
D./CE
DI/OE

B.
B. 1
B.
B.
B.
B.
B.
B,

V..

Fig. 4-1

40 Vc:c
EXTAL
XTAL
7 TIMER/Vpp

D.
C.
C.
C.

C.

Unit: _(inch)

•

DP-40
52.8(2.079)
54.0max.(2.126ma•.)

40

21

_lC;

•

•

~- a~i~
.. an
-9
20

1.2
(0.047)

DC-40
50.28
(1.919)

~.

rV,

2'

[QJ

N-

;~
211

O.25!X}J

(o.o'O_n,;)

•

FP-S4
2.9max.

(0.1 14m•• .)

0.IS±0.05
(0.006 ± 0.002)

(NOTE) Inch value indicated for your reference

Fig. 4-2

Dimensional Outline

~HITACHI
147

Unit: _(inch)

•

CP-44

17.53±0 12(O.19O±o.oo5)
6
7

I~

40

0

'17

I5.50 ± 0.50(0.61 0 ± 0.020)

Fig. 4-2

•
148

Dimensional Outline

HITACHI

5. ELECTRICAL CHARACTERISTICS
5.1 Electrical Characteristics for HD6305UO, HD6305VO
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit

Supply Voltage

VCC

-0.3 '" +7.0

V

Input Voltage

Vin

-0.3 '" VCC + 0.3

V

Operating Voltage

Topr

Storage Voltage

Tstg

o '"

°c

+70

-55 '" +150

°c

(Note)
These devices contain circuits to protect the inputs against high
static voltages or high electric fields.

Be careful not to apply any

voltage higher than the absolute maximum rating to these high input
impedance circuits.

For normal operation, we recommend the Vin and

Vout be constrained to the range VSS

~

(Vin or Vout )

~

VCC'

• MCU MODE ELECTRICAL CHARACTERISTICS
•

DC Characteristics (VCC = 5.0V ± 10%, VSS = GND, Ta
unless otherwise specified)
Item
~,

Input "High"
Voltage
Input "Low"
Voltage

Symbol

Test
Condition

STFl

EXTAL

All Inputs

VCC-0.5

-

VIL

-0.3

Wait
Stop

typ

VCC xO.7
2.0

Active
Current **
Dissipation

min

VIH

All Others

ICC

f=lMHz*

Standby
Input Leakage
Current
Three State
Leakage
Current

TIMER~
IIILI
INT' TB
Ao"'A7 ,BO"'B7,
CO"'C7,DO"'D6 IITSII

Input
Capacitance

All Inputs

Cin

Vin=0.5 '"
VCC-°. 5V
f=lMHz,
Vin=OV

0 '" +70°C

max

Unit

VCC +0.3
VCC+0.3
VCC+0.3

V

O.S

V

10

mA

2

5

mA

2

10

\.IA
\.IA

-

-

2

10

-

1

-

-

1

-

-

12

5

\.IA

pF

* The value at f=x MHz is gain by ICC=(f=XMHz) = ICC (f=lMHz) x X.
** VIR min = VCC -1. OV, VIL max = O. SV Penetrate current is not included.

~HITACHI
149

•

AC Characteristics (VCC = 5.0V
unless otherwise specified)

Item

Symbol

±

10%, VSS

1ID6305UO va
min
typ
max

Test
Condition

1ID63A05UO IVO
min
typ max

HD63B05UO VO
min
typ max

Unit

Clock
Frequency

fcl

0.4

-

4

0.4

-

6

0.4

-

8

MHz

Cycle Time

tcyc

1.0

-

10

0.666

-

10

0.5

-

10

}.IS

INT
Pulse Width

tIW!.

tcyc
+250

-

-

tcyc
+200

-

-

tcyc
+200

-

-

ns

INT2
Pulse Width

tIW!.2

tcyc
+250

-

-

tcyc
+200

-

-

tcyc
+200

-

-

ns

tRW!.

5

-

-

5

-

-

5

-

-

tcyc

-

-

tcyc
+200

-

-

tcyc
+200

-

-

ns

-

-

20

-

-

20

-

-

20

ms

80

-

-

80

-

-

80

-

-

ms

RES
Pulse Width
TIMER
Pulse Width

tcyc
+250

tTWL

Oscillation
Start Time
(Crystal)

tosc

Reset Delay
Time

tRHL

•

CL • 22pF±
20%
Rs - 60n
max
external
capacitance
2.2 }.IF

\.

Port Characteristics (VCC = 5.0V ± 10%, VSS
unless otherwise specified)
Item

Symbol

= GND, Ta = 0

~

+70·C

Test Condition

min

typ

max

Unit

lOR = -200].lA

2.4

-

V

-

V

VOR

lOR

= -lO].lA

VCC-0.7

-

Output "Low"
Voltage

VOL

IOL

= l.6mA

-

-

0.55

V

Input "High"
Voltage

VIH

2.0

-

VCC +0.3

V

VIL

-0.3

-

0.8

V

-

1

].lA

Output
"Righ"
Voltage

Input "Low"
Voltage
Input
Leakage
Current

Por\:: A,
B, C, D

Port A,
B, C. D

IIILI

Vin =
0.5WCC -0.5V

~HITACHI
150

GND, Ta

-

•

seI TimIng (Vee = S.OV ± 10%, VSS
unless otherwise specified)

GND, Ta = 0

HD6305UO/VO
Item

~

+70·e)
HD63BO suo IVO

HD63A05UO/VO

Symbol

Unit

m1n

typ

max

min

typ

max

min

typ

max

0.67

-

21845

0.5

-

16381

liS

250

-

-

250

ns

-

200
100

-

ns

-

-

Clock Cycle Time

tScyc

1

-

32768

Data Output Delay Time

tTXD

-

-

250

-

Data Set-up Time

tSRX

200

200

tHRX

100

-

-

Data Hold Time

-

100

-

ns

tScvc
Clock Output
Ds/CK

Data Output
D3/TX

\

,j

-

O.6V

IrO.6V

tn

HD630SUO

$1FF3
$1FF4
<>

$1FFF
$1000
<>

HD630SVO

<.

"'

L

<-

"'

{

Address of EPROM
~

,
~

,)

<>

<.

<>

$1FF3
$1FF4
<>

HN482764
HN27C64
or their equivalent

$1FFF
$1000
j

$1FF3
$1FF4
$1FFF

Remarks

$1800

<>

$1FF3
$1FF4

,)

<>

HN482764
HN27C64
or their equivalent

$1FFF

~HITACHI
163

I APPENDIX I
I.

DESIGN PROCEDURES AND SUPPORT TOOLS

Cross assembler and hardware emulator, containing various kinds of
computers, are available as supporting systems to develop users' programs.
Users' programs are mask programmed into ROM and shipped by Hitachi.

Fig. I-I shows a typical program design procedure and Table I-I
summarizes a set of system development support tool for HD6305UO and
HD6305VO.

Text Editor
Host Computer

(61

Cross Assembler
Host Computer

Emulator
EPROM On-Chip LSI,
HD63705VOC

No

Fig. I-I

Program Design Procedure

~HITACHI
164

The following explains the system development procedure.
1.

Specify functional assignment of I/O pins and allocation of RAM
area before starting programming.

2.

Design a flowchart to implement the functions and encode
this flowchart with mnemonic codes.

3.

Punch the coded format onto cards or write it on a floppy disk.
This set of coded form is a source program.

4.

Assemble the source program to gene rage an obj ect with a cross
system. And check errors out here.

5.
6.

Verify the program through hardware simulation with emulator or
EPROM on-chip microcomputer.
Send the completed program in EPROM to Hitachi.

7.

After Hitachi received user's specified ROM pattern, Hitachi
fabricate sample LSI for users' evaluation for the functions.

I
If

a user does not find any problem in the sample LSI, Hitachi will
start mass production of the LSI.

Table I-I System Development Support Tbols
Type No.

HD6305UO
HD6305VO

Emulator

EPROM
On-Chip LSI

IBM PC
Cross Assembler

H35MIX3
(HS35VEML03H)

HD63705VOC

S35IBMPC

~HITACHI
165

Single Chip Microcomputer ROM Ordering Procedure
(1)

Development Flowchart

Single chip microcomputer device is developed according to
the following flowchart after program development.
Customer

Hitachi



(>

(>

(>

(>

1

1

1

1

32768 IlS

SCR7

I

(>

1/32s

C7 terminal

o

Used as I/O terminal (by DDR).

1

Serial data output (DDR output)

SCR6

C6 terminal

o

Used as I/O terminal (by DDR).

1

Serial data input (DDR input)

SCRS

SCR4

0

0

-

0

1

-

1

0

Internal

Clock output (DDR output)

I

1

External

Clock input (DDR input)

Clock source

Cs terminal
Used as I/O terminal (bYI DDR).

~HITACHI
193

(2) SCI Data Register (SDR; $0012)
A serial-parallel conversion register that is used for transferring
data.
(3) SCI Status Register (SSR; $0011)
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving 8-bit data.

It is cleared

when reset or data is written to or read from the SCI data register
with the SCR5="1".

The bit can also be cleared by writing "0" into

it.
Bit 6 (SSR6)
Bit 6 is the TIMER2 interrupt request bit.

TIMER2 is multi-

plexed with the serial clock generator, and SSR6 is set each time
the internal transfer clock falls.

When reset, the bit is cleared.

It also be cleared by writing "0" in it.

(For details, see TIMER2.)

Bit 5 (SSR5)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software.
(SSR7) is masked.

When this bit is set to "1", the SCI interrupt

When reset, it is set to "1".

Bit 4 (SSR4)
Bit 4 is the TlMER2 interrupt mask bit which can be set or
cleared by software.
rupt (SSR6) is masked.

When the bit is set to "1", the TlMER2 interWhen reset, it is set to "1".

Bit 3 (SSR3)
When "1" is written into this bit, the presca1er of the transfer
clock generator is initialized.

When read, the bit is always "0".

Bits 2 IV 0
Not used.

Fig. 2-8

194

SCI Status Register (SSR; $0011)

$

HITACHI

SSR7

SCI interrupt request

0

Absent

1

Present

SSR6

TlMER Z interrupt request

0

Absent

1

Present

SSRS

SCI interrupt mask

0

Enabled

1

Disabled

SSR4

TlMERZ interrupt mask

0

Enabled

1

Disabled

(4) Data Transmission
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and S of port C are set at the serial data
output terminal and the serial clock terminal, respectively.

The

transmit data should be stored from the accumulator or index
register into the SCI data register.

The data written in the SCI

data register is transmitted from the C7/Tx terminal, starting with
the LSB, synchronously with the falling edge of the serial clock.
(Refer to Fig. Z-9.)

When 8 bits of data have been transmitted,

the interrupt request bit is set in bit 7 of the SCI status register
with the rising edge of the last serial clock.

This request can be

masked by setting bit S of the SCI status register.

Once the data

has been transmitted, the 8th bit data (MSB) stays at the C7/ Tx
terminal.

If an external clock source has been selected, the

transfer rate determined by bits 0

~

3 of the SCI control register

is ignored, and the CS/CK terminal is set as input.

If the internal

clock has been selected, the Cs/CK terminal is set as output and
clocks are transmitted at the transfer rate selected by bits 0

~

3

of the SCI control register.

~HITACHI
195

Illput Oa'l Latch
Timillf IC,/R_'

'Fig. 2-9

SCI Timing Chart

(5) Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are
determined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.

Then

dummy-writing or reading the SCI data register, the system is
ready for receiving data.

(This procedure is not needed after

reading a subsequent received data.

It must be taken after reset

and after not reading a subsequent received data.)
The data from the C6/Rx terminal is input to the SCI data
register synchronously with the leading edge of the serial clock
(Refer to Fig. 2-9).

When 8 bits of data have been received, the

interrupt request bit is set in bit 7 of the SCI status register.
This request can be masked by setting bit 5 of the SCI status
register.

If an external clock source has been selected, the

transfer rate determined by bits 0

~

3 of the SCI control register

is ignored and the data is received synchronously with the clock
from the C5 /'CK terminal. If the internal clock has been selected,
the C5 /CK terminal is set as output and 'clocks are output at the
transfer rate selected by bits 0

~

3 of the SCI control register.

(6) TlMER2
The SCI transfer clock generator can be used as a timer.
SCI clock selected by bits 3
(4

~s ~

approx. 32ms

~

The

0 of the SCI Control Register

in 4MHz operation) is received by bit 6 of the

SCI Status Register, and the timer 2 interrupt request bit is set
at each falling edge of the SCI clock.

Since this interrupt occurs

periodically, Timer2 is available for a reload counter or a timer.
Timer2 is multiplexed with the SCI transfer clock generator.
When using Timer2 independently of the SCI, external clock should
be selected as SCI clock source by setting both SCR5 and SCR4 to
"1".

If Internal clock is selected as a SCI clock source, reading
from or writing to the SDR initializes the prescalor of the SCI
transfer clock generator.

~HITACHI
196

CD

®@

®®

--"--1

L

t

i

CD : Transfer clock generator is reset and mask bit (bit 4 of SCI
status regis tor) is cleared
®.® : TlMER2 interrupt request
®.@ : TlMER2 interrupt request bit cleared
2.5

Reset
The MCU can be reset either by external reset input (RES) or
power-on reset.

(Refer to Fig. 2-10.)

On power up, the reset input

must be held "Low" for at least tosc to assure that the internal
oscillator is stabilized.

A sufficient time of delay can be obtained

by connecting a capacitance to the RES inputs as shown in Fig. 2-11.
5V

4.5/V

Vee

OV-------------J

...... ~VIL -RES

RES

Terminal

Internal

Re~t

-----------f""/ '

----------------~

Fig. 2-10

Power On and Reset Timing

Vee .--J\Jw-t=:--'I
100kn

:Vp

RES$ 2.2"F

HD6305X/Y
MCU

Fig. 2-11
2.6

Input Reset Delay Circuit

Internal Oscillator Options
The internal oscillator circuit is designed to meet the requirement for minimum external configurations.
ing a crystal (AT cut 2.0

~

It can be driven by connect-

8.0MHz) or ceramic oscillator between pins

5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 2-12.
Figs. 2-13 and 2-14 illustrate the specifications and typical arrangement of the crystal, respectively.

~HITACHI
197

l·o-8:.oMHz~

EXTAL
XTAL

HD6305X/Y
MCU

10-22pF±20%

Crystal Oscillator
EXTAL
XTAL

HD6305X/Y
MCU

Ceramic Oscillator
External
Clock
Input
EXTAL
NC

XTAL HD6305X/Y
MCU

External Clock Drive

Fig. 2-12

Internal Oscillator Circuit

c,

At Cut
Paralle
Resonance
7pF max.
XTALL---f~EXTAL Co;
f;2.0 -8.0MHz
Rs;60n max.

~~
Fig. 2-13

r---------------

Parameters of Crystal

(b)
(a)
[NOTE 1 Us. as short wirings as possible for connection of the crystal
with the EXTAl and XTAl terminals. 00 not allow these
wirings to cross others.

Fig. 2-14

Typical Crystal Arrangement

~HITACHI
198

2.7

Interrupts
There are six interrupts:

external interrupts (INT, INT2) ,

internal timer interrupts (TIMER, TIMER2), serial interrupt (SCI) and
interrupt by an instruction (SWI).
Of these six interrupts, the INT2 and TIMER interrupt or the SCI
and TIMER2 interrupt generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops and the
then CPU status is saved onto the stack.

Then, the interrupt mask bit

(I) of the condition code register is set and the start address of the
interrupt processing routine is obtained from a particular interrupt
vector address.
address.

Then the interrupt

~outine

starts from the start

System can exit from the interrupt routine by an RTI

instruction.

When this instruction is executed, the CPU status before

the interrupt (saved onto the stack) is pulled and the CPU restarts
the sequence with the instruction next to the one at which the interrupt occurred.

Table' 2-4 lists the priority of interrupts and their

vector addresses.
A flowchart of the interrupt sequence is shown in Fig. 2-15.
A block diagram of the interrupt request source is shown in Fig. 2-16.
(1) External Interrupt
In the block diagram, both the external interrupts INT and INT2 are
edge trigger inputs.

At the falling edge of each input, an interrupt

request is generated and latched.

The INT interrupt request is auto-

matically cleared if jumping is made to the INT processing routine.
The INT2 interrupt request is masked when "0" is written to bit 7 of
the Miscellaneous Register.
If the I bit of the Condition Code Register is set to "1",
interrupt requests of the external interrupt (INT, INT2) are
retained, but not processed. Immediately after the I bit is cleared,
the CPU jumps to the corresponding interrupt routine.

The INT2

interrupt can be masked by setting bit 6 of the Miscellaneous
Register.
The INT terminal status can be tested by a BIL or BIH instruction.

The INT falling edge detector circuit and its latching

~HITACHI

199

circuit, and INT2 terminal are unaffected by executing BIL and
BIH instructions.
(2) Internal Interrupt and SCI Interrupt
When I bit of the Condition Code Register is set to "1",
internal timer interrupts (TIMER, TIMER2) and SCI interrupt
requests are retained without being processed.

Immediately after I

bit is cleared, the CPU initiates the corresponding interrupt
service routine.

Timer interrupt, SCI interrupt, Timer2 interrupt

can be masked by setting bit 6 of Timer Control Register, bit 5 of
SCI Status Register, and bit 4 of SCI Status Register, respectively.
Table 2-4 Priority of Interrupts
Interrupt

Priority

Vector Address

RES

1

$lFFE, $lFFF

SWI

2

$lFFC, $lFFD

INT

3

$lFFA, $lFFB

TIMER/INT2

4

$lFF8, $lFF9

SCI/TIMER2

5

$lFF6, $lFF7

1.....1
$FF.....SP
O..... OOR·S
CLR iiii'l'Logic
SFF.....TOR
$7F .....Timer Prescaler
$50.....TCR
S3F .....SSR
$OO.....SCR
$7F .....MR

Fig. 2-15

200

Interrupt Flowchart

eHITACHI

Vectoring generated

$1 FFA. $1 FFB
BIH/BIL Test
Condition Code Register (CCR)

iNT Inter·
rupt Latch

INT
Falling Edge Detector

} - - - < t - t - - - - Vectoring generated

$1FF8.$1FF9
TIMER

SCI/TIMER.
} - - - _ - - - Vectoring generated
$1FF6.$1FF7
SCI

Fig. Z-16

Interrupt Request Generation Circuitry

(3) Miscellaneous Register (MR: $OOOA)
Miscellaneous Register (MR: $OOOA) specifies INT request sense
(edge sense or level sense) and controls INTZ interrupt.
Bit 7 of Miscellaneous Register (MR7) is an INTZ interrupt
request flag.

When the falling edge is detected in INTZ, MR7 is

set to "I".

MR7 can be checked by software if it is INT Z interrupt
or not in the interrupt service routine (vector address: $lFF8,
$lFF9).

This bit can be reset by software.

Bit 6 (MR6) is the INTZ interrupt mask bit.
set to "1", the INTZ interrupt is masked.

If this bit is

Both read and write are

possible with bit 7, but "I" cannot be written in this bit by
software.

Thus an interrupt cannot be requested by software.

During reset, bit 7 is initialized to "0", while bit 6 is
initialized to "I".
76543210

IMR7IMR61Z1Z1Z1Z1Z1Z1

I

tL__________

L._ _ _ _ _ _ _ _ _ _ _ _

Fig. Z-17

INTl Interrupt Mask
INTl Interrupt Request Flag

Miscellaneous Register (MR:$OOOA)

~HITACHI
201

2.8

Input/Output Ports
(1) I/O Ports
HD630SXO/YO and HD63P05YO have 32 I/O ports (Port A, B, C, G),
HD630SXl/Yl, HD630SX2/Y2 provide 24 r/o ports (Port A, B, C).

Each

terminal can individually function either as input or output by
programming the Data Direction Register.

If a corresponding bit of

Data Direction Register is set to "0", the I/O port functions as an
input.

While corresponding bit of Data Direction Register is pro-

grammed to "1", the I/O port functions as an output.

Port A, B or C,

when functioning as output and reading I/O port data, reads latched
data, even if the output level is flunched by the output load
(Refer to Fig. 2-l8(a».

In this case, Port G always reads the pin

level (Refer to Fig. 2-l8(b».

Thus even when "1" is transmitted,

Port G sometimes reads "0" if the load condition causes the output
voltage to decrease less than 2.0V.
During reset, all Data Direction Registers are initialized
to "0" and all I/O ports function as inputs.
I/O ports are compatible with TTL and CMOS in respect to both
input and output.
If I/O ports are not used, they should be connected to Vss
through resistors.

If these terminals are left open, they may

consume extra power.
(2) Output Ports (for HD630SXO/YO, HD63POSYO only)
There are 16 output-only terminals (ports E and F).
them can also read.

Each of

In this case, latched data is read even with

the output terminal level being fluctuated by the output load (as
with ports A, B and C).
When reset, "Low" level is transmitted from each output terminal.
(3) Input Ports

Seven input-only terminals are available (port D).

Writing

to an input terminal is invalid.
All input/output terminals, output terminals and input
terminals are TLL compatible and CMOS compatible in respect of
both input and output.
If I/O ports or input ports are not used, they should be
connected to Vss through resistors.

If these terminals are left

open, they may consume extra power.

202

~HITACHI

Bit of data
direction
register

Bit of
output
data

Status of
output

Input to

1

0

0

0

1

1

1

1

0

x

3-state

Pin

a.

Ports A, Band C

b.
Fig. 2-18

MCU

Port G

Input/Output Port Diagram

~HITACHI
203

2.9

Low Power Dissipation Mode
HD6305X family and HD6305Y family have three types of low power
dissipation modes:

Wait mode, Stop mode, and Stop mode.

(1) Wait Mode
When Wait instruction is executed, the MCU enters into the
WAIT mode; the oscillator does not stop, but the internal clock
stops.

The CPU stops but the internal peripherals (e.g.

and SCI) continue their current operations.

(Note:

Timer

Once the

system entered into the Wait mode, SCI can no longer be retriggered.)
During the Wait mode, RAM and I/O terminals hold their conditions
just before entering into the Wait mode, while I bit of the Condition Code Regi ster is cleared to "0".
The MCU can be recovered from the Wait Mode by an interrupt
(INT, TlMER/INT2, or SCI/TIMER2), RES or STBY.

The RES resets the

MCU, and the STBY brings it into the standby mode (Refer to Standby
mode for details).
When the CPU accepts interrupt request, the wait
mode escapes, then the CPU is brought to the operation mode and
vectors to the interrupt routine.

If the interrupt is masked by the

I bit of the condition code register, after releasing from the wait
mode,the MCU executes the instruction next to the WAIT.

If an

interrupt other than the INT (e.g., TIMER/INT2 or SCI/TlMER2) is
masked by the timer control register, miscellaneous register or
serial status register, the CPU does not receive any interrupt request,
Thus the wait mode cannot be released.
Fig. 2-19 shows a flowchart for the wait function.
(2) Stop Mode
When STOP instruction is being executed, the MCU enters into the
stop mode.

In this mode, the oscillator stops and the CPU and

peripheral stops functioning but the RAM, registers and
I/O terminals hold their condition just before entering into the
stop mode.
The escape from this mode can be done by an external interrupt
(INT or INT2), RES or STBY.

The RES resets the MCU and the STBY

brings it into the standby mode.

~HITACHI
204

When the CPU accepts interrupt request, the stop
mode escapes, then the CPU is brought to the operation mode and
vectors to the interrupt routine.

If the interrupt is masked by

the I bit of the condition code register, after releasing from the
stop mode, the MCU executes the instruction next to the STOP.
The MCU cannot be released from the STOP mode if the INTZ interrupt
is masked by the miscellaneous register.
Fig. 2-20 shows a flowchart for the stop function.

Fig. 2-21

shows a timing chart when the MCU is released from the stop mode.
For releasing from the stop mode by an interrupt, oscillation
starts upon input of the interrupt and, after the internal delay
time for stabilized oscillation, the CPU becomes active.

When

restarting by RES, oscillation starts when the RES goes "0" and the
CPU restarts when the RES goes "1".

The duration of RES="O" must

exceed tosc=20ms to assure stabilized oscillation.
(3) Standby Mode
The MCU enters into the standby mode when the STBY goes "Low".
In this mode, all operations stop and the internal condition is
reset holding the RAM contents.
impedance state.
"High".

The I/O terminals go into High-

The standby mode should escape by bringing STBY

The CPU must be restarted by reset.

The timing of input

signals at the RES and STBY is shown in Fig. 2-22.
Table 2-5 lists the status of each parts of the MCV in each
low

po~er

dissipation modes.

Transitions between each mode are

shown in Fig. 2-23.

~HITACHI
205

Oscillator Active
Timer and Serial
Clock Active
All Other Clocks
Stop

Initialize
CPU, TIMER. SCI.
I/O and All
Other Functions
No

No

Load PC from
Interrupt Vector
Addresses

Fetch
Instruct ion

Fig. 2-19

Wait Mode Flowchart

~HITACHI
206

Stop Oscillator
and All Clocks

No

No
to Standby
Mode
Turn on Oscillator
Wait for Time Delay
to Stabilize

Turn on Oscillator
Wait for Time Delay
to Stabilize

1=0

Load PC from
I nterrupt Vector
Addresses

Fetch
Instruct ion

Fig. 2-20

Stop Mode Flowchart

~HITACHI
207

Oscillator
E

I

STOP instruction
executed

Interrupt

Time required for oscillation to become
stabilized (built-in delay time)

restart

(a) Restart by Interrupt
Oscillator
E

STOP instruction
executed

Time required for oscillation to become
stabilized (tos e )

Reset
start

(b) Restart by Reset
Fig. 2-21

STBY

Timing Chart of Releasing from Stop Mode

\

RES

I

I

I
I
I
I
I

I

I

I
I

I

H
I
I
I

I

,-_.& _ ..... _ ..I'

\

I

if

.I
tose

Fig. 2-22
Table 2-5

I Restart

Timing Chart of Releasing from Standby Mode

Status of Each Part of MCU in Low Power Dissipation Modes
Condition

Mode

Start
WAIT in-

WAIT
Software
STOP

struction

STOP in
struction

Stand-

Hard-

by

ware

STBy="Low "

Oscillator

CPU

Timer,

Active , Stop

Register

RAM

I/O
terminal

Active

Keep

Keep'

Keep

STBY, RES, INT, INT2,
each interrupt request of
TIMER, TIMER2, SCI
STBY, RES, INT, INT Z

Serial

Stop

Stop

Stop

Keep

Keep

Keep

Stop

Stop

Stop

Reset

Keep

High impedance

~HITACHI
208

Escape

STBY="High"

Fig. 2-23

Transitions among Active Mode, Wait Mode,
Stop Mode, Standby Mode and Reset

~HITACHI
209

3.
3.1

APPLICATIONS AND PRECAUTIONS
Memory Space Expansion of HD6305X1/Y1, HD6305X2/Y2, HD63P05Y1

(1)

ROM
ROM space can be expanded by

e~ternally
I

connecting EPROM or

Fig. 3-1 show~ an example of using the

Mask ROM to the MCU.
HN482732A.

I

/

HD6305Xl, HD6305X2
HD6305Yl, HD6305Y2
HD63P05Yl

HN482732A
12

ADRO'VADR11

8

DATAo'VDATA7

Fig. 3-1

(2)

AO'VA11
00 'V 07

Memory Space Expansion for ROM

RAM

Fig. 3-2 shows a system configuration by using the HM6116.

HD6305Xl, HD6305X2
HD6305Yl, HD6305Y2
HD63P05Yl

HM6 11 6

ADRO 'V ADR10

AO'VAlO

DATAO'VDATA7

1/01 'V I/OS

E

Fig. 3-2

R/W

.....

A

.....

v-

~

....

OE
CS

Memory Space Expansion for RAM

~HITACHI
210

WE

3.2

Watch-Dog Timer
(1)

Purpose
A simple method of implementing the watch dog timer, which
is generally known as a means of recovery from a system upset,
will be described below.

(2)

Basic circuit
Fig. 3-3 shows the basic circuit for recovery from a system
upset.

Vee

Vee

R

Microcomputer

--'l.Alive
Pulse

Port
Monostable
Mu It i-vibrator

Fig. 3-3

(3)

Basic Circuit for Recovery from a System Upset

Operation outline
(i)

In structuring system software, design the whole system so
that a pulse is generated through the port within a
predetermined period (r:
®:

Sms+2ms = 7ms
Sms+Sms =lOms

«): 7ms

* Preset

as the pass

®

lOms VZl + VFl
Vout - GND when Vee < VZl + VFl
(b)

The voltage VZZ' applying to ZDZ, and the
ON level VFZ of Trl are constant, even if the Vee
changes.

v

The followings describe the RES signals.
Vee

----------t:]
( ThreShoi~)D~--~Ivout-L
voltage

L -_ _

~

______

~

= Vee when Vee > VZZ
Vout = GND when Vee < VZZ

{ Vout

-+____

__

+ VFZ
+ VFZ

When the Vee changes, threshold level VLM is affected by
replacing the Zener diodes ZD l and ZD Z•
(iii)

The Auto-reset function will be more stable by feeding
back the output signal to the RES terminal, fine tuning
the reference voltage, and providing hysteresis with the
VLMI and the VLMZ.

(VLMI is a voltage during the shifting

~HITACHI
213

from operation to resetting, and VLM2 is the voltage in
recovering.)

3.4

Manual Reset Circuit
(1)

Purpose
When the MCU is reset by an external switch, it is necessary
to prevent the MCU from chattering.

The following describes

a reset circuit in which chattering prevention and power-on
reset functions are provided.
(2)

Basic Circuit
Fig. 3-5 shows the basic circuit of manual reset.
Vee

Vin

Vou!

~--

r
Fig. 3-5
(3)

To the RES pin

HDaLSu

Basic Circuit of Manual Reset

Operation Principle
(i)

Power-on reset
During power-up, the capacitor C will be charged and the
Yin rising time will be delayed by the CR charge time, so
that power-on would be reset normally.
V

Vee

L-~-----

Vin

t=CxR

(ii)

Manual reset
When SW is on, the Vout goes "0" and the MCU is reset
When SW is off, the capacitor C is charged, so that the
rising time of Yin is delayed by the CR charge time.

~HITACHI
214

Chattering is prevented by the capacitor C and the schmidt
trigger HD74LS14.

OFF --1f-----ON - - - - t - - OFF

00 When SW OFF -- ON,
Vout = GND when Yin < O.BV

sw

® When SW ON -- OFF,
Vout

=

VCC when Yin > 1.6V

Vi n

Vout

AID Converter Circuit (1) •.• High Speed

3.5

(1)

Purpose
The following describes how to implement a simple AID
conversion (analog-digital conversion) using the resistance radder
(R-2R system).

(2)

Basic Circuit

Microcomputer
Vin

Analog "':":':':-'---II~
Input

v:
V

REF

=(~+Dn-I + ... +!!L+~ ) x V
2

zn-r

2'

2n

R

Vout

2R

Voltage of the output
"1" of the port

V

Port

Necessary number of
port=Accuracy bit+l

=0

: Vin ;;;;;VRI!F

Vout = 1 : Yin >VREF

r----t~----------Vin

VREF

2R

r--t-1

Fig. 3-6

Vo"ut"

AjD Converter Basic Circuit

M

"

~

Fig. 3-7

Timing Chart

~HITACHI
215

(3)

Operation Outline
The following describes the operation outline of 3-bits A/D
converter circuit.
(i)

The digital outputs (D3, D2, Dl) are changed from (1, 1, 1)
to (0, 0, 0) at the port.

VREF is reduced from 7/8 V to 0

by every 1/8 V according to Table 3-1.
(ii)

The output Vout • which is the result of comparison between
the analog input Vin and VREF, is reversed from "0" to "1"
when Vin is greater than VREF as shown in Fig. 3-7.

(iii)

The value of (D3, D2, D1), when Vout

is reversed from

"0" to "1", is a digital value to the analog input Vin.
Table 3-1

D3

D2

D1

VREF

0

0

0

0

0

0

1

1/8 x V

0

1

0

2/8 x V

0

1

1

3/8 x V

1

0

0

4/8 x V

1

0

1

5/8 x V

1

1

0

6/8 x V

1

1

1

7/8 x V

Value of VREF

Dl '" D3 are denoted by "1" or "0"
V:

Voltage of the port output "I"

~HITACHI
216

3.6

AID Converter Circuit (2) ... Low Speed
(1)

Purpose
The following describes the A/D conversion system utilizing
time for charge/discharge to/from the CR circuit.

This conversion

system is available even if the A/D conversion time is slow.
(2)

Basic Circuit
Operation Microcomputer
amplifier
HAl7902

Yin

Analogo---------~

Input

A

Number of
port
required = 2

R
A

;;;0

Yin
VaEl'

Port
Vout

Fig. 3-8

AID Converter Basic Circuit

n :

Timer

Count
value

T =To x n

To: Timer Interval
Fig. 3-9
(3)

Timing Chart

Operation Outline
(i)

Set the output terminal A of the port to "1", discharge the
external condenser C for a sufficiently long period, decline A
from "1" to "0" synchronously with the timer interrupt and
charge C.

(ii)

Check Vout for each timer interrupt and observe the time T in
which Vout declines from "1" to "0".
Yin is less than VREFo

(iii)

Vout becomes "0" when

Obtained as T=TO x n.

The obtained time T which is voltage converted is a digital
value of the analog input Yin.

~HITACHI
217

I

AID conversion
subroutine

3.7

Precautionj- Board Design of Oscillation Circuit
When connecting crystal and ceramic resonator with the XTAL and
EXTAL pins to oscillate, observe the followings in designing the
board.
Locate crystal, ceramic resonator, and load capacity Cl and

(1)

C2 as near the LSI as possible.

(Induction of noise from outside

to the XTAL and EXTAL pins may cause trouble in oscillation.)
(2)

Wire the signal lines to the neighbouring XTAL and EXTAL

(3)

pins as far apart as possible.
Board design of situating signal lines or power supply lines
near the oscillator circuit as shown in Fig. 3-11, should not be
used because of trouble in oscillation by induction.

The

resistor between the XTAL and EXTAL, and pins close to them
should be 10Mn or more.
..; Oil

....III ....
<=
00

~

00

..... .....

----

XTAL
EXTAL

XTAL

Cl--~~f-,
CI--+-~f-'l

EXTAL

--,

~

f--I

'"II

'{J

I

I
I

I
I

I
I
I
I

I

Design of Oscillation
Circuit Board

~HITACHI
218

I
I
I

I
I
I

Cl

Signal C

cf:;~
T
..

;2 -.J,.

HD6305X
HD6305Y
HD63P05Y

HD6305X
HD6305Y
HD63P05Y

Fig. 3-10

I

Fig. 3-11

Example of Circuit Causing
Trouble in Oscillation

3.8

Precaution; - Program of Write Only Register
Read/Modify/Write instructions are unavailable for changing the
contents of Write Only Register (e.g. DDR; Data Direction Register of
I/O port) of HD630SX, HD630SY and HD63POSY.
(1)

Data cannot be read from Write Only Register.
(e.g. DDR of I/O port)
While Read/Modify/Write instructions are executed in the
following sequence.
(i)
(ii)
(iii)

Reads the contents from appointed address.
Changes the data which has been read.
Turn the data back to the original address.
Thus, Read/Modify/Write instructions cannot be applied

to Write Only Register such as DDR.
(2)

For the same reason, do not set DDR of I/O port using BSET
and BCLR instructions.

(3)

Stored instructions (e.g. STA and STX, etc.)are available
for writting into the Write Only Register.

3.9

Precaution. - Sending/Receiving Program of Serial Data
Reading from or Writing into the SCI data register (SDR:$0012)
during sending/receiving of serial data may make sending/receiving
operation of SCI out of order.

~HITACHI
219

3.10 Precaution; - WAIT/STOP Instructions Program
When I bit of condition code register is "1" and interrupt
(INT, TIMER/INTZ, SCI/TIMERZ) is held, the MCU does not enter into
WAIT mode by executing WAIT instruction.
In that case, after the 4 dummy cycles, the MCU executes the next
instruction.
In the same way, when external interrupts (INT,

1NT2)

are held at

the bit I set, the MCU does not enter into the STOP mode by executing
STOP instruction.

In that case the MCU executes the next instruction

after the 4 dummy cycles.

3.11 Precaution; - 1b use the ERPOM ON-PACKAGE 8-hit Single-chip
Microcomputer
Please be careful of the following, since this MCU has a special
structure with pin socket on the package.
(1)

Do not apply high static volcage or surge voltage over
MAXIMUM RATINGS to the socket pins as well as the LSI pins.
Otherwise permanent damage to the device would be caused.

(Z)

When using 3Zk EPROM (Z4-pin) , insert it leaving the four
pins above open.

(3)

When inserting this into system products like mask ROM type
single chip microcomputer, be careful of the following to give
effective contact between the EPROM pins and socket pins.

~HITACHI
220

(a)

When soldering the LSI onto a printed circuit board, the
recommended condition is:

(b)

Temperature:

lower than 250°C

Time:

within 10 sec.

Be careful that detergent or coating does not get into the
socket during flux washing or board coating after soldering,
because that may adversely affect the socket contact.

(c)

Avoid permanent application of this during
continuous vibration.

(d)

The socket, when repeatedly inserted and removed, loses its
contactability.

It is recommended to use a new one when

used in production.

4 Pins (On index side) open.

24 Pin EPROM should be inserted
on the mark side with 4 above open.

o
o
o
o
o

o
o

o
o

o
o

0

a.4G2 JAPAN
1IiVHD63P05VO/Vl

•

HITACHI
221

4.

PIN ARRANGEMENT AND DIMENSIONAL OUTLINE
• HD630SXO, HD630SYO

Vss

G.

RES

G,
G,
G,
G.
G.

00
STBY
XTAL
EXTAL
NUM
TIMER
A,
A.
A.
A.
A,
A,
A,
A.
B,
B.
B,
B.
B,

B,
B,

B.
CdT.
e./Rx

c,/CK
C.
C,
C,
C,
C.

•

G.
G,
F,
F.
F.
F.
F,
F,
F,
F.

(FP-64)

E,
E.
E.
E.
E,
E,
E,
E.
0,

C./Tx III

D.IiN"T,

CVRX~"~.~"~=~=~:~~~~w."~~~.w.~.~.~
l~uuuuuJlOQQQQ~

D.
D.
0,
0,
0,
Vee

HD630SX1, HD630SX2, HD630SY1, HD630SY2
Vss
RES

OATAo

DATA,
DATA,

DATAl
XTAL
EXTAL
NUM
TIMER
A,
A.
A,
A.
A,
A,
A,
A.
B,

B,
B,
B.
B,
B,
B,

B.

c,rr.

CI/R.

C,/CK
C,
C,
C,
C,
C.

222

~

u

DATA4
DATA.
DATA,
DATA 7
E
A/W
ADRll
AOR'2

~

z

~

"'< "'< I>•
""" ~ ~ I~ I~

• ••

i

~

::
~

~

~ ~i
~ ~
•• •• ••
f.

<

~ ~ "
~

ADR"
ADR,o
ADA.
ADA,
ADR7
ADA,
ADA,

(FP-64)

ADR4

ADA,
ADA,
ADA,
ADA.

0,

i1I;:;~=:;:I3=~fi~i;;:g

DI/mT;
D.
D.

~

u ;;,;

0,
OJ

0,
Vee

~HITACHI

U r5 ~

Q

0 Q 0 Q!~
d

at

ADR~

311

D.

•

•

HD63POSYO

v,,
lIES
11iIT

mv

a
3

XTAL
EXTAL
NUM
TIMER
A, •
A.
A, "
A.I
A,
A,
A,I

Ao

B"
B.,
B"
B,
B,
Bo
C7/Tx
e./Rx
C./l:R
C.
C,
C,
C, 1
Co

OVec

OAn

VecO

OA,

VecO

F,

OAo

10,0

F.
F,

OA,

A.O
A11 0

OA,

VssO

OA,

A,oO

OA,

ao

OAo

0,0

000

0.0

00,

0,0

00,

O. 0

aVss

0, 0

a

v••

Go
G,
G,
IG,
G.
G,
G.
G,
F,
F.

VecO

OA.

HD63POSYl

lIES
11iIT

DATAo
DATA,
DATA2
1 DATA3

3

mIV
XTAL
EXTAL
NUM
TIMER
A,
A.
Aa 11
Aol
A,
A,
A,I
Ao

F,
Fo
E,
E.
E,
E.
E,
E,
E,
1 Eo
0,
D./ll'lTi
0,
D.

B.
B,
B,
Bo
C,/T.
e.!Rx
C,/l:R 7
C.
C,
C,
C, 1
Co

D,
D,
D,
Vee

DATA.

OVec

VecO

OAu

VccO

OA,

VecO

OA.

AoC

OA,

A,O

DATA,
DATA,
DATA?
E

RtW
AOR13
ADRI2
ADRI1

OAo

AuO

OA,

VssO

OA,

A,oO

OA,

ao

OAo

0, 0

000

0.0

00,

0,0

00,

O. 0

OVss

0, 0

ADR,o
ADRo
ADRo
ADR?
ADR,
ADA,
ADR.
ADR:.
AOR2

0,
Oe/iNT2
0,
D.
0,
0,
0,

Vee

~HITACHI
223

• DP-64S

(Unit: mm(inch)
57.6(2.268)
58.6max.(2.307max.)

33

o
1.0
(0.039)

32

.£

1 ;~

19.05
(0.750)

1

~:1r-----\ "'~")'
(0.070±0.010)

~ ~ O'~

(0.019 ± 0.004)

~~.0IO:~.8g.

IS'

8

eFP-64
2.9max.
(0.114max.)

---l-.

OISt O.OS
(0006' 0.002)

~0'.15'
(O~
-

1.110 0 .3 .

L--.--=D:-:::C:-_-=6:-:::4-=S~P:-----------·--~~-- _._-

57.3
(2.256)

o

o
32

Note) Inch value indicated for your reference.

Fig. 4-2

224

Dimensional Outline

~HITACHI

5.
5.1

ELECTRICAL CHARACTERISTICS
Electrical Characteristics of HD6305XO, HD6305YO, HD63P05YO
• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit

Supply voltage

Vee

Input voltage

Vin

Operating temperature

Topr

0

'V

+70

°e

Storage temperature

Tstg

-55

'V

+150

°e

[NOTE]

-0.3
-0.3

+7.0

V

Vee + 0.3

V

'V

'V

These products have a protection circuit in their input
terminals against high electrostatic voltage or high
electric fields.

Neverthless, be careful not to apply

any voltage higher than the absolute maximum rating to these
high input impedance circuits.
we recommende

To assure normal operation,

Vin' Vout ; VSS ~ (V in or Vout ) ~ Vee

~HITACHI
225

.. ELECTRICAL CHARACTERISTICS
•

DC Characteristics (Vee = 5.0V ± 10%, Vss

GND and Ta

unless otherwise specified)
Item

Symbol

Test
condition

RES , STBY
Input
voltage
"High"

EXTAL

All Inputs

VIL

Wait
lee

Stop

f=lMHz**

Standby
Input
leakage
current

TIMER,
INT,
STBY,D 1"'D 7

IIILI

BO
eO
Go
EO
FO

Input ***
capacity

All
terminals

'"
'"
'"
'"
'"

B7 ,
e 7,
G7 ,
E **
7 '**
F7'

Unit

Vee-0 •5

Vee +0 • 3

V

Vec+0.3

V

Vee+0 .3

V

-0.3

-

0.8

V

-

5

10

rnA

-

2

5

rnA

-

2

10

]JA

2

10

].lA

-

-

1

]JA

-

-

1

]JA

-

-

12

pF

Vin=0.5'"
Vec-°. 5V

Ao '" A7,
Threestate
current

max

2.0

Operating
Current
*
dissipation

typ

Vee xO . 7

VIR

Others
Input voltage "Low"

min

IITSII

e in

f=lMHz,
Vin=OV

* The value at f=XMHz is given by
lee (f=XMHz) = Iee(f=lMHz)xX.

VIH min = Vee - 1.OV, VIL max
For HD63P05YO, lee of EPROM is not included.
** In Standby Mode
*** HD63P05YO is MAX l5pF

~HITACHI
226

0.8V.

•

AC Characteristics (V CC
unless otherwise noted)

Item

•

Symbol

~

= GND,

5.0V ± 10%, Vss

Test
Condition

Ta

=0

~

+70·C,

HD63A05XO/YO
HD63PA05YO

HD6305XO/YO
HD63P05YO

HD63B05XO/YO
1ID63PB05YO

Unit

min

typ

max

min

typ

max

min

typ

max

0.4

-

6

0.4

8

MHz

0.666

-

10

0.5

-

10

~s

Clock
Frequency

fcl

0.4

-

4

Cycle Time

tcyc

1.0

-

10

INT
Pulse Width

tIWL

tcyc
+250

-

-

tcyc
+200

-

-

tcyc
+200

-

-

ns

INT2
Pulse Width

tIWL2

tcyc
+250

-

-

tcyc
+200

-

-

tcyc
+200

-

-

ns

RES
Pulse Width

tRWL

-

-

5

-

-

-

-

tcyc

TIMER
Pulse Width

tTWL

-

-

tcyc
+200

-

-

tcyc
+200

-

-

ns

Oscillation
Start Time
(Crystal)

tosc

CL=22pF±20%
Rs=60fl max

-

-

20

-

-

20

-

-

20

ms

Reset
Delay Time

tRRL

external
capacitance

80

-

-

80

-

-

80

-

-

ms

5
tcyc
+250

2.2~F

Port Characteristics (V CC
unless otherwise noted)

5.0V ± 10%, Vss

Item

Symbol

Output "High" Voltage
Port A, B, C, G,
E, F

VOH

GND, Ta

0

~

5

+ 70·C,

Test Condition

min

typ

max

Unit

2.4

-

V

-

V

IOH

= -200~A

IOH

= -lO~A

Vcc -0.7

-

IOL

= 1.6mA

-

-

0.55

V

Output ''Low'' Voltage

VOL

Input "High" Voltage

VIH

2.0

-

Vcc +0.3

V

VIL

-0.3

-

0.8

V

-1

-

1

~A

Input "Low" Voltage
Input Leakage Current

Port A, B, C, D,
G

IIILI

V.l.n = 0.5
VCC-O .5V

~

~HITACHI
227

•

SCI Timing (VCC = S.OV ± 10%, Vss
unless otherwise noted.)

Item

Symbol

Clock Cylce
Time
Data Output
Delay Time

Test
Condition

= GND,

=0

HD630SXO/YO
HD63POSYO
min
typ

Fig. 6-1
Fig. 6-2

~

+70'C,

HD63AOSXO/YO
HD63PAOSYO
min
max
typ

max

HD63BOSXO/YO
HD63PBOSYO

Unit

m:i.n

typ

max
16384

jJs

2S0

ns

32768

0.67

-

2184S

O.S

-

-

2S0

-

-

2S0

-

-

1

tScyc
tTxn

Ta

Data Set-up
Time

tSRX

200

-

-

200

-

-

200

-

-

ns

Data Hold
Time

tHRX

100

-

-

100

-

-

100

-

-

ns

tscyc
Clock Output
C5/~

2.4V
O.6V

O.6V

O.6V

trxD

2.4V

Data Output
C7/Tx

O.6V

_____

~
~::..~=-------t-HR-X----------~~-:;.;;~-..;..~}'-

Fig. 5-1

__

~::(.,.-----_

SCI Timing (Internal Clock)

tscyc -- ..._--Clock Input
Cs/CK

2.0V
O.8V

O.8V

O.8V

Data output
C.]/Tx

Data Input
C6/Rx

CSRX

tHRX

X

2 OV
.
O.8V

~.~~~

Fig. 5-2 SCI Timing (External Clock)

~HITACHI
228

:~
,I

Vee
TTL Load
(Port)
Test point
terminal

oo--__....___...:lo:L:=:':::;.•6:m:A....
40pF

[NOTES)

2.4kQ

'2kQ

1. The load capacitance includes stary capacitance caused
by the probe, etc.
2. All diodes are 152074

®

Fig. 5-J

'lest Load

~HITACHI
229

5.2

Electrical Characteristics of HD6J05Xl/X2, HD6J05Yl/Y2, HD6JP05Yl
•

ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit

Supply voltage

Vee

Input voltage

Vin

Operating temperature

Topr

0

tV

+70

°e

Storage temperature

Tstg

-55

tV

+150

°e

[NOTE]

-0.3
-0.3

+7.0

V

Vee + 0.3

V

tV

tV

These products have a protection circuit in their input
terminals against high electrostatic voltage or high electric
fields.

Notwithstanding, be careful not to apply any voltage

higher than the absolute maximum rating to these high input
impedance circuits.

To assure normal operation, we recom-

mended Vin' Vout ; VSS ~ (Vin or Vout ) ~ Vee

~HITACHI
230

•

ELECTRICAL CHARACTERISTICS
• DC Characteristics (V CC = S.OV

±

10%, VSS

~

GND, Ta

0

+70°C,

min

typ

max

Unit

VCC-O.S

-

VCC +0.3

V

VCC XO.7

-

VCC+0.3

V

2.0

-

VCC +0.3

V

-0.3

-

0.8

V

2.4

-

-

VCC- 0 . 7

-

-

-

-

O.SS

V

-

-

1.0

lJA

-

-

1.0

lJA

-

S

10

mA

-

2

5

mA

2

10

lJA

-

2

10

lJA

-

-

12

pF

unless otherwise specified.)
Item

Symbol

Test
Condition

RES, STBY
Input
voltage
"High"

EXTAL

VIH

Others
Input voltage "Low"

All Input

VIL

Output
voltage
"High"

All Output

VOH

Output voltage "Low"

All Output

Input
leakage
current

TIMER,
INT,
Dl ~ D7,
STBY

I OH = -20 0lJA
lOW

AO ~ A7'
BO ~ B7,
Co ~ C7 ,
ADRo
~ ADR13, *
DATAO

Threestate
current

VOL

-lOlJA

IOL =1.6mA

IIILI
Vin=O.S

V

~

VCC - O.SV
IITSII

~DATA7'

E*, R/W*
Operating
Current**
dissipation

Wait
ICC

Stop

f = lMHz***

Standby
Input****
capacity
*
**

All
terminals

Cin

f = lMHz,
Vin = OV

At standby mode
VIH min = VCC - 1.OV.

VIL max

0.8 V.

For HD63POSYl,

ICC of EPROM is not included.
***
****

The value at f

xMHz can be calculated by the following equation:

ICC (f = xMHz)

ICC (f = lMHz) multiplied by X.

HD63POSYI is MAX. lSpF

~HITACHI
231

•

AC Characteristics (VCC = 5.0V ± 10%, Vss =GND, Ta = 0
unless otherwise specified.)

Item

Symbol

Test
Condition

HD6305Xl/X2/Yl/Y2
HD63P05Yl

~

+70°C,

HD63A05X1!X2/Yl/Y2 HD63B05Xl/X2/Yl/Y2
HD63PA05Yl
HD63PB05Y1

min

typ

max

min

typ

max

min

typ

Unit

max

Cycle Time

tcyc

1

-

10

0.666

-

10

0.5

-

10

IlS

Enable Rise
Time

tEr

-

-

20

-

-

20

-

-

20

ns

Enable Fall
Time

tEf

-

-

20

-

-

20

-

-

20

ns

Enable Pulse
Width ("High"
Level)

PWEH

450

-

-

300

-

-

220

-

-

ns

Enable Pulse
Width
("Low" Level)

PWEL

450

-

-

300

-

-

220

-

-

ns

Address
Delay Time

tAD

-

-

250

-

-

190

-

-

180

ns

Address Hold
Time

tAH

40

-

-

30

-

-

20

-

-

ns

Data Delay
Time

tDW

-

-

200

-

-

160

-

-

120

ns

Data Hold
Time
(Write)

tRW

40

-

-

30

-

-

20

-

-

ns

Data Set-up
Time (Read)

tDSR

80

-

-

60

-

-

50

-

-

ns

Data Hold
Time (Read)

tHR

0

-

-

0

-

-

0

-

-

ns

Fig. 6-4

~HITACHI
232

•

Port Timing (VCC - 5.0V ± 10%, Vss - GND, Ta
unless otherwise noted.)

Item
Port Data
Set-up Time
(Port A, B,
c, D)
Port Data
Hold Time
(Port A, B,
C, D)
Port Data
Delay Time
(Port A, B,
C)

•

Symbol

INT Pulse
Width

IRT2

Pulse
Width
RES Pulse
Width
Control Setup Time
Timer Pulse
Width
Oscillation
Start Time
(Crystal)
Reset Delay
Time

0

~

HD6305Xl/X2/Yl/Y2
HD63P05Y1
min
typ
max

Test
Condition

tpDS

+70·C,

HD63A05Xl/X2/Yl/Y2 HD63B05Xl/X2/Yl/Y2
HD63PA05Y1
HD63PB05Y1
Unit
min
typ max
min
max
typ

200

-

-

200

-

-

200

-

-

ns

200

-

-

200

-

-

200

-

-

ns

-

-

300

-

-

300

-

-

300

ns

Fig. 6-5
tPOH

tpDW

Fig. 6-6

Control Signal Timing (VCC
unless otherwise noted.)

Item

=

Symbol

= 5.0V

Test
Condition

±

10%, Vss

= GND,

HD6305Xl/X2/Yl/Y2
HD63P05Y1
min
typ
max

-

-

tIWL2

tcyc
+250
tcyc
+250

-

tRWL

5

-

250

-

tcyc
+250

-

-

tIWL

tcs

Fig. 6-8

tTWL

Ta

0

~

+70·C,

HD63A05Xl/X2/Yl/Y2 HD63B05XI/X2/YI/Y2
HD63PA05Y1
HD63PB05Y1
Unit
min
typ max
min
typ
max
tcyc
+200
tcyc
+200
5
250
tcyc
+200

-

-

tcyc
+200

-

-

ns

-

tcyc
+200

-

ns

-

5

-

tcyc

-

-

250
tcyc
+200

-

-

ns

-

ns

tosc

Fig. 6-8*

-

-

20

-

-

20

-

-

20

ms

tRHL

**

80

-

-

80

-

-

80

-

-

ms

* ~ = 22pF±20%, RS
** 2.2 IlF

60n max.

•

HITACHI
233

•

SCI Timing (VCC = 5.0V ± 10%, Vss
unless otherwise noted)

Item

Symbol

Clock Cycle
Time

tScyc

Data Output
Delay Time

t Txn

Data Set-up
Time

tSRX

Data Hold
Time

tHRX

Test
Condition

= GND,

Ta

=0

~

+70°C,

HD6305Xl!X2!Yl!Y2 HD63A05Xl!X2!Yl!Y2 HD63B05Xl!X2!Yl!Y2
HD63PA05Yl
HD63PB05Yl
HD63P05Y1
typ

max

min

typ

max

min

typ

min

1

-

32768

0.67

-

21845

0.5

-

16384

]1s

Fig. 6-9

-

-

250

-

-

250

-

-

250

ns

Fig. 6-10

200

-

-

200

-

-

200

-

-

ns

100

-

-

100

-

-

100

-

-

ns

1---------tCYC---------~

E
PWfH

PWfl

t"

2.4V

Ao--A13
R/W

Address Valid

O.6V
tow

MCU Write
DATAo-DATA7

2.0V

MCU Read
DATAo-DATA7

O.SV

Fig. 5-4

Bus Timing

MCU Read
E

2.4V

\MV~·/

E

etpow
Port
A,B,C,D

Fi,g.

234

5-5

Unit

min

Port
A,B,C _ _ _ _ _ _ _--'

Port Data Set-up and Hold Times
(MCU Read)

$

Fig. 5-6

HITACHI

2.4V
O.6V

Data
Valid

Port Data Delay Time
(MCU Write)

Interrupt
Test

E
Address
Bus
Address
Address Address

PCoPC7
Data Bus
Op
Code

PCe-

Operand Irrelevant
Qp Code Data

CCR ~e~~o, ~;~to,

IX

,-------'/
PC'3

First Inst. of

Add'essAdd,ess Interrupt Routine

......

Fig. 5-7
E
Vee

Interrupt Sequence

~r~\\\\\\\\\\\\\ ~

==:=u-L

~,

: _Io_sc-_-_-_-".-1---+--------<
Vec-O.5V

~~,

________

~~-JI

t-Iosc-J

~JVee-05V

L>__,____

Vee- O.5V

Address

.--I///II////!I/~

Bus

1FFF

r,:J-.~I!WJ

R/W

7lI!llllj}1lllIJljJ

Dala Bus

wa~,_,---------;s,~-{1Nff!l§,}-Fig. 5-8

tscyC

Clock Output
Cs/CK

Reset Timing

.-.------i

2.4V
O.6V

Data Output
C7/Tx

Data Input
C6/ Rx

________

~t
~~~~

Fig. 5-9

-~~_-_-~_~~~~----~:~:----------_

___________t_H_RX__

__

SCI Timing (Internal Clock)

~HITACHI
235

tscvc Clock Input
Cs/C'i<

2.0V
0.8V

Data Output
C7/Tx
)

r

20V~

tHRX

SRX

~2.0V

0.8V

0.8V

Fig. 5-10

:(
.1

SCI Timing (External Clock)
Vee

TTL Load

IOl = 1 .6mA

(Port)

2.4kQ

Test point oo---_--_:::.=~=_J
terminel

c

12kQ

C =90pF for E, R/W, APRo'VADR13,
DATAO'VDATA7
C = 40pF for A, Band C PORT
[NOTES]

1. The load capacitance includes stary capacitance caused
by the probe. etc.
2. All diodes are 1S2074 <8>.

Fig. 5-11

•
236

Test Load

HITACHI

6.

ROM CODE ORDER METHOD
User's programs are mask programmed into ROM by Hitachi to be
shipped as LSI.

The users are requested to hand in three EPROMs in

which the same contents are written, ordering specifications and list
of the ROM contents.
Relationship between the address of the mask ROM and that of the
EPROM is shown in Table 6-1.

Write $FF for the unused address data of

EPROM.
Table 6-1

Relationship between the Address of Mask ROM and
that of EPROM

Type Name

Address of Mask ROM

HD630SXO
HD630SXl

$1000

$000

2

2

$lFFF

$FFF

$0140

$140

2

2

$OFFF

$FFF

$1000

$000

2

2

$lFFF

$FFF

$0140

$0140

2

2

$lFFF

$lFFF

HD630SYO
HD630SYl

HD6305YO
HD6305Yl

Address of EPROM

Remarks
HN482732A or
their equivalent
HN482732A or
their equivalent
HN482732A or
their equivalent
HN482764 or
their equivalent

~HITACHI
237

IAPPENDIX
I.

I

DESIGN PROCEDURE AND SUPPORT TOOL
Cross assembler and Hardware emulator, containing various kinds of
computers, are available as supporting systems to develop user's programs.
Hitachi will mask program user's programs into ROM to ship them as LSI.

Fig. 1-1 shows a typical program design procedure and Table 1-1
summarizes a set of system development supporting tool for the HD6305
MCU.

Text Editor
Host Computer

Cross Assembler
Host Computer

Emuletor
EPROM On-Chlp LSI,
HD63P05Y

Fig. I-I

238

Program Design Procedure

~HITACHI

The following explains the system development procedure.
1.

Specify functional assignment of I/O pins and allocation of RAM
area before starting programming.

2.

Design flowchart to implement the functions and encode this flow·'

3.

Punch the coded format onto cards or paper tape, or write it on a

chart with mnenic codes.
floppy disk.

This set of coded form is a source program.

4.

Assemble the source program to form an object program with
cross system. Then check errors out.

5.

Verify the program through hardware simulation with an emulator
or EPROM on-package microcomputer.

6.

Send the completed program in EPROM to Hitachi.

7.

After Hitachi received user's specified ROM pattern and options,
Hitachi will fabricate sample LSI for user's evaluation for the
functions. If a user finds no problem in the sample LSI,
Hitachi will start mass production of the LSI.
Table I-1 System Development Support

~ol

Type No.

Emulator

EPROM
On-Package LSI

IBM PC
Cross Assembler

HD6305XO/X1/X2
HD630 5YO/Yl/Y2

H35MIX5
(HS35YEML05H)

HD63P05YO/Yl

S35IBMPC

~HITACHI
239

Single Chip Microcomputer ROM Ordering Procedure
(1) Development Flowchart
Single chip microcomputer device is developed according to
the following flowchart after program development.
Remarks

Customer

Hitachi

-«)

x

0

0

x

x

o--x

x~

x

0

0

0

x

o--x

1"-01<»-'"

x

O:ON

Figure 2-9

~

: Change the state

Self Check Connections

•
264

x

HITACHI

2.7

Internal Oscillator Options
The MCU contains two oscillators: oscillator 1 for system clock
supply, and oscillator 2 for time base interruption and LCD drivers.
(1)

Oscillator 1 (OSCl)
The internal oscillator circuit can be driven by connecting a crystal or a
resistor between

X~L

and

EX~L.

A manufacturing mask option is available for

selecting better matching between the external components and the internal
oscillator at start up.
Figure 2-10 shows the connection of oscillator circuit.
A resistor selection graph to determine oscillation frequency of
RC oscillator is given in Figure 2-11.
When RC oscillation, the oscillation can be stopped by mask option
in halt status.
(2)

This saves consuming power when halting.

Oscillator 2 (OSC2)
Clocks are supplied to Timer, Time Base, A/D Converter, and LCD
Drive Circuit from OSC2 by connecting 32.768 kHz of crystal to XIN
and XOUT.

OSC2 operates even in the halt status, which permits

the MCU to implement intermittent action indicating LCD status.
In standby status, this frequency divider stops, while OSC2 keeps

I

on operating to maintain restart time after it has been relieazed
from the instruction.
Figure 2-12 shows the connection between OSCI and 2, while Figure
2-13 and 2-14 shows the relations between them.
Mask options are available for deciding if OSC2 is used or not.
When OSC2 is not used, OSC1/12 will be provided to the peripheral
circui t as 4>32k.
In this case, fix Xin pin to

Vce.

Figure 2-14 shows the combinations of selectable mask-options and
the corresponding system operation statuses.

Refer to this figure

in selecting mask-options on oscillation circuit.

~HITACHI
265

Crystal
Rs-l kSl

EXTAL

EXTAL

=

HD63L05
MCU

XTAL

10pF

HD63L05
MCU

100 kll
Typ.
XTAL

vcc6
RC Oscillator

Crvstal Oscillator

EXTA.L

EXTAL
Ext. Clock

MCU

XTAL

Input

Ext. Clock
Input

XTAL

HD63L05
MCU

Ext. Clock

Ext. Clock

Crystal Option

Resistor Option

Figure 2-10 Mask Option for Oscillator1

,...... 500
N

;';2

'-'

>tJ

I:l
Q)
::l

400
300

I

VCC =3.0V
Ta=25°C

\

\
\"

~

200

...........

0"
Q)

r...'"' 100
0

100

200

300

r---

400

Re sistance

Figure 2-11

--

500

f--.

600

700

( krl )

.Typical Resistor Selection Graph

~HITACHI
266

-

XOUT

Crystal
Rs=20kO=

fCl; frequency of OSC1
1/>32K; C clock for peripheral

HD63L05

XIN

10pF

MCU

veeT
Crystal Oscillator

Time base
Interrupt
LCD
Clock

XOUT
XIN

Vee

HD63L05

MCU

Figure Z-13 Relation between Oscillator1
and Oscillator2

No. U....

Figure 2-12 Connection of Oscillator2

System Operation

Combinations of Mask Option
OSCI Type

OSC2

~ Halt

Other Options
Used

*1

*2
Absent

Crystal
Oscillation

Stand-by

Not
Used
Used

Present

*3

*2
Absent

Stand-by
Not
Used
aSCI
ascillation at
Stand-by

CR
ascnlation
Present

aSCI
ascillation at
Stand-by

aSCI
Stops
aSCI
runs

Delay Time(s)
0 1/16 1/2 1 System
OSCI
x x 0 0
CPU
Peripheral
OSCI
0
0
0
0
CPU
Peripheral
OSCI
x x 0 0
CPU
Peripheral
aSCI
CPU
0
0
0
0
Peripheral
aSCI
x x x CPU
0
Peripheral
aSCI
0
0
0
0
CPU
Peripheral

aSCI x
Stops

x

x

*2
*3

-

At
Stand-by

0

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

-

-

0

x
0
0

x
0
0

x
0
0

x
0

x
x
0
0

x

aSCI
0
x
CPU
Peripheral
0
0 ... run
. Selectable
0
x
x
stop
. Unselectable
In selecting crystal oscillat1on, aSCI cannot be stopped 1n
halt status.
Delay time cannot be accurate without aSC2.
In selecting CR oscillation, stand-by operation is available
for any options.
aSCI
runs

0

0

0

..
..

Note *1

x

At

Figure 2-14 Oscillator2

0

x

x
x

...

Mask~option

and System Operation

$HITAGHI
267

(3)

Stand-by
The MCU goes into stand-by mode when STAND-BY is pulled "High".
In this status, all circuits, except OSC2, stop functioning holding
current status.

(Time Base, Timer, AID Converting Data are not held).

OSC1 restarts oscillating by pulling STAND-BY "Low".

Then the CPU

restarts its operating sequence after delay time for oscillation
stability has passed.
CPU operation must be masked after the CPU has been released from
stand-by mode until OSC1 oscillation is stabilized.
because OSC1 stops functioning in the stand-by mode.

This is
For this

reason, the HD63L05 MCU contains a frequency divider as a delay
circuit, which permits the CPU to gain the accurate delay time if
OSC2 is provided.

Users should be careful when OSC2 is not provided,

because the CPU starts functioning after

~J2k

has been divided by the inter-

nal divider corresponding to the selected delay time. This frequency circuit
also operates just after reset. Don't input

S~D-BY

again during the delay

time, because it will cause the system to malfunction. As a result, delay
time is calculated as:
[(J2768 Hz)/(OSC1)] x delay time.
12
2.8

Interruptions
There are six different interruptions to the MCU: external interruption through external interruption pin (INT), internal timer
interruption, interruption by termination of AID conversion, time base
interruption (2 types), and software interruption by an instruction (SWI).
When any interruption occurs, processing is suspended and the
present MCU status is pushed onto the stack.

The interruption mask

bit (I) in the Condition Code Register is set, the address of the
interruption routine is obtained from the appropriate interruption
vector address, then the interruption routine is executed.

When RTI

instruction has been completed, the MCU continues processing recovering
the MCU status by RTI instruction.

Table 2-1 provides a listing of the

interruptions, their priority, and the vector addresses.

In case a

number of interruptions occurred simultaneously the MCU processes them
according to the priority.
Figure 2-15 shows the system operation flow, in which the portion
surrounded with dot-dash line shows an interruption execution sequence.
Note:

A clear interruption bit instruction (CLI) allows to suspend

the processing of the program by an interruption after execution of
the next instruction while a set interruption bit instruction (SEI)
inhibits any interruptions before execution of the next instruction.

~HITACHI
268

When a mask bit of a control register is cleared by an instruction,
interruption is allowed before execution of the next instruction.
(1)

Acknowledging interruptions in HALT Status
In HALT status, the CPU stops functioning, while the peripheral
circuit are operating.

When an interruption is acknowledged, the

CPU reads the head address of the interruption routine from the
vector address corresponding to the interruption condition.

Then

the CPU executes interruption service to meet the interruption
condition.
(2)

Acknowledging interruptions in Stand-by Status
In Stand-by status, the system stops with power is supplied to it.
Any interruption request (including RES) is therefore, ignored.

Table 2-1
Interruption

Interruption Priority
Priority

Vector Address

RES

1

$FFE, $FFF

SWI

2

$FFC, $FFD

INT

3

$FFA, $FFB

TIMER

4

$FF8, $FF9

AID

5

$FF6, $FF7

TIME BASE

6

$FF4, $FFS

~HITACHI
269

-

Opo'otlon
Soq-

sa,_

Figure 2-15

System Operation Flowchart

~HITACHI
270

2.9

Input/Output (Port A,B,C)
There are 20 input/output pins.

All pins can be programmed

either as inputs or outputs under software control of the Data
Direction Register.

When programmed as outputs, all I/O pins read

output data of the programmed logic level even if the actual output level
is affected by output load (Refer to Figure 2-16).
(1)

Port Configuration
Figure 2-17 shows the port configuration.
Each pin can individually select four types of configurations by
mask option.

The following explains these.

A:

This port configuration is of general type.

B:

This configuration contains pull-up resistance to prevent input
from floating when using the port as an input.

Select this con-

figuration in stich cases as connecting the switch to port
directly.
C:

This port configu1ation is for driving key matrix.

If key

matrix is driven under this port configuration, the CPU can
read the necessary data precisely, even if more than two keys
are pushed simultaneously.
D:

This port configuration is NMOS open drain output, which is
convenient for removing wired OR or driving transistor circuit.
Users should be careful of the maximum output voltage of open
drain output.

Output voltage of open drain output covers from

"OV" to "VCC"·
2.10

A/D Converter
The MCU contains an 8-bit A/D converter based on the resistor
ladder system.

Figure 2-18 shows its block diagram.

The "High" side of reference voltage is applied to VRH ' while the
"Low" side of reference voltage is applied to VRL'
The reference voltage, which is divided by resistors into voltages
matching each bit, is compared with the analog input voltage in order
to implement A/D conversion.
As the analog input voltage is applied to the MOS gate of the
comparator through the analog multiplexer, this voltage comparison
system achieves high input impedance.

~HITACHI
271

AID converter provides two modes; AID conversion mode. and
program comparison mode.
(1)

AID Conversion Mode
This mode allows the MCU to perform AID conversion automatically.
AID conversion starts when AID operating mode selection bit is
initialized to "0". and "1" is programmed to AID conversion flag.
When AID conversion has been completed. AID conversion flag is
automatically reset while AID conversion interruption request
flag is set. In response to this interruption request. the MCU
loads the head address of AID conversion interruption routine.
then executes the interruption routine.

AID interruption can be

masked by setting AID interruption mask bit to "1".
The MCU requires about 2 ms to perform AID conversion itself.
However. the MCU requires 4 ms at most to complete the whole AID
conversion process. because clock generator is multiplexed with
Time Base and LCD drive circuit.
(2)

Program Comparison Mode
This mode allows the MCU to compare the predetermined standard level programmed into the AID data register with the analog input level. When "1"
is programmed in A/D operating mode selection bit, the MCU enters into program comparison mode. Result of the comparison is transmitted to comparison
result output bit by programming the digital value co~sponding to standard
level and by reading A/D control register. "1" is transmitted when analog
input level is higher than standard level, while "0" is transmitted when
analog input level is lower. Note that the NCU wastes more consuming power in
this mode, because supply voltage is supplied with the comparator constantly.
AID converter continues functioning even when halting.

So halt

power does not decrease when AID converter is functioning.

In

stand-by mode, conversion is suspended and comparat'or source power
is off.
AID converter sometimes reperforms AID conversion after being
recovered from stand-by mode.

However, its result cannot be

assured.

$
272

HITACHI

(3)

AID Interruption Request Flag (AID INT)
The AID INT bit is set to logical "1" after AID conversion has

AID INT bit

been completed, and is cleared by system reset.

should be reset by program under interruption subroutine.

Only

logical "0" can be programmed into this bit.

(4)

AID Interruption Mask (AID MASK)
If this bit is set, interruption request from the AID converter
is masked.

(5)

AID Converter Flag (CNV)
Set this bit to logical "1" in order to implement AID conversion.
During conversion, data of this bit holds "1".

The bit is

automatically reset to "0" when the AID conversion has been
completed.

In AID conversion, supply voltage is applied to the

comparator only when CNV="l".

The digital data, which is

obtained by AID conversion, is held in the AID data register.
This data is reset when the CNV is set to "1" again.

(6)

AID Operation Mode Selection Bit (Auto/Program)
This bit selects either auto-run 8-bit AID conversion or 8-bit
programmed comparator operation (Auto 8 bits AID conversion at

"0").

When this bit is reset to "0", the MCU selects the 8-bit

AID conversion mode, then performs AID conversion according to
the value represented by the AID conversion flag.

When this bit

is set to "1", the MCU selects Program Compare Mode, which allows
the program to compare the value between AID data register and
analog input level.
(7)

CaMP OUT
This bit transmits the result of comparator operation between
the standard level at AID register and analog input value
(Logical "1" means that input voltage is higher than programmed
reference voltage).

(8)

MPX
This bit selects 8-channel analog inputs.

The multiplexer is

an analog switch based on CMOS.

~HITACHI
273

8its of
Data
Direction
Regilter

8it Of Out-

put Dlda

0

OutPUt
Stete

Input to

MCU

0

0

3-8ta..

Pin

1

0

Figure 2-16 Port I/O Circuit

Output
Control
Circuit

Output

Input
(A)

~-

Standard port

(B)

PMOS
with
little
lOB

: Pull-up
PMOS

_J

VCC

Port with Input pull-up MOS
NMOS
Output

Output

~---L>O-i~o-.Input

L-Doo--!.::>o--_ Input

Port for Key matrix

(D)

Fig. 2-17

Open drain output

I/O Port Configuration

~HITACHI
274

..,

+---~~~~o-.Input

,..-

Vss

(C)

Output

( )-Ma8k Option
r---"'"'L~-CH,

(CH.l
(CH,1

Multi-

(CHd

plexer

Analog Input

(CH.l

I

Reference
Voltage
Input

L...._ _..J'---(CH.l

MPX

AID CTRL Regl...,

Channel

000

CH,

001

(CH.l

A/D
Interruption

::::::~::::::::::::::::~:::::::::D.QB~

010

(CH,1

011

(CH.l

100

(CH,1

101

(CH.l

110

(CH,1

111

(CH.l

Figure 2-18 8 Bits AID Converter Block Diagram

AID CTRL

';--::-.....L--::-.L-"7"-L.:.:.:~.L--:--L-:-_..,..._,....,JRegilter

Figure 2-19

AID Control Register Configuration

~HITACHI
275

2.11

LCD CIRCUIT
The system configuration of the LCD circuits is shown in Figure
2-20.

1/3 bias-l/3 duty drive, static drive, or output port con-

figuration can be selected in LCD circuit.

This selection can be

specified by both mask option and duty select bit of system control
register.
Segment data for display are stored in data registers (LCDI to
LCDS).

Since the circuits are connected to the output pins through

pin location block, users can specify a combination of datas to be
multiplexed with the segment output pins.

NOTE: In selecting LCD other than 1/3 bias-1/3 duty LCD, specify the Duty
bit within 1 rns since reset has been vectored.
The bit data of the LCD register

(LCDl to LCDS) are combined

with the timing clocks ($1, $2 or $3),and three combined bit data are
gathered to make a segment output data in 1/3 bias - 1/3 duty drive.
In case of static LCD drive or output port, timing is always fixed
to $1 (always "High") and one bit data of the LCD register is
assigned to segment pin.
Note that the output pins (SEGl3 to SEG17) are analog inputs
and mask options.
When the form of output port is selected by Duty bit ("00"),
$WRITE clock and fCL/4 (system clock) can be transmitted every time
data is written into LCDI register by setting EXT bit to "1".

This

signal is also available for connecting the MCU to external circuit
easily.

276

All bits of LCDl, LCDZ, LCD3 register are cleared by reset.

~HITACHI

2.12

Liquid Crystal Driver Waveforms
The LCD circuit is based on 1/3 bias - 1/3 duty driving.

Figure

2-21 shows the common electrode output signal waveforms (COMI' COM2.
COM3). segment signal waveforms (SEGI to SEG17) and LCD bias waveforms
(between COM and SEGMENT).
Assignment of segment pins to the bits of the LCD data register.
including the case in which segment pins are used as output pins. is
to be specified by the user when he orders masks.
(Note) •. The pin function (Vl/CR7 or V2/CRS) can be
mask options.

selected by

In case of 1/3 bias - 1/3 duty drive. select VI and V2

in order to reduce supply impedanc.e.

For your application. connect

0.1 ~F condensors between VI pin and VCC as well as between V2 pin and
VCC. respectively.

SEO,

SEG.
SEO.

SEO.
SEG.
SEG.

lEG.
SEG.
SEG.
SEG ..
SEGu

SEG ..
SEG.I
SEG.I
SEQ ..

Sy.tem
Cont.

SEO,I
SEG n

Duty

seG. -SEG.,

00

OUTPUTPQRT

01

STATIC LCD

Congnuof

10
COM,
COM,
COM,

_...........
Figure 2-20

"

11381..
113 Dutv LCD

10u,,1
LCD Circuit System Configuration

~HITACHI
277

COMMON 1

COMMON 2

COMMON 3

SEGMENT

11,2,31

COM. -SE';MENT

COM. -SEGMENT

COM.-SEGMENT

OUTPUT PORT
Vee

Vss

.._..
...Jr::::'1
.. , .. L:!:

STATIC LCD

Vee

Output levels
fN1ching D•• in
Regilter

Vss

Figure 2-21 LCD Driving Waveforms
2.13

Bit Manipulation

The MCU has the ability to set or clear any single random access
memory or input/output bit (except the data direction registers) with a
single instruction (BSET,BCLR). Any bit in the page zero read only memory
can be tested, using the BRSET and BRCLR instructions,and the program branches
as a result of its state. This capability to work with any bit in RAM,ROM
or I/O allows the user to have individual flags in RAM or to handle single
I/O bits as control lines.
NOTE

It is necessary to pay attention to the system control register,
the timer control register,and A/D control register when BSET,BCLR,or
Read/Modify/Write instructions are applied to them. If own interruption
request occured onto the interruption request bit (bit 7)of the control
register between read cycle and write cycle of these instructions,the
bit7 might be cleared in the write cycle and not acknowledged by CPU •

•
278

HITACHI

2.14

Addressing Modes
The MCU has ten addressing modes available for use by the programmer.
They are explained and illustrated briefly in the fillowing paragraphs.
(1) Immediate
Refer to Figure 2-22. The immediate addressing mode accesses constants
which do not change during program execution. Such instructions are
two bytes long. The effective address (EA) is the PC and the operand is
fetched from the byte following the opcode.
(2) Direct
Refer to Figure 2-23. In direct addressing, the address of the operand
is contained in the second byte of the instruct~on. Direct addressing
allows the user to directly address the lowest 256 bytes in memory.
All RAM space, I/O registers and 128 bytes of ROM are located in page
zero to take advantage of this efficient memory addressing.
(3) Extended
Refer to Figure 2-24. Extended addressing is used to reference any
location in memory space. The EA is the contents of the two byte following
the opcode.Extended addressing instructions are three bytes long.
(4) Relative
Refer to Figure 2-25. The relative addressing mode applies only to the
branch instructions. In this mode the contents of the byte following
the opcode are added to the program counter when the branch is taken.
EA=(PC)+2+Rel. ReI is the contents of the location following the
instruction opcode with bit 7 being the sign bit. If the branch is not
taken, Rel=O. When a branch takes place, the program goes to somewhere
within the range of +129 bytes to -127 of the present instruction.
These instructions are two bytes long.
(5) Indexed (No Offset)
Refer to Figure 2-26. This mode of addressing accesses the lowest
256 bytes of memory. These instructions are one byte long and their
EA is the contents of the index register.
(6) Index (8-bit Offset)
Refer to Figure 2-27. The EA is calculated by adding the contents of
the byte following the opcode to the contents of the index register.
In this mode,511 lowest memory locations are accessibl:. These
instructions occupy two bytes.
(7) Indexed (16-bit Offset)
Refe.r to Figure 2-28. This addressing mode calculates the EA by adding
the contents of two bytes following the opcode to the index register.
Thus.the entire memory space may be accessed. Instructions which use
this addressing mode are three bytes long.
(8) Bit Set/Bit Clear
Refer to Figure 2-29. This mode of addressing applies to instructions
which can set or clear any bit on page zero. The lower three bits in
the opcode specify the bit to be set or cleared while the byte following
the opcode specifies the addresss in page zero •

•

HITACHI
279

(9) Bit Test and Branch
Refer to Figure 2-30. This mode of add~essing applies to instructions
which can test any bit in first 256 locations ($OO-$FF) and branch to
any location relative to the PC. The byte to be tested is addressed
by the byte following the opcode • The individual bit within that byte
to be tested is addressed by the lower three bits of the opcode.
The third byte is the relative address to be added to the program counter
if the branch condition is met. These instructions are three bytes long.
The value of the bit tested is written to the carry bit in the condition
code register.
(10) Implied
Refer to Figure 2-31. The implied mode of addressing has no EA. A11
the information necessary to execute an instruction is contained in the
opcode. Direct operations on accumulator and ,the index register are included
in this mode of addressing. In addition,control instructions such as
SWI,RTI belong to this group. All implied addressing instructions are
one byte long.

.HITACHI
280

l-k I ilir===I__ AF8:: :J
t:
A

Index

:

PRQG LOA .1F8

Rea

I

J

:

Stack Point

05BE.~~A6E3
_____
05BF~
Fa

I

Prot! Count
05C0

CCR

Figure .2-22 Immediate Addressing Example

,,
,,,

Me.torY

CAT FCB 32 OO4B

20

PROG LOA CAT ffi20

B6
4B

,,
,,
,

lEA
OO4B

I

t

/

Adder

,
ffi2E

,

'"

A

00'00

20
I
Index Reg

I
I
,

Stac~

I

ElliDt

Pro!! Count
ffi2F
CCR

I
I
I

~
Figure 2-23 Direct Addressing Example
Memory

,

PROG LOA CAT

~
=rn]I__
O4OB~
,

0000

A
40
Index Reg

...J

:

CAT FCB 64 06E5t:J4Q:O=J----------.J

Stack Point
Prog Count
040C
CCR

Figure 2-24 Extended Addressing Example

~HITACHI
281

Memory

:,

§

A

Index ReI

,

:

r:=J2~7==t-t_.J

PROG BEQ PROG2 04A7
04A8

I-

17

Figure 2-25 Relative Addressing Example
, Me!ory

EA

:,
,,,

,,

I

0068

/

Adder

4C

TABL FCC/LV OOB8

t

Jx)

PROG LOA X

A
4C

I

49

.

~
f

iirlex-~ea

B8

,

Stack POlOt

ffiF<~

Proll Count
ffiF5
CCR

§
,,

Figure 2-26 Indexed (No Offset) Addressing Example

i
i

r\'lcn~Ory

,
TABL

PROG

FCB
FCB
FCB
FCB

:

s: BF

OO~9

BF

s: 86
s: OB

(XJ8A

~6

OOl!B
IICF 008(

,,

LOA T ABL,X 075B
075C

,

DB
CF

,,

I

/

lEA
(lOBC

f
Adder

,,

A
CF
Index Reg

1

03

1

Stack POint

I

8\1

§

~

r

EO

I

I

,

I

I

Prog Count
075E
CCR

,,

Figure 2-27 Indexed (8-Bit Offset) Addressing Example

282

~HITACHI

I
I

I

,, Me!or~' ,

I

D6

0093

I

FCB
FCB
FCB
FCB

II BF 077E

DB
I
Index Reg

I

H6

DB

I
I
I

Prog Count
0695
CCR

I

077F

I

02

Stack t'oint

I

HF

IIDB 0780
IICF 0781

1186

""

A

I
I

h
IJ

07
7E

0694

T ABL

Adder

/'

~

I

I

0780

T

I
I

I

PROG LOA TABL. X 0692

LI::A

I

CF

Figure 2-28 Indexed (16-Bit Offset) Addressing Example

I
I

PORT B EQU I 0001

Me,f,OT"

lEA

§i

T

/

BiI

6

I

~

""

~

,

PROG BCLR 6. PORT B 1581-"

ID

0590

()\

,

~

,,

I
I

A

I
I

Index ReI!

Sl!!£k~n!
Prog
nl
m91
CCR

I
I
I
I

''

e

Figure 2-29

I

0001

I
I

:

Bit Set/Bit Clear Addressing Example

•

HITACHI

283

i

MeirY

,I

PORT C EQU 2 0002

FO

lEA
0002

I
,,

'/
~t

"'ok

,,

I

fROO BRCLR 2. PORT C, PROO 2 (1;74

(I;

(1;75
(1;76

02
10

I
r-----

-i

(XX)()

~l

r-f
,

I

t
Adder

A

I

Index Reg

:~~n!
rog

~'"
,

CCR

C

1
Adder

I

/

,,

~

,
PROG TAX

,

ffiBA~
,,

,,

§
,,
,

Figure 2-31 Implied Addressing Example

•
284

HITACHI

I

(1)94

Figure 2-30 Bit Test and Branch Addressing Example

Memory

:

unt

OR

I

I

2.15

Instruction Set
The MCU has a set of 59 basic instructions.

They can be divided

into five different types: register/memory, read/modify/write, branch,
bit manipulation, and control.
explain each type.

The following paragraphs briefly

All the instructions within a given type are

presented in individual tables.
(1)

Register/Memory Instructions
Most of these instructions use two operands.
either the accumulator or the index register.

One operand is
The other operand

is obtained from memory using one of the addressing modes.

The

jump unconditional (JMP) and jump to subroutine (JSR) instructions
have no register operand.
(2)

Refer to Table 2-2.

Read/Modify/Write Instructions
These instructions read a memory location or a register, modify
or test its contents, and write the modified value back to memory
or to the register.

The test for negative or zero (TST) instruction

is an exception to the read/modify/ write instructions as it
does not perform the write.
(3)

Refer to Table 2-3.

Branch Instructions
The branch instructions cause a branch from the program when a
certain condition is met.

(4)

Refer to Table 2-4.

Bit Manipulation Instructions
These instructions are used on any bit in the first 256 bytes of
the memory.

One group either sets or clears.

performs the bit test and branch operations.
(5)

The other group
Refer to Table 2-5.

Control Instructions
The control instructions control the MCU operations during program
execution.

(6)

Refer to Table 2-6.

Alphabetical Listing
The complete instruction set is given in alphabetical order in
Table 2-7.

(7)

Op-code Map
Table 2-8 is an op-code map for the instructions used on the MCU.

~HITACHI
285

Table 2-2

Register!Memory Instructions
Addressing Mode

Immediate

Operation

Mnemonic

Op
Code

Indexed
(8-B it Offset)

Indexed
(NoOffse"

Extended

Direct

Indexed
(16-8it Offset)

Op
#
#
Op
Op
Op
#
#
#
Op
#
#
#
#
#
#
#
Bytes Cycles Code Bvtes Cycles Code Bytes Cycles Code Bytes Cycles Code Byte. Cycles Code Byte. Cycles

Load A from Memory

LOA

A6

2

2

B6

2

3

C6

3

4

F6

1

2

E6

2

4

06

3

Load X from Memory

LOX

AE

2

2

BE

2

3

CE

3

4

FE

1

2

EE

2

4

DE

3

5

Store A in Memory

STA

-

-

B7

2

4

C7

3

5

F7

1

3

E7

2

5

07

3

6

Store X in Memory

STX

-

-

-

BF

2

4

CF

3

5

FF

1

3

EF

2

5

OF

3

6

Add Memory to A

ADD

AB

2

2

BB

2

3

CB

3

4

FB

1

2

EB

2

4

DB

3

5

AOC

A9

2

2

B9

2

3

C9

3

4

F9

1

2

E9

2

4

09

3

5

Subtract Memory

SUB

AO

2

2

BO

2

3

CO

3

4

FO

1

2

EO

2

4

DO

3

5

Subtract Memory from
A with Borrow

SBC

A2

2

2

B2

2

3

C2

3

4

F2

1

2

E2

2

4

02

3

5

Add Memory and
Carry to A

5

AND Memory to A

AND

A4

2

2

B4

2

3

C4

3

4

F4

1

2

E4

2

4

04

3

5

OR Memory with A

ORA

AA

2

2

BA

2

3

CA

3

4

FA

1

2

EA

2

4

OA

3

5

EOR

A8

2

2

BB

2

3

CB

3

4

FB

I

2

E8

2

4

08

3

5

CMP

Al

2

2

Bl

2

3

Cl

3

4

Fl

1

2

El

2

4

01

3

5

CPX

A3

2

2

B3

2

3

C3

3

4

F3

1

2

E3

2

4

03

3

5

BIT

A5

2

2

B5

2

3

C5

3

4

F5

1

2

E5

2

4

05

3

5

Jump Unconditional

JMP

-

-

-

BC

2

2

CC

3

3

FC

1

2

EC

2

3

DC

3

4

Jump to Subroutine

JSR

BO

2

4

CD

3

5

FO

1

3

ED

2

4

DO

3

5

Exclusive OR Memory

with A

Arithmetic Compare A
with Memory

Arithmetic Compare X
with Memory

Bit Test Memory with
A (Logical Compere)

Symbol.: Op· Operation

-

-

-

ft • Instruction

Table 2-3

Read/Modify/Write Instructions
Addressing Mode

,..._----.Implied (A)
Operation

#

Implied (X)

Mnemonic

Op
Code

Bytes

#
Cvcles

Op
Code

Indexed
(No Offset)

Direct

#

#

Bytes

Cycles

Indexed
(8-Bit Offse"

Op
Code

#

#

#

#

Bytes

Cycles

Op
Code

#

Cycles

Op
Code

#

Bytes

Bytes

Cycle.

Increment

INC

4C

1

1

5C

I

1

3C

2

4

7C

1

3

6C

2

5

Decrement

DEC

4A

1

1

5A

1

1

3A

2

4

7A

I

3

6A

2

5

Clear

CLR

4F

1

1

5F

1

1

3F

2

4

7F

I

3

6F

2

5

Complement

COM

43

1

I

53

1

I

33

2

4

73

I

3

63

2

5

Negate
(2'. Complement)

NEG

40

I

1

50

1

I

30

2

4

70

I

3

60

2

5

Rotate Left Thru Carry

ROL

49

I

1

59

1

I

39

2

4

79

I

3

69

2

5

Rotate Right Thru Carry

ROR

46

1

1

56

1

I

36

2

4

76

1

3

66

2

5

Logical Shift Left

LSL

48

I

1

58

1

I

36

2

4

78

1

3

6B

2

5

Logicel Shift Right

LSR

44

I

1

54

1

1

34

2

4

74

1

3

64

2

5

Arithmetic 5hift Right

ASR

47

1

I

2

4

77

I

3

67

2

5

ASL

48

I

I

57
-SB-

TST

40

1

I

50

Arithmetic Shift Left
Test for Negative or

Zero
Symbols: Op"

~.tion

r 1II

I

-_.-

-

37
.

-

I

36

2

4

7B

I

3

6B

2

5

1

3D

2

4

70

I

3

60

2

5

# .. Instruction

~HITACHI
286

Tab Ie 2-4

Branch Instructions
Relative Addressing Mode

Operation

Mnemonic

Branch Always
Branch Never
Branch IF Higher
Branch IF lower or Same
Branch IF Carry Clear
(Branch IF Higher or Same)
Branch IF Carry Set
(Branch IF lower)
Branch IF Not Equal
Branch IF Equal
Branch IF Half Carry Clear
Branch IF Half Carry Set
Branch IF Plus
Branch IF Minus
Branch IF Interrupt Mask Bit is Clear
Branch IF Interrupt Mask Bit is Set
Branch IF Interrupt line is low
Branch IF Interrupt Line is High
Branch to Subroutine

#

Op
Code
20
21
22
23
24
24
25
25
26
27
2B
29
2A
2B
2C
20
2E
2F
AD

BRA
BRN
BHI
BlS
BCC
(BHS)
BCS
(BlO)
BNE
BEQ
BHCC
BHCS
BPl
BMI
BMC
BMS
Bil
BIH
BSR

#

Bytes
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

Cycles
3
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
2 or 3·
4

Symbol: Op = Oper.tion
# .. Instruction
• If branched, each instruction will be a 3-cvcle instruction.

Tab Ie 2-5

Bit Processing Instructions
Addressing Mode
Bit Set/Clear

Operations

Mnemonic

Branch IF Bit n is Set
Branch IF Bit n is Clear
Set Bit n
Clear Bit n

BRSET n (n = 0 ..... 7)
BRClR n (n = 0 .•... 7)
BSET n In = 0 ..... 7)
BClRn(n=0 ..... 7)

-

-

-

Bit Test and Branch
Op
#
#
Cycles
Bytes
Code
4 or 5·
2· n
3
4 or5·
01 + 2' n
3

10+2'n
11+2'n

2
2

4
4

-

Op
Code

#

#

Bytes

Cycles

-

-

-

Symbol: Op· Oper.tion
# - Instruction
• If Br....ched. each instruction will be • 5-cvcle instruction.

~HITACHI
287

Tab Ie 2-6 Control Instructions
Implied
Mnemonic Op
Code
Transfer A to X
97
TAX
Transfer X to A
TXA
9F
Set Carry Bit
SEC
99
Clear Carry Bit
ClC
98
Set Interrupt Mask Bit
SEI
9B
Clear Interrupt Mask Bit
CLI
9A
Software Interrupt
SWI
83
Return from Subroutine
81
RTS
Return from Interrupt
RTI
80
Reset Stack Pointer
RSP
9C
No-Qperation
NOP
90
Operation

Symbol: Op - Operation

#

#

Bytes Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
4
1
7
1
1
1
1

# .. Instruction

Table 2-7 Instruction Set
Mnemonic
ADC
ADD
AND
ASl
ASR
BCC
BClR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
Bil
BIT
BlO
BlS
BMC
BMI
BMS
BNE
BPl
BRA

Implied Immediate
x
x
x
x
x

ExDirect tended
x
x
x
x
x

Relative

x
x
x

Addressing Modes
Indexed Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)
x
x
x
x
x
x
x
x
x
x
x
x
x

•
•

x
x
x
x
x
x
x
x
x

x

x

x

H

1\

x

x

Bit
Test &
Branch

1\

x

Symbols for condition code:
H
Half Carrv (From Bit 3)
I
Interrupt Mask
N Negal;"" (Sign Bill
Z
Zero

x

x
x
x
x
x
x
x
x

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

I

N

• 1\
• 1\
• 1\1\
•
• 1\
• •
• •
• •
• •
• •
• •
• •
• •
• •
• 1\•
•
• •
• •
• •
• •
• •
• •
• •
• •

Z

C

1\

1\
1\

1\
1\
1\
1\

•
•
•
•
•
•
•
•
•
•
1\
•
•
•
•
•
•
•
•

•

1\
1\

•
•

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

(Continued)
C

1\
•

Carry/Borrow
Test and Set if True, Cleared Otherwise
Not Affected

~HITACHI
288

Condition Code
Bit
Setl
Clear

Tab Ie 2-7

Instruction Set (Continued)

Addressing Modes
Mnemonic
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
CLR
CMP
COM
CPX
DEC
EOR
INC
JMP
JSR
LOA
LOX
LSL
LSR
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STX
SUB
SWI
TAX
TST
TXA

Implied Immediate

Zero

Condition Code
Indexed
Indexed Indexed
(No
(8 Bits) (16 Bits)
Offset)

Relative

Bit
SIlt!
Clear

Bit
Test & H
Branch

x
x
x
x
x
x
x
x
x
x
x
x

x
x
x

x

I<

x

x

x
x
x
x
x
x

x

x

x
x

x

x
x
x
x
x

x
x
x

x
x
x

x

x

x

x
x

x
x
x
x

x
x
x
x
x
x
x
x

x
x
x
x
x
x
x

x

x

x

x

x
x

x

x
x

x
x
x
x

x
x

x
x

x

x

x

x

x
x
x

x
x
x

x
x

x

x

x

x

x

x
x

x
x
x

x
x

x
x

x

x

x
x
x

x

x

x
x

x

x

x
x
x

x

C

A
•
?

I

N

Z

C

• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• 0 • •
• • 0 1

•A

• •
• •

• •
• •
• •
•
•
•
•
•
•
•
•
•

•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•

x

Symbols for condition code:
H Half Carry IFrom Bit 3)
I
Interrupt MesIC
N Negative ISign Bid
Z

Direct

Extended

A

A
A

A
A
A
A

A

•
•
0
•
•

A

1
A

•
•
• A
•
• • • •
• • • •
• A A •
• A A •
• A A A
• 0 A A
• A A A
• • • •
• A A •
• A A A
• A A A
• • • •
? ? ? ?
• • • •
• A A A
• • • 1
1 • • •
• A A •
• A A •
• A A A
1 • • •
• • • •
• A A •
• • • •
A
A

A
A

Carry IBorrow
Test and Set if True, Cleared Otherwise
Not Affected
Load CC Register From Stack

*

HITACHI
289

Tab 1 e 2-8
Bit Manipulation

0
1
2
3
4
5
6
7
8
9
A
B
C
0
E

Set/
Clear

Rei

olR

I

A

0
BRSETO

1
BSETO
BClRO
BSETI
BClRl
BSET2
BClR2
BSET3
BClR3
BSET4
BClR4
BSET5
BClR5
BSET6
BClR6
BSET7
BClR7

2
BRA
BRN
BHI
BlS
BCC
BCS
BNE
BEQ

3

I

4

3/4 or 5
(NOTESI

2/4

BHCC
BHCS
BPl
BMI
BMC
BMS
Bil
BIH
2/20r3 2/4

I
I

X
5
NEG

I XI I .XO
I

6

I

7

-

-

-

TAX
ClC
SEC
Cli
SEI
RSP
NOP
TXA

1/"

1/1

-

-

-

INC
TST

-

[ 2/5

[ 1/3

I

-

[

-

[

BSR"I

2/2

EXT IX2
C

JSR(+11

I
[ 2/3

I

1 l·xo
.Xl

I

0
E
SUB
CMP
SBC
CPX
AND
BIT
lOA
STA (+11
EOR
AoC
ORA
ADD
JMP(-11
JSR
I

I

F

~SR(+1

[ 3/4

[ 3/5

HIGH
0
1
2
3 l
4 o
5 W
6
7
B
9
A
B
C
0
~

E

lOX
STX(+11

F

[ 2/4

1."-" is an undefined operation code.
2. The figure in the lowest row of each column gives the number of bytes and the cycles needed for the instruction.
The number of cycles for the asterisked ("I mnemonics is a follows:
RT!
7
RTS
4
SWI
9
BSR
4
3. The parenthesized figure must be edded to the cycle count of the associated Instruction.
4. If the instruction il branched. the cycle count is the larger figure.

~HITACHI
290

B

9

-

-

A

I

I

IMM

-

-

I

olR

IMP

8
RTI"
RTS"
SWI"

ROR
ASR
lSl/ASl
ROl
DEC

[ 111

IMP

COM
lSR

ClR
[ 1/1

Register/Memory

Control

Read/Modify /Write

Branch

Test &
Branch

BRClRO
BRSETI
BRClRl
BRSET2
BRClR2
BRSET3
BRClR3
BRSET4
BRClR4
BRSET5
BRClR5
BRSET6
BRClR6
BRSET7
F BRClR7

OP Code Map

[ 1/2

3. Executable Instruction
3.1 Symbol and Abbreviation
Shown below are the meaninqs of symbols and abbreviations.
(1) Operation
( ):

contents
movement direction

+:

addition

/\:

subtraction
AND

V:

OR

(±):
x:

Exclusive OR
NOT

(2) Register symbols in MPU
ACCA:

accumulator A

CCR: condition codes register
IX:

index register, 8 bits

pc:

program counter, 12 bits

PCH:

upper three bits of program counter

PCL:

lower eight bits of program counter

SP:

stack pointer, 5 bits

(3) Memory and addressing codes
M:

stored address

MH:

upper eight bits of stored address

ML:

lower ej.ght bits of stored address

M+l:

stored address M plus 1

Msp:

stored address indicated by stack pointer

Imm:

immediate value

Disp:
0:

displacement value = M -

displacement value

=M

-

(IX)

(IX)

DH:

displacement value

upper eight bits

DL:

displacement value

lower eight bits

Rel:

relative value

IMPLIED:

implied addressing

RELATIVE:

relative addressing

ACCUMULATOR:
INDEX REG.:
IMMEDIATE:
DIRECT:
EXTENDED:

accumulator addressing
index register addressing
immediate addressing

direct addressing
extended addressing

INDEXED 0 BYTE OFFSET:

indexed addressing 0 byte offset

INDEXED 1 BYTE OFFSET:

indexed addressing 1 byte offset

~HITACHI
291

INDEXED 2 BYTE OFFSET:
EA:

indexed addressing 2 byte offset

effective address

(4) Contents of bits 0 through 4 of condition codes register
C:

carry - borrow

bit 0

Z:

zero

bit 1

N:

negative
interruption mask

bit 2

I:

H:

half carry from bit 3 to bit 4

bit 3
bit 4

(5) Status of each bit before execution of instruction

.... ,
.... , 0)
.... , 0)

An:

bit n of ACCA (n = 7, 6, 5,

Mn:

bit n of M (n

Xn:

bit n of IX (n= 7, 6, 5,

7, 6, 5,

0)

(6) Status of each bit on result after execution of instruction
Rn: bit n of result (n = 7, 6, 5,
, 0)
( 7) Symbols on instruction's format
P:
each addressing mode on Immediate, Direct, Extended
and index of 0, land 2 bvte offset

....

Q:

each addressing mode on Direct and index of 0 and 1 byte
offset

A:

accumulator addressing mode

X:

index register addressing mode

DR:

direct addressing mode

dd:

relative operand (8 bits)

n:

bi t n of memory (n = 7, 6, 5,

.... , 0)

(8) Status of HD63L05'S interruption pin
INT:
status of interruption pin (high, low)

~HITACHI
292

3.2

Executable Instruction

Arithmetic Operation
ADC

ADC (ADd with Carry)
Format

II

I Conditi~

I

ADCP

R."

I:

~===========1I;:I====================~ N:
Operation

.

Z:

ACCA ... (ACCA) + (M) + (C)

C:

I

Description

C...os

II

Set if there is a carry from
bit 3, otherwise cleared.
Unaffected.
Set if the most significant bit
of the result is set; otherwise
cleared.
Set if the result is 0; otherwise
cleared.
Set if there was a carry from the
most significant bit of the
result; otherwise cleared.

II

Adds the contents of the carry bit C to the sum of the contents of ACCA
and M, and stores the result into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 ,I Byte 2

IMMEDIATE

ADC

Il1mm

A9

Imm

DIRECT
EXTENDED

ADC
ADC

M
M

B9
C9

MH

~;~:~D

ADC

0, X

F9

v Inn

INDEXED 1 BYTE
~E'SET

~~!~D 2 BYTE

ADC

Disp,X

E9

ADC

Disp X

D9

I
I

Byte 3

Number
of
bytes

Number
of CPU
cycles

2

2

2
3

3
4

1

2

I
I

M
ML

D
I

,

DR

DL

2

4

3

5

I

,,

I

Example

II

LOA
ADD
STA
LOA
ADC
STA

VAL2
EXVAL6
EXVAL6
VAll
EXVAL5
EXVAL5

(EXVAL5, EXVAL6)+(VAL1, VAL2)
=(EXVAL5, EXVAL6)

*
*
*
***
*

~HITACHI
293

I

Arithmetic Operation
ADD
ADD (ADD without carry)

'
I

1/

Format
ADDP

:======:::;-1-;:::
I==========~
Operation

ACCA

I

+

(ACCA) + (M)

Description

II

R: Condition Codes
Set if there is a carry from
bit 3; otherwise cleared.
I: Unaffected.
N: Set if the significant bit of the
result is "1"; otherwise cleared.
Z: Set if the result is "0"; otherwise cleared.
C: Set if there is a carry from the
most significant bit a the
result; otherwise cleared.

I

Adds the ACCA contents to the M contents and stores the result into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Operand
type

Mnemonic

Instruction code
Byte 1 : Byte 2

I
I

I

I
I
I
I
I

I

IMMEDIATE
DIRECT
EXTENDED

ADD
ADD
ADD

IN~~~D U BYTE
OFF
INDEXED 1 BYTE

ADD
ADD
ADD

OFF!':F.T
~NDEXED

IIImm
M
M
O,X

2 BYTE

OFFSET

DisD X
Disp,X

AB

BB
CB
FB
EB
DB

I

I

Example

II

LDA
ADD
STA

I
I
I
I
I

:

Imm
M
MH

I

I

I
I

I
I

I

I

VAll
WORK
RESULT

I
I

D
DR

I
I

:

DL

I
I
I

I
I

(VAL1)+(WORK)=(RESULT)

*
*

~HITACHI
294

I

I

I

ML

Number
of CPU
cycles

2

2

2

3

3
4

1

2

2

4
5

I

I
I
I

I
I

Byte 3

Number
of
bytes

3

Logical Operation
AND

AND (logical AND)

I~:

1/

Format

I

AND P

.

N:

~====~========~

II

Operation

ACCA

I

+

Z:
C:

(ACCA) A (M)

Description

Condition Codes

II

Unaffected
Unaffected
Set if the most significant bit of
the result is "1"; otherwise
cleared.
Set if the result is "0" otherwise
cleared.
Unaffected

I

Performs logical AND between the ACCA contents and M contents, and stores
the result into ACCA.

I

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Operand
type

Mnemonic

I

I
I

AND

I
I

AND

M

C4

0
0
0

EXTENDED
~;~;:u

AND

INDEXED 1 BYTE
OFFSET
I~~D Z BYTE
OFF ET

I
I

A4
B4

AND

"IU

Byte 1 :I Byte 2

ffImm
M

IMMEDIATE
DIRECT

u

Instruction code

O,X

F4

I

AND
AND

: Disp,X
I
: Disp,X

E4
D4

I

.
I

Example

0

MH

I
I

I

I
I

Number
of CPU
cycles

2

2

2

3

3

4

0

I
I

ML

I
I

I
I
I

Byte 3

I

I

1

2

2

4
5

I

D
DR

I
I

I

I

I

Imm
M

Number
of
bytes

I
I

I
I

:

.

DL

3

0
0

I
I

II
LDA
AND
STA
INC
BRA

O,X
#$OF
O,X
X
LOOP

ERASE UPPER 4 BITS

*

(RESTORE)

*
*
~HITACHI
295
-~~----.

-_._-.-.--

Shift and Rotation
ASL
ASL (Arithmetic Shift Left)

I

Format

I

I

II

Operation

b.

I

ASL Q
ASL A
ASL X

H:
I:
N:

II

Z:

C:

•

El~1

Condition Codes

I I I I I I I I~

Description

II

Unaffected
Unaffected
Set if the most significant bit of
the result is "1"; otherwise
cleared.
Set i f the resul t is "0"; otherwise
cleared.
Set if the most significant bit
is "1", otherwise cleared.

0

bo

I

Shifts the contents of ACCA, IX or M one bit to the left. The bit 0 is
loaded with "0". The carry bit C is loaded with the bit 7 of ACCA, IX
or M.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
ACCUMULATOR

Mnemonic
ASL

INDEX REG.

I
I

Operand
type

I
I
I
I

A
X

ASL

DIRECT
INDEXED U BYTE
OFFSET
INDEXED I HYTE
OFFSET

Instruction code
Byte 1 :I Byte 2
48
58

ASL
ASL

a,x

38
78

ASL

Disp X

68

M

I

I
I
I
I
I

I
I
I

II

LDA
CHECK ASL
BCS
BITOFF EQU
LDX

I

:

I

I
I
I
I
I

I

WORK
BRANCH FOLLOWING BIT
A
BITON *
7-6-5-4-3-2-1-0

*

#100

~HITACHI
296

D

I
I

I
I

Example

M

I

I

I

Byte 3

I

Number
of
bytes

Number
of CPU
cycles

1

1

1

1

2

1

4
3

2

5

Shift and Rotation
ASR
ASR

(Arithmetic Shift Right)

I Format IJ

I
H:
I:
N:

ASR Q
ASR A
ASR X

I

II

Operation

Z:
C:

,.

[[I I I I I I ]
b,

I

Description

II

Condition Codes

I-+@]

Unaffected
Unaffected
Set if the most significant bit of
the result is "1"; otherwise
cleared.
Set if the result is "0"; otherwisE
cleared.
Set if the least significant bit
is "1" before a shift; otherwise
cleared.

bo

I

Shifts the contents of ACCA, IX or M one bit to the right.
unaffected. The bit o is loaded into the carry bit C.

The bit 7 is

I

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Operand
type

Mnemonic

Byte 1

ACCUMULATOR
INDEX REG.

ASR
ASR

A
X

47
57

DIRECT

ASR

M
O,X
Disp,X

37

IND~D U JUT"

ASR
ASR

OFFSET
~;~~u

J. DlJ:"

Number
of
Byte 3 bytes

Instruction code
Byte 2

1
1

1
1

M

2

4

D

1
2

3
5

77

67

Number
of CPU
cycles

I
I
I
I
I

I

Example

II

ASR
BCS
ASR
BCS
ASR
BCS

WORK
OPTO
WORK
OPTl
WORK
OPT2

BRANCH OPTION (KEEPING BIT7)

*

$

HITACHI
297

Conditional Branch
BCC
BCC (Branch if Carry Clear)
Format

'I

II

BCC dd

I

+

II

Unaffected.

II

Operation
PC

Condition Codes

(PC)+0002+Rel i f (C)=O

Description

I

Tests the state of the C bit and causes a branch if it is "0".
If branched, this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Operand
type

Mnemonic
BCC

ReI

Byte I

Byte 2

24

ReI

I
I
I
I
I
I
I
I
I

I
I
I

I

Exa:mple

II
*

LDA
ADD
BCC

VAL2
EXVAL6
NORMAL

KETA AGARI NASHI

INC

X

KETA AGARI

~HITACHI
298

Number
of
Byte 3 bytes

Instruction code

2

Number
of CPU
cycles
2 or 3

Bit Control
BCLR
BCLR (Bit CLeaR bit n)

I

Format

I

II

Condition Codes
Unaffected.

BCLR n, DR

I

I

II

Operation

Mn ..

II

°

Description

I

Clears the bit n (n

=

0 through 7) of M.

The other bits are unaffected.

I

Addressing Mode and Number of CPU Cycles
Addressing
Mode

.

Mnemonic: Operand
,• type

DIRECT
DIRECT

BCLR
BCLR

O,M
1,M

DIRECT

BCLR

2,M

DIRECT
DIRECT
DIRECT

BCLR
BCLR
BCLR

3 M
4,M
S,M

DIRECT
DIRECT

BCLR
BCLR

6,M
7,M

LOA
AND
ORA
STA
BCLR
BCLR
BCLR

CNTRL
#$FO
WORK
CNTRL
O,CNTRL
6,CNTRL
7,CNTRL

I

Example

II

Instruction code
Byte 1 : Byte 2
•
I
11
M
M
13 ,
15 ,
M
17
19
lB
lD
iF

·
···
·
··
I

I

··•
··

Byte 3

Number
of
bytes

Number
of CPU
cycles

2
2

4
4

2

4

M
M
M

2

4
4
4

M
M

2

2
2
2

4
4

** MAKE CONTROL CODE **
*
*
*

CLEAR BIT 0,6,7 ABSOLUTELY

~HITACHI
299

Conditional Branch·
BCS
BCS (Branch if Carry Set)

II

Format

II

BCS dd

I

+

U

Unaffected

II

Operation
PC

Condition Codes

(PC)+OOO2+Rel i f (C)=l

Description

II

Tests the state of the C bit and causes a branch if it is "1".
If branched. this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Mnemonic
BCS

Instruction code

Operand
type

Byte 1

ReI

25

Byte 2

Byte 3

ReI

2

,,
,
I
I

I

Example

II
*

LOA
ADD
BCS

VAll
EXVAL6
ABNML

KETA AGAR!

STA

EXVAL6

KETA AGAR! NASH!

~HITACHI
300

Number
of
bytes

Number
of CPU
cycles
2 or 3

Conditional Branch
BEQ
BEQ (Branch of EQual)
Format

II

II

BEQ dd

I

+

Ij

Unaffected.

II

Operation
PC

Condition Codes

(pC)+0002+Rel if (Z)=l

Description

I

Tests the state of the Z bit and causes a branch if it is "1".
If branched, this instruction requires 3 cycles.

I

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Mnemonic
BEQ

Operand
type
Rel

Byte 1 I: Byte 2

I
I

I
I

I
I
I
I
I

27

Rel

I
0
0

0

I
0

I
I

0
0

I

0

I

I
I

:,

0

0
0

I

,,

II

LDA
BEQ
CMP
BEQ

WORK
AAAA
RESULT
BBBB

2 or 3

I
I

0

Example

2

Number
of CPU
cycles

0

I

I

Number
of
Byte 3 bytes

Instruction code

,
I

WORK

= 0

WORK

=

RESULT

~HITACHI
301

Conditional Branch
BHCC
BHCC (Branch if Half Carry Clear)
Format

Condition Codes

II

I'

BHCC dd

i

I

II

Unaffected

Operation
PC

I

+

"

(PC)+OOO2+Rel i f (H)=O

Description

I

Tests the state of the H bit and causes a branch if it is "0".
If branched, this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

I

Example

Mnemonic
BHCC

II
DAAH6

*

Operand
type

Instruction code
Byte I

Byte 2

ReI

28

CMP
BLS
LDX

#$9
DAALOW
#$60

DAALOW BHCC
TXA

DAAL9

~HITACHI
302

ReI

Byte 3

Number
of
bytes
2

Number
of CPU
cycles
2 or 3

$99 ---> INPUT
HIGH NYBLE NEEDS CORRECTION

Conditional Branch
BHCS
BHCS (Branch if Half Carry Set)

II

Format

II

BHCS dd

Operation
PC

I

+

Condition Codes

1/

Unaffected.

1/

(pC)+OOO2+Rel i f (H)=l

I

Description

Tests the state of the H bit and causes a branch i f it is l.
If branched, this instruction requires 3 cycles.

I

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

RELATIVE

BHCS

Operand
type
Rel

Instruction code
Byte 1 :I Byte 2
29

I
I

Rel

Byte 3

Number
of
bytes
2

Number
of CPU
cycles
2 or 3

I
I
I
I
I

·
I

·
I
I

I
I

·
·
I
I

I

Example

1/

CMP
BLS
DAAH7 LDX

*

DAALWl BHCS
NAD

#$9
DAALWl
#$60

$99 ---> INPUT
HIGH NYBLE NEEDS CORRECTION

DAAL6
#$F

~HITACHI
303

Conditional Branch
BHI
BHI (Branch if HIgher)
Format

II

Condition Codes

II

BHI dd

I

+-

Unaffected.

II

Operation
PC

II

(PC)+O002+Rel if (C V Z)=O
i.e. i f (ACCA) > (M)
(unsigned binary numbers)

II

Description

Causes a branch if both bit C and bit z are "0".
If the BHI instruction is executed immediately after execution of either of
the instructions CMP or SUB, the branch will occur only if the unsigned
binary number represented by the minuend (i.e. ACCA) was greater than the
unsigned binary number represented by the subtrahend (1. e. M).
This instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles

·

Addressing
Mode

Mnemonic •• Operand
type

RELATIVE

BHI

ReI

Instruction" code
Byte I ,: Byte 2
22

,

·
··
·,
··

ReI

*

·
··
,
·

2 or 3

I

I
I

LDA
CMP
BHI

VAll
VAL2
ZIP25

VAll

>

STA

WORK

VALl

-->

~HITACHI
304

2

I

I

II

Byte 3

Number
of CPU
cycles

I

I

Example

I
I
I
I
I

Number
of
bytes

·,
··
·
:·
··,

I

I

I
I

VAL2
WORK

(IGNORE SIGN BIT)
(LOWER OR SAME)

Conditional Branch
BHS
BHS (Branch if Higher or Same)
Format

II

II

BHS dd

Operation
PC

I

+

Condition Codes

II

Unaffected.

U

(PC)+OOO2+Rel i f (C)=O

I

Description

Following to an unsigned compare or subtract, BHS will cause a branch i f
the register is higher than or the same as the location in M.
If branched, this instruction requires 3 cycles.

I

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

RELATIVE

BHS

Operand
type
ReI

Instruction code
Byte I :I Byte 2
24

I
I

.

Byte 3

ReI

Number
of
bytes
2

Number
of CPU
cycles
2 or 3

I
I

I
I

I
I
I
I

I
I
I
I
I
I

I

Example

II
*

LDA
CMP
BHS

VAll
VAL2
ZIP26

VALl

>=

STA

WORK

VAll

--->

VAL2

IGNORE SIGN BIT

WORK (LOWER)

~HITACHI
305

Conditional Branch
BIB
BIB (Branch if Interrupt line is Bigh)

1/

Format

Condition Codes

II

BIB dd

II

Unaffected.

~====~========~
Operation

II

PC

I

+

(PC)+O002+Rel if INT-l (high)

Description

)1

Tests the state of the external interrupt pin (00) and causes a branch
if it is high.
If branched. this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Mnemonic

Operand
type

BIB

Number
of
Byte 3 bytes

Instruction code
Byte 1

Rel

Byte 2

2F

Rel

2

,
:,

,,
,,

I

Example

II

BIH
INTLl LDA
BRA
INTHO LDA
NEXT2 STA

INTHO
#$28
NEXT2
#$FF
PIA

INT LINE CHECK
OUTPUT DATA = $28
OUTPUT DATA
OUTPUT

~HITACHI
306

= $FF

Number
of CPU
cycles
2 or 3

Conditional Branch
BIL
BIL (Branch if Interrupt line is Low)
Format

II

Condition Codes

II

BIL dd

II

Unaffected.

~====~========~

II

Operation

PC

I

+

(PC)+O002+Rel if INT=O (low)

Description

II

Tests the state of the external interrupt pin and causes a branch if it is
low.
If branched, this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Mnemonic
BIL

Operand
type
Rel

Number
of
Byte 3 bytes

Instruction code
Byte 1 ,: Byt.e 2
2E

,I
,,
,
:
,,
,,

.

Rel

2

Number
of CPU
cycles
2 or 3

,
,,
I

,,

I

Example

II

BIL
INTH3 LDA
BRA
INTL2 LDA
NEXT4 STA

INTL2
#$45
NEXT4
#$0
PIA

INT LINE CHECK
OUTPUT DATA = $45
OUTPUT DATA = $00
OUTPUT

~HITACHI
307

Logical Operation
BIT
BIT (BIt Test)

II

Format

II ~:

BIT P

II

Operation

Z:

(ACCA) I\. (M)
C:

I

Description

Condition Codes

1/

Unaffected.
Unaffected
Set if the most significant bit of
the result of the AND is "1";
otherwise cleared.
Set if all the bits of the result
of the AND are "0"; otherwise
cleared.
Unaffected.

I

Performs the logical AND operation of the ACCA contents and the M contents
and modifies the respective condition codes. The contents of ACCA and
M are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

IMMEDIATE

BIT

IIImm

A5

BIT
BIT

M
M

B5
C5

~;~~u u Iml<

BIT

X

F5

UWI<"",D .I. ISITI<

OFFSET
lND=D L

BIT
BIT

BYTE

DisD.X
Disp,X

Imm

2

2

M
ML

2
3

3
4

1

2

2
3

4
5

Byte 1 :I Byte 2

DIRECT
EXTENDED

OFFSET

Byte 3

Number
of
bytes

Instruction code

E5
D5

I
I
I
I

·
·
·
I

MH

I

I
I

I
I

D
DR

DL

I
I
I
I

I

Example

II

EVBIT

*

NG

308

LDA
BIT
BEQ

VAll
OK

0

LDA
JMP

ERROR

#227

SET ERROR NUMBER

#$FS

= BIT ASSIGN (VALl)

~HITACHI

<=7

Number
of CPU
cycles

Conditional Branch
BLO
BLO (Branch if LOwer)
Format

1/

II

BLO dd

Operation
PC

I

+

Condition Codes

1/

Unaffected.

II

(PC)+O002+Rel if (C)=l

Description

I

Following to a compare, BLO will cause a branch if the register is lower
than the memory location.
Equivalent to the BCS executable instruction.
If branched, this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

I

Example

Mnemonic

I
I

Operand
type

Number
of
Byte 3 bytes

Instruction code
Byte 2

Byte I

BLO

ReI

25

ReI

LOA
CMP
BLO

VAll
VAL2
ZIP27

VAll

<

STA

WORK

VAll

-->

2

Number
of CPU
cycles
2 or 3

1/
*

VAL2 (IGNORE SIGN BIT)
WORK HIGHER OR SAME

~HITACHI
309

Conditional Branch
BLS
BLS (Branch if Lower or Same)
Format

II

Condition Cod'es

II

BLS dd

Operation

II

Unaffected.

"--

IJ

PC .... (PC)+O002+Rel if (C V Z)=l
i.e. if (ACCA) ~ (M)

I

I

Description

Causes a branch if either C or Z is "1".
If the BLS instruction is executed immediately after execution of either of
the instructions CMP or SUB, the branch will occur only if the unsigned
binary number represented by the minuend (i.e. ACCA) is less than or equal
to the unsigned binary number represented by the subtrahend (i.e. M).
If branched, this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

I

Example

II
*

Instruction code
Byte 1

BLS

ReI

23

LOA
CMP
BLS

VAll
VAL2
ZIP28

VAll <= VAL2 IGNORE SIGN BIT

STA

WORK

VALl

Byte 2

Byte 3

ReI

--->

~HITACHI
310

Number
of
bytes

Operand
type

Mnemonic

WORK (HIGHER)

2

Number
of CPU
cycles
2 or 3

Conditional Branch
BMC
BMC (Branch if interrupt Mask is Clear)

II

Format

II

BMC dd

I

~

IJ

Unaffected.

II

Operation
PC

Condition Codes

(pC)+0002+Rel if (1)=0

Description

I

Tests the state of the I bit and causes a branch if I is "0".
If branched, this instruction requires 3 cycles.

I

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Mnemonic

I
I

I
I

I

BMC

Operand
type
Rei

Instruction code
Byte 1 :I Byte 2
2C

I
I

Rei

Byte 3

Number
of
bytes
2

Number
of CPU
cycles
2 or 3

I

I
I
I
I

,

,I
I
I

I
I
I
I
I
I

I

Example

II

BMe
BIL
LDA
STA
MSKOFF RTS

MSKOFF
MSKOFF
PIA
WORK

INTMSK OFF?
INT LINE LOW?
READ DATA

~HITACHI
311

Conditional Branch
BMI
BMI (Branch i f MInus)

II

Format

II

BMI dd

i
I

I

+

1/

Unaffected.

II

Operation
PC

Condition Codes

(PC)+OOO2+Rel i f (N)=l

II

Description

Tests the state of the N bit, and causes a branch if N is "1".
If branched, this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 : Byte 2
I

RELATIVE

BMI

Rel

2B

I

Byte 3

Rel

I
I
I
I

:
I
I
I
I

I
I
I
I
I
I

I

Example

II
*

LDA
BMI

VAll
ZIP29

VAll

<

STA

WORK

VAL

--->

~HITACHI
312

0
WORK (PLUS)

Number
of
bytes
2

Number
of CPU
cycles
2 or 3

Conditional Branch
BMS
BMS (Branch if interrupt Mask is Set)
Format

II

Condition Codes

II

BMS dd

II

Unaffected.

~====~==========~

II

Operation

PC

I

+

(PC+0002+Re1 if (1)=1

Description

II

Tests the state of the I bit and causes a branch if I is "1".
If branched, this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
RELATIVE

Operand
type

Mnemonic
BMS

Re1

Instruction code
Byte 1 II Byte 2
2D

I
I

Re1

Byte 3

Number
of
bytes
2

Number
of CPU
cycles
2 or 3

.
I

.
I

I

Example

II
MSKOFl
MSKONl

BMS
RTS
BIL
LDA
STA
RTS

MSKONl
MSKOFl
PIA
WORK

INTMSK ON?
NO
INT LINE LOW?
DATA

~HITACHI
313

I

Conditional Branch
BNE
BNE (Branch if Not Equal)

II

Format

II

BNE dd

i

I

I

+

II

Unaffected.

II

Operation
PC

Condition Codes

(PC)+0002+Rel if (Z)=O

Description

I

Tests the state of the Z bit and causes a branch if Z is "0".
Following to a compare or subtract instruction, BNE will cause a branch
if the contents are different.
If branched, this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

I
I
I
I

Operand
type

I

RELATIVE

BNE

,
I

ReI

I
I
I

I

I
I
I

I

I

I
I

I
I

I
I

WORK
CCCC
RESULT
DDDD

WORK NOT

~

0

WORK NOT

~

RESULT

~HITACHI

Number
of
bytes
2

I

I

314

ReI

.

I
I
I
I

LDA
BNE
CMP
BNE

I

Byte 3

I
I
I
I

I

II

I
I

I
I
I

Example

Byte I I: Byte 2
26

I
I

I

Instruction code

Number
of CPU
cycles
2 or 3

Conditional Branch
BPL
BPL (Branch if PLus)

II

Format

Condition Codes

BPL dd

IJ

Unaffected.

~====~========~
Operation

II

PC

I

+

(PC)+O002+Rel if (N)=O

Description

IJ

Tests the state of the N bit, and causes a branch if N is "0".
If branched; this instruction requires 3 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

RELATIVE

Operand
type

Number
of
Byte 3 bytes

Instruction code
Byte I

BPL

ReI

2A

LOA
BPL

VALl
ZIP3l

VAL

STA

WORK

VALl

Byte 2
ReI

2

Number
of CPU
cycles
2 or 3

-.

I

Example

II
*

>=

0

--->

WORK (MINUS)

~HITACHI
315
--------"-------"-"--~

Unconditional Branch
BRA
BRA (BRanch always)
Format
BRA dd

I

+

II

"

II

Unaffected.

II

Operation
PC

Condition Codes

(PC)+OO02+Rel

Description

I

Causes an unconditional branch to the address given by the above expression.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic
BRA

RELATIVE

Operand
type
ReI

Instruction code
Byte I :I Byte 2
20

I
I

.
.

Byte 3

ReI

I
I
I
I

I
I
I
I
I
I
I
I
I
I

I

Example

II
*

LOA
STA
BRA

CHECKS EQU

EXVAL5
RESULT
ENOOl

BRANCH TO ENOOl ALWAYS

*
~HITACHI

316

Number
of
bytes

Number
of CPU
cycles

2

3

Conditional Branch
BRCLR
BRCLR (BRanch if bit n is CLeaR)

I Format II

I
H:

BRCLR n, DR, dd

/

PC

/

+

I:
N:
Z:
C:

II

Operation

Condition Codes

1/

Unaffected.
Unaffected.
Unaffected.
Unaffected.
Set i f (Mn)=l; otherwise cleared.

(PC)+O003+Rel if (Mn)=O

]

Description

\

Tests the bit n (n = 0 through 7) of M and causes a branch if the Mn
contents are O.
If branched, each instruction requires 5 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

/

Mnemonic

Operand
type

Byte 1 ,: Byte 2
I
01 , M
,,
03 , M

RELATIVE
RELATIVE
RELATIVE

BRCLR
BRCLR
BRCLR

O,M,Rel
1,M,Rel
2,M,Rel

RELATIVE

BRCLR

3,M,Rel

07

RELATIVE
RELATIVE
RELATIVE
RELATIVE

BRCLR
BRCLR
BRCLR
BRCLR

4,M,Rel
5,M,Rel
6,M,Rel
7,M,Rel

09
OB
aD
OF

Example

II
*

Number
of
Byte 3 bytes

Number
of CPU
cycles

Instruction code

as

,
:
,I
,,
,I
,,
,,

M

ReI
ReI
ReI

3
3
3

4 or 5
4 or 5
4 or 5

M

ReI

3

4 or 5

M
M
M
M

ReI
ReI
ReI
ReI

3
3
3
3

4
4
4
4

or
or
or
or

5
5
5

5

CNTRL
** SET CONTROL CODE **
#$OF
WORK
CNTRL
** ACTION **
BRCLR 4,CNTRL,ENGINE
BRCLR 7,CNTRL,GASCHK

LDA
AND
ORA
STA

~HITACHI
317

I

Unconditional Branch
BRN
BRN (BRanch Never)

II

Format

II

BRN dd

I

+

II

Unaffected.

II

Operation
PC

Condition Codes

(PC)+OOO2

Description

II

BRN is included here to demonstrate the nature of branches on the HD63L05 MCU.
Each branch is matched with an inverse that varies only in the least
significant bit of the opcode. BRN is the inverse of BRA. This
instruction may have some use during program debugging.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

RELATIVE

BRN

Operand
type
ReI

Instruction code
Byte 1 :I Byte 2
21

I
I

ReI

I
I

,

,,
I

I
I
I
I
I
I

,
I

,
I

I

Example

II
*

STX

4.X

BRN
BRN
BRN
BRN

*
*
*
*

** DELAY **

~HITACHI
318

Byte 3

Number
of
bytes

Number
of CPU
cycles

2

2

Conditional Branch
BRSET
BRSET (BRanch if bit n is SET)

I

I Format II

H:

BRSET n, DR, dd

I

PC

I

+

I:

N:
Z:
C:

II

Operation

Condition Codes

II

Unaffected.
Unaffected.
Unaffected.
Unaffected.
Set i f (Mn)=l; otherwise cleared.

(pC)+0003+Rel i f (Mn)=l

Description

I

Tests the bit n (n =
Mn contents are "I".

o

through 7) of M, and causes a branch if the

If branched, each instruction requires 5 cycles.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Byte 1 :I Byte 2

,I

RELATIVE
RELATIVE

BRSET
BRSET

o M ReI
I,M, ReI

00
02

RELATIVE
RELATIVE

BRSET
BRSET

2,M,Rel
3,M,Rel

04
06

RELATIVE

BRSET

4,M,Rel

08

,,

RELATIVE

BRSET

5,M,Rel

OA

I
I

M

RELATIVE
RELATIVE

BRSET
BRSET

6 M ReI
7,M,Rel

OC
OE

I

M
M

LOA
AND
ORA
STA

CNTRL
#$8E
WORK
CNTRL

BRSET
BRSET

O,CNTRL, OIL
7,CNTRL, GAS

I

Example

II
*

PROCl
PROC2

Byte 3

Number
of
bytes

ReI
ReI

3
3

4 or 5
4 or 5

ReI
Rel

3
3

4 or 5
4 or 5

I

ReI

3

4 or 5

,
,,
,

ReI

3

4 or 5

ReI
Rel

3
3

4 or 5
4 or 5

instruction code

,,
,,,
I

,
I

,

,
I

M
M

I
I
I
I

,
,I
I

I

M
M

I

M

,,,

I
I
I

,

,

I

Number
of CPU
cycles

I

** SET CONTROL CODE **
** ACTION **

~HITACHI
319

Bit Control
BSET
BSET (Bit SET bit n)

I Format II

I

Condition Codes

BSET n, DR

I

I

+-

Unaffected.

IJ

Operation
Mn

II

1

II

Description

(

Sets the bit n (n .. 0 through 7) of M.

All other bits are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Byte 1

Byte 2

I
I
I
I

DIRECT

BSET

O,M

10

M

DIRECT
DIRECT
DIRECT
DIRECT

BSET
BSET
BSET
BSET

I,M
2,M

12
14
16
18

M
M
M
M

I

DIRECT
DIRECT
DIRECT

BSET
BSET
BSET

S,M

lA
lC
IE

M
M
M

,
,,
,

LOA
BPL

RESULT
PLUS

BSET
BSET
EQU
LOA

2,CNTRL
3 ,WORK

I

Example

-

II
*
PLUS

3,M
4,M
6 M
7,M

(MINUS)

*

VAL2

~HITACHI
320

Number
of
Byte 3 bytes

Instruction code

I

I

I
I

I
I

I
I
I

I

Number
of CPU
cycles

2

4

2
2
2
2

4
4

2

4
4

2
2

4
4

4

Subroutine Control
BSR
BSR (Branch to SubRoutine)

II

Format

II

BSR dd

I

+
+
+
+

Ir

Unaffected.

II

Operation
PC
Msp
Msp
PC

Condition Codes

(PC)+OOO2
(PCL), SP
(PCR), SP
(PC)+Rel

+
+

(SP)-OOOl
(SP)-OOOl

I

Description

The less significant byte of the
The program counter is increased by "2".
contents of the program counter is pushed onto the stack. The stack pointer
The more significant byte of the contents of the
is then decreased by "1".
program counter is then pushed onto the stack. Unused bits in the Program
Counter high byte are stored as l's on the stack. The stack pointer is
A branch then occurs to the address specified by
again decreased by "1".
the program counter.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 : Byte 2
I

RELATIVE

BSR

Rel

AD

I

Rel

I

Byte 3

Number
of
bytes

Number
of CPU
cycles

2

4

I
I

,
,,
I

I
I
I
I

I
I
I
I
I
I

I

Example

II
*

LOA
BSR

#$3B
HAND

ACCA

=

INTERFACE(OOll 1011)

LOA
BSR

#$lE
FING

ACCA

=

INTERFACE(OOOl 1110)

~HITACHI
321

Bit Control
CLC
CLC (CLear Carry)

iF:' II

1\

I~======~============~
Operation II

Z:

c:

Condition Codes
Unaffected.
Unaffected.
Unaffected.
Unaffected.
Cleared.

C + 0

I

I

Description

Clears the carry bit C in the condition code register.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Operand
type

Mnemonic

IMPLIED

Instruction code
Byte 1 :I Byte 2

98

CLC

Byte 3

,
I
I

,I
I

:
,
,
I

I

,
I

,

I

I

I

I

I
I

I

I

Example

II

BNE
STA
CLC
RTS

CHK83
RESULT

I
I

RETURN CODE SET 'OK '

*
*
eH1TACHI
322

I

Number
of
bytes

Number
of CPU
cycles

1

1

Bit Control
CLl
CLI (CLear Interrupt mask)
Format

II

II.,

II

Condition Code.

II

CLI

Operation
I+-O

I

II

Description

Clears the interruption mask bit in the processor condition code register.
This enables the MCU to service interruptions. Interruptions that were
pending while the I bit was set will now begin to have effect.

Addressing Mode and Number of CPU Cycles
Addre88ing
Mode
IMPLIED

I

Example

II

I

Mnemonic

Operand
type

Instruction code
Byte 1

Byte 2

Byte 3

CLI

9A

SEI
RSP
JSR
CLI

INTERRUPT DISABLE
RESET STACK POINTER
SYSTEM INITIALIZE
INTERRUPT ENABLE

SYSINZ

Number
of
bytes

Number
of CPU
cycles

1

1

~HITACHI
323

Arithmetic Operation
CLR
CLR (CLeaR)

,

I

I Format II
CLR Q
CLR A
CLR X

I

Condition Codes

H:

I:
N:
Z:

II

Operation

C:

II

Unaffected
Unaffected.
Cleared.
Set.
Unaffected.

IX -+- 0
or
ACCA -+- 0
or
M-+-O

I

Description

II

The contents of IX, ACCA or M are replaced with "0".

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 ,: Byte 2

ACCUMULATOR

CLR A

4F

,

INDEX REG.

CLR X

SF

:,

DIRECT
~;~~1J U

ISUIS

~:~D 1 BYTE

CLR
CLR

,x

3F
7F

CLR

DiEiP.X

6F

M

Byte 3

I
I

:
,I
,,

M
D

I
I

,
I
I
I

I

Example

"

*

CLR
CLR
CLR
CLR

PNTR
PNTR+l
D,X
A

** INITIALIZE **

.HITACH.I.
324

Number
of
bytes

Number
of CPU
cycles

1

1

1

1

2

1

4
3

2

S

Comparison and Test
CMP
CMP (CoMPare)
Format

II

IR: Condition Codes II

I

CMP P

I:
N:

~============~======================~

II

Operation

Z:
C:

(ACCA)-(M)

I

Description

Unaffected.
Unaffected.
Set if the most significant bit
of the result of the subtraction
is "1"; otherwise cleared.
Set if the result of the subtraction is "0"; otherwise cleared.
Set if the absolute value of
memory is greater than the
absolute value of the accumulator;
otherwise cleared.

I

Compares the ACCA contents and the M contents, then sets the condition
codes which may then be used for controlling the conditional branches.
Both uperands are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Operand
type

Instruction code
Byte 1

Byte 2

Byte 3

Number
of
bytes

Number
of CPU
cycles

IMMEDIATE

CMP

IIImm

A1

Imm

2

2

DIRECT
EXTENDED

CMP
CMP

M
M

Bl
C1

M

2
3

3

CMP

X

F1

1

2

CMP
CMP

Di"'l> X
Disp,X

E1
D1

2
3

4
5

i~~~D U BYTE

OF S
iNDEXED 1. BYTE
OFFSET
~;~::D ~ BYTE

I

Mnemonic

Example

II

*

LOA

PNTR,X

CMP
BEQ
CMP
BEQ
BRA

#'A
SECTA
#'B
SECTB
INPUT

MH

D
DR

ML

DL

4

ACCA = 'A'
ACCA = 'B'

~HITACHI
325

Logical Operation
COM
COM (COMplement)

I

Format

I

II

H:

COM Q
COM A
COM X

I

I:
N:

II

Operation

Z:

IX +- (IX) = $FF-(IX)
or
ACCA +- (ACCA) = $FF-(ACCA)
or
M +-(M) = $FF-(M)

I

Condition Codes

Description

C:

II

Unaffected.
Unaffected.
Set if the most significant bit
of the result is "1"; otherwise
cleared.
Set if the result is "0"; otherwise cleared.
Set.

I

Replaces the contents of ACCA, IX or M with its l's complement.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

,

Instruction code

Mnemonic:, Operand
type

Byte 1 ,: Byte 2

I

ACCUMULATOR
INDEX REG.

COM
COM

DIRECT

COM

1l'ouEXED u BYTE
OFFSET
~~~~D 1 BYTE

COM
COM

I

I
I
I
I

,
I

A
X

53

M

33

,,
,
:

73

,I

43

X
Disp,X

63

I

M

I
I

D

Byte 3

Number
of
bytes

Number
of CPU
cycles

1
1

1
1

2

4

1

3

2

5

I
I

,
,
I
I

I

Example

II

*

SUBIN

EQU
INC
LDA
COM
RTS

*

X

PNTR, X
A

MODIFY DATA (REVERSE)

*
~HITACHI
326

Comparison and Test
CPX
CPX (ComPare indeX register)
Format

II

IR •. Condition Codes IJ

I

CPX P

I:
N:

:=======;-;::===========~

II

Operation

Z:

(IX)-(M)

I

C:

Description

Unaffected.
Unaffected.
Set if the most significant bit
of the result is "1"; otherwise
cleared.
Set if the result is "0"; otherwise cleared.
Set if the absolute value of the
contents of the memory is greater
than the absolute value of the
contents of IX; otherwise cleared.

I

Compares the IX contents with M contents. The condition code can be
collated by means of the next conditional branch instruction. Both
operands are unaffected.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 I: Byte 2

I
I

I

I
I

IMMEDIATE
DIRECT

CPX
CPX

IIImm
M

A3
B3

EXTENDED

CPX

M

C3

:

F3

I
I

u,DEXED 0 BYTE
OFFSET
INDEXED 1 BYTE
OFFSET
INDEXED Z BYTE
OFFSET

CPX

,X

CPX

Disp,X

E3

CPX

Disp,X

D3

Imm
M

I
I
I
I
I

Byte 3

I

I

MH

ML

I

I

D

I
I

DR

DL

Number
of
bytes

Number
of CPU
cycles

2
2

2
3

3

4

1

2

2

4

3

5

I

I
I
I

I

Example

'I

LOA
LOX
CPX
BEQ
CPX
BEQ

#$CC
PNTR
#$00
CR
#$OA
LF

ACCA

=

INTERFACE TO CR OR LF

CARRIAGE RETURN
LINE FEED

~HITACHI
327

Arithmetic Operation
DEC
DEC (DECrement)

I

Format

I

1/

DEC Q
DEC A
DEC X

I

H:
I:
N:

II

Operation

Z:

IX

-<- (IX)-Ol
or
ACCA -<- (ACCA)-Ol
or
M -<- (M)-Ol

I

Condition Codes

Description

C:

II

Unaffected.
Unaffected.
Set i f the most significant bit of
the result is "1"; otherwise
cleared.
Set i f the result is "0"; otherwise cleared.
Unaffected

I

Subtracts "1" from the contents of ACCA, IX or M.
Nand Z bits are set and reset according to the result of this operation.
C bit is unaffected by this operation.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 ,: Byte 2

ACCUMULATOR

DEC

A

4A

INDEX REG.
DIRECT

DEC
DEC

X
M

5A
3A

INDEXED 0 BYTE
OFFSET
INDEXED 1. BYTE
OFFSET

DEC
DEC

,X
Disp_,X

7A
6A

,I
,,
,
,
:
,:
,,

,
,,
,,
I

I

Example

II

*

LOOP23 DEC
BMI
LDX
STX
INC
BRA

*

NEXT

EQU

** MOVE **
A
NEXT
O,X
$100,X
X
LOOP23

*
*
*

*
~HITACHI

328

M

Byte 3

Number
of
bytes

Number
of CPU
cycles

1

1

1

1
4

2

1
D

2

3
5

Logical Operation
EOR
EOR (Exclusive OR)

'~.:.
I

1/

Format
EOR P

Condition Codes

N:

:======~-;::==========~

II

Operation

ACCA

,

+

Z:
C:

(ACCA) ED (M)

Description

II

Unaffected.
Unaffected.
Set if the most significant bit
of the result is "1"; otherwise
cleared.
Set if the result is "0"; otherwise cleared.
Unaffected.

I

Performs the logical EXCLUSIVE OR between the ACCA contents and M contents
and stores the result into ACCA.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

,

I
Mnemonic , Operand
I
type

IMMEDIATE
DIRECT

EOR
EOR

EXTENDED

EOR
EOR

~~~~~D 0 BYTE
INDEXED 1 BYTE

I

Byte 1 ,: Byte 2

I
I

,

flImm

,
M
,, M
,,
,, ,X
I

AS
BS
CS
FS

OFF~F'1'

EOR

: Disp,X

INUt;llliU Z llYn,;
OFFSET

EOR

: Disp, X

ES

I

,

DS

I

Example

II

*

Number
of CPU
cycles

I

,,
,
,,

2
2

2
3

,I
,,

ML

3
1

4
2

I
I

2

4

DL

3

5

,

Byte 3

Imm
M
MH

D
DR

I

,,

I

Number
of
bytes

Instruction code

,,

LDA
EOR
STA
BRA

** ARRANGE CONTROL CODE **
xxx x XXXX

CNTRL
#$99

CNTRL
ACTOl

1001 1001

~HITACHI
329

Arithmetic Operation
INC
INC (INCrement)

I

I

II

Format

H:
I:
N:

INC Q
INC A
INC X

I

II

Operation

Z:

IX

+- (IX)+Ol
or
ACCA +- (ACCA)+Ol
or
M +- (M)+Ol

I

Condition Codes

Description

C:

II

Unaffected.
Unaffected.
Set if the most significant bit
of the result is "1"; otherwise
cleared.
Set if the result is "0"; otherwise cleared.
Unaffected.

I

Adds "1" to the contents of ACCA, IX or M.
Nand Z bits are set or reset according to the result of this operation.
The C bit is not affected by this operation.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Operand
type

Instruction code
Byte 1 : Byte 2
I

ACCUMULATOR

INC

A

4C

I

INDEX REG.

INC

X

5C

I
I
I

DIRECT

INC
INC

M
,X

3C
7C

INC

Disp,X

6C

6;~~"

v

DXi"

HW"'A.W .1 BYTE

OFFSET

I

I
I
0

M

I
I
I
I

D

Byte 3

Number
of
bytes
1

Number
of CPU
cycles
1

1

1

2

1

4
3

2

5

I
I
I

I
I
I

I

Example

II

LOOP3

INC
CMP
BHI
LDX
STX
INC
BRA

A
#100
EXIT
O,X
$300.X
X
LOOP3

~HITACHI
330

*
CHECK COUNTER (100 TIMES)
MOVE

*

Conditional Branch
JMP
JMP (JuMP)

II

Format

Condition Codes

II

JMP P

I

+

Unaffected.

II

Operation

PC

IJ

EA

Description

I

A jump occurs to the instruction stored at the effective address. The
effective address is obtained according to the rules for EXTended,
DIRect or INDexed addressing.

Addressing Mode and Number of CPU Cycles
Addressing
Mode
DIRECT
EXTENDED
INDEXED u BYTE
OFFSET
INDEXED 1 BYTE
OFFSET
INDEXED 2 BYTE
. OFFSET

Mnemonic

Operand
type

Instruction code
I

Byte 1 : Byte 2

JMP
JMP

M
M

BC
CC

JMP

,X

FC

JMP
JMP

Disp X
Disp,X

EC
DC

,
I

,,
,
,,
,

I

,,
I
I

Example

II

LOA
STA
LOA
STA
JMP

VALl
EXVAL5
VAL2
EXVAL6
EN090

M
ML

MIl

,

,,
,,

I

Byte 3

D
DR

DL

Number
of
bytes

Number
of CPU
cycles

2

2

3

3

1

1

2

3

3

4

:,
,
,
I

I

DO TO END-ROUTINE

~HITACHI
331

Subroutine Control
JSR
JSR (Jump to SubRoutine)

II

Format

II

JSR P

I

-<-<-<-<-

II

Unaffected.

II

Operation
PC
Msp
Msp
PC

Condition Codes

(PC)+n Note )
(PCL), SP-<- (SP)-OOOl
(PCR) , SP -<- (SP)-OOQl
EA

Description

11

Note)
depending on the addressing
The program counter is increased by n
mode, then pushed onto the 2-byte stack. And the stack point is updated.
A jump occurs to the instruction stored at the effective address.
The effective address is obtained according to the rules for EXTended,
DIRect or INDexed addressing.
Note)

n is equal to 1, 2 or 3, depending on the number of bytes in the
instruction code. Refer to the addressing code and the number of
MPU cycles shown below.
Addressing Mode and Number of CPU Cy.:les

Addressing
Mode

Mnemonic

DIRECT

JSR

EXTENDED

M

JSR
JSR

Byte 1 : Byte 2

CD

,X
Disp,X
Disp,X

JSR

Instruction code

BD

M

JSR

INDEXED u BYTE
OFFSET
,ND""",,,u 1 BYTE
OFFSET
INDEXED 2 BYTE
OFFSET

Operand
type

FD
ED
DD

·,
·,
·,,,
I

,

I

,,
,
,
,,

M
MH

I
I

Byte 3

I
I

•I

,
I

D
DR

ML

DL

I

·

I

Example

II

*

START

EQU
JSR
JSR
JSR
JSR
JMP

I
I

** MAIN ROUTINE **
*

INTRTN
KBRTN
ANARTN
PRCRTN
ENDRTN

INITIALIZE
INPUT FROM KEY-BOARD
ANALYSE
PROCESS
END

~HITACHI
332

,

Number
of
bytes

Number
of CPU
cycles

2

4

3

5

1

3

2

4

3

5

Load

&

Store

LDA
LDA (LoaD Accumulator)
Format

'~::
I

1/

LDA P

:======:::;--;::==========~
Operation

II

Z:

ACCA .... (M)

I

Description

N:

C:

Condition Codes

II

Unaffected.
Unaffected.
Set if the most significant bit
of the result is "1"; otherwise
cleared.
Set if the result is "0"; otherwise cleared.
Unaffected.

I

Loads the M contents into the accumulator.

~HITACHI
333

Load & Store
LDX
LDX (LoaD indeX register)
Format

II

II !,

LDX P

II

Operation

Z:

C:

Condition Codes

II

Unaffected.
Unaffected.
Set if the most significant bit
of IX is "1"; otherwise cleared.
Set if all bits of IX of the
result are "0"; otherwise cleared.
Unaffected.

IX ... (M)

I

Description

I
The condition code is set according

Loads the M contents into IX.
to data.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

I
I
I
I

Operand
type

I

IMMEDIATE
DIRECT
EXTENDED
~NDEAED

LDX
LDX
LDX

u BYTE

OFFSET
INDEXED 1 BYTE
. OFFSET
INDEXED 2 BYTE
OFFSET

I
I
I

IIImm
M
M

Instruction code
Byte 1 :I Byte 2
AE

BE
CE

LDX

,X

FE

LDX

Disp X

EE

LDX

Disp X

DE

I
I

,
I
,I

II

LOX
STX
LOX
STX
LOX

I
I
I
I

VAll

WORK
O,X
RESULT
#$FF

~HITACHI
334

MH

ML

I

I
I

Example

M

I

I
I

I

Byte 3

, Imm

I

D
DR

DL

Number
of
bytes

Number
of CPU
cycles

2
2
3

3
4

2

1

2

2

4

3

5

Shift

&

Rotation

LSL
LSL (Logical Shift Left)

I

I Format II
LSL Q

H:
I:
N:

LSL A
LSL X

I

II

Operation

•

EJ+-I
b,

I

Condition Codes

Z:
C:

I I I I I I I I+-

Description

0

bo

U

Unaffected.
Unaffected.
Set if the most significant bit
of the result is Ill"; otherwise
cleared.
Set if the result is "0"; otherwise cleared.
Set if the most significant bit
of ACCA, IX or M is "1" before
the execution of an instruction;
otherwise cleared.

I

Shifts the contents of ACCA, IX or M 1-bit to the left. The bit 0 is
loaded with "0". The carry bit C is loaded with the most significant
bit of ACCA, IX or M.

I

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

Number
of
Byte 3 bytes

Instruction code

Operand
type

Byte 1

Byte 2

Number
of CPU
cycles

ACCUMULATOR

LSL

A

48

1

1

INDEX REG.
DIRECT

X
M
,X

58
38
78

M

1
2
1

1

OFFSET

LSL
LSL
LSL

OFFSET

LSL

DisD X

68

D

2

5

UlIUEXIIU U BYT!!

UIU!!XED ~ DYT!!

I

4
3

I
I
I
I

I
I

I
I
I
I

I

I

Example

II

LSL
LSL
LSL

WORK
WORK
WORK

** MULTIPLY

X 8 **

~HITACHI
335

Shift & Rotation
LSR
LSR (Logical Shift Right)

I

Format

I

1/

LSR Q
LSR A
LSR X

I

H:
I:
N:
Z:

II

Operation

Condition Codes

e:
------+

0

1 I I I I I I I I-{~]

Unaffected.
Unaffected.
Cleared.
Set if the result is "0"; otherwise cleared.
Set if, before execution of an
instruction, the least significant
bit of ACCA, IX or M is "1";
otherwise cleared.

b.

b7

I

II

Description

I

Shifts the contents of ACCA, IX or M I-bit to the right. The bit 7 is
loaded with "0". The carry bit C is loaded with the least significant
bit of ACCA, IX or M.

Addressing Mode and Number of CPU Cycles
Addressing
Mode

Mnemonic

ACCUMULATOR

LSR

INDEX REG.

LSR

DIRECT
lNlJ"lIl
incorrect operation
other interrupts
SliI interrupt
PCL ! PC+l
PCI.. ! PC
PCL J PC
PCH I (return Address) PCH I(return Address) PCH !(return Address)
Index Register
Index Register
Index Register
Accumulator
Accumulator
Accumulator
CCR
CCR
CCR
SliT
interrupt
routine
SliT
interrupt
routine
each interrupt routine
..
CCR:Cond~t~on Code Reg~ster

Figure 3 INTERRUPT

SEQUa~CE

~HITACHI
356

4.

Pin Arrangement and Package Information

•

HD63L05F1F(FP80)

~

XTAL

~

I,

:I

~

~

K
EXTAL •

'NC
C.

~

REI

~

c.

.,

~

~

sa

COM.

Ne

Ne

Vee:
XIN

COM.
COM.
&EG.

Ne
~

,~

)COUT

lEG.

NUM •
TIMER"

lEG.
Ne

YaH
Va

SEG.
SEG.

ee,

Ne

eet

lEG.
SEG.

.
Ne

~

VCM

•

.1

SEa.

HD63L05F1P (DP64S)

XIN

XOUT
0
NUM
TIMER.

VRH
VRL

S8

• REf
iN'f
Vss

CC.
CC,

EXTAL
XTAL

'

NC

E

NC

VCH

A,

A.

CHili

A,
A.
• A,

V./CH, '
SEG,,/CH,
SEG.. /CH,
V,/CH.
SEGIS/CHI

NC

A,

~~

•

~

SEG .. /CH ••
SEGn/CHI
SEG"
SEG ..'

g.

8,

~ 8.
~ 8,
~ 81

SEGIOI
SEG,
SEG.
SEG,
SEG.
SEG,
SEGI
SEG,
SEG,
SEG.

NC

Figure 4-1

I

Vee

8,
8,
• 8.
8.

e.
C,
c.
Co

COM,
COM,
COM.

Pin Assignment (Top View)

~HITACHI
357

Unit:
• FP-80
2.9maK.

(0.1I4m... )

(0.031 to.OO6)

--L

O.I~±O.O~

I
(0.0IUD.004)

\o.Q06±O.OOZ)

Al88IlIlIaUBWJIIII~rf-15"

~OOf>l±O.OIZ)

\.1±0 ..n .

• DP-64S
57.6(2.268)
58.6max.(2.307mlx.)

33

o
32

1.0
(0.039)

. ., d. ., I'

.&.~

19.05
(0.750)

~_~i!l:EO
U'========\
~l;t

I;

1.77B±0.25

~±0.010)

0.4B±0.10

II

(0.019±0.0~

.e'~

~~

JL
rf-IS"

0.25!t~llII)
\0.010'·.

N"";

e

Figure 4-2

358

$

Package Information

HITACHI

DDR

(inch)

5.

Electrical Characteristics

IIABSOLUTE MAXIMUM RATINGS
Item

VCC

Value
-O.3~ +5.5

Input Voltage

Vin

-0. 3·~ VCC+O. 3

Output Voltage

Vout

Supply Voltage

Symbol

Operating Temparature

Topr

-0 • 3 "" VCC+O • 3
-20-+75

Storage Temparature

Tstg

-55~+125

(NOTE)

Unit
V
V
V

!

°c
°c

Permanent LSI damage may occur if maximum ratings are exceeded.

I

~HITACHI
359

.DC CI{ARACTERISTICS (VCC=3.0±0.8V, VSS=OV, Ta=-20'V+75°C, typ means

typical value at VCC=3.0V unless otherwise noted.)
~ymbol

Item
XTAL, XIN
Input "High"
Level Voltage

Test Condition
Connect CL-0.5].lF
to VCH

O.5VCC+0.9
0.8VCC

e-°.

VC

Unit
V

VSS

NUM
(Test Mode)

VSS
0.5VCC
-0.2

-

O.5VCC
+0.2

V

30

].lA

VCC-0.2

(Normal Mode)
Connect CL=0.5].lF
to VCH

XTAL, XIN

Input PullUp Current

VCC

TIMER

VIH

NUM

Self Check
Input Voltage

max

-

-

RES, INT, SB
TIMER

Input "Low"
Level Voltage

typ
3

min

RES, INT, SB

NUM (Self Check

Mode)
RES (INT:Mask
Option)

VCC- 2 • l
VSS

VIL

VIM

VCC

V
V

VCC

V

VCC-l.a

V

0.2VCC

V

O.2VCC

V

0.2

V

Vr.r.

-I R1

VCC=3.0V, Vin=OV

3

15

IIINI

Vin = OV'VVCC

-

-

1.0

j.JA

f =400kHz
No load.

-

100

200

].lA

Tested after
setting up the
internal status
by self check.

-

40

80

].lA

2

5

].lA

-

200

600

].lA

R =100kHz
No load.

-

120

200

].lA

Tested after
setting up the
internal status
by self check.

-

60**

100**

].lA

2

5

].lA

-

220

600

].lA

-

0.3

V

NUM
Input Leackage TIMER, SB
Current
Dur~ng

*
r.rystal
Oscillation
Current

System
OperatioI1
At Halt

ICCl

At
Stand-By
At AID·
OperatioI1

Dissipation

*

RC
Oscillation

During
System
OperatioI1
At Halt

ICC2

At
Stand-By
At AID
Operatior:

Output "Low
Level Voltage

E

VOL

IOL = 30].lA

* By Mask option
** In the case that OSCI is stopped by Halt; 60].lA-30j.JA, 100].lA-60].lA

~HITACHI
360

.AC CHARACTERISTICS (VCC=3.0±0.8V, VSS=OV, Ta=-20'V+7S"C, typ means

typical value at VCC=3.0V unless otherwise noted.)
Item

Syabol

Operating Clock Frequency
Cycle 'Ilime

Test Condition

fc1
fcyc

Oscillation Frequency
(Resistor Option)

foSCR

External Clock Duty

a -100kSl

±1%

Duty

min

typ

lUX

unit

100

400

500

kHz

8

10

40

lis

300

400

500

kHz

45

50

55

%

Oscillation Start Time
(Crystal Option)

tOSCf

CD -10pF±20%, as -lk!'l max

-

-

150

ma

Oscillation Start Time
(Resistor Option)

toSCR

B.-lOOk!'l±l%,
Connect CL-0.5I1F to VCH

-

-

2

l1li

Oscillation Start Time (l2kHz)

tOSC2

CG-10pF±20%. as-20k!'l max

-

-

1

s

10

-

pF

10

-

pF

1

S

Internal Capacitance
of Oscillator

EXTAL

CD

XOUT
Delay Time of OBcillation
Delay Time
aeset Delay Time

RES Pulse Width

tDLY

Selected by maBk option

taLH

External Capacitance -2.2I1F

200

When OSC2 is used

48+1

tRW!.

When OSC2 is not used

tIW!.

TIMER Pulse Width

tTWL

1.5 tcyc+l

-

When OSC2 is not used

tcyc+l

-

In the case of counter

tcyc+l

-

When OSC2 is used

TIff Pulse Width

0

32

-

IDS

liB
118

liS

-

liS

-

liS

.PORT CHARACTERISTICS (VCC=3.0±0.8V t VSS=OV, Ta=-20'V+7SoC, typ means
typical value at VCC=3 OV unless otherwise noted.)
Svmbo

Item
Output "High" Level Voltage

Port A B,C

VOH

Port A,B,C
Output ''Low'' Level VoltaRe
Input "High" Level Voltage

PortABC

Vm

Port A,B,C

Input ''Low'' Level Voltage

Port A,BtC

VIH
VIL

Input Leackage Current

Port AtBtC

Input Pull-Up Current

Port AtB,C

IIINI
-1&2

Test Condition
CMOS Output Inu--l 00 \lA

min
V,.,.-o.l

Key Load CMOS Output
Inll--l0uA
1m -10ClJA

VCC-O.l

0.8VCC
VSS

Vin-OV - VCC
Vrr-l.OV, Vin-OV

4

tVD

-

max

-

O.l

Unit
V
V
V
V
V

-

VCC
0.2VC£:
1.0

I1A

20

40

uA

-

~HITACHI
361

"LCD DRIVER OUTPUT

CHARACTERISTICS(VCC-3.0V,VSs=OV,Ta.-2~

Item

Symbol
~OHI

Output "High" Level Voltage

Output "Low" Level Voltage

Output "High" Level Voltage

Output "Low" Level Voltage

Segment

Segment

Counnon

Common

Dividing Resistor

VOH2
VOH3
VOL 1
VOL2
VOL3
VOHI
VOH 2
VOH3
VOL I
VOL 2
VOL3
RLCD

Output "High" Level Voltage

Segment

VOH

Output "Low" Level Voltage

Segment

VOL

$
362

+75°C, unless otherwise noted.)

Test Condition
VI· I.OOV, V2- 2.00V
IOH- -llJA

min
2.8

typ max Unit
V

1.8

-

0.8

-

VI- I.OOV, V2- 2.00S
IOL- IlJA

-

VI - I.OOV, V2- 2.00V
IOH- -5lJA

2.8
1.8
0.8

VI - I.OOV, V2- 2.00V
IOL= 5lJA

-

-

-

-

Tested between VI and V2 45
90
In the case of Output
kTCC -0.3
Port, IOH=-30lJA
In the case of Output
Port, IOL=30lJA

HITACHI

-

-

-

V
V
V
V
V
V
V
V

2.2
1.2
0.2
180

V
V
V
!ill

2.2
1.2
0.2

- -

V

-

V

0.3

__~~______________~_VOHl

~

______-+______-+____~VOH2

____________-+__-r____~VOH3

Figure 5-1

Output Level of SEG and COM

Common Output
COM

V2

Segment Output
SEG
VSS~-------r----~

Figure 5-2

Power Supply Circuit for LCD Display

~HITACHI
363

• AID CONVERTER

CHARACTERISTICS*(VCC=3.0V,VSs.OV,Ta=-20·C~

+75°C,C=300pF,

unless otherwise noted.)
Item

Symbol

Conversion Accuracy

Absolute Accuracy
"High" Side
Reference Voltage

Input Voltage
Range

VHH - VRL
Input Range

8

bit

+2

LSB

Vce

V

-

V

VHH
Vec- 1•O

V

1.8

VTN

VHT
0.2
40

80

160

\OJ

-

4
+4

ms
LSB

60

liS

tCNV
Judge Error

-2

-

2

VRL-0.2V-----Analog Input Voltage - - -......~
(Ladder resistor indicates the compared
voltage. )
Figure 5-4

I

Example of 3 bit Resolution

~HITACHI
365

6.

Application

6.1

How to Confirm Operation Frequency
When pin E of the HD63L05 MCU is connected to VCC through the
resistor. the system clock ( E ) divided by OSCI is transmitted.
The clock output from the OSC2 is available as outputs of the COMI.
COM2. or COM3.

6.2

Method of the DAA (Decimal Adjust Accumulator)
(1)

Function
This subroutine is a simulation of the DAA instruction performed
by the HD63L05 MCU.

This is used immediately after the addition

of two bytes (ADD and ADC) which consist of two-digit BCD (Binary
Coded Decimal). respectively. This subroutine converts the result
of the BCD addition into two-digit BCD to transmit it from the
accumulator.
(2)

Linkage
The digit to be converted is input to the accumulator and operation jumps to the routine.
(Example)
LDA

ARGI

ADD

ARG2

JSR

DAA---Jumps to the DAA subroutine

STA

ARG3

Two-digit BCDs are stored in the ARGI and ARG2 respectively and
the operation jumps to the DAA after addition.

The result of the

addition is converted into BCD and is stored in the ARG3.
(3)

Result
The binary coded decimal digit is output to the accumulator.

(4)

Register to be influenced
(i)

IX guarantees the contents before jumping to the routine.

(ii)

Of the CCR (Condition Code Register). the C bit is set
when the result of the BCD addition or decimal conversion
is rounded up.

The previous contents in each bit of H. N

and Z cannot be guaranteed.

~HITACHI
366

(5)

Program specification
Program specification is shown in Table 6-1.
Table 6-1

Program Specification

Number of words(B) Work area(B) Execution time(usec) Reentra.nt
31
Intermediate interrupt
Possible

2*

Not
possib1e**

410

Relocation
Possible

Indicator

--

*: It is necessary to provide this work area within the stored RAM
($020 $07F).
**: Depending on the situation, it may be necessary to mask the interrupt during the execution of this subroutine.

I

~HITACHI
367

Figure 6-1

DAA Subroutine Flowchart

~HITACHI
368

Table 6-2

ADDRESS

OP CODE

0044
0045
0099
009B

B7
BF

009D
009E
OOAO
00A2
00A4

5F
25
Al
23

00A6
00A8
OOAA
OOAC
OOAE
OOAF
OOBl
00B2
00B3
00B5
00B7

DAA Subroutine Program List

AE

29
A4

Al
23
9F
AB

44*
45*
04
99
02
60
06
OF
09
04

COMMENT
ATEMP
XTEMP

RMB
RMB

1

DAA

STA
STX

ATEMP*
XTEMP*

Saves the input value

CLR
BCS
CMP
BLS
LDX

X
DAAH6

Vacates the IX to store the
converted value.
Branches if the value is equal
to or less than $99, otherwise
the higher 4 bits are also converted.

DAAH6
DAALOW

DAAL6
06

97
9F
BB
BE
81

DAADNE
44*
45*

BHCS
AND
CMP
BLS
TXA
ADD
TAX
TXA
ADD
LDX
RTS

1

11$99

DAALOW
11$60

Work area

DAAL6
II$OF
11$09

DAADNE
11$06

It is not necessary to convert
if the lower 4 bits are less than
$09.Therefore,branching is performed.
The converted value of the lower
4 bits.

ATEMP*
XTEMP*

Stores the converted value to A,
adds it to the original(ATEMP)
and prduces an output.

* It is necessary to provide ATEMP and XTEMP within the stored RAM
(Address $020 N $07F) in the work area.

~HITACHI
369

6.3

Cautions on the Programming the Write Only Register and Control Register
It is impossible to change the Write Only Register Contents (for
example, the Data Direction Register (DDR)of the I/O port) of the
HD63L05 MCU by applying the Read/Modify/Write instructions.
(1)

The Write Only Register (for example the DDR of the I/O port)
cannot read, the Read/Modify/Write instructions are executed in
the following sequence.
(i)
(ii)
(iii)

Reading the contents of the specified address
Changing the read-out data
Returning the changed data to the original address

Note that the Read/Modify/Write instructions cannot be
applied to the Write Only Register such as the DDR.
(2)

For the same reason, do not set the DDR of the I/O port or LCD
register by using the BSET and BCLR instructions of the HD63L05
MCU.

(3)

It is necessary to pay attention to the System Control Register,
the Timer Control Register, and the A/D Control Register when
BSET, BCLR, or Read/Modify/Write instructions are applied to them.
If one's own interruption request occured onto the interruption
request bit (bit 7) of the Control Register between read cycle and
write cycle of these instructions, the bit 7 may be cleared in the
write cycle and not acknowledged by

(4)

cpu.

Store instructions, such as STA or STX, are used to write
correctly in the Write Only Register or to avoid missing an
interruption of the Control Register.

6.4

Cautions on Executing BSR (Branch SubRoutine) Instruction
Sometimes the HD63L05 MCU does not execute the address munipu1ation normally with the second BSR instruction, if there exists the
BSR instruction in the address where branch has occurred.

For this

reason, do not execute the BSR instruction in the branched address.

~HITACHI
370

The following methods are available for substituting for the
second BSR instruction.
(1)

Insert the No OPeration (NOP) instruction before the second BSR
instruction in order to cause a branch in the address in which
the NOP instruction has been inserted.

(2)

Convert the BCR instruction in the branched address into Jump
SubRoutine (JSR) instruction.
B~R

LBL1

B~R

LBU-->1

--J

LBU
LBL3

______ J

An example of a
program which will
not execute branch
normally.

6.5

BSR

LBL1J
LBL1

NOP

LBL1

JSR

B~R

LBU -----

LBL2 -----

An example of a
program in which NOP
instruction is
inserted.

An example of a
program using JSR
instruction.

Cautions
(1)

To prevent the induced noise, the crystal oscillators should be
located as close to the LSI as physically possible.

Signal lines

should not run pararell with, or across the clock oscillator
inputs, such as XTAL, EXTAL, XIN, XOUT.

In particular, these

clock oscillator inputs should be separated as much as possible.
(2)

Functions and Cautions
A.

When STAND-BY goes "High", OSCl, system operation, and
peripheral circuits stop.

(OSC2 operates).

On power up, or

when reset, pull STAND-BY "Low".
B.

OSCl, system operation, and peripheral circuit restart
functioning by releasing them from. stand-by mode after the
delay time caused by the frequency divider.
If OSC2 is provided, clock is provided from OSCI with the
system after the delay time selected by $FFI.
If OSC2 is not provided, delay time means the period in which

~HITACHI
371

OSCI restarts functioning, after released from stand-by and the
period in which judging output of frequency divider, changes by
clock pulse transmitted to the delay circuit after restarting
the functions.
Note that the restart time of the system operation cannot be
prescribed precisely when using crystal oscillation, as
crystal oscillation affects both the restart time of the
oscillation and harmonic oscillation when restarting the
oscillation.
C.

In stand-by status, peripheral circuits (e.g. Time Base,
Timer, AID converter, and LCD driver) stop functioning.
When Time Base, Timer, AID converter go into stand-by mode
during functioning, Timer and Time Base stop functioning and
the result of AID conversion cannot be assurred.
Transmit the signal specifying if stand-by input is available
in order to control the stand-by signal.
stand-by signal to the port.

SB Input

SP
Port
Output

HD63L05
MCU

Figure 6-2

372

Example of SB Input Masking

~HITACHI

Then input the

7.

Evaluation Chip (HD63LOSEO)
The HD63LOSEO is a CMOS evaluation chip for the HD63LOS MCU.
Connecting an external EPROM (HN48Z73Z) to the chip, it can be operated
as a single chip microcomputer HD63LOS MCU.
100 pins flat package.

7.1

This chip is moulded in a

(Refer to Figure 7-1)

Block Diagram
The following describes input signals and output signals of the
HD63LOSEO MCU.

Basically, the same pin name means the same function as

the HD63LOS MCU.
•

VCC' VSS
Power is supplied to the LSI by using these pins.

Vce has a

voltage of 3.0V±0.8V and Vss is grounded .

•

00
This pin is used to interrupt the LSI processing externally.

•

XTAL, EXTAL
Input/Output Pins for the internal oscillator.

A crystal

(400 kHz typ.) is connected to these pins.

•

TIMER

An external input pin to count down the internal timer circuit.

•

RES

This pin resets the LSI.
•

STANDBY (SB)
This external input pin stops the LSI and holds data.

•

A/D Input Pins (CHl'VCH8)
This is an input pins for analog voltages needed for A/D conversion.
These may also be used as level check input under program control.

•

VRH, VRL
Reference voltages for A/D conversion are applied to these two
pins.

•

CCl, CCZ
These pins are not user application.

They should be left open.

~HITACHI
373

•

XIN, XOUT
A crystal (32.768kHz) is connected to these pins, for OSC2 oscillation.
When OSC2 is not used, connect XIN to VCC.

•

VCH
Decoupling pin from internal voltage

regulato~

Connect a capacitor

(O.5~F)

between VCH and VCC to stabilize the voltage.
•

•

MSET
This pin is not for user application.

ADCLK
This pin transmits a signal with 1/4 frequency of OSCI (100kHz typo
synchonized with system clock E).

•

Connect it to VCC.

NMOS open-drain output.

U/M

The HD63L05EO MCU can take two operation modes based on the state of
this pin.

When the pin is connected to VCC, the LSI operates as

a single chip microcomputer with external EPROM.

When the pin is

grounded, however, the HD63L05EO MCU operates in external extension
mode.
•

Input/Output Pins (AO'VA7' BO'VB7' CO'VC3)
These 20 pins consist of two 8-bit ports and one 4-bit port.
Each pin functions as an input or output under program control of
the Data Direction Register.

•

These are NMOS open-drain output.

DO'VD7
These pins are input pins for instruction or data from external
data bus.

For example, output from an external EPROM are applied

to these pins.
•

EO'VE7
These pins are NMOS open-drain outputs.

When the U/M is logical

"1", the internal address bus (AO'VA7) is transmitted.

When the

U/M is logical "0", the port E functions either as address bus or
as data bus.
bus.

When system clock E is "Low", port E functions as address

When system clock E is "High", port E functions as the peripheral

data bus.
•

FO'VF3
These pins are NMOS open-drain outputs.

When the U/M is logical

"1", the internal address bus (A8 'VAll) is transmitted.

~HITACHI
374

When

the U/M is logical "0", the port F transmits internal address bus
while system clock E is "Low".

•

CE/WR
This pin is a NMOS open-drain output.

When the U/M is "High",

CE signal (means address bus is in from $080 to $FFF) is transmitted.
•

When the U/M is "Low", Read/Write clock is transmitted.

LIR
NMOS open-drain output.

Fetch signal is available from this

pin.
•

HALT
NMOS open drain output.

When stand-by signal is acknowledged, the

output from this pin goes "Low" to control external clock source.

•

Vl, V2
These are pins for LCD driver.

When 1/3 bias - 1/3 duty drive,

connect Vl and V2 to VCC through condensor
•

Liquid Crystal Driver Pins
COM1~COM3

(COM1~COM3'

SEGll~SEG17

or as A/D inputs

SEGll~SEG17

(CH2~CH8)

function through selecting master-slice data.
multiplexed with A/D inputs

each).

I

SEG1~SEG17)

are for driving common electrodes, while

output pins for driving segments.
either

(O.l~F

SEG1~SEG17

are

functions as

by specifying the
SEGll~SEG17

are

(CH2~H8)'

~HITACHI
375

e

HD63L05EO

~ I~ ~
~!~««««m~.m====~
I;.

:; .... ;

NO

• NO

"'AL

" y.

NC

'INC

BXTAt

" F,
,. F.

NO
NO

....
.....
" ..

"NO
"NO

'..
SB

NO

"I:.E,

XIN

"NO

"'"

'I E,
X~

I~

TINBR

D.

~

"~
•• D.

iifiT

....

~

uNO

-~

"~

m

...

...

~

NO

~

"~

"~

u.

NO

810..

/Oil II

tl C,

NO

~

NC: No Connection

~H~

~; ~~~~i,-~~~~~~~~~~~

Figure 7-1 (a)

Pin Assignment (Top View)
Unit: mm(inch)

eFP-100

2.9malC.
(0.1 14m.. .)

~±O.I
0.006)

(0.012±0.004)

.
(0 00& ± 0.002)

~IHii'.H._"""'••yrt_15:
1.7±0.3
(0.061 ±0.oI2l

Figure 7-1 (b)

Package Information

~HITACHI
376

_f~5EO

COlllllOn
Driver
Out ut
He.~I---lIData
Latcb
S LCDl ':l

m~

I>-

LCD 2

ADCLlt

s

"'~

XIN

fi ••
imT

7

l
7

TIMER

LCD 8

..
,

s

...

III
III

, .....

......

Ao
AI
AI

U ..

~

~

t:

;::~

.. "
......

... 0

Ae
A.

!:I'"

~

:

"
0

u

....0

~

.......
-< g

X

Condition
sCode Reg'CCR
Stac
SPointer
SP
rogram
Counter
4 "Higb" PCH
Program
Counter
8 IlLow"
PCL

00

'"

.....

> "
" 0...
0·
u to

A

In ex
SRegister

~

i..

40

~!:I

Accumulator

....:
!:I
...
"
~

LCD?

U/M
nIT

0

~

LCD 3

XOUT

':l

COM,
COMI
COM.
SEG,
SEGz
SEG.
SEG4

!:I

L._

~

u

-<

-r--'--

........

CH,
(CHI)
(CHa)
(CH')
(CH,)
(CHe)
(CH.)
(CHa)

Bo

B,
Bz
B.
B.
B.

ALU

I

'--.. . . -r---B.
Be

Co

C,

Cz
Cs

Fo

'" Fa

Eo

'"

E.

Do

( ) Program Selection
Figure 7-"2

$

HD63L05EO Block Diagram

HITACHI
377

,...-----1 ADCLK (E: 100kHz)

ADB
PDB
CPU
PERIPHERAL
PERIPHERAL

CPU Read

PORT

PORT

CLK

DATA TO CPU

D

PORT E{

WR
RD EN

~~~X!§~~~~==x==:j MULTIPLEXED
ADD
(MONITOR

F{

& DATA
MODE)

_ _ _ _ _ _ _--1

ADB

(USER MODE)

L_r-iiLo;rrl

ADB

(MONITOR MODE)

_____

ADB

(USER MODE)

R/W

(MONITOR MODE)

~

MV,C,

~

CHIP ENABLE
(USER MODE)

Figure 7-3

HD63L05EO Timing Chart

~HITACHI
378

7.2

Memory Map
Figure 7-4 shows a memory map of the HD63L05EO Meu.
contained in the LSI.

$OOav$07F is

$OSav$FFF is not contained, thus it is necessary

to connect external EPROM (HN4S2732) to $OSav$FFF.

$F3av$FF3 is

not for user application, for Hitachi will replace these addresses
by the self check program.
$000

PORT A
PORT B

SOOI

I

I I I I
PORT C
NOT USED

S002
Soos

PORT A DDR·

SOH

PORT BOOR·
NOT USED

S005

1 PORT

C DDR·

NOT USED

S006
S 001

TIMER DATA REGISTER

S 008

TIMER CTRL REGISTER

S009
SOOA

NOT USED

SOOD

A/D DATA REGISTER

SOOE

A/D CTRL REGISTER

SOOF

$080
US ER PROGRAM

SOlO

NOT USED

SOlS

LCDI DATA REGISTER· 8

So l4.

LCD2 DATA REGI STER· 8

SOl5

LCDS DATA REGI STER· 1

$016

LCD+ DATA REGISTER· 1

SOl1

LCD5 DATA REGISTER· 1

SOl8

LCD6 DATA REGISTER· 1

SOl9

SF2F
SFSO

Reserved

LCD1 DATA REGI STER· 1

SOIA

I

SOIB

LCOS DATA· +
SYS CTRL REGISTER

NOT USED

NOT USED

SFEF

So IC

MASTER SLICE

(I)

SFFO

SOlD

MASTER SLICE

(2)

SFFI

/

SFF2
SFFs

$ 0 IF
RAM (96BYTE)

?20

-------------------STACK

/060
SOH
$ 080

EXTERNAL EP ROM

$FFF

• Write only register

~

Figure 7-4

TIME BASE VECTOR H

SFr.

TIME BASE VECTOR L

SFF5

A/D VECTOR H

SFF6

A/D VECTOR L

SFF1

TIMER VECTOR H

SFFS

TIMER VECTOR L

SFFy

INT VECTOR H

SFFA

INT VECTOR L

SFFB

SWI VECTOR H
SWI VECTOR L

SFFD

$FFC

RES VECTOR H

SFFE

RES VECTOR L

SFFF

Memory Map

~HITACHI
379

7.3

Pin Functions and Applications
(I)

Power
3V is supplied to VCC' then VDD is grounded.
to VCH through a condensor.

VCC is connected

(VCH :::+lV is transmitted) VI and

V2, which are connected to VCC through a condensor, are voltage
pins for LCD drive.
(2)

(VI :::+lV, V2 :::+2V are transmitted.)

Control Signals
Connect U/M and MSET to VCC'

(3)

Interfacing to the user system.
(a)

I/O port (AO'VA7' BO'VB7' CO'VC7)
Each pin has NMOS open-drain output.

Therefore, "High"

level of the output is obtained by connecting a resistor
to VCC'

When using as an input port, connect pull-up

resistor to VCC' if necessary.
(b)

Control pins (RES, INT, SB, TIMER)
Only RESET is connected to VCC through internal pull-up
PMOS in the LSI.

To avoid the floating input to 1Jf.f, S.B,

or TIMER, connect pull-up resistors between these terminals
and VCC, if necessary.
(c)

Others (SEGl'VSEG17, COMl'VCOM3, CHl'VCHa, CCl. CC2, VRH, VRL)
Bit correspondence between SEGI 'V SEG17 and LCD register is
fixed, which fixes the pin allocation and does not support
the port function as an output only port.
Note that the pin allocation of the HD63L05EO MCU is not
equivalent to that of the HD63L05 MCU.
The selection between SEG13 'V SEG17 (and master slice analog
input CH2 'VCH a ) can be specified by the external EPROM data.
VRH and VRL of the HD63L05EO MCU is equivalent to those of
the HD63L05 MCU.

$HITACHI
380

(4)

Interfacing to External EPROM
(a)

Data inputs (DO "'D7)
Connect the output pins from the EPROM to these pins.
Provide pull-down resistor to reduce input high level.

(b)

Address Outputs (EO "'E7, FO "'F3)
The address signals (AO "'All) is transmitted from these pins
to EPROM.

Connect them to VCC of the EPROM with pull-up

resistors.
(c)

Chip Select Output (CE)
Connect it to VCC of the EPROM with pull-up resistor.

When

ROM address is selected (from $080 to $FFF), "Low" level is
available.
(5)

Others (HALT, LIR, ADCLK)
Normally, these pins are not user application.

Keep them open.

~HITACHI
381

+3V

1 1 1

o.1 )JF O.1)JF

Vcc

O.5)JFT

VCR
VI
V2

OV

VSS
RD63L05EO

Figure 7-5

Connections for Power Supplying

~HITACHI
382

VCC

XTAL

---]1J--

VCH ---

I

XIN

32. 768kHz CJ
Crystal

xour
HD63L05EO
(b)

Figure 7-6

Connections for the Oscillators

~HITACHI
383

OUTPUT; R=20kfl
INPUT; R=150kfl

Vee
R

Vss
Figure 7-7

eonfigurati~~J NMOS open-drain Output

~HITACHI
384

+3V

+5V

-I

_ ov

I

~Rh

VCC

VCC

DO
Dl
D2
D3
D4
DS
D6
D7

00
01
02
03
04
05
06
07

EO
El
E2
E3
E4
ES
E6
E7
FO
Fl
F2
F3

AO
Al
A2
A3
A4
AS
A6
A7
AS

A9
AlO
All
R2

~

HN482732
(EPROM)

+SV .....

HD63LOSEO
(Evaluation Chip)

~ R2
CE

CE
r-

OE

VSS

GND

OV
Figure 7-8

OV

Interfacing between HD63LOSEO and EPROM
Rl, R2 = 20kO

~HITACHI
385

7.4

The Comparison between the HD63L05 MCU and the HD63L05EO
The HD63L05EO MCU is an evaluation chip for the HD63L05 MCU,
which supports the HD63L05 MCU function by connecting EPROM externally.
However, these two devices have some differences in the architectures.
Table 7-1 summarizes these.

Table 7-1

The Comparison between the HD63L05 MCU and the HD63L05EO MCU

ITEM

NO.

HD63L05EO
HD63L05
HD63L05EO

1

Operating
Voltage

2.2V"'3.SV

2

OSCI

XTAL/CR Mask option

3

OSC2

with OSCZ/without
mask option

4

REs

5

INT

6

TIMER

7

NUM

----.r-~
Timer input pin

supported.

XTAL

CR oscillation is
not supported.

Selectable
Master slice data is
set while reset-ilL"

Normal mode

User Mode

Equivarent to U/M

VSS

Test mode

Monitor Mode

Not supported

1/2VCC

Self check mode

STANDBY

9

MSET

Standby input

--

VRH/VRL

11

CCl/CC2

Not used

12

CHI "'CHS
Port input
type
!'ort output
type

A/D input pins
Pull-up R mask
option
CMOS
NMOS open drain
1/3 bias 1/3 duty,

15

LCD
pin

16

Pin location

17

Vb V2

IS

VCH

19

E

20

Port D

·
·

--

Present

10

13

Current cannot be

VCC

S

14

·
·
·
·
·

A/D Standard voltage

static,output pin,
master slice

Specified by mask
option

Liquid power sourcel
CH7,CHS'
LSI

·
·

·

Goes to "Low" li1hen

S.B.

--

Data input port
Address,data output
port

--

22

Port F

23

HALT

24

LIR

25

CE/WR

-----

26

PACKAGE

FP-SO/DP-64s

Not used

pin allocation of
CH7/CHR is different

Fixed pin location

Fixed pattern
Crystal source.

Reset/Halt/S.B.

Port E

Standby delay time
is se1ec table

NMOS Open drain
Only 1/3 bias 1/3
duty is supported

Goes to "Low" when

21

Not supported

Without pull-up R

Address output port
Goes to "Low"
when S.B.
Goes to "Low"

when Fetch cycle
-eE'="Low" in the

address $OSO"'$FFF
FP-lOO

~HITACHI
386

NOTE

Pin allocation of
CH7/CHS is different
Equivalent to
ADCLK

7.5

LCD Output
Note that LCD output of the HD63L05EO MCU is for 1/3 bias-1/3 duty
drive and its pin location block is fixed.

Table 7-2

Connections of the Pin location Block

LCD regi~ter
LCDI-O
I

z

S
4

5

6
?
LCD2-0
I
2
S
4

5

6
?
LCDS-O
I
2
S
45

6
LCD4--0
I

z

S

4

5
6
LCD5-0
I

z

S
4

5
6
LCD 6-0
I

z

3

45

6
LCD? -0
I
2
8
4

5
6
LCD8-0
I
2
3

Timing

SEGMENT Pin

COM.
COM.
COM I
COMI
COM I
COM.
COM.
Not used

SEG.
SEG.
SEG.
SEG.
SEGI
SEGI
SEGI
Not used

COM.
COM'
COM.
COMI
COM.
COM.
COM.
Not used

SEG.
SEG.
SEG.
SEG.
SEG.
SEG.
SEG.
Not used

COM.
COM.
COMI
COMI
COMI
COM.
COM.

SEGe
SEG.
SEG.
SEGe
SEGs
SEGo
SEG.

COM.
COM.
COMI
COMI
COMI
COM2
COM.

SEG.
SEG.
SEGlo
SEG.
SEGa
SEGa
SEGa

COM2
COM.
COM2
COMI
COM2
COM.
COM.

SEGII
SEGI2
SEGI2
SEGn
SEGlo
SEGlo
SEGn

COM.
COM.
COM I
COMI
COMI
COM.
COM.

SEGI.
SEGI.
SEGI4
SEGI3
SEGI2
SEGu
SEGI4

COM.
COM.
COMI
COMI
COMI
COM.
COM.

SEGlo
SEGlo
SEGI.
SEGle
SEGI.
SEGt5
SEGls

COM.
COM.
Not used
Not used

SEGI.
SEGI.
Not used
Not used

~HITACHI
387

7.6

Setting the mask-option data
The HD63LOSEO MCU contains two additional registers to specify the
master-slice data for
mask options.

SEGll~SEG17 (CH2~CHa)

and internal oscillator

During the RES input is "Low", address bus
E, Port F) become alternately $FFO and $FFI.

(AO~All:

from Port

Therefore, the output

data from the external EPROM (Address are $FFO and $FFl) can be written
into these registers through Port D.

3 cycles are necessary for

writing the master-slice data into the registers.
Table 7-3

iAddress Data
Master
Slice
Register
(1)

$FFO

Master
Slice
Register
(2)

$FFI

0

1
0

1

Master-slice select register in EPROM

7

6

S

Bit
4

3

2

1

0

*
*

CH2

CH3

CH4

CHS

CH6

CH7

CHa

SEG17 SEG16 SEGlS SEG14 SEG13 SEG12 SEGll

*
*

*

*

*

*

OSC2
Not
used
OSC2
Used

1/16 1/2
1 sec
sec
sec
Set I-bit within 4 bit to
"1". Set others to "0".

o sec

* : These bits are not used, write "0".
Note that only one bit of OSCI Delay Time select
bits can be set to logical "0".
System clock (ADCLK)

~In

selecting delay time,
it will delay the start.

Fig. 7-9

Start from Reset

~HITACHI
388

7.7

Electrical Characteristics

• ABSOLUTE MAXIMUM RATINGS
Item

Symbol

Value

Unit

Supply Voltage

VCC

-0.3

'V

+5.5

V

Input Voltage

Vin

-0.3

'V

VCC+O. 3

V

Output Voltage

Vout

-0.3

'V

VCC+0.3

V

Operating Temperature

Topr

-20

'V

+75

°c

Storage Temperature

Tstg

-55

'V

+125

°c

(NOTE)

Permanent LSI damage may occur if maximum ratings are
exceeded. Normal operation should be under recommended
operating conditions. If these conditions are exceeded,
it could affect reliability of LSI.

I

~HITACHI
389

•

DC CHARACTERISTICS

(VCC=3.0±0.8V, VSs=OV,Ta=-20 "-+75°C, typ means
typical value at VCC=3.0V unless otherwise noted.)

Item

Input
"High"
Level
Voltage

Symbol

XTAL, XIN

Test
Condition

min

typ

max

Unit

Connect
CL=0.511F
to VCH

VC C-0.3

-

VCC

V

O.5VCC+0.9

-

VCC

V

RES, INT, SB
TIMER

VIH

Input

Connect
CL=0.511F
to VCH

XTAL, XIN

"Low"

Level
Voltage

RES, INT, SB
TIMER

VIL

U/M
(Monitor Mode)

V

VCC

V

VCC-2.l

-

VCC-1.8

V

Vss

0.2VCC
0.2VCC

V

Vss

-

Vss

-

0.2

V

V

Input PullRES
Up Current

-I RI

VCC=3V,
Vin=OV

3

15

30

llA

Input
Leakage
Current

IIINI

Vin=OV "VCC

-

-

1.0

llA

f=400kHz,
No load.
Tested
after setting up
the internal status

-

100

200

llA

-

40

80

llA

-

2

5

llA

-

200

600

llA

TIMER, SB
During
System
Operation

Current
Crystal At Halt
Diss ipat ion (400kHz)
At
Standby
At AID
Operation

ICC

~HITACHI
390

-

VCC

VCC-O .2

0.8VCC

U/M (User Mode)

• AC CHARACTERISTICS (VCC=3.0±0.SV, VSS=OV, Ta=-2OV+75°C, typ means
typical value at VCC=3.0V unless otherwise noted.)
Item

Symbol

Test Condition

min

typ max Unit

100

400 500

Operating Clock Frequency
Cycle Time

fcl
tcyc

8

10

40

llS

External Clock Duty

Duty

45

50

55

%
ms

kHz

Oscillation Start Time (OSCI)

tOSCf

CD=10pF+20%,
RS=lkn

-

-

150

Oscillation Start Time (OSC2)

tOSC2

CD=10pF+20%,
RS=20kn

-

-

1

-

10

-

pF

10

-

pF

Internal Capacitance
of the Oscillator

I OSCI
I OSC2

EXTAL
CD

XOUT

s

Delay Time of Oscillation
(Program)

t DLy

0

-

Reset Delay Time

tRLH

200

-

-

ms

tRWL

48

-

-

lls

tIWL
tTWL

32

- -

lls

m

Pulse Width

!NT Pulse Width
TIMER Pulse Width

tcyc+l

-

1

s

llS

I

~HITACHI
391

• PORT CHARACTERISTICS

(VCC=3.0±O.8V, VSS=OV, Ta=-2OV+75°C, typ means
typical value at VCC=3.0V unless otherwise noted.)
Test Condition

Symbol

Item
Output "Low" Level Voltage

Port A,B,C
Port A,B,C

Input "Low" Level Voltage

Port A,B,C

V1L

Input Leackage Current

Port A,B,C

IIINI

Vin=O "-VCC

VOL

IOL=200IlA

Input

"High" Level Voltage

Output "Low" Level Voltage

ADCLK.«.L!I(
'iiAL'T",Port E,F

Input "High" Level Voltage

Port D

Input ltLowlf Level Voltage

Port D

.-

min

-

IOL=lOOIlA

Vnt .
VIH

o.BVee
V••

-

-

V,H

O.BVee

V,L

Vas

max

Unit

0.3

V

Vee
O. 2Vee

V

tva

-

1

-

V

IlA

0.3

V

Vec

V

O. 2Vee

V

• LCD DRIVER OUTPUT CHARACTERISTICS (VCC=3.0V, VSS=OV, Ta=2OV+75°C, unless
otherwise noted.)
Item
Output "High" Level Voltage

Output "Low" Level Voltage

Svmbol
vOHl
Segment

Segment

~-VOH3
VOL 1
VOL2
VOL3

Test Condition
Vl-

vl-

VOHI
Output "High" Level Voltage

Output "Lew" Level Voltage
Dividin~

Common

Connnon

Resistor

Output "High" Level Voltage
Output "Low" Level Voltage

Segment
Segment

VOH2
VOH3
VOLI
VOL2
VOL3
RLCD

1.00V,
IOH-

vl -

I.OOV',

v2 -

v2IOL= 51lA

1.8
0.8

2.00V

-51lA

1.00V,

2.00V

2.8
1.'3
0.8

-

tvo

-

-

-

VOH

Tested between VI and V2 45
90
In the case of Output
CC-0.3
Port, IOH-- 3OIlA

VOL

In the case of Output
Port, IOL= 30llA

~HITACHI
392

2.00V

1.00V, vz- 2.00V
IOL- lilA

10Hvl-

v2 -

-lilA

min
2.8

-

max

-

Unit
V
V
V

2.2
1.2

V

0.2

V

-

V
V

2.2
1.2
0.2
180

V

V
V
V
V
kS"l

- -

V

-

V

0.3

"';;';=~

______-L.._ VOHI

--------~------~--~-------------~--~--~--

VOH2

VOR3

Figure 7-10 Output Level of SEG and COM

VCC
COlllllon Output
V2

I

COM

VI

SEG

Segment Output

VSS

Figure 7-11 Power Supply Circuit for

~CD

Display

~HITACHI
393
----------

• AID CONVERTER CHARACTERISTICS *(VCC-3.0V, VSS-OV, Ta--20·C '\.+7S·C

unless otherwise noted.)
Symbol

Item
Conversion Accuracy

Ladder Resistor

bit

+2

LSB

Vce

V

-

V

Vec-I.O

V.

160

kQ

VR1.

VS~

LlVRRF

1.8

VTN

VRL
0.2
40

80

2

-

-

VRT.=O. 2V < Vin.::I

o

4 ----------------3
2

1

o

o

1/8 2/8

3/8

4/8 5/8 6/8

7/8

8/8

Analog Input Voltage
(Ladder resistor indicates the compared
voltage.)
Figure 7-13

I

Example of 3 bit Resolution

~HITACHI
395

8.

ROM Code Order Method

User's programs are mask programmed into ROM by Hitachi to be
shipped as LSI. Users are requested to hand in three EPROMs in which
the same contents are written,order specifications,mask option list,
• and list of the ROM contents.
Relationship between the address of the mask ROM and that of the EPROM
is shown in Table 8-~ Write $FF for the unused address data of the EPROM.
Table 8-1 Relationship between the Address
of Mask ROM and that of EPROM
Type name

Address of
Mask ROM
$080

Address of
EPROM
A

C'

)

$F2F
HD63L05Fl

$F30

A

"

$FF4

)
"

C'

$FFF

C'

User programs are
written in 'this area.

$F2F

C'

$FF3

$080

Remarks

"

$F30
C'

$FF3
$FF4
C'

This area is used for
the Self Check program
by Hitachi.
User supplied vectors are
written into this area.

$FFF

EPROM is a HN482732 or equivalent product.

~HITACHI
396

I APPENDIX
I.

Design Procedure and Supporting Tool

Cross assembler and Hardware emulator, containing various kinds of
computers, are available as supporting systems to develop users'
programs. Hitachi will mask program users' programs into ROM to ship them
as LSI.
Figure 1-1 shows a typical program design procedure.

Table 1-1

summarizes a set of system development supporting tool for the HD63L05
MCU.

~

(i)
Text Editor
Host Computer

®

@

@

@

®

Cross Assembler
Evaluation Kit
Host Computer

I

Emulator
Evaluation Kit

The following explains the system development procedure.

1.

Specify functional assignment of I/O pins, and allocation of RAM
area before starting programming.

2.

Design flowchart to implement the functions -and encode this flowchart with mnenic codes.

3.

Write the coded format on cards or a floppy disk.
coded form is a source program.

4.

Assemble the source· program to form an object program with an
assembler on either a resident system(evaluation kit) or cross
system. Then check errors out.

5.

Verify the program through hardware simulation by an aid of
evaluation kit

6.

Send the completed program in EPROM to Hitachi.

7.

After Hitachi received users' specified ROM pattern and options,
Hitachi will pilot product sample LSI for users I evaluation for
the functions. If a user finds no problem in the sample LSI,
Hitachi will start mass production of the LSI.

Figure 1-1

This set of

Program Design Procedure

~HITACHI
397

Table I-l System Development Support lbol
Type No.
HD63105Fl

Evaluation Kit

IBM PC
Cross Assembler

H315EVTl

S35IBMPC

~HITACHI
398

Single Chip Microcomputer ROM Ordering Procedure
(1) Development Flowchart
Single chip microcomputer device is developed according to
the following flowchart after program development.

(!) ROM code * 1

@ Mask Option List *2
@Ordering Specifications *3
Comput.ar processing

*1 2 sets of EPROM
*2 Part specific
*3 Generic for Hitachi
microcomputers

I

y

*4 The same ROM code as

ROM code for confirmation of ROM fabricating
specifications *4
OK

submitted

*5 Send it back after
approving
I~ Verification Listing
*5

I

t
I

Mask

Remarks

Customer

Hitachi

*6 3 pcs
*7 Start the following
flowchart after approving

Sample

*8 Send back signed working
sample approval form

I

*9 10 pcs

I

Working Sample (WS)
*6

I

•

I

® Confirmation

of function, characteristics
*7, *8

+
Engineering
*9

OK
Sample (ES)

I
I
Confirmation of function, characteristics,
quality

Commercial Sample (CS) I
(E!n)
(Note)

Please send in(!), ~, and (j)at ROM ordering, and send back ~,

®

after approving.

Device Development Flowchart

~HITACHI
399

(2)

Data you send and precautions
(a) Ordering specifications ----- Common style for all Hitachi
single chip microcomputer
devices. Please enter as
for the followings. The
format is shown in the next
page.

o

Basic ITEM
Environment Check List
Check List of attached data
Customer

(b) ROM code ----- Please send in the ordering ROM code by 2
sets of EPROM the same contents are written.
Enter ROM code No. in them. It is desirable to send in program list for easy
confirmation of the program contents.
(3) Change of ROM code
Note that if you change the ROM code once sended in or other
specification, the ROM must be developed from the beginning.
The cost of mask charge should be provided again in this case.
(4)

Samples and Mass production
(Working Sample) ----------- Sample for confirmation of the
contents of ROM code and that
of mask option. Normally 3 samples
are sent, but not guaranteed as for
reliability. Please evaluate and
approve immediately because the
following sample making and mass
production are set about after
obtaining your evaluation.

(Engineering Sample) ------- Sample for evaluating also reliability. 10 pcs are included
in mask charge.
(Commercial Sample) -------- Samples for pre-production which
maybe purchased separately.
(Mass Product) ------------- Products for actual mass production. Please enter the plan of
mass production in full.

~HITACHI
400

HD63L05F1
ORDERING SPECIFICATIONS
(1) GENERAL CHARACTERISTICS (Fill in blank space or appropriate boxD ).
Device
Type

Package Outline
(See Section)
3,4.1

Application
(be specific)

D

DP-40

D

FP-54

D

CP-44

Options!Remarks:

Customer
ROMCodeID
ROM Code
Media

D
D

EPROM
ZTAT™

Operating
Temperature

D

Standard

Remask

DYes DNo

M

S 'f Customer Programmed Start Address
ust pecl y:
Customer Programmed Stop Address

D

J Specification (-40"c to +8S"C), if offered

Previous Hitachi PIN

(2) OPERATING CHARACTERISTICS

LSI
Ambient
Temperature
LSI
Ambient
Humidity

·C

Average
Range

D

'C-

'c

Target Level
Of Reliability

%-

% Acceptable
% Quality Level

D
D

Average
Range

Power On
Duration

Average

Hours!Day

Maximum Applied
Voltage To LSI

Power
Supply
I/O

Max

V

Max

V

D

500 Fit
1000 Fit

D(

1.0%

D

0.65%

D(

)

0.4%
)

Remarks:

(3) ELECTRICAL CHARACTERISTICS

D

Purchasing Specifications

(4) CUSTOMER APPRO VAL
Customer Name
PO#
Accepted By (print)
Accepted By (signature)
Date

D Hitachi's Standard Specifications
Refer To Data Sheet:
( For Hitachi Use Only)
(5) ROM CODE VERIFICATION
LSI Type No.
Shipping Date of
ROM To Customer
Approved Date of
ROM From Customer

~HITACHI
401

I

HD63L05F
MASK OPTION LIST

Date of Order
Customer
Dept.
Accepted by
ROM Code ID.
LSI Type No. HD63L05F

* Select one type for each item
and check.
(1)

OSC Option
Select one type of OSCI option.

Type of
OSCI

Use of
OSC2

Condition

*1
XTAL

OSC.
CR
OSC.
*1 Crystal option of OSCI is not allowed to stop at halt.
*2 If OSC2 is not used, the delay time is not accurate.
*3 All CR option of OSCI allowed to use of stand-by mode.
(2)

I/O Option
Specify an I/O option for each terminal.

Port Mask Option
A B C D
AO
Al
A2
A3
A4
AS
A6
A7
BO
B1
B2
B3
B4
BS
B6
137
Co
C1
C2
C3
(3) LCD Driver

*4

Specify K-type if L-type is selected at LCD driver.

A:
B:
C:
D:
E:
F:
G:
H:
K:

Output without input pull-up PMOS.
Output with input pull-up PMOS.
Output for key scanning.Open drain output. (Max. VCC)
Input without pull-up PMOS.
Input with pull-up PMOS. '
A/D input.
Segment output.
Terminals for LCD display.

Specify a type of LCD driver.
Mask Option
SIP
Segment

I

I

L:
S:
P:

1/3 bias-I/3 duty LCD.
Static LCD.
Output Port.

••• Mask options indicated as _

are not available •••.

~HITACHI
402

LCD Pin Location

Segment Output Terminal
LCD
Timing
B
Regis- I COM COM COM SEG SEG SEG SEt; SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG U 0
•
2
ter
T
1
2
3
1
7
3 4
5 6
S 9 10 11 12 13 14 15 16 17 18 19
LCDl 0
1

LCD2

LCD3

LCD4

2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
0
1
2
3
4
5

LCD5

LCD6

6
0
1
2
3
4
5
6
0
1

I

2

3
4
5
6
LCD 7 0
1
2
3

LCDS

4
5
6
0
1
2

3

4>WRITE
1/4-oSCl

0
0

* Specify the
* When static
*

*

combination of timing and segment output terminal for each bit of LCD1 to LCD8.
or output port is selected. The timing is fixed at COM1. So specify COM1.
Don't specify the timing or segment output terminal for the terminal A/D input is selected at
(2) I/O option.
Specify the LCD pin-location even in such a case as unused segments are provided, and program
to put out those segments. The indication of segments cannot ,be defined as Hitachi will connect
unspecified segment to any registers to prevent circuit from malfunctioning.

~HITACHI
403

404

~HITACHI

HD630S/HD63LOS SERIES HANDBOOK

Section Six

Software
Application Notes

~HITACHI
405

406

~HITACHI

FOREWORD
The HD6305 is a family of 8-bit single chip CMOS microcomputers controlled
by microprogramming.

This family provides an easy to use instruction set

by adding instructions for decimal adjustment and a low power consumption
mode to those of the NMOS HD6805 FAMILY.
APPLICATION NOTES

summarize typical programs for the HD6305 FAMILY

to help users better understand the instruction set and to provide them
with references for making more customized programs.
Programs described in APPLICATION NOTES have already been debugged.
However, please be sure to check the operation in actual use.

~HITACHI
407

~HITACHI
408

Section 6
Software Application Notes
Table of Contents
Page

1.

HOW TO USE APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

413

Formats.....................................................

413

1.1

1.1.1

Specification Format (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

415

1.1.2 Description Format (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

421

1.1 .3

Flowchart Format (Format 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

424

1.1.4 Program Listing Format (Format 4). . . . . . . . . . . . . . . . . . . . . . . . ... . ..

426

1.2

How to Execute Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

428

1.3 Symbols.....................................................

430

PROGRAM APPLICATION EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

431

Program Application Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

433

MOVING DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

434

1.

Filling Constant Values (Fill) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

434

2.

Moving Memory Blocks (Move) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

439

3.

Moving Strings (Moves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

446

BRANCHING FROM TABLE (CCASE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

452

4.

Branching from Table (CCASE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

452

HANDLING ASCII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

459

5.

Converting ASCII Lowercase into Uppercase (TPR). . . . . . . . . . . . . . . . . . . ..

459

6.

Converting ASCII into 1-Byte Hexadecimal (Nibble). . . . . . . . . . . . . . . . . . . ..

464

7.

Converting 8-Bit Binary Data into ASCII (Co byte) . . . . . . . . . . . . . . . . . . . . . ..

469

BIT MANIPULATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

474

8.

Counting Number of Logical "1" Bits in 8-Bit Data (HCNT). . . . . . . . . . . . . ..

474

9.

Shifting 16-Bit Data (SHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

479

COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

484

10.

484

4-Digit BCD Counter (DECNT) ............... . . . . . . . . . . . . . . . . . . . ..

~HITACHI
409

COMPARISON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

489

11. Comparing 16-Bit Binary Data (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

489

ARITHMETIC OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

495

12. Adding 16-Bit Binary Data (ADD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

495

13. Subtracting 16-Bit Binary Data (SUB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

501

14.

Multiplying 16-Bit Binary Data (MUL) . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .

507

15.

Dividing 16-Bit Binary Data (DIV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

513

16. Adding 8-Digit BCD (ADDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

519

17.

Subtracting 8-Bit BCD (SUBD) . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

525

18.

16-Bit Square Root (SQRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

531

CONVERTING BCD INTO HEXADECIMALS .............................

537

19. Converting 2-Byte Hexadecimals into 5-Digit BCD (HEX) . . . . . . . . . . . . . ..

537

20.

Converting 5-Digit BCD into 2-Byte Hexadecimals (BCD) . . . . . . . . . . . . . ..

542

SORTING.........................................................

549

21 . Sorting (SORT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

549

~HITACHI
410

APPLICATION NOTES GUIDE

~HITACHI
411

~HITACHI
412

HD6305 FAMILY APPLICATION NOTES GUIDE>

<

1.

How to Use APPLICATION NOTES

1.1 Formats
APPLICATION NOTES consist of Formats 1 to 4, shown in Fig. 1.1.

Format 2 -DESCRIPTION

FUNCTION

Sample
Application

ARGUMENTS
CHANGES IN CPU
REGISTERS AND FLAGS
Format 1

1

RAM Description

Basic
Operation

SPECIFICATIONS
Format 3 -FLOWCHART

DESCRIPTION 1Function
Details'
User Notes

Format 4 - PROGRAM LISTING

SPECIFICATIONS NOTES

Forma t 4 - 1

1"'-1

1........ 1

...31» "/IlLY

PlIOClWlLlSTDIC

Format 3-1

1"'-1

.........

100,-r

Format 2 -~L

1D6:J01'MlU.Y

1III6:J05 'MIlLY

1""'1

1..... 1

DUCunlOil

Format 1 -

"'_I

1........ 1

IID6lO5FAIIILT

.lIKtllII

~

ClWICISlACftl
Imlll'l'lUMlDruu

Itorale

CoIIhIIU

.,u

Location Lith.

--eTIiIi •

(..,tood

. ; I1114eHMIII

r ......lt

.

~
,
,

-

...

~

~

~

. ,"
::;

IPICIFlCATICIIS

~
~

1;;;;;-

l..

lee.Cion

Itfttarl'\lft
~

~
f-

SPlClnCAnllllll lObI

Fig. 1.1 APPLICATION NOTES Formats

~HITACHI
413

Programs in APPLICATION NOTES can be implemented in two ways, i.e.
(1) without change or (2) partially changed.

Read the information that

applies to the type of implementation to be carried out.
(1)

Without change
(a)

All of Format 1

(b)

RAM Description and Sample Application in Format 2

(c)

PROGRAM LISTING in Format 4

(2) Partially changed (user originals)
All of Formats 1 to 4 after reading these formats, change the
FLOWCHART and PROGRAM LISTING according to user specification.

~HITACHI
414

1.1.1

SPECIFICATION Format (Format 1)
SPECIFICATION Format is represented in Fig. 1.2.

functions and specifications.

It gives program

Each item in the format is described

using Fig. 1. 2.

{\ )
(4 )

.
.

ITEM NUMBER AND PROGRAM NAME

I

FUNCTION

I

I

MCU/MPU

HD6305 FAMILY

ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS
•

LABEL

I

I)

)6)
(5 )

I

: No t offec ted

SPEC IFICATIONS
ROM (Bytes)

x : Undefined
Storage
Location

Contents

Byte
Lgth.

1 : Result

I
Entry

I
N

Returns

.

DESCRIPTION

IX

ACCA

Stack (Bytes)

I

~

Arguments

(8)

RAM (Bytes)

No. of eye les

Reentrant

I

Relocation

H

I

Interrupt

(1) Function Details

(2) User Notes

(9 )

•

SPECIFICATIONS NOTES

I

Fig. 1.2 SPECIFICATION Format

~HITACHI
415

(l)

ITEM NUMBER AND PROGRAM NAME:
Indicates item number and program name in APPLICATION NOTES.


Program name

{2}

K:u/MPU:

Indicates names of microcomputer and microprocessor family
applicable to a program.


HD6305

FAMILY

L
{3}

IQ)

Microcomputer and microprocessor family name
FAMILY

HD6305

LABEL:
Indicates the name identifying program entry point.
When using a program as it is, call the label "SHR".


\~8~

Entry point label: SHR

{4}

FUNCTION:
Explains program functions.


FUNCTION

I

(a) Shifts l6-bit binary data in RAM to right.
(b) Permits number of shifts to be freely determined.
(0) Permits easy ..,1tiplioation of l6-bit binary data by 2-n (n : number of

shifts).

~HITACHI
416

(5)

ARGUMENTS:
Explains entry arguments which must be set before execution of a
program, and return arguments after execution.
(a)

Contents:
Explains meanings of arguments.

(b)

Storage Location:
Indicates registers and RAMs in which arguments are to be
set.

(c)

The RAM is presented as a label followed by "(RAM)".

Byte Length:
Indicates byte length of the arguments.

ARGUMENTS

I
Storage

Contents

Location

16-bit
b-inary
data to
be
Entry shifted
to right
Argumenta

Number of

shifts
ReShift
turns results

(6)

Byte
Lgth.

SFT
(RAM)

2

IX

1

SFT
(RAM)

2

CHANGES IN CPU REGISTERS AND FLAGS:
Explains changes in CPU registers after executing a program
and flag changes of condition code register.

Meanings of ab-

breviations and symbols in the table are given as follows:
(a)

(b)

CPU register
ACCA:

Accumulator A

IX:

Index register

Flags of condition code register
C:

Carry/borrow flag (carry and borrow)

Z:

Zero flag (Indication in case of 0)

N:

Negative flag (Indication in case of negative)

I:

Interrupt flag (Interrupt mask)

H:

Half carry flag (Carry from bit 3 to bit 4)

~HITACHI
417

(c)

State of CPU registers and condition code register flags
.:

Not affected: Maintains previous values after executing
a program.

x :

Undefined

Does not maintain previous values after
executing a program.

Result

Be set with the result of executing a
program.


(Notes)

CHANGES IN CPU
REGISTERS AND FLAGS

•

In the example, after executing a program,

: Not affected

x : Undefined

contents of index register (IX), condition

I : Result

code register (CCR), bit C, bit N and bit Z
ACCA

•
C

N

(7)

IX

will be destroyed.

Thus, register contents

which will be destroyed should be saved

z

before executing a program.

•

SPECIFICATIONS:
Explains a program specification.
(a)

ROM

(Bytes):

Indicates ROM capacity used in a program.

(b)

RAM

(Bytes):

Indicates RAM capacity used in a program.

(c)

Stack (Bytes):

Indicates stack size used in a program.

The

RAM capacity in this table does not include
the stack size.

When the program is executed,

it is necessary to reserve the stack size in
RAM.
(d)

No. of cycles:

Indicates maximum number of execution cycles
when MCU executes a program.

Calculate the

execution time of the program as follows:
Execution time (sec) = Cycle number x cycle
time
Cycle time (sec)= 4/(External oscillator (Hz»

~HITACHI
418

(e)

Reentrant

Indicates whether a program has a structure which
can be called from two or more routines at the
same time.

(f)

Relocation

Indicates whether a program can be located in
any memory space.

(g)

Interrupt

Indicates whether MCU executes a program normally
after serving an interrupt routine during program
execution.

If impossible, inhibit interrupt

before the program is called.

SPECIFICATIONS
ROM (Bytes)

8
RAM (Bytes)
2

Stack (Bytes)

0

No. of cycles
110

Reentrant
No

Relocation
No

Interrupt
Yes

(8)

DESCRIPTION:
Explains detailed functions of a program and user notes.
(a)

Function Details : Gives an execution example and detailed
functions of a program.

(b)

User Notes

Explains notes and limitations when executing a program.

*

Be sure to read these items when using the
programs without change.

~HITACHI
419


DESCRIPTIOII
(1) Function Details

_ (a) Arg...nt d.etails
SPT

Holda l6-bit binary data to

(!WI)

be sbifted to rigbt.

After

SHR execution, containa sbift

result.
IX

Holds nuaber of l6-bit binary
data to be shifted to right.

Fig. 1 EXIIIP1e of SHR

execution

(b) Fig. 1 shows example of SHR execution.

If entry arg.....nts are held as shown

ift p,art@ of Fig. 1, l6-bit binary data is shifted to right as shown in part

@of Fig. 1.
(2) User Rotes
Be sure to hold data into IX within range of $01 S IX S ,OF.

When data outside this range is held, SFT (RAIl) becomes "0".

(9)

SPECIFICATIONS NOTES:
Explains notes on data process written in SPECIFICATIONS (7).

SPECIFICATIONS IlOTESJ
''Mo. of cycles" in "SPECIFICATIONS" represents the number of cycles needed to

shift 16-bit binary data to right by 7 bits.

$
420

HITACHI

1.1.2 DESCRIPTION Format (Format 2)
DESCRIPTION Format is represented in Fig. 1.3.

It gives remaining

Function Details, User Notes, RAM Description, Sample Application, and
Basic Operation.
Each item in the format is described using Fig. 1.3.
(1)-

ITEM NUMBER AND PROGRAM NAME

(4) -

DESCRIPTION

I

r

,-(2)
I£U/MPU

I

(3)

1ID6305 FAMILY

I

(3)

RAM Description

(4)

Sample Application

(5)

Basic Operation

Fig. 1.3 DESCRIPTION Format
(1)

ITEM NUMBER AND PROGRAM NAME }

(2)

MCU/MPU

(3)

LABEL

Same as SPECIFICATION
Format

~HITACHI
421

(4)

DESCRIPTION:
Gives RAM Description, Sample Application. and Basic Operation

(a)

RAM Description: Explains label and meaning of the RAM used in a
program.

1106305 FNlILY

SHR

(3) RAIl Description

(b)

Label

RAil

SFT

Upper byte

l6-bi t binary data to be shifted to right
is stored before execution.

Lower byte

Shift result is stored after execution.

Description

Sample Application: Gives a sample application in actual use.


(4) Saq>le Application
SHR subroutine is called after number of shifts and' l6-bit binary data to be
shifted to right are held.
WORKl

RMB

------Reserves memory byte for 16-bit binary data.

WORK2

RMB

WORK3

RMB

---- Reserves memory byte for number of shifts.
----- Reserves memory byte for l6-bit binary
shif t resul ts •

WORK 4

RMB

---- Reserves II8IIOry byte for register contents
saving.

STX

WORK4

- - Saves register contents that will be
destroyed by executing SHR.

LDA
STA
LDA
STA
LDX

WORKl
SFT
WORKl+l
SFT+l
WORK2

1

----- Loads number of shifts into entry argument
(Ix).

II&L.:.=_~s;:;;HR:;..aH
JSR
LDA
STA
LDA
STA
LDX

Stores l6-bit binary data to be shifted
into right in entry argument (SFT).

----- Calls SHR subroutine.

SFT
WORK3
SFT+l

)

WORK3+l
WORK4.

Stores shift results regarding l6-bit
----- binary (return argwaent (SFT» in RAIl.
----- Restores register.

~HITACHI
422

(c)

Basic Operation: Indicates operating principles of a program.

(5) Basic Operation
(a) Upper 8 bits in l6-bit binary are shifted to right.

to bit C.

Lower 8 bits are then rotated to right.

Here LSB is rotated

At this time, LSD in

bit C is rotated to MSB of lower 8 bits.

(b) IX is used to keep track of number of shifts.

9.

1IDf>30S PMILY

SHIPTDlG

SRR

FLOWCHART

Shifts upper 8 bits in l6-bit binary to
L...---,--''---' ----{ right. and shifts LSB to bit c.

~----J

Rotate. lower 8 bits in l6-bit binary to
right. Rotates LSB of upper 8 bits to ItSB

----{ of lower 8 bi ts.

L - - - . - - - - - - l ----{ Decrements shift counter.

( IX)

----{

Tests if shift is completed.

~HITACHI

425

1.1.4 PROGRAM LISTING Format (Format 4)
PROGRAM LISTING Format is represented in Fig. 1.5.
the format is described using Fig. 1.5
(1)

I
ITEM NUMBER AND PROGRAM NAME

(2)

Each item in

(3)

I

I

I II:U/MPU t

IID6305 FAMILY

ILABEL I

(4)------~p~~~G~~~L~IS~T~m~G===y-I------~------L-------------~---L---I

Fig. 1.5 PROGRAM LISTING Format
(1)

ITEM NUMBER AND PROGRAM NAME }

(2)

MCU/MPU

(3)

LABEL

Same as SPECIFICATION Format

~HITACHI
426

(4)

PROGRAM LISTING:

HD6305 FAMILY

9.

SHR

PIlOGRAK LISTING
00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013
00014
00015
00016
00017
0001a
00019
00020
00021
00022
00023
00024

(a

(c)~'
ENTRY:

.
II<

SFT

IX

ReTURNS: SFT

<16-BIT aINARY DATA)

6305 FAMILY

K::U/MPU

DESCRIPTION
(b) Fig. 1 shows example of MOVE execution.
If entry arguments are as shown in
part CD of Fig. 1, data in source
($1000 - $1009) is moved to destina-

CD Entry

argument

~Nffi')

1

DEA( RAM)
($90)

~~HfM)

tion ($90 - $99) as shown in part @

b15 SOA

I 1 : 0 I
b7 DEA. bO
I9 : 0 I

SOA+l bO
0

:

0

I

MCNl'

I

0 : A

l

I

of Fig. 1.
(2) User Notes

Address space
Destinatl.U1l(000

(a) As MeNT (RAM) is only one byte in
length, its data must be between $01
and $FF

Destination
] data block

($Ol~MCNT~$FF).
I--~~

(b) Do not hold MCNT (RAM) to "0", or
MOVE will not execute.
(c) MOVE is located in internal RAM.

@Resu1t
Source
s tart->SlOOO 1--..,......___-1
address
SOA (UM)

Do not move data block to RAM
where MOVE is stored, or execution
can not be stopped.

te length
to be moved
MCNT (RAM)

(d) Hold entry arguments so that source
area (Fig.

2

®)

and destination

area (Fig. 2@) do not overlap.

Fig. 1 Example of MOVE execution

If they do, the source data in
overlapping area (Fig. 2 ®) will be
destroyed.

Source Address space
start
address -.f<:.""",=",.."j---

-}(i\

Destination_~~

start
address

\Ill

}
__-____ C

Fig. 2 Example of overlapping
source area with destination
area

$
440

HITACHI

2.

I

MOVING MEMORY BLOCKS

MCU/MPU

I

lID630S FAMILY

I LABEL I MOVE

I

DESCRIPTION
(3) RAM Description

RAM

Label
b7

Upper byte

SOA

Description

bO

f--

Lower byte

-}

Source start address is stored in 2-byte
hexadecimals.

Destination start address is stored in
l-byte hexadecimal.
I---------! }
MeNT
Length of byte to be moved is stored
in l-byte hexadecimal.
LOA
MSUB
f-Instruction codes shown here are stored
DIS P H
by MOVE.
Source data is loaded into ACCA by
DISP L
calling this area as subroutine.
DEA

~-----i}
-

SPNT

HTS

-

}

Work area is reserved to save contents
of register IX.

I
~HITACHI
441

2.

I

MOVING MEMORY BLOCKS

DESCRIPTION

MCU/MPU

I

HD6305 FAMILY

I LABEL I MOVE

I

(4) Sample Application
MOVE subroutine is called after source start address, destination start
address and length of byte to be moved are held.
WORK 1

RMB

Reserves memory byte for source start

2

address.
WORK2
WORK 3

RMB

RMB

1

Reserves memory byte for destination

1

start address.
Reserves memory byte for loading byte
length to be moved.

WORK 4

RMB

Reserves memory byte for register

2

contents saving.

STA
STX

WORK 4
WORK4+1

LDA

WORKI

STA

SOA

LDA
STA
LDA
STA
LDA

WORK1+1
SOA+I
WORK 2
DEA
WORK 3

STA

MCNT

II JSR

MOVE

}-----

Saves register contents that will be
destroyed by executing MOVE.

}----

Stores source start address into entry
argument (SOA) .

} -----

Stores destination start address into

} -----

entry argument (DEA).
Stores length of byte to be moved into
entry argument (MCNT).

II

LDA

WORK4

LDX

WORK4+1

Calls MOVE subroutine.

}-----

Restores register.

~HITACHI
442

2.

MCU/MPU

MOVING MEMORY BLOCKS

MOVE

HD6305 FAMILY

DESCRIPTION
(5) Basic Operation
(a) In the HD6305 family, IX is one byte in length.

However, index addressing

can be performed with source start address of 2 bytes by calling the
subroutine shown in Fig. 3.
MSllB

LDA
RTS

[) IS

P . .\} Stores instruction codes for the
program into RAM as follows.

lJ
Label
MS L' U

Description

RAM

I--------,,---l}

In,''ock

0080
0080
0082
0083
0084
0088

0002
0001
0001
0004
0001

OEA
MCNT
MSUB

,.S~NT

1000
1000
A6 06
87 84
86 80
87 85
86 81
87 86
A6 81
87 87
31= 88
8E 88
80 84
8E 82
F7
3C 82
3C 88
3A 83
1011= 26 Fl
1021 81

1000
1002
1004
1006
1008
1DOA
100C
100E
10lO
101'2
1014
1016
1018
1019
1018
10lD

'MOVE
"

MOVEI

RMB
RM8
RMB
RM8

1

1
4

1

ORG

$1000

EOU
LDA
STA
LOA
STA
LOA
STA
LOA
STA
CLR
LOX
JSR
LOX
STA
INC
INC
DEC
BNE
RTS

'11$06
"
MSU8
SOA
"1SU8+1
SOA+1
MSU8+2
II$B1
MSU8+3
SPNT
SPNT
MSU8
DEA
O.X
DEA
SPNT
MCNT
MOVEI

DestInatIon ADDR
Transfer counter
Work aree for subroutIne
RelatIve date of source ADDR

Entry poInt
Store Instructlo~

cod~

Store source ADOR

(H)

(LOA Dlsp.X)

Store source ADOR (ll
Store InstructIon code (RTS)
CLear relatIve d~te of source ADDR
Loa(l reletlve (tllte of sOI/ree ADDR
Load transfer dllte
LOlld rlestlnatlo~ ADDR
Store transfer data
Increment destInatIon ADDR
Increme~t relatIve date of source ADDR
Decrement transfer counter
Looo untIL transfer counter. 0

~HITACHI
445

3.

I

MOVING STRINGS

I

FUNCTION

I

MCU/MPU

I LABEL IMOVES

HD6305 FAMILY

(a) Moves data block in memory to RAM using direct page addressing.

(b) Terminates moving process when terminator $00 is found in data table.
(c) Permits source and destination addresses to be freely selected in the
memory.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

•
x

Storage
Location

Contents

Byte
Lgth.

!

: Not affected

SPECIFICATIONS
ROM (Bytes)
34

: Undefined

RAM (Bytes)

Result

:

8
Source
start
address
Entry Destination
start
Arguaddress
ments
Returns

SOAS
(RAM)

I
DEAS
(RAM)

1

x

-

I

x

I

2
No. of cycles

Z

668

•

x

Reentrant

I

No
Relocation

x

H

•
DESCRIPTION

IX

C
N

-

-

ACCA

2

Stack (Bytes)

•

No
Interrupt
Yes

1

(1) Function Details
(a) Argument details

SOAS (RAM) : Holds source start address in 2-byte hexadecimals.
DEAS (RAM) : Holds destination start address in I-byte hexadecimal.

SPECIFICATIONS NOTES

I

"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed to
put terminator at the 16th byte.

~HITACHI
446

3.

HD6305 FAMILY

MCU/MPU

MOVING STRINGS

DESCRIPTION
(b) Fig. 1 shows example of MOVES execub15 SOAS
SIlAS
tion.
Entry
!S~)~~Hl~~1)1
I
:
1/
I
" :
If\
\Y
b7 Ilf:AS bO
If entry arguments are as shown in
arguments IH:AS(ltA~t)1
:
I
part

(Suo)

CD of Fig. I, data in source

II

bO

I

.

Destination~~~~

When

start ~ $\'"
addres s
DEAS (RAM)

it loads terminator $00, MCU
terminates moving process.
(2) User Notes

_

l

1/

Address space

($1000) is moved to destination ($90)
as shown in part ® of Fig. 1.

""

I

®Result

r-~":'--i

JDestination
data block

1

Source
start-·$IUUU
add r es s
1--"'""-'--'----1
SOAS (RAM)
Source data
1--"""':'-.---1 J b 10 c k

(a) Source data must not contain any $00
function other than terminator.
(b) MOVES is located in internal RAM.
Do not move data block to RAM

Terminator:
indicating
end of data
block

where MOVES is held, or execution
can not be stopped.
(c) Hold entry arguments so that source
area (Fig. 2@) and destination area
(Fig. 2 ©) do not overlap.

Fig. 1 Example of MOVES execution

1£ they

Source
start

do, the source data in overlapping
area (Fig. 2 ®) will be destroyed.
(d) Amount of data block that can be
moved is MCU address space using
direct page addressing minus a-byte

Address space

address--~~~~----}

Destination
start
address

®

~____ }""...,

I

RAM used by MOVES.

Fig. 2 Example of overlapping
source area with destination
area

~HITACHI
447

3.

! MCU/MPU!

MOVING STRINGS

HD6305 FAMILY

I LABEL TMOVES

I

DESCRIPTION
(3) RAM Description

Description

Label b7

RAM
bO
r---------------------~

Upper byte

S 0 A S f--

__} Source start address is stored in 2-byte
hexadecimals.

Lower byte
DRAS

~----I}

MSSUB

LDA

-

I--

r--

DISP

H

DISP

L

Instruction codes shown here are stored
by MOVES. Source data is loaded into
ACCA by calling this area as subroutine.

-

I--

Destination start address is stored in
I-byte hexadecimal.

-

RTS

SOPNT

~

Work area is reserved to save contents
__________~ } of register IX.

(4) Sample Application
MOVES subroutine is called after source start address and destination start
address are held.
Reserves memory byte for source start
address.
Reserves memory byte for destination
start address.
Reserves memory byte for register contents
saving.

WORKl

RMB

2

WORK 2

RMB

1

WORK3

RMB

2

STA
STX
LDA
STA
LDA
STA
LDA
STA

WORK3
WORK3+1
WORKl
SOAS
WORK1+l
SOAS+I
WORK 2
DEAS

JSR

K>VES

LDA

WORK3

LDX

WORK3+1

}-----

Saves register contents that will be
destroyed by executing MOVES.

}----

Stores source start address in entry
argument (SOAS).

}-----

Stores destination start address in

II

Calls MOVES subroutine.

}----•

448

entry argument (SOAS).

Restores register.

HITACHI

3.

MOVING STRINGS

HD6305 FAMILY

MCU/MPU

MOVES

DESCRIPTION
(5) Basic Operation

(a) In the HD6305 family. IX is one byte in length.

However. index addressing

can be performed with source start address of 2 bytes by calling the
subroutine shown in Fig •. 3.
MSSUB

DISP,X

LDA

}

Store instruction codes for

RTS

the program in RAM as follows.

JJ.

Label
MSSUB

RAM

Description

--I} In"T~"=

I-";;"~____

b.,.,..,'""~'"'""",""""

+-

ood . . fOT LDA DISP. X

Instruction code for RTS

(Notes) *1: Store the upper byte of the start· address in DISP H.
*2: Store the lower byte of the start address in DISP L.

Fig. 3 Details of instruction in RAM
(b) IX is used to indicate source and destination addresses. which are
alternately loaded into IX.
(c) Source data is loaded into ACCA by calling the subroutine shown in Fig. 3.
ACCA data is tested if it is terminator.

I

If so. MOVES is terminated.

If not. moving process continues until the terminator is found.

~HITACHI
449

3.

H0630S FAMILY

MOVING STRINGS

MOVES

FLOWCHART

Stores LOA operation code, destination
start address, RTS operation code so
that LOA OISP,X and RTS can be
executed in RAM.
$81-+MSSUD+3

----[ Clears source address pointer.

---{ Loads destination address pointer into
IX.
---{ Loads source data block into ACCA.

if source data is terminator
or not. If so, terminates MOVES.

---{ Loads destination address into IX.
---{ Stores source data in destination area.
---{ Increments destination address.

---{ Increments source address pointer.

___ { Executes LDA OISP ,X in RAM and
loads source data into ACCA.

(Note)

* MSSUB

does not appear in the PROGRAM LISTING because it is stored in RAM.

~HITACHI
450

3.

I

MOVING STRINGS

PROGRAM LISTING

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040

I

MCU/MPU

I

I

HD6305 FAMILY

LABEL

I

MOVES

********************************-***************

*
*

*

NAME: MOVING STRINGS (MOVES)

*
*

*

************************************************

0080
0080
00B2
00B3
0087

0002
0001
0004
0001

1000
1000
1002
1004
1006
1008
100A
100e
100E
i010
1012
1014
1016
1018
lOlA
101B
10lD
101F
1021

1000
A6 06
B7 83
B6 80
B7 84
B6 81
B7 85
A6 81
B7 86
3F 87
BE 87
BD 83
27 09
BE 82
F7
3C 82
3C 87
20 F1
81

,.

*
SOAS (SOURCE ADDR)
ENTRY
*
*
DEAS (DESTINATION ADDR)
*
*
RETURNS
NOTHING
*
*
*
*
************************************************
*
ORG
S80
*SOAS RMB
Source ADDR.
2
DEAS
MSSUB
SOPNT

RMB
RMB
RMB

1
4
1

*

ORG

S1000

*MOVES

EQU
LOA
STA
LOA
STA
LOA
STA
LOA
STA
CLR
MOVESI LOX
JSR
BEQ
LOX
STA
INC
INC
BRA
MOVES2 RTS

*IISD6

MSSUB
SOAS
MSSUB+l
SOAS+1
MSSUB+2
IIS81
MSSUB+3
SOPNT
SOPNT
MSSUB
MOVES2
DEAS
O.X
DEAS
SOPNT
MOVESI

Destination ADDR.
WorK area tor subroutine
ReLative data ot source ADDR

Entry point
Store instruction code (LOA Disp.X)
Store source ADDR (H)
Store source ADDR

(Ll

Store instruction code (RTS)
CLear reLative data ot source ADDR
Load reLative data of source ADDR
Load transter data
Brench it transter data = 0
Load destination ADDR
Store transter data
Increment destination ADDR
Increment reLative data of source ADDR
Branch MOVES

~HITACHI
451

4.

I

BRANCHING FROM TABLE

I

FUNCTION

I

MCU/MPU

HD630S FAMILY

I

LABEL

I

CCASE

Stores service routine start address in RAM corresponding to the I-byte

(a)

command in RAM.
(b) Permits easy decoding and processing of keyboard and other data inputs.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

•

: Not affected

SPECIFICATIONS
ROM (Bytes)

x : Undefined

Storage
Location

Contents

Byte
Lgth.

1:

43
RAM (Bytes)

Result

7

Command

CMMD
(RAM)
TBTOP
(RAM)

Program
start
address

TBTOP
(RAM)

Returns

2

Bit C
(CCR)

1

I

x

I

2
No. of cycles

C

Z

169

t

x

Reentrant

N

I

No
Relocation

x

H

Command
existance

DESCRIPTION

2

•

Stack (Bytes)

IX

ACCA

I

Entry Data
table
start
address
Arguments

1

•

•

No
Interrupt
Yes

I

(1) Function Details

(a) Argument details
CMMD (RAM) : Holds command such as ASCII.
TBTOP(RAM): Holds data table address in which the command corresponding
to that in CMMD (RAM) and command service routine start address
have been stored in 3-byte units.

After CCASE execution, it

contains the service routine start address in 2-byte hexadecimals
corresponding to the command in CMMD(RAM).
Bit C : Indicates CCASE termination.
Bit C=l : Data in data table is the same as that in CMMD(RAM).
Bit c=o : Data in data table differs from that in CMMD(RAM).
SPECIFICATIONS NOTES

I

"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed
to find data at the end of 3 data units.

~HITACHI
452

4.

1

BRANCHING FROM TABLE

MCU/MPU

HD630S FAMILY

LABEL

I

CCASE

I

DESCRIPTION

(b) Fig. I shows example of CCASE execution.

I

b7

CIIMD

bO

I.:. I
CDEntry
blS TBTOP TBTOP+1 bO
!
arguments T'/I?&.(N M) I I : D I • : • I
C~r.~\RAM)

If entry arguments are as

shown in part CD of Fig. I, CCASE
locates start address of command

,

Return
f
bitCblSTBTOP TBTOP+lbO
®argumentsl T~m~W')[Q I I : • I • : • I

service routine in data table (Fig.
2) and stores it in TBTOP (RAM) as

Fig. 1 Example of CCASE execution

shown in part ® of Fig. 1.
(c) Data table shown in Fig. 2 must be
set up before executing CCASE.

Address

Memory spaCQ

It
Start address _ _ $1 no 0 {
of data table
TBTOP (RAM)
Data block 1

contains 3-byte data units beginning

$4- 1

$ 10
~:...$~:....t1--1

at $IDOO and terminator indicating
the end of the table.

r-S ... 2

Data block 2 {

The first

$ 10
$ +5

Command 'A'

} Service routine

start address
I AI

for comnand
Coumand 'B'

} Service routine

~~:!ndd1~~SS

for

I

byte of the 3-byte data units is
command.

Description

I

[t}_."

The second and third bytes

contain upper and lower bytes of

'_'0-

ing the end of
block data

command service routine start
address respectively.

Fig. 2 Example of data table

(2) User Notes
Do not use $00 as argument (CMMD) or as command in data table.
It functions as terminator only.
(3) RAM Description
Label
RAM
b7

Description
bO
} l-byte command is stored.

CMMD

TBTOP

Upper byte

Lower byte
CSUS

-

Data table start address is stored in
2-byte hexadecimals before execution.
Command service routine start address
is stored in 2-byte hexadecimals after
execution.

}

LDA

DISP

H

-

I-DISP

L

-

Instruction codes shown here are stored
by CCASE. Data in data table are loaded
into ACCA by calling this area as
subroutine.

RTS

~HITACHI
453

4.

I

BRANCHING FROM TABLE

DESCRIPTION

K:U/MPU

I

HD6305 FAMILY

I

LABEL

I

CCASE

I

(4) Sample Application

CCASE subroutine is called after command and start address of data table are
held.
WORK 1

RMB

1

WORK2

RMB

1

----- Reserves memory byte for command.
Reserves momory byte for register contents
saving.

Saves register contents that will be
destroyed by executing CCASE.

STX

WORK2

LDA

1I$1D

STA

nrop }

LDA
STA
LDA
STA

11$00

TBTOP+l
WORKl
CMMD

II JSR

CCASE

LDX
BCC

WORK2
ERROR

Stores data table start address into
entry argument (TBTOP).

}

II

----- Stores command into entry argument (CMMD).
----- Calls CCASE subroutine.
Restores register.
Tests if there is data corresponding to
inputted command in data table.

*

Program branching to
command service
routine

ERROR

IERROR program I
ORG
FCC
FDB

$IDOO
'A'

FCC
FDB

'B'
$1045

FCB

$00

Executes error program because there is
no data corresponding to inputted
command in data table.
Start address of data table.
Command 'A'
Start address of command service routine
in case of command 'A'.
Command 'B'
Start address of command ser"ice routine
in case of command 'B'.

$1020

----- Indicates the end of data block.

$
454

HITACHI

4.

MCU/MPU

BRANCHING FROM TABLE

HD6305 FAMILY

CCASE

DESCRIPTION
(Note)

*

Example of branching to command service routine after CCASE execution:
CCASE functions only to store start address of command service routine in
TBTOP (RAM).

Program as in the example below to branch to command

service routine.

Method used in this example is to store operation

codes for JMP in TBTOP-l (RAM) and jump to command service routine.

J_S_R____C_C_A_S_E_--IJ11 ..... Calls CCASE subroutine.

Iul_ _

ERROR ·· .. ·······Branches to ERROR i f bit C is cleared.
#$CC
} ..... Stores JMP operat~on
.
code in RAM.
TBTOP-l

BCC
---.----LDA
STA
Jump to
command service J M P
routine

TBTOP-l

······Jumps to command service routine.

I

---~~~===-------------~
ERROR

E_RR_O_R_p_r_O_g_r_a_m_ _-,

LI_ _ _

(5) Basic Operation
(a) In the HD6305 family, IX is one byte in length.

However, index addressing

can be performed with data table start address of 2 bytes, by calling the
subroutine shown in Fig. 3.
eSUB

Label
CSUB

LDA
RTS
Jj.
RAM

DIS P, X

}

Stores instruction codes for
the program in RAM as follows.

Description

I-":;":"';;"~;':"'-:--I} 10"="00 00<1. for LOA DISP. X
~~...............,..,..,..,..,..,....,..,.,

+-

Instruction code for RTS

(Notes) *1: Stores the upper byte of the start address in DISP H.
*2: Stores the lower byte of the start address in DISP L.

Fig. 3 Details of instruction in RAM

~HITACHI
455

4.

BRANCHING FROM TABLE

DESCRIfrION

r

MCU/MPU

I

1

HD6305 FAMILY

I I
LABEL

CCASE

(b) IX is used to indicate data table start address.
(c) By calling the subroutine shown in Fig. 3, data table commands are read in
order from start address and compared with entry argument contents.
(d) If the data table commands match the entry argument contents (CMMD) , bit
C is stored and CCASE is terminated.
(e) If terminator $00 is found in data table, bit C is cleared and CCASE is
terminated.

~HITACHI
456

4.

HD6305 FAMILY

BRANCHING FROM TABLE

FLOWCHART

Stores LDA operation code,
destination start address, RTS
instruction code to execute
LDA DISP, X and RTS in RAM area.

___ ~Clears data table address pointer.
___ [LoadS I-byte from data table
into ACCA.
---[ Clears bit C.
(ACCA)=$~~_{Tests i f data table command

is terminator or not.
r -____~~~~$;OO

___ {In:rements the data table address
po~nter.

---1

Compares entry argument
data table command. If
adds "2" to the pointer
it with next data table

(CMMD) and
different,
to compare
command.

---IIf matched, stores command service
routine start address in RAM.

---I
n

*

c

T

Sets bit C to "1".

s

sun

_-_{Executes LDA DISP,X in RAM
and loads source data into ACCA.

(Note)

*

CSUB does not appear in the PROGRAM LISTING because it is stored in RAM.

~HITACHI
457

4,

I

BRANCHING FROM TABLE

PROGRAM LISTING

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021.
00072
00023
00024
00025
00026
00027
00028
00029
00030
0003t
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
n004"(
000<\4
00045
00046
00047
00041'1

I

I

HD6305 FAMILY

I

LABEL

I

ceASE

*************************************************

'"
'"
NAME : BRANCHING FROM TABLE (CCASE)
'"
'"
'"
'"
*************************************************
'"
'"
(COMMAND
ENTRY
CMMO
*
'"
T8TOP (' 1

II

n 1

STX

In' 2

,
•
•

,
•
7

,

(I

:~

tI II 1 1

ET\.

() ('

11 1 0 0

EOT

P{' 4-

IJ

1 () 1

J.::";U

:\Ah:

o

1 1 II

Al'h:

SY.\

II 1 1 1

~
II

1 1

1 u

0

A



II f; L

ETB

==
U

II

(J

liS

(' A.\

\I

X

1u

1

liT

f:M

,
F:

A

1 0 1 tJ

I.F

S l: II

H

1 0 1 1

\,T

J.; S ('

('

i 1

0

rr

}' s

i<

/)

1 1 0 1

(' R

liS

i=

M

E

1 I 1 0

SO

HS

F

1111

S I

\' S

11

0

(I

III

•

I II (I
(I

1 1 II

"

K

"

:-;

/

~HITACHI
466

I 0 I

!lEI.

6.

CONVERTING ASCII INTO I-BYTE
HEXADECIMAL

HD630S FAMILY

MCU/MPU

FLOWCHART

NIBBLE
NIBBLE:'---~----/

Tests if entry argument's
ASCII is '0' or less.

(bit C)=l

Tests if entry argument's
ASCII is 'G' or more.
(bit C)=l

Tests if entry argument's
ASCII is 'A' or more.
bit: N = 0
'A' to 'F'
bit N = I : '0' to '@'.
(bit N)=O

•
Tests if entry argument's
ASCII is within range of ':' to '@'.
'0' to '9'
bit C 0
bit C = I : , :' to '@'.

(bit C)=l

NIBI

-----~ Converts

ASCII into I-byte hexadecimal.

-----[ Clears bit C.

~HITACHI
467

6.

CONVERTING ASCII INTO I-BYTE
HEXADECIMAL

K:U/MPU

I

I

LABEL

*************************************************

1000
1000
1002
1004
1006
1008
100A
lOOC
100E
1010
1012
1013

1000
AO 30
25 OF
AB E9
25 OB
AB 06
2A 04
AB 07
25 03
AB OA
98
B1

*
*
NAME : CONVERTING ASCII
*
INTO 1-BYTE HEXADECIMAL (NIBBLE) *
*
*
***************************************************
*
*
ACCA (ASCII)
ENTRY
*
*
RETURNS : ACCA (BINARY DATA)
*
CARRY (C=0:TRUE.C-1:FALSE) **
*
*
*
*************************************************
*
ORG
S1000
*NIBBLE EQU
Entry poInt
*
ACCA (ASCII code) - '0' 7
SUB
11'0

NIBl
NIB2

BCS
ADD
BCS
ADD
BPL
ADD
BCS
ADD
CLC
RTS

NIB2
IISE9
NIB2
116
NIB1
117
NIB2
liSA

~HITACHI
468

HD6305 FAMILY

I

PROGRAM LISTING

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
'00023
00024
00025
00026
00027

I

Branch If ACCA('O'
ACCA - 'G' -) ACCA
Brllnch If ACCA)='G'
Test 'O'-'~' or 'A'-'F'
Brllnch It ACCA = 'A'-'F'
Test '0'-'9' or ': I_'G)'
Brllnch It ACCA = ':'-'~'
Convert ASCII Into bInary dllt
CLellr Cllrry

I

NIBBLE

CONVERTING 8-BIT BINARY DATA
INTO ASCII
FUNCTION

7.

MCU/MPU

I

I

HD630S FAMILY

I LABEL ICOBYTE

(a) Converts 8-bit binary data in ACCA into two ASCII characters and stores
result in RAM.
(b) Utilizes 7-bit ASCII in arguments.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

.:

Storage
Location

Contents

Byte
Lgth.

Not affected
Undefined

:

)(

1

SPECIFICATIONS
ROM (Bytes)
26

: Result

RAM (Bytes)
2

ACCA
8-bit
Entry binary
data

ACCA

I

1

Arguments

)(

COB
(RAM)

2

I

)(

C

Z

)(

)(

N
2-digit
Returns ASCII

IX

)(

H
)(

I

•

Stack (Bytes)

I

2
No. of cycles
63
Reentrant
No
Relocation
No
Interrupt
Yes

DESCRIPTION

I

(1) Function Details
(a) Argument details
ACCA : Holds 8-bit binary data to be
converted into ASCII.
COB : Holds data converted, from
(RAM)
upper and lower 4 bits of
8-bit binary data into 2-digit
ASCII, is set.

ACCA
b7
{ (8-bi t binary
argument
$F3)
~

CD Entry

bO

AfrA

I .. : a I

rOB (RAM)blScOIl
®Return
(2-digit
6
argument ASCII
'F'=$46,'3'=$33)

I•: I

\

COlII-I

a

bO

:" I

(b) Fig. 1 shows example of COBYTE execution.

If entry argument is as

shown in part CD of Fig. I, data

Fig. 1 Example of COBYTE
execution

converted from 8-bit binary data
into ASCII is contained to COB (RAM)
as shown in part ® of Fig. 1.
SPECIFICATIONS NOTES

I

"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed to
convert 8-bit binary data into ASCII.

~HITACHI
469

7.

I

CONVERTING 8-BIT BINARY DATA
INTO ASCII

MCU/MPU

I

HD6305 FAMILY

I

I

LABEL COBYTE

I

DESCRIPTION
(2) User. Notes

If 8-bit binary data in ACCA needs to be retained after COBYTE execution, it
should be saved in memory before execution.
(3) RAM Description
Description
RAM

Label

b7
COB

bO
Upper byte

-

-

Lower byte

Data is stored which have been converted
from upper 4 bits of 8-Hit binary data
into one-digit ASCII.
Data is stored which have been converted
from lower 4 bits of 8-bit binary data
into one-digit ASCII.

(4) Sample Application
COBYTE subroutine is called after 8-bit binary data is held.
WORKl

RMB

1

WORK2

RMB

2

WORK3

RMB

1

Reserves memory byte for 8-bit binary
data.
Reserves memory byte for 2-digit ASCII.
Reserves memory byte for register contents
saving.

I
I
I
I

Saves register contents that will be
destroyed by COBYTE execution.
----- Loads 8-bit binary data into entry
argument.

STX

WORK3

LDA

WORKl

JSR

COBYTE

LDA
STA
LDA
STA

COB
WORK2
COB+l
WORK2+l

LDX

WORK 3

II

----- Calls CO BYTE subroutine.

}----

Stores 2-digi t ASCII (return argument
(COB) ) in RAM.
Restores register.

~HITACHI
470

7.

CONVERTING 8-BIT BINARY DATA
INTO ASCII

DESCRIPTION

I

HD6305 FAMILY

MCU/MPU

I LABEL ICOBYTE

I

(5) Basic Operation
(a) 8-bi t binary data in ACCA is divided into 4 upper and 4 lower bits.
(b) Divided data is then checked by a comparison (instruction CMP). If data is
between $00 and $09 (~: blocked area in ASCII table shown as Table 1) ,

(c=J in

$30 is added. If data is between $OA and $OF
added. Result is converted into ASCII.

Table 1), $37 is

Table 1 ASCII Table

~
LSD

"
I

000

00 1

o0

0

u

XUL

IlLE

o0

0 1

SOH

Del

o fl

1

,
,
•
,

u

STX

l>C2

00 1 1

ETX

Df"

o

6

,

•

u0

o1

0

SP

o

I I

r--;)

I 00

.

.-A

101

p

R

+

C

T

EOT

1>(' 4

.;;o.;u

:\AK

o

1 1 0

Af'i\

SYS

t'

v

It

111

UEL

ETB

"-G

W

<'A!\

II

X

U

us

•

10 0 1

liT

A

10 1 0

LF

St:H

1 0

(I

f;

B

1 fIll

VT

ESC

1 1

II

f' F

rs

II

1 1 u 1

(' R

tiS

E

111 II

SO

Hs

F

1111

S I

\' S

(I

D

•

U

'"

~l

('

III

Q

1

1

o 10

1 10

Y

~

Z
K

'd

"

~

/

'!

u

DEL

~HITACHI
471

7.

CONVERTING 8-BIT BINARY DATA
INTO ASCII

~u/MPu

HD630S FAMILY

FLOWCHART

___ {

Saves 8-bit binary data of entry argument.

---{ Shifts upper 4 bits of 8-bit binary data
into lower 4 bits.
---{ Converts upper 4 bits into ASCII.
___ {

Stores result of ASCII conversion in RAM.

___ { Restores 8-bit binary data of entry
argument.

---{
---{

Clears upper 4 bits of 8-bit binary data.

Converts lower 4 bits into ASCII.

___ {

Stores results of ASCII conversion in RAM.

___ [

Converts entry data between $00 and $09
into ASCII.

___ {

Tests if data is $09 or less, or $OA
or more.

R T S

Converts data between $OA and $OF into
ASCII.

472

~HITACHI

7.

CONVERTING 8-BIT BINARY DATA
INTO ASCII

PROGRAM LISTING

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036

I

I

K:U/MPU

I

HD6305 FAMILY

I

LABEL

I

COBYTE

************************************************

'"

'"

NAME : CONVERTING 8-BIT BINARY DATA
'"
'"
(COBYTE)
INTO ASCII
'"
''""
'"
************************************************
'"
'"
ENTRY : ACCA (8-BIT BINARY DATA)
'"
'"
RETURNS : COB (2-BYTE ASCII)
'"
''""
************************************************'"
0080

'"

ORG

S80

0080 0002

COB

'"

RMB

2

1000

'"

ORG

S1000

1000
1001
1002
1003
1004
1005
1007
1009
100A
100C
100E
1010
1011
1013
1015
1017
1019

1000
97
44
44
44
44
AD OA
B7 80
9F
A4 OF
AD 03
B7 81
81
AB 30
Al 39
23 02
AB 07
81

'COBYTE
"

Eau
TAX
LSR
LSR
LSR
LSR
BSR
STA
TXA
AND
BSR
STA
RTS
CONIB ADD
CMP
BLS
ADD
CONIBl RTS

'"
A
A
A
A
CONIB
COB

2-byte ASCII

Entry point
Trensfer 8-blt blnery dete
Shift upper 4 bits to Lower 4 bits

IlS0F
CONIB
COB+l

Convert upper 4 bits Into ASCII
Store ASCII
Trensfer 8 bit binery dete
Mesk upper 4 bits
Convert Lower 4 bits into ASCII
Store ASCII

11'0
11'9
CONIBl
1l$07

Convert Into ASCII ('0'-'9')
ASCII = '0'-'9' or 'A'-'F' ?
Brench If ACCA = '0'-'9'
Convert Into ASCII ('A'-'F')

~HITACHI
473

COUNTING NUMBER OF LOGICAL "1"
BITS IN 8-BIT DATA

8.

I

MCU/MPU

I

FUNCTION

I

HD6305 FAMILY

LABEL

I

RCNT

(a) Counts number of logical "1" bits in 8-bit data string in ACCA, and stores
result in RAM.
(b) Permits easy parity checking.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

•

Not affected

:

SPECIFICATIONS
ROM (Bytes)

x : Undefined

Storage
Location

Contents

Byte
Lgth.

1:

14

Result

RAM (Bytes)
1

ACCA
8-bit
Entry data

ACCA

1

I

•I
•
C

Arguments
Number of
Relogical
turns
"1" bits

HBIT
(RAM)

N

1

x

R

•
DESCRIPTION

IX
x

Stack (Bytes)

I

0
No. of cycles

Z

134

x

Reentrant
No

I

•

Relocation
No
Interrupt
Yes

J

(1) Function Details
(a) Argument details
ACCA : Holds 8-bit data in which
number of logical "1" bits

CD

is counted.

(b) Fig. 1 shows example of RCNT execuIf entry argument is as

shown in part

CD of

Fig. 1, number of

logical "1" bits in 8-bit data
string is contained in RBIT (RAM) as
shown in part

® of

SPECIFICATIONS NOTES

I

I. I
I

\

RBIT : Holds numb.er of logical "I"
(RAM)
bit in 8-bit data.
tion.

bO
b7 A('C'A
ACCA
loll 1111 01 111
Entry
{(8-bit
argument data $76)
There are five
l' s.

®

RBIT (RAM)b7
Return {(The bit
..
argument number
of logical
1t1" $05)

I

!

IIBIT

:

Fig. 1 Example of HCNT
execution

Fig. 1.

I

"No. of cycles" in "SPEC IFICATIONS" represents the number of cycles needed to
count number of logical "1" bits in 8-bit data string.

~HITACHI
474

bO

• I

8.

COUNTING NUMBER OF LOGICAL
BITS IN 8-BIT DATA

"1"1

MCU/MPU

1

HD630S FAMILY

1 LABEL 1 HCNT

I

DESCRIPTION

(c) Contents of ACCA are saved after HCNT execution.
(2) User Notes
When counting number of logical "0" bits. take 1 's complement of ACCA before
HCNT execution.
(3) RAM Description
Label

Description

RAM

b7
HBI

bO

TIL-_ _ _ _ _---.JI

Number of logical "1" bits is stored
in I-byte hexadecimal.

(4) Sample Application
Subroutine HCNT is called after 8-bit data is held.
----- Reserves memory byte for 8-bit data.

WORK 1

RMB

1

WORK2

RMB

1

Reserves memory byte for number of
logical "1" bits in 8-bit data string.

WORK 3

RMB

1

Reserves memory byte for register contents
saving.

six

WORK 3

Saves register contents that will be
destroyea by HCNT execution.

LDA

WORK 1

Loads 8-bit data into entry argument
(ACCA).

JSR

HCNT

LDA

HBIT

STA

WORK 2

LDX

WORK3

Calls HCNT subroutine.

II

}

Stores number of logical "1" bits (return
argument (HBIT» in RAM.
----- Restores register.

~HITACHI
475

8.

COUNTING NUMBER OF LOGICAL
BITS IN 8-BIT DATA

DESCRIPTION

"1"1

MCU/MPU

I

HD6305 FAMILY

I

LABEL

I

RCNT

J

(5) Basic Operation
(a) IX is used to indicate number of 8-bit data rotations.
(b) Using rotate (instruction ROL) , data in ACCA is loaded into bit C one by one.
(c) Bit C is checked.

If "1", RBIT (RAM) is incremented; if "0", no operation

applied.
(d) IX is decremented each time (b) and (c) are executed.

(b) and (c) are

looped until IX is "0".
Number of logical "1" bits in 8-bit data is then determined.

~HITACHI
476

8.

COUNTING NUMBER OF LOGICAL "I"
BITS IN 8-BIT DATA
FLOWCHART

MCU/MPU

HD630S FAMILY

HeNT

HCNT

----[

Loads "8" in counter for execution of 8-bit
processing.

----I

Clears counter (HI bit counter) that keeps
track of number of logical "I" bits.

----{
----{

Rotates MSB of 8-bit data in bit C.

Tests if 8-bit data is "I" or "0".

When 8-bit data is logical "1", increments
HI bit counter.
Decrements counter every time one bit is
counted.
Tests if 8-bit processing is
executed.

( IXl#O

----~

Returns 8-bit data to entry state.

~HITACHI
477

8.

COUNTING NUMBER OF LOGICAL "1"
BITS IN 8-BIT DATA

K:u/MPU

I

J

LABEL

..
.....
..
NAME : COUNTING NUMBER OF LOGICAL "1"
.
(HCNT>
BITS IN B-BIT DATA
..************************************************
..
....
.....
ENTRY : ACCA (B-BIT DATA)
....
RETURNS : HBIT (HIGH BIT COUNTER)
..************************************************
************************************************

.

OOBO
ooao 0001
1000
1000
1002
1004
1005
1007
1009
100A
100C
1000

1000
AE oa
3F aO
49
24 02
3C aD
SA
26 Fa
49
81

..
HBIT

.
.HCNT

HCNTl
HCNT2

ORG

$BO
High b It counter

RMB
ORG
ECU
LOX
CLR
ROL
BCC
INC
DEC
BNE
ROL
RTS

$1000

..liB

HaIT
A
HCNT2
HBlT
X
HCNTl
A

~HITACHI
478

HD6305 FAMILY

I

PROGRAM LISTING

00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013
00014
00015
00016
00017
0001a
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028

I
I

Entry point
Set rotete counter
Cleer high bit counter
Rotete a-bit dete lett
Branch If cerry=O
Increment high bit counter
Decrement rotate counter
Loop until rotete countereD
Replace a-bit dete

I

HCNT

9.

SHIFTING l6-BIT DATA

I

MCU/MPU

I

FUNCTION

I LABEL I SHR

HD630S FAMILY

(a) Shifts l6-bit binary data in RAM to right.
(b) Permits number of shifts to be freely determined.
(c) Permits easy mUltiplication of l6-bit binary data by 2-n (n : number of
shifts) •
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

.:

Storage
Location

Contents

Byte
Lgth.

SPECIFICATIONS

Not affected

x :

Undefined

t:

Result

ROM (Bytes)
8

RAM (Bytes)
2

l6-bit
binary
data to
be
Entry shifted
to right
Arguments
Number of
shifts

ACCA
SFT
(RAM)

IX

2

•

I

1

I

DESCRIPTION

SFT
(RAM)

2

I

x

0
No. of cycles

C

z

110

x

x

Reentrant

N

I

No

•

x

ReShift
turns results

Stack (Bytes)

IX

H

Relocation
No

•

Interrupt
Yes

I

(1) Function Details
b7

(a) Argument details
SFT : Holds l6-bit binary data to
(RAM)
be shifted to right. After

Entry
CD argumen ts

{""""'''~,
Sf1,

(:!q'IH II)

IX

: Holds number of l6-bit binary

:

bO

, I

SrI

Sf'IH

bO

I'I'I"H'>'I"I'I'I'I+'I'I"I'I'I
\\\0

® argument
Return {~nm~1) "+1+1'1°1"1'1"1°1'1'1'10101'101

data to be shifted to right.

SPECIFICATIONS NOTES

b 15

IX

b~'\\

SHR execution, contains shift
result.

1 "

S)'I

Fig.

1

HI+'

Example of SHR
execution

J

"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed to
shift l6-bit binary data to right by 7 bits.

~HITACHI
479

9.

I

SHIFTING 16-BIT DATA

I

DESCRIPTION

MCU/MPU

(b) Fig. 1 shows example of SHR execution.

l

HD6305 FAMILY

1LABELl

SHR

If entry arguments are held as shown

in partG) of Fig. 1, 16-bit binary data is shifted to right as shown in part
®of Fig. 1.
(2) User Notes

Be sure to hold data into IX within range of $01 :;; IX :;; $OF.
When data outside this range is held, SFT (RAM) becomes "0".
(3) RAM Description
RAM

Label
SFT

b7

bO

-

-}

Upper byte
Lower byte

Description
l6-bit binary data to be shifted to right
is stored before execution.
Shift result is stored after execution.

(4) Sample Application

SHR subroutine is called after number of shifts and l6-bit binary data to be
shifted to right are held.
WORK 1

RMB

2

WORK 2

RMB

1

WORK 3

RMB

2

WORK 4

RMB

1

STX

WORK 4

LDA
STA

LDA
STA
LDX

II JSR
LDA
STA
LDA
STA
LDX

WORK 1 }
SFT
WORK 1+1
SFT+l
WORK 2
SHR

------Reserves memory byte for 16-bit binary data.
Reserves memory b),te for number of shifts.
Reserves memory byte for 16-bit binary
shift results.
Reserves memory byte for register contents
saving.

Saves register contents that will be
destroyed by executing SHR.
Stores 16-bit binary data to be shifted
into right in entry argument (SFT).
Loads number of shifts into entry argument
(IX).
Calls SHR subroutine.

SFT
}
Stores shift results regarding l6-bit
WORK 3
binary (return argument (SFT» in RAM.
SFT+1
WORK3+1
WORK 4
----- Restores register.

~HITACHI
480

9.

SHIFTING 16-BIT DATA

DESCRIPTION

I

I

K:u/MPU

I

HD6305 FAMILY

I

LABEL

I

SHR

(5) Basic Operation
(a) Upper 8 bits in 16-bit binary are shifted to right. Here LSB is rotated
to bit C. Lower 8 bits are then rotated to right. At this time, LSB in
bit C is rotated to MSB of lower 8 bits.
(b) IX is used, to keep track of number of shifts. IX is decremented each time
(a) is executed. (a) is looped until IX is "0".

~HITACHI
481

9.

SHIFTING l6-BIT DATA

MCU/MPU

HD6305 FAMILY

SHR

FLOWCHART

S H R

----{
----{
----{

---{

Shifts upper 8 bits in l6-bit binary to
right, and shifts LSB to bit C.
Rotates lower 8 bits in l6-bit binary to
right. Rotates LSB of upper 8 bits to MSB
of lower 8 bits.
Decrements shift counter.

Tests if shift is completed.

~HITACHI
482

9.

I

SHIFTING 16-BIT DATA

PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024

MCU/MPU

I

HD6305 FAMILY

I LABEL I SHR

I
***********.w***********************************

'"
'"

NAME : SHIFTING 16-BIT DATA

(SHR)

"

'"
'"
,.'"
ENTRY
SFT (16-BIT BINARY DATA)
IX
(SHIFT COUNTER)
'"
RETURNS
SFT (16-BIT BINARY DATA)
'"
'"
'************************************************
"
'"
'"
$80
ORG
'SFT
"
RMB
16-bit binery data
2
'"
'"
,.'"

************************************************

0080
0080 0002

,.

1000

,.

ORG

$1000

SHR

EOU
LSR
ROR
DEC
BNE
RTS

'"
SFT
SFH1
X
SHR

1000
1002
1004
1005
1007

1000
34 80
36 81
SA
26 F9
81

Entry point
Shift upper byte to right
Rotate lower byte to right
Decrement shift counter
Loop until shift counter = 0

~HITACHI
483

10.

I

MCU/MPU

4-DIGIT BCD COUNTER

I

FUNCTION

I LABEL IDECNT

HD6305 FAMILY

(a) Increments 4-digit BCD in RAM.
(b) Permits easy counting of interrupts (external, timer, etc).
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

.:

Not affected

SPECIFICATIONS
ROM (Bytes)

x : Undefined

Storage
Location

Contents

Byte
Lgth.

13

1: Result

RAM (Bytes)
2

ACCA
Entry

-

-

4-digit
BCD
counter

Arguments

Returns Counter
overflow or
not?

DESCRIPTION

I

-

DCNTR

2

(RAM)

1

Z

!

x

N

I

H

•

I

x

C

x

Bit C
(CCR)

Stack (Bytes)

IX

I

x

0
No. of cycles
42
Reentrant

•

No
Relocation
No
Interrupt
Yes

J

(1) Function Details
(a) Argument details
DCNT
(RAM)

: Used as counter of 4-digit

Counts at every DECNT

BCD.

CD Be fo re

{ IJ('N1'R( RAM)
execution (..... )

b 15

I

•

execution.
Bit C : Indicates counter status
(CCR)
after DECNT execution.

R

bi< C b15

®arguments
eturn {IX'NTH01AM) ~
(4JOO)

0

(see Fig. 2).

J"",~.
I

normal.

SPECIFICATIONS NOTES

I
~HITACHI

484

Fi g. 1 Example of DECNT

execution

I •:•I

I•: I

Bit C=1 : Counter overflows
Bit C=O : Counter has returned

bO

IX'NTR IX'NTItH
:

0

b+o

In the first loop, counts-up .lower
2 digits in 4-digit BCD counter.
In the second loop, adds carry to upper 2
digits.

----{

Adjusts result of addition into decimal,
and stores it in 4-digit BCD counter's
RAM.

---- {

Decrements pointer indicating address of
4-digit BCD counter and counter indicating
number of additions.

I

____{: Te.t. if count.-op i . completed.

~HITACHI
487

10.

I

4-DIGIT BCD COUNTER

PROGRAM LISTING

I

00001
00002
00003
00004
00005
00006
00007
OOOOS
00009
00010
00011
00012
00013 OOSO
00014
00015 OOSO 0002
00016

00017
0001S
00019
00020
00021
00022
00023
00024
00025
00026
00027
0002S

1000
1000
1002
1003
1004
1006
1007
1009
100A
100C

1000
AE 02
99
4F
E9 7F
SO
E7 7F
SA
26 F7
Sl

K:U/MPU

I

I

I

LABEL DECNT

**************************************************

**

NAME : 4-DIGIT SCD COUNTER (DECNT)

**

*

*

**************************************************

*

*
*
*

ENTRY
NOTHING
RETURNS : DCNTR (BCD COUNTER)
CARRY (C-0:TRUE,C-1:0VeR FLOW)

*

*
*

*
*
**************************************************

*
*
DCNTR
*
*DeCNT

ORG

$SO

RMB

2

ORG

$1000

eou
LOX
SEC
DECNTl CLR
ADC
DAA
STA
DEC
BNE
RTS

BCD counter

Entry point
Load ADDR polnte~ ( addition counter)
Set carry
Clear ACCA
A
DCNTR-l,X Increment BCD counter
Convert Into BCD
DCNTR-1, X Store BCD counter
Decrement ADDR pOinter
X
Loop until ADDR polnter=O
DECNTl

*
112

~HITACHI
488

HD6305 FAMILY

11.

COMPARING l6-BIT BINARY DATA

I

MCU/MPU

I

FUNCTION

HD630S FAMILY

I

LABEL

I

CMP

(a) Determines larger than / smaller than relationship (>,=, <) of l6-bit
binary data of 2 groups, and loads result into bit C and bit Z of ceR.
(b) Utilizes unsigned integers in arguments.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

.:

Not affected

SPECIFICATIONS
ROM (Bytes)

x : Undefined

Storage
Location

Contents

Byte
Lgth.

1

11

: Result

RAM (Bytes)
4

ACCA
First
value

CMD
(RAM)

2

Entry
Second
value

Arguments

ComReparison
turns
results

DESCRIPTION

CMT
(RAM)
bit C
bit Z
(CCR)

I

2

x

IX

I

I

0
No. of cycles

C

Z

20

t

t

Reentrant

N

I

x

1

•

Stack (Bytes)

H

•

•

No
Relocation
No
Interrupt
Yes

I

(1) Function Details

I

(a) Argument details
CMD (RAM) : Holds the first l6-bit binary value.
CMT (RAM) : Holds the second 16-bit binary value.
Bit C, Bit Z (CCR) : Bit C and bit Z of CCR are held according to
comparison results.

SPECIFICATIONS NOTES!
''No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed to
make equal comparand and comparative number.

~HITACHI
489

11.

COMPARING 16-BIT BINARY DATAl

I

I

HD6305 FAMILY

LABEL

I

CMP

I

DESCRIPTION
(b)

K:u/MPu

Table 1 shows example of CMP execution.

If entry arguments are as shown

in Table 1. bit C and bit Z of CCR are set accordingly.

Table 1.

Example of CMP execution

Entry arguments

Return arguments

First value
CMD (2 bytes
RAM)
$F67D

Second value
Large/small
relationship
>

$2200
$4001

<

CMT (2 bytes
RAM)

CCR
bit C

bit Z

$2001

0

0

$2200

0

1

$FOOO

1

0

(c) After CMP execution. entry arguments are contained.
(2) User Notes
When not using upper byte. set "0" in the upper byte.

If "0" is not set.

comparison is performed with undefined data set in the upper byte. and correct
data cannot be obtained.
(3) RAM Description
Label

Description

RAM

bO

b7
C M D

rI-

(

Lower byte
Upper byte

C M T

490

Upper byte

Lower byte

•

-

} The fi,at 16-bit bina'Y value is stored.

-

} ... aecond 16-bit binary value 1s stored.

HITACHI

11.

COMPARING l6-BIT BINARY DATA

MCU/MPU

I

HD630S FAMILY

I

LABEL

I

CMP

I

DESCRIPTION
(4)

I

Sample Application
CMP subroutine is called after the first value and the second value are held.
WORKl

RMB

2

Reserves memory byte for the first

WORK 2

RMB

2

l6-bit binary value.
Reserves memory byte for the second
l6-bit binary value.

Saves register contents that will be
destroyed by CMP execution.

TAX

'O~l
CMD

LDA
STA
LDA
STA
LDA
STA
LDA
STA

WORK2+1
CMT+l

JSR

CMP

TXA
BEQ

SKIP2

Restores register.
Branches to service routine when

BCC

SKIPl

CMD=CMT.
Branches to service routine when

}

Stores the first l6-bit binary value

WORK1+l
CMD+l

WO~2
CMT

into entry argument (CMD).
}

Stores the second l6-bit binary value
into entry argument (CMT).

Calls CMP subroutine.

II

I

CMD>CMT .

SKIP2

l
l

Service routine in easel
of CMDCMT

in easel

User program

~HITACHI
491

11.

COMPARING l6-BIT BINARY DATA

DESCRIPTION
(5)

I

K:U/MPU

I

J

HD6305 FAMILY

I

LABEL

I

CMP

Basic Operation

(a) When more than 2 bytes are compared, perform comparison for each byte.
(b) Bit C and bit Z of CCR are determined as return argument, after comparison
(instruction CMP) are executed.
(c) Upper bytes are compared using one-byte (comparison instruction CMP).
When equal, lower bytes are compared.
When not equal, CMP is terminated.

492

~HITACHI

11.

COMPARING 16-BIT BINARY DATA

MCU/MPU

HD630S FAMILY

CMF

FLOWCHART

---{

(CMD)+(CMT)

Compares upper 8 bits.

(CMD)=(CMT)

(O."H)-(O..,+»

----{

Compares lower 8 bits.

~HITACHI
493

11.

COMPARING 16-BIT BINARY DATA

MCU/MPU

I

I

LABEL

*******************~**************w.*************

**

.
0080
0080 0002
0082 0002
1000
1000
1002
1004
1006
1008
100A

1000
86 80
81 82
26 04
B6 81
B1 83
81

**
*
************************************************
** ENTRY CMD
(COMPARAND)
**
CMT
(COMPARATIVE
NUMBER)
*
** RETURNS CARRY & BIT Z (COMPARISON RESULT) *
*
*************************************************
*
ORG
sao
*CMD
RMB
Comparand
2
NAME: COMPARING 16-BIT BINARY DATA 
bit CIII

is contained in ADED (RAM). If
augend needs to be retained after
bit

+)

0

c01

0

:
:
:

0

A : F

I .... Augend

0

F :

1

I .... Addend

1

A : 0

I .... Addition
result

Description

RAM

b7

bO
Upper byte
Lower byte
Upper byte
Lower byte

-

} "-bit.binary augend i •• tor,d before
execut10n.
16-bit binary addition result is
stored after execution.

-

} "-bit binary addend is stored.

~HITACHI
496

result

Fig. 3 Example of addition when
upper byte is not used

(3) RAM Description

-

[,..-0--,-:....:A:.....JL.......:;A~:.......:-~...J1 .... Addi tion

0

ADD execution, it should be saved
in memory before execution.

ADER

I-Addend

Fig. 2 Example of addition
when carry is generated

destroyed because addition result

r-

8

Carry

(b) After ADD execution, augend is

ADED

9:

'\J

cannot be obtained.

Label

1 :.

12.

I

ADDING 16-BIT BINARY DATA

DESCRIPTION

K:U/MPU

I

lID6305 FAMILY

I

LABEL

I

ADD

I

(4) Sample Application
ADD subroutine is called after augend and addend are held.
WORK 1

RMB

2

Reserves memory byte for 16-bit binary
augend.

WORK 2

RMB

2

Reserves memory byte for 16-bit binary
addend.

WORK3

RMB

2

Reserves memory byte for 16-bit binary
addition results.

WORK4

RMB

1

Reserves memory byte for register contents.

STA

WORK 4

LDA
STA
LDA
STA
LDA
STA
LDA
STA

::1 }____

LDA
STA
LDA
STA
LDA

OVER

I Service

lof carry

Loads l6-bit binary augend into entry
argument (ADED).

WORK 1+1
ADED+l
::2}
WORK 2+1
ADER+l
ADD

BCS

----- Saves register contents that will be
destroyed by ADD execution.

Loads 16-bit binary.addend into entry
argument (ADER).

II

Calls ADD subroutine.
If carry is generated in addition result,
branches to service carry routine.

OVER

Stores addition result (return argument
(ADED» in RAM.
WORK4

----- Restores register.

routine in case

I

~HITACHI
497

I

12.

ADDING l6-BIT BINARY DATA

DESCRIPTION

I

I

K:U/MPU

1

HD6305 FAMILY

I

LABEL

I

ADD

(5) Basic Operation
(a) When more than 2 bytes are added, perform addition for each byte.
(b) Lower bytes (ADED+l, ADER+l) shown in (Formula 1) are added using l-byte
addition (instruction ADD) ignoring bit

c.

When carry is generated after performing (Formula 1), bit C is set.
(ADED + 1) + (ADER + 1) - ADED + 1

------- (Formula 1)

(c) Upper bytes (ADED, ADER) shown in (Formula 2) are added using l-byte
addition (instruction ADC) based on consideration of bit C.
(AD ED) + (ADER) + (bit C) - ADED -------------(Formula 2)
Bit C is taken into consideration because there is carry involved with the
addition result regarding lower bytes executed in (b).

~HITACHI
498

12.

ADDING l6-BIT BINARY DATA

I

MCU/MPU

I

HD630S FAMILY

I LABEL I ADD

I

FLOWCHART

ADD

ADD

I

 SBED+

---{

Subtracts lower 8 bits, and stores result
in minuend RAM (SBED).

---{

Subtracts upper 8 bits considering borrow
(bit C) which occurred in lower 8 bits,
and stores result in minuend RAM (SBED).

I
(SBED)-(SBER)-(bit C)
-SBED

I
RTS

$

HITACHI
505

13.

SUBTRACTING 16-BIT BINARY
DATA

MCU/MPU

I

J LABEL I

,.
,.
NAME : SUBTRACTING 16-BIT BINARY DATA (SUB) "
'"
'"
'"
***************************************************
'"
'"
ENTRY
SBED (MINUEND)
',."
'*"
SBER (SUBTRAHEND)
RETURNS
SBED (RESIDUAl)
'"
CARRY (C=O:TRUE.C=l:BORRDW) *'"
'"
'"
'***************************************************
"
***************************************************

*

0080
0080 0002
0082 0002
1000
1000
1002
1004
1006
1008
100A
100e

1000
B6 81
BO 83
B7 81
B6 80
B2 82
B7 80
81

'SBED
"
SBER

'"
'SUB
"

DRG

$80

RMB
RMB

2
2

DRG

$1000

EQU
LOA
SUB
STA
LOA
SBC
STA
RTS

SBED+1
SBER+1
SBED+1
SBED
SBER
SBED

,.

~HITACHI
506

HD6305 FAMILY

I

PROGRAM LISTING

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028

I

Minuend -)ResiduaL
Subtrahend

Entry point
Load Lower minuend
Subtract,.Lower subtrahend
Store Lower minuend area
Load upper minuend
Subtract upper subtrahend
Store upper minuend area

SUB

14.

MULTIPLYING 16-BIT BINARY
DATA
FUNCTION

I

MCU/MPU

HD6305 FAMTI..Y

I

LABEL

I

MUL

I

(a) Performs multiplication of l6-bit binary data in RAM and stores result
in 32-bit binary in RAM.
(b) Utilizes l6-bi t unsigned integers in arguments.
ARGUMENTS

J

CHANGES IN CPU
REGISTERS AND FLAGS

.:

Not affec ted

x: Undefined

Storage
Byte
Contents
Location Lgth.
Multipli- MCAND
2
(RAM)
cand
Entry
MER
Multi2
(RAM)
plier
Product
Arguments

(Upper 2
bytes)
Returns
Product
(Lower 2
bytes)

DESCRIPTIONS

PRDCT
(RAM)

2

I

1: Result
ACCA

6
Stack (Bytes)

x

IX

I

x

C

Z

x

x

N

I

•

(RAM)

H
2

ROM (Bytes)
33
RAM (Bytes)

x

MER

SPEC IFICATIONS

x

!

I

0
No. of cycles
785
Reentrant
No
Relocation
No
Interrupt
Yes

I

(1) Function Details
(a) Argument details
MCAND (RAM): Holds l6-bit binary multiplicand.
(RAM) : Holds l6-bit binary multiplier.
MER
After MUL execution, the lower 16 bits of multiplication
result is contained.
PRDCT (RAM): Contains upper 16 bits of product.

SPECIFICATIONS NOTES

I

"No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed
to hold $FFFF as entry argument.

~HITACHI
507

14.

MULTIPLYING 16-BIT BINARY
DATA

I

MCU/MPU

I

HD6305 FAMILY

I

LABEL

I

MUL

I

DESCRIPTION

(b) Fig. 1 shows example of MUL execution.
If entry arguments are as shown in
part

CD of

Fig. 1, multiplication

result is stored in PRDCT (RAM) and
MER (RAM) as shown in part ® of Fig.
1.

Fig. 1 Example of MUL execution

(c) Table 1 shows result when "0" is held
as entry argument.
(2) User Notes
(a) As shown in Fig. 2, when not using
upper byte, hold "0" in the upper
byte.

10: 0IF: A I<-MUltiplicand
10 : 0 Is :B I<-Multiplier

xl

If "0" is not held, multipli-

cation is performed with undefined
data, and correct product cannot be
obtained.

10 : 0 I 0

: 0

Is : 81 D : E I <-Product

Fi g. 2 Multiplication example when
upper byte is not used

Table 1 Product when not holding "0" as entry arguments
Entry argument
Multiplicand

Return argument
Product
(PRDCT:PRDCT+1: MER:MER+1)

(MCAND :MCAND+l)

Multiplier
(MER:MER+l)

$**** *

$0000

$00000000

$0000

$**** *

$00000000

$0000

$0000

$00000000

(Note) * $**** indicates hexadecimals.
(b) After MUL execution, multiplier is destroyed because lower 2 bytes of
Product is held in MER (RAM).
If minuend needs to be retained after MUL execution, it should be saved in
memory before execution.

Description

bO

~HITACHI
508

14.

MULTIPLYING l6-BIT BINARY
DATA
DESCRIPTION

I

K:U/MPU

I

HD6305 FAMILY

I

LABEL

I

MUL

1

(4) Sample Application
MUL subroutine is called after multiplicand and multiplier are held.
WORKl

RMB

2

WORK2

RMB

2

WORK 3

RMB

4

----- Reserves memory byte for l6-bit binary
multiplicand.
----- Reserves memory byte for 16-bit binary
multiplier.
----- Reserves memory byte for product.

WORK4

RMB

2

-----, Reserves memory byte for register contents

STA
STX
LDA
STA
LDA
STA
LDA
STA
LDA
STA

WORK 4 } ____ Saves register contents that will be
WORK4+l
destroyed by MUL execution.

JSR

MUL

LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
LDX

PRDCT
WORK 3
PRDCT+l
WORK3+1 >-___ _ Stores 32-bit binary product
(return argument (PRDCT. MER»
MER
WORK 3+2
MER+l
WOBK3+3
WORK4 ]-____ Restores register.
WOBK4+1

WORKl }
KCAND
WORK 1+1
MCAND+l

Stores 16-bit binary multiplicand into
entry argument (MER).

WOBK2 }
MER
WORK2+1
MER+l

Stores 16-bit binary multiplier into entry
argument (KCAND).

----- Calls MUL subroutine.

$

in RAM.

HITACHI
509

14.

MULTIPLYING l6-BIT BINARY
DATA

I

I

MCU/MPU

I

HD6305 FAMILY

LABEL

I

MUL

I

DESCRIPTION
(5) Basic Operation

(a) Fig. 3 shows example of 4-bit binary multiplication.
bit

3 2 1 0

l l l
x)

Multip licand x
bit 0 of multiplier (1)

1 1 0 1

Multiplicand

1 0 0 1

Multiplier

1 1 0 1

Multiplicand x
bit 1 of multiplier (0)
Multiplicand x
bit 2 of multiplier (0)
Multiplicand x
bit 3 of multiplier (1)

o
+)

---- CD

000 0

----@

0 0 0

----®

Partial products

----@

1 1 0 1

1 1 1 0 1 0 1 ---- ®
5

Fig. 3 A multiplication example ($00

x

(

Product

CD + @ + ® + @)

$09 = $75)

Multiplication of 4-bit binary data requires obtaining partial products, as
shown in CD

, @ , ® and

@, and adding them.

(® in Fig. 3 )

Each bit of binary data is either "0" or "1".
partial product is multiplicand
"0", its partial product is "0".

If multiplier bit is 1, its

(CD and @ in Fig. 3), while'if
(@and ® in Fig. 3)

multiplier bit is

(b) Using Fig. 3, the program is explained as follows:
(i) Clears RAM (PRDCT).
(ii) IX is used to indicate number of partial product.
(iii) To determine partial product for each 1 bit, tests whether LSB of
multiplier (MER), is "1" or "0".
(iv) If "1", Adds multiplicand to RAM for product, and stores sum in RAM
for product, because if LSB of RAM for multiplier is "1", partial product
is multiplicand.

If LSB of RAM for multiplier is "0", partial product is

"0", and there is no execution.
(v) To acquire the partial product for the next bit in RAM for
multiplier, rotates RAM for product and RAM for multiplier 1 bit right.
(vi) Decrements IX.
(vii) Loops (iii) to (vi) until IX is "0".

~HITACHI
510

14.

MULTIPLYING l6-BIT BINARY
DATA
FLOWCHART

MCU/MPU

HD630S FAMILY

MUL

----[ Clears RAM where product is to be stored.
____ { Stores counter indicating number of
partial products.

Tests i f LSB of multiplier is

---- [ "1" or "0".

Adds multiplicand to product because
____ { partial product is multiplicand
when LSB of multiplier is "1".

Shifts LSB of product to upper bit
of multiplier, and shifts LSB of
---- { multiplier to bit C by rotating RAM
for the product and multiplier
1 bit right.
Decrements counter indicating number of
---- { partial products.

---- [

Tests i f all the partial products
have been obtained or not.

~HITACHI
511

MULTIPLYING 16-BIT BINARY
DATA
PROGRAM LISTING
I

14.

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00039

....
..

I

MCU/MPU

I

I

LABEL

I

...

**************************~*#*******************

NAME : 16-BIT MULTIPLATION (MUL)

.
...
..
..

....
ENTRY
MACAND (MULTIPLICAND)
(MUL TIPLIER)
MER
....
RETURNS
PRDCT (UPPER PRODUCT>
(LOWER PRODUCT>
MER
..************************************************
..
S80
..MCAND ORG
MuLtipLicend
RM8
2

************************************************

0080
0080 0002
0082 0002
0084 0002
1000
1000
1002
1004
1006
1009
100B
1000
100F
1011
1013
1015
1017
1019
1019
10lD
101E
1020

3F
3F
AE
01
B6
88
B7
86
89
87
36
36
36
36
SA
26
81

PRDCT
MER

..
..MUL

82
83
10
85 OC MUll
81
83
83
80
82
82
82
MUL2
83
84
85
E6

Product (upper bytes)
MuLtipLier-)Product (Lower bytes)

RMB
RMB

2
2

ORG

S1000

CLR
CLR
LOX
BRCLR
LOA
ADD
STA
LOA
ADC
STA
ROR
ROR
ROR
ROR
DEC
9NE
RTS

CLeer product eree
PRDCT
PRDCT+l
Set b it counter
1U6
0.MER+1.MUL2 Brench if MER(O)=O
MCAND+l MCAND+PRDCT-)PRDCT
PRDCT+l
PRDCT+l
MCAND
PRDCT
PRDCT
PRDCT
Rotete product eree
PRDCT+l
MER
Rotete muLtiplier ereeMER+l
-and set LS9 ot MER to carry
X
Decrement bit counter
MUll
Loop until bit counter=O

~HITACHI
512

HD630S FAMILY

MUL

15.

DIVIDING 16-BIT BINARY DATA

I

MCU/MPU

HD6305 FAMILY

I

LABEL

I

DIV

I

FUNCTION

(a) Performs divis ions of 16-bit binary data in RAM and stores result
(quotient and residual) in 16-bit binary in RAM.
(b) Utilizes unsigned integers in arguments.
ARGUMENTS

I

CHANGES IN CPU
REGlSTERS AND FLAGS
: Not affected

•

Contents
Dividend

Byte
Lgth.

DVD
(RAM)

2

Entry
Divisor
Arguments
Quotient
Returns

DVS
(RAM)

t

I

: Result

ACCA
x

x

2

DVD
(RAM)

2

C

Z

x

x

N

I

x

Residual

I

IX

RSD
(RAM)

2

H
x

•

ROM (Bytes)
47
RAM (Bytes)

x : Undefined

Storage
Location

SPEC IFICATIONS

I

6
Stack (Bytes)
0
No. of cycles
1137
Reentrant
No
Relocation
No
Interrupt
Yes

DESCRIPTION

I

(1) Function Details
(a) Argument details
DVD (RAM) : Holds l6-bit binary dividend.
execution.
DVS (RAM) : Holds l6-bit binary divisor.

Contains quotient after DIV

RSD (RAM) : Holds 16-bit binary residual.

SPECIFICATIONS NOTES

I
$

HITACHI
513

15.

DIVIDING 16-BIT BINARY DATA

I

I

MCU/MPU

I

HD630s FAMILY

LABEL

1

DIV

DESCRIPTION

®

(b) Fig. 1 shows example of DIV execution.

Return arguments
bls bO bI5bO

If entry arguments are as shown in
part

CD of

~

Quotient

Fig. I, division result

.... ~

I,VII 111."1101

II.SII H.SJH
(.~uF:\U)

!."'UIIO+)

Residual

is stored in DVD (RAM) and RSD (RAM)
as shown part ® of Fig. 1.
(c) Table 1

S!"IOWS

result of holding

"0"

CD Entry

as argument.

arguments

Fig. 1 Example of DIV execution

(2) User Notes
(a) When not using upper byte as shown in

~

Fig. 2, hold "0" in the upper byte.

... ~

~)~

If "0" is not held, division is
performed with undefined data in the

Fig. 2 DIV example when upper
bytes are not used

upper byte, and correct result cannot
be obtained.
(b) After executing DIV, dividend is
destroyed because quotient is contained
in DVD (RAM).

If dividend needs to

be retained after DIV execution, it
should be saved in memory before execution.

TABLE 1 Results when holding "a" as entry arguments
Entry Arguments
Dividend (DVD)

Return Arguments

Divisor (DVS)

Quotient (DVD)

Residual (RSD)

$**** *

$ 0 0 0 0

$ F F F F

$ F F F F

$ 0 0 0 0

$*****

$ 0 0 0 0

$ 0 0 0 0

$ 0 0 0 0

$ 0 0 0 0

$ F F F F

$ 0 0 0 0

(Note)

*

$**** indicates hexadecimals.

(3) RAM Description

Description

RAM

Label

bO

b7
Upper byte

DVD
I-

Lower byte
Upper byte

OVS

f-

Lower byte
Upper byte

RSO
I-

Lower byte

} l6-bit binary dividend is stored

-

before execution.
16-bit binary quotient is stored
after execution.

-

} l6-bit binary divisor is stored.

-

} Work area is reserved to store
subtraction result of (OVO-DVS).
16-bit binary residual is stored
after execution.

~HITACHI
514

15.

DIVIDING 16-BIT BINARY DATA

I

MCU/MPU

I

HD6305 FAMILY

r LABELl

DIV

I

DESCRIPTION

(4) Sample Application
DIV subroutine is called after dividend and divisor are held.
Reserves memory
divisor.
Reserves memory
dividend.
Reserves memory
quotient.
Reserves memory
residual.
Reserves memory

byte for l6-bit binary

WORKl

RMB

2

WORK 2

RMB

2

WORK 3

RMB

2

WORK 4

RMB

2

WORK 5

RMB

2

STA
STX
LDA
STA
LDA
STA
LDA
STA
LDA
STA

WORK5 } _____ Saves register contents that will be
WORK5+l
destroyed by executing DIV.

II JSR
LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
LDX

WORKl }
DVS
WORK+l
DVS+l

byte for l6-bit binary
byte for l6-bit binary
byte for l6-bit binary
byte in stack register.

Stores l6-bit binary dividend into entry
argument (DVS).

WORK 2 }
Stores l6-bit binary dividend into entry
DVD
WORK2+l ----- argument (DVD).
DVD+l
----- Calls DIV subroutine.

DIV
DVD
WORK 3
DVD+l
WORK3+l
RSD
WORK 4
RSD+l
WORK4+l

~ ____

WORK 5 }
WORK5+l

Stores division result (return arguments
(DVD. RSD» in RAM.

Restores register.

~HITACHI
515

15.

DIVIDING 16-BIT BINARY DATA

I

DESCRIPTION

I

MCU /MPU

I

HD6305 FAMILY

TLABEL I DIV

(5) Basic Operation
(a) In binary code division, quotient and residual are obtained by repeated
subtraction.

Fig. 3 shows example of division ($OD + $03).

®®
Divisor

1 1

)
-)

1
1

1

0

0

Quotient

1

0

1

Dividend

0

0

CD
®

1

1

---- @

0

1

---- ®

1

-)

+)

1

1

0

0

1

1

1

-1

0

1

1

0

1

-)

+)
0

<-

Residual

Fig. 3 Division example ($00+ $03)
(b) Using Fig. 3, the flowchart is explained as follows;
(i) IX is used to indicate number of shifts.
(ii) Clears work area (RSD: RSD+1) where residual will be stored.
(iii) Sets bit C in advance to store "1" in quotient RAM.
(iv) Rotates DVD:DVD+1 (dividend

~

quotient and RSD:RSD+1 left 1 bit,

sets "1" in quotient RAM and simultaneously shifts MSB of DVD:
DVD+1 to LSB of RSD:RSD+1.

This is because when performing subtrac-

tion, the upper bits are fetched one by one from dividend.
(v) Subtracts divisor, DVS:DVS+1 from RSD:RSD+1.

If subtraction result

is positive, sets LSB of DVD:DVD+l to "1".
(Fig. 3

CD~®-®)

If subtraction result is negative, adds divisor to subtraction result
and clears "1" set in quotient RAM.
(Fig. 3

@ ~® -+@)

(vi) Decrements shift counter.
(vii) Loops (iii) to (vi) until shift counter is "0".

~HITACHI
516

15.

DIVIDING l6-BIT BINARY DATA

HD6305 FAMILY

K:U/MPU

DIV

FLOWCHART

____ { Loads number of shifts into shift
counter.
Clears work area where division result
----{ will be stored.
____ {

Sets bit C to store "i" in quotient RAM.

Shifts MSB of dividend to LSB of work
---- { area.

----~ Subtracts
____ {

divisor from work area.

Tes~s. if subtract~on

result is

posItIve or negatIve.

(RSD: RSDtl)
RETURNS
DVD
*
*
(RESIDUAL>
RSD
*
*
*
*
************************************************
*
$80
ORG
*DVD
Dividend -) Quotient
RMB
2
DVS
RSD

*
*
DIV
DIVl

DIV2

RMB
RMB

2
2

ORG

$1000

EQU
LOX
CLR
CLR
SEC
ROL
ROLROL
ROL
LOA
SUB
STA
LOA
SBC
STA
BCC
LOA
ADD
STA
LOA
AOC
STA
DEC
DEC
BNE
RTS

*IU6

RSD
RSD+l

DVD+l
DVD
RSD+l
RSD
RSD+l
DVS+l
RSD+1
RSD
DVS
RSD
DIV2
DVS+1
RSD+l
RSD+1
DVS
RSD

Divisor
Residual

Entr:- point
Set shift counter
CLellr worK (set Quotient afterwlI'd)
Set LSB of residuaL aree to high
Shift dividend lind set MSB -of dividend to LSB of worK
Work - divisor

->

WorK

Brench If worK ) divisor
WorK + Divisor -) Work

RSD

DVD+1
X
OIV1

CLeer LSB of residual area
Decrement shift counter
Loop until shift counter = 0

~HITACHI
518

HD630S FAMILY

16.

ADDING 8-DIGIT BCD

I

MCU/MPU

HD630S FAMILY

I LABEL I ADDD

1

FUNCTION

(a) Performs addition of 8-digit BCD in RAM, and stores result in 8-digit BCD in
RAM.
(b) Utilizes unsigned integers in arguments.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

•
Storage
Location

Contents

: Not affected

x :

Undefined

1:

Result

Byte
Lgth.

SPEC IF ICATIONS
ROM (Bytes)
14
RAM (Bytes)
8

Augend

ABD
(RAM)

4

Entry
Addend
Arguments
Addition
results
Returns Carry or
no carry

ACD
(RAM)

4

ABD
(RAM)

4

bit C
(CCR)

1

I

ACCA
x

I

IX
x

C

Z

!

x

N

I

x

H

•

x

I

Stack (Bytes)
0

No. of cycles
84
Reentrant
No
Relocation
No
Interrupt
Yes

DESCRIPTIONS

I

(1) Function Details
(a) Argument details
ABD (RAM): Holds 8-digit BCD augend.

After ADDD execution, Contains

addition result.
ACD (RAM) : Holds 8-digit BCD added.
Bit C (CCR) : Indicates whether a carry is generated or not after ADDD
execution.
Bit C=l: Carry is generated in addition result.
Bit C=O: No carry is generated in addition result.
(See Fig. 2)

SPECIFICATIONS NOTESf

~HITACHI
519

I

ADDING 8-DIGIT BCD

16.

I

DESCRIPTION

I

!£U/MPU

HD630S FAMILY

(b) Fig. 1 shows example of ADDD execution.
If entry arguments are as shown in

I

part I&ACDI&

b•• C b31

upper digits, hold "0" in the upper
digits. If "0" is not held, addition

ADDD

AIIIl AJIDI-I AIIDI-IAIIDI-I

ACD(IIAM)
(7800Il001)

®Re.ur. {AI1D(RAN)
arauaenta (8M88983)

I

II : 11-: ,I. : 0 I': .1 .... Aug.nd

(Is.......)

(2) User Notes
(a) As shown in Fig. 3, when not using

LABEL

b31

AIIIl(1IAM)

are contained in ABD (RAM) as shown in ®!~~nt.
part ® of Fig. 1.

I

bO

EJ 1-: .1-: .1.:
.1.: al ....Melitio•
ABDttABDt3 result
ADD

AJlDt.I

Fig. 1 Example of ADDD
execution

is performed with undefined data in
the upper digits, and correct result
cannot be obtained.
(b) After ADDD execution, augend is
destroyed because addition result

+)

Iv: 01.: .1.: 0II: 0I-Augend
11:·lo:aIO:olo:ol-Addend

Ii:

are contained in ABD (RAM). If augend

bit clll
01< 01.: 011: oI-Addition
result
C~
arry .

Fig. 2 Addition example when
carryi s generated

needs to be ratained after ADDD
execution, it should be saved in
memory before execution.
(c) Hold BCD data as augend and addend.
If data other than in BCD from is

+)

10: 0 10: 0 II : Z \8 : • I-Augend
10: 0 10: 0 I. : 810 : 6 I-Addend

bit c010: 0 \0: 0\3: 6\ g: v I-Addition
result

held, correct addition result

Fig. 3 Addition example when upper
digit is not used

·cannot be obtained.
(3) RAM Description

Description

RAM

Label

bO

b7
ABD

-

Upper byte

r--

-

Lower

~yte

Upper byte

ACD

r-...,-

-

Lower byte

•
520

-

8-digit BCD augend is stored before
execution.

-

8-digit BCD addition result is
stored after execution.

-

8-digit BCD addend is stored.

HITACHI

16.

ADDING 8-DIGIT BCD

MCU/MPU

J

DESCRIPTION

I

HD6305 FAMILY

I

LABEL

I

ADDD

(4) Sample Application
ADDD subroutine is called after augend and addend are held.
WORKl

RMB

4

Reserves memory byte for 8-digit BCD
augend.

WORK 2

RMB

4

WORK 3

RMB

4

Reserves memory byte for 8-digit BCD
addend.
Reserves memory byte for addition result.

WORK 4

RMB

2

Reserves memory byte for register contents
saving.

STA
STX

WORK 4 }
WORK4+l
WORKl
ABD
WORK+l
ABD+l
WORK1+2
ABD+2
WORK1+3
ABD+3
WORK2
ACD
WORK2+1
ACD+I
WORK2+2
ACD+2
WORK2+3
ACD+3

Saves register contents that will be
destroyed by executing ADDD.

LDA

STA
LDA

STA
LDA
STA
LDA

STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA
JSR

OVER

I

II

Stores 8-digit BCD added into entry
argument (ABD).

stores 8-digit BCD addend into entry
argument (ACD).

Calls ADDD subroutine.

BCS

ADDD
OVER

LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
LDX

ABD
WORK3
ABD+I
WORK3+1
ABD+2
WORK3+2
ABD+3
WORK3+3
WORK4 }
WORK4+1

If there is carry in addition result,
branches to service carry routine.

Service routine in case
of carry

Stores addition result (return argument
(ABD» in RAM.

Restores register.

I

~HITACHI
521

16.

ADDING 8-DIGIT BCD

DESCRIPTION

! MCU/MPU!

HD6305 FAMILY

! LABEL! ADDD

I

(5) Basic Operation
(a) When more than 2 bytes are added, perform addition for each byte.
(b) IX is used to indicate augend and addend addresses and is also used to count
number of addition.
(c) Clears bit C at first.
(d) Performs (Formula 1) on each byte of augend and addend using index addressing rode.
Augend + Addend + (bit C)

-

ACCA

------- (Formula 1)

Bit C is added in (Formula 1) because addition result of lower bytes
generate carry.
(e) Adjusts addition result of (d) to decimal value using decimal adjust
(instruction DAA), and stores it in augend RAM (ABD).
(f) Decrements IX each time (d) and (e) are executed.
(g) Loops (c) to (f) until IX is "0".

~HITACHI
522

16.

ADDING 8-DIGIT BCD

MCU/MPU

HD630S FAMILY

ADDD

FLOWCHART

---{
---{

Loads "4" in pointer indicating augend
address and counter indicating number of
addition.
Clears bit C for carry operation.

Adds addend and bit C to augend.
L---...r------' - - - {

---{

Adjusts addition result to decimal.
Stores decimal-adjusted result in augend

L----r-------' ---{ RAM.

---{

Decrements pointer indicating augend address
and counter indicating number of addition.

---{

Tests if addition in all the digits is
completed or not.

~HITACHI
523

16.

I ~ICU/NPU I

ADDING 8-DIGIT BCD

I

HD630S FAHILY

LABEL

I

I

PROGRAH LISTING
OCl:..""'0l
0000':0:..1 003
..."I0\."'lJ ...
(\.""1\":05

,.

0000",

0000,
00008
0000 0
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
000:5
00026
00027
00028
00029
00030

524

"'
..'"

ENTRY

ABD
ACD
ABD
CARRY

RETURNS

(AUGEND)
(ADDEND)
(SUM)
(C=O;TRUE.C=l;OVER FLOW)

,.
"'
"'
,."'
,.

"'
"'**~***********************~*********************
,.
0080

,.

ORG

$80

0080 0004
0084 0004

ABD
ACD

RMB
RMB

'4"

1000

,.

ORG

$1000

ADDD

EQU
LDX
CLC

1i4

1000
1002
1003
1005
1007
1008
100A
100B
1000

1000
AE 04
98
E6 7F
E9 83
8D
E7 7F
SA
26 F6
8.1

,.

ACDDl

LDA

ADC
DAA
STA
DEC
9NE
RTS

'"

ABD-l.X
ACD-l. X
ABD-l.X

"

ADDDl

Augend
Addend

-)

Sum

EnTry point
Set ADDR pointer (addition counter)
CLear car~y
Augend .. addend
Convert i'11:0 BCD
Store In augend are/!
Decrement ADDR pointer
Loop until AD DR pOinter

~HITACHI

0

ADDD

17.

SUBTRACTING 8-DIGIT BCD

MCU/MPU

I

HD6305 FAMILY

I

LABEL

I

SUBD

I

FUNCTION

(a) Performs subtraction of 8-digit BCD in RAM and stores result in 8-digit BCD
in RAM.
(b) Utilizes unsigned integers in arguments.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS
Not affected

e:

Undefined

x :

Storage
Byte
Location Lgth.

Contents
Minuend

SUBEDS
(RAM)

4

Entry
Subtrahend

Arguments
Returns

Subtraction
result
Borrow
or no
borrow

DESCRIPTION

SUBERS
(RAM)
SUBEDS
(RAM)

4

4

1

I

: Result

ACCA

IX

I I

1

ROM (Bytes)
25
RAM (Bytes)
8
Stack (Bytes)

x

0
No. of cycles

C

Z

146
Reentrant

x

1

x

N

I

x

e

H
bit C
(CCR)

SPECIFICATIONS

x

No
Relocation
No
Interrupt
Yes

I

(1) Function Details
(a) Argument details
SUBEDS (RAM) : Holds 8-digit BCD minuend. After SUBD execution. Contains
subtraction result.
SUBERS (RAM): Holds 8-digit BCD Subtrahend.
Bit C (CCR) : Indicates whether borrow is generated or not after SUBD
execution.
Bit C--o: Borrow is generated in subtraction result.
Bit C=l: No borrow is generated in subtraction result.
(See Fig. 2)

SPECIFICATIONS NOTEsl

525

I

SUBTRACTING 8-DIGIT BCD

17.

MCU/MPU

I

HD6305 FAMILY

1 1
LABEL

SUBD

I

DESCRIPTION

(b) Fig. 1 shows example of executing
SUBD.

Sl'REnS( RAM)

If entry arguments are as

shown in part

CD of

CD!~~~ents1

(P012:H56)

Fig. 1, subtrac-

SI lIl'RS ( RA.\I)
(

tion result is stored in SUBEDS
(RAM) as shown in part

® of

12:H·56j~)

I ~,:"21. ~,:".I',,:.I,:,:,,.I-subtrahend

-)

Fig. 1.

(2) User Notes

(a)

As

shown in Fig. 3, when not using

Fig. 1 Example of SUBD
execution

upper digits, hold "0" in the upper
digits.

If "0" is not held, sub-

II : 2 Is : + 15 : 61

traction is performed with undefined

7: 8

I. . .Minuend

data held in the upper digits, and
)

correct result cannot be obtained.
bit

(b) After SUBD execution, minuend is

cIT] 1<21 <212: 21 <21<-Subtractiol1
result

destroyed because subtraction

Fi g. 2 Subtraction example when
borrow is generated

result is contained in SUBEDS (RAM).
If minuend needs to be retained
after SUBD execution, it should be
saved in memory before execution.
(c) Hold BCD data as minuend and subtrahend.

If data other than BCD is held,

correct subtraction result cannot be
obtained.

)

bit CQ] 1 0 : 0 10: 01 5 : 51 2: q"'Subtraction
result

Fig. 3 Subtraction example when
upper digit is not used

(3) RAM Descri.Ption
Label

Description

RAM

bO

b7

Upper byte

SUBEOS

ttt-

Lower byte
Upper byte

SUBERS
f--

-

526

Lower byte

-

-

8-digit BCD minuend is stored
before execution.
8-digit BCD subtraction result
is stored after execution.

8-digit BCD subtrahend is stored.

~HITACHI

17.

SUBTRACTING 8-DIGIT BCD

MCU/MPU

I

HD6305 FAMILY

I

LABEL

I

SUBD

I

DESCRIPTION

(4) Sample Application
SUBD subroutine is called after minuend and subtrahend are held.
WORKl

RMB

4

----- Reserves memory byte for 8-digit BCD
minuend.

WORK 2

RMB

4

Reserves memory byte for 8-digit BCD
subtrahend.

WORK 3

RMB

4

Reserves memory byte for 8-digit BCD
subtraction result.

WORK 4

RMB

2

Reserves memory byte for register
contents saving.

STA
STX
LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA

WORK 4 } _____ Saves register contents that will be
WORK4+l
destroyed by executing SHR.
WORKl
SUBEDS
WORKl+l
Stores 8-digit BCD minuend into entry
SUBEDS+l
WORK 1+2
argument (SUBEDS).
SUBEDS+2
WORK 1+3
SUBEDS+3
WORK 2
SUBERS
WORK2+l
Stores 8-digit BCD subtrahend into entry
SUBERS+l
WORK 2+2
argument (SUBERS).
SUBERS+2
WORK2+3
SUBERS+3

JSR
BCC

SUBD
OVER

LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
LDX

SUBEDS
WORK3
SUBEDS+l
WORK3+l
Stores subtraction result (return argument
SUBEDS+2
(SUBEDS» in RAM.
WORK 3+2
SUBEDS+3
WORK 3+3
WORK 4 }
WORK4+1 ----- Restores register.

II

OVER

I

Service routine
in case of borrow

Calls SUBD subroutine.

II

If borrow is generated in subtraction
result. branches to service borrow routine.

I
~HITACHI
527

17.

SUBTRACTING 8-DIGIT BCD

I

DESCRIPTION

I

MCU/MPU

I

HD6305 FAMILY

I LABEL I SUBD

(5) Basic Operation
(a) Subtraction of BCD can be performed by (Formula 1) and (Formula 2).
Minuend-Subtrahend=Minuend+lO's complement of subtrahend .•.•. (Formula,}l)
10's complement of minuend=$99-Subtrahend+l

•••••••••••••••• (Formu1a 2)

(b) (Formula 1) and (Formula 2) are described as follows:
(i) Takes 10's complements of 8-digit subtrahend by (Formula 2) and stores
them in SUBERS (RAM).
(ii) IX is used to indicate minuend and subtrahend, and is also used to
count number of subtraction.
(iii) Performs (Formula 3) on every byte from LSB of 10's complement of minuend
and subtrahend using index addressing mode.
Minuend+lO's complement of subtrahend+(bit C) - ACCA ••• (Formula 3)
(iv) Adjusts subtraction result of (iii) to decilllel value using decimal
adjust(instructionDAA) and stores it in minuend RAM, (SUBERS).
(v) Decrements IX.
(vi) Loops (iii) to (iv) until IX is "0".

~HITACHI
528

17.

SUBTRACTING 8-DIGIT BCD

HD6305 FAMILY

MCU/MPU

SUBD

FLOWCHART

Takes 10's complement of subtrahend, and
stores it in subtrahend RAM.
However, only ($99-subtrahend) is
calculated in this part. Adds "1" in the
next step by setting bit C. (See Formula 2
in "(5) Basic Operation")

--- {

Loads "4" in pointer indicating minuend
address and counter indicating number
of subtraction.

--- {

Adds 10's complement of subtrahend and
bit C to minuend.

---1L Adjusts

addition result

to decimal.

___ { Stores decimal adjusted result in
minuend RAM.
Decremen~s pointer indicating minuend
address and counter indicating number of
subtraction.

--- {

___ ~ :ests if subtraction in all the digits
~s completed or not.

l

~HITACHI
529

17.

I

PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036

530

I

SUBTRACTING 8-DIGIT BCD

MCU/MPU

I

1 J

HD6305 FAMILY

LABEL

SUBD

***~********************************************

'"
'"

NAME : SUBTRACTING 8-DIGIT BCD

(SUBD)

,.
'"
>t

'"

************************************************

0080

'"
'"
'"
RETURNS
'"
',."
'"
'"
'"
************************************************
'"
$80
ORG

0080 0004
0084 0004

SUBEDS RM8
SUBERS RM8

',."

1000
1000
1002
1004
1006
1008
1009
1008
100C
100E
1010
1012
1013
1015
1016
1018

1000
AE 04
A6 99
EO 83
E7 83
SA
26 F7
99
AE 04
E6 7F
E9 83
80
E7 7F
SA
26 F6
81

ENTRY

'"

,.
,.

SU8D
SUBD:

SU8D2

SUBEDS
SUBERS
SU8EDS
CARRY

4
4

(MINUEND)
(SUBTRAHEND)
(RESIDUAl)
(C=l;TRUE.C=O;BORROW)

'"

Minuend -) ResiduaL
Subtr~hend

ORG

$1000

EOU
LOX
LOA
SUB
STA
DEC
BNE
SEC
LOX
LOA
ADe
DAA
STA
DEC
BNE
RTS

Entry point
Set subtr~ction counter
~$99
9999999 0 -Subtraend
SUBERS-1.X -) SUBERS
SU8ERS-l.X
X
SUBD1
Set carry bit
Set AD DR pointer(subtraction counter)
114
SUBEDS-1.X Minuend + negative of subtr~henc!
SUBERS-1.X
Convert into 8CD
SUBEDS-l.X Store in minuend area
Decrement ADDR pointer
X
Loop untiL AD DR pointer = 0
SUBD2

'jj4
"

~HITACHI

18.

l6-BIT SQUARE ROOT

MCU/MPU

1

I

HD630S FAMILY

I

FUNCTION

LABELl SQRT

(a) Obtains square root of l6-bit binary data in RAM and stores result in RAM.
(b) Utilizes unsigned integers in argument.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

.:

SPEC IFICATIONS
ROM (Bytes)

Not affected

x : Undefined

Contents

Entry

1

Storage
Byte
Location Lgth.

Data
to be
squared

SQRD
(RAM)

2

6

I

ACCA
x

Arguments
ReSquare
turns root

SANS+l
(RAM)

71
RAM (Bytes)

Result

:

I

x

C

Z

x

x

N

I

Stack (Bytes)

I

0
No. of cycles
861
Reentrant
No

•

x

1

IX

H

Relocation
No
Interrupt

x

Yes
DESCRIPTION

I

(1) Function Details
(a) Argument details
SQRD : Holds l6-bit binary data to
(RAM)
be squared.

CD Entry
{ S~RD~RAM) I
argument ( E3 0)

SANS-+l: Contains l6-bit binary square
(RAM)
root.

® Return

(b) Fig. 1 shows example of SQRT execution.

{SANS+l(RAM)
argument (SFl)

I

bO

blS
E :

3

SQRD

b7

I

E
I SQRD+l
I
:

0

1 bO

F :

1

I

SANS+!

If entry argument is as

shown in part CD of Fig. 1, square
contained in SANS+l (RAM) as shown in

Fi g. 1 Example of SQRT
execution

part ® of Fig. 1-

SPECIFICATIONS NOTES

I

"No. of cycles" represents the number of cycles needed to get square root of
$FFFF.

~HITACHI
531

18.

I

l6-BIT SQUARE ROOT

MCU/MPU

I

TLABEL I SQRT

HD6305 FAMILY

I

DESCRIPTION
(2) User Notes

(a) When not using upper byte as shown

0

in Fig. 2, holds "0" in the upper byte.

:

0

I

I

:

0

1

If "0" is not held, square root is
0

obtained with undefined data Held in
the upper byte, and correct result

:

4

Fig. 2 Example when not upper
bytes are not used

cannot be obtained.
(b) Values to the right of the binary
point are truncated.
(3) RAM Description

Description

RAM

Label

bO

b7
SQRD

SANS
(SANS+! )

-

Upper byte
Lower byte
Upper byte
Lower byte
Upper byte

SWORK
~

Lower byte

-

}
}
}

l6-bit binary data is stored.

Work area is reserved to store square
root before execution.
8-bit binary square root is stored in
SANS+l, and "0" is stored in SANS
after execution.
Work area is reserved to operate on
upper 2 bits of data to be squared.

~HITACHI
532

18.

1

16-BIT SQUARE ROOT

I

DESCRIPTION

M::U/MPU

I

HD6305 FAMILY

I I
LABEL

SQRT

(4) Sample Application
SQRT subroutine is called after data to be squared is held.
WORKl

RMB

2

Reserves memory byte for binary
data to be squared.

WORK 2

RMB

1

Reserves memory byte for 16-bit binary
square root.

WORK 3

RMB

2

Reserves memory byte for register contents
saving.

STA
STX

WORK 3 }
WORK3+l

Saves register contents that will be
destroyed by SQRT execution.

LDA

:~::+l

Stores data to be squared into entry

STA
LDA
STA

}

SQRT ~

Calls SQRT subroutine.

}-----

LDA

SANS+1

STA

WORK2

LDA

WORK3 }
WORK3+1

LDX

argument (SQRD).

SQRD+1

Stores 16-bit binary square root (return
argument (SANS+l» in RAM.

Restores register.

~HITACHI
533

18.

I

l6-BIT SQUARE ROOT

I

DESCRIPTION

r«:U/MPU

I

I

HD6305 FAMILY

LABEL

I

SQRT

(5) Basic Operation
(a) Fig. 3 shows calculation to obtain square root of l6-bit binary data. $05 of
hexadecimal $22 data to be squared.

@®©
1
1

1

1

I

1 1

1
1

0

1

I
1

(i) .••.•.••.

1

Square root

1

__ ~lJ___________ ::Y'_~_O_J_~_o_l_~~ __ ~ ......... Data to be
11

1

1

I

1

_________

010:

1
1

I

1

1

@

:

@

I

1 0

0

squared

---r~----------------~---~-------

:0:

I

_______

0i
100 I

®

1
10
®
---I~----------------4----T-----1 :1
1 1 0 1 01
®
10 1 0 1 1

1

1

--------

01110

I

1

I

1

:

101

•

I

01

@

Fig. 3 Calculating a square root
(b) The calculation in Fig. 3, is explained as follows:
(i) Clears square root area. SANS:SANS+l and work area SWORK:SWORK+l.
(ii) Rotates SQRD:SQRD+l and SWORK:SWORK+l 2 bits left to fetch upper 2 bits
of :data to be squared, and sets upper 2 bits of data to be squared in
SWORK:SWORK+1. (Fig. 3 @- ®)
(iii) Sets "1" in 2-byte area. SANS:'SANS+l from RAM address shown in SANS.

(Fig. 3@-®)
(iv) Subtracts SANS:SANS+l from SWORK:SWORK+l, and stores result in
(Fig. 3@-®. ®. @)
(v) When result is positive, increments SANS+l.
SWORK: SWORK+1.

(Fig. 3@- @)

When result is negative, decrements SANS+l, and adds SANS:
SANS+l to SWORK:SWORK+l.
(Fig. 3 @ • ® - ®)
(c) In SQRT, loops (ii) to (v) 8 times and then shifts SANS:SANS+l 1 bit.
right to halve SANS: SANS+1.

(Fig. 3@. @- @is square root).

~HITACHI
534

18.

l6-BIT SQUARE ROOT

HD6305 FAMILY

K:U/MPU

SQRT

FLOWCHART

number of shifts into shift
----( Loads
counter.
O---SWORK:SWORK+l

---{

Clears RAM used to obtain square
root (solution).

Stores upper 2 bits of data to be
squared in lower 2 bits of work area.

1

---

bit C

Sets "1" in solution.

~otate

(SANS:SANS+l)
, bit left
Subtracts solution from work area.

---{
---{

---{
---{

---{

Tests if subtraction result
is positive or negative.
Adds solution to subtraction result
to return to the state before subtraction.
Clears "1" set in solution.
Increments solution.

Decrements shift counter.
Tests if shift is completed or
not.
Shifts solution to right to halve
SANS:SANS+l.

~HITACHI
535

18.

I

16-BIT SQUARE ROOT

PROGRAM LISTING
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
,00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057

I

MCU/MPU

1

I·LABEL

1

************************************************

*
*
NAME : 16-6IT S~UARE ROOT (SORT)
*
*
*
*
************************************************
,.
*
ENTRY : SORD (16-6IT BINARY DATA) *
*
RETURNS : SANS (SOUARE ROOT)
,.*
,.*
************************************************

*

0080
0080 0002
0082 0002
0084 0002

*
SORD

SANS
SWORK

,.

1000
1000
1002
1004
1006
1008
100A
100C
100E
1010
1012
1014
1016
1018
lOlA
1016
1010
101F
1021
1023
1025
1027
1029
1026
1020
102F
1030'
1032
1034
1036
1037
1039
1036
1030
103F
1041
1043
1045

1000
AE 08
3F 84
3F 85
3F 82
3F 83
39 81
39 80
39 85
39 84
39 81
39 80
39 85
39 84
99
39 83
39 82
66 85
60 83
67 85
66 84
62 82
67 84
25 OA
3C 83
SA
26 08
37 82
36 83
81
66 85
66 83
67 85
66 64
69 62
B7 64
3A 83
20 E8

*
SORT

SORTI

SORT2

SORT3

ORG

S80

RM6
RM6
RM6

2
2
2

ORG

S100.0

EOU
LOX
CLR
CLR
CLR
CLR
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
SEC
ROL
ROL
LOA
SU6
STA
LOA
SBC
STA
BCS
INC
DEC
EiNE
ASR
ROR
RTS
LOA
ADD
STA
LOA
ADC
STA
DEC
BRA

*

118

SWORI<
SWORi<+l
SANS
SANS+1
SORD+I
SORD
SWORK+I
SWORK
SORO+I
SQRD
SWORK+l
SWORK
SANS+l
SANS
SWORK+1
SANS+l
SWORK+I
SWORK
SANS
SWORK
SORT3
SANS+I
X

SORTl
SANS
SANS+l
SWORK+1
SANS+I
SWORK+l
SWORK
SANS
SWORK
SANS+1
SORT2

Input 16-bit binery dete
SQuere rpot
Work erea

Entry point
Set shift counter
Cleer Work aree
Cleer SQuere root aree
Shift upper 2 bits of SORO eree
-and set lower 2 bits of swork

Set LSB of SANS aree
Swork - SANS -) Swork

6rench if minus
SANS + 1 -) SANS
Decrement shift counter
Loop until shift counter
Helve SANS:SANS+1
Add !lsein

SANS -1 -) SANS
Branch SO'H2

~HITACHI
536

HD6305 FAMILY

=0

SQRT

19.

CONVERTING 2-BYTE HEXADECIMALS INTO s-DIGIT BCD

I

MCU/MPU

I LABELl

HD630s FAMILY

HEX

I

FUNCTION

(a) Converts 2-byte hexadecimals data in RAM into s-digit BCD data and stores
result in RAM.
(b) Utilizes unsigned integers in argument.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

•

SPECIFICATIONS

: Not affected

ROM (Bytes)

x : Undefined

Storage
Location

Contents

Byte
Lgth.

1:

31

Result

RAM (Bytes)
6

Entry

2-byte
hexadecimal

HEXD
(RAM)

2

I

Arguments

ACCA
x

DECD

3

(RAM)

x

C

Z

x

x

N

I

x

ReS-figure
turns BCD

I

H

Stack (Bytes)

IX

I

0
No. of cycles
1257
Reentrant

•

No
Relocation
No
Interrupt

x

Yes
DESCRIPTION

I

(1) Function Details
(a) Argument details
HEXD : Holds 2-byte hexadecimals to
(RAM) be converted into BCD.
DECD : Contains s-gidit BCD.
(RAM)

CD argument
Entry
{IIEXIJ( RA.'d)
(SCIJFE)

(b) Fig. 1 shows example of HEX execution.

bls

I

bO

I : I : I
C
D
HEXD

b19

I 0.: I

F
E
IIEXD+l

1

I

bO

I

@ Return {1J ~ ~A~\J
5
2 : 7
3 : +
Fig. I, s-digit BCD, in this case
argument (527H) DECD IJECD+I DECD+2
"52734" is held in DECD (RAM) (see part
@of Fig. 1).
Fig. 1 Example of HEX EXECUTION
If argument is as shown in part

CD of

(2) User Notes
"0" is held as MSD (105) of return
argument.
SPECIFICATIONS NOTES

I
~HITACHI
537

19.

CONVERTING 2-BYTE HEXADECIMALS INTO 5-DIGIT BCD
DESCRIPTION

I

MCU/MPU

1

HD6305 FAMILY

1 J
LABEL

HEX

I

(3) RAM Description
Label

RAM

HEXD

Description

bO

b7
Upper byte
~

Lower byte
Upper byte

DECD
~

f--

Lower byte
HCNTR

(4) Sample Application
HEX subroutine is called after 2-byte hexadecima1s is held.
WORlU

RMB

2

WORK 2

RMB

3

WORK 3

RMB

2

STA
STX

WORK 3
WORK3+l

LOA

STA
LOA

STA
JSR
LOA
STA
LOA
STA
LOA
STA
LOA
LOX

Reserves memory byte for 2-byte
hexadecima1s.
Reserves memory byte for 5-digit BCD.
Reserves memory byte for register contents
saving.

1

WORK 1 }
HEXD
WORK 1+1
HEXD+I
HEX II
DECO
WORK 2
DECD+I
WORK2+l
DECD+2
WORK2+2
WORK 3 } ___ ...;_
WORK3+l

Saves register contents that will be
destroyed by HEX execution.
Stores 2-byte hexadecima1s into entry
argument (HEX).
Calls HEX subroutine.

Stores 5-digit BCD (return argument (DECO»
in RAM.

Restores register.

~HITACHI
538

19.

I

CONVERTING 2-BYTE HEXADECIMALS INTO 5-DIGIT BCD

MCU/MPU

I

HD6305 FAMILY

I LABEL I HEX

I

DESCRIPTION

(5) Basic Operation
(a) 4-bit binary (ABCD) construction is shown in Fig. 2 (Formula I, Formula 2).

ABC D = A x II· + B x II • + C x 2 1 + D x 2'

............ (Fo rmu la 1)

=rHAXll)+B'X2+C~X2+D
1

I

I

I

I'
I I
I I
I I

I

,

I
I
I

I

ct

......... (Formula 2)

I
I

I

I
I

,
T

Fig. 2 4-bit binary (ABCD)
(b) 2-byte hexadecimals can be converted into 5-digit BCD by calculating
(Formula 2).
decimal.
fJ
T

First, calculate

a = (A x 2) + B, and adjust result into

Next, the same calculation is done for

'" (a x 2) + C, and
(fJx 2) + D, both of which are adjusted into decimals.

(c) HEX uses HEXD and DECD (RAM) for a = (A x 2) + B
(i) Shifts 2-byte hexadecimals (HEXD) 1 bit left and rotates MSB to bit C.
(ii) Loads 5-digit BCD (DECD) into ACCA and calculates (ACCA) + (DECD) +
(bit C) ..... (ACCA), where

a

= (A ~: 2) + B is executed.

(iii) Adjusts result into decimal and stores them in DECD.
(iv) Loops (i) to (iii) sixteen times to convert 2-byte hexadecimals into

I

5-digit BCD.

•

HITACHI
539

---------------------------

19.

CONVERTING 2-BYTE HEXADECIMALS INTO 5-DIGIT BCD
FLOWCHART

MCU/MPU

~,....-------' ---{

.----======:;t-~ ---{

~---{
~----'---{

HD6305

FAMILY

Clears RAM where BCD is stored •

Stores number of shifts in loop counter.

Shifts and rotates 2-byte hexadecimals and
sets MSB of 2-byte hexadecimals to bit C.

Loads "3" into IX.
counter.

IX is inner loop

~-~

Doubles RAM where BCD is stored and
adds MSB of hexadecimal to result.

~---{

Adjusts result into decimal and stores
them in RAM where BCD is stored.

Decrements inner loop counter.
' - - - - r - - - - ' ---{

---{
'----.---------I - - - {

----C

Tests if all RAM where BCD is
stored, are converted or not.
Decrements loop counter.
Tests if shifts are completed or
not.

~HITACHI
540

HEX

19.

CONVERTING 2-BYTE HEXADECIMALS INTO S-DIGIT BCD
PROGRAM LISTINGT
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038

1

MCU/MPU

J

HD630S FAMILY

ILABEL I HEX
..
,.
.

************************************************

,.
,.
,.

,.

NAME : CONVERTING 2-BYTE HEXADECIMALS
INTO S-DIGIT BCD
(HEX)

..************************************************,.
..
,.

ENTRY : HEXD (2-BYTE HEXADECIMALS)

,.

RETURNS : DECO (S-DIGIT BCD)
,.
,.
,.
***********************~************************
,.
0080
0080 0002
0082 0003
0085 0001
1000
1000
1002
1004
1006
1008
100A
100C
100E
1010
1012
1014
1015
1017
101B
lOlA
101C
101E

1000
3F 82
3F 83
3F 84
A6 10
B7 85
3B B1
39 80
AE 03
E6 Bl
E9 B1
8D
E7 B1
SA
26 F6
3A BS
26 EC
81

..

HEXD
DECO
HCNTR

.
.

HEX

HEXl
HEX2

ORG

S80

RMB
RMB
RMB

2
3
1

ORG
EQU
CLR
CLR
CLR
LOA
STA
ASL
ROL
LDX
LOA
ADC
DAA
STA
DEC
BNE
DEC
BNE
RTS

2-byte hexedeclmeLs
S-dlglt BCD
Subtrectlon counter

S1000

,.
DECO
DECD+1
DECD+2
IH6

HCNTR
HEXD+1
HEXD

Entry point
CLeer S-dlglt BCD eree
Set shift counter
Shift MSB of HEXD to cerry

Set ADDR pointer (eddltlon counter)
DECD-l. X DECO .. 2 + C -> ACCA
DECD-1. X
Convert Into BCD
DECD-l.X Store S-dlglt BCD ereB
Decrement ADDR pointer
X
Loop untiL ADDR pointer = 0
HEX2
Decrement shift counter
HCNTR
Loop untiL shift counter = 0
HEX1

113

~HITACHI
541

20.

CONVERTING 5-DIGIT BCD INTO
2-BYTE HEXADECIMALS

FUNCTION

I

MCU/MPU

I LABEL I .BCD

HD6305 FAMILY

I

(a) Converts 5-digit BCD data in RAM into 2-byte hexadecimals and stores result
in RAM.
(b) Utilizes unsigned integers in argument.
ARGUMENTS

----..---..CHANGES IN CPU
REGISTERS AND FLAGS

I

e:

Not affected

x:

Byte
Lgth.

Storage
Location

Contents

.-

SPEC IFICATIONS
ROM (Bytes)

Undefined

70

Result

RAM (Bytes)

!:

8

Entry

5-digit
decimals

DEC
(RAM)

3

I

Arguments
Returns

2-byte
hexadecimals

HDATA
(RAM)

2

ACCA
x

I

Stack (Bytes)

IX
x

I

0
No. of cycles

C

Z

440

x

x

Reentrant

N

I

x

e

No
Relocation
No
Interrupt

H
x

Yes
DESCRIPTION

I

(1) Function Details
(a) Argument details
DEC : Holds 5-digit BCD to be
(RAM) converted into hexadecimal.

RAM

b7

HDATA: Contains 2-byte hexadecimals.
(RAM)

1 Entry

I<

!lDEC
115

S-digit BCD
2-byte hexadecimaLs
Digit counter
WorK area

Entry point
Load BCD DATA ADDR
Set figure counter

BCNTR
CLear Hex area
HDATA
HDATA+l
0.BCNTR.BCD4 Branch if bitO = 0
O.X
!I$F
Set Lower 4 bits of BCD data
HDATA+l ACCA + HDATA+l -> HDATA+l
HDATA+l
A
CLear ACCA
ACCA(O> + HDATA + C-)HDATA
HDATA
HDATA
Decrement digit counter
BCNTR
Loop unTiL figure counter = 0
BCD5
O.X

Set upper 4 bits of BCD data

A
A

A
A

BCD2
Branch BCD2
0.BCNTR.BCD3 Branch if bitO = 1
X
Increment BCD data ADDR
HDATA+l HDATA:HDATA+l*2->BWDRK:BWORK+l
HDATA
HDATA
BWORK
HDATA+l
BWDRK+l
HDATA:HDATA+1>1<4-)HDATA:HDATA+l
A
HDATA
A

HDATA
BWORK+l
HDATA+1
BWORK
HDATA
HDATA
BCDI

HDATA+l + BWORK+1->HDATA+1
HDATA

+

BWORK + C

Branch BCDI

~HITACHI
548

I LABEL I

I

-l

HDATA

BCD

21.

SORTING

I

MCU/MPU

I

HD6305 FAMILY

I

FUNCTIONS

LABELl

SORT

(a) Sorts unsigned byte oriented data in RAM in descending order.
(b) Permits number of bytes to be sorted to be freely selected.
(c) Utilizes unsigned integers in arguments.
ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS

•

Storage
Byte
Location Lgth.

Contents

: Not affected

x :

Undefined

1:

Result

SPECIFICATIONS
ROM (Bytes)
36
RAM (Bytes)
10

No. of
bytes to
be sorted
Entry
Arguments

Starting
address
of data
to be
sorted

ACCA
ACCA

1

IX

1

I

x

-

I

0
No. of cycles

Z

474

x

x

Reentrant

N

I

No
Relocation

x

-

-

I

x

C

H

Returns

Stack (Bytes)

IX

x

•

No
Interrupt
Yes

DESCRIPTION

I

(1) Function Details
(a) Argument details
ACCA: Holds number of bytes to be sorted; (No. of bytes to be stored - 1)
I-byte hexadecimal.
IX

: Holds starting address of data in RAM to be sorted in 1-byte

hexadecimal.

SPECIFICATIONS NOTES

I

''No. of cycles" in "SPECIFICATIONS" represents the number of cycles needed to
sort 5-byte ascending data to descending.

~HITACHI
549

21.

HD6305 FAMILY

SORTING

SORT

DESCRIPTION
(b) Fig. 1 shows example of SORT execution.

b7

If entry arguments are as shown in part Q) of

ACCA($H)

ACCA

b7

Fig. 1, sorted data is stored from

I X

($90)

bO

10:. I

I

bO

IX
9

:

0

I

address $90 in descending order (see

Memory space
Q)Entry
Start
argument address·-+$9o
As data to be sorted is 5-byte, $04
of data
t----I
(Number of bytes to be sorted; ($05)-1)
to be
sorted(IX)
is held in ACCA.
part

® of

Fig. 1).

(2) User Notes

~

(a) When loading number of bytes to be
sorted, holds (No. of bytes to be sorted
- 1) to ACCA for effective loop processing.

(b) Stores data to be sorted in RAM

® Result

using direct addressing.

Sorted
data

Memory space

r

Fig. 1 Example of SORT execution
(3) RAM Description

Label

Description

RAM

b7

bO
IX (address pointer) is saved.

SWORKI

1--------1 }
SWORK2
SWORK3
SCNT 1

~--------Il

SCNT 2
L---_----I }

Work area is reserved to exchange data
during sorting operation.
Counter is stored which shows how many
bytes remain to be sorted.
Counter is stored which shows how many
bytes remain to be compared.

~HITACHI
550

21.

I

SORTING

K:U/MPU

I

HD6305

FAMILY

I

LABELl SORT

DESCRIPTION}
(4) Sample Application
SORT subroutine is called after start address and number of bytes to be sorted
are held.
WORKl

RMB

RMB

WORK 2

1

Reserves memory byte for number of

1

bytes to be sorted.
Reserves memory byte for start address
to be sorted.

LDA

WORKl

LDX

WORK 2

----- Loads number of bytes to be sorted into
entry argument (ACCA) •
----- Loads start address of data to be sorted
into entry argument (IX) •

~

JSR

Calls SORT subroutine.

SORT

"

I
~HITACHI
551

21.

I

SORTING

HD6305 FAMILY

K:U/MPU 1

I

LABEL

I

SORT

I

DESCRIPTION
(5) Basic Operation

(a) Fig. 2 shows how three byte values are sorted in descending order.

Input data 1
..__&_ _1_0_ _ _8_...1
First
comparison
times
(n-1=2)
Second
comparison
times
(n-2=1)

S---io
[

lO~~ __

-

10

&

...

Number of bytes
n=3

8

......•......•.

CD

8

...............

®

8

...............

@

10

............... ®

10

............... ®

[

(Note)
11'''-.....

shows comparison.

><

shows data exchange •

Fig. 2 Example of Sorting
(i) Finds

t~e

lareest value among three and puts it into left position.

(See Fig. 2 CD , ® and @ )
(ii) Compares middle and right values and puts larger one in middle.
(See Fig. 2 CD

, @ and ® )

(b) Program processing
(0 Uses IX as two pointers.
(ii) First, use IX as pointer showing memory address where data is stored.

(iii) Loads this data into ACCA to be compared.
(iv) Increments address where data is stored and compares new value with
value (indicated with using index addressing mode) in ACCA.
(v) If value is larger than compared value in ACCA (memory> ACCA),
exchange them.
(vi) Loop (iv) to (v) until counter SCNT2, showing number of remaining
bytes,_ reaches "0".
(vii) When SCNT2 reaches "0", the largest data is stored in ACCA.
(viii) Then use IX as pointer when storing the largest data.
(ix) Stores contents of ACCA in address IX points, and loads next address,
at which the next largest data is to be stored, into IX.
(x) Decrements counter SCNT1 showing how many bytes remain to be sorted.
(xi) Loops (iv) to (x) until SCNT1 is "0" •

•
552

HITACHI

21.

SORTING

MCU/MPU

HD6305 FAMILY

SORT

FLOWCHART

Stores number of bytes to be sorted in
---{ SCNTl.
___ { Stores number of bytes to be compared in
SCNT2.
___ { Saves start address of data to be sorted
in RAM.
---{ Loads first data to be sorted into ACCA.

---{ Increments address pointer.

ACCA with value of

Exchanges data in ACCA with that pointed
by IX.

---{ Decrements number of bytes to be compared.

(SeNTz),..- 0

{

Tests if all the comparisons are
completed or not.

Continued on
next page

~HITACHI
553

I

21.

SORTING

HD6305 FAMILY

MCU/MPU

SORT

FLOWCHART

----I

maximum data in RAM in descending
Stores
order.

____ [Increments address whose data is loaded to
ACCA.
____ {necrements number of bytes remaining
to be sorted.
____ {

Loads the number of bytes remaining
to be compared.

____{Tests if all the data is completed
or not.
Continued
previous page _ _-'-_ _

(RTS)

~HITACHI
554

21.

I

SORTING

PROGRAM LISTING

I

I I

HD6305 FAMILY

LABEL

SORT

I
,.************************************************,.

00001

00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045

MCU/MPU

,.
,.

NAME : SORTING (SORT)

,.

,.
************************************************
,.
,.
,.
,.
,.

ENTRY :-ACCA (VOLUME OF SORTING DATA)
,.
IX
(TOP ADDR OF SORTING DATAS)"
RETURNS: NOTING
,.

,.
,.
************************************************
,.
0080
0080
0081
0082
0083
0084

0001
0001
0001
0001
0001

1000
1000
1002
1004
1006
1007
1008
1009
100B
100D
100E
1010
1012
1013
1015
1017
1019
1018
101C

1000
87 83
87 84
BF 80
F6
5C
F1
24 OA
87 81
F6
87 82
B6 81
F7
B6 82
3A 84
2<5 EE
8E 80
F7

se

1010 3A 83

101" 86 83
10:?1 26 DF
1023 8:

,.

ORG

SWORK1
SWORK2
SWORK3
SCNTl
SCNT2

RMB
RMB
RMB
RMB
RMB

,.
,.

SORT
SORTl
SORT2

ORG
EQU
STA
STA
STX
LDA
INC
CMP

Bce

SORB

STA
LDA
STA
LDA
STA
LDA
DEC
BNE
LDX
ST ..
INC
DEC
LDA
8NE
RTS

S80
Work tor ADDR oolnter
Work for data exchange
Work. for data exchange
Counter for sortln9 data
Counter tor comoarlng date
$1000

,.
SCNTl
SCNT2
SWORI<1
O.X
X

O.X
SORB
SWORI<2
O.X
SWORI<3
SWORK2
O.X
SWORI<3
SCNT2
SORT2
SWORKl
O.X
X

SCNTl
SCNTl
SORT)

Entry poInt
Store counter tor sortIng data
Store counter tor comparIng data
Store sortln9 date ADDR
Load sortln9 data
Set next sortln9 DATA ADDR
Compere comparing DATA wIth sortin9 date
Branch it comparIng DATA> sortin9 data
Exchange each data

Load exchanged data
Decrement compare data counter
Loop untiL compare data counter=O
Load sorting data ADDR
Store ml!x data
Increment sortin9 data ADDR
Decrement sortin9 data counter
Load sortins data counter
Loop unt;l sorting data counter=O

~HITACHI
555

~HITACHI
556

HD63051HD63L05 SERIES HANDBOOK

Section Seven

Hardware

Application Notes

I
~HITACHI
557

~HITACHI
558

FOREWORD
The HD6305 is a series of CMOS 8-bit single chip microcomputers controlled by
microprogramming.

The CPU, clock generator, ROM, RAM, I/O, timer and serial

communication interface are all resident on the chip.

This series can be

applied to a wide variety of systems, both small and large.
APPLICATION NOTES are written to help users design hardware systems using
examples of typical application functions with specific circuit diagrams,
timing charts and program examples.
Application examples in APPLICATION NOTES used in actual systems should be
tested for proper operation.

NOTE
The following hardware application notes were prepared for HD6305X and HD6305Y devices.
The applications, however, are generic in nature and also apply to HD6305U, HD6305V, and
HD63L05 devices.

~HITACHI
559

Section 7
Hardware Application Notes
Table of Contents
Page
APPLICATION NOTES GUiDE........................................

563

1.

HOW TO USE APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

565

Application Example Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

565

1.2 1st Section (Hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

567

1.3 2nd Section (Software) .........................................

571

1.4 3rd Section (Program Module) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

573

1.1

1.4.1

Specification Format (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

574

1.4.2 Description Format (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

580

1.4.3

Flowchart Format (Format 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

582

1.5 4th Section (Subroutine) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

584

1.6 5th Section (Program Listing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

587

1.7 Program Module Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

591

1.8 Symbols.....................................................

594

APPLICATION EXAMPLES... ..... . .. ...... . . ............ ..... . .. . ...

597

110 PORT APPLICATIONS
1.

HD61830 (LM200) Graphic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

599

2.

Liquid Crystal Module (H2570) Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

623

TIMER APPLICATIONS
3.

Duty Control of Pulse Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

641

4.

Pulse Width Measurement ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

655

5.

Input Pulse Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

664

6.

Zero Cross. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

672

7.

Key Matrix (8 x 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

683

8.

Fluorescent Display Control ................................ . . . . . . .

697

9.

Stepping Motor Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

709

INTERRUPT APPLICATION
10.

With a Commercially Available Keyboard. . . . . . . . . . . . . . . . . . . . . . . . . . ..

~HITACHI
560

734

SCI APPLICATIONS
11.

SCI Clock Synchronous (External Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . ..

748

12.

SCI Clock Synchronous (Internal Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . ..

760

13.

Liquid Crystal Driver (HD61100A) Control. . . . . . . . . . . . . . . . . . . . . . . . . . ..

772

EXTERNAL EXPANSION APPLICATION
14.

External Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

784

LOW POWER DISSIPATION/FAIL SAFE APPLICATION
15.

Low Power Dissipation Mode and HA1835P Control . . . . . . . . . . . . . . . . . ..

$

816

HITACHI
561

•
562

HITACHI

APPLICATION NOTES GUIDE

•

HITACHI
563

~HITACHI
564

1.

HOW TO USE APPLICATION NOTES
This chapter describes the configuration for each system application
example following this chapter.

1.1

APPLICATION EXAMPLE CONFIGURATION

1

Each application example in APPLICATION NOTES is divided into 5
sections, as shown in Fig. 1.1.

r---- - -- - - - - - - - - - - - - - - - - - - 1st Section - - - -.....•..1 HARDWARE DESCRIPTION
(Hardware)
1
1
1
1
1

Function
Microcomputer
Applications
Circuit Diagram
Pin Functions
Hardware Operation

-1
I
1
1
I
1

1

~---------------------------~
r-----------------------~

2nd Section ------4·~1 SOFTWARE DESCRIPTION
(Software)

progra.m Module
1
Configuration
1
Program Module
Functions
I
Program Module Sample
1
______
_ _Program)
_ _ _ _ _ .1
•L _ _ _ _ _ _ _ _ _ _ _ _Application
(Main

r-----------------------,

3rd Section - - - - - - 4...1 PROGRAM MODULE
(Program Module)
DESCRIPTION

FUNCTION
,ARGUMENTS
CHARGES IN CPU
REGISTERS AND FLAGS
SPECIFICATIONS
DESCRIPTION
Function
Details
SPECIFICATIONS
User Notes
NOTES
RAM
Description
FLOWCHART
Sample
Application
B~sic

- - - - - -

Operation
- - - - - - - - - - - - - - _I

r-----------------------.

4th Section - - - -..........1 SUBROUTINE
(Subroutine)
•
DESCRIPTION

1

1

FUNCTION
BASIC OPERATION

:

n~~

I

1

~---------------------~

r------

5th Section - - - - - - 4.... PROGRAM LISTING
(Program Listing)
I
1

L __

Fig. 1.1

-

1
-

-

- -

- -

-

-

- - -

Main Program Listing
Program Module
Listing
Subroutine'Listing

- - --I
I

I

------------------

J

Application Example Configuration

~HITACHI
565

(1)

1st Section (Hardware)
Describes the function, circuit diagram or hardware operation of
the HD6305 hardware example.

(2)

2nd Section (Software)
Describes the program module to control the hardware example in
the 1st section and shows the main program when using all program
modules.

(3)

3rd Section (Program Module)
Describes the program modules presented in the 2nd section in
detail, using a modular format for more efficient system use.

(4)

4th Section (Subroutine)
Describes the subroutines used in the above program modules.
Refer to it necessary when you use program module.

(5)

5th Section (Program Listing)
Presents sample application program listing for the above
modules.

A detailed explanation of all five sections follows.

~HITACHI
566

1.2

1ST SECTION (HARDWARE)
(1)

Function
Describes system specifications for the hardware used in the
particular application.
Example:

(1)

Fune: t ion
(a)

Controls dot matrix liquid crystal controller driver
H044780 (hereinafter, LCD-II) using the 1ID6305XO and
displays in character mode on liquid crystal lIOdule H2570.

(b)

H2570 displays 5x7 dot characters in l-colUD\ x l6-row.

(c)

Transfers ASCII from the HD6305XO as display data to LCD-II.
LCD-II automatically controls liquid ~rystal driver
HD44100 and LCD by controlling LCD-II with the 1ID6305XO.

(2)

Microcomputer Applications
Describes the typical functions of the microcomputer utilized for
the particular application.
Example:

(2)

Microcomputer Applications
Displays characters on H2570 by controlling LCD-II data bus
(DBo '" DB,) and control signals (E, as and R!W)
through port G and port F.

~IiITACHI
567

(3)

Circuit Diagram
Shows the circuit diagram for the hardware specified above.
Note) All the microcomputers described in APPLICATION NOTES are used
Plastic DIP.
Example:

(3)

Circuit Diagram
Liquid crystal module
H2S70

MCU
+5V

r-----------------------

HD6305XO
(HD6305YO)

go

I

DB HI

DB~'"

DBiLCD-

G2

81,
DBS

gl
gi

DB6

~

G7

v..
VDD
o

Fig. 1

•
568

H2570 Control Circuit

HITACHI

(4)

Pin Functions
Describes pin functions for interfacing external circuits using a
table.
Example:

(4)

Pin Functions
Pin function. at the interface between the HD630SXO and LCD-II
are shown in Table 1.
Table 1

Pin Name
(HD630SXO)
FO
F1

Active
Input/
Level:..)
Output ~High
r Low
Output

Pin Functions

Function

High

Enable signal

Low

Selects instruction register

High

Selects data register

Output

Pin
Name
(LCDII)

Program
Label

E
RS
PFDTR

Low
F2

Output
High

Go
G1
G2
G3
G4
GS

G6
G7

(a)

Input!
Ou~put

Input!
Ou~ut

Input!
Output
Input!
Ou~put

Input!
Output
Input!
Output
Input {

Writes data
(Microcomputer + LCD-II)
Re~ds data
(MicrocomDuter + LCD-II)

-

Ou~l'ut

-

Input!
Output

-

R/W
DBo

f--DBl

f--DB.

t--DB,

Data lines

f---

PGDTR

DB.

f--DB.

t--DB.

t--DB?

"Active Level" in Table I indicates as follow;
High

Logical I

Low

Logical 0
Logical I or Logical 0

(b)

l:2:j

in "Program Label" in Table I means there is no program

label.

~HITACHI
569

(5)

Hardware Operation
Describes hardware operation required to control external circuits
showing tUning charts.
Example:

(S)

Hardware Operation
LCD-II control signals

(as, a/W,

E) are controlled by the

program. Each LCD-II control signal timing chart i. shown
in Fig. 2.
The HD630S family utilizes I/O port rather than buses to
control LCD-II to eliminate any timing restriction. on
LCD-II.
Pin name (LCD-II)

as, a/w

E

DBo"'DB 7
(HD630SXO+LCD-II)_ _ _ _ _ _ _ _ _ _ _ _J JIo.----''lf-J

DBo"'DB7
(HD630SXO+-LCD-II) _ _ _ _ _ _ _ _ _ _ _ _J

'1._ _ __

*1

Data is written to LCTC at the falling edge of E.

*2

Data from LCD-II can be read during period Tl.

Fig. 2

570

1'0----.1

" '_ _ __

HD6305XO ++ LCD-II Interface

_HITACHI

1.3

2ND SECTION (SOFTWARE)
(1)

Program Module Configuration
Describes the necessary program modules to control the hardware
specified in the 1ST SECTION.

Each module in the Program Module

Configuration figure has module No. (number of modules:
at the upper right.

1

~

N)

The module No. of the main program is '0'.

Example:

(1)

Program Module Configuration
The program module configuration for character display on
the liquid crystal module is shown in Fig. 3.

Fig. 3

(2)

Program Module Configuration

Program Module Functions
Explains functions of each program module presented in Program
Module Configuration.

"No." in the table matches module No. in

Program Module Configuration.
Example:
(2)

Program Module Functions
Program module functions are summarized in Table 2.
Table 2

No.

Program Module Name

Program Module Functions
Function

Label

0

MAIN PROGRAM

LCDMN

Demonstrates 'character display on H2570.

1

RESET LCD-II

LCDRES

Resets LCD-II using instruction.

2

INITIALIZE LCD-II

LCDINT

3

DISPLAY ON LCD

LCDDSP

In1.t1.all.zes LCD-II to display characters
on LCD.
Transfers ASCII code to LCD-II and
disJ1,J/!YJI on H2570.

~HITACHI
571

(3)

Program Module Sample Application (Main Program)
Explains a sample program (Main Program) in flowchart format using
program modules described in Program Module Configuration.
Example:

(3)

Program Module Sample Application (Main Program)
The flowchart in Fig. 4 is an example of character display on

H2570 performed by program module in Fig. 3.
The program in Fig. 4 demonstrates the display on liquid
crystal shown in Fig. 5.

Main Program

-----{ Clears pointer indicating display data.

~:::::

---of

r----1L~iiii~r:::=~

Selects port G as output.

{
_____{

;:=::::c=~ ----::=::::c=~

Ca1ls program module LCDRES and resets
LCD-II.

Ca1ls program module LCDINT and
initializes LCD-II.

~;;:;:;;;:;r;::;;;~ ----{ Loads
display data into IX using index
addressing modes.

a

Tests i f data in data table is terminator
r-''-'- of Fig. 7, ASCII is stored
in current address of DDRAM, and
characters are displayed on LCD.

I

SPECIFICATIONS NOTES

I

{IX. ASCII b7I 4 IX: 3bOI

(2) Resu1 t

Fig. 7

~

Liquid cryst.' display

IIIIIIIIIIIII
C

Example of LCDDSP
Execution

(1) "SPECIFICATIONS" includes subroutine LCDBSY.

(2) "No. of cycles" in "SPECIFICATIONS" represents the number of cycles required
when subroutine LCDBSY is executed by the minimum cycles.

~HITACHI
634

I

PROGRAM MODULE NAME
DESCRIPTION

II DISPLAY ON LCD
II MCU/MPU I HD6305XO/YO ILABEL IfCDDS1
I~============~====~~==~

(c) Program module LCDDSP calls subroutines shown in Table 5.
Table 5 Subroutine Called in LCDDSP
ine
SubNout
Function
Label
ame
CHECK BUSY
Checks busy flag.
LCDBSY
FLAG
(2) User Notes
(a) Selects DDR of port G as output.
(b) Calls program modules LCDRES and LCDINT and initializes LCD-II to make
H2570 display characters using LCD-II.
(3) RAM Description
RAM is not used in program module LCDDSP.
(4) Sample Application
Program module LCDDSP is called after selecting I/O port, resetting LCD-II,
initializing LCD-II and storing display data.

I
LDA

tl$FF

}

--Selects port G as output.
PGDDR
LCDRES ----calls program module LCDRES and resets LCD-II.
LCDINT----Calls program module LCDINT and initializes LCD-II.
11$41 ----Stores display data in entry argument.
IMI--J-S-R------L-C-D-D-SP--~II--·Calls program module LCDDSP.
STA
JSR
JSR
LDX
I

I
I

(5) Basic Operation
(a) Microcomputer cannot write data into LCD-II when LCD-II is in operation.
Whether LCD-II is in operation or not can be checked by busy flag.
Therefore, program module LCDDSP calls subroutine LCDBSY and checks
LCD-II busy flag to test if LCD-II is in operation.
Busy flag - 1
LCD-II is in operation. Data cannot be written.
Busy flag - 0 : Data can be written into LCD-II.
(b) Controls LCD-II control signal and writes data into LCD-II with timing
iHus trated in "2.1 HARDWARE DESCRIPTION, (5) Hardware Operation".

~HITACHI
635

I

PROGRAM MODULE NAME
FLOWCHART

II

DISPLAY ON LCD

II MCU/MPU I HD6305XO/YO ILABEL IfCDDS~

~==========~==~====~==~~

____{Cal1s subroutine LCDBSY for LCD-II
busy check.
----1[sets signals RS to High. R/Wand E to Low.
-----[ Sets signal E to High.
-----[ Outputs ASCII for display to LCD-II.

-----[sets signal E to Low.

~HITACHI
636

2.4

SUBROUTINE DESCRIPTION

I

SUBROUTINE NAME

I

FUNCTION

I

~I===CH=E=C=K=BU=S=Y=F=LA=G==I~I=M=C=U=/=MP=U=Il-=HD=6=3=0=5=XO=/=Y=OJ:..=1L=A=B=E=L::.I~IL=C=D=B~S~

I

(1) Tests LCD-II status.
(2) Loops subroutine LCDBSY until LCD-II becomes READY.

I

BASIC OPERATION

I

The MSB of data bus becomes busy flag if LCD-II data bus is read
during RS=O, R/W=l and E=l.
MODULE USING Il
II PROGRAM
THIS SUBROUTINE
J

FLOWCHART

LCDINT, LCDDSP

LCDBSY )
LCDBSYj
$00 -+ PGDDR

------[Se1ects port G as input.

$04 -+ PFDTR

------[sets signals R/W to High, RS and E to Low.

LCDBYII
05 -+ PFDTR
(PGDTR)
-+ACCA

-------[sets signal E to High.
------[Loads busy flag into ACCA.

Shifts(ACCA)
1 bit left

------[ Loads busy flag into bit C.

$04 -+ PFDTR

------[sets signal E to Low.

L.(B_i_t_C<)~

_____{ Loops until busy flag

~C)=O
$FF -+ PGDDR

(

RTS

beco~s

"0".

------[ Selects port G as output.

)

~HITACHI
637

2.5

PROGRAM LISTING

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055

*****

*

0080
0080 0001
0081 0001

ORG

*POINTR

RMB
LCDCNT RMB

*

****

OOOC
0000
0007

RA.M ALLOCATION
$SO
1
1

EQU
EQU

$OC
$00
$07

*************

Port F data register
Port G data register
Port G data direction register

************************************************

*
*
*
************************************************
*
ORG
$1000
*
Clear' pointer'
LCDMN
CLR
A
*
*
*

1000
1000
1001
1003
1005
1007
1009
100C
100F
1011
1014
1016
lOIS
1018
1010
101F

4F
87
87
A6
87
CD
CD
8E
DE
A3
27
CD
3C
20
20

SO
00
FF
07
1021
1041
SO
10BA
FF
07
1059
80
FO
FE

LCDM1

PEND

MAIN PROGRAM : LCDMN

STA
STA
LOA
STA
JSR
JSR
LOX
LOX
CPX
BEQ
JSR
INC
8RA
BRA

POINTR
PGDTR
t:I$FF
PGDDR
LCDRES
LCDINT
POINTR
DDATA.X
t:I$FF
PEND
LCDDSP
POINTR
LCDMI
PEND

Initialize port G
Select port G as output
Reset LCD-II
Initialize LCD-II
Load data table pointer
Ascii data -> IX
Test if IX=$FF
Branch if IX=t:I$FF
Display data
Increment pointer
8ranch always LCDM1
End of main program

************************************************

*
*
NAME: LCDRES (RESET LCD-II)
*
*
**************************************************

1021
1023
1025
1027
1029
102A
102C
1020
102F

A6
87
A6
AE
SA
26
4A
26
B7

03
81
OC
FF
FD
FS
OC

*
*
ENTRY
NOTHING
*
*
NOTHING
RETURNS
*
*
*
*
************************************************
LCDRES LOA
STA
LCDRSI LOA
LCDRS2 LOX
LCDRS3 DEC
BNE
DEC
8NE
STA

t:l3
LCDCNT
t:I$OC
t:I$FF
X
LCDRS3
A
LCDRS2
PFDTR

~HITACHI
638

Pointer of display data table
Loop counter

SYMBOL DEFINITIONS

*
PFDTR
EQU
PGDTR
PGDDR

*************************

Initialize loop counter

Initialize ISms counter
Initialize inner counter
Decrement inner counter
Loop until inner counter=O
Decrement ISms counter
Loop until 15ms counter=O
Set RS=O.R/W=O.E=O

00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110

1031
1033
1035
1037
1039
103A
103C
103E
1040

A6
87
A6
87
4F
87
3A
26
81

LDA
STA
LDA
STA
CLR
STA
DEC
BNE
RTS

01
OC
30
OD
OC
81
E5

"$01
PFDTR
"$30
PGDTR

Set RS=O.R/W=O.E=l
d~ta

A

Write instruction
Set E=O

PFDTR
LCDCNT
LCDRS1

Decrement Loop counter
Loop untiL Loop counter=O

************************************************

1041
1043
1046
1047
1049
104B
104D
1050
1052
1053
1055
1056
1058

AE
CD
4F
B7
A6
B7
D6
B7
4F
B7
SA
26
81

06
1068
OC
01
OC
1083
OD
OC
EB

*
*
NAME: LCDINT (INITIALIZE LCD-II)
*
*
*
*
************************************************
*
*
ENTRY : NOTHING
*
*
RETURNS : NOTHING
*
*
**************************************************
LCDINT LDX"6
LCDIT1 JSR
LCDBSY
CLR
A
STA
PFDTR
LDA
"$01
STA
PFDTR
LDA
INS-1.X
STA
PGDTR
CLR
A
STA
PFDTR
DEC
X
BNE
LCDIT1
RTS

Load Loop counter
ChecK busy fLag
Set RS=O.R/W=O.E=O
Set E=l

Instruction data-)LCD-II
Set E=O
Decrement Loop counter
Loop untiL Loop counter=O

************************************************

1059
105C
lOSE
1060
1062
1064
1066
1068
106A

CD
A6
B7
A6
B7
BF
A6
B7
81

106B
02
OC
03
OC
OD
02
OC

*
*
NAME : LCDDSP (DISPLAY ON LCD-II)
*
*
**************************************************
*
*
ENTRY : IX (DISPLAY DATA)
*
*
RETURNS : NOTHING
*
*
*
*
************************************************

LCDDSP JSR
LDA
STA
LDA
STA
STX
LDA
STA
RTS

LCDBSY
"$02
PFDTR
"$03
PFDTR
PGDTR
"$02
PFDTR

ChecK busy fLag
Set RS=l.R/W=O.E=O

I

Set E=l
Display data-)LCD-II
Set E=O

************************************************

*
*
*

NAME : LCDBSY (CHECK BUSY FLAG)

$

*
*
*

HITACHI
639

00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148

106B
106C
106E
1070
1072
1074
1076
1078
1079
107B
107D
107F
1081
1083

4F
B7
A6
B7
A6
B7
B6
48
A6
B7
25
A6
B7
81

*******************************************~***

07
04
OC
05
OC
OD
04
OC
F3
FF
07

1084 OC
108A 43
109A FF

1FF6
1FF6
1FF8
1FFA
1FFC
1FFE

1000
1000
1000
1000
1000

LCDBSY CLR
Select port G as lnp6t
A
STA
PGDDR
1:*$04
LDA
Set RS=O.R/W=l.E=O
STA
PFDTR
1:*$05
LCDBYl LDA
Set E=l
STA
PFDTR
LDA
PGDTR
Read busy flag
Set busy flag to bit C
LSL
A
1=1$04
LDA
Set E=O
STA
PFDTR
BCS
LCDBY1
Loop untiL busy fLag=O
I=I$FF
LDA
SeLect port G as output
STA
PGDDR
RTS
************************************************
*
*
DATA TABLE
*
*
*
*
************************************************
INS
$OC.$18.$90.$07.$01.$08 *instr'uction
FCB
DDATA FCC
ICMOS MCU HD6305XI
*DispLay
$FF
FCB
************************************************
*
*
VECTOR ADDRESSES
*
*
*
*
************************************************
*
$1FF6
ORG
*
FDB
LCDMN
SCIITIMER2
FDB
LCDMN
TIMER/INT2
FDB
LCDMN
INT
FDB
LCDMN
SWI
FDB
LCDMN
RES
*
END

@HITACHI
640

I3.

DUTY CONTROL OF PULSE OUTPUT

3.1

HARDWARE DESCRIPTION
(1)

Func t ion

(a)

Outputs pulse with OV100% duty rate from the HD630SXO.

(b)

(2)

Performs DA conversion of output pulse with external
integration circuit.
Microcomputer Applications

(a)

Executes the interrupt routine with the built-in 8-bit
timer with 7-bit prescaler in the HD630SXO (hereinafter
timer) .

(b)

Switches port C and outputs p_ulse with the interrupt
routine.

(c)
(3)

Changes High and Low period of pulse with TDR.

Circuit Diagram
MCU
HD630SXO
(HD630SYO)
+SV
33 VCC

f,

22pF

IN'r

4 mY
5 XTAL

4MHzO

+12V

6 EXTAL
1---4--'<1

22pF

2.2f-JF
~~Vr~~--~.~>-~--~ DA output

Fig. 1
(4)

I

Duty Pulse Output Circuit

Pin Functions
Pin function for pulse output is shown in Table 1.
Table 1

Pin Function

Pin Name
(HD630SXO)

Input I
Output

Active Level
(High or Low)

Function

Program
Label

C3

Output

-

Outputs pulse

PCDTR

~HITACHI
641

(5)

Hardware Operation
Outputs pulse with av100% duty rate at each 0.3s, increasing
the duty rate 4% each time from port on the HD6305XO.
The pulse output and DA conversion are shown in Fig. 2.

100
40 : 60
Output from Port C3
(duty 40%)
8ms

Output after
DA conversion

8ms

5V
4.6V

r---'
I

n

:

",,,,,,,~

O• 3S

0.4V

r-'

.----I

(,.,.,.",,,,

~

:---'
I

r--

I

~

OV~~------------~~~----------~--~I----­

t

Fig. 2

(Note)

Pulse Output and Waveform after DA Conversion

The output voltage after DA conversion is proportional to
the duty.
The operational amplifier is used to prevent the
flactuation of analog output voltage caused by the load
in user system.

~HITACHI
642

3.2

SOFTWARE DESCRIPTION
(1)

Program Module Configuration
The program module configuration for pulse output is
shown in Fig. 3.

DUMN

MAIN
PROGRAM

1

DUSET I
SET DUTY

L.!..

lQ.

DUOUT I
OUTPUT
PULSE

12

Fig. 3 Program Module Configuration

(2)

Program Module Functions
Program module functions are summarized in Table 2.
Table 2 Program Module Functions

No.

Program Module Name

Label

0

MAIN PROGRAM

DUMN

Outputs pulse with ()'\,lOO% duty rate.

Function

1

SET DUTY

DUSET

Sets duty.

2

OUTPUT PULSE

DUOUT

Outputs pulse from I/O port.

~HITACHI
643

(3)

Program Module Sample Application (Main Program)
The flowchart in Fig. 4 is an example of DA conversion by
controlling pulse, performed by the program module in Fig. 3.
Main program in Fig. 4 changes pulse output with ~lOO% duty rate
lat

each 0.3 second, increasing the duty rate 4% each time.
Main Program

;:::=::r:::::::::::;

-----{ Initializes RAM for work.

'-::=::r==~ _____ { port
Initializes port C and
C as output.

selects bit 3 of

r

;:::=::r::::::~

-----{ Initializes timer control register.
-----{ Enables interrupt.

r--I,Jnm:i~C:=~ _____ { Stores
:==::r::::::~

entry argument in program
module DUSET.
{ Calls program module DUSET to store
----- entry argument in program module DUOUT.

Increments data for next pulse output.

Executes software timer of about

0.3s.

(IX);O

Timer Interrupt Routine

'::=::E::::::-'

_____ [ Executes program module DUOUT to output
puIs e .
Fig. 4

644

Program Module Flowchart

~HITACHI

3.3

I

PROGRAM MODULE DESCRIPTION

PROGRAM MODULE NAME

I

FUNCTION

II

II

SET DUTY

MCU/MPU IlHD6305XO/ YO II LABEL IIDUSET

I

IJ

(1) Stores High and Low output period corresponding to I-byte hexadecimal duty

stored in entry argument.

(2) Specifies duty each 4%.

I

ARGUMENTS

CHANGES IN CPU
REGISTERS AND FLAGS

1/
Storage
Location

Contents

•

Byte
Lgth.

ACCA
Duty

IX

1

I

x

ROM (Bytes)
40

Undefined
Result

I

RAM (Bytes)

IX

• I

I

SPECIFICATIONS

: Not affected

x :
:

t
Entry

JI

3
Stack (Bytes)
0

Arguments

Hi~h

HTIME
(RAM)

ou put
pen.od
Low
output
Reperiod
turns
Output
status
flag

LTIME

1

(RAM)

1

HLOUT
(RAM)

1

C

Z

x

x

N

I

x

•

No. of cycles
33
Reentrant
No

H

Relocation

•

Interrupt

No
Yes

I

DESCRIPTION
(1)

I

En«y
{
argument

Function Details

IX
($OA)

b7

I

IX
0

bO
A

: I

t

(a) Argument details
IX: Holds duty as I-byte
r
b7 HTIMEbO
hexadecimal number.
HTIME(RAM) I 6
4
HTIME(RAM) : Contains High output period.
($64)
LTIME
LTIME(RAM) : Contains Low output period. ~Return
HLOUT(RAM): Contains Flag indicating
arguments LTIME (RAM) I 9
6
($96)
what output is performed;
HLOUT
Low consecutive output,
HLOUT(RAM)I 0
2
High consecutive output,
($02)
or pulse output.
Fig. 5 Example of DUSET
Table 3 shows flag functions.
Execution

:

I
: I
: I

I

SPECIFICATIONS NOTES

I

"No. of cycles" in "SPECIFICATIONS" represents the number of cycles required
in case of duty 40%.

~HITACHI
645

PROGRAM MODULE NAME

II

SET DUTY

~========~==~==========~

DESCRIPTION

Table 3
Bit/Label
Bit 1 Bit 0

Label

HLOUT

0

0

1

0

1

1

Flag Functions
Function
uutputs
of Port
Outputs
Outputs
of port

Low consectively from bit 3
C.
pulse from bit 3 of port C.
High consect1vely trom b1t j
C.

(b) Fig. 5 shows an examples of program module DUSET execution.
When entry argument is as shown in part  of Fig. 6.
(c) Program module DUOUT calls neither program modules nor subroutines.
(2) User Notes
(a) Selects DDR of port C as output.
(b) Initializes timer.
(c) Clear bit I to enable timer interrupt.
(3) RAM Description
Label

Description

RAM
b7

bO

} Stores
} Stores

HTIME
LTIME

}

HLOUT

High output period.

Low output period.
Stores flag indicating High, Low or pulse
output from bit 3 of port C.

(4) Sample Application
Program module DUOUT is called to output pulse from bit 3 of port C
after initializing port C, timer and duty, and enabling interrupt.
I

LDA
STA
LDA
STA

11$08

PCDDR
11$00

}---selects bit 3 of port C as output.

TCR

}---sets timer dividing rate at + 32.

LDX

1110

--- Loads duty into entry argument of program module DUSET.

JSR

DUSET

---Calls program module DUSET to store High and Low output
periods in entry arguments of program module DUOUT.

CLI
I

---Enables interrupt.

I

~HITACHI
649
- - - - - - - - - - - - ---------------

PROGRAM MODULE NAME

II

DESCRIPTION

OUTPUT PULSE

II MCU/MPU I HD6305XO/YO ILABEL I~UOUT I

~==========~==~====~==~~

(5) Basic Operation
(a) Determines the previous output at every timer interrupt, and changes
output port. High to Low, Low to High. The period of High or Low is
stored in TDR.
(b) When duty is 0% or 100%. TDR is set to 50% output and the output port
remains in High or Low state.

~HITACHI
650

PROGRAM MODULE NAME
FLOWCHART

II

OUTPUT PULSE

II MCU/MPU I HD6305XO/YO ILABEL IIDUOUT I

I~==========~==~====~==~~

-----[Clears timer interrupt request flag.
(3,PCDTR)=O

----~Tests

whether Low or High.

(3,PCDTR)"O

-----[stores High period in TDR.
(l,HLOUT)=O

_____[ Tests output status flag in High
period.
-----[ Outputs High from bit 3 of port C.

-----[stores Low period in TDR.
_____[Tests output status flag in
Low period.
(O,HLOUT)"l
..---.....I..~;....., _____[ Outputs Low from bit 3 of port C.
DUOUT2

~HITACHI
651

3.4

SUBROUTINE DESCRIPTION
This application example calls no subroutines.

3.5 PROGRAM LISTING
00001
00002
00003
00004 0080
00005
00006 0080 0001
00007 0081 0001
00008 0082 0001
00009 0083 0001
00010
00011
00012
00013
0002
00014
0006
00015
0008
00016
0009
00017
00018
00019
00020
00021
00022
00023 1000
00024
00025 1000 4F
00026 1001 B7 83
00027 1003 B7 02
00028 1005 A6 08
00029 1007 B7 06
00030 1009 A6 OD
00031 100B B7 09
00032 100D 9A
00033 100E BE 83
00034 1010 AD 14
00035 1012 5C
00036 1013 A3 1A
00037 1015 26 01
00038 10 1 7 SF
00039 1018 BF 83
00040 lOlA AE FF
00041 101C A6 FF
00042 10lE 4A
00043 101F 26 FD
00044 1021 SA
00045 1022 26 F8
00046 1024 20 E8
00047
00048
00049
00050
00051
00052
00053
00054
00055

*

*>1<>1<>1<

RAM ALLOCATION
ORG

$80

>I<

HTIME
L TIME
HLOUT
WORK

RMB
RMB
RMB
RMB

High puLse data
Low puLse data
Output data ststus
Work for entry argument

>I<
>1<>1<>1<>1<

SYMBOL DEFINITIONS

*>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<

>I<

PCDTR
PCODR
TDR
TCR

EQU
EQU
EQU
EQU

$02
$06
$08
$09

Port C data register
Port C data direction
Timer data register
Timer control register

>1<>1<>1<>1<>1<>1<>1<*>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<

>I<

>I<

MAIN PROGRAM : DUMN

>I<
>I<

>I<
>I<

>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<*>1<>1<>1<>1<

>I<

*

DUMN

ORG

$1000

CLR
STA
STA
LDA
STA
LDA
STA

WORK
PCDTR
11$08
PCDDR
11$00
TCR

A

CLI
DUMN1

DUMN2
DUMN3
DUMN4

LDX
BSR
INC
CPX
BNE
CLR
STX
LDX
LDA
DEC
BNE
DEC
BNE
BRA

WORK
DUSET
X
1126
DUMN2
X

WORK
fj$FF

rlear entry argument
Initialize port C
SeLect port C bit 3 as output
Set prescaler 1/32
Enab lei nturrupts
Load entry argument of DUSET
Store entry argument of DUOUT
DUTY+4%-)entry argument
DUTY=104% ?
Store 0% duty
Store duty In entry argument
Execute 0.3s software timer

Il$FF
A

DUMN4
X

DUMN3
OUMNI

>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<*>1<>1<>1<>1<*>1<>1<>1<>1<>1<>1<>1<>1<>1<

>I<
>I<

>I<

NAME : DUSET (SET DUTY)

>I<
>I<

*

*>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<

>I<

>I<

>I<
>I<
>I<

ENTRY
RETURNS

IX
(DUTY DATA)
HTIME (HIGH PULSE PERIOD)
LTIME (LOW PULSE PERIOD)

~HITACHI
652

>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<>1<

>I<

>I<
>I<
>I<

00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110

1026
1027
1029
1028
102D
102F
1031
1033
1035
1037
1039
103B
103D
103F
1042
1044
1047
1049
1048
104D

104E
1050
1053
1055
1057
105A
lOSC
lOSE
1060
1062
1065
1067

5D
26 06
11 82
13 82
20 08
A3 19
26 OC
10 82
12 82
A6 7D
B7 80
B7 81
20 OE
D6 1067
B7 80
D6 107F
B7 81
11 82
12 82
81

1F
07
B6
87
00
17

20
B6
B7
03
16
80

1068 OA
1069 14
106A IE

HLOUT (OUTPUT STATUS FLAG)
*
*
*
*
************************************************
DUSET

DUSETl

DUSET2

DUSET3

DUSET4

TST
8NE
8CLR
8CLR
BRA
CPX
BNE
BSET
BSET
LDA
STA
STA
BRA
LDA
STA
LDA
STA
BCLR
BSET
RTS

Test tf duty=O% ?
X
DUSET1
O.HLOUT Set for Low
1.HLOUT Set for Low puLse
DUSET2
Test if duty=100%?
t:l25
Branch for puLse output
DUSET3
O.HLOUT Set for high
1.HLOUT Set for htgh puLse
Set 50% duty timming
t:l125
HTIME
LTIME
DUSET4
HTDATA-1.X Set period of high puLse
HTIME
LTDATA-l. X Set period of Low puLse
LTIME
O.HLOUT Set for Low puLse
1.HLOUT Set for high puLse

************************************************
*
*
NAME : DUOUT (OUTPUT PULSE)
*
*
*
*
************************************************
*
*
HTIME (HIGH PULSE PERIOD)
ENTRY
*
*
LTIME (LOW PULSE PERIOD)
*
*
HLOUT (OUTPUT STATUS FLAG)
*
*
RETURNS : NOTHING
*
*
*
*
************************************************

09
DUOUT BCLR
BRCLR
02 OB
LDA
81
STA
08
BRSET
82 OD
BCLR
02
BRA
09
DUOUT1 LDA
80
08
STA
82 0'2
BRCLR
BSET
02
DUOUT2 RTI

CLea (' interrupt request btt
7.TCR
3.PCDTR.DUOUTl High or Low output?
Store for Low puLse period
LTIME
TDR
0.HLOUT.DUOUT2 Duty=O%?
3.PCDTR Output Low puLse
DUOUT2
Store for high puLse period
HTIME
TOR
1.HLOUT.DUOUT2 Duty=100% ?
3.PCDTR Output high puLse

************************************************
*
*'
DATA
TABLE
*
*
*
*
************************************************
HTDATA FCB
FCB
FCB

10
20
30

4
8
12

*High puLse period

~HITACHI
653

I

00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170

106B
106C
1060
106E
106F
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
107A
107B
107C
1070
107E
107F
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
108A
108B
108C
lOBO
lOBE
l08F
1090
1091
1092
1093
1094
1095
1096
1097

28
32
3C
46
50
SA
64
6E
78
82
8C
96
AO
AA
B4
BE
CB
02
DC
E6
FO
FO
E6
DC
02
CB
BE
B4
AA
AO
96
8C
82
78
6E
64
SA
50
46
3C
32
28
IE
14
OA

1FF6
1FF6
1FF8
IFFA
1FFC
1FFE

1000
104E
1000
1000
1000

FCB
16
40
FCB
50
20
FCB
60
24
FCB
28
70
FCB
32
80
FCB
90
36
FCB
100
40
FCB
110
44
FCB
48
120
FCB
130
52
FCB
56
140
FCB
150
60
FCB
64
160
FCB
170
68
FCB
180
72
FCB
190
76
FCB
200
80
FCB
210
84
FCB
88
220
FCB
92
230
FCB
96
240
LTDATA FCB
4
*Low puLse period
240
FCB
230
8
FCB
12
220
FCB
16
210
FCB
200
20
FCB
190
24
FCB
180
28
FCB
170
32
FCB
160
36
FCB
150
40
44
FCB
140
FCB
130
48
FCB
120
52
FCB
110
56
FCB
100
60
FCB
90
64
FCB
80
6B
FCB
70
72
FCB
60
76
FCB
50
80
FCB
84
40
FCB
30
88
FCB
20
92
FCB
96
10
************************************************
.*
*
VECTOR ADDRESSES
*
*
*
*
************************************************
*
$lFF6
ORG
*
FDB
DUMN
SCI/TIMER2
FOB
TIMER/INT2
DUOUT
FOB
DUMN
INT
FOB
DUMN
SWI
RES
FOB
OUMN
lI<

END

~HITACHI
654

14.

PULSE WIDTH MEASUREMENT
4.1

HARDWARE DESCRIPTION
(1)

Function
(a)

Measures the High period of the pulse using the
HD6305XO.
100~s

to

255~s.

(b)

Measures pulse width from

(c)

Converts measurement result into binary coded decimal
(BCD) m.unber.

(2)

Microcomputer Applications
(a)

Measures pulse width using TIMER pin and INT pin of the
HD6305XO.

(b)

The HD6305XO counts down TDR while the TIMER pin is
High.

(c)

Executes interrupt routine on the INT falling edge,
reads TDR value, and measures pulse width.

(3)

Circuit Diagram

+5V

MCU
HD6305XO
(HD6305YO)

33 VCC

~.:o :::AL
.,tJ2PF

2 RES

2.2~F

7 NUM
1 Vss

Pulse input

ILJL

Fig. 1

Pulse Width Measurement Circuit

~HITACHI
655

(4)

Pin Functions
Pin functions for pulse width measurement are shown in Table 1.
Table 1

Pin Functions

Pin Name
(llD6305XO)

Input/
Output

INT

Input

Low

Detects falling edge of input
pulse and executes the external
interrupt routine.

TIMER

Input

High

Counts down the TDR during
"1" active period.

(5)

Active level
(High or Low)

Program
Label

Function

/

/

Hardware Operation
The HD6305XO measures the pulse width by counting down the
TDR using the E clock while TIMER pin is High, which is
given in Fig. 2.

TDR pulse count value N

N

4

E Clock

TIMER input pin

--------~I:

Clock width W

1 4 - - - - ' - - "~

(Note) When E clock cycle is l~s, the clock width W is
Measurement error is within l~s.

Fig. 2

Pulse Width Measurement

~HITACHI
656

4~s.

4.2

SOFTWARE DESCRIPTION
(1)

Program Module Configuration
The program module configuration for measuring pulse width and
converting result into BCD number is shown in Fig. 3.

PWMN

LQ..
MAIN
PROGRAM

I
PWCNT

I

HEX

LL

CONVERT L1..
HEXADECIMAL
INTO BCD

MEASURE
PULSE WIDTH

Fig. 3
(2)

I

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 2.
Table 2

No.

Program Module Functions

Program Module Name

Lavel

0

MAIN PROGRAM

PWMN

Obtains the pulse width in BCD number.

1

MEASURE PULSE WIDTH

PWCNT

Calculates the pulse width from TDR in
I-byte hexadecimal number.

2

CONVERT HEXADECIMAL
INTO BCD

HEX

Converts I-byte hexadecimal number into BCD.
See subroutine HEX in HD630S FAMILY
APPLICATION NOTES (SOFTWARE) for details.

Function

~HITACHI
657

(3)

Program Module Sample Application (Main Program)
The flowchart in Fig. 4 is an example of pulse width measurement
performed by the program module in Fig. 3.
The main program in Fig. 4 obtains the pulse width as BCD number.

Main Program
Loads $50 into TCR, disables timer
---- { interrupt and sets presca1er rate
to "+1".

(iN!) =1

pulse is Low.

----{ Initializes TDR.
is Low.
_____[C1ears RAM for storing pulse width.

-----[Enab1es interrupt.

Stores 1-byte hexadecimal pulse.
-----[ width in entry argument (HEXD(RAM»
subroutine HEX.

l

____

(

PWCNT

)

ca11S subroutine HEX and converts
1-byte hexadecimal pulse width into BCD.
See subroutine HEX in HD6305 FAMILY
APPLICATION NOTES (SOFTWARE) for
details.

lNT Interrupt Routine

PWCNT
MEASURE
_____[Obtains the pulse width in 1-byte
PULSE WIDTH
hexadecimal number.

Fig. 4

Program Module Flowchart

~HITACHI
658

of

4.3

PROGRAM MODULE DESCRIPTION

I

PROGRAM MODULE NAME

II

FUNCTION

I

I

II MCU/MPU I IHD6305XO/ YO I ILABEL IlpWCNT I

MEASURE PULSE WIDTH

(1) Calculates the pulse width in I-byte hexadecimal number and stores result

in TDRRAM(RAM).
(2) Sets oscillator frequency to 4MHz in P!"og!;am module PWCNT execution.

I

I

ARGUMENTS

CHANGES IN CPU
REGISTERS AND FLAGS
Storage
Location

Contents

•

Byte
Lgth.

-

-

-

SPECIFICATIONS

Not affected
x : Undefined
t : Result
:

ACCA
Entry

II

I

x

ROM (Bytes)
10
RAM (Bytes)

IX

I

I

I

• I

Stack (Bytes)
0

Arguments

Returns

Pulse
Width

TDRRAM
(RAM)

1

C

Z

x

x

N

I

x

•

No. of cycles
18
Reentrant
No

H

Relocation

•

No
Interrupt
No

I

DESCRIPTION
(1)

I

 Input

160 pulses

-I

~--------~

b7 bO
b7 bO
(a) Arguments details
STRTF IJIIIIJ
STRTF 0lID
STRTF(RAM): Holds flag indicating
($01)
~ ($00)
start/stop of pulse
count. Table 3 shows
ACCA
flag functions.
b7
bO
ACCA: Contains result of
Return [ ACCA
pulse count as I-byte
0
A:
<2> argument ($AO)
hexadecimal number.
Fig. 5 Example of PLSCNT
Execution

I

I

SPECIFICATIONS NOTES

I

I

"No. of cycles" in "SPECIFICATIONS" represents the number
of cycles required to start pulse count.

~HITACHI
667

PROGRAM MODULE NAME

II

II MCU/MPU I HD6305XO/YO ILABEL IrLSCN~

COUNT PULSES

I~========~====~====~~~

DESCRIPTION

Table 3
Bit/Label

Label

Flag Functions
Function

h,t

STRTF

0

Stops pulse count

I

Starts pulse count

(b) Fig. 5 shows an example of program module PLSCNT execution. If 160
pulses are input from TIMER pin as shown in part CD of Fig. 5, the count
result is contained in ACCA as shown in part  Return {FREQ
argument

Fig. 5

I

I_

(RAM)
($00)

b7

I

FREQ
bO
0 I
0

:

EXrmple of FRQCNT
Execution

"No. of cycles" in "SPECIFICATIONS" represents the number of
cycles requi red to measure frequency of 60 Hz.

~HITACHI
675

I

!

PROGRAM MODULE NAME

II

DESCRIPTION

II

I

Label

MEASURE POWER
FREQUENCY

Table 3
Bit/Label
bit I
bit 0

FREQ

II MCU/MPU IIHD6305XO/YO I! LABEL I fRQCN~

Flag Functions
Function

0

0

Frequency is 50Hz.

0

I

Frequency is 60Hz.

I

I

Frequency is other than 50Hz or 60Hz.

(b) Fig. 5 shows an example of program module FRQCNT execution. If power
supply of 50Hz is measured as shown in part 
Return
KEYONF
KEYONF(RAM) : Contains program
ar uments
module K84SCN
g
KEYONF(RAM) I 0:
1
($01)
completion status.
KEYONF(RAM)=1 : Indicates that
key scan data
Fig. 5 Example of K84SCN
is stored in
Execution
KEYDAT(RAM).

°:

I

I SPECIFICATIONS NOTES I
"No. of cycles" in "SPECIFICATIONS" represents the number of cycles required
until key data is valid.

~HITACHI
688

I

I

PROGRAM MODULE NAME

II

II MCU/MPU I HD6305XO/YO ILABEL IIK84SC1

KEY SCAN

I~========~====~======~~

DESCRIPTION

KEYONF(RAM)=O : Indicates that key scan data is not stored in
KEYDAT(RAM).
(b) Fig. 5 shows an example of program module K84SCN execution. If key in
part aD of Fig. 5 is depressed, key scan data is contained in
KEYDAT (RAM) as shown in par t 0 of Fig. 5.
(c) Program module K84SCN calls neither program modules nor subroutines.
(2) User Notes
(a) Initializes timer 2.
(b) Clears bit I and enables interrupt.
(3) RAM Description
Label

RAM
b7

Description
bO

NEW KEY

}
}

OLDKEY
STBDAT

}

KEYNUM

}

TOTLKY

}
}

KEYONF

}
}
}

KEYDAT
SCOUNT
CHATFL

Stores previous key input data.
Stores present key input data.
Stores data for strobe signal output.
Stores key number.
Stores total number of depressed key during present
key scan.
Stores flag indicating key being defined during
key scan.
Stores defined key number by key scan.
Stores counter for retrieving depressed key among
key input data.
Bit 3-0; Stores counter for counting number of key
scan data comparison.
Bit 7
Stores flag for indicating whether chatter
elimination has been completed.

(4) Sample Application
Program module K84SCN is called every 8ms after initializing timer 2 and
enabling interrupt.
I

LOOP

CLR
CLR
CLR
LDA
STA
LDA
STA
CLI
BRCLR

OLDKEY
KEYONF
PCDTR

LDA
STA
BCLR

KEYDAT
}---stores key scan data in RAM.
KEY SET
O,KEYONF - - --Clears key press flag.

I
I

II$OD

SCR
11$20
SSR

I

}- - - Clears RAM to be used.
- - - Initializes port C.

1---

Sets timer 2 interrupt cycle to 8ms, and
enables timer 2 interrupt.

- - -Enables interrupt.
O,KEYONF,LOOP---Tests key press. I

I

~HITACHI
689

PROGRAM MODULE NAME

II

DESCRIPTION

KEY SCAN

II

MCU/MPU

I

HD6305XO/YO

I I

LABEL fS4SC,

~========~==~====~====~

(5) Basic Operation.
(a) Executes key scan with every Sms timer interrupt. Checks key scan
execution flag (KEYONF(RAM» at the beginning of key scan, and decides
whether present key scan data will be executed or not.
(b) Outputs strobe signal from bit 3 to 0 of port C one by one, and fetches
key press data from port G.
(c) Tests if key scan data loaded into (b) is $FF.
(i) $FF key scan data means that key of the column supplying current
strobe signal was not depressed. Key scan for next column is started.
(ii) Key scan data other than $FF means key of the column supplying current
strobe signal is depressed. Test which row is pressed.

CD

Tests if bit C is 1 or 0 by shifting ACCA content where key scan
data is stored, by 1 bit to right S times. In case of bit C is 0,
the key was depressed.

~ To test double keys depressed, if key scan data includes 0, TOTLKY(RAM)

is incremented. In case of TOTLKY=l, KEYNUM(RAM) content is stored
in NEWKEY(RAM). In case of TOTLKY>I, double keys were depressed and
return from program-module is performed.
(d) Compares key data (NEWKEY(RAM» detected in (c) with previous key data
(OLDKEY(RAM». If they are the same, counts-up lower 4 bits of chatter
counter CHATFL(RAM). When the counter indicates "3", the key is defined.
This is indicated by setting MSB of chatter cancel flag CHATFL(RAM) to
" 1 ".
The CHATFL(RAM) indicates both counter and flag. The chatter
cancel flag is cleared when NEWKEY(RAM) and OLDKEY(RAM) data are
different, and when no key is depressed.

~HITACHI
690

I

PROGRAM MODULE NAME

II

KEY SCAN

II

MCU/MPU

I

HD6305XO/YO

I I~84SC'
LABEL

I~==========~==~====~==~~

FLOWCHART

~

__~____~

____ { Clears interrupt request bit of
timer 2.
is processed

data for strobe signal.

----{ Initializes RAM indicating key number.
____ { Initializes RAM indicating the number
of depressed key.
____{Initializes RAM storing newly-depressed
key number.
-----[ Outputs strobe signal.

-----[ Loads key input data.

~HITACHI
691

PROGRAM MODULE NAME
FLOWCHART

II KEY SCAN
II MCU/MPU I HD6305XO/YO ILABEL If84SC,
I~==========~==~====~==~~

___ {stores shift counter to check what
key is depressed among 8 bits.
---{ Shifts key input data I bit right.
---{ Tests if key is depressed.

___ J

1

Tests if 2 keys are depressed at the
same time.

____[ Stores depressed key number in
NEWKEY(RAM) .
----[ Increments RAM indicating key number.
---{ Decrements shift counter.

if one row key scan is completed.
4
___ { Shift strobe Signal data I bit right
to execute key scan for next column.
I

___ {Tests if all column key scan is
completed.

~HITACHI
692

I

PROGRAM MODULE NAME
FLOWCHART

II

II MCU/MPU I HD6305XO/YO ILABEL IE84SC,

KEY SCAN

I~==========~==~======~====~

present key input data is O.

(NEWKEY) =(OLDKEY)

__{compares present key input data with
previous key input data.
~,.....,,=o.=....---'

previous
NEWKEY(RAM)
and clears
of key scan
press.

--~Tests

if key is continuously pressed.

Compares the number of chatter
(CHATFL(RAM» with constant number.
If they are the same, determines as
key press and fetches key data.

--1[Increments the number of chatter.

--

{ Sets flag indicating the termination
of chatter prevention.

__{stores depressed key data in RAM for
processing with main program.
__{sets flag indicating depressed key
data being defined •

•

HITACHI
693

7.4

SUBROUTINE DESCRIPTION
This application example calls no subroutines.

7.5

PROGRAM LISTING

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
0004'4
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055

0080
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089

0001
0001
0001
0001
0001
0001
0001
0001
0001
0001

*
****
*
*
II<
*
>I<
*
*
*

NAME : 1<84SCN (II<

00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
0007B
00079
00080
OOOBI
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110

101E
1020
1023
1025
1027
1029
102B
1020
102F
1031
1033
1035
1037
1039
103B
1030
103F
1041
1043
1045
1046
1048
104A
104C
104E
1050
1052
1054
1056
1058
105A
105C
lOSE
1060
1062
1064
1066
1068
106A
106C
106F
1071
1073
1075
1077
1079
107B
1070
107F
1081
1083

10
00
A6
B7
A6
B7
3F
3F
B6
B7
B6
A1
26
A6
BB
B7
20
AE
BF
47
25
3C
BE
A3
25
BE
BF
3C
3A
26
37
26
B6
27
B1
27
B7
3F
20
OE
A6
B4
B1
27
3C
20
IE
B6
B7
10
80

*
* RETURNS : KEYOAT (KEY DATA)
KEYONF (ESTAFLISHMENT OF KEY ON) *
*
*
*
************************************************

1<84SCN BCLR
11
BRSET
84 60
LOA
08
STA
88
01
LOA
87
STA
CLR
86
82
CLR
88
K84SN1 LOA
STA
06
LOA
00
CMP
FF
BNE
08
LOA
08
87
ADD
87
STA
19
BRA
K84SN2 LOX
08
STX
89
1<84SN3 ASR
OC
BCS
INC
86
86
LOX
CPX
01
33
BCS
87
LOX
82
STX
K84SN4 INC
87
89
DEC
EB
BNE
88
K84SN5 ASR
01
BNE
82
LOA
BEQ
04
81
CMP
BEQ
06
81
1<84SN6 STA
CLR
83
17
BRA
83 14 1<84SN7 BRSET
OF
LOA
83
AND
CMP
03
BEQ
04
83
INC
BRA
08
83
K84SN8 BSET
82
LOA
85
STA
BSET
84
K84SN9 RTI

CLear interrupt request fLag
6.SSR
o.I
Fig. 6

Fluores{ent display +
II , 1,1 , , II I
Result
I

I '1Ihl'-, ~HI(lll:

Example of FLDSP Execution

I "No. of cycles" 'in "SPECIFICATIONS" represents the number
of cycles required to display 1 digit.

702

$F8
$82
$92
$99
$BO
$A4
$E9
$CO

~HITACHI

I

I

PROGRAM MODULE NAME

I

DESCRIPTION

Ir.:::=ll
.If::::l r;:;:l
II
II~==========~==~====~==~==
DRIVE FLUORESCENT
DISPLAY TUBE

~ HD6305XO/YOI~~

(c) Table 3 shows relation between display data and actual display.
Table 3
Display Data and
Corresponding Display
Display
Data

Display

Display
Data

n

$CO

$BO
$99

5

$82

r
-:

$A4

-.

I

$92

I.J
I
I

$E9

Display

1

$F8

..,

I I

$80

U
IJ_

$90

I'

:J

(d) Program module FLDSP calls neither program modules nor subroutines.
(2) User Notes
(a) Reserves data shown in Table 3 as data table.
(b) Selects DDRs of port A and port C as output.
(c) Initializes timer 2.
(d) Clears bit I to enable timer 2 interrupt.
(3) RAM Description
Label

bO

b7
SEGD

,.--

----

--

~

-

DSCNTR
DECD

Description

RAM

10 7
10 6
105
10 4
10 3
10 2
10 1
100

digit
digit
digit
digit
digit
digit
digit
dhit

-

Stores 8-digit display data shown in
Table 3.

l

Stores counter indicating digit to be
displayed.
Stores data indicating digit turned on.

~HITACHI
703

DRIVE FLUORESCENT
DISPLAY TUBE

PROGRAM MODULE NAME

I

MCU/MPU

I HP6305XO/YO ILABEL II FLDSP I

DESCRIPTION
(4) Sample Application
Program module FLDSP is executed every lms after clearing bit I, initializing digit output data, counter, port and timer 2. Fluorescent displays
when display data is stored in display RAM.
I
I
I

LDA
STA
LDA
STA
LDA
STA
STA
LDA
STA
LDA
STA
CLI
LDA
STA
LDA
STA
LDA
STA
LDA
STA
JSR

II$FE

DECD

}------

Initializes digit output data.

11$07 }
Initializes digit output counter.
DSCNTR
II$FF }
PADDR
- - - -- Selects ports A and C as output.
PCDDR
II$OA

SCR
11$2F

SSR

}-----

Sets interval of timer 2 interrupt to lms.

}----- Enables

timer 2 interrupt.

- - - - - - Enab les in terrupt •
11$11

SOA
11$00

SOA+l
IISEGD

DEA

Calls subroutine MOVE and transfers display
data from data table to SEGD(RAM) where display
data is stored.

II$OB

MCNT
MOVE

I

I

I

ORG
FCB

$1100
$FB, $B2, $92, $99, $BO, $A4, $E9, $CO - - - - - - - Display data

(5) Basic Operation
(a) Previous digit display is turned off and next digit is displayed every
timer interrupt.
(b) DSCNTR(RAM) is used as counter for display digits and pointer for display
data and digit data.
(c) Outputs display data and digit data to port using index addressing mode.
(d) Decrements counter for display digits and pointer for digit data.

~HITACHI
704

I PROGRAM MODULE NAME

DRIVE FLUORESCENT
DISPLAY TUBE

I MCU/MPU

I HD6305XO/YO

I LABEL IIFLDSP

I

FLOWCHART

------[Clears interrupt request bit of timer 2.
_____{Turns off display for constant period
each time one digit is displayed.
-----l[Loads pointer indicating display data.
------{Outputs display data into port A.
------[outputs digit signal to port C.
______[Decrements counter indicating display
digit.
8 digits are displayed.

otate(DECD
1 bit left

_____{InitializeS data for next display
output.

------[ Initializes data for display output.
______[Initializes counter indicating
display digit.

~HITACHI
705

8.4

SUBROUTINE DESCRIPTION
This application example calls no subroutines.

8.5

PROGRAM LISTING

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052

*

RAM ALLOCATION

*

ORG

$80

*
SEGD
DSCNTR
DECO
SOA
DEA
MCNT
MSUB
SPNT

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

8
1
1

*

SYMBOL DEFINITIONS

****
0080
0080
0088
0089
008A
008C
0080
008E
0092

0008
0001
0001
0002
0001
0001
0004
0001

****
0000
0002
0004
0006
0010
0011

*
PADTR

PCDTR
PADDR
PCDDR
SCR
SSR

EOU
EOU
EOU
EOU
EQU
EQU

1
1
4
1

$00
$02
$04
$06
$10
$11

DispLay data
Digit counter'
Digit data
Source address
Destination address
Transfer counter
Work area for subroutine
ReLative data of source address

************

Port A data register
Port C data register
Port A data direction register
Port C data direction register
SCI controL register
SCI status register

************************************************

**
MAIN PROGRAM : FLMN
**
*
*
************************************************
*
ORG
$1000

1000
1000
1002
1004
1006
1008
100A
100C
100E
1010
1012
1014
1016
1017
1019
101B
1010
101F
1021
1023
1025
1027
1029

A6
B7
A6
B7
A6
B7
B7
A6
B7
A6
B7
9A
A6
B7
A6
B7
A6
B7
A6
B7
AD
20

FE
89
07
88
FF
04
06
OA
10
2F
11
11
8A
00
8B
80
8C
08
80
25
FE

*
FLMN

LOA
STA
LOA
STA
LOA
STA
STA
LOA
STA
LOA
STA

t:I$FE
DECO
1=17
DSCNTR
I=I$FF
PADDR
PCDDR
t:I$OA
SCR
1=I$2F
SSR

LOA
STA
LOA
STA
LOA
STA
LOA
STA
BSR
BRA

t:I$l1
SOA
1=1$00
SOA+1
I=ISEGD
DEA

CLI

PEND

•
706

2

*************************

t:l8

MCNT
MOVE
PEND
HITACHI

InitiaLize digit data
InitiaLize digit counter
SeLect port A as output
SeLect port C as output
InitiaL Ize SCR
InitiaLize SSR
EnabLe interrupts
Stores source start address
into entry argument
Stores destinatlo start address
into entry argument
Stores Length of byte to be
moved into entry argument
Move Segment data
End of main program

00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108

*******************************************

**
*
*
*
*
*******************************************
*
*
ENTRY
DEGD (DISPLAY DATA)
*
*
RETURNS
NOTHING
*
*
*********************************************
**

102B
102D
102F
1031
1033
1035
1037
1039
103B
103D
1040
1041
1043
1045
1047
1049
104B
104D

10
A6
B7
BE
E6
B7
B6
B7
3A
OF
99
39
20
A6
B7
A6
B7
80

NAME : FLDSP (DRIVE FLOURSCENT DISPLAY
TUBE)

11
FLDSP
FF
02
88
80
00
89
02
88
89 05
89
08
FE
89
07
88

BCLR
LDA
STA
LDX
LDA
STA
LDA
STA
DEC
BRCLR
SEC
ROL
BRA
FLDSP1 LDA
STA
LDA
STA
FLDSP2 RTI

6.SSR
CLear interrupt request flag
"$FF
Turn off dispLay
PCDTR
DSCNTR
Load di9it counter
SEGD.X
Output dispLay data
PADTR
DE CD
Output digit data
PCDTR
DSCNTR
Decrement digit counter
7.DECD.FLDSP1 DispLay 8-di9it ?
Store next dl9it data
DECO
FLDSP2
InitiaLize digit data
"$FE
DECO
InitiaLize digit counter
In
DSCNTR

************************************************

104E
1050
1052
1054
1056
1058
105A
105C
lOSE
1060
1062
1064
1066
1067

A6
B7
B6
B7
B6
B7
A6
B7
3F
BE
BD
BE
F7
3C

D6
8E
8A
8F
8B
90
81
91
92
92

8E
8C
8C

**
NAME : MOVE (MOVING MEMORY BLOCKS)
**
*
*
************************************************
*
*
ENTRY
SOA (SOURCE ADDR)
*
*
DEA (DESTINATION ADDR)
*
*
MCNT (TRNSFER COUNTER)
*
*
RETURNS : NOTHING
*
*
*
*
************************************************

MOVE

MOVE1

LOA
STA
LOA
STA
LDA
STA
LDA
STA
CLR
LOX
JSR
LOX
STA
INC

"$06
MSUB
Store instruction code (LDA
SOA
Disp.X)
MSUB+1
Store source ADDR (H)
SOA+1
MSUB+2
SLore source ADOR (L)
"$81
MSUB+3
Store instruction code (RTS)
SPNT CLear reLative data of source ADDR
SPNT Load reLative data of source ADDR
MSUB
Load transfer data
DEA
Destination ADDR
O.X
Store transfer data
OEA
Increment destination ADDR

~HITACHI
707

00109 1069 3C 92

INC

SPNT

106B 3A BD
1060 26 F1
106F 81

DEC
BNE
RTS

MCNT
MOVE1

00110
00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136

************************************************
*
*
DATA TABLE
*
*
*
*
************************************************
*

1100
1100 F8

*

ORG

$1100

FCB

$F8.$82.$92.$99.$BO.$A4.$E9.$CO

************************************************
*
*
VECTOR ADDRESSES
*
*
*
*
************************************************
*

IFF6
IFF6
1FF8
1FFA
1FFC
1FFE

102B
1000
1000
1000
1000

*

*

ORG

$lFF6

FOB
FOB
FOB
FOB
FOB

FLDSP
FLMN
FLMN
FLMN
FLMN

END

~HITACHI
708

Increment reLetive dete of
source ADDR
Decremerrt transfer counter
Brench until transfer counter=O

SCIITIMER2
TIMER/INT2
INT
SWI
RES

19.

STEPPING MOTOR CONTROL
9.1

HARDWARE DESCRIPTION
(1)

Func t ion
(a)

Drives stepping motor using the HD6305XO.

(b)

Uses 4-phase 2 exciting stepping motor.

(c)

1 to 255 steps can be selected.

(d)

Controls slue pulse rate (slow-up, operating and slow-down)
when 12 steps or more are selected.

(e)

Selects clockwise (normal) slue and counterclockwise
(reverse) slue with stepping motor.

Operates backlash

when reverse slue is selected.
(2)

Microcomputer Applications
(a) Executes interrupt routine using 8-bit timer with
7-bit presca1er contained in the HD6305XO
(hereinafter, timer).
(b) Drives stepping motor by outputting pulses from port B
by interrupt routine.
(c) Generates slow-up and slow-down pulse rate by changing
TDR value.

(3)

Circuit Diagram

MCU
HD6305XO
(HD6305YO)

+5V
33
3
4
5

+12V

+

VCC
INT"
ST
XTAL

ISSl72x4

6 EXTAL

2lmS"

7 NUM
1 VSS

Fig. 1

Stepping Motor Control

~HITACHI
709

(4)

Pin Functions
Pin functions at the interface between the HD6305XO
and stepping motor are shown in Table 1.
Table 1

Pin Name
(HD6305XO)

Input/
Output

Active
level
(High
or Low)

B2

Output

-

B3

Output

-

B4

Output

-

B5

Output

-

(5)

Pin Functions

Function

Pin Name
(Motor)

Program
Label

i

A

Connects stepping motor.

PBDTR
B
A

Hardware Operation
The stepping motor supplies pulses at the HD6305XO I/O port as
shown in Fig. 2.

Reverse slue

•

C

At initialization
Normtl slue

Step Count --I1_4:.....L.1..:3;...L..=,2...L..:l=-+-=O+=-l...L.I...;;2;;....&...1.; ;,.3......1_4~1

A(BS)

.J

B(B4)

----.I

A(B3) -,
"lr(B2) - - ,

I

r
LL

B4

B2

(2 exciting type)

Fig. 2 Outline of Stepping Motor Operation

~HITACHI
710

Slow-up and slow-down pulse rate are supplied to the
stepping motor every four steps as shown in Fig. 3.

Slow-down pulse
rate area

Operating pulse
rate area

Slow-up pulse rate area
21
20

4 steps

1
....

........................ 5

6

I

o

Starts

7

sl~

Stops slue

Fig. 3 Outputs to the Stepping Motor
(a)

The pulse rate changes every 4 steps for slow-up and
slow-down.

(b)

In case of slow-up area to the operating pulse area, the
pulse rate changes in 21 steps to gradually increase the
slue speed.

(c)

In case of slow-down area to stop, the pulse rate changes
in 7 steps to gradually reduce the slue speed.

(d)

When reverse slue is selected, an additional one-step
rotation, followed by a normal

~ne-step

rotation, is

executed.

~HITACHI
711

9.2

SOFTWARE DESCRIPTION
(1)

Program Module Configuration
The program module configuration for stepping motor control
is shown in Fig. 4.

MAIN
PROGRAM

o

SMCLC

SMREV
GENERATE
STEPPING
MOTOR OUTPUT

PROCESS
DATA

Fig. 4
(2)

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 2.
Table 2

No.

712

Program Module Functions

Program Module Name

Label

0

MAIN PROGRAM

SMMN

Rotates stepping motor.

1

PROCESS DATA

SMCLC

Calculates output data for slow-up,
operating, slow-down and backlash by
supplying total step count.

2

GENERATE STEPPING
MOTOR OUTPUT

SMREV

Supplies pulses to the stepping motor.

Function

~HITACHI

(3)

Program Module Sample Application (Main program)
The flowchart in Fig. 5 is an example of the stepping motor rotation
performed by the program module in Fig. 4.

When the program module

of Fig. 5 is executed, the stepping motor makes 201 reverse
slue, then one normal slue.
Main Program

Initializes each pin of the stepping
motor. PBSM is the RAM for loading
data which is supplied to the stepping
motor at port B at the beginning of
each timer interrupt routine.
-----{ Selects port B as output.
____ -[ Initializes stepping motor start flag.
Specifies timing for output to the
stepping motor in TDR. TDRD(RAM) is the
RAM for loading the timer value to
TDR at the beginning of the timer
interrupt routine.
-----{ Specifies presca1er dividing rate 16.
-----{ Enables interrupt.
_____ { Stores reverse slue data in entry argument.
_____ { Stores 200-step data in entry argument.
-----

l

Determines values for processing of
slow-up, operating, and slow-down,
respectively, from the supplied step
count.

Timer Interrupt Routine

------[outputs to stepping motor.

Fig. 5

Program Module Flowchart

$

HITACHI
713

-. .-.. ----,,--.·-_-·-·.,--___

~_-_-.,_---....."....,...-c-.--_-.

_.

_~_.

_ ..

~_~

__ .

.

..._.-

- - - - - - - -_. __ . ._ - - - - - - -

9.3

I

PROGRAM MODULE DESCRIPTION

PROGRAM MODULE NAME

I

FUNCTION

II
II

II MCU/MPU IIHD6305XO/ YO IILABEL IISMCLC I

PROCESS DATA

Generates data for outputting to the stepping motor by the timer routine.
Sets data for slow-up, operating and slow-down after determining the
backlash requirement.

I

ARGUMENTS

II

CHANGES IN CPU
REGISTERS AND FLAGS
Storage
Location

Contents

FRFLG.
FLGI

1

I

Entry
Total
Step
Count

STEP

Slow-up
data
Operating data

l~i~:-dOwn

SUP
SHOLD
SOON
STEPE

Re- Il{ema~nder
turns of step
Norma~~
FRFLG.
Reverse
slue
FLGI
flag
Slue
start flag SMSF. FLG1

I

DESCRIPTION

:
x :
:

t

Norma1/
Reverse
slue
flag

Arguments

•

Byte
Lgth.

Not affected
Undefined
Result

ACCA
x

II

ROM (Bytes)
140
RAM (Bytes)

IX

I

x

SPECIFICATIONS

I

9

Stack (Bytes)
2

1

C

Z

No. of cycles

x

x

1

N

I

333
Reentrant

1
1

x

1

H

•

x

1
1

No
Relocation
No
Interrupt
Yes

I

(1) Function Details

(a) Argument details
FLGl(RAM) : Holds flag indicating slue direction and start of stepping
motor rotation. Flag functions are shown in Table 3.
STEP (RAM) : Holds total step count.
: Contains slow-up data.
SUP (RAM)
SHOLD(RAM) : Contains operating data.
SDWN(RAM) : Contains slow-down data.
STEPE(RAM) : Contains remainder of total step count divided by 4.

I

SPECIFICATIONS NOTES

I

"No. of cycles" in "SPECIFICATIONS" represents the number of
cycles required to execute data in the sample application.

~HITACHI
714

I

I PROGRAM MODULE NAME

I

DESCRIPTION

II
II
I I
II~========~==~====~==~~
PROCESS DATA

Table 3

Flag Functions

Bit/Label
Labe 1 ~S:=:MS':-:F=-=r=::F=RF=-LG7"""i
1

FLGI

o

o

1

MCU/MPU IIHD6305XO/YO II LABEL EMCLC

Function
Rotates stepping motor clockwise (normal).
Rotates stepping motor counterclockwise (reverse).
Stops slue.
Starts slue.

(b) Fig. 6 shows an example of

t

b7
FLGI
bO
program module SMCLC
(j) Entry
FLGl(RAM) 1- 1-1-1-1-1-1-1 0 I
execution.
If entry arguments are held
arguments (Reverse=O)
b7 SI'EPbO
as shown in part  (STEP)

-----[Stores data not to output operating data.

_____ [ Stores SDWNW(RAM) value as slow-down
data.

Stores STEP(RAM)-(SDWNW(RAM)+I+SHOLD
(RAM» as slow-up data.

_____[Stores normal or reverse slue data for
the stepping motor.
-----[ Clears the slow-up data table pointer.
_____[sets the flag for the/stepping motor
output.

~HITACHI
720

I

PROGRAM MODULE NAME
I

I

I
FUNCTION

GENERATE STEPPING
MOTOR OUTPUT

I

J

I MCU/MPU I IHD630SXO/ YO I LABEL IISMREV

I

I

Outputs pulse to the stepping motor.

I

ARGUMENTS

I

CHANGES IN CPU
REGISTERS AND FLAGS
Storage
Location

Contents

Byte
Lgth.

•
t

~1(t'~-up

SUP

1

Operat1ng
data

SHOLD
SDWN

1

I~~~~-down

Remainder
Entry of
the
step
Normal{
Reverse
slue flag
S.~ue start
Arguflag
ments

Re- Slue
turns start
flag

1

STEPE

1

FRFLG.
FLGI
SMSF.
FLGI

1

SMSF,
FLGI

1

1

:

II

Not affected

ROM (Bytes)

x : Undefined
: Result

I

x

105
RAM (Bytes)

IX

ACCA

I

SPECIFICATIONS

x

I

6
Stack (Bytes)
2

C

Z

x

x

N

I

x

•

H

•

No. of cycles
76
Reentrant
No
Relocation
No
Interrupt
No

I

DESCRIPTION

I

( 1) Function Details

(a) Argument details

FLGI (RAM) : Holds flag indicating rotation direction and rotation start
of the stepping motor. Flag functions are shown in Table 5.
STEP (RAM) ; Holds total slue step count.
SUP (RAM) : Holds slow-up data.
SHOLD (RAM): Holds operating data.
SDWN (RAM) : Holds slow-down data.
STEPE (RAM): Holds remainder of the total step count divided by 4.

I SPECIFICATIONS NOTES I

"No. of cycles" in "SPECIFICATIONS" represents the number
of cy cles req ui red to execute with data in the sample
application.

~HITACHI
721

I

I

PROGRAM MODULE NAME

I

DESCRIPTION

II
II

GENERATE STEPPING
MOTOR OUTPUT

Table 5
Label

Flag Functions

Bit/Label
SMSF
FRFLG

-

FLGI

1
0

0

Function
Rotates stepping motor clockwise (normal).
Rotates stepping motor counterclockwise (reverse).
Stops slue.
Starts slue.

-

1

II MCU/MPU IIHD6305XO/ YO II LABEL IISMREV I

(b) Fig. 7 shows an example of
program module SMREV
execution.
If the entry argument is
held as shown in part  of Fig. 7.
(c) Program module SMREV calls
other program modules and
subroutines shown in
Table 6.

b7 SUP bO
SUP (RAM)
($15)
SHOLD
SHOLD (RAM) [[:::::IJ
Entry
($07)
SDWN
arguments
SDWN (RAM) o::::TI
($15)
STEPE
STEPE (RAM) C2::::TI
~~Ol)
FLG 1
FLCI l- J - I - I - I - I - I 1
(RAM)
~
SMSF (Bit 1)
slue start (=1)
FRFLG (Bit 0)
Reverse slue (=0)

rr::I1

*
*
:STEP(TOTAL STEP COUNT)
*
*
RETURNS :SUP(SLOW-UP DATA)
*
*
SHOLD(OPERATING DATA)
*
*
SDWN(SLOW-DOWN DATA)
*
*
STEPE(REMAINDER OF STEP)
*
*
FRFLG(FORE/REVERSE SLUE FLAG)
*
*
SMSF(SLUE START FLAG )
*
*
*
*
************************************************
1021 00 88 02 SMCLC 8RSET FRFLG.FLG1.SMCL1 Fore or reverse sLue
1024 3C 82
INC
STEP
If reverse increment STEP
1026 86 82
SMCLl LOA
STEP
Load Lower 2 bit
1028 A4 03
tI$03
AND
102A 87 86
STA
STEPE
102C 34 82
Store 1/4 times of STEP
LSR
STEP
102E 34 82
LSR
STEP
1030 86 82
Te5t if STEP=O ?
LOA
STEP
BEQ
1032 27 3C
8ranch if STEP=O
SMCL5
1034 AE 04
LOX
1'*4
Initialize 4 steps counter
1036 8F 87
STX
SCNTR
1038 Al 01
til
Test If STEP=l?
CMP
BEQ
103A 27 3A
SMCL6
Branch If STEP=l
103C Al 02
CMP
1=12
Test if STEP=2?
BEQ
103E 27 3A
SMCL7
Branch If STEP=2
1040 3F 8A
CLR
SDWNW
Initialize work area
1042 A6 02
LOA
1=12
1044 87 89
STA
STEPW
1046 3C 8A
SMCL2 INC
SO WNW
Increment sLow-down work
1048 A6 04
Add slow-up work
LOA
tl4
104A 88 89
ADD
STEPW
104C 87 89
STA
STEPW
104E Al IE
CMP
1=130
Test if STEPW=)30?
Branch STEPW=)30
1050 24 33
8HS
SMCL9
1052 81 82
CMP
Test if STEPW=STEP?
STEP
8EQ
1054 27 3F
SMCL10
8ranch STEPW=STEP
1056 25 EE
BLO
Test if STEPW of
Fig. 5. key data is stored in key
buffer as shown in part (2) of Fig. 5.
(c) Program.module KEYIN calls neither
program modules nor subroutines.
SPECIFICATIONS NOTES

1/

~HITACHI
738

(1) Before

execution

Press
A key

[B)

b7
PS($OO) I

o :

PS

bO

I
PE($OO) I o : o I
0

fl1i

DITB~~
**
I

I
\,.

**

•

I

I PROGRAM MODULE NAME II

RECEIVE KEY DATA

II MCU/MPU I HD630SXO/YO I LABEL IIKEYIN I

I~==========~==~====~==~~

DESCRIPTION

b7 PS bO
PS($OO) 0; 0

(2) User Notes
(2) Result

(a) Clears RAM since 2-byte RAM is
used as pointer indicating key
buffer.

I E I
PE($OI) I 0 : I I
KEYBUF ~l
* .,.
I

I

(b) Selects DDR of port B as input.

**

(c) Clears INT2 interrupt mask bit.

**: hexadecimal

(d) Clears bit I to enable INT2 interrupt.

Fig. 5

Example of KEYIN
Execution

(3) RAM Description
Label
b7

PS
PE
KEYBUF

Description

RAM

bO

~t

dl
j

l

Stores pointer indicating unprocessed key
data in key buffer.
Stores pointer indicating key data in key
buffer.
Used as key buffer storing IS-byte key data.

(4) Sample Application

Program module KEYIN is called if ASCII key is pressed after RAM to be used
is cleard, INT2 interrupt is enabled, and after I/O port is selected and
interrupt is enabled.
I

I
I

CLR
STA
STA
STA
STA
CLI

A

PS
PE
MR

PBDDR

}-----

Clears RAM to be used.
Clears INT2 interrupt mask.
Selects port B as input.
Enables interrupt.

I

~HITACHI
739
--------~.

I

PROGRAM MODULE NAME

II

RECEIVE KEY DATA

II MCU/MPU I HD6305XO/YO I LABEL IIKEYIN I

I~==========~========~==~~

DESCRIPTION
(5) Basic Operation

(a) Input/output to/from key buffer.
(i)

Calls program module KEYIN at every INT2 interrupt and fetches key
data from key buffer. Then, calls program module KEYIN in main
program and fetches key data from key buffer.

(ii)

Clears starting point PS(RAM) and ending point PE(RAM) and stores
key data in key buffer starting address.

(iii) Program module KEYIN stores 1 byte of key data in 16-byte buffer
area pointed by PE(RAM) , and increments PE(RAM).
(iv)

Program module KEYOUT fetches 1 byte from l6-byte buffer area
pointed by PS(RAM) and increments PS(RAM).

(v)

PS(RAM) and PE(RAM) become "0" i f they are incremented till 15
bytes because the buffer area is l6-byte long.

(b) Input to key buffer
(i)

Program module KEY IN loads PE(RAM) into ACCA and increments ACCA.
Then, compares ACCA content with PS(RAM). If (ACCA)=PS(RAM), key
data is not stored in key buffer.
If (ACCA) ~ (PS), key data is stored in key buffer and PE(RAM) is
incremented.

(ii) Key buffer can be used up to 15 bytes.

~HITACHI
740

PROGRAM MODULE NAME
FLOWCHART

II
II
I
I II I
I~==========~==~====~==~~
RECEIVE KEY DATA

MCU/MPU

HD6305XO/YO

LABEL

KEYIN

'--_-.._---' ----{ Clears INT2 interrupt request flag.

----{ Loads key buffer pointer into IX.

'----..----'

----

Increments key buffer pointer.

(ACCA)=(PS)

=-_...,..._....;.;.0 ----{ Stores key data in key buffer.

----

Increments key buffer pointer.

I
~HITACHI
741

I
I

PROGRAM MODULE

NAME

II

FUNCTION

II MCU/MPU I~HD6305XO/Y~ ILABEL IrYOUTI

READ KEY DATA

II

Reads data from key buffer.

I

II

ARGUMENTS

CHANGES IN CPU
REGISTERS AND FLAGS
Storage
Location

Contents

•

Byte
Lgth.

: Not affected

ACCA

-

-

-

I

20
RAM (Bytes)

IX

I

x

x

SPECIFICATIONS

ROM (Bytes)

Undefined
: Result

x :

t
Entry

JI

I

18

Stack (Bytes)
0

Arguments

Returns

I

Unprocessed
key data
Unprocessed
key data
existence

DESCRIPTION

IX

Bit C
(CCR)

1

1

C

Z

t

x

27

N

I

Reentrant

x

•

No

No. of cycles

H

Relocation

•

Interrupt

No
Yes

I

b7 PS hO
PS(RAM)I 0 : 1
($01)
PE
PE(RAM)I
o: 3
($03)
47
K~YBUE
Before
40
~
execution
PS
30
32
PEr

(1) Function Details

J
I

(a) Argument details

 Return

DESCRIPTION
BitC = 1: No unprocessed data is
in key buffer.

1

BitC b7 IX bO
arguments IX
4 : 0
($40)
Fig. 6 Example of KEYOUT
Execution

loll

I

(b) Fig. 6 shows an example of program module KEYOUT execution.
Unprocessed data is contained into IX after
program module KEYOUT execution.
(c) Program module KEYOUT calls neither program modules nor subroutine.
(2) User Notes
Program module KEYOUT should be used with program module KEYIN.
(3) RAM Description
Label

RAM
bO

b7
PS
PE
KEYBUF

Description
} Stores pointer indicating unprocessed data in
} key buffer.
Stores pointer indicating key data in key buffer.

~: tU,ed ., key buffer "oring 15 byte key data.

fI-

.-t

j

(4) Sample Application
First, clears RAM to be used, enables INT2 interrupt, and initializes I/O
port. Second, enables interrupt and executes program module KEYIN. Then,
execute program module KEYOUT.

.

RMB

WORK1

1

I

Reserves memory byte for key buffer unprocessed
data .

I

0

LOOP

CLR
A
STA
PS
}-Clears RAM to be used.
STA
PE
MR
---Enables INT2 interrupt.
STA
STA
PBDDR ---Selects port B as input.
CLI
---Enables interrupt.
n----------K-E-Y-0-U-T--"II--Ca1ls
program module KEYOUT.
JSR

II

BCS
STX

LOOP
WORK1

---Tests if unprocessed data is in key buffer.
---Stores unprocessed data in return argument in
RAM.

~HITACHI
743

PROGRAM MODULE NAME

II

READ KEY DATA

II MCU/MPU I HD6305XO/YO ILABEL IB

I~==========~==~====~==~~

DESCRIPTION
(5) Basic Operation

(a) Input/output to/from key buffer.
See (a) of (5) Basic operation in program module KEYIN for details.
(b) Output from key buffer.
(i)
(ii)

Program module KEYOUT tests if values in starting pointer PS(RAM)
and values in ending pointer PE(RAM) are equal.
In case of PS(RAM)=PE(RAM), no key data is in key buffer and
bit C is set.

(iii) In case of PS(RAM)~PE(RAM), key data is fetched from key
buffer PS(RAM) indicates, and PS(RAM) is incremented.

~HITACHI
744

PROGRAM MODULE NAME
FLOWCHART

II

READ KEY DATA

II

MCU/MPU

I

HD6305XO/YO I LABEL IIKEYOUl

I~==========~========~==~~

~__~____~

----[Loads starting pointer into IX.
is in key

~

__ __-=...
~

~__~~~~

____[stores key buffer content in return
argument.

---- Increments starting pointer.

____ [Clears bit C, because unprocessed data
is in key buffer.
Sets bit C, because no unprocessed
---- [ data is in key buffer.
KEYOT2

I
~HITACHI
745

10.4

SUBROUTINE DESCRIPTION
This application example calls no subroutines.

10.5

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
0003S
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055

746

PROGRAM LISTING

*
*
*
PS

****

OOSO
0080
OOSl
00S2
0092

0001
0001
0010
0001

ORG

RMB
PE
RMB
I Return

argument

SCISOK(RAM)=l: Data is received
from master system.

I

SPECIFICATIONS NOTES

752

I

t

Bit 0

~

[SCIRDA
I-byte data
('C'=$43)

t

Bit 7
b7SCIRDA bO
4 : 3

I

SCISOK
SCISOK(RAM)
0 : 1
($01)
Example of SCISRD Execution

I

Fig. 5

I

I

"No. of cycles" in "SPECIFICATIONS" represents the number
of cycles are needed when having no wait time for receiving
data.

~HITACHI

I

PROGRAM MODULE NAME

II

SCI SLAVE RECEIVE

II

MCU/MPU

I

HD6305XO/YO

I

LABEL

I~

I~========~==~~====~~~

DESCRIPTION

SCISOK(RAM)=O: No data is received
from master system.
(b) Program module SCISRD execution
stores contents of SCI data
register in SCIRDA (RAM).
(c) SCISRD calls neither program
modules nor subroutines.
(2) User Notes
(a) Initializes SCR.
(b) When program module SCISRD is used, resetting system (in case of power on
reset, supplying power) should be performed from master system.
(c) Program module SCISRD should be called before master system begins
to send data.
(d) Program module SCISRD loops until sending data from master system is
completed.
(3) RAM Description
Label

RAM

SClRDA
SCISOK

Description
bO }

I}

Stores received data.
Stores existence of received data.

(4) Sample Application
Program module SCISRD is called if SDR is dummy-read, bit I is
cleared, data is received after I/O port is designated and SCR
and SSR are initialized.
LDA
STA
STA

LO<1P

LDA
STA
LDA
STA
LDA
CLl
BRCLR
LDA
BCLR

11$10
PCDTR
PCDDR

}- -

II$FO

}- - - - }-

SCR
11$18
SSR
SDR

- - -

- ---

Sets port C bit 4 to High.
Sets transfer rate and selects internal
clock source.
Enables SCI interrupt.

- -- -- ----

Dummy-reads and clears SDR.
Enables interrupt.
O,SCISOK,LOOP - -- Waits for receive completion.
SCIRDA - - - - - - Loads received data into ACCA.
O,SCISOK- - ,- - - - Clears flag indicating receive completion

(5) Basic Operation
(a) Receives serial data using SCI interrupt routine.
(b) SCI interrupt routine is generated at serial data transfer/receive.
(c) If SCI interrupt is generated after serial data is transferred, either
transfer or receive is decided by considering CK request signal being
out ut.

~HITACHI
753

PROGRAM MODULE NAME
FLOWCHART

II

II

SCI SLAVE RECEIVE

MCU/MPU

I HD6305XO/YO

I

LABEL

I~==========~==~====~==~~

____{ Tests whether transfer or receive
completion.
4,PCDTR)=1
----{ Releases CK request signal.

L..-'-';'-=T=':':"'...J - - - - { Stores

L..-_--.._ _...J - - - - { Sets

received data in SCIRDA(RAM).

flag indicating data receive.

L..-_-r-_...J - - - - { Clears

SCI interrupt request flag.

~HITACHI
754

IISCISRDI

I
I

PROGRAM MODULE NAME

II

FUNCTION

I

II MCU/MPU I IHD6305XO/YO I I LABEL IISCISTDI

SCI SLAVE TRANSFER

Sends data of ACCA to master system.

I

I

ARGUMENTS

CHANGES IN CPU
REGISTERS AND FLAGS
Storage
Location

Contents

•

Byte
Lgth.

:
x :
:

t

Not affected
Undefined
Result

ACCA
Entry Data to
be sent

ACCA

I

1

II

5
RAM (Bytes)

• I

I

I

ROM (Bytes)

IX

x

SPECIFICATIONS

0
Stack (Bytes)
0

Arguments

Returns

-

-

-

C

Z

•

x

13

N

I

Reentrant

x

•

No

No . of cycles

H

Relocation

•

No
Interrupt
Yes

I

DESCRIPTION

I

Q) Entry
{ACCA
b7 ACCA bO
3 I
argument 1-byte datal 4
('C'=$43)
~ bO
b7
SCI data
SDR I 4
3 I
register

:

(1) Function Details

:

(a) Argument details
ACCA: Holds data to be sent to
master system.

(2) Result

(b) Program module SCISTD execution
transfers contents of ACCA to
SDR and sends them to master.
(c) SCISTD calls neither program
modules nor subroutines.

I

SPECIFICATIONS NOTES

I

CKP~
Tx

~~ I I I I I
o

+

rLt

Bit 0
Bit 7
Fig. 6 Example of SCISTD
Execution

"No. of cycles" in "SPECIFICATIONS" represents number of
cycles needed when having no wait time for transfer
completion.

~HITACHI
755

PROGRAM MODULE NAME

SCI SLAVE TRANSFER

II.

II MCU/MPU I HD6305XO/YO I LABEL IISCIST4

I

DESCRIPTION
(2) User Notes

(a) Selects bit 4 of port C as output.
(b) Initialize SCI.
(3) RAM Description
RAM is not used by program module SCISTD.
(4) Sample Application

Call SCISTD after selecting I/O port, initializing SCR and SSR and storing
data to be sent.
WORKI

RMB

1

--

- --

}

--

I

Reserves memory byte for loading
data to be sent in user program.

I
I

LDA
STA
STA
LDA
STA
LDA
STA
LDA

II

JSR
I

11$10

PCDTR
PCDDR

- -

II$FO

}---}- - --

SCR
11$18

SSR
WORKI
SCISTD

} ---II

Sets port C bit 4 to High.
Selects external clock source.
Clears SCI interrupt request flag.
Loads data to be sent into entry argument.
Calls program module SCISTD.

(5) Basic Operation
Loads data to be sent into SDR and outputs CK request Signal.

~HITACHI
756

PROGRAM MODULE NAME
FLOWCHART

II

SCI SLAVE TRANSFER

II

MCU/MPU

I

HD6305XO/YO I LABEL IISCIST1

I~==========~========~==~~

L..-_-.-_---' ----{ Loads data to be sent into SDR.
L..-_-.-_---' ----{ Outputs CK request signal to master system.

I
~HITACHI
757

11.4

SUBROUTINE DESCRIPTION
This application example calls no subroutines.

11.5

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00d43
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055

PROGRAM LISTING

*
*
*
SCIRDA

****
0080
0080 0001
0081 0001

ORG

*

Received data
Existence of received data

SYMBOL DEFINITIONS

*
PCDTR
PCDDR
SCR
SSR
SDR

EQU
EQU
EQU
EQU
EQU

$02
$06
$10
$11
$12

********************

Port C data register
Port C data direction register
SCI contoroL register
SCI status register
SCI data register

************************************************

*

*
*
*
************************************************
MAIN PROGRAM : SCISMN

*
*

1000
1000
1002
1004
1006
1007
1009
100B
100D
100F
1011
1013
1014
1017
1019
101B
101E
1021

A6
B7
B7
4F
B7
A6
B7
A6
B7
B6
9A
01
B6
11
CD
CD
20

10
02
06

*
*
SCISMN

ORG

LDA
STA
STA
CLR
81
STA
FO
LDA
10
STA
18
LDA
11
STA
12
LDA
CLI
81 FD SCISM1 BRCLR
80
LDA
81
BCLR
103A
JSR
1035
JSR
Fl
BRA

$1000
!tUO
PCDTR
PCDDR
A

SCISOI<
!t$FO
SCR
!t$18
SSR
SDR

InitiaLize port C
SeLect port C bit 4 as output
InitiaLize SCISOI<
InitiaLize SCR
InitiaLize SSR

Dummy read of SDR
EnabLe interrupt
O.SCISOI<.SCISMl Test if received data
SCIRDA
Load received data
O.SCISOK Crear received data fLag
TPR
Convert into Lowercase
SCISTD
Output data to master
SCISM1

************************************************

*
*
*
************************************************
**
**
ENTRY
NOTHING
*
RETURNS
SCIRDA (RECEIVED DATA)
*
*
SCISOI< (SCISOK=l;TRUE.
*
*
SCISOI<=O;FALSE)
*
*
*
************************************************
*
*
*

NAME : SCISRD (SCI SLAVE RECEIVE)

1023 09 02 08 SCISRD BRCLR
1026 B6 12
LDA
1028 B7 80
STA

4.PCDTR.SCSRD1 Test if Tx or Rx
SDR
Store received data
SCIRDA

~HITACHI
758

************************

$80

RMB
SCISOI< RMB

****
0002
0006
0010
0011
0012

RAM ALLOCATION

00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100

102A
102C
102E
1030
1032
1034

10
20
18
A6
B7
80

81
02
02
38
11

BSET
BRA
SCSRD1 BSET
SCSRD2 LDA
STA
RTI

O.SCISOI<
SCSRD2
4.PCDTR
1t$38
SSR

Set received data fLag
Branch SCSRD2
Set CI<=l
CLear interrupt request flag

************************************************

*
*
**************************************************
*
*

1035 B7 12
1037 19 02
1039 81

103A
103C
103E
1040
1042
1044

Al
25
Al
22
A4

61
06
7A
02
DF

81

NAME : SCISTD (SCI SLAVE TRNSFER)

*
*
(DATA TO BE SENT)
ENTRY
ACCA
*
*
NOTHING
RETURNS
*
*
*
*
************************************************
SCISTD STA
BCLR
RTS

SDR
4.PCDTR

Store transfer data
Set CI(-pin=O

************************************************
*
*
*
* NAME : TPR (CONVERTING ASCII LOWERCASE
INTO ASCII)
*
*
*
*
************************************************
TPR

TPR1

CMP
BCS
CMP
BHI
AND
RTS

It'a
TPR1
It'z
TPR1
It$DF

ACCA - 'a' ?
Branch if ACCA ( , a'
ACCA - , z' ?
Branch if ACCA > ' z'
Convert Lowercase to Upper'case

************************************************

*
*

VECTOR ADDRESSES

*
*

*

*
************************************************
1FF6
1FF6
IFF8
1FFA
IFFC
IFFE

1023
1000
1000
1000
1000

*
*

ORG

$lFF6

FDB
FOB
FDB
FDB
FDB
END

SCISRD
SCISMN
SCISMN
SCISMN
SCISMN

SCIITIMER2
TIMERIINT2
INT
SWI
RES

~HITACHI
759

12.

SCI CLOCK SYNCHRONOUS (INTERNAL CLOCK)

12.1

HARDWARE DESCRIPTION
(1) Function
(a)

Transfers clock synchronous serial data to slave system,
and receives data from slave.

(b)

Handshakes using transfer/receive control signal to
transfer or receive data.

(2)

Microcomputer Applications
(a)

Transfers data to/from slave system using clock synchronous SCI.

(b)

Inputs CK request signal to bit 3 of port C from slave
system.

Outputs transfer rate clock to slave system

considering input state and receives data.
(c)

Outputs transfer request signal from bit 4 of port C to
inform data transfer to slave system.

(3)

Circuit Diagram

MCU
HD6305XO
(HD6305YO)

2 RES

7NUM

1

VSS

I

I
I
IL _____ JI

Fig. 1

Clock Synchronous SCI Circuit

~HITACHI
760

(4)

Pin Functions
Pin functions at the interface between the HD6305XO SCI pins and
slave system are shown in Table 1.
Table I

Pin Name
(HD6305XO)
CK

Input/
Output
Output

Active
Level
(High
or Low)
Low

Pin Functions

Function

Pin Name
(Slave
system)

Outputs transfer clock.

Serial
clock

Program
Lavel

/
~

Rx

Input

-

Receives data.

Serial
data
output

Tx

Output

-

Transfers data.

Serial
data
input

Low

Inputs transfer clock
request from slave.
Outputs clock if low.

CK
request
signal

Low

Informs transfer start
to slave.

Transfer
request
signal

C3

Input

Output

C4
(5)

L

PCDTR

Hardware Operation
SCI timing chart is shown in Fig. 2.

Transfer

, - - Loads data to be sent into SDR

request~

Transfer(C4)
signal

L_______ ________________________________
~

r--

~

Tx

I

slave sends data

Receive
CK request
(C3)

CK
Rx

Receive data
latch timing
Fig. 2

SCI Timing Chart

~HITACHI
761

12.2

SOFTWARE DESCRIPTION
(1)

Program Module Configuration
The program module configuration for serial communication with
slave system is shown in Fig. 3.
SCIMMN
MAIN
PROGRAM

,.:;S~C:.:;I:.:MRD:="'-'-_-r-~

SCIMTD

Fig. 3

(2)

o

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table ·2.
Table 2 Program Module Functions

No.

Program Module Name

Label

Function

0

MAIN PROGRAM

SCIMMN

Sends data to slave syStem and receive it
from slave system without change by using
the HD630SXO SCI.

1

SCI MASTER TRANSFER

SCIMTD

Sends serial data to slave system using
internal clock.

2

SCI MASTER RECEIVE

SCIMRD

Receives data from slave system using
internal clock.

~HITACHI
762

(3)

Program Module Sample Application (Main Program)
The flowchart in Fig. 4 is an example of sending serial data to
slave system and receiving it from slave system, performed by the
program module in Fig. 3.

Main Program

~==~====~ ----I

Seta tran,'er reque,t aignal to High.

-----[lnitializes SClMOK(RAM)
l.-_......-_--J

.---~;:;:;:;:r-....J

____{lnitializes serial clock transfer rate
and selects internal clock source .
Stores data in entry argument of
----{ program module SClMTD.

=:::c:::::~
~~~;;~____~

____ {Calls program module SClMTD and
transfer data to slave system.
{

Calis program module SClMRD and
receives data from slave system.

{

Tests i f data is received from
slave system.

Bit

(Bit C)=O
if received data equals sent data.

Fig. 4

Program Module Flowchart

~HITACHI
763

12.3

PROGRAM MODULE DESCRIPTION

=MA=S=TE=R=T=RAN=S=F=E=R==I~I=M=C=U=/=MP=U=H~H=D=6=3=0=5X=0=/=Y=0~11L=A=B=E=L~I~IS=C=IMT==:1

=P=RO=G=RAM==M=O=D=U=L=E=NAME=:::::II;:=S=C=I

::1

I

FUNCTION

I

Sends data in SCITDA(RAM) into slave system using internal clock.
ARGUMENTS

CHANGES IN CPU
REGISTERS AND FLAGS
Storage
Location

Contents

II

•

Byte
Lgth.

: Not affected
x : Undefined
: Result

ROM (Bytes)

t

ACCA
SCITDA
(RAM)

Entry Data to
be sent

1

I

x

C
Argumentsr----+--------r--------+-----;

I

x

•N

2
Stack (Bytes)
0
No. of cycles

Z

x

50

I

Reentrant

•

x

Returns

48
RAM (Bytes)

IX

I

H

I

SPECIFICATION

•

No
Relocation
No
Interrupt
Yes

DESCRIPTION

CD Entry

{
argument

(1) Function Details
(a) Argument details

,

3

:

3

b7 ScrTDA bO

SCITDA
(RAM)
('C'=$43)
SCI data

I

4

b7

I

:

SDR
4

I

bO

I

SCITDA(RAM): Holds data to be sent
to slave system.
(b) Program module SCIMTD execution
loads entry argument content
CZ> Output
into SDR and sends it to slave
system.
(c) Program module SCIMTD calls
Bit 7
Bit 0
neither program modules nor
Fig. 5 Example of SCIMTD Execution
subroutines.
SPECIFICATIONS NOTES

II

~HITACHI
764

PROGRAM MODULE NAME

II

DESCRIPTION

I

SCI MASTER TRANSFER

IB

HD6305XO/YO

88

(2) User Notes
(a) Initializes SCR.
(b) When using program module SCIMTD, resetting system (in case of power on
reset, activating power) is performed master reset firstly, then reset
slave system secondly.
(c) Sets slave to receiving state before program module SCIMTD execution.
(d) Program module SCIMTD loops until sending data is completed.
(3) RAM Description

RAM

Label

Description
Stores data to be sent.

SCITDA
SCIMOK

Indicates data.

(4) Sample Application
Calls program module SCIMTD after selecting I/O port, loading data to be
sent and initializing SCR.
I

I

LDA
STA
STA
LDA
STA
LDA
STA

II JSR

11$10
PCDTR
PCDDR

}----

II$E3

}- --}-- --

SCR
11$41
SClTDA
SCIMTD

II

Sets bit 4 of port C to High.
Selects internal clock source.
Loads data to be sent into entry argument.
Calls program module SCIMTD.

(5) Basic Operation
(a) When transfer request signal is output, CK request signal may output
from slave system with the same timing. Then, l2~s software timer is
executed and CK request signal is tested after CK request signal is
output.

I

(b) Transfers received serial data if CK request signal is output.
(c) Goes to the next step after SCI interrupt request flag is set and
transfer/receive completes.
(d) When serial data is received, retains transfer request in output state
until main program processes received data so that next data can not be
received.

~HITACHI
765

PROGRAM MODULE NAME .11 SCI MASTER TRANSFER
FLOWCHART

II MCU/MPU 1 HD6305XO/YO

I LABEL 1FCIMTDI

~==~==~==~====~~~
__ {sendS transfer request signal to slave
system.

Executes l2lJs software timer.

data to be sent.

flag.
__ {DUmmy-readS SDR and places SCI in
receive possible state.

--{ Tests SCI interrupt request flag.

--{ Selects external SCI clock source.
--{ Stores serial data in return argument.
--{ Selects internal SCI clock source.
--{ Sets flag indicating data receive.
is received during

--{ Releases transfer

rE!que~t

signal.

--{ Clears flag indicating data receive.

$HITACHI
766

I

I

II SCI MASTER RECEIVE
II MCU/MPU IIHD6305xo/yoJ LABEL IISCIMRDI
~========~====~==~==~~

PROGRAM MODULE NAME

I

I

FUNCTION

(1) Outputs serial clock and receives data from slave system.
(2) Permits outputting when slave system cannot output serial clock.

I

I

ARGUMENTS

Storage
Location

Contents

CHANGES IN CPU
REGISTERS AND FLAGS

I

I

•

Byte
Lgth.

: Not affected
x : Undefined
: Result

-

-

Entry

-

I

x

36
RAM (Bytes)

IX

I

I

ROM (Bytes)

t

ACCA

SPECIFICATIONS

I

x

0
Stack (Bytes)
0

Arguments
Received
data

ACCA

Returns ExistenCE
of
received
data

1

C

Z

•

x

N

I

x

•

H
Bit C
(CCR)

1

No • of cycles
43
Reentrant
No
Relocation

•

No
Interrupt
Yes

DESCRIPTION

CK

(J) Input

In

(1) Function Details
(a) Argument details
ACCA: Contains data received
from slave.
Bit C(CCR): Indicates existence
of received data.
Bit C

=

1 : No data is received
from slave system.

Bit C

=

0 : Data is received
from slave system.

SPECIFICATIONS NOTES

II

p~

Rx

nnnnnnnr

UUUUUUUU

:0]
I I I I I rL
o ~
•
Bit 0

1

Bit 7

Bit C b7 ACCA bO
(]) Return { ACCA @] I 4 : 3 I
argument ('C'-$43)
Fig. 6

Example of SCIMRD
Execution

~HITACHI
767

I

II

PROGRAM MODULE NAME

SCI MASTER RECEIVE

B

II MCU/MPU I HD6305XO/YO ILABEL I

I~==========~========~==~~

DESCRIPTION

(b) Program module SCIMRD execution contains SDR contents in return
argument ACCA.
(c) Program module SCIMRD calls neither program modules nor subroutines.
(2) User Notes
(a) Initializes SCR.
(b) When program module SCIMRD is executed, set bit 3 and bit 4 of data
register port C to "1".
(c) Goes to transfer possible state in slave system before program module
SCIMRD execution.
(d) Program module SCIMRD loops until receiving data from slave system is
completed.
(3) RAM Description
RAM is not used by program module SCIMRD
(4) Sample Application
Calls

progra~

module SCIMRD after selecting I/O port and initializing SCR.

I
I

LDA
STA
STA
LDA
STA
LOOP

II JSR
BCS

11$30

PCDTR
PCDDR

}--- Sets bit 3 and bit 4 of port C to High.

II$E3

} ---Selects internal clock source.

SCR
SCIMRD
LOOP

II ---Calls program module SCIMRD.
---Tests receive completion.

I

I

I

(5) Basic Operation
(a) Checks transfer request signal to test if data is received after
outputting the signal.
(b) Tests if CK request signal has been output from slave system.
(c) If output, sets SCI interrupt request flag, and stores serial data in
return argument after checking that serial data is received.

~HITACHI
768

PROGRAM MODULE NAME

II

SCI MASTER RECEIVE

II

MCU/MPU

I

HD6305XO/YO

I

LABEL IISCIM,

I~==========~==~====~==~~

FLOWCHART

_____{Tests if data has been received during
program module SCIMTD execution.

-----{ Releases transfer request signal.
-----{ Stores serial data in return argument.

-----[Tests CK request signal from slave system.

-----

{

Disables SCI interrupt and clears SCI
interrupt request flag.

Dummy-reads SDR and mades SCI receive
----- { possible state.

-----{ Tests SCI interrupt request flag.

-----{ Selects external SCI clock source.
-----{Stores serial data in return argument.
-----{ Selects internal SCI clock source.

SCMRD3
O+Bit C
__ {
~~~----,

I

Stor~s f~ag

indicating serial data
rece1ve 1n return argument.

'----r----J

~HITACHI
769

12.4

SUBROUTINE DESCRIPTION
This application example calls no subroutines.

12.5

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
0(')044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
770

PROGRAM LISTING

0080
0080 0001
0081 0001
0082 0001

*****
*
*SCIMO/(

RAM ALLOCATION
ORG

RMB
SCIRDA RMB
SCITDA RMB

*

****

************************

$80
1
1
1

Indicate of receiving data
Received data
SCI output data

SYMBOL DEFINITIONS

********************

>I<

0001
0006
0010
0011
0012

PCDTR
PCDDR

sen

SSR
SDR

EQU
EQU
EQU
EQU
EQU

$01
$06
$10
$11

$12

Port C data register
Port C data direction register
SCI controL register
SCI status register
SCI data register

********>1<*>1<*>1<>1<>1<***>1<**>1<>1<***************>1<***>1<*****

1000
1000
1002
1004
1006
1007
1009
100B
100D
100F
1011
1014
1017
1019
101B
10lD

A6
B7
B7
4F
B7
A6
B7
A6
B7
CD
CD
25
A3
26
20

10
01
06
80
E3
10
41
82
1043
101F
FB
41
Fa
FE

*>I<
*
MAIN PROGRAM : SCIMMN
*
*
*
>1<*****************>1<*******>1<>1<*>1<******>1<*>1<*********
*
ORG
$1000
*SCIMMN LDA
1:1$10
InitiaLize port C

STA
STA
CLR
STA
LDA
STA
SCMMN1 LDA
STA
JSR
SCMMN2 JSR
BCS
CPX
BNE
PEND
BRA

PCDTR
PCDDR
A

SCIMOI<
I:1$E3
SCR
1:1$41
SCITDA
SCIMTD
SCIMRD
SCMMN2
1:1$41
SCMMN1
PEND

SeLect port C bit 4 as output
InitiaLize SCIMOK
InltlaL Ize SCR
Store output data
Output SCI data
Receive SCI data
Loop untiL receive data
Test if Tx data=Rx data?
Branch if not equaL
End of program

**>1<***********>1<******>1<***>1<*****>1<****************

**
**
NAME: SCIMRD (SCI MASTER RECEIVE)
*
*
********>1<*******>1<*******************************

101F
1022
1025
1027
1029

09
06
A6
B7
B6

**
**
ENTRY
NOTHING
*
RETURNS
ACCA (RECEIVED DATA)
*
*
CARRY (C=O;TRUE.C=l;FALSE)
*
*
*
************************************************

01 18 SCIMRD BRCLR
01 1C
BRSET
38
LDA
11
STA
12
LDA

4.PCDTR.SCMRD1 Branch if Rx=O
3.PCDTR.SCMRD4 Branch If CK=O
1:1$38
InitiaLize SSR
SSR
SDR
Execute dummy read

~HITACHI

00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104

102B
102E
1030
1032
1034
1036
1038
103A
103C
103E
103F
1041
1042

OF
A6
B7
B6
AE
BF
20
18
B6
98
20
99
81

11 FD SCMRD2 BRCLR
LOA
F3
STA
10
LOA
12
E3
LOX
STX
10
BRA
04
01
SCMRD1 BSET
81
LOA
SCMRD3 CLC
BRA
01
SCMRD4 SEC
SCMRD5 RTS

************************************************

**

**
*
*
************************************************
**
ENTRY : SCITOA (TRANSFER DATA)
**
*
RETURNS: NOTHING
*
*
*
1043
1045
1047
1048
104A
104C
104E
1051
1053
1055
1058
1058
1050
105F
1060
1062
1065
1067
1069
106B
1060
106F
1071
1073

19
AE
SA
26
A6
B7
07
B6
B7
OF
00
18
11
81
BE
OF
A6
B7
B6
B7
A6
B7
10
20

01
02
FD
38
11
01 OF
82
12
11 FD
80 02
01
80
12
11 FD
F3
10
12
81
E3
10
80
02

NAME: SCIMTO (SCI MASTER TRANSFER)

************************************************

SCIMTD BCLR
LOX
SCMT01 DEC
BNE
LOA
STA
BRCLR
LOA
STA
SCMTD4 BRCLR
BRSET
BSET
SCMTD5 BCLR
RTS
SCMTD2 LOX
SCMTD3 BRCLR
LOA
STA
LOA
STA
LOA
STA
BSET
BRA

4,PCOTR Set request Low
"2
Execute software timer
X
SCMTD1
Mask SCI Interrupt
"$38
SSR
3,PCOTR,SCMTD2 Branch If CK=O
SCITOA
Store transfer data
SOR
7,SSR,SCMTD4 Loop untiL received data
O,SCIMOK,SCMTDS Set Tx=O
4,PCOTR Set request hl9h
O,SCIMOK CLear SCI recelvln9 fLa9

SDR
Execute dummy read
7,SSR,SCMTD3 Loop untiL received data
"$F3
SeLect SCI as event Input
SCR
Load transfer data
SOR
SCIROA
SeLect SCI as no cLock Input
"$E3
SCR
O,SCIMOK Set SCI recelvln9 fLa9
SCMTD1

************************************************

01)105

00106
00107
00108
00109
00110
00111
00112
00113
00114
00115
00116

7,SSR,SCMR02 Loop untiL received data
H$F3
SeLect SCI as event Input
SCR
Load received data
SOR
H$E3
SeLect SCI as no cLock Input
SCR
SCMRD3
4, PCOTR Set Rx=1
Load SCI data
SCIROA
CLear bit C
SCMRD5
Set bit C

IFF6
1FF6
1FF8
IFFA
IFFC
IFFE

1000
1000
1000
1000
1000

*
*
VECTOR ADDRESSES
*
*
**************************************************
*
ORG
$lFF6
*
FOB
SCIMMN
SCIITIMER2
FOB
FOB
FOB
FOB
END

SCIMMN
SCIMMN
SCIMMN
SCIMMN

TIMER/INT2
INT
SWI
RES

~HITACHI
771

I

13.

LIQUID CRYSTAL DRIVER (HD6ll00A) CONTROL

13.1

HARDWARE DESCRIPTION
(1) Func t ion
(a)

Controls LCD driver HD6ll00Ausing the HD630SXO to display
numerals (from 0 to 9) on LCD.

(2)

(b)

Liquid crystal displays with 8 segment x 10 digits
using dynamic drive.

(c)

Transfers 10 digits segment data from the HD630SXO to
HD61100A.

Microcomputer Applications
(a)

Port C controls HD6ll00Acontrol signals (M and CLl) and
common signal of liquid crystal, and displays numerals
on liquid crystal.

(b)

Controls HD6ll00A control signals (CL2 and DL) by using
clocked synchronizing SCI within the HD630SXO and
transfers display data to HD6ll00A.

(3) Circuit Diagram
MCU
HD630SXO
(HD630SYO)

+5V

~ VCC
~4 INT

ErF~
4f1Hz$ 6
22pF

2

---=-

EXTAL
RES

2. 211F= = 7

NUM
1"
...-=. VSS

7i~

+SV

STBY
XTAL

25 C7/ Tx
27 CS/CK
28 C4
29

r~i

3215$.s[4~ 33~9b44Bl

§

VlL VlR V4L V4R

V2L V2R V3L V3R

VEE
GND

~~ ESHL

46
VCC Yl

HD61100A

FCS

I

Y80

7;"-

-I

jHD74

L

IHCO

HD6ll00A Control

~HITACHI

Liquid crystal

80 -\ I-I rl nnll II n I-I 111-1

M CLI CL2 DL
44 37 40 41

Fig. 1
772

COMMON

I II II-lUI 1111 'I II II I
8-segment x 10-digit

(4)

Pin Functions
Pin functions at the interface between the HD630SXO and HD6ll00A
are shown in Table 1.
Table 1
Active
Level
(High
or Low)

Pin Functions

Pin Name
(HD630SXO)

Input/
Output

C3

Output

-

Alternate signal of LCD
driving output.

C4

Output

-

Outputs LCD driving signal
at the falling edge.

CLl

CK

Output

-

Triggers display data at
the falling edge.

CL2

TX

Output

-

Inputs display data.

DL

(S)

Pin Name Program
(HD61100A) Label

Function

M

PCDTR

~
~

Hardware Operation
Control signals (M, CL1, CL2, DL) of HD6ll00A and LCD common signal
are controlled by the HD630SXO clocked synchronizing SCI and port.
The timing chart of each signal is shown in Fig. 2.

Pin name on HD6ll00A

........I1

COMM:-lL_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

I/O port
control

------------'L

M~

CL1.-n'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~

__________ JUULM

Clock
synchronous

SCI
control

DL
80 bits output (10 digits)

Fig. 2

HD6305XO

~

HD6ll00A and LCD Interface

~HITACHI
773

I

13.2

SOFTWARE DESCRIPTION
(1)

Program Module Configuration
The program module configuration for character display on the
liquid crystal module is shown in Fig. 3.

Fig. 3

(2)

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 2.
Table 2

Program Module Functions

Program Module Name

Label

Function

0

MAIN PROGRAM

H61MN

Displays 8 segment x 10 digits LCD.

1

DISPLAY CHARACTER

H61DSP

2

TRANSFER CHARACTER
DATA

MOVE

No.

Transfers display data to HD6ll00A and
displays on LCD.
Stores display data in display RAM.
See subroutine MOVE in HD630S FAMILY APPLICATION NOTES (SOFTWARE) for details.

~HITACHI
774

(3)

Program Module Sample Application (Main Program)
The Flow chart in Fig. 4 is an example of character display on
liquid crystal performed by the program module in Fig. 3.
The main program in Fig. 4 demonstrates the display on liquid
crystal as shown in Fig. 5.
Main Program

:==::r==~
:::=::::r=::~

_____{Sets signals CLI' M and COMMON to Low,
Low and High respectiuely.
{Selects bits 2, 3 and 4 of port C as
output ports.
_____{Selects SCI to transfer clock output
and defines transfer clock width.

_____

-----{Enables SCI interrupt.

:==:::c:==;

:==::r==::: -----

Initializes pointer for display data
{ RAM and counter (CNTR(RAM» indicating
number of interrupts.

-----{ Sets signal CLI to High.
~:::r=::=:

-----{~~~~

signals CLI, M and Common to Low,
and Low, respectively.

:==:::r=::::::: _____{Stores display data in SDR and starts
~=::r====~

transfer.
-----{ Enables interrupt.

~:::r=::=:

~=::r==~ -----{

D.fin." "o"m add, ••• of di.play da1<**************************

**

**
*
*
***************************>1<**********************
*>I<
*>I<
ENTRY : SOA (SOURCE ADDR)
*
*
*>I<

1052 A6 D6

NAME : MOVE (MOVING MEMORY BLOCKS)

DEA (DESTINATION ADDR)
MCNT (TRANSFER COUNTER)
RETURNS : NOTHING

*

MSUB
SOA
MSUB+l
SOA+l
MSUB+2
H$8l
MSUB+3
SPNT

LDX

SPNT

8D
93

JSR
LOX
STA
INC
INC

MSUB
DEA
O.X
DEA
SPNT

00108 106F 3A 8E
00109 1071 26 Fl
"0110 1073 81

DEC
BNE
RTS

MCNT
MOVEl

1054
1056
1058
10SA
105C
lOSE
1060
1062

B7
B6
B7
B6
B7
A6
B7
3F

1066
1068
106A
106B
106D

BD
BE
F7
3C
3C

MOVE

8F
8B
90
BC
91
81
92
93

00102 1064 BE 93
8F
8D

*>I<
*

**************************************************
STA
LDA
STA
LDA
STA
LDA
STA
CLR
MOVE1

~HITACHI
782

Decrement counter
Test if CNTR=O?
Branch if not CNTR=O
InitiaLize counter

CNTR
4.PCDTR Set CLl=l
3.PCDTR.H6lDP2 Branch if M=l
HB
Set CL1=0.M=l.COMMON=0
PCDTR
DDATA-l.X Store dispLay data In SDR
SDR

H$D6

00103
00104
00105
00106
00107

*

*
*
**************************************************

LDA

00094
00095
00096
00097
00098
00099
00100
00101

*

Load InstructIon code
(LOA Dlsp.X)
Load source ADDR (H)
Load source ADDR CL)

Load instruction code CRTS)
CLear reLative data of source
ADDR
Load reLatIve data of source
ADDR
Load transfer data
Load destination ADDR
Store transfer data
Increment destihatlon ADDR
Increment reLative data of
source ADDR
Decrement transfer counter
Branch untiL transfer counter =0

00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135

1100
1100 14
1105 E7

1FF6
1FF6
1FF8
1FFA
1FFC
1FFE

1034
1000
1000
1000
1000

*************************************************
*
*
DATA TABLE
*
*
*
*
*************************************************
*
ORG
$1100
*
$14.$B3.$B6.$D4.$E6 *Se9ment data
FCB
$E7.$74.$F7.$F6.$77
FCB
**************************************************
*
*
VECTOR ADDRESSES
*
*
*
*
**************************************************
*
$lFF6
ORG
*
SCI/TIMER2
FOB
H61DSP
TIMER/INT2
FOB
H61MN
H61MN
INT
FOB
FOB
H61MN
SWI
H61MN
RES
FOB
*
END

I
~HITACHI
783

~4.:;-.;-::-E_X-::T:-:-E-::RN=A:-:-L-:----E_X-:P-:A-:N_S_I-:-ON=_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ....~
14.1

HARDWARE DESCRIPTION
(1)

Function
(a)

Controls externally expanded memory and peripheral LSls
using HD6305YZ.

(b)

Performs asynchronous serial interface with a console
typewriter using the HD6350 (hereinafter, ACIA).

(c)

Controls liquid crystal module (hereinafter, HZ57l)
through the HD63Zl (hereinafter, PIA) and displays inputs
from a console typewriter in character mode.

(2)

Microcomputer Applications
Interfaces with externally expanded LSls through address buses,
data buses and control signals (R/W, E) using the HD6305YZ
externally expanded functions.

(3)

Circuit Diagram
+5V
+5V

18
• 20

21

r/os

i~

r/01 15
1/05 14

HD74HC04

1/05 13
l/o~ 11

~~~~ 10

152076

r/ol

~
1

9

H2571

Von

~~s

7 ORo
8 OBI
9 DB2
10 DB3
11 DB ..

12 DBs

i4 DB s
OB,

6,
5 R/W

4"

Console
typewriter

r-----'
Jo-----i-:.RxDATA!

H075188

r-----(]

~~~--~I.mrs

1

----=.,=5=18-:JglHoO CTs

!I

I
I

I
I

I _____
TxDATA .J
L

Fig. 1

External Expansion Circuit

~HITACHI
784

(4)

Memory Map
(a)

Memories or peripheral LSIs are allocated in external
memory space using address decoder (HD74HC138).
ADR12 and ADR13 are connected to the HD74HC138 A and B pins.
16k byte memory space (from $0140 to $3FFF) are divided
into 4 (4k bytes) and allocated.

Table 1 shows system

address decode.
Table 1

System Address Decode

HD74HC138
Input

Out ut
C

A

B

Gl G2A G2B
ADR .. ADR,. Yo
H L L L L L L
H L L L L H H
H L L L H L
H
H L
L
L
H H H

-

(b)

Yl Yz

H
L
H
H

Address

Allocation

Y3

H H $0000
H H $1000
L H $2000
H L $3000

-

$OFFF
$lFFF
$2FFF
$3FFF

RAM

ROM
PIA
ACIA

Fig. 2 shows system memory map

$0000

I
$003F
$0040

\
$OOFF
$0100

I/O PORTS
TIMER
SCI
RAM

(192 Byte)
RAM

S

(64 Byte)

~

(HM6117)

$013F
$0140
$07CF

HD630SY2 internal regist er and
memory space

RAM

Not Used
$1000

)

ROM
(HM27C64)

DDRA/PIRA
CRA
DDRII PlRlI
CRB

$lFFF
$2000

}

PIA
(HD6321)

Not Used

$2FFF
$3000

}

CTRL/STS
TDR/RDR

ACIA
(HD63S0)

$3FFF

~
Fig. 2

$2000
$2001
$2002
$2003

I

$2FFF
$3000
$3001

Not Used
$3FFF

System Memory Map

~HITACHI
785

(5)

Hardware Operation
Fig. 3 shows timing charts of the HD6305Y2 and memories
(HN27C64, HM6ll7).

---'1

E

HD6305Y2

ADDRESS

I
1

J.

J

R/W
~decoder

tAD

delay time

-

CE
tCE
HN27C64

lt~

1

OE

~tOE- I--t osR-

tACC

t-tHR"

DATA
(OUT)
~decoder

delay time

I-'-'
E2
Data{CEl,C
read

t t COl ,2

DATA
(OUT)

HM6117

tOSR

M

~tHR_

t-tAS

twp

II

WE

:~~e

{

tDW

tOH

DATA

I--

(IN)

HD6305YZ

tAD:
tDSR:
tHR:
tDW:

Address delay time
Data set-up time
Data hold time
Data delay time

HN27C64

tCE:
tOE:
tACC:
tOH:

CE Output delay time
OE Output delay time
Access time
Data output hold time

HM6117

tAA:
tCOl,2:
tAS:
twp:
tDW:
tDH:

Address access time
CElt CEZ Output delay time
Address set-up time
Write pulse width
Input data set time
Input data hold time

Fig. 3

HD6305YZ/Memories Interface

~HITACHI
786

14.2

SOFTWARE DESCRIPTION
(1)

Program Module Configuration
The program module configuration to display data input from
a console typewriter on liquid crystal display system in Fig. 1
is shown in Fig. 4.

TPR
CHARACTERS

Fig. 4
(2)

DATA

DATA

CONVERT
INTO ASCII

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 2.
Table 2

No.

Program Module
Name

Program Module Functions

Label

Function

0

MAIN PROGRAM

EXPMN

Displays data input from console
typewriter on console typewriter
and liquid crystal display.

1

INITIALIZE
LCD-II

EXPINT

Initializes LCD-II.

2

DISPLAY
CHARACTERS

EXPDSP

Displays characters on liquid
crysta1.

3

SEND DATA

EXPOUT

Sends data to console typewriter.

4

RECEIVE DATA

EXPINP

Receives data from the console
typewriter.

5

CONVERT
INTO ASCII

TPR

I

Converts ASCII lowercase into ASCII
uppercase. See subroutine TPR in
HD6305 SERIES APPLICATION NOTES
(SOFTWARE) for details.

~HITACHI
787

(3)

Program Module Sample Application (Main Program)
The flowchart in Fig. 5 is an example of displaying data input
from console typewriter on liquid crystal display and console
typewriter, performed by the program module in Fig. 4.

Main Program
-----{ Enables INT2 interrupt.
Specifies data direction register A
-----{ (hereinaf ter, DDRA).
______[ Selects peripheral interface register A
(hereinafter, PIRA) as output.
-----{ Specifies PIRA.
-----{ Outputs signals

RS~O, R/W~l

and E=O.

_____ { Specifies data direction register B
(hereinafter, DDRB).
Selects peripheral interface register B
{
----- (hereinafter, PIRB) as output.
-----{ Specifies PIRB.
-----{ Initializes FUNC(RAM).
-----{ Initializes ENTRY(RAM).
_____ { Calls program module EXPINT to
initialize LCD-II.
-----{ Initializes instruction ($OE).
Calls subroutine EXPBSY to check busy
----- { flag.
_____ { Calls subroutine EXPINS to set
instruction in H257l.
-----{ Master-reset ACIA.
Initializes ACIA (1 start bit + 8-bit
-----{ data + 1 stop bit, 1/16, RTS=O, TIE=O,
RIE=l) .
-----{ Enables interrupt.

Fig. 5

Program Module Flowchart

~HITACHI
788

Tests if key data receive flag is set.

'--_....,.._ _..J

-----r

L---,------J ----{

Stores KEYDAT(RAM) in entry argument
ACCA.
Calls subroutine TPR to convert ASCII
lowercase in ACCA into ASCII uppercase.
See subroutine TPR in HD630S SERIES
APPLICATION NOTES (SOFTWARE) for details.
Clears key data receive flag.
RTS

=

O.

~----{

Stores ASCII uppercase in entry arguments
OUTDAT(RAM) and DSPDAT(RAM).

~-----{

Calls program module EXPOUT to send
display data to console typewriter.

~-----{

Calls program module EXPDSP to exhibit
characters on liquid crystal display.

INT2 Interrupt Routine

~-----{

Fig. 5

Calls program module EXPINP to receive
data from console typewriter and stores
it in key data buffer.

(Cont.)

I

Program Module Flowchart

~HITACHI
789

14.3

PROGRAM MODULE DESCRIPTION

I

PROGRAM MODULE NAME

I

FUNCTION

II
I

II MCU/MPU II HD6305Y2 II LABEL I ExpINTI

INITIALIZE LCD-II

Initializes LCD-II contained in H2571.

I

I

ARGUMENTS

I
Storage
Location

Contents

Function
initiali FUNC
(RAM)
zation
data($30)
Entry Entry mode
ENTRY
initiali- (RAM)
zation
data($06)

-

-

:

t

1

1

-

II

Not affected
•x : Undefined

Byte
Lgth.

Arguments

Returns

CHANGES IN CPU
REGISTERS AND FLAGS

I

ROM (Bytes)

: Result

ACCA
x

IX

I

x

SJ'ECIFICATIONS

I

138
RAM (Bytes)
5
Stack (Bytes)
2

C

Z

x

x

No. of cycles
54435

N
x

I

Reentrant

•

No

H

•

Relocation
No
Interrupt
Yes

I

DESCRIPTION

I

(1) Function Details
(a) Argument details
FUNC(RAM) : Holds function initialization data ($30).
ENTRY (RAM) : Holds entry mode initialization data ($06).
(b) Program module EXPINT initializes LCD-II with instructions as follows;
Display: Clear, Interface data length: 8 bits,
Display line: I, Character font: 5 x 7 dots,
Duty ratio: 1/8, DDRAM address: Increment,
Display shift: No.

I SPECIFICATIONS NOTES I
"No. of cycles" in "SPECIFICATIONS" represents the number of cycles required when
subroutine EXPBSY is executed at the minimum cycles.

~HITACHI
790

I

PROGRAM MODULE NAME

II

INITIALIZE LCD-II

II MCU/MPU II

HD6305Y2

II LABEL IEXPIN~

I~==========~============~~

DESCRIPTION

(c) Program module EXPINT calls other program modules or subroutines shown
in Table 3.
Table 3

Program Modules and Subroutines called in EXPINT
Label

Functions

CHECK BUSY FLAG

EXPBSY

Checks LCD-II busy flag.

INSTRUCTION SET

EXPINS

Sets instructions in LCD-II.

Program module/subroutine

(2) User Notes
Program module EXPINT cannot be called without initializing PIA.
(3) RAM Description
Label
TNCNT
CUNTl
INSDAT
FUNC
ENTRY

Description

RAM
b7

bO

}
}
}
}
}

Stores counter for initializing LCD-II.
Stores counter for initializing LCD-II.
Stores instruction data.
Stores function initialization data ($30).
Stores entry mode initialization data ($06).

~HITACHI
791

PROGRAM MODULE NAME
DESCRIPTION

II INITIALIZE LCD-II II MCU/MPU II HD6305Y2 II LABEL IrXPINTI
I~==========~==~====~==~~

(4) Sample Application
After initializing PIA and holding entry arguments, call program module
EXPINT.
I

I
I
I

LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA

I..

11$00

CRA
II$FF
DDRA
11$04

CRA
#$02
PIRA
#$00
CRB
II$FF
DDRB

---- Initializes PIA.

11$04

CRB
11$30

FUNC }---- Stores data in entry arguments FUNC(RAM) and ENTRY(RAM).
#$06
ENTRY

I_J_S_R____E_X_P_IN_T-LJII---- Calls program module EXPINT.

~HITACHI
792

PROGRAM MODULE NAME
DESCRIPTION

II

INITIALIZE LCD-II

II

MCU/MPU

II

HD6305Y2

II

LABEL I ExpINTI

I~==========~==~====~==~~

(5) Basic Operation
(a) Control of PIA is shown in Fig. 6 and Fig. 7.
In Fig. 6, data ($80) is output from port A; in Fig. 7, data ($80) is
input to port A.
Note that this controlling method is applied to the system in Fig. 1, and
memory map in Fig. 2.

'----T------I------{
'----T------I ------{

Stores "0" in bit 2 of control register
(hereinafter, CRA) to select DDRA.
CRA is allocated at $2001, so RS1=0, RSO=l.
Stores $FF in DDRA to select port A as
output.

~~------{

Sets bit 2 of CRA to "1" to select PIRA.

'----T------I ------{

Outputs $80 from port A by writing $80
into PIRA.

Fig. 6

'----T------I------{
'----T------I ------{
'----T------I------{

Control of PIA (Port A:

Output Port)

Sets bit 2 of CRA to "0" to select DDRA.
CRA is allocated at $2001, so RS1=0, RSO=l.
Stores $00 in DDRA to select port A as
input.
Sets bit 2 of CRA to "1" to select PIRA.
Moves input data from PIRA to ACCA.

Fig. 7

Control of PIA (Port A:

Input Port)

~HITACHI
793

PROGRAM MODULE NAME
DESCRIPTION

II

INITIALIZE LCD-II

II MCU/MPU II HD6305Y2

II LABEL IrXPINTI

I~==========~==~====~==~~

(b) Function initialization data ($30) must be written 3 times into LCD-II
as shown below to ensure LCD-II internal RESET. Afterwards, LCD-II busy
flag can be checked to select functions.
Reset
LCD-II

I
Wait 15ms
or more
after
reset.

I
Transfer
$30

I
Wait 4.1ms
or more

I
Transfer
$30

I
Wait 100)1SI
or more

I

L
Transfer
$30

•

I
(c) Data in Table 4 is transferred to LCD-II.
Table 4

LCD-II Initialization Data

Data

Function

$30

Sets interface length to 8 bits.

$08

Turns off all display.

$01

Clears all display.

$06

Specifies cursor direction right.
display.

Sets DDRAM address to $00

~HITACHI
794

Does no"£" shift

PROGRAM MODULE NAME

INITIALIZE LCD-II

II MCU/MPU II HD6305Y2 II LABEL I~XPIN~

FLOWCHART

-----{ Initializes loop counter.

-----~ Initializes counter for software timer.

Executes 30ms software timer.

(CUNTl) -1-+
CUNTl

Stores function initialization data
in entry argument.
Calls subroutine EXPINS to write
instructions in LCD-II.
(TNCNT) -1-+
TNCNT

______ {

Decrements loop counter.

(TNCNT)

,,0

------{ Tests if LCD-II reset is completed.

~HITACHI
795

PROGRAM MODULE NAME
FLOWCHART

(FUNC) ....
INSDAT

II

INITIALIZE LCD-II

II

MCU/MPU

II

HD630SY2

II

I~==========~========~==~~

---------{

Stores function initialization data.
(Interface length: 8 bits, Display line: 1,
Character font: SX7 dots, Duty ratio: 1/8)

---------{ Calls subroutine EXPBSY to check busy flag.
subroutine EXPINS to write instruction
----------{ Calls
in LCD-II.
Stores instruction data (display ON/OFF
in entry argument INSDAT(RAM).
---------{ control)
(display OFF, no cursor display, no blink)
----------{
----------

Calls subroutine EXPBSY to check busy flag.

subroutine EXPINS to write instruction
{ Calls
in LCD-II.

----------{

Stores instruction data (display clear)
in entry argument INSDAT(RAM).

----------{ Calls subroutine EXPBSY to check busy flag.
subroutine EXPINS to send instruction
----------{ Calls
to LCD-II.
Stores instruction data (entry mode) in
{ entry argument INSDAT(RAM).
--------(DDRAM address increments, moves cursor
right and display does not shift)
----------[ Calls subroutine EXPBSY to check busy flag.
_________ { Calls subroutine EXPINS to send instruction
to LCD-II.

~HITACHI
796

I

LABEL ExpINTI

PROGRAM MODULE NAME

II

FUNCTION

I

I

II MCU/MPU II

DISPLAY CHARACTERS

HD6305Y2

II LABEL IEXPDSpl

Outputs display data to LCD-II and displays it on liquid crystal display.

I

I

ARGUMENTS

I
Storage
Location

Contents

CHANGES IN CPU
REGISTERS AND FLAGS

•

Byte
Lgth.

: Not affected

Undefined
: Result

ACCA
DSPDAT
(RAM)

1

I

80
RAM (Bytes)

IX

I

x

I

ROM (Bytes)

x :

t
Entry Display
data

SPECIFICATIONS

II

•

1

I

Stack (Bytes)
2

Arguments

Returns

-

-

-

C

Z

x

x

N

I

Reentrant

x

•

Relocation

H

No. of cycles
113

No

•

No
Interrupt
Yes

I

DESCRIPTION

I

DSPDAT

'z'
Convert lowercase into
Uppercese

************************************************

*

*
~HITACHI

814

Check busy fLag
Write instruction in LCD-II

00221
00222
00223
00224
00225
00226
00227
00228
00229
00230
00231
00232
00233
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244

1119
1118
111E
1120
1122
1125
1128
112A
112C
112E
1130
1133
1135

A6
C4
27
A6
C7
C6
B7
A6
B7
A6
C7
IF
80

01
3000
13
05
3000
3001
84
FF
83
95
3000
OA

IFF6
1FF6
1FF8
1FFA
1FFC
1FFE

EXPINP LDA
AND
8EQ
LOA
STA
LOA
STA
LOA
STA
LDA
STA
EXPIP1 BCLR
RTI

1=1$01
SR
EXPIP1
*'1$05
SR
RDR
I

Execute
STOP
t Oscillation stabilization Restart
instruction '""" i
time instruction
~~ nterrupt
J
'.!
execution
Stop mode
------""'I:toP m O d e · ! - I - - - - - - - - - - - - - SW input
(INT)
Restart by INT interrupt

Fig. 3

Timing Chart in Stop Mode

~HITACHI
818

iii)

Wait Mode
Timing chart in Wait Mode is shown in Fig. 4.

55
Wait mode - - - - - - - l
SW input
T1 T2 Tl T2 T1 T2
Wait mode----------~~~~~--~~.-~~~

Tl

T2

Tl: Wait mode
T2: Program execution

Program execution----~
High: Execution
Low : Wait mode

Wait instruction-----L--4---L----~-L---4_~~»fl--~-L-~~----------­
execution timing

j~

Timer interrupt
timing
Fig. 4

(b)

Timing Chart in Wait Mode

HA1835P Control
Timing chart of pulse output and reset pin for
watchdog timer is shown in Fig. 5.
System burst

ICLK

-_rulJUll. .

--.H--+-J

I

Automatic reset signal

L

Watchdog Error _________--,...._ _ _---'r---s,
Output Switch

Fig. 5

)

Timing Chart of Pulse Output

~HITACHI
819

15.2

SOFTWARE DESCRIPTION
(1)

Program Module Configuration
Program module configuration for switch board controlling
HA1835P and low power dissipation mode is shown in Fig. 6.

LWPMN

o

MAIN
PROGRAM

LWPMOD

LWPWCH

LOW POWER
DISSIPATION

Fig. 6

(2)

CONTROL
HA1835P

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 2.

Table 2
No.

820

Program Module Functions

Program Module Name

Label

0

MAIN PROGRAM

LWPMN

1

LOW POWER
DISSIPATION

LWPMOD

Tests operation of low power dissipation
mode.

2

CONTROL HA1835P

LWPWCH

Tests operation of watchdog timer
using HA1835P.

Function
Demonstrates low power dissipation and
HA1835P control.

~HITACHI

(3)

Program Module Sample Application (Main Program)
The flowchart in Fig. 7 is an example of low power dissipation and
HA1835P control performed by the program module in Fig. 6.

Main Program

___ [Turns off all LEDs indicating low
power dissipation mode.

---{ Initializes LED counter.
---{ Initialize TDR.

- - { Turns off LED.

---{ Initializes work area for LED.
---{ Initializes 32ms counter.

Turns off LEDs indicating watchdog
timer ~est and reset modes.

---{ Tests operation of low power dissipation mode.
___{ Tests operation of watchdog timer using
HA1835P.

Fig. 7

Program Module Flowchart

~HITACHI
821

III

15.3

PROGRAM MODULE DESCRIPTION

I

PROGRAM MODULE NAME

II

FUNCTION

1/

I

II

LOW POWER DISSIPATION

I

MCU/MPU IlHD6305xo/yoJ LABEL I

~WPMO~

Tests operation of low power dissipation mode.

I

ARGUMENTS

CHANGES IN CPU
REGISTERS AND FLAGS

IJ

Storage
Location

Contents

II

SPECIFICATIONS

•

Byte
Lgth.

: Not affected
x : Undefined
: Result

ROM (Bytes)

t

ACCA
Entry

-

-

-

I

x

67

RAM (Bytes)

IX

I

• I

4

Stack (Bytes)
0

Arguments

Returns

-

-

-

C

Z

x

x

N

I

x

x

No. of cycles

H

•

92

Reentrant
No
Relocation
No
Interrupt
Yes

I

DESCRIPTION

I

(1) Function De tails
(a) Program module LWPMOD has no arguments.
(b) Executes standby mode, stop mode, and wait mode with switch.
corresponding LED for each mode; LED turns off after reset.

Lights

(2) User Notes

(a) Executes only one mode at a time.
(b) Selects only one mode switch.

I

SPECIFICATIONS NOTES II "No. of cycles"in "SPECIFICATION" represents the number of
cycles required when data is not stored in SBRAM(RAM) and
each mode is executed once.

822

~HITACHI

I

PROGRAM MODULE NAME

II

DESCRIPTION

I

LOW POWER DISSIPATION

I~

HD6305XO/YO

B B

(c) Initializes timer.
(d) Selects DDRs of bit 0-2 of port C as output.
(3) RAM Description
Label

Des cription

RAM

bO

b7
CNTRD
CNTRI
SBRAM

r-

Upper
Lower

-

Stores 32ms counter.
Stores Is counter.
Stores decision data to check reset data from
STANDBY mode.

(4) Sample Application
Calls program module LWPMOD after selecting I/O port and clearing RAM.
I

II

LDA
STA
STA
CLR
CLR

PCDTR
PCDDR
CNTRD
CNTRI

JSR

LWPMOD

11$07

I

} - - - Turns of f all LEDs indi ca ting modes.
---Clears 32ms counter.
- -- Clears Is counter.

II

---Call program module LWPMOD.

I
I

(5) Basic Operation

(a) Enters STANDBY mode by setting signal STBY to Low, returns with STBY to
High.
Software checks whether operation starts after activating on power or
returns from STANDBY mode.
When operation returns from STANDBY mode, turns.on LED. if not,
stores comparison data in SBRAM(RAM).
(b) Enters STOP mode by setting signal INT to High, returns with INT to Low.
When setting signal INT to High, LED indicates STOP mode and executes
stop instruction. When Low, returns from STOP and turns LED off.
(c) Enters WAIT mode by setting WAIT mode switch to High, returns with Low.
Returns at every timer interrupt and executes interrupt routine.
When WAIT mode switch is Low, enters WAIT mode after interrupt.
Whether or not operation is returned at every timer interruption can be
confirmed by LED counter incremented after return. When setting WAIT
mode switch to High, turns on LED indicating WAIT mode and executes WAIT
instruction. When Low, returns from WAIT mode and turns off LED indicating WAIT mode.

~HITACHI
823

I

PROGRAM MODULE NAME

POWER DISSIPATION

II MCU/MPU I HD6305XO/YO ILABEL IILWPM09

FLOWCHART

Tests whether operation starts after
activating power or returns from
STANDBY mode according to contents
of RAM.

on LED indicating STANDBY mode.

Stores comparison data to test if
--- { returns is caused by STANDBY mode.

-

LWPMDI

o+

Bit I

---{ Enables interrupt.

___{Tests whether operation enters STOP
mode with signal INT.
(INT)=O
----[ Turns ON LED indicating STOP mode.
___{Disables interrupt considering
release of STOP mode.
---{ Enters STOP mode.
---{ Enables interrupt.
---{ Turns off LED indicating STOP mode.

1

~HITACHI
824

PROGRAM MODULE NAME

II

LOW POWER DISSIPATION

I~

HD6305XO/YO

B B

FLOWCHART

___ {Tests whether operation enters WAIT
mode.
(0 ,PADTR) =0

---1[ Turns on LED indicating WAIT mode.

----[ Enters WAIT mode.

---~Turns off LED indicating WAIT mode.

r----'----,

___{stores counter data indicating
LED in port B and lights LED.

'--_-.-_---.J

I
$

HITACHI
825

I

PROGRAM MODULE NAME

I

FUNCTION

II

II

CONTROL HA1835P

MCU/MPU

II

I IfWPWC~

HD6305XO/YOJ LABEL

II

Tes ts watchdog timer operation using HA1835P.

I

ARGUMENTS

CHANGES IN CPU
REGISTERS AND FLAGS

1/
Storage
Location

Contents

•

Byte
Lgth.

Not affected
Undefined
: Result

:
x :

t

ACCA
Entry

-

-

I

-

11

x

•

I

ROM (Bytes)
44
RAM

IX

I

SPECIFICATIONS

I

(Bytes~

2
Stack (Bytes)
0

Arguments

Returns

-

-

-

C

Z

x

x

N

I

x

•

H

•

No. of cycles
58
Reentrant
No
Relocation
No
Interrupt
No

I

DESCRIPTION

I

(1) Function Details
(a) Program module LWPWCH has no arguments.
(b) Controls HA1835P using switch.
(2) User Notes
(a) Selects DDRs of bits 2, 3 and 4 of port A and ports Band C as output.
(b) Selects DDRs of bits

I

SPECIFICATIONS NOTES

826

II

o and

1 of port A as input.

"No. of cycles" in "SPECIFICATIONS" represents the number of
cycles required when data is not stored in ERRAM(RAM) and
an pulse generation is selected by switch.

~HITACHI

PROGRAM MODULE NAME

II

CONTROL HA1835P

II

MCU/MPU

I

HD6305XO/YO

I

LABEL

IILwpWC~

I~==========~==~====~==~~

DESCRIPTION
(3) RAM description
Label

RAM

Description

b7

bO

ERRAM

Stores check data .which tests whether
operation starts after activating power
or returns from watchdog timer error.

(4) Sample Application
Calls program module LWPWCH after selecting I/O port and clearing RAM.
I

BSET

4, PADTR

Turns off LED indicating watchdog timer test mode.

BSET

3, PADTR

Turns off LED indicating watchdog timer reset.

II JSR

LWPWCH

II

Calls program module LWPWCH

I
I
I

(5) Basic Operation
(a) Lights LED indicating watchdog timer mode, after main switch is
activated.
(b) When watchdog error switch is turned off, outputs pulse by 1ms software
timer. When turned on, stops pulse output and enter eternity loop.
(c) When turning off watchdog timer error switch. re-calls program after
reset. If data in ERRAM(RAM) and decision data are the same. turns on
LED indicating reset by watchdog timer error.
(d) Stores check data if it is not stored in ERRAM(RAM).

I
~HITACHI
827

PROGRAM MODULE NAME
FLOWCHART

II

CONTROL HAl835P

II

MCU/MPU

I

HD6305XO/YO I LABEL

IILwpWC~

~========~==~====~====~

_____{Lights LED indicating watchdog timer
mode after activating main power.
(ERRAM);'$55
Tests reset is performed by main switch
activation or by watchdog timer
according to contents of RAM.

reset after

LWPWHl

_____{Turns off LED indicating watchdog
timer mode.

_____{stores comparison data in RAM to test,
resetting from watchdog timer error.

Tests whether watchdog timer error
-----{ switch is on.
If ON, output pulse cannot be performed.

~HITACHI
828

I

PROGRAM MODULE NAME
FLOWCHART

II

CONTROL HA183SP

II MCU/MPU I HD630SXO/YO ILABEL IfWPWC~

I~========~~========~==~~

---

Executes lms software timer.

Outputs High and Low into HA183SP by
lms intervals.

LWPWHS

I
~HITACHI
829

15.4

SUBROUTINE DESCRIPTION

:==S=U=BR=O=UT=I=NE=N=AME==~I ==I=NC=REME==NT==C=OUN=T=E=R=~"=MC=U=I=MP=U=-I!:H=D=6=30=5=x=o=/y=o~1=LAB=E=L=I~f=WP=CN=!TI
::1

I

FUNCTION

Decrements LED counter CNTRI(RAM).
BASIC OPERATION
(1)

This subroutine is called for

(2)

Uses two counters to count up each second.

(3)

When incrementing one counter every timer interrupt, one second interval

e~ch

32ms timer interrupt.

is obtained after 30 times incrementing.

PROGRAM MODULE USING
THIS SUBROUTINE

FLOWCHART

~---r----~ ----~Clears

interrupt request bit.

~---r~~~ ----~Increments

32ms counter.

(CNTRI)"30
Displays on LED by decrementing in
binary once each second during WAIT
mode execution.

~~~~~~ ----~Increments

•
830

ls counter •

HITACHI

15.5

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055

PROGRAM LISTING

*
*
*
CNTRD
****

0080
0080
0081
0082
0084

0001
0001
0002
0002

0000
0001
0002
0004
0005
0006
0009
0008

CNTRI
ERRAM
SBRAM

*
*
PADTR

RAM ALLOCATION
ORG

$80

RMB
RMB
RMB
RMB

1
1
2

2

*************************
15 counter
32ms counter
Watch dog data RAM area
Standby RAM area

****

SYMBOL DEFINITIONS *********************

PBDTR
PCDTR
PADDR
PBDDR
PCDDR
TCR

EaU
EaU
EQU
EaU
EaU
Eau
EQU
EQU

TOR

$00
$01
$02
$04
$05
$06
$09
$08

Port A data register
Port B data register
Port C data register
Port A data direction register
Port B data direction register
Port 0 data direction register
Timer controL register
Timer data register

************************************************

*

MAIN PROGRAM : LWPMN

*
*

*

*
*

************************************************

*

1000
1000
1002
1004
1006
1008
100A
100C
lOOE
1010
1012
1014
1016
1018
lOlA
10lC
10lE

A6
B7
B7
A6
B7
A6
B7
B7
B7
3F
3F
18
16
A6
B7
02

*
07
LWPMN
02
06
OF
09
FF
08
01
05
80
81
00
00
IC
04
00 as LWPMN1

1021
1024
1026
1029

CD
20
CD
20

102B
F8
106E
F3

ORG

$1000

LDA
STA
STA
LOA
STA
LOA
STA
STA
STA
CLR
CLR
BSET
BSET
LOA
STA
BRSET

11$07

JSR
BRA
LWPMN2 JSR
BRA

PCDTR
PCDDR
I:l$F
TCR
I:l$FF

Turn off LED
SeLect port C bltO-2 as output
InitiaLize TCR
InitiaLize TOR

TOR

PBDTR
Turn off LED
SeLect portB as output
PBDDR
CLear 15 counter
CNTRD
CNTRI
CLear 32ms counter
4.PAOTR Turn off LED
3.PADTR Tur-n off LED
1:l$1C
SeLect port A bit2-4 as output
PADDR
I.PADTR.LWPMN2 Branch if HA1835P
test mode
Execute Low power mode
LWPMOO
LWPMN1
LWPWCH
Execute HA1835P mode
LWPMNI

************************************************

*
*
NAME : LWPMOD CLOW POWER DISSIPATION)
*
*
*
*
************************************************
*
*
INPUT : NOTHING
*
*
~HITACHI
831

I

00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110

*
*
102B
1020
102F
1031
1033
1035
1037
1039
103B
103C
103E
1040
1042
1044
1046
1048
104A
1040
104F
1051
1053
1055
1056
1058
105A
105B
105C
1050
105F
1061
1063
1065
1067
1068
106A
106C

106E
1070
1072
1074
1076
1078

A6
B1
26
A6
B1
26
A6
B7
9A
20

00
55
82
OC
AA
83

I:I$AA
SBRAM
LWPM02
t1$55
SBRAM+1
LWPM02
1:1$06
PCOTR

Test If SBRAM=$AA?

Br'anch if not equaL
Test if SBRAM+l=$55?
Branch If not equaL
Stand by LEO on

EnabLe interTupt
LWPM03
Store $AA In SBRAM
f:lMA
SBRAM
1:1$55
Stor'e $55 in SBRAM+1
SBRAM+1
LWPMOI
LWPM05
Test if STOP mode?
0.PAOTR.LWPM06 Branch if WAIT mode?
CNTRO
Couote r' LEO on
PBOTR
I:I$FF
SeLect por't B as output
PBOOR
f:I$05
PCOTR

Stop mode LED on
Disable intrTupt
STOP mode
Enable i nterTupt

tlD7
PCDTR
LWPMD3
1:103
PCDTR
1:107
PCDTR
LWPMD4

ALL LEO off
( INn = 1 -) WAIT mode LOaD
Wait mode LEO on
WAIT mode
ALL LEO off

************************************************
*
*
NAME : LWPWCH (CONTROL HA1835P)
*
*
*
*
************************************************
*
*
INPUT
NOTHING
*
*
OUTPUT
NOTHING
*
*
*
*
************************************************

LWPWCH BCLR
LOA
CMP
BNE
LOA
CMP

4.PADTR
1:1$55
ERRAM
LWPWH1
I:I$AA
ERRAM+l

~HITACHI
832

*
*

*********************************************~**

LWPMOO LOA
CMP
BNE
LOA
CMP
BNE
LOA
STA
LWPMOI CLI
BRA
OA
A6 AA
LWPM02 LOA
B7 84
STA
A6 55
LOA
B7 85
STA
20 F3
BRA
2F OC
LWPM03 BIH
00 00 16 LWPM04 BRSET
B6 80
LOA
B7 01
STA
A6 FF
LOA
B7 05
STA
81
RTS
A6 05
LWPM05 LOA
B7 02
STA
9B
SEI
8E
STOP
9A
CLI
A6 07
LOA
B7 02
STA
20 E5
BRA
A6 03
LWPM06 LOA
B7 02
STA
8F
WAIT
A6 07
LOA
B7 02
STA
BRA
20 OC

19
A6
B1
26
A6
B1

AA
84
00
55
85
07
06
02

OUTPUT : NOTHING

Watch d09 LEO on
Test if ERRAM+1=$55

Branch not equaL
Test if ~RRAM=$AA?

00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00129
00130
00131
00.132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156

107A
107C
107E
1080
1082
1084
1086
1088
108A
108D
108F
1090
1092
1095
1097
1099
109B

109C
109E
10AO
10A2
10A4
10A6
10A8
10AA

26 06
BNE
BCLR
17 00
18 00
BSET
20 08
BRA
A6 55
LWPWH1 LDA
B7 82
STA
A6 AA
LDA
B7 83
STA
00 00 FD LWPWH2 BRSET
A6 FA
LDA
LWPWH3 DEC
4A
26 FD
BNE
04 00 04
BRSET
14 00
BSET
BRA
20 02
15 00
LWPWH4 BCLR
81
LWPWH5 RTS

IF
3C
A6
B1
26
3F
3C
80

09
81
30
81
04
81
80

Branch if not equaL
Watch dog errar LED on
Watch dog LED off

Stor'e $55 in ERRAM
lass
ERRAM
t:I$AA
Store $AA in ERRAM+1
ERRAM+1
0.PADTR.LWPWH2 Loop if W.D sw on
Execute lms software timer
t:l250
A
LWPWH3
2.PADTR.LWPWH4 Branch if CLI<=l
2.PADTR Set CLI<= 1
LWPWH5
2.PADTR Set CLI<=O

************************************************
*
*
NAME : LWPCNT (INCREMENT COUNTER)
*
*
*
*
************************************************

LWPCNT BCLR
INC
LDA
CMP
BNE
CLR
INC
LWPCT1 RTI

7.TCR
CNTRI
t:I$30
CNTRI
LWPCT1
CNTRI
CNTRD

CLear interrupt request bit
Increment 32ms counter
Test if CNTRI=30
Brabch not equaL
CLear 32ms counter
Increment Is counter

************************************************
*
*
VECTOR ADDRESSES
*
*
*
*
************************************************
*

1FF6
1FF6
IFF8
1FFA
1FFC
IFFE

LWPWH1
3.PADTR
4.PADTR
LWPWH2

1000
109C
1000
1000
1000

*

*

ORG

$IFF6

FDB
FDB
FDB
FDB
FDB

LWPMN
LWPCNT
LWPMN
LWPMN
LWPMN

SCI/TIMER2
TIMERIINT2
INT
SWI
RES

I

END

~HITACHI
833

•
834

HITACHI

HD6305/HD63L05 SERIES HANDBOOK

Section Eight

APPENDIX:
Thchnical Q and A (Part I)

8-Bit Single-Chip Microcomputer

HD630SXO, HD630SX1, HD630SX2
HD630SYO, HD630SY1, HD630SY2

I
~HITACHI
835

~HITACHI
836

PREFACE

The HD6305X and HD6305Y are microprogram-controlled 8-bit
single-chip microcomputers that use CMOS 2.5 vm technology.
They have a very high compatibility with the HD6805 in terms
of instruction set.

The CPU, ROM, RAM, I/O, timer, and

serial communications interface (SCI) are all integrated
into one chip.
Each HD6305X-series microcomputer consists of:

A HD630SXO

with a 128-byte RAM and a 4-kbyte ROM on a single chip; a
HD6305X1 connectable to external memory; and a HD6305X2
without ROM.
Each HD6305Y-series microcomputer consists of:

A HD6305YO

with a 256-byte RAM and a 8-kbyte ROM on a single chip; a
HD6305Y1 with optional external memory; and a HD6305Y2
without ROM.
The CMOS technology enables these models to operate over a
wide range of supply voltages (Vcc operates in the 3 V - 6 V
range at operating frequencies of 0.1 MHz - 0.5 ftlHz) with
less power consumption.

The low-power-consumption modes

(STOP, WAIT, and STANDBY) available with these models permit
further power savings.
The instruction set includes DAA (decimal adjust instruction), and STOP and WAIT (used to enter the corresponding
low-power-consumption modes), in addition to the HD6805
instruction set.

I

The minimum instruction execution time is

0.5 vsec/cycle (f=2 MHz), permitting high-speed operation.

~HITACHI
837

HOW TO USE THIS MANUAL
This TECHNICAL QUESTIONS AND ANSWERS is a user reference manual that has been compiled in question-andanswer form.

It is based on technical inquiries from

HITACHI microcomputer users.
This manual should be used in conjunction with the
appropriate data book (which you should already have) •
You can make best use of this manual either by:

reading

all of it before you start to design any microcomputerapplied products, in order to strengthen your technical
background; or referring to it during the actual design
process, using it to help you solve specific problems
that may arise.
Although some of the items supplement the data book,
most of them are inquiries from the users.

In order to

meet future needs, we are prepared to increase the
number of Q & A items and to update the data book .

•
838

HITACHI

Contents
Q & A No.
Parallel Port
(1 Outputting Data from Ports after a Reset
(2) Serial 1/0 Pin Status
(3) Using Port C when Serial I/O is Used
Serial Port
(1) Designating Input or Output Operation of Serial
I/O Clock Pin
(2) SCI Prescaler Initialize Timing and Clock Output
Timing
(3) SSR7 (SCI Interrupt Request Bit) Set Timing
(4) Using SDR (SCI Data Register) when Serial I/O 1S
not Used
(5) Accessing SDR (SCI Data Register)
(6) Clearing SSR (SCI Interrupt Request Bit)
(7) Transmitting and Receiving Data Simultaneously
through Serial I/O
(8) Notes on Receiving Data through SCI in External
Clock Mode
(9) SCI Operation in External Clock Mode
(10) Initializing the Transfer Clock Generator
Prescaler
Timer /Co'un ter ::::J
(1) Timer Count-down Timing when External Clock is
Input
(2) Timer 2 Interrupt Cycles
(3) Reading/Writing Data from/into the TOR during
Timer Operation
(4) Timer Clock Input Source

Page

QA635-001B
QA635-002B
QA635-003B

841
842
843

QA635-004B

844

QA63S-00SB

845

QA63S-021B
QA635-024B

846
847

QA63S-02SB
QA63S-026B
QA63S-030A

848
849
850

QA63S-031A

851

QA635-032A
QA63S-033A

852
853

QA635-006B

854

QA63S-022B
QA63S-034A

855
856

QA635-035A

857

QA63S-007B
QA63S-008B
QA63S-009B
QA63S-010B
QA635-011B

858
859
860
861
862

QA635-012B

863

QA635-013B
Ql\635-036A

864
865

QA635-037A

866

QA635-014B

867

BUS Interface
Interrupt
I
(1) Schmitt Trigger Circuit of Interrupt Pin
(2) Servicing Timer Interrupt while Masked
(3) Servicing INT External Interrupt while Masked
(4) Servicing INT2 External Interrupt while Masked
(5) Servicing an Interrupt after a Reset (CCR I bit
initializing)
(6) Servicing External Interrupt after Returning
from Standby Mode
(7) Servicing Multiple Interrupts
(8) Time from Interrupt Occurrence to Interrupt
Servicing Routine Execution
(9) Servicing SCI (Serial I/O) Interrupt while
Masked
A/D Converter
Oscillator
I
(1) Timing of External Clock Input to the Oscillator
and E Clock Timing

I

~HITACHI
839

Q & A No.

Page

Reset
(1) Port Status at a Reset
(2) Bus Status at a Reset

Low Power Consum tion
Bus Status in Low-Power-Consumption Modes
(2) Executing an Instruction when Entering Standby
Mode
(3) Standby Mode Timing
(4) Returning from Standby Mode
(S) Entering Low-Power-Consumption Modes
(6) Entering Wait Mode
(7) Entering Stop Mode
(8) Returning Time from Stop Mode
(9) Current Consumption in Low-Power-Consumption
Mode
1

QA63S-0lSB
QA63S-0l6B

868
869

QA63S-0l7B
QA635-018B

870
871

QA635-019B
QA63S-020B
QA635-027B
QA635-028B
QA63S-029B
QA63S-038A
QA635-039A

872
873
874
875
876
877
878

QA63S-040A
QA635-023B

879
880

EPROM-'-on-chip
Software
(1) Accessing Not Used Areas on Memory Map
(2) Using Bit Manipulating Instruction for Output

Ports

I
Evaluation Kit
Emulator
SD
Data Buffer
(1) Statuses of Address Bus, Data Bus and Control
Line when the Internal Address Space is Accessed
Others

~HITACHI
840

QA63S-041B

881

No. QA635-001B

I

Io

.8S
o 8M
4S
Dl6M
DEvaluation kit Emulator

Type

HD6305XO/Xl/X2
HD6305YO/Yl/Y2

Theme

Outputting Data from Ports after a Reset

Question

Device

I

Which operation should be performed first to output data
through input ports A, B, C, D and G after a reset?;
storing data in the Data Register of the ports or
designating the corresponding DDR (Data Direction
Register)?

Answer

I

Store the data to be output in the Data Register first,
and then designate the corresponding DDR to data ou tpu t
(DDR=l) •
Since a reset causes the Data Register to become 0, if the
DDR is designated to data output before data 1.S stored in
the Data register, 0 is ou tpu t to the ports.

o Software
o SBC
o SD

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Titlel

*

8-bit Single-chip
Microcomputer
Data Book
Other Data Document
Ti tl e I

Reference Q & A Sheet

~
QA635-0l5B

Supplement

I

The HD6305Xl/X2 and HD6305Yl/Y2 do not have port G.

~HITACHI
841

No. QA63S-002B
Type

I

HD630SXO/Xl/X2
HD630SYO/Yl/Y2

Device

Io

.8S
o 8M
D16M
4S
DEvaluation kit Emulator

o Software
o SD
o SBC

Theme Serial I/O Pin Status
Question

I
-

After ports Cs to C7 are respectively used as CK, Rx
and Tx pins of the SCI (serial I/O) , these ports are specified as I/O pins using the SCR (SCI Control
Register)(SCR7=SCR6=SCR5=0). What is the value of the DDR
(Data Direction Register) when the ports are used as I/O
pins?

Answer

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

*

The DDR retains the value for the SCI, as shown below.
Pin
C7/Tx
C6/Rx

-

DDR value for SCI
1 (output port)
0 (input port)
0 (input port)

CS/CK
1 (output port)

Notes
When Tx is used, SCR7=l.
When Rx is used, SCR6=1.
In the case of external clock
source mode.
In the case of internal clock
source mode.

Even when the SCR value is changed after the SCI is used,
the DDR value shown in the above table is maintained. When
using Cs to C7 as I/O ports, rewrite the DDR value using
software.

Supplement I
SCR (SCI Control Register: $0010)
7
6
5
1
4
3
2
0
SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCRI SCRO
+
Clock source selection bit
SCI data input enable bit
SCI data output enable bit

I

I

r

I

I

I

I

I

I

r

~HITACHI
842

8-bit Single-chip
Microcomputer
Data Book
Other Data Document
Title I

Reference Q & A Sheet

~

No. QA63S-003B

I

I oo

Type

HD630SXO/Xl/X2
HD630SYO/Yl/Y2

Theme

Using Port C when Serial I/O is Used

Device

.8S
o 8M
4S
O16M
Eva lua tion kit Emulator

Question r
When ports Cs to C7 are used as the SCI (serial I/O) , is it
possible to use ports Co to C4 as usual I/O pins?

Answer

I

Yes. These ports can be used as usual I/O pins because
they are independent of the SCI. The ports affected by the
SCR (SCI Control Register) when the SCI is used are ports
Cs to C7 only. Input and output functions of ports Co
to C4 are selected using bits 0 to 4 of port C's DDR
(Data Direction Register).

o Software
o SD
o SBC

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-ch i p
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Apl'licable Manual
Ti t lei

*

8-bit Single-chip
Microcomputer
Data Book
Other Data Document
Title J

Reference _Q & A Sheet

~

Supplement

I

I
~HITACHI
843

No. QA63S-004B
Type

HD630SXO/Xl/X2
HD630SYO/Yl/Y2

I

Device

Io

o SM
OI6M
.SS
Cl 4S
Evaluation kit Emulator

o Software
o SD
o SBC

Theme Designating Input or Output Operation of Serial I/O Clock Pin
Question

I

Classification
Parallel Port
Serial Port
* Timer
/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title J

Does setting 0 or I in the corresponding DDR (Data
Direction Register) enable the clock pin CK to be
designated as an input or output pin when the SCI
(serial I/O) is used?

Answer

I

No. Bits 4 and 5 (SCR4,.2.) of the SCR (SCI Control
Register) designate the CK pin as input or output when the
SCI is used, not the DDR.
As shown below, the combination of bits 4 and 5 enables the
SCI clock source selection, determining whether the CK pin
is specified as an input or output pin.
SCRS SCR4 Clock source
CK pin (port C5)
0
0
Used as I/O pin (according tc
0
1
the DDR)
1
0
Internal
Clock output (DDR output)
I
1
External
Clock input (DDR input)

Supplement

f

1
SCRI

0

I

SCRO

I

Clock source selection bit

~HITACHI
844

~

I
I

Other Data Document
Title I

Reference Q & A Sheet

Note: The selection of input or output is made by the DDR
when SCRS is 0 and SCR4 is 0 or 1.

SCR (SCI Control Register: $0010)
7
6
5
4
3
2
I SCR7 I SCR6 I SCRS I SCR4 I SCR3 I SCR2

S-bit Single-chip
Microcomputer
Data Book

~

No. QA63S-00SB
Type

I

HD630SXO/Xl/X2
HD6305YO/Yl/Y2

Device

Io

.8S
o 8M
4S
o 16M
DEvaluation kit Emulator

o Software
o SD
o SBC

Theme SCI Prescaler Initialize Timing and Clock Output Timing
Ques tion

I

At what timing is the SCI (serial I/O) prescaler initialized?
In addition, when the internal clock is used (SCR4=O,
SCR5=1), at what timing lS the CK (seria I clock) output?

Answer

I

The prescaler is initialized when data is read from or
wt"i t ten into the SDR (SCI Data Regist~).
When the internal clock is used, the CK is output at the
baud rate specified by bits 0 to 3 of the SCR (SCI Control
Register) , immediately after the data reading/writing.
The SCI timing chart is shown below.

,~P<'ViOU'

( C./Rx)

8-bit Single-chip
Microcomputer
Data Book
Other Data Document
Titlel

d."

,

.\

I

2

3

..

!)

6

7

LSB

8

MSB

(C,/Tx)----J

Input data
latch timing

*

~

S«'"' do,k
(C,/Ci(J

Output data

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

_____

I

1 1 J

I

I

I

Reference Q & A Sheet

~

SCI Timing Chart

Supplement

I

~HITACHI
845

No. QA63S-021B
Type

I

HD630SXO/Xl/X2
HD630SYO/Yl/Y2

Device

I

CI 4S
.8S
D 8M
D 16M
DEvaluation kit, Emulator

o Software
o SD
D SBC

Theme SSR7 (SCI Interrupt Request Bit) Set Timing
Ques tion

I

After 8-bit data transmitting or rece1v1ng through the SCI
(serial I/O) is completed, SSR7 (SCI interrupt request bit)
of the SSR (SCI Status Register) is set. At what timing is
this setting performed?

Answer

I

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Titlel

*

SSR7 is set at the rising edge of the 8th CK (serial clock)
as shown below.
Serial ClOCk_~
<;J~~

SCI interrupt request bit

~HITACHI
846

Reference Q & A Sheet

No. QA635-024B

I

Io

o 8M
.8S
4S
Dl6M
DEvaluation kit, Emulator

Type

HD630SXO/Xl/X2
HD630SYO/Y 1/Y2

Theme

Using SDR (SCI Data Register) when Serial I/O is not Used

Ques tion

Device

I

Is it possible to use the SDR (SCR Data Register: $0012) as
a general-purpose register when the SCI (serial I/O) is not
used?

Answer

I

o Software
o SD
o SBC

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Osc i lla tor
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

*

Yes. The SDR can be used as a general-purpose register
when the SCI is not used i. e. , when the SCI clock is
stopped with SCR4 to SCR7 being O.
Other Data Document
Ti t Ie I

Reference Q & A Sheet

~

Supplement!
SCR (SCI Control Register: $0010)
2
7
6
1
5
4
3
0
! SCR7 ! SCR6 I SCRS I SCR4 I SCR3 I SCR2 I SCRI I SCRO I
I
Clock source selection bit
SCI data input pin enable bit
SCI data output pin enable bit

f

t

~HITACHI
847

No. QA63S-02SB
Type

I

HD630SXO/XI/X2
HD630SYO/YI/Y2

Device

I

4S
o 8M
.8S
Dl6M
DEvaluation kit Emulator

[J

Theme

Accessing SDR (SCI Data Register)

Question

I

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
TitleJ

What will happen if data is read from or written into the
SDR (SCI Data Register) while another data is being
transmitted or received through the SCI (serial I/O)?

Answer

o Software
o SD
DSBC

*

I

Normal operation can not be guaranteed for either
transmission or reception. Do not access the SDR during
data transmitting or receiving since the SCI becomes
disabled after the access (the MCU must be reset to use
the SCI again).
Other Data Document
Ti tIe I

Reference Q & A Sheet

~
QA63S-033A

Sup~lement

I
SDR (SCI Data Register: $0012)
7

Receive

-I MSB I

6

I

5

I

4

I

3

I

2

I

~HITACHI
848

1

0

I LSB I

____ Transmit

No. QA635-026B
Type

I

HD6305XO/Xl/X2
HD6305YO/Y1/Y2

Device

Io

.8S
o 8M
4S
Dl6M
DEvaluation kit Emulator

o Software
o SD
o SBC

Theme Clearing SSR (SCI Interrupt Request Bit)
Question

I

After data is transmitted or received through the SCI
(serial I/O), SSR7 (SCI interrupt request bit) is set
to 1. At this time, if 0 is set in SSR7 by software
to cl~ar the bit, is it possible to transmit or receive
the next data?

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrl!.E.t
A/D Converter
Oscillator
Reset
Low Power Consumption

*

EPROM-on-ch~

Answer

Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Ti t Ie I

I

No. When 0 is set in SSR7 by software, this bit is
cleared, and the next data transmitting and receiving cannot be performed. SSR7 is cleared under the following conditions.
~When data is read from or written into the SDR (SCI Data
Register) •
(After SSR7 is cleared and the octal counter is reset,
the next data transmitting/receiving is executed.)
KDWhen 0 is set in SSR7 by software.
(The SCI's octal counter is not reset, enabling no data
transmitting/receiving.)
Therefore, repeat data reading or writing from/into the SDR
to transmit/receive data repeatedly.
Dummy-read the SDR before receiving the first data.

Supplement

Other Data Document
Ti t Ie I

Reference Q & A Sheet

~

I

SSR (SCI Status Register: $0011)
7

6

5

4

3

2

1

0

I SSe SSR6 1SSR5 1SSR4 I SSR3 1><1><1><1
SCI interrupt request bit

~HITACHI
849

No. QA635-030A
Type

HD6305XO/XI/X2
HD6305YO/Y l/Y2

I

Device

I

o 8M
.8S
Dl6M
D4S
DEvaluation kit, Emulator

o Software
o SD
o SBC

Theme Transmitting and Receiving Data Simultaneously through Serial I/O
Ques tion

I

Is is possible to transmit and receive data simultaneously
through the SCI (serial I/O) by using the internal clock
for transmitting and the external clock for receiving, or
vice versa?

Answer

I

No. Only one clock sburce can be selected as the SCI
transfer clock. Simultaneous data transmission and reception using two transfer clocks are impossible.
When a single clock source is used, data can be transmitted
and received at the same time.

Classification
Parallel Port
Serial Port
Timer /Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Titiej

*

Other Data Document
Ti tIe I

Reference Q & A Sheet

~

Supplement

I

~HITACHI
850

No. QA635-031A
Type

HD6305XO/Xl/X2
HD6305YO/Yl/Y2

I

Device

I

.8S
o 8M
D16M
D 4S
DEvaluation kit Emulator

o Software
o SBC

o SD

Theme Notes on Receiving Data through SCI in External Clock Mode
Question

I

What should we pay attention to when using the external
clock to receive data through the .SCI (serial I/O)?

Answer

I

The external transf;er clock source does not enable
receiving side to check when data is transmitted.
Therefore, it is necessary to read out data in the
Data Register) as soon as the data is received, to
for receiving the next data.
Whether or not receiving has been completed can be
by an SCI interrupt or by testing bit 7 of the SSR
Status Register) by software.

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consum~tion
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Ti tIe I

*

the
SDR (SCI
prepare
checked
(SCI

Other Da ta Doc umen t
Title I

Reference Q & A Sheet

~

Supplement

I

SSR (SCI Status Register: $0011)
7
6
5
4
1
0
3
2
I SSe SSR6 1SSR5 1SSR4 1SSR3 1><1><1><1
SCI

i,,"=p' '"q.""

bi, (" No
1: Yes

,"que... )

~HITACHI
851

No. QA63S-032A
Type

HD630SXO/Xl/X2
HD630SYO /Y 1/Y2

Device

I

o 8M
.8S
D16M
Cl 4S
DEvaluation kit Emulator

o Software
o SBC

o SD

Theme SCI Operation in External Clock Mode
Ques tion ,
The SCI ( serial I/O) is in external c1oc~mode;
If the external clock is applied to the CK pin before the
CPU writes/reads data into/from the SDR (Serial Data
Register) after the one-byte data transmitting/receiving is
completed, will the SCI start the next data
transmitting/receiving?

Answer

I

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chi]:>
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
TitleJ

*

No. The SCI does qot start transmitting or receiving the
next data until the CPU writes/reads data into/from the
SDR. That is, any clock signal applied to the CK pin
before the CPU accesses the SDR wi 11 be ignored.
Other Data Document
Ti tIe'

Reference Q & A Sheet

~

Supplement

-

I

The CK pin can also used
as Cs pin. I t is controlled by bits 4 and 5
of the SCR (SCI Control
Register).

SCRS
0
0
1
1

SCR4

Clock
source

0
1
0
1

-

Cs pin

Used as I/O pin (accordin~
to the DDR)
Interna Clock output (DDR output)
External Clock input (DDR input)

~HITACHI
852

No. QA635-033A
Type

I

HD6305XO/Xl/X2
HD6305YO/Y l/Y2

Device

Io

.8S
o 8M
4S
Dl6M
DEvaluation kit Emulator

o Software
o SD
o SBC

Theme Initializing the Transfer Clock Generator Pres caler
Question

I

~he prescaler of the SCI transfer clock generator is ini-

tialized by reading/writing data from/into the SDR (SCI
Status Register) or by setting 1 in SSR3 (SCI Status
Register bit 3). What is the difference of the initialization performed by these two methods?

Answer

I

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chi£
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
~licable Manual
TitleJ

*

h'here are differences in the following points.
(1)

When data is read/written from/into the SDR, the SCI
octal counter is initialized at the same time the
pres caler is initialized. This causes the SCI to start
transmitting or receiving the next data.
(2) When I is set in SSR3, only the prescaler is initialized. The SCI does not start data
trasmitting/receiving.
IsSR3 is the bit to be used to initialize the presca ler when
the transfer clock generator is utilized as Timer 2.

Other Da ta Doc umen t
Ti tIe I

Reference J!

&

A Sheet

~
QA635-025B

Supplement

I

~SR (SCI Status Register: $0011)

7

6

5

4

3

2

I

0

I SSR7 I SSR6 I SSR5 I SSR4 I SS~>in)
D
(Input pin)
E, F
(Output pin)
G
(I/O pin)

DDR

Data
register

0

0

-

-

-

0

0

0

S-bit Single-chip
Microcomputer
Data Book

Status at a reset

.Designated as an input ports
(high impedance)
High impedance

o

Other Data Document
Ti tIe I

output

Designated as an input port
(high impedance)

Reference Q & A Sheet

~
QA63S-001B
QA63S-016B

Supplement

I

The HD6305XI/X2 and HD6305Yl/Y2 do not have ports E, F and G.

~HITACHI
868

No. QA63S-0l6B
Type

HD630SXO/xl/x2
HD630SYO/YI/Y2

Theme

I

Device

Io

o 8M
.8S
D16M
4S
DEvaluation kit Emulator

OSBC

Bus Status at a Reset

Ques tion

I
-

What are the statuses of the address bus, data bus and R/w
signal at a reset?

Answer

o Software
o SD

I

Classi fica tion
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
AID Converter
Osc i 11a tor
Reset
* Low
Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Ti tIe I

Their statuses are as shown below.

~

Address bus

Data bus

Status at a reset
Outputs $lFFF
Other Data Document
Ti tIe I

High impedance

-

R/w signal

High level (read)
Reference Q & A Sheet

~
QA63S-0lSB
QA63S-017B

Supplement

I

The above answer does not apply to the HD630SXO and HD630SYO since these
units cannot be expanded externally.

I

~HITACHI
869

No. QA635-0l7B

I

Io

4S
.8S
o 8M
D16M
DEvaluation kit Emulator

Type

HD6305XO/xl/x2
HD6305YO/Y l!Y2

Theme

Bus Status in Low-Power-Consumption Modes

Device

Question

-

What are the statuses of the address bus, data bus and R/w
signa I in low-power-consumption modes (wait, stop and
standby)?

*

o Software
o SD
o SBC

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
AID Converter
asci lla tor
Reset
Low Power Consumption
EPROM-on-chi~

Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Ti tIe I

Answer I
Their statuses are as shown below.
Mode
Wait

Address
bus
$IFFF

Stop

$IFFF

Standby

High
impedance

Data bus

R/w

High
ilIlI>edance
High
impedance
High
impedance

signal
High
level
High
level
High
impedance

E pin
E clock
output
Low
level
High
impedance

Other Data Document
Ti tIe I

Reference Q & A Sheet

~

Supplement

I

The above answer does not apply to the HD6305XO and HD6305YO since these
units cannot be expanded externally.

~HITACHI
870

No. QA635-0l8B

I

Io

4S
.8S
Dl6M
o 8M
DEvaluation kit Emulator

Type

HD630SXO/Xl/X2
HD630SYO/Y l/Y2

Theme

Executing an Instruction when Entering Standby Mode

Question

Device

I

The MCU enters standby mode by setting the STBY pin in Low.
What will happen to the instruction that was being executed
at that time?

o Software
o SD
o SBC

Classification
Parallel Port
Seria 1 Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

*

Answer

I

The instruction execution is stopped since the MCU enters
standby mode whether or not an instruction execution
sequence is executed. The MCU enters standby mode immediately after the STBY pin becomes Low.
In standby mode, the internal oscillator is stopped and the
contents of the MCU internal registers are destroyed. So,
be sure to perform a reset-start to return from standby
mode (the built-in RAM values are retained) •

E clock
STU Y

8-bit Single-chip
Microcomputer
Data Book
Other Data Document
Ti tIe I

-.JI

I
I

L..........-...

Reference Q & A Sheet
Standby mode

~
QA635-0l9B

Supplement

I

~HITACHI
871

No. QA635-0l9B

I

Type

HD6305XO/Xl/X2
HD6305YO!Yl/Y2

Theme

Standby Mode Timing

Question

Device

I

Cl 4S
.8S
o 8M
Dl6M
DEvaluation kit Emulator

I

In the following chart showing the timing at which the MCU
enters standby mode, is there any limit to the value of t?
In addition, at what timing should Vcc be dropped?
STBY

\

IJ

, ,, , ,
I, ,
L_ _1_

, '1

IfES

I

--!

I

t
Timing Chart of Returm.ng
from Standby Mode
Answer

I

I

l

.

Oscillation Restart
Stabilizing
Time
(t oSC =20 ms)

I

There is no limit to the value of to
-Eith~the STBY pin or RES pin can be Low first.
However,
the RES must~raised 20 msec or more behind the rising
edge of the STBY to restart operation.
The Vcc must be dropped after the STBY becomes Low. I t
should be returned to the specified level before the STBY
returns to High.

--

o Software
o SD
o SBC

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
* EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Ti tIe I
8-bit Single-chip
Microcomputer
Data Book
Other Data Document
Title I

Reference .Q& A Sheet

~
QA635-0l8B
QA6)5-020B

Supplement

I

~HITACHI
872

No. QA635-020B

I

HD6305XO/Xl/X2
HD6305YO/Yl/Y2

Type

Theme

Device

I oo

4S
.8S
o 8M
016M
Evalua tion ki t Emulator

o Software
o SD

0 SBC

Returning from Standby Mode

Questionl
Is there any method of returning from standby mode other
than reset-start?

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

*

Answer

I

No. In standby mode, the internal oscillator is stopped
and the MCU internal register values are destroyed. (The
contents of the Program Coun~are also destroyed.)
Therefore, only setting the STBY pin in High caused the MCU
to burst.
Be sure to perform a reset-start to return from standby
mode.

8-bit Single-chip
Microcomputer
Data Book
Other Data Document
Tit Ie I

I

S'i'lIT - - - - - - , \

----jIJf--~

L-.

\~_l\ \ l_L-__
\\
__ L_ ...

Timing Chart of Returning
from Standby Mode

Supplement

I

(

-jI!:I--_ _ _+:----j~

Oscillation Restart
Stabilizing
Time
(t osc =20 ms)

Reference Q & A Sheet

~
QA635-0l9B

I

I
~HITACHI
873

No. QA63S-0Z7B

I

Io

.8S
o 8M
Ol6M
4S
DEvaluation kit Emulator

Type

HD630SXO/XI/X2
HD630SYO/YI/YZ

Theme

Entering Low-Power-Consumption Modes

Device

Question'
Does executing the WAIT or STOP instruction always cause
the MCU to enter wait or stop mode?

o Software
o SD
o SBC

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-ch ip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Titlel

*

AnswerJ
No. The MCU en ters wait or stop mode only in the following
conditions.
When there is no interrupt requests.
--(The RES, STBY and INT pins are all High and the INT
interrup~tch and all interrupt bits are cleared. )
G) When the INTZ and internal interrupts are disabled by
the mask bits, and there is no other interrupts.
-(The RES, STBY and INT pins are all High, the INT
interrupt latch is cleared, and each interrupt mask
bit is set.)

CD

If the above conditions are not met, the MCU executes

the next instruction after the execution of the WAIT
and STOP instructions which requires 4 cycles.

Supplement

I

--

Other Data Document
Ti tIe I

Reference Q & A Sheet

~

In case G) above, the absence or presence of the INTZ and internal
interrupt requests has no effec t.

~HITACHI
874

No. QA63S-0Z8B

I

HD630SXO/Xl/XZ
HD630SYO/Yl/YZ

Type

Theme

Device

Io

.8S
4S
o 8M
Ol6M
DEvaluation kit Emulator

o Software
o SO
o SBC

Entering Wait Mode

Question

I

Are there any precautions about entering wait mode by the
WAIT instruction execution?

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SO
Data Buffer
Others
Al'plicable Manual
Title I

*

Answer

I

Note that the method of entering wait mode differs
Jepending on the returning method from wait mode.

~
Optl

frnm w.. it.

rnl..ion

an.nr

mmle

---

INT interrupt

INTZ, TIMER, TIMERZ, SCI

II rot~lrll

Executing
interrupt
routine

Clear the CCR I
bit. Set all interrupt mask bits.

Executing
an operation
after the
WAIT instruction*

Set the CCR I bit.
Set all interrupt
mask bits.

*.,

---

Clear the CCR I bit.
Set all mask bits except
the one for the interrupt
to be used.
--Do not cause any INT interrupts in wait mode.
Set the CCR I bit.
Set all mask bits except
the one for the interrupt
to be used.
-Do not cause any INT interrupts in wait mode.

Other Data Document
Ti tIe I

Reference Q & A Sheet

~

The INT interrupt requested (by detecting a falling edge
in the INT pin) before the WAIT instruction execution
has already been serviced.

Supplement

I

CCR (Condition Code Register) I bit: Interrupt mask bit (except software
interrupts)
Interrupt mask bits: INTZ - - - - Miscellaneous Register (MR: $OA) bit 6
TIMER - - - - Timer control Register (TCR: '$09) bit 6
TIMER2 - - SCI Status Register (SSR: $11 ) bit 4
SCI
SCI Status Register (SSR: $11) bit 5

I

--

~HITACHI
875

No. QA635-029B
Type

HD6305XO/Xl/X2
HD6305YO/Yl/Y2

Theme

Entering Stop Mode

Question

I

Device

I

.85
o 8M
Dl6M
DEvaluation kit Emulator

CI 45

I

Are there any precautions about entering stop mode by the
STOP instruction execution?

o Software
o SD
o SBC

Classification
Parallel Port
Serial Port
Timer /Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Ti tIe I

*

Answer

I

Note that the method of entering stop mode differs
depending on the returning method from stop mode.

~

Ope-

ration

from stop
mnd&

-INT

interrupt

--

INT2 interrupt

after a return

Executing
interrupt
routine

Clear the CCR I
bit. Set the INT2
interrupt mask bit
(MR6).

Executing
an operation
after the
STOP instruction*

Set the CCR I bit.
Set the INT2 inter
rupt mask bit
(MR6).

*.,

--

--

Clear the CCR I bit.
Set all mask bits except
the one for the interrupt
to be used.
-Do not cause any INT interrupts in stop mode.
Set the CCR I bit.
Set all mask bi ts except
the one for the interrupt
to be used.
Do not cause any INT interrupts in stop mode.

Other Data Document
Title I

Reference Q & A Sheet

~

--

The INT~terrupt requested (by detecting a falling edge
in the INT pin) before the STOP instruction execution
has already been serviced.

Supplement

I

CCR (Condition Code Register) I bit: Interrupt mask bit (except software
interrupts)
INT2 interrupt mask bit ----- Miscellaneous Register (MR: $OA) bit 6

--

~H'ITACHI
876

No. QA63S-038A
Type

HD630SXO/Xl/X2
HD630SYO/YI/Y2

Theme

I

Device

Io

4S
.8S
o 8M
Dl6M
DEvaluation kit, Emulator

OSBC

Returning Time from Stop Mode

Ques tion

I

How long is the internal delay when the MCU returns from
stop mode to operating mode by the interrupt INT or 1NT2·

--

Answer

o Software
o SD

I

is approximately 14 ms when a 4-MHz crystal oscillator
is used.
The internal delay time indicates the period whi Ie the CPU
execution is stopped and until the oscillating circuit
which was stopped in stop mode performs stabilized oscillation. This delay is automatically generated in the MCU.

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
* EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

It

Other Data Document
Title I

Reference

06-

A Sheet

~

Supplement

I

I
~HITACHI
877

No. QA635-039A
Type

Theme

HD6305XO/XI/X2
HD6305YO/YI/Y2

I

Device

I

.8S
CJ 4S
o 8M
Dl6M
DEvaluation kit Emulator

o Software
DSD

o SBC

Current Consumption in Low-Power-Consumption Mode

Question

I

Is the Icc (current consumption) in low-power-consumption
modes which is specified in the data sheets the value when
no load is applied to the I/O ports?

AnswerJ
Yes. Since the I/O ports maintain their output levels even
in stop and wait modes, the Icc will be increased by IOH or
IOL when a load is applied to the ports.
In standby mode, however, the I/O ports are in the high
impedance state, and the Icc is the same with or without
load.

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
* EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

Other Data Document
Ti tIe J

Reference Q & A Sheet

~

Supplement

I

•
878

HITACHI

No. QA63S-040A
Type

HD630SXO/XI/X2
HD630SYO/YI/Y2

Theme

1Device I

D4S

.8S

o Evaluation

o 8M
Ol6M
kit...L Emulator

o Software
o SD
OSBC

Accessing Not Used Areas on Memory Map

Ouestion

I

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interru--"t
A/D Converter
Oscillator
Reset
Low Power Consum~tion

What will happen if data is read from or written into the
area designated as Not Used on the memory map?

EPROM-on-ch~

Software
Evaluation Kit
Emulator
SO
Data Buffer
Others
Ap~licable Manual
TitleJ

*

Answer

I

Nothing will happen as long as the areas are not addresses
$13 to $lF.
Never access the $13 to $lF areas since they are used for
IC testing. Accessing (reading/writing) these areas causes
the MCU to burst.

Other Data Document
Title]

Reference.Q & A Sheet

~

Supplement

I

I
~HITACHI
879

No. QA635-023B

I

I

o 8M
.8S
D16M
D 4S
DEvaluation ki tL Emu la tor

Type

HD6305XO/Xl/X2
HD6305YO/Yl/Y2

Theme

Using Bit Manipulating Instruction for Output Ports

Question

Device

I

o Software
o SD
DSBC

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption

Is it possible to use the bit manipulating instruction for

the Data Registers of the output ports (ports A, B, C and G
used for output and output ports E and F)?

EPROM-on-ch~

Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Ap~licable Manual
TitleJ

*

Answer

I

Yes.
The bit manipulating instruction automatically reads out an
address, manipulates data in it and re-enters a result in
the address. This instruction can be used for any
read/write registers.
However, when data is read from the Port Data Register,
data output to port G is determined by a pin voltage. That
is, a voltage of less than 2.0 V due to the external circuit causes incorrect data to be output to port G. Design
the external circuit appropriately to prevent incorrect
data output.
To ports A, B, C, E and F, the logical levels stored in the
Port Data Register are output.

Supplement

I

The HD6305Xl/X2 and HD6305YI/Y2 do not have port E, F and G.

~HITACHI
880

8-bit Single-chip
Microcomputer
Data Book
Other Data Document
Title I

Reference Q

~

&

A Sheet

No. QA635-041B
Type

HD6305XO/Xl/X2
HD6305YO/YI/Y2

.8S
o 8M
4S
D16M
JDevice I oDEvaluation
kit Emulator

o Software
DSBC
o SO

Statuses of Address Bus, Data Bus and Control Line when the Internal
Address Space is Accessed

Theme

Question

I

What values are output to the address bus, data buses and
control line when the CPU access the internal address
space?

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SO
Data Buffer
Others
Applicable Manual
Title I

*

Answer

I

The same value as the accessed data is output to the
address bus and control line, whether the CPU accesses
the internal address space or external address space
and whether the CPU reads or writes data.
However, the data buses are in the high impedance state
when the CPU read data from the internal address space,
though the same value as the data written into the
internal space by the CPU is output to the data buses.

Other Data Document
Title I

Reference Q

&

A Sheet

~

Supplement

I

~HITACHI
881

.HITACHI
882

HD630S/HD63LOS SERIES HANDBOOK

Section Eight

APPENDIX:
Thchnical Q and A (Part II)

8-Bit Single-Chip Microcomputer

HD630SUO,HD630SVO

~HITACHI
883

•
884

HITACHI

PREFACE

The HD6305UO and HD6305VO are microprogram-controlled8-bit
single-chip microcomputers that use CMOS 2.5-pm technology.
These models are 40-pin versions of the HD6305XO.

The CPU,

memory, timer, serial communications interface (SCI), and
I/O are all integrated into one chip.

The only difference

between the HD6305UO and the HD6305VO lies in their memory
capacities.

The former has a 2-kbyte ROM and a l28-byte

RAM; the latter has a 4-kbyte ROM and a 192-byte RAM.
The CMOS technology enables these models to operate over a
wide range of supply voltages (Vcc operates in the 3 V - 6 V
range at operating frequencies of 0.1 MHz - 0.5 MHz) with
less power consumption.

The 10w-power-consumption modes

(STOP, WAIT, and STANDBY) available with these models permit
further power savings.
The instruction set includes DAA (decimal adjust instruction), and STOP and WAIT (used to enter the corresponding
10w-power-consumption modes), in addition to the HD6805
instruction set.

The minimum instruction execution time is

0.5 psec/cyc1e (f=2 MHz), permitting high-speed operation •

•

HITACHI
885

HOW TO USE THIS MANUAL
This TECHNICAL QUESTIONS AND ANSWERS is a user reference manual that has been compiled in question-andanswer form.

It is based on technical inquiries from

HITACHI microcomputer users.
This manual should be used in conjunction with the
appropriate data book (which you should already have) .
You can make best use of this manual either by:

reading

all of it before you start to design any microcomputerapplied products, in order to strengthen your technical
background; or referring to it during the actual design
process, using it to help you solve specific problems
that may arise.
Although some of the items supplement the data book,
most of them are inquiries from the users.

In order to

meet future needs, we are prepared to increase the
number of Q & A items and to update the data book.

~HITACHI
886

Contents
Q & A No.
Parallel Port
1 Outputting Data from Ports after a Reset
(2) Serial I/O Pin Status
(3) Using Port D when Serial I/O is Used

c==(1)Serial
Por~
Designating Input
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)

or Output Operation of Serial
I/O Clock Pin
Using SDR (SCI Data Register) when Serial I/O is
not Used
SSR7 (SCI Interrupt Request Bit) Set Timing
Clearing SSR (SCI Interrupt Request Bit)
Accessing SDR (SCI Data Register)
Transmitting and Receiving Data Simultaneously
through Serial I/O
Notes on Receiving Data through SCI in External
Clock Mode
SCI Operation in External Clock Mode
Initializing the Transfer Clock Generator
Prescaler
SCI Prescaler Initialize Timing and Clock Output
Timing

LTimer/Counter
(1) Reading/Writing Data from/into the TOR during
Timer Operation
(2) Timer Count-down Timing when External Clock is
Input
(3) Timer Clock Input Source
(4) Timer 2 Interrupt Cycles

Pa2e

QA635-301A
QA635-302A
QA635-303A

889
890
891

QA635-304A

892

QA635-305A

893

QA635-306A
QA635-307A
QA635-308A
QA635-309A

894
895
896
897

QA635-310A

898

QA635-311A
QA635- 312A

899
900

QA635-313A

901

QA635-314A

902

QA635-315A

903

QA635-316A
QA635-317A

904
905

QA635-318A

906

QA635-319A
QA635-320A

907
908

QA635-321A
QA635-322A
QA635-323A

909
910
911

QA635-324A
QA635-325A

912
913

QA635-326A

914

QA635-327A

915

BUS Interface
Interrupt
lime from Interrupt Occurrence to Interrupt
Servicing Routine Execution
(2) Schmitt Trigger Circuit of Interrupt Pin
(3) Servicing an Interrupt after a Reset (CCR I bit
initializi!!£2.
(4) Servicing INT External Interrupt while Masked
(5) Servicing INT2 External Interrupt while Masked
(6) Servicing SCI (Serial I/O) Interrupt while
Masked
(7) Servicing Timer Interrupt while Masked
(8) Servicing External Interrupt after Returning
from Standby Mode
(9) Servicing Multiple Interrupts

(1)

A/D Converter
Oscillator
(1) Timing of External Clock Input to the Oscillator
and E Clock Timing

I

~HITACHI
887

Reset
I
(1) Port Status at a Reset
Low Power Consumption
I
(1) Entering Low-Power-Consumption Modes
(2) Entering Wait Mode
(3) Entering Stop Mode
(4) Returning Time from Stop Mode
(5) Standby Mode Timing
(6) Returning from Standby Mode
(7) Executing an Instruction when Entering Standby
Mode
(8) Current Consumption in Low-Power-Consumption
Mode

Q & A No.

Page

QA635-328A

916

QA635-329A
QA635-330A
QA635-331A
QA635-332A
QA635-333A
QA635-334A
QA635-335A

917
918
919
920
921
922
923

QA635-336A

924

QA635-337A

925

QA635-338A

926

EPROM-on-chip
Software
I
(1) Using Bit Manipulating Instruction for Output
Ports
(2) Accessing Not Used Areas on Memory Map
Evaluation K i t ]
Emulator

I

SO.

r

Data Buffer
Others

~HITACHI
888

No. QA63S-301A

1 1

Type

HD630SUO
HD630SVO

Theme

Outputting Data from Ports after a Reset

Ouestion

Device

• 8S
a8M
a 4S
a16M
a Evaluation kit Emulator

I

Which operation should be performed first to output data
through input ports A, B, C and D after a reset?; storing
data in the Data Register of the ports or designating the
corresponding DDR (Data Direction Register)?

Answer

I

Store the data to be output in the Data Register first,
and then designate the corresponding DDR to data output
(DDR=l).
Since a reset causes the Data Register to become 0, if the
DDR is designated to data output before data is stored in
the Data register, 0 is output to the ports.

a Software
aSD
a SBC

Classi fica tion
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

*

HD630SUO, HD630SVO
Data Sheets
8-bit Single-Chip Microcomputer Data Book
Other Data Document
Title I

Reference ~ & A Sheet

~
QA63S-328A

Supplement

I

~HITACHI
889

No. QA63S-302A

I

HD630SUO
HD630SVO

Type

Theme

Device

Io

• 8S
o 8M
O16M
4S
DEvaluation kit Emulator

Serial I/O Pin Status

Question

1

After ports D3 to Ds are respectively used as CK, Rx
and Tx pins of the SCI (serial I/O), these ports are
specified as I/O pins using the SCR (SCI Control Register)
(SCR7=SCR6=SCRS=0). What is the value of the DDR (Data
Direction Register) when the ports are used as I/O pins?

Answer

I

The DOR retains the value for the SCI, as shown below.
Pin
D3/Tx
D4/Rx

Os/CK

OOR value for SCI
1 (output port)
0 (input port)
0 (input port)
1 (ou tpu t port)

Notes
When Tx is used SCR7=1.
When Rx is used SCR6=1.
In the case of external clock
source mode.
In the case of internal clock
source mode.

Even when the SCR value is changed after the SCI is used,
the DDR value shown in the above table is maintained. When
using D3 to DS as I/O ports, rewrite the DDR value using
software.

Supplement

I

SCR (SCI Control Register: $0010)
7
5
4
3
2
1
0
6
LSCR7 SCR6 I SCRsl SCR4 I SCR3 I SCR2 I SCRI I. SCRO
Clock source selection bit
SCI data input enable bit
SCI data output enable bit

f

t

~HITACHI
890

o Software
o SBC

OSD

Classification
Parallel Port
* Serial Port
Timer /Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Ti tIe I
HD630SUO, HD630SVO
Data Sheets
8-bit Single-Chip Microcomputer Data Book
Other Data Document
Title I

Reference Q & A Sheet

~

No. QA63S-303A
Type

HD630SUO
HD630SVO

Theme

I

Device

I oo

.8S
08M
4S
016M
Evaluation kit Emulator

o Software
o SBC

OSD

Using Port D when Serial I/O is Used

Question

I

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
A~plicable Manual
Title I

*

When ports D3 to DS are used as the SCI (serial I/O), is it
possible to use ports DO to D2 and D6 as usual I/O pins?

Answer

I

Yes. These ports can be used as usual I/O pins because
they are independent of the SCI. The ports affected by the
SCR (SCI Control Register) when the SCI is used are ports
D3 to DS only. Input and output functions of ports DO
to D2 and D6 are selected using bits 0 to 2 and 6 of
port D's DDR (Data Direction Register).

HD630SUO, HD630SVO
Data Sheets
8-bit Single-Chip Microcomputer Data Book
Other Data Document
Title I

Reference 0 & A·Sheet

~

Supplement

I

~HITACHI
891

No. QA635-304A
Type

J

HD6305UO
HD6305VO

Theme

Device

Io

D8M
• 8S
D 16M
4S
DEvaluation kit Emulator

Designating Input or Output Operation of Serial I/O Clock Pin

Question

I

Does setting 0 or 1 in the corresponding DDR (Data
Direction Register) enable the clock pin CK to be
designated as an input or output pin when the SCI
(serial I/O) is used?

Answer

o Software
o SBC

DSD

I

No. Bits 4 and 5 (SCR4. 5) of the SCR (SCI Control
Register) designate the CK pin as input or output when
the SCI is used, not the DDR.
As shown below, the combination of bits 4 and 5 enables the
SCI clock source selection, determining whether the CK pin
is specified as an input or output pin.
SCR5 SCR4 Clock source
CK pin (port Ds )
0
0
Used as I/O pin (according t(
0
1
the DDR)
1
0
Internal
Clock output (DDR out~ut)
1
External
1
Clock input (DDR input)

Classification
Parallel Port
* Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buff~r
Others
Applicable Manual
TitleJ
HD630SUO, HD6305VO
Data Sheets
8-bit Single-Chip Microcomputer Data Book
Other Data Document
Title I

~

Note: The selection of input or output is made by the DDR
when SCR5 is 0 and SCR4 is 0 or 1.

Supplement I
SCR (SCI Control Register: $0010)
7
6
5
4
3
2
I SCR7 I SCR6 I SCRsl SCR4 I SCR3 I SCR2

r

1

0

I SCRI I SCRO I

Clock source selection bit

~HITACHI
892

Reference Q & A Sheet

~

No. QA635-305A
Type

Theme

HD6305UO
HD6305VO

I

Device

I

.8S
C18M
C1l6M
C14S
CI Evaluation kit Emulator

Using SDR (SCI. Data Register) when Serial I/O is not Used

Question

I

Is it possible to use the SDR (SCR Data Register: $0012) as
a general-purpose register when the SCI (serial I/O) is not
used?

Answer

CI Software
CI SD
CI SBC

I

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

*

Yes. The SDR can be used as a general-purpose register
when the SCI is not used i.e., when the SCI clock is
stopped with SCR4 to SCR7 being O.
Other Data Document
Title I

Reference Q & A Sheet

~

Supplement

I

SCR (SCI Control Register: $0010)
7
6
5
3
1
0
4
2
I SCR7 I SCR6 I SCR5 I SCR4 I SCR3 I SCR2 I SCRI I SCRO I
Clock source selection bit
SCI data input pin enable bit
SCI data output pin enable bit

I

r

$

HITACHI
893

.--~------------

-~~-

No. QA635-306A
Type

I

HD630SUO
HD630SVO

Theme

Device

Io

• 8S
o 8M
O16M
4S
DEvaluation kit, Emulator

SSR7 (SCI Interrupt Request Bit) Set Timing

QuestionJ
After 8-bit data transmitting or receiving through the SCI
(serial I/O) is completed, SSR7 (SCI interrupt request bit)
of the SSR (SCI Status Register) is set. At what timing is
this setting performed?

Answer

o Software
o SBC

OSD

I
-

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

*

SSR7 is set at the rising edge of the 8th CK (serial clock)
as shown below.

~P<'ViOU" d.,.
Serial clock
(DS/CK)

~

Ou'pu' da<.
(D /Tx)
''I
3
----./

LSB

MSB

I

Input data
latch timing
(D/RX)

Other Data Document
Title I

I

I

1 I

I

I

SSR7

Reference Q & A Sheet

~

Supplement

I

SSR (SCI Status Register: $OOll )
7

6

5

4

3

2

1

0

I· SsE SSR6 I SSRS I SSR4 I SSR3 1><1><1><1
SCI interrupt request bit

~HITACHI
894

No. QA635-307A
Type

I

HD6305UO
HD630SVO

Theme

Device

I oo

• 8S
o 8M
4S
o 16M
Evalua tion kit Emulator

Clearing SSR (SCI Interrupt Request Bit)

Question

I

After data is transmitted or received through the SCI
(serial I/O), SSR7 (SCI interrupt request bit) is set
to 1. At this time, i f 0 is set in SSR7 by software
to clear the bit, is it possible to transmit or receive
the next data?

Answer

o Software
o SBC

DSD

I

No. When 0 is set in SSR7 by software, this bit is
cleared, and the next data transmitting and receiving cannot be performed. SSR7 is cleared under the following conditions.
CDWhen data is read from or written into the SDR (SCI Data
Regis ted.
(After SSR7 is cleared and the octal counter is reset,
the next data transmitting/receiving is executed.)
When 0 is set in SSR7 by software.
(The SCI's octal counter is not reset, enabling no data
transmitting/receiving.)
Therefore, repeat data reading or writing from/into the SDR
to transmit/receive data repeatedly.
Dummy-read the SDR before receiving the first data.

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface

'"

Interru~t

A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

Other Data Document
Title I

<1><1><1
LSCI interrupt request bit

~HITACHI
895

No. QA635-30SA
Type

Theme

I

HD6305UO
HD630SVO

Device

Io

.8S
o SM
4S
O16M
DEvaluation kit Emulator

o Software
o SBC

OSD

Accessing SDR (SCI Data Register)

Question

I

Classification
Parallel Port
Serial Port
* Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Tit1eJ

What will happen if data is read from or written into the
SDR (SCI Data Register) while another data is being
transmitted or received through the SCI (serial I/O)?

AnswerJ
Normal operation can not be guaranteed for either
transmission or reception. Do not access the SDR during
data transmitting or receiving since the SCI becomes
disabled after the access (the MCU must be reset to use
the SCI again).

Other Data Document
Title I

Reference Q & A Sheet

~
QA635-312A

Supplement

I
SDR (SCI Data Register: $0012)
7

Receive

_I MSB I

6

I

5

I

4

3

1

I

1

2

I

~HITACHI
896

0

I LSB I

--Transmit

No. QA635-309A
Type

HD6305UO
HD6305VO

Theme

I

Device

Io

• 8S
o 8M
4S
o 16M
DEvaluation kit Emulator

o SBC

Transmitting and Receiving Data Simultaneously through Serial I/O

Ques tion

I

Is is possible to transmit and receive data simultaneously
through the SCI (serial I/O) by using the internal clock
for transmitting and the external clock for receiving, or
vice versa?

Answer

o Software
OSD

Classification
Para lIel Port
Serial Port
Timer/Counter
BUS Interface

*

Interr~t

A/D Converter
Oscillator
Reset
Low Power Consu~tion
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

I

No. Only one clock source can be selected as the SCI
transfer clock. Simultaneous data transmission and reception using two transfer clocks are impossible.
When a single clock source is used, data can be transmitted
and received at the same time.
Other Data Document
Title I

Reference J( & A Sheet

~

Supplement

I

~HITACHI
897

Ne. QA635-310A
Type

HD6305UO
HD6305VO

Theme

I

Device

Io

• 8S
o 8M
D16M
4S
DEvaluation kit, Emulator

Notes on Receiving Data through SCI in External Clock Mode

Question

I

What should we pay attention to when using the external
clock to receive data through the SCI (serial I/O)?

Answer

o Software
o SBC

OSD

I

The external transfer clock source does not enable
receiving side to check when data is transmitted.
Therefore, it is necessary to read out data in the
Data Register) as soon as the data is received, to
for receiving the next data.
Whether 'or not receiving has been completed can be
by an SCI interrupt or by testing bit 7 of the SSR
Status Register) by software.

Classification
Parallel Port
Serial Port
* Timer/Counter
BUS Interface
InterruJ>t
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

the
SDR (SCI
prepare
checked
(SCI

Other Data Document
Title I

Reference Q & A Sheet

~

Supplement

I

SSR (SCI Status Register: $0011)
7
6
5
4
3
2
1
0
SCSSR61 SSR51 SSR41 SSR31><1><1><1

I

SCI

i",mup' «qU""

hi,

(0'

'0 '"q",," )

1: Yes

~HITACHI
898

No. QA63S-3llA
Type

I

HD630SUO
HD630SVO

Theme

Device

o 4S • 8S
o 8M
o 16M
DEvaluation kit Emulator

SCI Operation in External Clock Mode

Question

I

The SCI (serial I/O) is in external

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Title I

*

cLoc~mode;

If the external clock is applied to the CK pin before the

CPU writes/reads data into/from the SDR (Serial Data
Register) after the one-byte data transmitting/receiving is
completed, will the SCI start the next data
transmitting/receiving?

Answer

o Software
o SBC

OSD

I

No. The SCI does not start transmitting or receiving the
next data until the CPU writes/reads data into/gom the
SDR. That is, any clock signal applied to the CK pin
before the CPU accesses the SDR will be ignored.
Other Data Document
Title I

Reference Q & A Sheet

~

Supplement

I

The CK pin can also used
as DS pin. I t is controlled by bits 4 and S
of the SCR (SCI Control
Register).

SCRS

SCR4

0
0

0
1

1

0

1

1

Clock
source

DS pin

-

Used as I/O p.in (accordin~
to the DDR)
Internal Clock output (DDR output)
External Clock input (DDR input)

-

~HITACHI
899

No. QA63S-312A
Type

Theme

I

HD63CSUO
HD630SVO

Device

Io

• BS
o BM
o 16M
4S
DEvaluation kit Emulator

o Software
o SBC

OSD

Initializing the Transfer Clock Generator Prescaler

. QuestionJ
The pres caler of the SCI transfer clock generator is initialized by reading/writing data from/into the SDR (SCI
Status Register) or by setting 1 in SSR3 (SCI Status
Register bit 3). What is the difference of the initialization performed by these two methods?

Answer j

Classification
Parallel Port
Serial Port
Timer/Counter
BUS Interface
Interrupt
A/D Converter
Oscillator
Reset
Low Power Consumption
EPROM-on-chip
Software
Evaluation Kit
Emulator
SD
Data Buffer
Others
Applicable Manual
Ti tIe I

*

There are differences in the following points.
(1) When data is read/written from/into the SDR, the SCI

octal counter is initialized at the same time the
prescaler is initialized. This causes the SCI to start
transmitting or receiving the next data.
(2) When 1 is set in SSR3, only the prescaler is initialized. The SCI does not start data
trasmitting/receiving.
SSR3 is the bit to be used to initialize the prescaler when
the transfer clock generator is utilized as Timer 2.

Other Data Document
Ti tIe I

Reference Q & A Sheet

~
QA63S-30BA

Supplement

I

SSR (SCI Status Register: $0011 )
7

6

5

4

3

2

1

0

I SSR7 I SSR6 I SSRS I SSR4 I SSR3C>Plementj
SSR (SCI Status Register: $0011)
7
6
5
2
4
3
1
0
I SSR7 I SSR6 I SSRS I SSR4 I SSR3 l>