1988_Hitachi_HMCS400_Series_Handbook 1988 Hitachi HMCS400 Series Handbook

User Manual: 1988_Hitachi_HMCS400_Series_Handbook

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HMCS400 SERIES
HANDBOOK
• User's Manual
• Software
Application Notes
• Hardware
Application Notes

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MEDICAL APPLICATIONS

Hitachi's products are not authorized for use in MEDICAL APPLICATIONS,
including, but not limited to, use in life support devices without the written
/ consent of the appropriate officer of Hitachi's sales company. Buyers of
, Hitachi's products are requested to notify Hitachi's sales offices when planning
to use the products in MEDICAL APPLICATIONS.

When using this manual, the reader should keep the fullowing in mind:

1. This manual may, wholly or partially, be subject to change without notice.
All rights reserved: No one is permitted to reproduce or duplicate, in any
form, the whole or part of this manual without Hitachi's permission.
3. Hitachi will not be responsible for any damage to the user that may result
from accidents or any other reasons during operation of his unit according
to this manual.
4. This manual neither ensures the enforcement of any industrial properties
or other rights, nor sanctions the enfurcement right thereof.
2.

5. Circuitry and other examples described herein are meant merely to indicate characteristics and performance of Hitachi semiconductor-applied
products. Hitachi assumes no responsibility for any patent infringements
or other problems resulting from applications based on the examples
described herein.
6.

March 1988

No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.

© Copyright

1986. 1988. Hitachi America Ltd.

Printed in U.S.A.

ZTAT is a registered trademark of Hitachi America, Ltd. 1986, 1988

HMCS400 SERIES

User's Manual

Software Application Notes

Hardware Application Notes
Hitachi Sales Offices .....................Section 3 Page 346

HMCS400 SERIES

Section One

User's Manual

PREFACE
The HMCS400 Series is a CMOS 4-bit single-chip microcomputer which contains
variety of on-chip resources such as CPU, ROM, RAM, serial interface, and I/O.
The HMCS400 Series, advanced product of the HMCS40 Series, realizes high-speed
speed operation, high-level function and program-productive efficiency.
addition, it adopts the latest CMOS high break-down process and can drive
fluorescent display tube directly.

For additional information reference:
-Section 2, HMCS400 Series Software Application Notes
-Section 3, HMCS400 Series Hardware Application Notes

In

CONTENTS
1.

2.

3.

4.

5.

OVERVIEW. . . • • . • • • • . . . . . • . . . . . • . . . • . • • . . . . . . . . . . . . . . . . . • . . • . • • . • . . • . . . . • • . .

1

1.1

Features .•..•...••.•....... '" ......•. ....... ..••.... .•.. ..••. .........

1

1.2

Block Diagram..........................................................

3

1.3

Pin Description........................................................

5

INTERNAL STRUCTURE AND ITS OPERATION .•....•.•............•.•....•..•...•.•

6

2. 1

ROM Memory Map ..•..•.......•..••.....•.••.•...•.•.....•.....•..••....•.

6

2.2

RAM Memory Map .•.......••..••............•..•....•..•.•...••...........

9

2.3

Registers and Flags •.•..••..•......••...•.......•...•.••.....•...••....

14

2.4

Interrupt

16

2.5

Serial Interface ...........••.........•.........•.........•..••........

22

2.6

Timer..................................................................

27

2.7

Input /Output ........•................•..............•..........•..•..•.

31

2.8

Reset ....................•.....••........•.•.......•........•....•..•..

36

2.9

Internal Oscillator Circuit ............................................

37

2.10 Low Power Dissipation Mode ......••.•.....•.........•......•....•.•.•...

40

INSTRUCTION SySTEM........................................................

44

3.1

RAM Addressing Mode....................................................

44

3.2

ROM Addressing Mode and P Instruction..................................

44

3.3

Instruction Set ..•...•.......•..........•............•.....•....••.•...

48

3.4

Instruction Table......................................................

53

3.4.1

Functional Table .•...................•..........•.......•..........

53

3.4.2

Alphabetical Order Table ......•.•....•....•••...••.•....••.•....••.

56

3.4.3

Object Code Table ..................................................

58

PIN ARRANGEMENT AND PACKAGE DIMENSION .•..••...........•.•.•.•••...•...•...

60

4.1

Pin Arrangement •..•...•.......••...•.•.••......•...•...•...•....•.....•

60

4.2

Package Dimension .....•...••..•....•.....•. '.' . . . . . . • . . . • . . • . • • • . • • • . • .•

61

ELECTRICAL CHARACTERISTICS ....•..........•..•..•.•.•••...•.............•..

63

5.1

HMCS402/404/408 Absolute Maximum Ratings ............................... 63

5.2

HMCS402C Electrical Characteristics ....••...••.••.•....•..•..•..•••.••• 64

5.3

HMCS402CL Electrical Characteristics ................................... 72

5.4

HMCS402AC ·Electrical Characteristics ................................... 78

5.5

HMCS404C Electrical Characteristics .................................... 84

5.6

HMCS404CL Electrical Characteristics ................................... 92

5.7

HMCS404AC Electrical Characteristics ................................... 98

5.8

HMCS408C Electrical Characteristics .•....••.......•...............•.... 104

5.9

HMCS408CL Electrical Characteristics

108

5.10 HMCS408AC Electrical Characteristics
5.11 HMCS4l2/4l4 Absolute Maximum Ratings

112
118

5.12 HMCS4l2C Electrical Characteristics .•.•••..••....•••••••••..•••••.•.••

119

5.13 HMCS4l2CL Electrical Characteristics •.•••••.•.•••..•.•....•••..•••.••.

122

5.14 HMCS4l2AC Electrical Characteristics •.••••••.••.••.•.••••..•••••••••••

125

5.15 HMCS4l4C Electrical Characteristics .••.•.•.•••...••••..•.••••.•••.•••• 130

6.

5.16 HMCS4l4CL Electrical Characteristics ••...•••.••...•.•..•••••.••••••.••

133

5.17 HMCS4l4AC Electrical Characteristics

136

ASSEMBLY LANGUAGE........................................................
6.1

7.

Symbols and Abbreviations ••••..••••....••..•...•.••.•..•.•..•.•••...•.

141
141

6.2

Instruction Formats .••..•.•...........•..............•..•............. 141

6.3

Execution Instructions •..••.•.••••.••.•....••..•.•..•••••.•••••.•..••• 147

APPLICATIONS. • • • . . • • . . • . • . • • . • • • . . . . . • • • . . . . . . . . . . • . • . . . . • . . • . • • . • • . • • . ..
7.1

Example of Subroutine Program .....••.•.••••..•...•.•••.•....•.•...•..•
• • . • • . • . • • . • • • • • • • • • . • . . . • . • • • • . . • . • . • • • • • . • • . . • • • . • . •.

247
247

7.1.1

RAM Clear

248

7.1.2

RAM Data Transfer

249

7.1.3

RAM Data Exchange

250

7.1.4

Decimal Addition .•••••••••..•..•.•..•...............•......•.....

251

7.1.5

Decimal Subtrac tion ...••..•.••.•••.•...•••••..••..••..••.•.••.••. 252

7.1.6

Interrupt Service .••..•••.•..••.•..••..•.•.....••......•.•..•....

253

7.1. 7

Display Tube Dynamic Drive ••••.•••.•.••..•.•..••.....•...••..•..•

254

7.1.8

Keyboad Scan ...••..••••••.••.•••........................•........

25'9

7.1.9

Timer A Application Example •••••.•..•••.••.••••••.•••••••.•••••.•

260

7.1.10

Timer B Application Example

264

7.1.11

Serial Interface Application Example .............................

267

7.2

ALU (Arithmetic Logic Unit) and Decimal Adjust Instruction ..•......•... 270

7.3

Application of Logical Operation ........................... ..... .... ... 272

7.4

Checking Operation Frequency •••••.••..•••• ~ ..••••••.•••••••••••.••.•..

273

7.5

Watchdog Timer-System burst preventing circuit ••••••.•••••••.....•••••

274

7.6

Auto Reset Circuit ...................................................... 275

7.7

Manual Reset Circuit ................................. ,.................

277

7.8

Serial Data Transfer between HMCS402/404/408 and Other MPUs ••.••••••••

278

7.9

Reversing a String of Transmit/Receive Data in a Serial Interface
(LSB-MSB)

•.••••.••• , •••..••.•.•.••..•.•...• , •.•....•....•••..•.••.•••.279

7.10 Expansion of Input Ports .•••••••••••••.•••.•••.••.• , '. • • • • • • • • • • • • • • • • .• 281
7.11 A/D. Conversion Circuit (I) .•. High speed version ••••••••••••••..•.••• 282
7.12 A/D Conversion Circuit (II) ••. Low speed version ••'................... 28.4
7.13 Fluorescent. Display Tube Drive Application (1)'. ~ ••••..•••. ; •.• ';,. . • •.• 285

7.14 Fluorescent Display Tube Drive Application (II) .....•.•...•..•.••...... 292
8.

USER NOTES ............................•................................... 299
8.1

Precautions on Using W Register ......•.........•............•.......•.. 299

8.2

Precautions on the Contents of RAM and Register after Reset ............ 300

8.3

Notes on Unused Pins .................................................•. 301

8.4

Notes on Board Design of on Oscillation Circuit ........................ 302

8.5

Automatic Paging Facility of Cross Assembler for the HMCS400 Series .... 303

8.6

Precautions for Port Mode Register (PMR) Setting ....................... 305

9.

Difference between EPROM in-package type, EPROM on-package type and
Mask ROM type .................................•.......••.................. 307

10.

EPROM IN PACKAGE TYPE SINGLE CHIP MICROCOMPUTER HD4074008
(Under Development)

............................... " ..•................. 309

10.1

Overview ............................................................. , 309

10.2

ROM Memory Map .............................•.............•...•........ 315

10.3

RAM Memory Map ..•................................................•.... 316

10.4

Absolute Maximum Ratings ...................•........•...............•. 319

10.5

HD4074008 Electric Characteristics ..................•....•............ 320

10.6

Programming the On-chip Programmble ROM
324
ZTAT MCU On-chip PROM Characteristics and Precautions for Applications 329

10.7
11.

EPROM ON PACKAGE TYPE SINGLE CHIP MICROCOMPUTER HD6l4P080S/HD6l4P0160S •.. 333

11.1

Overview ••.........................................................•.. 333

11.2

ROM Memory Map .............•.......................................... 337

11.3

RAM Memory Map ....................................•................... 337

11.4

Precautions on Using EPROM on-Package Type Microcomputer .............. 341

11.5

Absolute Maximum Ratings ••....................•..............•.......• 341

11.6

HD6l4P080S/HD6l4P0160S Electrical Characteristics .•..............•.... 342

12.

EPROM ON PACKAGE TYPE MICROCOMPUTER HD6l4P180/HD40P4l8l .•..•..•.....•••.. 348

12.1

Overview .............•..................•...............••..•..•..•... 348

12.2

ROM Memory Map .•......••...............•.•...........................• 352

12.3

RAM Memory Map ..•...........•..............................•...•..•... 352

12.4

Precautions on Using EPROM on-Package Type Microcomputer ......•...•••. 356

12.5

Absolute Maximum Ratings •.............•....•...•.•....•.........•....• 357

12.6

HD6l4P180 Electrical Characteristics •...••...•.•..•...•........•.•...• 358

12.7

HD40P4l8l Electrical Characteristics .................................. 363

13.

PROGRA~

DEVELOPMENT PROCEDURE AND SUPPORT SYSTEM • ~ ••••••••••• " • • • ••• • •• ••

~66

13.1

Overview. • • • • • • • • . • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 366

13.,2

Development System •••••.•••••••••••••••••••••••••••••••••••••••

13.3

Emulator •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 373

13.4

Single Chip Microcomputer ROM Ordering Procedure •••••••••••••••••••••• 384

u ' ••••

369

Symbols and Abbreviations
PC

Program Counter

SP

Stack Pointer

I/E

Interrupt Enable Flag

IFO

INTO Interrupt Flag

IFl

INTI Interrupt Flag

IFTA

Timer A Interrupt Flag

IFTB

Timer B Interrupt Flag

IFS

Serial Interface Interrupt Flag

IMO

INTO Interrupt Mask

IMI

INTI Interrupt Mask

IMTA

Timer A Interrupt Mask

IMTB

Timer B Interrupt Mask

IMS

Serial Interface Interrupt Mask

PMR

Port Mode Register

SMR

Serial Mode Register

TMA

Timer Mode Register A

TMB

Timer Mode Register B

TCA

Timer Counter A

TCBL

Timer Counter B Lower Digits

TCBU

Timer Counter B Upper Digits

TLRL

Timer Load Register Lower Digits

TLRU

Timer Load Register Upper Digits

SRL

Serial Data Register Lower Digits

SRU

Serial Data Register Upper Digits

ST

Status

CA

Carry

A

Accumulator

B

B Register

W

W Register

X

X Register

SPX

SPX Register

Y

Y Register

SPY

SPY Register

M

Memory (RAM)

MR

Memory Register

RAM

Random Access Memory

ROM

Read Only Memory

R

Data I/O Pin or Data I/O Regist.er

D

Discrete I/O Pin or Discrete Latch

I
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OVERVIEW

1.

1 .1

Features
The new CMOS 4-bit microcomputer HMCS400 series satisfies the microcomputer

system which needs a large program capacity and high-level functions to meet
advanced applications.

The HMCS400 series offers high software-productive

architecture, enhanced peripheral functions, high speed instruction execution,
and support tools.

It also has the characteristics of low power dissipation

with CMOS process, and it is applicable to the product which needs low power
dissipation as portable machine.

o

o
o
o
o
o

o

o

o

o

o
o

o

o

Process: CMOS
Architecture is compatible with the HMCS40 series for easy replacement.
One cycle per instruction execution utilizing 10 bits per instruction
Powerful ROM and RAM addressing capability
16 nesting levels
Reinforced instruction system including logic arithmetic
operating instruction, BCD arithmetic operating instruction, and pattern
generating instruction
Reinforced interrupt function
Five interrupt levels (External : 2, Timer/
Counter: 2, Serial Interface 1)
8-bit serial interface
Two timer/counters
o

8-bit free running timer

o

8-bit autoreload timer/event counter

58 I/O lines (including 26 High Voltage (40V) I/O Lines); HMCS402/404/408
36 I/O lines (including 24 High Voltage (40V) I/O Lines); HMCS412/414
High-speed instruction execution HMCS408AC/412AC/414AC: 0.89~s
HMCS402AC/404AC : 1.29~s
EPROM on-package type HD614P080S/HD614P0160S
HD614P180/HD40P4181
EPROM in-package type HD4074008

HITACHI

"-J

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()

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l:

Table 1-1

HMCS400 Series Function List

Type Name
UJ

Supply Voltage (V)

HMCS402C/CL/AC

HMCS404C/CL/AC

HMCS408C/CL/AC

HMCS412C/CL/AC

HMCS414C/CL/AC

5/3/5

5/3/5

5/3/5

5/3/5

5/3/5

u--------------------------------------------------------------------------------------------------"l:! Max. I/O Terminal
VCC-40
VCC-40
VCC-40
VCC-40
VCC-40
.~ Voltage (V)

~----~~--------------------~---------------------------------------------------------------------

~ Operating Temperature
~ Range (OC)

-20 to +75

-20 to +75

-20 to +75

-20 to +75

-20 to +75

H ~--------------------------~----------------------------------------------------------------------oo..c:

...:IU

Package

Memory

ROM (vits)
RAM

(bits)

I/O Ports
Interrupt

DP-64S,FP-64

DP-42,DP-42S

DP-42,DP-42S

2,048 x 10

4,096 x 10

8,192 x 10

2,048 x 10

4,096 x 10

160 x 4

256 x 4

512

160 x 4

160 x 4

58

58

58

36

36

2

2

2

2

2

1

1

x 4

2

2

2

Serial
Interface

1

1

1

Instruction

99

99

99

98

98

Timer

8 bit x 2

8 bit x 2

8 bit x 2

8 bit x 1

8 bit x 1

SCI

8 bit x 1

8 bit x 1

8 bit x 1

EPROM on the Package
Type

HD614P080S

HD614P080S

HD614P080S
HD614P0160S

HD614P180
HD40P4181

HD614P180
HD40P4181

EPROM in the Package
Type

HD4074008

HD4074008

HD4074008

s::

a

-rt

.....
U

r..

DP-64S,FP-64

Timer/Counter

UJ

§

External

DP-64S,FP-64

1.2 Block Diagram
1.2.1

HMCS402/404 Block Diagram
R.o/R•• /R.21
SCi 51 SO

RESET

TEST osc,ose,

T1"0,--------,

Ru
Ru

ROM

R"
Roo

HMCS402CfCL/ AC; 2048x 10 bits
HMCS404C/Cll AC; 4096x 10 bitl

""
""

R"
Roo

Rn
Rn
Rn

R"
Ru

PC

""""

Roo
Ru
R"
R..

Roo

~::~ High Voltage Pins

1.2.2

HMCS408 Block Diagram
R.o/R .. ,;R,ul
SCi 51 SO
RESET

TEST ose, OSC,

TTOr--------.

Ru

ROM

R"
R"

8192

X

H)·bit

Ru
R"
R"
Roo
R"
Rn

An
A"
Ru

""""

Roo
Ru
R"
R"
Roo

r
I

,
I..

,.
I

I

... ,
II

I

R.]';'R;'~~~ :::~~RllR)O ~R!.l~2~'!.2~~22J:!'!'.R!2_R~'_R~~ ~~~~~~~i ~~~!~ll!'tO.l'_~Op!'OJ~f ~,_O! P~D3 D2 O. Do
~::~

High Voltage Pins

HITACHI

3

1.2.3 HMCS412/414 Block Diagram

RESET 'fEg'fosc, DSC2 Vee GND

r-----I
I

I RAdVdtll>

,.L-L--1-...L.,

I

L. ____I

!!

Interrupt

ROM

Instruction

SP

RAM 160X4 bit

(HMCS412C/AC/CL;
2048X 10 bit)
(HMCS414C/AC/CL;
4096X 10 bit)

Decoder

tI

R43R42A4\R4o A33/R3;,!/R3IR3o
INT,fNiO

11- -- -II

-I

r

II

-.1-II

I

~R23R22R21R2o:IR13R12Rl1A'~
0'40130120,,0'00,08 D7 0, Os 0.]03020,
00
L
______ ...J.!- ______ 1 lRo3Ro2RO,ROol:
_______11 __________________
J
~

'-----1
L
___ J High Voltage Pins

4

HITACHI

1.3 Pin Description
The MCU input and output signals are described below.
o

GND, Vcc, Vdisp
These are the Power supply pins for the MCU.

Connect the GND to the

ground (OV) and apply the VCC power supply voltage to the VCC pin.

The

Vdisp pin (multiplexed with RAI) is a power supply for high voltage I/O
pins with maximum voltage of 40V(VCC).
o

TEST
This pin is not for use by users.

o

It should be connected to VCC pin.

RESET
This pin is used to reset the MCU.

o

For details, see "2.7 Input/Output".

For details, see "2.8 Reset".

OSCI' OSC2
These are input pins for the internal oscillator circuit.

They can be

connected to the crystal resonator, ceramic filter resonator, resistor
(resistor oscillation is applied to the HMCS402C and HMCS404C)
or external oscillator circuits.

For details, see "2.9 Internal Oscillator

Circuit".
o

D-port
The D-port is input/output port addressed by one bit.
are standard-type pins and D4-DIS are high voltage pins.
for each pin can be selected using a mask option.

The pins DO to D3
The Circuit type

For details, see

"2.7 Input/Output".
oR-ports (RO to RA)
These are 4-bit I/O ports.

(RA however, is 2-bit construction.)

RO, R6.

R7 and R8 are output ports, R9 and RA are input ports, and RI to RS are I/O
ports.

RO, RI, R2 and RA are high voltage ports, and R3-R9 are standard

ports.

Each pin has a mask option which selects its circuit type.

The

pins R32, R33' R40, R4l, and R42 are multiplexed with INTO, INTI' SCK, SI,
and SO respectively.
o

For details, see "2.7 Input/Output".

INTO, INTI
These are input pins with which MCU operations can be interrupted
externally.

INTI can be used as and external event input pin for Timer B.

INTO and INTI are multiplexed with R32, R33 respectively.

For details,

see "2.4 Interrupt".

HITACHI

5

o

SCK, SI, SO
The Transfer Clock I/O pin (SCK), Serial Data Input pin (SI), and Serial
Data Output pin (SO) are used for serial interface.
multiplexed with R40, R41, and R42 respectively.

SCK, SI, and SO are

For details, see "2.5

Serial Interface".

2.

INTERNAL STRUCTURE AND ITS OPERATION

2.1

ROM Memory Map
Table 2-1 shows the ROM capacity of each family.

ROM memory map is

illustrated in Fig. 2-1 and described in the following paragraphs.

Table 2-1

Capacity of HMCS400 Series ROM
ROM Capacity

Family
HMCS402C, HMCS402CL, HMCS402AC

2,048 words x 10 bits

HMCS404C, HMCS404CL, HMCS404AC

4,096 words x 10 bits

HMCS408C, HMCS408CL, HMCS408AC

8,192 words x 10 bits

HMCS412C, HMCS412CL, HMCS412AC

2,048 words x 10 bits

HMCS4l4C, HMCS4l4CL, HMCS4l4AC

4,096 words x 10 bits

(1) Vector Address Area --- $0000 to $OOOF
Locations $0000 through $OOOF are reserved for JMPL instructions to branch
to the starting address of the initialization program and of the interrupt
service programs.

After reset of interrupt routine is serviced, the program

is executed from the vector address.
(2) Zero-Page Subroutine Area --- $0000 to $003F
Maximum Locations $0000 through $OFFF are reserved for ROM data.

P instruc-

tion allows to branch to the subroutine.
(3) Pattern Area --- $0000 to $07FF (HMCS402C/CL/AC, HMCS4l2C/CL/AC)
$0000 to $OFFF (HMCS404C/CL/AC, HMCS408C/CL/AC,
HMCS4l4C/CL/AC)
Maximum locations $0000 through $OFFF are reserved for ROM data.
struction allows referring to the ROM data as a pattern.
(4) Program Area --- $0000 to $07FF (HMCS402C/CL/AC, HMCS4l2C/CL/AC)
$0000 to $OFFF (HMCS404C/CL/AC, HMCS4l4C/CL/AC)
$0000 to $lFFF (HMCS408C/CL/AC)

6

HITACHI

P in-

o

$0000

15
16
Zero-Page Subroutine

63
64

(64Wordl)

Program

._\:
=.
~3F

(2046 Words)

JMPL Instruction

(Jump to

4

(Jump to

5

9

• $0002

1iiITO Routine)

JMPl Instruction

iNT1 Routine)

JMPL Instruction

6

.

Plttern

(Jump to RESET Routine)

2
3

$OOOF
$0010

$0000
$0001

JMPL Instruction

0
1

Vector Address

(Jump to TIMER-A Routine,
JMPL Instruction

$0008
$0009
$OOOA

JMPL Instruction

SOOOC

(Jump to SERIAL Routine)

SOOOo

10

12
13
'14

Not Used

lB3B3

$3FFF

$0006
$0007

(Jump to TlMER-8 Routine'

11

2047
2046

$0003
$0004
$0005

SOOOB

SOOOE
SOOOF

15

HMCS402C/AC/CL

o

SOOOO
Vector Address

$OOOF
$0010

15
16
Zero-Page Subroutine

63

(64Words)

Program
Pattern

(4D96Words)

Not
16363

(Jump to RESET Routine)

SOOOO
$0001

2

JMPL Instruction
(Jump to INTo Routine)

$0003

3
4

5
6

9

r-Ibb6

4095
4096

J MPL Instruction

1

._\:
\

S003F

64

0

Used
$3FFF

$0002

JMPL Instruction
(Jump to INT1 Routine)

$0004

JMPL Instruction

$0006

(Jump to TIMER-A Routine)

$0005
$0007

J MPl Instruction

$0008

(Jump to TIMER-6 Routine)

$0009

10

$OOOA

11

$0006

t2
13

JMPl Instruction

(Jump to SERIAL Routine)

14
1'5

$OOOe
$0000
SOOOE
$OOOF

HMCS404C/CL/AC

Fig. 2-1

ROM Memory Map

HITACHI

7

o

$0000
Vector AddreSS

5

lOOOF

B

$0010
Zero-Page Subroutine

63

I64Words}

\

Pattern

14096 Words}

4095
4096

._\,:
$1000

Program

18192 Words}
819 1
8192

3
4

5

l003F
$0040

64

0
1
2

$IFFF
$2000

J MPL Instruction

10000

(Jump to RESET Routine)

JMPL Instruction
IJump to iNTO Routinel

$0001
10002
$0003

J MPL Instruction

$0004

(Jump to

B

7

11
12
13

iNft Routine)

JMPL Instruction

(Jump 10 TIMER-A Routine)
JMPL Instruction
(Jump to

TIMER·B ROLltine)

$0005
$0006
$0007
10008
10009
$OOOA

$0008
J MPL I"s,ruction
(Jump to SERIAL Routine)

lOOOC
$0000

'u

$OOOE

15

$OOOF

Not Used

16383

$3FFF

HMCS408C/CL/AC

o

SOOOO
Vector Addresl

5
6

SoooF
Soo10
Zero-Page Subroutine

63
64

(64Words,

\

S003F
SOO4O

0
1

(2048 Words)

SOOOO
Soool

JMPL Instruction
(Jump to INTo Routine,

S0002
S0003

J MPL Instruction
(Jump to INT, Routine,

SOOO4

2
3
4

5
6
7

\':

Program
Pattern

JMPL Instruction

(Jump to RESET Routine,

JMPL Instruction
(Jump to TIMER-8 Routine,

11

12
13

204 7
204 8

S07FF
S0800

1
1'5

Not Used

16383

S3FFF

HMCS412C/CLjAC

Fig. 2-1

8

HITACHI

S0005
S0006
S0007

ROM Memory Map

S0008
S0009
SoooA
S0008
SoooC
SoooD
SoooE
SoooF

o

SOOOO

Vector Address
15
16

SOOOF
S0010

JMPL Instruction
(Jump to RESET Routine'

2

J MPL Instruction
(Jump to iNTO Routine'

S0002
• S0003

JMPL Instruction
(Jump to liii'i1 Routine'

SOOO4
SOOO5

3

\
.-\,~
4

Zero-Plge Subroutine
(84Words,

83
84

0
I

S003F

Program
Pattern

(4096 Words)

5
8

soooe
S0007

J MPL Instruction
(Jump to TIMER-8 Routine'

$ OFFF
$1000

SOOOB
SOOOB
SOOOA

II

4095
4096

SOOOO
SOOOI

12

SOOOB
SOOOC

13

SOOOD

14

SOOOE

1~

SOOOF

Not Used

16383

S3FFF

HMCS4l4C/CL/AC

Fig. 2-1

ROM Memory Map

2.2 RAM Memory Map
The MCU includes RAM as the data area and stack area.

In addition to these

areas, interrupt control bits and special function registers are also mapped
on the RAM memory space.

Table 2-2 shows the RAM capacity of each family.

RAM memory map is illustrated in Fig. 2-2 and described in the following
paragraphs.

Table 2-2 Capacity of HMCS400 Series RAM
Family

RAM Capacity

HMCS402C, HMCS402CL, HMCS402AC

160 digits x 4 bits

HMCS404C, HMCS404CL, HMCS404AC

256 digits x 4 bits

HMCS408C, HMCS408CL, HMCS408AC

512 digits x 4 bits

HMCS4l2C, HMCS4l2CL, HMCS412AC

160 digits x 4 bits

HMCS4l4C, HMCS4l4CL, HMCS4l4AC

160 digits x 4 bits

(1) Interrupt Control Bit Area

--~

$000 to $003

This area is used for interrupt controls, and is illustrated in Fig. 2-3.
It is accessable only by RAM bit manipulation instruction.

However, the

interrupt request flag cannot be set by software.

HITACHI

9

.-.------.----.--------~

(2) Special Function Registers Area --- $004 to $OOB
The Special Function Registers are the mode or data registers for the
external interrupt, the serial interface, and the timer/counter.

These

registers are classified into three types: Write-only, Read-only, and Read/
Write as shown in Fig. 2-2.

These registers cannot be accessed by RAM bit

manipulation instruction.
(3) Data Area

$020 to $07F (HMCS402C/CL/AC, HMCS4l2C/CL/AC, HMCS4l4C/CL/AC)
$020 to $ODF (HMCS404C/CL/AC)
$020 to $lDF (HMCS408C/CL/AC)

16 digits of $020 through $02F are called memory register (MR) and
accessable by LAMR and XMRA instructions.

The configuration is shown in

Fig. 2-4.
(4) Stack Area

$3CO to $3FF

Locations $3CO through $3FF are reserved for LIFO stacks to save the
contents of the program counter (PC), status CST) and carry (CA) when interruption is serviced.

This area can be used as 16 nesting level stack which

one level requires 4 digits.

A save condition is shown in Fig. 2-4.

program counter is restored by RTN and RTNI instructions.
are restored only by RTNI instruction.

The

Status and Carry

The area, not used for stacking, is

available as a data area.

o

$000
RAM-mapped Registers

$ 000

1

32

$ 01F
$020

Memory Registers(MR)
47 --------------- -- .....
48

$ 02F
$ 030

31

\

Data

127
128

$07F
$080
Not Used

3
4

Stack
(64Di9its)

$002
$003

Port Mode Reg.

(PMR)

W

$004

5

Serial Mode Reg.

(SMR) oW

$005

6

Serial Data Reg. Lower (SRL)

0

lR/w

8

$ 006
Serial Data Reg. Upper (SRU) :R/W $007
Timer Mode Reg. A
(TMA)! W $008

9

Timer Mode Reg. B

10
11
12

TIMER-B'

$ 3BF
$3CO

959
960

$ 001

Interrupt Control Bits

2

7

(96 Digits)

1023

0

(TMB): W

$009

(TCBLlTLRL) iR/W $OOA
(TCBUITLRU) iR/W $OOB
$OOC
Not Used
$ 01F

31
$3FF

* Two registers are mapped on same address.
R :Read Only
W :Write Only
R/W:Read/Write

10

Tjmer/EventT~csuL~ter BLower: R

Timer Load Reg. lower

11

T'mer/Evenh~o~c~er 8 Upper

Timer Load Reg. Upper

I R

(1) HMCS402C/CL/AC

Fig. 2-2 RAM Memory Map
10 HITACHI

(TLRLI
(TLRUI

I

oW $OOA

:W

$008

o

$000
RAM-mapped Registers
$OlF
$020
Memory Registers(MR)

------------------

\

$02F
$030

223
224

$ODF
$OEO
Not Used

$002

3
4

$003

5

(PMR) :W $004
(SMR) ,W $005
Serial Data Reg. Lower (SRL) !R/W $006
Port Mode Reg.

Serial Mode Reg.

7

Serial Data Reg. Upper (SRU) 'RjW $007

8

Timer Mode Reg. A

9

(TMB) I W $009
Timer Mode Reg. B
(TCBLITLRL) IR/W $OOA
TIMER-B'
(TCBU/TLRU): RjW $OOB
$ DOC

10
11
12

$ 3BF
$3CO

959
960
Stack
(64Digits)

$001

Interrupt Control Bits

2

6

Data
( 192Digits)

1023

$000

1

31
32
47
48

0

(TMA)! W

$008

Not Used
$OlF

31
$3FF

* Two registers are mapped on same address.
R :Read Only
W :Write Only
R/W:ReadjWrite

Timer Load Reg. Lower

,

~~~~~~~~~~~=+~r-~Tnim~e=r'L~~T~a~~~~~t)g'.u~p=p~er~~:-W"i:~~:
ITLRU)

,w

(2) HMCS404C/CL/AC

o

$000
RAM-mapped Registers
$OlF
$020

32
Memory Registers(MR)

------------------

\

$ 02F
$030

$002

3
4

$003
(PMR) :W $004
Serial Mode Reg.
(SMR) ,W $005
Serial Data Reg. Lower (SRL) !R/W $006
Serial Data Reg. Upper (SRU) :R/W $007

5

7

1448 DigiU)

8
9
$lDF
$lEO

Not Used
960

1023

10
11
12

Port Mode Reg.

Timer Mode Reg. A

Stack
(64Digit5)

(TMA) 1 W

$008

(TMB) I W $009
Timer Mode Reg. B
(TCBLITLRL) :R/W $OOA
TIMER-B'
(TCBU/TLRU): R/W $OOB
$ DOC

$ 3BF
$3CO

95 9

$001

Interrupt Control Bits

2

6

Data

479
480

$000

1

31
47
4B

0

Not Used
$ 01F

31
$3FF

* Two registers are mapped on same address.
R :Read Only
W :Write Only
R/W:Read/Write

Timer load Reg. Lower

1

~~~~~~~~~~~=+~r-'Tc.im~e=r7L~~:~~ri~~~tg.,u7.p~p~err-i:-W-j:~~:
ITLRU)
,W
(3) HMCS408C/CL/AC

Fig. 2-2 RAM Memory Map

HITACHI 11

o

sooo
RAM-mapped R.gistars
SOIF
S020

32
Memorv Registers(MR)

48

------------------

\

S02F
S030

Data
(96Digits)

127
128

$000

1

31
47

0

S 07F
S080
Not Used

3
4

Stack
(64Digits)

1023

,, w

Not Used
Not Used

5
6
7

8
9
10
11
12

(PMR)

Port Mode Reg.

$003
$004
$005

Not Used

$006
$007

Not Used

$008

(TMB) i W $009
Timer Mode Reg. B
(TCBL/TLRL) 'RIW $OOA
TlMER-B"
(TC8U/TLRU):R/VII $OOB
$OOC

S38F
S3CO

959
960

$001
$002 .

Interrupt Control Bits

2

Not Us8d
$OIF

31
$3FF

* Two registers are mapped on same address.
R

:Read Only

W

:Write Onlv

R/W:Read/Write

(4) HMCS412C/CL/AC, HMCS414C/CL/AC

Fig. 2-2 RAM Memory Map

o

2
3

bit 3

bit 2

bit 1

IMO
(1M of iNToi

IFO
(IF of INTo)

RSP
(Reset SP Bit)

bit 0
I/E
$000
(Interrupt Enable Flag)

IMTA
(1M of TIMER-A)

IFTA
(I,F of TIMER-A)

IMI
(1M of INT,)

IFI
(IF of INT,)

$001

Not Used

Not Used

IMTB
(1M of TIMER-B)

IFTB
(IF of TIMER-8)

$002

IMS
(1M of SERIAL)

iFS
(IF of SERIAL)

$003

Not Used

Not Used

Interrupt Re.quest Fllg

IF
1M

Jnterrupt Mask

liE
SP

Interrupt Enable Flag
Stack Pointer
''

(Nota) Each bit in Interrupt Control Bitt Area is-set by SEM/SEMO inJtruction. is reset bV REM/REMO in.tru~ticn and is tested bV TM/TMD
instruction. It is not affected by other instructions. Furthermore,lnterrupt Request Flag i. not affected bV SEM/SEMD instruction.
The content of Status becomes inY.rid when "Not Used" bit is tested.

(1) HMCS402, HMCS404, HMCS408

Fig. 2-3 Configuration of Interrupt Control Bit Area
12 HITACHI

bit 3

bit 2

bit 1

bit 0

IMO

IFO

RSP

liE

(1M of INTo)

(IF of INTo)

IReset SP Bit)

(Interrupt Enable Flag)

Not Used

Not Used

2

Not Used

Not Used

3

Not Used

Not Used

o

IF:
1M:

IM1

IF1

(1M of INT, )

(IF of INT, )

IMTB

IFTB

11M of Timer B)

(IF of Timer B)

Not Used

Not Used

$000

$001
$002
$003

Interrupt Request Flag
Interrupt Mask

liE:

Interrupt Enable Flag

SP:

Stack POinter

Note:

Each bit in the interrupt control bits area is set by the SEM/SEMD instruction, is reset by the REM/REMD instruction, and
is tested by the TM/TMD instruction. It is not affected by other instructions. Furthermore the interrupt request flag is not

affected by the SEM/SEMD instruction.
The content of status becomes invalid when "Not Used bit and RSP bit are tested by a TM or TMO instruction.
H

(2) HMCS412, HMCS414

Fig. 2-3

Configuration of Interrupt Control Bit Area

Memory Registers

32
33
34
35
36
37
38
39
40
4t
42
43
44
45
46
47

MRIO)
MRO)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)
MR(tO)
MR(11)
MR(12)
MR(13)
MR(t4)
MR(15)

S
S
S
S
S
S
S
S
$
$
$

S
S
S
S
$

Stack Area

960
020
021
022
023
024
025
026
027
028
029
02A
028
02C
020
02E
02F t023

Level
Level

level
Level

level
Level

level
level
level
level

Level
Level
Level

Leve'
Level
Level

16 S 3CO
15
14
13
12
11
to
9
8
7
6
5
4
3
2
1 S 3FF

bit3
10/0
1021
1022
1023

bit2

bitO

bot1

_,1-',_,
ST

PC ..

CA

""PC;"

PC

"PC";;

13

PC""";"

~

S 3FC

PC,

1

PC.

S 3FO

I ~ , pc,

:

PC,

S 3FE

PC.

S3FF

I

I

I

I

PC";'
)

PC;"

I

,

PC" to PC. ; Program Counter
ST; Status
CA; Carry

-- --

Note) l. As the HMCS402/HMCS412 have 2k ROM version, PCll, PC12 ,
used.

-- -PC 13

2.

As the HMCS404/HMCS414 have 4k ROM version, PC12 ,

3.

As the HMCS408 have 8k ROM version, PC13

Fig. 2-4

PCn

are not

are not used.

is not used.

Configuration of r4emory Register, Stack Area and Stack Position

HITACHI 13

2.3 Registers and Flags
The MCU has nine registers and two flags for the CPU operations.

They are

illustrated in Fig. 2-5 and described in the following paragraphs.

(1) Accumulator (A), B Register (B)
The 4-bit registers Accumulator and B Register are used to hold the results
of Arithmetic Logic Unit (ALU) , and to transfer data to/from memories, I/O,
and other registers.

(2) WRegister (W), X Register (X), Y Register (Y)
W Register is 2-bit, and X and Y Registers are 4-bit registers used for
indirect addressing of RAM.

Y Register is also used for D-port addressing.

W Register is a write-only register.

For details, see "8.1 Precautions on

Using W Register".

(3) SPX Register (SPX), Spy Register (SPY)
The 4-bit registers SPX and SPY Registers are used to assist X and Y
Register respectively.

(4) Carry (CA)
The Carry (CA) stores the overflow of ALU generated by the arithmetic
operation.

It is also affected by SEC, REC, ROTL and ROTR instructions.

During interrupt is serviced, Carry is pushed onto the stack and restored
by RTNI instruction (not by RTN instruction).

(5) Status (ST)
The Status (ST) latches and overflow and Not Zero generated from ALU,
results of bit test.
instructions.

It is a branch condition of BR, BRL, CAL or CALL

The value of the Status remains unchanged until the next

arithmetic compare of bit test instruction is executed.

Status becomes "1"

after the BR, BRL, CAL or CALL instruction is executed irrespectively whether
it is executed or skipped.

During the interrupt servicing, Status is pushed

onto the stack and restored back from the stack by RTNI instruction (not by
RTN instruction).

(6) Program Counter (PC)
The Program Counter is a l4-bit binary counter which controls the sequence
in which the instructions stored in ROM are executed.

14 HITACHI

(7) Stack Pointer (SP)
The lO-bit Stack Pointer contains the address at which the last data was
pushed onto the stack.
The Stack Pointer is initialized to locate $3FF on the RAM address, and
is decremented by 4 when data is pushed onto the stack, and incremented by
4 when data is restored back from there.

Upper 4 bits of the Stack Pointer

are fixed to "1111", so that the stack can be used up to 16 levels.
The Stack Pointer is initialized to $3FF in two ways; one is MeU reset
and the other is to reset RSP bit by REM or REMD instruction.

' -_ _ _ _--' Accumuillor

' -_ _ _ _......1

Rev"'"

8

SPX

Spy

PC

S.

5'ICk

rOWlI.,

Fig. 2-5 Registers and Flags

HITACHI 15

2.4

Interrupt
Maximum interrupt sources are five available on the MCU: External Request

(INTO, INTI), Timer/Counter (TIMER-A, TIMER-B), and Serial Port (SERIAL).
For each source, the Interrupt Request Flag (IF), Interrupt Mask (1M) and
interrupt vector addresses are provided to control and maintain and interrupt
request.

The Interrupt Enable Flag (I/E) is also used to control the total

interrupt operations.

(1) Interrupt Control Bits and Interrupt Service
The interrupt control bits are mapped on $000 through $003 of the RAM
space and are accessable by RAM bit manipulation instruction.
rupt Request Flag (IF) cannot be set by software.)

(The Inter-

The Interrupt Enable

Flag (I/E) and IF are set to "0", and the Interrupt Mask (1M) is set to "1"
at initialization by MCU reset.
Fig. 2-6 is a block diagram of the interrupt control circuits.

Table 2-3

shows the interrupt priority and vector addresses, and Table 2-4 shows the
interrupt conditions corresponding to each interrupt source.
request is generated when the IF is set to "1" and 1M is "0".

The interrupt
If the I/E is

"1" at this time, the interrupt will be activated and vector addresses will
be generated from the priority PLA corresponding to the five interrupt sources.
Fig. 2-7 shows the interrupt service sequence, and Fig. 2-8 shows the
interrupt service flowchart.

If the interrupt is requested, the instruction

being executed finishes in the first cycle.
cycle.

The I/E is reset in the second

In the second and third cycles, the Carry, Status and Program Counter

are pushed onto the stack.

In the third cycle, the instruction is re-executed

after jumping to the vector address.
In each vector address, program JMPL instruction to branch to a starting
address of the interrupt service program.

The IF which caused the interrupt

service has to be reset by software in the interrupt service program.

16 HITACHI

$ 000,0

Sequence Control

IE f - - - - - - - - - - - - f " " " " " ' \

, Pu,h PCfCAfST
. Reset liE
• Jump to Vector
Address

Priority Control
PLA

Vector Address

$ 003,0

(1) HMCS402, HMCS404, HMCS408
$000,0

Sequence
Control
·Push PC/CA/ST
'Reset liE
'Jump to Vector
Address

I/E

Vector Address
Priority Control PLA

$001,0

(2) HMCS412, HMCS414

Fig. 2-6

Interrupt Circuit Block Diagram
HITACHI 17

Table 2-3 Vector Address and Interrupt Priority
(1) HMCS402, HMCS404, HMCS408
Reset. Interrupt
RESET

(2) HMCS412, HMCS414

Vector addresses

Priority
-

INTo
INT,

2

TIMER-A

3

TlMER-B

4

$0000
$0002
$0004
$0006
$0008

SERIAL

5

$OOOC

1

Reset, Interrupt

Priority

Vector addresses

RESET

-

$0000

INTo

,

$0002

INT,

2

$0004

Timer B

3

$0008

Table 2-4 Conditions of Interrupt Service
(1) HMCS402, HMCS404, HMCS408

~

Interrupt

INTo

source

,
,

control bits
I/E
IFO·IMO

IF' ·IM'
IFTA ·IMTA

INT,

TIMER-A

,

0
0

*
*
*

,

IFTe·IMTB
IFS ·IMS

SERIAL

,

0
0
0

*
*

0
0
0
0

•

1

0

*
*
*
*

TIMER-B

,

1

,

,

• Don't car.

(2) HMCS412, HMCS414
Interrupt Control Bit
liE
IFO·IMO
IF1·IMl

*
*

IFTB·IMTB

Instruction

INTo

,
,

,

,

INT,

Timer B

0

0

1

0

,
1

*

*

Don t care

3

2

4

6

5

Cycles

I

I

I

I

I

I

I

I nltruction
execution

Interrupt
accePted

Stacking,
Reset of lIE

Stacking,
Vector address

is generated

JMPL instruction execution on the
vector addre••

Inrtruction

Execution at
starting Iddreu
of the interrupt
routine

Fig. 2-7
18 HITACHI

Interrupt Servicing Sequence

No

Yes
Yes

I/E~·O·
Stack~(pC)

Stack~(CA)
Stack~(ST)

PC~$0002

PC~$0004

PC~$0006

PC~$OO08

PC~$OOOC

(SERIAL Interrupt)

(1) HMCS402, HMCS404, HMCS408

Fig. 2-8

Interrupt Servicing Flowchart

HITACHI 19

Yes

Yes

No

I/E~O

(PC)
(CA)
Stack~ (ST)

Stack~
Stack~

PC~$0002

PC

~$0004

Yes

Yes

No

PC~$OOOB

(Timer B Interrupt)

(2) HMCS412, HMCS414

Fig. 2-8

20 HITACHI

Interrupt Servicing Flowchart

(2) Interrupt Enable Flag (I/E:$OOO, bit 0)
The Interrupt Enable Flag controls enable/disable of interrupt requests
from the sources as shown in Table 2-5.

It is reset by the interrupt servic-

ing and set by RTNI instruction.

Table 2-5

Interrupt Enable Flag

Interrupt Enable Flag

°

Interrupt Enable/Disable
Disable

I

Enable

(3) External Interrupts (INTO, INT1)
The external interrupt request inputs (INTO' INTI) can be selected by the
Port Mode Register (PMR:$004).

Setting the bit 3 and bit 2 of PMR causes

R33/INTI pin and R32/INTO pin to be used as INTI pin and INTO pin respectively.
The External Interrupt Request Flags (IFO, IFI) are set at the falling edge
of INTO, INTI inputs.

(Refer to Table 2-6).

INTI input can be used as a clock signal input of TIMER-B.
counts up at each falling edge of input.

Then, TIMER-B

When using INTI as TIMER-B external

event, and External Interrupt Mask (IMI) has to be set so that the interrupt
request by INTI will not be accepted.

Table 2-6

(Refer to Table 2-7.)

External Interrupt Request Flag

External Interrupt Request Flags

No

°

Yes

I

Table 2-7

Interrupt Requests

External Interrupt Mask

External Interrupt Masks

°
I

Interrupt Requests
Enable
Disable (masks)

(4) External Interrupt Request Flags (IFO:$OOO bit 2, $001 bit 0)
The External Interrupt Request Flags (IFO, IFI) are set at the falling
edge of INTO' INTI inputs respectively.

(5) External Interrupt Masks (IMO:$OOO bit 3, $001 bit 1)
The External Interrupt Masks are used to mask the external interrupt
requests.

HITACHI 21

(6) Port Mode Register (PMR:$004)
The Port Mode Register is a 4-bit write-only register which controls the
R32/INTO pin, R33/INTI pin, R41/SI pin and R42/S0 pin as shown in' Table 2:"'8.
The Port Mode Register will be initialized to $0 by MCV reset, all these pins
are therefore used as ports.

Table 2-8
PMR
bit 3
0

Port Mode Register
R,,/INT , pin

Used as R33 port input/output pin
Used as I NT I input pin

PMR
bit 2
0

R3,/INT o pin
Used as R32 port input/output pin
Used as I NT 0 input pin

PMR
bit 1
0

R.,/SI pin
Used as R., port input/output pin
Used as SI input pin

PMR
bit 0
0

R.,/SO pin
Used as R., port input/output pin
Used as SO output pin

2.5 Serial Interface
The serial interface is used to transmit/receive 8-bit data serially.

This

consists of the Serial Data Register, the Serial Mode Register, the Octal
Counter and the multiplexer as illustrated in Fig. 2-9.

Pin R40/SCK and the

transfer clock signal are controlled by the Serial Mode Register.

The

contents of the Serial Data Register can be written into or read out by
software.

The data in the Serial Data Register can be shifted synchronously

with the transfer clock signal.
STS instruction is used to initiate serial interface operations and to
reset the Octal Counter to $0.

The counter starts to count at the falling

edge of the transfer clock (SCK) signal and increments by one at ,the rising
edge of the SCK.

When the Octal Counter is reset to $0 after eight transfer

clock signals, or when a transmit/receive operation is discontinued by resettingthe Octal Counter, the SERIAL Interrupt Request Flag will be set.

22 HITACHI

Fig. 2-9 Serial Interface Block Diagram

(1) Serial Mode Register (SMR:$005)
The 4-bit write-only Serial Mode Register controls the R40/SCK, prescaler
divide ratio, and transfer clock source as shown in Table 2-9.
The Write Signal to the Serial Mode Register controls the operating state
of the serial interface.
The Write Signal to the Serial Mode Register stops the Serial Data Register
and Octal Counter from applying transfer clock, and it also resets the Octal
Counter to $0 simultaneously.

Therefore, when the Serial Interface is in the

"Transfer State", the Write Signal causes the Serial Mode Register to case
the data transfer and to set the SERIAL Interrupt Request Flag.
Contents of the Serial Mode Register will be changed on the second
instruction cycle after writing into the Serial Mode Register.

Therefore,

it will be necessary to execute the STS instruction after the data in the
Serial Mode Register has been changed completely.

The Serial Mode Register

will be reset to $0 by MCV reset.

(2) Serial Data Register (SRL:$006, SRU:$007)
The 8-bit read/write Serial Data Register consists of a low-order digit
(SRL:$006) and a high-order digit (SRV:$007).
The data in the Serial Data Register will be output from the SO pin, from
LSB to MSB, synchronously with the falling edge of the transfer clock signal.
At the same time, external data will be input from the SI pin to the Serial

HITACHI 23

Data Register, to MSB first, synchronously with the rising edge of the
transfer clock.

Fig. 2-10 shows the I/O timing chart for the transfer

clock signal and the data.
The read/write operations of the Serial Data Register should be performed
after the completion of data transmit/receive.

Otherwise the data may not

be guaranteed.

Table 2-9 Serial Mode Register
SMR
Bit 3

o

Used as Roo port input/output pin
Used as SCi< input/output pin

SMR

Transfer Clock

Bit 2

Bit 1

BitO

0

0

0

0

0

1

R4o/SCK Port
S~K

Clock Source

Presealer
Divide
Ratio

System Clock
Divide
Ratio

Output

Presealer

+2048

+4096

SCK
Output

Prescaler

.,.

512

+ 1024

SCi<
Output

Prescaler

-'-

128

-'-

Prescaler

.,.

32

0

1

0

0

1

1

SCK
Output

1

0

0

SCK
Output

1

SCK
Output

Prescaler

0

SCK
Output

System
Clock

1

SCK
Input

External
Clock

1

0

1

1

1

1

Presealer

.,.

256
64

8

.,.

16

2

+

4

.,.

1

-

-

(3) Serial Interrupt Request Flag (IFS:$003 bit 0)
The Serial Interrupt Request Flag will be set when the Octal Counter
counts eight transfer clock signals, or when data transfer is discontinued
by resetting the Octal Counter.

Refer to Table 2-10.

(4) Serial Interrupt Mask (IMS:$003 bit 1)
The Serial Interrupt Mask masks the interrupt request.

Refer to Table

2-11.

(5) Selection and Change of the Operation Mode
Table 2-12 shows the serial interface operation modes which are determined
by a combination of the value in the Port Mode Register and that in the
Serial Mode Register.
Initialize the serial interface by the Write Signal to the Serial Mode
Register, when the Operation Mode is changed.

24 HITACHI

Tramfer Clock

Serial Output Data

Serial Input Date

I I I I I I I I

Latch Timing

Fig. 2-10 Serial Interface I/O Timing Chart
Table 2-10 SERIAL Interrupt Request Flag
SERIAL Interrupt Request Flag

Interrupt Request

o

No
Yes

Table 2-11

SERIAL Interrupt Mask

SERIAL Interrupt Mask

Interrupt Request

o

Enable
Disable (mask)

Table 2-12 Serial Interface Operation Mode
PMR

SMR

Serial I nterface Operating Mode

Bit 1

Bit 0

1

0

0

Clock Continuous Output Mode

1

0

1

Transmit Mode

1

1

0

Receive Mode

1

1

1

Transmit/Receive Mode

Bit 3

(6) Operating State of Serial Interface
The serial interface has three operating states, the STS waiting state,
SCK waiting state, and Transfer state, as shown in Fig. 2-11.
The STS waiting state is the initialization state of the serial interface
internal state.

The serial interface enters this state in one of two ways:

either by changing the operation mode through a change in the data in the
Port Mode Register, or by writing data into the Serial Mode Register.

In

this state, the serial interface does not operate even i f the transfer clock
is applied.

If an STS instruction is executed, the serial interface shifts

to "SCK waiting state".

HITACHI 25

In this state the falling edge of the first transfer clock causes the
serial interface shift to "transfer state", while the Octal Counter counts-up
and the Serial Data Register shifts simultaneously.

As an exception, if the

clock continuous output mode is selected, the serial interface stays in
"SCK waiting state" while the transfer clock outputs continuously.
The Octal Counter becomes "000" again by 8 transfer clocks or by execution
of STS instruction, so that the serial interface returns to "SCK waiting
state", and the Serial Interrupt Request Flag is set simultaneously.
When the internal transfer clock is selected, the transfer clock output
is triggered by the execution of an STS instruction, and stops after 8 clocks.

(7) Example of Transfer Clock Error Detection
The serial interface functions abnormally when the transfer clock is
disturbed by external noises.

In this case, transfer clock error can be

detected by the procedure shown in Fig. 2-12.
If more than 8 transfer clocks are applied in the "SCK waiting state",
the state of the serial interface shifts as the following sequence: first,
"transfer state", second, "SCK waiting state" and third, "transfer state"
again.

The Serial Interrupt Flag should be reset before entering into the

STS state by writing data to SMR.

This procedure causes the serial IRF to

be set again .

• "Change PMR" means the change of

STS Waiting State

operation mode as below:

( Octal Counter

="000"

)

Transfer Clock Disable
Change PMR·

Transfer Clock

SC K Waiting State
IOctal Counter = "000")

Fig. 2-11

26 HITACHI

n
Transfer State

..

8 Transfer Clocks.
STS Instruction

(Octal Counter

(lFS ..... ' .. 1

Serial Interface Operation State

'* "000")

Ve.

Trlnlf" Dock

Fig. 2-12 Example of Transfer Clock Error Detection
2.6 Timer
The MeU contains a pres caler and two timer/counters (TIMER-A, TIMER-B).
A block diagram is shown in Fig. 2-13.

The prescaler is an ll-bit binary

counter, TIMER-A an 8-bit free-running timer, and TIMER-B an 8-bit autoreload timer/event counter.

Fig. 2-13 Timer/Counter Block Diagram
(1) Prescaler
The input to the prescaler is a system clock signal.

The prescaler is

initialized to $0000 by Meu reset, and it starts to count up the system clock
signal as soon as R.ESET input goes to logic "0".
counting up except in MeU reset and stop mode.

The pres caler keeps
The prescaler provides clock

signals to TIMER-A, TIMER-B and the serial interface.

The prescaler divide

ratio of the clock signals are selected according to the contents of the mode
registers, e.g. Timer Mode Register A (TMA), Timer Mode Register B (TMB),
Serial Mode Register (SMR).

HITACHI 27

(2) TIMER-A Operation
After TIMER-A is initialized to $00 by MCU reset, it counts up at every
clock input signal.

When the next clock signal is applied after TIMER-A

becomes $FF, it will generate an overflow and become $00.

This overflow

causes the TIMER-A Interrupt Request Flag (IFTA:$OOI bit 2) to go to "1".
This timer can function as an interval timer periodically generating overflow
output at every 256th clock signal input.
The clock input signals to TIMER-A are selected by the Timer Mode Register
A (TMA:$008).

(3) TIMER-B Operation
Timer Mode Register B (TMB:$009) is used to select the auto-reload function, input clock source, and the prescaler divide ratio of TIMER-B.

When

the external event input is used as an input clock signal to TIMER-B, select
the R33/INTI as INTI and set the External Interrupt Mask (IMl) to prevent an
external interrupt request from occurring.
TIMER-B is initialized according to the value written into the Timer Load
Register by software.

TIMER-B counts up at every clock input signal.

When

the next clock signal is applied to TIMER-B after it is set to $FF, TIMER-B
will generate overflow output.

In this case, if the auto-reload function is

selected TIMER-B is initialized according to the value of the Timer Load
Register, and if it is not selected, TIMER-B goes to $00.

The TIMER-B

Interrupt Request Flag (IFTB:$002 bit 0) will be set at this overflow output.

(4) Timer Mode Register A (TMA:$008)
The Timer Mode Register A (TMA) is a 3-bit write-only register.

The TMA

controls the prescaler divide ratio of TIMER-A clock input, as shown in
Table 2-13.
The TMA is initialized to $0 by MCU reset.

(5) Timer Mode Register B (TMB:$009)
The Timer Mode Register B (TMB) is a 4-bit write-only register which
controls the selection of the auto-reload function of TIMER-B and the
prescaler divide ratio, and the source of the clock input signal, as shown
in Table 2-14.
The Timer Mode Register B is initialized to $0 by MCU reset.
The operation mode of TIMER-B is changed at the second instruction cycle
after writing into the Timer Mode Register B.

Initialization of TIMER-B by

the write instruction to Timer Load Register should be performed after the
contents of TMB are changed.

Configuration and function of Timer Mode

Register is shown in Fig. 2-14.

28 HITACHI

Table 2-13 Timer Mode Register A
TMA

Table 2-14 Timer Mode Register B
TMB

Prescaler Divide Ratio

Bit 2

Bit 1

Bit 0

0

0

0

+2048

0

0

1

+1024

0

1

0

+ 512

0

1

1

+ 128

1

0

0

~

1

0

1

1

1

0

1

1

1

Auto·reload Function

Bit 3

No

0
1

Ves
TMB

Presealer Divide Ratio,
Clock Input Source

32

Bit 2

Bit 1

Bit 0

8

0

0

0

:2048

4

0

0

1

+ 512

2

0

1

0

: 128

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

:

PMR:$OO4

32

:
:

8
4
2

INT, (External Event Input)

SMR:$ 005

Transfer clock ,election

R40 /SCK pin mode selection

'---_ _ _ _ A.1 /S0 pin mode selection
' - - - - - - - - A.I/SI pin mode selection

' - - - - - - - - - - Au/INT; pin mode selection
' - - - - - - - - - - - - Ru/INTI pin mode selection

TMA:$OO8

L

TMB:$OO9

L

TIMER·B Input clock selection

'---_ _ _ _ _ _ Auto-reload function selection

TIMER·A Input clock selection

Fig. 2-14 Mode Register Configuration and Function

HITACHI 29

(6) TIMER-B (TCBL:$OOA, TCBU:$OOB, TLRL.$OOA, TLRU:$OOB)
TIMER-B consists of an 8-bit write-only Timer Load Register, and an 8-bit
read-only Timer/Event Counter.

Each of them has a low-order digit (TCBL:$OOA,

TLRL:$OOA) and a high-order digit (TCBV:$OOB, TLRV.$OOB).

(Refer to Fig. 2-2.)

The Timer/Event Counter can be initialized by writing data into the Timer
Load Register.

In this case, write the low-order digit first, and then the

high-order digit.

The Timer/Event Counter is initialized at the time when

the high-order digit is written.

The Timer Load Register has been initialized

to $00 by the MCV reset.
The counter value of TIMER-B can be obtained by reading the Timer/Event
Counter.

In this case, read the high-order digit first, and then the low-

order digit.

The count value of the low-order digit is latched at the time

when the high-order digit is read.

(7) TIMER-A Interrupt Request Flag (IFTA:$OOl bit 2)
The TIMER-A Interrupt Request Flag is set by the overflow output of
TIMER-A.

Refer to Table 2-15.

(8) TIMER-A Interrupt Mask (mTA:$OOl bit 3)
The TIMER-A Interrupt Mask prevents an interrupt request from being
generated by TIMER-A Interrupt Request Flag.

Refer to Table 2-16.

(9) TIMER-B Interrupt Request Flag (IFTB:$002 bit 0)
The TIMER-B Interrupt Request Flag is set by the overflow output of
TIMER-B.

Refer to Table 2-17.

(10) TIMER-B Interrupt Mask (IMTB:$002 bit 1)
The TIMER-B Interrupt Mask prevents an interrupt request from being
generated by TIMER-B Interrupt Request Flag.

Table 2-15 TIMER-A Interrupt Request Flag
TlMER-A Interrupt
Request Flag

0
1

0
1

30 HITACHI

Table 2-16 TIMER-A Interrupt Mask

Interrupt Request

TlMER-A Interrupt
Mask

No

0

Enable

Yes

1

Disable (Mask)

Table 2-17 TIMER-B Interrupt Request Flag
TIME R-B Interrupt
Request Flag

Refer to Table 2-18.

Interrupt Request

Table 2-18 TIMER-B Interrupt Mask

Interrupt Request

TlMER-B Interrupt
Mask

No

0

Enable

Yes

1

Disable (Mask)

Interrupt Request

2.7

Input/Output
The MCV has 58 I/O pins, 32 standard pins and 26 high voltage pins.

One

of these circuit types, CMOS, with pull-up MOS, and without pull-up MOS (NMOS
open drain) can be selected for each standard pin, and one of two circuit
types, with pull-down MOS and without pull-down MOS (PMOS open drain), can be
selected for each high voltage pins.

Since the pull-down MOS is connected

to the internal Vdisp line, the Vdisp line must be selected from the RAl/Vdisp
pin via mask option when at least one high voltage pin is selected as "With
pull-down MOS" option.

See Table 2-19 as for I/O pin circuit types.

When every input/output pin is used as an input pin, the mask option and
output data must be selected in the manner specified in Table 2-20.

(1) Output Circuit Operation of "With pull-up MOS" Standard Pins
In the "with pull-up MOS" standard pin option, the circuit shown in Fig.
2-15 is used to shorten rise time of output.
When an output instruction is executed, a write pulse will be generated
and applied to the R port addressed by this instruction.
switch the PMOS (B) to ON and shorten the rise time.

This pulse will

In this case, the

write pulse keeps PMOS in the ON state for one-eighth of the instruction
cycle time.

While the write pulse is "0", a high output level is maintained

by the pull-up MOS (C).
As the HLT signal becomes "0" in stop mode, MOS (A) (B) (C) turn OFF.

(2) D-port
The D-port is an I/O port which has 16 descrete I/O pins, each of which
can be addressed independently.

It can be set/reset through SED/RED and

SEDD/REDD instructions, and can be tested through TD and TDD instructions.
See Table 2-19 as for the classification of standard pin, high voltage pin
and the I/O pin circuit types.

(3) R-ports
The R-ports are 4-bit I/O ports.

The eleven R-ports in HMCS408 are

composed of 20 I/O pins, 16 output-only pins, and 6 input-only pins.

Data

is input through LAR and LBR instructions and output through LRA and LRB
instructions.

The MCV will not be affected by writing into the input-only

and/or non-existing ports, while invalid data will be read by reading from
the output-only and/or non-existing ports.
The R32' R33' R40, R4l, and R42 pins are multiplexed with the INTO, INTI'
SCK, SI, and SO pins respectively.

See Table 2-19 as for the classification

of standard pins, high voltage pins and selectable circuit types of I/O pins.

HITACHI 31

Pull
M3

Up

MOS ICI

~

PMOSIBI

.--1-----1--+----.__-,-

Write pulse
fOutput
instruction)

HL T

NMOSIAI

M,
'--J:)-~------ Data

~
MOS
Buffer

ON Resistance Value
HMCS40ZC/AC,HMCS404C/AC

HMCS40ZCL,HMCS404CL

MI

approx. Z50n

approx. Ikn

MZ

approx. Ikn

approx. 5kn

M3

approx. 40kfl
to I60kn (VC C=5V)

~
MOS
Buffer

approx. 75kr/ to lMr2(VCC=3V)
approx. 40kfl to l60kr/(VCC=5V)

ON Resistance Value
HMCS40BC. HMCS40BAC
HMCS412C. HMCS412AC
HMCS414C. HMCS414AC

HMCS40BCL
HMCS412CL
HMCS414CL

MI

approx. Z50n

approx. Ikfl

MZ

approx. Ikfl

approx. 1. 7kr/

M3

approx. 30krl
to I60kfl (VCC=5V)

approx. 60krl to lMr2(VCC=3V)
approx. 30krl to l60kfl(VCC=5V)

1 Instruction cycle

OutPUt instruction execution

Write pulse

Fig. 2-15

32 HITACHI

____________~Il~______

Output Circuit Operation of Standard Pins with "with Pull-up MOS" Option

Table 2-19

I/O Pin Circuit Type

(1) HMCS402/HMCS404/HMCS408 I/O Pin Circuit Type
\\Ilthout pull·up MOS
(NMOS open drain)
(A)

1/0
common
pins

~-' ~'data

data

C

~HLT

C

I:

li

"0

Applied
pins

~~.
~H[f

Do -0"
R,. -Rn,

data

Vee

pulse
HLT

output

I:

~

~:.". ~."

R60 -R 6l .

pulse

~~HU

output

R,o-R n ,

HLT

output
data

data

Rso -RS3

data

Vee

Output
pins

R40 -R43,

output

data

data

'0.

.

"~'.

output

"0

CMOS (C)

With pull·up MOS
(6)

Rao-R u

output

data

Vee

Input

pins

H~

input
~ data

HLT

input
data

Without pull·down MOS
(PMOS open drain) (D)

1/0

With pull·down MOS (E)

Applied pins

Vee

Vee

common

R,o-R'3

k(J::'~ut
data

1jVC~~d ..
f«J::HLT

~

0 4 -0 15 •

data

pins

RiO-Ail.
R20 -R u

_

HL~input

Vdlsp

Hl"'~

data

.E

!

Q

~

Vee

cJK]::HIT

~~."

Vee

c.
Output
pins

input
data

output

output

datI

data

Vee

i

:J:

Roo-R o,

Vdisp

~input
data

~inpUl
data

RAO

Vee

Vdisp

Input

pins
~input
data

RA1

INote)

In the stop mode,HIT signal is "0" and 110 pins ere in high Impedance stat •.

(to be continued)

HITACHI 33

Without pull-up MOS (NMOS open drain)
or CMOS (A or C)

With pull-up MOS (S)

·'e

-£-SCK

1/0
common
pins

c

:;

"0

fi

HLT
HL T+mode setect

~

0-

SCK

HLT

o-j

intema' SCK

.

HLT+"'Odese,~_
internal SCK

~:' o-~:

SCK (Note 2)
(OUTPUT MODE)

Vee

-a
"t>

Vee

Applied pins

Output
pins

U;

o--e--

Input
pins
~input
data

INTo.
INT,.
SI

input

data

SCK (Note 2)

HLT

HLT

SO

(INPUT MODE)

(Note 1)

In the stop mode, HLT signal is "0", HLT signal
are in high impedance state.

is "I" and I/O pins

(Note 2)

If the MCU is interrupted by serial interface in the external clock
input mode, the SCK terminal becomes input only.

Table 2-20 Data Input from Input/Output Common Pins
Possibility
of Input

Available pin condition
for input

CMOS

No

-

Without pull-up
MOS
(NMOS open drain)

Ves

"I"

With pull-up MOS

Ves

"I"

Without pull-down
MOS
(PMOS open drain)

Ves

"0"

With pull-down
MOS

Ves

"0"

I/O pin circuit type

Standard
pins

High
voltage
pins

Table 2-19

I/O Pin Circuit Type

(2) HMCS412/HMCS414 I/O Pin Circuit Type
Without pull-up MOS
(NMOS open drain) (A)

I~LT

2
a::

With pull-up MOS

Input

Input
data

r::--;;:-:=~-=-:data Write

I/O

1i

Common
Pins

_

r-o-lnput
data

iill..j'"p- ,Input
data

R20 - R2 3

II

c

a::

Vee

;

~
~

1:z:

Vee

Output
Pins

oJr---'M

2/2

STATUS

vCLE

Load A from Immediate

LAI i

Load B from Immediate

LBI I

Load Memory from Immediate

LMID i.d

load Memory from Immediate, Increment Y

LMIIY I

I

1/1

10'001 bi2;,io ;-..... M,Y+l ..... Y

N£

Table 3-2 Register-to-Register Instruction
MNEMONIC

OPERATION

OPERATION CODE

FUNCTION

STATUS

1I" 1

wz

YCLE

oad A from B

LAB

0 0 0 1 0 0 1 0 0 0

B _A

1/1

oad B from A

LBA

0 0 1 1 0 0 1 0 0 0

A ·B

11"1

oad A from Y

LAY

0 0 1 0 1 0 1 1 1 1

V-A

1I" 1

oad A from SPX

LASPX

0 0 0 1 1 0 1 0 0 0

SPX _A

11"1
11"1

oad A from SPY

LASPY

0 0 0 1 0 1 1 0 0 0

SPY-A

oad A from MA

LAMR m

1 0 0 1 1 1 m3m2m,mO

MR(ml-A

1 I" 1

xchange M R and A

XMRAm

1 0 1 1 1 1 m3m2m ,mO

MRlml··A

1/1

Table 3-3 RAM Address Instruction
OPERATION

MNEMONIC

OPERATION CODE

FUNCTION

LWI ;

00111 1 00 i, io

I_W

STATUS

WOR5V
CYCLE

Load W from Immediate

a a , a b ;2 11 10

1/1

;______ x

1/1

I-Y

1/1
1/1

Load X from Immediate

LXI

;

, 0

load Y from Immediate

LYI

;

, 0 0 0 0 1

Load X from A

LXA

0011101000

A-X

load Y from A

LYA

0011011000

A-Y

Increment Y

IY

0001011100

Y+l ...... Y

NZ

1/1

Decrement Y

OY

00110111 1 1

Y-l .y

NB

1/1

13.2 II

io

1/1

AddAtoY

AYY

0001010100

Y+A--Y

OVF

1/1

Subtract A from Y

SYY

0011010100

Y-A_Y

NB

1/1

Exchange X and SPX

XSPX

0000000001

X··SPX

1/1

Exchange Y and Spy

XSPY

0000000010

Y··SPY

1/1

Exchange X and SPX,Y and SPY

XSPXY

0000000011

X· ·SPX.y· ·SPY

1/1

Table 3-4 RAM Register Instruction
OPERATION

MNEMONIC

OPERATION COOE

FUNCTION

00100100yx
0110010000
d9 de dr d6 dsd. d3dl d, do
00010000yx

M ..... A, (~::~;~,\

STATUS

WZU

CYCLE

Load A from Memory

LAM(XYI

load A from Memory

LAMD

load B from Memory

LBM(XY)

load Memory from A

LMA(XYI

Load Memory from A

LMAO

d

1/1

M-A

2/2

M-B. (~::~~~I

1/1

load Memory from A, Increment Y

LMAIY(XI

00100101yx
A--+M, (~:~~;~)
0110010100
A-M
d,dsdrdsd5d. dl dl d, do
000101000x A--+M,Y + l-+Y(x. ·SPX!

load Memory from A, Oecrement Y

LMAOY(XI

001101000x

A-M. Y - 1-y,x· ·SPXI

Exchange Memory and A

XMA(XY)

00100000yx

M·-A. (~::~~~)

1/1

Exchange Memory and A

XMAD

1,:,110000000

M-A

2/2

Exchange Memory and B

XMB(XY}

00110000yx

M·-B. (~::~'~I

1/1

d

d

did. dJ d6d~d. d3d2d, do

1/1

2/2
NZ

1/1

NB

1/1

HITACHI 49

Note) (XY) and (X) have the meaning as follows:
(1)

The instructions with (XY) have 4 mnemonics and 4 object codes for each.
(example of LAM (XY) is given below.) The op-code X or Y is assembled as
follows.
MNEMONIC
LAM
LAMX
LAMY

LAMXY

(2)

V

0
0
1
1

:

:

x
0
1
0
1

FUNCTION

X-SPX

V-SPY
X -SPX, Y -spy

The instructions with (X) have 2 mnemonics and 2 object codes for each.
(example of LMAIY(X) is given below.) The op-code X is assembled as
follows.
FUNCTION

x ...... spx

Table 3-5 Arithmetic Instruction
OPERATION

MNEMONIC

FUNCTION

STATUS

WORD ....

~l

Add Immediate to A

AI i

1 0 1 0 0 0 i3 12 h io

A+ i ..... A

OVF

1/1

Increment B

IB

0001001100

B+1-B

NZ

1/1

Decrement B

DB

001 1001 1 1 1

B-l_B

NB

1/1

Decimal Adjust for AdditIon

DAA

0010100110

1/1

Decimal Adjust for Subtraction

DAS

0010101010

1/1

Negate A

NEGA

0001100000

A+1_A

Complement B

COMB

0101000000

l!-B

Rotate Right A with Carry

ROTR

0010100000

1/1
1/1
1/1

Rotate left A with Carry

ROTL

0010100001

Set Carry

SEC

001 1 101 111

1-CA

1/1

Reset Carry

REC

0011101100

O-CA

1/1

Test Carry

TC

0001 101 1 1 1

Add A to Memory

AM

0000001000

Add A to Memory

AMD

Add A to Memory with Carry

AMC

Add A to Memory with Carry

AMCD

Subtract A from Memory with Carry

SMC

jjJ,~,~ ~.~.J

d

2~ ~

0000011000
d

~9 Ja ~7 ~6 ~~ JJ3 ~2 ~1 ~o
o 0.1 0 0 1 1 0 0 0

1/1

CA

1/1

M+A-A

OVF

1/1

M+A-.A

OVF

2/2

OVF

1/1

OVF

2/2

NB

1/1

NB

2/2

M+A+CA-.A

OVF"'CA
M+A+CA--A

OVF"'CA
M-A-CA-A

NB"'CA

Subtract A from Memory with Carry

SMCD

2,~,~,2.U~,2,~,&

M -A-CA-.A

ORA.ndB

OR

0101000100

Al;B _A

AND Memory with A

ANM

0010011100

AnM-A

NZ

1/1

AND Memory with A

ANMD d

~,d, d,~.~, d. U,~, ~o

Ar-M_A

NZ

2/2

ORM

0000001100

Au M -.A

NZ

1/1

ORMD d

~.d-~,~.~,~.d,~,~, ~o

AUM-A

NZ

2/2

EOR Memory with A

EORM

00.00011100

A(,hM-A

NZ

1/1

EOR Memory with A

EORMD d

~- d, ~:il·~, d. d d'~'~'

A+;M_A

NZ

2/2

OR Memory with A
OR Memory with A

50 HITACHI

OPERATION COOE

..

d

NB"'CA

1/1

Table 3-6 Compare Instruction
OPERATION

MNEMONIC

OPERATION COOE

INEM

o 0 0 0 1 0 13 I] ,! 10
n~,~l ~,~ ~~,~

FUNCTION

STATUS

2

VeL.

Immediate Not Equal to Memory

I

ImmedIate Not Equal to Memory

INEMD

A Not Equal to Memory

ANEM

A Not Equal to Memory

ANEMD

1M

NZ

1/1

i 1M

NZ

0000000100

AiM

NZ

1/1

I ~'d.~'~.~'~' ~, cl,~, ~,

AIM

NZ

2/2

i,d

d

I

2/2

B Not Equal to Memory

BNEM

0001000100

B 1M

NZ

1/1

Y Not Equal to Immediate

YNEI

I

0001 1 ,

I) 12 I,

io

Y'tl

NZ

1/1

Immediate Less or Equal to Memory

ILEM

I

00001 1

13 I] I,

to

,"_M

NB

1/1

Immediate Less or Equal to Memory

ILEMD

I~d~,~ll,~~~~

,'_M

NB

2/2

A Less or Equal to Memory

ALEM

0000010100

A'_M

NB

1/1

IA

ALEMD

A _M

NB

2/2

0011000100

B _M

NB

1/1

1010' 1

A',_

NB

1/1

Less or Equal to Memory

B Less or Equal to Memory

BLEM

IA less or

ALEI

Equal to Immediate

Table 3-7

i,d

I ~ ~-~,~-n~ J

d

I

i3 12

n
i, io

I

RAM Bit Manipulation Instruction

OPERATION

MNEMONIC

Set Memory Bit

OPERATION CODE

00100001 n lnO

SEM n

FUNCTION

STATUS

Z

CYCLE

1-Mln)

1/1
2/2

Set Memory Bil

SEMD n,d

~·11J~ ~ ~~~ 1~~~o

1-Mln)

Reset Memory Bit

REM n

00 1 000 1 0 n,no

O-Mln)

1/1

Reset Memory Bit

O-oMln)

2/2

est Memory Bit

REMD n,d I ~-d d,~-nJ,-~,g:gg
TM n
001000,,",nO

est Memory Bit

TMD n,d

I

~9d8~1~6~~~JJ~z~:~

Min)

1/1

Min)

2/2

Table 3-8 ROM Address Instruction
MNEMONIC

OPERATION

Branch on Status 1

BR

b

OPERATION CODE

FUNCTION

STATUS

wz

CYCl

1 1 blb6bsb..b3b2blbo

1

1/1

~ ~ ~I ~ ~ ~,~~2~:~O

1

2/2

Long Branch on Status 1

BRL

u

Long Jump Unconditionally

JMPL

u

Subroutine Jump on Status 1

CAL

a

Long Subroutine Jump on Status 1

CALL

u

Table Branch

TBR

p

00 1 0 , 1 P3PzP,Po

1/ 1

Return from Subroutine

RTN

0000010000

1/3

Return from Interrupt

RTNI

0000010001

Table 3-9
OPERATION

Set Discrete I/O Latch

SEDD
REO

Reset Discrete 1/0 Latch Direct

REDD

Test Discrete I/O Latch

TO

Test Discrete I/O Latch Direct

TDD

load A from R·Port Register

2/2

~9 Ja~J J6cls~, ~J~;~,1~

1-IIE
C;A RESTORE

m

0 1 1 1

o

0 1

o

0

1 0 1 1 1 0 m]m2m l mO

o
m

FUNCTION

OPERATION CODE

o

SED

Reset Discrete I/O Latch

0 , 0 1 PlP2P'PO
d d dId d5d,dJdzdldo
01 1 1 aSa,aJ8Za180

1

1/2

1

2/2

ST

1/3

Input/Output Instruction

MNEMONIC

Set Discrete I/O Latch Direct

o,

0 0 1 1

1 0

o

1 1

o
o

0 1

o

0

mJmlm,mO

o

0 1 1 1 00 0 0 0

m

1

LAR

m

1

Load B from R·Port Register

LBR

m

1

o
o
o

load R·Port Register from A

LRA

m

1 0 1 1

Load R-Port Register from B

LRB

m

Pattern Generation

P

p

o

1

o

STATUS

1-DIY)

Z

yel

1/1

1_Dlm)

1/1

O-DIY)

1/1
1/1

O-Dlm)

1 0 m]mZm,mO

DIY)

1/1

D(m)

1/1

0 1 0 1 m]mlm,mO

Rlm)-A

1/1

0 1 00 m3ml m l mO

Rlm)~B

1/1

1 m]mlm,mO

A-Rim)

1/1

1 0 1 1 00 mJmlm,1llo

B-Rlm)

o

1 1 0 1 1 P3PZP,PO

1/1
1/2

HITACHI 51

Table 3-10 Control Instruction
OPERATION

2.

MNEMONIC

OPERATION CODE

No Operation

NOP

0000000000

Start Serial

STS

0101001000

1/1

Stand-by Modo

SBY

0101001100

1/1

Stop Modo

STOP

0101001101

1/1

FUNCTION

STATUS

CYCLE

1/1

Table 3-11 Op-Code Map
"

,

0

R8

R9~ 0I'\2\_\4\5\6\7\8\9\A\8\C\0\E\'

o

,

\NOPjI1SP~XlPYFx',I'l'.L

T""NII_/_AlfM

2
3
4
5

L8MIXV)
LMAIY(XI /

AMC

---- ----

IHEM

1(41

ItEM

1(4)

6\""'i. ~REoL _ _ _
0

•

XMAIXYI

l""'t

--:.

EOIII

--

VNEI

it4)

SEM n(21

REM n(2)

C

,

LW11(2)

IUIIL ____

E TO

,

0

,

SED

---- ---L81

LVI

---

0(4)
LIA

o LMADYIXI./"" "YL ____ -\ LV'L
LJCA.

---1(4)

3

LAI

,4)

4

LBR

m(4)

LAR

.,.4)

6

REDO

m(4)

.,.4)

8

LAMR
AI

9

lMllY

,4)

A

TOO
ALEI

C

LR8

m(4)

0

Lo.

m(41

,

SEOD

m(4)

XMRA

m(41

In.truction

114)

ILEMD

STS

----

~~- ____
""~

JMPl

0(4)

CALL

0(4)

BRL

0(4)

SEMD nl21

REMD n(2)

-~~

----1
SBYS1OI'/

TMD n(21

---- -JIMCt ____ -JI'"! ____

LMIO

i(4)

P

0(4)

\DY

IIEC~SK

CAL

al81

BR

biB)

V
V

ml41

<4)

V
V

U'" ~~~~~~~~~YCle

CJ'" ~~t~u~~~~t Address
(2-word/2-c:ycle)

52 HITACHI

r~

il4)

DB

;4)

8

0 .. · l-word/2-cyc)e

____ .[0.'1.--____
____
____

1(4)

LXI

E

INEMD

...,

~~

1(4)

2

•
,

----

----lTC ---- ---- -------

TM nl21
\SMCL ~'N"l ____

T8R

XMB(XY)

r-"
OR

"'"

9
LAMIXV)
\ lMAtXYI
A lIO'fln L _____ ID"L ____ . LDASL _ _ _ _ I ' "
B

---

____ ·\'ML ____ -IO."L ____

. ~E. ~ ]LAB1"'------] )8
____ 1'-""1_---- IV
An

7

_____ """-l ____
0\'\2\31 4 \5\6\7\8\9\A\8\C\0\E\'

r

: ...

~~:~~:~~~YCIB

3.4 Instruction Table
Three kinds of instruction tables are shown to explain the instructions
which construct Instruction System of the HMCS400 series.

3.4.1

Functional Table
Instructions are classified by function.

The table shows mnemonic

code and simple explanation of the function, and shows functional comparison between HMCS40 series and HMCS400 series.

HITACHI 53

CATEGORY
REGISTER
TO REGISTER

RAM ADDRESS

REGISTER
TO RAM

IMMEDIATE

ARITHMETIC

54 HITACHI

MNEMONIC
LAB
LBA
LAY
LASPX
LASPY
LAMR m
XMRA m
LXA
LYA
LXI i
LYI i
LWI i
IY
DY
AYY
SYY
XSPX
XSPY
XSPXY
LAM(XY)
LAMD d
LBM(XY)
XMA(XY)
XMAD d
XMB(XY)
LMA(XY)
LMAD d
LMAIY(X)
LMADY(X)
LMIIY i
LMID i,d
LAI i
LBI i
AI i
IB
DB
AMC
AMCD d
SMC
SMCD d
AM
AMD d
DAA
DAS
NEGA
COMB
SEC
REC
TC
ROTR
ROTL
OR
ANM
ANMD d
ORM
ORMD d
EORM
EORMD d

FUNCTION
B --+ A
A --+ B
Y --+ A
SPX --+ A
SPY --+ A
MR(m) --+ A
MR(m) +-+ A
A --+ X
A --+ Y
i --+ X
i --+ Y
i --+ W
Y + 1 --+ Y
Y - 1 --+ Y
Y + A --+ Y
Y - A --+ Y
X +-+ SPX
Y -Spy
X -SPX, Y Spy
M --+ A, (X-SPX, Y-SPY)
M(d) A
M --+ B, (X-SPX, Y-SPY)
M --+ A, (X-SPX, Y-SPY)
M(d) - + A
MB, (X-SPX, Y-SPY)
A --+ M, (X-SPX, Y-SPY)
A --+ M(d)
A --+ M, Y+l--+Y, (X -SPX)
A --+ M, Y-l--+Y, (X -SPX)
i --+ M, Y+l --+ Y
i --+ M(d)
i --+ A
i --+ B
A + i --+ A
B + 1 --+ B
B - I --+ B
M + A + CA --+ A, OVF CA
M(d) + A + CA-A, OVF-CA
M - A - CA - A, NB - CA
M(d) - A - "CA- A, NB -- CA
M + A --+A
M(d) + A --+ A
Decimal Adjust (Add)
Decimal Adjust (Subtract)
Ii. + 1 --+ A
B --+ B
1 --+ CA
0 --+ CA
Test CA
Rotate Right A with Carry
Rotate Left A with Carry
A u B --+ A
A n M --+ A
A n M(d)
--+ A
A u M --+ A
A U M(d) --+ A
A0M --+ A
A 0 M(d) --+ A

STATUS

NZ
NB
OVF
NB

NZ
NB
NZ

OVF
NZ
NB
OVF
OVF
NB
NB
OVF
OVF

CA

400

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

40

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

NZ
NZ
NZ
NZ
NZ
NZ
(to be continued)

CATEGORY

COMPARE

RAM BIT
MANIPULATION

ROM ADDRESS

INTERRUPT

MNEMONIC
INEM i
INEMD i,d
ANEM
ANEMD d
BNEM
YNEI i
ILEM i
ILEMD i,d
ALEM
ALEMD d
BLEM
ALEI i
SEM
n
SEMD n,d
REM
n
REMD n,d
n
TM
n,d
TMD
BR
b
BRL
u
JMPL u
CAL
a
CALL u
TBR
P
RTN
u
LPU
SELE
SEIFO
SEIFl
SETF
SECF
REIE
REIFO
REIFl
RETF
RECF
TIO
TIl
TIFO
TIFl
TTF
LTI
i
LTA
LAT
RTNI
SED
RED
TD

I/O

CONTROL

SEDD
REDD
TDD
LAR
LBR
LRA
LRB
P
NOP
STS
SBY
STOP

m
m
m
m
m
m
m
P

FUNCTION
i
i '"'"
A
A '"'"
B
Y '"
i :;;
i :;;
A :;;
A :;;
B :;;
A :;;
1
1

'"

M
M(d)
M
M(d)
M
i
M
M(d)
M
M(d)
M
i

~

STATUS
NZ
NZ
NZ
NZ
NZ
NZ
NB
NB
NB
NB
NB
NB

M~n)

M(d,n)
M(n)
M(d, n)
Test M(n)
M(n)
M(d, n)
Test M(d, n)
Branch on Status 1
1
1
Long Branch on Status 1
Long Jump Unconditionally
Subroutine Jump on Status 1
1
Long Subroutine Jump on Status 1
1
Table Branch
Return from Subroutine
Load Program Counter Upper
on Status 1
1
I/E
1
IFO
1
IFl
1
TF
CF
1
0
I/E
0
IFO
0
IFl
0
TF
0
CF
INTO
Test INTO
INTl
Test INTl
Test IFO
IFO
Test IFl
IFl
Test TF
TF
i ~ Timer/Counter
A -+ Timer/Counter
Timer/Counter -+ A·
ST
Return from Interrupt
1 -+ D(Y)
0 ~ Dey)
D(Y)
Test Discrete I/O Latch D(Y)
1 ~ D(m)
0 ~ D(m)
D(m)
Test Discrete I/O Latch D(m)
R(m) -+ A
R(m) -+ B
A -+ R(m)
R(m)
B
Pattern Generation
No Operation
Start Serial
Standby Mode
Stop Mode
~

0
0

~

~

400

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
.*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

~

~

~

~
~

~

~

~

~

~

~

40

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

HITACHI 55

3.4.2

Alphabetical Order Table
Instructions are arranged in its mnemonic code's alphabetical order.

MNEMONIC
AI
i
ALEI i
ALEM
ALEMD d
AM

AMD

d

~
~D
d
ANEM
ANEMD d

ANM

ANMD d
AYY
BLEM
BNEM
d
BR
BRL
u
a
CAL.
CALL u
COMB
DAA
DAS
DB
DY
EORM
EORMD d
IB
ILEM
ILEMD i,d
INEM i
INEMD i,d
IY
JMPL u
LAB
LAI
i
LAM(XY)
LAMD d
LAMR m
LAR m
LASPX
LASPY
LAY
LBA
LBI
i
LBM(XY)
LBR m
LMA(XY)
LMAD d
LMADY(X)
LMAIY(X)
LMID i,d
LMIIY
i
LRA m
LRB
m
LWI
i

OP CODE
10-1000- ••.•
10-1011- ••••
00-0001-0100
01-0001-0100
00-0000-1000
01-0000-1000
00-0001-1000
01-0001-1000
00-0000-0100
01-0000-0100
00-1001-1100
01-1001-1100
00-0101-0100
00-1100-0100
00-0100-0100
11- •.•. - •.••
01-0111- ••••
01-11 •• - ••.•
01-0110- ....
01-0100-0000
00-1010-0110
00-1010-1010
00-1100-1111
00-1101-1111
00-0001-1100
01-0001-1100
00-0100-1100
00-0011- ••.•
01-0011- ••••
00-0010- •..•
01-0010- ••.•
00-0101-1100
01-0101- •••.
00-0100-1000
10-0011- •...
00-1001-00 ••
01-1001-0000
1O-0111- •..•
10-0101- ••••
00-0110-1000
00-0101-1000
00-1010-1111
00-1100-1000
10-0000- ••••
00-0100-00 ••
10-0100- ••••
00-1001-01 ••
01-1001-0100
00-1101-000.
00-0101-000.
01-1010- .•••
10-1001- •...
10-1101- .•••
10-1100- ••••
00-1111-00 ••

W/C --- Word/Cycle

56 HITACHI.

FUNCTION
A+ i
A
A <_ 1.•
A:;; M
A --+ M(d)
M + A -+A
M(d) + A --+ A
M + A + CA -+ A, OVF -+ CA
M(d) + A + CA ....... A, OVF - CA
A 'i M
A 'i M(d)
An M -+A
A n M(d) --+ A
Y + A -+Y
B:;; M
B 'i M
Branch on Status 1
Long Branch on Status 1
Subroutine Jump on Status 1
Long Subroutine Jump on Status 1
B -+ B
Decimal Adjust (Add)
Decimal Adjust (Subtract)
B-1
B
Y- 1
Y
A $ M .... A
A $ M(d) -+ A
B + 1 -+ B
i :;; M
i :> M(d)
i 'i M
i 'i M(d)
Y + 1 -+ Y
Long Jump Unconditionally
B -+ A
i -+ A
M -+ A, (X+--+SPX, Y+--+SPY)
M(d) -+ A
MR(m) -+ A
R(m) -+ A
SPX -+ A
SPY
A
Y
A
A
B
i
B
M -+ B, (X+-+SPX, Y+-+SPY)
R(m)
B
A -+ M, (X+-+SPX, y-Spy)
A -+ M(d)
M, Y-l ....... Y, (X ....... SPX)
A
M,Y+I-Y, (X ....... SPX)
A
i -+ M(d)
i -+ M, Y+l - - Y
A -+ R(m)
B '-+ R(m)
i -+ W

--

........

STATUS
OVF
NB
NB
NB
OVF
OVF
OVF
OVF
NZ
NZ
NZ
NZ
OVF
NB
NZ
1
1
1
1

NB
NB
NZ
NZ
NZ
NB
NB
NZ
NZ
NZ

....-........

--

----

NB
NZ
NZ

W/C
1/1
1/1
1/1
2/2
1/1
2/2
1/1
2/2
1/1
2/2
1/1
2/2
1/1
III
1/1
1/1
2/2
1/2
2/2
1/1
1/1
1/1
1/1
1/1
1/1
2/2
1/1
1/1
2/2
1/1
2/2
1/1
2/2
1/1
1/1
1/1
2/2
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
2/2
1/1
1/1
2/2
1/1
1/1
1/1
1/1

(to be continued)

MNEMONIC
LXA
LXI
i
LYA
LY1
i
NEGA
NOP
OR
ORM
ORMD d
P
p
REC
RED
REDD m
REM
n
REMD n,d
ROTL
ROTR
RTN
RTNI
SBY
SEC
SED
SEDD m
SEM
n
SEMD n,d
SMC
SMCD d
STOP
STS
SYY
TBR
P
TC
TD
TDD
m
TM
n
TMD
n,d
XMA(XY)
XMAD d
XMB(XY)
XMRA m
XSPX
XSPXY
XSPY
YNEI i

OP CODE
00-1110-1000
10-0010- ....
00-1101-1000
10-0001- ..•.
00-0110 0000
00-0000-0000
01-0100-0100
00-0000-1100
01-0000-1100
01 1011- ....
00-1110-1100
00-0110-0100
10-0110- ....
00-1000-10 ..
01-1000-10 ..
00-10 10-0001
00-1010-0000
00-0001-0000
00-0001-0001
01 0100-1100
00-1110-1111
00-1110-0100
1O-111O- .•..

00-1000-01 ..
01-1000-01. .
00-1001-1000
01-1001-1000
01-0100-1101
01-0100-1000
00-1101-0100
00-1011- ....
00-01l0-1111
00-1110-0000
10-1010- ....
00-1000-11 ..
01-1000-11. .
00-1000-00 ..
01-1000-0000
00-1l00-00 ..
10-1111- ....
00-0000-0001
00-0000-0011
00-0000-0010
00-0111- ....

FUNCTION
A -+ X
i -+ X
A -+ Y
i -+ Y
A + 1 -+ A
No Operation
A u B -+ A
A u M -+ A
A u M(d) -+ A
Pattern Generation
0 -+ CA
0 -+ D(Y)
0 -+ D(m)
0 -+ M(n)
0 -+ M(d,n)
Rotate Left A with Carry
Rotate Right A with Carry
Return from Subroutine
Return from Interrupt
Standby Mode
1 -+ CA
1 -+ D(Y)
1 -+ D(m)
1 -+ M(n)
1 -+ M(d,n)
M-A-CA -+ A, NB -+ CA
M(d) - A - CA -+ A, NB -- CA
Stop Mode
Start Serial
Y - A -+ Y
Table Branch
Test Carry
Test Discrete I/O Latch D(Y)
Test Discrete I/O Latch D(m)
Test Memory Bit M(n)
Test Memory Bit M(d,n)
M - A , (X~ SPX, Y ++ Spy)
M(d) ++ A
M - B, (X-SPX, Y-SPY)
MR(m) A
X +--+ SPX
X +--+ SPX, Y ..- Spy
Y +--+ Spy
Y # i

STATUS

NZ
NZ

ST

NB
NB
NB
CA
D(Y)
D(m)
M(n)
M(d,n)

NZ

W/C
1/1
1/1
1/1
1/1
1/1
1/1
111
1/1
2/2
1/2
1/1
1/1
1/1
1/1
2/2
1/1
1/1
1/3
1/3
1/1
1/1
1/1
1/1
1/1
2/2
1/1
2/2
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
2/2
1/1
2/2
1/1
1/1
1/1
1/1
1/1
1/1

W/C---Word/cycle

HITACHI 57

3.4.3 Object Code Table
Instructions are arranged in object code order.
OP-CODE
00-0000-0000
00-0000-0001
00-0000-0010
00-0000-0011
00-0000-0100
00-0000-1000
00-0000-1100
00-0001-0000
00-0001-0001
00-0001-0100
00-0001-1000
00-0001-1100
00-0010- ....
00-0011- ••..
00-0100-00 ..
00-0100-0100
00-0100-1000
00-0100-1100
00-0101-000.
00-0101-0100
00-0101-1000
00-0101-1100
00-0110-0000
00-0110-0100
00-0110-1000
00-0110-1111
00-0111- .•..
00-1000-00 ..
00-1000-01 ..
00-1000-10 ..
00-1000-11 ..
00-1001-00 •.
00-1001-01 ..
00-1001-1000
00-1001-1100
00-1010-0000
00-1010-0001
00-1010-0110
00-1010-1010
00-1010-1111
00-1011- .••.
00-1100-00 ..
00-1100-0100
00-1100-1000
00-1100-1111
00-1101-000.
00-1101-0100
00-1101-1000
00-1101-1111
00-1110-0000
00-1110-0100
00-1110-1000
00-1110-1100
00-1110-1111

MNEMONIC
NOP
XSPX
XSPY
XSPXY
ANEM
AM
ORM
RTN
RTNI
ALEM
AMC
EORM
INEM i
ILEM i
LBM(XY)
BNEM
LAB
IB
LMAIY(X)
AYY
LASPY
IY
NEGA
RED

LASPX
TC
YNEI i
XMA(XY)
SEM
n
REM
n
TM
n
LAM (XY)
LMA(XY)
SMC
ANM

ROTR
ROTL
DAA
DAS
LAY
TBR
P
XMB(XY)
BLEM
LBA
DB
LMADY(X)
SYY
LYA
DY
TD

SED
LXA
REC
SEC

W/C --- Word/Cycle

58 HITACHI

FUNCTION
No Operation
X +-+ SPX
Y +-+ SPY
X +-+ SPX, Y +-+ SPY

STATUS

1tl

1/1
1/1
1/1
NZ

A'" M
M + A A U M -

OVF

A
A

NZ

Return from Subroutine
Return from Interrupt
A, OVF -

CA

i '" M
i ;;; M

M -

1/3
1/1

NZ
NZ

NZ
NZ

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1

OVF

1/1

NB
NZ

B '" M

B -- A

Y + A

-+

Y, (X -

SPX)

Y

Spy - A
Y+1--Y
X+ 1 - A
o - D(Y)
SPX -+ A
Test Carry

NZ

CA
NZ

Y '" i
M +-+ A, (X-SPX, Y-SPY)
1 - M(n)
o - M(n)
Test Memory Bit M(n)
M -+ A, (X +-+ SPX, Y +-+ SPY)
A - M, (X +-+ SPX, Y +-+ SPY)
M - A - CA -+ A, NB -+ CA
AnM-A
Rotate Right A with Carry
Rotate Left A with Carry
Decimal Adjust (Add)
Decimal Adjust (Subtract)

Y - A -

Y

Y -

Y

1

-+

A

-+

o 1 -

X

CA
CA

1/1
1/1
1/1
1/1
1/1
1/1
1/1

M(n)

1/1
1/1
1/1
1/1
1/1

NB

1/1

NZ

1/1

1/1
1/1
1/1
1/1
1/1

1/1
1/1
NB

1/1

1/1

Y, (X --.. SPX)

Test Discrete I/O Latch D(Y)
1 -+ D(Y)

1/1

1/1

Y - A
Table Branch
M --.. B, (X+-+SPX, Y+-+SPY)
B s MB
A _
B-1--B
A -+ M, Y-1 -

1/1

ST
NB
OVF

B, (X-SPX, Y ........ SPY)

B+1-B
A - M, Y+1 -

1/1
1/1
1/3

A;;; M

M + A + CA AE9M _ A

W/C

NB
NB
NB
NB
D(Y)

1/1
1/1
1/1
1/1
1/1

1/1
1/1
1/1
1/1
1/1

(to be continued)

OP-CODE
00-1l11-00 .•
01-0000-0100
01-0000-1000
01-0000-l100
01-0001-0100
01-0001-1000
01-0001-l100
01-0010- ••••
01-00l1- ••••
01-0100-0000
01-0100-0100
01-0100-1000
01-0100-1100
01-0100-1101
01-0101- ..•.
01-0l10- ••.•
01-0l11- .•..
01-1000-0000
01-1000-01. .
01-1000-10 .•
01-1000-l1 .•
01-1001-0000
01-1001-0100
01-1001-1000
01-1001-l100
01-1010- .•••
01-1011- .•..
01-11 •. - •...
10-0000- ....
10-0001- ...•
10-0010- ... .
10-0011- ... .
10-0100- ...•
10-0101- ...•
10-0110- ....
10-0111- ••.•
10-1000- ..•.
10-1001- ....
10-1010- •.•.
10-1011- ..••
10-1100- ..•.
10-l101- •...
1O-l11O- .•..
10-l1l1- .•..
11- .... - ....

MNEMONIC
LWI
i
ANEMD d
AMD

d

ORMD
ALEMD
AMCD
EORMD
INEMD
ILEMD
COMB
OR
STS
SBY
STOP

d
d

JMPL

u

CALL
BRL

u

d

d
i,d
i,d

B

u
d

SEMD
REMD
TMD

n,d
n,d
n,d

LAMD

d

LMAD
SMCD

d
d

ANMD

d

LMID

i,d

P

P

CAL
LBI
LYI
LXI
LAI
LBR
LAR

a
i

AI
LMIIY
TDD
ALEI
LRB

LRA
,SEDD
XMRA

BR
W/C --- Word/Cycle

-+

A u B

XMAD

REDD
LAMR

FUNCTION
i -+ W
A '" M(d) -+ A
A + M(d) -+ A
A U M(d) -+ A
A ~ M(d)
M (d) + A + CA -+ A, OVF
A EB M(d) -+ A
i of M(d)
i ;:;; M(d)

i
i

i
m
m

i
i
i
i

-+

B

-+

Y
X

-+
-+

R(m)
R(m)

B

-+

A

-+

A

i
i

A + i

-+

A

b

CA

-+

NB
OVF
NZ
NZ

NB

1
1

M(d,n)
NB
NZ

1

D(m)

i -+ M, Y+1 -+ Y
Test Discrete I/O Latch D(m)
A;:;; i
B -+ R(m)
A -+ R(m)
1 --+ D(m)
MR(m) +-+ A
Branch on Status 1

W/C
1/1
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
1/1
1/1
1/1
1/1
1/1
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
1/2
1/2
1/1
1/1
1/1

1/1
1/1
1/1

A
-+

MR(m)

m

-+

A

-+

m

m

OVF
NZ

Start Serial
Standby Mode
Stop Mode
Long Jump Unconditionally
Long Subroutine Jump on Status 1
Long Branch on Status 1
M(d) - - A
1 -+ M(d,n)
o -+ M(d,n)
Test Memory Bit M(d,n)
M(d) -+ A
A -+ M(d)
M(d) - A - ex -+ A, NB -+ CA
A n M(d) -+ A
i -+ M(d)
Pattern Generation
Subroutine Jump on Status 1

o

m
m

NZ

B

m

m
i

STATUS

OVF
NZ

D(m)
NB

1/1
1/1
1/1
1/1

1/1
1/1

1/1
1/1
1/1
1

1/1
1/1

HITACHI 59

4.
4.1

PIN ARRANGEMENT AND PACKAGE DIMENSION
Pin Arrangement (Top View)

8
a:
D"
Do>
D"
D"
D"

()

.."
."."."
..".n.n."
"

• oo

"

D"
D.
D.
D'
D.
D•
D.
D,
D,
D'
D.
GND
05C2

;

..

00

.;

00

00

;0

D,
0,
D•

GND

ose,

.

DSC,

.."."

TEST"

...

RESET

"

."."

A.u/Vdisp

.oo

.".".oo."."
."."...."

R32/iRTO
RJJ/iN'fi

.oo

."
.u
.oo

."
."."

...

(DP-64S)

D"
D"
D..
RA'/Vdt:sp
Roo

R.,
Ro,
Ro,
Roo
Roo

R"
R"

R,.
R"

R"

R"
R30

R"
R32;rmo

AJl/INT,
Vee

(DP-42. DP-42S)

DSC,

TnT
.ESET

."•..

.oo

.u

R.. ,/Vdl

."."
."."
.oo

R.2' SO
$,

V"

60 HITACHI

,; ~6 g~

I II

OCK

i

~

J

~

;:

; I~

"J

0

~ '"'::: ~
.i ~~\~

(0.01 9± 0.004)

~~
8

62 HITACHI

0'-15'

\0.0\~~"1i%\)

5.

ELECTRICALCHARACTERISTICS

5.1

HMCS402/404/408 Absolute Maximum Ratings
Item

Symbol

Supply Voltage

Vee

Terminal Voltage

VT

Total Allowance of .Input Currents
Total Allowance of Output Currents
Maximum Input Current

I:lo
-I:IO
10

Maximum Output Current

-10

Operating Temperature
Storage TemPl/rature

Tapr
Tug

.

.,

.

Value
-0.3 to +7.0
0.3 to Vee+0.3
Vee -45 to Vee +0.3
50
150
15
4
6
30
-20 to +75
-55 to +125

Unit
V
V
V
mA
mA
mA
mA
mA
mA
·C
C

Note
3
4
5
6
7,8
9, 10
9,11
9, 12

..

INat.l1

P.rmanent damage may occur.f Absolute MaXimum Ratings a,. a.cnded. Normal operation should be under the conditions of
"Electrical Characteristics". If these conditions a,. exceeded. it may CIUIlt the malfunction and .ffect the reliability of LSI.

(Not. 2)
INato3)
(Not. 4)
(Not. 5)
(Not. 61
(Not. 7)
(Not.SI
(Note 9)
INat.l0)
INate 111
INot.121

All volt_ ar. with r _ t to GND.
Applied to standard pins.
Applied to high valtogl pins.
Total allowance of input current is the totet sum of input current which flew in from all 1/0 pins to GND simultaneously.
Total allowance of output current is the total sum of the output current which flow out from Vee to all 1/0 pins simultaneously.
Maximum input current is the maximum amount of input current from each 1/0 pin to GND.

Applied to D, - D, ond R3 - R8.
Maximum OUtput current is the mu:imum amount of output current from

Applied to D, - D, and R3 - R8.
Applied to to RO - R2.

Vee to each 1/0 pin.

Applied to O. - 0 15 •

HITACHI 63

5.2

HMCS402C Electrical Characteristics

(1) DC Characteristics
(VCC=4V to 6V, GND=OV, Vdisp=VCC-40V to VCC, Ta=-20 to +75°C, if not specified.)
Item

min

Value
typ

max

rnr., iNr,

0. 7Vee

-

Vee+0.3

SI

0.7Vee
V ce - 0.5

-

Vee+0.3

V

Vee+0.3

V

Symbol

Test Conditions

Pin Name
RESET~K.

Input "High"
Voltage

Input "Low"
Voltage

V'H

OSC,
RESET,Sck,
INTo, iiiiT,
V'L

SCK,SO

Output "Low"
Voltage

VOL

SCK,SO

Input/Output
Leakage Current

-

0.22Vee

V

-

V

-IOH = 1.0 mA

V ee -1.0

-

0.22Vcc
0.5

-

V

-IOH = 0.01 mA

Vce-0.3

-

-

V

10L = 1.6 mA

-

-

0.4

V

Vin = OV to Vee

-

-

1

p.A

1

Current
Dissipation in
Active Mode

-

-

2.0

mA

2,6

-

-

2.4

mA

2,6

-

-

1.2

mA

3,6

-

-

1.6

mA

3,6

-

-

0.9

mA

4,6

-

-

1.3

mA

4,6

-

-

10

p.A

5

2

-

-

V

RESET~,

II'LI

Icc

TNT;, iiiiT"

SI,SO,OSC,

Vee

Vec=5V

Crystal or
Ceramic Filter
Oscillator
Option
I"", = 4MHz
f-iesistor
Oscillator
Option

. 100: = 4MHz

Maximum

ISBYI

VCC

Logic
Operation

Vee = 5V
Current

Dissipation in
Standby Mode
Minimum

ISBY2

VCC

Logic
Operation

Vee = 5V

Crystal or
Ceramic Filter
Oscillator
Option
IOte = 4MHz
Resistor
Oscillator
Option
100: = 4MHz
Crystal or
Ceramic Filter
Oscillator
Option
I"", =4MHz
Resistor
Oscillator
Option

foo: = 4MHz
Current
Dissipation in

I. top

Vee

V,top

Vee

Stop Mode
Stop Mode
Retain Voltage

64 HITACHI

V

-0.3

OSC,
VOH

Note

-0.3
-0.3

SI

Output "High"
Voltage

Unit

Vin(TEST) = Vee-0.3V to Vee
Vin(RESET) = OV to 0.3V

V

INote ,) Pull·up MOS current and output buffer current are excluded.
INote 2) The MCU is in the reset state. The input/output current does not flow.
Test Conditions; MCU state;
• Re.. t state in Operation Mode

• RESET. TEST ... Va:. voltage

Pin state;

• Do- 0), R3- R9 ... Va;; voltage
.O .. -D",RO-R2, RAO,RA1 ... VdisplJoltage
INote 3) The timer/counter operate with the fastest clock and input/output current does not flow.
Test Conditions: MCU state;
• Standby Mode
• Input/Output; Reset state
• TIMER·A; +2 prescaler divide ratio
• TlMER·S; +2 prescaler divide ratio

• SERIAL Interface; Stop
Pin state;

• RESET ···GND voltage

• TEST ... Va:. voltlge
.0,-0,. R3-R9 ... Va:. voltage
• D .. -D IS , RO-R2, RAQ, RA1 ... Vdisp voltage
(Note 4) The timer/counter operate with the slowest clock and input/output current does not flow.
Test Conditions: MCU state;
• Standby Mode
• Input/Output; Reset Itate
• TIMER·A; +2048 prescaler divide ratio
• TIMER·B; +2048 prasealer divide ratio

• SERIAL Interface; Stop
Pin state;

• RESET. ... GNO voltage

• TID ... Va:. voltage
.00 -0), R3- R9 .. ' Vee voltage
• O .. -D,~, RO-R2, RAQ, RA1 ... VdisP voltage
(Note 5) Pull-down MOS current is excluded.
(Note 6) When fosc"'x [MHz] , the Current Dissipation in Operation mode and Standby mode are estimated as fOllows:
max. value (fosc=x(MHz])

(2)

=~x

max. valueUosc""4(MHz])

Input/output characteristics for standard pin
(Vce=4V to 6V, GND=OV, Vdisp=Vee-40V to Vee. Ta=-20 to +75°e. if not specified.)
Item

Input "High"
Voltage

Symbol
V ,H

Input "Low"
Voltage

V ,L

Output "High"
Voltage

V OH

Pin Name

Do

Test Conditions

03.

R3 - R5. R9

Do

03.

R3 - R5. R9

Value
typ

max

0. 7Vee

-

Vee+0.3

V

-0.3

-

0.22Vcc

V

Do - 03.

Input/Output
Leakage Current
Pull-Up MOS
Current

VOL
II'LI

-10

Note

R3 - RS

-loH = 1.0mA

Vee- 1.O

V

1

-IOH = 0.01 mA

Vee-0.3

-

-

Do - 03.

-

V

1

IOL = 1.6 mA

-

-

0.4

V

Vin = OV to Vee

-

-

1

/JA

2

Vee - 5V
Vin =OV

30

60

120

/JA

3

R3 - RS
Output "Low"
Voltage

Unit

min

Do - 03.
R3 - RS

DO

03.

R3- R9

Do

03.

R3 - R9

(Note 1) Applied to I/O pinl With "CMOS" Output .. Iected by mask option.
(Note 2) Pull-Up MOS current and output buffer current are excluded.
(Note 3) Applied to I/O pins with "with Pull-up MOS" selected by mask option.

HITAGHI 65

(3)

Input/output characteristics for high voltage pin
(Vee=4V to 6V, GND=OV, Vdisp=Vee-40V to Vee, Ta=-20 to +75°e, if not specified.)
Item

Symbol

Input "High"
Voltage

V IH

Input "Low"
Voltage

V IL

Output "High"
Voltage

Pin Name
DIS, Rl
04
R2, RAO, RAI
O. DIS, Rl
R2, RAO, RAI

o. - DIs
V OH
RO -R2

o.
Output "Low"
Voltage

015
RO-R2

VOL

Input/Output
Leakage
Current

Ii ILl

Pull Down MOS
Current

Id

(Note 11
(Note 21
(Note 31
(Note 41

Test Conditions

o. -DIS
RO-R2
DIS
RO-R2
RAO, RAI
04-015
RO-R2
RAO, RAI

Value
typ

max

0.7Vee

-

Vee+O.l

V

Vee-4O

-

0.22Vee

V

-IOH=15mA, Vee=5V±10%

Vee- l .O

-IOH=9 mA
IOH=3 mA, Vee=5V±10%
-IOH=I.8mA

Vee-2.O
Vee 3.0
Vee-2.O

Note

V

150kn to Vee-40V

-

-

Vin • Vcc-40V to Vee

-

-

20

IJA

3

125

250

500

IJA

4

V diop = V ee -40V

o.

V diIP = Vee-35V
V in =Vee

Applied to 1/0 pin. with "with Pull-down MOS" ..Iected by mo.k option.
Applied to 1/0 pin. with "without Pull·down MOS (PMOS Open Oroinl" ..Iected by mOlk option.
Pull·down MOS curront end output buffer current are excluded.
Applied to 1/0 pin. with "with Pull·down MOS" selected by ma.k option.

66 HITACHI

Unit

min

-

V
V
V

Vee-37

V

1

Vee-37

V

2

(4) Ae characteristics
(Vee=4V to 6V, GND=OV, Vdisp=Vee-40V to Vee, Ta=-20 to +75°e, if not specified.)
Symbol

Item

Pin Name

Test
Conditions

min

Value
typ

max

Unit

Oscillation Frequency

fooo:

0.4

4

4.5

~.~ ~

Instruction Cycle Time

tcyc

1.78

2

20

IlS

u~O

Oscillator Stabilization
Time

tRC

OSC,.OSC,

-

-

20

ms

OSC,.OSC,

o~
~

S
~

...

OSC,.OSC,

1.8

3.0

4.2

MHz

1.9

2.66

4.44

IlS

-

-

0.5

ms

1

0.4

4.5

MHz

2

92

-

-

ns

2

OSC,

92

-

-

ns

2

tCPr

OSC,

2

OSC,

-

ns

tcP!

-

20
20

ns

2

1.78
2
2

-

20

IlS

2

-

-

tcye
tcye

3
3
3

tcye

a:C5

Oscillator Stabilization
Time

tRC

OSC,.OSC,

External Clock Frequency

fcp

OSC,

External Clock "High"
Level Width

tCPH

OSC,

sC

...- /

~"' O.S
~

3

ISB Yl
max

4

5

6

o

VeeVI
Icc VS. Vee Characteristics
(Crystal, Ceramic Filter Oscillator)

ISB Y2
max,

...-V

.5!!

o

I

Ta = -20 - +7Soe
fosc""2MHz
1.0

4

S

6

Vee(V)
ISBY VS. Vee Characteristics
(Crystal, Ceramic Fi Iter Oscillator)

500
Ta=-20-+75"C

400

Ta = -20 - +7soe

soo

max.

L

;;(
-3300

I

400

~

II

I

200

100

o

./

,.,.. /
::::: r::::- I -

41

2

3

-- -

4
Vee(V)

./'

max.

V

---

t yp.

V

200

min.

I--

5

I

I/

J

min.

'//

I

V

-Ip (Pull-up MOS Current) vs.
Vee Characteristics
15

typo

/'

/

100

6

I

o

20

10

30

40

so

Vee-VdiSP(V)

Ta = -20 - +7soe
Vee=6V

Id (Pull-down MOS Current) YS.
(Vee-Vdi,p) Characteristics

/

A sv
veey
/
LI
/
ve~
/

10

;;(

E
c:

E

./

/,

~

2

//

1

/'/

V

c

~'/

,
o

'E

is

///

~

l?- i-"

t----+--+---j;,.L~j...._o<~+_-__l

Vee=4V

1o::.._...I..=~==,,===!:===t::=::=::JVee=2.7V

2

VOL(V)
IOL min. VS. VOL Characteristics
(Standard Pin)

76 HITACHI

Vee=SV
2

"i

Vee = 2.7V

---

Ta = -20 - +7Soe

31-_-+-_--t_ _+-_-+__~"""'-_lVee=6V

3

2

3

Vee-VOH (V)
-IOH min. vs. (Vee-VOH) Characteristics
(Standard Pin "CMOS")

30

Ta' -20 - +75°C
VCC-6V

V
Y

/.1

~20

«

VCC- 5V

/

E

.....-11

/

r

h

I

~
~

10

...,..

o

~

./

;( 4

/

.§

~

I I
VCC=2.7~

[/"
},V

,/

VC;:::'"

V

Ta= -20- +75"C

5

T ......-

V V
.E

6

I

/ V
1/V

3

:r

o
I

/ VV

2

/10 V

V

~

V' V

V
L

VCC-5V

/"

..-

-

VCC=4V

- --

VCC-2.7V

f-

W I-

VCC-6V

L.

I,e f-"
3

4

5

o

VCC-VOH IV)

2

3

4

5

VCC-VOH (VI

-IOH min. vs. (VCC-VOH) Characteristics

-IOH min. vs. (VCC-VOH) Characteristics

(D. - 0" Pins)

(RO - R2 Pins)

HITACHI 77

5.4 HMCS402AC Electrical Characteristics
(1)

DC characteristics (VCC=4.5V to 6V, GND=OV, Vdisp=VCC-40V to VCC, Ta=-20 to +75°C,
if not specified.)
Value
Item

Input "High"
Voltage

Pin Name

Symbol

Test Conditions

RESET, SCK,
INTo, INTI
VIH

SI
OSC,

Input "Low"
Voltage

Output "High"
Voltage
Output "Low"
Voltage

typ

max

0. 7Vee

-

Vee+0 .3

0. 7V ee

-

Vee+0.3

V

Vee- 0•5

Vee+0 .3

V

-0.3

-

0.22V ee

V

RESET,SCK,
INTo,lNTI
V IL

Unit

min

V

SI

-0.3

-

0.22Vee

V

OSC,

-0.3

-

0.5

V

-

V

-

V

0.4

V

VOH

SCK, SO

VOL

SCK, SO

-IOH = 1.0 mA

Vee- 1.O

-IOH = 0.01 mA

Vee- 0.3

IOL = 1.6 mA

-

-

RESET,~,

Note

Input/Output
Leakage Current

IIILI

i'NTo, INTI
51, SO, OSC,

Vin=OVtoVee

-

-

1

p.A

1

Current
Dissipation in
Active Mode

lee

Vee

Vee = 5 V
fose = 6 MHz

-

-

3.0

mA

2,6

ISBYI

Vee

Maximum Logic Operation
Vee = 5 V
fose = 6 MHz

-

-

1.8

mA

3,6

ISBY2

Vee

Minimum Logic Operation
Vee = 5 V
fos e = 6MHz

-

-

1.35

mA

4,6

Current
Dissipation in
Stop Mode

Istop

Vee

ViA (TEST) = Vee -0.3V to Vee
V in (RESET) = OV to 0.3 V

-

-

10

p.A

5

Stop Mode
Retain Voltage

V"op

Vee

2

-

-

V

Current
Dissipation in
Standby Mode

INote 1) Pull-up MOS current and output buffer current are excluded.
(Note 2) The MCU is in the reset state. The input/output current does not flow.
• Reset state in Operation Mode
Test Conditions: MCU state;

Pin state;

• RESET, TEST

00.

Vrx; voltage

.00 -0 3 • R3 -A9· .. Vee voltage
.0.-0 15 • AO- R2, ANJ' RA1 ... Vdisp voltage
(Note 3) The timer/counter operate with the fastest clock and input/output current does not flow.

Test Conditions:

MCU state;

• Standby Mode
• Input/Output; Reset state
• TIMER·A; +2 prescaler divide ratio

• TIMER-a; +2 prasealer divide ratio

• SERIAL Interface; Stop
Pin state;

• RESET ... GND voltage

• TEST ... Vrx; voltage
.0 0 -0 3 • R3- R9· .. Vee voltage
• 0.-0 15 • RO-R2, R,AD. RA1 ... Vdisp voltage
(Note 4) The timer/counter operate with the slowest clock and input/output current does not flow.
Test Conditions: MCU state;
• Standby Mode
• I nput/Output; Reset state
• TIMER·A; +2048 prescaler divide ratio
• TIMER·S; +2048 prasealer divide ratio

• SERIAL Interface; Stop
Pin state;

• RESET.... GND voltage

• fEST ... Vrx; voltage
.00 -0 3 • R3-A9· .. Vee voltage
.0.-0 15 , RO-R2, RAQ. RA1 ... Vdisp voltage
(Note 5) Pull·down MOS current is excluded.
(Note 6) When fosc=x (MHzI . the Current Dissipation in Operation mode and Standby mode are estimated as follows:
max. value (fo1c=x[MHz]) =ix max. value (f o1c ""6 [MHz])

78 HITACHI

(2)

Input/output characteristics for standard pin
(Vee=4.5V to 6V, GND=OV, Vdisp=Vee-40V to Vee, Ta=-20 to +75°e, if not specified.)
Item

Symbol

Input "High"
Voltage

VI ...

Input "Low"
Voltage

V IL

Output "High"
Voltage

Vo ...

Output "Low"
Voltage

VOL

Input/Output
Leakage Current
Pull·Up MOS
Current

\lILI
-Ip

Pin Name

0,
R5. R9
0,.
R5. R9
0, .
RS
0,.
RS
0,.
RS
0,.
R9
0,.
R9

Do
R3 Do
R3 Do R3 Do
R3 Do R3 Do R3 Do
R3 -

Value

Test Conditions

Unit

Note

min

typ

max

0. 7Vee

-

Vee+0.3

V

-0.3

-

0. 22Vcc

V

-1 0 ... =1.0mA

Vee- 1.O

-

-

V

1

-1 0 ... = 0.01 mA

Vee-O.3

-

-

V

1

10L = 1.6 mA

-

-

0.4

V

Vin = OV to Vee

-

-

1

jJA

2

Vee - SV
Vi" = OV

30

60

120

jJA

3

(Note 1) Applied to 1/0 pins with "CMOS" Output selected by mask option.
(Note 2) Pull-up MOS current and output buffer current are excluded.
(Note 3) Applied to 110 pins "with Pull-up MOS" selected bv mask option.

(3)

Input/output characteristics for high voltage pin
(Vee=4.5V to 6V, GND=OV, Vdisp=Vee-40V to Vee, Ta=-20 to +75°e, if not specified.)
Item

Input "High"
Voltage
Input "Low"

VQlta_ge
Output "High"
Voltage

Symbol
VI ...
V IL

Pin Name

0 4 - 0 15 . Rl
R2. RAO. RAI
04-015. Rl
R2. RAO. RAI
04

-

015

V OH
RO - R2

0"
RO - R2

D4 -

Output "Low"
Voltage

VOL

Input/Output
Leakage
Current

I1ILI

Pull Down MOS
Current

I.

Value

Test Conditions

04 RO 04 RORAo.

015
R2
015
R2
RAI

0 4 - 0"
RO- R2
RAO. RAI

Unit

min

typ

max

0.7Vee

-

Vee+0.3

V

Vee - 4O

-

O. 22Vee

V

-

V

-

-

-

V
V
V

Note

-IOH=ISmA. Vee=SV ± 10%

Vee-3.O

-IOH=9mA
IOH 3mA. Vee SV ± 10%
-IOH=I.BmA

Vee-2.O
Vee-3.O
Vee- 2.O

V.if<> = Vee-4OV

-

-

Vee-37

V

1

IS0kf! to V ee -40V

-

-

V ee -37

V

2

Vi" • Vee-40V to Vee

-

-

20

jJA

3

12S

2S0

SOO

jJA

4

V. IIP = Vee -3SV
Vi" = Vee

(Note 1) Applied to lID pins "with Pull-down MOS" selected by mask option.
INote 2) Applied to 110 pins "without Pull-down MOS (PMOS Open Drain)" selected
INote 31 Pull-down MOS current and output buffer current are excluded.
INote 4) Applied to 110 pins "with Pull-down MOS" selected by mask option.

by

mask option.

HITACHI 79

(4) Ae characteristics
(Vee=4.5V to 6V, GND=QV, Vdisp=Vee-40V to Vee, Ta=-20 to +75°e, if not specified.)
Value
Symbol

Item

Pin Name

Test Conditions

Unit

min

typ

max

0.4

6

6.2

MHz

Oscillation Frequency

folc

Instruction Cycle Time

tCYC

1.29

1.33

20

j.ls

Oscillator Stabilization Time

tRC

OSC.,OSC.

-

ms

1

External Clock "High"
Level Width

tCPH

OSC.

61

-

20

-

ns

2

External Clock "Low"
Level Width

tCPL

OSC.

61

-

-

ns

2

External Clock Rise Time

tcp,

OSC.

20

ns

2

tCPI

OSC.

-

-

External Clock Fall Time

-

20

ns

2

INTo "High" Level Width

tlOH

iNTo

2

-

tcyC

3

iNiO "Low" Level Width

tlOL

INTo

2

tCYC

3

fiiIT1
fiiIT1

"H igh" Leve I Width

tllH

INT.

2

t cvc

3

"Low" Level Width

til L

INT.

2

RESET "High" Level Width

tRSTH

RESET

2

Input Capacitance

Cin

all pins

RESET Fall Time

tRSTI

~Note 1)

OSC',OSC.

Note

f; 1 MHz
Vin; 0 V

-

-

-

-

15

pF

-

-

20

ms

tCYC

3

tcyc

4

4

Oscillator stabilization time is the time until the oscillator stabilizes after Vee reaches 4.5V at "Power-on", or after RESET input level goes
"High" by resetting to quit the stop mode by MCU reset. At power ON or recovering from stop mode, apply RESET input more than 'tAc
to obtain the necessary time for oscillator stabilization. The circuits used to measure the value are described below. When using crystal or
ceramic filter oscillator, please ask a crystal oscillator maker's or ceramic filter maker's advice because oscillator stabilization time depends
on the circuit constant and stray capacity.
Crystal oscillator

Cryst.l: 6.0MHz NC·18C (Nihon Denpa Kogyol
RI : lMn <2%
C, : 20pF < 20%
C, : 20pF <20%

Ceramic filter oscillator

Ceramic filter: CSA6.00MG (Murata)

RI

: lMn <2%

C,
C,

: 30pF ± 20%
: 30pF ± 20%
(No.e31

(Note 2)

OSC,

!CPr
(Not. 41
RESET

80 HITACHI

'CPt

(5)

Serial interface timing characteristics
(Vee=4.5V to 6V, GND=OV, Vdisp=Vee-40V to Vee, Ta=-20 to +75°e, if not specified.)
At Transfer Clock Output
Item

•

Symbol

Pin Name

Test
Conditions

min

Value
typ

max

Unit

Note

Transfer Clock Cycle Time

tScyc

SCK

(Note 2)

1

-

-

tCYC

1,2

Transfer Clock "High"
Level Width

tSCKH

SCK

(Note 2)

0.5

-

-

tScyC

1,2

Transfer Clock "Low"
Level Width

tSCKL

SCK

(Note 2)

0.5

-

-

t ScyC

1,2

-

100
100

ns

1,2

ns

1,2

250

ns

1,2

-

ns

1

-

ns

1

I

Transfer Clock Rise Time

tSCKr

SCK

(Note 2)

-

Transfer Clock fall Time

tSCKf

SCK

(Note 2)

-

Serial Output Data
Delay Time

(Note 2)

toso

SO

Serial Input Data Set·up Time

tssl

Serial Input Data Hold Time

tHSI

51
51

150

-

min

Value
typ

300

At Transfer Clock Input
Item

Symbol

Pin Name

Test
Conditions

Transfer Clock Cycle Time

t ScyC

S-C-K

1

Transfer Clock "H igh"
Level Width

tSCKH

SCK

0.5

Transfer Clock "Low"
Level Width

tSCKL

SCK

0.5

-

Transfer Clock Rise Time

tSCKr

SCK

Transfer Clock fall Time

tSCKf

SCK

Serial Output Data
Delay Time

toso

SO

Serial I nput Data Set·up Time

tSSI

Serial Input Data Hold Time

tHSI

51
51

-

(Note 2)

JOO
150

-

-

max

-

-

Unit

Note

teye

1

tsCYC

1

tScYC

1

100

ns

1

100

ns

1

250

ns

1,2

-

ns

1

ns

1

(Note 1) Timing Diagram of Sanal Interface

so

____-«

51

H·
SSI

0.7Vee

'-____

0.22Vcc

• Vee - 2.0V and O.BV are the threshold voltage for transfer clock output.

(Nole21

;pq

0.7

Vee end 0.22 Vee ere.he threshold vollage for Iran.fer clock inpul.

Timing Load Circuit

Vee

Test
Pomt

C

30pF

RL=2.6i<"

R

1520748

12kU

or EquN.

HITACHI 81

(6)

Characteristics Curve (Reference data)
2.4

Ta=-20-+75'C
. fosc=6MHz
2.0

max

4

/

Ta- -20- +75'C
fosc=6MHz

3

/

o

2

3

I
./

5

4

malx .
IS8V2

// max

/

1.6

158. 1

/

0.4

6

Vcc(V)

o

Icc vs. Vee Characteristics
(Crystal, Ceramic Filter Oscillator)
500

2

3

4

5

'SBY vs. Vee Characteristics
(Crystal, Ceramic Filter Oscillator)

Ta'!-dO-~75'C

Ta=-20 - +75·C

400

500

«
300
.;!

.....- ~

T 200

......-

/

100

I-

./

max .

~t yp.

min.

I-- f - r5

4

3

2

6

~

«

I

tyP'1

"......

/

'/
100
I

+Il)'{;

,;lU'

I

:i 200 I

o

ma~.

II

300

Vcc(V)
-Ip (Pull·up MOS Current) vs.
Vee Characteristics

5 la

...-

I

400

a.

o

6

Vcc(V)

min.

/
10
20
30
40
Vcc-Vdisp(V)
Id (Pull·down MOS Current) vs.
(Vee - Vdi'p) Characteristics

50

Vcc=6V

./'"
/

/

~10

/

E

/

c:

'E

Vcc=5V

..... 1-""
,/
"..--

'/ L
// ./'"

Vcc=4.5V

~

E 3~--+---+---+---~--~~~

c:

.~ 2~-+--+---,j~:""'¥::::'~-===I

.E
I

~./

5

#. V

2
VCC-VOH(V)

/Y

-IOH min vs. (Vee - VOH) Characteristics
(Standard Pin "CMOS")

/

IL
o

82 HITACHI

3

2
VoL(V)
IOl min. VS. VOL Characteristics
(Standard Pin)

3

30

V

Ta=-20-+75'C

1/
/
20

V

/

6

v

Ta=-2 - +75'C

Vcc=4.5V

/

1/

4

/ V

l-

/

//
'/

/.
V

V

o

2

3
4
Vee-VOH(V)

V

5

/

5

-IOH min. VS. (Vee - VOH) Characteristics
(0 4 - DIS Pins)

o

lJ

J~
V

V

V
./

V

V

~ Vcc=4.5V

V:/l/
V

2

3

4

5

Vee-VOH(V)
-IOH min. vs. (Vee - VOH) Characteristics
(RO - R2 Pins)

HITACHI 83

5.5

HMCS404C Electrical Characteristics

(1)

DC characteristics
(VCC=4V to 6V, GND=OV, Vdisp=VCC-40V to VCC, Ta=-20 to +75°C, if not specified.)
Item

Symbol

Test Conditions

Pin Name

Input "Low"
Voltage

V'H

max

fN'!'O, 1N'F;

0. 7Vee
0.7Vec
V ee - 0.5

-

Vee+0.3

SI

Vee+0.3

V

-

Vee+0.3

V

OSC,
RESET,SCK,
INTo,lNT,
V'L

-0.3
-0.3

SI

-0.3

OSC,
Output "High"
Voltage

VOH

SCK, SO

Output "Low"
Voltage

VOL

·SCK,SO

Input/Output
Leakage Current

Current
Dissipation in

Icc

"i1'fTo, T"NT. ,

V

Yin = OV to Vee

-

-

1

/JA

1

-

-

2.0

mA

2,6

-

-

2.4

mA

2,6

-

-

1.2

mA

3,6

-

-

1.6

mA

3,6

-

-

0.9

mA

4,6

-

-

1.3

mA

4,6

-

-

10

/JA

5

2

-

-

V

Vee=5V

Logic
Operation

Minimum

Crystal or
Ceramic Filter
Oscillator
Option
tooc = 4MHz
Resistor
Oscillator
Option
f"" = 4MHz
Crystal or
Ceramic Filter
Oscillator
Option
tOle = 4MHz
Resistor
Oscillator

Logic
Operation
Vee = 5V

Crystal or
Ceramic Filter
Oscillator
Option
t"", =4MHz
Resistor
Oscillator

Option
fooc = 4MHz

Istop

Vee

Stop Mode
Retain Voltage

V. top

Vee

84 HITACHI

V

V

0.4

Option
f"" = 4MHz

Current
Dissipation in
Stop Mode

V

-

Vee = 5V

Vce

V

-

Current
Dissipation in
Standby Mode

ISBY2

V

0.22Vcc
0.5

-

Maximum

Vec

0.22Vee

Vee-0.3

-IOH = 0.01 mA

Active Mode

ISBY'

V

10L = 1.6 mA

Vee-1.O

SI,SO,OSC,

Vee

Note

-

-loH = 1.0 mA

RESET, SCl<.

II'LI

Unit

typ

RESET~

Input "High"
Voltage

Value
min

Vin(TEST) = Vcc-0.3V to Vee
Vin(RESET) = OV to O.3V

(Nol.'1 Pull-up MOS currant and output buffer current are excluded.
INoto21 The MCU is in the resat state. The input/output current does not flow.
Test Conditions:

MCU state;

• Reset state in Operation Mode

Pin ..ate;

0 RESET. TEST ... Va; voltage
00.- 0,. R3 - R9 ... Va; voltage
• 04-0U. AD-R2. RAQ' RA1 , .. Vdisp voltage
(Note 31 The timer/counter operate with the fastest clock and input/output current does not flow.
Test Conditions: MCU state;
• Standby Mode
• Input/Output; Reset state

• TIMER-A; +2 prescaler divide ratio

• TlMER-S; +2 presealer divide ratio

o SERIAL Interface; Stop
0 RESET ... GND voltage
o TEST ... Va; voltage
00.-0,. R3- R9 ... Vee voltage

Pin stata;

• O.-D u

•

RO- A2. RAQ. RA1 ". Vdisp voltage

(Note 41 The timer/counter operate with the slowest clock and input/output current does not flow.
Test Conditions:

MCU state;

• Standby Mode
• Input/Output; Reset state
• TIMER-A; +2048 prescaler divide ratio
• TIMER-8; +2048 prescaler divide ratio

Pin stata;

• SERIAL Interlace; Stop
0 RESET ... GND voltage
o TEST ... Va; voltage
• Do -0 3 • A3- R9 ... V cc voltage

.0 4 -0 15 • RO-A2. RAQ. AA1 ... Vdispvoltage
(Note 5) Pull-down MOS current is excluded.
(NotaSI When fosc=xlMHz]. the Currant Dissipation in Operation mode and Standby mode are estimated as follows:

rna •. valua (losc=x[MHzll ~~. mo •. value (lolC=4[MHzll

(2)

Input/output characteristics for standard pin
(Vee=4V to 6V, GND=OV, Vdisp=Vee-40V to Vee, Ta=-20 to +75°e, if not specified.)
Item

Symbol

Pin Name

Test Conditions

D. D••
R3 - RS. R9
Input "Low"
Do -D ••
V IL
Voltage
R3 - RS. R9
D. -D ••
-loH=I.0mA
Output "High"
R3- RS
V OH
Voltage
D. - D••
-IOH = 0.01 mA
R3 RS
Do - D•.
Output "Low"
VOL
IOL = 1.6 mA
Voltage
R3 RS
D. - D•.
Input/Output
Vin = OV to Vcc
!lILI
Leakage Current
R3 R9
D. - D••
Vee - 5V
Pull·Up MOS
-Ip
Current
Vin = OV
R3 R9
(Note 1) Appliad to 1/0 pins with "CMOS" Output selected by mask optIon.
Input "High"
Voltage

V IH

Value

Unit

Note

min

typ

max

0.7Vee

-

Vee+0 .3

V

-0.3

-

0.22Vcc

V

Vee- 1.O

-

1

-

-

V

Vee-0•3

V

1

-

-

0.4

V

-

-

1

llA

2

30

60

120

llA

3

(Note 2) Pull-up MOS current and output buffer current are excluded.

(Nota 31 Appliad to 1/0 pins with "with Pull·up MOS" ••Iected by m.. k option.

HITACHI 85

(3)

Input/output characteristics for high voltage pin
(Vee=4V to 6V, GND=OV, Vdisp=Vee-40V to Vee, Ta=-20 to +75°e, if not specified.)
Item

Symbol

Input "High"
Voltage

V'H

Input "Low"
Voltage

V'L

V OH

Output "Low"
Voltage

VOL

Input/Output
Leakage
Current

II'LI

Pull Down MOS
Current

Id

Test Conditions

-

015

RO - R2
D4 - DIs
RO - R2

0 4 - 015
RO - R2
0 4 - 015
RO - R2
RAO, RAl
D.-DIS
RO-R2
RAO, RAl

Value

Note

typ

max

O.7Vcc

-

Vcc+O.3

Vee-4O

-

O. 22Vee

V

-IOH=15mA, Vee=5V±10%

Vee-3.O

-

-IOH=9 rnA
-IOH-3 rnA, Vee-5V±10%
-IOH-1.8 rnA

Vee-2.O
Vee-3.O
Vee-2.O

-

-

V

V d;,p = Vee -40V

-

-

V cc -37

V

1

150k!1 to Vcc-4OV

-

-

V ee -37

V

2

-

-

20

IlA

3

125

250

500

IlA

4

Vin

= Vee-40V to Vee

Vd;sp = Vec-35V
Vin = Vee

Applied to lID pins with "with Pull-down MOS" selected by mask option.
Applied to 110 pins with "without Pull-down MOS (PMOS Open Drain)" selected by mask option.
,Pull-down MOS current and output buffer current are excluded.
Applied to 1/0 pins with "with Pull-down MOS" selected by mask option.

86 HITACHI

Unit

min

0 4 - 0 15 , Rl
R2, RAO, RAl
0 4 - 0 15 , Rl
R2, RAO, RAl
04

Output "High"
Voltage

(Note 11
(Note 2)
(Note 3)
(Note 41

Pin Name

V

V
V
V

(4)

AC characteristics
(VCC=4V to 6V, GND=OV, Vdisp=Vee-40V to Vee, Ta=-20 to +75°e, if not specified.)
Item

Symbol

Test
Conditions

Pin Name
OSC,.OSC,

min

Value
typ

max

0.4

4

4.5

1.78

2

20

IJ.S

-

-

20

ms

Unit

Note

MHz

Oscillation Frequency

fa""

~ .~~

Instruction Cycle Time

tCyc

u~O

Oscillator Stabilization
Time

tAC

OSC,.OSC,

Oscillation Frequency

fa""

OSC,.OSC,

RI=20k1H2%

1.8

3.0

4.2

MHz

Instruction Cycle Time

tCYC

RI=20kll±2%

1.9

2.66

4.44

IJ.S

Oscillator Stabilization
Time

tAC

OSC,.OSC,

RI=20kll±2%

-

-

0.5

ms

1

External Clock Frequency

fcp

OSC,

0.4

-

4.5

MHz

2

External Clock "High"
Level Width

tCPH

OSC,

92

-

-

ns

2

92

-

-

ns

2

-

-

20
20
20

ns

2
2
2
3
3

o~ S
~ l!

&!

0

~
o~

.~~

'" "
a:O

'""0

U
'iii

External Clock "Low"
Level Width

tCPL

asc,

~
x

External Clock Rise Time

tCPr

OSC,

External Clock Fall Time

tcp,

OSC,

Instruction Cycle Time

tCYC

E

w

1.78

2
2

INT,

2
2
2

-

-

-

-

15

pF

20

ms

tlOH

INTo "Low" Level Width

t,OL

INT, "High" Level Width

t'IH
tilL
tRSTH

TNii

Input Capacitance

Cin

all pins

RESET Fall Time

tRST!

RESET "High" Level Width

IJ.S

-

INTo
INTo

INTo "High" Level Width

INT, "Low" Level Width

ns

RESET
f=lMHz
V in = OV

teve
teye
teye
teye
teye

1

3
3
4

4

(Note 11 Oscillator stabilization time IS the time until the oscillator stabilizes after V(X reaches 4.0V at "Power-on", or after RESET Input
level goes to "High" by resetting to Quit the stop mode by MCU reset on the circuits below. At power ON or recovering from stop
mode, apply RESET input more than tAC to obtain the necessary time for oscillator stabilization. When using crystal or ceramic
filter oscillator, please ask a crystal oscillator maker's or ceramic filter maker's advice because oscillator stabilization time depends on
the circuit constant and stray capacity.
Crystal oscillator

Ceramic filter oscillator

e

Resistor oscillator

sc,

RI

OSC,

GND
Ceramic filter: CSA4.00MG (Murata)

Crystal: 4.194304MHz NC-18CINihon Denpa Kogyo)

C, : 22pF.20%

RI: lM.Il±2%
C. : 30pF.20%

C. : 22pF±20%

C. : 30pF '20%

RI: IM.Il ,2%

RI : 20k.ll±2%

INote 3)

INote 2)

OSC,

tCPr

tCPf

(Note 4)
RESET

tRSTI

HITACHI 87

(5)

Serial interface timing characteristics
(VCC=4V to 6V, GND=OV, Vdisp=VCe-40V to Vee, Ta=-20 to +75°e, if not specified.)
Symbol

Item

Test
Conditions

Pin Name

min

Value
typ

Unit

Note

t cvc

1,2

tsCYC

1,2

t ScyC

1,2

100
100

ns

1,2

ns

1,2

300

ns

1,2

ns

1

-

-

ns

1

min

Value
typ

max

(Note 2)

1

-

Transfer Clock Cycle Time

tScvc

SCK

Transfer Clock "High"
Level Width

tSCKH

SCK

(Note 2)

0.5

Transfer Clock "Low"
Level Width

tSCKL

SCK

(Note 2)

0.5

Transfer Clock Rise Time

tSCKr

SCK

(Note 2)

-

Transfer Clock Fall Time

tSCKf

SCK

(Note 2)

-

Serial Output Data
Delay Time

toso

SO

(Note 2)

Serial Input Data Set-up Time

tSSI

SI

Serial Input Data Hold Time

tHSI

SI

500
150

-

-

max

-

• At Transfer Clock Input
Item

Symbol

Test
Conditions

Pin Name

Transfer Clock Cycle Time

t ScyC

SCK

1

-

Transfer Clock "High"
Level Width

tSCKH

SCK

0.5

-

Transfer Clock "Low"
Level Width

tSCKL

SCK

0.5

Unit

Note

-

tCYC

1

tscvc

1

-

tsCYC

1

100

ns

1

100

ns

1

Transfer Clock Rise Time

tSCKr

SCK

-

Transfer Clock Fall Time

tSCKf

SCK

-

-

Serial Output Data
Delay Time

toso

SO

-

-

300

ns

1,2

Serial Input Data Set-up Time

tSSI

SI

500

-

-

ns

1

Serial Input Data Hold Time

tHSI

51

150

-

-

ns

1

(Note 2)

(Note 1) Timing Diagram of Serial Interface
tScvc

so

_ _ _ _-«

51

H

0.7Vee

'-____

.

'S5I

0.22Vec

* Vee - 2.0V and O.8V are the threshold voltage for transfer clock output.
0.7 Vee and 0.22 Vee are the threshold voltage for transfer clock input.

INole21

Timing Load Circuit

;P:}

Vee

Test
Point

C

30pF

88 HITACHI

RL =2.6"0

R

15207411

12k~l

or Equi\l.

(6)
4

Characteristics Curve (Reference data)
4

Ta=-20- +75'C
Vcc=5V

Ta- 20 +75'C
fosc=4MHz

3

Vax.

..... max.

/""

~

1

V

V

o

o

5

4

3

2

2

3

fosdMHz}
ICC vs. fol.Characteristics
(Crystal, Ceramic Filter Oscillator Option)

4

Ta- 20
Vcc=5V

3

V

max .

-<

/'
V
.......
V
/'

~

0.5

600

..

-<

..!'

100

I

... V

l/

V

I-- 1::::: V

-

40

Iyp1 -

min

J
6'

Vee (V)

- Ip vs VCC Characteristics

116HITACMJ

divide-~y-l~

10

ISBY vs VCC Characteristics
(Crystal, Ceramic Filter
Oscillator Option)

ICC vs VCC Characteristics
(Crystal, Ceramic Filter
Oscillator Option)

17 J-

fosc-4MHz '~E f--divide-byfosc-4MHz ,-f---

I I

Vee (V)

200

fos~-4Jz,
~
divide.,by-4

6
,
Vee (V)

o

10

I

500

..
.

-<

>-<

400
800
200
100

~ax

V

I
I
t yP

l

V

V

~in

V
10

20

30

400

50

60
70
Vee -V .... (V)

Id vs (VCC - Vdisp) Characteristics

L=~v L~5V I

v

5.0

)~
I~VV

Vee =4.5V
~ Vee =3.5V

4. 0

I'-4'-10SC,
GND
Crystal: 2.097152MHz
DS-MGQ 308 (Soiko)
Rf = 1MO ± 20%. Rd = 2.2kO ± 20%
C. = C, = 10pF ± 20%

tCPr

tCPf

(Note 3)

(Note 4)
RESET
tRSTf
Ceramic filter: CSA. 2.000MK (Murata)
Rf = 1 [MOl ± 20%. C•• C, = 30[pFl ± 20%

124 HITACHI

5.14 HMCS412AC Electrical Characteristics
(11 DC characteristics (Vee· 4.5V to 6V. GND • OV. Vdisp· Vcc-4DV to Vee. Ta = -20 to +75°C, if not specified. I
Item

Symbol

Pin Name

Test Conditions

Value
typ

max

O.aVCC

-

VCC+0.3

V

RESET.
Input "High"
Voltage

R32/~'

VIH

Note

R•• /INT,

Vcc-O·5

-

Vcc+O·3

V

RESET,
R32I1 NTo,
R3./iiii'f;"

-0.3

-

0.2Vcc

V

OSC,

-0.3

-

0.5

V

-

-

1

IJA

1

OSC,
Input "Low"
Voltage

Unit

min

VIL

,

Input/Output
Leakage Current

IIILI

RESET,
R.2I1NTo
R•• /I1iIT7,OSC,

Vin = OV to VCC

Current
Dissipation in
Active Mode

ICC

VCC

VCC 5V, tosc = 4MHz
divide·by·4

-

-

3.0

mA

2,5

~;:~~~~i~oi~e

ISBY

VCC

VCC - 5V, tosc = 4MHz
divide·by·4

-

-

1.4

mA

3,5

Current
Dissipation in
Stop Mode

Istop

VCC

Vin (TESTI =VCC-O.3VtoVCC
VCC, Vin (RESETI = 0 to 0.3V

-

-

10

jJA

4

Stop Mode
Retain Voltage

Vstop

VCC

2

-

-

V

!:iurrent

=

{Nota II Pull-up MOS current and output buffer current are excluded.
{Nota 21 The MCU is in the reset state. The input/output current does not flow.
MCU state;
• Reset state in Operation Mode
Test Conditions:
Pin state;
a RESET. TEST •.. Vee voltage
aD. - D•• R3 - R4 ... Vee voltage
"a 0, - 0". RO - R2, RAI ... Vdisp voltage
(Nota 31 The timer/counter operate with the fastest clock and input/output current does not flow.
Test Conditions:
MCU state;
• Standby Mode
• Input/Output; Reset state
a RESET ••. GND voltage
Pin stata;
a TEST •.. Veevol_
aD. - D•• R3 - R4 '" Vee voltage
aD, - 0". RO - R2, RAI ... Vdisp voltage
{Note 41 Pull·down MOS current is excluded.
{Note 51 When fose = x [MHz) • the Current Dissipation in Operation m~e and Standby mode are estimated 81 follows:
max. value {lose' x[MHz[ I =fx max. value (lose· 4[MHz[)

HITACHI 125

(2) Input/output characteristics for standard pin
(VCC = 4.5V to 6V. GND = OV Vdisp = VCC-4DV to VCC Ta = -20 to +15°C if not specified.)
Item
Input "High"
Voltage

Symbol

Pin Name

Value

Test Conditions
min

typ

max

Unit

VIH

Do - D3• R30 •
R31 • R4

0.1Vee

-

Vee+0.3

V

Input "Low"
Voltage

VIL

Do - D 3• R30 •
R31 • R4

-0.3

-

0.3Vee

V

Output "High"
Voltage

VOH

Note

Do - D 3• R30 •
R31 • R4

-IOH = 1.0mA

Vee-1.O

-

-

V

1

Do - D3• R30 •
R31 • R4

-IOH =O.5mA

Vee-0.5

-

-

V

1

VOL

Do - D3• R30 •
R 31 • R4

IOL = 1.6mA

-

-

0.4

V

Input/Output
Leakage Current

IIILI

Do - D3• R30 •
R31 • R4

Vin = OV to Vee

-

-

1

p.A

2

Pull·Up MOS
Current

-Ip

Do-D3. R30.
R31 • R4

Vee = 5V
Vin = OV

30

60

150

p.A

3

Unit

Note

Output" Low"
Voltage

(Note 1) Applied to 110 pins with "CMOS" Output selected by mask option.
(Note 2i Puii-up MOS current and output buffer current are excluded.
(Note 3) Applied to 110 pins with "with Pull-up MOS" selected by mask oPtion.

(3) Input/output characteristics for high voltage pin
(Vee = 4.5V to 6V. GND = OV. Vdisp = Vce-40V to Vee. Ta = -20 to +15°e. if not specified.)
Item
Input "High"
Voltage
Input "Low"
Voltage

Symbol

Pin Name

0.1Vee

-

Vee+0.3

V

VIL

Vee-40

-

0.3Vee

V

-IOH = 15mA

Vee-3.O

-

-

V

-IOH = 10mA

Vee 2.0

-IOH =4mA

Vee- 1.O

-

V

-IOH =3mA

Vee-3.O

-IOH =2mA

Vee-2.O

-IOH -O.SmA

Vee-1.0

-

VOH

VOL

V

-

V
V

Vdisp = Vee-4OV

-

-

Vee-37

V

1

D4 - DI4
RO - R2

150kf! to Vee-4OV

-

-

Vee-37

V

2

Vin = Vec-40V to Vee

-

-

20

p.A

3

Vdisp = Vee-35V
Vin = Vee

125

250

600

p.A

4

IIILI

Pull Down MOS
Current

Id

D4 - DI4
RO - R2
RA1

Applied to 110 PinS with " with Pull·down MOS " selected by mask option.
Applied to I/O pins with "without Pull-down MOS (PMOS Open Drain)" selected by mask option.
Pull·down MOS current and output buffer current are excluded.
Applied to 110 pins with "with Pull-down MOS" selected by mask option.

126 HITACHI

V

D4
DI4
RO- R2

D4 - DI4
RO - R2
RA1

1)
2)
3)
4)

max

D4 - D 14 • R1
R2. RA1

Input/Output
Leakage
Current

(Note
(Note
(Note
(Note

typ

D4 - D14 • R1
R2. RA1

RO- R2

Output "Low"
Voltage

min

VIH

D4 - DI4
Output "High"
Voltage

Value

Test Conditions

(4) AC characteristics (VCC

=4.SV to 6V, GND s
Symbol

Item

OV, Vdisp =VCC-40V to VCC, Ta
Pin Name

Test
Conditions

OSC"OSC 2

divide·by·4

= -20 to +7SoC, if not specified.)
Value

min

typ

max

0.2

4

4.5

1

20

!lS

-

-

20

ms

1

divide·by·4

92

-

-

ns

2

d ivide·by·4

92

-

-

ns

2

-

-

20

ns

2

-

20

ns

2

3

tcyc

3

teyc

3

INT,

2

-

teye

3

RESET

2

-

-

teye

2

-

tcye

4

-

-

15

pF

-

-

20

ms

lose

Instruction Cycle Time

tcyc

Oscillator Stabilization Time

tRC

OSC"OSC 2

External Clock "High"
Level Width

tCPH

OSC,

External Clock" Low"
Level Width

tCPL

OSC,

Externel Clock Rise Time

tCPr

asc,

External Clock Fall Time

tCPf

OSC,

INTo "High" Level Width

tlOH

INTo

2

INTo "Low" Level Width

tlOL

INTo

2

INT, "High" Level Width

tllH

INT,

iNTI "Low" Level Width

til L

RESET "High" Level Width

tRSTH
Cin

RESET Fall Time

tRST!

Note

0.89

Oscillation Frequency

Input Capacitance

Unit

1= lMHz
Vin = OV

all pins

MHz

4

(Note 11 Oscillator stabilization time is the time until the oscillator stabilizes after Vee reaches 4.SV at "Power-on", or after RESET input level goes
to "High" by resetting to quit the stop mode by MCU reset on the circuit below. At power-on or stop mode release, equal or more than
tRC is required for RESET input to reserve oscillation stabilization time. When using crystal or ceramic filter oscillator. please ask a crystal
oscillator maker's or ceramic filter maker's advice because oscillator stabilization time depends on the circuit constant and stray capacity.

(Note 2)

asc,

OSC,
GND
Crystal: 4.194304MHz
NC·18C (Nihon Denpa Kogyo)
Rf = 1 [Mnl ± 20%,
C, = C, = 22 [pFl ± 20%

(Note 3)
INT"INT,

(Note

4)

RESET

;;f 1
o8VCC
0.2VCC

tRSTH

~

-:t--R--S--Tf-:------

GND
Ceramic filter: CSA4.00MG (Murata)
Rf = 1 [Mnl ± 20%,
C, = C, = 30 [pFl ± 20%

HITACHI 127

HMCS412 Characteristics Curve (Reference Data)

7

-<

2. 5

5

e

-<
fosc=4!1Hz, I-divide-by-41

,.,- / '

.....

e

folJz1=

5

fosc=4MHz, _I
divide-by-8,_
fosc=4MHz, I
diVlide-iY-li-

.... ~ :::;:-

2. 0

. / divide-by-4 _

,.,-

~

0

..;::: ~

o. 5

I I

o

4

6

Filter Oscillator)

Filter Oscillator)

600

".

....

100

,.,- V

I

V

-I-:::c:

o

4

I
max-

/

"j~
~
mil

6

7

Vee (V)

-Ip vs VCC Characteristics

128 HITACHI

8

I

ISBY vs VCC Characteristics (Crystal,Ceramic

Icc vs Vee Characteristics (Crystal,Ceramic

-<

7

Vee (V)

Vee (V)

200

fosc=4MHz, I
divide-by-8
fosc=4MHz,T
divide-by-16

500

-<

".

....

7

400
300
200
100

lax

V

-'
I

~yp

fj

min

I

V
o

10

20

80

40

50

60

70

( Vee - V dl , . ) (V)

Id vs(VCC-Vdisp) Characteristics

J Jv t 1vl
CC

5.0

CC

1I

I

'jVee=j5V

/'/ V

Vee =35V

4.0

v~VII

«

E 3.0

c

E
..1

o

2.0

1.0

4. 0

tl, V

~ V1

~~

tv

....-...--

02 0.4

0.6 08

~

1.0

V

1.2

V V

0

v

1. 0

1.<

1.6

V

V

Vee =2.5V

~

V

0

~

~~~

1.8 2.0

02 0.4

VOL (V)
10L min vs VOL Characteristics

~~

./

./

V

./

~ t:::

~ ...--V

Vee =6 I -

V
V

...--V

06 0.8

/

I--

1.0 1.2

4.5

Vee Fa.5 v _

...--./'

Vee =5
Vee

Vee

2.5

~

1.4 1.6

1.8

2.0 2.2

2.4

Vee-VOH (V)
-lOH min vs(VCC-VOH) Characteristics

(Standard Pin)

(Standard Pin)

:;;:

:;;:

-.5
.§

E

1
5
7

Vee-Vou (V)
-lOH min vs (VCC-VOH) Characteristics
(D4-D5 Pins)

Vee-VOM (V)
-lOH min vs (YCC-YOH) Characteristics

(RO-R2 Pins)

HITACHI 129

5.15 HMCS4l4C Electrical Characteristics
(1) De characteristics (Vee = 3.5V to 6V, GND = OV, Vdisp = Vee-40V to Vee, Ta = -20 to +75°e, if not specified.)
Item

Input "High"
Voltage

Symbol

Pin Name

Test Conditions

RESET,
R32/~'
R33/INT,

VIH

VIL

max

0.8VCC

-

VCC+0.3

V

Note

Vee-O.S

-

Vec+0.3

V

-0.3

-

0.2Vee

V

OSC,

-0.3

-

O.S

V

-

-

1

p.A

1

VCC - SV, fose - 4MHz
divide·by-8

-

-

1.8

mA

2,S

Vce - SV, fose - 2MHz
divide-by-4

-

-

1.8

mA

2,S

Vce = SV, fose
divide-by-8

= 4MHz

-

-

1.0

mA

3,S

Vee - SV, fose - 4MHz
divide-by-4

-

-

1.0

mA

3, S

Vin (TEST) = Vee-0.3V to Vee
Vee, Vin (RESET) = 0 to 0.3V

-

-

10

p.A

4

2

-

-

V

Input/Output
Leakage Current

IIILI

RESET,
R32 /f'I',j"fo,
R33/~,OSel

Current
Dissipation in
Active Mode

ICC

Vec

Current
Dissipation in
Standby Mode

ISBY

Current
Dissipation in
Stop Mode

Istop

Vee

Stop Mode
Retain Voltage

Vstop

Vee

Vee

Vin

= OV to Vee

INote 11 Pull-up MOS current and output buffer current are excluded.
INot.21 The MCU is in the reset state. The input/output current does not flow.
Test Conditions:
MCU state;
• Reset state in Operation Mode
Pin state;
• RESET, TEST ,.. Vee voltage
.0 0

-

0 3 , A3 - R4 ... Vee voltage

.0, - 0". RD -

R2, RAl ... Vdisp voltage

INote 31 The timer/counter operate with the fastest clock and input/output current does not tIOW.
Test Conditions:
MCU state-;
• StandbY,Mode
• Input/Output; Reset state
Pin state;
• RESET .. , GND voltage
• TEST ." Vee voltage
• Do - 0 3 , R3 - R4 ...

Vee voltage

.0, - 0 ... RO - R2, RA 1 .. _Vdisp voltage
INote41 PUllwdown MOS current is excluded.
INot.51 When fosc '" x [MHz}, the Current Dissipation in Operation mode and Standby mode are estimated as follows:
max. value (fosc '" x(MHz)

130 HITACHI

Unit

typ

RESET,
R32/INT 0,
R33/~

OSC,
Input "Low"
Voltage

Value

min

=tx max. value (fosc

::C

4(MHz] I

(2) Input/output characteristics for standard pin
(Vee = 3.5V to 6V, GND = OV, Vdisp = Vee-40V to Vee, Ta = -20 to +75°e, if not specified.)
Item

Pin Name

Symbol

Value

Test Conditions
min

typ

max

Unit

Input "High"
Voltage

VIH

Do - D" R,o,
R31 , R4

0.7Vee

-

Vee+0.3

V

Input "Low"
Voltage

VIL

Do - D" R,o,
R 31 , R4

-0.3

-

0.3Vee

V

Output "High"
Voltage

VOH

Note

Do - D,. R,o,
R31 , R4

-IOH = 1.0mA

Vee-1.O

-

-

V

1

Do - D" R,o,
R31 , R4

-IOH =O.SmA

Vee-O.S

-

-

V

1

IOL = 1.6mA

-

-

0.4

V

Output Low"
Voltage

VOL

Do - D" R,o,
R 31 , R4

Input/Output
Leakage Current

IIILI

Do - D" R,o,
R31 , R4

Yin = OV to Vee

-

-

1

p.A

2

-Ip

Do - D" R,o.
R 31 , R4

Vee = SV
Yin = OV

30

60

1S0

p.A

3

Unit

Note

II

Pull·Up MOS
Current

..

..

(Note 1) Applied to 1/0 pms with CMOS Output selected by mask option .
(Note 2) Pull-up MOS current and output buffer current are excluded.
(Note 31 Applied to I/O pins with "with Pull-up MOS" selected by mask option.

(3) Input/output characteristics for high voltage pin
(Vee =3 5V to 6V GND =OV Vdisp = Vee-40V to Vee Ta
Item

Symbol

Pin Name

=-20 to +7soe

if not specified.)
Value

Test Conditions
min

Input "High"
Voltage
Input "Low"
Voltage

VIH

D4 - D'4, R1
R2, RA1

0.7Vee

VIL

D4 - D'4, R1
R2, RA1

Vee-4O

Output "High"
Voltage

VOH

= 1SmA, Vee = SV ± 20%

Vee-3.O
Vee-2.O

-IOH = 4mA

Vee- 1.O

-IOH - 3mA, Vee = SV ± 20%

Vee-3.O

-

=2mA, Vee = SV ± 20%

Vee-2.O

-

Vee- 1.O

-

max
Vee+0.3

V

0.3Vee

V

-

V

-

V

-

V

-

V
V

-

-

-

Vee-37

V

1

RO- R2

-IOH

D4 - D'4
RO- R2

Vdisp

D4 - D'4
RO- R2

1S0kn to Vee-4OV

-

-

Vee-37

V

2

-

-

20

p.A

3

12S

2S0

600

p.A

4

-IOH =O.BmA
Output "Low"
Voltage

-

-IOH = 10mA, Vee = SV ± 20%

-IOH
D4 - D'4

typ

=Vee-4OV

V

VOL

Input/Output
Leakage
Current

IIILI

D4 - D'4
RO- R2
RA1

Yin = Vee-40V to Vee

Pull Down MOS
Current

Id

D4 - D'4
RO - R2
RA1

Vdisp = Vee-3SV
Yin =Vee

(Note 1) Applied to 1/0 pms with "wIth Pull-down MOS" selected by mask option.

(Note 2) Applied to 110 pins with "without Pull-down MOS (PMOS Open Drain)" selected by mask option.
(Note 3) PuJl-down MOS current and output buffer current are excluded.
(Note 4) Applied to 1/0 pins with "with Pull-down MOS" selected by mask oPtion.

HITACHI 131

(41 AC characteristics (Vee· 3.5"

lO

6V, GND a OV, Vdisp = Vee-4DV to Vee, Ta - -20 to +7&°C, if not opecified.1 .

Symbol

Item
Oscill.tion Frequency

tosc

Instruction Cycle Time

tcyc

Oscill~tor

tRC

Stabilization Time

External Clock "High"
Level Width

Pin Name
OSC, , OSC,

Value

Test
Conditions

min

divide·by.s

0.4

4

4.5

MHz

divide·by4

0.2

2

2.25

MHz

1.78

2

20

Its

20

ms

1

-

-

ns

2

-

ns

2

-

-

ns

2

-

OSC, ,'OSC,
OSC,

tCPH

divide·by.s

92

divide-by4

203

divide-by·8

92

divide-by-4

203

External Clock "Low"
Level Width

tCPL

OSC,

External Clock Rise Time

tCPr

OSC,

External Clock Fall Time

tCPf

OSC,

-

iN'i';; "High"

Level Width

tlOH

TNr.

2

iNIo "Low" Level Width

tlOL

INTo

2

iN!, "High" Level Width

tl1H
tl1 L

iN!,
TNI,

2

INT, "Low" Level Width
RESET "High" Level Width

tRSTH

RESET

2

Input Capacitance

Cin

RESET Fall Time

tRSTf

typ

2

-

t = 1MHz
Vin=OV

all pins

-

-

max

Unit

Nota

ns

2

20

ns

2

-

20

ns

2

-

tcyc

3

tcyc

3

tcyc

3

tcyc

3

-

-

tcyc

4

16

pF

20

ms

-

4

(Note 1) Oscillator stabilization time is the time until the oscillator stabllizet after Vee reaches 3.5V at "Power~n". or after RESET input lavelgoes
to "High'~ by resetting to quit the stop mode bV MCU reset on the circuit below. At power-on or ..top mode rei .... aqual or more than
tRC is requi.red for RESET "input to reserve oscillation stabilization time. When ullng crystal or ceramic filter oscillator. pi .... alk I cryltlll
oscillator maker's or ceramic filter maker's advice because oscillator stabilization time depends on the circuit conltant and stray capacity.

(Note 2)

C.

L

OSC.

osc.
OSC.

tCPf

tcp,

GND

Crystel: 4.194304MHz
NC·18C (Nihon Denpa Kogyo)
Rf = 1 [Mill ± 20%, C. = C. = 22 [pFI ± 20%

OSC.

(Note 3)
INT., INT.

(Note 4)
RESET

OSC.

Ceramic filter:CSA 4.00MG (Murata)
Rf· 1 [Mill ± 20%, C•• C, = 30 [pFI ± 20%

132HITACH.

;;f
.8VCC
O.2VCC

1

tRSTH

~tR-S-Tf----

5.16 HMCS414CL Electrical Characteristics
(1) De characteristics (Vee = 2.5V to 6V, GND = OV, Vdisp = Vee-40V to Vee, Ta = -20 to +75°e, if not specified.)
Item

Input "High"
Voltage

Symbol

Pin Name

Test Conditions

RESSL.-.
R,,/INTo,
R,,/lN'F;"

VIH

OSC,

Value

R,,/~,

VIL

max

0.8VCC

-

VCC+0.3

V

Vcc-0.5

-

Vec+0.3

V

-0.3

-

0.2Vcc

V

-0.3

-

0.3

V

-

-

1

p.A

1

R,,/INT,
OSC,

Input/Output
Leakage Current
Current
Dissipation in
Active Mode

Current
Dissipation in
Standby Mode

Note

typ

RESET,
Input "Low"
Voltage

Unit

min

RESET,
R,,/~,

IIILI

Vin

=OV to VCC

R"/INT,,OSC,

Ice

Vec

ISBY

Vee

Current
Dissipation in
Stop Mode

I stop

Vce

Stop Mode
Retain Voltage

V stop

Vce

VCC = 3V, fose
divide·by·16

=4MHz

-

-

0.8

mA

2,5

Vec = 3V, fose
divide·by·8

= 2MHz

-

-

0.8

mA

2,5

VCC = 3V, fose
divide·by·16

=4MHz

-

-

0.5

mA

3,5

Vec =3V, fose
divide·by·8

=2MHz

-

-

0.5

mA

3,5

-

-

10

p.A

4

2

-

-

V

Vin (TEST) = VCC-0.3V to Vee
Vec, Vin (RESET) =0 to 0.3V

(Note 1) Pull·up MOS current and output buffer current are excluded.
(Not. 2) The MCU is in the reset state. The input/output current does not flow.

Test Conditions:

MCU state;

_ Reset state in Operation Mode

Pin state;

• RESET, TEST ...
• Do -

°

3 ,

Vee voltage
Vee voltage

R3 - R4 •..

• 0, - OW RO - R2, RAI ... Vdisp voltage
(Note 3) The timer/counter operate with the fastest clock and input/output current does not flow.

Test Conditions:

MCU state;

Pin state;

•
•
•
•

Standby Mode
Input/Output; Reset state
RESET ... GND voltage
TEST ... Vee voltage

.0 0

.

-

03' R3 - R4 ... VccvoltaAE!

• O. - D.. , RO - R2, RA 1 ... Vdisp voltage

(Note 4) Pull-down MOS current is excluded.
(Note 5) When fosc:: x{MHz], the Current Dissipation in Operation mode and Standby mode are estimated as follows:
max. value (fosc '" x[MHzj)

"'1' x max. value (fosc '" 4(MHz1)

HITACHI 133

(2) Input/output characteristics for standard pin
(Vee 2.5V to 6V. GND OV. Vdisp Vee-40V to Vee. Ta

=

Item

=

Symbol

=

Pin Name

=-20 to +75°e. if not specified.)

Test Conditions

Value

min

typ

max

Unit

Note

Input "High"
Voltage

VIH

Do - D,. R,o.
R31 • R4

0.7Vee

-

Vee+0.3

V

Input "Low"
Voltage

VIL

Do - D,. R,o.
R". R4

-0.3

-

0.3Vee

V

Output "High"
Voltage

VOH

Do - D,. R,o.
R31 • R4

-IOH =0.3mA

Vee-O.S

-

-

V

Output" Low"
Voltage

VOL

Do - D" R,o,
R31 , R4

IOL =0.4mA

-

-

0.4

V

Input/Output
Leakage Current

IIILI

Do - D" R,o,
R31 , R4

Yin = OV to Vee

-

-

1

p.A

2

Pull·Up MOS
Current

-Ip

Do - D" R,o,
R 31 , R4

..

1

Vee = 3V, Yin = OV

3

15

SO

p.A

3

Vee = SV, Yin = OV

30

60

lS0

p.A

3

Unit

Note

(Note 1) Applied to I/O pms with I CMOS Output selected by mask option .
(Note 2) Pull-up MOS current and output buffer current are excluded.
(Note 3) Applied to 1/0 pins with "with Pull-up MOS" selected by mask option.

(3) Input/output characteristics for high voltage pin
(Vee = 2.5V to 6V GND OV Vdisp Vee-40V to Vee Ta

=

Item
Input "High"
Voltage
Input "Low"
Voltage

Symbol

=

Pin Name

Test Conditions

Value
min

typ

max

D4 - D14 , Rl
R2, RAl

0.7Vee

-

Vee+0.3

V

VIL

D4 - D14 , Rl
R2, RAl

Vee-4O

-

0.3Vee

V

VOH

RO - R2

Output "Low"
Voltage

if not specified.)

VIH

D4 - D14
Output "H igh"
Voltage

=-20 to +75°e

VOL

-IOH = 15mA, Vee = 5V ± 20%

Vee-3.O

-

-

V

-IOH = 10mA, Vee = 5V ± 20%

Vee-2.O

-

-

V

-IOH = 2.SmA

Vee-1.O

-

V

-IOH = 3mA, Vee - 5V ± 20%

Vee-3.O

-

-

-IOH = 2mA, Vee - 5V ± 20%

Vee-2.O

-

-

V

-IOH =O.SmA

Vee-1.0

-

-

V

D4 - D14
RO- R2

Vdisp = Vee-4OV

-

-

Vee-37

V

1

D4 - D14
RO - R2

150kf! to Vee-4OV

-

-

Vee-37

V

2

-

-

20

p.A

3

125

250

600

p.A

4

Input/Output
Leakage
Current

IIILI

D4 - D14
RO - R2
RAl

Yin = Vee-40V to Vee

Pull Down MOS
Current

Id

D4 - D14
RO - R2
RAl

Vdisp = Vee-3SV
Yin = Vee

.

.

INote 1) Applied to 1/0 PinS With With Pull..ctown MOS selected by mask option .
(Note 2) Applied to 1/0 pins with "without Pull·down MOS (PMOS Open Drain)" selected by mask option.
INote 3) Pull·down MOS current and output buffer current are excluded.

INote 4) Applied to I/O pins with "with Pull·down MOS" selected by mask option.

134 HITACHI

V

(4) Ae characteristics (Vee = 2.5V to 6V. GND =OV. Vdisp· Vce-40V to Vee. Ta = -20 to+75°e. if not specified.)
Item

Symbol

ascillation Frequency

fosc

Instruction Cycle Time

!eyc

ascillator Stabilization Time

tRC

External Clock "High"
Level Width

Pin Name

asc,.asc,

Test
Conditions

asc,

Unit

Note

typ

divide·by·16

0.8

4

4.5

MHz

divide-by-8

0.4

2

2.25

MHz

3.55

4

20

IlS

-

60

ms

1

-

ns

2

-

ns

2

ns

2

max

divide·by·16

92

divide·by-8

203

divide·by·16

92

-

divide·by·B

203

-

-

ns

2
2

asc" asc,

tCPH

Value

min

External Clock "Low"
Level Width

tCPL

asc,

External Clock Rise Time

tCPr

asc,

-

-

20

ns

External Clock Fall Time

tCPf

asc,

-

20

ns

2

INTo "High" Level Width

tlOH

INTo

2

-

-

tcyc

3

INTo "Low" Level Width

tlOL

INTo

2

tcyc

3

tllH

INT,

2

-

-

INT, "High" Level Width

-

!eyc

3

INT, "Low" Level Width

tilL

INT,

2

-

-

tcyc

3

RESET "High" Level Width

tRSTH

RESET

2

-

-

tcyc

4

I nput Capacitance

Cin

all pins

-

-

15

pF

RESET Fall Time

tRSTf

-

-

15

ms

f = lMHz
Vin=OV

4

(Note 1) Oscillator stabilization time is the time until the oscillator stabilizes after Vee reaches 2.5V at "Power-on", or after RESET input level goes
to "High" by resetting to quit the stop mode by MCU reset on the circuit below. At power-on or stop mode release, equal or more than
tAC is required for RESET input to reserve oscillation stabilization time. When using crystal or ceramic filter oscillator. please ask a crystal

oscillator maker's or ceramic filter maker's advice because oscillator stabilization time depends on· the circuit constant and stray capacity.

1-9---1-1 ase,

....IVI~-I asc,

tCPr

tCPf

GNO
Crystal: 2.097152MHz
OS·MGO 308 (Soiko)
Rf = lMO ± 20%, Rd = 2.2kO ± 20%
C, = C, = 10pF ± 20%

ase,

(Note 3)
INT" INT,

(Note 4)
RESET

OSC,

tRSTf

Ceramic filter: CSA 2.000MK (Murata)
Rf = 1 [MOl ± 20%,
C, • C, = 30 [pFl ± 20%

HITACHI 1,35

5.17

HMCS414AC Electrical Characteristics'

(1) DC charaCteristics (Vee
Item

. Input "High"
VO.ltage

=4.5V to 6V, GND· OV, Vdisp =Vee-40Vto Vee. Ta. -20 to +75°e, if not specified.)
Pin Name

Symbol

Test Conditions

O.aVCC

-

VCC+0.3

V

VCC-O.S

-

VCC+0.3

V

R'2/~'

-0.3

-

0.2VCC

V

OSC,

-0.3

-

O.S

V

-

-

1

p.A

1

RESET,
VIL

Note

max

OSC,
Input "Low"
Voltage

Unit

typ

RESET,
.R32/~'
R. 3/INT,

VIH

Value
min,

Ru!l T,

RESET,

Input/Output
Leakage Current

IIILI

Current
Dissipation in
Active Mode

ICC

VCC

VCC = SV, fosc = 4MHz
divide·by-4

-

-

3.0

rnA

2, S

Dissipation in
Standby Mode

ISBY

VCC

VCC = SV, fosc = 4MHz
divide·by-4

-

-

1.4

rnA

3,S

Current
Dissipation in
Stop Mode

Istop

VCC

Vin (TEST) = VCC-0.3V to VCC
VCC, Vin (RESET) = 0 to 0.3V

-

-

10

p.A

4

Stop Mode
Retain Voltage

Vstop

VCC

2

-

-

V

R'2/~'

R33/IN

Current

I,

asc,

Vin

=OV to VCC

(Note 1) Pull·up MOS current and output buffer current are excluded.
(Note 2) The MCU is in the reset state. The input/output current does not flow.
Test Conditions:

MCU state;

Pin stete;

• Reset state in Operation Mode

• RESET, TEST ... Vee voltage
• D. - D" R3 - R4 ... Vee voltage
• D, - D.. , RO- R2, RA1 ... VdiSD voltage

(Nole3) The timer/coun,ter operate with the fastest clock and
Test Conditions:

MCU state:

inpu~/output

current does not flow.

• Standby Mode
• Input/Output; Reset state

Pin state;

• RESET ... GND vOltage
• 'i'ES'i" ... Vee voltage
• D. - D" R3 - R4 ... Vee vollage
(Nole4) Pull-down MOS currenl is eXClUded.· D, - D.. , RO - R2, RAl ... Vdisp voltage
(NOleS) When fosc ... x [MHz), the Current Dissipation in Operation mode and Standby mode are estimated as follows:
max. value (fose "" x(MHz]) =tx max. value (fose - 4 [Mt:tz] )

136 HITACHI

(21 Input/output characteristics for standard pin
(VCC - 4.5V to av. GND· OV. Vdisp· Vee-40V to Vcc. Ta· -20 to +75°C. if not spaciflecl.l
Item
Input "High"
Voltage

Symbol

Pin Name

Test Conditions

Value
min

typ

max

Unit

VIH

Do - 0,. R,o.
R3I • R4

0.7VCC

-

Vec+O·3

V

Input "Low"
Voltege

VIL

Do - 0,. R,o.
R3I • R4

-0.3

-

0.3Vce

V

Output "High"
Voltage

VOH

Note

Do - 0,. R,o.
R'I. R4

-IOH = 1.0mA

Vee- 1.O

-

-

V

1

Do - 0,. R,o.
R3I • R4

-IOH =0.5mA

Vce-O·5

-

-

V

1

0.4

V

1

J.lA

2

150

j.IA

3

Unit

Note

Output "Low"
Voltage

VOL

Do - 03, R, D ,
R'I. R4

IOL = 1.6mA

-

Input/Output
Leakage Current

IIILI

Do - 0,. R,o.
R'I. R4

Yin = OV to Vec

-

-

Pull·UpMOS
Current

-Ip

Do - 0,. R,o.
R'I. R4

Vee=5V
Vin=OV

30

60

(Note 1) Applied to I/O pms with "CMOS" Output selected by mask option.
(Note 2) Pull~up MOS current and output buffer current Bre excluded.
INote 31 Applied to 110 pin. with "with Pull·up MOS" selected by mesk option.

(31 Input/output characteristics for high voltega pin
'
(Vee· 4.5Vto av. GND -OV. Vdisp· Vee-40Vto Vcc. Ta. -20 to +75°C. if not spacified.1
Item

Symbol

Input "High"
Voltege

VIH

Input "Low"
Voltage

VIL

Pin Name

04

0 14 • R1

R2. RA1

04

-

0 14 • R1

-

0. 4

VOH

Input/Output
Leakage
Current

IIILI

Pull Down MOS
Current

Id

max

0.7Vee

-

VCC+0.3

V

Vec-40

-

0.3Vec

V

Vee-3.O

-

-

V

-IOH = 10mA

Vee-2.O
VCC-1.0

-'

V

-IOH=4mA
-IOH =3mA

Vce-3•O

-IOH =2mA

Vec-2.O

-IOH=O.8mA

Vec-1.0

-

V
V

RO- R2

Vdisp = Vce-4OV

-

04

150kU to VCC-40V

-

Yin = Vec-40V to Vee

-

-

20

J.lA

3

125

250

600

J.lA

4

04
VOL

typ

-

Ro - R,

Output "Low"
Voltage

Value
min

-IOH = 15mA

R2. RA1

04
Output "High"
Voltege

-

Test Conditions

-

0. 4

- D ••
RO- R2

04

-

0 1•

RO- R2
RA1

04

-

0 1,

RO-R2
RA1

..

Vdisp = Vec-35V
Vin = Vee

-

V

Vee-37

V

1

Vec-37

V

2

V

(Note 1) Applied to I/O pins with' with Pull-down MOS' selected by mask option .

INoto 21 Applied to 110 pins with "without Pull-down MOS IPMOS Open Drelnl" selected by mask option.
(Note 3) Pull-down MOS current and output buffer current are excluded,
(Note 4) Applied to I/O pins with "with Pull-down MOS" selected by mask option.

HITACHI 137

HMCS414 Characteristics Curve (Reference Data)

7

6

<

E

fosc-4MHz ,- I--

~

•

./

..- ~

2.5

. / divide-by-4 I--

I I

--- ~

;....--

fosc-4MHz "::"1-divide-by-8
fosc-4MHz ':-1-diVTde-~y-l~

fosc-4MHz t
ivide-by-4

<

E 2.0
./

./'

~ 1.0

....

V
/

-- V

0.5

~

fosc-4MHz,
divide-by-8 I-fosc-4MHz,

diVide-r-li-

---6

10

I I

7

10

Vee (V)

Vee (V)

ICC vs VCC Characteristics (Crystal, Ceramic

ISBY VB VCC Characteristics (Crystal, Ceramic

Filter Oscillation)

Filter Oscillator)

600

200

<

"

V
/'

mJ-

/

<

"

typI -

- ~t::: ~
.;

500

mil
6

7

Vee (V)
-Ip vs VCC Characteristics

400
800
200
100

lax

1/

/

r
I

yp
Jin

V

V

V

10

20

30

40

50

60

70

Vee-V dl , .

(V)

ld vs (VCC-Vdisp) Characteristics

HITACHI 139

L='sv
S.O

L~sv I
VcC"'UV

)/~ rl V

I I
, I

Vee=8SV

4.0

~

8. 0

.5

E
.. 2. 0

o

1. o

I.

~

/;,VV
hVV,J V
~

V
V V

no
u....

0.40

nA
.... u

<

, n

V

8.0

E

Vee =2.S

V V
V
L' V

V

·s
....o'"

2. 0

.... v

1.2

.1.4

.... 6

.

,.... 0

~

I

.0

V
~
~ V

0.2 0.4

V

V V

./'

0.6

0.8

1.0

VOL (V)

1.2

1.4

Vee=SV
./

Vcc4.5V

I ,

Vce ,=8T

V

-

1.6. 1.8

Vee-VOH

IOL min vs VOL Characteristics

V

r;:V

J...-~ I--VI--I--I -

~~~

Z.O

V

1/ . / ~

.:

V

nv.S

Vee=!L

4. 0

2.0

(V)

-IOH min vs (VCC-VOH) Characteristics

(Standard Pin)

(Standard Pin)

<

E

.:

c

·s
....'"

'il

....'0"

0

I

I

4

4

Vee-VOH (V)

Vee-VOH(V)
-IOH min vs (VCC-VOH) Characteristics
(D4 - D5 Pins)

140.HrrAcHl

Vcc=2.SV

-IOH min

vS

(VCC-VOH) Characteristics

(RO-R2 Pins)

6.

ASSEMBLY LANGUAGE

6.1

Symbols and Abbreviations
a ..... b

Tranfer from "a" to "b"

a-b
X

Exchange between

"1"

"High" level

"0"

IILowtt

Ita" and "b"

Logical negation (NOT)
level

LSB

Least Significant Bit

MSB

Most Significant Bit

NZ

Not Zero

NB
OVF

No Borrow
Overflow

n

AND

U

OR

J

(±)

Exclusive OR

#

Not Equal

S

$F

I Operation II
A+i-)A

DescriPtionl1
Adds the contents of Accumulator to 4 bit Immediate data (i3-0)
and stores the result in Accumulator.
Judges OVF simultaneously.

Address format and the number of execution cycles
Address format

Mnemonic

I
I

Operand
Instruction word
Number
format r---~~----r-~~--~~
First
I
Second
of words

I

$AI

I

Example

I
I

I

i

$28i

1

II

01830
01831
01832
01833
01834

148 HITACHI

190
28F
194

038
036

0620
0622
0623

Number.of
execut10n
cycles

*

SUBel

LAMD

AI
LMAD

*

$038
$F
$036

1

Compare Instruc tion

ALEI
ALEI

I

Format

(A Less or Equal to Immediate)

I

II

Status

II

NB
ALE I i

A > i

ST=O

A :;;; i

ST=l

I Operation II
A ;;; i

DescriPtionJ

I

Compares the contents of Accumulator to 4-bit Immediate data
(i 3"'0) .

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format

Instruction word
Second
First
I

I

ALEI

I

Example

01407
01408
01409
01410
01411

I
I

i

$2Bi

I
I

I

Number
of words

Number .of
execut~on
cycles

1

1

II
2F7
281
2B7
2F7

0476
0477
0476
0479

*
XMRA

$7

AI
ALE I

$I

XMRA

$7
$7

HITACHI 149

'Compare Instruction

ALEM
ALEM (A Less or Equal to Memory)

I

Format

II

I

II

Status

NB
ALEM

A

M

ST=O

A :;; M

ST=l

>

I Operation II
A :;; M

DescriPtionl1
Compares RAM addressed by W, X, and. Y registers to the contents
of Accumulator.

Address format and the number of execution cycles
Address format

ALEM

REGISTER

I

Example

I Operand
Mnemonic I format

Instruction word
First
I
Second

Number
of words

Number .of
execut~on
cycles

1

1

$014

II

01216
01217

150 HITACHI

014
1CE

03D7
03D8

ALEM
CAL

OS ERROR

Compare Instruction

ALEMD
ALEMD(A Less or Equal to Memory)

I

Format

Status

I

II

II

NB
ALEMD d

I

Operation

A

>

M

ST=O

A

~

M

ST=1

II
A

~

M (d)

DescriPtionl1
Compares RAM addressed by 10-bit direct address d9-0 to the
contents of Accumulator.

Address format and the number of execution cycles
Address format
DIRECT

I

Example

01218
01219

Mnemonic:
ALEMD

Operand
format

I
I
I

Instruction word
Second
First
I

Number
of words

Number.of
execution
cycles

I

d

$114

I
I

d

2

2

II
114 074
1CF

03D9
03DB

ALEMD
CAL

$074
OS ERROR

HITACHI 151

Arithmetic Instruction

AM
AM (Add A to Memory)

I

Format

Status

I

II

II

OVF
AM

I

Operation

M+ A

$F

ST=O

M + A > $F

ST=l

;£

II
M+A~A

DescriPtionl1
Adds RAM addressed by W, X, Y registers to the contents of
Accumulator and stores the result in Accumulator.
Judges OVF.
(Note)

When executing subtraction, execute AM after taking
complement of Accumulator with NEGA. (M-A-A)

Address format and the number of execution cycles
Address format
REGISTER

I

Example

. : Operand

Mnemon~c, format

AM

Instruction word
First
I
Second
$008

II

00949
00950
00951
00952

152 HITACHI

093
008
097

02FE
02FF
0300

*

KIARTHM6

LAMXY
AM

LMAXY

Number
of words

~~~g~Lg~

1

1

cycles

Arithmetic Instruction

AMD
AMD (Add A to Memory)

I

Format

II

Status

I

II

OVF
AMI)

d

M + A :;; $F

ST=O

M + A > $F

ST=l

I Operation II
M(d) + A-A

DescriPtionl1
Adds RAM addressed by 10-bit direct address dg-O to the contents
of Accumulator and stores the result in Accumulator.
Judges OVF.
(note) Subtraction

(M-A~A)

is the same as AM.

Address format and the number of execution cycles
Address format
DIRECT

I

Example

00935
00936
00937
00938
00939
00940

Mnemonic

I
I

Operand
format

$108

d

AMI)

Instruction word
First
I
Second
d

Number
of words

Number ,of

2

2

execut~on

cycles

II
190 06C
001
108 04C
051

02FO
02F2
02F3
02F5

*

KIARTHM4

LAMD
XSPY
AMD
LMAIYX

$06C
$04C

*

HITACHI 153

Arithmetic Instruction

AMC
AMC (Add A to Memory with Carry)

I

I

Format

1/

Status

1/
OVF

AMC

I

Operation

M+ A + CA ;;; $F

ST=O

M + A + CA > $F

ST=l

II
M + A + CA-4A
OVF-4 CA

DescriPtionl1
Adds RAM addressed by W, X, Y registers, the contents of Accumulator,
and those of Carry Flag, and stores the result in Accumulator.
Latches OVF into CA and judges it.
(Example)
(Initial contents)
after executing AMC
after re-executine AMC

M
8
8
8

A
9
1
10

CA
0
1
0

S
0
1
0

Address format and the number of execution cycles
Address format
REGISTER

I

Operand
Mnemonic: format
I

AMC

Instruction word
Second
First
I

Number
of words

Number .of
execut~on
cycles

I
I
I

1

1

$018

I
I

Example

1/

01165
01166
01167
01168
01169

154 HITACHI

235
OEF
018
ICE

03A9
03AA
03AB
03AC

*

LA!

$5

SEC
AMC
CAL

OSERROR

;A=5
;CA=l
;A=M(WXY)+A+CA

Arithmetic Instruction

AMCD
AMCD (Add A to Memory with Carry)

I

Format

II

I

Status

OVF

AMCD d

I

Operation

I~

M + A + CA :;; $F

ST=O

M + A + CA > $F

ST=1

11
M(d) + A + CA -4A
OVF-4CA

DescriPtionl]
Adds RAM addressed by 10-bit direct address d9-0. the contents
of Accumulator. and those of CA. and stores the result in
Accumulator.
Latches OVF into CA and judges it simultaneously.

Address format and the number of execution cycles
Address format
DIRECT

I

Example

00905
00906
00907
00908

Operand
Mnemonic: format
AMCD

I
I
I

Instruction word
First
I
Second

Number
of words

Number.of
execut10n
cycles

2

2

I

d

$118

:

d

I]

091
118 043
OA6

02D2
02D3
02D5

*
LAMX

AMCD

$043

DAA

HITACHI 155

Compare Ins true tion

ANEM
ANEM (A Not Equal to Memory)

I

Format

II

Status

II

NZ

ANEM

I

Operation

A = M

ST=O

A~M

ST=l

II
A~M

DescriPtionl1
Compares RAM addressed by W, X, Y registers to the contents of
Accumulator.

Address format and the number of execution cycles
Address format
REGISTER

I

Example

Operand
Mnemonic: format
ANEM

I

Instruction word
Second
First
I

Number
of words

Number .of
executlon
cycles

I
I
I

1

1

$004

I
I

II

01195
01196
01197

156 HITACHI

004
lCE

03C6
03C7

*

; IF M(WXY) /=ACC

ANEM
CAL

OSERROR

Compare Instruction

ANEMO
ANEMO (A Not Equal to Memory)

I

Format

I

II

Status

II

NZ
ANEMD d

I

Operation

A = M

ST=O

A!o;:M

ST=l

II
A~

M(d)

DescriPtionl1
Compares RAM addressed by 10-bit direct dg-O to Accumulator.

Address format and the number of execution cycles
Address format
DIRECT

Operand
Mnemonic: format
ANEMD

I
I

d

$104

I

I

Example

01729
01730
01731
01732

Instruction word
Second
First
I
I
I

I

d

Number
of words
2

Number.of
executlon
cycles
2

II
190 036
104 038
171 235

05A4
05A6
05A8

*

LAMD

ANEMD
BRL

$036
$038
SUBD

HITACHI 157

Arithmetic Instruction

ANM
ANM (AND Memory with A)

I

Format

II

I

Status

II

NZ
ANM

I

Operation

AnM=O

ST=O

An Ml<0

ST=l

II

DescriPtionl1
ANDs the contents of Accumulator and RAM addressed by W, X, Y
registers, and stores the result in Accumulator.

Address format and the number of execution cycles
Address format
REGISTER

I

Example

I Operand
Instruction word
Number
Mnemonic I format I--:::-:·,..:..;--'...:....;-r-...:.:...,S:----'""'d:---I
of words
Flrst
I
econ
ANM
1
$09C

II

00925
00926
00927
00928

158 HITACHI

091
0ge

051

02E5
02E6
02E7

LAMX

ANM
LMAIYX

*

Number.of
executlon
cycles
1

Arithmetic Instruc tion

ANMD
ANMD

I

(AND Memory with A)

I

Format

11

Status

II

NZ
ANMD d

AnM=O

ST=O

AnM~O

ST=l

I Operation II
An M(d)

-->

A

DescriPtionl1

ANDs the contents of Accumulator and RAM addressed by 10-bi t
direct address, and stores the result in Accumulator.

Address format and the number of execution cycles
Address format
DIRECT

I

Example

01009
01010
01011

Operand
Mnemonic: format

Instruction word
First
Second
I

I
I

Number.of
execut10n
cycles

2

2

I

I

ANMD

Number
of words

d

$19C

I
I

d

II
OAF
19C 02C
326

0330
0331
0333

LAY
ANMD

BR

$02C
KIINPUT1

HITACHI 159

RAM Address Instruc tion

AYY
AYY

I

Format

II

(Add A to y)

I

Status

II

OVF
AYY

I

Operation

Y + A ;;;; $F

ST=O

Y + A

ST=l

>

$F

II
Y +

A~Y

DescriPtionl1
Adds the contents of Y register to those of Accumulator and stores
the result in Y register.
Judges OVF.

Address format and the number of execution cycles
Operand
Mnemonic: format

Address format

AYY

I

Example

Instruction word
Second
First
I

Number
of words

Number.of
executlon
cycles

1

1

I

I

I
I

$054

I
I

II

01160
01161
01162
01163

160 HITACHI

ODF
054
ICE

03A5
03A6
03A7

DY
AYY
CAL

*

;Y=Y-l
;Y=Y+A
OS ERROR

Compare Ins true tion

BLEM
BLEM (B Less or Equal to Memory)

I

Format

Status

II

NB

BLEM

I

Operation

II

B > M

ST=O

B ::; M

ST=l

II
B ::; M

DescriPtionl1

Compares RAM addressed by W, X, Y registers to the contents of
B register.

Address format and the number of execution cycles
Address format

Example

01220
01221
01222

Instruction word
First
I
Second
$OC4

BLEM

REGISTER

I

, Operand
Mnemonic, format

,
,,

Number
of words

Number.of
executl.on
cycles

1

1

II

OC4
ICE

03DC
03DD

*

BLEM
CAL

OSERROR

HITACHI 161

Compare Ins true tion

BNEM
BNEM

I

Format

(B Not Equal to Memory)

I

II

Status

II

NZ
BNEM

I

Operation

B=M

ST=O

BIfM

ST=l

IJ
B~M

DescriPtionl1
Compares RAM addressed by W, X,

y

registers to the contents of

B register,

Address format and the number of execution cycles
Address format
REGISTER

I

Example

Operand
Mnemonic: format
BNEM

I
I
I

Instruction word
Second
First
I

Number
of words

Number ,of
executl.on
cycles

I
I
I

1

1

$044

II

01201
01202

162 HITACHI

044
ICE

03CB
03CC

BNEM
CAL

OS ERROR

lIF M(WXY)

/=B

ROM Address Instruction

BR
BR

I

Format

(Branch on Status

II

1)

II

Status
1

BR b

Set to 1 irrespectively of whether
BR is executed or skipped. (ST=l)

I

Operation

II

Conditional jump to an address
in the current page (256 words).

DescriPtionl1
Branches to the specified address if ST=l.
If ST=O, this instruction is skipped (takes one cycle time).
(Note) When BR is used at the last address in the page, this
instruction is executed in the next page because PC is
incremented automatically.
Address format and the number of execution cycles
Address format
DIRECT (8 bits)

I

Example
01445
01446
01447
01448
01449
01450
01451
01452
01453
01454
01455
01456

Operand
Mnemonic: format
BR

I

b

I
I

Instruction word
Second
First
I
~1l-b7b6b5b4:
b 3 b 2 b 1 b ol

Number.of
execut10n
cycles

1

1

.

II
2FE
OAF
2B3
3AO
2B7
3A4
2BB
3A8
000
3AC

Number
of words

0496
0497
0498
0499
049A
049B
049C
0490
049E
049F

*

XMRA

LAY
ALEI
BR

ALE I
BR

ALEI
BR

$E
$3
KITIMEO
$7
KITIME1
$B
KITIME2

;IF A=0,1,2,3
;IF A=4,5,6,7
;IF A=8,9,$A,$B

NOP
BR

KITIME3

;IF A=$C, $0, $E, $F

*

HITACHI 163

ROM Address Instruction

BRL
BRL(Long Branch on Status 1)

I

Format

II

Status

II

1

BRL u

Set to 1 irrespectively of whether
BRL is executed or skipped. (ST=l)

I

Operation

II

Conditional jump to any ROM
address space.

DescriPtionl1
P3~O,

If ST=l, jumps to the address specified by

dg-O'

If ST=O, BRL is skipped.
Takes 2-cyc1e time irrespective of execution and skip.

Address format and the number of execution cycles

I

Address format

Mnemonic

DIRECT

BRL

Example

I
I

Operand
format

Instruction word
First
Second
$17p

u

d

Number
of words

Number.of
executlon
cycles

2

2

II

01883
01884
01885

164 HITACHI

l8C 002
171 256
171 24F

0650
0652
0654

TMD
BRL

BRL

$0,$002
TBINTR
TLOOP1

IF ST-l
THEN JUMP TO TBINTR
OTHERWISE JUMP TO TLOOP1

ROM Address Instruction

CAL
CAL (Subroutine Jump on Status 1)

I

Format

II

Status

II

1

CAL a

Set to 1 irrespectively of whether
CAL is executed or skipped.

I

Operation

(ST=l)

II

Conditional subroutine jump to the
address specified by

a5~0

in

subroutine space.

I

DescriPtion]

If ST=l, performs subroutine jump to the specified address.
If ST=O, this instruction is skipped.
Takes l-cycle time to the skipped.
Subroutine space means 0 to 64 pages.
All bits of PC is saved on RAM.
Address format and the number of execution cycles
Address format

I Operand
Mnemonic I format

DIRECT (6 bits)

I

Example

CAL

a

Instruction word
First
I
Second

Number
of words

%01-lla5a~a3:
a 2 a 1 a ol

1

Number ,of
executl0n
cycles
2/1 (Skip)

II

00510
00511

laE 000
ICE

01A3
OlAS

TMD
CAL

2,$000
OS ERROR

;IFO
;IF ST=l

HITACHI 165

No.

I

19

I

I

ROM Address Instruction

I

CALL

CALL (Long Subroutine Jump on Status 1)

I

Format

I

II

Status

II

1
CALL u

Set to 1 irrespectively of whether
CALL is executed or skipped. (ST=!)

I

Operation

IJ

Conditional subroutine jump to
any ROM address space.

DescriPtionl1
If ST=l. performs subroutine jump to the specified address (P3-0. d9-0).
If ST=O, this instruction is skipped.

Takes 2-cycle time to be skipped.

Address format and the number of execution cycles
Address format
DIRECT

Operand
Mnemonic: format
CALL

I
, I

u

Instruction word
Second
First
I

Number
of words

I
I
I

2

$16p

I

I

Example

d

Number.of
executlon
cycles
2

II

00781
00782
00783
00784
00785

166 HITACHI

28F
OE8
160 28E

0276
0277
0278

*

KIRAM5

*

AI

$F

LXA
CALL

KIRAMS

;A=A+F
;X=A

Arithmetic Instruction

COMB
COMB (Complement B)

I

Format

I

II

Status

1/
No effect

COMB

I

Operation

II
B~B

DescriPtionl1
Stores l'S complement of the contents of B register in B register.
(Example)
B (result)

B
1

1

I I 1--1

1

1

1

1

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
COMB

I

I

Instruction word
Second
First
I

Number
of words

Number.of
execut10n
cycles

I
I

1

1

$140

I
I

I

Example
1/

00815
00816
00817
00818
00819
00820

048
008
076
140
010

0294
0295
0296
0297
0298

*

KlRAMC

LAB

LYA
YNEI
COMB

$6

;Y=B
;Y/=6
;B~B

RTN

HITACHI 167

Arithmetic Instruction"

DAA
DAA (Decimal Adjust for Addition)

I

Format

I

II

Status

No effect

DAA

I

Operation

II

II
Decimal adjust for addition

DescriPtionl1
If A <: 10 or CA=l, A+6-+A and l-+CA.
If A < 10 and CA=O, the contents of A and CA are unchanged.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
DAA

I

Example

I

Instruction word
Second
First
I
$OA6

I
I

I
I
I

II

00898
00899
00900
00901

168 HITACHI

091
018
OAG

02CC
02CD
02CE

*

KIARTHM1

LAMX

AMC
DM

Number
of words

Number .of
executlon
cycles

1

1

Arithmetic Instruction

DAS
DAS (Decimal Adjust for Subtraction)

I

Format

II

Status

II

No effect
DAS

I

Operation

II
Decimal adjust for
subtraction

DescriPtionl1
If A

~

10 or CA=O, A+lO-+A and O-+CA.

If A < 10 and CA=l, the contents of A and CA are unchanged.

Address format and the number of execution cycles
Address format

, Operand
Mnemonic, format
DAS

I

Example

00914
00915
00916
00917
00918

,,

Instruction word
First
I
Second
$OAA

Number
of words

Number ,of
execut~on
cycles

1

1

II
091
098

OM
051

02DC
02DD
02DE
02DF

*

KIARTHM2

LAMX

SMC
DAS
LMAIYX

HITACHI 169

Arithmetic Instruction

DB
DB (Decrement B)

I

Format

I

II

Status

II

NB
DB

I

Operation

B- 1 < 0

ST=O

B- 1

ST=l

~

0

II
B-

l~B

I

DescriPtio~

Decrements the contents of B register.
Judges NB.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
DB

I

Example

Instruction word
Second
First
I

Number
of words

Number .. of
execut10n
cycles

1

1

I

I

$OCF

I
I

I

I

II

01145
01146
01147

170 HITACHI

OCF
ICE

DB
CAL

0399
039A

*

;B=B-l
OS ERROR

RAM Address Instruction

DY
DY

I

Format

(Decrement y)

I

II

Status

II

NB
DY

I

Operation

< 0

ST=O

Y - 1 ;;: 0

ST=l

Y - 1

II
Y-l-->Y

DescriPtionl1
Decrements the contents of Y register.
Judges NB.

I

Address format and the number of execution cycles
Address format

Mnemonic:
DY

I

Example

00744
00745
00746
00747
00748

Operand
format

Instruction word
Second
First
I

Number
of words

Number ,of

1

1

execut~on

cycles

I

I

$ODF

I
I

I
I

II
ODF
064
05C

025E
025F
0260

*

DY
RED
IY

*

HITACHI 171

Arithmetic Instruction

EORM
EORM (EOR Memory with A)

I

Format

II

I

Status

II

NZ
EORM

I

Operation

A=O

ST=O

A?;;.O

ST=l

II

DescriPtionl1
Performs the logical exclusive "OR"-operation between the contents
of Accumulator and those of RAM addressed by W, X, Y registers.

Address format and the number of execution cycles
Address format
REGISTER

I

Example

, Operand
Instruction word
Number
Mnemonic, format r-~~'~----'-~S~--~d~'
of words
Flrst
,
econ
EORM

I

'

,'

$OlC:

II

00921
00922
00923
00924

172 HITACHI

091
Ole
051

02E2
02E3
02E4

Number ,of
executlon
cycles

*

KIARTHM3

LAMX

EORM
LMAIYX

1

1

Arithmetic Instruction

EORMD
EORMD (EOR Memory with A)

I

Format

Status

II

NZ

EORM!) d

I Operation

IJ

A=O

ST=O

A" M

ST=O

i ;;; M

ST=l

I Operation II
i ;;; M

DescriPtionl/
Compares the contents of RAM addressed by W, X, Y registers to
4-bit immediate data i3-0'

Address format and the number of execution cycles
Address format
REGISTER

I

Example

01210
01211
01212

Operand
Mnemonic: format
ILEM

I
I
I

Instruction word
Second
First
I

Number
of words

Number.of
execution
cycles

I
I
I

1

1

$03i

i

II
034
1CE

03D2
03D3

*

ILEM
CAL

$4
OS ERROR

HITACHI 175

No·1
29 I

I
I

Compare Instruction

ILEMD

ILEMD

I

Format

(Innnediate Less or Equal to Memory)

II

I

Status

1/
NB

ILEMD i, d

i

>

M

ST=O
ST=l

i ;:;; M

I

Operation

1/
i ;:;; M(d)

DescriPtionl1
Compares the contents of RAM addressed by lO-bit direct address
d9-0 to 4-bit innnediate data i3~0.

Address format and the number of execution cycles
Address format

Operand
format

I

DIRECT

I

Mnemonic:
ILEMD

I
I

i,d

Instruction word
Second
First
I
$l3i

I
I

I

d

Number
of words

Number ,of
execution
cycles

2

2

Example

1/
01820
01821
01822
01823
01824
01825
01826
01827
01828
01829

176 HITACHI

133
171
132
171
131
171
130
171
151

030
160
030
152
030
140
030
12E
100

060E
0610
0612
0614
0616
0618
061A
061C
061E

*

ILEMD
BRL
ILEMD
BRL
ILEMD
BRL
ILEMD
BRL

JMPL

$3,$030
INITD
$2,$030
PROGCX
$1, $030
PROGB
$0,$030
PROGA
MAIN

;IF M(030)o;:3
;IF M(030)=2
;IF M(030)=1
;IF M(030) =0

Compare Instruc tion

INEM
INEM (Immediate Not Equal to Memory)

I

Format

I

1-'

Status

II

NZ
INEM i

I

Operation

i

=

M

ST=O

i

~

M

ST=1

II
i~ M

DescriPtionl1
Compares the contents of RAM addressed by W, X, Y registers to
4-bit immediate data.

Address format and the number of execution cycles
Address format
REGISTER

I

Example

00700
00701
00702
00703

I Operand
Mnemonic I format

INEM

I
I

Instruction word
Second
First
$02i

i

Number
of words

Number.of
execut10n
cycles

1

1

II
201
02A
342

023E
023F
0240

*

KIZMN

LBI
INEM
BR

$1
$A
KIZM1

HITACHI 177

Compare Instruction

INEMD
INEMD (Immediate Not Equal to Memory)

I

Format

II

I

II

Status
NZ

INEMD i,d

I

Operation

i =

M

ST=O

i

M

ST=l

..

II
i ~ M(d)

I

DescriPtionJ

Compares the contents of RAM addressed by 10-bit direct address
d9-0 to 4-bit immediate data i3-0.

Address format and the number of execution cycles
Address format

I Operand
Mnemonic I format

Instruction word
Second
First

Number
of words

Number ,of
executlon
cycles

2

2

I

DIRECT

I

Example

INEMD

I
I

i ,d

I

$12i

I

d

II

01893
01894
01895

178 HITACHI

124 030
171 25C
171 104

0656
0658
065A

TBINTR

lNEMD
BRL

4,$030

BRL

MBACKO

lNEXTI

RAM Address Instruction

IV
IV (Increment

I

Format

I

II

y)

Status

II

NZ
IY

Y + 1 = 0
Y + 1

I

Operation

"

ST=O
ST=l

0

II
Y + 1 ~Y

DescriPtion]

I
Increments the contents of Y register.
Judges NZ.

Address format and the number of execution cycles
Address format

Mnemonic:
IY

I

Example

00848
00849
00850
00851

Operand
format

I

Instruction word
First
Second
I

Number.of
executlon
cycles

1

1

I
I

$05C

I
I

Number
of words

I

II
002
05C
3A3

XSFY
IY

02AB
02AC
02AD

BR

KINAMEO

*

HITACHI 179

ROM Address Instruction

JMPL
JMPL

I

Format

(Long Jump Unconditionally)

I

I

Status

JMPL u

I

Operation

II

No effect

II

Unconditional jump to any ROM
address space.

DescriPtionl
All bits of PC are replaced with l4-bit direct address P3-0. dg-O'
OP-code is as follows according to ROM capacity.
ROM 2k

P3=P2=P1=0

ROM 4k

P3=P2=0

ROM 8k

P3=0

Address format and the number of execution cycles
Address format
DIRECT

I

Example

Operand
Mnemonic: format
JMPL

I
I
I

u

Instruction word
Second
First
I

Number
of words

Number.of
executlon
cycles

I
I

2

2

$lSp

d

I

01611
01612
01613
01614
01615
01616
01617
01618
01619

180 HITACHI

lAO
lA3
lAO
lAD
lA3
lAE
lAF
lA8
151

030
032
035
036
037
038
039
03A
18B

052E
0530
0532
0534
0536
0538
053A
053C
053E

PROGA

LMID
LMID
LMID
LMID
LMID
LMID
LMID
LMID
JMPL

0,$030
$3,$032
$0,$035
$D,$036
$3,$037
$E,$038
$F,$039
$8,$03A
PROG

Regi ster-to-Regi ster
Instruction

LAB
LAB (Load A from B)

I

Format

I

II

Status

II

No effect
LAB

I

Operation

IJ
B-4A

DescriPtionl1
Transfers the contents of B register to Accumulator.
The contents of B register are unchanged.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
LAB

I

Instruction word
Second
First
I

Number.of
cycles

Number
of words

execut~on

1

1

I

I

$048

I
I

I

I

Example
I_I

01839
01840
01841
01842

048
194 035

0629
062A

*
LAB
LM1ID

$035

*

HITACHI 181

Immediate Instruction

LA!
LA! (Load A from Immediate)

I

Format

I

IJ

Status

II

No effect
LAI i

I

Operation

II
i-4A

DescriPtionl/
Transfers

4~bit

immediate data i3-0 to Accumulator.

Address format and the number of execution cycles
Operand
Mnemonic: format

Address format

LAI

I

Example

I
I
I

Instruction word
Second
First
I
I

i

$23i

I
I

Number
of words

Number.of
execut~on
cycles

1

1

II

01152
01153
01154
01155

182 HITACHI

230
210

039F
03AO

*
*

LAI
LYI

$0
$0

;A=O
;Y=O

RAM Register Instruction

LAM
LAM

I

Format

(Load A from Memory)

I

II

Status
1_1

No effect
LAM (XY)

I

Operation

II

M~A,(X-SPX,

YHSPY)

DescriPtionll:ransfers the contents of RAM addressed by W, X, Y registers to
Accumulator.
The contents of RAM is unchanged.
(When executing M A, exchanges x register for SPX register, and Y
register for SPY register according to the contents of x, y in OP-code.)
MNEMONIC
FUNCTION
y' x
LAM
0
0
X<-+SPX
LAMX
0 I 1
Y<-+SPY
1 I 0
LAMY
1 , 1
X-SPX, y .... SPY
LAMXY

,

Address format and the number of execution cycles
Address format
REGISTER

I

Example

00941
00942
00943

Operand
Mnemonic: format
LAM(XY)

I
I
I

Instruction word
, Second
First
I
%01-1001
-OOyx I

,

Number
of words

Number ,of
execut~on
cycles

1

1

II
091
198 04D
094

02F6
02F7
02F9

KIARTHM5

LAMX

SMCD
LMA

$04D

HITACHI 183

RAM Register Instruction

LAMD
LAMD (Load A from Memory)

I

Format

Ij

Status

No effect

LAMD d

I

Operation

II

II
M(d) -) A

DescriPtionl1
Transfers the contents of RAM addressed by 10-bit direct address
to Accumulator.
The contents of RAM is unchanged.

Address format and the number of execution cycles

Address format
DIRECT

I

Example

I Operand
Mnemonic I format

LAMD

I

Instruction word
First
I
Second
d

$190

d

II

01716
01717
01718

184 HITACHI

190 032
281
194 032

0592
0594
0595

PNEXTI

LAMD

$032

Al

1

LMAD

$032

Number
of words

Number.of
executlon
cycles

2

2

egl ster-to-Reglster
Instruction

LAMR
LAMR (Load A from MR)

I

Format

II

Status

II

No effect
LAMR m

I

Operation

II
MR(m)

~

A

DescriPtionl1
Transfers the contents of Memory Register (MR) addressed by 4-bit
direct address m3-0 to Accumulator.

(MR, second file of RAM, can be selected (l6-digits) by

m3~O.)

Address format and the number of execution cycles
Address format
DIRECT (4 bits)

I

Example

01532
01533
01534
01535
01536

I Operand
Mnemonic I format

LAMR

Instruction word
First
I
Second

:

$27m

m

I

Number
of words

Number ,of
executlon
cycles

1

1

II
276
281
203
1B1

04E2
04E3
04E4
04E5

*

LAMR

$6

AI

$1

LBI

$3

P

$1

HITACHI 185

Input/Output Instruction

LAR
LAR

I

Format

(Load A from R-Port Register)

II

Status

II

No effect
LARm

I

Operation

II

DescriPtionl1
Transfers the contents of R-Port add'ressed by 4-bit direct address
to Accumulator.
The contents of Port Register are unchanged.

Address format and the number of execution cycles
Address format
DIRECT (4 bits)

I

Example

I Operand
Mnemonic I format

Instruction word
First
I
Second

253
180 02Q
"

186MITACHI

Number.of
executlon
cycles

1

1

I

LAR

I
I

m

$25m

II

00980
00981
00982

Number
of words

0314
0315

*

KIINPUTO

LAR
XMAD

$3
$02D

Regl s te r-to-Regl s te r
lnstruction

LASPX
LASPX

I

Format

(Load A from SPX)

I

II

Operation

II

No effect

LASPX

I

Status

II
SPX-+ A

DescriPtionl1
Transfers the contents of SPX register to Accumulator.
The contents of SPX register are unchanged.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
LASPX

I

Example

00835
00836
00837

I
I
I

Instruction word
Second
First
I

Number
of words

Number.of
executlon
c:ycles

I

1

1

$068

I

II
068
281
OE8

029F
02AO
02A1

LASPX
AI
LXA

$1

;A=6
;A=A+1 A=7
;X=A
x=7

HITACHI 187

Regl. s ter-to'-Reg1s te r
Instruction

LASPY
LASPY

I

(Load A from SPY)

I

Format

1/

Status

IJ

No effect
LASPY

I

Operation

II
Spy

-4

A

DescriPtionl1

Transfers the contents of SPY register to Accumulator.
The contents of SPY register are unchanged.

Address format and the number of execution cycles
Address format

Mnemonic:
LASPY

I

Operand
format

J
I
I

Instruction word
Second
First
I

Number
of words

Number.of

I
I
I

1

1

$058

Example

1/

01015
01016
01017

188 HITACHI

002
058
2B3

0336
0337
0338

XSPY
LASPY

ALEI

$3

execut~on

cycles

egt ster-to-Regt ster
Instruction

LAY
LAY (Load A from

I

Format

II

y)

Status

II

No effect

LAY

I

Operation

II
Y-4A

DescriPtionl1

Transfers the contents of Y register to Accumulator.
The contents of Y register is unchanged.

Address format and the number of execution cycles
Address format

, Operand
Mnemonic, format
LAY

I

Example

00585
00586
00587

I

,,

Instruction word
First
I
Second

$OAF

Number
of words

Number.of
executlon
cycles

1

1

II
OAF
281
108 02F

OlE5
01E6
OlE7

LAY

AI
AMD

;A=Y

$1
$02F

;A=A+l
;A=A+M(02F)

HITACHI 189

RegLSter-to-Registe r
Instruction

LBA
LBA (Load B from A)

I

Format

Status

II

No effect

LBA

I

Operat ion

II

II
A~B

DescriPtionl1
Transfers the contents of Accumulator to B register.
The contents of Accumulator is unchanged.

Address format and the number of execution cycles
Address format

, Operand
Mnemonic, format
LBA

I

Example

Instruction word
First
I
Second
$OC8

Number
of words

Number.of
executl.on
cycles

1

1

II

00839
00840
00841

190 HITACHI

234
OC8

02A3
02A4

*

KINAMEO

LA1
LBA

$4

;A=4
;B=A B=4

Immediate Instruction

LSI
LSI (Load B from Immediate)

I

Format

I

II

Status

II

No effect
LBI i

I

Operation

II

-

i-+B

DescriPtionl1
Transfers 4-bit illUUediate data i3-0 to B register.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
LBI

I

I
I
I

i

Instruction word
Second
First
I

Number
of words

Number .of
executlon
cycles

I
I

1

1

$20i

Example

1/

00888
00889
00890

OAF
206

02C4
02C5

*

LAY
LBI

$6

HITACHI 191

RAM Register Instruction

LBM
LBM (Load B from Memory)

I

Format

I

I

Status

II

No effect
LBM (XY)

I

Operation

I

M--?B,(X~)SPX, Y~-)SPY)

DescriPtion] Transfers the contents of RAM addressed by W, X, Y registers to B
register.
The contents of RAM is unchanged.
During executing the above, executes the followings according to the
value of x, y in OP-code.
y
x
FUNCTION
MNEMONIC
LBM
0 I 0
X -SPX
LBMX
0 I 1
LBMY
1 I 0
Y -SPY
LBMXY
1 I 1
X-SPX, Y-SPY

'"
Address format and the number of execution cycles
Address format

LBM(XY)

REGISTER

I

Example

Operand
Mnemonic: format
I
I
I

Instruction word
Second
First
I
I
%00-0100
I
-OOyx I

Number
of words

Number ,of
executl.on
cycles

1

1

I

00809
00810
00811
00812
00813
00814

192 HITACHI

OCO
200
040
ODF
38E
010

028E
028F
0290
0291
0292
0293

KIRAMS

XMB
LBI
LBM
DY
BR
RTN

$0
KIRAMS

;SAVE B TO M(WXY)
;B=O
;B=M(WXY)
;Y=Y-1
;IF Y>=O THEN BR

Input/Output Instruction

LBR
LBR (Load B from R-Port Register)

I

Format

Status

1/

No effect

LBR m

I

II

Operation 1/

R(m)

--4

B

DescriPtionl1
Transfers the contents of R-Port addressed by 4-bit direct address
to B register.
The contents of Port Register is unchanged.

Address format and the number of execution cycles
Address format
DIRECT (4 bits)

I

, Operand
Mnemonic, format
LBR

m

Instruction word
First
I
Second
$24m

Number
of words

Number.of
executlon
cycles

1

1

Example 1/

LBR
LMB

$3

;B-R(3)
;M(WXY)-- B

HITACHI 193

RAM Register Instruction

LMA
LMA

I

Format

(Load Memory from A)

II

I

Operation

II

No effect

LMA (XY)

I

Status

II

A ---) M (X <-~ SPX , Y <-~ SPY)

DescriPtionl1

Transfers the contents of Accumulator to RAM addressed by W, X, Y
registers.
The contents of Accumulator is unchanged.
y

MNEMONIC
LMA
LMAX
LMAY
LMAXY

I

0
0
1
1 I

x
0
1
0
1

FUNCTION
X - SPX
Y -SPY
X- SPX, Y-SPY

Address format and the number of execution cycles
Address format
REGISTER

I

Example

Operand
Mnemonic: format
LMA(XY)

I
I
I

Instruction word
First
Second
I
I
%00-1001 I
-Olyx I

Number
of words

Number.of
executlon
cycles

1

1

II
LWI
LXI
XSPX
LXI
LYI
LAI
LMAX
LAI
LMAX

194 HITACHI

$0
$4
$3
$0
$5
;M(030)-$5
$A
;M(040)-$A

RAM Register Instruction

LMAD
LMAD (Load Memory from A)

I

Format

II

Status

No effect

LMAD d

I

Operation

II

II
A----)M(d)

DescriPtionl/
Transfers the contents of Accumulator to RAM addressed to lO-bit
direct address.
The contents of Accumulator is unchanged.

Address format and the number of cycles
Address format
DIRECT

I

Example

01901
01902
01903

, Operand
Mnemonic, format
LMAD

d

Instruction word
First
I
Second

$194

d

Number
of words

Number .of
execution
cycles

2

2

I]

230
118 034
194 034

0663
0664
0666

LAI
AMCD
LMAD

o
$034
$034

HITACHI 195

RAM Register Instruction

LMADY
LMADY

I

Format

(Load Memory from A, Decrement y)

II

I

Status

II

NB

LMADY (X)

Y- 1 < 0

ST=O

Y - 1 <: 0

ST=1

I Operation II
Y -

l~Y

(XHSPX),

A~M

DescriPtionl1 Transfers the contents of Accumulator to RAM addressed by W, X,
and Y registers.
The contents of Accumulator is unchanged.
Decrements the contents of Y register and judges NB.
(During executing the above, executes the following operation
according to the value of x in OP-code.
MNEMONIC
LMADY
LMADYX

FUNCTION

x

-

0

X-SPX

1

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
I

LMADY(X)

REGISTER

I

Example

Instruction word
Second
First
I

Number
of words

Number.of
execut~on
cycles

I
I
I

1

1

%00-1101
-OOOx

I
I

II

01048
01049
01050
01051

196 HITACHI

230
000
355

0354
0355
0356

*
LPE1

LA!

$0

LMADY

BR

LPE1

RAM Register Instruction

LMAIY
LMAIY

I

Format

(Load Memory from A, Increment y)

I

II
LMAIY (X)

I

Operation

Y + l-Y

Status

II

NZ
Y + 1 = 0

ST=O

Y + 1 ... 0

ST=l

II
(X~SPX),

A-M

DescriPtionllTransfers the contents of Accumulator to RAM addressed by W, X,
and Y registers.
The contents of Accumulator is unchanged.
Increments the contents of Y and judges NZ.
(During executing the above, executes the following operation according
according to the value of x in OP-code.
MNEMONIC
LMAIY
LMAIYX

x
0
1

FUNCTION

-

X-SPX

Address format and the number of execution cycles
Address format
REGISTER

I

Example

00909
00910
00911
00912
00913

Operand
Mnemonic: format
I

LMAIY(X)I
I

Instruction word
First
Second
I
I
%00-0101 I
-OOOx I

Number
of words

Number.of
execut~on
cycles

1

1

II
051
091
118 044
OA6
051

02D6
02D7
0208
020A
020B

LMAIYX
LAMX
AMCD

$044

DAA

LMAIYX

\

HITACHI 197

Immediate Instruction

LMID
LMID

I

Format

(Load Memory from Immediate)

II

Status

II

No effect
LMID i,d

I

Operation

II
i -) M(d)

DescriPtionl1
Transfers 4-bit immediate data i3-0 to RAM addressed by 10-bit
direct address d9-0'

Address format and the number of execution cycles
Address format

, Operand
Mnemonic, format

DIRECT

I

Example

LMID

Instruction word
Second
First
I

I

,

i,d

$lAi

I
I

,

d

Number
of words

Number ,of
executlon
cycles

2

2

II

01492
01493
01494
01495
01496

198 HITACHI

lAB
lAF
lAE
lAF

004
009
OOA
OOB

LMID
LMID
LMID
LMID

04B9
04BB
04BD
04BF

*

$B,$004
$F,$009
$E,$OOA
$F, $OOB

;TMB EXT INPUT
,TCBL=E
;TLRU=F

No·1
52 I

LMIIY

I

Format

I

II

Status

II

NZ
Y + 1 = 0
Y + 1

Operation

LMIIY

(Load Memory from Immediate, Increment Y)

LMIIY i

I

Immediate Instruction

"'

ST=O

0

ST=l

II
i-4M
Y + 1 -4 Y

DescriPtionl1
Transfers 4-bit immediate data i3-0 to RAM addressed by W, X, and
Y registers.
Increments the contents of Y register and judges NZ.

Address format and the number of execution cycles

I

Address format

Mnemonic:

REGISTER

LMIIY

Example

00961
00962
00963
00964
00965

Operand
format

I
I
I

Instruction word
Second
First
I

Number
of words

I
I

1

$29i

i

Number.of
execut10n
cycles
1

I

II
290
07A
309

0309
030A
030B

*
KIARTHM8

LMIIY

YNEI
BRS

$0
$A
KIARTHM8

*

HITACHI 199

Input/Output Instruction

LRA
LRA

I

Format

(Load R-Port Register from A)
Status

I

II

II

No effect
LRA m

I

Operation

II
A ~ R(m)

DescriPtionl1

Transfers the contents of Accumulator to R-Port register addressed
by 4-bit direct address m3-0'
The contents of Accumulator is unchanged.

Address format and the number of execution cycles
Address format
DIRECT (4 bits)

I

Example

Operand
Mnemonic: format
LRA

I
I
I

Instruction word
First
I
Second

m

Number
of words

Number.of
execut~on
cycles

1

1

$2Dm

II

00675
00676
00677
00678
00679
00680
00681

200 HITACHI

000
160 255
2Dl
2C2
338

022D
022E
0230
0231
0232

*

KIOUTC4

NOP
CALL
LRA
LRB

BR

*

KIZMC
$1
$2
IUOUTC9

Input/Output instruction

LRB
LRB (Load R-Port Register from B)

I

Format

II

Status

No effect

LRB m·

I

Operation

II

II
B~

R(m)

DescriPtionl1
Transfers the contents of B register to R-Port register addressed
by 4-bit direct address m3-0'
The contents of B register is unchanged.

Address format and the number of execution cycles
Address format
DIRECT (4 bits)

I

Example

,00664
00665
00666
00667
00668
00669
00670

, Operand
Mnemonic, format
LRB

Instruction word
First
I
Second

m

,

$2Cm

Number
of words

Number ,of
execut~on
cycles

1

1

:

II
000
160 255
2D2
2C4
338

0222
0223
0225
0226
0227

*

KIOUTCO

NOP
CALL
LRA
LRB
BR

KIZMC
$2
$4
KIOUTC9

*

HITACHI 201

RAM Address Instruction

LWI
LWI

1

(Load W from Immediate)

..

I

Format

I

II

Operation

II

No effect

LWI i

I

Status

II
i~W

DescriPtionl1
Transfers 2-bit immediate data il-O to W register.

/

Specifies RAM file No. with X register.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
LWI

I

Example

I
I
I

i

Instruction word
Second
First
I
%00-1111 I
-OOiliol

II

01690
01691
01692
01693

202 HITACHI

222
OFO
210
290

057E
057F
0580
0581

RAMINIT
RLOOP

LXI
LWI
LYI
LMIIY

2
0
0
0

Number
of words

Number.of
execut;Lon
cycles

1

1

RAM Address Instruction

LXA
LXA (Load X from A)

I

Format

II

Status

No effect

LXA

I

Operation

II

II

DescriPtionl1
Transfers the contents of Accumulator to X register.
The contents of Accumulator is unchanged.

Address format and the number of execution cycles
Address format

I Operand
Mnemonic I format

I

LXA

I

Example

01696
01697
01698

I
I

Instruction word
Second
First

$OE8

Number
of words

Number ,of
execut~on
cycles

1

1

II
068
281

OE8

0584
0585
0586

LASPX
AI

1

LXA

HITACHI 203

RAM Address Instruction

LXI
LXI

I

Format

(Load X from Immediate)

I

II

Status

II

No effect

LXI i

I Operation II
i~X

DescriPtionl1
Transfers 4-bit immediate data i3-0 to X register.
Specifies RAM file No.

Address format and the number of execution cycles
Address format

Mnemonic:
LXI

I

Example

Operand
format

I
I
I

i

Instruction word
Second
First
I

Number
of words

Number ,of
execut10n
cycles

I
I

I

I

$22i

I

II

00492
00493
00494
00495
00496
00497

204 HITACHI

OFO
224
21F
23F
281
000

0192
0193
0194
0195
0196
0197

LWI
LXI
LYI
LAI
AI
LMADY

$0
$4
$F
$F
$I

;W=O
;X=4
;Y=F
;A=F
;A=A+l
;M (WXY) =A Y=Y-l

RAM Address Instruction

LYA
LYA

I

Format

(Load Y from A)
Status

II

No effect

LYA

I

Operation

I~

II

Descript ionl ~
Transfers the contents of Accumulator to Y register.
The contents of Accumulator is unchanged.

Address format and the number of execution cycles
Address format

, Operand
Mnemonic, format
LYA

I

Example

01874
01875
01876

,

Instruction word
First
I
Second
$OD8

Number
of words

Number ,of
executlon
cycles

1

1

II
190 032
OD8
OE4

0645
0647
0648

TIMER

LAMD

$032

LYA
SED

HITACHI 205

RAM Address Instruction

LVI
LVI

I

Format

(Load Y from Immediate)

I

IJ

Status

II

No effect
LYI i

I

Operation

II
i~

Y

DescriPtionl/
Transfers 4-bit immediate data i3-0 to Y register.
Specifies RAM digit No. and address of discrete I/O.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
LYI

I

Example

I
I
I

i

Instruction word
Second
First
I
$2li

I

I

II

00218
00219
00220
00221
00222

206 H ,TACH I

OFO
220
210
002
218

00e4
OOeS
00e6
00e7
00e8

LWI
LXI
LYI
XSPY
LYI

$0
$0
$0
$8

Number
of words

Number.of
executlon
cycles

1

1

Arithmetic Instruction

NEGA
NEGA

I

Format

(Negate A)

II

Status

No effect

NEGA

I

Operation

II

1/

A+l-+A

DescriPtionl1
Takes 2's complement of the contents of Accumulator and stores
the result in Accumulator.

Address format and the number of execution cycles

Address format

I Operand
Mnemonic, format

NEGA

I

Example

00795
00796
00797
00798

I

,

Instruction word
First
, Second
$060

I

Number
of words

Number ,of
execut~on
cycles

1

1

II
04C
048
060

0282
0283
0284

*

KIRAM7

IB
LAB

NEGA

;B=B+l
;A=B
;A=-A

HITACHI 207

Control Instruction

NOP
NOP

I

Format

(No Operation)

I

II

Operation

II

No effect

NOP

I

Status

II

Updates the program counter only
and has no effect on the other
registers.
DescriPtionl1

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
NOP

I
I

Instruction word
Second
First
I

Example

II

01549
01550
01551
01552
01553
01554
01555
01556
01557

208 HITACHI

200
04C
000
000
000
000
000
3EB
010

04EA
04EB
04EC
04ED
04EE
04EF
04FO
04F1
04F2

Number ,of
executl.on
cycles

1

1

I

I
I

$000

I

I

Number
of words

KIDLYON

LBI
IB
NOP
NOP
NOP
NOP
NOP
BR
RTN

$0

*-6

Arithmetic Instruction

OR
OR (OR A and B)

I

Format

II

Status

No effect

OR

I

Operation

II

II
AUB --+ A

DescriPtionl1
Performs logical OR between the contents of Accumulator and those
of B register, and stores the result in Accumulator.

Address format and the number of execution cycles
Address format

I Operand
Mnemonic I format

$144

OR

I

Example

01136
01137
01138
01139
01140

Instruction word
First
I
Second

Number
of words

Number.of
executlon
cycles

1

1

II
20A
235
144
OC8

0392
0393
0394
0395

*

LBI
LA!

OR
LBA

$A
$5

;B=lOlO
;A=OlOl
;A=AUB A=llli
;B=F

HITACHI 209

Arithmetic Instruction,

ORM
ORM (OR Memory with A)

I

Format

II

I

Status

II

NZ
ORM

I

Operation

AUM = 0

ST=O

AUM ,0

ST=l

II
AUM-) A

DescriPtionl1
Performs logical OR between the contents of Accumulator and those
of RAM addressed by W, X, and Y registers, and stores the result
in Accumulator.

Address format and the number of execution cycles
Address format
REGISTER

I Operand
Instruction word
Number
Mnemonic I format I--F~i:-r"'s-t----"""-t,----~S:-e-c-o-n-d;-,,-t of words

ORM

$OOC

1

I Example 1/

01253
01254
01255

210 HITACHI

21F

OOC
ICE

03F6
03F7
03FB

LYI

$F

ORM
CAL

OSERROR

Number ,of
executl.on
cycles
1

Arithmetic Instructi

ORMD
ORMD

I

Format

(OR Memory with A)

I

II

Status

1/
NZ

ORMD d

I

Operation

ADM = 0

ST=O

ADM

ST=l

~

0

II
ADM(d) -> A

DescriPtionl1
Performs logical OR between the contents of Accumulator and those
of 10-bit direct address dg-O' and stores the result in Accumulator.

Address format and the number of execution cycles
Address format
DIRECT

I

Example

01256
01257
01258

Mnemonic:
ORMD

Operand
format

I
I
I

d

Instruction word
Second
First
I
$lOC

I
I

I

Number
of words

Number ,of
executlon
cycles

2

2

d

II
10C 07F
lCE

03F9
03FB

ORMD
CAL

$07F
OS ERROR

*

HITACHI 21 1

Input/Output InstructiOn

p

P

I

Format

(Pattern Generation)

I

1\

Status

II

No effect
P p

I

Operation

II

u.

lW1'I

10

ROM pattern
ROM at tern

11
00

Destination
to A,lS regls e
to Rl.~2 reglsters
to A.B and R.: ,8.2

R7 '" 110
pactern

R!!,RS

ROM pattern

Loads ROM bit pattern addressed by PC of which the contents are
replaced with Accumulator, B register, and 4-bit register into
Port register Rl, R2 , or Accumulator, B register.

DescriPtionl1

PC1J

Replaced PC

I
I
I

PCO
: P3 : P2 : PI : Po : B3 : B2 : Bl : BO : A3 : A2 : Al : Ao
Rg : RS : R7 :R6 :RS :R4 :R3 :R2: Rl :RO
ROM pattern
Loaded
into Accumulator, B
1
...
: BJ :B;Z : Bl : BO : AJ : A2 : Al : Ao
register
1 ... : R33:R32:R3l:R30:R23:R2~ R2l: R201 Loaded into Rl,R2 registers

I0 : 0

I

I
I

:

:

Address format and the number of execution cycles
Address format
REGISTER +
DIRECT(4 bits)

I

Example

Operand
Mnemonic: format
P

I
I
I

p

Instruction word
Second
First
r

:

$lBp

I

II

01782
01783
01784
01785

212 HITACHI

236
20E
lB7

05E2
05E3
05E4

*

LAI
LBI
P

6
$E
7

Number
of words

Number.of
executlDn
cycles

1

2

Arithmetic Instruction

REC
REC (Reset Carry)

I

Format

I

II

Operation

II

No effect

REC

I

Status

II
0----) CA

DescriPtionl1
Resets Carry.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
REC

I

I

Instruction word
Second
First
I

Number
of words

Number .of
executlon
cycles

I
I
I

1

1

$OEC

I
I

Example

11

01896
01897
01898
01899
01900

000
231
OEC
118 033
194 033

065C
065D
065E
065F
0661

INEXTl

NOP
LAI

1

REC
AMCD

LMAD

$033
$033

HITACHI 213

Input/Output Instruction

RED
RED (Reset Discrete I/O Latch)

I

Format

II

I

Status

RED

I

Operation

II

No effect

II
o~

D(Y)

DescriPtionl1
Resets discrete I/O latch addressed by Y register.

Address format and the number of execution cycles
Address format
REGISTER

I

Example
00223
00224
00225
00226
00227
00228
00229
00230
00231
00232
00233
00234
00235
00236
00237

Operand
Mnemonic: format
RED

I

Instruction word
Second
First
I

Number
of words

Number.of
executlon
cycles

I
I

1

1

$064

I
I

I

II

214 HITACHI

064
002
05C
002
05C
300
002
042
092

00C9
OOCA
OOCB
OOCC
OOCD
OOCE
OOCF
0000
0001

201
2C2
OE4

0002
0003
0004

*
RMLOOP

RED
XSPY
IY
XSPY
IY
BR

*+2

XSPY
LBMY
LAMY
*
LRA
LRB
SED
*

$1
$2

No.

I Input/Output

68

I

Instruction

REDO

REDO (Reset Discrete I/O Latch Direct)

I

Format

I

II

Status

II

No effect

REDD m

I~

I

Operation

0-- D(m)

DescriPtionl1
Resets discrete I/O latch addressed by 4-bit direct address m3-0'

Address format and the number of execution cycles
Address format
DIRECT (4 bits)

I

Example

Operand
Mnemonic: format
REDD

I
I
I

Instruction word
Second
First
I

Number
of words

Number ,of
executlon
cycles

1

1

I

m

I
I

$26m

II

01240
01241

ICE
262

03EB
03EC

CAL

REDD

OSERROR
$2

HITACHI 215
---~-

----- - - - - - - - - - - - - - - . - - - - - _ .

RAM: Bit Manipulation
lnstruc ·0

REM
REM

I

Format

(Reset Memory Bit)

II

I

Operation

II

No effect

REM n

I

Status

I~
o ~ M(n)

DescriPtionl1
Resets the bit specified by nl-O of RAM addressed by W, X, and
Y registers.

Address format and the number of execution cycles
Address format
REGISTER

I

Example

01034
01035
01036

"

Operand
Mnemonic: format
REM

,,I

n

Instruction word
Second
First
I
%00-1000 I
-10 n1 no'

II
094
OaB
08A

0347
0348
0349

LMA

REM

3

REM

2

Number
of words

Number.of
execut10n
cycles

1

1

RAM Bit Manipulatlon
Instruction

REMD
REMD (Reset Memory Bit)

I

Format

I

II

Operation

II

No effect

REMD n,d

I

Status

II
0---) M(d,n)

DescriPtionl1
Resets the bit specified by n1-0 of RAM addressed by 10-bit
direct address d9-0'

Address format and the number of execution cycles
Address format

I

DIRECT

I

Example

01497
01498
01499
01500
01501

Operand
Mnemonic: format
REMD

I
I

n,d

Instruction word
Second
First
I
I
%01-1000 I
d
-10 n1 no I

Number
of words

Number ,of
executlon
cycles

2

2

II
185
188
189
184

001
002
002
000

04C1
04C3
04C5
04C7

SEMD
REMD
REMD
SEMD

1,$001
0,$002
1,$002
0,$000

;SET lMl
;RESET lFTB
;RESET lMTB
;SET liE

*

HITACHI 217

Arithmetic Instruction

ROTL
ROTL (Rotate Left A with Carry)

I

Format

II

I

Operation

II

.,.

No effect

ROTL

I

Status

II

Rotates the contents of Accumulator
with Carry (CA) to the left by 1 bit.

DescriPtionl1
(Result)

~A3:A2:Al:Ao~

[fi]

IA2:Al:AO:CAI

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
ROTL

I

Example

I

lnstruction.word
Second
First
I
$OAl

I
I

I

I

II

00588
00589
00590
00591
00592

218 HITACHI

OEC
OAI
200
OBI

01E9
OlEA
OlEB
OlEC

REC
ROTL

*

LBI

$0

TBR

$1

Number
of words

Number.of
executlon
cycles

1

1

Arithmetic Instruction

ROTR
ROTR (Rotate Right A with Carry)

I

Format

I

II
ROTR

I

Operation

Status

I~

No effect

I~

Rotates the contents of Accumulator
with Carry (CA) to the right by 1
bit.
DescriPtionl1

~A3:A2:Al:AO·rJ

(Result)

~

ICA :A3: A2: All

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
ROTR

I

Example

01431
01432
01433
01434
01435

I
I
I

Instruction word
Second
First
I
I
$OAO
I

Number
of words

Number.of
execut10n
cycles

1

1

I

II
058
OAO
06F
390

0489
048A
048B
048C

*

KISCANT

LASPY

ROTR
TC
BR

KISCANR

HITACHI 219

ROM Address Instruction

RTN
RTN (Return from Subroutine)

I

Format

Status

II
RTN

I

Operation

II

No effec t

II
Retures from subroutine.

DescriPtionJ

I

Returnes the contents of PC saved in RAM. (stack area) when occuring
subroutine instruction or interrupt to PC.

Address format and the number of execution cycles
Address format

, Operand
Mnemonic, format
RTN

I

Example

Instruction word
First
I
Second

,

,

$OlO

1

I

IJ

00593
00594
00595
00596
00597

220 HITACHI

20e
04e
3EE
010

OlED
OlEE
OlEF
OlFO

*
KIDLYKEY

LBI
IB
BR
RTN

Number
of words

$R
*-1

Number .of
execut10n
cycles
3

ROM Address Instruction

RTNI
RTNI

I

Format

(Return from Interrupt)

II

Status

II

Restores the contents of Status

RTNI

saved before.

I

Operation

II

1 -) lIE return from subroutine

DescriPtionl1
This is the return instruction (RTN) accompanied by liE set
instruction.
Restores Carry and Status simultaneously.

Address format and the number of cycles
..

Address format

Operand
Mnemonic: format
RTNI

I

Example

01478
01479
01480

I
I
I

Instruction word
Second
First
I
$011

I
I

I

Number
of words

Number.of
executlon
cycles

1

3

II
2FF
18A 001
011

04B1
04B2
04B4

KITMRTN

XMRA
REMD
RTNI

$F
2,$001

HITACHI 221

SBY
SBY (Stand-by Mode)

I

Format

I

II

Operation

II

No effect

SBY

I

Status

II
Brings to Stand-by mode.

DescriPtionl1
The SBY instruction puts the MCU into the Standby mode. In the Standby
mode, the oscillator circuit is active and timer/counter and serial interface continue working. On the other hand, the CPU stops since the clock
related to the instruction execution stops. Registers, RAM and Input/
Output pins retain the state they had just before going into the Standby
mode. The Stand-by mode is released by RESET input or CPU interrupt.
If I/E=l, enters into interrupt sequence and if I/E=O, executes the
instruction next to SBY without executing interrupt process.
Address format and the number of execution cycles
Address format

I Operand
Mnemonic I format

SBY

I

Example

Instruction word
First
I
Second

$14C

IJ

.~

IY
SBY
LAR
LMAIY
LAR
LMAIY

'222 HITACHI

°
$1
$I

Number
of words

Number .of
execut10n
cycles

1

1

Arithmetic Instruction

SEC
SEC (Set Carry)

I

Format

I

II

Status

No effect

SEC

I

Operation

II

II
1-+ CA

DescriPtionl1
Sets Carry.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
SEC

I
I

Instruction word
Second
First
I'
$OEF

I

I

Example

I
I

I

Number
of words

Number .of
executlon
cycles

1

1

II
SEC
SMCD

;M-A-CA(O)-A

HITACHI 223

Input/Output In~trUct.ion

SED
SED (Set Discrete I/O Latch)

I

Format

I

II

Status

No effect

SED

I

Operation

II

II
1-.

D(Y)

DescriPtionl1

Sets discrete I/O addressed by Y register.

Address format and the number of execution cycles

I

Address format

"Mnemonic:

REGISTER

SED

Example

I
I
I

Operand
format

Instruction word
Second
First
I
$OE4

:

Number
of words
1

I

Number.of"
exec·u.tl.un
cycles
1

II

"

LYI
SED
IY
SED
IY
SED
IY
SED

$0

;0(0)=1
;0(1)=1
;0(2)=1
;0 (3)=1

i

Input/Output Instruction

SEDD
SEDD (Set Discrete I/O Latch Direct)

I

Format

II

I

Status

No effect

SEDD m

I

Operation

II

II
l~

D(m}

DescriPtionl1
Sets discrete I/O addressed by 4-bit direct address m3-0.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format

':

I

DIRECT (4 bits)
,,"

I

Instruction word
Second
First
I

,

Example

01101
01102
01103
01104
01105
01106

SEDD

I

I

m

$2Em

I
I
I

Number
of words

Number ,of
executlon
cycles

1

1

II
2EO
2E1
2E2
2E3

"

037A
037B
037C
0370

*

KIOINCLR

SEDO
SEDO
SEOO
SEOO

$0
$1

$2
$3

;0 (0) =1
;0 (1) =1
;0(2)=1
;0(3)=1

*

.

HITACHI22~.

RAM Bit Manipulation
Instruction

SEM
SEM (Set Memory Bit)

I

Format

II

I

Operation

II

No effect

-

SEM n

I

Status

II
1 ~ M(n)

DescriPtionl1
Sets the bit specified by nl-O of RAM addressed by W, X,and Y
registers.

Address format and the number of execution cycles
..

Address format

SEM

REGISTER

I

Example

Operand
Mnemonic: format

,,
I

n

Instruction word
First
,I Second
%00-1000 I
-01 n1 no'

II

01319
01320
01321
01322
01323
01324

226 HITACHI

Number
of words

Number.of
execut10n
cycles

1

1

..

220
08A
08B
084

0428
0429
042A
042B

*

*

LXI
REM
REM
BEM

$0
2
3
0

RAM Blt Mao1pulat1on
Instruc ion

SEMD
SEMD (Set Memory Bit)

I

Format

II

Status

No effect

SEMI> n,d

I

Operation

II

II
1 -+ M(d,n)

I

DescriPtion]

Sets the bit specified by nl-O of RAM addressed by 10-bit direct
address d9-0.

Address format and the number of execution cycles

I

Address format

Mnemonic

DIRECT

SEMI>

Example

01062
01063
01064
01065
01066

I
I

Operand
format

I
I
I

n,d

Instruction word
First
I
Second
%01-1000
I
d
-01 nl no I

Number
of words

Number.of
execut10n
cycles

2

2

II
187 043
363
18B 043
000

035E
0360
0361
0363

LPE3

SEMD
BR
REMD
NOP

$3,$043
LPE3
$3,$043

*

HITACHI 227

No·1
81

Arithmetic Instruction

I

SMC

I
I
SMC (Subtract A from Memory with Carry)

I

Format

II

I

Operation

II

NB of (M-A-CA)

SMC

I

Status

M - A - CA < 0

ST=O

M - A - CA

ST=l

i';

0

II
M- A -

CA~

A,

NB~

CA

\

I

DescriPtio~

Subtracts the contents of Accumulator and CA from the contents of
RAM addressed by W, X, and Y registers and stores the result in
Accumulator.
Latches NB into CA and judges it.

Address format and the number of execution cycles
Address format
REGISTER

Instruction word
Second
First
I

Operand
Mnemonic: format
SMC

Example

Number.of
executron
cycles

1

1

I

I

$098

I
I

I

Number
of words

I

I

II

01170
01171
01172
01173
01174,

228 HITACHI

OSC
098
ICE
OSC
008

03AD
03AE
03AF
03BO
03Bl

IY
SMC
CAL
IY
AM

;Y=Y+l
; A=M (WXY) -A- CA
OS ERROR
;Y=Y+l
;A=M(WXY)+A

Arithmetic Instruction

SMCD
SMCD (Subtract A from Memory with Carry)

I

Format

Status

II

NB of (M-A-CA)

SMCD d

I

Operation

II

M - A - CA

<

0

ST=O

M - A - CA

~

0

ST=1

II

M(d) - A -

CA~A, NB~CA

DescriPtionl1
Subtracts the contents of Accumulator and CA from the contents
of RAM addressed by 10-bit direct address d9-0, and stores the
result in Accumulator.
Latches NB into CA and judges it.

Address format and the number of execution cycles
Address format

M
' : Operand
nemon1C I format

Instruction word
First
I
Second

Number
of words

Number ,of
execut10n
cycles

2

2

I

DIRECT

I

Example

SMCD

d

$198

:

d

II
IY
SMCD
CAL

IY
AM

$035
OS ERROR

;Y=Y+l
;A=M(035)-A-CA
;Y=Y+l
;A=M(WXY)+A

HITACHI 229

Control Instruc tion

STOP
STOP

I

Format

(Stop Mode)

II

I

Status

No effect

STOP

I

Operation

II

II
Brings to Stop mode.

Description

II
Brings all operations to halt by stopping osci llation.
The contents of RAM are held.
Stop mode is released with reset and the next operation starts from
the reset state.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
STOP

I

Example

I

Instruction word
, Second
First

Number
of words

Number .of
executlon
cycles

I

1

1

,

$l4D

I
I

I

II

01593
0159.4
01595
01596
01597
01598
01599
01600

134
171
133
171
132
171
131
171

030
18B
030
161
030
1B6
030
lSB

0518
051A
051C
051E
0520
0522
0524
0526

ELSE 1

ILEMD
BRL

ILEMD
BRL
ILEMD
BRL
ILEMD
BRL

STOP

...

230 HITACHI

4,$030
PROG
3,$030
PROGD
2,$030
PROGC
1,$030
PROG

Control Instruction

(Note) The STS instruction is not available
in the HMCS4l2 and HMCS4l4.

STS

I

Format

STS

(Start Serial)

I

II

Operation

II

No effect

STS

I

Status

II
Serial Start

DescriPtionl/

Starts serial operation.
Outputs serial internal clock.
Enables itself to reset serial counter and input serial c lock to
serial counter and serial shift register.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format

Instruction word
Second
First
I

I

I

STS

I

Example

I
I

$148

I
I

Number
of words

~~~g~Lg~

I

1

cycles

II
LMID
LMID
LMID
LMID
SEM
REM
REM
STS

$3,
$5,
$A,
$3,
$0,
$0,
$1,

$
$
$

#
$000
$003
$003

;PMR
;SRL
;SRU
;SMR
;SET I/E
; RESET IFS
; RESET IMS
; START SCI

HITACHI 231

RAM Address Instruction

Syy
Syy (Subtract A from Y)

I

Format

I

II

Status

NB of (Y-A)

SYY

Y- A

I

Operation

II
< 0

ST=O

Y - A ;;: 0

ST=l

II
Y-A~Y

DescriPtionl1
Adds two's complement of the contents of Accumulator to the
contents of Y register. (y+A+l).

Address format and the number of execution cycles
Address format

I Operand
Mnemonic, format

SYY

I

Example

Instruction word
First
, Second
$OD4

Number
of words

Number.of
executlon
cycles

1

1

11

01158
01159

232 HITACHI

OD4
ICE

03A3
03A4

;Y=Y-A

SYY
CAL

OSERROR

ROM Address Instruction

TBR
TBR (Table Branch)

I

Format

I

II

1/
No effect

TBR P

I

Status

Operation

1/
Unconditional branch with
Table.

DescriPtionl1 PCII-0 are modified by Accumulator, B register, and 4-bit direct
address P3-O· That is, performs unconditional branch with the
data of Accumulator, B register, and 4-bit direct address.
PCl3-12 are O.
PC O
PC l3
0

/

: 0 : P3 : P2: PI : Po : B3 : B2 : BI : BO : A3 : A2 : Al >0

I

Address format and the number of execution cycles
Address format
REGISTER +
DIRECT (4 bits)

I

Operand
Mnemonic: format
TBR

I
I
I

P

Instruction word
Second
First
I

Number
of words

Number.of
execut~on
cycles

I
I

I

1

$OBp

I

Example

1/

LAI
LBI
TBR

$5
$7
$3

,JUMP TO Address ($0375)

HITACHI 233

Arithmetic Instruction

TC
TC

I

Format

(Test Carry)

I

II

Status

CA

TC

I

Operation

11
CA=O

ST=O

CA=l

ST=l

II
Tests the contents of CA
(Carry) .

DescriPtionl1
The contents of CA remains unchanged.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format

Ins truc tion word
First
Second
I

I

TC

I

Example

$06F

I
I

I
I

I

II

00244
00245
00246
00247
00248
00249
00250

234 HITACHI

*
25A
OAO
OAO
06F
OF3
3E2

OODB
OODe
OODD
OODE
OODF
OOEO

LAR
ROTR
ROTR

$A

TC

LWI
BR

$3
*+2

Number
of words

Number.of
execut10n
cycles

1

1

Input jOutput Instruc tion

TD
TD

I

Format

(Test Discrete I/O Latch)

I

II

Status

D (Y)

TD

I

Operation

II
D(Y) =0

ST=O

D(Y) =1

ST=l

II
Tests D(Y).

DescriPtionl1
Trsts discrete I/O addressed by Y register.
The contents of discrete I/O latch.

Address format and the number of execution cycles
Address format
REGISTER

I

Example

Operand
Mnemonic: format
TD

I
I
I

Instruction word
Second
First
I
$OEO

I
I
I

Number
of words

Number.of
executl0n
cycles

1

1

II
LYI

$12

TD

BRL

OSERROR

;TEST D(12)
;IF ST=l

HITACHI 235

Input/Output Instruction

TOO
TOO (Test Discrete· I/O Latch Direct)

I

Format

I

II

Status

D(m)

TDD m

I

Operation

IJ
D(m)=O

ST=O

D(m)=l

ST=l

II
Tests D(m).

DescriPtionl1
Tests discrete I/O addressed by 4-bit direct address m3-0.
The contents of discrete I/O latch.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
TDD

DIRECT (4 bits)

I

Example

I
I
I

m

Instruction word
Second
First
I

Number
of words

I
I

1

$2Am

I

II

01581
01582
01583
01584
01585
01586
01587
01588
01589
01590
01591
01592

236 "'ITACHI

2A3
171
171
2A2
171
171
2A1
171
171
2AO
171
171

109
12E
10E
140
113
152
118
160

0504
0505
0507
0509
050A
050C
050E
050F
0511
0513
0514
0516

MBACKO
NEXT1
NEXT 2
NEXT3

TDD
BRL
BRL
TDD
BRL
BRL
TDD
BRL
BRL
TDD
BRL
BRL

3
NEXT1
PROGA
2
NEXT2
PROGB
1
NEXT3
PROSCX
0
ELSE1
INITD

Number .of
execut~on .
cycles
1

RAM. Bit ~nipulat1on

TM
TM (Test Memory Bit)

I

Format

I

II

M(n)

TMn

I

Operation

Status

II
M(n)=O

ST=O

M(n)=l

ST=l

II
Tests M(n).

DescriPtionl1
Tests the bit specified by n1-0 of RAM addressed by W, X, and Y
registers.
The contents of RAM remains unchaned.

Address format and the number of execution cycles
Address format
REGISTER

,I

Example

01226
01227
01228
01229
01230

Operand
Mnemonic: format
TM

I

I
I

Instruction word
Second
First
I

Number
of words

Number .of
executlon
cycles

1

1

%00-1000 I
-llninOI

n

II
2lE
08F
lCE

03EO
03El
03E2

*

LYI

*

$E

TM

3

CAL

OBERROR

(

11 ITACH I 237

TMD (Tes t Memory Bi t)

I

Format

I

II

M(n)

1MD n,d

I

Operation

Status

II
M(n)=O

ST=O

M(n)=l

ST=l

II
Tests M(d,n)

DescriPtionl1
Tests the state of .bit specified by nl-O of RAM addressed by
W, X, and Y registers.

The contents of RAM remains unchanged.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
I

TMD

DIRECT

I

Example

I
I

n,d

Instruction word
Second
First
I
I
%01-1000 I
d
-11 n1 no I

Number
of words

Number ,of
executlon
cycles

2

2

II

01512
01513
01514
01515
01516
01517

238 HI,.ACI·U

253
2FC
18E 02c
308
3CA

0402
0403
0404
Q406
0407

*
LAR
XMRA

TMD
BR
BR

$3
$C
2,$02C
KICNTNXT
KICNTOSP

RAM-Register Instruction

XMA
XMA

I

Format

(Exchange Memory and A)

I

II

No effect

XMA (XY)

I

Operation

I

Status

II

(X_ SPX, y

~

SPY) ,M_ A

DescriPtionl1 Exchanges the contents of RAM addressed by W, X, and Y registers
with those of Accumulator.
(During executing the above, executes the followings according to the
value of x and y in OP~code.
MNEMONIC
y Ix
FUNCTION
XMA
XMAX

XMAY
XMAXY

0
0
0'1
1 I 0
1 : 1

--

X-SPX
Y-SPY
X-SPX, Y.... SPY

Address format and the number of execution cycles
Address format
REGISTER

I

. : Operand
Mnemon1c , format
XMA(XY)

I
I
I

Instruction word
Second
First
I

Number
of words

Number.of
execut10n
cycles

I
I
I

1

1

%00-1000

-OOyx

Example

1/

LWI
LXI
LYI
XSPY
LYI
LAI
XMAY
XMA

$0
$4
$5
$0
$5
;M(040)-A, Y=5
;M(045)-A

HITACHI 239

RAM· Register Instruction

XMAD
XMAD

I

Format

(Exchange Memory and A)

I

II

Status

No effect

XMAD d

I

Operation

II

II
M(d)

->

A

I

DescriPtio~

Exchanges the contents of RAM addressed by lO-bitdirect address
dg-O with those of Accumulator.

Address format and the number of execution cycles
Addr.ess format

XMAD

DIRECT

I

Example

Mnemonic:

Operand
format

I
I
I

Instruction word
First
Second
I

$180

d

I
I

Number
of words

Number ,of
executlon
cycles

2

2

d

I

II

01067
01068
01069
01070
01071
01072
01073

240 HITACHI

253
180 020
23C
19C 020
364
010

0364
0365
0367
0368
036A
036B

KIINPUT2

LAR
XMAD

LAI
ANMD

BRS

*

RTN

$3
$020
$C
$020
KIINPUT2

RAM-Register Instruction

XMB
XMB

I

Format

(Exchange Memory and B)

I

IJ

Status

No effect

XMB (XY)

I

Operation

I

II

(X~SPX, Y~SPY),M~B

DescriPtionl1

Exchanges the contents of RAM addressed by W, X, and Y registers
with those of B register.
(During executing the above, executes the followings according to the
value of x and y in OP-code.
y I x
MNEMONIC
FUNCTION
XMB
0
0
-XMBX
0 I 1
X-SPX
XMBY
1 I 0
Y-SPY
XMBXY
1 I 1
X-SPX, Y-SPY

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
I

XMB(XY)

REGISTER

I

Example

01129
01130
01131
01132
01133
01134
01135

Instruction word
Second
First
I

Number
of words

Number.of
executJ.on
cycles

I
I
I

1

1

%00-1100
-OOyx

I
I

II
*
OAF
207
IBI
OCI
051
38C

038C
038D
038E
038F
0390
0391

LAY
LBI
P
XMBX
LMAIYX
BR

$7
$1

;A=O
;B=7
;B,A=ROM (17Y)
;M(WXY)=B X--'SPX
;M(WXY)=A Y=Y+l X'-SPX

*-5

HITACHI 241

ReglS ter-to-Regl ste r
Instruction

XMRA
XMRA

I

Format

(Exchange MR and A)

IJ

Status

No effect

XMRA m

I

Operation

II

II
MR(m)

~A

DescriPtionl1
..

Exchanges the contents of Memory Register (MR) in RAM with those
of Accumulator.
16-digits (2 files) are MR, and 4-bit direct address m3-0 can
select any digit.

Address format and the number of execution cycles
Address format
DIRECT (4 bits)

I

Example

Op e rand I-_I....,n_s_t_r_u_c_t,.i_o_n_w_o_r_d-:--i Number
Mnemonic: format
First
I
Second
of words
XMRA

$2Fm

m

1

II

01057
01058
01059
01060

242 HITACHI

230
2F3

033B
035C

*
*

LA!
XMRA

$0
$3

Number.of
executl.on
cycles
1

RAM Address Instruction

XSPX
XSPX

I

Format

(Exchange Y and SPX)

II

Status

No effect

XSPX

I

Operation

IJ

II
X~~

SPX

DescriPtionl1
Exchanges the contents of X register with those of SPX register.

Address format and the number of execution cycles
Address format

I Operand
Mnemonic I format

$001

XSPX

I

Example

01123
01124
01125
01126
01127
01128

Instruction word
First
I
Second

Number
of words

Number.of
execut~on
cycles

1

1

I
I

I

II

226
001
OFO
227
210

0387
0388
0389
038A
038B

*

KISTATUS

LXI
XSPX
LWI
LXI
LYI

$6
$0
$7
$0

;X=6
;SPX
;W=O
; Spx=7
;Y=O

HITACHI 243

-RAM Address Instruction

XSPXY
XSPXY

I

Format

(Exchange X and SPX, Y·and SPY)

II

I

No effect

XSPXY

I

Operation

II

Status

II
X~

SPX

Y~

SPY

DescriPtionl1
Exchanges the contents of X register with those of SPX register,
and the contents of Y register with those of SPY register
simultaneously.

Address format and the number of execution cycles
Address format

Operand
Mnemonic: format
XSPXY

I

Example

I
I
I

Instruction word
Second
First
I

Number
of words

Number ,of
executlon
cycles

I
I
I

1

1

$003

II
LXI
XSPX
LXI
LYI
XSPY
LYI
XSPXY
XSPXY

244 HITACHI

$5
$0
$5
$0
;X=5, Y=5
;X=O, Y=O

RAM Address Instruction

XSpy
XSpy (Exchange Y and SPY)

I

Format

I

II

Status

No effect

XSPY

I

Operation

II

II
Y~SPY

Description

IJ
Exchanges the contents of Y register with those of SPY register.

Address format and the number of execution cycles
Address format

Mnemonic:
XSPY

I

Example

Operand
format

I

Instruction word
Second
First
I
$002

I
I

I
I

I

Number
of words

Number.of
execut~on
cycles

1

1

II
-

00987
00988
00989
00990
00991
00992
00993
00994

225
001
OFO
224
210
002
210

031D
031E
031F
0320
0321
0322
0323

*

LXI
XSPX
LWI
LXI
LYI
XSPY
LYI

$5
$0
$4
$0

;X=5
;W=O
;SPX=4
;Y=O

$0

;SPY=O

HITACHI 245

YNEI (Y Not Equal to Innnediate)

I

Format

I

II

Operation

II

NZ of (Y - i)

YNEI i

I

Status

Y=l

ST=O

Y~i

ST=l

IJ
Y", i

DescriPtionl1

Compares the contents of Y register to 4-bit innnediate data
(i3-0)'

Address format and the number of execution, cycles
Address format

Operand
Mnemonic: format
YNEI

I

Example

I
I
I

Instruction word
Second
First
I

Number
of words

Number .of
execut~on
cycles

1

1

I

i

$07i

I
I

II

01203
01204
01205
01206

246 MIJACHI

07A
ICE

03CD
03CE

*
*

YNEI
CAL

$A
OSERROR

7.

APPLICATIONS
Note that the circuits and programs shown in this item are example.

Please

examine them on your application carefully.

7.1

Example of Subroutine Program
Example of subroutine program much used in the HMCS400 series is shown in

this item.

Subroutine call is effective only when ST is "1".

As for sub-

routine 1 to 6, the following preconditions are applied.
(1) The locations from $030 to $06F of RAM are used as data area.
(2) The digits 4 to 15 of data area hold data.
(3) The locations from $020 to $02F of RAM (Memory Register MRO to MR15 are

used to save the register contents during interrupt service.
(4) A'

,

B' , SPX' , Spy', X'. y'. and W' show save area of A, B, SPX, Spy, X,

Y, and W during interrupt service.

Carry (CA) and Status (ST) save and

return automatically.
(5) On the program to be interrupted, if writing a value into W, the same value
is to be written into the location $020 (W"=MRO).
Address

~
4 bits
Upper
6 bits
$00

$01

RAM memory map
F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

~ ~ ~~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ .~ I~ Unusable ~ :~ ~ .~ ~ ~ i~ ~

$02

A'

$03

MSD

B' SPX' Spy' X'

y'

WIt

W'

LSD

$04
Data area

$05
$06

MSD

LSD

$07

Fig. 7-1

RAM Memory Map

HITACHI 247

7.1.1

RAMC1ear

RAM is not initialized by reset function.
. with progr"am when initializing RAM.

Therefore user initializes RAM

Subroutine which clears RAM address from $030 to $03F is shown in Fig. 7-2.

(Label)

(OP)

(operand)

LWI

$0

SBO
SFO

LXI

$3

LXI

$0

CL

LWIIY

$0

BR

CL

RTN

(Note)
$0

$p into W register and $Q into X
register, and performs subroutine

~M

Y+l--+Y

call for SFO at ST=l.

YoIdJ
y=O

When clearing $PQO to $PQF, loads

(Op)

(Operand)

LWI

$P

LXI

$Q
SFO

CALL

Fig. 7-2 RAM Clear Subroutine

7.1.2 RAM Data Transfer
The subroutine shown in Fig. 7-3 transfers the data of $OJO - $03F to $040 $04F
. (Label)

(OP)

(Operand)

CB

LWI

$0

VD

LXI

$4

XSPX
LXI

·Specifies receiving
L----,.-----' area

CF

LYI

TR

LAMX

LMAIYX
BR

$3
$0

. TR

RTN

~---'r----"

Specifies sending
area

(Note)

When transfering $RPO - $RPF to
$RQO -'$RQF, loads R into W
register, $Q into SPX register
and $P into X register. and
performs subroutine call for CF

M-+A

(X=$3)

at ST=l.

X+-+SPX
(OP)
A-+M
Y+l-+Y
X+-+SPX

(X=$4)

(Operand)

LWI

$R

LXI

$Q

XSPX
LXI
CALL

$P
CF

Fig. 7-3 RAM Data Transfer Subroutine

HITACHI 249

7.1.3

RAM Data Exchange

The subroutine shown in Fig. 7-4 exchanges the data of $03D to $03F with that
of $040 - $04F.

(Label)

(OP)

(Operand)

CHB

LWI

$0

CHF

LXI

$5

XSPX
LXI

$3

CHD

LYI

$0

EX

LAMX
XMAX

LMAIY

BR

EX

RTN

(Note)

When exchanging the data of
$RPO - $RPF with .that of $RQO $RQF, loads $p into X register

X+-+SPX

and $Q into SPX register, and
performs subroutine call for CHD
at ST=I.

A~M

X+-+SPX

(OP)

(Operand)

LWI

$R

A+M

LXI

$Q

Y+I-M

XSPX
LXI

$P

CALL

CHD

RTN

Fig, 7-4 . RAM Data Exchange Subroutine

250 HITACHI

7.1.4 Decimal Addition
The subroutine shown in Fig. 7-5 performs decimal addition between decimal
l2-digit data $034 - $03F and $044 - $04F, and stores the result in $034 - $04F.
(Label)

(OP)

(Operand)

LWI

$0

LXI

$3

XSPX
LXI

$4

REC
LYI
ADD

$4

LAMX

AMC
DAA

LMAIYX
BR

ADD

RTN
M---+A
(Note)

X-SPX

Carry data of the most significant
digit remaines in Carry (CA) in
this example.

Y+l---+Y
X~SPX

Y~O

Fig. 7-5 Decimal Addition Subroutine

HITACHI 251

7.1.5 Decimal Subtraction
The subroutine shown in Fig. 7-6 subtracts the decimal l2-digit data of $044 $04F from that of $034 - $03F, and stores the result in $034 - $03F.
(Label)

(OP)

LWI
LXI

(Operand)
$0
$3

XSPX

LXI

$4

SEC

LYI
SUB

$4

LAMX
SMC

DAS
LMAIYX
BR

SUB

RTN

(Note)

Borrow data of the most significant
digit remaines in Carry (CA) in
this example.

A-4 M
Y+l-4Y

XBSPX

Fig. 7-6 Decimal Subtraction Subroutine

2;)2 HITACHI

7.1.6

Interrupt Service
Carry (CA) and Status (ST) are saved and restored automatically.

SPX, Spy, X, Y, and W registers should be saved by software.

The A, B,

However, W must

be saved by the following process since it cannot be directly saved in memory
or a register.

If a value is written into W with the LWI instruction by a

program requiring an interrupt service, the same value as W must be written
to RAM area MRO; MRO is then saved in W' through the accumulator.

The value

of MRO should be the same as that of W during program execution.

In addition,

due to RAM retriction, the value of W must be 0 or 3.

Register save

(Label)
SAVE

(OP)
XMRA
LAB
XMRA
LASPX
XMRA
LASPY
XMRA
XSPX
LASPX
XMRA
LAY
XMRA
LAMR
XMRA

Refer to Fig. 7-7.

(Operand)
$F

(Comment)
A
SAVE

$E

B

SAVE

$D

SPX

SAVE

$C

SPY

SAVE

$B

X

SAVE

$A
$0
$9

Y

SAVE

W

SAVE

Y

LOAD

X

LOAD

SPY

LOAD

SPX

LOAD

B
A

LOAD
LOAD

RTN

Register return
LOAD

LOOPI
LOOP2

INEMD
BR
LWI
LMID
BR
LWI
LMID
XMRA

$3, $029
LOOP I
$3
$3, $020
LOOP2
$0
$0, $020
$A

LYA
XMRA

LXA
XSPXY
XMRA
LYA
XMRA

$B
$C
$D

LXA
XSPXY
XMRA

$E

LBA
XMRA

$F

RTN

Fig. 7-7

Interrupt Service Program
HITACHI 253

7.1.7 Display Tube Dynamic Drive
The program performs dynamic display of 9-digit BCD data, $037-$03F in
decimal.

The display tube has 7 display segments (excluding decimal point)

and is composed of9 digits in all (refer to Fig. 7-8).

Lower
Upper
FED

C

B

9

8

7

$03:-_-_-...I..,._-_-_--I..,..._-_-_-..L.
...._-_-_~-_-_~"T_-_.;.;:_--I."'"_-_-_-..L....._~-.....~-_-_-...
"T_-_-_-.....
T""_-_~_:r--t--'

[

R20
I

7 segment

RllMR21

~22

RIO

I

12

R23

Fig. 7-8 Configuration of Display Tube

Discrete I/O pins D7-D15 are used as digit control signals and data I/O
ports RI, R2 are used as segment signals.

The Y register addresses D port.

Segment display data are held in ROM pattern area and accessed by pattern
instructions.

This data is then loaded into registers and output from Rl, R2

ports.
For example, data "5" is stored at address $037 as a binary number
"(0101)2".

If this data is displayed in decimal, each segment signal

becomes R10=0, Rll=l, R12=l, R20=l, R2l=O, R22=1, and R23=1.
The above data is stored at address $115 of ROM pattern area as shown in
Table 7-1.

Table 7-1
Control
part

254 HITACHI

Contents of ROM Address $115

Data for segment display

r9

r8

r7

r6

r5

r4

r3

r2

rl

rO

1

0

1

1

0

I

0

1

1

0

(10)2 of the control part specifies that the contents of r7-rO are output
to Rl and R2 ports.
At this time, the pattern reference address should specify $115 as shown
in Table 7-2.

$5 is written into the accumulator, $1 in.to B register and $1

is specified as' direct data of the pattern instruction.
fixed.

The upper 2 bits are

Refer to pattern generation for additional information.

Fig. 7-9 shows allocation of ROM pattern area.
"0" in $110, and "I" in $111.

The segment data represents

In the same manner, segment data from 0 to 9

are represented from $110 to $119, respectively.
The flowchart for the display tube dynamic drive routine is shown in Fig.
7-10.

Fig. 7-11 and Fig. 7-12 show the program listing and timing chart,

respectively.

HITACHI 255

Table 7-2 Pattern Reference Address
B register
Fixed

01 0

Address

Accumulator

Direct

oI

0

Control
part
address

I0 I1

B3

B2

Bl

BO

A3

A2

Al

Ao

0

0

0

1

0

1

0

1

Display
character

Data for segment display

$110

1

o

$111

o

1

1

2

o

3

o

4

o

5

1

6

o

7

1

8

o

9

$119

Fig. 7-9 Allocation of ROM Pattern Area

256 HITACHI

M~A

Pattern
instruction
(Note 1)

T
'"'
.a

1 ~ D(Y)

.....00

(Note 2)

1

o ~ D(Y)

...1

Y+1~

Y

y"O

y=o

(Note 1)

The latter half of blanking time.

(Note 2)

Lighting time.

(Note 3)

The first half of blanking time.

*

Adjust the time by inserting appropreate process in (Note 1 '" 3).
Retain W, X, Y registers and status.

Fig. 7-10 Flowchart of Display Tube Dynamic Drive

HITACHI 257

(Label)

(OP)

(Operand)
$0
$3
$1

START

LWI
LXI
LBI
LYI

TOP

LAM

P

(ColIDI\en t)

$7
$1

I Note 1 I
Light

SED

I Note 2 I
RED
Light out

IY

I Note 3 I
BR
BR

Fig. 7-11

TOP
START

Program Listing of Display Tube Dynamic Drive

Rl

R2

f - - - Blanking

Fig. 7-12 Timing Chart

258 HITACHI

Light pulse

7.1.8 Keyboad Scan

1Note 21

This program is used by calling from

of display tube dynamic

drive.
Fig. 7-13 is a keyboad scan routine (9 x4) composed of key timing signal of
D7 '" DlS pins and input of RO port.

Key board

I

D7

1

-!

~

+

t
DIS

The timing of D7 '" DIS has already
specified in the display tube
dynamic routine.

(Y register)

R90 '" R93

(Label)

(OP)

KEY SCAN

LAR

(Operand)

(Comment)

$9

The first INPUT

$9

The second INPUT

YNEI

$0

Compares

BR

KEY RET

Not the same key

ALEI

$0

BR
XSPY

KEY RET

No input key

JOB

Goes processing routine
(JOB) having key in Y
and A registers

XSPY
LYA
LAR

SYY

Lights out the display

RED
Y~O

BRL

KEYRET
A:;;O

(Note)

XSPY
RTN

Returnes to dynamic
display

This program inputs data twice successively and compares then to keep
from keyboard chattering. If two inputs agree, key is loaded and the
program jumps to processing routine (JOB). Return to display tube
routine by RTN instruction at the end of JOB because return address
to display tube routine remains loaded in the stack if as it is.
Retain W, X, Y registers and Status in the JOB routine.

Fig. 7-13 Keyboard Scan Routine

. HITACHI 259
---._----_._--

.. _-

---------------..

~~

7.1.9 Timer A Application Example
Timer A is used as follows.

Its logical flowchart is shown in Fig. 7-17.

(1) Value is set in Timer Mode Register A (TMA).
Timer Mode Register A is a 3-bit write-only register located at address
$008 of RAM.
Prescaler divide ratio is determined by contents of the register and
generates Timer A clock pulse.

Timer Mode Register A is 0 during MCU

reset.
(2) Interrupt is initiated when an interrupt request occurs.
First, reset Timer A Interrupt Request Flag (IFTA) located in bit 2 of
$001.

Then set or reset Timer A Interrupt Mask (IMTA) located in bit 3

of $001.

Set or reset Interrupt Enable Flag (liE).

IMTA is set to "1" and liE to "0" during MCU reset.
These operations determine if the system will be interrupted or not after
Timer A interrupt request.
(3) Timer Counter A (TCA) starts to count clock pulses generated at or after

TMA setting.

TCA is $00 during MCU reset.

(4) The counter generates an overflow at the 256th pulse, and then starts to
c.ount from $00.
(5) Overflow is latched in Timer A Interrupt Flag (IFTA) and the process is
then performed according to the initial value.
of RAM $001.

IFTA is located in bit 2

This flag is reset by software.

(Note) The number of pulse counts immediately after setting Timer Mode
Register A to the first overflow is indefinite.
The followings are example of a clock using Timer A.
minutes and seconds.

The clock shows

Data of $030-$033 shows lower digits and upper digits

of seconds and minutes.

Refer to Fig. 7-14.

The clock is incremented every

second and figures are counted upward as in a normal clock.
The clock returns "0" after 59' 59", and the continues to count upwards.
The flowchart is shown in Fig. 7-15.

260 HITACHI

Address

~
4 bits

Upper
6 bits

$03

3

2

1

0

minute
(upper
digits)

minute
(lower
digits}

second
(upper
digits}

second
(lower
digits}

$04

Fig. 7-14 RAM Map of Clock using Timer A
When using a 4.19MHz crystal resonator as the oscillator, the system clock
becomes 525kHz.

Clock pulse frequency is precisely set at 256Hz by setting

the prescaler divide ratio to 1/2048.

Consequently, the Timer A Interrupt

Request Flag is set every second in this state.
An example of the program is shown in Fig. 7-16.

HITACHI 261

tv

0-

r-J

::t

~

()

-

(Note 5)

(Note 1)

::t

$O~M
Y+l~Y

(Note 2)
(Note 3)
(Note 4)

(Note 1)

RAM clear subroutine.

(Note 2)

Sets prescaler divide
ratio to 1/2048.

(Note 3)

Resets Timer A interrupt mask.

(Note 4)

Sets interrupt enable

(Note 5)

flag.
Save, return subroutine

II

II

Fig. 7-15 Flowchart of Main Routine

/'

~

1 )r------i

CA=l

0)
Fig. 7-16

Flowchart of Timer Subroutine

(Label)
Main routine

TIMER

Timer subroutine

SECH

MINH

(OP)
CALL
LAI
LMAD
REMD
SEMD
NOP
JMPL

(Operand)
RAMCLR
$0
$008
$3, $0001
$0, $000

CALL
LWI
LXI
LYI
LAM
REC
AI
DAA
LMAIY
TC
BR
BR

SAVE
$0
$3
$0

LAM
Al
ALEI
BR
LMIIY
LAM
REC
AI
DAA
LMAIY
TC
BR
BR
LAM
AI
ALEI
BR

DISP
RET

Sets prescaler divide ratio.
Resets timer interrupt mask.
Sets interrupt enable flag.

TIMER

Calls save routine.

$1

SECH
RET

$1
$5
DISP
$0
$1

MINH
RET

BR

$1
$5
DISP
$0, $033
RET

LMA
CALL
REMD

LOAD
$2, $001

U1ID

(Corrunent)
Calls RAM clear subroutine.

Calls return routine.
Resets Timer A interrupt
flag.

RTNI

Fig. 7-17

Program Listing of Timer A Application

HITACHI 263

7.1.10 Timer B Application Example
'Timer B .is used c ·as follows when using clock as an input.
and program listing are shown in Fig. 7-18 and

7-l9~

Its flowchart

respectively.

(1) Timer B Interrupt Mask (IMTB) is set to inhibit interrupts during setting
of each mode register.

IMTB exists is located in 1 of RAM $002.

It is

set to "1", and Interrupt Enable Flag to "0" during MCU reset.
(2) Setting: of Timer Mode Register B
4-bit Timer Mode register B (TMB) is located at $009 of RAM.

First, it

is determined whether or not the auto reload function is used by setting
or resetting bit 3.
Then the prescaler divide ratio and clock input source are specified.

In

the case of an external event input, specify bit 0, 1 and 2 according to
the pres caler divide ratio.

The Timer Mode Register B is not set bit by

bit, but the set value is loaded into RAM at one time.

This register is

set to "0000" during MCU reset.
(3) Initial value is set in lower bits (TLRO-3) of reload register located in
$OOA of RAM.
Initial value is set in upper bit.s (TLR4-7) of reload register located in
$OOB of RAM.

The value of reload register is $00 during MCU reset.

(4) Timer B Interrupt Request Flag (IFTB) is reset.

IFTB is located in bit 0

of RAM $002.
Timer B Interrupt Mask (IMTB) is reset.
Interrupt Enable Flag (liE) is set.
(5) Overflow generated from Timer Counter B is latched into Timer B Interrupt
Request Flag (IFTB) and the process is then performed according to
initialization of interrupt.

IFTB is located in bit 0 of RAM $002 and is

reset only by software.
The following sentences describes an example of setting the interrupt
cycle.

Suppose a 50.176 (msec) interrupt cycle is generated by using a

4MHz crystal.

8 frequency divider generates a 500kHz system clock, and

a 1.024 (msec) pres caler output cycle is obtained by using pres caler
divide ratio 1/512.

If the value 207 is loaded into the reload register,
1.024 x (256-207)-50.176 (msec).

Because (207)10-(11001111)2' set (1111)2=$F in lower digits of the reload
register and (1100)2=$C in upper digits.

264 HITAOHI

The flowchart and program listing are shown in Fig. 7-18 and 7-19,
respectively.

Note that the process time of this subroutine does not

exceed 50 msec.
(6) The contents of Timer Counter are read in twice; the lower 4 bits are
read immediately after reading the upper 4 bits because the lower 4 bits
are latched simultaneously when the upper 4 bits are read.

HITACHI 265

Sets Timer B interrupt Mask.
Transfers the value to Timer B Mode Register.
Transfers the value to Lower Digits of Reload Register.
Transfers the Value to Upper Digits of Reload Register.
Resets Timer B Interrupt Request Flat.
Resets Timer B Interrupt Mask.
Sets Interrupt Enable Flag.

Fig. 7-18 Flowchart of Timer B Application Example

(Label)
Main routine

TMB

(OP)
SEMD
LMID

(Operand)
$1, $002
$9, $009

LMID

$F, $010

LMID

$C, $011

REMD

$0, $002

REMD

$1, $002
$0, $000

SEMD
NOP
JMPL

(Comment)
Sets Timer B Interrupt Mask.
Transfers the value to Timer B
Mode register.
Transfers the value to lower
digits of reload register.
Transfers the value to upper
digits of reload register.
Resets Timer B Interrupt Request
Flag.
Resets Timer B Interrupt Mask.
Sets Interrupt Enable Flag.

TMB

Timer B interrupt routine
CALL

SAVE

Calls save routine.

IProcessing I
CALL
REMD

LOAD
$0, $002

Calls return routine.
Resets interrupt request flag.

RTNI

Fig. 7-19 Program Listing of Timer B Application

266· HITACHI

7.1.11

Serial Interface Application Example

Serial interface is used as follows.
(1) Data transfer (pres caler divide ratio: 1/128)
Fig. 7-20 shows the data transfer routine.

The program listing is shown

in Fig. 7-21.

Sets serial interface interrupt mask.
Transfers the contents of RAM to accumulator.
Transfers the contents of accumulator to lower bits
of serial data register.
Transfers the contents of RAM to accumulator.
Transfers the contents of accumulator to upper bits of
serial data register.
Sets R42/S0 pin as SO output pin.
Internal clock specifies prescaler divide ratio to 1/128.
Resets serial interface interrupt flag.
Resets serial interface interrupt mask.
Sets interrupt enable flag.
Serial interface start instruction

(

END)

Fig. 7-20 Data Transfer Routine
After STS instruction, 8-bit data is transferred from R42/S0 pin synchronously with pulse output from R40/sCK pin.
vector occurs.

IFS is then set and interrupt

If the program does not need to jump to an interrupt routine,

set IMS or reset liE before executing STS instruction.

HITACHI 267

Main routine

(OP)

(Operand)

SEMD

$1, $003

LAMD

$030

LMAD

$006

Sets serial interface interrupt mask.
Transfers the contents of RAM location
$030 to accumulator.
Transfers the contents of accumulator to

SRL.
Transfers the contents of RAM location
$031 to accumulator.
Transfers the contents of accumulator
to SRU.

LAMD

$031

LMAD

$007

LMID

$1, $004

Loads the value of $1 into PMR (SO).

LMID

$A, $005

Loads the value of $A into SMR.

REMD

$0, $003

Resets IFS.

REMD

$1, $003

Resets IMS.

SEMD

$0, $000

Sets liE.

STS

Starts serial interface operation.

Fig. 7-21
(2)

(Comment)

Program Listing of Data Transfer

Data reception (external clock)
Fig. 7-22 and Fig. 7-23 are flowchart and program listing of data
reception respectively.

Sets serial interface interrupt mask.
Programs R4l/s1 pin as SI pin.
Specifies external clock mode.
Resets serial interface interrupt flag.
Resets serial interface interrupt mask.
Sets interrupt enable flag.
Serial interface start instruction.

(

END)

Fig. 7-22
268 HITACHI

Flowchart of Data Reception

C'Interrup~
service..!
I
Error:,check
rout ... ne
I
I Save routine

I
I

I
Processing

I

Confirms error occurrence.

I

Saves registers.

J

Interrupt service.

I
~eturn routine]
I

I

0

-4

(

RTN

IFS

I

Restores registers.
Resets serial interface interrupt flag.

I
)

Fig. 7-22 Flowchart of Data Reception
Main routine
REPEAT

(OP)

(Operand)

SEMI>

$1, $003

Sets IMS.

LMID

$2, $004

Loads $2 into PMR. (S1)

LMID

$F, $005

Loads $F into SMR. (external clock)

REMI>

$0, $003

Resets IFS.

REMD

$1, $003

Resets IMS.

SEMI>

$0, $000

STS

(Comment)

Sets lIE.
Starts serial interface operation.

Interrupt routine
SEMI>

$1, $003

Sets IMS.

REMI>

$0, $003

Resets IFS.

LMID

$F, $005

Loads $F into SMR.

TMD

$0, $003

Tests IFS.

BRL

REPEAT

CALL

SAVE
IProcessing

CALL

LOAD

Error check

Calls save routine.

I

Interrupt service.
Calls return routine.

RTNI

Fig. 7-23 Program Listing of Data Reception

HITACHI 269

7.2 ALU (Arithmetic Logic Unit) and Decimal Adjust Instruction
ALU basically consists of a binary adder.

The block diagram of ALU is

shown in Fig. 7-24.
52 bus

51 bus Y

AND (Micro inst.)
OR (Micro ins t. )

CA (Carry)
+1 (Micro inst.)

Binary Adder

EOR (Micro inst.)
Result

OVF (Overflow)

Fig. 7-24 ALU Block Diagram
When the addition of two or more digits is performed, OVF (Carry) is
latched in CA and is put into the ALUat calculation. of the next digit.
Subtraction is performed .by using the inverse input on the bus 52.
is, calculation 51 - 52 is performed by the operation: 51 + 52 + 1.

That
But in

this case, OVF means no borrow.
When the subtraction of two or more digits is performed, OVF (that is,
borrow) should be latched in CA.

In this case, the second calculation is

performed by the operation: 51 + 52 + CA.
The following example shows the addition of l2-bit data.

(159)H + (26A)H = (3C3)H

+)

0001

0101

1001

(159)H

0010

OllO

1010

(26A)H

OlOll

1O0ll

DOll
+)

CA:!:,
DOll

CA

CA~

~

0
(3C3)H

"'(DOOll

"'@llOO

(3C3)H - (159)H = (26A)H

+)
+)

DOll

llOO

DOll

(3C3)H

lll0

1010

0110

(159)H

10001

10110
CA

01001
CA

CA:!::.
0010

(NOTE)

mOll0

~

"@1010

H means hexa-decimal number.

270 HITACHI

---.-

~

1
(26A)H

~o

Decimal Calculation
Decimal addition/subtraction using binary-coded decimal (BCD) is performed by
the combination of binary addition/subtraction and decimal adjust instruction.
The decimal adjust instruction performs the adjustment of Accumulator and
CA according to their contents.
Decimal addition
Aii:10 or CA=l
One digit

Binary addition
Decimal Adjust (Addition)

A+

6~A

l~C(CA)

A<10 and CA=O
A,CA: unchanged

Decimal subtraction

Aii:10 or CA=O
One digit

Binary subtraction
Decimal Adjust (Subtraction)

A + 10+A
O+CA
A<10 and CA=l
A,CA: unchanged

For example,
169+245=417
0001

0110

1001

169

+)

0010

0100

1000

248

+)

00011
CA

01010
CA

10001
CA

Binary addition

~O

00100
+)

Decimal Adjust
(Addition)

0110
417

0100
417-159=243
0100
+)

0001

0111

417
169

1110

1001

0110

10010
CA
+)

01010
CA

01101
CA

10010
+)

~1

@1101
Decimal Adjust
(Substraction)

1010
10010

Binary subtraction

1000

248

HITAOHI271

7.3 Application of Logical Operation
Examples of bit manipulation of the data: using logical operation
instruction are as follows.
R~:se'ts the least significant bit of the data latched in Rl port.

(1)

fi=g. 7-25 is the flowchart.

Sets $E into.memory.
Transfers the contents of Rl.port (latch) to
accumulator.
Performs logical AND operation between memory and
accumulator, and transfers the result to accumulator.
Transfers the contents of accumulator to Rl port
(latch).

If

Rl=$5,
The contents of memory

1110

The contents of accumulator

0101
0100
' - - - Only the least significant
bit is reset

Fig. 7-25 Flowchart Using Logical and Operation
(2)

Sets the least significant bit of the data latched in Rl port.
Fig. 7-26 is the flowchart.

Sets $1 into memory.
Transfer~

the contents of Rl port (latch) to
accumulator.
Performs logical OR operation between memory and
accumulator, and transfers the result to accumulator.
Transfers the contents of accumulator Rl port
(latch) •

*

If

Rl=$4
The contents of memory

0001

The contents of accumulator

0100

MUA

0101
'--- only the least significant bit
is set

Fig. 7-26 Flowchart Using Logical OR Operation
272M.YACHI

(3)

Tests the most significant bit of the data latched in Rl port.
Fig. 7-27 is the flowchart.

Loads $8 into memory.
Transfers the contents of Rl port (latch) to
accumulator.
Performs logical AND operation between memory
and accumulator.

(
If

END

)

Rl=$5,
The contents of memory

1000

The contents of accumulator

OlDl

mA

0000

ST (status)

~

0

Consequently program does not branch because ST=O.
jThe value of the most significant bit of Rl port is

o.

Fig. 7-27 Flowchart Using Logical and Operation
7.4 Checking Operation Frequency
Connecting TEST pin to GND causes D6 pin to output pulse.
pin is eight times as that of OSCl pin.

The cycle of the D6

Connect external pull-down resistor if

I/O circuit type of D6 pin is not "no pull-down MOS" S shown in Fig. 7-28.
The method in Fig. 7-28 may be inconvenient after the MCU has been
built into a system since it operates in test mode.

HITACHI 273

VCC

f'
Clock

RESET

D6
lOk0

MCU

7fr

:Jr

TE'ST

Fig. 7-28 Recommended Wiring to Check Operation Frequency
7.5 Watchdog Timer - System burst preventing circuitA simple method of implementing the watchdog timer which is generally
known as a means of recovery from a system problem is described below.

(1) Basic circuit
Fig. 7-29 shows the basic circuit of the watchdog timer.

Microcomputer
Port

Pulse

RESET Circuit Multi-vibrator

Fig. 7-29 Basic Circuit of Watchdog Timer
(2) Operation outline
(a) System software should be designed to generate a pulse through the
port within a predetermined period (TVZl + VFl
Vout=GND if VeeVZ2 + VF2
Vout=GND if Vee1.6V

Vout~
Fig. 7-36 Manual Reset Timing

HITACHI 277

7.8 Serial Data Transfer between HMCS402/404/408 and Other MPUs
The routine shown in Fig. 7-37 describes serial data transmission/
reception between the HMCS402/404/408 and other MPUs and storing the data in
RAM.

Hardware configuration available for this routine is shown in Fig. 7-38.

HMCS402/404/408

YES

When READY/ERROR signal
is transmitted within
certain time from other
MPU. the system judges that
error occurs during transmission and returns to

SRL ...... A

STS instruc tion
(receive 1 byte)

A

initialization of the main

...... M

SRU --. A
A

routine and waits for the

--. M

next READY signal.

Interrupt
routine

Fig. 7-37 Serial Data Transfer Routine

SCK

(R40)

CLOCK

SI

(R4l)

SO

SO

(R42)

READY/
ERROR

(R43)

HMCS402/404/408

. SI

-------------

READY/ERROR
MPU

Fig. 7-38 Example of Connection Between HMCS402/404/408 and Other MPU

278 HITACHI

7.9 Reversing a String of Transmit/Receive Data in a Serial Interface (LSB-MSB)
Serial interface for the HMCS402/404/408 is shown in Fig. 7-39.

Data is

input to the serial data register LSB first through the SI pin synchronously
with the rising edge of the transfer clock, while data is output from the
serial data register LSB first synchronously with the falling edge of the
transfer clock.
When serial data transfer is performed between the HMCS402/404/408 and
other MPUs, the string of data in the serial data register must be reversed
(LSB - MSB) if their data formats are different.

Programs for data string

conversion of the serial data register are shown in Fig. 7-40 and described
as follows.

INTERNAL BUS LINE

LSB I----(r~ SO

SI

SRL
SERIAL DATA REGISTER

Fig. 7-39 Serial Interface for the HMCS402/404/408
When MSB is transmitted first from another MPU to the HMCS402/404/408, the
data string input into the serial data register can be reversed using the
pattern instruction.

Pattern data is provided by the DC control instruction.

First, the order of bits in the serial data register are reversed by conversion
program (a), storing the data in memory (MD).

Next, by executing program (b),

this rearranged data is loaded from memory to the SDR in the correct bit
significance order.

The pattern data provided for ROM in the above case is

shown in Fig. 7-41.

HITAOHI279

SRL ($006)

SRU ($007)

: :

Other MPU -ILSB

Ip

The contents of A are stored in memory.
Processes the real SRU in the same way as

 )

Used

bitO

Area for storing pin No. of D port outputting High level to light
the FL display tube.

Decimal number to be displayed is set in GRID2, GRID3, GRID4, GRIDS, and
GRID7 in terms of BCD. "A" will be set in them to light out. As for other
area, to light, set the corresponding bit, and to light off, reset it.

Fig. 7-50 RAM Map for FL Display

HITACHI 287

Program Listing (1)
•••••••••••••••••••••••••••••••••••••••••

•
•

•
•
•

TIMER-B INTERRUPT ROUTIN

•

•••••••••••••••••••••••••••••••••••••••••
REGISTER SAVE
IFTB,$002

REMD

••••••••••••••••••••••••••••••••••••••••
LAST GRID RESET

••••••••••••••••••••••••••••••••••••••••
LAMD
LYA
RED

GRIDNO

•••••••••••••••••••••••••••••••••••••••
FL DRIVE

•••••••••••••••••••••••••••••••••••••••
Al
BR
HR
FLDRIVEI LAI
FLDRIVE2 LMAD
LBI
P

$1

FLDHI VEl
FLDRI \'E2
$9

GHIDNO
$F
$F

A:

FL

DATA AIU:AX

H 0 : COO.: I:

LWI
LXI
LYA
DB
LBI
LAM
BR
P
BR

288 HITACHI

$0
$C

$£
FLDHIV£3
$F
FLDRIVE~

lilT

HEO

Program Listing (2)
FLDRIVE2 IY
LBA
LAM
FLDRIVEs LXI
TM

$D

$0

SEC
BR

FLDRIVE~

REC
FLDRIVE~

ROTL
LRA

$0

LRB

$1

•••••••••••••••••••••••••••••••••••••••••

•

GRID ON

•••••••••••••••••••••••••••••••••••••••••
LAMD

GRIDNO

LYA
SED

REGISTER RESTORE

RTNI

HITACHI 289

Program Listing (3) Pattern area
•••••••••••••••••••••••••••••••••••••••••••••••••••••

•

SEGMENT PATTERN DATA

•

•••••••••••••••••••••••••••••••••••••••••••••••••••••
DRG

$FEO

DC

$1F6

DC

$160

0

DC

$1D5

2

DC

$1F1

8

DC

$168

+

DC

$1B8

DC

$187

DC

$1EO

6

DC

$lF7

DC

$1E8

9

DC

$100

BLANK

DC

$000

UNDEFINDED

DC

$000

UNDEFINDED

DC

$000

UNDEFINDED

DC

$000

UNDEFINDED

DC

$000

UNDEFINDED

8

•••••••••••••••••••••••••••••••••••••••••••••••••••••

•

GRID DATA ADDRESS PATTERN AREA

•

•••••••••••••••••••••••••••••••••••••••••••••••••••••

290 HITACHI

ORG

$FF9

DC

$109

GRID7

DC

$117

GRID6

DC

$106

GRID5

DC

$105

GRID+

DC

$10+

GRIDS

DC

$108

GRIDS

DC

$111

GRID1

FLOURESCENT DISPLAY
FUTABA

iI

8-MT-06ZYK

:11st2ndlI

~----~----T----r---r---~----r----~--------,

I

W1
~
VCC
+

CD
TDK

GND

SUN

I

i ON

I MON ,TUE:

1-,1! -,1:•:

I
nl

I

'-,

I

I

OFF:

'-IAM
(i)F
I

I,
I

WED

THU

I

I

:

I
Inln

i

-II
I • I

I
I

l:

: FRI

SAT

I

I
I

abc

0 (]) @

(2)

CH
ERROR
END

I

d

f

e

:

g

h

7G

@ @ @ @ ~_uG)

6G

SG 4G 3G

®

2G

IG

@ @ @ @ @

CD

Ij

*

C2

i

C3

@@@@®0~~

@

~3~2~1~0~3~2~I~O

L-....J(.;:;\v RAI/Vdisp
'i!!:I

®tD00CDt§@
DIS Dl4 D13 Dl2 Dn DIO D9

CC
\

HMCS402/404/408

L-._-II® GND

VCC

Vcc

1

t:o lC6

RESET

TEST

R62 R6l R60

RS3

RS2

@

®

@@@

@

@

...

Lf

RSI RSO

. ... .. .
©

@

7/18/19/
4/15/16/
1/12/13/

0/1. II. /

R2

1:

J,.

FUNCTION KEY

~

()

-

1:
I '.)

-0

I

I

I

I
I
I

lJ=ll~~ __L=-__ L=.:.LL_Lb-1_L1-d_L _______ J

Co~:~~ter
0
--1~

asc 1

C~
«

MCU

Fig. 8-2 Design of Oscillation
Circuit Board (I)

MCU

Fig. 8-3 Example of Circuit Causing
Trouble in Oscillation

(4) When operating MCU using an external clock, be careful of a long drop
from the external clock to the ascI pin.

Induction of noise on the aSCI

pin from signal lines or power supply lines can lead to malfunction of
the MCU.

302 HITACHI

Refer to Fig. 8-4.

osq
MCU

Fig. 8-4
8.5

Design of Oscillation Circuit Board (II)

Automatic Paging Facility of Cross Assembler for the HMCS400 Series
The following cross assemblers for the HMCS400 series have an automatic

paging facility.
(1) The S400XAS2F cross assembler for the H68SD operates under FDOS-III or
FDOS-II with its host computer Hitachi development system H68SD5A, H68SD5
or H68SD20.
(2) The S400XAS6F cross assembler for the H680SD200 operates under CP/M-68K*
with its host computer Hitachi development system H68SD200.
(3) The S400MDSIF and S400MDS2F cross assemblers for MDS operate under ISIS-II
or CP/M* with their host computer Intel development system MDS-220/230.
Owing to the automatic paging facility, programmers can use conditional
branch instructions for any size ROM without being concerned with page
(256 words/page) boundaries.

Two conditional branch instructions are

available for the HMCS400 series : BR and BRL.

The above cross assemblers

have a unique instruction which has no object code, i.e., BRS.

With the BRS

instruction, the object code is automatically converted to BR if the destination address is within the current page and to BRL if it is not within the
page.

With such object code generated, the mnemonic of the instruction in the

source statement remains "BRS".

* CP/M-68K

and CP/M are registered trademarks of Digital Research.

~

Within the page
(I-word
instruc tion)

BRS

BR

tl.on

Instruction

Out of the page
(2-word
instruction)
BRL

HITACHI 303

(4) When a BRS instruction appears, object code for BR is generated if the
destination address is within the current page and that of BRL if it is not
within the page.
(5) The BRS operand is a symbol name having a ROM address.

ST-NO

OBJECT

ADRS

oooni
00002
00003
00004

STATEMENTS

LBLI

EQU

LBL2

EQU

$100

BRS

LBL1·············

BRS

LBL2 •.•••••.•..•. @

0000

301
170

SOURCE

100

0001

00005
DOFF

300

00008
170

100

01FF

00011
00012

ORG

$FF

BRS

LBL2············· (])

ORG

$lFF
LBL2 ••...•..•••• @

*

00009
00010

BRS

*
302

0201

231

0202

BRS

00013
00014

CD

*

00006
00007

$1

00015
00016

LBL3

LAI

*

:1···········~

END

Fig. 8-5 Example of Automatic Paging

CD

Object code for the BR instruction is generated {f LBLI is in the
current page.

([) Object code for the BRL instruction is generated if LBL2 is not in the
current page.
([) Object code for the BR instruction is generated because BRS is on the
page boundary and LBL2 is in the following page.

(i)

GD

Object code for the BRL instruction is generated because BRS is on the
page boundary and LBL2 is not in the following page.
If the number of automatic paging operations exceeds 255, the assembler
outputs an error message and terminates the process.

In this case the

destination address of the BRS instruction is undefined.

304 HITACHI

8.6 Precautions for Port Mode Register (PMR) Setting
IFO and IFI (External Interrupt Request Flags) are set if R32/INTO and
R33/INTI programmed as INTO input pin, INTI input pin, respectively by
setting the bit 2 and 3 of PMR to 1 during R32/INTO and R33/INTI input
level LOW.

Thus, PMR should be specified as the external interrupt input

pin (INTO or INTI) only in external interrupt disable state.
IFI should be reset.

Then IFO or

Although PMR is set as external interrupt input during R32/INTO and
R33/lNTl input level high, IFO and IFI cannot be set.

External
interrupt

Notes for PMR setting
IFO is set if R32/INTO pin is programmed as INTO input pin
by setting bit 2 of PMR to 1 during R32/INTO input level low.
IFI is set if R33/INTI pin is programmed as INTI input pin
by setting bit 3 of PMR to 1 during R33/INTI input level low.

The following examples shows the programming example of PMR for INTO.
(Example 1) PMR is set in main routine

SEMD
LMID
REMD
REMD

IHO, $000
%0100, PMR
IFO, $000
IHO, $000

INTO MASK
R32-INT O
IFO RESET
INTO ENABLE

(Example 2) PMR is set in INTO interrupt routine
LMlD %0000, PMR
LMlD %0100, PMR
REMD IFO, $0000

R32- INT O
IFO RESET

HITACHI 305

9.

Difference between EPROM in-package type, EPROM on-package
type and Mask ROM type

~

EPROM in package

HD614P080S
HD614P0160S

HD4074008

Items

Typical instruction

1 ]1S

exection time

Power supply voltage
[V]

EPROM on package
HD614P180
HD40P4181

1. 33 ]1s

4.5 - 5.5

1. 33 ]1s/1 ]1S

4.5 - 5.5

4.5 - 5.5

ROM

8192 wordsxlO bits PROM

4096 wordsx10 bits (EPROM 2764)
8192 wordsx10 bits (EPROM 27128,27256)

RAM

512 digits X4 bits

576 digits x4 bits

576 digits X4 bits
992 digits X4 bits

NMOS Open drain

NMOS Open drain

PMOS Open drain

PMOS Open drain

I/O pin
circuit

Standard pins NMOS Open drain*l
High voltage
pins

Clock

PMOS Open drain*2

Crystal

0

0

generation Ceramic

0

0

0

-

-

-

Resistance

Package

Shrink type 64-pin dua1Shrink type 64-pin
in-line plastic package.
EPROM on package.
64-pin flat plastic package.
Shrink type 64-pin dualin-line ceramic package.
Type

DC-64S

Occupied area 18.8x57.3
High from
stand-off
(mm)

*1, *2

306 HITACHI

0

Typical 5V use

5.1
(max)

DP-64S
17 x58

42 pin EPROM on
package.

FP-64

DC-64SP

DC-42P

19.6x25.6

23 x57.3

19 x52.8

5.1

2.9

(max)

(max)

7.5 (max)
EPROM on-package

Mask ROM
HMCS402AC
HMCS402C
HMCS402CL

HMCS404AC
HMCS404C
HMCS404CL

1.33 us
2 lJS
4 lJS

1. 33 lJs
2 lJS
4 lJS

4.5 - 6
4
- 6
2.7 - 6

-

4.5
4
2.7

-

HMCS408AC
HMCS408C
HMCS408CL
1 lJS

2 lJS
4 lJS
4.5 - 6
3.5 - 6
2.5 - 6

6
6
6

HMCS4l2AC
HMCS4l2C
HMCS4l2CL

HMCS4l4AC
HMCS4l4C
HMCS4l4CL

1 Us
2 lJS
4 lJS
4.5 - 6
3.5 - 6
2.5 - 6

1 Us
2 lJS
4 Us
4.5 - 6
3.5 - 6
2.5 - 6

2048 wordsxlO bits

4096 wordsxlO bits

8192 wordsxlO bits

2048 wordsxlO bits

4096 wordsxlO bits

160 digits X4 bits

256 digits X4 bits

512 digitsX4 bits

160 digits x4 bits

160 digits x4 bits

Each pin selects "without pull-up MOS (NMOS open drain)",
"with pull-up MOS ll t or "CMOS".
Each pin selects "without pull-down MOS (PMOS open drain)"

.or "wi th pull-down MOS" .
0

0

0

0

0

0

0

0

0

-

-

-

HMCS402C

HMCS404C

Shrink type 64 pin dual-in-line plastic package.
64 pin flat plastic package.

DP-64S, FP-64

-

l7 x58, 19.4x25.6
5.1 (max) , 2.9 (max)

0

42 pin dual-in-line plastic package.
Shrink type 42 pin dual-in-line
plastic package.
DP-42, DP-42S
13.4X52.8, l4 x37.34
5.08 (max)

HITACHI 307

10.

EPROM IN PACKAGE TYPE SINGLE CHIP MICROCOMPUTER HD4074008
Under Development

10.1

Overview
The HD4074008 is a mass storage ZTAT microcomputer incorporating 8k words

of programmable ROM and 512 digits of RAM.

It is a CMOS 4-bit single-chip

microcomputer which is a member of the HMCS400 series microcomputers providing
the characteristics of high program productivity, high speed operation, and
low power dissipation.

(l) Features
o

Instruction Set Compatible with the HMCS402/404/408

o

8,192 words x 10 bits programmable ROM (Program spec. is compatible \with

o

512 digits x 4 bits RAM

the 27256 type)
o

58 I/O Lines Including 12 Large Current Pins (15mA), I/O Pin Circuit
Type; Open Drain with 5 Voltage use.

o

Two On-chip Timer/Counters

o

Clock Synchronous 8-bit Serial Interface

o

Five Interrupt Sources
External

2

Internal

3

o

Subroutine Stack

o

Two Low Power Dissipation Mode

Up to 16 levels including Interrupts
Standby Mode
Stop Mode
o

On-chip Oscillator
Crystal or Ceramic Filter (Externally drivable)

o

Minimum Instruction Cycle Time

o

Operation Mode

0.89~s

MCU Mode
PROM Mode
o

Package
64-Pin Shrink Type Plastic DIP
64-Pin Shrink Type Ceramic DIP with Window
64-Pin Flat Plastic Package

HITACHI 309

(2) Pin Arrangement (Top View)

!

0"
0"
Ou
0 ..
0·,
Roo ~
Ro.
Ro,
Ro,
R.o
R"
R"
Ru
R '0
R"
Rn
Rn
R40
R..
RJO
R,.

0.0
O.
O.
0,
O.
0,
O.
0,
0,
O.

0

r:'

osc,

OSC.
TEST
RESET
Ru
R"
R..
Roo
R"
Ru
R••
R..
R"
R"
R"
R,o

R32/i'N'fO

Rll/INT,

R,o
Rs>
Ru
R"
Roo
R.·
R02
R"

R'.J

R.2/S0
Roll/51

R.o/ID

v"

g
IX:

•

0

0

M

00

0

0

0

.; Q ,; .:; 0 .;

Ro.

0,
0,
O.
00
GNO

R.o
R"
R"
Ru

osc,
osc.
m'f
RESET
R"
R"
R"
RIO

Rn
Rn
R",
R..
RJO
R,·

R"
R"
Ro.

R,o

RIO
R"

R,.

R"

,r. ,r.

Ii

IX:

"

~

a: a:

in

,r.

~
ri

;;

~

a: a:

(FP-64)

(DP-64S)

(3) Block Diagram
PROM Mode

~cu

l

\fode

R. o/R.,/R.l/

Au/

Rlli

iNr. iNro

SCi( SI SO

R..

RESET TH'f OSC, OSC, VceGNO

11...------,

,-L-L-1---J.......,

R"
R"
R"

PROM

R~

8192X1Qb"

R"
R"
R"
R~

R"
R"
R"
R"

""""

R"
~

R"
R"
R"
R~

Mev
0,0, 0. Q,

Fig. 10-1
310 HITACHI

Block Diagram

Mode

PROM Mode

(4) Pin Function
Pin arrangement depending on the mode

OC-64S
OP-64S

PROM Mode

MCV Mode

Pin No.

FP-64

Symbol

I/O

Symbol
VCC

I/O

Pin No.

PROM Mode

MCV Mode

OC-64S
OP-64S

FP-64

Symbol

I/O

Symbol

I/O

1

59

011

I/O

33

27

R40/ SCK

I/O

04

I/O

2

60

012

I/O

34

28

R41/ S1

I/O

aS

I/O

3

61

013

I/O

35

29

R42/S0

I/O

06

I/O

4

62

D14

I/O

36

30

R43

I/O

07

I/O

5

63

015

[/0

37

31

R70

a

CE

I

6

64

ROO

a

Al

I

38

32

R71

a

OE

I

7

1

ROI

a

A2

I

39

33

R72

a

8

2

R02

a

A3

I

40

34

R73

a

9

3

Raj

a

A4

I

41

35

R80

a

10

4

RIO

I/O

A5

I

42

36

R81

a

11

5

Rll

I/O

A6

I

43

37

R82

a

12

6

R12

I/O

A7

I

44

38

R83

a

13

7

R13

I/O

A8

I

45

39

R90

I

Vpp

14

8

R20

I/O

AO

I

46

40

R91

I

A9

I

15

9

R21

I/O

AlO

I

47

41

R92

I

MO

I

16

10

R22

I/O

All

I

48

42

R93

I

M1

I

17

11

R23

I/O

Al2

I

49

43

RESET

I

RESET

I

18

12

RAO

I

50

44

TEST

I

TEST

I

19

13

RA1

I

51

45

aSCI

I

20

14

R30

I/O

AD

I

52

46

OSC2

a

A14

I

21

15

R31

I/O

53

47

GNO

I/O

GNO

22

16

R32/ INTO

I/O

54

48

00

I/O

00

I/O

23

17

R33/ INT 1

I/O

55

49

01

I/O

01

I/O

24

18

R50

I/O

56

50

02

I/O

02

I/O

25

19

R51

I/O

57

51

D3

I/O

03

I/O

26

20

R52

I/O

58

52

04

I/O

27

21

R53

I/O

59

53

05

I/O

28

22

R60

a

60

54

06

I/O

29

23

R6l

a

61

55

07

I/O

30

24

R62

a

62

56

08

I/O

31

25

R63

a

63

57

09

I/O

32

26

VCC

64

58

010

I/O

(Note)

.

I/O

Input/Output Pins

o

Output Pins

VCC

VCC

Input Pins

HITACHI 311

(5) Pin Description
The MCU input and output signals are described below.
o

GND, VCC
These are the power supply pins for the MCU.

Connect the GND to the

ground (OV) and apply the VCC power supply voltage to the VCC pin.
o

TEST
This pin is not for use by users.

o
"

It should be connected to VCC pin.

RESET
This pin is used to reset the MCU.

o

OSCI' OSC2
These are input pins for the internal oscillator circuit.

They can be

connected to the crystal resonator, ceramic filter resonator, or
external oscillator circuits.

The internal oscillator should be

selected using a mask option.
o

D-port
The D-port is input/output port addressed by one bit.
(DO-DIS) are I/O pins.

All pins

The pins DO to D3 are standard pins and

their circuit type is NMOS open drain.

The pins D4 to Dl5 are large

current standard pins, and their circuit type is PMOS open drain.
oR-ports (RO to RA)
These are 4-bit I/O ports.

(RA however, is 2-bit construction.)

RO,

R6, R7 and R8 are output ports, R9 and RA are input ports, and RI to
R5 are I/O ports.

All pins of port RO-RA are standard pins.

The circuit type of D4-D15 and RO-R2 is PMOS open drain, and that of
DO-D3 and R3-R8 is NMOS open drain. The pins R32. R33. R40. R41. and
R42'are multiplexed with INTO, INTI. ~ 51, and SO respectively.
o

INTO,

INTI

These are input pins with which MCU operations can be interrupted
externally.
Timer B.
o

INTi

can be used as and external event input pin for

INTO and INTI are multiplexed with R32, R33 respectively.

SCK, 51, SO
The Transfer Clock I/O pin (SCK), Serial Data Input pin (51), and Serial
Data Output pin (SO) are used for serial interface.
multiplexed with R40' R41. and R42 respectively.

312 HITACHI

SCK, 51, and SO are

PROM Mode Pins
o

Vpp
This pin is used for applying program voltage (l2.5V ±0.3V) to internal
PROM.

0

CE
This pin is input for programming and verifying internal PROM.

0

OE
This pin is input of data output control signal for verify.

o

AO-Al4
These pins are address input pins for internal PROM.

o

00-07
These are data buses for internal PROM.

o

MO. Ml
These pins are used for setting EPROM mode.

EPROM mode is set when

MO. Ml. and TEST pins are Low level and RESET pin is High level.

HITACHI 313

(6)

Package Dimensions
Unit: mm(inch)

DP-64S
57.6(2.268)
58.6max.(Z.307max.)

33

.

_

_

c ~ ,,;

I

~-~!~l~:
~±0.25
.

0.48' 0.10 II
(OOI9'0.0~

(0070- 0.010)

-

-

E'
~c""
~

0

19.05
(0 750)

1

- -

15

I

O.2~!%t.I
to.OIO!\i:l)

o

DC-64S

I

51.3(2.256)

[~~~~:JgI~:~:::::l ~
1.17S±0.25
(0.010±0.010)

314 HITACHI

A~.

(O.OIO!S!8l)

Unit: nun(inch)
FP-64.

2.9ma •.

(O.II.m~x.)

.1

(0.039. 0.006)

I

(0.014' 0.004)

~uuuuuuuuuuuuuuuuuu~

~'OOIZ)
1.1

t O.3{O.

O·

15'

-

10.2 ROM Memory Map
The MCU includes 8,192 words x 10 bits PROM.

PROM is described in the

following paragraphs and PROM Memory Map is illustrated in Fig. 10-2.
o

Vector Address Area --- $0000 to $OOOF
Locations $0000 through $OOOF are reserved for JMPL instructions to
branch to the starting address of the initialization program and of the
interrupt service programs.

After reset of interrupt routine is serviced,

the program is executed from the vector address.
o

Zero-Page Subroutine Area --- $0000 to $003F
Locations $0000 through $003F are reserved for subroutines.

CAL instruc-

tion allows to branch to the subroutine.
o

Pattern Area --- $0000 to $OFFF
Locations $0000 through $OFFF are reserved for ROM data.

P instruction

allows referring to the ROM data as a pattern.
o

Program Area --- $0000 to $lFFF

HITACHI 315

.0000

0

0
1
2
3

Vector Address

5
6

,000F
.0010
Zero-Page Subroutine

63
64

(64Words)

Pattern

(4096 Wordsl
4095
4096

\

4
5

6

,003F

:~\,l

$1000

11
12
13
1
1l;

Program

(81 92 Wordsl
819 1
819 2

$lFFF
$2000

.0000

JMPL Instruction
(Jump to RESeT Routine)

JMPl Instruction

'0001
,0002

(Jump to tNT0 Routine)

'0003

JMPL Instruction

.0004

(Jump to

iN"T1 Routine)

JMPl Instruction
(Jump to TIMER· A Routine)

JMPl Instruction
(Jump to TlMER·B Routine)

'0005
'0006
.0007
.0008
.0009
,000A
,000B

.OOOC

JMPl Instruction
(Jump to SERIAL Routine)

,0000

.OOOE
• 0001'

Not Used

1638 3

• 3FFF

Fig. 10-2

PROM Memory Map

10.3 RAM Memory Map
The MCU includes 512 digits x 4 bits RAM as the data area and stack area.
In addition to these areas, interrupt control bits and special function
registers are also mapped on the RAM memory space.

RAM memory map is

illustrated in Fig. 10-3 and described in the following paragraphs.
o

Interrupt Control Bit Area --- $000 to $003
This area is used for interrupt controls, and is illustrated in Fig. 10-4.
It is accessable only by RAM bit manipulation instruction.
interrupt request flag cannot be set by software.

However, the

RSP bit is used to

reset the stack pointer.
o

Special Function Registers Area --- $004 to $OOB
The Special Function Registers are the mode or data registers for the
external interrupt, the serial interface, and the timer/counter.

These

registers are classified into three types: Write-only, Read-only, and
Read/Write as shown in Fig. 10-3. These registers cannot be accessed by
RAM bit manipulation instruction.

316 HITACHI

o

Data Area --- $020 to $lDF
16 digits of $020 through $02F are called memory register (MR) and
accessable by LAMR and XMRA instructions.

The configuration is shown

in Fig. 10-5.
0

Stack Area --- $3CO to $3FF
Locations $3CO through $3FF are reserved for LIFO stacks to save the
contents of the program counter (PC) , status (ST) and carry (CA) when
interruption is serviced.

This area can be used as 16 nesting level

stack which one level requires 4 digits.

A save condition is shown in

Fig. 10-5. The program counter is restored by RTN and RTNI instructions.
Status and Carry are restored only by RTNI instruction.

The area, not

used for stacking, is available as a data area.

o

$000
RAM-mapped Registers

1
$ 01F
$020

31
32

\

Memory RegisterslMR)

47 --------------- --- $ 02F
48
$ 030

(448 Digits)

479
480

$l0F
Sleo

Not Used

$000
$002

3
4

$003
(PMR) :W $004
Serial Mode Reg.
(SMR) ,W $005
Serial Data Reg. Lower ISRL) !R/W $006

5

Port Mode Reg.

7

Sarial Data Reg. Upper ISRU) 'R/W $007

8

Timer Mode Reg. A

ITMA)! W

9

Timer Mode Reg, 8

ITMB): W

10
11
12

TIMER-B'

$ 3BF
$3CO

959
960
Stack
164Digits)

$001

Interrupt Control Bits

2

6

Data

1023

0

$008

$009
ITCBLITLRL) :R/W $OOA
ITCBU/TLRU): R/W $OOB
$OOC

Not Used
$01F

31
$3FF

* Two registers are mapped on same address.
R :Read Only
W :Write Only
R/W:Read/Write

Timer Load Reg. Lower

10~__~~~~~~__+-4-~~~I~TL~R~L~I~~__~'_W~$00A
11

Fig, 10-3

Timer L~~~ R~t Upper

:w

$ OOB

RAM Memory Map

HITACHI 317

bit 3

bit 2

bit 1

bit 0

IMO

IFO
(IF of INTo)

I/E
(Interrupt Enable Flag)

$000

(1M of INTo)

RSP
(Reset SP Bit)

IMTA
(1M of TIMER-A)

IFTA
(IF of TIMER-A)

IMl
(1M of INT,)

IFl
(IF of INT,)

$001

IMTB
(1M of TIMER-B)

IFTB
(IF of TIMER -B)

$002

IMS
(1M of SERIAL)

(IF of SERIAL)

o

2

Not Used

Not Used

3

Not Used

Not Used

IF
1M
lIE
SP
{NQte)

IFS

$003

Interrupt Request Flag
Interrupt Mask
Interrupt Enable Flag
Stack Pointer
Each bit in Interru!;)t Control Sits Area is set by SEM/SEMO instruction, is reset by REM/REMO instruction and is tested by TM/TMO
instruction. It is not affected by other instructions. Furthermore. Interrupt Request Flag i's not affected by SEM/SEMD instruction.

The content of Status becomes invarid when "Not Used" bit is tested.

Fig. 10-4

Configuration of Interrupt Control Bit Area

Memory Registers

32
33
34

$ 020
$ 021

MR(2)

$ 022
$ 023

Level 14

$ 024
$ 025

Level 12

$ 026
$ 027

Level 10

$ 028
$ 029

Level

35

MR(3)

36
37

MR(4)
MR(5)
MR(6)
MR(7)

38
39
40

Stack Area

960 Level 16 $3CO
Level 15

MR(O)
MR(1)

MR(8)

41
42

MR(9)

43
44
45
46

MR(I1)
MR(12)
MR(13)
MR(14)

47

MR(15)

MR(10)

$ 02A
$ 028
$
$
$
$

02C
020
02E
02F 1023

Level 13
Level 11
Level

Level

Level
Level
Level
Level
Level

Level

PCI3 to PCo ; Program Counter
ST; Status
CA; Carry

Fig. 10-5

318 HITACHI

:V'"
9

6

5
4
3
2

1 S 3FF

1021

1022
1023

bit2

b113

ST

I

_I

PC

13

bitl

bitO

PC;;

"iiC;";

$ 3FC

PC,

S 3FO

PC.

S 3FE

PC,

S 3FF

_I _1_1
PC.
PC" 1 PC,

CA

"PC"";"

I
1

1

)

_I
PC, I

pc,

Pi:

PC;"

'

1

I

I
I

(Note) As the HD4074008 is 8k EPROM
version, PCl3 is not used.

Configuration of Memory Register, Stack Area and Stack Position

10.4

Absolute Maximum Ratings
Item

Supply Voltage

Symbol
Vee

Pin Voltage

VT

Total Allowance of Input Currents

1:10
-1:10
10

Total Allowance of Output Currents
Maximum Input Current

Value
-0.3 to +7.0

V

3

50

mA

150

mA

15

mA
mA

4
5
6,7

4
6

-10

Operating Temperature

Topr

-20 to +75

Storage Temperature

T' t9

-55 to +125

30

(Not. 2)

INote31
INot.41
INote 51
INote 61
INot.7)
INoteS)
INot.9)
INote 10)
INote 111

Note

V

0.3 to Vee +0.3

Maximum Output Current

INot.,.

Unit

mA

B,9
B, 10

mA

B,11

·C
C

'.rmenent demlgl may occur If " Absolute Maximum Retlngl"of the LSI or the EPROM are exceeded. Normal operatIon should be
under the condltton. of "EllCtrlc" Ch.rlCt.riltics". If theM conditions are .xceeded, it m-v caUM the mllfunction and affect the
.lIllbllltv of LSI.
All voltage. are with respect to GNO.
Applied to standII'd pins.
Tot.1 allow.nce of input current is the totll,um of input curr.nt which flow in from ,II ,10 pins to GNO simultaneously.
Total allow.nc. of output curr.nt is the total sum of the output current which flow out from Vee to all I/O pins simultaneously.
Maximum input current is the maximum amount of input current from each I/O pin to GNO.
Applied to Do - OJ and R3 - RS.
Maximum output current is the maximum amount of output current from Vee to each I/O pin.
Applied to 00 - OJ and R3 - RS.
Applied to RO - R2.
Applied to O~ ... Du.

HITACHI 319

10.5 HD4074008 Electrical Characteristics
(1) DC Characteristics (Vee = 5V ± 10%, GND
Item

Symbol

Pin Name

z

OV, Ta

z

-20 to +75°C, if not specified.)
Value

Test Condition.

typ

max

rnr.. TNT;

O.avec

-

Vee+0.3

V

SI

0.7V ee

-

V

OSC,

V ee - 0.5

-

Vee+0 .3
Vee+0.3

-

0.2Vee

V

RESET~K.

Input "High"
Voltage

V'H

RESET.S~K.

Input "Low"
Voltage

~p.3

INTo.INT,
V'L

Unit

min

-0.3

SI
OSC,

Output "High"
Voltage

SCi<. SO

-loH = 1.0mA

VOH

Vee -1.0

-

-loH = 0.01 rnA

Vee-O·5

-

Output "Low"
Voltage

VOL

SCK.SO

IOL = 1.6 rnA

-

Vin = OV to Vee

-

-

-0.3

RESET.~

V

0.2Vee

V

O.!i

V

-

Note

V
V

0.4

V

1

IJA

1

Input/Output
Leakage Current

H'LI

iN'I';;". TNT;.

Current
Dissipation in
Active Mode

Icc

Vee

Vee=5V

-

-

4.5

rnA

2.4

ISBY

Vee

Maximum
Logic
Operation
Vee = 5V

-

-

1.7

rnA

3.4

Current
Dissipation in
Stop Mode

I,top

Vee

-

-

10

IJA

Stop Mode
Retain Voltage

V. tOP

Vee

2

-

-

V

Current
Dissipation in
Standby Mode

SI. SO. OSC,

Vin(TEST) • Vcc-O.3V to Vee
Vin(RESET) = OV to O.3V

(Note 1) Pull-up MOS current and output buffer current are excluded.

(Note 2) The MCU is in the reset stlte. The input/output current dOH not flow.
• Reset state in Operation Mode
Test Conditions: MCU state;
Pin .. ate;

- RESET. TEST ... Vee voltage
R3-R9 ... Vee voltage

_D. -0,.

eO.. -Ou.AO-R2,RAQ,RA1···GND voltage
(Note 3) The timer/counter operate and input/output current does not flow.
Test Conditions: MCU state;
• Standby Mode
-Input/Output; Relet Itate
- SERIAL Interface; Stop
• RESET ... GNO voltage
- TEST··· Vee voltage
• Do-D), R3-R9 .. , Vee voltage
RO-R2. RAQ. RA' .,. GND voltage
(Note 4) When fosc=x (MHz) , the Current Dissipation in Operation mode and Standby mode are estimated as follows:
Pin state:

-0.-0".

max. value (fose=x(MHz] I

320 HITACHI

"~x max. value (fosc=S[MHz])

(2) Input/Output Characteristics for standard pin - ,
(Vee =5V ± 10%, GND =OV, Ta = -20 to +75°C, if not specified.)
Item
Input "High"
Voltage

Symbol
V,,,

Pin Name

Test Conditions

max

0. 7V cc

-

Vcc+0.3

V

-0.3

-

0.3Vcc

V

IOL = 1.6 mA

-

-

0.4

V

Vin = OV to Vee

-

-

1

I1A

R3 - RS, R9

V'L

Output "Low"
Voltage

VOL

Do - 03,

Input/Output
Leakage Current

\I,Ll

Do - 03.

Do - 03.
R3 - R5. R9
R3- RS
R3- R9

Unit

typ

Do - 03,

Input "Low"
Voltage

Value
min

Note

1

(Note 1) Output buffer current are excluded.

(3) Input/output characteristics for standard pin - 2
(Vee =SV ± 10%, GNO =OV, Ta =-20 to +7Soe, if not specified.)
Item

Symbol

I nput "High"
Voltage

VIH

Input "Low"
Voltage

VIL

Pin Name

D. - 0 15 , Rl
R2. RAO, RAl

D. - DIs, Rl
R2, RAO, RAl

D. - DIs
Output "High"
Voltage

VOH
RO- R2

Input/Output
Leakage
Current

Test Conditions

RO - R2
RAO. RAl

Unit

typ

max

0.7VCC

-

VCC+0.3

V

-0.3

-

0.3VCC

V

-

V

-IOH = lSmA

Vce-3.O

-

-IOH = 10mA

Vee-2.O

-

-IOH =4mA

Vee- 1.O

-IOH = 3mA

Vee-3.O

-IOH = 2mA

Vee-2.O

-IOH -O.SmA

Vee 1.0

-

Vin=OtoVeC

-

-

D. - DIs
IIILI

Value

min

Note

V
V
V
V
V

1

I1A

1

(Note 1) Output buffer current are excluded.

HITACHI 321

(4) AC Characteristics (Vee .. 5V ± 10%. GND = OV. Ta" -20 to +75°C. if not specified.)
Symbol

Item

folC

Oscillation Frequency
Instruction Cycle Time

Pin Name
OSC,.OSC,

tCYC

Oscillator Stabilization
Time
External Clock "High"
Level Width
External Clock "Low"
Level Width

min

Value
typ

d ivide·by·8

0.4

8

9

divide·by.s

0.89

1

20

/JS

-

-

20

ms

1

-

ns

2

Test
Conditions

tRC

asc,.OSC,

tCPH

OSC,

divide·by·8

41

tCPL

OSC,

divide·by·8

41

-

External Clock Rise Time

tCPr

OSC,

External Clock Fall Time

tCPf

OSC,

-

-

I1IITO "H igh" Level Width

t'OH

INTO

T1iITO "Low" Level Width
iliiTi "High" Level Width
iliiTi "Low" Level Width

t'Ol
tllH

RESET "High" Level Width
Inpu t Capacitance

till
tRSTH
Cin

RESET Fall Time

iNIo

TNt,
iNT,
RESET
all pins

f=1MHz
Vin = OV

tRSTI

max

MHz

-

ns

2

15

ns

.2
2

15

ns

2
2

-

- '--------- - - - 2
-

teye

i

teye

-

-

i

2
2

teye

3
3

-

teye

4

-

-

.. -

t~e

15

pF

20

ms

INote 1) Oscillator stabilization time is the time until the oscillator stabilize. after Vee reach.. 4.5V at "Power-c;tn", or after. RESET
input level goes to "High" by resetting to' quit the stop mode by MCU reset on the Circuits below. At power ON or recovering
from stop mode, apply RESET input more than tAC to obtain the necessary time for oscillator stabilization. When using
crystal or ceramic filter oscillator, please ask a crystal oscillator maker's or ceramic filter maker's advice because oscillator

stabilization time depends on the circuit constant and stray capacity.

Crvstal oscillator

Ceramic filter oscillator

GND
Crystal: 8.388608MHz NC·18lNihon Denpa Kogyo)
RI- lMO <20%
C, - C, • 10pF • 20%

Ceramic filter: CSAB.OOMT (Murata)
RI. lMOt20%
C, • C, = 30pF • 20%
(Note 3)

(Not. 2)

OSC,

tCPr
(Noto41
RESET

322HITAOHI

'Cpt

Note

Unit

3
3

4

(S) Serial Interface Timing Characteristics
(Vee = SV ± 10%, GND = OV, Ta = -20 to +7SoC, if not specified.)
•

At Transfer Clock Output
Item

Symbol

Transfer Clock Cycle Time

Transfer Clock '"Low'"
Level Width

•

(Note 2)

SCK

tScyc:

Transfer Clock '"High'"
Level Width

Test
Conditions

Pin Name

min

Value
typ

-

1

tSCKH

SCK

(Note 2)

0.5

tSCKL

SCK

(Note 2)

0.5

Unit

Note

-

tc:vc

1,2

.-

tsCYC

1,2

-

tsCYC

max

Transfer Clock Rise Time

tSCKr

SCK

(Note 2)

Transfer Clock Fall Time

tSCKf

SCK

(Note 2)

-

-

Serial Output Data
Delay Time

toso

SO

(Note 2)

-

-

250

Serial Input Data Set-up Time

tSSI

SI

300

Serial Input Data Hold Time

tHSI

SI

150

-

-

._---

-100

ns

1,2
_.. - 1,2

100

ns

1,2

ns

1,2

ns

1

ns

1

At Transfer Clock Input
Symbol

Item

Test
Conditions

Pin Name

Value
min

typ

max

Unit

Note

tsc:yc

SCK

1

1

tSCKH

SCK

0.5

-

-

tCYC

Transfer Clock '"High'"
Level Width

tsc:vc

1

Transfer Clock '"Low'"
Level Width

tSCKL

SCK

0.5

-

-

Transfer Clock Rise Time

tSCKr

SCK

-

Transfer Clock Fall Time

tSCKf

SCK

-

Serial Output Data
Delay Time

toso

SO

Serial Input Data Set·up Time

t5s1

Senal Input Data Hold Time

tHSI

Transfer Clock Cycle Time

-

-

SI

300

-

51

150

(Note 2)

tsCYC

1

100

ns

1

100

ns

1

250

ns

1,2

~

ns

1

-

ns

1

(Note 1) Timing Diagram of Serial Interface
tSeye

so

>-{

____-«

51

tsso

0 7Vcc

'-_____

0.3Vee

• Vee - 2.0V and O.SV are the threshold voltage for transfer clock output.

O.aVec
(Note 2)

and

0.2 Vee are the threshold voltage for transfer clock

input.

Timing Load Circuit
Vee

Test
POint

~
C

3()pf

RL=26k\l

R

lS2074fY

12kl!

or Equlv.

HIT~CHI323

10.6 Programming the On-Chip Programmable ROM
The HD4074008's on-chip PROM is programmed in PROM mode.

PROM mode is set

by bringing TEST, MO, and M1 low, and RESET high as shown in Fig. 10-7.
In PROM lI\ode the MCU does not operate.

It can be programmed like a standard

27256 EPROM using a standard PROM programmer and a 64-to-28-pin socket
adapter. Table 10-2 lists recommeded PROM programmers and socket adapters.
Since an instruction of the HMCS400 series consists of 10 bits, the
HMCS400 series microcomputer incorporate conversion circuit to use general
perpose PROM programmer.

By this circuit, an instruction is read or programmed

using 2 addresses, lower 5 bits and upper 5 bits as shown in Fig. 10-8. For
example, if 8k words of on-chip PROM is programmed by general purpose PROM
programmer, 16k bytes of addresses ($0000-$3FFF) should be specified.
Precautions
1. Addresses $0000 to $3FFF should be specified if the PROM is programmed by the PROM programmer.

If addresses of $4000 or higher is

accessed, the PROM may not be programmed or verified.
plastic package type cannot be erased and reprogrammed.
unused address should be set to $FF.

Note that the
Data in

(Ceramic window packages can

be erased and reprogrammed by ultraviolet light.)
2. Be careful that the PROM programmer, socket adapter and LSI match.
Using the wrong programmer of socket adapter may cause an overvoltage and damage the LSI.

Make sure that the LSI is firmly fixed

in the socket adapter, and that the socket adapter is firmly fixed
in the programmer;
3. The PROM should be programmed with Vpp=12.SV.

Other PROMs use 21V.

If 21V is applied to the HD4074008, the LSI may be permanently
damaged.

(1)

12.5V is Intel's 27256 Vpp.

Programming and Verification
The HD4074008 can be high-speed programmed without causing
voltage stress or affecting data reliability.
Fig.10-9 is a programming flowchart, and Fig. 10-10 is a timing
chart.

For precautions on PROM programming, refer to "ZTAT MCU On-Chip

PROM Characteristics and Precautions for Applications".

324 ".'tACH.

\' ,I

\' cc

A,
A,
A,
A.
A.
A,
A,
A,
A,
A"
A ..
Au

u u
u u

-<

;>;>

O.
O.
0,
00

0,
0,
0,
0,

GND

GND

HD4074008

TEST
RESET

HD4074008

TEST
RESET
J\f,

.. M,Mo

1\10
A.

A"
A ..

A.

Vpp

Vpp

OE

CE

0,
0,
0.
0.

\" cc

~ ~ ~

0

'"I>il/>il

;>OOOOUO

(Top View)

(TOP View)

No mark: Open
Fig. 10-6

PROM Mode Pin Arrangement
Vee

Vee

l'

LRESET
, - - TEST
Mo
+---- M,
,IT

Vee

-----

00
\

07
Ao
\

A14

c::::::::>
r-:'--==:J

Data
OO~07

Address
Ao~ A,.

OE
CE
GND

JFig. 10-7

PROM Mode Function Diagram

HITACHI 325

10000
10001

0
0

~

0
0

0
0

bi••

bill

bill

bill

bil2
l1li7

....

bill

biIO

JMPLI_
CJump 10 RESET -no) .
JMPLI...._
CJump 10 INTO _nol

rfl5.:"> t } 10000
.!c.flSt'·, t

bil5

Vector Addr...

lOOOF
$0010

SoolF
$0020

JMPL Indruction

CJ""", .. TNT, _ I
JMPL Inltruction

Zofo· ..... _outino

C84_dol

"'"

l007F
10080
·PMte,n
(4098 Words)
S 1FFf

12000

~

10003
10004

I_
I_

CJ_ t. TIMER-A_I

10007

JMPL Iftllruction

loooa
S_
S_

CJump •• TlMER·8 Routinol

S003F
SOO4O

10000
10001
10002

loooe
JMPL Inltruction

lOOOC

CJump •• SERIAL Routinol

10000

11000

I_
lOOOF

Progr.m

C8192_clsl
I1FFF

$3FFF

$2000

Not U..d

(Note)

.

S7FFF

$ FFF

.

Three bits are not used.
(Set to "111")
(Note) When reading this address space, "$FF" is output.
Fig. 10-8

(2)

PROM Mode Memory Map

Erasing (Window package type)
The PROMs on HD4074008's in ceramic "window" packages can be erased
by ultra violet light.

All erased bits become ones.

Erasing conditions are: ultraviolet (UV) light with wavelength 2537A
with a minimum irradiation of l5W S/cm.
by exposing the LSI to a 12,000

~W/cm

These conditions are satisfied

UV source for 15-20 minutes, at

a distance of 1 inch.
For window-type packages, refer to "Window-Type Package Precautions".
Table 10-1
Mode
~
Programming
Verify
Programming
inhibited

326 t:tITACHI

Mode Selection

CE

OE

VPP

Low
High
High

High
Low
High

VPP
VPP
VPP

Data input
Data output
High impedance

Table 10-2

PROM Programmer and Socket Adapter

PROM Programmer
Type name
Maker
DATA I/O
AVAL Corp

29A
29B
PKW-1000
PKW-7000

Socket Adapter
Type name
Maker
Hitachi

HS408ESSllH

Hitachi

HS408ESS21H

Address + 1--Address

Fig. 10-9

High Speed Programming Flowchart

HITACHI 327

(3)

Programming electrical characteristics

DC Characteristics (VCC·6.V. ~Q •. ~5V, Vpp~12. 5V
Item

to. 3V.,

VSS=OV, Ta=25°C ±SOC, unless otherwise noted.)

Symbol

Test Condition

min

Input High Voltage

00-07 ,AO-A 14 OE,CE

VIR

2.2

Input Low Voltage

00-0 7. ,AO-A 14 OE,CE

VIL

-0.3

Output High Voltage

00-0 7

VOH

IOH=-200~A

Output Low Voltage

00-0 7

VOL

IOL-1. 6rnA

Input Leakage Current

00-°7' AO-A 14 OE,CE

IILlI

Vin -5.25V/O.5V

Vee Current

ICC

Vpp Current

Ipp

2.4

-

typ

-

max

Unit

VCC+O·3

V

0.8

V

-

V

-

0.45

-

2

~A

-

30

rnA

-

40

rnA

V

AC Characteristics (VCC=6V to.25V, Vpp=12.5V to. 3V, Ta=2SoC ±5°C, unless otherwise noted.)
Item

mi-n

typ

max

Unit

Address Set-up Time

Symbol
tAS

2

-

-

~s

or

tOES

2

-

-

~s

Data Set-up Time

tos

2

-

-

~s

Address Hold Time

tAH

0

-

~s

Set-up Time

Test Condition

Vpp Set-up Time

tvps

2

-

Program Pulse Width

tpw

0.95

1.0

CE Pulse Width when Overprogramm1ng

topw

2.85

VCC Set-up Time

tvcs

2

tOE

0

Data Hold Time

tOH

Output Disable Delay Time

tOF

'Data Output Delay Time

Fig.lO-lO

2

-

-

-

~s

130

ns

-

ms

78.75

ms

-

~s

500

ns

Input puIs. level 0.8 - 2.2V
Input rising/falling tim.

~

20ns

Timing reference level { input: l.OV, 2.0V
output: 0.8V, 2.0V

va..'fy

Program

e-

Addrass
tAS

Data

~

Data In Stabla
tD.

Data Out
tDH

~

Vpp
Vpp

Vee

Vee
Vee

tvps

GND

tve.

~

~

tOES

tOE

~

Fig. 10-10 PROM Programming/Verify Timing

328' HtTACHI

alid

~s

1.05

I~

10.7 ZTAT MCU On-Chip PROM Characteristics and Precautions for Applications
(1)

Principles of Programming/Erasing
The HD4074008's memory cells are the same as an EPROM's.

Therefore

they are programmed by applying high voltage to control gates and drains,
which injects hot electrons into the floating gate (Fig. 10-11).

The

condensed electrons in the floating gate are stable, surrounded by an
energy barrier of Si02 film.

Such a cell becomes a 0 bit due to the

memory threshold voltage change.

A cell with no condensed electrons at

its floating gate appears as a 1 bit.
The electron charge in memory cells may decrease as time goes by.
This can be caused by:

(9

Ultraviolet light, discharged by photo-emitting electrons
(erasure principle)

CD

Heat, discharged by thermal emitting electrons

CD

High voltage, discharged by a high electric field at the control
gate or drain
If the oxide film covering a floating gate is defective, the

erasure rate is great.

Normally, electron erasure does not occur,

because such defective devices are found and removed during testing.

Si02
Source

,-----1"
~---~

: /Control gate.

"'~

S~02

Floating gate
~
Drain source'lo.

(~')5
Programming ("0")

Fig. 10-11

r--=---,./ Control gate

I

,

(

\

N+

~

,e

I'

""

r

J el l

/Floating gate
/Drain
N+

\

\
Erasing ("1")

Cross-Section of EPROM Memory Cell

HITACHI 329

(2) Programming Precautions
The PROM memory cells should be programmed under specific voltage
and timing conditions.

The higher the program voltage and the longer

the program pulse is applied, the more electrons will be injected into
the floating gate.

However, if an overvoltage is applied to Vpp, the

p-n junction may be permanently damaged.
PROM programmer overshot.

Pay particular attention to

Negative voltage noise will cause a parasitic

transistor effect, which may reduce breakdown voltage.
The HD4074008 is connected electrically to the PROM programmer
through a socket adapter.
1.

Therefore, pay attention to the following:

Confirm that the socket adapter is firmly fixed on the PROM
programmer.

2.

Do not touch the socket adapter or the LSI during programming.
Mis-programming can be caused by poor contacts.

(3) HD4074008 Reliability After Programming
Generally, semiconductors are reliable except for initial failures.
To avoid failures, screening can be performed.

Screening at high

temperature removes PROM memory cells with data hold failures in a
short time.

This is done to the ZTAT's in the wafer stage, so ZTAT

data hold characteristics are high.

Exposing the LSI to 150°C after

user programming can effectively up grade these characteristics.
Fig. 10-12 shows the recommended screening flow.

Programming/Verification

Exposure in high tempera ture
without applying any power

lSO.e ±lO·e. 48Hr +8 Hr*
-8 Hr

Confirmation of reading
Vee=4.SV or S.5V

'*

Fig.

Exposing time is the time after
the temperature in fireplace
reaches 150°C

lO~12

Recommended Screening Flow

Note: If programming errors occur continuously during programming with

one PROM programmer. s top programming and check the PROM programmer or socket adapter.

If trouble occurs in verification after

programming, or after exposure to high temperatures, please
~tlform

330 HITACHI

a Hi tachi engineer.

(4)

Window-Type Package Precautions

Q)

Glass Erasure Window
If the glass window comes in contact with plastic or anything
with a static charge, the LSI may malfunction due to the electrostatic charge on the surface of the window.

If this occurs,

exposing the LSI to ultraviolet light for a few minutes neutralizes
the charge, and restores the LSI to normal operation.

However,

charge stored in the floating gate decreases at the same time, so
reprogramming is recommended.
Electrostatic charge buildup on the window is a fundamental cause
of malfunctions.

Measures for its prevention are the same as those

for preventing electrostatic breakdown:
Operators should be grounded when handling equipment.
Do not rub the glass window with plastics.
Be careful of coolant sprays, which may contain a few ions.
The ultraviolet shading label (which includes conductive
material) effectively neutralizes charge.

@

Ultraviolet Shading Label
If the LSI is exposed to fluorescent light or sunlight, its
memory contents may be erased by the small quantity of ultraviolet
light in these sources.

In strong light, the MCU may fail under

the influence of photocurrent.

To prevent these problems, it is

recommended that the device be used with an ultraviolet shading
label covering the erasure window after programming.
Special labels are sold for this purpose.
to absorb ultraviolet light.

They contain metal

When choosing a label, note the

following:
Adhesion (mechanical intensity) - Re-use and dust reduce
adhesion.

Peeling off a label may cause static electricity.

Therefore, erasing and rewriting is recommended after peeling.
Sticking a new label over the old one is better than replacing
a label.
Allowable temperature range - The allowable environmental
temperature range of the label should be noted.

If it is used

under conditions outside this range, the paste may stiffen or
adhere to the label, causing paste to remain on· the window when
the label is removed.

HITACHI 331

Moisture resistance - The allowable moisture range and
environmental conditions of the label should be noted.

It is

difficult to find a shade label applicable to all conditions.
The proper label should be selected depending on the intended
use of the Meu.

332 HITACHI

11. EPROM ON PACKAGE TYPE SINGLE CHIP MICROCOMPUTER HD614P080S/HD614P0160S
11.1 Overview
The HD6l4P080S is a 4-bit single chip microcomputer which can mount a
standard EPROM 2764/27128 as program memory. and a standard EPROM 27256 for the
HD6l4P0160S.
The HD6l4P080S/HD6l4P0160S is pin-compatible with the mask ROM type
HMCS402C/AC/CL. HMCS404C/AC/CL. HMCS408C/AC/CL and has the same functions
except for the range of power-supply voltage. ROM/RAM capacity. mask
option. and package.

By modifying the program in the EPROM. they can be

used for the evaluation or small scale production of the HMCS402C/AC/CL.
HMCS404C/AC/CL. HMCS408C/AC/CL.

(1) Hardware Features
•

4-bit Architecture

•

Capacity of Program Memory(ROM) and EPROM
4096 words x 10 bits ••••• HN482764. HN27C64
8192 words x 10 bits .•••• HN4827l28
16384 words x 10 bits ..••. HN27256

} HD6l4P080S
} HD6l4P0160S

•

Data Memory (RAM) Capacity •••.•• 576 digits x 4 bits

•

58 I/O Pins .•••• 26 I/O pins are high voltage (max. 40V)

•

2 Timer/Counters
II-bit Prescaler
8-bit Free Running Counter
8-bit Auto-reload Timer/Event Counter

•

Clocked Synchronous 8-bit Serial Interface

•

5 Interrupt sources
External

2

Timer/Counter

2

Serial Interface

1

•

Subroutine Stack
Up to 16 levels including interrupts

•

Minimum Instruction Cycle Time; 1.29

•

2 Low Power Dissipation Modes
Standby - Stops instruction execution while keeping clock generator and

~s

interrupt functions.
Stop

- Stops instruction execution and clock generation while retaining
RAM data

•

Clock Generator
External Connection of Crystal Resonator or Ceramic
Filter Resonator (externally drivable)

•

Power Voltage Range; 5V ± 10%

HITACHi 333

•

I/O Pin Circuit Type
All standard pins are "without pull-up MOS".
All high voltage pins are "without pull-down MOS".

•

Shrink Type 64 Pin EPROM On-package

(2) Software Features
•

Software Compatible with HMCS402C/AC/CL, HMCS404C/AC/CL, HMCS408C/AC/CL

•

Instruction Set Similar to and More Powerful than HMCS40 Series; 99 Instructions

•

High Programming Efficiency with 10-bit ROM/Word; 79 instructions are single-

•
•

Direct Branch to ROM Area
Direct Addressing to All RAM Area

•

Subroutine Nesting Up to 16 Levels Including Interrupts

•

Binary and BCD Arithmetic Operation

•

Powerful Logic Arithmetic Operation

•

Pattern Generation - Table Look Up Capability -

•

Bit Manipulation for Both RAM and I/O

word instructions.

334 HITACHI

(3) Pin Arrangement
0" 1
0'1 2

o.
o.
o.

0

0 ..
O.

0'3 3

D.

0,. 4

10,

0'5 5

O.

Roo •

O.

0,

I Vet

Vee 1(

l A'2

... ,.,;r

H,

A" Iii

0,
0,
0,
GND
05C2

RESET

R"
Ru
R... ,/Vdllp 1

R"

A,

CE@

('9 Ao

07 U

ill

R~

1

RnfiNi'O
R~

@o.

o. "

00.

05

R"
Ru

Ro,

7

R"
1

(o~

0) OJ

0.0

!!jGND

OJ @

R~

Roo

R"

R"

R"

Roo

3 R"
37 RIO

R"

R"

R"

R"
Ru

",/SO

R"

A.

, A.

A.l(

; A.

A" l~

7 A,

GNDtl

I A,

A'otl

, A,

...

celli

'

0,

1100

O.

0,

O.

,) 01

O.

I~GND

0,

,~

'.
'.
"

37 RI-i

tss•

O.7Vee
O.22Vcc

* VCC-2.OV and O.8V are the threshold voltage for transfer clock output.

(No,. 21

;pq

O.7VCC and 0.22

Vee are the threshold voltage for transfer clock input.

Timing Load Circuit

Vee

Test
Point

e

30pf

RL=2.8kO

R

1820748

. 12kQ

or Equiv.

HITACHI 345

(6 )
4

Characteristics Curve (Reference data)
4

Ta=-20-+75"C
Vcc,,;,SV

-------

o

2

3

Ta- 20-+7SC
fosc=4MHz

3

~
~

max;

./
./
1

4

S

o

6

2

Icc vs. Vcc characteristic
(crystal, ceramic resonator)

2.0r:T=-a-=-_-::2~O~_~+~7~S-':"C~-'--""'--'-"
~

6

Vee(V)

Icc vs. fose characteristic
(crystal, ceramic resonator)

Vcc

5

4

3

fosdMHz)

5V

2.0 Ta- 20-+75"C
fosc=4MHz

1.6

_ 1.61----+--I1---t---t-

«

ISBYI

y.

E

~ 1.21--~----+--+--7,£..-t_::;,.,...'_I

,/

Jl

./
ISBY2
max.

0.4

O'~--+--~2~-~3~-~4~-~5~~6

o

2

4

3

5

6

Vcc(V)

fosdMHz)
ISBY vs. fOle characteristics
(crystal, ceramic resonator)

ISBY vs. VCC characteristics
(crystal, ceramic resonator)

15

30
Ta - -20 - +7S'C

I

Ta - -20 .... +75°C

VCC=5.5V/

vcc+.S/
10

/

V

.%
/VC~-4.5V

.§

/

·ec:

/ V

1//

--

<

/

20

VCC=4.5V

/

J:

9

/

I

'V
1/

1#

IV
o

V

/

V

2

VOl(V)
IOl min. vs. VOL characteristics

(Standard Pin)

\

346 HITACHI

V

/

10

/.V
//

V

o

2

3

4

VCC-VOH(V)
-IOH min. vs. (Vee-VOH) characteristics

(D. - 0 IS pins)

8
Ta--20 - +75°C
VCJ.5·t V

A

4

;(

.5

c
'il!

5

T

V
1/V

3

2

1

V

V

-

~

. / VCC-4.5V

~V'

../.V

,"'~

/
o

4
VCC-VOH(V)
-IOH min. lIS. (VCC-VOH) characteristics

(RO - R2 pins)

HITACHI '347

12.

EPROM ON PACKAGE TYPE MICROCor<1PUTER HD614P180/HD40P4181

12.1 Overview
The HD614P180/HD40P4181 are 4 bit single-chip microcomputer which can
mount a standard EPROM 2764/27128 for program memory.
The HD614P180/HD40P4181 are pin compatible with the mask ROM type
HMCS412C/CL/AC and HMCS414C/CL/AC, and have the same function as them
except power supply voltage range, ROM capacity, RAM capacity, mask
option, and package.

By modifying the program in the EPROM, the

HD614P180/HD40P4181 can be used for the evaluation of the HMCS4l2C/
CL/AC and HMCS414C/CL/AC or for small-scale production.

(1) Hardware features
o

4-bit Architecture

o

Application to 4k, 8k words x 10 bits of EPROM

o

4096 words x 10 bits

HN482764, HN27C64

8192 words x 10 bits

HN4827128

Data Memory (RAM) Capacity •.•.•• 576 digits x 4 bits (HD614P180)
992 digits x 4 bits (HD40P4l8l)

o

36 I/O Pins - 24 I/O pins are high voltage up to 40V (max).

o

Timer/Counter
II-bit Prescaler
8-bit Auto-reload Timer/Event Counter

o

3 Interrupts
External

2

Timer/Counter

1

o

Subroutine Stack

o

Minimum Instruction Execution Time; 1.29

o

2 Low Power Modes

Up to 16 levels including interrupts
~s

(HD614P180), 0.89

~s

(HD40P4181)

Standby - Stops instruction execution while keeping clock generator
and interrupt functions included Timer/Counter and Serial
Interface in operation
Stop

- Stops instruction execution and clock generation while
retaining RAM data

o

Clock Generator
External Connection of Crystal Resonator or Ceramic
Filter Resonator (externally drivable)

o

Power Voltage Range; 5V ± 10%

348 HITACHI

0

I/O Pin Circuit Form
All standard pins are "without pull-up MOS".
All high voltage pins are "without pull-down MOS".

0

Shrink Type 42 Pin EPROM On-package

(2) Software features
o

Software Compatibel with HMCS4l2/4l4

o

Instruction Set Similar to and More Powerful than HMCS40 Series;

o

High Programming Efficiency with lO-bit ROM/Word; 78 instructions are

o

Direct Branch to All ROM Area

o

Direct or Indirect Addressing to All RAM Area

o

Subroutine Nesting Up to 16 Levels Including Interrupts

98 Instructions
single word instructions.

o

Binary and BCD Arithmetic Operation

o

Powerful Logic Arithmetic Operation

o

Pattern Generation - Table Look Up Capability -

o

Bit Manipulation for Both RAM and I/O

(3) Pin arrangement (Top View)

0"
013
O.

Roo

Vee 0
VecO
A'l0
A. 0
A. 0

Ro,

Ro,
Ro,
R,o
R"
R"
R13
R,o

A110
GNOO
Al00

R"
R22

0, C
0.0
0.0
O. 0
OJ C

R"
RJO
R"
RJ2/iNio
R33/INT,
Vee

ITo

"

HITACHI 349

(4) Recommended applicable EPROM
Type No.

Program Memory Capacity

fOSC(MHz)

6

HN27C64-30
HN482764-3
HN27C64G-25
HN482764

4
6

HN4827128-45
HN4827128-25

4
4096 words
HD614P180
HD40P4181
8192 words

EPROM Type No.

(5) Package dimension
unit: mm (inch)
DC-42P
528
12.0791

42

0

···0····

22

~ 8~
~~~

I I •• I . I . . . . . . ~

1

350 HITACHI

I L 2.54

21
10.1001

(6) Block diagrams
Rnl

R:ul

RESET

TAT; INTo

ftIf OSC I osc, VccGND

r--'-_.L.-lL--J.-,l lr- __ - _~~P'::'k.:g.: __ - _;,

:,
,

TIMER
8
INTERRUPT CONTROL

SP

RAM 578x4bil

PC

•

I

,

,

R.uRuR.,R.o iJiT,iNT;
R:n/RU/Al'ho .--------:AuRn'h, R~J,.• :AuR1IR'1
Alo:..J
,, ________

r r- . - - - - ~)_~~~~~ L__~'~~'~~~~~,~~o~~~•.?~~._D~ _O~jOl 0,0,
I

HD6l4P180

00

[=~~J High voltage

RESET

TrS'f CSC, 0$C2 VccGND

.-JC---L_..L_,,-,l lr- ____ ~:-!:a.:~~e____
:,
,

TIMER

8

:"I

INTERRUPT CONTROL
EPROM

RAM 992 x4btt

HD40P4l8l

SP

I

HN.82764I
HN27C64
H~27t28

[:::JHigh voltage

HITACHI 351

12.2 ROM Memory Map
ROM is described in the following paragraphs and ROM Memory Map is
illustrated in Fig. 12-1.

(1) Vector Address Area --- $0000 to $OOOF
Locations $0000 through $OOOF are reserved for JMPL instructions to
branch to the starting address of the initialization program and of
the interrupt service programs.

After reset of interrupt routine is

serviced, the program is executed from the vector address.

(2) Zero-Page Subroutine Area --- $0000 to $003F
Locations $0000 through'$003F are reserved for subroutines.

CAL

instruction allows to branch to the subroutine.

(3) Pattern Area --- $0000 to $OFFF
Locations $0000 through $OFFF are reserved 'for ROM data.

P instruc-

tion allows referring to the ROM data as a pattern.

(4) Program Area --- $000 to'$lFFF
12.3 RAM Memory Map
The HD614P180 includes 576 digits x 4 bits RAM as the data area and
stack area.

Also, the HD40P4181 includes 992 digits x 4 bits RAM.

In

addition to these areas, interrupt control bits and special function
registers are also mapped on the RAM memory space.

RAM memory map is

illustrated in Fig. 12-2 and described in the following paragraphs.

(1) Interrupt Control Bit Area --- $000 to $003
This area is used for interrupt controls, and is illustrated in
Fig. 12-3.

It is accessab1e only by RAM bit manipulation instruction.

However, the interrupt request flag cannot be set by software.

RSP

bit is only used to reset the stack Pointer.

(2) Special Function Registers Area --- $004 to $OOB
The Specia:1 Function Registers are the mode 'or data registers for
the external interrupt, the serial interface, and the timer/counter.

352 HI'rACHI

These registers are classified into three types: Write-only, Read-only,
and Read/Write as shown in Fig. 12-2.

These registers cannot be

accessed by RAM bit manipulation instruction.

(3) Data Area --- $020 to $21F [HD614P180]
$020 to $3BF [HD40P4181]
16 digits of $020 through $02F are called memory register (MR) and
accessable by LAMR and XMRA instructions.

The configuration is shown

in Fig. 12-4.

(4) Stack Area --- $3CO to $3FF
Locations $3CO through $3FF are reserved for LIFO stacks to save
the contents of the program counter (PC), status (ST) and carry (CA)
when interruption is serviced.

This area can be used as 16 nesting

level stack which one level requires 4 digits.
shown in Fig. 12-4.
instructions.

A save condition is

The program counter is restored by RTN and RTNI

Status and Carry are restored only by RTNI instruction.

The area, not used for stacking, is available as a data area.

EPROM""

~

Meu ROM Address

... "

SOOOO

0

$0001

0

0
0

0
0

blt4

bill

b112

bit 1

bltO

b119

Me

bit7

bite

bitS

JMPL Instruction
(Jump to RESET Routine)

50000
50001

JMPl Instruction
(Jump 10 INTO Routine)

50002
50003

$0010

JMPL Instruction
(Jump 10 INT 1 Routine,

50005

$OOlF

JMPl Instruction
(Jump to TlMER-B Routine)

$0007
SOOOS
50009

Lower 5 bit}
Upper 5 bit $ 0000

Vector Address

SOOOF

SOO1f

~

$0020
Zero-Page Subroutine
(64 Words)

S007F
S0080

50008

$0040

Paltern
(4096 Words)

SOFFF

"'"

S lFFf
S2000

$1000

Program

(8192 WOrds)

50004

SOOO'"
SOOO8
SOOOC
SOOOD
SOOO£
SOOOf

$ lFfF

S 3FFF

Not used

(Set to "",")

Fig. 12-1

ROM Memory Map

HITACHI 353

o

SOOO

u

SOlF

2

I~:O

3
4
5

1

RAM· mapped Reglste,.

31
32
Memory ReglsterslMR)

47

48

------------------------

S02F
S030

1~lertUJK

COn1tal lill

Port Mode Reg.

IPMRI I W

6

NOI Ulld
HOI U....

SOOI
SOOO

1007
1000
1001
IOCIA
1000
lOOC

7

HOI U....

Data

S

NOI UHd

(51~ DigitS)

9' Timer MOde Reg. 8

543
544

10
TIMER,a
11

S 21F
S 220

1000
1001
1002
1003
I_

.

ITMa: W
ITCal TLRll • R W

ITCaU,TLRUI: 'ROW

12

Not Used

959

Not Ulid

SlBF
SlCO

960
Stack
1840191tS)

I01F

3

1023

SlFF

•

; Reid Only
W : Write OnlV
Atw : Read/WtI18

Two reg.ster•• re mapped on same .ddr....

Ret.

Timer/Event Counte, BLower ITCBll

R

Timer lOid

Lower ITlRll

W

SOCIA

Timer/Event Counte, B Upper

R

Timer Loed Reg. Upper ITLRUI

W

aooo

ITCBUI

HD614P180.
o

u

SOOO

1

RAM·mapped ReglSll'S

31
32
Memory Reg.st,rs(MRI

47

48

------------------------

SOIF

2

rs~O

3
4
5
6

S02F
S030

1000
1001
$002
1003

In..,f'UP1 Control Bits

Pan Mode Reg.

IPMRI.

W

NOI U....
NotU....
Not U....

i
8

.

HOI U....
ITMIIII W
ITCal TLRlI I RIW
ITCaU/TLRUI • II/W

9 Timer Mode Reg, •

081.

10
TlMER·a
11

1928 Dig••,

Slack

$OIF

3

(84 DigitS)

1023

1-

Not U_

S38F
SlCO

959

1000
$000
$007
$000
1001
IOCIA
$OOC

12

960

a_

SlFF

• Two relllSllrs ar. rntpped on ume add'....

A

: Aead Only

W

: Write Only

R/W : Re.d/Wrlt8

Timer/Event Counter 8 Lower ITCall

R

Ttmet LOld RIO. Lower ITlIIll

W

$OCIA

Timer/Event Counte' 8 Upper ITCaUI

II

Tllner laid ..... Upper ITlRUI

W

1000

HD40P4181

Fig. 11-2 RAM Memory Map

354 HITACHI

bit 3

bit 2

bit 1

bit 0

IMO
(1M of iRT;)

IFO
(IF of iJiIT;)

RSP
(Reset SP Bit)

I/E
(Interrupt Enable Fleg)

sooo

Not Used

Not U..d

IMI
(1M of iNr,)

IFI
(IF of INT,)

$001

2

Not Used

Not U..d

IMTB
(1M of TIMER·B)

IFTB
(IF of TlMER·B)

$002

3

Not Used

Not Used

Not U..d

Not Used

$003

o

IF Int.lrrupt IIoquoIt Flog
1M In..,rupt M ....
liE I....'rupt En_ Flog

(Note)

SP Stack Point.r

Fig.

12~3

Configuration of Interrupt Control Bit Area

Memory Registers
980
MRIO)
$ 020
MRll)
S 021
MR(2)
S 022
MR(3)
S 023
MR(4)
S 024
MR(6)
S 026
MR(8)
S 028
MR(7)
$ 027
MR(8)
$ 028
MR(9)
$ 029
MRClO) $ 02A
MRlll) $ 028
MR(12) S 02C
MR(13)
$ 020
MR(14)
$ 02E
MR(16)
$ 02F 1023

32
33
34
36
38
37
38
39
40
41
42
43
44
46
48
47

Each bit in Interrupt Control Bits Area is set by SEM/SEM 0
instruction, is reset by REM/REMO instruction and is tested
byTM/TM 0 instruction. It is notaffected by other instructions.
Furthermore, Interrupt Request Flag is not affected by SEMI
SEM 0 instruction. The content of Status becomes invaid
when "Not Used" bit is tested.

Steck Are.
Level 18 S3CO
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level
Level
Level
Level
Level
3
I.evel
Level
2
Level I S3FF

bit3

'V
~

""

1022

1023

bit2

pc,;

ST
_I
PC,.
CA
I

Pc.

pc,;-

S3FC

Pc.

pc,

UFO

I

PC.

S3FE

I

Pc.'

S3FF

I
L

I

_I

I

PC.

I

PC.

_I

PC,.

pe;1
liCe

bitO

bitl
I

I

PC,

I

PC,.-PC.; Program Counter
ST;Stetua
CA;C.rry

Fig. 12-4 Configuration of Memory Register, Stack Area
and Stack Position

HITACHI 355

12.4 Precautions on using EPROM on Package Type Microcomputer
Since the HD6l4P180S/HD40P4l8l has a special structure with pin sockets
installed on the surface of the package, the following should be noted
when using it.
(1) Do not apply an electrostatic voltage or surge voltage more than the
maximum ratings to the pin socket pins.

This may destroy the LSI

permanently.
(2) When installing this LSI in system products in the same way as the mask
ROM 4-bit single chip microcomputer, observe the following in order to
maintain good ohmic contact between EPROM pins and pin sockets.
(a) When soldering the LSI on a printed circuit board, keep pin
conditions under 250°C within 10 seconds.

If these conditions

are exceeded, the solder fixing the pin sockets may melt and the
pins may fallout.
(b) Keep out detergent or coater from the pin sockets during flux
removal or board coating.

Flux or coater may decrease pin socket

contactivity.
(c) Avoid permanent use of this LSI in places with excessive vibration.
(d) Since repeated insertion/removal of EPROMs may decrease pin sockets'
contactivity, it is recommended to use new ones for your system
products.

356 HITACHI

12.5 Absolute Maximum Ratings
Symbol

Item
Supply Voltage

Vee

Terminal Voltage

VT

Total Allowance of Input Currents
Total Allowance of Output Currents
Maximum Input Current

1:10
-1:10
10

Maximum Output Current

-10

Operating Temperature
Storage Temperature

Top,
T.,g

Value
-0.3 to +7.0
-0.3 to Vee +0.3
Vee -45 to Vee +0.3
50
150
15
4
6
30

...

..

-20 to +75
-55 to +125

Unit
V
V
V
mA
mA
mA
mA
mA
mA
·C
·C

Note

3
4
5
8
7,8
9,10
9,11
9, 12

Permanent damage may occur If Absolute Maxtmum Ratings are excllded. Normal operetlon should be under the conditions of
"Electrical Characteristics" . If these conditions are exceeded, it mlY cauM the malfunction and affect the r.liability of LSI.
lNote21 All volt_ ere with , _ t to GND.
INote31 Applied to standard pinl.
INote41 Applied to high volteP pinl.
INote51 Total allowance of input current il the total sum of input current which flow in from all 110 pins to GNO simultaneously.
INoteSI Totl' allowance of output current il the totelsum of thl outpUt cumtnt which flON out from Vee to an 1/0 pinl simultaneously.
INote71 Maximum input current il the maximum amount of input current from uch 1/0 pin to GNO.
INoteSI Applied to D. - Os Ind R3, R4
INote91 Maximum output current il the maximum amount of output current from Vee to each 1/0 pin.
INotelOI Applied to D. -D •• nd R3, R4.
INotelll Applied to RO - R2.
INotel21 Applied to 0",-°1",

INote11

HITACHI 357

12.6 HD614P180 Electrical Characteristics
(1)

DC Characterlstici (Vee· 4.5V to 5.5V. GND· OV. Ta· -20 to +75°C. if not specified.)
Value
Item

Symbol

Pin Name

Tast Conditions

RESET.
Input "High"
Voltage
Input "Low"
Voltage
Input/Output
Leakage Current
Current
Dissipation in

Not.

Vee+O.3

V

~!-'-

-0.3

-

O.22Vee

V

OSC I

-0.3

-

0.5

V

-

-

1

,.A

1

-

-

2.0

rnA

2.4

-

-

1.2

mA

3.4

-

-

0.9

mA

4,5

-

-

10

,.A

2

-

-

V

INTO. INTI

RESE~
I.
llilTo•
OSC I

IIILI

Unit

-

0.7Vee

OSC I

VIL

mex

Vee-o.5

l'N'fQ.~

VIH

typ

min

Vin - OV to Vee

Vee+0 .3

V

VCC-5V
lee

VCC

Active Mode

IsaYl

VCC

fosc • 4MHz, divide-by..a
Maximum
Logic
Operation
VCC- 5V

f05C = 4MHz, divide-by..a
Current
Dissipation in
Standby Mode
ISBY2

VCC

Minimum
Logic
Operation
Vee-5V

fosc = 4MHz, divide-by..a
Current
Dissipation in

1-

Vee

V_

Vee

Stop Mode

Stop Mod.
Retain Voltage

Vln

(TeST) -

vee-0.3V to Vee

VI~ (RESET) - OV to 0.3V

(Note 11 Output buffer current ara ..cluded.
(Note 21 The MCU is in the reset stlte. The input/output current doe. not flow.
T.st Conditions: MCU state;
• Reset Itate in Operation Mode
Pin state;
• RESET. TEST '" Vee voltage
• 0.-0" R3- R4 ... Vee voltlge
• D. -0, •. RO-R2. RAI ... VCC -VCC-40V
(Nato 3) The timer/counter with the fastest clock Ind input/output current doel not flow.
Test Conditions: MCU state;
• Input/Output; Reset state
(Note 4) The timer/counter with the slowest clock and input/output current doel not flow.
Tast Conditions: MCU state;
• Standby Mode
• Input/Output; Raset state
• TIMER-B;+204B preseller divide ratio
Pin stato;
• RESET ... GND voltage
• 'i'ES'f ... VCC voillge
.0,-0,. R3-R4 ... Vee voillge
• D. -0, •• RO-R2. RA 1 ... VCC - Vee-4OV
(Note 6) When fo1c·x (MHz1. the Curr.nt Dissipation In Operation mod. end Stendby mode
ma•. value (fooc:=x[MHz) )_; x max. vllue (fosc.4[MHz))

358 HITAOH.I

.r.

_Imeted .. followa:

(2) Input/output characteristics for standard pin
Nec = 4.5V to 5.5V, GND = OV, Ta = -20 to +75°C, if not specified.)
Item
Input "High"
Voltage
Input "Low"
Voltage
Output" Low"
Voltage
Input/Output
Leakage Current

Symbol
V ,H
V,L
VOL
jllLI

Pin Name

Do - 0 3.
R3- R4
Do - D3.
R3- R4
Do - D3.
R3- R4
Do - D3.
R3- R4

Value

Test Conditions

Unit

max

min

typ

0.7Vee

-

Vee+ 0.3

V

-0.3

-

O.22Vee

V

10L = 1.6 mA

-

-

0.4

V

Yin = OV to Vee

-

-

1

Il A

Note

1

(Note 1) Output buffer current are excluded.

(3) Input/output characteristics for high voltage pin
(Vee· 4.5V to 5.5V, GND = OV,Ta = -20 to +75°C, if not specified.)
Item

Symbol

Pin Name

Value

Test Conditions
min

typ

max

Unit

Input "High"
Voltage

V ,H

0 4 - 0,4, R1.
R2. RA1

0. 7Vee

-

Vee+0.3

V

Input "Low"
Voltage

V ,L

0 4 - 0,4. R1.
R2. RA1

V ce -40

-

0.22Vee

V

-

V

V

/J.A

0 4 - 0'4
Output "High"
Voltage

VOH
RO- R2

Output "Low"
Voltage

VOL

Input/Output
Leakage
Current

II,d

0 4 - D'4.
RO- R2
0 4 - 0,4.
RO- R2.

-IOH -15mA

Vee-3.O

-IOH -9mA

Vee -2.0

= 3mA

-IOH -1.8mA

Vee-3.O
Vce -2.0

-

150kn to Ve e -40V

-

-

Vee -37

-

-

20

-IOH

Yin

= Vec-40V to Vee

Note

V
V
V

1

R"

(Note 11 Output buffer current are excluded.

HITACHI 359

(4) AC characteristics (Vee = 4.5V to 5.5V, GND = OV. Ta = -20 to +75°C, if not specified.)
Symbol

Item
Oscillation Frequency

10..

Instruction Cycle Time

tcyc

Oscillator Stabilization
Time
External Clock "High"
Level Width

0.4

4

4.5

divided·by-8

1.78

2

20

/JS

-

-

20

ms

1
2

MHz

100

-

-

ns

asc,
asc,
asc,

divided·by-8

100

-

-

ns

2

-

-

20
20

ns

2
2
3
3

t CPf

t,lilt:<

INTo "Low" Level Width

t'OL
t'1H

"Low" Level Width

divided·by-8

divided-by-8

iNTi "High" Level Width

fIiII,

RESET "High" Level Width

t'1L
tRSTH

Input Capacitance

eln

RESET Fall Time

tRST!

TNIo
'iNTO
'iNTi
'iNTi

-

all pins

-

-

-

15

pF

-

-

20

ms

2

2
2
2

RESET
l=lMHz
V,n = OV

ns

-

- - ~2..

-

teve
tcye
teve
tcye
tcyc

(Note 1) Oscillator stabilization time is the time until the oscillator stabilizes after Vee reaches 4.5V at "Power~on". or after RESET
input level goes to "High" by resetting to quit the stOp mode by MeU reset on the circuits below. At power ON or recovering
from stop mode, apply RESET input more than tRC to obtain the necessary time for oscillator stabilization, When using crystal
or ceramic filter oscillator, please ask a crystal oscillator maker's or ceramic filter maker's advice because oscillator stabilization
time depends on the circuit constant and stray capacity.
Crystal oscillator

Ceramic filter oscillator

Ceramic filter: CSA4.00MG (Murata)
RI: lM!1I,2%
C, : 30pF ± 20%
C, : 30pF ± 20%

Crystal: 4.194304MHz NC·l8C (Nih on Oenpa Kogyo)
RI:1M!1,2%
C, : 22pF ± 20%
C, : 22pF ± 20%

lNote 2)

lNote 3)

asc,
1CPr

(No,e41
RESET

360 HITACHI

1CPf

Note

max

asc,

tCPr

--

Unit

typ

tCPH

External Clock Rise Time
"High·:.Le~l'Iidth

Value
min

tRC

tCPL

External Clock Fall Time

asc,. OSC,

Test
Conditions

asc,. asc,

External Clock "Low"
Level Width

__lmO

Pin Name

3
3
4

4

(5) Characteristics curve (reference data)

4 Ta=-20- +75'C

4

;(
E

fosc=4MHz

T8=-20-+75"(;
Vcc=5V

3

max

3
max.

u2
.::

,

-

o

2

~

~

o

.!!!

-

~ 0.8

.!!!

0.4

2.0 Ta--20-+75,(;
fosc=4MHz

ISBY'
max.

----

o

2

6

Icc vs. Vcc characteristic
(crystal, ceramic resonator)

Ta=-20-+75"(;
Vcc=5V

E
] 1.2

5

VcdV)

fose( MHz)

<,.6

4

3

2

5

4

3

ICC vs. f asc characteristic
(crystal, ceramic resonator)
2.0

V

.7

./

1.6

E
~ '.2

./'

~

IsaY1

«

7

.ll
"""'i'SBY2
max .

./

~ 0.8

l/x.
VIsaY2
max.

.!!!

0.4

3

o

5

4

2

4

3

5

6

Vcc(V)

fose(MHz)

Isay vs. Vcc characteristics
(crystal, ceramic resonator)

Isay vs. f asc characteristics
(crystal, ceramic resonator)
5

30

Ta = -20 - +75°C

Ta = -20 - +75°C
VCC~5.5V/

VCCj5.5/

X

10

/
/ V
1//

5

/

~

.0c 6=4.5V
V

/

:--

/

20

E

c

~

'E

V(C-4·5V

V

::t:

/

0

T

1/

IV

0

/. V

/

/

W
1#

//

tr

J

/
o

V

V

2

VOL(V)
IOL min. vs. VOL characteristics
(Standard Pin)

3

o

4
2
3
5
VCC-VOH(VI
-IOH min. vs. (Vee-VoHI characteristics
(D. - 0 ,• pins)

HITACHI 361

6

Ta=-20 - +7S·C

5

Vc6=5.tV

4

/

1/

<
..§
C

'E

/

3

l/. /

I

-

/ ' 'VCC=4.5V

~V

:I:

0

....

?

2

./.. ;or

~~

".
oV
-IOH min.

lIS.

2
3
4
S
VCC-VOH(VI
(VCC-VOH) characteristics

(RO - R2 pins)

362 HITACHI

12.7 HD40P4181 Electrical Characteristics
(1) DC charleterillies (Vcc· 4.5V to 5.5V, GND· OV, Ta - -20 to +75'c, if not specified.)
Item

Input "High"
Voltage

Symbol

Pin Name

max

O.BVCC

-

VCC+0.3

V

VCC-O·S

-

Vcc+0.3

V

-0.3

0.3Vcc

V

0.3

-

0.5

V

Vin = OV to VCC

-

-

1

JJA

1

RESET

RESET,

TNT;),~

VIL

Note

typ

osc!
input "Low"
Voltage

Unit

min

i"fJ'Fo", TNT,

VIH

Value

Test Conditions

osc!
RESET.

Input/Output
Leakage Current

IIILI

Current
Dissipation in
Active Mode

ICC

VCC

VCC= SV
f ose = BM H z, d ivide·by·B

-

-

TBD

mA

2,4

ISBY

VCC

VCC= SV
fose = BMHz, divide·by·B

-

-

TBD

mA

3,4

Dissipation in
Stop Mode

Istop

VCC

Yin ('fESi') = VCC-0.3V to VCC
Yin (RESET) OV to 0.3V

-

-

10

JJA

Stop Mode
Retain Voltage

Vstop

VCC

2

-

-

V

TNT;), TN1";',
OSC!

~urrent

Dissipation in
Standby Mode
~urrent

=

(Note 1) Output buffer current are excluded.
(Note 2) The MCU is In the r...t .tat•• The input/output current does not flow.

Tlst Conditions:

MCU state;
Pin state;

•
•
•
•

Reset state in Operation Mode
RESET. mT ... Vee voltage
D. - 0,. R3 - R4 ... Vee voltage
D. - 0 ... RO - R2. RA1 .... Vee - Vee-40V

(Note 3) The timer/counter with the faltest clock and input/output current does not flow.

Tast Conditions:

MCU state;

• Input/Output; Reset state

(Note 4) The consumption of current in operation and standby mode is proportion to fose-

,When f olc - x (MHz), the value of each current is calculated.s follows.

max. valua (lose· xl - ~ x max. value (lose - 8[MHz]l.

HITACHI 363

(2) Input/output characteristics for standard pin
..
(Vee - 4.5V to 5.5V, GNO =OV, Ta = -20 to +75°e, if not specified.)
Item
Input "High"
Voltage

Symbol

Pin Name

Value

Test Conditions
min

typ

max

Unit

Note

VIH

Do - 0 3 •
R3- R4

0.7VCC

-

VCC+0.3

V

Input "Low"
Voltage

VIL

Do - 0 3 •
R3- R4

-0.3

-

0.3VCC

V

Output "Low"
Voltage

VOL

Do - 0 3 •
R3- R4

IOL = 1.SmA

0.4

V

IIILI

DO - 0 3 •
R3- R4

Vin=OV-VCC

-

-

Input /Output
Leakage Current

-

1

/lA

1

Unit

Note

INote 1) Output buffer current are excluded.

(3) Input/output characteristics for high voltage pin
(Vee = 4 5V to 5 5V GNO =OV Ta =-20 to +75°e if not spacified )
Item
Input "High"
Voltage
Input "Low"
Voltage

Symbol

Pin Name

Input/Output
leakage Current

HITACHI

max

O.7VCC

-

VCC+O·3

V

VIL

D. - 0 1. , Rl
R2. RAI

VCC-40

-

O.3VCC

V

-IOH = l5mA

VCC-3~O

-

-

V

-IOH = 10mA

VCC-2.0
VCC-l.0

-IOH=3mA

VCC-3.0

-IOH =2mA

VCC-2.0

-IOH -O.SmA

VCC-l.0

-

-

V

-IOH -4mA

-

l50kSl to V CC-40V

-

-

VCC-37

V

Yin = VCC-40V to VCC

-

-

20

p.A

VOH

VOL
IIlll

D. - 0 1•
RO - R2.

04

-

0 14

RO - R2. RA1

(Note 1 ~ Output buffer current are excluded.

364

typ

D. - 0 1•• Rl
R2. RAl

RO- R2

Output" Low"
Voltage

Value
min

VIH

D. - 0 1,
Output "High"
Voltage

Test Conditions

V
V
V
V

1

(4) Ae characteristics (Vee = 4.5V to 5.5V. GND = OV. Ta = -20 to +75°e. if not specified.)
Item

Symbol

Pin Name

Test
Conditions

Value
Unit

Note

min

typ

divided-by-8

0.4

8

9

divided-by-B

0.89

1

20

/1S

-

-

20

ms

1

max

Oscillation Frequency

fasc

Instruction Cycle Time

tcyc

Oscillator Stabilization Time

tRC

ascI. asc 2

External Clock "High"
Level Width

tCPH

ascI

divided-by-B

41

-

-

ns

2

External Clock "Low"
Level Width

tCPL

ascI

divided-by-8

41

-

-

ns

2

External Clock Rise Time

tCPr

ascI

15

ns

2

tCPf

ascI

-

-

External Clock Fall Time

-

15

ns

2

iNTo "H igh"

Level Width

tlOH

INTo

2

-

-

tcyc

3

ascI. asc 2

MHz

INT 0 "Low" Level Width

tlOL

INTo

2

-

-

tcyc

3

TNT;" "High" Level Width

tllH

INTI

2

-

-

tcyc

3

I NT I "Low" Level Width

til L

INTI

2

-

-

tcyc

3

RESET "High" Level Width

tRSTH

RESET

2

-

-

tcyc

4

I "put Capacitance

Cin

all pins

--

-

15

pF

RESET Fall Time

tRSTf

-

-

20

ms

f = lMHz
Vin = OV

4

(Note 1) Oscillator stabilization time is the time until the oscillator stabilizes after Vee reaches 4.SV at "Power-on", or after RESET input level
goes to "High" by resetting to quit the stop mode by MeU reset on the circuits below. At power ON or recovering from stop mode, apply
RESET input more than tRC to obtain the necessary time for oscillator stabilization, When using crystal or ceramic filter oscillator, please
ask a crystal oscillator maker's or ceramic filter maker's advice because oscillator stabilization time depends on the circuit constant and
stray capacity.
Ceramic filter oscillator

Crystal oscillator

Crystal: 8.388608MHz NC-18 (Nihon Denpa
Rf: 1Mn ± 20%
C 1 : 10pF ± 20%
C 1 : 10pF ± 20%

Ceramic filter: CSA8.00MT (Murata)
Rf: 1Mn±20%
C 1 : 30pF ± 20%
C 1 : 30pF ± 20%

KOQYo)

(Note

(Note 2J

3)

asc.
tCPr

tCPf

(Note 4)

RESET
O.2V cc

tRSTf

HITACHI 365

13. PROGRAM DEVELOPMENT PROCEDURE AND SUPPORT SYSTEM
13.1 Overview
The cross assembler and hardware simulator using various types of computers
are prepared by the company as supporting systems to develop user's programs.
User's programs are mask programmed into ROM and delivered as an LSI by
Hitachi.
Fig. 13-1 shows the typical program design procedure and Table 13-1 shows
system development support tools for the HMCS400 series used in this process.

CRT Editor

Cross Assetll.bler

~
H40OCMIX2
EPROM on package

type microcomputer
HD614P080S
HD614P0160S
HD614P180

HD40P4181
EPROM in package

type microcomputer
HD407400a

Fig. 13-1

Program Design Procedure

(De script ion)

(!)

When the user programs the system for the HMCS400 series microcomputer,
functional assignment of each I/O pin and allocation of RAM area in
accordance with the design system must be specified before actual
programming.

~ iA flowchart is prepared to implement the functions and is coded by using
the HMCS400 series' mnemonic codes.

366 HITACHI

~ Write a source program using the text editor and save it on a floppy disk.

~ Assemble and debug the source program and generate an object program.
~ Verify the program through hardware emulation with an emulator, H68SD5/5A,
H680SD200 or EPROM on package type microcomputer.
(]) Forward the completed program to Hitachi in the form of an EPROM.

Send

also "Single-chip microcomputer order specification" and "Mask option list"
at this time.

(i)

ROM and mask option are masked by Hitachi.
and the sample given to the user.

The LSI is tentatively produced

If the user does not detect any

programming programs, mass production can be started.

HITACHI 367

Table 13-1

System Development Support Tool

Ha r d ware System

HMCS402C/404C/408C
HMCS402AC/404AC/408AC
HMCS402CL/404CL/408CL

Partition
Emulator

H400CMIX2
HS408EML02H
HS408EMX22H

(Note 1)

EPROM on-package (Note 2)
type microcomputer

HD6l4P080S
HD6l4P0l60S

EPRON in-package (Note 3)
type microcomputer

HD4074008

(Note 1)

HMCS4l2C/4l4C
HMCS4l2AC/414AC
HMCS4l2CL/4l4CL

HD6l4P180
HD40P4l8l

-

Use the emulator with connecting to the H68SDS/SA or H680SD200.
Can be used in stand-alone.

(Note 2)

Specifications of power supply and mask option are not applicable.

(Note 3)

Specifications of power supply and mask option are not applicable
for the HD4074008.

Software
Host computer

Interface software

Cross assembler

H68SDS/SA

S400XAS3F (FDOSIII/IV) (Note 2)

S68EML1-F (Note 2)

H680SD200

S400XAS6M (CP/M-68k)

(Note 3)

S680EMLlF (Note 3)

INTELLEC® SERIES II
MODEL 220/230
VAX/VMS
IBM PC-DOS
HP64000
(Note 1)

S400MDSlF (for ISIS-II®)
S400MDS2F (for CP/M-80(!)
(Note 1)
S400VASlF
AS400PAIlSF

HMSI SW BOX

(Note 4)

S400MDS2F (for CP/M®)

S31IEM1-F (Note 4)
IN3EVM

(Note 5)

ISIS-II® is a registered trademark of Intell.
CP/M-68k and CP/M® are registered trademarks of Digital Research.

(Note 2)

This is included in the H400CMIX2.

(Note 3)

This is included in the HS408EMX22H.

(Note 4)

Overseas makers sell it.

(Note 5)

Sophia Systems Corp. sell it.

368 HITACHI

13.2

Development System

13.2.1

H68SD5A Development System

The H68SD5A is a development system capable of developing system programs
for the Hitachi 4-bit and 8-bit single-chip microcomputers.

It offers

high-level functions such as CRT display operations, assembler (based on
floppy disk), and debugging with emulator.

Software and hardware configura-

tions are shown in Fig. 13-2, 13-3, respectively.

Features
o Basic systems such as a CRT display, keyboard, and floppy disk drivers are
provided at a moderate price.
o Easy to debug hardware and software by emulator (option) suited for each
kind of MCU.
o The J68SD5A can perform system development through a CRT editor, assembler,
linkage editor, emulator, and EPROM writer (Note 1).
o System configuration corresponding to the purpose of development is provided
by easy connection of I/O devices such as a printer (parallel interface),
a console typewriter (serial interface), and an EPROM writer.

Serial

interface of the H68SD5A is completely provided with 3 circuits (1 circuit
for H68SD5).
o Allows program development of other products by exchanging emulator software.
Note 1)

Use the following EPROM writers available on the market.
AVAL CORPORATION; PKW-7000, PKW-1000
DATA I/O

29A, 29B

HITACHI 369

CRT editor

c::J Standard

configuration

_Expanded
configuration

Fig. 13-2 H68SD5 Software Configuration

I/O

Main module
1---- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

--I

I
I

I
I

I
I
I

I

I
I

I
I
I

I
I

I
I
I
I

QJ

c.J

...,01

'"

...,QJ
.....I::
o
......
1-1

I

I

I

I
I
:

I
I

~----------------------------------------------~
*1: Option
*2: User system

Fig. 13-3 H68SD5 Hardware Configuration

370 HITACHI

*2

*1

13.2.2

Development System H680SD200

The H680SD200 is a desk top type development support tool devoted to design
and develop application systems (4-bit, 8-bit, l6-bit micon system) which
make use of the l6-bit microprocessor HD68000.

Its front view is shown in

Fig. 13-4.
The H680SD200 consists of a CRT, two floppy disk drivers, and control
sections in one body.

The hardware configuration is shown in Fig. 13-5.

The H680SD200 incorporates parallel interface
and serial interface for EPROM writer.

(equiv~lent

to CENTRONICS')

The emulator for the HMCS404, HD630lX,

HD6301Y, and ASE for the real time emulator 68000, and ASE for the 64180
can be connected to the H680SD200.

Refer to Fig. 13-7 and 13-8.

Software configuration is shown in Fig. 13-6.

Assembler, C compiler, and

CRT editor operate under the operating system CP/M-68K®, and FORTRAN, super
PL/H (option) are provided as high level language compiler for the HD68000.
Features of the H680SD200 are listed below.
(1) General operating system CP/M-68K is applied.
(2) CRT editor which can edit on CRT display is equipped.
(3) 2M bytes of memory can be used by double sided floppy disk driver.
(4) C language, high level language for 68000 is equipped.
(5) High level language super PL/H and FORTRAN can be used for 68000 program
development.
(6) Real time emulator 68000ASE for 68000(12.5MHz max) and ASE for 64180 can
be used. (Option)
(7) Printer interface (equivalent to CENTRONICS') and EPROM writer interface
(equivalent to RS-232C) are provided to make printer-EPROM writer connection
easy.

Model PKW-7000/PKW-lOOO (EPROM writer of AVAL CORPORATION) and

Series 22, Model 29A (DATA I/O) can be connected.

(Option)

(8) Additional equipment of serial I/O board can supports emulator interface
to 4-bit or 8-bit device and VAX-II interface.

(Option)

(9) Assembler super PL/H is supported as 68000 symbolic debugger.

(Option)

(10) High speed operation can be realized using RAM disk.
CP/M-68K® is a registered trade mark of Digital Research.

HITACHI 371

Fig. 13-4 Front View of H680SD200

CJ
Standard
configuration

conf iguration

Fig. 13-5

*

SeJect 256k bytes or 2M bytes

Hardware Configuration
of H680SD200

r-----------------------------------,
I C¥ /M-68K
ICP /M-68K res ident module I :'
,
r-------------------J

-

__________ - ______ ...I

c:::::J

Standard
configuration

E xpanded
configuration

Fig. 13-6 Software Configuration of H680SD200
Cross macro
assembler

Fig. 13-7
372 HITACHI

Emulator

Emulator for 4-bit/8-bit
Singlechip

Macro assembler/Cross
macro assembler High
level language compiler
(16 bits)S-PL!H, FORTRAN

ASE

Fig. 13-8 ASE for 8-bit/16-bit Multichip

13.3

Emulator
This emulator is a completely integrated hardware and software development

system for Hitachi's 4-bit singlechip microcomputer HMCS400 series.

It

supports the following devices.
HMCS402C/CL/AC, HMCS404C/CL/AC, HMCS408C/CL/AC
HMCS412C/CL/AC, HMCS414C/CL/AC
HMCS424C/CL/AC, HMCS428C/CL/AC
The emulator develops application system by connecting to a host computer
or console.

It provides three system configurations depending on the

host computer or console.
o H400CMIX2 for H68SD5 or H68SD5A
o HS408EMX22H for H680SD200
o HS408EML02H for the host computers or consoles except for above.

13.3.1
o

Features

Designed to aid in development of software and hardware when connected
with the user system.

o

Can be connected with host system (H68SD5/5A, H680SD200, IBM-PC, etc.)
CRT console, and console typewriter.

o

Takes in and displays the result of the user program execution in real
time up to 2,048 cycles.

o

Provides eight external probes, which observe user system. operations with
real-time trace, useful as breakpoint conditions.

o

Provides HELP function to display all commands used in the emulator.

o

Can debug with the specified frequency.

HITACHI 373

o

Break function
- Enables to set four breakpoints by any combination of program counter,
instruction word, interrupt processing execution and external prove
state.
- Enables to execute continuously machine cycles 0 to 2000 after the above
breakpoint (trigger point).

o

Line assembler and disassembler
- Can display and/or change the user object program in mnemonics.

o

- Displays the user object program in the specified address in mnemonics.
Displays the address (in the user object program) of detected instruction.

o

Displays the execution time.

o

Displays the trace data for program testing.

o

Displays and/or changes MCU register, I/O ports and memory contents.

o

Program can be executed on RAM or EPROM based.
The H400CMIX2 (for H68SD5/5A)/ HS408EMX22H (for H680SD200)/ HS408EML02H

(for other host systems) emulator supports software and hardware when connected
with the HMCS400, 410, 420 series 4-bit Microcomputer Unit (MCU).
Normal development procedure is;
(1) make or change the user system,
(2) translate to user object program by 400 assembler on host system,
(3) download user object program through the serial interface,
(4) set the breakpoints at any conditions,
(5) execute real-time or single-step emulation from the specified address,
(6) display and/or change user object program in mnemonics, MCU internal
registers, I/O ports and internal RAMs,
(7) repeat steps (4) to (6) and upload to host system for debugging at
next time.
The emulator itself works as the object MCU.

The emulator is controlled

by host system, CRT console, or console typewriter.
BREAKPOINT FUNCTION
H400CMIX2/HS408EMX22H/HS408EML02H allow the user to set four break
conditions (TR, BRI to BR3) in the user program.

Each break condition

consists of PC (Program Counter) or AB (Address Bus), DB (Data Bus),
Interrupt an eight external probe signals.

When one of break condition is

detected, the emulator stops the user program, and displays the next PC, next
instruction, execution time, MCU register and I/O contents and internal RAM
contents.

TR, one of break conditions, stops the user program after

proceeding the machine cycles designated by COUNT if break condition matches.

374HITAOHI

REAL-TIME TRACE
H400CMIX2/HS408EMX22H/HS408EML02H can display execution results of up to
2047 machine cycles.

They have two display types, one is to display by the

instruction unit, the other one is to display by the machine cycle unit.

The

former one displays only program counter and instruction mnemonics, the latter
displays address bus, data bus, interrupt occurrence and eight external probes
in each machine cycle.
DISPLAY/CHANGE IN MNEMONICS
H400CMIX2/HS408EMX22H/HS408EML02H have two display and/or change commands.
One is I command which is executed in hexadecimal, the other is A command which
is executed in mnemonics.

Command A is very useful for debugging.

And

H400CMIX2/H408EMX22H/HS408EML02H display in mnemonic instruction.

They are

disassemble and display the object program in the specified address with DA
command.
DEBUG WITH A SPECIFIED FREQUENCY
H400CMIX2/HS408EMX22H/HS408EML02H allow some frequency.

The frequency is

expressed as the clock cycle in user's manual; the cycles should be
1.33~s,

2~s,

3~s,

than the above.

4~s,

5~s,

7~s,

10~s,

20~s.

l~s,

They won't allow other frequency

They select EXT by F command and input the specified

frequency to OSC pin.
COVERAGE TRACE
Coverage trace marks the passed address into coverage memory.
function is effective to know which address will be tested.
memory can't be cleared by "G" or
command.
memory.

"s"

Coverage

This coverage

command but can be cleared by CO RES

When starting the test of the user program, clear the coverage
For the next step, test the user program with G or S command.

S command execution marks the passed address into coverage memory.

G or

Check the

passed address and continue the test until all specified addresses were passed.
EXECUTION ON USER SYSTEM POWER SUPPLY
H400CMIX2/HS408EMX22H/HS408EML02H emulate on 3V to 5V.

Since H400CMIX2/

HS408EMX22H/HS408EML02H themselves work 5V ± 5%, connect VCC to
power supply for emulator.

However, since evaluation chip works on user

system power supply (3V to 5V), connect Vus to user system VCC
and Vdisp to power supply for display (0 to -35V).

HITACHI 375

Host
of I Evaluation
,
module
I

Main module

....----...,--r-- - --------l
I
I

I

User
system

'--T"""T~:

or

Console

cable
Coverage
tracer

L._

External probes
_ _ _.;;;;H..;.40~OCMIX2
Hardware Configuration of the Emulator

13.3.2 System Configuration
(A)

Connected with SD5/SD5A/SD200/IBM-PC/the other HOST

Afz---~-_~-:~~,;'

L- _ _ _ _ _ _ _ _ _ _ _

J

.t

(B)

H400CMIX2/HS408EMX22H
User I s System
/HS408EML02H
Connected with Console typewriter,(TTL level) or CRT console
(RS-232C level)

:7

Table 13-2 Connectable Console Typewriter
Company Name
CASIO COMPUTER CO.

TYPE
Typuter model 750-T-02

SHARP CO.

Sharpwriter model 300*

CITIZEN WATCH CO.

Protyper model 7652
*HITACHI Specification

376 HITACHI

13.3.3

Emulator commands

COMMAND
A
TR
BRI to 3
C

DESCRIPTION
Displays and modify object program in mnemonics.
Sets, displays and cancels breakpoints and trigger point.
Compares object program.

CO

Coverage tester

DA

Disassembler

F

Sets and displays clock cycle.

G

Executes user program.

HE

Displays the emulator command information.

I

Displays and modifies object program in hexadecimal.

ID

Dumps object program.

10

Displays and modifies I/O ports.

L

Loads object program.

M

Displays and modifies internal RAM.

MD

Dumps internal RAM.

N

Designates transfer rate.

0

Searches specified bit pattern.

P

Punches object program.

Q

Displays data of real-time trace.

R

Displays and modifies register.

S

Single-step trace of user program.

T

Transfers object program.

U

Sets and displays EPROM/user RAM.

V

Verifies object program.

HITACHI 377

13.3.4 Host connection configu1ation
Host

Configuration
OS:FDOS-Ill/IV
H400CMIX2,"

«:'""'
I.f'\H

Remarks

Item

CD

RS-232C Interface

Included

SDS/SA

Cable

in H400CMIX2

SIGNAL no
GND

@ Interface Program
SDS/SA:I
Ik1_---1

EML

S68EMLl-F

SEND

Cross Assembler

RECEIVE

S400XAS3F

RTS

_____ ..J

---~
I.f'\U

0«:
en..,

OOH
"'~
~'-'

cJ

2

G>--tt]

Q) Format converter
for

Provided by
HITACHI

H68SDS/SA++H680SD200
S68CNVl-F

OS:CP/M-68K

CD

HS408EMX22H
OH
N~

(;5~

EML

0

-----~

0'"

OOH

2

U

3

OS:PC-DOS

r.cii~-~~JI

U
;:E!iXl
iXlH
H '-'

EML

,S=]
<»----W

no SIGNAL

1-

I GND

~tx

2 SEND

:x

3 RECEIVE
4 RTS
5 CTS

GND

7-

7 GND

DCD

8

8 DCD

DTR

20

n= 20 DTR

Included
in

Interface Program
S680EMLlF

Same as above

Cross Assembler
S400XAS6F

Q) SIO Board

CD

HS408EML02H

i>-<
'""'
I;:E!

CTS

EMULATOR

HS408EMX22H

I

"'~
~'-'

RS-232C Interface
Cable

jD1@!,22
0:11

0'""'

I Cable Connection
Table

0

Included in

H680SIOIS

H680SD200

RS-232C Interface

Modify it

IBM-PC

Cable

according

SIGNAL

to the right

GND

Provided by

SEND

Interface Program
S31IEMI-F

Q) 400 Cross

EMULATOR

ro
I r--

HITEC-UK/

RECEIVE :[X

DESC

RTS

Provided by

CTS

Assembler for

HITEC-AS/

DSR

IBM-PC 400PASIIF

DESC

DTR
GND

:tx

no SIGNAL
I GND
2 SEND
3 RECEIVE
4 RTS
5 CTS

~~~

7t--

7GND

Host

Configuration
OS : VMS

Item

CD

HS408EML02H

Remarks

RS-232C Interface

Included in

Cable (1)

HS408EML02H

@ RS-232C Interface Connecting
Cab le (2)

.....

.....I U
--~~
;> .......

G) Switch Box *

®--ttl

®

CD

HS408EML02H
1

0

<-

1

no SIGNAL
1 GND

SEND

2 SEND
3 RECEIVE

Provided by

RTS

4 RTS

HMSI

CTS

5 CTS

400 Cro ss

Provided by

GND

7 GND

Assembler for

HITACHI

DCD

8 DCD

DTR

RS-232C Interface

Modify it

Cable

according

Interface Program
IN3EVM

Provided by
SOPHIA

G) 400 Cross
Assembler

G>-G]

SIGNAL no
GND
RECEIV

CP/M

IN-III

EMULATOR

GND

1 GND

SEND

2 SEND

RECEIV

3 RECEIVE

SIGNAL

RTS

10

zoo
H .......

EMULATOR

table is

to the right

HH
H::<::
HP-<

SW BOX

TBD •

VAX-ll S400VAS1F
OS:CP/M

1 Cable Connection
Table

Provided by
HITACHI

S400MDS2F

CTS

5 CTS

GND

7 GND

DCD
DTR

OS:CP/M,
ISIS-II

CD

Cable

HS408EML02H

--...l

00""
~~

8oo~

0

- ROM code *1
~Mask Option List*2
rDordering Specifications*3

1

Remarks
*1 Paper tape or 2 sets
of EPROM
*2 Style by each product
*3 Common style

Icomputer processing I

,

ROM code for confirmation of ROM fabricating
specifications*4

,

I

Mask

I

Sample

1

*4 The same ROM code as
delivered one.

OK
j2DConfirmation of resultl
*5

*5 Send it back after
partially approving

I
I

1
*6 Normally 2 or 3 pes.

IWOrking samP le*61

~Confirmation of function, characteristics
*7. *8

*7 Start the following
flowchart after approving
*8 Send them back after
approving with
specified form.

+

IEngineering Sample*9 II

*9 Normally 9 or 10 pes.
Confirmation of function,
characteristics, quality

+

ICommercial Sample

J

lEL)
(Note)

Please send inQ),Q), andQ) at ROM ordering, and send back ®,~ after
approving.

HITACHI 383

(2) Information to be submitted
(a) Ordering specifications; standard format for all Hitachi' single-chip
microcomputer devices.
the following items.

Please enter for
The format is shown

on the next page.
Basic ITEM
Environmental Check List
Check List of attached data
Customer
(b) ROM code; Include 2 sets of ROM code identical to the EPROM contents,
with ROM code No. entered on them.

A program listing

is desirable for easy confirmation of program contents.

(3) Change of ROM code
Note that if you change the ROM code once sent in or other specifications,
the ROM must be developed from the beginning.

The mask charge must be

applied again in this case.

(4) Samples and mass production
Working Sample; Sample for confirmation of ROM code and that of mask option.
Normally 2 or 3 samples are sent, but not guaranteed as for
reliability.

Please evaluate and approve immediately because

the following sample preparation and mass production are
determined after obtaining your evaluation.
Engineering Sample; Sample for evaluating device reliability.

10 pcs are

included in mask charge.
Commercial Sample; Sample for set trial production purchased with compensation.
Mass Production; Products for actual mass production.
mass production in full.

Please enter plan of

Refer to Single-chip Microcomputer

ROM Ordering Procedure (document No. HMCS·ORD-3M) for
details.

384 HITACHI

Single Chip Microcomputer
Ordering Specifications

(1)

Basic ITEM (Please fill in blanks or enter check marks: Microcomputer Family
Application (in full)
Function (in full)
ROM Code No.
ROM Code Media
Outline
Operating Temperature

OEPROM (ROM type name)
OFloppy
OPlastic DIP OPlastic flat package
OStandard
OJ specification (guarantees -40°C '"
+85°C)

Options

(2)

Environment Check List
This check list is used as data of single chip microcomputer LSI's design

reliability, but not used to control its performance assurance.

Please enter

usual environmental conditions.

Microcomputer Ambinet Temperature

average

°c

range

°c

Microcomputer Ambient Humidity

average

%

range
average

%

Power ON Duration
Max. Applied Voltage to
Microcomputer

power
supply
I/O

°c

'"

%

'"

hours/day
max.

V

max.

V

0500 fit 01000 fit
01.0 % 00.65 % 00.4 %

Target Level of Re liabi li ty
AQL
Remarks

Check List of Attached Data (Please fill in blanks or enter check marks:-

(3)

I

I

ROM Code
Mask Option List

o Attached
o Attached

ODelivered

o Delivered

o Delivery
o Delivery

data
data

Date of Order
Customer

*

For Hitachi's use only

LSI Type No.

Dept.
Accepted by

Shipping Date of ROM Fabricating
specifications
Approved Date of ROM Fabricating
Specifications

HITACHI 385

HMCS402C/AC/CL

Date of Order

1HMCS404C/AC/CL ·1
MASK OPTION LIST

Isv

Customer
: OHMCS402C,

Operation

I High
13V

Speed Operation

:OHMCS402AC,
:OHMCS402CL,

Oper at ion

OHMCS404C I
o HMCS404AC I
o HMCS404CL I

(.,x,v).

I/O OPTION

INPUT/OUTPUT

PIN

ROM Code Name

Note (I/O options masked by • are not available.)

I/O Option

(1)

Name
LSI Type Number
(Hitachi's entry)

Please enter check marks in 0

*

Dept.

.

A B C D E

PIN

.....0: Input /Output
'"."... Input/Output

DO
Dl

..

D2

."

D3

til

.,~

Input/Output
Input/Output

DS

Input/Output I····
Input/Output

..
.....
'"..
..

D7

0:

DS

00

.,

D9

~
R32
R3 r - R33

Input/Output

Input/Output

RS I RS2

Input/Output

RS3

::c Input/Output
Input/Output

D14

Input /Output

DIS

Input/Output

R60
I--R6l
R6
I R62
f--

R63
R70

R7

Ro2

RQ3
RIO
Rl

R2

Output

..
...

~

Output

.....0: Input/Output
....

Rl1
.,
R12 ....
-=g
RU

00

Input/Output

I

I·

I'·'

..
I.n ..

.

Input/Output
Input/Output

~

Input/Output
Input/Output

-R71
-R72
-R73

f-f--

'"...

Output

."

Output

."

Output

..

.,~

til

.' ......

p.

r

Output
Output
Output
Output

Rat

Output
Output
Input

-R91
R9 -

Input
Input

R93

Input

RAO
RA
'RAI

Input

~

••

Output

Output

R90

f-I--

..

.....0:

Output

-RS2

.....

Input/Output

IlS0

Rii3

Input/Output

R2l

R23

RS

.

fo Input/Output
~ .....
::c
t---

*

Output
Output

Input/Output

f--

.....

DU

RO

Input/Output
Input/Output

..c:00 Input/Output

~
~

Input/Output

-R43

RSO
I RSI

D11

I

Input/Output

Input/Output

....
g

.'.

.'

Input/Output

R4l
R4 I--R42

Input/Output

....

Input/Output

f--

Input/Output

D10
D12

Input/Output
Input/Output

R40

D4
D6

A B C D E

~

Input/Output

I/O OPTION

INPUT/OUTPUT

Input

Please ar
on RAI /V disp

Please enter "0" in applicable item for I/O option selection.
A; Without Pull-up MOS (NMOS Open Drain)

B; With Pull-up MOS

C; CMOS (not be used as Input)
D; Without Pull-down MOS (PMOS Open Drain)

386 HITACHI

E; With Pull-down MOS

Package

(3)

Package

·
RA1/V d ~sp
ORA1:Without Pull-down MOS (D)

0 DP-64S (shrink package)

o Vdisp

0

*

Please enter check marks (., x,,,;)
in applicable item.

Note)

FP-64

*

Please enter check marks (., x ,v )
in applicable item.

RA1/Vdisp has to be selected as Vdisp pin exept the case that all High
Pins are option D

(4)

Divider (DIV)

(5)

Clock divide ratio

•

ROM Code Media

Divided-by-8

0 EPROM: Emulator Type
0 EPROM: EPROM On-Package Microcomputer
Type

Check List of Application
(A)

Oscillator (CPG option)

o 402C/404C

----

::::J 402CL/404CL
o 402AC/404AC
(5V Operation)
(High Speed Operation)
(3v Operation)
::::JResistor (Rf-2Okn+2%)

CPG
option

*

o Ceramic Filter
o Crystal
o External Clock

o Ceramic Filter
o Crystal
o External Clock

o
o
o

Ceramic Filter
Crystal
External Clock

Please enter check marks (., x,V') in applicable item.

HITACHI 387

I

HMCS408C/ AC/ CL

MASK OPTION LIST

Isv

I

Speed Operation

[3V Operation

*

Customer

I

:OHMCS408C

Operation

I High

Date of Order

I

: 0 HMCS408AC
:0 HMCS408CL

I

(.,x,v).

DO

....'"c::

Input/Output

."

Input/Output

'"...
§...'"

DI
D2
D3

I/O OPTION

en

Input/Output
Input/Output

D6

Input/Output

D7

....'c::" Input/Output

'"
...
.....'"

D8

OJ

00

DlO

0

>

DU

B

E

....tIl

Input/Output

Dl3

Input /Output

Dl4

Input/Output

DIS

Input/Output

Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output

R60

'R6l ...."'"
R6
'R62 '"...
R63 '"

..

...

r--R71

~
~
RO

Output

RiD" '"
RlO ...."
'"
RI Rl1
-=-=- ...
.....'"
-Rl2
g.
Rl3
OJ

00

~

R22
i-='R23

*

."

Output

. ....

Output
Output
Output

IR73

Output

R80

Output

.

Output
Input/Output
Input/Output
Input/Output

R8 ~
IR82

...•....

.c.

.

.

Input/Output
Input/Output
Input/Output

Output
Output

IRR3

Output

R90

Input

I--

Input/Output

....~ Input/Output
tIl

...

Input
Input

R91

•

1. [ • .•~• •. • •

-

-R9 IR92

IR93

.

RAO
RA
~~c:
IRAI ~ ~~

Input
Input
Input

P ease ~ar~
on RAI /Vdisp

Please enter "0" in applicable item for I/O option selection.
A; Without Pull-up MOS (NMOS Open Drain)

B; With Pull-up MOS

C; CMOS (not be used as Input)
D; Without Pull-down MOS (PMOS Open Drain)

388 HITACHI

......

•••

Output

Ro2

R2 IR20
R21

Output
Output

R7 I - R72

f

Output

."

...~
en

R70

Output

E

Inpu t / Ou tpu t

RSO

00

C D

Input/Output

Rs1
RS R52
Rs3

Input/Output

B

Input/Output

R42
R43

Input/Output

I/O OPTION
A

Input/Output

R31
R32
R3 R33
R40
R41
R4

Input/Output

not available.)

Input/Output

~

..c:: Input/Output

Dl2

rn are

INPUT/OUTPUT

PIN

C D

Input/Output

DS

D9

A

Input/Output

D4

ROM Code Name

Note (I/O options masked by

INPUT/OUTPUT

PIN

Name
LSI Type Number
(Hitachi's entry)

Please enter check marks in 0

I/O Option

(1)

Dept.

E; With Pull-down MOS

Package
Package

RA1/V d ·
lSP
DRA1:Without Pull-down MOS (D)

0 DP-64S (shrink package)

DVdisp

0 FP-64

*

*

Please enter check marks (., x,../)
in applicable item.

Note)

Please enter check marks (., x ,v )
in applicable item.

RA1/Vdisp has to be selected as Vdisp pin even if one high voltage
pin is specified as "E".

(4)

Divider (DIV)

(5)

ROM Code Media
0 EPROM: Emulator Type

"LJ

EPROM: EPROM On-Package Mic rocomputer
Type

Check List of Application
(A)

CPG
option

*

Oscillator (CPG option)
DHMCS408C
(5V Operation)
o Ceramic Filter

D HMCS408CL
;:] HMCS408AC
(High Speed Operation)
(3V Operation)
D Ceramic Filter
o Ceramic Filter

o Crystal
o External

o Crystal
Clock

C External Clock

o
o

Crystal
External Clock

Please enter check marks (., x, v) in applicable item.

HITACHI 389

I

,I

HMCS412C/AC/CL
HMCS414C/AC/CL
MASK OPTION LIST

lsv

Operation

I High Speed Operation
13v Operation

*

:OHMCS412C,
:OHMCS412AC,
:0 HMCS412CL,

o HMCS414C I

Dept.

0
0

Name

HMCS414AC
HMCS414CL

Please enter check marks in 0
(.,x,v").

I/O Option

(1)

Date of Order
Customer

I
I

ROM Code Name
LSI Type Number
(Hitachi's entry)

Note (I/O options masked by iii are not available.)
INPUT/OUTPUT

*

Please enter "0" in applicable item for I/O option selection.
A; Without Pull-up MOS (NMOS Open Drain)

B; With Pull-up MOS

C; CMOS (not be used as Input)
D; Without Pull-down MOS (PMOS Open Drain)

E; With Pull-down MOS

RAlI Vd lSP
·
DRAI:Without Pull-down MOS CD)

o Vdisp

*

Please enter check marks C., X,";)
in applicable item.

Note)

RAl/Vdisp has to be selected as Vdisp pin even if one high voltage
pin is specified as "E".

(3)

Divider CDIV)

(4)

ROM Code Media
0 EPROM: Emulator Type
0 EPROM: EPROM On-Package Microcomputer
Type

Check List of Application
CA)

CPG
option

*

Oscillator CCPG option)

o HMCS4l2C/ 4l4C

CSV Operation)
o Ceramic Filter

;:J HMCS4l2CL/4l4CL
DHMCS4l2AC/4l4AC
CHigh Speed Operation)
(3V Operation)
o Ceramic Filter
o Ceramic Filter

o Crystal
o External

o Crystal
o External

Clock

Clock

o
o

Crystal
External Clock

Please enter check marks C., x,v') in applicable item.

HITACHI 391

HMCS400 SERIES

Section Two

Software
Application Notes

HMCS400 SERIES

Section Two

Software
Application Notes

400-3-02

PREFACE
HMCS400 is a series of 4-bit single chip microcomputers using an
innovative CMOS high breakdown voltage process.

This series is much

improved over the HMCS40 series in such areas as direct drive of fluorescent character display tube, operating speed, functions, and program development.
APPLICATION NOTES consists of typical application programs for the
HMCS400 series to help users better understand the instruction set and to
provide them with references for making more customized programs.
Programs described in APPLICATION NOTES have already been debugged.
However, please verify operation in actual use.

For additional information reference:
-Section 1, HMCS400 Series User's Manual
-Section 3, HMCS400 Series Hardware Application Notes

CONTENTS
Page

1.

2.

Application Programs Explanation Format .•....•.••.•...••.....•.

3

1.1

5

Symbols ..•........ ·..••.••.••.••.•••..•.•.•.•.•..••.••.•.••

1.2

SPECIFICATION Section

1.3

DESCRIPTION Section

1.4

FLOWCHART Section

1.5

PROGRAM LISTING Section

6
11

........................................
...•........••••....••.•.....•••..

16

17

Program Execution .••..........•••..••.•...•.••••••....•••.••••

18

2.1

Calling Programs in APPLICATION NOTES from User Programs ..•

18

2.2

Modifying Programs in APPLICATION NOTES According to
User Requirements

20

DATA TRANSFER
1.

FILL WITH A CONSTANT VALUE (FILL)

25

2.

MOVE DATA BLOCK (MOVE) ......•....•...•..•......•..••....•...•..

31

3.

MOVE STRING (MOVES) ••..••..........•.•..•....•.......•.••.•....

38

TABLE BRANCHING

4.

BRANCH FROM TABLE (CCASE)

.....................................

46

ASCII CONVERSION

Page

5.

CONVERT ASCII LOWERCASE INTO UPPERCASE (TPR)

••••••••••••••••••

54

6.

CONVERT ASCII INTO 1-DIGIT HEXADECIMAL (NIBBLE) ••••••••••••••••

59

7.

CONVERT 8-BIT BINARY DATA INTO ASCII (COBYTE) •..•••••••.•••..••

64

BIT MANIPULATION

8.

COUNT LOGICAL "1" BITS (HCNT)

9.

SHIFT 8-BIT DATA (SHR)

••..•.•••.•....••..•••.••••...•••

71
77

COUNTER

10.

4-DIGIT BCD COUNTER (DECNT)

.••.. , ••. . . • . . • . •••••••• . ••• . •• • .••

83

DATA COMPARISON

11.

COMPARE 8-BIT BINARY DATA (CMP)

.•..•••.•••.•.••••••...••••.•••

89

ARITHMETIC OPERATIONS

12.

ADD 8-BIT BINARY DATA (ADD)
BINAR~DATA

. • • • • .• . • • • . . • • . • • • • • • . • . • • • . • • • • • • 95
(SUB) •.•••..•••••....•••••.•••.•••• 102

13.

SUBTRACT 8-BIT

14.

MULTIPLY 16-BIT BINARY DATA (MUL)

109

15.

DIVIDE 16-BIT BINARY DATA (DIV)

118

16.

ADD 8-DIGIT BCD (ADDD)

126

17.

SUBTRACT 8-DIGIT BCD (SUBD)

18.

16-BIT SQUARE ROOT (SQRT)

•.•..••.•••••••.•.••••••.••••••. .- •• l33
•••••••••.•••.••.•••••.••••••.••••••• 140

BCD/HEXADECIMAL CONVERSION

Page

19.

CONVERT 2-BYTE HEXADECIMAL INTO 5-DIGIT BCD (HEX)

20.

CONVERT 5-DIGIT BCD INTO 2-BYTE HEXADECIMAL (BCD)

151
159

SORT FUNCTION

21.

SORT (SORT)

•••.••..•••••••.••••••.•.••.••..••••.••..•••••.•••• 169

Symbols and Abbreviations

.•......•..••.•••.......•......•.••.• 181

Symbolic Operands Used with Instruction Set Mnemonics ••••....•• 182
Immediate Instruction
183
Register-to-Register Instruction .•..••.•.••••••.•.•.•••••..•.• 183
RAM Address Instruction

183

RAM Register Instruction

184

Arithmetic Instruction

185

Compare Instruction
RAM Bit Manipulation Instruction
ROM Address Instruction

186
..•••••••••..•..••.••.•..••..• 186

. . . . • . . . • . . • . • • . • • • • . • • • . • • • • . • . . • . . • .• 186

Input/Output Instruction

186

Control Instruction

187

Op-Code Map

187

GUIDE TO USING THE HMCS400 SERIES
APPLICATION NOTES

1.

Application Programs Explanation Format

1
1

Explanation of each program in APPLICATION NOTES is divided into four
sections as shown in Fig. 1.1.

Section 1 - - SPECIFICATION

FUNCTION
ARGUMENTS
CHANGES IN CPU REGISTERS AND FLAGS
SPECIFICATIONS
SPECIFICATIONS NOTES

Section 2 - - DESCRIPTION

Function Details
User Notes
RAM Allocation
Sample Application
Basic Operation

Section 3 - FLOWCHART
Section 4 - PROGRAM LISTING

n:oolWl ~ISTlIIC

Fig. 1.1

n

Program Description

HITACHI

3

Programs in APPLICATION NOTES can be implemented in two ways, i.e.
(1) without modification or (2) with modification.
(1)

To use a program without modification, you will need:
(a)
(b)

The information in section 1
Function Details, User Notes, RAM Allocation and Sample
Application in Section 2

(c)
(2)

PROGRAM LISTING in Section 4

To modify a program, you will need:
All the information in Section 1 to 4; after reading these sections,
change the PROGRAM LISTING according to user specifications.

4 'HlTACHI

1.1

Symbols
Symbols and abbreviations used in APPLICATION NOTTES are described below.
(1)

Operation
Contents
a .... b

Transfer from "a" to "b"

a +-+b

Exchange between "a" and "b"

+

Addition

x

Multiplication

Subtraction
Division
(2)

Register symbols in MCV
A

Accumulator

B

B Register

W

W Register

X
y

Y Register

X Register

SPX
Spy
(3)

(4 )

SPX Register

=

SPY Register

Flag symbols in MCV
CA

Carry

ST

Status

Comparison sign
Equal

f.

Not-equal

>

Greater than

<

Less than

,;;; Greater than or equal
~

(5)

Less than or equal

Others

, ,

Delineates ASCII characters
Indicates labels of successive addresses

$

Indicates hexadecimal data

MD($***)

Specifies a digit in address space ($*** indicates

MR($*)

Specifies a digit in memory registers ($* indicates

address) •
address).

HITACHI

5

1.2

MSD

Most significant digit in address space

LSD

Least significant digit in address space

SPECIFICATION Section
I ___________ J
The SPECIFICATION Section is shown in Fig. 1.2 (:-----------':
blocked area

in Fig. 1.2). Each numbered item in the figure is described below.

(4)

(5)
Seor_se

No. of

f-_.,'_·"_'"_"_"_..,.::L.""",a'c!!l':::."p.,:o;,l::.,a'-! :: ::~.~!!::Ud
*:

Result

1 word-10 bits
ROM Words

Entry

SP

spy

ita

Stack

D

No. 0

c c e.

LeA

ST

Interru t OK1
DESCRIPTION

1- --- -- ---------- - - ----- - - - -----------,
(8)

1

T~IFI~Tl~S

~-

MOT'S

--

---~

Fig. 1.2

6.HITAOHI

I I

I

SPECIFICATION Section

(1)

ITEM NUMBER AND PROGRAM NAME:
Example:

(2)

19.

SHIFT 8-BIT DATA

MCU:
Indicates names of microcomputer series applicable to
the program.
Example:

)0 1

MCU

(3)

II HMCS400

SERIES

10)

LABEL:
Indicates the name identifying.program entry point.

Use this label

to call the program.
Example:

(4)

FUNCTION:
Describes program function.
Example:

II

FUNCTION

Shifts 8-bit binary data stored in RAM a specified number of times to the

right.

(5)

ARGUMENTS:
Describes entry arguments which must be initialized before program
execution, and return arguments after execution.
(a)

Contents:
Describes arguments' contents, e.g., constant, starting
address, string length.

HITACHI

7

(b)

Storage Location:
Indicates registers and RAMs in which arguments must be stored.
RAM locations are denoted by "(RAM)".
Note: Absolute storage locations in RAM address space are
designated by MD ($WXY, $WXY) using W, X and

Y addresses.

For example, MD ($033, $032) refers to the marked area
in the memory array shown below.

W

Y Address

X

Y

W

X

Y

G0!2J , 000
0

3

3

0

3

2

A

9

8

\

\

W, X

Address

-~

F

E

D

C

B

7

6

5

4~

3

2

I

0

~

0 2

~~

3
0 4

W, X, Y correspond to registers.
W, X, Y which are used to store memory addresses.

(c)

No. of Digits:
Indicates arguments' digit length.
Example:

I

ARGUMENTS

JI

Contents

Entry

Unsigned
a-bit binary MD ($033,
number to be
$032)
shifted to
the right
No. of shifts
B

Returns Shift result

8

HITACHI

1 digit 4 bits
No. of
Storage
Location Digits

MD($033,
$032)

2

1

2

(6)

CHANGES IN CPU REGISTERS AND FLAGS:
Describes changes in CPU registers and flag changes in condition
code register after executing a program.
The following symbols are used .

•

Not affected

Original contents are preserved.

x

Undefined

Original contents are destroyed.

Result

Contains results of program execution.

CHANGES IN CPU
REGISTERS AND FLAGS

.

Example:

: Not affected
x : Undefined

In this example, after executing

; .: Result

a program, contents of Accumulator,
A
x

B
x

X

y

x

x

SPX

Spy

(7)

CA
x

Y register, carry and status will
be destroyed.

•

•
W
•

I

B register, X register,
Thus, contents

which will be destroyed should be
saved before executing a program.

I

ST
x

I

SPECIFICATIONS:
Describes program operation specifications.
(a)

ROM (Words) : Indicates amount of ROM used by the program.
1 word consists of 10 bits.

(b)

RAM (Digits): Indicates amount of RAM used by the program.
1 digit consists of 4 bits.
(This value does not include memory needed for
the stack.)

(c)

Stack(Digits):Indicates amount of RAM used by the stack in
the program.

This memory must be reserved

when the program is executed.
(d)

No. of cycles:Indicates the maximum number of machine cycles.
Calculate the execution time required for
program execution as follows:

HITACHI

9

Execution time (sec) = Number of cycles x cycle time
Cycle time (sec) = 8/External oscillator frequency(Hz)
Note: BRS instruction is regarded as I cycle.
(e)

Reentrant

Indicates whether a program has a structure
which can be called from two or more routines
at the same time.

(f)

Relocatable

Indicates whether a program can be located in
any memory Space.

(g)

Interrupt OK?

Indicates whether MCU can continue a program
normally after serving an interrupt routine.
If cannot ("No"), inhibit interrupt before

the program is called.
Example:

l

SPECIFICATIONS

1 word=lO bits
ROM (Words)
11
RAM

Digits)
2

Stack (Digits)
0

No. of cycles
46

Reentrant
No
Relocatable
No
Interrupt OK?
Yes

(8)

SPECIFICATIONS NOTES:
Explanatory notes for items listed in (7) SPECIFICATIONS.
Example:

I

SPECIFICATIONS NOTES 11
"No. of cycles" in "SPECIFICATIONS" indicates the number of cycles required
to shift 8 bits of binary data 3 bits to the right.

10 HITACHI

1.3

DESCRIPTION Section

(1---------1:

The DESCRIPTION Section is shown in Fig. 1.3.

in Fig. 1.3).

t.. ________ ...

blocked area

Each numbered item in the figure is explained below.
lr;;J[HHcs4oo SERIEstr;BEL1~
1
'~=~=~~~~~~~~-~~-~~~·~~~~1

:I

FUNCTION

1

DESCRIPTION
(3)

II

I

RAM AHoeat ion

:

I

I

I
ARGUMENTS

CHANGES IN CPU

1 digit .. 4 biu
Contents

I~_-,

Storage

~~. 1of

8
____+-L!:!O'~,"!:.""",,-,p"'''''''1

REGISTERS AND FLAGS

I
I

SPECIFICATIONS

I
I

11=.=,
:",,=,=,7.,,;=,,=,;=.,;=91========1
": Undefined

I

1 word-tO bits

: Result

Entry

ROM

Words

RAM

1)1 its

Stack
spy

SPX

01 itl

No. of c cles
(4)

~

'--

I

r

,

51

I

Inteuu t OK?

I

I·

II

DESCRIPTION

I

(1)

I

Function Detaila

(5)

(2)

Sample Application

R locatable

Basic Operation

User Notes
I

I

II
II
II

II
II
,~~~~~~=-~~~~~~==~~~,
SPECIFICATIONS NOTES

H

Fig. 1.3
(1)

DESCRIPTION Section

Function Details:
Gives internal representation of arguments and results before and
after program execution, respectively, and describes basic
operation.

HITACHI 11

(2)

User Notes:
Gives precautions and limitations when executing the program.

*

Be sure to read these items when using the programs
without modification.

Example:
DESCRIPTION
(1) Function Details
(a) Argument details
MD($033,$032):
B

Holds 8-bit binary number to be shifted to the right.
After SHR execution, contains shift result.

Holds number of shifts.
Contents of B = Number of actual shifts - 1
(See (2) User Notes)

(b) Example of SHR execution is shown in Fig.
are as shown in part 

.~

: ............. u

(d) ......

00(:1 ..

00015

(e)

0001.;

00017
00018
(lQn:'l

n"!:

0100

213

OEC

01(1\
0102

0"0
OAO
0(>0

0103
DlO:.
0105

00013
00024
L)OO2'5

07\

0106
0107
0108
010"
011)1'0

~03

gg~:3~

i~~r;

0003('

(M'

)(SFT

YSFI
~AS~l

~

000:'2

0(1(';'0
I)OO:;>?

, "'0('033.$032> (B-en BINARY OATA1"

(c)~

00017
00013

OO(J20

132

(b)----2 .........................................................:

ggg:~

000\'1

LLEN

(a)~····;:;;;·:::;;·;:;:·:;:::·····················:
~O($033.1032> :;~i~~ ~~:~~A~ATlU

...............uu .................. u

I!!

I!

"

••••• u

:

•••• :

8-BIT BINARY Oi'l1A AOOR\~)
B-BIT BINARY DATA ADOR(,O

B-BIT BINARY OATA LSD AODIHY1-l
ENTRY POINT

Y$FT

'(SFT

SITA
"lORE ~H!Fl (lIn .. AND DECREMENT ADOI'<')"

BA<,FT
<'HR,"
DECREMENT SHIFT COUNTER
lOOP IJNTIl. ';HIFT ([)I'NTER •

'0

(f)

rI ------- -- --- - ----- - ---- --.-------- ---,I
When storing arguments in other RAM locations, change the EQU
I

operands for the following labels.

I

II

XSFT:

Defines X address of 8-bit binary number to be shifted
to the right.

II

I

YSFT:

Defines MSD Y address of 8-bit binary number to be shifted
to the right.

:
I

I
I

BASFT: Defines LSD Y address less 1 of 8-bit binary number to be
shifted to the right.
(YSFT-$2; if this is negative.

I
I

1L _______________________________
value should be defined as $F.)
JI

Fig. 1.5

PROGRAM LISTING Section

(a)

NAME: Name of a program.

(b)

ENTRY: Shows storage location and contents of entry arguments.

) means entry point label.

(c)

RETURNS: Shows storage location and contents of return arguments.

(d)

EQU: Defines RAM and its address by label.

(e)

SHR: Shows entry point label.

(f)

Explains how to modify this application example.

HITACHI 17

2.

Program Execution
The programs in APPLICATION NOTES have been considering efficiency and
portability.

The following shows how to execute these programs and how

to modify them according to user requirements.
2.1

Calling Programs in APPLICATION NOTES from User Programs
The procedure for calling programs in APPLICATION NOTES from user
programs is shown in Fig. 2.1.

All programs in APPLICATION NOTES

written as subroutines and should be called as shown in Fig. 2.1-

An example of a user program in which a program in APPLICATION NOTES
is called as a subroutine is shown in Fig. 2.2.

Program in APPLICATION NOTES

User Program

CALL FILL

Call subroutine

~_S?_,
I
I

Save necessary
register(s)

I

*Note

I

L_ - - - - -

______ J

r - -- - -

-------, *Note

/
I

Restore necessary:

L~_J
*Note: User must save and restore register(s),
if necessary.
Refer to the comments in next page.

Fig. 2.1

18 HITACHI

Procedure for Calling Programs in APPLICATION NOTES

User Program
LWI

$0

LMAD

$02D

LAMD

$OAl

Example with W

O.

... ..

Save register .

. ....

Initialize arguments •

LBA
LAMD

$OA2

LYA
LAMD

$OA3

LXA
LAMD

$OA4

LMAD

$04D

LAMD

$OAS

LMAD

$04C

II CALL

FILL

LMAD

$02D

II

Call program.
Restore register.

Fig. 2.2

Sample Application

Some programs may destroy register(s) contents before returning to the
user program, since register(s) are used not only as argument(s) but as
work area for calculation.

Usually, register(s) used as work area is

saved and restored in subroutine.

The programs in APPLICATION NOTES,

however, do not save nor restore register content(s).
If register(s) contents need to be saved, users must save and restore
register(s) contents as shown in Figs. 2.1 and 2.2.
Refer to the "SPECIFICATIONS" section for each program to determine
which registers should be saved as well as for details on subroutine
arguments and results.
Also, note that the amount of RAM used for the stack by each program
t

indicated in "SPECIFICATIONS" is in addition to that used when calling
the program (4 digits).

The entire stack area is 64 digits allowing

for a maximum nesting level of 16.

Thus, to prevent program malfunc-

tioning, both of the above must be considered when calling (and writing)
program subroutines.

HITACHI 19

2.2

Modifying Programs in APPLICATION NOTES According to User Requirements
The programs in APPLICATION NOTES may be modified depending on user
requirements.

~~~~--~~L--+--~--r--+--4---~-+--;---~-+--~--~-+--4SHR

RAM allocation
in APPLICATION NOTES

New RAM allocation
Fig. 2.3

RAM Allocation

For example, to modify RAM allocation for the SHR program as shown in
Fig. 2.3, the EQU instruction for the labels shown in Fig. 2.4 must be
changed as shown in Fig. 2.5, and the program them reassembled.
RAM allocations that can be modified are described after each program
listing, as shown in Fig. 2.4.
ST-NO

OBJECT

ADRS

SOURCE STATEMENTS

00001
00002
00003
0000 ..
00005
00006
00007
00008

010

0000

LLEN
1'2
...... ",,,,,,,,,,*,,,*,,,****,,,*,,,***,,,***********"'*"'**"'>10"'******"'*******," .. "'**11<
NAME

SHIFT 8-BIT DATA (SHR ~

'" **** *'" *****"'**** ***"' .. "' . . *** '" '" ** ... "''''*,

00009

00010
00011
00012

RETURNS

-Bf3 ---

'" "'*****'" *"''''''''''''''''''''''''''''*''''''''''''''''''"''''

r-isFi -- -EQU- -

00013

00014
00015
00016

I YSFT

__

l..e~S~T

00017
00018
00019

00020
00021

00021
00023
00024

00025
00026
00027
0002B

223
213
DEC

0100
0101
0102

090

0103

DAD
ODD
071
301

0104
0105
0106
0107
OlOB
0109

OlD

OIDA

303

DO'

00029
00030

'HR
SHRI
5HR2

EOU

>I<

S

OJ< "' ... " ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ... '''

ORO

$0100
XSFT
YSFT

REC

BRS

DB
BRS

RTN

II<

--s-aiT.iNARYDATAAOOR"'-- ----,
B-BIT BINARY OATA ADDR(Y)

:

Y£:T8..lS£ .8Q.O~'.!!...-.! _-.J

ENTRY POINT
LOAD ADDR(X)
LOAD AOOReY)
LOAD BINARY [lATA
ROTATE BINARY DATA
STORE SHIFT DATA AND DECREMENT ADDRIYl

LAM
ROTR
LMADY
YNEI

*

**"'''''''''''''''''''''' ****** '"

~Q~ _ _ _$1 _ _ _ _ _ _8~!.T ~!..N!:R!

EOU
LXI
LYI

.
.

"'II< ill'" ***""''''.''''** '" **** .. ****

110($033.$032) (a-BIT BINARY OATA)
(SHIFT COUNTER)
B
110($033. $032> (a-BIT BINARY DATA)

ENTRY

BASFT
SHR2

SHRI

DECREMENT SHIFT COUNTER
LOOP UNT IL SHIFT COUNTER" $0

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
XSFT:

Defines X address of 8-bit binary number to be shifted
to the right.

YSFT:

Defines MSD Y address of 8-bit binary number to be shifted
to the right.

BASFT: Defines LSD Y address less 1 of 8-bit binary number to be
shifted to the right. (YSFT-$2; if this is negative,
value should be defined as $F.)

Fig. 2.4

20 HITAOHI

Program Listing with Original RAM Allocations

changed
00013

0001 ..

XSFT
YSFT
BASFT

00015
00016

EOU
EOU
EOU

B-BIT BINARY DATA ADOR(X)

a-BIT BINARY DATA AODR(Y)
B-BIT BINARY DATA LSD AODRn')-l

00017

Fig. 2.5

Program Listing with New RAM Allocations

Note that in the program above, W register contents are not specified,
but have been assigned as W = 0 elsewhere (W, X, and Y register are
all needed for complete specification of a memory location). W register
has four possible selections, from 1 to 3.

If necessary, change

W register contents using the LWI instruction.

HITACHI 21

PROGRAM APPLICATION EXAMPLES

Page

Item

Program

Label

1

FILL WITH A CONSTANT VALUE

FILL

25

2

MOVE DATA BLOCK

MOVE

31

3

MOVE STRING

MOVES

38

4

BRANCH FROM TABLE

CCASE

46

TPR

54

NIBBLE

59

5
6

CONVERT ASCII LOWERCASE INTO
UPPERCASE
CONVERT ASCII INTO
I-DIGIT HEXADECIMAL

7

CONVERT 8-BIT BINARY DATA
INTO ASCII

COBYTE

64

8

COUNT

LOGICAL "1" BITS

HCNT

71

9

SHIFT

8-BIT DATA

SHR

77

10

4-DIGIT BCD COUNTER

DECNT

83

11

COMPARE

CMP

89

12

ADD

ADD

95

13

SUBTRACT

8-BIT BINARY DATA

SUB

102

14

MULTIPLY

16-BIT BINARY DATA

MUL

109

15

DIVIDE

DIV

118

16

ADD

ADDD

126

17

SUBTRACT

SUBD

133

18

16-BIT SQUARE ROOT

SQRT

140

19

CONVERT 2-BYTE HEXADECIMAL
INTO 5-DIGIT BCD

HEX

151

20

CONVERT 5-DIGIT BCD
INTO 2-BYTE HEXADECIMAL

BCD

159

21

SORT

SORT

169

8-BIT BINARY DATA

8-BIT BINARY DATA

16-BIT BINARY DATA

8-DIGITBCD
8-DIGIT BCD

II II

1. FILL WITH A CONSTANT VALUE

I

FUNCTION

MCU HMCS400 SERIES

II

Fills a specified number of bytes in

I

ARGUMENTS

II

Contents
Constant
Entry

1 digit= 4 bits
No. of
Storage
Location Digits
HCNST,
LCNST
2
(RAM)

No. of bytes
Starting
address

B

--

I

CHANGES IN CPU
REGISTERS AND FLAGS

DESCRIPTION

1_

SPECIFICATIONS

•x ::

Not affected
Undefined
t : Result
A

2

B

x

x

X

Y

x

x

SPX

SPY

•W
•

-

I

I

LABEL

with a constant value.

1

X, Y

--

Returns

R&~

II

CA
x

•

I

ST
x

I

1 word=lO bits
ROM (Words)
14
RAM (Digits)
2
Stack (Digits)
0
No. of cycles
155
Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

(1 ) Function Details
(a) Argument details
HCNST, LCNST(RAM):

Holds I-byte constant to fill an area in RAM.

B

:

Holds number of bytes of RAM to be filled with
constant (Contents of B = actual number of bytes
- 1. See (2) User Notes).

X, y

:

Holds starting address in RAM.

(b) Example of FILL execution is shown Fig. 1- If entry arguments are
as shown in part -M
Y

+ 1 ->- Y

--------{

Store upper digit of constant in
RAM pointed to by X and Y registers.

---------[

Increment Y address for next
storage location.

------{

Store lower digit of constant in
RAM pointed to by X and Y registers.

-----------[

Increment Y address for next
storage location.

---------

-[

--------{
----B'f$F

----[

---------{

Test if Y address is $0.
Increment X address.
Decrement byte counter indicating
number of bytes left to be filled
with constant.
Test if filling is completed.

HITACHI 29

1. FILL WITH A CONSTANT VALUE

IIMCUIIHMCS400 SERIES

I I LABEL II

II

PROGRAM LISTING

ST-NO

OBJECT

ADRS

00001
OUOO:

000 000

0000

ooom

SOURCE S.TATEMENTS

LLEN

NnME

00004
00005
00006
00007

132

.

**"' . . ,.,"'*****"'*'***********************"'****>1<:-1<************>t
FILL WITH A CONSTANT VALUE (FILL)

* "'"+' 1+' '" '" "'* >I< >I< *. . "'''' '" >I< >I< >I< >I< ** >I< >I< '" * '" '" >I< *' ** '+< '" '" ** '" '" *** >I< >I< >I< >I< *'" '" >I< >I< '" *"'''' >I< >I<

ood08

ENTRY

OOGOQ

00010
00011
GOOL?
0001 ?
0001'.

RETIjRNS

HCNST

-M
X +-+ SPX

_______[

Save Accumulator and B register
indicating source address.

-------[

Load source address data indicated
by MATB, B register and Accumulator
into B register and Accumulator .
Load upper digit or source data
into destination.
Load destination X address
for lower digit.

..

_----[

-----{

A->-M

lower digit
-----[ Store
in destination.

+

1 ->- Y

-----[

X +-+ SPX

-----[

Y

-----[

of source data

Increment destination Y address.
Load destination X address for
upper digit.

$0.

Test if Y register

---1 In"r~.n' '."i="=
---{

X addrm,

Restore Accumulator and B register
indicating source address.

Increment Accumulator
------{ source
address.
Test if

B register

indicating

indicating source

-----[ address needs incrementing.

-----(
-----[

Increment B register indicating
source address.
Decrement counter indicating byte
length of data block.

------[ Test if move is completed.

36HITAOHI

2.

I MCU II HMCS400 SERIES II LABEL I

MOVE DATA BLOCK
PROGRAM LISTING

II

ST-NO

OBJECT

ADR<;

S-OLIRCE STATEM£?NTS

00001

000 000

0000

LLFN
l32
"'."'''''1<'''.4''''**.+'",,,,****,+ ...... **** ... "' ... "'*11 .. '" "''''.,.,.. . . "'''' ...... ,.. ... ~,

00002
0(1003

N~~ME

00004
(IOOOS
00(106

00007
00008

: MOVE (lArA ALOCK

.

"'*'" *"''''. ***"' . . ** ...... "'*

(MDVE>

A.S

(~OURCE

0')000;1

X. Y

0.0010
OOOll
00012
00013

!:.py

(DESTINATION $TARTING ADDRESS>
(NO. OF BYTES)

ENTRY
RETURNS

0001'-'

00015
00016
00017
00018

EQU

LSOU

eQU

MT('~S

EQU

1i048
$04A
1F

ORG

$0100

M(1VE

STARTING ADDRESS)

NOTHING

HSrJU

OOOIQ

WORI( AREA FOR REGISTER(B)
WORK AREA FOR 14CCUMULATOR.A)
MSO (8-11BIT) OF DATA TABLE ADDRE:'S.

ENTRY POINT

EGllJ

000:'0
00021

194 04A

0100

LM"D

LSOU

0002:~

048

Oll023
00024
00025

194 048

0102
0103

LMAD

IISOU

SAVE' SOLIRCE ADOR(B)

0105
0107

L~MD

18F

P

LSOlJ
M1AB

LOAD SOURCE DATA

(IOO?6

Oct

0108

XM~X

00027
Q0028

051

0109

LMAIYX

313
068

OIOA
OIOB
OIOC
010['
OIOE
OIOF

BRS
LASPX
AI
XSPX

f)Oo~q

01)030
00031

noo::'2

lQI) 04A

282

001
OE8

0003':;

068

00034

282
001

00035

0110
Olll
0112
0113

on03('·
00037

QE8

00038
00039
00040
00041
00042
00043
00044

OC8
190 04A

0115

281
31B

0118
0119

31C

OllA

04C
002

190 048

ODF

oe:?

OIlB
OIIC
OllD
OllE

00047

300
010

OllF
0120

000,:-,8

SAVE SOURCE ADDR (A)

1..1:..)8

LOAD UPPER c:.OLJR[E DATA

LOAD LOWER SOURCE DATA AND INCREMENT ADDR(Y)
MOVEI

LXA
LASPX

BRf.1NCH IF AOORC() =1
INCREMENT ADDR< ~PX)

$0

INCREMENT ADDR' X'

(U

MOVE I

0116

O(104S
001)46

MOVE

MOVE2
MOVE3

XSPX
LXA
LAMD
LBA
LAMD

HSOU

LOAD SOURCE ADDR(A)

LSOU

LOAD SOURCE ADDR(B)
INCREMENT SOURCE AODR(A)
BRANCH IF A - T.O
BRANCH IF A - j ·$0
INCREMENT SOURCE ADDR(B)

AI

$1

6RS
BRS
IS

MOVE2
MOVE3

XSPY
D'·
XSPY

BRS
RTN

DECREMENT LENGTH COUNTER
MOVE

LOOP UNTIL LENGTH COI.lNTER

to

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
HSOU: Defines address where B register, indicating source
data address, is saved.
LSOU: Defines address where Accumulator; indicating source
data address, is saved.
MTAB: Defines MSD of the data table address referred to by the
pattern generation instruction (P).

HITACHI 37

I

3. MOVE STRING

I

IIMCUIIHMCS400 SERIESIILABELI

U •.I.'j;j".

II

FUNCTION

Moves string of data, stored in ROM, to a specified location in RAM using a
string terminator ($00) .

I

ARGUMENTS

II

Contents

Entry

Source starting address
(ROM)
Destination
starting
address (X)
Destination
starting
address (y)

I digit- 4 bits
No. of
Storage
Location Digits

I

CHANGES IN CPU
REGISTERS AND FLAGS

•x
t

SPECIFICATIONS

: Not affected
: Undefined
: Result

B,A

2

X

1

A
x

x

SPX

1

X

Y

x

x

Y

1

SPX

SPY

x

x

B

W
Returns

--

--

•

--

I
I

CA

•

I

ST
x

I

I word=IO bits
ROM (Words)
40
RAM (Digits)
2
Stack (Digits)
0
No. of cycles
478
Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

DESCRIPTION

(1) Function Details

(a) Argument details
B,A

:

Holds source (ROM) starting address as a 2-digit hexadecimal
number.

X

:

Holds destination (RAM) starting X address as a I-digit
hexadecimal number to indicate from where upper digit of
source data will be stored.

SPX

:

Holds destination (RAM) starting X address as a I-digit
hexadecimal number to indicate from where lower digit of
source data will be stored.
(Contents of SPX register = contents of X register + 1.
See (2) User Notes.)

y

:

Holds destination (RAM) starting y address as a I-digit
hexadecimal number.

I

SPECIFICATIONS NOTES

II

"No. of cycles" in "SPECIFICATIONS" indicates the number of cycles required
to move a string of data with the terminator in the 16th byte.

38 HITACHI

I II

13. MOVE STRING

I

MCU

HMCS400 SERIES

II

LABEL

I

MOVES

DESCRIPTION
(b) Example of MOVES execution is shown in Fig. 1. If entry arguments
are as shown in part CD of Fig. 1, data in source ROM ($OF12)
is moved to destination MD($05B'" $070), MD($06B'" $080) as shown
in part ~ of Fig. 1. When terminator ($00) is reached MCU
terminates moving of data block.

b7
B,A
($1, $2)

CD

Entry arguments

B

A bO

1

2

X

SPX

5

6

X,SPX
($5,$6)

b3
y

I

y

bO

QJ

($B)

ROM
Source (ROM)
starting
address -+ $OF12

1
1

Terminator

48
92

$OF:~ t-FU=liF_=_~tbR=;--1

Destination (RAM)
starting address

.MD ($05B)
MD ($06B)

Source
data
block

!

+

W,X\Y FED C B A 9
05

9 4 3

06

Destination
data
block

~ Result

07
08
RAM

Fig. 1

Example of MOVES Execution

HITACHI 39

II MCU II HMCS400

, 3. MOVE STRING

I

SERIES

II LABEL II

MOVES

DESCRIPTION
(2) User Notes
(a) ST flag is set after MOVES execution.
(b) When storing the destination starting address in SPX register,
contents of X register + 1 must be stored, otherwise data cannot
be moved successively to RAM. In Fig. 1, as contents of X register
is $5, $6 is stored in SPX register.
(c) Bit 8 of all words in the source data table must be set to
indicate loading of data into Accumulator and B register when
executing the pattern generation instruction (p).
(3) RAM Allocation

Fig. 2

Label

bO

~
MD ($04B)
b3

LSOUR

Description

RAM

b3

HSOUR

8

bO

MD ($04A)

40 HJTACHI

RAM Allocation

Work area for saving contents of B register
used to indicate source (ROM) address.
Work area for saving contents of Accumulator
used to indicate source (ROM) address.

I II

13. MOVE STRING

I

MCU

HMCS400 SERIES

II

LABEL

I

MOVES

DESCRIPTION
(4) Sample Application
Shown below is a sample application using MOVES with address space
allocated as follows.
MD($OA2,$OAI) :

Source starting address

MD($OAS~

Destination starting address

$OA3):

LWI

$0

LAMD

$OAS

..•.. Example with

w=o.

LXA
XSPX
LAMD

$OA4

Load destination starting address
into entry argument.

LXA
LAMD

$OA3

LYA
LAMD

$OA2 }

LBA
LAMD
1\ CALL

Load source starting address into
entry argument.

$OAI
MOVES II

..... Call MOVES.

HITACHI 41

13~

I

II MCU II HMCS400 .SERIES II LABEL II· MOVES.

MOVE STRING
DESCRIPTION
(5) Basic Operation

(a) Data stored at the address indicated by Accumulator and B register is
referred to Accumulator and B register, using the table look-up function
of the pattern generation instruction (P).
Program
LAI

$3

LBI

$1

P

$F

ROM

B Register Accumulator

m
ill

@J

}

ROM
Execution
~$OF12

[ill

After executing the pattern generation instruction
in the above program sequence, $CD is contained
in B register and Accumulator ($CD is stored
in lower 8 bits of word located at $OF13).
Since data table is allocated from $OFOO"'$OFFF,
subroutine MOVES uses $F as operand of the
pattern generation instruction (p).
Fig. 3

)
*Note:
If dotted area (bit 8) is
$1 as shown above, ROM
data is referred to
Accumulator and B
register after executing
the P instruction.

ROM Table and the P Instruction

(b) Accumulator and B register are used as a pointer to the source data.
(c) X and Y registers are used as a pointer to the destination location
in RAM.
(d) Data block, pointed to by Accumulator and B register, is moved
into Accumulator and B register using the pattern generation
instruction (P).
Data in Accumulator and B register is tested for terminator ($00).
If not, contents of Accumulator and B register is stored into
destination and destination address is then incremented.
(e) Operation loops to (d) until terminator ($00) appears.

42 HITACHI

II MCU II HMCS400

3. MOVE STRING

SERIES

II LABEL II

MOVES

FLOWCHART

Save Accumulator and B register
-------[ indicating source address.
Load source address data, indicated
.----- [ by MSTAB, B register and Accumulator,
into B register and Accumulator.
______ [save Accumulator before test for
terminator.

Test if source data is terminator
(Accumulator =$0, B register=$O).
If "Yes", terminate
MOVES.

X ....... SPX

Spy ->- A

Y

subroutine

____ {Store upper digit of source data
into destination.
_____ [Set destination X address
for lower digit.
------[ Restore Accumulator.

A->-M

_____[Store lower digit of source data
into destination.

+

-----[ Increment destination Y address.

1 ->- Y

X ....... SPX

_____ { Increment destination X address
for upper digit.
_____{Test i f destination Y address
is $0.

HITACHI 43

13 .. MOVE

I

II II

STRING

MCU

HMCS400 SERIES

II

LABEL

/I

MOVES

FLOWCHART

____ [

{

---- {

---of
---or

44 HITACHI

Restore Accumulat·or and B register
indicating source address.

Increment Accumulator
indicating source address.
Test if B register, indicating
source address, needs incrementing.
Increment B register indicating
source address.
Test if move is completed.

13. MOVE STRING

I

IIMCUIIHMCS400 SERIESIILABELII

~<>VES

II

PROGRAM LISTING
ST-NO

OB,JEer

ADRS

00(101

010

0000

00002
(lOOO3

SOURCE

STATH1ErJT:.
LLEN

'" t"'I'

"'*"'''' *"'''' ** '"

oono~

132
>I<*, 'I' 'I' i<

NAME

-1<."" ".t >I' >I<

*'" *"'* '" "''''''''''* "'''''''* '" "''''** '" *'"'''' "'** >1<"+'** . . . "'** '" **"'*

MOVE STRING (MOVES)

000013
(lOO(h
00007

"'''' +. >1<>1<

"'** '" 'I' ** ~ "' .. *+ t

00008

+- >1<" "'>to '" '" 'I' "',..

ENTRY

000(19
00010

( SOURCE STARTING ADORES'S )
It"'' ' *'" ** '" '" >II'" '" '" '" "'**"';~ "".., '" ** '" "'* '" '" "'''',..

A.S

x. '(

00011

0001 ':'!

'" +"

0001::.

00014

*"'*"'''' '" '" '" '" '" "'*** . . '" >1<'" '" '" ***'" '" >1<,.. "'******* **** ",,,,,,,>II,,,,,,,,,,,,,,,,,,,,,,,,,,, ** ******
'40'

EQU

1-048

OOOIS

HSOUR
LSOUR

EQU

00016

MSTAB

EQU

tQ4A
$F

ORG
EQU

'0100

MOVES

L~lAD

LSOUR

>I<

WORK AREA FOR REGISTER(B)
WORr< AREA FOR ACCUMULATOR
$0
INCREMENT ADOR(SPX)

'j;2

U-'r1'10
(H
8PS
MQVF';4

SAVE SOURCE AQOR(8)

LOPlD SOURCE DATA

'0
t10VESl
f'10VE S7

00(13(,

0(1)(.+0
O()041
000"2
OO(Vt!.
0('1044

HSOUR
LSOUR

1'1S rAB

OlO(~

0110
0111
0112
(1113

ENTRY POINT
SAVE SOURCE AOOR-

[

Load data table address into
Accumulator and B register.
Load data table contents,
specified by CCTAB, B register
and Accumulator, into B register
and Accumulator.

CWORK
Test for data table command or
terminator (Accumulator =$0,
B register=$O).
If terminator, set ST flag
and terminate CCASE.

Compare input command with
data table command.

HITACHI 51

4. BRANCH FROM TABLE

IIMCUIIHMCS400 SERIESIILABELII

CCASE

FLOWCHART

If input command and data table
command are the same, load service
routine starting address into
Accumulator and B register.

-----~

.- - --

If input command is different from
data table command, add "2" to LSD
of the data table address to compare
with the next data table command .

_---[

Test if LSD of data table address
generates a carry.

-----[

Increment the upper digit of data
table address.

.

52 HITACHI

[

Clear ST flag.

I II

4. BRANCH FROM TABLE
PROGRAM LISTING

MCU

ST-NO

OBJECT

AORS

010

0000

0002~

OAF
OC8

0100
0101

002

0102
0103

:1< ...

LCMr-1D
CWORK
CCTAB
CCASE

180 04A

048
319
104 04C

180 04A
10~ 04B

00035
00036
00037
00038
00039
00040
00041

31C
058
OC8

00042

010

00045
00046

00047

OSC
OAF
1BF

780
280
318
30A

osc

05C

000·,8

002

00049
00050

300
OSC
300

00051
000S2

.

132

*... II< '" "' ... ** '" * '" ****'" ** **lIC"' ... '" "' ...... ** **** *'" *"'''' oil"'' ' '" III '" ~** ... '" '" ** III. **

(lIn

0104
0105
0106
0108
0109
OIDA
OJOC
0100

0120
0121
0122

*

(DATA TABLE STARTING AOOR)

'"

A.B
ST FLAG

(SERVICE ROUTINE STARTING ADDR)'
(ST-O:FOUND. ST-I :FALSE)

EOU
EOU
EOU
EaLl

S04C
S04B
S04A
SF

ORG
EOU
LAY
LBA

SOlDO

CCASI

LAY
P
ALEI
XMAD
LAB
BRS
ANEMD
BRS

XMAD
ANEMD
8RS
LASPY

CCAS2
eCAS3

LBA
IY
LAY
P
AI
RTN
ALEI
BRS
BRS

CCAS4

LOAD Y INTO REGISTER1< ... '" *** ****** **** ** ...... **** '" '" ** '" '" **"' ...... *"' .... '" '" ** '" ** '"

HCMMD

31C

00043
00044

LLEN

RETURNS

OAF
1BF

CCASE

'" '" *** '" ~ ** '" '" '" "' ... '" .t.** ... '" "''''''' *"''''''' "'' '*11< * It< ** *** *** "'11<"'' ' '" * ** I<* >Ie '" '" '" '"

00032

00034

LABEL

NAME: 8RANCH FROM TABLE (CCASE)

00031
00033

II

1/

00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00070
00021
00023
00024
00025
00026
00027
00028
00029
00030

HMCS400 SERIES

CCASE

BRANCH IF li:frlI~TER('n
INCRf-MENT REGISTERlY)
BR?-It'JCH TO rc ASE

=1

£(I

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
HCMMD:

Defines upper digit address of 8-bit command.

LCMMD:

Defines lower digit address of 8-bit command.

CWORK:

Defines address where Accumulator, used as work area, is saved.

CCTAB:

Defines MSD of the data table referred to by the
pattern generation instruction (P).

HITACHI 53

JIMCU I HMCS400

5. CONVERT ASCII LOWERCASE INTO UPPERCASE

I

SERIES

II

LABEL

I_

II

FUNCTION

Converts ASCII lowercase data using 7-bit ASCII arguments into uppercase
data, loading result into Accumulator and B register.

I

II

ARGUMENTS
Contents

1 digit - 4 bits
No. of
Storage
Location Digits

CHANGES IN CPU
J
REGISTERS AND FLAGS

•x ::
t

Lowercase
(ASCII)

Entry

A,B

Not affected
Undefined
Result

:

A
t
X

2

Returns

Uppercase
(ASCII)

A,B

+

Y

•
•
W
•

2

I
I

DESCRIPTION

CA
x

1 word=lO bits
ROM (Words)
14
RAM (Digits)
0
Stack (Digits)
0
No. of cycles

B
x

SPX

SPY

•

I

ST
x

SPECIFICATIONS

13

I

Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

(1) Function Details

(a) Argument details
. A,B :

Holds ASCII lowercase.
After TPR execution, contains the corresponding uppercase
data.

(b) Example of TPR execution is shown in Fig. 1. If entry argument
lowercase 'a' ($61) is held in Accumulator and B register as
shown in part. I< >Ie

RETURNS

077
3{)8

28A
306
308

0100
0101
0102
0103

0104
0105
0106
0107
0108
0109
OIOA
010B

olOe

0100

A
B
A
B

(UPPER
(LOWER
(UPPER
(LOWER

BITS
BITS
SIrs
8I TS

OF
OF
OF
OF

* >I< ** >I< >I< >I< >I< *** >I< *** >I< >I< >I< >I< *' >I< >I< >I< **** >I< >I< >I< '1<"'" >I< >I< >I< >I< >I<

TPR
008
048
076
309
280
308
OAF
28E
010

>10".1, ...

CONVERT ASCII LOWERCASE INTO UPPERCASE I< **** >I< >I< >I< >I< >I< *** >I< >I< *** *** >I< >I< >I< >I< >I< * >I< >I< *'" >I< '" >I< >I< >I< >I< >I< >I< >I< >I< '" >I< >I< >I< >I< >I< >I< >I< >I< >I< >I< >I< >1<'" >I< >I< '" >I< *
ENTRY

>I<

132

********* *************** >1<>1<>1<>1<** +-If< ***,.. .... *******"'** '" ** '" ***** ** >I<

TPRI
TPR2
TPR3

ORG
EQU
L YA
LA8
YNEI
BRS
ALEI
BRS
LAY
Al
RTN
YNEI
BRS
ALEI
8RS
8RS

>I(

ASCII
ASCII
ASCII
ASCII
>I< >I<

**

>I< >I<

LOWERCASE)
LOWERCASE)
UPPERCASE)

UPPERCASE)

* ** >I< >Ie >I< >I< >I< >I< >I< >I< >I< '" ** **

>I< >I<

$0100

'6

ENTRY POINT
LOAD UPPER 4 BITS OF ~~SCII LOWERCASE
LOAD LOWER 4 BITS OF ASCll LOWERCASE
UPPER 4 BITS OF A:'CII LOWERCASE=t6 ?

$E

LOWER 4 BITS OF ASCII LOWERCASE :::<$0 ?
BRANCH IF LOWER 4 BITS OF ASCII LOWERCA5:.E =<$0
LOAD A FROM Y
CONVERT LOWERC(4$E INTO UPPERCASE

.7
TPR2
$A
TPRI
TPR2

UPPER ASCII "'$7 ?
BRANCH IF UPPER 4 BITS OF ASCII LOWERCASE"'':$7
LOWER 4 B1 TS OF ASC II LOWERCASE=<$A ?
BRANCH IF A =( $A
BRANCH IF A ) $A

TPR3
.0
TPR2

BRANCH IF UPPER 4 BITS OF ASCII LOWERCASE =/$6

16. CONVERT ASCII INTO

l~DIGIT

HEXADECIMAL

II II

MCU HMCS400 SERIES

II

LABEL

I=--

II

FUNCTION

Converts 7~bit ASCII, '0' to '9' or 'A' to 'F' in Y register and Accumulator,
into a l~digit hexadecimal number, loading result into Accumulator.

Irr=================~~~_1~d~i~g~i~t~=;4~b~i~t~s
ARGUMENTS
II
Storage
Location

Contents

No. of
Digits

CHANGES IN CPU
REGISTERS AND FLAGS

SPECIFICATIONS

• : Not affected
x : Undefined
~ : Result

1 word=lO bits
ROM (Words)
14

Entry

ASCII

Y,A

Hexaaec imal
number

A

2

1

Returnsr-----------~--------_+------__i

Conversion or
no conversion

ST

(1 bit)

A
:t
X

B

RAM (Digits)

Y

Stack (Digits)

SPX

Spy

•

•
•
W
•

CA
x

o

x

o
No. of cycles

•

I

ST

t

13

I

Reentrant
No
Re10catable
No
Interrupt OK?
Yes

II

DESCRIPTION

(1) Function Details
(a) Argument de,tails
Y,A:

Holds ASCII. After NIBBLE execution, contains a
hexadecimal number in Accumulator.

ST

Indicates status after NIBBLE execution.

:

l~digit

ST=O:

Indicates ASCII range of '0' to '9' or 'A' to 'F'.

ST=l:

Indicates ASCII other than '0' to '9' or 'A' to 'F'.

(b) Example of NIBBLE execution is shown in Fig. 1. If entry argument
is as shown in part Q) of Fig. 1, data $F, converted from ASCII
into a l~digit hexadecimal number, is contained in Accumulator
as shown in part (i) of Fig. 1.

I

SPECIFICATIONS NOTES

II

"No. in cycles" in "SPECIFICATIONS" indicates the number of cycles required
to convert $4 and $6 held in Y register and Accumulator, respectively.

HITACHI 59

16.

I

CONVERT ASCII INTO I-DIGIT HEXADECIMAL

II MCU II HMCS400 SERIES II LABEL 1\

NIBBLE

DESCRIPTION

Y

A

4

6

b7

bO

Entry argument

j
A
{ l-digit
Return arguments (hexadecimaJ
number
)
Fig. 1

ST

A
b3

bO

00]

Example of NIBBLE Execution

(2) User Notes
Data other than ASCII '0' to '9' or 'A' to 'F' held in Accumulator
and Y register is destroyed after NIBBLE execution.
(3) RAM Allocation

RAM is not used during NIBBLE execution.
(4) Sample Application
Shown below is a sample application using NIBBLE with address space
allocated as follows.
MD($OAI,$OAO)
MD($02B)
LWI

2-digit ASCII
I-digit hexadecimal number

$0

..... Example with W=O.

LYA

$OAI }

..... Load ASCII into entry argument.

LAMD

$OAO

LAMD

C_A_L_L__N_IB_B_L_E..!III . . . .. Call NIBBLE.

u...11

SKIP

60 HITACHI

BRS

SKIP

If ASCII is other than '0' to '9' or 'A' to
'F', branch to service routine.

LMAD

$02B

Store a I-digit hexade.cimal number, contained
in return argument, in RAM.

Service routine for
ASCII other than
'0' to '9' or 'A' to 'F'

I 6.
I

CONVERT ASCII INTO l-DIGIT HEXADECIMAL

IIMCU"HMCS400 SERIES

IILABEL II

NIBBLE

DESCRIPTION
(5) Basic Operation
(a) Data in Y register and Accumulator is tested if within range of '0'
to '9' (Ii
Ilarea in Table 1), using comparison instruction (ALE!).
(b) Next, data in Y register and Accumulator is tested if within range
of 'A' to 'F' (c:::=:Jarea in Table 1).
(c) If data is other than above, ST flag is set and operation terminated.
(d) After testing (a) and (b), ASCII is converted into a I-digit
hexadecimal number.
(i) If data is within range of '0' to '9', data in Accumulator is
contained as return argument.
(ii) If data is within range of 'A' to 'F', $9 is added to data in
Accumulator to convert ASCII into a l-digit hexadecimal number.
Table 1

.~

a

ASCII Table

1

2

3

4

5

6

7

111

LSD

000

001

010

all

100

101

llO

a 0000

NUL

DLE

SP

r'1f

@

P

,

1 0001

SOH

DC1

!

1

A

Q

a

q

2 0010

STX

DC2

2

B

R

b

r

3

C

S

c

s

4

D

T

d

t

3 OOll

ETX

DC3

"
#

4 0100

EaT

DC4

$

-

P

5 0101

ENG

NAK

%

5

E

U

e

u

6 0110

ACK

SYN

&

6

F

V

f

v

7 0111

BEL

ETB

7

G

W

g

w

8 1000

BS

CAN

(

8

H

X

h

x

9 1001

HT

EM

)

Y

i

y

LF

SUB

*

:J:

I

A 1010

:

J

Z

j

z

k

{

,

-

B lOll

VT

ESC

+

;

K

[

C llOO

FF

FS

,

<

L

\

1

I

D llOl

CR

GS

-

1

m

}

E 1110

SO

RS

n

'\,

F llll

SI

VS

0

DEL

/

=

M

>

N

t

?

0

+

HITACHI 61

I 6.
I

CONVERT ASCII INTO I-DIGIT HEXADECIMAL

IIMCUIIHMCS400 SERIES

II LABEL I

FLOWCHART

Test if ASCII in entry
argument is within range
of '0' to '9'.

Test if ASCII in entry
argument is within range
of 'A' to 'F'.

Convert ASCII into a I-digit
----- [ hexadecimal number.

-----[Clear ST flag.

62 HITACHI

NIBBLE

6. CONVERT ASCII INTO I-DIGIT HEXADECIMAL
PROGRAM LISTING

IIMCUIIHMCS400 SERIESIILABELI\

NIBBLE

~

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
OOOOB
OOOOQ
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030

100

0000

SOURCE STATEMENTS

·
··

LLEN

132

********************************"'*******"''''************"'**"'*****
NAME :

CONVERT ASCII INTO I-DIGIT HEXADECIMAL (NIBBLE»

···

***** '" ** "'* * ** ** * * ** '" III ** * '" '" "' ... '" * ** "' ... "'** II< III ***** lie ** ** **'" ** *' * "'''' ** '" **
ENTRY

Y
A
A
ST

RETURNS

(UPPER ASC II )
(LOWER ASC II )
(HEXAOECIMAL OATA)
Fl.AG (5T=I:CONVERTEO.ST=0:FALSE)

*** *** *"'* **** ... "',.. 'Ie ** **** ***:+: * '" ********* ** **** >Ie '" * . . . '" ~*:t. ... * II< lie "''''* II< ** >I<
NIBBLE
073
304
289
30C
074
300
286
309
300
2BO
300
289
280
010

0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
OIOA
o lOB
oloe
0100

NIBI

ORG
EOU
YNEI
BRS
ALEI
BRS
YNEI
BRS

NIB2
NIB3
NIB4

/)LEI
BRS
BRS
ALEI
BRS
AI
Al
RTN

.

$0100
$3

NIBI
$9
NIB3
$4
NIB4

ENTRY POINT
UPPER ASCII = $3 ?
BRANCH IF UPPER ASCII =/ $3
LOWER ASCII =( $9 7
BRANCH IF LOWER ASCII =< $9
lIPPER ASCI r = $4 ?
BRANCH IF UPPER ASCII =/ $4

$6

l.OWER ASCII

NIB2
NIB4
SO

BRANCH IF LOWER ASCII =< f,6
BHnNCH IF l nWER ASC JJ ) ,·6
LOWER ?\SCII =< $0 ?

=(

$6 ?

NIB4

BRANCH IF HSC II :.:: $0

$9

CONVERT ASCII INTO HEXADECIMAL NUMBER
CLEAR S TfHU~ FLAIl

$0

HITACHI 63

17. CONVERT 8-BIT BINARY DATA INTO ASCII

I

FUNCTION

IIMCUIIHMCS400 SERIESIILABELI

II

-

Converts a-bit binary data, held in SPY register and Accumulator, into
2-figure ASCII and stores result in RAM; uses 7-bit ASCII arguments.

I

ARGUMENTS

II

Contents
Upper digit
of 8-bit binary number
Entry

1 digit- 4 bits
No. of
Storage
Location Digits
Spy

CHANGES IN CPU
REGISTERS AND FLAGS

•x ::
~

1

A

1

Upper digit
of ASCII

MD($03D,
$03C)

2

Lower digit
of ASCII

MD($03B,
$03A)

2

DESCRIPTION

B

x

x

X

Y

x

x

SPX

Spy

•
•

x

W

Returns

I

Not affected
Undefined
: Result
A

Lower digit
of 8-bit binary number

SPECIFICATIONS

I

CA
x

I

ST
x

I

1 word=lO bits
ROM (Words)
19
RAM (Digits)
4
Stack (Digits)
4
No. of cycles
27
Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

(1) Function Details

(a) Argument details
SPY,A

:

MD($03D'\, $03A) :

Holds 8-bit binary number to be converted into
ASCII.
A: Lower digit)
(SPY: Upper digit,
Contains 2-figure ASCII.

(b) Example of COBYTE execution is shown in Fig. l. If entry arguments
are as shown in part 

N

t

n

'V

F

1111

SI

VS

?

0

+-

0

DEL

/

HITACHI 67

17.

I

CONVERT a-BIT BINARY DATA INTO ASCII

IIMCUIIHMCS400 SERIESIILABELII C()BYTE

FLOWCHART

_____ [

Load RAM address, where ASCII is
stored, into X register.

______ [ Load LSD address, where ASCII is
stored, into Y register.
Convert lower 4 bits of 8-bit
------[ binary data into ASCII.
A-+M
Y+1 -+ Y

Store lower digit of converted
.------[ ASCII in RAM.
______ [ Increment Y address where
ASCII is stored.

Store upper digit of converted
.------[ ASCII in RAM.
A-+M
Y

+

1

-+ Y

______ [ Increment Y address where
ASCII is stored.
______[Load upper 4 bits of 8-bit
binary number into Accumulator.
_____[convert upper 4 bits of 8-bit
binary number into ASCII.

A-+M
Y+1 .... Y

_____[Store lower digit of converted
ASCII in RAM •
._____[Increment Y.address where
ASCII is stored.
Store upper digit of converted
---- --[ ASCII in RAM.

68 HITACHI

17.

I

CONVERT 8-BIT BINARY DATA INTO ASCII

IIMCU"HMCS400 SERIES

II LABEL I

C()BYTE

FLOWCHART

______ [

$9

--.-- {

______

[

Load $3 as the upper digit of ASCII
'0' to '9'.
Test if data is less than $9 or
greater than $A. When data is
less than $9, contents of
B register and Accumulator
can be used as ASCII.
When data is greater than $A,
subtract $9 from the data and
load $4 into B register to
convert data into ASCII.

HITACHI 69

17.

CONVERT 8-BIT BINARY DATA INTO ASCII

I

PROGRAM LISTING
ST-NO

OBJECT

ADRS

010

0000

00031
00032
00033
00034
00035
00036
00037

LLEN

132

>1<"'' ' ' * "''''* *>1<**"'******"'** *"''''''''''''''''
NAME

",,,,>Ie

* '" "''''''''''''''''''' '1< '"

RETURNS

'" '" '" >I< '" '" '" '" '" '" '" "' ... '" '"

yeos

COSYlE
223
21A
160 100
050
04B
050
058
160 100
050
OCO
010

0100
0101
0102
0104
0105
0106
0107
0108
olOA
010B
010C

203

0100
OJOE
OIOF
OIlO
0111
0112

204
010

EQU
EOU

ORG
EOU
LXI
L YI
CALL
LMAIY
LAS
LMAIY

CONIB

CONISI

LSI
ALEI
BRS
AI
LSI
RTN

*'1< -..* .. +;1<"* *****

>I< '"

** '" '" '" '" "' ...... '" * '" >1\

"'*

$3
SA

>I< >I< '"

* '" II< >I< '" '"

"
B-BIT BINARY DATA»
B-BIT BINARY D(UA);
ASCII)
ASCII)

*'" >1<"'*"'* *'" *,.. '" "'' ' '" '" '" >I< '" '" '" >I< '" * '" >I< "'* '" '" '" *'" '"

",:+, '" '" '"

* '" ** '" "''''

A$CII ADDRI(

CONVERT B-BIT BINARY DATA INTO ASCII (COBYlE) >

'" * '" '" -+: '" '" '" '" II< '" '" "'''' '" '" >I< '" >I< '" *'" >I< >I< '" '" "'''' "'* '" '" >I< '" '" '"

312
287

LABEL II C()BYTE

SOURCE STATEMENTS

>I<

2B~

II

II

00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013
00014
00015
00016
00017
OOOIB
00019
00020
00021
00022
00023
00024
00025
00026
00027
0002B
00029

00030

IIMCUIIHMCS400 SERIES

CONIS

CONVERT UPPER 4 SITS BINARY INTO ASCll
STORE UPPER ASCII AND INCREMENT ADDR' Y)
STORE LOWER ASCI I

$3

LOAD UPPER ASCII

$9
CONISI
$7

BRANCH IF ASCII;:: '0' -'9'

$4

Ascrl =

'O'_'~I

OH 'A'-IF'

CONVERT BINARY DATA INTO
LOAD UPPER ASC I I

?

I~SCII

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
XCOB:

Defines X address of ASCII.

YCOB:

Defines LSD Y address of ASCII.

70 HITACHI

('A'-'F')

II II

1 8 • COUNT LOGICAL "1" BITS

I

MCU HMCS400 SERIES

II

LABEL

I_

II

FUNCTION

Counts number of logical "1" bits in 8-bit data string in HHBIT and LHBIT(RAM) ,
and loads result into B register; permits easy parity checking.

I

II

ARGUMENTS
Contents

1 digit= 4 bits
No. of
Storage
Location Digits

CHANGES IN CPU
REGISTERS AND FLAGS

•x ::
~

Entry

8-bit number

HHBIT,
LHBIT
(RAM)

Not affected
Undefined
: Result
A

2

I

DESCRIPTION
(1)

B

B

t

2

X

Y

Stack (Digits)
4
No. of cycles
68
Reentrant
No
Relocatable
No
Interrupt OK?
Yes

•
•
W
•

1

I

1 word=lO bits
ROM (Words)
19
RAM (Digits)

x

x

Spy

SPX
No. of
Returns logical "1"
bits

SPECIFICATIONS

CA
x

•

I

ST
x

I

II

Function Details
(a) Argument details
HHBIT,LHBIT(RAM):
B :

Holds 8-bit number in which number of logical "1"
bits will be counted.

Contains number of logical "1" bits in 8-bit number string.

(b) Example of HCNT execution is shown in Fig. 1. If entry argument is
as shown in part 11 II< ** *** '" ***** "' . . "'* "'III"'''' ** III'" 110: "''''*'''''' >II" "'''' >II'" *** ***

200
190
160
190
160
010
213
OAI
06F
30F
310
04C
ODF
30B

00024

IIMCUIIHMCS400 SERIES II LABEL II

040
lOA
04C
lOA

0100
0101
0103
0105
0107
0109
OIOA
o lOS
OIOC
DIDO
OIOE
OIOF
0110
Dill
0112

HC
HCI

HC2
HC3

EOU
EOU
ORG
EOU
LBI
LAMO
CALL
LAMO
CALL
RTN
LYI
ROTL
TC
BRS
BRS
IB
DY
BRS
RTN

$040
$04C

.

UPPER 4-BIT DATA ADDR
LOWER 4-BIT DATA ADDR

SOIOO

SO
HHBIT
HC
LHBIT
HC
$3
HC2
HC3

Hel

ENTRY POINT
CLEAR HIGH BIT COUNTER(B)
LOAD UPPER 4-BIT DATA
CALL I DIGIT COUNTER SUBROUTINE
LOAD LOWER 4-BIT DATA
CALL I DIGIT COUNTER SUBROUTINE
LOAD ROTATION COUNTER(Y)
ROTATE 8-SIT DATA LEFT I BIT
TEST CARRY
BRANCH IF CA • I
BRANCH IF CA • 0
INCREMENT liIGHT BIT COUNTER1<>1<>1<>1< *** **"'*** *** '" '" **

00004

NAME

>I< '"

*"'''' *"''''

>I< >1< .. '"

*** *** *'* ** "'*-*** *'" >I<

SHIFT 8-BIT DATA ( SHR)

OOOOS

aooo¢>

* .. '"

00007
00008
0000 0
00010

>1<;1<

MD($033,$032) (8-BIT BINARY DATA)
8
( ~HIFT COUNTEH)
MD( $033. $032) (8-BIT BINARy DATA)

ENTRY

nODI I

"' ....... ***** **** *********** >I< **

00013
00(11'-1

00015
00016
00017
00018
OOO~!l

000:-':;
00073
00024
00025
OOO~:"6

0(1(127
O()O28

223
'213

XSFT
'15FT

EOU

8ASFT

EOU

$3
$3
.1

ORG

$0100

SHR

EOU

1)100

EOU

LXI
SHRI

LYl

SHR2

XSFT
YSFT

OEC

noo

0101
(J 10'2
0103

0(-\0

01(Jy

LAfl
ROTR

000

0105

LMI~DY

071
303
(leF

0106

YI\JEI

BA~FT

0107

BRS
DB
eR$
RTN

SHR:'

00((:9

~Ol

0003(1

()!()

(lIOB
010'"/
OIOA

..

*** +'*,... ***"'* ************ >I< "'* >I<.+' '" '" '" ** "' .. "' . . '" *** >I< >I< ** ********,j.'''"
RETURNS

00012

01)019
00020

SHR

SERIES II LABEL II

>I< "' .....

** *'" ",,,,>1<* ** '" '" *"'>1< +. **.*** >I< "'>II '''''''* *' >t~.
8-BIT BIN(..)RY DATA ?)ODR(X)
8-BIT BINARY DATH ADDFI

REC

LO(4D erNHRY [If-\"!" f~
ROTATE B TNAf~Y D(.)lA
STORE ~HIF"I DATA ANf) DEC[{fi'lENl

SHRl

DECREMENT SHIFT COUNTfR
tOOP urn Il_ SH[FT r[lllNrER

~~ODR(

y)

1;0

When storing arguments in other RAM locations, change the EQV
operands for the following labels.
XSFT:

Defines X address of 8-bit binary number to be shifted
to the right.

YSFT:

Defines MSD Y address of 8-bit binary number to be shifted
to the right.

BASFT: Defines LSD Y address less I of 8-bit binary number to be
shifted to the right. (YSFT-$2; if this is negative,
value should be defined as $F.)

82 HITACHI

10. 4-DIGIT BCD COUNTER

\

I

FUNCTION

IIMCUI\HMCS400 SERIESIILABELIIIaIIIIIII

1\

Increments 4-digit BCD counter; permits easy counting of interrupts
(external, timer, etc.) .

I

ARGUMENTS

II

Contents

1 digit= 4 bits
No. of
Storage
Location Digits

CHANGES IN CPU
AND FLAGS

•
x

t

--

--

Entry

--

MD($03D "-'
$03A)

4-digit
BCD counter

: Not affected
: Undefined
: Result

A

B

X

Y

x

x

SPX

SPY

•

x

•

4

•

W

•

Returns
Overflow or
no overflow

(1 bit)

CA

CA
I

I

SPECIFICATIONS

I REGISTERS

DESCRIPTION

i

ST
I

x

I

1 word=lO bits
ROM (Words)
10
RAM (Digits)
4
Stack (Digits)
0
No. of cycles
30
Reentrant
No
Relocatab1e
No
Interrupt OK?
Yes

II

(1) Function Details

(a) Argument details
MD($03D"-' $03A):

Used as a 4-digit BCD counter, incremented by every
DECNT execution.

CA

Indicates counter status after DECNT execution.

:

(See Fig. 2)

CA = 1

:

Indicates counter overflows.

CA = 0

:

Indicates counter incremented normally.

(b) Example of DECNT execution is shown in Fig. 1. When DECNT is executed,
4-digit BCD counter is incremented as shown in part I<

NAME

00008
00009
00010
00011
00012
00013
0001"
00015
00016
00017

132

* '" '" "':+. '" >I< >I< '" '" ** '" '" * '" ** >I< >I< "" '" '" *' -. '" '" '" '" '" '" '" '" '" '" '" >1<* >I< ** '" '*' "" '" * '" ** >I< '" >I< '" ** >1<,., *** '" *'

'" '" .ole",,,, ... '" '" >I<

00007

II LABEL I

"'*

4-DIGIT BCD COUNTER I< '" "" >I< >I< '" '" >I< '" '"

*' ** ** '" >t. '" '" -t< ** '" "',.. ** '" '"

>I< '" '"

* 'IOk '" >1/ '" >I< '" ** >I< * >I< '" '" '" '" '" >Ie >I< '"

ENTRY

NOTHING

RETURNS

MD($03D'-$03PI)(4--0IGTr BCD COUNTER)

CA FLAG (CA""O; INCREMENTED. CA= 1: OVERFLOW)

**********"'********* *********"'**-+ "'* "'** ****** *** *** '" **
XDCNT

EQU

$3

YDeNT
BADeN

EOU
EOU

'A

ORG
EQU
LXI
LYI
SEC
LAI
AMC
OfiA
LMAIY
YNEI
BRS
RTN

$0100

OUOl8

00019

DECNT

00020
00021

223
21A

00022

OEF

00023
00024
00025

230
018
OM

00026

OSO

00027

07E

00028
00029

303
010

0100
0101
0102
0103
0104
0105
0106
0107
0108
0109

DECNTl

$E

XDCNT

YDCNT

>I<>t.>!' >I<

*'*_*** **

BCD COUNTER AD DR (X)
BCD COUNTER L~)O ADDR( Y)
BCD TERMINATOR r-OR ADORC()

ENTRY POINT
LOAD' ADDR, =, or <; uses unsigned integers as entry arguments.

L

ARGUMENTS

II

Contents

1 digit= 4 bits
No. of
Storage
Location Digits

First value

MD($033,
$032)

Second value

MD($043,
$042)

II REGISTERS
CHANGES IN CPU
AND FLAGS
•x
t

2

Entry

: Not affected
: Undefined
: Result

A

B
t
Y

x

2

X
x

x

SPX

Spy

•

x

W

Comparison
Returns result

B

•

1

I

I

DESCRIPTION

SPECIFICATIONS

CA
x

I

ST
x

I

1 word=10 bits
ROM (Words)
18
RAM (Digits)
4
Stack (Digits)
0
No. of cycles
28
Reentrant
No
Re1ocatab1e
No
Interrupt OK?
Yes

II

(1) Function Details

(a) Argument details
MD($033,$032) :

Holds the first value of 8-bit binary number.

MD($043,$042) :

Holds the second value of 8-bit binary number.

B

:

Contains $0, $1 or $2 according to comparison result.

(b) Example of CMP execution is shown in Table 1.
If entry arguments are as shown in Table 1, one of 3 codes ($0, $1,
$2) is contained in B register according to comparison result.
(c) Entry arguments are saved after CMP execution.

ISPECIFICATIONS NOTES II
"No. of cycles" in "SPECIFICATIONS" indicates the number of cycles required
to compare 2 values which are the same.

HITACHI 89

II MCUIIHMCS400 SERIES II LABEL I

11. COMPARE 8-BIT BINARY DATA

CMP

DESCRIPTION
Table 1

Example of CMP Execution
Return
Argument

Entry arguments
First value

Second value

MD($043,$042)

B
register

>

$20

$1

$22

=

$22

$2

$40

<

$FO

$0

---------MD($033,$032)

Greater
or less

$F6

----------

(2) User Notes
(a) ST flag is set after CMP execution.
(b) When upper digit is not needed, "0" must be stored in upper digit.
Otherwise correct data cannot be obtained since comparison is
performed with undefined data in upper digit.
(3) RAM Allocation

F1E:D:C1B:A:918i7:6:s:4:3:2:l:0
I
I
I
I
I
I
I
I
I
I

02

:
I

:
I

:
I

I
:

I
I

I
I

I
I

I
I

I
I

I
I

I
I

I
I

I

I

I

I

:

I

I
I
I
_ _ ~--I
I
I
:
I

I

--- .1--"1---'---1--'----1---...--- .... __ J __ ..J.

03
04
05

:

I

:

I

:

I

I
I

I
I

I

__ , __

.:'"'l.

I

--r --:- - i --t--:-- -~--:- -i --~-- . . . - i- - - MSD,LSD

:

I

I

I

:

I

I

I

- -t-I
I
i I MSDrLSD I
L __ +---,---l-- -:--

I

:

I

I

I

I

I

:

I

I

I

- -t- --I- --:-- -,- -~-- +-_I-__

I

I

I

I

I

L--

---Oh-- --~---'-- -:-- +- -;...- ~ - - ~- -:---+--~-- -l---L - -1-- ~ -- ~- --

~

Fig. 1

Label

RAM
b7

bO

Wfh~Jj

bO

;MSD~LSD;
MD($043, $042)

90 HITACHI

I

I

I

I

I

I

I

I

I

RAM Allocation

Description

MD($033, $032)
b7

I

I

First value of 8-bit binary number.
X and Y addresses are defined by XCMD and
YCMT, respectively.
Second value of 8-bit binary number.
X and Y addresses are defined by XCMT and
YCMT, respectively.

11. COMPARE 8-BIT BINARY DATA

IIMCUIIHMCS400 SERIES

IILABEL II

CMP

DESCRIPTION
(4) Sample Application
Shown below is a sample application using CMP with address space allocated
as follows.
MD ($OA3, $OA2)

First value of 8-bit binary number

MD($OB3,$OB2)

Second value of 8-bit binary number

LWI
LAMD

II

Example with W=O.

$OA3 }

LMAD

$033

LAMD

$OA2

LMAD

$032

LAMD

.....

$0

Store the first value of 8-bit binary number
in entry argument.

$OB3 }

LMAD

$043

LAMD

$OB2

LMAD

$042

CALL

CMP

Store the second value of 8-bit binary number
in entry argument.

II· ....

Call CMP.

LAB
Branch to service routine for
First value < Second value

ALEI

$0

BRS

SKIPl

ALEI

$1
}
SKIP2

Branch to service routine for
First value > Second value

BRS

$2
}
SKIP 3

Branch to service routine for
First value = Second value

JMPL

SKIP4

BRS
ALE I

}

(Continued on next page)

HITACHI 91

11. COMPARE 8-BIT BINARY DATA

IIMCUIIHMCS400 SERIESIILABELII

CMP

DESCRIPTION
(Continued from previous page)

SKIPI

Service routine in case of
First value < Second value
JMPL

SKIP2

Service routine in case of
First value > Second value
JMPL

SKIP3

SKIP4

SKIP4

Service routine in case of
First value = Second value

SKIP4
(5) Basic Operation
(a) In HMCS400 series, when comparison is performed with 2 groups of 2 or
more digits, the same operation sequence is repeated for each digit.
(b) After execution of comparison instruction (ALEM), result is contained
in B register.
(c) Upper digits are compared using comparison instruction (ALEM).
(i) If upper digits are the same, lower digits are then compared.
(ii) If not the same, CMP is exited.

92 HITACHI

11. COMPARE 8-BIT BINARY DATA

IIMCU IIHMCS400 SERIESIILABELII

CMP

FLOWCHART

Load MSD of RAM address, where
the first and the second values
are stored, into X and Y registers.

XCMT .... X
YCMT .... Y

____ -CClear B register where comparison
result is stored.

$0 .... B

~-':;:===----,

---[Load the second value from MSD.
___ [Load X address where the first
value is held.
___[compare first value with second
one.

A >M

__ {Test if the first and second
values are the same.

___[Load X address where the second
value is stored.
Y-l .... Y

___ rDecrement Y address where the first
L-and second values are stored.

Y+BACMT

Test if comparison for all digits
[ is completed.

Y=BACMT

HITACHI 93

11. COMPARE 8-BIT BINARY DATA
PROGRAM LISTING

IIMCUIIHMCS400 SERIES IILABEL II

II

ST-NO

OBJECT

ADRS

00001
00002
00003

010

0000

SOURCE STATEMENTS

LLEN

00004
00005

NAME

00006
00008
00009
00010
00011
00012
00013
000)4

RETURNS
>I(

>I< >I< '" >I< >I< "')/( '"

*XCMO
XCMT

YLMT

EQu

BACMT

[OU

00020

eMP

00021

223

00022

001
22"+

000:28
000:..-:9

213
'200
091
014
309
"~ j 1

0100
01Dl
0[02
0103
0104

010S

Cl'lPl

0106

004

0108
01(19

00031

,310

CIIO(~

00032

001

010B

>1<;1< >I< >I< '" >I<

** >I< >I< >I< '" >I< >I< >I< >I< ***** >I< ** >I< >I< ** ** '" '" >I<
FIRST VALUE ADDR( X)
SECOND VALUE AD DR I< >I< >I< >I< '" >I< >I< >I< '" >I< ** >I< >I< '" '" '" '" ** >I< >I< **** '" '"

L'!I
LSI
ALEM
BRS

0107

00030

ORG
EOU
LXI
XSPX

>1<:>1< >I< '"

MD($Q33. >032) (FIRST VALLIE)
MD($043. $042) ( SECOND VALUE>
B
(COMPARI SON RESUL T )

** >I< * >I< >I< ** ** '"
EOU
EQU

00015

00027

***'" '" ** '" "' . . >I< '"

ENTRY

00016
00017
00018
01)019

OOOT'::
0002';'

: COMPARE 8-BIT BIN!\RY DATA (CMP)

>I< '" '" >I< '" '" '" >I< >I< >I< >I< >I< >I<

00007

000'25
00026

132

>1<**>1<"'***"'**********************"'***********"'*******"'**"'''''''**

LI~JA[) ':.[COf')Cl V(~l.UE
DE TERr'l [Nr: REU'lTtrJl'J

CMP3

BACMT

CMPI

,.,

.,.

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
XCMD:

Defines X address of the first value.

XCMT:

Defines X address of the second value.

YCMT:

Defines MSD Y address of the first and second values.

BACMT: Defines loop terminator value for comparison with
decremented Y address. (YCMT-$2; if this is negative,
value should be defined as $F.)

94 HITACHI

CMP

12. ADD 8-BIT BINARY DATA

I

FUNCTION

IIMCUIIHMCS400 SERIESIILABELI

II

-

~

Performs addition of 8-bit binary data in RAM, and stores result in RAM;
uses unsigned integers as arguments.

I

ARGUMENTS

II

Contents

1 digit 4 bits
No. of
Storage
Location Digits
HAUG,
LAUG
(RAM)

Augend
Entry
Addend

HADD,
LADD
(RAM)

Addition
result

HAUG,
LAUG
(RAM)

CHANGES IN CPU
REGISTERS AND FLAGS

•x ::

Not affected
Undefined
t : Result

2

A

CA

I

DESCRIPTION

ST

B

•

x

X

2

Y

•
•W

•

Spy

SPX
2

•

•

Returns
Carry or
no carry

SPECIFICATIONS

(1 bit)
(1 bit)

I

CA

f

I

ST

t

I

1 word=10 bits
ROM (Words)
14
RAM (DiAits)
4
Stack (Digits)
0
No. of cycles
.li.
Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

(1) Function Details
(a) Argument details
HAUG, LAUG(RAM): Holds augend of 8-bit binary number.
execution, contains addition result.

After ADD

HADD, LADD(RAM) : Holds addend of 8-bit binary number.
CA, ST

: Indicates whether a carry is generated or not after

ADD execution.
CA=l, ST=l

: Indicates a carry is generated in addition result.

(See Fig. 2)
CA=O, ST=O

: Indicates no carry is generated in addition result.

HITACHI 95
------------ - - - - - - -

I II

12. ADD 8-BIT BINARY DATA

MCU

HMCS400 SERIES

II

LABEL

I

ADD

DESCRIPTION
(b) Example of ADD execution is shown in Fig. 1.

If entry arguments are
as shown in part 
FLAG (CA=O.ST-Q;BORROW
CA-l.ST=I;NORMAL RETURN)

*******Jk",********************************",************** .. ** ... *** . .

HMIN
LMIN
HSUB
LSUB
~U8

OEF
190
19B
194
190
19B
194

010

04C
03C
03C
040
030
030

0100
0101
0103
0105
0107
0109
0106
0100

Eeu
EeU
EeU
EOU

$03D
$03C
$04D
S04C

ORG
EeU
SEC
LAMD
SMCD
LMAD
LAMD
SMCD
LMAD
RTN

$0100
LSUB
LMIN
LMIN
HSUB
HMIN
HMIN

UPPER
LOWER
UPPER
LOWER

MINUEND
MINUEND
SUBTRAHEND
SUBTRAHEND

ENTRY POINT
SET CARRY FLAG
LOAD LOWER SUBTRAHEND
SUBTRACT LOWER SUBTRAHEND FROM LOWER MINUEND
STORE LOWER SUBTRACTION RESULT
LOAD UPPER SUBTRAHEND
SUBTRACT UPPER SUBTRAHEND FROM UPPER MINUEND
STORE UPPER SUBTRACTION RESULT

When storing arguments in other RAM locations, change the EQU
operands for the following labels.

108 HITACHI

HMIN:

Defines upper digit address of minuend.

LMIN:

Defines lower digit address of minuend.

HSUB:

Defines upper digit address of subtrahend.

LSUB:

Defines lower digit address of subtrahend.

14. MULTIPLY l6-BIT BINARY DATA

I

I

FUNCTION

IIMCUIIHMCS400 SERIESIILABELI

IIIIIIaIII

II

Performs multiplication of l6-bit binary data in RAM, and stores 32-bit
binary product in RAM; uses unsigned integers as arguments.

I

ARGUMENTS

II

Contents
Multiplicand
Entry

1 digit= 4 bits
Storage
No. of
Location Digits
MD($03D 'V
4
$03A)
MD($049 'V
$046)

Multiplier

Product
MD($04D'V
(upper 16
$04A)
Returns
bits)
Product
MD($049'V
(lower 16
$046)
bits)

I

DESCRIPTION

II CHANGES
IN CPU
REGISTERS AND FLAGS
•x
t

: Not affected
: Undefined
: Result

A

4

1 word=lO bits
ROM (Words)
29
RAM (Digits)

B

x

x

X

y

x

x

SPX

Spy

x

n

•

W

4

SPECIFICATIONS

•
4

CA
I

x

I

ST
x

I

Stack (Digits)
0
No. of cycles
1550
Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

(1) Function Details
(a) Argument details
MD ($03D 'V $03A) : Holds l6-bit binary multiplicand.
MD($049 'V $046): Holds l6-bit binary multiplier. After MUL execution,
contains lower l6-bit of product.
MD ($04D 'V $04A) : Contains upper l6-bit of product.
(b) Example of MUL execution is shown in Fig. 1. If entry arguments are
as shown in part Multiplicand x bit 1 of multiplier (0)->-

0

Multiplicand x bit 2 of multiplier (0)->Multiplicand x bit 3 of multiplier (1)->-

Multi'0 : 1: ... plicand
:0 i 1: ... Multiplier
I

0

0

0

+1

1

0

1

1

1

1

0

1

"i

... 2 Partial

... Q) products

... ®.
1

0

1

... 0) Product

(G)+@+Q)+@)
Fig. 4

Multiplication Example ($D x $9 = $75)

Multiplication of l6-bit binary data requires obtaininjl partial products,
as shown in
@,
and ®, and adding them.
(~in Fig. 4)
Each bit of binary data is either "0" or "1". If multiplier bit is "1",
its partial product is multiplicand (
and ® in Fijl. 4), while i f
multiplier bit is "0", its partial product is "0". «(V and
in
Fig. 4)

CD,

®

CD

®

(b) Program operation is described below according to the multiplication
example in Fig. 4.
(i) RAM for upper digit of product is cleared.
(ii) LSB of multiplier is tested whether it is "0" or "1" to obtain
partial product.
(iii) B register is decremented.
(iv) Operation loops (ii) and (iii) until B register is $F.

114 HITACHI

14. MULTIPLY 16-BIT' BINARY DATA

IIMCU IIHMCS400 SERIES II LABEL II

MUL

___ [ Load product and multiplier
address into X register.

- - { Clear RAM for produ«.

___ [ Load counter indicating number of
partial products.
___[Load LSD address where multiplier
is stored into Y register.
___[Clear CA flag so that "1" is not
set in MSB, when rotating RAM
for product.
___[Test whether LSB of multiplier is
"l" or "Olt.

Store LSB of product in MSB of
multiplier.
Rotate the next bit to calculate
the next partial product into
LSB of multiplier.

__ _ [Decrement counter indicating
number of partial products.

B#$F

___ [Test if all partial products
have been acquired.

HITACHI 115

14. MULTIPLY l6-BIT BINARY DATA

I

MCU IIHMCS400 SERIES

II

LABEL

/I

MUL

FLOWCHART

___ {save X address of product and

~====JC====~

multiplier.
- - - { Load X address of multiplicand.
- - - { Load Y address of LSB of multiplicand.

A+M
Y+I +Y

When LSB of multiplier is "1",
add multiplier to product because
partial product is multiplier in
this case.

X +-+ SPX

Y=BACAN
___ {Restore X address of product and
~-----r----~
multiplier.

116 HITACHI

14. MULTIPLY l6-BIT BINARY DATA
PROGRAM LISTING
ST-NO

OBJECT

AORS

010

0000

00038
00039
00040

00041

.

LLEN

132

...

*** * * '" *** * '" ** *"' ... "' . . . . *'" ** lie"'' ' "'* '" '" ** ... '" >I< '" ***** ...... "'lie.'" "'* '" ** * * * *
NAME , MUL TIPL Y a-BIT BINARY DATA (MUll

MD(S030-S03A) (MUL TIPLICANO)
MO(S049-$046) (MUL TlPLIER)
MD( $040-S046) (PRODUCT)

ENTRY

.

RETURNS

*********************************************** ... ********

224
21A
290
07E
302
20F
216
OEC
OBC
313

0100
0101
0102
0103
0105
0106

OAO

OlOe

000
075
308

0100
OIOE
010F
OlIO

00044

223

00045
00046

21A
091
018.
051
07E
316

DOl
30A

EQU
EQU
EQU
EQU
EQU
EQU
EQU

MUL

ORG
EQU
LXI

LYI
MUll

MUL2

0107

090

OCF

XMCAN
XPROW
YMLSB
YMPRO
YMCAN
BAPRO
BACAN

0104

0108
0109
OIOA
OIOB

210

306
010
001

00048
00049
00050
00051
00052

SOURCE STATEMENTS

********************************************************

00042
00043

00047

MUL

II

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036

00037

IIMCUIIHMCS400 SERIESIILABELII

6RS
MUL_'3

LYl

MUL4

LAM
ROTR
LMADY
YNEI
BRS
DB
BRS
RTN

Dill
MUL5

0114
OilS
0116
0117
011B
0119
OIIA
OIIB
OIIC

LYI
REC
TM

0112

O1l3

LMI!Y
YNEI
BRS
LBI

so

SA
$5
SE

LYI
LAMX
AMC
LMAIYX
YNEI
BRS
XSPx
BRS

MUL TIPLICANO
MUL TIPLIER &
MUL TlPLIER &
MULTIPLICAND
MULTIPLICAND
MULTIPLICAND
MUL TlPLICANO

ADOR(X)
PRODUCT AOOR(X)
PRODUCT LSD ADDR( Y)
& PRODUCT MSO AOOR(Y)
LSD ADDR(y)
& PRODUCT LSD ADDR(y)-1
& PRODUCT MSD ADDR(y)+1

S0100
XPROW
YMCAN

sO
BACAN
MUll
SF
YMLSB
SO
MUL5
YMPRO

ENTRY POINT
LOAD MULTIPLIER & PRODUCT ADDR(X)
LOAD MULTIPLICAND ADDR(Y>
CLEAR PRODUCT
LOAD BIT COUNTER
LOAD MULTIPLIER LSD ADDR INTO REG(Y)
CLEAR CARRY
TEST LSB OF PRODUCT = $0 ?
BRANCH IF LSB = $1
ROTATE PRODUCT AND MULTIPLIER I-BIT RIGHT

BAPRO
MUlA
MUL2

DECREMENT BIT COUNTER
LOOF' UNTIL BIT COUNTER'" !oF

XMCAN
YMCAN

SAVE PRODUCT & MULTIPLIER AOOR(X)
LOAD MULTIPLICAND ADDR(X> INTO REG(X)
LOAD MULTIPLICAND LSB ADDR(y) INTO REG(n

XSPX

LXI
MUL6

$3
$4
$6

MULl IPL ICAND + PRODUCT -\ MUL TIPL I(AND
BACAN
MUL6
MUL3

LOAO NEXT L S8

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
XMCAN:

Defines X address of multiplicand.

XPROW:

Defines X address of product and multiplier.

YMLSB:

Defines LSD Y address of product and multiplier.

YMPRO:

Defines MSD Y address of product and multiplicand.
(YMLSB + $7)

YMCAN:

Defines LSD Y address of multiplicand.
(YMLSB + $4)

BAPRO:

Defines LSD Y address less 1 of product and multiplicand.
(YMLSB-$l; if this is negative, value should be defined
as $F.)

BACAN:

Defines MSD Y address plus 1 of product and multiplicand.
(YMPRO + $1; if this is overflow, value should be defined
as $0.)

HITACHI 117

II I

115. DIVIDE 16-BIT BINARY DATA

I

FUNCTION

MCU

HMCS400 SERIES

II

LABEL

1_

JI

Performs divisions of 16-bit binary data in RAM, and stores result
(quotient and remainder) as l6-bit binary data in RAM; uses unsigned
integers as arguments.

I

ARGUMENTS

II

Contents

1 digit 4 bits
No. of
Storage
Location Digits

Dividend

MD($03A "-'
$037)

Divisor

MD($04E "-'
$04B)

II REGISTERS
CHANGES IN CPU
AND FLAGS

•x

4

4

MD($03E "-'
$03B)

4

I

DESCRIPTION

1 word;lO bits
ROM (Words)

Undefined

:

A

B

x

x

X

Y

x

x

SPX

Spy

~

RAM (DtRits)
12
Stack (Digits)
0
No. of cycles

•

x

MD($03A "-'
$037)

W

llJ.1l..

•

Returns
Remainder

: Not affected

t : Result

4

Entry

Quotient

SPECIFICATIONS

I

CA

I

x

ST
x

I

Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

(1) Function Details
(a) Argument details
MD($03A"-'$037) : Holds l6-bit binary dividend.
contains quotient.

After DIV execution,

MD($04E"-'$04B) : Holds l6-bit binary divisor.
MD($03E"-'$03B): Holds l6-bit binary remainder.
(b) Example of DIV execution is shown in Fig. 1.
If entry arguments are as shown in part
of Fig. I, division result
is contained in MD($03E "-'$037).

Q)

I

SPECIFICATIONS NOTES

I

"No. of cycles" in "SPECIFICATIONS" indicates the number of cycles required to
devide $FFFF by $2.

118 HITACHI

115. DIVIDE 16-BIT BINARY DATA

I

IIMCUIIHMCS400 SERIES

DESCRIPTION

Q)

II LABEL I

DlV

Return arguments

Quotient
Remainder
MD ($03A 'V $037)
MD ($03E 'V $03B)
b15
bO
b15
bO
10 10 10141----- I 0 1 F 13 I D 1
b15 Divisor bO
111010101
!

b15 Dividend bO
I 4 IF 13 1 D 1

MD($04E 'V $04B)

CD

.

MD($03A'V$037),

Entry arguments
Fig. 1

Example of DIV Execution

(c) Table 1 shows results when $0 is held in entry arguments.
Table 1

Results When Holding "0" in Entry Arguments

Entry Arguments
Dividend
MD($03A 'V $037)

Return Arguments

Divisor
MD($04E'V$04B)

$ 'Id< ** (note)

~OOOO

$0000

$'~***

$0000

$0000

Quotient
MD($03A 'V $037)

(note)

Remainder
MD ($03E 'V $03B)

$FFFf

$**** (note)

$0000

$0000

$FFFF

$0000

(note) $****: Hexadecimal data
(2) User Notes
(a) ST flag is set after DIV execution.
(b) When upper digits are not needed, "0" must be stored in upper digits
as shown in Fig. 2. Otherwise correct results cannot be obtained
since division is performed with undefined data in upper digit.
Quotient

I 0 lot 0 I 31
Divisor

--t 0 I 0

I 0 I CI

Fig. 2

Remainder
---

I 0 lot 0 I B I

)IOIOFIFI

Dividend
Division Example When Upper Digit is Not Used

HITACHI 119

115. DIVIDE l6-.BIT BINARY DATA

I

IIMCUIIHMCS400 SERIESIILABELII

DIV

DESCRIPTION
(c) After DIV execution, dividend is· destroyed since quotient is contained
in MD($03A 'V $037). If dividend needs to be retained after· execution.
it should be saved in memory before execution.

9

W.
02

03
04
05

8

1

7

3 :2 .' 1

I

I

;

I

I

:

:

:

:

:

:

1
1

1
1

:

I

:
I

I

I

I

:

1

LSD

MSn!==t==LSD

-,

0

,

1
1

1
1

I
I

1

I

of - - ... - - -t-- -T-- J - :
1
:
:
:
:
:
:
--'---,-- T--l--~--r--"1---I--,--.J---

1

:

I
1

1

I

"
1

I

1

+- - 1-- -1- - ,-- T--~ - -~--,--T - -,- -,--,--, --, -Fig. 3

,

,
I
1
1
1
1
I
1
___ 1._.1 __ L _! __ L __ -'-_.l __ .l
1

1

I

1

1

RAM Allocation

RAM

Description

b15

bO

l6-bit binary dividend before execution.
l6-bit binary quotient after execution.
X and Y addresses are def.inedby XDEND
and YDSOR, respectively.

bO

l6-bit binary divisor.
X and Y addresses are defined by XDSOR
and YDSOR. respectively.

bO

Work area where subtraction result
(Dividend-Divisor) is contained.
Stores l6-bit binary remainder after
execution. X and Y addresses are defined
by XDEND and YDEND. respectively •

llif~1
MD ($03A 'V $037)

tMSD

1

I

I

~~~~~:e:~""'4"~~'-'t~~- -1- -

1

b15

6 : 5 : 4

~~~~~~~~~~~?777~--~--L--~--~---~--~--

--1--

Label

I
I

i LSDl
MD($04E 'V $04B)

b15

~~~
MD($03E'V$03B)

.120 HITACHI

115.
I

DIVIDE l6-BIT BINARY DATA

IIMCUIIHMCS400 SERIES II LABEL II

DIV

DESCRIPTION

(4) Sample Application
Shown below is a sample application using DIV with address space allocated
as follows.
MD($OAA'V $OAn: Dividend.

After execution, quotient is contained.

MD($OAE'V $OAB): Divisor.

After execution, remainder is contained.

LWI

$0

LXI

$3

----Example with W=O.

XSPX

WORKl

LXI

$A

LYI

$7

LAMX

Store l6-bit binary dividend in entry
argument.

LMAIYX
YNEI

$A

BRS

WORKI

LXI

$4

XSPX

WORK2

LXI

$A

LYI

$B

LAMX

------ Store l6-bit binary divisor in entry
argument.

LMAIYX

II

YNEI

$F

BRS

WORK2

CALL

D_IV
__~II------Call DIV.

LXI

$A

U-____________

XSPX

WORK3

LXI

$3

LYI

$7

LAMX

------ Store division result, contained in
return arguments, in RAM.

LMAIYX
YNEI

$F

BRS
I

WORK3

I
I

HITACHI 121

115. DIVIDE 16-BIT. BINARY DATA

I

IIMCUIIHMCS400 SERIES II LABEL II

DlV

DESCRIPTION
(5) Basic Operation
(a) In binary data division, quotient and remainder are obtained by repeated
subtraction. Fig. 4 shows an example of binary division ($D ~$3).

G)
I
I

i
Divisor

-+

1

1

/

1

1

-)

1

1

-)

+)

$,,
0

0

1

-<-

Quotient
Dividend

~-Q)

0

0

--0

1

1

- 0

1

--@
--0)

1

1

0

0

-)

1

1

1

- 1

0

1

1

0

1

+)
0
Fig. 4

0

Division Example ($D

-<-

Remainder
$3)

(b) Referring to the division example in Fig. 4, the program is executed
as follows.
(i) RAM is cleared for remainder MD ($03E 'U $03B).
(ii) B register is used as shift counter.
(iii) CA flag is initialized to "1" to set "1" in RAM for quotient.
(iv) MD($03A 'U $037) (dividend) and MD($03E 'U $03B) are rotated 1 bit left
to set "1" in RAM for quotient. At the same time MSBis rotated into
LSB.
(v) This is performed because upper bits are fetched one by one from
dividend to subtract divisor MD($04E 'U $04B). Divisor MD($04E 'U $04B)
is then subtracted from MD($03E'U$03B). If subtraction result is
positive, "1" is retained in the LSB of MD($03A'U$037).
(Fig. 4 G) ....
G)
If subtraction result is negative, LSB of MD($03A'U$037) is cleared
and added divisor to subtraction result.
(Fig. 4 @ .... ® .... ® )

0 ..

(vi) Shift counter is decremented.
(vii) Operation loops from (iii) to (vi) until shift counter is "0".

122 HITACHI

115.

I

DIVIDE l6-BIT BINARY DATA

IIMCUIIHMCS400 SERIESIILABELII

DIV

FLOWCHART

~~~

---[

Clear work area, where remainder
will be stored after execution.

---[

Load number of shifts into shift
counter.

---[

Load divisor address into X and Y
registers.

---[

Initialize CA flag to "1" in RAM
for quotient.

Rotate MSB of dividend into LSB
in work area.

---[

--{

Set CA flag to perform
subtraction.
Load X and Y addresses of LSB of
work area and divisor.

Subtract divisor from work area.

HITACHI 123

II

115. DIVIDE 16-BIT BINARY DATA

I

Meu IIHMCS400 SERIES

II LABEL II

FLOWCHART

CA=1

---{

Test whether subtraction result
is positive or negative.

---{
---{

Clear CA flag to perform addition.
Load LSB of work area into
Y register.

Add divisor to subtraction result
to restore contents of work area.

A->-M
Y+I ->- Y
SPX ++ X

Clear "1" in RAM for quotient.

----[
___ {

124 HITACHI

Decrement shift counter.
Test i f shift is completed.

DIV

115.

I

DIVIDE l6-BIT BINARY DATA
PROGRAM LISTING
ST-NO

OBJECT

ADRS

00001
00002
00003
0000 ..

30A

0000

IIMCUIIHMCS400 SERIES II LABEL

SOURCE STATEMENTS

LLEN

132

'" '" >I< >I< "' .... >I< '" '" '" >I< >I< '" '" >I< '" '" >I< >1<>1<>1< >I< >I( II<

NAME

of< '"

>1< ... '"

** '" * >1<,.. ***** >I< >I<

*** ""** *** ***'... ************ "'** *"'*'",
MD( $03A-I,0371
MD( $04E -$04B)
MO( $03A-$037)
MD( $03E-$03B)

ENTRY

00009
RETURNS

00010

* '" *' '" '" >I< >I< '" '" >I< '" '"

DIVIDE 16-BIT BINARY DATA (DIV)

*********"'** "''''*'''''' '"

00006
00007
00008

00011

(DIVIDEND)
(DIVISOR 1
(QUOTIENT)
(REMAINDER)

00012
00013

******** '" *** "',,"* "'****************** * "'''''''''''''''' ******* **

OOOly
00015

XDENO
XDSOR
'mEND

00023
00024
00025
00026
00027
00028
00029
00030
00031
(JOO32
00033

0003':'

YDSOR

BADIV
DIV
0100
0101

290
07F

0102

302

0104

2(lF

0105
0106
0107
0108
0109
OIOA
0108
OIOC
0100
alOE
OlaF

223
217
OEF
090
O(-H

050
07F

00035

309

00036

OEF
218

00037
00038
nOO39

aLlO

00040
00041
00042
01)043
OOC1o:.4

(\91
("1':)8

0112
0113

(lSI

0114

O"?F
517

011 ~j
0116

00045

06F

0117
0118

0OO4t.
00048
00049
00050
00051

..; •• ...J

OFC
:218
091

OIlA
0118

olle

01lD
OllE
OIIF
0120

00055

217

000S6

081]
OCF
3(]t:.

0121
0122

00054
00057
00058
00059

010

DIV3

0123

EOU
EOU
EOU
EOU
EQU
ORG
EOU
LXI
L Y!
LMIIY
YNEI
BRS
LSI
LXI
L'!I
SEC
LAI1

$3
$4
$7
'8
OF

.

DIVIDEND. QUaT lENT & REMAINDER AODR(X)
01 VI SOR ADDR
DIVIDEND & QUOTIENT LSD ADDR
SET CARRY FU~G
SHIFT DIVIDEND 1-·8IT LEFTTO LOAD MSB OF DIVIDENO INTO LS8 OF WORK AREJ:.)

8ADIV
DIV3
YOSOR

SET CARRY FLAG
LOAD DIVISOR (.-\ODR(Y)

XSPX

DIV4

L)lI
LAMX
::;l'lC
LMATYX
"(NEI
BRS

TC
8RS
REC
L.Y!

OL 19

051
07F
:518
001

0(1053

OIV2

0111

018

00052

DIVI

0103

001
224

00047

>I<

>I<

223
218

DIV

I

00005

00016
00017
00018
00019
00020
00021
00022

II

[JIVS

XDSOR

LOAD c·rVISOR (.!jODR(X)
REMAINDER - DIVISOR - , REMAINDER

BRDIV
OIV4

TE:'T fARRY
DIV6

BRANCH IF REMAIN

) DIVIDEND
CARRY FL ?)G
LOAD l.SB OF WOR, AREA INTO REG(n
REM(UNOER + DIVJ:::;O~: - > REMAINDEf~

CL.EAR

YDSOR

U-)MX

AMC

LMAIYX

'r'NET
BRS

BADIV
DJV5
CLEr;R LSB OF OUOTIENT

x~px

LYI
REM
DIV6

YOEND

,0

[>8

0124

BRS

0125

RTtJ

0lV2

DECREMENT SHIFT COUNTER
LOOP UNTIL SHIFT COUNTER

$F

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
XDEND:

Defines X address of dividend, quotient and remainder.

XDSOR:

Defines X address of divisor.

YDEND:

Defines LSD Y address of dividend and quotient.

YDSOR:

Defines LSD Y address of divisor and remainder.
(YDEND + $4)

BADIV:

Defines MSD Y address plus 1 of divisor and remainder.
(YDEND + $8; if this is overflow, value should be defined
as $0.)

HITACHI 125

-

116. ADD 8-DIGIT BCD

I

FUNCTION

II

Performs addition of 8-digit BCD data in RAM, and stores result as 8-digit
BCD data in RAM; uses unsigned integers as arguments.

I

ARGUMENTS

II

Contents

1 digit= 4 bits
No. of
Storage
Location Digits

Augend

MD ($03D 'V
$036)

Addend

MD($04D'V
$046)

CHANGES IN CPU
REGISTERS AND FLAGS

•x
t

8

: Not affected
: Undefined
: Result

Entry

A

MD ($03D 'V
$036)

8

Carry or
no carry

CA

(1 bit)

x

x

SPX

SPY

x

•

W

DESCRIPTION

55

•

Returns

I

•

Y

X

I

CA
~

I

ST

f

SPECIFICATIONS

1 word=lO bits
ROM (Words)
12
RAM (Digits)
16
Stack (Digits)
0
No. of cycles

B

x

8

Addition
result

I

I

Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

(1) Function Details

(a) Argument details
MD($03D'V$036): Holds 8-bit BCD augend.
addition result.

After ADDD execution, contains

MD ($04D'V$046) : Holds 8-bit BCD addend.
: Indicates whether a carry is generated or not after

CA

ADDD execution.
CA=l

: Indicates a carry is generated in addition result.

(see Fig. 2)
: Indicates no carry is generated in addition result.

CA=O

I

SPECIFICATIONS NO'rES

.

N/A

126 HITACHI

II

~6.

I

II MCU II HMCS400 SERIES II LABEL II

ADD 8-DIGIT BCD

ADDD

DESCRIPTION
(b) Example of ADDD execution is shown in Fig. 1.

CD

If entry arguments are as shown in part
of Fig. 1, addition result
is contained in MD($03D'V$036) as shown in part @ of Fig. 1.

Entry
arguments

MD($03D 'V $036)b3l
MD($03D '0$036)
(12478032)
11 /2 14 / 7/ 8 / 0/ 3

1

MD($04D 'V $046)
(76008901)

bO

I2 I -

MD($04D '0$046)
/ 7 /6 /0/ 0 / 8 / 9 / 0 /1 I
.. . . . . . .

_

Augend

Addend

+)

@
2

Return
{MD($03D'V$036)
arguments (88486933)

Fig. 1

CA b31

I]]

MD($03D 'V $036)

bO

/ 8 /8 I 4 I 8 / 6 / 9 I 3 / 3 I -

Addition
result

Example of ADDD Execution

(2) User Notes
(a) ST flag is set after ADDD execution.
(b) When upper digits are not needed, "0" must be stored in upper digits
as shown in Fig. 3. Otherwise correct addition result cannot be
obtained since addition is performed with undefined data in upper
digits.

I 0 1 0 1 0 1 0 1 1 1 2 1 3 1 4 I- Augend

19161318121011101
+)
CA

11141012161010101

CA

[2J

IT]
Fig. 2

+)

Addition Example When
Carry is Generated

I 0 1 0 1 0 1 0 1 2 1 3 16 15

I- Addend

I 0 1 0 1 01 0 1 3 15 19 1 9!-Addition
result

Fig. 3

Addition Example When
Upper Digits are Not Needed

(c) After ADDD execution, augend is destroyed since addition result is
contained in MD($03D'V$036). If augend needs to be retained after ADDD
execution, it should be saved in memory before execution.
(d) BCD number must be stored in augend and addend, otherwise correct
addition result cannot be obtained.

HITACHI 127

116. ADD 8-DIGIT BCD
I

DESCRIPTION

II MCU II HMCS400 SERIES II LABEL"

ADDD

1/

(3) RAM Allocation

06

~
Fig. 4
Label

RAM Allocation
Description

RAM
b3l

bO

f£S~B
MD($03D '\,$036)

b3l

-

IMSD

bO

! ! MD($04D
i !'\, $046)
! ! !LSD\

8-digit BCD augend before
execution.
8-digit BCD addition
result after execution.
X and Y addresses are
defined by XAUGE and YAUGE,
respectively.
8-digit BCD addend
X and Y addresses are
defined by XADDE and YAUGE,
respectively.

(4) Sample Application
Shown below is a sample application using ADDD with address space allocated
as follows.
MD($OAD'\,$OA6) : Augend. After execution, addition result is
containd.
MD ($OBO '\, $0B6) : Addend

128 HITACHI

16. ADD 8-DIGIT BCD

IIMCUIIHMCS400 SERIES II LABEL

II

ADDD

DESCRIPTION
LWI
I
II
LXI

$0

------ Example with W=O.

$3

XSPX

WORKl

LXI

$A

LYI

$6

------ Store 8-digit BCD augend in entry
argument.

LAMX
LMAIYX
YNEI

$E

BRS

WORKl

LXI

$4

XSPX

WORK2

LXI

$B

LYI

$6

------ Store 8-digit BCD addend in entry
argument.

LAMX
LMAIYX
YNEI

$E

BRS

WORK2

II CALL

ADDD

Te
BRS

OVER

LXI

$A

II

------ Call ADDD.

}------ If a carry is generated in addition
result, branch to service routine.

XSPX

WORK3

LXI

$3

LYI

$6

LAMX

------ Store addition result, contained in
return argument, in RAM.

LMAIYX

OVER

YNEI

$E

BRS
II

WORK3

I
I
I

Service routine
in case of carry

HIT4CHI129
)

116.

I

II MCU II HMCS400 SERIES II LABEL I

ADD 8-DIGITBCD
DESCRIPTION

ADDD.

1/

(5) Basic Operation
(a) In HMCS400 series, when addition is performed with 2 or more digits,
the same operation sequence is repeated for each digit.
(b) X and Y registers are used as a pointer to augend and addend.
(c) CA flag is first cleared. Formula 1 is performed on each digit of
augend and addend using register indirect addressing mode .
Augend + Addend + (CA) + Accumulator

• . • . , (Formula 1)

CA flag is added in Formula 1 since digits previously added
occasionally generate a carry.
(d) Addition result calculated in (c) is adjusted to a decimal value using
the decimal adjust instruction (DAA). The result is then stored in
RAM in the augend location.
(e) Y register is incremented every time (c) and (d) is executed.
(f) Operation loops from (c) to (e) until 8-digit addition is completed.

130 HITACHI

116.
I

I

ADD 8-DIGIT BCD

MCU IIHMCS400 SERIES

II

LABEL

II

ADDD

FLOWCHART

--- [

Load augend address into SPX register.

--- [

Load addend address into X register.

___ [

Load LSD address of augend and
addend into Y register.

___ [

Clear CA flag to perform addition.

___[

Load addend digits from LSD.

- - - [ Load X address of augend.

A ... M

__ {

Perform addition (Augend+Addend+CA).

___ [

Adjust addition result to decimal.

---

[

Y+l ... Y

- - -[

Store decimal-adjusted result in
RAM at augend location.
Load X and Y addresses of addend
for next addition.

SPX ....... X

___ [

Test i f addition of all digits is
completed.

~---'

HIT~CHI131

-------------------------------- - - - - - - - - - -

116.

I

II II

ADD 8-DIGIT BCD
PROGRAM LISTING

MCU

II LABEL II

II

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025

010

0000

00026

HMCS400 SERIES

SOURCE STATEMENTS

·
·
·•
·

LLEN

132

.

"''''''' ... "'''''''''''''''' "'* >II "'*"'* *"' ••• "''''''''''''''''*'''''' "'''''''*'''''''''''' ***** ***********
NAME : ADD 8-DIGIT BCD (ADDD)

******************************"'*"'*********************"''''

.

: MD(S03D-5036) (AUGEND)
ENTRY
MO( $040-5046) (ADDEND)
RETURNS: MO( $03D-S036lII '" '" "'*"'«

XAUGE
XADDE
YAUGE
BAAUG
ADOD

223
001
224
216
OEC

00027

091

00028
00029

018
OA6

00030
00031
00032
00033

051
07E
30S
010

0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
OIOA
OIOB

ADDDI

>to

EQU
EQU
EQU
EQU
ORG
EQU
LXI
XSPX
LXI
LYI
REC
LAMX
AMC
DAA
LMAIYX
YNEI
BRS
RTN

$3
$4
56
SE

.

AUGEND ADDR(X)
ADDEND ADDR(X)
ADDEND .& AUGEND LSD ADORO')
ADDEND & ;\UGEND MSD ADDRA
ADJUST RESULT INTO DECIMAL
STORE RESULT IN AUGEND
TEST IF ADDITION IS COMPLETED
LOOP UNTIL REG(y) = BMUG

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
XAUGE:

Defines X address of augend.

XADDD:

Defines X address of addend.

YAUGE:

Defines LSD Y address of augend and addend.

BAAUG:

Defines MSD Y address plus I of augend and addend.
(YAUGE + $8; if this is overflow, value should be defined
as $0.)

132 HITAC~I

ADDD

117 .

I

II II

SUBTRACT 8-DIGIT BCD
FUNCTION

MCU HMCS400 SERIES

II I _
LABEL

JI

Performs subtraction of 8-digit BCD data in RAM, and stores result in RAM',
uses unsigned integers as arguments.

I

ARGUMENTS

II

Contents

1 digit- 4 bits
No. of
Storage
Location Digits
MD($03D '"
$036)

Minuend
Entry

MD($04D '"
$046)

Subtrahend

Subtraction
result

MD($03D '"
$036)

I

CHANGES IN CPU
REGISTERS AND FLAGS

.

: Not affected
x : Undefined
~ : Result

8

Borrow or
no, borrow

I

DESCRIPTION

1 word=lO bits
ROM (Words)
12

A

B

•

x

8

Y

X
x
SPX
x
W

8

x

Spy

•

•

Returns
CA

SPECIFICATIONS

(1 bit)

I

CA

f

I

ST

f

I

RAM (Digits)
16
Stack (Digits)
0
No. of cycles
55
Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

(1) Function Details
(a) Argument de'tails
MD($03D'V$036): Holds 8-digit BCD minuend.
After SUBD execution, contains subtraction result.
MD($04D'V$046): Holds 8-digit BCD subtrahend.
CA

: Indicates whether a borrow is generated or not after

SUBD execution.

i

CA=l

: Indicates no borrow is generated in subtraction result.

CA=O

:

SPECIFICATIONS NOTES

.

Indicates a borrow is generated in subtraction result.
(See Fig. 2)

II

N/A

HITACHI 133
-------------~-------------------

----------------------------

117.

I

SUBTRACTS-DIGIT BCD

IIMCUIIHMCS400 SERIES

II LABEL I

SUBD

DESCRIPTION
(b) Example of SUBD execution is shown in Fig. 1.
If entry arguments are as shown in part Q) of Fig. 1.
Subtraction result is contairLed in MD($03D '" $036) as shown in part
of Fig. 1.

MD ($03D '" $036)
(90123456)

Q)

{

Entry
arguments

MD($04D"'$046)
(12345678)

b31
MD($03D '" $036)
19101112131415

0

bO

I 6 1- Minuend

MD($04D "'$046)
111 2 13141 5 1 6 17 18 1 - Subtrahend

-2

0

Return
fMD ($03D '" $036)
arguments (77777778)

Fig. 1

CA

III

bO
b31
MD($03D "'$036)
Subtraction
17171717171717 ISI- result

Example of SUBD Execution

(2) User Notes
(a) ST flag is set after SUBD execution.
(b) When upper digits are not needed, "0" must be stored in upper
digits as shown in Fig. 3. Otherwise correct subtraction result
cannot be obtained since subtraction is performed with undefined data
in upper digits.

19

I 2 I 3 I 4 I 5 I 6 I 7 I 8 I- Minuend
I 0 11 I 2 I 3 I 4 15 16 I- Subtrahend

12

I2 I2 I2 I 2

11

-2

CA

@]

Fig. 2

CA.

[]

Fig. 3

I-- Subtraction

result

Subtraction Example When Borrow is Generated

I0 I 0 I 0 I 0 I 6 I 7
10 I 0 I 0 I 0 II I 2

-)

134 HITACHI

12 12 12

10

I0

10

I0

I- Minuend
14 I- Subtrahend

15 15
13

15 1 5 12 11

I- Subtraction

result

Subtraction Example When Upper Digits are Not Needed

SUBTRACT 8-DIGIT BCD

IIMCU "HMCS400 SERIES II LABEL II

SURD

II

DESCRIPTION

(c) After SUBD execution, minuend is destroyed since subtraction result is
contained in MD($03D~$036). If minuend needs to be retained after
SUBD execution, it should be saved in memory before execution.
(d) BCD number must be stored in minuend and subtrahend, otherwise correct
subtraction result cannot be obtained.
(3) RAM Allocation
F:E:D:C:B:A:9:8:7:6:S:4:3:2:1:0
02
03
04
05

I

I

I

I

I

I

I

I

I

I

I
I

I

:

I

:

I

I

:

~TI~_t1~Et}i~I
I

I
I
__ {I __ L_J
__ I __ +I __ I
~

I

06

I

V--

I

~_J

I

I

I

I

I

I __

Fig. 4

I

I
I

I
I

I

I

__ l

__ I

I

I

I

I

I

I

I

I

I

I

I

I

I
I
__ +_J
__

I

~_~

I

I
____
_
I

I

Description
bO

fu~A1
MD($03D

~$036)

bO

b3l

!

I

RAM Allocation

b3l

IMSD

I
I

~_~

~--L-_~-~ __ ~ __ ~_l __ ~

RAl'1

Label

-

'

i i ! i ! i
MD ($04D

~

$046)

LSDI

8-digit binary subtrahend
before execution.
8-digit binary subtraction
result after execution.
X and Y addresses are
defined by XSUBT and YSUBT,
respectively.
8-digit binary minuend.
X and Y addresses are
defined by XMINU and
YSUBT, respectively.

(4) Sample Application
Shown below is a sample application using SUBD with address space allocated
as follows.

MD($OAD

~$0A6)

MD($OBD~$OB6)

: Minuend
After execution, subtraction result is contained.
: Subtrahend

HITACHI 135

117 .

I

SUBTRACT 8-DIGIT BCD

II MCU IIHMCS400 SERIES

II

LABEL

I

SUBD

DESCRIPTION
LWI

$0

LXI

$3

----

Example with W=O.

XSPX

WORKl

LXI

$A

LYI

$6

Store 8-digit BCD minuend in entry
argument.

LAMX
LMAIYX
YNEI

$E

BRS

WORKl

LXI

$4

XSPX

WORK2

LXI

$B

LYI

$6

Store 8-digit BCD subtrahend in entry
argument.

LAMX
LMAIYX

II

YNEI

$E

BRS

WORK2

CALL

SUBD

lIn_- Call SUBD.

BRS

WORK3

BRS

BRROW

}----

LXI

$A

TC

WORK3

If borrow is generated in subtraction
result, branch to service routine.

XSPX

WORK4

LXI

$3

LYI

$6

LAMX
LMAIYX

BRROW

136 HITACHI

YNEI

$E

BRS

WORK4

Service routine
in case of borrow

----- Store subtraction result, contained in
return argument, in RAM.

SUBTRACT 8-DIGIT BCD
DESCRIPTION

IIMCUIIHMCS400 SERIES II LABEL

II

SUBD

II

(5) Basic Operation
(a) In HMCS400 series, when subtraction is performed with 2 or more
digits, the same operation sequence is repeated for each digit.
(b) X and Y registers are used as a pointer to minuend and subtrahend.
(c) CA flag is first set. Formula 1 is performed for each digit of
minuend and subtrahend using register indirect addressing mode.
Minuend - Subtrahend - (CA)

~

Accumulator

..... (Formula 1)

CA flag is subtracted in Formula 1 since subtraction result occasionally
generates a borrow.
(d) Subtraction result, calculated in (c), is adjusted to a decimal value
using the decimal adjust instruction (DAS).
(e) Y register is incremented every time (c) and (a) are executed.
(f) Operation loops from (c) to (e) until 8-digit subtraction is completed.

HITACHI 137

117.

I

SUBTRACT 8-DIGIT BCD

II II
MCU

HMCS400 SERIES

II

LABEL

I

FLOWCHART

___ [ Load minuend address into SPX register.
___ [Load subtrahend address into X register.
___ [Load LSD address of minuend and
subtrahend into Y register.

___ [Clear CA flag to perform subtraction.

I~~--,

___ [Load subtrahend digit from LSD.
---[Load X address of minuend.
___ [ Subtract subtrahend and CA from
minuend.
___ [ Adjust subtraction result to decimal.

___ [store decimal-adjusted result
into RAM for minuend.

A->-M
Y+I ->- Y

___ [Load X and Y addresses of subtrahend
for next subtraction.

SPX -+-+X

___ [Test if subtraction of all digits
is completed.
-::>----'

138 HITACHI

SUBD

117.

I

SUBTRACT 8-DIGIT BCD

IIMCUIIHMCS400 SERIES

IILABEL II

SUBD

II

PROGRAM LISTING
ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033

010

0000

SOURCE STATEMENTS
LLEN

132

.

""!II '" *.* "''''''''III'''''''''' ********** "" III '" III III ** *111"'''' >II ** *' "'''''*'''''''' *'" III'" *""*"',.. III"''''' '"
NAME: SUBTRACT B-DIGIT BCD (SUBD)

*************************************lfc******"'*********III'"

.

MD(S030-$036) (MINUEND)
MD(S04D-S046) (SUBTRAHEND)
RETURNS: MDII * *,.. *"" *"" >1<,.. II< "" '"

XSUBT
XMINU
YSUBT
BASUB
SUBD

223
001
224
216
OEF
091
098
OAA
OSI
07E
30S
010

0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
OIOA
OIOB

SUBDI

EQU
EQU
EDU
EQU

$3
S4
S6
SE

ORG
EQU
LXI
XSPX
LXI
LYI
SEC
LAMX
SMe
DAS
LMAIYX
YNEI
BRS
RTN

SOlDO
XSUBT
XMINU
YSUBT

BASUB
SUBDI

MINUEND ADDR(X)
SUBTRAHEND AODR( X)
MINUEND & SUBTRAHEND LSD ADDRCY)
MINUEND & SUBTRAHEND MSD ADDA(Y)+l
ENTRY POINT
LOAD MINUEND ADOR(SPX)
LOAD SUBTRAHEND ADOR(X)
LOAD MINUEND & SUBTRAHEND ADDR(Y)
SET CARRY FLAG
LOAD SUBTRAHEND DATA
M-A-INV(CA)->A
ADJUST RESULT INTO DECIMAl.
STORE RESULT IN MINUEND
TEST IF SUBTRACTION IS COMPLETED
l.OOP UNTIL Y ::: BASUB

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
XSUBT:

Defines X address of minuend.

XMINU:

Defines X address of subtrahend.

YSUBT:

Defines LSD Y address of minuend and subtrahend.

BASUB:

Defines MSD Y address plus 1 of minuend and subtrahend.
(YSUBT + $8; if this is overflow, value should be defined
as $0.)

HITACHI 139

II II

lIS. 16-BIT SQUARE ROOT

I

FUNCTION

MCU

HMCS400 SERIES

II

LABEL

1_

II

Obtains square root of 16-bit binary data in RAM, and store result in
RAM; uses unsigned integers as arguments.

I

ARGUMENTS

11

Contents

Entry

Number to
take square
root of

1 digit 4 bits
No. of
Storage
Location Digits

MD($03A '"
$037)

II CHANGES
IN CPU
REGISTERS AND FLAGS
•x ::

Not affected
Undefined
t : Result
A

4

B

x

x

X

Y

x

x

SPX

SPY

•

x

W
MD($04C,
$04B)

Returns Square root

I

DESCRIPTION

SPECIFICATIONS

•

2

I

CA
x

I

ST
x

I

1 word=10 bits
ROM (Words)
67
RAM (Digits)
12
Stack (Digits)
4
No. of cycles
1492
Reentrant
No
Relocatable
No
Interrupt OK?
Yes

II

(1) Function Details
(a) Argument details
MD($03A"'$037): Holds 16-bit binary number to take square root of.
MD($04C, $04B): Contains S-bit binary square root.
(b) Example of SQRT execution is shown in Fig. l. If entry argument is as
shown in part
of Fig. I, square root is obtained in MD($04C, $04B)
as shown in" part @ of Fig. l.

i7"rTT"T"'<"'-

YSQUR

CA
->-

Y

----- Increment solution.

Y=BASWR

- - --{Cleac "1" 'OUing in ,olucion.

o ->-

M(O)

SQRT7

Load X address in which work area
_____ [ and data to take square root of
are stored.
____ [Decrement counter indicating
number of shifts.
----[Test if shift is completed.

HITACHI 147

118.

I

II MCU II HMCS400 SERIES II LABEL I

16-BIT SQUARE ROOT
FLOWCHART

Shift solution right to adjust
digits.

M+A
Rotate A
1 bit left

A+M

Rotate RAM specified by X and Y
addresses 1 bit left.

YfBASWR

148 HITACHI

SQRT

II

118 . 16-BIT SQUARE ROOT

I

PROGRAM LISTING
ST-NO

OBJECT

ADRS

010

0000

00041
00042
00043
00044
00045

000(16
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
0006B
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
(10081

00082
00083
00084
OOO.~S

00086

LLEN

'" >I<

.**

*"''''

>I< >I< >I< '" >I< >II

132

SQRT

.
.

217
OEC
160 130
217
OEC
160 130
001
21B
OEF
160 130
OEF

218
091
098
OS1

07F
3J 9

06F
32A

218
DEC

091
018
051
07F
322
21B
088
331
OEF
21B
230
018
050
07F
32C
001
OCF

30A
001
21E
OEC
090
OAO
000
07A

337
010
090
O?-ll
050
07F
33D
010

0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
010A
010B
OIOC
010E
010F
0110
0112
0113

>I< '" '" '"

SORTI

SORT2

EQU
EQU
EQU
EQU
EQU
EQU
EOU

$3
$4
SB
S7
SE
SF
SA

ORG
EOU
LXI
XSPX
LXI
LYl
LAI
LMAX
LMAIYX
YNEI
BRS
LBI
LYI
REC
CALL
LYI
REC
CALL

S0100
XSQUA
XBINA
,(SOUR
SO

BASWR
SQRTI
S7
YBINA

>10:

SQRT3

SQRT4

SORTS
SQRT6

0120
012F
SORT?

SORT8

CASOR

DATA TO BE SOUARED MSD ADOR(Y)

ENTRY POINT
LOAD S~UARE ROOT ADDR(X) INTO rII '" '" >II "'>II **** ...... 'I< >Ie '" "'* "'* '" '" '" II< "',.. '" '" *'" "'* *>11 ** "',.. ... ,. . "'''''''''''''''''''

L YI
SEC
CALL

0114
0115
0117
0118
0119
QllA
011B
OJ lC
0110
011E
OIIF
0120
0121
0122
0123
0124
0125
0126
0127
012B
0129
012A
012B
012C

*.

"'* '" lie >Ie >Ie ***** *"' . . *'" *'" '" *' >II '" **** * >I< "'' ' ' ' '>11* '" * **

MD($03A-S037) (DATA TO BE SQUARED)
RETURNS : MD( ~04C. $048) (SOUARE ROOT>

SQRT
224
001
223
21B
230
095
051
07F
305
207

16-BIT SQUARE ROOT (SORT>

ENTRY

XBINA
XSOUA
YSOUR
YBINA
YSLSB
8ASWR
BASQU

00022

00040

I

SOURCE STATEMENTS

NAME :

00019
00020
00021

00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039

LABEL

***"'*"'*****"'*"'''''''********'''****'''****'''*'''*********+:******

00018

00025

II

II

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017

00023
00024

MCU IIHMCS400 SERIES

SQUARE ROOT -) WORK AREA

YSQUR

BASWR
SORB
SORTS
YSOUR

REG(Yl =/ BASWR ?
BRANCH IF REG(Yl =/ BASWR
TEST CARRY
BRANCH IF WORK AREA ( SQUARE ROOT
WORK AREA + SQUARE ROOT -) WORK AREA

LAMX
AMC
LMAIYX
YNEI
BRS
LYI
REM
BRS
SEC
LYl
LAI
AMC
LMAIY
YNEI
BRS

BASWR
SORT4
YSOUR
$0
SORT?

SOUARE ROOT + $1

-)

SQUARE ROOT

YSOUR
$Q

BASWR
SORT6

DECREMENT SHIFT COUNTER

XSPX

DB
8RS
XSPX
LYI
REC
LAM
ROTR
LMAOY
,(NEI
BRS
RTN
LAM
ROTL

CLEAR LSB OF SOUARE ROOT

SORT2

LOOP UNTIL !;HIFT COUNTER
ADJUST DIGITS

SF

YSLSB

BASQU
SORT8
ROT ATE MEMORY

I-BIT LEFT

LMAIY
YNEI
BRS
RTN

8ASWR

CASQR

HITACHI 149

118.

I

l6-BIT SQUARE ROOT
PROGRAM LISTING

IIMCUIIHMCS400 SERIESIILABELII

S(lRT

II

When storing arguments in other RAM locations, change the EQU
operands for the following labels.
XBINA:

Defines X address of number-to take square root of.

XSQUA:

Defines X address of square root.

YSQUR:

Defines LSD Y address of square root.

YBINA:

Defines LSD Y address of number to take square root of.
(YSQUR-$4)

YSLSB:

Defines MSD Y address of square root.

BASWR:

Defines MSD Y address plus 1 of work area. (YSQUR + $4; if this
is overflow, value should be defined as $0.)

BASQU:

Defines MSD Y address of number to take square root of.
(YSQUR-$l)

150 HITACHi

(YSQUR + $3)

19. CONVERT 2-BYTE HEXADECIMAL INTO 5-DIGIT BCD

I

FUNCTION

II II

MCU HMCS400 SERIES

II

LABEL

I_

II

Converts 2-byte hexadecimal data in RAM into 5-digit BCD data and stores
result in RAM; uses unsigned integers as arguments.

I

ARGUMENTS

II

Contents

1 digit= 4 bits
No. of
Storage
Location Digits

CHANGES IN CPU
REGISTERS AND FLAGS

•:

SPECIFICATIONS

Not affected

x : Undefined
~ : Result

Entry

MD($04D'V
$04A)

2-byte
hexadecimal

MD($046 'V
$042)

Returns 5-digit
BCD

4

A

5

I

I

DESCRIPTION

B

x

x

X

Y

x

x

SPX

Spy

•W
•

•

CA
x

1 word=10 bits
ROM (Words)
22
RAM (Digits)
9
Stack (Digits)
0
No. of cycles

I

ST
x

RR'i

I

Reentrant
No
Re1ocatab1e
No
Interrupt OK?
Yes

I

(1) Function Details
(a) Argument details
MD($04D 'V$04A): Holds a 2-byte hexadecimal number to be converted into
BCD number.
MD($046 'V $042): Contains ·a 5-digit BCD number.
(b) Example of HEX execution is shown in Fig. 1.
If argument is as shown in part CD of Fig. 1, a 5-digit BCD number,
in this case "52734", is contained in MD($046 'V$042), as shown in
part @ of Fig. 1.

ISPECIFICATIONS NOTES II

I

_/A

HITACHI 151

19. CONVERT 2-BYTE HEXADECIMAL INTO 5-DIGIT BCD
DESCRIPTION

I

MCU IIHMCS400 SERIES

Entry
argument

HEX

I
MD($04D

CD

/I LABEL II

{ MD ($04D

b1S
'V

$04A)( $CDFE)

I

C

I

D

'V

I

$04A)
F

bO
E

I

1
MD($046 '1,$042)

@

bl9
Return
argument

{ MD ($046 'V $042)
(52734)
Fig. I

I5

bO
2

7

3

4

I

Example of HEX Execution

(2) User Notes
(a) ST flag is set after HEX execution.
(b) When upper digits are not needed, "0" must be stored in upper
digits as shown in Fig. 2. Otherwise correct result cannot be
obtained since conversion is performed with undefined data in upper
digits.

o

o I

o

2

E

F

3

9

1
o
Fig. 2

Conversion Example When Upper Digits are
Not Needed

(c) After HEX execution, a 2-byte hexadecimal number is destroyed.
If a 2-byte hexadecimal number needs to be retained after HEX execution,
it should be saved in memory before execution.

152 HITACHI

19. CONVERT 2-BYTE HEXADECIMAL INTO 5-DIGIT BCDJI MCO IIHMCS400

I

SERIE~ II LABEL II

HEX

I

II

DESCRIPTION

(3) RAM Allocation

06

~
Fig. 3

RAM Allocation

RAM

Label

Description

bl5

bO

IMSD

LSDI
MD($04D

'V

$04A)

2-byte hexadecimal number.
X and Y addresses are
defined "by XHEXD and YHHEX,
respectively.
5-digit decimal number.
X and Y addresses are
defined by XHEXD and YHDEC,
respectively.

HITACHI 153

19. CONVERT 2-BYTE HEXADECIMAL INTO 5-DIGIT BCD I MCU IIHMCS400 SERIES

II LABEL I

HEX

DESCRIPTION
(4) Sample Application
Shown below is a sample application using HEX with address .space allocated
as follows.
MD($OAD·~

MD($OA6

~

LWI

$OAA): 2-byte hexadecimal number
$OA2): 5-digit BCD number

$0

----- Example with W=O.

I
I
I
I

XSPXY
LXI

$4

XSPX
LXI

$A

LYI

$A

LAMX

WORKl

----- Store a 2-byte hexadecimal number. in
entry argument.

LMAIY
YNEI

$E

BRS

WORK1

HE_X_--LJllu

CALL
u..._______

II

LXI

u

-

Call HEX.

$A

XSPX

WORK2

LXI

$4

LYI

$6

LAMX
LMADY

154 HITACHI

YNEI

$1

BRS

WORK2

Store 5-digit BCD number, contained in
return argument, in RAM.

I

19. CONVERT 2-BYTE HEXADECIMAL INTO 5-DIGIT BCD MCU IIHMCS400 SERIES

II LABEL I

HEX

DESCRIPTION
(5) Basic Operation
(a) If ABCD is 4-bit binary number, it is expressed as shown in Formula 1
and Formula 2.
ABCD = A x 2 3 + B x 22 + C X21 + D x 2 0

(Formula 1)

= [ {(A x2) +B} x2 +C jx2 +D

(Formula 2)

III "
Fig. 4

l

y

I

I

4-bit Binary (ABCD)

(b) a = (A X2)+B is first performed, referring to Formula 2.
Second, decimal adjustment is performed. Next, S =(a X2)+C,y=(S x2)+D
is calculated. Each calculation result is decimal adjusted to obtain
final 5-digit binary number.
(c) Calculation of a = (A x 2)+B

(i) Binary number string
loaded into CA flag.

MD($04D~$04A)

is rotated left, and LSB is

(ii) Decimal number string MD($046 ~$042) is shifted left to calculate
(A X2). Contents of CA flag is added to LSB of decimal number
string to calculate ( + B). a = (A x 2)+B is performed by this
process.
(iii) Addition result is decimal adjusted.
(iv) Operation loops from (i) to (iii) 16 times to complete conversion
of a 2-byte hexadecimal number into a 5-digit BCD number.

HITACHI 155

19. CONVERT 2-BYTEHEXADECIMAL INTO 5-DIGIT BCD

I

MCU IIHMCS400 SERIES

II LABEL I

FLOWCHART

-- [

Load X address, where a 2-byte
hexadecimal number and 5-digit BCD
number is stored, into X register.

_-[

Cl~r

RAM for BCD

o~b"r.

__ [ L. oad number of shifts into shift
counter.

Shift a 2-byte hexadecimal number
and load LSB into CA flag.

__ [ Load LSD address, where BCD number is
stored, into Y register.

156 HITACHI

HEX

19. CONVERT 2-BYTE HEXADECIMAL INTO 5-DIGIT BCD

I

MCV

II HMCS400

SERIES

II LABEL II .

HEX

FLOWCHART

___ fDouble BCD number in RAM and add
MSB of hexadecimal number to result.

Adjust result into decimal and store
it in RAM as BCD number.

__ _ lTest if a 5-digit BCD number
conversion is completed.

_ __ [ Decrement shift counter.

__ [ Test if shifts are completed.

HITACHI 157

I

19. CONVERT 2-BYTE HEXADECIMAL INTO 5-DIGIT BCD MCU IIHMCS400 SERIES

I

PROGRAM LISTING
ST-NO

OBJECT

AORS

010

0000

00028
00029
00030

00031
00032
00033

00034
00035
00036
00037
00038
00039
00040
00041

00042

I

SOURCE STATEMENTS

LLEN

132

***************************-** ********* *~:*'" **,j.: '" "'**** >1<'*'*****"' . . . "'******
NAME :

00005

OliO':??

LABEL

I

00001
00002
00003
00004
00006
00001
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026

II

** '" '" >I< '"

>I<

\I< >I< >I<

CONVERT 2-BYTE HEXADCIMAL INTO 5-DIGIT BCD (HEX)

* '" '" '" >I< >I< * >I< >I< *"'''' >I< >I< ** ** >I< * '" >I< ** >I< '" >I< >I< '" '" >I< >I< >I< >I< >I< >I< >I< '" ** >I< >I< '" '" '" >I< '" '" >I< >I< '" '" '" '" >I< '*' >I<
: MO($04D-$04A) (2-BYTE HEXADECIMAL DATA)
: MD(t046-$042) (5-DIGIT 8CD DATA)

ENTRY
RETURNS

*********"'***********************"'****"'****"'********"'**>1<:.1<***",******
XHEXD
YHHEX
YHOEC
8AHEX
BADEC
HEX

224
212
290
077

302
20F
21A
090
OA1
050
07E
307

212
090
OA1
OA6
050
077
30D
GCF
306
010

0100

0101
01Q2
0103
0104
0105
0106
0107
0108

I-IEXl

0110
DIll
0112
0113

0114
0115

ORG
EOU
LXI
LYI
LMIIY
YNEI
SRS

HEx2
HEX3

0109
010A
0108
010e
0100
010E
OIOF

EOU
EOU
EOU
EOU
EQU

HEX.,.

LSI
LYI
LAM
ROTL

$4
$A
$2
i,E
$7

.

HEXADECIMAL AND BCD DATA ADDR(x)
2-6YTE HEXADECIMAL DATA LSD ADor-~\ y}

S-DIGIT BCD D(~·IA LSD ADOR(Y)
2-8'(TE HEXADECIMAL DATA MSD ADDri- A
A+M+CA ->- A
A->-M

Y-l ->- Y

Add carry generated in 2-byte
hexadecimal RAM.

---- [ Decrement pointer to digits of a
5-digit BCD number.

YfBABDE
Test if 5-digit BCD conversion is
completed.

164 HITACHI

BCD

20. CONVERT S-DIGIT BCD INTO 2-BYTE HEXADECIMAL

I

MCll IIHMCS400 SERIES II LABEL

II

BCD

I

II

FLOWCHART

BCD4

II

cp

I""

YBHEX -+ Y
BCDS

l
M-+A

Double 2-byte hexadecimal RAM by
shifting 1 bit left.
Store the doubled number in
work area.

Rotate A
1 bit left
A -+ M

1----------X +-+ SPX
I
A-+M

f---------Y+l -+
Y

SPX +-+ X
Y'I'BABHE

<$=?
BR

Y'I'BABHE

Y=BABHE

r-

$1 .... B
BCD6
YBHEX .... Y
BCD7

M .... A
Rotate A
1 bit left

__ _ Shift data in work area 2 bits left:
multiply doubled data by 4.

A-+M
Y+l ->- Y
Y'I'BABHE

<$:?
BR

Y'l'BABHE

Y=BABHE

B-1 .... B

~

B'I'$F

cbB=$F

HITACHI 165

I

20. CONVERT 5-DIGIT BCD INTO 2-BYTE HEXADECIMAL MCU IIHMCS400 SERIES
FLOWCHART

II LABEL II

I

Add doubled 2-byte hexadecimal
number to 8-times-multiplied
data in work area. Store result
in 2-byte hexadecimal RAM.
As a result, 2-byte hexadecimal
RAM is multiplied by 10.
Y +1 -+ Y
X +-+ SPX

__ _[ Load X address of a 5-digit BCD
number.

166 HITACHI

BCD

-----."-------~

120 •

I

CONVERT 5-DIGIT BCD INTO 2-BYTE HEXADECIMAL" MCU IIHMCS400 SERIES
PROGRAM LISTING

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
0000\7
00048
00049
00050
00051
00052
00053
00054

010

0000

000515
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073

II LABEL II

BCD

II
SOURCE STATEMENTS

·
·
··

LLEN

132

********** ********** "''''*''''''**'''''''''''' II' ** '" '" 1Ie"'* ** *"''''***''' ******* '" ***
*
NAME : CONVERl S~DIGIT BCD INTO 2-BYTE

•
•

HEXADECIMAL (BCD)

·

******************************************************"'****
ENTRY
RETURNS

:MD(S046-S042)(5-DIGIT BCD DATA)
:MD(S04E-$04B)(Z-BYTE HEXADECIMAL DATA)

*****************)1.************************************"''''*'''*

XBBCD
XBWOR
YBHEX
YBDEC
BABHE
BABDE
BCD

225
216
003
224
21B
230
095
051
07F
306
21B
002
DEC
092
01B
050
230
01B
050
07F
310
002
ODF
071
002
31B
DID
21B
090
OAI
095
051
07F
31C
201
218
090
OA1
050
07F
324
OCF
323
001
21B
091
018
051
07F
32D
001
30A

0100
0101
0102
0103
0104
0105
0106
0107
aiDa
0109
010A
010B
OlOC
0100
010E
010F
0110
0111
0112
0113
0114
OilS
0116

BCDI

BCD2

BCD3

0117
011a
0119
011A
OIIB
011e
OliO
011E
OllF
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
012A
0126
012C

0120
012E
012F
0130
0131
0132
0133

EQU
EQU
EQU
EQU
EQU
EQU
ORG
EQU
LXI
LYI
XSPXY
LXI
LYI
LAI
LMAX
LMAIYX
YNEI
BRS
LYI
XSPY
REC
LAMY
AMC
LMAIY
LAI
AMC
LMAIY
YNEI
BRS
XSPY
DY
YNEI

$4
S5
SB
S6
SF
Sl

.

BCD AND HEXADEC I MAL DATA ADDR (X)
WORK AREA ADDR (X)
2-BYTE HEXADECIMAL DATA LSD ADDR(Y>
5-DIGITE BCD DATA MSD ADDR(¥)
2-BYTE HEXADECIMAL DATA MSD ADDR(Y>+1
5-0IGH BCD DATA LSD ADDR(Y)-l

SOlDO

XBWOR
YBDEC

ENTRY POINT
LOAD WORK AREA ADDR( SPX)
LOAD BCD DATA MSO ADDR( SPY>

XBBCD
YBHEX
$0

LOAD BCD &, HEXADECIMAL DATA ADDR(X>
LOAD HEXADECIMAL DATA ADDR(Y)
CLEAR WORK AREA & HEXADECIMAL DATA AREA

BABHE
BCOI
YBHEX

LOAD 2-BYTE HEXADECIMAL DATA ADOR(Y)
A + HEXADECIMAL DATA -) HEXADECIMAL DATA

SO

ADD CARRY

BABHE
BCD3
BABDE

DECREMENT BCD DATA ADDR(¥)
TEST IF BCD CONVERSION IS COMPLETED

XSPY

BCO ..
BeDS

BC06
BCD7

BCD8

BR5
RTN
LYI
LAM
ROTL
LMAX
LMAIYX
YNEI
8RS
LBI
LYl
LAM
ROTL
LMAIY
YNEI
BRS
DB
BRS
XSPX
LYI
LAMX
AMC
LMAIYX
YNEI
BRS
XSPX
BRS

BCD4
YBHEX

HEXADECIMAL DATA

BABHE
BCD5
$1
YBHEX

*'

2

-'>

HEXADECIMAL DATA & WORt-:. AREA

HEXADECIMAL DATI, • 4 -) HEXADECIMAL DATA

BABHE
BC07
BCD6
YBHEX

HEXADECIMAL DATA + WORK AREA -) HEXADECIMAL DATA

BABHE

BCD8
LOAD BCD DATA AODR of Fig. 1, sorted data is
stored from MD($053) in descending order as shown in part (i) of Fig. l.
As number to be sorted is 5 bytes, $3 is loaded into Accumulator as
shown in part Q,) of Fig. 1.

I

SPECIFICATIONS NOTES

II

"RAM" and "No. of cycles" in "SPECIFICATIONS" indicates that required to sort
5 bytes of ascending data in descending order.

HITACHI 169
--~~-

--.~-~.~--

.. -

--------~------------.------~.

?LSORT
I

IIMCUIIHMCS400 SERIESIILABELII

II

DESCRIPTION

No. of bytes to be sorted
($3)

A

m

J

>

Starting address
MD($053)

(j) Entry

arguments
b39

11 : 1
6

:

0

MD($053

IF: F I A
MD($053

:0

y

•

Spy

III ill

bO
8 : 6
$05C)
5-byte data is
sorted in
descending order.
bO
6
6
1
o: 8

'"

I 8

F

0

:

:

I

I

F

I

I

$05C)

'"

Fig. 1

X SPX

[I] [I]

I : I : I
A

!

{'"

@ Result

8

SORT

Example of SORT Execution

(2) User Notes
Number of bytes to be sorted must be loaded as "No. of bytes - $2" into
Accumulator for correct loop processing.
(3) RAM Allocation

~
02
----

03

F: E : D : C : B : A : 9 : 8 : 7 : 6 : 5 r·4 : 3 : 2 : 1 :.0
I

I

I

I

-I--T -

--r--

I

I

I

I

I

I

I

I

I

I

:

I

I

I

,

I

I

:

I

I

I

I

I

I

I

,

I

I

'

,

I

I

:.

:

I

I

-i--r -"1" -;- -r- f- -,--T - .--I---,--+--t-

I'"

~'I"I'II
-04--r--:--T-T--:---:--T--!--:--r----- --r- ~--~-~--"1"----~--~--r----~--~-05
______
+__ __ __
I

I

06

I

,

I

I

L_~

I

I

I

~
I

I

I

I

I

I

I

I

I

I

'

,

I

"

I
I

I
I

I
I

I
I

I
I

•
I

~
Fig. 2
Label
SCNTl

RAM
b3
bO

~
MD($04D)
b3

SCNT2

bO

~

170 HITACHI.

~
MD($04B)

I

I

I

I

I
I

.1
I

I

I
I

I
I

I

--+--~--~-~--+--~-~--~
I
t
I
I
I

RAM Allocation
Description
Counter indicating number of
remaining bytes ·to be sorted.
Counter indicating number of
remaining values to be compared.

MD($04C)
b3
bO
SWORK

I

I

.--~-~--~-~--r--i--!--~-~-----

Work area.

121.
I

SORT

IIMCUIIHMCS400 SERIESIILABELII

SORT

DESCRIPTION

(4) Sample Application
Shown below is a sample application using SORT with address space
allocated as follows.
MD($OAE)
Number to be sorted
MD($OAD, $OAC): Starting address of number to be sorted

LWI

$0

LAMD

$OAD

- - - - - Example with W=O.

LXA
XSPX

Load starting address of number to be
sorted into entry argument.

LXA
LAMD

$OAC

LYA
XSPY
LYA

II

LAMD

$OAE

CALL

SORT

Load number of bytes to be sorted
into entry argument.

II

- - - - - Call SORT.

HITACHI 171

121.

I

II MCU IIHMCS400. SERIES II LABEL II

SORT

SORT

DESCRIPTION
(5) Basic Operation
(a) Fig. 3 shows how 3 units of number are sorted in descending order.
Input data

5

10

Number of bytes: n=3

8

"'----- ......

10

8

. .... G)

105

8

·····0

5
First
compariSOn)
performed
n-l=2 times

,.------- ...
~

10
Second

J [10

Gcomparison
performed
n-2=1 times

10
Fig. 3

5

"'"8

.-------.

•• '" 

00042

00043
00044

..

**** '" "'***** ********** ********* "'*'" i<'" ***'*"'**"'** **"'************* '"
ENTRY
RETURNS

:A
(NO. OF 8YTES TO BE SORTED)
: X. SPX
I<
:NOTHING

**."'*"' . . **********************"''''****''' "'*"' ...... >Ie"'***"'*" ,,"'***"'***** *"' ... '"
SCNT!
seNT2
SWORK

00020

00040
00041

132

*********************************"'*"'**************************

00011
00012
00013
00014
00015
00016
00017
00018
00019

00033

SORT

SOURCE STATEMENTS

00009
( 1)010

00034
00035
00036
00037
00038
00039

LABEL 1\

II

00001
00002
00003
00004
00005
00006
00007
00008

00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032

II

SORT

194 040
194 04C
090
OSC
040
OSC

312
180
001
068
001
281
QE8
180
014
32F
05C
180
28F
180
307
003
050

046

046

04C
0 ... ('

Dlle

oco

00045

05C

00046

003

00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070

058
008
068

SORT2

180 040
28F
194 040
302
010
004
336
05C
OC4
335
315
ODF
030
05C

ORG
EOU
LMAD
LMAO
LAM
IY
L8M
IY
8RS
XMAD

SORn
SORT4

LASPX
XSPX
AI
LXA
XMAD
ALEM
8RS
IY
XMAD

AI
SORTS

XMAD
BHS
X$PXY
LMAIY

0110
011E
011F

XM8

0120

LASPY
LYA

SCNT!
SCNT2

ENTRY POINT
LOAD NO OF 8YTES TO 8E SORTED INTO seNTI
LOAD NO OF BYTES TO BE SORTED INTO SCNT2
LOAD COMPARISON DATA

LOAD SORTING

OAH~

ADDR3b,b,bo

1

1/1

~J.~ ~ ~ ~ ~3~2~:~~

1

2/2

d,d,d,d d,d.d,d,d,do
01 1 1 858483828,80

1

1/2

1

2/2

Long Branch on Status 1

BRL

u

Long Jump Unconditionally

JMPL

u

Subroutine Jump on Status 1

CAL

a

Long Subroutine Jump on Status 1

CALL

u

Table Branch

TBR

P

Return from Subroutine

RTN

0000010000

Return from Interrupt

RTNI

0000010001

o10

1 0 1 P3P,P,Po

2/2

~9 Js ~7 ds ds g4 ~:~:gl'~g

o0

1 0 1 1 P3P,p,po

1/1
1/3
'~I/E

CA RESTORE

ST

1/3

Input/Output Instruction
OPERATION

MNEMONIC

Set Discrete I/O Latch

SED

Set Discrete I/O Latch Direct

SEDD

Reset Discrete I/O Latch

RED

Reset Discrete 1/0 Latch Direct

REDD

Test Discrete 110 Latch

TD

Test Discrete I/O Latch Direct

TDD

Load A from R-Port Register

m

STATUS

WORD

ZE

OPERATION CODE

FUNCTION

0 0 1 1 1 001 0 0

'~D(YI

1/1

1 0 1 1 1 0 m3m2m,mO

'~D(ml

1/1

000 1 1 001 00

O~D(YI

1/1

1

o

o

0 1 1 1 0 000 0

D(YI

1/1

m

1 0 1 0 1 0 m3m2mlmO

D(ml

1/1

LAR

m

1 001 0 1 m3m2m,mO

R(ml~A

1/1

Load B from R-Port Register

LBR

m

1 0 0 1 00 m3m2m,mO

R(ml~B

1/1

Load R-Port Register from A

LRA

m

1 0 1 1 0 1 m3m2m,mO

A~R(ml

1/1

Load R-Port Register from B

LRB

m

1 0 1 1 00 m3m2m,mO

B~R(ml

Pattern Generation

P

P

0 1 1

186 HITACHI

m

0 1 1 0 m3m2m,mO

o

1 1 P3P,P'PO

O~D(ml

1/1

1/1
1/2

Control Instruction
OPERATION

~
CYCLE

MNEMONIC

OPERATION CODE

No Operation

NOP

0000000000

Start Serial

STS

0101001000

1/1

Stand-by Mode

SBY

0101001100

1/1

Stop Mode

STOP

0101001101

1/1

FUNCTION

STATUS

1/1

Op-Code Map
~R8

1

0

R9~

o l l ! 2 j3 4iSi6i7i8i9iAi8jCjDiEiF
o NOf'jXsPx[XSPYf'[,]'1'ML______ lAML _ _ _ loRMl...----1

RT~RTN~

ILEMJ."'----: - IAMCI ___

2

INEM

3

ILEM
____

i14)
ILABI ____ liS

___

1lASP!! ___

4
LSMIXY)
BNEM
5 LMAIYIX)L ___ AYVI
6 NEGAI

0

IEOIIMI

___

7
8

REOI - - - - - I~
YNEI

XM8IXY)
C
D LMADYlXL ___
E Tol ____

1_____

----

F

1

lLXA~

LWI i(2)
L81

i14)

1

LYI

i14)

2

LXI

i14)

3

LAI

i14)

4

L8R

m14)

5

LAR

m14)

6

REDO

m14)

7

LAMR

m14)

8

AI

i14)

9

LMIIY

i14)

A

TOO

m14)

8

ALEI

i14)

C

LR8

m14)

0

LRA

m14)

E

SEOO

m14)

F

XMRA

m14)

D ... t-word/2-cycle
Initruction

D· ..

cOMal ____

ILEMD
lOR I ____

I TC

. ._----

rlMC~L

...

~

LAM~L

i14)
I STS! ___
p14)

CALL

p14)

___ r
__--'" jlMAil

___

___
_____

i14)

JMPL
8RL
SEMD n12)

r''''''~

I 58Y ISTOPL.--'"

p14)

J

REMD n12)
~~
___

LMID

J

TMD n12)

r....!l. ___

i(4)

P

p14)

CAL

a16)

8R

b18)

JOB

i DY
=---:-lRECL---"'-iSEC

j LYAL

SEDI

0

7 I 8 I 9 I A I 8 I C I DiE i F
llMoJ ____ rOAM~

1'<"1 ___
- - r.....1___

IIY I ____

p14)

SVYl"""---___

61

INEMD

ii4)

I LBA I

5 i

~

____

SEM n12) I REM n12) I
TM n12)
LMAIXY)jSMCI ___ -IANM! ___
LAMIXY)
9
IDAAI ____
IDASI _ _
A ROfR/IlTl L _____
I LAY
T8R
BlEMI ___

[3 l4 j

i14)

XMAIXY)

8

Oil 12

V
V

lL
1/

l-word/3-cycle
I nstruction

D··· RAM Direct Addre..
Instruction

D···2-word/2-cycle
Instruction

12-word/2-cycle)

HITACHI 187

HMCS400 SERIES

Section Three

Hardware

Application Notes

¢

44,;;a;

#¢

;;;

4 W # _

d .,

¢4

4 "PD.

4

4·

l4

;

i

'A· ,

4

*'**""';;;

HARDWARE APPLICATION NOTE
• Application Note Guide
• System Application Examples
Zero Cross

3
37

AID Conversion

49

Pulse Output Duty Control

66

Pulse Width Measurement

87

Input Pulse Count

98

Key Matrix (8 x 4)

110

Fluorescent Display Tube Control

129

Stepping Motor Control

145

Use of Commercial Keyboards

187

Clock Synchronous SCI (External Clock)

204

Clock Synchronous SCI (Internal Clock)

217

Liquid Crystal Driver (HD61100A) Control

234

HD61830 (LM200) Graphic Mode

251

Liquid Crystal Module (Cycle Measurement)

287

Low Power Dissipation Mode and watching
Timer Execution Using the HA1835A

310

• Instruction Set

333

PREFACE

The HMCS402C, HMCS404C, and HMCS408C are 4-bit single chip microcomputers all
incorporating the latest CMOS high pressure resistant processes, and are
capable of driving directly flourescent display tubes.

Their performance

characteristics have been substantially upgraded from the previous HMCS40
series in terms of operation speed, functions and program efficiency.

A CPU, clock oscillator, ROM, RAM, I/O timer and serial interface (SCI) are
all outfitted on a single chip enabling the product to perform over a wide
range from small to large scale applications.

These Hardware Notes deal with application examples utilizing the special
functions of the HMCS402C, HMCS404C and HMCS408C.

It has been compiled to

assist system hardware designers by providing application examples with
circuit diagrams, timing charts and program listings.

(The examples have

been written for the HMCS404C but can be applied to the HMCS402C and HMCS408C.)

Application systems examples in these Notes should be tested by actual operation before being put to practical use.

For additional information reference:
-Section 1, HMCS400 Series User's Manual
-Section 2, HMCS400 Series Software Application Notes

LCD Driver Application
12

Liquid Crystal Driver (HD6ll00A) Control

13

HD61830 (LM200) Graphic Mode

14

Liquid Crystal Module (Cycle Measurement)

. . . . . . . . . . . . . . . . . . • . . 234

•...•.•.•......••............••.. 251
287

Low Power Dissipation/Fail Safe Applications
15

Low Power Dissipation Mode and
Watching Timer Execution Using the HA1835A

.......•......•.... 310

INSTRUCTION SET

Symbols and Abbreviations

333

Symbolic Operands Used with Instruction Set Mnemonics

334

Immediate Instruction

335

Register to Register Instruction

335

RAM Address Instruction

335

RAM Register Instruction

336

Arithmetic Instruction

337

Compare Instruction

338

RAM Bit Manipulation Instruction
ROM Address Instruction

••••••••...••....••.•...•......•.. 338

. • . . • • • . . • • • •• • . . • • . • • • • • • • • • . • • . • • . • . . • • .. 338

Input/Output Instruction

338

Control Instruction

339

Op-Code Map

..• . . • • • • . • . • • • . . • • • • • . . •• • • • . • . • . . . . . • . . • . . . . . . • . • • • •. 339

Hitachi Sales Offices .....•..•....••.••....•................•..•......•...... 346

CONTENTS
APPLICATION NOTE GUIDE
1

Explanation of Symbols

3

2

Application Example Configuration

4

3

1st Section (Hardware)

6

4

2nd Section (Software)

10

5

3rd Section (Program Module)

13

6

4th Section (Subroutine)

24

7

5th Section (Program Listing)

28

8

Program Module Execution

31

SYSTEM APPLICATION EXAMPLES
System Application Examples

36

I/O Port Applications
1

Zero Cross

37

2

A/D Conversion

49

Timer Applications
3

Purse Output Duty Control

...........................•....•...

66

4

Pulse Width Measurement •••••••••••••••••••••••••••••••••••••••

87

5

Input Pulse Count

98

6

Key Matrix (8

x 4)

110

7

Fluorescent Display Tube Control

8

Stepping Motor Control

.....•...••.•........•....... 129

145

Interrupt Applications
9

Use of Commercial Keyboards

•••••••••••••••••••••••••••••••••• 187

SCI Applications
10

Clock Synchronous SCI (External Clock)

204

11

Clock Synchronous SCI (Internal Clock)

217

APPLICATION NOTE GUIDE

1.

Explanation of Symbols
Symbols and abbreviations used in these Notes are as follows.
(1)

Operation
a+b

transfer from a to b

a+-rb

exchange a with b

+

addition
subtraction

(2)

(3)

logical product (AND)

x

mUltiplication

V

logical sum (OR)

/

division

G)

exclusive OR

Registers within the MCU
A

Accumulator

B

B register

W

W register

X

X register

SPX

SPX register

Spy

Spy register

ST

Status

Flags within the MCU
CA

(4)

A

Carry

Other Symbols
equivalence symbol
~

not equal to
denotes labels having consecutive addresses

$

denotes hexadecimal digits

>,<,~,~

=

MD ($***)

comparison symbols
denotes 1 digit in RAM area as used in direct addressing
mode ($*** specifies the address location)

MR

($*)

denotes 1 digit in memory registers as used in memory
register addressing mode ($* specifies the address
number)

MSD

denotes the highest digit in RAM

HITACHI
---~-~----.-

-.-

----- -----

3

2.

Application Example Configuration
This chapter explains the configuration of each system application example
following this chapter.

Each application example in APPLICATION NOTES is divided into 5 sections,

1

as shown in figure 1.

r-------------------------~

1st SECTION - - - - 4..~1 HARDWARE DESCRIPTION
(HARDWARE)'
,

I

I

FUNCTION
MICROCOMPUTER OPERATION
PERIPHERAL DEVICES
CIRCUIT DIAGRAM
PIN FUNCTIONS
~D~RE~~~~~ _ _ _ _

L ____________

I

I
,

I
,
~

2nd SECTION--_"IS-;-F;WAR;-;-SCRIPTIO~1-;ROG~ MODUL;---- - - - ,
(SOFTWARE)
I
CONFIGURATION'
,
PROGRAM MODULE
,
,
FUNCTIONS,
I
PROGRAM MODULE PROCESS
,
L ____________ FLO~(M~~ro~am) _ _ _ ~

r-----------------------1
r- FUNCTION
I

3rd SECTION ---·;1 PROGRAM MODULE
(PROGRAM MODULE)
I
DESCRIPTION
,
,

I

I
I
I
,
,

ARGUMENTS
I
r-CHANGES IN CPU
REGISTERS AND FLAGS
I
r- SPECIFICATIONS
,
r-DESCRIPTION----,Function
I
Details
I
r-SPECIFICATIONS rUser Notes
I
NOTES
r-RAM Allocation
,
'--FLOWCHART
r Sample
I
Application I
..... Basic .
,

I
L ____________________ ~=~~~J

,------------------------1

4th SECTION - - + I SUBROUTINE
tFUNCTION
(SUBROUTINE)
I
DESCRIPTION
BASIC OPERATION
I
PROGRAM MODULE USING
I
THIS SUBROUTINE
L ___________ FL~~~ _ _ _ _ _ _ _ _ _

,

I
I

~

~--------------------------,

L MAIN PROGRAM LISTING
I
c==PROGRAM MODULE LISTING
,
L ____________ !~~~~~~~~~ _____ ~

5th SECTION ---+I'" PROGRAM LISTING
(PROGRAM LISTING) ,

Figure 1.

4

HITACHI

Application Example Configuration

(1)

1st Section (Hardware)
Describes functions, circuit diagram, hardware operation for each
hardware application example and making specific use of HMCS400 series
characteristic functions.

(2)

2nd Section (Software)
Describes program module configuration which controls hardware
application example explained in the 1st Section.

Also shows main

program of sample application.

(3)

3rd Section (Program Module)
Describes program modules except main program, presented in the 2nd
Section,. in detail.

Each program module is described in the same

formal so that users can use them independently.

(4)

4th Section (Subroutine)
Describes subroutine used by each program module.

When using program

modules explained in the 3rd Section, refer to these subroutines, if
necessary.

(5)

5th Section (Program Listing)
Provides program listings for sample application explained in the
1st section.

A detailed explanation of all five sections follows.

HITACHI

5

3.

1st Section (Hardware)
3.1

Function
Describes system specifications for the hardware used in a particular
application.
EXample:

14.1.1

Function
Controls LCD module H2570 and displays "CMOS MCU m.lCS400" on the
liquid crystal display.

3.2

Microcomputer Operation
Describes typical functions of the microcomputer used in a particular
application.
Example:

14.1.2

Microcomputer Operation
(1) Controls HD44780 (hereafter abbreviated LCD-II) data bus through
ports R4 and R5.
(2) Controls LCD-II control signals (Signals RS, R/W and E)
through port D.
(3) To control LCD-II data bus and control signals by HMCS404C
software, there are no restrictions in terms of timing.
(4) From HMCS404C display data is transmitted to LCD-II in the form
of ASCII code.

Liquid crystal driver HD44100.and the liquid

crystal display are automatically controlled by LCD-II which is
in turn controlled by the HMCS404C.

6

HITACHI

3.3

Peripheral Devices
Describes typical functions of the peripheral devices used in a
particular application.
Example:

14.1.3

Peripheral Devices
(1) LCD controller driver HD44780 (LCD-II): Controls dot matrix
LCD of LCD module H2570.
(2) LCD driver HD44100: Drives LCD of LCD module H2570.
(3) LCD module H2570:

3.4

Provides a display of 16 characters x 1 row.

Circuit Diagram
Describes the circuit diagram for the hardware example.
Note) All microcomputers described in APPLICATION NOTES use the plastic
DIP type package.
Example:

14.1.4

Circuit Diagram

M(,Tl
+,v

II MC S .. 0 ... C

<:\~~~! ~:

r - - - - - - - - - - - - - - ------1
r;,~-----n~33~----~,~1~
II
JTi
n.~ .
DBn IIDU'H'.O
R~I

nO I LCD _ I

::

I

fA C D

nnE.-----::,o--+----jon2

+OV

lOOkO

Liquid Crystal Module Jl2570

g)

1t4~ a
R 2+

n~1 ~!

152076

~~

Dlh
I)B.

13

Dlh

I

..

~::r2'--'----"..;-+--1 ~~:

r---"4--I ns
r---7HIVW
E

Voo
Vo

Il,
D,

0,

I

IL ___

Fig. 14.1.

IID-U} 00

Vss
~

______________ _

H2570 Control Circuit

HITACHI

7

I/O options can be selected for the HMCS4qO series.
In the circuits shown in this manual, CMOS is selected for standard output
ports, with pull-up MOS is selected for standard input ports, with pulldown MOS is selected for high voltage ports.

3.5

Pin Functions
Describes interface between microcomputer and the external circuit using
a table.
Example:

14.1.5

Pin Functions
Pin functions at the connecting interface of HMCS404C and LCD-II are
shown in Table 14.1.
Table 14.1.

Pin Functions

Pin Name
(HMCS404C)

Input/
Output

Active
level

Function

Pin Name
(LCD-II)

DO

Input!
Output

Low

Selects instruction register

RS

High

Selects data register

Low

Data writing
(Microcomputer -+ LCD-II)
Data reading
(Microcomputer + LCD-II)

R!W

Enable signal

E

High
High

Data line

DBO
DBI

R42
R43

DB4

R50

DB5
DBG

R52

DB?

"Active Level" in the table indicates the following:
High

Logical I

Low

Logical 0
•. Logical I or 0

8

HITACHI

3.6

Hardware Operation
Describes hardware operation for controlling an external circuit using
a timing chart.
Example:

14.1.6

Hardware Operation
Control signals from both the HMCS404C and LCD-II is performed with
the timing shown in Fig. 14.2.

 Vref; continue next output under same conditions.
If low, Vin < Vref; conduct next output after clearing bits set in
ADU (RAM), ADL (RAM) •

(3) Software timer is being executed with due consideration for delay time
of the comparator.

HITACHI 57

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

A/D Conversion

I~

ADCNV

Flowchart:

Initialize ports R7, R8, ADU(RAM),
ADL(RAM)

,.....--...1---.., -----[ 'nitial"e

m~ry

addre""

L-_ _, - _ - - - ' - - - - - [

Set bit 3 of ADU (RAM) to 1

' -_ _-.-_ _...J - - - - - [

Output ADU (RAM) data from port R8

"'-_ _...,.-_ _.... ----- [Execute software timer
D(y)= 1

of port D(Y)

bit 3 of ADU(RAM) to 1

,....-_---I-----[

58 HITACHI

L -_ _

Set bit 2 of ADU(RAM) to 1

L-_ _. -_ _... - - - - - [

Output ADU(RAM) data from port R8

I

Program Module Name:
A/D Conversion

MCU: HMCS402C/
HMCS404C/HMCS408C

I~

ADCNV

Flowchart:

U-_ _.,.-_ _

u ----- [ Execute 10 lls software timer

D(y)= 1

-----[ Test condition of port D (Y)

-==:::;:r-----l-----[

L __

Clear bit 2 of ADU (RAM)

.J-----[
.J -----[

L -_ _.,.-_ _

Set bit 1 of ADU(RAM) to 1

L -_ _.,.-_ _

Output ADU (RAM) data from port R8

u-_ _.,.-_--Ju - - - - - [ Execute 10 lls software timer
D(y)= 1

- - - - - [ Test condition of port D (Y)

..a:::=::::;::r-----l-----[

L __

' - -_ _..,-_ _..J - - - - - [

.J-----[

L -_ _...-_ _

U-_ _...-_ _

Clear Bit 1 of ADU(RAM)

Set bit 0 of ADU (RAM) to 1

Output ADU (RAM) data from port R8

u-----[ Execute 10 lls software timer

D(y)= 1

- - - - - [ Test condition of port D (Y)

.J-----[

L..-_ _, -_ _

Clear bit 0 of ADU (RAM)

'--_ _-.-_ _.... -----[ Output ADU (RAM) data from port R8

HITACHI 59

MCV: HMCS402C/

Program Module Name:

HMCS404C/HMCS408C

A/D Conversion

I

L.bel,

.

Flowchart:

~
~
~

_ _.,-_ _.J - - - - - [

Load $4 in X register

_ _.,-_ _.J - - - - - [

Set 1 is ADL (RAM) bit 3

_ _.,-_ _.J - - - - - [

Output ADL (RAM) data from port R7

L.J..._ _.,-_---'.J

-----[

Execute 10 \ls software timer

D(y)= 1

----- [ Test condition of port D (Y)

,=:==:::::;:r--...J-----[

L __

Clear bit 3 of ADL(RAM)

'--_ _.,-_ _.... - - - - - [ Set bit 2 of ADL(RAM) to 1

'--_ _,..-_ _.... - - - - - [ Output ADL(RAM) data from port R7

'-'-_ _,..-_---Ju ----- [ Execute 10 \ls software timer
D(y)= 1

- - - - - [ Test condition of port D (Y)

-==:::::;:r--...J-----[
~__-;-__...J-----[
~__-;-__. .J -----[

L __

Clear bit 2 of ADL(RAM)

Set bit 1 of ADL(RAM) to 1

Output ADL (RAM) data from port R7

'-'-_ _.-_---'.... -----[ Execute 10 \ls software timer

60 HITACHI

ADCNV

MCU: HMCS402C/
HMCS404C/HMCS408C

Program Module Name:
A/D Conversion

I~
.

ADCNV

Flowchart:

D(y)= 1

----- [ Test condition of port D (Y)

L--===::;:r----I-----[

Clear bit 1 of ADL(RAM)

I.---r----I-----[ Set
I.---r----I ----- [

u...---r----IU-----[

bit 0 of ADL(RAM)

Output ADL (RAM) data from port R7

Execute 10 ].Js software timer

D(y)= 1

- - - - - [ Test condition of port D (Y)

L----:-:~;::::;:r----' -----[

Clear bit 0 of ADL (RAM)

HITACHI 61

2.4

SUBROUTINE DESCRIPTION

Subroutine Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

Software Timer

I

Label'

ADNOP

Function:
Executes 10

~s

software timer by NOP instruction.

Basic Operation:
1. Executes software timer in consideration of delay time for comparator
HA17901.
2. Executes of NOP instruction (2 times) and RTN instruction resulting in
execution of the 10 ~s software timer.

Flowchart:

ADCNV

(ADNOP
ADNOP

I

I..--_11..--.. . .I- - - NOP

I

NOP

I
RTN

62 HITACHI

1

l

10

~s software timer is executed

2.5

PROGRAM LISTING

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
0002B
00029
00030
00031
00032
00033
00034
00035
00036
00037
0003B
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057

010

0000

SOURCE STATEMENTS
LLEN
TITLE

*

****
*ADU

ADL
XHEXD
YHHEX
YHDEC
BAHEX
BADEC

132
AD CONVERSION

RAM ALLOCATION
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$030
S040
S4
SA
S2
SE
S7

********************************

UPPER AID CONVERSION FLAG
LOWER AID CONVERSION FLAG
HEXADECIMAL AND DECIMAL DATA ADDR(X)
2-BYTE HEXADECIMAL DATA ADDR(Y)
5-DIGIT BCD DATA LSD ADDR(Y)
2-8YTE HEXADECIMAL DATA MSD ADDR(Y)+l
5-DIGIT BCD DATA MSD ADDR(Y)+l

********************************************************

150
150
150
150
150
000
000
150

010
010
010
010
010
010

0000
0002
0004
0006
OOOB
OOOA
OOOB
OOOC

*
*
VECTOR ADDRESSES
*
*
**********************************************************
*
ORG
SOOOO
*
JMPL
ADMN
RESET
JMPL
JMPL
JMPL
JMPL
NOP
NOP
JMPL

ADMN
ADMN
ADMN
ADMN

INTO
INTl
TIMER-A
TIMER-B

ADMN

SERIAL

********************************************************

OFO
160
lAO
lAO
190
194
190
194
160
321

022
040
04C
030
04B
040
04A
06F

0010
0011
0013
0015
0017
0019
001B
0010
001F
0021

*
*
MAIN PROGRAMN : ADMN
*
*
*
*
********************************************************
*
ORG
$0010
*
ADMN
LWI
INITIALIZE W REGISTER
SO

CALL
AOCNV
AID CONVERTION
$0.$040
LOAD RESULT INTO HEX ENTRY ARGUMENT
LMID
LMID
SO.$04C
LAMD
ADU
$04B
LMAD
LAMD
ADL
$04A
LMAD
CALL
HEX
CONVERT RESULT INTO BCD DATA
END OF PROGRAM
PEND
BR
PEND
********************************************************

*
*
NAME : ADCNV (AD CONVERT)
*
*
*
*
********************************************************
*
*
NOTHING
ENTRY
*
*
RETURNS : ADU (UPPER AID CONVERSION FLAG)
*
*
ADL
(LOWER
AID
CONVERSION
FLAG)
*
*
**********************************************************

HITACHI 63

0005B
00059
00060
00061
00062
00063
00064
00065
00066
00067
0006B
00069
00070
00071
00072
00073
00074
00075
00076
00077
0007B
00079
OOOBO
OOOBl
000B2
000B3
000B4
000B5
000B6
000B7
OOOBB
000B9
00090
00091
00092
00093
00094
00095
00096
00097
0009B
00099
00100
00101
00102
00103
00104
00105
00106
00107
0010B
00109
00110
00111
00112
00113
00114

230
2DB
207
lAO
lAO
223
210
OB7
090
2DB
160
OEO
333
OBB
OB6
090
2DB
160
OEO
33B
OBA
OBS
090
2DB
160
OEO
343
OB9
084
090
2DB
160
OEO
340
08B
090
2DB
224
OB7
090
207
160
OEO
356
OBB
OB6
090
207
160
OEO
35E
OBA
OBS
090
207
160
OEO

030
040

OB5

OB5

OB5

OB5

OB5

OB5

OB5

64 HITACHI

0022
0023
0024
0025
0027
0029
002A
002B
002C
0020
002E
0030
0031
0032
0033
0034
0035
0036
0038
0039
003A
003B
003C
0030
003E
0040
0041
0042
0043
0044
0045
0046
004B
0049
004A
004B
004C
0040
004E
004F
0050
0051
0053
0054
0055
0056
0057
005B
0059
005B
005C
0050
DOSE
OOSF
0060
0061
0063

ADCNV

ADCNl

ADCN2

ADCN3

ADCN4

ADCN5

ADCN6

LAI
LRA
LRA
LMID
LMID
LXI
LYI
SEM
LAM
LRA
CALL
TO
BR
REM
SEM
LAM
LRA
CALL
TO
BR
REM
SEM
LAM
LRA
CALL
TO
BR
REM
SEM
LAM
LRA
CALL
TO
BR
REM
LAM
LRA
LXI
SEM
LAM
LRA
CALL
TO
BR
REM
SEM
LAM
LRA
CALL
TO
BR
REM
SEM
LAM
LRA
CALL
TO

SO
SB
S7
SO.ADU
SO.ADL
S3
sO
S3
SB
ADNOP
ADCNl
$3
S2
SB
ADNOP
ADCN2
$2
Sl
SB
ADNOP
ADCN3
Sl
SO
S8
ADNOP
ADCN4
SO
SB
S4
$3
S7
ADNOP
ADCN5
$3
S2
S7
ADNOP
ADCN6
S2
$1
$7
ADNOP

INITIALIZE R8 PORT
INITIALIZE R7 PORT
INITIALIZE RAM
DEFINE RAM STARTING ADDRESS
SET BIT 3 OF WORKU(RAM)
OUTPUT WORKU(RAM) DATA
TIME DELAY
COMPARE OUTPUT DATA WITH INPUT VOLTAGE
CLEAR BIT 3
SET BIT 2
OUTPUT DATA
TIME DELAY
COMPARE OUTPUT DATA WITH INPUT VOLTAGE
CLEAR BIT 2
SET BIT 1
OUTPUT DATA
TIME DELAY
COMPARE OUTPUT DATA WITH INPUT VOLTAGE
CLEAR BIT 1
SET BIT 0
OUTPUT DATA
TIME DELAY
COMPARE OUTPUT DATA WITH INPUT VOLTAGE
CLEAR BIT 0
OUTPUT DATA
CONVERT RAM ADDRESS
SET BIT 3
OUTPUT DATA
TIME DELAY
COMPARE OUTPUT DATA WITH INPUT VOLTAGE
CLEAR BIT 3
SET BIT 2
OUTPUT DATA
TIME DELAY
COMPARE OUTPUT DATA WITH INPUT VOLTAGE
CLEAR BIT 2
SET BIT 1
OUTPUT DATA
TIME DELAY
COMPARE OUTPUT DATA WITH INPUT VOLTAGE

00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
0012S
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167

366
OS9
OS4
090
207
160 OS5
OEO
36E
08S
010

0064
0065
0066
0067
0068
0069
006B
006C
0060
006E

ADCN7

ADMNS

BR
REM
SEM
LAM
LRA
CALL
TO
BR
REM
RTN

ADCN7
Sl
SO
S7
ADNOP
ADMNS
SO

CLEAR BIT 1
SET BIT 0
OUTPUT DATA
TIME DELAY
COMPARE OUTPUT DATA WITH INPUT VOLTAGE
CLEAR BIT 0

****************************************************************

*
*
NAME : HEX (CONVERT 2-BYTE HEXADCIMALS
*
*
INTO 5-DIGIT BCD)
*
*
*
*
****************************************************************
*
**
ENTRY : MD(S04D-S04A) (2-BYTE HEXADECIMAL DATA)
*
RETURNS
:
MD(S046-S042)
(5-DIGIT
BCD
DATA)
*
*
*
*
224
212
290
077
371
20F
21A
090
OA1
050
07E
376
212
090
OAl
OA6
050
077
37C
OCF
375
010

006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007C
0070
007E
007F
0080
0081
0082
0083
0084

****************************************************************

HEX

HEX1

HEX2
HEX3

HEX4

LXI
LYI
LMIIY
YNEI
BRS
LBI
LYI
LAM
ROTL
LMAIY
YNEI
BRS
LYI
LAM
ROTL
DAA
LMAIY
YNEI
BRS
DB
BRS
RTN

XHEXD
YHDEC
SO
BADEC
HEX1
SF
YHHEX

BAHEX
HEX3
YHDEC

BADEC
HEX4
HEX2

LOAD HEXADECIMAL ADDR(X)
LOAD BCD DATA ADDR(Y)
CLEAR BCD DATA ADDR(Y)

LOAD SHIFT COUNTER
LOAD HEXADECIMAL DATA AODR(Y)
SHIFT HEXADECIMAL DATA 1 BIT LEFT

LOAD BCD DATA LSD ADDR(Y)
BCD DATA AREA *2+CA-)A
CONVERT INTO BCD DATA ?
LOAD DECIMAL DATA
TEST IF CONVERSION IS COMPLETED
DECREMENT SHIFT COUNTER
LOOP UNTIL SHIFT COUNTER

~

SF

********************************************************

*

**

000
000
010

0085
0086
00B7

NAME : ADNOP (TIME DELAY)

*

*
*

********************************************************

ADNOP

*

NOP
NOP
RTN

END

HITACHI 65

SECTION 3.

3.1

PULSE OUTPUT DUTY CONTROL

HARDWARE DESCRIPTION

3.1.1

Function
Performs duty control of pulses output from the HMCS404C MCU in the
range from 0 - 100%, increasing the duty rate 10% every 0.7 sec.
The output pulses are input to an amplifier and integration circuit,
producing output voltages from 0 V to S V in O.S units.

3.1.2

Microcomputer Operation
Outputs high, low pulses from port D4 using timer B with interrupt
routines.

The high and low period of these pulses are varied with

TMB (Timer Mode B register).

3.1.3

Peripheral Devices
HD140S0B:

Operational Amplifier - Prevents the fluctuation of
analog output voltage caused by the load in user system.

HA17458:

Integration Circuit - Converts digital pulses output from
the MCU to analog.

66 HITACHI

3.1.4

Circuit Diagram

MCU

HMCS404C
(HMCS402C)
HMCS408C

+SV

50 'i'EsT

+SV
+SV
32

VCC

+12V
HA174.58

Fig. 3.1.
3.1.5

Duty Pulse Output

Pin Functions
Pin function for pulse output is shown in Table 3.1.

Table 3.1.

Pin Function

Pin Name
(HMCS404C)

Input/
Output
Output

Active Level
(High or Low)

Function
Output pulse

HITACHI 67

3.1.6

Hardware Operation
qutputs pulses with 0 - 100% duty rate every 0.7s, increasing the
duty rate 10% each time from port D4 on the HMCS404C.

The pulse

output and DA conversion are shown in Fig. 3.2.

Output from Port D4
(Duty 40%)

Output after DA
conversion

~.ov

-------------------------,..----,
I
I

4o.OV

-----------------~
I

,...---'

O.?S

1

'::
Fig. 3.2.

68 HITACHI

~

r-J

/"~)

... "

I

:
I

!
I

/ 1

;-

u

!

Pulse Output and Waveform after DA Conversion

I

I"""
I

3.2

SOFTWARE DESCRIPTION

3.2.1

Program Module Configuration
The program module configuration for pulse output is shown in Fig. 3.3.

DUMN

L2.

MAIN
PROGRAM

I

DUSET

DUOUT

~

OUTPUT
PULSE

SET DUTY

Fig. 3.3.

3.2.2

I
L2.

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 3.2.

Table 3.2.

Program Module Functions

No.

Program Module Name

Label

Function

o

Main Program

DUMN

Outputs pulse with 0 - 100% duty rate

1

Set Duty

DUSET

Sets duty

2

Output Pulse

DUOUT

Outputs pulse from I/O port

HITACHI 69

3.2.3

Program Module Process Flow (Main Program)
The flowchart in Fig. 3.4 is an example of D/A conversion by controlling pulse output, performed by the program modules in Fig. 3.3.
main program in Fig. 3.4 changes pulse output with 0

every 0.7 seconds, increasing the duty rate 10% each time.

Main Program
- - - - - [ Initialize W register
_____ [ Initialize TMB to auto reload,
prescaler .;- 32
-- ---[ Clear timer B interrupt mask

- - - - - [ Enable interrupt

- - - - - [ Load DUSET entry argument
_____ [ Execute DUSET, and initialize pulse
duty

Increment data for next pulse
output

Execute 0.7s software timer
Note) DECNT: 4-digit BCD counter.

CA=O

For details refer to HMCS400
Series Application Note
(Software Edition) on Software
DEC NT

Timer B interrupt routine
----- [ Execute DUOUT and output duty pulse

Fig. 3.4.

70 HITACHI

Program Module Sample Application

The

100% duty rate

3.3

PROGRAM MODULE DESCRIPTION

Proqram Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

Set Duty

Function:

Stores high and low output period corresponding to l-digit
hexadecimal duty stored in entry argument.

Arguments:
Contents
Entry

1 digit = 4 bits
Storage
No. of
Location Digits

Duty

Y

Registers and Flags:
A
x

1

•

High
output
width
Low
output
width
Output
pulse
mode flag

HTIMEU
HTIMEL
(RAM)
LTIMEU
LTIMEL
(RAM)
HOUTF
LOUTF
(RAM)

Specifications:

chan2es in CPU

X

Returns

DUSET

RAM (Digits) :

Y
x

Stack (Digits) : 0

•

•

CA
x

2

Description:
1. Function Details

•
x

t

:

7

Reentrant:

No

Relocatable:

No

Interrupt OK?: No

ST
x

Not Affected
Undefined
Result

b3 Y bO
Y register r-;\l
Entry
{
argument
($A)
~

(1) Argument details
Y: Holds duty as l-digit
hexadecimal number

44

No. of cycles: 30

W

2

10 bits

x

SPY

•

=

B

SPX

2

1 word

ROM (Words) :

HTlMEU:
HTlMEL(RAM)
($64.)

HTlku:
b7HTlMELbO

I LT ~MW: I
6

4

HTIMEU, HTIMEL (RAM): Contains high
LTIMEL
LTlMEU:
Return
output period
LTlMEL(RAM)
argument
(S
96)
LTIMEU, LTIMEL (RAM): Contains low
HOUTF:
output period
LOUTF(RAM)
Contains flag
HOUTF, LOUTF (RAM):
o : 2
($02)
indicat~ng what
Fi . 3.5. Example of Program
output 1S performed;
g
Module DUSET Execution
low consecutive output,
high consecutive output, or
pulse output.
Table 3.3 shows flag functions

I

[specifications Notes:

I
HITACHI 71

Program Module Name:

~:

Set Duty

HMCS402C/
HMCS404C/HMCS408C

I~

DUSET

Description:
Table 3.3.

Flag Functions

HOUTF

LOUTF

Function

1

o
o

Outputs high consecutively from port D4

1

Outputs low consecutively from port D4

o
o

Outputs pulses from port D4

(2) Program module DUSET calls neither program modules nor subroutines.
2. User Notes
Data set in Y must be in the range 0 ~ Y ~ 10 •
Setting data outside of this range will make high and low pulse width
measurement impossible.

72 HITACHI

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

Set Duty

ILOb'"

DUSET

Description:
3. RAM Allocation

FIE:DIC:BIA:9 1 8 1 7 : 6 : 5 1 4 : 3 : Z : 1 : 0

Fig. 3.6.

Label

RAM

•
b3

HOUTF

RAM Allocation

Description

bO

MD($O,$048)

b3

LOUTF

Flag indicating pulse mode from
port D4

bO

~

MD($O, $058)

-b7

HTIMEU:HTIMEL

bO
Stores upper and lower data of
high output width

MD($036.$035)

b7

bO
Stores upper and lower data of
low output width

LTIMEU:LTIMEL
MD($046, $045)

HITACHI 73

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

Set Duty

Label,
[_

DUSET

Description:
4. Sample Application

LAMD

WORK

} ...... Initialize

LAY

II

CALL

DUSET

II

duty

...... Call subroutine DUSET

5. Basic Operation
(1) Y is used as a table index pointer to indicate high or low output pulse
width corresponding to duty.
(2) Test if duty in Y is 0% or 100% and if so, store 0 in HTIMEU, LTIMEU(RAM)
or 10 in HTIMEL, LTIMEL(RAM).
(3) If duty set in Y is other than 0% or 100%, store high and low output
width in HTIMEU, HTIMEL(RAM) and LTIMEU, LTIMEL(RAM), respectively,
by pattern command.

74 HITACHI

r am M
Set Duty
_p_r_o_9__ _ ___o_d_u_l_e__N_arn
__e__: ________________
..

~

~--~

L._M_C_U_:__HMCS404C/HMCS408C
HM
__C_S_4_0_2_C_/____

.IL.L_a_b_e__
DUSET
l_:____________

~

Flowchart:

___ _ [ Test if low consecutive output or
not

~----~----~

___ _ [ Set pulse output mode flag to low
consecutive output

' - - _ - - . ._ _..J

DUSETl
- - - - [ Test if high consecutive output

____ [ Set pulse output mode flag to high
consecutive output

~

_ _1.-_---, - - - {

~....L.-----,

----[

,to.o high width

'to.o low width

HITACHI 75

Program Module Name:

~:

Set Duty

HMCS402C/
HMCS404C/HMCS408C

I~

.

Flowchart:

Store high width outputted from
port 04 by pattern (P) command

Store low width outputted from
port 04 by pattern (P) command

~

____~____~

' - - _ - - , ._ _..1

76 HITACHI

____ [ Set pulse output mode flag to
pulse output

DUSET

Program Module Name:
Output Pulse

Function:

DUOUT

Output duty pulse from port.

Arguments:
contents
Entry

MCU: HMCS402C/
HMCS404C/HMCS408C

High
output
width
Low
output
width
Output
pluse
mode flas

1 digit = 4 bits
Storage
No. of
Location Digits
HTIMEU
HTIMEL
(RAM)
LTIMEU
LTIMEL
(RAM)
HOUTF
LOUTF
(RAM)

Specifications:

Chanses in CPU
Registers and Flags:

1 word

= 10

bits

A

B

ROM (Words) :

•

•

RAM (Digits) :

X

Y

Stack (Digits) :

•

•

No. of cycles:

22

SPX

SPY

•

•

2

2

2

W

35
9

4

Reentrant:

No

Relocatable:

No

Interrupt OK?:

Yes

•

Returns

•
x

:

CA

ST

•

•

Not Affected
Undefined
Result

Description:

HTlMEU:
HTIMELCRAM)

1. Function Details

($64.)

Entry
argument

(1) Arguments details
HTIMEU (RAM) : Store upper data
high pulse width
HTIMEL (RAM) : Store lower data
high pulse width
LTIMEU (RAM) : Store upper data
low pulse width
LTIMEL (RAM) : Store lower data
low pulse width

LTIMEU:
LTlMEL(RAM)
($96)

HOUTF:

of

LOUTF(RAM)
($02 )

of

HTlMEU:
b7HTlMELbO

I

6

:

4.

I

LTIMEU:
LTIMEL
Q

:

HOUTF:
LOUTF

o :

of
of

@

Result {Port D4

Fig. 3.7.

Duty 40%
Example of DUOUT Execution

Specifications Notes:

HITACHI 77

Program Module Name:
Output Pulse

MCU: HMCS402C/
HMCS404C/HMCS408C

ILabel:
DUOUT
1--_ _ _ _ _ _---'

Description:
HOUTF(RAM): Store flag indicating what output is performed; low
LOUTF(RAM) consecutive output, high consecutive output, or pulse output.

Table 3.4.

Flag Functions

HOUTF

LOUTF

Function

1

o
o

Output high consecutively from port D4

1

Output low consecutively from port D4

o
o

Output pulse from port D4

(2) Program module DUOUT calls neither program modules nor subroutines.
2. User Notes
(1) Initialize timer B before use.
(2) IE bit should be initialized for interrupts when using timer B
interrupt.

78 HITACHI

Program Module Name:
Output Pulse

MCU: HMCS402C/
HMCS404C/HMCS40BC

I

Lobol,

DUOUT

Description:
3. RAM Allocation

Fig. 3.B.

Label

RAM

•

b3

HOUTF

RAM Allocation

Function

bO

MD($O.$048)

b3

LOUTF

Flag specifying mode selection for
pulses outputted from port 04

bO

Ea

MD($O. $058)

b7

Store upper and lower data of
high output width

HTIMEU:HTIMEL
MD($036. $035)

Store upper and lower data of low
output width

LTIMEU:LTIMEL
MD($046. $045)

•

b3

HLFLG

bO
Flag specifying high, low or pulse
from port 04

MD($ O. $056)

HITACHI 79

Program Module Name:
Output Pulse

MCU: HMCS402C/
HMCS404C/HMCS40BC

ILabe1'

DUOUT

Description:
4. Sample Application

LMID

$B,$009

REMD

1, $ 00 2

...... Initialize timer mode register B
...... Reset timer B interrupt mask

REMD

0, $ 0 0 2

...... Reset timer B interrupt request flag

SEMD

0, $ 00 0

...... Set interrupt enable flag

LAMD

WORK

LYA

II

CALL

DUSET

} ...... Store duty from user program in
subroutine DUSET entry argument

II

...... Call DUSET and initialize high output
width and low output width in DUOUT
entry argument

5. Basic Operation
Determines the previous output at every timer interrupt, and changes
output port, high to low, low to high.
The width of high or low is
stored in TLRL and TLRU.

80 HITACHI

Program Module Name:
Output Pulse

MCU: HMCS402C/
HMCS404C/HMCS408C

I~

DUOUT

Flowchart:

-- - - [ Clear timer B interrupt request flag

- - - - [ Save register

,----- [ T." i f output puto. i, low 0< high

Store high width pulse in TLRL and
TLRU

____ -[ Te,t i f duty i , O.
LOUTF=l

____ [ Since duty is not 0%, high is outputted
from port D4

- - - - [ Restore register

DUOUTl

HITACHI 81

Program Module Name:
Output Pulse

MCU: HMCS402C/
HMCS404C/HMCS408C

I~

DUOUT

Flowchart:

Store low pulse ,width in TLRL, TLRU

- - - - - - - - { T,.t i f duty," 100'

________ [ Since duty is not 100%, low is
outputted from port D4

82 HI:rACHI

3.4

SUBROUTINES
This application example calls no subroutines.

3.5

PROGRAM LISTING

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
0002B
00029
00030
00031
00032
00033
00034
00035
00036
00037
0003B
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057

010

0000

SOURCE STATEMENTS
LLEN
TITLE

"****
"WORK

HOUTF
LOUTF
HTIMEU
HTIMEL
LTIMEU
LTIMEL
HLFLG
XDCNT
YDCNT
BADCN

"****
"IE
IFTB
IMTB
TMB
TLRL
TLRU

132
DUTY CONTROL OF PULSE OUTPUT

RAM ALLOCATION
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

********************************

S03B
SO.S048
SO.S058
$036
S035
S046
S045
SO.S056
S3
SA
SE

SYMBOL DEFINITIONS
EQU
EQU
EQU
EQU
EQU
EQU

O.SOOO
0.S002
1. S002
S009
SOOA
SOOB

WORK AREA FOR DUTY DATA
UPPER DIGIT OF PULSE STATUS FLAG
LOWER DIGIT OF PULSE STATUS FLAG
UPPER DIGIT OF HIGH PERIOD OF PULSE
LOWER DIGIT OF HIGH PERIOD OF PULSE
UPPER DIGIT OF LOW PERIOD OF PULSE
LOWER DIGIT OF LOW PERIOD OF PULSE
PULSE OUTPUT SELECTION FLAG
BCD COUNTER ADDR(X)
BCD COUNTER LSD ADDR(Y)
BCD COUNTER FOR ADDR(Y)
****************************
INTERRUPT ENABLE FLAG
IF OF TIMER-B
1M OF TIMER-B
TIMER MODE REG B
TIMER LOAD REG LOWER
TIMER LOAD REG UPPER

********************************************************

150
150
150
150
150

010
010
010
010
05C

0000
0002
0004
0006
OOOB

"
"
VECTOR ADDRESSES
"
"
"********************************************************"
"
ORG
SOOOO
"
RESET
JMPL
DUMN
JMPL
JMPL
JMPL
JMPL

DUMN
DUMN
DUMN
DUOUT

INTO
INTl
TIMER-A
TIMER-B

********************************************************

"

"
"

MAIN PROGRAMN : DUMN
"
"********************************************************"

OFO
lAB
1B9
1B4
190
ODB
160
05C
07B
320
210

009
002
000
038
030

0010
0011
0013
0015
0017
0019
001A
001C
0010
001E
001F

"
"
DUMN
OUMN1

ORG

SOO10

LWI
LMID
REMD
SEMO
LAMD
LYA
CALL
IY
YNEI
BRS
LYI

SO
SB.TMB
IMTB
IE
WORK
DUSET
11
DUMN2
SO

INITIALIZE W REGISTER
INITIALIZE PRESCALER 1/32
ENABLE INTERRUPTS
LOAD ENTRY ARGUMENT OF OUSET
DEFINE DUTY RATE OF PULSE
DUTY+10X -) ENTRY ARGUMENT
DUTY =100" ?
STORE Ox DUTY

HITACHI 83

00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114

OAF
194
lAO
lAO
lAO
lAO
160
06F
317
328

038
03A
038
03C
03D
081

0020
0021
0023
0025
0027
0029
0028
002D
002E
002F

DUMN2

OUMN3

LAY
LMAD
LMID
LMID
LMIO
LMID
CALL
TC
BRS
BRS

WORK
$0.$03A
$0.$038
$0.$03C
$0.$030
DECNT

EXECUTE 0.7MS SOFTWARE TIMER

DUMN1
DUMN3

********************************************************

'"
'"

070
338
188
184
170
07A
347
184
188
1A8
1A3
lA8
1A3
010
OAF
20F
180
194
048
194
OAF
20F
1B1
194
048
194
188
188
346

048
058
03E
048
058
036
035
046
045

035
036

045
046
048
058

84 HITACHI

0030
0031
0032
0034
0036
0038
0039
003A
003C
003E
0040
0042
0044
0046
0047
0048
0049
004A
004C
004D
004F
0050
0051
0052
0054
0055
0057
0059
005B

'"
NAME : DUSET (SET DUTY)
'"
'"
'********************************************************
"
'"
'"
ENTRY
Y REGISTER (DUTY DATA)
'"
'"
RETRUNS : HTIMEU (UPPER HIGH PERIOD OF PULSE)
'"
'"
HTIMEL (LOWER HIGH PERIOD OF PULSE)
'"
'"
LTIMEU (UPPER LOW PERIOD OF PULSE)
'"
''""
LTIMEL (LOWER LOW PERIOD OF PULSE)
'"
HoUTF (UPPER PULSE STATUS FLAG)
''""
'"
LoUTF (LOWER PULSE STATUS FLAG)
'"
'********************************************************
"
'"
DUSET

DUSETl

DUSET2

DUSET3
DUSET4

YNEI
8RS
REMD
SEMD
BRL
YNEI
BRS
SEMD
REMD
LMID
LMID
LMID
LMID
RTN
LAY
L8I
P
LMAD
LAB
LMAD
LAY
LBI
P
LMAO
LAB
LMAD
REMD
REMD
8RS

$0
DUSETl
HoUTF
LoUTF
DUSET2
10
DUSET4
HoUTF
LoUTF
8. HTIMEU
3. HTIMEL
8. LTIMEU
3. LTIMEL
$F
$0
HTIMEL
HTIMEU

TEST IF DUTY =Or. ?

DEFINE FLAG TO OUTPUT LOW
TEST IF DUTY =10oX ?
DEFINE FLAG TO OUTPUT HIGH
SET SOX DUTY RATE

SET HIGH PERIOD OF PULSE
PATTERN

SET LOW PERIOD OF PULSE

$F
$1
LTIMEL

PATTERN

LTIMEU
HOUTF
LOUTF
DUSET3

DEFINE FLAG TO OUTPUT PULSE

********************************************************

'"

'"

NAME : DUOUT (OUTPUT PULSE)

'"
'"

00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171

*
*
*
*
ENTRY : HTIMEU (UPPER HIGH PERIOO OF PULSE)
*
*
HTIMEL
(LOWER
HIGH
PERIOO
OF
PULSE)
*
*
LTIMEU (UPPER LOW PERIOO OF PULSE)
*
*
LTIMEL (LOWER LOW PERIOO OF PULSE)
*
*
HOUTF (UPPER PULSE STATUS FLAG)
*
*
LOUTF (LOWER PULSE STATUS FLAG)
*
: NOTHING
RETURNS
*
*
*
*
********************************************************
********************************************************

188
2FF
18C
372
190
194
190
194
18C
370
2E4
184
2FF
011
190
194
190
194
18C
370
264
188
370

002
056
035
OOA
036
OOB
058
056
045
OOA
046
OOB
048
056

005C
005E
005F
0061
0062
0064
0066
0068
006A
006C
0060
006E
0070
0071
0072
0074
0076
0078
007A
007C
0070
007E
0080

OUOUT

OUOUTl
OUOUT2

REMO
XMRA
TMO
8RS
LAMO
LMAO
LAMO
LMAO
TMO
BRS
SEOO
SEMO
XMRA
RTNI
LAMO
LMAO
LAMO
LMAO
THO
BRS
REOO
REMO
BRS

IFT8
$F
HLFLG
OUOUT2
HTIMEL
TLRL
HTIMEU
TLRU
LOUTF
OUOUTl
$4
HLFLG
$F

CLEAR INTERRUPT REQUEST 8IT
SAVE X REGISTER
HIGH OR LOW OUTPUT ?
BRANCH IF LOW OUTPUT
STORE HIGH PERIOO OF PULSE

LTIMEL
TLRL
LTIMEU
TLRU
HOUTF
OUOUTl
$4
HLFLG
OUOUTl

STORE LOW PERI 00 OF PULSE

OUTY =0" ?
OUTPUT HIGH PULSE
RESTORE X REGISTER

OUTY =100" ?
OUTPUT LOW PULSE

********************************************************

*
*
NAME : OECNT (4-0IGIT BCO COUNTER)
*
*
*
********************************************************
*

*

*

ENTRY
NOTHING
*
*
RETURNS : HO($030-$03A)(4-0IGIT BCO COUNTER)
*
*
CA FLAG (CA=O;TRUE.CA=l;OVERFLOW)
**********************************************************

223
21A
OEF
230
018
OA6
050
07E
384
010

0081
0082
0083
0084
0085
0086
0087
0088
0089
008A

LOAO ADOR(X)
LXI
XDCNT
LOAO LSO AOOR(Y)
LYI
YOCNT
SET CARRY FLAG
SEC
$0
CLEAR A
OECNTl
LAI
INCREMENT BCO COUNTER
AMC
CONVERT INTO BCO DATA
OAA
STORE BCD COUNTER ANO 8CO OATA
LHAIY
REG(Y) = / BCO COUNTER ?
YNEI
8ADCN
LOOP UNTIL REG(Y) = BCD COUNTER
OECNTl
BRS
RTN
********************************************************
OECNT

HITACHI 85

00172
00173
00174
00175
00176
00177
00178
00179
00180
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
00198
00199
00200
00201

1E7
1CE
185
19C
183
16A
151
138
llF

00F1
00F2
00F3
00F4
00F5
00F6
00F7
00F8
00F9

"'
*
DATA TA8LE
*
"'
**********************************************************
*
ORG
SOFl
*
DC
SlE7
10
HIGH PERIOD OF PULSE
DC
DC
DC
DC
DC
DC
DC
DC

*
llF
138
151
16A
183
19C
1B5
1CE
1E7

86 HITACHI

01F1
01F2
01F3
01F4
01F5
01F6
01F7
01FB
01F9

*

*

SlCE
S185
S19C
S183
S16A
S151
S138
SllF

ORG

SlF1

DC
DC
DC
DC
DC
DC
DC
DC
DC

SllF
S138
S151
S16A
S183
S19C
SlB5
SlCE
SlE7

ENO

20
30
40
50
60
70
80
90

90
80
70
60
50
40
30
20
10

LOW PERIOD OF PULSE

SECTION 4.

4.1

PULSE WIDTH MEASUREMENT

HARDWARE DESCRIPTION

4.1.1

Function
Measures the input cycle of a pulse to determine pulse width in the
range from 100

~s

to 256

~s

stores result as a binary coded decimal

(BCD) number.

4.1.2

Microcomputer Operation
The HMCS404C uses the eight-bit auto reload type timer and event
counter to fetch values in the timer and event counter on the falling
and rising edges of the INTl pin, using the difference between these
values to measure the pulse width.

4.1.3

Circuit Diagram

Meu
+5V

HMCS404C
HMCS402C
( HMCS408C)

+5V
+5V
32

Vee

Pulse input

JL..JL
23

R33

Fig. 4.1.

/1 NT 1 1 - - - - - - - - - - 0

Pulse Width Measurement Circuit

HITACHI 87

4.1.4

Pin Functions
Pin functions for pulse width measurement are shown in Table 4.1.

4.1.5

Table 4.1.

Pin Functions

Pin Name
(HMCS404C)

Input/
Output

Active level
(High or Low)

Input

Low

Function
Detects falling edge of input
signal and executes interrupt
routine

Hardware Operation
Fig. 4.2 shows pulse width measurement.
2

~s,

E clock cycle is 1

~s.

Since system clock cycle is

In Fig. 4.2, pulse width W is 6

TCB pulse count value = N
Timer/event
counter

INTl pin

Cycle W

Fig. 4.2.

88 HITACHI

Measure Pulse Width

N=3

~s.

4.2

SOFTWARE DESCRIPTION

4.2.1

Program Module Configuration
The program module configuration for pulse width measurement and BCD
conversion is shown in Fig. 4.3.

PWMN

~
Main
Program

PWCNT

I

1
HEX

l2.

4.2.2

12.

Convert
Hexadecimals
into BCD

Pulse Width
Measurement

Fig. 4.3.

I

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 4.2.

Table 4.2.
No.

Program Module Functions

Program Module Name

Label

Function

o

Main Program

PWMN

Measures pulse width as a BCD number

1

Measure Pulse Width

PWCNT

Obtains pulse width as a 2-byte
hexadecimal number

2

Convert Hexadecimals
into BCD

HEX

Converts 2-byte hexadecimal number
into BCD number. Refer to HEX in
HMCS400 Series Application Note
(Software Edition) for details

HITACHI 89

4.2.3

Program Module Process Flow (Main Program)
The flowchart in Fig. 4.4 is an example of pulse width measurement
performed by the program module in Fig. 4.3.

Main Program

- - - - { Initialize W register

_____ [ Select prescaler divide ratio of timer
mode register as"'" 2
- - - - - [ Select INTl input pin by port mode register

- - - - - [Clear INTl

interrupt mask

- - - - - [ Clear INTl interrupt request flag

- - - - - [ Set interrupt enable flag
PWMNl .--_ _"'-_ _.,

- -- - { n,., "P""

PWDTHU
-+MD($04B)

PWDTHL
-+MD($04A)

di,'<,

00'

""d io ""

Store upper digits of 2-byte hexadecimal
- - - - - [ cycle value in input argument HEXD (RAM)
of module HEX

Store lower digits of 2-byte hexadecimal
- - - - -[ cycle value in input argument HEXD (RAM)
of module HEX

r

Call subroutine HEX and convert pulse
- - - - - width into BCD number.
See subroutine HEX in HMCS400 Series
Application Note (Software Edition)
for details

INTl interrupt routine

_____ [Obtain pulse cycle as a 2-byte hexadecimal
number

Fig. 4.4.

90 HITACHI

Program Module Flowchart

4.3

PROGRAM MODULE DESCRIPTION

Program Module Name: MEASURE PULSE
WIDTH

MCU: HMCS402C/
HMCS404C/HMCS408C

PWCNT

Function:
Obtains pulse cycle as a 2-byte hexadecimal number, and stores result in
PWDTHU, PWDTHL (RAM).

Arguments:
Contents

1 digit = 4 bits
Storage
No. of
Location Digits

Specifications:

Changes in CPU
Resisters and Flags:
B

ROM (Words) :

•

•

RAM (Digits) :

X

Y

Stack (Digits) :

•

•

No. of cycles:

36

SPX

SPY

Reentrant:

No

•

•

Relocatable:

No

Interrupt OK?:

No

W
Returns

PWDTHU
(RAM)

1

Period
(lower)

PWDTHL
(RAM)

1

x

:

CA

ST

•

•

0

Not Affected
Undefined
Result

Description:

160.us

(1) Argument details

6

•

•

1. Function Details

34

A
Entry

Period
(upper)

1 word = 10 bits

14

CD

PWDTHU, PWDTHL
(RAM) : Contains pulse width
as a 2-byte hexadecimal number.

o

Input

-I

PU1'"{~
~

Measurement
resul t
Fig. 4.5.

PWDTHU :
{ PWDTHL
(RAM)

b7 PWDTHU: bO

I

:

PWDTHL

2 -L_---J
L.._

($058, $057)

Example of PWCNT Execution

Notes:

HITACHI 91

Program Module Name: MEASURE PULSE
WIDTH

MCU: HMCS402C/
HMCS404C/HMCS408C

ILab'"

PWCNT

Description:
(2)

Example of PWCNT execution is shown in Fig. 4.5.
If pulse, whose high
period of pulse is 160 )ls, is input as shown in part CD of Fig. 4.5,
measurement result is stored in PWDTHU, PWDTHL(RAM) as a hexadecimal
number.

(3)

PWCNT calls neither program modules nor subroutines.

2. User Notes
(1)

Only period of pulses between 100 and 256 )ls can be correctly measured.

(2)

Bit IE is set to enable INTl interrupt.

(3)

Since a 2 jJs system clock is employed, an oscillator frequency of 4 MHz
is used to execute measurement of pulse cycles.

3. RAM Allocation

o2

I
I

t

I

I
I

I
I

I
I

1

!

;

I
I

I

I

I

I

I

I

I

-~-3-- --:--:--t--:--:---i-.--i---:--~--:-

---o4

--r--r--~--:---j--~-1

I

I

I

I

I

I

I

I

I

-----

o6

I

Fig. 4.6.
Label

RAM

b7

I

I

I

I

I

I

I

I

I

I

I

I

1_

--i--:--+--~--,--i--

I

--~-~--~--~--~--~--

~

I

--t--f---~--~--~--:--

I I i

---- --t--f---{--i--t--t-o5

I

1

-t--t--

I

i
I

I

I

I
I

I

--~--:--~--i--t--t-I

t-.~

J..

I

-L

L

RAM Allocation
Description

bO
Stores timer/event counter value
at the second falling edge

TCBNWU:TCBNWL
MD($038, $037)

b7

TCBODU:TCBODL

bO

~

Stores timer/event counter value
at the first falling edge

MD($048, $047)

b7

bO

PWDTHU: PWDTHL
I111111111111111111111111
MD($058, $057)

92 HITACHI

Stores difference (cycle) in
timer/event counter at the first
and second falling edges

Pro2ram Module Name: MEASURE PULSE
WIDTH

~:

HMCS402C/
HMCS404C/HMCS408C

I~

PWCNT

Description:
4. Sample Application

iNTi,

LMID

$8. PMR

Initialize port mode register as
input pin

REMD

IF 1

Reset external interrupt request flag

5. Basic Operation
Reads the timer/event counter value when the external interrupt request
flag is set on the INTl pin input falling edge.
In the same manner, read the timer/event counter value at the next falling
edge.
Pulse cycle is measured by calculating the difference between the two
values.

HITACHI 93

Program Module Name: MEASURE PULSE
WIDTH

MCU: HMCS402C/
HMCS404C/HMCS408C

1Labe',

PWCNT

Flowchart:

(

PWCNT

I

PWCNT

O->IFI

--- ----{ Clear external interrupt request flag

I
A-MR(F)

-------[ Save register

I
TCBU->
TCBNWU
_______

I

Read timer/event counter value and
set in TCBNWU (RAM), TCBNWL (RAM)

TCBL->
TCBNWL

I
1

-4

CA

------{ Set CA

I
TCBNWLTCBODL-CA
-> PWDTHL

Obtain pulse cycle by calculating the
difference in TCB values between former
and latter interrupts

I
TCBNWUTCBOD U-CA
-> PWDTHU

I
TCBNWU
-> TCBODU

I

- - - ----

Store TCBNWU (RAM), TCBNWL (RAM) to
TCBODU (RAM), TCBODL (RAM) to perform
measurement of next cycle

TCBNWL
-> TCBODL

I
MR(F)-A

I

(

94 HITACHI

RTNI

-- ------[ Restore register

4.4

SUBROUTINE DESCRIPTION
This application example calls no subroutines.

4.5

PROGRAM LISTING

ST-NO

06JECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00006
00009
00010
00011
00012
00013
00014
00015
00016
00017
00016
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057

lE7

0000

SOURCE STATEMENTS
LLEN
TITLE

132
PULSE WIDTH MEASUREMENT

*
**** RAM ALLOCATION ****************************************
*PWDTHU EQU
UPPER DIGIT OF PULSE WIDTH
$058

PWoTHL
TCBNWU
TCBNWL
TCBOoU
TC60DL
XHEXD
YHHEX
YHDEC
6AHEX
6ADEC

*
****
*TM6

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$057
$038
$037
$048
$047
$4
$A
$2
$E
$7

SYMBOL

DEFINITIONS

LOWER DIGIT OF PULSE WIDTH
TIMER CNTR B NEW UPPER
TIMER CNTR B NEW LOWER
TIMER CNTR B OLD UPPER
TIMER CNTR 6 OLD LOWER
HEXADECIMAL AND BCD DATA ADDR(X)
2-6YTE HEXADECIMAL DATA LSD ADoR(Y)
5-DIGIT BCD DATA LSD ADDR(Y)
2-6YTE HEXADECIMAL DATA MSD ADDR(Y)+1
5-DIG1T BCD DATA MSD ADDR(Y)+1

***********************************

EQU
TIMER MODE REGISTER B
$009
PORT MODE REGISTER
PMR
EQU
$004
EQU
$1.$001
INTERRUPT MODE FLAG
IMI
INTERRUPT REQUEST FLAG
EQU
$0.$001
IFI
EQU
INTERRUPT ENABLE FLAG
IE
$0.$000
TCBU
EQU
$OOB
TIMER CNTR 6 UPPER
EQU
TIMER CNTR BLOWER
TC6L
$OOA
****************************************************************

*
*
VECTOR ADDRESSES
*
*
******************************************************************
150
150
150
150
150

010
010
02A
010
010

0000
0002
0004
0006
0008

*

ORG

$0000

JMPL
JMPL
JMPL
JMPL
JMPL

PWMN
PWMN
PWCNT
PWMN
PWMN

RESET
INTO
INTl
TIMER-A
TIMER-6

****************************************************************

*
*
MAIN PROGRAM : PWMN
*
*
******************************************************************
OFO
lA6
lA8
189
188
184
lAO
lAO
190
194

009
004
001
001
000
040
04C
058
04B

0010
0011
0013
0015
0017
0019
0016
OOlD
001F
0021

*
*PWMN

PWMNI

ORG

$0010

LWI
LMID
LMID
REMD
REMD
SEMD
LMID
LMID
LAMD
LMAD

$0
$6.TMB
$8.PMR
IMI
IFI
IE
$0.$040
$0.$04C
PWDTHU
$04B

INITIALIZE W REGISTER
SELECT PRESCALER AS 1/2
SELECT INTl PIN
ENA8LE INTI INTERRUPT
ENABLE INTERRUPT
LOAD ENTRY ARGUMENT

HITACHI 95

00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
000B5
00086
00087
0008B
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
0010B
00109
00110
00111
00112
00113
00114

190 057
194 04A
160 04C
31B

188
2FF
190
194
190
194
OEF
190
19B
194
190
198
194
190
194
190
194
2FF
011

001
008
038
OOA
037
047
037
057
04B
038
058
038
048
037
047

224
212
290
077
34E
20F
21A
090
OA1
050
07E
353
212

96 HITACHI

0023
0025
0027
0029

002A
002C
0020
002F
0031
0033
0035
0036
0038
003A
003C
003E
0040
0042
0044
0046
0048
004A
0048

004C
0040
004E
004F
0050
0051
0052
0053
0054
0055
0056
0057
0058

lAMD
PWDTHl
lMAD
S04A
CAll
HEX
CONVERT HEX DATA INTO 8CD DATA
BRS
PWMN1
****************************************************************

*
*
NAME : PWCNT (MEASURE PULSE WIDTH)
*
*
******************************************************************
*
*
ENTRY
NOTHING
*
*
RETURNS : PWDTHU (UPPER PULSE WIDTH)
*
*
PWDTHl (lOWER PULSE WIDTH)
*
*
******************************************************************
PWCNT

REMD
IF1
CLEAR INTERRUPT REQUEST FLAG
XMRA
SF
SAVE REGISTER
lAMD
TCBU
lMAD
TC8NWU
STORE TIMER/EVENT COUNTER
lAMD
TCBl
lMAD
TC8NWl
SEC
SET CARRY FLAG
lAMD
TCBODl
CALCULATE PULSE WIDTH
SMCD
TCBNWl
lMAD
PWDTHl
lAMD
TC80DU
SMCD
TC8NWU
lMAD
PWDTHU
lAMD
TCBNWU
TCBNEW-)TCBOlD
lMAD
TCBODU
lAMD
TCBNWL
lMAD
TCBODl
XMRA
SF
RESTORE REGISTER
RTNI
********************************************************

*
*
NAME : HEX (CONVERT 2-BYTE HEXADCIMAlS INTO
*
*
5-DIGIT BCD)
*********************************************************
*
*
*
ENTRY : MD(S04D-S04A) (2-BYTE HEXADECIMAlS)
*
*
RETURNS
:
MD($046~S042) (5-DIGIT BCD)
*
*
**********************************************************
HEX

HEX1

HEX2
HEX3

LXI
LVI
lMIIY
YNEI
BRS
lBI
lYI
lAM
ROTl
lMAIY
YNEI
BRS
LYI

XHEXD
YHDEC
SO
BADEC
HEX1
SF
YHHEX

BAHEX
HEX3
YHDEC

lOAD HEXADECIMAL ADDR(X)
lOAD 8CD DATA ADDR(Y)
CLEAR BCD DATA ADDR(Y)

lOAD SHIFT COUNTER
lOAD HEXADECIMAL DATA ADDR(Y)
SHIFT HEXADECIMAL DATA 1-BIT lEFT

lOAD BCD DATA LSD ADDR(Y)

00115
00116
00117
OOlla
00119
00120
00121
00122
00123
00124
00125

090
OAl
OA6
050
077
359
OCF
352
010

0059
005A
005B
005C
0050
005E
005F
0060
0061

HEX4

*

lAM
ROTl
DAA
lMAIY
YNEI
BRS
DB
BRS
RTN

BCD DATA AREA *2+CA-)A
BADEC
HEX4
HEX2

CONVERT INTO BCD DATA ?
lOAD DECIMAL DATA
TEST IF CONVERSION IS COMPLETED
DECREMENT SHIFT COUNTER
lOOP UNTIL SHIFT COUNTER

a

SF

END

HITACHI 97

SECTION 5.

5.1

INPUT PULSE COUNT

HARDWARE DESCRIPTION

5.1.1

Function
Counts input pulses up to 255 pulses; the count value is returned as
a Hexadecimal number.

5.1.2. Microcomputer Operation
Inputs pulses through the INTl Pin of the HMCS404C and performs
pulse count by counting up timer B timer/event counter (hereinafter,
TCB) .

5.1.3

Circuit Diagram
Input pulse measurement circuit is shown in Fig. 5.1.

MCV

+5V

HMC S 4. 04. C
( HMCS4.02C)
HMCS408C
50 TEST

+5V
+5V
32

Vce

Pulse input
_ _ 23
R33/INTI~

Fig. 5.1.

98 HITACHI

JLJL

Input Pulse Measurement Circuit

5.1.4

Pin Functions
Pin functions of HMCS404C for counting pulses is shown in Table 5.1.
Table 5.1.
Pin Name
(HMCS404C)

5.1.5

Pin Functions
Input/
Output

Active Level
(High or LOw)

Function

Input

Low

Inputs pulse event

Hardware Operation
Fig. 5.2.shows input pulse count using INTl pin of the HMCS404C.
To set start/end timing for counting input pulses, the procedure
below must be performed in the main program.

CD
GD

Set flag in STRTF(RAM)
Clear flag is STRTF(RAM)

Pulse number N

~:':ePin

input

I I I I I'

Pulse count start

Pulse count end

Fig. 5.2.

Input Pulse Count

HITACHI 99

5.2

SOFTWARE DESCRIPTION

5.2.1

Program Module Configuration
The program module configuration for input pulse count is shown in
Fig. 5.3.

PLSMN
Main
Program

PLSCNT

Fig. 5.3.

5.2.2

I

J

Count
Pulses

~

HEX

l2:..

1

l2..

Convert
Hexadecimals
into BCD

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 5.2.
Table' 5.2.

Program Module Functions

No.

Program Module Name

Label

Function

o

Main Program

PLSMN

Counts input pulses as a BCD numbers

1

Count Pulses

PLSCNT

Obtains input pulse number by TCB
value

2

Convert Hexadecimals HEX
into BCD

100 HITACHI

Converts I-byte hexadecimal number
into BCD number. Refer to HEX in
HMCS400 Series Application Note
(Software Edition) for details

5.2.3

Program Module Process Flow (Main Program)
The flowchart in Fig. 5.4 is an example of counting input pulses,
performed by the program module in Fig. 5.3.

L------r---...J-----{ Initialize W register
'--_ _-.-_ _--' -----[ Select R33/INTl as INTl
L-_ _- ,_ _ _...J - - - - - [

Store start Flag in STRTF (RAM)

u...-----r---..... - - - - - [ Execute PLSCNT to count input pulse

Execute 200ms software timer

Fig. 5.4.

Program Module Flowchart

HITACHI 101

-J-----J[ Clear start Flag for

L -____- .____

U-____- .____

~-----[ Execute

input pulse count

PLSCNT and stop counting pulse

Load input pulse count result into entry
argument HEXDA(RAM) of subroutine HEX

r-----~----_,

_____ r

Load $0 into entry argument HEXDA3 I
~ HEXDA4(RAM) which do not use HEX

....

'-----.,.--

_____ [ Call HEX to convert hexadecimal count
result into a BCD number.
Refer to HEX in HMCS400 Series Application
Note (Software Edition) for details

Fig. 5.4.

102 HITACHI

Program Module Flowchart (cont)

5.3

PROGRAM MODULE DESCRIPTION

Program Module Name: COUNT PULSES

~:

Labe 1 :

HMCS402C/
HMCS404C/HMCS408C

PLSCNT

Function:
Counts pulses input from INTI pin, and loads count result into Accumulator, and
B register.

Arguments:

1 digit = 4 bits
Storage
No. of
Location Digits

Contents
Start/stop
Entry
request
flag

STRTF
(RAM)

Specifications:

Changes in CPU
Registers and Flags:
A

1

1 word

B

Returns

A, B

10 bits
16

RAM (Digits):

x

y

•

•

No. of cycles:

SPX

Spy

•

•

2

1

Stack (Digits):

Reentrant:

0
13

No

Relocatable:

No

Interrupt OK?:

W

Set TCB
value

=

ROM (Words):

No

•
CA

ST

•

x

•

Not Affected

x : Undefined

Result
Description:
1. Function Details
(1) Argument details
STRTF(RAM): Holds flag indicating
whether input pulse
count will start or
stop. Table 5.3 shows
flag functions.
A.B:

Contains input pulse count
result as a I-byte
hexadecimal number.

CD Input
pulse

{GJ,rul::rLi\GJ
STRTF

STRTF

($01)

@ Return
argument
Fig. 5.5.

($00)

{

B

L..-...:A~..J

A

~

Example of PLSCNT
Execution

I

Spooif1oa"on, Notes:

HITACHI 103

Program Module Name:

COUNT PULSES

MCU: HMCS402C/
HMCS404C/HMCS408C

I~

PLSCNT

Description:
Table 5.3.

(2)

Flag Function

Label

Bit 0

Function

STRTF

o

Ends pulse count

1

Start pulse count

Example of PLSCNT execution is shown in Fig. 5.5.
If 160 pulse is inputted by INTl pin as shown in port Q;) of Fig. 5.5,
loads measurement result into Accumulator, B register as shown in port
of Fig. 5.5.

(3)
2.

PLSCNT calls neither the program modules nor subroutines.

User Notes
The following procedure must be performed before PLSCNT execution.

3.

(1)

Counts input pulse up to 255 pulses by using TCB.

(2)

Sets R33/INTl as INTl before using module PLSCNT.

(3)

Sets STRTF to indicate the start and end of pulse counting.

RAM Allocation

Fig. 5.6.

Label

S T RT F

Description

RAM

•

b3

bO

MD($020)

104 HITACHI

RAM Allocation

Flag indicating whether input pulse
will start or stop

CD

Program Module Name:

COUNT PULSES

MQ!.: HMCS402C/
HMCS404C/HMCS408C

IL-,'

PLSCNT

Description:
4.

Sample Application

WORK1

EQU

$ 03 0

WORK2

EQU

$ 0 3 1

LMID

$ 8. PMR

1/

II

Allocate RAM area for pulse count result
in Hexadecimal

LMID

...... Select R33/ INT l as INTl
$ 1. STRTF ...... Store Flag indicating start of pulse count

CALL

PLSCNT

REMD

o. STRTF

...... Clear flag indicating end of pulse count

CALL

PLSCNTII

...... Call PLSCNT and end pulse count

LMAD

WORK1

LAB
LMAD

5.

f

J ......

WORK2

...... Call PLSCNT and start pulse count

1/

)

Store Hexadecimal pulse count in return
argument into RAM area

Basic Operation
(1) TCB (timer/event counter) is initialized by writing $00 into TCR
(timer/load register) .
(2) TCB counts up so that at the point of ending pulse count, reading TCB
will enable determination of the pulse count.

HITACHI 105

Program Module Name:

COUNT PULSES

!:!fQ: HMCS402C/
HMCS404C/HMCS408C

Label:

PLSCNT

Flowchart:

as event input from INTI pin

upper digit of timer/event counter
B register

L-____~----~

PLSCT2

106 HITACHI

----rl

Load lower digit of timer/event counter
into Accumulator

5.4

SUBROUTINE DESCRIPTION
This application example calls no subroutines.

5.5

PROGRAM LISTING

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057

010

0000

SOURCE STATEMENTS
LLEN
TITLE

*****
*STRTF

HEXDAI
HEXDA2
HEXDA3
HEXDA4
XHEXD
YHHEX
YHDEC
BAHEX
BADEC

*
****
*PMR

TMB
TCBL
TCBU
TLRL
TLRU

132
INPUT PULSE COUNT

RAM ALLOCATION
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

****************************************

S020
S04A
S04B
$04C
$040
$4
SA
$2
SE
S7

SYMBOL DEFINITIONS
EQU
EQU
EQU
EQU
EQU
EQU

S004
S009
SOOA
SOOB
SOOA
S006

START/STOP REQUEST FLAG
HEXADECIMAL DATA (I-DIGIT)
HEXADECIMAL DATA (2-DIGIT)
HEXADECIMAL DATA (3-DIGIT)
HEXADECIMAL DATA (4-DIGIT)
HEXADECMAL AND BCD DATA ADDR(X)
2-BYTE HEXADECIMAL DATA LSD ADDR(Y)
5-DIGIT BCD DATA LSD ADDR(Y)
2-BYTE HEXADECIMAL DATA MSD ADDR(Y)+1
5-DIGIT BCD DATA MSD ADDR(Y)+1
************************************
PORT MODE REGISTER
TIMER MODE REGISTER
TIMER/EVENT COUNTER
TIMER/EVENT COUNTER
TIMER LOAD REGISTER
TIMER LOAD REGISTER

8 (LOWER)
B (UPPER)
(LOWER)
(UPPER)

****************************************************************

150
150
150
150
150

010
010
010
010
010

150 010

0000
0002
0004
0006
0008
OOOC

*
*
VECTOR ADDRESSES
*
*
******************************************************************
*
ORG
SOOOO
*
JMPL
PLSMN
RESET

*
*

JMPL
JMPL
JMPL
JMPL

PLSMN
PLSMN
PLSMN
PLSMN

ORG

SOOOC

JMPL

PLSMN

INTO
INTI
TIMER-A
TIMER-B
SERIAL

****************************************************************

OFO
lA8 004
lAI 020
160 036
20F
23F
21F
002

0010
0011
0013
0015
0017
0018
0019
001A

*
*
MAIN PROGURAM : PLSMN
*
*
*
*
****************************************************************
*
ORG
SOOIO
*PLSMN
INITIALIZE W REGISTER
LWI
SO

PLSMNI
PLSMN2
PLSMN3

LMID
LMID
CALL
LBI
LAI
LYI
XSPY

S8.PMR
SI.STRTF
PLSCNT
15
15
15

SELECT INTI
SET START FLAG
START TO COUNT PULSE
EXECUTE 200MS SOFTWARE TIMER

HITACHI 107

00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
000B6
000B7
000B8
000B9
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114

21B
ODF
31C
002
000
ODF
3lA
2BF
319
OCF
31B
1BB
160
194
048
194
lAO
lAO
160
335

0018
001C
OOlD
OOlE
001F
0020
0021
0022
0023
0024
0025
020 0026
036 0028
04A 002A
002C
04B 0020
04C 002F
040 0031
047 0033
0035

PLSMN4

PEND

LYI
DY
BRS
XSPY
NOP
DY
BRS
AI
8RS
08
8RS
REMD
CALL
LMAD
LA8
LMAD
LMID
LMID
CALL
BRS

8

PLSMN4

PLSMN3
15
PLSMN2
PLSMNI
O.STRTF
PLSCNT
HEXDAI
HEXDA2
$0.HEXDA3
$0.HEXDA4
HEX
PEND

CLEAR START FLAG
STOP COUNTING PULSE
LOAD HEX ENTRY ARGUMENT
B REGISTER ---> HEX.DATA AREA 2
CLEAR UNUSED HEX.DATA AREA 3
CLEAR UNUSED HEX.DATA AREA 4

****************************************************************

**
**
NAME : PLSCNT (COUNT PULSE)
******************************************************************
**
*
ENTRY: STRTF (START/STOP REQUEST FLAG)

*

RETURNS: ACCUMULATOR A.B REGISTER (2'S COMPLEMENT OF TC8)*

*

lBC
340
190
OCB
190
150
lA7
lAO
lAO
010

020
OOB
OOA
046
009
OOA
OOB

0036
0038
0039
003B
003C
003E
0040
0042
0044
0046

*

****************************************************************

PLSCNT

PLSCTl
PLSCT2

TMD
BRS
LAMD
LBA
LAMD
JMPL
LMID
LMID
LMID
RTN

O.STRTF
PLSCTl
TCBU

TC8L
PLSCT2
$7.TMB
$O.TLRL
$O.TLRU

TEST START FLAG

LOAD UPPER DIGIT OF TIMER/EVENT COUNTER
-INTO B REGISTER
LOAD LOWER DIGIT OF TIMER/EVENT COUNTER INTO A
SET EVENT INPUT
CLEAR TIMER LOAD REGISTER

*****************************************************************

**

NAME : HEX (CONVERT 2-BYTE HEXADECIMAL INTO 5-DIGIT BCD)**

*******************************************************************

*

*

224
212
290
077

349
20F
2lA

108 HITACHI

0047
0048
0049
004A
004B
004C
0040

ENTRY : MD($04D-$04A) (2-BYTE HEXADECIMAL DATA)
*
*
RETURNS : MD($046-$042) (5-DI5IT BCD DATA)
*
*
*******************************************************************
HEX

HEXl

HEX2

LXI
LYI
LMIIY
YNEI
BRS
LBI
LYI

XHEXD
YHDEC
$0
BADEC
HEXI
$F
YHHEX

LOAD HEXADECIMAL ADDR(X)
LOAD BCD DATA ADDR(Y)
CLEAR 8CD DATA ADDRCY)

LOAD SHIFT COUNTER
LOAD HEXADECIMAL DATA ADDR(Y>

00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131

090
OAl
050
07E
34E
212
090
OAl
OA6
050
077
354
OCF
340
010

004E
004F
0050
0051
0052
0053
0054
0055
0056
0057
005B
0059
005A
005B
005C

HEX3

HEX4

*

LAM
ROTL
LMAIY
YNEI
BRS
LYI
LAM
ROTL
DAA
LMAIY
YNEI
BRS
DB
BRS
RTN

SHIFT HEXADECIMAL DATA l-BIT LEFT
BAHEX
HEX3
YHDEC

BADEC
HEX4
HEX2

LOAD BCD DATA LSD ADDR(Y)
BCD DATA AREA *2+CA-)ACCA
CONVERT INTO BCD DATA ?
LOAD DECIMAL DATA
TEST IF CONVERSION IS COMPLETED
DECREMENT SHIFT COUNTER
LOOP UNTIL SHIFT COUNTER • SF

END

HITACHI 109

SECTION 6.

6.1

KEY MATRIX (8 x 4)

HARDWARE DESCRIPTION

6.1.1

Function
Performs key scan of 8 x 4 key matrix, invalidating simultaneous
depression of more than 2 keys by software, and converting valid key
data into ASCII characters (A - Z or 1 - 6).

6.1.2

Microcomputer Operation
The HMCS404C uses timer B to execute timer/event counter every 8

IDS.

Key scan is performed by an output strobe signal through port D during
the interrupt routine and key scan data is fetched through port R.

6.1.3

Peripheral Devices
8 x 4 Key matrix : Keys to be depressed.

6.1.4

Circuit Diagram
Key scan control circuit is shown in Fig. 6.1.

+~v

MCU
HMCS4.0 4C

... 5V

41k.flX8

(::g~!~:g)
50 TEST

Do

+5V

D,
+5V

32

Vee

D,
D,

54

KRO

55

KRl

~6

KR2

51

KR8

H074HC14

9 RESET
r--=+---+-;JI;>O--il!:»-1ICo----"4"1

R,o
Ru
Rn
R..
R.o
R"
R..
R.,

Fig. 6.1.

no HITACHI

24
25
26
21
45
46
41
48

Key Scan Control Circuit

6.1.S

Pin Functions
Pin functions at the interface between the HMCS404C and the key
matrix are shown in Table 6.1.

6.1.6

Table 6.1.

Pin Functions

Pin Name
(HMCS404C)

Input/
Output

Active Level
(High or Low)

D3

Output

Low

D2

Output

Low

KR2

Dl

Output

Low

KRl

DO

Output

Low

KRO

RSO

Input

RSl

Input

KCl

RS2

Input

KC2

RS3

Input

KC3

RgO

Input

KC4

R9l

Input

KCS

R92

Input

KC 6

R93

Input

KC7

Pin Name
(Key matrix)

Function
Outputs strobe
signal

KR3

Inputs key
data

KCO

Hardware Operation
The timing chart for key scan is shown in Fig. 6.2.

Key depression
signal

orr
ON

___________________Vvv\~__________~O~N~
'--v--'

Chatter

Key fetch

CD

First key data

timing

@

Second key data

G)

Third key data

CD

(Timer interrupt)

®
CD

®
®

®

ON

Key data

______________O~F~F______________

,

--Jr___

valid timing

Key data is

valid

Fig. 6.2.

Chatter Prevention Timing

Key depression signal is checked every 8 ms.

If key data is the same

3 consecutive times, it is considered valid, and invalid otherwise.

HITACHI 111

6.2

SOFTWARE DESCRIPTION

6.2.1

Program Module Configuration
The program module configuration for key scan of 8 x 4 key matrix is
shown in Fig. 6.3.

K84.MN

I.!..
Main Program.

K84.SCN

J

1.2-

Key Scan

Fig. 6.3.

6.2.2

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 6.2.

Table 6.2.

112 HITACHI

Program Module Functions

No.

Program Module Name

Label

Function

0

Main Program

K84MN

Performs key scan of 8x4 key matrix
and converts key data into ASCII

1

Key Scan

K84SCN

Performs key scan of 8x4 key
matrix

6.2.3

Program Module Process Flow (Main Program)
The Flowchart in Fig. 6.4 is an example of a key scan of the 8 x 4 key
matrix performed by the program module in Fig. 6.3.

Main Program

L-----r---...J----{

Initialize W register

Clear RAM used by K84SCN

L-_ _~_---J

____ {select auto-reload function and select
Prescaler Divide Ratio as + 512

.----..I----.----t
L-_ _--.,...-_ _...... - - - - {

Seleot timer interrupt oyole to 8 mo

Clear timer B interrupt request flag

L-----r---.... -- - --[ Clear timer B interrupt mask

.-----.....,.,;:~:;::::r----'----{

Enable interrupt

flag to indicate key is depressed

Fig. 6.4.

Program Module Sample Application

HITACHI 113

Execute pattern instruction for storing
ASCII corresponding to depressed key data

Timer interrupt routine

'-_ _ _...-_ _ _.... ----{ Execute K84SCN to perform key scan

Fig. 6.4.

114 HITACHI

Program Module Sample Application (Cont)

6.3

PROGRAM MODULE DESCRIPTION
Name:

KEY SCAN

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

K84SCN

Function:
Performs key scan of 8x4 key matrix to store key data in KEYDTU(RAM) and
KEYDTL(RAM) •

Arguments:
Contents
Entry

-

1 digit = 4 bits
Storage
No. of
Location Digits

-

Specifications:

Changes in CPU
Re!l:isters and Flags:

-

ROM (Words):

141

•

•

RAM (Digits):

13

X

Y

Stack (Digits): 0

•

•

No. of cycles: 1870

Spy

•

Interrupt OK?:

KEYDTU
KEYDTL

1
1

•

Key data
valid/
invalid
flag

KEYONF

1

CA

ST

•

•

:

Reentrant: No
Relocatable: No

W

Key data

x

bits

B

•

•

= 10

A

SPX

Returns

1 word

No

Not Affected
Undefined
Result

Description:
1. Function Details
(1)

Argument details
KEYDTU(RAM): Stores upper digit of key data
KEYDTL(RAM): Stores lower digit of key data
KEYONF(RAM): Contains Flag indicating whether or not key data is valid.

Specifications Notes:
The number of cycles indicate is that necessary to validate key data.

HITACHI 115
----------

----------------

Program Module Name:

KEY SCAN

MCU: HMCS402C/
HMCS404C/HMCS408C

Label: K84SCN

Description:
Table 6.3.

(2)

Flag Function

Label

bit 0

Function

KEYONF

o

Indicates key data is invalid

1

Indicates key data is valid

Example of K84SCN execution is
shown in Fig. 6.5. If a key
is pressed as shown in part
of Fig. 6.5 , key data is
stored in KEYDTU(RAM) and
KEYDTL (RAM) .

0

(3)

CD

Depress the key

Key "D" is pressed
(in Fig. 6.1 of
key scan control
circuit)

1

K84SCN calls neither the program
modules nor subroutines.
KEYIYfU(RAM) K,EYDTU KEYDTL

2.

User Notes
The following procedure must be
performed before K84SCN execution.
(1)

(2)

3.

Initializes timer control/
status register B.

: KEYIYfL(RAM).
0
4[ ($05F,$05E)
Return
argument
KEYONF
KEYONF(RAM)
(0, $05D)
0 0 0

I I I

Fig. 6.5.

Sets IE to enable timer B
interrupt.

RAM Allocation

Fig. 6.6.

116 HITACHI

RAM Allocation

Example of K84SCN
Execution

Program Module Name: KEY SCAN

MCU: HMCS402C/
HMCS404C/HMCS408C

Label: K84SCN

Description:

Label

RAM
b3

Description
bO

KEYONF

Flag indicating whether or not key data
is valid

MD(S05D)
b3

KEYNMU

bO

II

Upper digit for storing key number

MD(S05C)

•

b3

KEYNML

bO
Lower digit for storing key number

MD(S05B)
b3

bO

TOTLKY

Stores total number of pressed keys
in the present key scan

MD(S05A)
b3

bO

NEWKYU

Upper digit for storing
data input

curr~nt

key

MD(S059)
b3

bO
Lower digit for storing current key
data input

NEWKYL
MD(S058)
b3

bO
Upper digit for storing previous key
data input

OLDKYU
MD(S057)

•

b3

OLDKYL

bO
Lower digit for storing previous key
data input

MD(S056)

HITACHI 117

Program Module Name: KEY SCAN

MCU: HMCS402C/
HMCS404C/HMCS408C

Label: K84SCN
--

Description:
Label

Description

RAM

b3

bO

~
MD(S055)

PRDATU

b3

Stores depressed key data (R9)

bO

PRDATL

Stores depressed key data (R7)

MD(S054)
b3

bO
Bit 0, 1: Stores counter for counting
number of key scan data
comparison
Bit 3: Stores flag for indicating
whether chatter elimination has
been completed

CHATFL
MD(S05S)

b3

bO
Upper digit for storing defined key
number by key scan

KEYDTU
MD(S05F)
b3

bO
Lower digit for storing defined key
number by key scan

KEYDTL
MD(S05E)

118 HITACHI

Program Module Name:

KEY SCAN

MCU: HMCS402C/
HMCS404C/HMCS40BC

Label: KB4SCN

Description:
4.

Sample Application

LMID
LMID
REMD
LMID

K84MNI

5.

0, 0 L D K Y U) ...... Clear RAM to be used

0, OLDKYL
KEYONF
S 9, TMB

LMID

$8, TLRL

LMID

SF, TLRU

REMD

IMTB

SEMD

IE

TMD

KEYONF

BR
REMD

K84MNI
KEYONF

Select timer B interrupt cycle to B ms
and enable timer B interrupt

} ...... Test if key is depressed
...... Clear key depressed flag

Basic Operation
(1) Key scan is executed every 8 ms interrupt. At the beginning of K84SCN,
key data valid/invalid flag KEYONF(RAM) is checked to determine whether
or not previous valid key data has been processed.
(2) Strobe signal (=low) is output through bits 0-3 of port D, and key scan
data is fetched through port R.
(3)

Key scan data fetched in (2) is tested whether or not it is $FF.
(a)

If $FF, no key is depressed and key scan for next column is executed.

(b)

If not $FF, some key is depressed and what row of depressed key is
tested.
(i) Accumulator, containing key scan data, is shifted 1 bit right
B times. CA is determined.
If CA is o , it means a key is
depressed.
(ii) Key data is numbered from 1 to 32, based on position in 8 x 4 key
matrix. Key data is stored in KEYNMU(RAM) and KEYNML(RAM).
(iii) TOTLKY(RAM) is incremented every time a key is depressed to check
for chatter. If TOTLKY(RAM) ~ 1, key data is stored in
NEWKYU(RAM) and NEWKYL(RAM). If TOTLKY(RAM) > 1, key scan is
completed since it indicates two keys are pressed at the same
time.

HITACHI 119

Program Module Name:

KEY SCAN

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

K84SCN

Description:
(4)

Key data (NEWKYU(RAM) and NEWKYL(RAM» obtained in (3) is compared with
previous key data (OLDKYU(RAM) and OLDKYL(RAM». If they are the same,
chatter counter (CHATFL(RAM» is counted up. When chatter counter
becomes 3, key data is valid. If key data is valid, MSB of CHATFL(RAM)
is set to l to indicate that key data is valid. CHATFL(RAM) includes
both a counter and a flag. CHATFL(RAM) is cleared, when (NEWKYU(RAM)
and NEWKYL(RAM» data differs from (OLDKYU(RAM) and OLDKYL(RAM» data
or no key is depressed.

120 HITACHI

MCU: HMCS402C/
HMCS404C/HMCS408C

Program Module Name: KEY SCAN

~K84SCN

Flowchart:

-r______

L-____

~----~Clear

timer B interrupt request flag

Save register

if key data has been processed by
program

, ____......______, - - - { '"'''oU,o _

L-____~------~

'0' "_,

____ [rnitialize RAM for number of depressed
keys

,----.. . .------.,----1'"'''0'''0
I--__

Co,

-=====!------~----_[
...-_ _",-_ _,---

,~

Co<

00' '" 0""",,,

Output strobe signal

-{~,

,., "00

~~

Test if a key is depressed every time
RD::T-U- [ strobe signal is output
: PRDATL
~$FF

~~~~~_-_.J.r-_-_-_-_-_'~----{Clear

l

CA

I f no key is depressed, store next
startlng key number

HITACHI 121

Program Module Name: KEY SCAN

~:

HMCS402C/
HMCS404C/HMCS408C

~K84SCN

Flowchart:

r--------2======r---~

_____ [Initialize shift counter to test which
key is depressed

Shift key scan data 1 bit right

-----{ Test if key is depressed

_____lf

Test if key chatter is generated.
If so, complete key scan

r-:""""..,.,..,.J....,__--...,

----1

Store depressed key number in RAM as
key data

L-~::::::::::~~

'-____.,.-____..... ----- [ Clear CA

.------.. . ----.. . ----1
L-____.,.-_ _....J - - - - -[

'nmmen' RAM indicaHng key nmMec

Decrement shift counter

Test if all keys have been checked
----{ whether or not they are 'depressed

122 HITACHI

Program Module Name: KEY SCAN

MCV: HMCS402C/
HMCS404C/HMCS408C

Label: K84SCN

Flowchart:

I -_ _

~

--.J----{

__

Output next strobe signal

to execute key scan

if key scan for all columns have
completed

if a key is depressed this time

Store current key data in RAM for next
key scan.
Clear RAM indicating number of key
scan

Restore register

HITACHI 123

Program Module Name: KEY SCAN

HCU: HMCS402C/
ID1CS404C/HMCS408C

Label: K84SCN

Flowchart:

with

if key data is valid

_____ [ Test if key scan has been executed 3
times

_____ [ Increment RAM indicating number of
key scan
_____ [ Set flag to "1" to indicate key data
is valid

_____ [ Store valid key number in return
argument

_____ [ Set flag to "1" to indicate a key is
depressed
~--------

124 HITACHI

__

~r---------~

6.4

SUBROUTINES
This application example calls no subroutines.

6.5

PROGRAM LISTING

ST-NO

OBJECT

ADRS

SOURCE STATEMENTS

00001
00002
00003
00004
00005
00006
00007
OOOOB
00009
00010
00011
00012
00013
00014
00015
00016
000l?
0001B
00019
00020
00021
00022
00023
00024
00025
00026
00027
0002B
00029
00030
00031
00032
00033
00034
00035
00036
00037
0003B
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057

010

0000

LLEN
132
TITLE
KEY MATRIX (B*4)
*
RAM
ALLOCATION
********************************
****
*
KEYDTU
EQU
$05F
UPPER KEY DATA
KEYDTL
EQU
$05E
LOWER KEY DATA
KEYONF
EQU
0.$050
KEY ON FLAG
EQU
$05C
UPPER KEY NUMBER
KEYNMU
EQU
$05B
KEYNML
LOWER KEY NUMBER
EQU
$05A
TOTAL KEY NUMBER
TOTLKY
$059
NEWKYU
EQU
UPPER NEW KEY DATA
NEWKYL
EQU
$05B
LOWER NEW KEY DATA
EQU
OLDKYU
S057
UPPER OLD KEY DATA
EQU
$056
OLDKYL
LOWER OLD KEY DATA
PRDATU
EQU
$055
R9 PORT DATA
EQU
$054
PRDATL
R5 PORT DATA
$053
CHATFL
EQU
CHATTER CTR AND END FLAG
*
**** SYMBOL DEFINITIONS ****************************
*
TMB
EQU
$009
TIMER MODE REGISTER B
IFTB
EQU
0.$002
IF OF TIMER B
EQU
IMTB
1.S002
1M OF TIMER B
EQU
INTERRUPT ENABLE FLAG
IE
O.SOOO
EQU
TLRU
$OOB
TLR UPPER
EQU
TLR LOWER
TLRL
SOOA
$2
EQU
CMPNUM
CHATTER NUMBER
********************************************************

*
*
*

*
*

VECTOR ADDRESSES

********************************************************

*
150
150
150
150
150
000
000
150

010
010
010
010
036
010

0000
0002
0004
0006
0008
OOOA
OOOB
OOOC

*

ORG

$0000

JMPL
JMPL
JMPL
JMPL
JMPL
NOP
NOP
JMPL

J, =,<) of 8-bit binary data of 2 group,
and loads "$0" "$1" or "$2" into B register as
a result

Calculate
Normal/Reverse
Data

SMFR

Tests whether the slue is normal or reverse and
sets the next data to the stepping motor

User Notes
When the slue is reverse, the maximum number of steps is $FE.
set, an exact slue data is not set.

3.

When $FF is

RAM Allocation

Fig. 8.7.

RAM Allocation

Specifications Notes: "No. of cycles" in "Specification" represents the number of
cycles required to execute data in the sample application.

HITACHI 153

Program Module Name: Process Data

MCU: HMCS402C/
HMCS404C/HMCS408C

Description:

Label
b7
STEPU:STEPL

Description

RAM
bO

~

Stores total step count

MD($08F, $08E)

HSUP:LSUP

b7

bO

~~

Stores one-fourth of the step count
due to slue-up

MD(SOS9,S038)
b7

bO

HSHOLD:LSHOLD
11111111111111111

Stores one-fourth of the step count
due to operating

MD(S047,S046)
b3
SDWN

bO

[ill]]]

Stores on~-fourth of the step count
due to slue-down

MD(S045)
b3
SDWNW

bO

§

WORK AREA for SDWN

MD(SOH)

•
•

b3
SMSF

bO
Stores flag indicating start slue for
the stepping motor

MD(2.S037 )

b3
STEPE

bO
Stores remainder of a total step
divided by 4

MD(S051)
b7

HSTEPW: LSTEIW

bO

~

MD(SOU,$042)

154 HITACHI

Stores WORK AREA for STEP

Program Module Name: Process Data

MCU: HMCS402C/
HMCS404C/HMCS408C

ILabelo
SHe",
.

Description:

Label

RAM

m
b3

SCNTR

Description

bO

Stores 4-step counter

MD(SOSO)
b7

HAUG:LAUG

bO

ti~~

Holds 8-bit binary augend.
After execution, contain addition result

MD(S03D,S03C)
b7

HADD:LADD

bO

~

Holds 8-bit binary addend

MD( $04.9, S048)
b7

bO
Holds 8-bit binary data to be
shifted to right

HSHR:LSHR
MD( SOH, S04E)
b7

bO

HMIN:LMIN

111111" 1I111111III

Holds 8-bit binary minuend.
After execution, contain subtraction resuit

MD(SOU ,S040)
b7

HSUB:LSUB

bO

~
MD($04D,S04.C)
b7

Holds 8-bit binary subtrahend

bO

HCMD:LCMD

Holds the first 8-bit binary value

MD(S03B,S03A)
b7

HCMT:LCMT

bO

IQ QIQ QI

Holds the second 8-bit binary value

MD(S04B,SOU)

HITACHi 155

Program Module Name:

Process Data

MCU: HMCS402C/
HMCS404C/HMCS408C

ILabe1'

SMCLC

Description:
'4.

Sample Application

WORKU
WORKL

EQU
EQU
SEMD
LAMD
LMAD
LAMD
LMAD

SO 5 5

} ............ Reserve memory byte for total step count

S 0 5 4

Set normal/reverse flag to normal

total step count into entry

CALL_ _ _s_M_c_L_c_..uII·· .. ·· .. · Call SMCLC and process
IIu...._...-_

156 HITACHI

the data

Program Module Name:

Process Data

MCV: HMCS402C/

HMCS404C/HMCS40BC

IL.b.,'

SMCLC

Description:
5.

Basic Operation
(1)

Tests whether slue is normal or reverse.
If it is reverse,
added to the total step count for backlush processing.

(2)

Slue-up and slue-down operations are executed every 4 steps. The total
step count is multiplied by one-fourth.
If the result is 2 or less, slue-up and slue-down are not executed.

(3)

If one-fourth the step count is 3 or more, values of slue-up data,
operating data, and slue-down data are determined for slue-up and
slue-down processing.

(4)

Slue-up of 21 steps and slue-down of 7 steps are executed.

(5)

Slue-up data, operating data, and slue-down data are shown in (a)
to (c), by one-fourth the step count "n" obtained in (3) and (4).
(a) At n

=3

to 29, n

=

2+4m (m

=

=

3 to 29, n < 2+4m (m

slue-up data
operating data
slue-down data
(c)

=

is

1 to 6)

slue-up data = one-fourth the total step count operating data
0
slue-down data = m
(b) At n

1

(m+2)

1 to 6)

one-fourth the total step count -

(m+l)

o
m

At n ;;: 30
slue-up data
operating data
slue-down data

21
one-fourth the total step count - 29
7

(6)

If one-fourth the step count is 0 , STEPE(RAM), the remainder of
one-fourth the step count only is output.

(7)

If one-fourth the step count is n(l to 2), a step count of "n x 4+STEPE
(RAM)" is output.

HITACHI 157

Program Module Name:

Process Data

~:

HMCS402C/
HMCS404C/HMCS408C

I~

SMCLC

Flowchart:

FRFLG=l

whether slue is normal or reverse

For reverse slue, backlash processing is
executed

r-----~----~

____ [store the remainder of total step counts
to be processed divided by 4

'--_......-_--..J

Divide total step counts to be processed
by 4 to permit 4-step processing

158 HITACHI

Program Module Name:

Process Data

MCU: HMCS402C/
HMCS404C/HMCS408C

[~

SMCLC

Flowchart:

if one-fourth the step count

r-----~----~

~

2

____ [Store "4" in SCNTR and "0" in SDWNW if
one-fourth the step count ~ 3

'----.-_.....

r-----~----~

----l

Store "2" in LSTEPW if one-fourth the
step count ~ 3

~~:::;:r---'

L -____~~~~

_____ [store data to test slue-down in RAM
if step count < 30

Store data to test slue-up in RAM
if step count < 30

HITACHI 159

Program Module Name:

Process Data

MCU: HMCS402C/
HMCS404C/HMCS408C

1Lobe',

SMCLC

Flowchart:

____ [ Test if one-fourth the step count

2

Store 4 in SCNTR(RAM) and 1 in LSHOLD
when one-fourth the. step counter is 2

STEPL; 2

Test if one-fourth the step count <
2 + 4n (n = 1 to 26)

1-----'

r---~~----~

SMeLl?

____ [ Store 0 in HSHOLD, LSHOLD if one-fourth
the step count :;; 2 + 4n

'---~--'"

____ [ Store 1 in LSHOLD when one-fourth the
step count = 2 + 4n

162 HITACHI

Program Module Name:

Process Data

MCU: HMCS402C/
HMCS404C/HMCS408C

I~

SMCLC

Flowchart:

L.._ _......._ _...J - - - - - [

Store SDWNW (RAM) value as slue-down data

Store one-fourth the step count (SDWNW(RAM) + operating data + 1) as
slue-up data

HITACHI 163

Program Module Name:
Generate Stepping Motor Output

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

SMREV

Function:
outputs pulse to the stepping motor.

Arguments:

1 digit = 4 bits
Storage
No. of
Contents
Location Digits
I
HSUP (RAM)
Slue up
Entry data
LSUP(RAM)
1
Operating HSHOLD(RAM)
1
data
LSHOLD(RAM)
1
Slue-down SDWN (RAM)
1
data
Remainder STEPE(RAM)
1
of the
step
Normal/
FRFLG(RAM)
1
reverse
slue flag
Slue
SMSF(RAM)
1
start
flag
ReSlue
SMSF(RAM)
1
turns start
flag

Changes in CPU
Registers and Flags:

Specifications:
1 word

= 10

ROM (Words):

bits

205

A

B

x

x

RAM (Digits):

X

y

Stack (Digits): 4

x

x

No. of cycles:

SPX
x

Spy
x

Reentrant:

23

No

Relocatable:

No

Interrupt OK?:

W

83

No

•
CA
x

•
x

:

ST
x

Not Affected
Undefined
Result

Description:
1. Function Details
(1)

Argument details
FRFLG:

SMSF (RAM)

Holds
start
shown
STEPU: STEPL (RAM) : Holds
Holds
HSUP : LSUP (RAM)
HSHOLD: LSHOLD (RAM) : Holds
Holds
SDWN(RAM)
STEPE(RAM) : Holds

Specifications Notes:

164 HITACHI

flag indicating rotation direction and rotation
of the stepping motor. Flag functions are
in Table 8.5.
total slue step count.
slue-up data.
operating data.
slue-down data.
remainder of the total step count divided by 4.

Program Module Name:
Generate Stepping Motor Output

MCU: HMCS402C/
HMCS404C/HMCS408C

SMREV

ILobel'

Description:
Table 8.5.

Label

Flag Functions

Bit/Label
SMSF
FRFLG

FLGl

(2)

Function

0

Rotates stepping motor clockwise (normal)

1

Rotates stepping motor counterclockwise
(reverse)

o

Stops slue

1

Starts slue

Fig. 8.8 shows an example of
SMREV execution.
If the entry argument is
held as shown in part
of
Fig. 8.8 outputs pulse to
the stepping motor.
Then, the slue start flag
SMSF(RAM) is contained as
shown in part
of Fig.
8.8.

HSUP

~

HSUP:LSUP(RAM)
MD ( $ 039, $ 038 )

CD

HSHOLD LSIDLD
HSHOLD:LSHOLD(RAM)
MD($047, $046)

GJ GJ

SJJ.1IN

SDWN(RAM)
MD($0+5)

(j) Entry

GJ
GJ

argument

0

STEPE
STEPE(RAM)
MD($051 )
SMSF(RAM)MD( 2, $087)

(3)

Slue start i=l)
FRFLG (RAM)MD 0, $037)
Reverse slue (=0)

SMREV calls other routines
shown in Table 8.6.

CD

!MlF FRFLG

1-1 +1 1
0

b3 SMlF

Return
argument

Fig. B.8.

Table 8.6.

LSUP

G

{SMSF(RAM)
MD (2, $ 0 3 7 )

bO

1-101-1-1

Example of SMREV Execution

Program Modules and Subroutines Used in SMREV

Program Module/
Subroutine Name

Label

Function

Load normal/
Reverse slue data

SMFR

Tests whether slue is normal or reverse and
stores next data in stepping motor

Subtracting
8-bit binary data

SUB

Performs subtraction of 8-bit binary data
in RAM, and stores result in RAM

Adding 8-bit
binary data

ADD

Performs addition of 8-bit binary data in
RAM, and stores result in RAM

HITACHI 165

MCU: HMCS402C/
HMCS404C/HMCS408C

Program Module Name:
Generate Stepping Motor Output

I

Labol ,

SMREV

Description:
2.

User Notes
(1)

Initializes timer B.

(2)

Clears bit IE to enable timer interrupt.

3. RAM Allocation

Fig. 8.9.
Label

RAM

Description

b7

HSUP:LSUP

RAM Allocation

bO

~

Stores one-fourth of the step count
due to slue-up

MD( S039, S038)

b7

bO

HSHOLD:LSHOLD
1111111111111111

Stores one-fourth of the step count
due to operating

MD(S047,S046)

b3

SDWN

bO

[illill]

Stores one-fourth of the step count
due to slue-down

MD($045)

b3

FRFLG

bO

[]

Stores flag indicating normal rotation
of the stepping motor

MD(O,S037)

b3

SMSF

bO

[]]
MD(?$037)

166 HITACHI

Stores flag indicating start slue
for the stepping motor

Program Module Name:
Generate Stepping Motor Output

MCU: HMCS402C/
HMCS404C/HMCS408C

Description:

RAM

Label

b3

SCNTR

Description

bO

mmfj

Stores 4-step counter

MD(S050)
b3

STEPE

~
MD(S051)
b3

PBSM

bO
Stores remainder of a total step divided
by 4

bO

mmm

Stores data output to stepping motor

MD(S080)
b7

HAUG:LAUG

~~
MD(S08D,S08C)
b7

HADD:LADD

bO
Holds 8-bit binary augend.
After execution, contain" addition result

bO

~$1Jj

Holds 8-bit binary addend

MD(S049,S04.8)
b7

bO

HMIN:LMIN

1111111111111111

Holds 8-bit binary minuend.
After execution contain subtraction
result

MD( SOH, S04.0)
b7

HSUB:LSUB

~
MD(S08B,S03A)
b7

HTLRD:LTLRD

bO

I

Holds 8-bit binary subtrahend

bO

I

Stores WORK AREA for timer load
register

MD(S082. S031)

HITACHI 167

Program Module Name:
Generate Stepping Motor Output

MCV: HMCS402C/
HMCS404C/HMCS408C

1Label , SMREV

Description:
Label

RAM
b7

Description
bO

~

HDDTA:LDDTA

stores address for slue-down data

MD(S034,S033)
b7

bO
Stores address for slue-up data

HUDTA:LVDTA
MD(S036,S035)

4.

Sample Application

WORKU

EQU

WORKL

E9 U

:::: }

........ .

Reserve memory byte for the total step
counter

LAI
LMAD

::SM

LRA

PBDTR

REMD

SMSF

LMID

II

) ........ .

......... Set rotation stop

LMID

S2., LTLRD)
SB, H T LRD

LMID

S 2, T L R L

LMID

SB, TLRU

LMID
SEMD

S B, T M B

REMD

FRFLG

LAMD

WORKU

Initialize output timing to the stepping
...... motor

IE··········· Enable interrupt

LMAD

STEPU

LAMD

WORKL

LMAD

STEPL

CALL

SMCLC

II

~--------------~

168 HITACHI

Initialize the stepping motor output pin

·····Calculate entry argument

Program Module Name:
Generate Stepping Motor Output

MCV: HMCS402C/
HMCS404C/HMCS408C

IWbel'

SMREV

Description:
5.

Basic Operation
(1)

Program module SMREV is called by the timer routine.

(2)

Outputs pulses one step to stepping motor every timer interrupt.

(3)

At the beginning of timer interrupt, timer timing (slue-up, operating
and slue-down slue) which is held in advance and output to the
stepping motor.

(4)

Following (3), data to be output at the next timer interrupt is
loaded.

(5)

Only the timer timing is held and no output is provided to the stepping
motor, when the rotation start flag SMSF(RAM) is cleared.

(6)

Slue-up or slue-down output data is supplied to the stepping motor
every 4-step.

(7)

To implement (6), a test is performed to determine if the 4-step output
is supplied within the same timing. Then, outputs are supplied in
the sequence of slue-up, operating and slue-down.
Normal/reverse slue is tested and if it is reverse, output for backlash
is provided.

(8)

Timing data for slue-up and slue-down should be set in the data table
in advance.

HITACHI 169

Progrqm Module Name:
Generate Stepping Motor Output

!-ICU: HMCS402C/
HMCS404C/HMCS408C

I~

SMREV

Flowchart:

I -_ _...,-_ _...J - - - - [

Clear timer B interrupt request flag

Save registers

.-_ _......._ _., -----[ Update the timer interrupt pedod

to the

to the stepping motor

Decrement cou~ter indicating output
to the stepping motor in 4 steps

_____ [ Test if 4-step outputs are given to the
stepping motor
o=SCNTR

170 HITACHI

Program Module Name:
Generate Stepping Motor Output

MCU: HMCS402C/
HMCS404C/HMCS408C

IL.bel'

SMREV

Flowchart:

____ [ Initialize counter indicating output
to the stepping motor in 4 steps

O+HSUP
- - - { Te,t if ,'ue-up output i , completed

O+LSUP

Decrement counter indicating output
slue-up data

HITACHI 171

Program Module Name:
Generate Stepping Motor Output

MCU: HMCS402C/
HMCS404C/HMCS408C

I~l'

SMREV

Flowchart:

Set timing for next slue-up output

172 HITACHI

Program Module Name:
Generate Stepping Motor Output

MCU: HMCS402C/
HMCS404C/HMCS408C

I~

SMREV

~----------'

Flowchart:

Test if steady state output is
[ terminated (Output of the remaining
o#STEP
- - - - step count from the total step count to
o~STEPE
be processed divided by 4)

- - - - [ 'toee .teady otate output

pulse rate output is
Oil,SIDID

SMREV7

Decrement counter indicating operating
pulse rate output

HITACHI 173

Program Module Name:
Generate Stepping Motor Output

MCU: HMCS402C/
HMCS404C/HMCS408C

I~

SMREV

Flowchart:

- - - - [ Test if slue-down output is completed

Decrement counter indicating slue-down
output

Initialize timing for the next slue-down
output

174 HITACHI

Program Module Name:
Generate Stepping Motor Output

MCU: HMCS402C/
HMCS404C/HMCS408C

I~

SMREV

Flowchart:

- - - {

Test if backlash processing is needed

- - - {

Te rmina te ou tpu t to the stepp ing motor

...-_ _J...._ _. , - - - {

Load ouepue for backlaoh pr=ming

or reverse slue data for
motor

Restore register

HITACHI 175

8.4

SUBROUTINE DESCRIPTION

~~

Calculate __
Normal/Reverse
Rotation
HMCS404C/HMCS408C
_s_u_b_r_o_u_t_i_n_e
N_am
__e__
: ____________________
-J L.M_C_U
__:_HM
__C_S_4_0__
2C_/______
.. Data

lL_a_b_e_l__
: __S_MF
__R
______

Function:
Tests whether slue flag (FRFLG(RAM» is normal or reverse, stores data for the
next stepping motor output in PBSM(RAM) •

Basic Operation:
Tests whether slue is normal or reverse, and then performs shift.
As a result, output data for one-step normal/reverse slue is obtained.
Program Module Using This Subroutine: SMCLC, SMREV
Flowchart:

Test if slue is normal or reverse

If normal, store data for the next
stepping motor output

If reverse, store data for the next
stepping output

176 HITACHI

~

8.5

PROGRAM LISTING

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
0003B
00039
00040
00041
00042
00043
00044
00045
OD046
00047
0004B
00049
00050
00051
00052
00053
00054
00055
00056
00057

207

0000

SOURCE STATEMENTS
LLEN
TITLE

*
****
*PBSM
LTLRD
HTLRD
LDDTA
HDDTA
LUDTA
HUDTA
FRFLG
SMSF
LSUP
HSUP
LCMD
HCMD
LAUG
HAUG
STEPL
STEPU
LMIN
HMIN
LSTEPW
HSTEPW
SDWNW
SOWN
LSHoLD
HSHoLD
LADD
HADD
LCMT
HCMT
LSU8
HSUB
LSHR
HSHR
SCNTR
STEPE
XSFT
YSFT
BASFT
XCMD
XCMT
YCMT
BACMT

*
*TMB

****

IFTB
IMTB
IE
TLRL
TLRU
PBDTR

132
STEPPING MOTOR CONTROL

RAM ALLOCATION
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

****************************************

$030
$031
$032
$033
$034
$035
$036
0.$037
2.$037
$038
$039
$03A
$03B
$03C
$03D
$03E
$03F
$040
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
S04E
S04F
$050
$051
$4
$F
$D
$3
$4
$8
$9

SYMBOL DEFINITIONS
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$009
0.$002
1.$002
0.$000
$OOA
$OOB
$6

WORK AREA FOR PBDTR
LOWER WORK AREA FOR TLR
UPPER WORK AREA FOR TLR
LOWER WORK AREA FOR TLR DOWN
UPPER WORK AREA FOR TLR DOWN
LOWER WORK AREA FOR TLR UP
UPPER WORK AREA FOR TLR UP
FORWARD OR REVERSE FLAG
STEPPING MOTOR START FLAG
LOWER SLUE-UP NUM8ER
UPPER SLUE-UP NUMBER
LOWER FIRST VALUE
UPPER FIRST VALUE
LOWER AUGEND
UPPER AUGEND
LOWER STEP NUMBER
UPPER STEP NUMBER
LOWER MINUEND
UPPER MINUEND
LOWER WORK FOR SUP
UPPER WORK FOR SUP
WORK FOR SDWN
SLUE DOWN NUMBER
LOWER OPERATING NUMBER
UPPER OPERATING NUMBER
LOWER ADDEND
UPPER ADDEND
LOWER SECOND VALUE NUMBER
UPPER SECOND VALUE NUM8ER
LOWER SUBTRAHEND
UPPER SUBTRAHEND
LOWER 8-BIT BINARY
UPPER 8-BIT BINARY
4 STEPS COUNTER
STEP-EXTRA NUMBER
8-BIT BINARY DATA ADDR(X)
8-BIT BINARY DATA ADDR(Y)
B-BIT BINARY DATA BRANCH ADDR(Y)
FIRST VALUE ADDR(X)
SECOND VALUE ADDR(Y)
START ADDR(Y) OF FIRST & SECOND VALUE
BRANCH ADDR(Y) OF FIRST & SECOND VALUE
************************************

TIMER MODE REGISTER 8
TIMER B INTERRUPT REQUEST 8IT
TIMER 8 INTERRUPT MUSK 8IT
INTERRUPT ENABLE BIT
LOWER TIMER LOAD REGISTER
UPPER TIMER LOAD REGISTER
R(6) PORT TO STEPPING MOTOR

HITACHI 177

00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114

****************************************************************

',."
,.

',."

VECTOR ADDRESSES

****************************************************************'"

150
150
150
150
150
000
000
150

010
010
010
010
120
010

0000
0002
0004
0006
0008
OOOA
0008
OOOC

'"
'"

ORG

$0000

JMPL
JMPL
JMPL
JMPL
JMPL
NOP
NOP
JMPL

SMMN
SMMN
SMMN
SMMN
SMREV

RESET
INTO
INTl
TIMER-A
TIMER-B

SMMN

SERIAL

,.****************************************************************,.
MAIN PROGRAM : SMMN
,.,.
,.,.
,.****************************************************************

OFO
239
206
180
18A
1A8
189
184
188
lAC
1A8
lAB
1A2
1A1
lAO
1A3
lAO
160
331

030
037
009
002
000
037
03F
03E
032
031
036
035
034
033
032

178 HITACHI

0010
0011
0012
0013
0015
0017
0019
0018
OOlD
001F
0021
0023
0025
0027
0029
002B
0020
002F
0031

SMMN

PEND

ORG

$0010

LWI
LAI
LRA
XMAD
REMD
LMID
REMD
SEMD
REMD
LMID
LMID
LMID
LMID
LMID
LMID
LMID
LMID
CALL
BR

$0
$9
PBDTR
PBSM
SMSF
$B.TMB
IMTB
IE
FRFLG
$C.STEPU
$8.STEPL
$B.HTLRD
$2.LTLRD
$1. HUDTA
$O.LUDTA
$3.HDDTA
$O.LODTA
SMCLC
PEND

INITIALIZE W REGISTER
INITIALIZE WORK AREA FOR PBOTR
INITIALIZE PBDTR
INITIALIZE SMSF
INITIALIZE TMB
INITIALIZE IMTB
ENABLE INTERRUPT
LOAD ARGUMENT
STORE ARGUMENT OF 200 STEP
INITIALIZE WORK AREA FOR TLR
LOAD SLUE-UP ADDRESS
LOAD SLUE-DOWN ADDRESS
CALCULATE SLUE DATA
END OF PROGRAM

,.

****************************************************************,.

,.

NAME : SMCLC (PROCESS DATA)
,.
,.
,.
****************************************************************
,.
,.
,.
,.
ENTRY
STEPU (UPPER NUMBER OF STEPS)

,.
,.
,.
,.
,.
,.

,.

RETURNS

STEPL (LOWER NUMBER OF STEPS)
FRFLG (l:FORWARD SLUE.O:REVERSE SLUE>
HSUP
(UPPER SLOW-UP DATA)
LSUP
(LOWER SLOW-UP DATA)
HSHOLD (UPPER OPERATING DATA)
LSHOLD (LOWER OPERATING DATA)
SDWN (SLOW-DOWN DATA)

,.

,.
,.
,.

,.
,.

00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171

STEPE (REMAINDER OF STEP)
FRFLG (FORWARD/REVERSE SLUE FLAG)
SMSF (SLUE START FLAG)

*
*
*
18C
340
231
OEC
118
194
230
118
194
233
19C
194
201
190
194
190
194
34F
160
190
194
190
194
120
367
133
367
132
170
131
3F3
3EB
1A4
lAO
lAO
1A2
190
281
194
190
194
190
194
lAO
lA4
381
160
190
194
190
194
190

037

03E
03E
03F
03F
03E
051
03E
04E
03F
04F
216
04E
03E
04F
03F
03F
03E
03E
101
03E
050
044
043
042
044
044
043
030
042
03C
049
048
233
030
043
03C
042
03F

0032
0034
0035
0036
0037
0039
0038
003C
003E
0040
0041
0043
0045
0046
0048
004A
004C
004E
004F
0051
0053
DOSS
0057
0059
0058
005C
DOSE
005F
0061
0063
0065
0066
0067
0069
006B
0060
006F
0071
0072
0074
0076
0078
007A
007C
007E
0080
0081
0083
0085
0087
0089
008B

*
*
*
******************************************************************

SMCLC

SMCLl

SMCL2

SMCL3
SMCL4

SMCL5

TMD
8R
LAI
REC
AMCD
LMAO
LAI
AMCD
LMAD
LAI
ANMD
LMAD
L8I
LAMD
LMAD
LAMD
LMAD
8RS
CALL
LAMD
LMAD
LAMD
LMAD
INEMD
8RS
ILEMD
8RS
ILEMD
BRS
ILEMD
BRS
BRS
LMID
LMID
LMID
LMID
LAMD
AI
LMAD
LAMD
LMAD
LAMD
LMAD
LMID
LMID
BRS
CALL
LAMD
LMAD
LAMD
LMAD
LAMD

FRFLG
SMCLI
$1

STEPL
STEPL
$0
STEPU
STEPU
3
STEPL
STEPE
1
STEPL
LSHR
STEPU
HSHR
SMCL2
SHR
LSHR
STEPL
HSHR
STEPU
O.STEPU
SMCL3
3.STEPL
SMCL3
2.STEPL
SMCLlS
1.STEPL
SMCLl2
SMCLll
4.SCNTR
O.SDWNW
O.HSTEPW
2.LSTEPW
SDWNW
1
SDWNW
HSTEPW
HAUG
LSTEPW
LAUG
O.HADD
4.LADD
SMCL5
ADD
HAUG
HSTEPW
LAUG
LSTEPW
STEPU

TEST IF FORWARD OR REVERSE SLUE
IF REVERSE INCREMENT STEP

STORE 1/4 TIME OF STEP
SET STEP-EXTRA DATA
SET SHIFT COUNTER
SET LOWER STEP
SET UPPER STEP
CALCULATE 1/4 TIME OF STEP
SET 1/4 TIME OF STEP

BRANCH IF HSTEP=/O
LOWER STEP DATA)-3?
BRANCH IF STEP)=3
LOWER STEP DATA)=2?
BRANCH IF STEP=2
LOWER STEP DATA)-l?
BRANCH IF STEP-I
BRANCH IF STEP=O
LOAD 4 INTO SCNTR
CLEAR WORK AREA FOR Sl.UE-DoWN
STORE SLUE-DOWN DATA
INCREMENT SLUE-DOWN WORK
LOAD DATA FOR JUDGING

HITACHI 179

00172
00173
00174
00175
00176
00177
00178
00179
00180
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
0019B
00199
00200
00201
00202
00203
00204
00205
00206
00207
00208
00209
00210
00211
00212
00213
00214
00215
00216
00217
0021B
00219
00220
00221
00222
00223
00224
00225
00226
00227
00228

194
190
194
lAl
1AE
398
160
170
190
194
190
194
190
194
190
194
160
048
2BO
36F
2B1
3B6
2B2
170
lAO
lAO
190
194
190
194
190
194
lAO
190
194
160
190
194
190
194
160
lAO
1A1
160
190
194
190
194
160
IB6
010
190
194
lAO
150
1A4
lAO

041
03E
040
040
04C

0080
008F
0091
0093
0095
0097
241 0098
109 009A
043 009C
038 009E
042 OOAO
03A 00A2
03F 00A4
04B 00A6
03E 00A8
04A OOAA
221 OOAC
OOAE
OOAF
OOBO
0081
00B2
00B3
127 00B4
047 00B6
046 OOBB
044 OOBA
045 OOBC
03F OOBE
041 OOCO
03E 00C2
040 00C4
040 00C6
044 00C8
04C OOCA
241 OOCC
047 OOCE
040 0000
046 00D2
04C 0004
241 0006
040 0008
04C OODA
241 OODC
041 OODE
039 OOEO
040 00E2
03B 00E4
1FB 00E6
037 00E8
OOEA
051 OOEB
050 OOED
051 OOEF
OF5 00F1
050 oon
047 00F5

180 HITACHI

SMCL6
SMCL7

SMCL8
SMCL9

SMCLlO
SMCLll

SMCLl2
SMCLl3

LMAD
LAMD
LMAD
LMID
LMID
BRS
CALL
8RS
LAMD
LMAD
LAMD
LMAD
LAMD
LMAD
LAMD
LMAD
CALL
LAB
ALEI
BRS
ALE I
BRS
ALEI
BRS
LMID
LMID
LAMD
LMAD
LAMD
LMAD
LAMD
LMAD
LMID
LAMD
LMAD
CALL
LAMD
LMAD
LAMD
LMAD
CALL
LMID
LMID
CALL
LAMD
LMAD
LAMD
LMAD
CALL
SEMD
RTN
LAMD
LMAD
LMID
JMPL
LMID
LMID

HMIN
STEPL
LMIN
1. HSUB
SE.LSUB
SMCL6
SU8
SMCLl6
HSTEPW
HCMD
LSTEPW
LCMD
STEPU
HCMT
STEPL
LCMT
CMP
0
SMCL4
1
SMCL8
2
SMCLl7
O.HSHOLD
O.LSHOLD
SDWNW
SOWN
STEPU
HMIN
STEPL
LMIN
O.HSUB
SDWNW
LSUB
SUB
HSHOLO
HSUB
LSHOLD
LSUB
SUB
O.HSUB
1. LSUB
SUB
HMIN
HSUP
LMIN
LSUP
SMFR
SMSF
STEPE
SCNTR
O.STEPE
SMCLl3
4.SCNTR
O.HSHOLD

1/4

STEP = 30 ?

BRANCH IF 1/4 STEP > 30
1/4 STEP = 2+4N (N=1-26) ?

BRANCH IF STEPW

1/4 STEP

BRANCH IF STEPW

1/4 STEP

DEFINE OPERATING DATA AS 0
LOAD SLUE-DOWN DATA
SLUE-UP DATA = 1/4 STEP - (SDWNW+OPERATING DATA+1)

(STEP-SOWN)

(STEP-SDWNW-SHOLD)
(STEP-SDWNW-SHOLD-1)

SET FORWARD OR REVERSE DATA
START STEPPING MOTOR
DEFINE STEPE AS OPERATING NuMBER
LOAD 4 INTO SCNTR
LOAD 0 INTO OPERATING DATA

00229
00230
00231
00232
00233
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
00248
00249
00250
00251
00252
00253
00254
00255
00256
00257
00258
00259
00260
00261
00262
00263
00264
00265
00266
00267
00268
00269
00270
00271
00272
00273
00274
00275
00276
00277
00278
00279
00280
00281
00282
00283
00284
00285

lAO
lAO
lAO
lAO
150
1A4
lAO
1A1
150
190
194
190
194
1A1
lAD
160
190
194
190
194
1Al
lAS
1A7
150
lAO
1Al
150

046
039
038
045
OE6
050
047
046
OF9
03F
041
03E
040
04D
04C
241
041
047
040
046
039
038
045
OE6
047
046
OBA

188 002
2F4
048
2F5
068
2F6
058
2F7
001
068
2F8
OAF
2F9

00F7
00F9
OOFB
OOFD
DOFF
0101
0103
0105
0107
0109
010B
010D
010F
0111
0113
0115
0117
0119
011B
011D
OllF
0121
0123
0125
0127
0129
0128

0120
012F
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
013A

LMID
O,LSHOLD
O,HSUP
LMID
SLUE-UP DATA = 0
LMID
O,LSUP
LMID
O,SDWN
SLUE-DOWN DATA
OWN
JMPL
SMCLlO
SMCLl5
4,SCNTR
LMID
O,HSHOLD
LMID
LOAD 4 INTO SCNTR
LMID
1,LSHOLD
DEFINE OPERATING DATA AS 1
JMPL
SMCLl4
SMCLl6
LAMD
STEPU
LOAD FETCH DATA
LMAD
HMIN
LAMD
STEPL
LMAD
LMIN
LMID
1. HSUB
SD,LSUB
LMID
STEP - 29
CALL
SUB
LAMD
HMIN
LMAD
HSHOLD
LAMD
LMIN
LMAD
LSHOLD
SET SLUE UP DATA
LMID
1. HSUP
LMID
5,LSUP
7,SDWN
LMID
SET SLUE DOWN DATA
JMPL
SMCLlO
SMCLl7
LMID
0, HSHOLD
DEFINE OPERATING DATA AS 1
1,LSHOLD
LMID
JMPL
SMCL9
****************************************************************
SMCL14

"
"
NAME : SMREV (GENERATE STEPPING MOTOR OUTPUT)
"
"
"****************************************************************"
"
ENTRY : HSUP (UPPER SLOW-UP DATA)
"
""
LSUP (LOWER SLOW-UP DATA)
"
HSHOLD (UPPER OPERATING DATA)
"
"
LSHOLD (LOWER OPERATING DATA)
"
"
SDWN (SLDW-DOWN DATA)
"
"
STEPE (REMAINDER OF STEP)
"
"
FLAG)
FRFLG (FORWARD I REVERSE SLUE
"
"*
SMSF (SLUE START FLAG)
"
RETURNS : SMSF (SLUE START FLAG)
"
"
"
"
****************************************************************
SMREV

REMD
XMRA
LAB
XMRA
LASPX
XMRA
LASPY
XMRA
XSPX
LASPX
XMRA
LAY
XMRA

IFTB
4

CLEAR TIMER-B INTERRUPT REQUEST BIT
SAVE A

5

SAVE B

6

SAVE SPX

7

SAVE SPY

8

SAVE X

9

SAVE Y

HITACHI 181

002B6
002B7
002B8
00289
00290
00291
00292
00293
00294
00295
00296
00297
00298
00299
00300
00301
00302
00303
00304
00305
00306
00307
00308
00309
00310
00311
00312
00313
00314
00315
00316
00317
00318
00319
00320
00321
00322
00323
00324
00325
00326
00327
0032B
00329
00330
00331
00332
00333
00334
OD335
00336
00337
00338
00339
00340
00341
00342

190
194
190
194
18E
347
371
190
2D6
231
OEF
198
194
120
36E
1A4
120
37F
120
37F
120
384
120
38C
120
3BC
120
3D4
1BC
3F7
1A1
184
36F
160
2F9
OD8
2F8
OEB
003
2F7
ODB
2F6
OEB
003
2F5
OCB
2F4
011
190
194
190
194
lAO
1A1
160
190
194

031
OOA
032
OOB
037
030

050
050
050
050
039
038
051
047
046
045
037
050
037
1FB

039
041
038
040
04D
04C
241
041
039

182 HITACHI

013B
013D
013F
0141
0143
0145
0146
0147
0149
014A
014B
014C
014E
0150
0152
0153
0155
0157
0158
015A
015B
015D
015E
0160
0161
0163
0164
0166
0167
0169
016A
016C
016E
016F
0171
0172
0173
0174
0175
0176
0177
0178
0179
017A
0178
017C
017D
017E
017F
0181
0183
01B5
01B7
0189
01B8
018D
018F

SMREV1

SMREV2
SMREV3
SMREV4

SMREV5

LAMD
LMAD
LAMD
LMAD
TMD
BRS
BRS
LAMD
LRA
LAI
SEC
SMCD
LMAD
INEMD
BRS
LMID
INEMD
8RS
INEMD
BRS
INEMD
BRS
INEMD
BRS
INEMD
BRS
INEMD
BRS
TMD
BRS
LMID
SEMD
BRS
CALL
XMRA
LYA
XMRA
LXA
XSPXY
XMRA
LYA
XMRA
LXA
XSPXY
XMRA
L8A
XMRA
RTNI
LAMD
LMAD
LAMD
LMAD
LMID
LMID
CALL
LAMD
LMAD

LTLRD
TLRL
HTLRD
TLRU
SMSF
SMREV1
SMREV4
PBSM
P8DTR
1
SCNTR
SCNTR
O. SCNTR
SMREV2
4.SCNTR
O.HSUP
SMREV5
O.LSUP
SMREV5
O.STEPE
SMREV6
O.HSHOLD
SMREV7
O.LSHOLD
SMREV7
O.SDWN
SMREV8
FRFLG
SMREV9
1. SCNTR
FRFLG
SMREV3
SMFR
9

REINITIALIZE TIMER INTERRUPTS
TEST IF DRIVE MOTOR
8RANCH IF SMSF = 1
BRANCH IF SMSF = 0
DRIVE STEPPING MOTOR

DECREMENT EVERY 4 STEPS
OUTPUT 4 STEPS 7
8RANCH IF SCNTR =/ 0
INITIALIZE COUNTER EVERY 4 STEPS
SLUE-UP COMPLETE

TEST IF OPERATING COMPLETED
TEST IF SLUE-DOWN COMPLETED

SET FORWARD DR REVERSE DATA
RESTORE REGISTERS

8
7
6
5
4
HSUP
HMIN
LSUP
LMIN
0.HSU8
I.LSUB
SU8
HMIN
HSUP

DECREMENT SLUE-UP COUNTER

SUP - 1

00343
00344
00345
00346
00347
00348
00349
00350
00351
00352
00353
00354
00355
00356
00357
00358
00359
00360
00361
00362
00363
00364
00365
00366
00367
00368
00369
00370
00371
00372
00373
00374
00375
00376
00377
00378
00379
00380
00381
00382
00383
00384
00385
00386
00387
00388
00389
00390
00391
00392
00393
00394
00395
00396
00397
00398
00399

190
194
190
OC8
194
190
194
IBF
194
048
194
lAO
lAl
160
190
194
190
194
150
190
194
lAO
150
190
194
190
194
lAO
lAl
160
190
194
190
194
150
231
OEF
198
194
190
194
190
194
lAO
190
194
160
190
OC8
190
18F
194
048
194
150
18A
150

040
038
036
030
035
03C
031
032
049
048
233
030
036
03C
035
16E
051
050
051
16E
047
041
046
040
040
04C
241
041
047
040
046
16E
045
045
034
030
033
03C
049
045
048
233
03D
03C
031
032
16E
037
171

0191
0193
0195
0197
0198
019A
019C
019E
019F
OlAl
01A2
01A4
01A6
01A8
OlAA
OlAC
OlAE
OlBO
0182
0184
0186
0188
018A
018C
018E
OlCO
01C2
01C4
01C6
01C8
01CA
OlCC
OlCE
0100
01D2
0104
0105
0106
0108
01DA
OlOC
OlOE
OlEO
01E2
01E4
01E6
01E8
OlEA
01EC
OlEO
01EF
01FO
01F2
01F3
01F5
01F?
01F9

SMREV6

SMREV7

SMREV8

SMREV9

LAMD
LMAD
LAMD
LBA
LMAD
LAMD
LMAD
P
LMAD
LAB
LMAD
LMID
LMID
CALL
LAMD
LMAD
LAMD
LMAD
JMPL
LAMD
LMAD
LMID
JMPL
LAMD
LMAD
LAMD
LMAD
LMID
LMID
CALL
LAMD
LMAD
LAMD
LMAD
JMPL
LAI
SEC
SMCD
LMAD
LAMD
LMAD
LAMD
LMAD
LMID
LAMD
LMAD
CALL
LAMD
L8A
LAMD
P
LMAD
LA8
LMAD
JMPL
REMD
JMPL

LMIN
LSUP
HUDTA

SET TIMING FOR NEXT SLUE-UP

HAUG
LUDTA
LAUG
SF
LTLRD

STORE LOWER WORK FOR TLR

HTLRD
O.HADD
1. LADD
ADD
HAUG
HUDTA
LAUG
LUDTA
SMREV2
STEPE
SCNTR
O.STEPE
SMREV2
HSHOLD
HMIN
LSHOLD
LMIN
0.HSU8
1.LSU8
SU8
HMIN
HSHOLD
LMIN
LSHOLD
SMREV2
1
SOWN
SOWN
HDDTA
HAUG
LDDTA
LAUG
O.HADD
SDWN
LADD
ADD
HAUG

INCREMENT UDTA

SET FOR OPERATING

DECREMENT OPERATING COUNTER

DECREMENT SLUE-DOWN COUNTER
SET TIMING FOR NEXT SLUE-DOWN

DDTA + SOWN

LAUG
SF
LTLRD
HTLRD
SMREV2
SMSF
SMREV4

STOP DRIVING STEPPING MOTOR

HITACHI 183

00400
00401
00402
00403
00404
00405
00406
00407
00408
00409
00410
00411
00412
00413
00414
00415
00416
00417
00418
00419
00420
00421
00422
00423
00424
00425
00426
00427
00428
00429
00430
00431
00432
00433
00434
00435
00436
00437
00438
00439
00440
00441
00442
00443
00444
00445
00446
00447
00448
00449
00450
00451
00452
00453
00454
00455
00456

....
...****************************************************************
NAME : SMFR (CALCULATE NORMAL/INVERSE ROTATION
.
..
DATA)
18C
190
30B
DEC
OA1
180
06F
307
010
184
150
OEC
DAD
180
06F
312
306
187
150

037
030

030

030
206
030

030
206

01F8
01FD
01FF
0200
0201
0202
0204
0205
0206
0207
0209
020B
020C
0200
020F
0210
0211
0212
0214

****************************************************************
TMD
FRFLG
NORMAL OR INVERSE ROTATION ?

SMFR

SMFR1
SMFR2
SMFR3

SMFR4

....
..

LAMD
BRS
REC
ROTL
XMAD
TC
BRS
RTN
SEMD
JMPL
REC
ROTR
XMAO
TC
BRS
BRS
SEMD
JMPL

P8SM
SMFR3
PBSM

BRANCH IF FRFLG=l
IF INVERSE. SET DATA FOR NEXT OUTPUT

SMFR2
$O.PBSM
SMFRl

IF NORMAL. SET DATA FOR NEXT OUTPUT

P8SM
SMFR4
SMFRl
$3.P8SM
SMFRl

.....

****************************************************************

224
21F
DEC
090
DAD
ODD
070
319
OCF
317
010

0216
0217
0218
0219
021A
021B
021C
0210
021E
021F
0220

223
001
224
21B
200
091
014
32A
332
004
331
001

0221
0222
0223
0224
0225
0226
0227
0228
0229
022A
022B
022C

184 HI1'A'CHI

NAME : SHR (SHIFT 8-BIT DATA)

****************************************************************

SHR
SHRl

SHR2

LXI
LYI
REC
LAM
ROTR
LMADY
YNEI
BRS
DB
BRS
RTN

XSFT
YSFT

BASFT
SHR2
SHRl

LOAD ADDR(X)
LOAIll ADDR(Y)

LOAD BINARY DATA
ROTATE BINARY DATA
STORE SHIFT DATA AND DECREMENT ADDR(Y)
DECREMENT SHIFT COUNTER
BRANCH UNTIL SHIFT COUNTER

= $0

...
...****************************************************************
NAME : CMP (COMPARE 8-BIT BINARY DATA)
.
..
****************************************************************

CMP

CMPl

CMP2

LXI
XSPX
LXI
LYI
LBI
LAMX
ALEM
BRS
8RS
ANEM
BRS
XSPX

XCMD

LOAD FIRST VALUE ADDR(SPX)

XCMT
YCMT
$0

LOAD SECOND VALUE NUMBER AOOR(X)
LOAD SECOND VALUE NUMBER ADDR(Y)
CLEAR B
LOAD SECOND VALUE
DETERMINE RELATION
BRANCH IF A <= M
BRANCH IF A ) M
TEST IF A = M
BRANCE IF A = M
LOAD SECOND VALUE ADDR(X)

CMP2
CMP4
CMP3

00457
00458
00459
00460
00461
00462
00463
00464
00465
00466
00467
00468
00469
00470
00471
00472
00473
00474
00475
00476
00477
00478
00479
00480
00481
00482
00483
00484
00485
00486
00487
00488
00489
00490
00491
00492
00493
00494
00495
00496
00497
00498
00499
00500
00501
00502
00503
00504
00505
00506
00507
00508
00509
00510
00511
00512
00513

ODF
079
326
04C
04C
010

022D
022E
022F
0230
0231
0232

CMP3
CMP4

DY
YNEI
BRS
IB
IB
RTN

8ACMT
CMP1

DECREMENT ADDR(y)
TEST LOOP COUNTER
INCREMENT B (RESULT>
INCREMENT B (RESULT)

****************************************************************

*
*
OEC
190
118
194
190
118
194
010

048
03C
03C
049
030
03D

0233
0234
0236
0238
023A
023C
023E
0240

NAME

:

ADD (ADD 8-BIT BINARY DATA)

*
*

*
****************************************************************

ADD

REC
LAMD
AMCD
LMAD
LAMO
AMCD
LMAD
RTN

LADD
LAUG
LAUG
HADD
HAUG
HAUG

CLEAR CARRY FLAG
LOAD LOWER ADDEND
ADD LOWER ADDEND TO LOWER AUGEND
STORE LOWER ADDITION RESULT
LOAD UPPER ADDEND
ADO UPPER ADDEND TO UPPER AUGEND
STORE UPPER ADDITION RESULT

****************************************************************

NAME : SU8 (SUBTRACT 8-BIT BINARY DATA)
OEF
190
198
194
190
198
194
010

04C
040
040
04D
041
041

0241
0242
0244
0246
0248
024A
024C
024E

*
*

*****************************************************************
SU8

SEC
LAMD
SMCD
LMAD
LAMD
SMCD
LMAD
RTN

LSU8
LMIN
LMIN
HSUB
HMIN
HMIN

SET CARRY FLAG
LOAD LOWER SU8TRAHEND
SU8TRACT LOWER SUBTRAHEND FROM LOWER MINUEND
STORE LOWER SUBTRACTION RESULT
LOAD UPPER SUBTRAHEND
SUBTRACT UPPER SUBTRAHEND FROM UPPER MINUEND
STORE UPPER SUBTRACTION RESULT

****************************************************************

*

*

SLUE-UP DATA TABLE
*
******************************************************************

1B7
1BC
1CO
1C4
1C7
1CA
1CD
1CF
lDl
103
105
107
1D8
IDA
lOB
lOC
lOE

OF 10
OF 11
OF12
OF13
OF14
OFl5
OF16
OF17
OFl8
OF19
OFlA
OF1B
OFlC
OF 10
OF1E
OF1F
OF20

ORG

$OF10

DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC

$lB7
$lBC
$lCO
$lC4
$lC7
$lCA
$lCD
$lCF
$101
$lD3
$105
$lD7
$lD8
$lOA
$lOB
$lDC
$lOE

215PPS
230PPS
245PPS
260PPS
275PPS
290PPS
305PPS
320PPS
335PPS
350PPS
365PPS
380PPS
395PPS
410PPS
425PPS
440PPS
455PPS

HITACHI 185

00514
00515
00516
00517
00518
00519
00520
00521
00522
00523
00524
00525
00526
00527
0052B
00529
00530
00531
00532
00533

1DF
lEO
1E1
1E2

OF21
OF22
OF23
OF24

DC
DC
DC
DC

SlDF
SlEO
$lE1
SlE2

470PPS
485PPS
500PPS
515PPS

****************************************************************

1B2
1CO
1CA
101
107
lOB
1DF

186 HITACHI

OF30
OF31
OF32
OF33
OF34
OF35
OF36

*
*
SLUE-DOWN DATA TABLE
*
*
******************************************************************
*
ORG
SOF30
*
DC
SlB2
200PPS
DC
DC
DC
DC
DC
DC
END

SlCO
SlCA
$101
$107
SlOB
$lDF

245PPS
290PPS
335PPS
3BOPPS
425PPS
470PPS

SECTION 9.

9.1

USE OF COMMERCIAL KEYBOARDS

HARDWARE DESCRIPTION

9.1.1

Function
Receives key data from a standard ASCII keyboard.

9.1.2

Microcomputer Operation
The HMCS404C accesses data from an ASCII keyboard using a First
In-First Out roll buffer.

Port R is selected to perform parallel

handshaking between the INTl pin and port R.

Input data is read at

the falling edge of the STROBE signal and data is written to the
roll buffer by input strobe interrupt.

9.1.3

Peripheral Devices
ASCII keyboard:

Outputs ASCII codes and STROBE signal.

HITACHI 187

9.1.4

Circuit Diagram
The interface circuit for reading data from an ASCII keyboard is shown
in Fig. 9.1.

MCV

+5V

HMCS+O'C

(~~g;!~:g)
so TEST

+L

+5V

vee

r----182076

ro- I:>.. HD7~e14

lOO]Ql

,!

c:
.><

g

v

lO~F

v

I:>.

49

IY

RESET

:=
22pF

"

51

P"'9~L

ascl
OSC2

22pF

~

GND

R"
R"
R,.
R.,
SO/R 42

SIIR"

SCK/R40
Ru/ I NTI

.
...
2.

2.
3.

""
28

I
STROBE

I
B 1 B2 BSBt.B,B,B.,

;1 1
I

I I II

I I

ASCII Keyboard

Fig. 9.1.

188 HITACHI

Reading Data from ASCII Keyboard

•

9.1.5

Pin Functions
Pin functions at the interface between the HMCS404C and ASCII keyboard
are shown in Table 9.1.

Table 9.1.

Pin Functions

Pin Name
(HMCS404C)

Input/
Output

Active
Level
(High
or Low)

R33/INTl

Input

Low

Input

Function
STROBE signal

Pin Name
(Keyboard)

Key data input signal

Input
Input
Input
R50

Input
Input
Input

9.1.6

Hardware Operation
The timing chart for the ASCII keyboard is shown in Fig. 9.2.

If a

key in ASCII keyboard is depressed, data and STROBE signal are output
as shown in Fig. 9.2.

ASCII keyboard
pin names
key data (Port R)
STROBE signal

~<,------,)r----

(INTl)--------------~~

I

CD
INTI interrupt generated

Fig. 9.2.

ASCII Keyboard Timing Chart

HITACHI 189

9.2

SOFTWARE DESCRIPTION

9.2.1

Program Module Configuration
The program module configuration for reading key data from ASCII
keyboard is shown in Fig. 9.3.

KEYMN

Main
Program

K EYIN

I

Receive
Key Data

KEYOUT

L.:.

Fig. 9.3.

9.2.2

~

Read
Key Data

TPR

L:.

I

Convert
ASCII

l2.

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 9.2.

Table 9.2.

Program Module Functions

No.

Program Module Name

Label

Function

0

Main Program

KEYMN

Receives key data from ASCII keyboard

1

Receive Key Data

KEYIN

Receives key data and writes then to
roll buffer

2

Read Key Data

KEYOUT

Reads data in roll buffer

3

Convert ASCII

TPR

Converts ASCII lower case into
upper case.
(Refer to TPR in HMCS400 Series
Application Note (Software Edition)
for details)

190 HITACHI

9.2.3

Program Module Process Flow (Main Program)
The flowchart in Fig. 9.4 is an example of key data input from ASCII
keyboard performed by the program module in Fig. 9.4.

Main Program

- - - - [ Initialize W register

- - - {

Cleor pointer indieating key buffer

- - - - [ Select INTI input pin

- - - - [ Clear interrupt mask

- - - - [ Enable interrupts

----[Read key data in key buffer
____ [Test if data is not completed on the key
buffer
__ _ _ [ Exchange contents of Accumulator and B
register
Call TPR and convert small case letters
- - - - [ of ASCII into large case letters.
(Refer to TPR in HMCS400 Series Application Note (Software Edition) for details)

INTI interrupt routine

L-______~------~

___ [.Receive key data and write them to
roll buffer

Fig. 9.4.

Program Module Flowchart

HITACHI 191

9.3

PROGRAM MODULE DESCRIPTION

Program Module Name:
Receive Key Data

MCU: HMCS402C/
HMCS404C/HMCS408C

Label: KEYIN

Function:
Receives key data from ASCII key board and writes them to roll buffer.

Arguments:

Changes in CPU
Registers and Flags:

None

B

•

RAM (Digits):

X

Y

Stack (Digits):

x

x

SPX

Spy

x

•

•

1. Function Details
(1)
(2)

KEYIN has no arguments.
Example of KEYIN execution is
shown in Fig. 9.5. If A
in ASCII keyboard is pressed
as shown in part (j) of Fig.
9.5. key data is written to
key buffer as shown in part
@ of Fig. 9.5.

Specifications Notes:

192 HITACHI

= 10 bits

x

:

2
0

No. of cycles: 36
Reentrant: No
Relocatable: No
Interrupt OK?: No

•

Description:

1 word

ROM (Words): 35

A

W

x

Specifications:

CA

ST

x

x

Not Affected
Undefined
Result

Program Module Name:
Receive Key Data

MCU: HMCS402C/
HMCS404C/HMCS408C

Description:

[L.bel,

Press A
key

KEYIN

0

PS
PS($032) @]
PE
execution
PE($031) @]

Q) Before

---~MD. ($040)
**
* * * (Note)
~

**

MD($05Ff--

***

PS

PS ($ 032)

J

After
PE($031)
execution

~

Fig. 9.5.

(3)
2.

hl.!Ji]

**: hexadecimal
Example of Program Module
KEYIN Execution

KEYIN calls neither the program modules nor subroutines.

User Notes
(1)

Both KEYIN and KEYOUT must use the same roll buffer.

(2)

The following procedure must be performed before KEYIN execution.
(a)

3.

PE
m

f*1*I ---I*T;r;]MD ( $ 040)

MD ($05F)

Note:

[Q]

Selects Port Mode register as INTI.

(b)

Clears INTI interrupt mask bit.

(c)

Sets bit IE to enable INTI interrupt.

RAM Allocation

Fig. 9.6.

RAM Allocation

HITACHI 193

Program Module Name:
Receive Key Data

MCU: HMCS402C/
HMCS404C/HMCS408C

ILobel'

KEY IN

Description:

RAM

Label
b3

Description

bO

~
MD(S03l)

PE

b3

Ending pointer indicating key data is
set to end of key buffer

bO

~
MD(S032)

PS

MD(S04F)

Starting pointer indicating start address
of unprocessed key data in key buffer

MD(S040)

.~~~m
MD(S05F)

4.

MD(S050)

Sample Application

LMID

REMD

S.O, P S }
..................... Clear RAM to be used
SO, PE
S 8, PMR ..................... Initialize INTl
..................... Clear INTl interrupt mask
1Ml

SEMD

IE

LMID
LM1D

5.

Key buffer to which 16 bytes key data
will be set

..................... Enable interrupts

Basic Operation
(1)

Input/output to/from roll buffer.
(a)

Calls program module KEYIN at every INTl interrupt and stores key
data in key buffer. Then, calls program module KEYOUT in main
program and fetches key data from key buffer.

(b)

Clears starting pointer PS(RAM) and ending pointer PE(RAM) and
stores key data in key buffer starting address.

194 HITACHI

Program Module Name:
Receive Key Data

MCU: HMCS402C/
HMCS404C/HMCS408C

i
L

KEYIN
"""

Description:

(2)

(c)

Program module KEYIN stores 1 byte of key data in 16-byte buffer
area pointed by PE(RAM) , and increments PE(RAM).

(d)

Program module KEYOUT fetches 1 byte from l6-byte buffer area
pOinted by PS(RAM) and increments PS(RAM).

(e)

PS(RAM) and PE(RAM) become "0" if they are incremented till 15
bytes because the buffer area is l6-byte long.

Input to key buffer
(a)

Program module KEYIN loads PE(RAM) into Accumulator and
increments Accumulator. Then, compares Accumulator content
with PS(RAM). If (Accumulator) =PS (RAM) , key data is not stored
in key buffer.
If (Accumulator) ~ (PS) , key data is stored in key buffer and
PE(RAM) is incremented.

(b)

Key buffer can be used up to 15 bytes.

HITACHI 195

Program Module Name:
Receive Key Data

MCU: HMCS402C/
HMCS404C/HMCS408C

ILabe. 1:

KEYIN

~----------------~

Flowchart:

____ [ Clear interrupt request flag

Save Register

- - - -

[ Tee c if key buffe< io full

----l
196 HITACHI

Load end poince< inco Y  $A

$6
TPR3
$0
TPR2

END

.HITACHI 203

SECTION 10.
10.1

CLOCK SYNCHRONOUS SCI (EXTERNAL CLOCK)

HARDWARE DESCRIPTION

10.1.1

Function
(1)

Receives ASCII sent from master as clock synchronous serial data
using the HMCS404C, converts the received data from ASCII
lowercase into uppercase and sends it to the master system.

(2)

Converts ASCII lowercase into uppercase, if lowercase is
received.

(3)
10.1.2

Uses protocol in which data is sent from master system first.

Microcomputer Application
(1)

Transfers data to/from master system using clocked synchronous
serial communication interface (hereinafter, SCI).

(2)

Transfers data by sending master receives request to master
system and receiving transfer clock from master system using
port D.

(3)

Outputs port DO slave receives request signal and informs
data transfer to slave system.

10.1.3

Circuit Diagram
MCU
HMCS404C
( HMCS402C)
HMCS408C

+5V

50

TEST

+5V
+5V

32

1---'
I

Slave receives request signal
Master receives request signal

Vee

5
55

Iso

IMaster

35

I

u~~

..

I system::=O~----------------:3~·'l/sI
I
I

I
I

L ___ .J

Fig. 10.1.

204 HITACHI

SCI Serial Communication

request signal

10.1.4

Pin Functions
Pin functions at the interface between the HMCS404C SCI pins and
master system pins.

Table 10.l.

Pin Functions

Pin Name
(HMSC404C)

Input/
Output

Active
Level
(High
or Low)

R4 0/SCK

Input

Low

R4l/ SI

Pin Name
Function

[Master
System

1

Inputs transfer clock when
receiving/sending serial
data

Serial
clock

Input

Inputs serial data

Serial
data
output

R42/ S0

Output

Outputs serial data

Serial
data
input

Dl

Output

Low

Requests transfer clock to
output to master system

Master
receives
request
signal

DO

Input

Low

Inputs transfer clock
request from master system
and output clock if low

Slave
receives
request
signal

HITACHI 205

10.1.5

Hardware Operation
SCI timing chart is shown in Fig. 10.2.

Holds SRU:SRL data to be sent

~

Master receives
request signal (Dll

r--

~--------------------------------------~

~

Transfer

so

(\O~t Transfer

data to master system

Slave receives
request Signal(D~

r-

SCK
Receive

SI
Receives data
input latch
timing
Set IFS.

Fig. 10.2.

10.2

SCI Timing Chart

SOFTWARE DESCRIPTION

10.2.1

Program Module Configuration
The program module configuration for SCI communication with master
system is shown in Fig. 10.3.

SCISMN
Main
Program

~

1
TPR

S CISTR .1

SCI Slave
Receive/
Transfer

l2.

Fig. 10.3.

206 HITACHI

I

I!.

Convert ASCII
Lowercase into
Uppercase

Program Module Configuration

10.2.2

Program Module Functions
Program module functions are summarized in Table 10.2.

Table 10.2.

Program Module Functions

No.

Program Module Name

Label

Function

o

Main Program

SCISMN

Communicates with master system
using clocked synchronous interface
SCI

1

SCI Slave Receive/
Transfer

SCISTR

Receives data from master system
using external clock

2

Convert ASCII
Lowercase into
Uppercase

TPR

Converts ASCII lowercase into
uppercase.
(Refer to TPR in
HMCS400 Series Application Note
(Software Edition) for details)

.HITACHI207

10.2.3

Program Module Application (Main Program)
Flowchart in Fig. 10.3 is an example of receiving ASCII from master
system, converting ASCII lowercase into uppercase and sending it to
master system, performed by the program module in Fig. 10.3.
Main program

[Initialize W register

Initialize RAM to be used

- - - {

Initial ize Port DO

- - - - [ Initialize Port Dl

- - - { Select receive mode

- - - {select external clock

- - - { Clear SCI interrupt request flag

- - - {

Clear SCI interrupt mask

- - - { Enable interrupt

- - - { Start SCI

{

Fig. 10.4.

208 HITACHI

Test if data is received from master
system

Program Module Flowchart

- - - { Test if sending data

D.=O
{
>---...,---

Test if slave receive requested

___ {Load sending data into serial data
register

- - - - [ Select sending mode

- - - { Clear sending data flag

- - - { Set sending data flag

- - - { Master received request

::;::.----l---{

0

Test receiving complete flag

- - - { Set sending data flag

I--::-::-;:;~:;:=+::;:==~__J---{ Clear receiving complete flag
- - - { Load TPR antry arguman'

Fig. 10.4.

Program Module Flowchart (Cont)

HITACHI 209
---------------

-------

---

{

u-----r---~u

.--____.L....____. , - -

-{

Call TPR and convert ASCII lowercase
into uppercase.
(Refer to TPR in
HMCS400 Series Application Note
(Software Edition) for details)

Storo rot=n .r"""ont of TPR in RAM

SCI interrupt routine

___ {

Fig. 10.4.

210 HITACHI

Execute SCISTR and sending/receiving
data to/from master system

Program Module Flowchart (Cont)

10.3

PROGRAM MODULE DESCRIPTION

Program Module Name:
TRANSFER/RECEIVE

SCI SLAVE

Label:

MCU: HMCS402C/
HMCS404C/HMCS408C

SCISTR

Function:
(1)

Input serial clock and receives data from master system.

(2)

Permits outputting when slave system cannot output serial clock.

Arguments:
Contents

1 digit = 4 bits
Storage
No. of
Location Digits

Registers and Flags:
A

--

Entry

--

--

Returns

End of
received
data

SCI£~)
(RAM)
SCIMEF
(RAM)

X

Y

Stack (Digits) :

•

No. of cycles:

Relocatable:

•

•

1

CA

ST

•

x

x

:

No

Interrupt OK?:

1

a
20

No

Reentrant:

SPY

W

•

4

RAM (Digits) :

•

•
1

25

ROM (Words) :

x

•
SCISRV

1 word = 10 bits

B

SPX

Received
data

Specifications:

Changes in CPU

Yes

Not Affected
Undefined
Result

Description:
1. Function Details
(1)

CD

Input

Argument details
SCISRV (RAM): Contains data
SCISRL
sent from master
system.
SCIMEF (RAM): Indicates
existence of
received data.

bit 0

Return
argumen

t

SCIS!u):
SCISRL

1

bit 7

I

b7

~8I~~~:

l-byte datal

4

('C'=$43)

SCIMEF

S(ClOMIE{

I0

:

:

3

1

bO

I

I

Fig. 10.5. Example of SCISRD Execution
Specifications Notes:
(1)
"No. of cycles" in "SPECIFICATIONS" represents the
number of cycles are needed when having no wait time for receiving data.
(2) Reset interrupt request flag with SOFTWARE in interrupt routine.

HITACHI 211

Program Module Name:
TRANSFER/RECEIVE

MCU: HMCS402C/
HMCS404C/HMCS408C

SCI SLAVE

Label:
--

SCISTR

Description:

2.

3.

SClMEF (RAM) =1:

Data is received from master system.

SClMEF (RAM) =0:

No data is received from master system.

(2)

SCISTR execution stores contents of SCI data register in SCISRU(RAM)
and SCISRL(RAM) .

(3)

SCISTR calls neither program modules nor subroutines.

User Notes
(1)

When program module SCISTR is used, resetting system (in case of
power on reset, supplying power) should be performed from master
system.

(2)

Program module SCISTR should be called before master system begins
to send data.

RAM Allocation

Fig. 10.6. RAM Allocation

Label

RAM
b3

SCISOK

Description

bO

fB

Flag indicating if data is received
from master system

MD($030)
b7

SCISRU:SCISRL

~
MD(S033,S032)

•

b3

SCIMEF

bO

bO

MD(S035)

212 HITACHI

Store data sent from master system

Flag indicating existence of receives
data

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

SCI SLAVE

TRANSFER/RECEIVE

Label:
--

SCISTR

Description:
4.

Sample Application

SEDD
LMID
LMID
REMD
REMD
SEMD
TMD

LOOPl
LOOP2

5.

BR
BR
LMID
LAMD
LBA
LAMD

$ 1

............ Set Port Dl to High

$ 2, PMR
$F, SMR

............ Select received mode

I F S

............ Clear SCI interrupt request flag

IMS

............ Clear SCI interrupt mask

............ Load clock source into external clock

I E · · · · · · · · · · · Enable interrupt
$0, SCIMEF}
L 0 0 P l · · · · · · · · · Test if receiving completed

LOOP2
$0, SCIMEF ............ Clear flag indicating receive
SCISRL

I

SCISRU

r

completion
Load receives data into Accumulator
and B register

Basic Operation
(1)

Receives serial data using SCI interrupt routine.

(2)

In case of
indicating
In case of
indicating

(3)

Serial interface movement is started by STS instruction.

recelvlng complete, read receives data and set flag
receive completion.
sending complete, select receives mode and clear flag
send data. Set master receives request to high.

HITACHI 213

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

SCI SLAVE

TRANSFER/RECEIVE

ILa~l'

SCISTR

Flowchart:

-J ----[

L-_ _....-_ _

Clear SCI interrupt request flag
register

o.
if sending data

-J---{
-J---{

L-_ _....-_ _

Select received mode

L-_ _-,-_ _

Clear flag indicating send data

___ {
L -__~~__--J

SCIST2

__

~{

Set master received request flag to
high

Load content of serial data register
into RAM

- - - { Set flag indicating receive completion

-J ---{
-J ---{

214 HITACHI

L-_ _......._ _

Start SCI

L-_ _-,-_ _

Restore register

10.4

SUBROUTINE DESCRIPTION
This application example calls no subroutines.

10.5

PROGRAM LISTING

ST-No

o8JECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074

363

0000

SOURCE STATEMENTS
LLEN
TITLE

132

CLOCKED SYNCHRONOUS SCI (EXTERNAL CLOCK)

***** RAM ALLOCATION
*SCISoK EOU
$030
SCISRU
SCISRL
SCIMTD
SCIMEF
SCIASU
SCIASL

*
****
*PMR

SMR
SRL
SRU
IMS
IFS
IE

EOU
EOU
EOU
EOU
EOU
EOU

****************************************

$032
$033
$034
$035
$036
$037

SYMBOL DEFINITIONS
EOU
EOU
EOU
EOU
EQU
EQU
EQU

$004
$005
$006
$007
1. $003
0.$003
O. $000

FLAG FOR SENDING DATA
UPPER RECEIVED DATA
LOWER RECEIVED DATA
SENDING DATA FLAG
RECEIVING DATA COMPLETE FALG
UPPER OUTPUT DATA
LOWER OUTPUT DATA
************************************

PORT MODE REGISTER
SERIAL MODE REGISTER
LOWER SERIAL DATA REGISTER
UPPER SERIAL DATA REGISTER
INTERRUPT MASK OF SERIAL
INTERRUPT REQUEST FLAG
INTERRUPT ENABLE FLAG

****************************************************************

150
150
150
150
150
000
000
150

OFO
lAO
lAO
lAO
lAO
lAO
lAO
lAO
2EO
2El
lA2
lAF
188
189
1B4
148
18C
340
18C
333
345
2AO
336
340
190
194
190
194

010
010
010
010
010
05B

030
032
033
034
035
036
037
004
005
003
003
000
030
034

036
007
037
006

0000
0002
0004
0006
0008
OOOA
OOOB
OOOC

0010
0011
0013
0015
0017
0019
001B
0010
001F
0020
0021
0023
0025
0027
0029
002B
002C
002E
002F
0031
0032
0033
0034
0035
0036
0038
003A
003C

*
*
VECTOR ADDRESSES
*
*
*
*
****************************************************************
*
oRG
$0000
*
SCISMN
RESET
JMPL
JMPL
INTO
SCISMN
JMPL
SCISMN
INTI
SCISMN
TIMER-A
JMPL
JMPL
TIMER-B
SCISMN
NOP
NoP
JMPL
SCISTR
SERIAL
****************************************************************

*
*
MAIN PROGURAM : SCISMN
*
*
******************************************************************
*
ORG
$0010
*SCISMN LWI
$0
INITIALIZE W REGISTER

SCISM1

SCISM2
SCISM3

LMID
LMID
LMID
LMID
LMID
LMID
LMID
SEDD
SEDD
LMID
LMID
REMD
REMD
SEMD
STS
TMO
BR
TMD
8R
BR
TOO
BR
8R
LAMD
LMAD
LAMD
LMAD

$O.SCISOK
$O.SCISRU
$O.SCISRL
$0. SCIMTD
$O.SCIMEF
$O.SCIASU
$O.SCIASL
$0
$1
$2.PMR
$F.SMR
IFS
IMS
IE

$O.SCISOK
SCISM6
$O.SCIMTD
SCISM2
SCISM4
$0
SCISM3
SCISM6
SCIASU
SRU
SCIASL
SRL

INITIALIZE RAM

INITIALIZE 0 PORT
INITIALIZE PMR
INITIALIZE SMR
INITIALIZE IFS
INITIALIZE IMS
ENABLE INTERRUPT
SCI START
TEST IF SENDING DATA
TEST IF SCIMTD
TEST IF SLAVE RECEIVE REQUESTED
LOAD SENDING DATA INTO SERIAL DATA REGISTER

HITACHI 215

00075
OD076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114
00115
00116
00117
0011B
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141

1A1
lAO
1A1
261
18C
349
34D
1A1
lAO
190
OC8
190
160
194
048
194
150

004
034
030
035
034
035
033
032
076
036
037
02C

003E
0040
0042
0044
0045
0047
0048
0049
004B
004D
004F
0050
0052
0054
0056
0057
0059

SCISM4
SCISM5
SCISM6

LMID
LMID
LMID
REDD
TMD
BR
BR
LMID
LMID
LAMD
LBA
LAMD
CALL
LMAD
LA8
LMAD
JMPL

$1. PMR
$O.SCIMTD
$1. SCISOK
$1
$O.SCIMEF
SCISM5
SCISM6
$1. SCIMTD
$O.SCIMEF
SCISRL
SCISRU
TPR
SCIASU

SELECT SENDING MODE
CLEAR SENDING DATA FLAG
SET SENDING DATA FLAG
CLEAR MASTER RECEIVE REQUEST
TEST RECEIVING COMPLETE FLAG
SET SENDING DATA FLAG
CLEAR RECEIVING COMPLETE FLAG
LOAD TPR ENTRY ARGUMENT
CONVERT LOWERCASE INTO UPPERCASE
STORE TPR RETURN ARGUMENT IN RAM

SCIASL
SCISM1

****************************************************************

188
2FF
lac
362
369
1A2
lAO
2E1
150
190
194
190
194
1A1
148
2FF
011

003
030
004
030
073
006
033
007
032
035

OD8
048
076
37F
2BO
37E
OAF
28E
010
077
37E
2BA
37C
37E

216 HITACHI

005B
0050
005E
0060
0061
0062
0064
0066
0067
0069
0068
006D
006F
0071
0073
0074
0075

0076
0077
0078
0079
007A
0078
007C
007D
007E
007F
0080
00B1
0082
0083

*
*
NAME : SCISTR
*
*
******************************************************************
*
*
ENTRY
NOTHING
*
*
RETURNS : SCISRU (UPPER RECEIVED DATA)
*
*
SCIRDU (LOWER RECEIVED DATA)
*
*
SCIMEF (SCIMEF=l;TRUE.SCIMEF=O;FALSE)
*
*
******************************************************************

CLEAR SERIAL INTERRUPT REQUEST FLAG
REMD
IFS
$F
SAVE A REGISTER
XMRA
TMD
$O.SCISOK
TEST IF SENDING DATA
BR
SCISTl
BR
SCIST2
$2.PMR
SELECT RECEIVING MODE
LMID
SCISTl
CLEAR SENDING DATA FLAG
$O.SCISOK
LMID
$1
SET MASTER RECEIVE REQUEST FLAG
SEDD
JMPL
SCIST3
STORE RECEIVED DATA IN RAM
LAMD
SRL
SCIST2
LMAD
SCISRL
SRU
LAMD
LMAD
SCISRU
$l.SCIMEF
SET RECEIVING COMPLETE FLAG
LMID
SCI START
SCIST3
STS
$F
RESTORE A REGISTER
XMRA
RTNI
****************************************************************
SCISTR

*
*
NAME : TPR (COVERT ASCII LOWERCASE INTO UPPERCASE)
*
*
*
*****************************************************************
TPR

TPR1
TPR2
TPR3

*

LYA
LAB
YNEI
BRS
ALEI
8RS
LAY
AI
RTN
YNEI
BRS
ALEI
BRS
BRS
END

$E

LOAD UPPER 4 BIT OF ASCII LOWERCASE
LOAD LOWER 4 BIT OF ASCII LOWERCASE
UPPER 4 BIT OF ASCII LOWERCASE = $6 ?
BRANCH IF UPPER 4 BIT OF ASCII LOWERCASE
LOWER 4 BIT OF ASCII LOWERCASE =( $0 ?
BRANCH IF LOWER 4 BIT OF ASCII LOWERCASE
LOAD A FROM Y
CONVERT LOWERCASE INTO UPPERCASE

$7
TPR2
$A
TPR1
TPR2

UPPER ASCII = $7 ?
BRANCH IF UPPER 4 BIT OF ASCII LOWERCASE
LOWER 4 8IT OF ASCII LOWERCASE =( SA 7
BRANCH IF A =< SA
BRANCH IF A > SA

$6
TPR3
$0
TPR2

SECTION 11.

11.1

CLOCK SYNCHRONOUS SCI (INTERNAL CLOCK)

HARDWARE DESCRIPTION

11.1.1

Function
(1)

Transfers clock synchronous serial data to slave system, and

(2)

Interfaces transfer clock output pin (hereinafter, SCK),

receives data from slave.

serial data input pin (hereinafter, SI) and serial data output
pin (hereinafter, SO) of the HMCS404C to master pins with each
pin of slave system.
(3)

Handshakes using transfer/receive control signal to transfer
or receive data.

11.1.2

Microcomputer Applications
(1)

Transfers data to/from slave system using clock synchronous

(2)

Inputs master receives request signal port Dl from slave

serial communication interface (hereinafter, SCI).

system.

Outputs transfer rate clock to slave system considering

input state and receives data.
(3)

Outputs slave receives request signal from port DO to inform data
transfer to slave system.

HITACHI 217

11.1.3

Circuit Diagram

MCV

HMCS404C
( HMCS40 2C)
HMCS408C

+5V

50 TEST

+5V
+5V

32

r ---

I
I

I
I

Slave receives request signal

Vee

H~

Master receives request signal 55

D.
R• .!SO
system 1-_=--=_---------------3~4 R.. lSI
SI

I Slave rs'!"o-::---------------...:3~5

I

I
~S_C-K--------------------------~3~3 R.o/SCK
I
I
IL ___ ....II
Fig. 11.1.

218 HITACHI

Clock Synchronous SCI Circuit

11.1.4

Pin Functions
Pin functions at the interface between the HMCS404C SCI pins and
slave system are shown in Table 11.1.

Table 11.1.

11.1.5

Pin Functions

Pin Name
(HMCS404C)

Input/
Output

Active
Level
(High
or Low)

SCK

Output

Low

SI

Input

Receives data

Serial data
output

SO

Output

Transfers data

Serial data
input

Dl

Input

Low

Inputs transfer clock
request from slave.
Outputs clock i f low

Master receives
request signal

DO

Output

Low

Informs transfer start
to slave

Slave receives
request signal

Function

Pin Name
(Slave system)

Outputs transfer clock

Serial clock

Hardware Operation
SCI timing chart is shown in Fig. 11.2.

rLoads data to be sent into SRU, SRL

Transfer
Slave receives
request signal (DO)

.

r- Slave

maxlO,us

sends data

~n
rIL______ _______________________________________JI

Masterreceives
request signal (D,)

SI

!...I_ _ _ _ _ _ _ _ _ _ _

------~~-S-B-----

so
Rece~ve

---Jr---

IL-1·_·

~

_________

~~S~B

____

Receives data
latch timing
Fig. 11.2.

SCI Timing Chart

HITACHI 219

11.2

SOFTWARE DESCRIPTION

11.2.1

Program Module Configuration
The program module configuration for serial communication with
slave system is shown in Fig. 11.3.

SCIMMN

~
Main Program

SCIMTR

I

I

SCMTRD

I
l!..

I.!..

SCI Master
Receives

SCI Master
Transfer

Fig. 11.3. Program Module Configuration

11.2.2

Program Module Functions
Program module functions are summarized in Table

Table 11.2.

220 HITACHI

11.2.

Program Module Functions

No.

Program Module Name

Label

Function

o

Main Program

SCIMMN

Sends data to slave system and
receive it from slave system
without change by using the
HMCS404C SCI

1

SCI Master Transfer

SCIMTR

Sends serial data to slave system
using internal clock

2

SCI Master Receive

SCMTRD

Receives data from slave system
using internal clock

11.2.3

Program Module Sample Application (Main Program)
The flowchart in Fig. 11.4 is an example of sending serial data to
slave system and receiving it from slave system, performed by the
program modules in Fig. 11.3.

Main Program

...J---{

L - - - r_ _

Initialize W register

Initialize RAM to be used

'--_-,._ _... ----{ Initialize port DO

L-_-,._ _... - - - {

Initialize pO.rt Dl

,--_-,._ _... - - - { Clear SCI interrupt mask

...J---{

L-_-,._ _

___ {
,--_-,._ _",

Select transfer/receive moo.e
Select prescaler divide ratio as .. 2
and system clock divide ratio as .. 4

'--_-,._ _... - - - { Clear SCI interrupt request flag
'--_-,._ _... - - - { Clear SCI interrupt mask
,--_-,._ _... - - - { Enable interrupt

___ {
r--~--~

Store ASCII A uppercase in B register
and Y register

'----,-----'

existence of

Fig. 11.4.

Program Module Flowchart

HITACHI 221

r -_ _ _

-::"~~:::;=r---LJ - - - - [

Execute SCIMTR

receiving complete flag

___ {
~-::-::-I"-----,

Load receives data into SCISRU (RAM) and
SCISRL (RAM)

L..----r--...I

SCI interrupt routine

___ { Execute SCMTRD and receiving data
from master system

Fig. 11.4.

222 HITACHI

Program Module Flowchart (cont.)

11.3

PROGRAM MODULE DESCRIPTION

Program Module Name:

SCI MASTER
TRANSFER

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

SCIMTR

Function:
Sends data in Band Y register to slave system using internal clock.

Arguments:
Contents
Entry

1 digit = 4 bits
Storage
No. of
Location Digits

Data to
be sent
Data to
be sent

B

Y

Specifications:

Changes in CPU
Re9:isters and Flags:

1

1

1 word = 10 bits

A
x

B
x

ROM (Words): 41

X

Y

Stack (Digits): 0

•

x

No. of cycles: 43

RAM (Digits): 3

Reentrant:

Spy

SPX

•

•

•
x

:

CA

ST

•

x

Not Affected
Undefined
Result

Description:

B register:
Entry
{ Y register
argument 1 byte data

1. Function Details

(3)

Yes

•

Returns

(2)

No

Interrupt OK?:

W

(1)

No

Relocatable:

Argument details
B register, Y register (RAM):
Holds data to be sent to
slave system.
Program module SCIMTR execution
loads entry argument content
into SRU, SRL and sends it to
slave system.
SCIMTR calls neither program
modules nor subroutines.

('C' =$43)

b7

B:Y

bO

~
~

b7

bO

SRU:SRL~

SCI data
register

SCKPi~

o

Output

SOP~0lllWL
o

Fig. 11.5.

t

I

bO

b7

Example of SCIMTR Execution

Specifications Notes:

HITACHI 223

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

SCI MASTER
TRANSFER

Label:
--

SCIMTR

Description:
2.

3.

User Notes

(1)

Sets slave receives request signal to low and sets slave receiving
state before program module SCIMTR execution.

(2)

When using program module SCIMTR, resetting system (in case of power
on reset, activating power) is performed master reset firstly, then
reset slave system secondly.

RAM Allocation

Fig. 11.6.

Label

RAM
b3

RAM Allocation

Description

bO

SCISOK

Flag indicating if sending data
MD(S030)

b3

SCIMOK

bO

~

Flag indicating if receiving data

MD( S031)

•

b3

SCIMTD

bO

MD(S034)

224 HITACHI

Flag indicating existence of transfer
data

Program Module Name:

SCI MASTER
TRANSFER

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:
--

SCIMTR

Description:
4.

Sample Application

SEDD
SEDD
LMID
LMID
LBI
LYI

so

} ............... Set port DO and Dl high

S 1
PMR

............... Select transfer/receive mode

SD. SMR

............... Select internal clock source

$ 3.

$ 6

S 1

} ............... Load data to be send into entry
argument

1u.I_c_A..,L_L____S_C_I_M_T_R_....JJil ................... Subroutine call program module SCIMTR
5.

Basic Operation
(1)

When slave receives request signal is output, master receives request
signal may output from slave system with the same timing. Then, 10 ~s
software timer is executed and master receives request signal is tested
after slave receives request signal is output.

(2)

Transfers receives serial data if master receives request signal is
output.

(3)

Goes to the next step after SCI interrupt request flag is set and
transfer/receive completes.

(4)

When serial data is received, retains transfer request in output
state until main program processes receives data so that next data
can not be received.

HITACHI 225

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

SCI MASTER
TRANSFER

~ SCIMTR

Flowchart:

if sending data

if receiving data

existence of master receives request

existence of transfer data

- - - { Request to send

- - - { Exeoute 10 "' .oftware time,

2

__ {

Test if existence of master receives
request

- - - - [ Set flag indicating sending data

- - - { Clear flag indicating receiving data

data in SRU(RAM) and

- - - { Start SCI

226 HITACHI

Program Module Name:

SCI MASTER
TRANSFER

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

SCIMTR

Flowchart:

~-;;::::::::::=r----'----[ Set slave

receives request

- - - { ExeMe 10 "' ,oftwm time,

'-----r---....I- - - - [ Set flag indicating receiving data

HITACHI 227

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

SCI MASTER
RECEIVE

Label:

SCMTRD

Function:
1.

Outputs serial clock and receives data from slave system.

2.

Permits outputting when slave system cannot output serial clock.

Arguments:
Contents

1 digit = 4 bits
Storage
No. of
Location Digits

Registers and Flags:

Returns

End of
receives
data

SCISRU
(RAM)
SCISRL
(RAM)
SCIMEF
(RAM)

1 word = 10 bits

A

B

ROM (Words) : 24

•

•

RAM (Digits) : 5

X

Y

Stack (Digits) : 0

•

•

No. of cycles:

SPX

SPY

Reentrant: No

•

•

Entry

Receives
data

Specifications:

Changes in CPU

Relocatable: No
Interrupt OK?: Yes

W

1

21

•

1
1

CA

ST

•

•

•

Not Affected
x : Undefined
Result

Description:
1. Function Details
(1)

Argument details
SCISRU,SCISRL(RAM) :
Contains data received
from slave.
SCIMEF(RAM):
Indicates
existence of receives data.
SCIMEF=O: No data is received
from slave system.
SClMEF=l: Data is received
from slave system.

Specifications Notes:

2.

SCK pin

CD

Input
SI pin

lJlJ1JlJlJUlJlr
IJl1lWL
o

o

t

i
Bit 0

~

SRU:SRL
SCI data reg~ster
SCIMEF b7 bO
SRU: SRL
SCIMEF(RAM)
1 byte data
('C'=$43)
Fig. 11.7. Example of SCMTRD Execution
Return
argument

1

0~

1. "No. of cycles" in "Specifications" represents the
number of cycles needed when having no wait time
for receiving data.
Reset interrupt requests flag with software in interrupt routine.

228 HITACHI

Bit 7

Program Module Name:

SCI MASTER
RECEIVE

Label:
-----

l'ICU: lillCS402C/
ill1CS404C/lillCS408C

SCMTRD

Description:

2.

3.

(2)

Program module SCMTRD execution contains SRU,SRL contents in return
argument accumulator.

(3)

SCMTRD calls neither program modules nor subroutines.

User Notes
(1)

When program module SCMTRD is executed, set Port Dl and Port D2 to
1.

(2)

Goes to transfer possible state in slave system before program module
SCMTRD execution.

RAM Allocation

,

o3

--:--:---t--:--:---i--:---:---l- imTIt-

o4
o5

--t--+--~--~--t--~-~--+--t--~-1--

I

o

I

I

I

I

I

I

t

I

-~--r--~--:---1--~--~---:----t--~--"'=~:.:..1==~
I

1

I

:

I

I

I

I

I

I

I

I

I

I

I

i

I

I

I

I

I

I

I---j
--i--~---t--t--i
6~l-~---L--L-~--~--L-_l__~__~~~J,~=I~~I;;J'=-JL

Fig. 11.8.

RAM

Label

b3

RAM Allocation
Description

bO

SCISOK

Flag indicating if sending data
MD($030)

b3

SCIMOK

bO

~

Flag indicating if receiving data

MD($031)

b7

bO

SCISRU:SCISRL

Stores data sent from slave system
MD($033,$032)

•

b3

SCIMEF

bO
Flag indicating existence of receives
data

MD(S035)

HITACHI 229

Program Module Name:

SCI MASTER
RECEIVE

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:
---

SCMTRD

Description:
4.

Sample Application

SEDD
SEDD
LMID
LMID
REMD
REMD
SEMD
LOOPl

LOOP2

5.

$ 0

}

............ Set port DO and port 01 high

$ 1
$ 8, PMR

............ Select transfer/receive mode

S D, SMR
IFS
IMS
IE

............ Select transfer clock Ratio
............ Clear SCI interrupt request flag
............ Clear SCI interrupt mask

............ Enable interrupt

TMD

$0, SCIMEF)

BR

L 0 0 P 2

BR

LOOPl

LAMD
LMAD
LAMD
LMAD

SRU
SCISRU
SRL
SCISRJJ

...... Test if receiving flag

}

Load receives data into accumulator
A and B register

Basic Operation
(1)

Checks slave receives request signal to test if data is received after
outputting the signal.

(2)

Tests if master receives request signal has been output from slave
system.

(3)

If output, sets SCI interrupt request flag, and stores serial data in
return argument after checking that serial data is received.

230 HITACHI

Program Module Name:

SCI MASTER
RECEIVE

MCU: HMCS402C/
HMCS404C/HMCS408C

I~

SCMTRD

Flowchart:

L----r---..J - - - { Clear SCI interrupt request flag

L----r---~

- - - { Save register

- - - - [ Test if sending data

- - - - [ Clear flag indicating sending data

- - - - [ Set slave receive request high

' - - - - - r - - -... - - - - [ Clear flag indicating receiving data

~

_ _~_~

____[ Read receives data and store it in
SCISRU and SCISRL(RAM)

'---~-';";";;;'"

L-;::-::=~;::::==r-----I----[ Set flag

indicating receives completion

- - - - [ Restore register

"-::::::::c:::::-'

HITACHI 231

11.4

SUBROUTINES
This application example calls no subroutines.

11.5

PROGRAM LISTING

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074

37E

0000

SOURCE STATEMENTS
LLEN
TITLE

132
CLOCKED SYNCHRONOUS SCI (INTERNAL CLOCK)

*
RAM ALLOCATION
****
*SCISOK EQU
$030
SCIMOK
EQU
$031
EQU
$032
SCISRU
SCISRL
EQU
$033
EQU
$034
SCIMTD
SCIMEF
EQU
$035
*
****
*PMR

SMR
SRL
SRU
IMS
IFS
IE

*******************************

SYMBOL DEFINITIONS
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$004
$005
$006
$007
$1. $003
$0.$003
$O.SOOO

FLAG FOR SENDING DATA
FLAG FOR RECEIVING DATA
UPPER RECEIVER DATA
LOWER RECEIVED DATA
SENDING DATA FLAG
RECEIVING DATA COMPLETE FLAG
***************************

PORT MODE REG.
SERIAL MODE REG.
LOWER SERIAL DATA REG.
UPPER SERIAL DATA REG.
INTERRUPT MASK OF SERIAL
INTERRUPT REQUEST FLAG OF SERIAL
INTERRUPT ENABLE FLAG

********************************************************

150
150
150
150
150
000
000
150

010
010
010
010
010
068

0000
0002
0004
0006
0008
OOOA
OOOB
OOOC

*
VECTOR ADDRESSES
*
*
*
*
********************************************************
*
ORG
$0000
*
JMPL
RESET
SCIMMN
JMPL
JMPL
JMPL
JMPL
NOP
NOP
JMPL

SCIMMN
SCIMMN
SCIMMN
SCIMMN

INTO
INTl
TIMER-A
TIMER-B

SCMTRD

SERIAL

********************************************************

*
*
MAIN PROGURAM : SCIMMN
**********************************************************
*
ORG
$0010
*

OFO
lAO
lAO
lAO
lAO
lAO
lAO
2EO
2El
185
lA3
lAD
188
189
184
206
211
lAl
160
lBC
335
32F
190
194
190
194
33D

030
031
032
033
034
035
003
004
OOS
003
003
000
034
03E
035
007
032
006
033

232 HITACHI

0010
0011
0013
0015
0017
0019
OOlB
0010
OOlE
001F
0021
0023
0025
0027
0029
002B
002C
0020
002F
0031
0033
0034
0035
0037
0039
0038
0030

*SCIMMN

SCIMNl

SCIMN2

PEND

LWI
LMID
LMID
LMID
LMID
LMID
LMID
SEDD
SEDD
SEMD
LMID
LMID
REMD
REMD
SEMD
L8I
LYI
LMID
CALL
TMD
8R
8R
LAMD
LMAD
LAMD
LMAD
8R

$0
$O.SCISOK
$O.SCIMOK
$O.SCISRU
$O.SCISRL
$O.SCIMTD
$O.SCIMEF
$0
$1
IMS
$3.PMR
$D.SMR
IFS
IMS
IE
$6
$1
$1. SCIMTD
SCIMTR
$O.SCIMEF
SCIMN2
SCIMNl
SRU
SCISRU
SRL
SCISRL
PEND

INITIALIZE W REGISTER
INITIALIZE RAM

INITIALIZE DO PORT
INITIALIZE IMS
INITIALIZE PMR
SELECT PRESCALER AS 1/2.SYSTEM CLOCK
CLEAR SERIAL INTERRUPT REQUEST FLAG
CLEAR SERIAL INTERRUPT MASK
ENABLE INTERRUPT
STORE OUTPUT DATA
SET SENDING OAT A FLAG
OUTPUT SCI DATA
TEST RECEIVING COMPLETE FLAG
STORE RECEIVE DATA IN RAM

END OF PROGRAM

********************************************************

*

1/4

00075
00076
00077
00078
00079
OOOBO
oOoBl
000B2
000B3
000B4
00DB5
000B6
000B7
OOOBB
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
0010B
00109
00110
00111
00112
00113
00114
00115
00116
00117
0011B
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
0013B
00139
00140
00141
00142
00143
00144
00145

NAME : SCIMTR (SCI MASTER TRANSFER)
*
*********************************************************

*
ENTRY: B REGISTER.Y REGISTER (TRANSFER DATA) *
*
RETURNS : NOTHING
*
*********************************************************
1BC
35E
1BC
35E
2A1
347
360
1BC
34B
35E
260
230
2B4
350
34D
2A1
353
35F
1A1
lAO
04B
.194
OAF
194
14B
010
2EO
230
2B4
364
361
1A1
150

030
031

034

030
034
007
006

031
05D

003E
OD40
0041
0043
0044
0045
0046
0047
0049
004A
0048
004C
004D
004E
004F
0050
0051
0052
0053
DOSS
0057
0058
005A
005B
005D
005E
005F
0060
0061
0062
0063
0064
0066

SCIMTR

SCIM1
SCIM2
SCIM3
SCIM4
SCIM5

SCIM6
SCIM7
SCIMB
SCIM9
SCIM10
SCIM11

TMD
BR
TMD
BR
TDD
BR
BR
TMD
BR
BR
REDD
LAI
AI
BR
BR
TOO
BR
BR
LMID
LMID
LAB
LMAD
LAY
LMAD
STS
RTN
SEDD
LAI
AI
BR
BR
LMID
JMPL

$0. SCISoK
SCIM7
$O.SCIMoK
SCIM7
$1
SCIM1
SCIM9
$O.SCIMTD
SCIM2
SCIM7
$0
$0
$4
SCIM4
SCIM3
$1
SCIM5
SCIM8
$l.SCISoK
$O.SCIMTD

TEST IF SENDING DATA

TEST IF RECEIVING DATA
TEST MASTER RECEIVING REQUEST
TEST IF SENDING DATA
CLEAR SLAVE RECEIVE REQUEST
EXECUTE IoMS SOFTWARE TIMER

TEST MASTER RECEIVE REQUEST
SET SENDING DATA FLAG
CLEAR RECEIVING DATA FLAG
STORE SENDING DATA IN RAM

SRU
SRL
$0
$0
$4
SCIM11
SCIM10
$l.SCIMoK
SCIM6

SCI START
SET SLAVE RECEIVE REQUEST
EXECUTE loMS SOFTWARE TIMER

SET RECEIVING DATA FLAG

****************************************************************

*
*
NAME : SCMTRD (SCI MASTER RECEIVE)
*
*****************************************************************

188
2FF
1BC
36F
374
lAO
2EO
150
lAO
190
194
190
194
1A1
2FF
011

003
030
030
OBO
031
007
032
006
033
035

0068
006A
006B
0060
006E
006F
0071
0072
0074
0076
007B
007A
007C
007E
0080
00B1

*
*
ENTRY
NOTHING
*
*
RETURNS : SCISRU (UPPER RECEIVED DATA)
*
SCISRL (LOWER RECEIVED DATA)
*
*
SClMEF (SCIMEF=O:TRUE.SCIMEF=l:FALSE)
*
*
*****************************************************************
SCMTRD

SCMTR1
SCMTR2

SCMTR3

REMD
XMRA
TMD
BR
BR
LMID
SEDD
JMPL
LMID
LAMD
LMAD
LAMD
LMAD
LMID
XMRA
RTNI

IFS
$F
$O.SCISoK
SCMTR1
SCMTR2
$O.SCISoK
$0
SCMTR3
$O.SCIMoK
SRU
SCISRU
SRL
SCISRL
$l.SCIMEF
$F

CLEAR SERIAL INTRRUPT REQUEST FLAG
SAVE A
TEST IF SENDING DATA
CLEAR SENDING DATA FLAG
SET SLAVE RECEIVING REQUEST FLAG
RECEIVING DATA FLAG
STORE RECEIVE DATA IN RAM

SET RECEIVING COMPLETE FLAG
RESTORE A

END

HITACHI 233

SECTION 12.

12.1

LIQUID CRYSTAL DRIVER (HD61100A) CONTROL

HARDWARE DESCRIPTION

12.1.1

Function
Controls the HD61100A liquid crystal driver and displays "9876543210"
on an LCD display.

12.1.2

Microcomputer Operation
The HMCS404C sends display data and control signals from to the
HD61100A to display graphics on the LCD.

Signals M and CLl of the

HD61100A and signal COMMON of the liquid crystal are controlled through
port R7.

In addition, the HD61100A control signals (signals CLZ' DL)

are controlled using the clock synchronous SCI (serial communication
interface) of port R7 to enable sending of display data to the
HD61100A.

12.1.3

Peripheral Devices
HD61100A LCD Driver:
10-digit LCD.

234 HITACHI

Performs static drive on an 8-segment x

12.1.4

Circuit Diagram
LCD driver (HD61100A) control circuit is shown in Fig. 12.1.

Meu
HMes.o~e

.sv

~esulID
CS~08

s

oW

r-112076

LOokO

!

~

.

l~•" ..."
vee

tlD74HC14

,ou"

Ii'"T

~

ffi-·_~or15..
BlpF

{

+~v

SOI8'l~!l88108f8~1 '"'
V'LV,.V",V" v...v..v... v..

81\

OSC ,

~

OSC,

oM l!!

GND

r

'-;:;RRu..
R,.

Fig. 12.1.

HDell

~ Fes

SOA..

88 SCK
80

'1:. f!!.

Vo
GND
~ SHL

M
M

CL, CL,
8'

Y,
I

OOA

~

~.
DL

COMMON

Liquid
crystal

I-;-\Ilnn n ooooooe:1
~ OOOUUUI)UIJU

(S-segment x lO-digit)

~l

~~1lrl

LCD Driver (HD61100A) Control Circuit

HITACHI 235

12.1.5

Pin Functions
Pin functions at the interface, between the HMCS404C and the
HD61100A are shown in Table 12.1.

Table 12.1.

Pin Name
(HMCS404C)

Pin Functions

Input/
Output

Active Level
(High or Low)

Output

12.1.6

Pin Name
(HD61100A
LCD)

Function
Outputs alternate signal
for LCD driving output

M

CLl

Output

--

Resets counter, outputs
synchronous signal of
latch clock for display
data

SCK

output

--

outputs shift clock
for display data

SO

Output

--

Inputs display data

DL

Hardware Operation
Timing chart of the HMCS404C, LCD, and the HD61100A is shown in Fig.
12.2.

LCD and HD61100A
pin names

COMMO~~_____________________________________

Controlled
by I/O ports

Controlled b Y{
clock
Synchronous
SCI

~.--------------

M

CL,

--'l____________________________________ __________ IL

C L.

CIIJr::J QI';
____ ____ J1JULJ~Uu

DL

..J~__..JL..J ...._"_.JL..JL_"...J'__I'_....J11....J'_'\....J\....J'I...J,L...IL...JL.._
Output 80 bits (10

Fig. 12.2.

236 HITACHI

-I
L

-------~

di9its~------

~

Timing Chart of HMCS404C, LCD, and HD61100A

.1

12.2

SOFTWARE DESCRIPTION

12.2.1

Program Module Configuration
The program module configuration for character display on LCD is
shown in Fig. 12.3.

H61MN
Main
program

1..£

H61DSP
Display
Character

Fig. 12.3.

12.2.2

L2.

Program Module Configuration

Program Module Functions
Program module functions are summarized in Table 12.2.

Table 12.2.

Program Module Functions

No.

Program Module Name

Label

Function

o

Main Program

H61MN

Performs static drive on an
8-segment x lO-digit LCD.
Initializes control registers and
data addresses used for the
interface between the HMCS404C
and the HD61100A

1

Display Character

H61DSP

Performs static drive of LCD
using the HD61100A and displays
numerals

HJTACHl237

12.2.3

Program Module Process Flow (Main Program)
The flowchart in Fig. 12.4. shows the procedure for displaying
numerals on or LCD as performed by the program module in Fig. 12.3.

Main program.

- - - - { Ini tialize W register

- - - {store to SO output pin

- - - - [ S t o r e to SCK output pin

- ---[Clear Serial interrupt mask

- - - - [call H61INT

- - - - [Enable interrupts

- - - -[~, ",="0' ._••• " ".ph, _

Executes pattern command for
storing display data in RAM

y- l-+Y
A-+M

Y1$F

-

- --[Test if all display data is stored

SCI Interrupt Routine

~--~~~~==~--l[

Fig. 12.4.

238 HITACHI

Execute H6lDSP to display numerals on LCD

Program Module Flowchart

n
u

123Y55
Fig. 12.5.

n

I

8

Example of H61MN Execution

HITACHI 239

12.3

PROGRAM MODULE DESCRIPTION

Program Module Name:

Display'
Character

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

H6lDSP

Function:
Sends display data to the HD61100A and displays characters on the LCD.

Arguments:
Contents
Entry

Dispaly
data

DDATA
(RAM)

Speci fications:

Changes in CPU

1 digit = 4 bits
Storage
No. of
Location Digits

Registers and Flags:

=

1 word

10 bits

ROM (Words) : 57

A

B

•

•

RAM (Digits) :

X

Y

Stack (Digits) :

•

•

No. of cycles: 435

SPX

SPY

•

•

10

Reentrant:

a

No

Relocatable:
Interrupt OK?:

W

2

No
No

•

Returns

•
x

Description:

:

CA

ST

•

•

Not Affected
Undefined
Result

Q)

1. Function Details
(1) Argument details
DDATA(RAM): Holds 10 digits of
display data.

Entry
argument
Display data
DDATA MD($049-$040)
( RAM)

(2) Example of H6lDSP execution is
shown in Fig. 12.6. If entry
argument is as shown in part Q)
of Fig. 12.6. characters are
displayed as shown in part
of Fig. 12.6.

Liquid Crystal

t

GD

Fig. 12.6.

Specifications Notes:

240 HITACHI

Example of H6lDSP Execution

Program Module Name:

Label:
--

MCU: HMCS402C/
HMCS404C/HMCS408C

Display
Character

H61DSP

Description:
(3)
2.

H61DSP calls neither the program modules nor subroutines.

User Notes
The following procedure must be performed before H61DSP execution.

3.

(1)

Initializes clock synchronous SCI to send display data.

(2)

Sets bit IE to enable SCI interrupts.

(3)

Clears IMS.

(4)

Executes STS command to generate SCI interrupts.

RAM Allocation

FIE:DICtBIAt91817t6i514:3:Z:1:0

o2
o4

o5
o6

:

:

:

:

I

:

1

:

I

1

:

I

I

I

I

I

I

:

I

I

I

I

I

I

I

1

I

I

I

I

I

I

I

I

I

I

I

I

i

I

I

I

I:

I

:

:

I

--~--~--+--4--~---f--~--~--~--~--~---~--t--~---~--

o3

I

- -~--r--~ --:--~.~--~~~~I~~~~i~'~~~~~~~
--~----l--i--t
__ ~--~ __ J_-J__:__ l __ l __ L__ ~ __ l--~--l--L-I
J

~

Fig. 12.7.

Label

I

I

l~

I

I

I

1

I

I

I

I

Ll-

RAM Allocation

RAM

Description

~--------~

DDATA

~--------~
MD($040)

Stores display data

MD($049)

CNTR

MD($05E)
b3

Used as Y register pointer to display
data and as a counter indicating number
of interrupts

bO

MFLG

Used as a test flag indicating
whether M signal will be high or low

MD(O,$053)
Flag Function is shown in Table 12.3.

HITACHI 241

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

Display
Character

Label:
--

H61DSP

Description:
Table 12.3.

4.

Flag Functions

Label

Bit/Label
Bit 0

Function

H F L G

0

Indicates M signal is low

1

Indicates M signal is high

Sample Application

LMID

$ I, PMR

LMID

$ B, S MR

REMD

IMS

LMID

$ 9, CNTR

.................. Initialize SCI

LAI
LRA

$ 7

LAI

$ 2

LRA

S 7

SEMD

MFLG

LAMD

S 0 4 9

LBI

$ 0

P

S 2

LMAD

SRL

Control M signal, CLI signal, common
signal

.................. Store segment data in SRL, SRV

LAB
LMAD

SRU
.................. Start SCI

STS
SEMD

I E

Enable interrupts

Store display data
in display RAM

ORG

$ 2 0 0

DC

$177, S141, SIBS, SIES, $IC&,
$IE6, $IF6, $143, S1F7, $IE7

242 HITACHI

......... Segment data

Program Module Name:

Display
Character

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

H61DSP

Description:
5.

Basic Operation
(1)

10 digits of display data are sent to the HD61100A to display numerals on
an 8 segments x 10 digits LCD. Shift clock and data signal are controlled
by the block synchronous SCI of the HMCS404C.

(2)

Display data is stored in display of RAM before execution.
interrupt executes display of 1 byte of data.

(3)

Pointer to display RAM and counter for number of interrupts are
decremented every interrupt. CNTR(RAM) is reinitialized each time 10
interrupts are executed.

(4)

The first enabling interrupts are performed by the main program.
From then on, after execute SCI command SCI interrupts are generated
automatically each time segment data are outputted.

(5)

Indicates MFLG is status of M signal of HD61100A.

(6)

Data stored at the address indicated by Accumulator and B register is
transferred to Accumulator and B register, using the table look-up
function of the pattern generation instruction (P).

(7)

Lower 8 bits of word stores segment data.

Program

LAI

$ 1

LBI

$ 0

P

$ 2

Content of ROM

Content of register

B

A

0

CD

B

A

0

IT]

Each SCI

l!:Jcec

~$O200

)

(Notes)

ill
I 1

I

1

I

I

L_.J

B

After executing a P instruction in the above program sequence,
$41 is contained in B register and Accumulator.
($41 is stored in lower 8 bits of word located at $0201).
(Note)

If dotted area (bit 8) is $1 as
shown above, ROM data is
transferred to Accumulator
and B register after executing
the P instruction.

HITACHI 243

Prosram Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

Display
Character

Label:

H6lDSP

Flowchart:

- - - - [ Set SCI interrupt request flag

Save registers

- - - { Save register

CNTR-l
CNTR

--->

-

- - {

___ {

---{

244 HITACHI

Decremeot pointer to dieploy RAM

Test if interrupt has been executed
10 times
Reinitialize Y register pointer to display
data and counter for number of
interrupts

Program Module Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

Display
Character

~

H61DSP

Flowchart:

_ _ _ _ [ Test whether M signal will be high or
low

- - - - [

CLl signal = High. M signal = Low.
COMMON signal = High

- - - - [

CLI signal = Low. M signal
COMMON signal = Low

High.

- - - - [ Set MFLG

- - - - [

CLl signal = High. M signal
COMMON signal = Low

- - - - [

CLl signal = Low. M signal
COMMON signal = High

-

-

High.

Low.

- - [ Clear MFLG

- - - - [ Reinitialize X register pointer

___ {

Load di"play RAM pointer inro Y reg'"ter

----

Read segment Data

HITACHI 245

Program Module Name:

Display
Character

MCU: HMCS402C/
HMCS404C/HMCS408C

~

H6lDSP

Flowchart:

----[stor" ""","nt

data in SRL, SRV (RAM)

- - - - [ Start SCI

246 HITACHI

-

- --[Restore register

-

- - - Restore registers

12.4

SUBROUTINE DESCRIPTION

Subroutine Na"lle:

Function:

MCU: HMCS402C/
HMCS404C/HMCS408C

Initialize

1",bel'

H61INT

Stores display data

Basic Operation:

(1)

Initializes counter, CLl, M, COMMON signal, MFLG and others.

(2)

Executes only once is this routine.

Progra"ll 110dule Using This Subroutine:

- - - - [ Initialize counter
CLI signal = High. M signal
- - - - [ COMMON signal = High
CLI signal = Low. M signal
- - - - [ COMMON signal = Low

----[set

Low.

High.

MFLG

Load segment data into SRL, SRV(RAM)

- - - - [ Start SCI

HITACHI 247

12.5

PROGRAM LISTING

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
000l?
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
0002B
00029
00030
00031
00032
00033
00034
00035
00036
00037
0003B
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074

011

0000

SOURCE STATEMENTS
LLEN
TITLE

*

****

"CNTR
MFLG

"
"PMR

*~**

132
LIQUID CRYSTAL DRIVER (HD61100) CONTROL

RAM ALLOCATION
EQU
EQU

********************************

COUNTER FOR DISPLAY
M SIGNAL JUDGMENT FLAG

S05E
0.S053

SYMBOL DEFINITlONS

******~*********.*.*********

EQU
PORT MODE REGISTER
S004
SMR
EQU
SERIAL- MODE REGISTER
S005
EQU
LOWER SERIAL DATA REGISTER
SRL
S006
EQU
S007
UPPER SERIAL DATA REGISTER
SRU
IMS
EQU
1M OF SERIAL
1. S003
IFS
EQU
0.S003
IF OF SERIAL
EQU
ENABLE INTERRUPT
IE
O.SOOO
********************************************************

*
*

*
*

VECTOR ADDRESSES

"
"
********************************************************
150
150
150
150
150
000
000
150

010
010
010
010
010
023

0000
0002
0004
0006
0008
OOOA
0008
OOOC

*
*

ORG

SOOOO

H61MN
RESET
JMPL
JMPL
H61MN
INTO
JMPL
H61MN
INTl
JMPL
H61MN
TIMER-A
JMPL
H61MN
TIMER-B
NOP
NOP
JMPL
H61DSP
SERIAL
********************************************************

*
*
MAIN PROGRAM-: H61MN
*
*********************************************************"

"

"
OFO
lAl
lA8
189
160
184
219
224
OAF
200
IBl
000
31C
322

004
005
003
05F
000

0010
0011
0013
0015
0017
0019
0018
001C
0010
001E
001F
0020
0021
0022

*H61MN

H61MNl

PEND

ORG

SOOlO

LWI
LMID
LMID
REMD
CALL
SEMD
LYI
LXI
LAY
L8I
P
LMADY
BR
BR

SO
1.PMR
S8.SMR
IMS
H61INT
IE
S9
S4
SO
Sl
H61MNl
PEND

INITIALIZE W REGISTER
SELECT SO
SELECT SCK
CLEAR SERIAL INTERRUPT MASK
ENABLE INTERRUPTS
STORE DESTINATION
STORE DISPLAY DATA IN RAM
TEST IF ALL DISPLAY DATA IS STORED
END OF PROGRAM

********************************************************

"
"

NAME : H61DSP (DISPLAY CHARACTER)

*
*

"********************************************************"
*
"
ENTRY : DDATA (DISPLAY DATA)
*
"
RETURNS : NOTHING
*
""
********************************************************"
188 003
2FF
068
2FE
001
068
2FD
OAF
2FC

248 'HITACHI

0023
0025
0026
0027
0028
0029
002A
002B
002C

H61DSP

REMD
XMRA
LASPX
XMRA
XSPX
LASPX
XMRA
LAY
XMRA

IFS
SF
SE
SO
SC

SET SCI INTERRUPT REQUEST FLAG
SAVE REGISTERS

00075
00076
00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00lD8
00109
00110
00111
00112
00113
00114
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161

048
2F8
190
28F
194
347
239
194
18C
341
235
2D7
232
2D7
184
236
207
231
207
188
224
190
008
090
200
IB2
194
048
194
148
2FB
OC8
2FC
008
2FE
OE8
001
2FD
OE8
2FF
011

lA9
235
207
232
207
184
190
200
182
194
048
194
148
010

05E
05E
05E
053

053

053
05E

006
007

05E

053
049
006
007

0020
002E
002F
0031
0032
0034
0035
0036
0038
003A
OD3B
003C
0030
003E
003F
0041
0042
0043
0044
0045
0047
0048
004A
004B
004C
0040
004E
0050
0051
0053
0054
0055
0056
0057
0058
0059
o05A
005B
005C
0050
005E

005F
0061
0062
0063
0064
0065
0067
0069
006A
006B
0060
006E
0070
0071

LA8
$B
XMRA
OECREMENT DISPLAY RAM POINTER
LAMO
CNTR
AI
SF
TEST IF 10 TIMERS SCI INTERRUPT ARE COMPLETED
LMAD
CNTR
BR
H61DP2
$9
REINITIALIZE POINTER
LAI
LMAD
CNTR
TEST MSIGNAL IS HIGH DR LOW
MFLG
TMD
BR
H61DPl
$5
LAI
CL1=1.M=0.COMMON=1
LRA
S7
CL1=0.M=1.COMMON=0
$2
LAI
$7
LRA
SET MFLAG
MFLG
SEMD
CL2=1.M=1.COMMON=0
LAI
S6
H6lDPl
$7
CL2=0.M=0.COMMON=1
LRA
$1
LAI
$7
LRA
CLEAR MFLAG
REMD
MFLG
REINITIALIZE X REG POINTER
$4
H6lDP2
LXI
LOAD DISPLAY RAM POINTER INTO Y REG
LAMD
CNTR
LYA
READ SEGMENT DATA
LAM
$0
LBI
$2
P
STORE SEGMENT DATA IN RAM
LMAD
SRL
LAB
LMAD
SRU
SCI START
STS
$B
RESTORE REGISTERS
XMRA
LBA
$C
XMRA
LYA
$E
XMRA
LXA
XSPX
$D
XMRA
LXA
$F
XMRA
RTNI
********************************************************

*
*
NAME : H61INT (START SCI)
*
*
**********************************************************

$9.CNTR
LMID
INITIALIZE COUNTER
$5
LAI
CL1=1.M=0.COMMON=1
LRA
$7
LAI
S2
CL1=0.M=1.COMMON=0
$7
LRA
MFLG
SET MFLAG
SEMD
$049
LAMD
LOAD SEGMENT DATA
$0
LBI
$2
P
LMAD
SRL
STORE SEGMENT DATA IN RAM
LAB
LMAD
SRU
STS
SCI START
RTN
********************************************************

H61INT

*
*

DATA TABLE

*

*
*

********************************************************

*
100
101
102
103
104
105
106
107
108
109

0100
0101
0102
0103
0104
0105
0106
0107
0108
0109

*

*
177
141
1B3
lE3
1C5
1E6

0200
0201
0202
0203
0204
0205

*

ORG

$100

DC
DC
DC
DC
DC
DC
OC
DC
DC
DC

$100
$101
$102
$103
$104
$105
S106
S107
$108
$109

ORG

S200

DC
DC
DC
DC
OC
DC

$177
$141
$lB3
SlE3
SlC5
$lE6

RAM DATA

SEGMENT DATA
0
1
2
3
4
5

HITACHI 249
--~-----~--

--

-~

-"-----_._-

-------~----

00162
00163
00164
00165
00166
00167

1F6
143
lF7
lE7

250 HITACHI

DC
DC
DC
DC

0206
0207
0208
0209

*

END

$lF6
$143
$lF7
SlE7

6
7

8
9

SECTION 13.

13.1

HD61830 (LM200) GRAPHIC MODE

HARDWARE DESCRIPTION

13.1.1

Function
Initializes graphic mode and displays dot graphics on the LM200
liquid crystal module.

13.1.2

Microcomputer Operation
The HMCS404C transfers display data to the dot matrix liquid crystal
graphic display controller LSI HD61830 (LCTC) from port R onto the
LCTC data bus (DBO - DB7), and transmits control signals E, R/W, and
RS through port D.

13.1.3

Port D and port R are controlled by software.

Peripheral Devices
HD61830 LCTC:

Receives control signals and display data from the

HMCS404C and in turn controls the HM6116 Display RAM and LM200.
LM200 Liquid Crystal Module:

Receives graphic display data and

control signals from the HD61830 LCTC.

A resolution of 64 x 240

pixels is provided in LM200 graphic mode.

In this application, the

graphic figure shown in Fig. 13.5 is displayed.

HITACHI 251

13.1.4

Circuit Diagram
LCTC control circuit is shown in Fig. 13.1.

MCU
HMCS404C

+5v

(~~g~: ~: g)
HV
50 TEST

LCTC
HD618.0

+5V

Liquid crystal module

Dl,c=J'io
LM'OO

D,

+5V

32

lookfl

L,

vee
56
55

152076
1"ID74HC14
49 RESET

D,
D, 50
D. 10
R,
Rll
R, 1.
R,

•

R"

15

R
53 GND

89kll
15pF

1. WE

Fig. 13.1.

a52HITA0HI

HV

VnJ> '

M

V..

FLM

V..

MAo
MA,
MA,
MA,
MA.
MA,
MA.,
MAo
MA.
MA.
MAIo
MD.
MD,
MD,
MD,
MD,
MD,
MD,
MD,

LCTC Control Circuit

-5V

..

HV

13.1.5

Pin Functions
Pin functions at the interface between the HMCS404C and LCTC are
shown in Table 13.1.
Table 13.1. Pin Functions
Pin Name
(HMCS404C)

Active Level
Input/Output (High or Low) Function

D2

Output

Dl

Output

DO

Output

RlO

Input/Output

Rll

Input/Output

R12

Input/Output

Pin Name
(LCTC)

High

Enables signal

E

R/W

High

Reads data

Low

writes data

High

Selects instruction
register

Low

RS

Selects data register
Data lines

DBO

R13

Input/Output

DB3

R20

Input/Output

DB4
DBS

R21

Input/Output

R22

Input/Output

R23

Input/Output

DB?

HITACHI 253

13.1.6

Hardware Operation
The timing chart for interfacing between the HMCS404C and each signal

is shown in Fig. 13.2.

Q) and @ in Fig. 13.2. show timing for read

and write.

Q) Data from LCTC can be read during Q) period.

@ Data

can be written to LCTC at the falling edge of signal E.

LCTC pin name
RS. R/W

E

DBO - DB7
(HMCS404C"" LCTC) _ _ _ _ _ _ _ _ _ _ _ _ _...J

DBO - DB7
(HMCS404C + LCTC)

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J

Fig. 13.2.

.254 'H'ITAOHI

HMCS404C LCTC Interface

13.2

SOFTWARE DESCRIPTION

13.2.1

Program Module Configuration
The program module configuration for graphic display on the liquid
crystal module is shown in Fig. 13.3.

L2HMN
Main
Ptograp!

L 2 HI NT

I

Ini tialize
LCTC

~

L2HWT

L2HMVE

~

Move
Cursor

L:..

I

Write
Data

~

Fig. 13.3. Program Module Configuration

13.2.2

Program Module Functions
Program module functions are summerized in Table 13.2.

Table 13.2.

Prugram Module Functions

No.

Program Module Name

Label

Function

0

Main Program

L2HMN

Demonstrates graphic display on LM200

1

Initialize LCTC

L2HINT Initializes LCTC for graphic mode

2

Move Cursor

L2HMVE Initializes LCTC cursor address

3

write Data

L2HWT

Writes instructions and data to the LCTC

HITACHI 255

13.2.3

Program Module Process Flow (Main Program)
The following flowchart (Fig. 13.4) demonstrates the process for
displaying graphics on the LM200 liquid crystal display, using the
modules described above.

Fig. 13.5 shows this applications display.

Main program

~--"'T""---'-----[ Initialize W register
LL_ _-.-_ _..IJ - - - - -

Execute L2HINT to initialize LCTC
[ for graphic mode

LL.._ _-,-_ _..u - - - - - [

Execute L2HCLR to clear display

RAM

Clear Y register used to count the
----- [ number of columns of display data
~---,-~--'
written to the LM200

.--_.1---.., ----{ Olm

pointo<

0' di.play ""C<>

Clear RAM counter used to indicate
----- [ the number of rows of display data
.--_.1-_-..,
written to the LM200

Store entry argument for L2HMVE
to initialize LCTC cursor address to
$0084

LL_ _-.-_ _..LJ - - - - - [

Initialize LCTC cursor address

r----l...---.-----[ ~:;
Fig. 13.4.

256 HITAOtil

instruction for display data
into entry argument of

Program Module Sample Application

Store display data in entry argument
of L2HWT

~-----[ the I/O port

Write display data to the LCTC through

Increment pointer to display data

Increment the counter indicating the
------ [ number of columns of display data
written

Yi=5

-----

[

Test if display data has been written
for 5 consecutive rows

..J----- [ Clear Y register

L -_ _-.-_ _

Fig. 13.4.

Program Module Sample Application (Cont.)

HITACHI 257

Add 30 to cursor address to move to
next row

Increment RAM counter indicating how
many rows of display data written

if 50 rows of display data have
written

Fig. 13.4.

258 HITACHI

Program Module Sample Application (Cont.)

Fig. 13.5.

Result of Program Module Execution

HITACHI 259

13.3

PROGRAM MODULE DESCRIPTION

Program Module Name: Initialize LCTC

Function:

Label: L2HINT

MCU: HMCS402C/
HMCS404C/HMCS408C

Initializes LCTC for graphic mode.

Arguments: None

Changes in CPU
Registers and FlaSls:

Specifications:
1 word

= 10

bits
31

B
x

ROM (Words) :
RAM (Digits) :

2

X

Y

Stack (Digits) :

0

•

•

No • of cycles: 1538

SPX

SPY

•

•

A
x

W

Reentrant:

No

Relocatable:

No

Interrupt OK?:

Yes

•
CA
x
•
x :

ST
x

Not Affected
Undefined
Result

Description:
1. Function Details
(1) Program module L2HINT has no arguments.
(2) After execution of L2HINT, the LCTC enters graphic mode and the LM200
display screen is cleared.
(3) L2HINT uses the subroutines shown in Table 13.3.
Table 13.3.

Subroutines Used by L2HINT

Subroutine Name
Check Busy Flag

Label Name

Function

L2HBSY

Checks LCTC busy flag

Specifications Notes:
The number of cycles indicated is the minimum number of cycles required by
subroutine L2HBSY.

260 HITACHI

Program Module Name: Initialize LCTC

Label:
--

MCU: HMCS402C/
HMCS404C/HMCS408C

L2HINT

Description:
2. User Notes
As this routine uses the P instruction (Pattern Generation Instruction),
pay close attention to the data reference addresses of the data table.

3. RAM Allocation

FIE:DICIBIAI9:81716151413:2:110

o2
o3
04

o5

:

:

:

;

I

:

I

I

:

I

-:- -t- -t--

:

:

~

~--~--~---~----:--t--~--~--~--i--'l.--

--:--:--t--~-:--:---:--:---:-~--IL __ __
I
I
I

:

:

I

:

I

I

I

I

I

I

i

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

--t--f---l--l--t--t-- --:-- +- -t---j--:--+ - -~ --,--t-I

I

I

--~-~--~--~--~--~--t--+--~--~--:--~--i--t--t-­

~~L-~__J-__L-~__~__~I--~'--ll---I~_~l'==l~~~:~~~l'==JL~Jl-----

Fig. 13.6. RAM Allocation

Label

RAM

b3

INTA

Description

bO
Holds lower digit of source address

MD($03A)

b3

INTB

bO

III

Holds upper digit of source address

MD($03B)

4. Sample Application

II

CALL

L2HINT

II

... '"

Call L2HINT

HITACHI 261

Program Module Name:

Initialize LCTC

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:
--

L2HINT

Description:
5. Basic Operation
(1) The instruction and data elements shown in Table 13.4 must be loaded into
the instruction and data registers in corresponding pains to initialize
LCTC. Program module L2HINT loads data shown in Table 13.4.
(2) RS signal is used to switch between the two registers;
High: Instruction register, Low: Data register
Table 13.4.

Data to be stored in LCTC

Instruction

Data

Function

$00

$32

Selects Display ON, Master mode and Graphic mode

$01

$07

Selects 8 bits of horizontal dots per character in
display

$02

$lD

Selects 30 bytes of horizontal bytes in the graphic
mode

$03

$lF

Selects 1/32 duty in multiplex display

$08

$00

Selects display starting address to $0000

$09

$00

$OA

$00

$OB

$00

Selects cursor address to $0000

(3) RS, R/W, and E signals are controlled by port DO' port Dl and port D2'
(4) Initialization data shown in Table 13.4 is previously stored in the
data table in ROM.

262 HITACHI

MCV: HMCS402C/
HMCS404C/HMCS408C

Program Module Name: Initialize LCTC

Label:

L2HINT

Flowchart:

r------L----~

-----l~tore

address in RAM for the Pattern

~nstruct~on

~~==:;:r_--J
LL_ _,..-_ _.I..J - - - - -

[Check LCTC busy flag

Load from RAM the data table address
-- --- [ for instructions or data into
r-----~----~
Accumulator and B register

L-____-,-_____ - - - - - [ Set

L-_ _,..-_ _ _ - - - - -

[set R/W signal low

. . J -----[ Set

L _ _,..-_ _

L------r------J

RS signal high

E signal high

_____ [output instruction through ports Rl
and R2 by the Pattern instruction

L ____-.-____-1-----[set

E signal low

L ____.,-____.....J-- - - - [Increment

---l-----[

L-____-,-____

Set RS signal low

....J-----[ Set

L-_ _-.-_ _

L-____-.-____---l

data table pointer

E signal high

_____ [output data through ports Rl and R2
by the pattern instruction

HITACHI 263

Program Module Name:

Initialize LCTC

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

Flowchart:

'----T"""--.... - - - - - [

Set E signal low

point

if initialization complete

264 HITACHI

L2HINT

Program Module Name: Move Cursor

Function:

Label:

L2HMVE

I

Loads cursor address value stored in DTADDR(RAM) into LCTC cursor
address counter.

Changes in CPU

Storage
Location

No. of
Digits

Reg:isters and Flags:

DTADDR
(RAM)

4

1 digit

Contents
Cursor
address

=

4 bits

Ar'2:uments:

Entry

MCU: HMCS402C/
HMCS404C/HMCS408C

Specifications:
1 word

=

10 bits

A

B

ROM (Words) :

29

x

•

RAM (Digits) :

8

X

Y

Stack (Digits) :
No. of cycles:

•

•

SPX

SPY

•

•

W

4
254

Reentrant:

No

Relocatable:

No

Interrupt OK?:

Yes

•

Returns

CA
x
•
x

:

ST
x

Not Affected
Undefined
Result

Description:
1. Function Details
(1) Argument details
DTADDR(RAM): Holds cursor address value to be loaded into cursor address
counter as 4-digits hexadecimal number.
(2) Program module L2HMVE loads cursor address value into cursor address
counter to change cursor address on display.
(3) Program module L2HMVE calls other program modules and subroutines shown
in Table 13.5.

Specifications Notes:
"No. of cycles" in "Specifications" represents the number of cycles needed
when subroutine L2HBSY is executed by the minimum cycles.

HITACHI 265

Program Module Name: Move Cursor

IL-,'

MCU: HMCS402C/
HMCS404C/HMCS408C

L2HMVE

Description:
Table 13.5. Program Modules and Subroutines Called in,L2HMVE
Program Module/
Subroutine Name
Write Data
to LCTC
Check Busy
Flag

Label

Function

L2HWT

Writes data to LCTC through I/O port of the
HMCS404C
Checks LCTC busy flag

L2HBSY

2. User Notes
The RAM area for storing the 4-digits hexadecimal of the cursor address
must be allocated.
3. RAM Allocation

FIE:DrC:BrA:91817:6i5r4:3:2:1:0

o2
o3

_ _ L __

o4
o

5

--:--E::::t3--:--t--;~_...J
:

:

:

:

:

I

1

I

:

I

:

:

I

I

I

I

I

I

:

I

I

:

I

:

:

I

:

:

1

:

1

I

:

:

:

I

I

J

I

I

I

I

I

I

:

_____ .J__

--t--~--~--4--t--~-~--+--t--~-1--+--~--~-i---~-~--~--~--~--~--t--+--~--~--:--~--i--t--~-­

~~6~l-~--~~--~--~-LI--~'

Fig. 13.7.
Label

__lr__J:-=11~J~~-=~I~'~~l'~l~~~l'---

RAM Allocation
Description

RAM

b15
DTADDR: DTADDR+l:
DTADDR+2 :DTADDR+3

~~
_
~ J~-

bO

~

MD($035, $034, $033, $03.)

b7

bO

INSTRL: INSTRU

Holds cursor address to be
stored in the cursor address
counter; consists of 4 hexadecimal digits

Holds value to initialize the
LCTC instruction register

MD($037, $036)

b7

bO

Holds value to initialize the
LCTC data register

DATARU:DATARL
MD($03D, $03C)

266 HITACHI

Program Module Name: Move Cursor

MCU: HMCS402C/
HMCS404C/HMCS408C

ILa~l'

L2HMVE

Description:
4. Sample Application

DTADDR

II

'" Allocate RAM area for storing
the 4-digit cursor address in
the user program

EQU

$ 0 8 2

LMID
LMID

$

o.

$

o. DT ADD R+ 1

DTADDR

LMID

$ 8.

LMID

$ 4. DTADDR+3

CA L L

L 2 HMV E

DTADDR+2

II

}

Load the cursor address stored
... in the user program into entry
arguments

... Call L2HMVE

5. Basic Operation

(1) To effect display at any location on LM200, the cursor address must be
written before writing display data.
(2) The cursor address consists of four digits.
Program module L2HWT is
used to first set the lower digit and then the upper digit.

HITACHI 267

Program Module Name: Move Cursor

M9}: HMCS402C/ .

HMCS404C/HMCS408C

I~

L2HMVE

Flowchart:

~-----[

Store instruction for writing cursor
address to the LCTC (lower digits)
into L2HWT entry arguments

~-----r

Store cursor address (lower digits)
into L2HWT entry arguments

~-----[ to the LCTC

Write cursor address (lower digits)

~----[
,....----L----- - - - - {

Store instruction for writing cursor
address to the LCTC (upper digits)
into L2HwTentry arguments

Store cursor address (upper digits)
into L2HWT entry arguments

~-----[ to the LCTC

write cursor address (upper digits)

268 HITACHI

Program Module Name: Write Data

Function:

=4

1 digit

Contents

Storage No. of
Location Digits

Returns

L2HWT

Writes data or instructions to the LCTC through an HMCS404C I/O port
under the control of signals RS, R/W and E.

Ar9:uments:

Entry

Label:

MCU: HMCS402C/
HMCS404C/HMCS40SC

LCTC
INSTRU
instruc- (RAM)
tion
INSTRL
(RAM)
DATARU
LCTC
(RAM)
data
DATARL
(RAM)

--

bits

Registers and Flags:

1

22

B

ROM (Words) :

x

•

RAM (Digits) :

4

Stack (Digits) :

4

1

X

Y

1

•

•

SPX

SPY

•

•

1

1 word = 10 bits

A

W

--

--

Speci fica tions:

Changes in CPU

No. of cycles:

96

Reentrant:

No

Relocatable:

No

Interrupt OK?:

Yes

•

•
x

CA

ST

x

x

:

Description:

Not Affected
Undefined
Result

CD

Arguments

l . Function Details

!""""
DATAHU

: IlATAllL
( IlAM)

(1) Argument details
INSTRU,INSTRL(RAM): Holds value to
initialize the LCTC instruction
register
DATARU,DATARL(RAM): Holds value to
initialize the LCTC data register

b7

bO

:cI
b7
bO
I :uI

i A~m-RL I

Entry

0

Il

I
®

Result

K~

--bO

b7

Note: Display position is different
from the cursor address

Fig. U.S. Example of L2HWT Execution

Specifications Notes:

The number of cycles indicated is the minimum number of
cycles required by subroutine L2HBSY.

HITACHI 269

~

Program Module Name: Write Data

M_C_U_:__HMCS404C/HMCS408C
HM
__C_S_4_0_2C_/________
L..

.
IL..L_a_b_e_l_:_L_2_H_WT
______

Description:
(2) Fig. 13.8 shows an example of program module L2HWT execution, in which
display data $BB is written to the LCTC.
(3) L2HWT uses the subroutines shown in Table 13.6.

Table 13.6.

Subroutines Used by Module L2HWT

Subroutine Name

Label Name

Function

Check Busy Flag

L2HBSY

Checks LCTC busy flag

2. RAM Allocation
I 9!BI7 ' 61514 ' 31211 ' 0
FIEIDICIBIA
I
I
I
I
I
I
I
I
I
I

o2
o3
o4
o5
o6

b---

I
I

I
I

I
I

t

I

I
I

I
I

I

I
I

I

I

I
I

I

I
I

I
I

I

--~--~---1---:--~--_---i-~---i---t---t---

__ ~ __ ~ __ J __ J__ J___
:

I

:

I

~

:

:

I

I

I

I

I

I

I

--i--+--~ --i--t--{--~--

__~ __ ~ __ ~ __ ~ __:__

+- -t---j--:--t - -~--I---t-:

:

:

:

I

:

:

:

I

I

I

I

I

I

I

I

--~-~--~--~--~--~--t--+--~--~--:--~--i--t--t-I
I
I
I
1 i- _~, 1 L 1--

Fig. 13.9.

Label

RAM Allocation

Description

RAM

b7

bO

Holds value to initialize
the LCTC instruction register

INSTRU: INSTRL(RAM)
MD($037. $036)

b7

bO

Holds value to initialize
the LCTC data register

DATARU:DATARL(RAM)
MD($03D.$03C)

270 HITACHI

~

~IL_L_a_b_e_1_:

Program Module Name: Write Data

M_C_U_:__HMCS404C/HMCS408C
HM
__C_S_4_0_2C_/________
L_

.

__
L2_H_WT
______

~

Description:
3. Sample Application

WORKIU

EQU

$ 03 7

WORKIL

EQU

$ 0 36

WORK 2 U

EQU

$ 03 D

WORK 2L

EQU

$ 03 C

LAMD

WORKIL

LMAD

INSTRL

LAMD

Allocates RAM area in the user
program to store value to
} ...... ini~ialize the instruction
reg~ster

Allocates RAM area in the user
} ...... program to store value to
initialize the data register

WORKIU

f

LMAD

IN STRI-'

)

LAMD

WORK2L

LMAD

DATARL

LAMD

WORK2U

LMAD

DATARU

CALL

L2HWT

1/u...._ _ _ _ _ _ _ _ _JJil

Store value to initialize the
...... instruction register into
entry arguments

Store value to initialize the
} ...... data register into entry
arguments

......

Calls L2HWT

HITACHI 271

Program Module Name: Write Data

MCU: HMCS402C/
HMCS404C/HMCS408C

IL.bel'

L2HWT

Description:
4. Basic Operation
(1) When writing data to the LCTC, the microcomputer must store data in
the LCTC instruction and data registers in corresponding pairs. To
switch between instruction and data registers, the RS signal is used
(high for instruction and low for data).
Fig. 13.10 shows the flowchart for writing data to the LCTC.

~-r---_I""{

Checks whether the LCTC is in
operation
Specify LCTC instruction register

Perform data write when E signal
changes from high to low

I····{

Specify LCTC data register

I····{

Perform data write when E signal
changes from high to low

1L-_S_e_t_R_S_S_i_g,..n_a_l_l_O_W_ _.....

I

I

Write data to data
register

Fig. 13.10. Procedure for Writing Data to LCTC
(2) When the LCTC is in operation, the microcomputer cannot write data to
it. However, LCTC operation can be distinguished by the LCTC busy flag.
Thus in this case, program module L2HWT calls subroutine L2HBSY to check
the busy flag and determine whether the LCTC is in operation.
Busy flag

1: LCTC is in operation, data cannot be written

Busy flag

0: Data can be written to the LCTC

272 HITACHI

Program Module Name: Write Data

MCU: HMCS402C/
HMCS404C/HMCS408C

I

L.be"

L2HWT

Flowchart:

U-_ _..--_ _u-----[

Check busy flag

....1-----[ Set

1..-_ _, -_ _

. .J -----[

I..-_ _..--_ _

RS signal high

Set R/W signal low

. . 1 -----[ Set

1..-_ _..--_ _

E signal high

r----""---,----{ Lo"" d.,.

Co inib.'i,e "e

...J-----[

Set E signal low

...J-----[

Set RS signal low

I..-_ _..--_ _

I..-_ _..--_ _

....1-----[ Set

1..-_ _..--_ _

r-""'"'"-;;:-,~,..--,----_l
1..-_ _, -_ _...... - - - - - [

d.,. regb'er

E signal high

La"" d.c.

'0

iniU.H,. "e d.c. regi"er

Set E signal low

HITACHI 273

13.4

SUBROUTINE DESCRIPTION

Subroutine Name:
Check Busy Flag

Function:

MCU: HMCS402C/
HMCS404C/HMCS408C

Label: L2HBSY

Checks whether LCTC is in operation and waits for ready state.

Basic Operation:
(1) Since the LCTC cannot be accessed by the microcomputer while it is in
operation, the LCTC busy flag must be checked.
(2) The RS, R/W and E signals are controlled by port R2 to read the busy flag.
Program Module Using This Subroutine: L2HWT, L2HINT, L2HMVE
Flowchart:

'--__,-__. .J -----[

Initialize port R2 as input

'--__,-__..J-----[

Set RS signal high

.--_-:--,:;~~=r--...J -----[ Set R/W signal

'--__,-__..J-----[
'--__,-__. J

high

Set E signal high

_____ [ Read value of LCTC busy flag into
the Accumulator

'--__,-__...J-----[ Set

E signal low

- - - - { Repea' loop =Hl buoy flag io mo
CA=l

274 HITACHI

Subroutine Name:

Function:

MCU: HMCS402C/
HMCS404C/HMCS408C

Clear Display

Label: L2HCLR

Clears the contents of display RAM in the LM200 and clears
the liquid crystal display.

Basic Operation:

Initializes cursor address to "$0000", calls L2HWT and
stores "$00" consecutively up to "$0780" in RAM.

Program Module Using This Subroutine:

L2HINT

Flowchart:
Store instruction "$AO" in L2HWT
----- [ entry argument for writing lower
~----~----~
byte of cursor address
~__~~~~~

_____ [ Store lower byte of cursor address
in L2HWT entry argument

u-----r------l.I

_____ [ Write lower byte of cursor address to
the LCTC
L2HWT
upper
of cursor address to

minuend "$780" for using in SUB

.-__~==~~__~

_____ [ Store subtrahend "$001" for using in
SUB

____~____~

_____ [store the data for transfering to the
LCTC instruction register

u-____~----u

_____ [ write the display data and clears the
display RAM

~

u-___r-_---l.I- HMIN:MMIN

:1HIr#$ooo

- - - [

Call SUB
the contents of display
to $780

HITACHI 275

Subroutine Name:

MCU: HMCS402C/
HMCS404C/HMCS408C

Subtract 12 Bits Binary Data
Function:

I~

SUB

.

Performs subtraction of 12 bits binary data in RAM, and stores
result in RAM.

Basic Operation:

When substraction is performed with 2 or more digits, the same
operation sequence is repreated for each digit. Subtraction
result is stored in RAM for minuend.

Program Module Using This Subroutine:

None

Flowchart:
SUB

I

SUB

1'-__

l_....
....,..C_A_--JI----- [

Set CA for borrow process

I

I

l

LSUB-+A

I

I----- [ Subtract lower digits 'and store

subtraction result in RAM for minuend

-----

l

I
-----

r

LMIN-A-CAI
-+LMIN

I

l
I

M S U B-+ A

I

I

MMIN-A-CA I
-+MMIN

I
I

I

H S U B-+A

I

HMIN-A-crl
-+HMIN
I

I
(

276 HITACHI

R T N

Subtract midd1ey digits considering
CA (borrow) and store subtraction
result in RAM for minuend

Subtract upper digits considering
CA (borrow) and store subtraction
result in RAM for minuend

13.5

PROGRAM LISTING

ST-NO

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057

100

0000

SOURCE STATEMENTS
LLEN
TITLE

132
HD61B30 (LM200) GRAPHIC MODE

*
**** RAM ALLOCATION ********************************
*COUNTU EQU
$030
UPPER DIGIT OF ROW COUNTER
COUNTL
DTADDR
INSTRU
INSTRL
DSPCTU
DSPCTL
INTA
INTB
DATARU
DATARL
HMIN
MMIN
LMIN
HSUB
MSua
LSU8

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

S031
S032
S036
S037
S038
S039
S03A
S03B
S03C
S03D
S03E
S03F
S040
S041
S042
S043

LOWER DIGIT OF ROW COUNTER
CURSOR ADDRESS
UPPER LCTC INSTRUCTION REGISTER DATA
LOWER LCTC INSTRUCTION REGISTER DATA
UPPER DIGIT OF DISPLAY DATA POINTER
LOWER DIGIT OF DISPLAY DATA POINTER
LOWER DIGIT OF SOURCE STARTING ADDR
UPPER DIGIT OF SOURCE STARTING ADDR
UPPER LCTC DATA REGISTER DATA
LOWER LCTC DATA REGISTER DATA
UPPER DIGIT OF MINUEND
MIDDLE MINUEND
LOWER DIGIT OF MINUEND
UPPER DIGIT OF SUBTRAHEND
MIDDLE DIGIT OF SUBTRAHEND
LOWER DIGIT OF SUBTRAHEND

********************************************************

150
150
150
150
150
000
000
150

OlD
010
010
010
010
010

0000
0002
0004
0006
OOOB
OOOA
OOOB
OOOC

*
*
VECTOR ADDRESSES
*
*
**********************************************************
*
ORG
SOOOO
*
JMPL
RESET
L2HMN
JMPL
JMPL
JMPL
JMPL
NOP
NOP
JMPL

L2HMN
L2HMN
L2HMN
L2HMN

INTO
INTl
TIMER-A
TIMER-B

L2HMN

SERIAL

********************************************************

*
*
MAIN PROGRAM : L2HMN
*
*
**********************************************************
*
ORG
SOO10
OFO
160
160
210
lAO
lAO
lAO
lAO
lAO
lAO
lA8

06F
OCl
038
039
030
031
032
033
034

0010
0011
0013
0015
0016
0018
001A
001C
001E
0020
0022

*L2HMN

LWI
CALL
CALL
LYI
LMID
LMID
LMID
LMID
LMID
LMID
LMID

SO
L2HINT
L2HCLR
SO
SO. DSPCTU
SO. DSPCTL
SO.COUNTU
SO.COUNTL
SO.DTADDR
SO.DTADDR+l
SB.DTADDR+2

INITIALIZE W REGISTER
INITIALIZE LCTC FOR GRAPHIC MODE
CLEAR DISPLAY
CLEAR COLUMN COUNTER
CLEAR DISPLAY DATA POINTER
CLEAR ROW COUNTER
STORE CURSOR ADDRESS(UPPER)
STORE CURSOR ADDRESS(LOWER)

HITACHI2n

00058
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076

00077
00078
00079
00080
00081
00082
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114

1A4
160
lAC
lAO
190
OC8
190
182
194
048
194
160
OEC
231
118
194
230
118

035
OA4
037
036
038
039
030
03C
08E
039
039
038

194 038

05C
075
32C
210
OEC
23E
118
194
231
118
194
230
118
194
230
118
194
OEC
231
118
194
230
118
194
123
326
122
326
36E

035
035
034
034
033
033
032
032
031
031
030
030
030
031

278 HITACHI

0024
0026
0028
002A
002C
002E
002F
0031
0032
0034
0035
0037
0039
003A
0038
0030
003F
0040

L2HMN1
L2HMN2

OO~2

0044
0045
0046
0047
0048
0049
004A
004C
004E
004F
0051
0053
0054
0056
0058
0059
0058
0050
005E
005F
0061
0063
0064
0066
0068
006A
0068
0060
006E

PEND

LMIO
CALL
LMID
LMIO
LAMD
L8A
LAMD
P
LMAD
LA8
LMAD
CALL
REC
LAI
AMCD
LMAD
LAI
AM CO
LMAD
IY
YNEI
BR
LYI
REC
LAI
AMCD
LMAD
LAI
AMCD
LMAD
LAI
AMCD
LMAD
LAI
AMCD
LMAD
REC
LAI
AMCD
LMAD
LAI
AMCD
LMAD
INEMD
8R
INEMD
8R
8R

$4.DTADDR+3
L2HMVE
$C.INSTRL
$O.INSTRU
DSPCTU

WRITE CURSOR ADDRESS TO LCTC
LOAD INSTRUCTION

DSPCTL
$2
DATARL

PATTERN

DATARU
L2HWT
$1
DSPCTL
DSPCTL
$0
DSPCTU
DSPCTU
S5
L2HMN2
SO
SE
DTADDR+3
DTADDR+3
Sl
DTADDR+2
DTADDR+2
SO
DTADDR+1
DTADDR+1
SO
DTADDR
DTADDR
Sl
COUNTL
COUNTL
SO
COUNTU
COUNTU
S3.COUNTU
L2HMN1
S2.COUNTL
L2HMN1
PEND

LOAD DISPLAY DATA

WRITE DISPLAY DATA TO LCTC
INCREMENT POINTER

INCREMENT COLUMN COUNTER
TEST IF COLUMN COUNTER c5
CLEAR COLUMN COUNTER
ADD CURSOR ADDRESS TO 30

INCREMENT ROW COUNTER

TEST IF ROW COUNTER -50
LOOP UNTIL DISPLAY END
END OF PROGRAM

********************************************************

*
*
NAME : L2HINT (INITIALIZE LCTC)
*
*
**********************************************************
*
*
ENTRY
NOTHING
*
*
RETURNS : NOTHING
*
*
*
*

00115
00116
00117
00118
00119
00120
00121
00122
00123
00124
00125
00126
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171

lAO
1A5
160
190
OC8
190
2EO
261
2E2
000
18'1
000
262
281
260
2E2
000
181
000
262
281
194
380
373
010

03A
038
OE8
038
03A

03A

006F
0071
0073
0075
0077
0078
007A
0078
007C
0070
007E
007F
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
008B
008C
0080

********************************************************

L2HINT
L2HITl

L2HIT2

LMID
LMID
CALL
LAMD
L8A
LAMD
SEDD
REDO
SEDD
NOP
P
NOP
REDO
AI
REDO
SEDD
NOP
P
NOP
REDO
AI
LMAD
8RS
8RS
RTN

$O.INTA
$5.INTB
L2H8SY
INT8

STORE LOWER DIGIT OF SOURCE ADDRESS
STORE UPPER DIGIT OF SOURCE ADDRESS
CHECK LCTC 8USY FLAG

INTA
0
1
2

RS=l
R/W=O
E=l
OUTPUT INSTRUCTION 8Y PATTERN INSTR

2
$1
0
2

E=O
INCREMENT ADDRESS
RS=O
E=l
OUTPUT DATA 8Y PATTERN INSTRUCTION

2
$1
INTA
L2HIT2
L2HITl

E=O
INCREMENT ADDRESS
BRANCH IF INTA=F
BRANCH IF INTA/=F

********************************************************

160
2EO
261
2E2
190
201
190
202
262
260
2E2
190
201
190
202
262
010

OE8

008E
0090
0091
0092
037 0093
0095
036 0096
0098
0099
009A
0098
030 009C
009E
03C 009F
OOAl
00A2
00A3

*
*
NAME : L2HWT (WRITE DATA TO LCTC)
*
*
**********************************************************
*
ENTRY : INSTRU (UPPER HALF OF INSTR TO LCTC) **
*
INSTRL (LOWER HALF OF INSTR TO LCTC) *
*
DATARU (UPPER DATA TO LCTC)
*
*
DATARL
(LOWER DATA TO LCTC)
*
*
RETURNS
:
NOTHING
*
*
**********************************************************
L2HWT

CALL
SEDD
REDO
SEDD
LAMD
LRA
LAMD
LRA
REDO
REDO
SEDD
LAMD
LRA
LAMD
LRA
REDO
RTN

L2H8SY
0
1
2
INSTRL
1
INSTRU
2
2
0
2
DATARL
1
DATARU
2
2

CHECK LCTC 8USY FLAG
RS=l
R/W=O
E=l

STORE DATA WRITTEN TO INSTRUCTION REG
E=O
RS=O
E=l
STORE DATA WRITTEN TO DATA REG
E=O

********************************************************

HITACHI 279

00172
00173
00174
00175
00176
00177
00178
00179
00180
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
00198
00199
00200
00201
00202
00203
00204
00205
00206
00207
00208
00209
00210
00211
00212
00213
00214
00215
00216
00217
00211;1
00219
00220
00221
00222
00223
00224
00225
00226
00227
0022B

,.
,.
,.
,.
NAME : L2HMVE (SET CURSOR ADDRESS)
,.
,.
********************************************************
,.
,.
,.
,.
ENTRY : DTADDR (CURSOR ADDRESS VALUE)
,.
,.
RETURNS : NOTHING
,.
,.
lAO
1AA
190
194
190
194
160
lAO
lAB
190
194
190
194
160
010

036
037
035
030
034
03C
08E
036
037
033
030
032
03C
08E

1AA
lAO
lAO
lAO
160
lAB
160
1A7
1A8
lAO
lAO
lAO
1A1
lAC
160
160
120
3DB
120
3DB
120
3DB
010

037
036
030
03C
08E
037
08E
03E
03F
040
041
042
043
037
08E
OF6
03E
03F
040

280 HITACHI

********************************************************

00A4
00A6
00A8
OOAA
OOAC
OOAE
0080
00B2
00B4
00B6
0088
OOBA
OOBC
OOBE
OOCO

L2HMVE

00C1
00C3
00C5
00C7
00C9
00C8
OOCD
OOCF
0001
0003
0005
0007
0009
OODB
0000
OODF
00E1
00E3
00E4
00E6
00E7
00E9
OOEA

L2HCLR

LMID
LMID
LAMD
LMAD
LAMD
LMAD
CALL
LMID
LMID
LAMD
LMAD
LAMD
LMAD
CALL
RTN

SO.INSTRU
SA.INSTRL
DTADDR+3
DATARL
DTADDR+2
DATARU
L2HWT
$O.INSTRU
SB.INSTRL
DTADDR+1
DATARL
DTADDR
DATARU
L2HWT

STORE INSTRUCTION
STORE DATA

WRITE LOWER CURSOR ADDR TO LCTC
STORE INSTRUCTION
STORE DATA

WRITE UPPER CURSOR ADDR TO LCTC

,.********************************************************,.
,.
,.
NAME : L2HCLR (CLEAR DISPLAY)
,.
,.
********************************************************

L2HCR1

LMID
LMID
LMID
LMID
CALL
LMID
CALL
LMID
LMID
LMID
LMID
LMID
LMID
LMID
CALL
CALL
INEMD
BRS
INEMD
BRS
INEMD
BRS
RTN

SA.INSTRL
SO.INSTRU
$O.DATARL
SO.DATARU
L2HWT
$B.INSTRL
L2HWT
$7.HMIN
S8.MMIN
SO.LMIN
SO.HSU8
$0. MSUB
$1. LSUB
SC.INSTRL
L2HWT
SUB
SO.HMIN
L2HCRI
$O.MMIN
L2HCR1
SO.LMIN
L2HCR1

STORE INSTRUCTION

STORE LOWER CURSOR ADDRESS
WRITE
STORE
WRITE
STORE

LOWER CURSOR AD DR TO LCTC
INSTRUCTION
UPPER CURSOR ADDR TO LCTC
MINUEND

STORE SUBTRAHEND
STORE DATA
WRITE DISPLAY DATA(SOO) TO RAM
TEST IF DISPLAY RAM IS CLEARED

,.********************************************************
*,.
NAME : L2HBSY (CHECK BUSY FLAG)

*
,.
*********************************************************

00229
00230
00231
00232
00233
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
00248
00249
00250
00251
00252
00253
00254
00255
00256
00257
00258
00259
00260
00261
00262
00263
00264
00265
00266
00267
00268
00269
00270
00271
00272
00273
00274
00275
00276
00277
00278
00279
002BO
00281
00282
00283
00284
00285

OOEB
OOEC
ODED
OOEE
OOEF
OOFO
00F1
00F2
00F3
00F4
00F5

230
202
2EO
2E1
2E2
252
262
OA1
06F
3EF
010

L2HBSY

L2HBYl

LAI
LRA
SEDD
SEDD
SEDD
LAR
REDD
ROTL
TC
BRS
RTN

$0
2
0
1
2
2
2

SELECT R2 AS INPUT
RS=l
R/W=l
E=l
READ LCTC BUSY FLAG
E=O

L2HBYl

LOOP UNTIL BUSY FLAG=l

********************************************************

OEF
190
198
194
190
198
194
190
198
194
010

043
040
040
042
03F
03F
041
03E
03E

00F6
00F7
00F9
OOFB
OOFD
OOFF
0101
0103
0105
0107
0109

*
*
NAME : SUB (SUBTRACT 12-BIT 8INARY DATA)
*
*
**********************************************************
SUB

SEC
LAMD
SMCD
LMAD
LAMD
SMCO
LMAD
LAMD
SMCD
LMAD
RTN

SET CARRY

LSUB
LMIN
LMIN
MSUB
MMIN
MMIN
HSUB
HMIN
HMIN

SU8TRACT LOWER DIGITS
LMIN-LSUB-)LMIN
SUBTRACT MIDDLE DIGITS
MMIN-MSUB-)MMIN
SUBTRACT UPPER DIGITS
HMIN-HSUB-)HMIN

********************************************************

*
*
*
*
********************************************************
DATA TABLE (DATA TO INITIALIZE LCTC)

*
200
232
201
207
202
210
203
21F
208
200
209
200
20A
200
20B
200

0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
015A
0158
015C
0150
015E
015F

DRG

$0150

*

DC
$200
$232
DC
$201
DC
DC
$207
$202
DC
$210
DC
$203
DC
DC
$21F
$208
DC
DC
$200
$209
DC
DC
$200
DC
$20A
DC
$200
$20B
DC
DC
$200
********************************************************

*
*
DATA TA8LE (DISPLAY DATA)
*
*
**********************************************************

*

HITACHI 281

00286
00287
00288
00289
00290
00291
00292
00293
00294
00295
00296
00297
00298
00299
00300
00301
00302
00303
00304
00305
00306
00307
00308
00309
00310
00311
00312
00313
00314
00315
00316
00317
00318
00319
00320
00321
00322
00323
00324
00325
00326
00327
00328
00329
00330
00331
00332
00333
00334
00335
00336
00337
00338
00339
00340
00341
00342

100
100
180
10F
100
lCO
100
lCO
llF
100
lEO
101
lCO
llF
100
IF8
103
lE7
13F
100
1F8
1C7
IF8
13F
100
IFC
137
1CO
17F
100
1FE
10F
180
17F
100
1FE
107
180
13F
100
IFE
103
lC3
13F
100
IFF
183
1E7
13F
100
IFF
1C1
12C
llC
100

282 HITACHI

0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
020A
0208
020C
020D
020E
020F
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
021A
0218
021C
021D
021E
021F
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
022A
0228
022C
0220
022E
022F
0230
0231
0232
0233
0234
0235
0236

*

ORG

$0200

DC
DC
DC
DC
DC
OC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC

S100
S100
S180
S10F
S100
SlCO
S100
SlCO
$llF
$100
$lEO
$101
SlCO
Sl1F
S100
SlF8
$103
SlE7
S13F
S100
SlF8
SlC7
SlF8
S13F
S100
SlFC
S137
SlCO
S17F
S100
SlFE
SlOF
S180
S17F
S100
SlFE
S107
S180
$13F
S100
SlFE
S103
SlC3
S13F
S100
SlFF
$183
SlE7
S13F
S100
SlFF
SlC1
S12C
SllC
S100

00343
00344
00345
00346
00347
00348
00349
00350
00351
00352
00353
00354
00355
00356
00357
00358
00359
00360
00361
00362
00363
00364
00365
00366
00367
00368
00369
00370
00371
00372
00373
00374
D037?
00376
00377
00378
00379
00380
00381
00382
00383
00384
00385
00386
00387
00388
00389
00390
00391
00392
00393
00394
00395
00396
00397
00398
00399

IFE
lEO
168
120
100
17E
170
lCE
14C
100
13E
IFO
lCC
18E
100
110
1FO
10F
10F
101
110
lEO
187
113
101
110
lEO
183
118
102
108
180
101
10F
102
108
100
100
106
102
108
100
100
100
102
108
100
100
100
101
110
100
100
100
101
110
100

0237
0238
0239
D23A
0238
023C
0230
D23E
023F
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
024A
0248
024C
0240
024E
024F
0250
0251
0252
0253
0254
0255
0256
0257
0258
0259
025A
0258
025C
0250
025E
025F
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
026A
0268
026C
0260
026E
026F

DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC

SlFE
SlEO
S168
S12D
S100
S17E
S170
SlCE
S14C
S100
S13E
SlFO
SlCC
S18E
$100
S110
SlFO
SlOF
SlOF
S101
S110
SlEO
S187
S113
SlDl
S110
SlEO
S183
S118
S102
S108
S180
S101
S10F
S102
S108
S100
S100
S106
S102
S108
S100
SlOO
S100
S102
S108
SlOO
S100
S100
S101
S110
S100
S100
SlOO
SlOl
S110
SlOO

HITACHI 283

00400
00401
00402
00403
00404
00405
00406
00407
00408
00409
00410
00411
00412
00413
00414
00415
00416
00417
00418

140
108
101
120
180
lAO
184
100
120
100
113
1C3
101
140
100
10C
1CO
101
180

0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
027A
0278
027C
027D
027E
027F
0280
0281
0282

00419

101

00420
00421
00422
00423
00424
00425
00426
00427
00428
00429
00430
00431
00432
00433
00434
00435
00436
00437
00438
00439
00440
00441
00442
00443
00444
00445
00446
00447
00448
00449
00450
00451
00452
00453
00454
00455
00456

100
1F8
103
100
106
1CO
1F7
107
100
102
13C
lEO
107
100
101
140
1F8
101
100
103
180
1FF
103
180
107
100
1FF
103
180
10F
100
19F
103
1CO
10F
100
10E

0283

284 HITACHI

0284
0285
0286
0287
0288
0289
028A
0288
028C
028D
028E
028F
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
029A
0298
029C
0290
029E
029F
02AO
02A1
02A2
02A3
02A4
02A5
02A6
02A7
02A8

OC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC

$140
$108
$101
$120
$180
$lAO
$184
$100
$120
$100
$113
$lC3
$101
$140
$100
$10C
$lCO
$101
$180
$10i

$100
$lF8
$103
$100
$106
$lCO
$lF7
$107
$100
$102
$13C
$lEO
$107
$100
$101
$140
$lF8
$101
$100
$103
$180
$lFF
$103
$180
$107
$100
$lFF
$103
$180
$10F
$100
$19F
$103
$lCO
$10F
$100
$10E

00457
00458
00459
00460
00461
00462
00463
00464
00465
00466
00467
00468
00469
00470
00471
00472
00473
00474
00475
00476
00477
00476
00479
00480
00481
00482
00483
00484
00485
00486
00487
00488
00489
00490
00491
00492
00493
00494
00495
00496
00497
00498
00499
00500
00501
00502
00503
00504
00505
00506
00507
00508
00509
00510
00511
00512
00513

100
1CO
10F
100
102
100
1CO
llF
100
102
100
lEO
11F
100
103
100
lEO
10F
1C6
107
100
lEO
10F
1DF
liE
100
lEO
1AF
1FA
llA
100
lEO
lEF
1FA
llA
100
100
177
1F6
llA
100
lA8
176
1F6
13F
100
164
1FD
1FF
13F
100
1C2
1FE
1FF
13F
100
1C2

02A9
02AA
02A8
02AC
02AD
02AE
02AF
0280
0281
0282
0283
0264
0265
0286
0287
0268
0269
026A
0266
026C
0260
026E
026F
02CO
02C1
02C2
02C3
02C4
02C5
02C6
02C7
02C8
02C9
02CA
02C6
02CC
02CD
02CE
02CF
0200
0201
0202
0203
0204
0205
0206
0207
02DB
0209
02DA
0206
02DC
0200
02DE
02DF
02EO
02E1

DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC

S100
SlCO
S10F
S100
S102
S100
SlCO
SllF
S100
S102
S100
SlEO
SllF
S100
S103
SlOO
SlEO
S10F
SlC6
S107
S100
SlEO
SlOF
SlDF
SllE
S100
SlEO
SlAF
SlFA
SllA
S100
SlEO
SlEF
SlFA
SllA
S100
SlDO
Sl77
SlF6
SllA
S100
SlAB
S176
SlFB
S13F
S100
S164
SlFD
SlFF
S13F
S100
SlC2
SlFE
SlFF
S13F
S100
SlC2

HITACHI 285
- - - - _.. __._.

__._---_._------

00514
00515
00516
00517
00518
00519
00520
00521
00522
00523
00524
00525
00526
00527
00528
00529
00530
00531
00532
00533
00534
00535
00536
00537
00538
00539

1FF
1FF
llF
100
184
1FF
1FF
llF
100
198
1FF
1FF
10F
100
160
1FF
1FF
10F
100
100
1FE
1DF
107
100

286 HITACHI

02E2
02E3
02E4
02E5
02E6
02E7
02E8
02E9
02EA
02E8
02EC
02ED
02EE
02EF
02FO
02F1
02F2
02F3
02F4
02F5
02F6
02F7
02F8
02F9

OC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC

*

END

$lFF
$lFF
$llF
$100
$184
$lFF
$lFF
$llF
$100
$198
$lFF
$lFF
$10F
$100
$160
$lFF
$lFF
$10F
$100
$100
$lFE
$lDF
$107
$100

SECTION 14.
14.1

LIQUID CRYSTAL MODULE (CYCLE MEASUREMENT)

HARDWARE DESCRIPTION

14.1.1

Function
Controls LCD module H2570 and displays "CMOS MCU HMCS400" on the
liquid crystal display.

14.1.2

Microcomputer Operation
(1) Controls HD44780 (hereafter abbreviated LCD-II) data bus through
ports R4 and R5.
(2) Controls LCD-II control signals (Signals RS, R/W and E)
through port D.
(3) To control LCD-II data bus and control signals by HMCS404C
software, there are no restrictions in terms of timing.
(4) From HMCS404C display data is transmitted to LCD-II in the form
of ASCII code.

Liquid crystal driver HD44100 and the liquid

crystal display are automatically controlled by LCD-II which is
in turn controlled by the HMCS404C.
14.1.3

Peripheral Devices
(1) LCD controller driver HD44780 (LCD-II): Controls dot matrix
LCD of LCD module H2570.
(2) LCD driver HD44100: Drives LCD of LCD module H2570.
(3) LCD module H2570:

Provides a display of 16 characters x 1 row.

HITACHI 287

14.1.4

Circuit Diagram

MCV
HMCS404C

+SV

SoTEiT'
+SV
+5V

32

lOOkn

Liquid Crystal Module H2570

r------- - --- -- - ------1

(n~g:~~g)

Vee

1S2076
HD74HC14

R~~3~3--------~7~1~

3345
DBo HD.~'18 0
R" I"-'--------...;:...H DB, LCD _ I
RfoZ 36
DBz:

R"F--------=-=--l--j DB,
R

24

~:

DB.

R"

::2:

27

::

DB~

.---'+--l RS
~-'-+--l

IVW
E

Vee

Do
D,

D,

Vo
I

HD40·UOO

Vss

IL ___________________ _

Fig. 14.1.

288 HITACHI

H2570 Control Circuit

14.1.S

Pin Functions
Pin functions at the connecting interface of HMCS404C and LCD-II are
shown in Table 14.1.
Table 14.1.

Pin Functions
Active
level

Pin Name
(LCD-II)

Pin Name
(HMCS404C)

Input/
Output

DO

RS
Input/
Low
Selects instruction register
Output ---H-i-gh------S-e-l-e-c-t-s--d-a-t-a--r-e-g-i-s-t-e-r---------

Low
High
High

Function

Data writing
(Microcomputer .... LCD-II)
Data reading
(Microcomputer + LCD- II)

R/W

Enable signal

E

Data line

DBO

R42

DB3
RSO

DB4
DBS

RS2

DB6
DB7

HITACHI 289

14.1.6

Hardware Operation
Control signals from both the HMCS404C and LCD-II is performed with
the timing shown in Fig. 14.2.

CD

Data is written to LCTC at the falling edge of E.

@

Data from LCD-II can be read during period Tl.

Pin name (LCD-II)
RS, IVW

E

DBO-DB7
(HMCS404C->LCD-H) ______________________- J

CD
DBO-DB7
(HMCS404C--LCD-H) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

Fig. 14.2.

290 HITACHI

HMCS404C ++ LCD-II Interface Timing Chart

14.2

SOFTWARE DESCRIPTION

14.2.1

Program Module Configuration
Fig. 14.3 shows the program module configuration for performing
display on the liquid crystal.

LCDMN
Main
Program

LCDRES

I

Reset
LCD-II

LCDINT

l2:.

LCDDSP

Initialize
LCD-II

Fig. 14.3.
14.2.2

L.£.

l2...

I

Display
on LCD-II

12.

Program Module Configuration

Program Module Functions
Outline of program module functions is shown in Table 14.2.

Table 14.2.

Program Module Functions

No.

Program Module Name

Label

Function

0

Main Program

LCDMN

Main program which conducts
character display on H2570

1

Reset LCD-II

LCDRES

Resets LCD-II according to instructions

2

Initialize LCD-II

LCDINT

Initializes LCD-II display mode

3

Display on LCD

LCDDSP

Sends ASCII code to LCD-II and
displays on H2570

HITACHI 291

14.2.3

Program Module Process Flow (Main Program)
An example of conducting character display on H2570 using the module
shown in Fig. 14.3 is shown in Fig. 14.4.

Execution of the main

program of Fig. 14.4 results in liquid crystal demonstration display
as shown in Fig. 14.5.

Main Program

-----[ Initialize W register
'---,---'

- ------[ Call LCDRES and resets LCD-II
U-_..,...-_.u

------[ Call LCDINT and initializes LCD-II
U-_,-_.u

..-__L.-_--.------[

Load leading address of the data table
in to the accumulator and B register

LCI'NNl

Transfer display data in the data table
by the P instruction to the accumulator
and B register

______ [Test whether transferred data is
If 0, end program

a or not.

A=o,B=O

___ [call LCDDSP and displays characters on
H2570

Increment pointer indicating display
data in data table

Fig. 14.4.

292 HITACHI

Example of Program Module Sample Application

0

=

r-'

=0

r-' r-, r-' r-' r-, r, r-, ,-, r-, r-, r-, r-' r-' r-, r1
:cnMlioi:si:
IIMilcliuliII IIH:IMllc::s::40lloll
01I
I
II II "
II II .. "
II II
II II II II II
L_..J L._J L._J L_.J L_J L._J I-._J L_J L_J L_JL_.J L_.JL_.JL_J L_..JL_.J

0

0

Fig. 14.5.

Example of Liquid Crystal Display

HITACHI 293

14.3

PROGRAM MODULE DESCRIPTION

Program Module Name:

Function:

Reset LCD-II

MCU: HMCS402C/
HMCS404C/HMCS408C

Label: LCDRES

Resets LCD-II by instruction.

Arguments: None

Changes in CPU
Registers and Fla9:s:

Specifications:
1 word = 10 bits

A

B

ROM (Words) :

x

x

RAM (Digits) :

0

X

Y

Stack (Digits) :

0

•

x

No. of cyc1es:33249

SPX

SPY

•

x

W

Reentrant:

26

No

Relocatable:

No

Interrupt OK?:

No

•
CA
x
•
x

:

ST
x

Not Affected
Undefined
Result

Description:
1. Function Details
(1) There are no arguments in LCDRES.
(2) LCD-II is to be reset without fail, even if power source requirements for
normal operation of the built-in reset circuit are not being met.
(3) Program module and subroutines are not being used by program module
LCDRES.
2. User Notes: LCDRES is to be executed immediately following turning on of
LCD-II power source.

Specifications Notes:

294 HITACHI

_p_r_o_g_r_am
__M_o_d_u_l_e_N_am_e_:_R_e_s_e_t_LC_D_-_I_I_--, ...._M_C_U_:_HM_C_S_4_0_2_C_/
HMCS404C/HMCS408C
_ _ _ _-' lL_ab_e_l_:
.
__L_C_D_RE_S_ _---l
L

Description:
3. RAM Allocation
RAM is not used by program module LCDRES.
4. Sample Application
LCD-II power source ON

II

CALL

LCDRES

/I

Call LCDRES

5. Basic Operation
(1) LCD-II may, by the process shown in Fig. 14.6, be reset by instruction.

LCD- II Reset

Fig. 14.6.

Resetting of LCD-II by Software

(2) Controls RS, R/W and E signals at the I/O port by software and output
$30.
(3) By loop processing of software timer which generates a delay time (15 ms),
and by program which transfers $30, resetting of LCD-II is achieved as
shown in Fig. 14.6.

HITACHI 295

Program Module Name: Reset LCD-II

~:

HMCS402C/
HMCS404C/HMCS408C

~

Flowchart:

r

L-____

Load, 2 onto the counter to loop
~----~----L process 3 times

Execute 15 ms software timer

296 HITACHI

LCDRES

Program Module Name: Reset LCD-II

!:!9l,: HMCS402C/
HMCS404C/HMCS408C

I~

LCDRES

Flowchart:

---[ Set RS signal low
L--_-,-_--'

---[ Set R/W signal low
L--_-,-_--'

---[ Set E signal low
L...----r--.......J

L -_ _..,-_ _..J - - - [

Set E signal high

Output instructions of the function set

'--__..,-__..1---[

Set E signal low

'--_ _..,-_ _~---[ Decrement counter
---[ Test if LCD-II reset complete

HITACHI 297

Program Module Name:
Initialize LCD-II

Function:

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

LCDINT

Initializes LCD-II display mode.

Arguments: None

Changes in CPU
Registers and Flags:

Specifications:
1 word

= 10 bits

A

B

ROM (Words) :

x

x

RAM (Digits) :

0

X

y

Stack (Digits) :

0

•

x

No. of cycles: 180

SPX

SPY

•

•

W

Reentrant:

18

No

Relocatable:

No

Interrupt OK?:

No

•
CA
x

ST
x

•
Not Affected
x : Undefined
Result
Description:
1. Function Details
(1) There are no arguments in LCDINT.
(2) Data in Table 14.3 is to be transferred to LCD-II and initialized in
display mode.

Specifications Notes:

298 HITACHI

Initialize
LCD-II
_p_r_o_g_r_am
__M_o_d
__
u_l_e_N_a_m_e__
: ______________
'-

~

HMCS404C/HMCS408C
.
...M_C_U__:_HM
__C_S_4_0_2_C_/______---JlL-a-b-e-l_:
__LC
__D_I_N_T______

~

Description:
Table 14.3.

LCD-II Display Mode Data

Data

Function

$08

Display OFF

$01

All display cleared, DDRAM address set to $00

$07

Cursor movement direction to the right and display shifted

$90

DDRAM address set to $10

$18

Select display shift direction to the left

$OC

Display ON

(3) In program module LCDINT, the subroutine in Table 14.4 is used.
Table 14.4.

Subroutine Used in Program Module LCDINT

Subroutine Name

Label

Functions

Busy check

LCDBSY

Check the LCD-II busy flag

2. User Notes
Resets LCD-II prior to execution of LCDINT.
3. RAM Allocation
RAM is not used program module LCDINT.
4. Sample Applications

II

CALL

LCD RES

CALL

LCDINT

ORG
DC

$ 100
$10C

DC

$ 11

II·. · . ·

Execute LCDRES and reset
LCD-II
Call LCDINT

} ........ Se=e dato table

8

HITACHI 299

Program Module Name:
Initialize LCD-II

~

M_C_U_:__HMCS404C/HMCS408C
HM
__C_S_4_02_C_/________
...

.
II-L_a_b_e_l_:
__
LC_D_I_NT
____

Description:
5. Basic Operation
(1) Performs busy flag check every time before outputting data.
(2) Set data shown in Table 14.3 into port R4 and R5, control LCD-II signals
E, R/W and RS through ports DO, 01 and 02, and initialize LCD-II with
this data.
(3) Repeat (1) to (2) 6 consecutive times and initialize.

300 HITACHI

~~

t!9!:

Program Module Name:
Initialize LCD-II

HMCS402C/
HMCS404C/HMCS408C

Label: LCDINT

Flowchart:

r-_~~:;:;:;::::;;:r--...J ----- [ Initialize counter
u-____~----u

. -_ _....l.._ _---,

_____ [ Execute LCDBSY and check LCD-II
busy flag

-----lI

Load data table address on to
accumulator and B register

'------r----' - - - - - [ Set RS signal low

L.....____

~----.J

----- [

Set R/W signal low

'------r----' ----- [ Set E signal low

'------r----'-----[
----- [
~---r---....I

Set. E signal high
Transfer instruction at the data table
mode to accumulator and B
reglster
dis~lay

Output display mode instruction

'------r---....I-----[ Set E signal

low

~o

-- ----[ Decrement counter

HITACHI 301

Program Module Name:
Display on LCD

Function:

LCDDSP

Writes ASCII code in DDRAM of LCD-II and displays graphically on
liquid crystal.

Arguments:
1 digit
Contents

=4

Specifications:

Changes in CPU
bits

Registers and Flags:

Storage No. of
LocaDigits
tion

Entry Display Upper B
data
(ASCII Lower A
code)

1
1

--

-- --

= 10 bits

1 word

A

B

ROM (Words) :

x

•

RAM (Digits) :

X

Y

Stack (Digits) :
No. of cycles:

29

Reentrant:

No

Relocatable:

No

Interrupt OK?:

No

•

•

SPX

Spy

•

•

W
Returns

Label:

MCU: HMCS402C/
HMCS404C/HMCS408C

13
0
0

•

•
x

CA

ST

•

•

Not Affected
: Undefined
Result

Description:
1. Function Details

B

{~

A: Stores the lower 4 b.its of the
ASCII code of the graphic display.
B: Stores the upper 4 bits of the
ASCII code of the graphic display.

('C' $43)

302 HITACHI

I
t

0:: III I I I I I I I
Liquid crystal

CD

Results

{

Fig. 14.7.

Specifications Notes:

Q 0

Entry
arguments ASCII code

(1) Argument details

A

C

Example of LCDDSP
Execution

Program Module Name:
Display on LCD

MCU: HMCS402C/
HMCS404C/HMCS408C

Label:

LCDDSP

Description:
(2) Fig. 14.7 shows an example of program module LCDDSP. If the entry
arguments are set in accumulator and B register as in Fig. l4.7-CD ,
ASCII code is written to the current DDRAM address and graphically
displayed on the liquid crystal.
(3) In program module LCDDSP, the subroutine shown in Table 14.5 is used.
Table 14.5.

Subroutine Used in Program Module LCDDSP

Subroutine Name

Label

Function

Busy check

LCDBSY

Checks busy flag of LCD-II

2. User Notes

(1) Resets LCD-II.
(2) Initializes LCD-II display mode.
(3) Stores entry arguments.
3. RAM Allocation
RAM is not used by program module LCDDSP.
4. Sample Application

II

CALL
CALL

LCD RES
LCDINT

LAI
LBI

4

CALL

LCDDSP

...... Execute LCDRES and reset LCD-II
...... Execute LCDINT and initialize LCD-II
display mode

}
II

...... Load entry arguments
...... Call LCDDSP

5. Basic Operation
(1) Checks LCD-II busy flag.
(2) Controls signals RS, R/W and E by software through port D and outputs
display data.

HITACHI 303

Program Module Name:
Display on LCD

MCU: HMCS402C/
HMCS404C/HMCS408C

~

LCDDSP

Flowchart:

-----l~
~____~____~

Save display data due to use of Accumulator
in subroutine LCDBSY

u....-----r-----.u-----[ Execute LCDBSY and check busy flag

~

'--____...,...-____ -----[ Restore display data

'-------r-----...J -----[ To write display data, set RS signal high

'-------r-----~ - - - - - [ Set R/W signal

low

'-------r-----...J -----[ Set E signal low
'-------r-----...J -----[ Set E signal high

.------..1...------, -----[ Output di'play data to lCD-H

L-------r-----...J -----[ Set E signal low

304 HITACHI

14 4

SUBROUTINE DESCRIPTION

Subroutine Name:

Function:

MCU: HMCS402C/
HMCS404C/HMCS408C

Busy Check

1Labol'

LCDBSY

Checks if LCD-II is busy and waits for ready state.

Basic Operation:

(1) Since, while LCD-II is in operation, it will not allow
access from microcomputers, checks must be made on the
LCD-II busy flag.
(2) Control of signals RS, R/W and E through port D is
performed by software together with busy flag check.

Program Module Using This Subroutine:

LCDDSP, LCDINT, LCDRES

Flowchart:

'--__-,-__..J-----[
'--__-,-__. J

Set RS signal low

_____ [ Set R/W signal at high to enable reading
of busy flag

r-----;;-;:::~~:;:~-----'-----[ Set E signal Low.

'--__.-__. J -----[

Initialize port R5 to entry port

'--__.-__...1-----[

Set E signal high

...-_ _J....._ _. . , - - - - - [

Read busy flag and test busy flag when
set at highest bit

'--__-,-__..J-----[

Set signal low

CA= 1

- -- --[ Test if busy flag check complete

HITACHI 305

14.5

PROGRAM LISTING

ST-No

OBJECT

ADRS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057

100

0000

SOURCE STATEMENTS
LLEN
TITLE

*
****
*LSoUR

132
LIQUID CRYSTAL MODULE (H2570) CONTROL

RAM ALLOCATION

****************************************

EQU
$020
WORK AREA FOR ACCA
HSoUR
EQU
$021
WORK AREA FOR B REGISTER
****************************************************************

*

*
VECTOR ADDRESSES
*
*
******************************************************************
150
150
150
150
150

040
040
040
040
040

150 040

0000
0002
0004
0006
0008

OOOC

*
*

*
*

ORG

$0000

JMPL
JMPL
JMPL
JMPL
JMPL

LCDMN
LCDMN
LCDMN
LCDMN
LCDMN

ORG

$OOOC

RESET
INTO
INTl
TIMER A
TIMER 8

JMPL
LCDMN
SERIAL
****************************************************************

*

OFO
160
160
230
200
194
048
194
190
IB2
ODB
2BO
048
354
356
2BO
363
OAF
160
190
OCB
190
2Bl
361
347

064
07E
020
021
020

090
021
020

306 HITACHI

0040
0041
0043
0045
0046
0047
0049
004A
004C
004E
004F
0050
0051
0052
0053
0054
0055
0056
0057
0059
005B
005C
005E
005F
0060

*

MAIN PROGRAM : LCDMN
*
*
*
*****************************************************************
*
ORG
$0040
*LCDMN
$0
INITIALIZE W REGISTER
LWI

LCDMNI

LCDMN2
LCDMN3

CALL
CALL
LAI
LBI
LMAD
LAB
LMAD
LAMD
P
LYA
ALEI
LAB
BR
BR
ALEI
BR
LAY
CALL
LAMD
LBA
LAMD
AI
BR
BR

LCDRES
LCDINT
SO
$0
LSoUR

RESET LCD-II
INITIALIZE LCD-II
LOAD DATA TABLE STARTING ADDR INTO ACCA
LOAD DATA TABLE STARTING ADDR INTO B REG
ACCA ---) LSoUR

HSoUR
LSoUR
$2

B REGISTER ---) HSoUR
LSoUR ---) ACCA
MOVE DISPLAY TO ACCA & B REGISTER

$0

TEST IF ACCA=O

LCDMN2
LCDMN3
$0
PEND

IF O. BRANCH TO LCDMN2
IF NOT O. BRANCH TO LCDMN3
TEST IF 8 REGISTER=O
IF O. BRANCH TO PEND

LCDDSP
HSoUR

DISPLAY FIGURE ON LCD-II
HSoUR ---) B REGISTER

LSoUR

LSoUR ---) ACCA
ACCA + $1 ---) ACCA
BRANCH IF ACCA =$F

$1

LCDMN4
LCDMNI

00058
D0059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00DB1
00082
00083
00064
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114

04C
347
363

0061
0062
0063

lCDMN4

INCREMENT B REGISTER
18
lCDMN1
lOOP UNTIL 8 REGISTER = SF
BR
PEND
PEND
BR
****************************************************************

*
*

NAME : lCDRES (RESET lCD-II)

.

*
*
****************************************************************
*..
*
ENTRY : NOTHING
*
RETURNS : NOTHING
*

202
239
21F
002
21F
000
000
ODF
369
002
ODF
367
28F
366
260
261
262
2E2
230
2D4
233
2D5
262
OCF
365
010

0064
0065
0066
0067
0068
0069
006A
006B
006C
006D
D06E
006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
0078
007C
007D

..****************************************************************.
lCDRES
lCDRS1
lCDRS2
LCDRS3

LBI
S2
INITIALIZE LOOP COUNTER
$9
lAI
EXECUTE 15MS SOFTWARE TIMER
$F
lYI
XSPY
$F
LYI
LCDRS4
NOP
NOP
DY
lCDRS4
BR
XSPY
DY
BR
lCDRS3
$F
AI
lCDRS2
BR
$0
REDD
RS=O
$1
R/W=O
REDO
$2
REDO
E=O
$2
E=l
SEDD
$0
LAI
$4
WRITE INSTRUCTION DATA
LRA
$3
LAI
LRA
$5
WRITE INSTRUCTION DATA
$2
REDD
SET E=O
DECREMENT lOOP COUNTER
DB
LOOP UNTIL LOOP COUNTER=O
8R
LCDRS1
RTN
****************************************************************

.
..
NAME : LCDINT (INITIALIZE LCD-II)
.*
****************************************************************
..
...
ENTRY : NOTHING
.
.. RETURNS
: NOTHING
*
****************************************************************

*

215
160 09D
OAF
200
260
261
262
2E2

007E
007F
0081
0082
00B3
0064
0085
0086

lCDINT
lCDIT1

LYI
CALL
lAY
LBI
REDO
REDD
REDD
SEDD

$5
lCDBSY

$0
$0
$1

$2
$2

INITIALIZE LOOP COUNTER
CHECK LCD-II BUSY FLAG
lOAD DATA TABLE ADDRESS INTO ACCA
lOAD DATA TABLE ADDRESS INTO B REG
RS=O
R/W=O
E=O
E=l

HITACHI 307

00115
00116
00117
OOllB
00119
00120
00121
00122
00123
00124
00125
00126
00127
0012B
00129
00130
00131
00132
00133
00134
00135
00136
00137
0013B
00139
00140
00141
00142
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156
00157
0015B
00159
00160
00161
00162
00163
00164
00165
00166
00167
0016B
00169
00170
00171

IB1
204
04B
205
OAF
262
ODF
37F
010

00B7
OOBB
00B9
OOBA'
OOBB
OOBC
OOBD
OOBE
OOBF

ODB
160 090
OAF
2EO
261
262
2E2
204
04B
205
262
010

0090
0091
0093
0094
0095
0096
0097
009B
0099
009A
009B
009C

P

LRA
LAB
LRA
LAY
REDO
DY
BR
RTN

Sl
S4

MOVE INSTRUCTION TO ACCA & B REG
OUTPUT INSTRUCTION

55
52
LCDITl

E-O
DECREMENT LOOP COUNTER
LOOP UNTIL LOOP COUNTER=O

,.****************************************************************,.
NAME : LCDDSP (DISPLAY ON LCD-II)
,.*
,.*
****************************************************************
,.
,.
,.
,.
ENTRY: B REGISTER,ACCUMULATOR (DISPLAY DATA)
,. RETURNS
,.
:-NOTHING
,.
,.
****************************************************************
LCDDSP
LYA
SAVE ACCA
CALL
LCDBSY
CHECK BUSY FLAG
LAY
RESTORE ACCA
SEDD
SO
RS=l
REDO
51
RIW-O
REDO
S2
E=O
SEDD
52
E=l
LRA
54
OUTPUT DISPLAY DATA
LAB
55
LRA
REDO
S2
E=O
RTN

,.****************************************************************,.
,.
,.
NAME : LCDBSY (CHECK BUSY FLAG)
,.
,.
260
2El
262
23F
205
2E2
255
OA1
06F
262
3AO
010

0090
009E
009F
OOAO
00A1
00A2
00A3

OOM

00A5
00A6
00A7
OOAB

****************************************************************

LCDBSY

REDO
50
RS=O
SEDD
51
R/W=l
REDO
52
E=O
LCDBY!
LAI
SF
SELECT R PORT AS INPUT
LRA
55
SEDD
52
E=l
LAR $5
READ BUSY FLAG
ROTL
TC
TEST CARRY
REDO
52
E-O
BR
LCDBY!
LOOP UNTIL BUSY FLAG-O
RTN
,.****************************************************************,.

,.

,.

DATA TABLE

,.

,.

****************************************************************
10C

308 HITACHI

0100

*

,.

ORG

50100

SOD

DC

$10C

00172
00173
0017"
00175
00176
00177
00178
00179
00180
00181
00182
00183
0018"
00185
00166
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196
00197
00198

118
191
107
101
108

143
14D
14F
153
120
140
143
155
120
148
140
143
153
134
130
130
100

0101
0102
0103
0104
0105

0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
020A
0206
020C
020D
020E
020F
0210

$01
$02
$03
$04
$05

*
*$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$OA
$08
SOC
$00
$OE
$DF
$10

*

DC
DC
DC
DC
DC

$118
$191
$107
$101
$108

DRG

$0200

DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC

$143
$14D
$14F
$153
$120
$140
$143
$155
$120
$148
$140
$143
$153
$134
$130
$130
$100

DC

DC
DC
DC
DC
DC
END

HITACHI 309

SECTION 15.

LOW POWER DISSIPATION MODE AND WATCHING TIMER EXECUTION
USING THE HA1S35A

15.1

HARDWARE DESCRIPTION

15.1.1

Function
Enters low power dissipation mode of the HMCS404C MCU and executes
fail safe mode with the HA1S35P watchdog timer.

15.1.2

Microcomputer Operation
Enters stop mode and standby mode and LUL-ns o:n LED i:ndicating

current mode, and counts down binary counter every second to display
mode elapsed time on a set of LED,s; stop mode is released by reset
input and standby mode by timer interrupt.

Controls and outputs

pulses to the HA1S35P through port DS.
15.1.3

Peripheral Devices
SW3: Sets stop mode in low power dissipation mode.
SW2: Sets standby mode in low power dissipation mode.
SW4: Stops output of pulses to the HA1S35P in fail safe mode and
executes system run away.

310 HITACHI

15.1.4

Circuit Diagram

+5V

MCU
HMCS40

Exclusive OR

".

Not Equal

Status is set when NZ, NB, or OVF occurs

Less than or Equal
DIRECT

Addressing by the instruction operand in the ROM code

REGISTER

Addressing by the contents of Address Register

I/E

Interrupt enable flag

PC

Program counter

SP

Stack pointer

ST

Status flag

CA

Carry flag

A

Accumulator

B

B register

W

W register

X

X register

SPX

SPX register

Y

Y register

Spy

SPY register

M

Memory (RAM)

MR

Memory register

R

Data I/O pin or data register

D

Discrete I/O pin or discrete latch

•

HITACHI 333

Symbolic Operands Used with Instruction Set Mnemonics
Symbol

Contents

Label

D

HD

B

n

RAM digit selection by 2 bits

0

0

0

0

m

RAM (MR) digit and port selection
by 4 bits

0

0

0

0

p

Replacement of contents of PC
by 4 bits

0

0

0

0

a

Replacement of contents of PC
by 6 bits

0

x

0

0

b

Replacement of contents of PC
by 8 bits

0

x

0

0

d

Replacement of PC or RAM direct
address by 10 bits

0

x

0

0

i

Immediate data by 4 bits (Note)

0

0

0

0

u

u = p + d (14 bits)

0

x

0

0

D: Decimal

o . . ..
(Note)

Can be used

HD: Hexadecimal

B: Binary

x .... Cannot be used

In case of LWI instruction, 2 bits.

•

334 HITACHI

Immediate Instruction
OPERATION

MNEMONIC

OPERATION CODE

FUNCTION

STATUS

wz

VClE

Load A from Immediate

LAI i

10001 1 i, i,;, io

i~A

1 00 000 i, i, i, io

i--B

1/1

~ d.J ~ J ~ d' d' d',:f.

i---+M

2/2

Load B from Immediate

LBI i

Load Memory from Immediate

LMID i,d

Load Memory from Immediate, Increment Y

LMIIY i

101001;' i, i, io

i~M,Y+1~Y

1/1

NZ

Register-to-Register Instruction
OPERATION

OPERATION CODE

MNEMONIC

Load A from B

FUNCTION

STATUS

1/1

wz

VClE

LAB

0 0 0 1 0 0 1 0 0 0

B~A

1/1

Load B from A

LBA

0 0 1 1 0 0 1 0 0 0

A~B

1/1

Load A from Y

LAY

0 0 1 0 1 0 1 1 1 1

Y~A

1/1

Load A from SPX

LASPX

0 0 0 1 1 0 1 0 0 0

SPX~A

1/1

Load A from SPY

LASPY

0 0 0 1 0 1 1 0 0 0

SPY~A

1/1

Load A from MR

LAMR m

1 0 0 1 1 1 m3m2mlmO

MR(m)~A

1/1

Exchange MR and A

XMRA m

1 0 1 1 1 1 m3m2m,mO

MR(m)-A

1/1

RAM Address Instruction
STATUS

wz

MNEMONIC

OPERATION CODE

FUNCTION

Load W from Immediate

LWI i

001 1 1 1 00 i, i,

i--W

Load X from Immediate

LXI

i

1 00 0 1 0 i, i, ;, io

i~X

1/1

Load Y from Immediate

LYI

i

100001;,;,;,io

i~Y

1/1

Load X from A

LXA

0011101000

A~X

1/1

Load Y from A

LYA

0011011000

A~Y

Increment Y

IY

0001011100

Y+1~Y

NZ

1/1

Decrement Y

DY

0011011 1 1 1

Y-1~Y

NB

1/1

AddAtoY

AYY

0001010100

Y+A~Y

Subtract A from Y

SYY

0011010100

Y-A~Y

Exchange X and SPX

XSPX

0000000001

X-SPX

Exchange Y and SPY

XSPY

0000000010

V-Spy

1/1

Exchange X and SPX,Y and SPY

XSPXY

0000000011

X-SPX,Y-SPY

1/1

OPERATION

VClE

1/1

1/1

,OVF
NB

1/1
1/1
1/1

HITACHI 335

RAM Register Instruction
OPERATION

MNEMONIC

Load A from Memory

LAM(XY)

Load A from Memory

LAMD

Load B from Memory

LBM(XY)

Load Memory from A

LMA(XY)

Load Memory from A

LMAD

d

STATUS

WOR~

ZLE

OPERATION CODE

FUNCTION

00100100yx
0110010000
d, d, d, d, d, d. d, d, d, do
00010000yx

M---+A. (~::~~~)

A---+M. (~:~m

1/1

A---+M

2/2

1/1

M---+A

2/2

M---+B. (~:~m

1/1

load Memory from A. Increment Y

LMAIY(X)

00100101yx
0110010100
d,d,d,d,d,d.d,d,d, do
000101000x

A---+M.Y + I---+YIX"sp'I

NZ

1/1

load Memory from A. Decrement Y

LMADY(X)

001101000x

A---+M.Y -1---+YIX"SP'I

NB

1/1

Exchange Memory and A

XMA(XY)

00100000yx

M~A. (~:~~~)

1/1

Exchange Memory and A

XMAD

11:1110000000
d, d, d, d, d, d. d. d, d, do

M-A

2/2

Exchange Memory and B

XMB(XY)

00110000yx

M-B. (~:~p~)

1/1

d

d

Notel (XYI and (xl have the meaning as follows:
(11 The instructions with (XYI have 4 mnemonics and 4 object codes for each. (example of LAM (XYI is given below. I
MNEMONIC

y

LAM
LAMX

0
0
1
1

LAMY
LAMXY
(21

:

:
:

x
0
1
0
1

FUNCTION
X"SPX
Y"SPY
X"SPX Y"SPY

The instructions with (xl have 2 mnemonics and 2 object codes for each. (example of LMAIY (XI is given below.!

MNEMONIC

FUNCTION

LMAIY
LMAIYX

336 HITACHI

X"SPX

Arithmetic Instruction
OPERATION

MNEMONIC

OPERATION CODE

FUNCTION

STATUS

i

1 0 1 0 0 0 i3 i, ;, io

A+i-A

OVF

Z

YCLE

1/1

Add Immediate to A

AI

Increment B

IB

0001001100

B+1-B

NZ

1/1

Decrement B

DB

0011001111

B-1-B

NB

1/1

Decimal Adjust for Addition

DAA

0010100110

Decimal Adjust for Subtraction

DAS

0010101010

Negate A

NEGA

0001100000

A+1-A

Complement B

COMB

0101000000

II-B

Rotate Right A with Carry

ROTR

0010100000

Rotate Left A with Carry

ROTL

0010100001

Sat Carry

SEC

0011101111

1-CA

Resat Carry

REC

0011101100

O-CA

Test Carry

TC

0001101111

Add A to Memory

AM

0000001000

M+A-A

OVF

1/1

Add A to Memory

AMD d

~.J.~,&~.&J ~ ~,lL

M+A-A

OVF

2/2

Add A to Memory with Carry

AMC

0000011000

OVF

1/1

Add A to Memory with Carry

AMCD d

U~'~'~5lJ,~,~, ~D

1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
CA

M+A+CA-A

OVF .... CA

M+A+CA-A

1/1

OVF .... CA

OVF

2/2

M-A-CA-A

NS .... CA

NB

1/1

M-A-CA-A

NB

2/2

SMC

0010011000

Subtract A from Memory with Carry

SMCD d

g.l3,g,g.3J,g,g, &

ORAandB

OR

0101000100

AUB-A

AND Memory with A

ANM

0010011100

AnM-A

NZ

1/1

AND Memory with A

ANMD d

~.H~~J.J J,~,g

AnM-A

NZ

2/2

OR Memory with A

ORM

0000001100

AUM-A

NZ

1/1

OR Memory with A

ORMD d

&do~,~.~, &J, J, ~,lL

AUM-A

NZ

2/2

EOR Memory with A

EORM

0000011100

A$M_A

NZ

1/1

EOR Memory with A

EORMD d

~J.~,~.~,lU~'~n

A
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