1988_IDT_High_Performance_CMOS_Data_Book 1988 IDT High Performance CMOS Data Book

User Manual: 1988_IDT_High_Performance_CMOS_Data_Book

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Integrated
Device
Technology

High Performance CMOS

.-

DATA BOOK
1988

Product Selector and Cross Reference Guides
Technology/Capabilities
Quality and Reliability
Static RAMs
Dual-Port RAMs
FIFO Memories
Digital Signal Processing (DSP)
Bit-Slice Microprocessor Devices (MICROSLICE™) and EDC
Reduced Instruction Set Computer (RISC) Processors
Logic Devices
Data Conversion
E2 PROMS-Electrically Erasable Programmable Read Only
Memories
Subsystems Modules
Application and Technical Notes
Package Diagram Outlines

.._ - . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ .

Integrated Device Technology, Inc.

HIGH-SPEED CMOS
DATA BOOK

,/

3236 Scott Boulevard, Santa Clara, California 95054
Telephone: (408) 727-6116· TWX: 910-338-2070. FAX: (408) 988-3029
Printed in U.S.A. 1/88
© 1988 Integrated Device Technology, Inc.

CONTENTS OVERVIEW

The block diagram on the cover of this book pictorially illustrates the multiple product lines
offered by Integrated Device Technology, a recognized leader in high-speed CMOS technology. lOT's broad line of products enables us to provide a complete CMOS solution to designers of high-performance digital systems. Our products include industry standard devices as
well as products with speed, lower-power, package and/or architectural benefits that allow the
designer to achieve Significantly improved system performance.
Use this book to find ordering Information: Start with the Ordering Information chart at
the back of each datasheet, or Cross Reference Guides (p 1-13) along with Package Diagram
Outlines (p 15-3), to compose the complete lOT part number. Reference data on our Technology Capabilities and Quality Commitments are included in separate sections (2, 3)
respectively} .
Use this book to find product data: Start with the Table of Contents, organized either alphanumerically by product line (p ii) or numerically across all products (p xiv); for a more complete summary of product line offerings, use the Product Selector Guide (p 1-2). These indexes will direct you to the page on which the complete technical data sheet can be found,
and may in some cases refer you to related Application or Technical Notes (p 14-1). Data
sheets may be of the following type:
ADVANCE INFORMATION-contain initial descriptions, subject to change,forproductsthat
are in development, including features and block diagrams.
PREll MI NARY -contain descriptions for products soon to be or recently released to production, including features, pinouts and block diagrams. Timing data are based on simulation or
initial characterization and are subject to change upon full characterization.
FINAL-contain minimum and maximum limits specified over the complete supply and temperature range for full production devices.
New Products, product performance enhancements, additional package types and new
product families are being introduced frequently. Please contact your local lOT sales representative or 1-BOO-IDT CMOS to determine latest device specifications, package types and
product availability.

Note: Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in
order to improve design or performance and to supply the best possible product. lOT does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in an lOT product. The Company makes no representations that circuitry described
herin is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components In life support device or systems unless
a specific written agreement pertaining to such Intended use Is executed between the manufacturer and an Officer of lOT.
1. Ufe support devices or systems are devices or systems which (a) are Intended for surgical Implant Into the body or (b) support or
sustain life and whose failure to perform, when properly used In accordance with Instructions for use provided In the labeling, can be
reasonably expected to result In a significant Injury to the user.
2. A critical component Is any component of a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to affect Its safety or effectiveness.

CEMOS, BiCEMOS, MICROSLlCE, Flexishift and SPC are trademarks of Integrated Device Technology, Inc.
SPC (Serial Protocol Channel) has a patent pending.
FAST is a trademark of Fairchild Semiconductor Co.

/

TABLE OF CONTENTS
PAGE

CONTENTS

Contents Overview .................................................................•....................... i
Disclaimer
Life Support Policy
Table of Contents
Alphanumeric Listing by Product Line ................................................................•..... ii
Numerical Index •...................•.................................................................. xiv
Product Selector and Cross Reference Guides
Part Number Description .................................................................................... 1-1
Product Selector Guide ..................................................................................... 1-2
Cross Reference Guides
Static RAM ......................................................................................•.....
EEPROM .............................................................................................
MICROSLICE and EDC .................................................................•...............
Digital Signal Processing .... " .................................. , .......................................
Data Conversion ..........•.............................•..............................•.......•.•.....
Subsystems . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . .

1-13
1-23
1-24
1-25
1-28
1-29

Technology/Capabilities
IDT... leading the CMOS Future ............................................................................... 2-1
IDT Military and DESC-SMD Program ......................•................................•................. 2-2
Radiation Hardened Technology .......................................................................... 2-3
IDT leading Edge CEMOS Technology .................................... ~ ................................... 2-4
Surface Mount Technology ................•................•...........................•................. 2-6
State-of-the-Art Facilities and Capabilities ................................................................... 2-7
Superior Quality and Reliability ..................................................................•........ 2-8
Quality and Reliability
IDT Commitment to Quality ..........................................................................•....... 3-1
Summary of Monolithic Hermetic Product Processing Flow .............................•...................... 3-2
Summary of Plastic Product Processing Flow ............................................................... 3-5
Radiation ToleranVEnhanced Products for Radiation Environments ........••..........•..........•.............. 3-9
Static RAMs
IDT6167
IDT6168
ID171681
ID171682
IDT6116
ID17187
IDT100490
ID17188
IDT6198
ID17198
ID171981
ID171982
ID17164
ID17186
IDT8M628
IDT8MP628
ID17MP564
ID171257
ID17MP156
ID17MC156
ID171258
IDT61298
ID171281
ID171282

16K (16K x 1) CMOS SRAM (Power Down) (14-74,14-200,14-253) ............................ 4-1
16K (4K x 4) CMOS SRAM (Power Down) (14-253) .......................................... 4-11
16K (4K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write (14-36, 14-74, 14-253)) '" 4-22
16K (4K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) (14-36, 14-74, 14-253) ........• 4-22
16K (2K x 8) CMOS SRAM (14-74, 14-253) ..........•.....•............................... 4-33
64K (64K x 1) CMOS SRAM (Power Down) (14-74, 14-253) ....................•.............. 4-44
64K (64K x 1) SiCMOS SRAM with ECl I/O ................................................ 4-52
64K (16K x 4) CMOS SRAM (Power Down) (14-74, 14-253) ..........•........................ 4-57
64K (16K x 4) CMOSSRAM (with Output Enable) (14-74, 14-253) .............................. 4-65
64K (16K x 4) CMOS SRAM (2 CE and OE) (14-74, 14-253) .................................. 4-74
64K (16K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) (14-36,14-74, 14-253) ... 4-84
64K (16K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) (14-36,14-74,14-253) ........ 4-84
64K (8K x 8) CMOS SRAM (Power Down) (14-74, 14-207, 14-253) ...........•................. 4-94
64K (4K x 16) CMOS SRAM (Po"wer Down) (14-74,14-253) ..•................................ 4-103
128K (8K x 16) CMOS SRAM ............................................................ 13-99
128K (8K x 16) CMOS SRAM (Plastic SIP) .................................................. 13-80
80K (16K x 5) CMOS SRAM (Plastic SIP) ................................................... 13-29
256K (256Kx 1) CMOS SRAM (Power Down) (14-74,14-253) ................................. 4-113
256K (256K x 1) CMOS SRAM (Plastic SIP) ................................. , ............... 13-17
256K x 1 CMOS SRAM (Ceramic SIP) .................................................•... 13-3
256K (64K x 4) CMOS SRAM (14-74, 14-253) .............................................. 4-124
256K (64K x 4) CMOS SRAM (with Output Enable) (14-74, 14-253) .................. " ......... 4-133
256K (64K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) (14-36,14-74,14-253) ... 4-143
256K (64K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) (14-36,14-74,14-253) ......... 4-143

II

TABLE OF CONTENTS (CONT'D)
CONTENTS
PAGE
Static RAMs (Cont'd.)
ID17MP456
256K (64K x 4) CMOS SRAM (Plastic SIP) .................................................. 13-23
ID171256
(32K x 8) CMOS SRAM (Power Down) (14-74, 14-253) ....................................... 4-153
IDT8M856
256K (32K x 8) Low-Power CMOS SRAM ................................... " .............. 13-113
ID17M656
256K (16K x 16) CMOS SRAM ........................................................... 13-48
IDT8MP656
256K (16K x 16) CMOS SRAM (Plastic SIP) ................................................. 13-80
IDT8M656
256K (16K x 16) CMOS SRAM ........................................................... 13-99
ID17M812
512K (64K x 8) CMOS SRAM ............................................................ 13-57
ID17M912
512K (64K x 9) CMOS SRAM ............................................................ 13... 57 ~/
IDT8M612
512K (32K x 16) CMOS SRAM ........................................................... 13"::g2
.
IDT8MP612
512K (32K x 16) CMOS SRAM (Plastic SIP) ............................. , ................... 13-74
ID17MC4032
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) ......................................... , . 13-15
ID171027
1 Megabit (1024 x 1) CMOS SRAM (Power Down) (14-74, 14-253) ............................. 4-168
ID17MC4001
1 Megabit (1024K x 1) CMOS SRAM w/Separate I/O (Ceramic SIP) ............................. 13-9
ID171 028
1 Megabit (256K x 4) CMOS SRAM (Power Down) (14-74, 14-253) ............................. 4-171
ID171 024
1 Megabit (128K x 8) CMOS SRAM (Power Down) (14-74, 14-253) ............................. 4-173
IDT8M824
1 Megabit (128K x 8) CMOS SRAM ....................................................... 13-107
IDT8MP824
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) ..................................... , ....... 13-86
ID17M624
1 Megabit (64K x 16) CMOS SRAM ....................................................... 13-41
ID17MB624
1 Megabit (64K x 16) CMOS SRAM (Plastic DIP) ............................................ 13-1
IDT8M624
1 Megabit (64K x 16) CMOS SRAM ....................................................... 13-92
IDT8MP624
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) .............................................. 13-74
ID17M4017
2 Megabit (64K x 32) CMOS SRAM ....................................................... '13-72
ID17MP4008
4 Megabit (512K x 8) CMOS SRAM (Plastic SIP) ............................................. 13-35
ID17M4016
4 Megabit (256K x 16) CMOS SRAM ...................................................... 13-70
Application Specific Memories
IDT6178
16K (4K x 4) CMOS Cache-Tag SRAM (14-47, 14-264, 14-268) ................................ 4-184
ID17174
64K (8K x 8) CMOS Cache-Tag SRAM (14-47, 14-264, 14-268) ................................ 4-186
ID17165
64K (8K x 8) Resettable CMOS SRAM (14-74, 14-207, 14-253) ................................ 4-196
ID171C65
64K (8K x 8) SRAM (Resettable CMOS I/O) (14-74,14-207, 14-253) ............................ 4-206
ID171501
64K (64K x 1) CMOS Synchronous RAM ................................................... 4-215
ID17MP6025
512K (64K x 8) Synchronous SRAM (Plastic SIP) ............................................ 13-123
ID17M6001
Dual, Multiplexed 16K x 20 SRAM ........................................................ 13-197
ID17M824
1 Megabit (128K x 8) Registered and Buffered SRAM Subsystem Family ......................... 13-168
ID171502
64K (4K x 16) CMOS Registered RAM (for Writable Control Stores) (14-154,14-197) ............... 4-224
ID17M6032
16K x 32 High-Speed Writable Control Store w/SPC (14-154) ............ ; ............. , ....... 13-199
ID17MB6042
8K x 112 High-Speed Writable Control Store w/SPC (14-154) .................................. 13-121
Dual-Port RAMs
ID17130
ID17140
ID17132
ID17142
ID171321
ID171421
ID171322
ID17133
ID17143
ID17134
ID171342
ID17M134
ID17M135
ID17M137
ID17M144
ID17M145

8K (1 Kx8) Dual-Port RAM (MASTER) (14-9,14-68, 14-74, 14-253, 14-260) ......................
8K (1Kx8) Dual-Port RAM (SLAVE) (14-9, 14-68, 14-74, 14-253, 14-260) ........................
16K (2K x 8) Dual-Port RAM (MASTER) (14-9, 14-68, 14-74, 14-253, 14-260) ....................
16K (2K x 8) Dual-Port RAM (SLAVE) (14-9, 14-74, 14-253) ...................................
16K (2K x 8) Dual-Port RAM (MASTER w/lnterrupts) (14-9, 14-74, 14-253, 14-260) ................
16K (2K x 8) Dual-Port RAM (SLAVE w/lnterrupts) (14-9, 14-74, 14-253, 14-260) ..................
16K (2K x 8) Dual-Port RAM (w/Semaphores) (14-9, 14-74, 14-139, 14-253) ............... ~ .....
32K (2K x 16) Dual-Port RAM (MASTER) (14-9, 14-68, 14-74, 14-253, 14-260) ...................
32K (2K x 16) Dual-Port RAM (SLAVE) (14-9, 14-74, 14-253) ..................................
32K (4K x 8) Dual-Port RAM (14-9, 14-68, 14-74, 14-253) ....................................
32K (4K x 8) Dual-Port RAM (w/Semaphores) (14-9, 14-74, 14-139, 14-253) .....................
64K (8K x 8) Dual-Port RAM (14-9, 14-68, 14-74) ...........................................
128K (16K x 8) Dual-Port RAM (14-9, 14-68, 14-74) .........................................
256K (32K x 8) Dual-Port RAM (14-9, 14-68, 14-74) .........................................
64K (8K x 8) Dual-Port RAM (SLAVE) (14-9,14-68, 14-74) ....................................
128K (16K x 8) Dual-Port RAM (SLAVE) (14-9, 14-68, 14-74) ..................................

ill

5-1
5-1
5-16
5-16
5-29
5-29
5-44
5-56
5-56
5-69
5-77
13-125
13-125
13-135
1\3-142
13-142

TABLE OF CONTENTS (CONT'D)
CONTENTS
FIFO Memo'rles
1017200
1017201 A
1017202A
10172021
1017203
1017204
10172041
1017205
10172103
10172104
10172401
10172402
10172403
10172404
10172413
1017252
1017M203
1017M204
1017M205
1017M206

PAGE
256 x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) ........................................ 6-1
512 x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) ........................................ 6-1
1K x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) ........................................ 6-14
1K x 9 FIFO (with Output Enable and Flag) ................................................. 6-27
2K x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) ........................................ 6-28
4K x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) ........................................ 6-28
4K x 9 FIFO (with Output Enable and Flag) ................................................. 6-41
8K x 9 FIFO .......................................................................... 6-42
2K x 9 Parallel-Serial FIFO (14-146) ....................................................... 6-43
4K x 9 Parallel-Serial FIFO (14-146) ....................................................... 6-43
64 x 4 FIFO ........................................................................... 6-69
64 x 5 FIFO ........................................................................... 6-69
64 x 4 FIFO with Output Enable .......................................................... 6-69
64 x 5 FIFO with Output Enable .......................................................... 6-69
64 x 5 FIFO (with Flags) ................................................................ 6-80
BiFIFO ............................................. '................................. 6-91
2K x 9 FIFO .......................................................................... 13-146
4K x 9 FIFO .......................................................................... 13-146
8K x 9 FIFO (14-1, 14-254, 14-257) ................................................... ; ... 13-157
16K x 9 FIFO (14-1, 14-254, 14-257) . '" .............................. " ...... " .......... 13-157

Digital SIgnal ProcessIng (DSP)
1017209
12 x 12 Parallel Multiplier-Accumulator (14-193) ................. '" ......................... 7-1
1017210
16 x 16 Parallel Multiplier-Accumulator (14-193) ......................................... " .. 7-9
1017243
16 x 16 Parallel Multiplier-Accumulator (19-Bit Output) (14-193) ................................ 7-9
1017212
12 x 12 Parallel Multiplier ............................................................... 7-20
12 x 12 Parallel Multiplier (Single Clock) ................................................... 7-20
1017213
32-/64-BitlEEE Floating-Point Multiplier (14-30, 14-95) ................................... '" . 7-30
101721264
101721265
32-/64-Bit IEEE Floating-Point ALU (14-30, 14-95) ............... '" ......................... 7-30
16 x 16 Parallel Multiplier (14-30) ..................................... '" ................. 7-55
1017216
1017217
16 x 16 Parallel Multiplier (Single Clock) (14-30) ............................................ 7-55
1017317
16 x 16 Parallel Multiplier (32-Bit Output) ............ , .. , ................................... 7-66
1017320
16-Bit Eight-level Pipeline Register ... " ............................................... '" . 7-68
1017381
16-Bit Cascadable ALU ................................................................. 7-70
Bit-Slice Microprocessor Devices (MICROSLICE TM) and Error Detection and Correction
Bit-Slice Microprocessor Devices (MICROSLlCE)
IOT39C01
4-Bit Microprocessor Slice (14-56) ................................' ........................ 8-1
IOT39C02
Carry-Lookahead Generator ................................. '" ......................... 8-12
IOT39C03
4-Bit Microprocessor Slice (14-56) ... " ............................................... " .. 8-16
IOT39C09
4-Bit Sequencer ....................................................................... 8-48
IOT39C11
4-Bit Sequencer .......................... " ........................................... 8-48
IOT39C10
12-Bit Sequencer (14-56,14-197) .. , .' .................................................... 8-63
IOT39C203
4-Bit Microprocessor Slice (14-56) ... " ................................................... 8-74
IOT39C705
16 x 4 Dual-Port RAM .................................................................. 8-110
16 x 4 Dual-Port RAM .................................................................. 8-110
IOT39C707
IOT49C25
Microcycle Length Controller ............................................................ 8-117
IOT49C401
16-Bit Microprocessor Slice ........................... ~ .. : .............................. 8-129
IOT49C402
16-Bit Microprocessor Slice (14-41, 14-56, 14-197, 14-200, 14-203) ........................... 8-139
IOT49C403
16-Bit Microprocessor Slice w/SPC (14-41, 14-56, 14-154, 14-197) ............................ 8-150
IOT49C404
32-Bit Microprogram Microprocessor w/SPC (14-86, 14-111, 14-154) ........................... 8-182
IOT49C410
16-Bit Sequencer (14-56,14-86,14-197,14-200) ........................................... 8-196
IOT49C411
20-Bit Interruptable Sequencer w/SPC (14-154) ............................................. 8-208
Error Detection and Correction
IOT39C60
16-Bit Cascadable EOC (14-22) .......................................................... 8-209
IOT49C460
32-Bit Cascadable EOC (14-22) .......................................................... 8-235

Iv

TABLE OF CONTENTS (CONT'D)
PAGE

CONTENTS

Reduced Instruction Set Computer (RISC) Processors
IDT79R2000
RISC CPU Processor ..........•........................................................ 9-1
IDT79R2010
RISC Floating-Point Accelerator (FPA) ..................................................... 9-10
IDT79R2020
RISC CPU Write Buffer ............................ ; .................................... 9-15
Logic Devices
IDT29FCT52
IDT29FCT53
IDT29FCT520
IDT29FCT521
IDT39C8XXX
IDT39C821
IDT39C822
IDT39C823
IDT39C824
IDT39C825
IDT39C826
IDT39C827
IDT39C828
IDT39C841
IDT39C842
IDT39C843
IDT39C844
IDT39C845
IDT39C846
IDT39C861
IDT39C862
IDT39C863
IDT39C864
IDT49 FCT60 1
IDT49FCT618
IDT49FCT661
IDT49FCT818
IDT54/74FCT138
IDT54/74FCT139
IDT54/74FCT161
IDT54/74FCT163
IDT54/74FCT182
IDT54/74FCT191
IDT54/74FCT193
IDT54/74FCT240
IDT54/74FCT241
IDT54/74FCT244
IDT54/74FCT245
IDT54/74FCT273
IDT54/74FCT299
IDT54/74FCT373
IDT54/74FCT374
IDT54/74FCT377
IDT54/74FCT399
IDT54/74FCT521
IDT54/74FCT533
IDT54/74FCT534
IDT54/74FCT540
IDT54/74FCT541
IDT54/74FCT543
IDT54/74FCT573
IDT54/74FCT574
IDT54/74FCT640

Non-Inverting Octal Register Transceiver (14-209) ..................•......•..............••. 10-1
Inverting Octal Register Transceiver (14-209) ................................•.............. 10-1
Multilevel Pipeline Register (14-209) ........................................•............. 10-6
Multilevel Pipeline Register (14-209) ...................................................... 10-6
IDT39C8XXX Family ............................................•......................• 10-11
10-Bit Non-Inverting Register (14-209) ...............................•......•.............. 10-164
10-Bit Inverting Register (14-209) ......................................................... 10-164
9-Bit Non-Inverting Register (14-209) ...................................................... 10-164
9-Bit Inverting Register (14-209) .......................................................... 10-164
8-Bit Non-Inverting Register (14-209) ...•.................................................. 10-164
8-Bit Inverting Register (14-209) .......................................................... 10-164
10-Bit Non-Inverting Buffer (14-209) ...............................................•....... 10-171
10-Bit Inverting Buffer (14-209) ...................................•............•.......... 10-171
10-Bit Non-Inverting Latch (14-209) ....................................................... 10-185
10-Bit Inverting Latch (14-209) ........................................................... 10-185
9-Bit Non-Inverting Latch (14-209) ...•.................................................... 10-185
9-Bit Inverting Latch (14-209) ............................................................ 10-185
8-Bit Non-Inverting Latch (14-209) ......•.•........................... ; ................... 10-185
8-Bit Inverting Latch (14-209) .....................................................•...... 10-185
10-Bit Non-Inverting Transceiver (14-209) ......................•........................... 10-192
10-Bit Inverting Transceiver (14-209) ....................................................•. 10-192
9-Bit Non-Inverting Transceiver (14-209) ...................................•............... 10-192
9-Bit Inverting Transceiver (14-209) ....................... ~ ............•..•............... 10-192
16-Bit Bidirectional Latch (14-209) ........................................................ 10-12
16-Bit Register with SPC (14-154,14-209) ....••.............•.•........................... 10-13
16-Bit Synchronous Binary Counter (14-209) ............................................... 10-29
Octal Register with SPC (14-154, 14-209) ................................................... 10-30
1-of-8 Decoder (14-209) ................................................................ ·10-43
Dual1-of-4 Decoder (14-209) .............................•.............................. 10-48
Synchronous Binary Counter w/Asynchronous Master Reset (14-209) ..............•............ 10-52
Synchronous Binary Counter w/Synchronous Reset (14-209) .................................. 10-52
Carry-Lookahead Generator (14-209) ..................................................... 10-57
Up/Down Binary Counter w/Preset and Ripple Clock (14-209) .................•.......•....... 10-62
Up/Down Binary Counter w/Separate Up/Down Clocks (14-209) ............................... 10-67
Inverting Octal Buffer/Line Driver (14-209) •........•....................................... 10-72
Non-Inverting Octal Buffer/Line Driver (14-209) ............................................. 10-76
Non-Inverting Octal Buffer/Line Driver (14-209) ......................................•...... 10-76
Non-Inverting Octal Bidirectional Transceiver (14-209) .................. : ..................•. 10-82
Octal D Flip-Flop w/Buffered Asynchronous Master Reset (14-209) ............................. 10-86
Universal Shift Register w/Common Parallel I/O Pins (14--209) ............................•.... 10-90
Octal Transparent Latch (14-209) ......................................................... 10-95
Non-Inverting Octal D Flip-Flop (14-209) ...... , ............................................ 10-99
Octal D Flip-Flop w/Clock Enable (14-209) •................•......................•........ 10-103
Quad Dual-Port Register (14-209) ....•.................•....c • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 10-107
8-Bit Comparator (14-209) .............................................................. 10-113
Octal Transparent Latch (14-209) ......................................•.................. 10-117
Octal D Flip-Flop (14-209) .............................................................. 10-121
Inverting Octal Buffer (14-209) .......................................•................... 10-125
Non-Inverting Octal Buffer (14-209) .....................................................•• 10-125
Octal Latched Transceiver (14-209) ....................................................... 10-129
Octal Transparent Latch (14-209) .............•............................................10-135
Octal D Register (14-209) ...............................................•............... 10-139
Inverting Octal Bidirectional Transceiver (14-209) .....................................•..... 10-143

v

TABLE OF CONTENTS (CONT'D)
CONTENTS
PAGE
Logic Devices (Cont'd.)
IDT54/74 FCT645 Octal Bidirectional Transceiver (14-209) ................................................... 10-147
IDT54/74FCT646 Non-Inverting Octal Register Transceiver (14-209) ........................................... 10-151
IDT54/74FCT648 Inverting Octal Register Transceiver (14-209) ............................................... 10-151
Inverting Octal Register Transceiver (14-209) ............................................... 10-157
IDT54/74FCT651
IDT54/74FCT652 Non-Inverting Octal Register Transceiver (14-209) ........................................... 10-157
IDT54/74FCT821 10-Bit Non-Inverting Register (14-209) ..................................................... 10-164
IDT54/74FCT822 10-Bit Inverting Register (14-209) ..............•.......................................... 10-164
IDT54/74FCT823 9-Bit Non-Inverting Register (14-209) ...................................................... 10-164
IDT54/74 FCT824 9-Bit Inverting Register (14-209) ....................................... , .................. 10-164
IDT54/7 4FCT825 8-Bit Non-Inverting Register (14-209) ...................................................... 10-164
IDT54/74FCT826 8-Bit Inverting Register (14-209) .......................................................... 10-164
IDT54/74FCT827 10-Bit Non-Inverting Buffer (14-209) ....................................................... 10-171
IDT54/74FCT828 10-Bit Inverting Buffer (14-209) ........................................................... 10-171
IDT54/74FCT833 8-Bit Transceiver w/Parity (14-209) ....................................................... 10-177
IDT54/74FCT834 8-Bit Transceiver w/Parity (14-209) ....................................................... 10--177
10-Bit Non-Inverting Latch (14-209) ....................................................... 10-185
IDT54/74FCT841
IDT54/74FCT842 10-Bit Inverting Latch (14-209) ........................................................... 10-185
IDT54/74FCT843 9-Bit Non-Inverting Latch (14-209) ........................................................ 10-185
IDT54/74 FCT844 9-Bit Inverting Latch (14-209) ............................................................ 10-185
IDT54/74FCT845 8-Bit Non-Inverting Latch (14-209) ..........................•............................. 10-185
IDT54/74FCT846 8-Bit Inverting Latch (14-209) ............................................................ 10-185
IDT54/74FCT853 8-Bit Transceiver w/Parity (14-209) ....................................................... 10-177
IDT54/74FCT854 8-Bit Transceiver w/Parity (14-209) ...............................................•....... 10-177
IDT54/74FCT861
10-Bit Non-Inverting Transceiver (14-209) ...................................•.............. 10-192
IDT54/74FCT862 10-Bit Inverting Transceiver (14-209) ...................................................... 10-192
IDT54/74FCT863 9-Bit Non-Inverting Transceiver (14-209) ................................................... 10-192
IDT54/74FCT864 9-Bit Inverting Transceiver (14-209) .................................................... ; .. 10-192
IDT54AHCT138
1-of-8 Decoder (14-209) ................................................................. 10-198
IDT54AHCT139
Dual 1-of-4 Decoder (14-209) .........................•.................................. 10-202
IDT54AHCT161
Synchronous Binary Counter w/Asynchronous Master Reset (14-209) ........................... 10-206
IDT54AHCT163
Synchronous Binary Counter w/Synchronous Reset (14-209) .................................. 10-206
IDT54AHCT182
Carry-Lookahead Generator (14-209) ..................................................... 10-211
IDT54AHCT191
Up/Down Binary Counter w/Asynchronous Presetting (14-209) ................................. 10-216
IDT54AHCT193
Up/Down Binary Counter w/Separate Up/Down Clocks (14-209) ............................... 10-220
IDT54AHCT240
Inverting Octal Buffer/Line Driver (14-209) ................................................. 10-225
IDT54AHCT244
Non-Inverting Octal Buffer/Line Driver (14-209) ............................................. 10-229
IDT54AHCT245
Octal Bidirectional Transceiver (14-209) ................................................•.. 10-233
IDT54AHCT273
Octal D Flip-Flop (14-209) ..............................•............................... 10-237
IDT54AHCT299
Universal Shift Register (14-209) ......................................................... 10-241
IDT54AHCT373
Octal Transparent Latch (14-209) ..•...................................................... 10-245
IDT54AHCT374
Non-Inverting Octal D Flip-Flop (14-209) ................•.................................. 10-249
IDT54AHCT377
Octal D Flip-Flop w/Clock Enable (14-209) ................................................. 10-253
IDT54AHCT521
8-Bit Comparator (14-209) ......... , .................................................... 10-257
IDT54AHCT533
Octal Transparent Latch (14-209) ........... ~ •..........•.....................•........... 10-261
IDT54AHCT534
Inverting Octal D Flip-Flop (14-209) ....................................................... 10-265
IDT54AHCT573
Octal Transparent Latch (14-209) .............................................•...•....... 10-269
IDT54AHCT574
Octal D Register (14-209) ........................•.............................••....... 10-273
Inverting Octal Bidirectional Transceiver (14-209) ..... ; .....................•.....•.......•. 10-277
IDT54AHCT640
IDT54AHCT645
Non-Inverting Octal Bidirectional Transceiver (14-209) ....................................... 10-281
Common Waveform Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-285
Data Conversion
IDT75C18
8-Bit Video DAC (14-266) ............................................................... 11-1
IDT75C19
9-Bit Video DAC (14-266) ............................................................... 11-12
Triple 8-Bit Video DAC Module (14-266) .........................•......................... 11-23
IDT75MB38
Triple 8-Bit Palette DAC .......................................... '.' . . . . . . . . . . . . . . . . . . . . . 11-29
IDT75C458
8-Bit Flash ADC ......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42
IDT75C48
8-Bit Flash ADC w/Overflow Output ................................. . . . . . . . . . . . . . . . . . . . . . . 11-50
IDT75C58
8-Bit Flash ADC Module .............•......•........................................... 11-58
IDT75M48
9-Bit Flash ADC Module ................................................................ 11-59
IDT75M49

vi

.-----------------------------------------------------------------------------------

TABLE OF CONTENTS (CONT'D)
CONTENTS
·PAGE
EEPROMs-Electrically Erasable Programmable Read Only Memories
16K (2K x 8) EEPROM ........................................ , ....................... ,. 12-1
IDT78C16A
IDT78C18A
16K (2K x 8) EEPROM w/SPC (14-154) .................................................... 12-10
8K x 8 EEPROM Module ................................................................ 12-22
IDT78M64
IDT78C64A
64K (8K x 8) EEPROM .................................................................. 12-30
IDT78C464A
64K (8K x 8) Registered EEPROM ........................................................ 12-32
IDT78C564A
64K (8K x 8) Registered EEPROM w/SPC (14-154) .......................................... 12-34
IDT78C256A
256K (32K x 8) EEPROM ................................................................ 12-36
IDT78C4256A
256K (32K x 8) Registered EEPROM ...................................................... 12-38
IDT78C5256A
256K (32K x 8) Registered EEPROM w/SPC (14-154) ........................................ 12-40
Subsystems Modules
Subsystem Ordering Information Page
Static RAM Modules
IDT7MB624
1 Megabit (64K x 16) CMOS SRAM (Plastic DIP) ............................................ 13-1
IDT7MC156
256K x 1 CMOS SRAM (Ceramic SIP) ..................................................... 13-3
IDT7MC4001
1 Megabit (1024K x 1) CMOS SRAM w/Separate I/O (Ceramic SIP) ............................. 13-9
IDT7MC4032
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) ........................................... 13-15
IDT7MP156
256K (256K x 1) CMOS SRAM (Plastic SIP) ....................... , ....................... ,. 13-17
IDT7MP456
256K (64K x 4) CMOS SRAM (Plastic SIP) .................................................. 13-23
IDT7MP564
80K (16K x 5) CMOS SRAM (Plastic SIP) ................................................... 13-29 .
IDT7MP4008
4 Megabit (512K x 8) CMOS SRAM (Plastic SIP) ............................................. 13-35
IDT7M624
1 Megabit (64K x 16) CMOS SRAM ....................................................... 13-41
IDT7M656
256K (16K x 16) CMOS SRAM ........................................................... 13-48
IDT7M812
512K (64K x 8) CMOS SRAM ............................................................ 13-57
IDT7M856
256K (32K x 8-Bit) CMOS Static RAM ..................................................... 13-63
IDT7M912
512K (64K x 9) CMOS SRAM ............................................................ 13-57
IDT7M4016
4 Megabit (256K x 16) CMOS SRAM ............. , ........................................ 13-70
IDT7M4017
2 Megabit (64K x 32) CMOS SRAM ....................................................... 13:-72
IDT8MP612
512K (32K x 16) CMOS SRAM (Plastic SIP) ................................................. 13-74
IDT8MP624
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) ....... , ..................................... 13-74
IDT8MP628
128K (8K x 16) CMOS SRAM (Plastic SIP) .................................................. 13-80
IDT8MP656
256K (16K x 16) CMOS SRAM (Plastic SIP) ................................................. 13-80
IDT8MP824
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) ............................................. 13-86
IDT8M612
512K (32K x 16) CMOS SRAM ........................................................... 13-92
IDT8M624
1 Megabit (64K x 16) CMOS SRAM ....................................................... 13-92
IDT8M628
128K (8K x 16) CMOS SRAM ............................................................ 13-99
IDT8M656
256K (16K x 16) CMOS SRAM ........................................................... 13-99
IDT8M824
1 Megabit (128K x 8) CMOS SRAM ....................................................... 13-107
IDT8M856
256K (32K x 8) Low-Power CMOS SRAM ................................................... 13-113
Dual-Port RAM, FIFO and Application Specific Memory Modules
8K x 112 High-Speed Writable Control Store w/SPC (14-154) .................................. 13-121
IDT7MB6042
IDT7MP6025
512K (64K x 8) Synchronous SRAM (Plastic SIP) ............................................ 13-123
IDT7M134
64K (8K x 8) Dual-Port RAM (14-9, 14-68, 14-260) .......................................... 13-125
IDT7M135
128K (16K x 8) Dual-Port RAM (14-9, 14-68, 14-260) ........................................ 13-125
IDT7M137
256K (32K x 8) Dual-Port RAM (14-9, 14-68, 14-260) ........................................ 13-135
IDT7M144
64K (8K x 8) Dual-Port RAM (SLAVE) (14-9,14-68, 14-260) ................................... 13-142
IDT7M145
128K (16K x 8) Dual-Port RAM (SLAVE) (14-9, 14-68, 14-260) ................................. 13-142
IDT7M203
CMOS Parallel In-Out FIFO Module 2K x 9-Bit & 4K x 9-Bit .................................... 13-146
CMOS Parallel In-Out FIFO Module 2K x 9-Bit & 4K x 9-Bit .................................... 13-146
IDT7M204
8K x 9 FIFO (14-1, 14-254, 14-257) ....................................................... 13-157
IDT7M205
IDT7M206
16K x 9 FIFO (14-1, 14-254, 14-257) ................ , ..................................... 13-157
IDT7M824
1 Megabit (128K x 8) Registered and Buffered SRAM Subsystem Family ........... , ............. 13-168
IDT7M820
128K x 8 SRAM w/Latched Address, Latched Data In, Latched Data Out ...................... 13-172
IDT7M821
128K x 8 SRAM w/Latched Address, Registered Data In, Registered Data Out ................. 13-175
IDT7M822
128K x 8 SRAM w/Latched Address, Registered Data In, Latched Data Out .................... 13-178
IDT7M823
128K x 8 SRAM w/Latched Address, Latched Data In, Registered Data Out .................... 13-181
IDT7M825
128K x 8 SRAM w/Registered Address, Registered Data In, Registered Data Out ............... 13-184
IDT7M826
128K x 8 SRAM w/Registered Address, Registered Data In, Latched Data Out ................. 13-187
IDT7M827
128K x 8 SRAM w/Registered Address, Latched Data In, Registered Data Out ................. 13-190
IDT7M828
128K x 8 SRAM w/Registered Address, Latched Data In, Latched Data Out .................... 13-193

vii

TABLE OF CONTENTS (CONT'D)
CONTENTS
Subsystems Modules (Cont'd.)
IDT75M48
8-Bit Flash ADC .......................................................................
IDT75M49
9-Bit Flash ADC ................................ ; .......................................
IDT75MB38
Triple 8-Bit Video DAC Module (14-266) ...................................................
IDT7M6001
Dual, Multiplexed 16K x 20 SRAM ..•.....................................................
IDT7M6032
16K x 32 High-Speed Writable Control Store w/SPC (14-154) ..................................
IDT78M64
8K x 8 EEPROM ........................................................................
Application and Technical Notes
Application Notes
Understanding the IDT7201/7202 FIFO .....................................................
AN-01
AN-02
Dual-Port RAMs Simplify Communications in Computer Systems (Rev. 1) ................ '" .....
AN-03
Trust Your Data with a High-Speed CMOS 16-,32- or 64-Bit EDC ..............................
AN-04
High-Speed CMOS TTL-Compatible Number-Crunching Elements for
Fixed- and Floating-Point Arithmetic ............................. : ................ ; ......
AN-OS
Separate I/O RAMs Increase Speed and Reduce Part Count ...................................
AN-06
, 16-Bit CMOS Slices-New Building Blocks Maintain Microcode Compatibility
Yet Increase Performance ............. ; .................................................
AN-07
Cache Tag RAM Chips Simplify Cache Memory Design ......................................
AN-OB
CMOS Breathes New Life Into Bit-Slice .............. : .....................................
AN-09
Dual-Port RAMs Yield Bit-Slice Designs Without Microcode ...................................
AN-10
Low-Power and Battery Back-Up Operation of CMOS Static RAMs ..............................
AN-11
A Powerful New Architecture for a 32-Bit Bit-Slice Microprocessor ..............................
AN-12
Using the IDT721264/65 Floating-Point Chip Set .......................•....................
AN-13
The IDT49C404 32-Bit Microprogram Microprocessor .. : .....................................
AN-14
Dual-Port RAMs with Semaphore Arbitration ................................................
AN-15
USing the IDT721 03/04 Serial-Parallel FIFO .................................................
AN-16
SPC Provides Board and System Level Testing Through a Serial Scan Technique .................
AN-17
FIR Filter Implementation Using FIFOs & MACs .............................................
AN-1B
High-Performance Controllers Need Microprogramming ......................................
Te~hnical Notes
TN-02
Build a 20 MIP Data Processing Unit ......................................................
TN-03
Using the. IDT49C402A ALU .............................................................
TN-04
Using High-Speed 8K x 8 RAMs ............................................ " ............
TN-OS
FCT -Fast, CMOS, TTL-Compatible Logic .................................................
TN-06
Designing with FIFOs ..................................................................
TN-07
Fast RAMs Give Lowest Power ............................................•..............
TN-DB
Operating FIFOs on Full and Empty Boundary' Conditions ....................................
TN-09
Cascading FIFOs or FIFO Modules .......................................................
TN-10
Dual-Port RAM Address Arbitration Metastability Testing ......................................
TN-11
Cache Timing for the 68020 ..............................................................
TN-12
Using IDT's Video D~Cs in 5V Only Systems ...............................................
TN-13
Cache Timing for the"B0386 ........................•.....................................
Package Diagram Outlines
Thermal Performance Data of IDT Packages ....................... , .........................................
Package Diagram Outline Indexes ......... ~ ..........................................•...................
Package Diagram Outlines ............... '" .. '.' . '.' ......................... " ..........•................

viii

PAGE
11-58
11-59
11-23
13-197
13-199
12-22

14-1
14-9
14-22
14-30
14-36
14-41
14-47
14-56
14-68
14-74
14-86
14-95
14-111
14-139
14-146
14-154
14-193
14-197
14-200
14-203
14-207
14-209
14-251
14-253
14-254
14-257
14-260
14-264
14-266
14-268
15-1
15-3
15-7

NUMERIC TABLE OF CONTENTS
PART #
100490
29FCT52
29FCT520
29FCT521
29 FCT53
39C01
39C02
39C03
39C09
39C10
39C11
39C203
39C60
39C705
39C707
39C8XXX
49C25
49C401
49C402
49C403
49C404
49C410
49C411
49C460
49FCT601
49FCT618
49FCT661
49FCT818
54/74FCT138
54/74FCT139
54/74FCT161
54/74FCT163
54/7 4FCT182
54/74FCT191
54/74FCT193
54/74FCT240
54/74 FCT241
54/74FCT244
54/74FCT245
54/74FCT273
54/74 FCT299
54/74 FCT373
54/74 FCT374
54/74FCT377
54/74 FCT399
54/74FCT521
54/74FCT533
54/74FCT534
54/74FCT540
54/74FCT541
54/74 FCT543
54/74FCT573
54/74 FCT574
54/74FCT640
54/74 FCT645
54/74 FCT646
54/74FCT648
54/74FCT651

PAGE
64K (64K x 1) BiCMOS SRAM with ECLI/O ................................................ 4-52
Non-Inverting Octal Register Transceiver ................................................... 10-1
Multilevel Pipeline Register .............................................................. 10-6
Multilevel Pipeline Register .............................................................. 10-6
Inverting Octal Register Transceiver ....................................................... 10-1
4-Bit Microprocessor Slice ............................................ ; ................. 8-1
Carry-Lookahead Generator ............................................................. 8-12
4-Bit Microprocessor Slice ............................................... ~ .............. 8-16
4-Bit Sequencer ....................................................................... 8-48
12-Bit Sequencer. . . . . . . . . . . . . . . . . . . .. . .................... ; .......................... 8-63
4-Bit Sequencer ........•...........................................................•.. 8-48
4-Bit Microprocessor Slice ...............................••............................. 8-74
16-Bit Cascadable EDC .....•........................................................... 8-209
16 x 4 Dual-Port RAM ................................................. '...........•..... 8-110
16 x 4 Dual-Port RAM ...................................•••............................ 8-110
39C8XXX Family ...................................................................... 10-11
Microcycle Length Controller ..............................................•............. 8-117
16-Bit Microprocessor Slice .............................................................. 8-129
16-Bit Microprocessor Slice ............................................................. 8-139
16-Bit Microprocessor Slice w/SPC ....................................................... 8-150
32-Bit Microprocessor Slice w/SPC •...................................... : ............... 8-182
16-Bit Sequencer ..................................................... :'................ 8-196
20-Bit Interruptable Sequencer w/SPC ....................•....................•........... 8-208
32-Bit Cascadable EDC ................................................................. 8-235
16-Bit Bidirectional Latch ............................................................... 10-12
16-Bit Register with SPC ....................................... ; ......................... 10-13
16-Bit Synchronous Binary Counter ....................................................... 10-29
Octal Register with SPC .. '..................................................•........... 10-30
1-of-8 Decoder ................................•....... '................ " .............. 10-43
Dual 1-of-4 Decoder .................................................................... 10-48 '
Synchronous Binary Counter w/Asynchronous Master Reset .......•........................... 10-52
Synchronous Binary Counter w/Synchronous Reset ...............................••......... 10-52
Carry-Lookahead Generator ... ' ........................' .. '...................•............ 10-57
Up/Down Binary Counter w/Preset and Ripple Clock ....................................... ': . 10-62
Up/Down Binary Counter w/Separate Up/Down Clocks ....................................... 10-67
Inverting Octal Buffer/Line Driver .......................................... , ............... 10-72
Non-Inverting Octal Buffer/Line Driver .................................................. '... 10-76
Non-Inverting Octal Buffer/Line Driver ................................. ; .•................. 10-76
Non-Inverting Octal Bidirectional Transceiver ................................... " .......... 10-82
Octal D Flip-Flop w/Buffered Asynchronous Master Reset ......... ; ...............•...•....... 10-86
Universal Shift Register w/Common Parallel I/O Pins ......................................... 10-90
Octal Transparent Latch ................................................................ 10-95
Non-Inverting Octal D Flip-Flop .......................................................... 10-99 '
Octal D Flip-Flop w/Clock Enable ......................................................... 10-103
Quad Dual-Port Register ...................... '..:.......................... , ............. 10-107
8-Bit Comparator ...............•.................... , ................... '......•..•...• 10":113
Octal Transparent Latch ........ ' .........................................•............... 10-117
Octal D Flip-Flop .......................... " ................•......................... 10-121
Inverting Octal Buffer ...........................•....................................... 10-125
Non-Inverting Octal Buffer ............................................................... 10-125
Octal Latched Transceiver ......................•............ ; ........................... 10-129
Octal Transparent Latch .................................. '.............................. 10-135
Octal D Register ....................................... ,' ................................ 10-139
Inverting Octal Bidirectional Transceiver ................................................... 10-143
Octal Bidirectional Transceiver ...........................................•............... 10-147
Non-Inverting Octal Buffer ............................................................... 10-151
Inverting Octal Register Transceiver ..................................................•.... 10-151
Inverting Octal Register Transceiver ....................................................... 10-157

Ix

NUMERIC,TABLE OF CONTENTS (CON'T.)
PART #
54/74FCT652
54/7 4FCT821
54/74 FCT822
54/74FCT823
54/74FCT824
54/74FCT825
54/74 FCT826
54/7 4 FCT827
54/74 FCT828
54/74 FCT833
54/74FCT834
54/74FCT841
54/74FCT842
54/74FCT843
54/74FCT844
54/74 FCT845
54/7 4FCT846
54/74FCT853
54/74FCT854
54/74 FCT861
54/74FCT862
54/74FCT863
54/74FCT864
54AHCT138
54AHCT139
54AHCT161
54AHCT163
54AHCT182
54AHCT191
54AHCT193
54AHCT240
54AHCT244
54AHCT245
54AHCT273
54AHCT299
54AHCT373
54AHCT374
54AHCT377
54AHCT521
54AHCT533
54AHCT534
54AHCT573
54AHCT574
54AHCT640
54AHCT645
6116
61298
6167
6168
6178
6198
71024
71027
71028
71256
71257
71258
71281

PAGE

Non-Inverting Octal Register Transceiver ......................•........•................... 10-157
10-Bit Non-Inverting Register .................................•....•.•................... 10-164
10-Bit Inverting Register ...............•..................•••.... : ....•................. 10-164
9-Bit Non-Inverting Register ............................................................. 10-164
9-Bit Inverting Register ...................•............................................. 10-164
8-Bit Non-Inverting Register ............................................................. 10-164
8-Bit Inverting Register .............................................•..•................ 10-164
10-Bit Non-Inverting Buffer .............................................................. 10-171
10-Bit Inverting Buffer ..........•....................................................... 10-171
8-Bit Transceiver w/Parity ............................................................... 10-177
8-Bit Transceiver w/Parity ..........•.................................................... 10-177
10-Bit Non-Inverting Latch .......................... '.~ .................•................. 10-185
10-Bit Inverting Latch ................................................................... 10-185
9-Bit Non-Inverting Latch ................................................................ 10-185
9-Bit Inverting Latch ..............•..................................................... 10-185
8-Bit Non-Inverting Latch ........•.•...................•........................•........ 10-185
8-Bit Inverting Latch .........•..................................•....................... 10-185
8-Bit Transceiver w/Parity ............................................................... 10-177
8-Bit Transceiver w/Parity .........•..................••................................. 10-177
10-Bit Non-Inverting Transceiver .............•.. .-. . . . . . . . . . • . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . 10-192
10-Bit Inverting Transceiver ...••..............•..........•..•.•..•....................... 10-192
9-Bit Non-Inverting Transceiver ..•........................................................ 10-192
9-Bit Inverting Transceiver .......•............................................•.......... 10-192
1-of-8 Decoder .....................................•.•................................ 10-198
Dual 1-of-4 Decoder .................................................•................. 10-202
Synchronous Binary Counter w/Asynchronous Master Reset ................................... 10-206
Synchronous Binary Counter w/Synchronous Reset .......................................... 10-206
Carry-Lookahead Generator ............................................................. 10-211
Up/Down Binary Counter w/Asynchronous Presetting ...........................•............ 10-216
Up/Down Binary Counter w/Separate Up/Down Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-220
Inverting Octal Buffer/Line Driver ...........................................•.•........... 10-225
Non-Inverting Octal Buffer/Line Driver ........................................••........... 10-229
Octal Bidirectional Transceiver ......................•.................................... 10-233
Octal D Flip-Flop ....................................•................................. 10-237
Universal Shift Register ................................................................. 10-241
Octal Transparent Latch .....•..........................................•............... 10-245
Non-Inverting Octal D Flip-Flop .......................................................... 10-249
Octal D Flip-Flop w/Clock Enable ...........................•.......................... '.. 10-253
8-Bit Comparator " ..........•.................................•........................ 10-257
Octal Transparent Latch ...............................•....................•........... 10-261
Inverting Octal D Flip-Flop ......... '..............................•...................... 10-265
Octal Transparent Latch ...................................... '.... ; ..................... 10-269
Octal D Register ..........................................................•............ 10-273
Inverting Octal Bidirectional Transceiver ......................................•............ 10-277
Non-Inverting Octal Bidirectional Transceiver ............................................... 10-281
16K (2K x 8) CMOS SRAM .............................................................. 4-33
256K (64K x 4) CMOS SRAM (with Output Enable) ............... .- ........................... 4-133
16K (16K x 1) CMOS SRAM (Power Down) .........................•....................... 4-1
16K (4K x 4) CMOS SRAM (Power Down) .................................................. 4-11
16K (4K x 4) CMOS Cache-Tag SRAM ................................... , ................. 4-184
64K (16K x 4) CMOS SRAM (with Output Enable) ...................••....................... 4-65
1 Megabit (128K x 8) CMOS SRAM (Power Down) ........................................... 4-173
1 Megabit (1024K x 1) CMOS SRAM (Power Down) .......................................... 4-168
1 Megabit (256K x 4) CMOS SRAM (Power Down) ........................................... 4-171
256K (32K x 8) CMOS SRAM (Power Down) ................................................ 4-153
256K (256K x 1) CMOS SRAM (Power Down) ............................................... 4-113
256K (64K x 4) CMOS SRAM ................................... ; ........................ 4-124
CMOS SRAM (Separate I/O-Output Follows Input at Write) ................................... 4-143

x

NUMERIC TABLE OF CONTENTS (CON'T.)
PART #

PAGE

71282
7130
7132
71321
71322
7133
7134
71342
7140
7142
71421
7143
71501
71502
7164
7165
71681
71682
7174
7186
7187
7188
7198
71981
71982
71C65
7200
7201A
72021
7202A
7203
7204
72041
7205
7209
7210
72103
72104
7212
721264
721265
7213
7216
7217
72401
72402
72403
72404
72413
7243
7252
7317
7320
7381
75C18
75C19
75C458
75C48

CMOS SRAM (Separate I/O-Output High Z at Write) ........................................ 4-143
8K (1 K x 8) Dual-Port RAM (MASTER) ..................................................... 5-1
16K (2K x 8) Dual-Port RAM (MASTER) .................................................... 5-16
16K (2K x 8) Dual-Port RAM (MASTER w/lnterrupts) .......................................... 5-29
16K (2K x 8) Dual-Port RAM (w/Semaphores) ............................................... 5-44
32K (2K x 16) Dual-Port RAM (MASTER) ................................................... 5-56
32K (4K x 8) Dual-Port RAM ............................................................. 5-69
32K (4K x 8) Dual-Port RAM (w/Semaphores) ............................................... 5-77
8K (1K x 8) Dual-Port RAM (SLAVE) ....................................................... 5-1
16K (2K x 8) Dual-Port RAM (SLAVE) ...................................................... 5-16
16K (2K x 8) Dual-Port RAM (SLAVE w/lnterrupts) ........................................... 5-29
32K (2K x 16) Dual-Port RAM (SLAVE) .•.............. '..................................... 5-56
64K (64K x 1) CMOS Synchronous RAM ......................................... : ......... 4-215
64K (4K x 16) CMOS Registered RAM (for Writable Control Stores) ............................. 4-224
64K (8K x 8) CMOS SRAM (Power Down) .................................................. 4-94
64K (8K x 8) Resettable CMOS SRAM ..................................................... 4-196
16K (4K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) ........................ 4-22
16K (4K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) .............................. 4-22
64K (8K x 8) CMOS Cache-Tag SRAM ..................................................... 4-186
64K (4K x 16) CMOS SRAM (Power Down) .................................................. 4-103
64K (64K x1) CMOS SRAM (Power Down) ................................................. 4-44
64K (16K x 4) CMOS SRAM (Power Down) ................................................. 4-57
64K (16K x 4) CMOS SRAM (2 CS and OE) ................................................ 4-74
64K (16K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) ....................... 4-84
64K (16K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) ................. , ........... 4-84
64K (8K x 8) SRAM (Resettable CMOS I/O) ................................................. 4-206
256 x 9 FIFO .......................................................................... 6-1
512 x 9 FIFO .......................................................................... 6-1
1K x 9 FIFO (with Output Enable and Flag) ................ ; ................................ 6-27
1K x 9 FIFO ..................•....................................................... 6-14
2K x 9 FIFO .......................................................................... 6-28
4K x 9 FIFO ..•....................................................................... 6-28
4K x 9 FIFO (with Output Enable and Flag) .....•........................................... 6-41
8K x 9 FIFO .......................................................................... 6-42
12 x 12 Parallel Multiplier-Accumulator .................................................... 7-1
16 x 16 Parallel Multiplier-Accumulator .................................................... 7-9
2K x 9 Parallel-Serial FIFO .............................................................. 6-43
4K x 9 Parallel-Serial FIFO ..................................... ; ........................ 6-43
12 x 12 Parallel Multiplier ...........•................................................... 7-20
32-/64-Bit IEEE Floating-Point Multiplier ................................................... 7-30
32-/64-Bit IEEE Floating-Point ALU ....................................................... 7-30
12 x 12 Parallel Multiplier (Single Clock) ................................................... 7-20
16 x 16 Parallel Multiplier ..... : ......................................................... 7-55
16 x 16 Parallel Multiplier (Single Clock) ................................................... 7-55
64 x 4 FIFO ........................................................................... 6-69
64 x 5 FIFO ........................................................................... 6-69
64 x 4 FIFO with Output Enable .......................................................... 6-69
64 x 5 FIFO with Output Enable .......................................................... 6-69
64 x 5 FIFO (with Flags) ................................................................ 6-80
16 x 16 Parallel Multiplier-Accumulator (19-Bit Output) ........................................ 7-9
BiFIFO ...................................... '........................................ 6-91
16 x 16 Parallel Multiplier (32-Bit Output) ................................................... 7-66
1-Bit CMOS Eight-level Pipeline Register ................................................... 7-68
16-Bit Cascadable ALU ................................................................. 7-70
8-Bit Video DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
9-Bit Video DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Triple 8-Bit PaietteDAC ................................................................. 11-29
8-Bit Flash ADC ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42

xi

NUMERIC TABLE OF CONTENTS (CON'T.)
PART #
75C58
75M48
75M49
75MB38
78C16A
78C18A
78C256A
78C4256A
78C464A
78C5256A
78C564A
78C64A
78M64
79R2000
79R2010
79R2020
7M134
7M135
7M137
7M144
7M145
7M203
7M204
7M205
7M206
7M4016
7M4017
7M6001
7M6032
7M624
7M656
7M812
7M820
7M821
7M822
7M823
7M824
7M825
7M826
7M827
7M828
7M856
7M912
7MB6042
7MB624
7MC156
7MC4001
7MC4032
7MP156
7MP4008
7MP456
7MP564
7MP6025
8M612
8M624
8M628
8M656
8M824

PAGE

8-Bit Flash ADC w/Overflow Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50
8-Bit Flash ADC .........•.............................................. '. . . . . . . . . . . . . . . 11-58
CMOS 9-Bit Flash ADC ................................................................ 11-59
Triple 8-Bit Video DAC ...............................•................................. 11-23
16K (2K x 8) EEPROM .......•.............................•............................ 12-1
16K (2K x 8) EEPROM w/SPC ............................................................ 12-10
256K (32K x 8) EEPROM ................................................................ 12-36
256K (32K x 8) Registered EEPROM ........................................•............. 12-38
64K (8K x 8) Registered EEPROM ...........................................•..........•. 12-32
256K (32K x 8) Registered EEPROM w/SPC ................................................ 12-40
64K (8K x 8) Registered EEPROM w/SPC ....... ~ .......................................... 12-34
64K (8K x 8) EEPROM .................................................................. 12-30
8K x 8 EEPROM ........•.............................................................. 12-22
RISC CPU Processor ....•.....•........................................................ 9-1
RISC Floating-Point Accelerator (FPA) ....•...•...............•............................ 9-10
RISC CPU Write Buffer .......••................•.•...............•..........••......... 9-15
64K (8K x 8) Dual-Port RAM ....•..............................................•......... 13-125
128K (16K x 8) Dual-Port RAM ........................................................... 13-125
256K (32K x 8) Dual-Port RAM ........................................................... 13-135
64K (8K x 8) Dual-Port RAM (SLAVE) ...................................................... 13-142
128K (16K x 8) Dual-Port RAM (SLAVE) .................................................... 13-142
CMOS Parallel In-Out FIFO Module 2K x 9-Bit & 4K x 9-Bit .................................... 13-146
CMOS Parallel In-Out FIFO Module 2K x 9-Bit & 4K x 9-Bit ..........................•......... 13-146
8K x 9 FIFO ...............................•.......................................... 13-157
16K x 9 FIFO ............•..................................•. ~ .•..................... 13-157
4 Megabit (256K x 16) CMOS SRAM .............. : ....................................... 13-70
2 Megabit (64K x 32) CMOS SRAM ....................................................... 13-72
Dual, Multiplexed 16K x 20 SRAM .................................................•..•... 13-197
16K x 32 High-Speed Writable Control Store w/SPC ..................•........•.............. 13-199
1 Megabit (64K x 16) CMOS SRAM ....................................................... 13-41
256K (16K x 16) CMOS SRAM .•.••.•.................................................... 13-48
512K (64K x 8) CMOS SRAM ...........•................................................ 13-57
128K x 8 SRAM w/Latched Address, Latched Data In, Latched Data Out .'~ .............•......... 13-172
128K x 8 SRAM w/Latched Address, Registered Data In, Registered Data Out ..........•......... 13-175
128K x 8 SRAM w/Latched Address, Registered Data In, Latched Data Out ....................... 13-178
128K x 8 SRAM w/Latched Address, Latched Data In, Registered Data Out ....................... 13-181
1 Megabit (128K x 8) Registered and Buffered SRAM'Subsystem Family ......................... 13-168
128K x 8 SRAM w/Registered Address, Registered Data In, Registered Data Out ........•......... 13-184
128K x 8 SRAM w/Registered Address, Registered Data In, Latched Data Out .................... 13-187
128K x 8 SRAM w/Registered Address, Latched Data In, Registered Data Out .............•....•. 13-190
128K x 8 SRAM w/Registered Address, Latched Data In, Latched Data Out ....................... 13-193
256K (32K x 8-Bit) CMOS SRAM Module ........•........................................•. 13-63
512K (64K x 9) CMOS SRAM ............................................................ 13-57
High-Speed Writable Control Store w/SPC ...........................•..................... 13-121
1 Megabit (64K x 16) CMOS SRAM (Plastic DIP) ............................................ 13-1
256K x 1 CMOS SRAM (Ceramic SIP) ..................................................... 13-3
1 Megabit (1024 x 1) CMOS SRAM w/Separate I/O (Ceramic SIP) .............................. 13-9
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) ........................................... 13-15
256K (256K x 1) CMOS SRAM (Plastic SIP) ................................................. 13-17
4 Megabit (512K x 8) CMOS SRAM (Plastic SIP) ............................................. 13-35
256K (64K x 4) CMOS SRAM (Plastic SIP) ................•..•.............................. 13-23
80K (16K x 5) CMOS SRAM (Plastic SIP) ............. ; .... ; ........... '" .................. 13-29
512K (64K x 8) Synchronous SRAM (Plastic SIP) ............................................ 13-123
512K (32K x 16) CMOS SRAM ........................................................... 13-92
1 Megabit (64K x 16) CMOS SRAM ....................................................... 13-92
128K (8K x 16) CMOS SRAM ............................................................ 13-99
256K (16K x 16) CMOS SRAM ........................................................... 13-99
1 Megabit (128K x 8) CMOS SRAM ....................................................... 13-107

xII

NUMERIC TABLE OF CONTENTS (CON'T.)
PAGE

PART#
SMS56
SMP612
SMP624
SMP62S
SMP656
SMPS24

256K (32K x 8) Low-Power CMOS SRAM ......................••..•..•.•...•....•.........•
512K (32K x 16) CMOS SRAM (Plastic SIP) .....•.•..•••••......•...•...•...•.•..••..•••...•
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) .................•••••...•...•.•...•........•
12SK (SK x 16) CMOS SRAM (Plastic SIP) ......•.•..•.••..•....•..•.............•..•.••..••
256K (16K x 16) CMOS SRAM (Plastic SIP) .............•...................•........•••...•
1 Megabit (12SK x S) CMOS SRAM (Plastic SIP) ......................................•......

xiii

13-113
13-74
13-74
13-S0
13-S0
13-S6

Product Selector and Cross Reference Guides

iI

PART NUMBER DESCRIPTION
4. A device speed identifier, when applicable, is either alpha characters, such as "A" or "8", or numbers, such as 20 or 45. The
speed units, depending on the product, are in nanoseconds or
megahertz.
5. A package identifier, composed of one or two alpha characters.
The data sheet should be consulted to determine the packages
available and the package identifiers for that particular product.
6. A temperature/process identifier. The product is available in
either the commercial or military temperature range, processed
to a commercial specification, or the product is available in the
military temperature range with full compliance to MILSTD-883. Many of lOT's products have burn-in included as part
of the standard commercial process flow.
7. A special process identifier, composed of alpha characters, is
used for products which require radiation enhancement (RE) or
tolerance (RT).

lOT's part number identifies the basic product, speed, power,
package(s) available, operating temperature and processing
grade. Each data sheet has a detailed description, using the
part number, on ordering the proper product for the user's application. The part number is comprised of a series of alpha-numeric
characters:
1. An "lOT" corporate identifier for Integrated Device Technology,
Inc.
2. A basic device part number composed of alpha-numeric
characters.
3. A device power identifier, composed of one or two alpha characters, is used to identify the power options. In most cases, the
following alpha characters are used:
"S" or "SA" is used for the standard product's power.
"LD or "LA" is used for lower power than the standard product.

Example:
IDT

xxx... xxx
Special Process
Processrremperature*
Package·
Speed
Power
Device Type*

• Field Identifier Applicable To All Products

1-1

High-Speed CMOS M,eROS,-,eETM Products

·

··
·

·
·
·

CMOS microprogrammable bit-slice microprocessor
family
CMOS Error Detection and Correction product family
IDT49COOO products offer dramatically improved system
performance through new innovative architectures
IDT39COOO products are pin-compatible, performanceenhanced 2900 family replacements

t/)

Meets or exceeds bipolar speeds and output drive at a
small fraction of the power consumption
Sequential letter suffix designates 20 % -40 % speed
upgrade
Instruction set/operation codes functionally identical to
2900 family

Oper. Power (max.)
(mW)
Mil.

Part Number

Description

Replaces

IDT39C01C
IDT39C01D
IDT39C01E

4-Bit lAP Slice

Am2901B,C; Am29C01C;
CY7C901

157
184
210

192
220
247

IDT39C03A
IDT39C03B

4-Bit lAP Slice

Am2903A

265

330

IDT39C203

4-Bit lAP Slice

Am29203

265

330

16-Bit lAP Slice

IMI4X2901B

945

1200

16-Bit lAP Slice, Quad 2901 with 8
additional destination functions and a
64 x 16 dual-port memory capacity

Four 2901 s & One 2902;
Am29C101; CY7C9101;
WSI59016

945

1200

IDT49C403
IDT49C403A

16-Bit lAP Slice, Quad 2903/29203 with
64 X 16 register file, 4 Q-registers, word/
BYTE control, BYTE swap, cascadable

Four 2903/29203s &
One 2902

1180

1375

IDT49C404

32-Bit lAP Slice, 3-port device with 32-Bit
ALU, 64 X 32 register file, cascadable
funnel shifter, priority encoder, merge
logic and mask generator

Two Am29334s &
One Am29332

1500

2000

Com'l.

a: IDT39C203A

0

t/)
t/)

IDT49C401

w IDT49C401 A

()

0

a: IDT49C402
c..
0

a:

IDT49C402A

()

:il

IDT49C404A

4-Bit Sequencer

Am2909A; CY7C909

236

302

12-Bit Sequencer with 33-Deep Stack

Am2910A; CY7C910

395

495

4-Bit Sequencer

Am2911A; CY7C911

236

302

16-Bit Sequencer with 33-Deep Stack

Am2910; Am29C10;
CY7C910

395

495

16 X 4 Register File Extension

Am29705A

210

275

16 X 4 Register File Extension

Am29707

210

275

IDT39C60
IDT39C60-1
IDT39C60A

16-Bit Cascadable Error Detection
Correction Unit

Am2960,.1,A; N2960;
MC74F2960,.1,A

446

550

w IDT49C460

32-Bit Cascadable Error Detection
Correction Unit

DP8402; 74AS632;
ALS632

500

690

t/)

IDT39C09A
IDT39C09B

a:
w IDT39C10B
()
z IDT39C10C
w
~

0

IDT39C11A

w IDT39C11B
t/)
IDT49C410
IDT49C410A

t/)

w IDT39C705A

u:

..J

IDT39C705B

ci
w

IDT39C707

a: IDT39C707A

()

c

IDT49C460A

IDT49C460B
a:
w IDT39C02A

:I:

I-

0

IDT49C25

Carry Lookahead Generator

Am2902A

30

30

Microcycle Length Controller

Am2925

30

30

1-2

High-Speed CMOS Static RAMs

·
··

.

Extremely fast access times
low power consumption

.

2V data retention battery backup on all low-power
devices

• Three·state outputs

Part Number

'M' type ceramic RAM modules are built with monOlithic
RAMs in lCC packages surface mounted onto multilayered, co-fired ceramic substrates using lOT's highreliability .vapor phase reflow soldering process
'MP' type commercial plastic modules are built using
lOT monolithic RAMs in SMD plastic packages, surface
mounted onto epoxy laminate (FR4) substrates

Max. Speed (ns)
Com'l.
Mil.

Description

Power (typical)
Standby
Oper.
(mW)
(I-IW)

MONOLITHIC

x 1)
x 4)
16K (4K x 4) with separate data inputs and outputs;

IDT6167

16K (16K

15

12

150

10

IDT6168

16K (4K

15

15

225

10

25

20

225

10

25

20

225

10

16K (2K

25

15

160

20

64K (64K

25

15

250

30

IDT71681

outputs track inputs during write mode
IDT71682
IDT6116
IDT7187
IDT100490
IDT7188
IDT6198

16K (4K x 4) with separate data inputs and outputs;
outputs in high impedance state during write mode

x 8)
x 1)
64K (64K x 1) with ECl 100K compatible 1/0
64K (16K x 4)
64K (16K x 4) with output enable (OE) for added

15

320

20

15

300

30

20

15

300

30

system flexibility
IDT7198

64K (16K x 4) output enable (OE) and second chip select
(CS 2 ) for added system flexibility and memory control

20

15

300

30

IDT71981

64K (16K X 4) with separate data inputs and outputs;
outputs track inputs during write mode

20

15

300

30

IDT71982

64K (16K X 4) with separate data inputs and outputs;
outputs in high impedance state during write mode

20

15

300

30

IDT7164

64K (8K X 8)

35

30

IDT7165

64K (8K X 8) with asynchronous clear and high-speed
chip select

35

30

250
250

30

250

30

30

IDT71C65

64K (8K X 8) with CMOS compatible I/O

35

IDT7186

64K (4K X 16)

55

30
45

300

30

IDT71257

256K (256K X 1)

35

25

350

100

IDT71258

256K (64K X 4)

35

25

350

100

IDT61298

256K (64K X 4) with output enable (OE) for added
system flexibility

35

25

350

100

IDT71281

256K (64K X 4) with separate data inputs and outputs;
outputs track inputs during write mode

35

25

350

100

IDT71282

256K (64K X 4) with separate data inputs and outputs;
outputs in high impedance state during write mode

35

25

350

100

IDT71256

256K (32K X 8)

45

35

250

15

IDT71027
IDT71028

1 Megabit (1024 X 1)

55

500

200

1 Megabit (256K X 4)

55

45
45

500

200

IDT71024

1 Megabit (128K X 8)

55

45

500

200

IDT6178

16K (4K X 4) cache-tag with cache address comparator
and asynchronous clear

15

12

300

IDT7174

64K (8K X 8) with cache address comparator,
asynchronous clear and high-speed chip select

45

35

250

IDT71501

64K (64K X 1) synchronous RAM; all inputs and
outputs latched

45

35

385

IDT71502

64K (4K X 16) registered RAM for writable control
store use; has on·board serial load. parity. breakpoint and
trace logic

45

35

350

30

CONTINUED

1-3

II

High-Speed CMOS Static RAMs (continuedj
Part Number

Max. Speed (ns)
Mil.
Com'l.

Description

Power (max.)
Oper.
Standby
(mW)
(mW)

MODULES
IDT7MP564

80K (16K X 5) static RAM module (plastic SIP)

15

550

IDT8MP628

x 16) plastic SIP RAM module
128K (8K x 16) RAM module with monolithic pinout
256K (256K x 1) plastic SIP RAM module
256K (256K x 1) static RAM module (ceramic SIP)
256K (64K x 4) plastic SIP RAM module
256K (32K x 8) RAM module with monolithic pinout
256K (32K x 8) RAM module with monolithic pinout

40

1650

165

40

1650

220

25

1375

330

25

1485

330

25

1705

330

50

40

2090

440

55

45

880

66

IDT8M628
IDT7MP156
IDT7MC156
IDT7MP456
IDT7M856
IDT8M856

128K (8K

50

110

(low-power)

x

IDT8MP656

256K (16K

40

1870

330

IDT8M656

256K (16K x 16) RAM module with monolithic pinout

60

40

1870

440

IDT7M656

256K (16K x 16, 32K x 8, 64K x 4) RAM modulecustomer configurable organization

25

15

7040

85

IDT7M812

512K (64K x 8) RAM module offering maximum
addressable memory required by 8-Bit MPs

35

25

5280

880

IDT7M912

512K (64K x 9) RAM module offering maximum
addressable memory required by 8-Bit MPs

35

25

5940

990

IDT8MP612

512K (32K

x 16) plastic SIP RAM module
x 16) RAM module with monolithic pinout
512K (16K x 32) RAM module with separate 110

40

1650

165

IDT8M612

512K (32K

60

·40

1650

275

30

5940

660

TBD

1348

330

40

1210

440

40

1210

550

40

1925

440

40

1925

495 -

25

10725

1320

IDT7MC4032

16) plastic SIP RAM module

(ceramic dual SIP)
IDT7MC4001

1 Megabit (1 024K
(ceramic SIP)

x 1) static

RAM module

IDT8MP824

1 Megabit (128K x 8) plastic SIP RAM module

IDT8M824

1 Megabit (128K X 8) RAM module with monolithic
pinout

IDT8MP624

1 Megabit (64K

IDT8M624

1 Megabit (64K
pinout

IDT7MB624

1 Megabit (64K x 16, 128K x 8, 256K x 4) plastic RAM
module - customer configurable organization

IDT7M624

1 Megabit (64K x 16, 128Kx 8, 256K x 4) RAM
module - customer configurable organization

35

25

10725

1320

IDT7M4017

2 Megabit (64K

x 32) RAM module
x 8) static RAM module (plastic SIP)
4 Megabit (256K x 16) RAM module
512K (64K x 8) registered static RAM module
1 Megabit (128K x 8) RAM module with registered

60

40

TBD

TBD

IDT7MP4008

4 Megabit (512K

40

2585

380

45

TBD

TBD

25MHz

TBD

TBD

60

45

2640

935

20MHz

25MHz

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

IDT7M4016
IDT7MP6025
IDT7M824

x 16) plastic SIP RAM module
x 16) RAM module with monolithic

60

60

bufferedllatched addresses and 1I0s
IDT7M6001

32K x 20 double buffered RAM module with
registered, multiplexed address

IDT7M6032

16K x 32 high-speed writable control store with SPCTM

IDT7MB6042

8K

x

112 high-speed writable control store with SPCTM

1-4

Higfl·Speed CMOS Dual·Port RAMs
•

High-speed, low-power

• Automatic power-down feature controlled byCE

•

Independent read or write access to any memory
location from either port

• 2V data retention battery back-up on all low-power
devices

•

Each port has separate controls, address and 1/0

•

•

On-chip port arbitration logic

•

Fully asynchronous operation from either port

• TNT and BUSY flags (BUSY only in

Part Number

Dual-port RAM modu~s built with IDT monolithic dualport RAMs in LCC packages, surface mounted to multilayered, co-fired ceramic substrates using IDT's highreliability vapor phase reflow soldering process

IDT7132/7142)

Max. Speed (ns)
Mil.
Com'l.

Description

Power (typical)
Oper.
Standby
(mW)
(mW)

45
45

35
35

325

16K (2K x 8) fastest available speeds in this industry
standard product; now multiple sourced

45

35

325

IDT7142

16K (2K x B) functions as slave with IDT7132 to
provide 16-Bit words or wider; pin compatible with
IDT7132

45

35

325

IDT71321

16K (2K x 8) high-speed dual-port with interrupt output
(MASTER)

45

35

325

IDT71421

16K (2K X 8) functions as slave with IDT71321 to
provide 16-Bit words or wider; pin compatible with
IDT71321

45

35

325

IDT71322

16K (2K X 8) with Semaphore

45

45

500

IDT7133

32K (2K X 16)

70

55

375

IDT7143

32K (2K X 16) functions as slave with IDT7133 to
provide 32-Bit words or wider

70

55

375

IDT7134

32K (4K X 8) high-speed operation in system where
on-chip arbitration is not needed

45

45

500

45
60

IDT7130

8K (1 K x 8) replaces Synertek SY2130

IDT7140

8K (1 K x 8) functions as slave with IDT7130 to provide
16-Bit words or wider; pin compatible with IDT7130

IDT7132

IDT71342

32K (4K X 8) with Semaphore

IDT7M134

64K (8K X 8) dual-port RAM module

IDT7M144

64K (8K X 8) functions as slave with IDT7M134 to
provide 16-Bit words or wider; pin compatible with
IDT7M134

IDT7M135

128K (16K X 8) dual-port RAM module

IDT7M145

128K (16K X 8) functions as slave with IDT7M135 to
provide 16-Bit words or wider; pin compatible with
IDT7M135

IDT7M137

256K (32K X 8) dual-port RAM module where on-chip
arbitration is not needed

1-5

325

45

500
950

20

60

45
45

950

20

60
60

45
45

1600

50

1600

50

60

55

1800

60

High-Speed CMOS FIFOs
•

Extremely fast access and cycle times

•

Master/slave multiprocessing applications

•

Low power consumption

•

Bidirectional and rate buffer applications

• Asynchronous and simultaneous read and write

• Auto retransmit capability - IDT7200 family

•

•

Fully expandable in depth and width

• Single read and write line operation - IDT7200 family
•

Empty, Full and Half-Full status flags - IDT7200 family

FIFO modules are built with lOT monolithic FIFOs in LCC
packages, surface mounted to a multilayer, co-fired
ceramic substrate using lOT's high-reliability vapor phase
reflow soldering process

• Six pin-compatible versions of varying depth - IDT7200
family

Part Number

Max. Speed (ns)
Mil.
Com'l.

Description

1DT72400 FIFO FAMILY
IDT72401
64 x 4, replaces MMI 67401 at 1/4 power
IDT72402
64 X 5, replaces MMI 67402 at 1/4 power
IDT72403
64 x 4, replaces MMI 67401 at 1/4 power, with
output enable
IDT72404
64 x 5, replaces MMI 67402 at 1/4 power, with
output enable
IDT72413
64 x 5, replaces MMI 67413 at 1/4 power, with
output enable, Half-Full and Almost-Full/Empty flags
1DT7200 FIFO FAMILY
IDT7200
256 x 9, 28-pin 300mil DIP
IDT7201A
512 x 9, replaces Mostek MK4501, with Half-Full
Flag
IDT7202A
1K x 9, with Half-Full Flag
IDT72021
1K x 9, with Half-Full and Almost-Full/Empty flags
and output enable
IDT7203
2K x 9, with Half-Full Flag
IDT7204
4K x 9, with Half-Full Flag, largest monolithic FIFO
available
IDT72041
4K x 9, with Half-Full and Almost-Full/Empty flags
and output enable
IDT7200 FIFO MODULE FAMILY
IDT7M203
2K x 9 FIFO module using four IDT7201s
IDT7M204
4K x 9 FIFO module using four IDT7202s
IDT7M205
8K x 9 FIFO module using four IDT7203s
IDT7M206
16K x 9 FIFO module using four IDT7204s
IDT72100 SERIAL FIFO FAMILY
IDT72103
2K x 9 parallel-serial input/output with FlexishiftTM,
40MHz serial rate
IDT72104
4K x 9 parallel-serial input/output with FlexishiftTM,
40MHz serial rate
IDT7250 BIDIRECTIONAL FIFO FAMILY
IDT7252
1K x 18 - 2K x 9 BiFIFOTM 48-pin DIP

Max. Power (mW)
Mil.
Com'l.

35MHz
35M Hz
35MHz

45MHz
45MHz
45MHz

250

195

250
250

195

35MHz

45MHz

250

1"95

35M Hz

45MHz

385

330

30

25
25

700

625

30

700

625

40

35

700

625

30

25

700

625

50

50

750

600

50

50

750

600

40

35

900

700

50

40

750

600

50

40

750

600

60

50

60

50

50

50

750

600

50

50

750

600

50

50

750

600

195

High-Speed CMOS DSP Building Blocks
•
•

• Supports integer formats

High speed, low power
Highly integrated LSI building blocks

•

Inputs and outputs directly TIL-compatible

• Very fast 50MHz components

Part Number

Description

Max. Speed (ns)
Com'l.
Mil.

Max. Power (mW)
Mil.
Com'l.

IDT7320

16-Bit Eight-level deep pipeline register

15

10

400

IDT7381

16-Bit Cascadable DSP ALU

35

30

400

300

IDT7383

16-Bit Cascadable DSP ALU

25

20

400

300

1-6

300

High-Speed CMOS Parallel Multiplier-Accumulators
•

High speed, low power

•

•

Parallel multiplier-accumulators with selectable
accumulation, rounding and pre loading

• All devices perform subtraction and double precision
addition and multiplication

Preload function allows output register to be preset

•

Extended product output for multiple accumulations

•

Inputs and outputs directly TIL-compatible

Max. Speed (ns)
Com'l.
Mil.

Max. Power (mW)
Mil.
Com'l.

12 x 12-Bit-pin and functionally compatible with
TRW TDC1009J

55

45

1000

750

IDT7210

16 x 16-Bit-with 35-Bit output; pin and functionally
compatible with TRW TDC1010J

40

35

1450

1250

IDT7243

16 x 16-Bit-with 19-Bit output; pin and functionally
compatible with TRW TDC1043

55

45

790

690

Part Number

Description

IDT7209

High-Speed CMOS Parallel Multipliers
•

Round control for rounding the MSP

• Configured for easy array expansion

•

Inputs and outputs directly TIL-compatible

•

• Three-state output controls and separate register enables

•

High speed, low power

User-controlled option for transparent output register
mode

Max. Speed (ns)
Mil.
Com'l.

Part Number

Description

IDT7212

12 x 12-Bit-pin ~nd functionally compatible with
TRW MPY012H

40

35

Max. Power (mW)
Mil.
Com'l.
875

685

IDT7213

12 x 12-Bit-with single clock architecture

40

35

875

685

IDT7216

16 x 16-Bit-pin and functionally compatible with
TRW MPY016H/K and AMD Am29516

25

20

1400

1200

IDT7217

16 x 16-Bit-with single clock architecture; pin and
functionally compatible with AMD Am29517

30

25

1400

1200

IDT7317

16 x 16-Bit-with single clock, 32-Bit output

25

20

1400

1200

.J::Ii.gMp-eeci CMOS Floating-Point Products

.

•

Full 32-Bit and 64-Bit multiply and ALU operations

• Advanced CEMOS technology

•

Pipelined and flow-through modes

•

•

144-Pin Grid Array

•

Full MIL-STD-883 compliant product available

•

High speed, low power - 500mW typical

Full IEEE standard 754 conformance

• Single 5V supply

Max. Speed (MFLOP)
Com'l.
Mil.

_

Max. Power (mW)
Com'l.
Mil.

Part Number

Description

IDT721264

32-/64-Bit Multiplier-pin and functionally
compatible with Weitek WTL 1264

12.5 (32-Sit)
6.2 (64-Sit)

16.7 (32-Bit)
8.3 (64-Bit)

750

625

IDT721265

32-/64-Bit ALU-pin and functionally
compatible with Weitek WTL 1265

12.5 (32-Bit)
12.5 (64-Sit)

16.7 (32-Sit)
16.7 (64-Bit)

750

625

1-7

High-Speed CMOS Data Conversion Products
•

High speed - low power

FLASH AID CONVERTERS

•

Available in military and commercial temperature ranges

•

•

Produced with advanced CEMOS high-performance
technology

IDT75C48 is pin and function compatible with TRW 1048
with half the power consumption, on-chip Error Detection
and Correction, extended analog input range and
improved output characteristics

•

IDT75C58 has enhanced features such as overflow
output and three-state control which allows stacking two
devices for 9-Bit resolution

•

IDT75M48 is a complete Flash ADC module product
with input buffer amplifier. reference voltage generator
and optimized layout and decoupling

VIDEO DACs
•

IDT75C18 is pin and function compatible with TRW 1018
with half the power consumption

•

IDT75C19 is world's first CMOS 9-Bit Video DAC

•

IDT75C458 PaletteDAC™ is pin and function compatible
with Brooktree BT458

•

IDT75MB38 is a triple 8-Bit, 125MHz module with
onboard voltage reference

Description

Replaces

Power
(mW)

IDT75C18

8-Bit, 125MHz Video DAC with ECl inputs

TDC1018

400

IDT75C19

World's first 9-Bit, 125MHz Video DAC

IDT75MB38

Triple 8-Bit, 125MHz Video DAC Module

BT109, TDC1318

1500

BT458

1000

TDC1048

500

Part Number

o

<
c

• IDT75M49 is a complete 9-Bit ADC module using two
IDT75C58 devices

400

IDT75C458

Triple 8-Bit, 125MHz PaletteDAC™

IDT75C48

8-Bit, 20MHz Flash ADC

o

IDT75C58

8-Bit, 20MHz Flash ADC with Overflow output

500

<

IDT75M48

Complete 8-Bit, 20MHz Flash Module using IDT75C48

800

IDT75M49

9-Bit, 20M Hz Flash Module using two IDT75C58s

c

1200

High-Speed CMOS £2 PROMs
•

Fast access times

• On-chip timer, latches, charge pump

•

Internal address and data input latches

•

•

Minimum endurance of 10,000 write cycles per byte

• 5 volt operation

•

Endurance failure rate

< 0.1 %

per 1,000 cycles

•

Write protection circuitry, VCC lockout for VCC = 4V

DATA polling

• Serial access versions with SPCTM (IDT78C18A,
IDT78C68A,IDT78C258A)

Max_ Speed (ns)
Com'l.
Mil.

Power (typical)
Oper.
Standby
(mW)
(mW)

Part Number

Description

IDT78C16A

2Kx 8 E2PROM

90

70

600

IDT78C18A

2K x 8 E2PROM with Serial Protocol Channel (SPC™)

90

70

600

4.5

IDT78M64

8K x 8 E2PROM module with JEDEC E2PROM pinout

85

70

1250

20

IDT78C64A

8K x 8 E2PROM

70

55

500

4.5

IDT78C464A

8K x 8 Registered E2PROM

70

55

500

4.5

IDT78C564A

8K x 8 Registered E2PROM with Serial Protocol
Channel (SPC™)

70

55

500

4.5

4.5

IDT78C256A

32K x 8 E2PROM

70

55

500

4.5

IDT78C4256A

32K x 8 Registered E2PROM

70

55

500

4.5

IDT78C5256A

32K x 8 Registered E2PROM with Serial Protocol
Channel (SPC™)

70

55

500

4.5

1-8

High-Speed CMOS Logic Products

·
·
·
·

·
·
···

FCTXXXA devices 35%-50% faster than FAST™ with
equivalent output drive but at dramatically lower CMOS
power over full temperature and voltage supply extremes
FCT devices same speed and output drive as FAST™,
but at dramatically lower CMOS power

54/74FCT8XXA devices same speed and output drive as
29800, but at dramatically lower CMOS power
54/74FCT8XXB devices 32 % -38 % faster than 29800
with equivalent output drive, but at dramatically lower
CMOS power

Both CMOS and TIL output compatible (eliminates need
for pull-up resistors when driving CMOS static RAMs)
Substantially lower input current levels than FASTTM or
ALS (5j.lA max.)
JEDEC standard pinout for DIP and LCC
Pin-compatible with industry standard MSI logic
Devices formerly designated 39CXXX are now designated

54/74FCT8XXA or 29FCTXXX

Power (typical)
Oper.
Standby
(JAW)
(mW)

Part Number

Description

Max. Speed (ns)
Mil.
Com'l.

I DT29FCT52A

Octal Registered Transceiver

11.0

10.0

10.0

I DT29FCT53A

Octal Registered Transceiver

11.0

10.0

10.0

5.0

IDT29FCT52B

Octal Registered Transceiver

7.2

6.5

10.0

5.0

5.0

IDT29FCT53B

Octal Registered Transceiver

7.2

6.5

10.0

5.0

I DT29FCT520A

Multilevel Pipeline Register

16.0

14.0

10.0

5.0

I DT29FCT521 A

Multilevel Pipeline Register

16.0

14.0

IDT49FCT601

16-Bit Bidirectional Latch w/Byte-Swap

IDT49FCT618

16-Bit Register with SPCTM

IDT49FCT661

16-Bit Synchronous Binary Counter

IDT49FCT818A

Octal Register with SPCTM

11.0

10.0

10.0

5.0

IDT54/74FCT138A

1-of-8 Decoder

7.8

5.8

10.0

5.0

IDT54/74FCT139A

Dual 1-of-4 Decoder

7.8

5.9

10.0

5.0

IDT54/74FCT161A

Synchronous Binary Counter

7.5

7.2

10.0

5.0
5.0

14.0

12.5

10.0

5.0

20.0

10.0

20.0

5.0

20.0

10.0

IDT54/74FCT163A

Synchronous Binary Counter

7.5

7.2

10.0

I DT54/7 4FCT182A

Carry Lookahead Generator

10.7

6.5

10.0

5.0

IDT54/74FCT191A

Up/Down Binary Counter

10.5

7.8

10.0

5.0

IDT54/74FCT193A

Up/Down Binary Counter

6.9

6.5

10.0

5.0

I DT54/7 4 FCT240A

Octal Buffer

5.1

4.8

10.0

5.0

IDT54/74FCT241A

Octal Buffer

4.8

4.5

10.0

5.0

IDT54/74FCT244A

Octal Buffer

4.8

4.5

10.0

5.0

IDT54/74FCT245A

Octal Bidirectional Transceiver

4.9

4.6

10.0

5.0
5.0

IDT54/74FCT273A

Octal D Flip-Flop

8.3

7.2

10.0

IDT54/74FCT299A

Octal Universal Shift Register

9.5

7.2

10.0

5.0

I DT54/7 4 FCT373A

Octal Transparent Latch

5.6

5.2

10.0

5.0

IDT54/7 4 FCT37 4A

Octal D Flip-Flop

7.2

6.5

10.0

5.0

IDT54/74FCT377A

Octal D Flip-Flop

8.3

7.2

10.0

5.0

IDT54/74FCT399A

Quad Dual-Port Register

7.5

7.0

10.0

5.0

IDT54/74FCT521A

8-Bit Comparator

9.5

7.2

10.0

5.0

IDT54/74FCT533A

Octal Transparent Latch

5.6

5.2

10.0

5.0

I DT54/7 4 FCT534A

Octal D Flip-Flop

7.2

6.5

10.0

5.0

IDT54/74FCT540A

Octal Inverting Buffer

10.0

5.0

IDT54/74FCT541A

Octal Non-inverting Buffer

10.0

5.0

I DT54/7 4 FCT543A

Octal Non-inverting Latched Transceiver

7.7

6.3

10.0

5.0

IDT54/74FCT573A

Octal Transparent Latch

5.6

5.2

10.0

5.0

IDT54/74FCT574A

Octal D Register

7.2

6.5

10.0

5.0
CONTINUED

1-9

High-Speed CMOS Logic Products (continued)
Part Number

Description

Max. Speed (ns)
Mil.
Com'l.

Power (typical)
Oper.
Standby
(mW)
(JlW)

IDT54/74FCT640A

Octal Bidirectional Transceiver

5.3

. 5.0

10.0

I DT54/74FCT645A

Octal Bidirectional Transceiver

4.9

4.6

10.0

5.0

I DT54/7 4FCT646A

Octal Non-inverting Registered Transceiver

7.7

6.3

10.0

5.0

6.3

5.6

5.0

IDT54/74FCT648A

Octal Inverting Registered Transceiver

10.0

5.0

I DT54/74FCT651 A

Octal Non-inverting Registered Transceiver

10.0

5.0

I DT54/7 4FCT652A

Octal Inverting Registered Transceiver

10.0

5.0

IDT54/74FCT821A

10-Bit Non-inverting Register

12.0

12.0

10.0

5.0

I DT54/7 4FCT822A

10-Bit Inverting Register

12.0

12.0

10.0

5.0

IDT54/74FCT823A

9-Bit Non-inverting Register

12.0

12.0

10.0

5.0

IDT54/74FCT824A

9-Bit Inverting Register

12.0

12.0

10.0

5.0

IDT54/74FCT825A

8-Bit Non·inverting Register

12.0

12.0

10.0

5.0

IDT54/74FCT826A

8-Bit Inverting Register

12.0

12.0

10.0

5.0

IDT54/74FCT827A

10-Bit Non-inverting Buffer

10.0

8.0

10.0

5.. 0

IDT54/74FCT828A

10-Bit Inverting Buffer

9.5

7.5

10.0

5.0

IDT54/74FCT833A

8-Bit Transceiver w/Parity

14.0

10.0

10.0

5.0

I DT54/7 4FCT834A

8-Bit Transceiver w/Parity

14.0

10.0

10.0

5.0

IDT54/74FCT841 A

10-Bit Non-inverting Latch

11.0

9.5

10.0

5.0

IDT54/74FCT842A

10-Bit Inverting Latch

12.0

10.0

10.0

5.0

I DT54/74FCT843A

9-Bit Non-inverting Latch

11.0

9.5

10.0

5.0

I DT54/7 4FCT844A

9-Bit Inverting Latch

12.0

10.0

10.0

5.0

I DT54/7 4FCT845A

8-Bit Non;inverting Latch

11.0

9.5

10.0

5.0

IDT54/74FCT846A

8-Bit Inverting Latch

12.0

10.0

10.0

5.0

IDT54/74FCT863A

8-Bit Transceiver w/Parity

14.0

10.0

10.0

5.0

IDT54/74FCT854A

8-Bit Transceiver w/Parity

14.0

10.0

10.0

5.0

IDT54/74FCT861A

10-Bit Non-inverting Transceiver

10.0

8.0

10.0

5.0

IDT54/74FCT862A

10-Bit Inverting Transceiver

9.5

7.5

10.0

5.0

10.0

8.0

10.0

5.0

9.5

8.5

10.0

5.0

12.0

9.0

10.0

5.0

IDT54/74FCT863A

9-Bit Non-inverting Transceiver

I DT54/7 4FCT864A

9-Bit Inverting Transceiver

IDT54/74FCT138

1-of-8 Decoder

I DT54/7 4FCT139

Dual 1-of-4 Decoder

12.0

9.0

10.0

5.0

IDT54/74FCT161

Synchronous Binary Counter

11.5

11.0

10.0

5.0

IDT54/74FCT163

Synchronous Binary Counter

11.5

11.0

10.0

5.0

IDT54/74FCT182

Carry Lookahead Generator

16.5

10.0

10.0

5.0

IDT54/74FCT191

Up/Down Binary Counter

16.0

12.0

10.0

5.0

IDT54/74FCT193

Up/Down Binary Counter

10.5

10.0

10.0

5.0

IDT54/74FCT240

Octal Buffer

9.0

8.0

10.0

5.0

IDT54/74FCT241

Octal Buffer

7.0

6.5

10.0

5.0

IDT54/7 4FCT244

Octal Buffer

7.0

6.5

10.0

5.0

IDT54/74FCT245

Octal Bidirectional Transceiver

7.5

7.0

·10.0

5.0

IDT54/7 4FCT273

Octal D Flip-Flop

15.0

13.0

10.0

5.0

IDT54/74FCT299

Octal Universal Shift Register

14.0

10.0

10.0

5.0

IDT54/7 4FCT373

Octal Transparent Latch

8.5

8.0

10.0

5.0

IDT54i74FCT374

Octal D Flip-Flop

11.0

10.0

10.0

5.0
CONTINUED

1-10

._-----_ .. - - - -

High-Speed CMOS L.ogic Products (continued}
Max. Speed (ns)
Mil.
Com'l.

Power (typical)
Oper.
Standby
(mW)
(J.iW)

Part Number

Description

IDT54/74FCT377

Octal 0 Flip-Flop

15.0

13.0

10.0

5.0

I DT54/74 FCT399

Quad Dual-Port Register

11.5

10.0

10.0

5.0

IDT54/74FCT521

8-Bit Comparator

15.0

11.0

10.0

5.0

I DT54/7 4FCT533

Octal Transparent Latch

12.0

10.0

10.0

5.0

IDT54/74FCT534

Octal 0 Flip-Flop

11.0

10.0

10.0

5.0

IDT54/74FCT540

Octal Inverting Buffer

9.0

8.0

10.0

5.0

IDT54/74FCT541

Octal Non-inverting Buffer

9.0

8.0

10.0

5.0

IDT54/74FCT543

Octal Non-inverting Latched Transceiver

10.0

8.5

10.0

5.0

IDT54/74FCT573

Octal Transparent Latch

5.0

I DT54/7 4 FCT57 4

Octal D Register

IDT54/74FCT640

8.5

8.0

10.0

11.0

10.0

10.0

5.0

Octal Bidirectional Transceiver

8.0

7.0

10.0

5.0

I DT54/7 4 FCT645

Octal f;3idirectional Transceiver

11.0

9,5

10.0

5.0

IDT54/74FCT646

Octal Non-inverting Registered Transceiver

11.0

9.0

10.0

5.0

I DT54/7 4FCT648

Octal Inverting Registered Transceiver

9.0

8.0

10.0

5.0

I DT54/7 4FCT651

Octal Non-inverting Registered Transceiver

10.0

9.0

10.0

5.0

I DT54/74 FCT652

Octal Inverting Registered Transceiver

9.0

8.0

10.0

5.0

IDT54/74FCT827

10-Bit Non-inverting Buffer

IDT54/74FCT828

10-Bit Inverting Buffer

IDT54/74FCT821 B

10-Bit Non-inverting Register

8.5

7.5

10.0

5.0

I DT54/7 4FCT822B

10-Bit Inverting Register

8.5

7.5

10.0

5.0

I DT54/7 4FCT823B

9-Bit Non-inverting Register

8.5

7.5

10.0

5.0

I DT54/7 4FCT824B

9-Bit Inverting Register

8.5

7.5

10.0

5.0

I DT54/7 4FCT825B

8-Bit Non-inverting Register

8.5

7.5

10.0

5.0

I DT54/7 4FCT826B

8-Bit Inverting Register

8.5

7.5

10.0

5.0

I DT54/7 4FCT827B

10-Bit Non-inverting Buffer

6.5

5.0

10.0

5.0

I DT54/7 4FCT828B

10-Bit Inverting Buffer

6.5

5.5

10.0

5.0

I DT54/7 4FCT833B

8-Bit Transceiver w/Parity

10.0

7.0

10.0

5.0

IDT54/74FCT834B

8-Bit Transceiver w/Parity

10.0

7.0

10.0

5.0

IDT54/74FCT841 B

10-Bit Non-inverting Latch

7.5

6.5

10.0

5.0

I DT54/7 4FCT842B

10-Bit Inverting Latch

9.0

8_0

10.0

5.0

IDT54/74FCT843B

9-Bit Non-inverting Latch

7.5

6.5

10.0

5.0

IDT54/74FCT844B

9-Bit Inverting Latch

9.0

8.0

10.0

5.0

IDT54/74FCT845B

8-Bit Non-inverting Latch

7.5

6.5

10.0

5.0

I DT54/7 4FCT846B

8-Bit Inverting Latch

9.0

8_0

10.0

5.0

IDT54/74FCT853B

8-Bit Transceiver w/Parity

10.0

7.0

10.0

5.0

IDT54/74FCT854B

8-Bit Transceiver w/Parity

10.0

7.0

10.0

5.0

IDT54/74FCT861 B

10-Bit Non-inverting Transceiver

6.5

6.0

10.0

5.0

IDT54/74FCT862B

10-Bit Inverting Transceiver

6.5

5.5

10.0

5.0

I DT54/74 FCT863B

9-Bit Non-inverting Transceiver

6.5

6.0

10.0

5.0

IDT541-74FCT864B

9-Bit Inverting Transceiver

6.5

5.5

10.0

5.0
5.0

IDT54AHCT138

1-of-8 Decoder

27.0

3.5

IDT54AHCT139

Dual 1-of-4 Decoder

25.0

3.5

5.0
CONTINUED

1-11

High-Speed CMOS l.ogic Products (continued)'

.

Power (typical)
Oper.
Standby
(mW)
(JlW)

Part Number

Description

Max. Speed (ns)
Mil.
Com'!.

IDT54AHCT161

Synchronous Binary Counter

20.0

3.5

5.0

IDT54AHCT163

Synchronous Binary Counter

20.0

3.5

5.0

IDT54AHCT182

Carry Lookahead Generator

20.5

3.5

5.0

IDT54AHCT191

Up/Down Binary Counter

22.0

3.5

5.0

I DT54AHCT193

UplDown Binary Counter

19.0

3.5

5.0

IDT54AHCT240

Octal Buffer

12.0

3.5

5.0

IDT54AHCT244

Octal Buffer

13.0

3.5

5.0

IDT54AHCT245

Octal Bidirectional Transceiver

15.0

3.5

5.0

IDT54AHCT273

Octal D Flip·Flop

17.0

3.5

5.0

IDT54AHCT299

Universal Shift Register

17.0

3.5

5.0

IDT54AHCT373

Octal Transparent Latch

19.0

3.5

5.0

IDT54AHCT374

Octal D Flip·Flop

18.0

3.5

5.0

IDT54AHCT377

Octal D Flip·Flop

20.0

3.5

5.0

IDT54AHCT521

8·Bit Comparator

17.0

3.5

5.0

IDT54AHCT533

Octal Transparent Latch

24.0

3.5

5.0

IDT54AHCT534

Octal D Flip·Flop

18.0

3.5

5.0

IDT54AHCT573

Octal Transparent Latch

15.0

3.5

5.0

IDT54AHCT574

Octal D Register

15.0

3.5

5.0

IDT54AHCT640

Octal Bidirectional Transceiver

14.0

3.5

5.0

IDT54AHCT645

Octal Bidirectional Transceiver

15.0

3.5

5.0

1-12

AMD

lOT

AMD CONT.

lOT

AMD CONT.

lOT

AM2167-3SDC
AM2168-SSPCB
AM99C641-2SDC
AM2167 -3SDCB
AM2168-70/BRA
AM99C641-2SDCB
AM2167 -3SLC
AM2168-70/BUC
AM99C641-2SLC
AM2167 -3SLCB
AM2168-70DE
AM99C641-2SLCB
AM2167-3SPC
AM2168-70DEB
AM99C641-2SPC
AM2167 -35PCB
AM2168-70LE
AM99C641-25PCB
AM2167-45/BRA
AM2168-70LEB
AM99C641-3SDC
AM2167-4S/BUC
AM99C641-3SDCB
AM2167-4SDC
AM2169-40DC
AM99C641-3SLC
AM2167 -4SDCB
AM2169-40DCB
AM99C641-35LCB
AM2167-45DE
AM2169-40LC
AM99C641-35PC
AM2167-4SDEB
AM2169-40LCB
AM99C641-35PCB
AM2167-45LC
AM2169-40PC
AM99C641-4S/BWA
AM2167 -45PC
AM2169-40PCB
AM99C641-4S/LMC
AM2167-5S/BRA
AM2169-50/BRA
AM99C641-4SDC
AM2167-55/BUC
AM2169-50DC
AM99C641-45DCB
AM2167-55DC
AM2169-S0DCB
AM99C641-4SDE
AM2167-SSDE
AM2169-S0DE
AM99C641-45DEB
AM2167 -5SDEB
AM2169-50DEB
AM99C641-45LC
AM2167-SSLC
AM2169-S0LE

IDT6167SA3SD
IDT6168SA55P
IDT7187L2SC
IDT6167SA3SD
IDT6168SA70DB
IDT7187L2SC
IDT6167SA3SL
IDT6168SA70LB
IDT7187L2SL22
IDT6167SA3SL
IDT6168SA70DM
IDT7187L2SL22
IDT6167SA35P
IDT6168SA70DM
IDT7187L2SP
IDT6167SA35P
IDT6168SA70LM
IDT7187L25P
IDT6167SA45DB
IDT6168SA70LM
IDT7187L3SC
IDT6167SA4SLB
IDT7187L2SC
IDT6167SA4SD
IDT6169SA3SD
IDT7187L3SL22
IDT6167SA4SD
IDT6169SA35D
IDT7187L3SL22
IDT6167SA45DM
IDT6169SA35L
IDT7187L35P
IDT6167SA45DM
IDT6169SA35L
IDT7187L35P
IDT6167SA45L
IDT6169SA35P
IDT7187L45CB
IDT6167SA45P
IDT6169SA35P
IDT7187L4SL22B
IDT6167SA5SDB
IDT6169SA4SDB
IDT7187L4SC
IDT6167SA55LB
IDT6169SA4SD
IDT7187L45C
IDT6167SAS5D
IDT6169SA45D
IDT7187L45CM
IDT6167SASSDM
IDT6169SA45DM
IDT7187L45CM
IDT6167SASSDM
IDT6169SA4SDM
IDT7187L4SL22
IDT6167SA5SL
IDT6169SA4SLM

AM99C641-4SLCB
AM2167-SSPC
AM2169-50LEB
AM99C641-4SLE
AM2167 -70/BRA
AM2169-S0PC
AM99C641-4SLEB
AM2167-70/BUC
AM2169-S0PCB
AM99C641-4SPC
AM2167-70DC
AM2169-70/BRA
AM99C641-45PCB
AM2167-70DCB
AM2169-70DE
AM99C641-SS/BWA
AM2167-70DE
AM2169-70DEB
AM99C641-S5/LMC
AM2167-70DEB
AM2169-70LE
AM99C641-SSDC
AM2167 -70LC
AM2169-70LEB
AM99C641-SSDCB
AM2167 -70PC
AM99C641-SSDE
AM2167-70PCB
AM9128-12/BJA
AM99C641-S5DEB
AM9128-12/BUC
AM99C641-S5LC
AM2168-35DC
AM9128-1S/BJA
AM99C641-55LCB
AM2168-35DCB
AM9128-1S/BUC
AM99C641-SSLE
AM2168-35LC
AM9128-70DC
AM99C641-55LEB
AM2168-3SLCB
AM9128-70DCB
AM99C641-SSPC
AM2168-35PC
AM9128-70DE
AM99C641-55PCB
AM2168-3SPCB
AM9128-70DEB
AM99C641-70/BWA
AM2168-4S/BRA
AM9128-70LC
AM99C641-70/LMC
AM2168-45/BUC
AM9128-70LCB
AM99C641-70DC
AM2168-4SDC
AM9128-70PC
AM99C641-70DCB
AM2168-4SDCB
AM9128-90/BJA
AM99C641-70DE
AM2168-4SDE

IDT7187L4SL22
IDT6167SASSP
IDT6169SA4SLM
IDT7187L4SL22M
IDT6167SA70DB
IDT6169SA4SP
IDT7187L4SL22M
IDT6167SA70LB
IDT6169SA4SP
IDT7187L4SP
IDT6167SA70D
IDT6169SA55DB
IDT7187L45P
IDT6167SA70D
IDT6169SA5SDM
IDT7187LSSCB
IDT6167SA70DM
IDT6169SASSDM
IDT7187L55L22B
IDT6167SA70DM
IDT6169SASSLM
IDT7187LSSC
IDT6167SA70L
IDT6169SASSLM
IDT7187L5SC
IDT6167SA70P
IDT7187LSSCM
IDT6167SA70P
IDT6116SA120DB
IDT7187L55CM
IDT6116SA120L32B
IDT7187L55L22
IDT6168SA35D
IDT6116SA150D[3
IDT7187L55L22
IDT6168SA35D
IDT6116SA1S0L32B
IDT7187LSSL22M
IDT6168SA35L
IDT6116SA70D
IDT7187L55L22M
IDT6168SA3SL
IDT6116SA70D
IDT7187L55P
IDT6168SA35P
IDT6116SA70DM
IDT7187LS5P
IDT6168SA3SP
IDT6116SA70DM
IDT7187L70CB
IDT6168SA45DB
IDT6116SA70L32
IDT7187L70L22B
IDT6168SA4SLB
IDT6116SA70L32
IDT7187L70C
IDT6168SA4SD
IDT6116SA70P
IDT7187L70C
IDT6168SA4SD
IDT6116SA90DB
IDT7187L70CM
IDT6168SA4SDM

AM9128-90/BUC
AM99C641-70DEB
AM2168-4SDEB
AM99C641-70LC
AM2168-4SLE
AM99C164-3Sx
AM99C641-70LCB
AM2168-4SLEB
AM99C164-4Sx
AM99C641-70LE
AM2168-4SPC
AM99C164-55x
AM99C641-70LEB
AM2168-45PCB
AM99C164-70x
AM99C641-70PC
AM2168-55/BRA
AM99C641-70PCB
AM2168-55/BUC
AM99C16S-3Sx
AM2168-SSDC
AM99C16S-4Sx
AM99C68-4S/BRA
AM2168-SSDCB
AM99C16S-SSx
AM99C68-4SDC
AM2168-S5DE
AM99C16S-70x
AM99C68-45DCB
AM2168-SSDEB
AM99C68-45PC
AM2168-55LE
AM99C328-4Sx
AM99C68-45PCB
AM2168-S5LEB
AM99C328-55x
AM99C68-55/BRA
AM2168-SSPC
AM99C328-70x
AM99C68-55DC
AM99C68-55DCB
AM99C88-12/BXC
AM99CS88-12/BXC
AM99C68-55DMB
AM99C88-15/BUC
AM99CS88-15/BUC
AM99C68-55PC
AM99C88-1S/BXC
AM99CS88-15/BXC
AM99C68-S5PCB
AM99C88-20/BUC
AM99CS88-20/BUC
AM99C68-70/BRA
AM99C88-20/BXC
AM99CS88-20/BXC
AM99C68-70DC
AM99C88-70/BUC
AM99CS88-70/BUC
AM99C68-70DCB
AM99C88-70/BXC
AM99CS88-70/BXC
AM99C68-70DMB
AM99C88-70DC

IDT6116SA90L32B
IDT7187L70CM
IDT6168SA4SDM
IDT7187L70L22
IDT6168SA4SLM
IDT7188L3Sx
IDT7187L70L22
IDT6168SA4SLM
IDT7188L4Sx
IDT7187L70L22M
IDT6168SA4SP
IDT7188L55x
IDT7187L70L22M
IDT6168SA45P
IDT7188L70x
IDT7187L70P
IDT6168SA55DB
IDT7187L70P
IDT6168SA55LB
IDT6198L3Sx
IDT6168SASSD
IDT6198L4Sx
IDT6168LA4SDB
IDT6168SA55D
IDT6198L55x
IDT6168LA45D
IDT6168SAS5DM
IDT6198L70x
IDT6168LA4SD
IDT6168SASSDM
IDT6168LA45P
IDT6168SA55LM
IDT71256L45x
IDT6168LA4SP
IDT6168SASSLM
IDT71256LSSx
IDT6168LA55DB
IDT6168SA55P
IDT71256L70x
IDT6168LASSD
IDT6168LASSD
IDT7164L120DB
IDT7164L120DB
IDT6168LA55DB
IDT7164L150L32B
IDT7164L150L32B
IDT6168LA55P
IDT7164L100DB
IDT7164L1S0DB
IDT6168LAS5P
IDT7164L2ooDB
IDT7164L2ooL32B
IDT6168LA70DB
IDT7164L2ooL32B
IDT7164L2ooDB
IDT6168LA70D
IDT7164L70L32B
IDT7164L70L32B
IDT6168LA70D
IDT7164L70L32B
IDT7164L70DB
IDT6168LA70DB
IDT7164L70D

NOTES:
A lower case • ·x·· indicates the packages of the
AMD part are unknown.·
All AM99 series parts have 2 Volt data retention
capability.

1-13

STATIC RAM CROSS REFERENCE GUIDE

AMO CONT.

IDT

AM99C68-70PC
AM99C88-70DCB
AM99C88H-35x
AM99C68-70PCB
AM99C88-70DE
AM99C88H-45/x
AM99C88-70DEB
AM99CL68-45/BRA
AM99C88-70LC
AM2l30-l0/BUC
AM99CL68-45DC
AM99C88-70LCB
AM2l30-l0/BXC
AM99CL68-45DCB
AM99C88-70LE
AM2l30-10DC
AM99CL68-45PC
AM99C88-70LEB
AM2l30-l0DCB
AM99CL68-45PCB
AM99CL88-l0/BUC
AM2l30-l0JC
AM99CL68-55/BRA
AM99CL88-l0/BXC
AM2l30-10LC
AM99CL68-55DC
AM99CL88-l2/BUC
AM2l30-10LCB
AM99CL68-55DCB
AM99CL88-l2/BXC
AM2l30-10PC
AM99CL68-55PC
AM99CL88-l5/BUC
AM2l30-10PCB
AM99CL68-55PCB
AM99CL88-l5/BXC
AM2l30-12JBUC
AM99CL68-70/BRA
AM99CL88-70/BUC
AM2l30-12/BXC
AM99CL68-70DC
AM99CL88-70/BXC
AM2l30-70/BXC
AM99CL68-70DCB
AM99CL88-70DC
AM2l30-70DC
AM99CL68-70PC
AM99CL88-70DCB
AM2l30-70DCB
AM99CL68-70PCB
AM99CL88-70LC
AM2l30-70JC
AM99CL88-70LCB
AM2l30-70LC
AM99C88-l0/BUC
AM99CS88-l0/BUC
AM2l30-70LCB
AM99C88-l0/BXC
AM99CS88-l0/BXC
AM2l30-70PC
AM99C88-l2/BUC
AM99CS88-l2/BUC
AM2l30-70PCB

IDT6l68LA70P
IDT7l64L70D
IDT7l64L35x
IDT6l68LA70P
IDT7l64L70DM
IDT7l64L45xB
IDT7l64L70DM
IDT6l68LA45DB
IDT7l64L70L32
IDT7l30Sl00L52B*
IDT6l68LA45D
IDT7164L70L32
IDT7l30Sl00CB
IDT6l68LA45D
IDT7l64L70L32M
IDT7l30Sl00C
IDT6l68LA45P
IDT7l64L70L32M
IDT7l30Sl00C
IDT6l68LA45P
IDT7l64L85L32B
IDT7l30Sl00J*
IDT6l68LA55DB
IDT7l64L85DB
IDT7l30Sl00L52*
IDT6l68LA55D
IDT7l64L85L32B
IDT7l30Sl00L52*
IDT6l68LA55D
IDT7l64L85DB
IDT7l30Sl00P
IDT6168LA55P
IDT7l64L85L32B
IDT7l30Sl00P
IDT6l68LA55P
IDT7l64L85DB
IDT7l30Sl20L52B*
IDT6l68LA70DB
IDT7l64L70L32B
IDT7l30Sl20CB
IDT6l68LA70D
IDT7l64L70DB
IDT7l30S70CB
IDT6l68LA70D
IDT7l64L70D
IDT7l30S70C
IDT6l68LA70P
IDT7l64L70D
IDT7l30S70C
IDT6l68LA70P
IDT7l64L70L32
IDT7l30S70J*
IDT7l64L70L32
IDT7l30S70L52*
IDT7l64L1OOL32B
IDT7l64L1OOL32B
IDT7l30S70L52*
IDT7l64Ll00DB
IDT7l64Ll00DB
IDT7l30S70P
IDT7l64L l20L32B
IDT7l64Ll20L32B
IDT7l30S70P

NOTES:
A lower case ·x" indicates the packages of the
AMD part are unknown.
All AM99 series parts have 2 Volt data retention
capability.
An asterisk "*" indicates the IDT part is NOT pin
for pin compatible.

LATTICE
SR16K4-25P
SR16K8-40R
SR64Kl-45PB
SR16K4-25PB
SR16K8-40RB
SR64Kl-45R
SR16K4-30C
SR16K8-40RM
SR64Kl-45RB
SR16K4-30CB
SR16K8-40RMB
SR64K1-45RM
SR16K4-30CM
SR16K8-40C
SR64Kl-45RMB
SR16K4-30CMB
SR16K8-45CB
SR64Kl-55C
SR16K4-30P
SR16K8-45CM
SR64Kl-55CB
SR16K4-30PB
SR16K8-45CMB
SR64Kl-55CM
SR16K4-30R
SR16K8-45P
SR64Kl-55CMB
SR16K4-30RB
SR16K8-45PB
SR64Kl-55P
SR16K4-30RM
SR16K8-45R
SR64Kl-55PB
SR16K4-30RMB
SR16K8-45RB
SR64Kl-55R
SR16K4-35C
SR16K8-45RM
SR64Kl-55RB
SR16K4-35CB
SR16K8-45RMB
SR64Kl-55RM
SR16K4-35CM
SR64Kl-55RMB
SR16K4-35CMB
SR256Kl-x
SR16K4-35P
SR64K4-35P
SR16K4-35PB
SR256K4-x
SR64K4-35PB
SR16K4-35R
SR64K4-40C
SR16K4-35RB
SR256K8-x
SR64K4-40CB
SR16K4-35RM
SR64K4-40CM
SR16K4-35RMB
SR64E4-35P
SR64K4-40CMB
SR16K4-40C
SR64E4-35P
SR64K4-40P
SR16K4-40CB
SR64E4-40C
SR64K4-40PB
SR16K4-40CM
SR64E4-40CB
SR64K4-40R
SR16K4-40CMB
SR64E4-40CM
SR64K4-40RMB
SR16K4-40P
SR64E4-40CMB

IDT

LATTICE CONT.

lOT

IDT6l68SA25P
IDT6ll6SA35L
IDT7l87S45P
IDT6l68SA25P
IDT6ll6SA35L
IDT7l87S45L
IDT6l68SA25D
IDT6ll6SA35LB
IDT7l87S45L
IDT6l68SA25D
IDT6ll6SA35LB
IDT7187S45LB
IDT6l68SA25DB
IDT6ll6SA35D
IDT7l87S45LB
IDT6l68SA25DB
IDT6ll6SA45D
IDT7l87S55C
IDT6l68SA25P
IDT6ll6SA45DB
IDT7l87S55C
IDT6l68SA25P
IDT6ll6SA45DB
IDT7l87S55CB
IDT6l68SA25L
IDT6ll6SA45P
IDT7l87S55CB
IDT6l68SA25L
IDT6ll6SA45P
IDT7l87S55P
IDT6l68SA25LB
IDT6ll6SA45L
IDT7l87S55P
IDT6l68SA25LB
IDT6ll6SA45L
IDT7l87S55L
IDT6l68SA35D
IDT6ll6SA45LB
IDT7l87S55L
IDT6l68SA35D
IDT6ll6SA45LB
IDT7l87S55LB
IDT6l68SA35DB
IDT7l87S55LB
IDT6168SA35DB
IDT7l257x
IDT6l68SA35P
IDT7l88SA35P
IDT6l68SA35P
IDT7l258x
IDT7l88SA35P
IDT6l68SA35L
IDT7l88SA35C
IDT6l68SA35L
IDT7l256x
IDT7l88SA35C
IDT6l68SA35LB
IDT7l88SA35CB
IDT6l68SA35LB
IDT6l98535P
IDT7l88SA35CB
IDT6l68SA35D
IDT6l98S35P
IDT7l88SA35P
IDT6l68SA35D
IDT6l98S35C
IDT7l885A35P
IDT6l68SA35DB
IDT6l98S35C
IDT7l88SA35L
IDT6l68SA35DB
IDT6l98S35CB
IDT7l88SA35LB
IDT6l68SA35P
IDT6l98S35CB

SR64K4-45CB
SR16K4-40PB
SR64E4-40P
SR64K4-45CM
SR16K4-40R
SR64E4-40P
SR64K4-45CMB
SR16K4-40RB
SR64E4-40R
SR64K4-45P
SR16K4-40RM
SR64E4-40RB
SR64K4-45PB
SR16K4-40RMB
SR64E4-40RM
SR64K4-55C
SR16K4-45C
SR64E4-40RMB
SR64K4-55CB
SR16K4-45CB
SR64E4-45C
SR64K4-55CM
SR16K4-45CM
SR64E4-45CB
SR64K4-55CMB
SR16K4-45CMB
SR64E4-45CM
SR64K4-55P
SR16K4-45P
SR64E4-45CMB
SR64K4-55PB
SR16K4-45PB
SR64E4-45P
SR16K4-45R
SR64E4-45P
SR64K8-35P
SR16K4-45RB
SR64E4-45R
SR64K8-35PB
SR16K4-45RM
SR64E4-45RB
SR64K8-40C
SR16K4-45RMB
SR64E4-45RM
SR64K8-40CB
SR64E4-45RMB
SR64K8-40CM
SR16K8-30C
SR64E4-55C
SR64K8-40CMB
SR16K8-30CB
SR64E4-55CB
SR64K8-40P
SR16K8-30CM
SR64E4-55CM
SR64K8-40PB
SR16K8-30CMB
SR64E4-55CMB
SR64K8-40R
SR16K8-30P
SR64E4-55P
SR64K8-40RB
SR16K8-30PB
SR64E4-55PB
SR64K8-40RM
SR16K8-30R
SR64E4-55R
SR64K8-40RMB
SR16K8-30RB
SR64E4-55RB
SR64K8-45C
SR16K8-30RM
SR64E4-55RM
SR64K8-45CB
SR16K8-30RM B

IDT7l88SA45C
IDTQl68SA35P
IDT6l98S35P
IDT7l88SA45CB
IDT6l68SA35L
IDT6l98S35P
IDT7l88SA45CB
IDT6l68SA35L
IDT6l98S35L
IDT7l88SA45P
IDT6l68SA35LB
IDT6l98S35L
IDT7l88SA45P
IDT6l68SA35LB
IDT6l98S35LB
IDT7l88SA55C
IDT6l68SA45D
IDT6l98S35LB
IDT7l88SA55C
IDT6l68SA45D
IDT6l98S45C
IDT7l88SA55CB
IDT6l68SA45DB
IDT6l98S45C
IDT7l88SA55CB
IDT6l68SA45DB
IDT6l98S45CB
IDT7l88SA55P
IDT6l68SA45P
IDT6l98S45CB
IDT7l88SA55P
IDT6l68SA45P
IDT6l98S45P
IDT6l68SA45L
IDT6l98S45P
IDT7l64S35P
IDT6l68SA45L
IDT6l98S45L
IDT7l64S35P
IDT6l68SA45LB
IDT6l98S45L
IDT7l64S35C
IDT6l68SA45LB
IDT6l98S45LB
IDT7l64S35C
IDT6l98S45LB
IDT7l64S35CB
IDT6ll6SA30D
IDT6l98S55C
IDT7l64S35CB
IDT6ll6SA30D
IDT6l98S55C
IDT7l64S35P
IDT6ll6SA30DB
IDT6l98S55CB
IDT7l64S35P
IDT6l16SA30DB
IDT6l98S55CB
IDT7l64S35L32
IDT6ll6SA30P
IDT6l98S55P
IDT7l64S35L32
IDT6ll6SA30P
IDT6l98555P
IDT7l64S35L32B
IDT6ll6SA30L
IDT6l98S55L
IDT7l64S35L32B
IDT6ll6SA30L
IDT6l98S55L
IDT7l64S45C
IDT6ll6SA30LB
IDT6l98S55LB
IDT7l64S45C
IDT6ll6SA30LB

1-14

STATIC RAM CROSS REFERENCE GUIDE

LATTICE CONT.

IDT

SR64E4-55RMB
SR64K8-45CM
SR16K8-35C
SR64K8-45CMB
SR16K8-35CB
SR64K1-35C
SR64K8-45P
SR16K8-35CM
SR64K1-35CB
SR64K8-45PB
SR16K8-35CMB
SR64K1-35CM
SR64K8-45R
SR16K8-35P
SR64K1-35CMB
SR64K8-45RB
SR16K8-35PB
SR64K1-35P
SR64K8-45RM
SR16K8-35R
SR64K1-35PB
SR64K8-45RMB
SR16K8-35RB
SR64K1-35R
SR64K8-55C
SR16K8-35RM
SR64K1-35RB
SR64K8-55CB
SR16K8-35RMB
SR64K1-35RM
SR64K8-55CM
SR16K8-40C
SR64K1-35RMB
SR64K8-55CMB
SR16K8-40CB
SR64K1-45C
SR64K8-55P
SR16K8-40CM
SR64K1-45CB
SR64K8-55PB
SR16K8-40CMB
SR64K1-45CM
SR64K8-55R
SR16K8-40P
SR64K1-45CMB
SR64K8-55RB
SR16K8-40PB
SR64K1-45P
SR64K8-55RM
SR64K8-55RMB

IDT6198S55LB
IDT7164S45CB
IDT6116SA35D
IDT7164S45CB
IDT6116SA35D
IDT7187S35C
IDT7164S45P
IDT6116SA35DB
IDT7187S35C
IDT7164S45P
IDT6116SA35DB
IDT7187S35CM
IDT7164S45L32
IDT6116SA35P
IDT7187S35CM
IDT7164S45L32
IDT6116SA35P
IDT7187S35P
IDT7164S45L32B
IDT6116SA35L
IDT7187S35P
IDT7164S45L32B
IDT6116SA35L
IDT7187S35L
IDT7164S55C
IDT6116SA35LB
IDT7187S35L
IDT7164S55C
IDT6116SA35LB
IDT7187S35LM
IDT7164S55CB
IDT6116SA35D
IDT7187S35LM
IDT7164S55CB
IDT6116SA35D
IDT7187S45C
IDT7164S55P
IDT6116SA35DB
IDT7187S45C
IDT7164S55P
IDT6116SA35DB
IDT7187S45CM
IDT7164S55L32
IDT6116SA35P
IDT7187S45CM
IDT7164S55L32
IDT6116SA35P
IDT7187S45P
IDT7164S55L32B
IDT7164S55L32B

CYPRESS

lOT

CY7C128-25DC
CY7C161-25DC*
CY7C164L-35DMB
CY7C128-25LC
CY7C161-35DC*
CY7C164L-35LC
CY7C128-25PC
CY7C161-35DMB*
CY7C164L-35LMB
CY7C128-25SC

IDT6116SA25D
IDT71981S25C
IDT7188L35CB
IDT6116SA25L24
IDT71981S35C
IDT7188L35L
IDT6116SA25P
IDT71981 S35CB
IDT7188L35LB
IDT6116SA25S0

NOTES:
A lower case "x" indicates the packages of the
AMD part are unknown.
All AM99 series parts have 2 Volt data retention
capability.
An asterisk "*" indicates the IDT part is NOT pin
for pin compatib,le.

CYPRESS CONT.

IDT

CYPRESS CONT.

lOT

CY7C161-35LC*
CY7C164L -35PC
CY7C128-35DC
CY7C161-35PC*
CY7C164L-45DC
CY7C128-35DMB
CY7C161-45DC*
CY7C164L-45DMB
CY7C128-35LC
CY7C161-45DMB*
CY7C164L-45LC
CY7C128-35LMB
CY7C161-45LC*
CY7C164L-45LMB
CY7C128-35PC
CY7C161-45LMB*
CY7C164L-45PC
CY7C128-35SC
CY7C161 L-25DC*
CY7C128-45DC
CY7C161 L-35DC*
CY7C166-25DC
CY7C128-45DMB
CY7C161L-35DMB*
CY7C166-25PC
CY7C128-45LC
CY7C161 L-35LC*
CY7C166-35DC
CY7C128-45LMB
CY7C161L-35LMB*
CY7C166-35DMB
CY7C128-45PC
CY7C161 L-45DC*
CY7C166-35LC
CY7C128-45SC
CY7C161 L-45DMB*
CY7C166-35LMB
CY7C128-55DC
CY7C161 L-45LC*
CY7C166-35PC
CY7C128-55DMB
CY7C161 L-45LMB*
CY7C166-45DC
CY7C128-55LC
CY7C166-45DMB
CY7C128-55LMB
CY7C162-25DC*
CY7C166-45LC
CY7C128-55PC
CY7C162-35DC*
CY7C166-45LMB
CY7C128-55SC
CY7C162-35DMB*
CY7C166-45PC
CY7C162-35LC*
CY7C166L-25DC
CY7C130-45DC
CY7C162-35LMB*
CY7C166L-25PC
CY7C130-45LC
CY7C162-45DC*
CY7C166L-35DC
CY7C130-45PC
CY7C162-45DMB*
CY7C166L-35DMB
CY7C130-55DC
CY7C162-45LC*
CY7C166L-35LC
CY7C130-55LC
CY7C162-45LMB*
CY7C166L-35LMB
CY7C130':'55PC
CY7C162L-25DC*
CY7C166L-35PC
CY7C162L-35DC*

IDT71981S35L
IDT7188L35P
IDT6116SA35D
IDT71981S35P
IDT7188L45C
IDT6116SA35DB
IDT71981S45C
IDT7188L45CB
IDT6116SA35L24
IDT71981S45CB
IDT7188L35L
IDT6116SA35L24B
IDT71981S45L
IDT7188L45LB
IDT6116SA35P
IDT71981S45LB
IDT7188L45P
IDT6116SA35S0
IDT71981L25C
IDT6116SA45D
IDT71981L35C
IDT6198S25C
IDT6116SA45DB
IDT71981L35CB
IDT6198S25P
IDT6116SA45L24
IDT71981 L35L24
IDT6198S35C
IDT6116SA45L24B
IDT71981 L35L24B
IDT6198S35CB
IDT6116SA45P
IDT7198LS45C
IDT6198S35L
IDT6116SA45S0
IDT71981 L45CB
IDT6198S35LB
IDT6116SA55D
IDT71981 L45L24
IDT6198S35P
IDT6116SA55DB
IDT71981 L45L24B
IDT6198S45C
IDT6116SA55L24
IDT6198S45CB
IDT6116SA55L24B
IDT71982S25C
IDT6198S45L
IDT6116SA55P
IDT71982S35C
IDT6198S45LB
IDT6116SA55S0
IDT71982S35CB
IDT6198S45P
IDT71982S35L
IDT6198L25C
IDT7130S45C
IDT71982S35LB
IDT6198L25P
IDT7130S45L52
IDT71982S45C
IDT6198L35C
IDT7130S45P
IDT71982S45CB
IDT6198L35CB
IDT7130S55C
IDT71982S45L
IDT6198L35L
IDT7130S55L52
IDT71982S45LB
IDT6198L35LB
IDT7130S55P
IDT71982L25C
IDT6198L35P
IDT71982L35C

CY7C166L-45DC
CY7C132-35DC
CY7C162L-35DMB*
CY7C166L-45DMB
CY7C132-35LC
CY7C162L-35LC*
CY7C166L-45LC
CY7C132-35PC
CY7C162L-35LMB*
CY7C166L-45LMB
CY7C132-45DC
CY7C162L-45DC·
CY7C166L-45PC
CY7C132-45LC
CY7C162L-45DMB*
CY7C132-45PC
CY7C162L-45LC*
CY7C167-25PC
CY7C132-55DC
CY7C162L-45LMB*
CY7C167 -25DC
CY7C132-55LC
CY7C167-25LC
CY7C132-55PC
CY7C164-25DC
CY7C167-35PC
CY7C164-25PC
CY7C167-35DC
CY7C140-45DC
CY7C164-35DC
CY7C167 -35LC
CY7C140-45LC
CY7C164-35DMB
CY7C167 -35DMB
CY7C140-45PC
CY7C164-35LC
CY7C167-35LMB
CY7C140-55DC
CY7C164-35LMB
CY7C167 -45PC
CY7C140-55LC
CY7C164-35PC
CY7C167 -45DC
CY7C140-55PC
CY7C164-45DC
CY7C167-45LC
CY7C164-45DMB
CY7C167-45DMB
CY7C142-35DC
CY7C164-45LC
CY7C167-45LMB
CY7C142-35LC
CY7C164-45LMB
CY7C167L-25DC
CY7C142-35PC
CY7C164-45PC
CY7C167L-25LC
CY7C142-45DC
CY7C164L-25DC
CY7C167L-25PC
CY7C142-45LC
CY7C164L-25PC
CY7C167L-35DC
CY7C142-45PC
CY7C164L-35DC
CY7C167L-35LC
CY7C142-55DC
CY7C167L-35PC
CY7C142-55LC
CY7C142-55PC
CY7C168-25DC
CY7C171-45LC
CY7C186-35DC
CY7C168-25LC
CY7C171-45LM B

IDT6198L45C
IDT7132S35C
IDT71982L35CB
IDT6198L45CB
IDT7132S35L52
IDT71982L35L
IDT6198L45L
IDT7132S35P
IDT71982L35LB
IDT6198L45LB
IDT7132S45C
IDT71982L45C
IDT6198L45P
IDT7132S45L52
IDT71982L45CB
IDT7132S45P
IDT71982L45L
IDT6167SA25P
IDT7132S55C
IDT71982L45LB
IDT6167SA25D
IDT7132S55L52
IDT6167SA25L
IDT7132S55P
IDT7188S25C
IDT6167SA35P
IDT7188S25P
IDT6167SA35D
IDT7140S45C
IDT7188S35C
IDT6167SA35L
IDT7140S45L52
IDT7188S35CB
IDT6167SA35DB
IDT7140S45P
IDT7188S35L
IDT6167SA35LB
IDT7140S55C
IDT7188S35LB
IDT6167SA45P
IDT7140S55L52
IDT7188S35P
IDT6167SA45D
IDT7140S55P
IDT7188S45C
IDT6167SA45L
IDT7188S45CB
IDT6167SA45DB
IDT7142S35C
IDT7188S35L
IDT6167SA45LB
IDT7142S35L52
IDT7188S45LB
IDT6167LA25D
IDT7142S35P
IDT7188S45P
IDT6167LA25L
IDT7142S45C
IDT7188L25C
IDT6167LA25P
IDT7142S45L52
IDT7188L25P
IDT6167LA35D
IDT7142S45P
IDT7188L35C
IDT6167LA35L
IDT7142S55C
IDT6167LA35P
IDT7142S55L52
IDT7142S55P
IDT6168SA25D
IDT71681 SA45L
IDT7164S35D
IDT6168SA25L
IDT71681 SA45LB

1-15

STATIC RAM CROSS REFERENCE GUIDE

CYPRESS CaNT.

lOT

CYPRESS CaNT.

lOT

CYPRESS CaNT.

lOT

CY7C186-35PC
CY7C168-25PC
CY7C171-45PC
CY7C186-45DC
CY7C168"'"25SC
CY7C171 L-25DC
CY7C186-45DMB
CY7C168-35DC
CY7C171 L-25LC
CY7C186-45PC
CY7C168-35DMB
CY7C171L-25PC
CY7C186-55DC
CY7C168-35LC
CY7C171L-35DC
CY7C186-55DMB
CY7C168-35LMB
CY7C171L-35LC
CY7C186-55PC
CY7C168-35PC
CY7C171 L-35PC
CY7C186L-35DC
CY7C168-35SC
CY7C186L-35PC
CY7C168-45DC
CY7C172-25DC
CY7C186L-45DC
CY7C168-45DMB
CY7C172"725LC
CY7C186L-45DMB
CY7C168-45LC
CY7C172-25PC
CY7C186L-45PC
CY7C168-45LMB
CY7C172-35DC
CY7C186L-55DC
CY7C168-45PC
CY7C172-35DMB
CY7C186L-55DMB
CY7C168-45SC
CY7C172-35LC
CY7C186L-55PC
CY7C168L-25DC
CY7C172-35LMB
CY7C168L-25LC
CY7C172-35PC
CY7C187-25DC
CY7C168L-25PC
CY7C172-45DC
CY7C187-25PC
CY7C168L-25SC
CY7C172-45DMB
CY7C187 -35DC
CY7C168L-35DC
CY7C172-45LC
CY7C187-35DMB
CY7C168L-35LC
CY7C172-45LMB
CY7C187-35LC
CY7C168L-35PC
CY7C172-45PC
CY7C187-35LMB
CY7C168L-35SC

IDT7164S35P
IDT6168SA25P
IDT71681SA45P
IDT7164S45D .
IDT6168SA25S0
IDT71681LA25D
IDT7164S45DB
IDT6168SA35D
IDT71681 LA25L
IDT7164S45P
IDT6168SA35DB
IDT71681LA25P
IDT7164S55D
IDT6168SA35L
IDT71681LA35D
IDT7164S55DB
IDT6168SA35LB
IDT71681 LA35L
IDT7164S55P
IDT6168SA35P
IDT71681 LA35P
IDT7164L35D
IDT6168SA35S0
IDT7164L35P
IDT6168SA45D
IDT71682SA25D
IDT7164L45D
IDT6168SA45DB
IDT71682SA25L
IDT7164L45DB
IDT6168SA45L
IDT71682SA25P
IDT7164L45P
IDT6168SA45LB
IDT71682SA35D
IDT7164L55D
IDT6168SA45P
IDT71682SA35DB
IDT7164L55DB
IDT6168SA45S0
IDT71682SA35L
IDT7164L55P
IDT6168LA25D
IDT71682SA35LB
IDT6168LA25L
IDT71682SA35P
IDT7187S25D
IDT6168LA25P
IDT71682SA45D
IDT7187S25P
IDT6168LA25S0
IDT71682SA45DB
IDT7187S35D
IDT6168LA35D
IDT71682SA45L
IDT7187S35DB
IDT6168LA35L
IDT71682SA45LB
IDT7187S35L
IDT6168LA35P
IDT71682SA45P
IDT7187S35LB
IDT6168LA35S0

CY7C172L-25DC
CY7C187-35PC
CY7C172L-25LC
CY7C187-45DC
CY7C169-25DC
CY7C172L-25PC
CY7C187-45DMB
CY7C169-25LC
CY7C172L-35DC
CY7C187-45LC
CY7C169-25PC
CY7C172L-35LC
CY7C187 -45LMB
CY7C169-35DC
CY7C172L-35PC
CY7C187-45PC
CY7C169-35DMB
CY7C187L-25DC
CY7C169-35LC
CY7C185-35DC
CY7C187L-25PC
CY7C169-35LMB
CY7C185-35PC
CY7C187L-35DC
CY7C169-35PC
CY7C185-45DC
CY7C187L-35DMB
CY7C169-40DC
CY7C185-45DMB
CY7C187L-35LC
CY7C169-40DMB
CY7C185-45LC
CY7C187L-35LMB
CY7C169-40LC
CY7C185-45LMB
CY7C187L-35PC
CY7C169-40LMB
CY7C185-45PC
CY7C187L-45DC
CY7C169-40PC
CY7C185-55DC
CY7C187L-45DMB
CY7C169L-25DC
CY7C185-55DMB
CY7C187L-45LC
CY7C169L-25LC
CY7C185-55LC
CY7C187L-45LMB
CY7C169L-25PC
CY7C185-55LMB
CY7C187L-45PC
CY7C169L-35DC
CY7C185-55PC
CY7C169L-35LC
CY7C185L-35DC
CY7C198-45DC
CY7C169L-35PC
CY7C185L-35PC
CY7C198-45PC
CY7C185L-45DC
CY7C198-55DC
CY7C171-25DC
CY7C185L-45DMB
CY7C198-55DMB
CY7C171-25LC
CY7C185L-45LC
CY7C198-55PC
CY7C171-25PC
CY7C185L-45LMB
CY7C171-35DC
CY7C185L-45PC
CY7C194-35DC
CY7C171-35DMB
CY7C185L-55DC
CY7C194-45DC

IDT71682LA25D
IDT7187S35P
IDT71682LA25L
IDT7187S45D
IDT6169SA25D
IDT71682LA25P
IDT7187S45DB
IDT6169SA25L
IDT71682LA35D
IDT7187S45L
IDT6169SA25P
IDT71682LA35L
IDT7187S45LB
IDT6169SA35D
IDT71682LA35P
IDT7187S45P
IDT6169SA35DB
IDT7187L25D
IDT6169SA35L
IDT7164S35D
IDT7187L25P
IDT6169SA35LB
IDT7164S35P
IDT7187L35D
IDT6169SA35P
IDT7164S45D
IDT7187L35DB
IDT6169SA35D
IDT7164S45DB
IDT7187L35L
IDT6169SA35DB
IDT7164S45L28
IDT7187L35LB
IDT6169SA35L
IDT7164S45L28B
IDT7187L35P
IDT6169SA35LB
IDT7164S45P
IDT7187L45D
IDT6169SA35P
IDT7164S55D
IDT7187L45DB
IDT6169LA25D
IDT7164S55DB
IDT7187L45L
IDT6169LA25L
IDT7164S55L28
IDT7187L45LB
IDT6169LA25P
IDT7164S55L28B
IDT7187L45P
IDT6169LA35D
IDT7164S55P
IDT6169LA35L
IDT7164L35D
IDT71256S45D
IDT6169LA35P
IDT7164L35P
IDT71256S45P
IDT7164L45D
IDT71256S55D
IDT71681SA25D
IDT7164L45DB
IDT71256S55DB
IDT71681SA25L
IDT7164L45L28
IDT71256S55P
IDT71681SA25P
IDT7164L45L28B
IDT71681SA35D
IDT7164L45P
IDT71258S35T
IDT71681SA35DB
IDT7164L55D
IDT71258S45T

CY7C171-35LC
CY7C185L-55DM B
CY7C194-45DM B
CY7C171-35LM B
CY7C185L-55LC
CY7C171-35PC
CY7C185L-55LM B
CY7C197-35DC
CY7C171-45DC
CY7C185L-55PC
CY7C197 -45DC
CY7C171-45DMB
CY7C197-45DMB

IDT71681 SA35L
IDT7164L55DB
IDT71258S45TB
IDT71681 SA35LB
IDT7164L55L28
IDT71681 SA35P
IDT7164L55L28B
IDT71257S35T
IDT71681 SA45D
IDT7164L55P
IDT71257S45T
IDT71681 SA45DB
IDT71257S45TB

MATRA-HARRIS

lOT

HM1-2064-2
HM4-65261 C-2
HM1-65728N-5
HM1-2064-5
HM4-65261C-5
HM3-65728K-5
HM1-2064-8
H M4-65261 C-8
HM3-65728M-5
HM3-2064-5
HM4-65261S-2
HM3-65728N-5
HM3-2064U-5
HM4-65261S-5
HM4-65728K-5
HM4-2064-2
H M4-65261 S-8
HM4-65728M-2
HM4-2064-5
HM1-65728M-5
HM4-2064-8
HM1-65263-2
HM1-65728N-2
HMT-2064-5
HM1-65263-5
HM1-65728N-5
HMT-2064U-5
HM3-65263-5
HM4-65263-2
HM1-65767H-5
HM1-6116-2
HM4-65263-5
HM1-65767K-2
HM1-6116-5
HM1-65767K-5
HM1-6116-8
HM1-65641-2
HM1-65767K-8
HM1-6116L-2
HM1-65641-5
HM1-65767M-2
HM1-6116L-5
HM1-65641-8
HM1-65767M-5
HM1-6116L-8
HM1-65641S-2
HM1-65767M-8
HM3-6116-5
HM1-65641S-5
HM3-65767H-5
HM3-6116L-5
HM1-65641S-8
HM3-65767K-5
HM4-6116-2
HM3-65641-5
HM3-65767M-5
HM4-6116-5
HM4-65641-2
HM4-65767H-5

IDT7164L150DM
IDT6167SA100LM
IDT6116SA55D .
IDT7164L70D
IDT6167SA55L
IDT6116SA35TP
IDT7164L150DB
IDT6167SA100LB
IDT6116SA45TP
IDT7164L70P
IDT6167SA70LM
IDT6116SA55TP
IDT7164L70P
IDT6167SA55L
IDT6116SA35L24
IDT7164L15OL32M
IDT6167SA70LB
IDT6116SA45L24M
IDT7164L70L32
IDT6116SA45L24
IDT7164L15OL32B
IDT6167LA55DM
IDT6116SA55L24M
IDT7164L70S0
IDT6167LA45D
IDT6116SA55L24
IDT7164L70S0
IDT6167LA45P
IDT6167LA55LM
IDT6167SA25D
IDT6116SA90DM
IDT6167LA45L
IDT6167SA35DM
IDT6116SA90D
IDT6167SA35D
IDT6116SA120DB
IDT7164L85DM
IDT6167SA35DB
IDT6116LA90DM
IDT7164L55D
IDT6167SA45DM
IDT6116LA90D
IDT7164L85DB
IDT6167SA45D
IDT6116LA120DB
IDT7164L55DM
IDT6167SA45DB
IDT6116SA90P
IDT7164L45D
IDT6167SA25P
IDT6116LA90P
IDT7164L55DB
IDT6167SA35P
IDT6116SA90L32M
IDT7164L55P
IDT6167SA45P
IDT6116SA90L32
IDT7164L85L32M
IDT6167SA25L

NOTES:
A lower case ·x· indicates the speed and/or
package of the part are unknown.·
*The CY7C1611162 come in a 300 mil package
vs. 400 milIDT71981/982.

1-16

STATIC RAM CROSS REFERENCE GUIDE

MATRA-HARRIS
CONT.
HM4-6116-8
HM4-65641-5
HM4-65767K-2
HM4-6116L-2
HM4-65641-8
HM4-65767K-5
H M4-6116L-5
HM4-65767K-8
HMl-65681-2
HM4-65767M-2
HMl-65161-2
HMl-65681-5
HM4-65767M-5
HMl-65161-5
HMl-65681-8
HM4-65767M-8
HMl-65161-8
HMl-65681 B-2
HM3-65161-5
HMl-65681 B-5
HMl-65768H-5
HM4-65161-2
HMl-65681C-2
HMl-65768K-2
HM4-65161-5
HMl-65681C-5
HMl-65768K-5
HM4-65161-8
HMl-65681C-8
HMl-65768K-8
HMl-65681S-2
HMl-65768M-2
HMl-65163-2
HMl-65681S-5
HMl-65768M-5
HMl-65163-5
HMl-65681S-8
HMl-65768M-8
HMl-65163-8
HM3-65681-5
HM3-65768H-5
HM3-65163-5
HM3-65681B-5
HM3-65768K-5
HM4-65163-2
HM3-65681C-5
HM3-65768M-5
HM4-65163-5
HM3-65681S-5
HM4-65768H-5
HM4-65163-8
HM4-65681-2
HM4-65768K-2
4-65681-5
HM4-65768K-5
HM1-65261-2
HM4-65681-8
HM4-65768K-8
HM1-65261-5
HM4-65681 B-2
HM4-65768M-2
HMl-65261-8
HM4-65681 B-5

lOT
IDT6116SA120L32B
IDT7164L55L32
IDT6167SA35LM
IDT6116LA90L32M
IDT7164L85L32B
IDT6167SA35L
IDT6116LA90L32
IDT6167SA35LB
IDT6168LA85DM
IDT6167SA45LM
IDT6116LA90DM
IDT6168LA55D
IDT6167SA45L
IDT6116LA70D
IDT6168LA85DB
IDT6167SA45LB
IDT6116LA90DB
IDT6168LA70DM
IDT6116LA70P
IDT6168LA55D
IDT6168SA25D
IDT6116LA90L32M
IDT6,68SA85DM
IDT6168SA35DM
IDT6116LA70L32
IDT6168SA55D
IDT6168SA35D
IDT6116LA90L32B
IDT6168SA85DB
IDT6168SA35DB
IDT6168SA70DM
IDT6168SA45DM
IDT6116LA85DM
IDT6168SA55D
IDT6168SA45D
IDT6116LA55D
IDT6168SA70DB
IDT6168SA45DB
IDT6116LA85DB
IDT6168LA55P
IDT6168SA25P
IDT6116LA45P
IDT6168LA55P
IDT6168SA35P
IDT6116LA55LM
IDT6168SA55P
IDT6168SA45P
IDT6116LA45L
IDT6168SA55P
IDT6168SA25L
IDT6116LA45LB
IDT6168LA85LM
IDT6168SA35LMHM
IDT6168LA55L
IDT6168SA35L
IDT6167LA85DM
IDT6168LA85LB
IDT6168SA35LB
IDT6167LA55D
IDT6168LA70LM
IDT6168SA45LM
IDT6167LA85DB
IDT6168LA55L

NOTES:
A lower case ·x· indicates the speed and/or
package the part are unknown.·
*The CY7C161/162 come in a 300 mil package
vs. 400 milIDT71981/982.

of

~

MATRA-HARRIS
CONT.

lOT

HM4-65768M-5
HMl-65261 B-2
HM4-65681C-2
HM4-65768M-8
HM1-65261 B-5
HM4-65681C-5
HMl-65261B-8
HM4-65681 C-8
HMl-65769H-5
HMl-65261C-2
HM4-65681S-2
HMl-65769K-2
HMl-65261C-5
HM4-65681S-5
HMl-65769K-5
HMl-65261C-8
HM4-65681S-8
HMl-65769K-8
HMl-65261S-2
HMl-65769M-2
HMl-65261S-5
HMl-65682-2
HMl-65769M-5
HMl-65261S-8
HMl-65682-5
HMl-65769M-8
HM3-65261-5
HMl-65682-8
HM3-65769H-5
HM3-65261 B-5
HM3-65682-5
HM3-65769K-5
HM3-65261 C-5
HM4-65682-2
HM3-65769M-5
HM3-65261S-5
HM4-65682-5
HM4-65769H-5
HM4:'65261-2
HM4-65682-8 .
HM4-65769K-2
HM4-65261-5
HM4-65769K-5
HM4-65261-8
HMl-65728K-5
HM4-65769K-8
HM4-65261 B-2
HMl-65728M-2
HM4-65769M-2
HM4-65261 B-5
HMl-65728M-5
HM4-65769M-5
HM4-65261 B-8
HM1-65728N-2
HM4-65769M-8

IDT6168SA45L
IDT6167LA70DM
IDT6168SA85LM
IDT6168SA45LB
IDT6167LA55D
IDT6168SA55L
IDT6167LA70DB
IDT6168SA85LB
IDT6169SA25D
IDT6167SA1ooDM
IDT6168SA70LM
IDT6169SA35DM
IDT6167SA55D
IDT6168SA55L
IDT6169SA35D
IDT6167SA1ooDB
IDT6168SA70LB
IDT6169SA35DB
IDT6167SA70DM
IDT6169SA450M
IDT6167SA55D
IDT6168LA55DM
IDT6169SA45D
IDT6167SA70DB
IDT6168LA45D
IDT6169SA45DB
IDT6167LA55P
IDT6168LA45DB
IDT6169SA25P
IDT6167LA55P
IDT6168LA45P
IDT6169SA35P
IDT6167SA55P
IDT6168LA55LM
IDT6169SA45P
IDT6167SA55P
IDT6168LA45L
IDT6169SA25L
IDT6167LA85LM
IDT6168LA55LB
IDT6169SA35LM
IDT6167LA55L
IDT6169SA35L
IDT6167LA85LB
IDT6116SA35D
IDT6169SA35LB
IDT6167LA70LM
IDT6116SA45DM
IDT6169SA45LM
IDT6167LA55L
IDT6116SA45D
IDT6169SA45L
IDT6,67LA70LB
IDT61 16SA55DM
IDT6169SA45LB

PERFORMANCE

lOT

P4C116-25CC
P4C168-35CC
P4C1681 L-25LM
P4C1 16-25LC
P4C168-35CM
P4C1681 L-25LMB
P4Cl16-25PC
P4C168-35CMB
P4Cl681 L-25PC
P4C116-30CC
P4Cl68-35LC
P4Cl681L-35CC
P4Cl16-30LC
P4Cl68-35LM
P4Cl681 L-35CM
P4C1 16-30PC

IDT6116SA25TD
IDT6168SA35D
IDT71 681 LA25LM
IDT6116SA25L24
IDT6168SA35DM
IDT71681LA25LB
IDT61 16SA25TP
IDT6168SA35DB
IDT71681 LA25P
IDT61 16SA30TD
IDT6168SA35L
IDT71 681 LA35D
IDT6116SA30L24
IDT6168SA35LM
IDT71681LA350M
IDT6116SA30TP

1-17

PERFORMANCE
CONT.

lOT

P4Cl68-35LMB
P4Cl681L-35CMB
P4Cl16-35CC
P4C168-35PC .
P4C1681 L-35LC
P4Cl16-35CM
P4Cl68-45CM
P4Cl681 L-35LM
P4Cl16-35CMB
P4Cl68-45CMB
P4C1681 L-35LM B
P4Cl16-35LC
P4Cl68-45LM
P4Cl681 L-35PC
P4Cl16-35LM
P4C1681L-45CC
P4Cl16-35LMB
P4Cl68-45LMB
P4Cl681 L-45CM
P4C1 , 6-35PC
P4C168L-20CC
P4C1681L-45CMB
P4C116L-25CC
P4C168L-20LC
P4Cl681L-45LC
P4C116L-25LC
P4Cl68L-20PC
P4Cl681 L-45LM
P4Cl16L-25PC
P4C168L-25CC
P4Cl681L-45LMB
P4Cl16L-30CC
P4Cl68L-25CM
P4C1681L-45PC
P4C116L-30LC
P4Cl68L-25CMB
P4Cl16L-30PC
P4C168L-25LC
P4Cl682-20CC
P4Cl16L-35CC
P4Cl68L-25LM
P4C1682-20LC
P4Cl16L-35CM
P4C168L-25LMB
P4Cl682-20PC
P4C116L-35CMB
P4Cl68L-25PC
P4C1682-25CC
P4Cl68L-35CC
P4Cl682-25CM
P4Cl16L-35LM
P4Cl68L-35CM
P4C1682-25CMB
P4C116L-35LMB
P4C168L-35CMB
P4C1682-25LC
P4C1 16L-35PC
P4C168L-35LC
P4C1682-25LM
P4C168L-35LM
P4Cl682-25LM B
P4Cl64-30CC
P4C168L-35LMB
P4C1682-25PC
P4C164-30LC
P4Cl68L-35PC
P4C1682-35CC
P4Cl64-30PC
P4Cl68L-45CM
P4Cl682-35CM
P4C164-35CC
P4Cl68L-45CM B
P4C1682-35CMB
P4Cl64-35CM
P4C168L-45LM

IDT6168SA35LB
IOT71681LA35DB
IDT6116SA35TD
IDT6168SA35P
IDT71681LA35L
IDT6116SA35TDM
IDT6168SA45DM
IDT71681 LA35LM
IOT6116SA35TDB
IDT6168SA45CB
IDT71681 LA35LB
IDT6116SA35L24
IOT6168SA45LM
IDT71681 LA35P
IDT6116SA35L24M
IDT71681LA45D
IDT6116SA35L24B
IDT6168SA45LB
IDT71681LA450M
IDT6' '6SA35TP
IDT6168LA20D
IDT71681LA45CB
IDT6116LA25TO
IDT6168LA20L
IDT71681 LA45L
IDT6116LA25L24
IDT6168LA20P
IDT71681 LA45LM
IDT6116LA25TP
IDT6168LA25D
IDT71681 LA45LB
IOT6116LA30TD
IDT6168LA25DM
IDT71681 LA45P
IDT6116LA30L24
IDT6168LA25DB
IDT6116LA30TP
IDT6168LA25L
IDT71682SA20D
IDT6116LA35TD
IDT6168LA25LM
IDT71682SA20L
IDT6116LA35TDM·
IDT6168LA25LB
IDT71682SA20P
IDT6116LA35TDB
IDT6168LA25P
IDT6116LA35L24
IDT6168LA350
IDT71682SA25DM
IDT6116LA35L24M
IDT6168LA35DM
IDT71682SA25DB
IDT61 16LA35L24B
IDT6168LA35DB
IDT71682SA25L
IDT6116LA35TP
IDT6168LA35L
IDT71682SA25LM
IDT6168LA35LM
IDT71682SA25LB
IDT7164S30TC
IDT6168LA35LB
IDT71682SA25P
IDT7164S30L28
IDT6168LA35P
IDT71682SA35D
IDT7164S30TP
IDT6168LA45DM
IDT71682SA35DM
IDT7164S35TC
IDT6168LA45CB
IDT71682SA35DB
IDT7164S35TCM
IDT6168LA45LM

STATIC RAM CROSS REFERENCE GUIDE

PERFORMANCE
CONT.
P4C1682-35LC
P4C164-35CMB
P4C168L-45LMB
P4C1682-35LM
P4C164-35LC
P4C1682-35LMB
P4C164-35LM
P4C1681-20CC
P4C1682-35PC
P4C164-35LMB
P4C1681-20LC
P4C1682-45CC
P4C164-35PC
P4C1681-20PC
P4C1682-45CM
P4C164-45CM
P4C1681-25CC
P4C1682-45CMB
P4C164-45CMB
P4C1681-25CM
P4C1682-45LC
P4C164-45LM
P4C1681-25CMB
P4C1682-45LM
P4C164-45LMB
P4C1681-25LC
P4C1682-45LMB
P4C164L-30CC
P4C1681-25LM
P4C1682-45PC
P4C164L-30LC
P4C1681-25LMB
P4C1682L-20CC
P4C164L-30PC
P4C1681-25PC
P4C1682L-20LC
P4C164L-35CC
P4C1681-35CC
P4C1682L-20PC
P4C164L-35CM
P4C1681-35CM
P4C1682L-25CC
P4C164L-35CMB
P4C1681-35CMB
P4C1682L-25CM
P4C164L-35LC
P4C1681-35LC
P4C1682L-25CMB
P4C164L-35LM
P4C1681-35LM
P4C1682L-25LC
P4C164L-35LMB
P4C1681-35LMB
P4C1682L-25LM
P4C164L-35PC
P4C1681-35PC
P4C1682L-25LMB
P4C164L-45CM
P4C1681-45CC
P4C1682L-25PC
P4C164L-45CMB
P4C1681-45CM
P4C1682L-35CC

lOT
IDT71682SA35L
IDT7164S35TCB
IDT6168LA45LB
IDT71682SA35LM
IDT7164S30L28
IDT71682SA35LB
IDT7164S35L28M
IDT71681 SA20D
IDT71682SA35P
IDT7164S35L28B
IDT71681SA20L
IDT71682SA45D
IDT7164S35TP
IDT71681SA20P
IDT71682SA45DM
IDT7164S45TCM
IDT71681SA25D
IDT71682SA45CB
IDT7164S45TCB
IDT71681 SA25DM
IDT71682SA45L
IDT7164S45L28M
IDT71681SA25DB
IDT71682SA45LM
IDT7164S45L28B
IDT71681SA25L
IDT71682SA45LB
IDT7164L30TC
IDT71681SA25LM
IDT71682SA45P
IDT7164L30L28
IDT71681SA25LB
IDT71682LA20D
IDT7164L30TP
IDT71681SA25P
IDT71682LA20L
IDT7164L35TC
IDT71681SA35D
IDT71682LA20P
IDT7164L35TCM
IDT71681 SA35DM
IDT71682LA25D
IDT7164L35TCB
IDT71681 SA35DB
IDT71682LA25DM
IDT7164L30L28
IDT71681SA35L
IDT71682LA25DB
IDT7164L35L28M
IDT71681 SA35LM
IDT71682LA25L
IDT7164L35L28B
IDT71681SA35LB
IDT71682LA25LM
IDT7164L35TP
IDT71681SA35P
IDT71682LA25LB
IDT7164L45TCM
IDT71681 SA45D
IDT71682LA25P
IDT7164L45TCB
IDT71681SA45DM
IDT71682LA35D

NOTES:
A lower case ·x· indicates the speed and/or
package of the part are unknown.·
*Jhe CY7C161/162 come in a 300 mil package
vs. 400 milIDT71981/982.

PERFORMANCE
CONT.

lOT

PERFORMANCE
CONT.

lOT

P4C164L-45LM
P4C1681-45CMB
P4C1682L-35CM
P4C164L-45LMB
P4C1681-45LC
P4C1682L-35CMB
P4C1681-45LM
P4C1682L-35LC
P4C168-20CC
P4C1681-45LMB
P4C1682L-35LM
P4C168-20LC
P4C1681-45PC
P4C1682L-35LMB
P4C168-20PC
P4C1681 L-20CC
P4C1682L-35PC
P4C168-25CC
P4C1681 L-20LC
P4C1682L-45CC
P4C168-25CM
P4C1681 L-20PC
P4C1682L-45CM
P4C168-25CMB
P4C1681L-25CC
P4C1682L-45CMB
P4C168-25LC
P4C1681L-25CM
P4C1682L-45LC
P4C168-25LM
P4C1681L-25CMB
P4C1682L-45LM
P4C168-25LMB
P4C1681L-25LC
P4C1682L-45LMB
P4C168-25PC
P4C1682L-45PC
P4C187-25CC
P4C188L-35CC
P4C198L-35LMB
P4C187-25PC
P4C188L-35CM
P4C198L-35PC
P4C187-2LC
P4C188L-35CMB
P4C198L-45CC
P4C187-30CM
P4C188L-35LC
P4C198L-45CM
P4C187-30CMB
P4C188L-35LM
P4C198L-45CMB
P4C187-30LM
P4C188L-35LMB
P4C198L-45LC
P4C187-30LMB
P4C188L-35PC
P4C198L-45LM
P4C187 -35CM
P4C188L-45CC
P4C198L-45LMB
P4C187-35CMB
P4C188L-45CM
P4C198L-45PC
P4C187-35LM
P4C188L-45CM B
P4C198L-55CM
P4C187-35LMB
P4C188L-45LC
P4C198L-55CMB
P4C187L-25CC
P4C188L-45LM
P4C198L-55LM
P4C187L-25PC
P4C188L-45LMB

IDT7164L45L28M
IDT71681 SA45CB
IDT71682LA35DM
IDT7164L45L28B
IDT71681 SA45L
IDT71682LA35DB
IDT71681 SA45LM
IDT71682LA35L
IDT6168SA20D
IDT71681 SA45LB
IDT71682LA35LM
IDT6168SA20L
IDT71681SA45P
IDT71682LA35LB
IDT6168SA20P
IDT71681 LA20D
IDT71682LA35P
IDT6168SA25D
IDT71681LA20L
IDT71682LA45D
IDT6168SA25DM
IDT71681 LA20P
IDT71682LA45DM
IDT6168SA25DB
IDT71681 LA25D
IDT71682LA45CB
IDT6168SA25L
IDT71681 LA25DM
IDT71682LA45L
IDT6168SA25LM
IDT71681 LA25DB
IDT71682LA45LM
IDT6168SA25LB
IDT71681 LA25L
IDT71682LA45LB
IDT6168SA25P
IDT71682LA45P
IDT7187S25C
IDT7188L35C
IDT6198L35L
IDT7187S25P
IDT7188L35CM
IDT6198L35P
IDT7187S25L22
IDT7188L35CB
IDT6198L45C
IDT7187S30CM
IDT7188L35L
IDT6198L45CM
IDT7187S30CB
IDT7188L35LM
IDT6198L45CB
IDT7187S30L22M
IDT7188L35LB
IDT6198L45L
IDT7187S35L22B
IDT7188L35P
IDT6198L45LM
IDT7187S35CM
IDT7188L45C
IDT6198L45LB
IDT7187S35CB
IDT7188L45CM
IDT6198L45P
IDT7187S30L22M
IDT7188L45CB
IDT6198L55CM
IDT7187S35L22B
IDT7188L45L
IDT6198L55CB
IDT7187L25C
IDT7188L45LM
IDT6198L55LM
IDT7187L25P
IDT7188L45LB

P4C198L-55LMB
P4C187L-2LC
P4C188L-45PC
P4C187L-30CM
P4C188L-55CM
P4C1981-25CC
P4C187L-30CMB
P4C188L-55CMB
P4C1981-25LC
P4C187L-30LM
P4C188L-55LM
P4C1981-30CC
P4C187L-30LMB
P4C188L-55LMB
P4C1981-30CM
P4C187L-35CM
P4C1981-30CMB
P4C187L-35CMB
P4C198-25CC
P4C1981-30LC
P4C187L-35LM
P4C198-25LC
P4C1981-30LM
P4C187L-35LMB
P4C198-25PC
P4C1981-30LMB
P4C198-30CC
P4C1981-35CC
P4C188-25CC
P4C198-30CM
P4C1981-35CM
P4C188-25LC
P4C198-30CMB
P4C1981-35CMB
P4C188-25PC
P4C198-30LC
P4C1981-35LC
P4C188-30CC
P4C198-30LM
P4C1981-35LM
P4C188-30CM
P4C198-30LMB
P4C1981-35LMB
P4C188-30CMB
P4C198-30PC
P4C1981-45C
P4C188-30LC
P4C198-35CC
P4C1981-45CM
P4C188-30LM
P4C198-35CM
P4C1981-45CMB
P4C188-30LMB
P4C198-35CMB
P4C1981-45LC
P4C188-30PC
P4C198-35LC
P4C1981-45LM
P4C188-35CC
P4C198-35LM
P4C1981-45LMB
P4C188-35CM
P4C198-35LMB
P4C1981-55CM
P4C188-35CMB
P4C198-35PC
P4C1981-55CMB
P4C188-35LC
P4C198-45CC
P4C1981-55LM
P4C188-35LM
P4C198-45CM
P4C1981-55LMB
P4C188-35LMB
P4C198-45CMB

IDT6198L55LB
IDT7187L25L22
IDT7188L45P
IDT7187L30CM
IDT7188L55CM
IDT71981S25C
IDT7187L30CB
IDT7188L55CB
IDT71981 S25L
IDT7187L30L22M
IDT7188L55LM
IDT71981 S30C
IDT7187L35L22B
IDT7188L55LB
IDT71981S30CM
IDT7187L35CM
IDT71981S30CB
IDT7187L35CB
IDT6198S25C
IDT71981S30L
IDT7187L30L22M
IDT6198S25L
IDT71981 S30LM
IDT7187L35L22B
IDT6198S25P
IDT71981 S30LB
IDT6198S30C
IDT71981S35C
IDT7188S25C
IDT6198S30CM
IDT71981 S35CM
IDT7188S25L
IDT6198S30CB
IDT71981S35CB
IDT7188S25P
IDT6198S30L
IDT71981S35L
IDT7188S30C
IDT6198S30LM
IDT71981 S35LM
IDT7188S30CM
IDT6198S30LB
IDT71981S35LB
IDT7188S30CB
IDT6198S30PC
IDT71981S45C
IDT7188S30L
IDT6198S35C
IDT71981S45CM
IDT7188S30LM
IDT6198S35CM
IDT71981S45CB
IDT7188S30LB
IDT6198S35CB
IDT71981 S45L
IDT7188S30P
IDT6198S35L
IDT71981S45LM
IDT7188S35C
IDT6198S35LM
IDT71981S45LB
IDT7188S35CM
IDT6198S35LB
IDT71981 S55CM
IDT7188S35CB
IDT6198S35P
IDT71981S55CB
IDT7188S35L
IDT6198S45C
IDT71981855LM
IDT7188S35LM
IDT6198S45CM
IDT71981S55LB
IDT7188S35LB
IDT6198S45CB

1-18

STATIC RAM CROSS REFERENCE GUIDE

PERFORMANCE
CONT.
P4C1981L-25CC
P4C188-35PC
P4C198-45LC
P4C1981 L-25LC
4C188-45CC
P4C198-45LM
P4C1981 L-30CC
P4C188-45CM
P4C198-45LMB
P4C1981 L-30CM
P4C188-45CMB
P4C198-45PC
P4C1981L-30CMB
P4C188-45LC
P4C198-55CM
P4C1981L-30LC
P4C188-45LM
P4C198-55CMB
P4C1981 L-30LM
P4C188-45LMB
P4C198-55LM
P4C1981L-30LMB
P4C188-45PC
P4C198-55LMB
P4C1981 L-35CC
P4C188-55CM
P4C198L-25CC
P4C1981 L-35CM
P4C188-55CMB
P4C198L-25LC
P4C1981L-35CMB
P4C188-55LM
P4C198L-25PC
P4C1981 L-35LC
P4C188-55LMB
P4C198L-30CC
P4C1981 L-35LM
P4C188L-25CC
P4C198L-30CM
P4C1981 L-35LMB
P4C188L-25LC
P4C198L-30CMB
P4C1981 L-45CC
P4C188L-25PC
P4C198L-30LC
P4C1981 L-45CM
P4C188L-30CC
P4C198L-30LM
P4C1981L-45CMB
P4C188L-30CM
P4C198L-30LMB
P4C1981 L-45LC
P4C188L-30CMB
P4C198L-30PC
P4C1981L-45LM
P4C188L-30LC
P4C198L-35CC
P4C1981L-45LMB
P4C188L-30LM
P4C198L-35CM
P4C1981L-55CM
P4C188L-30LMB
P4C198L-35CMB
P4C1981L-55CMB
P4C188L-30PC
P4C198L-35LC
P4C1981 L-55LM

IDT
ID171981 L25C
ID17188S35P
IDT6198S45L
ID171981 L25L
ID17188S45C
IDT6198S45LM
ID171981L30C
ID17188S45CM
IDT6198S45LB
ID171981L30CM
ID17188S45CB
IDT6198S45P
ID171981L30CB
IDT7188S45L
IDT6198S55CM
IDT71981L30L
ID17188S45LM
IDT6198S55CB
IDT71981L30LM
IDT7188S45LB
IDT6198S55LM
ID171981L30LB
IDT7188S45P
IDT6198S55LB
IDT71981L35C
IDT7188S55CM
IDT6198L25C
ID171981L35CM
ID17188S55CB
IDT6198L25L
ID171981 L35CB
IDT7188S55LM
IDT6198L25P
IDT71981 L35L
IDT7188S55LB
IDT6198L30C
IDT71981 L35LM
ID17188L25C
IDT6198L30CM
ID171981 L35LB
ID17188L25L
IDT6198L30CB
ID171981 L45C
ID17188L25P
IDT6198L30L
ID171981 L45CM
ID17188L30C
IDT6198L30LM
ID171981 L45CB
ID17188L30CM
IDT6198L30LB
IDT71981 L45L
IDT7188L30CB
IDT6198L30P
IDT71981 L45LM
ID17188L30L
IDT6198L35C
ID171981 L45LB
ID17188L30LM
IDT6198L35CM
ID171981 L55CM
ID17188L30LB
IDT6198L35CB
IDT71981 L55CB
ID17188L30P
IDT6198L35L
IDT71981 L55LM

NOTES:
A lower case ·x· indicates the speed and/or
package of the part are unknown.·
*The CY7C161/162 come in a 300 mil package
vs. 400 milID171981/982.

PERFORMANCE
CONT.

lOT

P4C198L-35LM
P4C1981L-55LMB
P4C1982-25CC
P4C1982L-35LC
P4C198A-45LM
P4C1982-25LC
P4C1982L-35LM
P4C198A-45LMB
P4C1982-30CC
P4C1982L-35LM B
P4C198A-45PC
P4C1982-30CM
P4C1982L-45CC
P4C198A-55CM
P4C1982-30CMB
P4C1982L-45CM
P4C198A-55CMB
P4C1982-30LC
P4C1982L-45CM B
P4C198A-55LM
P4C1982-30LM
P4C1982L-45LC
P4C198A-55LM B
P4C1982-30LM B
P4C1982L-45LM
P4C198AL-25CC
P4C1982-35CC
P4C1982L-45LMB
P4C198AL-25LC
P4C1982-35CM
P4C1982L-55CM
P4C198AL-25PC
P4C1982-35CMB
P4C1982L-55CMB
P4C198AL-30CC
P4C1982-35LC
P4C1982L-55LM
P4C198AL-30CM
P4C1982-35LM
P4C1982L-55LMB
P4C198AL-30CMB
P4C1982-35LM B
P4C198AL-30LC
P4C1982-45CC
P4C198A-25CC
P4C198AL-30LM
P4C1982-45CM
P4C198A-25LC
P4C198AL-30LM B
P4C1982-45CMB
P4C198A-25PC
P4C198AL-30PC
P4C1982-45LC
P4C198A-30CC
P4C198AL-35CC
P4C1982-45LM
P4C198A-30CM
P4C198AL-35CM
P4C1982-45LMB
P4C198A-30CMB
P4C198Al-35CMB
P4C1982-55CM
P4C198A-30LC
P4C198AL-35LC
P4C1982-55CMB
P4C198A-30LM
P4C198AL-35LM
P4C1982-55LM
P4C198A-30LMB
P4C198AL-35LMB
P4C1982-55LMB
P4C198A-30PC
P4C198AL-35PC
P4C1982L-25CC
P4C198A-35CC

IDT6198L35LM
ID171981 L55LB
ID171982S25C
ID171982L35L
ID17198S45LM
ID171982S25L
ID171982L35LM
ID17198S45LB
ID171982S30C
ID171982L35LB
ID17198S45P
ID171982S30CM
ID171982L45C
IDT7198S55CM
IDT71982S30CB
IDT71982L45CM
IDT7198S55CB
IDT71982S30L
IDT71982L45CB
IDT7198S55LM
IDT71982S30LM
IDT71982L45L
ID17198S55LB
ID171982S30LB
IDT71982L45LM
IDT7198L25C
ID171982S35C
ID171982L45LB
ID17198L25L
ID171982S35CM
ID171982L55CM
ID17198L25P
IDT71982S35CB
ID171982L55CB
ID17198L30C
ID171982S35L
ID171982L55LM
ID17198L30CM
ID171982S35LM
IDT71982L55LB
IDT7198L30CB
ID171982S35LB
ID17198L30L
ID171982S45C
ID17198S25C
IDT7198L30LM
ID171982S45CM
IDT7198S25L
ID17198L30LB
ID171982S45CB
IDT7198S25P
ID17198L30P
ID171982S45L
ID17198S30C
ID17198L35C
ID171982S45LM
IDT7198S30CM
ID17198L35CM
ID171982S45LB
IDT7198S30CB
ID17198L35CB
ID171982S55CM
IDT7198S30L
IDT7198L35L
ID171982S55CB
IDT7198S30LM
ID17198L35LM
IDT71982S55LM
ID17198S30LB
IDT7198L35LB
IDT71982S55LB
IDT7198S30P
IDT7198L35P
IDT71982L25C
IDT7198S35C

1-19

PERFORMANCE
CONT.

lOT

P4C198AL-45CC
P4C1982L-25LC
P4C198A-35CM
P4C198AL-45CM
P4C1982L-30CC
P4C198A-35CMB
P4C198AL-45CM B
P4C1982L-30CM
P4C198A-35LC
P4C198AL-45LC
P4C1982L-30CMB
P4C198A-35LM
P4C198AL-45LM
P4C1982L-30LC
P4C198A-35LMB
P4C198AL-45LMB
P4C1982L-30LM
P4C198A-35PC
P4C198AL-45PC
P4C1982L-30LMB
P4C198A-45CC
P4C198AL-55CM
P4C1982L-35CC
P4C198A-45CM
P4C198AL-55CMB
P4C1982L-35CM
P4C198A-45CMB
P4C198AL-55LM
P4C1982L-35CMB
P4C198A-45LC
P4C198AL-55LMB

IDT7198L45C
ID171982L25L
ID17198S35CM
ID17198L45CM
ID171982L30C
ID17198S35CB
ID17198L45CB
ID171982L30CM
ID17198S35L
ID17198L45L
ID171982L30CB
ID17198S35LM
IDT7198L45LM
IDT71982L30L
IDT7198S35LB
IDT7198L45LB
IDT71982L30LM
IDT7198S35P
IDT7198L45P
IDT71982L30LB
IDT7198S45C
IDT7198L55CM
ID171982L35C
IDT7198S45CM
IDT7198L55CB
ID171982L35CM
ID17198S45CB
ID17198L55LM
ID171982L35CB
ID17198S45L
ID17198L55LB

FUJITSU
MB81C67-35
MB81C69A-25C
MB81C78-45
MB81C67-45
MB81C69A-25P
MB81C78-55
MB81C67-45-W
MB81C69A-25Z
MB81C78-70
MB81C67-55
MB81C69A-30C
MB81C67-55-W
M B81 C69A-30P
MB81C78A-35CV
MB81C69A-30Z
MB81C78A-35P
MB81C68-35C
MB81C69A-35C
MB81C78A-35PF
MB81C68-35P
MB81C69A-35P
MB81C68-35Z
MB81C69A-35Z
MB8416A-12x
M B81 C68-45-W
MB8416A-12x
MB81C68-45C
MB81C71-35
MB8416A-12x
MB81C68-45P
MB81C71-45C
MB81C68-45Z
MB81C71-45Z
MB84256-10
MB81C68-55-W
MB81C71-55C
MB84256-10
MB81C71-55Z
MB84256-10
MB81C68A-25C

IDT
IDT6167SA35P
IDT6169SA25L
IDT7164S45P
IDT6167SA45P
IDT6169SA25P
IDT7164S55P
IDT6167SA45xM
IDT6169SA25D
ID17164S70P
IDT6167SA55P
IDT6169SA25L
IDT6167SA55xM
IDT6169SA25P
ID17164S35L22
IDT6169SA25D
IDT7164S35P
IDT6168SA35L
IDT6169SA35L
IDT7164S35S0
IDT6168SA35P
IDT6169SA35P
IDT6168SA35D
IDT6169SA35D
IDT6116LA90P
IDT6168SA45xM
IDT6116LA90D
IDT6168SA45L
ID17187S35P
IDT6116LA90TP
IDT6168SA45P
ID17187S45L22
IDT6168SA45D
ID17187S45D
ID171256L70L
IDT6168SA55xM
IDT7187S55L22
IDT71256L70P
IDT7187S55D
ID171256L70S0
IDT6168SA25L

STATIC RAM CROSS REFERENCE GUIDE

FUJITSU CONT.
MB81C68A-25P
MB81C74-25x
MB8464-15-W
MB81 C68A-25Z
MB81C74-35x
MB8464-15-W
MB81C68A-30C
MB8464-20-W
MB81C68A-30P
MB81C75-35
MB8464-20-W
MB81C68A-30Z
MB81C75-45
MB81C68A-35C
MB81C75-55
MB8464A-10-W
MB81C68A-35P
MB8464A-10-W
MB81C68A-35Z
MB81C81-45
MB8464A-15-W
MB81C81-55
MB8464A-15-W
MB8464A-70x
MB81C84-45
MB8464A-70x
MB81C84-55
MB8464A-70x

lOT
IDT6168SA25P
IDT7188S25x
IDT7164S150DM
IDT6168SA25D
IDT7188S35x
IDT7164S1SOL32M
IDT6168SA25L
IDT7164S2ooDM
IDT6168SA25P
IDT7198S35P
IDT7164S2ooL32M
IDT6168SA25D
IDT7198S45P
IDT6168SA35L
IDT7198S55P
IDT7164L1OODM
IDT6168SA35P
IDT7164L1ooL32M
IDT6168SA35D
IDT71257S45P
IDT7164L1SODM
IDT71257S55P
IDT7164L150L32M
IDT7164L70L32
IDT71258S45P
IDT7164L70P
IDT71258S55P
IDT7164L70S0

FAIRCHILD

lOT

F16ooDC45
F1600DMOB70
F1601DC70
F16ooLC45
F16ooLC70
F1601DMOB55
F1600DC55
F16ooLMOB70
F1601DMOB70
F1600DMOB55
F1601LC55
F1600LC55
F1601DC45
F1601 LC70
F1600LMOB55
F1601LC45
F1601LMOB55
F1600DC70
F1601DC55
F1601LMOB70

IDT7187S45C
IDT7187S70CB
IDT7187L70C
IDT7187S45L
IDT7187S70L
IDT7187L55CB
IDT7187S55C
IDT7187S70LB
IDT7187L70CB
IDT7187S55CB
IDT7187L55L
IDT7187S55L
IDT7187L45C
IDT7187L70L
IDT7187S55LB
IDT7187L45L
IDT7187L55LB
IDT7187S70C
IDT7187L55C
IDT7187L70LB

HARRIS

lOT

HM1-6516B-8
HM1-65162S-5
HM4-65262-8
HM4-65162-8
HM4-65262B-8
HM1-65162-8
HM4-65162C-8
HM1-65162B-8
HM4-65162S-5

IDT6116SA120DB
IDT6116LA55D
IDT6167SA70LB
IDT6116LA90DB
IDT6167SA70LB
IDT6116LA90DB
IDT6116SA90LB
IDT6116LA70DB
IDT6116LA55L

NOTES:
A lower case ·x· indicates the speed and/or
package of the part are unknown.·
*The CY7C161/162 come in a 300 mil package
vs. 400 milIDT71981/982.

HARRIS CONT.

lOT

HITACHI CONT.

lOT

HM1-65642-8
HM1-65162C-8
HM4-65642-8
HM1-65262-8
HM1-65262B-8

IDT7164L150DB
IDT6116SA90DB
IDT7164L150L32B
IDT6167SA70DB
IDT6167SA70DB

HM6789
HM6268LP-35
HM6789-30
HM6268P-25
HM6268P-35

IDT6198S25C
IDT6168LA35P
IDT6198S30C
IDT6168SA25P
IDT6168SA35P

HITACHI

lOT

INMOS

lOT

HM6116-2
HM62256LFP-10SL
HM6287CG-45
HM6116FP-2
HM62256LFP-8
HM6287CG-55
HM6116LFP-2
HM62256LP-10SL
HM6287CG-70
HM6116LP-2
HM62256LP-8
HM6287LP-45
HM6116P-2
HM62256P-8
HM6287LP-55
HM6287LP-70
HM6116ALP-12
HM6264FP-10
HM6287P-45
HM6116ALSP-12
HM6264LFP-10
HM6287P-55
HM6116AP-12
HM6264LFP-10L
HM6287P-70
HM6116ASP-12
HM6264LP-10
HM6264LP-10L
HM6288P-35
HM6167H-45
HM6264LP-10SL
HM6288P-45
HM6167H-55
HM6264P-10
HM6288P-55
HM6167HCG-45
HM6167HCG-55
HM6264AFP-12
HM65256AP-12
HM6167HLP-45
HM6264ALFP-12
HM6167HLP-55
HM6264ALSP-12
HM6716
HM6167HP-45
HM6264ASP-12
HM6716-30
HM6167HP-55
HM6267CG-35
HM6787
HM6168H-45
HM6267CG-45
HM6787-30
HM6168H-55
HM6267LP-35
HM6787CG
HM6168HLP-45
HM6267LP-45
HM6787CG-30
HM6168HLP-55
HM6267P-35
HM6168HP-45
HM6267P-45
HM6788
HM6168HP-55
HM6268LP-25

IDT6116SA90D
IDT71256L70P
IDT7187S45L
IDT6116SA90F
IDT71256L70S0
IDT7187S55L
IDT6116LA90S0
IDT71256L70P
IDT7187S70L
IDT6116LA90P
IDT71256L70P
IDT7187L45P
IDT6116SA90P
IDT71256S70P
IDT7187L55P
IDT7187L70P
IDT6116LA90P
IDT7164S70S0
IDT7187S45P
IDT6116LA90TP
IDT7164L70S0
IDT7187S55P
IDT6116LA90P
IDT7164L70S0
IDT7187S70P
IDT6116LA90TP
IDT7164L70P
IDT7164L70P
IDT7188S35P
IDT6167SA45D
IDT7164L70P
IDT7188S45P
IDT6167SA55D
IDT7164S70P
IDT7188S55P
IDT6167SA45L
IDT6167SA55L
IDT7164S70S0
IDT71256S70P
IDT6167LA45P
IDT7164L70S0
IDT6167LA55P
IDT7164L70TC
IDT6116SA25TD
IDT6167SA45P
IDT7164S70TC
IDT6116SA30TD
IDT6167SA55P
IDT6167SA35L
IDT7187S25C .
IDT6168SA45D
IDT6167SA45L
IDT7187S230C
IDT6168SA55D
IDT6167LA35P
IDT7187S25l22
IDT6168LA45P
IDT6167LA45P
IDT7187S30L22
IDT6168LA55P
IDT6167SA35P
IDT6168SA45P
IDT6167SA45P
IDT7188S25C
IDT6168SA55P
IDT61681A25P

IMS14ooP-35
IMS1420W-45
IMS16ooW-70
IMS14ooP-45
IMS1420W-55
IMS16ooW-70M
IMS14ooP-55
IMS1420W-55M
IMS1400P-70L
IMS1420W-70M
IMS1601S-55
IMS1400S-45
IMS1601S-70
IMS14ooS-45M
IMS1421S-40
IMS1601W-55
IMS14ooS-55
IMS1421S-SO
IMS1601W-70
IMS14ooS-55M
IMS1421W-40
IMS14ooS-70M
IMS1421W-SO
IMS1620S-45
IMS1400W-35
IMS1620S-55
IMS1400W-45
IMS1423P-25
IMS1620S-55M
IMS14ooW-45M
IMS1423P-35
IMS1620S-70
IMS14ooW-55
IMS1423P-45
IMS1620S-70M
IMS1400W-55M
IMS1423S-25
IMS1400W-70M
IMS1423S-35
IMS1624S-45
IMS1423S-35M
IMS1624S-55
IMS1403P-25
IMS1423S-45
IMS1624S-55M
IMS1403P-35
IMS1423S-45M
IMS1624S-70
IMS1403P-45
IMS1423S-55M
IMS1624S-70M
IMS1403P-55
IMS1423W-25
IMS1624W-45
IMS1403S-25
IMS1423W-35
IMS1624W-55
IMS1403S-35
IMS1423W-35M
IMS1624W-55M
IMS1403S-45
IMS1423W-45
IMS1624W-70
IMS1403S-55
IMS1423W-45M
IMS1624W-70M

IDT6167SA35P
IDT6168SA45L
IDT7187S70L
IDT6167SA45P
IDT6168SA55L
IDT7187S70LB
IDT6167SA55P
IDT6168SA55LB
IDT6167LA55P
IDT6168SA70LB
IDT7187L55C
IDT6167SA45D
IDT7187L70C
IDT6167SA45DB
IDT71681SA35C
IDT7187L55L
IDT6167SA55D
IDT71681 SA45C
IDT7187L70L
IDT6167SA55DB
IDT71681 SA35L
IDT6167SA70DB
IDT71681SA45L
IDT7188S45C
IDT6167SA35L
IDT7188S55C
IDT6167SA45L
IDT6168SA25P
IDT7188S55CB
IDT6167SA45LB
IDT6168SA35P
IDT7188S70C
IDT6167SA55L
IDT6168SA45P
IDT7188S70CB
IDT6167SA55LB
IDT6168SA25D
IDT6167SA70LB
IDT6168SA35D
IDT7198S45C
IDT6168SA35DB
IDT7198S55C
IDT6167SA25P
IDT6168SA45D
IDT7198S55CB
IDT6167SA35P
IDT6168SA45DB
IDT7198S70C
IDT6167SA45P
IDT6168SA55LB
IDT7198S70CB
IDT6167SA55P
IDT6168SA25L
IDT7198S45L
IDT6167SA25D
IDT6168SA35L
IDT7198S55L
IDT6167SA35D
IDT6168SA35LB
IDT7198S55LB
IDT6167SA45D
IDT6168SA45L
IDT7198S70L
IDT6167SA55D
IDT6168SA45LB
IDT7198S70LB

1-20

STATIC RAM CROSS REFERENCE GUIDE

INMOSCONT.
IMS1403W-25
IMS1423W-55M
IMS1403W-35
IMS1630S-45
IMS1403W-45
IMS1433x-35
IMS1630S-55
IMS1403W-55
IMS1630S-70
IMS16ooS-45
IMS1420P-45
IMS1600S-55
IMS18oox-35
IMS1420P-55
IMS16ooS-55M
IMS1420P-70L
IMS1600S-70
IMS1820P-35
IMS1420S-45
I MS16ooS-70M
IMS1820P-45
IMS1420S-55
IMS1600W-45
IMS1820P-55
IMS1420S-55M
IMS1600W-55
IMS1420S-70M
IMS1600W-55M
IMS1830x-45

lOT
IDT6167SA25L
IDT6168SA55LB
IDT6167SA35L
IDT7164S45D
IDT6167SA45L
IDT6116SA35
IDT7164S55D
IDT6167SA55L
IDT7164S70D
IDT7187S45C
IDT6168SA45P
IDT7187S55C
IDT71257S35x
IDT6168SA55P
IDT7187S55CB
IDT6168LA55P
IDT7187S70C
IDT71258S35P
IDT6168SA45D
IDT7187S70CB
IDT71258S45P
IDT6168SA55D
IDT7187S45L
IDT71258S55P
IDT6168SA55DB
IDT7187S55L
IDT6168SA70DB
IDT7187S55LB
IDT71256S45x

MITSUBISHI

lOT

M5M21 C67P-35
M5M5178P-45
M5M5188AP-25
M5M21 C67P-45
M5M5178P-55
M5M5188AP-35
M5M21 C67P-55
M5M5188P-45
M5M5187AD-25
M5M5188P-55
M5M21 C68P-35
M5M5187AD-35
M5M21 C68P-45
M5M5187AP-25
M5M5257P-35
M5M21 C68P-55
M5M5187AP-35
M5M5257P-45
M5M5187P-45
M5M5257P-55
M5M5165FP-70
M5M5187P-55
M5M5165FP-70L
M5M5258P-35
M5M5188AD-25
M5M5258P-45
M5M5188AD-35
M5M5258P-55

IDT6167LA35P
IDT7164L45P
IDT7188L25P
IDT6167LA45P
IDT7164L55P
IDT7188L35P
IDT6167LA55P
IDT7188L45P
IDT7187L25L22
IDT7188L55P
IDT6168LA35P
IDT7187L35L22
IDT6168LA45P
IDT7187L25P
IDT71257S35P
IDT6168LA55P
IDT7187L35P
IDT71257S45P
IDT7187L45P
IDT71257S55P
IDT7164S70S0
IDT7187L55P
IDT7164L70S0
IDT71258S35P
IDT7188L25L22
IDT71258S45P
IDT7188L35L22
IDT71258S55P

MOTOROLA

lOT

MCM2016P45
MCM6168P35
MCM6287P35
MCM2016P55
MCM6168P45
MCM6287P45

IDT6116SA45P
IDT6168SA35P
IDT7187S35P
IDT6116SA55P
IDT6168SA45P
IDT7187S45P

NOTES:
A lower case ·x· indicates the speed and/or
package of the part are unknown.·
*The CY7C161/162 come in a 300 mil package
vs. 400 milIDT71981/982.

MOTOROLA

lOT

SARATOGA CONT.

lOT

MCM2016P70
MCM6168P55
MCM6287P25
MCM6168P70
MCM2167P45
MCM6288P25
MCM2167P55
MCM6268P25
MCM6288P35
MCM2167P70
MCM6268P35
MCM6288P45
MCM6268P45
MCM6164P45
MCM6268P55
MCM6164P55
MCM6164P70

IDT6116SA70P
IDT6168SA55P
IDT7187S25P
IDT6168SA70P
IDT6167SA45P
IDT7188S25P
IDT6167SA55P
IDT6168SA25P
IDT7188S35P
IDT6167SA70P
IDT6168SA35P
IDT7188S45P
IDT6168SA45P
IDT7164S45P
IDT6168SA55P
IDT7164S55P
IDTI'164S70P

SSM6172L-25
SSM6168-25
SSM7188-25
SSM6168L-20
SSM7161-25
SSM7188L-25
SSM6168L-25
SSM7161 L-25
SSM7198-25
SSM7198L-25

IDT71682L25D
IDT6168SA25D
IDT7188S25C
IDT6168LA20D
IDT71981S25C
IDT7188L25C
IDT6168LA25D
IDT71981L25C
IDT7198S25C
IDT7198L25C

SONY

lOT

CXK5416P-35
CXK5814P-35
CXK58256P-10
CXK5416P-45
CXK5814P-45
CXK58256M-10
CXK5416P-55
CXK5814P-55
CXK5864AP-70L
CXK5464P-45
CXK5818PN-10
CXK5864AM-70L
CXK5464P-55
CXK5818M-10
CXK5464P-70
CXK5865P-45L
CXK5865P-55L

IDT6168LA35P
IDT6116LA35TP
IDT71256L70P
IDT6168LA45P
IDT6116LA45TP
IDT71256L70S0
IDT6168LA55P
IDT6116LA55TP
IDT7164L70P
IDT7188L45P
IDT6116L90P
IDT7164L70S0
IDT7188L55P
IDT6116L90S0
IDT7188L70P
IDT7164L45P
IDT7164L55P

VITELIC

lOT

V61C16P35
V61C34P90
V61C67P35
V61C16P35L
V61C67P35L
V61C16P45
V61C62P45
V61C67P45
V61C16P45L
V61C62P45L
V61C67P45L
V61C16P55
V61C62P55
V61C67P55
V61C16P55L
V61C62P55L
V61C67P55L
V61C16S35
V61C62P70
V61C16S35L
V61C62P70L
V61C68P35
V61C16S45
V61C68P35L
V61C16S45L
V61C64P45
V61C68P45
V61C16S55
V61C64P45L
V61C68P45L
V61C16S55L
V61C64P55
V61C68P55
V61C64P55L
V61C68P55L
V61C32P70
V61C64P70
V61C32P70L
V61C64P70L
V61C32P90
V61C32P90L

IDT6116SA35P
IDT71322S90P
IDT6167SA35P
IDT6116LA35P
IDT6167LA35P
IDT6116SA45P
IDT7188S45P
IDT6167SA45P
IDT6116LA45P
IDT7188L45P
IDT6167LA45P
IDT6116SA55P
IDT7188S55P
IDT6167SA55P
IDT6116LA55P
IDT7188L55P
IDT6167LA55P
IDT6116SA35TP
IDT7188S70P
IDT6116LA35TP
IDT7188L70P
IDT6168SA35P
IDT6116SA45TP
IDT6168LA35P
IDT6116LA45TP
IDT7164S45P
IDT6168SA45P
IDT6116SA55TP
IDT7164L45P
IDT6168LA45P
IDT6116LA55TP
IDT7164S55P
IDT6168SA55P
IDT7164L55P
IDT6168LA55P
IDT7132SA70P
IDT7164S70P
IDT7132LA70P
IDT7164L70P
IDT7132SA90P
IDT7132LA90P

NEC

lOT

5PD4311C-35
5PD43256G-10
5PD4362C-45
5PD4311C-45
5PD43256G-10L
5PD4362C-55
5PD4311 C-55
5PD4362C-70
5PD4311D-35
5PD4361 C-45
5PD4311 D-45
5PD4361 C-45L
5PD4364C-12
5PD4311 D-55
5PD4361 C-55
5PD4364C-12L
5PD4361 C-55L
5PD4364G-12
5PD4314C-35
5PD4361C-70
5PD4364G-12L
5PD4314C-45
5PD4361 C-70L
5PD4314C-55
5PD4361 K-40
5PD446C
5PD4361 K-45
5PD43256C-10
5PD4361 K-55
5PD4464C-x
5PD43256C-10L
5PD4464G-x

IDT6167SA35P
IDT71256S70S0
IDT7188SA45P
IDT6167SA45P
IDT71256L70S0
IDT7188SA55P
IDT6167SA55P
IDT7188SA70P
IDT6167SA35D
IDT7187S45P
IDT6167SA45D
IDT7187L45P
IDT7164S70P
IDT6167SA55D
IDT7187S55P
IDT7164L70P
IDT7187L55P
IDT7164S70S0
IDT6168SA35P
IDT7187S70P
IDT7164L70S0
IDT6168SA45P
IDT7187L70P
IDT6168SA55P
IDT7187S35L22
IDT6116LA70P
IDT7187S45L22
IDT71256S70P
IDT7187S55L22
IDT7164L70P
IDT71256L70P
IDT7164L70S0

SARATOGA

lOT

SSM6116-25
SSM6171-20
SSM7162-25
SSM6116L-25
SSM6171-25
SSM7162L-25
SSM6171 L-20
SSM6167-20
SSM6171L-25
SSM7164-25
SSM6167-25
SSM7164L-25
SSM6167L-20
SSM6172-20
SSM6167L-25
SSM6172-25
SSM7187-25
SSM6172L-20
SSM7187L-25
SSM6168-20

IDT6116SA25TD
IDT71681S20D
IDT71982S25C
IDT6116LA25TD
IDT71681 S25D
IDT71982L25C
IDT71681L20D
IDT6167SA20D
IDT71681L25D
IDT7164S25TC
IDT6167SA25D
IDT7164L25TC
IDT6167LA20D
IDT71682S20D
IDT6167LA25D
IDT71682S25D
IDT7187S25C
IDT71682L20D
IDT7187L25C
IDT6168SA2QD

1-21

STATIC RAM CROSS REFERENCE GUIDE

VTI

lOT

vr16H4-35
vr20C69-20
VT7132-55
vr16H4-45
vr20C69-25
VT7132-70
vr16H4-55

IDT71981-35
IDT6169SA20P
IDT7132SA55D
IDT71981-45
IDT6169SA25P
IDT7132SA70D
IDT71981-55
IDT6169SA35P
IDT7132SA90D
IDT6169SA45P
IDT7132SA35D
ITD6116SA20TP
IDT7132SA45D
ITD6116SA25TP
IDT7130SA1ooP
ITD6116SA35TP
IDT7142SA55D
IDT7188S25P
IDT7142SA70D
IDT6120SA20TP
IDT7188S35C
IDT7142SA90D
IDT6120SA25TP
IDT7188S45C
IDT7142SA35D
IDT6120SA35TP
IDT7188S55C
IDT7142SA45D
IDT6168SA20P
IDT6168SA25P
IDT6168SA35P
IDT6168SA45P

vr20C69-35
VT7132-90

vr20C69-45
VT7132A-35

vr20C18-20
VT7132A-45

vr20C18-25
vr2130
vr20C18-35
VT7142-55
vr65KS4-25
VT7142-70

vr20C19-20
vr65KS4-35CC
VT7142-90

vr20C19-25
vr65KS4-45CC
VT7142A-35

vr20C19-35
vr65KS4-55CC
VT7142A-45

vr20C68-20
vr20C68-25
vr20C68-35
vr20C68-45

NOTES:
A lower case ·x· indicates the speed and/or
package of the part are unknown.·
*The CY7C161/162 come in a 300 mil package
vs. 400 milIDT71981/982.

1-22

AMTEL

lOT

AT28C16A-15
AT28C16A-20
AT28C16A-25
AT28C16A-30
AT28C16A-35

IDT78C16A-150
IDT78C16A-200
IDT78C16A-250
IDT78C16A-300
IDT78C16A-350

EXEL

lOT

XLS2816AL-250
XLS2816AL-300
XLS2816AL-350

IDT78C16A-250
IDT78C16A-300
IDT78C16A-350

SEEQ

lOT

2816A-200
2816A-250
2816A-300
2816A-350

IDT78C16A-200
IDT78C16A-250
IDT78C16A-300
IDT78C16A-350

XICOR

lOT

X2816A-20
X2816A-25
X2816A-30
X2816A-35

IDT78C16A-200
IDT78C16A-250
IDT78C16A-300
IDT78C16A-350

1-23

FUNCTIONAL REPLACEMENTS
CYPRESS
7C901-23DC
7C901-23PC
7C901-27DMB
7C901-27LMB
7C901-31DC
7C901-31JC
7C901-31PC
7C901-32DMB
7C901-32LMB
7C909-30DC
7C909-30DMB
7C909-30PC
7C909-40DC
7C909-40DMB
7C909-40LMB
7C909-40PC
7C910-40DC
7C910-40JC
7C910-40PC
7C910-46DMB
7C910-50DC
7C910-50JC
7C910-50PC
7C910-51DMB
7C910-51LMB
7C9101-30DC

7C9101-30GC
7C9101-30JC
7C9101-30PC
7C9101-35DMB

7C9101-35GMB
7C91 01-35LM B
7C9101-40DC

.

7C9101-40GC
7C9101-40JC
7C9101-40PC

.

7C9101-45DMB
7C9101-45GMB
7C9101-45LMB
7C911-30DC
7C911-30DMB
7C911-30PC
7C911-40DC
7C911-40DMB
7C911-40LMB
7C911-40PC

lOT
IDT39C01DD
IDT39C01DP
IDT39C01 DDB
IDT39C01DLB
IDT39C01CD

-

IDT39C01CP
IDT39C01CDB
IDT39C01CLB
IDT39C09BD
IDT39C09BDB
IDT39C09BP
IDT39C09AD
IDT39C09ADB
IDT39C09ALB
IDT39C09AP
IDT39C10CD
IDT39C10CJ
IDT39C1OCP
IDT39C10CDB
IDT39C10BD
IDT39C10BJ
IDT39C10BP
IDT39C10BDB
IDT39C10BLB
IDT49C401AC
IDT49C402AG
IDT49C402AXC

-

IDT49C402AL
IDT49C401AC
IDT49C402AG
IDT49C402AXC
IDT49C401 ACB
IDT49C402AXCB
IDT49C402AGB

-

IDT49C402ALB
IDT49C401C
IDT49C402G
IDT49C402XC

-

IDT49C401C
IDT49C402G
IDT49C402XC
IDT49C401CB
IDT49C402GB
IDT49C402XCB

-

IDT49C402LB
IDT39C11BD
IDT39C11 BDB
IDT39C11BP
IDT39C11AD
IDT39C11ADB
IDT39C11ALB
IDT39C11AP

NOTE:
BOLD FACE ITEMS ARE
FUNCTIONAL REPLACEMENTS.

AMD

lOT

Am2901 C/BQA
Am2901 C/BUC
Am2901 C/BYC
Am2901 CDC
Am2901CDCB
Am2901CLC
Am2901CPC
Am2901CPCB
Am2903A1BXC
Am2903A/BYC
Am2903A1LMC
Am2903ADC
Am2903ADCB
Am2903ALC
Am2909A/BXA
Am2909A/BYA
Am2909A1B3C
Am2909ADC
Am2909ADCB
Am2909ALC
Am2909APC
Am2909APCB
Am2910AlBQA
Am2910AlBUC
Am2910AlBYC
Am2910ADC
Am2910ADCB
Am2910ALC
Am2910APC
Am2910APCB
Am29C10A-10DC
Am29C10A-10PC
Am29C10A-10PCB
Am29C101DC

IDT39C01 CDB
IDT39C01 CLB

Am29C101PC

.

Am29C101JC
Am2911 AlBRA
Am2911 A/BUC
Am2911 A/B2C
Am2911ADC
Am2911ADCB
Am2911ALC
Am2911APC
Am2911APCB
Am29203/BXC
Am29203DC
Am29203DCB
Am2960/BUC
Am2960/BXC
Am2960DC
Am2960DCB
Am2960LC
Am2960PC
Am2960PCB
Am2960JC
Am2960JCB
Am2960-1/BXC
Am2960-1/BUC
Am2960-1/BYC
Am2960-1PC
Am2960-1 PCB

-

IDT39C01CD
IDT39C01CD
IDT39C01CL
IDT39C01CP
IDT39C01CP
IDT39C03ACB

IDT39C03ALB
IDT39C03AC
IDT39C03AC
IDT39C03AL
IDT39C09ADB

-

IDT39C09ALB
IDT39C09AD
IDT39C09AD
IDT39C09AL
IDT39C09AP
IDT39C09AP
IDT39C10BDB
IDT39C10BLB

-

IDT39C10BD
IDT39C10BD
IDT39C10BL
IDT39C10BP
IDT39C10BP
IDT39C10BD
IDT39C10BP
IDT39C10BP
IDT49C401C
IDT49C402G
IDT49C402XC
IDT49C401C
IDT49C402G
IDT49C402XC

-

IDT39C11ADB
IDT39C11ALB
IDT39C11 ALB
IDT39C11AD
IDT39C11AD
IDT39C11AL
IDT39C11AP
IDT39C11AP
IDT39C203CB
IDT39C203C
IDT39C203C
IDT39C60LB
IDT39C60CB
IDT39C60C
IDT39C60C
IDT39C60L
IDT39C60P
IDT39C60P
IDT39C60J
IDT39C60J
IDT39C60-1CB
IDT39C60-1 LB

-

IDT39C60-1 P
IDT39C60-1 P

1-24

AMD CONT.

lOT

Am2960-1LC
Am2960-1JC
Am2960-1JCB
Am2960-1DC
Am2960-1DCB
Am2960ADC
Am2960ADCB
Am2960APC
Am2960APCB
Am29705/BXA
Am29705/BYA
Am29705/B3C
Am29705DC
Am29705DCB
Am29705LC
Am29705PC
Am29705PCB
Am29707DC
Am29707DCB
Am29707LC
Am29707PC
Am29707PCB

IDT39C60-1L
IDT39C60-1J
IDT39C60-1J
IDT39C60-1 C
IDT39C60-1C
IDT39C60AC
IDT39C60AC
IDT39C60AP
IDT39C60AP
IDT39C705ADB

TI

lOT

-

IDT39C705ALB
IDT39C705AD
IDT39C705AD
IDT39C705AL
IDT39C705AP
IDT39C705AP
IDT39C707D
IDT39C707D
IDT39C707L
IDT39C707P
IDT39C707P

SN54174ALS632A!3/4/SJD IDT49C460G
IDT49C460XC
SN54174ALS632A!3/4/5FN IDT49C46OJ
SN54174ALS632BJD
IDT49C460AG
IDT49C460AXC
SN54174ALS632BFN
IDT49C460AJ
SN54174AS632AJD
IDT49C460AG
IDT49C460AXC
SN54174AS632AFN
IDT49C460AJ

MOTOROLA

lOT

MC74F2960J
MC74F2960-1J
MC74F2960AJ

IDT39C60P
IDT39C60-1P
IDT39C60AP

NATIONAL

lOT

DP8402AD
DP8402AV
DP8403D

IDT49C460XC
IDT49C460J
IDT49C460XC
IDT49C460G
IDT49C460J
IDT49C460XC
IDT49C460G
IDT49C46OJ
IDT49C460XC
IDT49C460G

DP8403V
DP8404D
DP8404V
DP8405D

SIGNETICS

lOT

N2960

IDT39C60P

AMO

lOT

ANALOG CONT.

lOT

CYPRESS CONT.

29C509/BXC
29C509/BXC
29C509DC
29510
29510DC
29510DCB
29510XC
29L510/BXC
29L510DC
29L510DCB
29516
29516/BYC
29516/DMC
29516ADC
29516ADCB
29516ALC
29516AXC
29516DC
29516DCB
29516LC
29516XC
29L516/BXC
29L516/BYC
29L516DC
29L516DCB
29L516JC
29L516LC
29L516LMB
29L516PC
29L516PCB
29L516XC
29517
29517/BYC
29517/DMC
29517/LMC
29517ADC
29517ALC
29517AXC
29517DC
29517DCB
29517LC
29517XC
29L517/BXC
29L517DC
29L517DCB
29L517JC
29L517LC
29L517LMB
29L517PC
29L517PCB
29L517XC

7209
7209L90CB
7209L70C
7210
7210L75C
7210L75C
7210LU
7210Ll20CB
721 OL1 OOC
7210L100C
7216
7216L75FB
7216L75CB
7216L35C
7216L35C
7216L35L
7216LU
7216L65C
7216L65C
7216L65L
7216LU
7216L90CB
7216L90FB
7216L90C
7216L90C
7216L90J
7216L90L
7216L90LB
7216L90P
7216L90P
7216LU
7217
7217L75FB
7217L75CB
7217L75LB
7217L35C
7217L35L
7217LU
7217L65C
7217L65C
7217L65L
7217LU
7217L90CB
7217L90C
7217L90C
7217L90J
7217L90L
72176L90LB
7217L90P
7217L90P
7217LU

ADSP-1009SD
ADSP-1009TD
ADSP-1012
ADSP-1012
ADSP-1012JD ,
ADSP-1012KD
ADSP-1012SD
ADSP-1012TD
ADSP-1010
ADSP-1010AKD
ADSP-1010AKG
ADSP-1010JD
ADSP-1010JG
ADSP-1010KD
ADSP-1010KG
ADSP-1010SD
ADSP-1010SG
ADSP-1010TD
ADSP-1010TG
ADSp·1016
ADSP-1016AKD
ADSP-1016AKG
ADSP-1016JD
ADSP-1016JG
ADSP-1016KD
ADSP-1016KG
ADSP-1016SD
ADSP-1016SG
ADSP-1016TD
ADSP-1016TG

7209L170CB
7209L170CB
7212
7212
7212L115C
7212LL115C
7212L140CB
7212L140CB
7210
7210L75C
7210L75G
7210L165C
7210L165G
7210L165C
7210L165G
7210L200CB
7210L200GB
7210L200CB
7210L200GB
7216
7216L75C
7216L75G
7216L140C
7216L140G
7216L140C
7216L140G
7216L185CB
7216L185GB
7216L120CB
7216L120GB

CYPRESS

lOT

7C403-15DMB
7C403-15LC
7C403-15LMB
7C403-15PC
7C403-25DC
7C403-25DMB
7C403-25LC
7C403-25LMB
7C403-25PC
7C404
7C404-10DC
7C404-10DMB
7C404-10LC
7C404-10LMB
7C404-10PC
7C404-15DC
7C404-15DMB
7C404-15LC
7C404-15LMB
7C404-15PC
7C404-25DC
7C404-25DMB
7C404-25LC
7C404-25LMB
7C404-25PC
7C510
7C510-45DC
7C510-45GC
7C510-45LC
7C510-45PC
7C510-55DC
7C510-55DMB
7C510-55GC
7C510-55GMB
7C510-55LC
7C510-55LMB
7C51 0-55 PC
7C510-65DC
7C510-65DMB
7C510-65GC
7C510-65GMB
7C510-65LC
7C510-65LMB
7C51 0-65 PC
7C510-75DC
7C510-75DMB
7C510-75GC
7C510-75GMB
7C510-75LC
7C510-75LMB
7C510-75PC
7C516
7C516-38DC
7C516-38GC
7C516-38LC
7C516-38PC
7C516-42DMB
7C516-42GMB
7C516-42LMB
7C516-45DC
7C516-45GC
7C516-45LC

ANALOG DEVICES
ADSP·1009
ADSP-1009JD
ADSP-1009KD

lOT
7209
7209L135C
7209L135C

NOTE:
BOLD FACE ITEMS ARE
FUNCTIONAL REPLACEMENTS

7C401
7C401-10DC
7C40HODMB
7C401-10LC
7C401-10LMB
7C401-10PC
7C401-15DC
7C401-15DMB
7C401-15LC
7C401-15LMB
7C401-15PC
7C402
7C402-10DC
7C402-10DMB
7C402-10LC
7C402-10LMB
7C402-10PC
7C402-15DC
7C402-15DMB
7C402-15LC
7C402-15LMB
7C402-15PC
7C403
7C403-10DC
7C403-10DMB
7C403-10LC
7C403-10LMB
7C403-10PC
7C403-15DC

72401
72401L10D
74201L10DB
72401L10L
72401L10LB
72401L10P
72401L15D
72401L15DB
72401L15L
72401L15LB
72401L15P
72402
72402L10D
72402L10DEl
72402L10L
72402L10LB
72402L10P'
72402L15D
72402L15DB
72402L15L
72402L15LB
72402L15P
72403
72403L10D
72403L10DB
72403L10L
72403L10LB
72403L10P
72403L15D

1-25

lOT
72403L15DB
72403L15L
72403L15LB
72403L15P
72403L25D
72403L25DB
72403L25L
72403L25LB
72403L25P
72404
72404L10D
72404L10DB
72404L10L
72404L10LB
72404L10P
72404L15D
72404L15DB
72404L15L
72404L15LB
72404L15P
72404L25D
72404L25DB
72404L25L
72404L25LB
72404L25P
7210
7210L45D
7210L45G
7210L45L
7210L45P
7210L55D
7210L55DB
7210L55G
7210L55GB
7210L55L
7210L55LB
7210L55P
7210L65D
7210L65DB
7210L65G
7210L65GB
7210L65L
7210L65LB
7210L65P
7210L75D
7210L75DB
7210L75G
7210L75GB
7210L75L
7210L75LB
7210L75P
7216
7216L35D
7216L35G
7216L35L
7216L35P
7216L40DB
7216L40GB
7216L40LB
7216L45D
7216L45G
7216L45L

DIGITAL SIGNAL PROCESSING CROSS REFERENCE GUIDE

CYPRESS CO NT.

lOT

MMI CO NT.

7C516-45PC
7C516-55DC
7C516-55DMB
7C516-55GC
7C516-55GMB
7C516-55LC
7C516-55LMB
7C516-55PC
7C516-65DC
7C516-65DMB
7C516-65GC
7C516-65GMB
7C516-65LC
7C516-65LMB
7C516-65PC
7C516-75DC
7C516-75DMB
7C516-75GC
7C516-75GMB
7C516-75LC
7C516-75LMB
7C516-75PC
7C517
7C517-45DC
7C517-45GC
7C517-45LC
7C517-45PC
7C517-55DC
7C517-55DMB
7C517-55GC
7C517-55GMB
7C517-55LC
7C517-55LMB
7C517-55PC
7C517-65DC
7C517-65DMB
7C517-65GC
7C517-65GMB
7C517-65LC
7C517-65LMB
7C517-65PC
7C517-75DC
7C517-75DMB
7C517-75GC
7C517-75GMB
75C17-75LC
7C517-75LMB
7C517-75PC

7216L45P
7216L55D
7216L55DB
7216L55G
7216L55GB
7216L55L
7216L55LB
7216L55P
7216L65D
7216L65DB
7216L65G
7216L65GB
7216L65L
7216L65LB
7216L65P
7216L75D
7216L75DB
7216L75G
7216L75GB
7216L75L
7216L75LB
7216L75P
7217
7217L45D
7217L45G
7217L45L
7217L45P
7217L55D
7217L55DB
7217L55G
7217L55GB
7217L55L
7217L55LB
7217L55P
7217L65D
7217L65DB
7217L65G
7217L65GB
7217L65L
7217L65LB
7217L65P
7217L75D
7217L75DB
7217L75G
7217L75GB
7217L75L
7217L75LB
7217L75P

MMI

lOT

67401BJ
67401J
67401N
C57401AJB
C57401BJB
C57401JB
C57L401DJB
C67401AJ
C67401AN
C67401BJ
C67401J
C67401N
C67L401DJ
C67L401DN
67402
57402AJB
57402BJB·
57402JB
67402AJ
67402AN
67402BJ
67402J
67402N
C57402AJB
C57402BJB
C57402JB
C57L402DJB
C67402AJ
C67402AN
C67402BJ
C67402J
C67402N
C67L402DJ
C67L402DN
67411
57411JB
67411AJ
67411J
67412
57412JB
67412AJ
67412J
67413
57413JB
67413AJ
67413J
67C401
67C401-10N
67C401-10J
67C401-15N
67C401-15J
67C4013
67C4013-10N
67C4013-10J
67C4013-15N
67C4013-15J
67C402
67C402-10N
67C402-10J
67C402-15N
67C402-15J
67C4013

67401
57401AJB
57401BJB
57401JB
67401AJ
67401 AN

72401
72401L15DB
72401L25DB
72401L10DB
72401L15D
72401L15P

NOTE:
BOLD FACE ITEMS ARE
FUNCTIONAL REPLACEMENTS

lOT
72401L25D
72401L10D
72401L10P
72401L15DB
72401L25DB
72401L10DB
72401L15DB
72401L15D
72401L15P
72401L25D
72401L10D
72401L10P
72401L15D
72401L15P
72402
72402L15DB
72402L25DB
72402L10DB
72402L15D
72402L15P
72402L25D
72402L10D
72402L10P
72402L15DB
72402L25DB
72402L10DB
72402L15DB
72402L15D
72402L15P
72402L25D
72402L10D
72402L10P
72402L15D
72402L15P
72401
72401L25DB
72401L35D
72401L25D
72402
72402L25DB
72402L35D
72402L25D
72413
72413L25DB
72413L35D
72413L25D
72401
72401L10P
72401L10D
72401L15P
72401L15D
72403
72403L10P
72403L10D
72403L15P
72403L15D
72402
72402L10P
72402L10D
72402L15P
72402L15D
72404

1-26

MMI CONT.

lOT

67C4023-10N
67C4023-10J
67C4023-15N
67C4023-15J

72404L10P
72404L10D
72404L15P
72404L15D

THOMSON-MOSTEK

lOT

MK4501
MK4501-10N
MK4501-12N
MK4501-65N
MK4501-SN
MK4503
MK4503-10N
MK4503-12N
MK4503-65N
MK4503-SN

7201
7201SS0P
7201S120P
7201S65P
7201SS0P
7203
7203SS0P
7203S120P
7203S65P
7203S80P

TRW

lOT

MPY012
MPY012HJ1A
MPY012HJ1C
MPY012HJ1G
MPY016.
MPY016HJ1A
MPY016HJ1C
MPY016HJ1C
MPY016KJ1A
MPY016KJ1A1
MPY016KJ1C
MPY016KJ1C1
MPY016KJ1G
MPY016KJ1G1
TMC216H·
TMC216HC1A
TMC216HC1C
TMC216HC1G
TMC216HJ3A
TMC216HJ3C
TMC216HJ3G
TDC1009
TDC1009C1A
TDC1009C1F
TDC1 009J1 A
TDC1009J1C
TDC1009J1F
TDC1009J1G
TDC1010
TDC1010C1A
TDC1010C1F
TDC1010J1A
TDC1010J1C
TDC1010J1F
TDC1010J1G
TDC1043
TDC1043C1C
TDC1043C1G
TDC1043J3C
TDC1043J3G
TMC2009

7212
7212L140CB
7212L115C
7212Ll15C
7216
7216L1S5CB
7216L140C
7216L140C
7216L45CB
7216L45CB
7216L45C
7216L35C
7216L45C
7216L35C
7216
7216L185LB
7216L140L
7216L140L
7216L1S5CB
7216L140C
7216L140C
7209
7209170LB
7209L170LB
7209L170CB
7209L135C
7209L170CB
7209L135C
7210
7210L200LB
7210L200LB
7210L200CB
7210L165C
7210L200CB
7210L165C
7243
7243L100L
7243L100L
7243L100C
7243L100C
7209

DIGITAL SIGNAL PROCESSING CROSS REFERENCE GUIDE

TRWCONT.

IDT

WEITEK

lOT

WEITEK CONT.

lOT

TMC2009C1A
TMC2009C1C
TMC2009C1F
TMC2009C1G
TMC2009J3A
TMC2009J3C
TMC2009J3F
TMC2009J3G
TMC2010
TMC2010C1C
TMC2010C1C
TMC2010C1F
TMC2010C1G
TMC2010J3A
TMC2010J3C
TMC2010J3F
TMC2010J3G
TMC2110
TMC2110C1C
TMC2110C1C
TMC2110C1F
TMC2110C1G
TMC2110J3C
TMC2110J3C
TMC2110J3F
TMC2110J3G
TMC1043
TDC1043C1C
TDC1043C1G
TDC1043J3C
TDC1043J3G
TMC2009
TMC2009C1A
TMC2009C1C
TMC2009C1F
TMC2009C1G
TMC2009J3A
TMC2009J3C
TMC2009J3F
TMC2009J3G
TMC2010
TMC2010C1C
TMC2010C1C
TMC2010C1F
TMC2010C1G
TMC2010J3A
TMC2010J3C
TMC2010J3F
TMC201OJ3G
TMC2110
TMC2110C1C
TMC2110C1C
TMC2110C1F
TMC2110C1G
TMC2110J3C
TMC2110J3C
TMC211OJ3F
TMC2110J3G

7209L170LB
7209L135L
7209L120LB
7209L135L
7209L170CB
7209L135C
7209L120CB
7209L135C
7210
7210L165L
7210L200LB
7210L200LB
7210L165L
7210L200CB
7210L165C
7210L200CB
7210165C
7210
7210L100L
7210L120LB
7210L120LB
7210L100L
721 OL1 OOC
7210L120CB
7210L120CB
7210L100C
7243
7243L100L
7243L100L
7243L100C
7243L100C
7209
7209L170LB
7209L135L
7209L120LB
7209L135L
7209L170CB
7209L135C
7209L120CB
7209L135C
7210
7210L165L
7210L200LB
7210L200LB
7210L165L
7210L200CB
7210L165C
7210L200CB
7210L165C
7210
7210L100L
7210L120LB
7210L120LB
7210L100L
7210L100C
7210L120CB
7210L120CB
7210L100C

WTL2010
WTL2010AGCD
WTL2010AGMD
WTL2010AJC
WTL2010AJC
WTL2010AJM
WTL2010ALCC
WTL2010ALMC
WTL2010BGCD
WTL2010BGMD
WTL2010BJC
WTL2010BJM
WTL2010BLCC
WTL2010BLMC
WTL2010GCD
WTL2010GMD
WTL2010JC
WTL2010JM
WTL2010LCC
WTL2010LMC
WTL2016
WTL2016AGCD
WTL2016AGMD
WTL2016AJC
WTL2016AJM
WTL2016ALCC
WTL2016ALMC
WTL2016BGCD
WTL2016BGMD
WTL2016BJC
WTL2016BJM
WTL2016BLCC
WTL2016BLMC
WTL2016CGCD
WTL2016CGMD
WTL2016CJC
WTL2016CJM
WTL2016CLCC
WTL2016CLMC
WTL2016GCD
WTL2016GMD
WTL2016JC
WTL2016JM
WTL2016LCC
WTL2016LMC
WTL2017
WTL2017AGCD
WTL2017AGMD
WTL2017AJC
WTL2017AJM
WTL2017ALCC
WTL2017ALMC
WTL2017BGCD
WTL2017BGMD
WTL2017BJC
WTL2017BJM
WTL2017BLCC
WTL2017BLMC
WTL2017CGCD
WTL2017CGMD
WTL2017CJC
WTL2017CJM

7210
7210L65G
7210L75GB
7210L65C
7210L65C
7210L75CB
7210L65L
7210L75LB
7210L45G
7210L55GB
7210L45C
7210L55CB
7210L45L
7210L55LB
7210L100G
7210L120GB
7210L100C
7210L120CB
721 OL1 OOL
7210L120LB
7216
7216L65G
7216L75GB
7216L65C
7216L75CB
2716L65L
7216L75LB
7216L45G
7216L55GB
7216L45C
7216L55CB
7216L45L
7216L55LB
7216L35G
7216L45GB
7216L35C
7216L45CB
7216L35L
7216L45LB
7216L90G
7216L120GB
7216L90C
7216L120CB
7216L90L
7216L120LB
7217
7217L65G
7217L75GB
7217L65C
7217L75CB
7217L65L
7217L75LB
7217L45G
7217L55GB
7217L45C
7217L55CB
7217L45L
7217L55LB
7217L35G
7217L45GB
7217L35C
7217L45CB

WTL2017CLCC
WTL2017CLMC
WTL2017GCD
WTL2017GMD
WTL2017JC
WTL2017JM
WTL2017LCC
WTL2017LMC
WTL1264
WTL1264GCD
WTL1265
WTL1265GCD

7217L35L
7217L45LB
7217L90G
7217L120GB
7217L90C
7217L120CB
7217L90L
7217L120LB
721264
721264L60G
721265
721265L60G

NOTE:
BOLD FACE ITEMS ARE
FUNCTIONAL REPLACEMENTS

1-27

EXACT PIN REPLACEMENTS
TRW

lOT

TDC1018
TDC1048

IDT75C18
IDT75C48

HONEYWELL

lOT

HDAC10180

IDT75C18

SONY

lOT

CXA1096P

IDT78C48

BROOKTREE

lOT

BT458

IDT78C458

FUNCTIONAL EQUIVALENTS
PART NO.

lOT
IDT75C18
IDT75C18
IDT75C18
IDT75C18
IDT75C18
IDT75C18
IDT75C48
IDT75C48
IDT75C18
IDT75C18
IDT75C48
IDT75C48
IDT75C48
IDT75C48
IDT75C48
IDT75C18
IDT75C18
IDT75C48
IDT75C48
IDT75C18
IDT78C18
IDT75C18
IDT75C18
IDT75C48
IDT75C48
IDT75C18
IDT75C18
IDT75C18
IDT75C18
IDT75C18

AD9700
AD9768
BT101
BT102
BT106
BT108
CA3308
CX20052
EDH-10605
EDH-10805
HA19209
HA19210
MB40548
MC10318
MC10319
MN0605
MN0805
MP7683
MP7684
PNA7518
RGB-DAC83
SDA8005
SP9768
T1595
TML1080
TML1840
VOAC-0605
VOAC-0805H
VOAC-888E
VOAC-888T

1-28

EDI

lOT

EDHSMS12SC100
EDHSMS12SC120
EDHSMS12SC150
EDHSMS12SC100CB*
EDHSMS12SC120CB*
EDHSMS12SC150CB*
EDHS1 H256C-55
EDHS1 H256C-70
EDHS16H64C-55*
EDHS16H64C-70*
EDHS4H64C-55
EDHS4H64C-70
EDH880SHC-55*
EDHSSOSHC-70*
EDHSSOSA-10*
EDHSSOSA-12*
EDHSSOSA-15*
EDH880SC-10*
EDH880SC-12*
EDHSSOSC-15*
EDHSSOSCL-20*
EDHSSOSCL-25*
ED HSSOSAL-20*
EDHSSOSAL-25*
EDHSS32C-12
EDHSS32C-15
EDH8832C-20
EDHSS32C-12*
EDHSS32C-15*
EDHSS32C-20*
EDH8832HC-70*
EDHSS32HC-S5*

SMS24L100C
SMS24L100C
SMS24L100C
SMS24S100CB
SMS24S100CB
SMS24S100CB
SM156S55CS
SM156S70CS
7M624S55CB
7M624S65CB
SMP456S55S
SMP456S70S
8M864L55CB
8M864L75CB
7MS64LS5CB
7MS64L120CB
7MS64L15OCB
SMS64LS5CB
SMS64L120CB
SMS64L15OCB
SMS64L150CB
SMS64L150CB
7MS64L150CB
7MS64L150CB
SMS56LS5C
SMS56LS5C
SMS56LS5C
SMS56L100CB
SMS56L100CB
SMS56L100CB
7MS56S65CB
7MS56S75CB

DENSE PAC

IDT

DPS1024-XXX
DPS1026-XXX
DPS1027-XXX
DPS16X5-XXX
DPS257-XXX
DPS32HS-XXX
DPS40256-XXX
DPS41257-XXX
DPS412SS-XXX
DPS6432-XXX
DPS8645-XXX
DPSS088-XXX

7M624
7M624
7M624
SMP564
7M656
7MS56
8M856
SMS56
SMS24
7M4017
SMP456
7MS64

OTHER VENDORS

lOT

MOSEL
ZVREL
NEC
HITACHI

SMS24
SMS24
SMS24
SMS24

MS8S12S
Z10S
MC-120
HM66204

*MILITARY RAMS
NOTE:
BOLD FACE ITEMS ARE
FUNCTIONAL REPLACEMENTS

1-29

Technology/Capabilities

IDT ... LEADING THE CMOS FUTURE
A major revolution is taking place in the semiconductor industry
today. A new technology is rapidly displacing older NMOS and bipolar technologies as the workhorse of the 80's and beyond. That
technology is high-speed CMOS. Integrated Device Technology, a
company totally predicated on and dedicated to implementing
high-performance CMOS products, is on the leading edge of this
dramatic change.
Beginning with the introduction of the industry's fastest CMOS
2K x 8 static RAM, lOT has grown into a company with multiple divisions producing a wide range of high-speed CMOS circuits that
are, in almost every case, the fastest available. These advanced
products are produced with lOT's proprietary CEMOS ™ technology, a twin-well dry-etched, stepper-aligned process utilizing progressively smaller dimensions.
From inception, our product strategy has been to apply the
advantages of our extremely fast CEMOS technology to produce
the integrated circuit elements required to implement highperformance digital systems. lOT's goal is to provide the circuits
necessary to create systems which are far superior to previous generations in performance, reliability, cost, weight, and size. Many of
our innovative product designs offer higher levels of integration,
advanced architectures, higher density packaging, and system
enhancement features that are establishing tomorrow's industry
standards. The company is committed to providing its customers
with an ever-expanding series of these high-speed, lower-power IC
solutions to system design needs.
lOT's commitment, however, extends beyond state-of-the-art
technology and advanced products to providing the highest level

of customer service and satisfaction in the industry. Producing
products to exacting quality standards that provide excellent, longterm reliability is given the same level of importance and priority as
device performance. lOT is also dedicated to delivering these highquality advanced products on time. The company would like to be
known not only for its technological capabilities, but also for provid~
ing its customers with quick, responsive and courteous service.
lOT's productfamilies are available in both commercial and military grades. As a bonus, commercial customers obtain the benefits
of military processing disciplines, established to meet or exceed
the stringent criteria of the applicable military specifications.
lOT is the leading U.S. supplier of high-speed CMOS circuits.
The company's high-performance static RAMs, logic, OSP,
MICROSLICE ™ bit-slice microprocessor products, data conversion devices, Electrically Erasable PROMs, and modular subsystem assemblies complement each other to provide high-speed
CMOS solutions to a wide range of applications and systems.
Dedicated to maintaining its leadership position as a state-ofthe-art IC manufactuer, IOTwill continue to focus on maintaining its
technology edge as well as developing a broader range of innovative products. New products and speed enhancements are
continuously being added to each of the existing product families
and additional product lines will be introduced. Contact your lOT
field representative or factory marketing at 1-800-IOT-CMOS to determine the latest product offerings. If you're building state-of-theart equipment, lOT may be able to solve some of your design
problems.

2-1

fJll

IDT MILITARY AND DESC-SMD PROGRAM
control drawings. This program will go far toward reducing the
need for each defense contractor to make separate specification
control drawings for purchased parts. IDT plans to have SMDs for
many of its product offerings. Presently. IDT has 22 devices which
are listed or pending listing. The devices are from IDT's SRAM.
DSP. Logic and Microprocessor product lines. Additional devices
are being added from those product lines as well as from Data Conversion and EEPROMs. IDT expects the number of SMDs to be over
50 in 1988. Users should contact either IDT or DESC for current
status of products in the SMD program.

IDT is a leading supplier of military. high-speed CMOS circuits.
The company's high-performance static RAMs. Logic. DSP. Microprocessor. Data Conversion. Electrically Erasable memories and
Modular Subsystem product lines complement each other to provide high-speed CMOS solutions to a wide range of military applications and systems. Each product line offers products which are
fully compliant to the latest revision of MIL-STD-883. In addition.
IDT offers radiation tolerant. as well as enhanced. products.
IDT has an active program to have a Defense Electronic Supply
Center (DESC) listing for Standard Military Drawings (SMD) of its
products. The SMD program allows standardization of militarized
products and reduction of the proliferation of nonstandard source

SMD
SRAM

lOT

5962-86765
5962-85525
84036
5962-84132
5962-86015
5962-86859
5962-86875
5962-87002
5962-88552

IDT6168
IDT7164
IDT6116
IDT6167
IDT7187
IDT7198
IDT713017140
IDT7132/7142
IDT71256

DSP

IDT

5962-87531
5962-86873
5962-86846

IDT7201
IDT7216
IDT72404

LOGIC

IDT

5962-87630
5962-87629
5962-86862
5962-87644
5962-87628
5962-87627
5962-87654
5962-87655
5962-87656

IDT54FCT244
IDT54FCT245
IDT54FCT299
IDT54FCT373
IDT54FCT374
IDT54 FCT377
IDT54FCT138
IDT54FCT240
IDT54FCT273

MICROPROCESSOR lOT
5962-87708

IDT39C10

2-2

RADIATION HARDENED TECHNOLOGY
lOT manufactures and supplies radiation hardened products for
military/aerospace applications. Utilizing special processing and
starting materials. lOT's radiation hardened devices are able to
survive in hostile radiation environments. In total dose. dose rate
and environments where single event upset is of concern. lOT
products are designed to continue functioning without loss of performance. lOT can supply all of its products on these processes.

Total Dose radiation testing is performed in-house on an ARACOR
X-Ray system. External facilities are utilized for device research on
gamma cell. LlNAC and other radiation equipment. lOT has an ongoing research and development program for improving radiation
handling capabilities (See "lOT Radiation Tolerant/Enhanced
Products for Radiation Environments· in Section 3) of lOT products/processes.

2-3

lOT LEADING EDGE CEMOS TECHNOLOGY
been re-engineered and refined from the original 2.5 micron
CEMOS I to the present CEMOS III direct step-on-wafer, dry etch
process providing gate lengths as small as submicron (Figure 1).
Continual advancement of CEMOS technology allows IDT to implement progressively higher levels of integration and achieve increasingly faster speeds maintaining the company's established
position as the leader in high-speed CMOS integrated circuits.
CEMOS is a technology designed to optimize high-speed, lowpower and dense integration of advanced architecture VLSI and
memory products.

HIGH-PERFORMANCE CEMOS
CEMOS ™ (the "E" stands for enhanced) is a state-of-the-art
proprietary CMOS technology initially developed and continually
refined by IDT to be at the leading-edge of new high-speed CMOS
processes. It incorporates the best characteristics of traditional
CMOS, including low power, high noise immunity and wide operating temperature range; it also achieves speed and output drive
equal or superior to bipolar Schottky TTL.
The company has been producing CEMOS products in large
volume for over six years. During this time, CEMOS technology has

CEMOS III

CEMOS II

CEMOSI

B

A

C

B

A

Year

1981

1983

1984

1985

1986

1987

Drawn
Feature Size

2.5~

1.7~

1.5~

1.5~/1.2~

1.3~

1.2~

Leff

1.3~

1.1~

O.9~

O.9~

O.9~

O.8~

Basic
Process

Dual Well
Oxide Isolated
Ion Implanted
Wet Etch
Projection
Aligned

Dry Etch
Stepper
Aligned

Shrink

Spacer

Silicide
LDD
BPSG

Shrink
BiCEMOS™
Multi-Layer
Metal

Enhancements

CEMOS IV

CEMOS III - scaled process optimized for high-speed logiC.
Figure 1.

tion capacitance and transistor body effects and allows extremely
fast speeds. In addition, it significantly reduces soft errors induced
by high-energy alpha particles in fine line geometry memory
products.

DUAL-WELL STRUCTURES
CEMOS is constructed using an advanced dual-well, or twinwell; process architecture (Figure 2) to optimize the overall characteristics of a high-performance CMOS process. CMOS processes
using only "P-Wells" result in inferior P (or N) channel transistors or
compromised PIN channels. This compromise is largely eliminated by utilizing both a deep underlying main "well" (in this case a
"P-Well" in "N-substrate") and by altering the doping profile nearer
the surface of the P-channel transistor regions. The latter region
becomes the "N-Well" of the dual-well process. This technique
allows the fabrication of high-performance transistors in both
polarities.
The industry now recognizes that the best combination of balanced capabilities is achieved using this dual-well approach. This
construction technique supresses punch-through, minimizes junc-

ELECTROSTATIC DISCHARGE (ESD)
PROTECTION
Another traditional limitation associated with many MOS and bipolar products is electrostatic discharge induced failures. This
problem has also been solved by a combination of IDT's CEMOS
process and proper circuit design. All lOT products incorporate
proprietary ESD protection circuitry on all inputs and outputs to ensure that they are insensitive to repeated application of ESD stress
and do not exhibit the degradation found in other MOS or bipolar
products which can eventually result in product failure.

2-4

IDTCEMOS
Device Cross Section
Silicide

lOT CEMOS
Built-In High Alpha Particle Immunity

-3V

NMOS

+5V

CEMOS'·

Figure 2.

Figure 3.

IDTCEMOS
Latchup Suppression

ALPHA PARTICLES
Random alpha particles can cause memory cells to temporarily
lose their contents or suffer a "soft error. n Traveling with high energy levels, alpha particles penetrate deep into an integrated chip.
As they burrow into the silicon, they leave a trail of free electronhole pairs in their wake.
The cause of alpha particles in well documented and understood in the industry. lOT has considered various techniques to
protect the cells from this hazardous occurrence. These techniques include dual-well structures (Figures 2 & 3) and a polymeric
compound for die coating. Presently, a polymeric compound is
used in many of lOT's SRAMs; however, the specific technique
used may vary and change from device generation to the next as
the industry and lOT improve the alpha particle protection
technology.

\

il~
w

(a)

LATCHUP IMMUNITY
A combination of careful. design layout, selective use of guard
rings and proprietary techniques have resulted in virtual elimination of latchup problems often associated with older CMOS processes (Figure 4). The use of NPN and N-channel I/O devices
eliminates hole injection latchup. Double guard ring structures are
utilized on all input and output circuits to absorb injected electrons.
These effectively cut off the current paths into the internal circuits to
essentially isolate I/O circuits. Compared to older CMOS processes which exhibit latch up characteristics with trigger currents
form 10-20mA, IDT products inhibit latch up at trigger currents substantially greater than 700mA.

r-

I

~

- --

\

1\

0

Section A-A

(b) Collector Supply Voltage Vee

Figure 4.

2-5

-

M

SURFACE MOUNT TECHNOLOGY
Products that are to be interconnected to form larger electronic
elements are electrically tested, environmentally screened, performance selected and then thermally matched to the appropriate
ceramic or glass filled epoxy substrates. After modular assembly,
the finished product is 100% re-tested to ensure that it completely
performs to the specifications required.
As a result, lOT produces extraordinarily dense, high-speed
combinations of monolithic ICs as complex subsystem modular
assemblies. These modules convert SMDs to user-friendly DIPs!
SIPs providing customers with the density advantages of surface
mount in a format compatible with their extensive, thru-board,
assembly expertise.

To take full advantage of the low-power aspect of CMOS, and
obtain two to three times the space savings, CMOS products
should be used as SMDs (surface mount devices). However, most
integrated circuits sold today are still packaged in the traditional
DIP (dual in-line package) configuration and there is a tremendous
support industry to handle thru-board assembly.
Determined to utilize CMOS advantages, lOT re-invented the
DIP. This was accomplished by developing multilayered substrates (either co-fired ceramic or glass filled epoxy FR-4) with dual
in-line (DIP) or single in-line (SIP) pins. An advanced vapor phase
reflow surface mount technology was also developed after exhaustive evaluation proved vapor phase reflow to be the most efficient
method of heat transfer and to produce the most reliable solder
connections available.

2-6

STATE-OF-THE..;ART FACILITIES AND CAPABILITIES
Integrated Device Technology is headquartered in Santa Clara,
California - the heart of the "Silicon Valley." The company's operations are housed in five facilities totaling close to 400,000
square feet. These facilities incorporate all aspects of business
from research and development to design, wafer fabrication, assembly, environmental screening, test and administration. Inhouse capabilities incorporate scanning electron microscope
(SEM) evaluation, particle impact noise detection (PIND), plastic
packaging, military and commercial testing, burn-in, life test and a
full complement of environmental screening equipment.
lOT's 54,000 square foot Corporate Headquarters houses technology and product research and development. Teams equipped
with state-of-the-art computerized design and analytical tools conduct the continuous research and development required to push
CEMOS technology forward and to create future product lines.
This facility contains a 10,000 square foot Class 10 (no more than
10 particles larger than 0.2 micron per cubic foot) wafer fabrication
clean room used to produce the Microprocessor, DSPand Logic
product families, as well as support R&D.
Located adjacent to the headquarter facility, forming an lOT corpo rate campus, is a 100,000 square foot two-building complex that
houses the DSP Division and Microprocessor product line. Design
and product teams, along with administrative functions, are situated in these buildings.
A second small wafer fabrication area, used for research and development, is also located at this site. This facility houses its own
design tools, laboratories, test and burn-in facilities and in-house
plastic assembly.
lOT's Subsystem Division is housed in a third Santa Clara location, only a few blocks away from the other sites. This 37,000
square foot facility contains the development and product teams
that produce lOT's FCT, AHCT, IDT39C800 logic families and
modular assemblies. Included at this facility are a quick turnaround hermetic package assembly line and an advanced vapor
phase reflow surface mounting module assembly area.
lOT's largest facility is located in Salinas, California, about an
hour away from Santa Clara. This is the Static RAM Division's
headquarters, a 100,000 square foot facility located on a 14 acre
site. Constructed in 1985, this facility houses an ultra-modern
25,000 square foot high-volume wafer fabrication area measured

at Class 2-to-3 clean room conditions (a maximum of 2 to 3 particles per cubic foot of 0.2 micron or larger). Careful design and construction created a clean room environment far beyond the average of U.S. fab areas (Class 100), capable of producing large volumes of very high-density submicron geometry, fast static RAMs.
This facility also houses shipping areas for lOT's leadership family
of CMOS static RAMs. This site has future expansion capabilities to
accomodate a 250,000 square foot complex.
lOT's Packaging and Assembly Process Development teams
are located at the Corporate Headquarters in Santa Clara. To keep
pace with the development of new products and to enhance the
lOT philosophy of "Innovation," these teams have ultra modern,
integrated and correspondingly sophisticated equipment and environments at their disposal. All manufacturing is completed in
dedicated clean room areas (Class 10K minimum), with all preseal
operations accomplished under Class 100 Laminar Flow Hoods.
Development of assembly materials, processes and equipment
is accomplished in these two facilities under a fully operational production environment to ensure reliability and repeatable product.
The Hermetic Manufacturing and Process Development team
is currently producing custom products to the strict requirements
of MIL-STD-883. The fully automated plastic facility is currently
producing high volumes of USA manufactured product while developing state-of-the-art surface mounttechnology, patterned after
MIL-STD-883.
To extend these philosophies while maintaining strict control of
our processes, lOT has acquired an operational Assembly and
Test facility located in Penang, Malaysia. This facility is being upgradedto USA standards and will be fully operational mid-1988.
As in the USA facility, all assemblies will be accomplished under
laminar flow conditions (Class 100) until the silicon is encased in its
final packaging. All products in this facility will be manufactured to
the quality control requirements of MIL-STD-883.
lOT's faci lities total nearly 400,000 square feet of floor space and
house three wafer fabrication clean rooms, four assembly lines,
five test areas and four burn-in areas. All of these facilities are
aimed at increasing our manufacturing productivity to supply ever
larger volumes of high-performance, cost-effective leadership
CMOS products.

2-7

g

SUPERIOR QUALITY AND RELIABILITY
Maintaining the highest standards of quality in the industry on
all products is the basis of Integrated Device Technology's manufacturing systems and procedures. From inception, quality and reliability are built into all of lOT's products. Quality is "designed in"
at every stage of manufacturing -as opposed to being "tested-in"
later-"in order to ensure impeccable performance.
Dedicated commitment to fine workmanship, along with development of rigid controls throughout wafer fab, device assembly
and electrical test, create inherently reliable products. Incoming
materials and chemicals are subjected to careful Inspections.
Quality monitors, or inspections, are performed throughout the
manufacturing flow.
lOT military grade monolithic hermetic products are deSigned
to meet or exceed the demanding Class B reliability levels of MILSTO-883 and MIL-M-38510.
Productflow and test procedures for all monolithic hermetic military grade products are rn accordance with the latest revision and
notice of MIL-STO-883. State-of-the-art production techniques and
computer-based test procedures are coupled with tight controls
and inspections to ensure that products meet the requirements for
100% screening. Routine quality conformance lot testing is performed as defined in MIL-STO-883, Methods 5004 and 5005.
For module assemblies, additional screening of the fully assembled substrates is performed to assure package integrity and

mechanical reliability. One-hundred percent electrical tests are
performed on the finished module to ensure compliance with the
defined "subsystem" specifications.
By maintaining these high standards and rigid controls throughout every step of the manufacturing process, lOT ensures that commercial, industrial and military grade products consistently meet
customer requirements for quality, reliability and performance.

SPECIAL PROGRAMS
Class S. lOT also has all manufacturing, screening and test
capabilities in-house (except X-ray and some Group D tests) to perform complete Class S processing per MIL-STO-883 on all IDT
products and has supplied Class S products on several programs.
Radiation Hardened. lOT has developed and supplied several
levels of radiation hardened products for military/aerospace applications to perform at various levels of dose rate, total dose, Single
event upset (SEU), upset and latchup. lOT products maintain
nearly their same high-performance levels built to these special
process requirements. The company has in-house radiation testing
capability used both in process development and testing of deliverable product. lOT also has a separate group within the company
dedicated to supplying products for radiation hardened applications and to continue research and· development of process and
products to further improve radiation hardening capabilities.

2-8

---_._----------_._....__._--_.__

...

_.. ........ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _

Quality and Reliability

s
s

ranl

MILITARY DATA SHEET PARAMETRIC TEST
For compliant MIL-STD-883 products. IDT tests all electrical parameters except those parameters which are footnoted In the data
sheet as being guaranteed by design or as a summation of other
parameters. There are no electrical tests performed in production
or at Group A sample tests for those particular electrical
parameters.
In this 1988 Data Book. IDT has identified the electrical parameters which are guaranteed by design. However. there were omissions is some of the data sheets and the following electrical parameters should have had a footnote identifying them as being untested but guaranteed by design.

PART NUMBER
IDT39C01C/D/E

IDT39C03N39C03B

IDT39C60/-1/A

IDT49C402/A

VIH. VIL; Cycle time and clock characteristics: Read-modify-write cycle. Max. clock
frequency to shift Q. Min. clock period

IDT49C403/A

VIH. VIL. Multiply Instructions table. BCD Instructions table. sign magnitude to two's
complement conversion table. Divide Instruction table. single length normalization
table

IDT49C460/NB

Combinational Propagation Delays: Generate (to DATAo-31). LEDIAG (to DATA o- 31).
Internal control mode LE DIAG (to DATA o-31).
Internal control mode DATA o- 31 (to
DATA 0-31)

IDT7200S/L

tRLZ. tWLZ. tRHZ. tRPE. tWPF

IDT7201SNLA.

tRLZ. twLZ. tRHZ. tRPE. tWPF
tRLZ. tWLZ. tRHZ. tRPE. tWPF
tRLZ. tWLZ. tRHZ. tRPE. tWPF

PARAMETER
Cycle Time and Clock Characteristics:
Read-Modify-Write Cycle. Maximum Clock
Frequency to shift Q. Min. Clock Period
VIH. VIL. Min. clock low time. Min. clock high
time. Min. time CP and WE both low to
write. Multiply Instructions table. Divide Instructions table. Sign magnitude to two's
complement conversion table. single
length normalization table
Combinational Propagation Delays: Generate (to DATA o- 15). LE DIAG (to DATA o- 15).
Internal control mode LE DIAG (to DATA o- 15).
Internal control mode DATA 0-15 (to
DATA o- 15). Generate (to LE oUT ). Set-up
and Hold Time Relative to Latch Enable

IDT39C203/39C203A VIH. VIL. Min. clock low time. Min. clock high
time. Min. time CP and WE both low to
write. Multiply Instructions table. Divide Instructions table. BCD Instructions table.
Sign magnitude to two's complement conversion table. single length normalization
table
IDT39C705NB
VIH. VIL
IDT39C707NB
VIH. VIL
IDT49C401/A
VIH. VIL; Cycle time and clock characteristics: Read-modify-write cycle. Max. clock
frequency to shift Q. Min. clock period

IDT7202SNLA
IDT7203S/L
IDT72103

tRLZ. tWLZ. tRHZ. tpDlo tpD2. tSOHZ. tsOLZ. tOEHZ.
tOELZ

IDT72401

tSIR. tHIR. tSOR. tIPH. tOPH

IDT72402
IDT72403

tSIR. tHIR. t SOR • tIPH. tOPH
tSIR. tHIR. tSOR • tHZOE. tIPH. tOPH

IDT72404

tSIR. tHIR. tSOR. tHZOE. tIPH. t OPH

IDT72413

tIPH. tOPH. tORD. tpHZ. tpLZ. tPZL. tPZH
C REF• CIoVOCP • VOCN • Ro. Co. Fs. tPWL.
tPWH. tHo tSIo tRI. BWR. TCG. DG. GC. GI.
GE. FTc. PSRR (with 60Hz ripple). VIL. VIH.
VICM

IDT75C18

IDT75C19

CREF. CIoVOCP • VOCN • Ro. Co. Fs. tPWL.
tPWH. tHo tSI. tRI. BWR. TCG. DG. GC. GI.
GE. FTc. PSRR (with 60Hz ripple). VIL. VIH.
VICM

IDT75C458
IDT75C48
IDT75C58

tCLI2.5kg)

IDTSPEC

I
LEAD BOND PULL
TEST SAMPLE

2011

(> 3.0 grams)

I
2010

CONDo B

I
INCOMING
LIDS (SAMPLE)

PRE-CAP VISUAL
SAMPLE

2010

CONDo B

I

IDT SPEC

I
IDT SPEC PROVIDES LOT TRACEABILITY

I
1008

STABILIZATION BAKE

CONDo C, 24HR/150°C

I
1010

CONDo C,10 CYCLES
-65°C TO + 150°C

2001

CONDo E, Y1 Direction
> 30kg (PKG < 5g)
> 20kg (PKG :::. 5g)

I

CENTRIFUGE

I,

FINE LEAK TEST
GROSS LEAK TEST

1014

CONDo Aor B,
<5.0 X 1O-8ATM/CC/SEC.

1014

CONDo C

I

IDTSPEC

HERMETICITY SAMPLE:
(SEE NOTE 3)

PRE BURN-IN
ELECTRICAL TEST

FINE LEAK:
1014
CONDo A or B
,
<5.0Xl0-8
IDT,SPEC ATM/CC/SEC.
5004

COND.C

DC, AC, FUNCTIONAL @
(SEE NOTE 2)

+
SEE FINAL PROCESSING FLOW ON PAGE 3-3 FOR REMAINDER OF OPERATIONS AND NOTES

3-2

GROSS LEAK"

+ 25°C

Monolithic Hermetic Package Final Processing Flow

Operation

MIL-STO-883
Test Method

Military
Compliant

Commercial
Military
Temp. Range

Commercial
Temp. Range

Burn-In

1015/D at + 125°C
Min. or Equivalent

100%
160 Hours

100%
16 Hours

100%
16 Hours

Post Burn-in Electrical: Static (DC). Functional and
Switching (AC) (2)

IDT Spec.

100%
+25, -55 &
+125°C

100%
+ 125°C

100%
+70°C

Percent Defective Allowed (PDA)(4)

5004 or IDT Spec.

5%

10%

10%

Group A Electrical: Static (DC), Functional and
Switching (AC) (2)

5005 & IDT Spec.

Sample
-55 & + 125°C

Sample
+ 125°C

Sample
+70°C

Mark/Lead Straighten

IDT Spec.

100%

100%

100%

+ 25°C Electrical (2)

IDT Spec.

100%(5)

100%

100%

Final Visual/Pack

IDT Spec.

100%

100%

100%

Quality Conformance Inspection

5005 (Group B, C, D)

Yes

-

-

Quality Shipping Inspection
(Visual/Plant Clearance)

IDT Spec.

Sample

Sample

Sample

NOTES:

1.
2.
3.
4.
5.

6.

All screens are 100% unless otherwise noted.
All electrical test programs are per the applicable IDT test specification.
This hermeticity sample is performed after all lead finish operations.
If a lot fails the 5% PDA but is .::10%, the lot may be resubmitted to burn-in one time only to the same time and temperature conditions as
first submission. The subsequent post burn-in electrical test at + 25°C will be performed to a PDA of 3%.
IDT performs a 100% electrical test at + 25°C with a 2% PDA limit at this pOint to satisfy group A reqUirements, and considers this to be
equivalent to the group A requirement of an LTPD of 2, with an accept number of O. If a lot fails the 2% PDA limit, it may be rescreened
one time only to a tightened PDA limit of 1.5%.

@

Quality sample inspection

3-3

6.

Post Mold Cure: Plastic encapsulated devices are baked
to insure an optimum plastic seal so as to enhance moisture barrier characteristics.
Pre-Burn-In Electrical: Each product is 100% electrically
7.
tested at an ambient temperature of +25°C to IDT data
sheet or the customer specification.
8;
Burn-In: Except for MSI Logic family devices where it may
be obtained as an option, all Commercial Grade plastic
package products are burned-in 16 hours at + 125°C (or
equivalent), utilizing the same burn-in circuit conditions as
the Military Grade product.
Post-Burn-In Electrical: After burn-in, 100% ofthe plastic
9.
product is electrically tested to IDT data sheet or customer
specifications at the maximum temperature extreme. The
minimum temperature extreme is tested periodically on an
audit basis.
10. M ark: All product is marked with product type and lot code
identifiers.
11. Quality Conformance Inspection: Samples of the plastic
product which have been processed to 100% screening
requirements are subjected to the Periodic Quality Conformance Inspection Program. Where indicated the test
methods are patterned after MIL-STD-883 criteria.

SUMMARY
MONOLITHIC PLASTIC PACKAGE PROCESSING FLOW
Refer to the Monolithic Plastic Package Processing Flow
diagram. All test methods refer to MIL-STD-883 unless otherwise
stated.
1.
Wafer Fabrication: Humidity, temperature and particulate contamination levels are controlled and maintained
according to criteria patterned after Federal Standard 209,
Clean Room and Workstation Requirements. All critical
workstations are maintained at Class 100 levels or better.
Topside silicon nitride passivation is applied to all wafers
for better moisture barrier characteristics.
Wafers from each wafer fabrication area are subjected to
scanning electron microscope analysis on a periodic
basis.
Die-Sort Visual Inspection: Wafers are cut and separated
2.
and the individual die are 100% visually inspected to strict
internal criteria.
Ole Push Test: To ensure die attach integrity, product
3.
samples are routinely subjected to die push tests.
4.
Wire Bond Monitor: Product samples are routinely
subjected to wire bond pull tests to ensure the integrity of
the lead bond process.
Pre-cap Visual: Before the package is molded, 100% of
5.
the product is visually inspected to criteria patterned after
MIL-STD-883, Method 2010, Condition B.

3-4

,

Monolithic Plastic Package Processing Flow
(SEE NOTE 1)

OPTICAL INSPECTION SAMPLE

INCOMING LEAD FRAME VIS/DIM/
SAMPLE
INCOMING DIE ATTACH EPOXY
SAMPLE

Q

DIE ATTACH PUSH TEST SAMPLE

Q

LEAD BOND PULL TEST SAMPLE

INCOMING GOLD WIRE
SAMPLE

INCOMING MOLDING COMPOUND
SAMPLE

PRE-CAP OPTICAL SAMPLE INSPECTION

CHEMICAL DEFLASH

POST MOLD CURE
MECHANICAL DEFLASH
TRIM/FORM/SINGULATION
SOLDER DIP
OPEN/SHORT TEST SAMPLE
EXTERNAL VISUAL
BURN-IN BIASED/DYNAMIC AT + 125°C.
16 HRS. MINIMUM (OR EQUIVALENT)
ON ALL PRODUCTS
EXCEPT MSI LOGIC FAMILY DEVICES
(FCT. AND 39C800).
ON WHICH IT MAY BE OBTAINED AS
AN OPTION.

PRE-BURN-IN ELECTRICAL TEST +25°C (SEE NOTE 2)

ELECTRICAL TEST QUALITY SAMPLE + 70°C (SEE NOTE 2)

NOTES:
1)

All screens are 100% unless otherwise noted.

2)

All electrical test programs are per the applicable IDT test specification.

3)
4)

IDT performs a 100% electrical test at + 25°C with a 5% PDA limit at this point.

®

= Quality sample inspection

3-5

2.

SUMMARY
MODULE ASSEMBLY HERMETIC PACKAGE
PROCESSING FLOW(1)

3.

Refer to the Module Assembly Hermetic Package Processing
Flow diagram. All test methods refer to MIL-STD-883 unless
otherwise stated.

Components

4.

1.

Military Grade Class B monolithic microcircuit products utilized in Module Assembly products are
manufactured and screened in compliance with the
applicable demanding criteria of MIL-STD-883. (See the
'" Monolithic Hermetic Package Processing Flow diagram.)
2. Commercial Grade monolithic microcircuit products
utilized in Module Assembly products differ from Military
Grade only in the burn-in time and electrical test
temperatures.
3.
Passive components such as chip capacitors are
obtained from qualified vendors to the applicable military
and IDT specifications.

5.

6.

7.

Modules
1.

Module Assembly: The active and passive components
and substrates used in the assembly of modules must
pass incoming inspection requirements. The components
are then mounted onto the substrate using the reflow
solder vapor phase technique.

8.

Pre-Bum-In Electrical Test: Each module is 100%
electrically tested at an ambient temperature of + 25 ° C to
IDT data sheet or the customer specification.
Burn-In: 100% of Military Grade module product is
burned-in under the dynamic electrical conditions of
Method 1015, Condition D, for 44 ± 4 hours at a TA of
+ 125°C. Commercial Grade module products do not
require burn-in.
Post-Bum-In Electrical: After burn-in, 100% of the
Class B Military Grade product is electrically tested to IDT
data sheet or customer specifications over the -55°C to
+ 125 ° C temperature range. Commercial Grade products
are sample tested to the applicable temperature extremes.
PDA Calculation: A PDA (Percent Defective Allowed) of
5% is imposed on all Military module products for the
25°C parameters after completion of burn-in.
Mark: All product is marked with product type and lot code
identifiers. MIL-STD-883 compliant Military Grade products are identified with the required compliancy code
letter.
Quality Conformance Tests: Samples of the Military
Grade product which have been processed to 100%
screening tests are routinely subjected to the Quality
Conformance Inspection requirements of MIL-STD-883
applicable to Module Assembly products.
External Visual: Product is 100% visually inspected prior
to shipment to the applicable criteria for modules as
required by MIL-STD-883.

NOTE:
1. For quality requirements beyond Class B levels, such as SEM analysis. X-ray inspection. Particle Impact Noise Detection (PIND) test. Class S
screening or other customer specified screening flows. please contact your Integrated Device Technology sales representative.

3-6

Module Assembly Hermetic Package Processing Flow

MOTHER BOARD
INCOMING
INSPECTION
( SAMPLE)
PACKAGE CLEAN
COMPONENT
INCOMING
INSPECTION
(SAMPLE)

LCC SOLDER DIP

BOTTOM COMPONENT MOUNT
REFLOW SOLDER
VAPOR PHASE
PACKAGE CLEAN
TOP COMPONENT MOUNT
REFLOW SOLDER
VAPOR PHASE
PACKAGE CLEAN

BUMPER APPLICATION
FINAL VISUAL INSPECTION

EXTERNAL VISUAL
PRE BURN-IN
ELECTRICAL TEST
DC, AC, FUNCTIONAL @ 25°C

SEE FINAL PROCESSING FLOW ON PAGE 3-8 FOR REMAINDER OF OPERATIONS AND NOTES

3-7

Module Assembly Hermetic Package Final Processing Flow

Commercial
MIL-STD-883
Test Method

Military
Compliant

Burn-In

1015/0 at + 125 OC
Min. or Equivalent

100%
44 ± 4 Hours

-

-

Post Bum-in Electrical: Static (DC). Functional and
Switching (AC) (2)

IDTSpec.

100%
+25. -55 &
+125°C

100%
+125°C

100%
+70°C

Percent Defective Allowed (PDA) (3)

5004

5%

-

-

IDTSpec.

Sample
-55 & +125°C

Sample
+125°C

Sample
+70°C

Operation

Group A Electrical: Static (DC). Functional and
Switching (AC) (2)

Military
Temp. Range

Commercial
Temp. Range

Mark/Lead Straighten

IDTSpec.

100%

100%

100%

+25°C Electrical (2)

IDTSpec.

100%(4)

100%

100%

Final Visual/Pack

IDTSpec.

100%

100%

100%

Quality Conformance Inspection

(Note 5)

Yes

-

-

Quality Shipping Inspection
(Visual/Plant Clearance)

IDTSpec.

Sample

Sample

Sample

NOTES:
1.
2.

3.
4.

5.

6.

All screens are 100% unless otherwise noted.
All electrical test programs are per the applicable lOT test specification.
If a lot fails the .5% PDA but is ::;.10%. the lot may be resubmitted to bum-in one time only to the same time and temperature conditions as
first submission. The subsequent post burn-in electrical test at +25°C will be performed to a POA of 3%.
lOT performs a 100% electrical te~t at + 25° C with a 2% POA limit at this point to satisfy group A requirements. and considers this to be
equivalent to the group A requirement of an LTPD of 2. with an accept number of O. If a lot fails the 2% POA limit. it may be rescreened
one time only to a tightened PDA limit of 1.5%.
lOT presently utilizes QCI tests pattemed after method 5005. A new method for module products is under development by the military.

0

Quality sample Inspection

3-8

RADIATION TOLERANT/ENHANCED/HARDENED PRODUCTS FOR
RADIATION ENVIRONMENTS
INTRODUCTION
The need for high-performance CMOS integrated circuits in
military and space systems is more critical today than ever before.
The lower power dissipation that is achieved using CMOS technology, along with the high complexity and density leve.ls, ~akes
CMOS the nearly ideal component for all types of applications.
Systems designed for military or space applications are
intended for environments where high levels of radiation may be
encountered. The implication of a device failure within a military or
space system clearly is critical. IDT has made a significant contribution toward providing reliable radiation-tolerant systems by
offering integrated circuits with enhanced radiation tolerance. Radiation environments, IDT process enhancements and device tolerance levels achieved are described below.

THE RADIATION ENVIRONMENT
There are four different types of radiation environments that are
of concern to builders of military and space systems. These environments and their effects on the device operation, summarized in
Figure 1, are as follows:
Total Dose Accumulation refers to the total amount of accumulated gamma rays experienced by the devices in the system, ~~d is
measured in RADS(SI) for radiation units experienced at the silicon
level. The physical effect of gamma rays on semiconductor devices is to cause threshold shifts (Vt shifts) of both the active transistors as well as the parasitic field transistors. Threshold voltages
decrease as total dose is accumulated; at some point, the device
will begin to exhibit parametric failures as the input/output and
supply currents increase. At higher radiati(:ln accumulation le.vels,
functional failures occur. In memory circuits, however, functional
failures due to memory cell failure often occur first.
Burst Radiation or Dose Rate refers to the amount of radiation,
usually photons or electrons, experienced by devices in the system due to a pulse event, and is measured in RADS(SI) per second.
The effect of a high dose rate or burst of radiation on CMOS integrated circuits is to cause temporary upset of logic states and/or
CMOS latCh-up. Latch-up can cause permanent damage to the
device.
Single Event Upset (SEU) is a transient logic state change
caused by high-energy ions, such as energetic cosmic rays, striking the integrated circuits. As the ion passes through the siliCO~,
charge is created either through ionization or direct nuclear collision. If collected by a circuit node, this excess charge can cause a
change in logic state of the circuit. Dynamic nodes that are not actively held at a particular logic state (dynamic RAM cells for example) are the most susceptible. These upsets are transient, but can
cause system failures known as "soft errors."
Neutron Irradiation will cause structural damage to the silicon
lattice which may lead to device leakage and, ultimately, functional
failure.

RADIATION
CATEGORY

PRIMARY
PARTICLE

SOURCE

EFFECT

Total Dose

Gamma

Space or
Nuclear
Event

Permanent

DoseRate

Photons

Nuclear
Event

Temporary
Upset of Logic
State or
Latch-Up

SEU

Cosmic
Rays

Space

Temporary
Upset of
Logic State

Neutron

Neutrons

Nuclear
Event

Device Leakage
Due to Silicon
Lattice Damage

Figure 1.

DEVICE ENHANCEMENTS
Of the four radiation environments above, IDT has taken considerable data on the first two, Total Dose Accumulation and Dose
Rate. IDT has developed a process that significantly improves the
radiation tolerance of its devices within these environments. Prevention of SEU failures is usually accomplished by system-level
considerations, such as error checking and correction (ECG) circuitry, since the occurrance of SEUs is not particularly dependent
on process technology. Through IDT's customer contracts, SEU
data has been gathered on some devices. Little is yet known about
the effects of neutron-induced damage. For more information on
SEU testing, contact IDT's Radiation Hardened Product Group.
Figure 2 itemizes some of the enhancements that IDT has made
to its standard process in creating a radiation enhanced proce~s.
The use of epi substrate material provides a lower substrate re~ls­
tance environment to create latch-up free CMOS structures. Field
and gate oxides are less susceptible to radiation damage (Le.,
"hardened") by modifying the process architecture to allow lowertemperature processing. Device implants and Vts have been adjusted allowing more Vt margin.
STANDARD

ENHANCED

Substrate Material

n-

n- epi/n+

Field Oxide

sid

hardened

Gate Oxide

sid

hardened

Vt, n

0.75 volts

1.0 volts

Vt,p

-0.75 volts

-0.6 volts

1000°C

900°C

Process Temperature
Post Gate OXide

Figure 2.

3-9

100K RADs(Si) capability for non-memory products] without
failure.

RADIATION HARDNESS CATEGORIES
With the process enhancements described above,lDT offers integrated circuits with varying grades of radiation tolerance, or radiation "hardness," shown in Figure 3. The level of radiation hardness is defined by IDT as follows:
• Radiation Enhanced integrated circuits are defined as being
able to withstand a total dose of 30K RADs(Si) [memory devices,

TYPE OF
RADIATION

UNITS

• Radiation Tolerant integrated circuits are defined as being able
to withstand a total dose of 10K RADs(Si) without failure. Standard IDT products can be expected to exhibit radiation tolerance of (withstand) a total dose of 4K-6K RADs(Si) without
failure.

MEMORY

PRODUCT TYPES
MEMORY+
LOGIC

LOGIC

lOT
PROCESS

S15K
>10K
>30K

Standard
Tolerant
Enhanced

Total Dose

K RADs(Si)
Rate: 10K
RADs(Si)/min.

S6K
>10K
>30K

Dose Rate
(Latchup)

RADs(Si)/sec.
pulse width = 50ns

1.0E8
1.0E8
>2.4E10
>2.4E10
>2.4E10
--------------No Latchup--------------

S6K
>10K
>30K

Standard
Tolerant
Enhanced

Figure 3.

Integrated Device Technology now offers devices processed to
each of these radiation tolerant levels across the full product line.

lOT

XXXXX
DEVICE TYPE

--APOWER

Blank
RT
RE

--L-

~

PACKAGE

SPEED

MIL-STD-883, CLASS B
Standard
Radiation Tolerant
Radiation Enhanced

The appropriate part number corresponding to these radiation
hardness categories is defined In Figure 4.

~

PROCESS

---------'1

1-1

AA
RAD HARD

I

11---------------------1·

Figure 4.

Please contact your local IDT sales representative or factory
marketing to determine availability and price of any IDT product
processed In accordance with one of these levels of radiation
hardness.

hardness levels, as well as its high-performance and low power
dissipation. To serve this growing need for CMOS circuits that
must operate in a radiation environment, IDT has created a separate group within the company to concentrate on supplying products for these applications. Continuing research and development
of process and products, including the use of in-house radiation
testing capability, will allow Integrated Device Technology to offer
continuously increasing levels of radiation-tolerant solutions.

CONCLUSION
There has been widespread interest within the military and
space community In IDT's CMOS product line for its radiation

3-10

Static RAMs

------------------

----~~-~---

SRAM INTRODUCTION
Integrated Oevice Technology is the major U.S. supplier of highperformance Static Random Access Memories. leading edge
CEMOS and BiCEMOS process technology, coupled with
advanced design techniques, enables lOT to supply our military
and commercial customers with production volumes of the
industry's fastest SRAMs. lOT is committed to providing our
customers with early access to innovative circuit designs, taking
full advantage ofthis advanced process technology. This results in
the broadest range of SRAM speeds, densities and organizations
available in today's market.
Integrated with performance leadership at lOT is a commitment
to provide our customers with a wide selection of SRAM organizations. 16K, 64K and 256K devices are offered in x1, x4 and x8
organizations. This year, these offerings will be expanded to
include x16 and x9 devices, as well as 1 Megabit densities. To
further match lOT SRAMs with system architectural needs, several
devices are available with separate inputs and outputs, additional
control features and functions.
leadership products offered by lOT include BiCEMOS devices,
incorporating both TTL and ECl compatible inputs and outputs, as
well as CEMOS devices offering true CMOS I/O levels. These
products confirm our charter to offer technology to system designers in its most friendly and usable form.
Our intensive and innovative process technology development
effort has resulted in truly outstanding advances in device performance. Over the past 7 years, as an example, our 2K x 8 SRAM has
been redesigned in successively advanced CEMOS processes,

progressing from 2J.1 geometries to less than 1J.1. This resulted in
access time being improved by about a factor of 10, to the currently
available 15 nanosecond devices. This continuing dedication to
advancement will result in 1 Megabit CEMOS devices and 256K bit
BiCEMOS devices this year.
lOT's advanced SRAMs are available in a wide variety of
packages, ranging from commercial surface mount through DIPs
and lCCs to military flatpacks. This continually expanding
package offering is in direct response to critical second-level
interconnect issues confronting today's system designer. Our
commitment to technology extends to advanced, cost-effective
packaging techniques.
Both commercial and military versions of all lOT SRAMs are
available. Our military devices are manufactured and processed
strictly in conformance with all the administrative, processing and
performance requirements of Mll-STO-883. Having anticipated
increased military radiation resistance requirements, all devices
are also offered with special radiation resistant processing and
guarantees. As a leading supplier of military SRAMs, lOT provides
performance and quality levels second to none. Our commercial
products, in fact, share most processing steps with military
devices.
lOT's continuing commitment to cutting edge technology and
performance will assure the availability of SRAMs most compatible
with the exacting needs of today's systems. look to lOT SRAMs for
performance, technology, quality and imaginative solutions to
memory system problems.

TABLE OF CONTENTS
CONTENTS
Static RAMs
IDT6167
16K (16K x 1) CMOS SRAM (Power Down) (14-74, 14-200, 14-253) ...........................
IDT6168
16K (4K x 4) CMOSSRAM (Power Down) (14-253) .........................................
IDTl1681
16K (4K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write (14-36, 14-74, 14-253)) :.
IDTl1682
16K (4K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) (14-36, 14-74, 14-253) ........
IDT6116
16K (2K x 8) CMOS SRAM (14-74, 14-253) ...............................................
IDTl187
64K (64K x 1) CMOS SRAM (Power Down) (14-74, 14-253) ..................................
IDT100490
64K (64K x 1) BiCMOS SRAM with ECl I/O ...............................................
IDTl188
64K (16K x 4) CMOS SRAM (Power Down) (14-74, 14-253) ................... ~ . . . . . . . . . . . . ..
IDT6198
64K (16K x 4) CMOS SRAM (with Output Enable) (14-74, 14-253) ......................... '. . ..
IDTl198
64K (16K x 4) CMOS SRAM (2 CE and OE) (14-74, 14-253) .................................
IDTl1981
64K (16K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) (14-36, 14-74, 14-253) ..
IDTl1982
64K (16K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) (14-36, 14-74, 14-253) .......
IDTl164
64K (8K x 8) CMOS SRAM (Power D9wn) (14-74, 14-207, 14-253) ............................
IDTl186
64K (4K x 16) CMOS SRAM (Power Down) (14-74, 14-253) ..................................
IDT8M628
128K (8K x 16) CMOS SRAM ...........................................................
IDT8MP628
128K (8K x 16) CMOS SRAM (Plastic SIP) . .. . ...... . . .. . . . . ...... ... . .... . .. . . . . . . .... . . ..
IDTlMP564
80K (16K x 5) CMOS SRAM (Plastic SIP) .. ... . . ...... .... ... . . . . ... .. . . . .. .. .... .. . .......
IDTl1257
256K (256K x 1) CMOS SRAM (Power Down) (14-74, 14-253) ................................
IDTlMP156
256K (256K x 1) CMOS SRAM (Plastic SIP) .............. , ............... , ............. , . ..
IDTlMC156
256K x 1 CMOS SRAM (Ceramic SIP) ....................................................
IDTl1258
256K (64K x 4) CMOS SRAM (14-74, 14-253) .............................................
IDT61298
256K (64K x 4) CMOS SRAM (with Output Enable) (14-74,14-253) .......... ; . . . . . . . . . . . . . . . ..
IDTl1281
256K (64K x 4) CMOS SRAM (Separate I/O-Output Follows Input at Write) (14-36, 14-74, 14-253) ..
IDTl1282
256K (64K x 4) CMOS SRAM (Separate I/O-Output High Z at Write) (14-36, 14-74, 14-253) ........
IDTlMP456
256K (64K x 4) CMOS SRAM (Plastic SIP) ............................... , . .. . . .. ... . . . ....
IDTl1256
(32K x 8) CMOS SRAM (Power Down) (14-74, 14-253) ......................................
IDT8M856
256K (32K x 8) low-Power CMOS SRAM ........................ , ... ..... . .. . . . . . . . . . . . . ..
IDTlM656
256K (16K x 16) CMOS SRAM ..........................................................
IDT8MP656
256K (16K x 16) CMOS SRAM (Plastic SIP) ......... " ................... , . .. . .... . . . . .....
IDT8M656
256K (16K x 16) CMOS SRAM ..........................................................
IDTlM812
512K (64K x 8) CMOS SRAM ...........................................................
IDTlM912
512K (64K x 9) CMOS SRAM ...........................................................
IDT8M612
512K (32K x 16) CMOS SRAM ..........................................................
IDT8MP612
512K (32K x 16) CMOS SRAM (Plastic SIP) ...... , ............... , ....... , . . . . . ... . . . . .....
IDTlMC4032
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) ........................ , . .. .. .. ... . . . . . ..
IDTl1027
1 Megabit (1024 x 1) CMOS SRAM (Power Down) (14-74, 14-253) ............................
IDDMC4001
1 Megabit (1024K x 1) CMOS SRAM w/Separate I/O (Ceramic SIP) ............................
IDD1028
1 Megabit (256K x 4) CMOS SRAM (Power Down) (14-74, 14-253) ............................
IDD1024
1 Megabit (128K x 8) CMOS SRAM (Power Down) (14-74, 14-253) ............................
IDT8M824
1 Megabit (128K x 8) CMOS SRAM ......................................................
IDT8MP824
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) .......................... , ....... , . . .......
IDDM624
1 Megabit (64K x 16) CMOS SRAM ......................................................
IDDMB624
1 Megabit (64K x 16) CMOS SRAM (Plastic DIP) ...........................................
IDT8M624
1 Megabit (64K x 16) CMOS SRAM ......................................................
IDT8MP624
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) .......................... , .. ... .... . . . .....
IDDM4017
2 Megabit (64K x 32) CMOS SRAM ......................................................
IDDMP4008
4 Megabit (512K x 8) CMOS SRAM (Plastic SIP) .................................. , . . . ......
IDDM4016
4 Megabit (256K x 16) CMOS SRAM .....................................................
Application Specific Memories
IDT6178
16K (4K x 4) CMOS Cache-Tag SRAM (14-47, 14-264, 14-268) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDD174
64K (8K x 8) CMOS Cache-Tag SRAM (14-47, 14-264, 14-268) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDD165
64K (8K x 8) Resettable CMOS SRAM (14-74, 14-207, 14-253) ...............................
IDD1C65
64K (8K x 8) SRAM (Resettable CMOS I/O) (14-74,14-207,14-253) ................. , .........
IDD1501
64K (64K x 1) CMOS Synchronous RAM ..................................................
IDTlMP6025
512K (64K x 8) Synchronous SRAM (Plastic SIP) ...................... ~ . . . . . . •. . . . . . . . . . . ..
IDDM6001
Dual, Multiplexed 16K x 20 SRAM .......................................................
IDDM824
1 Megabit (128K x 8) Registered and Buffered SRAM Subsystem Family ...................... "
IDD1502
64K (4K x 16) CMOS Registered RAM (for Writable Control Stores) (14-154, 14-197) . . . . . . . . . . . . ..
IDDM6032
16K x 32 High-Speed Writable Control Store w/SPC (14-154) ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT7MB6042
8K x 112 High-Speed Writable Control Store w/SPC (14-154) .................................

PAGE
4-1
4-11
4-22
4-22
4-33
4-44
4-52
4-57
4-65
4-74
4-84
4-84
4-94
4-103
13-99
13-80
13-29
4-113
13-17
13-3
4-124
4-133
4-143
4-143
13-23
4-153
13-113
13-48
13-80
13-99
13-57
13-57
13-92
13-74
13-15
4-168
13-9
4-171
4-173
13-107
13-86
13-41
13-1
13-92
13-74
13-72
13-35
13-70
4-184
4-186
4-196
4-206
4-215
13-123
13-197
13-168
4-224
13-199
13-121

FEATURES:

DESCRIPTION:

• High-speed (equal access and cycle time)
- Military: 15/20/25/35/45/55/70/85/100ns (max.)
- Commercial: 12115/20/25/35ns (max.)
• Low power consumption
- IOT6167SA
Active: 200mW (typ.)
Standby:100jJW (typ.)
- IOT6167LA
Active: 150mW (typ.)
Standby:10jJW (typ.)
• Battery backup operation - 2V data retention voltage
(IDT6167LA only)
• Available in 20-pin CERDIP and plastic DIP, 20-pin Flatpack or
CERPACK, 20-pin SOIC and 20-pin lead less chip carrier
• Produced with advanced CEMOS ™ high-performance
technology
• CEMOS process virtually eliminates alpha particle soft-error
rates
• Separate data input and output
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-84132 is pending listing on
this function. Refer to Section 21page 2-4.

The IOT6167 is a 16,384-bit high-speed static RAM organized as
16K x 1. The part is fabricated using lOT's high-performance, highreliability technology- CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective alternative to bipolar and fast NMOS memories.
Access times as fast as 12ns are available with maximum power91
consumption of only 660mW.~he circuit also offers a reduced ~
power standby mode. When CS goes high, the circuit wil~utomatically go to, and remain in, a standby mode as long as CS remains high. In the standby mode, the device consumes less than
10jJW, typically. This capability provides significant system-level
power and cooling savings. The low-power (LA) version also offers
a battery backup data retention capability where the circuit typically consumes only 1jJW operating off a 2V battery.
All inputs and the output of the IDT6167 are TTL-compatible and
operate from a single 5V supply, thus simplifying system designs.
Fully static asynchronous circuitry is used, which requires no
clocks or refreshing for operation, and provides equal access and
cycle ti mes for ease of use.
The IDT6167 is packaged in a space-saving 20-pin, 300 mil
Plastic 'DIP or CERDIP, plastic 20-pin SOIC, 20-pin flatpack or
CERPACK and 20-pin leadless chip carrier, providing high boardlevel packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

Vcc
ROW
SELECT

16.384-BIT
MEMORY ARRAY

GND

COLUMN 1/0
--------~--------4>--~----------------------+-i>---Do~

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc,

DECEMBER 1987
OSC-1007/-

4-1

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6167SA/IDT6167LA CMOS STATIC RAM (16Kx 1-BIT)

PIN CONFIGURATIONS
~

.f~J

A2

A12

A3

All

A4

A10

A5

Ag

As

As

Dour

A7

DIP/SOIC/FLATPACK/CERPACK
TOP VIEW

~ ~ I~
~

6

LCC
TOP VIEW

LOGIC SYMBOL

PIN NAMES

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to + 125

°C

TslAs

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TsrG

Storage
Temperature

-55 to +125

-65 to +150

°C

Pr

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

4-2

Ao-A13

Address Inputs

DIN

DATA IN

CS

Chip Select

DOUT

DATA OUT

WE

Write Enable

GND

Ground

Vec

Power

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6167SAJIDT6167LACMOS STATIC RAM 16K(16Kx 1-Bm

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE

Vcc

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

Military
Commercial

V1H

Input High Voltage

2.2

-

6.0

V

V1L

Input Low Voltage

-0.5(1)

-

0.8

V

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND
OV

5.0V ± 10%

O°C to +70°C

OV

5.0V·± 10%

Vee

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

DC ELECTRICAL CHARACTERISTICS
SYMBOL

lIu l
Illol
VOL

PARAMETER

-

Vcc = 5.0V +10%

TEST CONDITION

MIN.

Input Leakage Current

Vee = Max., V1N = GND to Vcc

MIL.
COM'L.

Output Leakage CUrrent

Vcc = Max.
CS = \'IH ' VOLrr

MIL.
COM'L.

Output Low Voltage

10L = 8mA Vee, = Min.

= GND to 'bc

IDT6167SA
TYPP) MAX.

-

-

2.4

VOH
IOH = -4mA, Vcc = Min.
Output HIGH Voltage
NOTE:
1. Typical limits are at Vee = 5.0V, + 25°C ambient.

IDT6167LA
MIN. TypJ1) MAX.

UNIT

-

10
5

-

10
5

-

-

0.4

-

-

0.4

V

-

-

2.4

-

-

V

-

-

5
2

J.1A

5
2

J.1A

DC ELECTRICAL
SYMBOL

ICCl

lee2

CHARACTERISTICS(1)vc c = 5.0V ±10%, VlC = 0.2V, VHC = Vcc - 0.2V
6167SA12(4) 6167SA15 6167SA20/25 6167SA35 6167SA45(5) 6167SA55(5) 6167SA7O(5)
6167LA35 6167LA4S(5) 6167LA5S(5) 6167LA7O(5) UNIT
6167LA20/25
PARAMETER
POWER 6167LA12(4) 6167LA15
COM'LMIL COM'LMIL COM'L MIL COM'L MIL. COM'L MIL COM'L MIL. COM'L.MIL.

Operating Power
Supply Current
CS =VuJ
Outputs Open,
Vee = Max.,
f = 0(3)
Dynamic
Operating Current
CS = VIL
Outputs Open,
Vcc = Max.,
f = fMAX(3)

SA

-

90

ISB

ISBl

Full Standby
Power Supply
Current (CMOS
Level)
CS ~ VHC '
Vee = Max.,
\'IN ~VHC or
\'IN ::;; VLC f = 0(3)

-

90

90

90

90

90

-

55

60

55

60

55

60

-

60

-

60

-

60

100

120

100 110/100

100

100

-

100

-

100

-

100

85

90

65

70

-

65

-

60

-

60

45

50

35

35

-

35

-

35

-

35

90

90

90
mA

LA

SA

55 " \ ;

120">j
.,.,...:".,:,,:'"

mA

""'''<':

LA

'UU)~

SA

45

"

.,.,.,

Standby Power
Supply Current
(TTL Level)
CS ~VIH,
Vee = Max.,
Outputs Open
f = ~AX(3)

-

90

80170 85175

" ".

..... ....

35

35

mA

"',.......,.. ',', ..
LA

-

35

35

35

5

10

30/25 30/25

20

20

-

20

-

20

5

10

-

10

-

10

-

15

»
SA

5

10

-

10
mA

LA

0.9

-

0.9

2

0.05

2/0.9

0.05

NOTES:
1. All values are maximum guaranteed values.
2. Also available: 85ns and lOOns Military devices
3. f = fMAX (All Inputs cycling at f = lItRe!. f = 0 means no address control lines change.
4. aoc to + 70°C temperature range only.
5. -55°C to + 125°C temperature range only.

4-3

0.9

-

0.9

-

0.9

-

0.9

IDT6167SAJIDT6167LA CMOS STATIC RAM (16K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS
(L Version Only) VLC = 0.2V, VHC = Vcc - 0.2V

VDR
ICCDR

TEST CONDITION

PARAMETER

SYMBOL

MIN.

-

Vee for Data Retention

I

Data Retention Current

MIL
COM'L.

tCDR

Chip Deselect to Data Retention Time

tR(3)

Operation Recovery Time

lIu l(3)

Input Leakage Current

CS ?VHC
V1N <'! VHC or:$ VLC

TYP.(1)
V cc @
3.0V
2.0V

MAX.
Vcc@
2.0V

2.0

-

-

-

-

-

O.S

1.0

200

300

O.S

1.0

20

30

-

-

ns

-

-

ns

-

-

2

~A

DATA RETENTION MODE
VCC

AC TEST CONDITIONS
GNDto 3.0V
Sns
1.SV
1.SV
See Figures 1 and 2

SV

~

2S50

SV

4800
DATA OUT
30pF*

~

. 2S50

Figure 1. Outf)ut Load

'4800
SpF*

Figure 2. Output Load
(for t HZ ' tu. twz and tow)
* Including scope and jig.

4-4

J.lA

0

LOW Vee DATA RETENTION WAVEFORM

DATAoUT

V

t RC (2)

NOTES:
1. TA= +2SoC
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

UNIT
3.0V

IDT6167SA/IDT6167LA CMOS STATIC RAM 16K (16Kx 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
6167SA12(1)
6167LA12(1)
MAX.
MIN.

PARAMETER

SYMBO

(Vcc = 5.0V ±100/0, All Temperature Ranges)

6167SA15
6167LA15
MIN.
MAX.

6167SA35/45(2) 6167SA55(2)/70(2)
6167SA20/25
6167LA35/45(2) 6167LA55(2~70(2)
6167LA20/25
MIN.
MAX. MIN.
MAX. MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

12

tAA
t ACS

Address Access Time

- ..::::::,,:,::"'12
- .::/:;:> 12

Chip Select Access Time

.:}":::':;

15

-

20/25

-

35/45

-

55170

-

-

15

-

20/25

-

35/45

-

55170

ns

15

-

20/25

-

35/45

-

55170

ns
ns

ns

tOH

Output Hold from Address Change

3:2:::::::::::

-

5

-

5

S:::":"'\:::

3

-

5

-

5

-

5

Chip Deselect to Output in Low Z(3)

-

3

tLZ

5

-

tHZ

Chip Select to Output in High

:f:'::.::{

8

-

10

-

10

-

15/30

-

40

ns

tpu

Chip Select to Power Up Time(3)

-

0

-

0

-

0

-

0

-

ns

tpD

Chip Deselect to Power Down Time(3)

12

-

15

-

20/25

-

35

-

55170

ns

Z(3)

::<6::::==

.tt..,..

ns

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only. Also available: 85 and 100ns Military devices.
3. This parameter guaranteed but not tested.

TIMING WAVEFORM OF READ CYCLE NO.1

ADDRESS

DATA OUT

(1,2)

}=

',c'"

PR~IOUS:~ '~j X X *. .

~'----

----D-A-T-A-V-A-U-D-----

TIMING WAVEFORM OF READ CYCLE NO.2

(1,3)

' - " - - - - - - - - tRC(S) --------~~

tLZ (4)
DATA OUT
HIGH IMPEDANCE

r
_
_
_
"D-j _.
c3W~~~~ ::: -------Af
~. . . ------t

pu

NOTES:
1.
2.
3.
4.
5.

M is High for READ Cycle.
CS is low for READ cycle.
Address valid prior to or coincident with CS transition low.
Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
All READ cycle timings are referenced from the last valid address to the first transitioning address.

4-5

IDT6167SA/IDT6167LA CMOS STATIC RAM (16Kx 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL

6167SA12(1)
6167LA12(1)
MIN.
MAX.

PARAMETER

(Vcc = 5.0V ±10%, All Temperature Ranges)

6167SA15
6167LA15
MIN.
MAX.

6167SA20/25
6167SA35/4S(2) 6167SASS(2)/70(2)
6167LA20/25
6167LA35/45(2) 6167LA55(2)/70(2)
MIN.
MAX. MIN.
MAX. MIN.
MAX.

UNIT

WRITE CYCLE
Write Cycle Time

15

20/20

30/45

55/70

ns

Chip Select to End of Write

15

15/20

30/40

45/55

ns

Address Valid to End of Write

15

15/20

30/40

45/55

ns

Address Set-up Time

o

o

o

o

ns

Write Pulse Width

13

15/20

30

35/40

ns

Write Recovery Time

o

o

o

o

ns

Data Valid to End of Write

12

13/15

20/25

25/30

ns

Data Hold Time

o

o

o

o

Write Enable to Output in High

10

Z(3)

Output Active from End of Write (3)

o

10

o

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only. Also available: 85 and 100ns Military devices.
3. This parameter guaranteed but not tested.

4-6

15/30

o

ns
40

o

ns
ns

IDT6167SA/IDT6167LA CMOS STATIC RAM 16K (16K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING) (1,2,3)

twc
ADDRESS

~

)C

--.J ~
tAW
~

I\.
twp

I - - - tAS

:-

tWR

~,

/V

_tWZ(5)t ow (5)
DATA OUT

'""

/

'"

/

I 4 - - t Dw -

)K

DATA IN

"

I+--tOH DATA

VALID

)~

TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLEDTIMING)(1,2,3,4)

twc
ADDRESS

~K

)K
tAW

",
~tAS

/v
tWR

tew

-

I 4 - - t o w - _ tOH -

)K

DATA IN

VALID

DATA

)(

NOTES:

1.
2.
3.
4.
5.

~ or CS must be high during all address transitions.

A write occurs during the overlap (twFl of a low CS and a low ~.
tWR is measured from the earlier of CS or ~ going high to the end of the write cycle.
If the CS low transition occurs simultaneously with or after the VIr:. low transition, the outputs remain in the high impedance state.
Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).

4-7

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6167SA/IDT6167LA CMOS STATIC RAM (16Kx 1-Bln

NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
ISB

vs.

tAA

1.3
U
Ql

.~ 1.1

Icc vs.

(35ns Device)

1.S

Tl = 2StC

Vee

1\

\

~

m
'1(l

0.7

~

\

0.5
25

\

Ql

35

1.0

~

~ 0.9

'" "'

45

55

U
J)

0.8

=

T~

2StC
S.OV

85

0.7

25

'"

~

"~

1.0

35

45

55

V

~

75

.5
4.0

85

ISB

ISB

vs. Temperature

Vee = 5.0V

TA = J5 0 C

1.2 1T---+---I---4----1

1.5

1.1 1 - - - - 4 - - i - - - t - - - i

u

J)

1----+----'~-I---4----1

140

1.0

V

.5
4.0

m

/

_CI)

1.0

5.0

1----4----'~i---t--+-I

0.9 '--_-.1_ _..L--_-.1_----.J
-60
40
140

6.0

TA (0C)

Vee (V)
ISB1

vs. Supply Voltage

1.2

TA

=

ISB1

J25 C
0

vs. Temperature

J
100.0

I

)

Vee = 5.0V

0.9

/

V

1.0

S.O

6.0

in

V
./

V

-60

J

4-8

V

1K
100

"\
r'\

10.0

140

Vee (V)

.1

A

10K

1(l

1/

V'

0.8

0.7
4.0

/

_~ 10.0

1

Vee = 5.0V_
TA = 25°C
.

100K

I

~

1.1

6.0

Vee (V)

vs. Supply Voltage

Vee = S.OV

V
5.0

tAA(ns)

Icc vs. Temperature

d

u

J)

~

75

= 25 0

1.S

tAA(ns)

1.0

=

Vee

~

1.1

Icc vs. Supply Voltage

(35ns Device)

Tl

= S.OV

U

""'

~ 0.9

tAA

1.2

1.0

o

.

.J
2

3
V1N (V)

4

5

6

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6167SAJIDT6167LA CMOS STATIC RAM 16K (16Kx 1-BIT)

NORMALIZED TYPICAL DC AND AC CHARACTERISTICS
t AA • t ACS vs. Supply Voltage

ICCDR vs. Temperature

TA =

1----+---+---+---1

100.0

lsoc

1.2

~

I--_-+-__+-__~C---I

10.0

"""

o

.9

0.9

1.0 1--+----J4---I----I

0.8
4.0

140

-60

s.O

6.0

VccM

t AA • tACS

vs. Temperature

I

1.2

TA = 2SOC
1.3

I

en 1.1

J-

1.0

0.9

0.8

I
I
Voc~5V

II

Vcc = SV

j

t AA • t ACS vs. Output Loading

V

/

/

V

en 1.2

V

Jj

1.1

1.0
0.9

-60

140

/

/

/

1
/

V

V
o

100

200
C L (pF)

TRUTH TABLE
MODE

CS

WE

OUTPUT

POWER

Standby

H

X

HighZ

Standby

Read

L

H

DATA OUT

Active

Write

L

L

HighZ

Active

CAPACITANCE (TA= +25°C, f
SYMBOL

PARAMETER(1)

C IN

Input Capacitance

COUT

Output Capacitance

= 1.0MHz)

CONDITIONS

MAX.

UNIT

VIN':" OV

7

pF

VOUT= OV

7

pF

NOTE:
1. This parameter is determined by device characterization and is not
production tested.

4-9

300

IDT6167SA/lDT6167LA CMOS. STATIC RAM (16K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxxx
Device Type

999
Speed

A

A

Package

Process!
Temperature
Range

y:""k

P
D
1----------1 L
SO
E
F
12
15
20
25
35
1-----------------145
55
70
85
100

~-------------------------41ILA
SA
1--_______________________--1 6167

4-10

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
, Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Flatpack
Commercial Only

Military Only
Military Only
Military Only
Military Only
Military Only

Speed in Nanoseconds

Standard Power
Low Power
16K (16K x 1-Bit) CMOS Static RAM

FEATURES:

DESCRIPTION:

• High-speed (equal access and cycle time)
- Military: 15/20/25/35/45/55/70/85/100ns (max.)
- Commercial: 15/20/25/35ns (max.)
• Low power consumption
- IDT6168SA
Active: 225mW (typ.)
Standby: 100~W (typ.)
-IDT6168LA
Active: 225mW (typ.)
Standby: 1O~W (typ.)
• Battery backup operation-2V data retention voltage
(IDT6168LA only)
• Available in high-density 20-pin CERDIP and plastic DIP,
20-pin SOIC, 20-pin Flatpack and CERPACK and 20-pin
leadless chip Carrier
• Produced with advanced CEMOS ™ high·performance
technology ,

The IDT6168 is a 16,384-bit high-speed static RAM organized as
4K x 4.lt is fabricated using lOT's high-performance, high-reliability technology-CEMOS. This state-of-the-art technology, combined with innovative circuit design techniques, provides a
cost effective alternative to bipolar and fast NMOS memories.
Access times as fast as 15ns are available with maximum p o w e r .
consumption of only 550mW:....!he circuit also offers a reduced ~
power standby mode. When CS goes high, the circuit wil!..£.utomatically go to, and remain in, a standby mode as long as CS remains high. In the standby mode, the device consumes less than
10~W, typically. This capability provides significant system-level
power and cooling savings. The low-power (LA) version also offers
a battery backup data retention capability where the circuit typically consumes only 1~W operating off a 2V battery.
All inputs and outputs of the IDT6168 are TTL-compatible and
operate from a single 5V supply, thus simplifying system deSigns.
Fully static asynchronous circuitry is used, which requires no
clocks or refreshing for operation, and provides equal access and
cycle times for ease of use.
The IDT6168 is packaged in either a space saving 20-pin, 300
mil CERDIP or plastic DIP, 20-pin flatpack or CERPACK, 20-pin
SOIC, or 20-pin leadless chip carrier, providing high board-level
packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• CEMOS process virtually eliminates alpha particle soft-error
rates
•
•
•
•
•
•
•

Bidirectional data input and output
Single 5V (±10%) power supply
Input and output directly TTL-compatible
Three-state outputs
Static operation: no clocks or refresh required
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing# 5962-86705 is listed on this
function. Refer to Section 21page 2-4.

FUNCTIONAL BLOCK DIAGRAM

LOGIC SYMBOL
AO
Al
A2
A3
A4
A5
A6
A7
A6
Ag
A10
All

CS

1/01

A
VCC
GND
ROW
SELECT

I/~

1/0:3

16.384-BIT
MEMORY ARRAY

A
COLUMN I/O

1/04

~

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1967 Inlegraled Device Technology. Inc.

4-11

DECEMBER 1987
OSC-l006/-

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6168SAJIDT6168LA CMOS STATIC RAM 16K (4Kx 4-BIT)

PIN CONFIGURATIONS
Ao

Vee

A,

A"

A2
A3

AlO

A4

As

-i.£.».i
A10

A2

Ag

A5

1/04

Aa
A7

1/0:3

~

1/0,

GND

wr:.

1I0z

A3

Ag

A4

As

A5
Aa

1104

A7

1I0z

110:3

1(1)°13
()Z
(!)

RECOMMENDED DC OPERATING CONDITIONS

PIN NAMES
Ao-All

Address Inputs

1/01-1/~

Data InpuVOutput

~

Chip Select

Vec

Power

WE

Write Enable

GND

Ground

MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

4.5

5.0

5.5

'V

GND

Supply Voltage

0

0

0

V

Input High Voltage

2.2

-

6.0

V

Input Low Voltage

-0.5(1)

-

0.8

V

SYMBOL

"'H
ABSOLUTE MAXIMUM RATINGS

VTERM

RATING
Terminal Voltage
with Respect to
GND

-

LCC
TOP VIEW

DIP/SOIC/FLATPACK/CERPACK
TOP VIEW

SYMBOL

6__

PARAMETER'

"'L
NOTE:
1. VrL (min.) = -3.0V for pulse width less than 20ns.

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

Oto +70

-55 to +125

°C

TA

Operating
Temperature

TerAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

4-12

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V

O°C to +70°C

OV

5.0V

Vee

± 10%
± 10%

- - - - - - - - - - - - - - - _ .. _---_...... _--_...

_ .._ - - - - - - - - - - - - - - - - -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K X 4-BIT)

DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V ±10%
SYMBOL

PARAMETER

TEST CONDITION

MIN.

IDT6168SA
Typ.(l) MAX.

Ilu l

Input Leakage Current

Vee = Max., VIN = GND to Vee

MIL.
COM'L.

-

-

10
2

IILOI

Output Leakage Current

Vec = Max.
CS" = VIH , VOUT = GND to Vcc

MIL.
COM'L.

-

10
2

VOL

Output Low Voltage

VOH

Output High Voltage

IOL = 10mA, Vcc = Min.

-

IOL = SmA, Vcc = Min.

-

-

2.4

-

-

IOH = -4mA, Vec = Min.

0.5
0.4

-

IDT6168LA
MIN. TYP.(l) MAX.

UNIT

-

5
2

J.l.A

-

5
2

J.l.A

-

-

-

0.5

V

-

0.4

V

2.4

-

-

V

NOTE:
1. Typieallimits are at Vcc = 5.0V, + 25.° C ambient.

DC ELECTRICAL CHARACTERISTICS (1)
Vce = 5.0V ±10%, VLC = 0.2V, VHC = Vce -0.2V
SYMBOL

PARAMETER

POWER

6168SA15
6168LA15

6168SA20
6168LA20

6168SA25
6168LA25

6168SA35/45(4)
6168LA35/45 (4)

COM'L MIL COM'L.MIL. COM'L MIL COM'L.

lecl

ICC2

ISB

ISBl

Operating Power
Supply Current
CS = VIL,
Outputs Open
Vce = Max.,
f = 0(3)
Dynamic
Operating Current
CS = VII...
Outputs Open,
Vec = Max.,
f = fMAX (3)
Standby Power
Supply Current
(TTL Level)
CS ?:VIH,
Vec = Max.,
Outputs Open, f = frvlAX(3)
Full Standby
Power Supply
Current (CMOS
Level)
CS ?: VHe '
Vec= Max.,

(3)
VIN ?: VHC or
VIN :5 VLC , f = 0

SA

90

100

90

100· 90

100

90

MIL
100

-

100

-

100
rnA

LA

70

SO

70

80

70

SO

70

SO

-

SO

-

SO

SA

120

130

120

120

110

120

100

110

-

110

-

110

LA

110

120

100

110

90

100

SO

90/S0

-

SO

-

SO

SA

45

50

45

45

35

45

30

35

-

35

-

35

LA

35

40

30

35

25

30

20

25

-

20

-

20

SA

20

20

20

20

2

10

2

10

-

10

-

10

rnA

rnA

rnA
LA

0.2

5

2

5

0.05

0.3

0.05

0.3

NOTES:
1. All values are maximum guaranteed values.
2. Also available 85 and 100ns military devices.
3.
4.

6168SA70(2)
6168LA70(2) UNIT
COM'L. MIL COM'L MIL
6168SA55
6168LA55

f = frvlAX (All inputs except Chip Select cycling at f = 1/~C>. f = 0 means no address or eontrollines change.
-55°C to + 125°C temperature range only.

4-13

-

0.3

-

0.3

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6168SAJIDT6168LA CMOS STATIC RAM 16K (4Kx 4-BIT)

DATA RETENTION CHARACTERISTICS
SYMBOL
VDR

ICCDR

(LA Version Only)
TEST CONDITION

PARAMETER

t cDR(5)

Chip Deselect to Data Retention Time

t R(5)

Operation Recovery Time

-

MIL.

0.5(2)
1.0(3)

100(2)
150(3)

JlA

COM'L.

-

0.5(2)
1.0(3)

20(2)
30(3)

JlA

-

-

0
t

RC

-

-

(2)

LOW Vee DATA RETENTION WAVEFORM

DATA RETENTION MODE
Vee

AC TEST CONDITIONS
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

5V

DATA OUT

~

2550

5V

48oa
DATA OUT
3OpF*

~

2550

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for t HZ ' t L2 • twz and tow)
* Including scope and jig.

4-14

V

ns
ns

NOTES:
1. TA = +25°C
2. atVcc = 2V
3. atVcc = 3V
4. t Rc = Read Cycle Time
5. This parameter is guaranteed but not tested.

Input Pulse Levels
Input Rise/Fall Times
Input TIming Reference Levels
Output Reference Levels
Output Load

UNIT

-

CS ~ Vcc -O.'N
V1N ~ Vee -O.'N or ~ O.'N

MAX.

2.0

Vcc for Retention Data

Data Retention Current

IDT6168LA
TYP(1)

MIN.

IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(Vcc = 5.0V ±10%, All Temperature Ranges)
6168SA15
6168LA15
MIN. MAX.

PARAMETER

6168SA20/25 6168SA35/45(1) 6168SA55(1) 6168SA70(1)
6168LA20/25 6168LA35/45(1) 6168LA55(1) 6168LA70(1) UNIT
MAX. MIN. MAX. MIN. MAX.
MIN.
MAX. MIN.

READ CYCLE
Read Cycle Time

15

-

20/25

-

35/45

-

55.

-

70

-

ns

tAA

Address Access Time

15

-

20/25

ns

-

20/25

35/45

-

70

15

-

55

Chip Select Access Time

-

35/45

t ACS

-

70

ns

tOH

Output Hold from Address Change

3

-

5

5

-

5

3

-

5

5

-

5

5

-

ns

Chip Select to Output in Low

-

5

tLZ

-

tHZ

Chip Deselect to Output in High

-

8

-

10

-

15

-

25

-

30

ns

t pu

Chip Select to Power Up Time (2)

0

-

0

-

0

-

0

-

0

-

ns
ns

.. t AC

Z(2)
Z (2)

55

ns

tpD

Chip Deselect to Power Down Time (2)

-

15

-

20/25

-

35/40

-

50

-

60

t ACS

Read Command Set-up Time

-5

-5

-

-5

-

-5.

-

ns

Read Command Hold Time

-5

-

-5

tRCH

-

-5

-

-5

-

-5

-

ns

-5

NOTES:
1. -55°C to -125°C temperature range only. Also available 85 and lOOns military devices.
2. This parameter is guaranteed but not tested.

4-15

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)

TIMING WAVEFORM OF READ CYCLE NO.

ADDRESS

_EI4----:RC'"
1(1,2)

------

tAA

------------~.'

tOH

DATA OUT

DATA VALID

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

2(1,3)

14------------ t RC (5) ------------10-1

DATA OUT

DATA VALID
HIGH IMPEDANCE

Vcc SUPPLY
CURRENT

NOTES:
1.
2.
3.
4.
5.
6.

wr:. is High for READ Cycle.
cg is low for READ cycle.

cs

Address valid prior to or coincident with
transition low.
Transition is measured ±2oomV from steady state voltage with specified loading in Figure 2.
All READ cycle timings are referenced from the last valid address to the first transitioning address.
This parameter is guaranteed and not 100% tested.

4-16

.__ ._-_.... _- ----

---------------.----------

IDT6168SAJIDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

-------

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(Vce = 5.0V ±10%, All Temperature Ranges)
6168SA15 6168SA20/25 6168SA35/45(1) 6168SA5S(1) 6168SA70(1)
6168LA15
6168LA20/25 6168LA35/45(1) 6168LA55(1) 6168LA70(1) UNIT
MIN. MAX. MIN.
MAX. MIN.
MAX. MIN. MAX. MIN. MAX.

PARAMETER

WRITE CYCLE
twe

Write Cycle Time

-15

-

20

tcw

Chip Select to End of Write

15

20

tAW

Address Valid to End of Write

15

-

t AS

Address Set-up Time

0

0

twp

Write Pulse Width

15

-

60

-

ns

50

-

60

-

ns

50

60

-

ns

0

50

-

-

ns

3

6

-

7

-

13/20

-

25

-

30

ns

-

0

-

0

-

0

-

0

-

ns

tWR

Write Recovery Time

0

tow

Data Valid to End of Write

9

tOH

Data Hold Time

3

-

twz

Write Enable to Output in HighZ(2)

-

tow

Output Active from End of Write(2)

0

20

20
0
13

NOTES:
1. -55°C to -125°C temperature range only. Also available 85 and 100ns military devices.
2. This parameter is guaranteed but not tested.

4-17

\

50

-

30/40
30/40
30/40

-

30/40

-

0

-

0

-

0

17/20

20
3

-

25

3

-

3

-

0

0

60

ns

ns
ns
ns

IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K x 4-BI1)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING) (1,2,3)

~----------------------twc----------------------~

ADDRESS

104----------- tAw ---------------~
t AS --~---------

(4)

DATA OUT

_ ____________________
DATA IN

~~-tD-w---~I-.---tD-H=:1----------

\C

DATA VALID

--->t-

TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLEDTIMING)(l,2,3,5)

two
ADDRESS

~

)(

----/ (
tAW

"- ~

/1'

_ t AS

tWA

tcw

_ __________________________________

-

-Kr----t-DW------~-I.-----tD-H-~~-------------

L

DATA VALID

--->I-

NOTES:

wr::.

1.
or ~ must be high during all address transitions.
2. A write occurs during the overlap (twp or t cw ) of a low ~ and a low
3. tWA is measured from the earlier of ~ or
going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals should not be applied.
p. If the ~ low transition occurs simultaneously with or after the
low transition, the outputs remain in the high impedance state.
6. Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).

wr::..

wr::.

wr::.

4-18

-_ ......_---_.__...._ - - - - - - - - - - - - - - - -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6168SAJIDT6168LA CMOS STATIC RAM 16K (4K X 4-BIT)

CAPACITANCE (TA= +25°C, f =

TRUTH TABLE
MODE

CS

WE

POWER

OUTPUT

PARAMETER(1)

SYMBOL

Standby

H

X

HighZ

Standby

CIN

Read

L

H

DoUT

Active

COUT

Write

L

L

DIN

Active

1.0MHz)

CONDITIONS

MAX.

UNIT

= OV

7.

pF

Vour - OV

7

pF

~N

Input Capacitance
Output Capacitance

NOTE.
1. This parameter is determined by device characterization, but is not
production tested.

NORMALIZED TYPICAL DC AND AC CHARACTERISTICS

lee vs. Supply Voltage

I SB vs. Supply Voltage

lee VS. Temperature .

.

T~ = 25 J

I
Vcc = 5.0V

0

1.5

TA =

J5 C
0

1.5

1.5

o

o

.Y
1.0

V

.Y

1/

1.0

.5

'"

1'-0...

.......

~~

.5

4.0

5.0

6.0

-60

140

1.0

V

.5
4.0

5.0

Vee (V)

ISB1

vs. Supply Voltage

ISB1

T1 = +25!C

Vee = 5.0V

1.5 t - - - - I - - - i - - - + - - - I

100.0 t - - - ' - + - - + - - - + - - - f

m

t----I-~..t---+---I

L.....-_--'_ _- ' -_ _-'--_~

-60

40

TA (0C)

140

vs. Temperature

1.2

_C/J

0.5

6.0

Vee (V)

I SB vs. Temperature

1.0

V

1.0

..; 10.0 1-----+--+---+-#---/

/

/

1.0

t----I-~'+---+---I

0.8

4.0

5.0
Vee (V)

4-19

6.0

-60

140

IDT6168SA/IDT6168LA CMOS STATIC RAM 16K (4K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NORMALIZED TYPICAL DC AND AC CHARACTERISTICS

I

V

.; 1K

100.0

TA

1--'---+--.j-----4-~

(tc)

1.2

'"

r\

CI)

~ 10.0 I--'---+--.j--~------l

10.0

'j.

~

"

100

o

vs. Supply Voltage

I

A

10K

1.0

I

Vee = 5.0V_
TA = 25°C

100K

t AA • t Acs

I CCDR vs. Temperature

vs. VIN

IS81

-

~

1.0 I----+--r+---+-~

.J
2

3
VIN

4

1.0

5

-60

6

'"

.8
4.0

140

I"

5.0

M

VeeM

t AA • t Aes vs. Temperature

t AA • t Acs vs. Output Loading

Vee = 5V

1.2

1.2

CI)

CI)

'j.

_<

A

Device Type

Power

999
Sp

d

A

A

Package

Processl
Temperature
Range

y:~k

...................................~

~

TP
P
TD
D
L
SO

E
F
25
30
35
45
~..................................................~55

70

90
120

150

ILA

~--------------------------~I SA

...............................................................................................~ 6116

~

4-43

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic THINDIP
Plastic DIP (600 MIL)
THINDIP (CERDIP)
CERDIP (600 MIL)
Leadless Chip Carrier (Indicate 24-,28- or
32-pin)
.
Small Outline IC
CERPACK
Flatpack

Commercial Only
Commercial Only
Military
Military
Military
Military
Military

Only
Only
Only
Only
Only

Low Power
Standard Power
16K (2K x 8-Sit) Static RAM

FEATURES:

DESCRIPTION:

• High speed (equal access and cycle time)
- Military: 25/30/35/45/55/70/85ns (max.)
- Commercial: 15/20/25/30/35/45ns (max.)

The IDT7187 is a 65,536-bit high-speed static RAM organized as
64K x 1.lt is fabricated using lOT's high-performance, high-reliability technology, CEMOS. Access times as fast as 15ns are available
with maximum power consumption of 880mW.
Both the standard (S) and low-power (L) versions of the IDT7187
provide two standby modes-lsB and ISBI. ISB provides low-power
operation (358mW max.); ISBI provides ultra-low-power operation
(5mW max.). The low-power (L) version also provides the capability for data retention using battery backup. When using a 2V battery, the circuit typically consumes only 30~W.
Ease of system design is achieved by the IDT7187 with full asynchronous operation, along with matching access and cycle times.
The device is packaged in an industry standard 22-pin, 300 mil
plastic or hermetic DIP, 24-pin plastic SOIC, 22- and 28-pin leadless chip carriers, or 24-pin flatpack or CERPACK.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• Low power consumption
- IDT7187S
Active: 300mW (typ.)
Standby: 100~w (typ.)
- IDT7187L
Active: 250mW (typ.)
Standby: 30~w (typ.)
• Battery backup operation - 2V data retention (L version only)
• JEDECstandard high-density 22-pin plastic and hermetic DIP,
24-pin plastic SOIC, 22-pin and 28-pin leadless chip carrier and
24-pin flatpack and CERPACK
• Produced with advanced CEMOS TN high-performance
technology
• Separate data Input and output
• Input and output directly TTL-compatible
•
•
•
•

Three-state output
Static operation: no clocks or refresh required
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing# 5962-86015 Is pending listing on
this function. Refer to Section 21page 2-4.

FUNCTIONAL BLOCK DIAGRAM

LOGIC SYMBOL

A
Ao

DATA IN

GND

A

Al
A2

A

A3
A4

A5
As
A7
A8
Ag

Vee

A

65,536-81T
MEMORY ARRAY

ROW
SELECT

A
A
DATAoUT

A 10
All

A
A
~

A12

A 13
A14

DATA OUT

A15

A

A

AA

A

AAA

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-l025/-

4-44

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7187S/IDT7187L CMOS STATIC RAM 64K (64K x 1-BIT)

PIN CONFIGURATIONS
Ao
Al

Vee

A2
A3
A4

A14
A12

Ao
Al
A2
A3
A4

As

All

NC

As
A7
DATAoUT

Ala
Ag

As

A1S
A13

wr=.

CS

GND

-i

~

LJ

i i

A14
A13
A12
All
NC
AlO
Ag

As
A6
A7
DATA OUT

As
DATA IN

9

As
DATA IN

WE

CS

GND

Vee
A1S

A3
A4

All
AlO
Ag

DIP
TOP VIEW
0

Ao
Al
A2

A13
A12
NC

WE

0

NC

A14

A6
A7
DATAoUT

As
DATA IN

Vee

A1S

CS

GND

FLATPACK/CERPACK
TOP VIEW

SOIC
TOP VIEW
It)

~.£
INDEX

U U
w 22 21

1

20 [
19 [:

A14
A13

lS [

A12

I"

I

L....I

L....I

2

Al

]

3
4

A2

]

I. '-'
I

I

U

I

1'1

L....I

5

2S 27
26 [
25 [

A14
A13

1

L22-1 17[

All

A3

]

6

24 [

16 [:

A12

A4

]

7

23 [

15 [

AlO
Ag

14 [

]

s

All
NC

As

NC
A5

]

9

21 [

As
A7

]
]

10
11

2Q[
19 £:

~ ~~ ~ Fo

I-'

~ ~ I~
~

~

~

L28-2

22[

DATAoUT

Ala
Ag
As
NC

Q

22-PIN LCC
TOP VIEW

PIN NAMES
Ao-A15

Address Inputs

DATAIN

Data Input

CS

Chip Select

DATAoUT

Data Output

WE

Write Enable

GND

Ground

Vee

Power

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

Q

28-PIN LCC
TOP VIEW

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

PT
lOUT

J

~

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

-55 to + 125

-65 to +150

Power Dissipation

1.0

1.0

W

DC Output Current

50

50

mA

MIN.

TYP.

MAX.

Vee

Supply Voltage

PARAMETER

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

"'IH

Input High Voltage

2.2

-

6.0

V

"'IL

Input Low Voltage

-0.5(1)

-

0.8

V

UNIT

NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.

°C

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

GRADE
Military
Commercial

4-45

AMBIENT
TEMPERATURE

GND

Vec

-55°C to + 125°C

OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V ± 10%

MILITARY AND COMMERCIAL TEMPERATURE RANGES

I DT71875/IDT7187L CM05 5TATIC RAM 64K (64K xl-BIT)

DC ELECTRICAL CHARACTERISTICS
Vee = 50V +10%
SYMBOL

TE5T CONDITION

PARAMETER

Ilu l

Input Leakage Current

Vee = Max., VIN

IlLOI

Output Leakage Current

\be
~

VOL

Output Low Voltage

VOH

Output High Voltage

NOTE:
.. 1. Typical limits are at Vee = 5.0V,

MIN.
MIL.
COM'L.

= GND to Vee

= Max.
= VIH , VOUT = GND to Vee
IOL = 10mA, Vee = Min.
IOL = 8mA, Vee = Min.
IOH = -4mA, Vee = Min.

MIL.
COM'L.

IDT71875
TYP'!') MAX.

-

-

2.4

-

10
5

-

-

MIN.

10
5
0.5

-

0.4

-

-

2.4

IDT7187L
TYP'!') MAX.

-

UNIT

5
2

J.l.A

5
2

J.l.A

0.5

V

0.4

V

-

V

+ 25°C ambient.

DC ELECTRICAL CHARACTERISTICS(1)
= 5.0V ±10%, VLC = 0.2V, VHC = Vec - 0.2V

Vee

SYMBOL

PARAMETER

POWER

7187520
7187L20

7187515
7187L15

7187S25
7187L25

7187530/35
7187L30/35

COM'LMIL COM'LMIL COM'LMIL COM'L

ICC1

ICC2

ISB

ISB1

Operating Power
Supply Current
CS = VIL,
Outputs Open
Vee = Max.,
f = 0(2)
Dynamic
Operating Current
CS = VIL,
Outputs Open,
Vee = Max.,
f = fMAX(2)
Standby Power
Supply Current
(TTL Level)
CS ~ VIH,
Vee = Max.,
Outputs Open
f = f MAX (2)
Full Standby
Power Supply
Current (CMOS
Level)
CS ~ VHC ,
Vee = Max.,
\'IN ~VHC or
\'IN ~ VLC ' f = 0(2)

S

135

-

120

140

90

105

90

7187545/55(3)
7187L45/5S(3)

MIL COM'L
105

90

7187570
7187L70

7187585
7187L85

UNIT

MIL COM'L MIL. COM'L.MIL.
105

-

105

-

105
mA

..... »L.

L

115

-

l~O\ •••• ~.~O

S

165

-

' 170

L

150

70

85

70

85

70

85

-

85

-

85

120

130

110

120

110

120

-

120

-

120

100

110

95/90

110/100

85

95

-

90

-

90

55

55

45

50

45

50

-

50

-

50

. . . . . • .:.:.
,">

S

I':!~

mA

155

.... :.

65}H. ·····>60

:.: .>.

65

mA

I>c:
L

5

5!.?j-"

>~2/

1~9 -

50

55

45

50

40/35

45/40

30/25

35/30

-

28

-

28

20

25

15

20

15

20

15

20

-

20

-

20
mA

L

2.5

-

NOTE5:
1. All values are maximum guaranteed values.
2. f = fMAX (All inputs except Chip Select cycling at f
3. -55°C to + 125°C tem~r~ture range only.

1.0

2.0

0.3

1.5

0.3

1.5

0.3

1.5

= lltRd. f = 0 means no address or control lines change.

4-46

-

1.5

-

1.5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT7187S/IDT7187LCMOS STATIC RAM 64K(64Kx 1-BIT)

DATA RETENTION CHARACTERISTICS

(L Version Only) VLC = 0 2V VHC

= Vcc -

0 2V
TYP.(l)

SYMBOL

TEST CONDITION

PARAMETER

Vee @

MIN.

2.0V
VDR

-

Vec for Data Retention

I

MIL.
COM'L.

ICCDR

Data Retention Current

t CDR (3)

Chip Deselect to Data Retention Time

t R(3)

Operation Recovery Time

lIu l (3)

Input Leakage Current

CS~ VHC
VIN ~ VHC or ~ VLC

3.OV

MAX.
Vee @
2.0V
3.OV

2.0

-

-

-

-

-

10

15

600

900

-

10

15

150

225

t RC (2)

-

-

-

0

-

NOTES:
1. TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.

LOW Vee DATA RETENTION WAVEFORM

DATA RETENTION MODE
VCC

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND t03.0V
5ns
1.5V
1.5V
See Figures 1 and 2

5V

DATAoUT

~

2550

5V

4800
DATA OUT
30pF*

~

2550

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for t HZ ' t LZ • twz and tow)
* Including scope and jig.

4-47

UNIT
V
J.LA
ns

-

ns

2

J.LA

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7187S/IDT7187L CMOS STATIC RAM 64K (64K x 1-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc = 5V ±10%, All Temperature Ranges)

7187S85(2)
7187S15(l)/20
7187S35/45 7187S55(2) 7187S70(2)
7187S25/30
7187L85 (2) UNIT
7187L15(l~20
7187L25/30
7187L35/45 7187L55(2) 7187L70(2)
MAX.
MAX. MIN.
MAX. MIN. MAX. MIN. MAX. MIN.
MIN.
MAX. MIN.

PARAMETER

READ CYCLE
Read Cycle Time

t RC

25/30

-

35/45

-

55

-

70

-

85

-

ns

:i)\1:5/20

-

25/30

-

35/45

55

-

70

ns

-

25/30

-

35/45

55

-

70

-

85

.:.:::;:;::) 5/20

-

85

ns

-

5

-

5

5

-

5

-

ns

-

5

5

-

5

-

5

~

-

5

-

ns

7/8

-

20/25

-

25/30

-

30

-

30

-

40

ns

-

0

-

0

-

0

-

0

-

0

-

ns

15/20

-

20/30

35

-

40

ns

;',

15/20

;.;.;;;:;::::;."

tAA

Address Access Time

t ACS

Chip Select Access Time

-

tOH

Output Hold from Address Change

5

tLZ

Chip Select to Output in Low Z (3)

5.:::i::;:::::::

tHZ

Chip Deselect to Output in High Z (3)

-::.::":':::::

t pu

Chip Select to Power Up Time (3)

tpD

Chip Deselect to Power Down
Time (3)

9.:::\:::::::+:. : :

-

30/35

-

35

-

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.

TIMING WAVEFORM OF READ CYCLE NO.1

(1,2)

f=1-ot------------

ADDRESS

--------, t=

DATA OUT

IOH

1M

t RC (5)

------~.'
DATA VALID

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.2

(1,3)

14---------

tRC(5)---------~

tLZ (4)
DATA OUT

DATA VALID
HIGH IMPEDANCE

Vee SUPPLY
CURRENT

~----~~~~~~~~~~~~

NOTES:
1.
2.
3.
4.
5.

wt:. is High for READ Cycle.
CS is low for READ cycle.
Address valid prior to or coincident with
transition low.
Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
All READ cycle timings are referenced from the last valid address to the first transitioning address.

cs

4-48

- - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ m_ .. _ _ _ _ _ _ _ _

I D17187S/1 DT7187L CMOS STATIC RAM 64K (64K x 1-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

_

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(Vcc = 5V \10%. All Temperature Ranges)

7187S15(1)/20
7187S25/30
7187S35/45 7187S55(2) 7187S70(2)
7187S85(2)
7187L15(1)/20
7187L25/30
7187L35/45 7187L55(2) 7187L70(2)
7187L85(2) UNIT
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN. MAX. MIN. MAX. MIN.
MAX.

PARAMETER

WRITE CYCLE

twc

Write Cycle Time

13/17

.:\\:::c..

25/30

-

35/45

-

55

-

70

-

85

tcw

Chip Select to End of Write

13/17

/G}::::~

20/25

-

30/40

-

50

-

55

-

65

ns

tAW

Address Valid to End of Write

13/17

:::t::?:::::·
.::;)I::::::· -

20/25

-

30/40

-

50

-

55

-

65

ns

t As

Address Set-up Time

twp

Write Pulse Width

tWR

Write Recovery Time

0

ns

0

-

0

-

0

-

0

-

0

ns

13/1~::;:::::::::::;::

-

20

-

25/30

-

35

-

40

-

45

ns

O:{:(::;::::·

-

0

-

0

-

0

-

0

-

0

ns

~~to~W~+-D-m-a-V-al-id-t-o-E-n-d-o-fW--rit-e------~8-/~iO~:·:::~:\~/------~15-/-20------~-2-0-~-5-------+-2-5------_r-3-0-----~--35--------+--n-s-4~
:9:/:;;;:-=

tOH

Data Hold Time

twz

Write Enable to Output in High

tow

Output Active from End of Write (3)

Z(3)

.:::lH::::::;

::tXt.

-

5

-

5

-

5

-

5

-

5

-

ns

5/6

-

20/25

-

25/30

-

30

-

30

-

40

ns

o

o

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.

4-49

o

o

o

ns

___

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7187S/IDT7187L CMOS STATIC RAM 64K (64K xl-BIT)

TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)

(1,2,3)

~..................................................--twc--""''''''''''''''''''''''''''''''''''''''''''''''~

ADDRESS

twp - - - - - - - t

t WZ

(5)

.....--_toW(5) _ _~

DATA OUT
_

:~_tDw_tDH~._
1'----..f

_

DATA IN

DATA VALID

TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)

(1,2,3,4)

twc

ADDRESS

~K

)(
tAW

'~
I + - - t AS

____________________

DATA IN

/~
tWR

tcw

-

~:~-tD-w---~-I.---tD-"~:~-----

1'--

DATA VALID

---..f

NOTES:

1.
2.
3.
4.
5.

WE or CS must be high during all address transitions.
A write occurs during the overlap (tw~ of a low ~ and a low WE.
tWR is measured from the earlier of ~ or WE going high to the end of the write cycle.
If the CS low transition occurs simultaneously with or after the wr:. low transition, the outputs remain in the high impedance state.
Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).

4-50

IDT7187S/IDT7187L CMOS STATIC RAM 64K (64K x 1·BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE

CAPACITANCE

MODE

CS

WE

Standby

H

Read
Write

SYMBOL

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

OUTPUT

POWER

X

HighZ

Standby

C'N

Input Capacitance

L

H

DoUT

Active

C OUT

Output Capacitance

L

L

HighZ

Active

CONDITIONS

MAX.

\IN:d OV

8

pF

VOUT= OV

8

pF

NOTE:
1. This parameter is determined by device characterization, but is not
production tested.

ORDERING INFORMATION
IDT

xxxxx

A

Device Type

Power

999
Speed

A

A

Package

Process/
Temperature

UNIT

RMy~Mk

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL·STD·883, Class B

P
C
L

~--------------~ SO

E
F
15
20
25
30
'----------------~ 35
45
55
70
85

~--------------fl S

I L

~----------------------~ 7187

4-51

Plastic DIP
Sidebraze DIP
Leadless Chip Carrier (specify 22! 28 pins)
Small Outline IC
CERPACK
Flatpack

g~~~:~~::: g~:~ }
Speed in Nanoseconds
Military Only
Military Only
Military Only
Standard Power
Low Power
64K (64K x 1·Bit)

FEATURES:

DESCRIPTION:

• 65,536-words x 1-bit organization
• Low power dissipation: 320mW (typ.)
• Fully compatible with 100K logic level

The IDT100490 is a 100K compatible 65,536-bit high-speed
BiCEMOS ™ ECl static RAM organized as 64K x 1.
The IDT100490 is available with address access times as fast as
15ns with a typical power consumption of only 320mW. This product offers the advantages of low-power operation, without sacrificing speed, by integrating a dense high-speed CMOS static RAM
with internal level conversion. This allows the designer to reduce
package count in an ECl system without increasing either power
dissipation or access time.
Designed for very high-speed applications, the IDT100490 is
fully compatible with standard ECl 100K logic levels and offers extremely fast access times. The address access time of 15ns and
write pulse width of 10ns assure that operations of this BiCEMOS
part will be as fast as those available with less dense parts requiring
external address decoding.
The IDT100490 is fabricated using lOT's high-performance,
high-reliability BiCEMOS technology. Operating power dissipation is extremely low compared with most ECl-compatible bipolar
devices, lowering power supply and cooling requirements.

• Address access time: 15/20ns (max.)
• Write pulse width: 10ns (min.)
• Open emitter output for ease of memory expansion
• Static operation: no clocks or refresh required
• Separate data input and output
• JEDEC standard high-density 22-pin plastic and sidebraze DIP
and 24-pin Small Outline IC

LOGIC SYMBOL

PIN CONFIGURATIONS
vee

DATAoUT
Ao

DATA IN

A,
A2
A3
A4

C"S"

A5

A6

A'3
A'2

A7

A"

~

~o
Ag

wr:
A,S
A'4

VEE

DIP, TOP VIEW

Ao

DATA IN

FUNCTIONAL BLOCK DIAGRAM
Ao

A,
A2
A3
A4

DECODER

65,536-BIT
MEMORY ARRAY

As
Aa

A7
As
Ag
AIO
A"
A'2
A

DATAoUT

I/O CONTROL

DATA OUT

'3

Vee

DATAoUT
Ao

DATA IN

A,
A2

C"S"

A3

NC

~.

~5

A5

~4
~3
~2

A'4
A '5

wr:

A6
~

~,

As
NC

A
'0
Ag

VEE

SOle, TOP VIEW

BiCEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 1987

© 19S7 Integrated Device Technology, Inc.

DSC-loo4/-

4-52

IDT100490 HIGH SPEED BICMOS
ECL STATIC RAM 64K (64K x 1-BIT)

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS
SYMBOL

CAPACITANCE

(1)

VALUE

RATING

UNIT

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +85

°C

TBIAs

Temperature
Under Bias

-55 to + 125

°C

TSTG

Storage
Temperature

PT

Power Dissipation

lOUT

+0.5 to -7.0

V

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

SYMBOL
C IN

Input Capacitance

C OUT

Output Capacitance

CONDITIONS

TYP.

-

UNIT

6

pF

6

pF

TRUTH TABLE (1)

I Hermetic
I Plastic

-65 to + 150
-55 to + 125

°C

1.0

W

DC Output Current (Output High)

-50

mA

cs

WE

H
L
L

DATA OUT

FUNCTION

X

L

Deselected

H

RAM Data

Read

L

L

Write

NOTE:
1. H = High, L = Low, X = Don't Care

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
(VEE = -4.5V. RL = 500 to -2.0V, TA = 0 to
SYMBOL
VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VOHC

Output Threshold HIGH Voltage

VOLC

Output Threshold LOW Voltage

"'H

+ 85 ce, air flow exceeding 2m/sec)
TEST CONDITIONS

PARAMETER

Input HIGH Voltage

"'L

Input LOW Voltage

IIH

Input HIGH Current

"'N = VIHB or VILA
Guaranteed Input Voltage High/Low
for All Inputs
Guaranteed Input Voltage High/Low
for All Inputs
"'N

MAX. (A)

UNIT

-955

-880

mV

-1810

-1715

-1620

mV

-1035

-

-

mV

-1610

mV

-1165

-

-880

mV

-1810

-

-1475

mV

220

~A

170

~A

-50

-

-120

-70

-

mA

-

-

= VIHA

Ics
I Others

IlL

Input LOW Current

"'N = VILB

lEE

Supply Current

All inputs and outputs open

TYP.(l)

-1025

MIN. (B)

orVILB
"'N = VIHA
= VIHA orV ILB
"'N
"'N = VIHB or VILA

0.5

~A

NOTE:
1. Typical parameters are specified at VEE = -4.5V, TA = +25°C and maximum loading.

LOAD CONDITION

INPUT PULSE

Test Circuit
Vee (GND)

~%
-1.7V

~ ~_2_0_%_ _

30pF*

tR =tF = 2.0ns typo

-2.0V

*Includes probe and jig capacitance.

4-53

IDT100490 HIGH SPEED BICMOS
ECl STATIC RAM 64K (64K X 1-BIT)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
PARAMETER

SYMBOL

(VEE

= -4.5V ±5%, TA = 0 to

TEST CONDITION

+85°C, air flow exceeding 2m/sec)
IDT100490S15
MAX.
MIN.

IDT100490S20
MIN.
MAX.

UNIT

READ CYCLE
tAcs

Chip Select Access Time

-

Chip Select Recovery Time

-

-

10

t RCS
tAA

Address Access Time

-

-

15

-

10

10

ns

10

ns

20

ns

TIMING WAVEFORM OF READ CYCLE NO.1

\---------f%
~
----.j.'
r
t ACS

t""

. DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.2

ADDRESS

DATA OUT

RISE/FALL TIME
SYMBOL

PARAMETER

tR

Output Rise Time

tF

Output Fall Time

TEST CONDITION

-

-

4-54

IDT100490.
TYP.

MIN.

I
I

2
2

MAX.

I
I

-

UNIT
ns
ns

IDT100490 HIGH SPEED BICMOS
ECl STATIC RAM 64K (64Kx 1-BIT)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(VEE = -4.5V ±5%. TA = 0 to +85°C. air flow exceeding 2m/sec)

PARAMETER

TEST CONDITION

IDT100490S15
MIN.
MAX.

IDT100490S20
MIN.
MAX.

UNIT

WRITE CYCLE
15

2

-

-

3

-

4

Chip Select Set-up Time

-

2

3

t WHCS

Chip Select Hold Time

3

tws

Write Disable Time

tWR

Write Recovery Time

-

-

tw

Write Pulse Width

t wsA = minimum

10

t WSD

Data Set-up Time

2

tWHD

Data Hold Time

-

t WSA

Address Set-up Time

tw= minimum

tWHA

Address Hold Time

twscs

3

-

TIMING WAVEFORM OF WRITE CYCLE

ADDRESS

50%-

1+---- twsA---'*'t---DATAoUT

/4-------

twscs

----+loll--

4-55

tws

ns

4

-

10

-

10

ns

18

-

23

ns

3
4
3

ns
ns
ns
ns
ns
ns

1DT100490 HIGH SPEED BICMOS
ECl STATIC RAM 64K (64K x 1-BIT)

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
IDT

xxxxx

A

A

A

Device Type

Power

Package

Process!
Temperature
Range

~_k
~--------------~

P

C

SO
~

______________________

~

S

~----------------------------------------; 100490

4-56

+ 70°C)

Plastic DIP
Sidebraze DIP
Small Outline IC

15
20

~------------------------------~

Commercial (O°C to

} Speed in Nanoseconds
Standard Power
64K (64K x 1-Bit) BiCMOS ECl Static RAM

FEATURES:

DESCRIPTION:

• High-speed (equal access and cycle times)
- Military: 20/25/30/35/45/55{70/85ns (max.)
- Commercial: 15/20/25/30/35/45ns (max.)
• Low power consumption
- ID17188S
Active: 350mW (typ.)
Standby: 100}JW (typ.)
-ID17188L
Active: 300mW (typ.)
Standby: 30}JW (typ.)
• Battery backup operation-2V data retention
(L version only)
• Available in high-density industry standard 22-pin, 300 mil
ceramic and plastic DIP, 24-pin SOIC, 24-pin Flatpack and
CERPACK
• Produced with advanced CEMOS ™ technology
• Single 5V (±10%) power supply
• Inputs/outputs TTL-compatible
• Three-state outputs
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STD-883, Class B

The ID17188 is a 65,536-bit high-speed static RAM organized as
16K x 4. It is fabricated using IDT's high-performance, highreliability technology-CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost effective approach for memory intensive applications.
Access times as fast as 15ns are available, with typical power
consumption of only 300mW. The ID17188 offers a reduced power
standby mode, ISB1, which enables the designer to greatly reduce
device power requirements. This capability significantly decreases system power and cooling levels, while greatly enhancing
system reliability. The low-power version (L) version also offers a
battery backup data retention capability where the circuit typically
consumes only 30}JW operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate from a
single 5V supply. Fully static asynchronous circuitry, along with
matching access and cycle times, favor the simplified system design approach.
The ID17188 is packaged in 22-pin, 300 mil ceramic and plastic
DIPs, 24-pin SOICs, flat packs and CERPACKs, providing excellent
board-level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

LOGIC SYMBOL

A
Ao
Al
A2
A3
A4
A5
A6
A7
As
Ag
A l0
All
A12
A 13

I/~

Vcc
GND
DECODE

I/~

lIDs

65.536-BIT
MEMORY ARRAY

A
COLUMN 1/0

1/04

~~~~--------------------------------~

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology, Inc.

DECEMBER 1987
OSC-l026/-

4-57

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7188S/IDT7188L 64K (16K x 4-Bln CMOS STATIC RAM

PIN CONFIGURATIONS

Ao
Al
A2
A3
A4

Vee
A13
A12
A11
AlO
Ag

As

1/04

Ae
A7
A6

I/O:!

cs

1/02
1/01

GND

WE

DIP
TOP VIEW

FLATPACKlCERPACKlSOIC
TOP VIEW

PIN NAMES

RECOMMENDED DC OPERATING CONDITIONS

Ao-A13

Address Inputs

1/01 -1/04

Data 110

CS

Chip Select

Power

WE

Write Enable

Vee
GND

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

SYMBOL

Ground

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TB1AS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

PARAMETER

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

'-"H

Input High Voltage

2.2

6.0

V

'-"L

Input Low Voltage

-0.5(1)

-

0.8

V

'.

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
IN GS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

4-58

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND
OV

5.0V ± 10%

O°C to +70°C

OV

5.0V ± 10%

Vee

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7188S/IDT7188L 64K (16K x 4-BIT) CMOS STATIC RAM

DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V +10%
SYMBOL

PARAMETER

TEST CONDITION

lIu l

Input Leakage Current

IlLOI

Output Leakage Current

VOL

Output Low Voltage

VOH

Output High Voltage

MIN.

= GND to Vcc

MIL.
COM'L.

-

-

-

-

'OS" = VIH , Your = GND to Vcc

MIL.
COM'L.

-

Vcc = Max., VIN

Vee =

Max.

IOL = 10mA,Vcc = Min.

-

10L = 8mA, Vcc

-

= Min.
10H = -4mA, Vcc = Min.

NOTE:
1. Typical limits are at Vee = 5.0V,

IDT7188S
TYP.(l) MAX.
10
5

-

10
5

-

2.4

MIN.

-

0.4

-

-

2.4

0.5

IDT7188L
Typ.(l) MAX.

-

UNIT

5
2

J.l.A

5
2

J.l.A

0.5

V

0.4

V

-

V

+ 25°C ambient.

DC ELECTRICAL CHARACTERISTICS (1)
= 5.0V ±10%, VLC = 0.2V, VHC = Vcc - 0.2V

Vcc

SYMBOL

PARAMETER

POWER

7188S15
7188L15

7188S20
7188L20

7188S25
7188L25

7188S30/35
7188L30/35

COM'LMIL COM'L MIL COM'L. MIL COM'L MIL

ICCl

Icc2

IS9

IS91

Operating Power
Supply Current
CS = VIL,
Outputs Open
Vcc = Max.,
f = 0(2)
Dynamic
Operating Current
CS = VIL,
Outputs Open,
Vee = Max.,
f = fMAX(2)
Standby Power
Supply Current
(TTL Level)
CS ~ VIH,
Vcc = Max.,
Outputs Open
f = fMAX(2)
Full Standby
Power Supply
Current (CMOS
Level)
cg~ VHC '
Vee = Max.,
VIN ~ VHC or

\IN ~ VLC
f = 0(2)

S

135

-

L

115

-

.:lJ>. 1••~0
;i;:;~,

,,,

..

7188S45/55(3)
7188L45/55(3)

7188S70
7188L70

7188S85
7188L85

UNIT

COM'L MIL COM'L MIL COM'L. MIL

100

125

100

110

100

110

-

110

-

110

85

110

85

95

85

95

-

95

-

95

135

155

125

140

125

140

-

140

-

140

mA

.<

1~5b170

S

175

-

L

160

_ 114:,
ijA1>
..

mA
155

125

145 115/105125/115

100

110

-

110

-

105

70

55

60

45

50

-

50

-

50

/

S

j)

75

U.
<>
L

S

65

<

..••••...

~.

:"" ..

mA

;~

60

45

50

20

25

15

20

--

l;:~

50/45 55/50

40/35 45/40

15

20

30

35

-

35

-

35

15

20

-

20

-

20
mA

L

~dL

1.0

2.0

0.5

1.5

0.5

1.5

0.5

NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1ltRC. f
3. -55°C to + 125°C temperature range only.

4-59

1.5

-

1.5

-

= 0 means no input lines change.

1.5

I DT7188S/1 DT7188L 64K (16K x 4-BIT) CMOS STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VlC = O.2V. VHC = Vcc - O.2V
SYMBOL
VOR
ICCOR

TEST CONDITION

PARAMETER

MIN.

-

Vee for Data Retention
Data Retention Current

t COR (3)

Chip Deselect to Data Retention Time

t R(3)

Operation Recovery Time

Ilu l (3)

Input Leakage Current

CE ?VHC
? VHC or::; VlC

I MIL.
I COM'L.

~N

Typ.(1)
Vcc @
2.0V
3.0V

MAX.
Vee @
3.0V
2.0V

2.0

-

-

-

-

-

10

15

600

900

-

10

15

150

225

-

0
t RC (2)

-

NOTES:
1. TA = 25°C
2. t RC = Read Cycle Time
3. This parameter Is guaranteed but not tested.

~,

LOW Vee DATA RETENTION WAVEFORM

DATA RETENTION MODE
VCC

VOR ~ 2V

4.5V

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

5V

DATAoUT

~

2550

5V

4800
DATA OUT
30pF*

~

2550

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for t HZ' t LZ • twz and tow)
* Including scope and jig.

4-60

UNIT
V
~A

-

ns

-

ns

2

~A

IDT71 BBS/IDT71 BBl 64K (16K x 4-BIT) CMOS STATIC RAM

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc = 5.0V ±10%, All Temperature Ranges)

71BBS15(1)
71BBl15(1)
MIN. MAX.

PARAMETER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

71BBS20(4)
71BBL20(4)
MIN.
MAX.

71BBS35/45 71 BBS55/70(2) 71BBSB5(2)
71BBl35/45 71 BBl55/70(2) 71BBlB5(2) UNIT
MIN.
MAX. MIN. MAX. MIN. MAX.

71BBS25/30
71BBL25/30
MIN.
MAX.

READ CYCLE
t RC

Read Cycle Time

15

-

20

tAA

Address Access Time

15

-

tACS

Chip Select Access Time

-

tOH

Output Hold from Address Change

5

- .:;;: 1"'::::;:::5:::'

tLZ

Chip Selection to Output in Low Z(3)

5

tHZ

Chip Deselect to Output in High Z(3)

tpu

Chip Select to Power Up Time (3)

tpD

Chip Deselect to Power Down Time(3)

...~:\:::::::::::::':'

15

-

-

25/30

-

35/45

-

55{70

-

85

-

ns

-

25/30

35/45

-

85

ns

35/45

-

55{70

25/30

-

55{70

-

85

ns

5

-

5

-

5

-

5

-

ns

5

-

5

-

5

-

5

-

5

-

ns

-

8

-

10/13

-

15

-

20/25

-

30

ns

-

0

-

0

-

0

-

0

-

0

-

ns

15

-

20

-

25/30

-

35/45

-

55{70

-

85

ns

.::::.""<;:::::::
-.::::.:,,:'\:(:::1':'

':::Q:::::::::

. :::::::::, 11M>

S

75

140

'~<'''''''
150

mA

1-""'-

mA

..

115/105 125/115

-,-.'

~LLevel)

~VIH'
Vee = Max.,
Outputs Open f

6198S30/35
6198L30/35
COM'L MIL

<-

1

mA

1

-

rnA
L

2.5

-

1.0

2.0

0.5

1.5

0.5

1.5

0.5

1.5

-

1.5

-

1.5

NOTE5:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
3. -55°C to + 125°C temperature range only.

4-77

/

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7198S/IDT7198L CMOS STATIC RAM 64K (16K x 4-BIT)

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES

(L Version Only) VLC = O.2V, VHC

= Vcc

- 0 2V
TYP.(t)

SYMBOL·
VDR

TEST CONDITION

PARAMETER

MIN.

-

Vee for Data Retention

I COM'L.
MIL.

ICCDA

Data Retention Current

t CDR (3)

Chip Deselect to Data Retention Time

t R(3)

Operation Recovery Time

lIu l (3)

Input Leakage Current

CS~

"'IN

VHC

~ VHC ors VLC

Vee @
2.0V
3.0V

MAX.
Vee @
2.0V
3.0V

2.0

-

-

-

-

-

10

15

600

900

10

15

150

225

-

-

ns

-

-

ns

-

-

2

IlA

DATA RETENTION MODE
VCC

AC TEST CONDITIONS·
GNDto3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

:q

5V

2550

:q

5V

48OO
DATAOLrr
3OpF*

2550

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for tCLZt, 2' tOLZ' t CHZ1 , 2. tOHZ'

tow and t WHZ )
* Including scope and jig.

4-78

IlA

0

LOW Vee DATA RETENTION WAVEFORM

DATAoLrr

V

t RC (2)

NOTES:
1. TA = +25°C
2. t Rc = Read Cycle Time
3. This parameter is guaranteed but not tested.

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

UNIT

IDT7198S/IDT7198L CMOS STATIC RAM 64K (16K X 4-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(Vee = 5V ±100/0, All Temperature Ranges)

7198555(2) 7198570(2) 7198585(2)
7198S15(1)/20(5) 7198S25/30
7198S35/45
7198L15(1)/20(5) 7198l25/30
7198L55(2) 7198L70(2) 7198L85 (2) UNIT
7198L35/45
MAX. MIN.
MAX. MIN.
MAX. MIN. MAX. MIN. MAX. MIN.
MAX.
MIN.

READ CYCLE
25/30

-

35/45

-

55

-

70

-

85

-

25/30

-

55

-

70

ns

35/45

-

55

-

70

-

85

25/30

-

35/45

·····<15/20

-

85

ns

i_

5

-

5

-

5

-

5

-

"5

-

ns

....•.............~.

t RC

Read Cycle Time

tAA

Address Access Time

-

15/20

tACS1.2

Chip Select-1, 2 Access Time (3)

-

t CLZ1 . 2

Chip Select-1, 2 to Output in
Low Z(4)

5

15/20

ns

tOE

Output Enable to Output Valid

-

12/15

-

15/20

-

20/25

-

35

-

45

-

55

ns

toLZ

Output Enable to Output in
LowZ(4)

5

-

5

-

5

-

5

-

5

-

5

-

ns

tCHZ1.2

Chip Select-1, 2 to Output in
High Z(4)

-

.......•.........•......... 7/8

-

10/13

-

15

-

20

-

25

-

30

ns

tOHZ

Output Disable to Output in
High Z(4)

~.•

7/8

-

15

-

15

-

20

-

25

-

30

ns

tOH

Output Hold from Address
Change

5/.

-

5

-

5

-

5

-

ns

tpu

0

-

0

0

-

0

-

5

-

-

5

Chip Select to Power Up Time (4)

0

-

ns

tpD

Chip Deselect to Power Down
Time (4)

15/20

-

25/30

-

35/45

-

55

-

70

-

85

ns

< ...............

:

•.••.•.•••••••••..

.··9&··.···.··.

;'1

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. Both chip selects must be active low for the device to be selected.
4. This parameter guaranteed but not tested.
5. Preliminary data only for military devices.

4-79

·IDT7198S/IDT7198L CMOS STATIC RAM 64K (16K x 4-81T)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1 (1)

~.·CIo4l-_

-_tRC-=---=

ADDRESS

--t""~I-------- tAA _____""'--~.

I

i 0 0 i - - - - - tOE ----~
tOLZ(5)--~

1 4 - - - - - t ACS1 ' t ACS2 ----+--~
t CLZ1 , tCLZ2(5)----~

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.2

ADDRESS

(1,2,4)

~---------

--------------f

=1
= = =~-=-~ =:~=:_-=:_-=:_-= t=OH= ~ =-~-=-~-=~ :):I:~==================~=:)K:
lc~
tRC

~1~.:::.-=--=--:..-------tAA-----~-----I-=--=--=--:. .-1- - -

DATA OUT

..

TIMING WAVEFORM OF READ CYCLE NO.3 (1,3,4)

i 0 0 i - - - - - t ACS1 ,t ACS2 - - - - + i
tCLZ1 ' tCLZ2 (5)

DATA OUT

Vcc SUPPLY Icc - - - - - - - CURRENT
ISB

_ _ _ _ _...J

NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, ~ 1 = V IL ' ~ 2 = V1L•
3. Address valid prior to or coincident with ~1 and or ~2 transition low.
4. DE' = "'IL
5. Transition is measured ±200mV from steady state.

4-80

tOH

--I

1:======

IDT7198S/IDT7198L CMOS STATIC RAM 64K (16K x 4-BIT)

AC ELECTRICAL CHARACTERISTICS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(\be = 5V ±10%, All Temperature Ranges)
7198585(2)
7198S55 (2) 7198S70(2)
7198S25/30
7198S35/45
7198L85(2)
7198L55(2) 7198L70(2)
UNIT
7198L25/30
7198L35/45
MAX.
MAX. MIN.
MAX. MIN.
MAX. MIN. MAX. MIN. MAX. MIN.

7198515(1)/20(5)
SYMBOL

PARAMETER

7198L15(1~20(5)

MIN.
WRITE CYCLE
twc

Write Cycle Time

13/17

t CW1 . 2

Chip Select to End of Write (3)

13/17

tAw
t AS
twp

Address Valid to End of Write

13/17

Address Set-up Time
Write Pulse Width

t WR1 . 2

Write. Recovery Time

tWHZ

Write Enable to Output High Z(4)

tDW

Data Valid to End of Write

tDH

Data Hold Time

tow

Output Active from End of
Write (4)

0

O}
'/5>

ns
ns

0

6/7

-

7/10

-

10/15

-

25

-

30

-

40

ns

-

13/15

-

15/20

-

25

30

-

ns

-

0

-

0

0

-

35

0

-

0

-

ns

-

5

-

5

-

5

-

5

-

5

-

ns

..

20/25

13/17 : / -

8/10::

-

-

20/25
20/25

:/-

0./
- :>::::::::::::.

75
75

-

·:.b::::::

E' Is low during a WE controlled write cycle. the write pulse width must be the greater of twp or (tWHZ + tow) to allow the i/O drivers to turn off
and data to be placed on the bus for the required tow. If (jE" is high during a WE controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified twp.
8. (jE" = VIH

4-82

.MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7198S/IDT7198L CMOS STATIC RAM 64K (16Kx 4-BIT)

CAPACITANCE

TRUTH TABLE
MODE

CS1 CS2 WE

OE

I/O

SYMBOL

POWER

Standby

H

X

X

X

High Z

Standby

Standby

X

H

X

X

HighZ

Standby
Active

Read

L

L

H

L

Dour

Write

L

L

L

X

DIN

Active

Read

L

L

H

H

HighZ

Active

CIN

(TA= +25°C f = 10MHz)

PARAMETER(1)

CONDITIONS

MAX.

UNIT

\IN= OV

7

pF

Input Capacitance

Output Capacitance
7
pF
Cour
Vour= OV
NOTE:
1. This parameter is determined by device characterization, but is not
production tested.

ORDERING INFORMATION
;IDT

xxxxx

A

A

Device Type

Package

Process/
Temperature

~y:'~k

.......--------1

P
C
L
SO
Y
E
F

15
20
25
30
35
45
55
70
85
~

______________________--II S
IL

......._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 7198

4-83

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STO-883, Class B

Plastic DIP
Sidebraze DIP
Leadless Chip Carrier
Small Outline IC (Gull Wing)
Small Outline IC (J-bend)
. CERPACK
Flatpack

Commercial Only

Speed in Nanoseconds
Military Only
Military Only
Military Only
Standard Power
Low Power
64K (16K x 4-Bit)

FEATURES:

DESCRIPTION:

• Separate data inputs and outputs

The 10171981/10171982 are 65,536-bit high-speed static RAMs
organized as 16K x 4. They are fabricated using lOT's highperformance, high-reliability technology- CEMOS. This state-ofthe-art technology, combined with innovative circuit design techniques, provides a cost effective alternative to bipolar and fast
NMOS memories.
Access times as fast as 15ns are available with typical power
consumption of only 300mW. These circuits also offer a reduced
power standby mode (lsB). When CS , goes high, the circuit will
automatically go to, and remain in, this standby mode. In the ultralow-power standby mode (ISB1), the devices consume less than
2.5mW, typically. This capability provides significant system-level
power and cooling savings. The low-power (L) versions also offer a
battery backup data retention capability where the circuit typically
consumes only 30pW operating off a 2V battery.
All inputs and outputs of the 10171981/10171982 are TTL-compatible and operate from a single 5V supply, thus simplifying system designs. Fully static asynchronous circuitry is used, which
requires no clocks or refreshing for operation, and provides equal
access and cycle times for ease of use.
The 10171981/10171982 are packaged in either space-saving
28-pin, 400 mil hermetic DIPs, 28-pin 300 mil plastic 0lPsor28-pin
leadless chip carriers, providing high board-level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STO-883, Class B. making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• 10T71981S/L: outputs track inputs during write mode
• 10T71982S/L: high impedance outputs during write mode
• High speed (equal access and cycle time)
- Military: 20/25/30/35/45/55170/85ns (max.)
- Commercial: 15/20/25/30/35/45ns (max.)
• Low power consumption
- ID171981/2S
Active: 350mW (typ.)
Standby: 100pw (typ.)
- ID171981/2L
Active: 300mW (typ.)
Standby: 30pw (typ.)
• Battery backup operation - 2V data retention (L version only)
• High-density 28-pin hermetic and plastic DIP, 28-pin leadless
chip carrier .
• Produced with advanced CEMOS ™ high-performance
technology
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STO-883, Class B

FUNCTIONAL BLOCK DIAGRAM

A---r--...,

Vec
GND

ROW
SELECT

A

65.536 BIT
MEMORY ARRAY

----I

DD4f~~~~~
COLUMN I/O

----.lj

Y

D ---,-,....--.
D

-ttf"'L--1

CS,

Y
Y

cs2----======~~1

-------,
IDT71982 ONLY I

L..--l-l>-Y

1... _ _ _ _ _ _ _ _ _ _ .1

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-l028/-

4-84

IDT71981/1DT71982 CMOS STATIC RAMS 64K (16K X 4-Bln

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX
I

I

'-'

I

I.

'-'

I

I

I

I

1'-'

I

I

'-'

32U2827
1

A3

]

4

A4

]

5

25 [:

All

A5

]

e

24 [:

AlO

A12

26 [

Ae

]

7

A7

]

8

A8
Dl

:] 9
] 10

21 [: D3
20 [:

Y4

D2

]

11

19 [:

Y3

:] 12

18 [:

Y2

CSl

L28-2

23 [:

Ag

22 [:

D4

DIP
TOP VIEW
LCC
TOP VIEW

LOGIC SYMBOL

Ao
Al
A2

PIN NAMES
Y4

A3
A4
A5
Ae
A7
A8
Ag
A 10
A11
A12
A 13

Y3
Y2

VTERM

RATING
Terminal Voltage
with Respect to
GND

Address Inputs .

D 1-D4

DATA IN

Chip Selects

Yl-Y4

DATA oUT

WE

Write Enable

GND

Ground

OE

Output Enable

Vcc

Power

V,

ABSOLUTE MAXIMUM RATINGS
SYMBOL

Ao-A13

CS lo CS 2

-0.5 to +7.0

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

SYMBOL

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

loUT

DC Output Current

50

50

mA

PARAMETER

MIN.

TYP.

MAX.

Vcc

Supply Voltage

4.5

5.0

5.5

UNIT

GND

Supply Voltage

0

0

0

V

VIH
VIL

Input High Voltage

2.2

6.0

V

Input Low Voltage

-0.5(1)

-

0.8

V

V

NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

GRADE
Military
Commercial

4-85

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V ± 10%

Vee

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT71981/IDT71982 CMOS STATIC RAMS 64K (16K x 4-BIT)

DC ELECTRICAL CHARACTERISTICS

-

Vee = 50V +10%
SYMBOL

TEST CONDITION

PARAMETER

Ilu l

Input Leakage Current

IlLOI

Output Leakage Current

MIN.
MIL.
COM'L.

Vcc = Max., VIN = GND to Vcc

\be =

MIL.
COM'L.

Max.
~ = VIH , VOUT = GND to Vee

Output Low Voltage

VOH

Output High Voltage

NOTE:
1. Typical limits are at Vcc = 5.0V,

-

-

10L = 8mA, Vee = Min.

-

10L = -4mA, Vee = Min.

2.4

10L = 10mA, Vcc= Min.
VOL

IDT71981/2S
TYP.(l) MAX.

-

IDT71981/2L
MIN. TYP.(l) MAX.

-

0.4

-

-

-

2.4

-

10
5
10
5
0.5

UNIT

5
2

J.1A

5
2

J.1A

0.5

V

0.4

V

-

V

+ 25°C ambient.

DC ELECTRICAL CHARACTERISTICS (1)
Vcc = 5.0V ±10%, VLe = 0:2)1, VHe = Vee - 0.2V
SYMBOL

PARAMETER

71981/2S15 71981/2S20 71981/2S25 71981/2S30/35 71981/2S45/55(3) 71981/2S70 71981/2S85
POWER 71981/2L15 71981/2L20 71981/2L25 71981/2L30/35 71981/2L45/55(3) 71981/2L70 71981/2L85 UNIT
COM'LMIL COM'LMIL COM'LMIL COM'L

Operating Power
Supply Current
ICCl

ICC2

Outputs Open
Vcc = Max.,
f = 0(2)
Dynamic
Operating Current
CS = VIL,
Outputs Open,
Vcc = Max.,
f = fMAX(2)
Standby Power
Supply Current
(ITL Level)

ISB

ISBl

S

135

-

120

~=VILo

CS ~"'L,
Vcc = Max.,
Outputs Open
f = f MAX(2)
Full Standby
Power Supply
Current (CMOS
Level)
CS ~ VHe ,
Vcc= Max.,
'-"N ~VHC or
'-"N ~ VLC , f = 0(2)

MIL COM'L

MIL COM'LMIL COM'LMIL.

100

125

100

110

100

110

-

110

-

110

85

110

85

95

85

95

-

95

-

95

1fU

135

155

125

140

125

140

-

140

-

140

155

125

145 115/105125/115

100

110

-

110

-

105~

70

55

60

45

50

-

50

-

50

140
::::::.

mA

:::::::::::::::::>:,::
L

115

-

S

175

-

L

160

105\:.125

'S2:::.

.:2s:
-{::;J:~~

mA

:";'::::::}

..~:::

::::::::;.

S

75

:2< :::~
.:::::::::::::

L

5:!:~:i:~:i

50/45

55/50

•

mA

50

60

45

50

40/35

45/40

30

35

-

35

-

35

20

25

15

20

15

20

15

20

-

20

-

20

.:::::::::::::~:~>.

S

25

-

mA
L

2.5

-

1.0

2.0

0.5

1.5

0.5

1.5

0.5

1.5

-

1.5

-

NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1ltRC' f = 0 means no input Jines change.
3. -55°C to + 125°C temperature range only.

4-86

1.5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT71981/IDT71982 CMOS STATIC RAMS 64K (16Kx 4.BIT)

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) \tc = 0 2V VHC = \bc - 0 2V
PARAMETER

SYMBOL
VOR

TEST CONDITIONS

-

Vcc for Data Retention

~ MIL.

ICCOR

Data Retention Current

t COR(3)

Chip Deselect to Data Retention Time

t R(3)
Ilu l (3)

MIN.

COM'L.

CS~

\'IN

Operation Recovery Time

VHC

~ VHC or~ VLC

TYP.(1)

MAX.

Vcc @
2.0V 3.0V

Vcc @
2.0V 3.0V

2.0

-

-

-

-

-

10

15

600

900

10

15

150

225

-

-

0
t RC (2)

-

Input Leakage Current

2

JlA

TA = +25°C
t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.

LOW Vee DATA RETENTION WAVEF0A:M

DATA RETENTION MODE

Vcc

AC TEST CONDITIONS
GND t03.0V
5ns
1.5V
1.5V
See Figures 1 and 2

DATAOUT~4800
2550

Y

:q

5V 4800

DATAoUT

255Cl

SOpF'

Figure 1. Output Load

.

5pF*

Figure 2. Output Load
(for t CLZ1. 2. toLZ' t CHZ1 • 2. t oHZ'
tow and tWHz)
* Including scope and jig.

4-87

J.1A
ns

NOTES:

5V

V

-

1.
2.

Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

UNIT

ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT71981/IDT71982 CMOS STATIC RAMS 64K (16Kx 4-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(VCC = 5V ±100/0. All Temperature Ranges)
71981/2S15(1)/20 71981/2S25/30 71981/2S35/45 71981/2S5s12) 71981/2S7()12) 71981/2S85(2
71981/2L15(1)/20 71981/2L25/30 71981/2L35/45 71981/2L55(2) 71981/2L70(2) 71981/2L85(2 UNIT
MAX. MIN.
MAX.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MIN.

READ CYCLE
t RC

Read Cycle Time

tAA

Address Access Time

t AcS1 ,2

Chip Select-1. 2 Access Time (3)

t cLZ1 ,2

Chip Select-1. 2 to Output in
LOWZ(4)

5

tOE

Output Enable to Output Valid

-

tOLZ

Output Enable to Output in
Low Z (4)

5

t CHZ1 ,2

Chip Select-1. 2 to Output in
High Z(4)

tOHZ

Output Disable to Output in
High Z(4)

tOH

Output Hold from Address
Change

tpu

Chip Select to Power Up Time (4)

tpD

Chip Deselect to Power Down
Time (4)

15/20

-

. •.•• / • • 7
·}\:J5/2O
.....:::.·.\15120

25/30

-

35/45

-'

55

-

70

-

85

-

ns

-

25/30

-

35/45

-

55

70

ns

-

35/45

-

55

-

85

25/30

-

85

ns

70

.).~

5

-

5

-

5

-

5

-

5

-

ns

·>:52115

-

15/20

-

20/25

-

35

-

45

-

55

ns

5

-

5

-

5

-

5

-

5

-

ns

- :i'. 7/8

-

10/13

-

15

-

20

-

25

-

30

ns

- : : : 7/8

-

15

-

15

-

20

-

25

-

30

ns

-

5

-

5

-

5

-

5

0

-

0

-

0

-

5

0

0

-

ns

15/20

-

25/30

-

35/45

-

55

-

70

-

85

ns

:<::::::::.:.:.:.; ..

i:::
o.ri?:

f~;. : :

-

NOTES:
1. OOC to + 70°C temperature range only. Data for 20ns devices is preliminary for military temperature range.
2. -55°C to + 125°C temperature range only,
3. Both chip selects must be active low for the device to be selected.
4. This parameter guaranteed but not tested.

4-88

ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

10T71981/10T71982 CMOS STATIC RAMS 64K (16K x 4-BIT)

TIMING WAVEFORM OF READ CYCLE NO.1

(1)

~---------

ADDRESS

~
:

tRO

-------------401

____________________________________________~

~--~------- tAA

.1

" - - - - - tOE ----l~

" - - - - - t ACS1 ' t ACS2 ---t-----I~
tCLZ1 ' tClZ2 (5) ---~

DATAOlJT

TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)

ADDRESS

DATAOlJT

TIMING WAVEFORM OF READ CYCLE NO.3 (1,3,4)

" - - - - - - tAOS 1 ' t ACS2 ----~
t CHZ1 ' tCHZ2 (5) 1 4 - - -.......
tCLZ1 , tClZ2 (5)

DATAOlJT

Vee

Icc

cj~~~~+

Isa

--------~:f

NOTES:

wr:

1.
is High for Read Cycle.
2. Device is continuously selected, 'CS 1 = V IL ' 'CS 2 = V1L•
3. Address valid prior to or coincident with 'CS 1 ' and or 'CS2 transition low.

4.



12/15

-

30/35

-

40

ns

-

30/35

':

40

-

50

20/25

-

45

12/15

-

20/25

-

50

ns

-:::<:':"':

:;:;::::::::::)i

20/25
20/25

30/40

NOTES:
1. O°C to + 70°C temperature range only. Data for 20ns devices is preliminary for military temperature range.
2. -55°C to + 125°C temperatura range only.
3. This parameter guaranteed but not tested.
4. For IDT71981S/L only.
5. For IDT71982S/L only.

4-90

60
0
60

45

75

ns

ns
ns

ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT11981/IDT11982 CMOS STATIC RAMS 64K (16K X 4-BIT)

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1)
~---------------twe--------------~

ADDRESS

~------------- tAW ----------~

14------t

wP

(2) _ _ _ _~

DATA IN

DATAoUT

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1,5)

twe

",
.J'

ADDRESS

'\. '\. "\.

)(
~

tew

(4)

~~~ ~~

"}~

t WR1 .2 (3)

/ V////

tAW

I~

~b
t AS -

~£
t

WHZ

(6)

-

I-- tow- _ t OH

K

DATA IN

DATA VALID

I+-twv
DATA OUT (7)

DATA UNDEFINED

DATA OUT (8)

DATA UNDEFINED

4-91

tlY

'I
~

,
J

-

~ tOH

- t ow (6)-

"

J\.

DATA VALID (9)

r--

'--

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT71981/IDT71982 CMOS STATIC RAMS 64K (16K x 4-BIT)

TIMING WAVEFORM OF WRITE CYCLE NO.3 (WE CONTROLLED, OE LOW)

(1,5)

twc

'"

)(

ADDRESS

J~

f4-

"\."\. "

t WR1 .2 (3)

///////
tAW

1:'\. '\. '\.

t Wp (2)

I

~Ii.

/

....

t AS tow

)(

t OH -

DATA VALID

f4- - t IV

,.,

J~

-

- t wv -

jK

DATA UNDEFINED

DATA OUT (7)

!-- tWHZ (6)
DATA OUT (8)

DATA UNDEFINED

_

DATA VALID (9)

,
J

NOTES:
1. WE or ~1' or ~2 must be high during all address transitions.
2. A write occurs during the overlap (twp ) of a low WE, a low ~ 1 and a low ~2.
3. twR is measured from the earlier of ~1 ' ~ or WE going high to the end of the write cycle.
4. If the ~1 and or ~ low transition occurs simultaneously with the WE low transitions or after the
impedance state.
5. (jE' is continuously low ('OE = ~L).
6. Transition is measured ±200mV from steady state.
7. For IDT71981 only.
8. For IDT71982 only.
9. DATAoUT = DATAIN

TRUTH TABLE
MODE

CAPACITANCE

CSl CS2

WE

OE

OUTPUT

POWER

SYMBOL

WE transition, outputs remain in a high

(TA= +2S0 C, f = 1.0MHz)

PARAMETER(l)

Standby

H

X

X

X

HighZ

Standby

CIN

Input Capacitance

Standby

X

H

X

X

HighZ

Standby

C OUT

Output Capacitance

Read

L

L

H

L

~UT

Active

Write (1)

L

L

L

L

DIN

Active

Write (1)

L

L

L

H

HighZ

Active

Write (2)

L

L

L

X

HighZ

Active

Read

L

L

H

H

HighZ

Active

CONDITIONS

MAX.

UNIT

\'IN = OV

7

pF

VOUT= OV

7

pF

NOTE:
1. This parameter is determined by device characterization but is not
production tested.

NOTES:
1. For IDT71981 only.
2. For 10T71982 only.

4-92

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT71981/IDT71982 CMOS STATIC RAMS 64K (16K X 4-BIT)

ORDERING INFORMATION
lOT

xxxxx
Device Type

999
Speed

A

A

Package

Process!
Temperature
Range

y~k
P
~--------------~

C
L

15
20
25
30

Commercial (O°C to

Plastic DIP (300 mil)
Sidebraze DIP (400 mil)
Leadless Chip Carrier

Commercial Only

Speed in Nanoseconds

35

L-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

45
55
70
85

Military Only
Military Only
Military Only

S
L

Standard Power
Low Power

71981
--I 71982

L..--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

4-93

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

64K (16K x 4-Bit)
64K (16K x 4-Bit) High Impedance Outputs

FEATURES:

DESCRIPTION:

• High-speed address/chip select access time
- Military: 35/45/55170/85/1oo/120/150/200ns (max.)
- Commercial: 30/35/45ns (max.)
• Low power consumption
-.IDT7164S
Active: 300mW (typ.)
Standby: 1OO~w (typ.)
- IDT7164L
Active: 250mW (typ.)
Standby: 30~w (typ.)
• Battery backup operation - 2V data retention voltage (L Version
only)
• Produced with advanced CEMOS TM high-performance
technology
• Single 5V (±10%) power supply
• Input and output directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Available in standard 28-pin DIP (600 mil), 28-pin THINDIP
(300 mil), 28-pin LCC, 32-pin LCC and PLCC and 28-pin SOIC
• Pin-compatible with standard 64K static RAM and EPROM
• Military product available compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-85525 is pending listing on
this function. Refer to Section 21page 2-4.

The IDT7164 is a 65,536 bit high-speed static RAM organized as
8K x 8. It is fabricated using IDT's high-performance, high-reliability CEMOS technology.
Address access times as fast as 30ns are available with typical
power consumption of only 250mW. The circuit also offers a reduced power standby mode. When CS 1 goes high or CS 2 goes
low, the circuit will automatically go to, and remain in, a low-power
standby mode. In the full standby mode, the low-power device typically consumes less than 30~W. The low-power (L) version also offers a battery backup data retention capability where the circuit
typically consumes only 10~W operating off a 2V battery.
All inputs and outputs of the IDT7164 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation.
The IDT7164 is packaged in a 28-pin, 300 mil THINDIP; 28-pin,
600 mil DIP; 32-pin LCC and PLCC and 28-pin LCC and SOIC, providing high board-level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.-

FUNCTIONAL BLOCK DIAGRAM

Vcc
256 x 256

GND

MEMORY ARRAY

DECODER

COLUMN I/O

I/Os

CONTROL~------------------------------------4---~

CIRCUIT

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
DSC-1002/-

4-94

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7164S/IDT7164L CMOS STATIC RAM 64K (BK x B-BIT)

PIN CONFIGURATIONS·
NC

Vee

A12

~

A7
Ae

CSz
A8

. Ae

:]5

A5
A4

Ag

A5
A4

] e
]

7

A3
A2
Al

<:5E

A3
A2

]

8

INDEX

~~~u~~~

All
AlO

CS 1
1/0 8

AO
1/0 1

1/0 7

1/°2

I/0e

1/0 3
GND

1/°5
1/0 4

J32-1
&
L32-1

]g

29[:

As

28 [:

Ag

27 [:

All

26 [:

NC

25 [:

<:5E

24 [:

AlO

:] 11

23 [:

CS1

:] 12

22 [:

1/0 8

13
21 [:
14 15 16 17 18 19 20

1/0 7

Al
AO

]

NC
1/0 1

1

]

10

nnnnnnn

DIP/SOIC
TOP VIEW
32-PIN LCC/PLCC
TOP VIEW

LOGIC SYMBOL

PIN NAMES
Ao- A12

Address

~

1/01 -1/08

Data Input/Output

<:5E

Output Enable

CSI

Chip Select

GND

Ground

CS 2

Chip Select

Vee

Power

Write Enable

4-95

2B-PIN LCC
TOP VIEW

MILITARY AND COMMERCIAL TEMPERATURE RANGES

I DT7164S/1 DT7164L CMOS STATIC RAM 64K (SK X S-BIT)

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL
-0.5 to +7.0

MILITARY
-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

T91AS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

-55 to +125

MIN.

TYP.

MAX.

Vcc

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

~H

Input High Voltage

2.2

V

Input Low Voltage

-0.5(1)

-

6.0

~L

0.8

V

PARAMETER

SYMBOL

UNIT

°C

UNIT

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V

O°C to +70°C

OV

5.0V

GRADE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Military
Commercial

Vee

± 10%
± 10%

DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ±10%
SYMBOL

lIu l
IILol

PARAMETER
Input Leakage Current
Output Leakage Current

VOL

Output Low Voltage

VOH

Output High Voltage

TEST CONDITIONS
Vee = Max., V1N = GND to Vcc

\be = Max.
~1 = V1H , VOUT = GND to \be
IOL = 10mA, Vee = Min.
10L = SmA, Vcc = Min.

MIN.

10
5

-

-

-

-

2.4

MIL.
COM'L.

-

MIL.
COM'L.

-

IOH= -4mA, Vcc= Min.

IDT7164S
TYP.(I) MAX.

MIN.

IDT7164L
TYP.(I) MAX.

UNIT

-

5
2

J.l.A

5
2

J.l.A

0.5

-

-

0.5

V

-

0.4

-

0.4

V

-

-

2.4

-

-

V

10
5

NOTE:
1. Typical limits are at Vcc = 5.0V, +25°C ambient.

DC ELECTRICAL CHARACTERISTICS (1)
= 5.0V ±10%, VLC = 0.2V, VHC = Vee - 0.2V

Vcc

SYMBOL

ICCI

PARAMETER
Operating Power Supply
Current, ~1 = V1L' Outputs
Open, CS 2 = V1H
Vee = Max., f = 0(3)
Dynamic Operating Current

ICC2

~1 = V1L, Outputs Open,
CS2 = ~H' Vee = Max.,

f = f MAX (3)

IS9

ISBl

Standby Power Supply
Current (TTL Level), f = f MAX(3)
~1 ~ V1H ' or CS2 ~ ~L
Vee = Max., Outputs Open
Full Standby Power Supply
Current (CMOS Level) f = 0(3)
1. ~l~VHCand C~ ~ VHC
2. CS 2 S "tc, \be = Max.

POWER

IDT7164S45 IDT7164S55 1DT7164S70 1DT7164Sss(2)
IDT7164L45 IDT7164L55 1DT7164L70 IDT7164LS5(2) UNIT
COM'L MIL COM'L MIL COM'LMIL COM'L MIL COM'L MIL COM'L MIL
IDT7164S30 IOT7164S35
IDT7164L30 IOT7164L35

S

90

-

90

100

90

100

-

100

-

100

-

100

L

80

-

80

90

80

90

-

90

-

90

-

90

S

160

-

150

160

150

160

-

160

-

160

-

160

L

140

-

130

140

120

130

-

125

-

120

-

120

S

20

-

20

20

20

20

-

20

-

20

-

20

L

3

-

3

5

3

5

-

5

-

5

-

5

S

15

-

15

20

15

20

-

20

-

20

-

20

L

0.2

-

0.2

1.0

0.2

1.0

-

1.0

-

1.0

-

1.0

mA

mA

NOTES:
1. All values are maximum guaranteed values.
2. Also available: 100, 120, 150 and 200ns military devices.
3. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of llt RC' f

4-96

mA

mA

= 0 means no input lines change.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT1164S/IDT1164L CMOS STATIC RAM 64K (SK x S-BIT)

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V. VHC

= Vcc -

0.2V
TYP.(1)

PARAMETER

SYMBOL
VDR

TEST CONDITIONS

-

Vee for Data Retention

ICCDR

Data Retention Current

tCDR

Chip Deselect to Data Retention Time

tR

Operation Recovery Time

Ilu l (3)

Input Leakage Current

1. ~1 ?: VHC • CS 2 ?: VHC
2. CS 2 ~ VLC

I

Vee @
2.0V
3.0V

MIN.

MAX.
Vee @
2.0V
3.0V

2.0

-

-

-

-

-

10

15

200

300

10

15

60

90

-

-

-

ns

-

-

2

JlA

DATA RETENTION MODE

AC TEST CONDITIONS
GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

5V

~

2550

5V

480Q
DATAOLIT
30pF*

~

2550

48OQ
5pF*

Figure 2. Output Load

Figure 1. Output Load

(for tCLZ1.2' t OLZ• tCHZ1.2' t OHZ '
tow.t WHZ )

* Including scope and jig.

4-97

~

0

LOW Vee DATA RETENTION WAVEFORM

DATAOLIT

V

t RC (2)

NOTES:
1. TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

UNIT

ns

IDT7164S/IDT7164L CMOS STATIC RAM 64K (8K x 8-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc = 5V ±10%, All Temperature Ranges)

7164S30(l,6)
7164L30(1,6)
MIN.
MAX.

PARAMETER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7164S35(5)
7164L35(5)
MIN. MAX.

7164S45
7164L45
MIN. MAX.

7164S55(2)
7164L55(2)
MIN. MAX.

7164S70(2)
7164S85(2)
7164L70(2)
7164L85(2) UNIT
MAX. MIN. MAX.
MIN.

READ CYCLE
t RC

Read Cycle Time

30

-

35

-

45

-

55

-

70

-

85

-

tM

Address Access Time

30

-

45

-

70

ns .

-

45

55

-

70

-

85

40(5)

-

55

Chip Select-l, 2 Access Time (3)

-

35

tACS1.2

-

85

ns

t CLZ1 . 2

Chip Select-l, 2 to Output in Low

5

-

5

-

5

-

5

-

5

-

5

-

ns

tOE

Output Enable to Output Valid

-

15

-

20

-

25

-

30

-

35

-

40

ns

Z (4)
tCHZ1.2 Chip Select-1, 2 to Output in High Z (4)
Output Disable to Output in High Z (4)
tOHZ

0

-

0

-

0

-

0

-

0

-

0

-

ns

-

15

-

15

-

20

25

-

30

-

35

ns

30

-

'35

ns

5

5

-

ns

0

-

0

-

ns

-

70

-

85

ns

toLZ

Z (4)

Output Enable to Output in Low

35(6)

-

15

-

15

-

20

-

tOH

Output Hold from Address Change

5

5

-

5

Chip Select to Power Up Time (4)

0

0

-

5

t pu

-

0

-

0

-

tpD

Chip Select to Power Down Time (4)

-

30

-

35

-

45

-

55

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only. Also available: 100, 120, 150 and 200ns military devices.
3. Both chip selects must be active for the device to be selected.
4. This parameter guaranteed but not tested.
5. t ACS1 = 35ns, t ACS2 = 40ns
6. t ACS1 = 30ns, tACS2 = 35ns

4-98

25

ns

IDT7164S/IDT7164L CMOS STATIC RAM 64K (SK X 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1
ADDRESS

~

(1)

tRC --------~------------~
____________________________________________

"'"-1---------------

tM

14-------CS 2

~'-"'--'-

~

.. '

tOE

14------ t ACS2 -----+--~
14-------- tCL.Z2 (5) _ _ _--1001
14------- t AcS1 - - - t - - - - - . j
1 4 - - - - - - tCLZl (5) _ _ _-fOoj

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.2

ADDRESS

(1,2,4)

I------------------tRC ---------------------t=~
_ __

={

!=:===-tOH-tM~iXX1-----··_tOH~=1~

______

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.

3(1,3,4)

jr£

~""
:;~

t CLZ1(5)

1000 (

i - - t pu -

Iss

-------------

"

/

./~

~,

tpo .......
- t po -

NOTES:
1. ~ is High for Read Cycle.
2. Device is continuously selected, CS" 1 = V 111 CS 2 = V1H •
3. Address valid prior to or coincident with CS"1 transition low and CS 2 transition high.

4. <:5t= =

tCHZ2 (5)

- tCHZ1 (5)-

DATAoUT

CURRENT

-

t ACS1

tpu

Icc

~,

t ACS2
t CL.Z2(5)-

"'IL

5. Transition is measured ±200mV from steady state.

4-99

....

MILITARY AND COMMERCIAL TEMPERATURE RANGES

I DT7164S/I DT7164L CMOS STATIC RAM 64K (SK x S-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc = 5V -+10%, All Temperature Ranges)

7164S30(1)
7164L30(1)
MIN. MAX.

PARAMETER

7164S35
7164L35
MIN. MAX.

7164S45
7164L45
MIN. MAX.

7164S55(2)
7164L55(2)
MIN. MAX.

7164S70(2)
7164S85 (2)
7164L70(2)
7164L85 (2) UNIT
MIN.
MAX. MIN. MAX.

WRITE CYCLE
55

5

-

15

-

-

20

twc

Write Cycle Time

30

-

35

-

45

t CW1 . 2

Chip Select to End of Write

25

30

-

40

tAW

Address Valid to End of Write

25

30

-

40

tAS

Address Set-up Time

0

-

0

-

0

twp

Write Pulse Width

25

-

30

40

tWRl

Write Recovery Time (CS" I,

0

0

tWR2

Write Recovery Time (CS2)

5

-

5

-

tWHZ

Write Enable to Output High Z (3)

-

12

-

tow

Data to Write Time Overlap

13

15

tOH

Data Hold from Write Time(4)

3/5

-

3/5

tow

Output Active from End of Write (3)

5

-

5

WE)

0

3/5
5

70

-

85

-

ns

60

75

-

ns

75

-

ns

0

-

ns

75

-

ns

0

-

0

-

ns

5

-

5

-

5

-

ns

20

-

25

-

30

-

35

ns

-

25

-

30

-

35

ns

3/5

-

5

-

ns

50
50
0
50
0

3/5
5

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only. Also available: 100, 120, 150 and 200ns military devices.
3. This parameter guaranteed but not tested.
4. Vflth respect to CS"1 ' wr;, = 30ns, CS 2 = 5ns

4-100

60
0
60

3/5
5

ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7164S/IDT7164L CMOS STATIC RAM 64K (BK x S-BIT)

TIMING WAVEFORM OF WRITE CYCLE NO.

1(1)

~------------------twc------------------~

ADDRESS

CS 1

DATA OUT

TIMING WAVEFORM OF WRITE CYCLE NO.

2(1,6)

~----------------twc----------------~
----~

ADDRESS

,-------------

1 4 - - - - tcw -------t+-.....;
CS 1

DATAoUT

t;
-----------------iC1\-

t DW

t DH

----I

4XXXXX

DATAIN VALID
NOTES:
1. ~ must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS 1 and a high CS 2.
3. t WR1 ,2 is measured from the earlier of CS1 or ~ going high or CS 2 going low to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CSl low transition or CS2 high transition occurs simultaneously with the
low transitions or after the ~ transition, outputs remain in a high
impedance state.
6. DE is continuously low (DE = ~d.
7. DATAoUT is the same phase of write data of this write cycle.
8. If CSl is low and CS 2 is high during this period, I/O pins are in the output state. Data input signals must not be applied.
9. Transition is measured ±200mV from steady state.

wr:.

4-101

I DT7164S/IDT7164L CMOS STATIC RAM 64K (SK x S-BIT)

CAPACITANCE
SYMBOL
CIN

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE

(TA= +25°C, f = 1.0MHz)

PARAMETER(t)
Input Capacitance

CONDITIONS

MAX.

UNIT

WE

"CSt

CS 2

DE

1/0

S

pF

X

H

X

X

HIGHZ

Standby (I SB)

X

X

HIGHZ

Standby (ISB)

"'IN = OV

Output Capacitance
COUT
a
pF
VOUT= OV
NOTE:
1. This parameter is determined by device characterization but is not
production tested.

MODE

L

X
X

HIGHZ

Standby (ISB1)

X

HIGHZ

Standby (ISB1)
Output disable

X

VHC

X

X

VHCor
VLC
VLC

H

L

H

H

HIGH Z

H

L

H

L

DOUT

Read

L

L

H

X

DIN

Write

NOTE:
1. CS2 will power-down ~1' but ~1 will not power-down CS 2 .

ORDERING INFORMATION
lOT

xxxxx

A

A

A

Device Type

Power

Package

Process/
Temperature
Range

y:P
TC

~...................................~ 0
J
L
SO

~----------------~!~
4-102

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-SID-aa3, Class B
Plastic DIP
Sidebraze THINDIP
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Small Outline IC
Commercial Only ~
Military Only
Military Only
Military Only

J

Speed in Nanoseconds

Standard Power
Low Power
64K (8K x 8-Bit) CMOS Static RAM

FEATURES:

DESCRIPTION:

• 16-bit word width,· with separate control of upper and lower
bytes

The IDT7186 is an extremely high-speed 4K x 16-bit static RAM
designed for use in wide-word systems where high speed, low
power and board density are of the utmost importance.
The IDT7186 uses Sixteen bidirectional input/output lines to provide simultaneous access to all bits in a word and has two byte enable lines to allow the upper and lower byte of a word to be accessed either together or independently. A high-speed output enable pin allows designers to tum on the IDT7186's outputs at a
speed much higher than the already fast address access time and
achieve a considerable throughput-.?dvantage. An automatic
power down feature, controlled by CE, permits the on-chip circuitry to enter a very low standby mode.
Fabricated using lOT's CEMOS TM high-performance technology, the IDT7186 typically operates on only 300mW of power at
maximum access times as fast as 45ns. Low-power (L) versions offer battery backup data retention capability, typically consuming
30~W from a 2V battery.
The IDT7186 is packaged in either a sidebraze or plastic 40-pin
DIP. Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it Ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• High-speed access
- Military: 55/70/85ns (max.)
- Commercial: 45/55ns (max.)
• Low power consumption
- IDT7186S
Active: 400mW (typ.)
Standby: 100~W (typ.)
-IDT7186L
Active: 300mW (typ.)
Standby: 30~W (typ.)
• Separate upper-byte and lower-byte control for multiplexed bus
compatibility
• JEDEC compatible pinout
• Battery backup operation-2V data retention
• Available in 40-pin, 600 mil plastic and sidebraze DIP
• lTL-compatible
• Single 5V (±10%) power supply
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
Ao ------~-----,

65,536-BIT
MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology. Inc.

4-103

DECEMBER 1987
DSC-1024/-

91
~

MILITARY AND COMMERCIAL TEMPERATURE RANGES

JDT7186S/JDT7186L 64K (4K x 16-BIT) CMOS STATIC RAM

LOGIC SYMBOL

PIN CONFIGURATIONS

DIP
TOP VIEW

PIN NAMES
Ao-All

Addresses

1100-1/015

Data Input/Output

CE

Chip Enable

WE

Write Enable

OE

Output Enable

UB

Upper Byte Enable

LB
GND

Lower Byte Enable

Vcc

Power

Ground

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

-0.5 to +7.0

o to

+70

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

-55 to +125

UNIT
V

°C

TB1AS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

MIN.

TYP.

MAX.

UNIT

Vcc

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

'ltH

Input High Voltage

2.2

-

6.0

V

'ltL

Input Low Voltage

-0.5(1)

-

0.8

V

SYMBOL

PARAMETER

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

GRADE
Military
Commercial

4-104

AMBIENT
TEMPERATURE

GND

Vee

-55°C to + 125°C

OV

5.0V ± 10%

O°C to +70°C

OV

5.0V ± 10%

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT1186S/IDT7186L 64K (4K x 16-BITj CMOS STATIC RAM

DC ELECTRICAL CHARACTERISTICS
Vee = 50V -+10%
SYMBOL

PARAMETER

IDT1186S

TEST CONDITION

MIN.

MAX.
5
5
5
5

~A

0.4
0.5

V
V

-

V

10
10
10
10
0.4
0.5

-

-

2.4

lIu l

Input Leakage Current

Vee = Max., V1N = GND to Vee

IILOI

Output Leakage Current

Vee Max.
CE = V1H , VOUT = GND to Vee

MIL.
COM'L.

VOL

Output Low Voltage

10L = 6mA, \be = Min.
IOL = 8mA, Vee = Min.

-

VOH

Output High Voltage

IOH = -4mA, Vee = Min.

2.4

UNIT

MIN.

-

MIL.
COM·L.

DC ELECTRICAL CHARACTERISTICS

IDT1186L
MAX.

~A

~A

~A

(1)

Vee = 5V ±10%, VLe = 0.2V, VHe = Vee - 0.2V
SYMBOL

1OT1186S45
1OT1186L45
COM'L
MIL.

PARAMETER

POWER

Operating Power Supply Current
CE = "'IL ' Outputs Open,
Vee = Max., f = 0(2)

S

130

leel

L

115

-

S

160

-

ICC2

Dynamic Operating Current
CE = V1L , Outputs Open,
Vee = Max., f = f MAX (2)

L

140

-

S

40

ISB

Standby Power Supply Current
(lTL Level) CE ~ "'IH
\be = Max., f = fMAX (2)
Outputs Open

L

ISB1

Full Standby Power Supply
Current (CMOS Level)
CE ~ VHC , "'IN ~ VLC or V1N ~ VHC
Vee = Max., f=0(2)

-

IOT7186S55
IOT7186L55
COM'L
MIL
130

IOT7186S70
IOT7186L70
COM'L
MIL

UNIT

150

130

150

115

135

115

135

mA

160

190

160

190

mA

140

170

140

170

mA

-

40

40

40.

40

mA

6

-

6

6

6

6

mA

S

15

-

15

20

15

20

mA

L

0.5

-

0.5

1.5

0.5

1.5

mA

NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX' address and data input are cycling at the maximum frequency of read cycles of 11'1Rc. f = 0 means no input lines change.

4-105

mA

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7186S/IDT7186L 64K (4K x 16-BIT) CMOS STATIC RAM

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC

= O.2V. VHC = Vcc

SYMBOL
VDR

- O.2V

PARAMETER

TEST CONDITIONS

-

Vcc for Data Retention

ICCDR

I

MIL

Data Retention CUrrent

t cDR (3)

Chip Deselect to Data Retention Time

t R(3)

Operation Recovery Time

Ilu l

Input Leakage Current

(3)

MIN.

CE :? VHC
V1N :? VHC or S VLC

COM'L.

TYP.(1)
Vcc @
2.0V
3.0V

MAX.
Vcc @
2.0V
3.0V

2.0

-

-

-

-

-

-

-

600

900

-

-

200

300

-

-

ns

2

2

~A

0

-

t RC (2)

-

-

-

NOTES:
1. TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.

LOW Vee DATA RETENTION WAVEFORM

DATA RETENTION MODE
VCC

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

5V

DATA OUT

~

2550

5V

4800
DATAoUT
30pF*

~

2550

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for tow. tWHZ • tCHZ • tell •
t BHZ ' tBLl' t OHZ ' tOll)

* Including scope and jig.

4-106

UNIT
V
~A

ns

1DT7186S/IDT7186L 64K (4K x 16-BIT) CMOS STATIC RAM

AC ELECTRICAL CHARACTERISTICS ~cc =
SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

5V ±10%. All Temperature Ranges)
I DT7186S45 (1)
1DT7186L45 (1)

PARAMETER

MIN.

IDT7186S55
1DT7186L55

MAX.

MIN.

IDT7186S70
IDT7186L70

MAX.

MIN.

UNIT

MAX.

READ CYCLE
t AC

Read Cycle Time

45

-

55

-

70

-

ns

tAA

Address Access Time

45

-

55

ns

Chip Enable Access Time

45

-

55

tAB

Upper/Lower Byte Enable Access Time

20

-

25

-

70

t AcE

-

tCLl

Chip Enable to Output in Low

tOE

Output Enable to Output Valid

tBLl

Upper/Lower Byte Enable to Output in Low

tOll

Outputl:nable to Output in Low

tCHZ

Chip Disable to Output in High

tOHZ

Output Disable to Output in High

Z(2)

Z (2)

Z(2)

Z(2)
Z(2)

70

ns

30

ns
ns

5

-

5

-

5

-

-

20

-

25

-

30

ns

5

-

5

-

5

-

ns

5

-

5

-

5

-

20

-

25

-

20

-

25

-

ns

30

ns

30

ns

5

-

5

-

5

-

ns

-

20

-

25

-

30

ns

Chip Enable to Power Up Time

0

-

0

-

0

-

ns

Chip Disable to Power Down Time

-

45

-

55

-

70

ns

tOH

Output Hold from Address Change

tBHZ

Upper/Lower Byte Enable to Output in High

tpu
tpD

Z (2)

NOTES:
1. O°C to + 70°C temperature range only.
2. This parameter is guaranteed but not tested.

4-107

MILITARY AND COMMERCIAL TEMPERATURE RANGES

I DT7186S/I DT7186L 64K (4K x 16-BIT) CMOS STATIC RAM

TIMING WAVEFORM OF READ CYCLE NO.1

ADDRESS

~

~

(1)

t RC

.'

tAA

%=t~"l
t

tOE

ug
or

OHZ

(5)

BHZ

(5)

CHZ

(5)

tOll (5)

rn

t

tAB
t

BLl

(5)

t

t ACE
tCLl

(5)

DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.2 (Continuously Enabled Read)

(1,2,4,6)

ADDRESS

DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.3 (CE Controlled Read W/Power-Up/Down Timing) (1,3,4,6)

/4------ tACS -------+1
1 4 - - - - - tCLl (5)

---~

DATA OUT

VCC SUPPLY
CURRENT

bc
ISB

NOTES:
1. WE" is High for Read Cycle.
2. Device is continuously selected, cr = VII3. Address valid prior to or coincident with cr transition low.
4. ~ = VIL
5. Transition is measured ±200mV from steady state with 5pf load (including scope and jig).
6. ug orm = VIL

4-108

1DT7186S/IDT7186L 64K (4K x 16-BIT) CMOS STATIC RAM

AC ELECTRICAL CHARACTERISTICS
PARAMETER

SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

01cc = 5V +10% All Temperature Ranges)
I DT7186S45 (1)
IDT7186L45 (1)

IDT7186S55
1DT7186L55

IDT7186S70
IDT7186L70

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

UNIT

WRITE CYCLE
twc

Write Cycle Time

45

-

55

-

ns

Chip Enable to End of Write

40

-

50

-

70

tcw

60

tsw

Upper/Lower Byte Enable to End of Write

40

-

50

-

60

ns

60

0

-

ns

60

-

ns

0

-

-

0

-

ns

tAW

Address Valid to End of Write

40

-

50

t AS

Address Set-up Time

0

0

twp

Write Pulse Width

40

tWR

Write Recovery Time

0

-

50

ns

ns

tWHZ

Write to Output in High Z (2)

-

20

-

25

-

30

ns

tow

Data Set-up Time

20

-

25

30

-

ns

tOH

Data Hold from Write Time

3

3

3

tow

Output Active from End of Write (2)

5

-

-

5

-

5

-

ns

NOTES:
1. O°C to + 70°C temperature range only.
2. This parameter is guaranteed but not tested.

4-109

ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7186S/IDT7186L 64K (4Kx 16-BIT) CMOS STATIC RAM

TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)

(1,2,3,7,8)

~----------------------twc----------------------~

~K

ADDRESS

)~------------

---'-----------------------------~ ~~~========

---+-------------------------t--y-~------------------tAW------------------~
'~

tOH"O_

~,

-

'--------------------------------------+------+-------~
t AS ---~----------- tW~7) -----------.j _t-W-R--f4------------+~~

/~

'-------------------------~

~tWHZ(6~
•• (4)C·····························

DATA OUT

(4).)_

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _I_ _ _

~~-t-ow-----.I-.---tO-H_~~----I------

TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)

=L
_~~ ~

ADDRESS

twe

t~

tAW

*--

(1,2,3,5,8)

~,..---~
[

___________________

--K~tow ~ t~~~-------

TIMING WAVEFORM OF WRITE CYCLE NO.3, (UB or IB CONTROLLED TIMING)

=f

ADDRESS

or

[8

~

~

tAwtwc

~~ ·I~

_

f(1,2,3,5,9)

';Ii) ~

taw

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _K~tow

•. ~

tOH~~------

NOTES:

1.
2.
3.
4.
5.

wr:.. cr, or both 00 or rn must be high during all address transitions.

wr=.

A write occurs during the overlap (taw, tow or twp ) of a low 00 or [8, a low CE' and a low
tWR is measured from the earlier of 00, rn, CE' or
going high to the end of the write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the
00, or
low transition occurs simultaneously with or after the
low transition, the outputs remain in the high impedance state.
6. Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).
7. If OE' is low during a
controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off and
controlled write cycle, this requirement does not apply and the
data to be placed on the bus for the required tow. If OE' is high during an
write pulse can be as short as the specified twP'

wr:.

cr,

wr=

m

wr:.

arm =

8. 00
9. cr =

wr=

V1L

VrL

4-110

IDT7186S/IDT7186L'64K(4Kx 16-BIT) CMOS STATIC RAM

TRUTH TABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(1)

INPUTS

OUTPUTS
MODE

CE

WE

OE

mr

H

X

X

X

L

X

X

H

H

L

L

X

L

H

m
X

1/0,- 1/015

1/00 - 1/°7

Hi-Z

Hi-Z

Hi-Z
DATA IN

':

Deselected, Powered Down

Hi-Z

Both Bytes Deselected

Hi-Z

Write to Upper Byte Only

L

L

X

H

L

Hi-Z

DATA IN

Write to Lower Byte Only

L

L

X

L

L

. DATAIN

DATA IN

Write to Both Bytes (Word Write)

L

H

L

L

H

L

H

L

H

L

L

H

L

L

L

L

H

H

X

X

Hi-Z

DATA OUT
Hi-Z

DATA OUT

DATA OUT

DATA OUT

Hi-Z

Hi-Z

Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes (Word Read)
Outputs Disabled

NOTES:
1. H=High, L=Low, X=Don't Care, Hi-Z=High Impedance

ORDERING INFORMATION
IDT

xxxxx

A

999

A

Device Type

Power

Speed

Process!
Temperature
Range

y:rMk

L...-~__________~I

P

Commercial (O°C to

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B,

IC

Plastic DIP
Side braze DIP

I 45

Commercial Only }

L . . . - - - - - - - - - - i 55

Speed in Nanoseconds

l 70

r-~----_ _ _ _ _ _~IS

IL

~--------------------------------------~:

4-111

7186

+ 70°C)

Standard Power
Low Power
64K (4K x 16-Bit)

FEATURES:

DESCRIPTION:

• 81,920-bit CMOS static RAM module with decoupling capacitor

The IDT7MP564 is an 80K (16,384 x 5-bit) high-speed CMOS
static RAM constructed on an epoxy laminate substrate using 5
IDT6167 (16,384 x 1-bit) CMOS static RAMs in plastic surface
mount packages. Extremely fast speeds can be achieved with this
technique due to use of the IDT6167 RAMs, fabricated in IDT's
high-performance, high-reliability technology-CEMOS. This
state-of-the-art technology, combined with innovative circuit design techniques, provides the fastest 16K static RAMs available.
The IDT7MP564 Is avan~~l,e with access times as fast as 20ns,
with maximum power"cbhslJ~ption of only 2.2 watts. The circuit
also offers a reduced:Po~~r:standby mode. When CS goes high,
the circuit automatically goes to, and remains In, a standby mode
as long as CS rem~i[ls high, consuming only 963mW maximum.
Substantially 10W~rpower levels can be achieved in the I SBI mode
(less than 1~f1l\IV":ll)ax.).
Allinput$'ancf"'outputs of the IDT7MP564 are TTL-compatible
and oper~te'f~Qr.n"a single 5V supply, thus simplifying system designs.,F:DIlY'asYnchronous circuitry is used, requiring no clocks or
refreshIng ,for operation, and providing equal access and cycle
times'for ease of use.
:f'
1',~~\\

•
•
•
•

High speed: 20ns max.
Low power consumption: 1.1W typo
IDT7MP564 package options reduce overall height
Utilizes IDT6167s-high-performance 16K RAMs produced
with advanced CEMOS TM

• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (± 10%) power supply
• Inputs and outputs directly TTL-compatible

,i

FUNCTIONAL BLOCK DIAGRAM

J
'-IDT6167
' - DI (16KxI) Do
' - - - - - ( ( ] WE

cs

J

u
PIN NAMES

PIN CONFIGURATION

Ao -A13

Addresses

1/01-1/05 Data Inputs/Outputs
CS

t5c >o
0

0

c:(

0-,,= c:(-

N

c:(

CO)

"'ON

c:( c:(

-

N

'"

CD~

c:( c:(

...

c:(

0CO) - CO)

"'~

c:(

C)

c:(

Chip Select

WE

Write Enable

~
GND

Ground

Power

0
...... -0
- - -NCO)",
-0 - '"

c:(

c:( c:(c:(

SIP
SIDE VIEW
CEMOS is a trademark of Integrated Device Technology. Inc.

DECEMBER 1987

COMMERCIAL TEMPERATURE RANGE
©

OSC-7oo8/-

1987 Integrated DevIce Technology. Inc.

4-112

-_._--------------------------------

FEATURES:

DESCRIPTION:

• High-speed (equal access and cycle time)
- Military: 35/45/55/70ns (max.)
- Commercial: 25/35/45/55ns (max.)
• Low-power operation
-IDT71257S
Active: 400mW (typ.)
Standby: 400~W (typ.)
-IDT71257L
Active: 350mW (typ.)
Standby: 100~W (typ.)
• Battery backup operation-2V data retention (L version only)
• Produced with advanced CEMOS TM high-performance
technology

The IDT71257 is a 262, 144-bit high-speed static RAM organized
as 256K x 1.lt is fabricated using IDT's high-performance, high-reliability CEMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective altemative to bipolar and fast NMOS memories.
Access times as fast as 25ns are available with typical -_ ... _-,consumption of only 350mW. The IDT71257 offers a reduced
power standby mode, ISB1, which enables the designer to greatly
reduce device power requirements. This capability provides significant system level power and cooling savings. The low-power
(L) version also offers a battery backup data retention capability
where the circuit typically consumes only 1oo~W operation off a 2V
battery.
All inputs and outputs of the IDT71257 are TIL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation, providing equal access and cycle times
for ease of use.
The IDT71257 is packaged in a 24-pin 300 mil DIP and a 24-pin
SOIC, providing high board-level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

•
•
•
•

Single 5V (±10%) power supply
Input and output directly TIL-compatible
Static operation: no clocks or refresh required
Available in high-density industry standard 24-pin, 300 mil DIP
and 24-pin SOIC
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B

PIN CONFIGURATION

Ao
Al

FUNCTIONAL BLOCK DIAGRAM

A2

A17
A16

A3
A4
A5

A15
A14
A13

A6
A7
A8
DoUT

M

A12
All
Al0
A9
DIN

GND

~

~Vee

Ao

vee

~GND

ADDRESSES

DECODER

A17

262. 144-BIT
MEMORY ARRAY

. . . .. .

~

DATAIN

COLUMN 1/0

DATAoUT

DIP/Sale
TOP VIEW

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
OSC-l016/-

4-113

1DT71257S/IDT71257L CMOS
STATIC RAM 256K (256K x 1-BI1)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

LOGIC SYMBOL
Ao

GRADE

DIN

Al
A2

Military

A3

Commercial

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND
OV

5.0V ± 10%

O°C to +70°C

OV

5.0V ± 10%

Vcc

A4
A5

Ae

A7
As
As

ABSOLUTE MAXIMUM RATINGS

DoUT

SYMBOL

Al0
All
A12

VTERM

A13

A14
A15
AlB

A 17

wr=. cs

Addresses

DIN

Data Input

CS

Chip Select

WE

Write Enable

DoUT
GND

Data Output

Vee

Power

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAs

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute' maximum rating
conditions for extended periods may affect reliability.

PIN NAMES
Ao - A17

RATING
Terminal Voltage
with Respect to
GND

RECOMMENDED DC OPERATING CONDITIONS

Ground

SYMBOL

MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

PARAMETER

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH
VIL

Input High Voltage

2.2

-

6.0

V

-

0.8

V

Input Low Voltage

-0.5(1)

NOTE:
1. VIL = -3.0V for pulse width less than 20ns.

DC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

Vee = 5.0V ±10%

TEST CONDITIONS

MIN.

lIu l

Input Leakage Current

Vee = Max.• VIN = GND to Vee

MIL.
COM'L.

IILol

Output Leakage Current

Vee= Max.
CS = VIH , VOUT = GND to Vee

MIL.
COM·L.

VOL

Output Low Voltage

VOH

Output High Voltage

1DT71257S
MAX.

IDT71257L
MIN.
MAX.

-

10

-

-

5

5
2

UNIT
/-lA

-

10

5

10L = 8mA, 'te = Min.

-

-

0.4

-

0.4

V

10L = 10mA. Vee = Min.

-

0.5

-

0.5

V

10H = -4mA, Vee = Min.

2.4

-

2.4

-

V

4-114

5
2

J.lA

IOT71257S/IOT71257L CMOS
STATIC RAM 256K (256Kx 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (1) (VCC =
SYMBOL

\

ICCl

ICC2

PARAMETER
Operating Power
Supply Current
CS = VIL,
Outputs Open,
Vce = Max., f = 0(3)

S

L

Dynamic Operating
Current
CS = VIL ,
Outputs Open,
Vcc = Max., f = f MAX (3)

S

L

Standby Power
Supply Current
(TTL Level)

IS6

READ

60

-

50

60

50

60

50

60

WRITE(2)

110

-

100

110

100

110

100

110

-

110

READ

40

-

30

40

30

40

30

40

-

40

WRITE(2)

100

-

90

100

90

100

90

100

160

150

160

150

160

150

160

WRITE(2)

160

-

150

160

·150

160

150

160

READ

140

-

130

140

130

140

130

140

-

100

READ

WRITE(2)

140

-

130

140

130

140

130

140

-

140

35

'-

35

35

35

35

35

35

-

35

S

UNIT

60
rnA

160
160

rnA

140

rnA

CS ~ \1H,
Vcc= Max.,
Outputs Open,
f = fMAX(3)

IS61

5V ±10%, VLC = 0.2V, VHC = VCC - 0.2V)

I DT71257S25 IDT71257S35(4) IDT71257S45 IOT71257S55 1OT71257S70
I DT71257L35 (4) IDT71257L45 IDT71257L55 IDT71257L70
POWER FUNCTIOtI IDT71257L25
COM'L. MIL. COM'L.
MIL. COM'L. MIL. COM'L. MIL COM'L MIL

Full Standby Power
Supply Current
(CMOS Level)

L

20

-

20

20

20

20

20

20

-

20

S

30

-

30

35

30

35

30

35

-

35

L

1.5

-

1.5

4.5

1.5

4.5

1.5

4.5

-

4.5

rnA

CS ~ VHC ' Vcc= Max.
f = 0(3)

NOTES:
1. All values are maximum guaranteed values.
2. Write cycle current specifications are included to aid in the design of extremely sensitive applications. It should be noted that in most systems the ratio of
read cycles to write cycles is extremely high. When comparing these figures to those on other data sheets, we recommend that the read cycle data is used
(especially where "Average" current consumption figures are specified).
3. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of l/tRC' f = 0 means no input lines change.
4. Preliminary data for military devices only.

CAPACITANCE
SYMBOL
CIN

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

CONDITIONS
VIN = OV

Input Capacitance

MAX.

UNIT

11

pF

COUT
Output Capacitance
Vour= OV
11
pF
NOTE:
1. This parameter is determined by device characterization but is not
production tested.

TRUTH TABLE

(VLC = 0.2V, VHC = VCC - 0.2V)

WE

CS

OUTPUT

MODE

X

H

Hi-Z

Standby (IS6)
Standby (IS61)

X

VHC

Hi-Z

H

L

DOUT

Read

L

L

Hi-Z

Write

NOTE:
1. H = '-"H' L = VIL, X = Don't Care

4-115

I DT71257S/1 DT71257L CMOS
STATIC RAM 256K (256K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = Vcc - 0.2V
TYP,(1)
SYMBOL
VDR
Icc DR

PARAMETER

TEST CONDITIONS

MIN.

-

Vcc for Data Retention

I MIL.

Data Retention Current

t CDR (3)

Chip Deselect to Data Retention Time

t R(3)

Operation Recovery Time

CS ~VHC

I COM'L.

Vcc@
3,OV
2.0V

-

-

-

-

-

50

75

2000

3000

-

50

75

500

750

0

-

-

ns

-

-

-

-

t RC (2)

-

ns

LOW Vee DATA RETENTION WAVEFORM

DATA RETENTION MODE
4.5V

AC TEST CONDITIONS
GND t03.0V
5ns

1.5V
1.5V
See Figures 1 and 2

:q

5V

DATA OUT

2550

5V

4800
DATA OUT
30pF*

~

2550 .

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for tOUt tcu. t OHZ •
tWHZt tCHZ. tow)

*Including scope and jig.

4-116

UNIT

2.0

NOTES:
1. TA = +25°C
2. t Rc = Read Cycle Time
3. This parameter is guaranteed, but not tested.

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Leve!s
Output Reference Levels
Output Load

MAX.
V cc @
2.0V
3.0V

V

IlA

I DT71257S/I DT71257L CMOS
STATIC RAM 256K (256Kx 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(Vcc = 5V ±10%, All Temperature Ranges)

IDT71257S25(1)
1DT71257L25(1)
MIN.
MAX.

1DT71257S35
IDT71257L35
MIN.
MAX.

IDT71257S45
I DT71257S55 IDT71257S70(2)
1DT71257L55 1DT71257L70(2)
IDT71257L45
MAX. MIN.
MIN.
MAX. MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

25

-

35

-

45

-

55

-

70

-

ns

tAA

Address Access Time

-

25

35

-

70

ns

-

30

35

45

-

55

Chip Select Access Time

-

45

t AcS

-

55

-

70

ns

tCLZ

Chip Select to Output in Low Z (3)

5

-

5

-

5

-

5

-

5

-

ns

tpu

Chip Select to Power Up Time (3)

0

-

0

-

0

-

0

-

0

-

ns
ns

tpD

Chip Deselect to Power Down TIme(3)

-

25

-

45

-

70

-

13

15

-

20

-

55

Chip Deselect to Output in High Z (3)

-

35

tCHZ

25

-

30

ns

tOH

Output Hold from Address Change

5

-

5

-

5

-

5

-

5

-

ns

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.

4-117

IDT71257S/IDT71257L CMOS
STATIC RAM 256K (256K x l·BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

=i

l-----------

ADDRESS

tRC

----------t~

~--~-~------------------------~-tAA-----------------.-I----------

~-----

t ACS

-------t

104----- t CLZ (4) ----~
DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.2

(1,2)

ADDRESS

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.3 (1,3)

DATA OUT

NOTES:
1. WE is high for read cycle.
2. Device is continuously selected, CS = V1L •
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±200mV from steady state with 5pF load (including scope and jig).

4-118

--to-H
-------------

IDT71257S/IDT71257L CMOS
STATIC RAM 256K (256K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(VCC = 5V ±10%, All Temperature Ranges)

IDT71257S25(1)
IDT71257L25(1)
MAX.
MIN.

IDT71257S35
IDT71257L35
MIN.
MAX.

IDT71257S45
IDT71257S55 I DT71257S70(2)
IDT71257L45
1DT71257L55 I DT71257L70(2)
MAX, MIN.
MIN.
MAX. MIN.
MAX.

UNIT

WRITE CYCLE
30

-

40

-

50

-

ns

40

-

50

60

-

ns

30

-

-

60

30

20

-

40

-

60

-

ns

-

0

-

0

-

50

0

0

-

0

-

ns

Write Pulse Width

20

-

30

-

40

50

-

60

-

ns

tWA

Write Recovery Time

0

-

0

-

0

-

0

-

0

-

ns

tWHZ

Write Enable to Output in High Z (3)

-

13

-

15

-

20

-

25

-

30

ns

tDW

Data Valid to End of Write

15

20

-

30

0

-

5

-

ns

5

-

35

Data Hold Time

-

25

tDH

-

twc

Write Cycle Time

20

tcw

Chip Select to End 'of Write

20

tAW

Address Valid to End of Write

t AS

Address Set-up Time

twp

Output Active from End of Write (3)
tow
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to +125°C temperature range only.
3. This parameter guaranteed but not tested.

0

4-119

0

-

0

5

-

5

0
5

ns
ns

I DT71257S/1 DT71257L CMOS
. STATIC RAM 256K (256K X 1-81T)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1
(WE CONTROLLED TIMING)

(1,2,3)

twe

ADDRESS

~

--.-/

<

'./

/'
tAW

~,

/~
t AS

twp

,
/

'I\.

t WR ---

4-tWHZ(5~

-

DATAoUT

,::::::

tOW---

.. ::::.::<,

-----t(F
.: ... :."

~::::::::::):i

/'

~c

tow

.1.
I

tOH

TIMING WAVEFORM OF WRITE CYCLE NO.2 (1,2,3,4)
(CS CONTROLLED TIMING)

twe

ADDRESS

~

)(

--.-/ (
tAw

-

.

'AS

t

~

tew

/
tWR

,,-----------------------NOTES:
1. Vir=. or CS must be high during all address transitions.
2. A write oeeurs during the overlap (tew or twF) of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of the write cycle.
4. If the CS low transition occurs simultaneous with or after the WE low transition. the outputs remain in the high impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).

4-120

IDT71257S/IDT71257L CMOS
STATIC RAM 256K (256K xl-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxxx

999

Device Type

Speed

A
Package

A
Process/
Temperature
Range

y:Mk

IC
......- - - - - - - - il SO
25
35

Commercial (O°C to

Military (-55°C to + 125°C)
Compliant with MIL-STD-883, Class B
Sidebraze DIP
Small Outline IC
Commercial Only

~----------~45

55
70
L..-._ _ _ _ _ _ _ _ _ _ _ _--II

L

IS
......_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 71257

4-121

+ 70°C)

l

Speed In Nanosocon'"

Military Only
Low Power
Standard Power

256K (256K x 1-Bit) Static RAM

FEATURES:

DESCRIPTION

• High-clensity 256K (256K x 1) CMOS static RAM module
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
• Available in 28-pin SIP (single in-line package) for maximum
space saving

The IDT7MP156Is a 256K (256K x 1-bit) high-speed static RAM
module constructed on an epoxy laminate surface using four
IDT7187 64K x 1 static RAMs In surface mount packages. Extremely fast speeds can be achieved with this technique due to use
of 64K static RAMs fabricated In IDT's high-performance, high-reliability CEMOS technology.
The 7MP family of surface mounted SIP technology is a costeffective solution allowing for very high packing density. The
IDT7MP156 is offered in"a28-pln SIP (single in-line package). The
IDT7MP156 can be mbuht;~ on 200 mil centers, yielding 1.25
megabits of memo~J~,!eSefthan 3 square inches of board space.
The IDT7MP156Is'avallable with maximum access times as fast
as 25ns with ma~mum power consumption of 1.8 watts. The module also offe~~;:full,::~andby mode of 440mW (max.).
All input~,al;1d'outputs of the IDT7MP156 are TTL-compatible
single 5V supply. Fully asynchronous circuitry
and oper~t~
is used~,~e~iridg no clocks or refreshing for operation, and providing ~Rbal'~~CFess and cycla times for easa of usa.

• Fast access times: 25ns (max.) over commercial temperat\Jre
• Low power consumption
- Dynamic: less than 600mW (typ.)
- Full standby: less than 30mW (typ.)
• Utilizes IDT7187 high-performance 64K static RAMs produced with advanced CEMOS TM technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)

frOrn'a

• Single 5V (±10%) power supply
e Inputs and outputs directly TTL-compatibla

f'~~~;~""':~l~;~;~,t ~,.

PIN CONFIGURATION
Vee
A4
A,
As
A'3
WE"0

GEl
A2
A'2
As
A'0
WE"1

CE'1
Ao
A7
A9
A6
~
WE"2
DATA OUT
DATA IN
A3
All

~
WE"3
A'4
A,s
GND

64Kx 1

~~~ ---=':~--1

10
11
12

RAM

64Kx 1
RAM

64Kx 1
RAM

DATA
IN

DATA
OUT

64Kx 1
RAM

'11.. '

,~

14
IS
16
17
18
19

M11(1)

20

21
22

23
24
2S

PIN NAMES
A o-A ,S

26

27
28
SIP
TOP VIEW

NOTE:
1. For module dimensions, plese refer to module drawing M11 in the packaging section.

Address Unes

QN

Data Input

Q:,UT

Data Output

CE"0-3
WE"0-3

Chip Enable
Write Enable

Vee

Power

GND

Ground

CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated DevIce Technology. Inc..

DSC-7005/-

4-122

FEATURES:

DESCRIPTION:

• High-density 256K (256K x 1) CMOS static RAM module
• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• Available in low profile 28-pin ceramic SIP (single in-line
package) for maximum space saving
• Fast access times: 25ns (max.) over commercial temperature

The IDT7MC156 is a 256K (256K x 1-bit) high-speed static RAM
module constructed on a co-fired ceramic substrate using four
IDT7187 64K x 1 static RAMs in surface mount packages.
The 7MC family of ceramic SIPs offers the optimum in packing
density and profile height. The IDT7MC156 is offered in a 28-pin
p
profile package
is ideal
systems
with
minimal
board
ceramic
SIP (single
in-lin.,. ,.for
.e
. . . . .. . . a
. ckage). ,At
only
350 mils
high,spacing.
this low
Surface mount SIP technology also yields very high packing density, allowing greater than three IDT7MC156 modules to be
stacked per inch of bo;(f:a.~ce.
The IDT7MC156 i~'availat)fe with maximum access times as fast
as 25ns and maximuffi':~yver consumption of 1.8 watts. The module also offers a.full stanoby mode of 440mW (max.).
All inputs ~,
guts of the IDT7MC156 are TTL-compatible
and operate '. "'. Ingle 5V supply. Fully asynchronous circuitry
is used, re· ,\~''',. '<'rib clocks or refreshing for operation, and providtimes for ease of use.
ing eq

• Low power consumption
- Dynamic: less than 600mW (typ.)
- Full standby: less than 30mW (typ.)
• Utilizes IDT7187s high-performance 64K static RAMs produced with advanced'CEMOS TM technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible

PIN CONFIGURATION
Vee
A4
A,
A5
A'3
WE'D

CEO
A2
A'2
A8
A,D
WE'1
~,

AD
A7
A9
As

~2

WE'2
DATA OUT
DATA IN
A3
A11

'C'E3
WE'3
GND
A'4
A5
'

64Kx 1
RAM

10
11
12
13
14
15

64Kx 1
RAM

64Kx 1
RAM

64Kx 1
RAM

M16(1)

IS

17
18
19
DATAoUT

20

21
22

23
24
25

PIN NAMES

26

27
28
SIP
SIDE VIEW

NOTE:
1. For module dimensions, please refer to module drawing M16 in the packaging section.
CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
© 1987 Integrated 0eIItce Technology. Inc.

A o-A,S

Address Unes

DIN

Data Input

DoUT

Data Output

~o-3

Chip Enable

WE'o-3

Write Enable

Vee

Power

GND

Ground

DECEMBER 1987
4-123

DSC-7002/-

4

FEATURES:

DESCRIPTION:

• High-speed (equal access and cycle time)

The 10T71258Is a 262,144-bit high-speed static RAM organized
as 64K x 4. It is fabricated using lOT's high-performance, high-reliability CEMOS technology. This state-of-the-art technology, combined with iQnovative circuit design techniques, provides a costeffective alternative to bipolar and fast NMOS memories.
Access times as fast as 25ns are available with typical power
consumption of only 350mW. The 10T71258 offers a reduced
power standby mode, ISB1, which enables the deSigner to greatly
reduce device power requirements. This capability provides significant system level power and COOling savings. The low-power
(L) .version also offers a battery backup data retention capability
where the circuit typically consumes only 100~W operation off a
2V battery.
, All inputs and outputs of the 10T71258 are lTL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for,operation, providing equal access and cycle times
for ease of use.
The 10T71258 is packaged in a 24~pin 300 mil 'DIP and a 24-pin
SOIC providing high board-level packing densities.
Military grade product Is manufactured in compliance with the
latest revision of MIL-STO-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

- Military: 35/45/55/70ns (max.)
- Commercial: 25/35/45/55/ns (max.)
• Low-power operation
-10T71258S
Active: 400mW (typ.)
Standby:

400~W

(typ.)

-IDT71258L
Active: 350mW (typ.)
Standby: 100~W (typ.)
• Battery backup operation-2V data retention (L version only)
• Produced with advanced CEMOS ™ high-performance
technology.
• Single 5V (±10%) power supply
• Input and output directly lTL-compatibie
• Static operation: no clocks or refresh required
• Available In high-density Industry standard 24-pin, 300 mil DIP
and 24-pin SOIC
• Three-state outputs
• Military product compliant to MIL-STO-883, Class B

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION
Ao
Al

r

Vee
A1S
A14
A13
A12
All
Al0

A2
A3
A4
As
Ae
A7
A8
A9

Vee

Ao

ADDRESSES~

DECODER

CS

GND

L

A,S

1/0 4
1/0 3
1/0 2
1/0 1

INPUT
. DATA
CONTROL

~

GND

262,144-81T
MEMORY ARRAY

DIP/SOle
TOP VIEW

PIN NAMES
Ao - A,S

WE
GND

Addresses
Data Input/Output
Chip Select
Write Enable
Ground

Vee

Power

1/0, -1/04
~

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

4-124
---

_.. - - , - " ' - - - - -

DECEMBER 1987
DSC-l017/-

IDT71258S/IDT71258L CMOS
STATIC RAM 256K (64Kx 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

LOGIC SYMBOL

GRADE

Ao
Al
A2
A3
A4
As
Aa
A7
As
As
AlO
All
A12
A 13
A14
A 15

Military
1/0 1

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND
OV

5.oV ± 10%

O°Cto +70°C

OV

5.oV ± 10%

Commercial

Vee

1/0 2
1/0 3

ABSOLUTE MAXIMUM RATINGS

1/0 4

~

SYMBOL

WE

RATING

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

o to +70

-55 to +125

°C

TB1AS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

MIN.

TYP.

MAX.

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H
V1L

Input High Voltage

2.2

-

6.0

V

o.B

V

PARAMETER

Input Low Voltage

-0.5(1)

UNIT

NOTE:
1. V1L = -3.OV for pulse width less than 2ons.

DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ±10%
SYMBOL
Ilu l
IILOI

PARAMETER
Input Leakage Current
Output Leakage Current

VOL

Output Low Voltage

VOH

Output High Voltage

IDT71258S
MAX.
MIN.

TEST CONDITIONS
Vee = Max., V1N = GND to Vee

MIL.
COM'L.

-

Vee= Max.
CS = \'IH, VOUT = GND to Vce

MIL.
COM'L.

-

1DT71258L
MIN.
MAX.

UNIT

10
5

-

5
2

J.1A

-

10
5

5
2

J.1A

10L = BmA, Vee = Min.

-

0.4

-

0.4

V

10L = 10mA. Vee = Min.

-

0.5

-

0.5

V

10H = -4mA, Vee = Min.

2.4

-

2.4

-

V

4-125

-

I DT71258S/I DT71258L . CMOS
STATIC RAM 256K (64K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS(1)
SYMBOL

PARAMETER

POWER

(Vcc = 5V ±10%, V LC = 0.2V, VHC = Vcc - 0.2V)

FUNCTION

1DT71258S25 IDT71258S35(4) I DT71258S45 IDT71258S55
IDT71258L25 I DT71258L35 (4) 1DT71258L45 IDT71258L55
COM'L. MIL.

Icc1

Icc2

Operating Power
Supply Current
CS = VIL,
Outputs Open,
Vcc = Max., t. = 0(3)

S

L

Dynamic Operating
Current
CS = VIL ,
Outputs Open,
Vee = Max., t. = t. MAX (3)

S

L

Standby Power
Supply Current
(TTL Level)
CS ;:::VIH ,
Vcc = Max., Outputs
Open t. = t.MAX (3)

ISB

ISB1

COM'L. MIL.

COM'L. MIL.

COM'L. MIL.

IDT71258S70
1DT71258L70

READ

60

-

50

60

50

60

50

60

-

60

WRITE (2)

110

100

110

100

110

100

110

-

110

READ

40

30

40

30

40

30

40

-

40

WRITE (2)

100

-

90

100

90

100

90

100

-

100

READ

160

-

150

160

150

160

150

160

-

160

WRITE (2)

160

160

150

160

150

160

-

160

READ

140

130

140

130

140

130

140

-

140

WRITE (2)

140

-

150

130

140

130

140

130

140

-

140

35

-

35

35

35

35

35

35

-

35

S

-

UNIT

COM'L. MIL.

mA

mA

mA

Full Standby Power
Supply Current
(CMOS Level)

L

-

20

-

20

20

20

20

20

20

-

20

S

-

30

-

30

35

30

35

30

35

-

35
mA

CS ;::: VHC ' Vcc = Max.,
f= 0(3)

L

-

1.5

-

1.5

4.5

1.5

4.5

1.5

4.5

-

4.5

NOTES:
1. All values are maximum guaranteed values.
2. Write cycle current specifications are included to aid in the design ot. extremely sensitive applications. It should be noted that in most systems the ratio of
read cycles to write cycles is extremely high. When comparing these figures to those on other data sheets, we recommend that the read cycle data is used
(especially where ·Average· current consumption figures are specit.ied).
3. At t. = t.MAX address and data inputs are cycling at the maximum t.requency of read cycles ot. /tRC. f = 0 means no input lines change.
4. Preliminary data t.or military devices only.

CAPACITANCE
SYMBOL
C iN

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

Input CapaCitance

CONDITIONS

MAX.

"IN = OV

1i

\I

UNIT

pF
COLrr
Output CapaCitance
VOLrr=OV
11
pF
NOTE:
1. This parameter is determined by device characterization but is but production tested.

TRUTH TABLE

(VLC = 0.2V, VHC = Vee - O.2V)

WE

CS

I/O

MODE

X

H

Hi-Z

Standby (lsB)
Standby (ISB1)

X

V HC

Hi-Z

H

L

DOLrr

Read

L

L

DIN

Write

NOTE:
1.

H = "IH' L = VIL, X = DON'T CARE

4-126

10171258S/I DT71258L CMOS
STATIC RAM 256K (64K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = Vcc - 0.2V
SYMBOL
VDR
ICCDR

TEST CONDITIONS

PARAMETER·

MIN.

-

Vcc for Data Retention
Data Retention Current

t CDR (3)

Chip Deselect to Data Retention Time

t R(3)

Operation Recovery Time

CS ~VHC

I MIL.
I COM'L.

TVP,(1)
Vcc @
2.0V
3.0V

2.0

-

-

-

-

-

50

75

2000

3000

-

50

75

500

750

-

0

-

-

-

t RC (2)

-

-

-

NOTES:
1. TA '= +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.

LOW Vee DATA RETENTION WAVEFORM

DATA RETENTION MODE

"'H

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2

SV

DATA OUT

~

2S50

SV

480n
DATA OUT
30pF*

~

2550

Figure 1. Output Load

480n
5pF*

Figure 2. Output Load
(for toLZ. tCLZ. tOHZ.
tWHZo tCHZ. to~

*Including scope and jig.

4-127

MAX,
Vcc @
2.0V
3.0V

UNIT
V

J.LA
ns
ns

IDT71258S/IDT71258L CMOS
STATIC RAM 256K (64K X 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
SYMBOL

Vcc = 5V ±10%, All Temperature Ranges

I DT71258S25 (1) 1DT71258S35
IDT71258L25 (1) IDT71258L35
MIN.
MAX. MIN.
MAX.

PARAMETER

IDT71258S55 1DT71258S70(2)
IDT71258S45
IDT71258L55 IDT71258L70 (2)
IDT71258L45
MAX.
MAX. MIN.
MAX. MIN.
MIN.

UNIT

READ CYCLE
t RC

Read Cycle Time

25

-

35

-

45

-

55

-

70

-

ns

tAA

Address Access Time

-

25

-

35

-

45

-

55

70

ns

t ACS

Chip Select Access Time

-

30

-

35

-

45

-

55

-

70

ns

5

-

5

5

-

5

-

0

0

-

0

-

ns

0

-

5

Chip Select to Power Up Time(3)

-

t pD

Chip Deselect to Power Down Time(3)

-

25

35

-

55

ns

-

13

15

20

-

25

-

70

Chip Deselect to Output in High

-

45

tCHZ

-

30

ns

tOH

Output Hold from Address Change

5

-

5

-

5

-

5

-

5

-

ns

tCLZ
, t pu

Chip Select to Output in Low Z

(3)

Z(3)

NOTES:
1. O°C to + 70°C temperature range only.
2. -55 ° C to + 125 ° C temperature range only.
3. This parameter guaranteed. but not tested.

4-128

0

ns

_ _ _ _ _ _ 000 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _

1DT71258S/IDT71258L CMOS
STATIC RAM 256K (64K X 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.

---.cl4----'--._
-tloo-I---------

1(1)

_-~_

-_tR_C-

ADDRESS

tM

-------..-.1.'

"--------.;.°t ACS
1 + - - - - - t cLZ (4)

--------..1

- - - -...

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO. 2 (1~2)

ADDRESS

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.3 (1,3)

NOTES:
1.
2.
3.
4.

~ is high for read cycle.

Device is continuously selected, ~ = V1L •
Address valid prior to or coincident with CS transition low.
Transition is measured ±200mV from steady state with 5pF load (including scope and jig).

4-129

~

tOH

IDT71258S/IDT71258L CMOS
STATIC RAM 256K (64K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
SYMBO

PARAMETER

Vcc = 5V ±10%. All Temperature Ranges

IDT71258S25 (1) IDT71258S35
IDT71258L25 (1) 1DT71258L35
MAX. MIN.
MAX.
MIN.

IDT71258S45
IDT71258S55 IDT71258S70(2)
1DT71258L45
IDT71258L55 IDT71258L70 (2)
'MAX. MIN.
MIN.
MAX. MIN.
MAX.

UNIT

WRITE CYCLE
40

-

50

-

60

-

40

-

50

60

40

-

50

60

0

0

-

50

-

60

0

-

-

0

-

0

-

0

-

13

-

15

-

20

-

25

-

30

ns

20

-

30

35

-

0

0

-

ns

0

-

5

-

5

-

25

0

-

5

-

5

-

5

-

two

Write Cycle Time

20

tow

Chip Select to End of Write

20

-

30

tAW

Address Valid to End of Write

20

-

30

t AS

Address Set-up Time

·0

0

twp

Write Pulse Width

20

30

tWR

Write Recovery Time

0

-

tWHZ

Write Enable to Output in High Z (3)

-

tDW

Data Valid to End of Write

15

tDH

Data Hold Time

tow

Output Active from End of Write (3)

30

0

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed. but not tested.

4-130

40

0

ns
ns
ns
ns
ns
ns

ns
ns

IDT71258S/IDT71258L CMOS
STATIC RAM 256K (64K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)(1,2,3,6)
~----------------------twc----------------------~

ADDRESS

_____________________________)(~__________

~K

....- - - - - - - - - - - - - - - - - - tAW

---+--

-----------------~

/~

'-------------------------------~----'
WR

r-- t AS

--~--------

twp

------------..t:.-t

~,

-

/~

'---------------------------, 1 4 - - - - tow

+-- tWHZ ( 6 ) _

-----.j

DATA OUT

TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING) (1, 2, 3,5)

two

ADDRESS

~

--../ (

)K.
tAW

'~

//
... t WR - '

t AS

tow

/"

.. I.

NOTES:
1.
or CS must be high during all address transitions.
2. A write occurs during the overlap (tow or tw~ of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the
low transition, the outputs remain in the high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).

wr=.

wr=.

4-131

I DT71258S/1 DT71258L CMOS
STATIC RAM 256K (64K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XXX)(

A

999

A

A

Device Type

Power

Speed

Package

Process/
Temperature
Range
Commercial (O°C to

Y:,onk

+ 70°C)

Military (-55°C to + 125°C)
Compliant with MIL-STD-883. Class 8

'------------t

C
SO

Sidebraze DIP
Small Outline IC

Commercial Only

'---------------1

25
35
45
55
70

L
--I S

L-..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _

1.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1

4-132

71258

1

Speed In Nono,eoond,

Military Only
Low Power
Standard
Power
256K (64K x 4-Bit) Static RAM

----_.----------------------------------------------------------------------------------------

FEATURES:

DESCRIPTION:

• Fast Output Enable (OE) pin available for added system
flexibility
• High speed (equal access and cycle times)
- Military: 35/45/55/70ns (max.)
- Commercial: 25/35/45/55ns (max.)
• Low power consumption
- IDT61298S
Active: 400mW (typ.)
Standby: 400}Jw (typ.)
- IDT61298L
Active: 350mW (typ.)
Standby: 1OO}Jw (typ.)
• Battery back-up operation-2V data retention (L version only)
• JEDEC standard pinout
• 28-pin sidebraze DIP
• Produced with advanced CEMOS TM technology
• Bidirectional data inputs and outputs
• Inputs/Outputs TTL-compatible
• Three-state outputs
• Military product compliant to MIL-STD-883, Class 8

The IDT61298 is a 262,144-bit high-speed static RAM organized
as 64K x 4. It is fabricated using IDT's high-performance, high-reliability technology-CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost effective approach for memory intensive applications.
The IDT61298 features two memory control functions: Chip
Select (CS) and Output Enable (OE). These two functions greatly
enhance the IDT61298's overall flexibility in high-speed memory
applications.
.
Access times as fast as 25ns are available with typical power
consumption of only 350mW. The IDT61298 offers a reduced
power standby mode, 15B1. which enables the deSigner to considerably reduce device power requirements. This capability significantly decreases system power and cooling levels, while greatly
enhancing system reliability. The low-power (L) version also offers
a battery backup data retention capability where the circuittypically consumes only 100}JW when operating from a 2V battery.
All inputs and outputs are TTL-compatible and the device operates from a single 5 volt supply. Fully static asynchronous circuitry,
along with matching access and cycle times, favor the simplified
system design approach.
The IDT61298 is packaged in a 28-pin sidebraze THINDIP providing improved board-level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

FUNCTIONAL BLOCK DIAGRAM
A

GND
DECODER

262.144-BIT
MEMORY ARRAY

COLUMN I/O

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology, Inc.

DECEMBER 1987
4-133

OSC-1006/-

91
~

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT61298S/IDT61298LCMOS STATIC RAM 256K (64Kx 4-BIT)

LOGIC SYMBOL

PIN CONFIGURATION
Vee
A15

NC
Ao
Al
A2
A3
A4

Ao
Al
A2
A3
A4
A5
AS
A7
As
Ag
A10
All
A12
A13
A14
A15

A14
A13
A12
All
A10
NC
NC

A5
A6
A7
As
Ag

1/04
1/0:3

~

1/Cl.!

OE'

1/01

GND

~

1/01

1ICl.!

1/0:3

1/04

DIP

TOP VIEW

~

PIN NAMES
CS

Address Inputs
Chip Select

WE
OE

Write Enable
Output Enable

Ao-A15

1/01-4
\bc
GND

Data Input/Output
Power
Ground

4-134

OE'

~

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT61298S/IDT61298LCMOS STATIC RAM 256K (64Kx 4-BIT)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL

MILITARY

UNIT

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

o to + 70

TalAs

Temperature
Under Bias

-55 to + 125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to + 125

-65 to +150

°C

-0.5 to +7.0

-0.5 to +7.0

SYMBOL

V

-55 to +125

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

MIN.

TYP.

MAX.

Vcc

Supply Voltage

PARAMETER

4.5

5.0

5.5

UNIT
V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

-

6.0

V

VII...

Input Low Voltage

-0.5(1)

-

O.S

V

NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Military
Commercial

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V ± 10%

Vec

DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V ±10%
SYMBOL
Ilu l
IILOI

PARAMETER
Input Leakage Current
Output Leakage Current

VOL

Output Low Voltage

VOH

Output High Voltage

TEST CONDITIONS

MIN.

IDT61298S
TYP,<1) MAX.

= GND to Vee

MIL.
COM'L.

-

-

10
5

-

CS" = VIH , VOUT = GND to Vee

MIL.
COM'L.

-

Vee = Max., VIN
Vee

= Max.

10L = 10mA, Vcc = Min.
10L = SmA, Vee

= Min.
10L = -4mA, Vee = Min.

2.4

NOTE:
1. Typical limits are at Vee = 5.0V, + 25°C ambient.

4-135

MIN.

IDT6129SL
Typ.(1) MAX.

-

10
5

-

-

0.5

-

UNIT

-

5
2

JlA

-

5
2

JlA

-

-

0.5

V

0.4

-

-

0.4

V

-

2.4

-

-

V

MILITARY AND COMMERCIAL TEMPERATURE RANGES

I DT61298S/IDT61298L CMOS STATIC RAM 256K (64K X 4-BIT)

DC ELECTRICAL CHARACTERISTICS (1)
SYMBOL

PARAMETER
Operating Power
Supply Current

ICCI

ICC2

ISB

ISBI

CS = VIL.
Outputs Open.
Vcc = Max.• f = 0(3)
Dynamic Operating
Current
c:;s = VIL•
Outputs Open.
Vcc = Max.• f = fMAX (3)
Standby Power
Supply Current
(TTL Level)

POWER

S

L

S

L

= 5.0V ±10%. VLC = 0.2V. VHC = Vcc -0.2V

IDT61298S25 IDT61298S35 (2 IDT61298S45 IDT61298S55 IDT61298S70
IDT61298L25 IDT61298L35(2) IDT61298L45 IDT61298L55 IDT61298L70
COM'L MIL COM'L MIL COM'L MIL COM'L MIL COM'L MIL

READ

60

50:.

WRITE (4)

110

16.0

READ

40

WRITE (4)

100

{bi:(;:::;:'
:::tt®.:::::·

100

90

READ

160

\::::J~'

160

150

WRITE (4)

160

.:::::;:

':::::::::150

160

150

READ

140

-===::;::.;

:::.::]:30

140

130

WRITE (4)

140

,;:z.:.: :::}:::130
..:;..:.:........

140

S

35

60
.....:.::: 110
40

50

60

50

60

60

100

110

100

110

110

30

40

30

40

40

100

90

100

100

160

150

160

160

160

150

160

160

140

130

140

140

130

140

130

140

140

35

35

35

35

35

UNIT

mA

.;.;.

.:::::::::::::::::

.....

i;::: 35

35

mA

::::::::;:::7::::::::
mA

CS? VIH
Vcc = Max.• f = fMAX (3)
Outputs Open.

L

Full Standby Power
Supply Current
(CMOS Level)

S

CS ~ ~c
Vcc = Max.. f

L

= 0(3)

FUNCTION

Vcc

..:::::::::::::i::/W·
20

20

20

20

20

20

20

20

30

30

35

30

35

30

35

35

1.5

1.5

4.5

1.5

4.5

1.5

4.5

4.5

to;:;::::::'
.::::::::{:::\::/
mA

NOTES:
1. All values are maximum guaranteed values.
2. Preliminary data for military devices only.
3. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of l/tRC. f = 0 means no input lines change.
4. Write cycle current specifications are included to aid in the design of extremely sensitive applications. It should be noted that in most systems the ratio of
read cycles to write cycles is extremely high. When calculating total current consumption. the designer should weight these figures by the percentage of
·On" time as well as the anticipated ratio of read to write cycles (usually greater than 90%).

4-136

I DT61298S/1 DT61298L CMOS STATIC RAM 256K (64K x 4·Bln

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VHC = Vce - 0.2V
SYMBOL
VDR
ICCDR

TEST CONDITION

PARAMETER

-

Vcc for Data Retention

t CDR (3)

Chip Deselect to Data Retention Time

t R(3)

Operation Recovery Time

Ilu l (3)

Input Leakage Current

CS~

MAX.
Vee @
2.0V
3.0V

2.0

-

-

-

-

-

50

75

2000

3000

50

75

500

750

I COM'L.
MIL.

Data Retention Current

TYP.(1)
Vee @
3.0V
2.0V

MIN.

-

-

ns

-

-

ns

-

-

2

~A

DATA RETENTION MODE
4.5V

"'IH

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

5V

DATAoUT

~

2550

5V

480Cl
DATAoUT
30pF*

~

2550

4800
5pF*

Figure 2. Output Load
(for teLZ ,t OLZ ,tCHz , t OHZ ,
tow and t wHZ )

Figure 1. Output Load

* Including scope and jig.

4-137

~A

0

LOW Vee DATA RETENTION WAVEFORM

VDR ~ 2V

V

t RC (2)

VHC

NOTES:
1. TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.

VCC

UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT61298S/IDT61298L CMOS STATIC RAM 256K (64K X 4-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(Vcc = 5V ±10%. All Temperature Ranges)
61298S25 (1)
61298L25 (1)
MIN.
MAX.

61298S35(4)
61298L35 (4)
MIN. MAX.

61298S45
61298L45
MIN. MAX.

61298S55
61298L55
MIN.
MAX.

61298S70(2)
61298L70(2)
MIN. MAX.

UNIT

READ CYCLE
Read Cycle Time

t CLZ (3)

25

45

Address Access Time

25

Chip Select Access Time

30

..

.;:.;.:.....:.:.:::.:

35

55

Output Enable to Output Valid

70

ns

45

55

70

ns

5

5

ns

45

35

30

25

ns

55

5

Chip Select to Output in Low Z

70

45

t OLZ (3)

Output Enable to Output in Low Z

tCHZ (3)

Chip Select to Output in High Z

15

20

25

30

tOHZ (3)

Output Disable to Output in High Z

15

15

20

25

5

Output Hold from Address Change

5

5

o

Chip Select to Power Up Time
Chip Deselect to Power Down Time

35

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.
4. Preliminary data for military devices only.

4-138

5

5

ns

5

o
45

ns
ns
ns

o
55

ns

ns
70

ns

IDT61298S/IDT61298LCMOS STATIC

RA~

256K(64Kx 4-BIT)

TIMING WAVEFORM OF READ CYCLE NO.1

~

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(1)

t----------

ADDRESS

tRC

____________________:::::::::::::~--------------

Ioo-t--------

tAA

• '

14-----

tOE

-----l~

toLZ (5) - - - + I

~-------tAcs----~--~

14------ t CLZ (5)----.-j
DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)

j=~

RC

ADDRESS

OH
=1==:====-=-==_t=OH=_t
==t
=:>k-'
XJ-·,-=-=-_E==t =
AA

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.

3(1,3,4)

~------tACS----------+I
~----

tCLZ(5) _ _~

DATA OUT

Vcc

Icc

c3~~~~+

IS8

NOTES:

wr=.

1.
is High for Read Cycle.
2. Device is continuously selected, "C"S = V1L •
3. Address valid prior to or coincident with "CS" transition low.
4. DE" = \IL
5. Transition is measured ±200mV from steady state.

4-139

tCHZ (5)

14---.-1

IDT612988/1DT61298L CMOS STATIC RAM 256K (64K x 4-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(Vee = 5V ±10%, All Temperature Ranges)
61298S25 (1)
61298L25 (1)
MIN.
MAX.

61298835 (4)
61298L35 (4)
MIN.
MAX.

61298845
61298L45
MIN.
MAX.

61298S55
61298L55
MIN.
MAX.

61298870(2)
61298L70(2)
MIN. MAX.

UNIT

WRITE CYCLE
twe

Write Cycle Time

20

tew

Chip Select to End of Write

20

tAW

Address Valid to End of Write

20

t AS

Address Set-up Time

0

twp

Write Pulse Width

20

tWR
t WHZ (3)

Write Enable to Output in High Z

tow

Data Valid to End of Write

15

tOH

Data Hold Time

0

tow (3)

Output Active from End of Write

5

Write Recovery Time

0

;:::~~h::.

40

50

60

ns

40

50

60

ns

'<:::)30

40

50

60

ns

}:::::;O

0

0

0

ns

:::::. 30

40

50

60

ns

.{(:$.!:,

.:.;;::::
.::::::::':',

~:dI::

0

;.j::f:}·
:::::::;::;:"
:tt:::~
:;:Ii::;:::·

0
15

0
20

0
25

ns
30

ns

20

25

30

35

ns

0

0

0

0

ns

5

5

5

5

ns

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.
4. Preliminary data for military devices only.

4-140

IDT61298S/IDT61298L CMOS STATIC RAM 256K (64K x 4-Bln

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING) (1,2,3,7)
~........................................----......... twc------------------------~

ADDRESS

~.....- -.....------.....-------tAW

.....--------..........----~~

t wp

(7)

t WHZ (6)
1 4 - - - - tow

------~

DATA OUT

-------+CF=t~
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLED TIMING)

(1,2,3,5)

twc
ADDRESS

~

)(

---../ (
tAW

/~

'I\..
_t

AS

tWR

tew

__________________________________

-

~~-t-ow------.-r.-----to-H-~~------------

DATA IN

NOTES:
1.
2.
3.
4.
5.
6.
7.

WE or CS must be high during all address transitions.
A write occurs during the overlap (tcw or twp ) of a low CS and a low WE.
tWR is measured from the earlier of CS or WE going high to the end of the write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in the high impedance state.
Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).
If~ is low during a WE controlled write cycle, the write pulse width must be the larger oftwp or ("'/Hz+ tow) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t ow. If <::)E is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as
short as the specified twp .

4-141

IDT61298S/IDT61298L CMOS STATIC RAM 256K (64K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

TRUTH TABLE

SYMBOL

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

MODE

CS

WE

OE

I/O

POWER

Standby

H

X

X

HighZ

Standby

CIN

Input Capacitance

Read

L

H

L

DOUT

Active

COUT

Output Capacitance

Write

L

L

X

DIN

Active

Read

L

H

H

HighZ

Active

CONDITIONS

MAX.

UNIT

"IN = OV

11

pF

VOUT= OV

11

pF

NOTE:
1. This parameter is determined by device characterization but is not
production tested.

ORDERING INFORMATION
lOT

61298
Device Type

A
Power

999
Speed

A
Package

A
Process!
Temperature
Range

y~k
'----------1

'-------------i

C

Sidebraze DIP

25
35
45
55
70

Commercial only }

-I S
L

L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

'----------------------i

4-142

Military (-55°C to + 125°C)
Compliant with MIL-STD-883, Class B

61298

Speed in Nanoseconds
Military Only
Standard Power
Low Power
64K x 4-Bit

FEATURES:

DESCRIPTION:

•
•
•
•

The IDT71281/IDT71282 are 262,144-bit high-speed static
RAMs organized as 64K x 4. They are fabricated using IDT's highperformance, high-reliability technology-CEMOS. This 5tate-ofthe-art technology, combined with innovative circuit design
techniques, provides a cost effective alternative to bipolar and fast
NMOS memories.
Access times as fast as 25ns are available with typical power
consumption of only 350mW. These circuits also offer a reduced
power standby mode (Iss). When CS goes high, the circuit will
automatically go to, and remain in, this standby mode. The ultralow-power standby mode capability provides significant systemlevel power and cooling savings. The low-power (L) versions also
offer a battery backup data retention capability where the circuit
typically consumes only 100~W operating off a 2V battery.
All inputs and outputs of the IDT71281/IDT71282 are TTL-compatible and operate from a single 5V supply, thus simplifying system designs. Fully static asynchronous circuitry is used, which
requires no clocks or refreshing for operation, and provides equal
access and cycle times for ease of use.
The IDT71281/IDT71282 are packaged in 28-pin sidebraze
DIPs, providing high board-level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

Separate data inputs and outputs
IDT71281S/L: outputs track inputs during write mode
IDT71282S/L: I:ligh impedance outputs during write mode
High speed (equal access and cycle time)
- Military: 35/45/55170ns (max.)
- Commercial: 25/35/45/55ns (max.)

• Low power consumption
- IDT71281/2S
Active: 400mW (typ.)
Standby: 400~w (typ.)
- IDT71281/2L
Active: 350mW (typ.)
Standby: 100~w (typ.)
• Battery backup operation-2V data retention (L version only)
• High-clensity 28-pin DIP
• Produced with advanced CEMOS TM high-performance
technology
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
A

DECODER

262,144 BIT
MEMORY ARRAY

COLUMN I/O

'-++-1----1>- Y

'--f--+il>- Y

Y

L. _ _ _ _ _ _ _ _ _ _ .J

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
05C-1018/-

4-143

91
~

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT71281/1DT71282 CMOS STATIC RAMS 256K (64K x 4-BIT)

PIN NAMES

PIN CONFIGURATIONS
Ao
A1

Vcc
A15

A2
A3
A4

A14
A 13

A5
A6
A7

All
AlO
04

AS
Ag
01
O2

03

Ao-A15

Address Inputs

01- 0 4

DATA IN

CS

Chip Select

Y1 -Y4

DATA OUT

WE

Write Enable

GNO

Ground

Vc.c

Power

LOGIC SYMBOL

A12

Y4
Y3
Y2
Y1

CS

WE"

GND
DIP
TOP VIEW

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL

MILITARY

UNIT

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

Temperature
Under Bias

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

TSIAS

~.,..,

TSTG

-0.5 to +7.0

-0.5 to +7.0

-55 to +125

SYMBOL

V

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

rnA

TYP.

MAX.

Supply Voltage

PARAMETER

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

V

Input Low Voltage

-0.5(1)

-

6.0

VIL

0.8

V

UNIT

NOTE:
1. V!L (min.) = -3.0V for pulse width less than 20ns.

...............

...., .. vlu.~g

Temperature

MIN.

Vcc

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE

NOTE:
. 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods. may affect reliability.

Military
Commercial

4-144

AMBIENT
TEMPERATURE
-55°C to + 125°C
O°Cto +70 o C

GND

Vee

OV

5.0V

± 10%

OV

5.0V

± 10%

-----------------------------------------------------------------------------------------------

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT71281/IDT71282 CMOS STATIC RAM 256K (64K X 4-BIT)

DC ELECTRICAL CHARACTERISTICS (for all speeds)

-

Vcc = 50V +10%
SYMBOL

TEST CONDITION

PARAMETER

Vcc = Max., VIN

lIu l

Input Leakage Current

IILol

Output Leakage Current

VOL

Output Low Voltage

VOH

Output High Voltage

NOTE:
1. Typical limits are at Vee = 5.0V,

MIN.
MIL.
COM'L.

= GND to Vee

= Max.
= VIH , VOllT = GND to Vee
10L = 10mA, Vee = Min.
10L = 8mA, Vee = Min.
.loH = -4mA, Vcc = Min.

MIL.
COM'L.

Vec
~

-

IDT71281/2S
TYP.(1) MAX.

.

UNIT

-

-

-

5
2

JlA

-

-

5
2

JlA

0.5

V

0.4

V

-

V

-

10
5

-

10
5

-

-

0.5
0.4

-

-

-

2.4

-

2.4

IDT71281/2L
MIN. TYP.(1) MAX.

-

+ 25°C ambient.

DC ELECTRICAL CHARACTERISTICS(1)
= 50V -+10%, VLC = 02V VHC = Vcc -02V

Vcc

SYMBOL

PARAMETER

POWER

Operating Power /
ICCI

ICC2

ISB

ISBI

Supply Current
CS = VIL,
Outputs Open,
Vcc = Max., f = 0(2)
Dynamic Operating
Current
CS = VIL ,
Outputs Open,
Vcc = Max., f = fMA)«2)
Standby Power
Supply Current
(TTL Level),

S

L

S

L

S

71281/2S25
7128112L25

71281/2S35 (2)
71281/2L35(2)

71281/2S45
71281/2L45

COM'L MIL

COM'L MIL

COM'L MIL

L

Full Standby Power
Supply Current
(CMOS Level),

S

= Max.,

71281/2S55
71281/2L55

"120

110

120

110

120

150 )160

150

160

150

160

1(:iq .... 170

160

170

160

170

130

140

130

140

150

140

150

140

150

-

35

35

35

35

35

-

READ

60

-

50

50

60

50

60

130

-

120 :::::::::::130::::·

120

130

120

130

READ

40

30/ ::<::..40·

30

40

30

40

WRITE (4)

120

READ

160

-

WRITE (4)

170

-

READ

140

-

······130

140

WRITE (4)

150

-

140

35

j<

71281/2S70
71281/2L70

110

li~

60

60
130
40
120

170

L

'I.g'>

-

mA

140
150

35
mA

1

. ~g• • • • •• • •:• • • • i·

mA

160

k·::

20/:/

UNIT

COM'L MIL COM'L MIL

WRITE (4)

:::::::::}

CS '

MIN.

(>MAX.

71281/2S70 (2)
71281/2S45
71281/2S55
71281/2L70 (2)
71281/2L45
71281/2L55
MIN.
MAX. MIN.
MAX. MIN •
MAX.

UNIT

.•'}• > <• .

READ CYCLE

-

45

-

35

45

35

-

5

-

5

25

<~~>

55

-

70

-

ns

55

-

70

ns

45

-

55

-

70

ns

5

-

5

-

5

-

ns

15

-

20

-

25

-

30

ns

-

5

5

-

5

-

ns

0

-

0

-

0

-

0

-

ns

-

35

-

45

-

55

-

70

ns

t RC

Read Cycle Time

25

-

tM

Address Access Time

25./

t ACS

Chip Select Access Time (3)

-

30>, 1<:....

tCLZ

Chip Select to Output in Low Z (4)

5

L>

tCHZ

Chip Select to Output in High Z (4)

-

tOH

Output Hold from Address Change

5/-

t pu

Chip Select to Power Up Time (4)

d»

t pD

Chip Deselect to Power Down Time(4)

-

<7<>

.> . 1:f
.... :::.

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. Both chip selects must be active low for the device to be selected.
4. This parameter guaranteed but not tested.
5. Preliminary data for military devices only.

4-147

IDT71281/IDT71282 CMOS STATIC RAMS 256K (64Kx 4-BIT)

TIMING WAVEFORM OF READ CYCLE NO.

ADDRE$

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1(1)

~14----

~(

tAC

~~~~~~~~~~~~~~~--tAA-----------------·-I--------------· ~-t-O-H-----------

~-----

t ACS

------~

14----- tc~(4)-__~

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.

2(1,2)

~~~-----------

ADDRESS
DATA OUT

~=: _

t RC

------------~~

-=_t:=OH:=~ t~_A _-=~ =~ =~': ~.-XJ---·-'~_-=~_-=~_-=~l= = = t=OH= j=~:= = =

-==== -==::_-==::_-==::_-==::_

TIMING WAVEFORM OF READ CYCLE NO.

...

3(1,3)

14------ t ACS - - - - -....

DATA OUT
Vee Icc

c3~~~~t

ISB

NOTES:

1. wr=. is High for Read Cycle.
2. Device is continuously selected. CS = V,L.
3. Address valid prior to or coincident with cg transition low.
4. Transition is measured ±200mV from steady state.

4-148

___

MILITARY AND COMMERCIAL TEMPERATURE RANGES

iDT71281/IDT71282 CMOS STATIC RAM 256K (64K X 4-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vee = 5V ±100/0, All Temperature Ranges)

71281/2S25 (1)
71281/2L25 (1)
MAX.
MIN.

PARAMETER

71281/2S35(7)
71281/2L35(7)
MIN.
MAX.

71281/2S70 (2)
71281/2S45
71281/2S55
71281/2L70(2)
71281/2L45
71281/2L55
MIN.
MAX. MIN.
MAX. MIN.
MAX.

UNIT

WRITE CYCLE

-

20

twe

Write Cycle Time

tew

Chip Select to End of Write

tAw

Address Valid to End of Write

20

t AS

Address Set-up Time

0

twp

Write Pulse Width

20.

tWR

Write Recovery Time

0

tWHZ

Write Enable to Output in High Z (4. 6)

-

tDW

Data Valid to End of Write

15

tDH

Data Hold Time

0.

(3)

20

-

40

30

.. ·2:.::.

40

30

-

40

-

50

-

60

50

60

-

50

50.
0

-

-

ns

ns

0

-

ns

60

ns
ns

0<> 30.··
-

_ ... I••...• 0.

40.

-

0

-

.1:fL 1-

15

-

20

-

25

-

30.

-

25

-

30.

-

35

-

ns

0.

0

-

ns

5

-

35

-

40

45

ns

35

-

40

-

45

ns

..... .::::<,:

\

30

.. -

20.
0.

0

0

tow

Output Active from End of Write (4. 6)

5}<·

-

5

-

5

t ly

Data Valid to Output Valid (4. 5)

i.(

20

30

twv

Write Enable to Output Valid (4. 5)

-

20

-

-

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. Both chip selects must be active low for the device to be selected.
4. This parameter guaranteed but not tested.
5. For IDT71281S/L only.
6. For IDT71282S/L only.
7. Preliminary data for military devices only.

4-149

30

0

0
60

5

ns

ns

ns

IDT71281/IDT71282 CMOS STATIC RAMS 256K (64K x 4-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)(1,2,3)
twc
ADDRESS

~
----./
~

<

)(
tCHZ (5l

,

tAW

/~

-tAS

twp

-

tWR

""',

/~

f-i-- tWHZ (5,6)_

DATA UNDEFINED

DATAour(6)

OW

(2)

"

If

If

,

.......

)-

twy

I

DATAour(7)

t

)(

DATA UNDEFINED
t

________________________________
DATA IN

DATA VALID

~~-tD-W-----.-I.----t-DH-~~--___________
.(7).

TIMING WAVEFORM OF WRITE CYCLE NO.2, (CS CONTROLLEDTIMING)(1,2,3,4)

twc
ADDRESS

~

--./

)K

K
tAW

~tAS

'1

)~
tWR

tew

,,-----------------------t~
_________________
-ICt .;~
I

~

tow

to"

1""-------

NOTES:
1. wrc or ~ must be high during all address transitions.
2. A write occurs during the overlap (tcw or twp ) of a low ~. and a low wrc.
3. t WR is measured from the earlier of ~ or wrc going high to the end of the write cycle.
4. If the CS low transition occurs simultaneously with or after the wrclow transition, the outputs remain in the high impedance state (IDT71282 only).
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
6. IDT71282 only.
7. IDT71281 only.

4-150

IDT71281/IDT71282 CMOS STATIC RAM 256K (64K x 4-BI1)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

TRUTH TABLE
MODE

CS

WE

OUTPUT

POWER

Standby

H

X

HighZ

Standby

Read

L

H

DOUT

Active

Write (1)

L

L

DIN

Active

Write (2)

L

L

HighZ

Active

SYMBOL

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CIN

Input Capacitance

COUT

Output Capacitance

CONDITIONS

MAX.

'-IN = OV

11

pF

VOUT= OV

11

pF

NOTE:
1. This parameter is determined by device characterization but is not
production tested.
.

NOTES:
1. For IDT71281 only.
2. For IDT71282 only.

ORDERING INFORMATION'
lOT

xxxxx

999

A

A

Device Type

Speed

Package

Process!
Temperature
Range

y:rank

~------------------------------~l C
25
35
~--------------------~ 45
55
70
~

UNIT

____________________________

~I

S

I L

'-------________________________________________________________________________________--11

71281

1 71282

4-151

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STO-883, Class B
Sidebraze DIP
Commercial Only }
Speed in Nanoseconds
Military Only
Standard Power
Low Power
256K (64K x 4-Bit)
256K (64K x 4-Bit) High Impedance Outputs

FEATURES:

DESCRIPTION:

• High-density 256K (64K x 4) CMOS static RAM module
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
• Available in 28-pin SIP (single In-line package) for maximum
space saving
• Fast access times: 25ns (max.) over commercial temperature
• Low power consumption
- Dynamic: less than 1.2W (typ.)
- Full standby: less than 30 mW(typ.)
• Utilizes ID17187 high-performance 64K static RAMs produced
with advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible

The ID17MP456 Is a 256K (64K x 4-bit) high-speed static RAM
module constructed on an epoxy laminate surface using four
ID17187 64K x 1 static RAMs In plastic surface mount packages.
Extremely fast speeds can be achieved with this technique due to
the use of 64K static RAMs fabricated in IDT's high-performance,
high-reliability CEMOS technology.
The 7MP family of surface mounted SIP technology is a costeffective solution all0":t.,n~ . ",for very high packing density. The
ID17MP456 is offered "tn'la'~8-pin SIP. The ID17MP456 can be
mounted on 200 mil ~ters::l'yielding 1.25 megabits of memory in
less than 3 square inche$ of board space.
The ID17MP456Is available with maximum access times as fast
as 25ns, with I!)aiimflm power consumption of 3.3 watts. The module also Ofl'~'~·fuU standby mode of 440mW(max.).
All inpuiS' an~O'LJtputs ofthe IDTMP456 are TTL-compatible and
operate::f~bQ1a::"Single 5V supply. Fully asynchronous circuitry is
usedr(equiring no clocks or refreshing for operation and providing
equal:~cces~ and cycle times for ease of use.
,.\\~:'~'~:;:~~~

1
"1'1 :<::;,;'1

PIN CONFIGURATION
Vcc
A4
Al
A7
DATAoUTo
DATA INO
A5
A2
A12
A6
A10
DAiAoUTl
DATAINl

Ao
A13
Ag

DATA INPUT

cr
10
11
12
13
14
15
16

As

17

16
19

WE

20

STATIC RAM

M11(1)
DATA OUTPUT

21

A3

22

All

23
24
25

DATAOUT3
DATA IN3
GND
A14
A15

64Kx4 CMOS

WE

DATAOUT2
DATAIN2

cr

4

{f:::;~;:::::;::\
16
\\:~:~~PRESS ----'-'+---1

PIN NAMES

cr

Address Inputs
Chip Enable

WE

Write Enable

~NO - DIN3
DoUTo - DOUT3

Data Input
Data Output
Power

Ao-A'5

26

27
26
SIP
SIDE VIEW

NOTE:
1. For module dimensions. please refer to module drawing M11 in the packaging section.

Vee
GND

Ground

CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
© '987 Inlegrated DevIce Technology. Inc.

DECEMBER 1987
4-152

OSC-70071-

FEATURES:

DESCRIPTION:

• High-speed address/chip select time

The 10171256 is a 262,144-bit high-speed .static RAM organized as 32K x 8.lt is fabricated using lOT's high-performance, highreliability CEMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective alternative to bipolar and fast NMOS memories.
Address access times as fast as 35ns are available with power
consumption of only 300mW (typ.).-1!:le circuit also offers a reduced power standby mode. When CS goes high, the circuit will
automatically go to, and remain in, a low-power standby mode as
long as CS remains high. In the full standby mode, the low-power
device consumes less than 151lW, typically. This capability provides significant system level power and cooling savings. The lowpower (L) version also offers a battery backup data retention
capability where the circuit typically consumes only 51lW when
operating off a 2V battery.
All inputs and outputs ofthe 10171256 are TTL-compatible and
operation is from a single 5V supply, simplifying system designs.
Fully static asynchronous circuitry is used, requiring no clocks or
refreshing for operation, providing equal access and cycle times
for ease of use.
The 10171256 is packaged in a 28-pin SOIC, a 28-pin 600 mil
CEROIP or plastic DIP and 32-pin leadless chip carrier and PLCC,
providing high board-level packing densities.
The 10T71256 military RAM is manufactured in compliance with
the latest revision of MIL-STO-883, Class B, making it ideally suited
to military temperature applications demanding the highest level of
performance and reliability.

~

Military: 45/55/70/85ns (max.)
- Commercial: 35/45/55/70ns (max.)

• Low-power operation
- 10171256S
Active: 300mW (typ.)
Standby: 200IlW (typ.)
- ID171256L
Active: 250mW (typ.)
Standby: 151lW (typ.)
• Battery Backup operation-2V data retention
• Produced with advanced high-performance CEMOS ™
technology
• Single 5V(±10%) power supply
• Input and output directly TTL-compatible
• Static operation: no clocks or refresh required
• Available in standard 28-pin CEROIP and plastic OIP (600 mil),
28-pin SOIC and 32-pin LCC and PLCC
• Military product compliant to MIL-STD-883, Class B
• Standard Military Orawing# 5962-88552 is pending listing on
this function. Refer to Section 2/pa'ge 2-4.

FUNCTIONAL BLOCK DIAGRAM

. - 0 Vee
512 x 512
MEMORY ARRAY

ROW
DECODER

1/0 1

. - 0 GND

COLUMN I/O

INPUT
DATA
CIRCUIT

COLUMN DECODER

1/06

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

4-153

DECEMBER 1987
DSC-1015/-

III
~

IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K X 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

81 w·-

... N
- "
- U

C')

«3<

INDEX

UULlUUULl

Aa
A5
A4
A3
A2
AI
Ao
NC

1/0 1

:1
:1
:1
:1
:1
:1
J
:1
J

DIP/SOIC
TOP VIEW

4
5

3 2

1

32 31 30
29[

r:
27 r:
26 r:
2a

a
7
a

J32-1

&

9

L32-1

10
11

A8
Ag
All
NC

rn:
A10

CS

12

I/0 a

13

1/0 7

N

C')

C U

..

It)

..

QQzzQQQ
--(!I
--LCC/PLCC
TOP VIEW

PIN NAMES

LOGIC SYMBOL

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

Addresses

1/01-I/Oa

Data Input/Output

~

Chip Select

WE

Write Enable

OE

Output Enable

GND

Ground

Vee

Power

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

(1)

COMMERCIAL

Ao - A14

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TalAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

MIN.

TYP.

MAX.

UNIT

PT

Power Dissipation

1.0

1.0

W

Vee

Supply Voltage

4.5

5.0

5.5

V

lOUT

DC Output Current

50

50

mA

GND

Supply Voltage

0

0

0

V

V1H

Input High Voltage

2.2

-

6.0

V

V1L

Input Low Voltage

-0.5(1)

-

0.8

V

GRADE
Military
Commercial

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND
OV

5.0V

O°Cto +70°C

OV

5.0V

Vee

± 10%
± 10%

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

PARAMETER

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 2Ons.

4-154

IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

VCC = 5.0V +10%,
VlC = O.'ZoJ, VHC = Vcc -0.'ZoJ
IDT71256S
MIN.
MAX.

IDT71256L
MIN.
MAX.

TEST CONDITIONS

-

10

-

5

5

-

2

10

-

5

5

-

2

0.4

-

0.4

V

10l = 10mA, Vcc = Min.

-

0.5

-

0.5

V

IOH = -4mA, Vcc = Min.

2.4

-

2.4

-

V

Vcc = Max.; VIN = GND to Vcc

Ilul

Input Leakage Current

Illol

Output Leakage Current

. VOL-

Output Low Voltage

VOH

Output High Voltage

UNIT

MIL
COM'L

Vee = Max.

MIL

CS = VIH ' VOUT = GND to Vcc

COM'L

10l = SmA,

\to =

Min.

J.1.A
J.1.A
J.1.A
J.1.A

DC ELECTRICAL CHARACTERISTICS(1,3) VCC =
SYMBOL

ICCI

ICC2

IS6

IS61

PARAMETER
Operating Power
Supply Current
CS = Vll,
Outputs Open,
Vcc = Max., f = 0
Dynamic Operating
Current
CS = Vll,
Outputs Open,
Vcc = Max., f = f MAX (4)
Standby Power
Supply Current
(TTL Level)
CS ~ VIH ,f = fMAX(4)
Vcc= Max.,
Outputs Open.
Full Standby Power
Supply Current
(CMOS Level)
CS ~ VHC , f = 0
Vcc= Max.

POWER

S

L

S

L

S

FUNCTION

5V±10%, VlC == 0.2V, VHC = Vcc -0.2V
IDT71256x35 IDT71256x45 IDT71256x55

COM'L MIL

COM'L MIL

IDT71256x70

IDT71256x85

COM'L MIL COM'L MIL COM'L MIL

READ

30

-

30

40

30

40

30

40

-

40

WRITE (2)

90

-

90

100

90

100

90

100

-

100

READ

15

15

20

15

20

15

20

-

20

WRITE (2)

SO

READ

155

WRITE (2)

150

READ

135

WRITE (2)

130

-

20

-

UNIT

mA

SO

90

80

90

80

90

-

90

140

150

140

150

140

150

-

150

140

150

140

150

140

150

-

150

110

120

90

100

75

85

70

115

125

105

115

95

105

-

20

20

20

20

20

20

-

20

mA

90

mA
L

3

-

3

3

S

15

-

15

20

L

0.4

-

0.4

1.5

3

3

3

-

3

' 15

20

15

20

-

20

0.4

1.5

0.4

1.5

-

1.5

3

mA

NOTES:
1. All values are maximum guaranteed values.
2. Write cycle current specifications are Included to aid in the design of extremely sensitive applications. It should be noted that in most systems the ratio of
Read cycles to Write cycles is extremely high. When calculating total current consumption, the designer should weight these figures by the percentage of
·On" time as well as the anticipated ratio of Read to Write cycles (usually greater than 90%).
3. ·x" in part numbers indicates power rating (S or L).
4.

fMAX = 1/tRC

4-155

IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K X 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = O.2V, VHC
SYMBOL
VDR

0.2V

PARAMETER

TEST CONDITION

MIN.

-

2.0

Vcc for Data Retention

ICCDR
t

= Vee -

Data Retention Current
CS ~VHC

CDR

t R(3)

(3)

I

MIL
COM'L.

-

0

Chip Deselect to Data Retention Time

t RC (2)

Operation Recovery Time

TYP.(1)
Vee @
2.0V
3.0V

-

-

-

-

-

-

-

NOTES:
1. TA = +25°C
2. t RC = Read Cycle Time
3. This parameter Is guaranteed but not tested.

LOW Vee DATA RETENTION WAVEFORM

DATA RETENTION MODE
Vee

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
Sns
1.5V
1.SV
See Figures 1 and 2

5V

DATAoUT

~

2550

5V

4800
DATA OUT

~

2550

30pF*

.

4800
5pF'

Figure 2. Output Load
(for tOLZ.toLZ. t OHZ'
tWHZ' t OHZ ' tow)

Figure 1. Output Load

* Including scope and jig.

4-156

MAX.
Vee@
3.0V
2.0V

-

-

500

800

120

200

-

-

UNIT
V

J.lA
ns
ns

IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc = 5V+
- 10%, All Temperature Ranges)

I DT71256S35 (1) 1DT71256S45
IDT71256L35 (1) IDT71256L45
MAX. MIN.
MAX.
MIN.

PARAMETER

IDT71256S55
IDT71256S70 I DT71256S85 (2)
IDT71256L55
IDT71256L70 IDT71256L85 (2)
MAX.
MIN.
MIN.
MAX. MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

35

-

45

-

55

-

70

-

85

-

tAA

Address Access Time

-

35

45

-

70

-

85

ns

Chip Select Access Time

-

35

-

55

t ACS

-

55

-

70

-

85

ns

45

ns

tClZ

Chip Select to Output in Low Z (3)

5

-

5

-

5

-

5

-

5

-

ns

tOE

Output Enable to Output Valid

-

15

-

20

-

25

-

30

-

35

ns

tOll

Output Enable to Output in Low

Z (3)

0

-

0

-

0

-

0

-

0

-

ns

tCHZ

Chip Deselect to Output in High

Z(3)

-

15

20

-

30

-

35

ns

Output Disable to Output in High

-

15

20

-

25

tOHZ

-

25

-

30

-

35

ns

5

-

5

-

5

-

5

-

5

-

ns

Z(3)

Output Hold from Address Change
tOH
NOTES:
1. O°C to + 70°C temperature range orily.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed, but not tested.

4-157

IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1

ADDRESS

~

(1)

.'

tAA

tOH -

)t'

~:'Io..

~

tOE
-

t OHZ (5)

tOLZ(5)

'~

t CHZ (5)

t ACS
tCLZ (5)
DATA OUT

~

~

~"

~

TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)

~~~----------------. ADDRESS

__
DATA OUT

t

RC

--------------------~~

:'.:_t-~=~=~=~=~= = = = = =~:t=O-H=~=_t~A :~= = = = = = = :-W~:.I:

TIMING WAVEFORM OF READ CYCLE NO.3

. . .-•-.••••-•-.•• -•-!
•.••.

-,- - - - -

(1,3,4)

DATA OUT

NOTES:

1. WE is High for Read Cycle.
2. Device is continuously selected. cs = V,L.
3. Address valid prior to or coincident with CS transition low.
4. OE = V,L
5. Transition is measured ±200mV from steady state with 5pF load (including scope and jig).

4-158

:0"

1---

'IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32Kx S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(VCC = 5V±10%. All Temperature Ranges)

I DT71256S35 (1) IDT71256S45
IDT71256L35 (1) IDT71256L45
MIN.
MAX. MIN.
MAX.

1DT71256S55
IDT71256S70 IDT71256SS5 (2)
IDT71256L55
IDT71256L7O IDT71256LS5 (2)
MIN.
MAX.
MAX. MIN.
MAX. MIN.

UNIT

WRITE CYCLE

60

40

-

0

-

20

-

-

25

twc

Write Cycle Time

35

-

45

-

55

tew

Chip Select to End of Write

30

-

40

50

tAW

Address Valid to End of Write

30

40

t AS

Address Set-up Time

0

twp

Write Pulse Width

30

-

35

tWR

Write Recovery Time

0

-

0

-

tWHZ

Write to Output in High Z(3)

-

15

-

tow

Data to Write Time Overlap

15

20

5

tOH

Data Hold from Write Time

3

-

tow

Output Active from End of Write(3)

5

-

0

3

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed. but not tested.

4-159

70

-

85

-

ns

60

70

-

ns

70

-

ns

0

-

0

-

ns

25

-

30

-

35

ns

30

-

ns

3

-

ns

5

-

5

-

35

3

-

5

-

ns

50
0

0
45

3

0
50

ns

ns

IDT71256S AND IDT71256L
CMOS STATIC RAM 256K (32Kx S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, (WE CONTROLLED TIMING)

(1,2,3,5,7)

twc
ADDRESS

~

----./

K

K

X

tAW
~

t

OHZ

(6)-

~V

~
t

I - - - t AS

(7)

tWR

WP

~V

"'i'..

-

r-- t WHZ( 6 ) _
tow
(4)

DATA OUT

-';)

f 4 - - t ow

(4).?~-

t OH -

,

"'-

.......

./

TIMING WAVEFORM ·OF WRITE CYCLE NO.2, (WE CONTROLLED TIMING)

(1,2,3,5)

twc
ADDRESS

~
~

)K

K
tAW

~tAS

1
I

/'V
t

CW

(7)

tWR

j;::.tOW
DATA IN

I"

tOH

"'1

NOTES:
1.
2.
3.
4.
5.
6.
7.

WE must be high during all address transitions.
A write occurs during the overlap (tcw or twp ) of a low ~ and a low WE.
t WR is measured from the earlier of ~ or WE going high to the end of the write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in the high impedance state.
Transition is measured ±200 mV from steady state with a 5pF load (including scope and jig).
If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or (twz + t ow) to allow the I/O drivers to tum off and
data to be placed on the bus for the required tow If C5E"is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified t wp .

4-160

IOT71256S AND IDT71256L
CMOS STATIC RAM 256K (32K x 8-BIT)

CAPACITANCE
SYMBOL
C1N ·

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(TA= +25°C. f = 1.0MHz)

PARAMETER(l)
Input Capacitance

CONDITIONS

MAX.

V1N = OV

UNIT

pF
Cour
Output Capacitance
Vour= OV
11
pF
NOTE:
1. This parameter is determined by device characterization but is not
production tested.

TRUTH TABLE

11

VlC = 0.2V. VHC =Vcc-0.2V

WE

CS

OE

1/0

X

H

X

Hi-Z

X

VHC

X

Hi-Z

Standby (lSB1)

H

L

H

Hi-Z

Output Disable

FUNCTION
Standby (Isa>

H

L

L

DATA OUT

Read

L

L

X

DATAIN

Write

NOTE:
1. H = \IH' L = V1l• X = DON'T CARE

ORDERING INFORMATION
IDT

XXXX

A

999

A

A

Device Type

Power

Speed

Package

Process/
Temperature
Range

y:""k
P

D
~--------------~ SO
J
L
35
45
~----------------------~ 55
70
85
~

______________________

~I

L

IS
~--------------------------------------~ 71256

4-161

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
Plastic DIP
CERDIP
Small Outline IC
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Commercial onlY}
Speed in Nanoseconds
Military Only
Low Power
Standard Power
256K (32K x 8-Bit) Static RAM

FEATURES:

DESCRIPTION:

• High-density 256K (32K x 8-bit) CMOS static RAM module
• Equivalent to JEDEC standard for future monolithic 32K x 8
static RAMs
•
•
•
•
•
•
•
•
•
•
•

The IDT8M856 is a 256K (32,768 x 8-bit) high-speed static RAM
constructed on a co-fired ceramic substrate using four IDT7164
(8,192 x 8) static RAMs in lead less chip carriers. Functional equivalence to proposed monolithic 256K static RAMs is achieved by
High-speed-45ns (max.) commercial; 55ns (max.) military
utilization of an on-board decoder circuit that interprets the higher
Low power consumption; typically less than 225mW operating,
order address A13 and A14 to select one of the four 8K x 8 RAMs.
less than 500~W in full standby
Extremely fast speeds can be achieved with this technique due to
Utilizes IDT7164s-hlgh-performance 64K static RAMs
use of 64K static RAMs,ahdthe decoder fabricated in IDT's highproduced with advanced CEMOS ™ technology
performance, high-reliability"CEMOS technology.
'
, The IDT8M856 Is available with maximum access times as fast
CEMOS process virtually eliminates alpha particle soft error
" ' ,
rates (with no organic die coating)
as 45ns for com!:!lercialand 55ns for military temperature ranges,
with maximumpqwer consumption of only 825mW. The circuit
Assembled with I DT's high-reliability vapor phase solder reflow
also offers a'sOpstantially low-power standby mode. When CS
process
goes high, the,circ.uit will automatically go to a standby mode with
Pin-compatible with IDT7M864 (8K x 8 SRAM module)
power co~sumpti6n of only 83mW (max.).
Offered In the JEDEC standard 28-pin, 600 mil wide ceramic
The,U?T8M856 is offered in a 28-pin, 600 mil center sidebraze
sidebraze DIP
DIP:~is provides four times the density of the IDT7M864 (8K x 8
m~u'e)!n'''the same socket, with only minor pin assignment
Single 5V (t10%) power supply
~hanges>"ln addition, the JEDEC standard for 256K monolithic
Inputs and outputs directly TTL-compatible",,,, PiQ()l,!ts has been adhered to, allowing for compatibility with 256K
Modules available with semiconductor components compliant <' ::\,,~~nblithiCS.
to MI L-STD-883, Class B " " "
,r",'AII inputs and outputs of the IDT8M856 are TTL-compatible and
Finished modules tested at Room, Hot and Cold temperature~,>oPerate from a single 5V supply. Fully asynchronous circuitry is
for all AC and DC parameters
"r'
),} used, requiring no clocks or refreshing for operation, and providing
l';,:.,:l"
equal access and cycle times for ease of use.
All IDT military module semiconductor components are manufactured in compliance with the latest revision of MIL-STD-883,
Class B, making them ideally suited to applications demanding the
highest level of performance and reliability.

PIN CONFIGURATION

i=UNCTIONAL BLOCK DIAGRAM
o\ ,1" ':;~:
,.H\,·':

,,/l'!\", 1\

li..\!I~."

',/,!,

"'~ -A

12

1/0 1 -1/0 8
~
A2

8

Al

9

-

-''-

OE:

'-I.-

~

Ao

1/0 1 11
1/02
1/03

-

~

IDT7164
8Kx8
CMOS
STATIC
RAM

IDT7164
8Kx8
CMOS
STATIC
RAM

CS (
l

....... IDT7164
8Kx8
CMOS
~ STATIC
RAM
'---

~

r--IDT7164
,. 8Kx8
~ CMOS
~ STATIC
RAM
.......,~

CS l

CS?

DECODER ~

GND
DIP
TOP VIEW

---c
PIN NAMES
Ao - A14
1/01-1/08

NOTE:
* For module dimensions, please refer to module
drawing M1 in the packaging section.

CS

CEMOS is a trademark of Integrated Device Technology, Inc.

Vee

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc,

Addresses
Data Input/Output
Chip Select
Power

WE

DE
GND

Write Enable
Output Enable
Ground

DECEMBER 1987
D8C-7020/-

4-162

DESCRIPTION:

FEATURES:
• High-density 256K-bit CMOS static RAM module
• Customer-configured to 16Kx16, 32Kx8 or 64Kx4
• Fast access times
- Military: 20ns
- Commercial: 15ns
• Low power consumption

•
•
•
•
•
•
•
•

The ID17M656 is a 256K-bit high-speed CMOS static RAM constructed on a multilayered ceramic substrate using 16 IDT6167
(16Kx1) static RAMs in leadless chip carriers. Making 4 chip select
lines available (one for each group of 4 RAMs) allows the user to
configure the memory into a 16Kx16, 32Kx8 or 64Kx4 organization.
In addition, extremely high speeds'are achievable by the use of
IDT6167s fabricated in ,I",D,,T'S high-performance, high-reliability
technology, CEMOS. This state-of-the-art technology, combined
with innovative circuit design techniques, provides some of the
- Active: 3.2mW (typ.) (in 16K x 16 organization)
- Standby: 0.16mW (typ.)
fastest 16K static RAMs $vaiJable.
Utilizes 16 IDT6167shigh-performance 16K x 1 CMOS static
The ID17M656 is a\tailabla'with access times as fast as 15ns
RAMs produced with IDT's advanced CEMOS 1M technology
commercial and 20ns'i Jlitary temperature range, with maximum
CEMOS process virtually eliminates alpha particle soft error
operating power;,~nsumption of only 7.9W (significantly less if
rates (with no organic die coating)
organized 321S~~:::~t:~J)4Kx4). The RAM module also offers a
Assembled with IDT's high-reliability vapor phase solder reflow
maximum ~tCl8~I:iiJ)6wer mode of 3.0W and a maximum full
process
standby mppeqf~ 176mW.
Offered in 40-pin, 900 mil center sidebraze DIP, achieving very
The IQV~?5,g'iS offered in a hlgh-density 40-pin, 900 mil center
sideb~~eQ'~to take full advantage of the compact IDT6167s in
high memory density
leadl,~s~"9~iP~carriers.
Single 5V (± 10%) power S U P P I Y , . ; P . l t ' i n , p D t s and outputs ofthe'ID17M656 are TIJ_-compatible and
Dual Vee and GND pins for maximum noise immunity
o~ratl3/rom a single 5V supply. (NOTE: Both vc& pins need to be
Inputs and outputs directly TTL-compatible
;;~(;c,9nneCted to the 5V supply and both GND pins need to be
.
.
.
.
5,~r()pnded for proper operation.) Fully asynchronous circuitry is
Module available with semiconductor components compllant~;p"'::"',,:,:~d requiring no clocks or refreshing for operation, and providing
1;;,;;;,;i,,""t:equal access and cycle times for ease of use.
to MIL-STD-883, Class B.
,::,:~:,,;;.,} All IDT military module semiconductor components are manufactured in compliance with the latest revision of MIL-STD-883,
Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

m

PIN CONFIGURATION

""FUNCTIONAL BLOCK DIAGRAM
AO-AI3----~-4~--------~--------~~-------,

*GND

WE"-TOP----hr~--------~------~H--------,
CSO_3----++~r_------~+_------~H_------_,

D15
CS(12-1S)
D4

WE"(BOT)
Al
D14

A2
Ds
A3
A4
D 13

WE'-BOT--~~~======~======~======~

As
De
As

CS8_11----t+-~r-------~+--------H--------,

WE'(TOP)
D12

CS(4-7)

D7
*Vee
DIP
TOP VIEW

1. For module dimensions, please refer to module drawing M5 in the
packaging section.

PIN NAMES
Axx
CSxx

WE"xx

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

Addresses
Chip Selects
Write Enable

Dxx
Vee
GND

DATAIN/OUT
Power
Ground

DECEMBER 1987
4-163

DSC-7012/-

UI
~

DESCRIPTION:

FEATURES:
"-

The IDTBMP656S/IDT8MP62BS are 256K/12BK-bit high-speed
CMOS static RAMs constructed on an epoxy laminate substrate
using four IDT7164 BK x B static RAMs (IDT8MP656S) or two
IDT7164 static RAMs (IDT8MP62BS) in plastic surface mount
packages.
Functional equivalence to proposed monolithic static RAMs is
achieved by utilization of an on-board decoder that interprets the
higher order address A13 to Select one of the two BK x 16 RAMs as
the by-16 output and u~ing'~13:i and UB as two extra chip select
functions for lower byt,e:(lfO;:a) and upper byte (1/09-16) control,
respectively. (On the IDT8MP62BS 8K x 16 option, A 13 needs to be
externally groundeafor proper operation.) Extremely high speeds
are achievable bY;1he).Jse of IDT7164s. fabricated in IDT's high~
performancei"l1igt1~reliability CEMOS technology. This state-ofthe-art teChr;tOlogy, combined with innovative circuit design techniques, p~Qllide~lhe fastest 256K/12BK static RAMs available.
Theilf)T8~~1,P656S/IDTBMP62BS are available with maximum
oper~~ing p()wer consumption of only 1.BW {IDT8MP656S 16K x 16
optlO'n).,The modules also offer a full standby mode of 330mW

• High-density 256K/12BK CMOS static RAM modules
• 16K x 16 organization (IDTBMP656S) with BK x 16 option
(IDTBMP62B)
• Upper byte (1/09-16) and, lower byte (1/01-8) separated control
- Flexibility in application
• Fast access times
- 40ns (max.)
• Low power consumption
- Active: less than B25mW (typ. in 16K x 16 organization)
- Standby: less than 20mW (typ.)
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
• Offered in an SIP (single in-line) package for maximum
space-savings
• Utilizes IDT7164s-high-performance 64K static RAMs
produced with advanced CEMOS ™ technology

(mex:).:;:r

,i'::'!"",i"The' IDTBMP656S/IDTBMP62BS are offered in a

• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)

40-pin plastic

,,:"::;,.~I~i'For the JEDEC standard 40-pin DIP, refer to the IDTBM656S/

;' IDTBM62BS.
All inputs and outputs of the IDTBMP656S/IDTBMP62BS are
'". TTL-compatible and operate from a single 5V supply. (NOTE: Both
GND pins need to be grounded for proper operation.) Fullyasynchronous circuitry is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of
use.

!> :(,;'/)'

• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible

FUNCTIONAL BLOCK DIAGRAM

:'i?~~J

",li;'·(';:,.",:"
,<,,'.,

'7-;i;:

,i.\;\;
1109-16

'''',

"'"

"'"''

r1;;:

f)'"''

WE
'---

A 13
CS

HI

1/2 FCT139 ~
DECODER I'-'

IDT7164
8Kx8
CMOS
STATIC
RAM
~

IDT7164
8Kx8
CMOS
STATIC
RAM
(

'--

IDT7164
8Kx8
CMOS
STATIC
RAM

IDT7164
8Kx8
CMOS
STATIC
RAM

c;>

~

Y

~

t:

1/2 FCT139
DECODER I'-'

Y

CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
© 1987 Integrated DevIce Technology, Inc. '

DECEMBER 1987

4-164

OSC-7016/-

DESCRIPTION:

FEATURES:

The IDT8M656S/IDT8M628S are 256K1128K-bit high-speed
CMOS static RAMs constructed on a multi-layered ceramic substrate using four IDT7164 8K x 8 static RAMs (IDT8M656S) or two
IDT7164 static RAMs (IDT8M628S) in leadless chip carriers.
• Upper byte (1/09-16) and lower byte (1101-8) separated control
Functional equivalence to proposed monolithic static RAMs is
achieved by utilization of an on-board decoder that interprets t h e 9 1
- Flexibility in application
higher
order address A13 to select one.£f.the two 8K x 16 RAMs as ~
• Equivalent to JEDEC standard for future monolithic
the by-16 output and using LB and UB as two extra chip select
16K x 16/8K x 16 static RAMs
functions for lower byte ,0/91-8) and upper byte (1/09-16) control,
• High-speed
respectively. (On the IDt8M6~8S 8K x 16 option, A13 needs to be
- Military: 50ns (max.)
externally grounded fo/proper operation.) Extremely high speeds
are achievable by the u~,of IDT7164s fabricated in IDT's high- Commercial: 40ns (max.)
performance, higttreliability CEMOS technology. This state-of• Low power consumption: typically less than 825mW
the-art technolpgy.,;,~;!11bined with innovative circuit design techoperating (IDT8M656), less than 40mW in standby
niques, pro\,ige~tv~ fastest 256K/128K static RAMs available.
• Utilizes IDT7164s-high-performance 64K static RAMs
The IDT8M6SGS/IDT8M628S are available with access times as
fast as 490S'2V~( the commercial temperature range, with maxiproduced with advanced CEMOS ™ technology
mumOpera!iQg"power consumption of only 1.98W (IDT8M656S
• CEMOS process virtually eliminates alpha particle soft error
16K)!>1~pptton). The module also offers a full standby mode of
rates (with no organic die coating)
449mW (max.).
• Assembled with IDT's high-reliability vapor phase solder
;):rhe'~!!DT8M656S/IDT8M628S are offered in a high-density
reflow process
,<49~Piot600 mil center sidebraze DIP to take full advantage of the
• Offered in the JEDEC standard 40-pin, 600 mil wide ceramic
":',90'?,,,pact IDT7164s in lead less chip carriers.
sidebraze DIP
';;';¥~i",,::'jAII inputs and outputs of the IDT8M656S/IDT8M628S are TTL\~;;:;;;>':}90mpatible and operate from a single 5V supply. (NOTE: Both V CC
• Single 5V (±10%) power supply
,i';";:.'pins need to be connected to the 5V supply and both GND pins
• Inputs and outputs directly TTL-compatible
need to be grounded for proper operation.) Fully asynchronous
• Modules available with semiconductor components
circuitry is used, requiring no clocks or refreshing for operation,
,'}
compliant to MIL-STD-883, Class B
and providing equal access and cycle times for ease of use.
AIIIDT military module semiconductor components are manu• Finished modules tested at Room, Hot and Cold temp'~~ii~",
factured in compliance with the latest revision of MIL-STD-883,
tures for all AC and DC parameters
/"""
"
/~.:{" .. \~.\\
Class B, making them ideally suited to applications demanding the
~·':;·:i;2\~t
highest level of performance and reliability.
'
• High-density 256K1128K-bit CMOS static RAM modules

• 16K x 16 organization (IDT8M656) with 8K x 16 option
(IDT8M628)

FUNCTIONAL' BLOCK DIAGRAM
;;'..

\r

\\~,

A~~~~(
WE
OE-

'--

A13
CS
L8

IDT7164
8Kx8
CMOS
STATIC
RAM

H1/2 FCT139 ~
DECODER I'"

Y

)

IDT7164
8Kx8
CMOS
STATIC
RAM
{)

'"~

IDT7164
8KxB
CMOS
STATIC
RAM

IDT7164
8Kx8
CMOS
STATIC
RAM
()

~

Y
1/2 FCT139
DECODER

U8

t::-

1_

Y

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc,

4-165

DECEMBER 1987
OSC-7018/-

DESCRIPTION:

FEATURES:

The IDT7M812/IDT7M912 are 512K-bit high-speed CMOS
static RAMs constructed on a multi-layered ceramic substrate using 81DT71B7 64K x 1 static RAMs (IDT7M812) or9lDT71B7static
Fast access times
RAMs (IDT7M912) in leadless chip carriers. Extremely high speeds
are achievable by the use of IDT7187s fabricated in IDT's high- Military: 35ns (max.)
performance, high-reliability technology, CEMOS. This state-of- Commercial: 25ns (max.)
the-art technology, combined with Innovative circuit design teChLow power consumption
niques, provides the fastest 64K static RAMs available.
The IDT7M812/IDT7M912 are available with access times as
- Active: 2.4W (typ. in 64K x B organization)
fast as 2Sns commercial and 3Sns military temperature range, with
- Standby: 240~W (typ. in 64K x B organization)
maximum operating power'~onsumption of only 6.9W (IDT7M912,
Utilizes B (IDT7MB12) or 9 (IDT7M912) IDT71B7 high64K x 9 option). The mOdLilealso offers a standby power mode of
performance 64K x 1 CMOS static RAMs produced with IDT's
less than 3.2W (max.fand,a full standby mode of 1.2W (max.).
advanced CEMOS ™ technology
The IDT7MB12/IDT7M912 are offered in a high-density 40-pin,
CEMOS process virtually eliminates alpha particle soft error
600 mil center si<:ieoraze DIP to take full advantage of the compact
rates (with no organic die coating)
.
IDT7187s in leadle~s Chip carriers. The IDT7M912 (64K x 9) option
can provid~moi"~ flexibility in system application for error detecAssembled with IDT's high-reliability vapor phase solder
tion, paritybit;:~tc.
reflow process
AII,.inputsllnd outputs of the IDT7M812/IDT7M912 are TILAvailable in 40-pin, 600 mil center sidebraze DIP, achieving
c0rTlpatibl~ and operate from a single SV supply. (NOTE: Both Vee
very high memory density
.
phis needt'o be connected to the SV supply and both GND pins
Single 5V(±10%) power supply
,ree9. to,be grounded for proper operation.) Fully asynchronous cir,"'C;:: cuitr)lls used, requiring no clocks or refreshing for operation, and
Dual Vee and GND pins for maximum noise immunity
"".,providing access and cycles times for ease of use.
Inputs and outputs directly TIL-compatible
,\< ,.,.,. . . \,AIIIDT military module semiconductor components are compliModules available with semiconductor components,
,. iant to the latest revision of MIL-STD-883, Class B, making them
compliant to MIL-STD-BB3, Class B
":., ideally suited to applications demanding the highest level of
performance and reliability.
Finished modules tested at Room, Hot and Cold
t'
temperatures for all AC and DC parameters

• High-density 512K-bit CMOS static RAM module

• 64K x B (IDT7MB12) or 64K x 9 (IDT7M912) configuration
.•

•

•

•
•
•
•
•
•
•
•

"FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

-A 15 --..---<.------..---~J----_,

cs

~

--~+-~------~------~r_----,

PIN NAMES

DIP
TOP VIEW
NOTES:
1. Both Vee pins need to be connected to the 5V supply and both GND pins need to be grounded for proper
operation.
2. Pin 18 is Os and pin 23 is Ys in 64K x 9 (IDT7M912) option and both 18 and 23 are NC in 64K x 8
(IDT7M812) option.
3. For module dimensions. please refer to module drawing M4 in the packaging section,

Ao-AI5

Address

Do-Os

Data Input

Yo-ys

Data Output

CS

Chip Select

we.

Write Enable

Vec

Power

GND

Ground

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

19S7 Integrated DevIce Technology, Inc,

4-166

'------

-,

.----,~---

DECEMBER 1987
DSC-7013/-

FEATURES:

DESCRIPTION:

• High-density 32 bit word 512K (16K x 32) static RAM module
• Available in low profile 8S-pin sidebraze dual ceramic SIP
(single in-line package)

The ID17MC4032 is a 32-bit wide 512K (16K x 32) static RAM
module with separate I/O constructed on a co-fired ceramic substrate using eight 10171982 16K x 4 static RAMs in lead less chip
carriers. Extremely fast speeds can be achieved due to the use of
64K static RAMs fabricated in lOT's high-performance, high-reli-91
ability CEMOS ™ technology. The ID17MC4032 is available with ~
access time as fast as 30ns, with minimal power consumption.
The 7MC family of ceramic SIPs offers the optimum is packing
density and profile heig~t.,~Jhe 1017MC4032 is packaged in a
8S-pin dual ceramic 91P?Tt;i~:dual row configuration allows 88 pins
to be placed on a pa~ge(iess than 4.5 inches long and .27 inches
wide. At only 520mils higfT, this profile package is ideal for systems
with minimum~~cispacing. Extremely high packing density can
also be aChiQy~ci~iallowing four ID17MC4032 modules to be
stacked ~~ioQ~~.Qf board space.
All inp4tP ar\~ outputs of the .1017MC4032 are lTL-compatible
and 0~~!S::t!s:lm a single 5V supply. Fully asynchronous circuitry
is us~; reqt,llring no clocks or refreshing for operation, and providing .eq~tatcess and cycle times for ease of use.

• Separate I/O
• Fast access time: 30ns (max.)
• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• High impedance outputs during write mode
• CEMOS ™ process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled in lOT's high reliability vapor phase solder reflow
process
• Single 5V (±10%) power supply
• Inputs/outputs directly lTL-compatible
• Multiple GNO pins for maximum noise immunity

""""'"

"";,ll'

FUNCTIONAL BLOCK DIAGRAM

32

INPUT

16Kx 32 RAM

OUTPUT

32

DATA OUT

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 19871ntegraled DevIce Technology, Inc.

4~167

DECEMBER 1987
DSC-7004/-

FEATURES:

DESCRIPTION:

• One full megabit of static RAM in popular 1,024K x 1
configuration
.

The IDT71 027 is an extremely high-density (1 ,024K x 1-bit) highspeed static RAM designed for use in systems where fast computation, low power and board density are of the utmost importance.
The IDT71027 uses individual input and output lines to provide
fast read and write access to all memory locations. This function
allows designers to fully utilize the IDT7.1027's already fast 45ns
address access time to achieve a considerable throug~t advantage. An automatic power down feature, controlled by CS, permits
the on-chip circuitry to enter a very low standby power mode and
be brought back into operation at a speed equal to the address
access time. Fabricated using IDT's CEMOS ™ high-performance technology, the IDT71027 typically operates on only 500mW of power at
maximum access times as fast as 45ns. Low-power (L) versions offer battery backup data retention capability, typically consuming
200~W from a 2V battery.
All inputs and outputs of the IDT71027 are TTL-compatible and
the device operates from a standard 5V supply, simplifying system
design. The IDT71027 is packaged in a 28-pin DIP.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

• High-speed access
- Military: 55/70/90ns (max.)
- Commercial: 45/55/70ns (max.)
• Low power consumption
- IDT71027S
Active: 500mW (typ.)
Standby: 5mW (typ.)
-IDT71027L
Active: 500mW (typ.)
Standby: 200~W (typ.)
• Battery backup operation-2V data retention
• Available in 28-pin DIP
• TTL-compatible
• Single 5V (±10%) power supply
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

Ao------~-----,~-r------------------,

1.048,576-BIT
MEMORY ARRAY

DECODER

A

19

-----L___J

DATAIN

-----~

COLUMN I/O

DATA OUT

CONTROL

CEMOS is a trademark of Integrated Device Technology, Inc. '

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-1013/-

1987 Integrated DevIce Technology, Inc,

4-168

IDT71027S AND IDT71027L
CMOS STATIC RAM 1 MEG (1,024Kx 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

L.OGIC SYMBOL

Aa
Al

Vee
A 19
A 1S
A17

Aa
Al

A2
A3

A2
A3
A4·

Ale
A 1S

A4

As
NC

As
Ae
A7
As

A14

Ae
A7
As

NC
A 13

Ag

A11

Ag
Ala
All

A12

DATA OUT

A12

Ala
DATA IN

~

A 13
A14

CS

GND

DATA IN

A1S

Ale
DIP
TOP VIEW

A17

A 1S
A;g

TRUTH TABLE (1)

cs

WE

OUTPUT

H

X

Hi-Z

L

H

DOUT

Read

L

L

Hi-Z

Write

MODE
Deselected

NOTE:
1. H=High. L=Low, X=Don't Care, Hi-Z=High-lmpedance

4-169

DATA OUT

FEATURES:

DESCRIPTION:

• High-density 1 megabit (1024K x 1) CMOS static RAM
module

The 1017MC4001 is a 1 megabit (1024K x 1-bit) high-speed
static RAM module with separate I/O. The module is constructed
on a co-fired ceramic substrate using four 10171257 256K x 1 static
RAMs in surface mount packages.
The 7MC family of ceramic SIPs offers the optimum in packing
density and profile height. The 1017MC4001 is offered in a 30-pin
ceramic SIP (single in-line package). At only 420 mils high, this low
profile package is ideal for systems with minimal board spacing.
Surface mount SIP technology also yields very high packing density, allowing five 1017~.q9q1 modules to be stacked per inch of
board space.
"l\I' "ii)::I
The 1017MC4001,iisl.~v~i1able with maximum access times as
fast as 35ns, withmaximum power consumption of 1.35 watts. The
module also o~.Elrsa full standby mode of 330mW (max.).
All inputs ane:l"putputs of the 1017MC4001 are TTL-compatible
and operate.from asingle 5V supply. Fully asynchronous circuitry
Is used, requiring no clocks or refreshing for operation, and providing equal access times for ease of use.

• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• Available in low profile 3D-pin ceramic SIP (single in-line
package) for maximum space saving
• Fast access times: 35ns (max.)
• Separate I/O lines
• Low power consumption
-'- Dynamic: 1.35W (max.)
- Full standby: 330mW (max.)
• Single 5V(±10%) power supply
• Inputs and outputs directly TTL-compatible

,;",I\r.9~~

'1\.."!"",<

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

I{:~!,,- ::f) .

Vee
A4

Al

A5
A13
WEe

CEo

256Kx 1
RAM

A2

256Kx 1
RAM

256Kx 1
RAM

256Kx 1
RAM

A12

As

Al0
WE l

CEl
Ao
A7
A9
Ae

CE2

WE2
DATAoUT
DATA IN
A3

DATA
IN

DATA
OUT

All

PIN NAMES

CEl
WE3

Ao-17

GND

Address

A14

DATA IN

Data Input

A15

DATA OUT

Data Output

Ale

A17

SIP
SIDE VIEW

~o-3

Chip Select

WE"o-3

Write Enable

Vee

Power

GND

Ground

CEMOS is a trademark of Integrated Device Technology. Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated Devtce Technology. Inc.

08C-7003/-

4-170

FEATURES:

DESCRIPTION:

• One full megabit of static RAM in popular 256K x 4 configuration

The IDT71028 is an extremely high-density (256K x 4-bit), highspeed static RAM designed for use in systems where fast computation, low power and board density are of the utmost
importance.
The IDT71028 uses four bidirectional input/output lines to provide simultaneous access to all bits in a word and has a high-speed
45ns address access time to achieve a considerable through...e!:!.t
advantage. An automatic power down feature, controlled by CS,
permits the on-chip circuitry to enter a very low standby power
mode and be brought back into operation at a speed equal to the
address access time.
Fabricated using lOT's CEMOS ™ high-performance technology, the IDT71028 typically operates on only 500mW of power at
maximum access times as fast as 45ns. Low-power (L) versions offer battery backup data retention capability, typically consuming
200J,JW from a 2V battery.
All inputs and outputs of the IDT71028 are TTL-compatible and
the device operates from a standard 5V supply, simplifying system
design. The IDT71028 is packaged in a 28-pin DIP.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

• High-speed access
- Military: 55/70!90ns (max.)
- Commercial: 45!55/70ns (max.)
• Low power consumption
- IDT71028S
Active: 500mW (typ.)
Standby: 5mW (typ.)
- IDT71028L
Active: 500mW (typ.)
Standby: 200J,JW (typ.)
• Battery back-up operation-2V data retention
• Available in 28-pin DIP
• TTL-compatible
• Single 5V (±10%) power supply
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

\

Ao

t---

1.048,576-BIT
MEMORY ARRAY

DECODER

f---

J

,4

1/00-1/03

I

-

'-

-

f-

-

-

I .............. I

I

.Lf

COLUMN I/O

,4

I

I

CONTROL

,

~4

\

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology, 100.

DECEMBER 1987
05C-1014/-

4-171

4

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT71 028S/IDT71 028L CMOS STATIC RAM 256K (64K x 4-BIT)

LOGIC SYMBOL

PIN 'CONFIGURATION

Ao
Al '

Vee

A2 ,
A3
A4
A5
Ae
A7
As
Ag
AlO

Ale
A15
A14
A13
A12
All

Ao
Al
A2
A3
A4

A17

A5
A6
A7
AS
Ag
A10
All
A12
A13
A14
A15

NC

'CS
, CJE

1/°4
1/03
1/02
1/0 1

GND

~

A16
A17

DIP
TOP VIEW

TRUTH TABLE

cs

C5'E

WE

1/0 1 - 1/04

FUNCTION

H

X

X

HighZ

Deselected, Powered Down (lsB)
,Outputs Disabled

L

H

H

HighZ

L

L

H

DoUT

L

X

L

High Z

NOTE:
1.. H = High, L

Read Data from RAM
Write Data to RAM

= Low, X = Don't Care, High Z = High Impedance

4-172

1/01
1/02
1/03
1/04

FEATURES:

DESCRIPTION:

• One full megabit of static RAM in popular 128K x 8 configuration
• Two chip selects plus Output Enable pin
• High-speed access
- Military: 55/70/90ns (max.)
- Commercial: 45/55/70ns (max.)

The IDT71024 is an extremely high-density 128K x 8-bit highspeed static RAM designed for use in systems where fast computation, low power and board density are of the utmost importance.
The IDT71024 uses eight bidirectional InpuVoutput lines to
provide Simultaneous access to all bits in a word and has an outpu. t
enable (OE) pin which operates as fast as 25ns. This function
allows designers to access the IDT71024 at speeds much higher
than the already fast 45ns address access time to achieve a
considerable throughput advantage. An automatic power down
feature permits the on-chip circuitry to enter a very low standby
power mode and be brought back into operation at a speed equal
to the address access time.
Fabricated using IDTs CEMOS TM high-performance technology, the IDT71024 typically operates on only 500mW of power at
maximum access times as fast as 45ns. Low-power (L) versions
offer battery backup data retention capability, typically consuming
2OO}JW from a 2V battery.
All inputs and outputs of the IDT71024 are TTL-compatible and
the device operates from a standard 5V supply, simplifying system
design. The IDT71024 is packaged in a 32-pin DIP.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-~83, Class B.

• Low power consumption
- IDT71024S
Active: 500mW (typ.)
Standby: 5mW (typ.)
- IDT71024L
Active: 500mW (typ.)
Standby: 2oo}JW (typ.)
• Battery back-up operation-2V data retention
• Available. in 32-pin, 600 mil DIP
• TTL-compatible
• Single 5V (±10%) power supply
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
Ao------~-----,~-r------------------,

1,048,576-81T
MEMORY ARRAY

DECODER

A-16 - - - - L___.J

s

COLUMN I/O

8

CONTROL

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

4-173

DECEMBER 1987
OSC-l0t2/-

91
~

IDT71024S/IDT71024LCMOS STATIC RAM 1 MEGABIT (12SKxS-BIT)

PIN CONFIGURATION

MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOGIC SYMBOL

NC

Vcc

A,6
A,4

A,s
CS2

WE

A12
A7
As

A13
Aa
A9

As
A4
A3
A2
A,

All

OE"
AlO

CST

Ao

I/0 a

liD,
1/02
1/03

1/07
I/0a

GND

1/04

liDS

CS1 CS2
DIP
TOP VIEW

TRUTH TABLE
WE

INPUTS

OUTPUTS

CS 1 CS 2

OE 1/0 0 -1/0 7

FUNCTION

X

H

X

X

HighZ

Deselected

X

X

L

X

HighZ

Deselected

H

L

H

H

HighZ

Outputs disabled

H

L

H

L

DOUT

Read data from RAM

L

L

H

X

HighZ

Write data to RAM

NOTE:
1. H

= High, L = Low, X = Don't Care, High Z = High Impedance

DE WE

DESCRIPTION:

FEATURES:

The IDT8M824S is a1024K (131,072 x 8-bit) high-speed static
RAM constructed on a co-fired ceramic substrate using four
IDT71256 32K x 8 static RAMs in leadless chip carriers. Functional
equivalence to proposed monolithic one megabit static RAMs is
High"speed
achieved by utilization of an on-board decod. er that intoerprets the l
- Military: 60ns (max.)
higher order address A15 and A16 to select one of the four 32K x 8
RAMs. Extremely fast speeds can be achieved with this technique
- Commercial: 40ns (max.)
due to use of 256K static RAMs and the decoder fabricated in IDT's
Low power consumption
high-performance, hjgh-r~liability CEMOS technology.
- Active: less than 550mW (typ.)
The IDT8M824S is av"'iabl~with maximum access times as fast·
- Standby: less than 20mW (typ.)
as 40ns for commerci~lt~mp6rature range, with maximum power
consumption of 1.2 wafts'::p1e module offers a full standby mode of
CEMOS TN process virtually eliminates alpha particle soft
.
440mW (max.). ,,;:~~,
error rates (with no organic die coating)
The I DT8Mag~~;:jS9ffered in a 32-pin, 600 mil center sidebraze
Assembled with lOT's high-reliability vapor phase solder
DIP, adheri,pQ~~p::~~DEC standards for one megabit monolithic
reflow process
.
pinouts, al!QwlngJdr compatibility with future 1T\0nolithics.
Offered in the JEDEC standard 32-pin, 600 mil wide ceramic
All i~RI.,It$:er¢JloutPuts of the IDT8M824S are TTL-compatible
sidebraze DIP
and p~rat~Jr'O'm a single 5V supply. Fully asynchronous circuitry
Single 5V (±10%) power supply
is u~;.(~ulring no clocks or refreshing for operation, and providil)geqyaN!ccess and cycle times for ease of use.
Inputs and outputs directly TTL-compatible
.' \~.[e.III.QT military module semiconductor components are manuModules available with semiconductor components compli,'>'fa,ctured in compliance to the latest revision of MIL-STD-883, Class
ant to MIL-STD-883, Class 8
:<".:\,!=J,. 9'aking them ideally suited to applications demanding the highFinished modules tested at Room, Hot and Cold tempera:,/i"i~ . "".,:~: eSt' level of performance and reliability.
tures for all AC and DC parameters

• High-density 1024K (128K x 8) CMOS static RAM module
• Equivalent to JEDEC standard for future monolithic 128K x 8
static RAMs
•

•

•
•
•
•
•
•
•

:(l~~;;;~;;:.:*)

PIN CONFIGURATION

32Kx8
'-±::E====~ 10T71256
~+-~~------~ ~T~~~
..

RAM

10T71256

32Kx8
CMOS
L -__--I STATIC

~

RAM

...------I10T71256

.-r-----~

tlt1~;:::=::;1

32Kx8
CMOS
STATIC

10T71256
32Kx8

L..-------4

~T~~I~
RAM

RAM

~

lOT FCT139 0 - - - - - - - - - - 1
DECODER

O----------------...J

DIP
TOP VIEW
1. For module dimensions, please refer to module
drawing M2 in the packaging section.

PIN NAMES
Write Enable

A0- 16

Addresses.

WE

1/00-8

Oata Input/Output

OE

Output Enable

CS

Chip Select

GNO

Ground

Vee

Power

CEMOS is a trademark of Integrated Oevice Technology, Inc.

MILITARY AND COMMERCIAL TEMPE,RATURE RANGES
© 1987 Integrated DeII1ce Technology. Inc.

4-175

DECEMBER 1987
Prln1ed In U.S.A.

91
~

FEATURES:

DESCRIPTION:

• High-density 1024K (128K x 8) CMOS static RAM module

The IDT8MP824S is a1024K (131.072 x 8-bit) high-speed static
RAM constructed on an epoxy laminate substrate using four
IDT71256 32K x 8 static RAMs in plastic surface mount packages.
Functional equivalence to proposed monol ithic one megabit static
RAMs is achieved by utilization of an on-board decoder that interprets the higher order address AI5 and AI6 to select one of the four
32K x 8 RAMs. Extremely fast speeds can be achieved with this
technique due to use of 256K static RAMs and the decoder fabricated in IDT's high-perfci~oce. high-reliability CEMOS technol-

• Fast access time
- 40ns (niax.) over commercial temperature range
• Low power consumption
- Active: less than 500mW (typ.)
- Standby: less than 8mW (typ.)
• Cost-effective plastic surface-mounted RAM packages on an
epoxy laminate (FR4) substrate
• Offered in a SIP (single in-line package) for maximum spacesaving
• Utilizes ID171256s-high-performance 256K static RAMs produced with advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible

og~e IDT8MP824sJ~'::~:~~i'ft~le

with maximum access times as
fast as 40ns ove~~ithe commercial temperature range. with maximum operatinge~,~r consumption of 825mW. The module also
offers a full staQd~ymode of 330mW (max.).
The IDWMP,&24S is offered in a 30-pin SIP. For the 32-pin
JEDEC ~tand~r(jjDIP. refer to the IDT8M824S.
All i!1pu~'s'llt'18 outputs of the IDT8MP824S are TTL-compatible
and 9perate:from a single 5V supply. Fully asynchronous circuitry
is usoo.reCjuiring no clocks or refreshing for operation. and providir;lgequal access and cycle times for ease of use.
t.
;~J
,ll\\' ~~\ 'lo'"
1\,

,,1\.'.'

PIN CONFIGURATION
~\I{",,::i.:?:,~,,\\'''::,·r
'""""

10
11
12
13
14
M12(1) ::
17

18
19
20

21,
22

23
24
25
26

27
28
29

30

A7
A6
A5
A4
A3
A2
AI
AD
WE
Vce
GND
1/01
1/02
1/03
1/04
1/05
I/Oe
1/07
I/Os
CS
OE
As
A9
AID
All
AI2
AI3
AI4
AI5
A16

A0-14

(

":11

I/O I-S?',;,>I:;:::: .,::(

M~t:;\I'
.k!.":::;r\i""",.:"

~,~,;,,:,:::>'"

-

'--

IDT71256
32Kx8
CMOS
STATIC
RAM

IDT71256
32Kx8
CMOS
STATIC
RAM

-

~~

---

~y
A Is A 16 -

CS--C

CS~

CS

~

FCT139
DECODER

IDT71256
32Kx8
CMOS
STATIC
RAM

IDT71256
32Kx8
CMOS
STATIC
RAM

~

...,
~

SIP
SIDE VIEW

PIN NAMES
A O- 16
1/0 l_S
CS
Vee
WE
OE
GND

Addresses
Data Input/Output
Chip Select
Power
Write Enable
Output Enable
Ground

1. For module dimensions. please refer to module drawing M12 in the packaging section.
CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RAN~E
© 19S7 Integrated Devlce Technology, Inc,

DECEMBER 1987
DSC-7015/-

DESCRIPTION:

FEATURES:

The IDT7M624 is a 1024K-bit high-speed CMOS static RAM
constructed on a multi-layered ceramic substrate using 16
IDT7187 64K x 1 static RAMs in leadless chip carriers. Making four
chip select lines available (one for each group of 4 RAMs) allows
theusertoconfigurethememoryintoa64KX16,128KX80r256Kx
4 organization. In addition, extremely high speeds are achievable
by the use of IDT7187s fabricated in lOT's high-performance, highreliability technology, CEMOS. This state-of-the-art teChnology,
combined with innovativ~Cir,9uit design techniques, provides the
fastest 64K static RAMs available.
The IDT7M624 is c(va,iICibte""with access times as fast as 25ns
commercial and ~?ns' military temperature range, with maximum
operating powe~CQ\1~umption of only 12.3W (significantly less if
organized 128K~:,~oi256K x 4). The module also offers a standby
power mOCi,~;'Q!>?;:ryv (max.) and a full standby mode of 1.7W
(max.).
i:',,:;~ '."
The JPTIM&Z4 is offered in a 40-pin, 900 mil center sidebraze
DIP t9~,ke~9vantage of the compact IDT7187s in lead less chip
cal"rl.~rS;"l~:::, .,
,{:;AIt"iQPuts and outputs ofthe IDT7M624 are TTL-compatible and
;p~rCl.;~.from a single 5V supply. (NOTE: Both GND pins need to be
'\;;''Qr,o~iided for proper operation.) Fully asynchronous circuitry is
';;'<':\LlS~, requiring no clocks or refreshing for operation, and providing
ual access times for ease of use.
AIIIDT military module semiconductor components are compliant with the latest revision of MIL-STO-883, Class B, making them
ideally suited to applications demanding the highest level of
performance and reliability.

• High-density 1024K-bit CMOS static RAM module
• Customer-configured to 64K x 16, 128K x 8 or 256K x 4
• Fast access times
- Military: 35ns (max.)
- Commercial: 25ns (max.) .
• Low power consumption
- Active: 4.8W (typ. in 64K x 16 organization)
- Standby: 1.6mW (typ.)
• Utilizes 161DT7187 high-performance 64K x 1 CMOS static
RAMs produced with IDT's advanced CEMOS TM technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Offered in 4Q-pin, 900 mil center sidebraze DIP, achieving
very high memory density
• Pin-dompktible with IDT7M656 (256K RAM module)
•
•
•
•

Single 5V(±10%) power supply
Dual GND pins for maximum noise immunity
Inputs and outputs qirectly TTL-compatible
Modules available with semiconductor components compliant to MIL-STD-883, Class B
,(

• Finished modules tested at Room, Hot and Cold tem~a~~>
tures for all AC and DC parameters
.,,,,~;,,;:>,,. "';'

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION
(llGND

Ao -A 16

Vee

0 15

011
CS(6-1l)

CS(12-15)

WF.

CS0-3-++HHH------~~------~~------~

04

Do

"Chip Select

Al

Ao
A 13
0 10

Write Enable

A12

Ground

014
A2

05

01
A11
Al0

A3
A4
013

Power

WF.~~====~~==~~====~

og

CS8- l1 -+-+--<.-H------~+t------~+t--------..

Ag
O2

A5

06
A6

--.-~~-------.--------~--------~

As

. A7

A14
0 12

o

~(0-3)

CS(4-7)
07
03
A 15 -..;~_ _ _~ GNo(l)
DIP
TOP VIEW

NOTES:
1. Both GNo pins need to be grounded for proper operation.
2. For module dimensions, please refer to module drawing M6 in the
packaging section.
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

, DECEMBER 1987
OSC-7011/-

1987lnlegraled DevIce Technology. Inc.

4-177

g
~

DESCRIPTION:

FEATURES:

The IDT7MB624 is a 1024K-bit high-speed CMOS static RAM
constructed on an epoxy laminate substrate using 16 IDT7187
(64K x 1) static RAMs in plastiC surface mount packages. Making
four chip select lines available (one for each group of 4 RAMs) allows the user to configure the memory into a 64K x 16, 128K x 8 or
- 25ns (max.)
256K x 4 organization. In addition, extremely high speeds are
Low power consumption
achievable by the use of IDT7187s fabricated in IDT's high- Active: 4.8W (typ.) (in 64K x 16 organization)
performance, high-relial:lility CEMOS technology. This state-ofthe-art technology, com6i~ed with innovative circuit design tech- Standby: 1.6mW (typ.)
niques, provides thelasfest94K static RAMs available.
Utilizes 16 IDT7.187 high-performance 64K x 1 CMOS static
The IDT7MB624 is available with access times as fast as 25ns
RAMs produced with IDT's advanced CEMOS TM technology
over the commerc.ial temperature range, with maximum operating
CEMOS process virtually eliminates alpha particle soft error
power. consuTPtl~rl.pf only 9.6W (significantly less if organized
rates (with no organic die c9ating)
128K x 8 or 256t<~x4). The module also offers astandby power
Offered in 40-pin, 900 mil center plastic DIP, achieving very high
mode of 4.4w.(~a)C.) and a full standby mode of 1.7W (max.).
memory density
The IDlfMBp24 is offered in a high-density 40-pin, 900 mil centor PIa,St!pPU? take full advantage of the compact IDT7187s in
Cost-effective plastiC surface mounted RAM packages on an
plasticsurfaqe mount packages.
.
epoxy laminate (FR4) substrate
.
.,AI.I kiplJts and outputs of the IDT7MB624 are TTL-compatible
and o~riite from a single 5V supply. (NOTE: Both GND pins need
'> td~ grounded for proper operation.) Fully asynchronous circuitry
<·'.·· . is Lised, requiring no clocks or refreshing foroperation, and provid,.".,:~;i.:dng 'equal access times for ease of use.

• High-density 1024K-bit CMOS static RAM module
• Customer-configured to 64K x 16, 128K x 8 or. 256K x 4
., Fast access times
•

•
.
•
•
•

to

..'

t. >~ ·::~'./,n"\'
I;,)" w'

.. .,

'.:\~ j

FUNCTIONAL BLOCK DIAGRAM

ADDRESS - - - - . ' - " - - - 1

64K x 16
RAM

I/O

DJFA

CEMOS is a trademark of Integrated Device Technology, Inc.

DECEMBER 1987

COMMERCIAL TEMPERATURE RANGE
©

DSC-7001/-

1987 Integrated DevIce Technology, Inc.

4-178

FEATURES:

DESCRIPTION:

The IOTSM624S/IOTSM612S are 1024K/512K-bit high-speed
CMOS static RAMs constructed on a multi-layered ceramicsubstrate using four 10171256 32K x 8 static RAMs (IOTSM624S) or
two 10171256 static RAMs (IOT8M612S) in leadless chip carriers.
Upper byte (1109-16) and lower byte (I/O 1-8) separated control
Functional equivalence to proposed monolithic static RAMs is
- Allows flexibility in application
achieved by utilization of an on-board decoder that interprets t h e D i
higher order address A15 to select one of the two 32K x 16 RAMs as ~
Equivalent to JEOEC standard for future monolithic 64K x 16/
the by-16 output and using LB and UB as two extra chip select
32K x 16 static RAMs
functions for lower bytejl/01-8) and upper byte (1109-16) control,
High speed, 40ns (max.) over commercial temperature range
respectively. (On the IDT8M612S 32K x 16 option, A15 needs to be
Low power consumption
extemally groundedf,?cproper operation.) Extremely high speeds
are achievable by the ~ of 10171256s fabricated in lOT's highCEMOS ™ process virtually eliminates alpha particle soft error
performance, hiQP-reliability technology, CEMOS. This state-ofrates (with no organic die coating)
the-art technO!oQVI:;cqmbined with innovative circuit design techAssembled with lOT's high-reliability vapor phase solder reflow
niques, provj,¢Jes:t~efastest 1024K/512K static RAMs available.
process
The IOWM62~SlIDT8M612S are available with access times as
Offered in the JEDEC standard 40-pin, 600 mil wide ceramic
fast as 4pn$:'"
.'"
,

",
I'~';:(;;

1/09 -1/016

',,..,

,"'"

,,""''''

1/01 -1/08

_:":""C

,">

"J

WE
'---

IDT71256
32Kx8
CMOS
STATIC
RAM
)

I
I

1/2 FCT139
DECODER

I:::

IDT71256
32Kx8
CMOS
STATIC
RAM
(

IDT71256
32Kx8
CMOS
STATIC
RAM

-

IDT71256
32Kx8
CMOS
STATIC
RAM

0

()

to-

y

L=J

1/2 FCT139 [
DECODER ~

Y

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology, Inc,

4-179

DECEMBER 1987
DSC-7017/-

DESCRIPTION: '

FEATURES:
• High-density 1024K/512K-bit CMOS static RAM module
• 64K x 16 organization (IDTSMP624) with 32K x 16 option
(IDTSMP612)
• Upper byte (1/09-16) and lower byte (1/01-8) separated control
- Allows flexibility in application
• Fast access time: 40ns (max.)
• Low power consumption
• CEMOS TM process virtually 'eliminates alpha particle soft
error rates (with no organic die coating)
• Offered in a SIP (single in-line) package for maximum
space-savings
• Cost-effective plastic surface-mounted RAM packages on an
epoxy laminate (FR4) substrate
• Single5V (t10%) power supply
• Inputs and outputs directly TIL-compatible

FUNCTIONAL BLOCK DIAGRAM

The IDTSMP624S/IDTSMP612S are 1024K/512K high-speed
CMOS static RAMs constructed on an epoxy laminate substrate
using four ID171256 32K x S static RAMs (IDT8MP624S) or two
ID171256 static RAMs (IDTSMP612S) in plastic surface-mount
packages. Functional equivalence to proposed monolithic static
RAMs is achieved by utilization of an on-board decoder that interprets the higher order address A15 to select one ofthe two 32K x 16
RAMs as the by-16 outp~a;nd using LS and US as two extra chip
select functions for low~d~yte (1/01-8) and upper byte (1/09-16)
control, respectively.,(Oh the,IDT8MP612S 32K x 16 option, A15
needs to be externallygtoun'ded for proper operation.) Extremely
high speeds are.(l.~hievecfby the use of ID171256s fabricated in
IDT's high-perf9r~n~e, high-reliability technology, CEMOS. This
state-of-the-art~te~nnCilogy, combined with innovative circuit design techni~oo~>Provides the fastest 1024K/512K static RAMs
available,,: \)\",).1
The.,,1PTSMP624S/IDT8MP612S are available with access times
over the commercial temperature range, with maxias f8:~t:a~
mymoperating power consumption of only 1.SW (64K x 16 option).
T:6e';'module also offers a full standby mode of 330mW (max.)
<'~;I' \::Jtl~'j'DTSMP624S/IDTSMP612S are offered in a 40-pin plastic
 \:AI)JQT military module semiconductor components are compli'ant.to·the latest revision of MIL-STD-883, Class B, making them
",; }9~ally suited to applications demanding the highest level of
, pe'rformance and reliability.

• Multiple GND pins for maximum noise immunity
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components compliant
to MIL-STD~883, Class B

i}

'FUNCTIONAL BLOCK DIAGRAM

ADDRESS --~--~

256Kx4

256Kx 4

256Kx4

256Kx 4

RAM

RAM

RAM

RAM

DATA

DATA

DATA

DATA

WE'u - - - - - { ]
WE'L

-----<]

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 19871nlegraled DevIce Technology. Inc.

DECEMBER 1987
DSC-7009/-

4-183

4

FEATURES:

DESCRIPTION:

• High-speed address access time
- Military: 15ns
- Commercial: 12ns
• High-speed comparison time
- Military: 15ns
- Commercial: 12ns
• Low power consumption
- IDT6178S
Active: 300mW (typ.)
• Produced with advanced CEMOS ™ high-performance
technology
• Input and output TTL-compatible
• Three-state output
• Static operation: no clocks or refresh required
• Military product compliant to MIL-STD-883, Class B.

The IDT6178 is a high-speed cache address comparator subsystem consisting of a 16,384-bit static RAM organized as 4K x 4.
Cycle Time and Compare Access Time are equal. The IDT6178
features an on board 4-bit comparator that compares RAM contents and current input data. The result is an active high level on the
MATCH pin. The MATCH pins of severallDT6178s can be nanded
together to provide enabling acknowledging signals to the data
cache or processor.
The IDT6178 is fabricated usin~ IDT's high-performance, highreliability technology-CEMOS T • Address-to-compare access
times as fast as 12ns are available, with Tag Data-ta-compare
access times as fast as 12ns.
All inputs and outputs of the IDT6178 are TTL-compatible and
operate from a single 5V supply. Fully static asynchronous circuitry is used, which requires no clocks or refreshing for operation.
The IDT6178 is packaged in either a 22-pin, 300 mil plastic or
ceramic DIP and military grade product is manufactured in
compliance with the latest revision of MIL~STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

ADDRESS

4Kx4
HIGH-SPEED
STATIC RAM

-

~
MATCH
(DATA INPUTS =
RAM DATA OUTPUTS)

COMPARATOR

,-

DATA I/O

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology. Inc.

4-184

DECEMBER 1987
DSC-l030/-

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT6178S CMOS STATIC RAM 16K (4K x 4-BIT) CACHE-TAG RAM

LOGIC SYMBOL

PIN CONFIGURATION
Vee

A4
A5
Ae
A7
As
Ag
A10
A11
~

WE

A3

00 0

Az

00 1

A1
Ao

00 2

'CDi

00 3

0°3
0°2
0°1

MATCH

0°0
MATCH

GND

DIP
TOP VIEW

TRUTH TABLE

(1)

WE

OE

CLR

X

X

L

L

X

H

H

H

H

Data In

H

H

H

L

Data In

Compare, not equal

L

X

H

L

Data In

Write

H

L

H

L

Data Out

Read

MATCH 00 0

-

00 3

FUNCTION
Reset
Compare, equal

NOTE.
1. H = High, L = Low, X = Don't Care

4-185

FEATURES:

DESCRIPTION:

• High-speed address to MATCH comparison time
- Military: 45/55ns (max.)
- Commercial: 37/45ns (max.)
• High-speed address access time
- Military: 45/55ns (max.)
- Commercial: 35/45ns (max.)
• High-speed chip select access time
- Military: 25/30ns (max.)
- Commercial: 20/25ns (max.)

The IDT7174 is a high-speed cache address comparator subsystem consisting of a 65,536-blt static RAM organized as 8K x 8
and an 8-bit comparator. A single IDT7174 can map 8K cache
words into a 1 megabyte address space by comparing 20 bits of
address organized as 13 word cache address bits and 7 upper
address bits. Two IDT7174s can be combined to provide 28 bits of
address comparison, etc. The IDT7174 also provides a single RAM
clear contrOl, which clears all words In the Internal RAM to zero
when activated. This allows the tag bits for all locations to be
cleared at power-on or system-reset, a requirement for cache
comparator systems. The IDT7174 can also be used as an8Kx8
high-speed static RAM.
The IDT7174Is fabricated using lOT's high-performance, highreliability technology-CEMOS. Address access times as fast as
35ns, chip select times of 20ns and address-to-comparison times
of 37ns are available with maximum power consumption of
825mW.
All Inputs and outputs of the IDT7174 are TTL-compatible and
the device operates from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for
operation.
The IDT7174 Is packaged In a 28-pin DIP (600 mil and 300 mil),a
28-pin SOIC arid 32-pln LCC and PLCC, providing high board level
packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making It Ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• Low-power operation
- IDT7174S
Active: 300mW (typ.)
• High-speed asynchronous RAM Clear on Pin 1
(Reset Cycle Time = 2 x tAA)
• MATCH Output on Pin 26
• Produced with advanced CEMOS 1M high-performance
technology
..
•
•
•
•
•

Single 5V (±10%) power supply
Input and output directly TTL-compatlble
Three-state output
Static operation: no clocks or refresh required
Standard 28-pln DIP (600 mil and 300 mil), 28-pln SOIC, 32-pin
LCCand PLCC
• Military product compliant to MIL-STD-883, Class B
l

FUNCTIONAL BLOCK DIAGRAM
A

256 x 256
MEMORY ARRAY

ROW
CENTER

A
~

---------0 ~------~

110 .......----.:To---i

M

MATCH (OPEN DRAIN)

CEMOS Is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 19871nlegrated DevIce Technology. Inc.

4-186

DECEMBER 1987
DSC-10401-

IOT7174S CMOS STATIC RAM
64K (SK x S-BIT) CACHE-TAG RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
"R"ESET

Vee

....

MATCH
As
A9
All

LJLJU:1UULJ
4 3 2 U 32 31 30
] 5

]7

Ala

CS 1
I/0 s

1/07
I/0 e
1/05
1/04

GND

1

] e

erE

1/02
1/03

] s

J32-1

] 9

L3~-1

VTERM
TA

,

RATING
Terminal Voltage
with Respect to
GND
Operating
Temperature

All

26 [:

NC

erE
CS

NC

] 12

22 [

II0 s

] 13
14 15 16

21 [

1/07

17

18 19

AlO

20

nnnnnnn
'"

0

()

oq-

III

co

OOzzOOO
:::::: :::::- C!l

I/0 s
MATCH

PIN NAMES

R"E"S"ET
CS
erE
WE

Oto +70

Write Enable

Aa-12

Address

WE

1/01-8
CS

Data Input/Output

OE

Output Enable

Chip Select

GND

Ground

RESET

Memory Reset
Vcc
Data/Memory Match (Open Drain)

MATCH

Power

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL
-0.5 to +7.0

::::-::::-:::::-

LCC/PLCC
TOP VIEW

1/0 1
1/0 2
1/03
1/04
1/05
I/0 e
1/0 7

ABSOLUTE MAXIMUM RATINGS
SYMBOL

27[:

] 11

N

A12

As
A9

Aa

LOGIC SYMBOL

A3
A4
A5
Ae
A7
As
A9
Ala
All

29 [:

2S [

25 [
24 [
23 [

DIP/SOIC
TOP VIEW

Aa
Al
A2

NI~ 01 ~

~w()owC:(

INDEX~ r-;,...ct:f"""P-oct:.......a:...,..z..ry..>....3:..-r1.....:::i:......

WE

A12
A7
Ae
A5
A4
A3
A3
Al
Aa
1/01

MILITARY
-0.5 to +7.0

-55 to +125

UNIT

SYMBOL

V

°C

TB1AS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

PARAMETER

MIN.

TYP.

MAX.

Vcc

Supply Voltage

4.5

5.0

5.5

UNIT
V

GND

Supply Voltage

0

0

0

V

V1H

Input High Voltage (1)

2.2

-

6.0

V

V1HR

RESET Input High
Voltage

2.5(2)

-

6.0

V

-0.5(3)
Input Low Voltage
0.8
V
V1L
NOTES:
1. All inputs except RESET.
2. When using bipolar devices to drive the RESET input. a pullup resistor
of 1kn-10kn is usually required to assure this voltage.
3. V1L (min.) = -3.0V for pulse width less than 20ns.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial

4-187

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V ± 10%

Vec

IDT7174S CMOS STATIC RAM
64K (8K x 8-BIT) CACHE-TAG RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ±10%
TEST CONDITIONS

PARAMETER

SYMBOL

MIN.

IDT7174S
TYP.(1)

-

-

-

-

IIUI

Input leakage Current

Vce = Max., VIN = GND to Vee

MIL.
COM'L.

IILOI

Output Leakage Current(2)

Vee = Max.
CS = VIH • VOUT = GND to Vee

MIL.
COM'L.

IOL = 18mA MATCH

MIL.

-

IOL = 22mA MATCH

COM·L.

-

Output low Voltage

VOL

IOL
IOL
VOH

= 10mA, Vee = Min. (All outputs except MATCH)
= 8mA, Vee = Min. (All outputs except MATCH)

IOH = -4mA, Vee = Min.
(Except MATCH)

Output High Voltage

UNIT

MAX.
10
5

J1A

-

-

10
5

J1A

-

0.5

V

0.5

V

-

-

0.5

V

-

-

0.4

V

2.4

-

-

V

NOTES:
1. Typical limits are at Vee = 5.0V. +25°C ambient.
2. Data and MATCH

DC ELECTRICAL CHARACTERISTICS (1)
Vee = 5.0V ±10%
SYMBOL

IDT7174S35
COM'L
Mil.

PARAMETER

IDT7174S45
COM'L.
MIL

IDT7174S55
COM'L
MIL

UNIT

Ice1

Operating Power Supply Current Outputs Open.
Vee= Max., f = 0

110

-

110

125

-

125

mA

lec2

Dynamic Operating Current Outputs Open,
Vee = Max., f = f Max

150

-

140

150

-

145

mA

NOTE:
1. All values are maximum guaranteed values.

AC TEST CONDITIONS
Input Pulse levels
Input Rise/Fall Times
Input Timing Reference levels
Output Reference levels
Output load

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1, 2 & 3
5V

5V

DATA OUT

~

2550

5V

48on
30pF

Figure 1. Output load

DATA OUT

~

2550

48on
5pF*

Figure 2. Output load
(for tcLZ t oLZ, t cHZ ' tOHZ ,
tow,tWHZ)

* Including scope and jig

4-188

MATCH

--i~

RL

r

PF

RL = 200fl (COM'L.)
= 270fl (MIL.)
Figure 3. Output Load for MATCH

IDT7174S CMOS STATIC RAM
64K (SKx S-BIT) CACHE-TAG RAM

DATA

MILITARY AND COMMERCIAL TEMPERATURE RANGES

--

/

ADDRS

/

~

16-BIT
MICROPROCESSOR
5V

~

'>

,~

Logic 1

/V;3

CLEAR

(

-.

16/

20/

WAIT

---+

Y

~~7

.IVa

~

-

DATA
ADDRS

.IVa

"

"

IDT7174
CACHETAG
RAM

,~

IDT7164
CACHEDATA
RAM

MAIN
MEMORY

"

IDT7164
CACHEDATA
RAM

MATCH

+

--

MEMORY READ/WRITE
CONTROL LOGIC

,.

CACHE READ/WRITE

..

MAIN MEMORY READ/WRITE

Figure 4. Example of Cache Memory System Block Diagram
NOTES:
1. For more information. see application note AN-07 ·Cache-Tag RAM Chips Simplify Cache Memory Design".
2. RL = 2000 (commercial) or 2700 (military)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(Vee = 5.0V ±10%. All Temperature Ranges)
IDT7174S35
MIN.

MAX.

IDT7174S55 (2)

IDT7174S45

(1)

MIN.

MAX.

MIN.

MAX.

UNIT

WRITE CYCLE
twc

Write Cycle Time

35

-

45

-

55

Chip Select to End of Write

20

25

-

30

tAW

Address Valid to End of Write

30

40

-

50

-

ns

t AS

Address Set-up Time

0

0

-

0

Write Pulse Width

30

40

50

tWR

Write Recovery Time (CS. WE)

0

0

-

0

-

ns

twp

-

-

ns

tcw

ns

ns

ns

tWHZ

Write Enable to Output in High Z (3)

-

15

-

20

-

25

ns

tow

Data to Write Time Overlap

15

20

Data Hold From Write Time

2

Output Active from End of Write (3)

5

-

ns

tow

-

25

tOH

-

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed but not tested.

4-189

2
5

2
5

ns

ns

IDT7174S CMOS STATIC RAM
64K (SK x S-BIT) CACHE-TAG RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OFWRITE CYCLE NO.1

(1)

(

~--------------------twc------------------~

ADDRESS

(04------------------ tAW ----------------.1

~-------twp

(2) - - - _ . I

DATAoUT
tow
DATA IN

tOH
VALID DATA IN

TIMING WAVEFORM OFWRITE CYCLE NO.2

(1,6)

~--------------------twc--------------------~

ADDRESS

~------------~-----tAw--------------~~

-----+-~--_""""Ir__"""or'_ ~--------twp(2)---------.lI.I"-_+-------

DATA OUT

ttow
DATA IN

tOH~

---------------------iCI<-~ALlD DATA IN ~

NOTES:

1.
2.
3.
4.
5.
6.
7.
8.
9.

WE must be high during all address transitions.
A write occurs during the overlap (t wp) of a low
and a low ~.
tWR is measured from the earlier of"CS or WE going high to the end of the write cycle.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
If the "CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state.
DE is continuously low (DE = VIL).
'
DATAoUT is the same phase of write data of this write cycle.
If CS" is low during this period, I/O pins are in the output state. Data input signals of opposite phase to the outputs must not be applied to them.
Transition is measured ±200mV from steady state.
'

wr:.

4-190

10T7174S CMOS STATIC RAM
64K (8K x S-BIT) CACHE-TAG RAM

AC ELECTRICAL CHARACTERISTICS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(Vcc = 5.0V ±10%. All Temperature Ranges)
IOT7174S35

SYMBOL

PARAMETER

MIN.

10T7174S55

IOT7174S45

(1)

MAX.

MIN.

(2)

MAX.

MIN.

MAX.

UNIT

MATCH
t AOM

Address to MATCH Valid

-

37

-

45

ns

Chip Select to MATCH Valid

-

20

-

25

-

55

tCSM

30

ns

tCSMHI

Chip Deselect to MATCH High

-

20

-

25

-

30

ns

tOAM

Data Input to MATCH Valid

28

-

35

-

45

ns

tOEMHI

OE Low to MATCH High

25

-

ns

OE High to MATCH Valid

25

-

35

-

45

tOEM

45

ns

25

-

35

-

45

ns

25

-

35

45

ns

25

-

35

-

45

ns

-

5

-

5

-

ns

5

-

ns

tWEMHI

WE Low to MATCH High

tWEM

WE High to MATCH Valid

tRSMHI

RESET Low to MATCH High

-

tMHA

MATCH Valid Hold From Address

5

MATCH Valid Hold From Data
t MHO
NOTES:
1. DoC to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.

5

'""

5

35

MATCH TIMING

ADDRESS

CS

*

t AoM
tCSM

i

OE

Wi:

RESET

DATA

VALID READ DATAoUT

MATCH
NO MATCH

4-191

tMHA

•

IDT7174S CMOS STATIC RAM
64K (SK x B-BIT) CACHE-TAG RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (Vcc = 5.0V ±10%, All Temperature Ranges)
PARAMETER

SYMBOLI

I

IDT7174S3S (1)
MIN.
MAX.

I

IDT7174S4S
MIN.
MAX.

I

IDT7174SSS (2)
MIN.
MAX.

I

UNIT

RESET
t RSPW
t RSRC

I RESET Pulse Width
I RESET High to WE Low

I
I

(3)

-

65
5

1
I

-

80
10

1 100

-

10

-

I

I
I

ns
ns

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. Recommended duty cycle 10% maximum.

RESET TIMING

~

xXXXXXXXXXXXXXXXXXXXY

CAPACITANCE(l) (TA= +25°C, f = 1.0MHz)
SYMBOL
CIN
COUT

PARAMETER(l)
Input Capacitance

CONDITIONS
VIN = OV

TRUTH TABLE
MAX.

UNIT

WE

CS

OE

MATCH

1/0

FUNCTION

8

pF

X

X

X

L

H

-

Reset all bits to low

HighZ

Output Capacitance
Vour= OV
8
pF
NOTE:
1. This parameter is determined by device characterization, but is not
production tested.

RESET

X

H

X

H

H

H

L

H

H

L

DIN

H

L

H

H

H

DIN

MATCH

H

L

L

H

H

Dour

Read

L

L

X

H

H

DIN

Write

5V

IDT7174

CMOS Gate

IDT7174

Bipolar Gate

Driving the RESET pin with CMOS logic.

Driving the RESET pin with bipolar logic.

Figure 4.

4-192

Deselect chip
No MATCH

IDT7174S CMOS STATIC RAM
64K (SK x 8-BIT) CACHE-TAG RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(Vcc = 5.0V ±10%, All Temperature Ranges)
1OT7174S35

SYMBOL

PARAMETER

IOT7174S55

1OT7174S45

(1)

MAX.

MIN.

MIN.

MAX.

MIN.

(2)

MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

35

-

45

-

.55

-

ns

tAA

Address Access Time

35.

-

45

-

55

ns

tAcs

Chip Select Access Time

-

20

-

25

-

30

ns

tcLZ

Chip Select to Output in Low Z

0

-

0

-

0

-

ns
ns

tOE

Output Enable to Output Valid

-

20

-

25

-

30

toLZ

Output Enable to Output in Low Z (3)

0

-

0

-

0

-

ns

tCHZ

Chip Select to Output in High Z (3)

-

15

-

20

-

25

ns

tOHZ

Output Disable to Output in High Z

-

15

-

20

-

25

ns

tOH

Output Hold from Address Change

5

-

5

-

5

-

ns

(3)

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter is guaranteed but not tested.

4-193

IDT7174S CMOS STATIC RAM
64K (8Kx S·BIT) CACHE·TAG RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1

(1)

~--------............... tRC""''''''''''''''''''''''''''~

ADDRESS

..........-+.....~
t CLZ (5), .....- - _ 1

1 4 - - - - - t Acs 14-..........-

DATA OUT

TIMING WAVEFORM OFREAD CYCLE NO.2

ADDRESS

(1,2,4)

--i~I::~_tRC

-}--tOH--l

_~
__~__~=_:~:::::__tO_H~:tAA:_~-=~~_~""'--~'I~
~

DATAoUT

TIMING WAVEFORM OFREAD CYCLE NO.3

DATA OUT

(1,3,4)

~t~~
~ __:1--~~======================~
__________tC_LZ
__
(5)_

NOTES:

1.
2.
3.
4.
5.

~ ~~

______'_______

WE is High for Read Cycle.
Device is continuously selected, CS = V IL •
Address valid prior to or coincident with CS" transition low.
OE = V1L
Transition is measured ±200mV from steady state.

4-194

1_

¥

1017174S CMOS STATIC RAM
64K (SKx S-BIT) CACHE-TAG RAM

MILITARY AND COMMERCIAL TEMPERJ\TURE RANGES

ORDERING INFORMATION

lOT·

oev~ype

999
Speed

A
Package

A
Process!
Temperature

RMy:Mk
P

~

______________

TC
~

0

J
L
SO

L...-------------t
L...-_________________

~

L...----------------------f

4-195

Commercial (O°C to

+70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STO-883, Class B,
Method 5004
Plastic DIP
THINOIP (Sidebraze)
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Small Outline IC

35
45
55

Commercial Only }

S

StandMdPower

7174

64K (8K x 8-Bit) Cache-Tag RAM

Speed in Nanoseconds
Military Only

FEATURES:

DESCRIPTION:

• High-speed asynchronous RAM clear on Pin 1 (clears all RAM
bits to 0, reset cycle time = 2 x tM)

The ID17165Is a high-speed 65,536-bit static RAM, organized
8K x 8, with reset function. The RESET pin provides a single RAM
clear control which clears all words in the internal RAM to zero
when activated. This allows the memory bits for all locations to be
cleared at power-on or system reset, or for a fast clear to be available to graphics, histogramming and other designs where a byteby-byte RAM clear would cause noticeable system speed
degradation.
This product Is fabricated using IDT's high-performance, highreliability CEMOS technology. Address access time of 30ns and
chip select (CS 1) time of 15ns are available with maximum power
consumption of only 770mW. This circuit also offers a reduced
power standby mode. When CS2 goes low, the circuit will automatically go to and remain in a low-power standby mods. In the full
standby mode, the low-power device typically consumes less than
30~ W . The low-power (L) version also offers a battery backup data
retention capability where the circuit typically consumes only
10~W operating from a 2V battery.
All inputs and outputs of the IDT7165 are TTL-compatible and
the device operates from a single 5V supply, simplifying system
designs. Fully static asynchronous circuitry is used, so no clocks
or refreshing operation is required:
The IDT7165 is packaged in a 28-pin 300 or 600 mil DIP, 28-pin
SOIC, and 32-pin LCC and PLCC, providing high board level
densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
the military. temperature applications which require instant destruction of sensitive RAM data and demand the highest level of
performance and reliability.

• High-speed address access time
- Military: 35/45/55ns (max.)
- Commercial: 30/35/45/55ns (max.)
• High-speed chip select (CS1) time
- Military: 20/25/30/35ns (max.)
- Commercial: 15/20/25/30ns (max.)
• Low-power operation
- IDT7165S
Active: 300mW (typ.)
Standby: 100~W (typ.)
- IDT7165L
Active:250mW (typ.)
Standby: 30~W (typ.)
• Battery backup operation - 2V data retention voltage
(IDT7165L only)
• Produced with CEMOS ™ high-performance technology
• Single 5V(±10%) power supply
• Input and output directly TTL-compatible
• Three-state outpUt
• Static operation: no clocks or refresh required
• Standard 28-pin, 600 mil DIP, 300 mil DIP, 28-pin SOIC, 32-pin
LCC and PLCC
• Military product is compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

Ao

256 x 256

ROW
•

DECODER

•

1-----1

MEMORY ARRAY

~----q

1/01- 8

~~---,pL---i

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-1021/-

1987 Integrated Oevtce Technology. Inc.

4-196

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT7165S/IDT7165L CMOS STATIC RAM 64K (SK x S-BIT)

...

"'I~ u °IW en
INDEX~ ~. .,L. I-<~I" "L. ;Z.r;,.:.r~"~. {',':. ,f, " ",

~
A12
A7
Ae
A5
A4
A3
A3

r-1L..
.....

4

.....a:.-,....

3 2

] 5

U

32 31 30

1

]6
]7

Al

AO

]8

1/0 1

]9

1/02
1/03
GND

J32-1
&
L32-1

] 10

DIP/SOIC
TOP VIEW

29 [

As

28 [

Ag

27 [

All

26 [:

NC

25 [

DE

24 [

AlO

Ao
NC

]11

CS 1

] 12

1/08

1/0 1

] 13

1/07

14 15 16 17 18 19 20

nnnnnnn

LOGIC SYMBOL
LCC/PLCC
TOP VIEW

1/0 1
1/02
1/03

,1104
1/05
I/Oe

1/0 7
1/08

PIN NAMES

~

Write Enable

OSl

AO-12

Address

WE

CS 2

1/01-8

Data InpuVOutput

OE

Output Enable

OE

CS1, CS2

Chip Select

GND

Ground

WE

RESET

Memory Reset

Vee

Power

ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

. Temperature
Under Bias

-55 to +125

-65 to +135

°C

Tsm

Storage
Temperature

PT
lOUT

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

-55 to +125

-65 to +150

°C

Power Dissipation

1.0

1.0

W

DC Output Current

50

50

mA

PARAMETER

MIN.

TYP.

MAX•

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage (1)

VIHR

RESET Input High
Voltage

UNIT

2.2

-

6.0

V

2.5(2)

-

6.0

V

-0.5(3)
Input Low Voltage
0.8
V
VIL
NOTES:
1. All inputs except RESET.
2. When using bipolar devices to drive the RESET input, a pullup resistor
of 1k!1-10k!1 is usually required to assure this voltage.
3. VIL (min.) = -3.0V for pulse width less than 20ns.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

4-197

IDT7165S/IDT7165L CMOS STATIC RAM'64K (aKx a-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE

Military
Commercial

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND

OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V ± 10%

Vee

4-198

.----_.----------------------------------------------------------------------------

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7165S/IDT7165L CMOS STATIC RAM 64K (aK x a-BIT)

DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V ±10%
SYMBOL

TEST CONDITIONS

PARAMETER

MIN.

Ilu l

Input Leakage Current

Vee = Max .• VIN

= GND to Vce

MIL.
COM·L.

IILOI

Output Leakage Current

"CS" = VIH • VOUT = GND to Vce

MIL.
COM·L.

VOL

Output Low Voltage

VOH

Output High Voltage

Vee = Max.
IOL
IOL
10H

IDT7165S
IDT7165L
TYP.(1)
MAX. MIN. TYP.(l) MAX.

-

= 10mA, Vce = Min.
= SmA, Vee = Min.
= -4mA, Vce = Min.

2.4

-

10
5

-

10
5

-

UNIT

-

5
2

J.1.A

-

5
2

J.1.A

0.5

-

0.5

V

0.4

-

-

0.4

V

-

2.4

-

-

V

-

NOTE:
1. Typical limits are at Vee = 5.0V, + 25°C ambient.

DC ELECTRICAL CHARACTERISTICS (1)
Vce = 5.0V ±10%, VLC = 0.2V, VHe = Vee -0.2V
I DT7165S/L30
COM'L.
MIL.

1DT7165S/L35
IDT7165S/L45
IDT7165S/L55
COM'L.
MIL. COM'L.
MIL COM'L
MIL

SYMBOL

PARAMETER

POWER
S

90

-

90

100

90

100

90

100

ICCI (2)

Operating Power Supply Current
Outputs Open,
Vee = Max., f = 0

L

SO

SO

90

SO

90

SO

90

Dynamic Operating Current
Outputs Open,
Vee = Max., f = fMAX

S

160

-

150

160

150

160

150

160

L

140

-

130

140

120

130

115

125

S

20

-

20

20

20

20

20

20

L

3

-

3

5

3

5

3

5

S

15

-

15

20

15

20

15

20

L

0.2

-

0.2

1

0.2

1

0.2

1

lee2(2)

Standby Power Supply Current
(TTL Level) CS 1 ~ \o\H,
CS 2 S\o\L, and RESET ~ \o\H
\te = Max., Outputs Open

19B

Full Standby Power Supply
Current (CMOS Level)
CS2 S VLe and RESET ~ VHe •
Vee = Max.

ISBI

UNIT

mA

mA

mA

mA

NOTES:
1. All values are maximum guaranteed values.
2. CS2 = \o\H

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLe = 02V VHe = Vee - 02V
SYMBOL
VDR

PARAMETER

Data Retention Current

t CDR (3)

Chip Deselect to Data Retention Time

t

Operation Recovery Time

R

lIu l (3)

MIN.

-

Vee for Data Retention

IceDR

(3)

TEST CONDITION

CS 2 S VLC and
RESET

2.0

I MIL.
I COM'L.

~VHC

NOTES:
1. TA = +25°C
2. t Re = Read Cycle Time
3. This parameter is guaranteed but not tested.

4-199

-

:-

300
90

-

10

15

-

10

15

60

RC

-

Input Leakage Current

-

MAX.
Vee@
2.0V
3.0V

200

0
t

TYP.(1)
Vee@
2.0V
3.0V

(2)

UNIT
V
J.1.A

-

-

-

-

ns

-

2

J.1.A

ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT7165S/IDT7165L CMOS STATIC RAM 64K (SK x S-BIT)

LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE

AC TEST CONDITIONS

VOR 2!: 2V

vcc

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

tR
VOR
CS 1

5V

DATA OUT

~

255!1

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2

5V

480n
DATA OUT
30pF*

~

255!1

48on
5pF*

Figure 2. Output Load
(for tCU1, t CU2 • tou, t CHZ1 , t cHz2,
tOHZ, tow,tWHV

Figure 1. Output Load

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS (\bc
SYMBOL

= 5.0V ±10%. All Temperature Ranges)

1DT7165S30 (1)
1DT7165L30 (1)
MIN.
MAX.

PARAMETER

IDT7165S35
IDT7165L35
MIN.
MAX.

IDT7165S45
IDT7165L45
MIN.
MAX.

IDT7165S55
1DT7165L55
MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

30

-

35

-

45

-

·55

-

tM

Address Access Time

30

ns

25

30

ns

35

40

45

-

55

-

-

45

Chip Select-1 Access Time (2)

-

35

t ACSl

-

55

ns

0

-

0

-

0

-

0

-

ns

15

20

ns

t Acs2

Chip Select-2 Access Time (2)

tCLZl

Chip Select-1 to Output in Low Z

tcLZ2

Chip Select-2 to Output in Low Z (3)

5

-

5

-

5

-

5

-

ns

tOE

Output Enable to Output Valid

-

15

-

20

-

25

-

30

ns

toLZ
t CHZ1

Output Enable to Output in Low Z

0

-

0

-

0

-

0

-

ns

Chip Select-1 to Output in High Z (3)

15

ns

15

25

ns

Output Disable to Output in High Z (3)

-

15

-

15

-

25

tOHZ

-

20

Chip Select-2 to Output in High Z (3)

-

15

tCHZ2

-

25

ns

tOH

Output Hold from Address Change

5

-

5

5

5

Chip Select to Power Up Time (3)

0

0

-

ns

tpu

-

tpD

Chip Select to Power Down Time

-

45

-

55

ns

(3)

(3)

(3)

15

0

-

0

-

-

30

-

35

NOTES:
1. O°Cto +70°C temperature range only.
2. Both chip selects must be active for the device to be selected.
3. This parameter is guaranteed but not tested.

4-200

20
20

ns

IDT7165SjlDT7165L CMOS STATIC RAM 64K (SK x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1

(1)

ADDRESS

""-011.00""""_---- t

ACS2

----+--.1

,_~~~~-- t CLZ2 ( 5 ) - - - - . 1
CS 1

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.2

(1,2,4)

ADDRESS

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.3

(1,3,4)

DATA OUT

'tcSupply
Current
NOTES:

1. WE is High for Read Cycle.
2. Device is continuously selected, ~1 = VIL, CS2 = VIH •
3. Addresses valid prior to or coincident with ~1 transition low and CS2 transition high.,

4. O'E= VIL
5. Transition is measured ±200mV from steady state.

4-201

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7165S/IDT7165L CMOS STATIC RAM 64K (SKx S-BIT)

AC ELECTRICAL CHARACTERISTICS
PARAMETER

SYMBOL

(Vee = 5.0V ±10%. All Temperature Ranges)

IDT7165S30 (1)
IDT7165L30 (1)
MIN.
MAX.

IDT7165S35
IDT7165L35
MIN.
MAX.

IDT7165S45
IDT7165L45
MAX.
MIN.

IDT7165S55
1DT7165L55
MIN.
MAX.

UNIT

WRITE CYCLE
twe

Write Cycle Time

30

tew1

Chip Select-1 to End of Write

20

tew2

Chip Select-2 to End of Write

25

tAw
t AS

Address Valid to End of Write

25

Address Setup Time

0

twp

Write Pulse Width

25

tWR1

Write Recovery Time (CS 1. WE)

0

tWR2
tWHZ

Write Recovery Time (CS 2)
Write Enable to Output In High Z (2)

tDW

Data to Write Time Overlap

13

-

-

25

-

30

-

40

-

50

30

-

40

50

50

0
5

-

35

0
30

45

0
40

ns

0

-

5

-

ns

30

0

ns
ns
ns

ns
ns

0

5

-

5

-

-

12

-

15

-

20

-

25

ns

15

20

-

25

-

ns

3

5

-

5

-

5

-

ns

5

-

tDH1

Data Hold From Write Time (CS 1)

3

tDH2

Data Hold From Write Time (CS 2)
Output Active from End of Write (2)

5

-

5

-

tow

-

55

20

3

NOTES:
1. O°C to + 70°C temperature range only.
2. This parameter is guaranteed but not tested.

4-202

3
5
"

5

ns

ns
ns

I DT7165S/1 DT7165L CMOS STATIC RAM 64K (SK x a-BIT)

TIMING WAVEFORM OF WRITE CYCLE NO.1

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(1)

~--------------------twc------------------~
--------~

ADDRESS

,------------

14---------- tcw --------~
1.------------------ tAW --------------~

DATAoUT

<1L.

VALID DATA IN

~

(1,6)

TIMING WAVEFORM OFWRITE CYCLE NO.2
14---------------------twc--------------------~

ADDRESS

DATA OUT

NOTES:

1.
2.
3.
4.
5.
6.
7.
8.
9.

WE must be high during all address transitions.
A write occurs during the overlap (tw~ of a low WE, a low CS 1 and a high CS 2 .
t WR1 •2 is measured from the earlier of CSl or WE going high or CS 2 going low to the end of the write cycle.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
If the CS 1 low transition or CS 2 high transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a
high impedance state.
OE is continuously low (OE = V 1l ).
DATAoUT is the same phase of write data of this write cycle.
If CS"1 is low and CS 2 is high during this period, I/O pins are in the output state. Data input signals of opposite phase to the outputs
.
must not be applied to them.
Transition is measured ±200mV from steady state.

4-203

IDT7165S/IDT7165L CMOS STATIC RAM 64K (SK x S-BIT)

AC ELECTRICAL CHARACTERISTICS
\
PARAMETER

SYMBOL\

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(Vcc = 5.0V ±10%, All Temperature Ranges)

IDT7165S30(1)
IDT7165L30 (1)
MAX.
MIN.

IDT7165S35
\
IDT7165S45
\
IDT7165S55
IDT7165L35
IDT7165L45
IDT7165L55
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.

I

UNIT

RESET
t RSPW
t RsRC

I Reset Pulse Width (2)
I Reset High to WE Low

I

J

55

-

65

5

-

5

- I
- I

- I
- I

80
10

- I
- I

100
10

ns
ns

NOTES:
1. O°C to + 70°C temperature range only.
2. Recommended duty cycle = 10% maximum.

RESET TIMING

fl4---_

-_-_tRS_PW-=--_-_--+I

~
CAPACITANCE
SYMBOL
CIN
COUT

xXXXXxxXXxxxxxxXXXXXY
TRUTH TABLE

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance
Output Capacitance

CONDITIONS
VIN = OV

MAX

UNIT

8

pF

(VLC = 0.2V, VHC = Vcc - 0.2V)
CS 2

OE

RESET

1/0

X

X

X

X

L

-

Reset all bits to low

X

H

X

X

H

Z

Deselect chip

X

X

L

X

H

Z

Deselect power down(1)

X

VHC

X

X

H

Z

Deselect chip

X

X

VLC

X

VHC

Z

CMOS deselect
power down (1)

H

L

H

H

H

Z

Output disable

H

L

H

L

H

DoUT

Read

L

L

H

X

H

DIN

Write

WE

VOUT= OV

8
pF
NOTE:
1. This parameter is determined by device characterization, but is not production tested.

CS 1

FUNCTION

NOTE:
1. CS 2 will power down CS 1, but CS1 will not power down CS2.

+5 Volts

IDT7165

IDT7165

CMOS Gate

Bipolar Gate

Driving the RESET pin with CMOS logic.

Driving the RESET pin with bipolar logic.

Figure 3.

4-204

IDT7165Sj1DT7165L CMOS STATIC RAM 64K (SK x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxxx

A

999

A

A

Device Type

Power

Speed

Package

Process/
Temperature
Range

y:""k
P

Commercial (O°C to

+70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B.
Method 5004

J
L

Plastic DIP
THINDIP (Sidebraze)
CERDIP
Small Outline IC
Plastic Leaded Chip Carrier
Leadless Chip Carrier

30

Commercial Only }

TC

~--------------~ ~O

~------------------------i ~~

Speed in Nanoseconds

55
~-------------------------------i

L

S

' - - - - - - - - - - - - - - - - - - 1 7165

4-205

Low Power
Standard Power

64K (8K x 8-Bit) Static RAM

FEATURES:

DESCRIPTION:

• Input and output directly CMOS-compatible

The IDT71C65 is a 65,536-bit high-speed static RAM organized
as 8K x 8. Inputs and outputs are compatible with industry standard CMOS Input and output voltage levels.
This product is fabricated using IDT's high-performance, highreliability CEMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides a
cost-effective alternative to bipolar and fast NMOS memories. An
address access time of 30ns and a chipselect(CS 1) tlmeof 15ns
are available with typical power consumption of only 250mW. This
circuit also offers a reduced power standby mode. In the full
standby mode, the low-power device consumes less than 30~W
typically. The low-power (L) version also offers a battery backup
data retention capability where the circuit typically consumes only
80~W operation off a 2V battery.
All inputs and outputs of the IDT71C65 are CMOS-compatible
and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no
clocks or refreshing for operation, and providing equal access and
cycle times for ease of use.
The IDT71C65 is packaged in a 28-pin, 300 mil THINDIP; 600
mil plastiC DIP; a 32-pin LCC and a 28-pin SOIC, providing high
board level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• High-speed (equal access and cycle time)
- Military: 35/45/55ns (max.)
- Commercial: 30/35/45ns (max.)
• Low-power operation
- IDT71C65S
Active: 300mW (typ.)
Standby: 100I-lW (typ.)
- IDT71C65L
Active: 250mW (typ.)
Standby: 30I-lW (typ.)
• Battery backup operation-2V data retention (L version only)
• Produced with advanced CEMOS TM high-performance
technology
• Single 5V(±10%) power supply
• Static operation: no clocks or refresh required
• Available in standard 28-pin, 300 mil THINDIP; 28-pin, 600 mil
plastic DIP; 28-pin SOIC and 32-pin LCC
• Three-state outputs
• Military product compliant to MIL-STD-883, Class B

LOGIC SYMBOL

FUNCTIONAL BLOCK DIAGRAM

DECODER

•

256 x 256

MEMORY ARRAY

Vee

GND

liESET - - - - - 0
1/0 1- 8 ~t---,~---I ~-----..,"

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology, Inc.

4-206

DECEMBER 1987
OSC-l0ll/-

------ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

IDT11C65S/IDT11C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE 1/0 64K (SK x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
~
A12

Vee

A7
As

CSz

INDEX

~

UUUIIUULJ
3 2 U 32 31 30

Aa

1

A9
All

A5
A4
A3
A2
Al
Ao

C5E"

29 [:

Aa

2a [:

A9

27 [:

All

C

NC

26

AlO
L32-1

~1
I/O a

C5E"
C A10

25 [:

24

1/0 1
1/0 2
1/0 3

1/0 7

23 [:

~1

I/0 s

22 [:

1/0 5

21 [:

I/0a
1/0 7

GND

1/0 4

14 15 lS 17 la 19 20

nnnnnnn

DIP/SOIC
TOP VIEW
LCC
TOP VIEW

CAPACITANCE
SYMBOL

PIN NAMES

(TA= +25°C f = 10MHz)

PARAMETER(l)

CONDITIONS

MAX.-

UNIT

8
pF
Input Capacitance
VIN = OV
CIN
,COUT
8
pF
Output Capacitance
VOUT= OV
NOTE.
1. This parameter is determined by device characterization but is not
production tested.

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

VTERM

Terminal Voltage
with Respect to
GND(2)

TA

Operating
Temperature

-0.5 to +7.0

Oto +70

Address

N

1/01- I/0a

Data InpuVOutput

l1ESET(1)

Memory Reset

CSl, CS2

Chip Select

GND

Ground

Output Enable

wr=.

Power
Write Enable
\tc
NOTE:
1. A 1Kn pull-up resistor on the ~ input is required for added
noise immunity.
.

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL

Ao - A12

MILITARY
-0.5 to +7.0

-55 to +125

UNIT
V

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

rnA

MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

"IH

Input High Voltage

70% of vee

"IL

Input Low Voltage

-0.5(1)

-

PARAMETER

SYMBOL

5.5(2)

V-

30% of vee

V

NOTES:
1. VIL (min.) = -3.0V for pulse width less than 20ns.
2. If VIH = 5.5V, Vee = 4.5V, there is risk of latch up.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. All inputs and Vce pin. Data pins I/~ - I/0a must not be taken above
Vec + 1.0V.

GRADE
Military
Commercial

4-207

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V ± 10%

O°C to +70°C

OV

5.0V ± 10%

Vee

1DT71C65S/IDT71C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE I/O 64K (8K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Vee = 50V +10%
SYMBOL
Ilu l

IlLOI

PARAMETER

TEST CONDITIONS
Vee =' Max., V1N

Input Leakage Current

10L

Output Low Voltage

IOL

10H

Output High Voltage

IOH

IDT71C65L
IDT71C65S
MAX. MIN.
MAX.

-

10
5

-

-

J.1A

5
2

J.1A

0.5

4.4

-

4.4

COM'l.

3.7

-

3.7

-

MIl.

3.S

-

3.S

-

MIl.
COM'L.

10
5
0.1
0.44

,

UNIT

5
2

-

MIl.
COM'l.

= GND to VCC
= SOpA, Vee = Min.
= SmA, Vee = Min.
= 10mA, Vee = Min.
= -SOpA, \be = 4.5V
= -SmA, \be = 4.5V
= -6mA, \be = 4.5V

CS" 1

10H
VOH

MIl.
COM'L.

= GND to Vee

Vee = Max.
= "'IH , VOUT

Output Leakage Current

10L
VOL

MIN.

0.1

V

0.44

V

0.5

V
V

V

V

DC ELECTRICAL CHARACTERISTICS
Vee

= 5.0V ±10%, VLC = O.2V, VHC = Vee -O.2V, V1H = Vcc-O.SV, "'IL = O.SV

SYMBOL

PARAMETER

POWER

IDT71C65S30
IDT71C65L30
COM'L
MIL

5

-

5

20

15

20

-

20

1

0.2

1

-

1

170

160

170

125

135

115

125

S

20

-

20

20

20

L

3

-

3

5

S

15

-

15

L

0.2

-

0.2

95

L

S5

lec2(2)

Dynamic Operating Current
Outputs Open; Vee = Max., f

S

160

L

ISB

Standby Power Supply Current
1) CS 2 S"'IL, and ~~"'IH,f = fMA)«3)
2) CS"1 ~ "'IH,VCC = Max., Outputs Open,
CS2 ~ "'IH' f = f MAX(3), ~ ~ "'IH
Full Standby Power Supply Current
1) CS 2 SVLC , ~~VHc,1 = 0(3)
2) CS"1 ~ VHC ' CS2 ~ VHC , ~ ~ VHC
f = 0(3)

3

160

135

S

ISBl

105

20

-

-

lecl(2)

Operating Power Supply Current
Vce = Max., f = 0(3)

= f MAX (3)

IDT71C65S35
IDT71C65S45
I DT71C65S55
IDT71C65L45
I DT71C65L35
I DT71C65L55
COM'L
MIL COM'L
MIL. COM'L
MIL
95

105

95

105

85

95

85

95

UNIT
rnA

95
170

rnA

120
20
rnA

rnA

NOTES:
1. All values are maximum guaranteed values.
2. CS 2 = "'IH' CS"1 = "'IL
3. At fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.

4-208

- - - _ .. _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

1DT71C65S/IDT71C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE I/O 64K (8K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = Vcc - 0.2V
TYP.(l)
SYMBOL
VOR
ICCDR

TEST CONDITION

PARAMETER

-

Vcc for Data Retention
Data Retention Current
1)

tCOR

Chip Deselect to Data Retention Time

tR

Operation Recovery Time

IILlI

Input Leakage Current(3)

RESrr~VHC,CS1~VHC'

CS 2 ~ VHC
2) CS2 ~ VLC '

RESET ~

MIN.

I
I

V cc @
2.0V
3.0V

MAX.
V cc @
2.0V
3.0V

2.0

-

-

-

-

MIL.

-

10

15

200

300

COM'L.

-

10

15

60

90

-

-

-

ns

-

-

ns

VHC

0

-

t RC (2)

-

-

-

LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VOR ~ 2V

VDR
1
-"'----'-'

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDtoVcc
Sns
2.SV
2.SV
See Figures 1 and 2

---1

SV

DATAour
30pF*

Figure

jSPF*

Figure 2. Output Load
(for t cLZ1 , t CLZ2, tOLZ, t CHZ1, t CHZ2,
t OHZ, tOW,tWHV

1. Output Load

* Including scope and jig.

4-209

V

jlA

NOTES:
1. TA = +2SoC
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.
4. During data retention all I/O pins have to be ~ VLC or ~ VHC but ~ Vcc.

CS

UNIT

2

jlA

1DT71C65S/IDT71C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE 1/0 64K (SK x a-BIT)

AC ELECTRICAL CHARACTERISTICS (\Cc

= 5V ±10%; All Temperature Ranges)

IDT71C65S30(1)
IDT71C65L30(1)
MIN.
MAX.

PARAMETER

SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT71 C65S35
IDT71C65L35
MIN.
MAX.

IDT71C65S45
IDT71C65L45
MAX.
MIN.

IDT71 C65S55(4)
I DT71 C65L55(4)
MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

30

-

35

-

45

-

55

-

tAA

Address Access Time

-

30

-

35

-

45

55

ns

t Acs1

Chip Select 1 Access Time (2)

20

-

35

40

ns

Chip Select 2 Access Time (2)

-

25

t AcS2

-

40

-

45

-

55

ns

tCLZ1

Chip Select 1 to Output in Low Z (3)

0

0

-

0

5

5

-

5

5

-

ns

Chip Select 2 to Output in Low Z (3)

-

0

tCLZ2

-

tOE

Output Enable to Output Valid

-

20

-

25

-

35

-

40

ns

tOLZ

Output Enable to Output in Low Z (3)

0

-

0

-

0

-

0

-

ns

t CHZ1

Chip Select 1 to Output in High Z (3)

15

-

30

ns

20

-

25

Chip Select 2 to Output in High Z (3)

25

-

30

ns

tOHZ

Output Disable to Output in High

-

20

tCHZ2

-

20

-

25

-

30

ns

tOH

Output Hold from Address Change

5

5

-

5

0

0

0

-

0

-

ns

Chip Select to Power Up Time (3)

-

5

t pu

-

t pD

Chip Deselect to Power Down Time (3)

-

30

-

35

-

45

-

55

ns

Z(3)

35

15
15

NOTES:
1. O°C to + 70°C temperature range only.
2. Both chip selects must be active for the device to be selected.
3. This parameter is guaranteed but not tested.
4. -55°C to + 125°C temperature range only.

4-210

ns

ns

ns

IDT71C65S/IDT71C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE I/O 64K (SK x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1
ADDRESS

(1)

~

tRc

_____________________________________________

1oI~1_------- tM

.. '

1 + - - - - - tOE

tOLZ (5) - - - . . !

~'-""--"'-'

14------ t ACS2 - - - t - - . - j

\+----- t CLZ2 ( 5 ) - - - - . j
14------ t ACS1

----t--.-j

1 + - - - - - tCLZl (5) _ _ _-..!

DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)

ADDRESS

~--------------------f=~
_ __

~

tRC

_tM_-_-~~-.,-2~·'

: - - tOH

DATA OUT

'OH

-l

~~~---------~)K~----

TIMING WAVEFORM OF READ CYCLE NO.

3(1,3,4)

~~

/'r£
~~

~""

t Acs2
t cLZ2 ( 5 ) -

~

t ACS1
t cLZ1 (5)

I--- t CHZ1 ( 5 ) -

t pu
f+--t pu

CURRENT

Icc
IS6

"

K20CK

DATAoUT

-------------

/~

./
t

NOTES:
1.
is High for Read Cycle.
2. Device is continuously selected, CS 1 = V'L' CS 2 = V'H'
3. Address valid prior to or coincident with CS 1 transition low and CS 2 transition high.
4. DE" = \'IL
5. Transition is measured ±200mV from steady state.

wr:.

4-211

_
po

i - - t po -

~""

~

t

CHZ2

(5)

IDT71C65S/IDT71C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE 1/0 64K (SK x S-BIT)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(VCC = 5V ±10%, All Temperature Ranges)

IDT71 C65S30 (1)
IDT71C65l30 (1)
MAX.
MIN.

PARAMETER

1DT71 C65S35
1DT71C65L35
MAX.
MIN.

IDT71C65S45
IDT71C65L45
MIN.
MAX.

IDT71 C65S55 (2)
IDT71C65L55 (2)
MIN.
MAX.

UNIT

WRITE CYCLE

t AS

Address Set-up Time

0

twp

Write Pulse Width

25

tWR1

Write Recovery Time (~1,

tWR2

Write Recovery Time (CS 2)

0

-

-

0

tWHZ

Write Enable to Output In High Z (3)

-

10

-

12

-

tDW

Data to Write Time Overlap

15

18

-

tDH1

Data Hold From Write Time (~1 ' WE)

0

-

0

tDH2

Data Hold From Write Time (CS 2 )

5

-

5

tow

Output Active from End of Write (3)

5

-

5

twc

Write Cycle Time

30

tCW1

Chip Select 1 to End of Write

20

tCW2

Chip Select 2 to End of Write

25

tAW

Address Valid to End of Write

25

WE)

0

25

30

-

30

-

40

0

-

40

35
20

30

a
a

NOTES:
1. ODC to + 70 DC temperature range only.
2. -55 DC to + 125 DC temperature range only.
3. This parameter is guaranteed but not tested.

4-212

50

-

ns

-

a
a

15

-

20

ns

25

-

30

ns

-

0

-

0

-

5

-

5

-

5

-

ns

45

40

a
0

5

-

55
30

50
50
0

ns
ns
ns
ns
ns
ns

ns

ns
ns

IDT71 C65S/IDT71 C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE 1/0 64K (aK x a-BIT)

TIMING WAVEFORM OF WRITE CYCLE NO.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1(1)

~------------------twc------------------~

ADDRESS

DATAoUT

TIMING WAVEFORM OF WRITE CYCLE NO.

2(1,6)

~----------------twc----------------~

ADDRESS

14------- tcw

------'*-.......

DATAoUT

NOTES:
1.
must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS 1and a high CS 2.
3. t WR1 •2 is measured from the earlier of CS1 or
going high or CS 2 going low to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CSl low transition or CS2 high transition occurs simultaneouslywith the WE low transitions or after the
transition, outputs remain in a high
impedance state.
6. ~ is continuously low (OE' = 'vIL)'
7. DATA OUT is the same phase of write data of this write cycle.
S. If CSl is low and CS 2 is high during this period, I/O pins are in the output state. Data input signals must not be applied.
9. Transition is measured ±200mV from steady state.

wr=.

wr=.

wr=.

4-213

IDT71 C65S/IDT71 C65L CMOS RESETTABLE
RAM WITH CMOS COMPATIBLE 1/0 64K (SK X 8-BIT)

AC ELECTRICAL CHARACTERISTICS

~YMBOLI

MILITARY AND COMMERCIALTEMPERATURE RANGES

(Vee = 5.0V ±10%, All Temperature Ranges)

11DT71C65S30(1) I IDT71C65S35 IIDT71C65S45
IIDT71C65S55(2) I
1DT71C65L30(1)
IDT71C6SL35
IDT71C65L45
IDT71C65L5S(2)
MIN.
MAX. MIN.
MAX.
MIN.
MAX.
MIN.
MAX.

PARAMETER

UNIT
;

RE§Ej(3)

t RSPW
t RSR

I

l1ESET Pulse Width(4~

I

~HightoMLow

I
I

55

- I

- I

5

- I
- I

65
5

SO
10

- I
- I

100
10

- I
- I

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. A 1KO pull-up resistor to Vee on the ~ pin is required for added noise immunity.
4.. Maximum 10% duty cycle applies.

RESET TIMING

f"--

-_-_tRS_PW--=--_-_--...

M

XXXXXXXXXXXXXXXXXXXXY

ORDERING INFORMATION
lOT

XXX)(

Device Type

A
. Power

999
Speed

A
Package

A
Process/
Temperature
Range

y:'Mk
·1

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

~C

Plastic DIP
Sidebraze THINDIP
Leadless Chip Carrier
Small Outline IC

30
35

Commercial Only }

55

Military Only

~--------------~I ~O .

Speed in Nanoseconds

~----------------------~I' 45
1

~

______________________~I S
IL

' - - - - - - - - - - - - - - - - - - 1 1 71C65

4-214

+ 70°C)

Commercial (O°C to

Standard Power
Low Power
64K (SK x 8-Bit) CMOS I/O Resettable RAM

ns
ns

FEATURES:

DESCRIPTION:

• Internal pipeline registers on Address, Data and control lines

The IDT71501 is a high-speed 64K x 1 static RAM synchronized
with pipeline r~ters on the Address, Data, Chip Select (CS) and
Write Enable (WE) pins. This product is designed to assist in the
design of pipelined processing systems by removing the need for
external pipeline registers. The internal registers offer speed improvements through higher integration of system functions.
Read .9:,cle times are as fast as 35ns, with higher speed Output
Enable (OE) and Clock to Valid Data Outputfunctions to enable the
high-speed system designer the maximum throughput possible in
an efficient large-memory pipelined system. Write cycles are as
fast as 25ns. Fabricated using lOT's CEMOS high-performance
technology, these devices typically operate on 385mW of
power.
The IDT71501 is packaged in industry standard 24-pin, 300 mil
plastic and ceramic DIPs, as well as a 28-pin leadless chip carrier
(LCC) and a 24-lead, 300 mil gullwing SOIC.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• Very fast write cycle time
• High-speed
- Military: 45ns (max.)
- Commercial: 35/45ns (max.)
• Low power consumption: 385mW (typ.)
• All inputs/outputs TTL-compatible (VOL = O.4V @ IOL = 8mA)
• Separate, latched data input and output
• Three-state output
• Available in JEDEC standard 24-pin, 300 mil Sidebraze and
Plastic DIP, 24-pin, 300 mil SOIC and 28-pin LCC
• . Produced with advanced CEMOS TM high-performance
technology
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
Vee
GND

6S,S36-BIT
MEMORY

DATAoUT

ARRAY

R/W

ClK

----~--~----~--------------------------------~--~

~ --------------~--------------------~--------------------~~
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce TechnOlogy, Inc.

DECEMBER 1987
050-1038/-

4-215

4

1DT71501 SCMOS
SYNCHRONOUS RAM 64K (64K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
00.0

INDEX

0

c(
I.

I

Z

I

~.....,

CLK
Al

Al

A2

A2
A3
A4

A3
NC

As
A6

As
A6

A7

A7

DOUT

DOUT

A4

RtW

I.

:1
:1
:1
:1
:1

......

.....,

:1
:1
:1

1

4
S

6
7

L28-2

B

9
10
11

:1 12

RATING
Terminal Voltage
with Respect to
GND

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

GRADE
Military
Commercial

Operating
Temperature

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

DC Output Current

50

50

CAPACITANCE (TA =

Input Capacitance

CONDITIONS
VIN = OV

TYP.

mA

8

o

GND

Vee

-55°C to + 125°C

OV

5.0V ± 10%

O°C to +70°C

OV

5.0V ± 10%

MIN.

TYP.

MAX.

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

-

6.0

V

VIL

Input Low Voltage

-

0.8

V

SYMBOL

PARAMETER

-0.5(1)

NOTE:
1. Vil = -3.0V for pulse width less than 20ns.

+25°C, f = 1.0MHz)

PARAMETER(l)

AMBIENT
TEMPERATURE

RECOMMENDED DC OPERATING CONDITIONS

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CIN

~
c(

I

LCC
TOP VIEW

TA

SYMBOL

0

13 14 lS 16 17

ABSOLUTE MAXIMUM RATINGS

loUT

II

oj}
I

nnnnn
DIP/SOIC
TOP VIEW

VTERM

I

32U2627

Ao

GND

SYMBOL

I

UNIT
pF

COUT
Output Capacitance
VOUT= OV
8
pF
NOTE:
1. This parameter Is determined by device characterization but is not
production tested.

4-216

UNIT

--_ _-----------------------------------------------•..

1DT71501S CMOS
SYNCHRONOUS RAM 64K (64K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (Vee =
SYMBOL

PARAMETER

5.0V±10%)
IDT71501S

TEST CONDITIONS

MIN.

Ilu l

Input Leakage Current

Vee = 5.5V,

= OV to Vee

MIL.
COM'L.

IILOI

Output Leakage Current

CS = V1H , VOUT = OV to Vcc
Vee = Max.

MIL.
COM'L.

"C'S

= V1L, Output Open
Vee = Max.

MIL.
COM'L.

Min. Duty Cycle = 100%
Vee = Max., Output Open

MIL.
COM'L.

leel

Operating Power Supply Current

ICC2

Dynamic Operating Current

VOL

Output Low Voltage

VOH

Output High Voltage

\IN

MAX.

-

10L = 10mA, Vcc = Min.

-

10L = -4mA, Vee = Min.

2.4

10L = 8mA, Vee = Min.

DATA OUT

~

2250

DATA OUT
30pF*

~

2550

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for tOLZ. to HZ)

*Ineluding scope and jig.

4-217

10
5

J..lA

140
125

mA

140
125

mA

-

5V

4800

J..lA

0.5

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2

5V

10
5

0.4

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

UNIT

V
V

IDT71501S CMOS
SYNCHRONOUS RAM 64K (64K xl-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL

PARAMETER

MIN.

IDT71501S35
MAX.

IDT71501S45

UNIT

MIN.

MAX.

45

-

ns

7

ns

7

-

5

-

ns

5

ns

0

-

READ CYCLE
tcp

Clock Period (Read Cycle Time)

35

tCH

Clock High Time

7

tCl

Clock Low Time

7

ts

Data, Address, WE, CS Set-up Time

5

tH

Data, Address, WE, CS Hold Time

5

tOLZ

Output low Z Time (1,2)

0

-

tOHZ

Output High Z Time (1, 2)

-

15

-

20

ns

tpvo

Prop. Delay, ClK to Valid Data Out

13

18

Clock to Output in Low Z (2)

0

0

-

ns

tCOl

-

-

25

ns

Clock to Output In High Z (2)
20
tCOH
NOTES:
1. Transition Is measured ±200mV from low or high Impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.

TIMING WAVEFORM OF READ CYCLE

ns

ns

ns

(1)

tcp----------------~

1 4 - - - - tCH ----~----

tCl---~

ClK

ADDRESS,

cg

DATA VALID
ADDRESSZ

~--------tCOH---+---~

tPVD

DATAoLrr

DATA FROM
ADDRESS X

DATA FROM
ADDRESSY

NOTE:

1. The device must be selected by a CS level for the conditions above to take place.

4-218

DATA FROM
ADDRESSZ

IOT71501S CMOS
SYNCHRONOUS RAM 64K (64K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL

IOT71501S35

PARAMETER

MIN.

10T71501S45
MAX.

MIN.

MAX.

UNIT

WRITE CYCLE
tcp

Clock Period (Write Cycle Time)

25

-

35

-

ns

tCH

Clock High Time

7

7

-

ns

tCl

Clock low Time

7

-

7

ts

Data, Address, WE, CS Set-up Time

5

-

5

ns

tH

Data, Address, WE, CS Hold Time

5

-

5

-

TIMING WAVEFORM OF WRITE CYCLE

tcp
~---

-------.....-.j

tCH ---~----

ClK

ADDRESS,
DATA IN

CSor

WE" (1)

NOTES:
1. Either CS or WE" can be used to trigger a write cycle, provided that the other signal is low at the same time.
2. When a write is terminated, either CS or WE" must become high at least one ts before the next rising edge of ClK. .

TRUTH TABLE
MODE

A O- 15

Read

ADDR

Write

INPUT BEFORE ClKS
CS
WE
OE
DIN
l

X

H

l

AFTERClKS
Dour
Data

ADDR

l

Data

l

X

HighZ

Deselect

X

H

X

X

X

High Z

Disable

X

X

X

X

H

High Z

4-219

ns

ns

1DT71501S CMOS
SYNCHRONOUS RAM 64K (64K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XXXX

A

999

A

A

Device Type

Power

Speed

Package

Process!
Temperature
Range

y:Mk

1.----------1,16~o
'--_ _ _ _ _ _ _ _ _---1135

Commercial (O°C to

Military (-55°C to + 125°C)
Compliant to MIL-SID-883, Class B

Plastic DIP
Sidebraze DIP
Small Outline IC
LCC
Commercial Only }

145
~------------------------------~S
~--------------------------------------__I

4-220

71501

+ 70°C)

.
Speed In Nanoseconds

Standard Power
64K (64K x 1-Bit) CMOS Synchronous RAM

clock enables, as well as address and data inputs, must meet the
appropriate set-up and hold times with respect to the clock.
The eight data output bits are enabled when the output enable is
low and are in the high-impedance state when the output enable is
high. The chip select and write enable signals are also registered in
o flip-flops. These two flip-flops are loaded with new data on each
• 8-bit synchronous data input
low-to-high transition of the clock. The chip select is passed di• Synchronous chip select and write enable
rectly from the Q output of the D-type flip-flop to the 64K x 8 RAM.
The write enable signal isgated with the clock signal to generate a
• Separate clock enable for each register
delayed write enable pul~eHQ.essence, this gives the output of the
• Low standby power
address register time 19. sert,I.~and internally select the appropriate
• Onboard decoupling capacitors
byte of RAM before th\ilVvfi.tEninable goes low to write new data into
the RAM. Thus, toe low-to'-high transition of the clock causes the
• Available in 43-pin SIP (single in-line package) configuration
chip select and ..~ri~~.~nable flip-flops to be loaded with new data
• 2 Ground and 2 Vee pins
and immediatelideselects a previous write by means of the clock
going high,Jll~>pa!a lines to the RAM and the address lines to the
DESCRIPTION:
RAM may inpeep change to new values based on the low-to-high
transitign.9.f tbe clock. When the clock goes from high-to-Iow, if the
The IDT7MP6025 is a 64K x 8 synchronous RAM with edge trigchip~~I~cti$.IOW and the write enable is low, a write cycle is begun
gered registers on the address lines, data-in bus, data-out bus,
anp t~e $.!a at the RAM data inputs will be written into the selected
chip select and write enable. The edge triggered register of the 16
aPdre~. I(the write enable is high or the chip enable is high, data
address lines features an independent clock enable that allows the
,.yviU~C?~.be written into the memory.
address register to be selectively loaded. The address register will
,'~i ';,:;.,'
of the features of this configuration of memory that have
be loaded on the low-to-high transition of the clock when the clock
enable line is low and will hold its current contents on the 10w-tO-...\:,:"·''<:.fE3l;Jisters on all of the address lines, data input lines and data output
high transition of the clock when the clock enable is high. Similarly,'·';~:;•. :::~Jines as well as the control lines, is to provide the highest possible
the 8-bit data-in register will be loaded with new data on the low-to-"·'·'·:.; .,3,:,Clock rate in the system. All that is necessary is that the data, adhigh transition of the clock when the data-in clock enable is'''9~ ",~, dress, chip select, write enable and clock enables signals meet the
required set-up and hold time with respect to the clock. In this
and will hold its contents when the data-in clock enable is higtirTh~':\
manner, fully asynchronous operation is achieved. The
data-out register will receive new data from the 64K x 8 RJ\fvfW!)~r:I/
IDT7MP6025 is offered as a compact, cost-effective 43-pin plastiC
the clock enable line is low and will hold its data whel1;J~. ~iock
SIP module.
enable line is high at the low-to-high transition of the 'clOCk: All

FEATURES:

• 64K x 8 fully synchronous memory
• High-speed-20MHz read cycle time
• 16-bit synchronous address input

Qne

FUNCTIONAL BLOCK DIAGRAM

~15}

J---~~"'-----------+I

ADDRESS

Ao

64Kx8
RAM

~----------~cs

DATA OUT

8

CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated DevIce Technology. Inc.

DSC-70221-

4-221

D
,.4
...

different address. This allows systems to be built that can perform
fast Fourier Transforms in either a decimation-in-time or a decimation-in-frequency configuration. Data read from Memory 1 can be
synchronously loaded into its output register, while data can be
written into a different location in Memory 2. Similarly, data can be
read from Memory 1 and Memory 2 in parallel from two different
addresses and can be written into Memory 1 and Memory 2 at
unique addresses. Registers at the data input and data output provide fully synchronous pipelined operation. The, two memory systems are 20 bits wide and have multiplexed data input and data
output bits from the modul~ ~ata pins. By taking advantage of the
speed of the registers, data on~l1e pins can run at a speed twice that
of the memory. That is;t>othoutput registers can be read or both
input registers can be'loaqed in a single memory cycle.
•
Two address s~rces are available to each address register to
the RAM. Addr~sS6tJrce A or Address Source B may be selected
to load the e9g~triggered register for the 16K x 20-bit memory. The
•
IDT54/74FCT399jsused for the two input multiplexer and address
•
registe~:fdr~.~9h::
16K x 20 memory. All inputs and outputs of the
i
•
IDT7M4017;·are TTL-compatible and operate from a single 5V
supply::;:.::" ':""i;::'
. .;p1e iDnM6oo1 is offered as a compact 92-pin quad in-line
DESCRIPTION:
(QIP) ~ramic module. It is constructed using ceramic LCC comThe IDT7M6001 is a dual multiplexed 16K x 20 synchronous::I::::'P9neotS on a multilayer co-fired ceramic substrate and occupies
RAM module. It utilizes ten IDT71981 high-speed synchronous.(.::::i?r1,IYA.2 square inches of board space.
memories, along with the appropriate Input data, output data and ,i·:r:::;,":":e,,,:.'::;:;:,::AIIIDT military module semiconductor components are compliaddress registers. The device features the ability to be used in a\\\::<·')'~nt to the latest revision of MIL-STD-883, Class B, making them
ping-pong mode. That is, data can be loaded into one memory ar- "\,:::,:> ideally suited to applications demanding the highest level of
ray at one address and be read from the other memory arra~,;'af'ai"\
performance and reliability.

FEATURES:
•
•
•
•
•
•
•
•
•

Dual 16K x 20 synchronous RAM
Edge triggered data input and data output registers
Edge triggered data address registers
Two address register sources individually selectable
Separate chip select and write enables to each memory array
Individual clock lines to each register
Dual high-performance 16K x 20 memories
Unique ping-pong operation capability
Assembled with IDT's high-reliability vapor phase solder reflow
process
Available in compact 92-pin ceramic sidebraze alP (quad
in-line) package
Single 5V (±10%) power supply
Inputs and outputs directly TTL-compatible
Military modules available with semiconductor components
compliant to MIL-STD-883, Class B

REG

REG
D10-19

-=';'£-",-,--1

CKl 1

D

D°0-19

CP

01:1

cr1

CKO l

WE"1
DI
~

WE"

16K x 20
RAM
A

REG
DO 1--..;;;;27'0' - - - - - - t D
CP

Q

20

or:

or:2

14

CKI 2 - - - - i CP

CK0 2

cr2
WE"2
Q

ACK 2 - - - - - - I C P

Q

REG

D

REG

D

CP~-----

ACK l

Q

S2

------1

A

MUX

ADAo-13

~-----Sl

B

ADBo-13

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 19B7 Integrated DevIce Technology. Inc.

4-222

DECEMBER 1987
DSC-7028/-

DESCRIPTION:

FEATURES:

The IDT7M824 family is a set of 1024K-bit (128K x 8-bit) highspeed CMOS static RAM modules with registered/buffered/
latched addresses and I/Os. They are constructed on co-fired,
multi-layered ceramic substrates with sidebrazed leads using
16 IDT71981 (16K x 4) static RAMs, IDT logic devices and decoupiing capacitors. Devices in leadless chip carriers are mounted top
and bottom for maximum density.
20MHz read cycle time
Extremely high speeds are achievable by the use of IDT71981s
Low power consumption (typ.)
and logic devices fabri9f1t~,~ in IDT's high-performance, high- Active: 1.SW
reliability CEMOS ™ te9hn619Qy. This state-of-the-art technology,
- Standby: 7SmW
combined with innovatlvEildrcuit design techniques, provides the
Low input capacitance (typ.): input 20pF; output 2SpF
fastest circuits P9~sible:'The IDT7M824 has registered access
times of SOns (rnaX;},C;lVer the commercial temperature range and
High output drive (min.): 10L = 48mW; 10H = -1SmA
can be operateclWith:cycle times as fast as 20M Hz.
Available in 64-pin, 900 mil centre sidebraze DIP (with LCCs
Designi~gw't~tQis device can be very flexible because of such
on both sides), achieving very high memory density
features ~s,,~odHle select output and clock enables on all regisModule select output
ters, reg!S!E3fEKtwrite enable and 8-bit separate inputs and outputs.
Separate inputs and outputs
Becal.!S~ of"U1e proprietary IDT49C801, the modules are casca~~ble-'Jfl)ermS of depth with no additional external decoding.
Clear data and clock enables on all registers
T}1ewri!e enable can be turned off when the module is deselected.
Address, Input and outputs on separate clocks or latch
,,!nim~fl!jy to noise has been extended with such features as 8-bit
enables
i!;':~parate Inputs and outputs; addresses, inputs, and outputs on
Registered write e n a b l e ,•.::'."." •...

..

ns
ns

-- .'...

ns

-

ns

-

ns

5'}/ . ,.

-

ns

-

25

ns

_.' ....:.....

30

ns

~.,.

30

80

ns

30

ns

30

ns

30

-

35

ns

20

<

20

.,.

<

-

65
25
25

.. ,

.,
..

.' .. ,

............

<>

..

ns

ns

/ ... 25.

·i~

30

-

35

ns

}>.,.,.

60

-

75

-

90

ns

50,,)·.·.C

-

60

-

75
75

-

ns

60

40

-

50

-

60

ns

40

-

50

60

ns

50

-

60

-

75

ns

56»
.)
.:.

- .'.'.
-

\>. .. ",., -

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. This parameter guaranteed but not tested.

4-228

ns

FEATURES:

DESCRIPTION:

• 4K x 16-bit RAM with register at output, serial load and readback
• Designed for microprogram writable control store

The IDT71502 Registered RAM is designed expressly for effi~
cient use in writable control stores. This 65,536-bit high-speed
static RAM is organized as 4K x 16 bits with a high-speed register at
the RAM outputs and serial load and read back capability using the
lOT Serial Protocol Channel (SPC).lts architecture is optimized for
microprogram writable control store use. Hardware is provided for
software test and debug, parity checking and serial microcode
load at initialization.
The IDT71502 is available with address set-up before clock
times as fast as 35ns with a maximum power consumption of only
900mW.
All inputs and outputs of the IDT71502 are TIL-compatible and
the device operates from a single 5V supply. Fully static, asynchronous circuitry is used, requiring no clocks (with the exception ofthe
register clock) or refreshing for operation.
The IDT71502 is fabricated using lOT's high-performance,
high-reliability technology- CEMOS TM. This technology gives the
10T71502 the combination of low power, high speed and high density that makes it a cost-effective alternative to bipolar and NMOS
devices such as registered PROMs.
The IDT71502 is packaged in a 48-pin, 600 mil DIP, providing
high board level packing densities.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

• Serial Protocol Channel (SPC) allows load and readout of RAM
over a 4-wire channel .
• RAM address counter speeds RAM load, readout
• Outputs may be programmed to be registered or non-registered
in groups of 8 bits
• Initialize register allows initial microword selection
• Synchronous and asynchronous output enables allow for depth
expansion and bus driving
• Breakpoint comparator supports system diagnostics
• Parity check on outputs for high-reliability designs
• High-speed (address set-up before clock)
- Military: 45/55ns (max.)
- Commercial: 35/45ns (max.)
• Built in CMOS for low power consumption
• Inputs and outputs directly TIL-compatible
• Standard 48-pin DIP
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
SERIAL
DATA IN

SERIAL
DATA OUT

SERIAL PROTOCOL REGISTER
RAM lOAD/READ BACK lOGIC
lOAD/READOUT BUS

BREAKPOINT

ADDRESS

RAM ADDRESS

12

WE

cs
ClK

+

INIT

SYNCHRONOUS
OUT ENABLE
OUT ENABLE

PARITY
RAM DATAoUT
CEMOS and SPC are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-1039/-

1987 Integrated Device Technology, Inc.

4-229

911
~

IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

IDT71502S35(1)
I DT71502 l35 (1)
MAX.
MIN.

PARAMETER

SYMBOL

(VCC = 5V ±10%, All Temperature Ranges)
IDT71502S45
1DT71502L45
MIN.
MAX.

I DT71502S55(2)
IDT71502L55(2)
MIN.
MAX.

UNIT

RAM WRITE CYCLE
65

80

two

RAM Write Cycle Time

50

tWAS

RAM Write Address Set-up Time

0

twp

RAM Write Pulse Width

40

ns

tDW

RAM Write Data Set-up Before End
Of Write

20

ns

twcw

Chip Select To End Of Write

40

tWDH

RAM Write Data Hold Time

0

Write Recovery Time
tWA
NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.

ns
ns

ns
"='='

5

0

0

ns

5

5

ns

TIMING WAVEFORM OF WRITE CYCLE (1)

twc

ADDRESS

:=) (

)(

,

t wcw

~\.

/~tWAtwp

tWAS

"

DATA IN

--------KF t~

NOTE:
1. A write occurs during the overlap of both 'C'S" and

wr=. low.

4-230

/"

IDT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM

AC ELECTRICAL CHARACTERISTICS

(Vcc = 5V ±10%. All Temperature Ranges)
IDT71502S35(1)
1DT71502L35 (1)
MAX.
MIN.

PARAMETER

SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT71502S55(2)
IDT71502L55(2)
MIN.
MAX.

IDT71502S45
IDT71502L45
MAX.
MIN.

UNIT

TRACE WRITE CYCLE
t TWC

Trace Write Cycle Time

50

-

60

-

t TWDS

Trace Write Data Set-up Time

10

-

12

-

tTWDH

Trace Write Data Hold Time

0

-

t TWS

Trace Write Enable Set-up Time

10

-

t TCS

Trace Write Chip Select Set-up Time

10

tTWH

Trace Write Enable Hold Time

0

\r~

t TCH

Trace Write Chip Select Hold Time

0

-

0

::.: :{i: \:\:-\(::\

T\:\:::: \\'+

·t ::;:::.::

=::::·::::9

-

ns

-

ns
ns

15

-

ns

-

15

-

ns

:·:..··0

-

0

-

ns

0

-

0

-

ns

.::;::::::: 1?=:

\\

::::{::+::::{::::) \\::::J 2\:::::::\;:::

\: :

75
:;::
{\ 15;::::·)}':\\

:=::::

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.

TIMING WAVEFORM OF TRACE WRITE CYCLE (1)

~--------------------tTWc----------------------~

~--------tCWH--------~~·--------tCWL --------~~

CLOCK

DATA IN

~----- tTCS -

~ tTcH

NOTE:
1. A write occurs if both CS and ~ are low at the clock low-to-high transition

AC TEST CONDITIONS (Read and Write Cycles)
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V

GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

BK~----{

DATAOUT~
5000

30pF*.
(5pF for
toz. tsoz)

2200
30pF*

1

Figure 2. Output Load
(for BKPT pin)
*Includes scope and jig.

Figure 1. Output Load

4-231

HI

IDT71502S/lDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SPC AC ELECTRICAL CHARACTERISTICS (1)

VCC = 5V +10%, All Temperature Ranges
IDT71502S/L (1)

PARAMETER

SYMBOL

MIN.

MAX.

UNIT

tSCLK

SCLK Period

100

-

ns

tscw

SCLK Pulse Width

40

-

ns

t SDS

Serial Data Set-up Time

20

ns

tSDH

Serial Data Hold Time

0

-

tscD

Clock to serial Data Output Delay

50

ns

t SPD

Serial Data-In-to-Out Delay, Stub Mode

-

40

ns

tCMLH

Command/Data Set-up Time, Low-to-High(2)

20

-

ns

tCMHL

Command Set-up Time, High-to-Low (Execution Time)(2)

40

ns

tCMH

Command/Data Hold Time(2)

20

-

NOTES:
1. These specifications apply to all speed grades of the product.
2. C/D cannot change while CLOCK is high.

TIMING WAVEFORM OF SPC CHANNEL

~---------------tSCLK--------------~

SCLK

SERIAL DATA IN

SERIAL DATA OUT

C/O

COMMAND
EXECUTE TIME
(REFERENCE)

AC TEST CONDITIONS (SPC)
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V
GND to 3.0V
5ns
1.5V
1.5V
See Figure 3

SO

~

2550

4800
30pF*

Figure 3. Output Load for Serial Output
*Includes scope and jig.

4-232

ns

ns

IDT71502S/IDT71502l CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SPC FUNCTIONAL BLOCK DIAGRAM
COMMAND DATA (c/5) --~--------------------------,
SERIAL DATA IN

(SI)

---t---------r--------------,----.
SERIAL DATAoUT
(SO)

SERIAL CLOCK (SCll<)

---r--+-----L~

MUX ENABLES
J - - - - - - I - - - - - - I.. AND REGISTER
STROBES, ETC.

L...------r------..1
DATA
ClK

DIAGNOSTIC DATA
TO/FROM CHIP

SPC COMMAND FORMAT

o

4 3

7

SPC Command Code
4 bits

SPC Register Code
4 bits

SPC COMMAND CODES
COMMAND
CODE

READ/WRITE
FUNCTION

0

Read

Read Register

ACTION

NOTES
Uses Register Select Field

1

Write

Write Register

Uses Register Select Field

2

Read

Read Register and Increment Initialize Counter

Serial RAM Read

Write and Increment Initialize Counter

Serial RAM Write

3

Write

4-C

-

D

Write

Stub Diagnostic

Broadcast Commands

E

Write

Serial Diagnostic

Serial Commands

F

-

No-Op

Guaranteed No-Op

-

Reserved (No-Op)

SPC REGISTER CODES
REGISTER
CODE

READ/WRITE
FUNCTION

0

RIW

Initialize Counter

-

1

R/W

RAM Output

-

REGISTER

NOTES

2

R/W

Pipeline Register

-

3

R/W

Break Mask Register

4

R/w

Break Data Register

-

R/W

Set-up

5

+ Status Register

Break Multiplexer, Trace Mode, etc.

6

Rd Only

Y15 -Yo (Data Pins)

Data Pins of Chip

7

Rd Only

RAM Address

Address Going into RAM

8-F

-

Reserved (unused)

4-233

-

IDT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

REGISTERED RAM DATA FLOW BLOCK DIAGRAM
SPR READ DATA BUS

r------------

SERIAL
DATAoUT

SPR WRITE DATA BUS
TRACE

ADDRESS

WE

---...."e.=----~

----d

BREAKPOINT
COMPARE

L____ _ ____ J
~1 LEVEL
~oLEVEL

SET-UP
REGISTER

TNIT -!-i-~-_.__----Ir=~~

CDR

FLOW 15-8
FLOW 7-0
1--4-.....-4~-+-~.

I-r-+-+-+-+--f-f--.

-+~--~~--~

BREAK ON ADDRESS
BREAK PIPE
TRACE

POWER
UP

or:

--+------1

1-_ _ _.....L......I-L-L-L....L....lL.-_ STATUS BITS

RAM DATA OUT

PARITY

4-234

1DT71502S/IDT71502L CMOS STATIC RAM
64K (4K x Hi-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SET-UP REGISTER FORMAT
BIT

NAME

TYPE (1)

FUNCTION

POWER-UP
VALUE

15

CE

RO

Chip Enable State: NOR of All Chip Enable Pins

0

14

SOE FF

RO

0

13

SOE Pin

RO

12

OE Pin

RO

11

WE Pin

RO

6

CS o Level

RfIN

= Output Enabled. 0 = Output Disabled
SOE Pin State: 1 = High. 0 = Low
OE Pin State: 1 = High. 0 = Low
WE Pin State: 1 = High. 0 = Low
INIT Pin State: 1 = High. 0 = Low
Breakpoint Comparator Output: 1 = Compare Valid
BP Pin State: 1 = High. 0 = Low
o = CS1 is Low Active; 1 = CSI is High Active
o = CSo is Low Active; 1 = CSo is High Active

5

Non-Reg High

R/W

Set Pipeline Register Bits 15-8 to Flow-Through Mode

4

Non-Reg Low

R/w

Set Pipeline Register Bits 7-0 to Flow-Through Mode

0

3

-

-

(Unused)

0

10

INITPin

RO

9

BP Compare

RO

8

BP Pin

RO

7

CS 1 Level

R/W

SOE FF State: 1

o = Breakpoint on Pipeline Register Output. 1 = Breakpoint on RAM

0
0
0
0
0
0
0
0
0

2

BC Address

R/w

1

BC Pipelined

R/w

Set Breakpoint Output MUX for Pipeline FF Output

0

R/W

Set for Trace Mode: "15-0 to Pipeline Register. Pipeline Register to RAM.
Initialize Counter as Address. Write with Clock Pulse

0

0

Trace Mode

Address Inputs

NOTE:
1. RO means Read Only. R/W means Read/Write.

4-235

0

1DT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

GENERAL DESCRIPTION
register. This is the normal operating mode, where all the shift registers in a system are connected into one long shift register. The
SPC logic in the IDT71502 is automatically set to the Serial mode
by power up. The Stub command sets the latch and causes the serial output data to be taken from the serial input. In this mode, the
serial data is passed directly from one chip to the next so that all
command registers have the same data at their serial inputs. This
allows a broadcast mode where all command registers in a system
can be loaded with the same command at the same time.
SPC commands cause data to be written into registers or read
from various points on the chip. The SPC commands for the
IDT71502 Registered RAM are shown in the SPC Command
Codes and SPC Register Codes tables. The 8-bit command is
divided into two 4-bit fields. The four most significant bits define the
read or write function and the least significant four bits select a
register to be read or written ..

The IDT71502 Registered RAM consists of a 4K x 16-bit RAM
plus a 16-bit pipeline register and is designed for microcode
writable control store use. A serial shift register system, the Serial
Protocol Channel (SPC), is included on-chip for serial load and
read-back of the RAM data. A RAM address counter is also provided to speed up RAM load and read-back. The SPC serial shift
register is also configured to be used as a diagnostic register. The
shift register can read all status conditions on the chip such as the
RAM output, pipeline register output, data output pin state and
RAM load/read counter value. A breakpoint comparator is
included to support the diagnostic function. This breakpoint
comparator can be used to detect a particular bit pattern in the
RAM address or pipeline register outputs.
The IDT71502 Registered RAM includes features to support
control store applications. These include synchronous output
enable and an initialize register for selecting the initial value of the
pipeline register. A parity output is provided which indicates the
parity of the contents of the pipeline register. The parity output can
be used to provide parity check control for high-reliability systems.
The IDT71502 Registered RAM can also be used as a trace RAM
for recording external data. In this mode, the data I/O pins are
inputs and data is clocked into the RAM using the Initialize register
as the address counter. The Trace mode, in combination with the
breakpoint comparator, allows the IDT71502 Registered RAM to
be used as a one-chip logic analyzer.

RAM Load/Readback Logic
A detailed block diagram of the IDT71502 Registered RAM:
showing the various internal registers and the load and readback
paths, is shown in the Registered RAM Data Flow Block Diagram.
In addition to the logic shown in the Functional Block Diagram on
the first page of the data sheet, there is an Initialize Counter for
loading and initializing the RAM, Break Data and Mask registers for
the Breakpoint Comparator and multiplexers at the input to the
Pipeline register for allowing data from the data I/O pins to be
clocked into the Pipeline register in the Trace mode before being
written into the RAM. The data flow block diagram also shows the
various multiplexers for routing data for breakpoint and read back
use.

RAM Operation
After power up, and in its typical operating mode, the IDT71502
Registered RAM is set for pipelined read and direct (non-pipelined)
write. Data may be directly written into the RAM by driving the
address and data inputs and strobing the Write Enable input. Data
is read from the RAM by driving the address lines and clocking the
pipeline register.
The RAM may also be read and written by the Serial Protocol
Channel (SPC). This is the typical path for loading the RAM after
power up.

Initialize Counter
The Initialize Counter provides the initial address to the RAM after reset of the part. A pulse applied to the Initialize pin causes the
Initialize Counter to be gated to the RAM address and the RAM data
to be preset into the pipeline register. This provides an initial value
in the pipeline register before the first clock pulse arrives. The
Initialize Counter can be reset to zero at power up of the chip and
can be loaded with a value other than zero by the SPC. Once
loaded with a value by the SPC, this value is used in further chip
reset operations.

Serial Protocol Channel
The Serial Protocol Channel (SPC) logic consists of a 16-bit data
shift register, an 8-bit command register and clock logic consisting
of gates and a flip-flop. A block diagram of the command decode
logic is shown for reference. The command decode logic decodes
and executes the command in the command shift register using
the clock from the clock logic. The command is divided into two
four-bit fields. The most significant four bits of the command register define the command to be executed: read, write, etc. The least
significant four bits define the register to be read or written. (NOTE:
The data to the SPC is shifted in LSB first.)
The SPC is connected to the outside world through four wires.
These wires consist of serial data in and out, a shift clock and a
command/data line. When the command/data line is high, commands are shifted from the serial data into the command register
by the clock. When the command/data line is low, data is shifted
into the data shift register by the clock. When the command/data
line transitions from high (command) to low (data), a clock pulse is
generated internally to the command decode logic. This pulse
lasts from the beginning of the high-to-Iow transition to the next
serial clock pulse and is used to execute the command in the
command register.
Two of the defined commands are Serial and Stub. These commands control a latch which determines the source of the serial
data out in the command mode. The Serial command causes the
data output to be taken from the last stage of the command shift

Set-up Register
The Set-up Register is a 16-bit register used to set the chip operating mode and to read back chip operating status conditions. A
command word written into the Set-up Register sets 7 latches
which control the chip operating conditions. Reading the Set-up
Register provides the current status of these 7 latches and various
other signals on the chip. At power up, the 7 latches are cleared to
zero and the Initialize counter is cleared to zero. The format of the
Set-up Register is shown in the Set-up Register Format table.
The Set-up Register has 7 latches which determine the operating mode of the chip. These are CS 1 , CSa, Non-Reg Hi~ NonReg Low, BC RAM, Break P~ and Trace. The CS 1 and CS a bits
determine the polarity of the CS 1 and CS a chip enables. The NonReg High and Low bits set the upper and lower bytes of the Pipeline
Register to a flow-through mode, respectively. The BC RAM bit
determines the source of the data for breakpoint comparison,
either the Pipeline Register or the RAM address. The Break Pipe
latch switches the breakpoint pin multiplexer from the comparator
to the buffer flip-flop. The trace latch sets the chip into the Trace
mode.

4-236

1DT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Power Up State
Note that taking Vee from 5.0 volts to 2.0 volts and back to
5.0 volts will not cause power up reset.

Power up is defined as taking Vee from below 1.0 volts to
5.0 volts nominal. This generates power up reset, an internal signal
which resets several registers on the chip. After power up, the
IDT71502 is in the following state:
• Set-up Register cleared to zero
• Initialize Counter cleared to zero
• Breakpoint Mask Register cleared to equal (Breakpoint output
high)

Set-up Register: Programmable Chip Enable
The chip enable function is programmable by bits in the Set-up
Register. The logic for this is shown in Figure 1. The bits in the Setup Register define the active state of each Chip enable: high or low.
This allows up to four RAMs to be cascaded in depth with no
external decoders required (16K x 16 bits of RAM).

• SOE Flip-Flop cleared to outputs off

CE

}---,-_ _ _ _ _ _ _ _ _- . . TO SOE FLIP-FLOP
BREAKPOINT
COMPARATOR

WRITE FROM SPR - - - - - - - {

Figure 1. Chip Enable Logic Block Diagram

4-237

WRITE To RAM

IDT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM
.

MILITARY AND COMMERCIAL TEMPERATURE RAN~ES

Set-up Register: Non-Registered Outputs
Two bits of the Set-up Register. Non-Reg Hi and Non-Reg La.
can be setto cause the Pipeline Register bits 15-9 and 7-0. respectively. to be set to the flow-through mode. In the flow-through
mode, both latches of the register are open and the register acts
like a simple buffer with its outpu~ following its input. This allows the
user to have some non-registered bits in microcode applications.
The output circuit consisting of the Pipeline Register. the ~chro­
no us Output Enable (SOE). and the Output Enable (OE). has
some special logic to support this mode, as shown in Figure 2.

Also. activating the Initialize pin causes the Pipeline Register to be
put in the flow-through mode. Figure 2 shows the Pipeline Register
as two latches operated in the MASTER/SLAVE configuration. The
clock input will cause the latch pair to work as a register. If the Initialize pin is activated. both registers will be placed in the flowthrough mode by the OR gates. Also, if either Non-Reg bit is set. its
corresponding 8-bit portion of the register will be placed in the
flow-through mode.

RAM DATAoUT

MUX

NON-REG HI

RAM DATAoUT
NON-REG

15-8

MUX

La

7-0

INITIALIZE

MASTER
LATCH

SLAVE
'-----"T"""-...I

LATCH

CLOCK --r---~----+-~L---------------------4-----~-+~

~~-.-------r~------------~------~----~+-----------~

~--------------

______

~+-

________

~

____________- - J

ct------------------------~--------~------------------~

DATA OUT
15-8

DATA OUT
7-0

Figure 2. Output Logic Block Diagram

When in the flow-through mode, the output enable flip-flop for
that half must also be in the flow-through mode for external chip
expansion to work properly. A non-registered RAM bit must be enabled by a non-registered output enable, while a registered bit

must be enabled by a synchronous output enable. This is done by
using the non~stered bit to control a multiplexer which selects
between the SOE flip-flop input and output as the source of the
output enable.

4-238

1DT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

REGISTERED RAM DATA FLOW BLOCK DIAGRAM

r-----------------------------------------,
SPR READ DATA BUS
I

I
I
SERIAL
DATAIN

I

r - - - - - - - - - - - - - - t . - SERIAL

~:~-,.?t~rSEFiiAi::PAiD_nOCi5LiREciiSi=ERh..L-----___t-J
I

DATA OUT

I
I
I TRACE
I
I
I
I
ADDRESS

I
I

-r-------:-r,,-~

wr:. -r----~

L.. _ _ _ _ _ _ _ _

CE 1 LEVEL -----....-+-1
CEo LEVEL ------.-++-1

mrr

FLOW 15-8 - - - - r l - + t - t
FLOW 7-0 __--r-+-+++-I
BREAK ON ADDRS ----,-+-+-+++-1
BREAK PIPE --....-i-+-+-+-f-l--1
TRACE ~-H-t-H-+--t

...L~~-___r_--~;;;;;~

CD<
POWER
UP
~ ~--r---~

STATUS BITS
1- _ _ _ _ _ _ _ _ _ _ _ _ _

--------------------~
RAM DATA OUT

PARITY

4-239

1DT71502S/IDT71502L CMOS STATIC RAM
64K (4K X 16-BIT) REGISTERED RAM

MILITARY AND ~OMMERCIAL TEMPERATURE RANG,ES

CLOCK

CE·WE

SyNC WE

TCLK
(RAM WRITE)

-Wl
I

PIPELINE REGISTER
INPUT

~

B

I

PIPELINE REGISTER
OUTPUT

=x

X

5

i
I

~

D

X
I

B

I
I

D

X

~

I

C

IE

I

I

I

i

i

I

I
F I
I
I
I

I

X
I

C

n

fl

~

E

I

I

X

I

i
I

~

C

I

Al

I
I

INITIALIZE COUNTER
(RAM ADDRESS)

~

I
I
I
I

i
I

i

X

6

X

7

Figure 4. Trace Mode Sequence Timing Diagram

CLOCK

---J
II

TCLK
(RAM WRITE)

I

PIPELINE REGISTER
INPUT

j I---.....,.-----.....;----------------J~
!
DATA X

I

PIPELINE REGISTER
OUTPUT

INITIALIZE COUNTER
(RAM ADDRESS)

RAM DATA

+

1

=t=x I

DATA X

DATA X

""'""r------i--------------i:'---'X

i

I

l

I
OLD

+

2

I

I

i

X

N

I
I

I

:X

X

X

N

+

1

DATA X

Figure 5. Trace Mode Clock Timing Diagram

4-240

!

DATA X

+1

1DT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Parity Output
The Parity Output pin is generated from a 16-bit parity tree, as
shown in the Parity Tree Logic Block Diagram (Figure 6). Even parity is used. Parity is generated on the contents of the Pipeline Register. The parity output driver is three-state and is enabled by the
SOE Flip-Flop to allow depth expansion of the parity output.
The Parity Output always reflects the parity of the registered
value. Additional flip-flops and multiplexers are included in the

REGISTER BIT 15
REGISTER BIT 14
REGISTER BIT 13
REGISTER BIT 12
REGISTER BIT 11
REGISTER BIT 10
REGISTER BIT 9
REGISTER BIT 8

REGISTER BIT 7
REGISTER BIT 6
REGISTER BIT 5
REGISTER BIT 4
REGISTER BIT 3
REGISTER BIT 2
REGISTER BIT 1
REGISTER BIT 0

parity tree to cover the case of non-registered outputs. If one or
both bytes of the Pipeline Register are set to the Non-Registered
mode, a flip-flop pipeline delay is added to the corresponding byte
parity chain to make the result of that byte parity calculation the
same as if the Pipeline Register was not in the Non-Pipelined
mode.

~l?
~l?

CLOCK

....f------NON-REGISTER HI BYTE

OUTPUT DRIVER

D--{{--

~l?
~l?

sot:

PARITY OUTPUT

FLIP-FLOP

.....; . - - - - - - NON-REGISTER La BYTE

Figure 6. Parity Tree Logic Block Diagram

4-241

IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

REGISTERED RAM APPLICATIONS
Using the Registered RAM in Writable Control
Stores

16-bit microprogram-controlled system using the IDT71502 is
shown in Writable Control Store Using Registered RAM (Figure 7).
The system shown uses four IDT71502 Registered .RAM chips to
provide 4K x 64 bits of microcode writable control store.
.

The IDT71502 Registered RAM is designed expressly for efficient use In writable control stores. A simplified block diagram of a

16-BIT DATA BUS
BOARD
DIAGNOSTIC ACCESS

CONDITION
CODE TEST
LOGIC

,

IDT71502
REGISTERED
RAM
BITSO=15

I

•

IDT39C10A

MICROCODE
LOAD LOGIC

~ MICROPROGRAM

SEQUENCER

IDT71502
REGISTERED
RAM
BITS 16-31

t

,

"

~

-;;; g-;;;
01:
... _1:
CD 01\1

t

IDT71502
REGISTERED
RAM
BITS 32-47

SYSTEM CONTROL BITS

n

IDT71502
REGISTERED
RAM
BITS 48-63

+

+

C/) ... ..1:

a..(J

~

"
...

Figure 7. Writable Control Store Using Registered RAM

4-242

IDT49C402
REGISTER
ANDALU

1DT71502S/IDT71502L CMOS STATIC RAM
64K (4K x 16-8IT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Using the Parity Output
The parity output can be used in conjunction with an additional
IDT71502 Registered RAM to provide parity checking for control
stores. This is shown in the Parity Check in a Writable Control Store
System (Figure 8) block diagram. The parity output driver is gated

by the SOE Flip-Flop. This allows simple depth expansion of the
parity function by paralleling the parity outputs in the same manner
as the data outputs, as shown in the Parity Check in a Depth Expanded Writable Control Store System (Figure 9) block diagram.

-..

Serial Protocol Channel no

-~

V

~

IDT71502
4Kx 16
REGISTERED
RAM

IDT71502
4Kx 16
REGISTERED
RAM

IDT71502
4Kx 16
REGISTERED
RAM

#0

#7

PARITY BITS

-

-...

-

-...

a.

a.

>-

>-

lU

lU

t
8-BIT
COMPARATOR
IDT74FCT521A

+----"
CONTROL BITS 0-15

"

CONTROL BITS 112-127

Figure 8. Parity Check in a Writable Control Store System

4-243

-...
~

PARITY
ERROR

IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SERIAL PROTOCOL CHANNEL

--v

--~=\/

V

IDT71502
4Kx 16
REGISTERED
RAM

IDT71502
4Kx 16
REGISTERED
RAM

IDT71502
4K X 16
REGISTERED
RAM

#0

#7

PARITY BITS

------

-

l

--\I

V

BANKO

V

1----

IDT71502
4Kx 16
REGISTERED
RAM

IDT71502
4Kx 16
REGISTERED
RAM

IDT71502
4Kx 16
REGISTERED
RAM

#0

#7

PARITY BITS

BANK 1

1----

lit

>-

>-

+'

-...

+'

a..

a..

-...
CIS

8-BIT
COMPARATOR
IDT74FCT521 A

CIS

"
CONTROL BITS 0-15

-,

,
-----

"

CONTROL BITS 112-127

Figure 9. Parity Check In a Depth Expanded Writable Control Store System

4-244

...

PARITY
ERROR

1DT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Using Trace Mode as a Logic Analyzer
The Trace mode allows the IDT71502 to be used as an on-board
logic analyzer for system diagnostics. It is particularly powerful
when used in conjunction with the Breakpoint function. In the
Trace mode, data is recorded in sequential locations in the RAM
controlled by the Trace Counter. Since the incon'ling data is
clocked into the pipeline register, the set-up and hold times are
short and compatible with capturing changing bus data, for example. A block diagram of a system with an IDT71502 used in the
Trace mode is shown in Diagnostic Bus Monitoring Using Trace
Mode (Figure 10).
The Breakpoint outputs from the IDT71502 devices in a system
can be used to control the Trace mode writing. The Breakpoint

as

outputs are open drain types which provide a wire-AND function
when connected together to a single pull-up resistor. By tying the
Breakpoint outputs for the writable control store RAMs and the
trace RAM, a breakpoint comparison can be made over the full
microcode word plus the data bus contents. This comparison can
be used to enable the trace write so that only data which occurred
at the Breakpoint times is recorded. This allows recording the data
that was on the bus during each instance of an I/O write, for
example.

BOARD
DIAGNOSTIC ACCESS

MICROCODE
LOAD LOGIC
16-BIT DATA BUS

CONDITION
CODE TEST
LOGIC

IZ

5
a.
~

L5

a:

co

IDT71502
REGISTERED
RAM
BITS 0-15

IDT71502
REGISTERED
RAM
BITS 16-31

IDT71502
REGISTERED
RAM
BITS 32-47

IDT71502
REGISTERED
RAM
BITS 48-63

IDT49C402
REGISTER
AND ALU

SYSTEM CONTROL BITS

Figure 10. Diagnostic Bus Monitoring Using Trace Mode

4-245

IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Serial Loading of the IDT71502 Using the SPC
In order to use the 10T71502 in writable control store applications, it must be loaded with the microprogram before use. This is
done using the Serial Protocol Channel (SPC). Loading the RAM
over the SPC can be done in several ways. The microcode can be
loaded from a central microprocessor, which can perform both
microcode load and system diagnostics at power up, or it can be
loaded using dedicated load logic.
An example of a design of this dedicated load logic is shown in
the Microcode Load Logic Example (Figure !11). The purpose of
this example is to show how one goes about designing this logic.
This example shows an approach which loads the RAMs with data
from a single EPROM. The load logic gets the SPC command and

data information from the EPROM. It is controlled by single byte instructions from the same EPROM. The format of these instructions
is shown in Microcode Load Logic Instruction Formats (Figure 12),
and a map of the typical contents of the EPROM is shown in
Microcode Load EPROM Memory Map (Figure 13).
The load logic consists of a 16-bit address counter, an 8-bit shift
register, a 4-bit byte counter and a PAL containing a 2-bit instruction register. The logic in the PAL interprets the 2-bit load instructions to cause bytes of command or data information to be loaded
into the 10T74FCT299 shift register and shifted to the SPC. The two
10T74FCT161 counters are used to count the bytes being sent and
the 8 bits in each byte.

POW~~S~~ _ _ _ _ _ _"T'R_E_S_ET_. .
CLOCK

SERIAL DATA
TO IDT71502S

SERIAL CLOCK
COMMAND/DATA
END OF LOAD

Figure 11. Microcode Load Logic Example

I I I

BYTE COUNT

LOAD COMMAND

I I I

BYTE COUNT

LOAD COMMAND
USING SLOW CLOCK

BYTE COUNT

LOAD DATA

BYTE COUNT

STOP, END OF LOOP

0

0

0

II
II

0

I
I

Figure 12. Microcode Load Logic Instruction Formats

4-246

-----------------------------------

IDT71502S/IDT71502L CMOS STATIC RAM
64K (4Kx 16-BIT) REGISTERED RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

EPROM
ADDRESS

0000

EPROM Data

o

I I

4

0

LOAD 4 COMMAND BYTES

0001

COMMAND BYTE 0

0002

COMMAND BYTE 1

0003

COMMAND BYTE 2

0004

COMMAND BYTE 3

0005

1

I I

8

0

LOAD 8 DATA BYTES

0006

DATA BYTE 0

0007

DATA BYTE 1

ooOB

DATA BYTE 7

OOOC

oI a

I

OOOD

4

LOAD 4 COMMAND BYTES

COMMAND BYTE 0
ETC.

.1

o

STOP, END OF LOOP

Figure 13. Microcode Load EPROM Memory Map

ORDERING INFORMATION
IDT

XXXX

A

999

A

A

Device Type

Power

Speed

Package

Process/
Temperature
Range

·y:mOk

'------------tC

35

Commercial (O°C to

Sidebraze DIP

Commercial only

55

Military Only

L
S

Low Power
Standard Power

' - - - - - - - - - - - - - - - - - - - - - - - - t 71502

4-247

1

Speed in Nanoseconds

'-------------~45

'--------------------1

+ 70°C)

Military (-55°C to + 125°C) .
Compliant to MIL-STD-883, Class B

64K (4K x 16-Bit) Registered RAM

fashion. The device has the serial data-in and serial data-output
bits connected to form a 32-bit Serial Protocol Channel register.
The module features four separate output enables, one for each of
the IDT49FCT818 registers. Thus, the Y outputs from the
IDT49FCT818 registers may be enabled or put into the high-impedance state on individual8-bit boundaries. The Command/Data
(C/O), Serial Shift Clock (SCLK) and Parallel Clock (PCLK) are all
bus organized across the four IDT49FCT818 registers. The thirtytwo register output bits, eight from each device, are separately
brought out to form a 3~~t:>it wide pipeline register on the Writable
Control Store.
(;:):;:\.\!""
In normal operation, ~~~'fiom the 32-bit wide memory is loaded
into the IDT49FCT818':r~gisters on the low-to-high transition of
PCLK. Reading(ind writing of the memory by means of the Serial
Protocol ChaQri~'f:Js performed i[1 the normal fashion using the
IDT49FCT81~':Jllatis, the data to be loaded can be shifted in the
serial data inPb,tby using the SCLK and a load command executed
by shifting the p(oper command word in the serial data input when
the C/P:liri~'l~nn the command mode. This command will then be
exeytltedt>y. manipulating the C/O line and SCLK line in the desire(j fashion. Data is then written into the RAM by bringing the write
e(lable line on the RAM memory from the high state to the low state
DESCRIPTION:
~. I:lhd ~Ck to the high state.
.
The IDl7M6032 is a 16K x 32-bit Writable Control Store (WCS)
:,\::~:':'>\::>1he IDl7M6032 is offered in a compact 64-pin 600 mil wide ceRAM and pipeline register. It features eight IDl7198 16K x 4 high-,,":l':';:;i::;;ramic dual in-line module. It is constructed using ceramic LCC
performance static RAMs and four IDT49FCT818 Serial Protocof:?:::~':,:,,:.:;,,:;c6mponents on a multilayer co-fired ceramic substrate and occuChannel (S~C) registers. These devic~s are ~rranged to form the;;~;i,:~;,:~,!,\,,\} pies less than 2 square inches of board space.
..
16K x 32 Wntable Control Store RAM With Senal Protocol ChanDel ', .. '
The semiconductor components used on alilDT military modfor loading of the memory. The address lines, Chip select,(:writ~\
ules are manufactured in compliance with the latest revision of
MIL-STD-883, Class B, making them ideally suited to applications
enable and output enable of the RAMs are all bused tog~f\ler t9)
demanding the highest level of performance and reliability.
form one large 16K x 32 memory. Each eight outputs C?f::t~.~ RAM
are connected to the 0 inputs of an IDT49FCT818 in ttie'no.~mal

FEATURES:

• 16K x 32 high-performance Writable Control Store (WCS)
• Serial Protocol Channel (SPC 1M ) - reading, writing and
interrogation
• 4 byte/wide output enables
• Separate chip select, write enable and output enable memory
controls
• High fanout pipeline register
• Fully width expandable
• Designed for high-speed writable control store applications
• Assembled with IDT's high-reliability vapor phase solder reflow
process
• Compact 64-pin ceramic sidebraze DIP
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
e Military modules available ,,·,ith semiconductor components
manufactured In compliance to MIL-STO-883, Class B

FUNCTIONAL BLOCK DIAGRAM

A

16Kx 32 RAM
8 -IDT7198s

110

110

I/O

SDI

,------..SDO

C/r5
SCLK

IDT49FCT818

PCLK

Y

IDT49FCT818

OE

y

OE

IDT49FCT818

Y

OE

CEMOS and SPC are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology, Inc.
4-248

DECEMBER 1987
OSC-703O/-

outputs of the RAM are connected to the D inputs of an
IDT49FCT818 in the normal fashion. The device has the serial
data-in and serial data-output bits connected to form a 112-bit Serial Protocol Channel register. The command/data (C/O) and Serial Shift Clock (SCLK) are all bus organized across the fourteen
IDT49FCT818 registers. The 112 register output bits, 8 from each
device, are separately brought out to form a 112-bit wide pipeline
register on the Writable Control Store.
In normal operation, data from the 112~bit wide memory is
loaded into the IDT49F9T?J.~ registers on the low-ta-high transition of PCLK. Reading and~rjting of the memory by means of the
Serial Protocol Chal')~l,arErperformad using the protocol of the
IDT49FCT818. (For details of this operation, please refer to the
IDT49FCT818 dat~~heet.) The data to be loaded can be shifted in
the serial dataJllpvtJ:~y using the SCLK and a load command executed by s~illiQg tt::t~ proper command word in the serial data input
when the C/D Iioe'is in the command mode. This command will
then ~'~~~lJt,Eki by manipulating the C/O line and SCLK line in
the desired fashion. Data is then written into the RAM by bringing
thewrit~enable line on the RAM memory from the high state to the
Iqwst~tea.nd back to the high state.
,;",,!hE)JD17MB6042 is offered as a compact, cost-effective plastic
<:,'quadln-line module and occupies less than 9 square inches of
··:.'tioard space.

FEATURES:
• 8K x 112 high-performance Writable Control Store (WCS)
• Serial Protocol Channel (SPC TM) -reading, writing and
interrogation
• High fanout pipeline register
• Width expandable
• Designed for high-speed writable control store applications
• Assembled with IDT's high-reliability vapor phase solder reflow
process
• Compact quad in-line module
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible

DESCRIPTION:
The ID17MB6042 is an 8K x 112-bit Writable Control Store
(WCS) RAM and pipeline register. It features fourteen 8K x 8
ID17164 high-performance static RAMs and fourteen
IDT49FCT818 Serial Protocol Channel (SPC) registers. These devices are arranged to form the 8K x 112 Writable Control Store RAM
with Serial Protocol Channel for loading of the memory. Each eight

FUNCTIONAL BLOCK DIAGRAM

ADDRESS
A I2 -A o
13

cs
~

Ol:

3

2

cs
8Kx 112 RAM
14 - IDT7164s

~

OE
I/O

I/O

I/O

I/O

SDI
C/[)
SCLK

SDO
SDI

SDO
D
IDT49FCT818

Y

PCLK

Ol:

Yll1 - Y104

SDI

D
SDO
IDT49FCT818

y

"DE"

Y1Ol -YOO

SDI

D
SDO
IDT49FCT818

y

Y95 - Y88

at:

D
IDT49FCT818

Y

at:

Y7 -Yo

CEMOS and SPC are trademarks of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
©

DECEMBER 1987

1987 Integrated DevIce Technology. Inc.

0$0-7021/-

4-249

91
~

Dual-Port RAMs

DUAL-PORT RAMS
Integrated Device Technology has emerged as the leading
Dual-Port RAM supplier by combining advanced CEMOS technology with innovative circuit design. With system performance advantages as a goal, we have brought system design expertise together with circuit and technology expertise in defining dual-port
RAM products. Our dual-port memories are now industry standards.
The synergistic relationship between advanced process teChnology, system expertise and unique design capability add value
beyond that normally achieved. As an example, our dual-port
memories provide arbitration along with a completely tested solution to the metastability problem. Various arbitration techniques
are available to the designer to prevent contention and system wait
states. On-chip hardware arbitration, "semaphore" token passing

or software arbitration allow the most efficient memory to be
selected for each application. At IDT, innovation counts only when
it provides system advantages to the user.
Both commercial and military versions of alilDT memories are
available. Our military devices are manufactured and processed
strictly in conformance with all the administrative processing and
performance requirements of MIL-STD-883. Because we anticipated increased military radiation resistance requirements, all devices are also offered with special radiation resistant processing
and guarantees. As the leading supplier of military specialty RAMs,
IDT provides performance and quality levels second to none.
Our commercial dual-port memories, in fact, share most processing steps with military devices.

TABLE OF CONTENTS
PAGE

CONTENTS

Dual-Port RAMs
IDT7130
IDT7140
IDT7132
IDT7142
IDT71321
IDT71421
IDT71322
IDT7133
IDT7143
IDT7134
IDT71342
IDT7M134
IDT7M135
IDT7M137
IDT7M144
IDT7M145

8K (1 Kx8) Dual-Port RAM (MASTER) (14-9, 14-68, 14-74, 14-253, 14-260) .....................
8K (1Kx8) Dual-Port RAM (SLAVE) (14-9, 14-68, 14-74, 14-253, 14-260) .••....................
16K (2K x 8) Dual-Port RAM (MASTER) (14-9,14-68,14-74, 14-253, 14-260) ..................•
16K (2K x 8) Dual-Port RAM (SLAVE) (14-9, 14-74, 14-253) ............................•...•.
16K (2K x 8) Dual-Port RAM (MASTER w/lnterrupts) (14-9, 14-74, 14-253, 14-260) ...............
16K (2K 8) Dual-Port RAM (SLAVE w/lnterrupts) (14-9, 14-74, 14-253, 14-260) . . . .. . . . . .• . . . . ..
16K (2K x 8) Dual-Port RAM (w/Semaphores) (14-9, 14-74, 14-139, 14-253) ....................
32K (2K x 16) Dual-Port RAM (MASTER) (14-9, 14-68, 14-74, 14-253, 14-260) . . . . . . . . . . . . . . . . ..
32K (2K x 16) Dual-Port RAM (SLAVE) (14-9, 14-74, 14-253) .................................
32K (4K x 8) Dual-Port RAM (14:"9, 14-68, 14-74, 14-253) .................................••
32K (4K x 8) Dual-Port RAM (w/Semaphores) (14-9, 14-74, 14-139, 14-253) ....... ".............
64K (8K x 8) Dual-Port RAM (14-9, 14-68, 14-74) ..........................................
128K (16K x 8) Dual-Port RAM (14-9, 14-68, 14-74) ........................................
256K (32K x 8) Dual-Port RAM (14-9, 14-68, 14-74) ..................••....................
64K (8K x 8) Dual-Port RAM (SLAVE) (14-9,14-68, 14-74) ...................................
128K (16K x 8) Dual-Port RAM (SLAVE) (14-9, 14-68, 14-74) .................................

x

5-1
5-1
5-16
5-16
5-29
5-29
5-44
5-56
5-56
5-69
5-77
13-125
13-125
13-135
13-142
13-142

---~

...- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

• Standard Military Drawing# 5962-86875 is pending listing on
this function. Refer to Section 21page 2-4.

FEATURES:
• High-speed access
- Military: 45/55/70/90/100/120ns (max.)

DESCRIPTION:

- Commercial: 35/45/55/70/90/100ns (max.)

The IDT7130/IDT7140 are high-speed 1K x 8 dual-port static
RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit
dual-port RAM or as a "MASTER" dual-port RAM together with the
IDT7140 "SLAVE" dual-port in 16-bit-or-more word width systems.
Using the lOT MASTER/SLAVE dual-port RAM approach in 16-ormore-bit memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using lOT's CEMOS TM high-performance technology, these devices typically operate on only 325mW of power at
maximum access times as fast as 35ns. Low-power (LA) versions
offer battery backup data retention capability, with each dual-port
typically consuming 200J.lW from a 2V battery.
The IDT7130/7140 devices are packaged in 48-pin sidebraze or
plastic DIPs, 48- or 52-pin LCes, 52-pin PLCCs, and 48-lead
flatpacks.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

• Low-power operation
- IDT7130/40SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
- IDT7130/40LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
• MASTER IDT7130 easily expands data bus width to 16-or-morebits using SLAVE IDT7140
• On-chip port arbitration logic (IDT7130 only)
• BUSY output flag on IDT7130; BUSY input on IDT7140
• INT flag for port-ta-port communication
• Fully asynchronous operation from either port
• Battery backup operation - 2V data retention
• TTL-compatible, single 5V±10% power supply
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
~L----~----~r-~______________~

CE L ---++------0

D------+~-

OEL----~-J r------~==~~

'---....0----

OE R

.------+:.~------- A9R
.----+-'-1-------- A7R

•

A9L
A7L

RfiJiJ R
CE R

IIO ol

1--...-;--------- I/OoR

II07L

1----4__- - - - - - - II07R

lIDS'YL(1)

lIDS'YR(1)

r---,...t--+------

A6l

•

ROW
SELECT

MEMORY
ARRAY

AOl

ARBITRATION
INTERRUPT
LOGIC

A 6R

ROW
SELECT

__......

.....

~-;--------- AOR

AOR

(IDT7130
ONLy)
INTJ2)~

____________________________~

NOTES:
1. IDT7130 (MASTER):"BUSV is open drain output and requires puliup resistor.
IDT7140 (SLAVE): ~is input.
2. Open drain output: requires puliup resistor.
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1987

© 1987 Integrated DevIce Technology, Inc.

DSC-1000/-

5-1

5

IDT7130SA/LA AND 1DT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

INDEX~ r-"M"j,. .~,.,.~. . ,.JI:r-1"~" M~n-~. . ,.J: :>r-1"8"M"~,. .I~. .,OCI'1" ~"M"~" ~"OC
L.J L.J L.J L.J 1-' I I L...I L.J LJ

6 5 4

1..1 L.J LJ

3 2 I I 484746 45 44 43
L~
42:::
41 ::
40[

J9

J 10
J 11
J 12
J 13
J 14

39[
38 [
37 [

L48-1
&
F48-1

36 ::
35 C
34::
33 [
32 ::

J

18

31 ::

,..,19 20
,.., 21
r, 22
r, 23
" 24
r, r,25 26
" 27
r, 28
r, 29
,.., 30
,.,

48-PIN LCC/FLATPACK
TOP VIEW

DIP
TOP VIEW

INDEX~
LJ LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ

765432LJ525150494847
1
46:::

J8
J9
J 10
J 11
J 12

45C
44;:
43 [
42 [
41 :::
40 ;:

J52-1
&
L52-1

J 13
J 14
J 15
J 16

39[
38 [

J17

37[

J
J

36[

18
19

35 ;:
34[

J~

21 22 23 24 25 26 27 28 29 30 31 32 33

r, ,.., r, ,.,

OE R
AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R

N/C
It0 7R

I' " r, r, r, " r, r' "

52-PIN LCC/PLCC
TOP VIEW

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

SYMBOL

Operating
Temperature

Oto +70

-55 to + 125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

Tsm

Storage
Temperature

-55 to +125

-65 to +150

°C

TA

RECOMMENDED DC OPERATING CONDITIONS

PT

Power Dissipation

1.5

1.5

W

lOUT

DC Output Current

50

50

mA

MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH
V1L

Input High Voltage

2.2

-

6.0

V

Input Low Voltage

-0.5(1)

-

0.8

V

PARAMETER

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

GRADE
Military
Commercial

5-2

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND
OV

5.0V ± 10%

O°Cto + 70°C

OV

5.0V ± 10%

Vee

---------------------------------------------------------------------------------------------IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAMS SK (1 K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(Vee = 5.0V ±10%)

SYMBOL

PARAMETER

IDT7130SA
IDT7140SA
MAX.
MIN.

TEST CONDITIONS

IDT7130LA
1DT1140LA
MIN.
MAX.

UNIT

Ilu l

Input Leakage Current

Vee = 5.5V, \'IN = OV to Vee

-

10

-

5

J.lA

IlLOI

Output Leakage Current

CE = \'IH, VOUT = OV to Vee

-

10

-

5

J.lA

Val

Output Low Voltage (1100- 1/0 7 )

IOl = 4.0mA

-

0.4

-

0.4

V

VOL

Open Drain Output Low
Voltage (BUSY, INT)

IoL =

-

0.5

-

0.5

V

VOH

Output High Voltage

IOH= -4mA

2.4

-

2.4

-

V

16mA

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

PARAMETER

TEST CONDITION VERSION

(1)

(Vee = 5.0V ±10%)

7130 x 35(2) 7130 x 45 7130 x55 7130 x 70 7130 x 90 7130 X 100/120(3
7140 x 35(2) 7140 x 45 7140 x 55 7140 x 70 7140 x90 7140 x 100/120<3 UNIT
TYP. MAX. TYP. MAX. TYP.MAX. TYP.MAX. TYP.MAX. TYP.

SA
LA

Dynamic Operating
Current (Both Ports
Active)

CE =\'Il
Outputs Open
f = f MAX (4)

Standby Current
(Both Ports - TIL
Level Inputs)

CEl and CE R <:: \'IH
f = f MAX (4)

ISB2

Standby Current
(One Port-TIL
Level Inputs)

SA
CEl or CE R ~ V1H MIL.
LA
Active Port Outputs
Open, f = f MAX (4)
COM'L.

ISB3

SA
Both Ports CE land MIL.
LA
Full Standby Current
CE R<:: Vee -0.2V
(Both Ports-All
CMOS Level Inputs) \'IN <:: Vee -0.2V or
V1N $. 0.2V, f = 0(4) COM'L.

lee

ISB1

ISB4

MIL.

-

-

-

-

40
40

130
95

-

-

1.0
0.2

15
4

1.0
0.2

15
4

1.0
0.2

15
4

1.0
0.2

15
4

1.0
0.2

15
4

1.0
0.2

15
4.0

-

-

40
35

125
95

40
35

120
90

40
35

115 40
85 35

110
80

40
35

110
80

40
35

115
90

40
35

105
80

40
35

100
75

40
35

100 40
75 35

95
70

40
35

95
70

COM'L.

Et

75
75

MIL.

SA
LA

-

195
155
-

Et

-

-

COM'L.

25
25

65
45

Et
Et

One Port CEl or
SA
MIL.
LA
CE R <:: Vee -0.2V
Full Standby Current
V
~
Vee
-0.2V
or
1N
(One Port-All
CMOS Level Inputs) V1N S 0.2V
Aetive Port Outputs COM'L. ~
Open, f = fMAX (4)

-

-

-

230
185
190
145
65
55
65
45
135
110
120
85
30
10

MAX.

75
75
75
75
25
25
25
25
40
40
40
40
1.0
0.2

65 230
65 185
65 180
65 140
65
25
25
55
25 65
25
45
40 135
40 110
40 115
85
40
1.0 30
0.2 10

65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2

225
180
180
135
65
55
60
40
135
110
110
85
30
10

65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2

200
160
180
130
65
45
55
35
125
100
110
75
30
10

65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2

190
155
180
130
65
45
55
35
125
100
110
75
30
10

mA

mA

mA

mA

mA

NOTES.
1. x in part numbers indicates power rating (SA or LA).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4.

fMAX = 1/tRe = All inputs cycling atf = lIt Rc(exeept Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level
standby, ISB3 .

5-3

IDT7130SAlLA AND IDT7140SAlLA
CMOS DUAL-PORT RAMS SK (1 K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS
SYMBOL
VOR

(L Version Only)

PARAMETER

I DT7130LA/1 DT7140LA
TVp.(1)
MAX.
MIN.

TEST CONDITIONS

Vee for Data Retention

_

->

_

leeDR

Data Retention Current

Vcc - 2.0V, CE - Vcc 0.2V

t COR(3)

Chip Deselect to Data Retention Time

~N ~ Vcc -0.2V or ~N S 0.2V

t R(3)

Operation Recovery Time

IIMIL.

COM'L.

UNIT

2.0

-

-

V

-

100

4000

J..LA

100

1500

J..LA

0

-

-

ns

t RC (2)

ns

NOTES:
1. Vee = 2V, TA = +25°C
2. t RC = Read Cycle Time
3. This parameter Is guaranteed but not tested.

DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V
5ns
1.5V
1.5V
See Figures 1, 2 & 3

5V

DATAoUT

~

775!l

5V

125on
DATA OUT
1oopF*
(30pF for 35ns and
45ns versions)

Figure 1. Output Load

~

125oo.

.775!l5pF*

Figure 2. Output Load
(for tHZ.tU.twz. and tow)

* Including scope and jig.

5-4

5V
BUSY
or

INT

~

- l1'OOPF.
2700.

Figure 3. BUSY and INT
Output Load

-----

.------------------------------------------------------------

1DT7130SA/LA AND 1DT7140SA/LA
CMOS DUAL-PORT RAMS SK (1 K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

PARAMETER

7130 x 35(2)
7130 x 55
7130 x 90 7130 x 100/120(3)
7130 x 70
7130 x 45
7140 x 55
7140 x 35(2)
7140 x 70
7140 x 90 7140 X 100/120(3) UNIT
7140x 45
MAX.
MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN.
MIN.

READ CYCLE
t Rc

Read Cycle Time

35

-

45

-

55

-

70

-

90

-

100/120

-

ns

tAA
t AcE

Address Access Time

35

-

45

-

70

-

90

-

100/120

ns

35

-

45

55

-

70

-

90

ns

Output Enable Access Time

-

25

-

30

35

-

40

-

40

-

100/120

t AoE

-

55

Chip Enable Access Time

-

40/60

ns

tOH

Output Hold From Address Change .

0

-

0

-

10

-

ns

5

-

5

5

5

-

10

Output Low Z Time (1.4)

-

0

tLZ

-

5

-

5

-

ns

tHZ

Output High Z Time (1. 4)

-

15

-

20

-

30

-

35

-

40

-

40

ns

tpu

Chip Enable to Power Up Time (4)

0

-

0

-

0

-

0

-

0

-

0

-

ns

tpo

Chip Disable to Power Down Time (4)

-

50

-

50

-

50

-

50

-

50

-

50

ns

0

NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.

TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE

(1,2,4)

ADDRESS

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE

(1,3)

t ACE

-/

'1\

J

: ' - tHZ -

i ' - - tAoE -

}

\.

t HZ '"

~tLZI I
\\

DATA OUT

VALlOOATA

tLZ
Icc
CURRENT
ISB

_ t po -

I-- tpu

:l
--------J..... 50%

NOTES:
1. Rfii is high for Read Cycles.
2. Device is continuously enabled, CE = V1L •
3. Addresses valid prior to or coincident with CE transition low.
4. OE = \'JL

5-5

~

..

IDT7130SA/LA AND IDT7140SA/LA
'CMOS DUAL-PORT RAMS 8K(1 K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (6)
7130 x 35(2)
7130 x 55
7130 x 45
7140 x 55
7140 x 35(2)
SYMBOL
PARAMETER
7140 x 45
MIN.

MAX. MIN.

MAX. MIN.

7130 x 70
7130 x 90 7130 x 100/120(3)
7140 x 90 7140 x 100/120(3) UNIT
7140 x 70
MAX. MIN. MAX. MIN. MAX. MIN.
MAX.

WRITE CYCLE

-

70

-

90

-

100/120

50

-

85

-

901100

85

90/100

50

55

0

-

20

-

30

-

40

-

20

-

30

-

35

-

0

-

0

-

0

-

0

15

-

20

35

-

-

0

-

-

0

-

45

-

55

35

-

40

35

-

40

0

-

0

35

-

40

0

-

0

20

-

20

-

-

15

-

Data Hold Time

0

-

twz

Write Enabled to Output in
High Z(1,4)

-

tow

Output Active From End of Write (1,4)

0

twc

Write Cycle Time (5)

35

tEW

Chip Enable to End of Write

30

tAW
t AS

Address Valid to End of Write

30

Address Set-up Time

O·

twp

Write Pulse Width

30

tWR

Write Recovery Time

0

tow

Data Valid to End of Write

tHZ

Output High

tOH

Z

Time (1,4)

0

30

-

50
0

0

NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1. 2 and 3).
2, O°C to + 70°C temperature range only.
3, -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination. twc = t8M + t wp .
6, ·x· in part numbers indicates power rating (S or L).

5-6

0

0

ns

0

-

55/65

-

ns

0

ns

40

-

40

-

40

ns

-

0

-

ns

40

-

0

40/50

-

ns
ns
ns

ns

ns
ns

IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS SK (1 K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, (R/W CONTROLLED TIMING)

(1,2,3,7)

twc
ADDRESS

~
~

)K

K

t

(6)HZ

//
tAW
~

/V

~
~tAS

RNi

"',_twi.

t

(7)

tWR

Wp

f+--

/V
6

)_

tow
DATAoUT

L«

(4)

~

I+--tow

t OH

-

"

L

"
TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)

2> I -

(4)· ...........

L

(1,2,3,5)

~----------------------twc----------------------~

ADDRESS

--~~-------------tEW------------~

NOTES:
1.
2.
3.
4.
5.
6.
7.

RNi must be high during all address transitions.
A write occurs during the overlap (tEW or t wp ) of a low
and a low RNi.
tWR is measured from the earlier of
or RNI going high to the end of the write cycle.
During this period, the I/O pins are in the output state and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the RNi low transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig).
If DE is low during a RNI controlled write cycle, the write pulse width must be the larger of twp or twz + tow to allow the I/O drivers to turn off and
data to be placed on the bus for the required tow. If DE is high during an RNi controlled write cycle, this requirement does not apply and the write
pulse can be as short as the specified t wp .

cr

cr

5-7

1DT7130SA/LA AND IDT7140SA/LA
CMOS DuAL-PORT RAMS SK (1 K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
PARAMETER

SYMBOL

(a)

7130 x 35(1)
7130 x 55
7130 x 90 7130 x 100/120(2)
7130 x 45
7130 x 70
7140 x55
7140 x 35(1)
7140 x 70
7140 x 90 7140 x 100/120<2) UNIT
7140 x 45
MIN.
MAX. MIN. MAX. MIN.
MAX. MIN. MAX. MIN. MAX. MIN.
MAX.

BUSYTIMING

-

-

0

-

20

35

30

-

35

25

-

25

60

-

70

-

35

-

45

-

55

Write to BUSY (3. 6)

0

tWH

Write Hold After BUSY (7)

20

tBM

BUSY Access Time to Address

35

tBDA

BUSY Disable Time to Address

-

t BAC

BUSY Access Time to Chip Enable

t Boc

BUSY Disable Time to Chip Enable

tWDD

Write Pulse to Data Delay (4)

-

tDDD

Write Data Valid to Read Data
Delay (4)

-

tAPS

Arbitration Priority Set-up Time

5

-

5

tBDD

BUSY Disable to Valid Data

-

Note 5

-

NOTES:
1. O°C to

(5)

-

0
20

tWB

30

35
30

-

5

Note 5

+ 70°C temperature range only.
+ 125°C temperature range only.

-

45
40

30
80

Note 5

0

-

20

-

0
20

45
40
35
30
90
70

-

0

-

20

-

ns

50/60

ns

50/60

ns

45

-

50/60

ns

45

-

50/60

ns

100

-

120/140

ns

100/120

ns

45
45

90

ns

5

-

5

-

5

-

ns

-

Note 5

-

Note 5

-

Note 5

ns

5. tBDD is a calculated parameter and is the greater of 0, t WDD - twp (actual)
or t DDD - tDw(actual).
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention.
8. "x· in part numbers indicates power rating (S or L).

2. -55°C to

3. For SLAVE part (ID17140) only.
4. Port-to-port delay through RAM cells from writing port to reading port.

5-8

1DT7130SAlLA AND IDT7140SAlLA
CMOS DUAL·PORT RAMS BK (1 K x 8·Bm

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ WITH BUSY

ADDRR

"J\

MATCH

I

J[-

~

J

"

DATAIN R

j~

'-,

VALID

MATCH

/

r-- t BDD -

t BDA -

.¥

~~

J
tWDD

~~

DATAOUTL
tDDD

TIMING WAVEFORM OF WRITE WITH BUSY

twp

RNi

~tm
BUSY

CAPACITANCE
SYMBOL
CIN
COUT
NOTE:

[t""

I

"

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance
Output Capacitance

CONDITIONS

MAX.

UNIT

VIN = OV

11

pF

VOUT= OV

11

pF

1. This parameter is determined by device characterization but is not
production tested.

5-9

VALID

IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS SK (1 K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
CEl VALID FIRST:
ADDR
LAND R

=x

>C

ADDRESSES MATCH

~t~l (t =1_
BOC

BUSY R
CER VALID FIRST:
ADDR
LAND R

=x

>C

ADDRESSES MATCH

~t~_{ . (t =1_
BOC

BUSY l

TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION
LEFT ADDRESS VALID FIRST:
. . - - - - t RC OR twc ---~~

ADDRl

ADDRESSES MATCH

ADDRESSES DO NOT MATCH

ADDRR

BUSYR
RIGHT ADDRESS VALID FIRST:
. . - - - - t RC OR twc ----~

ADDRR

~~'~~

__________________
~'____________________- J
ADDRESSES MATCH
ADDRESSES DO NOT MATCH

ADDRl

BUSY l
NOTE:

1. CE l = CE R= "'l

5-10

(1)

IDT7130SA/LA AND 1DT7140SA/LA
CMOS DUAL-PORT RAMS SK (1 K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

7130 X 35(1)
7130 X 55
7130x 70
7130 X 90 7130 X 100/120(2)
7130 X 45
7140 X 55
7140 X 35(1)
7140 X 70
7140 X 90 7140 X 100/120(2) UNIT
7140 x45
MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN.
MAX.
MIN.

PARAMETER

INTERRUPT TIMING
tAS

Address Set-up Time

0

0

-

0

-

ns

0

0

-

0

-

0

-

0

0

-

-

Write Recovery Time

-

0

tWR

0

-

ns

tiNS

Interrupt Set Time

-

35

-

40

-

45

50

-

55

ns

Interrupt Reset Time

-

35

-

40

-

45

50

-

55

-

60{70

tlNR

-

6D{70

ns

0

NOTES:
1. DOC to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.

TIMING WAVEFORM OF INTERRUPT MODE (1,2)
LEFT SIDE SETS INTR :

~---------twc--------~

WRITE 3FF

4 _ t I N S_ _ _

RIGHT SIDE CLEARS INTR :

_"~\~\\-...\~\__\_\~\.....a.\\_\~\.~\.~\to....a\\......a.\.~\.--\_\~&_."'----..t____I
t,,,

______- :-____________,-. ___1

NOTES:
1. eEL = CE R= ~l
2. INTl and INTR are reset to VOH during power up.

5-11

IDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS aK (1 K x a-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF INTERRUPT MODE

(1,2)

. RIGHT SIDE SETS INT L:
two
WRITE 3FE

ADDRR
tAS
RNi R

..
INTl

f"

LEFT SIDE CLEARS INTL:

.Io...\\~'\~\'\-.3ro.\~\~'\.Io-\:L..J'\~\\~\~'\..Ji,..'\~\~\-.3ro.\\~'\~\.10.",;'\~\~"--__~
_ _--'/

----_____________~___l

!'NA

NOTES:
1. CE l = CE R= "'l
2. INTR and INTl are reset (high) during power up.

16-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
LEFT
RNi
BUSY

RIGHT
ANi

- - + -____~-_t -BU-S-Y

IDT7130

RNi

MASTER -BU-S-Y

+5V

+5V

NOTE:

1. No arbitration in IDT7140 (SLAVE). BUSY-IN inhibits write in IDT7140 (SLAVE).

5-12

~----tt---

ANi
BUSY

1DT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Contention occurs when both left and right ports are active and
both addresses match. When this situation occurs, the on-chip arbitration logic determines access. Two modes of arbitration are
provided: (1) if the addresses match and are valid before CE, onchip control logic arbitrates between CELand CE R for access; or (2)
if the CEs are low before an address match, on-chip control logic
arbitrates between the left and right addresses for access (refer to
Table III). In either mode of arbitration, the delayed port's BUSY flag
is set and will reset when the port granted access completes its
operation.

FUNCTIONAL DESCRIPTION:
The IDT7130/40 provides two ports with separate control, address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7130/40 has an automatic
power down feature controlled by CE. The CE controls on-chip
power down circuitry that permits the respective port to go into a
standby mode when not selected (CE high). When a port is enabled, access to the entire memo!YJl.rray is permitted. Each port
has its own Output Enable control (OE).ln the read mode, the port's
(JE turns on the output drivers when set LOW. Non-contention
READ/WRITE conditions are illustrated in Table I.
The interrupt flag (INll permits communication between ports
or systems. If the user chooses to use the interruptfunction, a memory location (mail box or message center) is assigned to each port.
The left port interrupt flag (INT d is set when the right port writes to
memory location 3FE (HEX). The left port clears the interrupt by
reading address location 3FE. Likewise, the right port interrupt fiag
(INTR) is set when the left port writes to memory location 3FF (HEX)
and to clear the interrupt flag (INTR ), the right port must read the
memory location 3FF. The message (8 bits) at 3FE or 3FF is userdefined. If the interrupt function is not used, address locations 3FE
and 3FF are not used as mail boxes, but as part of the random access memory. Refer to Table II for the interrupt operation.

DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:
Expanding the data bus width to sixteen-or-more-bits in a dualport RAM system implies that several chips will be active at the
same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one
will activate its BUSYL while another activates its BUSYR signal.
Both sides are now busy and the CPUs will wait indefinitely for their
port to become free.
To avoid this "Busy Lock-Out" problem, IDT has developed a
MASTER/SLAVE approach where only one hardware arbitrator, in
the MASTER, is used. The SLAVE has BUSY inputs which allow an
interface to the MASTER with no external components and with a
speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed, until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a
contention situation. Conversely, the write pulse must extend a
hold time past BUSY to ensure that a write takes place after the contention is resolved. This timing is inherent in all dual-port memory
systems where more than one chip is active at the same time.
The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs,
the write to the SLAVE will be inhibited due to BUSY from the
MASTER.

ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip enable match down to 5ns minimum and determine which port has
access. In all cases, an active BUSY flag will be set for the delayed
port. .
The BUSY flags are provided for the situation when both ports
simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic wi II determine which port has
access and sets the delayed port's BUSY flag. BUSY is set at
speeds that permit the processor to hold the operation and its respective address and data. It is important to note that the operation
is invalid for the port that has BUSY set LOW. The delayed port will
have access when BUSY goes inactive.

5-13

LJI

JDT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS BK (1 K x B-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLES
TABLE 1- NON-CONTENTION
READ/WRITE CONTROL (4)
LEFT OR RIGHT PORT (1)
OE

CE

R/W

FUNCTION

00-7

X

H

X

Z

Port Disabled and in Power Down
Mode.lsB2 or ISB4

X

H

X

Z

CER = CEL = H. Power Down
Mode.lsBl or ISB3

L

L

X

DATA IN

Data on Port Written Into Memory(2)

DATA oUT

Data in Memory Output on Port (3)

H

L

L

H

L

H

Z

High Impedance Outputs

NOTES:

1. AOL -A9L~ AOR-A9R
2. If BUSY = L. data is not written.
3. If BUSY = L. data may not be valid. see tWDD and tODD timing.
4. H = HIGH. L = LOW. X = DON'T CARE. Z = HIGH IMPEDANCE

TABLE II-INTERRUPT FLAG (1.4)
RIGHT PORT

LEFT PORT
CE l ·

R/WL
L

L

X

X
X

X
X

L

OE l

AOl - A9l

INTl

X
X

3FF

X

X
X

X

X

L

3FE

NOTES:
1. Assumes BUSYL = BUSYR
2. If BUSY L = L. then NC.

FUNCTION

A Ol -A 9R

CE R

OE R

X
X

X

X

X

L(2)

L

L

3FF

H(3)

Reset Right INTR Flag_

L (3)

L

L

X

3FE

X

Set Left INT L Flag

H(2)

X

X

X

X

X

Reset Left INT L Flag

R/W R

= H.

3.

4.

INTR
Set Right INT R Flag

If BUSYR = L. then NC.
H = HIGH. L= LOW. X = DON'T CARE. NC= NO CHANGE

TABLE 111- ARBITRATION (2)
FLAGS

RIGHT PORT

LEFT PORT

(1)

FUNCTION
CE l

AOl - A9l

CE R

BUSYL

AOL - ASR

BUSYR

H

X

H

X

H

H

L

Any

H

X

H

H

No Contention

H

X

L

Any

H

H

No Contention

L

~ AOR-A9R

L

H

H

No Contention

~

AOL -A9L

No Contention

ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L

LV5R

L

LV5R

H

L

L-PortWins

L

RV5L

L

RV5L

L

H

R-PortWins

L

Same

L

Same

H

L

Arbitration Resolved

L

Same

L

Same

L

H

Arbitration Resolved

CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL5R

= AOR-A9R

LL5R

= AOL -A9L

H

L

L-portWins

RL5L

= AOR-A9R

RL5L

= AOL -A9L

L

H

R-PortWins

LW5R

= AOR-A9R

LW5R

= AOL -A9L

H

L

Arbitration Resolved

LW5R

= AOR-A9R

LW5R

= AOL -A9L

L

H

Arbitr.ation Resolved

NOTE:
1. INT Flags Don't Care.
2. X = DON'T CARE. L = LOW. H = HIGH
LV5R = Left Address Valid ;;:: 5ns before right address.
RV5L = Right Address Valid ;;:: 5ns before left address.

Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left CE = LOW ;;:: 5ns before Right CEo
RL5L = Right CE = LOW;;:: 5ns before Left CEo
LW5R = Left and Right CE = LOW within 5ns of each other.

5-14

---_.. - - - - - _ . _ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1DT7130SA/LA AND IDT7140SA/LA
CMOS DUAL-PORT RAMS 8K (1 K x 8-BIn

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XXX)(

A

Device Type

Power

999
Speed

A

A

Package

Process/
Temperature
Range

y:,onk
p
C

J

~--------------~ L48
L52

F

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

35
45
55
70
90
100
120

ILA

~--------------------------~I SA
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - j

7130
7140

5-15

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

Plastic DIP
Sidebraze DIP
Plastic Leaded Chip Carrier
48-Pin Leadless Chip Carrier
52-Pin Leadless Chip Carrier
Flatpack
Commercial Only

1

Speed in Nanoseconds
Military Only
Low Power
Standard Power
aK (1 K x a-Bit) MASTER Dual-Port RAM
8K (1 K x 8-Bit) SLAVE Dual-Port RAM

FEATURES:

DESCRIPTION:

• High-speed access
- Military: 45/55/70/90/100/120ns (max.)
- Commercial: 35/45/55/70/90/100ns (max.)
• Low-power operation
- IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
- IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
• MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
• On-chip port arbitration logic (IDT7132 only)

The IDT7132/IDT7142 are high-speed 2K x 8 dual-port static
RAMs. The IDT7132 is designed to be used as a stand-alone 8-bit
dual-port RAM or as a "MASTER" dual-port RAM together with the
IDT7142 "SLAVE" dual-port in 16-bit-or-more word width systems.
USing the IDT MASTER/SLAVE dual-port RAM approach in 16-ormore-bit memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CEMOS ™ high-performance technology, these devices typically operate on only 325mW of power at
maximum access times as fast as 35ns. Low-power (LA) versions
offer battery backup data retention capability, with each dual-pori
typically consuming 20011W from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin sidebraze
or plastic DIP, 48- or 52-pin LCC, 52-pin PLCC, and a 48-lead
flat pack.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

•
•
•
•
•
•

BUSY output flag on IDT7132; BUSY input on IDT7142
Fully asynchronous operation from either port
Battery backup operation-2V data retention
lTL-compatible, single 5V±10% power supply
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing# 5962-87002 is pending listing on
this function. Refer to Section 2/page 2-4.

FUNCTIONAL BLOCK DIAGRAM
RIWR

RIWL
CE L

D-----\--+--

CER

O'E L

'---0----

O'ER

.----+-.f-----

AlOR
A7R

A10L
A7L

•

I/O OR

I/CoL
I--~-----

1/07L

1/07R

B'OSVR(l)

'SOSVL(l)

r---,..-+----.....

A6L
•

ROW
SELECT

MEMORY
ARRAY

A6R

ROW
SELECT

AOL

AOR
A10L -------t~

ARBITRATION

AOL -------t~

LOGIC

CE L ----........

(1017132
ONLy)

.....- - - - - AlOR
....- - - - - AOR

10+----- CE R
..,f------ RIWR

RIW L -------t~L.....,..._ _..,........

NOTES:
1. 1017132 (MASTER): OOSVis open drain output and requires pullup resistor.
1017142 (SLAVE): 'EiOS? is input.
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
OSC-1001/-'

5-16

IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K X S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

INDEX~ .r-'Mjr1'~" . .Jct,. .,.~,. ,I~n~-r. .JHtr 1'~."~. . ,.a:"M~, I~-r~"M!. ,.~ a:
L.JL..IL~L..II.JIIL-'L.JL

6 5 4

3

J8
J9
J 10
J 11
J 12
J 13
J 14
J 15
J 16
J 17
J 18

2

,-'L",L

4847 46 45 44 43
42::::
41 C
40e
3ge
38 e
L48-1
37e
I I

L~

&

36::::

F48-1

35e
34::::
33e
32::::
31:::

1920212223242526 272829 30

AOR
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/07R
I/06R

48-PIN LCC/FLATPACK
TOP VIEW

. .J . .J 5(JI~ti . .J 8

a:~I~ (J

g;

INDEX~ r-"':'M~......,..i.....z~ffi","a:""""~""",,,>","~~a:~ffi....z~<"",",

DIP
TOP VIEW

LJ LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ

7 6 5 4 3 2 U 5251 50 49 48 47
J8
1
461:
J9
J 10
J 11
J 12
41 I:
J 13
J52-1
40 I:
&
A7L J 14
L52-1
391:
ASL J 15
3a::
A9L J 16
371:
I/OoL
361:
I/0 1L
35[
0
I/ 2L
Me
I/0 3L J~
2122 23 24 2526 272829 30313233
AlL
A2L
A3L
A4L
A5L
A6L

r, r-, r, ,.,

I' ,., ,.,

OER
AOR
A1R
A2R
A3R
A4R
A5R
A6R

A7R
ASR
A9R

N/C
I/07R

r, r., ,., r1 ,., "

52-PIN LCC/PLCC
TOP VIEW

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM
TA

RATING
Terminal Voltage
with Respect to
GND
Operating
Temperature

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE

Oto +70

-55 to + 125

Military

°C

Commercial

TslAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.5

1.5

W

lOUT

DC Output Current

50

50

mA

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V

±

10%

O°C to +70°C

OV

5.0V

±

10%

Vce

RECOMMENDED DC OPERATING CONDITIONS
MIN.

TYP.

MAX.

Vcc

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H

Input High Voltage

-

6.0

V

V1L

Input Low Voltage

-

0.8

V

SYMBOL

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

PARAMETER

2.2
-0.5(1)

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

5-17

UNIT

IDT7132SA/LA AND 1DT7142SA/LA
CMOS DUAL·PORT RAM 16K(2K X 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(Vee = 5.0V±10%)

SYMBOL
Ilul

Input Leakage Current

Vee ,,; 5.5V, \'IN = OV to Vee

Illol

Output Leakage Current

CE = \'IH ,VOUT = OV to Vee

IDT7132LA
1DT7142LA
MAX.
MIN.

IDT7132SA
1DT7142SA
MAX.
MIN.

TEST CONDITIONS

PARAMETER

-

10

-

UNIT

5

J.l.A

10

-

5

J.l.A

VOL

Output Low Voltage (110 0 - 1/07)

10l = 4mA

-

0.4

-

0.4

V

VOL

Open Drain Output Low
Voltage (BUSY)

10l = 16mA

-

0.5

-

0.5

V

VOH

Output High Voltage

10H= -4mA

2.4

-

2.4

-

V

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1)
SYMBOL

PARAMETER

TEST CONDITION VERSION

(Vee = 5.0V±10%)

7132 X 35(2) 7132 X 45 7132 X 55 7132 x 70 7132 x 90 7132 X 100/120(3
7142 x 35(2) 7142 x 45 7142 x 55 7142 x 70 7142 x 90 7142 X 100/120(3 UNIT
TYP. MAX. TYP.MAX. TYP.MAX. TYP.MAX. IrYP.MAX. TYP.

--

-

75
75

195
155

r.:

25
25

65
45

SA
CE L or CE R ::: V1H MIL.
LA
Active Port Outputs
Open, f = fMAX (4)
COM'L.

-

-

40
40

130
95

-

1.0
0.2

MIL.

SA

COM'L.

Et

MIL.

SA

COM'L.

Dynamic Operating
Current (Both Ports
Active)

CE :=\'IL
Outputs Open
f = fMAl( 4)

Standby Current
(Both Ports - TTL
Level Inputs)

CEl and CE R ===\'IH
f = fMAX (4)

IS92

Standby Current
(One Port- TTL
Level Inputs)

IS93

SA
Both Ports CE land MIL.
LA
Full Standby Current
CER~Vee -0.2V
(Both Ports - All
\'IN
===
Vee
-0.2V
or
CMOS Level Inputs)
\'IN ~ 0.2V, f = 0(4) COM'L.

Icc

IS91

IS94

LA

LA

Et

r.:

One Port CE L or
SA
MIL.
LA
CE R ::: Vee- 0 .2V
Full Standby Current
\'IN
~
Vee
-0.2V
or
(One Port-All
CMOS Level Inputs) \'IN ~ 0.2V
Active Port Outputs COM'L.
Open, f = f MAX (4)

r.:

--

-

-

65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2

225
180
180
135
65
55
60
40
135
110
110
85
30
10

65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2

200
160
180
130
65
45
55
35
125
100
110
75
30
10

65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2

190
155
180
130
65
45
55
35
125
100
110
75
30
10

15
4

1.0
0.2

15
4

1.0
0.2

15
4

1.0
0.2

15
4

1.0
0.2

15
4.0

-

230
185
190
145
65
55
65
45
135
110
120
85
30
10

15
4

1.0
0.2

--

-

MAX.

65 230
65 185
65 180
65 140
25
65
55
25
25 65
25
55
40 135
40 110
40 115
85
40
1.0 30
0.2 10

75
75
75
75
25
25
25
25
40
40
40
40
1.0
0.2

mA

mA

mA

mA

-

-

-

40
35

125
95

40
35

120
90

40
35

115 40
85 35

110
80

40
35

110
80

40
35

115
90

40
35

105
80

40
35

100
75

40
35

100 40
75 35

95
70

40
35

95
70

mA

NOTES:
1. x in part numbers indicates power rating (SA or LA).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. fMAX = All inputs cycling atf = 1It Rc--

ns

-----

-----------------------------------------------------------------------------

1DT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
PARAMETER

SYMBOL

(6)

7132 X 35(2) 7132 x 45
7132 x 100/120(3)
7132 x 70
7132 x 90
7132 x55
7142 x 45
7142 x 100/120(3) UNIT
7142 x 35(2)
7142 x 90
7142 x 55
7142 x 70
MAX. MIN.
MAX.
MIN. MAX, MIN.
MAX. MIN. MAX. MIN. MAX. MIN.

WRITE CYCLE
twc

Write Cycle Time (5)

35

45

tEW

Chip Enable to End of Write

30

35

90

-

100/120

85

-

901100

0

-

50

-

55

-

55/65

0

-

0

-

0

55

-

70

40

-

50

ns

-

ns

90/100

-

ns

0

-

ns

ns

0

-

20

-

20

-

30

-

40

-

40

-

-

20

-

30

-

35

-

40

-

40

ns

0

-

0

-

0

-

0

-

0

-

ns

20

-

30

-

35

-

40

-

-

0

-

0

-

0

-

0

tAW

Address Valid to End of Write

30

35

tAS

Address Set-up Time

0

0

twp

Write Pulse Width

30

35

tWR

Write Recovery Time

0

0

tDW

Data Valid to End of Write

20

tHZ

Output High Z Time(l.4)

tDH

Data Hold Time

0

twz

Write Enabled to Output in
High Z(l,4)

-

tow

Output Active From End of Write (1,4)

0

15

15

-

0

40
0
40

50

NOTES:
1. Transition is measured ±5OOmV from low or high impedance voltage with load (Figures 1, 2 and 3).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination, twc = tBAA + t wP .
6. ·x· in part numbers indicates power rating (SA or LA).

5-21

85
0

40/50

-

ns

ns

ns
ns

••

IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, (R/W CONTROLLED TIMING)

(1,2,3,7)

two
ADDRESS

~

----I

)K

K

..

t

(6}-

HZ

/V
..
~

tAW

//

r\.

..

~tAS

t

(7)

tWR

Wp

'",-

,/

I'

-

_ t Wi 6 } _

..
DATAoUT

tow

<,(4».·:~ I -

:: ...

(4)

--tow

t OH -

./

'"

./

I"

TIMING WAVEFORM OF WRITE CYCLE NO.2, (CE CONTROLLED TIMING)

(1,2,3,5)

two
ADDRESS

)K

:=)K
tAW

_t

AS

1
1

)1'
•

tEW

RtW
I;-t

1'-

ow

-

tWR

-

f---tOH

"

-./1

NOTES:
1.
2.
3.
4.
5.
6.
7.

RiW must be high during all address transitions.
A write occurs during the overlap (tEW or twp ) of a low CE" and a low RIW.
t WR is measured from the earlier of CE" or Rm going high to the end of the write cycle.
During this period, the I/O pins are in the output state and input signals must not be applied.
If the ~ low transition occurs simultaneously with or after the RiW low transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig).
If DE is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (t wz + t ow) to allow the I/O drivers to turn off and
data to be placed on the bus for the required tow. If OE is high during an Rm controlled write cycle, this requirement does not apply and the write
pulse can be as short as the specified t wP .

5-22

---------------------------------------------

IDT7132SAlLA AND IDT7142SAlLA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

PARAMETER

7132 x 35(1)
7132 x 45
7132 X 100/120(2)
7132 x 55
7132 x 70
7132 x 90
7142 x45
7142 X 100/120(2) UNIT
7142 X 35(1)
7142 X 55
7142 X 70
7142 X 90
MIN. MAX. MIN.
MAX. MIN. MAX. MIN. MAX. MIN.
MAX. MIN.
MAX.

BUSY TIMING
0

-

0

20

-

20

-

45

-

45

-

45

40

40

-

45

BO

-

90

-

100

55

-

70

-

Note 5

-

Note 5

-

0

-

0

20

-

20

-

35

-

30

35

-

-

30

-

30

-

35

-

25

-

25

-

30

70

-

45

-

tWB

Write to BUSY (3.6)

0

tWH

Write Hold After BUSy(7)

20

-

tBAA

BUSY Access Time to Address

-

35

tBDA

BUSY Disable Time to Address

-

t BAC

BUSY Access Time to Chip Enable

t BDc

BUSY Disable Time to Chip Enable

tWDD

Write Pulse to Data Delay (4)

-

60

tDDD

Write Data Valid to Read Data
Delay (4)

-

35

tBDD

BUSY Disable to Valid Data (5)

-

Note 5

-

tAPS

Arbitration Priority Set-up Time

5

-

5

-

Note 5

-

5

-

-

35
30

5

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. For SLAVE part (IDT7142) only.
4. Port-to-port delay through RAM cells from writing port to reading port.
5. tBDD is a calculated parameter and is the greater of O. tWDD - twp (actual) or tDDD - tDw(actual).
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention.
B. ·x· in part numbers indicates power rating (SA or LA).

5-23

-

5

45

0

-

ns

20

-

ns

-

50/60

ns

50/60

ns

50/60

ns

50/60

ns

120/140

ns

90

-

100/120

ns

Note 5

-

NoteS

ns

45

-

5

-

ns

la

1DT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ WITH BUSY

'I

MATCH

J\

1

J ..

~

DATAIN

J

Jl
J~

R

VALID

MATCH

\.~

/

~tBDD-

t BDA -

'-~

BUSYL

-.'{J

tWDD

~(

DATA OUT L
tDDD

TIMING WAVEFORM OF WRITE WITH BUSY

twp

RiW

~t~
BUSY

[t~

I

"

5-24

VALID

IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x a-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
eEL VALID FIRST:
ADDR·
LAND R

~R

BUSYR

==><

>C

ADDRESSES MATCH

~t~-*~t'OO~*_

eE R VALID FIRST:
ADDR
LAND R

==><

>C

ADDRESSES MATCH

~t~_{ ~t'OO~*_
TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION
LEFT ADDRESS VALID FIRST:
1 - - . - - - t RC OR

twc ----I~

ADDRESSES MATCH

ADDRESSES DO NOT MATCH

RIGHT ADDRESS VALID FIRST:
\ 4 - - - - t RC OR twc ----~
ADDRESSES MATCH

ADDRESSES DO NOT MATCH

NOTE:

5-25

(1)

IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

16-BIT MASTERISLAVE DUAL-PORT MEMORY SYSTEMS
LEFT

RIGHT

....

_

~

RNi

RNi

10T7132
MASTER

BUSY

4~+5V

...

-

NOTE:

------

RNi

-

BUSY

+ 5V -,,/\/\/'-

1~~J~~l)

BUSY

RNi
BUSY

1. No arbitration in 10T7142 (SLAVE). BUSY-IN inhibits write in 10T7142 (SLAVE).

5-26

-..
~

IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES
if the CEs are low before an address match, on-chip control logic
arbitrates between the left and right addresses for access (refer to
Table II). In either mode of arbitration, the delayed port's BUSY flag
is set and will reset when the port granted access completes its operation.

FUNCTIONAL DESCRIPTION:
The I0T7132/42 provides two ports with separate control, address and I/O pins that permit independent access for reads or
writes to any location in memory. These devices have an automatic
power-down feature controlled by CE. The CE controls on-chip
power-down circuitry that permits the respective port to go into a
standby mode when not selected (cr high). When a port is enabled, access to the entire memory array is permitted. Each port
has its own Output Enable control (OE). In the read mode, the port's
iJE turns on the output drivers when set LOW. Non-contention
REAO/WRITE conditions are illustrated in Table I.

DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:'

The arbitration logic will resolve an address match or a chip enable match down to 5ns minimum and determine which port has
access. In all cases, an active BUSY flag will be set for the delayed
port.
The BUSY flags are provided for the situation when both ports
simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic will determine which port has
access and sets the delayed port's BUSY flag. BUSY is set at
speeds that permit the processor to hold the operation and its respective address and data. It is important to note that the operation
is invalid for the port that has BUSY set LOW. The delayed port will
have access when BUSY goes inactive.
Contention occurs when both left and right ports are active and
both addresses match. When this situation occurs, the on-chip arbitration logic determines access. Two modes of arbitration are
provided: (1) if the addresses match and are valid before CE, onchip control logic arbitrates between CJ;. and CE Rfor access; or (2)

Expanding the data bus width to sixteen-or-more-bits in a dualport RAM system implies that several chips will be active at the
same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one
will activate its BUSYL while another activates its BUSYRsignal.
Both sides are now busy and the CPUs will wait indefinitely for their
port to become free.
To avoid this "Busy Lock-Out" problem, lOT has developed a
MASTER/SLAVE approach where only one hardware arbitrator, in
the MASTER, is used. The SLAVE has i3ITSY inputs which allow an
interface to the MASTER with no external components and with a
speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed, until after the BDSY input has settled.Otherwise, the SLAVE chip may begin a write cycle during a
contention situation. Conversely, the write pulse must extend a
hold time past BCJSY to ensure that a write cycle takes place after
the contention is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the same
time.
The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs,
the write to the SLAVE will be inhibited due to BUSY from the
MASTER.

TRUTH TABLES

CAPACITANCE

ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:

SYMBOL

TABLE 1- NON-CONTENTION
READ/WRITE CONTROL
LEFT OR RIGHT PORT (1)

CIN
COUT

CE

OE

X

H

X

Z

X

H

X

Z

L

L

X

DATA IN

Data on Port Written Into Memory(2)

H

L

L

DATA OUT

Data in Memory Output on Port (3)

H

L

H

Z

Input Capacitance
Output Capacitance

CONDITIONS

MAX.

UNIT

VIN = OV

11

pF

VOUT= OV

11

pF

NOTE:
1. This parameter is sampled and not 100% tested.

FUNCTION

R/W

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

00-7

Port Disabled and in Power Down
Mode, ISB2 or ISB4

CE R = eEL = H. Power Down
Mode,IsB1 or ISB3

High Impedance Outputs

NOTES:
1. AOL - A10L '" AOR - A10R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see twoo and t BOO timing.
H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE

5-27

IDT7132SA/LA AND IDT7142SA/LA
CMOS DUAL-PORT RAM 16K (2K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE II-ARBITRATION (2)
LEFT PORT

FLAGS (1)

RIGHT PORT

FUNCTION
CE L

CE R

AOL - A 10L

A oR - A 10R

BUSYL

BUSYR

H

X

H

H

No Contention

Any

H

X
X

H

L

H

H

No Contention

H

X

L

Any

H

H

No Contention

H

H

No Contention

L

L
'" AOR- A l0R
'" AOL -A!oL
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L

LV5R

L

LV5R

H

L

L-PortWins

L

RV5L

L

RV5L

L

H

R-PortWins

L

Same

L

Same

H

L

Arbitration Resolved

L

Same

L

. Same

L

H

Arbitration Resolved

CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL5R

= AOR- A lOR

LL5R

= AOL -A1OL

H

L

L-PortWins

RL5L

= AOR- A l0R

RL5L

= AOL -A1OL

L

H

R-PortWins

LW5R

= AOR-A'OR
= AOR-AlOR

LW5R

= AOL -A'OL

H

L

Arbitration Resolved

LW5R

= AOL ":A'OL

L

H

Arbitration Resolved

LW5R

NOTE:
1. X = DON'T CARE, L = LOW, H = HIGH
2. LV5R = Left Address Valid ~ 5ns before right address.
RV5L = Right Address Valid ;:: 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left ~ =. LOW ~ 5ns before Right ~.
RL5L = Right CE = LOW ~ 5ns before Left CEo
LW5R = Left and Right ~ = LOW within 5ns of each other.

ORDERING INFORMATION
lOT

De~ype

999

A

A

Speed

Package

Process!
Temperature
Range

y:~k
P
C
J
~---------------~ L
F
35
45
55

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze DIP (600 mil)
Plastic Leaded Chip Carrier
Leadless Chip Carrier-indicate 48- or 52-pin
Flatpack
Commercial Only

1

Speed in Nanoseconds

~------------------------;70

90

100
120

ILA

~---------------------------~I SA
~

_________________________________________---I 7132
7142

5-28

Military Only
Low Power
Standard Power
16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM

- - -......_ - - - - - - - - - - - - - - - - - - - _ .

FEATURES:

DESCRIPTION:

• High-speed access
- Military: 45/55/70ns (max.)
- Commercial: 35/45/55ns (max.)

The IDT71321/IDT71421 are high-speed 2K x 8 dual-port static
RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used as a stand-alone 8-bit
dual-port RAM or as a "MASTER" dual-port RAM, together with the
IDT71421 "SLAVE" dual-port, In 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE dual-port RAM approach in
16-or-more-bit memory system applications results in full-speed,
error-free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate c o n - i i i
trol, address and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CEMOS ™ high-performance technology, these devices typically operate on only 325mW of power ~t,
maximum access times as fast as 35ns. Low-power (LA) versions
offer battery backup data retention capability with each port typically consuming 200~W from a 2V battery.
The IDT71321/71421 devices are packaged in 52-pin LCCs and
PLCCs. Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.

• Low-power operation
- IDT71321/421SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
- IDT71321/421LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
• Two INT flags for port-to-port communications
• MASTER IDT71321 easily expands data bus width to
16-or-more-bits using SLAVE IDT71421
• On-chip port arbitration logic (IDT71321 only)
•
•
•
•
•
•

BUSY output flag on IDT71321; BUSY input on IDT71421
Fully asynchronous operation from either port
Battery backup operation-2V data retention
TTL-compatible, single 5V ±10% power supply
Available in popular hermetic and plastic packages
Military product compliant to MIL~STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
RA"L----~----~r-~--__----------~
'OE L ---+-+------a

RA"R

crR

DEL - - - - - ( : L - J
A10L
A7L

OE R
A10R
A7R

•

•

I/O OR

IIOOL

1I07R

1/07L

'lIDSVR(l)

'lIDSVL(l)

A6R

A6L
ROW
SELECT

MEMORY
ARRAY

ROW
SELECT
AOR

AOL
A10L
AOL
eEL
R!ill L

A10R

----------1-.,

ARBITRATION
AND INTERRUPT
LOGIC

AOR

1+--------- eER
RA"R
INT

INT L(2)

(2)

R

NOTES:

1. ID171321 (MASTER): tiOS? is open drain output and requires pullup resistor. IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor.
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
OSC-l031/-

1987 Integrated DevIce Technology. Inc.

5-29

IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL·PORT RAMS 16K(2KxB-BIT) WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

i~jg~~~~~~~~ l
J

LJ LJLJLJLJ LJII LJLJLJ LJ

7 6 5 4 3 2

1

All
A2l
A3l
A4l
A5l
A6l
A7l
A8l
A 9l
IIOOl
IIOll
I/02l
II0 3l

I

I.

U 5251 50

J52-1
&
L52-1

J

49 48 47
46
45
44
43
42
41
40
39
38
37
36

..J ..J ..J ..J

0

CC

O'ER
AOR
AIR
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A 9R
NC
I/0 7R

a: cc a: cc a: cc

U
'OO'r:$Ozzr:J6ooooC5
::::::::::::::::::: (!J:::::-:::::::::::::::::::::::::::::::

LCC/PLCC
TOP VIEW

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

GRADE
Military

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V ± 10%

Vcc

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TS1AS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to + 150

°C

MIN.

TYP.

MAX.

Pr

Power Dissipation

1.5

1.5

W

Vee

Supply Voltage

4.5

5.0

5.5

V

lOUT

DC Output Current

50

50

mA

GND

Supply Voltage

0

0

0

V

V1H
V1l

Input High Voltage

2.2

-

6.0

V

-

0.8

V

Commercial

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those Indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

PARAMETER

Input Low Voltage

-0.5(1)

NOTE:
1. V1l (min.) = -3.0V for pulse width less than 20ns.

5-30

UNIT

IDT71321SAlLA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(Vee = 5.0V ±10%)

SYMBOL
Ilu l

PARAMETER

IDT71321SA
IDT71421SA
MIN.
MAX.

TEST CONDITION

Input Leakage Current

Vee = 5.5V, \'IN

=

-

OV to Vee

10

IDT71321LA
1DT71421LA
MIN.
MAX.

-

UNIT

5

~A

Output Leakage Current

CE = VIH , VOUT = OV to Vee

-

10

-

5

~A

Val

Output Low Voltage (1/0 0 - 1107)

IOl = 4mA

-

0.4

-

0.4

V

VOL

Open Drain Output Low
Voltage (BUSY/INT)

IOl = 16mA

-

0.5

-

0.5

V

VOH

Output High Voltage

IOH= -4mA

2.4

-

2.4

-

V

Illol

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1)
SYMBOL

Icc

IS61

IS62

ISB3

ISB4

PARAMETER

TEST CONDITION

VERSION

SA
LA
SA
COM'L. LA
SA
Standby Current
MIL.
LA
(Both Ports - TTL
CE land CE R 2: \'IH
SA
f = fMAX(5)
Level Inputs)
COM'L. LA
SA
Standby Current
CEl or CE R 2: '-'iH MIL.
LA
(One Port-TTL
Active Port Outputs
SA
Open, f = fMAX(5)
Level Inputs)
COM'L. LA
SA
Both Ports CE l and MIL.
LA
Full Standby Current
CE R 2: Vee -0.2V
(Both Ports - All
CMOS Level Inputs) \'IN 2: Vee -0.2V or COM'L. SA
VIN S 0.2V, f = 0(5)
LA
Dynamic Operating
Current (Both Ports
Active)

CE =\'Il
Outputs Open
f = fMAX(5)

-

-

-

75
75

195
155

(Vee = 5.0V ±10%)

71321x45
71321x55
71421x45
71421x55
TYP.(4)
TYP,I4)
MAX.
MAX.

-

--

40
40

130
95

-

-

1.0
0.2

15
4.0

1.0
0.2

15
4.0

1.0
0.2

15
4.0

-

-

SA
LA

-

-

40
35

125
95

40
35

120
90

40
35

110
80

SA
LA

40
35

115
90

40
35

115
80

40
35

100
75

-

-

-

-

-

-

25
25

65
45

230
185
190
145
65
55
65
45
135
110
120
85
30
10

65
65
65
65
25
25
25
25
40
40
40
40
1.0
0.2

230
185
180
140
65
55
65
45
135
110
115
85
30
10

71321x70(3)
71421x70(3)
UNIT
TYP.(4)
MAX.

75
75
75
75
25
25
25
25
40
40
40
40
1.0
0.2

MIL.

One Port CEl or
MIL.
CE R 2: Vee -0.2V
Full Standby Current
\'IN
2:
Vee
-0.2V
or
(One Port-All
CMOS Level Inputs) \'IN S 0.2V
Active Port Outputs COM'L.
Open, f = ft.1AX(5)

71321x35(2)
71421x35 (2)
TYP,I4)
MAX.

65
65

-

225
180
-

mA

-

25
25

65
55

-

-

40
40

135
110

-

-

1.0
0.2

30
10

-

-

mA

mA

mA

mA

NOTES:
1. ·x· in part numbers indicates power rating (SA or LA).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. Vee = 5V, TA = +25°C
5. f MAX = l/t RC = All inputs cycling at f = 1It Rc(exceptOutput Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level
standby IS63 '

5-31

IDT71321 SA/LA AND IDT71421 SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS

DATA RETENTION CHARACTERISTICS

VDR

(L Version Only)

PARAMETER

SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT71321 LA/IDT71421 LA
TYP.(1)
MIN.
MAX.

TEST CONDITION

Vcc for Data Retention

ICCDR

Data Retention Current

Vcc = 2.0V. CE ;:: Vcc -0.2V

t CDR (3)

Chip Deselect to Data Retention Time

\IN ;:: Vcc

-0.2V or

\IN

I MIL.
ICOM'L.

:5 0.2V

t

(3)
Operation Recovery Time
R
NOTES:
1. Vcc = 2V, TA = +25°C
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.

UNIT

2.0

-

-

V

-

100

4000

Jl.A

-

100

1500

Jl.A

0

-

-

ns

t RC (2)

-

-

ns

DATA RETENTION WAVEFORM

DATA RETENTION MODE
4.5V

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND t03.0V
5ns
1.5V
1.5V
See Figures 1, 2 & 3

5V

DATAoUT

~

n50.

.

5V

125Ofl
DATA OUT
1oopF*
30pF for
& 45ns
versions)

~5ns

Figure 1. Output Load

~

7750.

5V

125on

.5pF*

Figure 2. Output Load
(for tHz,tLZ,t wz , and tow)

* Including scope and jig.

5-32

-il'OO

27on

BUSY

.

P
F'

Figure 3. BUSY and INT
Output Load

1DT71321 SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

71321 SA/LA3S (2)
71421SA/LA3S(2)
MIN.
MAX.

PARAMETER

71321 SA/LA4S
71421SA/LA4S
MAX.
MIN.

71321 SA/LASS
71421 SA/LASS
MIN.
MAX.

71321SAlLA70(3)
71421SAlLA70(3)
MIN.
MAX.

UNIT

READ CYCLE
t RC

Aead Cycle Time

35

-

45

-

55

-

70

-

tM

Address Access Time

-

35

-

45

55

ns

Chip Enable Access Time

-

35

-

45

70

ns

tAOE

Output Enable Access Time

-

25

-

30

-

70

tACE

-

40

ns

tOH

Output Hold From Address Change

0

0

-

0

tLZ

Output Low Z Time (1.4)

5

-

5

-

5

-

5

-

ns

tHZ

Output High Z Time (1.4)

-

15

-

20

-

30

-

35

ns

tpu

Chip Enable to Power Up Time (4)

0

-

0

-

0

-

0

-

ns

tpD

Chip Disable to Power Down Time (4)

-

50

-

50

-

50

-

50

ns

55
35

0

NOTES:
1. Transition is measured ±SOOmV from low or high impedance voltage with load (Figures 1. 2 and 3).
2. O°C to+ 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.

TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE

(1,2,4)

ADDRESS

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE

(1,3)

1 4 - - - - - t A c E - - - - -..~1
-----'\.1

DATA OUT

Icc
CURRENT

_

~---tLZ--__-..I
_

~_

pu+l
t

50%

~
_
tpD
50%

Iss
NOTES:
1. ANi is high for Read Cycles.
2. Device is continuously enabled. CE = '-IL'
3. Addresses valid prior to, or coincident with. CE transition low.
4. 'O'E = V1L

S-33

ns

ns

IDT11321SAlLA AND IDT11421SAlLA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

71321 SAlLA3S(2)
71421 SA/LA3S(2)
MIN.
MAX.

PARAMETER

71321SAlLA4S
71421SA/LA4S
MIN.
MAX.

71321 SA/LASS
71421 SA/LASS
MIN.
MAX.

71321 SA/LA70(3)
71421 SA/LA70(3)
MIN.
MAX.

UNIT

WRITE CYCLE
70

40

-

a

-

a

40

-

50

a

-

a

20

-

20

-

0

-

15

-

-

0

two

Write Cycle Time (5)

35

tEW

Chip Enable to End of Write

30

tAW
t AS

Address Valid to End of Write

30

Address Set-up Time

a

twp

Write Pulse Width

30

tWR

Write Recovery Time

a

-

tow

Data Valid to End of Write

20

-

tHZ

Output High Z Time (1.4)

-

tOH

Data Hold Time

twz

Write Enabled to Output in
High Z (1.4)

tow

Output Active From End of Write

(1.4)

ns

30

-

30

-

35

ns

0

-

a

-

ns

20

-

30

-

35

ns

-

0

-

a

-

ns

20

-

15

-

a

-

-

a

45
35
35

a
35

a

NOTES:
1. Transition is measured ±500mV from low or high voltage with load (Figures 1, 2 and 3).
2. O°C to + 70°C temperature range only.
3. -55°C to + 125°C temperature range only.
4. This parameter guaranteed but not tested.
5. For MASTER/SLAVE combination, two = tBAA + t wp .

5-34

55
40

50
50

ns
ns
ns
ns
ns
ns

---"-"-"----------------------------~

IDT71321 SAl LA AND 1DT71421SAlLA
CMOS DUAL-PORT RAMS 16K(2KxS-BIT) WITH INTERRUPTS

-------------------

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING (1,2,3,7)
twc
ADDRESS

~

---../

)(

K

~

t

(6)HZ

/V
tAw
~

~~

~
t

I - - - t AS

(7)

tWR

Wp

/V

..... i'..

-

I---twrtow
/<::(4)::~ " -

• (4)""/<><

DATA OUT

~tow

t OH

-

.......
/

/

DATA IN

"

TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING (1,2,3,5)

~----------------------twc----------------------~

ADDRESS
~--------------------tAw------------------~

,---~-------------------~------------- tEW

-------------..j

RNi

DATA IN

NOTES:
1.
2.
3.
4.
5.
6.
7.

WE must be high during all address transitions.
A write occurs during the overlap (tEW or wp) of a low
and a low RlW.
tWR is measured from the earlier of
or R/W going high to the end of write cycle.
During this period, the I/O pins are in the output state, and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the RNi low transition, the outputs remain in the high impedance state.
Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
If DE is low during a RNi controlled write cycle, the write pulse must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off data to
be placed on the bus for the required tow. If O"E is high during an RlW controlled write cycle, this requirement does not apply and the write pulse
can be as short as the specified t wP .

cr

cr

5-35

IDT71321 SA/LA AND IDT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

PARAMETER

71321 SA/LA3S(1)
71421SA/LA3S(1)
MAX.
MIN.

71321SA/LA4S
71421 SA/LA4S
MAX.
MIN.

71321 SA/LASS
71421 SA/LASS
MAX.
MIN.

71321 SA/LA70(2)
71421 SA/LA70(2)
MIN.
MAX.

UNIT

BUSY TIMING

-

-10

35

30

-

-

30

-

30

-

25

-

25

60

-

70

-

35

-

45

tWB

Write to BUSY (3, 6)

0

tWH

Write Hold After BUSy(7)

20

-

tBM

BUSY Access Time to Address

-

35

tBDA

BUSY Disable Time to Address

-

t BAC

BUSY Access Time to Chip Enable

0
20

35

-

ns

20
45

-

45

ns

40

-

40

ns

35

-

35

ns

-

30

-

30

ns

-

80

-

90

ns

55

-

70

ns

5

-

ns

-

Note 5

ns

t BOO

BUSY Disable Time to Chip Enable

tWDD

Write Pulse to Data Delay (4)

tDDD

Write Data Valid to
Read Data Delay (4)

tAPS

Arbitration Priority Set-up Time

5

-

5

-

5

tBDD

BUSY Disable to Valid Data (5)

-

Note 5

-

Note 5

-

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.
3. For SLAVE part (IDT71421) only.
4. Port-to-port delay through RAM cells from writing port to reading port.
5. tBDD is a calculated parameter and is the greater of 0, tWDD - twp (actual) or tDDD - tDW (actual),
6. To ensure that the write cycle is inhibited during contention.
7. To ensure that a write cycle is completed after contention.

5-36

-

20

Note 5

-10

ns

1DT11321 SA/LA AND IDT11421 SA/LA
CMOS DUAL-PORT RAMS 16K(2KxB-BIT) WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ WITH BUSY

'If

MATCH

J~

If

Jr-

~

DATAIN

J

~'tJI\

R

VALID

MATCH

\.-:-\

/

~tBoo-

t BOA -

-'I-

~~

i

twoo

~if-

DATAOUTL

.JI\

tO~~

TIMING WAVEFORM OF WRITE WITH BUSY

twp

RNi

~t~
BUSY

tt~

/

"
5-37

VALID

IDT71321 SA/LA AND IDT71421 SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-Bm WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
eEL VALID FIRST:
ADDR
LAND R

=x

>C

ADDRESSES MATCH

~'~l · r::'~=1CER VALID FIRST:
ADDR
LAND R

=x

>C

ADDRESSES MATCH

~'~l r::'==1TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION

(1)

LEFT ADDRESS VALID FIRST:
10+----

ADDRL

tRC twc
OR

----~

ADDRESSES MATCH

-,~

ADDRESSES DO NOT MATCH

9 _______

tB_D_A=====~~_______

RIGHT ADDRESS VALID FIRST:
10+----

tRC twc
OR

-----I~

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

__________tB_DA_-_-_-_-_~_~~-------

-'~9
NOTE:

5-38

IDT71321 SA/LA AND IDT71421SAlLA
CMOS DUAL-PORT RAMS 16K (2Kx S-BIT) WITH INTERRU PTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

71321 SAlLA3S(1)
71421 SA/LA35(1)
MIN.
MAX.

PARAMETER

71321SA/LA45
71421 SA/LA45
MIN.
MAX.

71321 SA/LA55
71421SAlLA55
MIN.
MAX.

71321SA/LA70(2)
71421SAlLA70(2)
MIN.
MAX.

UNIT

INTERRUPT TIMING
t AS

Address Set-up Time

0

-

0

-

0

-

ns

Write Recovery Time

0

-

0

-

0

tWA

0

-

0

-

ns

tiNS

Interrupt Set Time

35

-

40

ns

35

-

40

-

50

Interrupt Reset Time

-

45

tiNA

-

50

ns

45

NOTES:
1. O°C to + 70°C temperature range only.
2. -55°C to + 125°C temperature range only.

TIMING WAVEFORM OF INTERRUPT MODE (1,2)
LEFT SIDE SETS INTR :

twc
WRITE 7FF

ADDRl
t AS
RiW l

r~

INTA

RIGHT SIDE CLEARS INTR :
- - - - - tRc-----f=-.j
ADDRA

READ 7FF
K~~~K.~~~~~~~~~t~W-R-------------------

~,\~\:a...;;I\.~\\~\~\....\~\.~\;a....:\.~\o....JI.\\~\...\~\.~\.;a....:\.~\o....JI.Vk~___~--~1

________~_;V"

NOTES:
1. CEl = CE A= \til
2. INTl and INTA are reset to VO H during power up.

5-39

IDT71321 SA/LA AND 1DT71421SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF INTERRUPT MODE (1,2)
RIGHT SIDE SETS INT L :
two
ADDRR

-

WRITE7FE

-if-

t AS

~~

L

-leo(
tWR

II
tiNS

Jk-

LEFT SIDE CLEARS INTL :

ADDAL

K..&...K.&...K.&...K.&...K.&...K.&...K.&...K.~:_t-W_R~~~~R~EA_~O_7-FE~_-_-_-_-_-+if=

RliiL

OE L
INTL

\_\a......l'.......a'\_,~,~\_\a......l\.......a\\_\~\_\a......l\~\\_\~\~\_\Io.+J&~-=~---'/
~_"N'

_________________ __j

NOTES:

1. OEL = ~R= VIL
2. rnTR and Tf\JiL are reset (high) during power up.

16-BIT MASTERISLAVE DUAL-PORT MEMORY SYSTEMS
LEFT

...

RiW IDT71321
RiW
_ _ MASTER _ _
BUSY
BUSY

-

,-,,~

A./V\r

..

-

+5V

. +5V

VV'-

--

AiW

ANi
IDT71421
SLAVE(1) _ _
BUSY ~
~ BUSY
NOTE:
1. No arbitration in IDT71421 (SLAVE). BlJsY:.IN Inhibits write in IDT71421 (SLAVE).

5-40

RIGHT

IDT71321SAlLA AND IDT71421SAlLA
CMOS DUAL-PORT RAMS 16K (2Kx 8-BIT) WITH INTERRU PTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES
Contention occurs when both left and right ports are active and
both addresses match. When this situation occurs, the on-chip arbitration logic determines access. Two modes of arbitration are
provided: (1) if the addresses match and are valid before CE, onchip control logic arbitrates between CEland CE Rfor access; or (2)
if the C'Es are low before an address matCh, on-chip control logic
arbitrates between the left and right addresses for access (refer to
Table III). In either mode of arbitration, the delayed port's BUSY flag
is set and will reset when the port granted access completes its
operation.

FUNCTIONAL DESCRIPTION:
The I0T71321/421 provides two ports with separate control, address and I/O pins that permit independent access for reads or
writes to any location in memory. These devices have an automatic
power down feature controlled by CEo The CE controls on-chip
power down circuitry that permits the respective port to go into a
standby mode when not selected (CE high). When a port is enabled, access to the entire memo!y'prray is permitted. Each port
has its own Output Enable control (OE) .In the read mode, the port's
~ turns on the output drivers when set LOW. Non-contention
REAO/WRITE conditions are illustrated in Table I.
The interrupt flag (INT) permits communication between ports
or systems. If the user chooses to use the interrupt function, a memory location (mail box or message center) is assigned to each port.
The left port Interrupt flag (INTl) is set when the right port writes to
memory location 7FE (HEX). The left port clears the interrupt by
reading address location 7FE. Likewise, the right port interrupt flag
(INTR) is set when the left port writes to memory location 7FF (HEX)
and to clear the interrupt flag (INT~, the right port must read the
memory location 7FF. The message (8 bits) at 7FE or 7FF is userdefined. If the interrupt function is not used, address locations 7FE
and 7FF are not used as mail boxes but as part of the random access memory. Refer to Table II for the interrupt operation.

DATA BUS WIDTH EXPANSION,
MASTERISLAVE DESCRIPTION:
Expanding the data bus width to sixteen-6r-more-bits in a dualport RAM system implies that several chips will be active at the
same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one
will activate its L BUSY while another activates its R BUSY signal.
Both sides are now busy and the CPUs will wait indefinitely for their
port to become free.
To avoid this "Busy Lock-Out" problem, lOT has developed a
MASTER/SLAVE approach where only one hardware arbitrator, in
the MASTER, is used. The SLAVE has BOSY inputs which allow an
interface to the MASTER with no extemal components and with a
speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a
contention situation. Conversely, the write pulse must extend a
hold time past BUSY to ensure that a write cycle takes place after
the contention is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the same
time.
The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs,
the write to the SLAVE will be inhibited due to'BOSY from the
MASTER.

ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip enable match down to 5ns minimum and determine which port has
access. In all cases, an active BUSY flag will be set for the delayed
port.
The BUSY flags are provided for the situation when both ports
simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic will determine which port has
access and sets the delayed port's BUSY flag. BUSY is set at
speeds that permit the processor to hold the operation and its respective address and data. It is important to note that the operation
is invalid for'the port that has BUSY set LOW. The delayed port will
have access when BUSY goes inactive.

CAPACITANCE

TRUTH TABLES

SYMBOL

TABLE 1- NON-CONTENTION
READ/WRITE CONTROL(4)
LEFT OR RIGHT PORT (1)

CIN

CE

OE

X

H

X

Z

Port Disabled and in Power Down
Mode, IS82 or ISB4

X

H

X

Z

CE R = CE l = H, Power Down
Mode. IS81 or IS83

L

L

X

DATA IN

H

L

L

DATA OUT

H

L

H

Z

Input Capacitance

CONDITIONS
VIN = OV

, MAX.

UNITS

pF
COUT
VOUT= OV
Output Capacitance
11
pF
NOTE:
1. This parameter is determined by device characterization but is not production tested.

FUNCTION

R/W

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

00-7

Data on Port Written Into Memory(2)
Data in Memory Output on Port (3)
High Impedance Outputs

NOTES:
1. AOl-Al0l p AoR-Al0R
2. If BUSY = l, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and t8DD timing.
4. H = HIGH, L = LOW, X = DON'T CARE, Z = HIGH IMPEDANCE

5-41

11

1DT71321 SA/LA AND IDT71421 SA/LA
CMOS DUAL-PORT RAMS 16K{2KxB-BIT) WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE II-INTERRUPT FLAG (1,4)
LEFT PORT

RIGHT PORT

FUNCTION

CE R

OE R

X
X

X

X

X

L(2)

L

L

7FF

H(3)

Reset Right I NTR Flag

L (3)

L

L

X

7FE

X

Set Left INTL Flag

H(2)

X

X

X

X

X

Reset Left INTL Flag

CEl

OEl

AOl - A 10l

INh

L

L

X
X

X
X
X

7FF

X
X
X

X
X

X
X

L

L

7FE

R/Wl

R/WR

INTR

AOl -A 1OR

Set Right INT R Flag

NOTES:
1. Assumes BUSYl = BUSYR = H.
2. If BUSY l = L, then NC.
3. If BUSYR = L, then NC.
4. H = HIGH, L= .LOW, X = DON'T CARE, NC= NO CHANGE

TABLE III-ARBITRATION (2)
LEFT PORT

FLAGS (1)

RIGHT PORT

FUNCTION
eEL

BUSYl

BUSYR

AOl - A 10l

CER

H

X

H

H

No Contention

Any

H

X
X

H

L

H

H

No Contention

H

X

L

Any

H

H

No Contention

H

H

No Contention

AOl - AtoR

L

L
"AOL -A1OL
" AOR-A1OR
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L

LV5R

L

LV5R

H

L

L-PortWins

L

RV5L

L

RV5L

L

H

R-PortWins

L

Same

L

Same

H

L

Arbitration Resolved

L

Same

L

Same

L

H

Arbitration Resolved

CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL5R

= AOR-A1OR

LL5R

= AOL -A1OL

H

L

L-PortWins

RL5L

= AOR-A1OR

RL5L

= AOL -Al0L

L

H

R-PortWins

LW5R

= AOR-Al0R

LW5R

= AOl -Al0L

H

L

Arbitration Resolved

LW5R

= AOR-Al0R

LW5R

= AOL -Al0L

L

H

Arbitration Resolved

NOTES:
1. INT Flags Don't Care.
2. X = DON'T CARE, L = LOW, H = HIGH
LV5R = Left Address Valid ~ 5ns before right address.
RV5L = Right Address Valid ~ 5ns before left address.
Same = Left and Right Addresses match within 5ns of each other.
LL5R = Left cr = LOW ~ 5ns before Right cr.
RL5L = Right'CE = LOW ~ 5ns before Left cr.
LW5R = Left and Right ~ = LOW within 5ns of each other.

5-42

JDT71321 SA/LA AND IDT71421 SA/LA
CMOS DUAL-PORT RAMS 16K(2Kx8-BIT) WITH INTERRUPTS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

lOT

DeV~ype

A
Package

A

y:-

Processl
Temperature

'---------4 JL

PLCC
LCC
Commercial Only }

70

Military Only

LA
SA

Low Power
Standard
Power

71321

16K (2K x 8-Bit) MASTER Dual-Port RAM
wI Interrupt
16K (2K x 8-Bit) SLAVE Dual-Port RAM
wI Interrupt

71421

5-43

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B

35

1...--------------1 55
45
1.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1

Commercial (O°C to

Speed in Nanoseconds

FEATURES:

DESCRIPTION:

• High-speed access
- Military: 45/55/70ns (max.)
- Commercial: 45/55/70ns (max.)

The IDT71322 is an extremely high-speed 2K x 8 dual-port static
RAM with full on-Chip hardware support of semaphore signalling
between the two ports.
The IDT71322 provides two independent ports with separate
control. address and I/O pins that permit independent. asynchronous access for reads and writes to any location in memory. To assist in arbitrating between ports. a fully independent semaphore
logic block is provided. This block· contains unassigned flags
which can be accessed by either side; however. only one side can
control the flag at anytime. An automatic power down feature. controlled by CE and 'SErVl. permits the on-Chip circuitry of each port
to enter a very low standby power mode.
Fabricated using lOT's CEMOS ™ high-performance technology. this device typically operates on only 500mW of power at
maximum access·times as fast as 45ns. Low-power (L) versions offer battery backup data retention capability. with each port typically consuming 200llW from a 2V battery.
The IDT71322 is packaged in a 48-piri sidebraze or plastic DIP
or 52-pin LCC and PLCC. Military grade product is manufactured
in compliance with the latest revision of MIL-STD-883. Class B.

• Low-power operation
- IDT71322S
Active: 500mW (typ.)
Standby: 5mW (typ.)
- IDT71322L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Full on-chip hardware support of semaphore signalling
between ports
• Battery backup operation-2V data retention
• TIL-compatible. single 5V(±10%) po~er supply
• Available in a variety of plastic and hermetic packages for both
through hole and surface mount applications
• Military product compliant to MIL-STD-883. Class B

FUNCTIONAL BLOCK DIAGRAM

- .t::

.s--'

T

~

~

v---

1I00L-1I07L

T

---

...

~l

I/O
COLUMN

~

r--.
.

--

~

I/O
COLUMN

MEMORY
ARRAY

~

SEMAPHORE
LOGIC

~

~

....

......,.

LEFT SIDE
ADDRESS
DECODE
LOGIC

'""

-

RIGHT SIDE
ADDRESS
DECODE
LOGIC

.

~

~

"

AOR - AlOR

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology, Inc.

DECEMBER 1987
DSC-1032/-

5-44

--_..- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDT11322S AND IDT71322L CMOS
DUAL-PORT RAM 16K (2K x a-BIT) WITH SEMAPHORES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX~

B,.d~ol!liw g~'il§O ~

~....nlU
.........a:
.........(J)rMZ..,.(4»~ f--

(4)

t+-DATA IN

tow

t OH -

./

......

"-

./

TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING (1,2,3,5,9)

~----------------------twc------------------------~

ADDRESS
~--------------------tAW--------------------~

CEor
SEM(8)

,---~-----------------

------14------------- tEW --------------~

Rm
DATA IN

NOTES:
1.

RiW must be high during all address transitions.

2. A write occurs during the overlap (tEW or fwp) of a low CE or SEM and a low RlW.
3. tWA is measured from the earlier of cr or R/W (or SEM or R/W) going high to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE or SEM low transition occurs simultaneously with or after the RNi low transition, the outputs remain in the high impedance state.

6. Transition is measured ±500mV from steady state with a 5pF load (including scope and jig).
7. If DE is low during a Rm controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off
and data to be placed on the bus for the required tow. If OE is high during an RiW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t wP '
8. To access RAM, CE = "'IL' SEM = "'IH' To access semaphore, CE
9. DE = V1L

= VIH, SEM = VIL • Either condition must be valid for the entire tEW time.

5-50

IDT71322S AND IDT71322L CMOS
DUAL-PORT RAM 16K (2K x B-BIT) WITH SEMAPHORES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE (1)

VALID ADDRESS

DATA 0

RNi

....- - - WRITE CYCLE - - -....f----·TEST CYCLE-----t
(READ CYCLE)

NOTE:

1. CE = V1H for the duration of the above timing (both write and read cycle).

TIMING WAVEFORM OF SEMAPHORE CONTENTION

A OA- A2A
SIDE (2) "A"

RNiA
SEM A

(1,3,4)

MATCH

X

ft,ps

A OB - A2B
SIDE (2) "B"

RmB
SEM B

NOTES:
DOR = DOL = V 1L , CE R = CE L = \IH' Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
Either side "A" = left and side "B" = right, or side "A" = right and side "B" = left.
3. This parameter is measured from the point where RNiA or SEM A goes high until RNi B or SEM B goes high.
4. If tsps is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

1.
2.

5-51

1OT71322S AND IDT71322L CMOS
DUAL-PORT RAM 16K (2K x S-BIT) WITH SEMAPHORES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

separate memory space from the dual-port RAM. This address
space is accessed by placing a low input on the SEM pin (which
acts as a chip select for the semal2b.ore flags) and using the other
control pins (Address, OE, and R/w) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins
Ao - A2. When accessing the semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If a low
level is written into an unused semaphore location, that flag will be
set to a zero on that side and a one on the other (see Table 1I).That
semaphore can now only be modified by the side showing the
zero. When a one is written into the same location from the same
side, the flag will be set to a one for both sides (unless a semaphore
request from the other side is pending) and then can be written to
by both sides. The fact that the side which is able to write a zero into
a semaphore subsequently locks out writes from the other side is
what makes semaphore flags useful in interprocessorcommunications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side
will be stored In the semaphore request latch for that side until the
semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data
bits so that a flag that is a one reads as a one in all data bits and a
flag containing a zero reads as all zeros. The read value is latched
into one side's output register when that side's semaphore select
(SEM) and output enable (OE) signals go active. This serves to
disallow the semaphore from changing state in the middle of a read
cycle due to a write cycle from the other side. Because of this latCh,
a repeated read of a semaphore in a test loop must cause either
signal (SEM or OE) to go inactive or the output will never change.
A sequence of WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
,processor requests access to shared resources by attempting to
write a zero into a semaphore location. If the semaphore is already
in use, the semaphore request latch will contain a zero, yet the
semaphore flag will appear as a one, a fact which the processor will
verify by the subsequent read (see Table II). As an example, assume a processor writes a zero to the left port at a free semaphore
location. On a subsequent read, the processor will verify that it has
written successfully to that location and will assume control over
the resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will fail,
as will be verified by the fact that a one will be read from that semaphore on the right side during a subsequent read. Had a sequence
of READ/WRITE been used instead, system contention problems
could have occurred during the gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 3. Two semaphore request latches feed into a semaphore flag. Whichever latch
is first to present a zero to the semaphore flag will force its side of
the semaphore flag low and the other side high. This condition will
continue until a one is written to the same semaphore request latch.
, Should the other side's semaphore request latch have been written
to a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's request
latch. The second side's flag will now stay low until its semaphore
request latch is written to a one. From this it is easy to understand
that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can
hang up until a one is written into that semaphore request latch.

FUNCTIONAL DESCRIPTION
The IDT71322Is an extremely fast dual-port 2K x 8 CMOS static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or
right side of the dual-port RAM to claim a privilege over the other
processor for functions defined by the system designer's software.
As an example, the semaphore can be used by one processor to
inhibit the other from accessing a portion of the dual-port RAM or
any other shared resource.
The dual-port RAM features a fast access time, and both ports
are completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right
port. Both ports are identical in function to standard CMOS static
RAM and can be read from, or written to, at the same time with the
only possible conflict ariSing from the simultaneous writing of, or a
simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may
be used by the system program to avoid any conflicts in the non. semaphore portion of the dual-port RAM. These devices have an
autolllatic power-down feature controlled by CE, the dual:QQ!!
RAM enable, and SEM, the semaphore enable. The CEand SEM
pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the
condition which Is shown in Table I where CE and SEM are both
high.
Systems which can best use the IDT71322 contain multiple
processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These
systems can benefit from a performance increase offered by the
IDT71322's hardware semaphores, which provide a lockout
mechanism without requiring complex programming.
Software handshaking between processors offers the maximum
in system flexibility by permitting shared resources to be allocated
in varying configurations. The IDT71322 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common methods of hardware arbitration Is that wait states are never
incurred in either processor. This can prove to be a major advantage in very high-speed systems.

HOW THE SEMAPHORE FLAGS WORK
The semaphore logic Is a set of eight latches which are independent of the dual-port RAM. These latches can be used to pass a
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphores provide a hardware assist for a
use assignment method called "Token Passing Allocation." In this
method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to
use this resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by reading it.
If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latCh, it determines
that the right side processor had set the latch first, has the token
and is using the shared resource. The left processor can then either
repeatedly request that semaphore's status or remove its request
for that semaphore to perform another task and occaSionally
attempt again to gain control of the token via the set and test
sequence. Once the right side has relinquished the token, the left
side should succeed in gaining control.
.~e semaphore flags are active low. A token is requested by
writing a zero Into a semaphore latch and is released when the
same side writes a one to that latch.
The eight semaphore flags reside within the IDT71322 in a

5-52

IDT71322S AND IDT71322L CMOS
DUAL-PORT RAM 16K (2K x S-BIT) WITH SEMAPHORES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 1- NON-CONTENTION READ/WRITE CONTROL
LEFT OR RIGHT PORT (1)
R/W

CE

SEM

OE

X

H

H

X

H

H

L

L

DATA oUT

X

X

X

H

Z

H

L

X

S

FUNCTION

00-7

Z

Port Disabled and in Power Down
Mode
Data in Semaphore Flag
Output on Port
Output Disabled

DATA IN

Port Data Bit Do Written Into
Semaphore Flag

H

L

H

L

DATA oUT

Data In Memory Output on Port

L

L

H

X

DATA IN

Data On Port Written Into Memory

X

L

L

X

-

Not Allowed

NOTE:
1.

AOL - A 10L t- AOR - A 10R
H = HIGH. L = LOW. X = DON'T CARE. Z
= Low-to-High transition

S

= HIGH IMPEDANCE

TABLE II-EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE (1)
FUNCTION

Do - 07 LEFT

Do - 07 RIGHT

STATUS

No Action

1

1

Semaphore free

Left Port Writes ·0" to Semaphore

0

1

Left port has semaphore token

0

1

No change. Right side has no write
access to semaphore

Left Port Writes "1" to Semaphore

1

0

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

1

0

No change. Left port has no write
access to semaphore

Right Port Writes "0"

to Semaphore

to Semaphore

0

1

Left port obtains semaphore token

1

1

Semaphore free

Right Port Writes "0" to Semaphore

1

0

Right port has semaphore token

Right Port Writes "1" to Semaphore

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

1

Semaphore free

Right Port Writes "1"

Left Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

1

NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71322.

5-53

IDT71322S AND IDT71322L CMOS
DUAL-PORT RAM 16K (2K x S-BIT) WITH SEMAPHORES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ing a zero into Semaphore 1. If it succeeded in gaining control, it
would lock out the left side.
Once the left side was finished with its task, it would write a one
to Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was sti II occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was
able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would
allow the two processors to swap 1K blocks of dual-port RAM with
each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
dual-port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides
rather than being given a common meaning as was shown in the
example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait
states. With the use of semaphores, once the two devices had determined which memory area was "off limits" to the CPU, both the
CPU and the I/O devices could access their assigned portions of
memory continuously without any wait states.
Semaphores are also useful in applications where no memory
"WAIT" state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
aSSigned RAM segments at full speed.
Another application is in the area of complex data structures. In
this case, block arbitration is very important. For this application
one processor may be responsible for building and updating a
data structure. The other processor then reads and interprets that
data structure. If the interpreting processor reads an incomplete
data structure, a major error condition may exist. Therefore, some
sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and
then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data
structure, thereby guaranteeing a consistent data structure.

The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same
time. The semaphore logic is specially designed to resolve this
problem. If simultaneous requests are made, the logic guarantees
that only one side receives the token. If one side is earlier than the
other in making the request, the first side to make the request will
receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other.
One caution that should be noted when using semaphores is
that semaphores alone do not guarantee that access to a resource
is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily
happen. Code integrity is of the utmost importance when semaphores are used instead of slower, more restrictive hardware intensive schemes.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any
semaphore request flag which contains a zero must be reset to a
one, all semaphores on both sides should have a one written into
them at initialization from both sides to assure that they will be free
when needed.

USING SEMAPHORES - Some Examples
Perhaps the simplest application of semaphores is their application as resource markers for the IDT71322's dual-port RAM. Say
the 2K x 8 RAM was to be divided into two 1K x 8 blocks which were
to be dedicated at anyone time to servicing either the left or right
port. Semaphore 0 could be used to indicate the side which would
control the lower section of memory, and Semaphore 1 could be
defined as the indicator for the upper section of memory.
To take a resource, in this example the lower 1K of dual-port
RAM, the processor on the left port could write and then read a zero
into Semaphore O. If this task were successfully completed (a zero
was read back rather than a one), the left processor would assume
control of the lower 1K. Meanwhile, the right processor would attempt to perform the same function. Since this processor was attempting to gain control of the resource after the left processor, it
would read back a one in response to the zero it had attempted to
write into Semaphore O. At this point, the software could choose to
try and gain control of the second 1K section by writing, then read-

RPORT

LPORT
SEMAPHORE
REQUEST FLIP FLOP

Do----I D

SEMAPHORE
REQUEST FLIP FLOP

Q

Q

D f - - - Do
WRITE

WRITE - -. .

SEMAP~~~6 ~~--------~----~

SEMAPHORE
READ

SEMAPHORE LATCH

FIGURE 3. 1DT71322 Semaphore Logic

5-54

--------

-----------------------------------------------------------------------------------------------------

1OT71322S AND IDT71322L CMOS
DUAL-PORT RAM 16K (2K x S-BIT) WITH SEMAPHORES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XXXX
A
Device Type Power

999

A

A

Speed

Package

Process/
Temperature

RT~-1:'Mk
P
C

J
L

5-55

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze DIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier

45
50
70

Speed in Nanoseconds

L

Low Power
Standard Power

71322

16K (2K x 8-Bit) Dual-Port RAM w/Semaphore

L..---------------------i S

'----------------------------1

Commercial (O°C to

FEATURES:

DESCRIPTION:

• High-speed access
- Military: 70/90ns (max.)
- Commercial: 55/70/90ns (max.)

The 1017133/7143 are high-speed 2K x 16 dual-port static
RAMs. The 1017133 is designed to be used as a stand-alone 16-bit
dual-port RAM or as a "MASTER" dual-port RAM together with the
1017143 "SLAVE" dual-port in 32-bit-or-more word width systems.
Using the lOT MASTER/SLAVE dual-port RAM approach in 16-bitor-wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic.
Both devices provide two independent ports with separate control, address and I/O pins that permit independent, asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using lOT's CEMOS ™ high-performance technology, these devices typically operate on only 375mW of power at
maximum access times as fast as 55ns. Low-power (L) versions
offer battery backup data retention capability, with each port
typically consuming 1mW from a 2V battery.
The 1017133/7143 devices have identical pinouts. Each is
packaged in a 68-pin PGA, 68-pin LCC, 68-pin PLCC, and 70 mil
center DIPs.
Military grade product is manufactured in compliance with the
latest revision of MIL-STO-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• Low-power operation
- 1017133/43S
Active: 375mW (typ.)
Standby: 5mW (typ.)
- 1017133/43L
Active: 375mW (typ.)
Standby: 1mW (typ.)
• Versatile control for write: separate write control for lower and
upper byte of each port
• MASTER 1017133 easily expands data bus width to 32 bits or
more using SLAVE 1017143
• On-chip port arbitration logic (1017133 only)
•
•
•
•
•

BUSYoutput flag on 1017133; BUSY input on 1017143
Fully asynchronous operation from either port
Battery backup operation-2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, OIP (600 mil, 70 mil centers), LCC and
PLCC
• Military product compliant to MIL-STO-883, Class B

FUNCTIONAL BLOCK DIAGRAM

R~~B--------~;====a~r---------h

OE

OEl-==~:~::~;f~~~~~~:f~/l

Al0l Ael ------l~---.

Al0R
AeR

I/Oel-1I0l5l --,L-----+-4-I
1I0ol-I/07L

troS"Yl (l)

RtWRlB
R

I/OeR-I/015R

--7"-----4'--t..::.::.J-L..::..;:.....-"n n/L.::;.:......J-t..:::.J--*---->O"--

I/OoR-I/07R

----f-----.r=-:-:-l

r:-:-:-::-:-l----f----

A7R

14----+---

AOR

ffirnV (l)
A7L

AOl - - - t - - - - I - t
A10l -------~
AOl-----+I
NOTES:
1. IDl7133 (MASTER): BUSY is open drain
output and requires pull-up resistor.
IDT7143 (SLAVE): BUSY is input.
2. LB = LOWER ~YTE
UB = UPPER BYTE

OE

C'El-----+I
l

- - - -....

~lUB----....

~ULB----~

R

1 4 - - - - - Al0R
ARBITRATION
LOGIC
(IDT7133
ONLy)

1 4 - - - - - AOR
14-----

C'E R

...---- OE

R

~RUB
R~RLB

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987lntegraled DevIce Technology. Inc.

DECEMBER 1987
5-56

DSC-l033/-

1DT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-81T)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
51
11
53
10

55

47

49

A7l

46

A3l

A4l

A2l

42

44

All

IDSVl

45

43

36

40

CE R
41

A2R

39

37

eEL mlSVR A1R

AOl

36

AOR

A4R
35

A3R

54

34

A5R

A6R

32
A6R

33
A7R

30
A lOR

31
A9R

28

29

09

A 10l

08

R/WLLB

07

58
59
Vee (l) R/WLUB

06

61
I/O ll

05

62
63
1/0 3l 1/0 2l

24
25
1/014R 1/0 15R

04

65
1/0 5l

64
1/0 4l

23
22
1/0 12R 1/0 13R

03

67
1/0 7l

66
1I0 6l

20

02

68
1/0 8l

1
1/0 9l

01

•

57

DIP
TOP VIEW

A5l

52

A6l

46

50

A6l

Pin 1 /
Designator

A9l
56

A

Oi: l

R/W RLE O1:R

60

26
27
GND(2) RtWRUE

G68-1

1/0 0l

21
110 lOR 1/0 11R

3
110 m

2
4
1/0 1Ol 1/0 12l

5
1/013l

13
II03R

15
1/0 5R

16
1/08R

10
I/OOR

12
1/0 2R

14
1/0 4R

16
1/0 6R

17

F

G

H

J

6
8
1/014l Vee (1)

C

B

11
7
9
1/015l GNO(2) 1/0 1R

D

E

II07R
K

PGATOPVIEW

NOTES:
1. Both Vee pins must be connected to the supply to assure
reliable operation.
2. Both GND pins must be connected to the supply to assure
reliable operation.
3. UB = Upper Byte, LB = Lower Byte.

...J
eX)

...J...J...J...J
r-- co 1.0""

...J...J...J
C"')

C\I

......

;: - 3 ~

...J~~I~
...J
0 0
g0....J....J...J

ggggggggg~~~ ~~~~
9 8 765432 1 68 67 66 65 64 63 62 61
1I09l
1/01Ol
1/011l
1/012l
1/013l
1/014l
1/015l
VCC (l)
GND(2)
I/O OR
1/01R
1/02R
1/03R
1/04R
1/0 5R
1/06R
1/07R

10
11
12
13
14
15
16
17

60 A6l
59 A5l
58 A4l
57 A3l
56 A2l
55 All
54 AOl
53 BUSV
l
52 CE l
51 CE R
50 BUSY
49 AOR R
48 A1R
47 A2R
46 A3R
45 A4R
44 A5R

J68-1

18
19

&

L68-2

20

21
22
23
24
25
26

2728293031323334 35363736 3940 414243
a: cea: a: a: a: a: 1l:N'
co

CDO

...... C\I C")...,.

Ll)-

rom

--::::::::::::::::::::::::::::::&~~

LCC/PLCC
TOP VIEW

5-57

a: a: a: a: a: a:

:Jci~

QQOOOOOOO~~

a

Q)

co,..... co

c(~ ~~~

19
1/0 9R

L

IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

Operating
Temperature

Oto +70

TS1AS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

2.0

2.0

W

lOUT

DC Output Current

50

50

mA

TA

-55 to +125

MIN.

TYP.

MAX.

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H

Input High Voltage

2.2

-

6.0

V

V1L

Input Low Voltage

-

0.8

V

SYMBOL

°C

PARAMETER

-0.5(1)

UNIT

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

GRADE
Military
Commercial

5-58

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V ± 10%

O°C to +70°C

OV

5.0V ± 10%

Vee

--------------------------------------------------IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(Either port, Vee= 5.0V ±10%)

SYMBOL

IDTI133S
IDTI143S
MAX.
MIN.

TEST CONDITIONS

PARAMETER

IDT7133L
IOT7143L
MIN.
MAX.

UNIT

Input Leakage Current

Vee = 5.5V, "iN = OV to Vee

-

10

MA

IlLOI

Output Leakage Current

-

10

-

5

CE = "iH ' VOUT = OVtoVee

5

MA

VOL

Output Low Voltage (I/Do-I/015)

10l = 4mA

-

0.4

-

0.4

V

VOL

Open Drain Output Low
Voltage (BUSY)

10l = 16mA

-

0.5

-

0.5

V

VOH

Output High Voltage

10H= -4mA

2.4

-

2.4

-

V

Ilu l

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (4)
SYMBOL

Icc

IS81

IS82

PARAMETER

TEST CONDITION

Dynamic Operating
Current (Both Ports
Active)

CE = "il
Outputs Open
f = fMAX(3)

Standby Current
(Both Ports - TTL
Level Inputs)

CEl and CE R ~ "iH
f = fMAX (3)

CEl or CE R ~ "iH
f = fMAX(3)
Active Port Outputs
Open
land
Both Ports
Full Standby Current ITR ~ Vec -0.2V
(Both Ports - CMOS "iN ~ Vce -0.2V or
Level Inputs)
V1N ~ 0.2V
f = 0(3)

Standby Current
(One Port- TTL
Level Inputs)

cr

IS83

IS84

VERSION
MIL.
COM'L.
MIL.
COM'L.
MIL.
COM'L.

S
L
S
L
S
L
S
L
S
L
S
L

(Vee = 5.0V ±10%)

I OTI133x55 (1)
IDTI143x55 (1)
TYP,(2)
MAX.

-

-

-

75
75

240
220

-

-

25
25

70
60

-

-

50
50

150
130

-

IDT7133x70
IDT7143x70
TYP,(2)
MAX.

1DT7133x90
IDT7143x90
TYP.(2)
MAX.

75
75
75
75
25
25
25
25
50
50
50
50

260
240
240
220
75
65
70
60
170
150
150
130

75
75
75
75
25
25
25
25
50
50
50
50

260
240
235
215
75
65
65
55
170
150
145
125

MIL.

S
L

-

-

-

1
0.2

30
10

1
0.2

30
10

COM'L.

S
L

1
0.2

15
4

1
0.2

15
4

1
0.2

15
4

S

-

-

45

160

45

155

L

40

140

40

135

S

45

140

45

140

45

135

L

40

120

40

120

40

115

One Port CEl or
MIL.
CE R ~ Vee -0.2V
Full Standby Current "iN ~ Vec -0.2V or
(One Port-All CMOS V1N ~ 0.2V
Level Inputs)
f = f MAX (3)
Active Port Outputs COM'L.
Open

UNIT

mA

mA

mA

mA

mA

NOTES:
1. O°C to + 70°C temperature range only.
2. Vce = 5V, TA = + 25°C
3. At f = f MAX address and data inputs are cycling at the maximum frequency of read cycles of 1It Re. f = 0 means no input lines change.
4. "x" in part numbers indicates power rating (S or L).

5-59

IDT7133S/L AND IDT7143S/L
CMOS DUAL· PORT RAM 32K (2K x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = O.2V, VHC
SYMBOL
VDR

= VCC -

IDT7133S/LJI DT7143S/L
MAX,
MIN.

TEST CONDITION

PARAMETER
Vee for Data Retention

[ MIL.
ICCDR

Data Retention Current

Vcc = 2.0V

t

Chip Deselect to Data Retention Time

"'N<:: VHcor S VLC

CE~

CDR

(3)

(1)

O.2V

t R(3)

Operation Recovery Time

lu(3)

Input Leakage Current

I COM'L.

VHc

UNIT

2.0

-

V

-

4000

pA

1500

pA

0

-

ns

t RC (2)

-

ns

-

2

pA

NOTES:
1. Vcc = 2V, TA = +2SoC.
2. t RC = Read Cycle Time.
3. This parameter Is guaranteed but not tested.

LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
Vee

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V
Sns
1.SV
1.SV
See Figures 1, 2, & 3

SV
SV

DATAour

~

7750

SV 12SOCl

12SCXl
DATA our
30pF*

Figure 1. Output Load

~

7750

SpF*

Figure 2. Output Load
(for tU.t HZ ' twz.tow)

* Including scope and jig.

5-60

---!130

27CXl

BUSY

PF'

Figure 3. BUSY Output
Load
(IDT7133 only)

1DT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL

IDT7133S/L55 (2)
I DT7143S/L55 (2)
MIN.
MAX.

PARAMETER

IDT7133S/L70
I DT7143S/L70
MAX.
MIN.

I DT7133S/L90
1DT7143S/L90
MAX.
MIN.

UNIT

READ CYCLE
t RC

Read Cycle Time

55

-

70

-

90

-

ns

tAA
t AcE

Address Access Time

55

ns

90

ns

Output Enable Access Time

35

-

90

55

-

70

t AOE

-

40

ns

tOH

Output Hold From Address Change

0

-

0

10

Output Low Z Time (1.3)

5

-

5

5

-

ns

tLZ

-

tHZ

Output High Z Time (1. 3)

-

30

-

35

-

40

ns

tpu

Chip Enable to Power Up Time (3)

0

-

0

-

0

-

ns

tpD

Chip Disable to Power Down Time (3)

-

50

-

50

-

50

ns

Chip Enable Access Time

70
40

NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (see Figures 1. 2 & 3).
2. O°C to + 70°C temperature range only.
3. This parameter is guaranteed but not tested.

TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE

(1,2,4)

~t~~ X;,....----_~t~~
¥'--______

ADDRESS

PREVIOUSDATA~

DATA OUT

X

~

D_AT_A_VA_L_ID_ _ _ _ _

TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE

(1,3)

t ACE

II

-/

~

J

~

f4--

t AOE

- tHZ -

-

f

1\

t Hz ' "

~tLZ-

..,

...

DATA OUT

I
\

I
\

-

VALID DATA

tLZ
CURRENT

Icc

_ t pD -

1

-tpu-'

__________________~50%

Iss
NOTES:
1. RNi is high for Read Cycles.
2. Device is continuously enabled, CE = \ok.
3. Addresses valid prior to or coincident with CE transition low.
4. OE = V1L

5-61

~

ns

IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K X 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL

IDT7133S/L55 (2)
IDT7143S/L55 (2)
MIN.
MAX.

PARAMETER

I DT7133S/L70
I DT7143S/L70
MIN.
MAX.

IDT7133S/L90
IDT7143S/L90
MIN.
MAX.

UNIT

WRITE CYCLE
twc

Write Cycle Time(4)

55

-

70

-

90

-

ns

tEW

Chip Enable to End of Write

40

-

50

-

85

ns

tAW

Address Valid to End of Write

40

-

50

-

85

-

t AS

Address Setup Time

0

0

-

0

Write Pulse Width

40

50

-

55

-

ns

twp
tWR

Write Recovery Time

0

0

-

0

-

ns

tow

Data Valid to End of Write

20

-

25

-

30

-

ns

tHZ

Output High Z Time(1. 3)

-

20

-

25

-

25

ns

ns

ns

tOH

Data Hold Time

5

-

5

-

5

-

ns

twz

Write Enable to Output in High Z(1. 3)

-

20

-

25

-

25

ns

tow

Output Active From End of Write(1.

0

-

0

-

0

-

ns

3)

NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (see Figures 1, 2 & 3).
2. O°C to + 70°C temperature range only.
3. This parameter is guaranteed but not tested.
4. For MASTER/SLAVE combination, twc = tSM + tWR + t wp .

5-62

IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (R/W CONTROLLED TIMING)

(1,2,3,7)

twc
ADDRESS

~

---./

)(

K

t

(6)HZ

/V
tAW
~

~/

~
~tAS

t

(7)

tWR

Wp

'""'~

RNi(a)

/V

-

~tWi6)_
tow
DATA OUT

~y/> .

>< . . . .•. . . . . .•. ( 4 ) . <

••

/>~

C.·.·.(4) •••• ·•. )

_tow

t OH

./

DATA IN

'"

WRITE CYCLE NO.2 (CE CONTROLLED TIMING)

-

-

"-

./

(1,2,3,5)

~-----------------------twc----------------------~~

ADDRESS
~---------------------tAw------------------~

--~~--------------tEW------------~

RNi(8)

DATA IN

NOTES:
1.
2.
3.
4.
5.
6.
7.

RNi or CE must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low CE and a low RNi.
tWR is measured from the earlier of
or R/W going high to the end of write cycle.
During this period, the 110 pins are in the output state, and input signals must not be applied.
If the CE low transition occurs simultaneously with or after the RNi low transition, the outputs remain in the high impedance state.
Transition is measured ±5OOmV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
If DE is low during a RNi controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the I/O drivers to turn off
and data to be placed on the bus for the required tow. If lJE is high during an RlW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t wp .
8. RNi for either upper or lower byte.

cr

5-63

IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL

PARAMETER

IDT7133S/L55 (2)
IDT7143S/L55 (2)
MIN.
MAX.

IDT7133S/L70
IDT7143S/L70
MIN.
MAX.

I DT7133S/L90
1DT7143S/L90
MIN.
MAX.

UNIT

BUSY TIMING
tWB

Write to BUSY

0

-

0

tWH

Write Hold After BUSY (1, 6)

30

-

30

tBM

BUSY Access Time to Address

-

50

tSOA
t BAC

BUSY Disable Time to Address

-

40

-

BUSY Access Time to Chip Enable

-

35

-

35

t BOC

BUSY Disable Time to Chip Enable

30

-

·30

twoo

Write Pulse to Data Delay

80

Write Data Valid to Read Data Delay (3)

55

-

90

tO~~

-

70

tsoo

BUSY Disable to Valid Data (4)

-

Note 4

-

tAPS

Arbitration Priority Set Up Time

5

-

5

(1, 5)

(3)

55
45

0

-

ns

30

-

ns

-

55

ns

45

ns

-

45

ns

45

ns

100

ns

90

ns

Note 4

-

Note 4

ns

-

10

-

ns

NOTES:
1, For SLAVE part (IDT7143) only,
2, DoC to + 70°C temperature range only,
3, Port to port delay through RAM cells from writing port to reading port.
4. tsoo is calculated parameter and is greater of O. twoo - twp (actual) or tooo - tow (actual),
5, To ensure that the write cycle is inhibited during contention.
6, To ensure that a write cycle is completed after contention,

TIMING WAVEFORM OF READ WITH BUSY

'if

MATCH

JI\

If

-\

j

~fJ\

DATAIN R

VALID

MATCH

'" )

~ t Boo -

t BoA -

~ ~\

BUSY L

-.'1J

twoo

'II

DATAoUT L

-11\
tO~~

TIMING WAVEFORM OF WRITE WITH BUSY
twp------------~

RNi

5-64

VALID

IDT7133S/L AND 1DT7143S/L
CMOS DUAL-PORT RAM 32K (2Kx 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
eEL VALID FIRST:
ADDR
LAND R

BUSY R

eE R VALID FIRST:
ADDR
LANDR

BUSY L

=:x

>C

ADDRESSES MATCH

~t~l
=:x

[t'OC=1>C

ADDRESSES MATCH

~t~l

[t'OC=1-

TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION (1)
LEFT ADDRESS VALID FIRST:

ADDRL

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

ADDRR

taAA9____tBD_A-=--=--.!~---

BUSY R

RIGHT ADDRESS VALID FIRST:
14----

ADDRR

t Rc OR t wc - - - - - . !

ADDRESSES MATCH

ADDRESSES DO NOT MATCH

ADDRL

NOTE:
1.

eEL

= CE R = ~L

5-65

1DT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES
arbitrates between the left and right addresses for access (refer to
Table II). In either mode of arbitration, the delayed port's BUSY flag
is set and will reset when the port granted access completes its operation.

FUNCTIONAL DESCRIPTION:
The IDT7133/43 provides two ports with separate control, address and I/O pins that permit independent access for reads or
writes to any location in memory. The devices have an automatic
power down feature controlled by CEo The CE controls on-chip
power down circuitry that permits the respective port to go into a
standby mode when not selected (CE high). When a port is enabled, access to the entire memo!YJlrray is permitted. Each port
has its own Output Enable control (OE).ln the read mode, the port's
OE turns on the output drivers when set LOW. Non-contention
READNJRITE conditions are illustrated in Table I.

DATA BUS WIDTH EXPANSION,
MASTER/SLAVE DESCRIPTION:
Expanding the data bus width to 32 bits or more in a dual-port
RAM system implies that several chips will be active at the same
time. If each chip includes a hardware arbitrator, and the addresses
for each chip arrive at the same time, it is possible that one will activate its BUSYl while another activates its BUSYRsignal. Both sides
are now busy and the CPUs will wait indefinitely for their port to become free.
To avoid this "Busy Lock-Out" problem, IDT has developed a
MASTER/SLAVE approach where only one hardware arbitrator, in
the MASTER, is used. The SLAVE has BUSY inputs which allow an
interface to the MASTER with no external components and with a
speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a
contention situation. Conversely, the write pulse must extend a
hold time past BUSY to ensure that a write cycle takes place after
the contention is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the same
time.
The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs,
the write to the SLAVE will be inhibited due to BUSY from the
MASTER.

ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION:
The arbitration logic will resolve an address match or a chip enable match down to 5ns minimum and determine which port has
access. In all cases, an active BUSY flag will be set for the delayed
port.
The BUSY flags are provided for the situation when both ports
simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic will determine which port has
access and sets the delayed port's BUSY flag. BUSY is set at
speeds that permit the processor to hold the operation and its respective address and data. It is important to note that the operation
is invalid for the port that has BUSY set LOW. The delayed port will
have access when BUSY goes inactive.
Contention occurs when both left and right ports are active and
both addresses match. When this situation occurs, the on-chip arbitration logic determines access. Two modes of arbitration are
.provided: (1) if the addresses match and are valid before CE, onchip control logic arbitrates between CEland CE Rfor access; or (2)
if the CEs are low before an address match, on-chip control logic

TABLE I-NON-CONTENTION READ/WRITE CONTROL(4)
LEFT OR RIGHT PORT (1)
R/WLB

R/W uB

X

CE
H

OE

X
X

X

H

X

Z

L

L

L

X

DATAIN

L

H

L

L

H

L

L

L

H

H

I/O 0-7
Z

FUNCTION

I/Os_15

Z

Port Disabled and in Power Down mode, IS82 or IS84

Z
DATA IN

CE R= CE l = H, Power Down Mode, IS81 or IS83
Data on Lower Byte and Upper Byte Written into Memory(2)

DATAIN

DATAoUT

Data on Lower Byte Written into Memory~2)Data in Memory Output on Upper Byte (3)

L

DATA OUT

DATA IN

Data in Memory Output on Lower Byte\3)Data on Upper Byte Written into Memory(2)

L

H

DATA IN

Z

Data on Lower Byte Written into Memory(2)

L

L

H

Z

DATA IN

Data on Upper Byte Written into Memory(2)

H

H

L

L

DATA OUT

Data in Memory Output on Lower Byte and Upper Byte(3)

H

H

L

H

X

DATA OUT

Z

Z

High Impedance Outputs

NOTES:
1. AOl-AlOl*AoR-AlOR
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. H = High, L = Low, X = Don't Care, Z = High Impedance, LB

=

Lower Byte, US = Upper Byte

5-66

IDT7133S/L AND 1DT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE II-ARBITRATION
LEFT PORT

FLAGS (1)

RIGHT PORT

FUNCTION
AOl - A 10l

CE R

H

X

L

Any

H

X

CE l

L

BUSYl

H

X

H

H

No Contention

H

X

H

H

No Contention

L

Any

H

H

No Contention

H

H

No Contention
L-PortWins

L

t- AOR-A1OR

BUSYR

A OR - A 10R

t- AOl -A1Ol

ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
L

LV5R

L

LV5R

H

L

L

RV5L

L

RV5L

L

H

R-PortWins

L

Same

L

Same

H

L

Arbitration Resolved

L

Same

L

Same

L

H

Arbitration Resolved

CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL5R

= AOR-A1OR

LL5R

= AOL -Al0L

H

L

L-PortWins

RL5L

= AOR-A1OR

RL5L

= AOL -Al0L

L

H

R-PortWins

LW5R

= AOR-Al0R

LW5R

= AOL -Al0L

H

L

Arbitration Resolved

LW5R

= AOR-Al0R

LW5R

= AOL -Al0L

L

H

Arbitration Resolved

NOTE:
1. X = Don't Care, L = Low, H = High
LV5R = Left Address Valid ;::: 5ns before right address
RV5L = Right Address Valid ;::: 5ns before left address
Same = Left and Right Address match within 5ns of each other

CAPACITANCE
SYMBOL

(TA = +25°C, f

PARAMETER(l)

CIN

Input Capacitance

COUT

Input/Output
Capacitance

LLSR = .Left CE = LOW ;::: 5ns before Right CE
RL5L = Right cr = LOW ;::: 5ns before Left cr
LW5R = Left and Right CE = LOW within 5ns of each other

= 1.0MHz)

CONDITIONS

MAX.

UNIT

VIN

= OV

11

pF

Vvo

= OV

11

pF

NOTE:
1. This parameter is determined by device characterization but is not
production tested.

5-67

IDT7133S/L AND IDT7143S/L
CMOS DUAL-PORT RAM 32K (2K x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT MASTER/SLAVE DUAL-PORT MEMORY SYSTEMS
RIGHT

LEFT
~

RNi

IDT7133
MASTER

4~+5V

..
~

RNi

-

RNi
BUSY

BUSY

+5V

IDT7143
SLAVE(1)

~ BUSY

'\IV'

RNi
BUSY

-~

NOTE:
1. No arbitration in IDT7143 (SLAVE). BUSY-IN inhibits write in IDT7143 (SLAVE).

ORDERING INFORMATION
IDT

xxxx

A

999

A

A

Device Type

Power

Speed

Package

Process/
Temperature
Range

y:raok
I ~C

'---------1 ~
1

1

55

Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Sidebraze Shrink-DIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Pin Grid Array
Commercial Only

~-------~170
90

' - - - - - - - - - - - - - - - l lISL

..............................................................................................._41I 7133
7143

~

5-68

}
Speed in Nanoseconds

Low Power
Standard Power
32K (2K x 16-Bit) MASTER Dual-Port RAM
32K (2K x 16-Bit) SLAVE Dual-Port RAM

FEATURES:

DESCRIPTION:

• High-speed access
- Military: 45/55/70ns (max.)
- Commercial: 45/55/70ns (max.)

The 1017134 is an extremely high-speed 4K x 8 dual-port static
RAM designed to be used in systems where on-chip hardware port
arbitration is not needed. This part lends itself to those systems
which cannot' tolerate wait states or are designed to be able to
externally arbitrate or withstand contention when both sides
simultaneously access the same dual-port RAM location.
The 1017134 provides two independent ports with separate
control, address and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. It is t h e O i
user's responsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports. An automatic power down feature, controlled by CE, permits the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using lOT's CEMOS 1M high-performance technology, these dual-ports typically operate on only 500mW of power at
maximum access times as fast as 45ns. Low-power (L) versions
offer battery backup data retention capability, with each port
typically consuming 200J.lW from a 2V battery.
The 1017134 is packaged in either a sidebraze or plastic 48-pin
DIP and 52-pin LCC and PLCC. Military grade product is manufactured in compliance with the latest revision of MIL-STO-883,
Class B.

• Low-power operation
- 1017134S
Active: 500mW (typ.)
Standby: 5mW (typ.)
- 1017134L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Battery backup operation - 2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in several popular hermetic and plastic packages
• Military product compliant to MIL-STO-883, Class B

FUNCTIONAL BLOCK DIAGRAM

RIW R

RlWL--~~-------a

~------~+--- ~R

~L--~~-------a

L-~>------ O'ER

OEL---~p~oc~zr<~<~
.

~

LJ LJ LJ LJ U

U

6 5 4 3 2

7

I I LJ LJ LJ LJ U

U 52 51 50
1

J 10
J 11

LJ

49 48 47
46::: OE R
45 ::: AOR
44::: AIR

43C A2R

J 12
J 13

42 :::
41 :::
40 :::
39 C
38 :::
37 :::
36 :::
35 :::

J52-1
&
L52-1

A3R
A4R

A5R
A6R

A7R
A8R

A9R
NC

JM
~C
21 22 23 24 25 26 27 28 29 30 31 32 33
r'

,.1

r,

''''I I' ''''1'''

r"'l r, "

I/0 7R

r, r"'l r"'l

LCC/PLCC
TOP VIEW

DIP
TOP VIEW

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TBIAS

Temperature
Under Bias

TSTG

Storage
Temperature

PT
lOUT

-0.5 to +7.0

o to

+ 70

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT
V

-55 to + 125

°C

-55 to +125

-65 to + 135

°C

-55 to +125

-65 to +150

°C

Power Dissipation

1.5

1.5

W

DC Output Current

50

50

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

SYMBOL
CIN

Input CapaCitance

COUT

Output CapaCitance

CONDITIONS

MAX.

UNIT

VIN = OV

11

pF

Vour= OV

11

pF

NOTE:
1. This parameter is determined by device characterization but is not
production tested.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Military
Commercial

AMBIENT
TEMPERATURE
-55°C to +125°C

GND
OV

5.0V ± 10%

O°C to +70°C

OV

5.0V ± 10%

Vce

RECOMMENDED DC OPERATING CONDITIONS
MIN.

TYP.

MAX.

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

-

6.0

V

V1L

Input Low Voltage

-0.5(1)

-

0.8

V

SYMBOL

PARAMETER

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

5-70

UNIT

1DT7134S AND 1DT7134L
CMOS DUAL-PORT RAM 32K (4K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL

(Vee = 5.0V ±10%)

10
10
0.4

10l = SmA

-

0.5

IOH= -4mA

2.4

-

Input Leakage Current

Vee

IILOI

Output Leakage Current

CE = V1H,VOUT = OV to Vee

Output Low Voltage

VOH

Output High Voltage

7'

5.5V. V1N = OV to Vee

Iol = 6mA

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (1)
SYMBOL

PARAMETER

TEST CONDITION
CE =V1l
Outputs Open
f = f MAX (3)

ISBl

Standby Current
(Both Ports- TTL
Level Inputs)

MIL.
CEl and CER ~ V1H
f = fMAX (3)
COM·L.

ISB2

Standby Current
(One Port- TTL
Level Inputs)

GEL or CE R ~ \fH MIL.
Active Port Outputs
Open, f = fMAX (3)
COM'L.

ISB3

Both Ports CE land MIL.
Full Standby Current
CE R ;::: Vcc -0.2V
(Both Ports-All CMOS
\'IN ~ Vcc -0.2V or COM'L.
Level Inputs)
\'IN ::; 0.2V, f = 0(3)

ISB4

Full Standby Current
(One Port-All CMOS
Level Inputs)

MIL.
COM'L.

One Port CEl or
MIL.
CE R ;::: Vec -0.2V
V1N ;::: Vcc -0.2V or
\'IN ::; 0.2V,
Active Port Outputs COM·L.
Open, f = fMAX (3)

UNIT

5

Jl.A

-

5

Jl.A

0.4

0.5

-

-

2.4

V
V

(Vee = 5.0V ±10%)

IDT7134x45
TYP.(2)
MAX.

IDT7134x55
TYP.(2)
MAX.

S
L
S
L
S
L
S
L
S
L
S
L

100
100
100
100
25
25
25
25
50
50
50
50

100
100
100
100
25
25
25
25
50
50
50
50

230
180
200
160
70
50
70
40
150
120
130
100

100
100
100
100
25
25
25
25
50
50
50
50

230
180
200
160
70
50
70
40
150
120
130
100

S
L

1.0
0.2

240
200
200
160
70
50
70
40
160
130
130
100
30
10

1.0
0.2

30
10

1.0
0.2

30
10

S
L

1.0
0.2

15
4.0

1.0
0.2

15
4.0

1.0
0.2

15
4.0

S
L

50
45

130
100

50
45

120
90

50
45

120
90

S
L

45
45

110
90

50
45

110
90

50
45

110
90

VERSION

Dynamic Operating
Current (Both Ports
Active)

Icc

-

-

Ilu l

VOL

IDT7134L
MAX.
MIN.

IDT7134S
MAX.
MIN.

TEST CONDITIONS

PARAMETER

IDT7134x70
TYP.(2)
MAX.

UNIT

mA

mA

mA

mA

mA

NOTES:
1. ·x· in part number indicates power rating (S or L).
2. Vcc = 5V, TA = +25°C
3. fMAX = 1/tRC = All inputs cycling atf = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS
level standy I SB3 .

5-71

IDT7134S AND IDT7134L
CMOS DUAL-PORT RAM 32K (4K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES(1)
(L Version Only) VLC = 0.2V, VHC
SYMBOL
VDR
ICCDR

= Vcc -

0.2V
TEST CONDITION

PARAMETER

MIN.

Vcc for Data Retention
Data Retention Current

CE ;:::VHC
\'IN ;::: VHC or~ VLC

t CDR (3)

Chip Deselect to Data Retention Time

t R(3)

Operation Recovery Time

I MIL.
I COM'L.

TYP.
V cc @
3.0V
2.0V

2.0

-

-

-

0

-

t RC (2)

-

-

NOTES:
1. VCC = 2V, TA = +2SoC
2. t RC = Read Cycle Time
3. This parameter is guaranteed but not tested.

LOW Vee DATA RETENTION WAVEFORM

DATA RETENTION MODE

'bc

4.SV

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
Sns
1.SV
1.SV
See Figures 1 & 2

5V

DATAoUT

~

7750

:q

5V

12S00
DATA OUT
30pF*

7750

Figure 1. Output Load

12S00
SpF*

Figure 2. Output Load
(for tu,t HZ ' twz,t ow )

*Including scope and jig.

5-72

-

MAX.
V cc @
2.0V
3.0V

-

-

4000

TBD

1S00

TBD

UNIT
V
~A

-

-

ns

-

-

ns

1OT7134S AND 1OT7134L
CMOS DUAL-PORT RAM 32K (4K x a-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
SYMBOL

IOT7134S55
IDT7134L55
MIN.
MAX.

IDT7134S45
IDT7134L45
MIN.
MAX.

PARAMETER

IOT7134S70
IDT7134L70
MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

45

-

55

-

70

-

ns

tAA

Address Access Time

45

-

55

-

70

ns

70

ns

40

ns

5

5

-

ns

5

-

5

-

ns
ns

tAcE

Chip Enable Access Time

t AOE

Output Enable Access Time

-

tOH

Output Hold From Address Change

5

tLZ

Output Low Z Time(l. 2)

5

-

tHZ

Output High Z Time(l. 2)

-

25

-

30

-

40

t pu

Chip Enable to Power Up Time(2)

0

-

0

-

0

-

ns

t pD

Chip Disable to Power Down Time(2)

-

50

-

50

-

50

ns

45
25

55
30

NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.

TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE

(1,2,4)

ADDRESS

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE

(1,3)

~----- tACE-----t....1

DATA OUT

CURRENT

L

_ ____~~--------_tPD-1 4 - - - - tLZ

Icc

---~

pu+1

t

50%

50%

ISB

NOTES:
1. RNi is high for Read Cycles.
2. Device is continuously enabled, CE =
3. Addresses valid prior to or coincident with CE transition low.
4. OE = V1L

"'L'

5-73

IDT7134S AND IDT7134L
CMOS DUAL-PORT RAM 32K (4K x a-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
PARAMETER

SYMBOL

1DT7134S45
IDT7134L45
MAX.
MIN.

IDT7134S55
IDT7134L55
MAX.
MIN.

IDT7134S70
1DT7134L70
MIN.
MAX.

UNIT

WRITE CYCLE
twc

Write Cycle Time

45

-

55

-

70

-

tEW

Chip Enable to End of Write

40

-

50

60

-

ns

tAW

Address Valid to End of Write

40

-

50

-

60

-

ns

ns

t AS

Address Set-up Time

0

-

0

-

0

-

ns

twp

Write Pulse Width

40

-

50

60

Write Recovery Time

0

0

0

tDW

Data Valid to End of Write

20

-

-

ns

tWR

-

25

-

30

-

ns

tHZ

Output High Z Time(1.2)

-

20

-

25

-

30

ns

tDH

Data Hold Time

3

-

3

-

3

-

ns

twz

Write Enabled to Output in
High Z (1.2)

-

20

-

25

-

30

ns

tow

Output Active From End of Write(1.2)

0

-

0

-

0

-

ns

NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.

5-74

ns

------

---------------------------------------

IDT7134S AND 1DT7134L
CMOS DUAL-PORT RAM 32K (4K X S.BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING (1,2,3,7)
~-----------------------twc----------------------~~

ADDRESS

~---------------------tAW------------------~~

--~~r-------------tw~7) ------------~~t~W~R~~----------------------~-

Rm

------+-----------,

, . . . - - - tow -----....,
DATA OUT

TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING

(1,2,3,5)

~---------------------twc---------------------~~

ADDRESS
~---------------------tAw-------------~

,----4---------------------------~~~------------tEW-------~

Rm

NOTES:

1.
2.
3.
4.
5.
6.
7.

RNi must be high during all address transitions.
A write occurs during the overlap (tEW or twp) of a low CE and a low RiW.
tWR is measured from the earlier of
or RiW going high to the end of write cycle.

cr

During this period, the I/O pins are in the output state, and input Signals must not be applied.
If the CE low transition occurs simultaneously with or after the Rm low transition, the outputs remain in the high impedance state.
Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
If OE is low during a RNi controlled write cycle, the write pulse width must be the larger of twp or (twz + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW' If OE: is high during an RlW controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t wP '

5-75

IDT7134S AND 1DT7134L
CMOS DUAL-PORT RAM 32K (4K X S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 1- NON-CONTENTION
READ/WRITE CONTROL

FUNCTIONAL DESCRIPTION:
The IDT7134 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to
any location in memory. These devices have an automatic power
down feature controlled by CEo The CE controls on-chip power
down circuitry that permi!§Jhe respective port to go into standby
mode when not selected (CE high). When a port is enabled, access
to the entire memo'Y array is permitted. Each port has its own Output Enable cqntrol (DE). In the read mode, the port's DE turns on
the output drivers when set LOW. Non-contention READ/WRITE
conditions are illustrated in the table below.

LEFT OR RIGHT PORT

(1)

FUNCTION

R/W

CE

OE

X

H

X

Z

Port Disabled and in Power Down
Mode. IS82 or IS84

X

H

X

Z

CE R = CEl = H, Power Down
Mode,ls81 or 1583

L

L

X

DATA IN

Data on Port Written Into

H

L

L

DATA OUT

Data in Memory Output on Port

X

X

H

00-7

Z

~emory

High Impedance Outputs

NOTE:
1.

AOL -AllL#oAOR-Al1R
H = HIGH. L = LOW. X = DON'T CARE. Z = HIGH IMPEDANCE

ORDERING INFORMATION
IDT

XXXX

A

Device Type Power

999

A

A

Speed

Package

Process/
Temperature

~"~:'Mk
~

______________

P

~

C
J
L

L..------------------------I
L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-j

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
Plastic DIP
Sidebraze DIP
PLCC
LCC

45
55
70

Speed in Nanoseconds

L
S

Low Power
Standard Power

'--___________________________--1 7134

5-76

Commercial (O°C to

32K (4K x 8-Bit) Dual-Port RAM

FEATURES:

DESCRIPTION:

• High-speed access
- Military: 45/55/70ns (max.)
- Commercial: 45/55/70ns (max.)
• Low-power operation
- IDT71342S
Active: 500mW (typ.)
Standby: 5mW (typ.)
- IDT71342L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Full on-chip hardware support of semaphore signalling between ports
• Battery backup operation - 2V data retention
• TTL-compatible; slngle+5V(±10%) power supply
• Available In popular hermetic and plastic packages
• Military product compliant to MIL-STD-883, Class B

TheIDT71342 is an extremely high-speed 4K x 8 dual-port static
RAM with full on-chip hardware support of semaphore signalling
between the two ports.
The IDT71342 provides two independent ports with separate
control, address and I/O pins that permit independent, asynchronous access for reads and writes to any location in memory. To
assist in arbitrating between ports, a fully Independent semaphore
logic block is provided. This block contains unassigned flags
which can be accessed by either side; however, only one side can
control the flag at a~e. An automatic power down feature, controlled by CE and SEM, permits the on-chip circuitry of each port
to enter a very low standby power mode (both CE and SEM high).
Fabricated using IDT's CEMOS 1M high-performance tachnologythis device typically operates on only 500mW of power at maximum access times as fast as 45ns. Low-power (L) versions offer
battery backup data retention capability, with each port typically
consuming 200JlW from a 2V battery. The device is packaged in
either a hermetic 52-pin lead less chip carrier or a 52-pin PLCC.
The1DT71342 military devices are manufactured In compliance
with the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

~
I/00l- 1/0 7l

,

.~

-

COWMN
I/O

~ COWMN
1/0

---..

MEMORY
ARRAY

~

~

SEMAPHORE
LOGIC

~

...,.

~

---

T

~
~I

-

r:::

-..

1-

....,.

~

LEFT SIDE
ADDRESS
DECODE
LOGIC

RIGHT SIDE
ADDRESS
DECODE
LOGIC

SEM R

--

'"

CEMOS Is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
05C-1035/-

5-77

IDT71342S AND 1DT71342L CMOS
DUAL-PORT RAM 32K (4K X 8-BIT) WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

INDEX
LJ LJ LJ LJ LJ LJ I I LJ LJ LJ LJ LJ LJ

7 6 5 4

All
A2l
A3l
A4l
A5l
ASl
A7l
ASl
A9l
I/Ool
1I0 1l
I/0 2l
I/03l

:IS
:I 9
Jl0
J 11
J 12
J 13

3

2

U 5251 50
1

J52-1
&
L52-1

49 4S 47
461:
45 I:
44:::
43 I:
42 I:
41 :::
401:
391:
381:
371:
3SI:

Jro

OE R
AOR
AIR

A2R
A3R

A4R
A5R

ASR

A7R
ASR

35[

A9R
NC

~I:

I/07R

21 22 23 24 2526 2728 29 30 31 32 33
r, r1 r, ,., .-, r-, r., r, •., ,., r, r'"l "

LCC/PLCC
TOP VIEW

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

-0.5 to +7.0

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAs

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.5

1.5

W

lOUT

DC Output Current

50

50

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

SYMBOL
CIN

Input CapaCitance

COUT

Output Capacitance

MAX.

UNIT

VIN = OV

11

pF

VOUT= OV

11

pF

CONDITIONS

NOTE:
1. This parameter is determined by device characterization but is not production tested.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Military
Commercial

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V ± 10%

O°C to +70°C

OV

5.0V ± 10%

Vee

RECOMMENDED DC OPERATING CONDITIONS
MIN.

TYP.

MAX.

Vce

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

-

6.0

V

Vil

Input Low Voltage

-0.5(1)

-

0.8

V

SYMBOL

PARAMETER

NOTE:
1. Vil (min.) = -3.0V for pulse width less than 20ns.

5-78

UNIT

------ .------------------------------------------------------------------------------------------------1OT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x B-BIT) WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(Vee = 5.0V ±10%)

SYMBOL

-

5

IJ..A

-

10

IJ..A

0.4

0.4

-

0.5

-

5

2.4

-

2.4

-

Input Leakage Current

Vee = 5.5V, '"IN = OV to Vee

-

IILOI

Output Leakage Current

CE = '"IH' VOUT = OV to Vee
IOl = 6mA

h

Output Low Voltage

VOH

Output High Voltage

= 8mA

IOH= -4mA

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

Icc

Icel

ISBl

ISB2

ISB3

ISB4

PARAMETER

Dynamic Operating
Current (Both Ports
Active)

TEST CONDITION
CE = V1l
Outputs Open
~ = Don't Care

V

0.5
V

(Vee = 5.0V ±10%)

IDT71342x45
TYP.(2)
MAX.

1OT71342x55
TYP.(2)
MAX.

IOT71342x70
TYP.(2)
MAX.

S
L
S
L

100
100
170
100

240
200
200
160

100
100
100
100

230
180
200
160

100
100
100
100

230
180
200
160

VERSION

MIL.

(1)

UNIT

10

Ilu l

VOL

IOT71342L
MAX.
MIN.

IOT71342S
MIN.
MAX.

TEST CONDITIONS

PARAMETER

f = f MAX (3)

COM'L.

Dynamic Operating
Current
(Semaphores
Both Sides)

CE ='"IH
SEM ='"Il
Outputs Open
f = f MAX (3)

MIL.

S
L

85
85

130
110

85
85

130
110

85
85

130
110

COM'L.

S
L

85
85

130
100

85
85

130
100

85
85

130
100

Standby Current
(Both Ports - TTL
Level Inputs)

MIL.
CEl or CE R ?: V1H
SEM l = SEM R ?:'"IH
COM'L.
f = f MAX (3)

Standby Current
(One Port- TTL
Level Inputs)

CEl or CE R ?: V1H
MIL.
Active Port Outputs
Open, f = f MAX (3)
SEMl =SEMR?: '"IH COM'L.

Full Standby Current
(Both PortsAll CMOS Level
Inputs)

Both Ports CEl and
MIL.
CE R ?: Vee -0.2V
'"IN ?: Vee -0.2V or
'"IN :5 0.2V
SEM l = SEM R ?:
COM'L.
Vcc -0.2V, f = 0(3)

One Port CE l or
CE R ?: Vee -0.2V
Full Standby Current '"IN ?: Vee -0.2V or
(One Port-All CMOS
V1N :5 0.2V,
Level Inputs)
Active Port Outputs
Open, f = f MAX (3)

r

~~

~g

~~

~g

~~

~g

25
25
50
50

70
40
160
130

25
25
50
50

70
40
150
120

25
25
50
50

70
40
150
120

S
L

50
50

130
100

50
50

130
100

50
50

130
100

S
L

1.0
0.2

30
10

1.0
0.2

30
10

1.0
0.2

30
10

S
L

1.0
0.2

15
4.0

1.0
0.2

15
4.0

1.0
0.2

15
4.0

MIL.

S
L

50
45

130
100

50
45

120
90

50
45

120
90

COM'L.

S
L

45
45

110
90

50
45

110
90

50
45

110
90

S
L
S
L

UNIT

mA

mA

mA

mA

mA

mA

NOTES:
1. ·x· in part numbers indicates power rating (S or L).
2.
3.

Vee = 5V, TA = +25°C
fMAX = 1/tRc = All inputs cycling aU = 1/t Rdexcept Output Enable). f = 0 means no address or controllines change. Applies only to inputs at CMOS level
standby, ISB3 .

5-79

1DT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x 8-BIT) WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES(1)
(L Version Only) VLC = 0.2V, VHC = Vcc - 0.2V
SYMBOL
VDR

TEST CONDITION

PARAMETER

MIN.

ICCDR

Data Retention Current

t CDR(3)

Chip Deselect to Data Retention Time

t R(3)

Operation Recovery Time

CS ~VHC
\'IN ~ VHC ors VLC

-

-

-

-

-

-

4000

TBD

-

-

-

4000

TBD

0

-

-

-

...:

ns

t RC,<2)

-

-

-

-

ns

1. Vcc = 2V, TA = +25°C
2. t Rc = Read Cycle Time
3. This parameter is guaranteed but not tested.

LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE

AC TEST CONDITIONS
GND to3.0V
5ns
1.5V
1.5V
See Figures 1 & 2

5V

DATAoLrr

~

7750,

5V

12500'
DATA OUT
30pF*

~

7750,

Figure 1. Output Load

12500'
5pF*

Figure 2. Output Load
(for tU.t HZ ' twz.tow)
* Including scope and jig.

5-80

UNIT

-

I MIL.
I COM'L.

NOTES:

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

MAX.
Vcc @
2.0V
3.0V

2.0

-

Vcc for Data Retention

TYP.
Vcc @
3.0V
2.0V

V
J.lA

--_ _------------------------------------------...

10T71342S AND IOT71342L CMOS
OUAL·PORT RAM 32K (4K x 8-BIT) WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

IOT71342S45
10T71342L45
MIN.
MAX.

PARAMETER

IOT71342S55
1DT71342L55
MIN.
MAX.

IOT71342S70
1DT71342L70
MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

45

-

55

-

70

-

ns

tM
t ACE

Address Access Time

45

-

55

ns

45

-

55

t AOE

Output Enable Access Time

-

25

-

30

-

70

Chip Enable Access Time (3)

-

tOH

Output Hold From Address Change

5

-

5

Output Low Z Time

5

-

5

-

5

tLZ
tHZ

Output High Z Time (1. 2)

-

25

-

tpu

Chip Enable to Power Up Time

0

-

tPD

Chip Disable to Power Down Time (2)

-

tsop

Sem Fig update Pulse (OE or SEM)

15

(1. 2)

(2)

70

ns

40

ns

-

ns

5

30

-

40

ns

0

-

0

-

ns

50

-

50

-

50

ns

-

20

-

20

-

ns

NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3. To access RAM. CE = '-"L' SEM = '-"H' To access semaphore; CE = \lH' SEM = VIL.

TIMING WAVEFORM OF READ CYCLE NO.1, EITHER SIDE

ADDRESS

DATA OUT

(1.2,4)

~~H~
~~.,.....----_t=~~
VAUD¥

XX~'"-------D-AT-A-VA-L-ID-----~

PREVIOUS DATA

TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE

(1.3)

,

tsoP--.J·...- - - - tAcE----o-i~
CEor

jl4----

SE'M (5)

")'l
\
~----~~----------~--~

tsOP+-----l,.,j\---- t AOE ~ t

LZ

-.

t HZ ....

-~,-/~/~--~-----~I~

~\~\~~--+_DA-T-A-VA-U-D--~~

DATA OUT
•

Icc
CURRENT

1--),.----+----

_

_

tLZ---~

~

- ~~------tpD
PU4
~W%

W%

NOTES:
1. Rm is high for Read Cycles.
2. Device is continuously enabled. CE = '-"L' This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CE transition low.
4. DE = VIL
5. To access RAM. CE = VIL • SEM = VIH . To access semaphore. CE = \lH' SEM = VIL.

5-81

ns

ILJIII

1DT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x S-BIT) WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
SYMBOL

1DT71342S45
IDT71342L45
MIN.
MAX.

PARAMETER

IDT71342S55
IDT71342L55
MIN.
MAX.

IDT71342S70
IDT71342L70
MIN.
MAX.

UNIT

WRITE CYCLE
55

-

70

50

-

60

40

-

50

60

Address Set-up Time

0

-

0

-

twp

Write Pulse Width

40

50

tWR

Write Recoverv Time

0

0

tDW

Data Valid to End of Write

20

-

tHZ

Output High Z Time (1.2)

-

tDH

Data Hold Time

twz

Write Enable to Output in
High Z (1.2)

twc

Write Cycle Time

tEW

Chip Enable to End of Write

tAW

Address Valid to End of Write

t AS

ns

0

-

-

60

-

ns

0
30

-

ns

25

-

20

-

25

-

30

ns

3

-

3

-

3

-

ns

-

20

-

25

-

30

ns

-

0

-

0

-

ns

10

-

10

ns

10

-

10

-

45
(3)

40

tow

Output Active From End of Write (1.2)

0

tSWR

SEM Flag Write to Read Time

10

tsps

SEM Flag Contention Window

10

NOTES:
1. Transition is measured ±500mV from low or high impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not tested.
3.

To access RAM, CE

= V,L' SEM = V,H' To access semaphore, CE = V,H' SEM = V,L' This condition must be valid for entire tEW time.

5-S2

ns
ns
ns

ns

ns

IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x 8-BIT) WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, R/W CONTROLLED TIMING (1,2,3,7)
twc
ADDRESS

~

----I

)(

K

z'6)-

tH

/V
tAW
GEor
SEM (8)

RNi

~

/~

~
~tAS

t

(7)

tWR

Wp

/~

"

-

i----twt)tow
DATA OUT

-. :. . . ». ..............> . . . . . . (4) .•><><>~

-'.
_tow

t oH -

-'

DATA IN

(4).») " -

'"

'"

./

TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED TIMING (1,2,3,5,9)

~----------------------twc----------------------~

ADDRESS

GEor
SEM (8)

---~------------- tEW

-------------+-1

RNi

NOTES:
1. Rm must be high during all address transitions.
2. A write occurs during the overlap (tEW or twp) of a low CEor srn and a low RNI.
3. tWR is measured from the earlier of CE or Rtw (or SEM or R/W). going high to the end of write cycle.
4. During this period, the 1/0 pins are in the output state, and input signals must not be applied.
5. If the GE or SEM low transition occurs simultaneously with or after the Rm low transition, the outputs remain in the high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. If DE is low during a Rm controlled write cycle, the write pulse width must be the larger of twp or (twz + tow) to allow the 110 drivers to turn off
and data to be placed on the bus for the required tow. If ~ is high during an Rm controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t wP .
8. To access RAM, GE = "IL' SEM = "IH. To access semaphore, GE = "IH' SEM = VIL. Either condition must be valid for the entire tEWtime.
9. DE = VIL

5-83

IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x 8-BIT) WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE (1)

VALID ADDRESS

VALID ADDRESS

DATA 0

RNi

Write Cycle ---~f--- Test Cycle
(Read Cycle)

NOTE:
1. CE

= V1H

for the duration of the above timing (both write and read cycle).

TIMING WAVEFORM OF SEMAPHORE CONTENTION

(1,3,4)

A OA - A2A
SIDE (2) 'A"

ANiA
SEM A

MATCH

fts~

X

A OB - A2B
SIDE (2) "B"

ANiB
SEM B

NOTES:

'-"H '

1. DOR = DOL = V IL' CE R = CE L =
semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. Either side "A" = left and side "B" = right. or side "A" = right and side "8" = left.
3. This parameter is measured from the point where ANiA or SEM A goes high until ANi B or SEM B goes high.
4. If tsps is violated. the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

5-84

IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x 8-BIn WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The eight semaphore flags reside within the IDT71342 in a
separate memory space from the dual-port .RAM. This address
space is accessed by placing a low input on the SEM pin (which
acts as a chip select for the semaE!']ore flags) and using the other
control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins
Ao - A2. When accessing the semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin Do is used. If a low
level is written into an unused semaphore location, that flag will be
set to a zero on that side and a one on the other (see Table II). That
semaphore can now only be modified by the side showing the
zero. When a one is written into the same location from the same
side, the flag will be set to a one for both sides (unless a semaphore
request from the other side is pending) and then can be written to
by both sides. The fact that the side which is able to write a zero into
a semaphore subsequently locks out writes from the other side is
what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side
will be stored in the semaphore request latch for that side until the
semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data
bits so that a flag that is a one reads as a one in all data bits and a
flag containing a zero reads as all zeros. The read value is latched
into one side's output register when that side's semaphore select
(SEM) and output enable (OE) signals go active. This serves to
disallow the semaphore from changing state in the middle of a read
cycle due to a write cycle from the other side. Because of this latch,
a repeated read..2!. a semaphore in a test loop must cause either
signal (SEM or OE) to go inactive or the output will never change.
A sequence of WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to
write a zero into a semaphore location. If the semaphore is already
in use, the semaphore request latch will contain a zero, yet the
semaphore flag will appear as a one, a fact which the processor will
verify by the subsequent read (see Table II). As an example, assume a processor writes a zero to the left port at a free semaphore
location. On a subsequent read, the processor will verify that it has
written successfully to that location and will assume control over
the resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will fail,
as will be verified by the fact that a one will be read from that semaphore on the right side during a subsequent read. Had a sequence
of READ/WRITE been used instead, system contention problems
could have occurred during the gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 3. Two semaphore request latches feed into a semaphore flag. Whichever latch
is first to present a zero to the semaphore flag will force its side of
the semaphore flag low and the other side high. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side's semaphore request latch have been written
to a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side's request
latch. The second side's flag will now stay low until its semaphore
request latch is written to a one. From this it is easy to understand
that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can
hang up until a one is written into that semaphore request latch.

FUNCTIONAL DESCRIPTION
The IDT71342 is an extremely fast dual-port 4K x 8 CMOS static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or
right side of the dual-port RAM to claim a privilege over the other
processor for functions defined by the system designer's software.
As an example, the semaphore can be used by one processor to
inhibit the other from accessing a portion of the dual-port RAM or
any other shared resource.
The dual-port RAM features a fast access time, and both ports
are completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right
port. Both ports are identical in function to standard CMOS static
RAMs and can be read from, or written to, at the same time with the
only possible conflict arising from the simultaneous writing of, or a
simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may
be used by the system program to avoid any conflicts in the nonsemaphore portion of the dual-port RAM. These devices have an
automatic power-down feature controlled by CE, the dua~
RAM enable, and SEM, the semaphore enable. The CEand SEM
pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the
condition which is shown in Table I where CE and SEM are both
high.
Systems which can best use the IDT71342 contain multiple
processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These
systems can benefit from a performance increase offered by the
IDT71342's hardware semaphores, which provide a lockout
mechanism without requiring complex programming.
Software handshaking between processors offers the maximum
in system flexibility by permitting shared resources to be allocated
in varying configurations. The IDT71342 does not use its semaphore flags to control any resources through hardware, thus allowIng the system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never
incurred in either processor. This can prove to be a major advantage in very high-speed systems.

HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are independent of the dual-port RAM. These latches can be used to pass a
flag, or token, from one port to the other to indicate that a shared
resource is in use. The semaphores provide a hardware assist for a
use assignment method called "Token Passing Allocation." In this
method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to
use this resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by reading it.
If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines
that the right side processor had set the latch first, has the token
and is using the shared resource. The left processor can then either
repeatedly request that semaphore's status or remove its request
for that semaphore to perform another task and occasionally
attempt again to gain control of the token via the set and test
sequence. Once the right side has relinquished the token, the left
side should succeed in gaining control.
The semaphore flags are active low. A token is requested by
writing a zero into a semaphore latch and is released when the
same side writes a one to that latch.

5-85
~~---

..- - ..

--------------

ID171342S AND ID171342L CMOS
DUAL-PORT RAM 32K (4K X 8-BIT) WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE I-NON-CONTENTION READ/WRITE CONTROL
LEFT OR RIGHT PORT (1)
R/W

CE

SEM

OE

X

H

H

X

Z

H

H

L

L

DATA OUT

X

X

X

H

Z

H

L

X

H

L

H

L

L

H

X

L

L

X

-

S

FUNCTION

DO-7
Port Disabled and in Power Down
Mode
Data in Semaphore Flag
Output on Port
Output Disabled

DATA IN

Port Data Bit Do Written Into
Semaphore Flag

L

DATA oUT

Data In Memory Output on Port

X

DATA IN

Data On Port Written Into Memory
Not Allowed

NOTE:
1.

AOL - A10L ;6 AOR - A 10R
H = HIGH, L = LOW, X = DON'T CARE, Z
= Low-to-High transition

S

= HIGH IMPEDANCE

TABLE 11- EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE
FUNCTION

Do - D7 LEFT

STATUS

Do - D7 RIGHT

No Action

1

1

Semaphore free

Left Port Writes ·0" to Semaphore

0

1

Left port has semaphore token

Right Port Writes ·0" to Semaphore

0

1

No change. Right side has no write
access to semaphore

Left Port Writes "1" to Semaphore

1

0

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

1

0

No change. Left port has no write
access to semaphore

Right Port Writes ·1" to Semaphore

0

1

Left port obtains semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

Right Port Writes ·0" to Semaphore

1

0

Right port has semaphore token

Right Port Writes "1" to Semaphore

1

1

Semaphore free

Left Port Writes ·0" to Semaphore

0

1

Left port has semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

NOTE:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.

5-86

---_._---------------------------------------------------1DT71342S AND 1DT71342L CMOS
DUAL-PORT RAM 32K (4K x 8-BIn WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ing a zero into Semaphore 1. If it succeeded in gaining control, it
would lock out the left side.
Once the left side was finished with its taSk, it would write a one
to Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was
able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would
allow the two processors to swap 2K blocks of dual-port RAM with
each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
dual-port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides
rather than being given a common meaning as was shown in the
example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait
states. With the use of semaphores, once the two devices had determined which memory area was "off limits" to the CPU, both the
CPU and the I/O devices could access their assigned portions of
memory continuously without any wait states.
Semaphores are also useful in applications where no memory
"WAIT" state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned RAM segments at full speed.
Another application is in the area of complex data structures. In
this case, block arbitration is very important. For this application
one processor may be responsible for building and updating a
data structure. The other processor then reads and interprets that
data structure. If the interpreting processor reads an incomplete
data structure, a major error condition may exist. Therefore, some
sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and
then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
interpreting processor to come back and read the complete data
structure, thereby guaranteeing a consistent data structure.

The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same
time. The semaphore logic is specially designed to resolve this
problem. If simultaneous requests are made, the logic guarantees
that only one side receives the token. If one side is earlier than the
other in making the request, the first side to make the tequest will
receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other.
One caution that should be noted when using semaphqres is
that semaphores alone do not guarantee that access to a resource
is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily
happen. Code integrity is of the utmost importance when semaphores are used instead of slower, more restrictive hardware intensive schemes.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power up. Since any
semaphore request flag which contains a zero must be reset to a
one, all semaphores on both sides should have a one written into
them at initialization from both sides to assure that they will be free
when needed.

USING SEMAPHORES - Some Examples
Perhaps the simplest application of semaphores is their application as resource markers for the IDT71342's dual-port RAM. Say
the 4K x 8 RAM was to be divided into two 2K x 8 blocks which were
to be dedicated at anyone time to servicing either the left or right
port. Semaphore 0 could be used to indicate the side which would
control the lower section of memory, and Semaphore 1 could be
defined as the indicator for the upper section of memory.
To take a resource, in this example the lower 2K 'of dual-port
RAM, the processor on the left port could write and then read a zero
into Semaphore O. If this task were successfully completed (a zero
was read back rather than a one), the left processor would assume
control of the lower 2K. Meanwhile, the right processor· would attempt to perform the same function. Since this processor was attempting to gain control of the resource after the left processor, it
would read back a one in response to the zero it had attempted to
write into Semaphore o. At this pOint, the software could choose to
try and gain control of the second 2K section by writing, then read1

I L PORT
,1---

R PORT
SEMAPHORE
REQUEST FLIP FLOP

SEMAPHORE
REQUEST FLIP FLOP

Oo----l

o

Q

Q

WRITE --~

SEMAP~~~6 ~~--------~----~

o

1-----

Do

~--

WRITE

SEMAPHORE
READ

SEMAPHORE LATCH

FIGURE 3. IDT71342 Semaphore Logic

5-87

IDT71342S AND IDT71342L CMOS
DUAL-PORT RAM 32K (4K x 8-BIT) WITH SEMAPHORE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xxxx
Device Type

A
Power

999
Speed

A

A

Package

Process!
Temperature
Range

Y:,aok
J

~------------~ L

'--------------1
'-------------------1
'-----------------------1

5-88

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
PLCC
LCC

45
55
70

Speed in Nanoseconds

L
S

Low Power
Standard Power

71342

32K (4K x 8-Bit) Dual-Port RAM w!Semaphore

substrate using four IDT7132 2K x 8 dual-port RAMs (IDT7M134) or
eight IDT7132 dual-port RAMs (IDT7M135) in leadless chip carri• High-density 64K1128K-bit CMOS dual-port RAM modules
ers. Dual-port function Is achieved by utilization of the two
• 16K x 8 organization (IDT7M135) with 8K x 8 option
on-board IDT54/74FCT138 decoder circuits that interpret the
(IDT7M134)
higl'!erorder addresses A l11 -13 and AR11-13 to select one of the eight
2K x 8 dual-port RAMs. (On IDT7M134 8K x 8 option, the A L13 and
• Low power consum~tion
A R13 need to be extemally grounded and the selection becomes
• CEMOS TM process virtually eliminates alpha particle soft
one of the four 2K x 8 dual-port RAMs.) Extremely high speeds are
error rates (with no organic die coating)
achieved in this fashion due to the use of the IDT7132 dual-port
RAM, fabricated in IDT'sJligh-performance CEMOS technology.
• On-chip port arbitration logic
The IDT7M134/135 pr:oyide two ports with separate control, ad• BUSY flags
dress and I/O pins t/1Cit" parrilit independent access for reads or
• Fully asynchronous operation from either port
writes to any location tl'!~'memory. The BUSY flags are provided
• Single 5V (t10%) power supply
for the situation ~Qen both ports simultaneously access the same
memory locatiOQ;;.~Tbe on-chip arbitration logic will determine
• Dual Vee and GND pins for maximum noise immunity
which port h,Cis~cc:ess and sets the BUSY flag of the delayed port.
• On-chip pull up resistors for open-drain BUSY flag option
BUSY is set at~ds that permit the processor to hold the opera• Inputs and outputs"directly TTL-compatible
tion and ,it~:r~s~e address and data. The delayed port will have
access,:whenBUSY goes high (inactive).
• Fully static operation
'fl1E(IDTIM134/135 are available with access times as fast as
• Modules available with semiconductor components
45ri§ COIT!p1erCial and 60ns military temperature range, with opercompliant to MIL-5TD-883, Class B
a~ing power consumption of only 2.1W/3.5W (max.). The module
• Finished modules tested at Room, Hot and Cold
,.al~offers a standby power mode of 1.4W/2.8W (max.) and a full
temperatures for all AC and DC parameters
'.' !>tandby mode of 660mW/1.3W (max.).
DESCRIPTION:
",AIIIDT military module semiconductor components are manu;::';' . )actured in compliance with the latest revision of MIL-STD-883,
The IDT7M134/135 are 64K1128K-bit high-speed CMOS dual~
ClassB,makingthemideallysuitedtoapplicationsdemandingthe
port static RAM modules constructed on a multi-layered cer~m!q
highest level of performance and reliability.
.

FEATURES:

in

PIN CONFIGURATION

PIN NAMES
LEFT PORT RIGHT PORT

cr L

NAMES

cr R

Chip Enable
Read/write Enable
RtwL
RtwR
Output Enable
OE"R
OE"L
tIDSVl
tIDSVR
"EmS? Flag (Open Drain)
PULL-UP Resistors for
R330L
R330R
Open-drain tIDSV Flag option
Address
AOL - A 13l
AOR - A13R
1I00l -10 7L 1I00R -1I0 7R Data Input/Output
Power
Vee
Ground
GND

DIP
TOP VIEW

NOTES:
1. Both Vee pins need to be connected to the 5V supply and both GND pins need to be grounded
for proper operation.
2. On 8K x 8 IDT7M134 option A13L and A13R need to be extemally connected to ground for proper
operation.
3. For module dimensions. please refer to module drawing M7 in the packaging section.

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
DSC-7023/-

5-89

FEATURES:

DESCRIPTION:

• High-density 256K-bit CMOS dual-port RAM module

The IDT7M137 is a 256K-bit high-speed CMOS dual-port static
RAM module constructed on a multi-layered ceramic substrate using eight IDT7134 dual-port RAMs in leadless chip carriers. The full
32K bytes of dual-port RAM are directly addressable by utilization
of the two on-board IDT54/74FCT138 decoder circuits that interpret the higher order addresses AL12-14 and AR12-14to select one of
the eight 4K x 8 dual-port RAMs. Extremely high speeds are
achieved in this fashion due to the use of the IDT7134 dual-port
RAM, f~bricated in IDT's high-performance CEMOS technology.
The' IDT7M137 proyld,es,two ports with separate control, address and I/O pins t~at peP-rlit independent, asynchronous access
for reads or writes td',a!1y location in the 'memory. The IDT7M 137 is
designed to be l:lsed in systems where on-chip hardware port arbi'tration is not ne9cied. It is the user's responsibility to ensure data
integrity when~imul~neously accessing the same memory location from both po'1s.
The Iq17M1,37 is available with access times as fast as 55ns
commercla!cujd 60ns military temperature range, with operating
power consumption of ';>nly 4W (max.) The modules also offer a
staQdby power mode of 3.6W (max.) and full standby mode of 1.3W

• 32K x 8 organization
• Low power consumption
• CEMOS ™ process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Battery backup operation - 2V data retention
• Fully asynchronous operation from either port
• Single 5V(±10%) power supply
• Dual Vcc and GND pins for maximum noise immunity
• Inputs and outputs directly TTL-compatible
• Fully static operation
• Modules available with semiconductor components compliant
to MIL-STD-883, Class B

(max.).'."
\, {AII.lpT military module semiconductor components are manuin compliance to the latest revision of MIL-STD-883, Class
,"',:B~ making them ideally suited to applications demanding the high, ,·~t level of performance and reliability.
~'factured

'Co:., ,{,"'"

PIN NAMES

PIN CONFIGURATION

NAMES

RIGHT PORT

LEFT PORT

CE"R

CE"L

Chip Enable

Rflh

RIWR

Read/Write Enable

~L

~R

Output Enable

AOL-14L

AOR-14R

Address

I/OoL-7L

I/OoR-7R

Data Input/Output

Vee

Power

GND

Ground

NOTES:
1. Both \be 'pins need to be connected to the 5V supply and both GND
pins need to be grounded for proper operation.
2. On 16K x8JDT7M136 option, A14L and A14R need to be externally connected to ground for proper operation.,
3. For module dimensions, please refer to module drawing M7 in the
packaging section.

DIP
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-7024/-

1987 Integrated Device Technology. Inc.

5-90

DESCRIPTION:

FEATURES:

The IDT7M144/145 are 64K/128K-bit high-speed CEMOS ™
SLAVE dual-port static RAM modules constructed on a multilayered, co-fired, ceramic substrate using four IDT7142 2K x 8
SLAVE dual-port RAMs (IDT7M144) or eight IDT7142 SLAVE dualport RAMs (IDT7M 145) in leadless chip carriers. Dual-port function
is achieved by utilization of the two on-board IDT54/74FCT138 decoder ci rcuits that interpret the higher order addresses At.11-13 and
ARI1-13 to select one of the eight 2K x 8 dual-port RAMs. (On
IDT7M144 8K x 8 option,the AL13 and AR13 need to be externally
grounded and the sel~~i()~ becomes one of the four 2K x 8
dual-port RAMs.) ........ .,:,i';
The IDT7M144/145 are designed as "SLAVE" dual-port RAM
modules to be \J~ed together with the IDT7M135/135 "MASTER"
dual-port RAM mqdules in 16-or-more-bit systems, whereas the
IDT7M 134/135 are designed to be used as stqnd-alone 8-bit dualport RAM ll)odLJ!e~, Using the IDT MASTER/SLAVE dual-port RAM
module approagh in 16-or-more-bit memory system applications
result~i(lt\JlI,speed operation without the need for additional discretel()gh .•. .
Both SLAVE IDT7M144/145 and MASTER IDT7M134/135 modu\es'~rovide two ports with separate control, address and I/O pins
that permit independent asynchronous access for reads or writes
'to any location in the memory. The BUSY flags are provided forthe
situation when both ports simultaneously access the same memory location. BUSY is set at speeds that permit the processor to
';'hold the operation and its respective address and data. The delayed port will have access when BUSY goes high (inactive). The
BUSY pins are outputs on the MASTER and inputs on the SLAVE.

• High-density 64K/128K-bit CMOS SLAVE dual-port RAM
modules
• Easily expands data bus width to 16-or-more-bits when used
with MASTER IDT7M134 or IDT7M135
• 16K x 8 organization (IDT7M145) or 8K x 8 option (IDT7M144)
• High-speed access
- Military: 60ns (max.)
- Commercial: 45ns (max.)
• Low power operation
- Active: 950mW (typ.) (IDT7M144)
- Standby: 20mW (typ.) (IDT7M144)
• BUSY input flags
• Fully asynchronous operation from either port
•
•
•
•
•

Fully static operation
Dual Vee and GND pins for maximum noise immunity
Inputs and outputs directly TTL-compatible
Single 5V(±10%) power supply
Modules available with semiconductor components compliant
to MIL-STD-883, Class B

PIN CONFIGURATION

PIN NAMES
RIGHT PORT

LEFT PORT

CE'R

CE'l

NAMES
Chip Enable

Rflh

R/WR

Read/Write Enable

ot:l
ffiJSYl

C5E"R

Output Enable

ffiJSYR

Busy Flag

AOl -A 13l

AOR-AI3R

Address

I/O OR -I/0 7R

Data Input/Output

I/OOl -I/Orl
Vee

Power

GND

Ground

NOTES:
1. Both Vee pins need to be connected to the 5V supply and both GND pins need to be grounded for
proper operation.
2. On 8Kx 81DT7M134 option, A13l and A13R need to be externally connected to ground for proper
operation.
3. IDT7M134/135 (MASTER): i3OS'Y is open drain output and requires pull up resistor. IDT7M144/145
(SLAVE): BO'SY is input.
4. For module dimensions, please refer to module drawing M7 in the packaging section.

DIP
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
Dse-7025/-

1987 Integrated Device Technology. Inc.

5-91

FIFO Memories

FIFO MEMORIES
Integration of IDT's high-speed static RAM tech~ology with
internal support logic yields high-performance, high-density FIFO
memories. A FIFO is used as a memory buffer between two
asynchronous systems with simultaneous read/write access. The
data rate between the two systems can be regulated by monitoring
the status flags and throttling the read and write accesses. Since
these FIFOs are built with an internal RAM pointer architecture,
there is no fall-through time between a write to a memory location
and a read from that memory location. System performance is
significantly improved over the shift register-based architecture of
previous FIFO designs which are handicapped with long
fall-through times.
IDT offers the widest selection of monolithic FIFOs, ranging
from shallow 64 x 4 and 64 x 5 to the high-density 4K x 9. Shallow
FIFOs regulate data flow in tightly coupled computational engines.
High density FIFOs store large data blocks in networking, telecommunication and data storage systems. The ID17200 FIFO family
(256 x 9 through the 4K x 9 FIFOs) are all pin and function

compatible, making density upgrades simple. AIiIDT FIFOs can
be cascaded to greater word depths and expanded to greater word
widths with no external support logic.
A variety of packages are available: standard plastic DIP and
CERDIP, surface mount ceramic LCC, PLCC and SOIC and highreliability Flatpack. Increasing board density is the overwhelming
goal of the IDT's package development efforts, as demonstrated
by the introduction of the 300 mil THINDIP.
The Parallel-Serial FIFO incorporates a serial input and a serial
output shifter for serial-to-parallel bus interface. The Parallel-Serial
FIFO also offers six status flags for flexible data throttling.
FIFO modules, composed of four LCC devices mounted on a
multi-layer co-fired ceramic substrate, increase densities to
16K x 9 which are pin-compatible with current monol ithic versions.
IDT is committed to offering FIFOs of increasing density and
speed and enhanced architectural innovations, such as Flexishift
and the BiFIFO, for easier system interface.

TABLE OF CONTENTS
PAGE

CONTENTS
FIFO Memories
IDT7200
IDT7201A
IDT7202A
IDT72021
IDT7203
IDT7204
IDT72041
IDT7205
IDT72103
IDT72104
IDT72401
IDT72402
IDT72403
IDT72404
IDT72413
IDT7252
IDT7M203
IDT7M204
IDT7M205
IDT7M206

256 x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
512 x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1K x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) .......................................
1K x 9 FIFO (with Output Enable and Flag) . . . . .• . .. •• . . . . . . . ... . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2K x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) •......................................
4K x 9 FIFO (14-1, 14-193, 14-251, 14-254, 14-257) .......................................
4K x 9 FIFO (with Output Enable and Flag) . . . . . •. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8K x 9 FIFO .........................................................................
2K x 9 Parallel-Serial FIFO (14-146) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . ..
4K x 9 Parallel-Serial FIFO (14-146) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
64 x 4 FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64 x 5 FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
64 x 4 FIFO with Output Enable .........................................................
64 x 5 FIFO with Output Enable .........................................................
64 x 5 FIFO (with Flags) ...............................................................
BiFIFO .............................................................................
2K x 9 FIFO .........................................................................
4K x 9 FIFO .........................................................................
8K x 9 FIFO (14-1, 14-254, 14-257) ...............•......................................
16K x 9 FIFO (14-1, 14-254, 14-257). .. ... . . .... ........ ... .... . . . . .. ...... ......... .. . ..

6-1
6-1
6-14
6-27
6-28
6-28
6-41
6-42
6-43
6-43
6-69
6-69
6-69
6-69
6-80
6-91
13-146
13-146
13-157
13-157

-----_ ... _--_ .._.__. _ - - - - - - - - - - - - - - - - - - - - - -

FEATURES:

DESCRIPTION:

• First-In/First-Out dual-port memory

The IDT7200/7201A are dual-port memories that utilize a special First-In/First-Out algorithm that loads and empties data on a
first-in/first-out basis_ The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for
unlimited expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of
ring pointers, with no address information required to load and unload data_ Data is toggled in and out ofthe devices through the use
of the Write
and Read (R) pins. The devices have a read/write
cycle time of 35ns (28.5MHz).
The devices utilize a 9-bit wide data array to allow for control and
parity bits at the user's option. This feature is especially useful in
data communications applications where it is necessary to use a
parity bit for transmission/reception error checking. It also features
a Retransmit (RT) capabili~that allows for reset of the read pointer
to its initial position when RT is pulsed low to allow for retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
The IDT7200/1 A are fabricated using IDT's high-speed CEMOS
technology. They are designed for those applications requiring
asynchronous and simultaneous read/writes in multiprocessing
and rate buffer applications.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

• 256 X 9 organization (IDT7200)
• 512 x 9 organization (IDT7201A)
• Low power consumption
• Ultra high speed-35ns cycle time (28.5MHz)
• Asynchronous and simultaneous read and write

rN)

• Fully expandable by both word depth and/or bit width
• IDT7200 and IDT7201 A are pin and functionally compatible with
Mostek MK4501, but with Half-Full Flag capability in single
device mode
• Master/Slave multiprocessing applications
• Bidirectional and rate buffer applications
• Empty and Full warning flags
• Auto retransmit capability
• High-performance CEMOS ™ technology
• Available in plastic DIP, CERDIP, 300 mil sidebraze THINDIP,
LCC, PLCC and Flatpack
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87531 is pending listing on
this function. Refer to Section 2/page 2-4.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DATA INPUTS
(Do-Ds)

w

Vcc
D4
D5
D6
D7

Ds
D3
D2
Dl
Do

IT/FIT
AS
EF

Xl
ff
00
01

XO/RF

07
06
05

O2
03

Q4

as
GND

R
DIP
TOP VIEW

oo~~ :?oo

INDEX
I

L..I;;

IIIII

L..IL...I

II

I'll

II

L...I

L...I

L...I

w

4 3 2 ..... 3231 30
1
29 I: D6
D2 :I 5
2S I: D7
Dl :J 6
27 I: NC
Do :J 7
26 I: IT/FIT
Xl :I S
J32-1
25 I: AS
&
i=F" :J 9
L32-1
24 I: EF
0 0 :J 10
Q
23 I: xo/RF
l :J 11
22 I: 0 7
NC :J 12
21 I: 0 6
13
O2 :I
14 15 16 17 IS 19 20

nnnnnnn

oo@~~oo

~~~fr
•
BUFFERS
...(>
DATA OUTPUTS
(Oo-Os)

(!)

LCC/PLCC
TOP VIEW

t----t---u

~~~----,---i=F"

I------~

CEMOS is a trademark of Integrated Device Technology, II1\?

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1987

© 1987 Integrated Device Technology. Inc.

OSC-2000/-

6-1

[II
I

IDT7200/7201A CMOS PARALLEL
FIRST·IN/FIRST·OUT FIFO 256 X 9·BIT & 512

ABSOLUTE MAXIMUM RATINGS

9·BIT

X

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED DC OPERATING CONDITIONS

(1)

RATING

COMMERCIAL

MILITARY

VTERM

Terminal Voltage
with Respect to
GND

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

Storage
Temperature

-55 to +125

SYMBOL

TSTG

DC Output Current

lOUT

-65 to + 135
-65 to +155

50

50

UNIT

MIN.

TYP.

MAX.

UNIT

Vee

Military
Supply Voltage

4.5

5.0

5.5

V

Vee

Commercial
Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

"'H

Input High
Voltage Commercial

2.0

-

-

V

"'H

Input High
Voltage Military

2.2

-

-

V

Input Low
Voltage
Commercial
and Military

-

-

0.8

V

PARAMETER

SYMBOL

°C
°C
mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

V.

(1)

IL

NOTE:
1. 1.5V undershoots are allowed for 10ns onee per cycle.

DC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5.0V ±10%, TA

SYMBOL

= O°Cto

PARAMETER

+70°C; Military: \be

= 5V ± 10%, TA =

1DT7200S/L
IDT7201 SA/LA
COMMERCIAL
tA
25,35ns

1DT7200S/L
1DT7201 SA/LA
MILITARY
tA
30,40ns

=

MIN. TYP.
IU(l)

Input Leakage Current
(Any Input)

ILo (2)

MAX.

=

MIN.

TYP.

MAX.

-55°C to +125°C)
1DT7200S/L
I DT7201 SA/LA
COMMERCIAL
tA
50,65,
80,120ns

=

MIN.

TYP.

MAX.

1DT7200S/L
1DT7201 SA/LA
MILITARY
tA
50,65,
80,120ns

=

MIN. TYP.

UNIT

MAX.

-1

-

1

-10

-

10

-1

-

1

-10

-

10

~A

Output Leakage Current

-10

-

10

-10

-

10

-10

-

10

-10

-

10

~A

VOH

Output Logic "1" Voltage
IOH = -2m A

2.4

-

-

2.4

-

-

2.4

-

-

2.4

-

-

V

VOL

Output Logic ·0" Voltage
10L = 8mA

-

-

0.4

-

-

0.4

-

-

0.4

-

-

0.4

V

Active Power Supply Current

-

-

125

-

-

140

-

50

80

-

70

100

mA

(3)

A"yerage Sta...!J9by £u~nt
(R = W = RS = FURT = \'JH

-

-

15

-

-

20

-

5

8

-

8

15

mA

(L)(3)

Power Down Current
(All Input = Vcc -0.2V)

-

-

500

-

-

900

-

-

500

-

-

900

~A

S)(3)

Power Down Current
(All Input = Vee -0.2V)

-

-

5

-

-

9

-

-

5

-

-

9

mA

lec1(3)
ICC2
I
I

CC3
c

d

NOTES:
1. Measurements with 0.4~ VIN~VCC .
2.
\'JH, 0.4 ~ VOUT~ Vec
3. Icc measurements are made with outputs open.

R;::

6-2

IDT7200/7201A CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 256 x 9-BIT & 512 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

-

(Commercial: Vcc = 5V +10%,
TA =O°Cto +70°C; Military: Vcc = 5V +10%, TA = -55°C to + 125°C)
COM'L.
SYMBOL

PARAMETER

7200x25
7201x25

MIL.
7200x30
7201x30

COM'L

MIL.

7200x35
7201x35

7200x40
7201x40

MILITARY AND COMMERCIAL
7200x50
7201xSO

7200x65
7201x6S

7201x80

7201x120 UNIT

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

fs

Shift Frequency

-

28.5

-

25

-

22.2

-

20

-

15

-

12.5

-

10

-

7

MHz

t RC

Read Cycle Time

35

-

40

-

45

-

50

-

65

-

80

-

100

-

140

-

ns

tA

Access Time

-

25

-

30

-

35

-

40

-

50

-

65

-

80

-

120

ns

tRR

Read Recovery Time

10

-

10

10

-

15

-

20

-

ns

-

30

35

40

50

-

65

-

80

-

20

25

-

15

Read Pulse Width (2)

-

10

t RPW

-

120

-

ns

tRLZ

Read Pulse Low to Data Bus
at LowZ(3)

5

-

5

-

5

-

10

-

10

-

10

-

10

-

ns

1>5>,

-

10

-

10

-

15

-

15

-

20

-

20

-

ns

5

-

5

-

5

-

5

-

5

-

5

-

5

-

ns

'<::..

,..
':., ....

5
.... <

tWLZ

Write Pulse Low to Data Bus
at Low Z (3. 4)

5

tDV

Data Valid from Read Pulse High

5

---

tRHZ

Read Pulse High to Data Bus
at High Z(3)

-

J~"

twc

Write Cycle Time

35

-

t wpw

Write Pulse Width (2)

25

-

tWR

Write Recovery Time

10

-

t DS

Data Set-up Time

15

:18

tOH

Data Hold Time

0

-

t Rsc

Reset Cycle Time

35

tRS

Reset Pulse Width (2) i

25

tRSS

Reset Set-up Time

tRS R

li __ r

20

-

20

-

25

-

30

-

30

-

30

-

35

ns

40

-

45

50

100

-

140

-

ns

-

35

40

50

65

-

80

-

120

-

ns

-

10

-

10

15

-

20

-

ns

20

-

30

30

-

40

40

-

ns

0

-

5

10

10

10

50

-

65

100

-

140

40

-

50

65

80

120

-

ns

45

-

-

20

18

50

-

80

. 10

-

65

30

-

65

-

80

120

-

ns

15

-

15

20

20

80

100

140

-

ns

65

-

65

-

80

120

-

ns

120

-

ns

20

40
··' •••·30«

-

35

25

A
-

-

30

-

35

Reset Recovery Time

10

-:-:

10

-

10

-

tRTC

Retransmit Cycle Time

35

-

1>40

45

-

50

tRT

Retransmit Pulse Width (2)

25

-

30

-

35

40

0

....

0

40
10

15

65

-

80

15

-

20

65

-

80

-

100

-

140

ns

65

-

80

-

100

-

140

ns

45

-

60

ns

60

60

-

60

-

-

60

45

60

ns

tRTS

Retransmit Set-up Time

25

30

40

-

50

Retransmit Recovery Time

10

10

-

35

tRTR

-

-

10

-

10

-

15

tEFL

Reset to Empty Flag Low

-

35

-

40

-

45

-

50

-

t HFH ,
tFFH

Reset to Half-Full
and Full Flag High

-

35

..

,'..

ns

-

-

50

80

ns

ns

ns

40

-

45

-

50

25

:<··'·_·"30

-

30

-

30

25

':::) 30

-

30

-

35

-

30.:
,•..• '·,.;:,·,·········30

35

-

40

-

50

-

65

-

80

-

120

-

ns

30

35

45

-

60

-

60

-

60

ns

30

-

45

60

-

60

60

ns

'+) 40

-

45

-

80

100

140

ns

tREF

Read Low to Empty Flag Low

tRFF

Read High to Full Flag High

-

tRPE

Read Pulse Width After EF High

25

-

tWEF

Write High to Empty Flag High

25

tWFF

Write Low to Full Flag Low

tWHF

Write Low to Half-Full Flag Low

Ii···········,,·,

tRHF

Read High to Half-Full Flag High

-

35

-

40

-

45

-

50

-

65

-

80

-

100

-

140

ns

t WPF

Write Pulse Width after FF High

25

-

30

-

35

-

40

-

50

-

65

-

80

-

120

-

ns

t XOL

Read/Write to

25

-

30

-

50

-

65

-

120

ns

-

30

40

-

50

-

65

-

80

25

-

40

Read/Write to XO High

-

35

tXOH

-

80

-

120

ns

tXI

XI Pulse Width

25

-

30

-

35

40

-

80

-

120

10

-

10

-

10

-

65

XI Recovery Time

-

50

tXIR

-

10

-

10

-

10

-

ns

15

-

15

-

15

-

ns

XO Low

25
35

t XIS
Xi Set-up Time
15
NOTES,
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5. ·x· in part rating indicates power rating (S/SA or ULA).

-

15

15

6-3

30

35

10
15

35
50

10
15

65

ns

IDT7200/7201A CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 256 X 9-BIT & 512 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

5V
GNDto 3.0V
5ns
1.5V
1.5V
See Figure 1

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

CAPACITANCE
CIN

30pF*

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

SYMBOL

1.1K
TO
OUTPUT
PIN
68 Low

25

30

35

40

50

65

80

120

ns

Read/Write to }ID High

25

30

35

40

50

65

80

120

ns

XI Pulse Width

25

30

35

40

50

65

80

120

ns

tXlR

XI Recovery Time

10

10

10

10

10

10

10

10

ns

t XIS

~ Set-up Time

15

15

15

15

15

15

15

15

ns

NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allOWed.
3. Values guaranteed by design. not currently tested.
4. Only applies to read data flow-through mode.
5. ·x· in part rating indicates power rating (SA or LA).

6-16

------ .--------------------------------------------------------------------------------------IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

5V

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

CAPACITANCE

1.1K
TO
OUTPUT
PIN

C1N

Input Capacitance

COUT

Output Capacitance

CONDITIONS

MAX.

30pF*

UNIT

V1N = OV

8

pF

OV

8

pF

VOUT=

Figure 1. Output Load

*Includes jig and scope capacitances.

NOTE:
1. This parameter is sampled and not 100% tested.

pointer is blocked from R so extemal changes in
the FIFO when it is empty.

SIGNAL DESCRIPTIONS
INPUTS

R will not affect

FIRST LOAD/RETRANSMIT (FLIRT)

DATA IN (Do-De)

This is a dual-purpose input. In the Depth Expansion Mode, this
pin is grounded to indicate that it is the first loaded (see Operating
Modes). In the Single Device Mode, this pin acts as the retransmit
input. The Single Device Mode is initiated by grounding the Expansion In (XI).
The IDT7202A can be made to retransmit data when the
Retransmit Enable Control (RT) input is pulsed low. A retransmit
operation will set the intemal read pointer to tDe first location and
will not affect the write pointer. Read Enable (R) and Write Enable
(li) must be in the high state during retransmit. This feature is useful when less than 1024 writes are performed between resets. The
retransmit feature is not compatible with the Depth Expansion
Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers.
EXPANSION IN (XI)

Data inputs for 9-bit wide data.

CONTROLS
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken
to a low state. During reset, both intemal read and write pointers are
set to the first location. A reset is required after power up before a
write operation can take place. Both the Read Enable (R) and
Write Enable fil) Inputs must be In the high state during the
window shown In Figure 2, (I.e., tRSS before the rising edge of
RS) and should not change until tRSR after the rising edS!. of
RS. Half-Full Flag (HF) will be reset to high after Reset (RS).
WRITE ENABLE

68m

(TA= +25°C. f = 1.0MHz)

PARAMETER(1)

SYMBOL

GND to 3.0V
5ns
1.5V
1.5V
See Figure 1

rN)

This input is a dual-purpose pin. Expansion In (XI) is grounded
to indicate an operation in the single device mode. Expansion In
(XI) is connected to Expansion Out (XO) of the previous device in
the Depth Expansion or Daisy Chain Mode.

A write cycle is initiated on the falling edge of this input if the Full
Flag (FF) is not set. Data set-up and hold times must be adhered to
with respect to the rising edge of the Write Enable (li). Data is
stored in the RAM array sequentially and independently of any ongoing read operation.
After half of the memory is filled and atthe falling edge ofthe next
write operation, the Half-Full Flag (HF) will be set to low and will
remain set until the difference between the write pointer and read
pointer is less than or equal to one half of the total memory of the
device. The Half-Full Flag (HF) is then reset by the rising edge of
the read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. Upon the completion of a valid read
operation, the Full Flag (FF) will go highaftertRFF, allowing a valid
write to begin. When the FIFO is full, the intemal write pointer is
blocked from W, so extemal changes in Wwill not affect the FIFO
when it is full.

OUTPUTS
FULL FLAG (FF)
The Full Flag (FF) will go low, inhibiting further write operation,
when the write pointer is one location from the read pointer, indicati~thatthe device is full. Ifthe read pointer is not moved after Reset
(RS), the Full-flag (FF) will go low after 1024 writes.
EMPTY FLAG (EF)
The Empty Flag (EF) will go low, inhibiting further read operations, when the read pointer is one location from the write pointer,
indicating that the device is empty. If the write pointer is not moved
after Reset (RS), the Empty Flag (EF) will go low after 1024 reads.

READ ENABLE (R)

EXPANSION OUT/HALF-FULL FLAG (XO/HF)

A read cycle is initiated on the falling edge of the Read Enable
(R) provided the Empty Flag (EF) is not set. The data is accessed
on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes high, the Data Outputs
(00-08) ,will retum to a high impedance condition until the next
Read operation. When all the data has been read from the FIFO, the
Empty Flag (EF) will go low, allowing the "final" read cycle but inhibiting further read operations with the data outputs remaining in a
high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go high after tWEF and a valid
Read can then begin. When the FIFO is empty, the intemal read

This is a dual-purpose output. In the single device mode, when
ExpanSion In (XI) is grounded, this output acts as an indication of a
half-full memory.
After half ofthe memory is filled and atthe falling edge of the next
write operation, the Half-Full Flag (HF) will be set to low and will
remain set until the difference between the write pointer and read
pointer is less than or equal to one half of the total memory of the
device. The Half-Full Flag (HF) is thEm reset by the rising edge of
the read operation.
In the Depth E!Q.ansion Mode, Expansion In (XI) is connected to
Expansion Out (XO) of the previous device. This output acts as a

6-17

[II
I

IDT7202SAlLA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

signal to the next device in the Daisy Chain by providing a pulse to
the next device when the previous device reaches the last location
ofmemo~.
.

DATA OUTPUTS (00 -Oa)

Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a high state.

~-------------------------tRSC --------------------------~

w

NOTES:
1. EF, FF and 'RF may change status during Reset, but flags will be valid at t RSC'
2. Wand R= V1H around the rising edge of RS.
Figure 2. Reset

6-18

- - - ' .. _ - - - - - - - - - - - - - - - - - - - - - - -

1DT7202SAlLA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1..~-----tRC

- - - - - I - . j - t RPW

___... , _ tA

-tDv-1
DATA OUT VALID

tRHZ

'}(!ll;j(

DATA OUT VALID

~

'/l)-----

I~-------twc-------------~
I~---- t wpw ---~

w

r,t
---------c(

DS

-----C(

-D-A-T-A-1N-----,. ....

DATAIN VALID

)>----

Figure 3. Asynchronous Write and Read Operation

LAST WRITE

IGNORED
WRITE

FIRST READ

ADDITIONAL
READS

FIRST WRITE

w

Figure 4. Full Flag From Last Write to First Read

LAST READ

IGNORED
READ

FIRST WRITE

ADDITIONAL
WRITES

FIRST READ

w

DATAOUT----r-t-_1~~~~~~--t------------_r------_t---1~~~~~

Figure 5. Empty Flag From Last Read to First Write

6-19

IDT7202SA/LA CMOS PARALLEL
FIRST·IN/FIRST·OUT FIFO 1024 X 9·81T

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1~-------------------------tRTC --------------------------~

tRT

---------------------+1 r-----+----

W. tt

FLAG VALID
NOTES:

1.

EF. FF and HF may change status during Retransmit. but flags will be valid at t RTC '
Figure 6. Retransmit

W

Figure 7. Empty Flag Timing

W

Figure 8. Full Flag Timing

6-20

IDT7202SAlLA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

HALF-FULL OR LESS

MORE THAN
HALF-FULL

HALF-FULL OR LESS

w

Figure 9. Half-Full Flag Timing

w

WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION

Figure 10. expansion Out

14----- tXl

w

---+----tXlR--~

WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION

Figure 11. expansion In

6-21

1DT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

grounded (see Figure 12). In this mode the Half-Full Flag 1!:!f),
which is an active low output, is shared with Expansion Out (XO).

OPERATING MODES
SINGLE DEVICE MODE
A single IDT7202A may be used when the application requirements are for 1024 words or less. The IDT7202A is in a Single Device Configuration when the Expansion In (XI) control input is

HF"

(HALF-FULL FLAG)
WRITE

IDT
7202A
FULL FLAG

(~)

RESET

(liS)

EXPANSION IN

(U) EMPTY FLAG
(RT) RETRANSMIT

(Xl)

Figure 12. Block Diagram of Single 1024 x 9 FIFO

WIDTH EXPANSION MODE

(EF ,FF and HF ) can be detected from anyone device. Figure 13
demonstrates an 18-bit word width by using two IDT7202As. Any
word width can be attained by adding additional IDT7202s.

Word width may be increased simply by connecting the corresponding Input control Signals of multiple devices. Status flags

(R) READ
IDT
7202A
RESET -------~I­

(tt) EMPTY FLAG
(tIT) RETRANSMIT

(liS)

(0) DATAouT

NOTE:
1. Flag detection is accomplished by monitoring the
connect any output control Signals together.

FF. EF and the HF signals on either (any) device used in the width expansion configuration. Do not

Figure 13. Block Diagram of 1024 x 18 FIFO Memory Used in Width Expansion Mode

6.,.22

1DT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

system (Le., FF is monitored on lhe device where W is used; EF is
monitored on the device where R is used). Both Depth Expansion
and Width Expansion may be used in this mode.

DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT7202A can easily be adapted to applications where the
requirements are for greater than 1024 words. Figure 14 demonstrates Depth Expansion using three IDT7202As. Any depth can be
attained by adding additionaIIDT7202As. The IDT7202As operate
in the Depth Expansion configuration when the following conditions are met:
1. The first device must be designed by grounding the First Load
(FL.) control input.

DATA FLOW-THROUGH MODES
Two types of flow-through modes are permitted: a read flowthrough and write flow-through mode. For the read flow-through
mode (Figure 17), the FIFO permits the reading of a single word
after writing one word of data into an empty FIFO. The data is enabled on the bus in (twEF + tNns after the rising edge of W, called
the first write edge, and it remains on the bus until the R line is
raised from low-to-high, after which the bus would go into a threestate mode after tRHZ ns. The EF line would have a pulse showing
temporary de-assertion and then would be asserted. In the interval
of time that R is low, more words can be written to the FIFO (the
subsequent writes after the first write edge will de-assert the Empty
Flag); however, the same word (written on the first write edge) presented to the output bus as the read pointer, would not be incremented when R was low. On toggling R, the other words that are
written to the FI FO will appear on the output bus as in the read cycle
timings.
In the write flow-through mode (Figure 18), the FI FO permits the
writing of a single word of da.!,a immediately after reading one word
of data from a full FIFO. The R line causes the FF to be de-asserted
but the W line, being low, causes it to be asserte.s!.again in anticipation of a new data word. On the rising edge of W, the new word is
loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write
pointer.
For additional information refer to Tech Note 8: "Operating
FIFOs on Full and Empty Boundary Conditions" and Tech Note 6:
"Designing with FIFOs".

2. All other devices must have FI. in the high state.
3. The Expansion Out (XO) pin of each device must be tied to the
Expansion In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Fgg (FF)
and Empty Flag (EF). This requires the ORing of all EFs and
ORing of all FFs (Le. all must be set to generate the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not
available in the Depth Expansion Mode.
For additional information refer to Tech Note 9: "Cascading
FIFOs or FIFO Modules".
COMPOUND EXPANSION MODE
The two expansion techniques described above can be applied
together in a straightforward manner to achieve large FIFO arrays
(see Figure 15).
BIDIRECTIONAL MODE
Applications which require data buffering between two systems
(each system capable of Read and Write operations) can be
achieved by pairing IDT7202As as shown in Figure 16. Care must
be taken to assure that the appropriate flag is monitored by each

TABLE I-RESET AND RETRANSMITSINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
OUTPUTS

INTERNAL STATUS

INPUTS

MODE
RS

RT

Xi

Read POinter

Write Pointer

EF

FF

Reset

0

X

0

Location Zero

Location Zero

0

1

1

Retransmit

1

0

0

Location Zero

Unchanged

X

X

X

Read/Write

1

1

0

Increment(1)

Increment(1)

X

X

X

HF

NOTES:
1. Pointer will increment if flag is high.

TABLE II-RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
INPUTS

MODE

INTERNAL STATUS

OUTPUTS

RS

FL

XI

Read Pointer

Write Pointer

EF

FF

Reset First Device

0

0

(1)

Location Zero

Location Zero

Reset All Other Devices

0

1

(1)

Location Zero

Location Zero

0
0

1
1

Read/Write

1

X

(1)

X

X

X

X

NOTES:
1. Xi is connected to
= Reset Input

As

XC of previous device. See Figure 14.

FURT = First Load/Retransmit. EF = Empty Flag Output. FF = Full Flag Output. Xi = Expansion Input. HF =

6-23

Half-Full Flag Output.

I

I

filii
•

I
I

IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT

w
0

9.
I

.
rorr

MILITARY AND COMMERCIAL TEMPERATURE RANGES

lw

,,

l=J=
9 ...
lOT
I 1 7202A
"Ty

r--

I

l=J=

\

91.A

I

lOT
7202A

I:
91.A

I

liS

..L

~

..

9,
I

~

0)

"

I;

"Ty

l=J=

,

~

~

'-

Ii

.

r--

I~

'---

-,

E1=

1-4

r-IT-

..'l

~

I--

~

I--

t-r-

I--

I-

...rr.

lOT
7202A I - t--

1~~

Figure 14. Block Diagram of3072 x 9 FIFO Memory (Depth expansion)

Og -017

0 0 -08

Ii.W.J1S

IDT7202A
DEPTH
EXPANSION
BLOCK

IDT7202A
DEPTH
EXPANSION
BLOCK

• • • _ _ _..,

•••

Do -08

•••
NOTES:

1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO expansion

6-24

IDT7202A
DEPTH
EXPANSION
BLOCK

Vee

IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

WA

RB
E"FB

~A

,

IDT

RFB

7202A

tt
DA

0-6

OB

I
V-

0-6

SYSTEM B

SYSTEM A

Ii

0A

I(

0-6

IDT
7202A

RA

DB

0-6

'i
WB

HFA
~B

EFA

Figure 16. Bidirectional FIFO Mode

W

DATA OUT

Figure 17. Read Data Flow-Through Mode

6-25

IDT7202SA/LA CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 1024 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

w

DATA IN
VALID

DATA OUT

I-tDs-1

~J
- - - - - - - - < w \ D A T A O U T VALID

)@~--------

Figure 18. Write Data Flow-Through Mode

ORDERING INFORMATION

IDT

XXXX
Device Type

999
Speed

A

A

Package

Process/
Temperature
Range

y:,aok
P
D
TC

'----------11 J

L
F

'--________________

~

25
30
35
40

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

Plastic Dip
CERDIP
Sidebraze THINDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
Flatpack

Commercial Only
Military Only
Commercial Only
Military Only

Access Time (tA )
Speed in Nanoseconds

50

65

}

80
120

'---________________________

~I

SA

ILA
L -______________________________________

~

Standard Power
Low Power

7202
1024 x 9-Bit FIFO

6-26

------.

-------------------------------------------------------------------------------------------------

FEATURES:

DESCRIPTION:

• First-In/First-Out (FIFO) dual-port memory

The ID172021 is a dual-port memory that utilizes a special FirstIn/First-Out algorithm that loads and empties data on a first-in/firstout basis. The device has Full, Empty, Half-Full and AlmostEmpty/Full flags to prevent data overflow or underflow. Expansion
logic allows wider and/or deeper FIFOs to be created using multiple devices without external logiC.
The reads and writes are internally sequential through the use
of ring pointers, with no address information required to load and
unload data. Data is toggled in and out of the device through the
use of Write (W) and Read (R) pins. The device has a read/write
access time of 25ns and a read/write cycle time of 35ns (28.5MHz).
The ID172021 can perform asynchronous and simultaneous read
and write operations.
The ID172021 utilizes a 9-bit wide dual-port RAM array to allow
for zero fall-through time and to allow the user. to store tag or parity
bits. This 9-bit feature is useful in data communications applications where transmiSSion/reception error checking is necessary. It
also features a Retransmit ( RT) capability that allows for reset of
the read pOinter to its initial pOSition, when RT is pulsed low, to allow for retransmission of data from the beginning. Four status flags
prevent the overflow or underflow of the FIFO and permit interrupt
signals to be sent to the transmitting data source.
The ID172021 is fabricated using IDT's high-performance
CEMOS ™ technology, which combines high speed and low
power consumption. Military grade product is manufactured· in
compliance with the latest revision of MIL-STD-883, Class 8, for
high reliability systems.

• 1Kx9-bit organization
• Ultra-high-speed: 25ns access time, 35ns cycle time (28.5MHz)
• Fully expandable in word depth and/or width
• Asynchronous and simultaneous read and write
• Functionally equivalent to tl:1e ID17202 but with Output Enable
and Almost-Empty/Full Flag
• Four status flags: Full, Empty, Half-Full (single device mode)
and Almost-Empty/Full (1/8 or 7/8) signal on 0, 128,512,896
and 1024-byte boundaries
• Output Enable controls the data output port
• Auto-retransmit capability·
• Master/Slave muitiprocesssing applications
• Video frame buffer or laser printer buffer applications
• Available in 32-pin DIP and surface mount 32-pin LCC and
PLCC
• Military product compliant to MIL-STD-883, Class 8

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DATA INPUTS
(D o-D 8 )

:J 5
:J 6
:J 7
:J 8

:J

9

:I 10

~ ~ ~ L1i ;2~ ~
J32-1

L3~-1

:J 11
:I 12

:J

DIP
TOP VIEW

13 14 15 16 17 18 19 20

29 [
28 I:

D6
D7

27 I:
26 [

FIlm'
liS

25
24
23
22
21

I: OE"
I: ~
I: RO"/HF
I: Or
I: 0 6

oo~~ltJ:ao

R"

CHJ

LCC/PLCC
PINOUT

1-----.

RT-----.IL..-_ _ _....
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

~

DECEMBER 1987
DSC-2003/-

6-27

FEATURES:

DESCRIPTION:

• First-In/First-Out dual-port memory

The IDT7203/7204 are dual-port memories that utilize a special
First-In/First-Out algorithm that loads and empties data on a firstin/first-out basis. The device uses Full and Empty flags to prevent
data overflow and underflow and expansion logic to allow for unlimited expansion capability In both word size and depth.
The reads and writes are internally sequential through the use of
ring pointers, with no address Information required to load and unload data. Data Is toggled in and out of the device through the use
of tl;1e Write fN) and Read (R) pins. The device has a read/write cycle time of 45ns (22.2MHz).
The device utilizes a 9-bit wide data array to allow for control and
parity bits at the user's option. This feature is especially useful in
data communications applications where it is necessary to use a
parity bit for transmission/reception error checking. It also features
a Retransmit (RT) capabil!!Yjhat allows for reset of the read pointer
to its initial position when RT is pulsed low to allow for retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
The IDT7203/7204 is fabricated using lOT's high-speed
CEMOS technology. They are designed for those applications
requiring asynchronous and simultaneous read/writes in
multiprocessing and rate buffer applications. The 4096 x 9 organization for the IDT7204 allows a 4096 deep word structure without
the need for expansion.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

• 2048 x 9 organization (IDT7203)
• 4096 x 9 organization (IDT7204)
• Low power consumption
- Active: 660mW (max.)
- Power down: 66mW (max.)
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Pin and functionally compatible with IDT7201A/7202A
• IDT7204 allows 4096 word structure without expansion
• Half-Full Flag capability in single device mode
• Master/Slave multiprocessing applications
• Bidirectional and rate buffer applications
• Empty and full waming flags
• Auto retransmit capability
• High-performance CEMOS 1M technology
• Available in CERDIP, Plastic DIP, PLCC and LCC
• Military product compliant to MIL-STD-883, Class B

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM

w

Vcc

08
03

04
05

INDEX

02

06

01

07

02
01

:J 5
:16

Do

FI711r
RS

Do

:17

xr

~

l=F'
00

>«:57HF

(;,1

07
06
05
04

O2

03
08

~

GND
DIP
TOP VIEW

xr

0' 0'8: ~ ::? 0'" C'

:18
l=F' :19
0 0 :J 10
0 1 :I 11
NC :112
O2 :J 13

WWWIIUUU
4 3 2 u 323130
1
29£:
28 [
27 [
26[
J32-1
25 £:
&
L32-1
24 £:
23 [:
22 £:
21 £:
14 15 16 17 18 19 20

nnr:nnnr.

O'cf~~la:oo'"
C!J

PLCC/LCC
TOP VIEW

_---'t----. >«:57HF

.......
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology, Inc.

DECEMBER 1987
OSC-2OO4/-

6-28

IDTI203/IDTI204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL

MILITARY

UNIT

SYMBOL

-0.5 to +7.0

-0.5 to +7.0

V

VCCM

Oto +70

-55 to + 125

°C

TSIAS

Temperature
Under Bias

-55 to +125

TSTG

Storage
Temperature

-55 to + 125

-65 to +155

°C

lOUT

DC Output Current

50

50

mA

-65 to +135

°C

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

PARAMETER

MIN.

TYP.

MAX.

UNIT

Military Supply
Voltage

4.5

5.0

5.5

V

Vccc

Commercial
Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage
Commercial

2.0

-

-

V

VIH

Input High Voltage
Military

2.2

-

-

V

VIL (l)

Input Low Voltage
Commercial &
Military

-

-

O.S

V

NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS
(Commercial: Vee= 5V ± 10%. TA = O°C to + 70°C; Military: Vcc = 5V ± 10%. TA

SYMBOL

PARAMETER

= -55°C to

+ 125°C)

IDTI203S/L
IDT7204S/L
COMMERCIAL
tA
50, 65, SO, 120n5
TYP.
MAX.
MIN.

=

tA
MIN.

=

IDT7203S/L
IDT7204S/L
MILITARY
50,65,80,120n5
TYP.
MAX.

UNIT

-

V

-

-

0.4

V

120

-

100

150

mA

S

12

-

12

25

mA

-

-

2

-

-

4

mA

-

-

S

-

-

12

mA

IIL(l)

Input Leakage Current (Any Input)

-1

-

1

-10

IOL(2)

Output Leakage Current

-10

-

10

-10

VOH

Output Logic "1" Voltage lOUT = -2mA

2.4

-

-

2.4

VOL

Output Logic ·0" Voltage lOUT = SmA

-

0.4

ICC1 (3)

Average Vcc Power Supply Current

-

75

ICC2 (3)

Average Standby Current
(if = W = RST = FlJRT = VIH)

-

ICC3 (L)(3)

Power Down Current
(All Input = Vcc -0.2V)

ICC3 (S)(3)

Power Down Current
(All Input = Vcc -0.2V)

NOTES:
1. Measurements with 0.4 ::;; VIN ::;; VOUT'
2. R?: V IH • 0.4 ::;; VOUT ::;; Vcc.
3. Icc measurements are made with outputs open.

6-29

10

J.LA

10

J.LA

IDT7203/1DT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 X 9-BIT

AC ELECTRICAL CHARACTERISTICS (1)
(Commercial: Vcc= 5V ± 10%. TA = O°C to + 70°C; Military: Vcc =
SYMBOL

PARAMETER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

± 10%. TA = -55°C to + 125°C)

5V

7203S/L50
7204S/L50
MAX.
MIN.

7203S/L65
7204S/L65
MAX.
MIN.

7203S/L80
7204S/L80
MIN.
MAX.

7203S/L120
7204S/L120
MIN.
MAX.

UNIT

f5

Shift Frequency

-

15

-

12.5

-

10

-

7

MHz

t RC

Read Cycle Time

65

-

80

-

100

-

140

-

ns

tA

Access Time

-

50

-

65

-

80

-

120

ns

tRR

Read Recovery Time

15

15

-

20

-

20

Read Pulse Width (2)

50

65

-

80

-

120

tRLZ

Read Pulse Low to Data Bus at
Low Z(3)

10

-

10

-

10

-

10

-

ns

t RPW

-

ns

tWLZ

Write Pulse Low to Data Bus at
Low Z(3.4)

15

-

15

-

20

-

20

-

ns

tov

Data Valid from Read Pulse High

5

-

5

-

5

-

5

-

ns

tRHZ

Read Pulse High to Data Bus at
High Z(3)

-

30

-

30

twc

Write Cycle Time

65

80

t wpw

Write Pulse Width (2)

50

65

tWR

Write Recovery Time

15

-

tos

Data Set-up Time

30

-

30

tOH

Data Hold Time

5

-

10

15

ns

-

30

-

35

ns

-

100

-

140

-

ns

-

80

-

120

20

-

20

-

ns

40

-

40

-

ns

10

10

-

ns

-

ns

80

-

100

-

140

-

ns

65

-

80

-

120

-

ns

50

-

80

-

120

-

ns

Reset Recovery Time

15

-

15

20

-

20

-

ns

t RTC

Retransmit Cycle Time

65

80

100

-

140

-

ns

tRT

Retransmit Pulse Width (2)

50

65

80

-

120

-

ns

tRTS

Retransmit Set-up Time

50

-

-

65

-

80

120

-

ns

tRTR

Retransmit Recovery Time

15

-

15

-

20

-

20

-

ns

tEFL

Reset to Empty Flag Low

-

65

-

80

-

100

-

140

ns

t HFH. tFFH

Reset to Half-Full and Full
Flag High

-

65

-

80

-

100

-

140

ns

tREF

Read Low to Empty Flag Low

-

45

-

60

-

60

-

60

ns

tRFF

Read High to Full Flag High

-

45

-

60

-

60

-

60

ns

tRPE

Read Pulse Width after EF High

50

-

65

-

80

-

120

-

ns

tWEF

Write High to Empty Flag High

-

45

-

60

60

-

60

ns

tWFF

Write Low to Full Flag Low

-

45

60

60

-

60

ns

tWHF

Write Low to Half-Full Flag Low

-

65

-

100

-

140

ns

t RSC

Reset Cycle Time

65

t RS

Reset Pulse Width (2)

50

tRSS

Reset Set-up Time

t RSR

65

tRHF

Read High to Half-Full Flag Low

-

65

-

80

-

100

-

140

ns

t WPF

Write Pulse Width after FF High

50

-

65

-

80

-

120

-

ns

t xoL

Read/write to XO Low

-

50

-

65

80

ns

Read/Write to XO High

-

50

-

65

-

120

t XOH

-

120

ns

tXI

XI Pulse Width

50

-

65

-

80

120

-

ns

tXIR

XI Recovery Time

10

-

10

-

10

110

-

ns

t XIS

XI Set-up Time

15

-

15

-

15

-

15

-

ns

NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design. not currently tested.
4. Only applies to read dataflow-through mode.

6-30

80

80

- - -.....- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

CAPACITANCE
SYMBOL
CIN (3)

5V

GND to 3.0V
5ns
1.5V
1.5V
See Figure 1

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

D.U.T

(TA= +25°C, f = 1.0MHz)(1)

ITEM

CONDITIONS

Input Capacitance

VIN = OV

COUT (2.3) Output Capacitance
VOUT= OV
NOTES:
1. This parameter is sampled and not 100% tested.
2. With output deselected.
3. Characterized values, not currently tested.

~

6800

1.1K

_ 30pF*

Figure 1. Output Load
MAX.

UNIT

8

pF

12

pF

*Includes jig and scope capacitances.

Empty Flag (EF) will go low, allowing the "final" read cycle but inhibiting further read operations, with the data outputs remaining in
a high impedance state. Onc~valid write operation has been accomplished, the Empty Flag (EF) will go high after tWEF and a valid
Aead can then begin. When the FIFO is empty, the internal read
pointer is blocked from R so external changes will not affect the
FIFO when it is empty.

SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (00- Da)
Data inputs for 9-bit wide data.

CONTROLS:

FIRST LOAD/RETRANSMIT (FLIRT)

RESET (RS)

This is a dual-purpose input. In the Depth ExpanSion Mode, this
pin is grounded to indicate that it is the first device loaded (see
Operating Modes). In the Single Device Mode, this pin acts as the
retransmit input. T~ Single Device Mode is initiated by grounding
the Expansion In (XI).
The IDT7203/7204 can be made to retransmit data when the
Aetransmit Enable Control (AT) input is pulsed low. A retransmit
operation will set the internal read pointer to the first location and
will not affect the write pointer. Aead Enable (R) and Write Enable
(W) must be in the high state during retransmit. This feature is useful when less than 2048/4096 writes are performed between resets.
The retransmit feature is not compatible with the Depth Expansion
Mode and will affect the Half-Full Flag (HF) depending on the relative locations of the read and write pointers.

Aeset is accomplished whenever the Aeset (AS) input is taken to
a low state. During reset, both internal read and write pointers are
set to the first location. A reset is required after power up before a
write operation.Qan take place. Both the Read Enable (R) and
Write Enable (W) Inputs must be in the high state during the
window shown in Figure 2 (i.e. tRSS before the rising edge of
RS) and should nO!.£hange until tRsR after the rising edge of
RS. Half-Full Flag (HF) will be reset to high after master Reset
(RS).
WRITE ENABLE (W)
A write cycle is initiated on the falling edge of this input if the Full
Flag (FF) is not set. Data set-up and hold times must be adhered to
with respect to the rising edge of the Write Enable (W). Data is
stored in the RAM array sequentially and independently of any ongoing read operation.
After half of the memory is filled, and at the falling edge of the
next write operation, the Half-Full Flag (HF) will be set to low and
will remain set until the difference between the write pointer and
read pointer is less than or equal to one half of the total memory of
the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibitil)g
further write operations. Upon the completion of a val id read operation, the Full Flag (FF) will go high aftertRFF, allowing a valid write to
begin. When the FIFO is full, the internal write pointer is blocked
from W, so external changes in Wwill not affect the FIFO when it is
full.

EXPANSION IN

(Xi)

This input is a dual-purpose pin. ExpanSion In (xi) is grounded
to indicate an operation in the single device mode. Expansion In
(XI) is connected to Expansion Out (XO) of the previous device in
the Depth Expansion or Daisy Chain Mode.

OUTPUTS:
FULL FLAG (FF)
The Full Flag (FF) will go low, inhibiting further write operation,
when the write pointer is one location from the read pointer, indicati!:!Q.that the device is full. If the read pointer is not moved after Aeset
(AS), the Full Flag (FF) will go low after 2048 writes for the IDT7203
and 4096 writes for the IDT7204.

READ -ENABLE (R)

EMPTY FLAG (EF)

A read cycle is initiated on the falling edge of the Aead Enable
(R) provided the Empty Flag (EF) is not set. The data is accessed
on a First-In/First-Out basis independent of any ongoing write
operations. After Read Enable (R) goes high, the Data Outputs (00
through 08) will return toa high impedance condition until the next
Aead operation. When all the data has been read from the FIFO, the

The Empty Flag (EF) will go low, inhibiting further read operations, when the read pointer is one location from the write pointer,
indicating that the device is emp!y:'lf the write pointer is not moved
after reset (AS), the Empty Flag (EF) will go low after 2048 reads for
the IDT7203 and 4096 reads for the IDT7204.

6-31

IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

In the Depth E~ansion Mode, Expansion In (Xi) is connected to
Expansion Out (XO) of the previous device. This output acts as a
signal to the next device in the Daisy Chain by providing a pulse to
the next device when the previous device reaches the last location
of memory.

EXPANSION OUT/HALF FULL FLAG (XO/HF)
This is a du~-purpose output. In the single device mode, when
Expansion In (XI) is grounded, this output acts as an indication of a
half-full memory.
After half of the memory is filled, and.2,!. the falling edge of the
next write operation, the Half-Full Flag (HF) will be set to low and
will remain set until the difference between the write pointer and
read pointer is less than or equal to one half of the total memory of
the device. The Half-Full Flag (HF) is then reset by the rising edge
of the read operation.

DATA OUTPUTS (00- as)
00 - 08 are data outputs for 9-bit wide data. These output are in
a high impedance cC?ndition whenever Read

~-------------------------tRse -------------------------~

w

NOTES:
1. £1=. ~ and FW may change status during Reset, but flags will be valid at t Rse '
2. Wand 11 = V1H around the rising edge of Jig.
Figure 2. Reset

6-32
.,

------

fR)

is in a high state.

------.------------------------------------------------1DT7203/1DT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT

1------tRc

MILITARY AND COMMERCIAL TEMPERATURE RANGES

---_Jl..j4---

tR~1

-------00(

-

tDV

t RPW

-I

DATA OUT VALID

tRHZ

)(XID(

DATA OUT VALID

=I

'Il}----

I~-------twc---------~
I~----

w

twpw ------1~

r,t
--------«

DS

tDH

-I

DATA IN VALID

))------C(

DATA IN VALID

Figure 3. Asynchronous Write and Read Operation

LAST WRITE

w

IGNORED
WRITE

FIRST READ

ADDITIONAL
READS

FIRST WRITE

Figure 4. Full Flag From Last Write to First Read

LAST READ

IGNORED
READ

FIRST WRITE

ADDITIONAL
WRITES

FIRST READ

w

-

DATAOUT----1-1r-~~~~~~-_t--------------_1-------_r--~~~~

Figure 5. Empty Flag From Last Read to First Write

6-33

»)----

IOT7203/IOT7204 CMOS PARALLEL
FIRST·IN/FIRST·OUT FIFO 2048 X 9·81T & 4096 X 9·81T

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1.... - - - - - - - - - - . . : . - - - t R T C
tRT

- - - - - - - - - - - . j , ____-+_ _ __

W.l1

HF.EF.FF
NOTE:
1. EF.

FLAG VALID

FF and HF may change status during Retransmit. but flags will be valid at t RTC'
Figure 6. Retransmit

w

Figure 7. Empty Flag Timing

w
Figure 8. Full Flag Timing

6-34

IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096

x 9-BIT

HALF-FULL OR LESS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

HALF-FULL OR LESS

MORE THAN HALF-FULL

w

Figure 9. Half-Full Flag Timing

w

WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION

Figure 10. Expansion Out

1 + - - - - tXI - - _......- - - t X 1 R - - - . I

w

WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION

Figure 11. Expansion In

6-35

IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9·BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

in a Single Oevice Configuration when the Expansion In (XI) can·
trol ine.!:!! is grounded (see Figure 10). In this mode, the Half·Full
Flag f!:!.F), which is an active low output, is shared with Expansion
Out (XO).

OPERATING MODES:
SINGLE DEVICE MODE
A single 1017203/7204 may be used when the application reo
quirements are for 2048/4096 words or less. The 1017203/7204 are

(HALF-FULL FLAG)
WRITE

DATA IN

lOT
7203/04

(rr) EMPTY FLAG

FULL FLAG

(fIT) RETRANSMIT

RESET

EXPANSION IN (5<1)

Figure 12. Block Diagram of Single 2048 x 9/4096 x 9 FIFO

WIDTH EXPANSION MODE

demonstrates an 18·bit word width by using two 10T7203/7204s.
Any word width can be attained by adding additional
10T7203/7204s.
.

Word width may be Increased simply by connecting the carres..e9nding input control signals of multiple devices. Status flags
(EF, FF and HF) can be detected from anyone device. Figure 13

DATA IN (D)

(R) READ
lOT
7203{7204

...
FUt-L_L_F_LA_G_ _....:....--..:...._ _--I720Ij'J204
RESET ---(:....~--'-)- - - - - t t -

(rr) EMPTY FLAG

t------.-

(fIT) RETRANSMIT

(0) DATA OUT

NOTE:

Flag detection is accomplished by monitoring the w.rr and HF' Signals on either (any) device used in the width expansion configuration. Do not connect any
output control signals together.
Figure 13. Block Diagram of 2048 x 18/4096 x 18 FIFO Memory Used In Width Expansion Mode

6-36

IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

must be taken to assure that the appropriate flag is monitored by
each systems (Le. FF is monitored on the device where W is used;
EF is monitored on the device where R is used). Both Depth Expansion and Width Expansion may be used in this mode.
DATA FLOW-THROUGH MODES

DEPTH EXPANSION (DAISY CHAIN) MODE
The 1017203{7204 can easily be adapted to applications when
the requirements are for greater than 2048/4906 words. Figure 14
demonstrates Depth Expansion using three 1017203/7204s. Any
depth can be attained by adding additional ID17203/7204. The
1017203/7204 operates in the Depth Expansion configuration
when the following conditions are met:
1. The first device must be designated by grounding the First Load
(FL.) control input.
2. All other devices must have

Two types of flow-through modes are permitted, a read flowthrough and write flow-through mode. For the read flow-through
mode (Figure 17), the FIFO permits a reading of a single word after
writing one word of data into an empty FIFO. The data is enabled
on the bus in (tWEF + tN ns after the rising edge of W, called the first
write edge, and it remains on the bus until the R line is raised from
low-to-high, after which the bus would go into a three-state mode
after tRHZ ns. The EF line would have a pulse showing temporary
deassertion and then would be asserted. In the interval of time that
R was low, more words can be written to the FIFO (the subsequent
writes after the first write edge will deassert the empty flag); however, the same word (written on the first write edge), presented to
the output bus as the read pointer, would not be incremented when
R is low. On toggling R, the other words that were written to the
FIFO will appear on the output bus as in the read cycle timings.
In the write flow-through mode (Figure 18), the FIFO permits the
writing of a single word of da~ immediately after reading one word
of data from a full FIFO. The R line causes the FF to be deasserted
but the W line being low causes it to be asserte~again in anticipation of a new data word. On the riSing edge of W, the new word is
loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write
pointer.
For additional information, refer to Tech Note 8: "Operating
FIFOs on Full and Empty Boundary Conditions" and Tech Note 6:
"DeSigning with FIFOs".

Fi. in the high state.

3. The Expansion Out (XO) pin of each device must be tied to the
Expansion In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full ~ (FF)
and Empty Flag (EF). This requires the ORing of all EFs and
ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not
available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9: "Cascading
FIFOs or FIFO Modules".

COMPOUND EXPANSION MODE
The two expansion techniques described above can be applied
together in a straightforward manner to achieve large FIFO arrays
(see Figure 15).

BIDIRECTIONAL MODE
Applications which require data buffering between two systems
(each system capable of Read and Write operations) can be
achieved by pairing 1017203/7204s as shown in Figure 16. Care

TRUTH TABLES
TABLE I-RESET AND RETRANSMITSINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
INPUTS

MODE
Reset
Retransmit
Read/Write

INTERNAL STATUS

OUTPUTS

RS

RT

XI

Read Pointer

Write Pointer

EF

FF

0
1
1

X

0

Location Zero

Location Zero

0

1

1

0
1

0

Location Zero

Unchanged

X

X

X

0

Increment(1)

Increment(1)

X

X

X

HF

NOTE:
1. Pointer will increment if flag is high.

TABLE II-RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
INTERNAL STATUS

INPUTS

MODE

OUTPUTS

RS

FL

XI

Read Pointer

Write Pointer

EF

FF

Reset First Device

0

(1)

Location Zero

Location Zero

0

1

Reset all Other Devices

0
1

0
1

(1)

Location Zero

Location Zero

0

1

X

(1)

X

X

X

X

Read/Write

NOTE:
1. Xi is connected to XO of previous device. See Figure 12.
RS = Reset Input. FURT = First Load/Retransmit. EF = Empty Flag Output. FF

6-37

= Full Flag Output. Xi = Expansion Input. HF = Half-Full Flag Output

(II
•

IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 X 9-BIT & 4096 X 9-BIT

9.

.

I

I

f

"

Iw

.
FF'

w
"[)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

9 ...

lOT
7203/04

f

T-y'

~

--..

rorr

.

.~

f.\-:,

...

~

~

I >
-rr-v

~

'-'----

..

Ff
~

Figure 14. Block Diagram of 6,144

X

~

lOT
7203/04

IDT720317204
DEPTH
EXPANSION
BLOCK

.

9,

Q)

,.

Vee

i-4

...IT.

...
~...
..: J

-,

-

~

IT
~

1--

t: 1i

l-

-=--

-

r~
9/12,288 x 9 FIFO Memory (Depth Expansion)

Os

'R:.W.~

I

.f

t;.-

lOT
9.L.A 7203/04

J..' ..L

I

~

I )

liS"

~

E"F

IDT7203/04
DEPTH
EXPANSION
BLOCK

-017

• • • _ _ _....

•••

Do -08

NOTES:
For depth expansion block see section on Depth Expansion and Figure 14.
For Flag detection see section on Width Expansion and Figure 13.

1.
2.

Figure 15. Compound FIFO Expansion

6-38

IDT7203/04
DEPTH
EXPANSION
BLOCK

EMPTY
,
-""

IDT7203/IDT7204 CMOS PARALLEL
FIRST-IN/FIRST-OUT FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

...- - - - R B
. - - - - -.... E"FB
IDT
7203/04 . - - - - -.... W B

"F"FA

0B 0-8

SYSTEM A

SYSTEM B

DB 0-8

IDT

RA - - - -.... 7203/04
W A ....C - - - - - - i

.....:--.----wB

E"FA ....:-:----l

I----~

Figure 16. Bidirectional FIFO Mode

w

DATA OUT

Figure 17. Read Data Flow-Through Mode

6-39

"F"FB

IDT7203fIDT7204 CMOS PARALLEL
FIRST·IN/FIRST·OUT FIFO 2048 X 9·BIT & 4096 X 9·BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

w

DATA IN
VALID

DATAIN

DATA OUT

I-tOS-/

~J

--------~DATA OUTVALID'@~-------

Figure 18. Write Data Flow·Through Mode

ORDERING INFORMATION
IDT

XXX><
Device Type

A
Package

A
Power

A"
Process/
Temperature
Range

y~k
P
D

~--------------~ J
L

Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STO-B83, Class B
Plastic DIP
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier

50

~

____________________--165

80
120
~

____________________________

~

S
L

7203
~------------------------------------~ 72M

6-40

Access Time (tA )
} Speed in Nanoseconds

Standard Power
Low Power
2045 x 9-Bit FIFO
4096 x 9-Bit FIFO

FEATURES:

DESCRIPTION:

• First-In/First-Out (FiFO) dual-port memory

The 10172041 is a dual-port memory that utilizes a special FirstIn/First-Out algorithm that loads and empties data on a first-in/
first-out basis. The device has Full, Empty, Half-Full and Almost~
Empty/Full flags to prevent data overflow or underflow. Expansion
logic allows wider and/or deeper FIFOs to be created using multiple devices, without external logic.
The reads and writes are Internally sequential through the use of
ring pointers, with no address information required to load and unload data. Oata is toggled in and out of the device through the use
of the Write rN) and Read (R) pins. The device has a read/write access time of 35ns and a read/write cycle time of 45ns (22MHz). The
10172041 can perform asynchronous and simultaneous read and
write operations.
The 10T72041 utilizes a 9-bit wide dual-port RAM array to allow
for zero fall-through time and to allow the user to store tag or parity
bits. This 9-bit feature is useful in data communications applications where transmission/reception error checking is necessary. It
also features a Retransmit (RT) capability that allows for reset of
the read pointer to its initial position, when RT is pulsed low, to allow for retransmission of data from the beginning. Four status flags
prevent the overflow or underflow of the FIFO and permit interrupt
signals to be sent to the transmitting data source.
The 10172041 is fabricated using lOT's high-performance
CEMOS ™ technology, which combines high speed and low
power consumption. Military grade product is manufactured in
compliance with the latest revision of MIL-STO-883, Class B, for
high-reliability systems.

•
•
•
•
•

4K x 9-bit organization
Ultra high speed: 35ns access time, 45ns cycle time (22MHz)
Fully expandable by both word depth and/or bit width
Asynchronous and simultaneous read and write
Functionally equivalent to the 1017204 but with Output Enable
and Almost-Empty/Full Rag

• Four status flags: Full, Empty, Half-Full (single device mode)
and Almost-Empty/Full (1/8 or 7/8) signalonO,512, 2048,3584,
and 4096-byte boundaries
• Output Enable controls the data output port
•
•
•
•

Auto retransmit capability
Master/Slave multiprocessing applications
Video frame buffer or laser printer buffer applications
Available in 32-pin OIP and surface mount 32-pin LCC and
PLCC

• Military product compliant to MIL-STO-883, Class B

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM
DATA OUTPUTS

(0 0 -0 8 )
INDEX

~~~

y;2 ~ ;29
28

CONSULT
FACTORY
FOR

27
26
25

10
P~~~GE
24
1123
12
13

22
21
14 15 16 17 18 19 20

w
I:

I:
I:
I:
I:
I:
I:
I:
I:

06
07

F[ffiT
~
~
~

W/FW
07
06

nnnnnnn

LCC/PLCC
TOP VIEW

... FW

r-~==i-

DIP

FLAG

TOP VIEW

LOGIC

I----r-- ~

1 - - - - + - - _ FF

L-..,..-..J--I--' AEF
R T - - - - . t......_ _....."t-----· X(J/FW
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
DSC-2OO7/-

6-41

DESCRIPTION:

FEATURES:
•
•
•
•
•

Firs~-In/First-Out dual-port memory

The IDT720S is a dual-port memory that utilizes a special FirstIn/First-Out algorithm that loads and empties data on a first-in/firstout basis. The device uses Full and Empty flags to prevent data
overflow and underflow and expansion logic to allow for unlimited
expansion capability In both word size and depth.
The reads and writes are internally sequential through the use of
ring pointers, with no address information required to load arid unload data. Data is toggled in and out of the device through the use
of the WRITE (N) and READ (R) pins. The device has a read/write
cycle time of 6Sns (1SMHz).
The device utilizes a 9-bit wide data array to allow for control and
parity bits at the user's option. This feature is especially useful in
data communications applications where It is necessary to use a
parity bit for transmission/reception error checking. It also features
a RETRAf;JSMIT (RT) capability that allows for reset of the read
pointer to its initial position, when RT is pulsed low, to allow for
retransmission from the beginning of data. A Half-Full Flag is available In the single device mode and width expansion modes.
The IDT720S is fabricated using IDT's high-speed CEMOSsubmicron technology. It is designed for those applications requiring
asynchronous and simultaneous read/writes In multiprocessing
and rate buffer applications. The 8K x 9 organization allows a 8196
deep word structure without the need for expansion.
Military grade product Is manufactured In compliance with the
latest revision of MIL-STD-883, Class B.

8K x 9-bit organization
Low power consumption
Ultra high speed: 6Sns cycle time
Asynchronous and simultaneous read and write

•
•
•
•
•
•
•
•
•

Fully expandable by both word depth and/or bit width
Pln-compatlble with IDT7~OO/01/02l03/04 FIFO family
Half-Full Flag capability In single device mode
MASTER/SLAVE multiprocessing applications
Bidirectional and rate buffer applications
Empty and Full warning flags
Auto retransmit capability
High-performance sub micron CEMOS TM technology
Available In 28-pin plastic DIP, CERDIP and 32-pin surface
mount LCC and PLCC
• Military product compliant to MIL-STD-883, Class B

PIN CONFIGURATIONS

w

~
D4
D5
D6

D8
D3
D2
D1
Do

INDEX'Ii

D7

F'C/J1T
liS

Xl

1='F'

~

00
01

W/FfF:
07
06
05
04

O2
03

FUNCTIONAL BLOCK DIAGRAM

L!L.!WIIWWW

"

4 3 2 w 3231 30
1
29 [:
D2 :15
28 [:
D1 :16
27 t:
Do :17
CONSULT
26t:
Xl :J 8
FACTORY
25 t:
FOR
:19
1='F'
PACKAGE
24 t:
0 0 :I 10
INFO
23 t:
0 1 :111
22t:
NC :I 12
21 t:
:I
13
O2
14 15 16 17 1819 20

D6
D7
NC

F'C/J1T
liS
~

W/FfF:
07
06

[1r:r:r:r:r:j"1

R
DIP
TOP VIEW

"FI/Ai

LCC/PLCC
TOP VIEW

CEMOS Is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-2008/-

6-42

FEATURES:

DESCRIPTION:

• 50ns parallel port access time
• 40MHz serial input/output port frequency
• Serial-to-Parallel, Parallel-to-Serial, Serial-to-Serial and
Parallel-to-Parallel operations

The IDT72103/72104 are high-speed Parallel-Serial FIFOs that
are ideally suited for serial communications, high-density media
storage and local area networks.
The devices have four ports: two 9-bit parallel ports and the
other two for serial input and serial output. A variety of operations
can be performed: Serial-to-Parallel, Parallel-to-Serial, Serial-toSerial and Parallel-to-Parallel. The Parallel-Serial FIFOs can expand in depth or width for any of these modes.
A unique feature that enhances the bandwidth is the handling of
serial word lengths that are not a multiple of 9. The IDT721 03/721 04
can be configured to handle serial wordlengths from 4 bits to words
of any length using multiple devices. This feature is provided without using any additional ICs. For example, a user can configure a
4K x 24 FIFO by using three devices to generate internal increments to the read/write pointers every 24 cycles.
A number offlags are provided to monitor the status of the FIFO.
These include Full, Almost-Full (when the FIFO is more than 7/8
full), Full-Minus-One (when the FIFO has one or zero locations left),
Empty, Almost-Empty (when the FIFO is less than 1/8 full), EmptyPlus-One (when there is only one or zero samples left in the FIFO)
and Half-Full.
Read and Write controls are provided to permit asynchronous
and simultaneous operations. An Output Enable control is provided on the parallel output port. Expansion control pins XO and
Xi are provided to allow cascading for deeper FIFOs.
The IDT72103/72104 are manufactured using lOT's CEMOS
technology. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Class 8.

• Easily expandable in depth and width
• Programmable word lengths from 4 bits to any bit width using
Flexishift ™ for serial operations without using any additional
components
• Multiple status flags: Full, Almost-Full (1/8 from full), Full-MinusOne, Empty, Almost-Empty (1/8 from empty), Empty-Plus-One
and Half-Full
• Asynchronous and simultaneous read and write operations
• Dual-ported zero fall-through time architecture
• Output enable control provided for parallel output port
• Retransmit capability in single device mode
• High-performance CEMOS ™ technology
• Available in 40-pin ceramic and plastic DIP,44-pin LCC and
J-Leaded PLCC
• Military product compliant to MIL-STD-883, Class B

APPLICATIONS:
•
•
•
•
•
•
•
•

High-Speed Oata Acquisition Systems
Local Area Network Buffers
Remote Telemetry Buffers
Serial Link Buffers
High-Speed Parallel Bus-ta-Bus Serial Communications
Magnetic Media Controllers
Single Chip Video Frame Buffers
FAX/Printer Buffers

FUNCTIONAL BLOCK DIAGRAM
SICP
SIX
SERIAL INPUT

DATA INPUTS

----.r-~S:-;:E~R7':IA'7"L7.IN:7:P~U;;:T---,

-----l..-

(0 0 -0 8 )

CIRCUITRY

~/PI ------~~S~E~R~IA~U~P~A~R~A~LL~E~L~=r~~~~~
CONTROL

"SO/PO ---~

WRITE
w -----.....~===
POINTER

rr/:~

XT--f

RESET
LOGIC
EXPANSION
LOGIC

r
r

r--,..~2-1-_
FLAG
LOGIC

rorr=T
mPTV+T
t-=2:.r----,~ EM15TV / rorr
I--~~

ALMOST -EMPTY/FULL .

~::::~------~ HALF-FULL

1+----11

SOCP

+
xo

SERIAL OUTPUT
CIRCUITRY

OUTPUT ENABLE

DATA OUTPUTS

(ot)

(0 0 -08 )

SOX
SERIAL OUTPUT

CEMOS and Flexishift are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-2009/-

6-43

IOT72103/IOT72104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION
o

SOCP

t§ 0" 00 0'13 ~oo'" 0" orrJ

INDEX

sox'

'SO/po
'5/PO)

m)

WRITE

Vee
READ

DATA'N
IDT
72103/4

(rr)
RESET

Parallel Data Output

Vee

By setting SO/PO HIGH, the Parallel-Out mode is chosen. A
read cycle is initiated on the falling edge of Read (F'I) provided the
Empty Flag is not set. The output data is accessed on a first-in/firstout basis, independent of the ongoing write operations. In the Parallel-Out mode, as shown in Figure 23 the data is available tA after
the falling ~ge of R and the output bus Q goes into high impedance after R goes HIGH.
Altemately, the user can access the FIFO by keeping R LOW
and enabling data on the bus by asserting Output Enable (OE).
When
is LOW, the OE signal enables data on the output bus.
When R is LOW and OE is HIGH, the output bus is three-stated.
When R is HIGH, the output bus is disabled irrespective of OE. The
enable and disable times for Output Enable are shown in Figure 22.

(liS)
(Sl/PI)

CRT)

EMPTY FLAG
RETRANSMIT

(OE") OUTPUT ENABLE

EXPANSION IN (XI)

Figure 3. Block Diagram of Single 2048

B

x 9/4096 x 9 FIFO

Width Expansion Mode
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags can
be detected from anyone device. Figure 4 demonstrates an 18-bit
word width by using two IDT72103/4s. Any word width can be attained by adding additionaIIDT72103/4s.

Single Device Mode
A single IDT721 03/4 may be used when the application requirements are for 2048/4096 words or less. The IDT72103/4 is in the
Single Device Configuration when the ExpanSion In (Xi) control input is grounded. (See Figure 3.) In this mode the Half-Full Flag
(HF), which is an active low output, is shared with Expansion Out
(XO).

6-50

IDT72103/IDT72104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

m:
(~/PO)

DATAIN (0)

Vcc
OUTPUT
ENABLE

(O!:)

WRITE----'-....:....---+lFULL FLAG
(FF)
IDT
- - - - - ' - - - ' - - - - 1 72103/4
RESET _ _~(,-"R"S.....:....)- - - . l l -

IDT
72103/4

(li)

READ

(~)

EMPTY FLAG

(liT)

RETRANSMIT

Vcc _ _ _(Sl~/P.:..t...I)_ _...

(0) DATAoUT

NOTE:
1. Flag detection is accomplished by monitoring the FF. l:F and the
connect any flag signals together.
Figure 4. Block Diagram of 2048

m: signals of either (any) device used in the width expansion configuration. Do not

x 18/4096 x 18 FIFO Memory Used In Width

Expansion Mode

TRUTH TABLES
TABLE 2: RESET AND RETRANSMITSINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
INPUTS

MODE

OUTPUTS

INTERNAL STATUS

'E'F';' 'E'F+T FF,

liS

~

XI

READ POINTER

WRITE POINTER

Reset

0

X

0

Location Zero

Location Zero

0

1

1

Retransmit

1

0

0

Location Zero

Unchanged

X

X

X

Read/Write

1

1

0

Increment

Increment

X

X

X

(1)

AEF,

(1)

FF-1

HF

NOTE:
1. Pointer will increment if appropriate flag is HI GH.

TABLE 3: RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
MODE

OUTPUTS

INTERNAL STATUS

INPUTS

AS'

FL

XI

READ POINTER

WRITE POINTER

EF

FF

Reset-First Device

0

0

(1)

Location Zero

Location Zero

0

1

Reset all Other Devices

0

1

(1)

Location Zero

Location Zero

0

1

Read/write

1

X

(1)

X

X

X

X

NOTES:
Xi is connected to XO of previous device.
2. RS = Reset Input. fuRT = First Load/Retransmit.

1.

EF

= Empty Flag Output.

6-51

FF =

Full Flag Output.

Xi

= Expansion Input

IDT72103/IDT72104 CMOS
PARALLEL·SERIAL FIFO 2048 x 9-BIT & 4096 x 9·BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

3. The Expansion Out (XO) pin of each device must be tied to the
Expansion In (Xi) pin of the next device. See Figure 5.
4. External logic is needed to generate a composite Full Flag (FF)
and Empty FI~ (EF). This requires the OR·ing of all EFs and
OR-Ing of C!!!..,FF ~.e., all must be set to generate the correct
composite FFor EF). See Figure 5.
5. The Retransmit (RT) lunctlon and Half-Full Flag (HF) are not
available In the Depth Expansion mode.

Depth Expansion (Daisy Chain) Mode
The IDT72103/4 can be easily adapted to applications where
the requirements are for greater than 2048/4096 words. Figure 5
demonstrates Depth Expansion using three IDT72103/4s. Any
depth can be attained by adding additional IDT72103/4s. The
IDT72103/4 operates in the Depth Expansion configuration when
the following conditions are met:
1. The first device must be designated by grounding the First Load
WI.) control Input.
2. All other devices must have FL in the high state.

w
D

FUII

9.
I

.

J

..T
I

Iw
f!l!
~

...

-

I
""'"Y

1:

4.-

f!l!

L

9, ..

\

IDT

72103
72104

I
"T-y

IDT

72103
72104

f!l!

'---

9.LA.

I

~

J..

)
~

I

~
r---

r---

72103
72104

9.
I

~

...rr.

~

.\

J
.'--I-r--

I-

--

r~

NOTE:

1. 'Sl/PI and ~/PO pins are tied to Vee'

Figure 5. Block Diagram of 6,144 x 9/12,288 x 9·FIFO Memory, Depth Expansion

6-52

.

,

Q)
Vee

~

1: -

IDT

I

~
~

~

'-

l={
~

~

IDT12103/IDT12104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Bidirectional Mode

achieved by pairing IDT721 03/4 as shown in Figure 6. Both Depth
Expansion and Width Expansion may be used in this mode.

Applications which require data buffering between two systems
(each system capable of Read and Write operations) can be

,..---

WA
rFA
DAO-S

..

~s

EFS

IDT
72103
72104

,-

Ws

DE
OsO-S

SYSTEM A

SYSTEM B

-A
OAO-S

DsO-S
IDT ,
72103
72104

DE
~A

~

Ws

[III

"F"Fs

Figure 6. Bidirectional FIFO Mode

I
Compound Expansion Mode
The two expansion techniques described above can be applied
together in a straightforward manner to achieve large FIFO arrays
(see Figure 7).

Oo-Os

0g-017

O(N-S)-ON

0(N-8)-ON

0g-017

Oo-Os
~.W.'FIS

•••

IDT721 03/1 04
DEPTH
EXPANSION
BLOCK

IDT721 03/104
DEPTH
EXPANSION
BLOCK

•••

IDT721 03/1 04
DEPTH
EXPANSION
BLOCK

D(N-S)-DN
Dg-DN

D(N-S)-DN

NOTES:
1. For depth expansion block see DEPTH EXPANSION Section and Figure 5.
2. For Flag detection see WIDTH EXPANSION Section and Figure 4.
Figure 7. Compound FIFO expansion

6-53

IDT72103/IDT72104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

the next clock cycle, after Iii is HIGH, all of the 0 lines go LOW
again and a new serial word input starts.
.
In the cascaded case, the first LOW~to-HIGH SICP clock edge
for a serial word will cause all timed outputs (D) to go LOW except
for Do of the least significant device. The D outputs of the least significant device will go high on consecutive clock cycles until De.
When Da goes HIGH, the SIX of the next device goes HIGH. On the
next cycle after the SIX input is brought HIGH, the Do goes HIGH;
then on the next cycle Dl and so one. A 01 gytput from the most
significant device is issued to create the W for all cascaded
devices.
The minimum serial word width is 4 bits and the maximum is virtually unlimited.
When in the Serial mode, the Least Significant Bit of a serial
stream is shifted in first. If the FIFO output is in the Parallel mode,
the first serial bit will come out on 00. The second bit shifted in is on
01 and so on.
In the Serial Cascade mode, the serial input (SI) pins must be
connected together. Each of the devices then receives serial information together and uses the SIX and Do-a lines to determine
whether to store it or not.
The example shown in Figure 10 shows the interconnections for
a serializing FIFO that transfers data to the internal RAM in 16-bit
quantities (i.e. every 16 SICP cycles). This corresponds to incrementing the write pointer every 16 SICP cycles.

Serial Operating Modes
Serial Data Input
The Serial Input mode is selected by grounding the S'i/Plline.
The Do-e lines are then outputs which are used to program the
width of the serial word. They are taps off a digital delay line which
are meant for connection to the Iii input. For instance, connecting
D6 to Iii will program a serial word width of 7 bits, connecting Di to
ViI will program a serial word width of 8 bits and so on.
By programming the serial word width, an economy of clock cycles is achieved. As an example, if the word width is 6 bits, then on
every 6th clock cycle the serial data register is written in parallel
into the FIFO RAM array. Thus, the possible clock cycles for an extra 3 bits of width in the RAM array are not required.
The SIX signal is used for Serial-In Expansion. When the serial
word width is 9 or less, the SIX input must be tied HIGH. When more
than 9 bits of serial word width is required, more than one device is
required. The SIX input of the least significant device must be tied
HIGH. The Da pin of the least significant device must be tied to SIX
of the next significant device. In other words, the SIX input of the
most significant and intermediate devices must always be connected to the Da of the next least significant device.
Figure 8 shows the relationship of the SIX, SICP and Do-a lines.
In the standalone case (Figure 8), on the first LOW-to-HIGH of
SICP, the DI-7 lines go LOW and the Do line remains HIGH. On the
next SICP clock edge, the 01 goes HIGH, then ~ and so on. This
continues until the 0 line, which is connected to W, goes HIGH. On

6-54

IDT72103/1DT72104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SINGLE DEVICE SERIAL INPUT CONFIGURATION

Vee

GND

SERIAL-IN CLOCK

SICP

SERIAL-IN DATA

SI

Vc'e

IDT721 03/4

°0-7

8

SIX

W

2

0

3

4

5

6

7

0

4

3

2

6

5

7

0

SICP
Do= 1

Dl~
D2

\

D3

\

D4

\

D5

\

D6

\

D7 \

w

\

\.J
/

\
/

\

/

\

'-/

/
/

\

/

\

/

1\
f\

Figure 8. Serial-In Mode Where 8-Bit Parallel Output Data is Read

6-55

/

'-'-'-'-"--I'L
I'L

10172103/10172104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SERIAL DATA IN

SERIAL INPUT
CLOCK

DATA INfflMED
OUTPUTS Do-s

-~t---___

~-~-r--";"""""

9

t - - - - - - - + - - -.......- - Sl/PI

~--~-----

DATA INTO
FIFO RAM

DELAYED
TIMING
GENERATOR

W

Figure 9. Serial-Input Circuitry

SERIAL INPUT WIDTH EXPANSION

GND

SERIAL-IN
DATA

SI

SERIAL-IN
CLOCK

SICP

Vee

GND

Vee

Vee

SI
SICP

10172103/104
FIFO #1

SIX

10172103/104
FIFO #2

SIX

Q~-s

W

W

Os

De

9
'--y--J
16-BIT
PARALLEL
OUTPUT
0
SICP

7

8

9

10

AA

Os OF FIFO #1
AND SIX OF
FIFO #2

\

III

De OF FIFO #2
ANDWTO
FIFO #1
AND FIFO #2

\

l',

14

15

0

I\JV\
u

/

'IL

Figure 10. Serial-In Configuration for Serial-In to Parallel-Out Data of 16 bits

6-56

IDT72103/IDT72104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SERIAL INPUT WITH DEPTH EXPANSION
00-7

Vcc

GND - - - - I

m/PI

0 0- 7

'SO/PO

Vcc----t

Ii .....- ......- H - IDT721 04

SICP - - -....- 1 - - - - - - - - - - '
GND
Vee
F"C/RT

IDT72104

SIX
SOX

SI

SICP

S I - - - - - t f - e - - - - - -.....
NOTE:
1. All SI/PI pins are tied to Vee and SO/PO pins are tied to GND.

BE is tied HIGH. For FF and EF connections see Figure 17.

Figure 11. An 8Kx 8 Serial·ln, Parallel-Out FIFO

SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION
SER IAL
DATA IN

l

1.

!

Vcc~

SI

SIX

I

~.

D8

SIX

I

SI

D8

W

W f4-

r----

SICP

'5

m

08

'F'C/RT

tl ~

SOX SO SOCP

xc:>

m

06

xc:>

D6

t

I
FULL
FLAG
EMPTY
FLAG

Vee
Vee

t

T
SIX

j
SI

SICP m

'F'C/RT

xc:>

+

W

1=1=

~

E'F'
Vee

SOX SO SOCP

SIX

D8
~

-

L..

08

l

SICP m

W I'F'C/RT
~

SOX SO SOCP

t

SOCP
SO
NOTE:
1. All ~ pins are connected together. All 'O'E' pins are connected HIGH. All m/PI and ~/PO pins are grounded.
Figure 17. A 128K x 1 Serial-In Serial-Out FIFO

6-60

SI

Vee

06

I-

IOT72103/10T72104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-81T & 4096 x 9-81T

MILITARY ANO COMMERCIAL TEMPERATURE RANGES

1+------------- t Ase

W

NOTE:
1. EF, FF and H F may change status during Reset, but flags will be valid at t ASC •
Figure 18. Reset

1 - - - - - - - - - - - - - - tATC
tAT

-----------+\ ,.____-+____

W,'A

FLAG VALID

NOTE:
1. EF, FF and

HF, AEF, FF-l and EF+ 1 may change status during Retransmit, but flags will be valid at t ATC .
Figure 19. Retransmit

6-61

- - - - - - - - - - - - - - - " ' - - .._ - - -

IDT721 03/1DT721 04 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT

w

MILITARY AND COMMERCIAL TEMPERATURE RANGES

WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION

Figure 20. Expansion-Out

14----

tXI

----1+---- tXIR --~

WRITE TO
FIRST PHYSICAL
LOCATION

w

READ FROM
FIRST PHYSICAL
LOCATION

Figure 21. Expansion-In

tOEHZ

00-8

Figure 22. Output Enable Timings

6-62

IDT72103/IDT72104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PARALLEL TIMINGS - READ/WRITE
1--------tRc

------.J

I--------twc-------~~

w

Figure 24. Write Operation in Parallel Data In Mode

Figure 23. Read Operation in Parallel Data Out Mode

PARALLEL TIMINGS - FLAGS

\'---/+------tREF(2)----~

\'----

w

NOTES:
1. Data is valid on this edge.
2. The Empty Flag is asserted by'R in the Parallel-Out mode and is specified by t REF . The"EF" flag is deasserted by the rising edge of W.
3. First rising edge of Write after ~ is set.

Figure 25. Empty Flag Timings In Parallel-Out Mode

W

\'----/+------

tWFF(l)-----l~

NOTE:
1. For the assertion time, tWFF is used when data is written in the Parallel mode. The rF" is deasserted by the rising edge of'R.
Figure 26. Full Flag Timings In Parallel-In Mode

6-63

10T721 03/10T721 04 CMOS
PARALLEL·SERIAL FIFO 2048

x 9·81T & 4096 x 9·81T

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PARALLEL TIMINGS-FLAGS

w

AEF

Almost Full
Almost Full

Almost Empty

+1

Almost Empty - 1

Almost Empty - 1

Figure 27. The Almost·Full, Half·Full and Full-1 Flag Timings

w

Figure 28. Empty + 1 Flag Timings

6-64

Almost Full

1DT72103/IDT72104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SERIAL TIMINGS - READ/WRITE

t+-: 1/tsocP -l

I 00

I 01

soep

sox

so
tSOHZ

so
NOTE:
1. After SO/PO has been set up, it cannot be dynamically changed; it can only be changed after a reset operation.
Figure 29. Read Operation In Serial-Out Mode

1. For the Standalone mode, N ~ 4 and the input bits are numbered Oto N-1.
2. For the recommended interconnections, DI is to be directly tied to Wand the t S4 and t H4 requirements will be satisfied. For users that modify Wexternally,
tS4 and tH4 have to be met.
3. After Sf/PI has been set up, it cannot be dynamically changed; it can only be changed after a reset operation.

Figure 30. Write Operation In Serial-In Mode

6-65

IDT72103/1DT72104 CMOS
PARALLEL~SERIAL FIFO 2048 x 9-BIT & 4096 X 9·BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SERIAL TIMINGS - FLAGS

I-- FIRST SERIAL-OUT WORo-+- SECOND SERIAL-OUT WORD-!
o

1

N-1

0

1

N-1

rv-\-

SOCP

w

NOTES:
1. The FIFO is full and a new read sequence is starting.
2. On the first rising edge of SOCp, the "FF is de·asserted. In the Serial·ln mode, a new write operation can begin after t RFFS1 after ~ goes HIGH. In the
Parallel·ln mode, a new write operation can occur immediately after"FF flag goes HIGH.
3. The FF=T Flag is deasserted after the first SOCP of the second serial word.
Figure 31. Full Flag and Full-1 Flag Deassertion In the Serlal·Out Mode

I--- SERIAL WORD A -+- SERIAL WORD B -+ LAST SERiGVilAL
WORD--! NOTE 4
SOCP

R'

------~

o

1

n-2

n-1

0

1

n-2

n-1

0

1

n-2

n-1

0

1

~

= On+1

~ ----'r----------------------------------------~~NOTE2
NOTE
_
/ _1

W

_

•

~ ~ ~

WORD A

WORD B

~I

NOTE 3

~-----------

1--\'
-=

t+' tWEF

_

.-------

LAST WORD

NOTES:
1. Parallel write shown for reference only. Can also use serial input mode.
2. The Empty Flag is asserted in the Serial-Out mode by using the tsocEF parameter. This parameter is measured in the worst case from the rising edge of the
SOCP used to clock data bit O. Whenever E"F_9()es LOW, there is only one word to be shifted out. In the Parallel·ln mode, the E""F flag is de asserted by the
rising edge of W. In the Serial-In mode, the EF flag is deasserted by the rising edge of W.
3. First Write riSing edge after E"F is set.
4. SOCP should not be clocked until E"F goes HIGH.
Figure 32. Empty Flag and Empty + 1 Flag Assertion in the Serial·Out Mode, FIFO Being Emptied

6-66

10172103/10172104 CMOS
PARALLEL-SERIAL FIFO 2048 x 9-BIT & 4096 x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SERIAL TIMINGS - FLAGS

I-

NEXT TO LAST
SERIAL WORD

-+

LAST SERIAL WORD

-I

SICP

W=

Dn-1

NOTES:
1. The Full Flag is asserted in the Serial-In mode by using the tSICFF parameter. This parameter is measured in the worst case from the rising edge of SICP
followed by a (tpD1 +tWFFl delay from the first rising edge of SICP of the last word.
2. First Read rising edge after f!l= is set.
3. SICP should not be clocked until IT goes HIGH.

Figure 33. Full Flag and Full-1 Flag Assertion in the Serial-In Mode, FIFO Being Filled

THIRD SERIAL-IN
WORD

~ FIRST SERIAL-IN WORD -+-SECOND SERIAL-IN WORD~

o

1

N-1

0

1

N-1

0

SICP

Dn-1 =

W

NOTES:
1. Parallel Read shown for reference only. Can also use serial output mode.
2. The Empty Flag is deasserted when an entire word has been loaded into the internal RAM. It can occur after the first rising edge of SICP of the second
Serial-In word. In the Serial-Out mode, a new read operation can begin tREFSO after"EF goes HIGH. In the Parallel-Outmode. a new read operation can occur
immediately after ~ goes HIGH.
3. The Empty + 1 Flag is deasserted after the first rising edge of SICP of the third Serial-In word.

Figure 34. Empty Flag and Empty + 1 Flag Oeassertlon In Serial-In Mode

6-67

IDT72103/IDT72104 CMOS
PARALLEL-SERIAL FIFO 2048

X

9-BIT & 4096

X

9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxxxx
Device Type

999
Speed

A
Process!
Temperature

RMy:1Mk
P

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B,

L

Plastic DIP
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier

50
65
80
120

(40MHz serial
(33MHz serial
(28M Hz serial
(25M Hz serial

S
L

Standard Power
Low Power

72103
72104

2048 x 9-Bit Parallel-Serial FIFO
4096 x 9-Bit Parallel-Serial FIFO

D

J

6-68

Commercial (O°C to

shift rate)
shift rate)
shift rate)
shift rate)

}
Parallel Access Time (t )
A

--------------------------------------------------------

bits. The IDT72402 and IDT72404 are asynchronous, highperformance First-In/First-Out memories organized as 64 words
bE bits. The IDT72403 and IDT72404 also have an Output Enable
(OE) pin. The FIFOs accept 4-bit or 5-bit data at the data input
(Do -D3, 4). The stored data stack up on a first-in/first-out basis.
A Shift Out (SO) signal causes the data at the next to last word to
be shifted to the output while all other data shifts down one location
in the stack. The Input Ready (IR) signal acts like a flag to indicate
when the input is ready for new data (IR = HIGH) orto signal when
the FIFO is full (IR = LOW). The Input Ready signal can also be
used to cascade multiple devices together. The Output Ready
(OR) signal is a flag to indicate that the output contains valid data
(OR = HIGH) or to indicate that the FIFO is empty (OR = LOW).
The Output Ready signal can also be used to cascade multiple devices together.
Width expansion is accomplished by logically ANDing the Input
Ready (IR) and Output Ready (OR) Signals to form composite
signals.
Depth expansion is accomplished by tying the data inputs of
one device to the data outputs of the previous device. The Input
Ready pin of the receiving device is connected to the Shift Out pin
of the sending device and the Output Ready pin of the sending device is connected to the Shift In pin of the receiving device.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital machines of widely varying operating frequencies. The 45MHz speed
makes these FIFOs ideal for high-speed communication and controller applications.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

First-In/First-Out dual-port memory
64 x 4 organization (IDT72401/03)
64 x 5 organization (IDT72402/04)
IDT72401/02 pin and functionally compatible
with MM167401/02
RAM-based FIFO with low fall-through time
Low power consumption
- Active: 175mW (typ.)
Maximum shift-rate-45MHz
High data output drive capability
Asynchronous and simultaneous read and write
Fully expandable by bit width
Fully expandable byword depth at 35MHz
IDT72403/04 have Output Enable pin to enable output data
High-speed data communications applications
High-performance CEMOS TM technology
Available In CERDIP, plastic DIP, LCC and SOIC
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing# 5962-86846 is pending listing on
this function. Refer to Section 2/page 2-4.

DESCRIPTION:
The IDT7240 1 and IDT72403 are asynchronous, highperformance First-In/First-Out memories organized 64 words by 4

FUNCTIONAL BLOCK DIAGRAM

SI
IR

INPUT
CONTROL
LOGIC

WRITE POINTER

~

(IDT72403 and
IDT72404)

WRITE MULTIPLEXER

00--3
MEMORY
ARRAY

D4
(IDT72402
and IDT72404)

MR

00--3
04 (IDT72402 and
IDT72404)

MASTER
RESET

READ MULTIPLEXER
READ POINTER

OUTPUT
CONTROL
LOGIC

SO
OR

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
080-2011/-

6-69

[II
I

IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4·BIT and 64 x 5·BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

IDT72401
IDT72403

IDT72402
IDT72404

NC/CE' (1)
IR
SI
Do
Dl
D2

Vee
SO
OR

NC/OI: (2)

00
01

Do
Dl
D2

SI

O2

03

D3
GND

Vee
SO
OR

IR

00
01
O2

03
04

D3
D4
GND

M"R

M"R

DIP/SOIC
TOP VIEW

DIP/SOIC
TOP VIEW

-

§:

fa

~!!; U
z ~g

INDEX
I

I

L....a

:J

4
Do ]5
Dl ]6
SI

I

I

L.J

I

I

I

I

3 2 LJ
1

I

I.

L....I

20

~

0a:
z_ 0

INDEX

Z

I

19
16 [: NC
16 [:

SI :J 4
Do ]5
Dl ]6

14[ O2

D2 ]7
D3 ]6

17 [:
L20-2

D2 ]7
NC ]6
9 10 11 12 13

~g

U U II U U
3 2 LJ 20 19

L.J

OR

00
15[ 0 1

1

L20-2

9

10 11 12 13

nnnnn

nnnnn

oO~OO
z
z

oO~OO
z
z

LCC
TOP VIEW

LCC
TOP VIEW

CJ

CJ

NOTES:
1. Pin 1: NC-No Connection IDT72401
-IDT72403
2. Pin 1: NC-No Connection IDT72402
-IDT72404

rn:
rn:

6-70

16 [:

OR

17 [:

00

16 [:
15[

01
O2

14 [:

03

1DT72401102/03/04 CMOS
PARALLEL FIFO 64 x 4-BIT and 64 x 5-BIT

ABSOLUTE MAXIMUM RATINGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED DC OPERATING CONDITIONS

(1)

RATING

COMMERCIAL

MILITARY

VTERM

Terminal Voltage
with Respect to
GND

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to + 125

°C

TBIAS

Temperature
Under Bias

':'55 to + 125

-65 to +135

°C

Storage
Temperature

-55 to +125

SYMBOL

TSTG

-65 to +150

UNIT

SYMBOL

°C

PARAMETER

MIN.

TYP.

MAX.

UNIT

Vcc

Military
Supply Voltage

4.5

5.0

5.5

V

Vcc

Commercial
Supply Voltage

4.5

5.0

5.5

V
V

GND

Supply Voltage

0

0

0

\IH

Input High Voltage

2.0

-

V

\IL (1)

Input High Voltage

-

-

O.S

V

NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.

50
DC Output Current
mA
50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
(Commercial: Vce
SYMBOL

= S.OV ±10%, TA = O°C to + 70°C; Military: \be = SV ±
PARAMETER

Vie (1)

Input Clamp Voltage

IlL

Low-Level Input Current

10%, TA

= -SSoC to + 12S°C)
MIN.

MAX.

-

-

-

Vee = Max., GND :::;V I :::; Vee

-10

-

~A

TEST CONDITIONS

UNIT

IIH

High-Level Input Current

Vee = Max., GND :::;V I :::; Vee

~A

Low-Level Output Current

Vee = Min., 10L = SmA

-

+10

VOL

0.4

V

'bH

High-Level Output Voltage

Vee = Min., 10H = -4mA

2.4

-

V

los(2)

Output Short-Circuit Current

Vee = Max., Vo = GND

-20

-90

mA

1HZ

Off-State Output Current
(IDT72403 and IDT72404)

Vee = Max., Vo = 2AV

-

+20

~A

Vee = Max., Vo = OAV

-20

-

~A

Vee = Max.: f = 10MHz
Commercial
Military

-

35
45

mA

III
Icc

(3.4)

Supply Current

NOTES:
1. FI FO is able to withstand a -1.5V undershoot for less than 10ns.
2. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
3. Icc measurements are made with outputs open.
4. Forfrequeneies greater than 10MHz, Icc = 35mA + (1.5mA x [f - 10MHzj) commercial, and Icc = 40mA + (1.5mA x [f - 10MHzj) military.

6-71

IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4-BIT and 64 x 5-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING CONDITIONS
(Commercial' Vee = SOV +10% TA = O°Cto +70°C' Military' Vee = SV +
- 10% , TA = -SSOCto + 12S°C)

-

MILITARY AND COMMERCIAL

COMMERCIAL
SYMBOL

PARAMETER

FIGURE

IDT72401 L45
IDT72402L45
IDT72403L45
IDT72404L45
MAX.
MIN.

IDT72401 L35
IDT72402L35
IDT72403L35
1DT72404L35
MIN.
MAX.

t SIH (l)

Shift In HIGH Time

2

9

tSIL

Shift In LOW Time

2

11

-

17

t lDS

Input Data Set-up

2

0

-

0

tlDH
t SOH (l)

Input Data Hold Time

2

13

15

Shift Out HIGH Time

5

9

-

tSOL

Shift Out LOW Time

5

11

tMRW

Master Reset Pulse

8

20

t MRS

Master Reset Pulse to SI

8

10

tSIR

Data Set-up to IR

4

3

tHIR

Data Hold from IR

4

13

tSOR

Data Set-up to OR HIGH

7

0

9

9

-

17
25
10
3
15
0

-

1DT72401 L25
IDT72402L25
IDT72403L25
IDT72404L25
MAX.
MIN.

IDT72401 L 15
IDT72402L15
1DT72403L15
IDT72404L15
MIN.
MAX.

I DT72401 L1 0
IDT72402L10 UNIT
IDT72403L10
IDT72404L1 0
MIN.
MAX.

11

-

11

-

ns

-

25

-

11

24

30

-

ns

0

-

0

-

0

-

ns

20

-

30

40

11

11

20

-

0

-

-

24
25
10
5

25
25
25
5
30
0

11

-

25

-

ns

30

-

ns

ns
ns

ns

30

-

0

-

ns

35
5

ns
ns

AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = S.OV ±10%, TA = O°C to + 70°C; Military: Vee = SV ± 10%, TA = -SSoC to + 12S°C)
COMMERCIAL
SYMBOL

PARAMETER

IDT72401 L45
FIGURE IDT72402L45
IDT72403L45
IDT72404L45
MAX.
MIN.

fiN

Shift In Rate

2

-

45

tlRL (1)

Shift In to Input Ready LOW

2

18

tlRH (1) Shift In to Input Ready HIGH

2

-

5

-

45

5

-

18

5

-

18

Shift Out Rate

fOUT

t ORL (l) Shift Out to Output Ready LOW
t ORH (l) Shift Out to Output Ready HIGH

18

MILITARY AND COMMERCIAL
IDT72401L35
IDT72402L35
IDT72403L35
IDT72404L35
MAX.
MIN.

IDT72401 L25
IDT72402L25
IDT72403L25
IDT72404L25
MIN.
MAX.
25

-

21
28

-

-

25

-

-

34

-

35

-

20

-

35

-

20

18

18

19

tODH

Output Data Hold (Previous Word)

5

5

-

5

-

5

-

t ODS

Output Data Shift (Next Word)

5

20

-

25

-

35

tPT

Data Throughput or "Fall-Through"

-

25

-

28

25

-

28

-

25

-

28

-

35

20

25

12

-

9

-

9

-

4,7

tMRIRH

Master Reset to IR HIGH

8

-

tMRQ

Master Reset to Data Output LOW

8

-

20

t ooe (3) Output Valid from ITE LOW

9

-

12

t

9

-

12

4

9

7

9

tMRoRL Master Reset to OR LOW

Hzoe

(3)

t IPH (2)

Output HIGH-Z from

ITE HIGH

Input Ready Pulse HIGH

t OPH (2) Output Ready Pulse HIGH

8

-

15

IDT72401 L 15
1DT72402L15
1DT72403L15
IDT72404L15
MIN.
MAX.

-

IDT72401L10
1DT72402L10 UNIT
IDT72403L1 0
IDT72404L1 0
MIN.
MAX.

-

10

MHz

35

40

ns

40

-

45

ns

15

-

10

MHz

15

35
40

40

ns

55

ns

5

-

5

-

ns

55

-

55

ns

40

-

65

-

65

ns

35

-

35

-

40

ns

40

ns

-

40

ns

35

ns

30

ns

11

-

ns

11

-

ns

-

35

35

15

-

11

-

11

11

-

11

-

20

30
25

NOTES:
1. Since the FIFO is a very high-speed device, care must be exercised in the design of the hardware and timing utilized within the design. Device grounding
and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capaCitor of 0.1~F directly between Vee and GND with very short lead length is recommended.
2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like
speed grades.
3. IDT72403 and IDT72404 only.

6-72

1DT12401/02/03/04 CMOS
PARALLEL FIFO 64 x 4·BIT and 64 x 5·BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V
3ns

SYMBOL

1.SV
1.SV
See Figure 1

(TA = +2S0C, f

PARAMETER(1)

CIN

Input CapaCitance

COUT

Output Capacitance

= 1.0MHz)

CONDITIONS

MAX.

UNIT

VIN = OV

S

pF

Vour= OV

7

pF

NOTE:

,1. This parameter is sampled and not 100% tested.

SV
ALL INPUT PULSES:
3.0V

-----.,,----_1
OUTPUT

10%
GND----"I
<3ns

10%

<3ns

*Includes jig and scope capacitances.
Figure 1. AC Test Load

SIGNAL DESCRIPTIONS

INPUT READY (IR)

INPUTS:

When Input Ready is HIGH, the FIFO is ready for new input data
to be written to it. When IR is LOW the FIFO is unavailable for new
input data. Input Ready is also used to cascade many FIFOs together, as shown in Figures 10 and 11 in the Applications section.

DATA INPUT (D o-3,4)
Oata input lines. The 10T72401 and 10T72403 have a 4-bit data'
input. The 10T72402 and 10T72404 have a 5-bit data input.

OUTPUT READY (OR)
When Output Ready is HIGH, the output (00-3.4) contains valid
data. When OR is LOW, the FIFO is unavailable for new output
data. Output Ready is also used to cascade many FIFOs together,
as shown in Figures 10 and 11.
OUTPUT ENABLE (OE) (IDT72403 AND 1OT72404 ONLy)

CONTROLS
SHIFT IN (SI)
Shift In controls the input of the data into the FIFO. When ~I is
HIGH, data can be written to the FIFO via the 0 0 - 3 • 4 lines.
SHIFT OUT (SO)
.

Output Enable is used to read FIFO data onto a bus. Output Enable is active LOW.

Shift Out controls the output of data out of the FIFO. When SO is
HIGH, data can be read from the FIF'O via the Oata Output (0 0- 3, 4)
lines.
MASTER RESET (MR)

OUTPUTS
DATA OUTPUT (0 0- 3,4)
Oata Output lines. The 10T72401 and 10T72403 have a 4-bit
data output. The 10T72402 and 10T72404 have a 5-bit data output.

Master Reset clears the FIFO of any data stored within. Upon
power up, the FIFO should be cleared with a Master Reset. Master
Reset is active LOW.

6-73

IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4-BIT and 64 x 5-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

Data Output

These 64 x 4 and 64 x 5 FIFOs are designed using a dual-port
RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer
and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the
Shift In (SI) control; the read pointer is incremented by the falling
edge of the Shift Out (SO). The Input Ready (IR) signals when the
FIFO has an available memory location; Output Ready (OR)..§lgnals when there is valid data on the output. Output Enable (OE)
provides the capability of three-stating the FIFO outputs.
FIFO Reset

Data is shifted out on the HIGH-to-LOW transition of Shift Out
(SO). This causes the internal read pointer to be advanced to the
next word location. If data is present, valid data will appear on the
outputs and Output Aeady (OR) will go HIGH. If data is not present,
Output Aeady will stay LOW indicating the FIFO is empty. The last
valid word read from the FIFO will remain at the FIFO's output
when it is empty. When the FIFO is not empty, Output Aeady (OR)
goes LOW on the LOW-to-HIGH transition of Shift Out. Previous
data remains on the output until the HIGH-to-LOWtransition of Shift
Out (SO).

--"Ihe FIFO must be reset upon power up using the Master Reset
(MR) Signal. This causes the FIFO to enter an empty state, signified
by Output Aeady (OA) being LOW and Input Ready (IA) being
HIGH. In this state, the data outputs (0 0- 3,4) will be LOW.

The FI FO operates in a fall-through mode when data gets shifted
into an empty FIFO. After a fall-through delay the data propagates
to the output. When the data reaches the output, the Output Ready
(OA) goes HIGH. Fall-through mode also occurs when the FIFO is
completely full. When data is shifted out of the full FIFO, a location
is available for new data. After a fall-through delay, the Input Ready
goes HIGH. If Shift In is HIGH, the new data can be written to the
FIFO.
Since these FIFOs are based on an internal dual-port AAM architecture with separate read and write pointers, the fall-through
time (tPT) is one cycle long. A word may be written into the FIFO on
a clock cycle and can be accessed on the next clock cycle.

Fall-Through Mode

Data Input
Data is shifted in on the LOW-to-HIGH transition of Shift In (SI).
This loads input data into the first word location of the FIFO and
causes Input Aeady to go LOW. On the HIGH-to-LOW transition of
Shift In, the write pointer is moved to the next word position and Input Ready (IA) goes HIGH, indicating the readiness to accept new
data. If the FIFO is full, Input Aeady will remain LOW until a word of
data is shifted out.

TIMING DIAGRAMS

.....- - - - - - l/flN - - - - - . r . t - - - - - - - l / f IN -----~

SHIFT IN

INPUT READY

INPUT DATA

Figure 2. Input Timing

6-74

IOT72401/02/03/04 CMOS
PARALLEL FIFO 64 X 4-81T and 64 x 5-81T

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING DIAGRAMS (Continued)

NOTE
SHIFT IN

L

.L NOTE 4

/7"--.. . .

\~--~-----------------

NOTE 1

\J

\.
NOTE 3
NOTE
------t~\_________________J/'-

INPUT READY

INPUTDATA

2'-l

_ _ _ _..I

___ ~~E~~ __

_ _ _ STABLE DATA

NOTES:
Input Ready HIGH indicates space is available and a Shift In pulse may be applied.
Input Data is loaded into the first word.
Input Ready goes LOW indicating the first word is full.
The write pointer is incremented.
The FIFO is ready for the next word.
If the FIFO is full then the Input Ready remains LOW.

1.
2.
3.
4.
5.
6.

NOTE: Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).

Figure 3. The Mechanism of Shifting Data Into the FIFO

SHIFT OUT

NOTE 5.

SHIFT IN

NOTE 1
INPUT READY

~---------- tpT------~--~.--

INPUT DATA

NOTES:
FIFO is initially full.
Shift Out pulse is applied.
Shift In is held HIGH.
As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.
The write pointer is incremented.

1.
2.
3.
4.
5.

Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH

6-75

IDT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4·BIT and 64 x 5·BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING DIAGRAMS (Continued)

......- - - - - 1 / fOUT ----~t------ 1IfOUT -----~

SHIFT OUT

OUTPUT READY

OUTPUT DATA

A-DATA

C-DATA

NOTE 1

NOTES:
1. This data is loaded consecutively A. 8. C.
2. Data is shifted out when Shift Out makes a HIGH to LOW transition.
Figure 5. Output Timing

NOTE 2
SHIFT OUT (7)

OUTPUT READY

NOTE 3

NOTE 1

- - - - -,
OUTPUT DATA

~

A-DATA

~~T~;-

- --

8-DATA

----------------------------------~'~\~----------------NOTES:
1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.
2. Shift Out goes HIGH causing the next step.
3. Output Ready goes LOW.
4. Read pointer is incremented.
5. Output Ready goes HIGH indicating that new data (8) is now available at the FIFO outputs.
6. If the FIFO has only one word loaded (A DATA) then Output Ready stays LOW and the A DATA remains unchanged at the outputs.
7. Shift Out pulses applied when Output Ready is LOW will be ignored.

Figure 6. The Mechanism of Shifting Data Out of the FIFO

6-76

IOT72401/02/03/04 CMOS
PARALLEL FIFO 64 X 4-BIT and 64 X 5-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING DIAGRAMS (Continued)
SHIFT IN

SHIFT OUT

OUTPUT READY

DATA OUTPUT

NOTE:
1. FIFO initially empty.

~

NOTE 1
...............-------tPT---""''''''''''''''''--f to PH
-'1______________________________________________

~

~

_________

4----------------------------~~~~~----------DATA VALID

Figure 7. tpT and toPH Specification

MASTER RESET

~....................-

INPUT READY
NOTE 1

tMRIRH - - - -.....~Ir----------'"'"

~-------tMRORL--------.....~

OUTPUT READY
....- - - -.....-

t MRS - - - - + I _ - - - - - - - - - - - - - - - - - - - - -

SHIFT IN

tMRQ ..........--..........-+1
DATA OUTPUT

NOTE:
1. Worst case, FIFO initially full.
Figure 8. Master Reset Timing

OUTPUT ENABLE

DATA OUT

NOTE:
1. High-Z transitions are referenced to the steady-state VOH - 500mV and VOL
instead of 30pF as shown in Figure 1.

+ 500mV levels on the output. ~ZOE is tested with 5pF load capacitance

Figure 9. Output Enable Tlmlng,10T72403 and 10T72404 Only

6-77

JDT72401/02/03/04 CMOS
PARALLEL FIFO 64 X 4-BIT and 64 x 5-BIT

MILITARY AN D COM MERCIAL TEM PERATU RE RANGES

APPLICATIONS

SI
IR
Do
Dl
D2
D3

SHIFT IN
INPUT READY

DATA OUT {

SI
IR
Do
Dl
D2
D3

OR
SO

00
01

tm

O2
03

1

"

~

OUTPUT READY
SHIFT OUT

OR
SO

00
01

} DATAOUT

O2
03

tm

Y

NOTE:
1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing ofthe
devices.
Figure 10. 128 x 4 Depth Expansion

IR
SI
Do
Dl
D2
D3

I ~,..
~~

SO
OR

IR
SI
Do
Dl
D2
D3

00
01

tm

O2
03

SO
OR

00
01

tm

O2
03

IR
SI
Do
Dl
D2
D3

SO
OR

SHIFT OUT

00
01

O2
03

tm

COMPOSITE
INPUT READY
IR
SI
Do
Dl
D2
D3

SHIFT IN

IR
SI
Do
Dl
D2
D3

SO
OR

IR
SI
Do
Dl
D2
D3

00
01

tm

O2
03

SO
OR

00
01

tm

IR
SI
Do
Dl
D2
D3

00
01

tm

SO
OR

O2
03

O2
03

SO
OR

00
01

JVfR'

O2
03

IR
SI
Do
Dl
D2
D3

IR
SI
Do
Dl
D2
D3

SO
OR

00
01

O2

JVfR'

. 03

SO
OR

00
01

tm

O2
03

t1R

,
NOTES:
1. When the memory is empty. the last word read will remain on the outputs until the Master Reset is strobed or a new data word falls through to the output.
However. OR will remain LOW. indicating data at the output is not valid.
2. When the output data changes as a result of a pulse on SO. the a R signal always goes LOW before there is any change in output data and stays LOW
until the new data has appeared on the outputs. Anytime OR is HIGH. there is valid stable data on the outputs.
3. If SO is held HIGH while the memory is empty and a word is written into the input. that word will appear aHhe output after a fall-through time. OR will go
HIGH for one internal cycle (at leastt ORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the
FIFO. they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.
4. When the Master Reset is brought LOW. the outputs are cleared to LOW. IR goes HIGH and OR goes LOW. If SI is HIGH when the Master Reset goes
HIGH. the data on the inputs will be written into the memory and IR will returntothe LOW state until Slis brought LOW. If SI is LOWwhen the Master Reset
is ended. IR will go HIGH. but the data on the inputs will not enter the memory until SI goes HIGH.
5. FIFOs are expandable in depth and width. However. in forming wider words. two extemal gates are required to generate composite Input and Output
Ready flags. This is due to the variation of delays of the FIFOs.
~

Figure 11. 192 x 12 Depth and Width Expansion

6-78

IOT72401/02/03/04 CMOS
PARALLEL FIFO 64 x 4·BIT and 64 x 5·BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

lOT

DeV~ype

xx

X

Package

Process/
Temperature
Range

y:'Mk

'---------1\I~~O
L -..................................................~

L -.........._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~I

45
35
25

+70°C)

Military (-55°C to + 125°C)
Compliant to MIL·STD·883, Class B

CERDIP
Leadless Chip Carrier
Plastic Dip
Small Outline IC
Commercial Only

15
10
L
Low Power

I

--1 72401
72402

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

72403
72404

6-79

Commercial (O°C to

64x4 FIFO
64 x 5 FIFO

64 x 4 FIFO with Output Enable
64 x 5 FIFO with Output Enable

FEATURES:'

DESCRIPTION:

• First-In/First-Out dual-port memory-45MHz

The 10T72413 is a 64 x 5, high-speed First-In/First-Out (FIFO)
that loads and empties data on a first-in/first-out basis. It is expandable in bit width. The 10T72413 25MHz and 35MHz versions are
cascadable in depth.
The FIFO has a Half-Full Flag, which signals when it has 32 or
more words in memory. The Almost-Full/Empty Flag is active
when there are 56 or more words in memory or when there are 8 or
less words in memory.
The 10T72413 is pin and functionally compatible to the MMI
67413. It operates at a shift rate of 45MHz. This makes it ideal for
use in high-speed data buffering applications. The IDT72413 can
be used as a rate buffer, between two digital systems of varying
data rates, in high-speed tape drivers, hard disk controllers, data
communications controllers and graphics controllers
The 10T72413 is fabricated using lOT's high-performance
CEMOS process. This process maintains the speed and high
output drive capability of TTL circuits in low-power CMOS.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

• 64 x 5 organization
• Low power consumption
- Active: 200mW (typical)
• RAM-based internal structure allows for fast fall-through time
• Asynchronous and simultaneous read and write
• Expandable by bit width
• Cascadable by word depth at 25MHz and 35MHz
• Half-Full and Almost-Full/Empty status flags
• 10T72413 is pin and functionally compatible with the M MI67413
• High-speed data communications applications
\

• Bidirectional and rate buffer applications
• High-performance CEMOS ™ technology
• Available in plastic DIP, CEROIP, LCC and SOIC
• Military product compliant to MIL-STO-883, Class B

PIN CONFIGURATION

t>E

Vee

HF
IR
SI
Do

AF/E

FUNCTIONAL BLOCK DIAGRAM

OUTPUT ENABLE
(l5E')

so
OR

01

00
01

O2

O2

03

03
04
tm

04

GND

FIFO
INPUT
STAGE

64x 5
MEMORY
ARRAY

INPUT
CONTROL
LOGIC

REGISTER
CONTROL
LOGIC

FIFO
OUTPUT
STAGE

DATA OUT
(0 0- 4 )

MASTER
RESET

DIP/SOIC
TOP VIEW

LCC
(CONSULT FACTORy)

FLAG
CONTROL
LOGIC

L20-2

OUTPUT
(SO) 5~~FT
CONTROL
LOGIC
OUTPUT
~_ _.... (OR) READY

HALF-FULL (HF)
ALMOST-FULL!
EMPTY (AF/E)

CEMOS is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Inlegraled Device Technology. Inc.

DECEMBER 1987
DSC-2015/-

6-80

1OT12413 CMOS PARALLEL
64 x 5-BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL

COMMERCIAL

RATING

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TslAs

Temperature
Under Bias

-55 to +125

Storage
Temperature

-55 to +125

TSTG

RECOMMENDED DC OPERATING CONDITIONS
MILITARY

UNIT

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

4.5

5.0

5.5

V

-0.5 to +7.0

-0.5 to +7.0

V

VCCM

Military
I
Supply Voltage

Oto +70

-55 to +125

°C

Vccc

Commercial
Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H

Input
High Voltage

2.0

-

-

V

VIL(l)

Input
Low Voltage

-

-

O.S

V

-65 to +135
-65 to +150

°C
°C

DC Output Current
50
50
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
(Commercial: Vee = 5V ±10%. TA =O°Cto +70°C. Military: Vcc ~ 5V ±10%. TA = -55°C to + 125°C)
SYMBOL

PARAMETER

"IC(l)

Input Clamp Voltage

IlL

Low-Level Input Current

IIH

High-Level Input Current

TEST CONDITIONS

= Max.; GND -5:V,
Vee = Max.; GND -5:V,
Vec

VOH
los (3)
1HZ

ILZ
lee (4)

Low-Level Output Voltage

High-Level Output Voltage
Output Short-Circuit Current
Off-State Output Current

Vee

Vee

= Min.

Vec

-

-

J.lA

-5: Vee

-

10

J.lA

-

0.4

V

2.4

-

V

-20

-90

mA

-

+20

-20

-

J.lA

-

70

mA

I MIL.
I COM'L

12mA
24mA

10L (lR. OR)(2)

SmA

10L (HF. AF/E)

SmA

10H (0 0 - 4 )

-4mA

10H (IR, OR)

-4mA

10H (HF, AF/E)

-4mA

Vo = OV
Vo = 2.4V
= Max.
Vo = O.4V
= Max.
= Max. Inputs LOW, Outputs Open,

Vee
f = 25MHz

UNIT

-10

Vee = Max.
Vec

Supply Current

= Min.

MAX.

-5: Vec

10L (00-4)
VOL

MIN.

MIL.
COM'L.

60

mA
NOTES:
1. FI FO is able to withstand a -1.5V undershoot for less than 10ns.
2. Care should be taken to minimize as much as possible the DC and capacitive load on IR and OR when operating atfrequeneies above"25MHz.
3. Not more than one output should be.shorted at a time and duration of the short circuit test should not exceed one second.
4. Frequencies greater than 25M Hz, I~ = 60mA + (1.5mA x [f - 25M Hz]) commercial and Icc = 70mA + (1.5mA x [f - 25M Hz]) military.

6-81

IDT72413 CMOS PARALLEL
64 x 5-BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING CONDITIONS
(Commercial: Vee = SV ±10%, TA =O°Cto +70°C, Military: Vce = SV ±10%,lA = -SSOCto + 12S°C)
COMMERCIAL

MILITARY AND COMMERCIAL
PARAMETER

SYMBOL
tSIH(I)
tSll(l)
tlDS
tlDH
tSOH(I)
tsol
tMAW
tMAS

Shift In HIGH Time
Shift In LOW Time
Input Data Set-Up

2

9

2
2

11
0

Input Data Hold Time

2
5
5

13

8
8

20
20

Shift Out HIGH Time
Shift Out LOW Time
Master Reset Pulse
Master Reset to SI

IDT72413L35
MAX.
MIN.

IDT72413L45
MAX.
MIN.

FIGURE

-

9
11

IDT72413l25
MAX.
MIN.

UNIT

9

-

16

-

ns

17
0

-

20
0

ns
ns

15

-

25

-

9

-

17

-

16
20

30

-

35

-

-

35
35

ns
ns
ns
ns
ns

AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = SV ±10%, TA =O°Cto +70°C, Military: Vec = SV ±10%, TA = -SSOCto + 12S°C)
COMMERCIAL

MILITARY AND COMMERCIAL
SYMBOL

PARAMETER

FIGURE

1DT72413L45
MIN.
MAX.

fiN

Shift In Rate
Shift In

to Input Ready LOW

2

-

45

tlAl (1)
t IAH (I)

Shift In ~ to Input Ready HIGH

2

-

18

fOLrr

Shift Out Rate

5

-

45

t OAl(l)

Shift Out ~ to Output Ready LOW

5

-

18

tOAH (1)

Shift Out ~ to Output Ready HIGH

5

-

18

t ODH (I)

Output Data Hold Previous Word

5

5

-

t ODS

Output Data Shift Next Word

5

-

tPT

Data Throughput or "Fall-Through"

4,7

-

tMAOAl

Master Reset ~ to Output Ready LOW

8

-

25

tMAIAH

Master Reset

8

-

25

tMAIAl(2)

Master Reset ~ Input Ready LOW

8

-

25

tMAQ

Master Reset ~ to Outputs LOW

8

-

20

tMAHF

Master Reset ~ to Half-Full Flag

8

-

tMRAFE

Master Reset ~ to AF/E Flag

8

-

t lPH

Input Ready Pulse HIGH

4

5

t OPH

Output Ready Pulse HIGH

7

t

2

t to Input Ready HIGH

t HIGH to Valid Data
t to AF/E HIGH

t ORo

Output Ready

5

9

tAEH

Shift Out

tAEl

Shift In

9

tAFl

Shift Out

10

tAFH
tHFH
tHFl
tpHz
tpLZ
t pZL
tpZH

t to AF/E
t to AF/E LOW
Shift In t to AF/E HIGH
Shift In t to HF HIGH
Shift Out t to HF LOW

10
11
11
12

Output Disable Delay
Output Enable Delay

12
12
12

IDT72413L35
MAX.
MIN.

IDT72413l25
MIN.
MAX.

UNIT

35

-

25

MHz

18

28

ns

35

-

-

18

-

20

5

-

20

-

20

25

28

25

-

25

5

5

-

-

5

-

5

-

7

ns

28

28

-

40

ns

28

-

40

ns

28

40

ns

28

-

40

ns
ns

18

-

5

20

25

ns

25

MHz

-

28

ns

-

25

ns

5

-

ns

-

20

ns

40

ns

-

30

ns

28

30

ns

28

-

30

ns

25

-

35

ns

28

-

40

ns

28

-

40

ns

-

5

-

ns

5

-

ns

28

-

28

-

28

-

28

-

28

-

40

-

28

-

28

ns

-

12

15

ns

12

-

12

-

40

12

15

ns

28

15
15

15
15

20

ns

20

ns

NOTES:
1. Since the FIFO is a very high-speed device. care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and
decoupling is crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines. high capacitances and/or poor supply
decoupling and grounding. A monolithic ceramic capacitor of 0.1JJF directly between Vee and GND with very short lead length is recommended.
2. If the FIFO is not full. (IR = HIGH). MA~ forces IR to go LOW. and MAt causes IR to go HIGH.

6-82

1DT12413 CMOS PARALLEL

64 x S-BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

STANDARD TEST LOAD

AC TEST CONDITIONS

DESIGN TEST LOAD

GND to3.0V

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

SV

SV

3ns
1.SV
1.SV
See Figure 1

2KO

OUTPUT

CAPACITANCE
SYMBOL
CIN

(TA= +2S0C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance

CONDITIONS
VIN = OV

COUT
VOUT= OV
Output Capacitance
NOTE:
1. This parameter is sampled and not 100% tested.
2. Characterized values, not currently tested.

MAX.

UNIT

S

pF

7

pF
*Includes jig and scope capacitances.

RESISTOR VALUES FOR STANDARD TEST LOAD

IoL

R1

R2

24mA

2000

3000

12mA

3900

7600

8mA

6000

12000

Figure 1. Output Load

FUNCTIONAL DESCRIPTION:

DATA OUTPUT

The 10172413,65 x 5 FIFO is designed using a dual-port RAM
architecture as opposed to the traditional shift register approach.
This FIFO architecture has a write pointer, a read pointer and controllogic, which allow simultaneous read and write operations. The
write pointer is incremented by the falling edge of the Shift In (SI)
control; the read pointer is incremented by the falling edge of the
Shift Out (SO). The Input Ready (IR) signals when the FIFO has an
available memory location; Output Ready (OR) s.!9!lals when there
is valid data on the output. Output Enable (OE) provides the
capability of three-stating the FIFO outputs.

Data is shifted out on the HIGH-ta-LOW transition of Shift Out
(SO). This causes the internal read pointer to be advanced to the
next word location. If data is present, valid data will appear on the
outputs and Output Ready (OR) will go HIGH. If data is not present,
Output Ready will stay LOW indicating the FIFO is empty. The last
valid word read from the FIFO will remain at the FIFO's output
when it is empty. When the FIFO is not empty, Output Ready (OR)
goes LOW on the LOW-to-HIGH transition of Shift Out.

FIFO RESET

The FIFO operates in a Fall-Through Mode when data gets
shifted into an empty FIFO. After the fall-through delay the data
propagates to the output. When the data reaches the output, the
Output Ready (OR) goes HIGH.
A Fall-Through Mode also occurs when the FIFO is completely
full. When data is shifted out of the full FIFO, a location is available
for new data. After a fall-through delay, the Input Ready goes HIGH.
If Shift In is HIGH, the new data can be written to the FIFO. The fallthrough delay of a RAM-based FIFO (one clock cycle) is far less
than the delay of a shift register-based FIFO.

FALL-THROUGH MODE

-.!he FIFO must be reset upon power up using the Master Reset
(MR) signal. This causes the FIFO to enter an empty state signified
by Output Ready (OR) being LOW and Input Ready (IR) being
HIGH. In this state, the data outputs (00-4) will be LOW.

DATA INPUT
Data is shifted In on the LOW-ta-HIGH transition of Shift In (SI).
This loads input data into the first word location of the FIFO and
causes the Input Ready to go LOW. On the HIGH-ta-LOWtransition
of Shift In, the write pointer is moved to the next word poSition and
Input Ready (IR) goes HIGH indicating the readiness to accept new
data. Ifthe FIFO is full, Input Ready will remain LOW until a word of
data is shifted out.

6-83

IDT72413 CMOS PARALLEL
64 x S-BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

INPUT READY (IR)

SIGNAL DESCRIPTIONS:

When Input Ready is HIGH. the FIFO is ready for new input data
to be written to it. When IR is LOW. the FIFO is unavailable for new
input data. Input Ready is also used to cascade many FIFOs
together. as shown in Figure 13 in the Applications section.

INPUTS:
DATA INPUT (00-4)
Data input lines. The IDT72413 has a 5-bit data input.

OUTPUT READY (OR)
When Output Ready is HIGH. the output (00-4) contains valid
data. When OR is LOW. the FIFO is unavailable for new output
data. Output Ready is also used to cascade many FIFOs together.
as shown in Figure 13 in the Applications section.

CONTROLS:
SHIFT IN (SI)
Shift In controls the input of the data Into the FIFO. When SI is
HIGH. data can be written to the FIFO via the D0-4 lines. The data
has to meet set-up and hold time requirements with respect to the
rising edge of SI.
SHIFT OUT (SO)

. OUTPUT ENABLE (OE)
Output Enable is used to enable the FIFO outputs onto a bus.
Output Enable is active LOW.

ALMOST-FULl/EMPTY FLAG (AFE)

Shift Out controls the output data from the FIFO.
MASTER RESET (MR)

Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or
more words) or 1/8 from empty (8 or less words).

Master Reset clears the FIFO of any data stored within. Upon
power uP. the FIFO should be cleared with a Master Reset. Master
Reset Is active LOW.
HALF-FULL FLAG (HF)

OUTPUTS:
DATA OUTPUT (00-4)
Data output lines. three-state. The IDT72413 has a 5-bit output.

Half-Full Flag signals when the FIFO has 32 or more words in it.

TIMING DIAGRAMS

1+------ 1/f1N - - - - - o I 4 - - - - - - 1 / f I N -----~
SHIFT IN

INPUT READY

INPUT DATA

Figure 2. Input Timing

6-84

IDT72413 CMOS PARALLEL
64 x 5-BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING DIAGRAMS (Continued)

NOTE 2
SHIFT IN (7)

NOTE 1
INPUT READY

INPUT DATA

-=

NOTE 5

NOTE 3

NOTE 6
' _ _ _ _ _ _ _ _ _ _ _ _ _ _J - - - - - - - ' : . . . . - -

STABLE DATA

NOTES:
1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied.
2. Input Data is loaded into the FIFO.
3. Input Ready goes LOW indicating the FIFO is unavailable for new data.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full, then the Input Ready remains LOW.
7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4).

Figure 3. The Mechanism of Shifting Data Into the FIFO

SHIFT OUT

NOTE 5

SHIFT IN

INPUT READY

I 'I"".1---------

NOTE

NOTE

\k
~.,..-

tpT - - - - - - - -....

INPUT DATA

t lPH - \ " '_ _ _ _ _ _ _ __

STABLE D A T A - - - = - -

NOTES:
1. FIFO is initially full.
2. Shift Out pulse is applied.
3. Shift In is held HIGH.
4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented. Shift In should not go LOW until (t PT + t IPH ).
Figure 4. Data Is Shifted In Whenever Shift In and Input Ready are Both HIGH

6-85

1DT72413 CMOS PARALLEL
64 X 5-81T FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING DIAGRAMS (Continued)

1+------ 1IfOUT ------14------ 1IfOUT - - - - - . . . . ;
SHIFT OUT

OUTPUT READY

C-DATA

OUTPUT DATA
NOTE 1

NOTES:
1. This diagram is loaded consecutively, A, B, C.
2. Output data changes on the falling edge of SO after a valid Shift Out sequence, i.e., OR and SO are both high together.

Figure 5. Output Timing

NOTE 4
SHIFT OUT(1)

OUTPUT READY

NOTE 3

NOTE 1

- - - - -"
OUTPUT DATA

'fIJJJlI!jJjjjJ

A-DA T A

~;-T;;-

- --

B-DATA

----------------------------------~'~'-------------------

NOTES:
1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.
2. Shift Out goes HIGH causing the next step.
3. Output Ready goes LOW.
4. Read pointer is incremented.
5. Output Ready goes HIGH indicating that new data (8) will be available at the FIFO outputs after tClAOns.
6. If the FIFO has only one word loaded (A-DATA), Output Ready stays LOW and the A-DATA remains unchanged at the outputs.
7. Shift Out pulses applied when Output Ready is LOW will be ignored.

FIgure 6. The MechanIsm of ShIftIng Data Out of the FIFO

6-86

1OT72413 CMOS PARALLEL
64 x 5·BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING DIAGRAMS (Continued)

SHIFT IN

SHIFT OUT

~........................................-tPT""'''''''''''''''''''''''''''''''''''''''''~
OUTPUT READY

NOTE 1

______________________________________~

~/

.

~

tOPH~~-------

NOTE:
1. FIFO initially empty.

Figure 7. tpT and tOPH Specification

MASTER RESET

INPUT READY

OUTPUT READY

...............-tMRS--------~~___________________

~

SHIFT IN

DATA OUTPUTS

HALF·FULL FLAG

ALMOST FULU
EMPTY FLAG

NOTE:
1. FIFO is partially full.

Figure 8. Master Reset Timing

6-87

IDT72413 CMOS PARALLEL
64 x 5-BIT FI FO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING DIAGRAMS (Continued)
SHIFT OUT

ALMOST FULUEMPTY

SHIFT IN

1. FIFO contains 9 words (one more than Almost-Empty).
Figure 9. tAEH and

tAEL

Specifications

SHIFT IN

ALMOST FULUEMPTY

SHIFT OUT
NOTE:
1. FIFO contains 55 words (one short of Almost-Full).

Figure 10. tAFH and tAFL Specifications

SHIFT IN

HALF-FULL

SHIFT OUT

1 4 - - - - - t HFL - - - - - . !
NOTE:
1. FIFO contains 31 words (one short of Half·Full).

Figure 11. tHFL and tHFH Specifications

3V

OV
1.5V

WAVEFORM 1 (1)

VOL

WAVEFORM

VOH

2(2)

1.5V

NOTES:

1. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
2. Waveform 2 Is for an output with internal conditions such that the output is high except when disabled by the output control.
Figure 12. Enable and Disable

6-88

1OT72413 CMOS PARALLEL
64 x 5-BIT FIFO WITH FLAGS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

APPLICATIONS

COMPOSITE
INPUT READY

HFOE"
1---+-4---1 IR
SI
Do

AF/E
SO
OR I - - - i - + - - - i

D1
D2
D3
D4 M"R"

HFOE
IR
SHIFT IN - -.....--ISI
Do

D1
D2
D3
D4

COMPOSITE
OUTPUT READY

~
~

~

°4

AF/E
SO
OR 1----+-'

~
~

~

Cl.3

MFI

°4
MASTER RESET

NOTE:
1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This
requirement is due to the different fall-through times of the FIFOs.

Figure 13. 64x15 FIFO with IOT72413

8-BITS

8-BITS

TWO

SYSTEM 1

SYSTEM 2

IDT72413
64x8
I----~

SI

S O t - - -.......
OR 14-----1 10 RDY

ENBL SII4-----4 IR

INTERRUPT

INTERRUPT

HALF-FULL FLAG

NOTE:
1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13.

Figure 14. Application for IDT72413 for Two Asynchronous Systems

6-89

IDT72413 CMOS PARALLEL
64 x 5-BIT FIFO WITH FLAGS

SHIFT IN
INPUT READY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SI
IR
Do
D1
D2
D3
D4

SI
IR

OR
SO
00
01
O2
03

Do
D1
D2
D3
D4

04

fVffi

OUTPUT READY
SHIFT OUT

OR
SO
00
01
O2
03

fVffi

}

DATAO~

04

y

1

NOTE:
1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.
Figure 15.128x5 Depth Expansion

ORDERING INFORMATION

xx

X

Package

Processl
Temperature
Range

y:Wnk

P
D
L...----------I L
SO
45

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic Dip
CERDIP
Leadless Chip Carrier
Small Outline IC
Commercial Only

L...------------~35

} Shift Frequency (MHz)

25
'-----------------~

'----------------------1

6-90

L

Low Power

72413

64 x 5-Bit FIFO with Flags

--------------,--

.----

quadruple system throughput performance of the peripheral interface by eliminating inefficiencies associated with widely varying,
mismatched bus widths. The BiFIFO can handle data transfers between 16-bit to 8-bit buses and 32-bit to 8-bit buses.
The BiFIFO can be accessed on either side by a microprocessor
or bit-slice machine. It contains a1 Kx18-bit FIFO in both directions.
The 8-bit port views a 2Kx9-bit FIFO instead of a 1Kx18-bit FIFO.
The ninth bit of this FIFO is available for control or parity and can be
stored in the FIFO array or parity can be checked or generated. A
unique data bypass mode allows for synchronous communication
between two devices for initialization. Later asynchronous communications can occur via the FIFOs.
To ease connection to peripherals and reduce parts count, a
requesVacknowledge-type handshake is included. that utilizes
Request (REO) and Acknowledge (ACK) signals. A microprocessor-type interface generates read and write strobes and accesses
the internal read and write pointers.
Four status flags can be programmed to access anyone of eight
internal flags. Four Full/Empty Flags can be chosen, as well as four
Full + Offset or Empty + Offset Flags. The offset value can be determined by the user. The polarity of the flags can also be set by the
user.
The BiFIFO has an innovative Reread (RER) and Rewrite (REW)
capability. The internal read and write pointers can be set to a position determined by the user through a control register. Then, upon
signalling the RER input, the read pointer is reset to the initial position and data is read again. With signalling REW, the write pointer is
reset to the initial position and data is written again.
The BiFIFO is available in a 48-pin DIP, 48-pin 70 mil center
SHRINK-DIP and surface mount 52-pin LCC and PLCC packages.
Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B.

FEATURES:
• Bidirectional First-In/First-Out (FIFO) memory
• Back-to-back 1Kx18-bit and 2Kx9-bit FIFO organization
• Facilitates processor-to-peripheral and processor-to-processor
communication
• Matches mixed bus widths: 16-bit to 8-bit buses and 32-bit to
8-bit buses
• Easy interface to microprocessor bus
• Asynchronous and simultaneous read and write operations
• Parity check and generate
• Convenient requesVacknowledge interface program option for
interface to peripherals
• Eight software programmable status Empty/Full Flags (offset
and polarity) selectable onto four output pins
• Typical interface applications include microprocessor to
floppy/hard disk controllers, microprocessor to SCSI bus,
microprocessor to Local Area Network (LAN) controllers and
microprocessor to 8-bit microcontroller
• Available in 48-pin DIP, and 70 mil center SHRINK-DIP and
surface mount 52-pin LCC and PLCC
• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
FIFOs are used to link microprocessors and peripherals
together asynchronously for sending and receiving data and commands. Often the data or commands must be sent in both directions. The IDT7252 BiFIFO is a compact, highly integrated solution
to simplifying data transfer between two processors or a processor
and peripheral of different bus bandwidths. Using the BiFIFO can

FUNCTIONAL BLOCK DIAGRAM
B PORT
ACCESS
CONTROL

APORT
ACCESS
CONTROL

REREAD
[)SB

R/WB
REWRITE

DATAA~~1~B~~------------------------~

FLAGA
FLAG B
FLAG c
FLAG D

PROGRAMMABLE
FLAG
LOGIC

HAND
SHAKE
INTERFACE
CONTROL

REO
ACK
CLK

CEMOS and BiFIFO are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
D5C-2016/-

6-91

DESCRIPTION:

FEATURES:

The IDT7M203/204 are FIFO memory modules that utilize a
special First-In, First-Out algorithm that loads and empties data
on a first-in, first-out basis. The device uses full and empty flags
to prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
The reads and writes are internally sequential through the use
of ring pointers, with no address information required to load and
unload data. Data is toggled ipand out of the device through the
use of the WRITE (W),,:and READ (R) pins. The device has a
•
read/write cycle time of 6505 (15MHz) for commercial and 70ns
•
(14M Hz) for militar9:temperature ranges.
•
The device utiIl2e~a~-bit wide data array to allow for control
•
and parity bits:afthe user's option. This feature is especially
useful in datci'comriHl'nications applications where it is necessary
•
to use a parity bit for transmission/reception error checking.
• Pin compatible with I DT7201 and Mostek MK4501, but with four
The IIj'T7M~03/204 are constructed on a multi-layered ceramic
times word depth (IDT7M203S) or eight times (IDT7M204S)
subst~~te\.ising four IDT7201 (512x9) or four IDT7202 (1 Kx9)
• Module available with semiconductor components 100%
FIFbs in\ lead less chip carriers. Extremely high speeds are
screened to MIL-STD-883, Class B
~Ctl'1eved lin th is fash ion due to the use of I DT7201s and IDT7202s
«abt'icated in lOT's high-performance CEMOS technology.
.,.,.:10':'5 military FIFO modules have semiconductor components
",,>jOO% processed to the test methods of MIL-STD-883, Class B,
"'::::'rnaking them ideally suited to applications demanding the
PIN CONFIGURATION
highest level of performance and reliability.
Vcc
W
08
04

•
•
•
•
•
•
•

First-In, First-Out memory module
2K x 9 organization (IDT7M203S)
4K x 9 organization (IDT7M204S)
Low-power consumption
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Assembled with lOT's high-reliability vapor phase solder reflow
process
Single 5V (±10%) power supply
Master/slave multiprocessing applications
Bidirectional and rate buffer applications
Empty and full warning flags
High-performance CEMOS™ technology

03

05

02

06

01

07

FUNCTIONAL BLOCK DIAGRAM
,"\,

:;,;,:,\,i:'~:.""""

DO

Xi

i"

00-08
00-08

W
Xo

;'~"i;::",'"

FF
00
01

R

T

RS

l..L

XI -

,07,.""''''''

os\
a5

02
03
08
GNO

I

Xo-

IDT7201/2

IDT7201/2

04

XI

Fe

XI

"'£-ur.

R
DIP
TOP VIEW

'-'-

xo

IDT7201/2

PIN NAMES

L-

W=
WRITE

FL =
FIRST LOAD

XI =
EXPANSION IN

EF =
EMPTY FLAG

R=
READ

D=
DATA IN

XO =
EXPANSION
OUT

Vee =
5V

RS =
RESET

Q=
DATA OUT

FF =
FULL FLAG

GND =
GROUND

Fe

XI

,~
I

vcc

Fe

ELn

II

lr-L7aU

1

Fe

J1...E"!r-

xO

IDT7201/2

~ X, FL ~

JU"!-

~U

-~
-

'--

DUAL 4-INPUT OR GATE

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1986 Integrated Device Technology. Inc.

6-92

JULY 1986
Print"id in U.S.A.

DESCRIPTION:

FEATURES:
• First-In/First-Out memory module
• 8K x 9 organization (IDT7M20SS)
•
•

•
•
•.
•
•
•
•
•
•
.•

The IDT7M20SS/206S are FIFO memory modules constructed
on a multi-layered ceramic substrate using four IDT7203 (2K x 9) or
four IDT7204 (4K x 9) FIFOs in lead less chip carriers. Extremely
16K x 9 organization (IDT7M206S)
high speeds are achieved in this fashion due to the use of IDT7203s
Low power consumption
and IDT7204s fabricated in IDT's high-performance CEMOS technology. These devices utilize a special First-In/First-Out algorithm
_ Active: 840mW (typo Com'l.)
that loads and empties data on a first-in/first-out basis. The device
- Power Down: 176mW (max. Com'l)
uses Full and Empty flags to prevent data overflow and underflow
Asynchronous and simultaneous read and write
and expansion logic to allov:-' for unlimited expansion capability in
both word size and dept\'l. ':""
Fully expandable by both word depth and/or bit width
The reads and writ~~are internally sequential through the use of
Assembled with IDT's high-reliability vapor phase solder reflow
ring pointers, with no add~ss information required to load and unprocess
load data. Data is!oggled in and out of the device through the use
Single SV (t10%) power supply
of the WRITE (~}:af'lci, READ fR) pins. The devices have a read/
MASTER/SLAVE multiprocessing applications
write cycle ti~e()f?Qns (2SMHz) for commercial and 6Sns (1SMHz)
for military,temperature ranges.
Bidirectional and rate buffer applications
The deylc~slJHlize a 9-bit wide data array to allow for control and
Empty and Full warning flags
paritybits~t,!he' user's option. This feature is especially useful in
High-performance CEMOS ™ technology
data;~ommlinications applications where it is necessary to use a
P~~itY bit for transmission/reception error checking.
Pin-compatible with IDT7201 and Mostek MK4S01, but with 16
l/IDT'~ Military FIFO modules have semiconductor components
.,;,:manl".lfactured in compliance with tho latost rovlslon ot MIL.
times word depth (IDT7M20SS) or 32 times (IDT7M206S)
Moduie available with semiconductor components compliantto
 10MHz

-

-

6

-

-

S

mAl
MHz

VOH

Output High Voltage

Vee = Min., IOH = -2.0mA

2.4

-

-

2.4

V

Output Low Voltage

Vcc = Min., IoL = SmA

-

-

0.4

-

-

-

VOL

0.4

V

J..LA

NOTE:
1. Typical implies Vee = 5V and TA = + 25°C.
2. Icc is measured at 10MHz and \IN= Oto 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range: lee = SO +
6(f - 10)mA, where f = operating frequency in MHz. For the military range, Icc = 100 + S(f - 10) where f = operating frequency in MHz, f = 1/tMA"
3. For frequencies greater than 10MHz.

7-3

IDT7209L 12 x 12-BIT PARALLEL
CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS - SLOW
(Commercial Vee= 5V ±10%, TA = O°C to + 70°C, Military Vec= 5V ±10%, TA = -55°C to + 125°C
for Commercial clocked multiply times of 100, 135ns or Military, 120, 170ns)
SYMBOL

COMMERCIAL
MILITARY
TYPJ1) MAX. MIN. TYp.!1) MAX.
MIN.

TEST CONDITIONS

PARAMETER

UNIT

Ilu l

Input Leakage Current

Vcc = Max., VIN = OV to Vcc

-

-

2

-

-

10

IILOI

Output Leakage Current

Hi Z, Vcc = Max., VOUT = 0 to Vcc

-

-

2

-

-

10

j.lA

Icc (2)

Operating Power Supply Current

Outputs Open Measured at 10MHz(2)

-

30

60

-

30

80

mA

lecQ1

Quiescent Power Supply Current

\'IN ~ VIH , V 1N :S;VIL

-

10

30

-

10

30

mA

ICCQ2

Quiescent Power Supply Current

\'IN 2: Vcc -0.2V, VIN :s; 0.2V

-

0.1

1.0

-

0.1

2.0

mA

Icc /f(2.3)

Increase in Power
Supply CurrenVMHz

Vcc = Max., f > 10MHz

-

-

5

-

-

7

VOH

Output High Voltage

Vcc = Min.,

VOL

Output Low Voltage

IoH

= -2.0mA

Vcc = Min., 10L = 8mA

J.lA

mAl
MHz

2.4

-

-

2.4

-

-

V

-

-

0.4

-

-

0.4

V

NOTE:
1. Typical implies Vce = 5V and TA = +25°C.
2. Icc is measured at 10MHz and VIN= Oto 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range: Icc = 60 +
5(f - 10)mA, where f = operating frequency in MHz. For the military range, Icc = 80 + 7(f - 10) where f = operating frequency in MHz, f = 1/tMA .
3. For frequencies greater than 10MHz.

AC ELECTRICAL CHARACTERISTICS COMMERCIAL
SYMBOL

PARAMETER

IDT7209L45
MIN. MAX.

(Vcc = 5V ±10%, TA = O°C to + lO°C)

IDT7209L65
MIN.
MAX.

1DT7209L1 00
MIN.
MAX.

ns

40

ns

1

-

35

-

40

ns

2

35

-

40

ns

2

-

25

-

ns

-

0

-

ns

25

-

ns

-

45

-

65

25

-

35

tENA

3 State Enable Time (1)

25

-

30

t OIS

3 State Disable Time (1)

-

25

-

30

ts

Input Register Set-up Time

15

-

25

25

25

Input Register Hold Time

3

-

3

Clock Pulse Width

15

-

25

-

1

-

135

35

-

-

tH

TEST LOAD
FIGURE

100

Multiply-Accumulate Time
Output Delay

tpw

UNIT

-

tMA
to

-

IDT7209L135
MIN.
MAX.

0

NOTE:
1. Transition is measured ±500mV from steady state voltage with loading specified in Figure 2.

AC ELECTRICAL CHARACTERISTICS MILITARY
SYMBOL

PARAMETER

IDT7209L55
MIN. MAX.

(Vec = 5V ±10%, TA = -55°C to + 125°C)
IDT7209L75
MIN. MAX.

IDT7209L120
MIN.
MAX.

IDT7209L170
MAX.
MIN.

UNIT

TEST LOAD
FIGURE
1

tMA

Multiply-Accumulate Time

-

75

-

120

-

170

ns

Output Delay

-

55

to

30

-

35

-

40

45

ns

1

tENA

3 State Enable Time (1)

-

30

-

35

45

ns

2

t OIS

3 State Disable Time(1)

-

30

-

35

-

-

40

-

45

ns

2

t8

Input Register Set-up Time

20

-

25

-

30

30

-

ns

-

-

3

-

0

-

ns

-

30

30

-

30

-

ns

-

tH

Input Register Hold Time

3

t pw

Clock Pulse Width

20

0

NOTE:
1. Transition is measured ±500mV from steady state voltage with loading specified in Figure 2.

7-4

40

IDT7209L 12 x 12-BIT PARALLEL
CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

AC TEST CONDITIONS

SYMBOL

GNDto 3.0V
Sns
1.SV
1.5V
See Figures 1 and 2

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

(TA= +2S0C, f = 1.0MHz)

PARAMETER(1)

CONDITIONS

CIN

Input Capacitance

COUT

Output Capacitance

MAX.

10

pF

VOUT= OV

12

pF

NOTE:

1. This parameter is sampled and not 100% tested.

Vcc

810n
TO
OUTPUT ~----~--~--~
PIN
40pF

1.1K

Figure 1. AC Output Test Load

DATA
INPUT

_ _

Figure 2. Output Three-State
Delay Load
(Vx = OV or 2.6V)

~v

/+-tsttH~

~~'f,~~

500n

TO
OUTPUT
PIN

-----------1 ---------------1
--------------

-------- 3V
1.SV

THREESTATE
CONTROL

OUTPUT
THREESTATE

~
t

DIS

HIGH IMPEDANCE

OV

Figure 3. Set-Up And Hold Time

Figure 4. Three-State Control Timing Diagram

7-5

UNIT

VIN = OV

IDT7209L 12 x 12-BIT PARALLEL
CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

INPUT

INPUT
CLOCK
OUTPUT
CLOCK
PRELOAD
THREE-STATE
CONTROL

OUTPUT

DATA OUT

HIGH IMPEDANCE

Figure 5. Timing Diagram

SIGNAL DESCRIPTIONS:

TC (Two's Complement)
When the TC Control is high, it makes both the X and Y input
two's complement inputs. When the TC Control is low, it makes
both inputs, X and Y, unsigned magnitude inputs.

INPUTS:
XItj (X11 - Xo)
Multiplicand Data Inputs
YIN

RND (Round)
A high level at this input adds a "1" to the most significant bit of
the LSP to round up the XTP and MSP data. RND, like ACC and
SUB, is loaded on the rising edge of either CLKX or CLKY and must
be valid for the duration of the input data.

(Yn - yo)

Multiplier Data Inputs

INPUT CLOCKS:

PREL (Preload)
When the PREL input is high, the output is driven to a high impedance state. When the TSX, TSL and TSM inputs are also high,
the contents of the output register can be preset to the preload data
applied to the output pins at the rising edge of CLKP. The PREL,
TSM, TSL and TSX inputs must be valid over the same period that
the preload input is valid.

CLKX,CLKY
Input data is loaded on the rising edge of these clocks.

CONTROLS:
ACC (Accumulate)
When ACC is high, the contents of the XTP, MSP and LSP registers are added to or subtracted from the multiplier output. When
ACC is low, the device acts as a simple multiplier with no accumulation being performed and the next product generated will be
stored directly into the output registers. The ACC Signal is loaded
on the rising edge of the CLKX or CLKY and must be valid for the
duration of the data input.

TSX, TSL, TSM (Three State Output Controls)
The XTP, MSP and LSP registers are controlled by direct nonregistered control signals. These output drivers are at high impedance (disabled) when control signals TSX, TSM and TSL are high
and are enabled when TSX, TSM and TSL are low.

OUTPUT CLOCK:

SUB (Subtract)

CLKP

When the ACC and SUB signals are both high, the contents of
the output register are subtracted from the next product generated
and the difference is stored back into the output registers at the rising edge of the next CLKP. When ACC is high and SUB is low, an
addition instead of a subtraction is performed. Like the ACC Signal,
the SUB signal is loaded into the SUB register at the rising edge of
either CLKX or CLKY and must be valid over the same period as the
input data is valid. When the ACC is low, SUB acts as a "don't care"
input.

Output data is loaded into the output register on the rising edge
of this clock.

OUTPUTS:
XTP (P26 - P24)
Extended Product Output (3-bits)
MSP (P23 - P,2)
Most Significant Product
LSP (P11 - Po)
Least Significant Product

7-6

1DT7209L 12 x 12-81T PARALLEL
CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRELOAD TRUTH TABLE
PREL

TSM

TSX

TSL

XTP

MSP

NOTES ON TWO'S COMPLEMENT FORMATS:

LSP

0

0

0

0

Q

Q

0

0

0

1

Q

Q

HiZ

0

0

1

0

Q

HiZ

Q

HiZ

1. In two's complement notation, the location of the binary point
that signifies the separation of the fractional and integer fields is
just after the sign, between the sign bit (_2°) and the next significant bit for the multiplier inputs. This same format is carried over to
the output format, except that the extended significance of the integerfield is provided to extend the utility of the accumulator. In the
case of the output notation, the output binary point is located between the 2° and 2 -1 bit positions. The location of the binary point
is arbitrary, as long as there is consistency with both the input and
output formats. The number field can be considered entirely integer with the binary point just to the right of the least significant bit for
the input, product and the accumulated sum.
2. When in the non-accumulating mode, the first four bits (P26
through P23) will all indicate the sign of the product. Additionally,
the P22 term will also indicate the sign with one exception, when
multiplying -1 x -1. With the additional bits that are available in this
multiplier, the -1 x -1 is a valid operation that yields a + 1 product.
3. In operations that require the accumulation of single products or
sum of products, there is no change in format. To allow for a valid
summation beyond that available for a single multiplication product, three additional significant bits (guard bits) are provided. This
is the same as if the product was accumulated off-chip in a separate 27-bit wide adder. Taking the sign at the most significant bit
position will guarantee that the largest number field will be used.
When the accumulated sum only occupies the right hand portion
of the accumulator, the sign wi II be extended into the lesser significant bit positions.

Q

0

0

1

1

Q

HiZ

0

1

0

0

HiZ

Q

Q

0

1

0

1

HiZ

Q

HiZ

0

1

1

0

HiZ

HiZ

Q

0

1

1

1

HiZ

HiZ

HiZ

1

0

0

0

HiZ

HiZ

HiZ

1

0

0

1

HiZ

HiZ

PL
HiZ

1

0

1

0

HiZ

PL

1

0

1

1

HiZ

PL

PL

1

1

0

0

PL

HiZ

HiZ

1

1

0

1

PL

HiZ

PL

1

1

1

0

PL

PL

HiZ

1
1
1
PL
PL
PL
1
NOTES:
Hi Z = Output buffers at high impedance (output disabled).
Q = Output buffers at low impedance. Contents of output register will
be transferred to output pins.
PL = Output buffers at high impedance or output disabled. Preload
data supplied externally at output pins will be loaded into the output register at the rising edge of CLKP.
BINARY POINT

SIGNAL
DIGrrVALUE

Figure 6. Fractional Two's Complement Notation

BINARY POINT

,

SIGNAL
DIGIT VALUE

Figure 7. Fractional Unsigned Magnitude Notation

7-7

fI

1DT7209L 12 x 12-BIT PARALLEL
CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

BINARY POINT
Xo
0
2

Yo
2

SIGNAL
DIGIT VALUE

SIGNAL

0

Po
0
2

I DIGIT VALUE

SIGNAL
DIGIT VALUE

Figure 8, Integer Two's Complement Notation

BINARY POINT
SIGNAL

Xo
2

0

Yo

2

SIGNAL

0

Po

2

DIGIT VALUE

0

DIGIT VALUE
SIGNAL
DIGIT VALUE

Figure 9. Integer Unsigned Magnitude Notation

ORDERING INFORMATION
lOT

XXXX

A

Device Type

Power

999
Speed

A

A

Package

Process/
Temperature
Range

y:onk

IC

'-------~I ~

Commercial (O°C to

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Topbraze DIP
Leadless Chip Carrier
Pin Grid Array

COM'L.

MIL.

45
65

55
75
120
170

100
135
L-______________________________

~I

+ 70°C)

) Sp.,.d in Nono""ond,

L
Low Power

L-______________________________________

7-8

~

7209

12 x 12 Parallel CMOS Multiplier-Accumulator

FEATURES:

DESCRIPTION:

• 16 x 16-bit parallel multiplier-accumulator with selectable
accumulation and subtraction

The IDT721 0/7243 are high-speed, low-power 16 x 16-bit parallel multiplier-accumulators that are ideally suited for real-time
digital signal processing applications. Fabricated using CEMOS
silicon gate technology, these devices offer a very low-power alternative to existing bipolar and NMOS counterparts, with only 1/7 to
1/10 the power dissipation and exceptional speed (35ns maximum) performance.
Pin and functional replacements for TRW's TDC1010J/
TDC1043, the IDT7210/7243 operate from a single 5 volt supply
and are compatible with standard TTL logic levels. The architecture of the IDT721 0/7243 is fairly straightforward, featuring individual input and output registers with clocked D-type flip-flops, a
preload capability (IDT7210 only) which enables input data to be
preloaded into the output registers, individual three-state output
ports for the Extended Product (XTP) and Most Significant Product
(MSP) and a Least Significant Product output (LSP) which is multiplexed with the v input. Unlike the IDT7210, the IDT7243 does not
have either a preload capability or a Least Significant Product
(LSP) output accessible externally.
The XIN and VIN data input registers may be specified through
the use of the Two's Complement input (TC) as either a two's complement or an unsigned magnitude, yielding a full-precision 32-bit
result that may be accumulated to a full 35-bit result. The three output registers-Extended Product (XTP), Most Significant Product
(MSP) and Least Significant Product (LSP) -are controlled by the
respective TSX, TSM and TSL input lines. The LSP output can be
routed through VIN ports in the IDT7210.
Continued on Page 2

• High-speed: 35ns multiply-accumulate time
• IDT721 0 features selectable accumulation, subtraction, rounding and preloading with 35-bit result
• IDT7243 features selectable accumulation, subtraction and
rounding with 19-bit result
• IDT7210 is pin and functionally compatible with the TRW
TDC1010J
• IDT7243 is pin and functionally compatible with the TRW
TDC1043
• Both devices perform subtraction and double precision addition
and multiplication
• Produced using advanced CEMOS ™ high-performance
technology
• Low power consumption (less than 250mW typical) -less than
1/10 the power of compatible bipolar and 1/7 the power of
NMOS designs
• Input and output directly TTL-compatible
• Single 5V supply
• Available in plastic and topbraze DIP, SHRINK-DIP, LCC, FinePitch LCC, PLCC, Flatpack and Pin Grid Array
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
X IN
ACC SUB
CLKX (X 15 - Xo) RND. TC'

YIN
CLKY (yw YO/P,5- Po)

XIN
ACC SUB.
CLKX (X15 - Xo) RND. TC

CLKP
TSX

TSX
16

MSPOUT
(P31 -

P16 )

IDT721 0

IDT7243

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology, Inc.

7-9

DECEMBER 1987
DSC-2018/-

10T7210lANO 1DT7243l 16 x 16-81T
PARAllEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DESCRIPTION (Continued)
sign extended in the two's complement mode or set to zero in the
unsigned mode. The Round (RND) control rounds up the Most Significant Product (MSP) and the 3-bit Extended Product (XTP) outputs. When Preload input (PREL) is active, all the output buffers are
forced into a high-impedance state (see Preload truth table) and
external data can be loaded into the output register by using the
TSX, TSL and TSM signals as input controls.

The Accumulate input (ACC) enables the device to perform
either a multiply or a multiply-accumulate function. In the multiplyaccumulate mode, output data can be added to or subtracted from
subsequent results. When the Subtraction (SUB) Input is active simultaneously with an active ACC, a subtraction can be performed.
The double precision accumulated result is rounded down to
either a single precision or single precision plus 3-bit extended
result. In the multiply mode, the Extended Product output (XTP) is

PIN CONFIGURATIONS
IOT7243

IOT7210
Xa
Xs
X4
X3
X2
Xl
Xo
po. Yo
Pl. Yl
P2. Y2
P3. Y3
P4. Y4
ps. Ys
Pa. Ya
P7. Y7
GND
PB. YB
P9. Y9
Pl0. Yl0
Pll. y"
P12. Y12
P13. Y13
P14. Y14
P1S. Y1S
Pla
P17
P1B
P19
P20
P2l
P22
P23

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 P64-1
&
18
19 C64-1
20
21

22
23
24
25
26
27
28
29
30
31
32

X7
XB
X9
XlO
Xll
X12
X13
X14
X1S
TSl
RND
SUB
ACC
ClKX
ClKY
Vee
TC
TSX
PREl
TSM
ClKP
P34
P33
P32
P3l
P30
P29
P2B
P27
P26
P2S
P24

Xa
Xs
X4
X3
X2
Xl
Xo
Yo
Yl
Y2
Y3
Y4
Ys
YB
Y7
GND
YB
Y9
Yl0
Yll
Y12
Y13
Y14
Y1S
Pla
P17
P1B
P19
P20
P2l
P22
P23

DIP
TOP VIEW

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 P64-1
&
18
19 D64-1
20
21
22
23
24
25
26
27
28
29
30
31
32
DIP
TOP VIEW

7-10

X7
XB
X9
Xl0
X"
X12
X13
X14
X1S
NC
RND
SUB
ACC
ClKX
ClKY
Vee
TC
'TSX
GND
TSM
ClKP
P34
P33
P32
P3l
P30
P29
P2B
P27
P2ti
P2S
P24

1DT7210L AND IDT7243L 16 x 16·BIT
PARALLEL CMOS MULTIPLlER·ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT7243

IDT7210
O-NC"')"'!:2'Ll)

.;:.;:>!~~)::oo~~>:>:>:>:>:>:

00

tt~f~iaa~~£~~~~£~

.;:.;:>!~~)::aa~~~~~~~~~

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

Pl. Yl 61
PO. YO 62
Xo 63
Xl 64
X2 65
X3 66
X4 67
X5 68
Xa 1

X7

2
X8 3

X9
Xl0
Xll
X12
X13
X14

6OM~~W~~~~~5OG~U~~«

4

5
a
7
a
9

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

Yl
Yo
Xo
Xl
X2
X3
X4
X5
X6
X7
X8
X9
Xl0
Xll
X12
X13
X14

17
18
19
20
21
22
23
24
25
2a
27
28
29
30
31
32
33

61
62
63
64
65
66
67
68
1
2
3

43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

J68-1
&
L68·2

8
9

P 17
P 18
P 19
P 20
P 21
P 22
P 23
P 24
P 25
P 26
P 27
P 28
P 29
P 30
P 31
P 32
P 33

10111213 14 151617 18192021 2223242526
~OOaJo~~ 0

II

OOOOXO:!c...,.

XZZ~o~~~~~~~~zw~~
a:
!~~)::O~~~~~~~~
.......... .... z .... 0 ...... C\I V
C')

n n n n n n nn nn n n n n n n

64636261605958575655545352515049

Pa.
P9.
Pl0
Pll
P12
P13
144
P15
Pla
P17
P18
P19
P20
P21
P22
P23

CLKP
P34
P33
P32
P31
P30
P29
P28
P27

P26
P25
P24

48:=l
47:=l
46:=l
45:=l
44:=l
43:=l
42:=l
41:=l
40:=l
39:=l
38:=l
7:=l
36:=l
5:=l
34:=l
33:=l

po. Yo =1
Xo =2
Xl =3
X2 =4
X3 =5
X4 =6
X5 =7
X6 =8
X7 =9
X8 =10
X9 =11
XlO =12
Xll =13
X12 =14
X13 =15
X14 =16

Yo
Yl
Y2
Y3
Y4
Y5
Ya
Y7

Pr.
GND
GND

TC
TSX
PREL
TSM

Ll)

~~~~~~~c.:l~~~~~~~~

Y8
Y9
• v,o
• V,1
• V,2
• V,3
• V,4
• V,5

17181920212223242526272829303132

U U U U U U U U UU U U U U U U
~~OaJo~~ 80~ m:!~ ~ ~ Pl
X~~~~dd>~~~~dc..c..c..
FLAT PACK
TOP VIEW

SHRINK·DIP
TOP VIEW

7-11

P16
P17
P18
P19
P20
P21
P22
P23
P
24
P25
P26
P27
P28
P29
P3Q
P31

IDT7210LAND IDT7243L 16 x 16-BIT
PARALLEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (Continued)
IOT721 0

11

NC

X15

RND

ACC

CLKy

TC

PREL CLKp

P33

TSL

SUB

CLKx

Vee

TSX

TSM

P32

NC

10

X13

X14

09

Xl1

X12

P30

P3l

08

Xg

XlO

P28

P29

07

X7

Xa

P26

P27

06

Xs

Xe

P24

P25

05

Xs

X4

P22

P23

Xl

X2

P20

P2l

03

Yo.
Po

Xc

P18

P19

02

NC

Yl.
Pl

Y3.
P3

Y5.
P5

Y7.
P7

Y8.
P8

YlO.
PlO

Y12.
P12

Y14.
P14

P16

P17

01

•

Y2.
P2

Y4.
P4

Y6.
P6

GND

Y9.

F9

Yll.
Pll

Y13.
P13

Y15.
P15

NC

B

C

D

E

F

G

H

04

Pin1/
Designator A

P34

G68-2

K

L

PGA
TOP VIEW

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

-'-0.5 to +7.0

o to

+70

RECOMMENDED DC OPERATING CONDITIONS

(1)

COMMERCIAL

MILITARY

UNIT

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

4.5

5.0

5.5

V

-0.5 to +7.0

V

VeeM

Military Supply
Voltage

-55 to +125

°C

Vee

Commercial
Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H

Input High Voltage

2.0

-

V

V1L

Input Low Voltage

-

-

0.8

V

TalAs

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

lOUT

DC Output Current

50

50

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

7-12

IDT7210L AND IDT7243L 16 x 16-BIT
PARALLEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS - FAST
(Commercial Vec= 5V ±10%, TA = O°C to + 70°C, Military Vee = 5V ±10%, TA = -55°C to + 125°C
for Commercial clocked multiply times of 20, 25, 35, 45, 55, 65, 75ns or Military 25, 30, 40, 55, 65, 75, 85ns)
SYMBOL

PARAMETER

TEST CONDITIONS

COMMERCIAL
MILITARY
Typ.(l) MAX. MIN.
Typ. 10MHz

-

-

6

-

-

8

mAl
MHz

J.lA

VOH
2.4
V
Output High Voltage
2.4
Vcc = Min., bH = -2.0mA
V (4)
Output
Low
Voltage
0.4
0.4
V
Vcc = Min., bL = 4mA
OL
NOTES:
1. TypicalimpliesVcc = 5V and TA = +25°C.
2. Icc is measured at 10MHz and V1N = Ot03V. For frequencies greater than 10MHz, the following equation is usedforthecommercial range: Icc = 90 +
6(f - 10)mA, where f = operating frequency in MHz. For the military range, Icc = 110 + 8(f - 10) where f = operating frequency in MHz, f = 1/tMA .
3. For frequencies greater than 10MHz.
4. 10L = 8mA for t MA = 20ns to 55ns.

DC ELECTRICAL CHARACTERISTICS - SLOW
(Commercial Vcc= 5V ±10%, TA = O°C to + 70°C, Military Vcc = 5V ±10%, TA = -55°C to + 125°C
for Commercial clocked multiply times of 100, 165ns or Military, 120, 200ns)
SYMBOL

PARAMETER

TEST CONDITIONS

COMMERCIAL
MILITARY
Typ. 10MHz

-

-

5

-

-

7

mAl
MHz

VOH

Output High Voltage

Vcc = Min., 10H = -2.0mA

2.4

2.4

V

Vee = Min., 10L = 4mA

0.4

-

-

-

Output Low Voltage

-

-

VOL

0.4

V

lIu l

Input Leakage Current

IlLOI
Icc (2)

-

-

2

-

UNIT

-

10

J.lA

NOTES:
1. Typical implies Vcc = 5V and TA = + 25° C.
2. Icc is measured at 10MHz and V1N = Oto 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range: Icc = 70 +
5(f - 1O)mA, where f = operating frequency in MHz. For the military range, Icc = 90 + 7(f - 10) where f = operating frequency in MHz, f = 1/t MA .
3. For frequencies greater than 10MHz.

7-13

1DT7210L AND IDT7243L 16 x 16-BIT
PARALLEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS COMMERCIAL
SYMBOL

(Vee = 5V ±10%, TA = O°Cto +70°C)

7210L45 7210L55 7210L65 7210L75 7210L100 7210L160
7210L35 7243L45 7243L55 7243L65 7243L75 7243L100 7243L160 UNIT
MIN.MAX. MIN.MAX. MIN.MAX. MIN.MAX. MIN.MAX. MIN. MAX. MIN. MAX.

PARAMETER

35

3-State Disable Time(1)

-

-

45

-

55

25

30

25

-

25

-

ts

Input Register Set-up Time

12

-

15

20

Input Register Hold Time

3

-

3

-

Clock Pulse Width

10

-

15

-

20

-

tH
tpw

tMA (2)

Multiply-Accumulate Time

t o(2)

Output Delay

t ENA (3)

3-State Enable Time (1)

t OIS (3)

25
25

25

3

-

30
30

75

30

-

25

-

25

3

-

25

-

165

ns

35

40

ns

35

-

40

ns

35

-

40

ns

-

30

-

ns

100

35

-

35

25

3

-

25

-

25

65
35
30

35

0

0
25

ns
ns

NOTES:
1. Transition is measured ±500mV from steady state voltage with loading specified in Figure 2.
2. See Test Load Figure 1.
3. See Test Load Figure 2.

AC ELECTRICAL CHARACTERISTICS MILITARY
SYMBOL

(Vec = 5V ±10%, TA = -55°C to + 125°C)

7210L55 7210L65 7210L75 7210L85 7210L120 7210L200
7210L40 7243L55 7243L65 7243L75 7243L85 7243L120 7243L200 UNIT
MIN.MAX. MIN.MAX. MIN.MAX. MIN.MAX. MIN.MAX. MIN. MAX. MIN. MAX.

PARAMETER

t MA (2)
t o (2)

Multiply-Accumulate Time

-

40

Output Delay

25

tENA (3)

3 State Enable Time(l)

t OIS (3)

3 State Disable Time(1)

-

ts

Input Register Set-up Time

tH
t pw

-

55

-

65

-

75

30

-

35

-

35

30

-

30

-

35

25

-

30

-

30

-

30

15

-

20

-

25

-

25

Input Register Hold Time

3

-

3

-

3

-

3

Clock Pulse Width

15

-

20

-

25

-

25

-

25

-

85

-

120

-

200

ns

35

40

45

ns

40

-

45

ns

35

-

40

-

45

ns

25

-

30

30

-

0

30

-

30

-

ns

3

-

35

0
30

ns
ns

NOTES:
1. Transition is measured ±500mV from steady state voltage with loading specified in Figure 2.
2. See Test Load Figure 1.
3. See Test Load Figure 2.

CAPACITANCE

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

SYMBOL

GND to3.0V
3ns
1.5V
1.5V
See Figures 1 and 2

CIN
COUT

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CONDITIONS

MAX.

UNIT

VIN = OV

10

pF

VOUT= OV

12

pF

Input Capacitance
Output Capacitance

NOTE:
1. This parameter is sampled and not 100% tested.

Vce
TO
OUTPUT
PIN

8100
TO
OUTPUT
PIN
40pF

1.1K

Vx=OOR 2.6V

Figure 1. AC Output Test Load

Figure 2. Output Three-State
Delay Load

7-14

-,

IDT7210L AND IDT7243L 16 x 16-81T
PARALLEL CMOS MULTIPLIER-ACCUMULATOR

DATA
INPUT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

-tt·~V
.
r- S

CL.OCK
INPUT - - - - - - -

tWj

f

______________- J

THREESTATE
CONTROL

----+:=

DIS

"

3V

OUTPUT
THREESTATE

- - - - - - - 1.5V

--------------oV

Figure 3. Set-Up and Hold Time

HIGH IMPEDANCE

Figure 4. Three-State Control Timing Diagram

INPUT

INPUT
CLOCK
OUTPUT
CLOCK
PRELOAD
THREE-STATE
CONTROL

OUTPUT

t

HIGH IMPEDANCE

Figure 5. Timing Diagram

7-15

IDT7210L AND IDT7243L 16 x 16-BIT
PARALLEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS:

TSX, TSL, TSM (Three-State Output Controls)
The XTP, MSP and LSP registers are controlled by direct nonregistered control signals. These output drivers are at high impedance (disabled) when control signals TSX, TSM and TSL are high
and are enabled when TSX, TSM and TSL are low.

INPUTS:
XIN (X15 - Xo)
Multiplicand Data Inputs

OUTPUT CLOCK:

YIN (Y15 - Yo)
Multiplier Data Inputs

CLKP
Output data is loaded into the output register on the rising edge
of this clock.

INPUT CLOCKS:
CLKX,CLKY

OUTPUTS:

. Input data is loaded on the rising edge of these clocks.

XTP (P34 - P32)

CONTROLS:

Extended Product Output (3-bits)

ACC (Accumulate)

MSP (P31 - P16)

When ACC is high, the contents of the XTP, MSP and LSP registers are added to or subtracted from the multiplier output. When
ACC is low, the device acts as a simple multiplier with no accumulation being performed and the next product generated will be
stored directly into the output registers. The ACC signal is loaded
on the rising edge of the CLKX or CLKY and must be valid for the
duration of the data input.

Most Significant Product
LSP (P15 - Po)
Least Significant Product (IDT7210 only), shared with YIN
input.

NOTES ON TWO'S COMPLEMENT FORMATS:

SUB (Subtract)

1. In two's complement notation, the location of the binary point
that signifies the separation of the fractional and integer fields is
just after the sign, between the sign bit (_2°) and the next significant bit for the multipl ier inputs. This same format is carried over to
the output format, except that the extended significance of the integer field is provided to extend the utility of the accumulator. In the
case of the output notation, the output binary point is located between the 2° and 2- 1 bit positions. The location of the binary point
is arbitrary, as long as there is consistency with both the input and
output formats. The number field can be considered entirely integer with the binary point just to the right of the least significant bit for
the input, product and the accumulated sum.
2. When in the non-accumulating mode, the first four bits (P34
to P31) will all indicate the sign of the product. Additionally, the P30
term will also indicate the sign with one exception, when multiplying -1 x -1. With the additional bits that are available in this mUltiplier, the -1 x -1 is a valid operation that yields a + 1 product.
3. In operations that require the accumulation of single products or
sum of products, there is no change in format. To allow for a valid
summation beyond that available for a Single multiplication product, three additional significant bits (guard bits) are provided. This
is the same as if the product was accumulated off-chip in a separate 35-bit wide adder. Taking the sign at the most significant bit
position will guarantee that the largest number field will be used.
When the accumulated sum only occupies the right hand portion
of the accumulator, the sign will be extended into the lesser significant bit positions.

When the ACC and SUB signals are both high, the contents of
the output register are subtracted from the next product generated
and the difference is stored back into the output registers at the rising edge of the next CLKP. When ACC is high and SUB is low, an
addition instead of a subtraction is performed. Like the ACC signal,
the SUB signal is loaded into the SUB register at the rising edge of
either CLKX or CLKY and must be valid over the same period as the
input data is valid. When the ACC is low, SUB acts as a "don't care"
input.
TC (Two's Complement)
When the TC Control is high, it makes both the X and Y input
two's complement inputs. When the TC Control is low, it makes
both inputs, X and Y, unsigned magnitude inputs.
RND (Round)
A high level at this input adds a "1" to the most significant bit of
the LSP to round up the XTP and MSP data. RND, like ACC and
SUB, is loaded on the rising edge of either CLKX or CLKY and must
be valid for the duration of the input data.
PREL (Preload) (IDT7210 only)
When the PREL input is high, the output is driven to a high impedance state. When the TSX, TSL and TSM inputs are also high,
the contents of the output register can be preset to the preload data
applied to the output pins at the rising edge of CLKP. The PREL,
TSM, TSL and TSX inputs must be valid over the same period that
the preload input is valid.
YIN/LSP Output-(LSP output, IDT7210 only)
Shares functions between 16-bit data input (YIN) and the least significant product output (LSP).

7-16

IDT7210L AND 1DT7243L 16 x 16-BIT
PARALLEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRELOAD TRUTH TABLE (10T7210 only)
PREL

TSM

TSL

0

TSX

0

0

0

XTP
Q

MSP
Q

LSP

0

0

0

1

Q

Q

HiZ

0

0

1

0

Q

HiZ

Q

0

0

1

1

Q

HiZ

HiZ

0

1

0

0

HiZ

Q

Q

0

1

0

1

HiZ

Q

HiZ

0

1

1

0

HiZ

HiZ

Q

Q

0

1

1

1

HiZ

HiZ

HiZ

1

0

0

0

HiZ

HiZ

HiZ

1

0

0

1

HiZ

HiZ

PL

1

0

1

0

HiZ

PL

HiZ

1

0

1

1

HiZ

PL

PL

1

1

0

0

PL

HiZ

HiZ

1

1

0

1

PL

HiZ

PL

1

1

1

0

PL

PL

HiZ

1
1
PL
PL
1
1
PL
NOTES:
Hi Z = Output buffers at high impedance (output disabled).
Q = Output buffers at low impedance. Contents of output register
will be transferred to output pins.
PL = Output buffers at high impedance or output disabled. Preload
data supplied externally at output pins will be loaded into the
output register at the rising edge of CLKP.

BINARY POINT

Figure 6_ Fractional Two's Complement Notation

7-17

IDT7210L AND IDT7243L 16 x 16-BIT
PARALLELC?MOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 7. Fractional Unsigned Magnitude Notation

BINARY POINT
SIGNAL

SIGNAL

SIGNAL
~~~

__

r-~~

__

~~~

__

~~

__

~~~~~

__

~~

__

~~~

__

~~

__

~~

__

~~

__

~~

__

~~

__L--L__

DIGIT
L-~~~VALUE

Figure 8. Integer Two's Complement Notation

BINARY POINT
Xo SIGNAL

2

0

DIGIT
VALUE

Yo SIGNAL

2

0

DIGIT
VALUE

Po SIGNAL

2

Figure 9. Integer Unsigned Magnitude Notation

7-18

0

DIGIT
VALUE

1DT7210LAND IDT7243L 16x 16-81T
PARALLEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XXXX
Device Type

A
Power

999
Speed

A

A

Package

Processl
Temperature
Range

y:Mk

P
XC
C
L----------t J
XL
L
F
G

Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze SHRINK-DIP*
Topbraze DIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier (25 MIL Center)*
Leadless Chip Carrier
Flatpack*
Pin Grid Array·
COM'L.
35*
45
55
65
100
165

~--------------------------~IL
I

7210

L------------------------------------~17243

* IDT7210 only.

7-19

MIL.
40*
55
65
75
85
120
200

) Speed"' N"""""ond,

Low Power
16 x 16 Parallel CMOS
Multiplier-Accumulator

DI

FEATURES:

DESCRIPTION:

• 12 x 12-bit parallel multiplier with double precision product

The IDT7212/IDT7213 are high-speed, low-power 12 x 12-bit
multipliers ideal for fast, real-time digital signal processing applications. Utilization of a modified Booths algorithm and IDT's highperformance, high-reliability technology, CEMOS, has achieved
speeds (35ns max.) exceeding bipolar at 1/10 the power
consumption.
The IDT72121IDT7213 are ideal for applications requiring highspeed multiplications such as fast Fourier transform analysis digital filtering, graphic display systems, speech synthesis and recognition and in any system requirement where multiplication speeds
of a mini/micro computer are inadequate.
All input registers, as well as LSP and MSP output registers, use
the same positive edge triggered D-type flip-flop. With the
IDT7212, there are independent clocks (CLKX, CLKY, CLKM,
CLKL) associated with each of these registers. The IDT7213 has
only J!.§Lngle clock input (CLK) and three register enables. ENX
and ENY control the two input registers, while ENP controls the
entire product.
The IDT7212/IDT7213 offer additional flexibility with the FA
control. The FA control formats the output for 2's complement by
shifting the MSP up one bit and then repeating the sign bit in the
MSB of the LSP.
Military grade product is manufactured in cbmpliance with the
latest revision of MIL-STD-883, Class B, making them ideally
suited to applications demanding the highest level of performance
and reliability.

• High-speed: 35ns maximum clock to multiply time
• Low power consumption: 150mW typical, less than 1/10 the
power of compatible bipolar parts
• Produced with advanced CEMOS ™ high-performance
technology
• IDT7212L is pin and functionally compatible with TRW
MPY012H
• IDT7213L requires only a single clock with register enables
• Configured for easy array expansion
• User-controlled option for transparent output register mode
• Round control for rounding the MSP
• Single 5V power supply
• Input and output directly TTL-compatible
• Three-state output
• Available in topbraze DIP and LCC
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

ClK
ClKY ----~~~--------~_+----------~
ClKX --+-+--+-~"""

~

rn?

MULTIPLIER
ARRAY

MULTIPLIER
ARRAY

FA----------------r-R)p~~wm~

FA
FT

FT --------------------~

ClKM -----------~
ClKl - - - - - - - - - - - - - + - - - - 1

12

IDT7212

MSPOUT
(P23 - P,2 )

Ems

12

IDT7213

lSPOUT
(P - Po)
"

MSPOUT
(P23 - P12l

lSPOUT
(Pll - Po)

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-2019/-

7-20

IDT7212LJIDT7213L 12 x 12·BIT PARALLEL CMOS MULTIPLIER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT7212

X7
X6

IDT7213

X7
X6

X6
X9
X10

X5
X4
X3
X2
X1
Xo
Po
P1
P2
P3
P4
P5
P6
P7
P6
P9
P10

X5
X4
X3
X2
X1
Xo
Po
P1
P2
P3
P4
P5
P6
P7
P6
P9
P10
P11

X11
CLKX
CLKY
RND
XM

Yo
Y1
Y2
Y3
Y4
Y5
Vee
Vee
Vee
V6
V7
V6
V9
V10
V11
VM
P23
P22
P21

P11
"Q"E[
~

GND
GND

FT
FA
CLKL
CLKM
P12
P13
P14
P15

orr

ITEM
GND
GND

FT
FA
CLK

P20

Effi5

P19
P16
P17
P16

P12
P13
P14
P15

DIP
TOP VIEW

DIP
TOP VIEW

IDT7212

(MS8) P23
P22
P22
P20
P19
P18
P17
P16
P15
P14
P13
P12

IDT7213

~~~~~~~~~~~~~~~~~

~~~~~~~~~~~~~~~~~

OO~~~~~M~~~OO~~Q~%«

OO~~~~~M~~~OO~~Q~%«

61
62
63
64
65
66
67
68

43
42
41
40
39
36
37
36
35
34
33
32
31
30
29
28
27

L68·2

NC
CLKM
CLKL

FA

FT

8
9

(MS8) P23

XM

RND
CLKY
CLKX
X 11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
Xo

P22
P22
P20
P19
P18
P17
P16
P15
P14
P13
P12

NC

61
62
63
64
65
66
67
66
1

43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
26
27

4
5

ENP
CLK

FA

FT

NC

1011121314 151617161920212223242526

1011 12 13 14 1516 17 18192021 222324 25 26

~~~~~~~~~~~~~~~~~
~~Ioro
m

~~~~~~~~~~~~~~~~~
~~Iolo
m

~

~

LCC
TOP VIEW

LCC
TOP VIEW

7-21

XM

RND

EN?

ENX

X 11
X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
Xo

NC

IDT7212UIDT7213L 12 x 12-BIT PARALLEL CMOS MULTIPLIER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM
TA

RATING
Terminal Voltage
with Respect to
GND

COMMERCIAL

RECOMMENDED DC OPERATING CONDITIONS
MILITARY

UNIT

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

4.5

5.0

5.5

V

-0.5 to +7.0

-0.5 to +7.0

V

VCCM

Military Supply
Voltage

Oto +70

-55 to +125

°C

Vcc

Commercial
Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.0

-

V

VIL

Input Low Voltage

-

-

0.8

V

Operating
Temperature

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.4

1.4

W

lOUT

DC Output Current

50

50

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation 01 the device at these or any other
conditions above those indicated in the operational sections 01 this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS-FAST
(Commercial Vcc = 5V ±10%, TA = O°C to + 70°C, Military Vce = 5V ±10%, T A = -55°C to + 125°C)
for Commercial clocked multiply times 0130, 35, 45, 70ns or Military, 40, 55, 90ns
SYMBOL

PARAMETER

TEST CONDITIONS

COMMERCIAL
MIN. TYP.(1) MAX.

-

-

50

-

20

-

6

-

-

Input Leakage Current

Vcc = Max., '-"N

IILol

Output Leakage Current

Hi Z, Vce = Max., VOUT = 0 to Vee

-

-

10

Icc (2)

Operating Power Supply Current

Outputs Open Measured at 10MHz(2)

30

65

ICcal

Quiescent Power Supply Current

VIN

<:: VIH , VIN

20

ICCQ2

Quiescent Power Supply Current

VIN

<:: Vce - 0.2V, \'IN

-

4

Icc /1(2.3)

Increase in Power Supply
Current/MHz

Vce = Max., 1 > 10MHz

VOH

Output High Voltage

Vee = Min., IOH = -2.0mA

VOL

Output Low Voltage

Vce = Min., 10L = 8mA

~ VIL
~ 0.2V

-

-

MILITARY
TYP.(1) MAX.

-

lIu l

= OVtoVcc

MIN.

10

UNIT

-

20

-

20

IlA

30

85

mA

20

50

mA

4

25

mA

8

mAl
MHz

IlA

2.4

-

-

2.4

-

-

V

-

-

0.4

-

-

0.4

V

NOTES:
1. Typical implies Vee = 5Vand TA = +25°C.
2. lee is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
lee = 65 + 6(f - 10}mA, where f= operating frequency in MHz. For the military range, Icc = 85 + 8(1 - 10} where f = operating frequency in MHz,
f = 1/tMUC(IDT7212}, f = 1itMC (IDT7213).
3. For frequencies greater than 10MHz.

7-22

---"'----------------------------

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT7212LJIDT7213L 12 x 12-BIT PARALLEL CMOS MULTIPLIER

DC ELECTRICAL CHARACTERISTICS-SLOW
(Commercial Vce = 5V ±100/0, TA = O°C to + 70°C, Military Vce = 5V ±100/0, TA = -55°C to + 125°C)
for Commercial clocked multiply times of 115ns or Military, 140ns
SYMBOL

PARAMETER

COMMERCIAL
MIN. TYP'(1) MAX.

TEST CONDITIONS

Ilu l

Input Leakage Current

Vec

IlLOI

Output Leakage Current

Hi Z, Vce = Max., VOUT = 0 to Vec

= Max., \'IN

= OVto Vec

bc(2)

Operating Power Supply Current

Outputs Open Measured at 10MHz(2)

ICCQl

Quiescent Power Supply Current

VIN ~ VIH ' VIN ~ VIL

ICCQ2

Quiescent Power Supply Current

VIN ~ Vcc - 0.2V, VIN ~ 0.2V

Icc If(2.

Increase in Power Supply
Current/MHz

Vcc = Max., f

VOH

Output High Voltage

Vce = Min., IOH

VOL

Output Low Voltage

Vce

3)

> 10MHz

= Min., IOL

= -2.0mA

-

-

MILITARY
TYp,(1) MAX.

UNIT

2

-

J.l.A

-

-

10

2

10

J.l.A

25

55

-

25

75

mA

10

30

-

10

30

mA

0.1

1.0

-

0.1

2.0

mA

-

-

7

mAl

-

2.4

-

-

V

0.4

-

:-

0.4

V

-

-

5

2.4

-

-

= 8mA

MIN,

MHz

:

NOTES:
1. Typical implies Vce = 5V and TA = +25°C.
2. Icc is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
Icc = 55 + 5(f - 10)mA, where f= operating frequency in MHz. For the military range, Icc = 75 + 7(f - 10) where f = operating frequency in MHz,
f = 1/tMue(IDT7212), f = 1/tMc (IDT7213).
3. For frequencies greater than 10MHz.

AC ELECTRICAL CHARACTERISTICS COMMERCIAL

.

SYMBOL

PARAMETER

(Vec = 5V ±100/0, T A = O°C to + 70°C)

IDT7212L35
IDT7213L35
MIN.
MAX.

IDT7212L45
1DT7212L70 1DT7212L115
IDT7213L45
IDT7213L70 IDT7213L115
MAX,
MAX. MIN.
MAX. MIN,
MtN.

t MUC

Unclocked Multiply Time

-

55

t Me

Clocked Multiply Time

-

35

-

UNIT

TEST
LOAD
FIGURE

-

105

-

155

ns

1

45

70

-

115

ns

1
1

65

ts

X, Y, AND Set-up Time

15

-

20

-

20

3

-

3

-

2

0

-

ns

X, Y, AND Hold Time

-

25

tH

ns

1

tpwH

Clock Pulse Width High

15

-

20

-

20

-

25

-

ns

1
1

tpWL

Clock Pulse Width Low

15

-

20

-

20

-

25

-

ns

tpop

Output Clock to P

25

25

30

40

ns

1

tENA

3 State Enable Time (2)

30

40

ns

2

35

ns

2

ns

1

ns

1

ns

t OIS

3 State Disable Time (2)

-

25

-

25

-

30

-

ts

Clock Enable Set-up Time (lDT7213 only)

15

-

20

-

25

-

25

tH

Clock Enable Hold Time (IDT7213 only)

3

-

3

-

3

-

0

-

t HCL

Clock Low Hold Time CLKXY Relative to
CLKMU1) (IDT7212 only)

0

-

0

-

0

-

0

-

25

35

NOTES:
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage with loading speCified in Figure 2.

7-23

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7212LJIDT7213L 12 x 12-BIT PARALLEL CMOS MULTIPLIER

AC ELECTRICAL CHARACTERISTICS MILITARY
SYMBOL

(Vcc = 5V ±10%, TA = -55°C to

1DT7212L55
1DT7212L90
IDT7212L40
1DT7213L55
1DT7213L90
IDT7213L40
MAX. MIN.
MAX.
MIN.
MAX. MIN.

PARAMETER

+ 125°C)
1DT7212L140
1DT7213L140
MAX.
MIN.

UNIT

TEST
LOAD
FIGURE
1

t MUC

Unclocked Multiply Time

-

60

-

75

-

185

ns

Clocked Multiply Time

-

40

-

55

-

130

t MC

90

-

140

ns

1

ts

X, Y, RND Set-up Time

20

-

20

-

25

-

30

-

ns

1

tH

X,

Y, RND Hold Time

3

-

3

-

2

-

0

-

ns

1

t pWH

Clock Pulse Width High

20

-

25

30

-

30

-

ns

1

t pWL

Clock Pulse Width Low

20

-

25

-

30

-

30

-

ns

1

t pDP

Output Clock to P

-

25

-

30

-

35

-

45

ns

1

tENA

3 State Enable time (2)

-

25

-

30

-

40

ns

2

3 State Disable Time (2)

-

25

-

25

-

40

-

45

t DIS

45

ns

2

ts

Clock Enable Set-up Time
(IDT7213 only)

20

-

25

-

30

-

30

-

ns

1

tH

Clock Enable Hold Time
(IDT7213 only)

3

-

3

-

2

-

0

-

ns

1

t HcL

Clock Low Hold Time CLKXY
Relative to CLKMU 1)
(IDT7212 only)

0

-

0

-

0

-

0

-

ns

1

NOTES:
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured ±500mV from steady state voltage with loading specified in Figure 2.

CAPACITANCE

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

SYMBOL

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CIN

Input Capacitance

COUT

Output Capacitance

CONDITIONS

MAX.

UNIT

VIN = OV

10

pF

VOUT= OV

12

pF

NOTE:
1. This parameter is sampled and not 100% tested.

Vcc

8100
TO
OUTPUT
PIN

TO
OUTPUT
PIN
40pF

IN3062

Figure 1. AC Output Test Load

5000

°40PFO

V,

Figure 2. Output Three-State Delay Load
f'lx OV or 2.6V)

=

7-24

------_.-----------------------------------------------------

1DT7212LJIDT7213L 12 x 12-BIT PARALLEL CMOS MULTIPLIER

DATA
INPUT

_ _

~V

\--tsttH~
~~~~~

MILITARY AND COMMERCIAL TEMPERATURE RANGES

THREESTATE
CONTROL

--------------1 --------------3V

----f=

OUTPUT
THREESTATE

- - - - - - - - - 1.5V

t

DIS

r-t~A

HIGH IMPEDANCE

- - - - - - - - - ' - - - - - - - - - - - OV
NOTE:
Diagram shown for HIGH data only. Output transition may be opposite
sense.
Figure 3. Set-Up And Hold Time

Figure 4. Three-State Control Timing Diagram

CLlO(
CLKY

INPUTX
RND

I

Y

~

ClKM
ClKl

OUTPUT P
~----------tMUC---------~

Figure 5. 1DT7212 Timing Diagram

ClK

ENX
ENY

X. Y.

I

RND

ENP

OUTPUT P
~-------------tMUC-------------~

Figure 6. IOT7213 Timing Diagram

7-25

IDT7212LJIDT7213L 12 x 12-81T PARALLEL CMOS MULTIPLIER

..

1~- - - t M c

I

ClK

MILITARY AND COMMERCIAL TEMPERATURE RANGES

_I
r----~

01-------.....6 ~~~v~ ~~O~ ~r:.1
DATA
TO X,Y
REGISTERS

DATA OUTPUT
TO MSP, lSP
REGISTERS

-./ I+- t

HCL (IDT7212)

Ol-------~D _R~C~V~ ~S~ ~ ,:,S~I

DATA
TOX,Y
REGISTERS

DATA OUTPUT
TO MSP, lSP
REGISTERS

Figure 7. Simplified Timing Diagram-Typical Application

SIGNAL DESCRIPTIONS:

CONTROLS:

INPUTS:

XM, YM(TCX, TCy)(l)
Mode control inputs for each data word. A low input designates unsigned data input with a high input used for two's
complement.

XIN (Xu through Xo)
Twelve Multiplicand Data Inputs
YIN (Yu through Yo)
Twelve Multiplier Data Inputs

FA (RS)(l)
When the format adjust control is HIGH, a full 24-bit product is
selected. When this control is LOW, a left-shifted 23-blt product
is selected with the sign bit replicated in the Least Significant
Product (LSP). This control is normally HIGH except for certain
fractional two's complement applications (see Multiplier Input/
Output Formats).

INPUT CLOCKS (IDT7212 ONLY):
ClKX
The rising edge of this clock loads the X11 - Xo data input regIster alDng with the two's complement and round registers.

FT

ClKY
The rising edge of this clock loads the Y11 - Yo data input register along with the two's complement and round registers.

When this control is HIGH, both the Most Significant Product
(MSP) and Least Significant Product (LSP) registers are
bypassed.

ClKM

OEl

The rising edge of this clock loads the Most Significant Product (MSP) register.

Three-state enable for LSP output.

ClKl

OEP
Three-state enable for MSP output.

The rising edge of this clock loads the Least Significant Product (LSP) register.

RND

Round control for the rounding of the Most Significant Product (MSP). When this control is HIGH, a one is added to the Most
Significant Bit (MSB) of the Least Significant Product (LSP).
Note that this bit depends on the state of the Format Adjust (FA)
control. If FA is LOW when RND is HIGH, a one will be added to
the PlO.lf FA is HIGH when RND is HIGH, a one will be added to
the P". In either case, the LSP output will reflect this addition
when RND is HIGH. Note also the rounding always occurs in the
positive direction which may introduce a systematic bias. The
RN D input is registered and clocked in at the riSing edge of the
logical OR of both CLKX and CLKY.

INPUT CLOCKS {IDT7213 ONLY):
CLK
The rising edge of this clock loads all registers.
ENX

Register enable for the X11 - Xo data input register along with
the two's complement and round registers.
ENY
Register enable for the Y11 - Yo data input register along with
the two's~~complement and round registers.

OUTPUTS:

ENP

MSP (P23 through P,2)

Register enable the Most Significant Product (MSP) and
Least Significant Product (LSP).

Most Significant Product Output

lSP (P'1 through Po)
Least Significant Product Output
NOTE:
1. TRW MPY012H/K pin designation.

7-26

IDT7212LJIDT7213L 12 x 12-BIT PARALLEL CMOS MULTIPLIER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

BINARY POINT

Figure 8. Fractional Two's Complement Notation

BINARY POINT

Figure 9. Fractional Unsigned Magnitude Notation

BINARY POINT

,.J,

Figure 10. Fractional Mixed Mode Notation

*In this format an overflow occurs in the attempted multiplication of the two's complement number 10000 ... 0 with 1000... 00 yielding an erroneous
product of -1 in the fraction case and _2?-2 in the integer case.
'

7-27

IDT7212LJIDT7213L 12 x 12·BIT PARALLEL CMOS MULTIPLIER

MILITARY AND COMMERCIAL TEMPERATURE RANGES
BINARY POINT
Xo

2

0

Yo
0

SIGNAL
DIGIT VALUE

SIGNAL

2

DIGIT VALUE

Po

SIGNAL

2

0

Po
0

2

DIGIT VALUE

1FA = 01

SIGNAL
DIGIT VALUE

1FA = 11

Figure 11. Integer Two's Complement Notation

BINARY POINT
Xo

2

0

Yo

2

0

Po

2

0

SIGNAL
DIGIT VALUE

SIGNAL
DIGIT VALUE

SIGNAL
DIGIT VALUE 1FA = 11
MANDATORY

Figure 12. Integer Unsigned Magnitude Notation

BINARY POINT

DIGIT VALUE
SIGNAL
I--+--'-+~I-+-t--;--'+"""'-t-i--t--+~ (UNSIGNED MAGNITUDE)

DIGIT VALUE

Figure 13. Integer Mixed Mode Notation

*Inthis format an overflow occurs in the attempted multiplication of the two's complement number 10000 ... 0 with 1000... 00 yielding an erroneous
product of -1 in the fraction case and _222 in the integer case.

7-28

IDT7212L/IDT7213L 12 x 12-61T PARALLEL CMOS MULTIPLIER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XXXXX
Device Type

A
Power

999
Speed

A
Package

A
Process/
Temperature

Rl~g_e____________~

BLANK
B

Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883,
Class B

C
L

Topbraze DIP
Leadless Chip Carrier
COM'L.
35

MIL.

45

40
140

70
115

'----------------------------------------1
'-------------------------------------------------j

7-29

~g

1

Speed in Nanoseconds

L

Low Power

7212
7213

12 x 12-Bit Parallel CMOS Multiplier
12 x 12-Bit Parallel CMOS Multiplier with
Single Clock

FEATURES:

DESCRIPTION:

• Conforms to the requirements of IEEE Standard 754, 1985
version, for full 32-bit and 64-bit multiply and arithmetic
operations
'" ,

The IDT721264 floating-point multiplier and the IDT721265
floating-point ALU provide high-speed 32-bit and 64-bit floatingpoint processing capability.
The IDT721264/65 are fabricated using lOT's advanced
CEMOS technology and are capable of a total flow-through multiply latency (time required from the input of the operand until the
result can be used by another device) of 180ns for single precision
and 270ns for double precision multiplications. This ultra-highspeed performance is achieved by combining both state-of-the-art
CEMOS technology and advanced circuit design techniques.
For signal processing applications, where higher throughput
speeds are required, operations including the function specification can be pipelined. For single precision multiplications, new
operands can be loaded and a product unloaded every 60ns, while
double precision multiplies can be accomplished at a 120ns
rating. The IDT721265 ALU executes all operations at a 60ns
pipelined throughput. All operations, including the function specification, are pipelined so there is no penalty for interleaving various
functions. The on-chip pipeline is automatically advanced, using
internal timers, so explicit pipeline flushing is not required.
, This flexible two-chip set operates in full conformance with the
requirements of IEEE standard 754,1985 version. It performs operations on single (32-bit) and double (64-bit) precision operands,
as well as conversion to 32-bit two's complement integers
(IDT721265 only). The IDT721264/65 accommodates all rounding
modes, infinity and reserved operand representations and the
treatment of exceptions such as overflow, underflow, invalid and
inexact operations. Exact conformance to the standards ensures
complete software portabil ity between prototype development and
final application. A "FAST" mode eliminates the time penalty for
denormalized numbers by substituting zero for a denormalized
number.
The flexible input/output architecture of these devices allows
them to be used in systems with one, two or three 32-bit buses, or
one 64-bit bus. Fully registered inputs and outputs, separately controlled, are loaded on each rising edge of the clock.
A 64-bit function control determines the arithmetic function to be
performed while a 4-bit status output flags arithmetic exceptions
and conditions. Both the function inputs and status outputs propagate along with the data to ease system design timing.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883C, Class B.

• Very high-speed operation
- 16.7 megaflops (60ns) pipelined ALU operation
(Add/Subtract/Convert/Compare)
- 16.7 megaflops (60ns) pipelined 32-bit (single precision)
multiplications
- 8.0 megaflops (120ns) pipelined 64-bit (double precision)
multiplications
• Full floating-point function arithmetic logic unit including:
-Add
- Subtract
- Absolute Value
- Compare
- Conversion to and from two's complement integer
- Performs 2-A to support Newton-Raphson division
• Low-power (500mW typical per device) operation
• Single 5 volt supply-no need for two supplies
• Advanced CEMOS ™ technology
• Flexible system design
- Three 32-bit ports allow two data inputs and one result
output every clock cycle
- One, two or three port architectures supported
- Single phase, edge-triggered clock interface, with fully
registered TIL-compatible inputs and outputs
• Full commercial and military ranges available
• Standard 144-pin grid array package
- Pin and functionally compatible with Weitek 1264/1265

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-2021/-

7-30

IDT721264/IDT721265 32·BIT AND 64·BIT
IEEE FLOATING·POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM
IDT721264 FLOATING-POINT MULTIPLIER

MUXAM
MUXAL
MUXBM
MUXBL

~
LOAD
MODE
!=REG

PIPELINED DATA PATH
STAGE 1
(USED 1 X FOR 32-BIT, 2 X FOR 64-BIT

LOAD
ACCUMULATOR

PIPE 1
PIPELINED DATA PATH
STAGE 2

f2 fa
E8
V;;c = 5V

7-31

IDT721264/IDT721265 32·BIT AND 64·BIT
IEEE FLOATING·POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM
IDT721265 FLOATING-POINT ALU

MUXAM
MUXAL
MUXBM
MUXBL

.J
LOAD
MODE
fi1EG

PIPELINED DATA PATH STAGE 1
LOAD
PIPE

PIPE 1
PIPELINED DATA PATH STAGE 2
PIPE 2
PIPELINED DATA PATH STAGE 3
PIPE 3

4

f2 fa
EB
\be = 5V

7-32

IDT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

15

GND

Yo

Y17

Y18

Y4

Y21

Y6

Y7

Y24

Y9

Yll

Y12

Y28

Y3Q

GND

14

Zl

Vee

GND

Y16

Y2

Y19

Y20

Y22

Y25

YlO

Y27

Y13

Y14

NC

Xo

Z3

Z17

Zo

NC

Yl

Y3

Y5

Y23

Y8

Y26

Y29

Y15

Y31

NC

X17

12

Z19

Z18

Z16

NC

X16

X18

11

Z20

Z4

Z2

Xl

X2

~

10

Z22

Z21

Z5

X3

X19

X21

9

Z7

Za

Z23

Xs

X20

Xa

8

Z24

Z9

Z8

X23

X22

X7

7

Z25

Zl1

Z26

Xa

X25

X24

6

Z10

Z12

Z28

X26

XlO

Xg

5

Z27

Z29

Z30

X29

X27

Xll

4

Z13

Z15

NC

X15

X13

X12

3

Z14

Vee

NC

NC

Sl

Ul

NC

GND

Fl

L4

La

NC

X31

X14

X28

2

Z31

NC

S2

Sa

csa

Uo

CLK

F4

Fa

NC

L2

NC

GND

NC

X30

GND

S3

GND

OE

U2

NC

NC

F5

F3

F2

NC

L3

Ll

esc

GND

B

C

D

E

F

G

H

J

K

L

M

N

p

R

13

•

1

A

G144-1

PIN 1 DESIGNATOR

PIN GRID ARRAY

TOP VIEW

7-33

- - - -..--- .....- - -

IDT721264/IDT721265 32·BIT AND 64·BIT
IEEE FLOATING·POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM

COMMERCIAL

RATING
Terminal Voltage
with Respect to
GND

-0.5 to +7.0

TA

Operating
Temperature

Oto +70

TBIAS

Temperature
Under Bias

-55 to +125

TSTG

Storage
Temperature.... ...

RECOMMENDED DC OPERATING CONDITIONS
MILITARY
-0.5 to +7.0

~55

to +125

-65 to +135

UNIT
V

°C
°C

;"55 to +125

-65 to + 155

°C

50

50

mA

DC Output Current

MIN.

TYP.

MAX.

UNIT

VCeM

Military Supply Voltage

4.5

5.0

5.5

V

Vee

Commercial Supply Voltage

4.75

5.0

5.25

V

GND

Supply Voltage

0

0

0

V

VIH
VIL

Input High Voltage

2.0

-

-

V

Input Low Voltage

-

-

0.8

V

PARAMETER

SYMBOL

NOTE:
1. 1.5V under shoots are allowed for 10ns once per cycle.

lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
(Commercial Vee = 5V ± 5%. TA = O°C to 70°C. Military Vee = 5V ±10%. TA = -55°C to + 125°C)
SYMBOL

PARAMETER

COMMERCIAL
MIN.
MAX.
10

TEST CONDITIONS

Ilul

Input Leakage Current

Vee = Max.• VIN = OtoVce

IILol

Output Leakage Current

Hi Z. Vee = Max .• VOUT = 0 to Vee

lee(1)

Operating Power Supply Current

Outputs Open. \be = Max.

'cea

Quiescent Power Supply Current

\'IN ;:: Vee - 0.2V. VIN :50.2V. Vee = Max.

MILITARY
MIN.
MAX.
20
-

UNIT
~A

'ee/1(1.2)

Increase in Power Supply CurrenVMHz Vee = Max .• f > 10MHz

-

4

-

VOH

Output High Voltage

Vee = Min .• IoH = -2.0mA

2.4

-

2.4

-

V

VOL

Output Low Voltage

Vee = Min .• IoL = 8mA

-

0.4

-

0.4

V

10
100
5

20

~A

120

mA

5

mA

6

mA/MHz

NOTES:
1. Icc is measured at 10MHz and VIN = TTL voltages. For frequencies greater than 10MHz. the following equation is used for the commercial range:
Icc = 100 + 4(f-10)mA. wheref = operating frequency in MHz. For the military range. I ce= 120 + 6(f-10) wheref = operating frequency in MHz.
2. For frequencies greater than 10MHz.

Vec

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
3ns
1.5V
1.5V
See Figure 1

8100
OUTPUT
PiN
40*pF

*Includes scope and jig.
Figure 1. Output Load

7-34

----•... _ - - - - - - - - - - - - - - - - - - - - - - - 1DT121264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING CONDITIONS
(Commercial Vcc
SYMBOL

= 5V ± 5%, TA = OOC to 70°C, Military Vcc = 5V ±10%, TA = -55°C to + 125°C)
PARAMETER

tCY = 30ns
MIN.
MAX.

tCY = 40ns
MAX.
MIN.

tCY = SOns
MIN.
MAX.

tCY= 60ns
MIN.
MAX.

UNIT

-

50

-

60

-

25

-

ns

20
20

25

-

ns

13

-

15

-

15

-

ns

3

-

3

-

3

-

ns

tCY

Clock Cycle Time

30

-

40

tCH

Clock HIGH Time

12

15

tCl

Clock LOW Time

12

-

ts

Input Set-up Time

11

tH

Input Hold Time

2

-

15

ns

AC ELECTRICAL CHARACTERISTICS
(Commercial Vcc = 5V ± 5%, TA = O°C to 70°C, Military \tc = 5V ±10%, TA = -55°C to
SYMBOL

PARAMETER

tCY = 30ns
MIN.
MAX.

tCY = 40ns
MIN.
MAX.

+ 125°C)
tCY = 50ns
MIN.
MAX.

tCY = 60ns
MIN.
MAX.

UNIT

too

Output Delay Time

-

28

-

30

-

35

-

35

ns

tvo

Output Data Valid

5

-

5

-

5

-

5

-

ns

toz

Output Disable Time

25

ns

35

-

35

25

-

35

Output Enable Time

-

30

tzo

-

35

ns

-

270
180
270

-

360
240
360

-

450
300
450

-

-

540
360
540

ns
ns
ns

60
60
120

-

80
80
160

-

100
100
200

-

-

120
120
240

ns
ns
ns

-

360
210
300

-

480
280
400

-

-

600
350
500

-

720
420
600

ns
ns
ns

tLA

Total Latency Time
IDT721265 ALU All Functions
IDT721264 MPY 32-Bit Functions
IDT721264 MPY 64-Bit Functions

-

-

30

-

-

top

Pipelined Time per Stage
IDT721265 ALU All Functions
IDT721264 MPY 32-Bit Functions
IDT721264 MPY 64-Bit Functions

t LAp

Pipelined Total Latency
IDT721265 ALU All Functions
IDT721264 MPY 32-Bit Functions
IDT721264 MPY 64-Bit Functions

Array Time
(IDT721265)

A. B register to Z register.
pipeline registers transparent

-

100

-

120

-

150

-

180

ns

Array Time
(IDT721264)

Time to Make One Pass Through
Multiplier Array for 64-Bit or 32-Bit

-

60

-

80

-

100

-

120

ns

tP64

Time for a 64-Bit Result to go from
the Pipeline Register to the Input
Register of the Z-Reg (DM. DL
Transparent)

-

90

-

120

-

150

-

180

ns

t p32

Time for a 32-Bit Result to go from
the Pipeline Register to the Input
of the DM. DL

-

60

-

80

-

100

-

120

ns

tFlOW64

Time Required for 64-Bit Data to Make
One Pass Through the Array and the
Transparent Pipeline Registers and
Transparent DM. DL to the Input of
the Z-Reg

-

120

-

160

-

200

-

240

ns

tFlOW32

Time Required for 32-Bit Data to Make
One Pass Through the Array and the
Transparent Pipeline Registers and
Transparent DM. DL to the Input of
the Z-Reg

-

120

-

160

-

200

-

240

ns

-

-

-

7-35

-

IDT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS:

GENERAL OPERATING MODES

INPUTS:

Both the Multiplier and the ALU are architected identically with
two input ports and one output port that surround the pipe lined
arithmetic array. The function control (6-bits) controls the selection
of the arithmetic operations with the input and output ports controlled by a total of 8 bits of the load and unload control registers.

XO-31 (Input Operand)
X operand inputs, 32-bit.
YO-31 (Input Operand)
Y operand inputs, 32-bit.

INPUT PORTS
The 101721264 multiplier and the 101721265 ALU have identical input and control structures that handle data on two 32-bit
buses (X and Y). The on-chip registers (AL, AM, BL, BM) can be
written from either of the buses or data can be passed from the inputs directly into the arithmetic unit.
Both devices can be used in a range of bus configurations for
operations in both 32-bit and 64-bit by configuring the input data in
combination with the high bandwidth output. Transfers of data input and output can be made at twice the pipeline rate. The input
buses are fully registered and can be configured for one or two
32-bit inputs or one 64-bit output. These registers are loaded on
each LOW-to-HIGH transition of the clock provided CSL is held
LOW.

CONTROL:

Lo-4 (load Control)
The input configuration of the 101721264 and 101721265 can be
configured through the use of the 5-bit load control to specify the
destination of the data from the X and Y inputs to the AM, AL, BM,
BL registers or the arithmetic array.

Fo-s (Function Control)
The function configuration of the 101721264 and 101721265
can be configured through the use of the 6-bit function control to
specify the operation to be performed. See Tables 3 and 4 for the
specific function controls for the multiplier and ALU.
UO-2 (Unload Control)
The unload control (UO-2) chooses the source of the output.

LOAD CONTROL

CSl (Input Enable)
When CSL is low, input ports X and Yare enabled. l.!J£!:!t data
buses may be shared with the ALU and multiplier with CSL.
CSU (Synchronous Output Enable)
When CSU is low, output port Z is enabled. Therefore,
microcode can control the three-stating of the Z output. Since CSL
is pipelined, it takes effect 2 clock cycles after it is asserted.
OE (Asynchronous Output Enable)
When DE is high, o~t port Z is enabled. When DE is high, the
Z output is enabled if CSU is low.
ClK (Clock)
The clock input.

The Load Control (Lo-4) is used to transfer data from the input
ports to the internal registers or the arithmetic array. La controls the
initiation of an operation. When this input is LOW only a data transfer occurs while, when it is held HIGH, data is transferred and an
operation is begun. The sequence of events is as follows: two registers (AREG and BREG) are loaded from the specified AL, AM, BL,
BM register and the X and Y ports and the FREG is loaded from port
F while, on the next cycle, the specified operation in the FREG begins with the data already loaded into the AREG and BREG. The X
and Y ports can be used as single operand operations and must be
loaded into the AREG. The configuration of these ports can be accomplished by using the Mode bits M15 and M14 for 16-, 32- and
64-bit data. The most significant halves of the AREG and BREG
must be loaded with any 32-bit operands.

OUTPUTS:

UNLOAD CONTROL

Zo-31 (Result)
The Z result output, 32-bit, three-state.

The Unload Control (UO-2) chooses whether the OM or OL register is sent to the Z register. The DM register stores the result of 32-bit
floating-point operations. With 64-bit operations, the most significant 32 bits are stored in the OM register; the least significant half is
stored in the OLregister. A 32-bit result is sentfrom the Z register to
the Z output port on each clock cycle.

SO-3 (Status)
The 4-bit status output indicates any exceptions which resulted
from multiplier or ALU operations.

POWER SUPPLY:
Vee (Power Supply)
Two power supply pins, 5V.
GND (Ground)
Eight ground pins,

av.

7-36

- - _ ..... - - - - - - - - - - - - - - - - - - - - - IDT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 1. LOAD CONTROL TRUTH TABLE
LOAD OPERATION

L4

L3

L2

L1

Lo

0

0

0

0

0

(0)

(NOP)

0

0

0

0

1

(1)

AM, AL -+ AREG; BM, BL -+ BREG; F1 -+ FREG

0

0

0

1

0

(2)

Load Mode

0

0

0

1

1

(3)

-Reserved

0

0

1

0

0

(4)

Y1 -+ AL; X1 -+ BL

0

0

1

0

1

(5)

Y1 -+ AL; X1 -+ BL; AM, Y1 -+ AREG; BM, X1 -+ BREG; F1 -+ FREG

0

0

1

1

0

(6)

Y1 -+ AM; X1 -+ BM

0

0

1

1

1

(7)

Y1 -+ AM; X1 -+ BM; Y1, AL -+ AREG; X1, BL -+ BREG; F1 -+ FREG

0

1

0

0

0

(8)

X1 -+ BM; Y1 -+ BL

0

1

0

0

1

(9)

X1 -+ BM; Y1 -+ BL; AM, AL -+ AREG; X1, Y1 -+ BREG; F1 -+ FREG

0

1

0

1

0

(10)

X1 -+ AM; Y1 -+ AL

0

1

0

1

1

(11)

X1 -+ AM; Y1 -+ AL; X1, Y1 -+ AREG; BM, BL -+ BREG; F1 -+ FREG

0

1

1

0

0

(12)

X1 -+ AL; Y1 -+ BL

0

1

1

0

1

(13)

X1 -+ AL; Y1 -+ BL; AM, X1 -+ AREG; BM, Y1 -+ BREG; F1 -+ FREG

0

1

1

1

0

(14)

X1 -+ AM; Y1 -+ BM

0

1

1

1

1

(15)

X1 -+ AM; Y1 -+ BM; X1, AL -+ AREG; Y1, BL -+ BREG; F1 -+ FREG

1

0

0

0

0

(16)

Y1 -+ BM

1

0

0

0

1

(17)

Y1 -+ BM; AM, AL -+ AREG; Y1, BL -+ BREG; F1 -+ FREG

1

0

0

1

0

(18)

Y1 -+ BL

1

0

0

1

1

(19)

Y1 -+ BL; AM, AL -+ AREG; BM, Y1 -+ BREG; F1 -+ FREG

1

0

1

0

0

(20)

Y1 -+ AL

1

0

1

0

1

(21)

Y1 -+ AL; AM, Y1 -+ AREG; BM, BL -+ BREG; F1 -+ FREG

1

0

1

1

0

(22)

Y1 -+ AM

1

0

1

1

1

(23)

Y1 -+ AM; Y1, AL -+ AREG; BM, BL -+ BREG; F1 -+ FREG

1

1

0

0

0

(24)

X1 -+ BM

1

1

0

0

1

(25)

X1 -+ BM; AM, AL -+ AREG; X1, BL -+ BREG; F1 -+ FREG

1

1

0

1

0

(26)

X1 -+ BL

1

1

0

1

1

(27)

X1 -+ BL; AM, AL -+ AREG; BM, X1 -+ BREG; F1 -+ FREG

1

1

1

0

0

(28)

X1 -+ AL

1

1

1

0

1

(29)

X1 -+ AL; AM, X1 -+ AREG; BM, BL -+ BREG; F1 -+ FREG

1

1

1

1

0

(30)

X1 -+ AM

1

1

1

1

1

(31)

X1 -+ AM; X1, AL -+ AREG; BM, BL -+ BREG; F1 -+ FREG

LOAD SEQUENCES
64-BIT OPERATIONS USING THE X AND Y PORTS
AS A SINGLE 64-BIT PORT

32-BIT OPERATIONS WITH TWO 32-BIT PORTS
OPERATION
LOAD MODE (1)

L4

L3

12

L1

Lo

INST#

0

0

0

1

0

(2)

OPERATION

Y1, AL -+ AREG; X1, BL-+
BREG; F1 -+ FREG;
0
0
1
1
(7)
1
Y1 -+ AM; X1 -+ BM
NOTE:
1. If the mode does not change between operations, it does not need to be
reloaded.

7-37

L4

L3

12

L1

Lo

INST#

LOAD MODE

0

0

0

1

0

(2)

X1 -+ AM; Y1 -+ AL

0

1

0

1

0

(10)

AM, AL -+ AREG; X1, Y1 -+
BREG; F1 -+ FREG;
X1 -+ BM; Y1 -+ BL

0

1

0

0

1

(9)

1DT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 2 UNLOAD CONTROL TRUTH TABLE
EDGE #2

EDGE#1

CSU

U2

Ut

Uo

0

0

0

0

DM31-0~ ZREG

STREG1 ~ S+, ZREG ~ Z+

0

0

1

0

DM 31-16, DL 31-16 ~ ZREG

STREG1 ~ S+, ZREG ~ Z+

0

1

0

0

DL31-0~ ZREG

STREG1 ~ S+, ZREG ~ Z+

DM 15- 0, DL 15- 0 ~ ZREG

STREG1 ~ S+, ZREG ~ Z+

0

1

1

0

1

X

X

X

S+ and Z+ Tri-Stated

TABLE 3. FUNCTION CONTROLS FOR FLOATING-POINT MULTIPLIER
F2

~

Fo

0

0

0

(0)

0

0

1

0

1

0

0

1

1
1

MNEMONIC

OPERATION

DESCRIPTION

F32x F32

MUL32

Single Multiply

(1)

F64 x F64

MUL64

Double Multiply

(2)

W32x F32

MULAW32

Single Multiply, A Wrapped

1

(3)

W64x F64

MULAW64

Double Multiply, A Wrapped

0

0

(4)

F32xW32

MULBW32

Single Multiply, B Wrapped

0

1

(5)

F64xW64

MULBW64

Double Multiply, B Wrapped

1

1

0

(6)

W32xW32

MULABW32

Single Multiply, A & B Wrapped

1

1

1

(7)

W64xW64

MULABW64

Double Multiply, A & B Wrapped

fs

~

F3

0

0

0

0

0

1

0

1

0

OPERATION

(0)

MNEMONIC

DESCRIPTION

AxB

MUL

Multiply

(1)

IAlx B

MULABSA

B Times Magnitude of A

(2)

Ax IBI

MULABSB

A Times Magnitude of B

0

1

1

(3)

IAI x IBI

MULABSAB,

Magnitude of A Times B

1

0

0

(4)

-(Ax B)

MULNEG

Multiply and Negate

1

0

1

(5)

(-lAb x B

MULNEGA

B Times Negative Value of A

1

1

0

(6)

Ax<-iBj)

MULNEGB

A Times Negative Value of B

1

1

1

(7)

-clAlxlBb

MULNEGAB

Negative Value of A Times B

7-38

"

----- - - - - - - - - - - - - - - - - - - - - - - - - ...

1DT121264/IDT121265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES
operands (ONRMs) to zero and rounds underflow or unnormalized
results (U NRMs) to zero. Mode bit M2 must be set to zero in the Fast
mode.

MULTIPLIER OPERATION: IDT721264
The 101721264 has exception detection handling circuitry, a
56 x 28-bit multiplier array, an exponent adder circuit, a normalizing shifter and a rounding circuit for IEEE format adjustment.
The exception detection circuit is at the beginning of the multiplier. Exceptions can be Not-a-Number (NaN) or a denormalized
input and timings are handled like normal numbers.
A clocked 54 x 28-bit multiplier array multiplies the mantissa
portion of the floating-point number. A single precision multiply
takes one pass through the array; a double precision multiply takes
two passes. Each pass through the array takes two clock cycles.
Partial results are stored in the accumulator (an adder and a
transparent latch). The cycle time determines the number of clock
cycles required to complete a multiplication. A long cycle time requires fewer clock cycles to complete the operation. A clock time
of 30ns calls for four cycles to perform a double preciSion multiply.
In the first two clock cycles, the operands are multiplied in the array. On the second cycle, the accumulator register must be latched
to retain the results. On the fourth cycle the accumulator register
must be transparent so that the results are passed to the pipeline
register. An accumulator timer can be set to latch or pass results
one to four clock cycles after the beginning of the operation. The
timer is reset at the beginning of each operation.

o

IEEE Mode
Fast Mode

ROUNDING MODE
Mode bits M1, M2 and M3 select the Rounding mode. Renormalization and IEEE rounding functions are performed between
the pipeline register and the OM and DL registers.
M3

M2

o
o

DESCRIPTION

o

Round to nearest value or if a tie, round
to even significand

o

Round towards positive infinity

Round to zero
, Round towards negative infinity

PIPELINE CONFIGURATION
Mode bit M4 controls whether the OM and OLregisters are transparent. Mode bit M5 controls whether the pipeline register is
transparent.

MULTIPLIER FUNCTION CONTROL

Y

i

DESCRIPTION

Mo

The multiplier controls are given in Table 3. The multiplier func-

ro:~ COEidf ::efl in th:tr~;aT :~

DESCRIPTION

o

Transparent DM, DL
Latched DM, DL

CS:
MB:
MA:
WB:
WA:

1- >
1- >
1- >
1- >
1->

Complement sign of result
Magnitude of B
Magnitude of A
Operand B is wrapped
Operand A is wrapped

EDGE 0

0

0
.1

F -+ F1

F -+ M3-e
F -+ M7-4

1

0

F - f F1

F-+M l1 - 8

1

1

F -+ F1

F -+ F1

Transparent pipeline regis~er

1

Latched pipeline register

Mode bits M7-6 control the timing of the partial product accumulator. The accumulator is alternately latched and made transparent
every N + 1 cycles, where N is the value of M7-6. The accumulator
timer is reset at the beginning of each operation. The accumulator
timer is used to achieve maximum throughput.

EDGE 1

F4

0

DESCRIPTION

0

ACCUMULATOR ADVANCE CONTROL

SO: 0- > Single preciSion operation
SO: 1- > Double precision operation
The Mode Control bits are loaded from the Fe-3 function control
bits. The F5-4 function control bits determine which of the four 4-bit
mode control subsets is loaded.
Fs

Ms

M7

Ms

o
o

0

N

o

F -+ M15-12

DESCRIPTION
N

N
N

= 1, Clock/1
= 2, Clock/2
= 3, Clock/3
= 4, Clock/4

MULTIPLIER MODE CONTROL

PIPELINE ADVANCE CONTROL

IEEE OR FAST MODE

Mode bits M11-8 control the pipeline advance control of the pipeline registers. If M11-8 are all zeros, the pipeline registers will only
be latched at the beginning of an operation. If M11-8 are non-zero
values, N, the pipeline registers will be clocked at the beginning of
every operation and every N cycles after the beginning of every operation. The internal pipeline advance timer is reset at the beginning of every operation.
For example, if N = 4 and operations are started on cycles 0, 6
and 10, pipeline advances will occur on cycles 0, 4, 6,10,14,18
and so on. The pipeline advance control is used to achieve maximum throughput.

Mode bit Me controls the way denormalized numbers are handled. If Me is 0, the IEEE format is used. The multiplier generates
denormalized operand exceptions and produces UNRM values on
underflow exceptions. The denormalized operands are sent to the
ALU to be wrapped; the wrapped numbers (WNRMs) can then be
multiplied. The IEEE Compatibility section discusses this in detail.
If Me is 1, the Fast mode is used in order to achieve the maximum performance, by eliminating the direct handling of
denormalized numbers. The multiplier flushes denormalized

7-39

IDT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

M10 Mg

M11
0
0

0

0

ALU MODE CONTROL

DESCRIPTION

Ma

0

0

MILITARY AND COMMERCIAL TEMPERATURE RANGES

0

N = 0, pipeline registers are latched

IEEE OR FAST MODE

1

N = 1, pipeline registers are clocked
1 cycle after first operation

Mode bit Mo controls the way denormalized numbers are handled. If Mo is 0, the IEEE format is used. The ALU generates
denormalized operand exceptions and produces UNRM values on
underflow exceptions. The IEEE Compatibility section discusses
this in detail.
If Mo is 1, the Fast mode is used in order to achieve the maximum performance by eliminating the direct handling of denormalized numbers. The ALU flushes denormalized operands (UNRMs)
to zero and rounds underflow or unnormalized results (UNRMs) to
zero Mode bit M2 must be set to zero in the Fast mode

0

0

1

0

N = 2, pipeline registers are clocked
2 cycles after first operation

0

0

1

1

N = 3, pipeline registers are clocked
3 cycles after first operation

1

1

1

1

N = 15, pipeline registers are clocked
15 cycles after first operation

BUS BANDWIDTH CONTROL
Mode bits M13-12are not used. Mode bits M15-14control the input
bus bandwidth of the X and Y input ports. When M15-14 are set to
zero, the X1 and Y1 registers are loaded every clock cycle from the
X and Y ports.
M 15

M14

DESCRIPTION

DATA PATH
X-> X1; Y-> Y1

0

0

N = 1, 32-but bus

0

1

N = 2, Reserved

1

0

N = 3, Unused

1

1

N = 4, Unused

DESCRIPTION

Mo
0

IEEE Mode

1

Fast Mode

ROUNDING MODE
Mode bits Ml, M2 and M3 select the Rounding mode. Renormalization and IEEE rounding functions are performed between
the pipeline register and the OM and OL registers
M3

0

M2
0

DESCRIPTION

Ml
0

Round to nearest value or if a tie, round
to even significand

0

1

0

Round to zero

1

0

0

Round towards positive infinity

ALU OPERATION: IDT721265

1

1

0

Round towards negative infinity

The 101721265 ALU has five basic components: exception detection circuitry, a shifter to normalize the smaller of the two input
operands, a 57-bit adder, a shifter to renormalize the result and
IEEE rounding circuitry. The 101721265 is easily considered as an
ALU with multiple internal pipeline registers. The internal pipeline
registers and the OM and OL registers can be made transparent by
mode bits M7-4.
The pipeline registers are clocked at the beginning of each operation and every N cycles thereafter, when N is given a value by
mode bits Ml1-8.

X

X

1

Round to zero, all cases

PIPELINE CONFIGURATION
Mode bits M7-4 determine which of the pipeline registers and
OM and OL registers are made transparent. If the mode bit is low,
the corresponding register is made transparent. If the mode bit is
high, the register is latched by the rising edge of the clock. If the
pipeline registers are made transparent, the latency time is reduced at the expense of slower overall throughput. The highest
system throughput results from enabling all the pipeline registers.
Mode bit M4 controls whether the OM and OL registers are transparent. Mode bits M7-5 control which of the pipeline registers are
transparent.

ALU FUNCTION CONTROL
The 101721265's function controls are shown in Table 4. The
lOT superset functions are highlighted in Table 5.
The Mode Control bits are loaded from the F3-o function control
bits. The F5-4 function control bits determine which of the four 4-bit
mode control subsets is loaded.
EDGE 0

EDGE 1

Fs

F4

0

0

F -+ F1

0

1

F -+ F1

F1 -+ Mr-4

1

0

F -+ F1

F1-+M,1-8

1

1

F -+ F1

F1 -+ M,5-12

PIPELINE ADVANCE CONTROL

F1 -+ ~-o

Mode bits Mll-8 control the pipeline advance control of the pipeline registers. If M11-8 are all zeros, the pipeline registers will only
be latched at the beginning of an operation. If Ml1-8 are non-zero
values, N, the pipeline registers will be clocked at the beginning of
every operation and every N cycles after the beginning of every operation. The internal pipeline advance timer is reset at the beginning of every operation.

7-40

1DT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

For example, if N = 4 and operations are started on cycles 0, 6
and 10, pipeline advances will occur on cycles 0, 4,6, 10, 14, 18
and so on. The pipeline advance control is used to achieve maximum throughput.

BUS BANDWIDTH CONTROL
Mode bits M13-12are not used. Mode bits M15-14 control the input
bus bandwidth of the X and Y input ports. When M15-14 are set to
zero, the X1 and Y1 registers are loaded every clock cycle from the
X and Y ports.

MIl

M 10

Mg

Ma

DESCRIPTION

0

0

0

0

N = O. pipeline registers are latched

MIS

0

0

0

1

N = 1. pipeline registers are clocked
1 cycle after first operation

0

1

N = 2, Reserved

0

1

0

N = 2, pipeline registers are clocked
2 cycles after first operation

0

0

1

0

N = 3, Unused

0

0

1

1

N = 3, pipeline registers are clocked
3 cycles after first operation

1

1

N = 4, Unused

1

1

1

1

N = 15, pipeline registers are clocked
15 cycles after first operation

7-41

M14

0

DESCRIPTION

DATA PATH

N = 1, 32-but bus

X-t X1; Y -t Y1

1DT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 4 FUNCTION CONTROLS FOR ALU-IDT721265
OPERATION
F2
Fl
Fo
F4
Fs
F:!

DESCRIPTION

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

(0)
(1)
(2)
(3)
(4)
(5)
(6)
(7)

F32 - F32
F64 - F64
IF32 - F321
IF64 - F641
IF321-IF321
IF641-IF641

Single Subtract
Double Subtract
Single ABS Subtract
Double ABS Subtract
Single Subtract ABS (1)
Double Subtract ABS(l)
RESERVED
RESERVED

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)

-F32 + 0
-F64 + 0
2 - F32
2 - F64
-F32 - F32
-F64 - F64

Single Negate
Double Subtract
Single 2-A (1)
Double 2-A(1)
Single 2's Complement of Addition (1)
Double 2's Complement of Addition (1)
RESERVED
RESERVED

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)

F32 + F32
F64 + F64
IF32 + F321
IF64 + F641
IF321 + IF321
IF641 + IF641

Single Addition
Double Addition
Single ABS Addition
Double ABS Addition
Single Add ABS
Double Add ABS
RESERVED
RESERVED

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)

F32 + 0
F64 + 0
F32 + IF321
F64 + IF641
IF321 + 0
IF641 + 0

Single Pass
Double Pass
Single Mixed Addition (1)
Double Mixed Addition (1)
Single Pass ABS
Double Pass ABS
RESERVED
RESERVED

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)

COMP F32 - F32
COMP F64 - F64
F32 -IF321
F64 -IF641
COMP IF321-IF321
COMP IF641-IF641

Single Compare
Double Compare
Single Mixed Subtract (1)
Double Mixed Subtract(l)
Single Compare ABS
Double Compare ASS
RESERVED
RESERVED

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
0
0
1
0
1

(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)

COMP F32 - 0
COMP F64 - 0
-IF321 + 0
-IF641 + 0
-IF321 -IF321
-IF641 -IF641

Single Compare with Zero
Double Compare with Zero
Single Negate of ASS(l)
Double Negate of ASS(l)
Single 2's Complement of Add ASS(l)
Double 2's Complement of Add ASS(l)
RESERVED
RESERVED

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0

0

0
1
0
0
0
1

(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)

U32 --+
U64 -}
D32 --+
D64 --+
U32 --+
U64 --+

a

0
0
0
0
1
1
1
1

Single Unwrap Exact
Double Umviap Exact
Single Wrap
Double Wrap
Single Unwrap Inexact
Double Unwrap Inexact
RESERVED
RESERVED

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)

F32 --+ 132
F64 --+ 164
132 --+ F32
164 --+ F64
F32 --+ F64
F64 --+ F32

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

...

a
1
1
0
0
1
1
0
0
1
1
0

a
1
1

a
1
0
1

a
0
0
1
0
1

NOTE:
1. IDT proprietary functions. Reserved functions in Weitek-Compatible mode.

7-42

D32 EX
D64 EX
W32
W64
D321NX
D64 INX

Single Fix
Double Fix
Single Float
Double Float
Single Convert to Double
Double Convert to Single
RESERVED
RESERVED

IDT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 5.IDT721265 ALU SUPERSET FUNCTION CONTROLS
OPERATION

DESCRIPTION

Fs

F4

f:J

F2

F1

Fo

0
0

0
0

0
0

1

0
0

0
1

(4)
(5)

IF321-IF321
IF641 - IF641

Single Subtract Absolute Value
Double Subtract Absolute Value

0
0

0
0

0
1

(10)
(11)

2 - F32
2- F64

Single 2 - A
Double 2 - A

0
0

0
0

0
1

(12)
(13)

-F32 - F32
-F64 - F64

Single 2's Complement of Addition
Double 2's Complement of Addition

0
0

0

(26)
(27)

F32 + IF321
F64 + IF641

Single Mixed Addition
Double Mixed Addition

0
0

0

(34)
(35)

F32 -IF321
F64 -IF641

Single Mixed Subtract
Double Mixed Subtract

0
0

0

(42)
(43)

-IF321 + 0
-IF641 + 0

Single Negate of Absolute Value
Double Negate of Absolute Value

0

(44)
(45)

-IF321 - IF321
-IF641 - IF641

Single 2's Complement of Add Absolute Value
Double 2's Complement of Add Absolute Value

0
0
0
0

0
0
0
0

0
0

0
0
0
0

0
0

RESULTS STATUS

During certain operations, more than one exception may occur.
The higher priority exception will be indicated on the result status
output.

The 4-bit Result Status (S3-0) indicates any exceptions or conditions of the results of a floating-point operation. Comparison conditions are shown on S3-0 when comparison operations are performed. Exception status is shown on 83-0 when exceptions occur
on an operation. Table 6 details the results status indicators.

PRIORITY
Highest

EXCEPTION
Operands A & B are NAN
Operand A is NAN

TABLE 6. STATUS TRUTH TABLE

Operand B is NAN
S+ S+ S+ s+
3
1
2
0

COMPARISON
CONDITION

0

0

0 (0)

Equal

Result

0

0

0

1 (1)

Less than

Result
-infinity, exact

Greater
than

Result finite and < > 0,
exact

0

1

0 (2)

0

0

1

1 (3)

Operands A & Bare Denormalized

= + 0 or -0, exact
= + infinity or

0

0

Invalid Operation

EXCEPTION STATUS

Operand A is Denormalized
Operand B is Denormalized
Underflow & Inexact
Underflow

Result finite and < > 0,
inexact

0

1

0

0 (4)

-Not used

0

1

0

1 (5)

Overflow & inexact

0

1

1

0 (6)

Underflow

0

1

1

1 (7)

Underflow & inexact

1

0

0

0 (8)

Operand A is denormalized

1

0

0

1 (9)

Operand B is denormalized

1

0

1

o (10)

Operands A & Bare
denormalized

1

0

1

1 (11)

-Not used

1

1

0

0 (12)

Operand A is NAN

1

1

0

1 (13)

Operand B is NAN

1

1

1

0 (14)

1

1

1

1 (15)

Overflow & Inexact
Lowest

TIMING
The 101721264 and 101721265 are designed to be able to operate as pipelined processors, to maximize systems throughput or to
be able to operate as flow-through processors to minimize the latency period from input to output result. The following figures explain the various timing constraints for pipelined and flow-through
modes in both single and double preciSion operations.

Operands A & B are NAN
Unordered

Result is Finite < > 0, Inexact

Invalid Operation

7-43

IOT721264/IOT721265 32·81T AND 64·81T
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

should be transparent (M4 = 0). The timing is shown in Figure 3.
The first cycle after the inputs and function code are loaded, the
64-bit multiplication begins. Two cycles later, the accumulator
stores the partial product of the first pass through the array. Two
cycles later, the unrounded results are latched into the pipeline
register. Three cycles later (tp64), the result is available on the output port.

MULTIPLIER TIMINGS
64-BIT MAXIMUM PIPELINED THROUGHPUT
For maximum throughput for 64-bit multiplications, the accumulator timer should be set to clock/2 (M7-6 = 1), the pipeline
advance control should be set to four (Ml1-8 = 4), the pipeline registers should be latched (Ms = 1) and the OM and OL registers
CLOCK
CSL, LOAD

FUNCTION

1----+--<

X,Y
CSU, UNLOAD

STATUS ~--+--~--~--+--~--~--1---r--+---1~

z ~--~I-----4-----+-----+----~----;-----;-----+-----+-----r-~

-I

110111 - - - - top = 120ns
~11~-----------------------t~p=30ons------------------------~·~1

tCY= 30ns

Figure 3. IOT721264 64·bit Pipelined Operation Timing

32-BIT MAXIMUM PIPELINED THROUGHPUT

The first cycle after the inputs and function code are loaded, the
32·bit multiplication begins. Two cycles later, the unrounded reo
suits are latched into the pipeline register. Two cycles later, the reo
suits are at the input of the OM register. One cycle later (tp32), the
result is available at the input of the ZREG and can be output on the
following cycle.

For maximum throughput for 32-bit multiplications, the accumulator timer should be set to clock/1 (M7-6 = 0), the pipeline
advance control should be set to two (Mll-8 = 2), the pipeline registersandtheOM and OL register should be latched (Ms = M4 =1).
The result of the multiplication will be stored on the most significant
half of the OM register. The timing is shown is Figure 4.
CLOCK
CSL,LOAD

FUNCTION

X,Y
CSU,UNLOAD ~---1-----+----~----+-----~

STATUS ~--4---+---+---4---+---+-----"f--<

Z

~-----~---4~---+-----+----~----~----~-{

II

I+- top = 60ns-l

t~p = 210ns -------------~-I

Figure 4. 1OT721264 32·bit Pipellned Operation Timing

7-44

tCY= 30ns

--

--

------------------------------------

1OT721264/IOT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The first cycle after the inputs and function code are loaded, the
64-bit multiplication begins. Two cycles later, the accumulator
stores the partial product of the first pass through the array. Four
cycles later (tFLoW64), the result is available at the input of the ZREG
and can be output on the following cycle.

64-BIT MINIMUM LATENCY FLOW-THROUGH
For minimum latency for 64-bit multiplications, the accumulator
timer should be set to clock/2 (M7-6 = 1), the pipeline advance
control should be set to zero (Mll-B = 0) and the pipeline registers
and OM and DL registers should be transparent (Ms = M4 = 0).
The timing is shown is Figure 5.
CLOCK
CSL, LOAD

FUNCTION 1---+--<

X.Y
CSU, UNLOAD

STATUS

~--_4----_+----~----+_--~r_--_+----_r~

1-----4-----+----~----+_--~r---_+----_+----;_----+_~

z ~--_+----4_----~--_+----4_----~--_4----_r----+_~

I10011------------- tLA = 2 7 0 n s - - - - - - - - - - - i..~1

tey = 30ns

Figure 5. 1OT721264 64-bit Flow-through Operation Timing

32-BIT MINIMUM LATENCY FLOW-THROUGH

The result of the multiplication wi II be stored on the most significant
half of the OM register. The timing is shown is Figure 6.
The first cycle after the inputs and function code are loaded, the
32-bit multiplication begins. Four cycles later (tFLOW32), the result is
available at the input of the ZREG and can be output on the following cycle.

For minimum latency for 32-bit multiplications, the accumulator
timer should be set to clock/2 (M7-6 = 1), the pipeline advance
control should be set to zero (Mll-8 = O) and the pipeline registers
and OM and DL registers should be transparent (Ms = M4 = 0).

CLOCK
CSL, LOAD

FUNCTION

x, Y
CSU, UNLOAD

STATUS

1-----4-----+----~---+_-<

I----~----_+----+----+_----I---_+__<

z ~--_+----+----+_---+----+----+_~

I"'"

11--------

~

= 180ns

tCY =

Figure 6. 1OT721264 32-bit Flow-through Operation Timing

7-45

30ns

1OT121264/10T121265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

should be set to two (Mll-S = 2) and all pipeline registers should be
enabled (M7 = Me = M5 = M4 = 1). The timing is shown in
Figure 7.

ALUTIMINGS
32-BIT AND 64-BIT MAXIMUM PIPELINED
THROUGHPUT
The ALU has the same throughput for 32-bit and 64-blt operations. For maximum throughput, the pipeline advance control
CLOCK
CSL,LOAD

FUNCTION

X,Y
CSU,
UNLOAD
STATUS

z
14

-1------------ ~p

= 360ns

tCY

----------~·I

= 30ns

Figure 7. 10T121265 32-blt and 64-blt Plpellned Timing.

32-BIT AND 64-BIT MINIMUM LATENCY
FLOW-THROUGH

should be disabled (M7
shown in Figure 8.

=

Me = M5

M4

For minimum latency for ALU operations, the pipeline advance
control should be set to zero (Mll-S = 0) and all pipeline registers
CLOCK
CSL, LOAD

FUNCTION

X,Y

CSU, UNLOAD

STATUS

z
LOAD
MODE
TIME

1---1-------------- ttA = 270ns -----------~
Figure 8. 10T121265 32-blt and 64-blt Flow-through Timing

7-46

=

0). The timing is

IDT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

~--------tCY--------~

~I·
ClK. CLOCK INPUT

A. B. F. l. U INPUTS

OE INPUT

S. C OUTPUT

NOTE:
1. CSU is lOW.

Figure 9. Input/Output Timing (1)

exponent value is e-1023. The fraction value is 1.f, where 1 is the
hidden bit and f is the fraction. The double precision number can
be represented as (1)S x 29-1023 x 1.1.

IEEE COMPATIBILITY
The IDT721264 and IDT721265 conform to the IEEE Standard
754, 1895 Version, which specifies floating-point processor data
formats, rounding modes and exception handling. Many data formats are specified in the IEEE Standard 754: single precision, double precision, normalized numbers, denormalized numbers,
wrapped numbers, zero and infinity. See Table 7. The Gradual Underflow section discusses how denormalized numbers (DNRMs)
are handled.

NORMALIZED NUMBERS (NORM)
Most operations are performed on normalized numbers. In normalized single precision numbers where the exponent ranges from
1 (00000001) to 254 (11111110), the fraction is normalized and the
hidden bit equals 1. This translates to a decimal number range
from 10 +38 to 10-38 for both positive and negative numbers and a
precision of 7 decimal places.
In normalized double precision numbers where the exponent
ranges from 1 to 2046, the fraction is normalized and the hidden bit
equals 1. This translates to a decimal number range from 10+ 307 to
10-308 for both positive and negative numbers and a precision of 15
decimal places.

DATA FORMATS
SINGLE PRECISION
The chip set performs 32-bit and 64-bit IEEE standard floatingpoint operations. The 32-bit data format has a single sign bit, a
23-bit magnitude fraction field and an 8-bit exponent field in the following format:
31 30
Sign bit

I

I

Infinity is defined as an exponent of 1 and a fraction of O. IEEE
Standard 754 defines both positive and negative infinity.

o

23 22
8-bit Exponent

INFINITY

ZERO

23-bit Fraction

Zero is defined as an exponent of 0, the hidden bit of 0 and a
fraction of O. IEEE Standard 754 defines both +0 and -0.

Exponents for normalized single precision numbers range from
1 to 254. Exponents of zero and 255 are reserved for special operands. The exponent bias is + 127, which means that the exponent
value is e-127. The fraction value is 1.f, where 1 is the hidden bit
and f is the fraction. The single precision number can be represented as (1)S x 29- 127 X 1.f.

DENORMALIZED NUMBERS (DNRM)
A denormalized number is defined with an exponent of 0, the
hidden bit of 0 and a non-zero fraction. Only the ALU can directly
handle denormalized numbers. To multiply two denormalized
numbers, the operands must first be wrapped by the ALU, then
sent to the multiplier for the multiplication of two wrapped (and normalized) numbers.

DOUBLE PRECISION
The 64-bit data format has a single sign bit, a 52-bit magnitude
fraction field and an 11-bit exponent field in the following format:
63 62
Sign bit

I

I

A wrapped number is created by normalizing a denormalized
number's fraction and subtracting the number of shifts from the exponent. The fraction is shifted left until the hidden bit is 1. The exponent equals one minus the number of shifts and is in two's complement format.' Only the ALU can wrap denormalized numbers and
the multiplier can operate on one or two wrapped numbers.

o

52 51
11-bit Exponent

WRAPPED NUMBERS (WNRM)

52-bit Fraction

Exponents for normalized double precision numbers range
from 1 to 2046. Exponents of zero and 2047 are reserved for special
operands. The exponent bias is + 1023, which means that the

7-47

IDT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

UN-NORMALIZED NUMBERS (UNRM)

NOT-a-NUMBER (NaN)

An un-normalized number results from an addition or multiplication which is smaller than the minimum representable normalized
number. An un-normalized number has a wrapped exponent, a
hidden bit of 1 and a normalized fraction. The smallest un-normalized number (UNRM.MIN) is the result of multiplying the two
smallest denormalized numbers (DNRM.MIN).

Not-a-Number is a special data format to flag data overflow or
underflow, un initialized operands and invalid operations
(i.e., 0 x 00). Not-a-Number has an exponent of all 1s and a nonzero fraction.

TABLE 7 IEEE SINGLE PRECISION FORMATS SUPPORTED BYTHE IDT721264 AND IDT721265
OPERAND :

.......

EXPONENT

FRACTION

VALUE

HIDDEN BIT

255

ANY

INFINITY

255

ALLO's

1

(_1)s 00

NORM. MAX

254

ALL 1's

1

(-1)s X 2127 x (2)

ANY

1

(-1)S x 2e- 127 x (1.1)

NORM

1 to 254

N/A

NONE

NAN

NORM.MIN

1

ALL O's

1

(-1)s X 2- 126 x (1)

DNRM.MAX

0

ALL 1's

0

(-1)S X 2- 126

DNRM

0

ANY

0

(-1)S x 2- 126 x (0.1)

DNRM.MIN

0

000... 01

0

(-1)S x 2-1262-23

WNRM.MAX

0

ALL 1's

1

(-1)S X 2- 126

ANY

1

(-1)S x 2 e - 127 x (1.1)

-22

ALL O's

1

(-1)S X 2- 149

UNRM.MAX

0

ALL 1's

1

(-1)S X 2- 126

UNRM. MIN

-171

ALL O's

1

(-1)s X 2- 298

0

ALLO's

1

(-1)S 0

WNRM
WNRM.MIN

Oto (-22)

ZERO

died differently in the multiplier and ALU. In the Fast mode the
underflow result is set to zero for both the multiplier and ALU. In the
IEEE mode, the multiplier will not round the underflow result but
will wrap it. The inexact status bit, So, is one if any of the truncated
bits contains a one. The ALU can unwrap the result, using the "UNWRAP EXACT" or"U NWRAP INEXACT" depending on the value of
So. The ALU status register will show whether the result is exact or
inexact.

ROUNDING MODES
The chip set supports the four IEEE Standard 754 rounding
modes: round to nearest, round toward zero, round toward plus
infinity and round toward minus infinity. Biased rounding or unbiased rounding may occur. Biased rounding introduces a small offset in the direction of the bias. IEEE Standard 754 specifies positive
bias, negative bias and bias toward zero. Unbiased rounding
rounds toward the nearest representable number. If a number is
halfway between two representable numbers, the number is
rounded towards the nearest even number which averages the
rounding up and down.

EXCEPTION HANDLING
The chip'set performs exception handling according to the IEEE
Standard 754. The status bits are pipelined synchronously with the
operands and partial results. The status bits are stored in the
STREG1 when the result is clocked into the output register until the
rising edge of the next clock cycle.
The result of an ALU Compare operation is shown on the status
output. A Compare result supersedes an exception status.

ROUND TO NEAREST (RN)
The result is rounded to the nearest representable number. If a
number is halfway between two representable numbers, the number is rounded towards the nearest even number.

ROUND TOWARDS ZERO (RZ)

INEXACT (INX)

The result is rounded to the nearest representable number not
greater in magnitude than the number.

When the result of an ALU or multiplier operation losses accuracy, an Inexact status is shown. The ALU computes more that 23
fraction bits in a single preciSion and 53 bits in double precision. If
any of the lesser significant bits equals 1, then an INX is signaled. In
floating-point to fixed-point conversions, any loss of accuracy will
signallNX. For normalized number operations, INX will not be signaled.

ROUND TOWARD PLUS INFINITY (RP)
The result is rounded to the nearest representable number not
less than the number.

ROUND TOWARD MINUS INFINITY (RM)

UNDERFLOW (UNF)

The result is rounded to the nearest representable number not
greater than the number.
If the result of an operation is less than the minimum
representable number, the underflow condition exists and is han-

Underflow is asserted if a rounded result is less than the minimum normalized number. If the result is exactly zero, UNF will not
be asserted.

7-48

IDT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The following tables represent different results obtained from
different operand formats and rounding modes. Tables for both
IEEE and Fast modes are shown. All results are in the "Result-Exception Status" format.

OVERFLOW {OVF}
Overflow is asserted if a rounded result is greater than the maximum normalized number. The result is either infinity or the largest
representable number and is a factor of the Round mode.
ROUNDING MODE

RESULT

RM or RZ

+ NORM. MAX (positive)

Floating-Point Add/Subtract ("Fast" Mode)
Floating-Point Multiply ("Fast" Mode)
Floating-Point Add/Subtract (IEEE Mode)

-NORM.MAX (negative)

RP or RZ

+ 00

RN or RP

Table 10.

RN or RM

Table 11.

Floating-Point Multiply (IEEE Mode)

Table 12.

Floating-Point Compare Status

Table 13.

Convert Single Precision to Double Precision

Table 14.

Convert Double Precision to Single Precision

-00

(positive)
(negative)

Overflow is also asserted if the result of a floating-to-fixed operation overflows the 32-bit format.

INVALID OPERATION {INV}
The following are Invalid Operations (INV):
• One of the operands is a NaN

• Ox

Table 8.
Table 9.

00

• +00-+00
• -00 + +00

Table 15.

Double Precision Float

Table 16.

Single Precision Float

Table 17.

Double Precision Fixed

Table 18.

Single Precision Fixed

Table 19.

Double Wrap Denormalized Value

• +00 + -00
• -00 - -00

Table 20.

Single Wrap Denormalized Value

Table 21.

Double Unwrap Exact Value

OPERATIONS

Table 22.

Single Unwrap Exact Value

TABLE 8. FLOATING-POINT ADD/SUBTRACT ("FAST" MODE)
INF

OK-ZERO(3)

DNRM
3
OK-ZERd )

NRM

ZERO

OK-NRM

OK-INF

INV-NAN

DNRM

OK-ZERO (3)

OK-ZERo(3)

OK-NRM

OK-INF

INV-NAN

NRM

OK-NRM

OK-NRM

OK-ZERO
UNF-ZERO
OK-NRM
OK-INF(4)

OK-INF

INV-NAN

INF

OK-INF

OK-INF

OK-INF

OK-INF(1)
INV-NAN(2)

INV-NAN

INV-NAN

INV-NAN

INV-NAN

INV-NAN

INV-NAN

AlB

NAN
NOTES:
1. +INF+INF-+ +INF
-INF-INF -+ -INF

ZERO

2. + INF-INF -+ NAN
-INF+INF -+ NAN
3. +ZERO+ZERO -+ +ZERO (RN. RZ. RP. RM)
-ZERO-ZERO -+ -ZERO (RN. RZ. RP. RM)
+ ZERO-ZERO -+ + ZERO (RN. RZ. RP)
+ ZERO-ZERO -+ -ZERO (RM)
-ZERO+ZERO -+ +ZERO (RN. RZ. RP)
-ZERO+ZERO -+ -ZERO (RM)
4. OVF will produce INF or MAX.NRM. depending upon the rounding mode
+ NRM.MAX if [(RM. RZ) AND (TRESULTS is +)]
+ NRM.MAX if [(RM. RZ) AND (TRESULTS is -)1
+INF if [(RN. RP) AND (TRESULT is +)1
-INF if [(RN. RM) AND (TRESULT is +)]

7-49

NAN

IDT721264/IDT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARYANDCOMMERCIAL TEMPERATURE RANGES

TABLE 9. FLOATING-POINT MULTIPLICATION ("FAST" MODE)
ZERO

AlB

NRM

DNRM

INF

NAN

OK-NRM

INF-NAN

INV-NAN

ZERO

OK-ZEAO

OK-ZEAO

DNRM

OK-ZERO

OK-ZEAO

OK-NRM

OK-INF

INV-NAN

OK-INF

INV-NAN

NRM

OK-ZEAO

OK-ZERO

UNF-ZEAO
OK-NAM
OK-INF(l)

INF

INF-NAN

OK-INF

OK-INF

OK-INF
INV-NAN

INV-NAN

INV-NAN

INV-NAN

INV-NAN

INV-NAN'

NAN

d,NV-NAN

NOTES:
1. OVF will produce INF or MAX.NRM. depending upon the rounding mode
+NAM.MAX if [~AM. RZ) AND~AESULTS is +)]
+ NAM.MAX if [ AM. AZ) AND AESULTS is -)] .
+ INF if [(AN. A ) AND (TAES LT is +)]
-INF if [(RN. AM) AND (TAESULT is-)]

TABLE 10. FLOATING-POINT ADD/SUBTRACT (IEEE MODE)
ZERO

DNRM

NRM

INF

ZERO

OK-ZEAO(3)

UNF-WNAM

OK-NRM

OK-INF

INV-NAN

DNRM

UNF-WNRM

UNF-WNAM
OK-ZEAO(3)
OK-NRM

OK-NRM
UNF-WNRM

OK-INF

INV-NAN

NRM

OK-NRM

UNF-WNRM
OK-NRM
OK-INF(4)

OK-ZERO
UNF-WNRM
OK-NAM
OK-INF(4)

OK-INF

INV-NAN

INF

OK-INF

OK-INF

OK-INF

OK-INF(l)
INV-NAN(2)

INV-NAN

INV-NAN

INV-NAN

INV-NAN

AlB

NAN
INV-NAN
INV-NAN
NOTES:
1. +INF+INF-+ +INF
-INF-INF -+ -INF
2. + INF-INF -+ NAN
-INF+INF -+ NAN
3. +ZEAO+ZERO -+ +ZERO (AN. RZ. RP. AM)
-ZERO-ZEAO -+ -ZERO (AN. AZ. AP. RM)
+ZEAO-ZERO -+ +ZERO (AN. RZ. RP)
+ ZERO-ZERO -+ -ZERO (AM)
-ZERO+ZERO -+ +ZERO (RN. RZ. AP)
-ZERO + ZEAO -+ -ZERO (RM)
4. OVF will produce INF or MAX.NRM. depending upon the rounding mode
+ NRM.MAX if [~AM. AZ) AND (TRESULTS is +)]
+ NAM.MAX if [ AM. RZ) AND (TAESULTS is -)]
+ INF if [(RN. A ) AND (TRESULT is +)]
-INF if [(RN. AM) AND (TRESULT is +)]

NAN

TABLE 11. FLOATING-POINT MULTIPLICATION (IEEE MODE)
AlB
ZERO

ZERO

DNRM

OK-ZERO

OK-ZEAO

OK-ZERO

NRM

INF

NAN

OK-ZEAO

INF-NAN

INV-NAN

OK-ZERO

DIN-ZERO

OK-INF

INV-NAN

OK-ZEAO

OK-ZEAO

UNF-ZEAO
OK-NAM
OK-INF(l)

OK-INF

INV-NAN

INF

INF-NAN

OK-INF

OK-INF

OK-INF

INV-NAN

NAN

INV-NAN

INV-NAN

INV-NAN

INV-NAN

INV-NAN

DNRM
NRM

~

NOTES:
1. OVF will produce INF or MAX.NAM. depending upon the rounding mode
+ NAM.MAX if [(RM. AZ) AND (TAESULTS is +)]
+ NAM.MAX if [(AM. AZ) AND (TAESULTS is -)]
+ INF if [(RN. AP) AND (TRESULT is +)]
-INF if [(RN. RM) AND (TRESULT is +)]

7-50

IDT721264/1DT721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 12. FLOATING-POINT COMPARE STATUS
INPUT B

I
N
P
U
T
A

U

U

U

U

U

NAN

U

U

U

U

U

U

L

L

L

L

+INF

L

L

L

E

U

U

L

L

L

L

+NRM

L

L

Note 1

G

U

U

L

L

L

L

+DNRM

L

Note 1

G

G

U

U

L

L

L

E

+ZERO

E

G

G

G

U

NAN

-INF

-NRM

-DNRM

-ZERO

+ZERO

+DNRM

+NRM

+INF

NAN

U

L

L

L

E

-ZERO

E

G

G

G

U

U

L

L

Note 1

G

-DNRM

G

G

G

G

U

U

L

Note 1

G

G

-NRM

G

G

G

G

U

U

E

G

G

G

-INF

G

G

G

G

U

U

U

U

U

U

NAN

U

U

U

U

U

NOTE:
1. Equal, less than or greater than
E-A = B
L-A < B
G-A> B
U - Unordered

TABLE 14. CONVERT DOUBLE TO SINGLE (1)
F64~

F64 OPERAND

TABLE 13. CONVERT SINGLE TO DOUBLE
F32~

F32 OPERAND

F64

F64 RESULT

177m

077777

177777

077777

1m77

177777

077600

000000

Om60
00000o

00000o

077577

00000o

043757
160000

00000o

037600

00000o

037760

00000o

00000o

000000

000200

00000o

000000

177m

034020

00000o

00000o

000000

033757
140000

00000o

033240

00000o

00000o
000000

000177

1m77

00000o

000001

00000o

00000o

177600

00000o

177577

177777

140000

00000o

100200

00000o

100177

177777

100000

000001

00000o

100000

00000o

00000o

177777

STATUS

COMMENTS

12

NaN

1

+INF

2

+MAX.NRM

2

+1

2

+MIN.NRM

2

+MAX.DNRM

00000o

2

+MIN.DNRM

00000o

000000
000000

0

+ZERO

1m60
00000o

00000o
000000

1

-INF

143757
160000

1m77
00000o

2

-MAX.NRM

140000

00000o

00000o

00000o

2

-2

134020

00000o

00000o
00000o

2

-MIN.NRM

133757
140000

177m
00000o

2

-MAX.DNRM

133200

00000o
00000o

2

-MIN.DNRM

00000o
00000o

0

-ZERO

100000

STATUS

COMMENTS

177777

12

NaN

077600

000000

1

+INF

177777
000000

077600

000000

5

+MAX.NRM
OPERAND

043757
170000

177777
000000

077600

000000

5

+OVF RESULT

043757
160000

177777
000000

077577

177777

2

'+MAX.NRM
RESULT

043757
177777

1m77

077400

000000

3

+ INEXACT

037760
000000

000000
000000

037600

000000

2

+1

034020
000000

000000
000000

000200

000000

2

+MIN.NRM
RESULT

034017
160005

177777
000000

000200

000000

3

+MIN.NRM
RESULT

033757
140000

177777
000000

000177

177777

6

+MAX.DNRM
RESULT

033240
000000

000000
000000

000000

000001

6

+MIN.DNRM
RESULT

033230
000000

000000
000000

000000

000001

7

+MIN.DNRM
RESULT

033220
000000

000000
000000

000000

000000

7

+ZERO
RESULT

000020
000000

000000
000000

00000o

00000o

7

+MIN.NRM
OPERAND

000017
177777

17m7

000000

000000

7

+MAX.DNRM
OPERAND

077777
177777

17m7

077m

077760
000000

000000
000000

077757
000000

177777

177777

177777

000000
00000o

00000o

000000

000000

00000o

0

+ZERO

177760
00000o

00000o
00000o

177600

00000o

1

-INF

177757
177777

177777
177777

177600

000000

5

-MAX.NRM
OPERAND

100000
000000

00000o

100000

000000

0

-ZERO

000000

NOTE:
1. Round Mode = RN

7-51

F32

F32 RESULT

101721264/101721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 17. DOUBLE FIX (1)

TABLE 15. DOUBLE FLOAT
132 -+ F64
132 OPERAND

F64 RESULT

F64 -+ 132
STATUS

COMMENTS

F64 OPERAND

132 RESULT

STATUS

COMMENTS

077777

177777

040737
177700

177777
000000

2

+ MAX
OPERAND

077777
177777

177777
177777

077777

177777

12

NAN

077777

177776

040737
177600

177777
000000

2

-

077760
000000

000000
000000

077777

177777

5

+INF

00000o

000002

040000
00000o

00000o
00000o

2

+2

077757
177777

177777
177777

077777

177777

5

+MAX.NRM
OPERAND

00000o

000001

037760
000000

000000

2

+1

040737
177740

177777
000000

077777

177777

5

+OVF

000000

000000

000000
000000

00000o

0

ZERO

040737
177700

177777
000000

077777

177777

2

+ MAX
RESULT

177777

177777

137760
000000

000000
000000

2

-1

040000
000000

000000
000000

000000

000002

2

+2

177776

140000
000000

000000
000000

2

-2

377760
000000

000000
000000

000000

000001

2

+1

000002

140737
177600

177777
000000

-

037750
000000

000000
000000

000000

000001

3

+1

100000

000001

140737
177700

177777
000000

2

-

037740
000000

000000
000000

000000

000000

3

ZERO

100000

00000o

140740
000000

000000
000000

2

-MAX
OPERAND

000020
000000

000000
000000

000000

000000

3

+MIN.NRM

000000
000000

000000
000001

000000

000000

3

+MIN.NRM

000000
000000

000000
000000

000000

000000

0

+ZERO

000000
000000

100000

000000

5

-INF

177777
100000

00000o
000000

2

TABLE 16. SINGLE FLOAT (1)
132 -+ F32
132 OPERAND

F32 RESULT

STATUS

COMMENTS

177760
000000
177757
177777

177777
000000

100000

000000

5

-MAX.NRM
OPERAND

140740
000100

000000
000000

100000

000000

5

-OVF

140740
000000

000000

100000

000000

2

-MAX
RESULT

140000
000000

000000
000000

177777

177776

2

-2

137760
000000

000000
000000

177777

177777

2

-1

137750
000000

000000
000000

177777

177777

3

-1

137740
000000

000000
000000

000000

000000

3

ZERO

100200
000000

00000o

000000

000000

3

-MIN.NRM

100000
000000

000000
000001

000000

000000

3

-MIN.DNRM

100000

000000

00000o

00000o

000000

000000

0

-ZERO

077777

177777

047400

000000

3

+ MAX OPERAND

077777

177700

047400

000000

3

-

077777

177600

047377

177777

2

-

000000

000002

040000

00000o

2

+2

000000

000001

037600

00000o

2

+1

000000

00000o

00000o

00000o

0

ZERO

177777

177777

137600

000000

2

-1

177777

177776

140000

00000o

2

-2

100000

00000o

147400

000000

2

-MAX OPERAND

NOTE:
1. Round Mode = RN

00000o

00000o

NOTE:
1. Round Mode = RN

7-52

101721264/ID1721265 32-BIT AND 64-BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 21. DOUBLE UNWRAP EXACT VALUE

TABLE 18. SINGLE FIX (1)
STATUS

COMMENTS

077777

177777

077777

1m77

12

NAN

077600

000000

077777

177777

5

+INF

077577

177777

077777

177777

5

+MAX.NRM

047400

000000

077777

177777

5

+OVF

047377

177777

077777

177600

2

+ MAX RESULT

040000

000000

000000

000002

2

+2

037600

000000

000000

000001

2

+1

037500

000000

000000

000001

3

+1

F32 OPERAND

132 RESULT

000200

000000

000000

000000

3

+MIN.NRM

000000

000001

000000

000000

3

+MIN.DNRM

000000

000000

000000

000000

2

+ZERO

177600

000000

100000

000000

5

-INF

177577

177m

100000

000000

5

-MAX.NRM

U64 OPERAND

D64 RESULT

STATUS

COMMENTS

000017
177777

177777
177777

000020
000000

000000
000000

3

+MIN.NRM
RESULT

000000
000000

000000
000000

000010
000000

000000
000000

6

+UNF

077777
177777

177777
177777

000010
000000

000000
000000

7

-

076320
000000

000000
000000

000000
000000

000000
000001

6

+MIN.DNRM
RESULT

076317
177777

177777
177777

000000
000000

000000
000001

7

-

NOTE:
1. Round Mode = RN

TABLE 22.
SINGLE UNWRAP EXACT VALUE (1)
U32 -+ D32

147400

000001

100000

000000

5

-OVF

147400

000000

100000

000000

2

-MAX RESULT

140000

000000

177777

177776

2

-2

100177

177777

100200

000000

3

137600

000000

177777

177777

2

-1

100000

000000

100100

000000

6

-

137500

000000

177777

177777

3

-1

177777

177777

100100

000000

7

137400

000000

000000

000000

3

-ZERO

172400

000000

100000

000001

6

-

100200

000000

000000

000000

3

-MIN.NRM

172577

177777

100000

000002

7

-

100000

000001

000000

000000

3

-MIN.DNRM

100000

000000

000000

000000

0

-ZERO

U32 OPERAND

TABLE 19.
DOUBLE WRAP DENORMALIZED VALUE
D64-+W64
W64 RESULT

STATUS

COMMENTS

000000
000000

000000
000001

076320
000000

000000
000000

2

+MIN.DNRM

000010
000000

00000o
00000o

000000
000000

000000
000000

2

-

000017
177777

177777
177m

000017
177777

177777
177776

2

+MAX.DNRM

TABLE 20.
SINGLE WRAP DENORMALIZED VALUE
D32 -+ W32
D320PERAND

W32 RESULT

STATUS

COMMENTS

172400

000000

00000o

100000

00000o

2

-

177m

100177

177776

2

-MAX.DNRM

100000

000001

100100
100177

2

D32 RESULT

NOTE:
1. Round Mode = RN

NOTE:
1. Round Mode = RN

D64 OPERAND

(1)

U64 -+ D64

F32 -+ 132

-MIN.DNRM

7-53

STATUS

COMMENTS

-

IDT721264/IDT721265 32-BIT AND 64·BIT
IEEE FLOATING-POINT MULTIPLIER AND ALU

MILITARY AND COMMERCIAL TEMPERATURE RANGES
exception is flagged. The denormalized operand must then be sent
to the IDT721265 to be wrapped. Once wrapped, the operand can
be sent back to the IDT721264 for multiplication. The result 0 the
multiplication will either be a normalized number or a UNRM.
If the result is a UNRM, status bit So indicates either UNF (if all
the truncated bits are equal to zero) or UNF-INX (if any of the
truncated bits is equal to one).
No rounding will occur regardless of the rounding mode
specified.
The underflowed number may then be sent to the I DT721265 for
"unwrapping". To unwrap a number, the fraction field is shifted
right and the exponent incremented by one for each shift position.
Status bit So must be used to conditionally execute the "UNWRAP
INEXACT" or "UNWRAP EXACT" instruction. The rounding must
be performed in the ALU. The unwrapping may have three possible
results:

GRADUAL UNDERFLOW
The minimum normalized number has an exponent of one and a
fraction field of zero. Zero has an exponent of zero and a fraction
field of all zeros. This gives users the ability to deal with numbers
between NORM.MIN and ZERO. These numbers are known as
denormals. Theirformat is given In the number format section. The
IEEE standard has specified gradual underflow as the way to handle denormals. Many of the features· of the IDT721264 and
IDT721265 are Included to deal with denormals in a manner consistent with IEEE Standard 754. Since denormals are very close to
zero, many applications can substitute zero for a denormal without
a significant loss of accuracy. For these applications, a "FAST"
mode is Included which substitutes zero for all denormalized Inputs to the IDT721264 and IDT721265. Zero is also inserted for all
UNRM outputs In "FAST" mode.
For all arithmetic operations, the IDT721265 handles denormal·
ized inputs directly as it would handle and other number.
Unfortunately, a floating-point multiplier must either operate
exclusively on normalized numbers or suffer large cost and
performance penalties in dealing directly with denormals. A nor·
malized format that yields an equivalent to a given denormalized
number is the wrapped formatThe number format table shows the
equivalence of wrapped and denormalized numbers. To translate
a denormalized number to a wrapped number, the fraction is nor·
malized (shifted up so that a one is in the hidden bit) and one is
subtracted from the exponent for every position shifted. The
IDT721264 can multiply correctly either two wrapped numbers or a
wrapped and a normalized number. To understand the full procedure, consider the following case.
Assume one of the two input operands to the IDT721264 is a de·
normalized number. Four cycles after the input, the de norm

RESULT

EXCEPTION

COMMENT

DNRM

UNF

When the denormalized result is
exact. Note that this result is possible
only if the UNWRAP EXACT
instruction is possible (I.e .. both the
input and the result must be exact).

DNRM

UNF-INX

If either the ·UNWRAP INEXACT"'
instruction is executed or if the
result of the ·UNWRAP INEXACT"
instruction is inexact.

ZERO

INX

The result is zero. but the
unwrapping has resulted in the loss
of precision.

ORDERING INFORMATION
lOT

XXXXXXDevice Type

A
Power

99

A

A

Speed

Package

Process/
Temperature
Range

-----II

L...I

L-------------------1
L----------------------i

7-54

:LANK

Commercial (O°C to + 70°C
Military (-55°C to +125°C)
Compliant to MIL-STD·883. Class 8

G

Pin Grid Array

30
40
50
60

(Commercial only)
Clock Cycle Time (ns)

L

Low Power

721264
721265

32·/64-8it Floating-POint Multiplier
32-/64-8It Floating-Point ALU

------_.--------------------------------------------------

FEATURES:

DESCRIPTION:

• 16 x 16 parallel multiplier with double precision product

The IDT7216/IDT7217 are high-speed, low-power 16 x 16-bit
multipliers ideal for fast, real time digital signal processing applications. Utilization of a modified Booths algorithm and IDT's highperformance, submicron CEMOS technOlogy, has achieved
speeds comparable to bipolar (20ns max.), at 1/10th the power
consumption.
The IDT7216/IDT7217 are ideal for applications requiring highspeed multiplication such as fast Fourier transform analysis, digital
filtering, graphic display systems, speech synthesis and recognition and in any system requirement where multipl ication speeds of
a mini/microcomputer are inadequate.
All input registers, as well as LSP and MSP output registers, use
the same positive edge-triggered D-type flip-flop. In the IDT7216,
there are independent clocks (CLKX, CLKY, ClKM, CLKl) associated with each of these registers. The IDT7217 has o~ single
clock input (ClK) and three register enables. ENX and ENY control
the two input registers, while ENP controls the entire product.
The IDT7216/IDT7217 offer additional flexibility with the FA control and MSPSEL functions. The FA control formats the output for
two's complement by shifting the MSP up one bit and then repeating the sign bit in the MSB of the LSP. The MSPSEL low selects the
MSP to be available at the product output port, while a high selects
the LSP to be available. Keeping this pin low will ensure compatibility with the TRW MPY016H.
The IDT7216/IDT7217 multipliers are manufactured in compliance with the latest revision of MIL-STD-883, Class B, making them
ideally suited to applications demanding the highest level of performance and reliability.

• 20ns clocked multiply time
• low power consumption: 120mA
• Produced with advanced submicron CEMOS™ highperformance technology
• IDT7216l is pin- and functionally-compatible with TRW
MPY016H/K and AMD Am29516
• IDT7217l requires only single clock with register enables
making it pin- and functionally-compatible with AMD
Am29517
• Configured for easy array expansion
• User-controlled option for transparent output register mode
• Round control for rounding the MSP
• Single 5V power supply
• Input and output directly TTL- compatible
• Three-state output
• Available in plastic DIP, Shrink-DIP, Fine-Pitch LCC~'LCC,
PlCC, Flatpack and Pin Grid Array
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87531 is pending listing on
this function. Refer to Section 2/page 2-4.

FUNCTIONAL BLOCK DIAGRAMS
RND

RND

YM

Y15-0 IF\ 5-0

ClK-~~---~T-~~

CLKY--+-~----~~--~

CLKX ---4-I-+..:r""

ENX ---4I--if-+.a-,
ENY---~--+---~~~~

FA---------;~~~~__ I

FA--------~~~~~~

FT-----~

FT -------+1

......T"-r~.,....,~...1

CLKM _ _ _ _ _ _ _-J

CLKL--------~-~

ENP--------r-4---r~

MSPSEL-------~

MSPSEL-------;

OEP-------------__~
MSP OUT (P31

OEP--------------~

-

P16 )

MSP OUT

IDT7216

(P31 -

P16 )

1DT7217

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987

1987 Integrated Device Technology. Inc.

7-55

)

DSC-2023/-

011

10T7216LJI0T7217L 16 x 16·BIT
PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
1OT7216

IOT7216/10T7217

IOT7217

64-PIN DIP
TOP VIEW
68-PIN SHRINK·DIP
TOP VIEW

* (IDT7217 Pin Designation)

64-PIN DIP
TOP VIEW

7-56

IDT7216LJIDT7217L 16 x 16·BIT
PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS (CONTINUED)
IDT7216/IDT7217

11

X13

X1S

RND

YM

Vee

GND

FT

OEP

X 14

CLIO< or

XM

Vee

GND

MSPSEl

FA

ClKM or
ENp·

NC

10

X 11

X 12

09

Xg

X10

P30 • ~4

P31 • ~s

08

X7

Xa

P2a • ~2

P29 • ~3

07

Xs

Xs

P26 • ~o

P27 • ~1

06

X3

X4

P24 • Pa

P2S ' Pg

05

X1

X2

P22 • Ps

P23 • P7

OEl

Xo

P2Q. P4

P21 • Ps

P1B' P2

P19 • P3

P16' Po

P17 • P1

04

03

02

/

Pin 1
Designator

NC

~

G68-2

ClKYor ClKlor
ClK*
rnv*
NC

Yo' Po

Y2• P2

Y4• P4

Ys • Ps

Ya• Pa

Y1O' ~o

Y12• P'2

•

Y1• P1

Y3 • P3

Ys ' Ps

Y7• P7

Yg. Pg

Y11 • ~1

Y13• P'3 Y1S ' P,s

A

B

C

D

E

F

G

·Pin designation for ID17217
PGA TOP VIEW

7-57

H

Y14' P,4

J

NC

K

l

IDT7216UIDT7217L 16 x 16-BIT
PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7217

IDT7216

PIe.
P'4.
P'3.
P'2.

P3 ,
P30
P29
P28
PI"~ P27
P,o. P28
Ps . P25
Pe• P24
P7 • P23
Ps • P22
PO. P2 ,
P4 • P20
P3 • P,s
P2 • P,e
PI' P'7
Po. P UI

= 1 -.rjt~~~===~:::==~~jj;=l-

P,5. P3 ,

=1
=2
=3
=4
=5
=6
=7
=6
=9
=10
=11
=12
=13
=14
=15
=16

P,3. P29
P'2. P28
P,,, P27
P,o. P26
Pg • P25
Pe.P24
P7 • P23
Pe • P22
P5 • P2 ,

P4 •
P3 •
P2 •
PI.
Po.

P20
P,g
P,e
P'7
P,e

Xe

8::J

Xo

~~~~~~~~>~~~~~~~
~i~~=~~o':~~~~~~~~

~~~~~~

0.0.0.0.0.0.

64-LEAD FLATPACK
TOP VIEW

64-LEAD FLATPACK
TOP VIEW

1DT7216

1DT7217

X'3
X'4

61
62
63

61
62

~ 63

ENX 64
RND 65

64

RND 65

XM

66

Y M 67
Vee 68
Vee 1
GND 2
GND 3

J68-1. l68-1
& L68-2

66

YM

67

V""

68
1

~~

J68-1. l68-1
& l68-2

GND 2
GND 3

~4

~4

FT5
FA

FT
FA

"OEJ5

5

UEP
ENP 8
NC 9

8

9
1011 12

M

131~

g re

~ ~

1516 1718 192021 222324 25 26

re

~ ~ ~ ~

;

10111213 14 1516 1718 192021 2223242526

~ ~ ~ ~ ~()

~~~~~~~~~~~~~~~~~
~~r1rfcir1~~~~~~~~~~

~~~~~a.a.a.a.a.a.a.a.a.a.a.z

~rfl~rfr1~~~~~~~~~~
LCC/PLCCI
FINE-PITCH LCC
TOP VIEW

LCC/PLCCI
FINE-PITCH LCC
TOP VIEW

7-58

Xe
X4
X3
X2
X,

UEI.
34::J
33::J

UUUUUUUUUUUUUUUU

~~~~~~~~~~~~~~~~
;,..;,; .. ;,oo':o':cto':~o:o:a:~rI:

ClKM
NC

X7

17181920212223242526272829 303132

UUUUUUUUUUUUUUUU

XM

X"
X,o
Xg
Xe

=3
=4
=5
=6
=7
=8
=9
=10
=11
=12
=13
=14
=15
=16

17 18 1920 21 222324 252627 2829 30 31 32

X'3
X'4
X,e
CLKX

X'2

PIA. P30 =2

elK
ENY

IDT7216UIDT7217L 16 x 16-BIT
PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(l)
SYMBOL
VTERM

COMMERCIAL

RATING
Terminal Voltage
with Respect to
GND

-0.5 to +7.0

RECOMMENDED DC OPERATING CONDITIONS
MILITARY

UNIT

-0.5 to +7.0

V

Operating
Temperature

Oto +70

-55 to +125

TB1AS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to + 155

°C

TA

MIN.

TYP.

MAX.

VCCM

Military Supply Voltage

4.5

5.0

5.5

V

Vcc

Commercial Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H
V1L

Input High Voltage

2.0

-

-

V

Input Low Voltage

-

-

O.S

V

SYMBOL

°C

PARAMETER

UNIT

mA
50
DC Output Current
50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS-FAST

(CommercialVcc = 5V ± 10%, TA = O°C to + 70°C, MilitaryVcc
20, 25, 35, 45, 55, 65ns or Military, 25, 30, 40, 55, 65, 75ns
SYMBOL

PARAMETER

= 5V ±10%, TA = -55°C to + 125°C) for Commercial clocked multiply times of

TEST CONDITIONS

MILITARY
COMMERCIAL
MIN, TYp!1) MAX. MIN. TYpP) MAX.

-

IILol

Output Leakage Current

= Max., V1N = Oto Vcc
Hi Z, Vcc = Max., VOUT = 0 to Vcc

ICC(2)

Operating Power Supply Current

ICCOl
ICC02
ICC /f(2.3)

-

20

10

-

20

J.l..A

SO

-

40

100

mA

20

40

50

mA

20

4

25

mA

"':)

4

-

20

4

-

6

mNMHz

10

-

Outputs Open Measured at 10MHz(2)

-

40

Quiescent Power Supply Current

V1N ~ '-"H ,V1N ~ V1L

Quiescent Power Supply Current

V 1N ~ Vcc -0.2V, V1N ~ 0.2V

-

Input Leakage Current

Vcc

= Max., f > 10MHz
Vcc = Min., 10H = -2.0mA
Vcc = Min., 10L = 4mA

Increase in Power Supply Current MHz Vcc

UNIT

-

-

lIu l

J.l..A

-

-

VOH
Output High Voltage
2.4
V
2.4
V (4)
Output Low Voltage
0.4
0.4
V
OL
NOTES:
1. Typical impliesVcc = 5V and TA = +25°C.
2. Icc is measured at 10M Hz and '-"N = 0 to 3V. For frequencies greater than 10M Hz, the following equation is used for the commercial range: Icc = SO +
4(f-10)mA; for the military range, Icc = 100 + 6(f-10). f = operating frequency in MHz, f = 1!tMucfor IDT7216 and f = 1/iMc for IDT7217.
3:.,For frequencies greater than 10MHz.
4. 10L = SmA for tMC = 20 to 55ns

-

-

-

DC ELECTRICAL CHARACTERISTICS-SLOW
(CommercialVcc = 5V ± 10%, TA = O°C to + 70°C, MilitaryVcc
75, 95, 140ns or Military 90, 120, 1S5ns
SYMBOL

PARAMETER

Ilul

Input Leakage Current

IlLOI

Output Leakage Current

= 5V ±10%, TA = -55°C to

TEST CONDITIONS

= Max., V1N = OtoVcc
Hi Z, Vcc = Max., VOUT = 0 to Vcc

Vcc

+ 125°C) for Commercial clocked multiply times of

MILITARY
COMMERCIAL
MIN. TYP!1) MAX. MIN. Typ~l) MAX.

-

-

-

2
2

-

ICC(2)

Operating Power Supply Current

Outputs Open Measured at 10MHz(2)

-

30

60

ICcal

Quiescent Power Supply Current

V1N ~ '-"H ,V1N ~ V1L

-

10

30

ICC02

Quiescent Power Supply Current

V1N ~ Vcc -0.2V, V1N -s;0.2V

-

0.1

1.0

Icc 11(2.3)

Increase in Power Supply Current MHz Vcc

-

4

VOH

Output High Voltage

Vcc

-

2.4

VOL

Output Low Voltage

Vcc = Min., 10L = 4mA

-

0.4

-

= Max., f > 10MHz
= Min., 10H = -2.0mA

2.4

-

UNIT

-

10

J.l..A

-

10

J.l..A

30

SO

mA

10

30

mA

-

1.0

2.0

mA

-

-

6

mNMHz

-

-

V

-

0.4

V

NOTES:
1. Typical implies Vcc = 5Vand TA = +25°C.
2. Icc is measured at 10M Hz and V1N = 0 to 3V. For frequencies greater than 10M Hz, the following equation is used for the commercial range: Icc = 60 +
4(f-10)mA, where f = operating frequency in MHz; for the military range, Icc = SO + 6(f-10) where f = operating frequency in MHz.
3. For frequencies greater than 10MHz.

7-59

IDT7216UIDT7217L 16 x 16-BIT
PARALLEL CMOS MULTIPLIERS

CAPACITANCE
SYMBOL
C IN
C OUT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Vcc

(TA = +25°C, f = 1.0MHz)

PARAMETER(1)

CONDITIONS

UNIT

MAX.

Input Capacitance

VIN = OV

10

pF

8100

Output Capacitance

VOUT = OV

12

pF

TO
OUTPUTo---.----L..--,
PIN

NOTE:
1. This parameter is sampled and not 100% tested.

5000

TO

OUTPUT~

.~ __ l

PIN

1.-.--..---'

AC TEST CONDITIONS
GND t03.0V
3ns
1.5V
1.5V
See Figures 1 and 2

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

............,l""'W"............,- 3V

~~9>~

'flfffJ{,t'H--i-. ~:v

________ 1

r

1.IK

Figure 1. AC Output Test Load

............,l"'''W"............,rT----~

DATA
INPUT

THREESTATE
CONTROL

3V
--------1.5V

-+=

V,

Figure 2. Output Three-State
Delay Load (VX = OV or 2.6V)

}_tE~

t DIS

OUTPUT
THREESTATE

- - - - - - - - - ' - - - - - - - - ov

1.

4OPF~

40pF

HIGH-1M PEOANCE

NOTE:
1. Diagram shown for HIGH data only. Output transition may be opposite sense.

Figure 3. Set-Up And Hold Time

Figure 4. Three-State Control Timing Diagram

AC ELECTRICAL CHARACTERISTICS COMMERCIA~3)
SYMBOL

PARAMETER

(Vcc= 5V±10%, TA = O°Cto +70°C)

7216L20/25
7216L35/45
7217L20/25
7217L35/45
MIN.
MAX. MIN.
MAX.

t MUC

Unclocked Multiply Time
Clocked MUltiply Time

-

30/38

t MC
ts

X, Y, RND Set-up Time

10/12

tH

X, Y, RND Hold Time

0/2

tPWH

Clock Pulse Width High

9/10

-

t pWL

Clock Pulse Width Low

9/10

-

tpDSEL
t pDP
t pDy

MSPSEL to Product Out

-

18/20

Output Clock to P

-

Output Clock to Y
3-State Enable Time (2)

-

7216L140
7216L75/90
7216L55/65
7217L140
7217L55/65
7217L75/90
MIN.
MAX.
MAX.
MIN.
MAX. MIN.
100/125

-

180

ns

75/90

-

140

ns

25

-

25

-

ns

2/0

-

0

-

25

ns

20

-

25

-

30/35

-

40

ns

30

-

35

-

40

ns

30

-

35

40

ns

30/35

35

40

ns

25

-

30

-

40

ns

55/65

-

75/85

35/45

-

55/65

-

12/15

-

20

3

-

3

-

10/15

15

-

20

10/15

-

20

-

-

25

25/30

18/20

-

25

18/20

-

25

18/20

-

25

15/18

-

22

-

20/25

UNIT

ns
ns

t DIS

3-State Disable Time (2)

-

ts

Clock Enable Set-up Time
(IDT7217 only)

10

-

10

-

10

-

25

-

25

-

ns

tH

Clock Enable Hold Time
(IDT7217 only)

0/2

-

3

-

3

-

3

-

3

-

ns

t HCL

Clock Low Hold TIme
CLKXY Relative to CLKML
(IDT7216 only) (1)

0

-

0

-

0

-

0

-

0

-

ns

tENA

NOTES:
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured + 500mV from steady state voltage with loading specified in Figure 2.
3. For test load, see Figure 1.

7-60

IDT7216U1DT1217L 16 x 16-BIT
PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS MILITARY
SYMBOL

PARAMETER

(3)

-

38/43

-

Clocked Multiplv Time

25/30

-

X Y RND Set-up Time

12

-

15/20

tH
tpWH

X Y, RND Hold Time

2

-

3

Clock Pulse Width High

10

tPWL

Clock Pulse Width Low

10

-

tpOSEL

MSPSEL to Product Out

-

20

tpop

Output Clock to P

tpOY

Output Clock to Y

tENA

3-State Enable Time (2)

t OIS

3-State Disable Time (2)

-

ts

Clock Enable Set-up Time
JlDT7217 only)

10

-

12115

tH

Clock Enable Hold Time
(IDT7217 only)

2

-

t HCL

Clock Low Hold Time
CLKXY Relative to CLKML
(lDT7216 only) (1)

0

-

tMuc
t MC
ts

Unclocked Multiplv Time

+ 125°C)

(VCC= 5V±10%, TA = -55°C to

7216L40/55
7216L25/30
7217L40/55
7217L25/30
MAX. MIN.
MAX.
MIN.

7216L185
7216L90/120
7216L65/75
7217L185
7217L90/120
7217L65/75
MAX. MIN.
MAX. MIN.
MAX.
MIN.

-

125[160

30

-

85/95

-

65/75

25
3

-

2/0

15

-

15

-

15

-

15

-

25/30

20

-

25/30

20

-

25
25

-

35

20

-

-

15

3

-

0

-

18

60175
40/55

25/30

UNIT

-

230

ns

185

ns

-

30

25/30

-

30

25/30

-

30

-

40

45

ns

45

ns

40

-

45

ns

40

-

45

ns

25

-

40

-

45

ns

-

30

-

30

-

ns

3

-

3

-

3

-

ns

0

-

0

-

0

-

ns

30/35
30/35
35/40

90/120

40

0

ns
ns
ns
ns

NOTES:
1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been
clocked.
2. Transition is measured + 500mV from steady state voltage with loading specified in Figure 2.
3. For test load, see Figure 1.

CLKX
CLKY

INPUT XI, Y I ,
RND

CLKM
CLKL

OUTPUTY

CLKM
CLKL

OUTPUTP
~---------------tMUC----------------~

Figure 5.IDT1216 Timing Diagram

7-61

IDT7216UIDT7217L 16 x 16-81T
PARALLEL CMOS MULTIPLIERS

ClK

MILITARY AND COMMERCIAL TEMPERATURE RANGES

l-tPWH-1

______~I

I~

____~

OUTPUTY

OUTPUTP
~-----------------tMUC-----+----------~

Figure 6.IDT7217 Timing Diagram

1~1I---tMC
ClK

_I

I
O------~D !l~~V~ ~~O! ~~I
DATA
TO X,Y
REG:STERS

DATA OUTPUT
TO MSP, lSP
REGISiERS

-..j

I+- t

HCl (IDT7216)

Of-------"""'iD _R~C~~ ~s!: ~ .!:oS!: I

DATA
TOX,Y
REGISTERS

DATA OUTPUT
TO MSP, lSP
REGISTERS

Figure 7. Simplified Timing Diagram-Typical Application

7-62

IDT7216LJIDT7217L 16 x 16-BIT
PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS
INPUTS:
FA (RS)(I)
When the format adjust control is HIGH, a full 32-bit product is
selected. When this control is LOW, a left-shifted 31-bit product is
selected with the sign bit replicated in the Least Significant Product
(LSP). This control is normally HIGH except for certain fractional
two's complement applications (see Multiplier Input/Output
Formats).

X IN (X1S through Xo)
Sixteen Multiplicand Data Inputs.
YIN (V1S through Yo )
Sixteen Multiplier Data Inputs. (This is also an output port for
~5-0)

INPUT CLOCKS (IDT7216 ONLy)

FT

CLKX

The rising edge of this clock loads the X I 5-0 data input register
along with the X mode and round registers.

When this control is HIGH, both the Most Significant Product
(MSP) and Least Significant Product (LSP) registers are
transparent.

ClKY
The rising edge of this clock loads the YI 5-0 data input register
along with the Y mode and round registers.

OEl
Three-state enable for routing LSP through YIN /LSPOUT port.
OEP
Three-state enable for the product output port.

CLKM

The rising edge of this clock loads the Most Significant Product
(MSP) register.

RND
Round control for the rounding of the Most Significant Product
(MSP). When this control is HIGH, a one is added to the Most Significant Bit (MSB) of the Least Significant Product (LSP). Note that
this bit depends on the state ofthe format adjust (FA) control. If FA
is LOW when RND is HIGH, a one will be added to the 2-16 bit
(P14 ).If FA is HIGH when RND is HIGH, a one will be added to the
2- 15 bit (Fh). In either case, the LSP output will reflect this addition
when RND is HIGH. Note also that rounding always occurs in the
positive direction which may introduce a systematic bias. The RN D
input is registered and clocked in at the rising edge of the logical
OR of both CLKX and CLKY.

ClKl
The rising edge ofthis clock loads the Least Significant Product
(LSP) register.

INPUT CLOCKS (IDT7217 ONLy)
ClK
The rising edge of this clock loads all registers.
ENX
Register enable for the XI 5-0 data input register along with the X
mode and round registers.

MSPSEl
When the MSPSEL is LOW, the Most Significant Product (MSP)
is selected. When HIGH, the Least Significant Product (LSP) is
available at the product output port.

ENY
Register enable for the YI 5-0 data input register along with the Y
mode and round registers.
ENP
Register enable for the Most Significant Product (MSP) and
Least Significant Product (LSP).

OUTPUTS
MSP (P31 through ~6)
Most Significant Product output.
lSP (P15 through Po)
Least Significant Product output.

CONTROLS
X M' Y M (TCX, TCy)(I)
Mode control inputs for each data word. A LOW input designates unsigned data input and a HIGH input designates two's
complement.

Y1S•O /lSPOUT (VIS through Yo or P1S through Po)
Least Significant Product (LSP) Output available when OEL is
LOW. This is also an output port for YI 5-0.

NOTE:
1. TRW MPY016H/K pin designation.

7-63

til

IDT7216LJIDT7217L 16 x 16-BIT
PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

BINARY POINT

SIGNAL
DIGIT VALUE
~~~~~~~~~~~~~~-c~~~~~~~~~~~~~~~~~~~~~~~

~~~~~~~~~~~~~~~~~~~~~~C--r~~~~~~~~~~-p~~~~~~~--~~--~~~

I~=ol

DIGIT VALUE
IFA=ll

Figure 8. Fractional Two's Complement Notation
BINARY POINT

SIGNAL
DIGIT VALUE
~~~~~_ _L-~~~~~_ _~~~~~~+-~~~~~~~~~~~~~~~~~~

1~=11

MANDATORY

Figure 9. Fractional Unsigned Magnitude Notation
BINARY POINT

SIGNAL
~~~~~~~~~~~~--M~S~B~~~~--~~~~~~~~~~~~~~~~~~~~~--~~--~~~

Figure 10. Fractional Mixed Mode Notation

DIGIT VALUE
IFA=ll
MANDATORY

BINARY POINT
SIGNAL
D!GITVI\LUE

SIGNAL
DIGIT VALUE
~~~~~--~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

I~=ol

SIGNAL
DIGIT VALUE

1FA =11
Figure 11. Integer Two's Complement Notation
*In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000 ... 0 with 1,000.0 yielding an erroneous
product of -1 in the fraction case and -2 30 in the integer case.

7-64

1DT7216LJIDT7217L 16 x 16-BIT
PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

BINARY POINT

SIGNAL
2 0

DIGIT VALUE

0

DIGIT VALUE

SIGNAL
2

IFA =

BINARY POINT

SIGNAL
~~~~~~~~~~~~~~-C~~~~~~~~~~~~~~~~~~~~~~~

DIGIT VALUE

I~=,I

MANDATORY

Figure 13. Integer Mixed Mode Notation

ORDERING INFORMATION
IDT

xxxx

XX

xxx

XX

X

Device Type

Power

Speed

Package

Process!
Temperature
Range

I

I

~LANK

Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B

P
XC
C
J
XL
L
F

Plastic DIP
Shrink-DIP
Topbraze DIP
Plastic Leaded Chip Carrier
Fine-Pitch LCC (.025 Centers)
Leadless Chip Carrier
Flatpack
Pin Grid Array

G
20
25
35
45
55
65
75

Commercial (tMd

90
140

I L
I

7216
7217

7-65

,1

MANDATORY

Figure 12. Integer Unsigned Magnitude Notation

Low Power
16 x 16 Multiplier

25
30
40
55
65
75
90
120
185

Military (tMd

FEATURES

DESCRIPTION

• 16 x 16-bit parallel multiplier with 32-bit output available
immediately

The IDT7317 is a high-speed, low-power 16 x 16-bit multiplier
which halves the processing time of previously available devices
by virtue of the whole 32-bit product being accessible on the output
bus. This feature eliminates the need for multiplexing the Most Significant Product (MSP) and Least Significant Product (LSP) on the
same 16-bit output bus. lOT's high-performance sub micron
CEMOS technology yields very fast (20ns) clocked multiply times.
The IDT7317 is ideal for Digital Signal Processing (DSP) applications requiring high-speed integer multiplications and requires
the double precision 32-bit product available on the output in one
clock cycle. Typical applications include Fast Fourier Transforms
(FFT), digital filtering and graphic display systems.
All input registers and MSP and LSP output registers are
designed with positive edge triggered D-type f.!iQ:!!ops. The
IDT7317 has one clock and three register enables - ENX and ENY
control the input registers; ENP controls the 32-bit output register.
An output scaling shifter can shift the 32-bit result up or down by
one position for sign extension or for greater result accuracy.
Military versions of the IDT7317 are manufactured in compliance with the latest revision of MIL-STD-883, Class B for highreliability systems.

• 20ns clocked multiply time
• Low power consumption: 80mA (worst case)
• One clock and three register enables
• Unsigned, Two's Complement or Mixed mode operations
• Flexible output scaling shifter
• Pipeline or Flow-through modes
• TTL-compatible InpuVoutput
• Three-state outputs
• Produced with advanced submicron CEMOS ™
high-performance technology
• Available in 84-lead Pin Grid Array
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAMS

r----I.-...I..:~--*-- CLK

LL-==::::i:===~:::r-- ~
~------+----- FTY

FTX

FTP
k-----------~---

SHO-2

~------~----~

Vss

Vcc

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

DECEMBER 1987
OSC-2026/-

7-66

IDT731716 x 16-BIT PARALLEL CMOS
MULTIPLIER WITH 32-BIT OUTPUT

MILITARY AND COMMERCIAL TEMPERATURE RANGES
FLOW~THROUGH-X

(FTX)
Flow-through control input. When FTX is high, the input register
X is transparent.

PIN CONFIGURATIONS
(CONSULT FACTORy)

FLOW-THROUGH-V (FTY)
Flow-through control input. When FTY is high, the input register
Y is transparent.
.

PIN DESCRIPTION
INPUTS
DATA INPUT (Xo-1S)
Sixteen-bit multiplicand data inputs.

FLOW-THROUGH-P (FTP)
Flow-through control input. When FTP is high, the output register P is transparent.

DATA INPUT (yO-IS)
Sixteen-bit multiplier data inputs.

SHIFT CONTROL (SHO-2)
Shift control input pins which are used to normalize or scale the
output as follows:

OUTPUTS
DATA OUTPUT (PO-31)
Thirty-two-bit product outputs, Po-15 is the LSP and P16-31 is the
MSP.
CONTROLS
CLOCK (CLK)
Clock input, the low-ta-high transition loads all registers.
ENABLE X REGISTER (ENX)
Register enable for the XO-15 data input register and X mode.
ENABLE V REGISTER (ENY)
Register enable for the Vo-15 data input register and V mode.

SH2

SH1

SHO

0

X

X

CONTROL
No shift

1

0

0

Shift up by 1 position arithmetic and fill 0

1

0

1

Shift up logical by 1 position and fill 0

1

1

0

Shift down by 1 position arithmetic and
sign extension

1

1

1

Shift down logical by 1 position and fill 0

OUTPUT ENABLE, PO-15 (OEL)
Three-state enable for the LSP, PO-15.

ENABLE P REGISTER (ENP)
Register enable for the PO-31 data output register.

OUTPUT ENABLE, P16-31 (O,EM)
Three-state enable for the MSP, PI6-31.

XM
Mode control for input XO-15. A low input designates unsigned
data input; a high input designates two's complement.

POWER SUPPLY

VM

VCCO-1
Two power supply pins, 5V.

Mode control for input YO-15. A low input designates unsigned
data input; a high input designates two's complement.

VSSO-3
Four ground pins,

7-67

av.

FEATURES:

pipeline registers. Under control offour instruction bits (10-3), input
data (00-15) can be loaded directly into any of the individual registers or ent,ered into the multi-level pipeline registers with a Load
and Shift instruction. Two other instructions allow contents to be
shifted or held.
An eight-to-one multiplexer allows data to be read from anyone
of eight registers (REGA-REqH). A 3-bit multiplexer select (SELo-2)
control selects which of the ~ht registers is available at the output
(Y0-15). An Output Enable (OE), when low, latches output data on
the output pins.
Manufactured in high-speed, sub micron CEMOS technology,
the register access time is 10ns, making the IDT7320 ideal for very
high-speed Digital Signal Processing (DSP) and Array Processing
applications.
The IDT7320 includes the innovative Serial Protocol Channel
(SPC) used for system diagnostics. This on-chip feature greatly
simplifies the task of writing and debugging microcode, field maintenance debug and test and system test during manufacture.
The IDT7320 is ideal for high-speed DSP applications which require an easily accessible scratch pad register for coefficients or
data. It can be used as a synchronous FIFO or for video delay lines.
Available packages include 48-pin plastic and ceramic DIP and
surface mount 52-pin LCC and PLCC. Military grade product is
manufactured in compliance with the latest revision of MiLSTD-883, Class B.

• Eight 16-bit high-speed pipeline registers
• Configurable to four two-level, two four-level or eight singlelevel registers
• Powerful instruction set: Transfer, Hold, Load Directly
• Fast 10ns access time
• Serial Protocol Channel (SPC ™ ) for diagnostics
• Functionally replaces four Am29520s
• Used for temporary address storage or programmable pipeline
registers for DSP and Array Processing systems
• Synchronous FIFO applications
• Coefficie~t storage for FIR filters
• Video delay line or temporary data storage applications
• High-performance, low-power, submicron CEMOS ™ technology
• Available in 48-pin plastic and ceramic DIP and 52-pin LCC and
PLCC
• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
· The IDT7320 contains eight 16-bit registers which can be configured to be four two-level, two four-level or eight single-level

FUNCTIONAL BLOCK DIAGRAM

0 0- 15
16

10 - 3

CP

3

Vcc -'111'----••

GND

SPC

--=j2{'--_-'--.

E

"'-_ _ _--'

SE~_2

SDI

soo
C/D

SCLK

CEMOS and SPC are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology, Inc.

7-68

DECEMBER 1987
DSC-2027/-

1017320 16-81T MULTI-LEVEL PIPELINE REGISTER

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATIONS
INDEX
L.1UUUUWiiULJU UUU
7

6

5

4

3

2

:18

U

52 51 50

1

:19

:110
:1 11

:1

12

:113

CONSULT FACTORY
FOR PACKAGE INFO

:1 14
:1 15
:1 16
:117
:118
:119

:1 20
21 22 23 24 25 26 27 28 29 30 31 32 33

nnnnnnnnnnnnn.
LCC/PLCC
TOP VIEW

DIP
TOP VIEW

PIN DESCRIPTION

SERIAL DATA OUTPUT (SDO)

INPUTS

Serial data output pin used for transmitting diagnostic data and
commands to a host system or a cascaded multi-level pipeline
register via its SDI pin.

DATA IN (00-15)

SERIAL CLOCK (SCLK)

Data input port, 16 bits wide.

Input pin used for clocking in diagnostic data and command information at the SOl pin. This pin should be tied low when the diagnostic function is not being used.

CONTROL
MULTIPLEXER SELECT (SELo-2)
Three-bit load control lines select the one of eight registers appearing on the output YO-15.

COMMAND/DATA (C/O)

Command/Data input pin, when tied low, defines the bit pattern
being received at the SDI pin as Data and, when high, defines the
incoming pattern as a command for executing diagnostic function.
This pin should be tied high when the diagnostics feature is not being used.

INSTRUCTION CONTROL (10-3)
Four-bit instruction control lines which determine the operation
to be performed on the registers.

OUTPUTS

CLOCK (CP)

Input clock pin.

DATA OUT (yO-15)
Data output port, 16 bits wide.

OUTPUT ENABLE (OE)

Output Enable latches data onto the output pins
low.

(yo-15)

when

POWER SUPPLY

SERIAL PROTOCOL CHANNEL (SPC)

Vee
One power supply pin, 5V;

SERIAL DATA INPUT (SOl)

VSSO-1

Serial data input pin used for receiving diagnostic data and
commands from a host system or from the SDO pin of a cascaded
multi-level pipeline register.

Two GND pins, OV.

7-69

high-performance CEMOS technology, the IDT7381 can perform
an ALU operation in 30ns. It functionally replaces four 54/74S381
four-bit ALUs in a compact, low-power CMOS 68-pin package.
The arithmetic logic unit is a 16-bit ALU with full carry
lookahead. It operates on two 16-bit operands (Ao-15 and BO-15).
The two-bit operand select (RSo-l) selects the Rand S operands
for the ALU. The three-bit ALU function (ALUo-2) selects the operation to be performed. The IDT7381 can perform 3 arithmetic functions: Not(R) + S, R + Not(S) and R + S; 3 logical functions:
R XOR'S, R OR Sand RAND Sand 2 initialization functions: Set F
to a and Preset F to 1. The 16-bitALU result (F) is available on the
output bus (Y0-15).
The input and 0...!:!!.e.ut registers are enabled under control of external pins: ENA, ENB and ENF, when low. The input and output
registers can be made transQarent under control of FTAB and FTF
pins. When Output Enable (OE) is low, the result is latched on the
output bus.
Two status flags, Overflow (OVF) and Zero, are available as outputs. Also, Propagate (P), Generate (GI), Carry Out (Cnt I6) and
Carry In (C n) are provided to cascade the IDT7381 for 32-bit or
wider data.
The IDT7381 is available in 68-pin surface mount, LCC and
PLCC and Pin Grid Array. Military grade product is manufactured
in compliance with the latest revision of MIL-STD-883, Class B, for
high-reliability systems.

FEATURES:
• High-performance 16-bit cascadable Arithmetic Logic Unit
(ALU)
• Fast 30ns ALU operations (33M Hz)
• 54/748381 instruction set
• Pipeline or Flow-through modes
• Input and output registers can be made transparent
• Cascadable with or without carry lookahead
• Internal feedback path for accumulation
• Pin and functionally compatible with Gould S614381 and
Logic Devices L4C381
• High-speed, low-power submicron CEMOS ™ technology
• Available in 68-pin surface mount PLCC and LCC and 68-pin
PGA
• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
The IDT7381 is a high-speed 16-bit cascadable Arithmetic
Logic Unit (ALU). This three-bus device consists of two input
registers, an ultra-fast 16-bit ALU and a 16-bit output register. With

FUNCTIONAL BLOCK DIAGRAM
A O- 15

8 0- 15

£NA ---~:-=-::-1
CP--~~==~~~________~
r---------------+---~~----,

'--_""T'"_......I4--e----+-'<---- RS O- l

p __--~--~--~----------~--~--7
G ----+----4-

C16 ~---;~------~
OVF ..----+-------~

16-81T ALU

f+------t--'l.----- ALUo-2

z--~j_----~~------__------~

k------+----

Cn

~----------.rIffi83~~--~----------~-----~
Vcc

------'~

GND

----i~

...~------------~-----

'----,.-_

~F

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
D8C-2028/-

7-70

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7381 16-BIT CASCADABLE ALU

PIN CONFIGURATIONS
INDEX

59
5S
57

r:

[:
[:

56 [:

55
54

53
52
51

J68-1
&
l68-2

50

Cn + 16 :120
P :121
G :]22
ZERO :123
OVF :124
"ENF :125
FTF :1 26

49
48
47
46
45
44

[:
[:

r:
r:

[:
[:
[:
[

[:
[:
[
[:

FTA8
RSl
RSo
12
11
10
Cn

VU~~~~~M~~~~~~~Qa

nnnnnnnnnnnnnnnnn

LCC/PLCC
TOP VIEW

11

87

86

84

82

80

ENS

RS l

12

10

85

83

~

E"N"A

FTA8

RS o

11

Cn

Fo

10

89

8s

09

8 11

810

F2

Fl

08

813

8 12

F4

F3

07

8 15

814

F6

F5

06

Al

Ao

Fs

F,

05

A3

A2

FlO

F9

04

A5

A4

F12

Fl1

03

A7

A6

F14

F13

02

As

A9

All

A 13

A 15

Vee

Cn + 16

G

OVF

OE

F15

01

•

A l0

A12

A14

ClK

GND

15

ZERO

"E"1'W

FTF

A

8

C

D

E

F

G

H

J

K

Pin 1 /
Designator

CONSULT FACTORY
FOR PACKAGE INFO

PGA
TOP VIEW

7-71

L

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT738116-BIT CASCADABLE ALU

PIN DESCRIPTION

ENABLE REG F (ENF )

INPUTS

FLOW-THROUGH REG F (FT)

DATA A INPUT (Ao-1S)

Flow-through control input. When this control signal is high, the
F register is transparent.

Register enable for output F register, active low.

Sixteen-bit data input port.

OUTPUT ENABLE (OE)

DATA B INPUT (BO-1S)

A control input pin which, when low, enables the three-state output buffer of YO-15. When high, it disables the three-state output
buffer.

Sixteen-bit data input port

CONTROLS

CARRY IN (C n)

ENABLE REG A (ENA)

Carry In signals a carry input from the lesser significant word in
the cascaded mode.

Register enable for the A Register, active low.
ENABLE REG B (ENB)

OUTPUTS

Register enable for the B Register, active low.
FLOW-THROUGH REG AlB (FTAB)

DATA OUTPUT (Y0-1S)

Flow-through control input. When this control is high, both register A and register B are transparent.

Sixteen-bit output port.
PROPAGATE(P)

OPERAND SELECT (RSo-1)

Propagate, when low, indicates the carry propagate output of
the ALU.

Two-bit inputs are used to select the R-operand for ALU:

OVERFLOW (OVF)

RSEL1

RSELo

MUXR

MUXS

0

0

A

F

0

1

A

0

1

0

0

B

Generate, when low, indicates the carry generate output of the
ALU.

1

1

A

B

CARRY OUT (Cn +1S)

Overflow indicates the two's complement overflow.
GENERATE(G)

Carry Out indicates the carry output.
CLOCK (CP)

ZERO DETECT (ZERO)

Clock Input.

Zero detection output is open-drain and requires a pull-up
resistor.

ALU INSTRUCTION (ALUo-2)

Three-bit instruction control lines determines the ALU operation
to be performed.
ALU 2

ALU 1

ALUo

0

0

0

FORCE F TO LOW

0

0

1

F=ti"+S

0

1

0

F=S+R"

POWER SUPPLY
Vee
One power supply pin, 5V.

FUNCTION

0

1

1

F=R+S

1

0

0

F = EXOR S

1

0

1

F = R ORS

1

1

0

F = RAND S

1

1

1

FORCE F TO HIGH

GND

One ground pin,

7-72

av.

---------------------------------

Bit-Slice Microprocessor Devices (MICROSLICE™) and EDC

(;II

BIT-SLICE MICROPROCESSOR DEVICES (MICROSLICE) AND EDC
Today, as for the past decade, the bit-slice processor offers the
ultimate in microprocessor flexibility and performance. Through
architectural enhancements and a powerful CEMOS technology,
lOT has extended bit-slice performance levels far ahead of rival
products.
The IOT49C4oo building block family exemplifies this performance leadership. Our new architectures enable the user to obtain
magnitudes of increased system speed while maintaining low
CMOS power. Featured in this standard product family are the
world's fastest microprogram microprocessors (including our new
32-bit lOT49C404), sequencers and register files. Additionally, lOT
manufactures pin-compatible CMOS 2900 products which offer
speed upgrades of up to 50% faster than bipolar equivalents.
lOT's streamlined, bit-slice architectures now enable highspeed system designers to develop ultra-fast, innovative systems
which use the most powerful building block product available.
Error detection and correction playa major role in maintaining
the integrity of data in large, high-speed memory boards. lOT's

new family of EOC products not only boost the reliability of memory
systems but do it utilizing ultra-fast CEMOS technology.
In March 1986, lOT introduced its first EOC product, the 16-bit
IOT39C60. It was the first CMOS EOC device ever available and
was also the world's fastest at 20ns maximum detect time. This
new performance plateau set the stage for lOT's next new device,
the industry-leading 32-bit IOT49C460. Available in April 1986, it
too sported the industry's fastest speeds while consuming ultralow CMOS power. It was also the only 32-bit EOC cascadable to
64 bits, ideal for today's large, high-speed systems.
Additionally, both 16- and 32-bit versions are available in spacesaving surface mount and dual in-line packages, aimed at satisfying the most stringent commercial and military product needs.
lOT will continue to introduce performance upgrades to its
existing product family, while. offering many new architectural
enhancements to the world of error detection and correction
products.

TABLE OF CONTENTS
CONTENTS
Blt·Sllce Microprocessor Devices (MICROSLICE TM) and Error Detection and Correction
Bit·Slice Microprocessor Devices (MICROSLlCE)
IDT39C01
4·Bit Microprocessor Slice (14-56) . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. ..
IDT39C02
Carry-Lookahead Generator ............................................................
IDT39C03
4-Bit Microprocessor Slice (14-56) . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . ..
IDT39C09
4-Bit Sequencer.. . . . .. . . . . . . . . . . . . .. . . ... . . . ... .. . . . . . . .. . ... . . . . . . . . . . . . . . . . . . ......
IDT39C11
4-Bit Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT39C10
12-Bit Sequencer (14-56. 14-197) .......................................................
IDT39C203
4-Bit Microprocessor Slice (14-56) ........... ~. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT39C705
16 x 4 Dual-Port RAM .................................................................
16 x 4 Dual-Port RAM .................................................................
IDT39C707
IDT49C25
Microcycle Length Controller ...........................................................
IDT49C40 1
16-BitMicroprocessorSlice ............................................................
IDT49C402
16-Bit Microprocessor Slice (14-41. 14-56. 14-197. 14-200. 14-203) ..........................
IDT49C403
16-Bit Microprocessor Slice w/SPC (14-41.14-56.14-154.14-197) ...........................
IDT49C404
32-Bit Microprogram Microprocessorw/SPC (14-86.14-111.14-154) ............. ~ ............
IDT49C410
16-Bit Sequencer (14-56.14-86.14-197.14-200) ..........................................
IDT49C411
20-Bit Interruptable Sequencer w/SPC (14-154) ............................................
Error Detection and Correction
IDT39C60
16-Bit Cascadable EDC (14-22) ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT49C460
32-Bit Cascadable EDC (14-22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

PAGE

8-1
8-12
8-16
8-48
8-48
8-63
8-74
8-110
8-110
8-117
8-129
8-139
8-150
8-182
8-196
8-208
8-209
8-235

1

~.

\

MICROSLICE ™ PRODUCT

FEATURES:

DESCRIPTION:

e Low-power CEMOS ™

The IDT39C01s are high-speed, cascadable ALUs which can be
used to implement CPUs, peripheral controllers and programmable
microprocessors. The IDT39C01's microinstruction flexibility allows
for easy emulation of most digital computers.
This extremely low-power yet high-speed ALU consists of a
16-word by 4-bit dual-port RAM, a high-speed ALU and the required
shifting, decoding and multiplexing logic. It is expandable in 4-bit
increments, contains a flag output along with three-state data outputs and can easily use either a ripple carry orfuiliookahead carry.
The nine-bit microinstruction word is organized into three groups of
three bits each and selects the ALU destination register, ALU source
operands and the ALU function.
The IDT39C01 is fabricated using CEMOS, a CMOS technology
designed for high-performance and high-reliability. It is a pin-compatible, performance-enhanced, functional replacement for all versions of the 2901.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

-Icc (max.)
Military: 3SmA
Commercial: 30mA
Fast
- IDT39C01C-meets 2901C speeds
- IDT39C01D-20% speed upgrade
-IDT39C01E-40% speed upgrade
e Eight-function ALU

- Performs addition, two subtraction operations and five logic
functions on two source operands
e Expandable

- Longer word lengths achieved through cascading any
number of IDT39C01s
e Four status flags

- Carry, overflow, negative and zero
e Pin-compatible and functionally equivalent to all versions of the
2901
e__
A_va_i_la_b_le_i_n_4_0-_p_in
___
DI p_a_n_d_4_4_-p_i_n_L_C_C
Military product available
compliant to ________________________________________________________
MIL-STD-883,
_

~__---~
••
~

FUNCTIONAL BLOCK DIAGRAM
RAMo

CP--==~~~~~~~~

READ ADDRESS
16 ADDRESSABLE
REGISTERS
B ADDRESS
A
B

READ/WRITE ADDRESS

DATA DATA
OUT OUT
INSTRUCTION
(1)

Cn

G:
P
Cn + 4
F3 (SIGN)
OVR

F=O

CEMOS and MICROSLICE are trademarks of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

DECl:MBER1987
D8O-9OOO/-

8-1

IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

A3
A2
A1

OE
Y3

uuuuu::uuu UU

Y2
Y1

AO

YO

16
18
17
RAM 3
RAM 0

P

OVR
C n+4

IT

VCC

~

F=O
10
11
12
CP

GNO

en
14
15
13

654

U

M O~ 41 40

39 [

RAM 3 ]9
RAMo ] 10
Vcc
F=O

:1

11
L44-1

NC

38 [

is

37 [

OVR

36 [
35 [

IT

34 [

C n +4

10
11
12

33 [

F3
GNO

32 [

en

31 [

14

30 [
29 [

15
13

03

00

CP
NC

82
83

°1
°2
°3
00

80
81

3 2

18 ]7
19 ]8

FLATPACK
(Consult Factory)

18 19 20 21 22 23 24 25 26 27 28

nnnnnnnnnnn

DIP
TOP VIEW

LCC
TOP VIEW

PIN DESCRIPTIONS
PIN NAME

I/O

DESCRIPTION

Ao-A3

I

Four address inputs to the register file Which selects one register and displays its contents through the A port.

8o- B 3

I

Four address inputs to the register file which selects one of the registers in the file, the contents of which is displayed through
the B port. It also selects the location into which new data can be written when the clock goes LOW.

10 -1 8

I

Nine instruction control lines which determine what data source will be applied to the ALU 10. 1. 2, what function the ALU will
perform 13.4.5 and what data is to be deposited in the 0 Register or the register file Ie. 7. 8 .

°0-°3

I

Four-bit direct data inputs which are the ALU data source for entering external data into the device. 0 0 is the LSB.

YO -Y3

0

Four three-state output lines which, when enabled, display either the four outputs of the ALU or the data on the A port of the
register stack. This is determined by the destination code Ie. 7. 8.

F3

0

Most significant ALU output bit (sign-bit).

F=O

0

Open drain output which goes HIGH if the Fo -F3 ALU outputs are all LOW. This indicates that the result of an ALU operation is
zero (positive logic).

en
en + 4

0

03

I
I/O

Bidirectional lines controlled by Ie. 7. 8 . Both are three-state output drivers connected to the TIL-compatible CMOS inputs.
When the destination code on Ie. 7, 8 indicates an up shift, the three-state outputs are enabled, the MSB of the 0 Register is
available on the 0 3 pin and the MSB ofthe ALU output is available on the RAMs pin. When the destination code indicates a down
shirt, the pins are the data inputs to the MSB of the 0 Register and the MSB of the RAM.

I/O

Both bidirectional lines function identically to 0 3 and RAM3 lines except they are the LSB of the 0 Register and RAM.

RAM3

00
RAMo

Carry-in to the internal ALU.
Carry-out of the internal ALU.

DE

I

Output enable on which, when pulled HIGH, the Y outputs are OFF (high impedance). When pulled LOW, the Y outputs are
enabled.

G,P

0

Carry generate and carry propagate output of the ALU. These are used to perform a carry-Iookahead operation.

OVR

0

Overflow. This pin is logically the Exclusive-OR ofthe carry-in and carry-out ofthe MSB ofthe ALU. At the most Significant end of
the word, this pin indicates that the result of an arithmetic two's complement operation has overflowed into the sigh-bit.

CP

I

Clock input. LOW-to-HIGH clock transitions will change the 0 Register and the register file outputs. Clock LOW time is internally
the write enable time for the 16 x 4 RAM which compromises the master latches of the register file. While the clock is LOW, the
slave latches on the RAM outputs are closed, storing the data previously on the RAM outputs. Synchronous MASTER-SLAVE
operation of the register file is achieved by this.

8-2

IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

inputs (b. 14. 15) are used to select the ALU function. This high-§peed
ALU also incorporates a carry-in (Cn) input, carry propagate (P) output, carry generate (G) output and carry-out (Cn + 4) all aimed at accelerating arithmetic operations by the use of carry-Iookahead
logic. The overflow output pin (OVR) will be HIGH when arithmetic
operations exceed the two's complement number range. The ALU
data outputs (Fo, F1. F2. F3) are routed to the RAM Q Register.inputs
and the Y outputs under control of the 16, 17. 18 control signal Inputs.
The MS8 of the ALU is output as F3 so the user can examine the
sign-bit without enabling the three-state outputs. An open drain output, F = 0, is HIGH when Fo = F1 = F2 = F3 = aso thatthe user can
determine when the ALU output is zero by wire-ORing these outputs
together.
REGISTER - The 0 Register is a separate 4-bit file intended for
multiplication and division routines and can also be u~ed .as an a?cumulator or holding register for other types of applications. It IS
driven from a 3-input multiplexer. In the no-shift mode, the multiplexer enters the ALU data into the 0 Register. In either the shift-up
or shift-down mode, the multiplexer selects the 0 Register data appropriately shifted up or down. The 0 shifter has two ports. 0 0 and
03, which operate comparably to the RAM shifter. They are controlled by the 16, 17, 18 inputs.
Register
The clock input of the IDT39C01 controls the RAM,
and A and 8 data latches. When enabled, the data is clocked into the
Register on the LOW-to-HIGH transition. When the clock is HIGH,
the A and 8 latches are open and pass data that is present at the
RAM outputs. When the clock is LOW, the latches are closed and
retain the last data entered. When the clock is LOW and RAM EN is
enabled, new data will be written into the RAM file defined by the 8
address field.

DEVICE ARCHITECTURE:
The IDT39C01 CMOS bit-slice microprocessor is configured four
bits wide and is cascadable to any number of bits (4, 8, 12,16, etc.).
Key elements which make up this four-bit r:nicroprocessor slice are:
(1) the register file (16 x 4 dual-port RAM) with shifter, (2) ALU and (3)
Register and shifter.
REGISTER FILE - RAM data is read from the A port as controlled
by the 4-bit A address field input. Data, as defined by the 8 address
field input, can be simultaneously read from the 8 port of the RAM.
This same code can be applied to the A select and 8 select field with
the identical data appearing at both the RAM A port and 8 port outputs simultaneously. New data is written into the file (word) defined
by the 8 address field of the RAM when activated by the RAM write
enable. The RAM data input field is driven by a 3-input multiplexer
that is used to shift the ALU output data (F). It is capable of shifting
the data up one position, down one position or not shifting at all. The
other inputs to the multiplexer are from the RAM3 and RAMo I/O
pins. For a shift up operation, the RAM3 output buffer is enabled and
the RAMo multiplexer input is enabled. During a shift down operation the RAMo output buffer is enabled and the RAM3 multiplexer
input is enabled. Four-bit latches hold the RAM data while the clock
is LOW with the A port output and 8 port output each driving separate latches. The data to be written into the RAM is applied from the
ALU F output.
ALU - The ALU can perform three binary arithmetic and five logic
operations on the two 4-bit input words Sand R. The S input field is
driven from a 3-input multiplexer and the R input field is driven from
a 2-input multiplexer with both having an inhibit capability. 80th
multiplexers are controlled by the 10. 1,. 12 inputs. This multiplexer
configuration enables the user to select various pairs of the A, 8, D,
and "0" inputs as source operands to the ALU. Microinstruction

o

a

a

o

o

91

-----------------------------------------------------!: .
ALU SOURCE OPERAND CONTROL
MNEMONIC

12

11

10

ALU FUNCTION CONTROL

ALU SOURCE
OPERANDS

MICROCODE
OCTAL
CODE

MICROCODE
MNEMONIC

R

S

15

14

13

OCTAL
CODE

ALU
FUNCTION

SYMBOL

AO

L

L

L

0

A

0

ADD

L

L

L

0

R Plus S

R+S

AB

L

L

H

1

A

B

SUBR

L

L

H

1

S Minus R

S-R

ZO

L

H

L

2

0

0

SUBS

L

H

L

2

R Minus S

R-S

ZB

L

H

H

3

0

B

OR

L

H

H

3

RORS

RVS

ZA

H

L

L

4

0

A

AND

H

L

L

4

RAND S

RAS

DA

H

L

H

5

D

A

NOTRS

H

L

H

5

RANDS

RAS

DO

H

H

L

6

D

0

EXOR

H

H

L

6

REX-OR S

RAJ'S

DZ

H

H

H

7

D

0

EXNOR

H

H

H

7

REX-NOR S

RAJ'S

8-3

IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ALU DESTINATION CONTROL

o REGISTER

RAM
FUNCTION

MICROCODE
MNEMONIC

FUNCTION

18

17

16

OCTAL
CODE

SHIFT

LOAD

SHIFT

OREG

L

L

L

0

X

NONE

NONE

NOP

L

L

H

1

X

NONE

X

RAM
SHIFTER

Y
OUTPUT

LOAD

0
SHIFTER

RAMo

RAM3

00

F-+O

F

X

X

03

X

X

NONE

F

X

X

X

X

X

X

X

RAMA

L

H

L

2

NONE

F-+8

X

NONE

A

X

RAMF

L

H

H

3

NONE

F-+8

X

NONE

F

X

X

X

X

RAMOD

H

L

L

4

DOWN

F/2-+8

DOWN

0/2-+0

F

Fa

IN3

00

IN3

RAMO

H

L

H

5

DOWN

F/2-+8

X

NONE

F

Fa

IN3

00

X

RAMOU

H

H

L

6

UP

2F-+8

UP

20-+0

F

INa

F3

INa

03

RAMU

H

H

H

7

UP

2F-+8

X

NONE

F

INa

F3

X

03

X = DON'T CARE. Electrically, the shift pin is a TIL input internally connected to a three-state output which is in the high-impedance state.
8 = Register Addressed by 8 inputs.
UP is toward MS8; DOWN is toward LS8.

SOURCE OPERAND AND ALU FUNCTION MATRIX
12,1,OOCTAL
OCTAL

15,4,3

ALU
FUNCTION

1

0

4

5

6

7

ALU SOURCE
A,B

0,0

0, B

O,A

D,A

0,0

0,0

A+8

A+8

0

8

A

D+A

0+0

0

R Plus S
en = H

A + 0 + 1

A+8+1

0+1

8 + 1

A + 1

D+A+1

D+0+1

0+1

en = L

0- A-1

8-A-1

0-1

8-1

A-1

A- D-1

0- D-1

-D -1

S Minus R
en = H

O-A

8-A

0

8

A

A-D

O-D

-D

en = L

A- 0-1

A - 8-1

-0 -1

-8 -1

-A -1

D - A-1

D - 0-1

0-1

2

R Minus S
en = H

A-O

A-8

-0

-8

-A

D-A

D-O

D

3

RORS

AVO

AVB

0

B

A

DVA

DVO

D

4

RANDS

AAO

AA8

0

0

0

DAA

DAO

0

5

RANDS

AAO

AA8

0

8

A

DAA

DAO

0

6

REX-OR S

A'V'O

A'V'8

0

8

A

D'V'A

D'V'O

D

7

REX-NOR S

A'V'O

A'V'B

0

8

A

D'V'A

D'V'O

D

A,O
0

1

+

3

2

en

== L

= PLUS; - = MINUS; A = AND; 'V'=

EX-OR; V = OR

8-4

------------------------------------------------------------------------------------------------IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ALU LOGIC MODE FUNCTIONS
OCTAL

15,4,3,

0
1
5
6

3
3
3
3

0
1
5
6

6
6
6
6

0
1
5
6

7
7
7
7

0
1
5
6

7
7
7
7

3
4
7

6
6
6
6

3
4
7

}

,
i

AND'~,

AVO
AV8
DVA
DVO

OR

A"V"O
A"V"8
D"V"A
D"V"O

EX-OR

A"V"O
~
D"V"A
D"V"O

EX-NOR

B

A
D

INVERT

0
8
A
D

PASS

2

3

3
4
7

4
4

2
3

4

4

4
7

5
5
5
5

0
1
5
6

0
8
A
0

PASS

=H

GROUP

FUNCTION

ADD

A+O
A+8
O+A
0+0

ADD
plus one

A+ 0 + 1
A+8+1
D+A+1
D+0+1

2
3
4
7

PASS

0
8
A
D

Increment

0+1
8+1
A+1
D+1

1
1
1
2

2
3'
4
7

Decrement

0-1
8-1
A-1
0-1

PASS

0
8
A
0

2
2
2
1

2
3
4

1's Camp.

-0 -1
-8 -1
-A -1
-D -1

2's com).
(Negate

-0
-8
-A
-0

Subtract
(1's Camp.)

0- A-1
8-A -1
A- D-1
0-0-1
A - 0-1
A- 8-1
0- A-1
0-0 -1

Subtract
(2'sComp.)

O-A
8-A
A-D
O-D
A-O
A-8
D-A
D-O

7
0
1

2

5
6
0

2
2
2

5
6

1

Po = Ro + So

P, = R, + S,
P2 = R2 + S2
P3 = R3 + S3

1\0
1\8
I\A
1\0

MASK

Cn

FUNCTION

DEFINITIONS

0
0
0
0

·ZERO·

=L

GROUP

0
0
0
0

1
1
1
1

Q

2

3

15,4,3, ~,1,O
0
0
0
1
0
5
0
6

AI\O
AI\B
DI\A
DI\O

2

3
3

Cn

OCTAL
FUNCTION

GRPUP

12,1,0

4
4
4
4

ALU ARITHMETIC MODE FUNCTIONS

Go = Ro So

G, = R, S,

G.!

= R2 S2

G:3

= R3 ~
C4 = G3 + P3 G 2 + P3 P2G, + P3 P2 P, Go + P3 P2 P, Poc;,
C 3 = G2 + P2 G, + P2 P, Go + P2 P, Po Cn
+ = OR

LOGIC FUNCTIONS FOR

G, 15, C n + 4

15,4,3

FUNCTION

P

0

R+S

~

1

S

R

2

R-S

3

RVS

4

--

AND OVR

G

G;

+ ~3 G 2 + ~3 ~2 G, + ~3 ~2 ~ Go

I

~p:!~Pa

RI\S

LOW

G3 + G2 + G, + Go

5

RI\S

LOW

6

R"V"S

7

R"V"S

+

4

I

OVR

I

C3"V"C 4

..

Same as R + S equations, but substitute SI for SI in definitions

G3 +G 2 +G, +Go

-

I

~ Pz P, Po + Cn

G3 + G2 + G, + Go + Cn

I

I

~~P'Pa +Cn
G3 + G2 + G, + Go + Cn

Same as R V S equation, but substitute RI for RI in definitions
Same as R V S equation, but substitute RI for RI in definitions

G3 + ~ G2 + ~ ~

G, +

NOTES:

1.

Cn + 4
C .

Same as R + S equations, but substitute RI for RI in definitions

LOW

-

1I

= OR

8-5

~ Pz P, Pol

G3 + P3 G 2 + P3 P2 G,
+ P3 F!? ~ Ja (Go + Cn)

I

...
...
~

~

See Note 2

IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

30

30

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
. specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 5% (Commercial)
Vee = 5.0V ± 10% (Military)

TA = O°C to + 70°C
TA = -55°C to + 125°C
SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP.(2)

MAX.

UNIT

IIH

Input HIGH Current
(All Inputs)

Vee = Max.
VIN = Vee

-

0.1

5

J.lA

IlL

Input LOW Current
(All Inputs)

Vee = Max.
VIN = GND

-

-0.1

-5

J.lA

VOH

Output High Voltage

Vee
VIN

2.4
2.4

4.3
4.3

-

V

VOL

Output Low Voltage

Vee
VIN = \.fH orVIL

-

0.3
0.3

0.5
0.5

V

"'H

Input High Voltage

Guaranteed Logic HIGH Level (1)

2.0

-

-

V

VIL

Input Low Voltage

Guaranteed Logic LOW Level (1)

-

-

0.8

V

-

-0.1
0.1

-10
10

J.lA

-30

-

-

rrA

10H = -1.0mA (MIL.)
IoH = -1.6mA (COM'L.)

= Min.
= \.fH orVIL
= Min.

loz

Output Leakage Current

Vcc = Max.

los

Output Short Circuit Current

Vcc

ioL = 16mA (MIL.)
ioL = 20mA (COM'L.)

VOUT =0
VOUT = VedMax.)

= Min.

VOUT = QV(2)

NOTES:
1. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
2. Not more than one output should be shorted at a time. Duration of the short circuit test shall not exceed one second.
3. Vee = 5.0V@TA +25°C

8-6

IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = O°C to + 70°C
Vcc = 5.0V ± 5% (Commercial)
TA = -55°C to + 125°C
Vcc = 5.0V ± 10% (Military)
VLC = 0.2V
VHC = Vcc - 0 2V
SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

(1)

TYP.(3) MAX.

UNIT

Quiescent Power Supply Current
CP = H (CMOS Inputs)

Vcc = Max.
VHC ~VIH ,"IL ~VLC
fcp= 0, CP = H

-

0.5

5.0

mA

ICCOL

Quiescent Power Supply Current
CP = L (CMOS Inputs)

Vcc = Max.
VHC ~VIH ,"IL ~VLC
fcp = 0, CP = L

-

0.5

5.0

mA

ICCT

Quiescent Input Power Supply (4)
Current (per Input @ TTL High)

Vcc = Max., \'IH = 3.4V, f CP = 0

-

0.3

0.5

mAl
Input

ICCD

Dynamic Power Supply Current

Vcc - Max.
VHC ~VIH ,V 1L ~ VLC
Outputs Open. DE = L

ICCOH

Vcc = Max.,
Outputs Open, OE = L
CP = 50% Duty cycle
VHC ~ \'IH , V1L ~ VLc
50% Data Duty Cycle
Icc

Total Power Supply Current(5)
Vcc = Max.,
Outputs Open, OE = L
CP = 50% Duty cycle
V1H = 3.4V. V1L= O.4V
50% Data Duty Cycle

MIL.

-

1.5

2.5

COM'L.

-

1.0

2.0

-

30

-

35

-

30

IDT39C01C

MIL.

fcp = 10MHz

COM'L.

IDT39C01D

MIL.

fcp = 15MHz

COM'L.

IDT39C01E

MIL.

fcp = 17.5MHz

COM'L.

IDT39C01C

MIL.

-

fcp = 10MHz

COM'L.

-

IDT39C01D

MIL.

fcp = 15MHz

COM'L.

IDT39C01E

MIL.

fcp = 17.5MHz

COM'L.

-

mAl
MHz

25

-

40

-

35

-

45

-

40

mA

35
30
40
35

NOTES:
4. ICCOT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCOH' then dividing by the total number of inputs.
5. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH (CDH)

+

ICCOL (1 - CDH)

+

ICCT (NT x DH)

+

ICCD (fcp)

CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period ("IN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock Input Frequency

3) Definition of input levels is very important. Since many inputs
may change coincidentally, significant noise at the device pins
may cause the VIL and VIH levels not to be met until the noise has
settled. To allow for this testing/board induced noise, lOT recommends using VIL ~ OV and VIH ~ 3V for AC tests.
4) Device grounding is extremely important for proper device testing. The use of multi-layer performance boards witt1 radial decoupiing between power and ground planes is required. The ground
plane must be sustained from the performance board to the OUT
interface board. All unused interconnect pins must be properly
connected to the ground pin. Heavy gauge stranded wire should
be used for power wiring and twisted pairs are recommended to
minimize inductance.

CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be taken into
account when testing high-speed CMOS devices in an automatic
environment. These are:
') Proper decoupling at the test head is necessary. Placement of the
capacitor set and the value of capacitors used is critical in reducing the potential erroneous failures resulting from large Vcc current changes. Capacitor lead length must be short and as close to
the OUT power pins as possible.
2) All input pins should be connected to a voltage potential during
testing. If left floating, the device may begin to oscillate causing
improper device operation and possible latch up.

8-7

IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CYCLE TIME AND CLOCK CHARACTERISTICS

IDT39C01C
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of the
IDT39C01Coverthe-SSoC to + 12SoCand O°Cto +70°Ctemperature range. VCC is specified at SV ±10% for military temperature range and SV ±S% for commercIal temperature range. All
times are in nanoseconds and are measured at the 1.SV signal
level. The inputs switch between OV and 3V with signal transition
rates of 1V per nanosecond. All outputs have maximum DC current
loads.

COMBINATIONAL PROPAGATION DELAYS (1)

CL

MIL

COM'L

Read-Modify-Write Cycle (from
selection of A, B, registers to end
of cycle)

UNIT

32

31

ns

Maximum Clock Frequency to
to shift 0 (50% duty cycle.
I = 432 or 632)

31

32

MHz

Minimum Clock LOW Time

15

15

ns

Minimum Clock HIGH Time

15

15

ns

Minimum Clock Period

32

31

ns

= SOpF
TO OUTPUT

FROM INPUT

Y

G,P

Cn + 4

F3

00
03

RAMo
RAM3

OVR

F=O

UNIT

MIL COM'L MIL COM'L MIL COM'L MIL. COM'L MIL COM'L MIL COM'L. MIL. COM'L MIL COM'L

-

ns
ns

-

-

35

-

-

ns

26

29

26

ns

A, B Address

48

40

48

40

48

40

44

37

48

40

48

40

48

40

D

37

30

37

30

37

30

34

30

40

38

37

30

37

30

-

Cn

25

22

25

22

21

20

-

-

28

25

25

22

28

25

-

10.1.2

40

35

40

35

40

35

44

37

44

37

40

35

40

35

13.4.5

40

35

40

35

40

35

40

35

40

38

40

35

40

Ie. 7. 8

29

25

-

-

-

-

-

-

-

-

-

-

29

A Bypass
ALU (I = 2XX)
Clock

J

ns
ns

40

35

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ns

40

35

40

35

40

35

40

35

40

35

40

35

40

35

33

28

ns

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)

~

CP:

INPUT

-/-

SET-UP TIME
BEFORE H-+L

HOLD TIME
AFTER H-+L

MIL

COM'L.

MIL

A, B Source Address

15

15

2

B Destination Address

15
_(1)

15

-

13.4.5

-

Ie. 7. 8

10

10

RAM 0.3. QO.3.

-

-

D

en
10.1.2

COM'L.
1 (3)

SET-UP TIME
BEFORE L-+H
MIL
30, 15

HOLD TIME
AFTER L-+H

UNIT

MIL

COM'L

2

1

2

1

ns

25

0

0

ns

COM'L

+ TPWL(4)

Do not change (2)

ns

-

20

20

0

0

ns

-

-

-

30

30

0

0

ns

-

-

-

30

3f]

0

0

n~

Do not change (2)

\

0

0

ns

0

0

ns

-

-

-

-

25

12

12'-

OUTPUT ENABLE/DISABLE TIMES
(CL

= SpF, measured to O.SV change of VOUT in nanoseconds)
ENABLE

INPUT

OUTPUT

MIL.

I

I

COM'L

DISABLE
MIL

I

COM'L.

I

23
25
23
25
OE
Y
NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain Signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -+ L transition to a1lowtime to access the source data before the latches close. The A address may then be
changed. The B address could be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4.
set-up time prior to the clock L -+ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes all
the time from stable A and B addresses to the clock L-+ H transition, regardless of when the H -+ L transition occurs.

The

8-8

IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CYCLE TIME AND CLOCK CHARACTERISTICS

IDT39C01D
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of the
IDT39C01Doverthe-SSoC to +12SoCandOOCto +70 0 Ctemperature range. VCC is specified at SV ±10% for military temperature range and 5V ±5% for commercial temperature range. All
times are in nanoseconds and are measured at the 1.5V signal
level. The inputs switch between OV and 3V with signal transition
rates of 1V per nanosecond. All outputs have maximum DC current
loads.

COMBINATIONAL PROPAGATION DELAYS (1) C L

MIL

COM'L

Read-Modify-Write Cycle (from
selection of A, B, registers to end
of cycle)

UNIT

27

23

ns

Maximum Clock Frequency to
to shift 0 (50% duty cycle.
I = 432 or 632)

37

43

MHz

Minimum Clock LOW Time

13

11

ns

Minimum Clock HIGH Time

13

11

ns

Minimum Clock Period

27

23

ns

= 50pF
TO OUTPUT

FROM INPUT

Y

G,P

Cn + 4

F3

Do
a,

RAMo
RAM3

OVR

F=O

UNIT

MIL COM'L MIL COM'L MIL COM'L MIL COM'L MIL COM'L MIL COM'L MIL COM'L MIL COM'L
A. B Address

33

30

33

30

33

30

33

28

33

30

33

30

33

30

D

24

21

23

20

23

20

21

20

25

24

24

21

25

22

Cn

18

17

17

16

14

14

-

-

19

18

17

16

19

18

-

10.1.2

28

26

27

25

26

24

28

24

29

25

27

24

27

25

-

13.4.5

27

26

27

24

26

24

26

24

27

26

26

24

27

26

Ie. 7. 8

18

16

-

-

-

-

-

-

-

:-

-

-

21

A Bypass
ALU (I = 2XX)

26

24

-

-

-

-

-

-

-

-

-

-

27

24

26

23

26

23

25

23

27

24

26

24

Clock

J

-

ns

-

ns

-

ns

-

21

21

21

ns

-

-

-

-

ns

27

24

20

19

ns

ns

ns

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)

~

~

CP:

SET-UPTIME
BEFORE H-+L

INPUT

HOLD TIME
AFTER H-+L

MIL

COM'L

MIL

A, B Source Address

11

10

0

B Destination Address

11
_(1)

10

-

13.4.5

-

-

Ie. 7. 8

7

7

RAM 0.3. 00.3.

-

-

D

en
10.1.2

-

COM'L

SET-UPTIME
BEFORE L-+H
MIL

24. (4)
11 + TPWL
Do not change (2)

0(3)

-

UNIT

COM'L

MIL.

COM'L

21.
(4)
10 + TPWL

2

1

ns

2

1

ns

-

16

16

0

0

ns

-

13

13

0

0

ns

-

19

19

0

0

ns

19
Do not change (2)

19

0

0

ns

0

0

ns

-

9

0

0

ns

-

-

HOLD TIME
AFTER L-+H

9

OUTPUT ENABLE/DISABLE TIMES
(CL

= SpF. measured to O.SV change of VOUT in nanoseconds)
ENABLE

INPUT

OUTPUT

OE

Y

MIL

16

I

I

COM'L

14

DISABLE
MILl COM'L

18

I

16

NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -+ L transition to allow time to access the source data before the latches close. The A address may then be
changed. The B address could be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L -+ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes all
the time frornstable A and B addresses to the clock L-+ H transition, regardless of when the H -+ L transition occurs.

8-9

IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CYCLE TIME AND CLOCK CHARACTERISTICS

IDT39C01E
AC ELECTRICAL CHARACTERISTICS

(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of the
IDT39C01Eoverthe-55°C to +125°CandOOCto +70 0 Ctemperature range. VCC is specified at 5V±10% for military temperature range and 5V ±5% for commercial temperature range. All
times are in nanoseconds and are measured at the 1.5V signal
level. The inputs switch between OV and 3V with signal transition
rates of 1V per nanosecond. All outputs have maximum DC current
loads.

COMBINATIONAL PROPAGATION DELAYS (1)

UNIT

MIL.

COM'L.

Read-Modify-Write Cycle (from
selection of A, B, registers to end
of cycle)

21

20

ns

Maximum Clock Frequency to
to shift (50% duty cycle,
I = 432 or 632)

46

50

MHz

Minimum Clock LOW Time

10

8

ns

Minimum Clock HIGH Time

10

8

ns

Minimum Clock Period

21

20

ns

a

C L = 50pF
TO OUTPUT

Y

FROM INPUT

G,P

Cn + 4

F3

F

00
03

RAMo

=0

OVR

RAM3

UNIT

MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L.
A, B Address

26

22

26

22

26

22

26

21

26

22

26

22

26

22

-

-

ns

D

18

16

17

15

17

15

16

15

19

18

18

16

19

16

-

ns

Cn

13

13

13

12

10

10

-

-

14

13

13

12

14

13

10.1.2

21

20

20

19

19

18

21

18

22

19

20

18

20

19

-

-

13.4.5

20

20

20

18

19

18

19

18

20

20

19

18

20

20

-

-

ns

ns
ns

16. 7,8

13

12

-

-

-

-

-

-

-

-

-

-

16

16

16

16

ns

A Bypass
ALU (I = 2XX)

19

18

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ns

ClockS

20

18

19

17

19

17

19

17

20

18

19

18

20

18

15

15

ns

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)

~

CP:

~

SET-UPTIME
BEFORE H-+L

INPUT

HOLD TIME
AFTER H-+L

MIL

COM'L

MIL.

A, B Source Address

8

7

0

B Destination Address

8

7

D

_(1)

en
10.1.2

-

13.4,5

-

-

16.7,8

5

5

RAM o. 3. Qo. 3.

-

-

COM'L.

0(3)

SET·UP TIME
BEFORE L-+H
MIL.

+1~P~L (4)

-

MIL.

COM'L.

15.7 (4)
+ TPWL

2

1

ns

2

1

ns

-

12

12

0

0

ns

10

10

0

0

ns

14

14

0

0

ns

-

14

14

0

0

ns

0

0

ns

0

0

ns

Do not change (2)

-

-

UNIT

COM'L.

Do not change (2)

-

HOLD TIME
AFTER L-+H

9

9

OUTPUT ENABLE/DISABLE TIMES
(CL

= 5pF, measured to O.5V change of VOUT in nanoseconds)
ENABLE

INPUT
OE

OUTPUT

y

DISABLE

MIL.

I

COM'L.

MIL

I

COM'L.

14

I

10

12

I

12

NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3 .. Source addresses must be stable prior to the H -+ L transition to allow time to access the source data before the latches close. The A address may then be
changed. The B address could be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L -+ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes all
the time from stable A and B addresses to the clock L-+ H transition, regardless of when the H -+ L transition occurs.

8-10

IDT39C01C/D/E 4-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND t03.0V

WIns
1.SV
1.SV
See Figure 4

(TA= +2SOC f = 1.0MHz)

PARAMETER(l)

SYMBOL
CIN

Input Capacitance

COUT

Output Capacitance

CONDITIONS

TYP.

UNIT

= OV

S

pF

VOUT = OV

7

pF

\IN

NOTE:
1. This parameter is sampled and not 100% tested.

INPUT/OUTPUT INTERFACE CIRCUIT
Vcc
ESD
PROTECTION
OUTPUTS
INPUTS

OUTPUTS

Figure 1. Input Structure (All Inputs)

Figure 2. Output Structure
(All Outputs Except F = 0)

Figure 3. Output Structure
(F = 0 Only)

TEST LOAD CIRCUIT

o--e

TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All other Outputs

Open

7.0V

soon

DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to ZOUT of the
Pulse Generator

soon

Figure 4. Switching Test Circuits

ORDERING INFORMATION
IDT

39C01
Device Type

x

X

Package

Process/
Temperature

~y:~NK
~

______________

P

~

Plastic DIP
Sidebraze DIP
CERDIP
LCC

C
D
L

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~

Commercial
(O°C to + 70°C)
Military
(-SSOC to + 12S°C)
Compliant to MIL-STD-883, Class B

Four-Bit Microprocessor Slice
High-Speed Four-Bit Microprocessor Slice
Ultra-High-Speed Four-Bit CMOS Microprocessor Slice

C
D

E

8-11

MICROSLICE ™ PRODUCT

FEATURES:

DESCRIPTION:

• Provides lookahead carries across any number of 4-bit
microprocessor ALUs
• Very high speed and output drive over full temperature and
voltage supply extremes

The IDT39C02A is a high-speed carry lookahead generator built
using advanced CEMOS TM, a dual metal CMOS technology. The
IDT39C02A is generally used with an arithmetic logic unit to provide high-speed lookahead over larger word lengths.
The IDT39C02A is a pin-compatib-Ie, performance enhanced,
functional replacement for all versions of the 2902.

• 6ns typical propagation delay
,
10L = 32mA over full military temperature range'
• CMOS power levels (5~W typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than bipolar (5~W max.)
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8
•

PIN CONFIGURATIONS

~ ~

INDEX

Gl

Vee

151
Go
150

152

G3
153
15

C n +y

:? ~

Go ]
150 ]

4

18 [:

5

17

C G2

Cn

G3

6

16

C

C n+x

153 :J

G2

NC

]

L20-2

NC

Cn

7

15 [:

C nu

] 8

14[:

Cn +y

9

G

GND

1<5"

LJUIIULJ
3 2 U 20 19

10 11

12 13

nnnnn

C n+ z

DIP/CERPACK/SOIC
TOP VIEW

LCC
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM

MICROSLICE and CEMOS are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© "1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
DSC-4059/-

8-12

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C02A CMOS CARRY LOOKAHEAD GENERATOR

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

V

-55 to +125

°C

.,~\

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

-0.5 to +7.0

o to

+70

DC Output Current
50
50
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Vce = 5.0V ± 5% (Commercial)
Vce = 5.0V ± 10% (Military)

TA = O°C to + 70°C
TA = -55°C to + 125°C
VLC = 0.2V
V,He= V.
"CC- 02V
SYMBOL

MIN.

TYP.(2)

MAX.

UNIT

Guaranteed Logic High Level

2.0

-

-

V

Guaranteed Logic Low Level

-

-

0.8

V

Input HIGH Current

Vce = Max., \'IN = Vcc

-

-

5

jJA

-

-5

jJA

-60

-120

-

mA

10H = -300jJA

VHC

Vcc

10H = -12mA MIL.

2.4

4.3

-

V

10H = -15mA COM'L.

2.4

4.3

-

IoL = 300jJA
10L = 32mA MIL.

-

GND
0.3

VLC
0.5

0.3

0.5

TEST CONDITIONS (1)

PARAMETER

VIH

Input HIGH Level

\'IL

Input LOW Level

IIH
IlL

Input LOW Current

Vce = Max., \'IN = GND

Ise

Short Circuit Current

Vce= Max.(3)

VOH

Output HIGH Voltage

Vce = Min.
\'IN = \'IH or\'lL

VOL

Vcc = Min.
\'IN = \'IH or\'lL

Output LOW Voltage

10L = 48mA COM'L.

V

Iccoc

Quiescent Power Supply Current
(CMOS Inputs)

Vcc = Max.
VHC :$ VIN :$ VLC
f = 0

-

0.001

2.0

mA

ICCOT

Quiescent Power Supply Current
(TTL Inputs)

Vcc = Max.
VIN = 3.4V (4)

-

0.5

2.5

mA

Dynamic poW"er Supply
Current

Vcc = Max.
Outputs Open
One Input Toggling
50% Duty Cycle

VHC :$\'IN :$ \te

-

0.15

-

mAl
MHz

VHC :$\'IN :$ VLC

-

1.5

-

\'IN = 3.4V(4)

-

2.0

-

ICCD

Icc

Total Power Supply Current

(5)

Vcc = Max.
f = 10MHz
Outputs Open
50% Duty Cycle
One Input Toggling

16.0
All Inputs
\'IN = 3.4V(4)
NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. Per TTL driven input (VIN = 3.4V); all other inputs at Vce or GND.
5. Icc = Iccoc + (ICCOT x NT) + (ICCD x f x N) + D x ND)
N = Total number of inputs toggling.
f
= Frequency in MHz.
D = Percent high duty cycle.
NT = Number of TTL statically driven inputs (\IN = 3.4V)
ND = Number of TTL dynamically driven inputs (VIN = 3.4V)

8-13

-

mA

IDT39C02A CMOS CARRY LOOKAHEAD GENERATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

DESCRIPTION

Cn

Carry Input

~,G1,G2, G3

Carry Generate Inputs (Active LOW)

tb ' 151 ' 152 ' 153

Carry Propagate Inputs (Active LOW)

Cn + x-q, + z

Carry Outputs

G

Carry Generate Output (Active LOW)

P

Carry Propagate Output (Active LOW)

TRUTH TABLE (1)
Cn

Go

150

X

H

X

H
H
L

H

X

L

X
X

X

X

L

H
H

H

X
X

X
L

H

X

L

X
X
X

X
X

X
X

H
H

H

X
X
X

X
X
L

X
X
X
X

H

X

L

L

Pl

G2

P2

G3

P3

X
X
X

H
H
H
L

X
X
X

X
X

L
L

X
H
H
H

H

X
H

L

X
X
X
X

X
X

L
L

X
X

X
X

H
H

H

X

X
X
X

X
X
L

X
X
X
X

L

X

L

H

Cn +x

Cn+ y

Cn + z

G

P

L
L
H
H

X
X

X
X
X

L

Gl

L
L
L
H
H
H
H
H
H
H
L

X
X
X
X

X
X
X

L
L
L

X
H
H
H

H

X
H

L

X
X
X
X

X
X

L
L

X

H

X

X
X
X

H

X
X

X
X

X

L

L

L

L
L
L
L
H
H
H
H
H
H
H
H
L

X
X
X
X

X
X
X

L
L
L

H

X
X
X

H

H
L

NOTE:
1. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't Care

8-14

H
H
H
H
L
L
L
L
H
H
H
H
L

IDT39C02A CMOS CARRY LOOKAHEAD GENERATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

COMMERCIAL

CONDITION(l)

TYPICAL

MIN.(2)

MAX.

MILITARY
MIN.(2)

UNIT
MAX.

tpLH
tpHL

Propagation Delay
Cn to C n + x
Cn+y.C n + z

6.0

3.0

14.0

3.0

16.5

ns

tpLH
tpHL

Propagation Delay
Po • P, • or P2 • to
C n + x. Cn + y. C n + z

6.0

2.0

9.0

2.0

11.5

ns

tpLH
tpHL

Propagation Delay
Go. G1 • or G2 to
C n + x. C n + y. C n + z

6.0

2.0

9.5

2.0

11.5

ns

tpLH
t pHL

Propagation Delay
P, • P2 or P3 • to G

7.0

3.0

12.0

3.0

16.5

ns

tpLH
t PHL

Propagation Delay
Gn to G

7.5

3.0

12.0

3.0

16.5

ns

tpLH
tpHL

Propagation Delay
Po to P

6.0

2.5

11.0

2.5

12.5

ns

CL = 50pF
RL = 500n

ORDERING INFORMATION
IDT

XXXXX

Device Type

xx

X

Package

Process/
Temperature
Range

y:LANK
P

+ 70°C)

L

Plastic DIP
CERDIP
Small Outline IC
CERPACK
Leadless Chip Carrier

39C02A

Carry Lookahead Generator

D
~------------------~ SO

E

L....------------------i

Commercial (DOC to

Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class 8

8-15

MICROSLICE ™ PRODUCT

FEATURES:

DESCRIPTION:

• Fast
- IDT39C03A matches 2903A speeds

The IDT39C03s are four-bit expandable CMOS microprocessor
slices. While executing the identical functions associated with the
high-speed IDT39 CO 1 series of 4-bit slices, the IDT39C03s also provide additional enhancements for use in arithmetic-oriented processors.
These extremely low-power yet high-speed microprocessors
consist of a 16-word by 4-bit dual-port RAM, a multidirectional threeport architecture, 1610gic operation ALU and the necessary shifting,
decoding and multiplexing logic. Compatible 2903A arithmetic and
logic instructions, including the special multiplication, division and
normalized instructions, are available on the IDT39C03s. Both are
easily expandable in 4-bit increments.
Both devices are pin-compatible, functional-replacements for
the 2903A. The fastest version, the IDT39C03B, is a 20% speed upgrade from the normal 2903A device. The IDT39C03A meets the
2903A speeds.
The IDT39C03s are fabricated using CEMOS TM, a CMOS technology designed for high-performance and high-reliability.
Military grade product is manufactured In compliance with the
latest revision of MIL-STD-883, Class B, making them ideally suited
to military temperature applications.

- IDT39C03B 20% speed upgrade
• Low-power CMOS
- Commercial: 50mA (max.)
- Military: 55mA (max.)
• Pin-compatible, performance enhanced functional replacement for the 2903A
• Cascadable to 8, 12, 16, etc. bits
• Expandable Register File
• On-chip Parity Generation and Sign Extension Logic
- Provide parity across the entire ALU output and sign extension
at any slice boundary
• On-chip Normalized Logic
- Floating-point mantissa and exponent easily developed using
single microcycle per shift
• On-chip multiplication and division logic
- Executes unsigned and two's complement multiplication
along with last cycle of two's complement multiplication
• Packaged in 48-pin plastic and ceramic DIPs and 52-pin LCC
• Military product available compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

4
"'0-3

4

A
ADDRESS

DATA IN

B
ADDRESS

A
RAM
B
DATA OUT
DATA OUT

4

80-3

we

CP

OE"B

DA o-3

DB o_3

D:

4

Cn +4
GIN
15/0VR

10- 8 ~---19~.r---'
[SS 1")---"
~/~

Cn
SIOo

SI03

0100

0103

PLA

!QI---L.-_..J

z

z

'O"E"y

CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.

MILITARY.AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
D8C9OO2/-

8-16

IDT39C03A/IDT39C03B FOUR·BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

o~

010:3
B3
B2
Bl

DAo
DAl

Bo
CP

DA2
DA3

10

12
13
14

i1

WRITE/MSS

CSS

Cn
C n +4
P/OVA
GND

fEi\j

WE
Vee

GIN

15
16
17
18

OEy
Yo

Yl
Y2

OE"B

Y3
SIO O
SI03

Ao
Al

A2
A3
DB3
DB2

Z
DBo
DBl

INDEX
UUUULJLJiiLJULJ
7 6 5 4 3 2 U 52 51 50 49 48 47
~

~

~

46 [:

NC

12

]8

13

]9

45 [:

10

14

:1

10

44

C

i1

11

43 [:

WRITE/MSS

12

42 [:

CSS

C

fEi\j

Cn
C n +4
P/OVA
GND
GIN

OE"y
Yo
Yl
Y2
NC

:1
:1
:1
:1
:1
:1

1

41

13
14

L52-1

C

WE

15

39

16

38 [

15

17

37 [:

16

:118
:1 19

36 [

17

35 [

18

:1

34[

OE"B

:1

20
21 22 23 24 25 26 27 28 29 30 31 32 33

nnnnnnnnnnnnr:

DIP
TOP VIEW
LCC
TOP VIEW

8-17

40 [

Vee

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
PIN NAME

DESCRIPTION

I/O

AO- 3

I

RAM A Address Inputs (TTL Input) - Four RAM address inputs which contain the address ofthe RAM word appearing at the RAM
A output port.

B O- 3

I

RAM B Address Inputs (TTL Input) - Four RAM address inputs which contain the address of the RAM word appearing at the
RAM B output port and into which new data is written when the WE input and the CP input are LOW.

WE

I

Write Enable Input (TTL Input) - The RAM write enable input. If WE is LOW, data at the Y I/O port is written into the RAM when
the CP input is LOW. When WE is HIGH, writing data into the RAM is inhibited.

DA o- 3

I

External Data Inputs (TTL Input) -A 4-bit external data input which can be selected as one of the IDT39C03 ALU operand
sources; DA 0 is the least significant bit.

EA

I

Control Input (TTL Input) - A control input which, when HIGH, selects DA o- 3 as the ALU R operand and, when LOW, selects
RAM output A as the ALU R operand and the DA o_3 output data.

I/O

External Data Inputs/Outputs (Three-State InpuVOutput) - A four-bit external data inpuVoutput. Under control of the 'O'E: B
input, RAM output port B can be directly read on these lines, or input data on these lines can be selected as the ALU S operand.

OE'B

I

Control Input (TTL Input) -A control input which, when LOW, enables RAM output B onto the DB o_3 lines and, when HIGH,
disables the RAM output B tri-state buffers.

Cn

I

Carry-in Input (TTL Input) - The carry-in Input to the IDT39C03 ALU.

lo-a

I

Instruction Inputs (TTL Input) - The nine instruction inputs used to select the IDT39C03 operation to be performed.

TE'N

I

Instruction Enable Input (TTL Input) - The instruction enable input which, when LOW, allows the
Register and the Sign
Compare flip-flop to be written. When lEN is HIGH, the
Register and Sign Compare flip-flop are in the hold mode. On the
IDT39C03, TE'N also controls WRrI1:.

Cn + 4

0

Carry-Out Output (TTL Input) - This output generally indicates the carry-out of the IDT39C03 ALU. Refer to Table 5 for an exact
definition of this pin.

G/N

0

Carry-Generate Output (TTL Output) - A multi-purpose pin which indicates the carry generate, G function, at the least
significant and intermediate slices and generally indicates the sign N of the ALU result at the most significant slice. Refer
to Table 5 for an exact definition of this pin.

P/OVR

0

Carry Propagate Output (TTL Output) - A multi-purpose pin which indicates the carry propagate, P, function at the least
Significant and intermediate slices and indicates the conventional two's complement overflow, OVR, signal at the most
significant slice. Refer to Table 5 for an exact definition of this pin.

DB o- 3

a

a

Z

I/O

Open-Drain I/O Pin (Open-Drain InpuVOutput)-An open-drain inpuVoutput pin which, when HIGH, generally indicates the
outputs are all LOW. For some Special Functions, Z is used as an input pin. Refer to Table 5 for an exact definition of this pin.

SIO o, SI0 3

I/O

Bidirectional Serial Shift I/Os for the ALU (Three-State InpuVOutput) - Bidirectional serial shift inputs/outputs for the ALU
shifter. During a shift-up operation, SIO o is an input and SI03 an output. During a shift-down operation, SI0 3 is an input and
SIO o is an output. Refer to Tables 3 and 4 for an exact definition of these pins.

0100 , 010 3

I/O

Bidirectional Serial Shift I/Os for the a Shifter (Three-State InpuVOutput) - Bidirectional serial shift inputs/outputs for the
a Shifter shifter which operate line SIOo and S10 3 . Refer to Tables 3 and 4 for an exact definition of these pins.

'['SS

I

Control Input (TTL Input) - An input pin which, when tied LOW, programs the chip to act as the least Significant slice (LSS) of an
IDT39C03 array and enables the WRrI1: output onto the WRITE/MSS pin. When LSS is tied HIGH, the chip is programmed to
operate as either an intermediate or most significant slice and the WRITE output buffer is disabled.

WRrI1:/MSS

I/O

Control Input (Three-State InpuVOutput) - When '['SS is tied LOW, the WRrI1: output signal appears at this pin; the WRTfE
signal is LOW when an instruction which writes data into the RAM is being executed. When [SS is tied HIGH, WRITE/MSS is an
input pin; tying it HIGH programs the chip to operate as an intermediate slice (IS) and tying it LOW programs the chip to operate
as the most Significant slice (MSS).

YO-3

I/O

Data Inputs/Outputs (Three-State InpuVOutput) - Four data inputs/outputs of the IDT39C03. Under control of the C5'E'y input,
the ALU shifter output data can be enabled onto these lines, or these lines can be used as data inputs when external data is
written directly into tile RAM.

OEy

I

Control Input (TTL Input) - A control input which, when LOW, enables the ALU shifter output data onto the YO- 3 lines and, when
HIGH, disables the YO- 3 three-state output buffers.

CP

I

Clock Input (TTL Input) - The clock Input to the IDT39C03. The Register and Sign' Compare flip-flop are clocked on the
LOW-to-HIGH transition of the CP signal. When enabled by WE, data is written in the RAM when CP is LOW.

a

8-18

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ARCHITECTURE OF THE IDT39C03
The IDT39C03s are high-performance, cascadable, 4-bit microprocessor slices used in CPUs, peripheral controllers, microprogrammable machines and in a number of other applications.
The functional blocks consist of the following:
- 16-word-by-4-bit dual-port RAM
- high-speed ALU and shifter
- Q register with shifter input

- 9-bit instruction decoder

DUAL-PORT RAM
Both the A and B ports of the dual-port RAM can be addressed
and read simultaneously at the respective RAM A and B output
ports. If both ports address the same memory location, identical
data will be read from both the A and B port. The latches at the RAM
output ports are transparent when the clock input, CP, is HIGH and
holds the RAM output data when CP is LOW. RAM data is read at the
DB (I/O) port under control of the OEB three-state output enable.
External data can be written directly into the RAM from the Y I/O
port, or the ALU shifter output data can be enabled onto the Y I/O
port and entered into the RAM. Data is written into the RAM at the B
address when the write enable input, WE, is LOW and the clock input, CP, is LOW.

ALU
The IDT39C03s perform seven arithmetic operations and nine
logic operations on two 4-bit operands. Various pairs of ALU source
operands are easily selected via the ALU multiplexer inputs. The EA
input selects either the DA external data input or RAM output port A
for use as one ALU operand. The OEB and 10 inputs select RAM output port B, DB external data input or the Q register content for use as
the second ALU source operand. During certain ALU operations, zeros are forced at the ALU operand inputs. Thus, the IDT39C03s are
capable of operating on data from two external sources, from an internal and external source, or from two internal sources. Table 1 indicates all the possible pairs of ALU source operands as a function of
the EA, OEB and 10 inputs.
With instruction bits 14, 13, 12, 11 and 10 LOW, the IDT39C03s execute special functions which have been defined in Table 4. When
the IDT39C03s execute instructions other than the nine special instructions, the ALU operation is defined by instruction bits 14, b, 12,
and 11. Table 2 defines the ALU operation as a function of these four
instruction bits.
Cascading the IDT39C03s, in either the carry lookahead or ripple
carry approach, is very simple. In a cascaded configuration, each
slice must be properly programmed to Most Significant SI ice (MSS),
Intermediate Slice (IS) or Least Significant Slice (LSS). The
IDT39C03s incorporate the carry generate (<3) and carry propagate
(p ) signals necessary for cascading.

TABLE 1.
ALU OPERAND SOURCES(l)
"EA

10

OE

ALU OPERAND R

ALU OPERAND S

L

L

L

RAM Output A

L

L

H

RAM Output A

RAM Output 8
D8 0_3
Q Register

L

H

X

RAM Output A

H

L

L

DA o_3

RAM Output B

H

L

H

DA o- 3
DA o_3

D8 0- 3

H
H
NOTE:
1. L = LOW, H

X

Q

Register

= HIGH, X = Don't Care

8-19

TABLE 2.
IDT39C03 ALU FUNCTIONS
14

13

12

11

HEX
CODE

L

L

L

L

0

L

L

L

H

1

L

L

H

L

2

L

L

H

H

3

L

H

L

L

4

L

H

L

H

5

L

H

H

L

6

L

H

H

H

7

H

L

L

L

8

H

L

L

H

9

H

L

H

L

A

H

L

H

H

B

H

H

L

L

C

H

H

L

H

D

H

H

H

L

E

H

H

H

H

F

NOTE:
1. L = LOW, H

(1)

ALU FUNCTIONS

10 = L I Special Functions
10= H I FI = HIGH
F = S Minus R Minus 1 Plus Cn
F = R Minus S Minus 1 Plus en
F = R Plus S Plus Cn
F = S Plus C n
F = S Plus Cn
F = R Plus Cn
F = R Plus Cn
Ii = LOW
Fj = RI ANDS I
Ii = RI EXCLUSIVE NOR SI
Fj = RI EXCLUSIVE OR SI
Ii = RI AND SI
FI = RI NORS I
FI = RI NAND S,
FI = RI ORS I

= HIGH, i = Ot03

Also generated is a carry-out signal, C n + 4, which is generally
available as an output of each slice. Both the carry-in (Cn ) and carryout (Cn + 4) signals are active HIGH. The ALU generates two other
status outputs. These are negative, N, and overflow, OVR. The N
output is generally the most significant (sign) bit of the ALU output
and can be used to determine positive or negative results. The OVR
output indicates that the arithmetic operation being performed exceeds the available two's complement number range. The Nand
OVR signals are availaQ!e as oU"!puts of the most signif~ant s!!.ce.
Thus, the multipurpose G/N and P/OVR outputs indicate G and P at
the least significant and intermediate slices, and sign and overflow
at the most significant slice. Refer to Table 5 for the exact definition
of these four signals.

ALU SHIFTER
Under instruction contrOl, the ALU shifter passes the ALU output
(F) non-shifted, shifts it up one bit position (2F) or shifts it down one
position (F/2). Both arithmetic and logical shift operations are possible. The arithmetic shift operation shifts data around the most
significant (sign) bit position of the MSS and a logical shift operation
shifts data through this bit position (see Figure 1). SIOo and SI03
are bidirectional serial shift inputs/outputs. During a shift-up operation SI03 is generally a serial shift input and SIOo a serial shift output. For exact definition of the SIOo and SI03 operation, refer to
Tables 3 and 4.
Also provided in the ALU shifter is sign extension at the slice
boundaries. Under instruction control, the SIOo (sign) input can be
extended through Yo, Y 1, Y2, Y 3, and propagated to the SI03 output.
Providing ALU error detection, the IDT39C03s ALU shifter contains a cascadable, five-bit parity generator/checker. Parity for the
Fa, Fl, F2, F3, ALU outputs and SI03 input is generated and, under
instruction control, is made available at the SIOo output.
The operation of the ALU shifter is defined by the instruction
inputs. Specified in Table 4 are the special functions and the
operations the ALU shifter performs. When the IDT39C03s execute
instructions other than special functions,the ALU shifter operation is

Ell
I

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

determined by instruction bits Is. 17. 16 and 15 . How these four bits operate with the ALU shifter is defined in Table 3.

When an instruction which writes data into the RAM is being performed, the WRITE output is LOW. Reference Tables 3 and 4 for
proper pin operation. When lEN is HIGH, the WRITE output is forced
HIGH and the Q R~ster and Sign Compare Flip-Flop contents are
preserved. When lEN is LOW, the WRITE output is enabled and the
Register and Sign Compare Flip-Flop can be written according to
the IDT39C03s instruction. The Sign Compare Flip-Flop is an onchip flip-flop which is used during a divide operation. See Figure 2.

a

ARITHMETIC SHIFT PATH-MSS

~hr

SPECIAL

FUNCTION
AORC

ARITHMETIC SHIFT PATH-LSS/IS

lEN

~ ~g~PARE
D

Q

Figure 2. Sign Compare Flip-Flop
ARITHMETIC AND LOGICAL SHIFT PATHS
ALL SLICE POSITIONS

SLICE POSITION PROGRAMMING

Figure 1.

Q REGISTER
The a Register is an auxiliary 4-bit register which is clocked on
the LOW-to-HIGH transition of the CP input. It is intended primarily
for use in multiplication and division operations; however, it can also
be used as an accumulator or holding register for some applications. The F output of the ALU can be loaded into the a Register and/
or the a Register can be selecte(j as the source for the ALU S operand. The shifter at the input to the a Register can shift the a Register
contents up one bit position (20) or down one bit position (0/2).
Only logical shifts are performed. Both 0100 and 0103 are bidirectional shift serial inputs/outputs. During a a Register shift-up op:eration, 0100 is a serial shift input and 0103 is a serial shift output.
During a shift-down operation, 0103 is a serial shift input and 0100
is a serial shift output.
The IDT39C03s provide the capability of double-length arithmetic and logical shifting. To perform the double-length shift, 0103 of
the MSS is connected to SIOo of the LSB and executing an instruction which shifts both the ALU output and the a Register.
The instruction inputs also control the a Register and shifter, as
shown in Table 4. When executing instructions other than the special functions, the a Register and shifter operation is controlled by
instruction bits Is, 17, 16 and 15, as shown in Table 3.

OUTPUT BUFFERS
80th the DB and Y ports arc bIdirectional I/O ports driven by
three-state output buffers with external output enable controls. The Y
output buffers are enabled when the OEy is LOW and are in the High
Z state when OEy is HIGH. The DB output buffers are enabled when
the OEe Input Is LOW. The zero, Z pin, is an open drain I/O that can
be wire-Ored between slices. As an output it can be used as a zero
detect status flag and generally indicates that the YO-3 pins are all
LOW. Table 5 defines the exact signal functions.

INSTRUCTION DECODER
The Instruction Decoder generates the required internal control
signals relative to the nine instruction inputs, lo-s, the Instruction Enable input, lEN, the LSS input and the WRITE/MSS input/output.

8-20

When the LSS input is LOW, the device becomes the Least Significant Slice and enables the WRITE o~t signal onto the
WRITE/MSS bidirectional I/O pin. When the LSS input is HIGH, the
WRITE/MSS pin becomes an input which when HIGH programs the
slice to operate as an Intermediate Slice (IS). Connecting it LOW
programs the slice to operate as a Most Significant Slice (MSS). The
WRITE/MSS pin must be tied HIGH via a pull-up resistor.
WRITE/MSS and LSS should not be connected together.

SPECIAL FUNCTIONS
Nine special functions are provided on the IDT39C03s which
make possible the implementation of the following operations:
• Single and Double Length Normalization
• Two's Complement Division
• Unsigned and Two's Complement Multiplication
• Conversion Between Two's Complement and Sign/Magnitude
Representation
• Incrementation by One or Two
Adjusting a single-precision or double-precision floating-point
number in order to bring its mantissa within a specified range can be
performed using the single-length and double-length normalization
operations. These special functions can be used to perform a two's
complement, non-restoring divide operation. They provide single
and double-precision divide operations and can be performed in
Un" clock cycles (where Un" is the number of bits in the quotient). The
unsigned multiply special function and the two two's complement
multiply special functions can be used to multiply two n-bit, unsigned or two's complement numbers, respectively, in Un" clock
cycles. During the last cycle of the two's complement multiplication,
a conditional subtraction (rather than addition) is performed due to
the fact that the sign bit of the multiplier carries negative weight.
The sign/magnitude-two's complement special function can be
used to convert number representation systems. A number expressed in sign/magnitude representation can be converted to the
two's complement representation, and vice-versa, in one clock
cycle.
Incrementing an unsigned or two's complement number by one
or two is easily accomplished using the increment by one or two
special function.

IDT39C03A/lDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 3 ALU DESTINATION CONTROL FOR
18 17 16

I
HEX
5 CODE

ALU

10

OR

11

OR

Y3

SI03

SHIFTER
FUNCTION

MOSTSIQ.
SLICE

OTHER
SLICES

MOSTSIG.
SLICE

12

OR

13

= HIGH , IEN=LOW

Y2
OTHER
SLICES

MOSTSIQ.
SLICE

OTHER
SLICES

Y1

YO

SIO O

WRiTE

QREG&
SHIFTER
FUNCTION

010 3

010 0

Z

L L L L

0

Arith. F/2 -t Y

Input

Input

F3

SI0 3

5103

F3

F2

F,

Fa

L

Hold

Z

L L L H

1

Log. F/2 -t Y

Input

Input

5103

5103

F3

F3

F2

F,

Fa

L

Hold

Z

Z

L L H L

2

Arith. F/2 -t Y

Input

Input

F3

SI03

510 3

F3

F2

F,

Fa

L

Log. 0/2
-to

Input

00

L L H H

3

Log. F/2 -t Y

Input

Input

SI03

5103

F3

F3

F2

F,

Fa

L

Log. 0/2
-to

Input

00

L H L L

4

F-tY

Input

Input

F3

F3

F2

F2

F,

Fa

Parity

L

Z

Z

Fo

Parity

H

Input

00

F,

Fa

Parity

H

F-t 0

Z

Z

F1

Fa

Parity

L

F-t 0

Z

Z

F,

Fa SIOo Input

L

Hold

Z

Z

F,

F,

Fa SIOo Input

L

Hold

Z

Z

F1

F1

Fa SIOo Input

L

Log.
20-t0

03

Input

L

Log.
20-t0

03

Input

L H L H

5

F-t Y

Input

Input

L H H L

6

F-tY

Input

Input

F3

F3

F2

F2

L H H H

7

F-tY

Input

Input

F3

F3

F2

F2

H L L L

8

Arith. 2F-t Y

F2

F3

F3

F2

F1

H L L H

9

Log. 2F-t Y

F3

F3

F2

F2

H L H L

A

Arith. 2F -t Y

F2

F3

F3

F2

F3

F3

F2

F2

F,

H L H H

B

Log. 2F-t Y

~

~

F2

F2

F,

Fl

Fa SIOo Input

H H L L

C

F-tY

F3

F3

F3

F3

F2

F2

F1

H H L H

D

F-t Y

H H H L

E

SIOo-t Yo.
Y1 .Y2 .Y3

H H H H

F

F-tY

~
SIO o

NOTE:
1. Parity = F3'V' F2'V' F1'V' Fo'V'SI0 3•

F3

F3
SIO o
F3
L = LOW

~

F3

F2

510 0

SIO o

510 0

F3

~

F2

Z = High Impedance

8-21

Hold
Log. 0/2
-to

F2

F1

Fa
Fa

Z
Z

510 0 SIO o SIO o Input
F2

F1

Fa

Z

'V' = Exclusive OR.

H

Hold

Z

Z

H

Log. 20
-to

03

Input

L

Hold

Z

Z

L

Hold

Z

Z

H = HIGH

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 4. SPECIAL FUNCTIONS FOR 14 = 13 = 12 = 11 = 10 LOW
(HEX)
1.1 7 1• 15

SPECIAL
FUNCTION

0

Unsigned Multiply

ALU
FUNCTION
F=S+C n if Z=L
. F=R+S+C n if Z=H

ALU SHIFTER
FUNCTION

(4)

a

SI03
OTHER
MSS SLICES

REGISTER
SIOo & SHIFTER 0103 0100 WRITE
FUNCTION

Log F/2 4 Y (1)

Z

Input

Fo

Log 0/2
40

Input

00

L

Z

Input

Fa

Log 0/2
40

Input

00

L

1

(5)

2

Two's Complement
Multiply

F=S+C n if Z=L
F=R+S+C n if Z=H

Log F/2 4

3
4

(5)
Increment by
One or Two

F=S+1+C n

F4Y

Input

Input

Parity

Hold

Z

Z

L

5

Sign/Magnitude
Two's COmplement

F=S+C n if Z=L
F=g+C n if Z=H

F4y(3)

Input

Input

Parity

Hold

Z

Z

L

6

Two's Complement
Multiply Last Cycle

F=S+C n ifZ=L
F=S-R-1+Cn if Z=H

Log F/2 4 y(2)

Z

Input

Fa

Log 0/2
40

Input

00

L

7

(5)

8

Single Length
Normalize

F=S+C n

F4 Y

F3

I)

Z

Log 20
40

0 3 Input

L

9

(5)

A

Double Length
Normalize and
First Divide Op

F=S+C n

Log 2F 4 Y

R3"i7'~

F3

Input

Log 20
40

0 3 Input

L

8

(5)

C

Two's Complement
Divide

F=S+R+C n ifZ=L
F=S-R-1 +Cn
ifZ=H

log 2F 4 Y

R3"i7'~

I)

Input

Log 20
40

0 3 Input

L

F=S+R+Cn if Z=L
F=S-R-1+Cn if Z=H

F4Y

F3

F3

Z

Log 20
40

03

Input

L

D

(5)

E

Two's Complement
Divide Correction
and Remainder

F

(5)

Y (2)

NOTES:
1. At the most significant slice only, the C n+ 4 signal is internally gated to the Y:3 output.
2. At the most significant slice only, F3"i7' OVR is internally gated to the Y3 output.
3. At the most significant slice only, S3 "i7' F3 is generated the Y3 output.
4. The 0 Register cannot be used explicitly as an operand for any Special Functions. It is defined implicitly within the functions.
5. NotValid
6. L = LOW, H = HIGH, X = Don't Care, Z = High Impedance, "i7' = Exclusive OR, PARITY = SIO 3"i7' F3"i7' F2"i7' F1"i7' Fo

8-22

- _... - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I DT39C03A/1 DT39C03B FOU R-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 5 IDT39C03A STATUS OUTPUTS
GIN

P/OVR
(HEX) (HEX)
10
18 - 5
14 - 1

GI
(1=0 to 3)

PI
(1=0 to 3)

C n +4

X

0

H

0

1

0

X·

1

X

"Fi l " SI

"FiIVS I

GV PC n

X

2

X

RI " 51

RI V5 1

GVPC n

X

3

X

RI " SI

RIV SI

GV PCn

X

4

X

0

SI

GVPC n

X

5

X

0

51

GVPC n

X

6

X

0

RI

GVPC n

X

7

X

0

AI

GV PC n

X
X
X
X
X
X
X
X

8

0

1
1

F

X
X
X
X
X
X
X
X

0

0

L

1
1

0
8

L
L

2

0

L

3

0

L

"Fil " 51
RI " SI
"Fil " 51
OifZ=L
RI"~ if
Z=H
(Note 6)
(Note 6)
ifZ=L
RI " SI if
Z=H
(Note 6)

0
0
0
0
0
0
0
0

4

0

L

(Note 1)

(Note 2)

0

9
A
B
C

D
E

AI"SI
RI "SI
RI " SI
RI "SI

o

5

0

L

6

0

L

7
8
9
9

0
0
0
8
0
0

L
L
L
L
L
L

o ifZ=L

A

B
C

0

L

D

0

L

E

0

L

F

0

L

RI "

SI if
Z=H
(Note 6)

RI VS I
RI VS I

1
1
1
1
SI ifZ=L
RI V ~ if
Z=H

-

SlifZ=L
RIV SI if
Z=H

-

GV PCn

GVPCn

MOSTSIG. OTHER MOST SIG. OTHER MOST SIG.
SLICES
SLICE
SLICE
SLICES
SLICE

0
Cn + 3"V'
C n +4
Cn + 3"V'
C n +4
n + 3"V'
C n +4
C n + 3"V'
C n +4
C n + 3"V'
C n +4
C n + 3"V'
C n +4
n + 3"V'
C n +4

c

c

0
0
0
0
0
0
0
0
Cn + 3"V'
Cn + 4

F3

G

Yo Y, Y2 Y3

Y OY'Y 2Y 3 Y OY'Y2Y3

15

F3

G

YOY,Y2 Y3

Yo Y, Y2Y3 Yo Y, Y2Y3

J5

F3

G

Yo Y, Y2 '13

Yo Y, Y2 Y3

J5

F3

G

YoY, Y2 Y3

YoY, Y2 Y3 Yo Y, Y2 Y3

J5

F3

G

YoY, Y2 Y3

YoY, Y2 Y3 Yo Y, Y2Y3

F3

G

YoY, Y2 Y3

YoY, Y2Y3 Yo Y, Y2Y3

P

F3

G

YoY, Y2 ?3

YoY, Y2Y3 YoY, Y2 Y3

P

F3

G

YoY, Y2 ?3

Yo Y, Y2 Y3 Yo Y, Y2Y3

0
0
0
0
0
0
0
0

F3
F3
F3
F3
F3
F3

G
G

YOY'Y2 Y 3
Y OY'Y2 Y3
Y OY'Y2 Y3
Y OY'Y2'(3
Yoy, Y2Y3

15

F~

G

F3

G

Y OY'Y2Y3

F3

G

Input

Input

G
G

G
G

-

-

-

-

-

-

-

-

-

f5

F3

G

Input

Input

-

-

-

-

F3

Yo Y, Y2Y3

Yo Y, Y2 Y3

GV PCn

C n + 3"V'
Cn + 4

15

F3 ifZ=L
F3"V'S3 if
Z=H

G

S3

Input

GV PCn

C n + 3"V'
Cn + 4

15

F3

G

Input

Input

-

-

-

-

-

15

03

G

000,0203

-

-

-

-

-

G

(NoteS)

(NoteS)

(Note 5)

-

-

-

-

-

0

SI

(Note 3)

(Note 6)
(Note 6)

-

-

-

-

-

-

0

SI

(Note 4)
-

F2"V'F,

f5

F3

-

-

-

P

F3

G

-

-

-

15

F3

G

-

-

-

R I" SI if
Z=L
RI "SI
Z=H
(Note 6)

RIV SI if
Z=L
RI VSI
Z=H

-

-

00

G

SI ifZ=L
RIV SI if
Z=H

-

-

-

-

SI ifZ=L
SI ifZ=H

RI VS I if
Z=L
"FiIV ~ if
Z=H

00

f5

-

C n + 3"V'
C n +4

(Note 6)

YOY'Y2 Y3
Yo Y, Y2 Y3
YoY, Y2 Y3
YoY, '(2Y3
YoY, Y2Y3
Y OY'Y2 Y3 Yo Y, Y2 Y3
YOY'Y2Y3 YoY, Y2Y3
Y OY'Y2 Y3 '(0'(''(2'(3

YOY'Y2?3
Y OY,Y2'13
Y OY'Y2?3
YoY, Y 2?3
YOY'Y2?3
YoY, Y 2?3
'(oY,Y2?3

C n + 3"V'
Cn + 4

Yo Y, Y2 Y3

P

-

GV PCn

RI " SI if
Z=L
"Fil" SI if
Z=H
(Note 6)

INTERMEDIATE LEAST SIG.
SLICE
SLICE

0

GVPCn

GVPC n

-

02 "V' 0,

-

C n + 3"V'
Cn + 4

C n + 3"V'
Cn + 4

-

Sign
Compare
FF Output

Sign
Compare
FF Output

-

Yo Y, Y2 Y3
Input

00

-

000,020 000,0203

Input

Input

-

-

Input

Input

Continued next page

NOTES:

1.
2.
3.
4.
5.

. Z(OEY = L)

If LSS is LOW, Go = So and G'.2.3 = O. If LSS is HIGH, GO.'.2.3 = O.
If LSS is LOW, Po = 1 and P,.2.3 = S'.2.3- If LSS is HIGH, PI = S I.
At the most significant slice, C n+4 = 0 3 "V'02' At other slices C n+4 = G V PCn.
At the most significant slice, C n+4' = F3 "V' F2 . At other slices C n+4 = G V PCn.
Z = 0 00, 0 2 0 3 ~o ~, 1=2 ~3·

8-23

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES (Cont'd.):
6. Not Valid.
7. L = LOW = O. H = HIGH = 1. V = OR. A = AND. 'V'= EXCLUSIVE OR. P = P 3P2P1Po.
G = G3VG2P3VG1P2P3 VGOP1P2P3.Cn+3= G2 VG 1 P2 VG OP1 P2 VC nPOP1 P2

TIME IN NANOSECONDS
OVER COMMERCIAL OPERATING RANGE

Shown below is a circuit diagram for a 16-bit application using
four IDT39C03s, one IDT39C02 and a status shift control device.
This application has four key speed paths which are defined
below:
1. Mlcrocycle Time (t cHCH )
Minimum elapsed time between a LOW-to-HIGH clock transition and the next LOW-to-HIGH clock transition.
2. Data Set-up Time (t OVCH)
Minimum allowable time between valid data on the D inputs
and the clock LOW-to-HIGH transition.
3. D to Y (tTOVYV )
Maximum time needed to receive valid Y output data after the
D inputs are valid.

t ovcH

tCHYV
CYCLE

tovyv

A

B

A

B

A

Logic

99

79

79

63

Logic Rotate

118

94

99

79

Arithmetic

130

104

109

Multiply

152

122

113

Divide

139

111

113

tCHYV

B

A

59

47

81

65

79

63

98

78

87

91

73

112

90

90

95

76

135

108

90

95

76

121

97

B

4. CP to Y (t TCHYV )
Maximum time required to obtain valid Y outputs after a clock
LOW-to-HIGH transition.

FROM
MICROPROGRAM
MEMORY

DATA IN

r--------------------- 16-------------------- --- -,
I

4

~ SI03
~
STATUS
SHIFT
CONTROL

CP

CLOCK

1

1

I

i

f-f--

•

•

DA

0103
IDT39C03
C MSS

•

I

~

N

z

DA

I

IDT39C02

V

f--

•

DA
IDT39C03
IS

DA
IDT39C03
IS

I
I
I
SIO o
010 0

~

r-

CP PIPELINE
REGISTER

Cn j 4 IDT39C03
LSS
A

I

B
10

Y

CP

Y

CP

Y

CP

Y

CP

L

t

1

t

1

t

I

i

I

1

I

1

I

1

~---------------------

1

-----------------------

16

V-OUT

TIMING WAVEFORM FOR DATA IN , CLOCK AND Y OUTPUT
CP

1+----- tDVCH---~_------- t CHcH ----------+1
D

8-24

IDT39C03A1IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

30

30

mA

SYMBOL

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

C IN

Input Capacitance

C OUT

Output Capacitance

CONDITIONS

TYP.

UNIT

VIN = OV

5

pF

VOUT = OV

7

pF

NOTE:
1. This parameter is sampled and not 100% tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 5% (Commercial)
Vee = 5.0V ± 10% (Military)

TA = O°C to + 70°C
TA = -55°C to +125°C
VLe = 0.2V
VHe = Vee - 0.2V
SYMBOL

TEST CONDITIONS (1)

PARAMETER

MIN.

TYP,!2)

MAX.

UNIT

2.0

-

V

"IH

Input HIGH Level

Guaranteed Logic High Level

"IL

Input LOW Level

Guaranteed Logic Low Level (4)

-

-

0.8

V

IIH

Input HIGH Current

Vec = Max., VIN = Vee

-

0.1

5

~A

IlL

Input LOW Current

Vee = Max., "IN = GND

~A

VOH

Output HIGH Voltage

Vee = Min.
"IN = "'IH or"lL

(4)

-

-0.1

-5

10H = -300~A

VHe

Vee

-

10H = -12mA MIL.

2.4

4.3

IoH = -15mA COM'L.

2.4

4.3

-

-

GND

VLe

0.3

0.5

0.3

0.5

-0.1

-10

0.1

10

-

-

10L = 300~A
VOL

loz

Output LOW Voltage

Off State (High Impedance)
Output Current

Vee = Min.
"IN = "IH or"lL

IoL = 20m A MIL.
10L = 24mA COM'L.

Va = OV
Vee = Max.

Vo = Vee (Max.)

-30
Vee = Min., VOUT = OV(3)
Output Short Circuit Current
los
NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.

8-25

V

V

~A

mA

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = OOC to + 70°C
TA = -55°C to +125°C
VlC = 0.2V
VHC = Vcc - 0.2V
SYMBOL

VCC = 5.0V ±5% (Commercial)
Vcc = 5.0V ±10% (Military)

TEST CONDITIONS

PARAMETER

ICCOH

Quiescent Power Supply Current
CP = H (CMOS Inputs)

Vcc = Max.
VHC ~ VIN • VIN ~ VlC
fcp = O. CP = H

ICCOl

Quiescent Power Supply Current
CP = L (CMOS Inputs)

Vcc = Max.
VHC :5 VIN, VIN ~ VlC
fcp = 0, CP = L

ICCT

Quiescent Input Power Supply(5)
Current (per Input @ TTL High)

Vcc

ICCD

Dynamic Power Supply Current

Vcc = Max.
VHC ~ VIN, \IN .:;: VlC
Outputs Open, BE = L

Total Power Supply Current(6)

TYP.(2)

MAX.

UNIT

-

5

15

mA

-

5

15

mA

-

0.25

0.5

mAl
Input

MIL.

-

0.5

2.0

COM'L.

-

0.5

1.5

MIL.

-

10

35

COM'L.

-

10

30

MIL.

-

20

55

COM'L.

-

20

50

= Max. VIN = 3.4V, fcp = 0

Vcc = Max., fcp.....= 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VHC ~ VIN ' VIN ~ VlC
ICC

MIN.

(1)

Vcc = Max., fc~ 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
\'IH = 3.4V, \'Il = O.4V

mAl
MHz

mA

NOTES:
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCOH, then dividing by the total number of inputs.
6. Total Supply Current isthe sum ofthe Quiescent current and the Dynamic current (at either CMOS orTTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH(CD H) + ICCOl (1 - CD H) + ICCT (NT x DH) + ICCD (fcp)
CDH = Clock duty cycle high period
D H = Data duty cycle TTL high period (V IN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock Input frequency
.

CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test environment. Large output currents are being switched in very short
periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing
results:
1) All input pins should be connected to a voltage potential during
testing. If left floating, the device may oscillate, causing improper
device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be distributed to
decouple power supply lines and be placed as close as possible
to the OUT power pins.

8-26

3) Device grounding is extremely critical for proper device testing.
The use of multi-layer performance boards with radial decoupiing between power and ground planes is necessary. The
ground plane must be sustained from the performance board to
the OUT interface board and wiring unused interconnect pins to
the giOund plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being recommended for minimized inductance.
4) To guarantee data sheet compliance, the input thresholds should
be tested per input pin in a static environment. To allow fortesting
and hardware-induced noise, lOT recommends using Vil ~ OV
and VIH ;::: 3V for AC tests.

-_

.....

_---------------------------------

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED COMMERCIAL
RANGE PERFORMANCE

TABLE 7.
ENABLE/DISABLE TIMES ALL FUNCTIONS(1)

The tables below specify the guaranteed performance of the
IDT39Ca3A over the commercial operating range of aoc to
+ 70°C with Vcc from 4.75 to 5.25V. All data are in nanoseconds,
with inputs switching between a and 3V at 1V/ns and measurements made at 1.SV. All outputs have maximum DC load.

FROM

TO

ENABLE

DISABLE

OEy

Y

25

21

DEB

DB

25

21

la

SIO

25

21

la

010

38

38

la. 7. 6. 5

010

38

38

14.3.2.1.0

010

38

35

WRITE

25

21

TABLE 6. CLOCK AND WRITE PULSE
CHARACTERISTICS ALL FUNCTIONS
Minimum Clock Low Time

30ns

Minimum Clock High Time

30ns

Minimum Time CP and WE both Low to Write

15ns

LSS

NOTE:
1. C L = 5pF for output disable tests. Measurement is made to a 0.5V
change on the output.

TABLE 8 SET-UP AND HOLD TIMES ALL FUNCTIONS
LOW-TO-HIGH

HIGH-TO-LOW
t PWL

FROM

WITH RESPECT TO

SET-UP

HOLD

Y

CP

Don't Care

MHIGH

CP

15

~LOW

CP

Don't Care

Don't Care

A, B Source

CP

20

3

B Destination

CP

6

0100 . 3

CP

Don't Care

Don'tCare

la. 7. 6. 5

CP

12

-

lEN HIGH

CP

24

TEN LOW

CP

Don't Care

Don't Care

14.3.2.1.0

CP

18

-

Don't Care

I
I

SET-UP
14

HOLD
3

COMMENTS
Store Y in RAM/O (1)

0

Prevent Writing

I

15

0

Write into RAM

I

Don't Care

Don't Care

Latch Data from RAM Out

3

Write Data into B Address

TpwL

TpwL

I
I

3

Shift

0

Write into

0

Prevent Writing into

21

0

Write into

a

32

0

Write into

0(2)

TpwL

I
I

a

17
20

0(2)

a

NOTES:
1. The internal V-bus to RAM set-up condition will be met 5ns after valid Y output (DE y = L)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing.
3. For all other set-up conditions not specified in this table, the set-up time should be the delay to stable Y output plus the Y to RAM internal set-up
time. Even if the RAM is not being loaded, this set-up condition ensures valid writing into the register and sign compare flip-flop.
4. WE controls writing into the RAM. lEN controls writing into and, indirectly, controls M through the WRITE'/MSS output. To prevent writing, TEN and
~ must go HIGH during the entire clock LOW time. They may go LOW after the clock has gone LOW to cause a write, provided the WE LOW and
TEN LOW set-up times are met. Having gone LOW, they should not be returned HIGH until after the clock has gone HIGH.
5. A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6. Writing occurs when CP and WE are both LOW. The B address should be stable during this entire period.
7. Because la.7.6.5 controls the writing or not writing of data into RAM and
they should be stable during the entire clock LOW time unless TEN is HIGH,
which prevents writing.
8. The set-up time prior to the clock LOW-TO-H IG H transition occurs in parallel with the set-up time prior to the clock HIGH-TO-LOW transition and the clock
LOW time. The actual set-up time requirement on 14.3.2.1.0 relative to the clock LOW-TO-HIGH transition is the longer of (1) the set-up time prior to
clock L -+ Hand (2) the sum of the set-up time prior to clock H -+ L and the clock LOW time.

a

a

a,

8-27

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED COMMERCIAL RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT BY ONE OR TWO INSTRUCTIONS (SF4)
TO
FROM
Y

C n +4

G,P

Z

A, B Addr

67

55

52

DA,DB

58

50

40

Cn

33

18

N

OVR

DB

WRITE

74

61

67

28

-

-

65

54

58

-

-

35

28

26

-

-

-

010 0 ,3

SI03

SIOo
PARITY

41

62

78

35

59

65

23

30

38

SIOo

18-0

64

64

50

72

61

62

-

34

26*

50*

62*

74*

CP

58

42

43

61

54

58

22

-

22

37

54

60

SIOo, SI03

23

-

29

-

-

-

44

44

44

44

-

44

Y

-

17

-

TEN

-

-

-

-

-

EA

58

50

-

19

44

-

29

MSS

-

35

59

65

-

-

-

-

40

65

54

58

-

-

20

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. Standard Functions: See Table 2, Increment SF4: F = S + 1 + C n

MULTIPLY INSTRUCTIONS (SFO SF2, SF6)
TO
FROM

A, B Addr

DA, DB

Cn

Is-o

CP

Z

SIO o, SI0 3

G,15

Z

N

OVR

DB

(55)

-

-

(61)

(67)

(55)

(52)

(67)

(55)

(52)

-

-

MSS

(58)

(50)

-

-

(54)

(58)

-

IS

(58)

(50)

(40)

LSS

(58)

(40)

MSS

35

150)
(18)

IS

(33)

(18)

LSS

(33)

MSS

SLICE

Y

C n +4

MSS

(67)

IS

(67)

LSS

WRITE

010 0 ,3

SIOo

(28)

-

-

-

(41)

(28)
(28)

-

-

(41)

-

(35)

-

(23)

(26)

73*
73*

(41)

-

-

(28)

(26)

-

(18)

-

-

-

-

-

94

75

-

-

88

88

-

-

-

-

-

-

(26)

(34)

(26)

73*

(22)

(37)

(22)

(37)

-

IS

94

75

71

-

LSS

94

75

71

30

MSS

(58)

(42)

-

(54)

(58)

(22)

(35)
(35)
(23)
(23)

IS

(58)

(42)

(43)

-

-

-

(22)

-

LSS

90

71

67

26

-

-

(22)

-

(22)

69

MSS

64

45

-

-

58

58

-

-

43

-

-

-

43

IS

64

45

41

-

LSS

-

-

-

-

-

Any

(23)

-

-

-

-

-

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or
Two Instruction Test.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. Unsigned Multiply
Two's Complement Multiply
Two's Complement Multiply Last Cycle
SFO: F=S+C n if z=o
SF2: F=S+C n if Z=O
SF6: F=S+C n if Z=O
F=S+R+C n if Z= 1
F=R+S+C n if Z=1
F=S-R-1+Cn if Z=1
Y=Log. F/2
Y=Log. F/2
Y=Log. F/2
0= Log. 0/2
0 = Log. 0/2
0 = Log. 0/2
Y3 =C n +4 (MSS)
Y3 =F3E9 OVR (MSS)
Y3 = OVR E9 F3 (MSS)
Z=Oo (LSS)
Z=Oo (LSS)
Z=Oo (LSS)

8-28

- - -...._ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED COMMERCIAL RANGE PERFORMANCE
DIVIDE INSTRUCTIONS (SFA, SFC, SFE)
TO
FROM

A. B Addr

DA.DB

Cn

18 - 0

CP

Z
SIOo. SI03

SLICE

Y

G,P

Z

N

OVR

DB

WRITE

010 0 • 3

MSS

(67)

61/(55)

-

(74)/-

(61)

(67)

(28)

-

-

62

IS

(67)

(55)

(52)

(74)/-

-

(28)

(41)

C n +4

-

SI03

LSS

(67)

(55)

(52)

(74)/-

-

(28)

-

-

MSS

(58)

55/(50)

-

(65)/-

(54)

(58)

-

-

-

59

IS

(50)
(50)

(40)

(65)/-

-

-

(65)/-

-

1.35)

MSS

(33)

33/(18)

-

(35)/-

(28)

27

IS

(33)

(18)

-

(35)/-

32
(23)

(35)/-

-

-

-

-

-

(23)

(72)/29

(61)177

(62)177

-

-

(35)

(40)

-

-

LSS

(58)
(58)

-

(26)

63/83·

(26)

(62)/83·

-

(34)

(26)

(62)/83·
(54)179

LSS

(33)

(18)

MSS

(64)/84

75/68

-

-

(41)

IS

(64)/84

(64)/68

(50)170

(72)

LSS

(64)/84

(64)/68

(50)170

(72)

-

-

MSS

(58)/80

46/64

-

(61)/25

(54)/66

(58)/66

(22)

-

(22)

IS

(58)

(42)

(43)

(61)/-

-

-

(22)

(22)

(54)

LSS

(58)

(42)

(43)

(61)/-

-

(22)

(22)

(54)

-

-

-

-

-

-

-

-/54

-

-/54

-

-

-

-

-

-

-

MSS

-

-

-

IS

-/55

-/39

-/41

LSS

-/55

-/39

-/41

Any

(23)

-

-

-

-

NOTES:
1. A· _. means the delay path does not exist.
2. An ••• means the output is enabled or disabled by the input. See enable and disable times. A number shown with an ..... is the delay to correct
data on an enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. If two delays are given. the first is for first divide and normalization; the second is for two's complement divide and two's complement divide
correction.
5. Double Length Normalize and First Divide Op
Two's Complement Divide
Two's Complement Divide Correction and Remainder
SFA: F=S+C n
SFC: F=R+S+Cn if Z=O
SFE: F= R+S+C n if z=o
Y=Log.2F
F=S-R-1+C n ifZ=1
F=S-R-1+C n ifZ=1
0=Log.20
Y=Log.2F
Y=F
SI03 = F3 E9 R3(MSS)
0 = Log. 20
0 = Log. 20
Cn +4 = F3 Eft F2 (MSS)
SIO~ = f3W. R3(MSS)
Z= ~3 (MSS) from previous cycle
OVR=f2IDil (MSSL _
Z= 3 E9 3 (MSS) from
Z=QOQ 1 Q 2Q 3 Fo 1=1 F:! ~
previous cycle
6. This specification is not tested but is guranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-29

Ell'

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED COMMERCIAL RANGE PERFORMANCE
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SFS)
TO
FROM

A, B Addr

DA, DB

Cn

Is-o

CP

Z
SIOo, SI0 3

SLICE

Y

G,P

Z

N

OVR

DB

MSS

97

81

-

42

89

89

(28)

-

IS

(67)

(55)

(52)

-

(28)

-

(28)

-

-

C n +4

LSS

(67)

(55)

(52)

-

-

-

MSS

94

76

-

37

84

84

IS

(58)

(50)

(40)

-

-

-

-

32

27

-

-

-

-

LSS

158)

(50)

(40t

MSS

(33)

(18)

IS

(33)

(18)

-

LSS

(33)

(18)

-

-

-

-

-

MSS

85

67

-

28

82

73

-

WRITE

-

-

QIO o, 3

SI03

-

102

-

(62)

-

(62)

-

97
(59)
(59)

-

(30)

(26)

88*

(30)
(30)

IS

85

67

63

-

-

-

(26)

88*

LSS

85

67

63

-

-

-

-

-

-

(34)

(26)

88*

MSS

94

76

-

37

84

84

(22)

(22)

97

IS

(58)

(42)

(43)

-

-

(22)

(22)

(54)

(22)

(54)

-

-

-

-

60

-

60

-

-

-

LSS

(58)

(42)

(43)

-

MSS

-

-

-

-

-

IS

57

39

35

-

-

LSS

57

39

35

-

-

(23)

-

-

-

-

Any

-

-

(22)

-

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct data on an
enabled output.
3. An ( ) means the delay Is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4.SF5:F=S+C n ifZ=0
Y3 =S3EBF3 (MSS)
Q=Q
F = S + C n if Z = 1
Z = S 3 (MSS)
N = F3 if Z = 0
N = F3 EB S3 if Z = 1
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-30

IDT39C03A1IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED COMMERCIAL RANGE PERFORMANCE
SINGLE LENGTH NORMALIZATION (SFS)
TO
FROM

A, BAddr

DA. DB

Cn

18- 0

CP
SIO o , SI0 3

SLICE

Y

G,P

Z

N

OVR

DB

WRITE

010 0 ,3

SI03

MSS

(67)

-

-

-

-

(28)

-

(67)

(55)

(52)

-

(28)

-

LSS

(67)

(55)

(52)

(28)

MSS

(58)

-

-

-

-

-

-

-

(62)

IS

-

(59)

-

-

-

-

-

-

-

-

C n +4

IS

(58)

(50)

(40)

LSS

(58)

(50)

(40)

MSS

(33)

-

-

IS

(33)

(18)

LSS

(33)

(18)

-

-

MSS

(64)

37

-

29

24

24

IS

(64)

(64)

(50)

29

LSS

(64)

(64)

(50)

29

-

-

MSS

(58)

29

-

26

26

IS

(58)

(42)

(43)

26

LSS

(58)

(42)

(43)

26

Any

(23)

-

-

-

-

-

-

(62)
(62)
(59)
(59)
(30)
(30)

-

-

(26)

(62)*

-

-

(26)

(62)*

-

(34)

(26)

(62)*

29

(22)

(22)

(54)

-

-

(22)

-

(22)

(54)

-

-

(22)

(22)

(54)

-

-

-

-

-

-

(30)

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the outputis enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct data on an
enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.

...9:LEIi.

4. SF8: F = S + C n
Cn +.!..=
02 (MSS)
OVR = 02 ffi 01 (MSS)
N = 0 3 (MSS)
Z = 0 0 0 10 2 0 3
Y=F
0= LOG. 20
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-31

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED MILITARY
RANGE PERFORMANCE

TABLE 10.
ENABLE/DISABLE TIMES ALL FUNCTIONS(l)

The tables below specify the guaranteed performance of the
IDT39C03Aoverthe military operating range of -55°Cto + 125°C
with Vcc from 4.5 to 5.5V. All data are in nanoseconds, with inputs
switching between 0 and 3V at 1V/ns and measurements made at
1.5V. All outputs have maximum DC load.

FROM

TO

ENABLE

DISABLE

OEy

Y

25

21

DEe

DB

25

21

Is

SIO

25

21

Is

010

38

38

Is, 7, 6, 5

010

38

38

14,3,2,1, a

010

38

35

WRITE

30

25

TABLE 9. CLOCK AND WRITE PULSE
CHARACTERISTICS ALL FUNCTIONS
Minimum Clock Low Time

30ns

Minimum Clock High Time

30ns

Minimum TIme CP and ~ both Low to Write

30ns

[SS

NOTE:
1. C L = 5pF for output disable tests. Measurement is made to a 0.5V
change on the output.

TABLE 11 SET-UP AND HOLD TIMES ALL FUNCTIONS
HIGH-TO-LOW

LOW-TO-HIGH
t pWL

I
I

FROM

WITH RESPECT TO

SET-UP

HOLD

CP

Don't Care

Don't Care

HIGH

CP

15

WE" LOW

CP

Don't Care

Don'tCare

I

A, B Source

CP

20

3

8 Destination

1

CP

6

0100,3

CP

Don't Care

Don'tCare

Is, 7, 6, 5

CP

12

-

TEN HIGH
lEN LOW

CP

24

CP

Don't Care

Don'tCare

I

21

0

CP

18

-

I

32

0

Y

WE"

14,3,2,1,

a

SET-UP

HOLD

14

3

COMMENTS
Store Y in RAMIO (1)

0

Prevent Writing

15

0

Write into RAM

Don't Care

Don't Care

Latch Data from RAM Out

3

Write Data into B Address

TpWL

TpwL

I
I

a

17

3

Shift

20

0

Write into 0(2)

0

TpWL

Prevent Writing into
'Write into

a

a

Write into 0(2)

NOTES:
1. The internal V-bus to RAM set-up condition will be met 5ns after valid Y output (OI: y = L)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing.
3, For all other set-up conditions not specified in this table, the set-up time should be the delay to stable Y output plus the Y to RAM internal set-up
time. Even if the RAM is not being loaded, this set-up condition ensures valid writing into the a register and sign compare flip-flop.
4. wr;, controls writing into the RAM. lEN controls writing into a and, indirectly, controls
through the WRlTE/MSS output. To prevent writing, TEf\J and
wr;, must go HIGH during the entire clock LOW time. They may go LOW after the clock has gone LOW to cause a write, provided the WE" LOW and
TEN LOW set-up times are met. Having gone LOW, they should not be returned HIGH until after the clock has gone HIGH.
5, A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6. Writing occurs when CP and WE" are both LOW. The B address should be stable during this entire period.
7. Because IS,7.6,5 controls the writing or not writing of data into RAM and 0, they should be stable during the entire clock LOW time unless lEN is HIGH,
which prevents writing.
8. The set-up time prior to the clock LOW-TO-HIGH transition occurs in parallel with the set-up time priorto the clock H IGH-TO-LOW transition and the clock
LOW time. The actual set-up time requirement on 14,3,2,1,0 relative to the clock LOW-TO-HIGH transition is the longer of (1) the set-up time prior to
clock L -+ Hand (2) the sum of the set-up time prior to clock H -+ L and the clock LOW time.

wr:.

8-32

IDT39C03A/IDT39C03B FOUR·BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED MILITARY RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT BY ONE OR TWO INSTRUCTIONS (SF4)
TO
FROM
Y

C n +4

'0,15

Z

N

5100
PARITY

OVR

DB

WRITE

010 0,3

-

23

33

40

36

26*

58*

75*

89*

A, B Addr

70

58

52

78

68

67

28

DA, DB

60

52

40

66

55

58

SIO O

5103

-

47

71

84

-

35

61

74

Cn

35

19

-

41

31

29

18-0
CP

72

69

56

80

71

69

-

60

42

43

67

55

58

22

-

22

41

61

66

SIOo, SI03

26

-

29

-

-

29

19

44

44

44

44

-

-

44

Y

-

-

17

-

-

-

-

44

-

-

-

-

-

-

20

-

-

52

40

66

55

58

-

-

60

-

-

MSS

-

35

61

74

TEN
EA

-

NOTES:
1. A· -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. Standard Functions: See Table 2, Increment SF4: F = S+ 1 + C n

MULTIPLY INSTRUCTIONS (SFO, SF2, SF6)
TO
FROM

A, BAddr

DA,DB

Cn

18- 0

CP

Z
SIOo, SI03

'0,15

Z.

N

OVR

DB

WRITE

010 0,3

5100

(58)

-

-

(68)

(67)

(52)

-

-

-

(70)

(58)

(52)

-

(28)

MSS

62

(52)

-

-

-

(28)
(28)

(55)

(58)

-

-

-

(31)

(29)

-

-

(47)

(58)

-

(26)

81*
81*

SLICE

Y

MSS
IS

72
(70)

LSS

C n +4

(47)
(47)

IS

(60)

(52)

(40)

LSS

(60)

(52)

(40)

MSS
IS

40
(35)

(19)
(19)

LSS

(35)

(19)

-

-

-

MSS

108

84

-

-

98

98

IS

108

84

80

-

LSS

108

84

80

33

-

-

-

MSS
IS

62

(42)

-

-

(55)

(58)

(22)

-

(22)

(60)

(42)

(43)

-

-

(22)

-

(22)

LSS

104

80

74

29

-

-

(41)
(41)

(22)

-

(22)

77

MSS

75

51

-

-

65

65

-

-

IS

75

51

47

-

-

-

-

-

-

Any

(26)

-

-

-

LSS

-

-

-

-

-

-

-

-

-

-

-

(35)
(35)
(35)
(23)
(23)
(23)

-

(26)

(36)

(26)

81*

48
48

-

NOTES:
1. A· -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. Unsigned Multiply
Two's Complement Multiply
Two's Complement Multiply Last Cycle
SFO: F=S+Cn if Z=O
SF2: F=S+C n if Z=O
SF6: F=S+C n if Z=O
F=S+R+C n if Z=1
F=R+S+C n if Z=1
F=S-R-1 +Cn if Z=1
Y = Log. F/2
Y = Log. F/2
Y = Log. F/2
0= Log. 0/2
0 = Log. 0/2
0 = Log. 0/2
Y3 =C n +4 (MSS)
Y3 =F3 EB OVR (MSS)
Y3 = OVREB F3 (MSS)
Z = 0 0 (LSS)
Z = 0 0 (LSS)
Z = 0 0 (LSS)
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-33

IDT39C03A/1DT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED MILITARY RANGE PERFORMANCE
DIVIDE INSTRUCTIONS (SFA, SFC, SFE)
TO
FROM
SLICE

A, BAddr

DA,DB

Cn

16- 0

CP

Z
SIOo, SI03

Y

C n +4

0,15

Z

N

OVR

DB

WRITE

010 0 ,3

SI03

-

-

(71)
(71)

-

(61)

-

-

(61)
(61)

(26)

76/98·

MSS

(70)

72/(58)

-

(78)/-

(68)

(67)

(28)

IS

(70)

(58)

(52)

(78)/-

-

(28)

LSS

(70)

(58)

(52)

(78)/-

-

-

(28)

MSS

(60)

66/(52)

-

(66)/-

(55)

(58)

IS

(60)

(52)
(52)

(40)

(66)/-

-

-

(40)

(66)/-

-

-

37/(19t
(19)

-

(41)/-

(31)

(29)

(41)/-

-

-

-

LSS

(60)

MSS

(35)

IS

(35)

LSS

(35)

(19)

-

(41)/-

-

-

MSS

(72)/96

89/79

-

(80)/33

(71)/91

(69)/91

IS

(72)/96

(69)/79

(56)/79

(80)/-

-

LSS

(72)/96

(69)/79

(56)/79

(80)/-

-

-

MSS

(60)/91

51/74

-

(67)/28

(55)/74

IS

(60)

(42)

(43)

(67)/-

-

LSS

(60)

(42)

(43)

(67)/-

-

MSS

-

-

-

IS

-/63

-/46

-/46

-

LSS

-/63

-/46

-/46

-

-

Any

(26)

-

-

-

-

-

-

(71)

36
(33)
(33)

(26)

(75)/98*

-

(36t

(26)

(75)/98·

(58)/74

(22)

(22)

(61)/93

-

(22)

-

(22)

-

-

-

-

-

-

(22)

(61)

(22)

(61)

-

-

-

-/65

-

-/65

-

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct
data on an enabled output.
3. An ( ) means the delay Is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. If two delays are given, the first is for 1st divide and normalization; the second is for two's complement divide and two's complement divide
correction.
Two's Complement Divide Correction and Remainder
5. Double Length Normalize and First Divide Op
Two's Complement Divide
SFA: F=S+C n
SFC: F=R+S+C n if 2=0
SFE: F=R+S+C n if 2=0
F=S-R-1 +C n if 2=1
Y=Log.2F
F=S-R-1 +C n if 2=1
Y=F
0= Log. 20
Y=Log.2F
0=Log.20
SI03 =F~EB R 3(MSS)
0=Log.20
2=F3 EB R3 (MSS) from previous cycle
C n+4 =F3EB F2 (MSS)
SI0?=F3~ A3(MSS)
OVR=,Ez
(MSS)
2= ~ EB 3 (MSS) from
prevIous cycle
2 = 0 0 01 0'"2031="0 ~1 ~2 ~3
6. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

m.EJ

8-34

I DT39C03A/I DT39C03B FOU R·BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED MILITARY RANGE PERFORMANCE
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SFS)
TO
FROM

A. B Addr

DA. DB

Cn

16- 0

CP

Z
SIOo. SI03

SLICE

Y

Cn+4

G,P

Z

N

OVR

DB

WRITE

QIO O• 3

MSS

114

95

-

49

106

106

(28)

IS

(70)

(58)

(52)

-

-

-

(28)

-

-

(33)

(26)

109*

(26)

109*
109*

LSS

(70)

(58)

(52)

-

-

-

(28)

MSS

108

89

-

43

101

101

IS

(60)

(52)

(40)

-

-

-

-

-

-

-

-

-

35

(29)

-

-

SI03
125
(71)
(71)
119
(61)

LSS

(60)

(52)

(40)

MSS

36

(19)

IS

(35)

(19)

LSS

(35)

(19)

-

-

MSS

98

79

-

33

97

88

IS

98

79

73

-

-

-

LSS

98

79

73

-

-

-

-

-

(36)

(26)

MSS

108

89

-

43

101

101

(22)

(22)

119

IS

(60)

(42)

(43)

-

-

-

(22)

-

(22)

(61)

(22)

(61)

LSS

(60)

(42)

(43)

MSS

-

-

-

IS

65

46

40

LSS

65

46

40

Any

(26)

-

-

-

-

(22)

-

-

-

-

-

-

(61)
(33)
(33)

76
76

-

NOTES:
1. A" - ' means the delay path does not exist.
2. An"*' means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*. is the delay to correct data on an
enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. SF5: F = S + Cn if Z = 0
Y3 = S3 EB F3 (MSS)
Q = Q
F = S + Cn if Z = 1
Z = S3 (MSS)
N = F3 if Z =.0
Y = F
N = F3EBS31fZ = 1
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-35

Ell
•

IDT39C03A!1DT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03A GUARANTEED MILITARY RANGE PERFORMANCE
SINGLE LENGTH NORMALIZATION (SF8)
TO
FROM

A, B Addr

DA,DB

en

18 - 0

CP
SIO o , SI0 3

Cn+4

G,P

Z

N

OVR

DB

WRITE

SLICE

Y

MSS

(70)

-

-

-

-

-

(28)

-

IS

(70)

(58)

(52)

-

-

(28)

-

LSS

(70)

(58)

(52)

-

-

(28)

-

-

(71)
(71)

-

-

(61)

-

-

-

-

-

(33)

-

-

(33)

27

-

(26)

(75)·

MSS

(60)

-

-

-

IS

(60)

(52)

(40)

LSS

(60)

(52)

(40)

-

MSS

(35)

-

IS

(35)

(19)

-

-

-

LSS

(35)

(19)

-

-

-

MSS

(72)

47

-

33

27

-

SI03

-

-

-

QIO o,3

-

(71)
(61)
(61)

IS

(72)

(69)

(56)

33

-

-

(26)

(75)·

LSS

(72)

(69)

(56)

33

-

-

-

-

(36)

(26)

(75)·

MSS

(60)

31

-

28

26

31

(22)

-

(22)

(61)

IS

(60)

(42)

(43)

28

-

(22)

(61)

(60)

(42)

(43)

28

(22)

(22)

(61)

Any

(26)

-

-

-

-

-

(22)

LSS

-

-

-

-

-

(33)

NOTES:
1. A • _. means the delay path does not exist.
2. An ••• means the output is enabled or disabled by the input. See enable and disable times. A number shown with an ••• is the delay to correct data on an
enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. SF8: F = S + en
en + 4= 0:LEJL O2 (MSS)
OVR = O 2
0 1 (MSS)
N = 0 3 (MSS)
Z = '00 '0 10 2 0 3
Y=F
0= LOG. 20
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

EB

8-36

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03B GUARANTEED COMMERCIAL
RANGE PERFORMANCE

TABLE 13.
ENABLE/DISABLE TIMES ALL FUNCTIONS(l)

The tables below specify the guaranteed performance of the
IDT39C03B over the commercial operating range of O°C to
+ 70°C with Vee from 4.75 to 5.25V. All data are in nanoseconds,
with inputs switching between 0 and 3V at 1VIns and measurements made at 1.5V. All outputs have maximum DC load.

FROM

TO

ENABLE

DISABLE

C5""E"y

Y

20

17

ora

DB

20

17

la

SIO

20

17

la

010

30

30

la, 7, 6, 5

010

30

30

14,3,2,1,0

010

30

30

~

20

17

TABLE 12. CLOCK AND WRITE PULSE
CHARACTERISTICS ALL FUNCTIONS
Minimum Clock Low Time

24ns

Minimum Clock High Time

24ns

Minimum Time CP and ~ both Low to Write

12ns

[SS

NOTE:
1. C L = 5pF for output disable tests. Measurement is made to a 0.5V
change on the output.

TABLE 14. SET-UP AND HOLD TIMES ALL FUNCTIONS
HIGH-TO-LOW

LOW-TO-HIGH
tpWL

FROM

I

WITH RESPECT TO

SET-UP

Y

CP

Don't Care

~HIGH

CP

12

~LOW

CP

Don't Care

Don't Care

A, B Source

CP

16

3

B Destination

CP

5

010 0,3

CP

Don't Care

Don't Care

la, 7, 6, 5

CP

10

-

fEi\J HIGH

CP

19

fEi\JLOW

CP

Don't Care

Don't Care

I

14,3,2,1.0

CP

14

-

I

HOLD
Don't Care

SET-UP

.1

HOLD

11

TpWL

COMMENTS

3

Store Y in RAM/O (1)

0

Prevent Writing
Write into RAM

I

12

0

1

Don't Care

Don't Care

Latch Data from RAM Out

3

Write Data into B Address

TpWL

I
I

a

14

3

Shift

16

0

Write into

0

Prevent Writing into

17

0

Write into

a

25

0

Write into

0(2)

TpWL

0(2)

a

NOTES:
1. The intemal V-bus to RAM set-up condition will be met 5ns after valid Y output (C5""E"y= L)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing,
3. For all other set-up conditions not specified in this table, the set-up time should be the delay to stable Y output plus the Y to RAM internal set-up
time. Even if the RAM is not being loaded, this set-up condition ensures valid writing into the register and sign compare flip-flop.
4. ~ controls writing into the RAM. lEN controls writing into and, indirectly, controls WE through the WRITE/MSS output. To preventwr.!!!!!9, fEi\J and
~ must go HIGH during the entire clock LOW time. They may go LOW after the clock has gone LOW to cause a write, provided the WE LOW and
fEi\J LOW set-up times are met. Having gone LOW, they should not be returned HIGH until after the clock has gone HIGH.
5. A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6. Writing occurs when CP and WE are both LOW, The B address should be stable during this entire period,
7. Because la,7,6,5 controls the writing or not writing of data into RAM and 0, they should be stable during the entire clock LOW time unless fEi\J is HIGH,
which prevents writing.
8. The set-up time prior to the clock LOW-TO-HIGH transition occurs in parallel with the set-up time prior to the clock HIGH-TO-LOW transition and the clock
LOW time. The actual set-up time requirement on 14,3,2,1,0 relative to the clock LOW-TO-HIGH transition is the longer of (1) the set-up time prior to
clock L -+ Hand (2) the sum of the set-up time prior to clock H -+ L and the clock LOW time.

a

a

8-37

Ell

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03B GUARANTEED COMMERCIAL RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT BY ONE OR TWO INSTRUCTIONS (SF4)
TO
FROM

SIOo
PARITY

G,15

Z

N

OVR

DB

WRITE

010 0,3

SIOO

SI03

44

41

60

49

54

23

50

62

32

52

43

47

-

-

33

40

28

47

52

Y

C n +4

A. B Addr

54

DA.DB'

46

Cn

26

15

-

28

22

20

-

-

19

24

30

18-0

51

51

40

58

49

50

-

27

21*

40*

50*

59*

CP

46

34

35

49

43

47

18

-

18

30

43

48

SIOo. SI03

19

-

23

-

-

-

-

-

23

15

'MSS

35

35

35

35

35

35

-

-

14

-

-

-

-

Y

-

-

-

-

-

-

-

16

32

52

43

47

-

-

TE"fJ

-

-

'EA

46

40

-

-

-

-

28

47

52

NOTES:
1. A" - " means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. Standard Functions: See Table 2. Increment SF4: F = S + 1 + Cn

MULTIPLY INSTRUCTIONS (SFO, SF2 SF6)
TO
FROM

A. B Addr

DA. DB

Cn

18- 0

CP

Z
SIOo. SI03

G,P

Z

N

OVR

DB

WRITE

SLICE

Y

MSS

(54)

(44)

-

-

(49)

(54)

(23)

-

IS

(54)

(44)

(41)

-

-

-

(23)

LSS

(54)

(44)

(41)

-

-

-

(23)

MSS

(46)

(40)

-

(43)

(47)

-

-

-

C n +4

IS

(46)

(40)

(32)

-

LSS

_(46)

J40)

_(32)

-

-

-

MSS

28

(15)

-

(22)

, (20)

IS

(26)

(15)

-

LSS

(26)

(15)

-

-

-

-

MSS

75

60

-

-

70

70

IS

75

60

57

-

-

-

(43)

(47)

-

-

(18)

46

46

-

LSS

75

60

57

24

MSS

(46)

(34)

-

IS

(46)

(34)

(35)

-

LSS

72

57

54

21

MSS

51

36

-

IS

51

36

33

-

-

-

-

Any

(19)

-

-

-

LSS

-

-

-

-

-

-

010 0 • 3

SIOo

-

(33)
(33)
(33)
(28)
(28)
(28)

-

-

(21)

58*

(21)

58*

-

(27)

(21)

58*

(18)

-

(18)

(30)

-

(18)

(30)

(18)

55

-

-

34

-

(18)

-

-

(19)
(19)
(19)

34

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct
data on an enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. Unsigned Multiply
Two's Complement Multiply
Two's Complement Multiply Last Cycle
SFO: F=S+C n if Z=O
SF2: F=S+C n if Z=O
SF6: F=S+C n if Z=O
F=S+R+C n if Z= 1
F=R+S+C n if Z=1
F=S-R-1 +Cn if Z=1
Y = Log. F/2
Y = Log. F/2
Y = Log. F/2
0= Log. 0/2
0 = Log. 0/2
0 = Log. 0/2
Y3 =C n+4(MSS)
Y3 =F3 ffiOVR(MSS)
Y3 = OVRffi(MSS)
Z=Oo (LSS)
Z=Oo (LSS)
Z=Oo (LSS)
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-38

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03B GUARANTEED COMMERCIAL RANGE PERFORMANCE
DIVIDE INSTRUCTIONS (SFA, SFC, SFE)
TO
FROM

A, B Addr

DA, DB

Cn

18- 0

CP

Z
SIOo, SI03

Y

C n +4

MSS

(54)

48/(44)

IS

(54)

(44)

SLICE

0,15

Z

N

OVR

DB

-

(60)/-

(49)

(54)

(41)

(60)/-

-

(23)

-

-

-

(28)

-

-

(19)

-

-

(19)

(21)

(50)/66*

LSS

(54)

(44)

(41)

(60)/-

-

-

MSS

(46)

44/(40)

-

(52)/-

(43)

(47)

IS

(46)

(40)

(32)

(52)/-

-

WRITE

010 0 ,3

(23)

-

-

50

(23)

-

-

(33)

-

-

(33)

-

-

(28)

LSS

(46)

(40)

(32)

(52)/-

-

MSS

(26)

26/(15)

(28)/-

(22)

23

IS

(26)

(15)

-

(28)/-

-

(28)/-

-

-

-

-

57/23

(49)/62

(50)/73

-

LSS

(26)

(15)

MSS

(51)/67

(51)/54

-

IS

(51)/67

(51)/54

(40)/56

57/-

LSS

(51)/67

(51)/54

(40)/56

57/-

-

-

MSS

(46)/64

37/51

-

(49)/20

(43)/53

IS

(46)

(34)

(35)

(49)/-

LSS

(46)

(34)

(35)

(49)/-

-

MSS

-

-

-

IS

-/44

-/31

-/33

-

LSS

-/44

-/31

-/33

-

Any

(19)

-

-

-

SI03

47

26

-

(21)

(50)/66*

-

(27)

(21)

(50)/66*

(47)53

(18)

-

(18)

(43)/63

-

(18)

(18)

(43)

(18)

-

(18)

(43)

-

-

-

-

-

-

-

-/43

-

-

-

-/43

-

-

-

NOTES:
1. A· - " means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. If two delays are given, the first is for 1st divide and normalization; the second is for two's complement divide and two's complement divide
correction.
Two's Complement Divide Correction and Remainder
5. Double Length Normalize and First Divide Op
Two's Complement Divide
SFE: F=R+S+C n ifZ=O
SFA: F=S+C n
SFC: F= R+S+C n if Z=O
F=S-R-1+C n ifZ=1
Y=Log.2F
F=S-R-1+C n ifZ=1
Y=F
0=Log.20
Y=Log.2F
0=Log.20
SI03 = F €a R (MSS)
0 = Log. 20
Z = F3 E9 R3(MSS) from previous cycle
C n + 4 =~3E9 ~(MSS)
SI0~=F3~ H3(MSS)
OV~=
ill £J (MSS)
Z = ~ E9 3 (MSS) from
Z=OoQ, 0"2 Q3r-o 'F", 'F"2 'F"3
prevIous cycle
6. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

.5!

8-39

JDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C038 GUARANTEED COMMERCIAL RANGE PERFORMANCE
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SFS)
TO
FROM

A. B Addr

OA. DB

Cn

18- 0

CP

Z

SLICE

Y

c,,+4

G,P

Z

N

OVR

DB

WRITE

010 0 ,3

SI03

-

(50)

MSS

77

65

-

34

72

72

(23)

-

IS

(54)

(44)

(41)

-

(23)

-

(23)

-

-

(24)

(21)

70·

LSS

(54)

(44)

(41)

-

-

-

MSS

75

60

-

30

67

67

-

IS

(46)

(40)

(32)

-

-

-

26

22

-

-

-

-

-

-

82
(50)

-

78

-

(47)

LSS

14ra

140)

J32t

MSS

(26)

(15)

-

IS

(26)

(15)

-

LSS

(26)

(15)

-

-

MSS

68

54

-

23

66

58

-

IS

68

54

50

(21)

70·

54

50

-

-

-

68

-

-

LSS

-

(27)

(21)

70·

MSS

75

60

-

30

67

67

(18)

-

(18)

77

IS

(46)

(34)

(35)

-

-

-

(18)

-

(18)

(43)

(18)

-

(18)

(43)

-

-

-

-

-

48

-

-

48

LSS

(46)

(34)

(35)

MSS

-

-

-

-

IS

46

32

28

-

-

LSS

(19)

32

28

-

-

-

-

147)
(24)
(24)

NOTES:
1. A" -" means the delay path does not exist.
2. An "." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct data on an
enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. SF5: F = S + Cn if Z = 0
Y3 = S3
F3 (MSS)
0 = Q
F = S + Cn if Z = 1
Z = S3 (MSS)
N = F3 if Z =.0
N = F3
S3 If Z = 1
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

EB

EB

8-40

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C038 GUARANTEED COMMERCIAL RANGE PERFORMANCE
SINGLE LENGTH NORMALIZATION (SF8)
TO
FROM

A, B Addr

DA, DB

Cn

18 - 0

CP

Z
SIOo. SI0 3

SLICE

Y

MSS

(54)

IS

(54)

G,P

Z

N

OVR

DB

WRITE

QIO o,3

SI03

-

(41)

-

(23)

(44)

-

(23)

-

-

(50)

(23)

-

-

(50)

-

-

-

(47)

-

-

(47)
(47)

C n +4

LSS

(54)

(44)

(41)

-

MSS

(46)

-

-

-

IS

(46)

(40)

(32)

-

-

(50)

LSS

(46)

(40)

(32)

-

-

-

(26)

-

-

-

-

(26)

(15)

-

-

(24)

LSS

(26)

(15)

-

-

-

-

IS

-

-

-

MSS

-

(24)

MSS

(51)

30

-

23

19

19

-

-

(21)

(50)*

IS

(51)

52

(40)

23

-

-

-

-

(21)

(50)*

LSS

(51)

52

(40)

23

-

-

-

(27)

(21)

(50)*

MSS

(46)

23

-

21

21

21

(18)

(18)

(43)

IS

(46)

(34)

(35)

21

-

(18)

(18)

(43)

LSS

(46)

(34)

(35)

21

-

(18)

-

(18)

(43)

MSS

-

-

-

-

-

-

-

LSS

-

-

-

-

-

-

(19)

-

-

Any

-

-

-

-

-

-

IS

-

-

-

-

-

-

-

(24)

NOTES:
1. A "-" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct data on an
enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. SF8: F = S + C n
C n +~= Sl:LEIL O2 (MSS)
OVR = O 2 EB 0, (MSS)
N = 0 3 (MSS)
Z = 0 0 0,0 2 0 3
Y = F
0= LOG. 20
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-41

GIl
I

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03B GUARANTEED MILITARY
RANGE PERFORMANCE

TABLE 16.
ENABLE/DISABLE TIMES ALL FUNCTIONS(l)

The tables below specify the guaranteed performance of the
IDT39C038 over the military operating range of -SSOCto + 125°C
with \6c from 4.5 to S.SV. All data are in nanoseconds. with inputs
switching between 0 and 3V at 1VIns and measurements made at
1.SV. All outputs have maximum DC load.

FROM

TO

ENABLE

C5"E"y

Y

20

17

DEB

DB

20

17

TABLE 15. CLOCK AND WRITE PULSE
CHARACTERISTICS ALL FUNCTIONS
Minimum Clock Low Time

24ns

Minimum Clock High Time

24ns

Minimum Time CP and

wr:. both Low to Write

DISABLE

Is

SIO

20

17

Is

010

30

30

Is, 7, 6, 5

010

30

30

14,3,2,1,0

010

30

28

WRiTE'

24

20

['SS

NOTE:
1, C L = 5pF for output disable tests, Measurement is made to a 0,5V
change on the output.

24ns

TABLE 17 SET-UP AND HOLD TIMES ALL FUNCTIONS
HIGH-TO-LOW

LOW-TO-HIGH
tpWL

FROM

I
I

WITH RESPECT TO

SET-UP

HOLD

Y

CP

Don't Care

Don't Care

SET-UP

HOLD

11

3

wr:. HIGH

CP

12

WE" LOW

CP

Don't Care

Don't Care

A, B Source

CP

16

3

B Destination

CP

5

0100,3

CP

Don't Care

Don't Care

Is, 7, 6, 5

CP

10

-

TEN HIGH
TEN LOW

CP

19

0

Prevent Writing into Q

CP

Don't Care

Don't Care

l

17

0

Write into

14,3,2,1,0

CP

14

-

I

25

0

Write into 0(2)

0

Prevent Writing

12

0

Write into RAM

Don't Care

Don't Care

Latch Data from RAM Out

3

Write Data into B Address

TpWL

I
I

COMMENTS
Store Y in RAM/Q (1)

TpWL

I
I

14

3

ShiltQ

16

0

Write into 0(2)

TpWL

a

NOTES:
1, The internal V-bus to RAM set-up condition will be met 5ns alter valid Youtput (~y= L)
2. The set-up time with respect to CP falling edge is to prevent writing, The set-up time with respect to CP rising edge is to enable writing,
3, For all other set-up conditions not specified in this table, the cot-up tim~ :;hou!d bo tho delay to stable Y output plus the Y to RAM internal set-up
time, Even if the RAM is not being loaded, this set-up condition ensures valid writing into the Q register and sign compare flip-flop,
4,
controls writing into the RAM, TEN controls writing into and. indirectly, controls WE" through the WRITE"/MSS output. To prevent writing, lEN and
WE" must go HIGH during the entire clock LOW time, They may go LOW alter the clock has gone LOW to cause a write, provided the WE LOW and
TEN LOW set-up times are met. Having gone LOW, they should not be returned HIGH until alter the clock has gone HIGH.
5, A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6. Writing occurs when CP and WE" are both LOW. The B address should be stable during this entire period.
7. Because IS,7,6,5 controls the writing or not writing of data into RAM and a, they should be stable during the entire clock LOW time unless lEN is HIGH,
which prevents writing.
8. The set-uptime prior to the clock LOW-TO-HIGH transition occurs in parallel with the set-up time prior to the clock HIGH-TO-LOWtransition and the clock
LOW time. The actual set-up time requirement on 14 ,3,2,1,0 relative to the clock LOW-TO-HIGH transition is the longer of (1) the set-up time prior to
clock L ~ Hand (2) the sum of the set-up time prior to clock H ~ L and the clock LOW time.

wr:.

a

8-42

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03B GUARANTEED MILITARY RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT BY ONE OR TWO INSTRUCTIONS (SF4)
TO
FROM

SIOo
PARITY

Y

C n +4

G,P

Z

N

OVR

DB

WRITE

010 0 • 3

SIOo

SI03

A. B Addr

56

46

42

62

55

54

23

-

57

67

48

42

32

53

44

46

-

28

49

59

-

-

38

DA.DB

19

26

32

29

21

46

60

72

-

18

33

49

53

-

-

23

15

-

-

35

-

-

-

-

-

28

49

59

Cn

28

15

-

33

25

23

18- 0

57

55

45

64

57

55

-

CP

48

33

34

54

44

46

18

SIOo. SI03

20

-

23

-

-

-

MSS

35

35

35

35

35

-

Y

-

-

-

14

-

-

-

-

-

48

42

32

53

44

46

-

lEN
EA

16

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. Standard Functions: See Table 2. Increment SF4: F = S + 1 + Cn

MULTIPLY INSTRUCTIONS (SFO,

SF2~

SF6)
TO

FROM

A. B Addr

DA.DB

Cn

18-0

CP

Z
SIOo. SI03

SLICE

Y

C n +4

'0,15

Z

N

OVR

DB

WRITE

010 0• 3

SIOo

MSS

58

(46)

-

(55)

(54)

(23)

-

IS

(56)

(46)

(42)

-

-

(23)

(38)

-

(23)

(44)

(46)

-

-

(28)

-

-

-

-

-

(28)

(25)

(23)

-

-

-

-

-

78

78

-

(21)

-

-

(21)

65*

(29)

(21)

65*

-

(18)

(33)
(33)

(18)

62

-

-

38

IS

(28)

(15)

-

LSS

(28)

(15)

-

MSS

86

67

-

IS

86

67

64

-

LSS

86

67

64

27

-

MSS

50

-

(44)

(46)

(48)

(33)
(33)

-

IS

(34)

-

-

-

52

52

-

-

LSS

(56)

(46)

(42)

MSS

50

(42)

-

IS

(48)

(42)

(32)

LSS

(48)

(42)

(32)

MSS

32

(15)

LSS

83

64

59

23

MSS

40

-

IS

60
60

40

38

LSS

-

-

Any

(20)

-

-

-

-

(18)
(18)
(18)

-

-

-

-

-

(18)

(38)
(38)

(28)
(19)
(19)
(19)
65*

38

-

-

NOTES:
1. A· - .. means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See. enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. Unsigned Multiply
Two's Complement Multiply
Two's Complement Multiply Last Cycle
SFO: F=S+Cn if Z=O
SF2: F=S+C n if z=o
SF6: F=S+C n if z=o
F=S+R+C n ifZ=1
F=R+S+C n ifZ=1
F=S-R-1+C n ifZ=1
Y=Log. F/2
Y=Log. F/2
Y=Log. F/2
0= Log. 0/2
0 = Log. 0/2
0 = Log. 0/2
Y 3 =C n +4(MSS)
Y3 =F3 E90VR(MSS}
Y3 = OVR E9 (MSS)
Z = 0 0 (LSS)
Z = 0 0 (LSS)
Z = 0 0 (LSS)
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-43

IDT39C03A/IDT39C03B FOUR·BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03B GUARANTEED MILITARY RANGE PERFORMANCE
DIVIDE INSTRUCTIONS (SFA, SFC, SFE)
TO
FROM

A. B Addr

DA.DB

Cn

18- 0

CP

Z
SIOo. SI03

G,P

Z

N

OVR

DB

WRITE

010 0 ,3

SIO

58/(46)

-

(62)/-

(55)

(54)

(23)

(57)

(42)

(62)/-

-

(57)

(46)

(42)

(62)/-

-

(23)

(56)

-

(48)

(42)

-

(53)/-

(44)

(46)

-

-

-

(46)

-

(49)

-

(49)

-

-

(49)

-

-

SLICE

Y

MSS

(56)

IS

(56)

LSS
MSS

C n +4

(23)

IS

(48)

(42)

(32)

(53)/-

-

LSS

(48)

(42)

(32)

(53)/-

-

-

MSS

(28)

30/(15)

(33)/-

(25)

(23)

IS

(28)

(15)

-

(33)/-

-

-

(57)

LSS

(28)

(15)

(33)/-

-

MSS

(57)177

72/63

-

(64)/-

(57)173

(55)173

-

(45)/63
(45)/63

(64)/-

-

-

(21)

(60)178*

(64)/-

-

-

-

-

(29)

(21)

(60)178*

(18)

(49)174

(18)

(49)

(18)

(49)

-

-

-

-

-

-

IS

(57)177

(55)/63

LSS

(57)177

(55)/63

MSS

(48)173

40/59

-

(54)/22

(44)/59

(46)/59

(18)

IS

(48)

(33)

(34)

(54)/-

-

(18)

LSS

(48)

(33)

(34)

(54)/-

MSS

-

-

-

IS

-/50

-/37

-/37

-

LSS

-/50

-/37

-/37

-

Any

(20)

-

-

-

-

-

(18)

-

-

29
(19)

-

(19)

(21)

(60)178*

-

-/52
-/52

-

NOTES:
1. A· _. means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. If two delays are given. the first is for first divide and normalization; the second is for two'S complement divide and two's complement divide
correction.
5. Double Length Normalize and First Divide Op
Two's Complement Divide
Two's Complement Divide Correction and Remainder
SFA: F=S+C n
SFC: F=A+S+Cn if Z=O
SFE: F=A+S+C n if Z=O
Y=Log.2F
F=S-A-1+C n if Z=1
F=S-A-1 +C n if Z=1
0= Log. 20
Y= Log. 2F
Y=F
SI03 = F3 €B R3(MSS)
0=Log.20
0=Log.20
Z = ~3 (MSS) from previous cycle
Cn +4 = F3 ill F2 (MSS)
SIO~ = f3W, R3(MSS)
OVA = f2ffi..!) (MSS)
Z = 3 €B 3 (MSS) from
previous cycle
Z=QOQ 1 Q 2 Q3tb F"1 ~ 1;
6. This specification is not tested but is guranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-44

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C038 GUARANTEED MILITARY RANGE PERFORMANCE
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SFS)
TO
FROM

A. BAddr

DA. DB

Cn

18- 0

CP

Z
SIOo. SI03

SLICE

Y

c,,+4

0,15

Z

N

OVR

DB

WRITE

010 0 ,3

-

-

MSS

92

76

-

39

85

85

(23)

-

IS

(56)

(46)

(42)

-

-

(23)

-

(23)

LSS

(56)

(46)

(42)

-

-

MSS

86

72

-

35

80

80

-

-

IS

(48)

(42)

(32)

-

-

-

-

-

-

28

(23)

-

-

-

-

-

SI03
100
(57)
(57)
95
(49)

LSS

(48)

(42)

(32)

MSS

29

(15)

IS

(28)

(15)

LSS

(28)

(15)

-

-

-

MSS

78

64

-

26

78

78

-

-

(21)

IS

78

64

58

-

87*

64

58

-

-

(21)

78

-

-

LSS

-

(29)

(21)

87*

-

(18)

95

(18)

(49)

(18)

(49)

-

(49)
(26)
(26)
(26)
87*

MSS

86

72

-

34

80

80

(18)

IS

(48)

(33)

(34)

-

-

-

(18)

-

-

(18)

-

-

-

-

-

-

60

-

-

-

-

-

-

60

-

LSS

(48)

(33)

(34)

-

MSS

-

-

-

IS

52

37

32

-

LSS

52

37

32

-

Any

(20)

-

-

-

-

NOTES:
1. A" - " means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct data on an
enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. SF5: F = S + Cn if Z = 0
Y3 = S3 E9 F3 (MSS)
Q = Q
F = ~ + Cn if Z = 1
Z = S3 (MSS)
N = F3 if Z ;" 0
Y = F
N = F3 E9 S3 if Z = 1
5. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-45

IDT39C03A/IDT39C03B FOUR·BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03B GUARANTEED MILITARY RANGE PERFORMANCE
SINGLE LENGTH NORMALIZATION (SFS)
TO
FROM

A, B Addr

DA,DB

Cn

18- 0

CP
SIOo, SI0 3

0,15

Z

N

OVR

DB

WRITE

-

-

-

(42)

-

(46)

(42)

-

(48)

-

-

-

IS

(48)

(42)

(32)

-

-

(23)

(46)

LSS

_(48)

(42)

.(32)

-

MSS

(28)

-

IS

(28)

(15)

SLICE

Y

MSS

(56)

IS

(56)

LSS

(56)

MSS

C n +4

LSS

(28)

(15)

MSS

(57)

38

-

-

-

-

-

-

-

26

22

22

-

-

(23)
(23)

-

-

IS

(57)

(55)

(45)

26

LSS

(57)

(55)

(45)

26

-

-

-

MSS

(48)

25

-

23

20

25

(18)

IS

(48)

(33)

(34)

23

-

(18)

LSS

(48)

(33)

(34)

23

-

Any

(20)

-

-

-

-

-

-

-

-

-

(57)

-

(57)

-

(57)
(49)

-

(49)

-

(26)

-

(26)

(49)

-

(26)

(21)

(60)*

(21)

(60)*

(21)

(60)*

-

(18)

(49)

(18)

(49)

(18)

(49)

-

-

-

-

SI0 3

(29)

-

(18)

010 0 ,3

NOTES:
1. A "-" means the delay path does not exist.

2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct data on an
enabled output.
3. An ( ) means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. SF8: F = S + C n
N = 0 3 (MSS)
Y=F
0= LOG. 20

C n + ~= 0a...Efl. 02 (MSS)

Z = 0 0 0,0 2 0 3

8-46

OVR = 02

E9

0, (MSS)

IDT39C03A/IDT39C03B FOUR-BIT
CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C03 INPUT/OUTPUT
INTERFACE CIRCUITRY
Vee
ESD
PROTECTION
OUTPUTS

IIH ' - - - - - , - - -....

INPUTS

OUTPUTS

Figure 1. Input Structure (All Inputs)

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

Figure 3. Open Drain Structure

Figure 2. Output Structure
(All Outputs)

SWITCHING WAVEFORMS
GND to 3.0V

-====]~~aE!~==~2J

Wins

INPUTS 3.0V
OV -

1.5V
1.5V
See Figure 4

CLOCK 3.0V
OV

OUTPUTS

TEST LOAD CIRCUIT
TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All other Outputs

Open

DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
Rr = Termination resistance: should be equal to Zour of the
Pulse Generator

Figure 4. Switching Test Circuits

ORDERING INFORMATION
XXXXX

X

Device Type

Process
Temperature

:
Y

' Mk

Ran

P

~----------------~

C
L

' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 39C03A

39C03B

8-47

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class 8
Plastic DIP
Sidebraze DIP
Leadless Chip Carrier
4-8it CMOS IJP Slice
High-Speed 4-Bit CMOS IJP Slice

MICROSLICE ™ PRODUCT

FEATURES:

DESCRIPTION:

• Low-power CMOS
- Commercial: 45mA (max.)

The IDT39C09/11 devices are high-speed, 4-bit address sequencers intended for controlling the sequence of microinstructions located in the microprogram memory. They are fully cascadable and can be expanded to any increment of 4 bits.
The IDT39C09s can select an address from any four sources: 1)
external direct inputs (D); 2) external data from the R inputs, stored
in an internal register; 3) a 9-word deep push-pop stack; or 4) a program counter register. Also included in the stack are additional
control functions which efficiently execute nested subroutine linkage. Each output can be ORed with an external input for conditional skip or branch instructions. A ZERO input line forces the outputs to all zeroes. All outputs are three-state and are controlled by
the OE (Output Enable) pin.
The IDT39C11s operate identically to the IDT39C09s, except
the four OR inputs are removed and the D and R inputs are tied together. They are fabricated using CEMOS ™ , CMOS technology
designed for high-performance and high-reliability. Military grade
product is manufactured in compliance with the latest revision of
MIL-STD-883, Class B, making them ideally suited to military temperature applications demanding the highest level of performance
and reliability.

- Military: 55mA (max.)
• Fast
- A version meets standard speed
- B version is 20%-50% speed upgrade
• 9-Deep stack
- Accommodates nested loops and subroutines
• Cascadable
- Infinitely expandable in 4-bit increments
• Available in 28-pin DIP and LCC (IDT39C09) and 20-pin DIP,
LCC and SOIC (IDT39C11)
• Pin-compatible, functional enhancement for all versions of the
2909/2911
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

r---------,
I
R (IDT39C09 ONLy) I
1- _ _ _ _ _ _ _ _ .J

FiE---+-..

o and R connected
on IOT39C11 only.
0 0 - 3 ---'-"---';;;'<-'

So~----~~~~--t-~~
Sl----~

r-------,

I IDT39C09 ONLY I
I {g~ ~ ---+---1---1----11--...,
I
OR 1 _-~---~-...,
IL.. _ _ _
OR 0 ---+--....,
____ J
ZERO

4

_-...1---...1--.....1--....,

CEMOS and MICROSLICE are trademarks of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

OCTOBER 1987
DSO-9003/-

8-48

IDT39C09A/B AN D IDT39C11 A/B
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IDT39C11

IDT39C09
RE

IDT39C09

CP

pUP

R3

Vee
CP

R2
R,

PUP

RE

FE

D3

Ro
OR 3

C n +4
Cn

D2
D,

D3
OR 2
D2
OR,

OE
Y3
Y2

ZERO

Yo

Y,

So

S,

D,
ORo

Yo
S,

Do
GND

So
ZERO

FE

Vee

C n +4
Cn
OE
Y3
Y2

Do
GND

Y,

LJUU;;ULJU

Ro
OR 3
D3
OR 2
D2
OR,
D,

:J 5

432U282726
25[

:l6
:J7

:J 8
:J 9
:J 10
:J "

DIP/SOIC
TOP VIEW

L28-1

FE

24[

C n +4

23[

Cn

22[

DE

2'[

Y3
Y2

20[

19[

Y,

16 17 '8

'2 13

'4 '5
nnnnnnn

001

a

a ~ a
cncn
>-

0

a:OZa:
0 g:J

o

Lee
TOP VIEW

DIP
TOP VIEW

IDT39C11
Q.

I~ J~ 2 I~

PIN DESCRIPTIONS

1'1

NAME
S,. So

I/O
I

L..I

DESCRIPTION

1'1

L......I

I

Control lines for address source selection.

D3

]4
]5

]6

FE. PUP

I

Control lines for push/pop stack.

D2
D,

RE

I

Enable line for internal address register.

Do

]7

OR I

I

Logic OR inputs on each address output line.
(IDT39C09 ONLY.)

GND

:] 8

ZERO

I

When LOW. forces output lines to zero.

OE

I

Output Enable. When OE is HIGH. the Y outputs
are OFF (high impedance).

Cn

I

Carry-in to the incrementer.

RI

I

Inputs to the internal address register.
(IDT39C09 ONLY.)

DI

I

Direct inputs to the multiplexer.

CP

I

Clock input to the AR. jlPC register and
Push-Pop stack.

YI

0

Address outputs from IDT39C09/11. (Address
inputs to control memory.)

Cn + 4

0

Carry out from the incrementer.

I

II

I.

20

19

,

3 2 U

L...I

L......I

L20-2

r
9

'0
nnnnn
" '2 '3

a ~ a
~
fficncn>->-

N

Lee
TOP VIEW

8-49

C n +4
Cn

DE
Y3
Y2

IDT39C09A/B AND IDT39C11 AlB
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

the PUP input is HIGH, the PUSH operation is enabled. The stack
pointer will then increment and the memory array is written with the
microinstruction address following the subroutine jump that initiated the PUSH. A POP operation is initiated at the end of a
microsubroutine to obtain the return address. A POP will occur
when FE and PUP are both LOW, implying a return from a subroutine. The next LOW-to-HIGH clock transition causes the stack
pointer to decrement. If the FE input is HIGH, no action is taken by
the stack pointer regardless of any other input.
The ZERO is used to force the four outputs to the binary zero
state. When LOW, all Y outputs are LOW regardless of any other
inputs (except OE). Each Youtput bit also has a separate OR input
such that a conditional logic one can be forced at each Youtput
(IOT39C09 only). This allows jumping to different microinstructions on programmed conditions.
The Output Enable (OE) input controls the Y outputs. When
HIGH, the outputs are programmed to a high impedance condition.

MICROPROGRAM SEQUENCER ARCHITECTURE
The IOT39C09/11 's architecture consists of the following segments:
- Multiplexer
- Direct Inputs
- Address Register
- Microprogram Counter
- Stack

MULTIPLEXER
The multiplexer is controlled by the So and SI inputs to select
the address source. The two inputs control the selection of the address register, direct inputs, microprogram counter or stack as the
source of the next microinstruction address.

DIRECT INPUTS
This 4-bit field of inputs (01) allows addresses from an external
source to be output on the Youtputs. On the IDT39C11s, these inputs are also used as inputs to the register.

OPERATION OF THE IDT39C09/11
Figure 1 lists the select codes for the multiplexer. The two bits
applied from the microword register (and additional combinational
logic for branching) determine which data source contains the address for the next microinstruction. The contents of the selected
source will appear on the Y outputs. Also in Figure 1 is the truth table for the output control and the push/pop stack control. So, SI,
FE and PUP operation is explained in Figure 2. All four define the
address appearing on the Y outputs and the state of the internal
registers following a clock LOW-to-HIGH transition.
The columns on the left explain the sequence of microinstructions to be executed. At address J + 2, the sequence control portion of the microinstruction contains the command· Jump
to Subroutine at A". At the time T2, this instruction is in the !J.WR and
the IOT39C09 inputs are set up to execute the jump and save the
return address. The subroutine address A is applied to the 0 inputs
from the !J.WR and appears on the Y outputs. The first instruction of
the subroutine, I (A), is accessed and is at the inputs of the !J.WR.
On the next clock tranSition, I (A) is loaded into the !J.WR for execution and the return address J + 3 is pushed onto the stack. The return instruction is executed at T5. Figure 4 is a similar timing chart
showing one subroutine linking to a second, the latter consisting of
only one microinstruction.
Figures 3 and 4 are examples of subroutine execution. The instruction being executed at any given time is the one contained in
the microword register (!J.W..£!l. The contents of the !J.WR also controls the four signals So ,SI, FE and PUP. The starting address of the
subroutine is applied to the 0 inputs of the IDT39C09 at the correct
time.

ADDRESS REGISTER
The Address Register (AR) consists of 4 Ootype, edge-triggered
flip-flops which are controlled by the Register Enable (RE) input.
With the address register enable LOW, new data will be entered
into the register on the clock LOW-to-HIGH transition. The address
register is also available as the next microinstruction address to the
multiplexer.

MICROPROGRAM COUNTER
Both devices contain a microprogram counter (!J.PC), which
consists of a 4-bit incrementer followed by a 4-bit register. The incrementer has Carry-In (C n) and Carry-Out (C n + 4) for easy and
simple cascading.
When the least significant carry-in to the incrementer is HIGH,
the microprogram register is loaded on the next clock cycle with
the current Y output word pi us one (Y + 1 -+ !J.PC). If the least significant C n is LOW, the incrementer passes the Y output word
unmodified and the microprogram register is loaded with the same
Y word on the next clock cycle (Y -+ !J.PC).

STACK
The 9-deep stack, which stores return addresses when executing microinstructions, is an input to the multiplexer. It contains a
stack pointer which always points to the last word written. The
added stack depth of 9 on the IOT39C09/11 allows for additional
microinstruction nesting.
The stack pointer is an up/down counter controlled by File End
(FE) and Push/POP (PUP) inputs. When the FE input is LOW and

8-50

IDT39C09A/B AND IDT39C11A/B
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ADDRESS SELECTION

OUTPUT CONTROL

S1

So

SOURCE FOR Y OUTPUTS

SYMBOL

OR I

ZERO

OE

L
L
H
H

L
H
L
H

Microprogram Counter
Address/Holding Register
Push-Pop Stack
Direct Inputs

J.l.PC
AR
STKO
DI

X
X
H
L

X
L
H
H

H
L
L
L

YI
Z
L
H
Source selected by So S 1

Z = High Impedance

SYNCHRONOUS STACK CONTROL
FE

PUP

H

X

No change

L

H

Increment stack pOinter, then push current PC
onto STKO

L

L

Pop stack (decrement stack pointer)

PUSH-POP STACK CHANGE

H = High
L = Low
X = Don't Care
Figure 1.

CYCLE

So. S1. FE. PUP

J.l.PC

N
N+1

L L L L

J
J + 1

K
K

-

N
N+1

L L L H

J
J + 1

K
K

-

N
N + 1

LLHX

J
J + 1

K
K

-

N
N + 1

L H L L

J
K+ 1

K
K

N
N + 1

L H L H

J
K+ 1

K
K

-

N
N + 1

LHHX

J
K+ 1

K
K

-

N
N + 1

H L L L

J
Ra + J

K
K

Ra

N
N+ 1

H L L H

J
Ra + 1

K
K

Ra

N
N + 1

H L H X

J
Ra + 1

K
K

Ra

N
N + 1

H H L L

J
D + 1

K
K

-

N
N + 1

H H L H

J
D + 1

K
K

-

N
N+ 1

H H H X

J
D + 1

K
K

-

-

-

-

REG

COMMENT

YOUT
J
J
J
K
-

K
K

Pop Stack

End Loop

Push J-IPC

Set-up Loop

Continue

Continue

Pop Stack; Use AR for Address

End Loop

Push J-IPC; Jump to Address in AR

JSRAR

Jump to Address in AR

JMPAR

Jump to Address in STKO; Pop Stack

-

PRINCIPAL USE

RTS

Jump to Address in STKO; Push J-IPC

-

Jump to Address in STKO

-

D
D

D

-

Pop Stack; Jump to Address on D

End Loop

Jump to Address on D; Push J-IPC

JSR D

Jump to Address on D

JMP D

X = Don't Care, 0 = LOW, 1 = HIGH, Assume CN = HIGH

Figure 2. Output and Internal Next-Cycle Register States for IDT39C09/11

8-51

Stack Ref (Loop)

IDT39C09A!B AND IDT39C11A/B
4·BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CONTROL MEMORY
ADDRESS

SEQUENCER
INSTRUCTION

To
T1
T2
T6
T7

J- 1
J
J + 1
J+2
J+3
J + 4

JSR A

-

-

-

-

-

T3
T4
T5

In the columns in figures 3 and 4, the sequence of microinstructions to be executed are shown. At address J + 2, the com·
mand "Jumpto Subroutine atA" is contained inthesequencecon·
trol portion of the microinstruction. At time T2 , this instruction is in
the j.lWR and the IDT39C09 inputs are set up to execute the jump
and save the return address. The subroutine address A is applied
to the 0 inputs from the j.lWR and appears on the Y outputs. The
first instruction of the subroutine, I (A), is accessed and is at the in·
puts of the j.lWR. On the next clock transition, I (A) is loaded into the
j.lWR for execution and the return address J + 3 is pushed onto the
stack. The return instruction is executed at Ts. Figure 4 shows a
similar timing chart of one subroutine linking to a second, the latter
consisting of only one microinstruction.

MICROPROGRAM

EXECUTE
CYCLE

A
A+ 1
A+2

I (A)

-

-

RTS

-

-

-

-

-

-

-

EXECUTE CYCLE
CLOCK
SIGNALS

To

-

T1

0

0

IT

H

H

PUP
0

X
X

j.lPC
STKO
STK1
STK2
STK3

IDT39C09/11
Output
ROM Output

Internal
Registers

T3

T4

Ts

T6

T7

3
L

0

0

H

H

X
X

H

X
X

X
X

2
L
L
X

J + 1

J + 2

J + 3

-

-

A+ 1
J + 3

A+2
J + 3

-

-

-

-

-

-

-

Y

J + 1

J + 2

A

A+ 1

A+2

M

I (J + 1)

JSRA

I (A)

I (A + 1)

j.lWR

I (J)

I (J + 1)

JSRA

I (A)

A

0

0

H

H

X
X

X
X

A+3
J + 3

J + 4

J + 5

-

-

-

-

J + 3

J + 4

J + 5

RTS

I (J + 3)

I (J + 4)

I (J + 5)

I (A + 1)

RTS

I (J + 3)

I (J + 4)

-

Contents of j.lWR
(Instruction
being executed)
Cn = High

Ts

T9

~ILIL IL IL IL IL IL IL IL

Sl. S0

IDT39C09/11
Inputs
(from j.lWR)

T2

Figure 3. Subroutine Execution

8-52

IDT39C09A/B AND IDT39C11A/B
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CONTROL MEMORY
MICROPROGRAM

EXECUTE
CYCLE

ADDRESS

To
T1
T2
T9

J-1
J
J + 1
J + 2
J + 3

SEQUENCER
INSTRUCTION

-

JSRA

-

-

-

-

-

-

-

-

A
A + 1
A+2
A+3
A+4

T3
T4
Ts
T7
T8

JSR B

RTS

-

-

-

-

-

T6

-

B

RTS

-

-

-

EXECUTE CYCLE

To

T1

T2

T3

T4

Ts

T6

T7

T8

T9

- i Li Li Li LrL..JrLrLrLrL ~

CLOCK
SIGNALS

X

X

3
L
H
A

j.lPC
STKO
STK1
STK2
STK3

J + 1

J + 2

J + 3

-

-

-

A + 1
J + 3

-

-

-

-

-

-

-

IDT39C09/11
Output

Y

J + 1

J + 2

A

A + 1

A+2

B

A+3

A+4

J + 3

J + 4

ROM Output

M

I(J + 1)

JSRA

I(A)

I(A + 1)

JSR B

RTS

I(A + 3)

RTS

I(J + 3)

I(J + 4)

Contents of j.lWR
(Instruction
being executed)

j.lWR

I(J)

I(J + 1)

JSRA

I (A)

I(A + 1)

JSR B

RTS

I(A + 3)

RTS

I(J + 3)

Sl.S0
IDT39C09/11
Inputs
(from j.lWR)

Internal
Registers

it
PUP
D

0
H
X

0
H
X

-

0
H
X
X

0
H
X

X

3
L
H
B

2
L
L
X

A+2
J + 3

A+3
J + 3

-

-

B + 1
A+3
J + 3

-

Cn = High
Figure 4. Two Nested Subroutines. Routine B is Only One Instruction

8-53

0
H
X

X

2
L
L
X

A+4
J + 3

A+5
J + 3

J + 4

-

-

-

-

-

0
H
X

X

-

IDT39C09A1B AND IDT39C11A/B
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C09/11 APPLICATIONS

CONTROL UNIT ARCHITECTURE

The IDT39C09 and IDT39C11 are four-bit-slice sequencers
which are cascaded to form a microprogram memory address
generator. Both products make available to the user several lines
which are used to directly control the internal holding register, multiplexer and stack. By appropriate control of these lines, the user
can implement any desired set of sequence control functions; by
cascading parts he can generate any desired address length.
These two qualities set the IDT39C09 and IDT39C11 apart from the
IDT39C10, which is architecturally similar, but is fixed at 12 bits in
length and has a fixed set of 16 sequence control instructions. The
IDT39C09 or IDT39C11 should be selected instead of the
IDT39C10 under the following conditions: (1) address less than 8
bits and not likely to be expanded; (2) address longer than 12 bits;
(3) more complex instruction set needed than is available on
IDT39C10.

The recommended architecture using the IDT39C09 or
IDT39C11 is shown in Figure 5. The path from the pipeline register
output through the next address logic, multiplexer and microprogram memory is all combinational. The pipeline register contains the current microinstruction being executed. A portion of that
microinstruction consists of a sequence control command such as
"continue", "loop", "return from subroutine", etc. The bits representing this sequence command are logically combined with bits
representing such things as test conditions and system state to
generate the required control Signals to the IDT39C09 or
IDT39C11.

IDT39C09 OR IDT39C11

I------~

~I
I

~I

OTHER BRANCH
ADDRESS SOURCE

D

R

F

PC

~I

~I

'------.--~~
VARIOUS
TEST
CONDITIONS

_ .J

ADDRESS
MICROPROGRAM MEMORY
BRANCH NEXT ADDRESS
ADDRESS
SELECT
OTHER

TEST
SYSTEM STATE

CLOCK

3-5 BITS

L...-_ _ _ _ _- - '

3

Figure 5. Recommended Computer Control Unit Architecture Using the IDT39C09A/B and IDT39C11 AlB

IDT39C09A/B AND IDT39C11 AlB
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C09/11 EXPANSION

OR inputs. In the IDT39C09, separate four-bit fields are provided
for the holding register and the direct branch inputs to the multiplexer. In the IOT39C11, these fields are internally tied together.
This may affect the design of the branch address system, as shown
in Figure 7. Using the IDT39C09, the register inputs may be connected directly to the microprogram memory; the internal register
replaces part of the pipeline register. The direct (0) inputs may be
tied to the mapping logic which translates instruction op codes into
microprogram addresses. While the same technique might be
used with the IOT39C11, it is more common to connect the
IDT39C11's D inputs to a branch address bus onto which various
sources may be enabled. Shown in Figure 7 is a pipeline register
and a mapping ROM. Other sources might also be applied to the
same bus. The internal register is used only for temporary storage
of some previous branch address.

Figure 6 shows the interconnection of three IDT39C11 s to form a
12-bit sequencer. Note that the only interconnection between
packages, other than the common clock and control lines, is the
ripple carry between J..LPC incrementors. This carry path is not in
the critical speed path if the IOT39C11 Y outputs drive the
microprogram memory, because the ripple carry occurs in parallel
with the memory access time. If, on the other hand, a microaddress
register is placed at the IDT39C11 output, then the carry may lie in
the critical speed path since the last carry-in must be stable for a
set-up time prior to the clock.

SELECTING BETWEEN THE IDT39C09 AND IDT39C11
The difference between the IDT39C09 and the IOT39C11 involves two signals: the data inputs to the holding register and the

BRANCH ADDRESS IN

~------------~----~~------------+---~~-So
Y3-0

Sl

FE
PUP
4KWORD
MICROPROGRAM
MEMORY

RE
CP

MICROINSTRUCTION

Figure 6. Twelve Bit Sequencer

D

IDT39C09

Figure 7. Branch Address Structure

8-55

IDT39C09A/B AND IDT39C11A/B
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The second difference between the IDT39C09 and IDT39C11 is
that the IDT39C09 has OR inputs available on each address output
line. These pins can be used to generate multi-way single-cycle
branches by simply typing several test conditions into the OR lines
(see Figure 8). Typically, a branch is taken to an address with zeros
in the least significant bits. These bits are replaced with 1s or Os by
test conditions applied to the OR lines. In Figure 8, the states of the
two test conditions Xand Yresult ina branch to 1100, 1101, 11100r
1111.

HOW TO PERFORM COMMON FUNCTIONS
WITH THE IDT39C09/11

x

1. CONTINUE
PUP

So

L

L

H

x

To

------+---~~~

Y

T 1 ------+---t---.

o

T2
T3

------i~

o

Contents of PC placed on Y outputs; PC incremented.

2. BRANCH
H

So

FE

PUP

H

H

x

Feed data on D inputs straight through to memory address lines.
Increment address and place in PC.

3. JUMP TO SUBROUTINE
H

So

FE

PUP

H

L

H

Yo

Subroutine address fed from D inputs to memory address.
Current PC is pushed onto stack where it is saved for the return.

Y

x

4. RETURN FROM SUBROUTINE
S1

So

H

L

PUP
L

Figure 8. Use of OR Inputs to Obtain 4-Way Branch

L

The address at the top of the stack is applied to the microprogram memory
and is incremented for PC on the next cycle. The stack is popped to
remove the return address.

8-56

IDT39C09A/B AND IDT39C11A/B
4-BIT CMOS MICROPROGRAM SEQUENCER

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TSIAS

Temperature
Under Bias

TSTG

Storage
Temperature

PT

Power Dissipation

lOUT

DC Output Current

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

o to

+70

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

1.0

1.0

W

30

30

mA

SYMBOL
CIN

(TA= +25°C, f = 1.0MHz)

PARAM ETER (1)

CONDITIONS

TYP.

VIN = OV

Input Capacitance

COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.

UNITS

5

pF

7

pF

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
TA = OoC to + 70°C

Vcc = 5.0V ±5% (Commercial)
Vcc = 5.0V ±10% (Military)

TA = -55°C to +125°C
VLC = 0.2V
VHC = Vcc -0.2V
SYMBOL

PARAMETER

TEST CONDITIONS

(1)

MIN.

TYP.(2)

MAX.

0.8

V

UNIT

VIH

Input HIGH Level

Guaranteed Logic High Level

VIL

Input LOW Level

Guaranteed Logic Low Level (4)

-

-

IIH

Input High Current

Vcc = Max., VIN = Vcc

-

0.1

5

J.lA

IlL

Input LOW Current

Vcc = Max., VIN = GND

-

-0.1

-5

J.lA

VHC

Vcc

-

VOH

Output HIGH Voltage

Vcc = Min.
VIN = 'v\H or'v\L

(4)

10H = -300J.lA
10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

4.3

-

GND

VLC

0.3

0.5

0.3

0.5

Vo = OV

-

-0.1

-10

Vo = Vcdmax.)

-

0.1

10

-30

-50

-

10L = 300J.lA
VOL

Output LOW Voltage

Vcc = Min.
VIN = 'v\H or'v\L

10L = 20m A MIL.
10L = 24mA COM'L.

loz
los

Off State (High Impedance)
Output Current
Output Short Circuit Current

Vcc = Max.
Vcc = Max., VOUT = OV(3)

2.0

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.

8-57

V

V

V

J.lA
mA

IOT39C09A/B AN D IOT39C11 AlB
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (CONT'D)
TA = OOCto +70 0 C
TA = -55°C to +125°C
VLC = 0.2V
VHC = Vcc -0.2V
SYMBOL

VCC = 5.0V±5% (Commercial)
Vcc = 5.0V ±10% (Military)

TEST CONDITIONS

PARAMETER

ICCOH

Quiescent Power Supply Current
CP = H (CMOS Inputs)

Vcc = Max.
VHC ~ VIN. VIN ~ VLC
fcp = O. CP = H

ICCOl

Quiescent Power Supply Current
CP = L (CMOS Inputs)

Vcc = Max.
VHC :$ VIN. VIN ~ VLC
fcp = O. CP = L

ICCT

Quiescent Input Power Supply(5)
Current (per Input @ TIL High)

Vcc

ICCD

Dynamic Power Supply Current

Vcc = Max.
VHC :$ VIN, \IN <;;. VLC
Outputs Open, ~ = L

IcC

Total Power Supply Current(6)

MIN.

TYP.(2)

MAX.

UNIT

-

2.5

5

mA

-

2.5

5

mA

-

0.3

0.5

mAl
Input

MIL.

-

2.0

4.0

COM'L.

-

2.0

3.0

MIL.

-

25

45

COM'L.

-

25

35

MIL.

-

35

55

COM'L.

-

35

45

(1)

= Max. VIN = 3.4V. fcp = 0

Vcc = Max., fep = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VHC ~ VIN • VIN ~ VLC
Vec = Max., fcp = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
\'IH = 3.4V, VIL = O.4V

mAl
MHz

mA

NOTES:
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCOH, then dividing by the total number of inputs.
6. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS or TIL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH(CDH) + Iccol (1 - CD H) + ICCT (NT X DH) + ICCD (fep)
CDH = Clock duty cycle high period
DH = Data duty cycle TIL high period (VIN = 3.4V)
NT = Number of dynamic inputs driven at TIL levels
fcp = Clock Input frequency

CMOS TESTING CONSIDERATIONS

3) Definition of input levels are very important. Since many inputs
may change coincidently, significant noise at the device pins
may cause the VIL and VIH levels not to be met until the noise has
settled. To allow for this testing/board induced noise, IDT recommends using Vil :5 OV and VIH :::: 3V for AC tests.

There are certain testing considerations which must be taken
Into account when testing high-speed CMOS devices in an automatic environment. These are:
1) Proper decoupling at the test head is necessary. Placement of
the capacitor set and the value of capacitors used is critical in
reducing the potential erroneous failures resulting from large
Vec current changes. Capacitor lead length must be short and
as close to the DUT power pins as possible.

4) Device grounding is extremely important for proper device testing. The use of multi-layer performance boards with radial
decoupling between power and ground planes is required. The
ground plane must be sustained from the performance board to
the DUT interface board. All unused interconnect pins must be
properly connected to the ground pin. Heavy gauge stranded
wire should be used for power wiring and twisted pairs are recommended to minimize inductance.

2) All input pins should be connected to a voltage potential during
testing. If left floating, the device may begin to oscillate causing
improper device operation and possible latchup.

8-58

-_._

..•.

_---------------------------------

IDT39C09A/B AND IDT39Cl1A/B
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE III
GUARANTEED SET-UP AND HOLD TIMES

IDT39C09B/IDT39C11 B SWITCHING
CHARACTERISTICS OVER OPERATING RANGE
Table I, II and III below define the timing characteristics of the
I DT39C09B/11 B over the operating voltage and temperature
ranges. The tables are divided into three types of parameters: clock
characteristics, combinational delays from inputs to outputs and
set-up and hold time requirements. The latter table defines the time
prior to the end of the cycle (Le., clock LOW-to-HIGH transition)
that each input must be stable to guarantee that the correct data is
written into one of the intemal registers.
Measurements are made at 1.SV with VIL = OV and VIH = 3.0V.
For three-state disable tests, C L
S.OpF and measurement is to
O.SV change on output voltage level. All outputs have maximum
DC loading.

COMMERCIAL
FROM INPUT

=

TABLE I
CYCLE TIME AND CLOCK CHARACTERISTICS
TIME

COMMERCIAL

MILITARY

Minimum Clock LOW Time

12

12

Minimum Clock HIGH Time

12

12

SET-UP HOLD
TIME
TIME

HOLD
TIME

RE

6

2

7

3

ns

RI (2)
PUP

6

2

7

3

ns

9

2

10

3

ns

FE

9

2

10

3

ns

Cn

6

2

7

3

ns

DI

8

0

9

0

ns

OR I

8

0

9

0

ns

So.~

11

0

12

0

ns

ZERO

7

0

8

0

ns

= SOpF (except output disable test)
COMMERCIAL

MILITARY
UNIT

FROM INPUT
Y

Cn + 4

Y

Cn + 4

DI

14

15

16

17

ns

So. Sl

13

15

15

17

ns

OR I

14

14

15

15

ns

Cn

-

11

-

12

ns

ZERO

14

14

15

15

ns

OE LOW (enable)

14

15

14

15

-

ns

OE HIGH (disable)(l)

-

= LH
= LL
= HL

17

17

19

19

ns

17

17

19

19

ns

17

17

19

19

ns

Clock t Sl So
Clock t Sl So
CiocktS1S0

UNIT

SET-UP
TIME

NOTES:
1. A" times relative to clock LOW-to-HIGH transition.
2. On IDT39C11. RI and DI are internally connected together and labeled
DI . Use RI set-up and hold times when D inputs are used to load
register.

TABLE II
MAXIMUM COMBINATIONAL
PROPAGATION DELAYS
CL

(1)

MILITARY

ns

NOTE:
1. C L = 5pF
tpwL
-(Tablel)-

tpwH
-(Tablel)r----------,~~~~~~~

r--------

3.0V
1.5V

CP

OV
ts
(Table "I)

tH
(Table "I)
3.0V

ALL INPUTS
(EXCEPTOE)

1.5V
OV
INPUTS TO Y OR Cn + 4
(Table II)
VOH

YOUT
C n +4

1.5V
VOL

8-59

I DT39C09A/B AN D I DT39C11 AlB
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C09A/IDT39C11 A SWITCHING
CHARACTERISTICS OVER OPERATING RANGE

TABLE III
GUARANTEED SET-UP AND HOLD TIMES

Table I, II and III below define the timing characteristics of the
IDT39C09N11A over the operating voltage and temperature
ranges. The tables are divided into three types of parameters: clock
characteristics, combinational delays from inputs to outputs and
set-up and hold time requirements. The latter table defines the time
prior to the end of the cycle (Le., clock LOW-to-HIGH transition)
that each input must be stable to guarantee that the correct data is
written into one of the internal registers.
Measurements are made at 1.5V with VIL = OV and VIH = 3.0V.
For three-state disable tests, CL = 5.0pF and measurement is to
O.5V change on output voltage level. All outputs have maximum
DC loading.

COMMERCIAL
FROM INPUT

TABLE I
CYCLE TIME AND CLOCK CHARACTERISTICS
TIME

COMMERCIAL

MILITARY

Minimum Clock LOW Time

20

20

Minimum Clock HIGH Time

20

20

HOLD
TIME

SET-UP
TIME

HOLD
TIME

RE

19

4

19

5

ns

RI (2)

10

4

12

5

ns

PUP

25

4

27

5

ns

FE

25

4

27

5

ns

Cn

18

4

18

5

ns

DI

25

0

25

0

ns

OR I

25

0

25

0

ns

So.s,

25

0

29

0

ns

ZERO

25

0

29

0

ns

register~

CL = 50pF (except output disable test)
COMMERCIAL

MILITARY
UNIT

Y

Cn +4

DI

17

So. S1

29

OR I

Y

Cn + 4

22

20

25

ns

34

29

34

ns

17

22

20

25

ns

Cn

-

14

-

16

ns

ZERO

29

34

30

35

ns

OE LOW (enable)

25

25

25

25

-

ns

OE HIGH (disable)(1)

-

t S1 So
Clock t S1 So
Clock t S1 So

= LH

39

44

45

50

ns

= LL

39

44

45

50

ns

= HL

44

49

53

58

ns

Clock

UNIT

SET-UP
TIME

NOTES:
1. All times relative to clock LOW-to-HIGH transition.
2. On IDT39C11. RI and DI are internally connected together and labeled
DI . Use RI set-up and hold times when D inputs are used to load

TABLE II
MAXIMUM COMBINATIONAL
PROPAGATION DELAYS

FROM INPUT

(1)

MILITARY

ns

NOTE:
1. C L = 5pF
tpwH
-(Tablel)3.0V
1.5V

CP

OV
ts
(Table III)

tH
(Table III)
3.0V

ALL INPUTS
(EXCEPT C5E)

1.5V
OV
INPUTS TO Y OR C n+ 4
(Table II)
VOH

YOUT

1.5V

C n +4

VOL

8-60

IDT39C09A/B AND IDT39C11A1B
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST LOAD CIRCUIT

L--o

7.0V

TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All other Outputs

Open

DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the
Pulse Generator.

Figure 9_ Switching Test Circuit (all outputs)

SWITCHING WAVEFORMS

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

INPUTS 3.0V

OV----..J./lIJ.
CLOCK 3.0V

OV
CLOCK
TO
OUTPUT I ...----~~
DELAY
OUTPUTS

INPUT/OUTPUT INTERFACE CIRCUITRY

Vec

INPUTS

O----",/\J"-~-~_I

Figure 11. Output Structure

Figure 10_ Input Structure

8-61

GND to 3.0V

Wins
1.5V
1.5V
See Figure 9

IDT39C09A/B AND IDT39C11A/B
4-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

)()()()()(

X

x

X

Device Type

Speed

Package

Process/
Temperature

:
Y

ROO

Mk

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

D
P
L
SO

CERDIP
Plastic DIP
LCC
Small Outline IC (IDT39C11 only)

A
B

Standard-Speed Sequencer
High-Speed Sequencer

39C09

4-Bit CMOS Microprogram Sequencer
4-Bit CMOS Microprogram Sequencer

' - - - - - - - - - - - - - - - - - - - lI 39C11

8-62

Commercial (O°C to

MICROSLICE ™ PRODUCT

FEATURES:

DESCRIPTION:

• Low-power CEMOS ™

The IDT39C1 0 microprogram sequencers are designed for use
in high-performance microprogram state machines. These microprogram sequencers are intended for use in controlling the sequence of microinstructions executed in the microprogram memory. The IDT39C10s provide several conditional branch instructions that allow branching to any microinstruction within the 4K
microword address space. A 33-deep last-in/first-out stack provides for a very powerful microprogram subroutine return linkage
and looping capability. With this depth of a microprogram return
stack, the microprogrammer has maximum flexibility in nesting
subroutines and loops. The counter contained in the IDT39C10s
provides for microinstruction loop counts of up to 4096, in terms of
total count length.
The IDT39C10s provide a 12-bit address to the microprogram
memory. This microprogram sequencer selects one of four
sources for the address. These are (1) the microprogram address
register, (2) external direct input, (3) internal register counter and
(4) the 33-deep LIFO stack. The microprogram counter usually
contains an address that is one greater than the microinstruction
currently being executed in the microprogram pipeline register.
The IDT39C10s are fabricated using CEMOS, a CMOS technology designed for high-performance and high-reliability. The devices are pin-compatible, performance-enhanced, functional replacements for the 2910A.
~

-Icc (max.)
Military: 90mA
Commercial: 75mA
• Fast
- IDT39C10B matches 2910A speeds
- IDT39C10C 30% speed upgrade
• 33-Deep stack
- Accommodates highly nested loops and subroutines
• 12-bit address width
• 12-bit internal loop counter
• 16 powerful microinstructions
• Three output enables control 3-way branch
• Available in 40-pin DIP and 44-pin LCC/PLCC
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87708 is pending listing on
this function. Refer to Section 2/page 2-4.

r..

FUNCTIONAL BLOCK DIAGRAM

RLD ~~--------------~

DECREMENT/
HOLD/LOAD

R=O

CI

OE r;~----~---4---+--------~

'fj
CEMOS and MICROSlICE are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-9004/-

8-63

IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
Dot indicates pin 1 for PLCC

6

PC

5

4

3

2

]7

MAP ]8

38 [

13

]9

37 [

12

] 10

36 [

Vcc

] 11

J44-1

11

] 12

L44-1

10

] 13

CCEN
CC
RLD
NC

] 14

Yo
NC
35 [
CI
34[ CP
33 [
GND
32 [
NC

&

] 15

31 [

OE

] 16

30 [

Y11

29 [

011

]17
18 19 20 21 22 23 24 25 26 27 28
""1"'""1'-'''''''''''''''''''''''''''''''''''''''
•
I
I
I
I
" , . , '"
I
I
I
'"
I
I.

I~

0<0

~ c:l >: Om . ; Om ~ J

DIP
TOP VIEW

PLCC/LCC
TOP VIEW

PIN DESCRIPTIONS
PIN NAME

01

1/0

DESCRIPTION

I

Direct input to register/counter and
multiplexer Do is LSB.

II

I

Selects one-of-sixteen instructions.

CC

I

Used as test criterion. Pass test is a
LOW on CC.

CCEN

I

Whenever the signal is HIGH, CC is
ignored and the part operates as
though CC were true (LOW).

CI

I

Low order carry inputto incrementer
for microprogram counter.

RLD

I

When LOW forces loading of register/counter regardless of instruction
or condition.

OE

I

Three-state control of YI outputs.

CP

I

Triggers all internal state changes at
LOW-to-HIGH edge.

YI

0

Yo is LSB, Yl1

FuIT

0

Indicates that 33 items are on the
stack.

PC

0

Can select #1 source (usually Pipeline Register) as direct input source.

MAP

0

Can select #2 source (usually Mapping PROM or PLA) as direct input
source.

VECT

0

Can select #3 source (for example,
Interrupt Starting Address) as direct
input source.

Address to microprogram memory.
is MSB.

8-64

-!

IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRODUCT DESCRIPTION

an empty stack may place unknown data on the Youtputs, but the
stack pointer is designed not to end around. Thus, the stack pointer
will remain at the 0 or stack empty location if a pop is executed
while the stack is already empty.
The IDT39C10s' internal 12-bit register/counter is used during
microinstructions eight, nine and fifteen. During these instructions,
the 12-bit counter acts as a down counter and the terminal count
(count = 0) is used by the internal instruction PLA as an input to
control the microinstruction branch test capability. The design of
the internal counter is such that, if it is preloaded with a number N
and then this counter is used in a microprogram loop, the actual
sequence inthe loopwill be executed N + 1 times. Thus, it ispossible to load the counter with a count of 0 and this will result in the
microcode being executed one time. The 3-way branch microinstruction, Instruction 15, uses both the loop counter and the external condition code input to control the final source address from
the Y outputs of the microprogram sequencer. This 3-way branch
may result in the next address coming from the 0 inputs, the stack
or the microprogram counter.
The IDT39C1 Os provide a 12-bit address at the Y outputs that are
under control of the OE input. Thus, the outputs can be put in the
three-state mode, allowing the writable control store to be loaded
or certain types of external diagnostics to be executed.
In summary, the IDT39C10s are the most powerful microprogram sequencers currently available. They provide the deepest
staCk, the highest performance and the lowest power dissipation
for today's microprogrammed machine design.

The IDT39C10s are high-performance CMOS microprogram
sequencers that are intended for use in very high-speed microprogrammable microprocessor applications. The sequencers allow for direct control of up to 4K words of microprogram.
The heart of the microprogram sequencers is a 4-input multiplexer that is used to select one of four address sources to select
the next microprogram address. These address sources include
the register/counter, the direct input, the microprogram counter or
the stack as the source for the address of the next microinstruction.
The register/counter consists of twelve D-type flip"flops which
can contain either an address or a count. These edge-triggered
flip-flops are under the control of a common clock enable, as well
as the four microinstruction control inputs. When the load control
(RLD) is LOW, the data at the D inputs is loaded into this register on
the LOW-to-HIGH transition of the clock. The output of the register/
counter is available at the multiplexer as a possible next address
source for the microcode. Also, the terminal count output associated with the register/counter is available at the internal instruction
PLA to be used as a condition code input for some of the microinstructions. The IDT39C10s contain a microprogram counter that
usually contains the address of the next microinstruction compared to that currently being executed. The microprogram counter
actually consists of a 12-bit incrementerfollowed by a 12-bit register. The microprogram counter will increment the address coming
out of the sequencer going to the microprogram memory if the
carry-in input to this counter is HIGH; otherwise, this address will
be loaded into the microprogram counter. Normally, this carry-in
input is set to the logic HIGH state so that the incrementer will be
active. Should the carry-in input be set LOW, the same address is
loaded into the microprogram counter. This is a technique that can
be used to allow execution of the same microinstruction several
times.
There are twelve D-inputs on the IDT39C10s that go directly to
the address multiplexer. These inputs are used to provide a branch
address that can come directly from the microcode or some other
external source. The fourth input available to the multiplexer for
next address control is the 33-deep, 12-bit wide LIFO stack. The
LIFO stack provides return address linkage for subroutines and
loops. The IDT39C10s contain a built-in stack pointer that always
points to the last stack location written. This allows for stack reference operations, usually called loops, to be performed without
popping the stack.
The stack pointer internal to the IDT39C10s is actually an up/
down counter. During the execution of microinstructions one, four
and five, the PUSH operation may occur depending on the state of
the condition code input. This causes the stack pointer to be incremented by one and the stack to be written with the required return
linkage (the value contained in the microprogram counter). On the
microprogram cycle following the PUSH, this new return linkage
data that was in the microprogram counter is now at the new location pointed to by the stack pointer. Thus, any time the multiplexer
looks at the staCk, it will see this data on the top of the stack.
During five different microinstructions, a pop operation associated with the stack may occur. If the pop occurs, the stack pointer is
decremented at the next LOW-to-HIGH transition of the clock. A
pop decrements the stack pointer which is the equivalent of removing the old information from the top of the stack.
The IDT39C10s are designed so that the stack pOinter linkage
allows any sequence of pushes, pops or stack references to be
used. The depth of the stack can grow to a full 33 locations. After a
depth of 33 is reached, the FULL output goes LOW. If further
PUSHes are attempted when the stack is full, the stack information
at the top of the stack will be destroyed but the stack pointer will not
end around. It is necessary to initialize the stack pointer when
power is first turned on. This is performed by executing a RESET
instruction (Instruction 0). This sets the stack pointer to the stack
empty pOSition -the equivalent depth of zero. Similary, a pop from

IDT39C10 OPERATION
The IDT39C10s are CMOS pin-compatible implementations of
the Am2910 &2910A microprogram sequencers. The IDT39C10's
microprogram is functionally identical ex.cept that it provides a
33-deep stack to give the microprogram mer more capability in
terms of microprogram subroutines and microprogram loops. The
definition of each microprogram instruction is shown in the table of
instructions. This table shows the results of each instruction in
terms of controlling the multiplexer, which determines the Y outputs, and in controlling the signals that can be used to enable various branch address sources (PL, MAP, VECT). The operation of
the register/counter and the 33-deep stack after the next LOW-toHIGH transition of the clock are also shown. The internal multiplexer is used to select which of the internal sources is used to drive
the Y outputs. The actual value loaded into the microprogram
counter is either identical to the Y output or the Y output value is
incremented by 1 and placed in the microprogram counter. This
function is under the control of the carry input. For each of the microinstruction inputs only one of the three outputs (PL, MAP,
VECT) will be LOW. Note that this function is not determined by
any of the possible condition code inputs. These outputs can be
used to control the three-state selection of one of the sources for
the microprogram branches.
Two inputs, CC and CCEN, can be used to control the conditional instructions. These are fully defined in the table of instructions. The RLD input can be used to load the internal register/
counter at any time. When this input is LOW, the data at the 0 inputs
will be loaded into this register/counter on the LOW-to-HIGH transition of the clock. Thus, the RLD input overrides the internal hold or
decrement operations specified by the various microinstructions.
The OE input is normally LOW and is used as the three-state enable for the Y outputs. The internal stack in the IDT39C1 Os is a lastin/first-out memory that is 12-bits in width and 33 words deep. It has
a stack pointer that addresses the stack and always pOints to the
value currently on the top of the stack. When instruction 0 (RESET)
is executed, the stack pOinter is initialized to the top of the stack
which is, by definition, the stack empty condition. Thus, the contents of the top of the stack are undefined until the forced PUSH
occurs. A pop performed while the stack is empty will not change

8-65

Ell
•

I

IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

the stack pointer in any way; however, it will result in unknown data
at the Y outputs.
By definition, the stack is full any time 33 more pushes than pops
have occurred since the stack was last empty. When this happens,
the Full Flag will go LOW. This signal first goes LOW on the
microcycle after the 33 pushes occur. When this signal is LOW, no
additional pushes should be attempted or the information on the
top of the stack will be lost.

input to the 0 inputs on the microprogram sequencer. The JMAP
instruction branches to the address appearing on the 0 inputs. In
the flow diagram shown in Figure 1, we see that the branch actually
will be to the contents of microinstruction 85 and this instruction
will be executed next.

THE IDT39C10 INSTRUCTION SET

The simplest branching control available in the IDT39C10
microprogram sequencers is that of conditional jump to address.
In this instruction, the jump address is usually contained in the microinstruction pipeline register and presented to the 0 inputs. If the
test is passed, the jump is taken while, if the test fails, this instruction executes as a simple continue. In the example shown in the
flow diagram of Figure 1, we see that if the test is passed, the next
microinstruction to be executed is the content of address 25. If the
test is failed, the microcode simply continues to the contents of the
next instruction.

INSTRUCTION 3CONDITIONAL JUMP PIPELINE (CJP)

This data sheet contains a block diagram of the IDT39C10
microprogram sequencers. As can be seen, the devices are controlled by a 4-bit microinstruction word (13-10). Normally, this word
is supplied from one 4-bit field of the microinstruction word associated with the entire state machine system. These four bits provide
for the selection of one of the sixteen powerful instructions associated with selecting the address of the next microinstruction. Unused Y outputs can be left open; however, the corresponding most
significant 0 inputs should be tied to ground for smaller microwords. This is necessary to make sure the internal operation of the
counter is proper should less than 4K of microcode be implemented. As shown in the block diagram, the internal instruction
PLA uses the four instruction inputs as well as the
CCEN and
the internal counter = 0 line for controlling the sequencer. This internal instruction PLA provides all of the necessary internal control
signals to control each particular part of the microprogram sequencer. The next address at the Y outputs of the IDT39C10s can be
from one of four sources. These include the internal microprogram
counter, the last-in/first-out stack, the register/counter and the
direct inputs.
The following paragraphs will describe each instruction associated with the IDT39C1 Os. As a part of the discussion, an example of
each instruction is shown in Figure 1. The purpose of the examples
is to show microprogram flow. Thus, in each example the microinstruction currently being executed has a circle around it. That
is, this microinstruction is assumed to be the contents of the pipeline register at the output of the microprogram memory. In these
drawings, each of the dots refers to the ti me that the contents of the
microprogram memory word would be in the pipeline register and
is currently being executed.

INSTRUCTION 4PUSH/CONDITIONAL LOAD COUNTER (PUSH)

ce,

With this instruction, the counter can be conditionally loaded
during the same instruction that pushes the current value of the
microprogram counter on to the stack. Under any condition independent of the conditional testing, the microprogram counter is
pushed on to the stack. If the conditional test is passed, the counter
will be loaded with the value on the 0 inputs to the sequencer. If the
test failS, the contents of the counter will not change. The PUSH/
Conditional Load Counter instruction is used in conjunction with
the loop instruction (Instruction 13), the repeat file based on the
counter instruction (Instruction 9) or the 3-way branch instruction
(Instruction 15).

INSTRUCTION 5CONDITIONAL JUMP TO SUBROUTINE
R/PL (JSRP)

This instruction is used at power up time or at any restart sequence when the need is to reset the stack pointer and jump to the
very first address in microprogram memory. The Jump 0 instruction does not change the contents of the register/counter.

Subroutines may be called by a Conditional Jump Subroutine
from the internal register or from the external pipeline register. In
this instruction the contents of the microprogram counter are
pushed on the stack and the branch address for the subroutine call
will be taken from either the internal register/counter orthe external
pipeline register presented to the 0 inputs. If the conditional test is
passed, the subroutine address will be taken from the pipeline register. If the conditional test fails, the branch address is taken from
the internal register/counter. An example of this is shown in the flow
diagram of Figure 1.

INSTRUCTION 1 CONDITIONAL JUMP TO SUBROUTINE (CJS)

INSTRUCTION 6CONDITIONAL JUMP VECTOR (CJV)

The Conditional Jump to Subroutine instruction is the one used
to call microprogram subroutines. The subroutine address will be
contained in the pipeline register and presented at the 0 inputs. If
the condition code test is passed, a branch is taken to the subroutine. Referring to the flow diagram for the IDT39C1 Os shown in Figure 1, we see that the content of the microprogram counter is 68.
This value is pushed onto the stack and the top of stack pointer is
incremented. If the test is failed, this Conditional Jump to Subroutine instruction behaves as a simple continue. That is, the content
of microinstruction address 68 is executed next.

The Conditional Jump Vector instruction is similar to the Jump
Map instruction in that it allows a branch operation to a microinstruction as defined from some external source, except that it is
conditional. The Jump Map instruction is unconditional. If the conditional test is passed, the branch is taken to the new address on
the 0 inputs. If the conditional test is failed, no branch is taken but
rather the microcode simply continues to the next sequential microinstruction. When this instruction is executed, the VECT output
is LOW unconditionally. Thus, an external 12-bit field can be enabled on to the 0 inputs of the microprogram sequencer.

INSTRUCTION 2JUMP MAP (JMAP)

INSTRUCTION 7CONDITIONAL JUMP R/PL (JRP)

This sequencer instruction can be used to start different
microprogram routines based on the machine instruction opcode.
This is typically accomplished by using a mapping PROM as an

The Conditional Jump register/counter or external pipeline register always causes a branch in microcode. This jump will be to one
of two different locations in the microcode address space. If the test

INSTRUCTION 0JUMP 0 (JZ)

8-66

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER

INSTRUCTION 12LOAD COUNTER AND CONTINUE (LDCT)

is passed, the jump will be to the address presented on the D inputs
to the microprogram sequencer. If the conditional test fails, the
branch will be to the address contained in the internal register/
counter.

The Load Counter and Continue instruction is used to place a
value on the D inputs in the regisler/counter and continue to the
next microinstruction.

INSTRUCTION 8REPEAT LOOP COUNTER NOT EQUAL TO 0
(RFCT)

INSTRUCTION 13TEST END OF LOOP (LOOP)

This instruction utilizes the loop counter and the stack to implement microprogrammed loops. The start address for the loop
would be initialized by using the PUSH/Conditional Load Counter
instruction. Then, when the repeat loop instruction is executed, if
the counter is not equal to 0, the next microword address will be
taken from the stack. This will cause a loop to be executed as
shown in the Figure 1 flow diagram. Each time the microcode sequence goes around the loop, the counter is decremented. When
the counter reaches 0, the stack will be popped and the microinstruction address will be taken from the microprogram counter.
This instruction performs a timed wait or allows a single sequence
to be executed the desired number of times. Remember, the actual
number of loops performed is equal to the value in the counter plus

The Test End of Loop instruction is used as a last instruction in a
loop associated with the stack. During this instruction, if the conditional test input is fail ed, the loop branch address will be that on the
stack. Since we may go around the loop a number of times, the
stack is not popped. If the conditional test input is passed, then the
loop is terminated and the stack is popped. Notice that the loop instruction requires a PUSH to be performed at the instruction immediately prior to the loop return address. This is necessary so as to
have the correct address on the stack before the loop operation. It
is forthis reason that the stack pointer always points to the last thing
written on the stack.

INSTRUCTION 14CONTINUE (CONT)

1.

INSTRUCTION 9REPEAT PIPELINE COUNTER NOT EQUAL TO 0
(RPCT)

Continue is a simple instruction where the address for the microinstruction is taken from the microprogram counter. This instruction simply causes sequential program flow to the next microinstruction in microcode memory.

This instruction is another technique for implementing a loop
using the counter. Here, the branch address for the loop is contained in the pipeline register. This instruction does not use the
stack in any way as a part of its implementation. As long as the
counter is not equal to 0, the next microword address will be taken
from the D inputs of the microprogram sequencer. When the
counter reaches 0, the internal multiplexer will select the address
source from the microprogram counter, thus causing the
microcode to continue on and leave the loop.

INSTRUCTION 15WAY BRANCH (TWB)

TH~EE

The Three-Way Branch instruction is used for looping while
waiting for a conditional event to come true. If the event does not
come true after some number of microinstructions, then a branch is
taken to another microprogram sequence. This is depicted in Figure 1 showing the IDT39C1 O's flow diagram and is also described
in full detail in the IDT39C10's instruction operational summary.
Operation of the instruction is such that any time the external conditional test input is passed, the next microinstruction will be that
associated with the program counter and the loop will be left. The
stack is also popped. Thus, the external test input overrides the
other possibilities. Should the external conditional test input not be
true, the rest of the operation is controlled by the internal counter. If
the counter is not equal to 0, the loop is taken by selecting the address on the top of the stack as the address out of the Y outputs of
the IDT39C10s. In addition, the counter is decremented. Should
the external conditional test input be failed and the counter also
have counted to 0, this instruction "times out". The result is that the
stack is popped and a branch is taken to the address presented to
the D inputs of the IDT39C10 microprogram sequencers. This address is usually provided by the external pipeline register.

INSTRUCTION 10CONDITIONAL RETURN (CRTN)
The Conditional Return instruction is used for terminating subroutines. The fact that it is conditional allows the subroutine either
to be ended or to continue. If the conditional test is passed, the
address of the next microinstruction will be taken from the stack
and it will be popped. If the conditional test failS, the next microinstruction address will come from the internal microprogram
counter. This is depicted in the flow diagram of Figure 1.1t is important to remember that every subroutine call must somewhere be
followed by a return from subroutine call in order to have an equal
number of pushes and pops on the stack.

INSTRUCTION 11 CONDITIONAL JUMP PIPELINE AND POP (CJPP)

CONDITIONAL TEST

The Conditional Jump Pipeline and Pop instruction is a technique for exiting a loop from within the middle of the loop. This is
depicted fully in the flow diagram for the IDT39C10s as shown in
Figure 1. The conditional test input for this instruction results in a
branch being taken if the test is passed. The address selected will
be that on the D inputs to the microprogram sequencer and, since
the loop is being terminated, the stack will be popped. Should the
test be failed on the conditional test inputs,the microprogram will
simply continue to the next address as taken from the
microprogram counter. The stack will not be affected if the conditional test input is failed.

Throughout this discussion we have talked about microcode
passing the conditional test. There are actually two inRuts associated with the conditional test input. These include the CCEN and
the CC inputs. The CCEN input is a condition code enable. Whenever the CCEN input is HIGH, the CC input is ignored and the device operates as though the CC input were true (LO'l"{). Thus, a fail
of the external test condition can be defined as CCEN equals LOW
and CC equals HIGH. A pass condition is defined as a CCEN equal
to HIGH or a CC equal to LOW. It is important to recognize the full
function of the condition code enable and the condition code inputs in order to understand when the test is passed or failed.

8-67

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C10B!C 12·BIT CMOS MICROPROGRAM SEQUENCER

IDT39C10 INSTRUCTION OPERATIONAL SUMMARY
COUNTER
CC
STACK
13 -1 0
MNEMONIC
TEST
CLEAR
JZ
X
X
0
PASS
PUSH
X
CJS
1
NC
FAIL
X
NC
JMAP
X
X
2
PASS
NC
X
3
CJP
FAIL
NC
X
PASS
X
PUSH
4
PUSH
FAIL
X
PUSH
PASS
PUSH
X
5
JSRP
FAIL
X
PUSH
PASS
NC
X
CJV
6
FAIL
NC
X
PASS
NC
X
7
JRP
NC
FAIL
X
POP
X
=0
8
RFCT
NOT = 0
NC
X
=0
NC
X
9
RPCT
NOT = 0
NC
X
PASS
X
POP
10
CRTN
NC
FAIL
X
PASS
X
POP
CJPP
11
NC
FAIL
X
LDCT
X
X
NC
12
PASS
X
POP
13
LOOP
NC
FAIL
X
14
CONT
X
X
NC
PASS
=0
POP
PASS
NOT = 0
POP
15
TWB
FAIL
=0
POP
FAIL
NOT = 0
NC
NC = No Change; DEC = Decrement

8-68

ADDRESS
SOURCE
0

D
PC
D
D
PC
PC
PC
D
R
D
PC
D
R
PC
STACK
PC
D
STACK
PC
D
PC
PC
PC
STACK
PC
PC
PC
D
STACK

REGISTER!
COUNTER
NC
NC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
NC
NC
NC
NC
DEC
NC
DEC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
DEC
NC
DEC

ENABLE
SELECT
PL
PL
'PI:
MAP
'PI:
PI
PL
'PI:
PL
PC
VECT

VECT
'PI:
PI
PL
'PI:
PC
PC
PL
PI
'PI:

PC

PL
PI
PI
'PI:
PL
PC
'PI:
PI

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER

FIGURE 1. IDT39C10B FLOW DIAGRAMS

o Jump Zero (JZ)

2 Jump Map (JMAP)

1 Cond JSB PL (CJS)

~~~8

3 Cond Jump PL (CJP) .

4 Push/Cond LD CNTR (PUSH)

6665~8

65h
66
67 •
68
69

67
68

25
26

8 Repeat Loop. CNTR

65

66
67

N

20
21

(PUSH)

REGISTER/
COUNTER

11 Cond Jump PL & POP (CJPP)
STACK
66 (PUSH)

66
67 (e}--+-----t-.40
68
41
69
42
70
71
14 Continue (CONT)

65t

66 •
67
68

9 Repeat PL. CNTR

~

30
31

0 (RPCT)

10 Cond Return (CRTN)

STACK

68
69 •
70

65

30
31
32
33
34

67
6 •

0 (RFCT)

~
66

REGISTER/
COUNTER

5

35
36

~

A

5 Cond JSB R/PL (JSRP)

STACK

66

65h
66
67 •
68
69

N

7 Cond JUMP R/PL (JRP)

6 Cond Jump Vector (CJV)

66
65L,
67
85
68
86

STACK
40
41
42
43

67
68
69
70

65
66

~N

COUNTER
(LDCT)

65

67
68

66
67
68
69
70

12 LD CNTR & Continue (LDCT)

65rCOUNTER
66 •
67
68

15 Three-Way Branch (TWB)

7

65
66
67
68
69

~
N

72
73

8-69

STACK'
(PUSH)
REGISTER/
COUNTER

30
31
32
33
34
35
36
37

13 Test End Loop (LOOP)

66

65

67
68
69
70
71
72

STACK
(PUSH)

IDT39C10B!C 12-BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C10 INSTRUCTIONS
13- 10 MNEMONIC

REG!
CNTR
CONTENTS

NAME

PASS

FAIL

CCEN

= LOW and CC = HIGH

Y

STACK

CCEN

= HIGH or CC = LOW

Y

STACK

REG!
CNTR

ENABLE

0

JZ

Jump Zero

X

0

CLEAR

0

CLEAR

HOLD

PL

1

CJS

Cond JSB PL

X

PC

HOLD

D

PUSH

HOLD

PC

2

JMAP

Jump Map

X

D

HOLD

D

HOLD

HOLD

MAP

3

CJP

Cond Jump PL

X

PC

HOLD

D

HOLD

HOLD

PL

4

PUSH

PUSH!Cond Ld Cntr

X

PC

PUSH

PC

PUSH

Note 1

PL

5

JSRP

Cond JSB R/PL

X

R

PUSH

D

PUSH

HOLD

PL

6

CJV

Cond Jump Vector

X

PC

HOLD

D

HOLD

HOLD

VECT

7

JRP

Cond Jump R/PL

X

R

HOLD

F

HOLD

DEC

PC

*0

F

HOLD

F

HOLD

DEC

PL

=0

PC

POP

PC

POP

HOLD

PC

8

9

RFCT

RPCT

Repeat Loop, CNTR * 0

Repeat PL, CNTR * 0 .

*0

D

HOLD

D

HOLD

DEC

PL

=0

PC

HOLD

PC

HOLD

HOLD

PI

10

CRTN

Cond RTN

X

PC

HOLD

F

POP

HOLD

PL

11

CJPP

Cond Jump PL & POP

X

PC

HOLD

D

POP

HOLD

PI

12

LDCT

LD Contr & Continue

X

PC

HOLD

PC

HOLD

LOAD

PL

13

LOOP

Test End Loop

X

F

HOLD

PC

POP

HOLD

PI

14

CONT

Continue

15

lWB

Three-Way Branch

X

PC

HOLD

PC

HOLD

HOLD

PL

*0

F

HOLD

PC

POP

DEC

PI

=0

D

POP

PC

POP

HOLD

PC

NOTE:
1. If CCEN = LOW and CC = HIGH, hold; else load. X = Don't Care

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

-0.5 to +7.0

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

SYMBOL
CIN

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TS1AS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

30

30

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance

CONDITIONS
V1N = OV

COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

8-70

TYP.

UNIT

5

pF

7

pF

IDT39C10B/C 12·BIT CMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
TA = OOC to + 70°C
TA = -55°C to +125°C
VLC = 0.2V
VHC = Vcc -0.2V
SYMBOL

Vcc = 5.0V ± 5% (Commercial)
Vcc = 5.0V ±10% (Military)

TEST CONDITIONS

PARAMETER

(1)

MIN.

TYP.(2)

MAX.

-

-

V

0.8

V

UNIT

VIH

Input HIGH Level

Guaranteed Logic High Level (4)

2.0

VIL

Input LOW Level

Guaranteed Logic Low Level (4)

IIH

Input High Current

Vcc

0.1

5

jlA

IlL

Input LOW Current

Vcc

-

-0.1

-5

JlA

IOH

VHC

Vcc

VOH

Output HIGH Voltage

IOH

2.4

4.3

V

2.4

4.3

-

-

GND

VLC

0.3

0.5

0.3

0.5

VOL

Output LOW Voltage

Vcc
ViN

= Max., '-"N = Vcc
= Max., ViN = GND

\IN

= Min.
= ViH or \lL

Vcc

= -300jlA
= -12mA MIL.
IOH = -15mA COM'L.
10L = 300JlA
IOL = 20mA MIL.
10L = 24mA COM'L.
Vo = OV
Vo = Vcc (max.)

= Min.
= ViH or \lL

loz

Off State (High Impedance)
Output Current

Vcc

= Max.

los

Output Short Circuit Current

Vcc

= Min., VOLrr = OV (3)

ICCOH

Quiescent Power Supply Current
CP = H

Vcc = Max.
VHC ~ '-"H ' \lL ~ VLC
fcp = 0, CP = H

ICCOL

Quiescent Power Supply Current
CP = L

Vcc = Max.
VHC ~ VIH , V IL ~ VLC
fcp = 0, CP = L

ICCT

Quiescent Input Power Supply (5)
C~rrent (per Input @TTL High)

Vcc

ICCD

Dynamic Power Supply Current

Vcc = Max.
VHc ~ VIH , VIL ~ VLC
Outputs Open, ITE = L

ICC

Total Power Supply Current (6)

-0.1

-10

-

0.1

10

-30

-

-

rnA

-

35

50

rnA

-

35

50

rnA

-

0.3

0.5

mN

MIL.

-

1.0

3.0

COM'L.

-

1.0

1.5

MIL.

-

45

80

COM'L.

-

45

65

MIL.

-

50

90

COM'L.

-

50

75

= Max. VIH = 3.4V, fcp = 0

Vcc = Max., fcp = 10MHz
Outputs Open, ITE = L
CP = 50% Duty cycle
VHC ~ VIH ' \lL ~ VLC
Vcc = Max., fcp = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
ViH = 3.4V, VIL = O.4V

V

JlA

Input

mN

MHz

rnA

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at'tc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out IccoH, then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:

CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period (VIN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock Input frequency

8-71

IDT39C10B/C 12-BITCMOS MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CMOS TESTING CONSIDERATIONS

2) All input pins should be connected to a voltage potential during
testing. If left floating, the device may begin to oscillate causing
improper device operation and possible latchup.

3) Definition of input levels is very important. Since many inputs
may change coincidentally, significant noise at the device pins
may cause the VIL and \lJH levels not to be met until the noise has
settied. To allow for this testing/board induced noise, lOT recommends using "'L~ OV and "'H~ 3V for AC tests.
4) Device grounding is extremely important for proper device testing. The use of multi-layer performance boards with radial
decoupling between power and ground planes is required. The
ground plane must be sustained from the performance board to
the OUT interface board. All unused interconnect pins must be
properly connected to the ground pin. Heavy gauge stranded
wire should be used for power wiring and twisted pairs are recommended to minimize inductance.

IDT39C10C AC ELECTRICAL CHARACTERISTICS

IDT39C1 OB AC ELECTRICAL CHARACTERISTICS

I. SET-UP AND HOLD TIMES

I. SET-UP AND HOLD TIMES

There are certain testing considerations which must be taken
into account when testing high-speed CMOS devices in an automatic environment. These are:
1) Proper decoupling at the test head is necessary. Placement of
the capacitor set and the value of capacitors used is critical in
reducing the potential erroneous failures resulting from large
Vee current changes. Capacitor lead length must be short and
as close to the DUT power pins as possible.

t(h)

tIs)

INPUTS
COM'L.

MIL.

COM'L.

UNIT

MIL.

t(h)

tIs)

INPUTS

MIL

COM'L.

COM'L.

UNIT

MIL.

01-+ R

6

7

0

0

ns

01-+ R

16

16

0

0

ns

01 -+ PC

13

15

0

0

ns

01 -+ PC

30

30

0

0

ns

10-3

23

25

0

0

ns

10-3

35

38

0

0

ns

CC

15

18

0

0

ns

CC

24

35

0

0

ns

CCEN

15

18

0

0

ns

CCEN

24

35

0

0

ns

CI

6

7

0

0

ns

CI

18

18

0

0

ns

RLD

11

12

0

0

ns

RLD

19

20

0

0

ns

II. COMBINATIONAL DELAYS
Y

INPUTS
COM'L.
12

II. COMBINATIONAL DELAYS
FULL

PL, VECT, MAP
MIL. COM'L.
15

MIL. COM'L.

-

-

10- 3

20

25

13

15

-

CC

16

20

-

-

CCEN

16

20

-

CP
OE(l)

28

33

10/10

13/13

-

-

0 0- 11

UNIT

PL, VECT, MAP

Y

INPUTS

MIL.

COM'L.
20

MIL. COM'L.
25

FULL

MIL. COM'L.

ns

0 0 -11

-

-

-

ns

10- 3

35

40

30

35

ns

CC

30

36

-

ns

CCEN

30

36

CP
OE(l)

40

46

-

-

-

-

-

22

25

ns

-

-

ns

-

MIL.

UNIT
ns

-

-

31

35

ns

ns
ns
ns

NOTE:
1. Enable/Disable. Disable times measure to 0.5V change on output voltage level with CL = 5pF.

25/27 25/30
ns
NOTE:
1. Enable/Disable. Disable times measure to 0.5V change on output voltage leve! with CL = 5pF.

III. CLOCK REQUIREMENTS

III CLOCK REQUIREMENTS

COM'L

MIL

UNIT

COM'L

MIL

UNIT

Minimum clock LOW time

18

20

ns

Minimum clock LOW time

20

25

ns

Minimum clock HIGH time

17

20

ns

Minimum clock HIGH time

20

25

ns

Minimum clock period

35

40

ns

Minimum clock period

50

51

ns

8-72

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C10B/C 12-BIT CMOS MICROPROGRAM SEQUENCER

AC TEST CONDITIONS·
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

IDT39C10B INPUT/OUTPUT
INTERFACE CIRCUIT

GND to 3.0V

WIns
1.5V
1.5V
See Figure 3

Vcc

OUTPUTS

INPUTS Q--.-J'V'v"v--+--I

Figure 1. Input Structure

Figure 2. Output Structure

TEST LOAD CIRCUIT

TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All other Outputs

Open

DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to ZOLrr of the
Pulse Generator

Figure 3. Switching Test Circuits

ORDERING INFORMATION
IDT

39C10
Device Type

X

X

x

Speed

Package

Process/
Temperature
Range

------il :',"k

, - - - - I

.................................................................

~

~

P
C

D

J
L

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
Plastic DIP
Sidebraze DIP
CERDIP
PLCC
LCC
Fast 12-Bit Microprogram Sequencer
Ultra-fast 12·Bit Microprogram Sequencer

8-73

(;II
I

•

MICROSLICE™ PRODUCT

FEATURES:

DESCRIPTION:
The IDT39C203s are four-bit expandable, high-performance
CMOS microprocessor slices. Along with the standard features associated with the IDT39C01s and IDT39C03s, the lOT 39C203s
also incorporate additional enhancements for arithmetic-oriented
processors.
These extremely low-power yet high-speed three-port three-address architectured microprocessors consist of a 16-word by 4-bit
dual-port RAM with latches on both outputs, high-performance
ALU and shifter, a flexible Q register with shifter input, and nine-bit
instruction decoder. Additionally, special instructions which allow
the easy implementation of multiplication, division, normalization,
BCD arithmetic and conversion are standard on the IDT39C203s.
Both devices are easily expandable in 4-bit increments.
They are pin-compatible, functional replacements for all versions of the 29203. The fastest version, the lOT 39C203A, is a 20%
speed upgrade from the normal 29203 device. The IDT39C203
. meets the 29203 speeds.
The IDT39C203s are fabricated using CEMOS TM , CMOS technology designed for high-performance and high-reliability.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• Fast
- IDT39C203 matches 29203 speeds
- IDT39C203A 20% speed upgrade
• Low-power CMOS
- Military: 55mA (max.)
- Commercial: 50mA (max.)
• Pin-compatible, performance-enhanced functional
replacement for the 29203
• Cascadable to 8, 12, 16, etc. bits
• Infinitely expandable register file
• Improved I/O capability
- DA, DB and Y ports are bidirectional
• Performs BCD arithmetic
- Features automatic BCD add, subtract and conversion
between binary and BCD
• On-chip parity generation and sign extension logic
• On-chip normalization logic
• On-Chip multiplication division logic
• Packaged in 48-pin plastic and sidebraze DIP, 52-pin LCC
• Military product available compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
4

4
80-3

~

TEN
CJl:s

D8 0- 3

Cn
SIOo
SI03

101--+------1

alD.3 1C1--~~---==t=:::::::::=~

.

....---..~.....

alOo

10_8~.·•

[SS

PLA.

WRiIT/MSS

•

CJl:yC>----~-~

z

TENz
CEMOS and MICROSLICE are trademarks of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-9006/-

1987 Integrated DevIce Technology. Inc.

8-74

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

Q~

QID.J
B3
B2
Bl
Bo
CP
10

DAo
DAI
DA2
DA3
12
13
14
Cn
C n +4

MILITARY AND COMMERCIAL TEMPERATURE RANGES

INDEX
WL.:UUULJiiL.:UUL.:LJLJ

7

II

WRlTE"/~

LSS
TI:N
WE

PIOVR
GND

Vee
15
16
17
18

GIN

OE"y
Yo
Yl
Y2
Y3
SIO o
SI03

Z
DBo
DBI

:Ja

13

]9

14

:1
:1

Cn

6 5 4

3

2

U

52 51 50 49 48 47

1

10

C n +4

11
] 12

P/OVR

] 13

GND

] 14

GIN

:1 15

L52-1

Yo
Yl
Y2
NC

NC

45 [
44 [:
43 [

10

11
wmIT/1V1S"S

42 [

[SS

41 [
40 [:

TEN
WE

39 [:
38 [

Vee
15

37 [:

16

:118
:1 19
]20

36 [:
35 [

17
18

34 [:

O'E"B

21 22 23 24 25 26 27 28 29 30 31 32 33

nnnnnnnnnnnnn

DIP
TOP VIEW
LCC
TOP VIEW

8-75

46 [

16
]17

O'E"y :1

OE"B
Ao
Al
A2
A3
DB2
DB3

12

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-81T CMOS MICROPROCESSOR SLICE

PIN DESCRIPTION
PIN NAME

DESCRIPTION

I/O

Ao - A3

I

Four address inputs to the RAM containing the address of the RAM word appearing at output port A.

Bo - B3

I

Four address inputs to the RAM which selects one of the words in the RAM. the contents of which is displayed through
the B port. It also selects the location into which new data can be written when the WE input and CP input are low.

DA o-3

I/O

Four-bit bidirectional data pins for entering external data into the ALU. The DA lines act as either RAM port A output data
or as input operand R to the ALU.

DBo-3

I/O

Four-bit bidirectional data pins for entering external data into the ALU. The DB lines act as either RAM port B output
data or as input operand S to the ALU.

WE

I

The RAM write enable input which. when LOW. causes the Y I/O port data to be written into the RAM when the CP input
is low. When WE is HIGH. writing data into the RAM is inhibited.

EA

I

Enable input which. when HIGH. selects DA o_3 as the ALU R operand and. when LOW. selects RAM output A as the ALU R
operand and the DA o_3 output data.

OE B

I

Output enable. which. when HIGH selects DB o- 3 as the ALU S operand. and. when LOW. selects RAM output B as the
ALU S operand and the DB o_3 output data.

SIO o. - SI0 3

I/O

Bidirectional serial shift inputs/outputs for the ALU shifter. SIO o is an input SI03 an output during a shift-up operation.
SI03 is an input and SIO o an output during a shift-down operation. Refer to Tables 3 and 4 for an exact definition of
of these pins.

0100. - 0103

I/O

Bidirectional serial shift inputs/outputs for the ALU shifter. They operate like the SIO o and SI0 3 pins. Refer to Tables 3
and 4 for an exact definition of these pins.

Cn

I

Carry-in input to the ALU.

lEN

I

Instruction enable input. When LOW. it enables writing into the 0 register and the Sign Compar~-flop and RAM.
When HIGH. the 0 register and the Sign Compare flip-flop are in hold mode. On the IDT39C203. EIN does not affect WRITE
but internally disables the RAM write enable.

LSS

I

Input pin. when held LOW. ~ the chip to act as the Least Significant Slice (LSS) of an IDT39C203 array and enables
the WRITE output onto the WRITE/M$S pin. When LSS is held HIGH. the chip acts as either an Intermediate or Most
Significant Slice (MSS) and the WRITE output buffer is disabled.

I/O

The write output Signal appears atthis pin when LSS is held LOW. When an instruction which causes data to be written into the
RAM is being executed. the WRITE signal is LOW. When LSS is HIGH. WRITE/MSS is an input pin; holding it HIGH programs
the chip to operate as an Intermediate Slice (IS) and holding it LOW programs the chip to operate as the Most Significant
Slice (MSS).

WRITE/MSS

Cn+ 4
Z

0
I/O

This output indicates the carry-out of the ALU. Refer to Table 5 for an exact definition of this pin.
An open collector inpuVout pin. When HIGH. it indicates that all outputs are LOW. Z is used as an input pin for some special
functions. Refer to Table 5 for an exact definition of this pin.

G/N

0

OEy

I

A control input pin. When LOW the ALU shifter output data is enabled onto the YO- 3 lines. When HIGH the YO- 3 three-state
output buffers are disabled.

CP

I

Clock input to the IDT39C203. The §Ian Compare flip-flop and the 0 register are clocked on the LOW-to-HIGH transition
of the CP signal. When enabled by WE and CP is LOW. data is written in the RAM.

0

P indicates the carry propagate function at the Least Significant and Intermediate slices and indicates the conventional two's
complement overflow (OVR) signal at the Most Significant Slice. Refer to Table 5 for an exact definition of this pin.

YO- 3

I/O

Four data inputs/outputs of the IDT39C203. Controlled by the OEy input. the ALU shifter output data can be enabled onto
these lines or external data is written directly into the RAM using these lines as data inputs.

10- 8

I

P/OVR

G indicates the carry generate function at the Least Significant and Intermediate slices and indicates the sign (N) of the
ALU result at the Most Significant Slice. Refer to Table 5 for an exact definition of this pin.

The nine instruction inputs used to select the IDT39C203 operation to be performed.

8-76

IDT39C203/A 4-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES
signals that are necessary in a cascaded system are available as
outputs on the IDT39C203 Least Significant and Intermediate
slices.
The IDT39C203 provides a carry-out signal· (Cn+4) which is
available as an output of each slice. the carry-in (Cn) and carry-out
(Cn+4) are both active HIGH. Two other status outputs are generated by the ALU. These are the negative (N) and the overflow
(OVR). The N output indicates positive or negative results. while
the OVR output indicates that the arithmetic operation performed
exceeded the available two's complement range. Thus. the pins
G/ Nand P/OVR indicate carry generate or propagate on the Least
Significant and Intermediate slices and sign and overflow on the
Most Significant Slice. Refer to Table 5 for an exact definition of
these four signals.

DEVICE ARCHITECTURE
The IDT39C203 is a CMOS high-performance 4-bit microprocessor slice cascadable to any number of bits (8. 12. 16. etc.). Its
versatile microinstructions allow emulation of virtually any digital
computer. The ALU sources. function and destination can be
selected by the 9-bit microinstruction set. Key elements which
make up this 4-bit microprocessor slice are: (1) the RAM file (a 16x4
dual-port RAM) with latches on both outputs. (2) high-performance
ALU with shifter. (3) a flexible Q register with shifter input and (4) a
nine-bit instruction decoder.

RAM FILE
RAM data is read from the A port as controlled by the 4-bit A address field input. Simultaneously. data can be read from the B port
as defined by the 4-bit B address field input. If the same address is
applied at both the A input field and the B input field. identical data
will appear at the two respective output ports. Data is written into
the RAM when WE and lEN are both LOW and the clock CP is
LOW. Both the RAM output data latches are transparent. while the
clock pulse CP is HIGH and latches the data when CP is low.
New data is written into the RAM word defined by the B address
field. External data at the Y I/O port can be written directly into the
RAM or ALU shifter output data can be enabled onto the Y I/O port
and written into the RAM. The three-state output enable OEBallows
RAM B port data to be read at the DB I/O port. while EA performs
the same function for the A port data the DA I/O port.

Table 2 IDT39C203 ALU Functions(l)
ALU FUNCTIONS
13
12
11
10
14

ALU
The ALU can perform seven arithmetic and nine logic operations on the two 4-bit input words Sand R. Multiplexers at the ALU
inputs allow selection of various pairs of ALU source operands.
The EA input selects either external DA data or RAM A-port output
data as the 4-bit R source operand. The 0 EB and 10 inputs provide
selection of either RAM B port output or external DB data or the
Q register output as the 4-bit S source operand. Also. during
certain ALU operations. zeros are forced at the ALU operand
inputs. Thus. the ALU can operate on data from two external
sources. from an external and an internal source or from two internal sources. Table 1 shows all possible pairs of source operands
as selected by EA. OEB and 10 inputs.

Table 1 ALU Operand Sources (1)

Special Functions

L

L

L

L

L

L

L

L

L

H

~

L

L

L

H

X

F=S-R-1+C n

= HIGH

L

L

H

L

X

F=R-S-1+C n

L

L

H

H

X

F=R+S+C n

L

H

L

L

X

F=S+C n

L

H

L

H

X

F=5+C n

L

H

H

L

L

Reserved Special Functions

L

H

H

L

H

F=R+C n

L

H

H

H

L

Reserved Special Functions

L

H

H

H

H

F=R+C n
Special Functions

L

H

H

H

L

H

L

L

L

H

FI =LOW

H

L

L

H

X

FI =Ri AND 51
FI = Ri EXCLUSIVE NOR S I

H

L

H

L

X

H

L

H

H

X

~

H

H

L

L

X

FI =Ri AND SI

=Ri EXCLUSIVE OR 51

H

H

L

H

X

H

H

H

L

X

FI =Ri NOR5 1
Ji=Ri NAND 51

H

H

H

H

X

FI =Ri OR 51

EA

10

OEB

ALU OPERAND R

ALU OPERAND S

L

L

L

Ram Output A

Ram Output B

Note:

L

L

H

Ram Output A

DBo_3

1. L= LOW, H=HIGH, i = Oto 3. X = DON'T CARE

L

H

X

Ram Output A

Q

Register

H

L

L

DAo-3

Ram Output B

ALU SHIFTER

H

L

H

DAo-3

DB o_3

H

H

X

DAo-3

Q

The ALU shifter shifts the ALU output data under instruction
control. It can shift up one bit position (2F). shift down one bit position (F/2) or pass the ALU output non-shifted (F). An arithmetic shift
operation shifts the data around the Most Significant (sign) Bit of
the Most Significant Slice and a logical shift operation shifts the
data through the Most Significant Bit. Figure 1 shows these shift '
patterns. The SIOo and SI03 are bidirectional serial shift input/output pins. During a shift-up operation. SIOo is generally an input
while SI03 is an output; whereas. during a shift-down operation,
SIOo is generally an output while SI03 acts as an input. Refer to
Tables 3 and 4 for an exact definition of these pins.
The ALU shifter also provides sign extension and parity generating/checking capabilities. Under instruction control. the SIOo
(sign) input can be extended through Yo. Y1 • Y2 • and Y3 and be
propagated to the SI03 output. A cascadable, five-bit parity
generator/checker generates parity for the Fa. F1 • F2 and F3 ALU
outputs. the SI03 input and. under instruction control. is made

Register

Note:

1. L= LOW,H=HIGH,X=DON'TCARE
The ALU performs special functions when instruction bits 13 • 12 •
11 and 10 are LOW. Table 4 defines these special functions and the
operation which the ALU performs for each. When the ALU executes instructions other than the special functions. the operation is
defined by instruction bits 14 • 13 • 12 and 11 . Table 2 defines the
operation as a function of these four instruction bits.
The IDT 39C203 may be cascaded in either a ripple carry or
lookahead carry fashion. When configured as cascaded ALUs. the
IDT39C203s must be programmed to be a Most Significant Slice
(MSS). an Intermediate Slice (IS) or a Least Significant Slice (LSS)
of the array. The carry generate (5) and carry propagate (p)

8-77

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

a REGISTER FILE

available at the SIOo output. Table 4 defines the special functions
and the operation the ALU shifter performs for each instruction. For
instructions other than the special functions, the ALU shifter
operation is determined by instruction bits 18 , 17 , 16 and 15. Table 3
defines the ALU shifter operation as a function of these four bits.

SIO,

JlJc; ; I ~

a

The register is a separate 4-bitfile intended primarily for multiplication and division routines and can also be used as an accumulator or holding register for other types of applications. The ALU
output (F) can be loaded into the register and/or the register
can be selected as one of the ALU S operands. The shifter at the
input tothe register performs only logical shifts. It can shift-upthe
data one bit position (20) or down one bit position (0/2). For a
shift-up operation, 010 0 acts as an input while 0103 acts as an output; whereas for a shift-down operation 010 0 is an output and
0103 is an input. By connecting 0103 of the Most Significant Slice
to S,IOo of the Least Significant Slice, double-length arithmetic and
logical shifting is possible with cascaded IDT39C203s.
Table 4 defines the special functions and the operations which
register and the shifter performs for selected instruction
the
inputs. While executing instructions other than the special functions, the
register and the shifter operation is controlled by
instruction bits 18 , 17 , 16 and 15 . Table 3 defines the register and
shifter operation as a function of these four bits.

a

a

SIO,

ARITHMETIC SHIFT PATH-MSS

I:::I~

a

SIO,

a

ARITHMETIC SHIFT PATH-LSS/IS

I;;;I~

a

a

SIO,

LOGICAL SHIFT PATH
ALL SLICE POSITIONS
Figure 1.

Table 3. ALU Destination Control for I oor 11 or I 20r 13 = HIGH, lEN =LOW(I)
Y3

SI0 3

ALU

Y2
WRITE

o REG&
SHIFTER 0103
FUNCTION

HEX
la 17 16 Is CODE SHIFTER MOST SIG. OTHER MOST SIG. OTHER MOST SIG. OTHER
FUNCTION
SLICE
SLICES
SLICE
SLICES
SLICES
SLICE

'1

'0

SIO o

/'MS""S

L L l

F2

Fl

Fo

l

Hold

Z

Z

Fo

l

Hold

Z

Z

Input

00

Input

00

L l

l

L H

0

Arith F!2-+Y

Input

Input

F3

SI03

SI 0 3

F3

1

log. F/2-+Y

Input

Input

SI03

SI03

F3

F3

F2

Fl

0100

L l H l

2

Arith. F!2-+Y

Input

Input

F3

SI0 3

SI0 3

F3

F2

Fl

Fo

l

Log. 0/2
-+0

L L H H

3

Log. F/2-+Y

Input

Input

SI03

SI03

F3

F3

F2

Fl

Fo

L

Log. 0/2
-+0

F3

F3

F2

F2

Fl

Fo

Parity

L

Hold

Z

Z

H

Log. 0/2
-+0

Input

00

H

F-+O

Z

Z

L H L L

4

F-+Y

Input

Input

l H L H

5

F-+Y

Input

Input

F3

F3

F2

F2

Fl

Fo

Parity

L H H L

6

F-+Y

Input

Input

F3

F3

F2

F2

Fl

Fo

Parity

Input

Input

F3

F3

~

F2

Fl

Fo

Parity

L

F-+O

Z

Z

SIO o Input

L

Hold

Z

Z

L H H H

7

F-+Y

H L L L

8

Arith . 2F-+Y

F2

F3

F3

F2

Fl

Fl

Fo

H L L H

9

Log.2F-+Y

F3

F3

F2

F2

Fl

Fl

Fo

SIO o Input

·L

Hold

Z

Z

H L H L

A

Arith. F/2-+Y

F:;:

F:;

F3

F2

Fl

Fl

Fo

SIO o Input

L

Log. 20
-+0

03

Input

H L H H

B

Log. F/2-+Y

F3

F3

F2

F2

Fl

Fl

Fo

SIO o Input

L

03

Input

H H L L

C

F-+Y

F3

F3

F3

F3

F2

F2

Fl

Fo

Z

H

Log. 20
-+0
Hold

Z

Z

H H L H

0

F-+Y

F3

F3

F3

F3

F2

F2

Fl

Fo

Z

H

Log. 20
-+0

03

Input

H HH L

E

SIOo-+Yo •
Y1 • Y2 • ~

SIO o

SIO o

SIO o

SIO o

SIO o

L

Hold

Z

Z

H H H H

F

F-+Y

F3

F3

F3

F3

F2

L

Hold

Z

Z

NOTE:
1. Parity = F3'V' F2'V'F1 'V' Fo'V'SI03 •

L = LOW

Z = High Impedance

8-78

SIO o SIO o SIO o Input
F2

Fl

Fo

'V'= Exclusive OR.

Z

H = HIGH

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

INSTRUCTION DECODER

SPECIAL FUNCTIONS

The internal control signals necessary for the operation of the
IDT39C203 are generated by the instruction decoder as a function
of the nine instruction inputs, 10-8; the instruction enable input,
lEN; the LSS input; and the MSS/WRITE inpuVoutput.
The WRITE output is LOW when an instruction which writes data
into the RAM is executed. Refer to Tables 3 and 4 for a definition
of the WRITE output as a function of the instruction inputs. When
lEN is HIGH, the WRITE output is forced HIGH and the Q re..9§ter
and Sign Compare flip-flop contents are preserved. When lEN is
LOW, the WRITE output is enabled and the Q register and Sign
Compare flip-flop can be written according to the IDT39C203s
instruction. The Sign Compare flip-flop shown in Figure 2 is an
on-chip flip-flop which is used during a divide operation.

Sixteen special functions are provided on the IDT39C203 which
permit the implementation of the following operations:
•
•
•
•

• Incrementation and decrementation by one or two
• BCD add, subtract, and divide by two
• Single and double-precision BCD-to binary and binary-te-BCD
conversion
Adjusting a Single-precision or double-precision floating-point
number in order to bring its mantissa within a specified range can
be performed using the single-length and double-length normalization operations. Three special functions can be used to perform
a two's complement, non-restoring divide operation. They provide
single and double-precision divide operations and can be performed in "n" clock cycles (where "n" is the number of bits in the
quotient).
The unsigned multiply special function and the two two's
complement multiply special functions can be used to multiply two
n-bit, unsigned or two's complement numbers, respectively, in "n"
clock cycles. During the last cycle of the two's complement
multiplication, a conditional subtraction, rather than addition, is
performed due to the fact that the sign bit of the multiplier carries
negative weight. .
The sign/magnitude two's complement special function can be
used to convert number representation systems. A number
expressed in Sign/magnitude representation can be converted to
the two's complement representation, and vice-versa, in one clock
cycle. Incrementing an unsigned or two's complement number by
one or two is easily accomplished using the increment by one or
two special functions.
In addition to BCD arithmetic special functions to add or
subtract two BCD numbers, a BCD divide by two adjust
instructions can be used to obtain a valid BCD representation after
shifting a number down by one bit. The BCD/binary conversion
special function instructions permit single and double-precision
algorithms to convert from BCD-to-binary and from binary-te-BCD.

~~

SPECIAL
FUNCTION
AORC

TEN

0

Single and double length normalization
Two's complement division
Unsigned and two's complement multiplication
Conversion between two's complement and sign/magnitude
representation

Q

~ ~'8~PARE

Figure 2. Sign Compare Flip·Flop

SLICE POSITION PROGRAMMING
Holding the LSS pin LOW programs the IDT39C203 slice (LSS)
and enables the WRITE output signal onto the MSS/WRITE I/O
pin. When LSS is tied HIGH, the MSS/WRITE pin becomes an input
tying MSS/WRITE LOW programs the slice to operate as the Most
Significant Slice (MSS); tying it HIGH causes the slice to operate as
an Intermediate Slice. The MSS/WRITE pin should be tied HIGH
through a reSistor, independent of the LSS pin.

8-79

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-81T CMOS MICROPROCESSOR SLICE

Table 4. Special Functions (7,8)
HEX
HEX
18 17 1e 15 14 13 1211 10

0

L

0

1

L

0

1

H

0

2

L

0

3

L

0

4

L

0

SPECIAL
FUNCTION
Unsigned Multiply
BCD to Binary
Conversion
Multiprecision
BCD to Binary
Two's Complement
Multiply
Decrement by
One or Two

6

L

0

Increment by
One or Two
Sign/Magnitude
Two's Complement
Two's Complement
Multiply, Last Cycle

7

L

0

BCD Divide by Two

5

L

0

8

L

0

9

L

0

9

H

0

A

L

0

B

L

C

Single Length
Normalize
Binary to BCD
Conversion
Multiprecision
Binary to BCD

SI03
ALU SHIFTER
FUNCTION
MSS OTHER
SLICES

ALU
FUNCTION

o REGISTER
SIO o & SHIFTER 010 3 0100 WRITE
FUNCTION

m-s-s

F=S+C n if Z=L
F=R+S+C n if Z=H

Log F/2-+y(1)

X

Input

Note 4

Log F/2-+Y

Input

Input

Fo

Note 4

Log F/2-+Y

Input

Input

Fo
Fo

F=S+C n if Z= L
F=R+S+C n if Z=H

Log F/2-+y(2)

X

Input

Fo

Log 0/2
-+0
Log 0/2
-+0

Input

00

L

Input

00

L

Hold

X

00

L

Log 0/2
-+0

Input

00

L

F=S-2+C n

F-+Y

Input

Input

Parity

Hold

X

X

L

F=S+1+C n

F-+Y

Input

Input

Parity

Hold

X

X

L

F=S+C n if Z=L
F=S+C n if Z=H
F=S+C n if Z= L
F=S-R-1 +Cn if Z=H

F-+y(3)

Input

Input

Parity

Hold

X

X

L

Input

00

L

X

X

L

L F/2-+y(2)
F-+Y

Note 4

X

Input

Fo

Log 0/2
-+0

Input

Input

Parity

Hold

X

Log 20
-+0
Log 20
-+0

F-+Y

F3

F3

Note 5

Log 2F-+Y

F3

F3

Input

Note 5

Log 2F-+Y

F3

F3

Input

Hold

Double Length
Normalize and
First Divide Op

F=S+C n

Log 2F-+Y

R3'V"~

F3

Input

Log 20
-+0

0

BCD Add

F = R + S + C n BCD (6)

F-+Y

0

0

X

Hold

L

0

Two's Complement
Divide

F=S+R+CnifZ=L
F=S-R-1 +C n
ifZ=H

Log 2F-+Y

R3'V"F

F3

Input

Log 20
-+0

D

L

0

BCD Subtract

F = R-S-1 + C n BCD (6)

F-+Y

0

0

X

Hold

E

L

0

Two's Complement
Divide Correction
and Remainder

F=S+R+C n if Z=L
F=S-R-1+Cn if Z= H

F-+Y

F3

F3

X

Log 20
-+0

F

L

0

BCD Subtract

F=S-R-1+C n BCD (6)

F-+Y

0

0

X

Hold

F=S+C n

0 3 Input

L

0 3 Input

L

X

Input

L

0 3 Input

L

X

L

X

0 3 Input

L

X

L

X

0 3 Input

X

X

NOTES:
1. At the Most Significant Slice only, the C n+ 4 signal is internally gated to the Y3 output.
2. At the Most Significant Slice only, F3'V" OVR is internally gated to the Y3 output.
3. At the Most Significant Slice only, S3 'V" F3 is generated the Y3 output.
4. On each slice, F = S if magnitude of S 0-3 is less than 8, and F = S minus three if magnitude of SO-3 is 8 or greater.
5. On each slice, F = S if magnitude of SO-3 is less than 5, and F = S plus three if magnitude of SO-3 is 5 or greater. Addition is modulo 16.
6. Additions and Subtractions are BCD adds and subtracts. Resu!ts are undefined if R or S are not in valid BCD fermat.
7. The 0 register cannot be used explicitly as an operand for any special functions. It is defined impliCitly within the functions.
8. L = LOW, H = HIGH, X = Don't Care, 'V" = Exclusive OR, PARITY = SIO 3'V"F3'V" F2'V"F 1'V"Fo

8-80

L

L

IDT39C203/A 4-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Table 5. IDT39C203 Status Outputs
P/OVR
(HEX) (HEX)

18- 5

14- 1

X

0

X

1

10

GI
(I=Oto3)

PI
(1=0 to 3)

C n +4

H

0

1

0

X

R"I" SI

AIVS I

GV PCn

X

2

X

R I " 51

RI V51

GV PCn

X

3

X

RI " SI

RIVS I

GV PCn

X

4

X

0

SI

GV PCn

X

5

X

0

51

GV PCn

6

H

0

RI

GVPC n

X

7

H

0

AI

GV PCn

X
X
X
X
X
X
X
X

8

H

0

9

AI"SI
RI"SI
R"I" SI
RI"SI
R"I" 51
R I " SI

F

X
X
X
X
X
X
X

0
0
0
0
0
0
0
0

0

0

L

R I " 51
OifZ=L
RI " SI if
Z=H

1
1
RI VS I
RI VS I
1
1
1
1
SI ifZ=L
RI V SI if
Z=H

1

0

L

0

SI

1

8

L

0

2

0

L

OifZ=L
RI " SI if
Z=H

SI
SI ifZ=L
RIV SI if
Z=H

3

0

L

Note 6

4

0

L

Note 1

X

A
B
C

D

E

GIN

Z(OEy= L)

MOST SIG OTHER MOST SIG. OTHER MOST SIG.
SLICE
SLICES
SLICE
SLICES
SLICE

0
Cn + 3"V'
Cn + 4
C n + 3"V'
Cn+ 4
Cn + 3"V'
Cn + 4
C n + 3"V'

INTERMEDIATE LEAST SIG.
SLICE
SLICE

0

F3

G

Yo Y1 Y2 Y3

Yo Y1 '12 Y3

Yo Y 1 Y2 '13

P

F3

G

YO?l ?2?3

YO?l '12 ?3

?o Y 1 ?2?3

P

?0?1 '12 Y3

?oY1Y2?3

F3

G

YO?l ?2Y3

P

F3

G

?0?1 ?2Y3

?0?1 '12?3

?0?1 Y2?3

P

F3

G

?0'1l ?2 ?3

?O'1l '12 ?3

?0?1?2 ?3

C n + 3"V'
Cn + 4

P

F3

G

Yo Y 1?2?3

Yo Y 1Y2 Y3

?0?1 Y2?3

C n + 3"V'
Cn + 4
C n + 3"V'
C n +4

P

F3

G

YO?l ?2?3

?o Y 1?2?3

'10 Y 1?2 Y3

C, + 4

0
0
0
0
0
0
0
0

P

F3

G

YOY 1Y2 Y3

Yo Y 1Y2 Y3

YOY 1Y2 ?3

0
0
0
0
0
0
0
0

F3
F3
F3
F3
F3
F3
F3
F3

G
G
G
G
G
G
G
G

Yo Y1 Y2 Y3
Yo Y1 Y2 Y3
Yo '11 Y2 Y3
Yo Y1 '12 Y3
YOYl Y2Y3
?o Y 1 ?2?3
YOYl Y2Y3
Yo Y1 Y2 Y3

?o Y1 Y2 Y3
Yo Y1 Y2 Y3
Yo Y1 '12 '13
Yo '11 Y2 Y3
YOYl Y2 Y3
Yo Y1 '12 Y3
YOYl Y2 Y3
Yo Y1 Y2 Y3

YOY1 Y2 Y3
Yo Y 1 Y2 Y3
Yo Y1 '12.Y3
'10 Y 1 Y2 Y3
YOYl Y2 Y3
Yo Y 1 '12 Y3
YOYl Y2 Y3
Yo Y 1 Y2 Y3

Input

Input

00

GVPC n

C n + 3"V'
Cn + 4

P

F3

G

GVPC n

C n + 3"V'
Cn + 4

P

F3

G

?O Y 1Y2 Y3

YOY 1?2?3

Yo Y 1?2?3

0

F3

G

Yo Y1 Y2 Y3

Yo Y1 Y2 Y3

YOY1 Y2 Y3

0

0

GVPC n

C n + 3"V'
Cn + 4

P

F3

G

Input

Input

00

Note 7

GV PCn

Cn + 3"V'
Cn + 4

P

F3

G

?oY1?2?3

YO'll ?2?3

?0?1?2 '13

Note 2

GVPC n

C n + 3"V'
Cn + 4

P

F3

G

YOY 1?2?3

?oY1Y2 Y3

?oY1?2 Y3

G

S3

Input

Input

Input

Input

00

Yo'll ?2?3

YOY 1Y2 ?3

5

0

L

0

SI ifZ=L
SI ifZ=H

GV PCn

C n + 3"V'
Cn + 4

P

F3 ifZ=L
F3"V'8.3 if
Z=H

6

0

L

OifZ=L
AI" SI if
Z=H

SI if Z=L
RIV SI if
Z=H

GV PCn

C n + 3"V'
Cn + 4

P

F3

G

7

0

L

0

SI

GV PCn

P

F3

G

Yo'll ?2 Y3

8

0

L

0

SI

Note 3

C n + 3"V'
Cn + 4
02"V'01

P

03

G

0 00 10 203 0 00 10 20 3 0 00 10 20 3

9

0

L

0

SI

GV PCn

C n + 3"V'
Cn + 4

9

L
L
L

0
0

SI
SI
RI VS I

G
G

B

8
0
0

C

0

L

D

0

A

P

F3

0

0

0

Note 4
GV PCn

F2"V' Fl
Note 8

P
Note 8

F3
F3
Note 9

G
Note 9

'00'0 1'02'03

'OcP 1'02'03

'00'0 1'02'03

00 0 10 2'03 00 0 10 2 0 3 0 00 102 0 3
Note 5
Note 5
Note 5
YOYl Y2Y3 Yo Yl Y2'13 YOY1Y2'13

RI " SI
RI" SI if
Z=L
AI" SI if
Z=H

RIV SI if
Z=L
AIV SI if
Z=H

GV PCn

C n + 3"V'
Cn + 4

P

F3

G

Sign
Compare
FF Output

Input

Input

L

RI " 51

RIV"S"I

GV PCn

C n + 3"V'
C n +4

P

F3

G

?oY1Y2?3

?0?1?2 '13

YO?l Y2 Y3

RIV SI if
Z=L
AI VS I
Z-H

GV PCn

C n + 3"V'
Cn + 4

P

F3

G

Sign
Compare
FF Output

Input

Input

AIVS I

GVPC n

C n + 3"V'
Cn + 4

P

F3

G

?0?1 ?2?3

?0?1 Y2 '13

E

0

L

RI" SI if
Z=L
AI"SI
Z-H

F

0

L

AI" SI

?0?1 ?2?3

Notes on next page

8-81

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

NOTES:
1. If LSS Is LOW, Go = Soand G'.2.3 = O.lf LSS Is HIGH, G 0.'.2.3 = O.
2. If LSS Is LOW, Po = 1 and P'.2.3 = S,.2.3 . If LSS Is HIGH, PI = SI .
3. At the most significant slice, C n+4 = 0 3 '9'0 2, At other slices C n+4 = G V PCn.
4. Atthemostslgnlficantslice,Cn+4 = F3'9'F2 . At other slices C n+4 = GVPC n.
5. Z = 0 0'0,'02 '03 Fo II ~ F3·
6. IfLSSls LOW, Go = 0 andG,.2.3 = S'.2.3.lfLSSisHIGH,G o.,.2.3= SO.'.2.3'
7. If LSS Is LOW, Po = S and P,.2.3 = S . If LSS is HIGH, PO.'.2.3 = 1.
8. On all slices P=(Po + P3 ) (Po + P2 ) (Po + el, + P2 ).
9. On all slices el=el 3 (el o + el, + P2 ) (Cla + el,) (~ + el 2) (P3 + P, • 152 • el o).
10. L = LOW = 0, H = HIGH = 1, V = OR, 1\ = AND, '9'= EXCLUSIVE OR, P = P 3P2P, Po,
G = G3 VG 2 P3 VG,P2 P3 VG,P,P2 P3 ,C n +3= G2 VG, P2 VG OP,P2 VC:nPoP'P2 VC nPoP'P2

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

GRADE
Military
Commercial

TA

Operating
Temperature

Oto +70

-55 to +125

°c

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°c

TSTG

Storage
Temperature

-55 to +125

-65 to +150

Power DisSipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

GND
OV

5.0V ± 10%

O°Cto +700C

OV

5.0V ± 5%

CAPACITANCE
SYMBOL

°c

PT

AMBIENT
TEMPERATURE
-55°C to + 125°C

(TA= +25°C, f = 1.0MHz)

PARAMETER(I)

CIN

Input Capacitance

C OUT

Output Capacitance

CONDITIONS

8-82

TYP.

UNIT

VIN = OV

5

pF

VOUT = OV

7

pF

NOTE:
1. This parameter is sampled and not 100% tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated In the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Vee

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
TA = O°C to + 70°C
TA = -55°C to + 125°C
VLC = 0.2V
VHC = Vcc - 0.2V
SYMBOL

Vcc = 5.0V ± 5% (Commercial)
Vcc = 5.0V ± 10% (Military)

TEST CONDITIONS (1)

PARAMETER

\'IH

Input HIGH Level

Guaranteed Logic High Level

\'IL

Input LOW Level

Guaranteed Logic Low Level (4)

IIH

Input HIGH Current

Vcc = Max., \'IN = Vcc

IlL

Input LOW Current

Vcc = Max., VIN = GND

(4)

10H = -300~A
VOH

VOL

Output HIGH Voltage

Output LOW Voltage

Vcc = Min.
\'IN = \'IH or\'lL

Vcc = Min.
\'IN = \'IH or\'lL

MIN.

TYP,<2)

MAX.

UNIT

2.0

-

V

-

-

0.8

V

-

0.1

5

~A

-

-0.1

·5

~A

VHC

Vcc

-

IOH = -12mA MIl.

2.4

4.3

-

IOH = -15mA COM'l.

2.4

4.3

-

IOL = 300~A

-

GND

IOL = 20mA MIl.

-

0.3

VLC
0.5

IOL = 24mA COM'l.

-

0.3

0.5

-

-0.1

-10

0.1

10

·30

-

-

mA

Vo = OV

V

V

Off State (High Impedance)
Output Current

Vcc = Max.

los

Output Short Circuit Current

Vcc

ICCOH

Quiescent Power Supply Current
CP = H (CMOS Inputs)

Vcc = Max.
VHC ::; \'IN ' \'IN ::; VLC
fcp = 0, CP = H

-

5

15

mA

ICcaL

Quiescent Power Supply Current
CP = L (CMOS Inputs)

\k:c = Max.
VHC ::; \'IN ' \'IN ::; VLC
fcp = 0, CP = L

-

5

15

mA

ICCT

Quiescent Input Power Supply (5)
Current (per Input @ TTL High)

Vcc = Max. \'IN = 3.4V, fcp = 0

-

0.25

0.5

mN

Dynamic Power Supply Current

Vcc = Max.
VHC ::; \'IN , \'IN .~...vLC
Outputs Open, OE = L

MIl.

-

0.5

2.0

COM'l.

-

0.5

1.5

MIl.

-

10

35

COM'l.

-

10

30

MIl.

-

20

55

20

50

loz

ICCD

Icc

Total Power Supply Current(6)

Vo =Vcc

= Min.,

VOUT

= OV

(3)

Vcc = Max., fop = 10MHz
Outputs Open, DE = L
CP = 50% Duty cycle
VHC ::; VIN , \'IN::; VLC
Vcc = Max., i:;p....::.. 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
\'IH = 3.4V, \'IL = O.4V

~A

Input

mAl

MHZ

mA

COM'l.

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise·free environment.
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCOH , then dividing by the total number of inputs.
6. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS or TTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH (C~) + ICCOL (1 - CD H) + ICCT(NT X DH) + ICCD (fcp)
CD H = Clock duty cycle high period.
DH = Data duty cycle TTL high period (\liN = 3.4V).
NT = Number of dynamic inputs driven at TTL levels.
fcp = Clock input frequency.

8-83

MILITARV AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

IDT39C203A GUARANTEED COMMERCIAL
RANGE PERFORMANCE

Table 13 Enable/Disable Times All Functions (1)
FROM

TO

ENABLE

DISABLE

'O"E"y

V

20

17

OEB

DB

20

17

EA

DA

20

17

la

SIO

20

17

la

010

30

30

la. 7. 6. 5

010

30

30

14,3,2.1,0

010

30

28

WRITE'

20

The tables below specify the guaranteed performance of the
IDT39C203A over the commercial operating range of 0 to + 70°C
with Vcc from 4.75 to 5.25V. A" data are in nanoseconds, with inputs switching between 0 and 3Vat 1V/ns and measurements
made at 1.5V. A" outputs have maximum DC load.

Table 12. Clock and Write Pulse Characteristics All Functions
Minimum Clock Low Time

24ns

Minimum Clock High Time

24ns

Minimum Time CP and Wt. both Low to Write

12ns

[SS

17
NOTE:
1. C L = 5.0pF for output disable tests. Measurement is made to a
0.5V change on the output.

Table 14. Set-up and Hold Times All Functions
HIGH-TO-LOW

LOW-TO-HIGH
tpwL

FROM
V

WE

WITH RESPECT TO

SET-UP

HOLD

CP

Don't Care

Don't Care

HIGH

CP

12

Wt.LOW

CP

Don't Care

Don't Care

A, B Source

CP

16

3

B Destination

CP

5

010 0. 3

CP

Don't Care

Don't Care

la. 7. 6. 5

CP

10

-

TEN HIGH

CP

19

TEN LOW

CP

Don't Care

14. 3. 2,1,0

CP

14

I
I

SET-UP

HOLD

11

3

TpWL

T 12
I Don't Care

0

Prevent Writing

0

Write into RAM

Don't Care

Latch Data from RAM Out

3

Write Data into B Address

14

3

Shift a

16

0

Write into 0(2)

TpwL

1
I

COMMENTS
Store V in RAM/a (1)

TpwL

0

Prevent Writing into a

Don'tCare 1

17

0

Write into a

I

26

0

Write into 0(2)

-

NOTES:
1. The internal V-bus to RAM set-up condition will be met 5ns after valid V output (OE'y= L)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing.
3. Fai aU other set-up conditions not specified in this table, the set-up time should be the delay to stable V output plus the V to RAM internal set-up
time. Even if the RAM is not being loaded, this set-up condition ensures valid writing into the a register and sign compare flip-flop.
4. WE controls writing into the RAM. lEN controls writing into a and, indirectly, controls WE through the WRITE'/MSS output. To prevent writing, TEN and
WE must go HIGH during the entire clock LOW time. They may go LOW after the clock has gone LOW to cause a write, provided the WE LOW and
lEN LOW set-up times are met. Having gone LOW, they should not be returned HIGH until after the clock has gone HIGH.
5. A and 8 addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6. Writing occurs when CP and WE are both LOW. The B address should be stable during this entire period.
7. Because la.7.6,5 controls the writing or not writing of data into RAM and O. they should be stable during the entire clock LOW time unless TEN is HIGH.
which prevents writing.
8. The set-up time prior to the clock LOW-TO-H IGH transition occurs in parallel with the set-up time prior to the clock HIGH-TO-LOW transition and the clock
LOW time. The actual set-up time requirement on 14.3.2.1.0 relative to the clock LOW-TO-HIGH transition is the longer of (1) the set-up time prior to
clock L -+ Hand (2) the sum of the set-up time prior to clock H -+ L and the clock LOW time.

8-84

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203A GUARANTEED COMMERCIAL RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT/DECREMENT BY ONE OR TWO INSTRUCTIONS (SF3, SF4)
TO
FROM

Y

C n +4

A, B Addr

54

44

DA,DB

46

40

Z

N

OVR

DA,
DB

WRITE

010 0,3

SIOO

SI03

42

59

49

54

22

50

62

52

43

46

-

-

33

32

28

47

52

'0,15

SIOo
PARITY

Cn

26

14

-

28

22

22

-

-

18

24

30

18-0

51

51

40

58

49

50

-

27

21

40

50

59

CP

46

34

34

49

43

46

18

-

18

30

43

48

SIOo, SI03

18

-

23

-

-

-

-

35

35

35

35

-

35

-

~

46

40

32

52

43

46

-

-

-

15

35

-

23

1VfSS

-

28

47

52

NOTES:
1. A" -" means the delay path does not exist.
2. An "." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct
data on an enabled output..
3. Standard Functions: See Table 2, Increment SF4: F=S+1 +Cn and Decrement SFD: F=S-2+C n

MULTIPLY INSTRUCTIONS (SFO, SF2, SF6)
TO
FROM

A, B Addr

DA, DB

SLICE

Y

C n +4

'0,15

Z

N

OVR

DA,
DB

WRITE

010 0 ,3

SIOo

MSS

(44)

-

(54)

(22)

-

(44)

(42)

(22)

(44)

(42)

-

(22)

(33)

MSS
IS

(46)

(40)

-

-

(43)

(46)

-

(28)

(46)
(46)

(40)

(32)

-

-

(40)

(32)

-

28

(14)

-

(22)

(22)

(18)

IS

(26)

(14)

-

LSS

(26)

(14)

-

-

MSS

75

60

-

-

-

-

(28)
(28)

MSS

-

-

70

70

58

75

60

57

-

58

75

60

57

24

-

(21)

LSS

-

-

(21)

IS

-

-

-

(33)

(54)

-

-

LSS

-

(49)

IS

(54)
(54)

-

(27)

(21)

58

MSS

(46)

(34)

-

(46)

(18)

(30)

(34)

(34)

(18)

(30)

75

60

57

24

-

(18)

LSS

-

-

(18)

(46)

-

(43)

IS

(18)

58

MSS

51

36

-

-

46

46

IS

51

36

33

-

LSS

-

-

-

Any

(18)

-

-

-

-

-

-

-

LSS
Cn

18-0

CP

Z
SIOo, SI03

(18)

-

-

-

(33)

(18)
(18)

34

34

-

NOTES.
1. A" _. means the delay path does not exist.
2. An "." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct
data on an enabled output.
3. A number is parentheses means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
4. Unsigned Multiply
Two's Complement Multiply
Two's Complement Multiply Last Cycle
SFO: F=S+C n if Z=O
SF2: F=S+Cn if z=o
SF6: F=S+Cn if Z=O
'
F=S+R+Cn ifZ=1
F=R+S+Cn ifZ=1
F=S-R-1 +Cn ifZ=1
Y=Log. F/2
Y=Log. F/2
Y=Log. F/2
0= Log. 0/2
0 = Log. 0/2
0 = Log. 0/2
Y3 =
+4 (MSS)
Y3 = F:3 E9 OVR (MSS)
Y3 = OVR E9 FJ (MSS)
Z=Oo (LSS)
Z=Oo (LSS)
Z=Oo (LSS)

en

8-85

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

IDT39C203A GUARANTEED COMMERCIAL RANGE PERFORMANCE DIVIDE INSTRUCTIONS
(SFA, SFC, SFE)
TO
FROM

A, B Addr

DA, DB

Cn

18- 0

CP

Z
SIOo, SI03

SLICE

Y

MSS

(54)

IS

(54)

G,P

Z

N

OVR

DA,
DB

WRITE

010 0 ,3

SI03

49/(44)

-

159)/-

~49)

~54)

(22)

(44)

(42)

(59)/-

-

(22)

-

-

(50)

-

(24)

-

(21)

(50)/66

C n +4

LSS

(54)

(44)

(42)

(59)/-

-

-

MSS

(46)

44/40

-

(52)/-

(43)

(46)

-

IS

(46)

(40)

(32)

(52)/-

LSS

(46)

(40)

(32)

(52)/-

-

-

MSS

_(26)

26/(14)

128)/-

J22)

122)

IS

(26)

(14)

-

(28)/-

-

LSS

(26)

(14)

-

(28)/-

-

-

MSS

(51)/67

60/54

-

(58)/23

(49)/62

(50)/62

-

-

IS

(51)/67

(51)/54

(51)/67

(51)/54

(40)/(56)
(40)/(56)

(58)/-

LSS

(58)/-

MSS

(46)/68

37/55

-

-

(49)/24

(43)/53

IS

(46)

(34)

(34)

(49)/-

LSS

(46)

(34)

(34)

(49)/-

-

MSS

-

-

-

-

-

IS

-/44

-/31

-/33

-

-

LSS

-/44

-/31

-/33

Any

(18)

-

-

-

-

(22)

-

-

-

(50)
(50)
(47)
(47)
(47)

-

26

-

(24)

-

(21)

(50)/66

-

(27)

(21)

(50)/66

(46)/53

(18)

(18)

(43)/63

-

(18)

-

(18)

(43)

(18)

(43)

-

-

-

-

-

(18)

-

-

-

-/43
-/43

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct
data on an enabled output.
3. A number is parentheses means the delay path Is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
4. If two delays are given, the first is for 1st divide and normalization; the second is for two's complement divide and two's complement divide
correction.
Two's Complemen~ Divide Correction and Remainder
5. Double Length Normalize and First Divide Op Two's Complement Divide
SFA: F=S+C n
SFC: F= R+S+C n if Z=O
SFE: F=R+S+C n if Z=O
F=S-R-1+C n ifZ=1
Y=Log.2F
F=S-R-1 +C n if Z=1
Y= Log. 2F
Y=F
0=Log.20
0=Log.20
SI03 = F3 El1 R3 (MSS)
O=Log~O_ .
Z=~ El1 R3(MSS) from previous cycle
C n +4 =F3El1 F2 (MSS)
SlOp = W3(MSS)
Z= 3
3 (MSS) from previous cycle
OVR = Fz ffi Fl (MSS)

Z=QOQ1~Q31b"F, ~ ~

8-86

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203A GUARANTEED COMMERCIAL RANGE PERFORMANCE BCD INSTRUCTIONS
(SF1,SF7,SF9,SFB,SFD,SF~
TO
FROM

A. B Addr

DA. DB

en
18- 0

CP

S100-3

SLICE

Y

C n +4

G.p

DA.
DB

WRITE

QIO O• 3

SIO o

54

(22)

-

(50)

(62)

(22)

-

-

44

-

44

(50)

(62)

(22)

-

44

(50)

(62)

-

36

(47)

(52)

36

(47)

(52)

36

(47)

(52)

24

29

35

24

29

35

Z

N

OVR

54

MSS

58

48

-

(59)

IS

58

48

44

(59)

LSS

58

48

44

(59)

-

MSS

49

42

-

(52)

47

47

-

IS

49

42

38

(52)

-

-

SI03

SIOo
PARITY

IS

58

(51)

50

(58)/36

(21)

(40)

(50)

(59)

58

(51)

50

(58)/36

-

-

LSS

-

-

-

(27)

(21)

(40)

(50)

(59)

MSS

50

42

-

54/24

50

50

(18)

-

(18)

31

48

52

IS

50

42

40

54/24

-

(18)

31

48

52

50

42

40

54/24

(18)

31

48

52

(18)

-

-

-

-

-

(18)

Any

-

(18)

LSS

-

-

-

-

-

LSS

49

42

38

(52)

-

-

MSS

29

18

30

26

26

IS

29

18

30

-

30

-

-

-

(58)/36

50

(50)

-

LSS

29

18

MSS

58

(51)

-

-

-

-

24

29

35

(21)

(40)

(50)

(59)

NOTES:
1. Binary-ta-BCD and multiprecision Binary-to-BCD instructions only.
2. BCD-ta-binary conversion (SF1). Binary-to-BCD conversion (SF9). BCD subtract (SFD. SFF). BCD divide by two (SF7). BCD add (SFB)
3. A· -" means the delay path does not exist.
4. A number in parentheses means the delay path is the same as specified in the Standard Functions and Increment by One orTwo Instructions Table. This
specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
5. If two delays are given. the first is for 1st divide and normalization; the second is for two's complement divide and two's divide correction.

8-87

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

IDT39C203A GUARANTEED COMMERCIAL RANGE PERFORMANCE
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SF5)
TO
FROM

A, B Addr

DA, DB

Cn

18- 0

CP

Z
SIOo, SI0 3

SLICE

Y

C n +4

G,P

Z

N

OVR

DA,
DB

WRITE

QIO O,3

MSS

78

67

-

36

71

71

(22)

-

84

IS

(54)

(44)

(42)

-

(22)

-

-

(50)

(22)

-

-

(50)

-

LSS

(54)

(44)

(42)

-

-

-

MSS

75

63

-

32

67

67

-

IS

(46)

(40)

(32)

-

-

26

(21)

-

LSS

(46)

(40)

(32)

MSS

(26)

(14)

-

-

IS

(26)

(14)

(26)

(14)

-

-

LSS

-

-

-

MSS

68

54

-

22

66

58

IS

68

54

50

-

-

LSS

68

54

50

-

-

-

-

MSS

75

63

-

32

67

67

IS

(46)

(34)

(34)

-

-

-

-

LSS

(46)

(34)

(34)

-

-

MSS

-

-

-

-

IS

46

31

28

-

-

LSS

46

31

28

-

-

-

Any

(18)

-

-

-

-

-

SI03

-

80

-

(47)

-

_(47)

-

(24)

-

-

(24)

(21)

70·

-

(21)

70·

(27)

(21)

70·

(18)

-

(18)

80

(18)

-

(18)

(43)

(18)

-

(18)

(43)

-

-

-

-

(24)

-

-

48

-

48

-

-

NOTES:
1. A" _. means the delay path does not exist.
2. An "." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct
data on an enabled output.
3. A number is parentheses means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
4. SF5:F=S+C n ifZ=0,
Y3=S3E9F3(MSS),
Q=Q
F=S+Cn ifZ=1,
Z=S3(MSS),
N=F3 ifZ=O
N=F3E9S3ifZ=1

8-88

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203A GUARANTEED COMMERCIAL RANGE PERFORMANCE
SINGLE LENGTH NORMALIZATION (SF8)
TO

FROM

A, BAddr

DA,DB

Cn

18- 0

CP
SIOo, SI0 3

G,P

Z

N

OVR

DA,
DB

WRITE

QIO O,3

-

-

-

(22)

-

(22)

-

-

-

-

SLICE

Y

MSS

(54)

-

-

IS

(54)

(44)

(42)

LSS

(54)

(44)

(42)

-

-

MSS

(46)

-

-

-

C n +4

IS

(46)

(40)

(32)

LSS

(4~

(401

~32)

MSS

(26)

-

-

-

IS

(26)

(14)

-

-

-

(22)

-

-

-

-

-

-

-

LSS

(26)

(14)

-

-

-

(51)

30

-

-

MSS

23

19

19

-

-

-

-

SI0 3
(50)
(50)
(50)
(47)

-

(47)

-

~4D

-

(24)

(24)

-

(24)

(21)

(50)·

IS

(51)

(51)

(40)

23

-

(21)

(50)·

LSS

(51)

(51)

(40)

23

-

-

-

-

(27)

(21)

(50)·

MSS

(46)

23

-

24

21

21

(18)

(18)

(4~

IS

(46)

(34)

(34)

24

-

-

(18)

(18)

(43)

LSS

(46)

(34)

(34)

24

-

-

(18)

-

(18)

(43)

Any

(18)

-

-

-

-

-

-

-

-

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct
data on an enabled output.
3. A number is parentheses means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
4. SF8: F=S+C n
C n t.1 = q" ffi 02 (MSS)
OVR=02 $ 0, (MSS)
N=03 (MSS)
Z=QOQ,Q2 Q3
Y=F
o = Log. 20

8-89

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

IDT39C203A GUARANTEED MILITARY RANGE
PERFORMANCE

Table 16. Enable/Disable Times All Functions (1)

Table 15. Clock and Write Pulse Characteristics All Functions
Minimum Clock Low Time

24ns

Minimum Clock High Time

24ns

Mi~imum Time CP and wr:. both Low to Write

24ns

TO

ENABLE

DISABLE

OE"y

Y

20

17

0I:a

DB

20

17

EA

DA

20

17

FROM

The tables below specify the guaranteed performance of the
IDT39C203A over the military operating range of -55°C to
+ 125 °C with Vee from 4.5 to 5.5V. All data are in nanoseconds,
with inputs switching between 0 and 3V at WIns and measurements made at 1.5V. All outputs have maximum DC load.

16

SIO

20

17

16

010

30

30

16,7,6,5

010

30

30

14,3,2,1,0

010

30

28

24
l3S
WliTT1:
20
NOTE:
1. C L = 5.0pF for output disable tests. Measurement is made to a
0.5V change on the output.

Table 17. Set-up and Hold Times All Functions
HIGH-TO-LOW

LOW-TO-HIGH
t pwL

FROM

I
I

WITH RESPECT TO

SET-UP

HOLD

Y

CP

Don't Care

Don't Care

wr:. HIGH

CP

12

wr:.LOW

CP

Don't Care

Don't Care

A, B Source

CP

16

3

B Destination

CP

5

010 0,3

CP

Don't Care

Don't Care

16,7,6,5

CP

10

-

TrnHIGH

CP

19

Trn LOW

CP

Don't Care

Don't Care

14,3,2,1,0

CP

14

-

SET-UP

HOLD

11

3

COMMENTS
Store Y in RAM/a (1)

0

Prevent Writing

I

12

0

Write into RAM

I

Don't Care

Don't Care

Latch Data from RAM Out

3

Write Data into B Address

TpWL

TpWL

I
I

14

3

Shift a

16

0

Write into

0

Pr~vent Writing into a

17

0

Write into a

26

0

Write into

TpwL

I
I

0(2)

0(2)

NOTES:
1. The intemal V-bus to RAM set-up condition will be met 5ns after valid Y output (OE"y= L)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing,
3. Fer a!! cther :let-up conditions not SPecified in this tab;e, the set-up lime should be the delay to stable Y output plus the Y to RAM internal set-up
time. Even if the RAM is not being loaded, this set-up condition ensures valid writing into the a register and sign compare flip-flop.
4. wr:. controls writing into the RAM. lEN controls writing into a and, indirectly, controls wr:. through the W"RliE/lV1SS output. To prevent writing, Trn and
wr:. must go HIGH during the entire clock LOW time. They may go LOW after the clock has gone LOW to cause a write, provided the
LOW and
Trn LOW set-up times are met. Having gone LOW, they should not be returned HIGH until after the clock has gone HIGH.
5. A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6. Writing occurs when CP and
are both LOW. The B address should be stable during this entire period,
7. Because la,7,6,5 controls the writing or not writing of data into RAM and A, they should be stable during the entire clock LOW time unless TEN is HIGH,
which prevents writing.
8. The set-up time prior to the clock LOW-TO-HIGH transition occurs in parallel with the set-up time priorto the clock HIGH-TO-LOW transition and the clock
LOW time. The actual set-up time requirement on 14,3,2,1,0 relative to the clock LOW-TO-HIGH transition is the longer of (1) the set-up time prior to
clock L -+ H and (2) the sum of the set-up time prior to clock H -+ L and the clock LOW time.

wr:.

wr:.

8-90

IDT39C203/A 4-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203A GUARANTEED MILITARY RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT/DECREMENT BY ONE OR TWO INSTRUCTIONS (SF3, SF4)
TO
FROM

a,lS

Z

46

42

62

42

32

53

Y

C n +4

A, B Addr

56

DA,DB

48

OVR

DA,
08

WRITE

010 0 ,3

54

54

22

38

57

67

46

-

-

44

-

28

49

59

N

Cn

28

15

-

33

25

23

18-0

58

55

45

64

57

55

-

CP

48

34

34

54

44

46

18

SIOo, SI03

21

-

-

23

-

-

MSS

35

-

35

35

35

35

Eli:

48

42

32

53

44

46

-

SIO o

SI0 3

SIOo
PARITY

-

-

18

26

32

29

21

46

60

71

-

18

33

49

53

-

23

15

-

-

35

-

-

-

28

49

59

NOTES:
1. A· _. means the delay path does not exist.
2. An ••• means the output is enabled or disabled by the input. See enable and disable times. A number shown with an " •• is the delay to correct
data on an enabled output..
3. Standard Functions: See Table 2. Increment SF4: F=S+1 +C n and Decrement SF3: F=S-2+C n

MULTIPLY INSTRUCTIONS (SFO, SF2, SF6)
TO
FROM

A, B Addr

DA, DB

Cn

18- 0

CP

Z

SLICE

Y

C n +4

a,P

z

N

OVR

DA,
DB

WRITE

010 0,3

MSS

(56)

(46)

-

(54)

(54)

(221

-

IS

(56)

(46)

(42)

-

-

-

(22)

-

-

-

(22)

-

-

(44)

(46)

-

-

-

-

-

-

(25)

(23)

-

-

-

-

-

LSS

(56)

(46)

(42)

MSS

(48)

(42)

-

IS

(48)

(42)

(32)

LSS

(48)
32

(421
(15)

~32)

MSS

-

-

-

-

SIOo
(38)
(38)
(38)
(28)
(28)
(28)
(18)

IS

(28)

(15)

-

LSS

(28)

(15)

-

MSS

86

67

-

-

78

78

-

-

(21)

IS

86

67

64

-

-

-

-

(21)

65·

LSS

86

67

64

26

-

-

-

(29)

(21)

65·

(44)

(46)

(18)

(18)

(33)

-

-

(18)

-

(18)

(33)

(18)

-

(18)

66

-

-

38

-

-

-

-

MSS

(48)

(34)

-

IS

(48)

(34)

(34)

-

LSS

87

68

63

27

-

-

MSS

60

41

-

52

52

IS

60

41

38

-

-

LSS

-

-

-

-

-

-

-

-

(18)
(18)
65·

38

-

-

(21)
Any
SIOo. SI03
NOTES:
1. A" - • means the delay path does not exist.
2. An " •• means the output is enabled or disabled by the input. See enable and disable times. A number shown with an " •• is the delay to correct
data on an enabled output.
3. A number in parenthesis means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Tests.
4. Unsigned Multiply
Two's Complement Multiply
Two's Complement Multiply Last Cycle
SFO: F=S+C n ifZ=O
SF2: F=S+C n ifZ=O
SF6: F=S+C n ifZ=O
F=S+R+C n if Z=1
F=R+S+C n if Z=1
F=S-R-1 +C n if Z=1
Y3 =C n + 4 (MSS)
Y3=F3ffiOVR(MSS)
Y3 = OVR ffiF3(MSS)
Z=Oo (LSS)
Z=Oa (LSS)
Z=Oo (LSS)
Y=Log. F/2
Y=Log. F/2
Y=Log. F/2
0= Log. 0/2
0 = Log. 0/2
0 = Log. 0/2 .

8-91

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203A GUARANTEED MILITARY RANGE PERFORMANCE DIVIDE INSTRUCTIONS (SFA, SFC, SFE)
TO
FROM

A. B Addr

DA,DB

Cn

18- 0

CP

2
SIOo,SI03

SLICE

Y

C n +4

G,P

Z

N

OVR

DA,
DB

MSS

(56)

58/(46)

-

(62)/-

(54)

(54)

(22)

IS

(56)

(46)

(42)

(62)/-

(56)

(46)

(42)

(62)/-

-

(22)

LSS

-

MSS

(48)

53/(42)

-

(53)/-

(44)

(46)

-

IS

(48)

(42)

(32)

(53)/-

(48)

(42)

(32)

(53)/-

-

-

LSS
MSS

(28)

30/(15)

-

-

(33)/-

(25)

(23)

IS

(28)

(15)

-

(33)/-

-

-

(22)

-

WRITE

-

010 0 • 3

SI03

-

(57)

-

(57)

-

(49)

(57)

(49)
J49)

-

-

-

29

-

-

(26)

-

-

(26)

(21)

61178*

(21)

(60)178*

-

(29)

(21)

(60)178*

LSS

(28)

(15)

-

(33)/-

-

-

-

MSS

(58)177

71/63

-

(64)/26

(57)173

(55)173

-

IS

(58)177

(55)/63

(45)/63

(64)

LSS

i55)163
41/64

145)/63

(64)

-

-

-

MSS

. (5&77
(48)178

(54)/27

(44)/59

(46)/59

(18)

-

(18)

(49)174

IS

(48)

(34)

(34)

(54)

-

(18)

(49)

(48)

(34)

(34)

(54)

(18)

(18)

(49)

MSS

-

-

-

-

-

IS

-/50

-/37

-/37

LSS

-/50

-/37

-/37

-

-

(18)

LSS

-

-

-

Any

(21)

-

-

-

-

-

-

-

-

-

-

-

-/52

-

-

-/52

-

-

-

NOTES:
1. A· - • means the delay path does not exist.
2. An "*" means the. output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. A number is parentheses means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
4. If two delays are given, the first is for 1st divide and normalization: the second is for two's complement divide and two's complement divide
correction.
5. Double Length Normalize and First Divide Op
Two's Complement Divide
Two's Complement Divide Correction and Remainder
SFA: F=S+C n
SFC: F=R+S+C n if2=0
SFE: F= R+S+C n if 2=0
SI03 = F3 E9 R3 (MSS)
F=S-R-1+Cn if 2=1
F=S-R-1+Cn if 2=1
Y= Log. 2F
C n +4 =F3E9 F2 (MSS)
Y=F
Q=Log.2Q
OVR = Fz ffi F1 (MSS)
0=Log.20
2= ~ E9 R3(MSS) from previous cycle
2=00 0 1 0"2 0 3Fo t-; ~ ~
3
SID?
R3(MSS)
Y=Log.2F
2= ~
3 (MSS) from
Q=Log.20
prevIous cycle

=4 W,

8-92

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

IDT39C203A GUARANTEED MILITARY RANGE PERFORMANCE BCD INSTRUCTIONS
(SF1,SF7,SF9,SFB,SFD,SF~
TO
FROM

A. B Addr

DA.DB

en
18- 0

CP
SI00--3

DA,
DB

WRITE

QIO o• 3

SIOo

SI03

SIOo
PARITY

56

(22)

48

(57)

(67)

(22)

-

48

(57)

(67)

-

(22)

-

-

-

-

48

(57)

(67)

(53)

51

51

-

-

-

40

(49)

(59)

40

(53)

-

-

(59)

(53)

-

-

40

(49)

(59)

31

21

-

35

30

30

-

(49)

40

-

40

43

27

31

38

IS

31

21

35

-

-

27

31

38

-

-

-

-

35

-

-

27

31

38

(64)/40(1)

58

58

-

-

(21)

(46)

(60)

(71)

SLICE

y

C n +4

MSS

60

52

IS

60

52

LSS

60

52

MSS

50

IS

G,P

Z

N

OVR

-

(62)

56

46

(62)

-

46

(62)

43

-

50

43

LSS

50

MSS

LSS

31

21

-

MSS

61

(55)

-

IS

61

(55)

56

(64)/40(1)

-

(46)

(60)

(71)

(55)

56

(64)/40(1)

-

-

(21)

61

-

-

LSS

(29)

(21)

(46)

(60)

(71)

MSS

54

43

-

56/27(1)

53

53

(18)

-

(18)

34

50

59

IS

54

43

42

56/27(1)

-

-

(18)

-

(18)

34

50

59

LSS

54

43

42

56/27(1)

-

-

(18)

(18)

34

50

59

Any

(21)

-

-

-

-

-

-

-

-

-

-

-

NOTES:
1. Binary-to-BCD and multiprecision Binary-to-BCD instructions only.
2. BCD-to-binary conversion (SF1). Binary-to-BCD conversion (SF9). BCD subtract (SFD. SFF). BCD divide by two (SF7). BCD add (SFB)
3. A· _. means the delay path does not exist.
4. A number in parentheses means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
5. If two delays are given. the first is for 1st divide and normalization; the second is for two's complement divide and two's complement divide cor
rection.

8-93

IDT39C203/A 4·81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203A GUARANTEED MILITARY RANGE PERFORMANCE
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SFS)
TO
FROM
SLICE

A. B Addr

DA.DB

Cn

16 - 0

CP

Z
SIOo. SI03

y

Cn

+.

0,15

Z

N

OVR

DA,
DB

WRiTE

MSS

91

78

-

42

85

85

(22)

(56)

(46)

(42)

-

-

IS

(22)

-

LSS

(56)

(46)

(42)

-

-

-

MSS

86

74

-

37

81

81

IS

(48)

(42)

(32)

-

-

-

LSS

(48)

(42)

(32)

-

MSS

29

(15)

-

-

28

(23)

IS

(28)

(15)

-

-

-

-

26

78

70

-

-

LSS

(28)

(15)

MSS

78

63

-

IS

78

63

58

-

-

LSS

78

63

58

-

-

-

(22)

-

010 0• 3

-

SI03
102
(57)
(57)

90

-

(49)

-

(49)

-

(21)

87*

(21)

87*

(29)

(21)

87*

-

(26)
(26)
(26)

MSS

85

74

-

37

81

81

(18)

98

(48)

(34)

(34)

-

-

(1~>-

IS

-

(18)

(18)

(49)

-

-

-

-

(18)

-

(18)

(49)

-

61

-

61

LSS

(48)

(34)

(34)

MSS

-

-

-

IS

52

37

32

LSS

52

37

32

Any

(21)

-

-

-

-

-

-

-

-

-

-

-

-

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the output Is enabled or disabled by the Input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. A number Is parentheses means the delay path Is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but Is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
Y3 =S3ffi F3(MSS).
O=Q
4. SF5: F=S+Cn if Z=O.
F=S'+Cn if Z=1.
Z=S3(MSS).
N=F3 if Z=O
Y=F
N=F3ffiS3 if Z=1

8-94

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203A GUARANTEED MILITARY RANGE PERFORMANCE SINGLE LENGTH NORMALIZATION (SF8)
TO
FROM

A. BAddr

DA.DB

Cn

18-0

CP

0,15

Z

N

OVR

DA,
DB

-

-

(22)

(46)

(42)

-

-

(56)

-

-

-

-

SLICE

Y

MSS

(56)

IS

C n +4

-

WRITE

0100 ,3

-

-

(22)

-

-

(22)

-

LSS

(56)

(46)

(42)

MSS

(48)

-

-

IS

(48)

(42)

(32)

LSS

(48)

(42)

(32)

MSS

(28)

-

IS

(28)

(15)

26

-

-

-

-

-

-

SI03
(57t
(57)
(57)
(49)

-

(49)

-

(49)

-

(26)

-

-

-

-

-

-

-

22

22

-

(21)

60·

(21)

60·

-

-

(29)

(21)

60·

-

(18)

(49)

LSS

(28)

(15)

MSS

(58)

38

-

IS

(58)

(55)

(45)

26

LSS

(58)

(55)

(45)

26

-

MSS

(48)

25

-

27

21

25

(18)

IS

(48)

(34)

(34)

27

-

-

(18)

LSS

(48)

(34)

(34)

27

-

-

(18)

(26)
(26)

(18)

(49)

(18)

(49)

Any
(21)
SIOo. SI0 3
NOTES:
1. A" -" means the delay path does not exist.
2. An "." means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct
data on an enabled output.
3. A number is parentheses means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
4.

SF8: F=S+C n
N=03 (MSS)
Y=F
0= Log. 20

C n+4 = 03 ffi 02 (MSS)
Z=000102Q3

OVR=02

E9 0l(MSS)

8-95

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

IDT39C203 GUARANTEED COMMERCIAL RANGE
PERFORMANCE

Table 7. Enable/Disable Times All Functions(l)
FROM

TO

ENABLE

DISABLE

C5l:y

Y

25

21

C5l:a

DB

25

21

EA

DA

25

21

18

SIO

25

21

18

010

38

38

The tables below specify the guaranteed performance of the
IDT39C203 over the commercial operating range of 0 to 70 0 C with
Vee from 4.75 to 5.25V. All data are in nanoseconds, with inputs
switching between 0 and 3V at 1V/ns and measurements made at
1.5V. All outputs have maximum DC load.

Table 6. Clock and Write Pulse Characteristics All Functions
Minimum Clock Low Time

30ns

Minimum Clock High Time

30ns

Minimum Time CP and wt=. both Low to Write

15ns

18.7.6.5

010

38

38

14

010

38

35

3

210

[SS
25
WRiiE'
21
NOTE:
1. C L = 5pF for output disable tests. Measurement is made to a
0.5V change on the output.

Table 8. Set-up and Hold Times All Functions
HIGH-TO-LOW

LOW-TO-HIGH
t pwL

FROM

WITH RESPECT TO

SET-UP

I
I

HOLD

Y

CP

Don't Care

wt=. HIGH

CP

15

wt=.LOW

CP

Don't Care

Don't Care

A. B Source

CP

20

3

B Destination

CP

6

0100 . 3

CP

Don't Care

Don't Care

Is. 7, 6. 5

CP

12

-

Don't Care

SET-UP
14

0

Prevent Writing

0

Write into RAM

Don'tCare

Don't Care

Latch Data from RAM Out

3

Write Data into B Address

I

TpWL

I
J

JE:j HIGH

CP

24

JE:jLOW

CP

Don't Care

Don't Care

14,3.2,1,0

CP

18

-

3

COMMENTS
Store V in RAMla (1)

15

TpWL

I

HOLD

17

3

Shift a

20

0

Write into 0(2)

0

Prevent Writing into a

21

0

Write into a

32

0

Write into 0(2)

TpWL

I
I

NOTES:
1, The internal V-bus to RAM set-up condition will be met 5ns after valid V output (O~ y= L)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing.
3. For all other set-up conditions not specified in this table, the set-up time should be the delay to stable Y cutput pius tha V to RAM internal set-up
time. Even if the RAM is not being loaded, this set-up condition ensures valid writing into the a register and sign compare flip-flop.
4. wt=. controls writing into the RAM. lEN controls writing into a and, indirectly, controls ~ through the WRTiE/MSS output. To prevent writing, TE:'i'J' and
must go HIGH during the entire clock LOW time. They may go LOW after the clock has gone LOW to cause a write, provided the WE LOW and
JE:j LOW set-up times are met. Having gone LOW, they should not be returned HIGH until after the clock has gone HIGH.
S. A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6. Writing occurs when CP and WE are both LOW. The B address should be stable during this entire period.
7. Because IS.7,6.5 controls the writing or not writing of data into RAM and a, they should be stable during the entire clock LOW time unless ~ is HIGH,
which prevents writing.
8. The set-up time prior to the clock LOW-TO-HIGH transition occurs in parallel with the set-up time prior to the clock HIGH-TO-LOW transition and the clock
LOW time. The actual set-up time requirement on 14,3,2,1.0 relative to the clock LOW-TO-HIGH transition is the longer of (1) the set-up time prior to
clock L-+ Hand (2) the sum of the set-up time prior to clock H -+ L and the clock LOW time.

wr=.

8-96

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203 GUARANTEED COMMERCIAL RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT/DECREMENT BY ONE OR TWO INSTRUCTIONS (SF3, SF4)
TO
FROM

N

OVR

DA.
DB

WRITE

010 0• 3

SIOo

SI03

SIOo
PARITY

74

61

67

28

78

58

-

35

59

65

-

35

28

27

-

-

62

54

-

41

65

23

30

38

Y

C n +4

G.P

Z

A. BAddr

67

55

52

DA.DB

58

50

40

Cn

33

18

18-0

64

64

50

72

61

62

-

34

26*

50*

62*

74*

CP

58

42

43

61

54

58

22

22

37

54

60

SIOo, SI03

23

-

29

-

-

44

44

44

44

-

44

-

~

58

50

40

65

54

58

-

19

44

-

29

~

-

-

35

59

65

-

NOTES:
1. A· -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
3. Standard Functions: See Table 2, Increment SF4: F = S + 1 + C n and Decrement SF3: F = S - 2 + C n

MULTIPLY INSTRUCTIONS (SFO, SF2, SF6)
TO
FROM

G,P

Z

N

OVR

DA,
DB

WRITE

010 0• 3

SIOo

(55)

-

(67)

(28)

-

(55)

(52)

-

-

(28)

(67)

-

(58)

(50)

-

(54)

(58)

IS

(58)

(50)

(40)

-

-

LSS

(58)

(50)

(40)

-

-

MSS

35

(18)

-

(28)

(27)

(23)

.(33)

(18)

-

-

IS

-

-

-

-

(41)

MSS

-

(41)

(52)

-

(61)

(55)

(23)

88

88

-

(26)*

73*

-

-

-

(26)*

73*

(34)

(26)*

73*

(54)

(58)

(22)

-

(22)

(37)

-

-

(22)

-

(22)

(37)

(22)

(22)

73

58

58

-

-

-

-

-

-

43
43

Y

C n +4

MSS

(67)

IS

(67)

LSS

SLICE

A, B Addr

DA,DB

Cn

18- 0

CP

Z
SIOo, SI03

LSS

(33)

(18)

MSS

94

75

-

IS

94

75

71

-

LSS

94

75

71

30

MSS

(58)

(42)

-

IS

(58)

(42)

(43)

-

LSS

94

75

71

30

MSS

64

45

-

IS

64

45

41

-

LSS

-

-

-

(23)

-

-

Any_

-

-

-

(28)

-

(41)
(35)
(35)
(35)

(23)

-

-

NOTES:
1. A· _. means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output. An "*" shown without a number means the output is disabled by the input or it is enabled but the delay to correct
data is determined by something else.
3. A number in parentheses means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instructions Test.
4. Unsigned Multiply
Two's Complement Multiply
Two's Complement Multiply Last Cycle
SFO: F=S+C n if Z=O
SF2: F=S+C n if Z=O
SF6: F=S+C n if Z=O
F=S+R+C n if Z=1
F=R+S+C n if Z=1
F=S - R - 1 +Cn if Z=1
Y=Log. F/2
Y=Log. F/2
Y=Log. F/2
a = Log. 0/2
a = Log. 0/2
0 = Log. 0/2
Y 3 =C n +4 (MSS)
Y3 =F3 ED OVR (MSS)
Y3 = OVR ED (MSS)
Z=Oo (LSS)
Z=Oo (LSS)
Z=Oo (LSS)

8-97

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

IDT39C203 GUARANTEED COMMERCIAL RANGE PERFORMANCE DIVIDE INSTRUCTIONS
(SFA, SFC, SFE)
TO
FROM

A, B Addr

DA,DB

Cn

18- 0

CP

Z
SIOo. SI03

Z

N

OVR

DA,
DB

WRITE!
MSS

-

SLICE

Y

Cn+4

G,P

MSS

(67)

61/(55)

-

(74)/-

(61)

(67)

(28)

IS

(67)

(55)

(52)

(74)/-

(67)

(55)

(52)

(74)/-

-

(28)

LSS

-

MSS

(58)

55/(50)

-

(65)/-

(54)

(58)

-

(28)

-

IS

(58)

(50)

(40)

(65)/-

LSS

(58)

(50)

(40)

(65)/-

-

-

MSS

(33)

33/(18)

(35)/-

(28)

(27)

IS

(33)

(18)

(35)/-

-

-

(35)/-

-

-

-

(72)/29

(61)177

(62)177

-

LSS

(33)

(18)

MSS

(64)/84

75/68

-

-

-

010 0 ,3

SI03

-

62

-

62
62
59
59
59
32
30

-

30

(26)*

63/83*

(26)*

(62)/83*

IS

(64)/84

(64)/68

(50)170

(72)/-

-

-

LSS

(64)/84

(64)/68

(50)70

(72)/-

-

-

-

-

(34)

(26)*

(62)/83*

MSS

(58)/85

46/69

-

(61)/30

(54)/66

(58)/66

(22)

-

(22)

(54)179*

(22)

(54)

(22)

(54)

IS

(58)

(42)

(43)

(61)/-

(58)

(42)

(43)

(61)/-

-

MSS

-

-

-

(22)

LSS

-

-

-

-

-

IS

-/55

-/39

-/41

-

LSS

-/55

-/39

-/41

-

-

-

Any

(23)

-

-

-

-

-

-

-

(22)

-

-

-

-

-

-/54

-

-

-/54

-

NOTES:
1. A" - " means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output. This speCification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two
Instruction Test.
3. A number is parentheses means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This speCification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
4. If two delays are given. the first is for 1st divide and normalization; the second is for two's complement divide and two·s complement divide
correction.
5. Double Length Normalize and First Divide Op Two's Complement Divide
Two's Complement Divide Correction and Remainder
SFA: F=S+C n
SFC: F=R+S+Cn ifZ=O
SFE: F=R+S+C n if Z=O
Y=Log.2F
F=S-R-1+Cn ifZ=1
F=S-R-1 + C n if Z= 1
Q=Log.20
,
Y=Log.2F
Y=F
0=Log.20
SI03 = F3 E9 R (MSS)
O=Log.gO_.
Z = 11 E9 R3(MSS) from previous cycle
Cn+4 = F3 E9 F2 (MSS)
SIO =T3(MSS)
Z = R3 E9 3 (MSS) from previous cycle
OVR
ffi (MSS)
Z=QO O I ~Q3lb
~ ~

=.Ez

£J

II

8-98

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203 GUARANTEED COMMERCIAL RANGE PERFORMANCE BCD INSTRUCTIONS
(SF1,SF7,SF9,SFB,SFD,SF~
TO
FROM

A, B Addr

DA,DB

Co

16 - 0

CP

S100-3

SLICE

y

Cn +4

MSS

72

60

IS

72

60

G,P

DA,
DB

WRITE

QIO O,3

510 0

510 3

68

(28)

55

(62)

(78)

(28)

-

-

-

-

55

(62)

(78)

-

55

(62)

(78)

45

(59)

(65)

-

-

45

(59)

(65)

-

-

45

(59)

(65)

30

36

44

30

36

44

Z

N

OVR

-

(74)

68

55

(74)

-

LSS

72

60

55

(74)

-

-

(28)

MSS

61

52

-

(65)

59

59

IS

61

52

48

(65)

-

-

-

LSS

61

52

48

(65)

-

-

-

MSS

36

23

37

33

33

-

IS

36

23

-

37

-

-

37

-

(72)/45'

62

(62)

IS

72

(64)

63

(72)/45'

-

-

LSS

72

(64)

63

(72)/45'

-

-

-

MSS

62

53

-

68/30'

62

62

(22)

IS

62

53

50

68/30'

62

53

50

68/30'

-

(22)

LSS
Any

(23)

-

-

-

-

LSS

36

23

MSS

72

(64)

-

SIOo
PARITY

-

30

36

44

(26)

(50)

(62)

(74)

-

(26)

(50)

(62)

(74)

(34)

(26)

(50)

(62)

(74)

(22)

39

60

65

(22)

39

60

65

(22)

-

(22)

39

60

65

-

-

-

-

-

-

NOTES:
1. Binary-to-BCD and multi precision Binary-to-BCD instructions only.
2. BCD-to-binary conversion (SF1), Binary-to-BCD conversion (SF9). BCD subtract (SFD. SFF). BCD divide by two (SF7). BCD add (SFB)
3. A number in parentheses means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions
Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-99

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

IDT39C203 GUARANTEED COMMERCIAL RANGE PERFORMANCE
SIGN MAGNITUDE TO lWO'S COMPLEMENT CONVERSION (SFS)
TO
FROM

A, BAddr

DA,DB

Cn

18 - 0

CP

Z
SIOo, SI03

G,P

Z

N

OVR

DA,
DB

WRITE

010 0,3

-

-

SLICE

Y

MSS

97

84

-

45

89

89

(28)

IS

(67)

(55)

(52)·

-

(28)

C n +4

LSS

(67)

(55)

(52)

-

-

-

MSS

94

79

-

40

84

84

IS

(58)

(50)

(40)

-

-

32

(27)

-

-

-

-

-

-

-

(28)

5103
105
(62)
(62)
100

LSS

(58)

(50)

(40)

MSS

(33)

(18)

-

IS

(33)

(18)

-

LSS

(33)

(18)

-

-

MSS

85

67

-

28

82

73

-

88·

85

67

63

-

(26)

88·

85

67

63

-

-

-

LSS

-

-

(26)

IS

-

(34)

(26)

88·

MSS

94

79

-

40

84

84

(22)

(22)

100

IS

(58)

(42)

(43)

-

-

-

(22)

-

(22)

(54)

(22)

(54)

-

60

-

-

-

-

-

-

-

LSS

(58)

(42)

(43)

MSS

-

-

-

IS

57

39

35

LSS

57

39

35

Any

(23)

-

-

-

-

(22)

-

-

(59)
(59)
(30)
(30)
(30)

60

NOTES:
1. A" - • means the delay path does not exist.
2. An " •• means the output is enabled or disabled by the input. See enable and disable times. A number shown with an " •• is the delay to correct
data on an enabled output. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or
Two Instruction Test.
3. A number in parentheses means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table. This speci
fication is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
4. SF5:F=~+CnifZ=0,
Y3=S3EBF3 (MSS),
Q=O
F=S+Cn ifZ=1,
Z=S3(MSS),
N=F3 ifZ=O
N =F3 EBS3 if Z= 1

8-100

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

IDT39C203 COMMERCIAL RANGE PERFORMANCE SINGLE LENGTH NORMALIZATION (SF8)
TO
FROM

A, B Addr

DA,DB

Cn

18- 0

CP
SIOo, SI0 3

SLICE

Y

MSS

(67)

-

IS

(67)

(55)

LSS

(67)

(55)

C n +4

G,P

DA,
DB

WRITE

QIO o, 3

510 3

(28)

-

-

(62)

-

-

-

-

-

-

(59)

--

-

_L30)

-

-

-

(30)

(26)

(62)*

(26)
·(26)

(62)*

Z

N

OVR

-

-

(52)

-

-

-

(52)

-

-

(28)

-

-

(28)

-

MSS

(58)

-

-

IS

(58)

(50)

(40)

-

LSS

(58)

(50)

(40)

-

MSS

(33)

-

-

-

-

24

24

-

IS

(33)

(18)

LSS

(33)

(18)

-

MSS

(64)

37

-

29

IS

(64)

(64)

(50)

29

-

-

LSS

(641

~641

(50)

29

-

-

MSS

(58)

29

-

30

26

29

(22)

IS

(58)

(42)

(43)

30

-

(22)

LSS

(58)

(42)

(43)

30

-

(22)

Any

(23)

-

-

-

-

-

-

(34)

-

-

(62)

-

(62)
(59)
(59)

(30)
(62)*

(22)

(54)

(22)

(54)

(22)

(54)

-

-

NOTES:
1. A· -" means the delay path does not exist.
2. An .*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an .*" is the delay to correct
data on an enabled output. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or
Two Instruction Test.
3. A number is parantheses means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.
4.

SF8: F=S+Cn
N=03 (MSS)
Y=F
O=LOG 20

Cn~

=- ~ §? 02 (MSS)

OVR=02

E9

Z=00010203

8-101

01(MSS)

Ell
,I

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203 GUARANTEED MILITARY RANGE
PERFORMANCE

Table 10_ Enable/Disable Times All Functions (1)
FROM

TO

ENABLE

DISABLE

Dry

Y

25

21

01:a

DB

25

21

EA

DA

25

21

la

SIO

25

21

la

010

38

38

Ie. 7. 6. 5

010

38

38

14 3 2 1 0

010

38

35

The tables below specify the guaranteed performance of the
IDT39C2030verthe military operating range of-55°C to + 125°C
with Vcc from 4.5 to 5.5V. All data are in nanoseconds, with inputs
switching between 0 and 3V at WIns and measurements made at
1.5V. All outputs have maximum DC load.

Table 9. Clock and Write Pulse Characteristics All Functions
Minimum Clock Low Time

30ns

Minimum Clock High Time

30ns

Minimum Time CP and ~ both Low to Write

30ns

[SS
WFiiiE"
30
25
NOTE:
1. C L = 5.0pF for output disable tests. Measurement is made to a
0.5V change on the output.

Table 11. Set-up and Hold Times All Functions
HIGH-TO-LOW

LOW-TO-HIGH

t pwL

WITH RESPECT TO

SET-UP

HOLD

Y

FROM

CP

Don't Care

Don't Care

Wi: HIGH
Wi: LOW

CP

15

CP

Don't Care

Don't Care

A, B Source

CP

20

3

B Destination

CP

6

01~.3

CP

Don't Care

Don't Care

la. 7. 6. 5

CP

12

-

TEN' HIGH

CP

24

TEN LOW

CP

Don't Care

Don't Care

14.3.2.1.0

CP

18

-

I
I

SET-UP

HOLD

14

3

COMMENTS
Store Y in RAM/O (1)

0

Prevent Writing

I

15

0

Write into RAM

I

Don't Care

Don't Care

Latch Data from RAM Out

3

Write Data into B Address

TpWL

TpWL

I
I

3

Shift

0

Write into

0

Prevent Writing into

21

0

Write into

a

32

0

Write into

0(2)

TpwL

I
I

a

17
20

0(2)

a

NOTES:
1. The internal V-bus to RAM set-up condition will be met 5ns after valid Y output (OE y= L)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing.
3. Fer a!! ether ::et·up conditions not specified in this tabie, the sel-up time should be the delay to stable Y output plus the Y to RAM internal set-up
time. Even if the RAM is not being loaded, this set-up condition ensures valid writing into the register and sign compare flip-flop.
4. ~ controls writing into the RAM. lEN controls writing into and, indirectly, controls WE through the WRITE/MSS output. To prevent writing, JE1iJ and
Wi: must go HIGH during the entire clock LOW time. They may go LOW after the clock has gone LOW to cause a write, provided the WE LOW and
TEN LOW set-up times are met. Having gone LOW, they should. not be returned HIGH until after the clock has gone HIGH.
5. A and B addresses must be set up prior to the clock HIGH-TO-LOW transition to latch data at the RAM output.
6. Writing occurs when CP and WE' are both LOW. The B address should be stable during this entire period.
7. Because la.7,6.5 controls the writing or not writing of data into RAM and 0, they should be stable during the entire clock LOW time unless lEN is HIGH,
which prevents writing.
8. The set-up time prior to the clock LOW-TO-HIGH transition occurs in parallel with the set-up time priorto the clock HIGH-TO-LOW transition and the clock
LOW time. The actual set-up time requirement on 14.3.2.1.0 relative to the clock LOW-TO-HIGH transition is the longer of (1) the set-up time prior to
clock L -+ Hand (2) the sum of the set-up time prior to clock H -+ L and the clock LOW time.

a

a

8-102

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203 GUARANTEED MILITARY RANGE PERFORMANCE
STANDARD FUNCTIONS AND INCREMENT/DECREMENT BY ONE OR TWO INSTRUCTIONS (SF3. SF4)
TO
FROM

OVR

DA,
DB

WRITE

010 0 ,3

68

67

28

-

55

58

-

Y

C n +4

G,P

Z

N

A, B Addr

70

58

52

78

DA,DB

60

52

40

~6

en

35

19

-

41

31

29

Is-o

72

69

56

80

71

69

-

CP

60

42

43

67

55

58

22

SIOo, SI03

26

-

-

29

-

-

~

44

-

44

44

44

44

D:

60

52

40

66

55

58

-

SIOo
PARITY

SIOo

SI03

-

47

71

84

-

35

61

74

23

33

40

36

26*

58*

75*

89*

-

22

41

61

66

-

29

19

-

-

-

44

-

35

61

74

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output.
;'
3. Standard Functions: See Table 2, Increment SF4: F = S + 1 + C n and Decrement SF3: F = S - 2 + Cn

MULTIPLY INSTRUCTIONS (SFO, SF2 SF6)
TO
FROM

A, B Addr

DA,DB

Cn

Is-o

CP

Z
SIOo, SI03

G,P

Z

N

OVR

-DA,
DB

WRITE

010 0 ,3

SIOo

-

-

(47)

-

(47)

SLICE

Y

MSS

(58)
(58)

-

-

(68)

(67)

IS

(70)
(70)

(52)

-

-

LSS

(70)

(58)

(52)

(28)

(52)
(52)

(55)

(58)

-

(40)

-

-

(40)

MSS

40

(19)

-

(31)

(29)

-

-

98

98

-

-

-

(52)

-

-

LSS

(60)
(60)
(60)

-

-

MSS
IS

-

-

(28)
(28)

C n +4

-

IS

(35)

(19)

LSS

(35)

(19)

MSS

108

84

-

IS

108

84

80

-

LSS

108

84

80

33

-

-

MSS

62
(60)

(42)
(42)

-

-

(55)

(58)

IS

(43)

-

-

-

-

-

-

-

(35)

-

(23)

(35)
(23)

-

-

(23)

(26)

81*

(26)

81*

(36)

(26)

81*

(22)

-

(22)

-

(22)
(22)

(41)
82

LSS

109

85

79

34

-

(22)

-

(22)

75

51

-

-

-

MSS

65

65

-

IS

75

51

47

-

-

-

Any

(26)

-

-

-

LSS

-

-

-

-

-

-

-

-

-

(47)
(35)

(41)

48
48

-

NOTES:
1. A" - " means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or
Two Instruction Test.
3. A number in parentheses means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. Unsigned Multiply
Two's Complement Multiply
Two's Complement Multiply Last Cycle
SFO: F=S+C n if Z=O
SF2: F=S+C n if Z=O
SF6: F=S+C n if Z=O
F=S+R+C n ifZ=1
F=R+S+C n ifZ=1
F=S-R-1 +C n ifZ=1
Y=Log. F/2
Y=Log. F/2
Y=Log. F/2
0= Log. 0/2
0 = Log. 0/2
0 = Log. 0/2
Y3 =C n +4 (MSS)
Y3 =F3 EB OVR (MSS)
Y3 = OVA EB F3(MSS)
Z=Oo (LSS)
Z=Oo (LSS)
Z=Oo (LSS)

8-103

IDT39C203/A 4·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203 GUARANTEED MILITARY RANGE PERFORMANCE DIVIDE INSTRUCTIONS (SFA, SFC, SFE)
TO
FROM
SLICE

Y

C n +4

G,P

Z

N

OVR

DA,
DB

WRITE

010 0 ,3

SI03

MSS
IS

(70)
(70)

72/(58)
(58)

-

(78)/(78)/-

(68)

(67)

(58)

(52)

(78)/-

(71)

66/(52)

-

(66)/-

(55)

(58)

-

(60)

(66)/(66)/-

-

-

~6QL

(40)
(40)

-

LSS
MSS

(52)
(52)

-

(61)

IS

-

-

(35)

37/(19)

-

(41)/-

(31)

(29)

-

-

-

MSS

(70)
(60)

-

-

LSS

-

(28)
(28)

(71)

(52)

Cn

IS

(35)

(19)

-

(41)/-

-

-

-

LSS

(35)

(19)

-

-

(71)/91

(69)/91

(56)/79
J5~9

-

-

(7W96

(80)/(80)/-

-

-

(60)/97
(60)

51/80
(42)

(58)/74

(43)

(67)/34
(67)/-

(55)/74

CP

LSS
MSS
IS

89/79
(69)/79
(6 91179

(80)/33

18- 0

(72)/96
(72)/96

-

(41)/-

MSS
IS

LSS

(60)

(42)

(43)

(67)/-

-

-

-

-

-

Z

MSS
IS

-/63

-/46
-/46

-/46
-/46

-

-

-

-

A. BAddr

DA,DB

LSS
SIOo. SI03

Any

-/63
(26)

-

-

(28)

-

-

-

(71)

(61)
(61)
36

-

-

(33)

(26)

76/98

-

(36)

(26)
(26)

(75)198*

(22)
(22)

-

(22)
(22)

(61)/93
(61)

(22)

-

(22)

(61)

-

-

-

-

-

-

-

-

-

-

(33)

(75)/98*

-

-

-/65
-/65

-

-

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the output is enabled or disabled by the input. See enable and disable times. A number shown with an "." is the delay to correct
data on an enabled output. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two
Instruction Test.
3. A number in parentheses means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. Double Length Normalize and First Divide Op
Two's Complement Divide
Two's Complement Divide Correction and Remainder
SFA: F=S+C n
SFC: F=R+S+C n if 2=0
SFE: F=R+S+C n if 2=0
Y=Log.2F
F=S-R-1+C n if 2=1
F=S-R-1+C1, if 2=1
0=Log.20
Y=Log.2F
Y=F
SI03 =F3$ R3 (MSS)
O=Lo~
0=Log.20
C n +4 = F3$ F2 (MSS)
SlOp = F3~ R3(MSS)
2= F3 $ R3(MSS) from previous cycle
OVR =.Ez ffi F1 (MSS)
2 = ~ EB 3 (MSS) from
2=00Q10"20311, ~ ~ 1=3
prevIous cycle

8-104

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

IDT39C203 GUARANTEED MILITARY RANGE PERFORMANCE BCD INSTRUCTIONS
(SF1,SF7,SF9,SFB,SFD,SF~
TO
FROM

A. B Addr

DA.DB

en
18- 0

CP

S100-3

SLICE

y

C n +4

MSS

75

65

IS

75

65

G,P

DA.
DB

WRITE

70

(28)
(28)

-

Z

N

OVR

-

(78)

70

57

(78)

-

LSS

75

65

57

(78)

-

-

(28)

-

MSS

62

54

-

70

64

64

-

IS

62

54

50

70

-

-

-

-

LSS

62

54

50

70

-

-

MSS

39

26

(41)

37

37

IS

39

26

-

(41)

-

LSS

39

26

MSS

76

72

QIO o• 3

SIO o

SI0 3

SIOo
PARITY

-

60

(71)

(84)

-

60

(71)

(84)

60

(71)

(84)

-

50

(61)

(74)

50

(61)

(74)

-

50

(61)

(74)

34

39

48

34

39

48

-

-

34

39

48

(26)

(58)

(75)

(89)

-

(41)

-

-

(80)/50'

73

73

-

-

IS

76

72

70

(80)/50'

-

-

(26)

(58)

(75)

(89)

LSS

76

72

70

(80)/50'

-

-

-

-

(36)

(26)

(58)

(75)

(89)

MSS

67

54

-

70/34'

66

66

(22)

-

(22)

43

63

74

IS

67

54

52

70/34'

43

63

74

54

52

70/34'

(22)

-

(22)

67

-

(22)

LSS

(22)

43

63

74

Any

(26)

-

-

-

-

-

-

-

-

-

-

-

NOTES:
1. Binary-to-BCD and multiprecision Binary-to-BCD instructions only.
2. BCD-to-binary conversion (SF1). Binary-to-BCD conversion (SF9). BCD subtract (SFD. SFF). BCD divide by two (SF7). BCD add (SFB)
3. A number is parentheses means the delay path is the same as specified in the Standard Functions and Increment by One or Two Instructions Table. This
specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or Two Instruction Test.

8-105

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203!A 4·BIT CMOS MICROPROCESSOR SLICE

IDT39C203 GUARANTEED MILITARY RANGE PERFORMANCE
SIGN MAGNITUDE TO TWO'S COMPLEMENT CONVERSION (SFS)
TO
FROM
SLICE

A, B Addr

DA.DB

Cn

18 - 0

CP

Z
SIOo• SI03

Y

C n +4

G,'P

Z

N

OVR

DA,
DB

WRITE!
MSS

-

-

MSS

114

98

-

52

106

106

(28)

IS

(70)

(58)

(52)

-

-

(28)

LSS

(70)

(58)

(52)

(28)

-

MSS

108

92

-

-

-

46

101

101

-

IS

(60)

(52)

(40)

-

-

-

-

-

-

-

35

(29)

-

-

-

-

-

-

LSS

(60)

(52)

(40)

MSS

36

(19)

-

-

IS

(35)

(19)

LSS

(35)

(19)

MSS

98

79

-

33

97

88

-

IS

98

79

73

-

-

LSS

98

79

73

-

-

-

-

MSS

108

92

-

46

101

101

(22)

IS

(60)

(42)

(43)

-

-

(22)

-

-

-

-

LSS

(60)

(42)

(43)

MSS

-

-

-

IS

65

46

40

LSS

65

46

40

Any

(26)

-

-

-

-

-

-

(22)

-

010 0,3

SI03
128
(71)
(71)
112

-

(61)

-

(33)

-

(33)

-

(33)

(61)

(26)

109*

-

(26)

109*

(36)

(26)

109*

-

(22)

122

(22)

(61)

(22)

(61)

-

-

-

-

76

-

-

-

76

NOTES:
1. A" -" means the delay path does not exist.
2. An "*" means the output Is enabled or disabled by the input. See enable and disable times. A number shown with an "*" is the delay to correct
data on an enabled output. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or
Two Instruction Test.
3. A number Is parentheses means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. SF5: F=S+Cn if Z=O.
Y3 =S3(B F3(MSS).
0=0
F=~+Cn if Z=1.
Z=S3(MSS).
N=F3 if Z=O
Y=F
N=F3 (BS3 if Z=1

8-106

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203 GUARANTEED MILITARY RANGE PERFORMANCE SINGLE LENGTH NORMALIZATION (SF8)
TO
FROM

A, B Addr

DA,DB

Cn

18 - 0

CP

Z
SIOo, SI03

GtP

Z

N

OVR

OAt
DB

WRITE

QIO O,3

SI03

-

-

(28)

LSS

(70)

(58)

(52)

(28)

MSS

(60)

-

-

IS

(60)

(52)

(40)

-

-

-

(71)

(52)

-

-

(58)

-

(28)

(70)

-

SLICE

Y

MSS

(70)

IS

C n +4

LSS

(60)

(52)

(40)

MSS

(35)

-

-

IS

(35)

(19)

-

LSS

(35)

(19)

MSS

(72)

47

-

-

-

-

-

(71)
(61)
(61)

-

(61)-

-

(33)

(26)

(75)·

-

-

33

27

27

-

-

(26)

(75)·

(36)

(26)

(75)·

(22)

(61)

(22)

(61)

(22)

(61)

-

-

-

-

IS

(72)

(69)

(56)

33

-

LSS

(72)

(69)

(56)

33

-

-

-

MSS

(60)

31

-

34

26

31

(22)

IS

(60)

(42)

(43)

34

-

-

(22)

LSS

(60)

(42)

(43)

34

-

(22)

MSS

-

-

-

-

-

-

LSS

-

-

-

IS
Any

(26)

-

-

-

-

(71)

(33)
(33)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

NOTES:
1. A· _. means the delay path does not exist.
2. An ••• means the output is enabled or disabled by the input. See enable and disable times. A number shown with an ••• is the delay to correct
data on an enabled output. This specification is not tested but is guaranteed by correlation to the Standard Function and Increment by One or
Two Instruction Test.
3. A number in parentheses means the delay is the same as in the Standard Functions and Increment by One or Two Instructions Table.
4. SF8: F=S+C n
C n +4 = ~ ~ O 2 (MSS)
OVR=02 EB 0 1 (MSS)
N=03 (MSS)
Z=Q OQ 1 Q 2 Q 3
Y=F
0=Log.20

8-107

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C203INPUT/OUTPUT
INTERFACE CIRCUITRY
Vcc
ESD
PROTECTION

OUTPUTS

INPUTS

Figure 4. Output Structure (All Outputs)

Figure 3. Input Structure (All Inputs)

OUTPUTS

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input TIming Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

WIns
1.5V
1.5V
See Figure 6
Figure 5. Open Drain Structure

TEST LOAD CIRCUIT

SWITCH POSITION
TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to loUT of the
Pulse Generator

Figure 6. Switching Test Circuits (All Outputs)

SWITCHING WAVEFORMS
INPUTS 3.0V

OV----..J.
CLOCK 3.0V

OV
CLOCK
TO
OUTPUT I_------I~
DELAY
OUTPUTS

8-108

IDT39C203/A 4-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

39C2D3
Device Type

x

x

Speed

Process/
Temperature

y:~k

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

L

Plastic DIP
Sidebraze DIP
Leadless Chip Carrier

Blank
A

Standard Speed 4-Bit Slice
High-Speed 4-Bit Slice

P

L..------------i C

8-109

Commercial (DOC to +7D°C)

MICROSUCE ™ PRODUCT
operation. New incoming data is written into the 4-bit RAM word
selected by the B address. The D inputs are used to load new data
into the device.
Featured ~re two separate output ports which allow any two 4-bit
words to be read from these outputs simultaneously. Also featured
is a 4-bit latch for each of the two output ports with a common Latch
Enable (h§..input being used to control all eight latches. Two Write
Enable (WE) inputs are designed such that Write Enable 1 (WE1)
and Latch Enable (LE) inputs can be connected to the RAM to operate in an edge-triggered mode. The Write Enable inputs control
the writing of new data into the RAM. Data is written into the B
address field when both Write Enables are LOW. If either of the
Write Enables are HIGH, no data is written into the RAM.
Three-state outputs allow several devices to be easily cascaded
for increased memory size. When OEAinput is HIGH, the A output
port is in the high i~dance mode. The same respective operation occurs for the OEB input.
The IDT39C707s function identically to the IDT39C705s, except
each output port ha~separate Latch Enable (LE) input. Also, an
extra Write Enable (WE) may be connected directly to the lEN of
the IDT39C203/A for improved cycle times when compared to the
IDT39C705s. The WEIBLE input can then be connected directly to
the system clock.
These performance-enhanced, pin-compatible replacements
for all respective versions of the 29705s and 29707s are fabricated
using IDT's high-speed, high-reliability CEMOS technology.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

FEATURES:
• Fast
- Available in either industry-standard speed or 20% speed
upgraded versions
• Low-power CEMOS ™
- Military: 50mA (max.)
- Commercial: 40mA (max.)
• 16-word x 4-bit dual-port CMOS RAM
• Non-inverting data output with respect to data input
• Easily cascadable with separate Write Enables
• Separate 4-bit latches with enables for each output port
(IDT39C707/A has separate output control)
• IDT39C705A1B pin-compatible to all versions of the 29705
• IDT39C707/A pin-compatible to all versions of the 29707
• Available in CERDlP, Plastic DIP, LCC and SOIC
• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
The IDT39C705s are high-performance 16-word-by-4-bit dualport RAMs. Addressing any of the 16 words is performed via the
4-bit A address field with the data appearing on the A output port.
The same respective operation holds true for the B address input!
output port and can happen simultaneously with the A port

FUNCTIONAL BLOCK DIAGRAM
IDT39C70SAlB

A3
A2
A1

A
A
ADDRESS
DECODER

Ao

't'%~~~o~Jt;;3'T

ADDRESS

8 {

ADDRESS

}
A-PORT

WE

8
ADDRESS
DECODER

B-PORT

WE 1
WE 2

ALo
OEA

LE
A-DATA
4-81T
LATCH

8-DATA
4-81T
LATCH

CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Imegrated DevIce Technology. Inc.

DECEMBER 1987
DSC-9007/-

8-110

IDT39C705A/B AND IDT39C707/A
16-WORD-BV-4-BIT DUAL-PORT RAM

MILITARV AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM
IDT39C707/A

A ''1;;f,..~~~o~i-.t;~1T

A

ADDRESS
DECODER

ADDRESS

}

A-PORT

B{
B
ADDRESS
DECODER

ADDRESS

WE

B-PORT
.-------WE,
D------WE2

ALE
.....- - - WEIBLE
A-DATA
4-BIT
LATCH

B-DATA
4-BIT
LATCH

PIN CONFIGURATIONS
IDT39C705A/B

IDT39C707/A

D,

Vee

D,

Do

D2
D3
WE 2
Ao

Do

WE,

eo

s,
Bz

WE,
Bo
B,
B2
B3

A,
A2

8.3

ALO

ALE
WEIBLE

VBo
VAo
VB,

A3
OE A
OE B
VA3
VB3

VA,
GND

VA 2
VB2

VA,
GND

LE

VBo
VAo
VB,

DIP
TOP VIEW

DIP/SOIC
TOP VIEW

oluJ
:;0 o~o"'c5'

m

INDE
:1 5

0

0

~ ~ ~ ~ ~8 ~ ~25C

] 6

]7
]8
]9

INDE

L28";1

24[
23[
22[
2'[
20[
,9C

:1 ,0
] "
1213 14 15 1617 '8
nr:nnnnn

~ ~ ~ L,! ~8 ~ ~

B, :1 5
B2
B3
ALE
WEIBLE
VBo

VAo

] 6

] 7
:1 8

L28-1

:1 9

] '0
:1 "

•

25[.
24[
23r:
22[
2,r:
20r:
,9[

'2'3 '4 '5 '617 '8

nnnnnnn

oJ c:f@ ~ ';mM ct.M
>->-eJ>->->->LCC
TOP VIEW

LCC
TOP VIEW

8-111

. _ - - - - - - - - - - .._.. _._._--_ _._._--...

....-

IDT39C70SA/B AND IDT39C707/A
16-WORD·BY-4·BIT DUAL-PORT RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
I/O

DESCRIPTION

Ao-A3

I

Four address inputs at the A address decoder which select one of the 16 memory words for output through the
Aport.

8o- B3

I

(Four address inputs at the B address decoder which select one of the 16 memory words for output through the
B port. The B address field also selects the word into which new data is written.

PIN NAME

00- D3

I

Four inputs for writing new data into the RAM.

YA o-YA 3

0

Four three-state A Data Latch outputs which display A port data and also allow several devices to be easily cascaded.

Y8o-Y~

0

Four three-state B Data Latch outputs which display B port data and also allow several devices to be easily cascaded.

LE

I

The LE input controls the RAM A Data Latch and B Data Latch. When the LE input is HIGH, the latches are open
(transparent) and the output data from the RAM is selected by the A and B address fields. When LE is LOW, the latches
are closed and they retain the last data read from the RAM independent of changes in the A and B address fields
(IDT39C705A/B only).

ALo

I

This input is used to force the A Data Latch. When ALO input is HIGH, the A L~tches operate in their normal fashion.
Once the A Latches are forced LOW they remain LOW independent of the ALO input if the latches are closed
(IDT39C705A1B only).

ALE

I

This input controls the A Data Latch. When ALE is HIGH, the latch is open (transparent) and the data from the RAM, as
selected by the A address field, is present at the A output. When ALE is LOW, the latch is closed and retains the last
data read from the RAM independent of changes in the A address field (IDT39C707/A only).

WE 1 , WE 2

I

When both Write Enables are LOW, new data can be written into the word selected by the B address fields. If either
Write Enable input is HIGH, no new data can be written into the memory.

WEIBLE

I

This input controls the writing of new data into the RAM and display of data at the B Data Latch output. When WEIBLE
is LOW together with WE 1 and WE2, new data is written into the word selected b.Y.!tle B address fields. When WEIBLE
or any other Write Enable input is HIGH, no data is written into the RAM. When WEIBLE is HIGH, the B Latch is open
(transparent) and, when this input is LOW, the B Data Latch is closed (IDT39C707/A only) .

OE A

I

When the A port output enable is LOW, data at the A Data Latch inputs in presented at the YAI outputs. When OEA is
HIGH, the YAI outputs are in the high-impedance (off) state.

OE B

I

When the B port output enable is LOW, data at the B Data Latch inputs is presented at the YB I outputs. When
HIGH, the YB I outputs are in the high-impedance (off) state.

OE B is

IDT39C70SA/B FUNCTION TABLES
VA READ CONTROL

WRITE CONTROL
WE 1

WE 2

FUNCTION

RAM OUTPUTS AT
DATA-LATCH INPUTS

INPUTS

A-PORT

B·PORT

L

L

Write D into B

A Data (A'" B)

Input Data

L

L

Write D into B

Input Data (A = B)

Input Data

X

H

No Write

A-Data

B-Data

H

X

No Write

A·Data

B-Data

H = HIGH
L = LOW
X = Don't Care

YA OUTPUT

FUNCTION

X

Z

High Impedance

X

L

ForceYA LOW

OE A

ALO

LE

H

X

L

L

L

H

H

A Port RAM Data

Latches Transparent
(Open)

L

H

L

NC

Latches Retain Data
(Closed)

H = HIGH
L = LOW
X = Don't Care

Z = High Impedance
NC = No Change

VB READ CONTROL
INPUTS
OE B

LE

YB OUTPUT

FUNCTION

H

X

Z

High Impedance

L

H

B Port RAM Data

Latches Transparent (Open)

L

L

NC

Latches Retain Data (Closed)

H = HIGH
L = LOW
X = Don't Care

Z = High Impedance
NC = No Change

8-112

IDT39C70SA/B AND IDT39C707/A
16-WORD-BY-4-BIT DUAL-PORT RAM

MILITARY Arm COMMERCIAL TEMPERATURE RANGES

IDT39C707/ A FUNCTION TABLES
VA READ CONTROL

WRITE CONTROL
WE1

WE2 WEIBLE

RAM OUTPUTS
AT LATCH INPUTS

FUNCTION

A PORT
L

L

L

INPUTS

B PORT

Write D into B A Data (A "1= B)

Input Data

X

X

H

No Write

A-Data

B-Data

X

H

X

No Write

A-Data

B-Data

H

X

X

No Write

A-Data

YA OUTPUT

ALE

H

X

Z

High Impedance

L

H

A Port RAM Data

Latches Transparent (Open)

L

L

NC

Latches Retain Data (Closed)

H = HIGH
L = LOW
X = Don't Care

B-Data

H = HIGH
L = LOW
X = Don't Care

FUNCTION

OE A

Z = High Impedance
NC = No Change

VB READ CONTROL
INPUTS
WEIBLE

H

X

Z

High Impedance

L

H

B Port RAM Data

Latches Transparent (Open)

L

L

NC

Latches Retain Data (Closed)

H = HIGH
L = LOW
X = Don't Care

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

FUNCTION

YB OUTPUT

OEe

Z = High Impedance
NC = No Change

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLVVOLTAGE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

GRADE
Military
Commercial

AMBIENT
TEMPERATURE

GND

-55°C to + 125°C

OV

5.0V ± 10%

O°C to +70°C

OV

5.0V ± 5%

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

CIN

Input CapaCitance

lOUT

DC Output Current

30

30

mA

COUT

Output CapaCitance

CAPACITANCE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

SYMBOL

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CONDITIONS

8-113

TYP.

UNIT

VIN = OV

5

pF

VOUT= OV

7

pF

NOTE:
1. This parameter is sampled and not 100% tested.

."

Vcc

IDT39C705A/B AND IDT39C707/A
16-WORD-BY-4-BIT DUAL-PORT RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
- TA = O°C to + 70°C
Vee = 5.0V ± 5% (Commercial)
Vee = 5.0V ± 10% (Military)
TA = -55·Cto +125°C
VLe = 0.2:J
VHe = Vee - 0.2V
MIN.

TYP.(2)

MAX.

UNIT

\IH

Input HIGH Level

Guaranteed Logic High Level (4)

2.0

-

-

V

~L

Input LOW Level

Guaranteed Logic Low Level (4)

-

0.8

V

IIH

Input HIGH Current

Vee = Max., VIN = Vee

0.1

5

J.lA

IlL

Input LOW Current

Vee = Max., \IN = GND

-

-0.1

-5

J.lA

VHe

Vee

-

SYMBOL

TEST CONDITIONS (1)

PARAMETER

IoH = -300J.lA
VOH

Vee = Min.
~N = ~H or\lL

Output HIGH Voltage

10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

4.3

-

-

GND

VLe

0.3

0.5

0.3

0.5

-0.1

-10

0.1

10

J.lA

-15

-

-

mA

10L = 300J.lA
VOL

Vee = Min.
VIN = 'vIH or'vlL

Output LOW Voltage

IOL = 20mA MIL.
IoL = 24mA COM'L.

V

V

Off State (High Impedance)
Output Current

Vee = Max.

Vo = OV

loz

OE = \lH

Vo = Vee Max.

los

Output Short Circuit Current

Vec = Min., VOUT = OV (3)

leeoH

Quiescent Power Supply Current
WE = H

Vee = Max.
VHe :5 VIH, VIL :5 VLe
fWE = 0, WE = H

-

3

5

mA

leeol

Quiescent Power Supply Current
WE = L

Vcc = Max.
"i-ie :5 VIH , VIL :5 \te
fWE = 0, WE = L

-

3

5

mA

ICCT

QUiescent Input Power Supply
Current (per Input @ TIL High) (5)

Vee = Max., ~N

-

0.3

0.5

Input

Vee = Max.
VHC :5 VIH, VIL :5 VLe
Outputs Open, OE = L

-

1.7

3.5

Dynamic Power Supply Current

MIL.

IceD

COM'L.

-

1.7

2.5

mAl
MHz

Vec = Max., fWE = 10MHz
Outputs Open, OE = L
WE = 50% Duty cycle
VHe :5 VIH , VIL :5 VLC

MIL.

-

20

40

COM'L.

-

20

30

MIL.

-

25

50

COM'L.

-

25

40

Icc

(6)

Total Power Supply Current

= 3.4V, fWE

Vee = Max.,fWE= 10MHz
Outputs Open, OE = L
WE' = 50% Duty cycle
VIH = 3.4V, VIL = O.4V

=0

mAl

mA

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vec = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These Input levels provide zero noise immunity and should only be static tested in a noise-free environment.
5. leeT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out leeoH' then dividing by the total number of inputs.
6. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS or TIL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
lee = ICCOH (WEH) + ICCOl (1 - WE H) + lecr (Nr x D H) + IceD
WE H =
DH =
Nr =
fWE =

(fwEl

Write duty cycle high period.
Data duty cycle TIL high period (VIN = 3.4V).
Number of dynamic inputs driven at TIL levels.
Write frequency.

8-114

IDT39C70SA/B AND IDT39C707/A
16-WORD-BY-4-BIT DUAL-PORT RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

3) Definition of input levels is very important. Since many inputs
may change coincidentally, significant noise at the device pins
may cause the VIL and VIH levels not to be met until the noise has
settled. To allow for this testing/board induced noise, lOT
recommends using VIL !> OV and VIH ;::: 3V for AC tests.
4) Device grounding is extremely important for proper device testing. The use of multi-layer performance boards with radial
decoupling between power and ground planes is required. The
ground plane must be sustained from the performance board to
the OUT interface board. All unused interconnect pins must be
properly connected to the ground pin. Heavy gauge stranded
wire should be used for power wiring and twisted pairs are
recommended to minimize inductance.

CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be taken
into account when testing high-speed CMOS devices in an
automatic environment. These are:
1) Proper decoupling at the test head is necessary. Placement of
the capacitor set and the value of capacitors used is critical in
reducing the potential erroneous failures resulting from large
Vcc current changes. Capacitor lead length must be short and
as close to the OUT power pins as possible.
2) All input pins should be connected to a voltage potential during
testing. If left floating, the device may begin to oscillate causing
Improper device operation and possible latchup.

AC ELECTRICAL CHARACTERISTICS
PARAMETERS

FROM

TEST CONDITIONS

TO

IDT39C70SA
IDT39C707
COM'L

IDT39C70SB
IDT39C707A

UNIT

MIL

COM'L.

MIL

25

30

20

24

ns

20

20

16

16

ns

20

20

16

16

ns

Access Time

A or B Address
Stable

YA Stable or
YB Stable

Turn-on Time

OEA or OE B LOW

YA or YB Stable

Turn-off Time

OEA or OE B HIGH

YAorYB Off

Reset Time

ALO LOW

YALOW

20

20

16

16

ns

Latch Enable Time

LE HIGH

YA and YB Stable

20

22

16

16

ns

WE, and WE2 LOW

YA orYB

LE

30

35

22

24

ns

D

YAorYB

LE

30

35

22

24

ns

Transparency

LE

= HIGH

c;. = 5pF

= HIGH
= HIGH

MINIMUM SETUP AND HOLD TIME
PARAMETERS

FROM

TEST CONDITIONS

TO

IDT39C70SA
IDT39C707
COM'L.

MIL

IDT39C70SB
IDT39C707A
COM'L

UNIT

MIL

Data Set-up Time

D Stable

Either WE HIGH

12

15

9

12

ns

Data Hold Time

Either WE

D Changing

0

0

0

0

ns

Address Set-up Time

B Stable

Both WE LOW

6

8

4

6

ns

Address Hold Time

Either WE HIGH

B Changing

0

0

0

0

ns

Latch Close Before
Write Begins

LE LOW

WE, LOW

WE 2 LOW

0

0

0

0

ns

LELOW

WE 2 LOW

WE, LOW

0

0

0

0

ns

Address Set-up
Before Latch Closes

A or B Stable

LELOW

12

15

9

12

ns

MINIMUM PULSE WIDTHS
PARAMETERS

INPUT

PULSE

TEST CONDITIONS

IDT39C70SA
IDT39C707
COM'L.

MIL

IDT39C70SB
IDT39C707A
COM'L

UNIT

MIL
ns

WE,

HIGH-LaW-HIGH

WE 2 LOW

15

15

12

12

WE2

HIGH-LaW-HIGH

WE, LOW

15

15

12

12

ns

A Latch Reset Pulse

ALO

HIGH-LaW-HIGH

15

15

12

12

ns

Latch Data Capture

LE

LOW-HIGH-LOW

15

18

12

12

ns

Write Pulse Width

NOTE:
The IDT39C705B1707A meet or exceed all the specifications of the IDT39C705A1707.

8-11S

IDT39C705AJB AND IDT39C707/A
16-WORO-BY-4-BIT DUAL-PORT RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS

TEST LOAD CIRCUITS

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND t03.0V

Wins
1.5V
1.5V
See Figure 1

TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All other Outputs

Open

DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to ZOUT of the
Pulse Generator

Figure 1. Switching Test Circuit

INPUT/OUTPUT INTERFACE CIRCUIT
Vcc
ESD
PROTECTION

INPUTS

OUTPUTS

Figure 2. Input Structure

Figure 3. Output Structure

ORDERING INFORMATION
IDT

xxxxxxx

x

Device Type/Speed

Process/
Temperature
Range

I

__ I

Blank

~B
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

P

D
L
SO

39C705A
-I 39C705B
39C707
39C707A

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

8-116

Commercial (ODC to

+ 70DC)

Military (-55 DC to + 125 DC)
Compliant to MIL-STD-883, Class B
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC (IDT39C705 only)

Standard Speed Dual-Port RAM
High-Speed Dual-Port RAM
Standard Speed Dual-Port RAM
High-Speed Dual-Port RAM

MICROSLICE 1M PROOUCT

FEATURES:

DESCRIPTION:

• Similar function to AMO's Am2925 bipolar controller with
improved speeds and output drive over full temperature and
voltage supply extremes
'
• Four microcode-controlled clock outputs allow clock cycle
length control for 15 to 30% increase in system throughput.
Microcode selects one of eight clock patterns from 3 to 10
oscillator cycles in length
• System controls for RUN/HALT and Single Step
- Switch-debounced inputs provide flexible halt controls
• Low input/output capacitance
- 6pF inputs (typ.)
- 8pF outputs (typ.)
• CMOS power levels (5}JW typo static)
• Available in 300 mil 24-pin plastic and ceramic THINDlP,
28-pin LCC and PLCC packages and CERPACK
• Both CMOS and TTL output compatible
• Substantially lower input current levels than AMO's bipolar
Am2900 series (5}JA max.)
• Military product compliant to MIL-STO-883, Class B

The IOT49C25/A are single-chip general purpose clock generator/drivers built using lOT's advanced CEMOS 1M, a dual metal
CMOS technology. It has microprogrammable clock cycle length to
provide significant speed-up over fixed clock cycle approaches and
meets a variety of system speed requirements.
The lOT49C25/A generate four different simultaneous cl.ock output waveforms tailored to meet the needs of the IOT3900 CMOS
family and other MOS and bipolar microprocessor-based systems.
One of eight cycle lengths may be generated under microprogram
control using the cycle length inputs, Ll, l.2 and l:3.
A buffered oscillator output, Fo, is provided for external system
timing in addition to the four microcode controlled clock outputs,
Cl, C2, C3 and C4.
System control functions include RUN, HALT, Single-Step, Initialize and Ready/Wait controls. In addition, the FIRST/LAST input
determines where a halt occurs and the Cx input determines the
end point timing of wait cycles. WAITACK indicates that the
IOT49C25/A are in a wait state.

---------------a
FUNCTIONAL BLOCK DIAGRAM

OSC------~

~------------------------------~.-------~

MICROCYCLE
CONTROL
LATCH

CONTROL
STATE
DECODER

FIRST/[AST

HALT
11UN
SSNC
SSNO

RUN/HALT
AND
SINGLE STEP
CONTROL

WAIT
CONTROL

J-------------------

WAIT ACK

~--------~----------------~

nW"ArrIT~RnE~Q~---------------------------------~

~--------------------------------~
cx--------------------------------------~

CEMOS and MICROSLICE are trademarks of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-4060/-

1987 Integrated Device Technology, Inc.

8-117

IDT49C25/A HIGH·PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX

Vee
Cx

GND

11EAI5V
L,

mrr

L2

WArmE'Q

L2
L3
C,
C2
C3
C4
SSNC
SSNO
GND

:]5

L3 ]6
C, :] 7
C2 :] 8

~

RUN
RA'CT

C3 :] 9
C4 :] 10
NC :] "

FIRSTJ[AST
OSC
NC
Fo
Vcc

'2 '3 '4 '5 '6 '7 '8
nnnnnnn

DIP/CERPACK
TOP VIEW
LCC/PLCC
TOP VIEW

PIN DESCRIPTIONS
PIN NO.

NAME

DESCRIPTION

I/O

6.7.8.9

C,. C2• C3• C4

a

System clock outputs. These outputs are all active during every system clock cycle. Their timing is determined by
clock cycle length controls. L,. L2 and L3'

3.4.5

L,. L 2• L3

I

Clock cycle length control inputs. These inputs receive the microcode bits that select the microcycle lengths. They
form a control word which selects one of the eight microcycle waveform patterns F3 through F,o.

14

Fo

a

The buffered oscillator output. Fo internally generates all of the timing edges for outputs C,. C2. C3• C4 and
WAITACK Fo rises just prior to all of the C,. C2. C3. C4 transitions.

18.19

RA'CT and RUN

I

Debounced inpu~rovide RA'CT control. These inputs determine whether the output clocks run or not. A LOW
input on RACT (
= HIGH) will stop all clock outputs.

17

FIRST/[AST

I

RA'CT time control input. A HIGH input in conjunction with aHACT command will cause a haltto occur when C4 =
LOW and C, = C2 = C3 = HIGH (see clock waveforms). A LOW input causes a RA'CT to occur when C, = C2 =

11.10

SSNO and
SSNC

I

Single Step control inputs. These debounced inputs allow system clock cycle single stepping while RAIT is actio
vated LOW.

21

WAITREQ

I

The Wait Request active LOW input. When LOW. this input will cause the outputs to halt during the next oscillator
cycle after the Cx input goes LOW.

23

Cx

I

Wait cycle control input. The clock outputs respond to a wait request one oscillator clock cycle after Cx goes LOW.
Cx is normally tied to anyone of C,. C2. C3 or C4.

20

WAITACK

a

The \A!a.Jt Acknc't.'!edge active LOV-! Ct:+.pt:t. \A!hcn LOV'!. t'1:~ output ind!c:ltc~ t'1o.t c.!! clock output:; arc In tho N\AJAITstate.

2

riEAt5Y'

I

The riEAt5Y' active LOW input is used to continue normal clock output patterns after a wait stage.

22

mrr

I

The Initialize active LOW input. This input is intended for use during power up initialization.of the system. When
LOW. all clock outputs run free regardless of the state of the Halt. Single Step. Wait Request and Ready inputs.

16

OSC

I

External oscillator input. (TIL level inputs.)

C3 = LOW and C4 = HIGH.

8-118

IDT49C25/A HIGH·PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOGIC DIAGRAM
STATE MACHINE DECODER
(6-AND-OR-INVERTER)

)-:.OS,:"C:"""--I BUFFER

fa

fa

K2 = C4C3 E3 E2 E1HW+A2A1C4C3E3 E2HW+
A2A1C3C2HW+C3C2C1+C2H +C2 W
K3 = C4C3 E3 E2 E1HW+A2A1C4C3HW+
C3C2+C3C1+C3H+C3W

Kt=

C3C2C1HW+C4H+C4W

B1 = A2C3E1HW+C4C3E1HW+A2A1 C4C3+
A 1H·A1W

Bz = C4C3 E2 Rw +A1 C4 C3 E3 RW +A2A1 C4RW +
A 2C3 HW+A2H+A2W

Kl

fa

EXAMPLE:

E1

:~z
Z

=

Bz

D

fa

B1

D

AS + CD+ EF
fa

L. _ _ _ _ _ _ _ .J

CK

CK

0

A2

Q

A2

0

A1

Q

A1

r--------------------------------,
STATE MACHINE CONTROL

+5V

1

>-----~==+----------+I------------~
1

....----,0 1

r-~==~--~~

r~--'

RS
LATCH

1
1

fa

1

R

1

- - - - ' 01
C)~--------~~I

H

~4---,
1
1

SSNO

WAIT

fa

I
I
REO

I
I fa
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ J

8-119

IDT49C25/A HIGH·PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

ABSOLUTE MAXIMUM RATINGS
RATING

SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

100

100

mA

SYMBOL
CIN

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance

CONDITIONS TYP.
VIN = OV

MAX. UNIT

6

10

pF

COUT
Output Capacitance
VOUT = OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to + 70°C
Vcc = 5.0V ± 5% (Commercial)
TA = -55°C to + 125°C
Vcc = 5.0V ± 10% (Military)
VLC = 0.2V
VHC = Vcc - 0.2V
SYMBOL
"'H
"'L
IIH

MIN.

TYP.(2)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic High Level

2.0

-

V

Input LOW Level

Guaranteed Logic Low Level

0.8

V

Input HIGH Current

Vcc = Max., "'N = Vcc

-

-

25

J.lA

TEST CONDITIONS (1)

PARAMETER

SSNO,SSNC,RON,RAIT
Vcc = Max.
VIN = O.4V

IlL

FIRST/LAST

-

-5

J.lA

-1.2

mA

Vcc = Max. (3)

-60

-120

VHC

Vcc

VHC
2.4

Vcc
4.0

-

mA

Vcc = 3V, "'N = VLC or VHC ' 10H = -32J.lA

2.4

4.0

-

GND

VLC

GND

-

VLC
0.5

Vcc = Min., IN = -18mA

Isc

Short Circuit Current

10H = -300J.lA
Vcc = Min.

10H = -3.0mA MIL.

"'N = '-"H or "'L

10H = -5.0mA COM'L.

IOL = 300J.lA

-

Vcc = Min.

10L = 16mA MIL.

-

"'N = "'H or"'L

10L = 24mA COM'L.

-

Vcc = 3V, "'N = VLC or VHC,I OL = 300J.lA
VOL

Output LOW Voltage

mA

-0.7

Clamp Diode Voltage

Output HIGH Voltage

-1.0
-1.5

-

Other Inputs

VI

VOH

-

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

8-120

0.5

V

V

IDT49C25/A HIGH-PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V;
SYMBOL

vHC =

Vcc - 0.2V
PARAMETER

TEST CONDITIONS (1)

ICCQ

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC ; \'IN :5 VLC
fl = 0

ICCT

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
\'IN = 3AV(3)

Dynamic Power Supply Current

Vcc = Max.
Outputs Open

ICCD

I

\'IN ~ VHC
\'IN :5 VLC

Vcc = Max.
Outputs Open
fl = 5MHz
READY. SSNO. WAiT REO. HAIT. TNTi = Vcc
L 1• L 2 • L 3. SSNC. FIRST/CAST. "RUN. Cx = GND
Icc

Total Power Supply Current (4)

Vcc = Max.
Outputs Open
fl = 5MHz
SSNO. HALT = 'Icc
READY. WAIT REQ. TNTf = 3AV (98% duty cycle)
L 1 • L 2 • L3. SSNC.FIRST/LAST."RUN. C x= GND

Typ.(2)

MAX.

UNIT

-

0.001

1.5

rnA

-

0.5

2.0

rnA

-

0.15

0.25

rnA/MHz

-

6A

2.25

MIN.

rnA

-

2.25

9.25

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3AV); all other inputs at Vcc or GND.
4. Icc = IQUIESCENT + IINPUTS + IDYNAMIC
Icc = ICCQ + ICCT DH NT + ICCD (fcp/2)
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TIL High Input (VIN = 3AV)
DH = Duty Cycle for TIL inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current caused by an input Transition pair (HLH or LHL)
fcp = ClockFrequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N, = Number of inputs at f,
All currents are in milliamps and all frequencies are in megahertz.

8-121

IDT49C25/A HIGH-PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT49C25A (7)

IDT49C25
SYMBOL

PARAMETER

CONDITION

COM'L

tvp,(1)
t

MIN.

MIL

COM'L

TYP,<6)

MAX.

MIN.

MAX.

MIL

UNIT

MIN.

,MAX.

MIN.

MAX.

1

fMAX1

Fe Frequency
(Cx Connected)(1)

-

31

-

31

-

-

40

-

40

-

ns

2

fMAX2

Fe Frequency
(Cx= HIGH)

42

-

-

-

-

50

-

-

-

-

ns

3

tOFFSET

Fe (S~1'T~6~2. C3.
C4 or
(S)

-

-

8.5

-

8.5

-

-

6.0

-

6.0

ns

4

tOFFSET

Fe (S~ to C1. C2. C3.
C4 or AITAC~ Ct)

-

17

-

18

-

-

11.5

-

12

ns

-

2

2

-

-

1.5

-

1.5

ns

1.5

1.5

ns

8.0

-

8.0

ns

-

-

3.0

-

3.0

ns

6

-

6

ns

-

12

12

-

ns

-

0

0

12
\_0

-

0

12

-

12

0

\-

0

-

12

-

12

-

ns

-

-

tSKEW

~ (S)toC3 (S)

-

7

tsKEW

C1 (S) to C4 (t)
Opposite Transition

-

-

11

-

8

tsu

L 1• L2• L3 to

C; (S)
L1• L2• L3 to C; (S)

-

4

-

4

8

-

18

5

tSKEW

6

C1 (S)toC2(S)

9

tH

10

tsu

11

tH

12

tsu

WArmEato Fe (S)(3)

13

tH

WATTJ1E'Q to fo (S )(3)

14

tsu

~toFe (S)(3)

15

tH

~tofo (S)(3)

16

tsu

17

tsu

18

tsu

19

tsu

20

tPWL

21

t pLH

22

t pLH

23

t pHL

Cx to Fe (S)(2)
Cx to Fe (S)(2)

liON. HAI:T (S) to
Fe (S)(3,4)

CL = 50pF
RL = 5000

18
0

2

8

0
18

18

-

18
0
18
0

0

2
11

-

18

-

0
18

-

12

ns
ns
ns
ns
ns

SSNC. SSNO to
Fe (S)(3.4)

-

18

-

18

-

-

12

-

12

-

ns

FIRST/~to

-

18

-

18

-

-

12

-

12

-

ns

18

-

.18

-

-

12

-

-

-

18

-

2.3

-

ns

25

-

27

-

16

-

18

ns

-

'16

-

-

8.5

-

10.5

ns

10.5

ns

Fe (S)(5)

TNTT (S ) to Fe (S )(3)
TNTT LOW Pulse Width
TNTT to WAITACR
OSCto Fe

-

20

-

25

-

13

13

16

8.5

ns

NOTES:
1. The frequency guarantees apply with C x connected to C 1• C 2' C 3' C4 • or HIGH. The Cx input load must be considered part of the 50pf/5000 clock output
loading.
2. These set-up and hold times apply to the Fe LOW-to-HIGH transition of the period in which Cx goes LOW.
3. The.se inputs are synchronized internally. Failure to meet ts may cause a 1/Fe delay but will not cause incorrect operation.
4. These inputs are "debounced" by an internal R-S flip-flop and are intended to be connected to manual break-before-sake switches.
5. FIRST/'CAST normally wired HIGH or LOW.'
6. Typical values are at Vcc = 5.0V. + 25°C ambient and maximum loading.
7. These values are preliminary only.

8-122

IDT49C25/A HIGH·PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING WAVEFORMS

Fa

fa
(INTERNAL)

Figure 2. Normal Cycle Without Wait States (Pattern F6 Shown)

WAIT TIMING (Cx Connected to C1 )
PERIOD
1
2

w

w

w

w

Fa

fa
(INTERNAL)

~ ------------~----~I

WAlfAcK

Figure 3. Wait Timing (Cx Connected to C1)

8-123

IDT49C25/A HIGH-PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED DESCRIPTION
The IDT49C25/A are dynamically programmable generalpurpose clock controllers. They can be logically separated into
two parts-a state machine decoder and a state machine control
section.
The state machine takes microcode information from the
Microcycle Length _(L) Inputs L1. L2 and l:J and counts the funda-

mental frequency of the oscillator (OSC) to create the clock outputs
Fa. Cl. C2. C3 and C4.
The clock outputs have a characteristic wave shape relationship
for each microcycle length. For example. Cl is always LOW only on
the last Fa clock period of a microcycle and C4 is always LOW on the
first. C3 has an approxi mate duty cycle of 50% and C2 is HIGH for all
but the last two periods (see Figure 4).

PATIERN

PATIERN
WAVEFORMS
AND
TIMING

INPUT
CODE

WAVEFORMS
AND
TIMING

INPUT
CODE

L3 .L2 .Ll

L3 .L2 .Ll
Cl

Cl

F,
LHH

Fa

Cl

Cl

Fa

LHL

Fa

Fa

Cl

Cl

Ii

I1l

HLH

HHL

Fa
Cl

Cl

Fia

Fa

HLL

HHH

Fa

Fa

Figure 4. IDT49C25/A Clock Waveforms

8-124

IDT49C25/A HIGH-PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The current state of the machine is contained in a register, part of
which is the Clock Generator Register. C1, C2, C3 and C4 are the
outputs of this register. These outputs and the outputs of the
Microcycle Control Latch are fed into combinatorial logic to generate the next state. On each falling edge of the internal clock, the
next state is entered into the current state register. The Microcycle
Control Latch is latched when C1 is HIGH. This means that it will be
loaded during the last state of each microcycle (C1 = C2 = C3 =
LOW, C4 = HIGH). This internal latch selects one of eight possible
microcycle lengths, F3 to FlO.
The state machine control logic, which determines the mode of
operation ofthe state machine, is intended to be connected to a front
panel. There are four b;isic modes of operation of the IDT49C25/A
comprised of RUN, HALT, WAIT and SINGLE STEP.

Vee
SPDTSWITCH

IDT49C25/A
NC
NC

System Timing

SSNC

L - - - - I SSNO

GND

In the typical computer, the time required to execute different
instructions varies. However, the time allotted to each instruction is
the time that it takes to execute the longest instruction. The
IDT49C25/A allow the user to dynamically vary the time allotted for
each instruction, thereby allowing the user to realize a higher
throughput.

SPOT PUSHBUTTON SWITCH

IDT49C25/A Control Inputs

Figure 5. Switch Connection for RUN/HALT and Single Step

The control inputs fall into two categories, microcycle length
control and clock control. Microcycle length control is provided via
the "L" inputs which are intended to be connected to the
microprogram memory. The "L" inputs are used to select one of
eight cycle lengths ranging from three oscillator cycles for pattern F3
to ten oscillator cycles for pattern FlO. This information is always
loaded at the end of the microcycle into the Microcycle Control
Latch which performs the function of a pipeline register for the
microcycle length microcode bits. Therefore, the cycle length goes
in the same microword as the instruction that it is associated with.
The clock control inputs are used to synchronize the
micropro..9..@!!l machine with the external world and I/O devices. Inputs like RUN, HALT, SSNO and SSNC, which start and stop execution, are meant to be connected to switches on the front panel of the
microprogrammed machine (see Figure 5). These inputs have internal pull-up resistors and are connected to an R-S flip-flop in order
to provide switch debouncing. The FIRST/LAST input is used to
determine at what point of the microcycle the IDT49C25/A will halt
when HALTor a SINGLE STEP is initiated. In most applications, the
user wires this input HIGH or LOW, depending on his design.

When HALT is held low (RUN= HIGH), the state machine will
start the halt mode on the last (C1 = LOW) or the first (C4 = LOW)
state of the microcycle as determined by the FIRST/LAST input.
When RUN goes low (HALT = HIGH), the state machine will resume
the run mode.
The WAITREQ, Cx, READY and WAITACK signals are used to
synchronize other parts of a computer system (memory, I/O devices) to the CPU by dynamically stretching the microcycle. For
example, the CPU may access a slow peripheral that requires the
data remain on the data bus for several microseconds. In this case,
the peripheral pulls the WAITREQ line LOW. The Cx input lets the
design specify when the WAITREQ line is sampled in the
microcycle. This has a direct impact on how much time the peripheral has to respond in order to request a wait cycle (see Figure 6).
The READY line is used by the peripheral to signal when it is ready to
resume execution of the rest of the microcycle. The WAITACK line
goes LOW on the next oscillator cycle after the Cx input goes LOW
and remains LOW until the second oscillator cycle after READY
goes LOW.

Fo

WAITACK

Figure 6. WAIT/READY Timing

8-125

IDT49C2S/A HIGH-PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The SSNO and SSNC Inputs are used to Initiate the SINGLE
STEP mode. These debounced inputs allow a single microcycle to
occur while in the halt mode. SSNO (normally open) and SSNC
(normally closed) are intended to be connected to a momentary
SPOT switch. After SSNO has been low for one clock edge, the state
machine will change to the next run mode. The microcycle will end
on the first or last state of the microcycle, depending on the state of
the FI RST/LAST .

AC Timing Signal References
Set-up and hold times In registers and latches are measured relative to the clock signals that drive them. In the IOT49C2S/A, the
external oscillator provides a free running clock signal that drives all
the registers on the devices. This clock is provided for the user
through the buffered output of Fa. Therefore, Fa is used as the reference of set-up, hold and clock-to-output times. However, for the
Microcycle Control Latch, the set-up and hold times are referenced
to the Cl output which is the buffered version of the latch enable.
This reference is appropriate for the Microcycle Control Latch because, in a typical application, this latch is considered part of the
pipeUne registered which is also driven by one of the "Cft outputs.

Fa

SSNC

SSNO

C1

C2&C3

I
I
I
IL _ _ _ _ _ _ _ _ _ _ JI

C4

HALT

MODE

Figure 7. Single Step Timing Sequence

8-126

RUN

MODE
(F3)

HALT

MODE

IDT49C25/A HIGH-PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR THREE-STATE OUTPUTS
Vcc

SWITCH POSITION

()--e 7.0V

TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

5000
DEFINITIONS
C L = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to:lour of the
Pulse Generator

5000

SET-UP, HOLD AND RELEASE TIMES

TIMING
INPUT _ _ _ _ _ _ _ _
ASYNCHRONOUS CONTROL
PRESET - - - - - - , .
CLEAR
ETC.

J1

PULSE WIDTH

'\,_-+____

-

-

---+---+----- -

3V
1.5V

OV

3V
1.5V

OV

SYNCHRONOUS CONTROL
PRESET

CLEAR~

CLOCK ENABLE
ETC.

tsu

PROPAGATION DELAY

3V
SAME PHASE - {
INPUT TRANSITION

1.5V

OV
t pLH

_---...;......"'-t--

OUTPUT

1.5V

~

PLH

OPPOSITE PHASE
INPUT TRANSITION

VOH

'-_ _ _ _--'--.,.,--_ _

VOL

3V

1.5V

OV

8-127

IDT49C25/A HIGH-PERFORMANCE
CMOS MICROCYCLE LENGTH CONTROLLER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT49C25/A

xx

x

Device Type

Process/
TempeILrn_t_ur_e____________

~

L------------------------------------------l

8-128

+ 70°C)

BLANK

Commercial (O°C to

B

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

P
D
J
L
E

Plastic DIP
CERDIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
CERPACK

25
25A

Microcycle Length Controller
Fast Microcycle Length Controller

MICROSLICE ™ PRODUCT

FEATURES:

DESCRIPTION:

• Fast
- 30% faster than four 2901Cs and one 2902A

The IDT49C401s are high-speed, fully cascadable 16-bit CMOS
microprocessor slice units which combine the standard functions of
four 2901s and a 2902 with additional control features aimed at enhancing the performance of bit-slice microprocessor designs.
The IDT49C401s include all of the normal functions associated
with standard 2901 bit-slice operation: (a) a 3-bit instruction field (10,
h, 12) which controls the source operand selection for the ALU, (b) a
3-bit microinstruction field (13, 14, 15) used to control the eight possible functions of the ALU and (c) sixteen destination control functions
which are selected by the microcode inputs (16,17,18,19). Eight of the
sixteen destination control functions reflect the standard 2901 operation, while the other eight additional destination control functions
allow for shifting the Q Register up and down, loading the RAM or Q
Register directly from the 0 inputs without going through the ALU
and new combinations of destination functions with the RAM A port
output available at the Y output pins of the device. Also featured is an
on-chip dual-port RAM that contains 16 words by 16 bits.
The IDT49C401 s are fabricated using CEMOS, a CMOS technology designed for high performance and high reliability. These performance enhanced devices feature both bipolar speed and bipolar
output drive capabilities, while maintaining exceptional microinstruction speeds at greatly reduced CMOS power levels.

• Low Power CEMOS ™
- Military: 22SmA (max.)
- Commercial: 180mA (max.)
• Functionally equivalent to four 2901s and one 2902
• Pin-compatible, performance-enhanced replacement for
IMI4X2901B
• Independent, simultaneous access to two 16-word x 16-bit
register files
•

Expanded destination functions with eight new operations allowing Direct Data to be loaded directly into the dual-port
RAM and Q Register

• Cascadable
• Available in 64-pin DIP
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

0
1

ALU
SOURCE

3
4
5

ALU
FUNCTION

2

6

7 DESTINATION
8
CONTROL
9

z
Q

..-U

W

=>8

READ ADDRESS

~U
Zw
_0

~

U
:E

DIRECT DATAIN

CARRY IN
MSS

DATAoUT
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-90 101-

8-129

IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION
o

u..Q eta:

.5'
_

~.:;
_ _

~

~

~

~ 0" 0

c

-;='

'l1

~

:!

U

>"

et0

N

_

~'

0'"

_..,.

0""

,A

~'

Oan

_0

oU)

~

0-

~

0
Z

(!l

iW
>g 10

~ m enN

en'"

~

..,.

:

0 8 c5 0" c5 c5'" c5 c5an
0

N

~

a:

an

..2'

.J oJ

~ ~ J :3 ~ ~

~ ~ >

.J

DIP
TOP VIEW

;{!!

0

II

u.

PIN DESCRIPTIONS
PIN NAME

DESCRIPTION

I/O

Ao- A 3

I

Four address inputs to the register file which selects one register and displays its contents through the A port.

8o- B3

I

Four address inputs to the register file which selects one of the registers in the file, the contents of which is displayed through
the B port. It also selects the location into which new data can be written when the clock goes LOW.

10 -19

I

Ten instruction control lines Which determine what data source will be applied to the ALU 1(0, 1, 2), what function the ALU will
perform 1(3, 4, 5) and what data is to be deposited in the 0 Register or the register file 1(6, 7, 8, 9). Original 2901 destinations are
selected if 19 is disconnected. In this mode, proper 19 bias is controlled by an internal pullup resistor to Vcc.

Do-D15

I

Sixteen-bit direct data inputs which are the data source for entering external data into the device ALU, 0 Register or RAM. Do is
the LSB.

YO-Y 15

a

Sixteen three-state output lines which, when enabled, display either the sixteen outputs of the ALU or the data on the A port of
the register stack. This is determined by the destination code 1(6,7,8,9).

G/F15

0

F=O

a

Cn

A multipurpose pin which indicates the carry generate (G) function at the least significant and intermediate slices or as F15, the
= HIGH, F15 is enabled. If MSS =
LOW, G is enabled.

mosts~nificant ALU output (sign bit). G/Fj5 selection is controlled by the MSS pin. If MSS

I

Open drain output which goes HIGH ifthe Fo -F15 ALU outputs are all LOW, This indicates that the result of an ALU operation is
zero (positive logic),
Carry-in to the internal ALU.

a

Carry-out of the internal ALU.

0 15
RAM 15

I/O

Bidirectional lines controlled by 1(6,7,8,9), Both are three-state output drivers connected to the TTL-compatible inputs,
When the destination code on 1(6, 7, 8, 9) indicates an up shift, the three-state outputs are enabled, the MSB of the 0 Register is
available on the 0 15 pin and the MSB ofthe ALU output is available on the RAM 15 pin. When the destination code indicates a
down shift, the pins are the data inputs to the MSB of the 0 Register and the MSB of the RAM.

00
RAMo

I/O

Both bidirectional lines function identically to 0 15 and RAM 15 lines, except they are the LSB of the 0 Register and RAM.

Cn + 16

DE

I

Output enable. When pulled HIGH, the Y outputs are OFF (high impedance). When pulled LOW, the Youtputs are enabled.

PIOVR

a

A multipurpose pin which indicates the carry propagate (fS) output for performing a carry lookahead operation or overflow
(OVR) the Exclusive-OR of the carry-in and carry-out of the ALU MSB. OVR, at the most significant end of the word, indicates
that the result of an arithmetic two's complement operation has overflowed into the sign bit. PIOVR selection is controlled by
the MSS pin. If MSS = HIGH, OVR is enabled. If MSS = LOW, P is enabled.

CP

I

The clock input. LOW-to-HIGH clock transitions will change the 0 Register and the register file outputs. Clock LOW time is
internally the write enable time for the 64 x 16 RAM which compromises the master latches of the register file. While the clock is
LOW, the slave latches on the RAM outputs are closed, storing the data previously on the RAM outputs, Synchronous
MASTER-SLAVE operation of the register file is achieved by this,

MSS

I

When HIGH, enables OVR and F,5 on the fS"!OVR and G/F15 pins. When LOW, enables G and P on these pins, If left open,
internal pullup resistor to Vcc provides declaration that the device is the most significant slice and will define pins as OVR and
F15·

8-130

IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEVICE ARCHITECTURE:
The IDT49C401 CMOS bit-slice microprocessor is configured
sixteen bits wide and is cascadable to any number of bits (16, 32, 48,
64). Key elements which make up these 16-bit mi~ropr?cessor
slices are the (1) register file (16 x 16 dual-port RAM) with shifter, (2)
ALU and (3) a Register and shifter.
REGISTER FILE-A 16-bit data word from one of the 16 RAM
registers can be read from the A port as selected by the 4-bit A address field. Simultaneously, the same data word or any other word
from the 16 RAM registers can be read from the B port as selected by
the 4-bit B address field. New data is written into the RAM register
location selected by the B address field during the clock (CP) LOW
time. Two 16-bit latches hold the RAM A port and B port during the
clock (CP) LOW time, eliminating any data races. During clock
HIGH, these latches are transparent, reading the data selected by
the A and B addresses. The RAM data input field is driven from a
four-input multiplexer that selects the ALU. ?utput or the D in~~ts.
The ALU output can be shifted up one pOSition, down one position
or not shifted. Shifting data operations involves the RAM15 and
RAMo I/O pins. For a shift up operation, the RAM shifter MSB is connected to an enabled RAM15 I/O output while the RAMo I/O input is
selected as the input to the LSB. During a shift down operation, the
RAM shifter LSB is connected to an enabled RAMo I/O output, while
the RAM15 I/O input is selected as the input to the MSB.
ALU - The ALU can perform three binary arithmetic and five logic
operations on the two 16-bit input words S a.nd R. ~he ~ in~ut field is
driven from a 3-input multiplexer and the R Input field IS dnven from
a 2-input multiplexer, with both having a zero source operand. Both
multiplexers are controlled by the 1(0.1.2) i.nputs. This multiplexer
configuration enables the user to select vanous pairs of the A, B, D,
and "0" inputs as source operands to the ALU. Microinstruction
inputs 1(3.4.5) are used to select the ALU function. This high-speed
ALU cascades to any word length, providing carry-In (Cn), carry-out
(Cn+16) and an open-drain (F = 0) outp~t. When al.1 bits o~ the ALU
are zero, the pull-down device of F = 0 IS off, a"owlng a '!!Ire-OR of
this pin over a" cascaded devices. Multipurpose pins G/FI5 and

a

P/OVR are aimed at accelerating arithmetic operations. For intermediate and least significant slice~ the MSS pin is progra...!!lmed
LOW, selecting the carry-generate (G) and carry-propagate (P) o~t­
put functions to be used by carry lookahead logic. For the most significant slice, MSS is programmed high, selecting the sign-bit (FI5)
and the two's complement overflow (OVR) output functions. The
sign bit (FI5) allows the ALU sign bit to be monitored without enabling the three-state ALU outputs. The overflow (OVR) output is high
when the two's complement arithmetic operation has overflowed
into the sign bit as logica"y determined from the Exclusive-OR of the
carry-in and carry-out of the most significant bit of the ALU. For a"
16-bit applications, the MSS pin on the IDT49C401s is tied high or
not connected since only one device is needed. With MSS open or
tied high, internal circuitry wi" direct pins 33 and 34 to function as
F15 and OVR, respectively. It is in this 16-bit operating mode that the
IDT49C401s function identically to the IM14X2901B. The ALU data
outputs are available at the three-state outputs Y(0-15) or as inputs to
the RAM register file and Register under control of the 1(6.7.8.9) instruction inputs.
REGISTER-The
Register is a separate 16-bit register intended for multiplication and division routines and can also be used
as an accumulator or holding registerfor other types of applications.
It is driven from a 4-input multiplexer. In the no-shift mode, the mUltiplexer enters the ALU F output or Direct Data into the a Register. In
either the shift up or shift down mode, the multiplexer selects the
Register data appropriately shifted up or down. The
shifter. has
two ports, 00 and 015, which operate comparably to the RAM shifter.
They are controlled by the 1(6.7.8.9) inputs.
Register
The clock input of the IDT49C401 controls the RAM,
and A and B data latches. When enabled, the data is clocked into the
Register on the LOW-to-HIGH transition. When the clock is HIGH,
the A and B latches are open and pass data that is present at the
RAM outputs. When the clock is LOW, the latches are closed and
retain the last data entered. When the clock is LOW and 1(6. 7. 8. 9) define the RAM as the destination, new data wi" be written into the RAM
file defined by the B address field.

a

a

a

12

11

10

ALU FUNCTION CONTROL
ALU SOURCE
OPERANDS

MICROCODE
OCTAL
CODE
0

a

a

ALU SOURCE OPERAND CONTROL
MNEMONIC

a
a

MICROCODE
MNEMONIC

R

S

15

14

13

OCTAL
CODE

ALU
FUNCTION

SYMBOL

A

Q

ADD

L

L

L

0

R Plus S

R+S

1

A

B

SUBR

L

L

H

1

S Minus R

S-R

L

2

0

Q

SUBS

L

H

L

2

R Minus S

R-S

H

3

0

B

OR

L

H

H

3

RORS

RVS

L

4

0

A

AND

L

L

4

RANDS

RAS

L

H

5

D

A

NOTRS

H
H

L

H

5

RANDS

RAS

H

L

6

D

Q

EXOR

6

REX-OR S

R"i7'S

7

D

0

EXNOR

H
H

L

H

H
H

H

7

REX-NOR S

R"i7'S

AQ

L

L

L

AB

L

L

H

ZQ

L

H

ZB

L

H

ZA

H

L

DA

H

DQ

H

DZ

H

H

8-131

Ell
I

I

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE

ALU ARITHMETIC MODE FUNCTIONS
OCTAL
15,4,3, ~,1,O
0
0

0
0
0

1

5

Cn

=L

GROUP
ADD

6

Cn

FUNCTION
A+O
A+8
D+A
D+O

Increment

0-1
8-1
A-1
0-1

PASS

2
3

1
1
1
2

2
3

2
2
2
1

2
3

1
1
1
1
2
2
2
2

0

o -A-1

1

8 - A-1
A - 0-1
0- 0-1
A- 0-1
A - 8-1
0- A-1
0- 0-1

4
7

4
7

PASS

Decrement

1's Compo

5

6
0
1

5

6

Subtract
(1's Comp.)

ADD
plus one

0
8
A
D

0
0
0
0

4
7

GROUP

-0
-8
-A
-0

-1
-1
-1
-1

ALU LOGIC MODE FUNCTIONS

=H

OCTAL

FUNCTION
A+ 0 + 1
A+8+1
D+A+1
D+ 0 + 1

15,4,3,

0+1
8 + 1
A+1
0+1
0
8
A
0

2's com).
(Negate

-0
-8
-A
-D

Subtract
(2's Comp.)

O-A
8-A
A-O
O-D
A-O
A-8
O-A
0-0

GROUP

4
4
4
4

5
6

3
3
3
3

5
6

6
6
6
6

5
6

7
7
7
7

5
6

7
7
7
7

2
3
4
7

INVERT

6
6
6
6

2
3
4
7

PASS

3
3
3
3

2
3
4
7

PASS

4
4
4
4

3
4
7

5
5
5
5

8-132

12,1,0
0
1

AND

AAO
AA8
DAA
OAO

OR

AVO
AV8
OVA
OVO

EX-OR

A'V'O
A'V'8
D'V'A
D'V'O

EX-NOR

A'V'O
~
D'V'A
D'V'O

0
1

0
.1

0
1

Q
A
0
8
A
0
0
8

A
0

0
"ZERO·

0

0
0

0
1

8
D

2

5
6

FUNCTION

MASK

AAO
AA8
'BAA
[)AO

IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SOURCE OPERAND AND ALU FUNCTION MATRIX

(1)

12 ,1,0 OCTAL
OCTAL
15,4,3

ALU
FUNCTION

0

Cn = L
R Plus S
Cn = H

0

3

2

1

5

4

6

7

D,O

ALU SOURCE
A,B

0,0

O,B

O,A

D,A

D,O

A+O

A,O

A+B

Q

B

A

D+A

D+O

D

A+0+1

A+B+1

0+1

B + 1

A+1

D+A+1

D+0+1

D + 1

Cn = L
S Minus R
Cn = H

0- A-1

B-A-1

0-1

B-1

A-1

A - D-1

0- D-1

-D -1

O-A

B-A

0

B

A

A-D

O-D

-D

A - 0-1

A - B-1

-0 - 1

-B -1

-A -1

D-A-1

D - 0-1

D -1

2

Cn = L
R Minus S
Cn = H

A-O

A-B

-0

-B

-A

D-A

D-O

D

3

RORS

AVO

AVB

0

B

A

DVA

DVO

D

4

RANDS

AAO

AA B

0

0

0

DAA

DAO

0

5

RANDS

AAO

AAB

0

B

A

DAA

DAO

0

6

REX-OR S

A"V'O

A"V'B

0

B

A

D"V'A

D"V'O

D

7

REX-NOR S

A"V'O

A"V'B

0

B

A

D"V'A

D"V'O

D

1

NOTE:
1. + = Plus; - = Minus; A = AND; "V' = EX-OR; V = OR

ALU DESTINATION CONTROL(l)
RAM
FUNCTION

MICROCODE
MNEMONIC

16

HEX
CODE SHIFT

Ie

18

17

OREG

H

L

L

L

8

NOP

H

L

L

H

9

o REGISTER
FUNCTION

Y
OUTPUT

LOAD

RAM
SHIFTER

LOAD

SHIFT

X

NONE

NONE

F--.O

F

X

X

NONE

X

NONE

F

X

RAMo

0
SHIFTER

00

0 15

X

X

X

X

X

X

RAM 15

RAMA

H

L

H

L

A

NONE

F--.B

X

NONE

A

X

X

X

X

RAMF

H

L

H

H

B

NONE

F--.B

X

NONE

F

X

X

X

X

RAMOD

H

H

L

L

C

DOWN

F/2--.B

F

Fa

IN 15

00

IN 15

RAMD

H

H

L

H

D

DOWN

F/2--.B

X

NONE

F

Fa

IN 15

00

X

RAMOU

H

H

H

L

E

UP

2F--.B

UP

20--.0

F

INa

F15

INa

0'5

RAMU

H

H

H

H

F

UP

2F--.B

X

NONE

F

INa

F15

X

0 15

DFF

L

L

L

L

0

NONE

D--.B

NONE

F--.O

F

X

X

X

X

DFA

L

L

L

H

1

NONE

D--.B

NONE

F--.O

A

X

X

X

X

FDF

L

L

H

L

2

NONE

F--.B

NONE

D--.O

F

X

'X

X

X

FDA

L

L

H

H

3

NONE

F--.B

NONE

D--.O

A

X

X

X

X

XODF

L

H

L

L

4

X

NONE

DOWN 0/2--.0

F

X

X

00

IN 15

DOWN 0/2--.0

DXF

L

H

L

H

5

NONE

D--.B

X

NONE

F

X

X

00

X

XOUF

L

H

H

L

6

X

NONE

UP

20--.0

F

X

X

INa

015

Existing 2901
Functions

New Added
IDT49C401
Functions

X
F
X
X
H
H
7
NONE
NONE D--.O
015
XDF
L
H
X
NOTE:
1. X = Don't Care. Electrically, the shift pin is a TTL input intemally connected to a three-state output which is in the high-impedance state.
B = Register Addressed by B inputs
UP is toward MSB; DOWN is toward LSB

8-133

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE

ABSOLUTE MAXIMUM RATINGS
SYMBOL

CAPACITANCE

(1)

COMMERCIAL

RATING

MILITARY

UNIT

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TsrG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

50

50

mA

-0.5 to +7.0

-0.5 to +7.0

SYMBOL

Input Capacitance

CIN

V

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CONDITIONS
'-"N = OV

Output Capacitance
COUT
VOUT = OV
NOTE:
1. This parameter is sampled and not 100% tested.

TYP.

UNIT

5

pF

7

pF

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification Is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC, ELECTRICAL CHARACTERISTICS
Vec = 5.0V ± 5% (Commercial)
Vce = 5.0V ± 10% (Military)'

TA = O°C to + 70°C
TA = -55°C to +125°C
VLC = 0.2V
VHC = Vcc-O 2V
SYMBOL

TEST CONDITIONS (1)

PARAMETER

'-"H

Input HIGH Level

Guaranteed Logic High Level (4)

'-"L

Input LOW Level

Guaranteed Logic Low Level (4)

IIH

Input HIGH Current

Vcc = Max., VIN

IlL

Input LOW Current

Vee = Max., '-"N

VOH

VOL

Output HIGH Voltage

Output LOW Voltage

Vee
'-"N

Vee
'-"N

\

= Vcc
= GND
IOH

= Min.
= '-"H or'-"L

icH
IOH
IOL

= Min.
= '-"H or'-"L

IoL

= -300jJA
= -12mA MIL.
= -15mA COM'L.
= 300jJA
= 20mA MIL.

IOL = 24mA COM'L.
Vo

loz

Off State (High Impedance)
Output Current

Vee = Max.

los

Output Short Circuit Current

Vee = Min.', VOUT

= OV

Vo = Vcc (Max.)

= OV

(3)

MIN.

TYP.(2)

MAX.

UNIT

2.0

-

-

V

-

-

0.8

V

-

0.1

5

jJA
jJA

-

-0.1

-5

VHC

Vec

-

2.4

4.3

-

2.4

4.3

-

-

GND

VLC

-

0.3

0.5

-

0.3

0.5

-0.1

-10

0.1

10

-15

-30

-

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.

8-134

V

V

jJA
mA

IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont'd.)
TA = OOC to + 70°C
TA = -55°C to +125°C
VLC = 0.2V
VHC = Vcc -0.2V
SYMBOL

VCC = S.OV±S% (Commercial)
Vcc = S.OV ±10% (Military)

Quiescent Power Supply Current
CP = H

Vcc = Max.
VHC ~ VIN ,VIN ~ VLC
fcp = 0, CP = H

Quiescent Power Supply Current
CP = L

Vcc = Max.
VHC s: VIN, VIN ~ VLC
fcp = 0, CP = L

ICCT

Quiescent Input Power Supply(5)
Current (per Input @ TTL High)

Vcc

ICCD

Dynamic Power Supply Current

Vcc = Max.
VHC s: V1N , \IN ~ V LC
Outputs Open, OE = L

ICCOH

ICCOL

Total Power Supply Current

MAX.

MIL.

150

245

COM'L.

150

195

MIL.

80

125

COM'L.

80

98

-

0.3

0.5

MIL.

-

2.0

3.0

COM'L.

-

2.0

2.5

MIL.

-

135

210

COM'L.

-

135

170

MIL.

-

145

225

COM'L.

-

145

180

MIN.

UNIT
mA

mA

= Max. VIN = 3.4V, fcp = 0

Vcc = Max., fcp = 10MHz
Outputs Open, DE = L
CP = 50% Duty cycle
VHC ~ V1N ' V1N ~ VLC
Icc

TYP.(2)

TEST CONDITIONS (1)

PARAMETER

mAl
Input
mAl
MHz

mA

(6)

Vcc = Max., fcp = 10MHz
Outputs Open, DE = L
CP = 50% Duty cycle
\'IH = 3.4V, V1L = O.4V

NOTES:
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out IccoH, then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS orTTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH(CD H) + ICCOL (1 - CD H) + ICCT (NT X D H) + ICCD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period (VIN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock Input frequency

CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test environment. Large output currents are being switched in very short
periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing
results:
1) All input pins should be connected to a voltage potential during
testing. If left floating, the device may oscillate, causing improper
device operation and possible latchup.

3) Device grounding is extremely critical for proper device testing.
The use of multi-layer performance boards with radial decoupiing between power and ground planes is necessary. The
ground plane must be sustained from the performance board to
the OUT interface board and wiring unused interconnect pins to
the ground plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being recommended for minimized inductance.

4) To guarantee data sheet compliance, the input thresholds should
be tested per input pin in a static environment. To allow for testing
and hardware-induced noise, lOT recommends using VIL :::; OV
and VIH ~ 3V for AC tests.

2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be distributed to
decouple power supply lines and be placed as close as possible
to the OUT power pins.

8-135

IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C401A
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)

CYCLE TIME AND CLOCK CHARACTERISTICS

The tables below specify the guaranteed performance of the
IDT49C401A over the -55°C to + 125°C and aOCto + 7aOCtemperature ranges. All times are in nanoseconds and are measured
at the 1.5V signal level. The inputs switch between av and 3V with
signal transition rates of 1Vper nanosecond. All outputs have maximum DC current loads.

COMBINATIONAL PROPAGATION DELAYS (1)

MIL.

COM'L.

Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)

28

24

ns

Maximum Clock Frequency to
shift Q (50% duty cycle,
I = C32 or E32)

35

41

MHz

UNIT

Minimum Clock LOW Time

13

11

ns

Minimum Clock HIGH Time

13

11

ns

Minimum Clock Period

36

31

ns

= 50pF

CL

TO OUTPUT
FROM INPUT

(MSS = H)

(MSS.= L)
G,P

y

F15

Qo
Q15

RAMo
RAM 15

F=O

C n +16

OVR

UNIT

MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L.
A, B Address

41

37

39

35

41

37

41

37

37

34

41

37

40

36

D

32

29

29

26

29

26

31

28

27

25

32

29

28

26

Cn

29

25

-

-

26

24

25

23

20

18

29

26

23

21

10,1,2

35

32

30

27

35

32

34

31

29

26

35

32

30

27

13,4,5

35

32

28

26

34

31

34

31

27

25

35

32

28

26

-

16,7,8,9

25

23

-

-

-

-

-

-

-

-

-

-

20

18

A Bypass
ALU (I = AXX,
1XX,3XX)

30

27

-

-

-

-

-

-

-

-

-

-

-

34

31

31

28

33

30

34

31

30

27

34

31

34

-

Clock

-

ns

-

ns

-

ns

20

18

ns

-

-

-

ns

31

25

23

ns

ns
ns

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)

~

CP:

INPUT

~

SET-UP TIME
BEFORE H--+L
MIL.

COM'L.

HOLD TIME
AFTER H--+L
MIL.
0(3)

A, B Source Address

11

10

B Destination Address

11

10

D

-(1)

-

-

Cn

-

-

13,4,5

-

-

-

16,7,8,9

11

10

RAM 0, 15, Qo, 15

-

-

10,1,2

COM'L.
0(3)

SET-UP TIME
BEFORE L--+H
MIL.
24 (4)

COM'L.
21 (4)

Do not change (2)

-

-

12/22 (5)

10/20 (5)

-

-

UNIT

MIL.

COM'L.

2

1

ns

2

1

ns

2

1

ns

17

15

0

0

ns

28

25

0

0

ns

28

25

0

0

ns

0

0

ns

0

0

ns

Do not change (2)
'

HOLD TIME
AFTER L--+H

12

11

NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable priorto the H --+ L transition to allow time to access the source data before the latches close. The A address may then be
changed, The B address could be changed if it is not a destination; Le., if data is not being written back into the RAM, Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L --+ H transition is to allow time for data to be accessed, passed through the ALU, and returned to the RAM. It includes all
the time from stable A and B addresses to the clock L--+ H transition, regardless of when the H --+ L transition occurs,
5. First value is direct path (DATAIN --+ RAM/Q Register). Second value is indirect path (DAT~N --+ ALU --+ RAM/Q Register).

8-136

IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C401
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)

CYCLE TIME AND CLOCK CHARACTERISTICS

The tables below specify the guaranteed performance of the
IDT49C401 over the -55°C to + 125°C and O°Cto +70°Ctemperature ranges. All times are in nanoseconds and are measured
at the 1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have maximum DC current loads.

COMBINATIONAL PROPAGATION DELAYS (1)

MIL.

COM'L.

Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)

50

48

ns

Maximum Clock Frequency to
shift 0 (50% duty cycle,
I = C32 or E32)

20

21

MHz

UNIT

Minimum Clock LOW Time

30

30

ns

Minimum Clock HIGH Time

20

20

ns

Minimum Clock Period

50

48

ns

CL ::: 50pF
TO OUTPUT

FROM INPUT

(MSS = H)

(MSS= L)
G,P

Y

F15

00

RAMo
RAM 15

F=O

C n +16

OVR

0 15

UNIT

MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L.
A, B Address

52

47

47

42

52

47

47

42

38

34

52

47

44

40

-

-

ns

D

35

32

34

31

35

32

34

31

27

25

35

32

28

26

-

ns

Cn

29

26

-

-

29

26

27

25

20

18

29

26

23

21

41

37

30

27

41

37

38

35

29

26

41

37

30

27

13.4.5

40

36

28

26

40

36

37

34

27

25

40

36

28

26

-

ns

10.1.2

-

16. 7. 6. 9

26

24

-

-

-

-

-

-

-

-

-

-

20

18

20

18

ns

A Bypass
ALU (I = AXX,
1XX, 3XX)

30

27

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ns

42

38

41

37

42

38

41

37

30

27

42

38

41

37

25

23

ns

-

Clock

ns
ns

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)

~

CP:

INPUT

SET-UP TIME
BEFORE H-+L
MIL

COM'L.

A, B Source Address

20

18

B Destination Address

20
_(1)

18

-

13.4.5

-

-

16.7.6.9

12

11

RAMo. 15. 00.15

-

-

D
Cn
10.1.2

~

-

HOLD TIME
AFTER H-+L
MIL.
0(3)

COM'L
0(3)

SET-UP TIME
BEFORE L-+H
MIL.
50(4)

-

30/40 (5)

MIL

COM'L.

48(4)

2

1

ns

2

1

ns

26/36(5)

2

1

ns

35

32

0

0

ns

-

45

41

0

0

ns

-

45

41

0

0

ns

0

0

ns

0

0

ns

Do not change (2)

-

UNIT

COM'L.

Do not change (2)

-

HOLD TIME
AFTER L-+H

-

12

11

NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -+ L transition to allow time to access the source data before the latches close. The A address may then be
changed. The B address could be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and B are not changed
during the clock LOW time.
4. The set-up time prior to the clock L -+ H transition is to allow time for data to be accessed, passed through the ALU, and returned to the RAM. It includes all
the time from stable A and B addresses to the clock L-+ H transition, regardless of when the H -+ L transition occurs.
5. First value is direct path (DATAIN -+ RAM/Q Register). Second value is indirect path (DATAN -+ ALU -+ RAM/Q Register).

8-137

IDT49C401/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C401A
OUTPUT ENABLE/DISABLE TIMES
(CL

= 5pF. measured to O.5V change of VOUT

AC TEST CONDITIONS

ENABLE
INPUT

OUTPUT

OE

Y

MIL
25

I

I

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

in nanoseconds)
DISABLE

COM'L
23

MIL

I

I

25

COM'L

GNO t03.0V

WIns
1.5V
1.5V
See Figure 1

23

IDT49C401
OUTPUT ENABLE/DISABLE TIMES
(C L = 5pF, measured to O.5V change of VOUT in nanoseconds)
ENABLE
INPUT

OUTPUT

OE

Y

TEST LOAD CIRCUIT

DISABLE

MIL

I

COM'L

22

I

20

MIL
20

I

I

COM'L
18

INPUT/OUTPUT INTERFACE CIRCUIT
Vcc
ESO
PROTECTION
OUTPUTS
OUTPUTS

Figure 2. Input Structure (All Inputs)

Figure 3. Output Structure
(All Outputs Except F
0)

=

Figure 4. Output Structure
(F = 0)

ORDERING INFORMATION
lOT

49C401
Device Type

x
Process/
Temperature
Range

y:~k
'------------1
'-----------------1

8-138

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

C

Sidebraze DIP

Blank
A

16-Bit J.lP Slice
High-Speed 16-Bit J.lP Slice

MICROSLICE ™ PRODUCT

FEATURES:

DESCRIPTION:

• Functionally equivalent to four 2901s and one 2902
• IDT49C402A 45% faster than four 2901s and one 2902A
• Expanded two-address architecture with independent, simultaneous access to two 64 x 16 register files
• Expanded destination functions with 8 new operations allowing
Direct Data to be loaded directly into the dual-port RAM and Q
Register
• Clamp diodes on all inputs provide noise suppression
• Fully cascadable
• 68-pin PGA, Shrink-DIP (600 mil, 70 mil centers) and LCC (25 and
50 mil centers)
• Military product compliant to MIL-STD-883, Class B

The IDT49C402s are high-speed, fully cascadable 16-bit CMOS
microprocessor slice units which combine the standard functions of
four 2901s and a 2902 with additional control features aimed at enhancing the performance of bit-slice microprocessor designs.
The IDT49C402s include all of the normal functions associated
with standard 2901 bit-slice operation: (el) a 3-bit instruction field (la,
h,(2) which controls the source operand selection for the ALU; (b) a
3-bit microinstruction field (13, 14, 15) used to control the eight possible functions of the ALU; (c) eight destination control functions
which are selected by the microcode inputs (Ie ,17, (8); and (d) a tenth
microinstruction input, 19, offering eight additional destination control functions. This 19 input, in conjunction with Ie, hand 18, allows for .
shifting the Q Register up and down, loading the RAM or Q Register
directly from the D inputs without going through the ALU and new
combinations of destination functions with the RAM A port output
available at the Y output pins of the device.
Also featured is an on-chip dual-port RAM that contains 64 words
by 16 bits-four times the number of working registers in a 2901.
The IDT49C402s are fabricated using CEMOS, a CMOS technology designed for high performance and high reliability. These performance enhanced devices feature both bipolar speed and bipolar
output drive capabilities~ while maintaining exceptional microinstruction speeds at greatly reduced CMOS power levels.

Ell
.

'

•

FUNCTIONAL BLOCK DIAGRAM
/"

RAMo
CLOCK
0
1

2
3

4
5

ALU
SOURCE

z
Q
I-

ALU
FUNCTION

6
7 DESTINATION
8
CONTROL

9

Uw

=>8

READ ADDRESS

~U
Zw
_0

0

ex:

U

::E

DIRECT DATAIN

CARRY IN
MSS

DATAoUT
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-9011/-

8-139

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE

PIN CONFIGURATIONS
o

:2:

O~~~~~~~~~~~Oa~~~
9 8 7 6 5 4 3 2 1 68 67 66 6564 63 62 61
D2
D3
D4
D5
D6
D7

10
11
12
13
14
15
GND 16
D8 17
Dg 18
D 10 19
Dll 20
D12 21

A3
A2

A,

Ao
13
14
15
10
I,
12

J68-1.
L68-1
&

L68-2

Vee
OE

D 13 22
D14
D 15
Y15
Y14

80
8,
82
83
84

23
24
25
26
2728293031323334353637383940414243

~~~~~~~~~J;~~~:~m
u.1CJ~O

~:E

LCC/PLCC
TOP VIEW
DIP
TOP VIEW

17
18

Ig
MSS

RAM 15
Q15

Cn +16
t5/0VR

G/F15

F=O

Y9

Y10
Y11
Y12

Y13
Y'4

PGA
TOP VIEW

8-140

Pin 1 indicator
for PLCC

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
PIN NAME

I/O

DESCRIPTION
Six address inputs to the register file which selects one register and displays its contents through the A port.

Aa- A 5

I

80- 8 5

I

Six address inputs to the register file which selects one of the registers in the file, the contents of which is displayed through
the B port. It also selects the location into which new data can be written when the clock goes LOW.

10-1 9

I

Ten instruction control lines which determine what data source will be applied to the ALU I (0, 1,2), what function the ALU will
perform 1(3, 4, 5) and what data is to be deposited in the 0 Register or the register file 1(6, 7, 8, 9). Original 2901 destinations are
selected if 19 is disconnected. In this mode, proper 19 bias is controlled by an internal pull up resistor to Vcc ,

Do -015

I

Sixteen-bit direct data inputs which are the data source for entering external data into the device ALU, 0 Register or RAM. Do is
the LS8.

Ya-Y 15

0

Sixteen three-state output lines which, when enabled, display either the sixteen outputs ofthe ALU or the data on the A port of
the register stack. This is determined by the destination code 1(6,7,8,9).

G/F15

0

A multipurpose pin which indicates the carry generate (G) function at the least significant and intermediate slices or as F15 the
most significantALU output (sign bit). G/F,5 selection is controlled by the MSS pin. If MSS = HIGH, F15 is enabled. If MSS =
LOW, G is enabled,

F= 0

0

Open drain output which goes HIGH if the Fa -F15 ALU outputs are all LOW. This indicates that the result of an ALU operation is
zero (positive logic).

Cn

I

Carry-in to the internal ALU.

Cn +16

0

0 15
RAM 15

I/O

8idirectionallines controlled by 1(6,7,8,9). Both are three-state output drivers connected to the TIL-compatible inPLIts.
When the destination code on 1(6, 7, 8, 9) indicates an up shift, the three-state outputs are enabled, the MSB of the 0 Register is
available on the 0 15 pin and the MSB of the ALU output is available on the RAM 15 pin. When the destination code indicates a
down shift, the pins are the data inputs to the MS8 of the 0 Register and the MSB of the RAM.

00
RAMo

I/O

80th bidirectional lines function identically to 0 15 and RAM 15 lines except they are the LSB of the 0 Register and RAM.

Carry-out of the internal ALU.

DE

I

Output enable. When pulled HIGH, the Y outputs are OFF (high impedance). When pulled LOW, the Y outputs are enabled.

P/OVR

0

A multipurpose pin which indicates the carry propagate (P) output for performing a carry lookahead operation or overflow
(OVR) the Exclusive-OR of the carry-in and carry-out of the ALU MS8. OVA, at the most sign!!!cant end of the word, indicates
that the result of an arithmetic two's complement operation has overflowed into the sign bit. P/OVR selection is controlled by
the MSS pin. If MSS = HIGH, OVR is enabled. If MSS = LOW, P is enabled.

CP

I

The clock input. LOW-to-HIGH clock transitions will change the 0 Register and the register file outputs. Clock LOW time is
internally the write enable time for the 64 x 16 RAM which compromises the master latches ofthe register file. While the clock is
LOW, the slave latches on the RAM outputs are closed, storing the data previously on the RAM outputs. Synchronous
MASTER-SLAVE operation of the register file is achieved by this.

MSS

I

When HIGH, enables OVR and !'i5 on the P/OVR and G/F15 pins. When LOW, enables G and P on these pins. If left open,
internal pullup resistor to Vcc provides declaration that the device is the most significant slice.

DEVICE ARCHITECTURE:
The IDT49C402 CMOS bit-slice microprocessor is configured
sixteen bits wide and is cascadable to any number of bits (16, 32,48,
64). Key elements which make up this 16-bit microprocessor slice
are the (1) register file (64 x 16 dual-port RAM) with shifter, (2) ALU
and (3) Q Register and shifter.
REGISTER FILE-A 16-bit data word from one of the 64 RAM
registers can be read from the A port as selected by the 6-bit A address field. Simultaneously, the same data word, or any other word
from the 64 RAM registers, can be read from the 8 port as selected
by the 6-bit 8 address field. New data is written into the RAM register
location selected by the 8 address field during the clock (CP) LOW
time. Two sixteen-bit latches hold the RAM A port and 8 port during
the clock (CP) LOW time, eliminating any data races. During clock
HIGH these latches are transparent, reading the data selected by the
A and 8 addresses. The RAM data input field is driven from a fourinput multiplexer that selects the ALU output or the D inputs. The
ALU output can be shifted up one position, down one position or not
shifted. Shifting data operations involve the RAM15 and RAMo I/O
pins. For a shift up operation, the RAM shifter MS8 is connected
to an enabled RAM15 I/O output while the RAMo I/O input is selected
as the input to the LS8. During a shift down operation, the RAM
shifter LS8 is connected to an enabled RAMo I/O output while the
RAM15 I/O input is selected as the input to the MS8.

ALU - The ALU can perform three binary arithmetic and five logic
operations on the two 16-bit input words Sand R. The S input field is
driven from a 3-input multiplexer and the R input field is driven from
a 2-input multiplexer with both having a zero source operand. 80th
multiplexers are controlled by the 1(0, 1,2) inputs. This multiplexer
configuration enables the user to select various pairs of the A, B, D,
Q and "0" inputs as source operands to the ALU. Microinstruction
inputs 1(3,4,5) are used to select the ALU function. This high-speed
ALU cascades to any word length, providing carry-in (Cn), carry-out
(C n + 16) and an open-drain (F = 0) output. When all bits of the ALU
0 is oft, allowing a ~ire-OR of
are zero, the pull-down device of F
this pin over all cascaded devices. Multipurpose pins G/F15 and
P/OVR are aimed at accelerating arithmetic operations. For intermediate and least significant slice~ the MSS pin is progra..!J1med
LOW, selecting the carry-generate (G) and carry-propagate (P) output functions to be used by carry lookahead logic. For the most significant slice, MSS is programmed high, selecting the sign-bit (F15)
and the two's complement overflow (OVR) output functions. The
sign bit (F15) allows the ALU sign bit to be monitored without enabling the three-state ALU outputs. The overflow (OVR) output is high
when the two's complement arithmetic operation has overflowed
into the sign bit as logically determined from the Exclusive-OR of
the carry-in and carry-out of the most significant bit ofthe ALU. The
ALU data outputs are available at the three-state outputs Y(a-15)or as

8-141

=

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE
inputs to the RAM register file and Q Register under control of the
1(6,7,8,9) instruction inputs.
Q REGISTER-The Q Register is a separate 16-bit file intended
for multiplication and division routines and can also be used as an
accumulator or holding register for other types of applications. It is
driven from a 4-input multiplexer. In the no-shift mode, the multiplexer enters the ALU F output or Direct Data into the Q Register. In
either the shift up or shift down mode, the multiplexer selects the Q
Register data appropriately shifted up or down. The Q shifter has

two ports, Qo and Q15, which operate comparably tothe RAM shifter.
They are controlled by the 1(6,7,8,9) inputs.
The clock input of the IDT49C402 controls the RAM, Q Register
and A and B data latches. When enabled, the data is clocked into the
Q Register on the LOW-to-HIGH transition. When the clock is HIGH,
the A and B latches are open and pass data that is present at the
RAM outputs, When the clock is LOW, the latches are closed and
retain the last data entered. When the clock is LOW and 1(6, 7, 8, 9) define the RAM as the destination, new data will be written into the RAM
file defined by the B address field.

ALU FUNCTION CONTROL

ALU SOURCE OPERAND CONTROL
ALU SOURCE
OPERANDS

MICROCODE
MNEMONIC
12

10

11

MICROCODE
MNEMONIC

OCTAL
CODE

R

S

15

13

OCTAL
CODE

ALU
FUNCTION

SYMBOL

Aa

L

L

L

0

A

a

ADD

L

L

L

0

R Plus S

R+S

AB

L

L

H

1

A

B

SUBR

L

L

H

1

S Minus R

S-R

za

L

H

L

2

0

a

SUBS

L

H

L

2

R Minus S

R-S

ZB

L

H

H

3

0

B

OR

L

H

H

3

RORS

RVS

ZA

H

L

L

4

0

A

AND

H

L

L

4

RANDS

RAS
RAS

DA

H

L

H

5

D

A

NOTRS

H

L

H

5

RANDS

Da

H

H

L

6

D

a

EXOR

6

REX-OR S

R'V'S

H

H

H

7

D

0

EXNOR

H
H

L

DZ

H
H

H

7

REX-NOR S

R'V'S

ALU LOGIC MODE FUNCTIONS

ALU ARITHMETIC MODE FUNCTIONS
OCTAL

15,4,3, I:z, 1, 0
0
0
0
1
0
5
0
6
0
0
0
0

2
3
4

1
1
1
2

2
3
4

2
2
2
1

2
3
4

1
1
1
1
2
2
2
2

14

Cn

=L

GROUP
ADD

Cn

FUNCTION
A+a
A+B
D+A
D+a

PASS

a
B
A
D

Decrement

a -1
B-1
A -1
D -1

1's Comp,

-a -1
-B -1
-A -1
-D -1

7

7

7
0

1
5
6
0
1

5
6

Subtiact

(1's Comp,)

a BAa AADD-

A-1
A-1
D-1
D-1
a-1
B-1
A-1
a-1

GROUP
ADD
plus one

Increment

=H

OCTAL

FUNCTION
A+ a + 1
A+B+1
D+A+1
D + a + 1
a
B
A
D

+
+
+
+

15 ,4,3,
4
4
4
4

1
1
1
1

PASS

a
B
A
D

2's com),
(Negate

-a
-B
-A
-D

Subtract
(2's Comp,)

a-A
B-A
A-D
a-D
A-a
A-B
D-A
D-a

3
3
3
3

8-142

12 ,1,0

GROUP

AND

AAQ
AAB
DAA
DAa

OR

AVa
AVB
DVA
DVa

EX-OR

A'V'a
A'V'B
WA
D'V'a

0
1

5
6
0
1

5
6

6
6
6
6

0
1

5
6

FUNCTION

A'V'a

7

0

7
7
7

1

5
6

7
7
7
7

2
3
4
7

INVERT

6
6
6
6

2
3
4
7

PASS

a
B
A
D

3
3
3
3

2
3
4
7

PASS

a
B
A
D

4
4
4
4

2
3
4
7

·ZERO·

0
0
0
0

5
5
5
5

0
MASK

AAa
"AB
BAA
BAa

1

5
6

EX-NOR

PS..JJ

D'V'A
D'V'a
a

~

A

D

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SOURCE OPERAND AND ALU FUNCTION MATRIX (1)
12 ,1,OOCTAL
OCTAL

15,4,3

°

ALU
FUNCTION

3

2

1

5

4

6

7

ALU SOURCE
A,B

o,a

O,B

O,A

D,A

D,a

D,O

A+a

A,a

A+B

a

B

A

D+A

0+0

0

0

Cn = L
R Plus S
Cn = H

A+ 0 + 1

A+B+1

0+1

B + 1

A + 1

D+A+1

0+0+1

0+1

o -A-1

B-A-1

0-1

B-1

A-1

A-D -1

0-0-1

-0 -1

1

Cn = L
S MInus R
Cn = H

O-A

B-A

0

B

A

A-D

0-0

-0

A- 0-1

A-B-1

-0 -1

-B -1

-A - 1

o -A-1

0- 0-1

0-1

2

Cn = L
R Minus S
Cn = H

A-O

A-B

-0

-B

-A

D-A

0-0

0

3

ROR S

AVO

AVB

0

B

A

OVA

DVO

0
0

4

RANDS

AAO

AAB

0

0

0

DAA

DAO

5

RANDS

AAO

AAB

0

B

A

DAA

DAO

0

6

REX-OR S

A'V'O

A'V'B

0

B

A

D'V'A

D'V'O

0

7

REX-NOR S

A'V'O

A'V'B

0

B

A

D'V'A

D'V'O

0

NOTE:
1. + = Plus; -

= Minus; A = AND; 'V' = EX-OR; V = OR

ALU DESTINATION CONTROL(1)
RAM
FUNCTION

MICROCODE
MNEMONIC

19

I,

17

18

HEX
CODE SHIFT

o REGISTER
FUNCTION

LOAD

SHIFT

Y
OUTPUT

LOAD

RAM
SHIFTER
RAMo

0
SHIFTER

RAM 15

00

0 15

OREG

H

L

L

L

8

X

NONE

NONE

F-tO

F

X

X

X

X

NOP

H

L

L

H

9

X

NONE

X

NONE

F

X

X

X

X

RAMA

H

L

H

L

A

NONE

F-tB

X

NONE

A

X

X

X

X

RAMF

H

L

H

H

B

NONE

F-tB

X

NONE

F

X

X

X

X

RAMOD

H

H

L

L

C

DOWN

F/2-tB

F

Fa

IN 15

00

IN'5

RAMO

H

H

L

H

0

DOWN

F/2-tB

X

NONE

F

Fa

IN,5

00

X

RAMOU

H

H

H

L

E

UP

2F-tB

UP

20-t0

F

INa

F15

INo

0'5

RAMU

H

H

H

H

F

UP

2F-tB

X

NONE

F

INa

F'5

X

0'5

OFF

L

L

L

L

0

NONE

D-tB

NONE

F-tO

F

X

X

X

X

DFA

L

L

L

H

1

NONE

D-tB

NONE

F-tO

A

X

X

X

X

FDF

L

L

H

L

2

NONE

F-tB

NONE

D-tO

F

X

X

X

X

D-tO

A

X

X

X

X

F

X

X

00

IN 15

DOWN 0/2-t0

FDA

L

L

H

H

3

NONE

F-tB

NONE

XODF

L

H

L

L

4

X

NONE

DOWN 0/2-t0

DXF

L

H

L

H

5

NONE

D-tB

X

NONE

F

X

X

00

X

XOUF

L

H

H

L

6

X

NONE

UP

20-t0

F

X

X

INa

0'5

Existing 2901
Functions

New Added
IDT49C402
Functions

X
X
X
L
H
7
X
NONE NONE D-tO
F
015
XDF
H
H
NOTE:
1. X = Don't Care. Electrically, the shift pin is a TTL input internally connected to a three-state output which is in the high-impedance state.
B = Register Addressed by B inputs.
UP is toward MSB; DOWN is toward LSB.

8-143

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

CAPACITANCE

(1)

COMMERCIAL

MILITARY

-0.5 to +7.0

-0.5 to +7.0

UNIT

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.5

1.5

W

lOUT

DC Output Current

50

50

mA

SYMBOL

Input Capacitance

CIN

V

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CONDITIONS
\IN = OV

COUT
Output Capacitance
VOUT = OV
NOTE:
1. This parameter is sampled and not 100% tested.

TYP.

UNIT

5

pF

7

pF

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
speCification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V ± 5% (Commercial)
Vcc = 5.0V ± 10% (Military)

TA = O°C to + 70°C
TA = -55°C to + 125°C
SYMBOL

TEST CONDITIONS (1)

PARAMETER

\lH

Input HIGH Level

Guaranteed Logic High Level

VIL

Input LOW Level

Guaranteed Logic Low Level (4)

IIH

Input HIGH Current

Vcc = Max., VIN = Vcc

IlL

Input LOW Current

Vcc = Max., \IN = GND

VOH

VOL

Output HIGH Voltage

Output LOW Voltage

Vec = Min.
\IN = \lH or \lL

Vce = Min.
\IN = \lH or \lL

(4)

Off State (High Impedance)
Output Current

Vee = Max.

los

Output Short Circuit Current

Vee = Min., 'lOUT = 0'1 (3)

TYP,(2)

MAX.

UNIT

2.0

-

-

V

-

-

0.8

V

0.1

5

~A

-

-0.1

-5

~A

IoH = -300~A

VHe

Vee

IcH = -12mA MIL.

2.4

4.3

V

IoH = -15mA COM'L.

2.4

4.3

-

IoL = 300~A

-

GND

VLC

IoL = 20mA MIL.

-

0.3

0.5

IcL = 24mA COM'L.

-

0.3

0.5

-0.1

-10

0.1

10

-15

-30

-

Va = OV

loz

MIN.

Vo = Vce (Max.)

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment.

8-144

V

~A

mA

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE

DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = OOCto +70 0 C
TA = -55°C to +125°C
VLC = 0.2V
v HC = vcc -02V
SYMBOL
ICCOH

ICCOL

ICCT

ICCD

VCC = 5.0V ±5% (Commercial)
Vcc = 5.0V ±10% (Military)

TEST CONDITIONS

PARAMETER
Quiescent Power Supply Current
CP = H (CMOS Inputs)

Vcc = Max.
VHC -::; VIH , VIL -::; VLC
fcp = 0, CP = H

Quiescent Power Supply Current
CP = L (CMOS Inputs)

Vcc = Max.
VHC :5 VIH, VIL -::; VLC
fcp = 0, CP = L

Quiescent Input Power Supply(5)
Current (per Input @ TIL High)

VCC = Max. VIH = 3.4V, fcp = 0

Dynamic Power Supply Current

Vcc = Max.
VHC :5 VIH , 'vJL S VLC
Outputs Open, C5E' = L

Total Power Supply Current

TYP.(2)

MIL.

-

150

245

COM'L.

-

150

215

MIL.

-

80

125

COM'L.

-

80

110

MAX.

UNIT
mA

mA

Vcc = Max., fcp = 10MHz
Outputs Open, ()E' = L
CP = 50% Duty cycle
VHC s VIH , VIL -::; VLC
ICC

MIN.

(1)

MIL.

-

0.3

0.6

COM'L.

-

0.3

0.5

MIL.

-

2.0

3.0

COM'L.

-

2.0

2.5

MIL.

-

135

210

COM'L.

-

135

190

MIL.

-

145

225

COM'L.

-

145

200

(6)

VCC = Max., fcp = 10MHz
Outputs Open, C51: = L
CP = 50% Duty cycle
VIH = 3.4V, VIL = O.4V

mAl
Input

mAl
MHz

mA

NOTES:
5. ICCT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out IccoH, then dividing by the total number of inputs.
6. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS or TIL input levels). Forall conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH(CDH) + IccoL (1 - CD H) + ICCT (NT X D H) + ICCD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TIL high period (VIN = 3.4V)
NT = Number of dynamic inputs driven at TIL levels
fcp = Clock Input frequency

3) Device grounding is extremely critical for proper device testing.

CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test environment. Large output currents are being switched in very short
periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing
results:

1) All input pins should be connected to a voltage potential during
testing. If left floating, the device may OSCillate, causing improper
device operation and possible latchup.

The use of multi-layer performance boards with radial decoupiing between power and ground planes is necessary. The
ground plane must be sustained from the performance board to
the DUT interface board and wiring unused interconnect pins to
the ground plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being recommended for minimized inductance.
4) To guarantee data sheet compliance, the input thresholds should
be tested per input pin in a static environment. To allow fortesting
and hardware-induced noise, IDT recommends using VIL :5 OV
and VIH ~ 3V for AC tests.

2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be distributed to
decouple power supply lines and be placed as close as possible
to the DUT power pins.

8-145

EI."

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE

CYCLE TIME AND CLOCK CHARACTERISTICS

IDT49C402A
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of the
IDT49C402A overthe-SSOC to + 12SoCandO°Cto +70 0 Ctemperature ranges. All times are in nanoseconds and are measured
at the 1.5V signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have maximum DC current loads.

Mil.

COM'L

Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)

UNIT

28

24

ns

Maximum Clock Frequency to
shift 0 (50% duty cycle,
I = C32 or E32)

35

41

MHz

Minimum Clock lOW Time

13

11

ns

Minimum Clock HIGH Time

13

11

ns

Minimum Clock Period

36

31

ns

= SOpF

COMBINATIONAL PROPAGATION DELAYS(1) CL

TO OUTPUT
FROM INPUT

(MSS

(MSS.= l)
G, P

Y

= H)

00

RAMo
RAM 15

F=O

C n +18

OVR

F15

0 15

UNIT

MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L. MIL. COM'L.
A. B Address

41

37

39

35

41

37

41

37

37

34

41

37

40

36

-

-

D

32

29

29

26

29

26

31

28

27

25

32

29

28

26

-

-

ns

Cn

28

25

-

-

26

24

25

23

20

18

29

26

23

21

-

ns

10,1,2

35

32

30

27

35

32

34

31

29

26

35

32

30

27

35

32

28

26

34

31

34

31

27

25

35

32

28

26

-

ns

13,4,5

-

9

25

23

-

-

-

-

-

-

-

-

-

-

20

18

20

18

ns

A Bypass
AlU (I
AXX.,
1XX,3XX)

=

30

27

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ns

J

34

31

31

28

33

30

34

31

30

27

34

31

34

31

25

23

ns

Ie, 7, 8,

Clock

ns

ns

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)

INPUT

SET-UP TIME
BEFORE H-+l
MIL

COM'L

A, B Source Address

11

10

B Destination Address

11
_(1)

10

D

~

~

CP:

-

Cn

-

-

10,1,2

-

-

13,4,5

-

-

Ie, 7, 8, 9

11

10

RAMo, 15,00,15

-

-

HOLD TIME
AFTER H-+l
MIL
0(3)

COM'L
0(3)

SET-UP TIME
BEFOREl-+H
MIL

COM'L

21,10 + TPWl(4)

Do not change (2)

-

-

12/22 (5)

10/20 (5)

-

UNIT

MIL.

COM'L

2

1

2

1

ns

2

1

ns

ns

17

15

0-

0

ns

28

25

0

0

ns

28

25

0

0

ns

0

0

ns

0

0

ns

Do not change (2)

-

HOLD TIME
AFTER l-+H

12

11

NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock lOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -+ l transition to allow time to access the source data before the latches close. The A address may then be
changed. The B address could be changed if it is not a destination; i.e" if data is not being written back into the RAM. Normally A and B are not changed
during the clock lOW time.
4. The set-up time prior to the clock l-+ H transition is to allow time for data to be accessed, passed through the AlU and returned to the RAM. It includes all
the time from stable A and B addresses to the clock l-+ H transition, regardless of when the H -+ l transition occurs.
S. First value is direct path (DATA IN -+ RAM/O Register). Second value is indirect path (DATAtN -+ AlU -+ RAM/O Register).

8-146

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CYCLE TIME AND CLOCK CHARACTERISTICS

IDT49C402
AC ELECTRICAL CHARACTERISTICS
(Military and Commercial Temperature Ranges)
The tables below specify the guaranteed performance of the
IDT49C402 over the -SSoC to + 12SoCand O°Cto +70°Ctemperature ranges. All times are in nanoseconds and are measured
at the 1.SV signal level. The inputs switch between OV and 3V with
signal transition rates of 1V per nanosecond. All outputs have maximum DC current loads.

COMBINATIONAL PROPAGATION DELAYS (1)

MIL

COM'L

Read-Modify-Write Cycle (from
selection of A, B registers to end
of cycle)

50

48

ns

Maximum Clock Frequency to
shift 0 (50% duty cycle,
I = C32 or E32)

20

21

MHz

Minimum Clock LOW Time

30

30

ns

Minimum Clock HIGH Time

20

20

ns

Minimum Clock Period

50

48

ns

UNIT

CL = SOpF
TO OUTPUT

FROM INPUT

(MSS = H)

(MSS= L)
G,P

y

F15

00

RAMo
RAM 15

F=O

C n +16

OVR

0 15

UNIT

MIL COM'L MIL COM'L MIL COM'L MIL COM'L MIL COM'L MIL. COM'L. MIL COM'L. MIL COM'L
A, B Address

52

47

47

42

52

47

47

42

38

34

52

47

44

40

D

35

32

34

31

35

32

34

31

27

25

35

32

28

26

-

-

ns

Cn

29

26

-

-

29

26

27

25

20

18

29

26

23

21

-

-

ns

10.1.2

41

37

30

27

41

37

38

35

29

26

41

37

30

27

ns

40

36

28

26

40

36

37

34

27

25

40

36

28

26

-

-

13.4.5

-

ns

Ie. 7. 8. 9

26

24

-

-

-

-

-

-

-

-

-

-

20

18

20

18

ns

A Bypass
ALU (I = AXX.
lXX,3XX)

30

27

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ns

42

38

41

37

42

38

41

37

30

27

42

38

41

37

25

23

ns

Clock

J

-

ns

SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP INPUT)

~

CP:

INPUT

SET-UP TIME
BEFORE H-+L
MIL

COM'L

A, B Source Address

20

18

B Destination Address

20
_(1)

18

10.1.2

-

Is. 4. 5

-

-

Ie. 7. 8. 9

12

11

RAMo. 15.QO.15

-

-

D
Cn

~
HOLD TIME
AFTER H-+L
MIL
0(3)

COM'L
0(3)

SET-UP TIME
BEFORE L-+H
MIL.
50. 20

COM'L.

+ TPW~4)

Do not change (2)

-

-

-

30/40 (5)
35

26/36(5)
32

-

MIL

UNIT

COM'L.

2

1

ns

2

1

ns

2

1

ns

0

0

ns

45

41

0

0

ns

45

41

0

0

ns

0

0

ns

0

0

ns

Do not change (2)

-

HOLD TIME
AFTER L-+H

12

11

NOTES:
1. A dash indicates a propagation delay or set-up time constraint does not exist.
2. Certain signals must be stable during the entire clock LOW time to avoid erroneous operation.
3. Source addresses must be stable prior to the H -+ L transition to allow time to access the source data before the latches close. The A address may then be
changed. The B address could be changed if it is not a destination; i.e., if data is not being written back into the RAM. Normally A and 8 are not changed
during the clock LOW time.
4. The set-up time prior to the clock L-+ H transition is to allow time for data to be accessed, passed through the ALU and returned to the RAM. It includes all
the time from stable A and B addresses to the clock L-+ H transition, regardless of when the H -+ L transition occurs.
5. First value is direct path (DATAIN -+ RAM/Q Register). Second value is indirect path (DATAN -+ ALU -+ RAM/Q Register).

8-147

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C402A
OUTPUT ENABLE/DISABLE TIMES

AC TEST CONDITIONS

ENABLE
INPUT

OUTPUT

OE

Y

MIL

22

I

I

COM'L

20

DISABLE
MIL

I

COM'L

20

I

18

GND to 3.0V

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

(CL = 5pF, measured to O.5V change of VOUT in nanoseconds)

Wins
1.5V
1.5V
See Figure 1

IDT49C402
OUTPUT ENABLE/DISABLE TIMES
(CL = 5pF, measured to 0.5V change of VOUT In nanoseconds)
ENABLE
INPUT

OUTPUT

OE

Y

DISABLE

MIL

I

COM'L

MIL

I

COM'L

25

I

23

25

I

23

TEST LOAD CIRCUIT

Figure 1. Switching Test Circuit (All Outputs)

INPUT/OUTPUT INTERFACE CIRCUIT
Vce
ESD
PROTECTION

OUTPUTS
OUTPUTS

Figure 2. Input Structure (All Inputs)

Figure 3. Output Structure
(All Outputs Except F = 0)

8-148

Figure 4. Output Structure
(F
0)

=

IDT49C402/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CRITICAL SPEED PATH ANALYSIS
Critical speed paths are for the I DT49C402A versus the equivalent bipolar circuit implementation using four 2901Cs and one
2902A is shown below.
The IDT49C402A operates faster than the theoretically achievable values of the discrete bipolar implementation. Actual speed
values for the discrete bipolar circuit will increase due to on-chip/
off-chip circuit board delays.
.

TIMING COMPARISON: IDT49C402A vs 2901Cw/2902A
DATA PATH
(COM'L.)

16-BIT
J-IP SYSTEM

AB ADDR -+ F

=0

DATA PATH
(MIL.)

AB ADDR -+ RAMo, 15

AB ADDR -+ F

=0

UNIT

AB ADDR -+ RAMo, 15

~71

~71

~83.5

~83.5

ns

IDT49C402A

37

36

41

40

ns

Speed Savings

34

35

42.5

43.5

ns

Four 2901 Cs + 2902A

TIMING COMPARISON: IDT49C402 vs 2901C w/2902A
DATA PATH
(COM'L.)

16-BIT
J-IP SYSTEM

AB AD DR -+ F = 0

DATA PATH
(MIL.)

AB ADDR -+ RAMo, 15

UNIT

AB ADDR -+ F = 0

AB ADDR -+ RAMo, 15

~71

~71

~83.5

~83.5

ns

IDT49C402

47

40

52

44

ns

Speed Savings

24

31

31.5

39.5

ns

Four 2901 Cs + 2902A

ORDERING INFORMATION
IDT

XXXXXX

Device Type

X

x

X

Speed

Package

Process!

Tem~~:~NK

PG

SHRINK-DIP Sidebraze
PLCC
Leadless Chip Carrier (50 mil centers)
Leadless Chip Carrier (25 mil centers)
Pin Grid Array
Plastic Pin Grid Array

BLANK
A

Standard Speed
High-Speed

49C402

16-Bit Microprocessor Slice

XC

J
~--------------~ L

XL
G

I.....------------------------i

1.....--------------------------------1

Commercial
(O°C to + 70°C)
Military
(-55°C to +125°C)
Compliant to MIL-STD-883, Class B

8-149

FEATURES:

DESCRIPTION:

• Monolithic 16-bit CMOS ~P Slice
• Replaces four 2903As/29203s and a 2902A

The IDT49C403 is a high-speed, fully cascadable 16-bit CMOS
microprocessor slice. It combines the standard function of four
2903s/29203s and one 2902 with additional control features aimed
at enhancing the performance of all bit-slice microprocessor
designs.
Included in this extremely low power, yet fast IDT49C403 device
are 3 bidirectional data buses, 64 word x 16-bit two-port expandable RAM, 4 word x 16-bit Q Register, parity generation, sign extension, multiplication/division and normalization logic. Additionally,
the IDT49C403 offers the special feature of enhanced byte support
through both word/byte control and byte swap control.
The IDT49C403 easily supports fast 100ns microcycles and will
enhance the speed of all existing quad 2903N29203 systems by
50%. Being specified at an extremely low 225mA, the IDT device offers an immediate system power savings and improved
reliability.
Also featured on the IDT49C403 is an innovative diagnostics
capability known as Serial Protocol Channel (SPC). This on-chip
feature greatly simplifies the task of writing and debugging
microcode, field maintenance debug and test, along with system
testing during manufacturing.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• Fast
- 50% faster than four 2903As/29203s and a 2902
• Low power CMOS
- Commercial: 250mA (max.)
- Military: 275mA (max.)
• Performs binary and BCD Arithmetic
• Expanded two-address architecture with independent,
simultaneous access to two, expandable 64 x 16 register files
•
•
•
•

Word/Byte Control
Expanded 4 x 16 Q Register
Performs Byte Swap and Word/Byte Operation
Fully cascadable without the need for additional carry
lookahead

• Incorporates three 16-bit Bidirectional Busses
• Includes Serial Protocol Channel (SPC TM)
- Flexible on-chip diagnostics
- Serially monitors all pin states
- Reads and Writes to Register File
• High Output Drive
- Commercial: 16mA (max.)
- Military: 12mA (max.)
• Available in 108-pin PGA
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

A
ADDRESS
DA ~----il----""'"

DB

010

ALU
STATUS

a
SIO

~~-+------------+----~

SLICE
CONTROL

---i1.J±2222F=

SPC
CONTROL

y

CEMOS, SPC and MICROSLICE are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
OSC-OOI2/-

1987 Inlegraled Device Technology, Inc.

8-150

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED BLOCK DIAGRAM

AO-5

6

DA O- 15

Cn

Cn + 16

GIN
SIOo

PIOVA

SI015
01~5

0100

OEY
10- 6

[SS

16

Z

~

(O.D)

WIilTE
W/rJ

SCLK
C/O

YO- 15
SDO

8-151

DCMP

Ell

IDT49C403/A 16·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

(@)

®
L
® ®
K
® ®
J
® ®
H
® ®
G
® ®
F
® ®
E
® ®
D
® ®
c ® ®
B
®®
.
A :~'. ®

M

®
®
®
®
®
®
®
®
®
®
®
®

2

PIN
NO.
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
B1
B2
83

NAME

N/C
Vee

OEB
D85
D83
D80
GND
Is
la

GIN
Yo
Vee
12
11
Cn

PIN
NO.
B4
B5
B6
87

NAME
DB7
D84
DB1
MSS

88

17

B9
B10
B11
B12
C1
C2
C3
C4
C5
C6

Cn + 1a
P/OVA
Y1
Y3
DBa
14
GND
10
DB6
D82

3

® ® ®® ® ® ® ® (@)
® ® ®® ® ® ® ® ®
® ® ® ® ®
® ® ®"®
II
II
r-----J
® ® ®
I
I
I
I ® ® ®
I
I
10S-PIN
I
I ® ® ®
P.GA
I
I
I
I ® ® ®
BOTTOM
VIEW
I
I
I
I
I
I ® ® ®
I
I
® ® ®
® ® ® ® ® ® ® ® ®
® ® ® ® ® ® ® ® ®
® ® ® ® ® ® ® ® (@)
r1

L. _ _ _ _ _ ,

L _ _ _ _ _ _ _ _ _ _ _ ..I

4

5

6

7

S

9

10

11

12

PIN
NO.

NAME

PIN
NO.

NAME

PIN
NO.

NAME

PIN
NO.

NAME

PIN
NO.

NAME

PIN
NO.

NAME

C7
C8
C9
C10
C11
C12
D1
D2
D3
D10
D11
D12
E1
E2
E3

DCMP

E10
E11
E12
F1

wis
OEY
SIOo
GND
D815
D814
0100
SI0 15
01015
OEA
DAO
DA1
Yg

H1
H2
H3
H10
H11
H12
J1
J2
J3
J10
J11
J12
K1

DA2
DA3
DA5
Y13

K4
K5
K6

DA8
DA12

Vee

Be

Yll

K8

E34

WE
82
85
01
SCLK

M10
M11
M12

K7

Y10
DA4
DA6

K9
K10
K11
K12
L1

WAITE
GND
SDO

Ys
GND

K3

L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9

15
lEN
Y2
Y5
Ya
D811
D89
13
Y4
Y7

Z
DB13
DB12
D810

F2
F3
F10
F11
F12
G1
G2
G3
G10
G11
G12

K2

8-152

A1
SDI
Y 14
Y12
DA7
Ao
A3

L2
L3
L4
L5
L6

N/C

Y15
A2
A4
DA9
DA11
DA14

ISS

ci5
Vee
A5
DA10
DA13
DA15
GND
CP
B1
83

C\J
N/C

IDT49C403/A H)-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
PIN NAME

DESCRIPTION

1/0

AO-5

I

Six address inputs to the RAM containing the address of the RAM word appearing at output port A.

8 0- 5

I

Six address inputs to the RAM which selects one of the words in the RAM, the contents of which is displayed through
the 8 port. It also selects the location into which new data can be written when the WE input and CP input are low.

DAo-15

I/O

Sixteen bi-directional data pins acting as operands R for entering external data into the ALU. DA a is the LSB. The DA
lines also function as an external output for RAM port A.

DBo-15

I/O

Sixteen bi-directional data pins for entering external data into the ALU. The DB lines act as either RAM port B output
data, or as input operands S to the ALU.

WE

I

The RAM write enable input, which when LOW causes the Y I/O port data to be written into the RAM when the CP input
is low. When WE is HIGH writing data into the RAM is inhibited.

OEA

I

Output enable, which, when HIGH selects DAo-15 as the ALU R operand, and, when LOW, selects RAM output A as the
ALU R operand and the DA O- 15 output data.

OEB

I

Output enable, which, when HIGH selects DB o- 15 as the ALU S operand, and, when LOW, selects RAM output 8 as the
ALU S operand and the DB o_15 output data.

SlOe
51015

I/O

Bidirectional serial shift inputs/outputs for the ALU shifter. SIO ill an input and SIO 15is an output during a shift-up operation.
51015 is an input and 5100 is an output during a shift-down operation. Refer to Tables 4 (a, b, c, d) and 5 for an exact
definition of these pins.

OIOe
01015

I/O

Bidirectional serial shift inputs/outputs for the 0 registers shifter. They operate like SIO o and 510 15 pins. Refer to
Tables 4 (a, b, c, d) and 5 for an exact definition of these pins.

Cn

I

Carry-in input to the ALU.

lEN

I

Instruction enable input. When LOW, it enables writing into the q~ister and the Sign Compare flip-flop. When HIGH,
the 0 register and the Sign Compare flip-flop are in hold mode. lEN does not affect WRITE, but internally disables the
RAM write enable.

LSS

I

Input p-in, when held LOW, causes the chip to act as either stand alone slice (SA) or the least significant slice (LSS),
When LSS is held HIGH, the chip acts as either an intermediate slice or most significant slice.

MSS

I

Input pin, when held LOW, programs the chip to act as either stand alone slice (SA) or the most significant slice (MSS),
and holding it HIGH programs the chip to act either as an intermediate slice (IS) or the least significant slice (LSS).

0

The WRITE signal is LOW when an instruction which causes data to be written into the RAM is being executed. This pin
is normally connected to the WE pin.

Cn + 16

0

This output indicates the carry out of the ALU. Refer to Tables 6a and 6b for an exact definition of this pin.

Z

I/O

An open drain bidirectional pin. When HIGH it indicates that all outputs are LOW. Z is used as an input pin for some
special functions. Refer to Tables 6a and 6b for an exact definition of this pin.

WRITE

G/N

0

G indicates the carry generate function at the least significant and intermediate slices, and indicates the sign, N, of the
ALU result at the most significant slice. Refer to Tables 6a and 6b for an exact definition of this pin.

OEV

I

A control input pin. When LOW the ALU shifter output data is enabled onto the Va-Is lines. When HIGH the VO- 15
three-state output buffers are disabled.

CP

I

Clock input. The Sign Compare flip-flop and the 0 register are clocked on the LOW-to-HIGH transition of the CP signal.
WhenWE and CP are LOW, data is written into the RAM.

J5'/OVR

0

J5' indicates the carry propagate function at the least significant and intermediate slices, and indicates the conventional
two's complement overflow, OVR, signal at the most significant slice. Refer to Tables 6a and 6b for an exact definition
of this pin.

Vo- 15

I/O

Sixteen bi-directional data pins. Controlled by OEY input, the ALU shifter output data can be enabled onto these lines, or
external data is written directly into the RAM using these lines as data inputs.

10- 8

I

The nine instruction inputs used to select the IDT49C403 operation to be performed.

0 0- 1

I

Two address pins to select one of the four 0 registers.

w/S

I

Word/sytS control pin. Used only in the standard function mode, it selects Word mode when held HIGH and Byte mode
when held LOW. Must be tied HIGH when the special functions are being used.

SDI

I

Serial Data Input pin, used for receiving diagnostic data and commands from a host system or from the SDO pin of a
cascaded processor.

SDO

0

Serial Data Output pin, used for transmitting diagnostic data and commands to a host system or a cascaded processor
via its SDI pin.

C/O

I

Input pin, when LOW defines the bit pattern being received at the SDI pin as Data, and when HIGH defines the incoming
pattern as a Command for executing diagnostic functions. This pin shOUld be tied HIGH when the diagnostics feature is
not being used.

SCLK

I

Input pin used for clocking in diagnostic data and command information at the SDI pin. This pin should be tied LOW
when the diagnostics function is not being used.

DCMP

0

Output pin, which, when HIGH indicates that the internal comparison between the V or 0 bus data and the data from
the diagnostics data register resulted in a TRUE (they were equal). This feature is used for breakpoint detection. It is an
open-drain pin and can be wire AND with other DCMP pins.

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MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

Table 2 IDT49C403 ALU Functions(l)

DEVICE ARCHITECTURE

14

The IDT49C403 CMOS microprocessor slice is configured sixteen bits wide and is cascadable to any number of bits (32, 48, 64,
etc.). Key elements which make up this sixteen-bit microprocessor
slice are: (1) the RAM file (a 64 x 16 dual-port RAM) with latches on
both outputs. (2) a high-performance ALU with shifter, (3) a flexible
Q register file (4 x 16 bits) with shifter input, (4) a nine-bit instruction
decoder, and (5) Serial Protocol Channel.
The IDT49C403 incorporates Serial Protocol Channel (SPC TM).
For system testing and debugging purposes SPC is a method by
which data can be entered into and extracted from a device
through a serial data input output, thus providing access to all internal registers.

REGISTER FILE
The Register File is composed of 64 x 16 bit RAM locations. The
RAM data is read from the A-port as controlled by the 6-bit A address field input. Simultaneously, data can be read from the B port
as defined by the 6-bit B address field input. If the same address is
applied at both the A input field and the B input field, identical data
will appear at the tW...Q..Lespective output ports. Data is written into
the RAM when WE,IEN and the clock CP are LOW. Both the RAM
output data latches are transparent while CP is HIGH and latch the
data when CP is LOW. The three-state output enable OEB allows
RAM B port data to be read at the DB I/O port, while OEA performs
the same function for the A port data at the DA I/O port.
New data is written into the RAM word defined by the B address
field. External data at the Y I/O port can be written directly into the
RAM, or the ALU shifter output data can be enabled onto the Y I/O
port and written into the RAM.

13

12

11

ALU FUNCTIONS

10
L

Special Functions

L

L

L

L

L

L

L

L

H

~

L

L

L

H

X

F=S-R-1+Cn

= HIGH

L

L

H

L

X

F=R-S-1+Cn

L

L

H

H

X

F=R+S+C n

L

H

L

L

X

F=S+C n

L

H

L

H

X

F=S+C n

L

H

H

L

L

Reserved Special Functions
F=R+C n

L

H

H

L

H

L

H

H

H

L

Reserved Special Functions

L

H

H

H

H

F=R+C n
Special Functions

H

L

L

L

L

H

L

L

L

H

~ = LOW

H

L

L

H

X

FI=RANDS

H

L

H

L

X

F1 =RI EXCLUSIVE NOR SI

H

L

H

H

X

F) =R I EXCLUSIVE OR 8 1

H

H

L

L

X

~

=R I AND 8 1

H

H

L

H

X

~

=RI NOR 8 1

H

H

H

L

X

F1 =RI NAND 8 1

H

H

H

H

X

~=RIORSI

NOTE:
1. L=LOW, H=HIGH, i=O to 15, X=Don't Care

ALU
The ALU can perform seven arithmetic and nine logiC operations on the two 16-bit input words Sand R. Multiplexers at the ALU
inputs allow selection of various pairs of ALU source operands.
The OEA input selects either external DA data or RAM A port output
data as the 16-bit R source operand. The OEB and 10 inputs provide selection of either RAM B port output, external DB data orthe
Q register file output as the 16-bit S source operand. Also, during
certain ALU operations, zeroes are forced at the ALU operand inputs. Thus, the ALU can operate on data from two external sources,
from an external and an internal source, or from two internal
sources. Table 1 shows all possible pairs of source operands as
selected by OEA, OEB, and 10 inputs.

The IDT49C403 may be cascaded in either a ripple carry or
carry lookahead fashion. When configured as cascaded ALUs, the
IDT49C403s must be programmed to be a most significant slice
(MSS), an intermediate slice (I~ or a least significant slic~ (LSS) of
the array. The carry generate, G, and carry propagate, P, signals
that are necessary in a cascaded system are available as outputs
on the IDT49C403 least significant and intermediate slices.
The IDT49C403 provides a carry-out signal C n + 16 which is
available as an output of each slice. The carry-in, Cn, and carry-out,
C n + 16, are both active HIGH. Two other status outputs are generated by the ALU. These are the negative, N, and the overflOW, OVR.
The N output indicates positive or negative results, while the OVR
output indicates that the arithmetic operation performed e~ceeded
the available two's complement range. Thus the pins G/N and
f5/0VR indicate carry generate or propagate on the least significant
and intermediate slice, and sign and overflow on the most significant slice.
Refer to Tab!es 5a and 5b fer an exact definition of these faui
signals.

Table 1. ALU Operand Sources(l)
OEA

10

OEB

ALU OPERAND R

L

L

L

Ram Output A

ALU OPERAND S
Ram Output 8

L

L

H

Ram Output A

D80-15
Register

L

H

X

Ram Output A

Q

H

L

L

DAo-15

Ram Output 8

H

L

H

DAo-15

D8 0- 15

H
H
X
DAo-15
NOTE:
1. L = LOW, H = HIGH, X = DON'T CARE

ALU DESTINATION CONTROL
The following tables show how the shifter at the output of the
ALU should function for non-special instructions. The main addition with respect to the IDT39C203 is the built in byte capability.
The 49C403 has two write enables internally. One for the upper
byte and one for the lower byte. The enable~re controlled by the
instruction decode, external WE and the W/B input. For convenience to the user. the unused bits on the Y bus (MSB, ...... 8) are
zero during ~eration. The WE input must be directly connected to the WRITE output, or indirectly through some amount of
gating (I.e., expansion RAM decoding gates).

Q Register

The ALU performs special functions when instruction bits 13,12,
I, , and 10 are LOW. Table 5 defines these special functions and the
operation which the ALU performs for each. When the ALU executes instructions other than the special functions, the operation is
defined by instruction bits 14, 13,12, and 11. Table 2 defines the operation as a function of these four instruction bits.

8-154

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The sign extend function is an exception to the rule with regard
to the internal byte write enables. When executed, all of the write
enables are active, irrespective of W/B. In the SA and LSS slices,
the contents of bit 7 is replicated on bits 8 to 15 and SI015 in the byte
mode. In the word mode bit 15 is placed on S1015. In this wayan
8-bit word (byte) or a 16-bit word can be extended to the entire
width of the native data path. Extends of larger words than these,
such as 24 and 32 bits, can be achieved by steering the MSS and
LSS inputs of the IS slices to inform which device has the sign bit to
extend. As Sign Extend requires internal gating ofthe write enables
to the upper and lower portions of RAM, the instruction will not work
with locations in memory expansion RAM.

shift operation shifts the data around the most significant (Sign) bit
of the most significant slice and a logical shift operation shifts the
data through the most significant bit. Figure 1 shows these shift
patterns. The SIOo and SI015are bidirectional serial shift inpuVoutput pins. During a shift-up operation, SIOo is generally an input
while SI015 is an output, whereas during a shift-down operation
SIOo is generally an output while SI015 acts as an input. Refer to
Tables 4 (a, b, c, d) and 5 for an exact definition of these pins.
The ALU shifter also provides sign extension and parity generating/checking capabilities. Under instruction control, the SIOo
(Sign) input can be extended through Yo, Yl, Y2, ..•..Y15and propagated to the SI015 output. A cascadable, five-bit parity generator/
checking generates parity for the Fo, Fl, F2, ..... F15 ALU outputs
and SI015 input and, under instruction control, is made available at
the SIOo output.

ALU SHIFTER
The ALU shifter shifts the ALU output data under instruction
control. It can shift up one bit position (2F), shift down one bit position (F/2), or pass the ALU output non-shifted (F). An arithmetic

ARITH.
BYTE
OPERATION

SI~5 ......--;::::o=o==o=o=o=o==o=o::::;:=N=:;::I::J'...~.. ~.'. .~'.....~''''.';~''';::~>~>~<~>~>~>~Hr SIOo
MSB

[

LOG.

8

7

6

0

SI~5 ......-----;;::::::========::;:::~~~~.. ~. '.;_.;...;.~.";. ~.;'.;,~': ":'~":,.: .~:•.•.;.,:.,.'.. ~.:,. .•,:,~,..:.:.,.,.,"..':•..•.~.:,':,
MSB

8

WORD
OPERATION

LOG.

,

r---

SIOo

==N==I<=/:····====================="'=,·,·:,:=,:,"":=':':"'=:i=i~\~~

MSB
[

SIOo

o

7

SI~5 ......1 - - - - - - - ,

ARITH.

r---

~

I>

....0

14

SI~5YL;;.•

~)r SIO

o

,;;;;;t';;;;;:·';;;;;;.;;;;;;;;;;;.;;;;;.;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.;;;;;;;;;;;.;;;;;.;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;.;;;;;;;.;.;
....

MSB

0

Figure 1. IDT49C403 Arithmetic and Logical Shift Operations

Table 5 defines the special functions and the operation the ALU
shifter performs for each instruction. For instructions other than the
special functions, the ALU shifter operation is determined by instruction bits 18, 17, Ie, and 15. Table 4 (a, b, c, d) defines the ALU
shifter operation as a function of these four bits.

shifts. It can shift-up the data one bit position (20) or down one bit
position (0/2). For a shift-up operation, 0100 acts as an input while
01015 acts as an output; whereas, for a shift-down operation, 0100
is an output and 01015 is an input. By connecting 01015 of the most
significant slice to SIOo of the least significant slice, double-length
arithmetic and logical shifting is possible with cascaded
IDT49C403s.
The 00 and 01 inputs enable selection of anyone of the four
16-bit 0 register files. Once a specific 0 register has been selected,
access to the other three 0 registers is disabled and can be
gained only after changing 00 and 01 levels to enable a different a
register.
Table 5 defines the special functions and the operations which
the a register and shifter perform for selected instruction inputs.
While executing instructions other than the special functions, the
register and shifter operation is controlled by instruction bits 18,17,16
and 15. Table 4 (a, b, c, d) defines the 0 register and shifter
operation as a function of these four bits.

WORD/BYTE CONTROL AND BYTE SWAP
In addition to the special ALU functions, the IDT49C403 also
provides a Word and Byte control and Byte Swap features.
The W/Bpin at the Instruction Decoderlnput selects ALU operation on either a Word or a Byte. When W/B is HIGH, the ALU operates on a Word and, when W/Bis LOW, the ALU operates on a Byte.
Table 4 (a, b, c, d) shows the ALU Destination Controls for Word
and Byte operations for each instruction mode.
The Byte Swap special function allows the positions of the Upper and Lower bytes to be swapped before entering them as the
ALU S operand. The ALU function then adds C n to this swapped
word as its F output. Table 5 shows the instruction set that allows
the ALU to operate the Byte Swap feature.

a

INSTRUCTION DECODER

a REGISTER FILE

The internal control signals necessary for the operation of the
IDT49C403 are generated by the instruction decoder as a function
2!..!he nine instruction inputs, 10-8; the ingruction enable input,
lEN; the LSS input; the MSS input; the W/B input and the WRITE
output.
The WRITE output is LOW when an instruction which writes data
into the RAM is executed. Refer to Tables 4 (a, b, c, d) and 5 for

The 0 register is a separate 4-word by 16-bit file intended primarily for multiplication and division routines and can also be used
as an accumulator or holding register for other types of applications. The ALU output, F, can be loaded into the 0 register and/or
the 0 register output can be selected as one of the ALU S operands. The shifter at the input to the 0 register performs only logical

8-155

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

ment, non-restoring divide operation. They provide single and
double-precision divide operations and can be performed in "n"
clock cycles (where "n" is the number of bits in the quotient).
The unsigned multiply special function and the two two's complement multiply special functions can be used to multiply two
n-bit, unsigned or two's complement numbers respectively, in 'n'
clock cycles. During the last cycle of the two's complement multiplication, a conditional subtraction rather than addition is performed due to the fact that the sign bit of the multiplier carries negative weight.
The sign/magnitude-two's complement special function can
be used to convert number representation systems. A number
expressed in sign/magnitude representation can be converted to
the two's complement representation, and vice-versa, in one clock
cycle.
Incrementing an unsigned or two's complement number by one
or two is easily accomplished using the increment by one or two
special function.
In addition to BCD arithmetic special functions to add or subtract two BCD numbers, a BCD divide by two adjust instruction
can be used to obtain a valid BCD representation after shifting a
number down by one bit.
The BCD/Binary conversion special function instructions permit
single and double-precision algorithms to convert from BCD-toBinary and from Binary-to-BCD.
The Byte Swap feature allows the swapping of Lower and Upper
bytes of a word before presenting them as the ALU S operand. The
ALU then adds the carry C n to this swapped word to form its F output. This feature functions only for the ALU S operand.

a definition of the WRITE output as a function of the instruction
inputs.
When lEN is HIGH, the WRITE output is forced HIGH and the Q
regist~nd Sign Compare Flip-Flop contents are preserved.
When lEN is LOW, the WRITE output is enabled and the Q register
and Sign Compare Flip-Flop can be written according to the
IDT49C403 instruction. The Sign Compare Flip-Flop is an on-chip
flip-flop which is used during a divide operation. See Figure 2.

R"?~'~

SPECIAL
FUNCTION
AORC

TE"fJ

D

Q

~ ~lg~PARE
Figure 2. Sign Compare Flip-Flop

SLICE POSITION PROGRAMMING
The IDT49C403 can be programmed to operate in either a cascaded application or in the standalone mode. Table 3 shows its
four programmed modes.

Table 3. SLICE Programming
SLICE PROGRAM INPUTS

MSS

rss

MODE OF OPERATION

LOW

LOW

Stand Alone Slice (SA)

SERIAL DIAGNOSTICS

LOW

HIGH

Most Significant Slice (MSS)

HIGH

HIGH

Intermediate Slice (IS)

HIGH

LOW

Least Significant Slice (LSS)

The Serial Protocol Channel ™ (SPC) is a flexible on-chip feature of the IDT49C403 and is a set of pins by which data can be
entered into and extracted from a device through a serial data input
and output port.
SPC can be used at many pOints in the life of a product fordiagnostic purposes such as system level design debug and development; system test during manufacturing and field maintenance debug and test. It allows for observation of critical signals deep within
the system. During system test, when an error is observed, these
signals may be modified in order to zero in on the fault in the system. Serial diagnostics is primarily a scheme utilizing only four
pins to examine and alter the internal state of a system for the purpose of monitoring and diagnosing system faults.

SPECIAL FUNCTIONS
Seventeen special functions are provided on the IDT49C403
which permit the implementation of the following operations:
• Single and Double Length Normalization
• Two's Complement Division
• Unsigned and Two's Complement Multiplication

Detailed SPC Architecture of the IDT49C403 BitSlice Microprocessor

• Conversion Between Two's Complement and Sign/Magnitude
Representation
• Incrementation and Decrementation by One or Two

The IDT49C403, a quad Am2903/29203 16-bit microprocessor
slice, which includes an ALU and register file, is one of the devices
on which lOT has incorporated the Serial Protocol Channel. The
implementation of SPC on the IDT49C403 is shown in Figure 3.
Only four SPC pins (SOl, SOD, SCLK and C/O) are used to
serially access the I/O pad cells, as well as the internal ALU
registers and buses. To control or monitor a section (such as the
ALU), the appropriate command is loaded into the SPC command
register. The desired function is then executed and the status
information captured in the data register. The status information
can then be serially shifted out and observed to verify proper
system functionality.

• BCD Add, Subtract, and Divide by Two
• Single and Double-precision BCD-to Binary and Binary-to-BCD
Conversion
• Byte Swap
Adjusting a single-precision or double-precision floating-point
number in order to bring its mantissa within a specified range can
be performed using the single-length and double-length normalization operations.
Three special functions can be used to perform a two's comple-

8-156

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLlCS"

I/O PAD CELL

RAM

Q
REG

r+

cm

MUX

COMMAND

DATA

SOl

SCLK

SDO

~

Figure 3. Conceptual Diagram of IDT49C403 Die Incorporating SPC Scan Path

The block diagram in Figure 4 shows the detailed SPC architecture for the IDT49C403. It primarily consists of serial registers for
command, data, addresses and decode/control logic. The SPC
command register consists of a four-bit field (signals 4-7) and four
discrete control lines (Signals 3, 2, 1,0). The four-bit field coordinates the transfer of data between RAM and the SPC data register,
as well as controls an on-chip break detect mechanism. The other

discrete signals control the serial scan path through the I/O cells.
The SPC data register is in series with a RAM address register
and I/O pad scan. The SPC data register is connected to the internal bus to gain access to the RAM register file as well as a data
break point feature. The point of connection is the Y bus from the
ALU back into the RAM.

8-157

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

SDI

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SPC COMMAND REGISTER

7-4

SDO

2

Cll)
BYPASS
SCLK

READ

STROBES

16

Figure 4. Internal Organization of the SPC

The multiplexer at the output transmits information via the SDO
pin selecting data from either the SPC data register and the I/O
pads or the command string from the SPC command register.

reserved. Bits 4 through 7 form the opcode field for reading and
writing into the device.
The 4-bit command opcode field gives 16 possible command
opcodes. The first 8 are reserved for writing data from the SPC data
register into the registers and RAM on the device. The second
8 opcodes are reserved for reading data from registers and RAM
into the 16-bit SPC data register.

IDT49C403 SPC Command Opcodes
The SPC command register consists of an 8-bit field, as shown
in Figure 5. Bit 1 enables the READ function of the I/O pad cells. Bit
3 enables the BYPASS function to bypass the I/O pad cells and
scan out only the RAM address and data registers. Bits 0 and 2 are
COMMAND OPCODES
OPCODE
0
1
2
3
4
5
6

7

FUNCTION
Write RAM
Write
Registers
Write Break Control
Write Break Data
Reserved
Reserved
Reserved
Reserved

RESERVED

a

' - - - - - READ
L...-_ _ _ _ _ RESERVED
' - - - - - - - - BYPASS

COMMAND
OPCODES

'--__________

8
9
10
11
12
13
14
15

Read RAM
Read
Registers
Read Break Control
Read Break Data
ViewY
Reserved
Reserved
NOP

a

}
~-------------------------

Figure 5. SPC Command Register and Opcodes for the IDT49C403

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IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The command with opcode 0 causes a write to the internal
device RAM. Opcode 1 is used to write to the Q registers.
Opcodes 2 and 3 are used to write data from SPC data register into
the break data register and break control registers, respectively.
Opcodes 4 through 7 are reserved opcodes.
Opcode 8 is used for reading RAM data into the SPC data register. Opcode 9 is used to read a value out of the Q registers. (Here,
also, the address register supplies the address of the Q register to
be accessed). Opcodes 10 and 11 are used for reading the break
control register and the break data register, respectively.
Opcode 12 is used to strobe data from the Z bus into the 16-bit
diagnostics data register. Opcodes 13 and 14 are reserved opcodes. The last opcode, 15, is a no-operation opcode. This opcode
can be used to scan the data in and out of the I/O pad cells and use
the device in a pass-through mode (in a cascaded application)
without affecting normal device operation.
All the reserved opcodes, if executed, perform a no-operation;
however, they should not be relied upon to always perform NOPs
as future upgrades may make use of reserved opcodes.

lowered and the SCLK line is raised. This is the strobe which
actually clocks the data into the RAM or register in the device.

Pad Cell Scan Path
Each I/O cell on the IOT49C403 contains a flip-flop which can
be used to store the state of that cell and then be scanned out.
Figure 6 shows the logic configuration. The READ line is enabled
by a bit in the SPC command register and gated by the XFER signal, thus loading the scan flip-flops in parallel. The SCLK is then
used to scan the data out of the SOO pin in series with the address
and SPC data registers.
SDO

INTERNAL
CORE CIRCUITRY

Accessing the Contents of the IDT49C403 Register File
To read data from the device's internal RAM or other logic circuitry into the SPC data register, the address and don't care bits
(for the SPC data register) are shifted in. The command is shifted
into the SPC command register. The command register must be
decoded to determine what data paths are to be steered in order to
get data into the SPC data register. The read strobe, generated by
the strobe logic, must then strobe this data (in parallel) into the SPC
data register. The data can now be shifted out via the SOO pin and
its contents disassembled and observed.
To perform the write operation, address and data must first be
shifted into the SPC data register. The command is then shifted into
the SPC command register via the command mode. This register
provides information as to what data paths are to be steered. The
address is supplied by the address register in the data scan path.
The write strobe is then generated between the time the C/O line is
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Y15
Y14
Y13
Y12
Y11
Y10
Y9
YB
01015
SI015
0100
SIOO
OEY
Z
W/B

Y7
Y6
Y5
Y4
Y3
Y2
Y1
YO

IEi"J
PIN

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

SCLK

READ

SDI

Figure 6. Serial Scan in the I/O Cell

The BYPASS bit in the SPC command register selects whether
the shifting of the I/O cells will be bypassed such that only the RAM
address and data registers are scanned out. When the READ bit is
HIGH, data is transferred from the pins to the scan register when
SCLK transitions HIGH after C/D has transitioned LOW. The
BYPASS bit inthecommand register is active HIGH so that a HIGH
level bypasses scanning the I/O cells.
Figure 7 shows the order in which the I/O pad cells are scanned.
The clocking will shift out the data on the Y'5 pin first and continue
in series until the WRITE pin is shifted out last.

GIN
CN16
15
16
17
18
DCMP
MSS
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
OEB
CN
10
11
12
13
14
DB8
DB9

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74

DB10
DB11
DB12
DB13
DB14
DB15

OEA
DAD
DA1
DA2
DA3
DA4
DA5
DA6
DA7
AD
A1
A2
A3
A4
A5
DA8
DA9
DA10
DA11

Figure 7. Shift Order of I/O Pad Cells

8-159

75
76

77
78
79
80
81
82
83
84
85
86
87
88
89
90

DA12
DA13
DA14
DA15
[SS
CP

WE
BO
B1
B2
B3
84
85
00
Q1

WR"i"IT

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

Y

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Q

Grn~---I
CP

B

16
TO
DIAGNOSTIC
4--------+------~------------~
DATA
REGISTER

Figure 8. Breakpoint Detect Circuitry
latched equal-to, Vee or GNO. The latched equal-to input into the
multiplexer gives the user the ability to pipeline the match signal,
thus shortening the system cycle time in the diagnostics mode.
The Vee and GNO inputs to the multiplexer allow the programmer
to disable the break compare feature by forcing the OCMP pin
either LOW or HIGH, respectively.
When a match is made, the OCMP line goes HIGH. Thus, if any
one slice in a cascade application does not match, the wire-ANOed
OCMP will be low. Selecting Vee via the multiplexer will disable
matches altogether. To select GNO, disable anyone slice from the
comparison.
Figure 9 shows the format of the break data and break control
register. The break data pattern is 16 bits wide, with bit 16 being the
most significant bit and last to be shifted in. The Break Control register contains three fields. Bits 0 and 1 control the OCM P output and
bit 2 selects between the Y and the Q bus to be compared with the
break data register. Bits 3 to 15 are reserved for future expansion.

Breakpoint Detection on the IDT49C403
Figure 8 shows the diagnostics breakpoint detection circuit on
the lOT49C403. This circuit is designed to allow the user to monitor
certain key data buses and detect the data patterns on the Y and Q
buses. When a data pattern is detected, a breakpoint compare signal is generated on the OCMP pin and is used to halt the system
operation. The OCMP is an open drain signal and should be wireORed with OCMP lines of other similar devices and monitored by
the main sequencer in the system. The breakpoint detection
mechanism thus allows for an easier debug of microcode with regard to the data path.
At the heart of the breakpoint detection circuit is a comparator
which compares data from the break data register with data from
either the Y bus orthe Q bus. The break control register determines
which of the two buses is selected for a comparison. The break
control register also steers a multiplexer at the output of the
comparator. This multiplexer selects between the equal-to signal,
BREAK DATA
REGISTER FORMAT

15

I

BREAK CONTROL
REGISTER FORMAT

0

BREAK DATA PATTERN

3

15

I

2
BUS

SEL

1

BREAK POINT CONTROL ACCESS
BUS SEL

BUS

0
1

Y
Q

DCMP CONTROL

0
0
1
1

0
1
0
1

DCMP STATUS
LOW
PIPELINED
NON-PIPELINED
HIGH

Figure 9. Breakpoint Control Registers and Opcodes

8-160

0

DCMP
CONTROL

I

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

store can be initialized through the SPC path. A register with SPC is
used for the instruction register going into the IOT49C410 (1B-bit
microprogram sequencer) as well as data registers around the
IOT49C403. In this way, the designer may use the Serial Protocol
Channel to observe and modify the microcode coming out of the
writable control store, as well as observing and being able to modify data and instructions in the overall machine.
The block diagram of the diagnostics ring shows how the devices with diagnostics are hooked together in a serial ring via the
SOl and SOO signals. The diagnostics signals may be generated
through registers which are hooked up to a microprocessor. This
microprocessor could conceivably be an IBM PC.

The SPC version allows data to be transferred into and out of a
device and can also accommodate addresses and commands using the same number of pins. This is accomplished with a reconfiguration of the function of the diagnostic pins and internal logic.
With this vastly expanded capability, SPC can conveniently be
used in RAMs, peripherals an complex logic functions. These new
capabilities allow the user to monitor and modify all of the storage
elements and pins of a device. With a simple hardware interface
and appropriate software, any type personal or mini computer
can be turned into a development system for lOT parts with serial
diagnostics.
Figure 10 shows the Serial Protocol Channel being used with a
writable control store in a microprogrammed design. The control

WCS
IDT7198

(16Kx4)

._-------I
I

Figure 10. Typical Microprogram Application with SPC

8-161

-------------_._--,---

"---"-

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

Table 4a. ALU Destination Control (Word Mode) for 10 or I, or 13
I, 17 Ie 15

ALU SHIFTER
FUNCTION

HEX

Arith.

F/2~

Y

0

L L L H

Log.

F/2~

Y

1

L

L H L

Arith.

F/2~

Y

2

L

L H H

Log.

F/2~Y

3

L

H L L

F~Y

4

L H L H

F~Y

5

L

H H L

F~Y

6

L

H H H

F~Y

7

2F~

MSS

SA

L L L L

= HIGH, lEN = LOW

S10'5
LSS

IS

Input

.

SIOo

WRITE

o REGISTER
AND SHIFTER
FUNCTION

0100

010'5

Fa

L

Hold

Z

Z

I
I

L

Hold

Z

Z

Parity

L

Log.

0/2~0

Input

00

L

Log.

0/2~0

Input

00

Hold

L

0/2~0

Log.

H

Z

Z

Input

00

H

F~O

Z

Z

L

F~O

Z

Z

L

Hold

Z

Z

H L L L

Arith.

Y

8

F,4

F,4

H L L H

Log.2F-+Y

9

F-i5

F-i5

L

Hold

Z

Z

H L H L

Arith. 2F -+ Y

A

Log. 20 -+0

0'5

Input

Log. 2F-+ Y

B

~4
~5

L

H L H H

~4
~5

L

Log. 20-+0

0'5

Input

H H L L

F~Y

C

Hold

Z

Z

H H L H

F-+Y

D

~

H
H

Log. 20-+0

0'5

Input

SIOo

L

Hold

Z

Z

F-i5

L

Hold

Z

Z

H H H L

Sign Extend

H H H H

j

E

F~Y

F

F'5

SIOo
F'5

F'5

Table 4b. ALU Destination Control (Byte Mode) for 10 or I, or 13
ALU
I, 17 Is 15 SHIFTER HEX
FUNCTION

SA

L L L L Arith. F/2-+Y

0

Input

F/2~Y

1

L L H L Arith. F/2-+Y

2

F/2~Y

3

L H L L

F~Y

4

L H L H

F-+Y

5

L H H L

F-+Y

6

L H H H

F-+Y

7

H L L L Arith. 2F-+Y

8

F6

H L L H Log. 2F-+Y

9

F,

2F~Y

A

H L H H Log. 2F-tV

B

H H L L

F-+V

C

H H L H

F-+V

D

H H H L Sign Extend

E

H H H H

F

L L L H Log.
L L H H Log.

H L H L Arith.

F-+V

IS

= HIGH, lEN = LOW

I

SIO o

S10'5
MSS

Input

LSS

SA

..

Fa

MSS

IS

S10'5 S10'5

1
Parity

j
SIOo SIOo ~ Input

LSS

o REGISTER
010 0
010,5
WRITE AND SHIFTE
FUNCTION MSS/ISI SA/LSsl MSS/IS SA/LSS

Fa

L

Hold

Z

j

L

Hold

Z

L

Log.0/2~

L

Log. 0/2-+0

Parity

L

Hold

j

H
H

F~

L

F-+O

..

L

Hold

Log.

0/2~

I

..
..

Input - 1 0 1 0 ' 5 1 0 0
00
Input 010,5

I

I

..

Z
Input - 1 0 1 0 , 5

J

00

..

Z

~

L

Hold

F6

,..!L

L

Log. 20-+0

01 00

1

07

F7

F7

L

Log. 20

~O

0100

I

07

1 Input_
Input-

I

07

I

H

j

j

H

Parity = F'5 'V' 1i4 ...... 'V' F3 'V' F2 'V' F, 'V' Fa 'V' S10'5
'V' = Exclusive OR

Hold
Log. 20

~O

0100

L

Hold

Z

L

Hold

Z

L = LOW
H = HIGH
Z = High Impedance

SA = Stand Alone
MSS = Most Significant Slice
IS = Intermediate Slice
LSS = Least Significant Slice

8-162

I

Z

..
Input-

..

..

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

Table 4c. ALU Destination Control for 10 or 11 or 13

MILITARY AND COMMERCIAL TEMPERATURE RANGES

= HIGH, lEN = LOW

SI015
18 17 16 15

ALU SHIFTER
FUNCTION

HEX

SA

Y15

MSS

IS

LSS

SA

MSS

Y14
IS

LSS

SA

MSS

Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word

L L L
L L L
L L H
L L H
L H L
L' H L
L H H
L H H
HL L
H L L
H L H
HL H
H H L
H H L
H H H
HH H

•

~ o~

L

Arlth.

F/2-+Y

0

H

Log.

F/2-+Y

1

L

Arlth.

F/2-+Y

2

H
L

Log.

F/2-+Y

3

~

F-+Y

4

F15

H

F-+Y

5

L

F-+Y

e

H
L
H

F-+Y

7

Arlth.

2F-+Y

8

Fe

F14

Log.

2F-+Y

9

F7

F15

L

Arlth.

2F-+Y

A

Fe

F14

H
L
H
L
H

Log.

2F-+Y

B

F7

F

F-+Y

C

F-+Y

0

jj 1

Sign Extend
F-+Y

E

F

Input

15

SIOO

~
~

~
F

15

~
F 15

~
~
~

SIOO

HEX

SA

MSS

F15

0

~

SI015 0

~ ~
F15

F15

0

~

~
~

~
~

~

~

F14

F14

0

I

or

F14

1 11 l

F14

I

F14

~
~
~

F14

I---

~
~
~

F15

-

~

.!L

F 15

0

IS

~

SI015

1 1 ~ ~ ~ 1 1 [1

F15

1r

0

~
~

~
~

Table 4c. ALU Destination Control for 10 or 11 or 13
ALUSHIFTER
FUNCTION

0

LSS

IS

Byte Word Byte Word

I

~

F15

SIOa SIOa SIOa SIOa

0

F15

F15

F15

0

F15

I I
-

F7

0

I--'-

~

F14

£r.
0

~

F14

F14

F14

SIOa SIOa SIOO SIOO F7

0

F14

0

F14

0

I

= HIGH, lEN = LOW (cont'd.)
LSS

SA

MSS

IS

LSS

SA

MSS

IS

LSS

Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word

8-163

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

Table 4c ALU Destination Control (cont'd) for 10 or 11 or 13

= HIGH , lEN = LOW

Va

Ie 17 18 15

ALU SHIFTER
FUNCTION

HEX

SA

Vo

VS-1

MSS

IS

LSS

SA

MSS

IS

SA

LSS

MSS

IS

LSS

Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word

L L L
L L L
L L H
L L H
L H L
L H L
L H H
L H H
HL L
HL L
HL H
HL H
H H L
H H L
H H H
H H H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

Arlth.
Log.
Arlth.
Log.

F/2-+Y
F/2-+Y
F/2-+Y

a SI015 F7
1
F7
2 SI015

F/2-+Y
F-+Y
F-+Y
F-+Y

3
4

5
a

F-+Y
Arlth. 2F-+Y
Log. 2F-+v
Arlth. 2F-+Y
Log. 2F-+Y
F-+Y
F-+Y
Sign Extend

7
8
9

A
B
0

E
F

F-+Y

i = 1 to 6 (for 05-1)
i = 9 to 14 (for 013-9)

F7

a

F7

a

SI015 F7 FI+l FI+l
F7
SI015

FI+1 a

a

F1

FI+1 FI+l 11+1 Fl

F1

J

F7

J J J

Fe

Fe

Fe

Fe

J

F6

F6

F5

F5

F5

F5

F5

F5 FI_l FI-l

...£2...

~

J J
F6

!!

F6
Fa
SIOo SIOo SIOO SIOo
a F6 a Fa

FI

J J J J J

FI

FI

FI

Fa

Fa

FI

FI-l

FI-l FI-1 FI_l SIOo SIOO

Fa

F6

FI

~

FI

!II I

FI

rh-

FI

Fa

Fa

IIII

FI
FI
SIOO SIOO SIOO SIOO
a FI
a
FI

L L L L

Arith. F/2-+Y

0

L L L H Log.
L L H L

F/2-+Y

Arith. F/2-+Y

L L

F-+Y

4

L H L H

F-+Y

5

L H

HL
H HH

F-+Y

6

L

F-+Y

7

Arith. 2F-+Y

8

H

Leg. 2F-+Y

9

HL
HH

Arith. 2F-+Y

A

L

L L

H
HL
HH
L

MSS

LSS

IS

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Fa

Fa

SI0 15

Fa

SI0 15

Fa

Fa

Fa

Parity

Parity

Parity

Parity

Parity

2

3

L L

SA

1

F/2-+Y

L L H H Log.

Fa

F1

Fa

Fa

SIOO

SIOo SIO OSIOO

..!.Q.

..!.Q. Fa Fa

Fa
Fa
SIOo SIOo SIOo SIOo
a Fa a Fa

SIO o
HEX

HL
HL
HL
HL
HH
HH
HH
HH

Fl

J J J

Fa

FI

SA = Stand Alone
MSS = Most Significant Slice
IS = Intermediate Slice
LSS = Least Significant Slice

ALU SHIFTER
FUNCTION

H

Fl

J J J

18 17 18 15

L

a

1
1
1
! ! 1 ! !!! j 1 ! j !!! 1 j j j
1 jj 1 jjjjj 1 jjj
F7

Fe

C

a

Log. 2F-+Y

B

F-+Y

C

F-+Y

D

Sign Extend

E

F-+Y

F

-Parity

•

Input

8-164

II

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

Table 4d. ALU Destination Control for 10 or 11 or 13

o REGISTER
I, 17 Ie 15

= HIGH, lEN = LOW

010 15

~ND

SHIFTER HEX
FUNCTION

MSS/IS

0 15

I
I Byte IWord
SA/LSS

I

Byte Word

..

L L L L Hold

0

Z

L L L H Hold

1

Z

L L H L Log. 0/2-+0

2

Input

L L H H Log. 0/2-+0

3

Input

L H L L Hold

4

Z

L H L H Log. 0/2-+0

5

Input

..

L H H L F-tO

6

Z

..

L H H H F-+O

7

H L L L Hold

8

H L L H Hold

9

H L H L Log. 20-+0

A

H L H H Log. 20-+0

B

H H L L Hold

C

H H L H Log. 20-+0

D

H H H L Hold

E

Z

H H H H Hold

F

Z

..

L L L L Hold

0

L L L H Hold

1

MSS/IS

Byte Word

Byte Word

Byte Word

..

Hold

010

15
r-

~

101015
Hold

-

r01015
r-

j
0100 1 0 15 1 0 7 1 0 15
0100 1 0 15 1 0 7 1 0 15

rf---

-

Z

0100 1 0 15 1 0 7 1 0 15

014

Hold

..
..

Hold

Byte Word

I

01+1

01+1

..

Hold

-0
- 9

MSS/IS

I Byte IWord

Byte Word

..

Hold

I---

2

L L H H Log. 0/2-+0

3

L H L L Hold

4

L H L H Log. 0/2-+0

5

Os 1010 15 1 Os

L H H L F-+O

6

F7

Os 1010151 Os

Hold

-

-

~

09

~

r---S-

~

~

~

r-

I---

Hold
;---

Hold

Hold

Hold
0
- 7

Hold

01-1

01-1

07

f---

~

I---

f---

Hold

Hold

r-

r---

01-1

01-1

-Hold

r-

~

Hold

-

-Hold7
-Hold

07

r---

r-

Hold

Hold

Hold

r-

r--Hold

Hold

r-

rHold

Hold

r-

01-1

I---

~

Hold

r---

f---

0

I

SA/LSS

MSS/IS

I Byte IWord

Byte Word

..

Hold

Os 101015 1 Os

Hold

0

- 9
~

- 09
-

Hold

0

I

010 0

0

SA/LSS

MSS/IS

I Byte IWord
.

Hold

I

Byte Word

0 1+1

..

01+1
Hold
01+1
FI

L H H H F-+O

7

F7

FI

H L L L Hold

8

Hold

Hold

H L L H Hold

9

Hold

Hold

..
..
..
..
..
..
..
..

..

H L H L Log. 20-+0

A

06

01-1

H L H H Log. 20-+0

B

06

01-1

H H L L Hold

C

Hold

Hold

H H L H Log. 20-+0

D

06

01-1

..

H H H L Hold

E

Hold

Hold

H H H H Hold

F

Hold

Hold

..
..

..
..

01

.. 010 151

00

01

.. 01 0 151

00

Hold
0 1
Fo
Fo
Hold
Hold
010 0
010 0
Hold
010 0
Hold
Hold

..

Z

.. 010 15 1 0 0

..

Z

..
..

j

..
..
..
..

..
..
..

Input
Input
Z

Input
Z
Z

Z = High Impedance
SA = Stand Alone
MSS = Most Significant Slice
IS = Intermediate Slice
LSS = Least Significant Slice

Parity = F 15 'V' F14 ...... 'V' F3 'V' F2 'V' F1 'V' Fo 'V' SI0 15
'V' = Exclusive OR
i = 1 to 6 (for 0 6 - 1)
i = 9 to 14 (for 0 14-9 )

8-165

I

SA/LSS

I Byte IWord
..
..

Z
Z

L L H L Log. 0/2-+0

-

~

Hold

r---

0 6- 1
SA/LSS

Hold

Byte Word

= HIGH, lEN = LOW (cont'd.)

07
MSS/IS

SA/LSS

Byte Word

~

r-

0
- 14

Hold

MSS/IS

0 1+1

01-1

Hold

r0
r 14Hold
r-

r---

r-

0 14

~

~

..

~

0 1+1
r
-

r--L
Hold

Hold

Hold

;---

r-

~
~

Hold
-

Word

..

Hold

-

Hold

Byte

~

Hold

01015

~
~

SA/LSS

Hold

010 5
- 1

;---

r-

Table 4d. ALU Destination Control for 10 or 11 or 13

o REGISTER
I, 17 Ie 15 ~ND SHIFTER HEX
FUNCTION

SA/LSS

..
..
..

0,

0 14-9

MSS/IS

..
.

..
.

..

..
..
..
..

..

..

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Table 5. Special Functions (7)
HEX
18 17 16 15

0

14

HEX
13 1211 10

L

0

1

L

0

1

H

0

2

L

0

3

L

0

SPECIAL
FUNCTION
Unsigned Multiply
BCD-to-Binary
Conversion
Multiprecision
BCD-to-Binary

ALU
FUNCTION

ALU SHIFTER
FUNCTION

F=S+C n if Z=L
F=R+S+C n if Z=H

o REGISTER

SI015
SIOO

& SHIFTER 01015 0100 WRITE

MSS

OTHER
SLICES

Log F/2-tY
(1)

Z

Input

Fo

Log 0/2-t0 Input

00

L

(4)

Log F/2-tY

Input

Input

Fo

Log 0/2-t0 Input

00

L

(4)

Log F/2-tY

Input

Input

Fo

00

L

Log F/2-tY
(2)

Z

Input

Fo

00

L

F-tY

Input

Input

Parity

Hold

Z

Z

L

Two's Complement F=S+C n if Z=L
Multiply
F=R+S+C n ifZ=H
Decrement by
F=S-2+Cn
One or Two

FUNCTION

Hold

Z

Log 0/2-t0 Input

4

L

0

Increment by
One or Two

F=S+ 1 +Cn

F-tY

Input

Input

Parity

Hold

Z

Z

L

4

H

0

Byte Swap + C n

F=(LB. UB)+C n

F-tY

Input

Input

Parity

Hold

Z

Z

L

Sign/Magnitude
Two's Complement
Two's Complement
Multiply. last Cycle

F=S+C n if Z= L
F/2 -tV
(3)
F='S"+C n ifZ=H
Log F/2-tY
F=S+C n if Z= L
F=S-R-1 +C n if Z=H
(2)

Input

Input

Parity

Hold

Z

Z

L

00

L

Z

L

5

L

0

6

L

0

7

L

0

BCD Divide by Two

8

L

0

Single Length
Normalize

9

L

0

9

H

0

Binary-to-BCD
Conversion
Multiprecision
Binary-to-BCD

Z

Input

Fo

F-tY

Input

Input

Parity

Hold

F-tY

F15

F 15

Z

Log 20-tO

0 15 Input

L

(5)

Log 2F-tY

F15

F 15

Input

Log 20-t0

0 15 Input

L

(5)

Log 2F-tY

F15

F15

Input

Hold

Log 2F-tY

R15 V
F15

F15

Input

Log 20-tO

(4)

F=S+C n

Double Length
Normalize and
First Divide Op

F=S+C n

F=R+S+CnBCD (6)

A

L

0

B

L

0

BCD Add

Log 0/2-t0 Input

F-tY

0

0

Z

Hold

Log 2F-tY

R15
VF

F 15

Input

Log 20-tO

C

L

0

Two's Complement F=S+R+C n if Z=L
Divide
F=S-R-1 +C n if Z=H

0

L

0

BCD Subtract

F = R-S-1 + Cn BCD (6)

F-tY

0

0

Z

Hold

E

L

0

Two's Complement
F=S+R+C n if Z=L
Divide Correction
F=S-R-1 +C n if Z=H
and Remainder

F-tY

F15

F 15

Z

Log 20-tO

F

L

0

BCD Subtract

F = R-S-1 + CnBCD (6)

F-tY

0

0

Z

Hold

Z

Z

Input

L

0 15 Input

L

Z

Z

BCD Nibble propagate:
BCD Slice propage:

9.

BCD Nibble generate:
BCD Slice generate:

L = LOW
H = HIGH
Z = High Impedance

l5fJ1 = W41+0 + P41+3) (P41 + 0 + ~1+2l (P41+0 + <341 + 1 + P.t1+2)

Z

P = PN 3 PN 2 PN 1 PN o
041+3(041+0 + <341 + 1 + P41 + 2) (<341 + 0 + <341 + 1) (1541 + 1 + ~1+2l (~1+3 + P.;1+1 • P41+2 • ~I+ol
G = GN3 V GN 2 PN3 V GN 1 PN 2 PN 3 V GN 0 PN 1 PN 2 PN 3

GN 1 =

LB = Lower Byte
UB = Upper Byte

'V' = Exclusive OR
Parity = SI015 'V' F15 'V' F14 'V' F13 'V' . . . . .. 'V' Fo

8-166

Z

0 15 Input

NOTES:
1. At the most significant slice only. the C n+ 16 signal is internally gated to the Youtput.
2. At the most significant slice only. F15 'V' OVR is internally gated to the Y output.
3. At the most significant slice only, S15 'V' F15 is generated the Y output.
4. On each nibble, F = S if magnitude of S is less than 8, and F = S minus three if magnitude of S is 8 or greater.
5. On each nibble, F = S if magnitude of S is less than 5, and F = S plus three if magnitude of Sis 5 or greater. Addition is modulo 16.
6. Additions and Subtractions are BCD adds and subtracts. Results are undefined if R or S are not in Villid BCD format.
7. The Q register cannot be used explicitly as an operand for any Special Functions. It is defined implicitly within the functions.

8.

Z

0 15 Input

Z

L
L
L

L

L

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Table Ga. IDT49C403 Status Outputs (Word Mode)
GI
PI
(1=0 to 15) (1=0 to 15)

P/OVR

GIN

HEX
18 17 16 15

HEX
14 13 12 11

10

X

0

H

0

1

0

0

0

X

1

X

Ri A Si

RiVSi

GVPC n

C n+15 "il' C n+16

X

2

X

Ri A Si

RiVSI

GVPC n

Cn+ 15 "il' C n+ 16

X

3

X

RiASi

RiVSi

GVPC n

X

4

X

0

Si

GVPC n

X

5

X

0

Si

GVPC n

X

6

X

0

Ri

X

7

X

0

X

8

H

0

C n+1S

Z(OEY = L)
OTHER
SLICES

MSS

ISS

LSS

SA

F15

G

1 (y)

1(Y)

1(Y)

1 (Y)

P

F15

G

1(Y)

1(Y)

1(Y)

1(Y)

p

F15

G

1(Y)

1(Y)

1(Y)

1(Y)

C n+15 "il' C n+16

P

F15

G

f(Y)

1(Y)

1(Y)

1(y)

C n+ 15 "il' C n+16

p

F15

G

1M

1 (y)

1M

1(Y)

C n+15 "il' C n+16

P

F15

G

1M

fM

f(Y)

f(Y)

GVPC n

C n+ 15 "il' C n+ 16

P

F15

G

1M

1(Y)

1M

1(Y)

Ri

GVPC n

C n+15 "il' C n+16

j5

F15

G

fM

f (Y)

f(Y)

f(Y)

1

0

0

0

F15

G

1M

1(Y)

1M

1(Y)

MSSISA

OTHER
SLICES MSSISA

X

9

X

Ri A Si

1

0

0

0

F15

G

fM

f (Y)

f(Y)

1(y)

X

A

X

Ri A Si

RiVSi

0

0

0

F15

G

1M

1(Y)

1M

1(Y)

X

B

X

Ri A Si

RiVSi

0

0

0

F15

G

1(Y)

f(Y)

1 (y)

1(Y)

X

C

X

Ri A Si

1

0

0

0

F15

G

1M

1(Y)

1(Y)

1(Y)

X

D

X

Ri A Si

1

0

0

0

F15

G

1(Y)

1(Y)

1 (y)

1(Y)

X

E

X

RiASi

1

0

0

0

F15

G

1(y)

1 (Y)

1 (Y)

1(Y)

X

F

X

Ri A Si

1

0

0

0

F15

G

1(Y)

1 (Y)

1(Y)

1(Y)

o i1Z=L
0

0

L

RiASi
i1Z=H

Sii1Z=L
RiVSi
i1Z=H

GVPC n

C n+15 "il' C n+16

j5

F15

G

Input

Input

00

00

1

0

L

0

Si

GV PCn

C n+ 15 "il' C n+ 16

P

F15

G

1(Y)

1(Y)

1M

1(Y)

1

8

L

0

Si

0

0

0

F15

G

1(Y)

1(Y)

1(Y)

1(Y)

o i1Z=L

Si i1Z=L
RiVSi
ifZ=H

GVPC n

C n+15 "il' C n+16

j5

F15

G

Input

Input

00

00

0

L

Ri A Si
i1Z=H

3

0

L

(6)

(7)

GVPC n

Cn+ 15 "il' C n+ 16

p

F15

G

1(Y)

1(Y)

1(Y)

1(Y)

4

0

L

(1)

(2)

GV PCn

C n+15 "il' C n+16

P

F15

G

f(Y)

1(Y)

f(Y)

1(Y)

4

8

L

(1)

(2)

GVPC n

C n+15 "il' C n+16

p

1(Y)

1M

1(Y)

GV PCn

C n+ 15 "il' Cn+ 16

2

F15

G

1M

P

Fi5 i1Z =L
F15"il'S15
ifZ=H

G

5,5

P

F15

G

Input

5

0

L

0

§.i i1 Z=L
Si i1Z=H

6

0

L

Oi1Z=L
RiA Si
ifZ=H

Sii1Z=L
RiVSi
i1Z=H

GVPC n

C n+15 "il' C n+16

7

0

L

0

Si

GVPC n

Cn+15 "il' C n+16

j5

F15

G

1M

1(Y)

f(Y)

f(Y)

8

0

L

0

Si

(4)

O 2 "il' 0 1

0,5

G

1(0)

1(0)

f(0)

1(0)

9

0

L

0

Si

GVPC n

Cn+15 "il' C n+16

P
p

F15

G

f(0)

f(0)

f(0)

1(0)

9

8

L

0

Si

0

0

0

F15

G

f(O)

1(0)

f (a)

f (a)

A

0

L

0

Si

(3)

F2 "il' Fl

j5

F15

G

(5)

(5)

(5)

(5)

B

0

L

Ri A Si

RiVSi

GV PCn

(8)

(8)

F15

(9)

f(Y)

1 (Y)

1(Y)

f(Y)

C

0

L

RiASi
ifZ=L
RiA Si
ifZ=H

RiVSi
ifZ=L
RiVSi
ifZ=H

GVPC n

Cn+ 15 "il' Cn+ 16

P

F15

G

D

0

L

RiASi

RiVSi

GVPC n

C n+15 "il' C n+16

(8)

F15

(9)

RiVSi
i1Z=L
RiVSi
ifZ=H

GVPC n

Cn+15 "il' Cn+16

P

F15

G

RiVSi

GV PCn

Cn+15 "il' C n+16

(8)

F15

(9)

E

0

L

RiASi
i1Z=L
AI A Si
ifZ=H

F

0

L

AI

A Si

Input Input

S15

Input

00

00

Sign
Sign
Compare
Compare
Input Input
FF
FF
Output
Output
f(Y)

f(Y)

fM

1 (y)

Sign
Sign
Compare
Compare
Input Input
FF
FF
Output
Output
f(Y)

1(Y)

f(Y)

fM

Continued next page

8-167

IDT49C403/A 16-81T CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES:
1. 11 lSS is lOW. Go = So and G 1.2, 3" ..• 15 = 0.11 lSS is HIGH. Go, 1,2,3" ..• 15 = 0
2. 11 lSS is lOW. Po = 1 and Pl, 2, 3, ...• 15 = Sl, 2, 3, ...•15. 11 lSS is HIGH. PI = SI
3. At the most significant slice. C n+ 16 = 015 'V' 014. At other slices C n+ 16 = G V PCn
4. Atthemostsignificantslice.Cn+16 = F15'V' F14, At other slices Cn+16 = GVPC n
5. Z = 0 00 102 0 3 ... 015FO Fl F2 F; ... F 15
6. 11 lSS is lOW. Go = 0 and G 1, 2, 3,. ..• 15 = S1, 2, 3,. ..• 15. 11 lSS is HIGH. Go, 1, 2, 3,' . ·.15
7. 11lSSislOW.Po = SoandP1,2, 3, .. ·.15= 1. 11 lSS is HIGH. PO,1,2,3..... 15 = 1
8. BCD Nibble propagate: J5fJ 1 = (F541 + 0 + ]541+3) (F541 + 0 + G41+~ (]541+0 + <341 + 1 + ~1+2)
BCD Slice propage:
P = PN3 PN2 PN 1 PNo

9.

<341+3(<341+0 + <341 + 1 + ~1+2) (<341 + 0 + <341 + 1) (1541 + 1
G = GN3 V GN 2 PN 3 V GN 1 PN 2 PN 3 V GN o PN 1 PN 2 PN 3

00 1 =

BCD Nibble generate:
BCD Slice generate:

V = OR
II = AND
'V' = Exclusive-OR
P = P15P14 ...... P3P2P1PO
G = G 15 V G 14P15 V G 13P14 1l5 V G12P13 P14 P,5
= So, 1,2,3,' ..• 15
V G ll P12 P13 P14 1l5 V ...... VG 1P2 P3 P4 ",P15

+ ~I+~

(~1+3

+ P.;1+1 .1541 + 2

• ~I+o)

1 M = Yo Y1 '12'13 ...... '(,5
1 (0) = 0 00 10 20 3 ...... 0 15
l = lOW = 0
H = HIGH = 1

Table 6b. IDT49C403 Status Outputs (Byte Mode)
HEX
HEX
18 17 18 15 14 13 12 11

GIN

P/OVR

I

01
(1=0 to 7)

PI
(1=0 to 7)

C n +7

0

H

0

1

0

X

1

X

Ri II Si

RiVSi

X

2

X

Ri II Si

RiVSI

X

3

X

Ri II Si

X

4

X

X

5

X

OTHER
SLICES MSS/SA

Z (OEY = l)
OTHER
SLICES

MS

ISS

LSS

SA

0

0

F7

G

1 (Y)

1 (Y)

1(Y)

1 (Y)

GV PCn

Cn+7 'V' Cn+8

P

F7

G

1(Y)

1M

1 (Y)

1M

GVPC n

C n+ 7 'V' Cn+8

P

F7

G

f(Y)

1 (Y)

1 (Y)

1M

RiVSi

GVPC n

Cn+7 'V' Cn+8

P

F7

G

1M

1M

1M

1M

0

Si

GVPC n

Cn+7 'V' Cn+8

P

F7

G

1(Y)

1M

1M

1M

X

0

Si

GV PCn

C n+7 'V' Cn+8

P

F7

G

1(Y)

1 (Y)

1 (Y)

1M

6

X

0

Ri

GV PCn

Cn+7 'V' C n+8

P

F7

G

1M

1 (Y)

1 (Y)

1M

X

7

X

0

Ri

GV PCn

Cn+7 'V' Cn+8

P

F7

G

1(y)

1 (Y)

f(Y)

1M

X

8

H

0

1

0

0

0

F

G

1M

1M

1 (y)

1M

X

9

X

Ri II Si

1

0

0

0

F

G

1(y)

1(Y)

1M

1M

X

A

X

Ri II Si

RiVSi

0

0

0

F

G

1(Y)

1M

1M

1M
1M

X

MSS/SA

X

B

X

Ri II Si

RiVSi

0

0

0

F

G

1(Y)

1M

1M

X

C

X

Ri II Si

1

0

0

0

F

G

1(Y)

1(Y)

1M

1 (y)

X

D

X

Ri II Si

1

0

0

0

F

G

1(Y)

1M

1 (y)

1M

X

E

X

Ri II Si

1

0

0

0

F

G

1(Y)

1 (y)

f(Y)

1 (y)

X

F

X

RiASi

1

0

0

0

F

G

1M

1 (Y)

f(Y)

f(Y)

NOTES:
f M = Yo '11'12'13 ...... Y7
f(0) = 0 00 10 20 3 , ..... 0 7
l = lOW = 0
H = HIGH = 1

V = OR
II = AND
'V' = Exclusive OR
P = P7 P6· ..... P3 P2 P1 Po
G = G 7 V G6P7 V G5 P6 P7 V G4 P5 P6 P7
V G3P4 P5 P6 P7 V ...... V G 1P2 P3 P4 ... P7

8-168

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TslAs

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

-0.5 to +7.0

-0.5 to +7.0

SYMBOL

V

PT

Power Dissipation

1.5

1.5

W

lOUT

DC Output Current

50

50

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

C IN

Input Capacitance

C OUT

Output Capacitance

CONDITIONS

TYP.

UNIT

VIN = OV

10

pF

VOUT = OV

15

pF

NOTE:
1. This parameter is sampled and not 100% tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
TA = O°C to + 70°C
TA = -55°C to + 125°C
VLC = 0.2V
VHC = Vce - 0.2V
SYMBOL

Vee = 5.0V ± 5% (Commercial)
Vee = 5.0V ± 10% (Military)

TEST CONDITIONS (1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

-

V

O.S

V

\lH

Input HIGH Level

2.0

VIL

Input LOW Level

-

-

IIH

Input HIGH Current

Vee = Max., \IN = Vec

-

0.1

5

~A

IlL

Input LOW Current

Vee = Max., \IN = OV

~A

-

-0.1

-5

VHC

Vee

-

10H = -6mA MIL.

2.4

4.3

-

10H = -SmA COM'L.

2.4

4.3

-

10L = 300~A

-

GND

10L = 12mA MIL.

-

0.3

VLe
0.5

10L = 16mA COM'L.

-

0.3

0.5

Vo = OV

-

-

-10

Vo = Vee (max.)

-

-

10

-15

-

-

10H =
VOH

VOL

loz
los

Output HIGH Voltage

Output LOW Voltage

Vee = Min.
VIN = \lH or \lL

Vee = Min.
\IN = \lH or \lL

Off State (High Impedance)
Output Current

Vce = Max.

Output Short Circuit Current

Vee = Min., VOUT = OV

(3)

-300~A

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a nOise-free environment.

8-169

V

V

~A

mA

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403/A 16·BIT CMOS MICROPROCESSOR SLICE

DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = O°C to + 70°C
Vcc = 5.0V ± 5% (Commercial)
TA = -55°C to + 125°C
Vcc = 5.0V ± 10% (Military)
VlC = 0.2V
VHC = Vcc - 0.2V
TEST CONDITIONS

SYMBOL

PARAMETER

ICCQH

Quiescent Power Supply Current
CP = H (CMOS Inputs)

Vcc = Max.
VHC :5 \'IN ' \'IN :5 VlC
fcp = 0, CP = H

Iccol

Quiescent Power Supply Current
CP = L (CMOS Inputs)

Vcc = Max.
VHC :5 \'IN , \'IN :5 VlC
fcp = 0, CP = L

Iccr

Quiescent Input Power Supply
Current (per Input @ TIL High)

Vcc

ICCD

Dynamic Power Supply Current

Vcc = Max.
VHC :5 \'IN ' \'IN :5 VlC
Outputs Open, DE = L

Total Power Supply Current

MAX.

-

150

250

mA

-

50

100

mA

-

0.3

0.5

MIL.

-

3.6

7.7

COM'L.

-

3.6

5.2

MIL.

-

136

252

COM'L.

-

136

227

MIL.

-

150

275

COM'L.

-

150

250

= Max. \'IN = 3.4V, fcp = 0

Vcc = Max., fop = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VHC :5 \'IN , \'IN :5 VlC
Icc

TYP.(2)

MIN.

(1)

UNIT

mNinput

mA/MHz

mA

(6)

Vcc = Max., fop = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
\'IH = 3.4V, \'Il = O.4V

NOTES:
5. Iccr Is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out I CCOH ' then dividing by the total number of inputs.
6. Total Supply Current isthe sum of the Quiescent current and the Dynamic current (at either CMOS or TIL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH (CDH)

+

Iccol (1 - CDH)

+

Iccr(Nr x D H)

+

ICCD (fcp)

CDH = Clock duty cycle high period.
DH = Data duty cycle TIL high period (\'IN = 3.4V).
Nr = Number of dynamic inputs driven at TIL levels.
fcp = Clock input frequency.

8-170

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARV AND COMMERCIAL TEMPERATURE RANGES

IDT49C403A GUARANTEED COMMERCIAL AND
MILITARY RANGE PERFORMANCE

Table 8. Enable/Disable Times All Functions
FROM

The tables below specify the guaranteed performance of the
IDT49C403A over the commercial operating range of 0 to + 70°C
with Vee from 4.75 to 5.25V, and over the military operating range
of -55 to + 125°C with Vce from 4.5 to 5.5V. All data are in
nanoseconds, with input switching between 0 and 3V at 1V/ns and
measurements made at 1.5V. All outputs have maximum DC load.

Table 7. Clock and Write Pulse Characteristics All Functions
COM'L. MIL
Minimum Clock Low Time

..

10

,

1\

UNIT

Minimum Clock High Time

10

< it

ns

10

\

11

ns

Table

DISABLE
COM'L MIL

UNIT

DEy

V

12

j3

10

if

ns

DEB

DB

14

he:

12

ns

ns

EA

DA

15

16

13

j:
j,

la

SID

23

25

12

13

la

010

16

ii

21

22

ns

la, 7, 6, 5

010

17

18

19

26

ns

ns

26

····22·······
010
21
19
14,3,2,1,0
ns
NOTE:
C L = 5,OpF for output disable tests. Measurement is made to a 0,5V change
on the output.

ns

Minimum Time CP and WE both Low to Write

ENABLE
COM'L
MIL

TO

9. Set-up and Hold Times All Functions
tpWL
I

I

FROM

WITH RESPECT TO

HOLD
SET-U P
SET-UP
HOLD
COM'L M IL. COM'L M IL. COM'L MIL. COM'L MIL.

V

CP

-

WE HIGH

CP

7

WE LOW

CP

-

A. B Source

CP

11

B Destination (3)

CP

6

B Destination (3)

lEN

6

B Destination (3)

WE

6

CP

la, 7, 6, 5

CP

-

lEN HIGH (3)

CP

7

lEN LOW

CP
CP

-

CP

-

CP

-

010 0,15

(3)

14,3,2,1,0
0 0 .01

Cn

i

-

.u

2

)

...•

8

2)

-

~)

2
....

UNIT

COMMENTS

ns

Store V in RAM/O
Prevent Writing
Write into RAM

(1)

2

ns

10

0

ns

-

-

ns

Latch Data from RAM Out

(3)

(3)

2

ns

Write Data into B Address

(3)

(3)

2

ns

Write Data into B Address

(3)

~

2

ns

Write Data into B Address

-

5

-

23

:;

c

(3)

10

IHii
.
....

7

-

-

8
28

i'

.7

8

2

••••

0

/

Shift

ns

Write into

ns

Prevent Writing into

ns

Write into

0

and RAM (2)
0

and RAM

0

and RAM
and RAM (2)

>

ns

Write into

0

.~

2

2

ns

Write into

0

~9

0

0

ns

ALU Carry In to RAM

16

H

a

ns

(2)

NOTES:
1. The internal V-bus to RAM set-up condition will be met 5ns after valid V output (OEy= 0)
2. The set-up time with respect to CP falling edge is to prevent writing, The set-up time with respect to CP rising edge is to enable writing,
3. The writing of data is controlled by CPo IEN. and WE; all must be LOW in order to write, The set-up time of B destination address is with respectto the last of
these three inputs to go LOW. and the hold time is with respect to the first to go HIGH.
4. A· _. implies this path does not exist.

8-171

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403A GUARANTEED COMMERCIAL AND MILITARY RANGE PERFORMANCE
STANDARD AND INCREMENT/DECREMENT BY ONE OR TWO INSTRUCTIONS (SF3, SF4)
TO
FROM

SLICE

Y
Com'l. Mil. Com'l. Mil.

41

MSS
IS
LSS
SA

34

MSS
IS
LSS
SA

27

MSS
IS
LSS
SA

38

MSS
IS
lSS
SA

43

MSS

Any

21

S100-15

Any

"

FROM

SLICE

DA, DB

18-0

CP

DA,DB

OVR

N

WRITE

010 0,15

SIOo

SI015::::'::: ::.:.:. SIOO
. PARITY

47

50

47

50

34

36

34

36

,I" ~

26

i

47

50

28

15

23
23

34
34

39

42
42

~q

26

i :28

26

28

23

25

36

38

42

45

36

38

42

45

I»

51

55

54

58

I»

51

55

54

58

2325:

21

24

20:<

38

~~.::

••• ::

37

41

ns

37

41

ns

ns

16

19

C n +16
Mil.

G,
Com'l.

ns

20

II

Com'l.

..

ns

:::

.. :::::

39

1/

Mil.

38

48

'"
44

Y

36

22

32

Com'l.

ns

46

~'

UNIT

Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil.' C(;iil'l. Mil.

.:::

MSS
IS
LSS
SA

A, BAddr

Z

G,P

p<:>

Z:I:N<>

Mil:Com'l.

Mil.

rc~iri'l> ~II.

DA,DB

OVR

Com'l.

Mil.

Com'l.

Mil.

WRITE
Com'l.

Mil.

01 °0,15
Com'l.

Mil.

SIOo
Com'l.

UNIT

Mil.

MSS
A, BAddr

~S

ns

SA

DA, DB

MSS
IS
LSS
SA
MSS
IS
LSS
SA
IS
MSS
lSS

18- 0

SA

-

i

-

.:-:::.

ns

::.:...,
::::::::::

::::::.::::.

-

-i
-::.:

.::: ...

':::

jIll,

-

::.:

-

-

--

MSS
CP::/

-

-

-

~~ ..:

:.... "'-:.:

-

ns

-,:::

-

-

:SA .:

::::::

n:

-

<-

/>~~-~~~.:~-~--+~

S100-15

Unsigned Multiply
SFO: F=S+CnlfZ=l
F=S+R+CnlfZ=H
Y15=Cn+16 (MSS)
Z=QO(lSS)
Y=Log F/2
O=Log 0/2

Two's Complement Multiply
SF 2: F=S+Cn If Z=l
F=S+R+Cn If Z=H
Y15=F15 VOVR (MSS)
Z=OO(lSS)
Y=Log F/2
0=Log0/2

Two's Complement Multiply Last Cycle
SF2: F= S+CnI1Z=L
F=S-R-1+Cn If Z=H
Y15=OVRV F15 (MSS)
Z=QO(lSS)
Y=log F/2
O=Log 0/2

8-172

A '-' Implies that particular data path
Is not valid.

IDT49C403/A 16·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403A GUARANTEED COMMERCIAL AND MILITARY RANGE PERFORMANCE
BCD INSTRUCTIONS (SF1, SF?, SF9, SFB, SFD, SFF)
TO
FROM

SLICE

Y

Cn +16

Com'l. Mil. Com'l. Mil.

A. BAddr

DA. DB

18-0

MSS
IS
LSS
SA

CP

MSS
IS
LSS
SA

Z
(DEy =
low)

MSS
IS
LSS
SA

S100-15

Any

OVR

DA,DB

WRITE

010 0,15

SIOo

Mlj~

:::

:::::

I Iii

.:::::

MSS
IS
LSS
SA
MSS
IS
LSS
SA

N

Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l.

MSS
IS
LSS
SA

Cn

z

G,P

I: ••:.·••••••••••••••••

SIOo
PARITY
Com'l. Mil.

IIi

ns

\)

:::::

UNIT

. ns

::::::
::::::

::::::...

:::::::::::
:::::::::::

I

::::::::
::::::::
.::::::::
::::::::

..•..••••.•••••••••:..

ns

:::::::::

::;::::::::
:::::::::

ns

ns

.. :::::

I

ns

NOTE:
1.
Binary to BCD and multlpreclslon Binary to BCD Instructions only
BCD to Binary conversion (SF 1)
BCD divide by two (SF 7)

Binary to BCD conversion (SF 9)
BCD add (SF B)

SIGN MAGNITUDE TO TWO'S
FROM

COMPLE~~~+ho~VER~ldN (SFS)
c ..c

...

- ...- ....

c.c

DA, DB

SLICE

Com'l.

Mil.

WRITE
Com'l.

Mil.

010 0,15
Com'l.

Mil.

SIOo
Com'l.

UNIT

Mil.

A. BAddr

MSS
IS
LSS
SA

ns

DA. DB

MSS
IS
LSS
SA

ns

;1

ns

I

I»>

i

ns

ns

ns

S100-15

ns

Any
I

SF5: F=S+CnlfZ=L
F=S+Cn IfZ=H
Y15=S15 'V' F15 (MSS)
Z=SI5 (MSS)

Y=F
0=0
N=FI5; Z=L
N=FI5 'V'SI5; Z=H

8-173

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403A GUARANTEED COMMERCIAL AND MILITARY RANGE PERFORMANCE
DIVIDE INSTRUCTIONS
SFC
AND SINGLE LENGTH NORMALIZATION (SFB)
FROM

SLICE

Y

OVR
Mil.

A. BAddr

Com'l.

SIOo

DA,DB

UNIT

Mil.

MSS
IS
LSS

SA

DA,DB

MSS
IS
LSS

SA

Cn

MSS
IS
LSS

ns

SA

18- 0

ns

CP

ns

(OEya
low)

MSS
IS
LSS
SA

S100-15

Any

Z

NOTES:

Double Length Normalize and First DIvide Op
SFA: F=S+Cn
N=FI5(MSS)
S1015=F15 "V'R15 (MSS)
Cn+ 16=F15 "V'F14 (MSS)
OVIi=.'=Z.~llMSSL
Z=OO 010203 .•• 015 FO FI F2 F3 .•. FI5
Y=Log 2F
Q=Log20

Two's Complement Divide Correction and Remainder
SF2: S=CnlfZ=L

~:.tl15+~nRI:I~~s) from previous cycle
Y=F
0= Log 20

8-174

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403 GUARANTEED COMMERCIAL AND
MILITARY RANGE PERFORMANCE

Table 11. Enable/Disable Times All Functions
FROM

The tables below specify the guaranteed performance of the
IDT49C403 over the commercial operating range of 0 to 70°C with
\(;c from 4.75 to 5.25V, and over the mil itary operating range of -55
to + 125°C with Vccfrom 4.5 to 5.5V. All data are in nanoseconds,
with input switching between 0 and 3V at 1V/ns and measurements
made at 1.5V. All outputs have maximum DC load.
Table 10 Clock and Write Pulse Characteristics All Functions
COM'L.

MIL.

UNIT

Minimum Clock Low Time

12

ns

Minimum Clock High Time

12

ns

Minimum Time CP and WE both Low to Write

12

ns

ENABLE
COM'L
MIL

DISABLE
COM'L MIL

UNIT

OEy

V

15

12

I;

ns

OE B

DB

17

15

ff

ns

EA

DA

18

16

18

SIO

28

15

ns

18

010

20

2

25

ns

18,7,6,5

010

21

2:

22

ns

:~

ns

27)

..

Table 12.

TO

010
25
22
ns
14,3,2,1,0
NOTE:
C L = 5.0pF for output disable tests. Measurement is made to a 0.5V change
on the output.

and Hold Times All Functions

NOTES:
1. The intemal V-bus to RAM set-up condition will be met 5ns after valid V output (OEy= 0)
2. The set-up time with respect to CP falling edge is to prevent writing. The set-up time with respect to CP rising edge is to enable writing.
3. The writing of data is controlled by CP, lEN, and WE; all must be (OW in order to write. The set-up time of B destination address is with respectto the last of
these three inputs to go LOW, and the hold time is with respecfto the first to go HIGH.
4. A· - ' implies this path does not exist.

8-175

IDT49C403/A 16·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403A GUARANTEED COMMERCIAL AND MILITARY RANGE PERFORMANCE
STANDARD AND INCREMENT/DECREMENT BY ONE OR TWO INSTRUCTIONS (SF3, SF4)
T O , <
FROM

SLICE

Y

C n +18

Com'l. Mil. Com'l. Mil.

A, BAddr

DA, DB

MSS
IS
LSS
SA
MSS
IS
LSS
SA

53

49

40

34

G, P

18-0

CP

SIOo 15

33

MSS
IS
LSS
SA

48

MSS
IS
LSS
SA

51

Any

28

Any

25

N

OVR

DA, DB

Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l.

53

57

50

32

5357

~: l~:
.

MSS
IS
LSS
SA

Z

56

60,

43

4if

43

46""

32

'34'

32

34....

43

'46'

43

.,46

35

":':-""

56

60

WRITE

0100,15

SIOO

SI015/',:", SIOO

'

lUI

I,:
2:.

1.li'!

I::::

MSS
IS
LSS
SA

S100-15

Any

.:..

II!I

.«« ..

<\i
I·:::..

Ic:

1.
Binary 10 BCD and multi precision Binary to BCD Instructions only
NOTE:
BCD to Binary conversion (SF1)
Binary to BCD conversion
BCD divide by two (SF7)
BCD add (SFB)

1<>·

ns

ns

...

.'......•.•.••:

Yi

«

MSS
IS
LSS
SA

~••• :.

ns

UF"":··
ns

r:}}}r":::::·
.:

1:::-·

I:}·:·:• :·:

IIII

ns

<

illll:

UNIT

ns

liiillill !ii Iii iilUi

:,:,::

:,:,:

SIOO
PARITY
I'Com'l. Mil.

111.11111111\

:i
>:,
.2

MSS
IS
LSS
SA

SI01j~]

SIOO

IIIIIIJ

MSS
IS
LSS
SA

Z
(OEy=
low)

010 0,1 5

Com'l. Mil. Com'l. MII. Com'l. MII. Com·l. MII. Com'l. MII. Com'l. Mil. Com'l. MII. Com'l. MII. Com'l•.::'

ns

~~~~~~j~:,':. :.t .• .'.>
.«)}

(S~9)~IIS

SIGN MAGNITUDE TO TWO'S COMPLI

,~N ~E§l

Tt

OVR
Com'l.

DA, DB
MO.

Com'l.

Mil.

I

WRITE
Com'l.

Mil.

010 0,15
Com'l.

Mil.

SIOo
Com'l.

UNIT

Mil.

MSS
A, BAddr

::'ss
SA

DA. DB

MSS
IS
LSS
SA

ns

.<•••••••••••:.

ns

ns

ns

SF5: F=S+CnIIZ=L
F=S+Cn II Z=H
Y15=S15 'V' F15 (MSS)
Z=SI5 (MSS)

Y=F

Q=Q
N=FI5; Z=L
N=FI5 'V'SI5; Z=H

8-177

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

IDT49C403 GUARANTEED COMMERCIAL AND MILITARY RANGE PERFORMANCE
DIVIDE INSTRUCTIONS
SFC SF AND SINGLE LENGTH NORMALIZATION

Com'l,

A, BAddr

MSS
IS
LSS
SA

DA, DB

MSS
IS
lSS
SA

Cn

MSS
IS
lSS
SA

18-0

MSS
IS
LSS
SA

CP

MSS
IS
LSS
SA

low)

MSS
IS
lSS
SA

S100-15

Any

Z

(OEy=

OVR

Y

FROM

81 00

UNIT

Mil,

NOTES:

Double length Normalize and First Divide Op

Two's Complement Divide Correction and Remainder
SF2: S=CnlfZ=l

SFA: F=S+Cn

~-:.'1;"l\+~n~igiM~s) from previous cycle

~1~i~:~~~~R15 (MSS)

Y=F
0=log20

Cn+16=F15 'V'F14 (MSS)
OVIi=.t:Z.:~..FllMSSL
Z=OO 010203 ... 015 FO F1 F2 F3 ••. F15
Y=Log 2F
O=Log20

8-178

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CLK

SCLK

C/[)

SOl

SOO

Figure 11. IDT49C403 SPC Timing Waveforms

IDT49C403/A SPC AC TIMING
SYMBOL

PARAMETERS

TEST CONDITIONS

MIN.

MAX.

UNIT

t pD

SCLKTO SOO

3

15

ns

t pD

C/[)to SOO

3

50

ns

t5

C/L5to SCLK

5

-

ns

t5

CLKto c/L5

20

-

ns

10

-

ns

5
5

-

ns
ns

t5

SOl to SCLK

tH

C/15to SCLK

tH

CLKto SCLK

RL
CL

= 500n
= 50pF

ns

tH

SOl toSCLK

5

tw

Pulse Width SCLK

20

-

teye

SCLK Period

50

-

ns

tE

Execution, C/15 to SCLK

50

-

ns

ns

3) Definition of input levels is very important. Since many inputs
may change coincidentally. significant noise at the device pins
may cause the VIL and VIH levels not to be met until the noise has
settled. To allow for this testing/board induced noise. lOT recommends using VIL ~ OV and VIH ~ 3V for AC tests.
4) Device grounding is extremely important for proper device testing. The use of multi-layer performance boards with radial
decoupling between power and ground planes is required. The
ground plane must be sustained from the performance board to
the OUT interface board. All unused interconnect pins must be
properly connected to the ground pin. Heavy gauge stranded
wire should be used for power wiring and twisted pairs are recommended to minimize inductance.

CMOS TESTING CONSIDERATIONS
There are certain testing considerations which must be taken
into account when testing high-speed CMOS devices in an automatic environment. These are:
1) Proper decoupling at the test head is necessary. Placement of
the capacitor set and the value of capacitors used is critical in
reducing the potential erroneous failures resulting from large
Vee current changes. Capacitor lead length must be short and
as close to the OUT power pins as possible.
2) All input pins should be connected to a voltage potential during
testing. If left floating. the device may begin to oscillate causing
improper device operation and possible latchup.

8-179

IDT49C403/A 16·BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C403 INPUT/OUTPUT
INTERFACE CIRCUITRY
Vee
ESD
PROTECTION

OUTPUTS

INPUTS

Figure 13. Output Structure (All Outputs)

Figure 12. Input Structure (All Inputs)

OUTPUTS

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to3.0V

WIns
1.5V
1.5V
See Figure 15
Figure 14. Open Drain Structure

SWITCHING WAVEFORMS
INPUTS

3.0V
O V - - - -.......-

CLOCK 3.0V
OV
CLOCK
TO

~W&~

I-------..j

1.5V

OUTPUTS

TEST LOAD CIRCUIT
Vcc

500n

TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS
C L = Load capacitance includes jig and probe capacitance
R T= Termination resistance: should be equal to ZOUT
of the pulse generator

500n

Figure 15. Test Load Circuit

8-180

IDT49C403/A 16-BIT CMOS MICROPROCESSOR SLICE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

49C403
Device Type

x

x

Speed

Process/
Temperature
Range

y:,onk

L...----------I G
Blank
-I A

L...-_ _ _ _ _ _ _ _ _ _ _ _ _

8-181

Commercial (O°C to + 70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B
Pin Grid Array
Standard
Speed
High Speed

MICROSLICE TM PRODUCT

FEATURES:

DESCRIPTION:

• High speed CMOS
- Microcycle Time: 80ns
• Three bi-directional 32-bit data I/O ports
- DA, DB, Y
• 64-word x 32-bit expandable 7-port register file
- 3 input ports and 4 output ports
- Writes 3 operands and reads 4 operands in one cycle
• 64-bit in, 32-bit out cascadable funnel shifter
- Fast alignment to any bit boundary
• 32-bit high-speed ALU cascadable to 64 bits
- Selects status flags from any bit boundary
• Flexibie mask generator and merge logic
- Selects bit-fields on any width, on any boundary

The IDT49C404 is a cascadable, microprogrammable, highspeed CMOS 32-bit microprocessor slice. This monolithic, highly
parallel, 3-port device consists of a 7-port 64-word by 32-bitworking
RAM, 64 bits in/32 bits out cascadable funnel shifter, high-speed
multi-function 32-bit ALU and 32-bit mask generation and merge
logic.
The IDT49C404 uniquely incorporates shift, ALU and merge
functions into a single cycle and utilizes an orthogonal instruction
set to create a highly parallel architecture that achieves added
performance.
Supporting ultra-fast cycle times, the IDT49C404 offers a verylow-power CMOS alternative to existing bipolar counterparts.
This 32-bit device has been optimized, both architecturally and
instruction set-wise, for use in all types of dedicated intelligent controllers such as high-speed graphics engines, array processors, fast
disk and communication controllers, robotics, data base manipulation, design automation and AI.
Also featured on the IDT49C404 is an innovative diagnostics
capability known as Serial Protocol Channel (SPC). This on-Chip
feature greatly simplifies the task of writing and debugging
microcode, field maintenance debug and test, along with system
testing during manufacturing.
The IDT49C404 is fabricated using CEMOS ™ , IDT's advanced
CMOS technology designed for high-performance and high-reliability. The device is packaged in a 208-lead pin grid array. Military
grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making them ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

•
•
•
•
•

Priority encoder
Powerful orthogonal instruction set
Built-in multiplication/division support
Counter function
Includes Serial Protocol Channel (SPC ™ )
- Flexible on-Chip diagnostics
- Serially monitors all pin states
- Reads and writes to Register File
• Single 5V supply
• Available in 208-pin PGA
• Military product compliant to MIL-STD-883, Class B

SIMPLIFIED BLOCK

DIAGRArM~====;-I_-r-F==l===-l
A

a

liN
64 x 32-Bit
RAM

B

T
DB
OPEA
SEL

MSK

MAG

y
CEMOS MICAOSLICE and SPC are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1967 Integrated DevIce Technology, Inc.

DECEMBER 1987
DSC-0013/-

8-182

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM
DA31-Q

ASEL

BSEL

TC31
TC o

TSEL1-Q
B5- 0

A5-Q

WE"B

WE"A

T5-Q

0 5- 0

WE"T

CP

~~-----4------~- ~B

A

DA

DA A

T

o

B DB

o
Y DA A

T

0

T

B DB

OE'A. MSEL

B

o

T

DB

Y

DA ABO T DB1s Os

r-;:;:~-"'+-+-I-+-4-4-W--4--

SPe_o W5- 0

...........,._....J+-f---,l--+-+__+___+_+--+--__+_-

MSK1_
0

otB.NSEL--+------+---~

VSEL 2 _0

SSEL 2 _0 --4----+------4---i~_ _ _ _..,...----""

FUN 4 -Q
ML ---i------ti

COUTo N.

OVF. C 31
ALU 2_0

--1-------.....

4-------~-----r--~--+_- Co

: ....- - - 1 - - -

MRG 1-0

SDI------.
~----------_+_--OEy

SCLK

C/L>

SDO DCMP ZSEL

8-183

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C404 PIN CONFIGURATION

o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
00000000000000000
00000000000000000
00000000000000000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00000000000000000
00000000000000000
0000000000000000
0000000000000000
1

2

3

4

5

6

7

8

lS

PIN
NO.

A

G2

0

G3

P

G4

N

G14

PIN
NAME

M
L

K

J
H

R2

G

A3
A4

A5

A6

9 10 11

PGA
BOTTOM
VIEW

N17

A7

P1

A8

P2

A9

P3

A10

P4

A11

P5

A12

P6

A13

P7

A14

P8

A15

P9

A16

PIN
NO.

P10

A17

A1

P11

S1
S2

A2

E2

K3

P12

A3

E3

K4

P13

S3

A4

E4

K14

P14

S4

A5

E14

K15

P15

S5

A6

E15

K16

P16

S6

07

E16

K17

P17

S7

DO

E17

L1

01

sa

09

F1

L2

02

S9

010

F2

L3

03

S10

011

F3

L4

04

S11

012

F4

L14

05

S12

S13

A7

A13

C13

013

F14

L15

06

A14

C14

014

F15

L16

07

S14

A15

C15

015

F16

L17

08

S15

A16

B16

C16

016

F17

M1

09

S16

A17

B17

C17

017

G1

M2

010

S17

8-184

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
PIN NAME

DESCRIPTION

DA31-0

Thirty-twa-bit data input/output port is under control of the signal C5"E"A. When the OEA is low, RAM output port A can be directly
read on these lines. Data on these lines can be selected as the source for the ALU, funnel-shifter or loaded into port A of the
working RAM.

DB 31 - 0

Thirty-twa-bit data input/output port is under control of the signal C5"E" B' When the C5"E"B is low, RAM output port B can be directly
read on these lines. Data on these lines can be selected as the source for the ALU, funnel-shifter or loaded into port B of the
working RAM.

Y31 - 0

Thirty-twa-bit data input/output port is under control of the signal OE y. When OEy is low, the merge output can be directly
read on these lines. Data on the lines can be loaded into port T of the working RAM or selected as the source for the ALU
when "OE"y is high.

~y

A control input pin which, when low, enables the output of merge-logics on the lines Y31 - 0 and, when high, disables the
Y31-0 three-state output buffers.

WF:.A

The write control signal for RAM input port A. If the signal
(input port A) when the clock signal is low.

WE"a

The write control signal for RAM input port B. If the signal WF:.a is low, the data on the DB lines or Z bus is written into the RAM
(input port B) when the clock signal is low.

WE"T

The write control signal for RAM input port T. If the signal WF:.T is low, the data on the Z lines, Y lines, T
into the RAM (input port T) when clock signal is low.

OE'A

A control input for data input/output port DA. When"OE"A is low, RAM output port A is read on the DA line. When OE A is
high, the data on the data lines can be selected as the source for the ALU or loaded into port A of the working RAM.

C5"E"a

wr:.A is low, the data on the DA lines or Z bus is written into the RAM

+ C1 arT + C2 is written

A control input for data input/output port DB. When OE'a is low, RAM output port B can be read on these lines. When is
~B high, the data on the DB lines can be selected as the source for the ALU or loaded into port T of the working RAM.

CP

The clock input to the IDT49C404. When clock is low, data is written in the seven-port RAM.

TC o

Used as carry input for the T counter.

TC31

Used as carry output for the T counter.

ML

The input pin which can be used to load the external bit in order to fill in the vacant positions of a word in shift-linkage.

Co

The carry input to the least significant bit of the ALU.

COUT

Indicates the carry-output.

N

Indicates the sign N of the ALU operation.

OVF

Indicates the conventional two's complement overflow.

C31

The carry output pin which is used to ripple the carry in the expansion mode (64-bit).

ZERO

The open drain input/output pin which, when high, generally indicates that all outputs are low.

ALU z_o

Instruction inputs are used to select the operations for the ALU.

As-o

Six RAM address inputs which contains the address of the RAM word appearing at RAM output port A and into which new
data is written when WF:.A is low.

B s- o

Six RAM address inputs which contains the address of the RAM word appearing at RAM output port B and into which new
data is written when WF:.a is low.

Ts- o

Six RAM address inputs which contains the address of the RAM word appearing at output port T and into which new data
is written under control of TSEL.

ASEL

Defines what data RAM port A receives, either DA or Z bus.

BSEL

Defines what data RAM port B receives, either DB or Z bus.

0 5- 0

Six RAM address inputs which contain the address of the RAM word appearing at output port O.

SP6- 0

The seven pins are used to specify the start positions or the number of shift positions.

Ws-o

The six pins are used to specify the word width.

ZSEL

Selects the source of the Z bus between the output of the ALU (F) or the Y bus.

MSEL

Taken together with OE A, selects the source of the M input into the funnel shifter.

NSEL

Taken together with OE'a, selects the source of the N input into the funnel shifter.

VSELz- o

Selects the source of the V bus used for merging with the output of the ALU.

ZD

Chooses zero detect of the ALU output (F) or the Y bus.

SSELz_o

Selects the source of the S operand input to the ALU.

FU N 4-0

Controls the operation of the funnel shifter.

MSK1-0

Selects the function of the mask generator.

MRG1-0

Controls the merge function.

8-185

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS (Cont'd)
DESCRIPTION

PIN NAME
TSEL1-Q

Selects the source of the data to be written into the T port of the RAM.

SOl

Serial data input to the SPC command and data registers for diagnostics.

SOO

Serial data output from SPC command and data registers for diagnostics.

SCLK

SHIFT clock for loading the SPC command and data registers for diagnostics.

Cf[)

Command/data control input for SPC operation.

DCMP

The open drain compare output for SPC diagnostics.

VCC 7-Q

Eight pins for power supply 5 volt, all of which must be connected to 5 volts.

GNOl6-0

Sixteen pins for ground, all of which must be connected to ground.

SEVEN-PORT RAM

DEVICE ARCHITECTURE
The IDT49C404 is a high-speed 32-bit microprogram mabie
CMOS microprocessor slice which can be cascaded to 64-bits. It
allows simple, yet high-speed, arithmetic and logic operations on
subfields, shift, rotate, mask and merge.
In general, the IDT49C404 can be viewed as a 7-port working
RAM feeding into a funnel shifter, then into an ALU and then into
merge logic. The control of each of these blocks is orthogonal, allowing the user to select data from registers, shift it, operate on it with
the ALU and then merge it in only one cycle. Optionally, the funnel
shifter or ALU can be bypassed, allowing the user additional flexibility. In this way, the designer may avoid paying a performance penalty when a particular algorithm requires only one or the other. Thus,
the cycle time can be tailored to match the processing
requirements.
The IDT49C404 can "be divided into the following functional
segments:
- Three 32-bit bidirectional I/O ports
- Seven-port 64-word x 32-bit RAM
- 64 bits in/32 bits out cascadable funnel shifter
- 32-bitALU

The IDT49C404 incorporates a 64-word by 32-bit RAM which has
seven ports - four read ports and three write ports. The four read
ports are A, B, Q and T. The A and B ports are considered the data
path ports and can be used interchangeably. During most cycles,
they supply data to the funnel shifter, ALU and merge logic. These
ports can be considered to be similar to the A and B ports of the
IDT39C203. The Q and T output ports are used mainly for controlling such things as start and width for the funnel shifter and mask
generation for merge operations. Since the Q and T ports are
outputs of the RAM, the start positions may be computed on previous cycles using the ALU, thus providing extensive programmer
flexibility.
There are three write ports; A; Band T. The A and B ports are typically used for results from the current cycle and the T port is used
for incrementing counter values in the RAM, as well as loading data
from the Y bus in parallel with ALU operations. There are four address buses controlling A, B, Q and T. In one cycle, the seven-port
RAM is capable of writing to three locations while reading from four
locations. This feature highlights the IDT49C404's highly parallel
arch itecture.

64-81T FUNNEL SHIFTER

- Mask generator
- Merge logic

The funnel shifter accepts two 32-bit operands (A, B, 0, DA, DB or

n which are operated on as a 64-bit word. The output of the funnel

- Diagnostics circuitry

THREE BUS ARCHITECTURE
The IDT49C404's 3-bus architecture consists of three bidirectional 32-bit ports (DA, DB and Y). The DA and DB
bl-directional buses connect respectively to the A and B RAM outputs and A and B RAM inputs. Thus, data can be read out of the RAM
on DA and DB or data can be brought in independently on DA and
DB. This special feature allows for easy RAM expansion. Since data
can be brought out on the DA and DB buses, other ALU elements
can be connected externally which extend the overall ALU, funnel
shifter, mask and merge capabilities.
The third 32-bit bus, Y, is the output of the merge logic and also
the Input back Into the RAM ports A, Band T via the Z bus or internal
Y bus.The Z MUX multiplexes between the ALU or the Y bus. By selecting the output of the ALU, the results of the ALU operation can be
stored back into the RAM while data may be brought out through the
merge path onto the Y bus. This results in an ALU operation in parallel with the extraction of data out of the register file. Additionally,
there is an altemate data path which allows the Y bus to connect directly into the T MUX such that data can be written from the ALU
back into the RAM while data is being brought in, at the same time,
through the Y bus to the RAM.
This three bus approach allows for the easy data accessibility
necessary when designing high-performance microprocessorbased systems.

shifter is the result of selecting any consecutive 32-bit word within
the 64-bit operand. The 32-bit word can start on any bit boundary
between 0 and 31. The M and N input muxes allow the user to swap
the data as well as duplicate it, allowing for barrel shifting. The funnel shifter also has the capability of taking any 32-bit word as an
input and extending the sign, as well as providing zero fill. Through
special hooks in the architecture, the funnel shifter can be expanded
along with the ALU/merge logic to perform 64-bit operations in a
single cycle.

ALU
The output of the funnel shifter feeds the 32-bit ALU. The ALU can
perform conventional binary operations such as logic, addition,
subtraction, as well as multiplication and division. Also, the sum of
the start and the width information can be used to select the bit
boundary from which the carry, sign and overflow flags will output
as status. This allows for true arbitrary subfield operations. The other
ALU inputs are selected from A, B, 0, T or mask generator.

MASK GENERATION AND MERGE LOGIC
The mask generation and merge logic allows for field manipulation within the 32-bit resulting word. The mask generator, which
determines how the bits will be merged between V and F, is controlled by start and width input pins. The start and width can also
come from 0 or T. T is used for start and 0 is used for width, thus
start/width can be calculated, stored in the register file and used in
the mask generator. An alternate to the mask generator is a mask

8-186

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

which comes directly from the Q or T outputs of the RAM, allowing
for totally arbitrary masks.
The V input of the merge logic comes from a multiplexer which
can select any output of the RAM, OA, OB,all1sorallOs. The Finput
is connected to the output of the ALU. The mask is used to merge the
V and F input on a bit-by-bit basis, which results in the Y output.
Included in the merge logic is a priority detect circuit. It is used
to produce a binary weighted code to indicate the location of the
highest order one on its input.

The IOT49C404 accommodates a variety of diagnostics operations. It not only includes the standard Serial Protocol Channel but
also the ability to scan data out of the I/O pad cells (as shown in Figure 2) which are connected to the pins of the device. In this way, the
state of external connections can be observed, thus telling a lot
about the system surrounding the IOT49C404. The scan path
through the I/O pad cells is in series with the serial data register.

SERIAL DIAGNOSTICS
The Serial Protocol Channel (SPC) is a set of pins by which data
can be entered Into and extracted from a device (such as the
IOT49C404) through a serial data input and output port. SPC can be
used at many points in the life of a product for diagnostic purposes
such as: system level design debug and development, system test
during manufacturing and field maintenance debug and test. SPC is
of significant benefit as board level packing densities increase. This
is because access to test and debug points becomes difficult. This
is particularly true in double-sided surface mount technologies.
As companies like lOT continue to integrate more onto each device and put each device into smaller and smaller packages such
as surface mount devices, the board level testing becomes more
complex for the designer and the manufacturing divisions of companies. To help this situation, a serial diagnostics scheme was developed. It allows for observation of critical signals deep within the
system. During system test, when an error is observed, these signals
may be modified in order to zero in on the fault in the system.
SPC is''''primarily a scheme utilizing only four pins SOl, SOO,
SCLK, C/O to examine and alter the internal state of a system, for
the purpose of monitoring and diagnosing system faults. The SPC
has been defined in such a way that it can be implemented with
a small number of gates. In many cases, SPC can be added by utilizing less than 5% of the total logic gates. As more gates are added
to each device and the number of pins increase, the overhead for
diagnostics decreases.
In the following block diagram of a typical application, the Serial
Protocol Channel is shown being used with a writable control store
in a microprogrammed design. The control store can be initialized
through the SPC path. A register with SPC is used for the instruction
register going into the IOT49C410 (16-bit microprogram sequencer) , as well as data registers around the lOT49C404. In this way, the
designer may use the Serial Protocol Channel to observe and modify the microcode coming out of the writable control store, as well as
observing and being able to modify data and instructions in the
overall machine.
The block diagram of the diagnostics ring in Figure 1 shows how
the devices with diagnostics are hooked together in a serial ring via
the SOl and SOO signals. The diagnostics Signals may be generated through registers which are hooked up to a microprocessor.
This microprocessor could conceivably be an IBM PC.

C/1:5

SDO

SDI

SCLK

Figure 2. Conceptual Diagram of IDT49C404 Die Incorporating SPC
Scan Path

CONTROL INPUTS
The control inputs of the IOT49C404 which make up the instruction set are highly orthogonal and provide the user with the highest
degree of control over each individual functional unit. Each major
unit in the IOT49C404 has its own set of control lines. The following
diagrams show the microprogram word layout of the individual
fields, as well as the opcodes and functions for each of the fields.
In order to maintain simplicity and orthogonality, the instruction
combinations which are used infrequently and require special extended control (divide, multiply, etc.) are grouped together and
labled as special instructions. To use these instructions, a special
instruction trap door mechanism was employed in the ALU control
field (opcode = 101). In the case of special instructions, the T
source select and merge control define the particular instructions
to be performed. Some special instructions require immediate operands which are provided by other fields such as start, width, funnel
shift contrOl, etc.

Figure 1. Typical Microprogram Application With SPC

8-187

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C404 INSTRUCTION FIELDS
44

4342 41

40 39 38 37

36 35 34

OE"y OI:A MSEL SSEL MASK ML
'GEe NSEL
GEN

30 29

FUNNEL
SHIFTER

24 23

WIDTH

17 16
START

14 13

TSEL

16-BIT IMMEDIATE FIELD
7-BIT IMMEDIATE FIELD

12 11

ALU

10 9

MRG

7 6

5 4

3 2

SPECIAL INSTRUCTION
FIELD

INSTRUCTION SET SUMMARY
N SOURCE SELECTION

M SOURCE SELECTION
MNEMONIC

~A

MSEL

M SOURCE

MNEMONIC

OEe

NSEL

AOE

0

0

A

BOE

0

0

B

T

0

1

T

0

0

1

0

A

1

0

A

B

1

0

B

DA

1

1

DA

DB

1

1

DB

N SOURCE

MASK SOURCE
MNEMONIC

MSK

EXT

0

SOURCE

0

Start and Width from Instruction
T & 0 Supply Start and Width

INT

0

1

T32

1

0

T as a 32-Bit Mask

032

1

1

o as a 32-Bit Mask

S SOURCE
MNEMONIC

ALU
MNEMONIC

ALU

FUNCTION

ADD

0

0

0

R+S+Co

SUBR

0

0

1

S-R-1+Co

SUBS

0

1

0

R-S-1+Co

OR

0

1

1

R orS

AND

1

0

0

Rand S
Special Instruction

-

1

0

1

EXOR

1

1

0

R exorS

EXNOR

1

1

1

R exnor S

SSEL

SOURCE

DA

0

0

0

A

0

0

1

DA
A

0

0

1

0

0

T

0

1

1

T

B

1

0

0

B

DB

1

0

1

DB

Y

1

1

0

Y

MASK

1

1

1

MASK

V SOURCE
MNEMONIC

VSEL

SOURCE

MERGE CONTROL

DA

0

0

0

DA

MNEMONIC

A

0

0

1

A

F

0

0

0

0

1

0

0

V

0

1

Pass V

T

0

1

1

T

FtoV

1

0

Merge FN

B

1

0

0

B

Vto F

1

1

Merge V/F

DB

1

0

1

DB

ZEROS

1

1

0

O's

ONEs

1

1

1

1's

8-188

MRG

0

ZSEL ASEL WEA
VSEL
WEe
ZD
BSEL WET

FUNCTION
Pass F

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SPECIAL INSTRUCTIONS (AlU = 101)
MNEMONIC

VSEl

MRG

FUNCTION

OPERANDS

UMLT

0

0

0

0

0

Unsigned Multiply

A,B,T

TMLT

0

0

0

0

1

Two's Complement Multiply

A,B,T

TMLTL

0

0

0

1

0

Two's Complement Multiply Last Cycle

A,B,T

DIVF

0

0

0

1

1

First Divide

A. B, T

DIV

0

0

1

0

0

Second Divide

A,B,T

DIVL

0

0

1

0

1

Last Divide

A,B,T

PRF

0

0

1

1

0

Prioritize First Cycle (32 Bits)

S, Mask

PRS

0

0

1

1

1

Prioritize Second Cycle (64 Bits)

INC

0

1

0

0

0

S

DEC

0

1

0

0

1

S -Imm (7-Bit) - 1

LDI

0

1

0

1

0

Load T with Imm (16-Bit)

LDC1

0

1

0

1

1

Load C1 from Z bus

LDC2

0

1

1

0

0

Load C2 from Z bus

EXCHG

0

1

1

0

1

Exchange RAM Locations

LDAB

0

1

1

1

0

Load DA into B address

DA

LDBA

0

1

1

1

1

Load DB into A address

DB

SMAGT

1

0

0

0

0

Sign Magnitude/Two's Complement Conversion

S

PROGS

1

0

0

0

1

Program Slice

-

+

Imm (7-Bit)

+

S
S,lmm

Co

+ Co

S,lmm
16-Bit Imm
S
S
DA, DB

Z BUS CONTROL
ZBUS SOURCE

T SOURCE
MNEMONIC

TSEL

SOURCE

MNEMONIC

ZSEL

SOURCE

Z

0

0

Z Bus

F

0

F Bus

Y

0

1

Y Bus

Y

1

Y Bus

TC1

1

0

T

TC2

1

1

T

+
+

C1
C2

+ TC o
+ TCo
ZERO DETECT SOURCE

A RAM DEST
MNEMONIC

ASEl

SOURCE

DA

0

DA Bus

Z

1

Z Bus

MNEMONIC

BSEl

Z

0

Z Bus

DB

1

DB Bus

B RAM DEST
SOURCE

8-189

MNEMONIC

ZD

F

0

SOURCE
F Bus

Y

1

Y Bus

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNNEL SHIFT OPERATIONS
MNEMONIC

FUN

FUNCTION

OPERANDS

SMLZ

0

0

0

0

0

Shift M and fill with 0

SNLZ

0

0

0

0

1

Shift N and fill with 0

SMLM

0

0

0

1

0

Shift M and fill with ML

ML,M

SNLM

0

0

0

1

1

Shift N and fill with ML

ML, N

XNM

0

0

1

0

0

Extract field from

N,M

XMN

0

0

1

0

1

Extract field from

M,N

SMAZ

0

0

1

1

0

Shift M arithmetic and fill 0

SNAZ

0

0

1

1

1

Shift N arithmetic and fill 0

SMAM

0

1

0

0

0

Shift M arithmetic and fill ML

Sign, M, ML

SNAM

0

1

0

0

1

Shift N arithmetic and fill ML

Sign, N, ML

BM

0

1

0

1

0

Barrel shift M

BN

0

1

0

1

1

Barrel shift N

N

PM

0

1

1

0

0

Pass M

M

PN

0

1

1

0

1

Pass N

N

PZ

0

1

1

1

0

Pass all Os

0

PO

0

1

1

1

1

Pass all1s

SMLZBA

1

0

0

0

0

Shift M and fill with 0, Bypass ALU

SNLZBA

1

0

0

0

1

Shift N and fill with 0, Bypass ALU

SMLMBA

1

0

0

1

0

Shift M and fill with ML, Bypass ALU

ML,M

SNLMBA

1

0

0

1

1

Shift N and fill with ML, Bypass ALU

ML, N

XNMBA

1

0

1

0

0

Extract field from N & M, Bypass ALU

N,M

XMNBA

1

0

1

0

1

Extract field from M & N, Bypass ALU

SMAZBA

1

0

1

1

0

Shift M arith. and fill 0, Bypass ALU

O,M
0, N

Sign, M, 0
Sign, N, 0

M

1
O,M
O,N

M,N
Sign, M, 0

SNAZBA

1

0

1

1

1

Shift N arith. and fill 0, Bypass ALU

SMAMBA

1

1

0

0

0

Shift M arith. and fill ML, Bypass ALU

Sign, M, ML

SNAMBA

1

1

0

0

1

Shift N arith. and fill ML, Bypass ALU

Sign, N, ML

BMBA

1

1

0

1

0

Barrel shift M, Bypass ALU

BNSA

1

1

0

1

1

Barrel shift N, Bypass ALU

N

POCM

1

1

1

0

0

Pass 1s Complement of M

M

POCN

1

1

1

0

1

Pass 1s Complement of N

N

PMFM

1

1

1

1

0

Pass M and fill ML bit from BitO to SP

M

PNFM

1

1

1

1

1

Pass N and fill ML from BitO to SP

N

8-190

Sign, N, 0

M

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

CAPACITANCE

(1)

COMMERCIAL
-0.5 to +7.0

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MILITARY
-0.5ta +7.0

UNIT

SYMBOL

V

CIN
Cl/o(2)

TA

Operating
Temperature

Oto +70

-55 to +125

or.

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.S

1.S

W

lOUT

DC Output Current

50

50

rnA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance
I/O Capacitance

CONDITIONS

TYP.

UNIT

"IN = OV

10

pF

VOUT= OV

15

pF

NOTE:
1. This parameter is sampled and not 100% tested.
2. Includes only output pins.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V ± 5% (Commercial)
Vee = 5.0V ± 10% (Military)

TA = O°C to + 70°C
TA = -55°C to + 125°C

MIN.

TYP.(2)

MAX.

UNIT

Vec = Max.

2.0

-

-

V

Input LOW Level (4)

Vcc = Min.

V

Input HIGH Current

Vcc = Max., "IN = Vcc

-

O.S

IIH

5

~A

IlL

Input LOW Current

Vcc = Max., "IN = OV

-

-

-5

~A

10H = -300~A

VHC

Vcc

IoH = -6mA MIL.

2.4

4.3

V

IoH = -SmA COM'L.

2.4

4.3

-

-

GND

VLe

SYMBOL

Input HIGH Level

"IL

VOH

TEST CONDITIONS (1)

PARAMETER

"IH

(4)

Output HIGH Voltage

Vee = Min.
"IN = "IH or"lL

IoL = 300~A
VOL

loz

Output LOW Voltage

Off State (High Impedance)
Output Current

Vce = Min.
"IN = "IH or"lL

IoL = 12mA MIL.
IoL = 15mA COM'L.

Va
Vec = Max.

= OV

Vo = Vee (Max.)

0.3

0.5

0.3

0.5

-

-0.1

-10

-

0.1

10

-

-

Vcc = Min., VOUT = OV (3)
-15
Short Circuit Current
los
NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one !ime. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a nOise-free environment.

8-191

V

~A

rnA

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = OOC to + 70°C
TA = -55°C to +125°C
VLC = 0.2V
VHC = Vcc - 0 2V
SYMBOL

VCC = 5.0V ±5% (Commercial)
Vcc = 5.0V ± 10% (Military)

TEST CONDITIONS

PARAMETER

(1)

MIN.

TYP.(2)

-

-

-

mA

MAX.

UNIT

ICCOH

Quiescent Power Supply Current
CP = H

Vcc = Max.
\'JH ~ VHC ' VIL OS; VLC
f CP = 0, CP = '6c

ICCOL

Quiescent Power Supply Current
CP = L

Vcc = Max.
\'JH ~ VHC ' V1L OS; VLC
fcp = 0, CP = OV

-

-

-

mA

ICCT

Quiescent Input Power Supply (5)
Current (per Input @ TIL High)

VCC = Max. VIL

-

-

-

mA

-

-

-

Dynamic Power Supply Current

Vcc = Max.
VHC OS; \'JH' \'JL os;-.Ylc
Outputs Open, OE = OV

MIL.

ICCD

COM'L.

-

-

-

MIL.

-

-

-

COM'L.

-

-

-

MIL.

-

300

400

COM'L.

-

250

350

= 3.4V, fcp = 0

Vcc = Max., fcp = 10MHz
Outputs Open, ~ = OV
50% Duty cycle
VHC OS; '-"Ho VIL OS; VLC
ICC

Total Power Supply Current

(6)

VCC = Max., fc'bE- 10MHz
Outputs Open,
= OV
50% Duty cycle
'-"H = 3.4V, '-"l = O.4V

mAl
MHz

mA

NOTES:
5. CCOT Is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out ICCOCH' then dividing by the total number of inputs.
6. Total Supply Current is the sum of the Quiescent current and the Dynamic current (at either CMOS orTIL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = 'ccOH(CDH) + Iccol (1 - CD H) + ICCT (NT X DH) + ICCD (fcp)
CDH = Clock duty cycle high period
DH = Data duty cycle TIL high period (VIN = 3.4V)
NT = Number of dynamic inputs driven at TIL levels
fcp = Clock Input frequency

3) Device grounding is extremely critical for proper device test-

CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test environment. Large output currents are being switched in very short
periods and proper testing demands that test set-ups have minimized Inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing
results:

1) All Input pins should be connected to a voltage potential durIng testing. If left floating, the device may oscillate, causing improper device operation and possible latchup.

2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be distributed to
decouple power supply lines and be placed as close as possible
to the OUT power pins.

8-192

ing. The use of multi-layer performance boards with radial decoupiing between power and ground planes is necessary. The
ground plane must be sustained from the performance board to
the OUT interface board and wiring unused interconnect pins to
the ground plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being recommended for minimized inductance.

4) To guarantee data sheet compliance, the input thresholds
should be tested per input pin, in a static environment. To allow
for testing and hardware-induced noise, lOT recommends using
VIL :s OV and VIH ~ 3V for AC tests.

-------------------------------- ----------------_._-_.-

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C404 PROPAGATION DELAYS
TA

= OOC to

+ 70°C, Vee

=

(1)

+5V ±5%
TO OUTPUT
Y

FROM INPUT

ALU
only

FS
only

A,B,a,T

55

55

DA,DB

37

37

NSEL, MSEL,
MS, NS, OEA,
DEB

-

-

-

MSK, FS, STR, W
ALU

ALU
& FS

ALU
only

FS
only

75

58

58

56

40

40

-

-

-

-

-

-

-

-

-

-

-

-

ALU
& FS

ALU
only

FS
only

78

-

-

60

-

-

-

li

- ( »,

2i2±

MRG, ZD
Y

-

-

-

-

-

-

-

-

-

'£7

ec

~\ \\ ,." •. ··,·,·····+·/,)C
··"·Uc
"" •••• H,·
H> -

-Hi ),

-:}

ALU
& FS

ALU=""'" ..... ALU
only
')~fS

. ,. 1,.;;;
- """""1"'2""':~
-,4(),(

36

Co

STATUS
FLAGS

DCMP

ZERO

. . . .•. . . 1.,. . . . [>
C>__) I>
I

BE::
>i'
-

-

;

••

•••.••••••••'....

~HUI' .

UNIT

ns

34\1/' ns

I···i)··'··~
-

-

-

ns
ns
ns
ns

-

-

ns
ns

"".,.'
NOTE.
......
.. . .
1. On any given cycle, an arithmetic operation without a Shifti:lp~ratj()ri¢aDb~p~rform~d(ALU only) or a shift operation without an arithmetic operation can
be performed (FS only) or, finally, both operations in seri¢$inClbe,$illgle9ycl~ (ALU + FS) .
........•••••••••••••............. "' .........•••.•.••••.•.•••••••••.•.••.....•.•.•••..•••.'.....,.......•,'.','."

SET-UP AND HOLD

TIMES~~LATIVEf6cLOa~ {CP INPUT

··~---f
HOLD TIME
AFTER H-L

Aiij!. T;9AddM~~>

($Qur9E:!Or Destiriatiqb)

18

SET-UP TIME
BEFORE L-H

HOLD TIME
AFTER L-H

o

UNIT
ns

o

ns

o
o

ns

ns

ILiNES

Y

8-193

ns

IDT49C404/A 32-BIT CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C404A PROPAGATION DELAYS

(1)

o

TA = OOCto +70 C, Vee = +5V ±5%
TO OUTPUT

Y
FROM INPUT

ALU

FS

only

only

ALU
& FS

ALU
only

FS

only

STATUS»
FLAGS)::::'"

DCMP

ZERO
ALU
&FS

ALU

FS

only

only

ALU
& FS

ALU';';;,Al:l,.I,
pnly , '/a.;FS\

UNIT

A,B,Q,T
DA,DB
NSEL, MSEL,
MS, NS, 'OrA,

L5E"B
MSK, FS, STR, W

ALU
Co
MRG,ZD

ns

Y

ns

""",
NOTE:
1. On any given cycle, an arithmetic operation without a Shift~B¥ratio~8~b~p~rform~diAtu only) or a shift operation without an arithmetic operation can
be performed (FS only) or, finally, both operations in serie~in()~ElSinglecy6Ie (ALU + FS).

t---f
HOLD TIME
AFTER H-L

'·':A"·'s TdAddr~~k.·,'."

SET-UP TIME
BEFORE L-H

HOLD TIME
AFTER L-H

UNIT
ns

'(s()qr~*6ibestiriati96l"

ns
ns

I LINES

ns

y

ns

8-194

IDT49C404/A 32-81T CMOS MICROPROGRAM
MICROPROCESSOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST LOAD CIRCUIT

SWITCH POSITION
TEST
Open Drain
Disable Low
Enable Low
All Other Outputs

SWITCH
Closed
Open

DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to ZoUT of the
Pulse Generator

Figure 1. Switching Test Circuits (All Outputs)

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

Wins
1.5V
1.5V
See Figure 1

ORDERING INFORMATION
IDT

XXXXXXX
Device Type

x
Process/

Tem~~ :~NK

Commercial (O°C to + 70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B

PG

G
49C404
49C404A

8-195

208-pin Plastic Pin Grid Array
208-pin Pin Grid Array
32·Bit CMOS Microprogram Microprocessor
High-Speed 32·Bit CMOS Microprogram
Microprocessor

MICROSLICE

'01

PRODUCT

FEATURES:

DESCRIPTION:

• 16-bit wide address path
- Address up to 65,536 words of microprogram memory

The IDT49C41 Os are architecture and function code compatible
to the 2901A with an expanded 16-bit address path, thus allowing
for programs up to 65,536 words in length. They are microprogram
address sequencers intended for controlling the sequence of execution of microinstructions stored in microprogram memory. Besides the capability of sequential access, they provide conditional
branching to any microinstruction within their 65,536 microword
range.
The 33-deep stack provides microsubroutine return linkage and
looping capability. The deep stack can be used for highly nested
microcode applications. Microinstruction loop count control is
provided with a count capacity of 65,536.
During each microinstruction, the microprogram controller provides a 16-bit address from one of four sources: 1) the
microprogram address register (jJPC), which usually contains an
address one greater than the previous address; 2) an external (direct) input (D); 3) a register/counter (R) retaining data loaded during a previous microinstruction; or 4) a last-in/first-out stack (F).
The IDT49C410s are fabricated using CEMOS, a CMOS technology designed for high performance and high reliability.
The IDT49C410s are pin-compatible, performance-enhanced,
easily upgradable versions of the 2901A.
The IDT49C41Os are available in 48-pin DIPs (600 mil x 100 mil
centers or space-saving 400 mil x 70 mil centers), 48-pin LCC,
52-pin PLCC and 48-pin flatpacks.

• 16-bit loop counter
- Pre-settable down-counter for counting loop iterations and
repeating instructions
• Low-power CEMOS ™
-Icc (max.)
Military: 90mA
Commercial: 75mA
• Fast
- IDT49C410 meets 2910A spe~ds
- IDT49C410A 30% speed upgrade
• 33-deep stack
- Accommodates highly nested microcode
• 16 powerful microinstructions
- Executes 16 sequence control instructions
• Available in 48-pin 600 mil plastic and sidebraze, 48-pin 400 mil
SHRINK-DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack
• Three enables control branch address sources
• Four address sources
• 2901A instruction compatibility
• Military product available compliant to MIL-STD-883, Class B

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

DECREMENT/
HOLD/LOAD

R=O

CI

OE

C=~------+---+---r-------~~

DIP
TOP VIEW
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-9014/-

8-196

IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

UUULJ WII LJUU UULJ

6 5 4
VECT

PC
MAP
13
12
VCC
11
10
CCEN
CC
RLD
FULL

3 2

U

]9
] 10
] 11
] 12
] 13
] 14
;] 15
] 16
]17
] 18

7

48 47 46 45 44 43
42
41
40
39
38
37
36
35
34

]7
]8

L48-1

[:
[
[:
[
[
[
[:
[
[:

33 [:
32 [
31 [

6 5 4

3 2 1 52 51 50 49 48 47
46
45
44
43
42
41
40
39
38
37
36
35
34

VECT

D1
Y1
Do
YO
CI
CP
GND

PC
MAP
13
12
Vcc

J52-1

11
10

OE
Y 11

CCEN
CC
RLD
FULL
NC

D11
Y10
DlO

19 20 21 22 23 24 25 26 27 28 29 30

nnnnnnnnnnnn

21 22 23 24 25 26 27 28 29 30 31 32 33

PLCC
TOP VIEW

LCC
TOP VIEW

IDT49C410 PIN DESCRIPTIONS
PIN NAME

1/0

DESCRIPTION

DI

I

Direct input to register/counter
and multiplexer, Do is LSB.

II

I

Selects one of sixteen instructions.

CC

I

Used as test criterion. Pass test is a
LOW on CC.

CCEN

I

Whenever the signal is HIGH, CC
is ignored and the part operates
as though CC were true (LOW).

CI

I

Low order carry input to incrementer for microprogram counter.

RLD

I

When LOW forces loading of register/counter regardless of instruction or condition.

OE

I

Three-state control of YI outputs.

I

Triggers all internal state changes
at LOW-to-HIGH edge.

YI

0

Address to microprogram
memory. Yo is LSB, '115 is MSB.

FULL

0

Indicates that 33 items are on the
stack.

PL

0

Can select #1 source (usually
Pipeline Register) as direct input
source.

MAP

0

Can select #2 source (usually
Mapping PROM or PLA) as
direct input source.

VECT

0

Can select #3 source (for
example, Interrupt Starting
Address) as direct input source.

CP

Pin 1 Identifier
484746454443424140393837
36

35
34

33
32
31
30

F48-1

29

10
11
12

28
27
26

./

"-

1314151617 181920 21 2223 24

FLATPACK
TOP VIEW

8-197

25

IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

linkage (the value contained in the microprowam counter) ..On the
microprogram cycle following the PUSH, this new return linkage
data that was in the microprogram counter is now at the new location pointed to by the stack pointer. Thus, any time the multiplexer
looks at the staCk, it will see this data on top of the stack.
During five different microinstructions, a pop operation associated with the stack may occur. If the pop occurs, the stack pointer is
decremented at the next LOW-to-HIGH transition of the clock. A
pop decrements the stack pointer which is the equivalent of removing the old information from the top of the stack.
The IDT49C410s are designed so that the stack pointer linkage
allows any sequence of pushes, pops or stack references to be
used. The depth of the stack c~ow to a full 33 locations. After a
depth of 33 is reached, the FULL output goes LOW. If further
PUSHes are attempted when the stack is full, the stack information
at the top of the stack will be destroyed but the stack pOinter will not
end around. It is necessary to initialize the stack pointer when
power is first turned on. This is performed by ex~cuting a RESET
instruction (instruction 0). This sets the stack pOinter to the stack
empty position-the equivalent depth of o. Similarly, a pop from an
empty stack may place unknown data on the Y outputs, but the
stack pointer is designed so as not to end aroun~. ~hus, the. stack
pointer will remain at the 0 or stack empty location If a pop IS executed while the stack is already empty.
The IDT49C410s' internal 16-bit register/counter is used during
microinstructions eight, nine and fifteen. During these instructions,
the 16-bit counter acts as a down counter and the terminal count
(count = 0) is used by the internal instruction :'LA as an input to
control the microinstruction branch test capability. The deSign of
the internal counter is such that, if it is preloaded with a number N
and then this counter is used in a microprogram loop, the actual
sequenceinthe loop will be executed N + 1 time~. T~us, itis~oSSi­
ble to load the counter with a count of 0 and thiS Will result In the
microcode being executed one time. The 3-way branch microinstruction, instruction 15, uses both the loop counter and the external condition code input to control the final source address from
the Y outputs of the microprogram sequencer. This 3-way branch
may result in the next address coming from the D inputs, the stack
or the microprogram counter.
The IDT49C410s provide a 16-bit address at the Youtputs that
are under control of the OE input. Thus, the outputs can be put in
the three-state mode, allowing the writable control store to be
loaded or certain types of external diagnostics to be executed.
In summary, the IDT49C410s are the most powerful
microprogram sequencers currently available. They provide t~e
deepest staCk, the highest performance and the lowest power diSsipation for today's microprogrammed machine design.

PRODUCT DESCRIPTION
The IDT49C410s are high-performance CMOS microprogram
sequencers that are intended for use in very high-speed
microprogram mabie microprocessor applications. !he sequencers allow for direct control of up to 64K words of microprogram.
The heart of the microprogram sequencer is a 4-input multiplexer that is used to select one of four address sources t? select
the next microprogram address. These address sources Include
the register/counter, the direct input, the microprogram counter or
the stack as the source for the address of the next microinstruction.
The register/counter consists of sixteen D-type flip-flop~ which
can contain either an address or a count. These edge-tnggered
flip-flops are under the control of a common clock enable as well as
the four microinstruction control inputs. When the load control
(RDL) is LOW, the data at the D-inputs is loaded into this regist~r on
the LOW-to-HIGH transition of the clock. The output of the reglster/
counter Is available at the multiplexer as a possible next address
source for the microcode. Also, the terminal count output associated with the register/counter is available atthe internal instruction
PLA to be used as a condition code input for some of the
microinstructions. The IDT49C410s contain a microprogram
counter that usually contains the address of the next microinstruction compared to that currently being executed. The
microprogram counter actually co~sists of a 16-bit increm~nt.erfol­
lowed by a 16-bit register. The microprogram counter wlllincrement the address coming out of the sequencer going to the
microprogram memory if the carry-in input to this counter is HIGH;
otherwise this address will be loaded into the microprogram
counter. Normally, this carry-in input is set to the logic HIGH state
so that the incrementer will be active. Should the carry input be set
LOW the same address is loaded into the microprogram counter.
This is a technique that can be used to allow execution of the same
microinstruction several times.
There are sixteen O-inputs on the lOT49C41 Os that go directly to
the address multiplexer. These inputs are used to provide a branch
address that can come directly from the microcode or some other
external source. The fourth input available to the multiplexer for
next address control is the 33-deep, 16-bit wide LIFO stack. The
LIFO stack provides return address linkage for subroutines and
loops. The IOT49C41Os contain a built-in stack pOinter that always
points to the last stack location written. This allows for stack.reference operations, usually called loops, to be performed without
popping the stack.
The stack pOinter internal to the IDT49C410s is actually an up/
down counter. During the execution of microinstructions one, four
and five, the PUSH operation may occur dependi~g on the s~ate of
the condition code input. This causes the stack pOinter to be incremented by one and the stack to be written with the required return

8-198

IDT49C410/A 16·BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FIGURE 1. IDT4941 0 FLOW DIAGRAMS

o Jump Zero (JZ)

1 Cond JSB PL (CJS)

2 Jump Map (JMAP)

:~68
3 Cond Jump PL (CJP)

~h25

67

68

41

68

69
70

42
43

65~8

STACK

68

REGISTER!
COUNTER

66
67

26

66

40

4 Push/Cond LD CNTR (PUSH)

69

65~

STACK

67

N

85
86

5 Cond JSB R!PL (JSRP)

STACK

66

66
67 •

20
21

8 Repeat Loop, CNTR 'F- 0 (RFCT)

65

~

66.
67
68

A
67
6 •

35
36

69

6

REGISTER!
COUNTER

N

11 Cond Jump PL & POP (CJPP)

30
31

9 Repeat PL, CNTR '4 0 (RPCT)

STACK
(PUSH)

65
66
67
68

69 •
70

p

10 Cond Return (CRTN)

COUNTER
(LOCT)

.

65

66

67 r.H---1----.. 40

65~

68

41

69
70
71

42

68

68

32
33
34
35
36

COUNTER
13 Test End Loop (LOOP)

15 Three-Way Branch (TWB)

65

66
67

65t

30
31

69
70

12 LD CNTR & Continue (LDCT)

66 •
67

66 •
67
68

66
67

STACK
(PUSH)

65

14 Continue (CONT)

32
33
34

5

65h
68

30
31

7 Cond JUMP R/PL (JRP)

6 Cond Jump Vector (CJV)

65
66
67
68

69

~
67
N

72
73

8-199

STACK
(PUSH)
REGISTER!
COUNTER

68

69
70
71
72

STACK
(PUSH)

IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C410 OPERATION

microprogram counter; the last-in/first-out stack; the register/
counter and the direct inputs.
The following paragraphs will describe each instruction associated with the IDT49C410s. As a part of the discussion, an example
of each instruction is shown in Figure 1. The purpose of the examples is to show microprogram flow. Thus, in each example the microinstruction currently being executed has a circle around it. That
is, this microinstruction is assumed to be the contents of the pipeline register at the output of the microprogram memory. In these
drawings, each of the dots refers to the time that the contents of the
microprogram memory word would be in the pipeline register and
is curr13ntlY being executed.

The IDT49C41Os are CMOS pin-compatible implementations of
the Am2910 and Am2910A microprogram sequencers. The
IOT49C410 sequencers are functionally identical except that they
are 16 bits wide and provide a 33-deep stack to give the
microprogrammer more capability in terms of microprogram subroutines and microprogram loops. The definition of each
microprogram instruction is shown in the table of instructions. This
table shows the results of each instruction in terms of controlling
the multiplexer which determines the Y outputs and in controlling
the signal.§..!hat can be used to enable various branch address
sources. (PL,MAP, VECT). The operation of the register/counter
and the 33-deep stack after the next LOW-to-H IGH transition of the
clock are also shown. The internal multiplexer is used to select
which of the internal sources is used to drive the Y outputs. The actual value loaded into the microprogram counter is either identical
to the Youtput or the Y output value is incremented by 1 and placed
in the microprogram counter. This function is under the control of
the carry input. For each of the microinstruction inputs, only one of
the three outputs (PL, MAP or VECT) will be LOW. Note that this
function is not determined by any of the possible condition code
inputs. These outputs can be used to control the three-state selection of one of the sources for the microprogram branches.
Two inputs, CC and CCEN, can be used to control the conditional instructions. These are fully defined in the table of instructions. The RLO input can be used to load the internal register/
counter at any time. When this input is LOW, the data at the D inputs
will be loaded into this register/counter on the LOW-to-HIGH transition of the clock.Thus, the RLD input overrides the internal hold or
decrement operations specified by the various microinstructions.
The OE input is normally LOW and is used as the three-state enable for the Y outputs. The internal stack in the IDT49C410s is a
last-in/first-out memory that is 16 bits in width and 33 words deep. It
has a stack pointer that addresses the stack and always pOints to
the value currently on the top of the stack. When instruction 0 (RESET) is executed, the stack pointer is initialized to the top of the
stack which is, by definition, the stack empty condition. Thus, the
contents of the top of the stack are undefined until the forced PUSH
occurs. A pop performed while the stack is empty will not change
the stack pointer in any way; however, it will result in unknown data
at the Y outputs.
By definition, the stack is full any time 33 more PUSHes than
pops have occurred since the stack was last empty. When this happens, the FULL flag will go LOW. This Signal first goes LOW on the
microcycle after the 33 pushes occur. When this Signal is LOW, no
additional pushes should be attempted or the information on the
top of the stack will be lost.

INSTRUCTION 0JUMP 0 (JZ)
This instruction is used at power-up time or at any restart sequence when the need is to reset the stack pointer and jump to the
very first address in microprogram memory. The Jump 0 instruction does not change the contents of the register/counter.

INSTRUCTION 1 CONDITIONAL JUMP TO SUBROUTINE (CJS)
The Conditional Jump to Subroutine instruction is the one used
to call microprogram subroutines. The subroutine address will be
contained in the pipeline register and presented at the D inputs. If
the condition code test is passed, a branch is taken to the subroutine. Referring to the flow diagram for the lOT49C41 Os shown in figure 1, we see that the content of the microprogram counter is 68.
This value is pushed onto the stack and the top of the stack pointer
is incremented. If the test is failed, then this conditional Jump to
Subroutine instruction behaves as a simple continue. That is, the
contents of microinstruction address 68 are executed next.

INSTRUCTION 2JUMP MAP (JMAP)
This sequencer instruction can be used to start different
microprogram routines based on the machine instruction opcode.
This is typically accomplished by using a mapping PROM as an
input to the D inputs on the microprogram sequencer. The JMAP
instruction branches to the address appearing on the 0 Inputs. In
the flow diagram shown in Figure 1, we see that the branch actually
will be to the contents of microinstruction 85 and this instruction
will be executed next.

INSTRUCTION 3 CONDITIONAL JUMP PIPELINE (cjP)

THE IDT49C410 INSTRUCTION SET

The simplest branching control available in the IDT49C410
microprogram sequencers is that of Conditional Jump to Address.
In this instruction, the jump address is usually contained in the microinstruction pipeline register and presented to the D inputs. If the
test is passed, the jump is taken. If the test fails, this instruction executes as a simple continue. In the example shown in the flow diagram of Figure 1, we see that, if the test is passed, the next microinstruction to be executed is the contents of address 25. If the
test is failed, the microcode simply continues to the contents of the
next instruction.

This data sheet contains a block diagram of the IDT49C410
microprogram sequencers. As can be seen, the devices are controlled by a 4-bit microinstruction word (13-10). Normally, this word
is supplied from one 4-bit field of the microinstruction word associated with the entire state machine system. These four bits provide
for the selection of one of the sixteen powerful instructions associated with selecting the address of the next microinstruction. Unused Y outputs can be left open; however, the corresponding most
significant D inputs should be tied to ground for smaller
microwords. This is necessary to make sure the internal operation
of the counter is proper should less than 64K of microcode be implemented. As shown in the block diagram, the internal instruction
PLA uses the four instruction inputs, as well as the CC, CCEN and
the internal counter = 0 line for controlling the sequencer. This
internal instruction PLA provides all of the necessary internal control signals to control each particular part of the microprogram
sequencer. The next address at the Y outputs of the IDT49C41Os
can be from one of four sources. These include the internal

INSTRUCTION 4PUSH/CONDITIONAL LOAD COUNTER (PUSH)
With this instruction, the counter can be conditionally loaded
during the same instruction that pushes the current value of the
microprogram counter on to the stack. Under any condition independent of the conditional testing, the microprogram counter is
pushed on to the stack. If the conditional test is passed, the counter
will be loaded with the value on the 0 inputs to the sequencer. Ifthe

8-200

JDT49C410!A 16-BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

test fails, the contents of the counter will not change. The PUSH/
Conditional Load Counter instruction is used in conjunction with
the loop instruction (Instruction 13), the repeat file based on the

counter instruction (Instruction 9) or the 3-way branch instruction
(Instruction 15).

IDT49C410 INSTRUCTION OPERATIONAL SUMMARY
13 -1 0

MNEMONIC

CC

COUNTER
TEST

STACK
CLEAR
PUSH
NC
NC
NC
NC
PUSH
PUSH
PUSH
PUSH
NC
NC
NC
NC
POP
NC
NC
NC
POP
NC
POP
NC
NC
POP
NC
NC
POP
POP
POP
NC

0

JZ

X

X

1

CJS

PASS
FAIL

X
X

2

JMAP

X

3

CJP

4

PUSH

5

JSRP

6

CJV

7

JRP

PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL
PASS
FAIL

X
X
X

8

RFCT

X
X

9

RPCT

X
X

10

CRTN

11

CJpp

12

LDCT

X

X

13

LOOP

PASS
FAIL

X
X

14

CONT

X

X

lWB

PASS
PASS
FAIL
FAIL

=0
NOT = 0
=0
NOT = 0

15

PASS
FAIL
PASS
FAIL

X
X
X
X
X
X
X
X

=0
NOT = 0
=0
NOT = 0
X
X
X
X

ADDRESS
SOURCE
0
0

PC
D
D
PC
PC
PC
D
R
D
PC
D
R
PC
STACK
PC
D
STACK
PC
D
PC
PC
PC
STACK
PC
PC
PC
D
STACK

REGISTER!
COUNTER
NC
NC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
NC
NC
NC
NC
DEC
NC
DEC
NC
NC
NC
NC
LOAD
NC
NC
NC
NC
DEC
NC
DEC

ENABLE
SELECT
PL
PL

PI

MAP
PL

PI
PL

PI
PL

PC
VECT
VECT
PL

PC

PL

PI
f!.
PL
PL

PC
PL

PI
PL

PI
PC
PL
PL

PC

PI
PI

NC = No Change, DEC = Decrement

INSTRUCTION 5CONDITIONAL JUMP TO SUBROUTINE R/PL
(JSRP)

the conditional test is failed, no branch is taken but rather the
microcode simply continues to the next sequential microinstruction. When this instruction is executed, the VECT output is
LOW unconditionally. Thus, an external 16-bit field can be enabled
on to the D inputs of the microprogram sequencer.

Subroutines may be called by a Conditional Jump Subroutine
from the internal register or from the external pipeline register. In
this instruction, the contents of the microprogram counter are
pushed on the stack and the branch address for the subroutine call
will be taken from either the internal register/counter or the external
pipeline register presented to the D inputs. If the conditional test is
passed, the subroutine address will be taken from the pipeline register. If the conditional test fails, the branch address is taken from
the internal register/counter. An example of this is shown in the flow
diagram of Figure 1.

INSTRUCTION 7CONDITIONAL JUMP R/PL (JRP)
The Conditional Jump register/counter or external pipeline register always causes a branch in microcode. This jump will be to one
of two different locations in the microcode address space. If the test
is passed, the jump will be to the address presented on the D inputs
to the microprogram sequencer. If the conditional test fails, the
branch will be to the address contained in the internal
register/counter.

INSTRUCTION 6CONDITIONAL JUMP VECTOR (CJV)

INSTRUCTION 8REPEAT LOOP COUNTER NOT EQUAL TO 0
(RFCT)

The Conditional Jump Vector instruction is similar to the Jump
Map instruction in that it allows a branch operation to a microinstruction, as defined from some external source. This instruction is
similar to the Jump Map instruction except that it is conditional.
The Jump Map instruction is unconditional. If the conditional test is
passed, the branch is taken to the new address on the D inputs. If

This instruction utilizes the loop counter and the stack to implement microprogrammed loops. The start address for the loop
would be initialized by using the PUSH/conditional load counter

8-201

IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

instruction. Then, when the repeat loop instruction is executed, if
the counter is not equal to 0, the next microword address will be
taken from the stack. This will cause a loop to be executed as
shown in the Figure 1 flow diagram. Each time the microcode sequence goes around the loop, the counter is decremented. When
the counter reaches 0, the stack will be popped and the microinstruction address will be taken from the microprogram counter.
This instruction performs a timed wait or allows a single sequence
to be executed to the desired number of times. Remember, the actual number of loops performed is equal to the value in the counter
plus 1.

INSTRUCTION 13TEST END OF LOOP (LOOP)
The Test End of Loop instruction is used as a last instruction in a
loop associated with the stack. During this instruction, if the conditional test input is failed, the loop branch address will be that on the
stack. Since we may go around the loop a number if times, the
stack is not popped. If the conditional test input is passed, the loop
is terminated and the stack is popped. Notice that the loop instruction requires a PUSH to be performed at the instruction immediately prior to the loop return address. This is necessary in order to
have the correct address on the stack before the loop operation.
Forthis reason, the stack pointer always points to the last thing written on the stack.

INSTRUCTION 9REPEAT PIPELINE, COUNTER NOT EQUAL TO 0
(RPCT)

INSTRUCTION 14CONTINUE (CONT)

This instruction is another technique for implementing a loop
using the counter. Here, the branch address for the loop is contained in the pipeline register. This instruction does not use the
stack in any way as a part of its implementation. As long as the
counter is not equal to 0, the next microword address will be taken
from the 0 inputs of the microprogram sequencer. When the
counter reaches 0, the internal multiplexer will select the address
source from the microprogram counter, thus causing the
microcode to continue on and leave the loop.

The Continue instruction is a si mple instruction whereby the address for the microinstruction is taken from the microprogram
counter. This Instruction simply causes sequential program flow to
the next microinstruction in microcode memory.

INSTRUCTION 15THREE WAY BRANCH (TWB)
The Three Way Branch instruction is used for looping while waiting for a conditional event to come true. If the event does not come
true after some number of microinstructions, a branch is taken to
another microprogram sequence. This is depicted in Figure 1
showing the IDT49C410 flow diagrams and is also described in full
detail in the IOT49C410s' instruction operational summary. Operation of the instruction is such that, any time the external conditional
test input is passed, the next microinstruction will be that associated with the program counter and the loop will be left; the stack is
also popped. Thus, the external test input overrides the other possibilities. Should the external conditional test input not be true, then
the rest of the operation is controlled by the internal counter. If the
counter is not equal to 0, the loop is taken by selecting the address
on the top of the stack as the address out of the Y outputs of the
IOT49C410s. In addition, the counter is decremented. Should the
external conditional test input be failed and the counter also have
counted to 0, then this instruction "times out". The result is that the
stack is popped and a branch is taken to the address presented to
the D inputs of the lOT49C41 microprogram sequencers. This address is usually provided by the external pipeline register.

INSTRUCTION 10CONDITIONAL RETURN (CRTN)
The Conditional Return instruction is used for terminating subroutines. The fact that it is conditional allows the subroutine either
to be ended or continue. If the conditional test is passed, the address of the next microinstruction will be taken from the stack and it
will be popped. If the conditional test fails, the next microinstruction address will come from the internal microprogram
counter. This is depicted in the flow diagram of Figure 1.1t is important to remember that every subroutine call must somewhere be
followed by a return from subroutine call in order to have an equal
number of pushes and pops on the stack.

INSTRUCTION 11 CONDITIONAL JUM,p PIPELINE AND POP (CJPP)
The Conditional Jump 'Pipeline and Pop instruction is a technique for exiting a loop from within the middle of the loop. This is
depicted fully in the flow diagrams for the lOT49C41 Os as shown in
Figure 1. The conditional test input for this instruction results in a
branch being taken if the test is passed. The address selected will
be that on the 0 inputs to the microprogram sequencer and since
the loop in being terminated, the stack will be popped. Should the
test be failed on the conditional test inputs, the microprogram will
simply continue to the next address as taken from the
microprogram counter. The stack will not be affected if the conditional test input is failed.

°

CONDITIONAL TEST
Throughout this discussion we have talked about microcode
passing the conditional test. There are actually two inputs associated with the conditional test input. These include the CCEN and
the CC inputs. The CCEN input is a condition code enable. Whenever the CCEN input is HiGH, the CC input is ignored and the device operates as though the CC input were true (LOW). Thus, a fail
of the external test condition can be defined as CCEN equals LOW
and CC equals HIGH. A pass condition is defined as a CCEN
equal to HIGH or a CC equal to LOW. It is important to recognize
the full function of the condition code enable and the condition
code inputs in order to understand when the test is passed or
failed.

INSTRUCTION 12LOAD COUNTER AND CONTINUE (LDCT)
The Load Counter and Continue instruction is used to place a
value of the 0 inputs in the register/counter and continue to the next
microinstruction.

8-202

IDT49C410/A 16·BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

-0.5 to +7.0

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

SYMBOL
CIN

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to + 125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

1.0

1.0

W

lOUT

DC Output Current

30

30

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance

CONDITIONS
VIN = OV

COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.

TYP.

UNIT

5

pF

7

pF

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 5% (Commercial)
Vcc = 5.0V ± 10% (Military)

TA = O°C to + 70°C
TA = -55°C to + 125°C
VLC = 0.2V
VHC = Vec - 0.2V
SYMBOL

TEST CONDITIONS (1)

PARAMETER

VIH

Output HIGH Level

Guaranteed Logic High Level

VIL

Output LOW Level

Guaranteed Logic Low Level

IlL

Input HIGH Current

IlL

Input LOW Current

VOH

VOL

loz

Output HIGH Voltage

Output LOW Voltage

Off State (High Impedance)
Output Current

(4)

MIN.

TYP.(2)

MAX.

2.0

-

-

V

0.8

V

UNIT

Vcc = Max., \'IN = Vec

-

0.1

5

~A

Vec = Max., \'IN = GND

-

-0.1

-5

~A

10H = -300~A

VHC

VHC

10H = -12mA MIL.

2.4

4.3

V

10H = -15mA COM'L.

2.4

4.3

-

10L = 300~A

-

GND

VLc

10L = 20m A MIL.

-

0.3

0.5

10L = 24mA COM'L.

-

0.3

0.5

Vo =0

-

-0.1

-10

Vo = Vcc (Max.)

-

0.1

10

-

-

Vcc= Min.
\'IN = VIH or~L

Vcc = Min.
\'IN = VIH or~L

(4)

Vcc= Max.

-30
Output Short Circuit Current
Vcc = Min., VOUT = OV (3)
los
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at a time. Duration of the short Circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise·free environment.

8-203

V

~A

mA

IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = O°C to + 70°C
Vcc = 5.0V ± 5% (Commercial)
TA = -55°C to + 125°C
Vcc = 5.0V ± 10% (Military)
VLC = 0.2V
VHC = Vec - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

(1)

TYP.(2) MAX.

UNIT

Quiescent Power Supply Current
CP = H (CMOS Inputs)

Vcc = Max.
VHC :5 V1H • "IL :5 VLC
fc = 0, CP = H

-

35

50

mA

ICCOL

Quiescent Power Supply Current
CP = L (CMOS Inputs)

Vcc = Max.
VHC :5 V1H ' "IL :5 VLC
fcp = 0, CP = L

-

35

50

mA

ICCT

Quiescent Input Power Supply
Current (per Input @ TTL High)(5)

Vcc

-

0.3

0.5

mAl
Input

ICCD

Dynamic Power Supply Current

Vcc = Max.
VHC :5 V1H , V1L :s; \tc
Outputs Open, DE = L

-

1.0

3.0

1.0

1.5

45

80

ICCOH

Icc

= Max., "IN = 3.4V, fcp = 0
MIL.
COM'L.

Vcc = Max., fcF' = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VHC :5 \1H , V1L :5 VLC
Vcc = Max., fcF' = 10MHz
Outputs Open, OE = L
CP = 50% Duty cycle
VHC :5 V1H , \1L :5 VLC

Total Power Supply Current(6)

MIL.
COM'L.

-

45

65

MIL.

-

50

90

COM'L.

-

50

75

mAl
MHz

mA

NOTES:
5. ICCOT is derived by measuring the total current with all the inputs tied together at 3.4V, subtracting out IccOH, then dividing by the total number of inputs.
6. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS orTTL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = ICCOH (CD H)

+

IccoL

(1 - CDH)

+

ICCT (NT

X

DH)

+

ICCD (fcp)

. CDH = Clock duty cycle high period
DH = Data duty cycle TTL high period (\,'IN = 3.4V)
NT = Number of dynamic inputs driven at TTL levels
fcp = Clock Input Frequency

CiviOS TESTiNG CONSiDERATiONS

3) Definition of input levels is very important. Since many inputs
may change coincidentally, significant noise at the device pins
may cause the VIL and VIH levels not to be met until the noise has
settled. To allow for this testing/board induced noise. lOT recommends using VIL :5 OV and VIH ;::: 3V for AC tests.

There are certain testing considerations which must be taken
into account when testing high-speed CMOS devices in an automatic environment. These are:
1) Proper decoupling at the test head is necessary, Placement of
the capacitor set and the value of capacitors used is critical in
reducing the potential erroneous failures resulting from large
Vcc current changes, Capacitor lead length must be short and
as close to the DUT power pins as possible,

4) Device grounding is extremely important for proper device testing. The use of multi-layer performance boards with radial
decoupling between power and ground planes is required. The
ground plane must be sustained from the performance board to
the OUT interface board. All unused interconnect pins must be
properly connected to the ground pin. Heavy gauge stranded
wire should be used for power wiring and twisted pairs are recommended to minimize inductance.

2) All input pins should be connected to a voltage potential during
testing, If left floating, the device may begin to oscillate causing
improper device operation and possible latch up.

8-204

IDT49C410/A 16-BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C410A
AC ELECTRICAL CHARACTERISTICS
I. SET-UP AND HOLD TIMES
t(h)

tIS)

INPUTS

IDT49C410
AC ELECTRICAL CHARACTERISTICS
1. SET-UP AND HOLD TIMES

MIL.

COM'L.

MIL.

6

7

0

0

ns

DI-+R

t(h)

tIS)

INPUTS

UNIT

COM'L.

UNIT

COM'L.

MIL.

COM'L.

MIL.

DI-+R

16

16

0

0

ns

DI-+PC

30

30

0

0

ns

35

38

0

0

ns

13

15

0

0

ns

23

25

0

0

ns

CC

15

18

0

0

ns

CC

24

35

0

0

ns

CCEN

15

18

0

0

ns

CCEN

24

35

0

0

ns

CI

6

7

0

0

ns

CI

18

18

0

0

ns

RLD

11

12

0

0

ns

RLD

19

20

0

0

ns

DI-+PC
' 0- 3

0 3
' -

II. COMBINATIONAL DELAYS
INPUTS

Y
COM'L.

II. COMBINATIONAL DELAYS

PL, VECT, MAP
MIL.

COM'L.

MIL.

FULL
COM'L.

MIL.

UNIT

12

15

-

-

-

20

25

13

15

-

-

ns

CC

16

20

-

-

-

ns

CCEN

16

20

-

-

-

-

CP

28

33

-

-

22

10/10

13/13

-

-

-

DO-11
' 0- 3

OE (1)

INPUTS

PL, VECT, MAP

Y
COM'L.

MIL.

COM'L.

FULL
MIL.

UNIT

MIL.

COM'L.

-

ns

-

ns

20

25

-

-

35

40

30

35

CC

30

36

ns

CCEN

30

36

-

-

-

25

ns

40

46

-

-

31

35

ns

-

ns

CP
OE (1)

25/27

25/30

-

-

-

-

ns

ns

DO-11
0 3
' -

ns
ns

NOTE:
1. Enable/Disable. Disable times measure to 0.5V change on output voltage level with C L = 5pF.

NOTE:
1. Enable/Disable. Disable times measure to 0.5V change on output voltage level with C L = 5pF.

III. CLOCK REQUIREMENTS

III. CLOCK REQUIREMENTS

COM'L.

MIL.

UNIT

COM'L.

MIL.

UNIT

Minimum Clock LOW Time

18

20

ns

Minimum Clock LOW Time

20

25

ns

Minimum Clock HIGH Time

17

20

ns

Minimum Clock HIGH Time

20

25

ns

Minimum Clock Period

35

40

ns

Minimum Clock Period

50

51

ns

SWITCHING WAVEFORMS
INPUTS 3.0V
O V - - - -......~
CLOCK 3.0V
OV
CLOCK

TO

OUTPUT
DELAY
OUTPUTS

8-205

I~_ _ _ _-I~

IDT49C410/A 16·BIT CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT49C410 INPUT/OUTPUT
INTERFACE CIRCUITRY

Vee

ESD
PROTECTION

OUTPUTS

INPUTS

Figure 2. Output Structure

Figure 1. Input Structure

TEST LOAD CIRCUIT
TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All other Outputs

Open

DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to ZOUT of the
Pulse Generator

Figure 3. Switching Test Circuits

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V

WIns
1.5V
1.5V
See Figure 3

8-206

IDT49C410/A 16-81T CMOS
MICROPROGRAM SEQUENCER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

49C410
Device Type

x
Process!
Temperature
Range

y:'Mk

P
XC
'--_ _ _ _ _ _ _ _ _ _-1 C
J
L
F

' - - - - - - - - - - - - - - - - - - - 1 Blank
A

8-207

Commercial (DOC to

+70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STO-883, Class B
Plastic DIP
Sidebraze SHRINK-DIP
Sidebraze DIP
PLCC
LCC
Flatpack
16-Bit Microprogram Sequencer
Fast 16-Bit Microprogram Sequencer

FEATURES:

- Easy access to internal stacks and registers

• Interrupt priority handler
- Handles up to 8 interrupts
- Throughput of one interrupt/cycle
- Maximum latency of 2 cycles

- Incorporates address break point detect
• Military product compliant to MIL-STD-883, Class B

DESCRIPTION:
The IDT49C411 is a 20-bit high-performance CMOS interruptable microprogram sequencer. This flexible, yet fast sequencer is
used for controlling the sequence of execution of microinstructions
stored in the microprogram memory. It has been optimized for use
in microprogram designs of very high-speed dedicated applications such as graphics, disk controllers, communications and DSP
engines.
Its three bus architecture provides direct address access of up
to 1 megaword of microprogram memory. The IDT49C411 includes such powerful features as a 20-bit counter/register, multiway branching, flexible condition code testing via an internal multiplexer and three independent 64-deep stacks. All three stacks enable the user to perform fast context switches every clock cycle
with a maximum throughput latency of two clock cycles.
The IDT49C411 incorporates Serial Protocol Channel (SPC), an
on-chip diagnostics feature which allows access to the internal
stacks and registers. Also included is the provision for breakpoint
detection. SPC simply and easily provides for system board and
system level design verification, manufacturing test and field main.
tenance support.
The IDT 49C411 is fabricated using CEMOS TM , IDT's advanced
CMOS technology designed for high-performance and highreliability.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.

• 20-bit wide address path
- Addresses up to 1Mbyte words of microprogram memory
• Two Input address buses (D, A)
- Bidirectional D bus provides access to internal stacks and
ALU data path
- Bus A provides convenient input from pipelined register
• 20-bit loop counter
- Presettable down counter for counting loop interations and
repeating instructions
- Nested looping using loop stack
• Three independent 64-deep stacks
- Allow for nested subroutines, interrupts and loop counters
- Fast interrupt context switch on every clock cycle
• Multiple condition code inputs
- Eliminates external condition code multiplexer
- Includes ALU status flag inputs
- Provides test and branch on <, > , =, etc.
• Multiway branch inputs
- Allows for parallel test and branch on multiple inputs
• Incorporates Serial Protocol Channel (SPC ™)
- On-chip diagnostics

FUNCTIONAL BLOCK DIAGRAM
D

A

Trn
IRQ
C,N,V,Z
CCO-7
CCSEL

MW

20

CONDITIONAL
TEST &
BRANCH

MULTIWAY
TEST &
BRANCH

20

INST

INSTRUCTION DECODE
COUNTER

PC-1

PC

COUNTER
STACK

INTERRUPT
RETURN
STACK

SUBROUTINE
RETURN
STACK

CIN

MUX

SDI

C/f5
SCLK

SDO

Y

CEMOS and SPC are registered trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Inlegrated DevIce Technology, Inc.

DECEMBER 1987
DSC-9015/-

8-208

MICROSLICE ™ PRODUCT

FEATURES:

DESCRIPTION:

• Low power CEMOS ™
- Military: 100mA (max.)
- Commercial: 85mA (max.)

The IDT39C60 family are high-speed, low-power, 16-bit Error Detection and Correction Units which generate check bits on a 16-bit
data field according to a modified Hamming Code and correct the
data word when check bits are supplied. When performing a read
operation from memory, the IDT39C60s will correct 100% of all
single bit errors, will detect all double bit errors and some triple bit
errors.
The IDT39C60s are easily cascadable from 16 bits up to 64 bits.
Sixteen-bit systems use 6 check bits, 32-bit systems use 7 check
bits and 64-bit systems use 8 check bits. For all three configurations,
the error syndrome is made available.
All incorporate 2 built-in diagnostic modes. Both simplify testing
by allowing for diagnostic data to be entered into the device and to
execute system diagnostic functions.
The IDT39C60s are pin-compatible, performance-enhanced
functional replacements for all versions of the 2960. They are fabricated using CEMOS, a CMOS technology designed for highperformance and high-reliability. The devices are packaged in
either 48-pin DIPs, or 48-pin LCC and 52-pin PLCC and LCCs.
Military grade product is manufactured in compliance to the
latest revision of MIL-STD-883, Class B.

• Fast
- Data in to error detect
IDT39C60A: 20ns (max.), IDT39C60-1: 25ns (max.)
IDT39C60: 32ns (max.)
- Data in to corrected data out
IDT39C60A: 30ns (max.), IDT39C60-1: 52ns (max.)
IDT39C60: 65ns (max.)
• Improves system memory reliability
- Corrects all single-bit errors, detects all double and some
triple-bit errors
• Cascadable
- Data words up to 64 bits
• Built-in diagnostics
- Capable of verifying proper EDC operation via software
control
• Simplified byte operations
- Fast byte writes possible with separate byte enables
• Available in 48-pin DIP, 52-pin PLCC and LCC, as well as spaceefficient 48-pin Shrink-DIP (70 mil pin centers) and 48-pin LCC
• Pin-compatible to all versions of the 2960
• Military product available compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
LEoUT
OE BYTE 0
CSa-B
DATAa_7
DATA 8-15
OE BYTE 1
SCa-B

DIAG

~t~~=r=:::::!---'

LE ID r
CODE
DIAG MODE 1"')-~:""-'-+01
CONTROL
PASSTHRU .:=)----+01
LOGIC
GENERATE 1"')----+01
CORRECT D~--+L_ _ _ _...J

CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-901B/-

8-209

IDT39C60/-1/A 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT .

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION
CORRECT
DATA15
DATA14
DATA13
DATA12
LEIN
LEolAG
OE"BYTE 1
DATA 11
DATA 10
DATA 9
DATA 6
GND
DATA 7
DATA 6
DATA 5
DATA 4
OE"BYTEO
LEoUT
DATA 3
DATA 2
DATAl
DATA 0
SC 1

PASS THRU .
DIAG MODEl
DIAG MODEa
CODE ID2
CODE IDl
CODE 100
GENERATE
CB6
CBo
CB5
CB4
CB3
Vee
CB 2
CBl
MOLT ERROR

rnROR
OE"se

Sec

SCs
SC3
SC2
SC4

INDEX
ULJLJUU;;UULJ LJLJLJ

6 5 4 3

LE 01AG
DE" BYTE 1
DATA 11
DATA 10
DATA 9
DATA 6
GND
DATA 7
DATA 6
DATAs
DATA 4
DE" BYTEo

2

U

46 47 46 45 44 43

]7
]6
]9

]
]
]
]
]
]
]
]
]

10
11
12
13
14
15
16
17
16

l48-1

19 20 21 22 23 24 2S 26 27 26 29 30

nnnnnnnnnnnn

Sea

DIP
TOP VIEW
(600 mil x 100 mil CENTERS)
(400 mil x 70 mil CENTERS)
LCC
TOP VIEW
(560 mil x 650 mil)

INDEX
ULJUUULJli LJUU

LE 01AG

:J 6

DE" BYTE 1 :J 9
DATA 11
DATA 10
DATA 9
DATA 6
GND
DATA 7
DATA 6
DATA 5
DATA 4
OE" BYTE 0

:J 10
]11
:1 12
:J 13
] 14
:J lS
:J 16

~

~

~

7 6 S 4 3 ~ 525150 49 46 47
PIN 1
INDICATOR
FOR PLCC

J52-1
&
L52-1

:J 17

:116
:J 19
NC :1 20
21 22 23 24 25 26 27 26 29 30 31 32 33

nnnnnnnnnnnnn

PLCC/LCC
TOP VIEW
(750 mil x 750 mil)

8-210

46
4S
44
43
42
41
40
39
36
37
36
3S
34

[:

£:
£:
£:
£:
£:
£:
£:
£:
£:
[:

£:
£:

NC
GENERATE
CB6
CBo
CBs
CB4
CB3
Vee
CB 2
CBl
MuLT ERROR
ERROR
OEse

42
41
40
39
36
37
36
3S
34
33
32
31

[
[
[
[
[
[
[
[
[
[
[
[

GENERATE
CB 6
CBo
CBs
CB4
CB3
Vee
CB 2
CBl
MuLT ERROR

EffiOR
OE"se

IDT39C60/-l/A l6-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS
PIN NAME
DATA o_15

I/O

DESCRIPTION

I/O

16 bidirectional data lines. They provide input to the Data Input Latch and receive output from the Data Output Latch. DATAo is
the least significant bit; DATA 15 the most significant.

CB O-6

I

Seven check bit input lines. The check bitlines are used to input check bits for error detection. Also used to input syndrome bits
for error correction in 32- and 64-bit configurations.

LEIN

I

Latch Enable-Data Input Latch. Controls latching of the input data. When HIGH, the Data Input Latch and Check Bit Input
Latch follow the input data and input check bits. When LOW, the Data Input Latch and Check Bit Input Latch are latched to their
previous state.

GENERATE

I

Generate Check Bits input. When this input is LOW, the EDC is in the Check Bit Generate mode. When HIGH, the EDC is in the
Detect mode or Correct mode. In the Generate mode, the circuit generates the check bits or partial check bits specific to the
data in the Data Input Latch. The generated check bits are placed on the SC outputs. In the Detect or Correct modes the EDC
detects single and mUltiple errors and generates syndrome bits based upon the contents of the Data Input Latch and Check Bit
Input Latch. In Correct mode, single-bit errors are also automatically corrected - corrected data is placed at the inputs of the
Data Output Latch. The syndrome result is placed on the SC outputs and indicates, in a coded form, the number of errors and
the bit-in-error.

SCO-6

0

Syndrome/Check Bit outputs. These seven lines hold the check/partial check bits when the EDC is in Generate mode and will
hold the syndrome/partial syndrome bits when the device is in Detect or Correct modes. These are 3-state outputs.

OJ:sc

I

Output Enable -Syndrome/Check Bits. When LOW, the 3-state output lines SC O- 6 are enabled. When HIGH, the SC outputs
are in the high impedance state.

rnROR

0

Error Detected output. When the EDC is in Detect or Correct mode, this output will go LOW if one or more syndrome bits are
asserted, meaning there are one or more bit errors in the data or check bits. If no syndrome bits are asserted, there are no errors
detected and the output will be HIGH. In Generate mode, ERROR is forced HIGH. (In a 64-bitconfiguration, ERROR must be
implemented externally.)

MOLT ERROR

0

Multiple Errors Detected output. When the EDC is in Detect orCorrect mode this output, if LOW, indicates thatthere are two or
more bit errors that have been detected. If HIGH, this indicates that either one or no errors have been detected. In Generate
mode, MOLT ERROR is forced HIGH. (In a 64-bit configuration, MUL T ERROR must be implemented externally.)

CORRECT

I

Correct input. When HIGH, this signal allows the correction network to correct any single-bit error in the Data Input Latch (by
complementing the bit-in-error) before putting it into the Data Output Latch. When LOW, the EDC will drive data directly from
the Data Input Latch to the Data Output Latch without correction.

LEoUT

I

Latch Enable - Data Output Latch. Controls the latching ofthe Data Output Latch. When LOW, the Data Output Latch is latched
to its previous state. When HIGH, the Data Output Latch follows the outputofthe Data Input Latch as modified by the correction
logic network. In Correct mode, single-bit errors are corrected by the network before loading into the Data Output Latch. In
Detect mode, the contents of the Data Input Latch are passed through the correction network unchanged into the Data Output
Latch. The inputs to the Data Output Latch are disabled with its contents unchanged if the EDC is in Generate mode.

OJ: BYTEo
OJ: BYTE 1

I

Output Enable - Bytes 0 and 1, Data Output Latch. These lines control the 3-state outputs for each of the two bytes of the Data
Output Latch. When LOW, these lines enable the Data Output Latch and, when HIGH, these lines force the Data Output Latch
into the high impedance state. The two enable lines can be separately activated to enable only one byte of the Data Output Latch
at a time.

PASSTHRU

I

Pass Thru input. This line, when HIGH, forces the contents of the Check Bit Input Latch onto the Syndrome/Check Bit outputs
(SCO-6) and the unmodified contents of the Data Input Latch onto the inputs of the Data Output Latch.

DIAG MOD EO-l

I

Diagnostic Mode Select. These two lines control the initialization and diagnostic operation of the EDC.

CODE IDo-2

I

Code Identification inputs. These three bits identify the size of the total data word to be processed and which 16-bit slice of
larger data words a particular EDC is processing. The three allowable data word sizes are 16, 32, and 64 bits and their respective
modified Hamming codes are designated 16/22,32/39 and 64/72. Special CODE ID inputOOl (lD 2 ,ID 1 , IDo) is also used to
instructthe EDC thatthe signals CODE IDo-2' DIAG MODEo-l, CORRECT and PASSTHRU are to betaken from the diagnostic
latch rather than the control lines.

LE DIAG

I

Latch Enable - Diagnostic Latch. The Diagnostic Latch follows the 16-bit data on the input lines when HIGH. When LOW, the
outputs of the Diagnostic Latch are latched to their previous states. The DiagnostiC Latch holds diagnostic check bits and internal control signals for CODE 100-2, DIAG MODEo-l, CORRECT and PASSTHRU.

8-211

IDT39C60/-1/A 16-81T CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PRODUCT DESCRIPTION

DETAILED PRODUCT DESCRIPTION

The IDT39C60 EDC Unit is a powerful 16-bit cascadable slice
used for check bit generation, error detection, error correction and
diagnostics. As shown In the Functional Block Diagram, the device
consists of the following:

The IDT39C60 EDC Unit contains the logic necessary to generate check bits on a 16-bit data input according to a modified Hamming code. The EDC can compare internally generated check bits
against those read with the 16-bit data to allow correction of any
single bit data error and detection of all double and some triple bit
errors. The IDT39C60 can be used for 16-bit data words (6 check
bits), 32-bit data words (7 check bits) or 64-bit data words (8 check
bits).

-

Data Input Latch
Data Output Latch
Diagnostic Latch
Check Bit Input Latch
Check Bit Generation Logic
Syndrome Generation Logic
Error Detection Logic
Error Correction Logic
Control Logic

CODE AND BYTE SELECTION

DATA INPUT/OUTPUT/DIAGNOSTIC LATCHES
The LEIN, Latch Enable input, controls the Data Input Latch which
can load 16 bits of data from the bidirectional DATA lines. The
input data is used for either check bit generation or error detection/
correction.
The 16 bits of data from the DATA lines can be loaded into the
Diagnostic Latch under control of the Diagnostic Latch Enable,
LEDIAG, giving check bit information in one byte and control information in the other byte. The Diagnostic Latch is used when in Internal
Control mode or in one of the Diagnostic modes.
The Data Output Latch is split into 2 bytes and enabled onto the
DATA lines through separate byte control lines. The Data Output
Latch stores the result of an error correction operation or is loaded
directly from the Data Input Latch under control of the Latch Enable
Out (LEoUT). The PASSTHRU control input determines which data is
loaded.

The 3 code identification pins, 102-0, are used to determine the
data word size from 16, 32 or 64 bits and the byte position of each
16-bit IDT39C60 EDC device.
Code 16/22 refers to a 16-bit data field with 6 check bits.
Code 32/39 refers to a 32-bit data field with 7 check bits.
Code 64/72 refers to a 64-bit data field with 8 check bits.
The ID2-0 of 001 is used to place the device in the Internal Control
mode as described later in this section.
Table 1 defines all possible identification codes.

CHECK AND SYNDROME BITS
The IDT39C60 provides either check bits or syndrome bits on the
three-state output pins SCo-e. Check bits are generated from a
combination of the Data Input bits, while syndrome bits are an Exclusive-OR of the check bits generated from read data with the read
check bits stored with the data. Syndrome bits can be decoded to
determine the single bit in error or that a double error was detected.
Some triple bit errors are also detected. The check bits are labeled:
CX, CO, C1, C2, C4
for the 8-bit configuration
CX, CO, C1, C2, C4, C8
for the 16-bit configuration
CX, CO, C1, C2, C4, C8, C16
for the 32-bit configuration
CX, CO, C1, C2, C4, C8, C16, C32 for the 64-bit configuration
Syndrome bits are similarly labeled SX through S32.

CHECK BIT GENERATION LOGIC
This block of combinational logic generates 7 check bits using a
modified Hamming code from the 16 bits of data input from the Data
Input Latch.

SYNDROME GENERATION LOGIC
This logic compares the check bits generated through the Check
Bit Generator with either the check bits in the Check Bit Input Latch
or 7 bits assigned in the Diagnostic Latch.
Syndrome bits are produced by an exclusive-OR of the two sets
of bits. A match indicates no errors. If errors occur, the syndrome
bits can be decoded to indicate the bit in error, whether 2 errors were
detected or 3 or more errors.

ERROR DETECTION/CORRECTION LOGIC
The syndrome bits generated by the Syndrome Logic are decoded and used to control the ERROR and MULT ERROR outputs.
If one or more errors are detected, ERROR goes low. If two or more
errors are detected, both ERROR and MULT ERROR go low. Both
outputs remain high when there are no errors detected.
For single bit errors, the correction logic will complement (correct) the bit in error, which can then be loaded into the Data Out
Latches under the LEoUT control. If check bit errors need to be corrected, then the device must be operated in the Generate mode.

CONTROL LOGIC
The control logic determines the specific mode of operation, usually from external control Signals. However, the Internal Control
mode allows these Signals to be provided from the Diagnostic
Latch.

CONTROL MODE SELECTION
Tables 2 and 3 describe the 9 operating modes of the IDT39C60.
The Diagnostic mode pins, DIAG MODE1-0, define 4 basic areas of
operation, with GENERATE, CORRECT and PASSTHRU, further
dividing operation into 8 functions with the ID2-0 defining the ninth
mode as the Internal mode.
Generate mode is used to display the check bits on the outputs
SCo-e. The Diagnostic Generate mode displays check bits as stored
in the Diagnostic Latch.
Detect mode provides an indication of errors or multiple errors on
the outputs ERROR and MULT ERROR. Single bit errors are not
corrected in this mode. The syndrome bits are provided on the outputs SCo-e. For the Diagnostic Detect mode, the syndrome bits are
generated by comparing the internally generated check bits from
the Data In Latch with check bits stored in the diagnostic latch rather
than with the check bit latch contents.
Correct mode is similar to the Detect mode except that single bit
errors will be complemented (corrected) and made available as input to the Data Out Latch. Again, the Diagnostic Correct mode will
correct Single bit errors as determined by syndrome bits generated
from the Data Input and contents of the Diagnostic Latch.
The Initialize mode provides check bits for all zero bit data. Data
In Latch is set and latched to a logiC zero and made available as
input to the Data Out Latch.
The Internal mode disables the external control pins DIAG
MODE1-0, CORRECT, PASSTHRU and CODE 10 to be defined by
the Diagnostic Latch. When in the internal mode, the diagnostic
latch should have the CODE ID different from 001 as this would
represent an invalid operation.

8-212

IDT39C60/-1/A 16-81T CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 1.
HAMMING CODE AND SLICE IDENTIFICATION
CODE
102

CODE
101

CODE
100

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

TABLE 2.
DIAGNOSTIC MODE CONTROL

HAMMING CODE
AND SLICE SELECTED
Code 16/22
Internal Control Mode
Code 32/39, Bytes 0 and
Code 32/39, Bytes 2 and
Code 64172, Bytes 0 and
Code 64172, Bytes 2 and
Code 64172, Bytes 4 and
Code 64172, Bytes 6 and

1
3
1
3

DIAG
MODE1

DIAG
MODEo

0

0

Non-diagnostic mode. The EDC functions
normally in all modes.

0

1

Diagnostic Generate. The contents of the
Diagnostic Latch are substituted for the
normally generated check bits when in the
Generate mode. The EDC functions normally in
the Detect or Correct modes.

0

Diagnostic Detect/Correct In the Detect or
Correct mode, the contents of the Diagnostic
Latch are substituted for the check bits normally
read from the Check Bit Input Latch. The EDC
functions normally in the Generate mode.

1

Initialize. The outputs of the Data Input Latch
are forced to zerces and the check bits generated correspond to the all zero data. The latch is
not reset, a functional difference from the
Am2960.

5
7

1

1

DIAGNOSTIC MODE SELECTED

TABLE 3.
IDT39C60 OPERATING MODES
OPERATING
MODE

DM1

PASSDMO GENERATE CORRECT THRU

Generate

0
1

0
0

Detect

0
0

0
1

1

0

0

Correct

0
0

0
1

1

1

PASSTHRU

0
0
1

0
1
0

X

Diagnostic Generate

0

1

0

0

X

DATA OUT LATCH
(LEour= HIGH)

SCO-6
(OEsc = LOW)

-

Check Bits Generated from Data
In Latch

0

ERROR
MULT ERROR

-

Data In Latch

Syndrome Bits Data In/Check
Bit Latch

Error Dep(1)

0

Data In Latch with
Single Bit Correction

Syndrome Bits Data In/Check
Bit Latch

Error Dep

X

1

Data In Latch

Check Bit Latch

X

0

-

High

Check Bits from Diagnostic Latch

Error Dep

Diagnostic Detect

1

0

1

0

0

Data In Latch

Syndrome Bits Data In/Diagnostic
Latch

Diagnostic Correct

1

0

1

1

0

Data In Latch with
Single Bit Correction

Syndrome Bits Data In/Diagnostic
Latch

Error Dep

X

Data In Latch
Set to 0000

Check Bits Generated from Data
In Latch (0000)

-

Initialization Mode
Internal Mode

1

1

X

X

ID2-0 = 001 Control Signals ID2-0, DIAG MODE1-0, CORRECT and PASSTHRU
are taken from the Diagnostic Latch

NOTE:
1. ERROR DEP (Error Dependent): ERROR will be low for single or multiple errors, with MUL TERROR low for double or multiple errors. Both signals are high
for no errors.

8-213

IDT39C60/-1/A 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

16-BIT DATA WO'AD CONFIGURATION

A single IDT39C60 EDC Unit, connected as shown in Figure 2,
provides all logic needed for single bit error correction and double
bit error detection of a 16·bit data field. The identification code 16/22
indicated 6 check bits are required. The CBe pin is, therefore, a
"Don't Care" and ID2, IDl, IDo = 000.

Figure 1 Indicates the 22·bit data format for two bytes of data and
6 check bits.

DATA

15

CHECK BITS

I BYTEo

BYTE1

8 7

CX

CO

I I I I
C1

C2

C4

C8

0

USES MODIFIED HAMMING CODE: 16/22
16 DATA BITS WITH 6 CHECK BITS
Figure 1. 16·Bit Data Format

INPUT CHECK BITS
FOR 16-BIT CONFIGURATION

~~----------~--------D-O-N-'l'
DATA o_15

CX

CO

C1

C2

C4

C8 CARE

DATA 0-15
~

IDT39C60 EDC

000

CODE ID

MUCT
ERROJ1

------------~~----------SYNDROME/CHECK BIT OUTPUTS
Figure 2. 16·Bit Configuration

Table 3 describes the operating modes available. The output pin
is forced high for either syndrome or check bits since only
6 check bits are used for the 16/22 code.

Table 4 indicates the data bits participating in the check bit generation. For example, check bit CO is the Exclusive-OR function or
the 8 data input bits marked with an X. Check bits are generated and
output in the Generate and Initialization mode. Check bits are
passed as stored in the PASSTHRU or Diagnostic Generate mode.

see,

TABLE 4. 16-BIT MODIFIED HAMMING CODE-CHECK BIT ENCODE CHART (1)
GENERATED
CHECK BITS

PARITY

CX

Even (XOR)

PARTICIPATING DATA BITS
0

CO

Even (XOR)

X

C1

Odd (XNOR)

X

C2

Odd (XNOR)

X

C4

Even (XOR)

C8

Even (XOR)

1

2

3

X

X

X

X

X

4

5

X

X

7

X

X

X

8

9

X

X

X

X

X

X
X

6

X

X

X

X

X

X

X

11

X

12

13

X
X

X

X

10

15

X
X

X

X

14

X

X
X

X

X

X

X

X

X

X

X

X

NOTE:
1. The check bit is generated as either an XOR or XNOR of the eight data bits noted by an ·X" in the table.

Syndrome bits are generated by an Exclusive-OR of the generated check bits with the read check bits. For example, SX is the XOR
of check bits CX from those read with those generated. Table 5
indicates the decoding of the six syndrome bits to indicate the bit in
error for a single bit error or whether a double or triple bit error was
detected. The all zero case indicates no errors detected.
In the Correct mode, the syndrome bits are used to complement
(correct) single bit errors in the data bits. For double or multiple error

detection, the data available as input to the Data Out Latch is not
defined.
Table 6 defines the bit definition for the Diagnostic Latch. As de·
fined in Table 3, several modes will use the Diagnostic check bits
to determine syndrome bits or to pass as check bits to the SCO-5
outputs. The Internal mode substitutes the indicated bit position for
the external control signals.

8-214

IDT39C60/-1/A 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 5.
SYNDROME DECODE TO BIT-IN-ERROR
SYNDROME
BITS
SX

S8
S4
S2

0
0
0

1
0
0

0
1
0

1
1
0

'0
0
1

1
0
1

TABLE 6.
DIAGNOSTIC LATCH LOADING-16-BIT FORMAT

(1)

0
1
1

1
1
1

DATA BIT

INTERNAL FUNCTION

0

Diagnostic Check Bit X

1

Diagnostic Check Bit 0

M

2

Diagnostic Check Bit 1

T

3

Diagnostic Check Bit 2

6

T

4

Diagnostic Check Bit 4

SO

Sl

0

0

0

*

C8

C4

T

C2

T

T

0

0

1

C1

T

T

15

T

13

7

0

1

0

CO

T

T

M

T

12

0

1

1

T

10

4

T

0

T

T

M

5

1

0

0

CX

T

T

14

T

11

5

T

6,7

Don't Care

1

a

1

T

9

3

T

M

T

T

M

8

CODE 100

1

1

0

T

8

2

T

1

T

T

M

9

T

10

CODE 10 1
CODE 102

1

1

1

M

T

T

M

T

M

M

NOTE:
1. * = No errors detected
Number = Number of the single bit·in·error
T = Two errors detected
M = Three or more errors detected

DATA

Vee

OE"

Diagnostic Check Bit 8

11

DIAG MODE o

12

DIAG MODE1

13

CORRECT

14

PASSTHRU

15

Don't Care

CHECKS

BYTE 1
IDT39C60

OE" DATA - - - I OE' BYTE 2

MOLT ERROR

SCo-4

SYNDROMES/
CHECK BITS
Figure 3. 8·Bit Configuration

8-215

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

32-BIT DATA WORD CONFIGURATION
Two IDT39C60 EDC Units, connected as shown in Figure 5, provide all logic needed for single bit error correction and double bit
error detection of a 32-bit data field. The Identification code 32/39
indicates 7 check bits are required. Table 1 gives the ID2, IDl, IDa
values needed for distinguishin~e 0/1 from byte 2/3. Valid
syndrome, check bits and the ERROR and MULT ERROR signal
come from the byte 2/3 unit. Control signals not indicated are connected to both units in parallel. The OEsc always enables the SCO-6
outputs of byte 0/1, but must be used to select data check bits or
syndrome bits fed back from the byte 2/3 for data correction modes.
Data In bits 0 through 15 are connected to the same numbered
inputs of the byte 0/1 EDC unit, while Data In bits 16 through 31 are
connected to byte 2/3 Data Inputs 0 to 15, respectively.
Figure4 indicates the 39-bit data format of 4 bytes of data and
7 check bits. Check bits are input to the byte 0/1 unit through a
tri-state buffer unit such as the IDT74FCT244. Correction of single
bit errors of the 32-bit configuration requires a feedback of syndrome bits from byte 2/3 into the byte 1/0 unit. The MUX shown on
the functional block diagram is used to select the CBO-6 pins as the
syndrome bits rather than internally generated syndrome bits.
Table 3 describes the operating modes available for the 32/39
configuration.
Syndrome bits are generated by an Exclusive-OR of the generated check bits with the read check bits. For example, SX is the XOR
of check bits CX from those read with those generated. Table 7 indicates the decoding of the 7 syndrome bits to determine the bit in
error for a single bit error or whether a double or triple bit error was
detected. The all zero case indicates no errors detected.
In the Correct mode, the syndrome bits are used to complement
(correct) single bit errors in the data bits. For double or multiple error
detection, the data available as input to the Data Out Latch is not
defined.
Performance data is provided in Table 8 in relating a single
IDT39C60 EDC with the two cascaded units of Figure 5. As indicated, a summation of propagation delays is required from the cascading arrangement of EDC units.
Table 9 defines the bit definition for the Diagnostic Latch. As
defined In Table 3, several modes will use the Diagnostic check bits
to determine syndrome bits or to pass as check bits to the SCO-6 outputs. The Internal mode substitutes the indicated bit position for the
external control signals.
Table 10 indicates the Data Bits participating in the check bit
generation. For example, check bit CO is the Exclusive-OR function
of the 16 data input bits marked with an X. Check bits are generated
and output in the Generate and Initialization mode. Check bits are
passed as stored in the PASSTHRU or Diagnostic Generate mode.

TABLE 7.
SYNDROME DECODE
TO BIT-IN-ERROR FOR 32 BITS (1)
SYNDROME
BITS

24 23

1615

0
0
0

1
0
0

0
1
0

0
0
1

1
0
1

0
1
1

1
1
1

SO

S1

S2

0

0

0

0

*

C16

C8

T

C4

T

T

30

0

0

0

1

C2

T

T

27

T

5

M

T

0

0

1

0

C1

T

T

25

T

3

15

T

0

0

1

1

T

M

13

T

23

T

T

M

0

1

0

0

CO

T

T

24

T

2

M

T

0

1

0

1

T

1

12

T

22

T

T

M

0

1

1

0

T

M

10

T

20

T

T

M

0

1

1

1

16

T

T

M

T

M

M

T

1

0

0

0

ex

T

T

M

T

M

14

T

1

0

0

1

T

M

11

T

21

T

T

M

1

0

1

0

T

M

9

T

19

T

T

31

1

0

1

1

M

T

T

29

T

7

M

T

1

1

0

0

T

M

8

T

18

T

T

M

1

1

0

1

17

T

T

28

T

6

M

T

1

1

1

0

M

T

T

26

T

4

M

T

1

1

1

1

T

0

M

T

M

T

T

M

NOTE:
1. * = No errors detected
Number = Number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected

TABLE 8.
KEY AC CALCULATIONS
FOR THE 32-BIT CONFIGURATION
32-BIT
PROPAGATION DELAY
FROM

COMPONENT DELAY
FROM IDT39C60
AC SPECIFICATIONS

TO

DATA

Check Bits Out (DATA to SC)

+ (CB to SC, CODE ID 011)
+

(DATA to SC) + (CB to SC, Code ID 011)
(CB to DATA, CODE ID 010)

DATA

Corrected
DATA Out

DATA

Syndromes Out (DATA to SC)

DATA

ERROR for
32 Bits

DATA

for 32 Bits

(DATA to SC)
011)

MULl t:HROH (DATA to SC)

+ (CB to SC. CODE ID 011)
+ (CB to ERROR. CODE ID
+ (CB to MuL I

CODE ID 011)

CHECK BITS
BYTE 0 1 CX

8 7

1
1
0

SX

DATA
BYTE 31 BYTE 2 1 BYTE 1
31

S16
S8
S4

CO

C1 1 C2 1

0

USES MODIFIED HAMMING CODE 32/39
32 DATA BITS WITH 7 CHECK BITS
Figure 4. 32-Bit Data Format

8-216

C4

C8

C16

ERHOH,

IDT39C60/-1/A 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA 16-31
DATAo-1S
INPUT C~ECK BITS
r - - - ,
~
, CX CO C1 C2 C4 C8 C16' I 1/80F I
IIDTFCT240
I
I
I

TABLE 9.
DIAGNOSTIC LATCH LOADING-32-BIT FORMAT

1

17'\77'\7VV~

L. _ _ _ .J

IDT74FCT244

t--

Ceo C~

DATA

CB.! CB.3 CB4 CBs Ce.,

IDT39C60 EDC
BYTE 0 AND 1

OEsc
CODE 10

"1-

-010

Sea SC 1 SC2 SC3 SC4 SCs Sc;,

'-----l
Ceo C~

DATA

CB.! CB.3 CB4 CBs Ce.,

IDT39C60 EDC
BYTE 3 AND 4

MOLT

'C5"E"sc
CODE 10

ERROR

t--

ERL I

ERROR
SX/CX
S4/C4
S16/C16
S1/C1
\...
SO/CO
S2/C2
S8/C8
..I
'v"'"
SYNDROME/C~ECK

INTERNAL FUNCTION

0

Diagnostic Check Bit X

1

Diagnostic Check Bit 0

2

Diagnostic Check Bit 1

3

Diagnostic Check Bit 2

4

Diagnostic Check Bit 4

5

Diagnostic Check Bit 8

6

Diagnostic Check Bit 16

7

Don't Care

8

Slice 0/1-CODE 100

9

Slice 0/1-CODE 10 1

10

Slice 0/1-CODE 10 2

11

Slice 0/1-DIAG MODE o

12

Slice 0/1 - DIAG MODE 1

13

Slice 0/1 - CORRECT

14

Slice 0/1-PASSTHRU

15

Don't Care

16-23

Sea SC 1 SC2 SC3 SC4 SCs Sc;,

ERROR

MOLT

-011

DATA BIT

BIT OUTPUTS

Don't Care

24

Slice 2/3-CODE 100

25

Slice 2/3-CODE 101

26

Slice 2/3-CODE 102

27
28

Slice 2/3-DIAG MODE o
Slice 2/3-DIAG MODE 1

29

Slice 2/3 - CORRECT

30

Slice 2/3-PASS THRU

31

Don't Care

Figure 5. 32-Bit Configuration

TABLE 10. 32-BIT MODIFIED HAMMING CODE-CHECK BIT ENCODE CHART
PARTICIPATING DATA BITS

GENERATED
CHECK BITS

PARITY

CX

Even (XOR)

X

0

CO

Even (XOR)

X

C1

Odd (XNOR)

X

C2

Odd (XNOR)

X

C4

Even (XOR)

C8

Even (XOR)

C16

Even (XOR)

GENERATED
CHECK BITS

PARITY

CX

Even (XOR)

CO

Even (XOR)

1

X

2

3

X
X

4

6

7

8

9

X

X

X

X

X

X

X

X

X
X

X

5

X

X

X

X

X

X

X

X
X

X

X

X

X

X

X

16

17

18

19

20

21

X

X

X

X

X

X

X

23

24

25

X

X
X

X

X

C1

Odd (XNOR)

X

C2

Odd (XNOR)

X

C4

Even (XOR)

C8

Even (XOR)

X

X

C16

Even (XOR)

X

X

X
X

X

X

8-217

13

14

15

X
X

X

X

X

X

X

X
X

X

X

X

X

X

X

X

26

27

30

31

BITS

X
X

X

X

12

X

X

PARTICIPATIN~DATA

22

11

X
X

X

10

X

X

X

X

X

X

28

29

X

X

X

X

X

X
X

X

X
X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Syndrome bits are generated by ~n Exclusive-OR of !he generated check bits with the read check bits. For example, SX IS the XOR
of check bits CX from those read with those generated. Table 11
indicates the decoding of the 8 syndrome bits to determine the
bit in error for a single bit error or whether a double ortriple bit error
was detected. The all zero case indicates no errors detected.
In the Correct mode, the syndrome bits are used to co~plement
(correct) single bit errors in the data bits. For double or multiple error
detection, the data available as input to the Data Out Latch is not
defined.
Performance data is provided in Table 12 in relating a single
IDT39C60 EDC with the four units of Figure 7. Delay through the
exclusive, or MSI, gates and the 3-state buffer must be included.
Table 13 indicates the Data Bits participating in the check bit
generation. For example, check bit CO is the Exclusive-OR function
or the 32 data input bits marked with an X. Check bits are generated
and output in the Generate and Initialization mode. In the
PASSTHRU mode, the contents of the check bit latch are passed
through the external Exclusive-OR gates and appear inverted at
the outputs labeled CX to C32.
Table 14 defines the bit definition for the Diagnostic Latch.As
defined in Table 3, several modes will use the Diagnostic check bits
to determine syndrome bits or to pass as check bits to the SCa-6 outputs. The Internal mode substitutes the indicated bit position forthe
external control Signals.

64-BIT DATA WORD 'CONFIGURATION
The IDT39C60 EDC Units connected with the MSI gates, as
shown in Figure 6, provide the logic needed for single bit error correction and double bit error detection of a 64-bit data field. The Identification code 64/72 is used, indicating 8 check bits are required.
Check bits and Syndrome bits are generated external to the
IDT39C60 EDC using Exclusive-OR gates. For error correction, the
syndrome bits must be fed back to the CSa-6 inputs. Thus, external
tri-state buffers are used to select between the check bits read in
from memory and the syndrome bits being fed back.
The ERROR signal is low for one or more errors detected. From
any of the 4 devices, M ULT ERROR is low for some double bit errors
and for all three bit errors. Both are high otherwise. The DOUBLE
ERROR signal is high only when a double bit error is detected.
Figure 6 indicates the 72-bit data format of eight bytes of data and
8 check bits. Check bits are input to the various units through a
tri-state buffer such as the IDT74FCT244. Correction of single bit
errors of the 64-bit configuration requires a feedback of syndrome
bits as generated external to the IDT39C60 EDC ..The MUX s.hown
on the functional block diagram is used to select the CBa-6 pins as
the syndrome bits rather than internally generated syndrome bits.
Table 3 describes the operating modes available for the 64/72
configuration.
'"1

USES MODIFIED HAMMING CODE 64/72
64 DATA BITS WITH 8 CHECK BITS
Figure 6. 64-Bit Data Format

-

TABLE 11 SYNDROME DECODE TO BIT IN-ERROR
S32
S16
S8
S4

SYNDROME
BITS

0
0
0
0

1
0
0
0

0
1
0
0

1
1
0
0

0
0
1
0

(1)

1
0
1
0

0
1
1
0

1
1
1
0

0
0
0
1

1
0
0
1

0
1
0
1

1
1
0
1

T
53

T
37

51
T
50

SX SO S1

S2

0
0
0
0
0
0
0
0

0
0

0
0

0

*

C32

C16

T

C4

T

T

T

43

T
59

M

C2

T
M

C8

1

T

T

T
M

T
M
T

M
T
M

T
13

41
T
40

57
T
56

T
29

T
23
T

33

T

T

T

T
28

T
0

10

T

T

26

22
20

T

1
1

M
T
T

M
T
T
M
T
1
M
T

T
11
9

M
M

M
M

T
T

T
T

T
T
27

T
T
21

25

19

M
T
T

T

45

61

T

T

8

T

24

18

T

44
42

T
60
58

T
T

T

T

M

M

0
0
1
1
1
1

1

0

C1

1

1

0
0

0

T
CO

1

T

1
1

0

T
16

0
0

0

1

0
0
0
0

1

1

1

1

1
1

1
1
1

0
0
1

0
1
0

1

1

1

1

1

1
1
0

T
49

CX
T

M
T
T
M

T

M

M
T
17
M
T

NOTE:
1.· * = No errors detected .. T

T

M
T
T
48

M
M
T
M
T
T
32

= Two errors detected,

T
12

T
M
Number

T
T
M

1
0
1
1

0
1
1
1

1
1
1
1

M

T

46

62

T

M

T

T

T
M

35

T

15

T
34

7
T

T
M

T
M
T

T

6

T
M
M

4
T

T
T
M
14

T
M
T
M
M
T
T
M
63
T
M
T
T
M

T
T

T
5
3

55

39

T

M

T

T

52

T
38
36

2

T

T
54
T

T

= The number of the Single bit-in-error,

8-218

0
0
1
1

M

T
T

T

M

T
M

M

T

M

M
T
T
M
47
T
M
T
T
M

= More than two errors detected.

31
T
M
T
T
M
30
T
T

M
T
M
M
T

IDT39C60/-1/A 16-81T CMOS
ERROR DETECTION AND CORRECTION UNIT

OE"sc
IDT74FCT244

rI

-~

MILITARY AND COMMERCIAL TEMPERATURE RANGES

D63-48

~l
.11 I

~

16

C8 C4 C2 C1 CO CX D1S-

D31-16

D47-32
16

~V

- 1a

16

~ 1'<,

I~'

:~
I~

!

r--.l

CBe CEls CB4 CB3

.r-=

C5E"sc

c~

CB1 cBo

IDT39C60
BYTE6AND7

r"',"',"'. """""" I'
~

CBe CBS CB4 C~ CB2 CB1 CBo

D

l

-=

OE"sc

lh-= C5E"sc BYTE
IDT39C60
2 AND 3

IDT39C60
BYTE 4 AND 5

CBs CBS CB4 CB3 CB2 CB1 CBo

D

l-

O'i:sc

D

IDT39C60
BYTEOAND1

SCaSCSSC4 SC3 SC2 SC1 SCc

sCa sCs SC4 SC3 SC2 SC 1SCc

SC6SCSSC4 SC3 SC2 SC1 sCc

I

I

MOLT
ERROR

CBe CBS CB4 C~ CB2 CB1 CIla

D

L--

-

I

~XOR ~XOR ~XOR ~OR
_\lS8/C8

\JS4/C4

!

:W::W:

~~

~XOR

S4 /C4

illf~

XOR

S8/CS

I

---, I

I I

_\JS16/C16

S2/C2

S2/C2 S16/C16

N~~
R

NOR

'1J
0

S1/C1

S1/C1

-Uti

~XOR ~XOR
S32/C32

S32/C32

~

DOUBLE ERROR
NOTES.
1. In PASSTHRU mode the contents of the Check Latch appear on the XOR outputs inverted.
2. In Diagnostic Generate mode the contents of the Diagnostic Latch appear on the XOR outputs inverted.
Figure 7. 64-Bit Configuration

TABLE 12. KEY AC CALCULATIONS FOR THE
64-BIT CONFIGURATION
64-81T
PROPAGATION DELAY

COMPONENT DELAY
FROM IDT39C60
AC SPECIFICATIONS

FROM

TO

DATA

Check Bits Out

(DATA to SC)

DATA

Corrected
DATA Out

(DATA to SC) + (XOR Delay) + (Buffer
DELAY) + (CB to DATA. CODE ID 1xx)

DATA

Syndromes

(DATA to SC)

DATA

ERROR for
64-Bits

(DATA to SC)
Delay)

DATA

MuLT ERROR
for 64-Bits

(DATA to SC) + (XOR Delay) + (Buffer
Delay) + (CB to MULT ERROR. CODE
ID 1xx)

DATA

DOUBLE
ERROR for
64-Bits

(DATA to SC) + (XOR Delay)
(XOR/NOR Delay)

+

+
+

(XOR Delay)

(XOR Delay)
(XOR Delay)

+

(NOR

+

8-219

SO/CO

SO/CO

~

XO~
SX/CX

SX/CX

IDT39C60/-1/A 16·BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 13. 64-BIT MODIFIED HAMMING CODE-CHECK BIT ENCODE CHART
GENERATED
CHECK BITS

PARITY

CX

Even (XOR)

0

CO

Even (XOR)

X

C1

Odd (XNOR)

X

C2

Odd (XNOR)

X

1

2

3

X

X

X

X

X

4

7

X

X

X

X

X

X

X

X

X

Even (XOR)

C16

Even (XOR)

X

X

X

X

X

X

X

X

C32

Even (XOR)

X

X

X

X

X

X

X

X

16

17

18

19

20

21

X

X

X

X

X

Even (XOR)

9
X

X

Even (XOR)

CX

X

8
X

X

C4

PARITY

X

6

X
X

X

X

5

C8

GENERATED
CHECK BITS

X

X

22

23

X

24

25

X

X

Even (XOR)

X

Odd (XNOR)

X

C2

Odd (XNOR)

X

C4

Even (XOR)

C8

Even (XOR)

X

X

C16

Even (XOR)

X

C32

Even (XOR)

X

X
X

X

X

X

X
X

X

X
X

PARITY

CX

Even (XOR)

X

CO

Even (XOR)

X

C1

Odd (XNOR)

X

C2

Odd (XNOR)

X

32

X

X

X

X

X

X

33

X

34

35

X
X

36

38

39

X

X

X

X

X

X

X

Even (XOR)

X

X

37

C16

Even (XOR)

C32

Even (XOR)

GENERATED
CHECK BITS

PARITY

X

CX

Even (XOR)

X

CO

Even (XOR)

X

C1

Odd (XNOR)

X

C2

Odd (XNOR)

X

Even (XOR)
Even (XOR)

C16

Even (XOR)

C32

Even (XOR)

14

15

X
X

X

X

X

X
X

X

X

X

X

X

X

X

26

27

28

29

30

31

X

X
X
X

X

X

X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

40

42

43

46

47

X
X

X

X

X

X

X

X

X

41

X

44

45

X

X

X

X

X

X
X

X

X
X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

58

59

62

63

X

PARTICIPATING DATA BITS
48

C4

13

X

X

X
X

X

Even (XOR)

C8

12

X

PARTICIPATING DATA BITS

GENERATED
CHECK BITS

C8

11

PARTICIPATING DATA BITS

C1

,

10

X
X

CO

C4

(1)

PARTICIPATING DATA BITS

49

X

50

X
X

54

55

X

X

X

X

X

52

X

X

X

X

53

X

X

56

X

X

X

X

X'

X

X

X

X

60

61

X

X

X

X

X

X
X

X

X
X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

NOTE:
1. The check bit is generated as either an XOR or XNOR of the 32 data bits noted by an ·X" in the table.

8-220

57

X
X

X

X
X

X

51

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 14.
DIAGNOSTIC LATCH LOADING-64-BIT FORMAT
INTERNAL FUNCTION

DATA BIT

INTERNAL FUNCTION

DATA BIT

0

Diagnostic Check Bit X

31

Don't Care

1

Diagnostic Check Bit 0

32-37

Don't Care

2

Diagnostic Check Bit 1

38

3

Diagnostic Check Bit 2

39

Don't Care

4

Diagnostic Check Bit 4

40

Slice 4/5-CODE IDa

Diagnostic Check Bit 16

Diagnostic Check Bit 8

41

Slice 4/5-CODE IDl

Don't Care

42

Slice 4/5-CODE ID2

8

Slice 0/1-CODE IDa

43

Slice 4/5-DIAG MODEa

9

Slice 0/1-CODE IDl

44

Slice 4/5-DIAG MODEl

10

Slice 0/1-CODE ID2

45

Slice 4/5-CORRECT

11

46

Slice 4/5-PASSTHRU

12

Slice 0/1-DIAG MODE a
Slice 0/1-DIAG MODEl

47

Don't Care

13

Slice O/1-CORRECT

48-54

Don't Care

14

Slice 0/1 - PASSTHRU

55

Diagnostic Check Bit 32

15

Don't Care

56

Slice 6/7-CODE IDa

16-23

Don't Care

57

Slice 6/7-CODE IDl

24

Slice 2/3-CODE IDa

58

Slice 6/7-CODE ID2

25

Slice 2/3-CODE IDl

59

Slice 6/7-DIAG MODEa

26

Slice 2/3-CODE ID2

60

Slice 6/7-DIAG MODEl

27

Slice 2/3-DIAG MODEa

61

Slice 6/7-CORRECT

28

Slice 2/3-DIAG MODEl

62

Slice 6/7 - PASSTHRU

29

Slice 2/3-CORRECT

63

Don't Care

30

Slice 2/3-PASSTHRU

5
6,7

Some multiple errors will cause a data bit to be inverted. For
example, in the 16-bit mode where bits 8 and 13 are in error, the
syndrome 1111000 (SC, SO, S 1, S2, S4, S8) is produced. The bitin-error decoder receives the syndrome 11100 (SO, S1, S2, S4, S8)
which it decodes as a single error in data bit a and inverts that bit.
Figure 8 indicates a method for inhibition correction when a multiple error occurs.

DATA

IDT39C60

CHECKS

CORRECT
MULT
ERROR

Figure 8. Inhibition of Data Modification

8-221

CORRECT

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES
the value of the inputs and the internal states. Be sure to carefully
read the following definitions of symbols before examining the
tables.·

FUNCTIONAL EQUATIONS
The following equations and tables describe in detail how the
output values of the IOT39C60 EOC are determined as a function of

DEFINITIONS
01
CI
OLI
SI

i-

PA
PB
PC
PO
PE
PF
PG 1
PG 2

i-

PG 3
PG 4

iii-

iiiiiii-

DATAl if LEIN is HIGH or the output of bit i of the Data Input Latch if LEIN is LOW
CB I if LE IN is HIGH or the output of bit i of the Check Bit Latch if LE IN is LOW
Output of bit i of the Diagnostic Latch
Internally generated syndromes (same as outputs of SCI if outputs enabled)
Do EB
Do EB
OeEB
OoEB
Do EB
O2 EB
0 1 EB
0 1EB

0 1 EB
0 1 EB
OgEB
D:3 EB
0 1 EB
0 3 EB
0 4 EB
O2 EB

O2 EB 0 4EB 0 6 EB De EB 010EB 0 12
O2 EB 0 3 EB 0 4 EB 0 5 EB De EB 0 7
010EB o,lEB O,2EB 013EB 0 14
0 4 EB 07EB 09EB 010EB 013EB 0 15
0 5 EB OeEB 0 7 EB 011 EB 012EB 0 13
0 4 EB 0 5 EB De EB 0 14 EB 0 15
De EB 0 7
0 3 EB 0 5

De EB Dg EB 011 EB 0 14
010EB 012EB 013EB 0 15

ii-

Error Signals

(S6. (IDl + ID 2)) • 'SO. 54 • 'S3 . ~ . Sf . "SO + GENERATE + INITIALIZE + PASSTHRU
MOLT ERROR:

~: i -

(16 and 32-Bit Modes)

i-

((S6· 10,) EB S5 EB S4 EB S3 EB S2 EB S1 EB SO) (ERROR) + TOME
i - TmJE" + GENERATE + PASSTHRU + INITIALIZE

+ GENERATE + PASSTHRU + INITIALIZE

MOLT ERROR: (64-Bit Modes)

TABLE 15. TOME (Three or More Errors) (1)
SO
(2)S6
S5
S4

0
0
0
0

1
0
0
0

0
1
0
0

1
1
0
0

0
0
1
0

1
0
1
0

0
1
1
0

1
1
1
0

0
0
0
1

1
0
0
1

0
1
0
1

1
1
0
1

0
0
1
1

1
0
1
1

0
1
1
1

1
1
1
1
0

S1

S2

S3

0

0

0

0

0

0

1

0

1

1

1

0

1

1

1

0

0

0

0

0

1

0

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

1

0

0

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

NOTES:
1. S6, S5, ... SO are internal syndromes except in Modes 010,100,101,110,111 (CODE ID 2,ID 1, IDo).ln these modes, the syndromes are input over the
check bit lines. S6 i - C6, S5 i - C5, ... S1 i - C1, SO i - CO.
2. The S6 internal syndrome is always forced to 0 in CODE ID 000.

SC OUTPUTS
Tables 16, 17, 18, 19,20 show how outputs SCo-e are generated in each control mode for various CODE IDs (internal control mode not
applicable).

TABLE 16. GENERATE MODE (Check Bits)
GENERATE
MODE (CHECK BITS)

000

CODE 1D2-0
100

010

011
PG 2 EB PG 4
EB CBo

SCo

i-

PG 2 EB PG 3

PG 1EB PG 3

SCI

i-

PA

PA

PA EB CBl

SC2

i-

PO

PD

PD EB CB2

SC3

i-

PE

PE

SC4

i-

PF

PF

SC5

i-

PC

PC

SC6

i-

1

PB

PG 2 EB PG 3

101
PG 2 EB PG 3

110

111

PG 1EB PG 4

PG 1EB PG 4

PA

PA

PA

PA

PO

PD

PD

PD

PE EB CB3

PE

PE

PE

PE

PF EB CB4

PF

PF

PF

PF

PC EB CB5

PC

PC

PC

PC

PC EB CB6

PB

PB

PB

PB

8-222

IOT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 17 DETECT AND CORRECT MODES (Syndromes)
DETECT AND CORRECT
MODES (SYNDROMES)
SC o +SC, +SC2 +SC3 +SC4 +SC5 +-

000

EB PG 3
EB CO
PA EB Cl
PITEB C2
FE EB C3
PF EB C4
PC EB C5

PG 2

010

EB PG 3
EB CO
PA EB Cl
PD EB C2
PE" EB C3
PF EB C4
PC EB C5
PB EB C6

PG ,

011(1)
PG 2

EB PG 4

EB CBo
PA EB CB,
PD EB CB2
PE EB CB3
PF EB CB4
PC EB CB5
PC EB CBe

CODE 102-0
100

EB PG 3
EB CO
PA EB Cl
PD EB C2
PE EB C3
PF EB C4
PC EB C5

PG 2

SCe +1
PB
NOTE:
1. In CODE ID2_0 all the Check Bit Latch is forced transparent; the Data Latch operates normally.

101
PG 2 EB PG 3

110

EB

PG ,

PG 4

111

EB

PG ,

PA

PA

PA

PD

PD

PD

PE

PE

PE

PF

PF

PF

PC

PC

PC

PB

PB

EB C6

PB

PG 4

EB C6

TABLE 18 DIAGNOSTIC READ MODE
DIAGNOSTIC
READ MODE
SC o +-

000
PG 2

EB PG 3

SC5 +-

EB DLo
PA EB DL,
PIT EB DL2
PE" EB DL3
PF EB DL4
PC EB DL5

SCe +-

1

SC, +SC2 +SC3 +SC4 +-

010
PG ,

EB PG 3

EB DLo
PA EB DL,
PD EB DL2
PE" EB DL3
PF EB DL4
PC EB DL5
PB EB DLe

011(1)
PG 2

EB PG 4

EB CBo
PA EB CB,
PD EB CB2
PE EB CB3
PF EB CB4
PC EB C B 5
PC EB CBe

CODE ID2-0
100
PG 2

EB PG 3

EB DLo
PA EB DL,
PD EB DL2
PE EB OL3
PF EB DL4
PC EB DL5
PB

101
PG 2 EB PG 3

110
PG ,

EB

PG 4

111
PG ,

EB

PA

PA

PA

PD

PD

PD

PE

PE

PE

PF

PF

PF

PC
PB

PC
PB

EB DL6

PG 4

PC
PB

EB DL7

NOTE:
1. In CODE ID2- 0 all the Check Bit Latch is forced transparent; the Data Latch operates normally.

TABLE 19 DIAGNOSTIC WRITE MODE
DIAGNOSTIC
WRITE MODE

CODE 102-0
000

010

011 (1)

100

101

110

111

SC o +-

OLD

OLD

CBo

DLo

1

1

1

SC, +-

DL,

DL,

CB,

DL,

1

1

1

SC2 +-

DL2

_ DL2

CB2

DL2

1

1

1

SC 3 +-

DL3

DL3

CB 3

DL3

1

1

1

SC 4 +-

DL4

DL4

CB 4

DL4

1

1

1

SC 5 +-

DL5

DL5

CB 5

DL5

1

1

1

DL6

CB 6

1

DLe

DL7

SC 6 +-

1

1

NOTE:
1. In CODE ID2_0 all the Check Bit Latch is forced transparent; the Oata Latch operates normally.

TABLE 20 PASSTHRU MODE
PASSTHRU
MODE

CODE 102-0
000

010

011 (1)

100

101

110

111

SC o +-

Co

Co

CBo

Co

1

1

1

SC, +-

C,

C,

CB,

C,

1

1

1

SC2 +-

C2

C2

CB2

C2

1

1

1

SC 3 +-

C3

C3

CB 3

C3

1

1

1

SC 4 +-

C4

C4

CB 4

C4

1

1

1

SC 5 +-

C5

C5

CB 5

C5

1

1

1

SC e +-

1

C6

CBe

1

1

Ce

Ce

NOTE:
1. In CODE ID2_0 all the Check Bit Latch is forced transparent; the Data Latch operates normally.

8-223

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE 22. CODE ID 2- 0 = 010(1)

TABLE 21. CODE 1D2-0 = 000 (1)
SS
S4
S3

0
0
0

0
0
1

0
1
0

0
1
1

1
0
0

1
0
1

1
1
0

1
1
1

0
1
0
0

0
1
0
1

0
1
1
0

0

-

11

1

8

12

1

0

9

13

15

1

1

10

-

-

CB6
CBS
CB4
CB2 CB1 CB3

S2

S1

0

0

-

-

-

5

-

11

14

-

0

1

-

1

2

6

8

12

-

-

0
0

-

1
1

-

0
1

0

3
4

7

-

13

9

10

-

15

-

NOTE:
1. Unlisted S combinations are no correction.

0
0
0
1

0
0
1
0

0
0
1
1

1
1
0
0

1
1
0
1

1
1
1
0

S1

0

-

-

-

5

-

11

14

-

0

1

-

1

2

6

8

12

-

-

1

1

-

-

0

3

4

7

-

13

9

10

-

15

-

CBO
CB6
CBS
CB4
CB2 CB1 CB3

1
1
1
1

0

0

NOTE:
1. Unlisted S combinations are no correction.

1
0
1
0

1
0
1
1

14

-

-

-

-

5

-

-

-

1

2

6

-

-

3

7

0

4

-

0
0
1
0
0

0
0
1
0
1

0
0
1
1
0

0
0
1
1
1

1
1
0
0
0

1
1
0
0
1

1
1
0
1
0

1
1
0
1
1

5

0

0

-

11

14

-

-

-

-

0

1

8

12

-

-

-

1

2

6

1

0

9

13

15

-

-

-

3

7

1

1

10

-

-

-

-

0

4

-

1
0
1
0
1

1
0
1
1
0

1
0
1
1
1

NOTE:
1. Unlisted CB combinations are no correction.

TABLE 25. CODE 1D2-0 = 101 (1)
CBO
CB6
CBS
CB4
CB2 CB1 CB3

1
0
0
1

TABLE 24. CODE ID2-0 = 100 (1)

0
0
0
0

S2

1

1
0
0
0

NOTE:
1. Unlisted CB combinations are no correction.

TABLE 23. CODE 1D2-0 = 011 (1)
S6
S5
S4
S3

0
1
1
1

TABLE 26. CODE 1D2-0 = 110(1)

0
0
0
0
0

0
0
0
0
1

0
0
0
1
0

0
0
0
1
1

1
1
1
0
0

1
1
1
0
1

1
1
1
1
0

1
1
1
1
1

-

0

0

-

-

-

5

-

11

14

0

1

-

1

2

6

8

12

-

1

0

-

-

3

7

9

13

15

1

1

-

0

4

-

10

-

-

CBO
CB6
CBS
CB4
CB2 CB1 CB3

0
1
0
0
0

0
1
0
0
1

0
1
0
1
0

0
1
0
1
1

1
0
1
0
0

-

-

5

-

11

14

-

1

2

6

8

12

-

-

3

7

9

13

15

0

4

-

10

-

-

-

0

0

0

1

1

0

-

1

1

-

NOTE:
1. Unlisted CB combinations are no correction.

NOTE:
1. Unlisted CB combinations are no correction.

TABLE 27. CODE ID2-0= 111 (1)
CBO
CB6
CBS
CB4
CB2 CB1

ca3

0
1
1
0
0

0
1
1
0
1

0
1
1
1
0

0
1
1
1
1

1
0
0
0
0

1
0
0
0
1

1
0
0
1
0

1
0
0
1
1

5

0

0

-

11

14

8

12

-

-

-

1

-

-

0

1

2

6

1

0

9

13

15

-

-

3

7

1

1

10

-

-

-

-

0

4

-

NOTE:
1. Unlisted CB combinations are no correction.

8-224

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

CAPACITANCE

(1)

COMMERCIAL
-0.5 to +7.0

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MILITARY
-0.5 to +7.0

UNIT
V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

lOUT

DC Output Current

30

30

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

SYMBOL
C IN

Input Capacitance

C OUT

Output Capacitance

CONDITIONS

TYP.

VIN = OV

5

pF

VOUT= OV

7

pF

UNIT

NOTE:
1. This parameter is sampled and not 100% tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATI NGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
Vcc = S.OV ± 5% (Commercial)
Vcc = S.OV ± 10% (Military)

TA = O°C to + 70°C
TA = -55°C to + 125°C
VLC = 0.2V
VHC = Vcc - 0.2V
SYMBOL

TEST CONDITIONS (1)

PARAMETER

V

0.1

5

IJA

-0.1

-5

IJA

4.3

-

V

4.3

-

GND

VLC

Vo = OV

-

Vo = Vcc (max.)

-

\'IL

Input LOW Level

Guaranteed Logic Low Level (4)

IIH

Input HIGH Current

IlL

Input LOW Current

(4)

Vcc = Max., \'IN = Vcc
Vcc = Max., \'IN = GND

VHC

Vcc

10H = -12mA MIL.

2.4

10H = -15mA COM'L.

2.4

Vcc = Min.
VIN = \'IH or\'lL

10L = 300IJA

loz

Output LOW Voltage

Off State (High Impedance)
Output Current

2.0

-

10H = - 3OOIJ A

VOL

-

VCC = Min.
VIN = \'IH or\'lL

10L = 20mA MIL.
10L = 24mA COM'L.

Vcc = Max.

-30
Output Short Circuit Current
Vcc = Min., VOUT= OV (3)
los
NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levelS provide zero noise immunity and should only be static tested in a noise-free environment.

8-225

UNIT

V

Guaranteed Logic High Level

Output HIGH Voltage

Typ.(2) MAX.

-

Input HIGH Level

VOH

MIN.

0.8

VIH

0.3

0.5

0.3

0.5

-0.1

-10

0.1

10

-

-

V

IJA
mA

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS (Cont'd)
TA = O°C to + 70°C
TA = -55°C to + 125°C
VLC = 0.2V
V,HC -v,
- cc -02V

Vcc = 5.0V ± 5% (Commercial)
Vcc = 5.0V ± 10% (Military)

TEST CONDITIONS

SYMBOL

PARAMETER

lceo

Quiescent Power Supply Current
(CMOS Inputs)

ICCT

Quiescent Input Power Supply (5)
Current (per Input @ TIL High)

ICCD

Icc

Dynamic Power Supply Current

Total Power Supply Current

(6)

= Max.
:s \'IN' \'IN :s VLC
=0
VCC = Max. \'IN = 3.4V, fop = 9
Vcc = Max.
VHC :s \'IN, \'IN :s VLC
Outputs Open. at: = L
Vcc = Max., fOF' = 10MHz
Outputs Open, OE" = L

(1)

Vcc
VHC
fop

50% Duty Cycle
VHC < \'IN, \'IN < VLC
Vcc = Max., fop = 10MHz
Outputs Open, OE" = L
50% Duty Cycle
\'IN = 3.4V, \'IN = O.4V

MIN.

TVP.(2)

MAX.

UNIT

-

3.0

5.0

rnA

-

0.3

0.5

mA/lnput

5.0

8.5

COM'L.

-

5.0

7.0

MIL.

-

53

90

COM'L.

-

53

75

MIL.

-

60

100

COM'L.

-

60

85

MIL.

rnA/MHz

rnA

NOTES:
5. ICCT Is derived by measuring the total current with ail the inputs tied together at 3.4V, subtracting out ICCQ, then dividing by the total number of Inputs.
6. Total Supply Current is the sum ofthe Quiescent current and the Dynamic current (at either CMOS or TIL input levels). For all conditions, the Total Supply
Current can be calculated by using the following equation:
Icc = Icco

+

ICCT (NT X DH)

+

ICCD (fop)

DH = Data duty cycle TIL high period (\'IN = 3.4V)
NT = Number of dynamic inputs driven at TIL levels
fop = Operating frequency

CMOS TESTING CONSIDERATIONS
Special test board considerations must be taken into account
when applying high-speed CMOS products to the automatic test
environment. Large output currents are being switched in very short
periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing
results:
1) All input pins should be connected to a voltage potential during
testing. If left floating, the device may oscillate, causing improper
device operation and possible latchup.
2) Placement and value of decoupling capacitors is critical. Each
physical set-up has different electrical characteristics and it is
recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the
minimum lead lengths. They should also be distributed to
decouple power supply lines and be placed as close as possible
to the OUT power pins.

3) Device grounding is extremely critical for proper device testing.
The use of multi-layer performance boards with radial decoupling between power and ground planes is necessary. The ground
plane must be sustained from the performance board to the OUT
interface board and wiring unused interconnect pins to the
ground plane is recommended. Heavy gauge stranded wire
should be used for power wiring, with twisted pairs being recommended for minimized inductance.
4) To guarantee data sheet compliance, the input thresholds should
be tested per input pin in a statiq environment. To allow for testing
and hardware-induced noise, lOT recommends using VIL :s OV
and VIH ~ 3V for AC tests.

8-226

IDT39C60/-1/A 16·81T CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60 INPUT/OUTPUT
INTERFACE CIRCUITRY
Vee
ESD
PROTECTION
IIH ......- - - - , - - -...

INPUTS

OUTPUTS

Figure 10. Input Structure (All Inputs)

Figure 11. Output Structure

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

TEST LOAD CIRCUITS

GND to 3.0V

WIns
1.5V
1.5V
See Figure 12

TEST

SWITCH

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS
CL = Load capacitance: includes jig and probe capacitance
RT = Termination resistance: should be equal to 2'oUT of the
Pulse Generator

8-227

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60A over the commercial operating range ofOoC to + 70°C,
with Vcc from 4.7SV to S.2SV. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.SV. All outputs have maximum DC load.

COMBINATIONAL PROPAGATION DELAYS

SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

c L = SOpF
FROM INPUT
DATA0-15
CBO-6
(CODE ID2- 0
000,011)

TO OUTPUT
SCO-6
20
14

DATA 0-15 ERROR
30
25

20
20

TO
(LATCHING
UP DATA)

SET-UP
TIME

HOLD
TIME

LEIN

5

3

' LEIN

5

3

LEoUT

24

2

23

CBO-6
(CODE ID 000, 011)

LEoUT

21

0

CBO-6
(CODE ID 010, 100,
101,110,111»

LEoUT

21

0

23

CBO-6
DATA 0-15

14

GE:f\JERATE:

15

25

14

17

CORRECT
(Not Internal
Control Mode)

-

20

-

-

18

20

DIAG MODE
(Not Internal
Control Mode)

22

PASSTHRU
(Not Internal
Control Mode)

22

CODE 10 2 - 0

23

28

25

28

LEIN
(From latched
to transparent)

22

32(1)

22

25

25

25

18

18

21

21

GENERATE

LEOLrr

26

0

CORRECT

LEoUT

22

0

DIAG MODE

LEouT

22

0

PASSTHRU

LEoUT

22

0

CODE ID2-0

LEoUT

25

0

LEIN

LEoUT

28

0

DATA 0-15

LEolAG

5

3

OUTPUT ENABLE/DISABLE TIMES

-

13

-

Output disable tests performed with C L = SpF and measured to
O.SV change of output voltage level.

-

INPUT

LE DIAG
(From latched to
transparent; Not
Internal Control
Mode)

22

Internal Control
Mode: LE OIAG
(From latched
to transparent)

28

Intemal Control
Mode: DATA o_15
(Via Diagnostic
Latch)

DATA 0-15

23

CB O_6
(CODE ID2-0 010,
100,101,110,111)

LEOLrr
(From latched
to transparent)

FROM INPUT

MULT ERROR

32

38

22

28

OE:" BYTE o'
OE:" BYTE 1
OEsc

25

31

38

28

ENABLE

DISABLE

DATA o_15

24

21

SCO-6

24

21

MINIMUM PULSE WIDTHS

I
28

OUTPUT

LEIN, LEoUT' LEolAG

31

NOTE:
1. DATA IN (or LE IN ) to Correct DATAOLrr measurement requires timing as
shown in Figure 13 below.
VALID
INPUT DATA
DATA 0-15

=:1. DATA
TO LEON
HOLD TIME

_ _ _ _ _ _~
OE BYTE 0& 1

Figure 13.

8-228

CORRECT DATA
OUTPUT

12

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60Aoverthe military operating range of -SsoC to + 12SoC,
with Vee from 4.SV to S.SV. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.SV. All outputs have maximum DC load.

COMBINATIONAL PROPAGATION DELAYS

SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

c L = SOpF
TO OUTPUT
FROM INPUT

SC o_s

DATA 0-15

ERROR

MULT ERROR

DATA 0-15

22

35

24

27

CBO-6
(CODE ID2- 0

17

28

24

27

TO
(LATCHING
UP DATA)

FROM INPUT

SET-UP
TIME

HOLD
TIME

DATA 0-15

LEIN

5

3

CBO-6

LEIN

5

3

000,011)

DATA o- 15

LEoUT

27

2

CB O_6
(CODE ID2-0 010,

27

CBO-6
(CODE ID 000, 011)

LEoUT

24

0

21

CBO-6
(CODE ID 010, 100,

LEoUT

24

0

GENERATE

LEoUT

29

0

CORRECT

LEoUT

25

0

DIAG MODE

LEoUT

25

0

PASSTHRU

LEoUT

25

0

CODE ID2-0

LEoUT

28

0

LEIN

LEoUT

30

0

DATA 0-15

LEolAG

5

3

17

20

24

100,101,110,111)
GENERATE
CORRECT
(Not Inte~nal
Control Mode)
DIAG MODE
(Not Internal
Control Mode)

20

28

18

101,110,111»

25

25

28

21

24

PASSTHRU
(Not Internal
Control Mode)

25

CODE ID2-0

26

31

28

31

LEIN
(From latched
to transparent)

24

37(1)

26

29

LEoUT
(From latched
to transparent)

21

24

OUTPUT ENABLE/DISABLE TIMES
-

16

-

Output disable tests performed with C L = SpF and measured to
O.SV change of output voltage level.

-

INPUT

LE 01AG
(From latched to
transparent; Not
Internal Control
Mode)

24

Internal Control
Mode: LE OIAG
(From latched
to transparent)

30

Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)

28

37

26

'OE" BYTE o,

29

OEBYTE 1
OEsc

43

32

35

43

32

ENABLE

DISABLE

DATA o_15

28

25

SCO-6

28

25

MINIMUM PULSE WIDTHS

I
30

OUTPUT

LEIN, LEouT' LEolAG

35

NOTE:

1. DATAIN (or LE 1N ) to Correct DATAoUT measurement requires timing as
shown in Figure 14 below.

CORRECT DATA
OUTPUT

VALID
INPUT DATA
DATA 0-15

::=:I

_ _ _ _ _ _~

DATA TO LEIN
HOLD TIME

OE BYTE 0& 1
Figure 14.

8-229

12

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60-1 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60-1 over the commercial operating range of 0 0 C to + 70°C,
with Vee from 4.7SV to S.2SV. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.SV. All outputs have maximum DC load.

COMBINATIONAL PROPAGATION DELAYS

SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

C L = 50pF
FROM INPUT
DATA o_15
CBO-6
(CODE ID2- 0

TO OUTPUT
SCo-s

DATA 0-15

ERROR

28

52

25

23

50

MOLi

23

TO
(LATCHING
UP DATA)

FROM INPUT

ERROR

50
47

SET-UP
TIME

HOLD
TIME

DATA 0-15

LEIN

6

7

CBO-6

LEIN

5

6

000,011)

DATA 0-15

LEoUT

34

5

CB O- 6
(CODE ID2-0 010.

LEoUT

35

0

LEoUT

27

0
0

28

34

29

34

CBO-6
(CODE ID 000, 011)

35

63

36

55

CB O- 6
(CODE ID 010, 100,

100,101,110,111)

GEf\JEI1ATE

101,110,111))

CORRECT
(Not Internal
Control Mode)

-

DIAG MODE
(Not Internal
Control Mode)

50

45

78

59

75

PASSTHRU
(Not Internal
Control Mode)

36

CODE ID2-0

61

90

60

80

LEIN
(From latched
to transparent)

39

72(1)

39

59

LEoUT
(From latched
to transparent)

-

44

29

46

GEf\JERATE

LEoUT

42

CORRECT

LEoUT

26

1

DIAG MODE

LEoUT

69

0

PASSTHRU

LEoUT

26

0

CODE ID2-0

LEoUT

81

0

LEIN

LEoUT

51

5

DATA 0-15

LE olAG

6

8

OUTPUT ENABLE/DISABLE TIMES

31

-

Output disable tests performed with C L = 5pF and measured to
0.5V change of output voltage level.

-

INPUT

LE OIAG
(From latched to
transparent; Not
Internal Control
Mode)

45

Internal Control
Mode: LE OIAG
(From latched
to transparent)

67

Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)

67

78

96

45

66

65

86

66

OE"sc

OUTPUT

ENABLE

DISABLE

DATA 0-15

30

30

SCO-6

30

30

MINIMUM PULSE WIDTHS

I
96

DE:BYTE o'
01: BYTE 1

LEIN, LEoUT, LE OIAG

86

NOTE:

1. DATAIN (or LE IN ) to Correct DATAoUT measurement requires timing as
shown in Figure 15 below.
VALID

CORRECT DATA
OUTPUT

INPUT DATA
DATA 0-15

==:l

~_ _ _ _ _~

DATA TO LEIN
HOLD TIME

OE BYTEo&l
Figure 15.

8-230

15

IDT39C60/-1/A 16-81T CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60-1 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60-1 over the military operating range of-55°Cto + 125°C,
with Vcc from 4.5V to 5.5V. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.5V. All outputs have maximum DC load.

SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

COMBINATIONAL PROPAGATION DELAYS

c L = 50pF

TO
(LATCHING
UP DATA)

TO OUTPUT
FROM INPUT
DATA o-15
CB O_6
(CODE ID2- 0
000,011)

SCO-6

DATA 0-15

ERROR

MULT ERROR

31

59

28

56

25

55

25

CB O_6
(CODE ID2_0 010,
100,101,110,111)

30

GENERATE

38

69

41

CORRECT
(Not Internal
Control Mode)

-

49

-

DIAG MODE
(Not Internal
Control Mode)
PASSTHRU
(Not Internal
Control Mode)

58

39

38

89

51

31

65

34

50

SET-UP
TIME

HOLD
TIME

DATA 0-15

LEIN

7

7

CBO-6

LEIN

5

7

DATA 0-15

LEoUT

39

5

CBO-6
(CODE ID 000,011)

LEoUT

38

0

62

CBO-6
(CODE ID 010, 100,
101,110,111»

LEoUT

30

0

-

GENERATE

LEoUT

46

0

CORRECT

LEoUT

28

1

DIAG MODE

LEoUT

84

0

37

90

54

CODE ID 2- 0

69

100

68

90

LEIN
(From latched
to transparent)

39

82(1)

43

66

LEoUT
(From latched
to transparent)

-

PASSTHRU

LEoUT

30

0

CODE ID2-0

LEoUT

89

0

LEIN

LEoUT

59

5

DATA 0-15

LEDIAG

7

9

33

-

Output disable tests performed with C L = 5pF and measured to
O.5V change of output voltage level.

-

OUTPUT

ENABLE

DISABLE

OE BYTE1

DATA o_15

35

35

OEsc

SCO-6

35

35

INPUT
50

Internal Control
Mode: LE DIAG
(From latched
to transparent)

75

88

106

49

74

~BYTEo'

72

96

MINIMUM PULSE WIDTHS

I
75

106

74

LEIN, LEoUT, LEDIAG

96

NOTE:
1. DATAIN (or LE 1N ) to Correct DATAoUT measurement requires timing as
shown in Figure 16 below.
VALID
INPUT DATA

CORRECT DATA
OUTPUT

DATA 0-15

~

........._ _ _ _ _ _

DE BYTE 0& 1

Ell
I

OUTPUT ENABLE/DISABLE TIMES

LE D1AG
(From latched to
transparent; Not
Internal Control
Mode)

Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)

FROM INPUT

DATATOLEIN
HOLD TIME

Figure 16.

8-231

15

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT39C60 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60 over the commercial operating range of O°C to + 70°C,
with Vcc from 4.75V to 5.25V. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.5V. All outputs have maximum DC load.

COMBINATIONAL PROPAGATION DELAYS

SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

C L = 50pF
FROM INPUT
DATAO-15

SC O_6
32

TO OUTPUT
DATA o_15 ERROR
65(1)

32

50

CB o_6
(CODE ID2_0
000,011)

28

CB O_6
(CODE ID2-0 010,
100,101,110,111)

28

45

29

34

GEIiJERAiE

35

63

36

55

CORRECT
(Not Internal
Control Mode)

-

45

-

-

DIAG MODE
(Not Internal
Control Mode)

50

56

78

29

59

47

75

PASSTHRU
(Not Internal
Control Mode)

36

CODE 102-0

61

90

60

80

LEIN
(From latched
to transparent)

39

72(1)

39

59

LEoUT
(From latched
to transparent)

29

46

SET-UP
TIME

HOLD
TIME
7

DATA 0-15

LEIN

6

C B O-6

LEIN

5

6

DATA 0-15

LEoUT

44

5

C B O-6
(CODE ID 000, 011)

LEoUT

35

0

CBO-6
(CODE ID 010,100,
101,110,111))

LEoUT

27

0
0

GENERATE

LEoUT

42

CORRECT

LEoUT

26

1

DIAG MODE

LEoUT

69

0

PASSTHRU

LEoUT

26

0

CODE ID 2-0

LEoUT

81

0

LEIN

LEoUT

51

5

DATA 0-15

LEDIAG

6

8

OUTPUT ENABLE/DISABLE TIMES
-

31

-

Output disable tests performed with C L = SpF and measured to
O.SV change of output voltage level.

-

INPUT

LE D1AG
(From latched to
transparent; Not
Internal Control
Mode)

45

Internal Control
Mode: LE DIAG
(From latched
to transparent)

67

Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)

44

TO
(LATCHING
UP DATA)

FROM INPUT

MULT ERROR

78

45

DE" BYTE o'

65

OE

BYTEI

OEsc

96

66

86

96

66

ENABLE

DISABLE

DATA o_15

30

30

SCO-6

30

30

MINIMUM PULSE WIDTHS

I
67

OUTPUT

LEIN, LEoUT' LE DIAG

86

NOTE:
1. DATAIN (or LE 1N ) to Correct DATAoUT measurement reqUires timing as
shown in Figure 17 below.

VALID

CORRECT DATA
OUTPUT

INPUT DATA
DATA 0-15

==:1

_ _ _ _ _ _~
OE BYTEo&1

DATA TO LEIN
HOLD TIME

Figure 17.

8-232

15

IDT39C60/-1/A 16-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

~ILlTARY

AND COMMERCIAL TEMPERATURE RANGES

IDT39C60 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance)
The tables below specify the guaranteed performance of the
IDT39C60 over the military operating range of -SsoC to + 12SoC,
with Vcc from 4.SV to S.SV. All data are in nanoseconds, with
inputs switching between OV and 3V at 1V per nanosecond and
measurements made at 1.SV. All outputs have maximum DC load.

COMBINATIONAL PROPAGATION DELAYS

cL =

SET-UP AND HOLD TIMES
RELATIVE TO LATCH ENABLES

SOpF
TO OUTPUT

FROM INPUT
DATA o_15
CBO-6
(CODE ID2- 0
000,011)

SC O_6
35
30

DATA o_15 ERROR
73(1)
61

36
31

56
50

7

7

LEIN

5

7
5

LEoUT

38

0

62

CB O-6
(CODE ID 010, 100,
101,110,111))

LEoUT

30

0

-

GENERATE:

LEoUT

46

0

CORRECT

LEoUT

28

1

DIAG MODE

LEoUT

84

0

37

GENERATE

38

69

41

CORRECT
(Not Internal
Control Mode)

-

49

-

90

PASSTHRU
(Not Internal
Control Mode)

39

51

34

54

CODE ID 2 - 0

69

100

68

90

LEIN
(From latched
to transparent)

44

82(1)

43

66

LEoUT
(From latched
to transparent)

-

PASSTHRU

LEoUT

30

0

CODE ID 2 - 0

LEoUT

89

0

LEIN

LEoUT

59

5

DATA 0-15

LE DIAG

7

9

OUTPUT ENABLE/DISABLE TIMES
33

-

Output disable tests performed with C L = SpF and measured to
O.SV change of output voltage level.

-

OUTPUT

ENABLE

DISABLE

OE BYTE o'
OE BYTE1

DATA o_15

35

35

OEsc

SCO-6

35

35

INPUT

LE 01AG
(From latched to
transparent; Not
Internal Control
Mode)

50

Internal Control
Mode: LE DIAG
(From latched
to transparent)

75

Internal Control
Mode: DATA o_15
(Via Diagnostic
Latch)

LEIN

CBO-6

50

31

65

DATA o- 15

LEoUT

50

89

HOLD
TIME

DATA o- 15
30

58

SET-UP
TIME

CBO-6
(CODE ID 000, 011)

CB O- 6
(CODE ID2-0 010,
100,101,110,111)

DIAG MODE
(Not Internal
Control Mode)

TO
(LATCHING
UP DATA)

FROM INPUT

MULT ERROR

88

106

49

74

72

96

MINIMUM PULSE WIDTHS

I
75

106

74

LEIN, LEoUT' LE DIAG

96

NOTE:
1. DATAIN (or LE 1N ) to Correct DATAoUT measurement requires timing as
shown in Figure 18 below.
CORRECT DATA
OUTPUT

:=:I

_ _ _ _ _ _ _~

DATA TO LE IN
HOLD TIME

"Oi: BYTE 0 & 1
Figure 18.

8-233

15

IDT39C60/-1/A 16-81T CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxxxx

X

x

Device Type

Package

Process!
Temperature
Range

Y:"nk
P
XC

~------------------~

C

J

L
l..--______________________________---j

39C60
39C60-1
39C60A

8-234

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
Sidebraze Shrink-DIP
Sidebraze DIP
Plastic Leaded Chip Carrier
Leadless Chip Carrier
16-Bit EDC Unit
Fast 16-Bit EDC Unit
Ultra-fast 16-Bit EDC Unit

FEATURES:

DESCRIPTION:

• Fast
- IDT49C460B
-IDT49C460A
-IDT49C460

Detect
25ns (max.)
30ns (max.)
40ns (max.)

The IDT49C460s are high-speed, low-power, 32-bit Error Detection and Correction Units which generate check bits on a 32-bit
data field according to a modified Hamming Code and correct the
data word when check bits are supplied. The lOT49C460s are performance-enhanced functional replacements for 32-bit versions of
the 2960"When performing a read operation from memory, the
IDT49C460s will correct 100% of all single bit errors and will detect
all double bit errors and some triple bit errors.
The lOT49C460s are easily cascadable to 64-bits. Thirty-two-bit
systems use 7 check,bits and 64-bit systems use 8 check bits. For
both configurations, the error syndrome is made available.
The IDT49C460s incorporate two built-in diagnostic modes.
Both simplify testing by allowing for diagnostic data to be entered
into the device and to execute system diagnostic functions.
They are fabricated using CEMOS ™, a CMOS technology designed for high-performance and high-reliability. The devices are
packaged in a 68-pin PGA, sidebraze Shrink-DIP (600 mil, 70 mil
centers), LCC (25 mil and 50 mil centers) and PLCC.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

Correct
30ns (max.)
36ns (max.)
49ns (max.)

• Low-power CMOS
- Commercial: 95mA (max.)
- Military: 125mA (max.)
• Improves system memory reliability
- Corrects all single bit errors, detects all double and some
triple-bit errors
• Cascadable
- Data words up to 64-bits
• Built-in diagnostics
- Capable of verifying proper EDC operation via software
control
• Simplified byte operations
- Fast byte writes possible with separate byte enables
• Functional replacement for 32- and 64-bit configurations of the
2960
• Available in PGA, Sidebraze Shrink-DIP, LCC and PLCC
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
LE OUT /GENERATE
DE BYTE 0-3

L>----+---,

CBO-7 r-~~----~-4--------------~
DATA 0-31

SCO-7

LEOIAG

CODE ID C~:"';'--r----..,
DIAG MODE r::-)-~---+f
CONTROL
LOGIC
LE OUT /GENERATE
CORRECT L....,;~--4.____.J
CEMOS and MICROSLICE are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
OSC-9017/-

1987 Integrated Device Technology. Inc.

8-235

IDT49C460/A/B 32-BIT CMOS
ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION
_0

ww

no

:>0

031
0 30
0 29
0 28
0 27
0 26
0 25
GNO
0 24
0 23
0 22
0 21
0 20
0 19
0 18
017
Vee
016
~2
LE OUT /GENERATE
CORRECT
LEDIAG
ERROR
MULT ERROR
GNO
OEse
SC7
SC6
SC5
SC4
SC3
SC 2
SCl
SC o

:::::: wIB

.

g gJ ~ l\i re di~
ao~~oouuIOooooooo~
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

olD'

Vee
O2
03
04
05
06
07
08
GNO
09
010
011
012
013
014
015

DEl

;:;~~gg~;;;

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

0 24
0 23
0 22
0 21
020
0 19
0 18
0 17
Vee
0 16

J68-1.
L68-1
&
L68-2

~

LE OUT /GENERATE
CORRECT
LEDIAG

ERROR

MULT ERROR
GNO
27 28293031 323334 353637 383940 41 4243

dlcifcifc:a c5'c5"mcO'0'6 u"'u"'u"'d'cJ'o/J

uuuuuuuu~~~~~~~~o

PLCC/LCC
TOP VIEW

SHRINK-DIP
TOP VIEW

I~ I
~

0

Wf-

CJU
W

Cl

a:
a: ffi

I~

co
~~ ~g...J
0
8 -/uS"
wOW
::> z
o~ooooooo~oo...Ju...Jffi~~
M '" _ 0
'" a:>....
"'z '" '" '" '" ___

,,0

OEse
SC7
SCs
SC 5
SC4
SC3
SC2
SC,
SCo
CBo
CB 1
CB2
CB3
CB 4
CB 5
CBs

o '" M
-">-">-"0;

DESCRIPTION

PCLK

I

Parallel Data Register Clock

EN

I

Clock Enable for PCLK (enabled
when low)

"C'CR

I

Asynchronous 16-Bit Clear (active
low)

DI 5-0

1/0

Parallel Data Register Input Pins
(Do = LSB, D15 = MSB)

YI 5-0

1/0

Parallel Data Register Output Pins
(Yo = LSB, Y15
MSB)

=

'Y'OEu. L

I

Output Enables for Y Bus (Overidden
by SPC Inst. 8 and 14)

SEL

I

Selects Between Parallel Data Register
Q or Y Bu~ for Rc~d B~ck Da.ta.

LE

I

Controls a Latch in the Read Back
Path (transparent when High)

DC:5E'

I

Output Enable for D Bus (Overidden
by SPC Inst. 9)

SDI

I

Serial Data In for SPC operation

SDO

0

Serial Data Out for SPC operation

Ci!5

I

Mode Control for SPC

SCLK

I

Shift cIcek for SPC operations

10-14

4a
45
44
43
42
41

£: Yl1
£: Yl0
£: Yg
[

r:
[

40[
39[
38[

37 [

Ya
GND
SCLK
NC
LE
GND
Y7

35 [

Y6
Y5

34[

Y4

38[

IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC TO.

TRUTH TABLE (1)
Cfi5 SCLK PCLK

MILITARY AND COMMERCIAL TEMPERATURE RANGES

m

CI:R

150E

SEL

LE

VOEU,L

D

Y

FUNCTION

X

X

X

X

X

X

X

X

H

X

High Z

X

X

X

X

L

X

X

X

H

X

L

Clear Parallel Data Register

X

X

H

H

X

X

X

L

X

NC

Hold Parallel Data Register

X

X

L

H

X

X

X

L

Input

D

Clock D-to-Y

X

X

X

X

H

L

H

H

H

Q

X

Read Back Parallel Data Register

X

X

X

X

H

L

L

H

H

Y

Input

H
L

L
X

S
S
S
X

S
S

TIi-State Y

Read Back Y Data Bus

X

X

X

X

X

X

X

X

X

Shift Bit into SPC Command
Register

X

X

X

X

X

X

X

X

X

Shift Bit into SPC Data Register

H or L
(Static)

X

X

X

X

X

X

X

X

Execute SPC Command During Time
Between C/15 & SCLK

X

X

X

L

X

L

X

X

X

Read data stored in feedback latch

NOTE:
H = HIGH Voltage Level, L= LOW Voltage Level, X= Don't Care, Z= High Impedance,

10-15

n

L

=

Low-to-High/High-to-Low Transition

IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC ™

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

MILITARY AND COMMERCIAL TEMPERATURE RANGES

-0.5 to +7.0

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

SYMBOL

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to + 125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CIN

Input Capacitance

Cva

I/O Capacitance

MAX. UNIT

CONDITIONS TYP.
VIN = OV

6

10

pF

VOUT = OV

8

12

pF

NOTE:
1. This parameter is guaranteed by characterization data and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This Is a stress rating only and functional operation of the device at these or any other
conditions above those Indicated in the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vee - 0.2V
Commercial: TA = OOC to + 70°C; 'to = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL
'-"H
'-"L
IIH

MIN.

TYP.(2)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

VI = Vee

-

-

5

VI = 2.7V

-

VI = 0.5V

-

-5(4)

VI = GND

-

-

VI = "ce

-

-

15

VI = 2.,iv

-

VI = 0.5V

-

_15(4)

VI = GND

TEST CONDITIONS(1)

PARAMETER

I~ut HIGH Current
( xcept I/O pins)

Vee = Max.
III

IIH

I~ut LOW Current

( xcept I/O pins)

Input HIGH Current
(I/O pins only)

5(4)
~A

-5

-

-

'-"K

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

-0.7

-1.2

V

los

Short Circuit Current

Vee = Max!3), Vo = GND

-60

-120

-

mA

-

Vee = Max.
III

Input LOW Current
(I/O pins only)

Output HIGH Voltage

Vee = Min.
\'IN = \'IH or\'ll

VHC

Vee

VHC

\Co

10H = -12mA MIL.

2.4

4.3

IoH = -15mA COM'L.

2.4

4.3

-

GND

VlC

GND

VLC

Iol = 24mA MIL.

-

0.3

0.5

Iol = 32mA COM'L.

-

0.3

0.5

Vee = 3V, \'IN = VlC or VHC • 10l = 300~
IoL = 3OO~A
VOL

Output LOW Voltage

Vee = Min.
\'IN = \'IH or\'ll

200
VH
Input Hysteresis on Clocks Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-16

~A

-15

IoH = -300tJ A

Vee = 3V, \'IN = VlC or VHC • IoH = -32 ~
VOH

15(4)

-

V

V

mV

IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= 0.2V; '4ic =

SYMBOL

Vee - 0.2V
TEST CONDITIONS (1)

PARAMETER
Vee = Max.

MIN.

TYP.(2)

MAX.

UNIT

Icc

Quiescent Power Supply Current

VIN ~ VHC ; "'N ~ \tc
fcp = fl = 0

-

0.001

1.5

mA

~Iee

Quiescent Power Supply Current
TTL Inputs HIGH

Vee = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

Dynamic Power Supply Current(4)

Vee= Max.
Outputs Open
?O£U.L = GND
One Input Toggling
50% Duty Cycle

\'IN ~ '4ic
\'IN ~ \tc

-

0.15

0.25

mAl
MHz

\'IN ~ VHC
\'IN ~ \tc
(FCT)

-

1.5

4.0

V IN = 3.4Vor
VIN = GND

-

2.0

6.0

ICCD

Vee = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
YOE"u. L = GND
One Bit Toggling
atf l = 5MHz

50%~~

SEL,
Ic

Total Power Supply Current(6)

cm,

,
, LE, SOl,
SCLK = Vee

Vee = Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
?O£u = GND
Sixteen~its Toggling
at~ = 2.5MHz

50l'o~C&'R

SEL,

C/r5,

,
, LE, SOl,
SCLK = Vee

mA
VIN ~ VHC
\'IN -~ VLC
(FCT)

-

6.8

12.8(5)

VIN = 3.4Vor
VIN = GND

-

11.0

29.8(5)

NOTES:
1. For 'conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the 'applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. I c = I QUIESCENT + IINPLrrS + I DYNAMIC
Ic = lee + ~Iee DH NT + iceD (fcp/2 + fl NI )
lee = Quiescent Current
~I ee = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT ;,. Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-17

/
IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC 1M

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT49FCT618
SYMBOL

CONDITION(1)

PARAMETER

COM'L
MIN.(2)

MAX.

MIN.(2)

COM'L
MAX.

T1

PCLK j toy

3.0

12.5

3.0

14.0

T2

SCLKj toSDO

3.0

12.5

3.0

14.0

T3

SDI toSDO
(in stub mode)

3.0

12.5

3.0

14.0

3.0

12.5

3.0

14.0

3.0

12.5

3.0

14.0

2.0

12.5

3.0

14.0

2.0

12.5

3.0

14.0
14.0

T4
t pLH
t pHL
T5
T6
T7

(
uL=Low
Inst. 8 &. 14)
SCLK j toY
(VO"Eu. L = High.
Inst.8)
C/O" to SDO
(Inst. 0.1.2.4)
LEto D
YtoD

2.0

12.5

SELor~toY

2.0

12.5

3.0
3.0

no

SELto 0

2.0

12.5

3.0

14.0

Sl

D to PCLK j

2.5

3.0

-

12.0

-

14.0

4.0

-

5.0

2.0

-

2.5

-

8.0

-

9.0

-

2.0

-

2.5

3.0
3.0

-

4.0
4.0
4.0

-

S2

C/15 to SCLK j

S3

SDI toSCLK j

tsu
S5

Yor D to c/o
(Inst. 0, 2 & 4)
C/l) (Low) to
PCLKj
(Inst. 3 & 13)

i

S6

Yto PCLK
(Inst.3)

S7

Yto LE

S8

SEL to LE
E'Nto PCLK

S9

PCLK i to LE
S10 (Low)

-,

CL = 50pF
RL = 500n

3.0

-

3.0

-

4.0

-

2.0

2.5
14.0

Dto PCLK i

H2

C/l) to SCLK

i

12.0

-

H3

SDI toSCLK j

1.0

-

1.0

-

2.0

-

2.5

-

2.0

-

2.5

-

2.0

-

2.5

-

3.0

-

3.0

2.0

-

2.0

2.0

-

2.0

-

2.0

-

2.0

-

H5

H6

YorDtoC/O"~

(Inst. 0, 2 & 4)
SCLK (Low) to
PCLKj
(Inst. 3 & 13)
c/l) (Low) to
PCLKj
(Inst. 3 & 13)

H7

Yto PCLK j
(Ilist. 3)

H8

Yto LE
SEL to LE

H9

MAX.

MIL
MIN.(2)

UNIT
MAX.

14.0

H1

H4

MIN.(2)

ns

~tOY

T8
T9

S4

tH

IDT49FCT618A
MIL

Hl0 E'Nto PCLK

i

ns

ns

i

(Continued)

10-18

ns

!

IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT49FCT618A

IDT49FCT618
SYMBOL

PARAMETER

COM'L

CON DITION (1)

MIN.(2)

t pHZ
tpLZ

MAX.

MINP)

MAX.

1Z

"iOEU. L toY

3.0

8.0

3.0

8.0

2Z

SCLK
to D
(Inst. 9)

3.0

9.0

3.0

9.0

3Z

C/D' PO D or Y
(Inst. 9)

3.0

9.0

3.0

9.0

4Z

SCLK
to Y
("?'OE'u. L = High
Inst. 8 & 14)

3.0

9.0

3.0

9.0

3.0

9.0

3.0

9.0

t

t

6Z
Z1

~U.L toY

Z2

C/D'! to D
(Inst. 9)

t pZH
tpZL

~tOY

CL = 50pF
RL = 500n

2.0

9.0

3.0

10.0

3.0

10.0

3.0

10.0

3.0

10.0

3.0

10.0

MAX.

MIL
MIN.(2)

UNIT
MAX.

ns
3.0

10.0

3.0

10.0

Z4

(
U L = High
Inst. 14)
"[5(5"E"toD

2.0

9.0

3.0

10.0

W1

PCLK (High & Low)

7.0

8.0

-

W2

SCLK (High & Low)

25.0

25.0

W3

CfD' (High)

25.0

-

W4

LE (High-Low)

W5

a:R (Low)

7.0
7.0

-

Z3

MIN.(2)

ns

t

C/D' to
to D or Y
("?'OE'u L = High
Inst. 14)
"[5(5"E"to D

5Z

tw

COM'L

MIL

25.0
8.0
8.0

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

10-19

-

IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

GENERAL WAVEFORMS FOR PARALLEL INPUTS AND OUTPUTS

y

__~'
__X.I-~)~I~(~----_\--®-+I---+1--

tpHL

~U_l

I ~__""' I

1-

---®iJ
tpHZ

\

~hID
tpZH

READ BACK LATCH SETUP & HOLD ITEMS

l~------~~
11
l
- - I ·;\.1'-----1

LE

~~··----~tw------~-~-·.-----~tw------~·~

y

-X
~
S7

SEL

tsu

-I-

tH

J@)

~ 'j' ~
tsu

PCLK

r

I

tH

--IT.;ij

.~

10-20

IDT49FCT618/A HIGH-SPEED 16-81T
REGISTER WITH SPCTh!

MILITARY AND COMMERCIAL TEMPERATURE RANGES

READ BACK PROPOGATION DELAYS

~ ~I------ 1
uvt:

SEL

D

_ _ _ _ _ _- - - - J

--F
~:. tH4-:'- - t~
®

I·

t pHL

t pHL

\'----

tpHZ

GENERAL WAVEFORMS FOR SERIAL PROTOCOL INPUTS AND OUTPUTS

SCLK

SDI

d

r~N~'Q---f\---r~rL.
tw

~ tsu·1· 1@.
tH

SDO

Cil)

de

H®
tP~

_ _ _ _ _ _ _ _ __ _ _

(DECODE)

~ll.

(EXECUTE)

\I~_

~.---------------~.~~
tw

10-21

IDT49FCT618/A HIGH·SPEED 16-BIT
REGISTER WITH SPC TM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED WAVEFORMS OF SERIAL PROTOCOL OPERATIONS
Y -

SPC Data (Inst. 0)

D -

SPC Data (Inst. 2)

PARALLEL DATA REGISTER -

SET STUe MODE (Inst.12)

STATUS- SPC Data (Inst. 4)

SCLK

C/[5

SPC Data (Inst. 1)

SET SERIAL MODE (Inst. 11)

SCLK

@1-fooI1--t-H~.""f---t-su--~.I®

D.Y.YOE.
PCLK

-<

c/[5

I)

SDO

®I- tsu-I-tH·1 

SPCCOMMANO
REGISTER
SOl

SOO
SPCOATA
REGISTER

SCLK

!fill

With respect to executing an SPC command, there are four dis-1lL!II
tinct phases: (1) data is shifted in, (2) followed by the SPC command, (3) the SPC command is executed, (4) data is shifted out.
During the data mode, data is simultaneously shifted into the SPC
data register while the data in the register is shifted out. During the
command mode, opcode type Information Is shifted through the
serial ports.
The command is executed when the last bit Is shifted in and the
C/O line is brought low. The execution phase is ended with the next
serial clock edge. Execution of SPC commands is p~ormed by
stopping the SPC clock, SCLK, and lowering the C/O line from
high-to-Iow. Later the SCLK may be transitioned from low-te-high.
SPC commands and data can be shifted any time without regard
for operation. During the execution phase, care must be taken that
there is no conflict between the SPC operation and parallel operation. This means that if the SPC operation attempts to load the parallel data register (opcode 10) while PCLK is in transition, the results are undefined. In general, it is required that the PCLK be static
during SPC operations. The synchronous commands (opcodes 3
and 13), however, allow the PCL~ to run. In these operations the
HIGH-te-LOW transition of the C/O line takes on the function of an
arm signal in preparation forthe next LOW-te-HIGH transition of the
PCLK.

10-23

IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Y - - . SPC Data (Inst. 0)
SDI
XFER
(EXECUTE
SPC
COMMAND)

C/[)"

SCLK

---i>

D

SERIAL
PROTOCOL

LE

SCLK

C/I)
CJ[)

SCLK
SDO
XFER

10 1

0

PARALLEL DATA REG - - . SPC Data (Inst. 1)
SDI

D

DOE'

SPC COMMANDS
There are 16 possible SPC opcodes. Thirteen of these are utilized; the other three are reserved and perform NO-OP functions.
The top eight opcodes, 0 through 7, are used for transferring data
into the SPC data register for shifting out. The lower eight opcodes,
8 through 15, are used for transferring data from the SPC data register to other parts of the device. Two of the commands are also
used for connecting the data in and out pins.

SERIAL
PROTOCOL

LE

SCLK
DATA

C/I)

COM~AND~J=~~~~~~---REGISTERS

OPCODE

0

SPCCOMMAND
Y to SPC Data Register

1

Parallel Data Register to SPC Data Register

2

D to SPC Data Register

3

Y to SPC Data Register Synchronous w/PCLK

4

Status

5-7

Y

SDO

?rn: u. L SEL

Opcode 2 transfers data which is on data input pin 0 into the
SPC data register.

(?rn: u. IJ PCLK. etc) to SPC Data Register

Reserved (NO-OP)

8

SPC Data to Y (~u, L is overidden)

9

SPC Data to D (DOE' is overidden)

10

SPC Data to Parallel Data Register

11

Select Serial Mode

12

Select Stub Mode

13

SPC Data to Y Synchronous w/PCLK

14

Connect D to Y (?O'E"u, L is overidden)

15

NO-OP

D - - . SPC Data (Inst. 2)
SDI

D

"[)'Q'E

!
SERIAL
PROTOCOL

LE

SCLK
DATA

C/D

&
COMMAND
REGISTERS

Opcode 0 is used for transferring data from the Youtput pins into
the SPC data register. Opcode 1 transfers data from 'the output of
the parallel data register into the SPC data register.

SDO

10-24

Y

?rn: u. L SEL

------------------------~.-----

IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC TOO

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Opcode 3 transfers data on the Y pins to the SPC data register
on the next PCLK, thus achieving a synchronous observation ofthe
parallel data register In real time. This operation can be fQ.l"ced to
repeat without shifting in a new command by pulsing C/D LOWHIGH-LOW after each PCLK. As soon as data is shifted out using
SCLK, the command is terminated and must be loaded in again.
Y -

STATUS SDI

SPC Data (Inst 4)
D

SERIAL
PROTOCOL

SPC Data SYNCHRONOUS w/PCLK (Inst 3)

LE

SCLK

SDI

DATA
C/[)
SERIAL
PROTOCOL

&

LK

COMMAND
REGISTERS

LE

SCLK
DATA
C/O

PCLK

&

CIJi

COMMAND

Y

SOO

~U,L SEL

REGISTERS

Opcodes 5 through 7 are reserved, hence designated NO-OP.

SPC Data -

Y ?DE" U,L SEL

SDO

SDI

Y (Inst 8)
D

Opcode 4 is used for loading status into the SPC data register.
The format of bits is shown below.
15

14

13

12

11

10

9

8

7

6

o

SERIAL
PROTOCOL

LE

SCLK
DATA

Cit)

&
COMMAND
REGISTERS

SDO

Y

?DE" U,L

SEL

Opcode 8 is used for transferring data directly to the Y pins,
When executing opcode 8, the state of YOE u, L is a don't care and
data will be output even if YOE' u, L= HIGH. Opcode 9 is used for
transferring SPC data to the D pins. Op.§rations 8 and 9 can be temporarily suspended by raising the C/D input and resumed by lowering the C/O. As soon as SCLK completes transition, the command is terminated.

10-25

IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SERIAL MODE

SPC Data - . D (Inst. 9) .
SDI

D

~

DEVICE #1

DEVICE #2

DEVICE #3

DEVICE #4

DEVICE #5

SOO

SDI

SERIAL
PROTOCOL

LE

In Stub mode, SDlls connected directly to SDO. The serial input
ofthe command register is connected to SDl.ln this way, the same
SPC command can be loaded into multiple devices of like type.
For example, in four clock cycles the same command could be
loaded into 81DT49FCT618s (128-bit pipeline register). Dissimilar
devices must be segregated into serial scan loops of similar type
as shown below (Le., other devices from IDTthat incorporate SPC).
During the command phase, the serial shift clock must be slowed
down to accommodate the delay from SDI to SDO through all of the
devices. The slower clock is typically a small tradeoff compared to
the reduced number of clock cycles.

SCLK
DATA
C/r)

&
COMMAND
REGISTERS

SDO

Y

Y'ITE U,L

SEL

STUB MODE

Opcode 10 is used for transferring data from the SPC Data register into the parallel data register, irrespective of the state of PCLK.
However, PCLK must be static between ci5 going HIGH-ta-LOW
and SCLK going LOW-ta-HIGH.

DEVICE #2

DEVICE #3

DEVICE #4

SDI--~---r---Hr---r---~--~--~~~SDO

SPC Data - . PARALLEL DATA REGISTER (Inst. 10)
SOl

D

~
SDI--~---r--~r---r---~~SDO

SERIAL
PROTOCOL

LE

SCLK
DATA

C/r)

Opcode 13 transfers data from the SPC data register to the pipeline register on the next PCLK. Opcode 14 connects the D bus to
the Y l2.us. Operation 14 can be temporarily su~ended by raising
the C/D input and resumed by lowering the C/D input again. The
operation is terminated by SCLK.

COM~ANDpq~~~~~~----REGISTERS

SDO

Y

Y'ITE U,L

SEL

Opcodes 11 and 12 are used to set Serial and Stub mode,
respectively. After executing one of these opcodes, the device remains in this mode through other Serial Protocol operations until
reprogrammed using either command. The serial mode is the default mode that the IDT49FCT618 powers up in. In Serial mode,
commands are shifted through the command register and then to
the SDO pin. This Is the typical mode used when several varieties
of devices that utilize the SPC access method are employed on
one serial ring.

10-26

IDT49FCT618/A HIGH-SPEED 16-81T
REGISTER WITH SPC™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SPC Data ... PARALLEL DATA REGISTER SYNCHRONOUS
w/PCLK (Inst. 13)
SDI

D

SERIAL
PROTOCOL

LE

SCLK
C/IT

Opcodes 3 and 13 transfer data sy~hronous to the PCLK which
means that the High-to-Low on the C/O input is an arm signal. The
data and command can be shifted in while the PCLK is running.
The ciB line is dropped prior to the desired PCLK edge and raised
afterwards, before the next edge; Instruction 13 can be repeated
many times by leaving the C/O line low during multiple transitions
of the PCLK while not clocking SCLK. PCLK cycles can even be
skipped by raising the C/O input during the desired clock periods.
Instruction 3 can be repeated by pulsing the C/O high after each
PCLK.

DATA
&
COMMAND

C/O
REGISTERS
SCLK

SDO

Y

EXECUTE
(SPCCMD)

?OE' U.L SEL

PCLK

CONNECT D TO Y (Inst.14)
SDI

D

The ability to repeatedly execute a synchronous command can
provide major benefits. For example, the synchronous read (Instruction 3, Y to SPC data) instruction could be clocked into the serial command register. Then; it could be continuously executed by
pulsing the C/O line HIGH. When the whole system is stopped
(PCLK quiescent), the serial data register will contain the next to the
last state of the parallel data register. That value can be shifted out
and the current state of the parallel data register can then be observed, allowing for the observation of two states of the parallel
data register (the current and the previous).

DOE

SCLK

CfI)

10-27

IDT49FCT618/A HIGH-SPEED 16-BIT
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TYPICAL APPLICATION
In the block diagram of the typical application, the register with
SPC register is shown being used with a writable control store in a
microprogrammed design. The control store can be initialized
through the diagnostics path. The SPC data register with SPC is
used for the instruction register going into the IOT49C410, as well
as parallel data registers around the IOT49C403. In this way, the
designer may use the SPC register to observe and modify the
microcode coming out of the writable control store, as well as observing and being able to modify data and instructions in the overall machine. The IOT49C403 is a 16-bit version of the 2903A1203
which includes an SPC port for diagnostic and break point
purposes.
The block diagram of the diagnostic ring shows how the devices
with SPC Data are hooked together in a serial ring via the SOl and
SOO signals. The SPC signals may be generated through registers
which are hooked up to a microprocessor. This microprocessor
could conceivably be an IBM PC.

As companies like lOT continue to Integrate more onto each device and put each device into smaller packages such as surface
mount devices, the board level testing becomes more complex for
the designer and the manufacturing divisions of companies. To
help this situation, SPC was invented. This allows for observation
of critical signals deep within the system. During system test when
an error is observed, these signals may be modified in order to zero
in on the fault in the system.
SPC is primarily a scheme utilizing only a few pins (4) to examine and alter the internal state of a system for the purpose of monitoring and diagnosing system faults. It can be used at many pOints
in the life of a product: design debug and verification, manufacturing test and field service. This document describes a serial diagnostic scheme which was developed at lOT and will be used in future VLSllogic devices designed by lOT.

TYPICAL MICROPROGRAM APPLICATION WITH SPC ™

SDI

SDO

IDT49C410
SEQUENCER
~

______L-________ SDO
~

IDT49C403
(w/SPC)
AlU WITH REGISTER FilE
WCS
IDT71981

SDI

SDO
SDI

SDI

ORDERING INFORMATION
IDT

xxxx

X

x

Device Type

Package

Process/
Temperature

Ran~:'~k
XC
C

+ 70°C)

l

Sidebraze Shrink-DIP
Sidebraze DIP
Plastic leaded Chip Carrier
leadless Chip Carrier

49FCT618
49FCT618A

16-Bit Register with SPC™
High-Speed 16-Bit Register with SPC™

J

L.....-----------------l

Commercial (O°C to

Military (-55°C to + 125°C)
Compliant to Mll-STD-883, Class B

10-28

FEATURES:

DESCRIPTION:

• 16-bit synchronous up/down counter, synchronously
programmable
• Maximum frequency of 50MHz commercial
• Clock to V-bus of 15ns commercial
• Both synchronous and asynchronous clear inputs
• Three-state counter outputs interface directly with busorganized systems

The IDT49FCT661 is a programmable 16-bit synchronous up/
down binary counter which is conveniently organized for operation
in a standalone configuration, as well as interfaced with a processor. All operations except latch, output enable and asynchronous
clear happen on the rising edge of the Clock Input (CP).
With a LOAD input LOW, the counter will load the value at the
output of the input latch. The input latch is transparent when LE is
LOW, allowing for easy connection to processor address decode
and strobe logic. The D-Bus Output Enable, (OEo) is used for reading back the state of the counter in processor-based applications.
When OEo is LOW, the latch is closed and the D bus is driven with
the contents of the latch; otherwise the oLtput buffer is in a highimpedance state when OEo is HIGH. Counting is enabled only
when CEI" and CE T are LOW and LOAD is HIGH. The Up/Down
Input, (UfO), controls direction of the count. Internal ca.!!YJookahead logic and an active LOW on Ripple Carry Outp.!:!!JBCO} allow for counting and cascading. During up-count, the RCO is LOW
at binary 65K and upon down-count is LOW at binary O. Normal
cascade operations ~uire only the RCO to be connected to the
succeeding block at CET • When counting, the Clock Carry Output
(CCO) provides a HIGH-LOW-HIGH pulse for a duration equal to
the clock LOWtime of the input clock only when RCO is LOW. Two
active LOW resets are available: synchronous clear (SC~ and
Master Asynchronous Clear (ACLR). The output control (OEy) input forces the output to high impedance when LOW, otherwise the
V-bus reflects the output of the counter.

• Ripple carry output for cascading
• Clocked carry output for convenient modulo configuration
• Latched inputs provide for modulo load function or interface to a
processor
• Latched readback path for interface to a processor
•
10L = 48mA commercial and 32mA military
• CMOS power levels (5',JW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Available in 48-pin Shrink-DIP, 52-pin PLCC and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
D

UfD
LOAD

Up
CE T

16-SIT
SYNCHRONOUS
COUNTER

CP

Vee
GND

Y

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
OSC-4oo1/-

1987 Integrated Oevlce Technology. Inc.

10-29

FEATURES:

DESCRIPTION:

• High-speed, non-inverting 8-bit parallel register for any data
path, control path or pipelining application
• . New, unique command capability which allows for multiplicity
of diagnostic functions
• High-speed Serial Protocol Channel (SPC ™ ) provides
- Controllability:
- Serial scan in new machine state
- Load new machine state "on the fly"
- Temporarily force Y output bus
- Temporarily force data out the D input bus (as in loading
WCS)
- Observability:
- Direct observe 0 and Y buses
- Serial scan out current machine state
- Capture machine state "on the fly"
• IOL = 32mA (commercial) and 24mA (military)
• CMOS power levels (5jJW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than 29818 and
54/74AS818 (5jJA max.)
• Available in plastic and sidebraze DIP, PLCC and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class 8

The IDT49FCT818 is a high-speed, general purpose octal register with Serial Protocol Channel (SPC). The D-to-Y path of the octal
register provides a data path that is designed for normal system operation wherever a high-speed clocked register is required.
The SPC command and data registers are used to observe and
control the octal data register for diagnostic purposes. The SPC
command and data registers can be accessed while the system,is
performing normal system function. Diagnostic operations then
can be performed "on the fly", synchronous with the system clock,
or can be performed in the "single step" environment. The SPC
port utilizes serial data in and out pins (a concept originated at 18M)
which can participate in a serial scan loop throughout the system.
Here normal data, address, status and control registers are replaced with the IDT49FCT818. The loop can be used to scan in a
complete test routine starting point (data, address, etc). Then, after
a specified number of clock cycles, the data can be clocked out
and compared with expected results.
As well as diagnostic operations, SPC can be used for initializing at power-on time functions such as Writable Control Store
(WCS).

FUNCTIONAL BLOCK DIAGRAM
SDI

~-O

SCLK

Cj[)

SERIAL
PROTOCOL
DATA
AND
COMMAND
REGISTERS

PARALLEL
DATA REGISTER

PCLK

~y

SDO

CEMOS and SPC are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

10-30

DECEMBER 1987
DSC-4003/-

IDT49FCT818/A/B HIGH-SPEED OCTAL
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
~y

SCLK

~ >010
... O~O 0-'"
O(/)lQz>O>-

INDEX

Vee
C!D

UULJ;;UUU

4 3 2 LJ 282726

Y7

D7
D6

D6 :] s

Y6

Ds
D3

Ys
Y4
Y3

D2
D1

Y2
Y1

D4

Do
SDI

Ds

:Je

D4
NC

:] 8

D3

:] 9

L28-1

D2 :] 10
D1 :] 11

Yo
SDO

GND

:J7

2S[
24[

Y6
YS

23[

Y4

22[

NC

21[
20[

Y3
Y2 -

19[

Y1

12 13 14 1S 16 17 18

nnnnnnn

PCLK

O-OO~O~

O@zZd o
(!)

DIP/SOIC/CERPACK
TOP VIEW

a.(/)

lCC
TOP VIEW

TRUTH TABLE (1)

LOGIC SYMBOL

SDI

C/O

SClK

PClK

OEy

D

X

X

X

H

X

X

X

L

H

H

Clock D toY

X

X

L

L

L

Clock D toY

SDO

SCLK

PCLK

C/L>

O1: y

S
S

Y

FUNCTION

High Z Tri-state Y

H

S

X

X

X

X

Shift bit into SPC
Command register

L

S

X

X

X

X

Shift bit into SPC Data
register

L

S

H or L
(Static)

X

X

X

Execute SPC command
during time between
C/O & SCLK

NOTE:
H
HIGH Voltage Level

L

LOW Voltage Level

X

Don't Care

Z

High Impedance

L S

=

Transition, H to Lor L to H

PIN DESCRIPTION
PIN NAME

I/O

DESCRIPTION

PCLK

I

D 7- 0

1/0

Y7-Q

1/0

Parallel Data Register Output Pins (Yo = LSB, Y7 = MSB)

OEy

I

Output Enable for Y Bus (Overidden by SPC Inst. 8 & 14)

Parallel Data Register Clock
Parallel Data Register Input Pins (Do = LSB, D7 = MSB)

SDI

I

Serial Data In for SPC Operation. Data and command shifts in the Least Significant Bit first

SDO

0

Serial Data Out for SPC Operation. Data and command shifts out the Least Significant Bit first

C/O

I

Mode Control for SPC

SCLK

I

Serial Shift Clock for SPC Operations

10-31

IDT49FCT818/A/B HIGH-SPEED OCTAL
REGISTER WITH SPC ™

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

MILITARY AND COMMERCIAL TEMPERATURE RANGES

-0.5 to +7.0

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

SYMBOL

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to + 125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

CIN

Input Capacitance

CliO

I/O Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VoUT = OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress ratIng only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; 'tc = 5.0V±5%
Military: TA = -55°C to +125°C; Vee = 5.0V±10%
SYMBOL
"'H
"'L
IIH

MIN.

TYP,!2)

Input HIGH Level

Guaranteed Logic High Level

2.0

Input LOW Level

Guaranteed Logic Low Level

-

TEST CONDITIONS(l)

PARAMETER

I~ut HIGH Current
( xcept I/O pins)

MAX,

UNIT

-

-

V

0.8

V

VI = Vee

-

-

VI = 2.7V

-

-

5(4)

= 0.5V

-

-

-5(4)

VI = GND

-

VI = Vce

-

15

VI = 2.7V

Vec = Max.
IlL

IIH

VI

I~ut LOW Current

( xcept I/O pins)

Infcut HIGH Current
(I 0 pins only)
Vcc = Max.

IlL

"'K
los

VOH

Infcut LOW Current
(I 0 pins only)

-

VI = 0.5V

-

-

= GND

-

-15

-0.7

-1.2

V
mA

-5

15(4)
_15(4)

Vee = Min., IN = -18mA

-

Short Circuit Current

Vcc = Max!3), Vo = GND

-60

-120

-

Vcc = 3V, \'IN = VLC or VHC ' 10H = -32jJA

VHC

Vcc

-

ICH = -300jJA

VHe

Vcc

-

= -12mA MIL.
10H = -15mA COM'L.
or VHC ' 10L = 300jJA
10L = 300jJA

2.4

4.3

-

Output HIGH Voltage

VI

Vcc = Min.
\'IN = \'IH or\'lL

Output LOW Voltage

10H

= VLC

Vcc = Min.
VIN = \'IHor\'lL

10L = 24mA MIL.
10L

= 32mA COM'L.

2.4

4.3

-

-

GND

VLC

-

GND

VLC

-

0.3

0.5

-

0.3

0.5

VH
200
Input Hysteresis on Clocks Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. .
4. This parameter is guaranteed but not tested.

10-32

jJA

-

Clamp Diode Voltage

Vcc = 3V, \'IN
VOL

5

-

jJA

V

V

mV

IDT49FCT818/A/B HIGH-SPEED OCTAL
REGISTER WITH SPC™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~VHC; "IN
fcp= fl = 0

~Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
~Y = GND
One Input Toggling
50% Duty Cycle

ICCD

Ic

Total Power Supply Current

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

"IN ~ VHC
"IN :s VLC

-

0.15

0.25

"IN ~ VHC
"IN :s VLC
(FCT)

-

1.5

4.0

VIN = 3.4V
VIN = GND

-

2.0

6.0

TEST CONDITIONS (1)

PARAMETER

(6)

:s

VLC

Vcc= Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
OEy = GND
One Bit Toggling
atf l = 5MHz
50% Duty C'ycle
SCLK = C/D =
SDI = Vcc
Vcc= Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
OEy = GND
Eight Bits Toggling
atf l = 5MHz
50% Duty c~cle
SCLK = C/ =
SDI = Vcc

MIN.

mAl

mA
\'IN ~ VHC
\'IN :s VLC
(FCT)

-

3.75

7.s(5)

VIN = 3.4V
VIN = GND

-

6.0

16.S(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable. but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

+

10-33

MHz

IDT49FCT818/A/B HIGH-SPEED OCTAL
REGISTER WITH SPC Thl

MILITARV AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT49FCT818A

IDT49FCT818
SYMBOL

CONDITION(1)

PARAMETER

MIL

COM'L

COM'L

IDT49FCT818B

MIL

COM'L

MIL

UNIT

MIN!2) MAX. MIN!2) MAX. MIN!2) MAX. MIN!2) MAX. MIN!2) MAX. MIN!2) MAX.

t pHL
tpLH

T1

PCLK t to Y

3.0

12.5

3.0

14.0

3.0

10.0

3.0

11.0

T2

SCLK t to SDO

3.0

12.5

3.0

14.0

3.0

10.0

3.0

11.0

-

-

-

-

T3

SDI toSDO
(in stub mode)

3.0

12.5

3.0

14.0

3.0

10.0

3.0

11.0

-

-

-.

-

C/D! toY
T4

(DEy = Low
Inst. 8 & 14)

3.0

12.5

3.0

14.0

3.0

10.0

3.0

11.0

-

-

-

-

T5

SCLK t toV
(OEy = High,
Inst. 8)

3.0

12.5

3.0

14.0

3.0

10.0

3.0

11.0

-

-

-

-

-

-

-

-

-

-

T6

C/D to SDO

3.0

12.5

3.0

14.0

3.0

10.0

3.0

11.0

-

S1

D to PCLK t

2.5

3.0

2.5

-

cm toSCLK t

12.0

-

3.0

S2

-

S3

SDI toSCLK t

4.0

S4

YorDtoC/D!
(Inst. 0, 2 & 4)

tsu

(Inst. 0,1,2 & 4)

S5
S6

Vto PCLK t
(Inst. 3)

t pZH
t pZL

-

-

2.5

-

-

-

8.0

-

9.0

-

-

-

-

-

2.0

-

2.5

-

-

-

-

-

5.0

2.0

-

2.5

8.0

-

9.0

2.0

-

2.5

14.0

H1

Dto PCLKt

2.0

-

2.5

H2

C/D to SCLK t

12.0

14.0

H3

SDI toSCLK t

1.0

-

1.0

H4

Vor D to C/D!
(Inst. 0, 2 & 4)

2.0

-

2.5

2.0

-

2.0

-

H5

SCLK (Low) to
PCLKt
(Inst. 3 & 13)
C/[5 (Low) to
PCLK t
(Inst. 3 & 13)

CL = 50pF
RL = soon·

-

12.0
4.0

-

ns

ns

2.0

-

2.5

-

-

-

14.0

-

-

-

1.0

-

1.0

-

-

-

12.0

-

-

-

-

2.0

-

2.5

-

-

-

-

...:.

2.5

-

2.0

-

2.5

-

-

-

-

-

2.5

-

2.0

-

2.5

-

-

-

-

-

-

H7

Yto PCLK t
(Inst. 3)

3.0

-

3.0

-

3.0

-

3.0

-

1Z

OEy toV

3.0

8.0

3.0

8.0

3.0

8.0

3.0

8.0

-

-

-

-

2Z

SCLK t to D
(Inst. 5 & 9)

3.0

9.0

3.0

9.0

3.0

9.0

3.0

9.0

-

-

-

-

3Z

C/DttoDorY
(Inst. 5 & 9)

3.0

9.0

3.0

9.0

3.0

9.0

3.0

9.0

-

-

-

-

4Z

SCLK t to Y
(OEy = High
Inst. 8 & 14)

3.0

9.0

3.0

9.0

3.0

9.0

3.0

9.0

-

-

-

-

5Z

CLQ to t to D or Y
(OEy = High
Inst. 14)

3.0

9.0

3.0

9.0

3.0

9.0

3.0

9.0

-

-

-

-

ns

-

ns

Z1

OEy to Y

3.0

10.0

3.0

10.0

3.0

10.0

3.0

10.0

-

-

-

-

Z2

C/D!toD
(Inst. 5 & 9)

3.0

10.0

3.0

10.0

3.0

10.0

3.0

10.0

-

-

-

ns

C/[5 ! to V

Z3

tw

5.0

2.0

-

-

-

H6

t pHZ
tpLZ

PCLKt
(Inst. 3 & 13)

14.0

-

-

C/[5 (Low) to

tH

-

(OEy = High
Inst. 14)

3.0

10.0

3.0

10.0

3.0

10.0

3.0

10.0

-

-

-

-

-

8.0
25

-

7.0
25

-

8.0

-

25

-

-

-

-

-

W1

PCLK (High & Low)

7.0

W2

SCLK (High & Low)

25

W3

C/I) (High)

25

25

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
10-34

25

25

-

ns

IDT49FCT818/A/B HIGH-SPEED OCTAL
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

GENERAL AC WAVEFORMS FOR PARALLEL INPUTS AND,OUTPUTS

,'PCLK

D

y

GENERAL AC WAVEFORMS FOR SERIAL PROTOCOL INPUTS AND OUTPUTS

SCLK

SDI

SDO

C/D

'

---------1
..

\I~-

~.---------------~~Q§D
1
tw

10-35

IDT49FCT818/A/B HIGH-SPEED OCTAL
REGISTER WITH SPC ™

MILITARV AND COMMERCIAL TEMPERATURE RANGES

DETAILED WAVEFORMS OF SERIAL PROTOCOL OPERATIONS

v-

SPC Data (Inst. 0)

D -

SPC Data (Inst. 2)

SET SERIAL MODE (Inst. 11)

Status -

SPC Data (Inst. 4)

SET STUB MODE (Inst. 12)

PARALLEL DATA REGISTER -

SCLK

D,

SPC Data (Inst. 1)

SCLK

v,m,

PCLK

SDO

SPC Data CONNECT Y TO D (Inst. 5)
SPC Data -

SPC Data -

PARALLEL DATA REGISTER (Inst. 10)
Y (Inst. 8)

CONNECT D TO Y (Inst. 14)

D (Inst. 9)

SCLK

SCLK

I
C/D

I·

tH

l@

D

I

7l7W WZZZ

r

I

Y

t pZH
t pLZ

v -

C/D"

t'~:1 ag
SPC Data -

SPC Data ,SYNCHRONOUS W/PCLK (Inst. 3)

SCLK

SCLK

CiF5

CiD

PCLK

PCLK

Y

10-36

PARALLEL DATA REGISTER SYNCHRONOUS
W/PCLK (Inst. 13)

IDT49FCT818/A/B HIGH-SPEED OCTAL
M
REGISTER WITH SPC·

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DETAILED FUNCTIONAL BLOCK DIAGRAM
SDI
r--1

-----------------------------,
SERIAL PROTOCOL COMMAND & DATA REGISTERS
I

I
I

1

1

I

D

1

1
1

Cfi)

I
I

SCLK

L ___________________ _

y

SDO

register is used to control loading of data to and from the data register with other storage elements in the device.
With respect to executing an SPC command, there are four distinct phases: (1) data is shifted in, (2) followed by the command, (3)
the command is executed, and (4) data is shifted out. During the
data mode, data is si multaneously shifted into the serial data register while the data in the register is shifted out. During the command
mode, opcode-type information is shifted through the serial ports.
The command is executed when the last bit is shifted in and the
C/O line is brought low. The execution phase is ended with the next
serial clock edge.
~

The detailed block diagram consists of two main elements: the
parallel data register and the SPC data/command registers. The
main data path is from the 0 inputs down to the data register and
through to the Y outputs. This path is typically used during standard operations. For diagnostic or systems initialization, the internal SPC data path is used. This path allows access between the
SPC data and command registers and the standard data path, pins
and data register. The SPC data and command registers are accessed via the SOl, SOD, ci5 and SCLK pins.

rTiJI

C/O

SPCCOMMAND
REGISTER

XFER
(EXECUTE
SPC
COMMAND)

C/O
SDO

SOl
SPCDATA
REGISTER

SCLK

----I~

SCLK
C/O

SPC FUNCTIONAL DESCRIPTION
SCLK

The Serial Protocol Channel (SPC) has been optimized for the
minimum number of pins and the maximum flexibility. The data is
passed in on a Serial Data Input pin (SOl) and out on a Serial Data
Output pin (SOD). The transfer of the data is controlled by a Serial
Clock (SCLK) and a Command/Data mode input (C/O). These four
pins are the basic SPC pins. To the outside, the SPC appears as
two serial shift registers in parallel- one for command and the
other data. The serial clock shifts data and the Command/Data
(C/O) line selects which register is being shifted. The command

XFER

CD 10 0
1

10-37

IDT49FCT8181A1B HIGH-SPEED OCTAL
REGISTER WITH SPCTM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SPC data and commands are shifted in through the SOl pin,
which is a serial input pin, and out through the SOO pin, which is a
serial output pin. Data and commands are shifted in Least Significant Bitfirst; Most Significant Bit last (Yo = LSB, Y15 = MSB). Execution of SPC commands is performed by stopping the shift clock,
SCLK, and lowering the ci5 line from high-te-Iow. Later the SCLK
may then be transitioned from low-to-high. SPC commands and
data can be shifted anytime, without regard for operation. During
the execution phase, care must be taken that there is no conflict
between the SPC operation and parallel operation. This means that
if the SPC operation attempts to load the parallel data register (opcode 10) while PCLK is in transition, the results are undefined. In
general, it is required that the PCLK be static during SPC operations. The synchronous commands (opcode 3 and 13), however,
allow the PCLK to run. In these operations, the high-to-Iow transition of the ci5 line takes on the function of an arm signal in preparation for the next low-to-high transition of the PCLK.

SDI

SERIAL
PROTOCOL
SCLK
C/l5

SDI

~

SPC Data (Insll)
D

SERIAL
PROTOCOL

Parallel Data Register to SPC Data Register

4

Status (~y. PCLK) to SPC Data Register

5

Connect Y to D

8

Data Register

Y to SPC Data Register

Y to SPC Data Register Synchronous w/PCLK

9

Y

SPCCOMMAND

2
3

6-7

PCLK

SDO

There are 16 possible SPC opcodes. Fourteen of these are utilized, the other two are reserved and perform NO-OP functions. The
top eight opcodes, 0 through 7, are reserved for transferring data
into theSPC data reg ister for shifting out. The lower eight opcodes,
8 through 15, are used for transferring data from the SPC data register to other parts of the device. Two of the commands are also
used for connecting the data in and out pins.

0
1

DATA
&
COMMAND

'O-----~y

SPC COMMANDS

OPCODE

Y ~ SPC Data (Insl 0)
D

D to SPC Data Register

SCLK
C/l5

Reserved (NO-OP)

DATA
&
COMMAND

PCLK

REGISTERS

OEy

SPC Data to Y (~ is overidden)
SPC Data to D

10

SPC Data to Parallel Data Register

11
12

Select Serial Mode
Select Stub Mode

13

SPC Data to Parallel Data Register Synchronous
w/PCLK

14

Connect D to Y (OE is overidden)

15

NO-OP

SDO

Y

D ~ SPC Data (Inst. 2)
SDI

Opcode 0 is used for transferring data from the Y output pins into
the SPC data register. Opcode 1 transfers data from the output of
the register, before the tri-state gate, into the SPC data register.
Opcode 2 transfers data from the 0 input pins into the SPC data
register.

D

SERIAL
PROTOCOL'
SCLK
C/l5

DATA
&
COMMAND

PCLK

-c>-----OEy

REGISTERS

SDO

10-38

Y

IDT49FCT8181A1B HIGH-SPEED OCTAL
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Opcode 5 connects Y to D. Opcodes 6 and 7 are reserved,
hence designated NO-OP.

Opcode 3 transfers data on the Y pins to the SPC data register
on the next PCLK, thus achieving a synchronous observation of the
SPC data register in real time. This operation can be forced to repeat without shifting in a new command by pulsing ci510w-highlow after each PCLK. As soon as data is shifted out using SCLK, the
command is terminated and must be loaded in again.

Connect Y to D (Inst 5)
SDI

SERIAL
PROTOCOL

Y -+ SPC Data Synchronous w/PCLK (Inst. 3)
SDI

D

SCLK

D

Cio
SERIAL
PROTOCOL

DATA
&
COMMAND

PCLK

REGISTERS

OE"y

SCLK

C!D

DATA
&
COMMAND

Y

SDO

REGISTERS
SPC Data -+ Y (Inst 8)
SDI

SDO

D

Y
SERIAL
PROTOCOL
SCLK
PCLK

DATA
C/O

Opcode 4 is used for loading status into the SPC data register.
The format of bits is shown below.

&
COMMAND

Ll----- O!:y

REGISTERS

SDO

Y

Opcode 8 is used for transferring SPC data directly to the Ypins.
When executing opcode 8, the state of OE y is a "do not care"; that
is, data will be output even if OE y = HIGH. Opcode 9 is used for
transferring SPC data to the D pins. Qperands 8 and 9 can be temporarily suspended by raising the C/D input and resumed by lowering the cffJ. As soon as SCLK completes transition, the command is terminated.
Status -+ SPC Data (Inst. 4)
SDI

SPC Data -+ D (Inst 9)
D
SDI

SERIAL
PROTOCOL

SERIAL
PROTOCOL

SCLK

SCLK
PCLK

DATA
C/15

C/I)

UEy

SDO

PCLK

DATA

&
COMMAND

&
COMMAND

UEy

REGISTERS

Y

SDO

10-39

Y

IDT49FCT818/A/B HIGH-SPEED OCTAL
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Opcode 10 is used for transferring data from the SPC data register into the parallel data register, irrespective of the state of PCLK.
However, PCLK must be static between C/O going high-to-Iow and
SCLK going low-to-high.

STUB MODE
DEVICE #2

DEVICE #3

DEVICE #4

SDI-;---.---41---,---+~--,---T-~SDO

SPC Data -+ Parallel Data Register (Inst. 10)

D

SDI

SDI--t---.....----t-t-----...---t-- SDO
SERIAL
PROTOCOL
SCLK

C/D

DATA
&
COMMAND

PCLK

.1./'------.-----'

Opcode 13 transfers data from the SPC data register to the parallel data register on the next PCLK. Opcode 14 connects the D bus
to the Y. Operation 14 can be temporarily suspended by raising the
C/O input and resumed by lowering the C/O input again. The operation is terminated by SCLK.

L'}-----~y

REGISTERS

SPC Data -+ Parallel Data Register Synchronous w/PCLK (Inst. 13)
SDO

Y

D

SDI

Opcodes 11 and 12 are used to set Serial and Stub Mode, respectively. After executing one of these opcodes, the device remains in this mode until programmed otherwise. The Serial mode
is the default mode that the IDT49FCT818 powers up in. In Serial
mode, commands are shifted through the SPC command register
and then to the SDO pin. This is the typical mode used when several varieties of devices that utilize the SPC access method are employed on one serial ring.

SERIAL
PROTOCOL
SCLK
C/D

SERIAL MODE

DEVICE #1
501

DEVICE #2

DEVICE #3

DEVICE #4

PCLK

DATA
&
COMMAND
REGISTERS

DEVICE #5

SDO

SDO.

In Stub mode, SOl is connected directly to SDO. In this way, the
same diagnostic command can be loaded into multiple devices of
like type. For example, in four clock cycles the same command
could be loaded into 8 IDT49FCT818s (64-bit pipeline register).
Dissimilar devices must be segregated into serial scan loops of
similar type, as shown below. During the command phase, the serial shift clock must be slowed down to accommodate the delay
from SOl to SDO through all of the devices. The slower clock is typically a small tradeoff compared to the reduced number of clock
cycles.

Y

Connect D to Y (Inst. 14)
SDI

D

SERIAL
PROTOCOL
SCLK
PCLK

DATA

C/r5

&
COMMAND
REGISTERS

10-40

.6--------

~y

------------------------

.-~-.---.-.-.-----------------------.

IDT49FCT818/A/B HIGH-SPEED OCTAL
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Opcodes 3 and 13 transfer data synchronous to the PCLK which
means that the high-to-Iow on the C/O input is an arm signal. The
data and command can be shifted in while the PCLK is running.
The C/O line is dropped prior to the desired PCLK edgeand raised
before the next edge. Instruction 13 can be repeated over many
ti mes by leaving the C/O line low during multiple transitions of the
PCLK while not clocking SCLK. PCLK cycles can even be skipped
by raising the C/O input during the desired clock periods. Instruction 3 can be repeated by pulsing the C/O high after each PCLK.

The ability to continuously execute a synchronous command
can provide major benefits. For example, the synchronous read
(Instruction 3, Y to SPC data) instruction could be clocked into the
SPC data register. Then, it could be continuously executed by
pulsing the C/O line high. When the whole system is stopped
(PCLK quiescent), the serial data register will contain the next to the
last state of the parallel data register. That value can be shifted out
and the current state of the parallel register can then be observed,
allowing for the observation of two states of the parallel register (the
current and the previous).

TYPICAL APPLICATION
In the block diagram of the typical application, the SPC data
register is shown being used with a writable control store in a
microprogrammed design. The control store can be initialized
through the diagnostics path. The SPC data register is used for the
instruction register going into the IOT49C410, as well as for data
registers around the IOT49C403.ln this way, the designer may use
the SPC data register to observe and modify the microcode coming out of the writable control store, as we II as observing and being
able to modify data and instructions in the overall machine. The
lOT49C403 is a 16-bit version of the 2903A/203 which includes an
SPC port for diagnostic and break point purposes.
The block diagram of the diagnostics ring shows how devices
with diagnostics are hooked together in a serial ring via the SOl and
SOO signals, The diagnostics signals may be generated through
registers which are hooked up to a microprocessor. This microprocessor could conceivably be an IBM PC.

C/D

SCLK

EXECUTE
(SPC CMO)

PCLK

TYPICAL MICROPROGRAM APPLICATION WITH SPC ™

--1

~
IR
(REG w/SPC)
49FCT818

SOl

SOD

I

I

1

OATAIN
(REG w/SPC)
49FCT818

rl

IOT49C410
SEQUENCER

SO D

!

IOT49C403

r---.

ALU WIT

~W/SPCJ

.
REGI TER FILE

WCS
10171981

SOD

SOl

-

S01

!

PIPELINE REG

(R4~~C.f~f8C)

SOD

SOl

I

I

I

10-41

OATAouT
(REG w/SPC)
49FCT818

~

froD

IDT49FCT818/A/B HIGH-SPEED OCTAL
REGISTER WITH SPC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

As companies like IOT continue to integrate more onto each device and put each device into smaller packages such as surface
mount devices, the board level testing becomes more complex for
the designer and the manufacturing divisions of companies. To
help this situation, serial diagnostics was invented. This allows for
observation of critical signals deep within the system. Ouring system test, when an error is observed, these signals may be modified
in order to zero in on the fault in the system.

Serial diagnostics is primarily a scheme utilizing onlya few pins
(4) to examine and alter the internal state of a system for the purpose of monitoring and diagnosing system faults. It can be used at
many points in the life of a product: design debug and verification,
manufacturing test and field service. This document describesa
serial diagnostic scheme which was developed at lOT and will be
used in future VLSllogic devices designed by lOT.

ORDERING INFORMATION

IDT

XXX)(

Device Type

Commercial (O°C to .+ 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

'--------------------1

10-42

P
C
E
L

so

Plastic DIP
Sidebraze DIP
CERPACK
Leadless Chip Carrier
Small Outline IC

49FCT818
49FCT818A
49FCT818B

Octal Register with SPC ™
High-Speed Octal Register with SPC ™
High-Speed Octal Register with SPC ™

FEATURES:

DESCRIPTION:

• IDT54/74FCT138 equivalent to FAST™speed;
IDT54/74FCT138A 35% faster than FAST 1M

The IDT54/74FCT138 and IDT54/74FCT138A are 1-of-8 decoders built using advanced CEMOS T~ a dual metal CMOS technology. The IDT54/74FCT138 and IDT54/74FCT138A accept three binary weighted inputs (Ao. Al. Az) and. when enabled. provide eight
mutually exclusive active LOW outputs (00 -0,). The
IDT54/74FCT138 and IDT54/74FCT138A feature three enable inputs. two active LOW (El • Ez) and one active HIGH (E3). All outputs
will be HIGH unless El and Ez are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to
a 1-of-32 (5 lines to 32 lines). decoder with just four
IDT54/74FCT138 or IDT54/74FCT138A devices and one inverter.

• Equivalent to FAST ™speeds and output drive over full
temperature and voltage supply extremes

= 48mA (commercial) and 32mA (military)

•

10L

•
•
•
•
•
•
•
•
•

CMOS power levels (5J.1W typo static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST ™(5J.1A max.)
1-of-8 decoder with enables
JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Enhanced versions
Military product compliant to MIL-STD-883. Class B
Standard Military Drawing# 5962-87654 is listed on this
function. Refer to Section 21page 2-4.

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM

Ao
Al

Vcc

Az

00
01

~1
~z

03

E3

04

Oz

07

05

GND

06
DIP/SOIC/CERPACK
TOP VIEW

INDEX

-i

00

~

z

J3 10

A2

UUIIULJ
3 z U 20 19
1
]4
16 [:

~1

:J

NC

01

17e: Oz

5

]6

L20-2

1:"2 ]7
E3 :J 6

16 [:

NC

15[:

03
04

14 [:
9 10 11 12 13

nnnnn
... 0

o

co

III

10 (!l
z z 10 10
LCC
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-4005/-

10-43

IDT54/74FCT138/A FAST
CMOS 1·0F·8 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

COMMERCIAL

CAPACITANCE
MILITARY

SYMBOL

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

CIN

(TA =+25°C, f = 1.0MHz)

PARAMETER(l)
Input Capacitance

CONDITIONS TYP,
VIN = OV

MAX, UNIT

6

10
pF
COUT
Output Capacitance
VOUT= OV
8
12
pF
NOTE:
1. This parameter is guaranteed by characterization data and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = O.2V; VHC = - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V ±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V ±10%
SYMBOL

TEST CONDITIONS(l)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

~H

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

~L

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

-

-

5

-

5(4)

-

-

-5(4)

-

-

-5

-0.7

-1.2

V

-60

-120

-

mA

= VLC or VHC ' 10H = -32 jJA

VHC

Vcc

-

-300~A

VHC

\bc

2.4

4.3

VI
IIH

Input HIGH Current
Vee

VI

=

Max.

=

Min., IN

VI

IlL

Input LOW Current

~K

Clamp Diode Voltage

Vec

los

Short Circuit Current

Vec = MaxP), Vo = GND

VI

Vcc
VOH

Output LOW Voltage

= 3V, ~N

= -18mA

10H

Vcc = Min.
"iN = "iH or"iL

VOL

Output HIGH Voltage

Vcc
"iN

=

10H = -12mA MIL.

= 3V, ~N = VLC

2.4

4.3

-

-

GND

VLC

=

-

GND

VLC

-

0.3

0.5

-

0.3

0.5

10L

= Min.
= "iH or"iL

=

-15mA COM'L.

300~A

10L = 32mA MIL.
10L

=

48mA COM'L.

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-44

-

or VHC ' 10L = 300jJA

10H
Vcc

= Vcc
= 2.7V
= 0.5V
= GND

~A

V

V

IDT54/74FCT138/A FAST
CMOS 1-0F-S DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

TEST CONDITIONS

PARAMETER

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC ; VIN ~ VLC
fl = 0

~Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current (4)

Vcc= Max.
Outputs Open
One Input Toggling
50% Duty Cycle

VCC = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
One Input Toggling

Ic

Total Power Supply Current

TYP.(2)

MAX.

UNIT

0.001

1.5

mA

-

0.5

2.0

mA

-

0.15

0.3

mAl
MHz

"iN ~ VHC
"iN ~ VLC
(FCT)

-

1.5

4.5

VIN = 3.4V
VIN = GND

-

1.8

5.5

(1)

"iN ~ VHC
"iN ~ VLC

MIN.

-

(6)

Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
One Input Toggling

VIN ~ VHC
VIN ~ VLC
(FCT)

VIN = 3.4V

mA

-

0.38

2.3(5)

-

0.63

3.3(5)

VIN = GND
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25 0 C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-45

IDT54/74FCT138/A FAST
CMOS 1-0F-8 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION

PIN NAMES
Address Inputs

Ao - A2

E1 ,E 2

Enable Inputs (Active LOW)

E3

Enable Input (Active HIGH)

00 - 0 7

Outputs (Active LOW)

TRUTH TABLE
OUTPUTS

INPUTS
El

~

E3

Ao

Al

A2

00

01

O2

03

04

05

06

07

H
X
X

X
H
X

X
X
L

X
X
X

X
X
X

X
X
X

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

L
L
L
L

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT138
SYMBOL

PARAMETER

tpLH
tpHL

PropagatiolJ.. Delay
Ao to On

tpLH
tpHL

Prppaga]on ~elay
El or E 2to On

tpLH
tpHL

Propagatio!}, Delay
E3 to On

CONDITION (1)

CL = 50pF
RL = 5000

TYp~3)

COM'L,
MIN.(2) MAX.

IDT54/74FCT138A
MIL.

MIN!2)

MAX.

TYP.(3)

COM'L.
MIN,(2)

MIL.

MAX.

MIN.(2)

UNIT

MAX.

7.0

1.5

9.0

1.5

12.0

4.5

1.5

5.8

1.5

7.8

. ns

6.0

1.5

9.0

1.5

12.5

4.5

1.5

5.9

1.5

8.0

ns

6.0

1.5

9.0

1.5

12.5

4.5

1.5

5.9

1.5

8.0

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.

10-46

IDT54/74FCT138/A FAST
CMOS 1-0F-8 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type.

X
Package
Commercial
MIL-STD-883, Class B

L...-----------J

10-47

P
D
SO
E
L

Plastic DIP
CERDIP
Small Outline IC
CERPACK
Leadless Chip Carrier

138
138A

1-of-8 Decoder
Fast 1-of-8 Decoder

FEATURES:

DESCRIPTION:

• IDTS4/74FCT139 equivalent to FAST™speed;
IDT54/74FCT139A 35% faster than FAST ™
II Equivalent to FAST ™output drive over full temperature and
voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (SjJW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™(SJ.lA max.)
• Dual 1-of-4 decoder with enable
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDTS4/74FCT139 and IDTS4/74FCT139A are dual 1-of-4
decoders built using advanced CEMOS TM, a dual metal CMOS
technology. The devices have two independent decoders, each of
which accept two binary weighted inputs (Ao-Al) and provide four
mutually exclusive active LQ.W output~ (00 -(3). Each decoder
has an active LOW enable (E). When E is HIGH, all outputs are
forced HIGH.

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM

DIP/SOIC/CERPACK
TOP VIEW

g

INDEX

~

to

Iw

1'1 I
L.J L..I

3

:J
:J

2

0

z

I

I

0

~1Uf

1'1

U

I

L...I

I

I

L.J

20 19

1

18 [:

AOb

17 [:
16 [:

Alb
NC

]7

15 [:

OOb

]8

14C

01b

4
5

:]6

L20-2

~~r4~~
to

00

.0

.0

lozziOlO
(!l
LCC
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Inlegrated Device Technology. Inc.

DECEMBER 1987
DSC-4006/-

10-48

JDT54/74FCT139/A FAST
CMOS DUAL 1-0F-4 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL

RATING

COMMERCIAL

CAPACITANCE
MILITARY

UNIT

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

. TalAs

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

-0.5 to +7.0

-0.5 to +7.0

SYMBOL

V

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CIN

Input Capacitance

COUT

Output Capacitance

CONDITIONS TYP.

MAX. UNIT

''IN = OV

6

10

pF

VOUT = OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
IN GS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLc = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V ±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V ±10%
MIN.

TYP.(2)

MAX.

UNIT

~H

Input HIGH Level

Guaranteed Logic High Level

2.0

-

V

~L

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

SYMBOL

IIH

TEST CONDITIONS (1)

PARAMETER

Input HIGH Current
Vcc = Max.

VI = \Cc

-

VI = 2.7V

-

VI = 0.5V

5
5(4)
_5(4)

jJA

IlL

Input LOW Current

.....;

-

-5

'vIK

Clamp Diode Voltage

\Cc = Min., IN = -18mA

-

-0.7

-1.2

V

los

Short Circuit Current

\to = Max!3), Vo = GND

-60

-120

-

mA

Vcc = 3V, ''IN = VLC or VHC ' 10H = -32jJA

VHC

Vcc

10H = -300jJA

VHC

\Cc

10H = -12mA MIL.

2.4

4.3

V

10H = -15mA COM'L.

VOH

VOL

Output LOW Voltage

Output HIGH Voltage

VI = GND

2.4

4.3

-

Vcc = 3V, '-"N = VLC or VHC , 10L = 300jJA

-

GND

VLC

10L = 300jJA

-

GND

VLC

0.3

0.5

0.3

0.5

Vcc = Min.
VIN = "lHor'-"L

VCC = Min.
'-"N = '-"H or'-"L

10L = 32mA MIL.
10L = 48mA COM'L.

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-49

V

IDT54/74FCT139/A FAST
CMOS DUAL 1-0F-4 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS (1)

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~VHC; "'IN ~ VLC
fl = 0

~Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current (4)

\be = Max.
Outputs Open
One Input Toggling
50% Duty Cycle

Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
One Input Toggling

Ic

MIN.

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

"'IN ~ VHC
"'IN ~ VLC

-

0.15

0.3

mA!
MHz

"'IN ~ VHC
"'IN ~ VLC
(FCn

-

1.5

4.5

-

1.8

5.5

VIN = 3.4V
VIN = GND

Total Power Supply Current(6)

mA
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
One Input Toggling
on Each Decoder

"'IN ~ VHC
VIN ~ VLC
(Fen

-

3.0

7.5(5)

VIN = 3.4V
VIN = GND

-

3.5

9.5(5)

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. + 25°C ambient and maximum loading.
.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable. but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPLrrS + IDYNAMIC
.
, Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (\'IN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-50

IDT54/74FCT139/A FAST
CMOS DUAL 1-0F-4 DECODER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS

INPUTS

OUTPUTS
A1

00

01

~

~

X

X

H

H

H

H

L

L

L

L

H

H

H

L

H

L

H

L

H

H

L

L

H

H

H

L

H

H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care

H

H

H

L

E

Ao

H

PIN NAMES
Ao,A,

'l:A, 'l:B
0 0 -03

DESCRIPTION
Address Inputs
Enable Inputs (Active LOW)
Outputs (Active LOW)

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT139
SYMBOL

PARAMETER

tpLH
tpHL

Propagation Delay
Ao orA, to On

tpLH
tpHL

Propagation Delay
'l:A or 'l:B to On

CONDITION(')

CL = 50pF
RL = 500n

TYP.(3)

IDT54/74FCT139A

COM'L

MIL

MIN.(2) MAX.

MIN!2) MAX.

COM'L
TYP.(3)

MIN.(2)

MAX.

6.0

1.5

9.0

1.5

12.0

4.5

1.5

5.9

1.5

7.8

ns

5.5

1.5

8.0

1.5

9.0

4.0

1.5

5.5

1.5

7.2

ns

ORDERING INFORMATION
A

X

Device Type

Package

UNIT

MIN.(2)

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.

IDTXXFCT
Temp. Range

MIL

MAX.

Commercial
MIL-STO-883, Class B

1....-----------1
L.-______________-I
L.----------------------i

10-51

P
D
SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERDIP

139
139A

Dual1-of-4 Decoder
Fast DuaI1-of-4 Decoder

54
74

-55°C to +125°C
O°C to + 70°C

FEATURES:

DESCRIPTION:

• IDT54/74FCT161/163 equivalent to FAST™ speedJ
IDT54/74FCT161A/163A 35% faster than FAST T
• Equivalent to FAST ™ output drive over full temperature and
voltage supply extremes
• IOL =48mA (commercial), 32mA (military)
• CMOS power levels (5pW typo static)
• TIL input and output level compatible
• CMOS output level compatible
• Substantia"y lower input current levels than FAST™ (5pAmax.)
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT161/163 and IDT54/74FCT161N163A are
high-speed synchronous modul0-16 binary counters built using
advanced CEMOS ™ , a dual metal CMOS technology.They are
synchronously presettable for application in programmable dividers and have two types of count enable inputs plus a terminal count
output for versatility in forming synchronous multi-stage counters.
The IDT54/74FCT161 and IDT54/74FCT161A have asynchronous
Master Reset inputs that override all other inputs and force the outputs LOW. The IDT54/74FCT163 and IDT54/74FCT163A have
Synchronous Reset inputs that override counting and parallel
loading and allow the outputs to be simultaneously reset on the
rising edge of the clock.

FUNCTIONAL BLOCK DIAGRAM
Po

~~--==~~-----------+----------~-------+~--------~

CEP ~==~~==r-~-------.---+-+-----------.~~------~~~------,
CET

--~---+~------------~---+-+------------+-++---------+~~-------+------44-,

TC

CP

DETAIL A

DETAIL A

DETAIL A

L.. _ _ _

Q,

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Company

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology. Inc.

10-52

DECEMBER 1987
D8C-4oo7/-

IDT54/74FCT161/A & IDT54/74FCT163/A FAST
CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATIONS

RATING

SYMBOL

DIP/SOIC/CERPACK
TOP VIEW

I

I"..J

3

Po ]4
P1 ]5
NC ]6

I

I

L..J

2

1'1

I

U

I

I

L....I

I'

L..J

20 19

1

L20-2

18[:

00

17e

0

16[:

NC

1

P2

]

7

15[:

O2

P3

]8

14[:

03

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

VTERM
TA

Operating
Temperature

Oto + 70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

CAPACITANCE
SYMBOL

~~~~~
LCC
TOP VIEW

MILITARY

Terminal Voltage
with Respect to
GND

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

INDEX
•

(1)

COMMERCIAL

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

GIN

Input Capacitance

GOUT

Output Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT = OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

* MR FOR '161
* SA FOR '163

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLe = 0.2V; VHe = Vec - 0.2V
Commercial: TA = O°C to + 70°C; 'be = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL

TEST CONDITIONS(l)

PARAMETER

MIN.

TYP.(2)

MAX.

-

-

V

0.8

V

Input HIGH Level

Guaranteed Logic High Level

2.0

"IL

Input LOW Level

Guaranteed Logic Low Level

IIH

Input HIGH Current

IlL

Input LOW Current

-

"IK

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

-0.7

-1.2

V

los

Short Circuit Current

Vee = Max.(3), Vo = GND

-60

-120

mA

VHe
VHe

. Vee
Vec

Output HIGH Voltage

Vee = 3V, "IN = VLe or VHe.IoH = -32 jJA
10H = -300J.lA
Vce = Min.
10H = -12mA MIL.
"IN = "IH or "IL
10H = -15mA COM'L.

-

2.4

4.3

-

"I = Vee
"I = 2.7V

Vee = Max.

VOH

.

"I = 0.5V
"I = GND

Vee = 3V, "IN = VLC or VHe. 10L = 300jJA
10L
VOL

Output LOW Voltage

Vee = Min.

10L

"IN = "IH or"lL

10L

= 300J.lA
= 32mA MIL.
= 48mA COM'L.

-5(4)

J.lA

-5

4.3

-

-

GND

VLe

-

GND

VLe

-

0.3

0.5

0.3

0.5

For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vec = 5.0V, + 25°C ambient and maximum loading.
Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
This parameter is guaranteed but not tested.

10-53

5
5(4)

2.4

NOTES:
1.
2.
3.
4.

UNIT

"IH

V

V

IDT54/74FCT161/A & IDT54/74FCT163/A FAST
CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL'TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS (IDT54/74FCT161/A)
VLC = 0 2V' \4ic = Vcc - 0 2V
TEST CONDITIONS (1)

PARAMETER

SYMBOL

Icc

.6.lcc

ICCD

Ic

MIN.

TYP.(2)

MAX.

UNIT

Quiescent Power Supply Current

Vcc = Max.
Vcc ~ VHC ; \'IN :S VLC
fcp = fl = 0

-

0.001

1.5

rnA

Power Supply Current per
TTL Input HIGH

Vcc = Max.
\'IN = 3AV(3)

-

0.5

2.0

rnA

Dynamic Power Supply Current (4)

Vcc = Max.
Outputs Open
Load Mode
CEP = CET = ~ = GND
MR =Vcc
One Bit Toggling
50% Duty Cycle

\'IN ~ VHC
\'IN :S VLC (FCT)

-

0.15

0.25

rnA/MHz

\'IN ~ VHC
\'IN :S VLC (FCT)

-

3.75

7.75(5)

Total Power Supply Current(6)

Vcc = Max.
Outputs Open
Load Mode
fcp= 10MHz
50% Duty Cycle
CEP = CET = ~ = GND
MR =Vcc
Four Bits Toggling
atfl = 5MHz
50% Duty Cycle

rnA
\'IN = 3AVor
\'IN = GND

-

5.0

12.75(5)

TYP.(2)

MAX.

POWER SUPPLY CHARACTERISTICS (IDT54/74FCT163/A)
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

TEST CONDITIONS(1)

PARAMETER

Icc
.6. Icc

,ICCD

Ic

MIN.

UNIT

Quiescent Power Supply Current

Vcc = Max.
Vcc ~ VHC ; \'IN :S VLC
fcp = fl = 0

-

0.001

1.5

rnA

Power Supply Current per
TTL Input HIGH

Vcc = Max.
\'IN = 3AV(3)

-

0.5

2.0

rnA

Dynamic Power Supply Current (4)

Vcc = Max.
Outputs Open
Load Mode
CEP = CET = ~ = GND
~ = Vcc
One Bit Toggling
50% Duty Cycle

\'IN ~ VHC
\'IN :S VLC (FCT)

-

0.15

0.25

rnA/MHz

\'IN ~ VHC
\'IN :S VLC (FCT)

-

3.75

7.75(5)

Total Power Supply Current (6)

Vcc = Max.
Outputs Open
Load Mode
fcp= 10MHz
50% Duty Cycle
CEP =CET = ~ = GND
~ = Vcc
Four Bits Toggling
at fl = 5MHz
50% Duty Cycle

rnA
\'IN = 3AVor
\'IN

= GND

-

5.0

12.75(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value spe~ified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V,· + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3AV); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc
.6. Icc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TTL High Input (VIN = 3AV)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

+

10-54

IDT54/74FCT161/A & IDT54/74FCT163/A FAST
CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE (2)

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

DESCRIPTION

CEP

Count Enable Parallel Input

CET

Count Enable Trickle Input

CP

Clock Pulse Input (Active Rising Edge)

MR ('161)

Asynchronous Master Reset Input (Active LOW)

SR ('163)

Synchronous Reset Input (Active LOW)

PO- 3

Parallel Data Inputs

PE

Parallel Enable Input (Active LOW)

0 0- 3

Flip-Flop Outputs

TC

Terminal Count Output

SR(1)

PE

CET

CEP

ACTION ON THE RISING
CLOCK EDGE (S)

L
H
H
H
H

X
L
H
H
H

X
X
H
L
X

X
X
H
X
L

Reset (Clear)
Load (Pn -+ On)
Count (Increment)
No Change (Hold)
No Change (Hold)

NOTES:
1. For FCT163/163A only.
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don't Care

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT161A
IDT54/74FCT163A

IDT54/74FCT161
IDT54/74FCT163
(1)

TYPP)

MIL.

COM'L.

MINP) MAX. MINP) MAX.

TYPP)

MIL.

COM'L.

MIN,<2) MAX. MIN.<2) MAX.

t pLH
tpHL

Propagation Delay CP to On
(PE Input HIGH)

7.0

2.0

11.5

2.0

11.0

4.5

2.0

7.5

2.0

7.2

ns

tpLH
t pHL

Propagation Delay CP to On
(PE Input LOW)

7.0

2.0

10.0

2.0

9.5

4.5

2.0

6.5

2.0

6.2

ns

t pLH
t pHL

Propagation Delay
CP to TC

10.0

2.0

16.5

2.0

15.0

6.5

2.0

10.8

2.0

9.8

ns

t pLH
t pHL

Propagation Delay
CETto TC

4.5

1.5

9.0

1.5

8.5

3.0

1.5

5.9

1.5

5.5

ns

t pHL

Propagation Delay MR to On
(,F161)

9.0

2.0

14.0

2.0

13.0

5.9

2.0

9.1

2.0

8.5

ns

t pHL

Propagation Delay
MR to TC

8.0

2.0

12.5

2.0

11.5

5.2

2.0

8.2

2.0

7.5

ns

5.0

5.5

-

5.0

-

4.0

4.5

-

4.0

-

ns

tsu(H)
tsu(L)

Set-up Time, HIGH or LOW
Pn to CP
CL = 50pF
RL = 500n

tH(H)
tH(L)

Hold Time, HIGH or LOW
Pn to CP

2.0

2.0

-

1.5

-

1.5

2.0

-

1.5

-

ns

tsu(H)
tsu(L)

Set-up Time, HIGH or LOW
PE" or SA to CP

11.0

13.5

-

11.5

-

9.0

11.5

-

9.5

-

ns

tH(H)
tH(L)

Hold Time, HIGH or LOW
PE or SR to CP

2.0

1.5

-

1.5

-

1.5

1.5

-

1.5

-

ns

tsu(H)
tsu(L)

Set-up Time, HIGH or LOW
CEP or CET to CP

11.0

13.0

-

11.5

-

9.0

11.0

-

9.5

-

ns

tH(H)
tH(L)

Hold Time, HIGH or LOW
CEP or CET to CP

0

0

-

0

-

0

0

-

0

-

ns

tw(H)
tw(L)

Clock Pulse Width (Load)
HIGH or LOW

5.0

5.0

-

5.0

-

4.0

4.0

-

4.0

-

ns

tw(H)
tw(L)

Clock Pulse Width (Count)
HIGH or LOW

6.0

8.0

-

7.0

-

5.0

7.0

-

6.0

-

ns

5.0

5.0

-

5.0

-

4.0

4.0

-

4.0

-

ns

6.0

6.0

-

6.0

-

5.0

5.0

-

5.0

-

ns

tw(L)
tREM

"MFt Pulse Width, LOW
(,F161)
Recovery Time MR to CP
(,F161)

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.

10-55

IDT54/74FCT161/A & IDT54/74FCT163/A FAST
CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXX)(

X

Device Type

Process

y

Blank

Commercial

B

MIL-STD-883, Class B

P
D
L
SO

Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK

E
161
163

161A
163A

I 54
I 74

10-56

Synchronous Binary Counter
with Asynchronous Master Reset
Synchronous Binary Counter
with Synchronous Reset
Fast Synchronous Binary Counter
with Asynchronous Master Reset
Fast Synchronous Binary Counter
with Synchronous Reset

FEATURES:

DESCRIPTION:

• IDT54/74FCT182 equivalent to FAST™speed;
IDT54/74FCT182A 35% faster than FAST ™
• Equivalent to FAST TMspeeds and output drive over full
temperature and voltage supply extremes
• 10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5jJW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™(5)JA max.)
• Carry lookahead generator
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT182 and IDT54/74FCT182A are high-speed
carry lookahead generators built using advanced CEMOS TM, a
dual metal CMOS technology. The IDT54/74FCT182 and
IDT54/74FCT182A are carry lookahead generato!:? th~ aC.gept up
to four pairs of actlYe LQW Q..arry 'propagate (P 6, P 1 , P2, P3) and
Carry Generate (Go, G 1 , G 2 , G 3 ) signals and an active HIGH
carry input (Cn) and provides anticipated HIGH carries (Cn+y,
Cn+z) across four groups of binary aQders. These products al§.o
have active LOW Carry Propagate (P) and carry generate (G)
outputs which may be used for further levels of lookahead.

PIN CONFIGURATIONS
0

10:-16 ~ -:Y~
...... ......
...... ......

INDEX

G1
P1

Vee

I

]52

3

Go

G2

Go

]4

Po

Cn
Cn+x
Cn+y

Po
NC

]5

G3
P3
P
GND

G3
153

G
Cn+z

DIP/SOIC/CERPACK
TOP VIEW

I

LJ

20 19

1

18[

H[
L20-2

16[

]7

15[

C n +x

:] B

14 [:

Cn+y

11 12 13
,...,9 n10 ,...,
nn
JQ.. 0 u
z z ~I-

0

1

I1C"

II

TC

J

I III

I
I
CLOCK K

l..-.( ~

Q
L--

?

l ,.

~t>-

Q

0

~

1

I

1

1-0

I

I

J CLOCK K

l..-.( ~

CEE'AR t>-

O

Q

1

L.:::..-

1

J CLOCK K

1.......4 ~

O

CEE'AR t>-

Q

L-

V

?
01

O2

CEMOS Is a trademark of Integrated Device Technology, Inc.
FAST Is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

10-62

DECEMBER 1987
DSC-4009/-

IDT54174FCT191/A FAST CMOS
UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

ABSOLUTE MAXIMUM RATINGS
SYMBOL

P1

Vee

01

Po

00

CP

CE

RC

UID
O2

TC
]5[

03

P2

GND

~

DIP/CERPACK/SOIC
TOP VIEW

0

~

0

0 0 ]4

LJUIIUU
3 2 U 20 19
1

CE ]5

18[:

CP

17[:

Fie

NC

]6

16[:

NC

UID

:] 7

15[:

O 2 ]8

14[:

TC
]5[

L20-2

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to + 125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Oa:-z ~cE

INDEX

RATING

CAPACITANCE
SYMBOL

9 10 11 12 13

nnnnn
c
o z zo~rf:'

CI~

C')

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance

CONDITIONS TYP.
VIN = OV

MAX. UNIT
10

10

pF

12
12
pF
COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is measured at characterization but not tested.

Cl

lCC
TOP VIEW

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VlC = 0.2V; VHe = Vee - 0.2V
Commercial: TA = O°C to + 70°C; Vee = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL

TEST CONDITIONS(l)

PARAMETER

MIN.

Typ.(2)

-

MAX.

UNIT

-

V

0.8

V

\'JH

Input HIGH Level

Guaranteed Logic High Level

2.0

\'Jl

Input LOW Level

Guaranteed Logic Low Level

-

-5

-0.7

-1.2

V

-

mA

III

Input LOW Current

\'JK

Clamp Diode Voltage

Vec = Min., IN = -18mA

-

los

Short Circuit Current

Vee = MaxP), \(, = GND

-60

-120

VHC
VHC

Vee

10H = -300)JA
10H = -12mA MIL.

2.4

4.3

10H = -15mA COM'l.

2.4

4.3

-

GND

Vle

10l = 300)JA

-

GND

Vle

10l = 32mA MIL.

-

0.3

0.5

10l = 48mA COM'L.

-

0.3

0.5

IIH

VI = Vee

Input HIGH Current

VI = 2.7V

VCC = Max.

VI ·= 0.5V
VI = GND

Vee = 3V, \'IN = VLC or VHc.l oH = -32 jJA
VOH

Output HIGH Voltage

Vee = Min.
\'IN = \'IH or\'Jl

Vee = 3V, VIN = VlC or VHC • 10l = 300jJA
VOL

Output LOW Voltage

Vce = Min.
\'IN = \'IH or\'Jl

-

Vee

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-63

5
5(4)
-5(4)

-

)JA

V

V

IDT54/74FCT191/A FAST CMOS
UPIDOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
V LC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

TEST CONDITIONS (1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC ; \'IN ~ VLC
fcp = fl = 0

-

0.001

1.5

mA

~Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
Preset Mode
J5L = C'E = UID =
CP = GND
One Bit Toggling
50% Duty Cycle

\'IN ~ VHC
\'IN ~ VLC

-

0.15

0.25

mAl
MHz

\'IN ~ VHC
\'IN ~ VLC
(FCT)

-

3.0

6.5(5)

Total Power Supply Current(6)

Vce = Max.
Outputs Open
Preset Mode
'PL = BE = O/D =
CP = GND
Four Bits Toggling
atf l = 5MHz
50% Duty Cycle

ICCD

Ic

mA
VIN = 3.4Vor
VIN = GND

-

4.0

10.5(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Dolcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

RC TRUTH TABLE
OUTPUT

INPUTS

DESCRIPTION

CE

TC(1)

CP

Rc

Count Pulse Input (Active Rising Edge)

L

H

-U-

-U-

Parallel Data Inputs

H

X

X

H

CE

Count Enable Input (Active LOW)

CP
Pa-3
PL

Asynchronous Paraiiel Load Input (Active LO'N)

UfD

Up/Down Count Control Input

QO-3

Flip-Flop Outputs

RC

Ripple Clock Output (Active LOW)

TC

Terminal Clock Output (Active HIGH)

X
H
X
L
NOTES:
1. TC is generated internally.
2. H = HIGH Voltage Level, L= LOW Voltage Level, X= Don't Care

TRUTH TABLES
MODE SELECT TABLE
INPUTS

10-64

MODE

PI.

CE

H

L

L

H

L

H

L

X

X

X

Preset (Asynch.)

H

H

X

X

No Change (Hold)

DID

CP

S
S

Count Up
CountDown

IDT54/74FCT191/A FAST CMOS
UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT191A

IDT54/74FCT191
SYMBOL

PARAMETER

COM'L

MIL.

CONDITION(1)

COM'L

MIL

TYpP) MIN.(2)
TYP.!3)
MAX. MINP) MAX.

UNIT

MIN.(2) MAX. MIN52) MAX.

tpLH
tpHL

Propagation Delay
CPto an

8.5

1.5

16.0

2.5

12.0

5.5

1.5

10.5

2.5

7.8

ns

tpLH
tpHL

Propagation Delay
CP toTC

10.0

2.0

16.0

3.0

14.0

6.5

2.0

10.5

3.0

9.1

ns

tpLH
tpHL

Propagatio!!"pelay
CPto RC

5.5

1.5

12.5

2.5

8.5

3.6

1.5

8.2

2.5

5.6

ns

tpLH
tpHL

propctation Delay

5.5

2.0

8.5

2.0

8.0

3.6

2.0

5.6

2.0

5.2

ns

tpLH
tpHL

Propjlgation Delay
UID to tiC

11.0

4.0

22.5

4.0

20.0

7.2

4.0

14.7

4.0

13.0

ns

tpLH
tpHL

Propjlgation Delay
U/DtoTC

7.0

3.0

13.0

3.0

11.0

4.6

3.0

8.5

3.0

7.2

ns

tpLH
tpHL

Propagation Delay
Pn to an

10.0

1.5

16.0

2.0

14.0

6.5

1.5

10.4

2.0

9.1

ns

tpLH
tpHL

Prop~ation

9.0

3.0

14.0

3.0

13.0

5.9

3.0

9.1

3.0

8.5

ns

4.5

6.0

-

5.0

-

4.0

5.0

-

4.0

-

ns

Eto~

PL to

Delay

an
CL = 50pF
RL = 500n

tsu(H)
tsu(L)

Setup Time
HIGH or LOW
Pn to J5L

tH(H)
tH(L)

Hold Time
HIGH or LOW
Pn to J5L

2.0

1.5

-

1.5

-

1.5

1.5

-

1.5

-

ns

tsu(L)

Setup Time LOW
CE to CP

10.0

10.5

-

10.0

-

9.0

9.5

-

9.0

-

ns

tH(L)

Hold Time LOW
CE to CP

0

0

-

0

-

0

0

-

0

-

ns

tsu(H)
tsu(L)

Setup Time
HIGH or LOW
DID to CP

12.0

12.0

-

12.0

-

10.0

10.0

-

10.0

-

ns

tH(H)
tH(L)

Hold Time
HIGH or LOW
DID to CP

0

0

-

0

-

0

0

-

0

-

ns

tw(L)

PL Pulse Width LOW

6.0

8.5

-

6.0

8.0

-

ns

5.0

7.0

-

5.0

4.0

6.0

-

5.5

CP Pulse Width LOW

-

5.5

tw(L)

4.0

-

ns

6.0

7.5

-

6.0

-

5.0

6.5

-

5.0

-

ns

tREM

Re~very

Time
PL to CP

NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vec = 5.0V, + 25°C ambient and maximum loading.

10-65

IDT54/74FCT191/A FAST CMOS
UP/DOWN BINARY COUNTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temp. Range.

XXXX
Device Type

X
Process

I

I Blank

~B

D
E
' - - - - - - - - - - - - - - 1 SO
L
191
191A

10-66

Commercial
MIL-STD-883, Class B
CERDIP
CERPACK
Small Outline IC
Leadless Chip Carrier
Up/Down Binary Counter
Fast Up/Down Binary Counter

+ 125°C

54

-55°C to

74

O°C to + 70°C

FEATURES:

DESCRIPTION:

• IDT54/74FCT193 equivalent to FAST™speed;
IDT54/74FCT193A 35% faster than FAST ™
• Equivalent to FAST ™output drive over full temperature and
voltage supply extremes
• 10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™(5~A max.)
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT193 and IDT54/74FCT193A are u~/down
modul0-16 binary counters built using advanced CEMOS T ,a dual
metal CMOS technology. Separate count-up and count-down
clocks are used and, in either counting mode, the circuits operate
synchronously. The outputs change state synchronously with the
LOW-to-HIGH transitions on the clock inputs. Separate terminal
count-up and terminal count-down outputs are provided that are
used as the clocks for subsequent stages without extra logic, thus
simplifying multi usage counter designs. Individual preset inputs
allow the circuit to be used as a programmable counter. Both the
Parallel Load (PI.) and the Master Reset (MR) inputs
asynchronously override the clocks.

FUNCTIONAL BLOCK DIAGRAM
Po

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© .1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-4011/-

10-67

IDT54/74FCT193/A FAST CMOS
UP/DOWN BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATIONS

SYMBOL
VTERM

LJU;;UU
3 2 U 20 19

0 0 ]4

18[:

MR

]5

17[:

Teo

NC ]6
CPu ]7
O2 :] 8

L20-2

9

10

11

16r:

NC

15[:

TC u

14[:

f5[

Z

(!)

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TsTa

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

CAPACITANCE
SYMBOL

12 13

nnnnr.
MO () rf.' o..N

o

MILITARY

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

oa:-~~r£

CPo

(1)

COMMERCIAL

TA

DIP/SOIC/CERPACK
TOP VIEW
INDEX

RATING
Terminal Voltage
with Respect to
GND

Z

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

CIN

Input Capacitance

COUT

Output Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is guaranteed by characterization data and not tested.

LCC
TOP VIEW

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vce - 0.2V
Commercial: TA = O°C to + 70°C; Vec = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
TEST CONDITIONS (1)

TYP.(2)

MAX.

UNIT

VIH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

\'IL

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

-

5

-

-5(4)

-0.7

-1.2

V
mA

SYMBOL

PARAMETER

MIN.

IlL

Input LOW Current

\'IK

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

los

Short Circuit Current

Vee = Max., (3) Vo = GND

"':60

-120

-

VHC
VHC

Vcc

-300~A

Output HIGH Voltage

Vee = 3V, \'IN = VLC or VHe , 10H =
IoH =
Vcc = Min.
IoH =
\'IN = \'IH or\'lL
IoH =

-12mA MIL.

2.4

4.3

-

-15mA COM'L.

2.4

4.3

-

-

GND

VLC

GND

VLC

0.3

0.5

-

0.3

0.5

IIH

VI = Vcc

Input HIGH Current

VI = 2.7V

Vce = Max.

VOH

VI = 0.5V
VI = GND

-32~

Vcc = 3V, \'IN = VLC or VHC , 10L = 300~
IoL = 300~A
VOL

Output LOW Voltage

Vee = Min.

IoL = 32mA MIL.
IoL = 48mA COM'L.

\'IN = \'IH or\'lL

Vec

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-68

5(4)

~A

-5

V

V

IDT54/74FCT193/A FAST CMOS
UP/DOWN BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

TEST CONDITIONS (1)

PARAMETER

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~VHC; "IN :5 VLC
fcpu = fcpo = f I = 0

.6. Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
Preset Mode
J5L = MR = CPu =
CPo = GND
One Bit Toggling
50% Duty Cycle

Total Power Supply Current

\Cc = Max.
Outputs Open
Preset Mode
fit = MR = CP =
CPo = GND U
Four Bits Toggling
atf l = 5MHz
50% Duty Cycle

Icco

Ic

(6)

MIN.

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

VIN ~ VHC
"IN :5 VLC

-

0.15

0.25

mAl

\IN ~ VHC
\IN :5 VLC
(FCT)

-

3.0

6.5(5)

mA

VIN = 3.4Vor
VIN = GND

-

4.0

5
10.5 )

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IOYNAMIC
Ic = Icc + .6. l cc DHNT + Icco (fcp/2 + fl NI )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

FUNCTION TABLE

DESCRIPTION

MR

PL

CPu

CPo

H

X

X

X

Reset (Asyn.)

L

X

X

Preset (Asyn.)

H

H

H

No Change
Count Up
Count Down

CPu

Count Up Clock Input (Active Rising Edge)

CPo

Count Down Clock Input (Active Rising Edge)

L

MR

Asynchronous Master Reset (Active HIGH)

L

PI:

Asynchronous Parallel Load Input (Active LOW)

L

H

t

H

PO- 3

Parallel Data Inputs

L

H

H

t

QO-3

Flip-flop Outputs

TCo

Terminal Count Down (Borrow) Output (Active LOW)

TC u

Terminal Count Up (Carry) Output (Active LOW)

10-69

MODE

MHz

IDT54/74FCT193/A FAST CMOS
UP/DOWN BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERA1.:URE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT193A

IDT54/74FCT193
SYMBOL

PARAMETER

CONDITION(1)

MIL.

(3)

TYP.

MIN!2) MAX.

COM'L.
(3)
MIN.(2) MAX. TYP.

MIL.
MIN.(2) MAX.

COM'L.
MIN!2) MAX.

UNIT

tpLH
tpHL

Propagation Delay
CPu or CPo
"fC0 or "fC o .

7.0

2.0

10.5

2.0

10.0

4.6

2.0

6.9

2.0

6.5

ns

tpLH
tpHL

Propagation Delay
CPu or CPo to On

9.5

2.0

14.0

2.0

13.5

6.2

2.0

9.1

2.0

8.8

ns

t pLH
tpHL

Propagation Delay
Pn to On

11.0

2.0

16.5

2.0

15.5

7.2

2.0

10.8

2.0

10.1

ns

tpLH
fPHL

Prop~ation

10.0

2.0

13.5

2.0

14.0

6.5

2.0

9.1

2.0

8.8

ns

Delay

PL to On

t pHL

Propagation Delay
MR to On

11.0

3.0

16.0

3.0

15.5

7.0

3.0

10.4

3.0

10.1

ns

tpLH

Propagation Delay
MR to TCu

10.5

3.0

15.0

3.0

14.5

6.5

3.0

9.8

3.0

9.4

ns

t pHL

Propagati0.!lPelay
MRtoTC o

11.5

3.0

16.0

3.0

15.5

7.5

3.0

10.4

3.0

10.1

ns

12.0

3.0

18.5

3.0

16.5

8.0

3.0

12.0

3.0

10.8

ns

~pa~on Delay

tpLH
tpHL

'PL to TC u or TC o

tpLH
tpHL

propa~ion Delay
Pn toT uor'FC o

CL = 50pF
RL = 5000

11.5

3.0

16.5

3.0

15.5

7:5

3.0

10.8

3.0

10.1

ns

tsu(H)
tsu(L)

Set-up Time,
HIGH or LOW
Pn to PI.

4.5

6.0

-

5.0

-

4.0

5.0

-

4.0

-

ns

tH (H)
tH (L)

Hold Time,
HIGH or LOW
Pn to PI.

2.0

2.0

-

2.0

-

1.5

1.5

-

1.5

-

ns

tw(L)

PL Pulse Width,
LOW

6.0

7.5

-

6.0

-

5.0

6.5

-

5.0

-

ns

tw(L)

CPu or CPo
Pulse Width, LOW

5.0

7.0

-

5.0

-

4.0

6.0

-

4.0

-

ns

tw(L)

CPu Dr CPo
Pulse Width, LOW
(Change of Direction)

10.0

12.0

-

10.0

-

8.0

10.0

-

8.0

-

ns

tw(H)

MR Pulse Width,
HIGH

6.0

6.0

-

6.0

-

5.0

5.0

-

5.0

-

ns

tREM

-Becovery Time
PL to CPu or CPo

6.0

8.0

-

6.0

-

5.0

7.0

-

5.0

-

ns

tREM

Recovery Time
MR to CPu or CPo

4.0

4.5

-

4.0

-

3.0

3.5

-

3.0

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = -5.0V, + 25°C ambient and maximum loading.

10-70

IDT54/74FCT193/A FAST CMOS
UP/DOWN BINARY COUNTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type

x
Process

y:~k
P
D

L...------------I SO
L
E
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _---1 193
193A

10-71

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Up/Down Binary Counter
Fast Up/Down Binary Counter

FEATURES:

DESCRIPTION:

• IDT54/74FCT240 equivalent to FAST™speed;
IDT54/74FCT240A 40% faster than FAST ™
• Equivalent to FAST ™output drive over full temperature and
voltage supply extremes
• 10L = 64mA (commerCial) and 48mA (military)
• CMOS power levels (5}JW typo static)
• TTL Input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™(5}JA max.)
• Octal buffer/line driver with 3-state output
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87655 is listed on this
function. Refer to Section 2/page 2-4.

The IDT54/74FCT240/A are octal buffer/line drivers built using
advanced CEMOS T~ a dual metal CMOS technology. The devices
are designed to be employed as memory and address drivers,
clock drivers and bus-oriented transmitter/receivers which provide
improved board density.

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM

DrA-----O
'C5"I: B

DAo

DAo

080

DBo

DA,

OA,

OB,

DB,

DA z

OA z

OB z

DB z

DA3

OA 3

083

DB3

DIP/SOIC/CERPACK
TOP VIEW

INDEX

u
3

U; I U U
Z U 20 '9

DA,

]4

'6 [:

00,

]5

17[

DBo

DA z

]6

16 [:

OA,

L20-2

GAo

ooz

]7

'5 [:

DB,

DA3

]6

'4 [:

OAz

~~fi~~

laS'
0 al' ~ cS'
0ao
0
LCC
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

'967 Integrated DevIce Technology, Inc.

DECEMBER 1987
DSC-40'3/-

10-72

IDT54/74 FCT240/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

ABSOLUtE MAXIMUM
SYMBOL

RATING

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

RATINGS(1)
COMMERCIAL

MILITARY

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

-0.5 to +7.0

-0.5 to +7.0

SYMBOL

UNIT
V

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

C IN

Input Capacitance

COUT

Output Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTES:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vce - O.2V
Commercial: TA = O°C to + 70°C; Vee = 5.0V ±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V ±10%
SYMBOL

TEST CONDITIONS(1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

~H

Input HIGH Level

Guaranteed LogiC High Level

2.0

-

-

V

~L

Input LOW Level

Guaranteed LogiC Low Level

-

-

0.8

V

IIH

Input HIGH Current
Vec = Max.

IlL

VI = Vee

-

-

5

VI = 2.7V

-

5(4)

= 0.5V

-

VI = GND

-

Vo = Vee

-

Vo = 2.7V

-

Vo = 0.5V

-

-

-

-0.7

-1.2

V

-60

-120

mA

VHe

Vee

= -300~A

VHe

Vee

10H = -12mA MIL.

2.4

4.3

10H = -15mA COM'L.

VI

Input LOW Current

loz

Off State (High Impedance)
Output Current

Vee = Max.

~K

Clamp Diode Voltage

Vce = Min., IN

los

Short Circuit Current

Vcc = MaxP), Vo = GND

Vo = GND

Vee = 3V, VIN
VOH

Output HIGH Voltage

= -18mA
= VLe

Output LOW Voltage

Vee = Min.
"iN = "iH or"iL

4.3

-

GND

VLC

10L = 300~A

-

GND

VLe

= 48mA MIL.

-

0.3

0.55

10L = 64mA COM'L.

-

0.3

0.55

10L

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-73

~A

-10

2.4

Vee = 3V, "iN = VLC or VHe , 10L =
VOL

10(4)
_10(4)

300~A

10H

~A

10

-

or VHe , 10H = -32~A

Vee = Min.
"iN = "iHor"iL

_5(4)
-5

V

V

I DT54/74FCT240/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS FOR 'FCT240
V LC

= O.2V: VHC = Vcc -

SYMBOL

0.2V

PARAMETER

TEST CONDITIONS (1)

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC : VIN ~ VLC
fl = 0

~Icc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(4)

Vec= Max.
Outputs Open
OEA = OE B = GND
One Input Toggling
50% Duty Cycle

ICCD

Vec = Max.
Outputs Open
fl = 10MHz
50% D~Cycle
OEA = OE B = GND
One BitToggling
Ic

MIN.

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

"'N ~ VHC
"'N ~ VLC

-

0.15

0.25

mAl
MHz

VIN ~ VHC
"'N ~ VLC
(FCT)

-

1.5

4.0

VIN = 3.4V
VIN = GND

-

1.8

5.0
mA

Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% D~Cycle
OEA = OE B = GND
Eight Bits Toggling

V (6)
"'N ~ HC
"'N ~ VLC
(FCT)

-

3.0

6.5(5)

VIN = 3.4V(6)
VIN = GND

-

5.0

14.5(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + fl NI )
,
Icc = Quiescent Current
~Icc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-74

IDT54/74 FCT240/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

OEA, OE B
Dxx
Oxx

INPUTS

3-State Output Enable Input (Active LOW)
Inputs
Outputs

H =
L =
X =

z

=

OUTPUT

D

OEA,OE B
L

L

L

H

L

X

Z

H
HIGH Voltage Level
LOW Voltage Level
Don't Care
High Impedance

H

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT240
SYMBOL

PARAMETER

tpLH
tpHL

Propagation Delay
Dn to On

tpZH
t pZL

Output Enable
Time

tpHz
tpLZ

Output Disable
Time

CONDITION(1)

CL = 50pF
RL = 500n

TYP.(3)

COM'L

IDT54/74FCT240A
MIL.

MIN~2)

MIN.(2) MAX.

TYP.(3)
MAX.

COM'L
MIN.(2)

MIL

UNIT

MAX.

MIN.(2)

MAX.

5.0

1.5

8.0

1.5

9.0

3.5

1.5

4.8

1.5

5.1

ns

7.0

1.5

10.0

1.5

10.5

4.8

1.5

6.2

1.5

6.5

ns

··6.0

1.5

9.5

1.5

12.5

4.3

1.5

5.6

1.5

5.9 .

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXXFCT
Temp. Range

A

X

Device Type

Process

I

I Blank

~B

L-----------i

L..---.:..._ _ _ _ _ _ _ _ _ _ _ _ _-I

MIL-STD-883, Class B

P
D
SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

240
240A

Inverting Octal Buffer/Une Driver
Fast Inverting Octal Buffer/Une Driver

L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--I54

74

10-75

Commercial

-55°C to +125°C
O°C to + 70°C

DESCRIPTION:

FEATURES:
• IDT54/74FCT241/244 equivalent to FAST ™speed
IDT54/74FCT241A/244A 35% faster than FAST M
• Equivalent to FAST ™output drive over full temperature
and voltage supply extremes

The IDT54/74FCT241/244 and IDT54/74FCT241Al244A are octal buffer/line drivers built using advanced CEMOS TM, a dual metal
CMOS technology. The devices are designed to be employed as
memory and address drivers, clock drivers and bus-oriented transmitter/ receivers which provide improved board density.

t

•

•
•
•
•
•

= 64mA (Commercial), 48mA (Military)
CMOS power levels (5~W typo static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST ™ (5pA max.)
Octal buffer/line driver with 3-state output
10L

• JEDEC standard pinout for DIP and LCC
• Product available In Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87630 is listed on this function. Refer to Section 2/page 2-4.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS
~A
DAo
OBo
DAI
OBI

Vcc
OE"e*
OAo
DBa
OA 1
DBI
OA 2
DB2
OA 3
DB3

DA2
OB 2
DA3
OB 3
GND

OE"A-----O

DAo - - - - i f - - - i

IIIo

o
•

I

.......

3

o~ o

0
1'1'
t-J I I

2

LJ

I

DAI

---+---1

OEe for 'FCT244

m

~fo

c(

---+------<

DBa

*.Q§ for 'FCT241

DIP/SOIC/CERPACK
TOP VIEW

INDEX

OBo

OAo

OBI

1'1

L..I

.......

20 19

1

18[
17[:

L20-2

16 [:
15[
14 [:

DA2

OAo
DBa
OA 1

---+---1
D~

DBI
OA 2

LCC
TOP VIEW

DA3

---+---1

OB3

---------<

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-4020/-

10-76

IDT54/74FCT241A AND IDT54/74FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TBiAS

Temperature
Under Bias

TSTG

Storage
Temperature

PT

Power Dissipation

lOUT

DC Output Current

COMMERCIAL
-0.5 to +7.0

o to

+70

CAPACITANCE (TA= +25°C, f = 1.0MHz)
MILITARY
-0.5 to +7.0

SYMBOL

UNIT

CIN

V

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

0.5

0.5

W

120

120

mA

PARAMETER(1)
Input CapaCitance

CONDITIONS TYP.
VIN = OV

MAX. UNIT

6

10

pF

COUT
Output Capacitance
VOUT= OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.OV±5%
Military: TA = -55°C to + 125°C; Vcc = 5.OV±10%
SYMBOL

TEST CONDITIONS(1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

\lH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

\lL

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

-5

hH

Input HIGH Current
Vee = Max.

hL

Input LOW Current

VI = Vcc

-

5
5(4)

VI = 2.7V

-

VI = 0.5V

-

VI = GND

-

-

Vo = Vcc

-

-

10

Vo = 2.7V

-

10(4)

'-10

-0.7

-1.2

V

-

mA

_5(4)

loz

Off State (High Impedance)
Output Current

Vee = Max.

\lK

Clamp Diode Voltage

Vec = Min., IN = -18mA

-

los

Short Circuit Current

Vec = MaxPJ, Vo = GND

-60

-120

Vee = 3V, \IN = VLC orVHC • 10H = -32~

VHe

Vee

10H = -300~A

VHe

Vee

-

10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

4.3

-

-

GND

VLC

Vo = 0.5V
Vo = GND

VOH

Output HIGH Voltage

Vee = Min.
\IN = \lH or \lL

Vec = 3V, \IN = VLC or VHe • 10L = 300~
VOL

Output LOW Voltage

Vee = Min.
VIN = \lH or \lL

_10(4)

10L = 300~A

-

GND

VLe

10L = 48mA MIL.

-

0.3

0.55

10L = 64mA COM'L.

-

0.3

0.55

VH
Input Hysteresis on Clock Only
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.OV, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-77

~A

I
~A

V

mV

IDT54174FCT241A AND IDT54/74FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS FOR 'FCT241
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS(1)

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~ ~c; VIf"~ ~ VLC
fl = 0

6. l cc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
OEA = OEe = GND
One Input Toggling
50% Duty Cycle

ICCD

Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
OEA = OEe = GND
One Bit Toggling
Ic

MIN.

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

VIN ~ VHC
\'IN ~ VLC

-

0.15

0.25

mAl
MHz

\'IN ~ VHC
\'IN ~ VLC
(FCT)

-

1.5

4.0

VIN = 3AV
\'IN = GND

-

1.8

5.0
mA

Total Power Supply Current(6)
\'IN
Vcc = Max.
Outputs Open
fl =.2.5MHz
50% Duty Cycle
OEA = OEe = GND
Eight Bits Toggling

~

VHC (6)
\'IN ~ VLC
(FCT)

VIN = 3AV(6)
VIN = GND

-

3.0

6.5(5)

-

5.0

14.5(5)

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Per TTL driven Input (VIN = 3AV); all other inputs at Vcc or GND.
4. This parameter Is not directly testable. but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + 6. lcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
6.lcc = Power Supply Current for a TTL High Input (VIN = 3AV)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp. = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-78

IDT54/74FCT241A AND IDT54174FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS FOR 'FCT244
VLC = 0.2V: VHC = Vee - 0.2V
SYMBOL

PARAMETER

Icc

Quiescent Power Supply Current

Alcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(4)

Vee= Max.
Outputs Open
OEA = OE B = GND
One Input Toggling
50% Duty Cycle

ICCD

Vee = Max.
Outputs Open
fl = 10MHz
50% D~Cycle
OEA = OE B = GND
One BitToggling
Ic

TYP.(2)

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

VIN ~ VHC
'-"N :5 VLC

-

0.15

0.25

'-"N ~ VHC
VIN :5 VLC
(FCT)

-

1.5

4.0

VIN = 3.4V
VIN = GND

-

1.8

5.0

TEST CONDITIONS (1)
Vee = Max.
VIN ~ VHC : \'IN :5 VLC
fl = 0

MIN.

UNIT

mAl
MHz

mA

Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% D~Cycle
OEA = OE B = GND
Eight Bits Toggling

'-"N ~ VHC (6)
'-"N :5 VLC
(FCT)

-

3.0

6.5(5)

VIN = 3.4V(6)
'-"N = GND

-

5.0

14.5(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fl NI )
Icc = QUiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = DUty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-79

IDT54/74FCT241A AND IDT54/74FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
OEA, OE~l)

TRUTH TABLE FOR 'FCT241
INPUTS

DESCRIPTION

OE B

OE AI

3-State Output Enable Input (Active LOW)

OUTPUT

D

Dxx

Inputs

L

H

L

L

Oxx

Outputs

L

H

H

H

NOTE:
1. For 'FCT241 use OEs, and for 'FCT244 use OEs

H

L

X

Z

TRUTH TABLE FOR 'FCT244
INPUTS

L

L

L

H

H

H

X

Z

L

X
Z

HIGH Voltage Level
LOW Voltage Level

H
L

OUTPUT

D

OEAIOE B

Don't Care
High Impedance

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR 'FCT241
IDT54/74FCT241A (4)

IDT54/74FCT241
SYMBOL

tpLH
tpHL

PARAMETER

CONDITION(l)

Propagation Delay
Dn to On

tpZH
tpZL

Output Enable
Time

tpHZ
tpLZ

Output Disable
Time

CL = 50pF
RL = 500n

COM'L
TYPP)

MIN.(2) MAX.

MIL.
MIN~2)

MIL.

COM'L.
TYpJ3)

MAX.

MIN.(2)

UNIT

MAX.

MIN.(2)

MAX.

4.0

1.5

6.5

1.5

7.0

3.0

1.5

4.5

1.5

4.8

ns

5.5

1.5

8.0

1.5

8.5

4.0

1.5

5.6

1.5

6.0

ns

4.5

1.5

7.0

1.5

7.5

3.0

1.5

5.0

1.5

5.5

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
4. These numbers are preliminary only.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR 'FCT244
IDT54/74 FCT244
SYMBOL

PARAMETER

tpLH
t pHL

Propagation Delay
Dn to On

tpZH
t pZL

Output Enable
Time

tpHZ
tpLZ

Output Disable
Time

CONDITION(l)

C L = 50pF
RL = 500n

TYP.(3)

COM'L.
MIN.(2) MAX.

IDT54/74FCT244A
MIL.

MIN~2)

MAX.

TYP!3)

COM'L.

MIL.

UNIT

MIN.(2)

MAX.

MIN.(2)

MAX.

4.5

1.5

6.5

1.5

7.0

3.1

1.5

4.3

1.5

4.6

ns

6.0

1.5

8.0

1.5

8.5

3.8

1.5

5.2

1.5

5.5

ns

5.0

1.5

7.0

1.5

7.5

3.3

1.5

4.6

1.5

4.9

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vce = 5.0V, + 25°C ambient and maximum loading.

10-80

IDT54/74FCT241A AND IDT54/74FCT244/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temp. Range

A

X

X

Device Type

Package

Process

y

Blank

Commercial

B

MIL-STD-883, Class B

P
D
SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

241
241A
244
244A

Octal Buffer/Line Driver
Fast Octal Buffer/Line Driver
Octal Buffer/Line Driver
Fast Octal Buffer/Line Driver

I 54
I 74

10-81

-55°C to + 125°C
O°Cto +70°C

FEATURES:

DESCRIPTION:

• IDT54/74FCT245 equivalent to FAST™speed;

The IDT54/74FCT245 and IDT54/74FCT245A are 8-bit noninverting, bidirectional buffers built using advanced CEMOS TM, a
dual metal CMOS technology. These bidirectional buffers have
3-state outputs and are intended for bus-oriented applications. The
TransmiVReceive (T/R) input determines the direction of data flow
through the bidirectional transceiver. Transmit (active HIGH)
enables data from A ports to B ports. Receive (active LOW) enables
data from B ports to A ports. The Output Enable (OE) Input, when
HIGH, disables both A and B ports by placing them in High Z
condition.

IDT54/74FCT245A 35% faster than FAST ™
• Equivalent to FAST™output drive over full temperature
and voltage supply extremes
• 10L = 64mA (commercial) and 48mA (military) for both ports
• CMOS power levels (5~W typo static)
• TTL input and output level compatible

• CMOS output level compatible
• Substantially lower input current levels than FAST ™(5~A max.)
• Non·inverting buffer transceiver
•
•
•
•

JEDEC standard pinout for DIP and LCC
Product available in Radiation Tolerant and Enhanced versions
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing# 5962-87629 is listed on this function. Refer to Section 21page 2-4.

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM

TItl
Ao
A1
A2
A3
A4
A5
As
A7
GND

Vcc

TItl

OE"
Be

(19)

81
82
83
84
85

(18)
(3)

A1

~

(16)
(5)
(15)

00 ~
0 ICC
-...
ct:ct:I-'>
I

I

I

I.

~

3 2

]4
]5
]s
]7

I

I

I

II

'-I

L..I

20

A4

"

(14)

19

Be
81
82

]8

(7)

A5

82

83

84

(13)
A

83
84

85

(8)

s

(12)

9 10 11 12 13

_

nnnnn

.t g moo 0

L20-2

:] 8
9 10 11 12 13

t.r"""1""""",

~,...,
I'

CP

I

I

I

I

I

I

o~f.;oo
(!)

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Do

Dl

D2

D4

D3

D5

D6

D7

CP

CEMOS Is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

DSC-4015/-

10-86
- - - - ---------------

DECEMBER 1987

IDT54/74FCT273/A FAST CMOS
OCTAL D FLIP-FLOP WITH CLEAR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

CAPACITANCE

(1)

COMMERCIAL
-0.5 to +7.0

MILITARY
-0.5 to +7.0

UNIT

SYMBOL

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

rnA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CIN

Input Capacitance

Cour

Output Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

Vour= OV

8

12

pF

NOTE:
1. This parameter is guaranteed by characterization data and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V: ~c = - 0.2V .
Commercial: TA = O°C to + 70°C; Vee = 5.0V ±5%
Military:TA = -55°C to +125°C; Vcc = 5.0V ±10%
MIN.

TYP,(2)

MAX.

UNIT

VIH

Input HIGH Level

Guaranteed Logic High Level

2.0

V

'lrL

Input LOW Level

Guaranteed Logic Low Level

0.8

V

VI = 2.7V

-

VI = 0.5V

-

-

-

VI = GND

-

-

-5

-

-0.7

-1.2

V

-

rnA

SYMBOL

TEST CONDITIONS (1)

PARAMETER

VI = \bc
IIH

Input HIGH Current
Vcc = Max.

IlL

Input LOW Current

'irK

Clamp Diode Voltage

\bc = Min., IN = -18mA

los

Short Circuit Current

Vec = MaxP), Vo = GND

-60

-120

Vcc = 3V, \1N = VLC or VHC ' 10H = -:-32~A

VHC

Vee

10H = -300~A

VHC

Vcc

10H = -12mA MIL.

2.4

4.3

10H= -15mA COM'L.

VOH

Output LOW Voltage

VOL

Output HIGH Voltage

= 3V, VIN

2.4

4.3

= VLCor VHC , IoL = 300~A

-

GND

VLC

IOL = 300~A

-

GND

Vt.c

0.3

0.5

0.3

0.5

200

-

Vcc = Min.
~N = ~Hor~L

IOL

= 32mA MIL.

IOL = 48mA COM'L.
VH

5(4)
-5(4)

-

Vcc = Min.
~N = ~HorVIL

Vcc

5

-

Input Hysteresis on Clock Only

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-87

~A

V

V

mV

IDT54/74FCT273/A FAST CMOS
OCTAL D FLIP-FLOP WITH CLEAR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= 0.2V; vHC = vcc

SYMBOL

- 0.2V
TEST CONDITIONS

PARAMETER

(1)

MIN.

Typ.(2)

MAX.

UNIT

Icc

Quiescent Power Supply Current

Vcc = Max.
\IN ~ VHC ; \IN :5 VLC
fcp = fl = 0

-

0.001

1.5

mA

~Icc

Power Supply Current Per TIL
Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

Dynamic Power Supply Current (4)

Vcc = Max.
Outputs Open
MR = Vcc
One Bit Toggling
50% Duty Cycle

\IN ~ VHC
\IN :5 VLC

-

0.15

0.25

mA/MHz

\IN ~ VHC
\IN :5 VLC
(FCT)

-

1.5

4.0

\IN = 3.4V
or
\IN = GND

-

2.0

6.0

ICCD

Vcc = Max.
Outputs Open
fcp= 10MHz,
50% Duty Cycle
MR = Vcc
One Bit Toggling
atfl = 5MHz
50% Duty Cycle
Total Power Supply Current (6)

Ic

mA
Vcc = Max.
Outputs Open
fcp= 10MHz,
50% Duty Cycle
"fJR = Vcc
Eight Bits Toggling
fl = 2.5MHz
50% Duty Cycle

\IN ~ VHC
VIN :5 VLC
(FCT)

-

3.75

7.8(5)

\IN = 3.4V
or
\IN = GND

-

6.0

16.8(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (1cp/2 + 11 NI )
Icc = Quiescent Current
~I cc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at 11
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

INPUTS

OPERATING MODE

OUTPUT

MR

CP

DN

~

Do - D7

Data Inputs

MR

Master Reset (Active LOW)

Reset (Clear)

L

X

X

L

CP

Clock Pulse Input (Active Rising Edge)

Load '1'

H

h

H

Load '0'

H

t
t

I

L

00

- 0

7

Data Outputs

H = HIGH voltage steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady rate
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don't Care
= LOW-to-HIGH clock transition

t

10-88

IDT54/74FCT273/A FAST CMOS
OCTAL D FLIP-FLOP WITH CLEAR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

CONDITION (1)

TYP.(3)

IDT54/74 FCT273
COM'L
MIL
MIN.(2) MAX.

MIN~2)

TYP.(3)

MAX.

IDT54/74FCT273A
COM'L
MIL
MIN.(2)

MAX.

MIN.(2)

UNIT
MAX.

tpLH
tpHL

Propagation Delay
Clock to Output

7.0

2.0

13.0

2.0

15.0

5.0

2.0

7.2

2.0

8.3

ns

tpLH
tpHL

Propagation Delay
fV1'RtoOutput

8.0

2.0

13.0

2.0

15.0

5.0

2.0

7.2

2.5

8.3

ns

tsu

Set-up Time
HIGH or LOW
Data to CP

3.0

3.0

-

3.5

-

1.0

2.0

-

2.0

-

ns

tH

Hold Time
HIGH or LOW
Data to CP

1.0

2.0

-

2.0

-

1.0

1.5

-

1.5

-

ns

tw

Clock Pulse Width
HIGH or LOW

4.0

7.0

-

7.0

-

3.0

6.0

-

6.0

-

ns

4.0

7.0

-

7.0

-

3.0

6.0

-

6.0

-

ns

3.0

4.0

-

5.0

-

1.5

2.0

-

2.5

-

ns

MR Pulse Width

tw

HIGH or LOW

tREM

Recovery Time
MAtoCP

CL = 50pF
RL = 5000

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type

X

P~:'~k
P
D
' - - - - - - - - - - - ; SO
L

'----------------1

10-89

Commercial
MIL-STD-883. Class B

E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

273
273A

Octal D Flip-Flop w/Clear
Fast Octal D Flip-Flop w/Clear

FEATURES:

DESCRIPTION:

• IDT54/74FCT299 equivalent to FAST 1M speed;
IDT54/74FCT299A 25% faster than FAST 1M
• Equivalent to FAST ™output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (5jJW typo static)
• TTL Input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5jJA max.)
• 8-input universal shift register
• JEDEC standard pinout for DIP and LCC
• Product available In Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class 8
• Standard Military Drawing# 5962-86862 is listed on this
function. Refer to Section 2/page 2-4.

The IDT54/74FCT299 and IDT54/74FCT299A are built using
advanced CEMOS TM, a dual metal CMOS technology. The
IDT54/74FCT299 and IDT54/74FCT299A are 8-input universal
shift/storage registers with 3-state outputs. Four modes of operation are possible; hold (store), shift left, shift right and load data.
The parallel load Inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Additional outputs are
provided for flip-flops 00-07 to allow easy serial cascading. A
separate active LOW Master Reset is used to reset the register.

PIN CONFIGURATIONS

~~~~c£

INDEX

••

I

""

,",

I

32U2019
1

1/0 6 ]4
1/0 4 ] 5
1/0 2 ] 6
1/0 0 :J 7
0 0 :J 8

L20-2

18[

DS 7

17 [:

07
1/0 7
1/0 5
1/0 3

16[
15 [:
14 [:

9

10 11

12 13

nnnnn
DIP/SOIC/CERPACK
TOP VIEW

~ ZW
0
0 c..
(!:lO

u

g-

FUNCTIONAL BLOCK DIAGRAM
LCC
TOPV IEW

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Devtce Technology. Inc.

10-90

DECEMBER 1987
DSC-4016/-

IDT54/74FCT299/A FAST CMOS
a-INPUT UNIVERSAL SHIFT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

COMMERCIAL
-0.5 to +7.0

CAPACITANCE
MILITARY
-0.5 to +7.0

UNIT

SYMBOL

V

TA

Operating
Temperature

Oto +70

-55 to +125

°c

TSIAS

Temperature
Under Bias

-55 to + 125

-65 to +135

°c

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°c

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

CIN

Input Capacitance

ClIO

I/O Capacitance

MAX, UNIT

CONDITIONS TYP,
VIN = OV

6

10

pF

Vour= OV

8

12

pF

NOTE:
1. This parameter is guaranteed by characterization data and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHe = Vee - 0.2V
Commercial: TA = O°C to + 70°C; 'to = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL
"'H
"'L
IIH

TEST CONDITIONS(l)

MIN.

TYPP)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic High Level

2.0

-

V

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

-

5

PARAMETER

VI = Vee

I~ut HIGH Current .
( xeept I/O pins)

VI = 2.7V
Vcc = Max.

IlL

IIH

VI = 0.5V

I~ut LOW Current

( xcept I/O pins)

Infcut HIGH Currents
(I 0 pins only)

IlL

"'K
los

VOH

Infcut LOW Currents
(I 0 pins only)

5(4)

-

-5(4)

-

-5

-

_15(4)
-15

-

VI = Vcc

VI = 0.5V
VI = GND

-

-

-1.2

V
mA

15
184)

Clamp Diode Voltage

Vec = Min., IN = -18mA

-

-0.7

Short Circuit Current

Vee = Max!3), Vo = GND

-60

-120

-

Vcc = 3V, VIN = VLC or VHe , IoH = -32 jJA

VHC

Vec

-

10H = -300jJA

VHC

Vec

10H = -12mA MIL.

2.4

4.3

10H = -15mA COM'L.

2.4

4.3

-

-

GND

VLC

10L = 300jJA

-

GND

VLC

10L = 32mA MIL.

-

0.3

0.5

10L = 48mA COM'L.

-

0.3

Output HIGH Voltage

Vee = Min.
VIN = VIH or VIL

Output LOW Voltage

Vcc = Min.
"'IN = "'IH or"'lL

I

VH
200
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-91

jJA

-

Vee = 3V, "'IN = VLC or VHe , 10L = 300jJA
VOL

-

VI = GND

VI = 2.7V
Vee = Max.

-

jJA

V

V

0.5

-

mV

IDT54/74FCT299/A FAST CMOS
a-INPUT UNIVERSAL SHIFT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS(1)

MIN.

TYP.(2)

MAX.

UNIT

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN e:: VHC ; "'IN ::S VLC
fcp = fl =0

-

0.001

1.5

mA

.6.lcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max .
VIN = 3.4V(3)

-

0.5

2.0

mA

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
OE l = OE2 = GND
MR = Vcc
So = Sl = Vcc
DS o = DS l = GND
One Bit Toggling
50% Duty Cycle

"'IN e:: VHC
VIN ::S VLC

-

0.15

0.25

mAl
MHz

"'IN e:: VHC
"iN ::S VLC
(FCT)

-

1.5

4.0

VIN = 3.4V
"iN = GND

-

2.0

6.0

ICCD

Ic

Vcc = Max.
Outputs Open
fcp= 1.0MHz
50% D\:!!y'Cycle
OEl = OE:! = GND
MR = Vcc
So = Sl = Vcc
DSo = DS 7 = GND
One Bit Toggling
atfl = 5MHz
50% Duty Cycle
Total Power Supply Current(6)

mA
Vcc = Max.
Outputs Open
fcp= 10MHz
50% Du'!y""Cycle
OEl = OE2 = GND
MR = Vcc
So = Sl = Vcc
DSo = DS7 = GND
Eight Bits Toggling
atfl = 2.5MHz
50% Duty Cycle

"'IN e:: VHC
"iN ::S VLC
(FCT)

-

3.75

7.8(5)

"iN = 3.4V
VIN = GND

-

6.0

16.8(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPLrrS + IDYNAMIC
Ic = Icc + .6. l cc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-92

IDT54/74FCT299/A FAST CMOS
a-INPUT UNIVERSAL SHIFT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS

INPUTS

DESCRIPTION

PIN NAMES

MR

Clock Pulse Input (Active Edge Rising)

CP

S1

So

RESPONSE

CP

Asynchronous Reset 0 0 -0 7 = LOVI

DSo

Serial Data Input for Right Shift

L

X

X

X

DS 7

Serial Data Input for Left Shift

H

H

H

I

Parallel Load; I/O -+On-+On

SO,S7

Mode Select Inputs

H

L

H

I

Shift Right; DS o -+0 0 , 0 0 -+0 1 , etc.

/ViR

Asynchronous Master Reset Input (Active LOW)

H

H

L

I

Shift Left; DS 7 -+0 7 • 0 7 -+0 6 • etc.

OE 1 • OE 2
1/00 - 1/0 7

3-State Output Enable Inputs (Active LOW)

H

L

L

X

Hold

0 0 .0 7

Serial Outputs

Parallel Data Inputs or 3-State Parallel Outputs

H = HIGH Voltage Level
L

= LOW Voltage Level

X = Don't Care

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT299A

IDT54/74 FCT299
SYMBOL

PARAMETER

CONDITION(11

COM'L.
TYP.(31

MIN.(21 MAX.

MIL.

MIL.

COM'L
TYP.(31

MIN~21

MAX.

UNIT

MIN.(21

MAX.

MIN.(21

MAX.

tpLH
tpHL

Propagation Delay
CP to 0 0 or 0 7

7.0

2.5

10.0

2.5

14.0

5.0

2.5

7.2

2.5

9.5

ns

tpLH
tpHL

Propagation Delay
CP to I/On

6.0

2.5

12.0

2.5

12.0

5.0

2.5

7.2

2.5

9.5

ns

t pHL

Propagation Delay
MR to 0 0 or 0 7

7.0

2.5

10.0

2.5

10.5

5.0

2.5

7.2

2.5

9.5

ns

7.0

2.5

15.0

2.5

15.0

6.0

2.5

8.7

2.5

11.5

ns

tpHL

pro~ation Delay

R to I/On

tpZH
t pZL

Output Enable Time
~to I/On

8.0

1.5

11.0

1.5

15.0

5.5

1.5

6.5

1.5

7.5

ns

tpHZ
tpLZ

Output Disable Time
OEto I/On

5.5

1.5

7.0

1.5

9.0

4.0

1.5

5.5

1.5

6.5

ns

tsu

Set-up Time
HIGH or LOW
So or Sl to CP

2.0

8.5

-

8.5

-

2.5

4.0

-

5.0

-

ns

tH

Hold Time
HIGH or LOW
So or Sl to CP

0

0

-

0

-

-1.5

0

-

0

-

ns

tsu

Set-up Time HIGH
or LOW I/On.
DS o or DS 7 to CP

0.5

5.5

-

5.5

-

2.5

4.0

-

5.0

-

ns

tH

Hold Time HIGH
or LOW I/On.
DS o or DS 7 to CP

0

2.0

-

2.0

-

1.0

2.0

-

2.0

-

ns

tw

CP Pulse Width
HIGH or LOW

7.0

7.0

-

7.0

-

4.0

5.0

-

6.0

-

ns

7.0

7.0

-

7.0

-

4.0

5.0

-

6.0

-

ns

7.0

7.0

-

7.0

-

4.0

5.0

-

6.0

-

ns

tw
tREM

MR Pulse Width
LOW
Recovery Time
MRtoCP

C L = 50pF
RL = 5000

NOTES:

1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.

10-93

IDT54/74FCT299/A FAST CMOS
a-INPUT UNIVERSAL SHIFT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXX><
Device Type

X
Process

I

I Blank

~B

P
D

MIL-STD-SS3, Class B

L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

299
299A

B-Input Universal Shift Register
Fast B-Input Universal Shift Register

L - - - - - - - - - - - - i SO

10-94

Commercial

+ 125°C

54

-55°C to

74

O°C to + 70°C

FEATURES:

DESCRIPTION:

• IDT54/74FCT373 equivalent to FAST TN speed;
IDT54/74FCT373A 35% faster than FAST TN
• Equivalent to FAST TN output drive over full temperature
and voltage supply extremes
• 10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST TN (5~A max.)
• Octal transparent latch with enable
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87644 is listed on this
function. Refer to Sction 2/page 2-4.

The IDT54/74FCT373 and IDT54/74FCT373A are 8-bit latches
built using advanced CEMOS TN, a dual metal CMOS technology.
These octal latches have 3-state outputs and are intended for busoriented applications. The flip-flops appear transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the set-up times is latched. Data..§>pears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the bus output
is in the high impedance state.

PIN CONFIGURATIONS

0 ..
o0afo
o~o

INDEX

OE

Vcc

00

07

Do
Dl
01
°2
D2
D3
03
GND

D7
D6
06
05
D5
D4

I

I

L.,...J

Dl

]4

I

I

.......

I

I

I

I

I

"1

L....a

........

3 2 U 20 19
1

0 1 :] 5
°2 ]6
D2 :] 7
D3 :] 8

18C D7
D6
16 [: 0 6
15 [: 0 5
14[: D5
17 [:

L20-2

~~~~~

°4
LE

mJ

o~~oo
(!)

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM

CEMOS is a trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-4017/-

10-95

IDT54/74FCT373/A FAST CMOS
OCTAL TRANSPARENT LATCH

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

-0.5 to +7.0

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

SYMBOL

UNIT
V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA= +25°C, f = 10MHz)

PARAMETER(l)

CIN

Input Capacitance

COUT

Output Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; 'tc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc· = 5.0V±10%
SYMBOL
"'H
"'L
IIH

TEST CONDITIONS(l)

PARAMETER
Input HIGH Level

Guaranteed Logic High Level

Input LOW Level

Guaranteed Logic Low Level

Input HIGH Current
Vcc = Max.

IlL

Input LOW Current

loz

Off State (High Impedance)
Output Current

Vec = Max.

VIK

Clamp Diode Voltage

Vee = Min., IN

los

Short Circuit Current

VOH

VOL

Output HIGH Voltage

Output LOW Voltage

TYP.(2)

MAX.

UNIT

2.0

-

-

V
V

MIN.

-

-

0.8

VI = Vcc

-

-

5

VI = 2.7V

-

-

5(4)

VI = 0.5V

-

-

-5(4)

VI = GND

-

-

-5

Vo = Vcc

-

-

10

Vo = 2.7V

-

-

10(4)

-

-10(4)
-10

IJA

IJA

Vo = 0.5V

-

Vo = GND

-

-

-

-0.7

-1.2

V

Vcc = MaxP), Vo = GND

-60

-120

mA

Vec = 3V, '-"N = VLC or VHC , 10H = -32JJA

VHC

Vce

-

10H = -300IJ A

VHC

Vee

-

10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

4.3

-

-

GND

VLe

10L = 300IJ A

-

GND

VLC

10L = 32mA MIL.

-

0.3

0.5

0.3

0.5

= -18mA

Vec = Min.
'-"N = '-"H or '-"L
Vec

= 3V, '-"N

Vec

= Min.

'-"N

= VLC or VHC , 10L = 300JJA

= '-"H or'-"L

10L = 48mA COM'L.

VH
200
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-96

-

V

V

mV

IDT54/74FCT373/A FAST CMOS
OCTAL TRANSPARENT LATCH

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

TEST CONDITIONS(1)

PARAMETER

Icc

Quiescent Power Supply Current

Vee = Max.
'-"N ~ VHC ; '-"N ::5 VLC
fl = 0

~Icc

Power Supply Current Per TTL
Inputs HIGH

Vcc = Max.
'-"N = 3.4V(3)

Dynamic Power Supply Current(4)

Vcc = Max.
Outputs Open
OE = GND
LE = Vcc
One Input Toggling
50% Duty Cycle

ICCD

Vcc = Max.
Outputs Open
fl = 10MHz,
50% Duty Cycle
OE = GND
LE = Vcc
One Bit Toggling

MIN.

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

'-"N ~ VHC
V1N ::5 VLC

-

0.15

0.25

mAl

'-"N ~ VHC
'-"N ::5 VLC
(FCn

-

1.5

4.0

VIN = 3.4V
'-"N = GND

-

1.8

5.0

MHz

mA

Total Power Supply Current(6)

Ic

Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
OE = GND
LE = Vcc
Eight Bits Toggling

V1N ~ VHC
VIN ::5 VLC
(FCn

-

3.0

6.5(5)

'-"N = 3.4V
'-"N = GND

-

5.0

14.5(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Iee DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

INPUTS

OUTPUTS

Do - D7

Data Inputs

On

LE

OE

On

LE

Latch Enables Input (Active HIGH)

H

H

L

H

ITE

Output Enables Input (Active LOW)

L

H

L

L

3-State Latch Outputs

X

X

H

Z

00

-

07

H
L
X
Z

10-97

= HIGH Voltage Level

= LOW Voltage Level
= Don't Care
= HIGH Impedance

IDT54n4FCT373/A FAST CMOS
OCTAL TRANSPARENT LATCH

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74FCT373
SYMBOL

PARAMETER

CONDITION(1)

,COM'L
TYP.(3)

IDT54/74 FCT373A
MIL

MIN.(2) MAX.

COM'L
TYP.(3)

MIN!2)

MAX.

MIN.(2)

MIL

UNIT

MAX.

MIN.(2)

MAX.

tpLH
tpHL

Propagation Delay
Dn to On

5.0

1.5

8.0

1.5

8.5

4.0

1.5

5.2

1.5

5.6

ns

tpZH
tpzL

Output Enable
Time

7.0

1.5

12.0

1.5

13.5

5.5

1.5

6.5

1.5

7.5

ns

tpHZ
tpLZ

Output Disable
Time

6.0

1.5

7.5

1.5

10.0

4.0

1.5

5.5

1.5

6.5

ns

tpLH
t pHL

Propagation Delay
LE to On

9.0

2.0

13.0

2.0

15.0

7.0

2.0

8.5

2.0

9.8

ns

tsu

Set-up Time
HIGH or LOW
Dn to LE

1.0

2.0

-

2.0

-

1.0

2.0

-

2.0

-

ns

tH

Hold Time
HIGH or LOW
Dn to LE

1.0

1.5

-

1.5

-

1.0

1.5

-

1.5

-

ns

tw

LE Pulse Width
HIGH or LOW

5.0

6.0

-

6.0

-

4.0

5.0

-

6.0

-

ns

CL = 50pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vec = 5.0V, + 25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXX)(

Device Type

Commercial
MIL-SID-883, Class B

~----------i

L----------------I
L-___________________

~

10-98

P
D
SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

373
373A

Octal Transparent Latch
Fast Octal Transparent Latch

54

-55°C to

74

O°C to

+ 125°C

+ 70°C

FEATURES:

DESCRIPTION:

• IDT54{74FCT374 equivalent to FAST™speed;
IDT54/74FCT374A 35% faster than FAST ™
• Equivalent to FAST™output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™(5~A max.)
• Positive, edge-triggered Master/Slave, D-type flip-flops
• Buffered common clock and buffered common three-state
control
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87628 is listed on this
function. Refer to Section 21page 2-4.

The IDT54{7 4FCT374 and IDT54{7 4 FCT374A are 8-bit registers
built using advanced CEMOS TM, a dual metal CMOS technology.
These registers consist of eight D-type flip-flops with a buffered
common clock and buffered 3-state output control. When the output enable (OE) input is LOW, the eight outputs are enabled. When
the OE input is HIGH, the outputs are in the three-state conditions.
Input data meeting the set-up and hold time requirements of the
D inputs is transferred to the 0 outputs on the LOW-to-HIGH transition of the clock input.

PIN CONFIGURATIONS

o0oro0 >-0
8 ..

tNDEX

OE'
00
Do
Dl
01
O2
D2
D3
03
GND

Vee
07
D7
D6
06
Os
Ds
D4
04
CP

o

UUIILJLJ
3 2 LJ 20 19

18 r:

]4
]s

:J 6
:J 7

L20-2

17 [:

D7
D6

16 [:

06

IS [:

Os
Ds

14 r:

]8

IDJ

9 10 11 12 13

nnnnn

c5'~ 500'
CJ

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
D3

D2

D4

Ds

D6

D7

CP
CLOCK

OE'
OUTPUT
ENABLE

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of FairChild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 19871nlegrated DevIce Technology, Inc.

10-99

DECEMBER 1987
DSo.4018/-

IDT54/74FCT374/A FAST CMOS
OCTAL D REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTEAM

RATING
Terminal Voltage
with Respect to
GND

COMMERCIAL
-0.5 to +7.0

CAPACITANCE
MILITARY
-0.5 to +7.0

SYMBOL

UNIT

CIN

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to + 125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance

CONDITIONS TYP.
VIN = OV

MAX. UNIT

6

10

pF

COUT
Output Capacitance
VOUT= OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Fo"owing Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL

TEST CONDITIONS (1)

PARAMETER.

TYP.(2)

MAX.

UNIT

'-jH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic Low Level

-

0.8

V

VI = Vec

-

-

5

VI = 2.7V

-

-

5(4)

IIH

Input HIGH Current
Vee

IlL

= Max.

Input LOW Current

VI = 0.5V

-

-

_5(4)

= GND

-5

-

-

Vo = Vee

-

-

Vo = 2.7V

-

-

10(4)

-

_10(4)

VI

loz

Off State (High Impedance)
Output Current

Vce

= Max.

'-jK

Clamp Diode Voltage

Vec

= Min., IN

los

Short Circuit Current

Vcc = MaxP! Vo = GND

VOH

Output HIGH Voltage

-

-

-10

-

-0.7

-1.2

V

-60

-120

-

mA

VHC

Vec

-

= -300)JA

VHC

\bc

-

10H = -12mA MIL.

2.4

4.3

-

10H

= 3V, \'IN = VLe

= -15mA COM'L.

2.4

4.3

-

GND

VLe

GND

VLC

= 32mA MIL.

-

0.3

0.5

10L = 48mA COM'L.

-

0.3

0.5

10H
Vec

IoL =

or VHC '

300jJA

10L = 300)JA
VOL

Output LOW Voltage

Vee = Min.
\'IN = \'IH or\'lL

10L

-

VH
200
Input HysteresiS on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value speCified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-100

jJA

= GND

orVHc.l oH = -32jJA

Vce = Min.
\'IN = \'IH or\'lL

10

-

= -18mA

= 3V, \'IN = VLC

jJA

Vo = 0.5V
Vo

Vec

MIN.

-

V

V

mV

IDT54/74FCT374/A FAST CMOS
OCTAL D REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; '4ic = Vcc - 0.2V
SYMBOL

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN e! VHC : VIN :5 VLC
fcp = fl = 0

.0.lcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
BE = GND
One Bit Toggling
50% Duty Cycle

Ic

Total Power Supply Current(6)

Typ.(2)

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

"iN e! VHC
"iN :5 VLC

-

0.15

0.25

mA!
MHz

"iN e! VHC
"iN :5 VLC
(FCT)

-

1.5

4.0

VIN = 3.4Vor
VIN = GND

-

2.0

6.0

TEST CONDITIONS(1)

PARAMETER

Vcc = Max.
Outputs Open
fcp = 10MHz
29.% Duty Cycle
OE = GND
One Bit Toggling
atf l = 5MHz
50% Duty Cycle

MIN.

UNIT

mA

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle

"iN e! VHC
"iN :5 VLC
(FCT)

-

3.75

7.8(5)

VIN = 3.4Vor
VIN = GND

-

6.0

16.8(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25 0 C ambient and maximum loading.
3. Per TTL driven input (\ijN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .0. l cc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.0. l cc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

INPUTS
FUNCTION

DI

The D flip-flop data inputs.

CP

Clock Pulse for the register. Enters data on the
LOW-to-HIGH transition.

01

The register three-state outputs.

BE

Output Control. An active-LOW three-state control
used to enable the outputs. A HIGH level input
forces the outputs to the high impedance (off)
state.

CLOCK

01

0,

Q,

Hi-Z

H
H

L
H

X

X

Z
Z

NC
NC

~

LOAD
REGISTER

L
L
H
H

L
H
L
H

L
H
Z
Z

H
L
H
L

H
L
X
Z
~

NO =

10-101

OUTPUTS INTERNAL

OE

--iT
--iT
--iT

HIGH
LOW
Don't Care
High Impedance
LOW-to-HIGH transition
No Change

IDT54/74FCT374/A FAST CMOS
OCTAL D REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IOT54/74 FCT374A

IOT54/74FCT37 4
SYMBOL

PARAMETER

CONDITION(1)

COM'L.
TYpP)

MINP) MAX.

MIL.

COM'L.

MIL.
MIN~2)

MAX.

UNIT

TYPP)

MIN.(2)

MAX.

MIN.(2)

MAX.

tpLH
tpHL

Propagation Delay
CP to On

6.6

2.0

10.0

2.0

11.0

4.5

2.0

6.5

2.0

7.2

ns

tpZH
tpZL

Output Enable
Time

9.0

1.5

12.5

1.5

14.0

5.5

1.5

6.5

1.5

7.5

ns

tpHZ
tpLZ

Output Disable
Time

6.0

1.5

8.0

1.5

8.0

4.0

1.5

5.5

1.5

6.5

ns

tsu

Set-upTime
HIGH or LOW
Dn to CP

1.0

2.0

-

2.5

-

1.0

2.0

-

2.0

-

ns

tH

Hold Time
HIGH or LOW
Dn to CP

0.5

2.0

-

2.0

-

0.5

1.5

-

1.5

-

ns

tw

CP Pulse Width
HIGH or LOW

4.0

7.0

-

7.0

-

4.0

5.0

-

6.0

-

ns

CL = 50pF
RL = soon

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type

X
Process/
Temperature

"MY:'Mk

'------------j
'-----------------i

10-102

Commercial
MIL-STO-883, Class B

P
D
SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

374
374A

Octal D Register (3-state)
Fast Octal D Register

54

-55°C to + 125°C

74

O°C to + 70°C

FEATURES:
• IDT54/74FCT377 equivalent to FAST™speed;
IDT54/74FCT377A 45% faster than FAST™
• Equivalent to FAST ™output drive over full
temperature and voltage supply extremes
• laL = 48mA (commercial) and 32mA (military)
• CMOS power levels (5jJW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5jJA max.)
• Octal D flip-flop with clock enable
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-87627 is pending listing on
this function. Refer to Section 2/page 2-4.

DESCRIPTION:
The IDT54/74FCT377 and IDT54/74FCT377A are octal D flipflops built using advanced CEMOS TM, a dual metal CMOS technology. The IDT54/7 4AFCT377 and IDT54/7 4 FCT377A have eight
edge-triggered, D-type flip-flops with individual D inputs and 0
outputs. The common buffered Clock (efl input loads all flip-flops
simultaneouslywhen the Clock Enable (CE) is LOW. The register is
fully edge-triggered. The state of each D input, one set-up time
before the LOW-to-HIGH clock transition, is transferred to the
corresponding flip-flop's 0 output. The CE input must be stable
only one set-up time prior to the LOW-ta-HIGH clock transition for
predictable operation.

PIN CONFIGURATIONS

cr

Vcc

00

c5'o~~o

INDEX

07

Do
D1

1'1

......

01

D7
De
Oe

:] 5

O2

05

]e

D2
D3

D5
D4

03

04

GND

:] 4

I

L.....J

I.

II

I

I

L-I

I

I

L.J

3 2 U 20 19
1

16C

D7

17[:

De

1e [:

Oe

:] 7

15[:

:] 6

14C

05
D5

L20-2

IDl

~~N~~

CP

o~~oo
0

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Do

Dl

00

D2

D3

D4

D5

D6

D7

01

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1967 Integrated Device Technology.

DECEMBER 1987
OSC-4019/-

Inc.

10-103

IDT54/74FCT377/A FAST CMOS
OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA= +25°C, f = 1.0MHz)
PARAMETER(1)
CONDITIONS TYP.
SYMBOL

ABSOLUTE MAXIMUMRATINGS(1)
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TSIAS

Temperature
Under Bias

TSTG

Storage
Temperature

COMMERCIAL
-0.5 to +7.0

o to

+70

MILITARY
-0.5 to +7.0

UNIT

CIN

V

-55 to + 125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Input Capacitance

VIN = OV

MAX. UNIT

6

10

pF

COUT
Output Capacitance
VOUT= OV
12
8
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT. INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = O.2V; VHC = Vcc - 0.2V
Commercial: TA == O°C to + 70°C; 'bc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10'Yo
SYMBOL

TEST CONDITIONS (1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

~H

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

~L

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

VI = Vcc

-

-

5

VI = 2.7V

-

-

5(4)

VI = 0.5V

-

-

-5(4)

VI = GND

-

-

-5

Vo = Vcc

-

-

10

Vo = 2.7V

-

-

10(4)

Vo = 0.5V

-

-

-1014)

Vo = GND

-10

IIH

Input HIGH Current
Vcc = Max.

IlL

Input LOW Current

~A

loz

Off State (High Impedance)
Output Current

Vcc = Max.

-

-

~K

Clamp Diode Voltage

Vcc = Min., IN = -18mA

-

-0.7

-1.2

V

los

Short Circuit Current

Vcc = MaxP), Vo = GND

-60

-120

mA

Vcc = 3V, \'IN = VLC or VHC , 10H = -32~

VHC

Vcc

-

10H = -300~A

VHC

Vcc

-

10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

VOH

Output HIGH Voltage

Vcc = Min.
\'IN = \'IHor \'IL
Vcc = 3V, \'IN

VOL

Output LOW Voltage

= VLC

2.4

4.3

-

or VHC , 10L = 300~

-

GND

VLC

10L = 300~A

Vcc = Min.
\'IN = \'IH or \'IL

-

GND

VLC

= 32mA MIL.

-

0.3

0.5

10L = 48mA COM'L.

-

0.3

0.5

10L

VH
Input Hysteresis on Clock Only
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-104

-

~A

V

V

mV

IDT54/74FCT377/A FAST CMOS
OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS (1)

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ?: VHC ; VIN ~ VLC
fcp = fl = 0

b..lcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
CE = GND
One Bit Toggling
50% Duty Cycle

ICCD

Ic

Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
CE = GND
One Bit Toggling
atf l = 5MHz
50% Duty Cycle

MIN.

Typ.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

\'IN ?: VHC
\'IN ~ VLC

-

0.15

0.25

mAl

\'IN ?: VHC
\'IN ~ VLC
(AHCT)

-

1.5

4.0

VIN = 3.4Vor
VIN = GND

-

2.0

6.0

MHz

mA

Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fcp = 1.0MHz
50% Duty Cycle
CE = GND
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle

\'IN ?: VHC
\'IN ~ VLC
(AHCT)

-

3.75

7.8(5)

V IN = 3.4Vor
VIN = GND

-

6.0

16.8(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + b..lcc DHNT + ICCD (fcp/2 + ~ NI )
Icc = Quiescent Current
b..lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N, = Number of Inputs at f,
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

OPERATING MODE

Do-D7

Data Inputs

CE

Clock Enable (Active LOW)

Load "1"

0 0 -0 7

Data Outputs

Load "0"

CP

Clock Pulse Input
Hold (Do Nothing)

INPUTS

OUTPUTS

0

CP

CE

t
t
tX

I

h

I

I

L

h
H

X
X

No Change
No Change

D

H

H = HIGH Voltage Level
h = HIGH Voltage Level one setup time priorto the LOW-to-HIGH Clock
Transition
L = LOW Voltage Level
= LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
X = Immaterial

t

10-105

= LOW-to-HIGH Clock Transition

IDT54/74FCT377/A FAST CMOS
OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74 FCT377
SYMBOL

PARAMETER

CONDITION(1)

Typ~3)

COM'L
MIN.(2) MAX.

I DT54/74FCT377A
MIL

COM'L
TYP!3)

MIN~2)

MAX.

MIL

UNIT

MIN.(2)

MAX.

MIN.(2)

MAX.

tplH
tpHl

Propagation Delay
CPto On

7.0

2.0

13.0

2.0

15.0

5.0

2.0

7.2

2.0

8.3

ns

tsu

Set-upTime
HIGH or LOW
On to CP

1.0

2.5

-

3.0

-

1.0

2.0

-

2.0

-

ns

tH

Hold Time
HIGH or LOW
Onto CP

1.0

2.0

-

2.5

-

1.0

1.5

-

1.5

-

ns

tsu

Set-upTime
HIGH or LOW
cr to CP

1.5

3.0

-

3.0

-

1.0

2.0

-

2.0

-

ns

tH

Hold Time
HIGH or LOW
cr to CP

3.0

4.0

-

5.0

-

1.0

2.0

-

2.0

-

ns

Clock Pulse
Width, LOW

4.0

7.0

-

7.0

-

4.0

6.0

-

7.0

-

ns

tw

Cl = 50pF
Rl = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXX FCT
Temp. Range

XXXX
Device Type

X
Process

I

I Blank

~B

MIL-STD-883, Class B

P
D
E
SO
L

Plastic DIP
CERDIP
CERPACK
Small Outline IC
Leadless Chip Carrier

377

Octal D Flip-Flop w/Clock Enable
Fast Octal D Flip-Flop w/Clock Enable

54

-55°C to + 125°C

L . . - - - - - - - - - - - - - - - - i 377A

10-106

Commercial

FEATURES:

DESCRIPTION:

• IDT54/74FCT399 equivalent to FAST™ speed;
IDT54/74FCT399A 30% faster than FAST ™
• Equivalent to FAST ™pinout/function and output drive over full
temperature and voltage supply extremes

Both these devices are high-speed quad dual-port registers.
They select four bits of data from either of two sources (Ports) under
control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH
transition of the Clock input (CP). The 4-bit D-type output register is
fully edge-triggered. The Data inputs (lox, I,x) and Select input (S)
must be stable only one set-up time prior to, and hold time after,
the LOW-to-HIGH transition of the Clock input for predictable
operation.

•
•
•
•
•
•
•

IOL = 48mA (commercial) and 32mA (military)
CMOS power levels (5~W typo static)
TTL input and output level compatible
CMOS output level compatible
Available in 16-pin DIP and Sale, and 20-pin Lee
Military product compliant to MIL-STD-883, Class B
Product available in Radiation Tolerant and Enhanced versions

FUNCTIONAL BLOCK DIAGRAM

lOA

S
QA
IIA

IDI

loB
QB
liB

loc
Qc
Ilc

100

Qo
110

CP

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
oSC-4023/-

1987 Integrated Device Technology. Inc.

10-107

IDT54FCT399/A AND 1DT74FCT399/A FAST CMOS
QUAD DUAL-PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

cf~g~a

INDEX
S
QA

Vee
QO

lOA

100

11A
11B

110
11C
lac

lOB
QB

3

I 1
......

I

I

I

I

I.

1'--'

2 U

I

.......

20 19

lOA ] 4

18 [:

] 5

17[

110

16 [:

NC

15 [:

IIC

14[

lac

IIA
NC

]

6

L20-2

liB ]7
lOB ] 8

QC ·
CP

GND

Cl
t I
'-I

100

9 10 11 12 13

nnnnn

O'cng ::?a
LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

LOGIC SYMBOL

PIN DESCRIPTION
PIN NAMES
S

S
CP

FUNCTIONAL TABLE
INPUTS

OUTPUTS

S
I

10
I

11
X

Q

I

h

X

H

L

h

X

I

L

h

X

h

H

H = HIGH Voltage Level
L = LOW Voltage Level
h = HIGH Voltage Level one set-up time prior to the LOW-to-HIGH clock
transition
= LOW Voltage Level one set-up time prior to the LOW-to-HIGH clock
transition
X = Immaterial

10-108

DESCRIPTION
Common Select Input

CP

Clock Pulse Input (Active Rising Edge)

lOA -100

Data Inputs from Source 0

11A -110

Data Inputs from Source 1

QA - Q o

Register True Outputs

IDT54FCT399/A AND 1DT74FCT399/A FAST CMOS
QUAD DUAL·PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

COMMERCIAL
-0.5 to +7.0

MILITARY
-0.5 to +7.0

V

TA

Operating
Temperature

TSIAS

Temperature
Under Bias

TSTG

Storage
Temperature

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

o to

-55 to +125

°C

-55 to + 125

-65 to +135

°C

-55 to +125

-65 to + 150

°C

+ 70

SYMBOL

UNIT

(TA = +25°C, f

PARAMETER(l)

CIN

Input Capacitance

C OUT

Output Capacitance

= 1.OMHz)

CONDITIONS TYP.

= OV
VOUT = OV
VIN

MAX, UNIT

6

10

pF

8

12

pF

NOTE:
1. This parameter is guaranteed by characterization data and not
tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V ±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V ±10%
SYMBOL

TEST CONDITIONS (1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

"jH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

"jL

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

-

-

5

-

-

5(4)

-

_5(4)

VI
IIH

Input HIGH Current
Vcc

IlL

"'K
los

VOH

VOL

VI

= Max.

VI

Input LOW Current
Clamp Diode Voltage
Short Circuit Current

Output HIGH Voltage

Output LOW Voltage

VI

= 'tc
= 2.7V
= 0.5V
= GND

= Min., IN = -18mA
Vec = Max~3), Vo = GND
Vcc = 3V, '-"N = VLC or VHC , 10H = -32jJA
10H = -300jJA
Vcc = Min.
10H = -12mA MIL.
'-"N = '-"H orVIL
10H = -15mA COM'L.
Vcc = 3V, '-"N = VLC or VHC , 10L = 300jJA
10L = 300jJA
Vcc = Min.
10L = 32mA MIL.
VIN = '-"H or "'IL
10L = 48mA COM'L.
Vcc

-

-

-

-5

-

-0.7

-1.2

V

-60

-120

mA

VHC

Vcc

-

VHC

'to

-

2.4

4.3

-

2.4

4.3

--

-

GND

VLC

-

GND

VLC

-

0.3

0.5

-

0.3

0.5

V

V

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-109

jJA

I DT54 FCT399/A AND I DT74FCT399/A FAST CMOS
QUAD DUAL-PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS (1)

MIN.

TYP.(2)

MAX.

UNIT

Icc

Quiescent Power Supply Current

Vec = Max.
VIN ~ VHC ; \IN :5 VLC
fcp = fl = 0

-

0.001

1.5

mA

.6olcc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

"'N ~ VHC
\IN :5 VLC

-

0.15

0.25

mA/MHz

"'N ~ VHC
\IN :5 VLC
(FCT)

-

1.5

4.0

-

2.0

6.0

ICCD

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
One Input Toggling
atfl = 5MHz
50% Duty Cycle
S = Steady State

Ic

VIN = 3.4V
VIN

~r GND

Total Power Supply Current(6)

mA
\bc= Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
Four Inputs Toggling
atf l = 5MHz
50% Duty Cycle
S = Steady State

"'N ~ VHC
\'IN :5 VLC
(FCT)

-

3.75

7.75(5)

VIN = 3.4V
or
VIN = GND

-

5.0

12.75(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested .
. 6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .6olcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.601 cc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-110

IDT54FCT399/A AND IDT74FCT399/A FAST CMOS
QUAD DUAL-PORT REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54FCT399A

IDT54FCT399
SYMBOL

PARAMETER

CONDITIONS !>---J
:: -!> !>---J
:: -!>!>---J
:: -!> !>---J
:: -!> !>---J
:: -!> !>---J
:: -!> !>---J
:: -!> !>---J

°A=B

B7
A7
Be
Ae
B5
A5
B4
A4

GND

DIP/SOIC/CERPACK
TOP VIEW

INDEX
U U II U
3

A1
B1
A2
B2
A3

:J 4
] 5
] e
] 7
] 8

2

U

U

20 19
18 [:

17 [:

L20-2

1e [:
15[
14 [

B7
A7
Be
Ae

B5

TA=B

~----------------~

LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 In1egrated Device Technology, Inc.

DECEMBER 1987
DSC-4024/-

10-113

IDT54/74FCT521/A/B FAST CMOS
8-BIT IDENTITY COMPARATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

-0.5 to +7.0

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

SYMBOL
C IN

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lour

DC Output Current

120

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance

CONDITIONS TYP.
VIN':" OV

MAX. UNIT

6

10

pF

Cour
Output Capacitance
8
Vour= OV
pF
12
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = O.2V; VHC = Vec - 0.2V
Commercial: TA = O°C to + 70°C; Vee = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL
"'H

"'L
IIH

MIN.

TYP.(2)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic High Level

2.0

-

V

Input LOW Level

Guaranteed Logic Low Level

-

0.8

V

TEST CONDITIONS(1)

PARAMETER

-

-

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

-0.7

Short Circuit Current

Vee = MaxP), Vo = GND

-60

-120

Vee = 3V, \'IN = VlC or VHe , 10H = -32~

VHC

Vee

-

Input HIGH Current
Vee = Max.

IlL

"'K

los

VOH

Input LOW Current

Output HIGH Voltage

Vee = Min.
\'IN = \'IH or\'lL

VI =\bc

-

VI = 2.7V

-

VI = 0.5V

-

VI = GND

Output LOW Voltage

Vcc = Min.
\'IN = \'IH or\'lL

~A

-5
-1.2

V
mA

icH = -300~A

VHC

Vcc

-

2.4

4.3

-

icH = -15mA COM'L.

2.4

4.3

-

GND

VlC

IoL = 300pA

-

GND

VLC

IoL = 32mA MIL.

-

0.3

0.5

Iol = 48mA COM'L.

-

0.3

0.5

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-114

5(4)
-5(4)

icH = -12mA MIL.

Vee = 3V, \'IN = VlC or VHC ' IOL = 300J.lA
VOL

5

V

V

IDT54/74FCT521/A/B FAST CMOS
8-BIT IDENTITY COMPARATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V· VHC = Vcc - 0.2V
SYMBOL

Quiescent Power Supply Current

Vcc = Max.
VIN ;::: VHC ; \.'IN ::;; VLC
fl = 0

Power Supply Current Per TTL
Inputs HIGH

Vcc = Max.
\.'IN = 3.4V(3)

ICCD

Dynamic Power Supply Current (4)

Vcc = Max.
Outputs Open
One Input Toggling
50% Duty Cycle

Ic

Total Power Supply Current (6)

Vcc = Max.
Outputs Open
fl = 10MHz,
50% Duty Cycle

Icc

.6. Icc

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

\.'IN ;::: VHC
\.'IN ::;; VLC

-

0.15

0.25

mA/MHz

\.'IN;::: VHC
\.'IN ::;; VLC (FCT)

-

1.5

4.0(5)

\.'IN = 3.4V
\.'IN = GND

-

1.8

4.8(5)

TEST CONDITIONS

PARAMETER

MIN.

(1)

mA

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable. but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .6.lcc DHNT + ICCD (fcp/2 + fl N1 )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N 1 = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
Ao - A7
!lo - S7
IA = B
0A= B

TRUTH TABLE
INPUTS

DESCRIPTION
Word A Inputs
Word S Inputs
Expansion or Enable Input (Active LOW)
Identity Output (Active LOW)

IA

OUTPUT
A,B

=B

0A=

A = S*
Ai'S
A = S*
A,foS

L
L
H
H

B

L
H
H
H

H = HIGH Voltage Level
L = LOW Voltage Level
*Ao = So. Al = B 1 , A2 = S2' etc.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT521
SYMBOL

PARAMETER

CONDITION(l)
TYp,<3)

tpLH
tpHL

Propagation Delay
An or Sn to OA = B

tpLH
tpHL

P.ropagatio.!] Delay
IA = B to 0A = B

CL = 50pF
RL = 500n

COM'L.
MIN~2)

MAX.

IDT54/74FCT521A
MIL.

MIN.(2)

TYp,<3)

MAX.

COM'L.
MIN.(2)

MAX.

UNIT

MIL.
MIN~2)

MAX.

7.0

1.5

11.0

1.5

15.0

5.5

1.5

7.2

1.5

9.5

ns

5.0

1.5

10.0

1.5

9.0

4.4

1.5

6.0

1.5

7.8

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.

10-115

IDT54/74FCT521/AIB FAST CMOS
8-BIT IDENTITY COMPARATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(CONTINUED)
I DT54/74FCT521 B
SYMBOL

CONDITION (1)

PARAMETER

Propagation Delay
An or Bn to OA = B
P.r:opagatio.!J Delay
IA = B to 0A = B

CL = 50pF
RL = 5000

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXX FCT
Temp. Range

XXX)(

Device Type

Commercial
MIL-STO-883, Class B
P
D
'------------\ E
L
SO
521
' - - - - - - - - - - - - - - - - - ; 521A
521 B

10-116

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
8-Bit Comparator
Fast 8-Bit Comparator
Very Fast a-Bit Comparator

FEATURES:

DESCRIPTION:

• IDT54/74FCT533 10.0ns max. clock to output;
IDT54/74FCT533A 5.2n5 max. clock to output
• Equivalent to FAST™ output drive over full temperature
and voltage supply extremes
• 10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5}JW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5}JA max.)
• Octal transparent latch with 3-state output
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT533 and IDT54/74FCT533A are octal transparent latches built using advanced CEMOS TM, a dual metal
CMOS technology. The IDT54/74FCT533 and IDT54/74FCT533A
consist of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the set-up times is latched. Data~pears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the bus output
is in the high impedance state.

PIN CONFIGURATIONS
Vcc

00

07

DO
D1

D7
D6

01

O2

06
05

D2
D3

D5
D4

03
GND

ora

a

INDEX
~

0,....,

010 0;:;> 10
LJUJJLJU

3 2 U

20 19

:J

18[:

4
0 1 ]5
O2 :J 6
D1

D2

]7

D3

]6

D7

17[: D6
L20-2

15[:

06
05

14[:

D5

16 [:

9 10 11 12 13

nnnnn

04

IO~~IOci'

LE

(!J

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Do

D1

D2

D3

D4

D5

D6

D7

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1967 Integrated Device TeChnology. Inc.

DECEMBER 1987
DSC-4025/-

10-117

IDT54/74FCT533/A FAST CMOS
OCTAL TRANSPARENT LATCH (3-STATE)

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

MILITARY AND COMMERCIAL TEMPERATURE RANGES

-0.5 to +7.0

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

SYMBOL
CIN

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTO

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance

CONDITIONS TYP.
VIN = OV

MAX.

UNIT

10

pF

6

Output Capacitance
8
12
COUT
VOUT= OV
NOTE:
1. This parameter is measured at characterization but not tested.

pF

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vee - 0.2V
Commercial: TA = O°C to + 70°C; Vee = 5.0V±50/0
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL

TEST CONDITIONS(1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

YrH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

YrL

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

VI = Vec

-

-

5

VI = 2.7V

-

-

_5(4)
-5

-

10(4)

IIH

Input HIGH Current
Vcc = Max.

IlL

VI = 0.5V

Input LOW Current

VI = GND
Vo = Vec
Vo = 2.7V

loz

Off State (High Impedance)
Output Current

Vce = Max.

YrK

Clamp Diode Voltage

Vcc = Min., IN = -18mA

los

Short Circuit Current

Vo = 0.5V

Output HIGH Voltage

-

_10(4)

J-IA

-

-10

-0.7

-1.2

V

Vee = Max. (3), Vo = GND

-60

-120

-

mA

Vcc = 3V, VIN = VLC orVHC , 10H = -32J.IA

VHC

Vcc

-

Vcc = Min.
~N = ~Hor~L

Vee = Min.
~N = ~Hor~L

"

10H = -300J-lA

VHC

Vcc

-

10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

4.3

-

-

GND

VLC

10L = 300J-lA
Output LOW Voltage

10

-

Vcc = 3V, ~N = VLC or VHC , 10L = 300J.IA
VOL

J-IA

-

Vo = GND

VOH

5(4)

10L = 32mA MIL.
10L = 48mA COM'L.

GND

VLe

0.3

0.5

0.3

0.5

VH
200
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-118

-

V

V

mV

IDT54/74FCT533/A FAST CMOS
OCTAL TRANSPARENT LATCH (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

Icc

.6.lcc

ICCD

TEST CONDITIONS (1)

PARAMETER

TYP.(2)

MAX.

UNIT

Quiescent Power Supply Current

Vcc = Max.
\'IN ~ VHC ; \'IN :5 VLC
fl = 0

-

0.001

1.5

rnA

Power Supply Current Per TTL
Inputs HIGH

Vcc = Max .
\IN = 3.4V(3)

-

0.5

2.0

rnA

Dynamic Power Supply Current (4)

Vcc = Max.
Outputs Open
OE = GND
LE = Vcc
One Input Toggling
50% Duty Cycle

\'IN ~ VHC
\'IN :5 VLC

-

0.15

0.25

rnA!
MHz

\'IN ~ VHC
VIN :5 VLC (FCT)

-

1.5

4.0

\'IN = 3.4V
\'IN = GND

-

1.8

5.0

\'IN ~ VHC
\'IN :5 VLC (FCT)

-

3.0

6.5(5)

\'IN = 3.4V
\'IN = GND

-

5.0

14.5(5)

Vcc = Max.
Outputs Open
fl = 10MHz,
50% Duty Cycle
DE = GND
LE = Vcc
One Bit Toggling
Ic

MIN.

rnA

Total Power Supply Current (6)
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
OE = GND
LE = Vcc
Eight Bits Toggling

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = iaUIEsCENT + IINPUTS + IDYNAMIC
Ic = Icc + .0.Icc DHNT + ICCD (fcp/2 + fl N I)
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

INPUTS

OUTPUTS

Do - D7

Data Inputs

On

LE

OE

LE

Latch Enable Input (Active HIGH)

H

H

L

L

OE'

Output Enable Input (Active LOW)

L

H

L

H

00 - 07

Complementary 3-State Outputs

X

X

H

Z

H =
L =
X =
Z =

10-119

HIGH Voltage Level
LOW Voltage Level
Don't Care
HIGH Impedance

On

IDT54/74FCT533/A FAST CMOS
OCTAL TRANSPARENT LATCH (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74FCT533
SYMBOL

PARAMETER

CONDITION(1)

COM'L
TYP.(3)

MIN.(2) MAX.

IDT54/74FCT533A
MIL

COM'L
TYP.(3)

MIN~2)

MAX.

MIN.(2)

MIL

UNIT

MAX.

MIN.(2)

MAX.

tpLH
tpHL

Propagation Delay
Dn to On

6.0

1.5

10.0

1.5

12.0

4.0

1.5

5.2

1.5

5.6

ns

tpLH
tpHL

Propagatioll Delay
LE to On

9.0

2.0

13.0

2.0

14.0

7.0

2.0

8.5

2.0

9.8

ns

t pZH
tpZL

Output Enable
Time

8.0

1.5

11.0

1.5

12.5

5.5

1.5

6.5

1.5

7.5

ns

tpHZ
tpLZ

Output Disable
Time

6.0

1.5

7.0

1.5

8.5

4.0

1.5

5.5

1.5

6.5

ns

tsu

Set-upTime
HIGH or LOW
Dn to LE

1.0

2.0

-

2.0

-

1.0

2.0

-

2.0

-

ns

tH

Hold Time
HIGH or LOW
Dn to LE

1.0

1.5

-

1.5

-

1.0

1.5

-

1.5

-

ns

tw

LE Pulse Width
HIGH or LOW

5.0

6.0

-

6.0

-

4.0

5.0

-

6.0

-

ns

CL = 50pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type

X

Package

Commercial
MIL-STD-883, Class B
P
D
' - - - - - - - - - - - - - 1 SO
L
E

' - - - - - - - - - - - - - - - - - - - - - i 533

10-120

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

533A

Octal Transparent Latch (3-State)
Fast Octal Transparent Latch (3-State)

54

-55°C to + 125°C

FEATURES:

DESCRIPTION:

• IDT54/74FCT534 10.0ns max. clock to output;
IDT54/74FCT534A 6.5ns max. clock to output
• Equivalent to FAST ™ output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5~A max.)
• Octal D flip-flop with 3-state output
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class 8

The IDT54/74FCT534 and IDT54/74FCT534A are octal D-type
flip-flops built using IDT's advanced CEMOS TM, a dual metal
CMOS technology. The IDT54/74FCT534 and IDT54/74FCT534A
are high-speed, low-power octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for busoriented applications. A buffered Clock (CP) and Output Enable
(OE) are common to all flip-flops.

PIN CONFIGURATIONS

0lw 8 ....

o

INDEX

0100>10

'C5'E'

I

I'

L-'

00
Do

Dl

Dl

01

I

I

I

I"

L...J

'-'

]4

:J 5

17[

L20-2

]e
D2 ]7
8
D3

O2

I

3 2 U 20 19
1
la[

O2

01

I.

.......

:J

D2
D3

le[
15 [:
14 [:

D7
De

0e
05
D5

9 10 11 12 13

nnnnn

03

10' ~

GND

IDI

En:) 0'

C!l

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
D3

D4

D5

De

D7

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology.

DECEMBER 1987
DSC-4028/-

Inc.

10-121

IDT54/74FCT534/A FAST
CMOS OCTAL D FLIP-FLOP (3-STATE)

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

MILITARY AND COMMERCIAL TEMPERATURE RANGES

-0.5 to +7.0

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

Operating
Temperature

TelAs

Temperature
Under Bias

TSTG

Storage
Temperature

PT

Power Dissipation

.0.5

0.5

W

lOUT

DC Output Current

120

120

mA

-55 to +125

°c

-55 to +125

-65 to +135

°C

-55 to +125

-65 to + 150

°C

+70

CIN

V

TA

o to

SYMBOL

(TA= +25°C, f = 1.0MHz)

PARAM ETER (1)
Input Capacitance

CONDITIONS TYP,
VIN = OV

MAX, UNIT

6

10

pF

COUT
Output Capacitance
8
12
pF
VOUT = OV
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stre'ses greater than those listed under ABSOLUTE MAXIMUM RATIN.GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - O.2V
Commercial: TA = O°C to + 70°C; 'tc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
SYMBOL
"'H
"'L
IIH

TEST CONDITIONS(l)

PARAMETER

loz

"'K
los

VOH

VOL

TYP.(2)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

VI = Vcc

-

-

5

VI = 2.7V

-

-

5(4)

VI = 0.5V

-

-

-5(4)

VI = GND

-

-

-5

Vo = Vcc

-

-

10

Vo = 2.7V

-

-

10(4)

Vo = 0.5V

-

-

-101 4)

Vo = GND

-

-

-10

-

-0.7

-1.2

V
mA

Input HIGH Current
Vcc = Max.

IlL

MIN.

Input LOW Current

Off State (High Impedance)
Output Current

Vcc = Max.

Clamp Diode Voltage

Vcc = Min., IN = -18mA

Short Circuit Current

Vcc = MaxP), Vo = GND

-60

-120

Vcc = 3V, \'IN = VLC or VHC , 10H = -32JJA

VHC

Vcc

-

10H = -300JJA

VHC

\tc

-

10H = -12mA MIL.

2.4

4.3

-

IOH = -15mA COM'L.

Output HIGH Voltage

Output LOW Voltage

Vcc = Min.
\'IN = \'IH or \'IL

2.4

4.3

-

Vcc = 3V, \'IN = VLC or VHC , 10L = 300JJA

-

GND

VLC

10L = 300JJA

-

GND

VLC

10L = 32m A MIL.

-

0.3

0.5

10L = 48mA COM'L.

-

0.3

0.5

Vcc = Min.
\'IN = \'IH or\'lL

VH
Input Hysteresis on Clock Only
200
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-122

-

JJA

JJA

V

V

mV

IDT54/74FCT534/A FAST
CMOS OCTAL D FLIP-FLOP (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
= 0 2V' vHC = Vcc - 0 2V

VLC

SYMBOL

Icc

~Icc

Icco

TEST CONDITIONS

PARAMETER

MAX.

UNIT

Quiescent Power Supply Current

Vcc = Max.
\'IN 2! VHC ; VIN $ VLC
fcp = fl = 0

-

0.001

1.5

mA

Power Supply Current Per TTL
Inputs HIGH

Vcc = Max.
\'IN = 3.4V(3)

-

0.5

2.0

mA

Dynamic Power Supply Current (4)

Vcc = Max.
Outputs Open
OE = GND
One Bit Toggling
50% Duty Cycle

\'IN 2! VHC
\'IN $ VLC

-

0.15

0.25

\'IN 2! VHC
\'IN $ VLC
(FCT)

-

1.5

4.0

\'IN = 3.4V
or
\'IN = GND

-

2.0

6.0

Vcc = Max.
Outputs Open
fcp = 10MHz,
50% Duty Cycle
OE = GND
One Bit Toggling
atf l = 5MHz
50% Duty Cycle
Ic

TYP.(2)

MIN.

(1)

Total Power Supply Current (6)

mAl
MHz

mA

Vcc = Max.
Outputs Open
fcp = 10MHz,
50% Duty Cycle
OE = GND
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle

\'IN 2!
\'IN $
(FCT)
VIN

VHC
VLC

= 3.4V
or

VIN

= GND

-

3.75

7.8(5)

-

6.0

16.8(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + ICCD (fcp/2 + 11 NI )
Icc = Quiescent Current
.6.!cc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N 1 = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

Do - D7

Data Inputs

CP

Clock Pulse Input (Active Rising Edge)

O"E"

3-State Output Enable Input (Active LOW)

00 - 0 7

Complementary 3-State Outputs

OUTPUTS

INTERNAL

OE

INPUTS
CP

01

01

Q1

Hi-Z

H
H

L
H

X
X

Z

Z

NC
NC

LOAD
REGISTER

L
L
H
H

~
~

L
H
L
H

H
L
Z
Z

L
H
L
H

FUNCTION

H =
L =
X =
Z =
~=
NC =

10-123

~
~

HIGH
LOW
Don't Care
High Impedance
LOW-to-HIGH transition
No Change

IDT54/74FCT534/A FAST
CMOS OCTAL D FLlP~FLOP(3~STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES
,

.'

'

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
:

SYMBOl:,

PARAMETER

CONpITION(1 1 : Typ!3)

IDT54/74 FCT534
COM'L.

IDT54/74 FCT534A
MIL.

MIN.(21 MAX. . MIN~21

Typ.(31

MAX.

COM'L.
MIN.(21

MIL.

MAX.

MINPI

UNIT
MAX.

tpLH
t PHL

Propagation Delay
CPto On

6.5

1.5

10.0

1.5

11.0

4.5

1.5

6.5

1.5

7.2

ns

tpZH
tpZL

Output Enable
Time

9.0

1.5

12.5

1.5

14.0

5.5

1.5

6.5

1.5

7.5

ns

tpHZ
tpLZ

Output Disable
Time

6.0

1.5

8.0

1.5

8.0

4.0

1.5

5.5

1.5

6.5

ns

tsu

Set-upTime
HIGH or LOW
Dn to CP

1.0

2.0

-

2.5

-

1.0

2.0

-

2.0

-

ns

tH

Hold Time
HIGH or LOW
Dn to CP

0.5

1.5

-

1.5

-

1.0

1.5

-

1.5

-

ns

tw

CP Pulse Width
HIGH or LOW

4.0

7.0

-

7.0

-

4.0

5.0

-

6.0

-

ns

CL = 50pF
RL = 500a

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type

X
Package

X
Processl
Temperature
Range

Y:oo,

10-124

MIL-STD-883, Class B

E

Plastic DIP
CERDIP
Sma" Outline IC
Leadless Chip Carrier
CERPACK

534
534A

Octal D Flip-Flop (3-State)
Fast Octal D Flip-Flop (3-State)

54

-55°C to + 125°C

P

D
~----------------~ SO
L

1....------------------------------1

Commercial

--._-------------------------------------------

FEATURES:

DESCRIPTION:

• IDT54/74FCT540/41 equivalent to FAST™ speed;

The IOT54/74FCT540/A and IOT54/74FCT541/A are octal
buffer/line drivers built using advanced CEMOS TM, a dual metal
CMOS technology.
These devices are similar in function to the IDT54/74FCT240
and IDT54/74FCT241, respectively, except that the inputs and outputs are on opposite sides of the package. This pinout arrangement makes these devices especially useful as output ports for
microprocessors, allowing ease of layout and greater board
density.

IDT54/74FCT540A/41A 30% faster than FAST ™
• Equivalent to FAST ™ output drive over full temperature and
voltage supply extremes
• IOL = 64mA (commercial), 48mA (military)
• Octal buffer/line driver with 3-state output
• Pinout arrangement for flow-through architecture
• CMOS power levels (5}.lW typo static)
• Substantially lower input current levels than FAST ™ (5}.lA max.)
• Available in CERDlP, Plastic DIP, LCC and SOIC
• TTL input and output level compatible
• CMOS output level compatible
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
DEA

PIN CONFIGURATIONS

DEB
c(

~ o~

INDEX

00

0

m

>0 ~

Do

00

Dl

~1

D2

02

D3

03

D4

04

Ds

OS

~~~~~

D6

Oe

OzO

D7

07

UUIIUU
3

D2 :] 4
D3 :] s
D4 ]e
DS ]7
De :] 8

2 U 20 19
1
18[ 00
17 [: 01
le[ 02
L20-2
lS[ 03
14 [: 0 4

.... 0

~

DIP/SOIC/CERPACK
TOP VIEW

....

00

LCC
TOP VIEW

IDT54/74 FCT540
'O!:A

OEB

Do

00

Dl

01

D2

02

03

03

D4

04

Ds

Os

D6

06

D7

07

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
DEA, DEB
Dxx

DESCRIPTION
3-State Output Enable Input (Active LOW)
Inputs

Oxx

Outputs

TRUTH TABLE
OUTPUT

INPUTS
OEA, DEB
L
L
H =
L =
X =
Z =

IDT54/74FCT541
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc_

10-125

H
HIGH Voltage Level
LOW Voltage Level
Don't Care
High Impedance

D
L

540
H

541
L

H

L

H

X

Z

Z

DECEMBER 1987
OSC-4029/-

([!]

IDT54/74FCT540/A and IDT54/74FCT541/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL

RATING

COMMERCIAL

CAPACITANCE
MILITARY

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

-0.5 to +7.0

-0.5 to +7.0

SYMBOL

UNIT
V

(TA= +25°C, f = 1.0MHz)'

PARAMETER(1)

CIN

Input Capacitance

COUT

Output Capacitance

CONDITIONS TYP.

MAX.

UNIT

VIN = OV

6

10

pF

VOUT = OV

8

12

Typ.(2)

pF
NOTE:
1. This parameter is guaranteed by characterization data and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = O.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vee = 5.0V±5%
Military: TA = -55°C to +125°C; Vee = 5.0V±10%
SYMBOL

TEST CONDITIONS(1)

MAX.

UNIT

\'IH

Input HIGH Level

PARAMETER

Guaranteed LogiC High Level

2.0

-

-

V

\'IL

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

-

5

VI = Vec
IIH

Input HIGH Current
Vee = Max.

IlL

Input LOW Current

MIN.

VI = 2.7V

-

-

5(4)

VI = 0.5V

-

-

-5(4)

VI = GND

-

Vo = 2.7V

-

-

-5

Vo = Vee

10(4)

Vo = 0.5V

-

-

-10(4)

Vo = GND

jJA

10

loz

Off State (High Impedance)
Output Current

Vee = Max.

-

-

-10

\'IK

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

-0.7

-1.2

V

los

Short Circuit Current

Vec = Max!3), Vo = GND

-60

-120

mA

Vee = 3V, VIN = VLe orVHC • 10H = -32jJA

VHC

Vee

-

VOH

Output HIGH Voltage

Vee = Min.
\'IN = \'IH or\'lL

10H = -300jJA

VHe

Vee

10H = -12mA MIL.

2.4

4.3

IOH = -15mA COM'L.

2.4

4.3

-

GND

VLe

GND

VLC

IOL = 48mA MIL.

-

0.3

0.55

IOL = 64mA COM'L.

-

0.3

0.55

Vee = 3V, \'IN = VLe or VHC • 10L = 300jJA
IOL = 300jJA
VOL

Output LOW Voltage

Vee = Min.
\'IN = \'Iii or\'lL

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-126

jJA

V

IDT54/74FCT540/ A and I DT54/7 4FCT541/ A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
TEST CONDITIONS(1)

PARAMETER

SYMBOL

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~VHC; "IN ~ VLC
11 = 0

.D.lcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current (4)

Vcc= Max.
Outputs Open
ClEA = (JEB = GND
One Input Toggling
50% Duty Cycle

ICCD

Ic

MIN.

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

"IN ~ VHC
"IN ~ VLC

-

0.15

0.25

mA/MHz

Vcc = Max.
Outputs Open
11 = 10MHz
50% Duty Cycle
OEA = nEB = GND
One Input Toggling

"IN ~ VHC
"IN ~ VLC
(FCT)

-

1.5

4.0

VIN = 3.4V
VIN = GND

-

1.8

5.0

Vcc = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
OEA = DEB = GND
Eight Inputs Toggling

"IN ~ VHC
YtN ~ VLC
(FCT)

-

3.0

6.5(5)

VIN = 3.4V
VIN = GND

-

5.0

14.5(5)

Total Power Supply Current (6)

mA

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = 10UIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .D.lcc DHNT + ICCD (fcpf2 + fl NI )
Icc = Quiescent Current
.D.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at 11
All currents are in milliamps and all frequencies are in megahertz.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74FCT540/541
SYMBOL

PARAMETER

CONDITIONS(1)

COM'L

TYP.(3) MIN.(2) MAX. MIN.(2)
Propagation Delay
to On IDT54174FCT540

tpLH
tpHL

On

tpLH
tpHL

On

Propagation Delay
to On IDT54174FCT541

IDT54/74FCT540A/541 A

MIL
MAX.

COM'L
MIL
TYP.(3) MIN.(2) MAX. MIN.(2) MAX.

UNIT

5.0

2.0

8.5

2.0

9.5

-

-

-

-

-

ns

5.0

2.0

8.0

2.0

9.0

-

-

-

-

-

ns

CL = 50pF
RL = 500n

tpZH
tpZL

Output Enable Time

7.0

2.0

10.0

2.0

10.5

-

-

-

-

-

ns

tpHZ
tpLZ

Output Disable Time

6.0

2.0

9.5

2.0

12.5

-

-

-

-

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at 'bc = 5.0V. +25°C ambient and maximum loading.

10-127

IDT54/74FCT540/A and IDT54/74FCT541/A
FAST CMOS OCTAL BUFFER/LINE DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temperature
Ra ge

xxxx
Device Type

A
Package

A
Process

Y:Wnk
P
D
L
SO

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC

540
541
540A
541A

Non-Inverting Octal Buffer/Line Driver
Inverting Octal Buffer/Line Driver
Fast Non-inverting Octal Buffer/Line Driver
Fast Inverting Octal Buffer/Line Driver

54
74

-55°C to + 125°C
O°C to + 70°C

~--------------~ E

'------------------i
'-------------------------1

10-128

Commercial
MIL-STD-883, Class B

----

....

-- - - - - - - - - - - - - - - - - - -

FEATURES:
• IDT54174FCT543 equivalent to FAST™speed;
IDT54/74FCT543A is 25% faster than FAST ™

DESCRIPTION:
The IDT54174FCT543 and IDT54174 FCT543A are non-inverting
octal transceivers built using advanced CEMOS T~ a dual metal
CMOS technology. These devices contain two sets of eight D-type
latches with separate input and output controls for each set. For
data flow from A to B, for example, the A-to-B Enable (CEAB) input
must be LOW in order to enter data from Ao -A7 or to take data from
Bo-B7, as indicated in the Truth Table. With CEAB LOW, a LOW
signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B
latches transparent; a subsequent LOW-to-HIGH transition of the
LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB
both LOW, the 3-state B output buffers are active and reflect the
data present at the output of the A latches. Control of data from B to
A is similar, but uses the CEAB, LEAB and OEAB inputs.

• Equivalent to FAST ™output drive over full temperature
and voltage supply extremes
•

10L

= 64mA (commercial), 48mA (military)

• 8-bit octal latched transceiver
• Separate controls for data flow in each direction
• Back-to-back latches for storage
• CMOS power levels (5JjW typo static)
• Substantially lower input current levels than FAST ™(5JjA max.)
• TTL input and output level compatible
• CMOS output level compatible
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

r-------------.,

I
I
I

DETAIL A

Ao--~--~--------r-<

I
I
I
I
I
I

Bo

oJ

DETAILAx7

OEBA

----------------0
0---------------- OEAB

~ ------------~
~------------- LEAS

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

10-129

DECEMBER 1987
DSC-4030/-

IDT54174FCT543 AND IDT54174FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER

MILITARY AND COMMERCIALTEMPERATURE RANGES

PIN CONFIGURATIONS

«CD

1«
CD

oWwO
....J Z

c:t: 10
'[E"8'A

Vcc

O'EBA

'CEB"A

Ao

Bo

A1
A2

B1

CD

0

UUU;IUUU
432U282726
25[

A3

B2
B3

A4

B4

A4

:19

A5

B5

A5

:J

Aa

Ba

As

:111

A7

1« m

~.oW

:1

B

L28-1

10

B7

CEAE3

'CE'AB

GND

'OEA"e"

ct~~§EPo~m

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

LOGIC SYMBOL

LEAB CEAB CEBA LEBA
Ao

Bo
B1

A1
A2

B2
B3

A3

A4

B4

A5
Aa

B5
Ba
B7
OEAB

A7
OEBA

TRUTH TABLE For A-TO-B (Symmetric with B-TO-A)
LATCH
STATUS

INPUTS
CEAB

'[E'A'B

OEAB

A-TO-B

X

X

Storing

X

H

-

Storing

X

-

H

H

-

PIN NAMES
~

Bo-B7
HighZ

HighZ

L

L

L

Transparent

Current A Inputs

L

H

L

Storing

Previous· A Inputs

..
* Before LEAB LOW-to-HIGH TranSition

PIN DESCRIPTIONS

OUTPUT
BUFFERS

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown: B-to-A flow control is the same, except using
CEBA, LEBA and OEBA

10-130

DESCRIPTION
A-to-B Output Enable Input (Active LOW)

OEBA

B-to-A Output Enable Input (Active LOW)

CEAB
CEBA

A-to-B Enable Input (Active LOW)

ITAB

A-to-S Latch Enable Input (Active LOW)

B-to-A Enable Input (Active LOW)

LEBA

B-to-A Latch Enable Input (Active LOW)

Ao-A7

A-to-B Data Inputs or B-to-A 3-State Outputs

Bo-Br

B-to-A Data Inputs or A-to-B 3-State Outputs

IDT54/74FCT543 AND IDT54/74FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TSIAS

Temperature
Under Bias

TSTG

Storage
Temperature

o to

+70

CAPACITANCE

(1)

COMMERCIAL
-0.5 to +7.0

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MILITARY

UNIT

-0.5 to +7.0

SYMBOL

V

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

100

100

mA

(TA';;' +25°C, f = 1.0MHz)
PARAMETER(l)
CONDITIONS TYP.

C'N

Input Capacitance

CliO

I/O Capacitance

MAX. UNIT

V,N = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter Is sampled and not 100% tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT~
INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposureto absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VlC = 0.2V; VHC = Vce - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL

TEST CONDITIONS(l)

PARAMETER

MIN.

TYP.(2)

V
V

-

V, = 2.7V

-

V, = 0.5V
V, = GND

-

V, = Vec

-

-

15

V, = 2.7V

-

-

15(4)

= 0.5V

-

-15(4)

V, = GND

-

Guaranteed Logic High Level

2.0

Input LOW Level

Guaranteed Logic Low Level

-

Vee = Max.

0.8

V, = Vcc

Input HIGH Level

Input HIGH Current
(Except I/O pins)

UNIT

-

"IH
"Il
I'H

MAX.

5
5(4)
-5(4)

~A

I'L

I~ut LOW Current
( xcept I/O pins)

I'H

In?cut HIGH Currents
(I 0 pins only)

I'l

In?cut LOW Currents
(I 0 pins only)

"IK

Clamp Diode Voltage

Vcc = Min., IN = -18mA

-

-0.7

-1.2

V

los

Short Circuit Current

Vec = Max!3), Vo = GND

-60

-120

-

mA

Vcc = Max.

V,

VHC

Vcc

= -300~A
= -12mA MIL.

VHC

Vcc ,

2.4

4.3

10H = -15mA COM'L.

Vcc = 3V, V,N = VLC or VHC ' 10H = -32~
VOH

VOL

10H
Output HIGH Voltage

Output LOW Voltage

Vec = Min.
V,N = "'H or"'L

10H

-5

-15

-

2.4

4.3

-

Vcc = 3V, "'N = VLC or VHC ' 10L = 300~

-

GND

VLC

10L = 300~A

-

GND

VLC

0.3

0.55

0.3

0.55

Vec = Min.

10L = 48mA MIL.

"'N = "'H or"'L

10L = 64mA COM'L.

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25 ° C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-131

~A

V

V

IDT54/74FCT543 AND IDT54/74FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VlC = 0 2V' VHC = Vcc - 02V
SYMBOL

PARAMETER

TEST CONDITIONS (1)

Icc

Quiescent Power Supply Current

Vec = Max.
VIN ~ VHC : VIN :5 VlC
fcp = fl = 0

t.lcc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(4)

\Cc = Max.
Outputs Open
CEAB & 01:AB = Low
CEB'A = High
One Input Toggling
50% Duty Cycle

ICCD

Vee= Max.
Outputs Open
fcp = 10MHz
50% DUtyO'?'X:
CE"AB &
= Low

Ic

Total Power Supply Current(6)

crBALEtjfh
fcp =
= 10MHz
One Bit Toggling
atf l = 5MHz
50% Duty Cycle
Vcc= Max.
Outputs Open
fcp = 10MHz
50% Du~ Cycle
CE'AB & OEAB ;", Low
crBA t i9 h
fcp = LE B = 10MHz
Eight Bits Toggling
atf l = 5MHz
50% Duty Cycle

MIN.

Typ.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

"'N ~ VHC
VIN :5 VlC

-

0.15

0.25

mAl

"'N ~ VHC
"'N :5 VlC
(FCT)

-

1.5

4.0

VIN = 3.4Vor
VIN = GND

-

2.0

5.6
mA

"'N ~ VHC
"'N :5 VlC
(FCT)

-

3.75

7.8(5)

VIN = 3.4Vor
VIN = GND

-

6.0

15.0(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + t.lcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
t.lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-132

MHz

IOT54/74FCT543 AND IDT54/74FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I OT54/74FCT543A

IDT54/74 FCT543
SYMBOL

PARAMETER

CONDITION(1)

TYP.(3)

COM'L.

MIL.

MIN.(2) MAX.

MIN.(2) MAX.

Typ.(3)

COM'L.
MIN!2)

MIL.

MAX.

MIN.(2)

UNIT
MAX.

t pLH
t pHL

Propagation Delay
Transparent Mode
An to 8 n or 8 n to An

5.0

3.0

8.5

2.0

10.0

-

-

-

-

-

ns

tpLH
tpHL

Propagation Delay
LE8A to An,
LEAB to 8 n

8.5

3.0

12.5

3.0

14.0

-

-

-

-

-

ns

t pZH
t pZL

Output Enable Time
OE8A or OEA8
toA n or8 n
CE8A or CEA8
to An or 8 n

7.0

3.0

12.0

3.0

14.0

-

-

-

-

-

ns

tpHZ
t pLZ

Output Disable Time
OE8A or OEA8 to
An or 8 n
CEBA or CEAB to
An or Bn

5.5

2.5

9.0

2.5

13.0

-

-

-

-

-

ns

tsu

Set-up Time,
HIGH or LOW
An or 8 n to
LE8A or LEAB

-

3.0

-

3.0

-

-

-

-

-

-

ns

tH

Hold Time,
HIGH or LOW
An or 8 n to
LEBA or LEAB

-

3.0

-

3.0

-

-

-

-

-

-

ns

CL = 50pF
RL = 5000

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.

10-133

IDT54/74FCT543 AND IDT54/74FCT543A
FAST CMOS OCTAL REGISTERED TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xx

Temperature

xx
Device Type

A
Package

A
Process

I

I Blank

~B

P
D

1.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1

10-134

MIL-STO-883, Class B

SO
E

Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK

543
543A

Octal Registered Transceiver
Fast Octal Registered Transceiver

54
74

-55°C to + 125°C
O°C to + 70°C

'------------i L

1...-_ _ _ _ _ _ _ _ _ _ _ _ _-1

Commercial

FEATURES:

DESCRIPTION:

• IDT54!74FCT573 equivalent to FAST ™speed;
IDT54/74FCT573A 35% faster than FAST ™
• Equivalent to FAST ™output drive over full temperature
and voltage supply extremes
• 10L = 48mA (commercial) and 32mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5~A max.)
• Octal transparent latch with enable
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54!74FCT573 and IDT54!74FCT573A are 8-bit latches
built using advanced CEMOS TM, a dual metal CMOS technology.
These octal latches have 3-state outputs and are intended for busoriented applications. The flip-flops appear transparent to the data
when Latch Enable. (LE) is HIGH. When LE is LOW, the data that
meets the set-up times is latched. Data~pears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the bus output
is in the high impedance state.

PIN CONFIGURATIONS
~

-

Vee

I

Dl
D2
D3

D2 ]4
D3 ] s

O2

03
04

D4
Ds
D6
D7
GND

0

I

I

L..J

00
01

Do

fa

0

CJCJO~o

INDEX

D4

:J

1'1'1

L..J

I

I

I

I

..............

3 2 U 20 19
1

6

01

17[

O2

lS[

03
04

L20-2

Ds ]7
D6 ]8

Os

18[

1m

Os

~~~~~

06
07

o~~CScf

LE

(!)

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Do

Dl

D2

D3

D4

Ds

D6

D7

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Inlegraled DevIce Technology. Inc.

DECEMBER 1987
DSC-4031/-

10-135

IDT54/74FCT573/A FAST CMOS
OCTAL TRANSPARENT LATCH

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TBIAS

Temperature
Under Bias

TSTG

Storage
Temperature

-0.5 to +7.0

o to

. CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT
V

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to + 150

°C

+ 70

SYMBOL

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

C IN

Input Capacitance

COUT

Output Capacitance

MAX, UNIT

CONDITIONS TYP.
VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated In the operational sections of this
specification is not im plied. Exposure to absol ute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; 'tc = 5.0V±5%
Military: TA = -55°C to +125°C; Vcc = 5.0V±10%
MIN.

TYP.(2)

MAX.

~H

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

~L

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

VI = Vcc

-

-

5

IIH

Input HIGH Current

VI = 2.7V

-

-

5(4)

VI = 0.5V

-

-

-5(4)

VI = GND

-

-

-5

Vo = Vcc

-

Vo = 2.7V

-

-

10(4)

Vo = 0.5V

-

-

_10(4)

SYMBOL

TEST CONDITIONS (1)

PARAMETER

Vcc = Max.
IlL

I

Input LOW Current

loz

Off State (High Impedance)
Output Current

~K

Clamp Diode Voltage

los

Short Circuit Current

Vcc = Max.

Output LOW Voltage

jJA

-

-10

Vcc = Min., IN = -18mA

-0.7

-1.2

V

Vec = Max!3), Vo = GND

-60

-120

-

mA

VHe

Vec

-

=

VLC orVHc,l oH = -32jJA

Vee = Min.
"'IN = "'IH or "'IL

IOH = -300jJA

VHC

\tc

-

10H = -12mA MIL.

2.4

4.3

-

10H = -15mA COM'L.

2.4

4.3

-

-

GND

VLC

10L = 300jJA

-

GND

VLC

10L = 32mA MIL.

-

0.3

0.5

10L = 48mA COM'L.

-

0.3

0.5

Vcc = 3V, "'IN = VLC or VHC ' 10L = 300jJA
VOL

10

-

Vcc = 3V, VIN
Output HIGH Voltage

jJA

-

Vo = GND

VOH

UNIT

Vee = Min.
"'IN = "'IH or"'lL

VH
200
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-136

-

V

V

mV

IDT54/74FCT573/A FAST CMOS
OCTAL TRANSPARENT LATCH

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; \1;c = Vcc - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS (1)

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC ; VIN ~ VLC
fcp= fl = 0

.6. Icc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3AV(3)

Icco

Ic

Dynamic Power Supply Current(4)

Total Power Supply Current(6)

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

\'IN ~ VHC
\'IN ~ VLC

-

0.15

0.25

mAl

\'IN ~ VHC
\'IN ~ VLC
(FCT)

-

1.5

4.0

VIN = 3AVor
VIN = GND

-

1.8

5.0

\'IN ~ VHC
\'IN ~ VLC
(FCT)

-

3.0

6.5(5)

VIN = 3AVor
VIN = GND

-

5.0

14.5(5)

Vcc= Max.
Outputs Open
OE = GND
LE = Vec
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE = GND
LE = Vcc
One Bit Toggling

MIN.

MHz

mA
Vcc = Max.
Outputs Open
fcp= 2.5MHz
50% Duty Cycle
OE = GND
LE = Vcc
Eight Bits Toggling

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPLrrS + 10YNAMIC
Ie = Icc + .6.lce DHNT + IceD (fcp/2 + fl NI )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TTL High Input (VIN = 3AV)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

OUTPUTS

INPUTS

Do-D7

Data Inputs

On

LE

DE

On

LE

Latch Enables Input (Active HIGH)

H

H

L

H

BE

Output Enables Input (Active LOW)

L

H

L

L

0 0 -0 7

3-State Latch Outputs

X

X

H

Z

H
L

X
Z

10-137

HIGH Voltage Level
LOW Voltage Level
Don't Care
High Impedance

IDT54/74FCT573/A FAST CMOS
OCTAL TRANSPARENT LATCH

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/74FCT573
SYMBOL

PARAMETER

CONDITION(l)

TYP.(3)

COM'L.
MIN.(2) MAX.

I DT54/74FCT573A
MIL.

COM'L.

MIN~2)

MAX.

TYPP)

MIN.(2)

MIL.

UNIT

MAX.

MIN.(2)

MAX.

tpLH
tpHL

Propagation Delay
Dn to On

5.0

1.5

8.0

1.5

8.5

4.0

1.5

5.2

1.5

5.6

ns

tpLH
tpHL

Propagation Delay
LE to On

9.0

2.0

13.0

2.0

15.0

7.0

2.0

8.5

2.0

9.8

ns

tpZH
tpz L

Output Enable
Time

7.0

1.5

12.0

1.5

13.5

5.5

1.5

6.5

1.5

7.5

ns

t pHZ
tpLZ

Output Disable
Time

6.0

1.5

7.5

1.5

10.0

4.0

1.5

5.5

1.5

6.5

ns

tsu

Set-upTime
HIGH or LOW
Dn to LE

1.0

2.0

-

2.0

-

1.0

2.0

-

2.0

-

ns

tH

Hold Time
HIGH or LOW
Dn to LE

1.0

1.5

-

1.5

-

1.0

1.5

-

1.5

-

ns

tw

LE Pulse Width
HIGH or LOW

5.0

6.0

-

6.0

-

4.0

5.0

-

6.0

-

ns

CL = 50pF
RL = 5000

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXX FCT
Temp. Range

XXXX
Device Type

Commercial
MIL-STD-883, Class B
P
D
I...-.------------l SO
L
E
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _--1 573
573A

10-138

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Octal Transparent Latch
Fast Octal Transparent Latch

FEATURES:

DESCRIPTION:

• IDT54/74FCT574 equivalent to FAST™ speed;
IDT54/74FCT574A 35% faster than FAST ™

The I DT54/74FCT574 and I DT54/74FCT574A are 8-bit registers
built using advanced CEMOS TM, a dual metal CMOS technology.
These registers consist of eight D-type flip-flops with a buffered
common clock and buffered three-state output control. When the
output enable (OE) input is LOW, the eight outputs are enabled.
When the OE input is HIGH, the outputs are in the three-state
conditions.
Input data meeting the set-up and hold time requirements of the
D inputs is transferred to the 0 outputs on the LOW-to-H IGH transition of the clock input.

• Equivalent to FAST ™ output drive over full temperature
and voltage supply extremes
•

10L

= 48mA (commercial) and 32mA (military)

• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST ™ (5~A max.)
• Positive, edge-triggered Master/Slave, D-type flip-flops
• Buffered common clock and buffered common three-state
control
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

PIN CONFIGURATIONS
INDEX

DE

Vcc

Do
D1
D2
D3
D4
Ds
D6
D7
GND

00
01

o-

0

0

~ >8

(')

0

ULJIIUU
3 2 l.J 20 19

O2
03
04
Os
06
07
CP

]4

01

]5

°2
03
04

]6

L20-2

]7

:J 8
9 10 11 12 13

°5

IDJ

nnnnn

Q~~OO
(!)

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM

CP
CLOCK

DE
OUTPUT
ENABLE

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-4032/-

10-139

IDT54/74FCT574/A FAST
CMOS OCTAL D REGISTERS (3-STATE)

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power DIssipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

-0.5 to +7.0

-0.5 to +7.0

SYMBOL
CIN

V

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)
Input Capacitance

CONDITIONS TYP.
V1N = OV

MAX. UNIT
10

6

Output Capacitance
8
12
VOUT= OV
COUT
NOTE:
1. This parameter is measured at characterization but not tested.

pF
pF

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is notimplied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VlC = O.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; 'tc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vec = 5.0V±10%
SYMBOL
"'H
"'l

MIN.

TYP.(2)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic High Level

2.0

-

V

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

-

5

-

-5(4)
-5

TEST CONDITIONS(l)

PARAMETER

VI = Vee
IIH

Input HIGH Current

VI = 2.7V
Vee = Max.

IlL

loz

VI = 0.5V

Input LOW Current

VI = GND

-

-

Vo = Vee

-

-

10

-

10(4)

-

-1014)

Vo = 2.7V

los

VOH

Vec = Max.

-

-10

Clamp Diode Voltage

Vcc = Min., IN = -18mA

-

-0.7

-1.2

V

Short Circuit Current

Vee = !¥lax. (3), Vo = GND

-60

-120

-

mA

Vec = 3V, \'IN = VlC or VHC , 10H= -32jJA

VHC

Vee

-

-

Vo = 0.5V

Output HIGH Voltage

Vec = Min.
\'IN = \'IH or\'lL

10H = -300j.lA

VHC

Vcc

10H = -12mA MIL.

2.4

4.3

10H = -15mA COM'L.

2.4

4.3

-

-

GND

VlC

GND

VLe

0.3

0.5

0.3

0.5

Vec = 3V, \'IN = Vle or VHe , 10L = 300jJA
10l = 300j.lA
VOL

j.lA

Off State (High Impedance)
Output Current

Vo = GND

"'K

5(4)

Output LOW Voltage

Vec = Min.
\'IN = \'IH or\'lL

10l = 32mA MIL.
10L = 48mA COM'L.

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-140

j.lA

V

V

IDT54/74FCT574/A FAST
CMOS OCTAL D REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

= 0.2V: VHC = Vcc

VLC

SYMBOL

- 0.2V

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ::: VHC ; VIN :5 VLC
fcp = fl = 0

.6.lcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc
\'IN

Dynamic Power Supply Current (4)

Vcc = Max.
Outputs Open
OE = GND
One Bit Toggling
50% Duty Cycle

ICCD

Total Power Supply Current (6)

MAX.

UNIT·

-

0.001

1.5

mA

-

0.5

2.0

mA

VIN ::: VHC
\'IN :5 VLC

-

0.15

0.25

mAl
MHz

\'IN::: VHC
\'IN :5 VLC
(FCT)

-

1.5

4.0

-

2.0

6.0

MIN.

(1)

= Max.
= 3.4V(3)

Vcc = Max.
Outputs Open
fcp = 10MHz,
50% Duty Cycle
OE = GND
One Bit Toggling
atf l = 5MHz
50% Duty Cycle
Ic

TYP.(2)

TEST CONDITIONS

PARAMETER

= 3.4V

\'IN

or

= GND

\'IN

mA

Vcc = Max.
Outputs Open
fcp = 10MHz,
50% Duty Cycle
OE = GND
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle

'-"N ::: VHC
\'IN :5 VLC
(FCT)

= 3.4V

'-"N

or
\'IN

= GND

-

3.75

7.8(5)

-

6.0

16.8(5)

NOTES:
1.
2.
3.
4.
5.
6.

For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .6. lcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

DI

The D flip-flop data inputs.

CP

Clock Pulse for the register. Enters data on the
LOW-to-HIGH transition.

01

The register three-state outputs.

ITE

Output Control. An active-LOW three-state control
used to enable the outputs. A HIGH level input
forces the outputs to the high impedance (off)
state.

INPUTS

FUNCTION

H
L
X
Z

INTERNAL

CLOCK

DI

O.

Hi-Z

H
H

L
H

X
X

Z
Z

NC
NC

LOAD
REGISTER

L
L
H
H

L
H
L
H

L
H

H
L
H
L

....r-

-iT"
-iT"
-iT"

= HIGH
= LOW
= Don't Care
= High Impedance
LOW-to-HIGH transition

-iT" =

NC = No Change

10-141

OUTPUTS

OE

Z
Z

Q.

IDT54/74FCT574/A FAST
CMOS OCTAL D REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74 FCT574
SYMBOL

PARAMETER

CON OmON (1)

COM'L
TYPP)

MIN.(2) MAX.

I DT54/74FCT574A
MIL

MINF)

MAX.

TYP.(3)

COM'L.
MIN.(2)

MAX.

MIL.
MIN.(2)

UNIT
MAX.

tpLH
t pHL

Propagation Delay
CPto On

6.6

2.0

10.0

2.0

11.0

4.5

2.0

6.5

2.0

7.2

ns

tpZH
tpZL

Output Enable
Time

9.0

1.5

12.5

1.5

14.0

5.5

1.5

6.5

1.5

7.5

ns

tpHZ
tpLZ

Output Disable
Time

6.0

1.5

8.0

1.5

8.0

4.0

1.5

5.5

1.5

6.5

ns

tsu

Set-upTime
HIGH or LOW
Dn to CP

1.0

2.0

-

2.5

-

1.0

2.0

-

2.0

-

ns

tH

Hold Time
HIGH or LOW
Dn to CP

0.5

2.0

-

2.0

-

0.5

1.5

-

1.5

-

ns

tw

CP Pulse Width
HIGH or LOW

4.0

7.0

-

7.0

-

4.0

5.0

-

6.0

-

ns

CL = 50pF
RL = 5000

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type

X
Package

X

~~:rMk

Commercial
MIL-sm-883, Class B

L-.---------l

L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _-I

10-142

P
D
SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

574
574A

Octal D Register (3-State)
Fast Octal D Register (3-State)

74

O°C to + 70°C

FEATURES:

DESCRIPTION:

• IDT54174FCT640 7.0ns max. data to output;
IDT54/74FCT640A 5.0ns max. data to output
• Equivalent to FAST™output drive over full temperature and
voltage supply extremes

The IDT54174FCT640 and IDT54174FCT640A are 8-bit inverting
buffer transceivers built using advanced CEMOS TM, a dual metal
CMOS technology. These'octal bus transceivers are designed for
asynchronous two-way communication between data buses. The
devices transmit data from the A bus to the B bus or from the B bus
to the A bus, depending u.Q9n the level atthe direction control (T/R)
input. The enable input (OE) can be used to disable the device so
the buses are effectively isolated.

•
•
•
•
•
•
•
•
•

IOl = 64mA commercial and 48mA military
CMOS power levels (5~W typo static)
TTL input and output level compatible
CMOS output level compatible
Substantially lower input current levels than FAST ™(5~A max.)
Inverting buffer transceiver
JEDEC standard pinout for DIP, LCC and SOIC
Product available in Radiation Tolerant and Enhanced versions
Military product compliant to MIL-STD-883, Class B

PIN CONFIGURATIONS

T/I1

Vee

Ao
Al
A2
A3
A4
As
As
A7

C5l:
So
81
82
83
84
8s
~

GND

~

DIP/SOIC/CERPACK
TOP VIEW

INDEX

01__
ICC

-

« «
A2
A3
A4
As
As

]4
]s
]s
]7
]8

L...I

&....I

3

2

0

>

111-1

U

~
L...I

20 19

18[
17 [:

L20-2

IS[
15 [:

14 [:

So
81
82
83
84

LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-4033/-

1987 Integrated Device Technology, tnc.

10-143

IDT54/74FCT640/A FAST CMOS
OCTAL INVERTING BUFFER TRANSCEIVER

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to + 7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TalAs

Temperature
Under Bias

-55 to + 125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

SYMBOL
CIN

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance

CONDITIONS TYP.
"'N = OV

MAX.

6

UNIT

10

pF

VOUT = OV
ClIO
I/O Capacitance
8
12
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vee -0.2V
Commercial: TA = O°C to + 70°C; 'te = 5.0V±5%
Military: TA = -55°C to +125°C; Vee = 5.0V±10%

"'H
"'L
IIH

TEST CONDITIONS (1)

PARAMETER

SYMBOL

MIN.

TYP.(2)

Guaranteed Logic High Level

2.0

-

-

V

Input LOW Level

Guaranteed Logic Low Level

-

0.8

V

I~ut

HIGH Current
( xcept I/O pins)

VI = Vce

-

-

VI = 2.7V

-

-

5(4)

-

-5(4)

-

-5

VI = O.4V

-

( xcept I/O pins)

VI = GND

IIH

Input HIGH Current
(I/O pins only)

VI = Vee

IlL

Input LOW Current
(I/O pins only)

-

VIK

Clamp Diode Voltage

Vcc = Min., IN = -18mA

los

Short Circuit Current

I~ut LOW Current

VI = 2.7V
Vcc = Max.

VOH

Output HIGH Voltage

VI = O.4V

-

15

-

15(4)

-

_15(4)

}JA

}JA

-

-15

-0.7

-1.2

V

Vcc = Max. (3), Vo = GND

-60

-120

mA

Vce = 3V, "'IN = VLC orVHc.l oH = -32JJA

VHC

Vcc

10H = -300}JA

VHC

\tc

10H = -12mA MIL.

2.4

4.3

IOH = -15mA COM'L.

2.4 '

4.3

-

GND

VLC

Vcc = Min.
"'IN = "'IHor "'IL

GND

VLC

10L = 32mA MIL.

-

0.3

0.55

10L = 48mA COM'L.

-

0.3

0.55

10L = 300}JA
Output LOW Voltage

5

-

VI = GND

Vcc = 3V, "'IN = VLC or VHC • 10L = 300JJA
VOL

UNIT

Input HIGH Level

Vee = Max.
IlL

MAX.

Vcc = Min.
\1N = \1H or\1L

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-144

V

V

IDT54/74FCT640/A FAST CMOS
OCTAL INVERTING BUFFER TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

TEST CONDITIONS

PARAMETER

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

MIN.

(1)

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC ; '-'iN :5 VLC
fl = 0

.6. Icc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
DE = GND
TIA = GND or Vcc
One Input Toggling
50% Duty Cycle

'-'iN ~ VHC
'-'iN :5 VLC

-

0.15

0.25

Vcc = Max.
Outputs Open
fl = 10MHz

'-'iN ~ VHC
\/iN :5 VLC
(FCT)

-

1.5

4.0

VIN = 3.4Vor
VIN = GND

-

1.8

5.0

ICCD

mAl

MHz

50~ D~Cycle

TIR = OE = GND
One Bit Toggling
Ic

Total Power Supply Current

mA

(6)

Vcc = Max.
Outputs Open
fl = 2.5MHz
50j'o D®'. Cycle
TIR = DE = GND
Eight Bits Toggling

\/iN ~ VHC
VIN :5 VLC
(FCT)

-

3.0

6.5(5)

VIN = 3.4Vor
VIN = GND

-

5.0

14.5(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25 0 C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the' Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .6. l cc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.6.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
, ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

INPUTS
OE

OPERATION

T/A

DESCRIPTION

OE

Output Enable Input (Active LOW)

TiA

TransmiVReceive Input

L

L

Bus B Data to Bus A

L

H

Bus A Data to Bus B

Ao-A7

Side A Inputs or 3-State Outputs

H

X

Isolation

Bo-B7

Side B Inputs or 3-State Outputs

10-145

IDT54/74FCT640/A FAST CMOS
OCTAL INVERTING BUFFER TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT640
SYMBOL.

PARAMETER

tpLH
tpHL

Propagation Delay
AtoBorBtoA

tpZH
tPZL
t pHZ
tpLZ

Outpulinable Time
for OE and T/R

CON DITION (1)

CL = 50pF
RL = 500n

Outpu!..Qisable llme
for OE and TIR

TYP~3)

COM'L

I DT54/74FCT640A
COM'L.

MIL.

MIN.(2) MAX.

MIN~2)

MAX.

TYPP)

MIL.

MIN.(2)

MAX.

MIN.(2)

6.0

2.0

7.0

2.0

8.0

3.5

1.5

5.0

1.5

5.3

ns

11.0

2.0

13.0

2.0

16.0

4.8

1.5

6.2

1.5

6.5

ns

7.0

2.0

10.0

2.0

12.0

4.5

1.5

5.0

1.5

6.0

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.

ORDERING INFORMATION
IDTXX FCT
Temp. Range

XXXX
Device Type

X
Package

UNIT
MAX.

X

Commercial
MIL-STD-883, Class B

'------------1

'-----------------1

P
D
SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

640

Octal Inverting Buffer Transceiver
(equivalent to FAST™)
Octal Inverting Buffer Transceiver
(faster than FAST™)

640A
- I 54

L-..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

10-146

-55°C to + 125°C

FEATURES:

DESCRIPTION:

• IDT54/74 FCT645 equivalent to FAST ™ speed;
IDT54/74FCT645A 35% faster than FAST ™
• Equivalent to FAST ™ output drive over full temperature
and voltage supply extremes
• 10L = 64mA (commercial) and 48mA (military)
• CMOS power levels (5}JW typo static)
• Sub~tantially lower input current levels than FAST ™ (5}JA max.)
• Nori~inverting buffer transceiver
• TTL input and output level compatible
• CMOS output level compatible
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT645 and IDT54/74FCT645A are 8-bit noninverting buffer transceivers built using advanced CEMOS TM, a
dual metal CMOS technology. These non-inverting buffer transceivers are designed for asynchronous two-way communication
between data buses. The devices transmit data from the A bus to
the B bus or from the B bus to the A bus, depending upon the level
at the direction control (T/R) input. The enable input (OE) can be
used to disable the device so the buses are effectively isolated.

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM

Tm

Vee

Tm

~

Ao
A1
A2
A3
A4
A5
As
A7
GND

(1)

(19) ~

Bo
B1
B2
B3
B4
B5
Bs
B7

Ao

(2)

(18)

A1

(3)

1m

So

(17)

B1
A2

(4)
(16)

DIP/SOIC/CERPACK
TOP VIEW

B2
A3

(5)

(15)

B3

INDEX

A4

ULJIIUU
3

A2
A3
A4
A5
As

]
]

LJ

2

L20-2

7
8
9

(14)

20 19

1

:1 4
:1 5
:1 S

(6)

B4

Bo
17[: B1
16 [: B2
15[ B3
14[ B4
18 [:

As

(7)

(13)

Ae

Bs

(8)

(12)

Be

10 11 12 13

nnnnn

(9)

.t~mafar

(11)

(!l

~

LCC
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology, Inc.

10-147

DECEMBER 1987
DSC-4034/-

IDT54/74FCT645 FAST CMOS
NON·INVERTING BUFFER TRANSCEIVER

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TSIAS

Temperature
Under Bias

TSTG

Storage
Temperature

PT
lOUT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

-0.5 to + 7.0

o to

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

CIN

V

-55 to +125

°C

-55 to +125

-65 to + 135

°C

-55 to + 125

-65 to +150

°C

Power Dissipation

0.5

0.5

W

DC Output Current

120

120

mA

+70

SYMBOL

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)
Input Capacitance

CONDITIONS TYP.
VIN = OV

MAX.

UNIT

10

pF

6

I/O Capacitance
8
12
pF
Vour= OV
CliO
NOTE:
1. This parameter is guaranteed by characterization data and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; 'bc = 5.0V±5%
Military: TA = ·55°C to + 125°C; Vcc = 5.0V±10%
TEST CONDITIONS (1)

MAX.

UNIT

~H

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

~L

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

VI = \bc

-

-

5

VI = 2.7V

-

-

5(4)

VI = 0.5V

-

-5(4)

VI = GND

-

-

-5

VI = \bc

-

-

15

VI = 2.7V

-

-

15(4)

VI = 0.5V

-

-

_15(4)

VI = GND

SYMBOL

IIH

PARAMETER

I~ut HIGH Current
( xcept I/O pins)

Vcc = Max.
IlL

I~ut LOW Current

( xcept I/O pins)

MIN.

TYP.(2)

~A

IIH

Input HIGH Current
(I/O pins only)

IlL

Input LOW Current
(I/O pins only)

-15

~K

Vee = Min., IN = -18mA

-

-

Clamp Diode Voltage

-0.7

-1.2

V

los

Short Circuit Current

Vec = MaxP), Vo = GND

-60

-120

-

mA

Vcc = Max.

Vcc = 3V, '-"N = VLC or VHC • 10H= ·32 ~
VOH

Output HIGH Voltage

Vcc = Min.
'-"N = '-"H or '-"L

VHC

Vcc

-

IOH = -300jJA

VHC

\bc

-

IOH = -12mA MIL.

2.4

4.3

-

IOH = -15mA COM'L.

2.4

4.3

-

-

GND

VLC

-

GND

VLC

0.3

0.55

0.3

0.55

Vee = 3V, '-"N = VLC or VHC • IOL = 300~
10L = 300jJA
VOL

Output LOW Voltage

Vcc = Min.
'-"N = '-"H or'-"L

IOL = 48mA MIL.
IOL = 64mA COM'L.

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-148

~A

V

V

IDT54/74FCT645 FAST CMOS
NON-INVERTING BUFFER TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLV CHARACTERISTICS
VLC

=

0.2V; VHC

SYMBOL

= Vcc

- 0.2V
TEST CONDITIONS

PARAMETER
C~ment

1.5

mA

-

0.5

2.0

mA

"IN e:: VHC
"IN :5 VLC

-

0.15

0.25

mA/MHz

VIN e:: VHC
"IN :5 VLC (FCT)

-

1.5

4.0

"IN = 3.4V
VIN = GND

-

1.8

5.0

"IN e:: VHC
"IN :5 VLC (FCT)

-

3.0

6.5(5)

"IN = 3.4V
"IN = GND

-

5.0

14.5(5)

Power Supply Current Per TIL
Inputs HIGH

Vcc = Max.
"IN = 3.4V(3)

Dynamic Power Supply Current (4)

Vcc = Max.
Outputs Open
OE = GND
T/R = GND or Vcc
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fl = 10MHz,
50% Duty Cycle
T/R = OE = GND
One Bit Toggling

mA
Vee = Max.
Outputs Open
fl = 2.5MHz
50% Duty Cycle
T/R = OE = GND
Eight Bits Toggling

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .t:.lee DHNT + ICCD (fcp/2 + fl NI )
Icc = QUiescent Current
..6.lee = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
OE
T/R
Ao-A7
Bo-B7

UNIT

0.001

.t:.lcc

Total Power Supply Current (6)

MAX.

-

Quiescent Power Supply

Ic

TYP.(2)

Vcc = Max.
"IN e:: VHC ; "IN :5 VLC
fl = 0

Icc

ICCD

MIN.

(1)

TRUTH TABLE

DESCRIPTION
Output Enable Input (Active LOW)
TransmiVReceive Input
Side A Inputs or 3-State Outputs
Side B Inputs or 3-State Outputs

INPUTS

10-149

OE

T/R

L
L
H

L
H
X

OPERATION
Bus B Data to Bus A
Bus A Data to Bus B
Isolation

IDT54/74FCT645 FAST CMOS
NON-INVERTING BUFFER TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74 FCT645A

IDT54/74FCT645
SYMBOL

tpLH
t pHL

PARAMETER

CONDITION(1)

Propagation Delay
AtoBorBtoA

COM'L
TYpJ3)

COM'L

MIL

MIN.(2) MAX.

MIN!2)

MAX.

TYPJ3i

MIN.(2)

MIL

MAX.

MIN.(2)

UNIT

MAX.

6.0

1.5

9.5

1.5

11.0

3.3

1.5

4.6

1.5

4.9

ns

9.0

1.5

11.0

1.5

12.0

4.8

1.5

6.2

1.5

6.5

ns

9.0

1.5

11.0

1.5 '

12.0

4.8

1.5

6.2

1.5

6.5

ns

tpZH
t pZL

Out~

tpZH
tpZL

Outp~

t pHZ
tpLZ

OutJ)ut Disable Time
OE to A or B(4)

6.0

1.5

12.0

1.5

13.0

4.5

1.5

5.0

1.5

6.0

ns

tpHZ
tpLZ

Output Enable Time
T/R to A or B(4)

6.0

1.5

12.0

1.5

13.0

4.5

1.5

5.0

1.5

6.0

ns

Enable Time
OE to A or B

Enable Time
T/R to A or B

CL = 50pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at Vcc = 5.0V. + 25 0 C ambient and maximum loading.
4. This parameter is guaranteed but not tested.

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type

X

pror'

"

B

~Blank

Commercial
MIL-STD-883. Class B

'--------------l
'------------------1

10-150

P
D
SO
L
E

PlastiC DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

645
645A

Non-Inverting Buffer Transceiver .
Fast Non-Inverting Buffer Transceiver

FEATURES:

DESCRIPTION:

• IDT54[74FCT646 and IDT54[74FCT648 equivalent to FAST™
speed;
• IDT54i7J~FCT646A and IDT54/74FCT648A are 30% faster
than FAST
• Equivalent to FAST output drive over full temperature and
voltage supply extremes
• Independent registers for A and B buses
• Multiplexed real-time and stored data
• Choice of true and inverting data paths
• 3-state outputs
• IOL = 64mA (commercial) and 48mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Available in 24-pin, 300 mil CERDIP, plastic DIP, SOIC,
CERPACK and 28-pin LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54[74FCT646/A and IDT54/74FCT648/A consist of a
bus transceiver circuit with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from
the input bus or from the internal registers. Data on the A or B bus
will be clocked into the registers as th~ appropriate clock pin goes
to a high logic level. Enable Control G and direction pins are provided to control the transceiver function. In the transceiver mode,
data present at the high impedance port may be stored in eitherthe
A or the B register, or in both. The select controls can multiplex
stored and real-time (transparent mode) data. The direction control
determines which bus will receive data when the enable control
G isActive LOW. In the isolation mode (EnableControIGHIGH),
A data may be stored in the B register and/or B data may be stored
in the A register.

FUNCTIONAL BLOCK DIAc:iRAM

DIR

-~--i

CBA -----------+----------------~
SBA ----------;-----~
CAB
SAB

--------;-;-~

-,
1 OF 8 CHANNELS

54/74FCT646
ONLY

-l

54/74FCT646
ONLY

TO 7 OTHER CHANNELS

CEMOS is a registered trademark of Integrated Device Technology. Inc.
FAST is a trademark of Fairchild Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
OSC-4035/-

10-151

IDT54/74FCT646/A AND IDT54/74FCT648/A
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
CPAB
SAB

Vee
CPBA·

DIR

INDEX

SBA

Al

G

A2
A3
A4
As
Ae
A7
Ae
GND

Bl

LJUUIIUUU

432U2S2726

B2
B3
B4
Bs
Be
B7
Be

:]s

25[

G

:] 6

24 [

Bl

23 [

B2

22[

NC

21 [
20[

B3
B4

19 [

Bs

:J e
A4
As
A6

L28-1

:J 9
:J 10
:J 11
12 13 14 15 16 17 18

nnnnnnn
....

0)

Cl 0

0)

....

co

c:(c:(ZZCIlCIlCIl
(!l

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

LOGIC SYMBOL
PIN DESCRIPTION
DESCRIPTION

PIN NAMES
CPAB

Al

A2

A3

A4 As

Ae

A7 Ae

SAB
DIR
CPBA
SBA

G

Bl

B2

B3

B4 Bs

B6

B7 Be

Al - As

Data Register A Inputs
Data Register B Outputs

Bl - Be

Data Register B Inputs
Data Register A Outputs

CPAB,CPBA

Clock Pulse Inputs

SAB, SBA

TransmiVReceive Inputs

DIR, G

Output Enable Inputs

FUNCTION TABLE
DATA 1/0(1)

INPUTS
G

DIR

CPAB

CPBA

SAB

SBA

Al - As

H
H

X
X

H or L

H or L

Input

t

X
X

Input

t

X
X

L

L

X

X

X

L
Output

L

L

X

H or L

X

H

L

H

X

X

L

X
Input

L

H

H or L

X

H

X

B, - B8

OPERATION or FUNCTION
FCT646/A

FCT648/A

Isolation
Store A and B Data

Isolation
Store A and B Data

Input

Real Time B Data to
A Bus
Stored B Data to A Bus

Real Time B Data to
A Bus
Stored B Data to A Bus

Output

Real Time A Data to
B Bus
Stored A Data to B Bus

Real Time A Data to
B Bus
Stored AData to B Bus

NOTES:

1. The data outputfunctions may be enabled or disabled by various signals atthe Gand DIR inputs. Data inputfunctions are always enabled; i.e., data atthe
bus pins will be stored on every LOw-to-HIGH transition of the clock inputs.

2. H = HIGH
L = LOW
X = Don't Care
t = LOW-to-HIGH Transition

10-152

IDT54/74FCT646/A AND IDT54/74FCT648/A
FAST CMOS OCTAL TRANSCEIVER/REGISTER

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

VTERM
TA

Operating
Temperature

TSIAS

Temperature
Under Bias

TSTG

Storage
Temperature

-0.5 to +7.0

o to

CAPACITANCE

(1)

COMMERCIAL

Terminal Voltage
with Respect to
GND

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MILITARY
-0.5 to +7.0

UNIT
V

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

+70

SYMBOL

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

CIN

Input CapaCitance

CliO

I/O CapaCitance

CONDITIONS TYP.

MAX.

UNIT

VIN = OV

6

10

pF

VOUT = OV

8

12

pF

NOTE:
1. This parameter is guaranteed by characterization and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
MIN.

TYP.(2)

MAX.

UNIT

"'IH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

V

"'IL

Input LOW Level

Guaranteed Logic Low Level

0.8

V

IIH

Input HIGH Current
(Except I/O pins)

-

-

SYMBOL

TEST CONDITIONS (1)

PARAMETER

"'I = \tc
Vcc = Max.,

"'I

= 2.7V

-

= 0.5V

-

5
5(4)
-5(4)

pA

IlL

Input LOW Current
(Except I/O pins)

"'I
"'I

= GND

-

IIH

Input HIGH Current
(I/O pins only)

"'I

= \tc

IlL

Input LOW Current
(I/O pins only)

-

-

-15

"'IK

Clamp Diode Voltage

Vcc = Min., IN = -18mA

-

-0.7

-1.2

V

los

Short Circuit Current

Vcc = MaxI3), Vo = GND

-60

-120

mA

VHC

Vee

VHC

Vcc

Output High Voltage

Vcc = 3V, "'IN = VLC or VHC • 10H = -32pA
10H = -300pA
Vcc = Min.
10H = -12mA MIL.
"'IN = "'IH or"'lL
10H = -15mA COM'L.

-

-

2.4

4.0

-

2.4

4.0

-

Vcc = 3V, "'IN = VLC or VHC ,IOL = 300pA
10L = 300pA
Vcc = Min.
IOL = 48mA MIL.
VIN = "'IH or"'lL
10L = 64mA COM'L.

-

GND

VLC

-

GND

VLC

-

0.3

0.55

0.3

0.55

\I = 2.7V
\I = 0.5V

Vcc = Max.,

VOH

VOL

Output Low Voltage

'vi

= GND

-

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These parameters are guaranteed but not tested.

10-153

-5
15
15(4)
-15(4)

pA

V

IDT54/74FCT646/A AND IDT54/74FCT648/A
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

TEST CONDITIONS

PARAMETER

Icc

Quiescent Power Supply Current

Vcc = Max.
'-"N ~ VHC ; '-"N ~ VLC
fcp = fl = 0

.t:olcc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max .
VIN = 3.4V(3)

Dynamic Power Supply Current

Vcc = Max.
Outputs Open
G = GND
DIR = GND
One Input Toggling
50% Duty Cycle

ICCD

(4)

Vcc = Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
G= GND
DIR = GND
One Bit Toggling
atf l = 5MHz
50% Duty Cycle
Ic

T'{Pp>

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

-

0.15

0.25

mA/MHz

'-"N ~ VHC
VIN ~ VLC
(FCT)

-

1.5

4.0

'-"N = 3.4V
or
'-"N = GND

-

2.0

6.0

(1)

'-"N ~ VHC
'-"N ~ VLC

MIN.

Total Power Supply Current (6)

mA
Vcc = Max.
Outputs Open
fcp= 10MHz
~O% Duty Cycle
G= GND
DIR = GND
Eight Bits Toggling
atf l = 5MHz
50% Duty Cycle

'-"N ~ VHC
'-"N ~ VLC
(FCT)

-

6.75

12.75(5)

'-"N = 3.4V
or
'-"N = GND

-

9.75

(5)
21.75

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (YIN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + .t:olcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
.t:olcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH =' Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
= Input Frequency
N I = Number of Inputs at '1
All currents are in milliamps and all frequencies are in megahertz.

'1

10-154

I DT54/74FCT646/A AND IDT54/74FCT648/A
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT646A (4)

I DT54/74FCT646
SYMBOL

PARAMETER

CONDITIONS(1

TYpP)

COM'L.

MIL.

MINP) MAX. MINP)

TYP.(3)

MAX.

COM'L.

MIL.

UNIT

MINJ2) MAX. MINJ2) MAX.

t pLH
t pHL

Propagation Delay
Bus to Bus

8.0

2.0

9.0

2.0

11.0

-

2.0

6.3

2.0

7.7

ns

t pZH
t pZL

Output Enable Time
Enable to Bus &
DIR to A or B

9.0

2.0

14.0

2.0

15.0

-

2.0

9.8

2.0

10.5

ns

tpHZ
tpLZ

Output Disable Time
Enable to Bus &
Direction to Bus

9.0

2.0

9.0

2.0

11.0

-

2.0

6.3

2.0

7.7

ns

8.0

2.0

9.0

2.0

10.0

-

2.0

6.3

2.0

7.0

ns

12.0

-

2.0

7.7

2.0

8.4

ns

CL = 50pF
RL = 5000

tpLH
tpHL

Propagation Delay
Clock to Bus

tpLH
tpHL

Propagation Delay
SBA or SAB to A or B

10.0

2.0

11.0

2.0

tsu

Set-up time HIGH
or LOW
Bus to Clock

3.0

4.0

-

4.5

-

-

2.0

-

2.0

-

ns

tH

Hold time HIGH
or LOW
Bus to Clock

1.0

2.0

-

2.0

-

-

1.5

-

1.5

-

ns

tpw

Pulse Width.
HIGH or LOW

4.0

6.0

-

6.0

-

-

5.0

-

5.0

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at \(:;c = 5.0V. + 25°C ambient and maximum loading.
4. These are preliminary numbers only.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I OT54/74FCT648 (4)
SYMBOL

PARAMETER

CONOITIONS(1

TYpP)

COM'L.

I DT54/74FCT648A (4)

MIL.

MIN,(2) MAX. MIN,(2)

MAX.

TYPP)

COM'L.

MIL.

UNIT

MIN.(2) MAX. MIN.(2) MAX.

t pLH
tpHL

Propagation Delay
Bus to Bus

7.0

2.0

8.0

2.0

9.0

-

2.0

5.6

2.0

6.3

ns

t pZH
t pZL

Output Enable Time
Enable to Bus &
DIR to A or B

9.0

2.0

15.0

2.0

18.0

-

2.0

10.5

2.0

12.6

ns

t pHZ
t pLZ

Output Disable Time
Enable to Bus &
Direction to Bus

9.0

2.0

9.0

2.0

11.0

-

2.0

6.3

2.0

7.7

ns

7.0

2.0

9.0

2.0

10.0

-

2.0

6.3

2.0

7.0

ns

12.0

-

2.0

7.7

2.0

8.4

ns

CL = 50pF
RL = 5000

tpLH
tpHL

Propagation Delay
Clock to Bus

t pLH
t pHL

Propagation Delay
SBA or SAB to A or B

10.0

2.0

11.0

2.0

tsu

Set-up time HIGH
or LOW
Bus to Clock

3.0

4.0

-

4.5

-

-

2.0

-

2.0

-

ns

tH

Hold time HIGH
or LOW
Busto Clock

1.0

2.0

-

2.0

-

-

1.5

-

1.5

-

ns

tpw

Pulse Width.
HIGH or LOW

4.0

6.0

-

6.0

-

-

5.0

-

5.0

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Typical values are at \(:;c = 5.0V. +25°C ambient and maximum loading.
4. These are preliminary numbers only.

10-155

IDT54/74FCT646/A AND IDT54/74FCT648/A
FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temperature
Range

xxxx

x

Device Type

Process/
Temperature
Range
1

---~I :''"'

1....-

P
D
~--------------------~SO

L

E
646
646A
648
648A
~

______________________________________~154

174

10-156

Commercial
MIL-SID-883, Class 8
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
Non-inverting Octal Transceiver/Register
Fast Non-inverting Fast Octal Transceiver/
Register
Inverting Octal Transceiver/Register
Fast Inverting Fast Octal Transceiver/Register

(-55°C to + 125°C)
(O°C to + 70°C)

FEATURES:

DESCRIPTION:

• IDT54/74FCT651 and IDT54/74FCT652 are equivalent to
FAST ™ speeds

The IDT54/74FCT6511A and IDT54/74FCT652/A, built in
CEMOS ™ , consist of bus transceiver circuits, D-type flip-flops
and control circuitry arranged for multiplex transmission of data
directly from the data bus or from the internal storage registers.
GAB and GSA are provided to control the transceiver functions.
SAB and SBA control pins are provided to select either real-time or
stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during
the transition between stored and real-time data. A low input level
selects real-time data and a high selects stored data.
Data on the A or B data bus, or both, can be stored in the internal
D flip-flops by low-to-high transitions at the appropriate clock pins
(CPAB or CPBA), regardless of the select or enable control pins.
When SAB and SBA are in the real-time transfer mode, it is also
possible to store data without usin~ internal D-type flip-flops by
simultaneously enabling GAB and GBA.ln this configuration, each
output reinforces its input. Thus, when all other data sources to the
two sets of bus lines are at high impedance, each set of bus lines
will remain at its last state.

• IDT54/74FCT651A and IDT54/74FCT652A 30% faster than
FAST ™ speeds

• Bidirectional bus transceiver and registers
• Independent registers for A and B buses
• Real-time data transfer or stored data transfer
• Choice of true and inverting data transfer
• 3-state outputs
• 10L = 64mA (commercial) and 48mA (military)
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Available in 24-pin 300 mil DIP, SOIC and 28-pin LCC
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

IDT54/74FCT651/A (Inverting)

IDT54/74FCT652/A (Non-inverting)

CPAB

SAB

CPAB

GAB

«

!Xl

«

en

en

en

=>

=>

=>

!Xl

!Xl

!Xl

SAB

GAB

!Xl

en

=>
!Xl

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Fairchird Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-4037/-

1987 Integrated Device Technology. Inc.

10-157

IDT54/74FCT651/A AND IDT54/74FCT652/A FAST
CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
INDEX
CPA8
SA8
GA8
A1
A2
A3
A4
A5
Ae
A7
As
GND

Vcc
CP8A
S8A

A1

:]

GSA

A2

:] e

81
82

A3
NC

:] 7
:] S

83
84
85
8e
87
8s

A4
A5

:19
:] 10

Ae

:]

UUUIIUUU
432U2S2726
25[

5

L28-1

11

.... co 0 ()
co .... >,>-

s

D2

:]

D3

:J 6

D4

:] 7

NC :]

Y7
Y8
Y9
CP

D7

~

INDEX

LOGIC SYMBOLS

10
D

D

Y

8

D5

:] 9

CP----'

06

:] 10

01: _ _ _ _ _ _----l

0 7 :J

11
12 13 14 15 16 17 18

nnnnnnn
cl'0'~~~~~
(!l

DIP/CERPACK/SOIC
TOP VIEW

LCC
TOP VIEW

IDT54/7 4FCT823/IDT54/7 4FCT824 9-BIT REGISTERS

Do

Vee
Yo

Dl

Y1

D2

Y2

D3

D7

Y3
Y4
Ys
Y6
Y7

08

Y8

D4
D5
D6

ern

EN

GNO

CP

~oJWu

INDEX

8o~

oOIOZ::>>'>-

LJUU;;UUU
432U262726

O2 :J 5

2S[

Y2

0 3 :] 6

24 [

Y3

23 [

Y4
NC

0 4 :J 7
NC :] 6

22[

L28-1

D5

:] 9

21 [

D6

:] 10

20 [

YS
Y6

07

:] 11

19 [

Y7

12 13 14 15 16 17 18

D

9

CP

rn---....J
C'['R - - - - - - - '

01: _ _ _ _ _ _----l

nnnnnnn

cl'§OUa..IZ~
ZZUIW

U

DIP/CERPACK/SOIC
TOP VIEW

(!l

,

LCC
TOP VIEW

IDT54/7 4FCT825/IDT54/7 4FCT826 8-BIT REGISTERS
0E 1

Vee

01:2

0E3

Do

Yo

Dl

Y1

O2

Y2

D3

Y3

Y4
Ys

D4

Ds
D6

Y6

D7

Y7

C'['R

rn

GND

CP

INDEX
I I
L.....I

I I
L.....I

4

3

I

I

~

2

I

I

II

U

I

I

L.....,I

1'1
.......

Dl :] s

25 [

Y1

~4[

Y2
Y3

D

8

D2

:] 6

D3

:] 7

23 [

NC

:1 8
:1 9

22[

NC

CP

21 [

EN----'

L28-1

Ds

:] 10

20[

Y4
Y5

D6

:111

19[

Y6

D4

CLA - - - - - - - '

12 13 14 IS 16 17 18

nnnnnnn

OE 1

lZ >:
o/cr.Oua..
zu,w

OE 2 - - - - - < l

da

DIP/CERPACK/SOIC
TOP VIEW

I

'-'

26 27 26

LCC
TOP VIEW

10-165

0E3

IDT54174FCT821 A/B-26A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE REGISTERS
'

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
NAME

DESCRIPTION

I/O

DI

I

The D flip-flop data inputs.

C(J:i

I

For both inverting and non-inverting registers, when
the clear input is LOW and DE" is LOW, the 0 1
outputs are LOW. When the clear input is HIGH, data
can be entered into the register.

CP

I

Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.

0

YI , YI

rn

I

'C5E"

I

The· register three-state outputs.
Clock Enable. When the clock enable is LOW, data
on the DI input is transferred to the 0 1 output on the
LOW-to-HIGH clock transition. When the clock
enable is HIGH, the 0 1 outputs do not change state,
regardless of the data or clock input transitions.
Output Control. When the DE" input is HIGH, the YI
are in the high impedance state. When the
input is LOW, the TRUE register data is present at
the YI outputs.

~uts

FUNCTION TABLES (1)
IDT54/74FCT822/24/26

FUNCTION TABLES (1)
IDT54/74FCT821/23/25
INTERNAL
OUTPUTS

INPUTS

DE

"EN

0,

CP

0,

Y,

H
H

X
X

L
L

L
H

~

H
L

Z
Z

High Z

Clear

H
L

L
L

X
X

X
X

X
X

L
L

Z
L

Clear

Z
NC

Hold

H
L

H
H

H
H

X
X

X
X

NC
NC

Z
NC

Hold

Z
Z
L
H

Load

H
H
L
L

H
H
H
H

L
L
L
L

L
H
L
H

i
i
i
i

H
L
H
L

Z
Z
H

EN

0,

CP

0,

Y,

H
H

X
X

L
L

L
H

~

L
H

Z
Z

HighZ

H
L

L
L

X
X

X
X

X
X

L
L

Z
L

H
L

H
H

H
H

X
X

X
X

NC
NC

H
H
L
L

H
H
H
H

L
L
L
L

L
H
L
H

i
i
i
i

L
H
L
H

Load

L

NOTE:

NOTE:
1. H = HIGH, L = LOW, X = Don't Care, NC
HIGH Transition, Z = High Impedance

FUNCTION

CI:R

CI:R

DE

INTERNAL
OUTPUTS

INPUTS

FUNCTION

= No Change, i = LOW-to-

1. H = HIGH, L = LOW, X = Don't Care, NC
HIGH Transition, Z = High Impedance

10-166

= No Change, i = LOW-to-

IDT54/74FCT821A/B-26A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE REGISTERS

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

100

. 100

mA

-0.5 to +7.0

-0.5 to +7.0

SYMBOL

Input Capacitance

CIN

V

(TA -- +25°C f - 10MHz)

PARAMETER(1)

CONDITIONS TYP.

= OV
VOUT = OV

MAX. UNIT
10 '

6

VIN

pF

8
COUT
Output Capacitance
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; \Cc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
SYMBOL

TEST CONDITIONS(1)

PARAMETER

MIN.

loz

Input lOW Current

Off State (High Impedance)
Output Current

Vcc

= Max.

VI = Vec
VI = 2.7V

-

VI = 0.5V

-

VI = GND

-

Vo = Vcc

-

Vo = 2.7V

-

-

Clamp Diode Voltage

los

Short Circuit Current

VOH

Output HIGH Voltage

Output lOW Voltage

~A

-

-

-0.7

-1.2

V

-75

-120

VHC

Vcc

-

rnA

10H = -300~A

VHC

Vec

-

10H = -15mA MIl.

2.4

4.3

-

Vcc
\'IN

= Min.
= \'IH or\'lL

Vcc

= 3V, \'IN = VLC

Vcc
\'IN

= Min.
= \'IH or\'lL

or VHC ' IOL
IOL
10L
10L

-32~

= -24mA COM'l.
= 300~
= 300~A
= 32mA MIl.
= 48mA COM'l.

2.4

4.3

-

-

GND

VLC

-

GND

VLC

-

0.3

0.5

-

0.3

0.5

VH
200
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-167

10
10(4)

-

10H

VOL

-5

-10

Vce

Vcc

~A

-1d 4 )

= 0.5V
= GND

= Min., IN = -18mA
= MaxP), Vo = GND
= 3V, \'IN = VLe or VHC , 10H =

Vcc

5(4)
-5(4)

-

Vo
Vo

VIK

V

5

Guaranteed logic low level

IlL

V

0.8

-

VIL

Input LOW Level

Vcc = Max.

UNIT

-

-

2.0

Input HIGH Current

MAX.

-

'-IH

Guaranteed Logic High Level

IIH

TYP.(2)

-

Input HIGH Level

-

V

V

mV

IDT54/74FCT821A/B-26A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

PARAMETER

Icc

Quiescent Power Supply Current

Alcc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current(4)

\bc = Max.
Outputs Open
OE = GND
One Bit Toggling
50% Duty Cycle
Vcc= Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
atfl = 5MHz
50% Duty Cycle

Ic

Total Power Supply Current (6)

TYP,!2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

"'N ;:: VHC
VIN ~ VLC

-

0.15

0.25

mAl

"'N ;::: VHC
"'N ~ VLC
(FCn

-

1.5

4.0

VIN = 3.4Vor
VIN = GND

-

2.0

6.0

VIN ;::: VHC
"'N ~ VLC
(FCn

-

3.75

7.8(5)

VIN = 3.4Vor
VIN = GND

-

6.0

16.8(5)

TEST CONDITIONS(1)
Vcc = Max.
VIN ;:::VHC ; "'N ~ VLC
fcp = fl = 0

Vcc= Max.
Outputs Open
fcp = 10MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling
at fl = 2.5MHz
50% Duty Cycle

MIN.

mA

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
Alec = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at 11
All currents are in milliamps and all frequencies are in megahertz.

10-168

MHz

IOT54/74FCT821A/B·26A/B HIGH·PERFORMANCE
CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
PARAMETER
tpLH
tpHL
tpLH
tpHL

TEST(l)
CONDITIONS

DESCRIPTION

PITIragation Delay Clock to YI
( E = LOW)

IOT54/74FCT821 A·26A

IOT54/74FCT821 B·26B

COM'L.
MIL.
MIN.(2) MAX. MIN.(2) MAX.

COM'L.
MIL.
MIN. (2) MAX. MIN.(2) MAX.

UNIT

CL = 50pF
RL = 5000

-

12

-

12

-

7.5

-

8.5

ns

CL = 300pF(3)
RL = 5000

-

20

-

20

-

15

-

16

ns

tsu

Data to CP Set-up Time

4

-

4

-

3

-

3

-

ns

tH

Data CP Hold Time

2

-

2

-

1.5

-

1.5

-

ns

tsu

Enable (ENS) to CP
Set-upTime

4

-

4

-

3.0

-

3.0

-

ns

tsu

Enable (ENS) to CP
Set-up Time

4

-

4

-

3.0

-

3.0

-

ns

0

-

ns

-

9.5

ns

6.0

-

ns

6.0
6.0

-

ns

6.0

-

ns

CL = 50pF
RL = 5000

tH

Enable (E"N) Hold Time

2

-

2

-

0

-

tpHL

Propagation Delay, Clear to Yj

-

20

-

20

-

9.0

tsu

Clear Recovery (CLR S) Time

7

7

-

6.0

7

-

6.0

7

-

6.0

t pWH
tpWL
t PWL
tpZH
t pZL
tpZH
tPZL
t pHZ
tpLZ
t pHZ
tpLZ

Clock Pulse Width

7

-

7

-

6.0

-

CL = 50pF
RL = 5000

-

14

-

15

-

8

-

9

ns

CL = 300pF (3)
RL = 5000

-

23

-

25

-

15

-

16

ns

CL = 5pF(3)
RL = 5000

-

9

-

10

-

6.5

-

7

ns

CL = 50pF
RL = 5000

-

16

-

18

-

7.5

-

8

ns

HIGH

7

I LOW

7

-

I

Clear (CLR = LOW) Pulse Width

Output Enable Time OE
StoYI

Output Disable Time OE"
tOYI

S

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

10-169

ns

IDT54/74FCT821A/B-26A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type

X
Process

I

I Blank

~B

10-170

Commercial
MIL-STD-883, Class B

P
D
E
L
SO

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC

821A
821B
822A
822B
823A
823B
824A
824B
825A
825B
826A
826B

10-Bit Non-Inverting Register
Fast 10-Bit Non-Inverting Register
10-Bit Inverting Register
Fast 10-Bit Inverting Register
9-Bit Non-Inverting Register
Fast 9-Bit Non-Inverting Register
9-Bit Inverting Register
Fast 9-Bit Inverting Register
8-Bit Non-Inverting Register
Fast 8-Bit Non-Inverting Register
8-Bit Inverting Register
Fast 8-Bit Inverting Register

54
74

-55°C to + 125°C
O°C to + 70°C

--"""- - - - - - - - - - - - - - - - - -

FEATURES:

DESCRIPTION:

• Faster than AMO's Am29827-28 series
• Equivalent to AMD's Am29827-28 bipolar buffers in pinout!
function, speeds and output drive over full temperature and
voltage supply extremes
• High-speed butters
- Non-inverting tpD = 3.5ns typo
- Inverting tpD = 4.0ns typo
• IOL = 48mA (commercial), 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (5jJW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD's bipolar
Am29800 Series (5jJA m a x . ) '
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT800 Series is built using advanced
CEMOS ™ , a dual metal CMOS technology.
The IDT54/74FCT827NB and IDT54/74FCT828NB 10-bit bus
drivers provide high-performance bus interface buffering for wide
data/address paths or buses carrying parity. The 10-bit buffers
have NOR-ed output enables for maximum control flexibility. All
buffer data inputs have 200mV minimum input hysteresis to
provide improved noise rejection.
All of the IDT54/74FCT800 high-performance interface family
are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All
inputs have clamp diodes and all outputs are designed for
low-capacitance bus loading in the high impedance state.

FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT827A/B-IDT5474FCT828A/B 10-BIT BUFFERS

PRODUCT SELECTOR GUIDE
10-BIT BUFFoER

I
l

Non-inverting

IDT54/74FCT827f1,B

Inverting

IDT54/74FCT828A/B

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-4010/-

10-171

IDT54/74FCT827A/B-IDT54/74FCT828A/B
HIGH-PERFORMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOGIC SYMBOL

PIN CONFIGURATIONS
IDT54/7 4FCT827 A/B/IDT54/7 4FCT828A/B

- orca

INDEX

o

Vee

0E"1

Do

I

O2
D3
D4

4

Ys
Y6

Ds
D6

0

.y~~

0 Z

0

t

I

~.....,

Yo
Y1
Y2
Y3
Y4

01

I

I.

3

~

2

I

I

I

I

I

I

II.....,.....,

U

I

I

......

28 27 26

O2

:] s

2S

03
04

:] 6

24

:] 7

23

NC

:J

Os

:] 9

0 6 :]
0 7 :J

a

22

l28-1

10

20

Y7

Da

Ya
Y9

nnnnnnn

01: 2

000

D9

YO- 9

D O- 9

Y3
Y4
NC

0E"1

£: Y6

01: 2

Y7

19 [

11

Y2

Ys

21 [

D7

GND

£:
£:
£:
£:

12 13 14 lS 16 17 18
Q)

DIP/CERPACK/SOIC
TOP VIEW

'"

a
a i0

C\I

W

Z

'"
>'>-

Q)

LCC
TOP VIEW

PIN DESCRIPTION
NAME

I/O

OE"I

I

When both are LOW the outputs are
enabled. When either one or both are HIGH
the outputs are High Z.

01

I

10-bit data input.

YI

0

10-bit data output.

DESCRIPTION

FUNCTIONAL TABLES
IDT54/74FCT827A/B (NON-INVERTING) (1)
INPUTS

OUTPUT

"C5"E1

0E 2

DI

YI

L
L

L
L

L
H

L
H

H
X

X
H

X
X

Z
Z

NOTE:
1. H = HIGH, L

= LOW, X = Don't Care, Z =

IDT54/74FCT828A/B (INVERTING)(l)
INPUTS

FUNCTION

OUTPUT

FUNCTION

OE 1

OE 2

DI

YI

Transparent

L
L

L
L

L
H

H
L

Transparent

Three-State

H
X

X
H

X
X

Z
Z

Three-State

NOTE:
1. H = HIGH, L

High Impedance

10-172

= LOW, X = Don't Care, Z = High Impedance

I DT54/7 4FCT827A/B-I DT54/74FCT828A/B
HIGH-PERFORMANCE CMOS BUFFERS

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TBIAS

Temperature
Under Bias

TSTG

Storage
Temperature

MILITARY AND COMMERCIAL TEMPERATURE RANGES

-0.5 to +7.0

o to

CAPACITANCE

(1)

COMMERCIAL

MILITARY
-0.5 to +7.0

UNIT

CIN

V

-55 to +125

°C

-55 to + 125

-65 to + 135

°C

-55 to + 125

-65 to +150

°C

+70

SYMBOL

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

100

100

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)
Input Capacitance

CONDITIONS TYP.

MAX. UNIT

6

VIN = OV

10

pF

COUT
Output Capacitance
VOUT = OV
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; 'bc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V+10%
SYMBOL
"'H
"'L

TEST CONDITIONS(l)

PARAMETER

"'K
los

VOH

V

0.8

V

Input LOW Level

Guaranteed Logic Low Level

-

Input HIGH Current

Input LOW Current

5
5(4)

VI = 2.7V

-

VI = 0.5V

Vo = 2.7V

-

-

10(4)

Vo = 0.5V

-

-

_10<4)

Vo = GND

VI = GND

-

-5(4)

-

-5

-

10

~A

Off State (High Impedance)
Output CUrrent

Vcc = Max.

-

-

-10

Clamp Diode Voltage

Vcc = Min., IN = -18mA

-

-0.7

-1.2

V

Short Circuit Current

Vce = MaxP), Vo = GND

-75

-120

mA

Vcc = 3V, \IN = VLC or VHC ' 10H = -32}JA

VHC

Vcc

-

IOH = -300~A

VHC

Vcc

10H = -15mA MIL.

2.4

4.0

10H = -24mA COM'L.

2.4

4.0

-

-

GND

VLC

IOL = 300~A

-

GND

VLC

IOL = 32mA MIL.

-

0.3

0.5

10L = 48mA COM·L.

-

0.3

0.5

Output HIGH Voltage

Vce = Min.
\IN = \lH or\lL

Vcc = 3V, \IN = VLC or VHC ' 10L = 300}JA
VOL

UNIT

-

2.0

Vo = Vcc
loz

MAX.

-

Guaranteed Logic High Level

Vcc = Max.
IlL

TYP.(2)

Input HIGH Level

VI = Vcc
IIH

MIN.

Output LOW Voltage

Vcc = Min.
\IN = \lH or\lL

VH
200
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-173

-

-

~A

V

V

mV

IDT54/74FCT827A/B-IDT54/74FCT828A/B
HIGH-PERFORMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0 2V' VHC = Vee - 0.2V
SYMBOL

TEST CONDITIONS

PARAMETER

(1)

V~C = Max.

MIN.

TYP.(2)

MAX.

UNIT

Icc

Quiescent Power Supply Current

VIN ~VHC; "'N ::; VLC
fl = 0

-

0.001

1.5

mA

Alcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

Dynamic Power Supply Current (4)

OE'
T/R

\'IN ~ VHC
\'IN ::; VLC

-

0.15

0.25

mAl
MHz

\'IN ~- VHC
\'IN :::; VLC
(FCT)

--

1.5

4.0

VIN = 3.4V
VIN = GND

-

1.8

5.0

ICCD

Vcc= Max.
Outputs Open
= GND
= GND or Vcc
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fl = 10MHz
50% Duty Cycle
OE' = GND
One Bit Toggling

Ic

Total Power Supply Current (6)

mA
Vcc = Max.
Outputs Open
fl = 2.5MHz
50% -Duty Cycle
OE' = GND
Eight Bits Toggling

\'IN ~ VHC
\'IN :::; VLC
(FCT)

-

3.0

6.5(5)

VIN = 3.4V
VIN =; GND

-

5.0

14.5(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3:4V)
DH = Duty Cycle for TTL Inputs High
'
NT = Number of TTL Inputs at DH
..
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-174

IDT54/74FCT827A/B-IDT54174FCT828A/B
HIGH-PERFORMANCE CMOS BUFFERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT827A/28A
PARAMETER

tpLH
tpHL
tpLH
tpHL
t pLH
tPHL
tpLH
tpHL
tpzH
tpZL
t pZH
tpZL
tpHZ
tpHL
tpHZ
tpHL

DESCRIPTION

Propagation Delay from DI to ~
IDT54/74FCT827AlB (Non-inverting)

Propagation Delay from DI to YI
IDTS4/74FCT82BA/B (Inverting)

Output Enable Time OE: to YI

Output Disable Time OE: to YI

TEST (1)
CONDITIONS

COM'L
MIN.(2) MAX.

MIL
MIN.(2) MAX.

IDT54/74FCT827B/28B
COM'L.
MIN.(2)

MIL.
MAX. MIN.(2) MAX.

UNIT

CL = 50pF
RL = 500n

-

8

-

10

-

5.0

-

6.5

ns

CL = 300pF(3)
RL = 500n

-

15

-

17

-

13.0

-

14.0

ns

CL = 50pF
RL = 500n

-

7.5

-

9.S

-

S.5

-

6.S

ns

CL = 300pF(3)
RL = soon

-

14

-

16

-

13.0

-

14.0

ns

CL = SOpF
RL = 500n

-

15

-

17

-

8.0

-

9.0

ns

CL = 300pF(3)
RL = 500n

-

23

-

25

-

1S.0

-

16.0

ns

CL = 5pF(3)
RL = 500n

-

9

-

10

-

6.0

-

7.0

ns

CL = 50pF
RL = 500n

-

17

-

19

-

7.0

-

8.0

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.

10-175

I DTS4/74 FCT827A/B-IDTS4/74FCT828A/B
HIGH-PERFORMANCE CMOS BUFFERS

MILITARY ANDCOMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDTXXFCT

xx

x

Device Type

Commercial
MIL-STD-883, Class B

1------------1

L..--------------------l
1..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1

10-176

P
D
E
L
SO

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC

827A
828A
827B
828B

Non-inverting 10-Bit Buffer
Inverting 10-Bit Buffer
Fast Non-inverting 10-Bit Buffer
Fast Inverting 10-Bit Buffer

54
74

-55°C to + 125°C
O°C to + 70°C

FEATURES:

DESCRIPTION:

• Equivalent to AMD's Am29833-34 and Am29853-54 bipolar
parity bus transceivers in pinouVfunction, speeds and output
drive over full temperature and voltage supply extremes
• High speed bidirectional bus transceiver for processororganized devices
Non-inverting propagation delay = 7.0ns max.
Inverting propagation delay = 7.0ns max.
• Buffered direction three state control
• Error Flag with open-drain output
• 10L = 48mA (commercial) and 32mA (military)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD's bipolar
Am29800 series (5~A max.)
• Available in Plastic DIP, CERDIP, LCC and SOIC
• Product available in Radiation Tolerant and Enhanced
versions

The IDT54/74FCT833/34/53/54 are high-performance bus
transceivers designed for two-way communications. They each
contain an 8-bit data path from the R (port) to the T (port), a 8-bit
data path from the T (port) to the R (port), and a 9-bit parity checker/
generator. Two options are available: the IDT54/74FCT833/34 registeroption and the IDT54/74FCT853/54 latch option. With the register option, the error flag can be clocked and stored in a register
and read at the ERR output. The clear (CLR) input is used to clear
the error flag register. With the latch option, the error can be either
passed, stored, sampled or cleared at the error flag output by using
the EN and CLR controls.
The output enables OE T and OER are used to force the port outputs to the high-impedance state so that the device can drive bus
lines directly. In addition, OERand OET can be used to force a parity error by enabling both lines simultaneously. This transmission
of inverted parity gives the designer more system diagnostic capability. The IDT54/74FCT833 and IDT54/74FCT853 are non-inverting, while the IDT54/74FCT834 and IDT54/74FCT854 present inverting data at the outputs. The devices are specified at 48mA and
32mA output sink current over the commercial and military temperature ranges, respectively.

• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT833
(Device Shown Non-inverting)

IDT54/74 FCT853
(Device Shown Non-inverting)

(1)

(1)

PARITY

PARITY

OE"T

ClK

NOTE:
1. Non-inverting buffer for IDT54174FCT833/53, inverting buffer for
IDT54174FCT834/54, note that the inverting device converts the positive logic "R" bus levels to negative levels on"r bus.

CEMOS is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

DECEMBER 1987
OSC-4012/-

10-177

IOT54/74FCT833A/B. IOT54174FCT834A/B. IDT54174FCT853A/B AND
IOT54/74FCT854A/B FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
IOT54/74FCT853/54

IDT54/74FCT833/34

I DT54/74FCT833/34
OE"R
Ro
R1
R2

Vee
To
T1

C5ER
Ro
R1

T2

R2

R3

T3

R3

R4

T4

R5
R6

T5

R4
R5

T6

R6

R7

~

ern

T7
PARITY
(5"E"T

ern

(5"E"T

GND

ClK

GND

'EN

rnA

IDT54/74 FCT853/54

Vee
To
T1
T2

a:

INDEX"),.

T3
T4
T5
T6
T7
PARITY

R7

R2
R3
R4
NC
R5
R6
R7

0

citC'fo g~~~
WWWiiWUU
:l 5 4 3 2 '1' 2827 2625 [
:l6
]7
]8
]9
] 10
]11

t.5'o

INDEX ~,,""---.a:
R2
R3
R4
NC
Rs
R6
R7

T2
24[ T3
23[ T4
22[ NC
L28-1
21[ T5
20[ T6
19[ T7
1213 14 15 1617 18

0

.

. -.. . .tC'. n/.0........z...,>_o.,..~...,f.'-.-_
..
UL.:Wii UWW
4 3 2 '1' 2827 26 [
:15
25
24[
23[
22[
L28-1
21[
20[
19[
12 13 14 15 1617 18
!"1nnnnnn

:16
]7
]8
]9
] 10
] 11

r1nnn:-!r1r1

T2
T3
T4
NC
T5
T6
T7

ffila:oo~ ~~

a:dazdfoa:
«
Q.

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW

PIN DESCRIPTION
PIN NO.

NAME

DESCRIPTION

I/O

I DT54/74 FCT833/34
1

OER

2-9

RI

10

ERR

I

110

RECEIVE enable input.
8-bit RECEIVE data output.

0

Output from fault registers. Registers detection of odd parity fault on using clock edge (ClK). A registered ERR output remains low until cleared. Open drain output, requires pull up resistor.

11

ClR

0

Clears the fault register output.

16-23

1j

I/O

8-bit TRANSMIT data output.

15

PARITY

I/O

14

OET

I

TRANSMIT enable input.

13

ClK

I

External clock pulse input for fault register flag.

1-bit PARITY output.

I DT54/74 FCT853/54
1

OE R

2-9

RI

10

ERR

I
I/O

0

RECEIVE enable input.
8-bit RECEIVE data output.
Output from fault latches. Latches detection of odd parity fault on active enable EN. A latched ERR
output remains lOW until cleared. Open drain output, requires pull up resistor.

11

ClR

0

Clears the fault latch output.

16-23

1j

I/O

8-bit TRANSMIT data output.

I/O

15

PARITY

14

OE T

I

TRANSMIT enable input.

1-bit PARITY output.

13

EN

I

Enable latch input for fault flag.

ERROR FLAG OUTPUT TRUTH TABLE
IDT54/7 4FCT853/IDT54/7 4FCT854
IDT54/7 4FCT833/IDT54/7 4FCT834
(LATCH OPTION)
(REGISTER OPTION)
INPUTS

INTERNAL
TO DEVICE

OUTPUTS
PRE-STATE

OUTPUT

ERRn -1

ERR

ClR

ClK

POINT"P"

H
H
H

t
t
t

H
l

l

-

-

-

-

H
l
l

Sample
(1's
Capture)

-

H

Clear

H
l

INPUTS

FUNCTION

GET IS HIGH and GER IS lOW.

INTERNAL
TO DEVICE

OUTPUTS
PRE-STATE

OUTPUT

ERRn-1

ERR

EN

ClR

POINT "P"

l
l

l
l

l
H

l
l
l

H
H
H

-

H

l

l

-

H

l
H

l
l
H

Sample
(1's
Capture)

-

H

Clear

l
H

l
H

Store

-

H
H
H
H
(5"E"T IS HIGH and (5"E"R IS lOW.

10-178

FUNCTION

l
H

Pass

I OT54/7 4FCT833A/B, I OT54/74FCT834A/B, I OT54/74FCT853A/B AN 0
IDT54/74FCT854A/B FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLES
IDT54/74FCT833 NON-INVERTING REGISTER OPTION
OUTPUTS

INPUTS

OfT OE R CIA
L
L
L
L

H
H
H
H

-

H
H
H
H

L
L
L
L

H
H
H
H

-

-

L

H
H
H
H

H
H
H
H

H
L
H
H

L
L
L
L

L
L
L
L

-

-

-

-

CLK

RI

(k

OF H'S)

TI INCL PARITY

(k

OF H'S)

RI

1j

PARITY

ERR{l)

FUNCTION

-

H (Odd)
H (Even)
L(Odd)
L (Even)

NA
NA
NA
NA

NA
NA
NA
NA

H
H
L
L

L
H
L
H

NA
NA
NA
NA

t

NA
NA
NA
NA

H (Odd)
H (Even)
L(Odd)
L (Even)

H
H
L
L

NA
NA
NA
NA

NA
NA
NA
NA

H
L
H
L

Receive data from T Port
to R Port with parity test
resulting in flag; transmitting
path is disabled.

-

-

-

NA

NA

H

Clear the state of error flag
register.

-

-

z
z

i

t
t
t
-

-

-

L (Odd)
H (Even)
H (Odd)
H (Even)
L (Odd)
L (Even)

z
Z
Z
Z

H
H
L

NA
NA
NA
NA

H
H
L
L

H

NA
NA
NA
NA

RI

1j

PARITY

ERR{l)

Z
Z

NA
NA.
NA
NA

.

z·
z
Z
Z

l
H
L

Transmit data from R Port
to T Port with parity;
receiving path is disabled.

80th transmitting and receiving paths are disabled.
Parity logic defaults to transmit mode.

Forced-error checking.

IDT54/74FCT834 INVERTING REGISTER OPTION(2)
OUTPUTS

INPUTS

OfT OE R

CLK

RI (k OF L'S)

TI INCL PARITY (k OF H'S)

FUNCTION

i
i

H (Odd)
H (Even)
L(Odd)
L (Even)

NA
NA
NA
NA

NA
NA
NA
NA

L
L
H
H

H
L
H
L

NA
NA
NA
NA

Transmit data from R Port
to T Port with parity; ,
receiving path is disabled.

NA
NA
NA
NA

H (Odd)
H (Even)
L(Odd)
L (Even)

L
L
H
H

NA
NA
NA
NA

NA
NA
NA
NA

H
L
H
L

Receive data from T Port
to R Port with parity test
resulting in flag; transmitting
path is disabled.

L

-

-

-

-

-

-

H
H
H
H

H
L
H
H

-

-

-

z
z

z
z

z

.

Z
Z

L
L
L
L

-

NA
NA
NA
NA

-

L
L
L
L

H
H
H
H

-

H
H
H
H

L
L
L
L

H
H •.
H
H

-

-

H
H
H
H
L
L
L
L
H
L

t

ern

t

t

i

-

-

-

L (Odd)
H (Even)

-

H (Odd)
H (Even)
L (Odd)
L (Even)

NA
NA
NA
NA

= High

= Low

= Low to high transition of clock
·Store the Error State of the Last Receive Cycle

Z
NA

= High Impedance
= Not Applicable
= Don't Care or Irrelevant

H

Clear the, state of error flag
register.

Z
Z

Z
Z
Z

H
L
H

80th transmitting and receiving paths are disabled.
Parity logic defaults to transmit mode.

L
L
H
H

L
H
L
H

NA
NA
NA
NA

Odd = Odd number of logic one's
Even = Even number of logic one's
= 0, 1, 2, 3, 4, 5, 6, 7

NOTES:
1. Output state assumes HIGH output pre-state.
2. Note that for the negative levels on the 8 Port, an "W represents a logic "0· while an "L" represents a logic ''1".

10-179

Forced-error checking.

IDT54/74FCT833A/B, IDT54/74FCT834A/B, IDT54/74FCT853A/B AND
IDT54/74FCT854A/B FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTION TABLES (CONTINUED)
IDT54/74FCT853 NON-INVERTING LATCH OPTION
OUTPUTS

INPUTS

O'ET 6E R erR

-

EN

-

RI

(k

OF H'S)

TI INCL PARITY

(k

OF H'S)

RI

lj

PARITY

ERR(1)

FUNCTION

-

H (Odd)
H (Even)
L(Odd)
L (Even)

NA
NA
NA
NA

NA
NA
NA
NA

H
H
L
L

L
H
L
H

NA
NA
NA
NA

Transmit data from R Port
to T Port with parity;
receiving path is disabled.

L
L
L
L

NA
NA
NA
NA

H (Odd)
H (Even)
L(Odd)
L (Even)

H
H
L
L

NA
NA
NA
NA

NA
NA
NA
NA

H
L
H
L

Receive data from T Port
to R Port with parity test
resulting in flag; transmitting
path is disabled.

H
H
H
H

L
L
L
L

NA
NA
NA
NA

H (Odd)
H (Even)
L (Odd)
H (Even)

H
H
L
L

NA
NA
NA
NA

NA
NA
NA
NA

H
L
H
L

Receive data from T Port
to R Port, pass the error test
resulting to error flag;
transmitting path is disabled.

L

H

H

NA

-

-

NA

NA

-

-

L

H

-

-

-

NA

NA

H
H
H
H

H
H
H
H

H
L

H
H
L
L

-

-

-

L(Odd)
H (Even)

-

-

Z
Z
Z
Z

Z
Z
Z
Z

Z
Z
Z
Z

H
H
L

L
L
L
L

L
L
L
L

H (Odd)
H (Even)
L (Odd)
L (Even)

NA
NA
NA
NA

NA
NA
NA
NA

H
H
L
L

H
L
H
L

NA
NA
NA
NA

RI

lj

PARITY

ERR(1)

L
L
L
L

H
H
H
H

H
H
H
H

-

-

L
L
L
L

L
L
L
L

H
H
H
H

L
L
L
L

H

-

-

-

-

·
·
H

Store the state of error flag
register.
Clear the state of error flag
register.
Both transmitting and receiving paths are disabled.
Parity logic defaults to transmit mode.

Forced-error checking.

IDT54/74FCT854 INVERTING LATCH OPTION (2)
INPUTS

OET OE R

~

EN

RI (k OF H'S)

OUTPUTS
TI INCL PARITY (k OF H'S)

FUNCTION

L
L
L
L

H
H
H
H

-

-

-

H (Odd)
H (Even)
L (Odd)
L (Even)

NA
NA
NA
NA

NA
NA
NA
NA

L
L
H
H

H
L
H
L

NA
NA
NA
NA

Transmit data from R Port
to T Port with parity;
receiving path is disabled.

H
H
H
H

L
L
L
L

L
L
L
L

L
L
L
L

NA
NA
NA
NA

H (Odd)
H (Even)
L (Odd)
L (Even)

L
L
H
H

NA
NA
NA
NA

NA
NA
NA
NA

H
L
H
L

Receive data from T Port
to R Port with parity test
resulting in flag; transmitting
path is disabled.

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

NA
NA
NA
NA

H (Odd)
H (Even)
L (Odd)
L (Even)

L
L
H
H

NA
NA
NA
NA

NA
NA
NA
NA

H
L
H
L

Receive data from T Port
to R Port, pass the error test
resulting to error flag;
transmitting path is disabled.

H

L

H

H

NA

-

-

NA

NA

-

-

L

H

-

-

-

NA

NA

H
H
H
H

H
H
H
H

-

H
L

H
H
L
L

L (Odd)
H (Even)

-

Z
Z
Z
Z

Z
Z
Z
Z

Z
Z
Z
Z

H
L
H

L
L
L
L

L
L
L
L

-

H (Odd)
H (Even)
L(Odd)
L (Even)

NA
NA
NA
NA

NA
NA
NA
NA

L

H
H

L
H
L
H

NA
NA
NA
NA

H
L
Z
NC

=
=
=
=

-

-

-

High
Low
High impedance
No Change

L.

= Not Applicable
NA
·Store the Error State of the Last Receive Cycle
= Don't Care or Irrelevant

·
·
H

10-180

Clear the state of error flag
register.
Both transmitting and receiving paths are disabled.
Parity logic defaults to transmit mode.

Forced-error checking.

Odd = Odd number of logiC one's
Even = Even number of logic one's
= 0, 1, 2, 3, 4, 5, 6, 7

NOTES:
Output state assumes HIGH output pre-state.
2. Note that for negative logic levels on the B Port, an "W represents a logic "0" while an "L" represents a logic "1".

1.

Store the state of error flag
register.

IDT54/74FCT833A/B, IDT54/74FCT834A/B, IDT54/74FCT853A/B AND
IDT54/74FCT854A/B FAST CMOS PARITY BUS TRANSCEIVER

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TSIAS

Temperature
Under Bias

TSTG

Storage
Temperature

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

o to

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to +150

°C

+70

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

SYMBOL
CIN

Input Capacitance

CliO

I/O Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT = OV

8

12

pF

NOTE:
1. This parameter is guaranteed by characterization and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; Vcc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vcc = 5.0V±10%
SYMBOL

TEST CONDITIONS (1)

PARAMETER

MIN.

VIH

Input HIGH Level

Guaranteed LogiC High Level

2.0

V'L

Input LOW Level

Guaranteed Logic Low Level

-

VI = Vcc
IIH

Input HIGH Current (Except I/O pins)

VI = 2.7V
Vcc = Max.

IlL

VI

Input LOW Current (Except I/O pins)

0.5V

Input HIGH Current (I/O pins only)
Vcc = Max.

VI = 2.7V

-

15(4)

VI = 0.5V

-

-

-15(4)

VI = GND

-

-

-15

-0.7

-1.2

V

-60

-120

mA

VHC
VHe

Vcc

-300~A

-15mA MIL.

2.4

-24mA COM'L.

2.4

4.3

-

GND

VLC

GND
0.3

VLC
0.5

0.3

0.5

0.3

0.5

los

Short Circuit Current

Vcc = Max'<3), Vo = GND

Output HIGH Voltage
(Except "ERR)

Vcc = 3V, '-"N = VLC or VHC ' IoH =
10H =
Vec = Min.
10H =
'-"N = '-"H or '-"L
IoH =

VOL

Output LOW Voltage

Vcc = Min.

~A

-5

Vcc = Min., IN = -18mA

-32~

All other
outputs
VIN = '-"H
orVIL

IoL = 300~A
IoL = 32mA MIL.
IoL = 48mA COM'L.

-

ERR

IoL = 48mA

-

=

5(4)
-5(4)

15

Clamp Diode Voltage

3V, '-"N

V

5

-

'-"K

=

V

0.8

-

Vcc

Input LOW Current (I/O pins only)

Vcc

UNIT

-

-

=

IlL

VOH

MAX.

-

-

VI = GND
VI

IIH

=

TYP.(2)

VLC or VHC ' 10L

=

300~

"ce
4.3

200
Input Hysteresis on 1j and RI
VH
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

-

~A

V

V

mV

10-181
- - _ ..

_-_ _--_._------------•..

IDT54/74FCT833A/B, IDT54/74FCT834A/B, IDT54/74FCT853A/B AND
IDT54/74FCT854A/B FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC

= 0.2V; VHC =

SYMBOL

'Icc

~Icc

ICCD

Vcc - 0.2V
PARAMETER

TEST CONDITIONS

Quiescent Power Supply Current

Vcc = Max.
VIN :5 VHC ; \IN :5 VLC
fl = 0

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(4)

Vcc= Max.
Outputs Open
~T = i:Jf: R = GND
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
fcp = 10MHz (CLK or rn)
50% Duty Cycle
OET = GND
O'ER = \bc
fl = 2.5MHz
One Input Toggling

TYP.(21

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

\IN ~ VHC
\IN :5 VLC

-

0.15

0.25

mA/MHz

\IN ~ VHC ;
\IN :5 VLC
(FeT)

-

1.2

3.4

VIN = 3.4V
VIN = GND

-

1.6

5.4

(1)

MIN.

UNIT

Icc
mA

Total Power Supply Current(6)
Vcc = Max.
Outputs Open
fcp = 10MHz (CLK or rn)
50% Duty Cycle
OET = GND
fl = 2.5MHz
i:Jf: R = Vcc
Eight Inputs Toggling

\IN ~ VHC ;
\IN :5 VLC
(FCT)

-

3.8

7.8(5)

VIN = 3.4V
VIN = GND

-

6.0

16.8(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IOUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + ~Icc DHNT + IceD (fcp/2 + fl NI )
Icc = Quiescent Current
~Icc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N 1 = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-182

IDT54/74FCT833A/B, IDT54/74FCT834A/B, IDT54/74FCT853A1B AND
IDT54/74FCT854A/B FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER TEMPERATURE RANGE
IDT54174FCT8XXB (3)

IDT54/74 FCT8XXA (3)
PARAMETERS

CONTJi~ToNS(4)

DESCRIPTION

COM'L
MIN. MAX.

MIL
MIN. MAX.

COM'L
MIN. MAX.

MIL
MIN. MAX.

UNIT

-

10.0

-

14.0

-

7.0

-

10.0

-

14.0

-

7.0

-

17.5

-

21.5

-

14.5

-

17.5

-

21.5

-

-

15.0

-

20.0

-

-

15.0

-

20.0

-

10.5

22.5

-

27.5

-

18.0

t pHL

-

22.5

-

27.5

-

18.0

-

21.5

ns

tpZH

12.0

-

16.0

-

8.5

11.0

ns

tpZL

-

tpHZ

tpLH
tpHL
t pLH

CL
Propagation Delay
R I to TI • TI to R I

CL

t pHL
tpLH
tpHL
t pLH

tpZL
tpZH

CL
Propagation Delay
RI to PARITY

CL

CL
Output Enable Time
OE R• OEr to R I .1j

CL

CL

= 50pF
= 300pF(6)
= 50pF
= 300pF (6)

tpHZ

CL

tpLZ

17.5

ns

10.5

-

14.0

ns

-

14.0

ns

-

21.5

ns

ns

10.0

ns

17.5

ns

12.0

-

16.0

-

8.5

-

11.0

ns

19.5

23.5

-

16.0

-

18.5

ns

19.5

-

23.5

-

16.0

-

18.5

ns

-

10.7

-

14.7

-

7.2

-

9.8

ns

-

10.7

-

14.7

-

7.2

-

9.8

ns

12.0

-

16.0

-

8.5

-

11.0.

ns

-

12.0

-

16.0

-

8.5

-

11.0

ns

12.0

-

16.0

-

8.5

11.0

-

ns

0

-

ns

= 50pF
= 300pF(6)
= 5pF(6)

tpLZ
Output Disable Time
OE R.l5E r to R I' 1j

10.0

14.5

-

= 50pF

tsu

lj. PARITY to ClK Set-up Time

tH

lj. PARITY to ClK Hold Time (1)

0

-

0

-

0

-

tsu

Clear Recovery Time ClR to ClK (2)

-

15.0

-

20.0

-

10.5

-

14.0

ns

7.0

-

9.5

-

5.5

7.0

-

ns

lOW

7.0

-

9.5

-

5.5

7.0

-

ns

lOW

7.0

-

9.5

-

5.5

-

7.0

-

ns

-

12.0

-

16.0

-

8.5

-

11.0

ns

-

12.0

-

16.0

-

8.5

11.0

ns

-

15.0

-

20.0

-

10.5

-

15.0

-

20.0

-

10.5

-

-

15.0

-

20.0

15.0

-

20.0

-

10.5

-

10.5

-

22.5

-

27.5

-

18.0

-

21.5

ns

-

22.5

-

27.5

-

18.0

-

21.5

ns

(1)

HIGH

CL

tw

Clock Pulse Width

tw

Clear Pulse Width

tpHL

Propagation Delay ClK to ERR (1)

CL

tpLH

Propagation Delay ClR to ERR

CL

tpLH
tpHL

(1)

frQpagation-Delay T I• PARITY TO
ERR (PASS Mode Only)
IDT54/74FCT853 and IDT54/74FCT854

t pLH
tpHL
Propagation Delay
tpLH
tpHL

= 50pF

CL

= 50pF
= 50pF
= 50pF

,
CL

= 50pF

C

= 300pF (6)

OER to PARITY
L

NOTES:
1. For IDT54/74FCT853/54. replace ClK with EN.
2. Not applicable to IDT54/74FCT853/54.
3. XX represents 33. 34. 53 and 54.
4. See test circuit and waveforms.
5. Minimum limits are guaranteed but not tested on Propagation Delays.
6. These parameters are guaranteed but not tested.

10-183

14.0

ns

14.0

ns

-

14.0

ns

-

14.0

ns

I DT54/74FCT833A/B, IDT54/74FCT834A/B, IDT54/74FCT853A/B AN D
IDT54/74FCT854A/B FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temp. Range

xxxx
Device Type

A
Package

A
ProcessfTemperature

y:~k
P

________________________________

~I

+ 7D°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B

E

Plastic DIP
Cerdip
Leadless Chip Carrier
Small Outline IC
CERPACK

833A
833B
834A
834B
853A
853B
854A
854B

Non-inverting Parity Bus Transceiver (Register Option)
Fast non-inverting Parity Bus Transceiver (Register Option)
Inverting Parity Bus Transceiver (Register Option)
Fast inverting Parity Bus Transceiver (Register Option)
Non-inverting Parity Bus Transceiver (Latch Option)
Fast non-inverting Parity Bus Transceiver (Latch Option)
Inverting Parity Bus Transceiver (Latch Option)
Fast inverting Parity Bus Transceiver (Latch Option)

D
L
SO

~

Commercial (DOC to

54

I 74

10-184

-55°C to + 125°C
DOC to +7DoC

FEATURES:

DESCRIPTION:

• Equivalent to AMO's Am29841-46 bipolar registers in pinout/
function, speeds and output drive over full temperature and
voltage supply extremes

The IOT54/74FCT800 Series is built using advanced
CEMOS ™ , a dual metal CMOS technology.
The IOT54/74 FCT840 Series bus interface latches are designed
to eliminate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths or buses
carrying parity. The IOT54/74FCT841 and IOT54/74FCT842 are
buffered, 10-bit wide versions of .the popular '373 function. The
IOT54/74FCT843 and IOT54/74FCT844 are 9-bit wide buffered
latches with Preset (PRE) and Clear (CLR)-ideal for parity bus
interfacing in high-performance systems. The IOT54/74FCT845
and IOT54/74FCT846 are 8-bit buffered latches with all the '843/4
controls plus multiple enabl~OEl , OE2, OE3L!Q. allow multiuser
control of the interface, e.g., CS, OMA and RO/WR. They are ideal
for use as an output port requiring high IoL/loH.
All of the IOT54/74FCT800 high-performance interface family
are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All
inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in the high impedance state.

• High-speed parallel latches
- Non-inverting transparent tpD = 5.5ns typo
- Inverting transparent tpD = 6.0ns typo
• Buffered common latch enable, clear and preset input
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (5J.lW typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMO's bipolar
Am29800 Series (5J.lA max.) ,
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STO-883, Class B

FUNCTIONAL BLOCK DIAGRAM

PRODUCT SELECTOR GUIDE
10-BIT

DEVICE
9-BIT

a-BIT

I Non-inverting

54{7 4FCT841 AlB 54{74FCT843A/B 54{74FCT845A/B

/Inverting

54{74FCT842NB 54{74FCT844A/B 54f74FCT846A/B

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-4014/-

1987 Integrated Device Technology, Inc.

10-185

IDT54174FCT841 A/B·46A/B HIGH·PERFORMANCE
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOGIC SYMBOLS

PIN CONFIGURATIONS
IDT54/7 4FCT841/IDT54/7 4FCT842 1O-BIT LATCHES

6d'fo~-»~-;

INDEX
Vee
Yo
Y1

Do
D1

uuu;;uuu

D3

Y4
Ys
Ye
Y7
Y8
Yg
LE

D4
Ds
De
D7
D6
Dg
GND

3 2 U26272e

4

:]6

2S[
24[

D4

:17

Y2
Y3

23[

NC

:ls

Y4
NC

Ds
De
D7

:1 9

D2
D3

Y2
Y3

D2

:15

22[

L28-1

21[
20[

:1 10

19[

:1 11

Ys
Y6
Y7

D

LE
~

12 13 14 15 16 17 16

nnnnnnn

oO'~~ ~~~
C!l

LCC
TOP VIEW

DIP/CERPACK/SOIC
TOP VIEW

IDT54/7 4FCT843/IDT54/7 4FCT844 9-BIT LATCHES
~0fo0 0
OOOz.g~-;

INDEX
Vee
Yo
Y1

Do
D1

uuu;;uuu
4

Y2
Y3

D2
D3

Y4
Ys

D4
Ds

Y6
Y7

De
D7
D8

Y6

3 2 U

28 27 2e

:15

D2
D3

:le

2S[
24[

Y2
Y3

23[

Y4
NC

D4

:17

NC

:16

Ds

:19

21[

D6
D7

:1 10

20[

Ys
Ye

19[

Y7

22[

L28-1

:1 11
12 13 14 15 16 17 16

ITR

J5R"E"

nnnr:nnn

GND

LE

°ISOO
oa
Z

LE

PRE:

ern
~

oa.~~
a:
a.

LCC
TOP VIEW

DIP/CERPACK/SOIC
TOP VIEW

IDT54/7 4FCT845/IDT54/7 4FCT846 8-BIT LATCHES

D4
Ds
D6
D7

INDEX
Vee
C5E"3
Yo
Y1
Y2
Y3
Y4
Ys
Y6
Y7

ITR

PRE"

GND

LE
DIP/CERPACK/SOIC
TOP VIEW

~

0folwo oro
N

~1
~2
Do
D1
D2
D3

'"

oOOz.gO~

D1
D2

:15

ULJU;IUUU
4 3 2 U282726
' 2S[

:le

24[

D3

:17

23[

NC

:1 8

D4
Ds
D6

:1 9

L28-1

:1 10
12 13 14 15 16 17 16

Y2
Y3

22[

NC

21[
20[

Y4
Ys
Y6

19[

:1 11

Y1

LE
PRE
CLR

nnnnnnn

C5E"1

I()a
S 0 0 W[~
a.

0E2

0-

Z

-1

LCC
TOP VIEW

10-186

a:

OE 3

D

IDT54/74FCT841A/B-46A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
NAME

DESCRIPTION

I/O

I DT54/74FCT841/43/45 (Non-inverting)
When C[R" is low, the outputs are LOW ifOE is LOW.
When 'CCR" is HIGH, data can be entered into the
latch.

C[R"

I

DI

I

The latch data inputs.

LE

I

The latch enable input. The latches are transparent
when LE is HIGH. Input data is latched on the HIGHto-LOW transition.

VI

a

The 3-state latch outputs.

OE

I

The output enable control. When OE is LOW, the
outputs are enabled. When OE is HIGH, the outputs
VI are in the high-impedance (off) state.

f5"R"E"

I

Preset line. When f5"R"E" is LOW, the outputs are HIGH
if OE is LOW. Preset overrides CLR.

IDT54/74FCT842/44/46 (Inverting)

ern

I

When C[R" is low, the outputs are LOW ifOE is LOW.
When ern is HIGH, data can be entered into the
latch.

DI

I

The latch inverting data inputs.

LE

I

The latch enable input. The latches are transparent
when LE is HIGH. Input data is latched on the HIGHto-LOW transition.

VI

a

The 3-state latch outputs.

OE

I

The output enable control. When OE is LOW, the
outputs are enabled. When OE is HIGH, the outputs
VI are in the high-impedance (off) state.

PRE

I

Preset line. When PRE is LOW, the outputs are HIGH
if OE is LOW. Preset overrides CLR.

FUNCTION TABLES (1)
IDT54/74FCT841/43/45
INTER- OUTNAL
PUTS

INPUTS

ern

PRE

m:

H

H

H

H

H
H

FUNCTION TABLES (1)
IDT54/7 4FCT842/44/46
INTER- OUTNAL
PUTS

INPUTS

FUNCTION

ern

PRE

m:

FUNCTION

LE

01

01

H

X

X

X

Z

HighZ

H

H

H

H

H

L

L

Z

High Z

H

H

H

H

H

H

H

H

Z

High Z

H

H

H

H

L

H

Z

HighZ

H

H

L

X

NC

Z

Latched (High Z)

H

H

H

L

X

NC

Z

Latched (High Z)

VI

01

01

VI

X

X

X

Z

HighZ

H

H

L

Z

HighZ

LE

H

H

L

H

L

L

L

Transparent

H

H

L

H

H

L

L

Transparent

H

H

L

·H

H

H

H

Transparent

H

H

L

H

L

H

H

Transparent

H

H

L

L

X

NC

NC

Latched

H

H

L

L

X

NC

NC

H

L

L

X

X

H

H

Preset

H

L

L

X

X

H

H

Preset

L

H

L

X

X

L

L

Clear

L

H

L

X

X

L

L

Clear

L

L

L

X

X

H

H

Preset

L

L

L

X

X

H

H

Preset

L

H

H

L

X

L

Z

Latched (High Z)

L

H

H

L

X

L

Z

Latched (High Z)

H

L

H

L

X

H

Z

Latched (High Z)

H

L

H

L

X

H

Z

Latched (High Z)

NOTE:

NOTE:
1. H = HIGH, L = LOW, X = Don't Care, NC
HIGH Transition, Z = High Impedance

Latched

= No Change, t = LOW-to-

1. H = HIGH, L = LOW, X = Don't Care, NC = No Change,
HIGH Transition, Z = High Impedance

10-187

t = LOW-to-

IDT54/74FCT841 A/B·46A/B HIGH·PERFORMANCE
CMOS BUS INTERFACE LATCHES

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

CAPACITANCE

(1)

COMMERCIAL
-0.5 to + 7.0

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MILITARY
-0.5 to +7.0

UNIT

SYMBOL

V

CIN
COUT

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

100

100

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance
Output Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT = OV

8

12

pF

NOTE:
1. This parameter is guaranteed by characterization data and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following conditions apply unless otherwise specified:
VLC = 0.2V; VHC = Vcc • 0.2V
Commercial: TA = O°C to + 70°C; 'bc = 5.0V±5%
Military:TA = ·55°Cto +125°C;Vcc = 5.0V±10%
SYMBOL

TEST CONDITIONS(1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

~H

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

~L

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

-

-

5

= 2.7V

-

\I = 0.5V

-5(4)

\I = GND

-

-

-5

Va = \bc

-

-

10

Vo = 2.7V

-

-

10(4)

Vo = 0.5V

-

-

-1d4 )

-

-10

-0.7

-1.2

V

-75

-120

-

mA

VHC

Vcc

V

\I = \(;c
IIH

Input HIGH Current
\I
VCC = Max.

IlL

Input LOW Current

loz

Off State (High Impedance)
Output Current

Vcc = Max.

~K

Clamp Diode Voltage

Vcc = Min., IN = -18mA

los

Short Circuit Current

Vcc = MaxP),

Vo = GND

'b

= GND

IOH = -300J.lA

VHC

\(;c

IoH = -15mA MIL.

2.4

4.3

10H = -24mA COM'L.

2.4

4.3

-

-

GND

VLC

-

GND

VLC

0.3

0.5

0.3

0.5

Vcc = 3V, \IN = VLC or VHc.l oH = ·32 pA
VOH

Output HIGH Voltage

Vcc = Min.
\IN = \lH or \lL

Vcc = 3V, \IN = VLC or VHC ' 10L = 300pA
IoL = 300J.lA
VOL

Output LOW Voltage

Vcc = Min.
\IN = \lH or \lL

5(4)

IoL = 32mA MIL.
IoL = 48mA COM'L.

VH
200
Input Hysteresis on Clock Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-188

-

pA

pA

V

mV

IDT54/74FCT841A/B-46A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V: VHC = Vcc - 0.2V
SYMBOL

Icc

Quiescent Power Supply Current

Vcc = Max.
VIN ~VHC: '-"N
fl = 0

t:.lcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V (3)

Dynamic Power Supply Current (4)

Vcc= Max.
Outputs Open
BE = GND
LE = \tc
One Input Toggling
50% Duty Cycle

ICCD

s

Total Power Supply Current

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

'-"N ~ VHC
''IN S VLC

-

0.15

0.25

mN
MHz

''IN ~ VHC
''IN S VLC
(FCT)

-

1.5

4.0

VIN = 3.4Vor
VIN = GND

-

1.8

5.0

(1)

VLC

\bc = Max.
Outputs Open
fl = 10MHz
!2Q.% Duty Cycle
OE = GND
LE = Vcc
One Bit Toggling
Ic

TYP.(2)

TEST CONDITIONS

PARAMETER

MIN.

UNIT

mA

(6)

\bc = Max.
Outputs Open
fl = 2.5MHz
5.QYo Duty Cycle
OE = GND
LE = Vcc
Eight Bits Toggling

''IN ~ VHC
''IN S VLC
(FCT)

-

3.0

6.5(5)

V IN = 3.4V
VIN = GND

-

5.0

14.5(5)

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + t:.lcc DHNT + ICCD (fcp/2 + fl NI )
Icc = Quiescent Current
t:.lcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.

10-189

IDT54/74FCT841 A/B-46A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
I DT54/7 4FCT841 A-46A
PARAMETER

TEST (1)
CONDITIONS

DESCRIPTION

COM'L
MIN.

tpLH
(IDT54!74FCT841. 43, 4S)
t pHL

CL
RL

Data (DI ) to Output (VI )
(LE = HIGH)

= 300pF(3)
= SOOO
C L = 50pF
RL = SOOO

CL
RL

tpLH
tpHL
tsu

Data to LE Set-up Time

tH

Data to LE Hold Time

tpLH
(IDTS4!74FCT842, 44, 46)
t pHL
t pLH
tpHL

Data to LE Set-up Time

tH

Data to LE Hold Time

tpLH
tpHL

CL
RL

Data (DI ) to Output (VI )
(LE = HIGH)

tsu

= 300pF(3)
= SOOO
C L = 50pF
RL = SOOO
C L = SOpF
RL = SOOO
C L = 300pF(3)
RL = SOOO

Latch Enable (LE) to VI

tpLH

Propagation Delay, Preset to VI

tsu

Preset Recovery (t'RE

tpHL

Propagation Delay, Clear to 'r'j

tsu

Clear Recovery (CUi

J) Time

LE Pulse Width

HIGH

t pwL

Preset Pulse Width

LOW

tpWL

Clear Pulse Width

LOW

tpHZ
tpLZ
tpHZ
tpLZ

Output Enable Time DE
to VI

L

Output Disable Time "Ol:
to VI

J

CL
RL

= SOpF
= SOOO

J) Time

tpwH

tpZH
t pZL

= SOpF
= 5000

CL
RL

tpLH
t pHL

t pZH
tpzL

= 50pF
= 5000

-

9.S

CL
RL
CL
RL
CL
RL
CL
RL

= SOpF
= 5000
= 50pF
= SOOO
= 300pF (3)
= SOOO
= 5pF (3)
= 5000
= 50pF
= SOOO

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter guaranteed but not tested.

10.:.190

MIN.

COM'L

MAX.

-

11

MIN.

MAX.

-

6.S

MIL
MIN.

UNIT

MAX.

-

7.S

ns

-

13

-

1S

-

13

-

1S

ns

2.5

-

2.5

-

2.5

-

2.5

ns

2.S

-

3

-

2.S

-

2.5

-

-

10

-

12

-

8.0

-

9.0

ns

-

13

-

1S

-

13

-

15

ns

-

2.5

2.5

-

ns

2.S

-

2.S

3

-

2.5

-

ns

-

12

-

16

-

8.0

-

10.5

ns

-

16

-

20

-

1S.5

-

18

ns

-

12

-

14

-

8.0

-

10

ns

10

-

13

ns

6

2.5
2.5

14
13
14

-

17
15
17

ns

11

ns

10

-

10

ns

4

-

4

-

ns

4

4
4

-

ns

4

-

10

9

8

-

9

-

-

14

-

1S

-

8

-

8.5

ns

-

23

-

2S

-

14

-

1S

ns

-

9

-

10

-

6

-

6.S

ns

-

12

-

12

-

7.0

-

7.5

ns

6
CL
RL

MAX.

IDT54/74FCT841 B-46B

MIL

8

ns

IDT54/74FCT841A/B-46A/B HIGH-PERFORMANCE
CMOS BUS INTERFACE LATCHES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXX)(

Device Type

Commercial
MIL-STD-883, Class B

L..-----------------l

10-191

P
D
E
L
SO

Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC

841A
842A
843A
844A
845A
846A
841B
842B
843B
844B
845B
8468

10-Bit Non-inverting Latch
10-Bit Inverting Latch
9-Bit Non-inverting Latch
9-Bit Inverting Latch
8-Bit Non-inverting Latch
8-Bit Inverting Latch
Fast 10-Bit Non-inverting Latch
Fast 10-Bit Inverting Latch
Fast 9-Bit Non-inverting Latch
Fast 9-Bit Inverting Latch
Fast 8-Bit Non-inverting Latch
Fast 8-Bit Inverting Latch

FEATURES:

DESCRIPTION:

• Equivalent to AMD's Am29861-64 bipolar registers in pinout!
function, speeds and output drive over full temperature and
voltage supply extremes
• High-speed symmetrical bidirectional transceivers
- Non-inverting tpD = 5.5ns typo
- Inverting tpD = 6.0ns typo
•
10L = 48mA (commercial), and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (5~W typo static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than AMD's bipolar
Am29800 Series (5~A max.)
• Product available in Radiation Tolerant and Enhanced versions
• Military product compliant to MIL-STD-883, Class B

The IDT54/74FCT800 Series is built using advanced
CEMOS ™ , a dual metal CMOS technology.
The IDT54/74FCT860 Series bus transceivers provide highperformance bus interface buffering for wide data/address paths
or buses carrying parity. The IDT54/74FCT863/64 9-bit transceivers have NOR-ed output enables for maximum control flexibility.
All of the IDT54/74FCT800 high-performance interface family
are designed for high-capacitance load drive capability while providing low-capacitance bus loading at both inputs and outputs. All
inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in the high impedance state.

FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT861/IDT54/74FCT862 10-BIT TRANSCEIVERS

PRODUCT SELECTOR GUIDE
DEVICE
10-BIT

I Non-inverting
I Inverting

9-BIT

IDT54/74FCT861

IDT54/74FCT863

IDT54/74FCT862

IDT54/74FCT864

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-4022/-

10-192

I DT54/74 FCT861 A/B-64A/B HIGH-PERFOR MANCE
CMOS BUS TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM
IDT54/7 4FCT863/IDT54/7 4FCT864 9-BIT TRANSCEIVERS

Ro

R6

PIN CONFIGURATIONS
IDT54/7 4FCT861/IDT54/7 4FCT862 1O-BIT TRANSCEIVERS

Ro

Vee
To

Rl
R2
R3
R4

Tl
T2
T3
T4

R5
Re
R7
Rs
R9
GND

0E"R"1

orn2

Rs

GET 1

0ET2

LOGIC SYMBOLS
IDT54/74FCT861

Fa
0
rErZo§E::v..-?.=

INDEX

"O"ER"

Te

UUUI;UUU

4 3 2 LJ 2S 27 26
1
25
24

£: T2
£: T3

23 [

£:
21 £:
20 £:
19 £:
22

L28-1

Ts
Te
T7
Ts
T9

nnnnnnn

"O"Ei

CO"'O()~~~
C:C:

T4
NC

T

Ts
Te
T7

12 13 14 15 16 17 IS

zzw

CJ
DIP/CERPACKJSOIC
TOP VIEW

0

LCC
TOP VIEW

IDT54/7 4FCT863

IDT54/7 4FCT863/IDT54/7 4FCT864 9-BIT TRANSCEIVERS
"O"ER"1
Ro

Vee
To

Rl
R2
R3
R4

Tl
T2
T3
T4

Rs
R6
R7
Rs

Ts
T6
T7
Ts

0ER2
GND

0Ei2
DEi 1
DIP/CERPACK/SOIC
TOP VIEW

IrE

rErZ~§E::v..-?.=

INDEX

0

UUU;IUUU

R2 :15
R3 :1 6
R4 ]7

4 3 2LJ2S2726
1
25
24
23

NC :1 S

22

L28-1

Rs :]9
Re :1 10
R7 :J 11

21
20
19
12 13 14 15 16 17 IS

nnnnnnn

a:~~§Eg~~
o

Cl
0 0
LCC
TOP VIEW

10-193

£:
£:
£:
£:
£:
£:
£:

T2
T3
T4
NC
Ts
Te
T7

T

IDT54/74FCT861A/B-64A/B HIGH-PERFORMANCE
CMOS BUS TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION
NAME

DESCRIPTION

I/O

IDT54/74FCT861/62
QEl1

I

When LOW in conjunction with OET, HIGH activates
the RECEIVE mode.

OET

I

When LOW in conjunction with QEl1, HIGH activates
the! TRANSMIT mode.

R,

I/O

10-bit RECEIVE inpuVoutput.

1j

I/O

10-bit TRANSMIT inpuVoutput.

IDT54/74 FCT863/64

0El1,

I

When LOW in conjunction with 0ETj , HIGH
activates the RECEIVE mode.

OET,

I

When LOW in conjunction with ~, , HIGH
activates the TRANSMIT mode.

R,

I/O

9-bit RECEIVE inpuVoutput.

1j

I/O

9-bit TRANSMIT inpuVoutput.

FUNCTION TABLES(1)
IDT54/74FCT861/63 (Non-inverting)
INPUTS

"t5ET

~

L
L

OUTPUTS

INPUTS

FUNCTION
~

R,

T,

H

L

N/A

N/A

L

Transmitting

L

H

H

N/A

N/A

H

Transmitting

L

H

L

N/A

L

H

L

N/A

H

H

X

NOTE:
1. H = HIGH, L = LOW, Z
Applicable

R,

FUNCTION TABLES (1)
IDT54/74FCT862/64 (Inverting)

'~

T,

OUTPUTS

T,

R,

T,

H

L

N/A

N/A

H

Transmitting

H

H

N/A

N/A

L

Transmitting

L

N/A

Receiving

H

L

N/A

L

H

N/A

H

H

N/A

Receiving

H

L

N/A

H

L

N/A

X

Z

Z

High Z

H

H

X

X

Z

Z

= High Impedance, X = Don't Care, N/A =

Not

FUNCTION

R,

'OER

Receiving
Receiving
HighZ

NOTE:
1. H = HIGH, L = LOW, Z = High Impedance, X = Don'tCare,N/A = Not
Applicable

10-194

IDT54/74FCT861A/B-64A/B HIGH-PERFORMANCE
CMOS BUS TRANSCEIVERS

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

TBIAS

Temperature
Under Bias

TSTG

Storage
Temperature

PT
louT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

o to

-55 to +125

°C

-55 to +125

-65 to +135

°C

-55 to +125

-65 to + 150

°C

Power Dissipation

0.5

0.5

W

DC Output Current

100

100

mA

+70

SYMBOL

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CIN

Input Capacitance

CliO

I/O Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is guaranteed by characterization data and not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
VLC = 0.2V; VHC = Vcc - 0.2V
Commercial: TA = O°C to + 70°C; 'tc = 5.0V±5%
Military: TA = -55°C to + 125°C; Vee = 5.0V±10%
SYMBOL

TEST CONDITIONS (1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

-

-

V

0.8

V

-

5

"IH

Input HIGH Level

Guaranteed Logic High Level

2.0

"IL

Input LOW Level

Guaranteed Logic Low Level

IIH

'vi
'vi
'vi
'vi
'vi
'vi
'vi

I~ut HIGH Current

(

cept I/O pins)

Vcc = Max.,
IlL

Input LOW Current
(Except I/O pins)

= GND

-

= Vcc

-

= 2.7V

-

= Vee
= 2.7V
= 0.5V

5(4)
'-

-5(4)

-

-5
15

-15

~A

IlL

Input LOW Current
(I/O pins only)

-

-

"IK

Clamp Diode Voltage

Vee = Min., IN = -18mA

-

-0.7

-1.2

V

los

Short Circuit Current

Vee = Max!3), Vo = GND

-75

-120

-

mA

IIH

Input HIGH Current
(I/O pins only)
Vee = Max.,

"I

= 0.5V
= GND

VHC

Vee

-

10H = -300~A

VHC

Vee

-

10H = -15mA MIL.

2.4

4.3

-

10H = -24mA COM'L.

2.4

4.3

-

-

GND

VLC

Vce = 3V, 'vIN = VLe orVHc.l oH = -32~
VOH

Output HIGH Voltage

Vce = Min.
'vIN = 'vIH or'vlL

Vce = 3V, 'vIN = VLe or VHC • 10L = 300~

-

GND

VLe

IoL = 32m A MIL.

-

0.3

0.5

IoL = 48mA COM'L.

-

0.3

0.5

IoL =
VOL

Output LOW Voltage

Vce = Min.
'vIN = 'vIH or'vlL

300~A

VH
200
Input Hysteresis on TI and R I Only
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

10-195

15(4)
-15(4)

-

~A

V

V

mV

IDT54/74FCT861A/B-64A/B HIGH-PERFORMANCE
CMOS BUS TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

PARAMETER

Icc

Quiescent Power Supply Current

L\lcc

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
V,N = 3.4V(3)

Dynamic Power Supply Current (4)

Vcc= Max.
Outputs Open
OE = GND
TiFt = GND or \bc
One Input Toggling
50% Duty Cycle

Icco

Vcc = Max.
Outputs Open
f, = 10MHz
50% Duty Cycle
OE = GND
One Bit Toggling
Ic

TYP.(2)

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

'-"N ;::: VHC
"IN :::; VLC

-

0.15

0.25

mAl

"IN ;::: VHC
"IN :::; VLC
(FCT)

-

1.5

4.0

V,N = 3.4Vor
V,N = GND

-

1.8

5.0

"IN ;::: VHC
"IN :::; VLC
(FCT)

-

3.0

6.5(5)

V,N = 3.4V
V,N = GND

-

5.0

14.5(5)

TEST CONDITIONS(1)
Vcc = Max.
V,N ;:::VHC ; '-"N :::; VLC
f, = 0

MIN.

Total Power Supply Current(6)

UNIT

MHz

mA
Vcc = Max.
Outputs Open
f, = 2.5MHz
50% Duty Cycle
OE = GND
Eight Bits Toggling

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (V,N = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + I'NPUTS + IOYNAMIC
Ic = Icc + L\lcc DHNT + Icco(fcp/2 + f, N, )
Icc = Quiescent Current
L\lcc = Power Supply Current for a TIL High Input ("IN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f, = Input Frequency
N I = Number of Inputs at f,
A" currents are in milliamps and a" frequencies are in megahertz.

10-196

IOT54/74FCT861A/B-64A/B HIGH-PERFORMANCE
CMOS BUS TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IOT54/74FCT861 A-64A
PARAMETER

tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpLH
tpHL
tpZH
tpZL
tpZH
tpZL
t pHZ
tpLZ
tpHZ
t pLZ

TEST (1)
CONDITIONS

DESCRIPTION

MIL.
COM'L.
MIN!2) MAX. MIN.(2) MAX.

= 50pF
= 500n
= 300pF (3)
= 500n
CL = 50pF
RL = 500n
CL = 300pF(3)
RL = 500n
CL = 50pF
RL = 500n
CL = 300pF(3)
RL = 500n
CL = 5pF(3)
RL = 500n
CL = 50pF
RL = 500n

CL
Propagation Delay from
RL
RI toTI orlj to RI
IDT54/74FCT861/IDT54/74 FCT863 C
L
(Non-inverting)
RL
Propagation Delay from
RI to TI or lj to RI
IDT54/74FCT862/IDT54/7 4FCT864
(Inverting)

Output Enable Time 0E"i'" to
lj or O"E"R to RI

Output Disable Time OET to
lj or OEA to RI

IDT54/74FCT861 B-64B
COM'L.
MIN.

MIL.
MIN.

MAX.

-

8

-

10

-

6.0

-

6.5

ns

-

15

-

17

-

13

-

14

ns

-

7.5

-

9.5

-

5.5

-

6.5

ns

-

14

-

16

-

13

-

14

ns

-

15

-

17

-

8.0

-

9.0

ns

-

20

-

22

-

15

-

16

ns

-

9

-

10

-

6

-

7

ns

-

17

-

19

-

7.0

-

8.0

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter guaranteed but not tested.

ORDERING INFORMATION
IDTXXFCT
Temp. Range

XXXX
Device Type

X
Package

X
Process

I·

I Blank

~B

10-197

Commercial
MIL-STD-883, Class B

E
SO
L

Plastic DIP
CERDIP
CERPACK
Small Outline IC
Leadless Chip Carrier

861
862
863
864

10-Bit Non-Inverting Transceiver
10-Bit Inverting Transceiver
9-Bit Non-Inverting Transceiver
9-Bit Inverting Transceiver

P

o

L..------------------1

UNIT

MAX.

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes

The IDT54AHCT138 are 1-of-8 decoders built using advanced
CEMOS T~ a dual metal CMOS technology. The IDT54AHCT138
accepts three binary weighted inputs (Ao, AI, A2) and, when enapled....! provides eight mutually exclusive active LOW outputs
(00 -Ch). The IDT54AHCT138 features three enable inputs, two active LOW (El' E2) and one active HIGH (E3). All outputs will be
HIGH unless Eland E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a
1-of-32 (5 lines to 32 lines) decoder with just four IDT54AHCT138
devices and one inverter.

• 11 ns typical address to output delay
•
10L = 14mA over full military temperature range
• CMOS power levels (5J,1W typo static)
• Both CMO$.!nd TIL output compatible
• Substantially lower Input current levels than ALS (5J,1A max.)
• 1-of-8 decoder with enables
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP/CERPACK
TOP VIEW

cic(~

INDEX

:?IO

UU:;ULJ
3 2 U 20 19
A2

E'1
NC

1

]4
]5

L20-2

]6

E'2 ] 7
E3 :] 8
9

18 [:

01

17[

O2

16[

NC

15 [:

'03

14 [:

04

10 11 12 13

07

'06

05

'04

03

O2

'0 1

00

rnnnn
/0 (!l~ ~ /010)
LCC
TOP VIEW

CEMOS is a trademark of Integrated Device Technology. Inc.

DECEMBER 1987

MILITARY TEMPERATURE RANGE

DSC-4038/-

© 1987 Integrated DevIce Technology, Inc.

10';'198

-

--- - - - - - - - - - - - - - - - - - - -

IDT54AHCT138 HIGH·SPEED
CMOS 1·0F·8 DECODER

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage with Respect
toGND

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

(TA= +25°C. f = 1.0MHz)

PARAMETER(1)

VALUE

UNIT

-0.5 to +7.0

V

C IN

Input Capacitance

COUT

Output Capacitance

TA

Operating Temperature

-55 to +125

°C

TBIAS

Temperature Under Bias

-65 to +135

°C

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

SYMBOL

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
IN GS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vee = 5.0V ± 10%
Vle = 0.2V
VHe = Vee - 0.2V
SYMBOL

TEST CONDITIONS (1)

PARAMETER

MIN.

Typ.(2)

MAX.

UNIT

"IH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

"Il

Input LOW Level

Guaranteed Logic Low Level

0.8

V

IIH

Input HIGH Current

Vee = Max·'~N = Vee

-

III

Input LOW Current

Vee = Max·'~N = GND

-

-

Isc

Short Circuit Current

Vce = Max.P)
Vee = 3V. ~N

VOH

Output HIGH Voltage

Output LOW Voltage

I
I

Vee = Min.
~N = ~Hor~l
Vee = 3V. VIN

VOL

= Vle or ~c. IOH = -32JJA
IOH = -1501JA
IOH = -1.0mA

= Vle or \i-ie. IOl = 300 JJA

I
I

Vee = Min.
~N = VIHor~l

IOl = 300J.lA
10l = 14mA

5.0

J.lA

-5.0

J.lA

-60

-100

-

VHe ,

Vec

-

rna.
rna.

VHe
2.4

Vee

-

4.3

-

V

-

GND

Vle

-

GND

Vle
0.4

-

V

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. + 25 ° C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-199
- - - -.•.

_-------.----------------

IDT54AHCT138 HIGH·SPEED
CMOS 1·0F·8 DECODER

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = O.2V; VHC = Vcc - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS

ICCQ

Quiescent Power Supply Current

Vcc = Max.
VIN ::: VHC ; \'IN ~ VLC
fl = 0

ICCT

Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current (5)

Vcc= Max.
Outputs Open
One Input Toggling
50% Duty Cycle

Vcc = Max.
Outputs Open
fl = 1.0MHz
50% Duty Cycle
One Input Toggling

Icc

MIN.

(1)

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

\'IN ~ VHC
\'IN ~ VLC

-

0.15

0.3

mAl

\'IN ::: VHC
\'IN ~ VLC
(AHCT)

-

0.15

1.8

-

0.4

2.8

VIN = 3.4V
or VIN = GND

Total Power Supply Current (4)

MHz

mA
VjN
Vcc = Max.
Outputs Open
fl = 250kHz
50% Duty Cycle
Six Inputs Toggling

~

VHC (6)
VIN ~ VLC
(AHCT)

-

0.23

2.0

-

1.7

8.0

VIN = 3.4V or (6)
VIN = GND

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. Icc = 10UIESCENT + IINPUTS + IDYNAMIC
Icc = Icco + ICCT DH NT + ICCD (fcp/2 + fl N I)
Icco = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non·Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-200

IDT54AHCT138 HIGH-SPEED
CMOS 1-0F-8 DECODER

MILITARY TEMPERATURE RANGE

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

DESCRIPTION

Ao- A2

Address Inputs

E1 • E2

Enable Inputs (Active LOW)

E3

Enable Input (Active HIGH)

00 - 0 7

Outputs (Active LOW)

TRUTH TABLE
INPUTS

OUTPUTS

E1

E2

E3

Ao

Ai

A2

00

01

O2

03

04

05

0&

07

H
X
X

X
H
X

X
X

L

X
X
X

X
X
X

X
X
X

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

L
L
L
L

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
L
L
L

L
L
L
L

H
H
H
H

L
H
L
H

L
L
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

H
H
H
H

L
H
H
H

H
L
H
H

H
H
L
H

H
H
H
L

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

tpLH
tpHL

PropagatiolJ.. Delay
An to On

tpLH
tpHL

PrQpaga.!ion Q.elay
El or E2to On

tpLH
tpHL

Propagatio!J. Delay
E3 to On

CONDITION(1)

CL = 50pF
RL = 500n

TYP.

MIN.(2)

MAX.

UNIT

11.0

1.5

27.0

ns

13.0

1.5

20.0

ns

13.0

1.5

20.0

ns

NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX
Device Type

X
Process

I

10-201

1 8

MIL-STD-883. Class 8

D
L
E

CERDIP
Leadless Chip Carrier
CERPACK

138

1-of-8 Decoder

54

-55°C to

+ 125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full temperature
and voltage supply extremes

The IDT54AHCT139 are dual 1-of-4 decoders built using advanced CEMOS TM, a dual metal CMOS technology. The device
has two independent decoders, each of which accept two binary
weighted inputs (AQ. -A.1l and provide four mutually exclusive active LOW outputs (00 -03). Each decoder has an active LOWenable (E). When E is HIGH, all outputs are forced HIGH.

•
•
•
•
•

9ns typical address to output delay
IOL = 14mA over full military temperature range
CMOS power levels (5~W typo static)
Both CMOS and TIL output compatible
Substantially lower input current levels than ALS (5~A max.)

• Dual1-of-4 decoder with enable
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

1:A

AOA
AlA
OOA

01A

OZA
03A

GND
DIP/CERPACK
TOP VIEW

:?~

c5

 IIt u u

:] 4

]6

VALUE

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DIP/CERPACK
TOP VIEW

INDEX

(1)

RATING
Terminal Voltage with Respect
toGND

CAPACITANCE

03

~~

(TA= +25°C. f = 1.0MHz)

PARAMETER(l)

SYMBOL
CIN

Input Capacitance

COUT

Output Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

()

* MR for 161

* SA for 163

LCC/PLCC
TOP VIEW

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
TA =
'tc=
VLC =
VHC =

-55°C to + 125°C
5.0V ± 10%
0.2V
Vee - 0.2V

SYMBOL
"'H
"'L
IIH

~
~

PARAMETER

TEST CONDITIONS (1)

TYP.(2)

MAX.

UNIT

-

V

Input HIGH Level

Guaranteed Logic High Level

2.0

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

Input HIGH Current

Vcc = Max.,

-

-

5

~A

"'N = Vcc
Max., "'N = GND

IlL

Input LOW Current

VCC =

Isc

Short Circuit Current

Vcc = Max.!3)

VOH

Output HIGH Voltage

Vcc = Min.

Vcc = 3V, "'N = VLC or VHC ,IOH = -32~A

"'N
Output LOW Voltage

"'N

I

I

-5

~A

-

mA

-

Vcc

VHC

Vcc

-

= -1.0mA

2.4

4.3

-

-

GND

VLC

IoL = 300~A

GND

IoL = 14mA

-

-

VLC
0.4

=

= VLC orVHC ' 10L = 300~A

= "'H or"'L

-100

VHC

I 10H

Vcc = Min.

"'N

-60

-150~A

I 10H

= "'H or"'L

Vee = 3V,
VOL

MIN.

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-207

V

V

IDT54AHCT161/163 HIGH-SPEED CMOS
SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS (IDT54AHCT161)
SYMBOL

PARAMETER

ICCQ

Quiescent Power Supply Current

Vcc = Max.
'-"N ;::: VHC ; '-"N :5 VLC
fcp = fl = 0

ICCT

Power Supply Current per TTL
Inputs HIGH

Vcc = Max.
'-"N = 3.4V(4)

Dynamic Power Supply Current(5)

Vcc = Max.
Outputs Open
Count Mode
CEP = CET = MR =
PE =VHC
PO- 3 = VLC

Total Power Supply Current(4)

Vcc";' Max.
Outputs Open
fcp= 10MHz,
SO% Duty Cycle
Count Mode
CEP = CET = MR =
PE =VHC
PO- 3 = VLC

ICCD

Icc

POWER SUPPLY CHARACTERISTICS (IDT54AHCT163)
PARAMETER

ICCQ

Quiescent Power Supply Current

Vcc = Max.
'-"N ;::: VHC ; '-"N :5 VLC
fcp = fl = 0

ICCT

Power Supply Current per TTL
Inputs HIGH

Vcc = Max.
VIN = 3.4V(4)

Dynamic Power Supply Current (5)

Vcc = Max.
Outputs Open
Count Mode
CEP = CET = SR =
PE =VHC
PO- 3 = VLC

Total Power Supply Current (4)

Vcc = Max.
Outputs Open
fcp = 1.0MHz,
SO% Duty Cycle
Count Mode
CEP = CET = SR =
PE =VHC
PO- 3 = VLC

Icc

TYP.(2)

MAX.

-

0.001

1.S

mA

-

o.s

2.0

mA

CP
'-"N ;::: VHC
'-"N :5 VLC (AHCT)

-

0.2

0.3

mA/MHz

CP
'-"N ;::: VHC
'-"N :5 VLC (AHCT) (6)

-

1.0

3.0

CP
'-"N = 3.4Vor
'-"N = GND(6)

-

MIN.

mA
1.3

4.0

TYP.(2)

MAX.

UNIT

-

0.001

1.S

mA

-

o.s

2.0

mA

CP
'-"N ;::: VHC
'-"N :5 VLC (AHCT)

-

0.2

0.3

mA/MHz

CP
'-"N ;::: VHC
'-"N :5 VLC (AH CT) (6)

-

1.0

3.0

CP
'-"N = 3.4Vor(6)

MIN.

mA

-

1.3

4.0

VIN = GND

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = S.OV, + 2SoC ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. Icc = IQUIESCENT + IINPUTS + IDYNAMIC
Icc = ICCQ + ICCT DH NT + ICCD (fcp/2 + fl N I)
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
S. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-208

UNIT

VLC = 0.2V; VHC = VCC - 0.2V

TEST CONDITIONS (1)

SYMBOL

ICCD

VLC = 0.2V;VHC = VCC -0.2V

TEST CONDITIONS (1)

IDT54AHCT161/163 HIGH-SPEED CMOS
SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARVTEMPERATURE RANGE

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION

PIN NAMES
CEP
CET
CP
MR (,161)
SR('163)
PO- 3

PE

0 0- 3
TC

SR(l)

Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Terminal Count Output

L
H
H
H
H

PE

CET

X
L
H
H
H

CEP

X
X

X
X

H
L

H

X

L

ACTION ON THE RISING
CLOCK EDGE (S)
Reset (Clear)
Load (Pn -+ an)
Count (Increment)
No Change (Hold)
No Change (Hold)

X

NOTES:
1. For AHCT163 only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

CONDITION(l)

TYP.

MIN.(2)

MAX.

UNIT

tpLH
tpHL

Propagation Delay
CP to an (PE Input HIGH)

12.0

2.0

20.0

ns

tpLH
tpHL

Propag!!!l.on Delay
CP to an (PE Input LOW)

12.0

2.0

20.0

ns

tpLH
tpHL

Propagation Delay
CPtoTC

18.0

2.0

30.0

ns

tpHL
tpHL

Propagation Delay
CETtoTC

10.0

1.5

16.0

ns

Delay
to an (161)

10.0

2.0

27.0

ns

Propagation Delay
fJR"to TC

10.0

2.0

31.0

ns

ts(H)
ts (L)

Set-up Time, HIGH or LOW
Pn to CP

-

20.0

-

ns

tH(H)
tH (L)

Hold Time, HIGH or LOW
Pn to CP

-

0

-

ns

ts(H)
ts (L)

Set-up Time, HIGH or LOW
PE orSRto CP

-

20.0

-

ns

tH(H)
tH(L)

Set-up Time, HIGH or LOW
!5E or SF! to CP

-

0

-

ns

ts(H)
ts (L)

Set-up Time, HIGH or LOW
CEP or CET to CP

-

25.0

-

ns

tH(H)
tH(L)

Set-up Time, HIGH or LOW
CEP to CET to CP

-

0

-

ns

tw(H)
twILl

Clock Pulse Width (Load)
HIGH or LOW

-

20.0

-

ns

tw(H)
tw(L)

Clock Pulse Width (Count)
HIGH or LOW

-

20.0

-

ns

tw(L)

MR Pulse Width, LOW
(161)

-

20.0

-

ns

t REC

Recovery Time
MR to CP (161)

-

20.0

-

ns

tpHL
tpHL

p~agation

CL = 50pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

10-209

IDT54AHCT161/163 HIGH·SPEED CMOS
SYNCHRONOUS PRESETTABLE BINARY COUNTERS

MILITARY TEMPERATURE RANGE

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX
Device Type

X

X

Package

Process

I

B

MIL·STD·883. Class B

D
L
E

CERDIP
Leadless Chip Carrier
CERPACK

161

Synchronous Presettable Binary Counter
with Asynchronous Master Reset
Synchronous Presettable Binary Counter
with Synchronous Reset

163

L..----------------------I

10-210

54

·55°C to

+ 125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 8ns typical propagation delay
•
10L = 14mA over full military temperature range
• CMOS power levels (5~W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5~A max.)
• Carry lookahead generator
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class B

The IDT54AHCT182 is a lookahead generator built using advanced CEMOS T~ a dual metal CMOS technology. The
IDT54AHCT182 is generally used with a 4-bit arithmetic logic unit
to provide high-speed lookahead over word lengths of more than
four bits.

PIN CONFIGURATIONS

~Kig~~

INDEX

I

G1

Vcc

151
Go
Po

152

G2
Cn

G3

]5
]6

G3 :J
P3

G

GND

]4

NC

Cn + x
Cn + y

P3
P

GO
150

Cn + z

DIP/CERPACK
TOP VIEW

:J

I.

I

~

L-J

3

2

I

I

II

•••

L-I

I

L-I

U 20 19
1

L20-2

7
8

18 [:

G2

17 [:

Cn

16[

NC

15[:

C n +x

14 [:

Cn + y

~~fi~~
lO- n 0
z z :~
(!1
cJ

mJ

LCC
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated Device Technology, Inc.

DSC-4041/-

10-211

IDT54AHCT182'HIGH-SPEED CMOS
CARRY LOOKAHEAD GENERATOR

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

VALUE

UNIT

Terminal Voltage with Respect
to GND

-0.5 to +7.0

V

CIN

Input Capacitance

COUT

Output Capacitance

TA

Operating Temperature

-55 to +125

°C

TalAs

Temperature Under Bias

-65 to +135

°C

Tsm

Storage Temperature

-65 to +150

°C

PT
, lOUT

(TA= +25°C, f = 1.0MHz)

PARAMETER(l)

RATING

Power Dissipation

0.5

W

DC Output Current

120

mA

SYMBOL

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10 '

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vec = 5.0V ± 10%
VLC = O.2V
VHC = Vee - 0.2V
SYMBOL
VIH
"'L
IIH

TEST CONDITIONS (1)

PARAMETER

MAX.

UNIT

Guaranteed Logic High Level

2.0

-

-

V

Input LOW Level

Guaranteed Logic Low Level

-

-

0.8

V

Input HIGH Current

Vee = Max., '-"N = Vee

-

-

5.0

~A

IlL

Input LOW Current

Vee = Max., VIN = GND

Short Circuit Current

Vee = Max. (3)

VOH

Output HIGH Voltage

Vee = 3V, '-"N = VLe or VHe , IOH = -32J-IA

I
I

Vee = Min.
'-"N = '-"Hor'-"L

IOH = -200~A
10H = -12mA

Vee = 3V, ViN = \te or~e. IOL = 300J-IA
VOL

TYp'(2)

Input HIGH Level

Isc

Output LOW Voltage

I
I

Vee = Min.
'-"N = '-"H or '-"L

IOL = 300~A
IOL = 14mA

MIN.

-

-

-5.0

~A

-60

-100

-

IrA

VHe

Vee

-

IrA

VHe
2.4

Vee
4.3

-

V

-

GND

VLe

GND

VLe
0.4

-

NOTES.
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-212

V

IDT54AHCT182 HIGH·SPEED CMOS
CARRY LOOKAHEAD GENERATOR

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; \1.tc = Vcc - 0.2V
SYMBOL

TEST CONDITIONS

PARAMETER

ICCQ

Quiescent Power Supply Current

Vcc = Max.
VIN ~VHC; "IN :::; 'It.c
fl = 0

ICCT

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current(5)

Vee= Max.
Outputs Open
One Input Toggling
50% Duty Cycle

Total Power Supply Current

Vcc = Max.
Outputs Open
fl = 1.0MHz
50% Duty Cycle
One Bit Toggling

Icc

(4)

MIN.

(1)

'v'JN ~ VHC
'v'JN :::; VLC
'v'JN ~ VHC
'v'JN :::; VLC
(AHCT)

TYP.(2)

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

-

0.15

0.3

-

0.15

1.8

mAl
MHz

(6)

mA
VIN = 3.4V or
VIN = GND

(6)

-

0.4

2.8

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. Icc = IQUIESCENT + IINPUTS + IDYNAMIC
Icc = ICCQ + ICCT DH NT + ICCD (fcp/2 + fl N I)
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-213

UNIT

IDT54AHCT182 HIGH-SPEED CMOS
CARRY LOOKAHEAD GENERATOR

MILITARY TEMPERATURE RANGE

DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION

PIN NAMES
Cn

Carry Input

Gu, G2

Carry Generate Inputs (Active LOW)

G1

Carry Generate Input (Active LOW)

~
Po

Carry Generate Input (Active LOW)
Carry Propagate Inputs (Active LOW)

,P1

P2
P3

Carry Propagate Input (Active LOW)

C n +x-Cn + 2

Carry Outputs

G
P

Carry Generate Output (Active LOW)

Carry Propagate Input (Active LOW)

Carry Propagate Output (Active LOW)

TRUTH TABLE
OUTPUTS

INPUTS
Cn

Go

Po

X

H

X

H
H
L

H

X

L

X
X

X

X

H
H

H

L

X
X
X

H

X

L

X
X
X

X
X

X
X
H

X

P1

G2

P2

G3

P3

L

H
H

X
X
X

X
X
L

X
X
X
X

H

X

L

X
X
X

H
H
H
L

H

en + y

Cn + z

G

P

X
X

L
L

X

X

H
H
H

X
L

X
X

L
L
L
H
H
H

X
X
X

H

X
X
X
X
L
L

X
X

X
X

H
H

H

X
X
X

X
X
L

X
X
X
X

L

X

L

H

q, +x
L
L
H
H

X
X

L

L

X
X

G1

H
H
H
H
L

H

X
X
X

L
L
L

X

X

H
H
H

H

X
L

X
X

X
X
X
X
L
L

H

X

X
X
X

X
X

H

L

L

L

H

L
L
L
L
H
H
H
H

X
X
X
X

X
X

H
H
H
H
L

X
X
X
X

H

X
X
X

L
L
L

X
X
X

X

H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care

10-214

H
H
H
H
L
L
L
L
H
H
H
H
L

IDT54AHCT182 HIGH-SPEED CMOS
CARRY LOOKAHEAD GENERATOR

MILITARY TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
tpLH
tpHL
tpLH
t pHL
tpLH
tpHL

PARAMETER

CON DITION (1)

MIN.(2)

TYP.

Propagation Delay

en to C n + x. Cn + y. en + z
Po. Pc or p:!. to

UNIT

8.0

-

20.5

ns

8.0

-

15.5

ns

8.0

-

15.5

Pr.9p~ati0'l Delay

Cn + x.

MAX.

n + y. C n + z

Plop~ation_ Delay
Go. G1• or G2 • to

Cn + x. Cn + y. Cn + z

CL = 50pF
RL = 500n

ns

tpLH
t pHL

fropagatLon Delay
~. P:!. or R.3. to G

9.0

-

20.5

ns

tpLH
t pHL

Propagation Delay
Gn to G

9.5

-

20.5

ns

tpLH
ProPiigatio_n Delay
8.0
t pHL
Pn to P
NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

-

16.5

ns

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX

x

Device Type

Process

II-------II
~----------------~

B

MIL-STD-883. Class B

D

CERDIP
Leadless Chip Carrier
CERPACK

L
E

'--------------------1
'-----------------------~

10-215

182

Carry Lookahead Generator

54

-55°C to +125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
•
10L = 14mA over full military temperature range
• CMOS power levels (5jJW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5jJA max.)
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class B

The IDT54AHCT191 is a reversible modul0-16 binary counter,
featuring synchronous counting and asynchronous presetting,
built using advanced CEMOS TM, a dual metal CMOS technology.
The preset feature allows the IDT54AHCT191 to be used in programmable dividers. The Count Enable input, the Terminal Count
output and the Ripple Clock output make possible a variety of
methods of implementing multi usage counters. In the counting
modes, state changes are initiated by the rising edge of the clock.

FUNCTIONAL BLOCK DIAGRAM
CP UID

Po

~ 0]
I

~

I

~

~

lQJ

~)

rI

-

~

J

0

1I

)..

CLOCK K

i.....< PRESET

CLEAR

O

Q

1
fie

T

I

TC

P.

L--

1

II

)..

10
I

J CLOCK K
-< PRESET
CLEAR PQ
L-

?

a
1

?

I

Vtl
1

II

J..

1
I

J CLOCK K
-< PRESET
CLEAR :>Q
L-

a
1

?

.

~ tJ
1

II

)..

I

J CLOCK K
-< PRESET
CLEAR pQ
L-

a
1

?

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE
©

DECEMBER 1987

1987 Integrated DevIce Technology. Inc.

DSC-4042/-

10-216

IDT54AHCT191 HIGH·SPEED CMOS
UP/DOWN BINARY COUNTER

MILITARY TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

PIN· CONFIGURATIONS

SYMBOL
P1

Vcc

01
00

cr

CP

RC

U/D

VTERM

Po

Operating Temperature

-55 to +125

°C

-65 to +135

°C

TC

TSTG

Storage Temperature

-65 to +150

°C

O2

PC

PT

Power Dissipation

0.5

W

03

P2

lOUT

DC Output Current

120

mA

GND

P3

;: U
3

2

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

Ll

LJ 20 19

:J 4

18 [:

CP

]5

17 [:

RC

16C

NC

15 [:

TC

L20-2

]6

UID ]7

O2

V

Temperature Under Bias

oa:-~~rE

NC

UNIT

TA

INDEX

00

VALUE
-0.5 to +7.0

TSIAS

DIP/CERPACK
TOP VIEW

cr

(1)

RATING
Terminal Voltage with Respect
toGND

:J 8

14 [:

CAPACITANCE
SYMBOL
CIN

PC

nnn ~~
9

10 11

(TA= +25°C. f = 1.0MHz)

PARAMETER(l)
Input Capacitance

CONDITIONS TYP.
VIN = OV

MAX. UNIT

6

10

pF

Output Capacitance
VOUT= OV
COUT
8
12
pF
NOTE:
1. This parameter is measured at characterization but not tested.

o'" z0 0z rf'rf:'
c:l

LCC
TOP VIEW

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vcc = 5.0V ± 10%
VLC = 0.2V
VHC = Vcc - 0.2V
SYMBOL
"'H
"'L
IIH

TEST CONDITIONS (1)

PARAMETER

MAX.

UNIT

Guaranteed Logie High Level

2.0

-

-

V

Input LOW Level

Guaranteed Logie Low Level

-

-

0.8

V

Input HIGH Current

Vce = Max·'~N = Vcc

-

-

5.0

J.lA

IlL

Input LOW Current

Vcc = Max·'~N = GND

Short Circuit Current

Vee = Max. (3)

VOH

Output HIGH Voltage

Vcc = 3V. ~N = VLC orVHC.I OH = -32j.JA

I
I

Vcc = Min.
~N = ~Hor~L

10H = -150~A
10H = -1.0mA

Vcc = 3V. 'ViN = VLC or '.i-ic. 10L = 300j.JA
VOL

Typ.(2)

Input HIGH Level

Isc

Output LOW Voltage

I
I

Vcc = Min.
"IN = "IH or"lL

10L = 300J.lA
10L = 14mA

MIN.

-

-

-5.0

J.lA

-60

-100

-

ITA

VHe
VHC

Vce

-

ITA

Vcc

2.4

4.3

-

V

-

GND

VLC

GND

VLC
0.4

-

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-217

V

IDT54AHCT191 HIGH-SPEED CMOS
UP/DOWN BINARY COUNTER

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0 2V· VHC = VCC - 0 2V
SYMBOL

TEST CONDITIONS

PARAMETER

ICCQ

Quiescent Power Supply Current

Vcc = Max.
VIN 2: VHC: "IN ~ VLC
fcp = fl = 0

ICCT

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Icco

Dynamic Power Supply Current(5)

Icc

Vcc= Max.
Outputs Open
Count Up or Down
CE = VLC
~L = Po-~ = VHC
UID = VHC or VLC

"IN 2: VHC
"IN ~ VLC

Vcc = Max.
Outputs Open
fcp = 1.0MHz
50% Duty Cycle
~unt Up or Down
~E = VLC
fL = Po - P3 = ~c
UfD = VHC or VLC

Total Power Supply Current (4)

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

-

0.2

0.3

mAl
MHz

-

0.2

1.7

MIN.

(1)

"IN 2: VHC
"IN ~ VLC
(AHCT)

(6)

V IN = 3.4V or
VIN = GND

mA
(6)

-

0.3

2.7

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. Icc = IQUIESCENT + IINPUTS + IDYNAMIC
Icc = ICCQ + ICCT DH NT + ICCD (fcp/2 + fl N I)
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

RC TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS

TC(l)

CE

CP

U

U

L

H

H

X

X

H

X

L

X

H

. NOTES:
1. TC is generated internally.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

TRUTH TABLES
MODE SELECT TABLE
INPUTS
MODE
PL

CE

UfD

CP

H

L

L

H

L

H

t
t

L

X

X

H

H

X

X
X

DESCRIPTION

PIN NAMES

RC

Count Up
Count Down
Preset (Asynch.)
No Change (Hold)

10-218

BE

Count Enable Input (Active LOW)

CP

Count Pulse Input (Active Rising Edge)

Pa-3

Parallel Data Inputs

"PL

Asynchronous Parallel Load Input (Active LOW)

UID

UplDown Count Control Input

QO-3

Flip-Flop Outputs

Rc

Ripple Clock Output (Active LOW)

TC

Terminal Clock Output (Active HIGH)

.__

IDT54AHCT191 HIGH-SPEED CMOS
UP/DOWN BINARY COUNTER

.~I--.

.__ __
~

~!!l

......._____ ..;

MILITARY TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
MIN!2)

MAX.

UNIT

-

1.5

22.0

ns

-

2.0

34.0

ns

Propagation Delay
CP to RC

-

1.5

24.0

ns

t pLH
tpHL

Propagation Delay
GEtoRC.

-

2.0

21.0

ns

tpLH
t pHL

Propagation Delay
UID to 11C

-

4.0

30.0

ns

tpLH
t pHL

Propagation Delay
UID toTC

-

3.0

30.0

ns

tpLH
tpHL

Propagation Delay
Pn to an

-

1.5

2S.0

ns

tpLH
tpHL

prop~ation

-

3.0

34.0

ns

-

2S.0

-

ns

ns

SYMBOL

PARAMETER

tpLH
tpHL

Propagation Delay
CPto an

tpLH
t pHL

Propagation Delay
CP to TC

tpLH
tpHL

L to

CONDITION(1)

TYP.

Delay

an

CL = SOpF
RL = soon

ts(H)
ts(L)

Set-up Time
HIGH or LOW
Pn to PC

tH(H)
tH (L)

Hold Time
HIGH or LOW
Pn to PC

-

1.5

-

ts (L)

Set-up Time LOW
GEto CP

-

2S.0

-

tH(L)

Hold Time LOW
CE to CP

-

0

-

ts(H)
ts(L)

Set-up Time
HIGH or LOW
UID to CP

-

20.0

-

ns

tH(H)
tH(L)

Hold Time
HIGH or LOW
UID to CP

-

0

-

ns

tw(L)

J5[ Pulse Width LOW

-

25.0

-

ns

tw(L)

CP Pulse Width LOW

-

20.0

-

ns

t REC

Recovery Time
15[to CP

-

20.0

-

ns

NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX
Device Type

X

x

Package

Process

---II

B

MIL-STD-883, Class B

'------------1

D
L
E

CERDIP
Leadless Chip Carrier
CERPACK

191

Binary UplDown Counter

1.--1

L..------------------i

' - - - - - - - - - - - - - - - - - - - - - - - - ; 54

10-219

-55°C to

+ 125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• IoL = 14mA over full military temperature range
• CMOS power levels (5)JW typo static)
• Both CMOS and TIL output compatible
• Substantially lower input current levels than ALS (5)JA max.)
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class B

The IDT54AHCT193 is an u,e/down modulo-16 binary counter
built using advanced CEMOS M, a dual metal CMOS technology.
Separate count-up and count-down clocks are used and, in either
counting mode, the circuits operate synchronously. The outputs
change state synchronously with the LOW-to-HIGH transitions on
the clock inputs. Separate Terminal Count-up and Terminal Countdown outputs are provided that are used as the clocks for subsequent stages without extra logic, thus simplifying multi usage
counter designs. Individual preset inputs allow the circul!.. to be
used as a programmable counter. Both the Parallel Load (Pl) and
the Master Reset (MRl inputs asynchronously override the clocks.

FUNCTIONAL BLOCK DIAGRAM
Po

P,

iCo
(BORROW)

MR

0,

CEMOS Is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE
©

DECEMBER 1987.

'987 Integrated DevIce Technology, Inc.

DSC-4043/-

10-220

IDT54AHCT193 HIGH-SPEED
CMOS UP/DOWN BINARY COUNTER

MILITARY TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATIONS

VTERM

VALUE

UNIT

Terminal Voltage with Respect
toGND

-0.5 to +7.0

V

INDEX

00
CPD
NC

L.....!

3

2

I

U

I

L....I

TA

Operating Temperature

-55 to +125

°C

TSIAS

Temperature Under Bias

-65 to +135

°C

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DIP/CERPACK
TOP VIEW

L..-I

(1)

RATING

SYMBOL

L-J

20 19

:J 4
:J 5

1

] 6

L20-2

MR

TeD
NC

CAPACITANCE

iC u

CPu] 7

O2 ] 8

SYMBOL

PL
9

10 11 12 13

nnnnn

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CIN

Input Capacitance

COUT

Output Capacitance

MAX. UNIT

CONDITIONS TYP.
VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.
LCC
TOP VIEW

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vee = 5.0V + 10%
VlC = 0.2V
VHC = Vee -0.2V
TEST CONDITIONS(1)

MIN.

TYP.(2)

MAX.

UNIT

V,H

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

V,l

Input LOW Level

Guaranteed Logic LOW Level

V

Input HIGH Current

Vee = Max., ~N = Vee

-

0.8

IIH

-

5

pA

-5

)JA

-60

-100

-

mA

VHe
VHC

Vee

2.4

4.3

-

-

GND

VlC

GND

VLC

-

0.4

SYMBOL

PARAMETER

'll

Input LOW Current

Vec = Max., VIN

Isc

Short Circuit Current

Vec = Max. (3)

VOH

Output HIGH Voltage

Vee = 3V, ~N

= GND

= Vle or VHC ' 10H = -32 JJA

I 10H = -150)JA

Vee = Min.
~N = ~H or~l

I IOH =-1.0mA

Vec = 3V, VIN = VLe or VHe , 10l = 300 JJA
VOL

Output LOW Voltage

I IOl = 300pA

VCC = Min.
~N = ~H or~l

I 10l = 14mA

Vee

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-221

V

·V

IDT54AHCT193 HIGH-SPEED
CMOS UP/DOWN BINARY COUNTER

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS.
VLC = 0 2V' ~C = VCC - 02V
SYMBOL

PARAMETER

TEST CONDITIONS(1)

ICCQ

Quiescent Power Supply Current

Vee = Max.
VIN ~ VHC ; "'N ~ VLC
fcpu = fcpo = fl = 0

ICCT

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current(5)

Icc

Total Power Supply Current(4)

Vcc= Max.
Outputs Open
Count Up or Down
P'L = Po-~ = VHC
MR= VLC
Vcc = Max.
Outputs Open
fcp = 1.0MHz
50% Duty Cycle
fount Up or Down
PL = Po-F?! = VHC
MR = \tc

MIN.

'-"N ~ VHC
'-"N ~ VLC

'-"N ~ VHC(B)
VIN ~ VLC
(AHCT)
VIN
VIN

= 3.4V or(B)
= GND

TYP.(2)

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

-

0.2

0.3

mAl

-

0.2

1.7

MHz

mA

-

0.3

2.7

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. Icc = IQUIESCENT + IINPUTS + IDYNAMIC
Icc = ICCQ + ICCT DH NT + ICCD (fcp/2 + fl N I )
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-222

UNIT

--------IDT54AHCT193 HIGH-SPEED
CMOS UP/DOWN BINARY COUNTER

MILITARY TEMPERATURE RANGE

FUNCTION TABLE

DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION

PIN NAMES

MR

l5t:
X

MODE

CPu

CPD

X

X

Reset (Asyn.)

Count Up Clock Input (Active Rising Edge)

H

CPo

Count Down Clock Input (Active Rising Edge)

L

L

X

X

Preset (Asyn.)

MR

Asynchronous Master Reset Input (Active HIGH)

L

H

H

H

No Change

PI:

Asynchronous Parallel Load Input (Active LOW)

L

H

t

H

Count Up

Pa-3

Parallel Data Inputs

L

H

H

t

Count Down

CPu

°0-3

Flip-Flop Outputs

reo

Terminal Count Down (Borrow) Output (Active LOW)

iCu

Terminal Count Up (Carry) Output (Active LOW)

H = HIGH Voltage Level
L = LOW Voltage Level
X

= Immaterial

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
tpLH
t pHL

PARAMETER

CONDITION(1)

TYP.

Propagation Delay

MIN.(2)

MAX.

UNIT

~or~
u or
0

-

2.0

19.0

ns

tpLH
t pHL

Propagation Delay
CPu or CPo to an

-

2.0

20.0

ns

tpLH
t pHl

Propagation Delay
Pn to an

-

2.0

20.0

ns

tpLH
tpHL

propPtation Delay
to an

-

2.0

31.0

ns

t pHl

Propagation Delay
MR to an

-

3.0

31.0

ns

tpLH

Propagation Delay
MRtoTCu

-

3.0

31.0

ns

t PHL

Propagation Delay
MRtoTCo

-

3.0

31.0

ns

tpLH
tpHL

Propagation Delay
]5[ to TCuor Teo

-

3.0

31.0

ns

t pLH
tpHL

propa~on Delay
Pn to C u or Teo

-

3.0

20.0

ns

ts(H)
ts(L)

Set-up Time.
HIGH or LOW
Pn to l5[

-

25.0

-

ns

tH(H)
tH(L)

Hold Time.
HIGH or LOW
Pn to J5[

-

"1.5

-

ns

C L = 50pF
RL = SOOO

PI: Pulse Width.
LOW

-

25.0

-

ns

tw(L)

CPu or CPo
Pulse Width. LOW

-

20.0

-

ns

tw(L)

CPu or CPo
Pulse Width. LOW
(Change of Direction)

-

20.0

-

ns

tw(H)

MR Pulse Width.
HIGH

-

10.0

-

ns

t REc

Recovery Time
l5[ to CPu or CPo

-

20.0

-

ns

t REc

Recovery Time
MR to CPu or CPo

-

20.0

-

ns

tw(L)

NOTES:

1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

10-223

IDT54AHCT193 HIGH-SPEED
CMOS UP/DOWN BINARY COUNTER

MIUTARYTEMPERATURERANGE

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

>O
•

So

(3)

Fa

00

(18)

(2)

(16)

A3
Ia:
-..

01:

Bl
A2

DIP/CERPACK
TOP VIEW

0

(19)

(17)

Be
Br

--

(1)

(9)

Be

A7

a)" mco mill .

(11)

(!)

Br

LCC
TOP VIEW

CEMOS is a registered trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE
©

DECEMBER 1987
DSC-4046/-

19S71ntegrated Device Technology. Inc.

10-233

IDT54AHCT245 HIGH-SPEED CMOS
NON-INVERTING BUFFER TRANSCEIVER

MILITARY TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS· (1)
UNIT

-0.5 to +1.0

V

Operating Temperature

-55 to +125

°C

TBIAS

Temperature Under Bias

-65 to +135

°C

TSTa

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

VTERM
TA

RATING
. Terminal Voltage with Respect
toGND

CAPACITANCE
VALUE

SYMBOL

SYMBOL
CIN

(TA= +25°C f = 10MHz)

PARAMETER(1)
Input Capacitance

MAX. UNIT

CONDITIONS TYP.
VIN = OV
VOUT= OV

6

10

pF

1/0 Capacitance
8
pF
12
ClIO
NOTE:
1. This parameter is measured at characterization but not tested.

DC Output Current
120
mA
lOUT
NOTE:
.1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vee = 5.0V + 10%
VLC = O.2V
VHC = Vee - O.2V
SYMBOL
VIH
"'L

TEST CONDITIONS (1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

Input LOW Level

Guaranteed LO!;jic LOW Level

-

-

0.8

V

-

-

5

IJA

-

-

-5

IJA

\

IIH

Input HIGH Current
(Except I/O Pins)

Vcc = Max.• \tiN = Vcc

IlL

Input LOW Current
(Except I/O Pins)

Vee

IIH

Input HIGH Current
(1/0 Pins)

Vcc = Max.• Va = Vcc

-

-

15

IJA

IlL

Input LOW Current
(I/O Pins)

Vcc = Max.• Vo = GND

-

-

-15

jJA

Iso

Short Circuit Current

Vcc = Max. (3)

-60

-100

-

mA

Vcc = 3V. VIN = VLC or ~c. IOH = -32 jJA

VHC
VHC

Vee

-

Vee

-

2.4

4.3

-

VOH

O~ut HIGH Voltage

Po A and B

= Max.• VIN

= GND

I
I

Vce = Min.
\tiN = \tiH Qr\tiL

IOH = - 15OIJA
IOH = -12mA

Vcc = 3V. \tiN = VLC or VHC ' IOL = 300
VOL

0u:r.ut LOW Voltage
Po A and B

l

Vcc = Min.
VIN = \tiH or VIL

IOL = 300IJA

I IOL = 14mA

-

GND

VLC

GND

VLC

-

0.4

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-234

V

V

IDT54AHCT245 HIGH-SPEED CMOS
NON-INVERTING BUFFER TRANSCEIVER

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V: VHC = VCC - 0.2V
PARAMETER

ICCQ

Quiescent Power Supply Current

Vcc= Max.
VIN ~ VHC ; \'IN :5 VLC
fl = 0

ICCT

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

Dynamic Power Supply Current(5)

Vcc= Max.
Outputs Open
OE = GND
T/R = GND or Vcc
One Input Toggling
50% Duty Cycle

ICCD

Vcc = Max.
Outputs Open
fl = 1.0MHz
50% Duty Cycle
OE = GND
One Bit Toggling

Icc

TYP.(2)

MAX.

-

0.001

1.5

rnA

-

0.5

2.0

rnA

\'IN ~ VHC
\'IN :5 VLC

-

0.15

0.25

rnA!
MHz

\'IN ~ VHC
VIN :5 VLC
(AHCT)

-

0.15

1.8

VIN = 3.4V
\'IN = GND

-

0.4

2.8

TEST CONDIT/ONS (1)

SYMBOL

MIN.

UNIT

rnA

Total Power Supply Current(4)
VCC = Max.
Outputs Open
fl = 250kHz
50% Duty Cycle
OE = GND
Eight Bits Toggling

\'IN ~ VHC (6)
"IN :5 VLC
(AHCT)

-

0.3

2.0

-

2.3

10.0

"IN = 3.4V(6)
VIN = GND

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vco = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V): all other inputs at Vcc or GND.
4. lco = IQUIESCENT + IINPUTS + IDYNAMIC
lco = Icco + ICOT DH NT + ICOD (fcp/2 + fl N I)
ICOQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-235

m

IDT54AHCT245 HIGH-SPEED CMOS
NON-INVERTING BUFFER TRANSCEIVER

MILITARY TEMPERATURE RANGE

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION
Output Enable Input (Active LOW)

PIN NAMES
OE
T/A

TransmiVReceive Input

Ao-A7

Side A Inputs or 3-State Outputs

8o-B 7

Side B Inputs or 3-State Outputs

INPUTS
OE

OUTPUTS

TIR

Bus B Data to Bus A

L

L

L

H

Bus A Data to Bus 8

H

X

High Z State

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

tpLH
tpHL

Propagation Delay
Ato 8
8to 8

tZH
tZL

Output Enable
Time

tHZ
tLZ

Output Disable
Time

tDLH
tDHL

Propagation Delay
T/~ to A or 8(3

CONDITION(1)

CL = 50pF
RL = 500n

TYP.

MIN.(2)

MAX.

UNIT

8.0

1.5

15.0·

ns

15.0

1.5

25.0

ns

11.0

1.5

18.0

ns

14.0

-

-

ns

NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed by design.

ORDERING INFORMATION
IDTXXAH CT
Temp. Range

XXXX

X

Device Type

Process

~I

1---'

~----------I

8

o
L
E

1------------------1 245
L--_ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ __!

10-236

54

MIL-STD-883, Class 8
CERDIP
Leadless Chip Carrier
CERPACK
Non-Inverting 8uffer Transceiver
-55°C to +125°C

FEATURES:

DESCRIPTION:

• Equivalent toAlS speeds and output drive over full temperature
and voltage supply extremes
• 10ns typical clock to output
• IOL = 14mA over full military temperature range
• CMOS power levels (5~W typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than AlS (5~A max.)
• Octal D flip-flop with clear
• JEDEC standard pinout for DIP and lCC
• Military product compliant to Mll-STD-883, Class B

The IDT54AHCT273 are octal D flip-flops built using advanced
CEMOS TM, a dual metal CMOS technology. The IDT54AHCT273
has eight edge-triggered D-type flip-flops with individual D inputs
and Q9utputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input,
one set-up time before the lOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's 0 output.
All outputs will be forced LOW in~endently of Clock or Data
inputs by a lOW voltage level on the M R input. The device is useful
for applications where the true output only is required and the
Clock and Master Reset are common to all storage elements.

PIN CONFIGURATIONS
1M!

Vee

00

03
03

07
07
06
06
05
05
04
04

GNO

CP

Do
Dl

01
O2
O2

0
...
o0d'~
:!E~O

INDEX

01
01
~
O2

03

'"

L..I

I
L...I

3

2

,'1

I

U

I

I

L..I

I

I

L..I

20 19

1

]4

07
06
06
05
05

]5

L20-2

]6

:J 7
:J 6
9

10 11

m

12 13

nnnnn

'" 0 a.. " "
°zoOO
(!l

DIP/CERPACK
TOP VIEW

LCC
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
00

01

O2

03

04

05

D6

07

CP

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE
©

DECEMBER 1987

1967 Integrated Device Technology. Inc.

DSC-4047/-

10-237

IDT54AHCT273 HIGH-SPEED
CMOS OCTAL D FLIP-FLOP WITH CLEAR

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage with Respect
to GND

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

VALUE

UNIT

-0.5 to +7.0

V

TA

Operating Temperature

-55 to +125

°C

TBIAs

Temperature Under Bias

-65 to +135

°C

TSTG

Storage Temperature

-65 to + 150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

SYMBOL
CIN

(TA= +25°C. f = 1.0MHz)

PARAM ETER (1)
Input Capacitance

MAX. UNIT

CONDITIONS TYP.
VIN = OV

6

10

pF

Output Capacitance
pF
COUT
8
12
VOUT= OV
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1, Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vcc = 5.0V ± 10%
VlC = 0.2V
VHC = Vcc - 0.2V
SYMBOL
"'H
"'l
IIH

MIN.

TYP.(2)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

Input LOW Level

Guaranteed Logic Low Level

-

0.8

V

Input HIGH Current

Vcc = Max·.\'IN = Vcc

-

-

5.0

iJ A

TEST CONDITIONS (1)

PARAMETER

III

Input LOW Current

Vcc = Max·.\'IN = GND

-

-

-5.0

iJ A

Isc

Short Circuit Current

Vcc = Max. (3)

-60

-100

-

rrA

Vcc = 3V. \'IN = VLC orVHc.l oH = -32iJA

V HC

Vcc

-

rrA

VHC
2.4

Vcc

-

V

VOH

Output HIGH Voltage

I
I

Vee = Min.
\'IN = VIHorVll

IOH = -150uA
IOH = -1.0mA

Vcc = 3V. VIN = VLC or~C.IOl = 300iJA
VOL

Output LOW Voltage

I
I

Vcc = Min.
\'IN = \'IH orVll

IOl = 300iJA
IOL = 14mA

-

-

4.3
GND

VLC

GND

VLC
0.4

-

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-238

-

V

IDT54AHCT273 HIGH-SPEED
CMOS OCTAL D FLIP-FLOP WITH CLEAR

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0 2V; VHC = vcc - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS

(1)

MIN.

Typ.(2)

MAX.

Icco

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC : ~N $ VLC
fcp = fl = 0

ICOT

Power Supply Current P~r TIL
Inputs HIGH

Vcc = Max.
~N = 3.4V(3)

Dynamic Power Supply Current (5)

Vcc = Max.
Outputs Open
JJR = Vcc
One Bit Toggling
50% Duty Cycle

~N ~ VHC
~N $ VLC

-

0.15

0.25

Vcc = Max.
Outputs Open
fcp = 1.0MHz.
50% Duty Cycle

~N ~ VHC
~N $ VLC
(AHCT)

-

0.15

1.8

-

0.65

3.8

ICCD

MR "'" Vcc
One Bit Toggling
atf l = 500kHz
50% Duty Cycle
lco

~N ;"·3.4V

or
~N = GND

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

mA/MHz

Total Power Supply Current (4)

rnA
Vcc = Max.
Outputs Open
fcp= 1.0MHz.
50% Duty Cycle
MR = Vcc
Eight Bits Toggling
fl = 250kHz
50% Duty Cycle

~N ~

VHC (6)
~N $ VLC
(AHCT)

-

0.63

2.2

-

2.88

11.2

~N = 3.4V(6)

or
~N = GND

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Per TIL driven input ~N = 3.4V); all other inputs at Vcc or GND.
4. Icc = 'QUIESCENT + 'INPUTS + IDYNAMIC
lco = Icco + ICOT DH NT + ICOD (fcp/2 + fl N I)
ICOQ = Quiescent Current
ICCT = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICOD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = ClockFrequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-239

IDT54AHCT273 HIGH-SPEED
CMOS OCTAL 0 FLIP-FLOP WITH CLEAR

MILITARY TEMPERATURE RANGE

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

Do - 0 7
JJR
-

07

INPUTS

OPERATING MODE
MR'

Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs

CP

00

TRUTH TABLE

DESCRIPTION

OUTPUT

CP

ON

~

Reset (Clear)

L

X

X

L

Load '1'

H

h

H

Load '0'

H

t
t

I

L

H = HIGH Voltage steady state
h = HIGH Voltage Level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW Voltage Level steady state
I = LOW voltage Level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don't Care
= LOW-to-HIGH clock transition

t

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

CONDITION(1)

TYP.

MIN.(2)

MAX.

UNIT

tpLH
tpHL

Propagation Delay
CP to On

10.0

2.0

17.0

ns

tpLH
tpHL

Propagation Delay
fM! to Output

12.0

2.0

21.0

ns

3.0

10.0

-

ns

0.6

1.0

-

ns

ts

Set-up Time
High or Low
. Data to CP

tH

Hold Time
High or Low
Data to CP

tw

Clock Pulse Width
High or Low

10.0

16.0

-

ns

Recovery Time
MRto CP

5.0

15.0

-

ns

t REc

CL = 50pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX

X

Device Type

Process

IL-------il
'------------1

B

MIL-STD-883, Class B

o

CERDIP
Leadless Chip Carrier
CERPACK

L
E

'--_ _ _ _ _ _ _ _ _ _ _ _ _---1 273
' - - - - - - - - - - - - - - - - - - - - - - - \ 54

10-240

Octal 0 Flip-Flop with Clear
-55°C to

+ 125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 9ns typical clock to output
• 10l = 14mA over full military temperature range
• CMOS power levels (5~W typo static)
• 80th CMOS and TIL output compatible
• Substantially lower input current levels than ALS (5~A max.)

The IDT54AHCT299 is an 8-input universal shift register built
using advanced CEMOS TM, a dual metal CMOS technology. The
IDT54AHCT299 is an 8-input universal shift/storage register with
3-state outputs. Four modes of operation are possible: hold (store),
shift left, shift right and load data. The parallel load inputs and flipflop outputs are multiplexed to reduce the total number of package
pins. Additional outputs are provided for flip-flops 00-07 to allow
easy serial cascading. A separate active LOW Master Reset is used
to reset the register.

• 8-input universal shift register
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8

PIN CONFIGURATIONS

~I~

INDEX

U U
3

I/Oe ]4
1/0 4 ]5

1/0 2

]

6

1/0 0

]

7

0

cE' >0 C/),; u u

2 U 20 19
1
18[
17 [:

leC 1/0 7

L20-2

15C 1/0 5
14[ 1/0 3

00 ] 8

GND

DS o

DS 7
07

~~~

f4A

~ 0

a.

c/)0

~OU

m

g

LCC
TOP VIEW

DIP/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Sl

So

CEMOS is a registered trademark of Integrated Devi~~ Technology, Inc.

MILITARY TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated Device Technology. Inc.

OSC-4048/-

10-241

IDT54AHCT299 HIGH·SPEED CMOS
8·INPUT UNIVERSAL SHIFT REGISTER

ABSOLUTE MAXIMUM RATINGS

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

(TA= +25°C, f = 1.0MHz)

RATING

VALUE

UNIT

VTERM

Terminal Voltage with Respect
toGND

-0.5te +7.0

V

C IN

Input Capacitance

TA

Operating Temperature

-55 to +125

°C

COUT

Output Capacitance

TBIAS

Temperature Under Bias

-65 to +135

°C

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

SYMBOL

SYMBOL

PARAMETER(1)

MAX. UNIT

CONDITIONS TYP.
VIN = OV

6

10

pF

VOUT = OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Str~sses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°Cto +125°C
Vcc = 5.0V + 10%
VLC = 0.2V
VHC = Vcc - 0.2V
MIN.

TYP.(2)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

V

Input LOW Level

Guaranteed Logic LOW Level

0.8

V

IIH

Input HIGH Current
(Except I/O Pins)

Vcc = Max., VIN = Vee

-

-

-

5

J.lA

IlL

Input LOW Current
(Except I/O Pins)

Vcc = Max., V1N = GND

-

-

-5

J.lA

IIH

Input HIGH Current
(1/0 Pins)

Vcc = Max., VI = Vcc

-

-

15

J.lA

IlL

Input LOW Current
(I/O Pins)

Vcc = Max., VI = GND

-

-

-15

J.lA

Short Circuit Current

Vcc = Max. (3)

-60

-100

-

mA

VHC
VHC

Vcc

Output HIGH Voltage

Vcc = 3V, VtN = VLC or VHC , 10H = -32J.lA
10H =-200J.lA
Vcc = Min.
VIN = VtH or VtL
10H =-1.0mA

V

2.4

4.3

-

SYMBOL
"'H
"'L

Isc

VOH

TEST CONDITIONS (1)

PARA.'ETER

I
I

Vcc = 3V, VIN = VLC or VHC , 10L = 300J,JA
VOL

Output LOW Voltage

I 10L = 300J.lA

Vee == Min.
V1N = VIHorVIL

I

10L-= 14mA

Vcc

-

GND

VLC

.-

GND

VLC

-

-

0.4

V

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-242

-~-

----_._---

---------

IDT54AHCT299 HIGH-SPEED CMOS
a-INPUT UNIVERSAL SHIFT REGISTER

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; \1.ic = vee - 0.2V
SYMBOL

PARAMETER

ICCQ

Quiescent Power Supply Current

ICCT

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3AV(3)

Dynamic Power Supply Current(S)

Vcc= Max.
Outputs Open
OE l = DE2 = GND
MR = Vcc
So = Sl = VCC
DSo = DS l = GND
One Bit Toggling
50% Duty Cycle

leeD

Icc

TYP.(2)

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

ViN ;::: VHC
"'IN :5 VLC

-

0.15

0.25

mAl

"'IN ;::: VHC
"'IN :5 VLC
(AHCl)

-

0.15

1.8

VIN = 3AVor
VIN = GND

-

0.65··

3.8

TEST CONDITIONS(l)
Vee = Max.
VIN ;::: VHC ; ViN :5 VLC
fcp = fl = 0

Vcc = Max.
Outputs Open
fcp= 1.0MHz
50% D~Cycle
OEl = OE 2 = GND
MR = Vcc
Sa=Sl=VCC
DS o = DS l = GND
One Bit Toggling
at fl = 500kHz
50% Duty Cycle

MIN.

UNIT

MHz

1

Total Power Supply Current(4)

mA
Vcc = Max.
Outputs Open
fcp= 1.0MHz
50% Du.!Y,.Cycle
OEl = OE2 = GND
MR = Vcc
Sa = Sl = Vcc
DSo = DSl = GND
Eight Bits Toggling
at fl = 250kHz
50% Duty Cycle

"'IN ;::: VHC (6)
"'IN :5 VLC
(AHCl)

VIN = 3AV (6)
VIN = GND

-

0.63

2.2

-

2.88

11.2

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. + 25°C ambient and maximum loading.
3. Per TTL driven input ("'IN = 3AV); all other inputs at Vcc or GND.
4. Icc = IQUIESCENT + IINPLrrS + IDYNAMIC
Icc = ICCQ + ICCT DH NT + leeD (fcp/2 + fl N I)
leeQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable. but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-243

IDT54AHCT299 HIGH-SPEED CMOS
8-INPUT UNIVERSAL SHIFT REGISTER

MILITARY TEMPERATURE RANGE

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION

PIN NAMES

INPUTS

CP

Clock Pulse Input (Active Edge Rising)

DSo

Serial Data Input for Right Shift

RESPONSE

CP

MR

Sl

So

L

X

X

X

Parallel Load; 1I0~ON

Asynchronous Reset 0 0 • 0 7 = LOW

DS7

Serial Data Input for Left Shift

H

H

H

S

~,S7

Mode Select Inputs

H

L

H

S

Shift Right DS o -+00 , 0 0 -+0 1 • etc.

MR

Asynchronous Master Reset Input (Active LOW)

H

H

L

S

Shift Left; DS7 -+0 7• 0 7-+0 6 • etc.

OE1 • 0E 2

3-State Output Enable Inputs (Active LOW)

H

L

L

X

Hold

1100 -110 7

Parallel Data Inputs or 3-State Parallel Outputs

0 0 .0 7

Serial Outputs

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
PARAMETER

SYMBOL

CONDITION(l)

TYP.

MIN.(2)

MAX.

UNIT
ns

tpLH
tpHL

Propagation Delay
CPto 0 0 or 0 7

9.0

-

17.0

tpLH
tpHL

Propagation Delay
CPto liON

8.0

15.0

ns

9.0

-

15.0

ns

9.0

-

15.0

ns

10.0

-

18.0

ns

tpHL
tpHL

p~agation Delay

to 0 0 or 0 7
Delay
to liON

pro~ation

tZH
tZL

Output Enable Time
rn:to liON

tHZ
tLZ

Output Disable Time
rn:to liON

7.5

-

12.0

ns

ts

Setup Time HIGH or LOW
So or Sl to CP

4.0

8.5

-

ns

tH

Hold Time HIGH or LOW
So orS1 to CP

1.0

0.0

-

ns

ts

Setup Time HIGH or LOW
liON. DSo or DS7 to CP

1.5

5.5

-

ns

tH

Hold Time HIGH or LOW
liON. DS o or DS7 to CP

0

2.0

-

ns

tw

CP Pulse Width HIGH or LOW

8.0

8.0

-

ns

tw

Krn Pulse Width Low
Recovery Time Krn to CP

8.0

8.0

-

ns

8.0

8.0

-

ns

t REC

CL = 50pF
RL = soon

NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAH CT
Temp. Range

XXXX
Device Type

X
Process

----II

B

MIL-STD-883. Class B

'-----------i

D
L
E

CERDIP
Leadless Chip Carrier
CERPACK

, - - - I

'-----------------1

299

'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 54

10-244

a-Input Universal Shift Register
-55°C to +125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full temperature
and voltage supply extremes

The IDT54AHCT373 are 8-bit latches built using advanced
CEMOS rM , a dual metal CMOS technology. This octal latch has
3-state output and is intended for bus-oriented applications. The
flip-flops appear transparent to the data when Latch Enable (LEl is
HIGH. When LE is LOW, the data that meets the set-up times is
latched. Data~pears on the bus when the Output Enable (OEl is
LOW. When OE is HIGH, the bus output is in the high impedance
state.

• 10ns typical data to output delay
• IOL = 14mA over full military temperature range
• CMOS power levels (5J.1W typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5J.1A max.)
• Octal transparent latch with enable
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8

PIN CONFIGURATIONS
o
fa 0 "
ooo:J;o

INDEX
N
00
Do
D1
°1
°2
D2
D3
03
GND

Vee

LJU::UU

°7
D7
D6
06
Os
Ds
D4
04
LE

D1
01
O2
D2
D3

3 2 LJ 20 19
1
18[ D7
]s
17[: D6
16 [: 0 6
]6
L20-2
]7
IS[ Os
14[ Ds
]8

:J 4

~~~~~

II!

o~~oo
(!J

LCC
TOP VIEW

DIP/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Do

D1

D2

D3

D4

Ds

06

D7

CEMOS is a trademark of Integrated Device Technology. Inc.
MILITARY TEMPERATURE RANGE
1987 Integrated Device Technology. Inc.

DECEMBER 1987

©

OSC-4049/-

10-245

IDT54AHCT373 HIGH-SPEED
CMOS OCTAL TRANSPARENT LATCH

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
. Terminal Voltage with Respect
toGND

MILITARY TEMPERATURE RANGE

CAPAcITANCE

(1)

(TA= +25°C. f = 1.0MHz)

VALUE

UNIT

-0.5 to +7.0

V

CIN

Input Capacitance

COUT

Output Capacitance

TA

Operating Temperature

-55 to + 125

°C

TBIAS

Temperature Under Bias

-65 to +135

°C

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

loUT

DC Output Current

120

mA

SYMBOL

PARAMETER(1)

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vcc = 5.0V ± 10%
VLC = 0.2V
VHC = Vcc - 0.2V
SYMBOL

TEST CONDITIONS (1)

MIN.

TYP.!21

MAX.

UNIT

"'H
VIL

Input HIGH Level

PARAMETER

Guaranteed Logic High Level

2.0

-

V

Input LOW Level

Guaranteed Logic Low Level

0.8

V

IIH

Input HIGH Current

Vcc = Max., "'N = Vce

-

-

5.0

J.lA

IlL

Input LOW Current

Vcc = Max.• VIN = GND

-

-5.0

J.lA

Isc

Short Circuit Current

Vcc = Max. (3)

-60

-100

-

rrA

Vcc = 3V. VIN = VLC or VHC ' 10H = -32IJA

VHC

Vcc

-

rrA

VHC
2.4

Vcc
4.3

-

V

GND

VLC

GND

VLC
0.4

VOH

Output HIGH Voltage

Vcc = 3V. ~N
VOL

Output LOW Voltage

I
I

Vcc = Min.
"'N = VIHor"'L
=

Vt.c

IoH = -150iJA
10H = -1.0mA

or~C.IOL = 300IJA

I
I

Vcc = Min.
VIN = VIH or "'L

10L = 300J.lA
10L = 14mA

-

-

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-246

V

JDT54AHCT373 HIGH-SPEED
CMOS OCTAL TRANSPARENT LATCH

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC

= 0 2V' VHC = VCC -

SYMBOL

0.2V

ICCQ

Quiescent Power Supply Current

Vco = Max.
\'IN ~ VHC : \'IN ~ VLC
fl = 0

IcoT

Power Supply Current Per TIL
Inputs HIGH

Vcc
\'IN

Dynamic Power Supply Current (5)

Vcc = Max.
Outputs Open
OE = GND
LE = Vcc
One Input Toggling
50% Duty Cycle

loco

Icc

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

VIN ~ VHC
VIN ~ VLC

-

0.15

0.25

rnA/MHz

VIN ~ VHC
VIN ~ VLC (AHCT)

-

0.15

1.8

-

0.4

2.8

(1)

= Max.
= 3.4V(3)

VCC = Max.
Outputs Open
fl = 1.0MHz,
50% Duty Cycle
OE = GND
LE = Vcc
One Bit Toggling
Total Power Supply Current (4)

MIN.

TEST CONDITIONS

PARAMETER

Vcc = Max.
Outputs Open
fl = 250kHz
50% Duty Cycle
OE = GND
LE = Vcc
Eight Bits Toggling

\'IN

= 3.4V
or

\'IN

= GND
rnA

\'IN ~ VHC
\'IN ~ VLC (AHCT) (6)
\'IN

= 3.4v(6)
or

\'IN

= GND

-

0.3

2.0

-

2.3

10.0

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (\'IN = 3.4V): all other inputs at Vcc or GND.
4. Icc = IQUIESCENT + IINPUTS + IDYNAMIC
Icc = IcoQ + IcoT DH NT + ICCD (fcp/2 + fl N I)
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = ClockFrequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-247

m

IDT54AHCT373 HIGH-SPEED
CMOS OCTAL TRANSPARENT LATCH

MILITARY TEMPERATURE RANGE

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

DESCRIPTION

Do - 0 7
LE
OE

00

-

07

OUTPUTS

INPUTS

Data Inputs
Latch Enables Input (Active HIGH)
Output Enables Input (Active LOW)
3-State Latch Outputs
H =
L =
X =
Z=

On

LE

OE

On

H
L
X

H
H
X

L
L
H

H
L

Z

HIGH Voltage Level
LOW Voltage Level
Don't Care
HIGH Impedance

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

CONDITION(l)

TYP.

MIN.(2)

MAX.

UNIT

tpLH
tpHL

Propagation Delay
On to On

10.0

1.5

19.0

ns

tZH
tZL

Output Enable
Time

15.0

1.5

24.0

ns

tHZ
tLZ

Output Disable
Time

9.0

1.5

16.0

ns

tpLH
tpHL

Propagation Delay
LE to On

20.0

2.0

27.0

ns

4.0

10.0

-

ns

CL = 50pF
RL = 5000

ts

Set-up Time
HIGH or LOW
On to LE

tH

Hold Time
HIGH or LOW
On to LE

3.0

1.5

-

ns

tw

LE Pulse Width
HIGH or LOW

7.0

10.0

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAH CT
Temp. Range

XXXX
Device Type

X
Process

I

10-248

IB

MIL-STD-883, Class B

D
L
E

CERDIP
Leadless Chip Carrier
CERPACK

373

Octal Transparent Latch

54

-55°C to

+ 125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 10ns typical address to output delay
• IOL = 14mA over full military temperature range
• CMOS power levels (SJjW typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than ALS (SJjA max.)

The IDTS4AHCT374 are 8-bit registers built using advanced
CEMOS T~ a dual metal CMOS technology. These registers consist of eight D-type flip-flops with a buffered common clock and
buffered 3-state output control. When the output enable (0 E) input
is LOW. the eight outputs are enabled. When the OE input is HI GH.
the outputs are in the three-state conditions.
Input data meeting the set-up and hold ti me requirements of the
D inputs is transferred to the 0 outputs on the LOW-to-HIGH transition of the clock input.

• Octal D register (3-state)
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883. Class 8

PIN CONFIGURATIONS
a

0Fo

0

OOO~O

INDEX

'"

"-'

3
D1

]4

0 1 :J

5

:J

a

O2

I

L..J

I

I

It'

I

L...J

t-...

I

I

L...J

2 U 20 19
1
la[

L20-2

D7

17£:

Da

la[

Oa

D2

]7

15 [:

05

D3

:J

14 [:

D5

a
9

10 11 12 13

nnnnn

0

0
z E5

0

o~

(!l

LCC
TOP VIEW

DIP/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM

CP
CLOCK

OE
OUTPUT
ENABLE

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated DevIce Technology. Inc.

DSC-40501-

10-249

IDT54AHCT374 HIGH-SPEED CMOS
OCTAL D REGISTER (3-STATE)

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage with Respect
toGND
Operating Temperature

TA

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

VALUE

UNIT

SYMBOL

-0.5 to +7.0

V

-55 to +125

°C

CIN
COUT

TBIAS

Temperature Under Bias

-65 to +135

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)
Input Capacitance
Output Capacitance

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

°C

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation 6f the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vcc = 5.0V ± 10% (Military)
VLC = 0.2V
VHC = Vcc - 0.2V
MIN.

TYPJ2)

MAX.

UNIT

\'IH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

V

\'IL

Input LOW Level

Guaranteed Logic Low Level

0.8

V

IIH

Input HIGH Current

Vcc = Max., \'IN = Vcc

-

-

5

j.JA

SYMBOL

TEST CONDITIONS (1)

PARAMETER

-

-

-5

j.JA

-60

120

-

mA

= VLC or VHC ,IoH = -32j.JA

VHC

Vcc

-

I 10H

= -150j.JA

VHC

Vcc

-

= -1.0mA

2.4

4.3

-

-

GND

VLC

GND

VLC
0.4

IlL

Input LOW Current

Vcc = Max., VIN = GND

Isc

Short Circuit Current

Vcc

VOH

Output HIGH Voltage

= Max. (3)
Vcc = 3V, VIN
Vcc = Min.

I 10H

\'IN = \'IH orVIL

Vcc = 3V, \'IN = VLC or VHC , 10L
VOL

Output LOW Voltage

I IOL

Vcc = Min.
\'IN = \'IH or\'lL

L IoL

= 300j.JA
= 300j.JA
= 14mA

-

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-250

V

V

---------------'

---------------------JDT54AHCT374 HIGH-SPEED CMOS
.oCTAL D REGISTER (3-STATE)

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; ~c = Vcc - 0.2V
SYMBOL

TEST CONDITIONS

PARAMETER

MIN.

(1)

TYP,I2)

MAX.

UNIT

ICCQ

Quiescent Power Supply Current

Vcc = Max.
VIN ;::VHC ; "IN '!S VLC
fcp'= fl = 0

-

0.001

1.5

mA

ICCT

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
VIN = 3.4V(3)

-

0.5

2.0

mA

ICCD

5
Dynamic Power Supply Currenl )

Vcc= Max.
Outputs Open
BE = GND
One Bit Toggling
50% DUty Cycle

ViN ;:: VHC
ViN '!S VLC

-

0.15

0.25

mAl

ViN ;:: VHC
ViN '!S VLC
(AHCT)

-

0.15

1.8

V IN = 3.4Vor
ViN = GND

-

0.65

3.8

Icc

Vcc = Max.
Outputs Open
fcp = 1.0MHz
§Q% Duty Cycle
DE = GND
One Bit Toggling
at f I = 500kHz
50% DUty Cycle
Total Power Supply Current

mA

(4)

Vcc = Max.
Outputs Open
fcp = 1.0MHz
§Q% Duty Cycle
DE = GND
Eight Bits Toggling
at f I = 250kHz
50% Duty Cycle

ViN ;:: VHC
ViN '!S VLC
(AHCT)

(6)

VIN = 3.4V or
ViN = GND

(6)

-

0.63

2.2

-

2.88

11.2

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. Icc = IQUIESCENT + IINPUTS + IDYNAMIC
ICC = lceo + ICCT DH NT + ICCD (fcp/2 :f- fl N I)
Icco = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
IceD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-251

MHz

IDT54AHCT374 HIGH-SPEED CMOS
OCTAL 0 REGISTER (3-STATE)

MILITARY TEMPERATURE RANGE

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION

PIN NAMES

INPUTS
FUNCTION

D,

The D flip-flop data inputs.

CP

Clock Pulse for the register. Enters data on the
LOW-to-HIGH transition.

0,

The register three-state outputs.

BE

Output Control. An active-LOW three-state control
used to enable the outputs. A HIGH level input
forces the outputs to the high impedance (off)
state.

OUTPUTS INTERNAL

OE

CLOCK

0,

0,

0,

Hi-Z

H
H

L
H

X
X

Z
Z

NC
NC

LOAD
REGISTER

L
L
H
H

-?
-?
-?

L
H
L
H

L
H
Z
Z

L
H
L
H

-.r

H
L
X
Z

HIGH
LOW
Don't Care
High Impedance
.Jf;: LOW-to-HIGH transition
NO = No Change

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
CONDITION(1)

MIN.(2)

MAX.

UNIT

2.0

18.0

ns

11.0

1.5

20.0

ns

9.0

1.5

24.0

ns

2.0

10.0

-

ns

Hold Time
HIGH or LOW
DN to CP

0.5

1.5

-

ns

CP Pulse Width
HIGH or LOW

10.0

16.5

-

ns

SYMBOL

PARAMETER

TYP.

tpLH
t pHL

Propagation Delay
CPto On

10.0

tZH
tZL

Output Enable Time

tHZ
tLZ

Output Disable Time

ts

Set-upTime
HIGH or LOW
DN to CP

tH

tw

CL = 50pF
RL = 500n

NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX

X

Device Type

Process

----II B

, - - - I

D

'------------1 L

E
' - - - - - - - - - - - - - - - - - \ 374
1---------~------------I54

-...

--------

----------_ ..

10-252

MIL-STD-883, Class B
CERDIP
Leadless Chip Carrier
CERPACK
Octal D Register (3-State)
-55°C to +125°C

.........

_

--_..__

.•.

------

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes

The IDT54AHCT377 is an octal D flip-flop built using advanced
CEMOS T~ a dual metal CMOS technology. The IDT54AHCT377
has eight edge-triggered, D-type flip-flops with individual D inputs
and 0 outputs. The common buffered Clock (CPlJ.nput loads all
flip-flops simultaneously when the Clock Enable (CE) is LOW. The
register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to
the corresponding flip-flop's 0 output. The CE input must be stable
only one set-up time prior to the LOW-to-HIGH clock transition for
predictable operation.

• 10ns typical propagation delay
• IOL = 14mA over full military temperature range
• CMOS power levels (5J.lW typo static)
• Both CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5J.lA max.)
• Octal D flip-flop with clock enable
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class B

PIN CONFIGURATIONS
CE
00

Vcc

Do
Dl
01
O2
D2
D3
03
GND

D7
D6
06

od'~~6'

INDEX

07
Dl

L..: U I; U U
3 2 LJ 20 19
1
16 [:
]4

17e

0 1 ]5

05

Oz

DS
D4
04
CP

D2
D3

]6
]7
]6

D7
D6

16C 0 6
lSC 05
14C DS

L20-2

m

9 10 11 12 13

nnnnn
o §i) 5 oVaV
(!]

DIP/CERPACK
TOP VIEW

LCC
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Do

Dl

D2

D3

D4

Ds

D6

D7

CEMOS is a trademark of Integrated Device Technology, Inc.

DECEMBER 1987

MILITARY TEMPERATURE RANGE
© 1987 Integrated Device Technology, Inc.

DSC-40S1/-

10-253

IDT54AHCT377 HIGH·SPEED CMOS OCTAL
D FLlp·FLOP WITH CLOCK ENABLE

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

RATING

VALUE

UNIT

Terminal Voltage with Respect
toGND

-0.5 to +7.0

V

CIN

·Input Capacitance

COUT

Output Capacitance

TA

Operating Temperature

-55 to +125

°C

TBIAS

Temperature Under Bias

-65 to + 135

°C

TSTG

Storage Temperature

-65 to + 150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

SYMBOL

CONDITIONS TYP.

MAX. UNIT

VIN = OV

6

10

pF

Vour= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
INGS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification Is not implied. Exposure to absolute maximum rating con~
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vcc = 5.0V ± 10%
VLC = 0.2V
VHC = Vcc - O.2V
TEST CONDITIONS (1)

MAX.

UNIT

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic Low Level

-

V

IIH

Input HIGH Current

Vce = Max',"'N = Vce

-

0.8

jJA

IlL

Input LOW Current

Vcc = Max., VIN = GND

-

-

5.0
-5.0

jJA

Short Circuit Current

Vce = MaxP)

-60

-:-100

-

tnI\

Vec = 3V, VIN = VLe or VHe , 10H = -32 JlA

VHC
VHC

Vee

-

tnI\

2.4

4.3

-

V

Ise
VOH

PARAMETER

Output HIGH Voltage

I

Vee = Min.
"'N = VIH or"'L

I

10H = -1501JA
10H = -1.0mA

Vce = 3V, VIN = VLC or \l-ic, 10L = 300 JlA
VOL

Output LOW Voltage

I
I

Vcc = Min.
VIN = VIH orVIL

10L = 300)JA
10L = 14mA

MIN.

TYP,(2)

VIH

SYMBOL

Vec

-

GND

VLC

-

GND

VLC
0.4

-

-

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-254

V

JDT54AHCT377 HIGH-SPEED CMOS OCTAL
D FLIP-FLOP WITH CLOCK ENABLE

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; '4tc = Vco - 0.2V
SYMBOL

ICCQ

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC ; \IN
fcp = fl = 0

I COT

Quiescent Power Supply Current
TTL Inputs HIGH

VCC = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Current(S)

Vcc= Max.
Outputs Open
CE = GND
One Bit Toggling
50% Duty Cycle

Icc

s

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

VJN ~ VHC
VJN S VLC

-

0.15

0.25

mAl
MHz

VIN ~ VHC
VJN :S VLC
(AHCT)

-

0.15

1.8

V IN = 3.4Vor
VJN = GND

-

0.65

3.8

MIN.

(1)

VLC

Vcc = Max.
Outputs Open
fcp = 10MHz
§Q% Duty Cycle
CE = GND
One Bit Toggling
at f I = 500kHz
50% Duty Cycle
Total Power Supply Current

TYP.(2)

TEST CONDITIONS

PARAMETER

mA

(4)

Vcc = Max.
Outputs Open
fcp = 1.0MHz
§Q% Duty Cycle
CE = GND
Eight Bits Toggling
at f I = 250kHz
50% Duty Cycle

VJN ~ VHC
VJN S VLC
(AHCT)

(6)

VIN = 3.4V or
VIN = GND

(6)

-

0.63

2.2

-

2.88

11.2

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. lco = IQUIESCENT + 'INPUTS + IDYNAMIC
Icc = ICCQ + ICCT DH NT + ICCD (fcp/2 + fl N d
ICCQ = Quiescent Current
ICOT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL inputs at DH
ICOD = Dynamic Current caused by an input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-255

UNIT

IDT54AHCT377 HIGH-SPEED CMOS OCTAL
o FLIP-FLOP WITH CLOCK ENABLE

MIUTARYTEMPERATURERANGE

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

,

DESCRIPTION

INPUTS

OPERATING MODE

0 0 -0 7

Data Inputs

CE

Clock Enable (Active LOW)

Load "1"

0 0 -0 7

Data Outputs

Load ·0"

CP

Clock Pulse Input
Hold (Do Nothing)

OUTPUTS
0

0

CP

CE

t
t
t

I

h

I

I

L

h
H

X
X

No Change
No Change

X

H

H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
L = LOW Voltage Level
= LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock
Transition
X = Immaterial

t

= LOW-to-HIGH Clock Transition

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL
tpLH
t PHL

PARAMETER

CONDITION(1)

Propagation Delay
CPto~

TYP.

MIN}2)

MAX.

10.0

2.0

20.0

ns

5.0

2.0

-

ns

2.0

1.5

-

ns

3.0

2.0

-

ns

UNIT

ts

Set-upTime
HIGH or LOW
ON to CP

tH

Hold Time
HIGH or LOW
ON to CP

ts

Set-upTime
HIGH or LOW
BE to CP

tH

Hold Time
HIGH or LOW
BE to CP

2.0

2.0

-

ns

tw

Clock Pulse Width, LOW

7.0

7.0

-

ns

CL = 50pF
RL = 5000

NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX

X

Device Type

Process

'<-------II
'------------i
'----------------i

CERDIP
Leadless Chip Carrier
CERPACK

521

8-Bit Identity Comparator

'----------------------154

10-256

MIL-STD-883, Class B

B
D
L
E

-55°C to +125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full temperature
and voltage supply extremes
• 9ns typical propagation delay
• IOL = 14mA over full military temperature range
• CMOS power levels (SJJW typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than ALS (SJJA max.)
• 8-bit identity comparator
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8

The IDTS4AHCTS21 is an 8-bit identity comparator built using
advanced CEMOS TM, a dual metal CMOS technology. The device
compares two words of up to eight bits each and provides a LOW
output when the two words match bit for bit. The expansion input
TA = B also serves as an active LOW enable input.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

IA= B

Vcc

Ao
Bo
Al
Bl
A2
B2
A3
B3

°A=B
B7
A7
B6
A6
Bs
As
B4
A4

GND
DIP/CERPACK
TOP VIEW

Ao
Bo
Al
Bl
A2
B2
A3
B3
A4
B4
As
Bs

INDEX

Al
Bl
A2
B2
A3

:J
:J
:J
:J
:J

~

L....I

3

2

II

L.....I

4

S
6

......

LJ 20 19

L20-2

7
8

18 [: B7
17 [: A7
16 r: B6
IS r: A6
14[ Bs

A6
. B6
A7
B7
IA= B

-1>N
-1>N
-1>N
-1>N
-1>N
-1>N
-1>N
-1>N

°A=B

lCC
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE
©

DECEMBER 1987

1987 Integrated Device Technology, Inc.

OSC-4052/-

10-257

1m

IDT54AHCT521 HIGH-SPEED
CMOS 8-BIT IDENTITY COMPARATOR

ABSOLUTE MAXIMUM RATINGS

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

. RATING

VALUE

UNIT

VTERM

Terminal Voltage with Respect
toGND

-0.5 to +7.0

V

CIN

Input Capacitance

TA

Operating Temperature

-55 to +125

°C

COUT

Output Capacitance

SYMBOL

TBIAS

Temperature Under Bias

-65 to + 135

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5.

W

lOUT

DC Output Current

120

mA

SYMBOL

MAX. UNIT

CONDITIONS TYP.
VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

°C

NOTE:
1. Stresses greater than those lIsted under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implIed. Exposure to absolute maximum rating conditions for extended periods may affect relIability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vcc = 5.0V ± 10%
VLC = 0.2V
VHC = Vee - 0.2V
MIN.

Typ.(2)

MAX.

UNIT

VIH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

V

VIL

Input LOW Level

Guaranteed Logic Low Level

IIH

Input HIGH Current

Vcc = Max.,VIN = Vcc

-

SYMBOL

TEST CONDITIONS (1)

PARAMETER

IlL

Input LOW Current

Vcc = Max., VIN = GND

Isc

Short Circuit Current.

Vcc = Max. (3)

VOH

Output HIGH Voltage

Output LOW Voltage

-5

~A

-60

120

-

mA

V

0.8

V

5

~A

VHC

Vcc

= -300~A

VHC

Vcc

-

= -12mA

2.4

4.3

-

Vcc = 3V. \'IN = VLC orVHC , 10L = 300~A

-

GND

VLC

= 300~A

-

GND

IoL = 14mA

-

-

VLC
0.4

Vcc = 3V, VIN "" VLC or VHC ,IOH = -32~A

VOL

-

-

I 10H

Vcc = Min.
VIN = VIH or \'IL

I 10H

I 10L

Vcc = Min.
VIN = VIH or VIL

I

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-258

V

--------------------

.-.. ~-~----.--.

_._-_..........- - - - - - - - - - - - -

IDT54AHCT521 HIGH·SPEED
CMOS 8·BIT IDENTITY COMPARATOR

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = Vcc - 0.2V
SYMBOL

Icco

Quiescent Power Supply Current

Vcc = Max.
\'IN ~ VHC ; \'IN :5 VLC
fl = 0

ICCT

Power Supply Current Per TTL
Inputs HIGH

Vcc
\'IN

ICCD

Dynamic Power Supply Current (5)

Vcc
Output Open
One Input Toggling
50% DUty Cycle

Total Power Supply Current (4)

Vcc = Max.
Output Open
fl = 1.0MHz.
50% Duty Cycle
On 8it Toggling

Icc

TYP.(2)

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

\'IN ~ VHC
\'IN :5 VLC

-

0.15

0.25

mA/MHz

\'IN ~ VHC
\'IN :5 VLC (AHCT)

-

0.15

1.8

= 3.4V or
= GND

-

0.4

TEST CONDITIONS

PARAMETER

= Max.
= 3.4W)
= Max.

\'IN
\'IN

MIN.

(1)

UNIT

mA
2.8

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. Icc = 'OUIESCENT + 'INPUTS + IDYNAMIC
Icc = ICCQ + ICCT DH NT + ICCD (fcp/2 + fiN I)
Icco = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable. but is derived for use in Total Power Supply calculations.

'1

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
Ao -A7
~ -8 7

IA = B
tiA = B

TRUTH TABLE
INPUTS

DESCRIPTION
Word A Inputs
Word 8 Inputs
Expansion or Enable Input (Active LOW)
Identity Output (Active LOW)

OUTPUT

'A = B

A,B

0A= B

L
L
H
H

A = 8*
A 1- 8
A = 8*
A'" 8

L
H
H
H

H = HIGH Voltage Level
L = LOW Voltage Level
*Ao = 8 0 • Al

= B1 • A2 = B2 . etc.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

tpLH
tpHL

Propagation Delay
AN or 8 N to C)A = B

tpLH
tpHL

Propagation Delay
'A = B to 0A = B

CONDITION(l)

TYP.

CL = 50pF
RL =

MIN.(2)

MAX.

UNIT

9.0

-

17.0

ns

5.0

-

11.0

ns

soon

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

10-259

1m

IDT54AHCT521 HIGH-SPEED
CMOS 8-BIT IDENTITY COMPARATOR

MILITARY TEMPERATURE RANGE

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX
Device Type

x
Process

I

IB

MIL-STD-883. Class B

D
L
E

CERDIP
Leadless Chip Carrier
CERPACK

521

8-Bit Identity Comparator

54

-55°C to + 125°C

10-260

------

--.---~-

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full temperature
and voltage supply extremes

The IDT54AHCT533 are octal transparent latches built using advanced CEMOS ™ I a dual metal CMOS technology. The
IDT54AHCT533 consists of eight latches with 3-state outputs for
bus organized system applications. The flip-flops appeartransparent to the data when Latch Enable (LE) is HIGH. When LE is LOW,
the data that meets the set-up times is latched. Dat~pears on the
bus when the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high impedance state.

• 11ns typical clock to output
• 10L = 14mA over full military temperature range
• CMOS power levels (5jJW typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5J.1A max.)
• Octal transparent latch with 3-state output
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8

PIN CONFIGURATIONS
~

Vee

00

0

Do

D7

D,

06

0,

3

0,

0 , :J

O2

]6

O2

]7

D3

:J

D4

03

04

GNO

,..."

20 19

1

18

5

06
05
D5

U

2

]4

O2
D2

0

u;; u u

U

7

03

0fo

a

oIOO~IO

INDEX

L20-2

r:

06

le[

06
05

15 [:
14C

8
9

10 11

D7

17 [:

05

12 13

nnnnn
IO@~IOC

LE

1m

t!:l

LCC
TOP VIEW

DIP/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Do

D,

D2

04

03

D5

D6

07

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated DevIce Technology, Inc.

OSC-4053/-

10-261

JDT54AHCT533 HIGH-SPEED CMOS
OCTAL TRANSPARENT LATCH (3-STATE)

ABSOLUTE MAXIMUM RATINGS

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

(TA= +25°C, f = 1.0MHz)

RATING

VALUE

UNIT

VTERM

Terminal Voltage with Respect
toGND

-0.5 to + 7.0

V

CIN

Input Capacitance

TA

Operating Temperature

-55 to +125

°C

C OUT

Output Capacitance

TBIAS

Temperature Under Bias

-65 to +135

°C

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

SYMBOL

SYMBOL

PARAMETER(l)

CONDITIONS TYP.

UNIT

MAX.

VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vcc = 5.0V ± 10%
VLC = O.2V
VHC = Vee - O.2V
MIN.

TYP,(l)

MAX.

UNIT

VIH

Input HIGH Level

Guaranteed Logic High Level

2.0

-

V

"'IL

Input LOW Level

Guaranteed Logic Low Level

-

0.8

V

IIH

Input HIGH Current

Vee = Max., "'IN =

-

-

5

~A

IlL

Input LOW Current

Vee

-

-5

~A

SYMBOL

loz
Ise

TEST CONDITIONS (1)

PARAMETER

= Max., "'IN

Off State (High Impedance)
Output Current

Vee = Max.

Short Circuit Current

Vee = Max. (3)
Vee = 3V, "'IN

VOH

Output HIGH Voltage

Output LOW Voltage

= GND

l Vo = Vee
I Vo = GND
= VLC

or VHe ,IoH
llOH

Vee = Min.
"'IN = VrH or VIL
Vee

VOL

Vee

I 10H

= 3V, "'IN = VLe

or VHe ,IoL

I 10L

Vee = Min.
VIN = "'IH or"'lL

llOl

= -32).1A
= -150).lA
== -1.0mA

= 300).lA
= 300).lA
= 14mA

-

-

-10

-60

~A

-100

-

VHe

Vce

-

VHe
2.4

Vce
4.3

-

-

GND

VLe

GNO

-

-

VLe
0.4

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics for the applicable device type .
. 2. Typical values are at Vee == 5.0V, + 25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-262

10

mA

V

V

- - - - - - - - - - - - - - - - -------IDT54AHCT533 HIGH·SPEED CMOS
OCTAL TRANSPARENT LATCH (3.STATE)

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
vLC = 0.2V; VHC = vcc - 0.2V
SYMBOL

PARAMETER

TYP.(2)

MAX.

UNIT

-

0.001

1.5

rnA

-

0.5

2.0

rnA

\'IN ~ VHC
\'IN S VLC

-

0.15

0.25

rnA/MHz

VIN ~ VHC
\'IN S VLC (AHCT)

-

0.15

1.8

\'IN = 3.4V
or
VIN = GND

-

0.4

2.8

TEST CONDITIONS (1)

MIN.

~

ICCQ

Quiescent Power Supply Current

Vcc = Max.
\'IN ~ VHC ; \'IN S VLC
fl = 0

ICCT

Power Supply Current Per TTL
Inputs HIGH

Vcc = Max.
\'IN = 3.4V(3)

Dynamic Power Supply Current (5)

Vcc = Max.
Outputs Open
OE = GND
LE = Vee
One Input Toggling
50% Duty Cycle

ICCD

VCC = Max.
Outputs Open
fl = 1.0MHz,
50% Duty Cycle
OE = GND
LE = VCC
One Bit Toggling
Icc

Total Power Supply Current (4)

rnA
Vcc = Max.
Outputs Open
fl = 250kHz
50% Duty Cycle
OE = GND
LE = VCC
Eight Bits Toggling

\'IN ~ VHC
\'IN S VLC (AHCT)(6)

-

0.3

2.0

\'IN = 3.4V(6)
or
\'IN = GND

-

2.3

10.0

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. Icc = IQUIESCENT + IINPUTS + IDYNAMIC
lee = ICCQ + ICCT DH NT + ICCD (fcp/2 + fl N I )
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fcp = ClockFrequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-263

m

IDT54AHCT533 HIGH-SPEED CMOS
OCTAL TRANSPARENT LATCH (3-STATE)

. MILITARY TEMPERATURE RANGE

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

00 - 0 7

OUTPUTS

INPUTS

Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary 3-State Outputs

Do - 0 7
LE
OE

DN

LE

OE

ON

H
L
X

H
H
X

L
L
H

L
H
Z

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = HIGH Impedance

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
CONDITION(1)

TYP.

MIN.(2)

MAX.

UNIT

tplH
tpHl

Propagation Delay
Dn to On

11.0

1.5

24.0

ns

tZH
tZl

Output Enable
Time

15.0

1.5

20.0

ns

tHZ
tLZ

Output Disable
Time

11.0

1.5

22.0

ns

tplH
tpHl

Propagation Delay
LE to ON

15.0

2.0

28.0

ns

7.0

15.0

-

ns

SYMBOL

PARAMETER

Cl = 50pF
Rl = 5000

ts

Set-upTime
HIGH or LOW
Dn to LE

tH

Hold Time
HIGH or LOW
Dn to lE

5.0

1.5

-

ns

tw

lE Pulse Width
HIGH or LOW

7.0

15.0

-

ns

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX
Device Type

X
Process

---II

B

MIL-STD-883, Class B

'-------------1

D
L
E

CERDIP
Leadless Chip Carrier
CERPACK

<---I

'---------------------l
L-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

10-264

533

Octal Transparent Latch (3-state)

54

-55°C to +125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full temperature
and voltage supply extremes

The IDT54AHCT534 are high-speed, low-power octal D-type
flip-flops featuring separate D-type inputs for each flip-flop and
3-state outputs for bus-oriented applications. A buffered Clock
(CP) and Output Enable (OE) are common to all flip-flops.
They are built using IDT's advanced CEMOS TM, a dual metal
CMOS technology.

•
•
•
•
•
•
•
•

10ns typical clock to output
IOL = 14mA over full military temperature range
CMOS power levels (5~W typo static)
80th CMOS and TIL output compatible
Substantially lower input current levels than ALS (5~A max.)
Octal D flip-flop with 3-state output
JEDEC standard pinout for DIP and LCC
Military product compliant to MIL-STD-883, Class 8

PIN CONFIGURATIONS

a/0ofo0 ~ /0

INDEX

C5E

VCC
07
D7
D6
06
05
D5
D4
0 4
CP

00
Do
D,
0,

O2
D2
D3
03
GND

0

o
I

I

I

I

L..I.......,

3

D,
0,

]4
]5

O2 :J 6
D2 ]7
D3 ]8

I

I

I

I

I

I

L..I

,....,

I

I

L..I

2 U 20 19
1
18 [:
17[:
16[:
L20-2
15 r:
14 c:

9 10 11 12 13

D7
D6
06
05
D5

nnr.nn

/0

~

& /0'

m

O>q

C!J

LCe
TOP VIEW

DIP/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Do

D,

D2

D3

D4

D5

D6

D7

CP

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated Device Technology. Inc.

OSC-4054/10-265

IDT54AHCT534 HIGH-SPEED
CMOS OCTAL D FLIP-FLOP (3-STATE)

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING'
Terminal Voltage with Respect
toGND

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

VALUE

UNIT

-0.5 to +7.0

V

TA

Operating Temperature

-55 to +125

°C

TBIAS

Temperature Under Bias

-65 to +135

°C

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

SYMBOL
CIN

(TA= +25°C. f = 1.0MHz)

PARAMETER(l)
Input Capacitance

MAX. UNIT

CONDITIONS TYP.
VIN = OV

6

10

pF

pF
Output Capacitance
8
12
COUT
VOUT= OV
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vcc = 5.0V ± 10%
VlC = 0.2V
VHC = Vcc - O.2V
SYMBOL

TEST CONDITIONS(1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

-

V

0.8

V

5

~A

~A

\.IH

Input HIGH Level

Guaranteed Logic High Level

2.0

\.Il

Input LOW Level

Guaranteed logic Low Level

-

-

IIH

Input HIGH Current

Vcc = Max.• \.IN = Vcc

-

-

III

Input LOW Current

Vcc = Max .• \.IN = GND

-

-

-5

-

10

-

-

-10

loz
Isc

VOH

I Vo = Vcc
I Vo = GND

Off State (High Impedance)
Output Current

Vcc = Max.

Short Circuit Current

Vcc = Max.(3)

-60

-120

Vcc = 3V. \.IN = VlC or VHC .loH = -32~A

VHC

VCC

VHC
2.4

Vcc

-

4.3

-

Output HIGH Voltage

l'oH = -150~A

VCC = Min.
\.IN = \.IH or \.Il

.l'oH = -1.0mA

-

GND

VlC

I IOl = 300~A

-

GND

t'ol= 14mA

-

-

Vle
0.4

Vcc = 3V. \.IN = VlC or VHC .Iol = 300~A
VOL

Output LOW Voltage

Vcc = Min.
\.IN = \.IH orVll

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-266

~A

mA

V

V

IDT54AHCT534 HIGH·SPEED
CMOS OCTAL D FLlp·FLOP (3·STATE)

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS

vLC = O.IN· vHC = Vcc - O.IN
SYMBOL

lceo

Quiescent Power Supply Current

Vcc = Max.
'-"N ~ VHC : '-"N S VLC
fcp = fl = 0

IOCT

Power Supply Current Per TTL
Inputs HIGH'

Vcc
'-"N

Dynamic Power Supply Current (5)

Vcc
Outputs Open
OE = GND
One Bit Toggling
50% Duty Cycle

Icco

Icc

Total Power Supply Current (4)

TYP.(2)

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

'-"N ;=: VHC
'-"N S VLC

-

0.15

0.25

mA/MHz

'-"N ~ VHC
'-"N S VLC (AHCT)

-

0.15

1.8

-

0.65

3.8

= Max.
= 3.4V(4)
= Max.

Vcc = Max.
Outputs Open
fcp = 1.0MHz.
50% Duty Cycle
OE = GND
One Bit Toggling
at f I = 500kHz
50% Duty Cycle

'"

MIN.

TEST CONDITIONS(1)

PARAMETER

VCC = Max.
Outputs Open
fcp = 1.0MHz.
50% Duty Cycle
OE = GND
Eight Bits Toggling
atf I = 250kHz
50% DUty Cycle

'-"N

= 3.4V
or

'-"N

= GND

mA
'-"N ~ VHC
'-"N S VLC (AHCT) (6)

'-"N

0.63

2.2

-

2.88

11.2

= 3.4V(6)
or

'-"N

-

= GND

NOTES:
1.
2.
3.
4.

For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at Vcc = 5.0V. + 25°C ambient and maximum loading.
Per TTL driven input <"'N = 3.4V): all other inputs at Vcc or GND.
Icc = IQUIESCENT + IINPUTS + IOYNAMIC
Icc = lceo + Iccr DH N r + Icco (fcp/2 + fl N I)
lceo = Quiescent Current
Iccr = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
N r = Number of TTL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = ClockFrequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable. but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-267

UNIT

IDT54AHCT534 HIGH-SPEED
CMOS OCTAL D FLIP-FLOP (3-STATE)

MILITARY TEMPERATURE RANGE

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
DESCRIPTION

PIN NAMES

Do - 0 7
CP
OE

00 - 07

OUTPUTS

INTERNAL

OE

CP

DI

ON

°1

Hi-Z

H
H

L
H

X
X

Z
Z

NC
NC

L
L
H
H

~

LOAD
REGISTER

L
H
L
H

H
L

L
H
L
H

INPUTS

FUNCTION

Data Inputs
Clock Pulse Input (Active Rising Edge)
3-State Output Enable Input (Active LOW)
Complementary 3-State Outputs

--.r--.r--.r-

Z
Z

= HIGH
= LOW
= Don't Care
= High Impedance
~ = LOW-to-HIGH transition
NC = No Change
H
L
X
Z

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

CONDITION(1)

MIN~2)

TYP.

MAX.

UNIT

2.0

18.0

ns

11.0

1.5

20.0

ns

11.0

1.5

16.0

ns

2.0

10.0

-

ns

Hold Time
HIGH or LOW
On to CP

0.5

1.5

-

ns

CP Pulse Width
HIGH or LOW

7.0

16.0

-

ns

tpLH
tpHL

Propagation Delay
CPto On

10.0

tZH
tZL

Output Enable
Time

tHZ
tLZ

Output Disable
Time

ts

Set-upTime
HIGH or LOW
On to CP

tH
tw

CL = 50pF
RL = 500n

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAH CT
Temp. Range

XXXX
Device Type

X

X

Package

Process

11--------;1
'------------1
'------------------1

B

MIL-STO-883, Class B

o
L
E

CERDIP
Leadless Chip Carrier
CERPACK

534

Octal 0 Flip-Flop (3-state)

' - - - - - - - - - - - - - - - - - - - - - ; 54

10-268

-55°C to +125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 10ns typical data to output delay
• IOL = 14mA over full military temperature range
• CMOS power levels (5~W typo static)
• 80th CMOS and TIL output compatible
• Substantially lower input current levels than ALS (5~A max.)
• Octal transparent latch with enable
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8

The IDT54AHCT573 are 8-bit latches built using advanced
CEMOS Tr", a dual metal CMOS technology. These octal latches
have 3-state outputs and are intended for bus-oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up
times are latched. Data a.epears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high
impedance state.

PIN CONFIGURATIONS
~

INDEX
~

Vee

Do
Dl
D2
D3
D4
D5
D6
D7
GND

00

D2 ]4
D3 ]5
D4 ]6
D5 ]7
D6 ]8

°1
O2
03
04
°5
06
07
LE

0lw 8 °

o 0 ° > 0
uu;;uu
3 2 U
1

20

19

L20-2

18C

01

17 [:

O2

16C
15 [:
14 [:

03

04
05

~~fi~~

in)

O~~Oa
(!)

LCC
TOP VIEW

DIP/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM
Do

Dl

D2

D3

D4

D5

D6

D7

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated Device Technology. Inc.

10-269

DSC-4055/-

IDT54AHCT573 HIGH-SPEED CMOS·
OCTAL TRANSPARENT LATCH

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage with Respect
toGND

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

(TA= +25°C. f = 1.0MHz)

PARAMETER(1)

VALUE

UNIT

-0.5 to +7.0

V

CIN

Input Capacitance

COUT

Output Capacitance

TA

Operating Temperature

-55 to +125

°C

TSIAS

Temperature Under Bias

-65 to +135

°C

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

SYMBOL

MAX. UNIT

CONDITIONS TYP.
VIN = OV

6

10

pF

VOUT= OV

8

12

pF

NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vee= 5.0V + 10%
VLC = 0.2V
VHC = Vee - 0.2V
SYMBOL
"'H
"'L

TEST CONDITIONS(1)

PARAMETER
Input HIGH Level

Guaranteed Logic HIGH Level

Input LOW Level

Guaranteed Logic LOW Level

UNIT

-

-

V

-

-

0.8

V

-

5

~A
~A

-

-

-10

Vcc = MaxJ3)

-60

-100

-

mA

Vcc = 3V. '-"N = VLC or VHC.I OH = -32~
IOH = -150~A
Vee = Min.

VHC
VHC

Vcc
Vcc

V

2.4

4.3

-

-

GND

VLC

-

GND

VLC

-

-

0.4

Vcc = Max.• '-"N = Vcc

Input LOW Current

Vcc = Max.• VIN

loz

Off State (High Impedance)
Output Current

Vcc = Max.

Isc

Short Circuit Current

Output HIGH Voltage

-

= GND

I Vo =Vcc
I Vo

= GND

I
J IOH=

VIN = '-"H or '-"L

-1.0mA

Vcc = 3V. '-"N = VLC or VHC • IOL = 300~
Output LOW Voltage

MAX.

-5

Input HIGH Current

VOL

Typ.(2)

2.0

-

IIH
IlL

VOH

MIN.

I

Vcc = Min.
'-"N = '-"HorVIL

IOL = 300~A

I IOL = 14mA

-

NOTES:
1. For conditions shown as max. or min .• use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V. +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-270

10

~A

V

__ _ - - - - - - - _ _ _--_.__

----------------------------------------_.

IDT54AHCT573 HIGH·SPEED CMOS
OCTAL TRANSPARENT LATCH

...

.. ..

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; \1-tc = Vco - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS(1)

Icco

Quiescent Power Supply Current

Vcc = Max.
V,N ;::VHC ; "IN :::; VLC
f, = 0

ICCT

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
V,N = 304V(3)

ICCD

Icc

Dynamic Power Supply Current(S)

Total Power Supply Current(4)

Vco= Max.
Outputs Open
DE = GND
LE = Vec
One Bit Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
f, = 1.0MHz
§Q.% Duty Cycle
OE = GND
LE = Vcc
One Bit Toggling

MIN.

TYP.(2)

MAX.

UNIT

-

0.001

1.5

rnA

-

0.5

2.0

rnA

"IN ;:: VHC
"IN ::; VLC

-

0.15

0.25

mAl
MHz

"IN ;:: VHC
"IN :::; VLC
(AHCT)

-

0.15

1.8

V,N = 304Vor
V,N = GND

-

004

2.8

"IN ;:: VHC
V,N ::; VLC
(AHCT)

-

0.3

2.0

-

2.3

10.0

rnA
Vcc = Max.
Outputs Open
f, = 250kHz
§Q.% Duty Cycle
OE = GND
LE = Vce
Eigpt Bits Toggling

V,N
V,N

(6)

= 304V or (6)
= GND

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vco = 5.0V, +25°C ambient and maximum loading.
3. Per TTL driven input (V,N = 304V); all other inputs at Vco or GND.
4. lco = IQUIESCENT + I'NPUTS + IDYNAMIC
Icc = IcoQ + ICCT DH NT + ICCD (fcp/2 + f, N I)
Icco = Quiescent Current
IcoT = Power Supply Current for a TIL High Input (V,N = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL inputs at DH
loco = Dynamic Current caused by an input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
f, = Input Frequency
N I = Number of inputs at f,
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-271

.

IDT54AHCT573 HIGH-SPEED CMOS
OCTAL TRANSPARENT LATCH

MILITARY TEMPERATURE RANGE

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

DESCRIPTION

OUTPUTS

INPUTS

0 0 -0 7

Data Inputs

On

LE

OE

On

LE

Latch Enables Input (Active HIGH)

H

H

L

H

DE

Output Enables Input (Active LOW)

L

H

L

L

0 0 -0 7

3-State Latch Outputs

X

X

H

Z

H
L
X
Z

HIGH Voltage Level
LOW Voltage Level
Don't Care
High Impedance

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

TYP.

MIN.(2)

MAX.

UNIT

tpLH
tPHL

Propagation Delay
ON to ON

10.0

1.5

15.0

ns

tZH
tZL

Output Enable
Time

15.0

1.5

21.0

ns

tHZ
tLZ

Output Disable
Time

9.0

1.5

15.0

ns

t pLH
tpHL

Propagation Delay
LE to ON

CONDITION(1)

CL = 50pF
RL = 5000

20.0

2.0

27.0

ns

ts

Set Up Time
HIGH or LOW
ON to LE

4.0

2.0

-

ns

tH

Hold Time
HIGH or LOW
ON to LE

3.0

1.8

-

ns

7.0

5.0

-

ns

LE Pulse Width
tw
HIGH or LOW
NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX
Device Type

X
Process

I

10-272

IB

MIL-STO-883, Class B

0
L
E

CERDIP
Leadless Chip Carrier
CERPACK

573

Octal Transparent Latch

54

-55°C to

+ 125°C

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full
temperature and voltage supply extremes
• 10ns typical address to output delay
• IoL = 14mA over full military temperature range
• CMOS power levels (5J.1W typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5J.1A max.)
• Octal D register (3-state)
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8

The IDT54AHCT574 are 8-bit registers built using advanced
CEMOS ™ , a dual metal CMOS technology. These registers consist of eight D-type flip-flops with a buffered common clock and
buffered three-state output control. When the output enable (OEl
input is LOW, the eight outputs are enabled. When the OE input is
HIGH, the outputs are in the three-state condition.
Input data meeting the set-up and hold time requirements of the
D inputs is transferred to the 0 outputs on the LOW-to-HIGH transition of the clock input.

PIN CONFIGURATIONS
INDEX

-

~

0

00
•

I

•••

&.....I

"-'

3

2

I

8

U

I

0

>0

I.

I

L....I

••

L-J

20 19

1

]4

]5
]6

L20-2

]7

18[

O2

16[

03
04
05

15 [:

]8

01

17 [:

14 [:

A~~~g
.... 0

o z
(!)

IDJ

& 00

LCC
TOP VIEW

DIP/CERPACK
TOP VIEW

FUNCTIONAL BLOCK DIAGRAM

CP
CLOCK

t5E
OUTPUT

ENABLE

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE
©

DECEMBER 1987

1987 Integrated Device Technology. Inc.

DSC-4056/-

10-273

IDT54AHCT574 HIGH-SPEED
CMOS OCTAL D REGISTER (3-STATE)

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

RATING

VALUE

UNIT

Terminal Voltage with Respect
toGND

-0.5 to +7.0

V

TA

Operating Temperature

-55 to +125

°C

TSIAS

Temperature Under Bias

-65 to +135

°C

TsTa

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

SYMBOL
CIN

Input Capacitance

CONDITIONS TYP.
VIN = OV

MAX. UNIT

6

10

pF

pF
COUT
Output Capacitance
8
12
VOUT= OV
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification Is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vee = 5.0V ± 10%
VLC = 0.2V
VHC = Vcc -0.2V
SYMBOL

TEST CONDITIONS(1)

PARAMETER

MAX.

UNIT

Input HIGH Level

Guaranteed Logic High Level

2.0

-

-

V

VIL

Input LOW Level

Guaranteed Logic Low Level

V

Input HIGH Current

Vcc = Max., \'IN = Vcc

5

~A

IlL

Input LOW Current

Vcc = Max., VIN = GND

-5

~A

-

-

0.8

IIH

-

-10

Vee = Max. (3)

-60

-120

-

Vcc = 3V, VIN = VLC or VHC ,IOH = -32~A

VHC

Vcc

-

VHC
2.4

Vcc
4.3

-

-

GND

VLC

-

GND

VLC

-

0.4

loz
Isc

VOH

Off State (High Impedance)
Output Current
Short Circuit Current

Output HIGH Voltage

Vcc = Max.

I Vo = Vcc
JVo = GND
I 10H
I 10H

Vcc = Min.
\'IN = VIH or VIL

= -150~A
= -1.0mA

Vee = 3V, \'IN = VLC or VHC ,IOL = 300~A
VOL

Output LOW Voltage

I 10L

Vcc = Min.
\'IN = \'IH or\k

I 10L

=

300~A

= 14mA

MIN.

TYP.(2)

\'IH

-

NOTES:
1. For conditions shown as max. or min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. DUration of the short Circuit test should not exceed one second.

10-274

10
~A

mA

V

V

IDT54AHCT574 HIGH-SPEED
CMOS OCTAL D REGISTER (3-STATE)

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC

= 0.2V; vHC = Vcc -

SYMBOL

0.2V
PARAMETER

TYP.(2)

MAX.

UNIT

-

0.001

1.5

mA

-

0.5

2.0

mA

"'IN ~ VHC
"'IN S VLC

-

0.15

0.25

mA/MHz

Vcc = Max.
Outputs Open
fcp = 1.0MHz,
50% Duty Cycle
OE = GND
One Bit Toggling
at fl = 500kHz
50% Duty Cycle

"'IN ~ VHC
"'IN S VLC
(AHCT)

-

0.15

1.8

"'IN = 3.4V
or
"'IN = GND

-

0.65

3.8

Vcc = Max.
Outputs Open
fcp = 1.0MHz,
50% Duty Cycle
OE = GND
Eight Bits Toggling
at f I = 250kHz
50% Duty Cycle

"'IN ~ VHC (6)
"'IN S VLC
(AHCT)

TEST CONDITIONS (1)

ICCQ

Quiescent Power Supply Current

Vcc = Max.
"'IN ~ VHC ; VIN S VLC
fcp = fl = 0

ICCT

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc = Max.
"'IN = 3.4V(3)

ICCD

Dynamic Power Supply Current(5)

Vcc = Max.
Outputs Open
OE = GND
One Bit Toggling
50% Duty Cycle

Icc

MIN.

mA

Total Power Supply Current(4)

-

0.63

2.2

-

2.88

11.2

VIN = 3.4V(6)

or
"'IN = GND

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, + 25°C ambient and maximum loading.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. Icc = 'QUIESCENT + IINPUTS + 'DYNAMIC
Icc = ICCQ + ICCT DH NT + ICCD (fcp/2 + fl N I)
ICCQ = Quiescent Current
ICCT = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL inputs High
NT = Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
NI = Number of inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-275

IDT54AHCT574 HIGH-SPEED
CMOS OCTAL 0 REGISTER (3-STATE)

MILITARY TEMPERATURE RANGE

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES

TRUTH TABLE

DESCRIPTION

CP

01

nE

OUTPUTS

INTERNAL

OE

CLOCK

INPUTS
D.

01

01

Hi-Z

H
H

L
H

X
X

Z
Z

NC
NC

LOAD
REGISTER

L
L
H
H

L
H
L
H

L
H
Z
Z

L
H
L
H

FUNCTION

The 0 flip-flop data Inputs.
Clock Pulse for the register. Enters data on the
LOW-to-HIGH transition.
The register three-state outputs.
Output Control. An active-LOW three-state control
used to enable the outputs. A HIGH level input
forces the outputs to the high impe-jance (off)
state.

01

-.r-

~

--"
--"

= HIGH
= LOW
= Don't Care
= High Impedance
= LOW-to-HIGH transition
NC = No Change

H
L
X
Z

-.r-

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SYMBOL

PARAMETER

CONDITION(1)

MIN.(2)

TYP.

MAX.

UNIT

2.0

15.0

ns

11.0

1.5

21.0

ns

9.0

1.5

15.0

ns

2.0

2.0

-

ns

Hold Time
HIGH or LOW
ON to CP

0.5

1.5

-

ns

CP Pulse Width
HIGH or LOW

10.0

6.0

-

ns

tpLH
tpHL

Propagation Delay
CPto ON

10.0

tZH
tZL

Output Enable
Time

tHZ
tLZ

Output Disable
Time

ts

Set-upTime
HIGH or LOW
ON to CP

tH

tw

CL = 50pF
RL = 500a

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAH CT
Temp. Range

XXXX

X

X

Device Type

Package

Process

---tl

,"----I

'--------------1

8

MIL-STD-883, Class 8

o

CERDIP
Leadless Chip Carrier
CERPACK

L
E

' - - - - - - - - - - - - - - - - - ; 574

10-276

Octal 0 Register (3-state)

FEATURES:

DESCRIPTION:

• Equivalent to ALS speeds and output drive over full temperature
and voltage supply extremes

The IDT54AHCT640 are 8-bit inverting buffer transceivers built
using advanced CEMOS TM, a dual metal CMOS technology. These
octal bus transceivers are designed for asynchronous two-way
communication between data buses. The devices transmit data
from the A bus to the 8 bus or from the 8 bus to the A bus, depending upon the level at the direction control (T/R) input. The enable
input (OE) can be used to disable the device so the buses are effectively isolated.

• 10ns data to output
• 10L = 14mA over full military temperature range
• CMOS power levels (5J.1W typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5J.1A max.)
• Inverting buffer transceiver
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8

PIN CONFIGURATIONS

FUNCTIONAL BLOCK DIAGRAM

T/l1

Vee

Ao
Al

DE
So

A2

Bl

A3

B2

A4

B3

A5

B4

Ae

85

A7

Be

GND

TIA

(19)

Ao

Al

A2

82

(5)
(15)

Fa

83

.i~~~o

A4

LJUIIULJ
3 2 LJ 20 19

(6)
(14)

A2

:] 4

18 [:

A3

]5

17 [:

A4

]e

A5

]7

Ae

]8

L20-2

m

81

(4)
(16)

A3
0

So

(3)
(17)

Br

I£I:

OE'

(2)
(18)

DIP/CERPACK
TOP VIEW

INDEX

(1)

So

A5

81

Ie [:

82

15 [:

83

14 [:

B4

84

(7)
(13)

Ae

85

(8)
(12)

~~r4~~

8e

(9)
A7

"'f@mafaf

(11)

CJ

Br

LCC
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated Device Technology. Inc.

DSC-4057/-

10-277

IDT54AHCT640 HIGH·SPEED CMOS
OCTAL INVERTING BUFFER TRANSCEIVER

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
. Terminal Voltage with Respect
toGND

MILITARY TEMPERATURE RANGE

CAPACITANCE

(1)

VALUE

UNIT

-0.5 to +7.0

V

TA

Operating Temperature

-55 to +125

°C

TelAs

Temperature Under Bias

-65 to +135

°C

TSTG

Storage Temperature

-65 to +150

°C

PT

Power Dissipation

0.5

W

lOUT

DC Output Current

120

mA

SYMBOL
CIN

(TA= +25°C, f = 1.0MHz)

PARAM ETER (1)
Input Capacitance

CONDITIONS TYP.
VIN = OV

MAX. UNIT

6

10

pF

COUT
VOUT= OV
8
12
pF
Output Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT·
IN GS may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or any other
conditions above those Indicated in the operational sections of this
specification Is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE·
Following Conditions Apply Unless Otherwise Specified:
TA = -55°C to + 125°C
Vcc = 5.0V + 10%
VlC = 0.2V
VHC= Vcc -0.2V
SYMBOL

TEST CONDITIONS (1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

-

V

0.8

V

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

Input LOW Level

Guaranteed Logic LOW Level

-

-

IIH

Input HIGH Current
(Except I/O Pins)

Vee = Max., "'N = Vcc

-

-

5

JJA

III

Input LOW Current
(Except I/O Pins)

Vcc = Max., "'N = GND

-

-

-5

JJA

IIH

Input HIGH Current
(I/O Pins)

Vee = Max., VI = Vcc

-

-

15

JJA

III

Input LOW Current
(I/O Pins)

Vee = Max., VI = GND

-

-

-15

JJA

Isc

Short Circuit Current

Vee = Max. (3)

-60

-100

VHC

Vee

Output HIGH Voltage

VHC

Vcc

-

mA

Vee = 3V, "'N = VlC or VHC • 10H = -32 JJA
10H = -150jJA
Vcc = Min.

2.4

4.3

-

VIH
"'l

VOH

I
I

"'N = "'H or"'l

10H = -12mA

-

GND

VlC

I 10l = 300JJA

-

GND

VlC

I

-

-

0.4

Vee =3V, "'N = VlC or VHe , 10l = 300 JJA
VOL

Output LOW Voltage

Vec = Min.
VIN = "'HorVll

10l = 14mA

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

10-278

V

V

IDT54AHCT640 HIGH·SPEED CMOS
OCTAL INVERTING BUFFER TRANSCEIVER

MILITARY TEMPERATURE RANGE

POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; \i-tc = Vcc - 0.2V
PARAMETER

I ceo

Quiescent Power Supply Current

Vcc = Max.
VIN ~ VHC ; "'N ~ VLC
fl = 0

ICCT

Quiescent Power Supply Current
TIL Inputs HIGH

Vcc = Max.
VIN = 3AV(3)

Dynamic Power Supply Current(5)

Vcc= Max.
Outputs Open
BE = GND
T/R = GND or'tt
One Input Toggling
50% Duty Cycle

ICCD

Vcc = Max.
Outputs Open
fl = 1.0MHz
§Q% Duty Cycle
OE = GND
One Bit Toggling
Icc

Total Power Supply Current

TYP.(2)

MAX.

-

0.001

1.5

mA

-

0.5

2.0

mA

"'N ~ VHC
"'N ~ VLC

-

0.15

0.25

"'N ~ VHC
"'N ~ VLC
(AHCT)

-

0.15

1.8

VIN = 3AVor
VIN = GND

-

004

2.8

TEST CONDITIONS

SYMBOL

MIN.

(1)

UNIT

mAl
MHz

mA

(4)

Vcc = Max.
Outputs Open
fl = 250kHz
§Q% Duty Cycle
OE = GND
Eight Bits Toggling

"'N ~ VHC (6)
"'N ~ VLC
(AHCT)

VIN = 3AV or
VIN = GND

(6)

-

0.3

2.0

-

2.3

10.0

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Per TIL driven input (YIN = 3AV): all other inputs at Vcc or GND.
4. Icc = laulEscENT + IINPUTS + IDYNAMIC
Icc = I ceo + ICCT DH NT + ICCD (fcp/2 + fl N I)
Icco = Quiescent Current
ICCT = Power Supply Current for a TIL High Input (YIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
ICCD = Dynamic Current caused by an input Transition pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fl = Input Frequency
N I = Number of inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
5. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
6. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.

10-279

IDT54AHCT640 HIGH-SPEED CMOS
OCTAL INVERTING BUFFER TRANSCEIVER

MILITARY TEMPERATURE RANGE

TRUTH TABLE

DEFINITION OF FUNCTIONAL TERMS
PIN NAMES
OE

DESCRIPTION
Output Enable Input (Active LOW)

T/R

Transmit/Receive Input

Ao-A7

Side A Inputs or 3-State Outputs

Bo-B7

Side B Inputs or 3-State Outputs

INPUTS
OE

OPERATION

TIR

L

L

Bus B Data to Bus A

L

H

Bus A Data to Bus B

H

X

Isolation

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
CONDITION(1)

SYMBOL

PARAMETER

tpLH
t pHL

Propagation Delay
Ato B
BtoA

tZH
tZL

Output Enable
Time

tHZ
tLZ

Output Disable
Time

CL = 50pF
RL = 5000

TYP.

MIN.(2)

MAX.

UNIT

10.0

1.5

14.0

ns

15.0

1.5

27.0

ns

12.0

1.5

20.0

ns

NOTES:
1. See test circuit and waveform.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

ORDERING INFORMATION
IDTXXAHCT
Temp. Range

XXXX
Device Type

X
Package

X
Process

----il

B

MIL-STD-883, Class B

L...----------l

D
L
E

CERDIP
Leadless Chip Carrier
CERPACK

640

Octal Inverting Buffer Transceiver

,----I

L...-_ _ _ _ _ _ _ _ _ _ _ _ _--1

'----------------------l54

10-280

-55°C to +125°C

FEATURES:

DESCRIPTION:

• Equivalentto ALS speeds and output drive overfull temperature
and voltage supply extremes

The IDT54AHCT645 are 8-bit non-inverting buffer transceivers
built using advanced CEMOS ™ , a dual metal CMOS technology.
These non-inverting buffer transceivers are designed for asynchronous two-way communication between data buses. The devices
transmit data from the A bus to the 8 bus or from the 8 bus to the A
bus, depending upon the 1/74evel at the direction control (T/R) input. The enable input (OE) can be used to disable the device so the
buses are effectively isolated.

• 8ns typical data to output delay
• 10L = 14mA over full military temperature range
• CMOS power levels (5JJW typo static)
• 80th CMOS and TTL output compatible
• Substantially lower input current levels than ALS (5JJA max.)
• Non-inverting buffer transceiver
• JEDEC standard pinout for DIP and LCC
• Military product compliant to MIL-STD-883, Class 8

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

Tm

Vee

Ao
AI
A2
A3
A4
A5
Ae
A7

DE"
Bo
B,
B2
B3
B4
B5
Be
B7

GND

Tm

(1)
(19)

Ao

(18)

A,

~

INDEX

oJQ:

0

A3
A4

UUIIUU

A2
A3
A4
A5
Ae

:J 4
]5
]e
]7
] 8

3 2 U 20 19
1
L20-2

9 10 11 12 13

A5

~

00.....

B4

(7)
(13)

Ae

B5

(8)
(12)

nnnnn
.,(

~

(6)
(14)

Bo
B,
B2
B3
B4

B2

(5)
(15)

fa

 50dB
• Registered data and video controls
• Differential current outputs
• Flexible video controls
• Inherently low glitch energy
• Multiplying mode capability
• Single 5V power supply
• Available in 24-pin hermetic DIP, 24-pin plastic DIP and
.
28-pin LCC
• Military product is compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

CONTROL

LOGIC

FH, BLANK
BRT, SYNC

iii

CONY,
CONV

2

FT

REF+

REF-

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology, Inc.

DECEMBER 1987
D5C-5000/-

11-1

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C18 8-BIT CMOS VIDEO DAC

PIN CONFIGURATIONS

D5
D6

dO 0- d) oln 0" d' 0'"

D4
D3
D2
D1
VEEA

Dr
D8
VEED
~

OUT+
OUT-

FT

AGND

CONV

N/C

FH

1

25_

D1

24[:

NC

]7

23[:

VEEA

22[:

OUT +
OUT-

L28-1

:]8

FT ]9
DGND

NC

REF+
REF-

BLANK
BRT

_5

VEED :16

CONV
CL5FW

COMP

VGND

_] tt tt tt u'ts ~ ~ [_

21 [:

]10
-]11

20[:
19[-

-~~fifi~~~-

AGND

COMP

:::C~f-()+'()

SYNC

u.za:zu.u.z

~w~~~
LCC
TOP VIEW

DIP
TOP VIEW

FUNCTIONAL DESCRIPTION
GENERAL INFORMATION
The ID175C18 output current is proportional to the product of
the digital input data and the analog reference current. All the digital Inputs, data and control are compatible with standard ECl logic
levels. The ID175C18 is normally operated synchronously with
data being latched by the rising edge of the convert clock, CONV.
FT, the feedthrough control input, determines the operating mode.
When FT is lOW, the part operates in the synchronous mode and
the low-to-hlgh transition of the convert clock, CONV, latches data
and control values into internal D-type registers. The registered values are then decoded and presented to switched current sinks
which produce the appropriate analog output values. When FT is
HIGH, the part operates asynchronously and the digital inputs are
not latched. The analog output, then, changes in response to the
digital Inputs without regard to clock. FT is the only asynchronous
input and is typically tied to the appropriate DC level.
The ID175C18 uses a 6x2 segmented DAC approach where the
six MSBs ofthe input data are decoded into a parallel "Thermometer" code which produces sixty-four "coarse" output levels. The remaining two lSBs of the input data drive three binary weighted current switches with a total contribution of one-sixty-fourth of full
scale. The MSB and lSB currents are summed at the output to produce 256 analog levels.
SYNC, BLANK, FH (Force High) and BRT (BRighT) are special
control inputs which drive appropriately weighted current
switches. These currents are summed at the output with the level
produced by the data inputs to allow for specific levels required by
video applications such as the sync pulses and the blanking levels.

reference for the transistors in the DAC. The feedback loop internally includes current sources which are identical to the current
sink transistors, guaranteeing that the reference current will be precisely mirrored in the DAC.
Since the output currents are proportional to the digital data and
the reference current, the full-scale output current may be adjusted
over a limited range by varying the reference current. In the same
vein, the stability of the output depends strongly on the stability of
the reference. The reference current is normally applied to REF+,
while REF- is usually connected to a negative reference through a
resistor equal to the effective impedance seen on REF+.
Through careful design of the reference amplifier, no external
compensation capacitor is required and the COMP pin should be
left unconnected.

CONTROLS

...

The ID175C18 has four special control inputs: SYNC, BLANK,
FH (Force High) and BRT (BRighT), as well as FT (Feed Through
control). Typically, the ID175C18 is operated in the synchronous
mode which ensures the lowest output noise. When FT is forced
HIGH, the input registers pass the data and control information
through without latching, allowing the analog output to change
asynchronously.
In the synchronous mode, the control inputs are registered by
the rising edge of CONV in the same manner as the data inputs.
The controls, like the data, must be stable for a set-up time (ts) before, and a hold time (tH) after, the rising edge of CONV. In the
asynchronous mode, only the minimum pulse widths are relevant.
The video controls produce specific output levels which are
used for frame synchronization, horizontal blanking, etc. as described in various standards such as RS-343A. The effect of these
controls on the analog output is shown below. The internal logic
simplifies the use of the controls in video applications. BLANK,
SYNC and FH override the data inputs. SYNC overrides all other
inputs and produces a full negative level. FH drives the analog output to full-scale producing a reference white level. The BRT control
creates a "whiter than white" level by adding 10% of full-scale to
the present output value.

POWER CONSIDERATIONS
The ID175C18 operates from separate analog and digital
supplies to provide the highest noise immunity on the analog output to digital switching spikes. All power and ground pins must be
connected.

REFERENCE CONSIDERATIONS
The ID175C18 has two reference inputs, REF+ and REF-,
which are simply the non-inverting and inverting inputs to an
internal buffer amplifier. The output of this amplifier serves as the

11-2

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C18 8-BIT CMOS VIDEO DAC

VIDEO CONTROL OUTPUT VALUES (4)
SYNC

BLANK

FH

BRT

DATA

OUT-(mA~1)

OUT-(V)(2)

OUT-(IRE)(3)

Sync

1

X

X

X

X

28.57

-1.071

-40.0

Blank

0

1

X

X

X

20.83

-0.781

10% White

0

0

1

1

X

0.00

0.00

110.0

White

0

0

1

0

X

1.95

-0.073

100.0

Black

0

0

0

0

00

19.40

-0.728

7.5

White

0

0

0

0

FF

1.95

-0.073

100.0

10% Black

0

0

0

1

00

17.44

-0.654

17.5

0.00

110.0

DESCRIPTION

10% White
0
0
0
FF
0.00
1
NOTES:
1. OU"f+ is complementary to OUT-. Current is specified as conventional current when flowing into the device.
2. Voltage produced when driving the standard load configuration (37.5 ohms). See Figure 4.
3. 140 IRE units = 1.OOV
4. RS-343A tolerance on all control values is assumed.

10UT+

0.0

= 28.57 - 10UT-'

DATA INPUTS

CLOCK INPUT CONV

The inputs of the IDT75C18 are single ended, ECl-compatible.
Internal pull down resistors force unconnected pins to a logic lOW
level.
In the synchronous mode (FT is lOW), the data inputs are registered by the rising edge of CONV. The data inputs must be stable
for a set-up time (ts) before, and a hold time (tH) after, the rising
edge of CONV. In the asynchronous mode (FT is HIGH), the input
registers are disabled and only the minimum pulse widths are relevant. In this mode, the analog output changes asynchronously in
response to the input data.
SYMBOL
FUNCTION

The clock input to the IDT75C18 (CONV) is a differential EClcompatible input. This signal may be driven single ended by connecting CONV to a suitable bias voltage (Vee) which determines
the switching threshold of CONV.

Dl
D2
D3
D4
Do
De
D7
De

ANALOG OUTPUTS
The two analog outputs of the IDT75C18 are high impedance
complementary current sinks which are capable of driving a doubly terminated 75 ohm load to standard video levels. The output
voltage will be the product of the output current and the effective
load impedance and will usually be between 0 and -W when the
VEE = -5.2V. The outputs sink current from AGND, so that in the positive supply case (interfacing to CMOS or TTL), the output voltage
swings between + 5V and + 4V. In AC coupled applications, this
DC bias is unimportant. Shown below is a simple circuit which references the output voltage to the most negative supply.

Data Bit 1 (MSB)

•
•
•
Data Bit 8 (LSB)

ANALOG
+5V -.-~-----,

The inputs of the IDT75C18 are voltage comparators with the
threshold level set to approximately -1.27V, ensuring the correct
logic state when driven by standard ECloutputs. It is possible to
overdrive the inputs without harming the device, allowing a direct
interface to CMOS logic. In general, the input signals will correctly
drive the IDT75C18 as long as they remain between VEED, VEEA and
AGND, DGND and meet the VIL and VIH specifications.
The diagram below shows a simple two resistor level shifter
which allows the IDT75C18 to be driven from TTL signals.

1KO

iii

LM313
5000

1K

+
1jJF

5.0V - - -.....- - - - - -.....- - - - ,

AGND REF +

REF-

IDT75C18

OUT +

0.01jJF
390

390

OUT-~~--+--r----'

IN
ANALOG GROUND

~
OV - - -......- - - - - - - - - - - '

11-3

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C18 8-BIT CMOS VIDEO DAC

ABSOLUTE MAXIMUM RATINGS
SYMBOL

RATING

RECOMMENDED OPERATING CONDITIONS

(1)
VALUE

UNIT

SYMBOL

PARAMETER
Digital Supply Voltage
(REF DONd

MIN.

TYP.

MAX.

VEEO

-4.9

-5.2

-5.5

V

VEEA

Analog Supply Voltage
(REF AaNO)

-4.9

-5.2

-5.5

V

VAGNO

Analog Ground
Voltage (REF DONO)

-0.1

0

+0.1

V

VEEAVEEO

Supply Voltage
Differential

-0.1

0

+0.1

V

V1CM

CONY, Common
Mode Range

-0.5

-

-2.5

V

V10F

CONY, Differential
Range

0.4

1.2

V

V1L

Input Voltage,
Logic LOW

-1.49

-

-

V

'-"H

Input Voltage,
Logic HIGH

-

-

-1.045

V

IREF

Reference Current,
Video Std.(l)
a-Bit Lin.

1.059
1.0

1.115

1.171
1.3

rnA
mA

TA

Ambient
Temperature

POWER SUPPLIES
VEEO

Measured to DONO

-7.0 to +0.05

V

VEEA

Measured to DONO

-7.0 to +0.05

V

AOND

Measured to DONO

-0.5 to +0.5

V

INPUT VOLTAGES
CONY, Data
& Controls
REF Input,
Applied Voltage (2)

Measured to DoNO

V EEO to 0.5

Measured to AONO

V EEA to 0.5

V

6.0

mA

0.5

mA

-2.0 to +0.4

V

REF+

REF Input,
Applied Current(3,4) REF-

V

OUTPUT
Analog Output,
Applied Voltage (2)

Measured to AONO

Analog Output, (3 4)
. Applied Current '

50

Short
Circuit Duration

mA

Unlimited

TEMPERATURE
Operating,
Ambient

Storage

-55 to +125

DC

Oto +70

DC

Military

-65 to +150

DC

Commercial

-55 to +125

DC

Military
Commercial

I
I

MIL.
COM'L.

-55

-

0

-

UNIT

+125

DC

+70

DC

NOTE:
1. Minimum and maximum values allowed by ±50/0 variation given in
RS-343Aand RS-170 after initial gain correction of device.

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Absolute Maximum
Ratings are limiting values applied individually While all other parameters are within specified operating conditions. Functional operation under any of these conditions Is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the
device.

11-4

----------------_._._.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C18 8-BIT CMOS VIDEO DAC

DC ELECTRICAL CHARACTERISTICS
Specified over the Recommended Operating Conditions unless otherwise stated.
MAX.

UNIT

-

125

rnA

5

pF

Input Capacitance,
Data & Controls

-

5

pF

Vocp

Compliance Voltage,
+ Output

-1.2

+0.1

V

VOCN

Compliance Voltage,
-Output

-1.2

+0.1

V

SYMBOL

PARAMETERS

IEEA+
IEEO

Supply Current

CREF

Equivalent Input C,
REF (+), REF (-)

CI

MIN.

TEST CONDITIONS
VEEA = VEEO = Max.,(1)Static

-

kO

Ro

Equivalent Out R

20

Co

Equivalent Out C

-

20

pF

lop

Max. I, +Output

VEEA = Typ., SYNC = BLANK= 0
FH = BRT = 1

30

-

mA

I
ON

Max. I, -Output

VEEA = TYP.,SYNC = 1

30

-

rnA

IlL

Input Current, Logic
LOW, Data & Controls

VEEO = Max.; VI = -1.40V

-

200

~A

IIH

Input Current, Logic
HIGH, Data & Controls

VEEO = Max.; VI = -1.00V

IIC

Input Current, CONV

V EEO = Max.; -2.5

< \'J < -0.5

-

200

~A

-

50

~A

1DT75C18x100
MAX.
MIN.

IDT75C18x125
MIN.
MAX.

NOTE:
1. Worst case for all Data and Control States. No termination on IOUT+or 10UT-.

AC ELECTRICAL CHARACTERISTICS
Specified over the Recommended Operating Conditions unless otherwise stated.
SYMBOL

TEST CONDITIONS

PARAMETERS

IDT75C18x70
MAX.
MIN.

UNIT

Fs

Max. Conversion Rate

VEEA ,VEEO = Min.

-

70

-

100

-

125

MHz

tpWL

CONV LOW Time

6

-

ns

6

-

4

CONV HIGH Time

-

5

tpwH

VEEA , VEEO = Min.
VEEA , VEEO = Min.

4

ts

Set-up Time, Data & Control

VEEA , VEEO = Min.

8

-

6

5

ns

tH

Hold Time, Data & Control

VEEA , VEEO = Min.

5

-

1

-

0

-

tose

CONV to OUT Delay

-

10

-

8

ns

DATA to OUT Delay

-

14

tOST

VEEA ' VEEO = Min. FT = 0
VEEA , VEEO = Min. FT = 1

20

-

16

-

13

ns

-

-

-

-

-

-

ns

-

-

-

ns

VEEA ' VEEO = Min. FT = 0
0.2%
tSI

Current Setting Time

tRI

Current Rise Time

0.8%
3.2%

-

-

10% to 90% of Full Scale

-

3.0

11-5

5

ns

ns

-

-

-

ns

2.1

-

1.7

ns

iii

1DT75C18 a-BIT CMOS VIDEO DAC

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SYSTEM PERFORMANCE CHARACTERISTICS
Specified over the Recommended Operating Conditions unless otherwise stated.
SYMBOL

PARAMETERS

TEST CONDITIONS

MIN.

MAX.

UNIT

= Typ.
= Typ.

-

0.2

%FS

-

0.2

%FS

-

t10

J.lA

ELI

Linearity Error Integral

VEEA • VEED , I REF

ELD

Linearity Error Differential

VEEA ' VEED , I REF

IOF

Output Offset I

EG

Abs. Gain Error

TCG

Gain Error Tempco

= Max. SYNC = BLANK = 0,
=1
VEEA , VEED , I REF = Typ.
VEEA , VEED
FH = BRT

= 1mV

BWR

Ref. Bandwidth -3dB

~VREF

DP

Differential Phase

4 x NTSC

DG

Differential Gain

4x NTSC

PSRR

Power Supp. Rej. Ratio

VEEA , VEED , IREF
VEEA , VEED , IREF

PSS

-

t5

%FS

-

to.024

%FS/OC

1.0

Deg.

1

MHz

-

2.0

%

-

45

dB

Power Supp. Sensitivity

V EEA' V EED' I REF

= Typ.(1)
= Typ.(2)
= Typ.

GC

Peak Glitch Charge

GI

Peak Glitch Current

GE

Peak Glitch Energy

FTc

Clock Feedthrough

FTD

Data Feedthrough

I

-

55

dB

-

120

~VN

Registered Mode Typ. (3. 4)

-

800

fc

Registered Mode

1.2

rnA

Registered Mode Typ. (4)

-

30

pV-Sec

Data Constant (5)

-

-50

dB

Clock Constant (5)

-

-50

dB

NOTES:
1. 20kHz, t 0.3V ripple superimposed on VEEA. VEED ; dB relative to full gray scale.
2. 60Hz, to.3V ripple superimposed on VEEA , VEED ; dB relative to full gray scale.
3. fcoulombs = microamps x nanoseconds.
4. 37.50 load. Because glitches tend to be symmetric, average glitch area approaches zero.
5. dB relative to full gray scale, 250MHz bandwidth limit.

11-6

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT75C18 8-BIT CMOS VIDEO DAC

~

----=-.=A-----*I-~---

~.

DATA,CONTROL

INPUTS'DST_F
~tDS

OUT-

~tSI-,
1/2 LSB
Figure 1. Timing Diagram

\jDF

__- :-_______x_____'
1

i

o.ov

',,~:~---------------------

,,

,, ,

,,

------------------~----~~-----------------

V'CM

,

,,

,

V 1CM MIN.

III
-1.3V

MAX.--------------~~:~~:-----X""------ ::::
Figure 2. CONVert, CONVert Switching Levels

11-7

IDT75C18 8·BIT CMOS VIDEO DAC

MILITARY AND COMMERCIAL TEMPERATURE RANGES·

CURRENT
SINK #N

r-----------.,

r-------------P

v-+------.------------f----0 OUT+

.---:-' v ......-------i~--__1.-----..I---{) OUTREFERENCE
AMPLIFIER

r-------.,

-.

REF+o---+-~----------~+----,

'REF

I

REF - o - - - l l - - - - I

I

I

I
I
I

I

I

I

I
I

I _______ J
I..

I

'lEEA

1..---.1

Figure 3. Equivalent Output Circuit

VIDEO
MONITOR
OUT-

~750
r---~I
750

750 I
I L
I
IL. _ _ _ _ .JI

COAX, R

IDT75C18

~ j

750

750

~

CCAX~75n

0

INVERSE

VIDEO

TEST LOAD:
OUT +
OUT-

D--r-----+---. VIDEO OUT
RL
37.50

0 TO -1 VOLT

~=~ND

Figure 4. Standard load Configuration

11-8

IDT75C18 8-BIT CMOS VIDEO DAC

IRE

mV (REF AGND )
__

110

o

100

-73

.;;.8R;.;;I..;;.G.;.;H.;.T_~

MILITARY AND COMMERCIAL TEMPERATURE RANGES

_________________________________ _
NORMAL HIGH (WHITE)

--r------------------.>-.. >.. -w

i~i ~!I I:ljI J 111;1111il il)1 111;1;;1\256L___N~~~ ~'::(~c;:~
"GRAY LEVELS·

7.5

-728

o

-781

-40

___ _f; . . . . • . . > • • • • • • •.• • • • • • • • • • • • • •

-------------------------"T'

-1071 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ......._ _
SY_N_C_ _....... _ _ _ _ _ _ _ _ _

Figure 5. Video Output Waveform for Out- and Standard Load Configuration

11-9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C18 8-BIT CMOS VIDEO DAC

MSB

VIDEO
DATA
(ECl)

lSB

D5

D4

D6

D3

D7

D2

06

01

-S.2V

r------,

VEEA
-S.2V

OUT+

VEEO

~

OUT-

C1

IDT75C18

CONVert

CONY

CQNITert

CONY

N/C

AGNO

I
I

FT

(ECl)

-

FH

R1 SOO
R2
9000

T = Eel TERMINATION

REF-

BLANK

VR1
lM313

SYNC
------{

BRT

------------------------------~
-S.2V

PARTS LIST
RESISTORS
R1

1kO

Pot

10 Turn

R2

9000

1% Metal Film
1% Metal Film

Ceramic disc

R3

2.00kO

R4

37.S0

1/8W
1/8W
1/8W

0.1~F

SOV

1% Metal Film

CAPACITORS
C1-C3

INTEGRATED CIRCUITS
U1

IDT7SC18

D/A Converter

VOLTAGE REFERENCES
VR1

lM113 or lM313

Bandgap Reference

INDUCTORS

L1

I

I
I
I1... _ _ _ _ _ _ -'I

IREF

REF+

[

I
I

~~~~======~======I~
ICfRC
75~ iI
I

DGNO

~g~~ROlS

VIDEO
MONITOR

Ferrite Bead Shield Inductor Fair-Rite
PIN 2743001112 or Similar

Figure 6. Typical Interface Circuit

11-10

IDT75C18 8-BIT CMOS VIDEO DAC

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XXX)(
X
Device Type Power

X

x

X

Speed

Package

Process/
Temperature

Rony:LANK

11-11

Commercial (O°C to

+ 70° C)

Military (-55°C to + 125°C)
Compliant to MIL-SID-883, Class B

TP
D
l

Plastic THINDIP
CERDIP
leadless Chip Carrier

70
100
125

} Speed In M""",,,,,,

S

Standard Power

75C18

ECl-Compatible

FEATURES:

DESCRIPTION:

• Graphics-ready

The IDT75C19 is a 70/100/125 MegaSample per Second
(MSPS), 9-blt Digital to Analog Converter. It can directly drive a
doubly terminated 75Cl load to levels compatible with RS-343A.
Four special controls for blanking, synchronization and highlighting allow the device to be used In typical video applications with no
extra components.
The IDT75C19 is built using lOT's high-performance CEMOS TM
process. Innovative design methods, which Include on-chip data
registers and precise matching of propagation delays, as well as
an improved segmenting/decoding architecture, significantly reduce glitch energy. The IDT75C19 offers high-performance and
low power In a 24-pin hermetic DIP, 24-pin plastic DIP or 28-pin
LCC.
The IDT75C19 Is functionally compatible with the TRW
TDC1018, with the advantage of low power due to CMOS processIng. Besides providing higher reliability by running cooler, power
supply requlremonts are reduced. Another advantage of the lower
power dissipation is that this part may be packaged in a spacesaving, cost-effective, 0.3 inch plastic package.
The IDT75C19 military DAC Is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the highest
level of performance and reliability.

• Function-compatible with TRW TDC1018
• 9 bits, 1/2 LSB linearity
• 70, 100, 125MHz models available
• ECL-compatible inputs
• Low power dissipation < 400mW
• Power supply noise rejection> 50dB
• Registered data and video controls
• Differential current outputs
• Flexible video controls
• Inherently low glitch energy
• Multiplying mode capability
• Single 5V power supply
• Available In 24-pin hermetic DIP, 24-pin plastic DIP and
28-pin LCC
• Military product is compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

9
/

D1 - D9
FH.BLANK
BRT. SYNC
CON~

CONV

)

CONTROL
LOGIC

I
)

/

~

REGISTER
.I.

4

;..

t-+

~

2

FT
Ali-

A

."

.....

.....

OUT +
OUT-

~

r+

/

CURRENT
SWITCHES

REFERENCE
CURRENT
SOURCES

~
I I

REF+

REF-

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-5001/-

19871nlegraled DevIce Technology. Inc.

11-12

_._..._ - - - - - - - - - - - - - - - - - - -

IDT75C19 9-BIT CMOS VIDEO DAC

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

D5
D6

D4

Dr

D2

D8

Dl

D3

VEED
CONY

VEEA

com

OUT-

•

N/C
V EED
CONY

OUT+

FT

FT
DGND

D9

FH
BLANK

REF+
REF-

BRT

SYNC

- 5

N/C

I

•••••••••

I

••

4' 3' '2 U 2s 27 26 [_
1

25 -

Dl

]6

24[:

N/C

] 7

23[:

VEEA

'CONV ]

AGND

VGND

-)

8

L28-1

]9
] 10

] 1;2 13 14 15 16 17

22[:

OUT +

21C

OUT-

20[:

AGND

1~9r:

nnnnnnn

DIP
TOP VIEW

D9

LCC
TOP VIEW

FUNCT!ONAL DESCRIPTION
GENERAL INFORMATION
The IDT75C19 output current is proportional to the product of
the digital input data anc:l the analog reference current. All the digital inputs, data and control, are compatible with standard ECl
logic levels. The IDT75C19 is normally operated synchronously
with data being latched by the rising edge of the convert clock,
CONY. FT, the feedthrough control input, determines the operating
mode. When FT is lOW, the part operates in the synchronous
mode and the low-ta-high transition of the convert clock, CONY,
latches data and control values into internal D-type registers. The
registered values are then decoded and presented to switched current sinks which produce the appropriate analog output values.
When FT is HIGH, the part operates asynchronously and the digital
Inputs are not latched. The analog output, then, changes in response to the digital inputs without regard to clock. FT is the only
asynchronous input and is typically tied to the appropriate DC
level.
The IDT75C19 uses a 6x3 segmented DAC approach where the
six MSBs of the input data are decoded into a parallel "Thermometer" code which produces sixty-four "coarse" output levels. The remaining three lSBs of the input data drive seven binary weighted
current switches with a total contribution of one-sixty-fourth of full
scale. Tho MSB and lSB currents are summed at the output to praduce 512 analog levels.
SYNC, BLANK, FH (Force High) and BRT (BRighT) are special
control inputs which drive appropriately weighted current
switches. These currents are summed at the output with the level
producec! by the data inputs to allow for specific levels required by
video applications such as the sync pulses and the blanking levels.

REFERENCE CONSIDERATIONS
The IDT75C19 has two reference inputs, REF+ and REF-,
which are simply the non-inverting and inverting inputs to an internal buffer amplifier. The output of this amplifier serves as the reference for the current sources in the DAC. The feedback loop internally includes a transistor which is identical to the current sink transistors, guaranteeing that the reference current will be precisely
mirrored in the DAC.
Since the output currents are proportional to the digital data and
the reference current, the full-scale output current may be adjusted
over a limited range by varying the reference current. In the same
vein, the stability of the output depends strongly on the stability of
the reference. The reference current is normally applied to REF +,
while REF - is usually connected to a negative reference through a
resistor equal to the effective impedance seen on REF+.

CONTROLS
The IDT75C19 has four special control inputs: SYNC, BLANK,
FH (Force High) and BRT (BRighT), as well as FT (Feed Through
control). Typically, the IDT75C19 is operated in the synchronous
mode which ensures the lowest output noise. When FT is forced
HIGH, the input registers pass the data and control information
through without latching, allowing the analog output to change
asynchronously.
.
In the synchronous mode, the control inputs are registered by
the rising edge of CONY in the same manner as the data inputs.
The controls, like the data, must be stable for a set-up time (ts) before, and a hold time (tH) after, the rising edge of CONY. In the
asynchronous mode, only the minimum pulse widths are relevant.
The video controls produce specific output levels which are
used for frame synchronization, horizontal blanking, etc. as described in various standards such as RS-343A. The effect of these
controls on the analog output is shown below. The internal logic
simplifies the use of the controls in video applications. BLANK,
SYNC and FH override the data inputs. SYNC overrides all other
inputs and produces a full negative level. FH drives the analog output to full-scale producing a reference white level. The BRT control
creates a "whiter than white" level by adding 10% of full-scale to
the present output value.

POWER CONSIDERATIONS
The IDT75C19 operates from separate analog and digital
supplies to provide the highest noise immunity on the analog output to digital switching spikes. All power and ground pins must be
connected.

11-13

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C19 9-BIT CMOS VIDEO DAC

VIDEO CONTROL OUTPUT VALUES (4)
SYNC

BLANK

FH

BRT

DATA

OUT-(mA)(1)

OUT-(V)(2)

OUT-(IRE)(3)

Sync

1

X

X

X

X

28.57

-1.071

-40.0

Blank

0

1

X

X

20.83

-0.781

10% White

0

0

1

1

X
X

0.00

0.00

110.0

White

0

0

1

0

X

1.95

-0.073

100.0

Black

0

0

0

0

000

19.40

-0.728

7.5

White

0

0

0

0

1FF

1.95

-0.073

100.0

10% Black

0

0

0

1

000

17.44

-0.654

17.5

0.00
10% White
0
0
0
1
1FF
0.00
NOTES:
1. OUT+ is complementary to OUT-. Current is specified as conventional current when flowing into the device. lOUT + = 28.57 2. Voltage produced when driving the standard load configuration (37.5 ohms). See Figure 4.
3. 140 IRE units = 1.00V
4. RS-343A tolerance on all control values is assumed.

110.0

DESCRIPTION

0.0

10UT-.

DATA INPUTS

CLOCK INPUT CONV

The inputs of the IDT75C19 are single ended, ECl-compatible.
Internal pull down resistors force unconnected pins to a logic lOW
level.
In the synchronous mode (FT is lOW), the data inputs are registered by the rising edge of CONY. The data inputs must be stable
for a set-up time (ts ) before, and a hold time (tH) after, the rising
edge of CONY. In the asynchronous mode (FT is HIGH), the input
registers are disabled and only the minimum pulse widths are relevant. In this mode, the analog output changes asynchronously in
response to the input data.

The clock input to the IDT75C19 (CONV) is a differential Eelcompatible input. This signal may be driven single ended by connecting CONY to a suitable bias voltage (Vss) which determines
the switching threshold of CONy.

SYMBOL

FUNCTION

Dl
D2
D3
D4

Data Bit 1 (MSB)

D~

De
D7
DB
DB

ANALOG OUTPUTS
The two analog outputs of the IDT75C19 are high impedance
complementary current sinks which are capable of driving a doubly terminated 75 ohm load to standard video levels. The output
voltage will be the product of the output current and the effective
load impedance and will usually be between OV and -1V when VEE
= -S.2V. The outputs sink current from AGND, so that in the positive
supply case (interfacing to CMOS or TTL), the output voltage
swings between +5Vand +4V.ln AC coupled applications, this
DC bias is unimportant. Shown below is a simple circuit which references the output voltage to the most negative supply.

•
•

•
Data Bit 9 (LSB)

LM313

The inputs of the IDT75C19 are voltage comparators with the
threshold level set to approximately -1.27V, ensuring the correct
logic state when driven by standard ECloutputs. It is possible to
overdrive the inputs without harming the device, allowing a direct
interface to CMOS logic. In general, the input signals will correctly
drive the IDT75C19 as long as they remain between VEED, VEEA and
AGND, DGND and meet the VIL and VIH specifications.
The diagram below shows a simple two resistor level shifter
which allows the IDT75C19 to be driven from TTL signals.

5000

AGND REF+

1K

+

REF390

IDT75C19

OUT +

I--+---+--i---+--.....I

OUT-

I--+---+--i--.......

390
5.0V - - -....- - - - - -__-----.

IDT75C19
IN

ANALOG GROUND

INPUTS

~

OV _ _ _....._ _ _ _ _ _ _ _ _ _.....1

11-14

1DT75C19 9-BIT CMOS VIDEO CAC

MILITARYANCCOMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL

RATING

RECOMMENDED OPERATING CONDITIONS
VALUE

UNIT

SYMBOL

POWER SUPPLIES
VEED

Measured to DGND

-7.0 to +0.05

V

VEEA

Measured to DGND

-7.0 to +0.05

V

AGND

Measured to DGND

-0.5 to +0.5

V

VEED
VEEA

INPUT VOLTAGES
CONY, Data

& Controls

Measured to DaND

REF Input.
Applied Voltage(2)

Measured to AGND

REF Input.
Applied Current(3.4)

REF+
REF-

VEED to 0.5

V

VEEA to 0.5

V

6.0
0.5

mA
mA

OUTPUT
Analog Output,
Applied Voltage(2)

Measured to AGND

Analog Output,
Applied Current(3.4)
Short
Circuit Duration

-2.0 to +0.4

V

50

mA

Operating,
Ambient
Storage

Military
Commercial

-55 to +125
Oto +70

Military

-65 to +150

Commercial

-55 to +125

°c
°c
°c
°c

MIN.

TYP.

MAX.

-4.9

-5.2

-5.5

V

UNIT

-4.9

-5.2

-5.5

V

VAGND

Analog Ground
Voltage (REF DGND )

-0.1

0

+0.1

V

VEEAVEED

Supply Voltage
Differential

-0.1

0

+0.1

V

V1CM

CONY. Common
Mode Range

-0.5

-2.5

V

V1DF

CONY, Differential
Range

0.4

1.2

V

V1L

Input Voltage,
Logic LOW

-1.49

-

-

V

"rH

Input Voltage.
Logic HIGH

-

-

-1.045

V

IREF

Reference Current,
Video Std.(1)
9-Blt Lin.

-

1.171
1.3

mA
rnA

TA

Ambient
Temperature

-55

-

125

0

-

70

°c
°c

Unlimited

TEMPERATURE

PARAMETER
Digital Supply Voltage
(REF DGND)
Analog Supply Voltage
(REF AGND)

I

MIL.

I COM'L.

1.059
1.0

1.115

NOTE:
1. Minimum and maximum values allowed by ±5% variation given in
RS-343A and RS-170 after initial gain correction of device.

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Absolute Maximum
Ratings are limiting values applied individually while a" other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to. speCified range.
4. Current is specified as conventional current when flowing into the
device.

11-15

IOT75C19 9-81T CMOS VIDEO DAC

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Specifications over the recommended operating conditions, unless otherwise stated.
SYMBOL

PARAMETERS

MAX.

UNIT

-

125

mA

Equivalent Input C,
REF (+), REF (-)

-

5

pF

CI

Input Capacitance,
Data & Controls

-

5

pF

Vocp

Compliance Voltage,
+ Output

-1.2

+0.1

V

VOCN

Compliance Voltage,
-Output

-1.2

+0.1

V

Ro

Equivalent Out R

20

-

kCl

Co

Equivalent Out C

-

20

pF

30

-

mA

IEEA+
IEED

Supply Current

C AEF

TEST CONDITIONS

MIN.

VEEA = VEEO = Max.l1l, Static

lop

Max. I, +Output

VEEA = Typ.,SYNC = BLANK= 0
FH = BRT = 1

ION

Max. I, -Output

VE EA = Typ., SYNC = 1

30

IlL

Input Current, Logic
LOW, Data & Controls

VEEO = Max.; VI = -1.40V

-

200

)JA

IIH

Input Current, Logic
HIGH, Data & Controls

VEEO = Max.; VI = -1.00V

-

200

)JA

IIC

Input Current, CONY

VEEO = Max.; -2.5 < VI < -0.5

-

50

)JA

IOT75C19 x 100
MIN.
MAX.

IDT75C19 x 125
MIN.
MAX.

mA

NOTE:
1. Worst case for all Data and Control States. No termination on 10uT+or 10UT-'

AC ELECTRICAL CHARACTERISTICS
Specifications over the recommended operating conditions unless otherwise stated
SYMBOL

PARAMETERS

TEST CONDITIONS

I DT75C19 x 70
MIN.
MAX.

UNIT

Fs

Max. Conversion Rate

VEEA ,VEEO = Min.

-

70

-

100

-

125

MHz

tpWL

CONY LOW Time

VEEA , VEEO = Min.

6

-

5

-

4

-

ns

tPWH

CONY HIGH Time

VEEA , VEEO = Min.

6

-

5

4

-

ns

ts

Set-up Time, Data & Control

8

5

1

-

0

-

ns

Hold Time, Data & Control

-

6

tH

VEEA ,VEEO = Min.
VEEA ,VEEO = Min.

-

tosc

CONY to OUT Delay

-

10

-

8

ns

DATA to OUT Delay

-

14

tosT

VEEA ' VEEO = Min. FT = 0
VEEA , VEEO = Min. FT = 1

20

-

16

-

13

ns

VEEA ,VEEO = Min. FT = 0
0.2%

-

-

3.0

-

-

10% to 90% of Full Scale

-

-

3.2%

-

ns

0.8%

1.7

ns

tSI

tAl

Current Setting Time

Current Rise Time

5

11-16

2.1

ns

ns
ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C19 9-BIT CMOS VIDEO DAC

SYSTEM PERFORMANCE CHARACTERISTICS
Specifications over the recommended operating conditions unless otherwise stated.
MIN.

MAX.

UNIT

ELI

LInearity Error Integral

VEEA • VEEO • I REF = Typ.

-

0.1

%FS

ELD

LInearity Error Differential

-

0.1

%FS

IOF

Output Offset I

VEEA • VEEO ' I REF = Typ.
VEEA • VEEO = Max. SYNC = BLANK = O.

-

±10

~

EG

Abs. Gain Error

-

±5

%FS

TCG

Gain Error Tempco

-

±0.024

%FSrC

BWR

Ref. Bandwidth -3dB

.D.V REF = 1mV

1

OP

Differential Phase

Fs= 4x NTSC

-

1.0

Oeg.

OG

Differential Gain

Fs= 4x NTSC

%

45

dB

PSRR

Power Supp. Rej. Ratio

-

2.0

VEEA • VEEO ' IREF = Typ.(l)
VEEA • VEEO • IREF = Typ.(2)

55

dB

PSS

Power Supp. Sensitivity

V EEA' V EEO' I REF = Typ.(3.4)

-

120

JjVN

GC

Peak Glitch Charge

Registered Mode Typ.

fc

Peak Glitch Current

Registered Mode

-

800

GI

1.2

mA
pV-Sec

SYMBOL

PARAMETERS

TEST CONDITIONS

FH = BRT = 1
VEEA • VEEO ' I REF = Typ.

MHz

GE

Peak Glitch Energy

Registered Mode Typ. (4)

-

30

FTc

Clock Feedthrough

Data Constant (5)

-

-50

dB

FTo

Data Feedthrough

Clock Constant (5)

-

-50

dB

NOTES:
1. 20kHz. ±0.3V ripple superimposed on VEEA • VEEO ; dB relative to full gray scale.
2. 60Hz. ±O.3V ripple superimposed on VEEA • VEEO ; dB relative to full gray scale.
3. feourombs
microamps x nanoseconds
4. 37.50 load. Because glitches tend to be symmetric. average glitch area approaches zero.
5. dB relative to full gray scale. 250MHz bandwidth limit.

=

11-17

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C19 9-BIT CMOS VIDEO DAC

tPWH

~~C-~-\~r=\c===\C=V==

~,'----'I~''----'I~I'
I
'----'I~',----''L
.

-.

.-ts--. . . .--- t

--I.

y_-r____

tPWL

1.-

CONV

H- .

V"*_____

DATA. CONTROL _ _ _ _

_-_-_-_-_-_-_-_-_-_-I_N-_p-_UT-_-S~-tO-ST-__+----'F

IIIIII-.....

OUT-

OUT+

1/2 LSB

.-tSI---t>

Figure 1. Timing DIagram

"'OF

__~--------x'"----- ';,~:~--------------------i _______________ ~~~~--~~~-----------------

V~"

""
"

""

"

o.OV

V1CM

-1.3V

~~:~~:-----"'\x:\,.______ ::

MAK ______________

Figure 2. CONVert, CONVert Switching Levels

11-18

MIN.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT75C19 9-BIT CMOS VIDEO DAC

CURRENT
SINK#N
r----------.,
.--------_Y '\I-t----<.._------+---O OUT +
. - - -_ _;..J

\,...A----t----1>----..&....--uOUT-

REFERENCE
AMPLIFIER

r-------.,
REF - 0--11----1

I

I

I

I
I
I

I

I
I

I
I
~;------+---------------------1----------VE~
I!.. _ _ _ _ _ _ _ J I!.. _ _ _
OJ

Figure 3. Equivalent Output Circuit

VIDEO
MONITOR
OUT-

IDT75C19

~750
r---~I
COAX I R
750 I
750
I L
I
I
I
1... _ _ _ _ .1
750

75Q~ 1 COAXG{75Q
TEST LOAD:
OUT+
OUT-

D--,---.---. VIDEO OUT
RL
37.50

OTO -1 VOLT

Figure 4. Standard Load Configuration

11-19

0

INVERSE

VIDEO

MILITARY AND COMMERCIAL TEMPERATURE RAN.GES

IDT75C19 9-BIT CMOS.VIDEO DAC

IRE

mV (REF Acmo)

o __

...... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

,...._;;;.BR~I..;..G;;.;H.;.T_

110

100

-73

--1------------------512 "GRAY LEVELS·

7.5

-728

o

-781

-40

.L___~~~~~(~LA.::~

___ _

--------------------L..----"""T"

-1071 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
SY_N_C_ _....... _ _ _ _ _ _ _ _ _

Figure 5. Video Output Waveform for Out- and Standard Load Configuration

11-20
........... _ ... _ . - . _ - - . _ - - _ .

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7SC19 9-81T CMOS VIDEO CAC

MSB

VIDEO
DATA
(ECl)

05

04

06

03

07
lSB
-5.2V

01

09

VEEA

-------1 CONV

AGNO

CONV

FT

-

L.. _ _ _ _ _ _

IREF

REF+
FH

R2
9000

T = ECl TERMINATION

VR1
lM313

SYNC
------{

J

REF-

BLANK
[

iGf

IDT7SC19

DGNO

(ECl)

VIDEO
MONITOR

I

C1

N/C

~g~~ROlS

r------,

our-

--------1

-5.2V

I
I

OUT+

VEEO

~
CONVert
CONVert

_~r""rl""'-.~-J

08

BRT

---------------~
-S.2V

PARTS LIST
RESISTORS
R1

1kO

Pot

R2

9000

1/8W

1% Metal Film

R3

2.00kO

1/8W

1% Metal Film

R4

37.50

1/8W

1% Metal Film

0.1~F

50V

Ceramic disc

10Tum

iii

CAPACITORS
C1-C3

INTEGRATED CIRCUITS
U1

IDT75C19

D/A Converter

VOLTAGE REFERENCES
VR1

lM113 or lM313

Bandgap Reference

INDUCTORS
l1

Ferrite Bead Shield Inductor Fair-Rite
PIN 2743001112 or Similar

Figure 6. Typical Interface Circuit

11-21

IDT75C19 9·BIT CMOS VIDEO DAC

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxxx

X

Device Type Power

X

x

X

Speed

Package

Process/
Temperature

Rany:LANK

'----------j

'---------------1

'------------------1

'----------------------1

11-22

Commercial (O°C to

+ 70° C)

Military (-55°C to + 125°C)
Compliant to MIL·STD·883. Class 8

TP
D
L

Plastic THINDIP
CERDIP
Leadless Chip Carrier

70
100
125

}

Speed in Megahertz

S

Standard Power

75C19

9·Bit CMOS Video DAC

FEATURES:

DESCRIPTION:

• Graphics Ready

The IDT75MB38 is a 70/100/125 MegaSample per Second
(MSPS), triple 8-bit Digital to Analog Converter capable of directly
driving a 750 load to standard video levels. Most applications
require no extra registering, buffering or deglitching. All inputs are
ECl-compatible and the part runs from a single -5.2V supply.
The IDT75MB38 is built using three IDT75C18 Video DACs in
small outline plastic packages, mounted on an epoxy laminate
(FR4) substrate. The module fits into a standard 40-pin DIP
(600 mil) footprint. Due to IDT's high-performance CEMOS TM
process, power consumption is kept under 1500mW.

• Pin-compatible with TDC1318 & BT109
• Triple 8-bit DACs, 1/2 lSB linearity
• 70/100/125MHz update rate
• ECl-compatible inputs
• low power consumption: 1500mW
• On-board voltage reference
• Complementary current outputs
• Registered SYNC, BLANK and OVERLAY inputs
• Surface mount packages on an epoxy laminate substrate

FUNCTIONAL BLOCK DIAGRAM

IOUTREO+

RED 0 0 - 7

lOUT REOGREEN DO-7

BLUE 0 0- 7

I OUT GREEN +
LATCH
I OUT GREEN-

CONV
SYNC
lOUT BLUE +
BLANK
lOUT BLUEOVERLAY

FSAOJUST

CEMOS is a trademark of Integrated Device Technology, Inc.

DECEMBER 1987

COMMERCIAL TEMPERATURE RANGE

DSC-5005/-

© 1987 Integrated Device Technology, Inc.

11-23

IDT75MB38 TRIPLE 8-BIT VIDEO DAC

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION

VEEA
FSADJ

NC
BLANK
OVERLAY
I OUT+ B
I OUT- B
I OUT+ R
I OUT- R
I OUT+ G
lOUT - G

SYNC
CONV
(G MSB) Dm

Doo
D5G
D4G
D3G
D2G

VCCA~_ _ _...J

DIP
TOP VIEW

GENERAL INFORMATION

DATA INPUTS

The IDT75MB38 is built using three monolithic Video DACs, a
voltage reference and an operational amplifier to control the fullscale output current. All devices are housed in plastic SOIC packages and are mounted on a multilayer FR4 substrate. Conventional
through-hole pins are attached for connection to the user's printed
circuit board.
The IDT75MB38 provides 24 data input pins (8 each for red, blue
and green) which are ECl-compatible. Data are latched on the rising edge of the clock input, CONV. In addition,three control signals are available which ease the interface to RS-343 systems.
The IDT75MB38 outputs three pairs of complementary analog
current signals which will directly drive the 750 inputs of a color
video CRT. The current produced by these outputs is directly proportional to the product of the digital input data and the reference
current.

The IDT75MB38 has 24 data inputs which are ECl-compatible
and have an internal pull-down resistor which forces unconnected
pins to their inactive state. Each DAC, red, green and blue, has 8
data inputs which are latched on the rising edge of the clock,
CONV. Data must be valid for a set-up time (ts) before and a hold
time (t H ) after this edge to be correctly latched.

POWER
The IDT75MB38 operates from separate analog and digital
supplies to provide the highest nOise immunity on the analog output to digital switching spikes. All power and ground pins must be
connected and properly decoupled.

SYMBOL

FUNCTION

D7
De
D5
D4
D3
D2
D1
Do

MSB

•
•
•
LSB

CONTROL INPUTS
The IDT75MB38 has three special control inputs, SYNC, BLANK
and OVERLAY, which ease the interface in video applications.
These inputs are ECl-compatible and have an internal pull-down
resistor which forces unconnected pins to their inactive state. The
controls, as the data inputs, are latched on the rising edge of clock.
The video controls produce specific output levels for RS-343
compatible synchronization and blanking. Also provided is a
110% white Overlay function. SYNC is only active on the lOG output and overrides all other data and control on that output only.
BLANK is active on all three DACs, overrides OVERLAY and data,
and produces a "blacker than black" level. OVERLAY produces a
"whiter than white" level and overrides data on all three DACs.

REFERENCE
The IDT75MB38 has an on-board voltage reference and associated circuitry which provides a bias voltage for the DAC current
switches and sets the full-scale current. Typically, a 1.1 K resistor is
connected between the FS Adjust pin and VCCA which provides the
reference current to the DACs.

11-24

COMMERCIAL TEMPERATURE RANGE

1DT75MB38 TRIPLE 8-BIT VIDEO DAC

CLOCK

ANALOG OUTPUTS

The clock input, CONV, is a single-ended, ECl-compatible input. On the rising edge of CONV, all data and control inputs are
latched provided that they were valid for a set-up time before and a
hold time after the edge.

The IDT75MB38 has three complementary current outputs corresponding to the red, green and blue DACs. These outputs are
high-impedance current sinks which can directly drive a doubly
terminated 750 load to video levels compatible with the RS-343A
standard. The output current is proportional to the product of the
DAC input data and the reference current set on the FS Adj pin.

VIDEO OUTPUT VALUES (4)
VOUT _(3)mV

VOU T+(3)mV

SYNC

BLANK

OVERLAY

DATA

louT_(2)mA

110% White

0

0

1

X

0.00

0.00

28.56

-1071

Reference White

0

0

0

FF

1.95

-73

26.61

-998

Reference Black

0

0

0

00

19.41

-728

9.15

-343

Blank

0

1

X

X

20.83

-781

7.73

-290

Sync(l)

1

X

X

X

28.56

-1071

0

0

DESCRIPTION

IOUT+(2)mA

NOTES:
1. lOG output only. lOR and 108 have no SYNC input.
2. Current is specified as conventional current when flowing into the device.
3. Voltage produced when driving the standard load configuration. 37.50.
4. RS-343A tolerance on all control values assumed.

IRE

mV (REF VCCA )

110

o

100

-73

7.5

-728

o

-40

_ _.;,.O.;.VE~R.;.;LA;..;.;.Y_.,.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
NORMAL HIGH (WHITE)

-781 -------------------~----~

-1071 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

SYNC
(Green Output only)
.....-----~- - - - - - - -

Figure 1. Video Output Waveform for Out- and Standard Load Configuration

11-25

--

COMMERCIAL TEMPERATURE RANGE

1DT75MB38 TRIPLE 8·BIT VIDEO DAC

VIDEO
MONITOR

r----~~.2.!:~_~!C7~50~=rQ- - - ~"I
750 I
I

I

1DT75MB38

~~~--~~--~--4----o0 INVERSE

'-------'

VIDEO

TEST LOAD:
OUT+

RL

OUT-

37.50

~= V

CCA

Figure 2. Standard Load Configuration

r=\
tr=='J
c-\
1\
=---;
CJ.
~I
~L

__I 'PM 1-

CONV

+--ts-'I~4f---- t H - .

----y_-+-_~~~~~~_D_A_TA_._C_O_N_TR_O_L_-_-=-=:;t\

___

INPUTS

~_~"*_ _ _ __
~

_-_-_-

our
OUT+
1/2 LSB

~tSI---+

Figure 3. Timing Diagram

11-26

__...... _--._ ........ _.__

.

. -....

_._-------------

COMMERCIAL TEMPERATURE RANGE

1DT75MB38 TRIPLE 8-BIT VIDEO DAC

. CURRENT
SINK#N

r----------.,

...--_ _ _ _ _+' \,-+----..-------+---00UT+

REFERENCE
AMPLIFIER
r-------.,

I
To Internal
Voltage
Reference
1.25V Nom.
(Ref VCCA )

I

I

I
I
I

I

I

I

I

IL

I
_ _ _ _ _ _ _ .J

IL

~~-----*-----------~---------VE~

___

.J

Figure 4. Equivalent Output Circuit

III

11-27

COMMERCIAL TEMPERATURE RANGE

1DT75MB38 TRIPLE 8·BIT VIDEO DAC

ORDERING INFORMATION
lOT

xxxx
X
Device Type Power

X

X

Package

Process!
Temperature
Range

-----II

1
...

'-----------i

BLANK

Commercial (O°C to

P

Plastic DIP (Module)

'--------------1 70
100

}

+ 70° C)

Speed in Megahertz

125
S

Standard Power

75MB38

Triple 8-Bit Video DAC Module

11-28
._. __ ... _ - - - -

•.

_ - - - _.•__. _ - - -

FEATURES:

DESCRIPTION:

• 125/110/80MHz operating speed
• Fixed pipeline delay: 8 clock cycles

The IDT75C458 is a triple 8-bit video DAC with on-chip, dualported color palette memory. This chip is specifically designed for
the display of high resolution color graphics. The architecture
eliminates the ECl pixel interface by providing multiple TTl-compatible pixel ports and by multiplexing the pixel data on-chip.
The IDT75C458 supports up to 259 simultaneous colors from a
palette of 16.8 million. Other features included on-chip are programmable blink rates, bit plane masking and blinking as well as a
color overlay capability. The IDT75C458 generates RS-343A compatible red, green, and blue video outputs which are capable of directly driving a doubly terminated 750 coaxial cable.
The IDT75C458 military DACs are manufactured in compliance
with the latest revision of Mll-STD-883, Class B, making them ideally suited to military temperature applications demanding the
highest level of performance and reliability.

• Triple 8-bit DACs
• Integral and differential linearity < 1/2lSB
• 256 x 24 Dual-Ported Color Palette RAM
• 4 x 24 Dual-Ported Overlay Palette RAM
• Multiplexed TTL pixel and overlay inputs
• RS-343A compatible RGB outputs
• Universal 8-bit MPU interface
• CEMOS 1M monolithic construction
• Single 5V power supply
• 84-pin ceramic and plastic PGA package
• Typical power dissipation: 1OQOmW
• Pin- and function-compatible with Brooktree BT458
• Military product is compliant to Mll-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
a:R

ClK

VREF

FSADJ

~------f--

COMP

R

III

E
A

LATCH

D

OLo-Ol1 {A-E}

S'7NC --+----1.,.
BLINK REG

t3CAN1< --+---.1

READ REG
TEST REG
ADDR REG
COMM REG

co

C1 R/W

cr

CEMOS and PaletteDAC are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-5002J-

1987 Integrated DevIce Technology. Inc.

11-29

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PAlETTEDAC ™

PIN CONFIGURATIONS
A

12

B

COMP AGND

G

C

D

E

F

VAA

P 7{D}

P 7{B}

P6{E}

P 7{E} P 7{C}

11

10e

AGND

VAA

10

lOG

FSADJ

VREF

9

VAA

10

8

C1

R/W

7

VAA

CO

H

P6 {C} P6{B}

P7{A} P6{D}

J

Ps{E}

K

l

Ps{C} Ps{B}

P6{A} Ps{D} Ps{A}

M

P4{E}

P4 {C} P4 {A}

P4 {D} P4{B} SYf\JC

'BLANK

05

CIT

ClK

VAA

VAA

CONSULT FACTORY
FOR PACKAGE INFO
6

AGND

AGND

P3 {E}

AGND

5

a:-

D7

P3 {C}

P3 {D}

4

D6

Ds

P3 {A}

P3 {B}

3

D4

D2

Pz{A}

P2 {C}

PdE}

2

D3

Dl

Po{D} PI {A} PI {D}

P1 {E}

P2 {D}

Po{C}

PI {C}

P2 {B}

6. ALIGNMENT MARK

Do
Olo{B} Olo{E} Oll {B} Oll {E} Po{B}

Olo{A} Olo{C} Olo{D} Oll {A} Oll {C} Oll {D} Po {A}

Po{E} PI {B}

PGA
TOP VIEW

GENERAL INFORMATION:
The IDT75C458 triple 8-bit PaietteDAC is a highly integrated
building block which interfaces a relatively low bandwidth frame
buffer memory to an analog RS-343A, high bandwidth output. To
decrease the frame buffer memory requirements, the IDT75C458
has a color lookup table (dual-port RAM) included on-chip.The basic functional blocks are the microprocessor bus interface, the
frame buffer memory interface and multiplexer, a dual-port RAM
with one R/W port and one high-speed R/O port and three 8-bit
video speed DACs.

An access to a control register requires writing a 4 through 7 into
the address register (CO =C1 =0) and then writing or reading data
to the selected register (CO = 0, C1 = 1). When accessing the control registers, the address register is not changed, facilitating readmodify-write operations. If an invalid address is loaded into the
address register, data written is ignored or invalid data is read out.
It is also possible to access the color palette information. The
palette is organized as 256 addresses with 8 bits of red, blue and
green information. Additionally, there are four extra addresses
assigned to overlay information, yielding a total memory size of
260 x 24.
Access to the palette entries is, again, through the address register. The desired palette address is loaded into the address register, CO and C1 are modified to point to the color palette or overlay
and the information is read or written. In this case, however, an
internal counter is used to access the red, green or blue color information. The first color palette or overlay access reads or writes red.
The next access is for green, while the third access is for blue. After
the third access, the address register is incremented, allowing the
reading or writing of the red information of the next palette address.
When writing, red and green information is temporarily stored in
registers and, during the blue cycle, all 24 bits are written.

MICROPROCESSOR BUS INTERFACE
The IDT75C458 supports a standard microprocessor bus interface, allowing the MPU direct access to the internal control registers and color/overlay palettes. The dual-port .color palette RAM
and overlay registers allow color updating without contention with
the display refresh process.
The bus interface consists of eight bidirectional data pins,
Do - 0 7 , with two control inputs, CO and C1, a read/write direction
input, R/W, and a clock input, CE . A.!!9ata and control information
are latched on the falling edge of CE, as shown in Figure 1. All
accesses to the chip are controlled by the data in the address
register combined with the control inputs CO, C1 and R/W,
depicted in the Truth Table (Table 1).

11-30

JDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The multiplexing factor, 4:1 or 5:1, is programmable from the
command register, bit l.ln the 4:1 mode, the {E} color and overlay
inputs are not used and the lD clock should be CLOCK divided by
4. The {E} color and overlay inputs must be connected to a valid
logic level.
The overlay inputs (Olo - all) have the same timing as the pixel
inputs (Po - P7).It is possible to use additional bit planes or external
logic to control the overlay selection for cursor generation.

The internal counter is reset by an access to the address or any
of the control registers. After setting the address register, it is possible to read or write the entire palette without accessing the address
register again. Some care is needed; only continuous reads or
writes are allowed and it is not possible to switch between the color
palette and overlay.
The color palette RAM and overlay registers are dual-ported
which allows simultaneous access from the MPU port (Do - D7)
and the pixel port (Po - P7 {A-E}). If the pixel port is reading the
same palette entry as the MPU is writing, it is possible that the DAC
output may be invalid. It is recommended that the palette and overlay entries be updated during the blanking time.
ADDRESS REGISTER
DATA

X
$OO-$FF
$00
$01
$02
$03
$04
$05
$06
$07

C1

CO

0
0
1
1
1
1
1
1
1
1

0
1
1
1
1
1
0
0
0
0

INTERNAL MULTIPLEXING
lD is typically ClK divided by four or five and it latches color
and overlay information on every rising edge, independent of ClK.
A digital Pll allows lD to be phase inde~ndent of ClK. The only
restriction is that only one riSing edge of lD is allowed to occur per
four (4:1 multiplexing) or five (5:1 multiplexing) ClK cycles.

ACCESS
Address Register
Color Palette
Overlay Color 0
Overlay Color 1
Overlay Color 2
Overlay Color 3
Read Mask Register
Blink Mask Register
Command Register
Test Register

Color Palette
On the riSing edge of each ClK cycle, eight bits of color information (Po - P7) and two bits of overlay information (Olo - Oll ) for
each pixel are processed by the read mask, blink mask and command registers. This information provides the address to the dualport color palette RAM. Note that Po is the lSB when addressing
the color palette RAM. The value stored at a selected address
determines the displayed color. In this way, 8 bits of information
can select from a palette of over 16 million with 256 simultaneous
displayed colors (plus 3 overlay colors). Through the use of the
control register, individual bit planes may be enabled or disabled
for display and/or blinked at one of four blink rates and duty cycles.
The blink timing is based on vertical retrace intervals which are
defined by at least 256 lD cycles since the last falling edge of
BLANK. The color changes during this normally blanked time.
The processed pixel data is then used to select which color palette entry or overlay register is used to provide color information.
Table 2 illustrates the truth table used for color selection.

NOTE:
Control input CO = 1 enables the internal counter which accesses the red,
green and blue colors individually and increments the address counter
after the blue access. CO = 0 disables auto-increment of the address
register allowing read-modify-write operations.
Table 1. Truth Table for MPU Operations

FRAME BUFFER INTERFACE
The frame buffer interface consists of five 8-bit input ports which
correspond to five consecutive pixels. In addition, there are two
extra bits per port which may be used for overlay information. To
reduce the bandwidth requirements for the pixel data, the
IDT75C458 latches 4 or 5 pixels (the multiplex factor is
programmable..!Q. 4 or 5 by bit 1 of the command register) on each
rising edge of lD. The color and overlay information is internally
multiplexed at the pixel clock frequency, ClK, and sequentially
output. This arrangement allows pixel data to be transferred at a
rate 4 or 5 times slower than the pixel clock. Typically, lD is the
pixel clock divided by 4 or 5 and is used to clock data out of the
frame buffer memory.
As shown in Figure 2, sync, blank, color and overlay information
are latched on the rising edge of lD . Up to 40 bits of color information are input through Po - P7 {A-E} and up to 10 bits of overlay
information are input through Olo - all {A-E}. Both sync and
blank have separate inputs, SYNC and BLANK, respectively. The
IDT75C458 outputs color information on each clock cycle. Four or
five pixels are output sequentially, beginning with the {A} information, then the {B} information, until the cycle is completed with the
{D} or {E} information. In this configuration, sync and blank times
are limited to multiples of four or five clock cycles.

CR6

OL 1

OLo

P7 - Po

1
1

0
0

0
0

$00
$01

Color palette entry $00
Color palette entry $01

1
0

0
0
0
1
1

0
0
1
0
1

$FF
$xx
$xx
$xx
$xx

Color palette entry $FF
Overlay color 0
Overlay color 1
Overlay color 2
Overlay color 3

x
x
x

PALETTE ENTRY

NOTE:
CR6 is bit 6 of the Command Register.
Table 2. Palette and Overlay Select

11-31

iii

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC TM

Video Generation, DACs

Monitor Interface

On every ClK cycle, the selected 24 bits of color information
(8 bits each of red, green and blue) from the Color Palette RAM are
presented to the three 8-bit OJA converters. The I0T75C458 uses a
5 x 3 segmented approach where the four MSBs of the input data
are decoded into a parallel "Thermometer" code which produces
thirty two "course" output levels. The remaining three lSBs of input
data drive eight binary weighted current switches with a total contribution of one-thirty second of full scale. The MSB and lSB currents are summed at the output to produce 256 levels.
The SYNC and BLANK inputs are plpelined to maintained synchronization with the pixel data. Both inputs drive appropriately
weighted current switches which are summed at the output of the
OACs to produce the specific output levels required by RS-343, as
shown in Figure 3. Note that the sync information is only available
at the lOG (green) output and that the input data to the OAC sums
with the syn~nt. Table 3 details the output levels associated
with SYNC, BLANK and data.

The analog outputs of the I0T75C458 are high-Impedance current sources which are capable of directly driving a doubly terminated 750 coaxial cable to standard video levels. A typical output
circuit is shown in Figure 3.

Description

S

B

WHITE
DATA
DATA & SYNC
BLACK
BLACK & SYNC
BLANK
SYNC

1
1
0
1
0
1
0

1
1
1
1
1
0
0

DAe
data

100 (rnA)

lOR. lOB

$FF
data
data
$0
$0

26.67
data + 9.05
data + 1.44
9.05
1.44
7.62
0

19.05
data + 1.44
data + 1.44
1.44
1.44
0
0

X
X

(rnA)

NOTE:
Typical values with full scale lOG = 26.67mA. RSET = 5230,
VREF = 1.235V. S is S'Y'NC, B is m:ANK.

Table 3. Video Output Truth Table

100

IOR,IO B
mA

V

mA

V

19.05

0.714

26.67

1.000

···

···

··
·

··
·

NORMAL HIGH (WHITE)

1.44

9.954

9.05

0.340

0.00

0.000

7.62

0.286

0.00

0.000

--r----------------256 "GRAY LEVELS"

j

NORMAL LOW (BLACK)

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ......._ _ _--11-

Figure 1. Composite Video Output Waveform

Figure 2. Pixel Timing

11-32

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

I

\

ts

I
R/W
CO,C1

HAUHU

I

tH

I
I

...

XX

XX XX

i'-- HI-Z TO DATA BUS DRIVEN
CHIP ENABLE TO DATA VALID

""-"-

"

1./////////////

DATA VALID

' \"-'\
"-"-'\'\'\'\
L

ts

I
XX

xxx

H

XH X

XX XI

-,

XXI

,UHI X .XXX

Xl UHX

CHIP DISABLE TO HI-Z

/
tH-1

IXXXXXXXXX XXXXXXX XX XX XXXX XXX XXX X

I

Figure 3. Data Bus Timing

COMP

VAA

+5.0V

VREF
33)JF

O.1)JF

IDT75C458
OV

VGND

FSADJ
RSET

lOB

VIDEO OUT

lOG

Figure 4. Typical Application

11-33

m

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

PIN DESCRIPTIONS
DESCRIPTION

PIN NAME
DATA BUS
Do - D7

8-bit, bidirectional data bus. Data is input and output over this bus and the flow is controlled by RtW and CE:. D7 is the most significant
bit.

CE:

Chip Enable input. The chip is enabled when this control pin is LOW. During a write cycle (RtW lOW), the data present on Do - D7 is
internally latched on the lOW-to-HIGH transition of this pin.

cr

Read/Write Control input. The Read/Write input is latched on the HIGH-to-lOW transition of
and determines the direction of the
bidirectional data bus Do - D .lf R!Wis HIGH during the falling edgeofCE, a read cycle occurs. If R/VVis lOW during the falling edge of
D7 are latched on the rising edge of

R!W

7
cr, a write cycle occurs and,
additionally, Do CO,C1

cr.

Register Control inputs. CO and C1 determine which register or palette entry is accessed during a read or write cycle. These inputs are
latched on the HIGH-to-lOW transition of

cr.

PIXEL
ClK,

CIJ<

Pixel Clock inputs. These inputs are differential and may be driven by ECl operating from a
normally the system pixel clock rate.

+ 5V supply. The clock frequency is

B5

W

load Clock Input. The load Clock is normally ClK divided by 4 or 5 (determined by the Control Register, bit
The pixel data, Po - P7
{A-E} and Olo - Ol, {A-E}, 'E3CAfiiR and SY'NC are internally latched on the lOW-to-HIGH transition of D.

Po - P7 {A-E}

Pixel Input Data. These inputs provide the address input to the color palette RAM. The data stored at a particular address is the color
output by the DAC. Four or five consecutive pixels, as determined by bit 7 in the Command Register, are internally latched on the lOWto-HIGH transition of W. The pixels are output sequentially, first {A} then {B}. After all four or five pixels have been output, the cycle
repeats. Unused inputs must be connected to a valid logic level.

Olo - Ol, {A-E}

Pixel Overlay Inputs. The Overlay inputs have the same timing as Po - P7 and select between either the color palette or the overlay
palette. When the overlay palette is selected, the pixel information Po - P, {A-E} is ignored. Bit 6 of the command register determines if
Overlay =0 displays overlay color 0 or the color palette entry. See Table 2 for details.

ffi:ANR

Composite Blank Input. A lOW on this input forces the analog outputs (lOR' lOG' lOB) to the blanking level. The m:ANR input is
internally latched on the lOW-to-HIGH transition of W. This input overrides all other pixel information.

S?NC

CompOSite Sync Input. A lOW on this Input subtracts approximately 7mA from the lOG analog output and overrides no other pixel
information. For the correct SYNC level, this input should be lOW only when m:Af\IR is also lOW. The ~ inputis internally latched
on the lOW-to-HIGH transition of ill.

ANALOG
AGND
VAA
V REF
FSAD

Analog Ground Power Supply, OV.
Analog Power Supply, 5V.
Voltage Reference Input, 1.235V. This input supplies a reference voltage for the DAC circuitry. Care must be taken to correctly decouple
this voltage because noise on this pin will couple directly to the DAC outputs.
Full-Scale Adjust Input. The current flowing from this pin to AGND is directly proportional to the full-scale analog output current Normally, a resistor is connected between this pin and AGND . The voltage on this pin is approximately equal to V REF' The relationship
between the full-scale output current and RSET is:
lOG (mA) = 11.294 x VREF M/RSET (KO)
lOR, lOB (mA) = 8.067 x VREF M/RSET (KO)

lOG' lOR' lOB

Green, Red and Blue DAC current outputs.

COMP

Compensation Input. This pin provides the ability

to compensate the internal reference operational amplifier.

11-34

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC Thl

MILITARYANDCOMMERCIAL TEMPERATURE RANGES

INTERNAL REGISTERS
Command Register

Read Mask Register

The Command Register is accessed by reading or writing with
the Address Register = $06, CO = 0 and C1 = 1 (see Table 1). It provides control over multiplexing and blink rate selection. The Command Register may be read or written at any time. CR7 (Command
Register bit 7) corresponds to D7 (Data Bus bit 7).

The Read Mask Register is accessed by reading or writing with
the Address Register=$04, CO=O and C1 = 1 (see Table 1). It
internally ANDs the pixel information with a bit from the register
before the color palette selection, effectively enabling (HIGH) or
disabling (lOW) the entire pixel plane. The Read Mask Register
may be read or written at any time. RMR7 (Read Mask Register
bit 7) corresponds to D7 (Data Bus bit 7).

CRO

Olodisplayenable. This bit isANDed internally with
the data from Olo prior to the palette selection. If
CRO is lOW, the internal ala bits are set lOWallowing only overlay colors 0 and 2 to be selected.

CR1

Ol1 display enable. This bit isANDed internally with
the data from Ol1 prior to the palette selection. If
CR1 is lOW, the internal Ol1 bits are set lOWallowing only overlay colors 0 and 1 to be selected.

CR2

Olo blink enable. If this bit is set HIGH, the Olo bit is
internally switched between the value input and 0 at
the rate specified by the CR4 and CR5 bits. CRO
must be set HIGH for this function.

CR3

Blink Mask Register
The Blink Mask Register is accessed by reading or writing with
the Address Register = $05, CO = 0 and C1 = 1 (see Table 1). Each
register bit causes the corresponding pixel bit (Po - P7 ) to internally
switch between the input value and 0 at the blink rate specified in
the Command Register. For this function to work, the corresponding enable bit in the Read Mask Register must be set HIGH. The
Blink Mask Register may be read or written at any time. BMR7
(Blink Mask Register bit 7) corresponds to D7 (Data Bus bit 7).

Test Register
The Test Register is accessed by reading or writing with the
Address Register = $07, CO=O and C1 = 1 (see Table 1). This
register allows the MPU to read the 24 input bits of the DACs. The
register bits are defined below.

Ol1 blink enable. If this bit is set HIGH, the Ol1 bit is
internally switched between the value input and 0 at
the rate specified by the CR4 and CR5 bits. CR1
must be set HIGH for this function.

CR4, CR5

Blink Rate Select. These bits select blink rates based
on Vertical Sync cycles, defined as more than 256
LD cycles during BLANK.

CR6

Color Palette RAM enable. This bit specifies whether
to use the Color Palette or the Overlay Palette when
OLo = Ol1 = lOW.

CR7

Multiplex Select. This bit selects between 4:1
(CR7=0) or 5:1 (CR7= 1) multiplexing. When using
4:1 multiplexing, the {E} inputs are never used and
must be connected to a valid logic level.

CR7

CR6

CR5

CR4

CR3

CR2

TR7-TR4
TR3
TR2
TR1
TRO

Read data (one nibble of red, blue or green)
Upper (lOW) or lower (HIGH) nibble select
Blue enable
Green enable
Red enable

The desired DAC is selected by setting only one color enable bit
(Do - D2 ) HIGH and the upper or lower nibble is selected with D3 .
After this write operation, a subsequent read yields the DAC data
on D7 - D4 and the previously written enable data on Do - D3 . For a
correct read, pixel and overlay data must remain constant for the
entire MPU read cycle. When BLANK is asserted, the Test Register
information D7 - D4 will be forced to zero. TR7 (Test Register bit 7)
corresponds to D7 (Data Bus bit 7).

C~R1
i~

0 d;",ble OLo

1 enable Olo
o disable Ol1
1 enable all

'--_ _ _ _ _ _ _ _- ; 0 blinking of OLo disabled
1 blinking of Olo enabled
o blinking of Ol1 disabled
' - - - - - - - - - - - - - - - ; 1 blinking of Ol1 enabled

'--------------------1

0016 Vsync on /48 Vsync off
01 16 Vsync on /16 Vsync off
10 32 Vsync on /32 Vsync off
11 64 Vsync on /64 Vsync off

'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 0 Use overlay color 0
1 Use color palette 0

'----------------------------1

COMMAND REGISTER DESIGNATIONS

11-35

04:1 Multiplex
1 5:1 Multiplex

m

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

MR7

RMR6

MRS

RMR4

RMR3

RMR2

TAr :::=~
1 enable P1

'------------1 01 disable
P2
enable P
2

'---------------i 01 enable
disable P3
P
3

1--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _...,0

disable P
4
1 enable P4

L..---------------------i

0 disable P5
1 enable P5

L..------------------------i

0 disable Pe
1 enable Pe

'-----------------------------4 01 enable
disable P
P

7

7

READ MASK REGISTER DESIGNATIONS

BMR7

BMR6

MRS

BMR4

BMR3

BMR2

BMR1

BMRO

I

I

:~ ~~:~ ~~ ~:~~~g

o disable P1 blinking
1 enable P1 blinking

L..-----------i 0 disable P2 blinking
1 enable P2 blinking

'---------------i

0 disable P3 blinking
1 enable P3 blinking

L..-__________ ____...,O disable P4
~

L..----------------------4

blinking
1 enable P4 blinking

0 disable P5 blinking
1 enable P5 blinking

'-------------------------1 01 disable
Pe blinking
enable Pe blinking
L..-_________________________--I

BLINK MASK REGISTER DESIGNATIONS

11-36

0 disable P blinking
7
1 enable P7 blinking

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC TM

ABSOLUTE MAXIMUM RATINGS
SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(1)

RATING

VALUE

UNIT

POWER SUPPLIES
VAA

Measured to AGND

-0.5 to +7.0

V

Measured to AGND

-0.5V to VAA + 05

V

Measured to AGND

INPUT VOLTAGE
Applied Voltage(2)
OUTPUT
Applied Voltage(2)

-0.5V to VAA + 05

V

Applied Current(2.3.4) Extemally forced

-1.0 to +6.0

mA

Short
Circuit Duration

1.0

S

Single output
High to AGND

TEMPERATURE
Operating.
Ambient
Storage

Military

-55 to +125

Commercial

Oto +70

Military

-65 to +150

Commercial

-55 to +125

°c
°c
°c
°c

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect reliability. Absolute Maximum Ratings are limiting values applied individually while all other
parameters are within specified operating conditions. Functional
operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the
device.

iii

11-37

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

DC ELECTRICAL CHARACTERISTICS
SYMBOL

TEST CONDITIONS

PARAMETER

UNIT

MIN.

TYP.

MAX.

4.75

5.0

5.25

V

-

200

-

mA

VM +0.5

V

0.8

V

VM

Power Supply

Measured to VGND

1M
V (I)
IH
V (I)
IL

Power Supply Current

VM

Input Voltage HIGH

2.0

Input Voltage LOW

AGND -0.5

VCIH

Clock Input Voltage HIGH

VM -1.0

VCIL

Clock Input Voltage lOW

A GND -0.5

-

-

-

-

-

-

0.4

V

-

-

10

J.lA

IIH

Input Current HIGH

\'IN

IlL

Input Current lOW

\'IN

VOH

Output Voltage HIGH

VM

VOL

Output Voltage lOW

VM

loz

= Typ.

= 2.4V
= 0.8V
= Min., 10H = -800J.lA
= Min., 10L = 6.4mA

2.4

Output 3-State Current

NOTE:
1. All digital inputs except ClK and

VM +0.5

V

VM -1.6
1

V
J.lA

1

J.lA

-

V

CD<.

AC ELECTRICAL CHARACTERISTICS
Following conditions apply unless otherwise specified:
TA = O°C to + 70°C (Commercial Temperature Range)
TA = -55°C to + 125°C (Military Temperature Range)
VM =5.0V ±5%
TTL Inputs, VIL = 0.8V, ViH = 2.0V, rise/fall time < 5ns
ClK Inputs, VIH = VM -1.0V, ViL =VM -1.6V, rise/fall time <2ns
Timing reference pOints at 50% of signal swing
IDT75C458-125
SYMBOL

PARAMETER

MAX.

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

UNIT

-

125

-

-

110

MHz

28

-

80

-

-

20

MHz

-

125

-

ns

-

0

-

ns

-

15

-

-

-

25

-

ns

-

10

-

-

75

-

-

100

ns

15

-

15

ns

-

50

-

ns

5

-

1.6

-

-

2.0

ns

-

50

-

ns

-

20

-

20

-

-

ns

-

ns

Clock Frequency

FLO

ill Clock

tMPUCY

MPU Cycle Time

tcs

Control Set-up Time

0

-

tCH

Control Hold Time

15

-

cr HIGH Time

25

ct: to

10

-

tCEH
t CEZO

Data Bus Driven

100

32

-

110

-

10

75

-

15

-

0
15
25

cr to Data Valid
cr to Data Bus HI-Z

-

twos

Write Data Set-up Time

35

-

-

40

tWDH

Write Data Hold Time

0

Clock Cycle Time

8

tCLKPL

Clock Pulse Width lOW

3.2

tCLKPH

Clock Pulse Width HIGH

3.2

-

0

tCLKCY

-

tCLKT

Clock Transition Time

-

-

1.6

-

t LOCY

[j) Cycle Time

32

-

36

t LOPH

[J) Pulse Width HIGH

13

-

-

15

-

t LDPL

m Pulse Width lOW

13

-

15

-

tps

Pixel Data Set-up Time

3

4

tpH

Pixel Data Hold Time

2

-

-

-

tCED
t cEoZ

IDT75C458-80

TYP.

FCLK

Frequency

IDT75C458-110

MIN.

-

11-38

9
4
4

2

-

0
12
5

4
2

ns

ns

ns
ns
ns
ns

ns
ns

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ANALOG OUTPUT DC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

MIN.

TEST CONDITIONS

TYP.

MAX.

UNIT

Res

Resolution

-

8

LSB Current Size

-

69.1

-

bits

I LSS
LI

Integral Linearity

-

1/2

±1

LSB

-

1/2

±1

LSB

10

50

}JA

-1.0

-

1.2

V

-

2

5

%

Lo

Differential Linearity

10

Offset Error

Vcc

Output Compliance Voltage

EM

Matching Error (DAC to DAC)

}JA

-

50

-

dB

Measured to BLANK

17.69

19.05

20.40

mA

White Current

Measured to BLACK

16.74

17.62

18.50

mA

Black Current

Measured to BLANK

0.95

1.44

1.90

mA

-

0

-

mA

Blank Current lOG

6.29

7.62

8.96

mA

Sync Current lOG

-

0

-

mA

PSRR

Power Supply Rejection Ratio

Iw(1)

White Current

Iw(1)
IS(l)
ISIJINK
I SIJINK (1)

Blank Current lOR' lOs

I SYNC

NOTE:
1. RSET =523Cl. VREF =1.235V

ANALOG OUTPUT AC ELECTRICAL CHARACTERISTICS
Following conditions apply unless otherwise specified:
TA=O°Cto +70°C (Commercial Temperature Range)
TA = -55°C to + 125°C (Military Temperature Range)
VAA = 5.0V ±5%
TTL Inputs, V1L =0.8V, V1H =2.0V, rise/fall time <5ns
CLK Inputs, '-"H= VAA -1.0V, '-"L =VAA -1.6V, rise/fall time <2ns
Timing reference points at 50% of signal swing
IDT75C458-125
SYMBOL

PARAMETER

IDT75C458-110

IDT75C458-80

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

Mitt

TYP.

MAX.

UNIT

-

110

-

80

MHz

5

-

-

5

-

ns

FCLK

Clock Frequency

-

-

125

tvo

Video Output Delay Time

-

5

-

-

tvr

Video Output Transition Time

2

-

-

2

-

-

2

-

ns

ts

Video Output Skew (1)

-

0

2

-

0

2

-

0

2

ns

tSI

Video Output Settling Time

-

8

-

ns

50

-

12

-

-

50

-

Crosstalk. DAC to DAC

-

50

CT

100

-

100

-

-

100

-

pV-s

Glitch Energy

-

50

GE

-

-

Clock and Data Feedthrough

-

10

FT

pV-s

tvp

Pipeline Delay

8

-

8

8

-

8

8

-

8

clock

NOTE:
1. C L =10pF. 10%-90% points

11-39

50

50

pV-s

1DT15C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 5. Video I/O Timing Diagram

tMPUCY
tCEH

tcs
tCH

CO.C1

XXXI XX XX

R/W

IIIIIII

:1

L

I

I

1

:11 III I

1

1

1

xx

1

II II

twos

I

xx

xx

I

t WOH

1

1

II

II

xx

1

III

.1

.1

II I

UXXH

.XXXXXHXXXI.

.1.

II II II

I

"1

I

I

I

II I

I

II

I

Figure 6. MPU WRITE Timing Diagram

tMPUCY
tCEH

tcs
tCH

CO.C1

:XXXXXXXXXXXX XX

II II I

R/W

I

I

.XXXXXX

:XXXXXXXXXXXX XX XXXXX XXXI XXXXX X1

.-

t CEO -

~tCEOZ'-

. tCEZO

"

/////////////
'\.'\'\'\'\'\'\'\'\'\'\'\,

/

Figure 7. MPU READ Timing Diagram

11-40

I

I

UXXXXXXXXXXX

.II.XX II II

II

IDT75C458 CMOS TRIPLE 8-BIT PALETTEDAC ™

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

DeV~ype

X

X

X

x

Power

Speed

Package

Process!
Temperature
Range

Y:LANK

~--------------4G

'----------------1

~~O }

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883. Class B
Pin Grid Array

Speed in Megahertz

125

'-----------------~S

L---------------------------------------475C458

Standard Power
Triple 8-bit PaietteDAC TM

iii

11-41

FEATURES:

DESCRIPTION:

• 8-bit resolution

The IDT75C48 is a 20 MegaSample per Second (MSPS), fully
parallel, 8-bit Flash Analog to Digital Converter. The wide input
analog bandwidth of 7MHz permits the conversion of analog input
signals with full-power frequency components up to this limit with
no input sample and hold. Low power consumption, due to
CEMOS TM processing, virtually eliminates thermal considerations. The IDT75C48 is available in 28-pin plastic and hermetic
DIPs and a 28-pin LCC.
The IDT75C48 consists of a reference voltage generator, 255
comparators, encoding and EDC (Error Detection and Correction)
logic and an output data register. A single clock starts the conversion process and controls all internal operations. Two control inputs allow the output coding format to be programmed for straight
binary or offset two's complement in either the true or inverted
form.
The IDT75C48 military Flash NO Converters are manufactured
in compliance with the latest revision of MIL-STD-883, Class B,
making them ideally suited to military temperature applications
demanding the highest level of performance and reliability.

• 20 MSPS conversion rate
• Pin- and function-compatible with TRW 1048
• Low power consumption: 500mW
• Extended analog input range
• On-chip EDC (Error Detection and Correction)
• Improved output logic HIGH drive, no pull-up needed
• No sample and hold required
• Differential Phase < 1 Degree
• Differential Gain < 2%
• 1/2 LSB linearity
• Selectable output formats
• TTL-compatible
• Available in 28-pin Plastic DIP, CERDIP and LCC
• Military product Is compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
NMINV
NLiNV
VIN

CONY

1

RT

~r=10
V
>-~r;-...
V

R1
R
R

R

~

>-~

R/2

255 TO 8
ENCODE
+EDC

RM
R/2

>-~

--..

LATCH

r-.-

R

R

>-~

R

~

R2
RB

255 DIFFERENTIAl,.
COMPARATORS

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
OSC-5003/-

11-42

IDT75C48 FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES
(j)

PIN CONFIGURATIONS

m>

:::2

NMINV

O2

RM

03

RB
AGND
VIN
VIN
VIN
VIN
VIN
AGND
AT

04
~ND

Vee
VEE
VEE
VEE
Vee
~ND

NLiNV

000

INDEX

t

~ND

Vee
VEE
VEE
VEE
Vee
~ND

:J 5
:Ja
:17
:J 8
:J 9

0 8 (LSB)

06

07

4

3

'"
'
- I I II

2

::<

-------1

10K

------------------------1

-2,OOV ----......

Figure 5. Mid-Point Adjust

11-48

C1-C4
C5-C15
C12

10J.lF
0.1JlF
1-6pF Variable

U1
U2
U3
U4

IDT75C48
HA-2539-5
uA741C
LM313

01

2N2907

L1, L2

Ferrite Bead

15

CLOCK
-5,2V

o,on
80.7n
1Kn
2Kn
2200
2KO
1KO
2Kn
2Kn
10KO
20Kn
27n

U1

IDT75C48
26

R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12

IDT75C48 FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

DeV~Ype

X

X

X

x

Power

Speed

Package

Process/
Temperature
Range

y~LANK
L -______________

~

P
D
L

I--_ _ _ _ _ _ _ _ _ _~

20

L--------------------~S

L---------------------------------------475C48

Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
Plastic DIP
CERDIP (600 mil)
Leadless Chip Carrier

MHz
Standard Power

Flash ND Converter

iii

11-49

FEATURES:

DESCRIPTION:

•
•
•
•
•
•

8-blt resolution
20 MSPS conversion rate
Overflow Output
Low power consumption: 500mW
Extended analog input range
On-chip EDC (Error Detection and Correction)

•
•
•
•
•
•

Tri-state outputs
Improved output logic HIGH drive, no pull-up needed
No sample and hold required
Differential Phase == 1 Degree
Differential Gain == 2%
1/2 LSB linearity

The IDT75C58 is a 20 MegaSample per Second (MSPS), fully
parallel, 8-bit Flash Analog to Digital Converter. The wide input
analog bandwidth of 7MHz permits the conversion of analog input
signals with full-power frequency components up to this limit with
no input sample and hold. Low power consumption due to
CEMOS™ processing virtually eliminates thermal considerations.
The IDT75C58 is available in 28-pin plastic and hermetic DIPs and
a 28-pin LCC.
The IDT75C58 consists of a reference voltage generator, 255
comparators, encoding and EDC (Error Detection and Correction)
logic and an output data register. A single clock starts the conversion process and controls all internal operations. An additional
comparator detects an Overflow condition (VIN more positive than
Full-Scale + 1LSB) and activates the OVFL output. This output, together with two output enable inputs (OE1 and OE2), allow the
stacking of two IDT75C58s for 9-bit resolution with no external
components.
The IDT75C58 military Flash ND Converters are manufactured
in compliance with the latest revision of MIL-STD-883, Class B,
making them ideally suited to military temperature applications
demanding the highest level of performance and reliability.

• TTL-compatible
• Available in 28-pin CERDIP and Plastic DIP or LCC
• Military product Is compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
CONV

V1N

RT

I

-

I

-

OVFL

~MY
~~
~HY

·::

256 TO 9
ENCODE
+EDC

127

~W
;.
~

~

LATCH

~

128

~~

·

255

~~6
~V
~1

'---

256 DIFFERENTIAL
COMPARATORS

I

OE2

I

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-5004/-

11-50

IDT75C58 FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
OE2

D7 (MSB)

INDEX

OET

D6
D5
D4

uuu

RB
AGNO
NC

DoNO
Vee
VEE
VEE
VEE
Vee
DoNO
OVFl

DoNO
Vee
VEE
VEE
VEE
Vee
DoNO

RM
V1N
V1N
AGNO
RT
Vee
CONV

:J 5

4

3

I

I

2

.....

'-'

.....

28 27 26
25[

:Je

24[

:17

:J 8
:Js

L28-1

23[

RM

22[

V1N
V1N

21[

:J 10
:J 11

AGNO
NC

20[
19[

AGNO
RT

14 15 16 17 18

nnnnn

Do (lSB)

D3
D2

D1

DIP
TOP VIEW

lCC
TOP VIEW

GENERAL INFORMATION

Due to the unavoidable coupling with the clock and the input
signal, RT and RB should provide low AC impedance to ground.
For applications with a fixed reference, a bypass capacitor is
recommended.

The IDT75C58 has four functional sections: a comparator array,
a reference voltage generator, encoding logic with EDC and output
logic. The comparator array compares the input signal with 256 reference voltages to produce an N - of - 256 code. This is sometimes
called a "Thermometer" code because all of the comparators with
their reference voltage less than the input signal will be "on" while
those with their reference above the input will be "off".
The reference voltage generator consists of a string of precisely
matched resistors which generate the 256 voltages needed by the
comparators. The voltages at the ends of the resistor string set the
maximum and minimum conversion range and are typically OV
and -2V, respectively.
Included in the encoding function is Error Detection and Correction logic which ensures that a corrupted Thermometer code is
correctly encoded.
The output logic latches and holds the data constant between
samples. The output timing is designed for an easy interface to
external latches or memories using the same clock as the ADC.

CONTROL
Two function control pins, OE1 and OE2 control the outputs with
the function shown in Table 1.

CONVERT
The IDT75C58 begins a conversion with every rising edge of the
convert Signal, CONV. The analog input Signal is sampled on the
rising edge of CONV, while the outputs of the comparators are encoded on the falling edge. The next rising edge latches the encoder output which is presented on the output pins.
The input sample is taken within 15ns of the rising edge of
CONV. This is called tSTO or the Sampling Time Offset. This delay
varies by a few nanoseconds from part to part and as a function of
temperature, but the short term uncertainty or jitter is less than
60ps. If the maximum CONV pulse width HIGH time (tpWH) is exceeded, the accuracy of the input sample may be impaired. The
maximum CONV pulse width LOW time (tpWL) may be exceeded'liI
but the digital output data for the sample taken by the previous rising edge of CONV will be meaningless. It is recommended that
CONV be held LOW during longer periods of inactivity.
The digital output data is presented at to. the Digital Output Delay Time, after the next rising edge of CONV. Previous output data
is held for the tHO (Output Hold Time) after the riSing edge of CONV
to allow for non-critical timing in the external circuitry. This means
that the data for sample N is acquired while the converter is taking
sample N+2.

POWER
The IDT75C58 requires two power supply voltages, Vee and
VEE. Typically, VEE = -5.0V and Vee = + 5.0V. Two separate
grounds are provided, AGNO and DGNO, the analog and digital
grounds. The difference between AGNO and DGNO must not exceed
± O.1V and all power and ground pins must be connected.

REFERENCE
The IDT75C58 converts analog input signals that are within the
range of the reference (VRB:£. VIN :£. VRT) into digital form. VRB (Reference Bottom) and VRT (Reference Top) are applied across the
reference resistor chain and both must be within the range of
+O.1V to -2.1V. In addition, the voltage applied across the reference resistor chain (VRT-VRB) must be between 1.8V and 2.2V, with
VRT more positive than VRB. Nominally, VRT = O.OVand VRB = -2.0V.
The IDT75C58 provides a midpoint tap, RM, which allows the
converter to be adjusted for optimum linearity or a non-linear transfer function. Adjustment of RM is not necessary to meet the linearity
specification. Figure 6 shows a circuit which will provide approximately 1/2 LSB adjustment to the midpoint. The characteristic impedance of RM is about 1700 and this node should be driven from
a low impedance source. Any noise introduced at this point will
couple directly into the resistor chain, seriously affecting
performance.

ANALOG INPUT
The IDT75C58 uses strobed, auto-zeroing, latching comparators. For optimum performance, the source impedance of the analog driver must be less than 250. All three analog input pins must
be connected together as close to the package as possible. The
input signal must remain within the range of Vee to VEE to prevent
damage to the device.
If the analog input signal is within the reference voltage range,
the output will be a binary number between 0 and 255. An input signal below VRB will yield a full-scale (all outputs low) output while an
input above VRT will cause an OVFL output.

11-51

1DT75C58 FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OUTPUT

OVFL

O.OOOOV
-0.0080V
-0.0160V

11111111
11111111
11111110

1
0
0

-0.9961 V
-1.0039V
-1.0118V

-1.0160V
-1.0240V
-1.0320V

10000000
01111111
01111110

0
0
0

-1.9921V
-2.0000V

-2.0320V
-2.0400V

00000001
00000000

0
0

RANGE

STEP
-2.0000V FS
-7.8431 mY/Step

-2.0480V FS
-8.000mV/Step

256
255
254

O.OOOOV
-0.0078V
-0.0156V

129
128
127
001
000

:
:

:

:

.

:

:

:

:

:

Figure 1. Output Coding

CONY

ANALOG INPUT
Sample N+2

+

-

DIGITAL OUTPUT

Figure 2. Timing Diagram

Vee

8100
To Output Pin 0--..-......1---+
40pF

Figure 4. Output Load 1

Figure 3. Output, Enable/Disable Timing

Do - 0 7

OEl

OE2

0

1

Valid

Valid

1

1

HighZ

Valid

X

0

HighZ

High Z

1N3062

OVFL

Table 1. Function Control

11-52

1DT75C58 FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL

RATING

VALUE

UNIT

-0.5 to +7.0

V

POWER SUPPLY
Vcc

Measured to DGNO

VEE

Measured to AGNO

-0.5 to -7.0

V

AGNO

Measured to DGNO

-0.5 to +0.5

V

CONV, OE1, OE2

Measured to DGNO

-0.5 to Vcc + 0.5

V

V1N ,VRT,VRB

Measured to AGNO

Vcc to VEE

V

VRT

Measured to VRB

-2.2 to +2.2

V

INPUT VOLTAGE

OUTPUT
Applied Voltage

Measured to DGNO

-0.5 to Vcc + 0.5

Applied Current (2. 3. 4)

Externally forced

-3.0 to +6.0

Short Circuit Duration

Single output High to DGNO

1.0

(2)

V
mA
S

TEMPERATURE
Operating,
Ambient

Military

-55 to +125

°C

Commercial

o to

°C

Military

-65 to +150

°C

Commercial

-55 to +125

°C

+70

Storage
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational section ofthis specification is not implied. Exposure to Absolute Maximum Rating conditions
for extended periods may affect reliability. Absolute Maximum Ratings are limiting values
applied individually while all other parameters are within specified operating conditions.
Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current when flowing into the device.

III

AC ELECTRICAL CHARACTERISTICS
Specifications over the Recommended Operating Conditions unless otherwise stated.
SYMBOL

PARAMETER

TEST CONDITIONS

TEMPERATURE RANGE
COMMERCIAL
MILITARY
MIN.

MAX.

MIN.

UNIT

MAX.

Fs

Max. Conversion Rate

Vcc = Min.,VEE = Min.

20

-

20

-

MSPS

tsTO

Sampling Time Offset

Vcc = Min.,VEE = Min.

0

10

0

15

ns

to

Digital Output Delay

Vcc=Min.,VEE=Min., Load 1

-

30

-

35

ns

tHO

Digital Output Hold Time

Vcc = Max.YEE = Max., Load 1

5

5

Output Disable Time from HIGH

Vcc = Min.,VEE=Min., Load 1

tLl

Output Disable Time from LOW

Vcc = Min.,vEE= Min., Load 1

-

-

-

ns

tHZ

-

tZH

Output Enable Time to HIGH

Vcc=Min.,VEE=Min., Load 1

-

ns

Output Enable Time to LOW

Vcc = Min.,vEE= Min., Load 1

-

-

tlL

-

-

-

ns

11-53

ns
ns

IDT75C58 FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Specifications over the Recommended Operating Conditions unless otherwise stated
SYMBOL

PARAMETER

TEST CONDITIONS

TEMPERATURE RANGE
COMMERCIAL
MILITARY
MIN.

Icc

Positive Supply Current

Vcc = Max., static (1)

lEE

Negative Supply Current

VEE = Max., static (1)

IREF

Reference Current (RT to RB)

RREF
RIN

MAX.

MIN.

70

80

-

UNIT

MAX.
mA

-35

V RT , VRB = NOM

-

Reference Resistance (RT to RB)

V RT , VRB = NOM

250

-

220

-

Ohm

Equiv. Input Resistance

V RT , VRB = NOM, VIN = VRB

100

-

100

-

KOhm

CIN

Equiv. Input Capacitance

VRT, VRB = NOM, VIN = VRB

pF

VEE = Max.

10

-

50

Input Const. Bias Current

-

50

ICB

10

jJA

IlL

Input Current Logic LOW

Vcc = Max., VIH = 0.5V
CONV, NMINV, NLINV

±25

-

±25

jJA

±25

-

±25

jJA

50

50

jJA

0.5

-

0.5

V

2.4

-

jJA

IIH

Input Current, Logic HIGH

Vcc= Max., VIL = 2.4V

II

Input Current, Max. Input Voltage

Vcc = Max., VI = 'kc

-

VOL

Output Voltage, Logic LOW

Vcc = Min., IOL = 4.0mA

-

VOH

Output Voltage, Logic HIGH

Vcc = Min., IOH = -2.0mA

2.4

loz

Output High Z Current

Vcc=Max.

CI

Digital Input Capacitance

TA = +25°C, F=1MHz

Digital Output Capacitance
Co
NOTE:
1. Worst case, all digital inputs and outputs LOW.

TA = +25°C, F = 1MHz

-

9

-

-

-35

mA

10

mA

V

15

-

15

pF

20

-

20

pF

SYSTEM PERFORMANCE
Specifications over the Recommended Operating Conditions unless otherwise stated.
SYMBOL

PARAMETER

TEST CONDITIONS

TEMPERATURE RANGE
COMMERCIAL
MILITARY
MIN.

MAX.

MIN.

UNIT

MAX.

ELI

Linearity Error, Integral

VRT , VRS = NOM

-

0.2

-

0.2

ELD

Linearity Error, Differential

VRT , VRB = NOM

-

0.2

-

0.2

%FS

Cs

Code Size

25

175

25

175

%NOM

EOT

Offset Error, Top

VIN =VRT

-

45

mV

Offset Error, Bottom

V IN =VRB

-30

-30

mV

Tco

Offset Error, Temperature Coefficient

VIN=VRB

-

-

45

EOB

±20

-

±20

Jl.vrc

%FS

Bw

Bandwidth, Full Power Input

7

-

5

-

MHz

TTR

Transient Response, Full Scale

-

20

-

20

ns

53
52

-

Signal to Noise Ratio
SNR

20MSPS Conversion Rate,
10MHz Bandwidth

Peak Signal IRMS Noise

1.248MHz Input
2.438MHz Input

54
53

-

RMS Signal/RMS Noise

1.248MHz Input
2.438MHz Input

45
44

-

-

-

Fs =4xNTSC

-

EAP

Aperture Error

DP

Differential Phase Error

DG

Differential Gain Error

Fs =4xNTSC

Noise Power Ratio

DC to 8MHz White Noise
Bandwidth 4 Sigma Loading
1.248 MHz Slot
20MSPS Conversion Rate

NPR

11-54

-

-

dB

44
43

-

60

-

60

ps

1

-

1

Degree

-

2

-

2

%

36.5

-

36.5

-

dB

dB

IDT75C58 FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED OPERATING CONDITIONS
SYMBOL

TEMPERATURE RANGE
COMMERCIAL
MILITARY

PARAMETER
MIN.

NOM

MAX.

MIN.

NOM

UNIT
MAX.

Vcc

Positive Power Supply

4.75

5.0

5.25

4.5

5.0

5.5

VEE

Negative Power Supply

-4.75

-5.0

-5.5

-4.5

-5.0

-5.5

V

VAGND

Analog Ground Voltage (ref DemD)

-0.1

0

+0.1

-0.1

0

+0.1

V

tpWL

CONV, Pulse Width LOW

18

18

ns

22

20,000

22

-

100,000

CONV, Pulse Width HIGH

20,000

ns

Input Voltage, Logic LOW

-0.5

-

100,000

tPWH
V1L

0.8

-0.5

0.8

V

V1H

Input Voltage, Logic HIGH

2.0

-

2.0

IOL

Output Current, Logic LOW

-

Vcc+· 1
4.0

-

Vcc +·1
4.0

mA

V

V

IOH

Output Current, Logic HIGH

-

-

-400

-

-

-400

j.lA

VAT
VAB

Most Positive Reference Voltage (1)

-0.1

0

+0.1

-0.1

0

+0.1

V

Most Negative Reference Voltage (1)

-1.9

-2.0

-2.1

-1.9

-2.0

-2.1

V

VAr-VAB

Reference Voltage Range

1.8

2.0

2.2

1.8

2.0

2.2

V

V1N
TA

Input Voltage Range

VAB
0

-

VAT

VAB

VAT

V

-

-

°C

Case Temperature

-

70

Tc

-

-55

-

+125

°C

Ambient Temperature, Still Air

-

NOTE:
1. VAT must be more positive than VAB and the voltage reference differential must be within the specified range.

CALIBRATION

TYPICAL INTERFACE

The calibration of the IDT75C58 involves the setting of the 1st
and 255th comparator thresholds to the desired voltages. This is
done by varying the top and bottom voltages on the reference resistor chain, VAT and VAB, to compensate for any internal offsets.
Assuming a nominal OV to -2V reference range, apply -O.0039V (1/2
LSB from OV) to the analog input, continuously strobe the device
and adjust VAT until the OVFL output toggles between 0 and 1. To
adjust the 256th comparator, apply -1.996V (1/2 LSB from -2V) to
the analog input and adjust VAB until the converter output toggles
between the codes 0 and 1.
The offset errors are caused by the parasitic resistance between
the package pins and the actual resistor chain on-chip and are
shown as R1 and R2 in the Functional Block Diagram. The offset
errors, EOT and EOB, are specified in the System Performance Table and indicate the degree of adjustment needed.
The previously described calibration scheme requires that both
ends of the reference resistor chain be adjustable, i.e. be driven by
operational amplifiers. A simpler method is to connect the top of
the resistor chain, RT, to analog ground or OV and to adjust this end
of the range with the input buffer offset control. The offset error at
the bottom of the resistor chain results in a slight gain error which
can be compensated for by varying the voltage applied to RB. This
is a preferred method for gain adjustment since it is not in the input
signal path. See Figure 5 for a detailed circuit diagram of this
method.

Figure 5 shows a typical application example for the IDT75C58.
The analog input amplifier is a bipolar wideband operational amplifier whose low impedance output directly drives the ND Converter. The input buffer amplifier is configured with a gain of minus
two which will convert a standard video input signal (1V p-p) to the
recommended 2V converter input range. Both VIN pins are connected together as close to the package as possible and the input
buffer feedback loop is closed at this point. Bipolar inputs, as well
as the calibration of the reference top, are accomplished using the
offset control. A band-gap reference is used to provide a stable
voltage for both the offset and gain control. A variable capacitor in
the input buffer fee.dback loop allows optimization of either the step
or frequency response and may be replaced by a fixed value in the
final version of the printed circuit board.
To ensure operation to the rated specifications, proper decoupiing is needed. The bypass capacitors should be located close to
the chip with the shortest lead length possible. Massive ground
planes are recommended. If separate digital and ground planes
are used, they should be connected together at one point close to
the IDT75C48.
The bottom reference voltage, VAB, is supplied by an inverting
amplifier buffered by a PNP transistor. The transistor provides a low
impedance source and is necessary to provide the current flowing
through the resistor chain. The bottom reference voltage may be
adjusted to cancel the gain error introduced by the offset voltage,
EOB, as discussed in the calibration section.

11-55

iii

1DT75C58 FLASH AID CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

eli

+5V----------__----------------~~----------_4~--------_,

R1

@
~

R3

C13

C15~

ANALOG
INPUT
R7

~

PARTS LIST

18

6

Vee

Vee

10
Vee

21
"'IN
"'IN
RM

R12

U1
ID175C58
26
RB
AGND
19

17

RT

D7 (MSB)
D6
D5
D4
D3
D2

CONV

5.11

Do
Do (LSB)

13
14
15
16

CLOCK--------~----~--+_~----_+--------~

-S.2V'--------......-----~---_..-----------__4

__

ID175C58

11-56

0.00
80.70
1KO
2KO
2200
2KO
1KO
2KO
2KO
10KO
20KO
270

C1-C4
CS-C16
C12

1-6pF Variable

U1
U2
U3
U4

IDT7SC58
HA-2S39-5
uA741C
LM313

Q1

2N2907

L1, L2

Ferrite Bead

10~F
0.1~F

__l

Figure 5. Application Example

Figure 6. Mid-Point Adjust

R1
R2
R3
R4
RS
R6
R7
R8
R9
R10
R11
R12

IDT75C58 FLASH A!D CONVERTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CLOCK
ANALOG
INPUT
OV

CONV

GET r-- OV

V1N

OE2
IDT75C58

RT

··

Do-~

Rs

I
ClK
'---

CONV

OE2 f-5V

V1N

GET
IDT75C58

-2V

LATCH
INa

OVFl

RT

Rs

.

IN7

··

Oo-~

INO

0 8 I - - - D8 (MSB)

.
0; r--:Or

I--Do (lSB)

Figure 7. Simplified 9-81t Application

ORDERING INFORMATION

lOT

De~ype

X

X

X

x

Power

Speed

Package

Process!
Temperature
Range

Y:LANK

~

____________~I D
Il

~----------------------~: 20
~----------------------------~I S
~------------------------------------~:75C58

11-57

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to Mll-STO-883. Class B
CERDIP (600 mil)
lCC (450 mil square)
MHz

Standard Power

Flash AID Converter

iii

FEATURES:

DESCRIPTION:

•
•
•
•
•
•
•
•
•

The IDT75M48 is a 20 MegaSample per Second (MSPS), fully
parallel Flash Analog to Digital Converter subsystem. Contained
within the module is the IDT75C48 Flash ADC and all the peripheral components needed to make a fully functional converter.
Careful attention has been paid to the substrate layout and power
supply bypassing to ensure the highest performance.
The IDT75M48 is built using LCC packages mounted on a multilayer ceramic substrate using IDT's .high-reliability vapor phase
solder reflow process.
The IDT75M48 military ADC module is available with semiconductor components manufactured in compliance with the latest
revision of MIL-8TD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

20 MSPS conversion rate
8-bit resolution
1/2 LSB linearity
Low power consumption: 750mW
24-pin, 600 mil DIP footprint
Input bandwidth > 7MHz, no sample and hold required
On-board voltage reference and analog input buffer .
TTL-compatible inputs and outputs
Assembled with IDT's high-reliability vapor phase solder reflow
process
• Modules available with the semiconductor components compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
CONY

CONY
VIN

ClK

VIN

RT

0 0 -0 7
LATCH

0 0 -0 7

IDT75C48

>--4~------~

Rs

f

f

Vee

f

GND

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
0$0-5006/-

11-58

FEATURES:

DESCRIPTION:

•
•
•
•
•
•
•
•
•

The ID175M49 is a 9-bit, 20 MegaSample per Second (MSPS),
fully parallel Flash Analog to Digital Converter subsystem. Contained within the module are two ID175C58 Flash ADCs and all the
peripheral components needed to make a fully functional 9-bit
converter. Careful attention has been paid to the substrate layout
and power supply bypassing to ensure the highest performance.
The ID175M49 is built using lCC packages mounted on a multilayer ceramic substrate using IDT's high-reliability vapor phase
solder reflow process.
The ID175M49 military ADC module is available with the semiconductor components manufactured in compliance with the latest revision of Mll-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

20 MSPS conversion rate
9-bit resolution
1/2 lSB linearity
low power consumption: 950mW
24-pin, 600 mil DIP footprint
Input bandwidth > 7MHz
On-board voltage reference and analog input buffer
TTL-compatible inputs and outputs
Assembled with IDT's high-reliability vapor phase solder reflow
process
• Modules available with semiconductor components compliant
to Mll-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

CONV --------------------------------------~----------------,

CONV
VIN

ClK
OVFl

RT

OVFL

0 0 -07
LATCH

IDT75C58

VEE

Do- D8

-

RB

GND-

0"E"2

Vcc -

iii

CONV

RT

0"E"1
OVFL

VIN
IDT75C58

0 0 -07

l...-_ _ _ _ _ _ _ _--I

RB

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

DECEMBER 1987
OSC-5OO7/-

11-59

------------------

s

E2 PROMS-Electrically Erasable Programmable Read Only
Memories

s

ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORIES
An Electrically Erasable (E2) CEMOS technology has been developed to produce high-performance, programmable, nonvolatile devices that include E2PROMs.ln memory products, it is
lOT's intent to develop E2PROMs that mimic SRAM performance.
lOT E2 products will closely follow IDT SRAM innovations in speed,
. density and application specific features. Products include JEOEC
pin-function compatible E2 PROMs, E2 PROMs with serial accessi-

bility and registers, and high density E2 PROM modules. lOT
nonvolatile products utilize the industry standard floating gate thin
oxide technology and are fully tested to meet endurance and data
retention specifications.
lOT E2PROMs are designed for military and commercial
temperature applications. Radiation tolerant and radiation
enhanced E2PROMs will also be available.

TABLE OF CONTENTS
CONTENTS

PAGE

EEPROMs-Electrlcally Erasable Programmable Read Only Memories
IDT78C16A
16K (2K x 8) EEPROM .................................................................
IDT78C18A
16K (2K x 8) EEPROM w/SPC (14-154) ........................................ , ..... . . ...
IDT78M64
8K x 8 EEPROM Module . . . . .. . .. . . . .. . .. .. .. .. . . .. .. . . .. . .. . .. . .. . . . .. .. .. . . . . . .. . . ...
IDT78C64A
64K (8K x 8) EEPROM ............................................... '..................
IDT78C464A
64K (8K x 8) Registered EEPROM .......................................................
IDT78C564A
64K (8K x 8) Registered EEPROM w/SPC (14-154) .........................................
IDT78C256A
256K (32K x 8) EEPROM. . . . . .. .. . . . .. . . .. . . . . . . . . . . . . . .. . .. . . . . . . . .. .. . . . . . . . . .. . . ....
IDT78C4256A
256K (32K x 8) Registered EEPROM .....................................................
IDT78C5256A
256K (32K x 8) Registered EEPROM w/SPC (14-154) .......................................

12-1
12-10
12-22
12-30
12-32
12-34
12-36
12-38
12-40

FEATURES:

DESCRIPTION:

• 5 volt only operation
• Fast access times
- Military: 75ns (max.)
- Commercial: 70ns (max.)

The ID178C16A is a 5 volt only 2K x 8 Electrically Erasable Programmable Read-Only Memory (EEPROM). This high-speed
CEMOS ™ EEPROM is written on a byte basis and provides 16,384
bits of non-volatile data storage (data retention in excess of 100
years). Its fast read access time allows zero wait state read cycles
with high-performance microprocessors.
Writing is simplified by an internal charge-pump and timer circuit which eliminates the need for special external programming
voltage and write pulse shaping circuits. Byte erase before write
occurs automatically and input buffers, latches and internal timer
free the host system for other tasks during the write cycle. A DATA
Polling mode provides a method for determining write cycle completion. The ID178C16A also contains a dual voltage detection
logic circuit which allows the device to be used in older applications which incorporate external programming circuits.
The ID178C16A is function- and pinout-compatible with the
IDT6116, 2K x 8 static RAM. It is ideal for systems requiring nonvolatility and in-system data modifications.
Military grade product is manufactured in compliance to the latest revision of MIL-STD-883, Class B, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• On-chip timer
- Automatic byte erase before write
- Byte write 10ms max.
• DATA Polling-detection of write cycle completion
• Low-power CEMOS ™ technology
- 125mA active current
- O.gmA standby current (full CMOS)
• Data protection circuitry (Vee lockout for Vee < 3.8V)
provides data integrity on power up/power down
•
•
•
•

Minimum endurance of 10,000 write cycles per byte
Endurance failure rate < 0.1% per 1000 cycles
JEDEC approved byte-wide pinout
24-pin THINDIP (300 mil.), 24-pin DIP (600 mil.) and 32-pin LCC

• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

X
BUFFERS
LATCHES AND
DECODER

16.384 BIT
EEPROM
ARRAY

ADDRESS
INPUTS
Ao- AlO

Y

BUFFERS
LATCHES AND
DECODER

I/O
BUFFERS
AND
LATCHES

CONTROL
LOGIC

DATA
INPUTS/OUTPUTS
1/00 - 1/07

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1967 Integrated Device Technology. Inc.

DECEMBER 1987
DSC-6000/-

12-1

1DT78C16A FAST CMOS
EEPROM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

A7
A6

Vee

A5
A4

A9

o\!:U 0

,...000

~zzz~l3:z

INDEX

A8

II
'-I

4

I I
L-J

I I
L..J

I'
I I

II
L....II

I I
L...I

I I
L...I

3 2 L.l 32 31 30

wr:.

Aa

:J

A3
A2

C5E"

A5

:1 a

A9

Al0

A4

CE"

A3

:J
:1

NC

Al
Ao

I/~

A2

1/00
1/01
1/02

I/0a
1/05
1/04
1/03

GND

5

1

7

NC

8

L32-1

Al0

CE"

NC

I!~

14 15 16 17 18 19 20

LCC
TOP VIEW

Addresses-Column

A4 - Al0

Addresses-Row

CE

Chip Enable

DE

Output Enable

WE

Write Enable

1/00 - 1/07

Data Input (10 - 17) during write;
Data Output (0 0 - 0 7) during read

Vee

Power

GND

Ground

12-2

DE

Al

nnnnnnn

PIN NAMES

As

Ao

1/00

DIP
TOP VIEW

Ao - A3

29 [

I/0a

IDT78C16A FAST CMOS
EEPROM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEVICE OPERATIONAL MODE (1)

Noise Protection
The IDT78C16A will typically reject write pulses that are less
than 15ns. This prevents spurious noise from initiating a write
cycle.

PIN
MODE

1/00

-

1/0 7

CE

OE

WE

Read

V 1L

VIL

V1H

DataOUT (0 0 - 07)

Byte Write

V 1L

V 1H

V 1L

DatalN (10 - 17)

Standby

V 1H

Write Inhibit

Don't
Care

Don't
Care

High Z

Don't
Care

V 1L

Don't
Care

High Z

Don't
Care

Don't
Care

V 1H

Write Inhibit
Holding either OE LOW, WE HIGH or CE HIGH during a poweron and power-off, will inhibit inadvertent writes.

DATA Polling
The IDT78C16A has a maximum write cycle time of 10ms; a
write will always be completed in less than the maximum cycle
time. Write cycle completion is readily determined via a simple
software routine (DATA Polling) that performs a read operation
while the device is in an automatic write mode. If a read command
(addressed to the last byte written) is given while the IDT78C16A is
still writing, the inverse of the most significant bit (1/07 pin) of the
last byte written will be present. True data is not released until the
write cycle is completed. Thus, a DATA polling monitor of the output (or periodic read of the last written byte) for true data can be
used to detect early completion of a write cycle.

High Z

NOTE:
1. All control inputs are TTL-compatible.

READ MODE
Chip Enable (CE) and Output Enable (OE) must be logically active in order for data to be avai lable at the outputs. After a selected
byte address is stable, CE is taken to a TIL LOW (enabling chip).
The Write Enable (WE) pin should remain deselected (TIL HIGH)
during the entire read cycle. Data is gated from the device outputs
by selecting the OE pin (TIL LOW).

ENDURANCE
lOT's EEPROM technology employs the Fowler-Nordheim
method of tunneling across a thin oxide. IDT78C16A EEPROMs
are deSigned and tested for applications requiring extended endurance.
The endurance failure mechanism associated with EEPROMs
results from the charge trapping in the thin tunneling dielectric.
This failure is a function of the numberof write cycles that each byte
in the part has experienced. Trapped charges accumulate slowly
with each write cycle, eventually becoming large enough to prevent reliable writing to the bit cell. Since some bits may be more
sensitive than others, an endurance failure is typically a single bit
failure (Le. a failure of a single bit to properly write or retain data).
To test for endurance, sample devices are written 10,000 times
at every byte location and checked for data retention capability.
lOT's tests ensure that shipped devices will write a minimum of
10,000 times (at every byte location) with a maximum failure rate of
1%. This means that up to 1% of a sample of devices will fail to
write or retain data after being written to 10,000 times. Those devices that do fail typically have a single bit(s) that fails to retain data
after being written.
For more detailed information please refer to the !Dr Reliability
Report on Endurance.

WRITE MODE
The IDT78C16A is programmed electrically in-circuit and does
not require any external latching, erasing or timing. Writing to the
IDT78C16A is as easy as writing to a static RAM. When a write cycle
is initiated, the device automatically latches the address, data and
control signals as it begins its write operation.
A write cycle is initiated when both CE and WE are LOW and OE
is HI.GH. The IDT78C16A supports both a CE and WE controlled
write cycle. All ~uts, except for data, are latched on the falling
edge of either CE or WE, whichever occurs last. Data is then
latched in by the rising edge of either CE or WE, whichever occurred first. An automatic byte erase of the existing data at the addressed location is performed before the new data byte is written.
Once initiated, a byte write operation will automatically proceed to
completion within 10ms.

STANDBY MODE
The IDT78C16A features a standby mode which reduces the
maxi mum active current from 125mA to 20mA for TIL levels and to
O.gmA for CMOS levels. With CE ~ VIH all outputs are in the high
impedance state.

DATA PROTECTION
Nonvolatile data is protected from inadvertent writes in the following manner:

Power Up/Down
On-chip Circuitry provides protection against false write during
Vee power up/down. The IDT78C16A features an internal sensing
circuit that disables the internal.l2!:9Q@..mmin9.£rcuit if Vee < 3.8V.
This prevents input signals at CE, WE and OE from triggering a
write cycle during a Vee power up/down event.

12-3

IDT78C16A FAST CMOS
EEPROM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS
RATING

SYMBOL

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

(1)

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

VTERM

Terminal Voltage
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°c

TBIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°c

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°c

MIN.

TYP.

MAX.

PT

Power Dissipation

1.0

1.0

W

Vco

Supply Voltage

4.5

5.0

5.5

V

lOUT

OC Output Current

50

50

mA

VIH
VIL

Input High Voltage

2.2

3.5

6.0

V

Input Low Voltage

-0.3

0.4

0.8

V

VWl

Write Inhibit

3.8

-

-

V

GRADE
Military
Commercial

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND
OV

5.OV ± 10%

O°Cto +70°C

OV

5.OV ± 10%

Vee

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

PARAMETER

CAPACITANCE
CIN

(TA= +25°C, f = 1.0MHz, Vec = 5.0V)

PARAMETER(1)

SYMBOL

Input Capacitance

CONDITIONS

TYP.

\'IN = OV

Output CapaCitance
VOUT = OV
COUT
NOTE:
1. This parameter is sampled and not 100% tested.

ENDURANCE
PARAMETER

UNIT

UNIT

6

pF

8

pF

Minimum Endurance

DC ELECTRICAL CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified
TA = OOCto +70 0 C

vee = 5.OV±10% (Commercial)

TA = -55°C to +125°C

Vee = 5.OV±10% (Military)

VLC = 0.2V
C L = 30pF

VHC = Vee -0.2V

SYMBOL
Ilu l

PARAMETER

TEST CONDITIONS

Input Leakage Current

Vcc = Max., \'IN = GND to Veo

-

Output Leakage Current

CE = '-"H orOE = VIH,
VI/O = GND to Vco

leol

Operating Power Supply Current
Vee = Max., f = 0

CE = VIL•
11/0 = OmA

Ic02

Dynamic Operating Current
Voo = Max., f = fMAX

CE
11/0

ISB

Standby Power Supply Current
(TTL Level)

CE ~\'IH' Vec = Max .• 11/0 = OmA
VIN ~ VIH or 0 :5 VIN :5 VIL

ISBl

Full Standby Power Supply Current
(CMOS Level)

CE ~ VHO • Vco = Max., 11/0 = OmA
VIN ~ Voo -0.2V or 0 :5VIN :5 0.2V

VOL

Output Low Voltage

Voo

VOH

Output High Voltage

Vec

IlLOI

MIN.

= VIL,
= OmA

= Min., 10L = 8mA
= Min .• 10H = -2mA

12-4

MAX.

UNIT

10

~A

-

10

~

125

ITA

-

125

ITA

-

20

ITA

0.9

ITA

-

0.4

V

2.4

-

V

IDT78C16A FAST CMOS
EEPROM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(Vcc = 5.0V +10%,
C L = 30pF, O°C to + 70°C)
COMMERCIAL O°C to +70°C
78C16A70
78C16A90/1 00
78C16A120
78C16A150
MAX.
MIN.
MAX.
MIN. MAX.
MIN.
MAX.
MIN.

78C16A200
MIN.
MAX.

UNIT

READ CYCLE
150

70

-

70

-

-

5

-

5

120

60/65

-

-

5

tCE

Chip Enable Access Time

-

70

-

90/100

tAA

Address Access Time

70

-

90/100

tOE

Output Enable to Output Valid

-

50

-

tcu

Chip Enable to Output in LowZ(1)

5

-

5

120

150

200

ns

200

ns

70

ns
ns

tau

Output Enable to Output in Low Z(1)

5

-

5

-

5

-

5

-

5

-

tCHZ

Chip Disable to Output in High Z (I)

0

20

0

20

0

20

0

20

0

20

ns

tOHZ

Output Disable to Output in High Z (I)

0

20

0

20

0

20

0

20

0

20

ns

5

-

5

-

5

-

5

-

5

-

ns

Output Hold from Address Change
tOH
NOTE.
1. This parameter is guaranteed but not tested.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

ns

(Vcc = 5.0V ±10%, C L = 30pF, -55°C to + 125°C)

78C16A75
MIN.
MAX.

MILITARY -55°C to +125°C
78C16A90/100 78C16A 120/150 78C16A200/250 78C16A300/350
MIN.
MAX.
MIN. MAX.
MIN.
MAX.
MIN.
MAX.

UNIT

READ CYCLE
tCE

Chip Enable Access Time

tAA

Address Access Time

tOE

Output Enable to Output Valid

-

tcu

Chip Enable to Output in Low Z(1)

5

75
75
50

-

90/100

5

-

300/350

ns

300/350

ns

70

ns

5
5

-

ns

5

-

0

30

0

30

ns

-

120/150

-

200/250

120/50

200/250

70

-

5

-

5

5

-

5

-

0

30

0

30

90/100
60/65

70

tau

Output Enable to Output in Low Z(l)

5

-

tCHZ

Chip Disable to Output in High Z (I)

0

30

tOHZ

Output Disable to Output in High Z (1)

0

30

0

30

0

30

0

30

0

30

ns

5

-

5

-

5

-

5

-

5

-

ns

Output Hold from Address Change
tOH
NOTE:
1. This parameter is guaranteed but not tested.

12-5

ns

IDT78C16A FAST CMOS
EEPROM 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

ADDRESS

DATA OUT
NOTE:
1. WE is HIGH for Read Cycle.

TIMING WAVEFORM OF READ CYCLE NO.

ADDRESS

DATA OUT
NOTE:
1. WE is HIGH; CE

2(1)

t= tOH--L=1. i= t~=l_
~

_ _ _ _ _ _ _ _.......

= "'L; OE = "'L

TIMING WAVEFORM OF READ CYCLE NO.

3(1)

DATA OUT
NOTE:
1. WE is HIGH; OE = V1L; address valid prior to or coincident with CE transition LOW.

12-6

DATAVALID

~

IDT7SC16A FAST CMOS
EEPROM 16K (2K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(VCC

SYMBOL

= 50V -+10%

All Temperature Ranges' C L

PARAMETER

= 30pF)
MIN.

MAX.

UNIT

WRITE CYCLE
t AS

Address Set-up Time

5

tAH

Address Hold Time

50

tos

Data Set-up Time

20

tOH

Data Hold from Write Time

15

tOES

Output Enable Set-up Time

5

tOEH

Chip Enable Hold from Write Time

15

t CES

Chip Enable Set-up Time

-

-

ns
ns
ns
ns
ns

0

-

ns
ns

ns

tCEH

Chip Enable Hold Time

0

-

twp

Write Pulse Width

50

-

ns

tWB

Byte Write Cycle

10

ms

tOBV

DATA Polling to DATA Valid

-

tWH

Write Hold Time

15

top

End of Write Pulse to DATA Polling

15

t wES

Write Enable Set-up Time

0

tWEH

Write Enable Hold Time

0

-

tov

Data Valid Time

-

1

(1.2)

NOTES:
1. Data must be valid within 1J.ls maximum and must remain valid if twp is longer than 1J.ls.
2. This parameter is guaranteed but not tested

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels

GNDto 3.0V
5ns
1.5V
1.5V

12-7

tOE
ns
ns
ns
ns
J.ls

IDT7SC16A FAST CMOS
EEPROM 16K (2K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, WE CONTROLLED

ADDRESS

TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED

ADDRESS

DATA IN

12-8

IDT78C16A FAST CMOS
EEPROM 16K (2K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA POLLING

READ
BYTE

~
N

~READ.
BYTE

N

1/0(1)

NOTE:
1. Most significant bit of the byte being written is inverted and available at I/O 7 if a Read command is issued. All other outputs are high impedance at this
time. True data will not be released until the Write cycle is completed.

ORDERING INFORMATION
IDT

xxxx
Device Type

999
Speed

A

A

Package

Process/
Temperature
Range

Y:,onk
TO

~--------------~

~

______________________~

~--------------------i

12-9

D
L

70
75
90
100
120

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to, MIL-STD-883, Class B
THINDIP (CERDIP)
CERDIP
Leadless Chip Carrier
Commercial Only
Military Only

Speed in Nanoseconds

150
200
250
300
350

Military Only
Military Only
Military Only

78C16A

16K (2K x 8-Bit) Fast CMOS EEPROM

FEATURES:

DESCRIPTION:

• 2K x 8 EEPROM with serial write and read back
• 5 volt only operation
• Fast access times
- Military: 75ns (max.)
- Commercial: 70ns (max.)

The IDT78C18A is a 5 volt only 2K x 8 Electrically Erasable
Programmable Read-Only Memory (EEPROM) with Serial Protocol Channel (SPC). SPC complements the EEPROM's parallel
information path by providing a serial link (4 additional pins) by
which Its nonvolatile array can be loaded or read. The IDT78C18A
is written on a byte basis and provides 16,384 bits of nonvolatile
data storage (data retention in excess of 100 years). Fast read
access times allow zero wait state cycles with high-performance
microprocessors.
Writing is simplified by an internal charge-pump and timer
circuit which eliminates the need for external programming voltage
and write pulse shaping circuits. Internal latches free the host system for other tasks duri~write cycle. Byte erase before write
occurs automatically. A DATA Polling mode is provided for determining write cycle completion.
The IDT78C18A is ideal for systems requiring nonvolatility and
In-system data modifications. With SPC, a serial link can be established during board layout for easy field updates of code changes.
The IDT78C18A military EEPROM is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding the
highest level of performance and reliability.

• Low-power CEMOS ™ technology
- Active Current: 125mA
- Standby Current (full CMOS): 0.9mA
• Serial Protocol Channel (SPC) allows load and readout of the
memory array over a 4-wire channel
• On-Chip timer
- Automatic byte erase before write
- Byte write 10ms max.
• DATA Polling-detection of write cycle completion
• Data protection circuitry (Vee lockout for Vee < 3.8V)
provides data Integrity on power up/power down
• Minimum endurance of 10,000 write cycles per byte
• Endurance failure rate < 0.1 % per 1000 cycles
• Available in 28-pin THINDIP and 32-pin LCC
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

X
BUFFERS
LATCHES AND
DECODER

16,384 BIT
EEPROM
ARRAY

ADDRESS
INPUTS
Ao- A '0
Y

BUFFERS
LATCHES AND
DECODER

~

C5E"

1/0
BUFFERS
AND
LATCHES

CONTROL
LOGIC

DATA
INPUTS/OUTPUTS
1/00 -1/07

~

SERIAL
DATA IN

{

SOl
SCLK
C/[5

SERIAL
PROTOCOL
CHANNEL

SERIAL
DATA OUT

CEMOS and SPC are trademarks of Integrated DeVice Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

DECEMBER 1987
D5e-8001/-

12-10

1DT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K X 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

INDEX

A7
Ae

II
L-.I

4
A4 :1 5

A5
A4
A3
SCLK

A3 :1 e
SCLK ] 7

A2

:1 8

I

I

I

I I
II

3 2 U

II
L-I

II
L...,I

I I
L...I

32 31 30

1

29 [

we.
rn=

27 [

NC

26 [:

SDO

Al
C/L>

:J

9

25 [

A10

]

10

24 [

cr

Ao

:1
:1

11

23 [

SDI

12

22 [

IIOr

lIDo
1/01
1/02

L32-1

:1 13

21
14 15 16 17 18 19 20

£: 1/06

nnnnnnn

GND

DIP
TOP VIEW

LCC
TOP VIEW

DEVICE OPERATIONAL MODE

~

DE

CE

MODE

PIN NAMES

(1,2)

WE

1/00 - 1/07

Read

"'IL

V1L

V1H

Data our (0 0 - 0 7)

Byte Write

"'IL

V1H

V1L

Data lN (10:- 17)

Standby

"'IH

Don't
Care

Don't
Care

HighZ

Don't
Care

V1L

Don't
Care

HighZ

Don't
Care

Don't
Care

V1H

HighZ

VH (2)

HighZ

Write Inhibit

Chip Erase

VH (2)

"'IL

Ao -A3

Addresses-Column

A4 - A10

Addresses-Row

cr
rn=
we.
lIDo - 1/07

NOTES:
1. All control inputs are TIL-compatible.
2. VH = High Voltage; optional function, consult IDT for more details.

CE

OE

Command

X

X

WE
X

H

Data

X

X

X

L

Execute

X

X

X

C/O

L

SCLK

Data Input (10 - 17) during write;
Data Output (0 0 - 0 7) during read
Serial Data Input
Serial Data Output

SCLK

Data Clock Input

C/15

CommandlData

FUNCTION
Shift bit into command register

S

Execute command during time
between C/L> and SCLK

Shift bit into data register

12-11

Output Enable
Write Enable

SDO

S
S

NOTE:
1. X = Don't Care

Chip Enable

SDI

SPC OPERATIONAL MODES (1)
MODE

I

~

L-I

IDT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K x B-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

monitor of the output (or periodic read of the last written byte) for
true data can be used to detect early completion of a write cycle.

READ MODE
Chip Enable (eE) and Output Enable (OE) must be logically
active In order for data to be available at the outputs. After a selected byte address Is sta~ CE Is taken to a TTL LOW (enabling
Chip). The Write Enable (WE) pin should remain deselected (TTL
HIGH) during the entire read cycle. Data Is gated from the device
outputs by selecting the OE pin (TTL LOW). For serial read function, see description within -Serial Protocol Channel" section.

CHIP ERASE
In particular applications, erasure of the entire chip (all bytes simultaneously) may be desired. An optional chip erase feature of
the 10T78C18A allows erasure of the entire chip within 5ms. Contact lOT for more details regarding this optional function.

WRITE MODE

ENDURANCE

The 10T78C18A is programmed electrically In-clrcuit and does
not require any extemallatching, erasing or timing. Writing to the
10T78C18A Is as easy as writing to a static RAM. When a write cycle
Is Initiated, the device automatically latches the address, data and
control signals as It begins Its write operation.
A write cycle Is Initiated when both CE and WE are LOW and
OE is HIGH. The 10T78C18A supports both a CE and WE controlled write cycle. AJ!..!!'lp~except for data, are latched on the
failing edge of either CE orWE, whichever occurs last. Data Is then
latched In by the rising edge of either CE or WE, whichever occurred first. An automatic byte erase of the existing data at the addressed location is performed before the new data byte Is written.
Once Initiated, a byte write operation will automatically proceed to
completion within 10ms. For serial write function, see description
within -Serial Protocol Channel" section.

lOT's EEPROM technology employs the Fowler-Nordheim
method of tunneling across a thin oxide. IDT78C18A EEPROMs
are designed and tested for applications requiring extended
endurance.
The endurance failure mechanism associated with EEPROMs
results from the charge trapping In the thin tunneling dielectric.
This failure is a function ofthe number of write cycles that each byte
In the part has experienced. Trapped charges accumulate slowly
with each write cycle and eventually become large enough to prevent reliable writing to the bit cell. Since some bits are more sensitive than others, an endurance failure Is typically a single bit failure
(i.e. a failure of a single bit to properly write or retain data).
To test for endurance, sample devices are written 10,000 times
at every byte location and checked for data retention capability.
10rs tests ensure that shipped devices will write a minimum of
10,000 times (at every byte location) with a maximum failure rate of
, %. This means that up to , % of a sample of devices will fail to
write or retain data after being written to 10,000 times. Those devices that do fall typically have a single bit(s) thatfalls to retain data
after being written.
For more detailed information please refer to the IDT Reliability
Report on Endurance.

STANDBY MODE
The IDT78C18A features a standby mode which reduces the
maximum active current from 125mA to 20mA for TTL levels and to
0.9mA for CMOS levels. With CE ~ VIH all outputs are in the high
impedance state.

DATA PROTECTION
Nonvolatile data Is protected from Inadvertent writes in the following manner:

Power Up/Down
On-chlp circuitry provides protection against false write during
Vee power up/down. The 10T78C18A features an Internal sensing
circuit that disables the Intemal..E!:...OQ@!!lming circuit if Vee < 3.8V.
This prevents Input signals at CE, WE and OE from triggering a
write cycle during a Vee power up/down event.

Noise Protection
The IDT78C18A will typically reject write pulses that are less
than 15ns. This prevents the initiation of a write cycle by a noise
occurrence.

Write Inhibit
Holding either OE LOW, WE HIGH or CE HIGH during a poweron and power-off, will inhibit inadvertent writes.

DATA POLLING
The IDT78C18A has a maximum write cycle time of 10ms; a
write will always be completed in less than the maximum cycle
time. Write cycle completion is readily determined via a simple
software routine (DATA Polling) that performs a read operation
while the device Is in an automatic write mode. If a read command
(addressed to the last byte written) is given while the IDT78C18A is
still writing, the inverse of the most significant bit (1/07 pin) of the
last byte written will be present. The most significant bit becomes
valid when the write cycle is completed. Thus, a DATA Polling

SERIAL PROTOCOL CHANNEL
The Serial Protocol Channel (SPC 1M) provides a method by
which data can beJ!ntered or extracted from the memory array via
four unique pins CD, SCLK, SOl and SOO. SPC logic consists of a
24-blt data shift register, a 4-bit command register and clock logic
consisting of gates and a flip-flop (see block diagram). From the
outside, SPC appears like two parallel serial shift registers; one for
command and the other data. Data is clocked In on a Serial Data
Input pin (SOl) and out on a Serial Data Output pin (SOO). The
transfer of data Is controlled by a serial clock (SCLK) and a Command/Data mode input (C/O). The serial clock (SCLK Input) shifts
Information and the Command/Data (C/O) Input selects the register that will be shifted. The command register (when loaded and
executed) controls the loading of data into and out of the data register with regard to writing to or reading from an addressed location
of the memory array.
There are two modes for the shift operation: when C/O Input ~
LOW, data Information is shifted through the device and, when C/O
Is HIGH, command is shifted through. As the C/O line transitions
from HIGH (command) to LOW (data), a clock pulse is intemally
generated to the command decode logic and is used to execute
. the instruction in the command register (clock pulse ends when
serial clock transitions from LOW to HIGH). There are four steps to
executing an SPC command: data Is shifted in, command bits are
then shifted in, the command is then executed and data is clocked
(shifted) out. (Note: The data to the SPC Is shifted In LSB first.) DurIng the data mode, data is simultaneously shifted into the serial
data register while data in the register is shifted out.

12-12

IDT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K x B-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Command codes that are utilized for read/write operations are
shown below:

All functions can be performed serially, including DATA Polling. The operation of serial DATA Polling is the same as SPC read.
The byte being written is read and bit 23 (representing 1/07) will be
the complement of the most significant data bit until the write cycle
is completed. (After completion of the write cycle, bit 23 will show
true data.)

Command Words (4-bit Command Register):
Read
Write (Byte)
Invalid Command-Reserved for Optional Chip
Erase

0000
0001
0010
3

j

}

No Operation

15

clO
SDI

MUX

1---- SDO

SERIAL
DATA REGISTER
SCLK

READ DATA

ADDRESS -----------;~~__~

DATA 1/0
Figure 1. Detailed SPC Block Diagram

12-13

IDT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

To Read Data Out:
Execute (C/[5 HIGH to LOW executes command)
Shift In 11 Address Bits and
13 Oon't Care Bits on SOl
SCLK

Shift Out 11 Address in 10 Shifts·, 5 Oon't Care
and 8 Oata Bits on SOO

Shift In 4
Command Bits
on SOl

.rtI1I1Il ..U-

-11- .J1J1.I1JL

Cll5
Command
Register (SOl)

Oata Register (SOl)
23

10

I_

0

13Oon'1 - + - 1 1 Address-l

caree~s

_

e~s

_

Execution loads data addressed into
Oata Register for clocking out on SOO

321 0

23

~

L
L

1615
60ala

ens

-?
~

5 Oon'l

1110

Care e~s

0

Lll
Address-l
Lens _

Read Code
• When C/[5 is brought LOW, address bit 0 Is already at SOO,
First riSing edge on SCLK after C/I5 goes LOW shifts out the
next address bit at SOO,

To Write Data In:
Execute (Write cycle begins on falling edge of C/[5 and
concludes within t we),
Clock should be brought HIGH within 2ms
to prevent triggering second write cycle,

Shift In 11 Address Bits, 5 Oon't
Care and 8 Oata Bits on SOl
SCLK

.rtI1I1Il ..U-

Cll5

321 0

~

Write Code

12-14

IDT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM

COMMERCIAL MILITARY

RATING
Terminal Voltage
with Respect to
GND

-0.5 to +7.0

-0.5 to +7.0

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

UNIT

GRADE

V

Military

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND
OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V ± 10%

Vee

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

SYMBOL

MIN.

TYP.

MAX.

UNIT

PT

Power Dissipation

1.0

1.0

W

Vcc

Supply Voltage

4.5

5.0

5.5

V

lOUT

DC Output Current

50

50

mA

VIH
VIL

Input High Voltage

2.2

3.5

6.0

V

Input Low Voltage

-0.3

0.4

0.8

V

VWl

Write Inhibit

3.8

-

-

V

Commercial

RECOMMENDED DC OPERATING CONDITIONS

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
speCification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

PARAMETER

CAPACITANCE
SYMBOL

(TA= +25°C. f = 1.0MHz. Vee = 5.0V)

PARAMETER(l)

CONDITIONS

TYP.

UNIT

6

pF

8

pF

CIN
Input Capacitance
\'IN = OV
COUT
Output Capacitance
VOUT = OV
NOTE:
1. This parameter is sampled and not 100% tested.

ENDURANCE
PARAMETER

VALUE

Minimum Endurance

10.000

DC ELECTRICAL CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
TA = O°C to + 70°C
Vee = 5.0V ±10% (Commercial)
TA = -55°C to + 125°C
Vee = 5.0V ±10% (Military)
VLC = 0.2V
VHC = Vee - 0.2V
CL= 30pF
SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

MAX.

-

10

J.lA

10

J.lA

125

m\

125

m\

20

m\

0.9

m\

-

0.4

V

2.4

-

V

Ilul

Input Leakage Current

Vee = Max·.\'IN = GND to Vee

IILol

Output Leakage Current

CE = \'IH or ~ = \'IH. VVO = GND to Vee

leel

Operating Power Supply Current
Vee = Max.• f = 0

CE = \'IL. Iva = OmA

ICC2

Dynamic Operating Current
Vcc = Max.• f = fMAX

CE" = \'IL.lva = OmA

ISB

Standby Power Supply Current
(TTL Level)

CE ~ \'IH •Vee = Max.• 1"0 = OmA

ISBl

Full Standby Power Supply Current
(CMOS Level)

CE ~ VHC •Vcc = Max.• Ivo = OmA

VOL
VOH

Output Low Voltage

\'IN ~ Vcc -0.2V or 0 :5 VIN :5 0.2V
Vcc = Min .• IOL = 8mA

-

Output High Voltage

Vcc = Min .• IOH = -2mA

\'IN ~ \'IH or 0 :5 \'IN :5 \'IL

12-15

-

UNIT

IDT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
SYMBOL

-

(VCC = 5V +10% All Temperature Ranges; C L = 30pF)

COM'LONLY
IDT78C18A70
MIN.
MAX.

PARAMETER

IDT78C18A75(2)/90
MAX.
MIN.

COMMERCIAl/MILITARY
IDT78C18A100/120 IDT78C18A150/200
MAX. MIN.
MAX.
MIN.

UNIT

READ CYCLE
tCE

Chip Enable Access Time

-

70

-

75/90

-

100/120

-

150/200

ns

tM

Address Access Time

-

70

-

75/90

-

100/120

150/200

ns

tOE

Output Enable to Output Valid

-

50

-

50/60

-

65170

-

70

ns

tcLZ

Chip Enable to Output in Low Z(1)

5

5

-

5

Output Enable to Output in Low Z(l)

5

-

5

toLZ

-

5

-

5

-

ns

tCHZ

Chip Disable to Output in High Z

0

20

0

20/30

0

20/30

0

20/30

ns

tOHZ

Output Disable to Output in High Z

0

20

0

20/30

0

20/30

0

20/30

ns

tOH

Output Hold from Address Change

5

-

5

-

5

-

5

-

ns

(1)
(1)

5

ns

NOTES:
1. This parameter Is guaranteed but not tested.
2. Military temperature range only.

AC ELECTRICAL CHARACTERISTICS

(VCC

SYMBOL

= 5V -+10%

All Temperature Ranges; C L

PARAMETER

= 30pF)
MIN.

MAX.

UNIT

-

ns

-

ns

WRITE CYCLE
tAs

Address Set-up Time

5

tAH

Address Hold Time

50

tos

Data Set-up Time

20

tOH

Data Hold from Write Time

15

tOES

Output Enable Set-up Time

5

tOEH

Chip Enable Hold from Write Time

15

tCES

Chip Enable Set-up Time

0

-

ns
ns

ns
ns
ns

tCEH

Chip Enable Hold Time

0

Write Pulse Width

50

-

ns

twp
tWB

Byte Write Cycle

-

10

ms

tOE

ns

tOBV

r5ATA Polling to r5ATA Valid

-

tWH

Write Hold Time

15

-

ns

top

End of Write Pulse to r5ATA Polling

15

-

ns

t wEs

Write Enable Set-up Time

0

-

ns

tWEH

Write Enable Hold Time

0

-

ns

tov

Data Valid Time (1.2)

-

1

J.ls

NOTES:
1. Data must be valid within 1J.ls maximum and must remain valid if twp is longer than 1J.ls.
2. This parameter is guaranteed but not tested.

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels

GND t03.0V
5ns
1.5V
1.5V

12-16

IDT78C18A FAST CMOS
EEPROM WITH SPC 16K (2Kx 8-BIT)

TIMING WAVEFORM OF READ CYCLE NO.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1(1)

ADDRESS

DATA OUT
NOTE:
1. WE is HIGH for Read Cycle.

TIMING WAVEFORM OF READ CYCLE NO.

2(1)

ADDRESS

DATA OUT
NOTE:
1. WE is HIGH; CE =

"'L; OE = "'L

TIMING WAVEFORM OF READ CYCLE NO. 3(1)

(t~z1-

DATA OUT
NOTE:
1. WE is HIGH; OE = V1L; address valid prior to or coincident with CE transition LOW.

12-17

1DT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, WE CONTROLLED

ADDRESS

DATA IN

TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED

ADDRESS

DATA IN

12-18

------------------

1DT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA POLLING

~
READ
BYTE
N

~READ
BYTE
N

1/0(1)

NOTE:

1. Most significant bit of the byte being written is inverted and available at 1/07 if a Read command is issued. All other outputs are high impedance at this
time. True data will not be released until the Write cycle is completed.

12-19

IDT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SPC AC ELECTRICAL CHARACTERISTICS

-

-

Vcc - 5V +10% All Temperature Ranges

PARAMETER

SYMBOL

MIN.

MILITARY (1)

COMMERCIAL(1)
MAX.

UNIT

MIN.

MAX.

100

ns

15

-

tSCLK

SCLK Period

100

tscw

SCLK Pulse Width

50

t SDS

Serial Data Set-up Time

15

-

tSDH

Serial Data Hold Time

5

-

5

-

ns

tscD

Clock to Serial Data Output Delay

4

25

4

25

ns

tSCLCMD

Clock to Command Set-up Time (3)

50

50

Command/Data Set-up Time, LOW to HIGH

50

tCMHL

Command Set-up Time, HIGH to
LOW (Execution Time)(4)

tAA

tAA

-

ns

tCMLH

-

100

2(10)(6)

100

2(10)(6)

l Read Cycle

I Write/Erase Cycle

50

50

0
0
tSCLKCD Clock LOW to C/15 HIGH
NOTES:
1. These specifications apply to all speed grades of the product.
2. This parameter guaranteed but not tested.
3. C/15 cannot change while clock Is high.
4. During a write/erase cycle SCLK should be brought HIGH within 2ms to prevent triggering another write/erase cycle.

-

14------- tSCLK ------~
tscw

--+1-.--- tscw

SCLK

SERIAL DATA IN

SERIAL DATA OUT

t SCLKCD 1+--_01

C/15

COMMAND
EXECUTE TIME
(REFERENCE)

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels

GNDto 3.0V
5ns
1.5V
1.5V

12-20

r---

ns
ns

ns
ns
ns

IDT78C18A FAST CMOS
EEPROM WITH SPC 16K (2K X 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxxxx

999

A

A

Device Type

Speed

Package

Process/
Temperature
Range

y:""k
J TO

L . . . . . - - - - - - - - - - il L

L.....__________________________

~

70
75
90

100
120
150

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STD-883, Class B
THINDIP (CERDIP)
Leadless Chip Carrier

Commercial Only
Military Only

1

Sp..d;n N"""econd,

200

L-------:-------------_178C18A

12-21

16K (2K x 8-Bit) EEPROM with SPC

FEATURES:

DESCRIPTION:

• Equivalent to JEDEC standard 8K x 8 monolithic EEPROM
• 8,192 x 8 CMOS EEPROM module complete with decoder and
decoupling capacitor
• Fast access times
- Military: 85ns (max.)
- Commercial: 70ns (max.)

The IDT78M64 Is a 5 volt only 8K x 8 Electrically Erasable
Programmable Read-Only Memory (EEPROM) constructed on a
co-fired ceramic substrate using four IDT78C16A (2K x 8)
EEPROMs in lead less chip carriers. Functional equivalence to
monolithic 64K EEPROMs is achieved by utilization of an on-board
decoder circuit that interprets the higher order address All and A12
to select one of the four 2K x 8 EEPROMs.
_The IDT78M64 offers a reduced power standby mode. When
CE goes HIGH, the circuit will automatically go to, and remain in, a
standby mode as long as these conditions are held. In standby
mode, the module consumes less than 440mW. Substantially
lower power levels can be achieved in the IS81 mode (less than
20mWmax.).
The pinout of the IDT78M64 Is equivalent to monolithic 64K
EEPROMs. Its fast read access time allows zero wait state read
cycles with high-performance microprocessors.
All IDT module semiconductor components are manufactured
in compliance with the latest revision of MIL-STD-883, Class B,
making them ideally suited to military temperature applications
demanding the highest level of performance and reliability.

• On-chlp timer
- Automatic byte erase before write
- Byte write 10ns max.
•
•
•
•
•
•
•
•
•

DATA POlling-detection of write cycle completion
Utilizes IDT78C16As-high-performance 16K EEPROMs
Single 5V (±10%) power supply
Data protection circuitry (Vee lockout for Vee < 3.8V)
Provides data integrity on power up/power down
Minimum endurance of 10,000 write cycles per byte
Endurance failure rate < 0.1% per 1000 cycles
Available In 28-pin, 600 mil DIP
Military modules available with semiconductor components
compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

I/Do-I/Or

WE

t5E

-

IDT78C16A
2Kx8
CMOS
EEPROM

-----

'--

IDT78C16A
2Kx8
CMOS
EEPROM

IDT78C16A
2Kx8
CMOS
EEPROM

~

'--'---

IDT78C16A
2Kx8
CMOS
;::
..... EEPROM

~

~

l

~

,.

-

,.

,-

,. DECODER
::>,.

-

CEMOS Is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
OSC-8008/-

12-22

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1DT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT)

PIN CONFIGURATIONS

NC

Vee

A12

~

NC

A7
As

A6
Ag
All

A5
A4

~

A3
A2

Al0

cr

Al
Ao
1/00

I/~

I/Oa
1/05

1/01
1/02
GND

1/04
1/03

DIP
TOP VIEW

PIN NAMES

DEVICE OPERATIONAL MODE (1)
MODE
~

CE

'OE

WE

Read

\'JL

VIL

VIH

DATAoUT (00 - 0 7)

Byte Write

\'JL

VIH

VIL

DATA IN (10 - 17)

Standby

\'JH

Don't
Care

Don't
Care

High Z

Don't
Care

VIL

Don't
Care

High Z

Don't
Care

Don't
Care

VIH

HighZ

Write Inhibit

1/00 -1/0 7

NOTE:

1. All control inputs are TIL-compatible.

12-23

Ao - A12

Addresses

cr

Chip Enable

DE"

Output Enable

~

Write Enable

1/00 - 1/07

Data Input (10 - 17) during write;
Data Output (00 - 0 7) during read

IDT7SM64 64K CMOS EEPROM MODULE (SK x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

READ MODE

Write Inhibit

Chip Enable (CE) and Output Enable (OE) must be logically
active in order for data to be available at the outputs. After a selected byte address is sta~ CE is taken to a TTL LOW (enabling
Chip). The Write Enable (WE) pin should remain deselected (TTL
HIGH) during the entire read cycle. Data is gated from the device
outputs by selecting the OE pin (TTL LOW).

Holding either OE LOW, WE HIGH or CE HIGH during a poweron and power-off will inhibit inadvertent writes.

DATA POLLING
The IDT7BM64 has a maximum write cycle time of 10ms; a write
will always be completed in less than the maximum cycle time.
Write cycle completion is readily determined via a simple software
routine (DATA Polling) that performs a read operation while the
device is in an automatic write mode. If a read command (addressed to the last byte written) is given while the IDT7BM64 is still
writing, the inverse of the most significant bit (1/07 pin) of the last
byte written will be present. True data is not released until the write
cycle is completed. Thus, a DATA polling monitor of the output (or
periodic read of the last written byte) for true data can be used to
detect early completion of a write cycle.

WRITE MODE
The IDT78M64 Is programmed electrically in-circuit and does
not require any external latching, erasing or timing. Writing to the
IDT78M64 is as easy as writing to a static RAM. When a write cycle
is initiated the device automatically latches the address, data and
control signals as it begins its write operation.
A write cycle Is initiated when both CE and WE are LOW and
OE is HIGH. The IDT78M64 supports both a CE and WE controlled write cycle. All inputs, except for data, are latched on the
falling edge of either CE orWE, whichever occurs last. Data isthen
latched in by the rising edge of either CE or WE, whichever occurred first. An automatic byte erase of the existing data at the addressed location is performed before the new data byte is written.
Once initiated, a byte write operation will automatically proceed to
completion within 10ms.

ENDURANCE
lOT's EEPROM technology employs the Industry accepted
Fowler-Nordheim tunneling across a thin oxide. IDT7BM64
EEPROM modules are designed and tested for applications requiring extended endurance.
The endurance failure mechanism associated with EEPROMs
results from the charge trapping In the thin tunneling dielectric.
This failure is a function of the number of write cycles that each byte
in the part has experienced. Trapped charges accumulate slowly
with each write cycle and eventually become large enough to prevent reliable writing to the cell. Since some bits may be more sensitive than others, an endurance failure is typically a single bit failure
(i.e~ a failure of a single bit to properly write or retain data).
To test for endurance, a sample of devices is written 10,000
times at every byte location and checked for data retention capability. IDT test screens ensure that shipped devices will write a minimum of 10,000 times (at every byte location) with a maximum failure rate of 1%. This means that up to 1% of a sample of devices will
fail to write or retain data after being written to 10,000 times. Those
devices that do fail typically have a single bit(s) that fails to retain
data after being written.
For more detailed information please refer to the IDT Reliability
Report on Endurance.

STANDBY MODE
The IDT78M64 features a standby mode which reduces the
maximum active current from 250mA to BOmA for TTL levels and to
4mA for CMOS levels. With CE ~ VIH, all outputs are in the high
impedance state.

DATA PROTECTION
Nonvolatile data is protected from inadvertent writes in the following manner:

Power Up/Down
On-chip circuitry provides protection against false write during
Vee power up/down. The IDT78M64 features an internal sensing
circuit that disables the internal.2r9~ming circuit if Vee < 3.BV.
This prevents input signals at CE, WE and OE from triggering a
write cycle during a Vee power upldown event.

Noise Protection
The IDT7BM64 will typically reject write pulses that are less than
15ns. This prevents the initiation of a write cycle by a noise occurence.

12-24

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7SM64 64K CMOS EEPROM MODULE (SK X S-BIT)

ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

RECOMMENDED OPERATING

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

10Lrr

DC Output Current

50

50

mA

TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
GND
GRADE
Vec
TEMPERATURE
Military
-55°C to + 125°C
OV
5.0V ± 10%
Commercial

O°C to +70°C

5.0V ± 10%

OV

RECOMMENDED DC OPERATING CONDITIONS
MIN.

TYP.

MAX.

Vee

Supply Voltage

4.5

5.0

5.5

VIH
VIL

Input High Voltage

2.2

3.5

6.0

V

Input Low Voltage

-0.3

0.4

0.8

·V

VWI

Write Inhibit

3.8

-

-

SYMBOL

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may aff~ct reliability.

PARAMETER

UNIT
V

V

CAPACITANCE (TA= +25°C, f = 1.0MHz, Vec = 5.0V)
PARAMETER(1)

SYMBOL
CIN

ENDURANCE

Input Capacitance

CONDITIONS

TYP.

"IN = OV

VOLrr = OV
Output CapaCitance
GaUT
NOTE:
1. This parameter is sampled and not 100% tested.

PARAMETER
Minimum Endurance

UNIT

28

pF

33

pF

DC ELECTRICAL CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified
TA = OOC to + 70°C

Vee = 5.0V ± 10% (Commercial)

TA = -55°C to +125°C
VLe = 0.2V
CL = 30pF

Vee = 5.0V±10% (Military)
VHe = Vee -0.2V

SYMBOL
Ilu l

PARAMETER

TEST CONDITIONS

MIN.

MAX.

UNIT

Input Leakage Current

Vee = Max., "'N = GND to Vee

-

15

JlA

-

15

JJA

250

rrA

Output Leakage Current

CE = \'IH orOE = VIH,
VI/a = GND to Vee

leel

Operating Power Supply Current
Vee = Max., f = 0

CE = VIL,
h/o = OmA

lee2

Dynamic Operating CUrrent
Vee = Max., f = fMAX

CE = VIL,
11/0 = OmA

-

250

rrA

ISB

Standby Power Supply Current
(TTL Level)

-

SO

rrA

ISBl

Full Standby Power Supply Current
(CMOS Level)

CE ~ "'H, Vee = Max., 11/0 = OmA
VIN ~ VIH or 0 :5\ojN :5 VIL
CE ~ VHe , Vee = Max., 11/0 = OmA
VIN ~ Vee ~0.2V or 0 :5"'N :5 0.2V

-

4.0

rrA

VOL

Output Low Voltage

Vee = Min., 10L = SmA

-

0.4

V

VOH

Output High Voltage

Vcc = Min.,l oH = -4mA

2.4

-

V

IILOI

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels

GNDto 3.0V
5ns
1.5V
1.5V

12-25

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT)

AC ELECTRICAL CHARACTERISTICS

(Vcc = 50V +10% C L = 30pF)
MILITARY ONLY

SYMBOL

PARAMETER

78M64120/150
MIN.
MAX.

78M6485/100
MIN. MAX.

78M64250 78M64300 78M64350
78M64200
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

UNIT

READ CYCLE
300

70

-

5

-

5

-

5

-

0

30

0

30

0

30

-

5

-

120/150

-

200

120/150

-

200

60/65

-

70

-

5

-

5

Output Enable to Output in Low Z

5

-

5

-

tCHZ

Chip Disable to Output in High Z

0

30

0

tOHZ

Output Disable to Output in High Z

0

30

tOH

Output Hold from Address Change

5

-

85/100

Output Enable to Output Valid

-

tCLZ

Chip Enable to Output in Low Z

toLZ

tCE

Chip Enable Access Time

tAA

Address Access Time

tOE

AC ELECTRICAL CHARACTERISTICS

85/100

250

70

-

-

350

ns

350

ns

70

5

-

ns

5
5

-

ns

5

-

5

30

30

0

30

0

30

0

ns

0

30

0

30

0

30

5

ns

5

-

5

-

5

-

ns

250

300
70

ns

(Vcc - 50V +10% C L = 30pF)
COMMERCIAL ONLY

SYMBOL

PARAMETER

78M6470
MIN. MAX.

78M6485
MIN. MAX.

78M64100
MIN. MAX.

78M64120
MIN. MAX.

78M64150
MIN.
MAX.

78M64200
MIN. MAX.

UNIT

READ CYCLE
tCE

Chip Enable Access Time

-

85

Address Access Time

-

70

tAA

70

-

85

tOE

Output Enable to Output Valid

-

50

-

60

tcLZ

Chip Enable to Output in Low Z

5

-

5

toLZ

Output Enable to Output in Low Z

5

-

5

tCHZ

Chip Disable to Output in High Z

0

20

tOHZ

Output Disable to Output in High Z

0

tOH

Output Hold from Address Change

5

AC ELECTRICAL CHARACTERISTICS

-

100

-

5
5

0

20

20

0

-

5

-

200

-

5

0

20

-

-

120

-

150

120
70

-

70

-

5

-

5

5

5

0

20

0

20

20

0

20

0

-

5

-

5

100
65

150

ns

200

ns

70

ns

-

ns

5

20

0

20

ns

0

20

0

20

ns

5

-

5

-

ns

ns

(Vcc = 5.0V +10%, All Temperature Ranges; C L = 30pF)

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

WRITE CYCLE
t AS

Address Set-up Time

5

-

ns

tAH

Address Hold Time

50

ns

tos

Data Set-up Time

20

tOH

Data Hold from Write Time

15

-

ns

ns

tOES

Output Enable Set-up Time

5

-

ns

tOEH

Chip Enable Hold from Write Time

15

ns

tCES

Chip Enable Set-up Time

0

tCEH

Chip Enable Hold Time

0

twp

Write Pulse Width

50

-

tWB

Byte Write Cycle

ns
ns
ns

tOBv

DATA Polling to DATA Valid

-

tWH

Write Hold Time

15

top

End of Write Pulse to DATA Polling

15

t WES

Write Enable Set-up Time

0

-

tWEH

Write Enable Hold Time

0

-

ns

tov

Data Valid Time

-

1

J.ls

NOTES:
1. Data must be valid within 1jJs maximum and must remain valid if twp is longer than 1J.ls.
2. This parameter is guaranteed but not tested.

12-26

10

ms

tOE
ns
ns
ns

IDT7SM64 64K CMOS EEPROM MODULE (SK x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1(t)

ADDRESS

DATA OUT
NOTE:
1. WE is HIGH for Read Cycle.

TIMING WAVEFORM OF READ CYCLE NO.

ADDRESS

DATA OUT
NOTE:
1. WE is HIGH; CE

2(1)

t; t~-t=1. i= to"=1_
_________

~

= '1L; OE = '1L

TIMING WAVEFORM OF READ CYCLE NO.

3(1)

DATA OUT
NOTE:
1. WE is HIGH; OE = V1L ; address valid prior to or coincident with CE transition LOW.

12-27

DATA VALID

~

IDT78M64 64K CMOS EEPROM MODULE (8K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1, WE CONTROLLED

ADDRESS

DATA IN

TIMING WAVEFORM OF WRITE CYCLE NO.2, CE CONTROLLED

.......- - - tAH - - - - . !

ADDRESS

DATA IN

12-28

~~~(~~~~-r~~~~----

IDT7SM64 64K CMOS EEPROM MODULE (SK x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA POLLING

~
READ
BYTE
N

.~READ
BYTE
N

NOTE:
1. Most significant bit 01 the byte being written is inverted and available at I/O 711 a Read command is issued. All other outputs are high impedance at this
time. True data will not be released until the Write cycle is completed.

ORDERING INFORMATION
lOT

xxxxx

x

Device Type

Process!
Temperature
Range

y:-

~------------~I 0
I

70

Commercial (O°C

to + 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STO-883, Class B
CEROIP

Commercial Only

85
L-----------------------~I

100
120
150
200
250
300
350

Speed in Nanoseconds
Military Only
Military Only
Military Only

Standard Power

64K (8K x 8-Bit) EEPROM Module

12-29

FEATURES:

DESCRIPTION:

• 5 volt only operation
• Fast access times
- Military: 70ns (max.)
- Commercial: 55ns (max.)

The IDT78C64A is a 5 volt only 8K x 8 Electrically Erasable Programmable Read-Only Memory (EEPROM). Fabricated using
IDT's CEMOS TM process, this EEPROM provides 64K bits of nonvolatile data storage (data retention in excess of 100 years).
The IDT78C64A features fast read access times, allowing zero
wait state read cycles with high-performance microprocessors.
Write time is automatically timed out by an internal timer and input
latches secure address/data information, freeing the host system
for other tasks during a write cycle. A 64-byte page mode allows 1
to 64 bytes to be written within a single write cycle, to minimize total
write time. The DATA Polling method for determining write cycle
completion is supported by the IDT78C64A. Data protection feature~nclude Vee lockout, write. inhibit, noise protection for
the WE pin and software write protection.
The IDT78C64A is function- and pinout-compatible with the
IDT7164, 8K x 8 static RAM. It is ideal for systems requiring nonvolatility and in-system data modifications.
The IDT78C64A Military EEPROM is manufactured in compliance to the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the
highest level of performance and reliability.

• On-chip timer
- Automatic byte erase before write
- Byte write 10ms max.
• DATA Polling-detection of write cycle completion
• 64-byte page write operation, page write 10ms max.
• Low-power CEMOS ™ technology
- Active Current: 100mA
- Standby Current (full CMOS): 0.9mA
• Data protection circuitry (Vee lockout for Vee < 3.8V)
provides data integrity on power up/power down
• Software write protection
• Minimum endurance of 10,000 write cycles per byte
• Endurance failure rate < 0.1% per 1000 cycles
• JEDEC approved byte-wide pinout
• Available in 28-pin DIP and 32-pin LCC
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

64-BYTE PAGE BUFFER

ADDRESS
INPUTS

Ao- A12

ADDRESS
BUFFERS
LATCHES &
DECODER

64K-BIT
EEPROM
ARRAY

CONTROL
LOGIC

I/O BUFFERS

DATA INPUTS/OUTPUTS 1/00

-

1/07

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
OSC-8oo5/-

12-30

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7SC64A FAST CMOS EEPROM 64K (SKxS-BIT)

PIN CONFIGURATIONS

NC

Vee

A12
A7

WE

Ae

A8

A5

A9

•

I

I. II

3 2

]

4
5

]

e

'-' '-' '-'

NC

...............
U
32 31
1
I

I

I

I

II

30

29 [:

28

C

A8
A9

Al1

A4

All

A4

]7

27 [:

A3
A2

OE'

A3

]

8

26[

NC

AlO
~

A2

]

9

25 [:

'OE'

Al

]

10

24 [:

AlO

I/~
I/0e

Ao

]

11

23 [:

~

NC

:1
:1

12

22C

I/~

21 [:
13
14 15 Ie 17 18 19 20

I/0e

Al
Ao

1/00
1/01
1/02

1/00

1/05
1/04
1/03

GND

L32-1
':

nnnnnnn

DIP
TOP VIEW

LCC
TOP VIEW

PIN NAMES

DEVICE OPERATIONAL MODE (1)
MODE
~

Ao - A12

Addresses
Chip Enable

DATAoUT (00 - 0 7)

CE
DE

VIL

DATA IN (10 -1 7)

WE

Write Enable

Don't
Care

Don't
Care

HighZ

1/00 - 1/07

Data Input (10 - 17) During Write;
Data Output (00 - 0 7) During Read

Don't
Care

VIL

Don't
Care

HighZ

Don't
Care

Don't
Care

VIH

HighZ

CE

O£

WE

Read

VIL

VIL

VIH

Byte Write

'ltL

VIH

Standby

'ltH

Write Inhibit

1/00 - 1/07

NOTE:
1. All control inputs are TTL-compatible.

12-31

Output Enable

FEATURES:

DESCRIPTION:

• 5 volt only operation
• Fast access times
- Military: 70ns (max.)
- Commercial: 55ns (max.)

The IDT78C464A is a 5 volt only 8K x 8 Registered Electrically
Erasable Programmable Read-Only Memory (Registered
EEPROM). Fabricated in IDT'sCEMOS process, this Registered
EEPROM provides 64K bits of non-volatile data storage (data
retention in excess of 100 years).
The IDT78C464A features fast read access times, allowing zero
wait state read cycles with high-performance microprocessors.
Write time is automatically timed out by an internal timer and input
latches secure address/data information, freeing the host system
for other tasks during a write cycle. A 64-byte page mode allows
one to 64 bytes to be written within a single write cycle to minimize
total write time. The DATA Polling method for determining write
cycle completion is supported by the IDT78C464A. Data protection features include Vee lock-out, write inhibit, noise protection for
the WE pin and software write protection.
The IDT78C464A has an initialize function (INIT) which activates an 8-bit word loaded into the on-Chip Initialize register. This
registered word is user-programmable with any desired word (i.e.
can be used to establish a PRESET or CLEAR word on the outputs). The IDT78C464A Military EEPROM is manufactured in compliance with the latest revision of MIL-STD-883, Class B , making it
ideally suited to military temperature applications demanding the
highest level of performance and reliability.

• On-chip timer
- Automatic byte erase before write
- Byte write 10ms max.
•
•
•
•
•

DATA Polling-detection of write cycle completion
64-byte page write operation, page write 10ms max.
On-chip edge triggered registers
Synchronous and asynchronous output enable
Programmable asynchronous register (INIT)

• Low-power CEMOS ™ technology
- 1OOmA active current
• Data protection circuitry (Vee lockout for Vee < 3.8V) provides
. data Integrity on power up/power down
• Software write protection
•
•
•
•

Minimum endurance of 10,000 write cycles per byte
Endurance failure rate < 0:1% per 1000 cycles
28-pin Dip, 32-pin LCC
Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

64-BYTE PAGE BUFFER

ADDRESS
BUFFERS
LATCHES &
DECODER

ADDRESS
INPUTS

Ao- A'2

64K-BIT
EEPROM
ARRAY

C'S-__--{]
~--t--..-a

mT

RCLK

-~~~-----4

-1~-+------~

~--------------~------------~

DATA INPUTS/OUTPUTS 1/0 0

-

1/07

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
05C-8006/-

12-32

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7SC464A FAST CMOS REGISTERED EEPROM 64K (SK x S-BIT)

PIN CONFIGURATIONS

mrr

Vee

A12

WE

I

4

A4

I

I

II

1

I I
L-I

I.
~

I

I

L.....I

32 31 30
29[:

]

6

28 [:

]

7

27 [:
26 [:

:] 8

OE"

A3
A2
Al
Ao

I I
L.....I

3 2 U

]5

A8
A9
All

A5

,., I
L..I

~

RCLK

A7
A6

25 [

]

9

CS

]

10

24 [

IIOr
IIDe

]

11

23 [:

1/00

:] 12

1/01

1/05

1/02

1/04
1/03

AlO

GND

22 [
21 [
:] 13
14 15 16 17 18 19 20

nnnnnnn

LCC
TOP VIEW

DIP
TOP VIEW

DEVICE OPERATIONAL MODES (1)
MODE
~

CS

WE

OE

H

X

L

Read

X

H

H

Read

H

H

L

Read

L

H

L

Write

L

L

X

Deselected

TBD

PIN NAMES

RCLK

S
X

S
S
X

1/0 0 - 1/07

Ao - A12

Addresses

HighZ

CS

Synchronous Output Enablel
Chip Enable (Write)

HighZ

C5"E"

Output Enable

High Z

~

Write Enable

Data Out at
Addresses

1/00

Data In at
Addresses

TN1T

Initialize

RCLK

Register Clock

NOTE:

1. ·X" = Don't Care

12-33

-

1/0 7

Data Input (10 - 17) During Write;
Data Output (00 - 07) During Read

FEATURES:

DESCRIPTION:

• 5 volt only operation

The IDT78C564A is a 5 volt only 8K x 8 Registered Electrically
Erasable Programmable Read-Only Memory (Registered
EEPROM) with Serial Protocol Channel (SPC). SPC complements
the EEPROM's parallel information path by providing a serial link
(four additional pins) by which its memory array can be written or
read. Fabricated using IDT's CEMOS ™ process, this EEPROM
provides 64K bits of non-volatile data storage (data retention in excess of 100 years).
The IDT78C564A features fast read access times, allowing zero
wait state cycles with high-performance microprocessors. Write
time is automatically timed out by an internal timer and input
latches secure address/data information, freeing the host system
for other tasks during a write cycle. A 64-byte write page buffer allows 1 to 64 bytes to be written within a single write cycle to minimize total write time. The DATA Polling method for determining
completion of the write cycle is supported by the IDT78C564A.
Data protection features include Vee lockout, write inhibit, noise
protection for the WE pin and software write protection.
The IDT78C564A is ideal for systems requiring nonvolatility and
in-system data modifications. With SPC, a serial link can be established during board la}o'out for easy field updates of code changes.
The initialize function (INIT) can be used to activate an 8-bit word
loaded into the on-chip Initialize register. This registered word is
user-programmable with any desired word.
The IDT78C564A Military EEPROM is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding the
highest level of performance and reliability.

• Fast access times
- Military: 70ns (max.)
- Commercial: 55ns (max.)
• Serial Protocol Channel (SPC) allows load and read-out of the
memory array over a 4-wire channel
• On-Chip timer
- Automatic byte erase before write
- Byte write 10ms max.
• DATA Polling-detection of write cycle completion
• 64-byte page write operation, page write 10ms max.
• On-chip edge triggered registers
• Programmable asynchronous register (INIT)
• Low-power CEMOS ™ technology
- Active Current: 100mA
• Data protection. circuitry (Vee lockout for Vee < 3.8V)
provides data integrity on power up/power down
• Software write protection
• Minimum endurance of 10,000 write cycles per byte
• Endurance failure rate < 0.1% per 1000 cycles
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

SERIAL {
SDI
SERIAL PROTOCOL CHANNEL
1-----1-_ SDO} SERIAL
DATA IN
SCLK
C/I:) _ _ _ _ _ _ _ _ _-.~------------~------------~
DATAo~

64-BYTE PAGE BUFFER

ADDRESS
INPUTS

64K-BIT
EEPROM
ARRAY

Ao- A12

CS--...--a
wr:. ---!--.--a
mi -~-~----~

RCLK

-1--1--r------~

~------------~-------------

DATA INPUTS/OUTPUTS 110 0 -1/0 7
CEMOS and SPC are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

DECEMBER 1987
DSC-8oo7/-

1987 Integrated Device Technology, Inc.

12-34

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7SC564A FAST CMOS EEPROM 64K (SKxS-SIT)

PIN CONFIGURATIONS
(CONSULT FACTORy)

DEVICE OPERATIONAL MODES(1)

~

CE

WE.

Deselected

H

X

L

Read

X

H

H

Read

H

H

L

Read

L

H

L

Write

L

L

X

MODE

OE

RCLK

S

PIN NAMES
1/00 -1/0 7
HighZ

Ao - A12

Addresses

CS

Synchronous Output Enable/Chip
Enable (Write)

HighZ

DE

Output Enable

S

HighZ

WE

Write Enable

S

Data Out at
Addresses

1/00 - 1/07

Data Input (10 - 17) During Write;
Data Output (0 0 - 0 7) During Read

Data In at
Addresses

SOl

Serial Data Input

X

X

NOTE:
1. X = Don't Care

SPC OPERATIONAL MODES (1)
MODE
"CE
O"E
WE
lm5

SCLK

SDO

Serial Data Output

SCLK

Data Clock Input

C/O

Command/15ata

INTi

Initialize

RCLK

Register Clock

FUNCTION

Command

X

X

X

H

S

Shift bit into command register

Data

X

X

X

L

S

Shift bit into data register

Execute

X

X

X

S

Execute command during time
between C/D and SCLK

S

NOTE:

1. X = Don't Care

12-35

FEATURES:

DESCRIPTION:

• 5 volt only operation
• Fast access times
- Military: 70ns (max.)
- Commercial: 55ns (max.)

The IDT78C256A is a 5 volt only 32K x 8 Electrically Erasable
Programmable Read Only Memory (EEPROM). Fabricated using
IDT's CEMOS process, this EEPROM provides 256K bits of nonvolatile data storage (data retention in excess of 100 years).
The IDT78C256A features fast read access times allowing zero
wait state read cycles with high-performance microprocessors.
Write time is automatically timed out by an internal timer and input
latches secure address/data information, freeing the host system
for other tasks during a write cycle. A 64-byte page mode allows
1 to 64 bytes to be written within a single write cycle to minimize
total write time. The DATA Polling method for determining write
cycle completion is supported by the IDT78C256A. Data
protection features include Vcc lockout, write inhibit, noise protection for the WE pin and software write protection.
The IDT78C256A is function and pinout compatible with the
IDT71256. 32K x 8 static RAM. It is ideal for systems requiring nonvolatility and in-system data modifications. The IDT78C256
military EEPROM is manufactured in compliance with the latest
revision of MIL-STD-883. Class B. making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.

• On-chip timer
- Automatic byte erase before write
- Byte write 10ms max.
• DATA Polling-detection of write cycle completion
• 64-byte page write operation (page write 10ms max.)
• Low-power CEMOS ™ technology
- Active Current: 100mA
- Standby Current (full CMOS): 0.9mA
• Data protection circuitry (Vee lockout for Vcc < 3.8V)
provides data integrity on power up/power down
• Software write protection
• Minimum endurance of 10,000 write cycles per byte
• Endurance failure rate < 0.1% per 1000 cycles
• JEDEC approved byte wide pinout
• Available in 28-pin DIP and 32-pin LCC
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

64-BYTE PAGE BUFFER

ADDRESS
INPUTS

1.0- A14

ADDRESS
BUFFERS
LATCHES &
DECODER

256K-BIT
EEPROM
ARRAY

CONTROL
LOGIC

110 BUFFERS

DATA INPUTS/OUTPUTS 110 0

-

1/07

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology, Inc.

DECEMBER 1987
OSC-8oo2/-

12-36

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT78C256A FAST CMOS EEPROM 256K (32K x 8-BIT)

PIN CONFIGURATIONS

Vee

A14
A12
A7

wr:

LJUUIIULJU
4 3 2 U 32 31 30

A13

Ae

A8
A9
All

As
A4

Ae ]

5

]

e

:1

7

]

8

]

9

1

29 [

CONTACT
FACTORY
FOR
PACKAGE
INFO

27 [:

26[

A3

'OE"

A2

Al0

Al
Ao

CE'

]

10

IIOr

]

11

23 [:

1/00
1/01
1/02

I/0e

:1
:1

12

22[

1/05

24 [

21 [:
17

18 19

20

:::::::: a oocS

6Q

DIP
TOP VIEW

OO
Z ::::::::::::

LCC
TOP VIEW

PIN NAMES

DEVICE OPERATIONAL MODE (1)
MODE
~

13
14 15 le

25 [

nnnnnnn

1104
1103

GND

A8

28 [:

Ao - A14

Addresses

CE'

Chip Enable

CE

Ol:

WE

Read

~L

V'L

V'H

DATAoUT (00 - 0 7)

"OE"

Output Enable

Byte Write

~L

V'H

V'L

DATA'N (10 -1 7)

wr:

Write Enable

Standby

~H

Don't
Care

Don't
Care

HighZ

1100

Data Input (10 - 17) During Write
Data Output

Don't
Care

V'L

Don't
Care

1107
HighZ

Don't
Care

Don't
Care

V'H

HighZ

Write Inhibit

1/00 -1/0 7

NOTE:
1. All control inputs are TTL-compatible.

12-37

(00 -

0 7) During Read

FEATURES:

DESCRIPTION:

• 5 volt only operation
• Fast access times
- Military: 70ns (max.)
- Commercial: 55ns (max.)

The IDT78C4256A is a 5 volt only 32K x 8 Registered Electrically
Erasable Programmable Read-Only Memory (Registered
EEPROM). Fabricated in IDT's CEMOS process, this Registered
EEPROM provides 256K bits of non-volatile data storage (data
retention in excess of 100 years).
The IDT78C4256A features fast read access times allowing zero
wait state read cycle with high-performance microprocessors.
Write time is automatically timed out by an internal timer and input
latches secure address/data information, freeing the host system
for other tasks during a write cycle. A 64-byte page mode allows
one to 64 bytes to be written within a single write cycle to minimize
total write time. The DATA Polling method for determining write
cycle completion is supported by the IDT78C4256A. Data protection features include Vcc lock-out, write inhibit, noise protection for
the WE pin and software write protection.
The IDT78C4256A has an initialize function INIT which activates an 8-bit word loaded into the on-chip Initialize register. This
registered word is user programmable with any desired word (Le.
can be used to establish a PRESET or CLEAR word on the outputs). The IDT78C4256A military EEPROM is manufactured in
compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding
the highest level of performance and reliability.

• On-chip timer
- Automatic byte erase before write
- Byte write 10ms max.
• DATA Polling-detection of write cycle completion
• 64-byte page write operation, page write 10ms max.
• On-chip edge triggered registers
• Synchronous and asynchronous output enable
• Programmable asynchronous register (INIT)
• Low-power CEMOS ™ technology
- 100mA active current
• Data protection circuitry (Vcc lockout for Vcc < 3.8V) provides
data integrity on power up/power down
• Software write protection
• Minimum endurance of 10,000 write cycles per byte
• Endurance failure rate < 0.1% per 1000 cycles
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

64-BYTE PAGE BUFFER

ADDRESS
INPUTS

Ao- A14

ADDRESS
BUFFERS
LATCHES &
DECODER

256K BIT
EEPROM
ARRAY

cs-...---a

~==t=~~~~~--~----------~~~--~~U:Ze1

RCLK -.~--~----------~

~------------~------------~

DATA INPUTS/OUTPUTS 1/0 0 - 1/07

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology. Inc.

DECEMBER 1987
OSC-8oo3/-

12-38

1DT78C4256A FAST CMOS REGISTERED EEPROM 256K (32K x B-BIT)

MILITARY AND COMMERCIAL TEMPEI;IATURE RANGES

PIN CONFIGURATION

TO BE DETERMINED

DEVICE OPERATIONAL MODES (1)
MODE
~

~

WE

OE

PIN NAMES

RCLK

j

Ao- A14

Addresses

HighZ

~

Synchronous Output Enable!
Chip Enable (Write)

HighZ

~

Output Enable

1/00 -1/07

Deselected

H

X

L

Read

X

H

H

Read

H

H

L

j

HighZ

wr:.

Write Enable

Read

L

H

L

j

Data Out at
Addresses

1/00 - 1/07

Data Input (10 - 17) During Write;
Data Output (00 - 0 7 ) During Read

Write

L

L

X

Data In at
Addresses

TNTT

Initialize

RCLK

Register Clock

X

X

NOTE:

1. ·X· = Don't Care

12-39

FEATURES:

DESCRIPTION:

•

The IDT78C5256A is a 5 volt only 32K x 8 Electrically Erasable
Programmable Read Only Memory (EEPROM) with Serial Protocol
Channel (SPC). SPC complements the EEPROM's parallel information path by providing a serial link (4 additional pins) by which
its memory array can be written or read. Fabricated in lOT's
CEMOS process, this EEPROM provides 256K bits of nonvolatile
data storage (data retention in excess of 100 years).
The IDT78C5256A features fast read access times allowing zero
wait state cycles with high-performance microprocessors. Write
time is automatically timed out by an intemaltimer. and Input
latches secure address/data information, freeing the host system
for other tasks during a write cycle. A 64-byte write page buffer
allows 1 to 64 bytes to be written within a single write cycle to minimize total write time. The DATA Polling method for determining
completion of the write cycle is supported by the IDT78C5256A.
Data protection features include Vee lockout, write inhibit, noise
protection for the WE pin and software write protection.
The IDT78C5256A is ideal for systems requiring nonvolatility
and in-system data modifications. With SPC, a serial link can be
established during board layout.JQr. easy field updates of code
changes. The initialize function (INIT) can be used to activate an
8-bit word loaded into the on-chip Initialize register. This registered
word is user programmable with any desired word. The
IDT78C5256A military EEPROM is manufactured in compliance
with the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the highest
level of performance and reliability.

5 volt only operation

• Fast access times
- Military: 70ns (max.)
- Commercial: 55ns (max.)
• Serial Protocol Channel (SPC) allows load and readout of the
memory array over a 4-wire channel
• On-chip timer
- Automatic byte erase before write
- Byte write 10ms max.
• DATA Polling-detection of write cycle completion
• 64-byte page write operation (page write 10ms max.)
• On-chip edge triggered registers
• Programmable asynchronous register (INIT)
• Low-power CEMOS TM technology
- Active Current: 100mA
• Data protection circuitry fYee lockout for Vee < 3.8V)
provides data integrity on power up/power down
• Software write protection
• Minimum endurance of 10,000 write cycles per byte
• Endurance failure rate < 0.1 % per 1000 cycles
• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM
SDI
SERIAL
SClK
SERIAL PROTOCOL CHANNEL
1 - - - 1 - _ SDO} SERIAL
DATA IN { . cf[5 _ _ _ _ _ _ _ _ _-.~------------~------------~
DATAo~

54-BYTE PAGE BUFFER

ADDRESS
INPUTS

256K-BIT
EEPROM
ARRAY

Ao- A14

cs -....----0
--1--..--0

WE"
mT

-;-~-----,

RClK - . - I - - i - - - - - - - i

~--------------~------------~

DATA INPUTS/OUTPUTS 1/0 0 -1/0 7
CEMOS and SPC are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
DSC-8004/-

12-40

IDT7SC5256A FAST CMOS EEPROM WITH SPCTM
256K (32K x S-BIT)

MILITARY AND COMMERCIALTEMPERATURE RANGES

PIN CONFIGURATIONS
(CONSULT FACTORy)

DEVICE OPERATIONAL MODES(1)
MODE
~

cs WE

OE

RCLK

--1

PIN NAMES
Ao - A14

Addresses

HighZ

CS

Synchronous Output Enable/
Chip Enable (Write)

1/00 -1/07

H

X

L

Read

X

H

H

X

HighZ

DE"

Output Enable

Read

H

H

L

--1

HighZ

~

Write Enable

Read

L

H

L

j

Data Out at
Addresses

1/00
1/07
SDI

Data Input (10 - 17) during write
Data Output (0 0 - 0 7) during read
Serial Data Input

Write

L

L

X

SDO

Serial Data Output

SCLK

Data Clock Input

C/l>

Command/Data

TNlT

Initialize

RCLK

Register Clock

Deselected

Data In at
Addresses

X

NOTE:
1. X = Don't care

SPC OPERATIONAL MODES(1)
MODE

CE

OE

WE

CIO

Command

X

X

X

H

S

Shift bit into command register

Data

X

X

X

L

S

Shift bit into data register

Execute

X

X

X

I-

S

Execute co!!}mand during time
between CIO and SCLK

SCLK

FUNCTION

NOTE:

1. X = Don't Care

12-41

Subsystems Modules

SUBSYSTEM PRODUCTS .INTRODUCTION
A unique combination of resources and experience sets the
Subsystems Division apart from its competitors. lOT's advanced
technology, multiple manufacturing plants and the backing of sister divisions allow us to offer a diverse range of module products
quickly and cost-effectively. In addition, our capabilities are flexible enough to include standard and custom modules, as well as a
complete, self-contained, U.S.-based military device assembly
and module operation.
lOT's subsystems provide a modular approach which allows
designers to meet several important criteria needed In a modem
electronics system. These features include:
High Performance
High Reliability
Compact Size
Low Power
Quick Design Time
Ease of Manufacture
Competitive Cost

High-performance CMOS products in surface mounted packages are combined with thermally matched substrates to produce
very dense and highly reliable modules. Conventional pins are
then attached to these modules so that they can be plugged Into a
circuit board in a conventional through-hole manner.
This process allows production of a Megabit static RAM in a
standard size dual in-line package several years before the avail·
able technology can produce a comparable monolithic device. In
addition, an application specific product can be manufactured that
could not be easily or cost-effectively produced as a monolithic device. These ASIC products can include error detection, parity, address latching or buffering and wide words (x16 and x32).
Complete memory systems, such as megabyte-size highspeed caches or writable control stores, can also be produced on a
single plug-in module. Systems can now be designed with the major memory portions supplied as a single fully-tested high density
component. This approach gives customers access to surface
mount technology without the need to invest in special design,
manufacturing and testing facilities.

TABLE OF CONTENTS
CONTENTS

I'
I

Subsystems Modules
Subsystem Ordering Information Page
Static RAM Modules
lDT7MB624
1 Megabit (64K x 16) CMOS SRAM (Plastic DIP) ...........................................
IDT7MC156
256K x 1 CMOS SRAM (Ceramic SIP) ............................. ~ .. , ........ '" ........
IDT7MC4001
1 Megabit (1024K x 1) CMOS SRAM w/Separate I/O (Ceramic SIP) ............................
IDT7MC4032
512K (16K x 32) CMOS SRAM (Ceramic Dual SIP) ................ "..... ........ ... ...... ....
IDT7MP156
256K (256K x 1) CMOS SRAM (Plastic SIP) .................. : ......... , . ..... .... . ........
IDT7MP456
256K (64K x 4) CMOS SRAM (Plastic SIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT7MP564
80K (16K x 5) CMOS SRAM (Plastic SIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT7MP4008
4 Megabit (512K x 8) CMOS SRAM (Plastic SIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1 Megabit (64K x 16) CMOS SRAM ......................................................
" IDT7M624
IDT7M656
256K (16K x 16) CMOS SRAM ..........................................................
IDT7M812
512K (64K x 8) CMOS SRAM ...........................................................
IDT7M856
256K (32K x 8-Bit) CMOS Static RAM ....................................................
IDT7M912
512K (64K x 9) CMOS SRAM ...........................................................
IDT7M4016
4 Megabit (256K x 16) CMOS SRAM .....................................................
IDT7M4017
2 Megabit (64K x 32) CMOS SRAM ......................................................
IDT8MP612
512K (32K x 16) CMOS SRAM (Plastic SIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT8MP624
1 Megabit (64K x 16) CMOS SRAM (Plastic SIP) " .................. . .......... ......... ....
IDT8MP628
128K (8K x 16) CMOS SRAM (Plastic SIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT8MP656
256K (16K x 16) CMOS SRAM (Plastic SIP) .. ..... ................... ........ .. ............
IDT8MP824
1 Megabit (128K x 8) CMOS SRAM (Plastic SIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT8M612
512K (32K x 16) CMOS SRAM ..........................................................
IDT8M624
1 Megabit (64K x 16) CMOS SRAM ......................................................
IDT8M628
128K (8K x 16) CMOS SRAM ;..........................................................
IDT8M656
256K (16K x 16) CMOS SRAM ..........................................................
IDT8M824
1 Megabit (128K x 8) CMOS SRAM ......................................................
IDT8M856
256K (32K x 8) Low-Power CMOS SRAM .......................... . ......... ..............
Dual-Port RAM, FIFO and Application Specific Memory Modules
IDT7MB6042
8K x 112 High-Speed Writable Control Store w/SPC (14-154) ............................. ....
IDT7MP6025
512K (64K x 8) Synchronous SRAM (Plastic SIP) ...........................................
IDT7M134
64K (8K x 8) Dual-Port RAM (14-9, 14-68, 14-260) .........................................
IDT7M135
128K (16K x 8) Dual-Port RAM (14-9, 14-68, 14-260) .......................................
IDT7M137
256K (32K x 8) Dual-Port RAM (14-9, 14-68, 14-260) .......................................
IDT7M144
64K (8K x 8) Dual-Port RAM (SLAVE) (14-9,14-68,14-260) ..................................
IDT7M145
128K (16K x 8) Dual-Port RAM (SLAVE) (14-9, 14-68, 14-260) ................................
IDT7M203
CMOS Parallel In-Out FIFO Module 2K x 9-Bit & 4K x 9-Bit ...................................
IDT7M204
CMOS Parallel In-Out FIFO Module 2K x 9-Bit & 4K x 9-Bit ..... ........ ....... .... ...........
IDT7M205
8K x 9 FIFO (14-1, 14-254, 14-257) . . . . . . . . . . . . .. . . .. . .. . .. . .. . . . . . .... . . . . . . . . . . . . . . . . ..
IDT7M206
16K x 9 FIFO (14-1, 14-254, 14-257) . " ................................................. ,
IDT7M824
1 Megabit (128K x 8) Registered and Buffered SRAM Subsystem Family. . . . . . ... . . . . ... .. . . .. ..
IDT7M820
128K x 8 SRAM w/Latched Address, Latched Data In, Latched Data Out. . . .. . . . . . . .. . . . . .. ..
IDT7M821
128K x 8 SRAM w/Latched Address, Registered Data In, Registered Data Out ................
IDT7M822
128K x 8 SRAM w/Latched Address, Registered Data In, Latched Data Out. . . . . . . . . .. . . . . . . ..
IDT7M823
128K x 8 SRAM w/Latched Address, Latched Data In, Registered Data Out. . . . . . . . . . . . .. . .. ..
IDT7M825
128K x 8 SRAM w/Registered Address, Registered Data In, Registered Data Out ..............
IDT7M826
128K x 8 SRAM w/Registered Address, Registered Data In, Latched Data Out ................
IDT7M827
128K x 8 SRAM w/Registered Address, Latched Data In, Registered Data Out ................
IDT7M828
128K x 8 SRAM w/Registered Address, Latched Data In, Latched Data Out..... ..............
IDT75M48
a-Bit Flash ADC ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT75M49
9-Bit Flash ADC ....................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDT75MB38
Triple 8-Bit Video DAC Module (14-266) ...................................................
IDT7M6001
Dual, Multiplexed 16K x 20 SRAM .......................................................
IDT7M6032
16K x 32 High-Speed Writable Control Store w/SPC (14-154) .................................
IDT78M64
8K x 8 EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

PAGE

13-1
13-3
13-9
13-15
13-17
13-23
13-29
13-35
13-41
13-48
13-57
13-63
13-57
13-70
13-72
13-74
13-74
13-80
13-80
13-86
13-92
13-92
13-99
13-99
13-107
13-113
13-121
13-123
13-125
13-125
13-135
13-142
13-142
13-146
13-146
13-157
13-157
13-168
13-172
13-175
13-178
13-181
13-184
13-187
13-190
13-193
11-58
11-59
11-23
13-197
13-199
12-22

------------------------------------

MODULE PART NUMBER GUIDE

DEVICE TYPE

POWER SPEED

PACKAGE PROCESS

I

~
I

BLANK -

COMMERCIAL 0° C to + 70°C

B

Military-55°Cto+125°C

-

SEE PACKAGE TABLE
SPEED - Guaranteed Minimum
Performance in Nanoseconds
POWER -

S - Standard Power
L - Low Power

' " - - - - - - - - - - - - - - - - - - ; Device Type

PACKAGE TABLE
CODE

SUBSTRATE

COMPONENTS

C

CO-FIRED CERAMIC SIDEBRAZE, DUAL IN-LINE

CERAMIC

N

CO-FIRED CERAMIC SIDEBRAZE, DUAL IN-LINE

PLASTIC

P

FR4 EPOXY LAMINATE, DUAL IN-LINE

PLASTIC

S

FR4 EPOXY LAMINATE, SINGLE IN-LINE (SIP)

PLASTIC

CS

CO-FIRED CERAMIC, SINGLE IN-LINE

CERAMIC

Z

FR4 EPOXY LAMINATE, STAGGERED SIP (ZIP)

PLASTIC

V

FR4 EPOXY LAMINATE, VERTICAL, DUAL ROW (SIP TYPE)

PLASTIC

CV

CO-FIRED CERAMIC, VERTICAL, DUAL ROW (SIP TYPE)

CERAMIC

K

FR4 EPOXY LAMINATE, QUAD IN-LINE (QIP)

PLASTIC

CK

CO-FIRED CERAMIC, QUAD IN-LINE

CERAMIC

FEATURES:

DESCRIPTION:

• High-density 1024K-bit CMOS static RAM module

The IDT7MB624 is a 1024K-bit high-speed CMOS static RAM
constructed on an epoxy laminate substrate using 16 IDT7187
(64K x 1) static RAMs in plastic surface mount packages. Making
four chip select lines available (one for each group of 4 RAMs) allows the user to configure the memory into a 64K x 16, 128K x 8 or
256K x 4 organization. In addition, extremely high speeds are
achievable by the use of IDT7187s fabricated in lOT's highperformance, high-reliability CEMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides the fastest 64K static RAMs available.
The IDT7MB624 is available with access times as fast as 25ns
over the commercial temperature range, with maximum operating
power consumption of only 9.6W (significantly less if organized
128K x 8 or 256K x 4). The module also offers a standby power
mode of 4.4W (max.) and a full standby mode of 1.7W (max.).
The IDT7MB624 is offered in a high-density 40-pin, 900 mil center plastic DIP to take full advantage of the compact IDT7187s in
plastic surface mount packages.
All inputs and outputs of the IDT7MB624 are TTL-compatible
and operate from a single 5V supply. (NOTE: Both GND pins need
to be grounded for proper operation.) Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access times for ease of use.

• Customer-configured to 64K x 16, 128K x 8 or 256K x 4
• Fast access times
- 25ns (max.)
• Low power consumption
- Active: 4.8W (typ.) (in 64K x 16 organization)
- Standby: 1.6mW (typ.)
• Utilizes 16 IDT7187 high-performance 64K x 1 CMOS static
RAMs produced with lOT's advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Offered in 40-pin, 900 mil center plastiC DIP, achieving very high
memory density
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate

FUNCTIONAL BLOCK DIAGRAM

ADDRESS

16/

A

/

wr=

'-'

OE"

r-

CS

r
'-'

,.....
'-'

WE

RAM

LB

r'-'

LB

UB

r-

UB

'-'

64K x 16

OE
CS

1/0

DATA

CEMOS is a trademark of Integrated Device Technology, Inc.

DECEMBER 1987

COMMERCIAL TEMPERATURE RANGE
©

OSC-7oo1/-

1987 Integrated Device Technology, Inc.

13-1

IDT7MB624S 1 MEGABIT CMOS STATIC RAM PLASTIC MODULE

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION

PIN NAMES
Ao - A15
Do - 0 15
~

WE
Vee
GND

DIP
TOP VIEW
NOTES:

1. Both GND pins need to be grounded for
proper operation.

PACKAGE DIMENSIONS
(M1S) 40-PIN PLASTIC DIP

~

I-

-I

[~;i;l~i;il~i;;l~i;;l [~ ~i
~h

0.035
0.060

~~~;

-lh -.Jh·
0.100
TYP.

g.g~~

0.013'
0.022

0.12'
0.175
.

13-2

Addresses
Data Inpu1/0utput
Chip Select
Write Enable
Power
Ground

FEATURES:

DESCRIPTION:

• High-density 256K (256K x 1) CMOS static RAM module
• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• Available in low profile 28-pin ceramic SIP (single in-line
package) for maximum space saving
• Fast access times: 25ns (max.) over commercial temperature
• Low power consumption
- Dynamic: less than 600mW (typ.)
- Full standby: less than 30mW (typ.)
• Utilizes IDT7187s high-performance 64K static RAMs produced with advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organiC die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly ITL-compatible

The IDT7MC156 is a 256K (256K x 1-bit) high-speed static RAM
module constructed on a co-fired ceramic substrate using four
IDT7187 64K x 1 static RAMs in surface mount packages.
The 7MC family of ceramic SIPs offers the optimum in packing
density and profile height. The IDT7MC156is offered in a 28-pin
ceramic SIP (single in-line package). At only 350 mils high, this low
profile package is ideal for systems with minimal board spacing.
Surface mount SIP technology also yields very high packing density, allowing greater than three IDT7MC156 modules to be
stacked per inch of board space.
The IDT7MC156 is available with maximum access times as fast
as 25ns and maximum power consumption of 1.8 watts. The module also offers a full standby mode of 440mW (max.).
All inputs and outputs of the IDT7MC156 are ITL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access times for ease of use.

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

Vee
A4
AI
A5
A13

c')

~o

cro
A2
A12
A8
Al0

~1

eEl
Ao
A7
A9
A6
CE"2
~2

DATA OUT
DATA IN
A3
A11

64Kx 1
RAM
10
11
12
13
14
15
16

J:l

Jl'

64Kx 1
RAM

64Kx 1
RAM

64Kx 1
RAM
,

ADDRESS _1",,6'&--/-1
/

,

,

M16(1)

17

18
19
DATA OUT

20

21
22

~3

23
24
25

GND
A14
A15

27
28

C'E3

(

PIN NAMES

26

Ao-AI5

SIP
SIDE VIEW
NOTE:
1. For module dimensions, please refer to module drawing M16 in the packaging section.
CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

Address Unes

DIN

Data Input

DoUT

Data Output

CSO- 3

Chip Enable

~o-3

Write Enable

Vce

Power

GND

Ground

DECEMBER 1987

© 1987 Integrated DevIce Technology, Inc.

DSC-7002/- .

13-3

IDT7MC156 256K (256K x 1-BIT)
CMOS STATIC RAM SIP MODULE

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage with Respect
toGND
Operating Temperature

TA
TSIAS
TSTa

Temperature Under Bias
Storage Temperature

_ COMMERCIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING CONDITIONS

(1)

VALUE

UNIT

MIN.

TYP.

MAX.

UNIT

-0.5 to +7.0

V

Vcc

Supply Voltage

4.5

5.0

5.5

V

°C

GND

Supply Voltage

0

0

0

V

°C

VIH
VIL

Input High Voltage

-

6.0

V

-

0.8

V

Oto +70
-55 to +125
-55 to +125

°C

50

mA

DC Output Current

SYMBOL

PARAMETER

Input Low Voltage

2.2
-0.5(1)

NOTE:
1. VIL = -3.0V for pulse width less than 20ns.

lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress ratIng only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is notimplied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE

Vcc
5.0V ± 10%

DC ELECTRICAL CHARACTERISTICS
\be = 5.0V ±10%, Vcc (Min.) = 4.5V, Vcc (Max.) = 5.5V. VLe = 0.2V. VHe = Vee SYMBOL
Ilu l

Input Leakage Current

IILOI

Output Leakage Current

ICCl

Operating Power Supply
Current

ICC2

Dynamic Operating Current

Iss

Standby Power Supply
Current

IS81
VOL
VOH

0.2V

TEST CONDITIONS

PARAMETER

MIN.

= Max.; VIN = GNDtoVcc
= Max.• "C'S = "'IH. 'loUT = GND to Vce
"C'S = \k. Vee = Max.•
Output Open. f = 0
"C'S = \'tL. Vcc = Max.•
Output Open. f = fMAX
Vcc

IDT7MC156
(1)
(2)
TYP.
MAX.
15
15

Vcc

110

= Max.• Output Open

Full Standby Power Supply
Current
Output Low Voltage

CS ~ VHC. "'IN ~ \i-ie or VLC
Ves = Max.• Output Open

Output High Voltage

10H

10L

= 8mA. Vee = Min.
= -4mA, Vcc = Min.

NOTES:
1. Vcc = 5V. TA = +25°C
2. tAA = 35. 45. 45. 55ns
3. tAA = 25. 30ns

13-4

120

245

90

180

UNIT

)5

~A

}1;5.;::;

~A

36((

mA

::::::~:~:;:;:;:

"C'S ~ \iH or (TTL Level)
Vcc

225

MAX. (3)

-:330:

mA

:~~:

mA

:::::';":':'::::

6

2.4

60

f:AA:-

mA

0.4

::::::9\4

V

::;:;:;:::2:

V

IDT7MC156 256K (256K x 1-BI1)
CMOS STATIC RAM SIP MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V

5V
GND t03.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATAoUT

~

2550

48OQ

,

DATA OUT

~48OQ.

2550

30pF

5pF*

Figure 2. Output Load

Figure 1. Output Load

(for t cLZ1 •2• toLZ' tCHZ1.2. t oHZ '
tOW.tWHZ)

*Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
(Vcc

= 5V ±10%. TA = O°C to + 70°C)
PARAMETER

SYMBOL

IDT7MC156S25 IDT7MC156S30 IDT7MC156S35 IDT7MC156S45 IDT7MC156S55
MAX.
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.

UNIT

READ CYCLE

30

-

35

-

45

-

55

-

ns

30

-

35

ns

-

35

45

-

55

30

-

45

::.:.:;:::::?5

-

55

ns

Chip Select to Output in Low Z

5 ::;:::::::::::::~:::-

5

-

5

-

5

-

5

-

ns

t RC

Read Cycle Time

25

tAA
t ACS

Address Access Time

-

}~:H:..
':::'::25"

Chip Select Access Time

-

t CLZ1 . 2 (1)
tCHZ (1)

Chip Select to Output in High Z

- . :::::}it:::

20

-

25

-

25

-

30

-

30

ns

tOH
t pU (I)

Output Hold from Address Change

Q:::::;;.::.:j:

5

-

5

-

5

-

ns

0

-

5

Chip Select to Power Up Time

-

0

-

0

-

0

-

ns

t pO (I)

Chip Deselect to Power Down Time

25

-

30

-

35

-

45

-

55

ns

.:if:}}
.'.

'::;:;~.::.,

NOTE:
1. This parameter guaranteed but not tested.

AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%. TA = O°C to + 70°C)
SYMBOL

PARAMETER

IDT7MC156S25 IDT7MC156S30 IDT7MC156S35 IDT7MC156S45 IDT7MC156S55
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.

UNIT

WRITE CYCLE
twc

Write Cycle Time

25

.:;):i:;:::

30

35

45

55

ns

tcw

Chip Selection to End of Write

25

.t;::1:

25

30

40

50

ns

·:::;::::::f·:...,

25

30

40

50

ns

5

5

5

5

ns

20

25

35

45

ns

0

0

0

0

ns

tAW

Address Valid to End of Write

25

t AS

Address Set-up Time

5

twp

Write Pulse Width

20.::;::~:::::::::::·

tWR

Write Recovery Time

tWHZ(I)

Write Enable to Output in High Z

tow

Data to Write Time Overlap

tOH

Data Hold from Write Time

tow (1)

Output Active from End of Write

::~;~~{::::?

-

o.::~:i);:~:::: ;:·;::::t: 20
:i~:.:;r
:@~~t:::
'::::/b::

30

25

25

30

ns

20

20

25

25

ns

5

5

5

5

ns

0

0

0

0

ns

NOTE:
1. This parameter guaranteed but not tested.

13-5

lUI

IDT7MC156 256K (256K xl-BIT)
CMOS STATIC RAM SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

~-----------------------------------------tRc-----------------~
ADDRESS

~---------

tAA

-------------------------~

1...1-------- t ACS ----------------+-----~
,...1_------- tCLZ (5) _ _ _ _ _-+1

TIMING WAVEFORM OF READ CYCLE NO.

ADDRESS

DATAoUT

2(1,2,4)

={= = = =t-OH=_tA =~=-=-.-t~ -_=-=;- .1~~:t-tOH-DATA VALID

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

3(1,3,4)

DATA OUT

NOTES:
1. WE" is High for Read Cycle.
2. Device is continuously selected, CS = V1L•
3. Address valid prior to or coincident with CS transition low.
4. OE" = V1L
5. Transition is measured ±2oomV from steady state. This parameter is sampled and not 100% tested.

13-6

IDT7MC156 256K (256K x 1-81T)
CMOS STATIC RAM SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS

~

-..J

~

<

)(
)'

,

tAW

./~

- tAS

.....

t

,
-t

tOHZ

(7)

tWA

WP

I+-

..,"

f4-

(6)-

(6)

-tOW-l

(4)

DATA OUT

tO HZ ( 6 ) _

WHZ

(4)

tow_

----------~E---->~r-----tOH

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 2, 3, 5)

twc
ADDRESS

~

--.-/

)K

K
tAw

I - - - tAS

/'

"

tWA

tcw

tow
'/

I'

tOH

"

/1

NOTES:
1. WE" or CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS and a low WE".
3. tWA is measured from the earlier of CS or WE" going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE" low transition, the outputs remain in a high impedance state.
6. Transition is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a WE" controlled write cycle, write pulse (twp) > tWHZ + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If
~ is high during a WE" controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wP .

13-7

IDT7MC156 256K (256Kx 1-BIT)
CMOS STATIC RAM SIP MODULE

TRUTH TABLE
MODE
CS

COMMERCIAL TEMPERATURE RANGE

CAPACITANCE
OE

WE

OUTPUT

POWER

Standby

H

X

X

High Z

Standby

Read

L

L

H

DOUT

Active

Read

L

H

H

High Z

Active

Write

L

X

L

DIN

Active

SYMBOL
C IN

(TA= +25°C, f = 1.0MHz)

TEST

CONDITIONS

Input Capacitance

VIN = OV

COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.

ORDERING INFORMATION
IDT

xxxx
Device Type

999

A

A

Speed

Package

Process!
Temperature
Range

I

I Blank
CS

13-8

Commercial (DOC to

+ 70°C)

Ceramic SIP

25
30
35
45
55

} Spaod In Nanooecond'

S

Standard Power

7MC156

256Kx 1-Bit

TYP.

UNIT

35

pF

40

pF

FEATURES:

DESCRIPTION:

• High-density 1 megabit (1024K x 1) CMOS static RAM
module

The ID17MC4001 is a 1 megabit (1024K x 1-bit) high-speed
static RAM module with separate I/O. The module is constructed
on a co-fired ceramic substrate using four ID171257 256K x 1 static
RAMs in surface mount packages.
The 7MC family of ceramic SIPs offers the optimum in packing
density and profile height. The ID17MC4001 is offered in a 30-pin
ceramic SIP (single in-line package). At only 420 milS high, this low
profile package is ideal for systems with minimal board spacing.
Surface mount SIP technology also yields very high packing density, allowing five ID17MC4001 modules to be stacked per inch of
board space.
The ID17MC4001 is available with maximum access times as
fast as 35ns, with maximum power consumption of 1.35 watts. The
module also offers a full standby mode of 330mW (max.).
All inputs and outputs of the ID17MC4001 are TTL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access times for ease of use.

• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• Available in low profile 30-pin ceramic SIP (single in-line
package) for maximum space saving
• Fast access times: 35ns (max.)
• Separate I/O lines
• Low power consumption
- Dynamic: 1.35W (max.)
- Full standby: 330mW (max.)
• Single 5V(±10%) power supply
• Inputs and outputs directly TTL-compatible

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION
Vee
A4
Al
A5
A13
WEo
CEo
A2
A12
A8
AlO
WE l
CEl
Ao
A7
A9
A6
CE2
WE2
DATAoUT
DATA IN
A3
A11
CEl
WE3
GND
A14
A15
A16
A17

()

()

256Kx 1
RAM
10
11
12
13
14
15
16
17
18
19

()

()

256Kx 1
RAM

()

()

256Kx 1
RAM

0

()

256Kx 1
RAM

18/
/

ADDRESS

I

20

DATA
IN

21
22

23
24
25

I

DATA
OUT

PIN NAMES
A 0-17

Address

27
28

DATA IN

Data Input

DATA OUT

Data Output

29

CS0-3

Chip Select

WE'0-3

Write Enable

26

30

SIP
SIDE VIEW

Vee

Power

GND

Ground

CEMOS is a trademark of Integrated Device Technology, Inc.

DECEMBER 1987

COMMERCIAL TEMPERATURE RANGE
© 1987 Integrated DevIce Technology. Inc.

DSC-7003/-

13-9

IDT1MC40011 MEGABIT (1024Kx 1-BIT)
CMOS STATIC RAM SIP MODULE·

COMMERCIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS(l)
SYMBOL
VTERM
TA

RATING
Terminal Voltage with Respect
toGND
Operating Temperature

TB1AS

Temperature Under Bias

TSTG

Storage Temperature

lOUT

DC Output Current

VALUE
-0.5 to +7.0

V

Oto +70

°C

-55 to +125

°C

-55 to +125

°C

50

mA

MIN.

TYP.

MAX.

UNITS

Vee

Supply Voltage

PARAMETER

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H

Input High Voltage

2.2

6.0

V

V1L

Input Low Voltage

-0.5(1)

-

0.8

V

SYMBOL

UNIT

NOTE:
1. V1L = -3.0V for pulse width less than 20ns.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE

Vee
5.0V ±10%

.DC ELECTRICAL CHARACTERISTICS
\bc

= 5.0V ±10%. Vcc (Min.) = 4.5V. Vcc (Max.) = 5.5V. VLC = 0.2V. VHc = Vcc -

SYMBOL

PARAMETER

lIu l

Input Leakage Current

IILol

Output Leakage Current

leel

Operating Power Supply
Current

TEST CONDITIONS

= Max.: VIN = GNDtoVcc
Vcc = Max., cg = \'IH, VOUT = GND to \(;c
cg = \'IL, Vcc = Max.,
Output Open, f = 0
cg = \'IL. Vee = Max.,
Output Open, f = fMAX

Dynamic Operating Current

ISB

Standby Power Supply
Current

cg ~ \IH

ISBl

Full Standby Power Supply
Current

CS ~VHC' \'IN ~ VHC or :5 V LC
Vcs = Max., Output Open

Output Low Voltage

10L

Output High Voltage

IDT7MC4001
MIN.

Vcc

lee2

VOL
VOH

0.2V

Vcc

MAX.

UNIT

1.9.

J.lA

:60.}:

mA

or (TTL Level)

= Max., Output Open

= 8mA, Vcc = Min.
10H = -4mA. Vee = Min.

13-10

2.4

IDT7MC4001 1 MEGABIT (1024K x 1-BI1)
CMOS STATIC RAM SIP MODULE

COMMERCIAL TEMPERATURE RANGE

q
5V

AC TEST CONDITIONS
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

4800

DATAoUT

2550

q
5V

DATAoUT

2550

30pF*

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for tCU1, 2. tou. t CHZ1, 2. tOHZ'
tow and tWHV

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
Ncc = 5V ±10%, TA = O°C to + 70°C)
SYMBOL

PARAMETER

IDT7MC4001 S35
MIN.
MAX.

IDT7MC4001 S45
MIN.
MAX.

IDT7MC4001 S55
MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

35

-

45

-

55

-

ns

tAA

Address Access Time

-

35

45

ns

Chip Select Access Time

-

35

45

-

55

t Acs

-

55

ns

t CU1 . 2 (1)

Chip Select to Output in Low Z

10

-

10

-

10

-

ns

tCHZ (1)

Chip Select to Output in High Z

-

25

-

35

-

45

ns

tOH
t pU (l)

Output Hold from Address Change

5

5

-

ns

0

0

-

5

Chip Select to Power Up Time

-

0

-

ns

t pO (l)

Chip Deselect to Power Down Time

-

35

-

45

-

55

ns

NOTE:
1. This parameter guaranteed but not tested.

AC ELECTRICAL CHARACTERISTICS
Ncc = 5V ±10%, TA = O°Cto +70°C)
SYMBOL

PARAMETER

IDT7MC4001 S35
MIN.
MAX.

I DT7MC4001 S45
MIN.
MAX.

IDT7MC4001 S55
MIN.
MAX.

UNIT

WRITE CYCLE
twc

Write Cycle Time

35

-

45

-

55

tcw

Chip Selection to End of Write

30

-

40

-

50

tAW

Address Valid to End of Write

30

-

50

Address Set-up Time

5

5

Write Pulse Width

25

35

-

5

twp

45

tWR
t WHZ (l)

Write Recovery Time

5

-

40

t AS

5

-

5

-

Write Enable to Output in High Z

-

25

-

30

-

40

tow

Data Valid to End of Write

20

-

25

35

-

ns

tOH

Data Hold from Write Time

5

-

5

-

5

-

ns

tow (1)

Output Active from End of Write

5

-

5

-

5

-

ns

NOTE:
1. This parameter guaranteed but not tested.

13-11

ns
ns
ns
ns
ns
ns
ns

IDT7MC40011 MEGABIT (1024Kx 1-BIT)
CMOS STATIC RAM SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

t RC

ADDRESS

~--~.. I

tAA

~toLZ-

CS

t AcS

•

tCLZ (5)

DATAOUT

TIMING WAVEFORM OF READ CYCLE NO.

ADDRESS

2(1,2,4)

={~;=~-=~=~-t-O-H=-t-A =-~-=.-t~ - =. ..:-,~~:t-tOH-..

DATAoUT

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

DATA VALID

3(1,3,4)

DATAoUT

NOTES:
1. WE" is High for Read Cycle.
2. Device Is continuously selected, CS = V'L.
3. Address valid prior to or coincident with CS transition low.
4. ~ = V'L
5. Transition is measured ±2oomV from steady state. This parameter is sampled and not 100% tested.

13-12

IDT7MC40011 MEGABIT (1024Kx 1-BIT)
CMOS STATIC RAM SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS

~

--.J

)~

K

/"
tAW

~~

)1'

f4--

t

t AS

(7)

tWR

WP

""~

r-

~,

_t

r--- t WHZ( 6 ) -

tOHZ

(6)

(6)_

r-- tOW--J

. (4)

DATA OUT

OHZ

(4)

tow_

tOH

----------~E---->~~---------TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)

twc
ADDRESS

~

)K

...--.J (
tAW

+ - - tAS

"

/V
tWR

tcw

,
I'

tow

~

tOH

"

./1

NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS and a low Wt:..
3. tWR is measured from the earlier of CS or Wt:. going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the Wt:.low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a Wt:. controlled write cycle, write pulse (twp) > tWHZ + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If
C5E: is high during a
controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wP .

wr:.

13-13

IDT7MC4001 1 MEGABIT (1024K x 1-BIT)
CMOS STATIC RAM SIP MODULE

COMMERCIAL TEMPERATURE RANGE

CAPACITANCE

TRUTH TABLE
MODE
CS

WE

OUTPUT

POWER

SYMBOL

(TA= +25°C, f = 1.0MHz)
CONDITIONS

TEST

Standby

H

X

HighZ

Standby

CIN ·

Input Capacitance

Read

L

H

DoUT

Active

COUT

Output Capacitance

Write

L

L

HighZ

Active

pF

VOUT= OV

20

pF

PACKAGE OUTLINE

SIDE
VIEW
0.420
MAX.

0.125
0.175

BACK VIEW
0.100
TYP.

0.015
0.022

0.010
MAX.

ORDERING INFORMATION

lOT

xxxx
Device Type

A

999

A

A

Power

Speed

Package

Process!
Temperature
Range

----II Blank

L...I

~--------------~CS

35
L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-I 45

Commercial (O°C to + 70°C)

Ceramic SIP

} Speed in Nanoseconds

55

~----------------------------~S
~------------------------------------~7MC4oo1

13-14

Standard Power
1024K x 1-Bit

UNIT

35

NOTE:
1. This parameter is sampled and not 100% tested.

FRONT VIEW

TYP.

VIN = OV

FEATURES:

DESCRIPTION:

• High-density 32 bit word 512K (16K x 32) static RAM module
• Available in low profile 88-pin sidebraze dual ceramic SIP
(single in-line package)

The IDT7MC4032 is a 32-bit wide 512K (16K x 32) static RAM
module with separate I/O constructed on a co-fired ceramic substrate using eight IDT71982 16K x 4 static RAMs in leadless chip
carriers. Extremely fast speeds can be achieved due to the use of
64K static RAMs fabricated in IDT's high-performance, high-reliability CEMOS ™ technology. The IDT7MC4032 is available with
access time as fast as 30ns, with minimal power consumption.
The 7MC family of ceramic SIPs offers the optimum is packing
density and profile height. The IDT7MC4032 is packaged in a
88-pin dual ceramic SIP. The dual row configuration allows 88 pins
to be placed on a package less than 4.5 inches long and .27 inches
wide. At only 520 mils high, this profile package is ideal for systems
with minimum board spacing. Extremely high packing density can
also be achieved allowing four IDT7MC4032 modules to be
stacked per inch of board space.
All inputs and outputs of the IDT7MC4032 are TIL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of use.

• Separate I/O
• Fast access time: 30ns (max.)
• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• High impedance outputs during write mode
• CEMOS ™ process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled in IDT's high reliability vapor phase solder reflow
process
• Single 5V (±10%) power supply
• Inputs/outputs directly TIL-compatible
• Multiple GND pins for maximum noise immunity

FUNCTIONAL BLOCK DIAGRAM

ADDRESS

INPUT

14/

WE
DE"
CSI-2

,....
'-'
,....
'-'
,....

16K x 32 RAM

'-'

OUTPUT

,. 32

DATA OUT

CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
©

DECEMBER 1987

1987 Inlegrated Device Technology, Inc.

DSC-7oo4/-

13-15

IDT7MC4032 512K (16K x 32) CMOS STATIC RAM
DUAL CERAMIC SIP MODULE WITH SEPARATE 1/0

COMMERCIAL TEMPERATURE RANGE

PIN OUT

PIN NAMES
GNO
01 0
011
01 2
01 3
01 4
01 5
Ole
01 7
Ao
A2
A4
016
019
Oho
0111
Oh2
Oh3
01 14
01 15

we.
\be

DE
Ohe
01 17
01 16
01 19
0120
0121
0122

O~~

A6
Ala
A12
0124
0125
0126
0127
0126
0129
0130
Ohl
GNO

I

88
87
86
85
84
83
82
81
80
79
78

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50
49
48
47
46
45

Vee
000
001
002
003
004
005
OOe
O~

Al
A3
As
006
009
0010
00 11
00 12
001 3
0014
0015
CSL
GNO
CSu
0016
0017
00 16
0019
0020
0021
0022
0023
A7
A9
All
A13
0024
0025
0026
0027
0026
0029
0030
0031
Vee

A O- 13

Addresses

01 0- 31

Oata Input

000- 31

Oata Output

M

Write Enable

OE

Output Enable

CS L

Chip Select (Lower)

CSu

Chip Select (Upper)

Vee

Power

GNO

Ground

PACKAGE OUTLINE
I_

_I

4.450
M~

0.520
M~

0.270

-.I

MAX·i

L.
I

~

TO.360
MAX

-.L

0.100
TYP.
MAX.

0.055

TYP.

0.025

PIN NO.1

13-16

0.010
0.040

0.125
0.175

0.007
0.013

.

- - - - - - - - - - - - - - - - - - - - - - - - _ . - - _........_._........ _._-----

FEATURES:

DESCRIPTION

• High-density 256K (256K x 1) CMOS static RAM module

The IDT7MP156 is a 256K (256K x 1-bit) high-speed static RAM
module constructed on an epoxy laminate surface using four
IDT7187 64K x 1 static RAMs in surface mount packages. Extremely fast speeds can be achieved with this technique due to use
of 64K static RAMs fabricated in lOT's high-performance, high-reli.
ability CEMOS technology.
The 7MP family of surface mounted SIP technology is a costeffective solution allowing for very high packing density. The
IDT7MP156 is offered in a 28-pin SIP (single in-line package). The
IDT7MP156 can be mounted on 200 mil centers, yielding 1.25
megabits of memory in less than 3 square inches of board space.
The IDT7MP156 is available with maximum access times as fast
as 25ns with maximum power consumption of 1.8 watts. The module also offers a full standby mode of 440mW (max.).
All inputs and outputs of the IDT7MP156 are TTL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of use.

• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
• Available in 28-pin SIP (single in-line package) for maximum
space saving
• Fast access times: 25ns (max.) over commercial temperature
• Low power consumption
- Dynamic: less than 600mW (typ.)
- Full standby: less than 30mW (typ.)
• Utilizes IDT7187 high-performance 64K static RAMs produced with advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organiC die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

Vee
A4
Al
A5
A13
WE"0

(')

C'EU
A2
A12
A8
AlO

WE;
CE"1
Ao
A7
Ag
A6
~
WE"2
DATA OUT
DATA IN
A3
All
CE"3
WE"3
A14
A15
GND

(~

64Kx 1
RAM
9
10
11
12
13
14
15
16

ADDRESS

(~

0

64Kx 1
RAM

0

()

0

64Kx 1
RAM

1

64Kx 1
RAM

16/
/

M11(1)

17

18
19

I

20

DATA
IN

21

I

DATA
OUT

22

23
24
25

PIN NAMES

26

Ao-A15

Address Unes

27
28

QN

Data Input

[{,UT

CE"o-3

Data Output
Chip Enable

WE"o-3

Write Enable

SIP
TOP VIEW
NOTE:
1. For module dimensions, plese refer to module drawing M11 in the packaging section.

Vee

Power

GND

Ground

CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated DevIce Technology. Inc.

f>"

13-17

OSC-7oo5l-

IDT7MP156 256K (256K x 1-BIT)
CMOS STATIC RAM·PLASTIC SIP MODULE

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

RATING
Terminal Voltage with Respect
toGND

COMMERCIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING CONDITIONS

(11
VALUE

UNIT

MIN.

TYP.

MAX.

-0.5 to +7.0

V

Vco

Supply Voltage

4.5

5.0

5.5

V

Supply Voltage

0

0

0

V

Input High Voltage

-

6.0

V

-

O.S

V

TA

Operating Temperature

Oto +70

°C

GND

TBIAS

Temperature Under Bias

-10 to +S5

°C

VIH
VIL

TSTG

Storage Temperature

-55 to +125

°C

50

mA

DC Output Current

PARAMETER

SYMBOL

2.2
-0.5(1)

Input Low Voltage

UNIT

NOTE:
1. VIL (min.) = -3.0V for pulse width less than 2Ons.

lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE

Vee
5.0V ± 10%

DC ELECTRICAL CHARACTERISTICS
\bo = 5.0V ±10%. Vee (Min.) = 4.5V. Vee (Max.) = 5.5V. VLO = 0.2V. VHO = Vee - 0.2V
SYMBOL

TEST CONDITIONS

PARAMETER

.MIN.

Ilu l

Input Leakage Current

Vee = Max.; VIN = GND to \bo

-

IILOI

Output Leakage Current

Voc = Max.• ~ = \'IH. \loUT = GNDtoVeo

-

leol

Operating Power Supply
Current

~ = \'IL. Vee = Max .•

lee2

Dynamic Operating Current

ISB

Standby Power Supply
Current

ISBl

Full Standby Power Supply
Current
Output Low Voltage

VOL
VOH
Output High Voltage
NOTES:
1. Veo = 5V. TA = +25°C
2. tAA = 35. 45. 45. 5sns
3. tAA = 25. 30ns

IDT7MP156
TYP.(11 MAX. (21

-

MAX. (31

UNIT

15

15

15

:j5

IJA

IJA

Output Open. f = 0

-

110

225

SbO

mA

~ = 'v'IL. Voo = Max.•

-

120

245·

&30

mA

-

90

1S0

;~4d

mA

Output Open. f

= fMAX

~ ~ VIH or (TTL Level)

Vee

= Max.• Output Open

CS ~ VHO. \'IN ~ "i-ie or VLO
Ves = Max.• Output Open
IOL

= SmA. Veo

= Min.

IOH = -4mA. Voo = Min.

13-18

:::::::::.:::;:;:

2.4

mA

6

60

-

0.4

\0.4

V

-

',:<.:.;.:-:

V

IDT7MP156 256K (256K xl-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

5V

DATAoVT

~

2550

5V

4800

DATAoVT

30pF

~

2550

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for t cu1 ,2. tOUt t CHZ1 ,2' t oHZ '
tow. t WHZ )

*Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%, TA = -55°C to + 125°C and O°C to 70°C)
PARAMETER

SYMBOL

IDT7MP156S25 IDT7MP156S30 IDT7MP156S35 IDT7MP156S45 I DT7M P156S55
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

25

-

30

-

35

-

45

-

55

-

ns

tAA

Address Access Time

25

-

45

ns

30

35

-

45

-

55

25

-

35

Chip Select Access Time

-

30

tACS

-

55

ns

tCLZ1.2(1)

Chip Select to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tCHZ (1)

Chip Select to Output in High Z

-

20

-

25

-

25

-

30

-

30

ns

tOH

Output Hold from Address Change

5

-

5

5

-

5

-

5

Chip Select to Power Up Time

0

-

0

0

-

0

-

0

-

ns

tpu(1)

-

t pD (I)

Chip Deselect to Power Down Time

-

25

-

30

-

35

-

45

-

55

ns

ns

ns

WRITE CYCLE
twc

Write Cycle Time

25

-

30

-

35

-

45

Chip Selection to End of Write

25

-

25

30

-

40

-

55

tcw
tAW

Address Valid to End of Write

25

-

25

30

-

40

-

50

tAS

Address Set-up Time

5

-

5

twp

Write Pulse Width

20

20

tWR
t WHZ (I)

Write Recovery Time

0

-

0

-

0

-

0

-

0

-

Write Enable to Output in High Z

-

20

-

25

-

25

-

30

-

30

ns

tDW

Data to Write Time Overlap

15

-

20

20

-

25

Data Hold from Write Time

5

-

5

5

-

5

Output Active from End of Write

0

-

0

0

-

0

-

ns

tow (1)

-

25

tDH

-

NOTE:
1. This parameter guaranteed but not tested.

13-19

5
25

5
0

50

5

-

5

35

-

45

ns
ns
ns
ns
ns

ns

ns

IDT7MP156 256K (256K xl-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

~-----------------tRC--------------~

ADDRESS

1_----------- tACS -------+---+-1
1 _ - - - - - - - tCLZ (5) _ _ _..-1

DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)

ADDRESS

=1
....

DATAoUT

t RC

.1

tOH

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

Etoo

•I

tAA

DATA VALID

3(1,3,4)

DATAoUT

NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = V1L and UB',
= V1L for 16 output active.
3. Address valid prior to or coincident with CS'transition low.
4. DE = "'IL
5. Transition is measured ±2oomV from steady state. This parameter is sampled and not 100% tested.

m

13-20

IDT7MP156 256K (256Kx 1-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
~-----------------------twc""----------------------~

~-----------------

ADDRESS

~------------------.... tAW""----------------~

.....__-+________~~~~~I-------------twf)

....----------~~__tW-R--------~---------------

WE

DATA oUT
.....__________________________________

4C~-t-ow--------_-t-OH--~

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)

twc
ADDRESS

~

----.-/

)K

K
tAW

~II'

'I\..
~tAS

tWR

tcw

tow

I--

tOH

I.,.,

I'

II

NOTES:
1. WE or 'CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low 'CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the 'CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a WE controlled write cycle, write pulse (twp) > tWHZ + tow) to allow the I/O drivers to tum off and data to be placed on the bus for the required tow. If
~ is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp .

13-21

IDT7MP156 256K (256K xl-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE

CAPACITANCE
CIN

(TA= +25°C, f == 1.0MHz)

TEST

SYMBOL

COMMERCIAL TEMPERATURE RANGE

Input Capacitance

CONDITIONS
VIN = OV

COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.

TYP.

UNIT

35

pF

40

pF

ORDERING INFORMATION
lOT

xxxx

999

A

A

Device Type

Speed

Package

Process/
Temperature
Range

I

I Blank

13-22

Commercial (O°C to

+ 70°C)

S

Plastic SIP

25
30
35
45
55

} Spoed In Nonoseoond'

S

Standard Power

7MP156

256Kx 1-Bit

FEATURES:

DESCRIPTION:

• High-density 256K (64K x 4) CMOS static RAM module
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
• Available in 28-pin SIP (single In-line package) for maximum
space saving
• Fast access times: 25ns (max.) over commercial temperature
• Low power consumption
- Dynamic: less than 1.2W (typ.)
-Full standby: less than 30 mW(typ.)
• Utilizes IDTl187 high-performance 64K static RAMs produced
with advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly lTL-compatible

The IDTlMP456 is a 256K (64K x 4-bit) high-speed static RAM
module constructed on an epoxy laminate surface using four .
IDTl187 64K x 1 static RAMs in plastic surface mount packages.
Extremely fast speeds can be achieved with this technique due to
the use of 64K static RAMs fabricated in lOT's high-performance,
high-reliability CEMOS technology.
The 7MP family of surface mounted SIP technology is a costeffective solution allowing for very high packing density. The
IDTlMP456 is offered in a 28-pin SIP. The IDT7MP456 can be
mounted on 200 mil centers, yielding 1.25 megabits of memory in
less than 3 square inches of board space.
The IDT7MP456 is available with maximum access times as fast
as 25ns, with maximum power consumption of 3.3 watts. The module also offers a full standby mode of 440mW(max.).
All inputs and outputs of the IDTMP456 are lTL-compatible and
operate from a single 5V supply. Fully asynchronous circuitry is
used, requiring no clocks or refreshing for operation and providing
equal access and cycle times for ease of use.

PIN CONFIGURATION
Vcc
A4
A1
A7
DATAoUTO
DATAINO
A5
A2
A12
A8
A10
DATAOUT1
DATAIN1

Ao
A13
Ag

As
DATAOUT2
DATAIN2

FUNCTIONAL BLOCK DIAGRAM
DATA INPUT

14
ADDRESS _ _--.;.;1B'T/'---I
,

-----{c
64Kx4 CMOS

-----{C
10
11
12
13
14
15
16
17
18
19

WE
CE"

20

A3
A11
DATAOUT3
DATA IN3
GND
A14
A15

22

STATIC RAM

M11(1)
DATA OUTPUT

21
23
24
25

PIN NAMES
A o-A15

26

27
28
SIP
SIDE VIEW

NOTE:
1. For module dimensions, please refer to module drawing M11 in the packaging section.

Address Inputs

CE

Chip Enable

WE

Write Enable

~No - DIN3
DoUTo - DOUT3

Data Input
Data Output

Vee
GND

Power
Ground

CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated Device Technology. Inc.

DSC-7007/-

13-23

IDT7MP456 256K(64K x 4-BI1)
CMOS STATIC RAM PLASTIC SIP MODULE

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

COMMERCIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING CONDITIONS

(1)

RATING

VALUE

UNIT

Terminal Voltage with Respect
toGND

-0.5 to +7.0

V

TA

Operating Temperature

Oto +70

°C

TelAS

Temperature Under Bias

-10 to +S5

°C

TSTG
lOUT

Storage Temperature

-55 to +125

DC Output Current

50

MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

\'IH

Input High Voltage

2.2

6.0

V

\'IL

Input Low Voltage

-0.5(1)

-

O.S

V

SYMBOL

°C _

PARAMETER

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 2Ons.

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. this Is a stress ratIng only and functional operation of the device at these or any other
conditions above those Indicated In the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE

Vee
5.0V ± 10%

DC ELECTRICAL CHARACTERISTICS
SYMBOL

Vce= 5.0V ±10%, Vee (Min.) = 4.5V, Vee (Max.) = 5.5V
TEST CONDITIONS

PARAMETER

-

-

15

:)15<

J-IA

-

15

01§:'

J-IA

-

1S0

360

;I~;

mA

-

240

440

.. ~.

mA

Output Leakage Current

leel

Operating Power Supply Current

Vee = Max. , Output Open
F=O

le02

Dynamlo Operating Current

Vee = Max., Output Open
f = fMAX

= Max.
if§ = V1H ,VOUT = GND to Vee

~=VIL

ISBl

Full Standby Power Supply Current

VOL

Output Low Voltage

VOH

Output High Voltage

MAX.(3 UNIT

V.

IILOI

Standby Power Supply Current

I DT7MP456
TYP,' """",> ......
5):'"
,:""":,:,:",,

tOH

Output Hold from Address Change

5

t pU (l)

Chip Select to Power Up Time

o':'.»::·.::{.

0

-

0

-

t pO (l)

Chip Deselect to Power Down Time

-

-

30

-

35

30

-

35

-

..:',',',',',',

-::::'>:"'>"·"""c.v

25

ns

5

-

5

-

5

-

5

-

-

25

-

30

-

35

-

40

ns

5

-

5

-

5

5
0

-

ns

0

-

-

45

-

55

ns

45

-

55

-

ns

50

-

ns

5

ns

ns

WRITE CYCLE
twc

Write Cycle Time

tcw

Chip Selection to End of Write

~

tAW

Address Valid to End of Write

25.,.,· .......

Address Set-up Time

twp

Write Pulse Width

tWR
t WHZ (l)

Write Recovery Time

tow

Data to Write Time Overlap

tOH

Data Hold from Write Time

51;!

tow (1)

Output Active from End of Write

d:{,·i . . ):-

Write Enable to Output in High Z

5

....
::::':::':.:.:::.:,:.-

oLr J:.=

20

.,;,(.::::)""

30

-

30

-

5

-

5

-

5

20

-

25

-

35

0

-

0

-

0

-

-

25

-

25

-

30

20

-

50

40

-

25

tAs

26·

25

20

5

-

5

0

-

0

NOTE:
1. This parameter guaranteed but not tested.

13-25

40

5
0

45
0

-

-

30

25

25

-

ns

-

ns
ns
ns
ns

5

-

ns

0

-

ns

IDT1MP456 256K(64K x 4-Bln
CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS

~

----./

)(

K

/'
~

tAw

)1'

~
~tAS

t

(7)

""'~

~"

I+-- t WHZ( 6 ) -

tOHZ

I-

tWR

Wp

-t

(6)_

(6)

-tow

(4)

DATA OUT

OHZ

(4)

tow_

----+CE-~)!--tOH

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)

twc
ADDRESS

~<

)K
tAw

'~

/1"

~tAS

tWR

tcw

,
I'

tow

tOH

"

"I

NOTES:
1.
or CS" must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS" and a low M.
3. tWR is measured from the earlier of CS" or WF:. going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS" low transition occurs simultaneously with or after the
low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a WF:. controlled write cycle, write pulse (twp) > tWHZ + tow) to allow the I/O drivers to turn off and data to be placed on the busforthe required tow. If
OE is high during a WF:. controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wP '

wr=.

wr:.

13-27

IDT7MP456 256K(64K x 4-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE

CAPACITANCE
SYMBOL

COMMERCIAL TEMPERATURE RANGE

(TA= +25°C, f = 1.0MHz)

PARAMETER(t)

C IN

Input Capacitance

C OUT

Output Capacitance

CONDITIONS

TYP.

VIN = OV

35

UNIT
pF

VOUT= OV

40

pF

NOTE:
1. This parameter is sampled and not 100% tested.

ORDERING INFORMATION
lOT

xxxxx

A

DevicoTypo

Process!
Temperature·
Range

-----il Blank

1....

......--------------~II S
~..................................................~

25
30
35
45
55

......--------.....------------.....--~II S

..................................................-------.....__i:

~

13-28

8MP456

Commercial (O°C to + 70°C)
Plastic SIP

}

Speed In Nanoseconds

Standard Power
64Kx 4-bit

FEATURES:

DESCRIPTION:

• 81,920-bit CMOS static RAM module with decoupling capacitor

The IDT7MP564 is an 80K (16,384 x 5-bit) high-speed CMOS
static RAM constructed on an epoxy laminate substrate using 5
IDT6167 (16,384 x 1-bit) CMOS static RAMs in plastic surface
mount packages. Extremely fast speeds can be achieved with this
technique due to use of the IDT6167 RAMs, fabricated in IDT's
high-performance, high-reliability technology - CEMOS. This
state-of-the-art technology, combined with innovative circuit design techniques, provides the fastest 16K static RAMs available.
The IDT7MP564 is available with access times as fast as 20ns,
with maximum power consumption of only 2.2 watts. The circuit
also offers a reduced power standby mode. When CS goes high,
the circuit automatically goes to, and remains in, a standby mode
as long as CS remains high, consuming only 963mW maximum.
Substantially lower power levels can be achieved in the I SB1 mode
(less than 138mW max.) ..
All inputs and outputs of the IDT7MP564 are TTL-compatible
and operate from a single 5V supply, thus simplifying system designs. Fully asynchronous circuitry is used, requiring no clocks or
refreshing for operation, and providing equal access and cycle
times for ease of use.

•
•
•
•

High speed: 20~s max.
Low power consumption: 1.1W typo
IDT7MP564 package options reduce overall height
Utilizes IDT6167s-high-performance 16K RAMs produced
with advanced CEMOS ™

• CEMOS process virtually eliminates alpha particle soft error
rates (with no organiC die coating)
• Single 5V (± 10%) power supply
• Inputs and outputs directly TTL-compatible

FUNCTIONAL BLOCK DIAGRAM

L-

~

-

,.
-

IDT6167
DI (16KxI) Do

-WE

U

..---

CS

,..

DI

IDT6167
(16KxI)Do

'"' WE

~

IDT6167
DI (16KxI) Do

'"' WE

,.

J

'---

- WE

-

IDT6167
DI (16KxI) Do

,..- WE

CS

IDT6167
DI (16KxI) Do

CS

cs

U
PIN NAMES
Ao -A,3

Addresses

1/0,-1/05 Data Inputs/Outputs
CS

c:(

~

N

'"

J

CS

PIN CONFIGURATION

o 8 06-=
a>

J

Chip Select

WE

Write Enable

\be

Power

GND

Ground

"'0 -c:(c:(~c:(o
N '" CD~ .... '" '" "'jCJ) '" 0 ...... ~ N'" '" '"
- c:(1Uc:(ci 0 - cicici0-

c:( c:( c:(c:(

SIP l
SIDE VIEW
CEMOS is a trademark of Integrated Device Technology, Ino.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 1987

© 1987 Integrated Device Technology. Inc.

OSO-7008/-

13-29

IDT7MP564 SOK (16K x 5) CMOS STATIC RAM
PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING CONDITIONS

TRUTH TABLE
MODE
Standby

CS

WE

OUTPUT

POWER

H

X

High Z

Standby

(TA = O°C to -+- 70°C)
MIN •

. TYP.

Supply Voltage

4.5

5.0

5.5

V

0

0

0

V

-

6.0

V

O.B

V

PARAMETER

SYMBOL

Read

L

H

DOUT

Active

Vee

Write

L

L

HighZ

Active

GND

Supply Voltage

VIH

Input High Voltage

2.2

VIL

Input Low Voltage

-0.5(1)

MAX.

UNITS

NOTE:
1. VIL (min.) = -1.0V for pulse width less than 20ns.

DC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vee= 5.0V ±10%, TA = O°C to + 70°C)
TEST CONDITIONS

PARAMETER

MIN.

UNIT

MAX.

-

-

15

-

-

15

J1A

200

400

mA

200

400

mA

BO

175

mA

-

5

25

mA

10L = BmA

-

V

2.4

-

0.4

10H = -4mA

-

V

lIu l

Input Leakage Current

Vcc = 5.5V, VIN = OVto Vcc

IILol

Output Leakage Current

CS = VIH ,VOUT = OV to Vcc

Operating Power Supply Current

CS = VIL , Output Open, Vee = Max., f= 0

ICC2

Dynamic Operating Current

CS = VIL ,Output Open, Vee = Max., f = fMAX.

ISB

Standby Power Supply Current

CS ~ VIH

ISBl

Full Standby Power Supply
Current

CS ~ Vcc - 0.2V
VIN ~ Vee - 0.2V or ~ 0.2V

VOL

Output Low Voltage

VOH

Output High Voltage

ICCl

IDT7MP564
TYP.(l)

J1A

NOTES:
1.Vee = 5V, TA = +25°C

ABSOLUTE MAXIMUM RATINGS(1)

AC TEST CONDITIONS

RATING

VALUE

VTERM

Terminal Voltage with Respect
to GND

-0.5 to +7.0

V

TA

Operating Temperature

Oto +70

°C

TBIAS

Temperature Under Bias

-10to +85

°C

TSTG

Storage Temperature

-55 to +125

°C

lOUT

DC Output Current

50

mA

SYMBOL

Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

UNIT

SYMBOL

DATA OUT

CONDITIONS

~

255fl

(TA= + 25°C, f = 1.0MHz)

PARAMETER(l)

4Bon
DATA OUT
30pF*

Figure 1. Output Load
MAX.

UNIT

CIN

Input Capacitance

V IN = OV

30

pF

COUT

Output Capacitance

VOUT= OV

22

pF

+5V

+5V

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CAPACITANCE

GND t03.0V
5ns
1.5V
1.5V
See Figures 1 & 2

~

255fl

13-30

5pF*

Figure 2. Output Load
(for t HZ ' t LZ •twz. and tow )

*Including scope and jig

NOTE:
1. This parameter is sampled and not 100% tested.

4Bon

IDT7MP564 SOK (16Kx 5) CMOS STATIC RAM
PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc= 5.0V±10%, TA = O°Cto +70°C)
IDT7MP564L20
MIN.
MAX.

PARAMETER

IDT7MP564L25
MIN.
MAX.

IDT7MP564L35
MAX.
MIN.

IDT7MP564L45
MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

20

-

25

-

35

-

45

-

tAA
t ACS

Address Access Time

-

20

25

ns

20

-

45

-

-

35

Chip Select Access Time

-

45

ns

tOH

Output Hold from Address Change

3

-

5

-

5

5

5

-

ns

3

-

5

Chip Select to Output in Low Z

-

5

tLZ
tHz

Chip Deselect to Output in High Z

-

10

-

10

-

15

-

20

ns

tpu

Chip Select to Power Up Time

0

-

0

-

0

-

0

-

ns

tpo

Chip Deselect to Power Down Time

-

20

-

25

-

35

-

45

ns

35

45

-

ns

40

-

ns

40

-

ns

5

-

ns

ns

25

-

ns

3

-

ns

25

35

ns

ns

WRITE CYCLE
twc

Write Cycle Time

20

Chip Select to End of Write

15

-

25

tcw
tAW

Address Valid to End of Write

15

-

20

t AS

Address Set-up Time

2

3

twp

Write Pulse Width

13

17

-

25

tWR

Write Recovery Time

0

-

-

0

0

tow

Data Valid to End of Write

13

20

Data Hold Time

2

-

15

tOH

3

-

3

-

twz

Write Enable to Output in High Z

-

7

-

10

-

15

-

20

ns

tow

Output Active from End of Write

0

-

0

-

0

-

0

-

ns

_tl4---_

TIMING WAVEFORM OF READ CYCLE NO.

ADDRESS

20

30
30
5

35
3

1(1,2)

-_tR_C(51~_*=

" " ' - - - - - - - tAA ------1.-.1'
~--- toH----t
PREVIOUS DATA VALID

DATA OUT

DATA VALID

TIMING WAVEFORM OF READ CYCLE NO. 2<,,3)

14---------- t Rc

(5,1---------..1

tHZ (4. 6)

1.--1

DATA OUT

DATA VALID
HIGH IMPEDANCE

:~_~ -_-_~_-~_tP_u________________________________~
___t_po_~

___ __
VccSUPPLY
CURRENT

NOTES:
1. WE is high for read cycle.
2. CS is low for read cycle.
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ±SOOmV from steady state voltage with specified loading in Figure 2. This parameter is sampled, not 100% tested.
5. All READ cycle timings are referenced from the last valid address to the first transitioning address.
6. For any given speed, operating voltage and temperature, tHzwill be less than or equal to tLZ.

13-31

ns

IDT7MP564 BOK (16K x 5) CMOS STATIC RAM
PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1)

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1)
...- - - - - t wC ( 3 ) - - - - - - . I
ADDRESS
~----r--""\

DATA IN

DATAo~

______________________11

HIGH IMPEDANCE
NOTES:
1. CS or WE must be high during address transitions.
2. IF CS goes high simultaneously with WE high. the output remains in a high impedance state.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured ± 200mV from steady state voltage with specified loading in Figure 2. This parameter is sampled and not 100% tested.
LOW Vee DATA RETENTION CHARACTERISTICS (TA = O°Cto +70°C)
SYMBOL
VDR
ICCDR

PARAMETER

Data Retention Current

tCDR

Chip Deselect to Data Retention Time

tR

Operation Recovery Time

NOTES:
1. TA = +25°C
2. @Vee = 2V

TEST CONDITIONS

Vee for Data Retention
CS ~ Vec -0.2V
V IN ~ VCC -0.2V or ~ 0.2V

3. @Vee = 3V
4. t RC = Read Cycle Time

LOW Vee DATA RETENTION WAVEFORMS
DATA RETENTION MODE

13-32

MIN.

TYP.(1)

2.0

-

-

10(2)
15(3)

0
t (4)
RC

-

-

MAX.

300(2)
400(3)

-

UNIT
V
J.lA
ns
ns

IDT7MP564 SOK (16Kx 5) CMOS STATIC RAM
PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

NORMALIZED TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs. Voltage

1.6
TA

J+25°C

1.4
II)

N

~

1.2

c
~

8 1.0
0.8

1.6

l
Vee =5.5V

Vee' =4.5V

1.4

1.4

=c
~

Address Access Time vs.
Ambient Temperature

Supply Current vs.
Ambient Temperature

1.6

V

/
./

0.6

4.5

V

/

=c

'C
II)
.!::!

II)

~ 1.2

c
~

'"'"

..? 1.0
0.8

4.75

5.0

5.25

N

".........

:; 1.2

E
c

z

-; 1.0

...

",

r'.

-75

V

V

0.8

0.6

5.5

~

0.6

125

75

-75

125

Vee (Volts)

Standby Power Supply Current
vs. Voltage

1.6

I 0
TA=+25

1.4

.~

~ 1.2

o

~

1.0

til

.!I

1.6

j

Vee' =5.5V

1.4

V
/

=c

0.8

/

0.6

4.5

/
4.75

=c
CI)

.!::!

ca

V

E

1.2

0

~
til

.!I

=c lOoo
II)

-,

.!::!

ca

5.25

5.5

1.0

75

J+25°C

=c
II)

N

:; 1.1

E

c
~

~

V'

./

../

V
a

so

/

0.1
-25

Address Access Time vs.
Capacitive Load
TA

/

~

0.6
-75

,

~

"

Vee (Volts)

1.2

E 100

c

'~

0.8

5.0

Full Standby Power Supply Current
Data Retention Current vs.
Ambient Temperature

Standby Power Supply Current
vs. Ambient Temperature

100

Capacitive Load (pF)

13-33

125

-so

a

100

150

IDT7MP564 80K (16Kx 5) CMOS STATIC RAM
PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
lOT

XXXX

A

Device Type Power

999

A

Speed

Package

A

Ray

Process!
Temperature

~--------------~

BLANK

Commercial (OOC to

S

Plastic SIP

20
25

Speed in Nanoseconds

~-----------~ 35

+ 70° C)

45
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _~

L
Low Power

L..---------------------i

13-34

7MP564

16K x 5-Bit Static RAM Module

FEATURES:

DESCRIPTION:

• High-density 4 megabit (512K x 8) CMOS static RAM module
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
• Available in 36-pin SIP (single in-line package) for maximum
space saving
• Fast access times
- 45ns (max.)
• Low power consumption
- Dynamic: 2.6W (max.)
- Full standby: 1.9 (max.)
• CEMOS ™ process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible

The ID17MP400B is a 4 megabit (512K x B-bit) high-speed static
RAM module constructed on an epoxy laminate surface using sixteen ID171256 32K x 8 static RAMs in plastic surface mount packages. Extremely fast speeds can be achieved with this technique
due to the use of 256K static RAMs fabricated in IDT's highperformance, high-reliability CEMOS technology.
The 7MP family of surface mounted SIP technology is a costeffective solution allowing for very high packing density. The
ID17MP400B is offered in a 36-pin SIP. The 7MP4008 can be
stacked on 300 mil centers, yielding greater than 12 megabits of
RAM in less than 5 square inches of board space.
The ID17MP400B is available with maximum access times as
fast as 45ns with maximum power consumption of 2.6 watts. The
ID17MP400B also offers a full standby mode of 1.9W (max.).
All inputs and outputs of the ID17MP400B are TTL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation and providing equal access and cycle times for ease of use.

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM
NC

Vee
WE

10
11
12
13
14
15
16
17
18
M17(1)
19
20

21
22

23
24
25
26

27
28
29
30

31
32
33
34
35
36

1/02
1/°3
1/00
Al
A2
A3
A4
GND

ADDRESS

19/
/

,..,

-

~05

10
All
A5
A 13
A14
NC

512KxS
RAM

-

,..,

I/O

m

A15
AlB
A12
A18
AB
1/°1
GND
Ao
A7
A8
A9
1/°7
1/°4
1/°6
A17

.,./'s
DATA

PIN NAMES
Ao- 18

Addresses

1/00-7

Data Inputs/Outputs
Output Enable

c:>E"
WE

Vee
c:>E"

m

Vee

SIP
SIDE VIEW

GND

Write Enable
Module Select
Power
Ground

NOTE:
1. For module dimensions, please refer to module drawing M17 in the packaging section.
CEMOS is a trademark of Integrated Device Technology, Inc.

DECEMBER 1987

COMMERCIAL TEMPERATURE RANGE
© 1987 Integrated DevIce Technology, Inc.

DSC-7006/-

13-35

IDT7MP400a 4 MEGABIT (S12K x a-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE

ABSOLUTE MAXIMUM RATINGS

(1)

RATING

VALUE

UNIT

Terminal Voltage with Respect
toGND

-0.5 to +7.0

V

SYMBOL
VTERM

COMMERCIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING CONDITIONS
MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

4.5

5.0

5.5

V

Supply Voltage

0

0

0

V

SYMBOL

PARAMETER

TA

Operating Temperature

Oto +70

°C

·GND

TB1AS

Temperature Under Bias

-10 to +S5

°C

V1H

Input High Voltage

2.2

-

6.0

V

TSTG

Storage Temperature

-55 to +125

°C

V1L

Input Low Voltage

-0.5(1)

-

O.S

V

lOUT

DC Output Current

50

mA

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE

Vee
5.0V ±10%

DC ELECTRICAL CHARACTERISTICS
Vec -- 50V+10 %
SYMBOL

Vce(Min) = 45V Vee (Max) = 55V VLC = 02V VHC =Vee -02V
PARAMETER

TEST CONDITIONS

MIN.

I DT7MP4008S
MAX.

UNIT

lIu l

Input Leakage CUrrent (1)

Vee = Max.: "iN = GND to Vcc

-

80

Jl.A

IILol

Output Leakage Current

Vee = Max.
CS = "iHo VOUT = GND to Vce

-

80

J.lA

-

390

mA

="iL
Vcc = Max., Output Open
f = fMAX

-

470

mA

~ V1H or (TTL Level)·
Vcc= Max.
Output Open

-

350

mA

350

mA

0.4

V

-

V

CS

= "iL
Vee = Max., Output Op3n
f = 0

lec1

Operating Power Supply Current

lee2

Dynamic Operating Current

ISB

Standby Power Supply Current

ISB1

Full Standby Power Supply Current

CS ~ VHC,"iN

VOL

Output Low Voltage

10L = SmA, Vee = Min.

-

VOH

Output High Voltage

10H = -4mA, Vee = Min.

2.4

CS

CS

~ VHC or :5 VLe
Ves = Max., Output Open

NOTE:
1. Ilu l forA 1S -A 18 andM"S" = 400Jl.A(max.).

13-36

IDT7MP40084 MEGABIT (512K x S-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V

5V

GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATAoUT

~

255!l

48on

DATA OUT

~

255!l

30pF

Figure 1. Output Load

48on
5pF*

Figure 2. Output Load
(for t CLZ1 •2• toLZ' tCHZ1.2. t OHZ '
tOW.tWHZ)

*Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(Vee = 5V ±10%. TA

= O°C to + 70°C)

IDT7MP4008S45
MAX.
MIN.

IDT7MP4008S55
MIN.
MAX.

IDT7MP4008S70
MIN.
MAX.

UNIT

READ CYCLE
t AC

Read Cycle Time

45

-

55

-

70

-

tM

Address Access Time

45

-

70

ns

Chip Select Access Time

-

55

t Acs

-

70

ns

t CLZ1 . 2 (1)

Chip Select to Output in Low Z

5

-

5

-

5

-

ns

tOE

Output Enable to Output Valid

-

20

-

25

-

30

ns

toLZ (1)

Output Enable to Output in Low Z

0

-

0

-

0

-

ns

tCHZ (1)

Chip Select to Output in High Z

25

-

35

ns

Output Disable to Output in High Z

25

-

30

tOHZ (1)

-

25

-

30

ns

tOH

Output Hold from Address Change

5

-

5

-

5

-

ns

55

-

70

50

60

50

-

5

-

5
55

5

-

10

-

45

55

ns

WRITE CYCLE
twc

Write Cycle Time

45

tcw

Chip Selection to End of Write

40

tAW

Address Valid to End of Write

40

t AS

Address Set-up Time

5

twp

Write Pulse Width

35

tWA

Write Recovery Time

5

-

t wHZ (1)

Write Enable to Output in High Z

-

15

-

20

-

25

ns

tDW

Data Valid to End of Write

20

-

25

-

30

ns

5

-

5

5

-

5

-

tDH

Data Hold from Write Time

5

tow (1)

Output Active from End of Write

5

NOTE:
1. This parameter guaranteed but not tested.

13-37

45

60

ns
ns
ns
ns
ns
ns

ns
ns

IDT7MP40084 MEGABIT (S12K x 8-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

~-----------------tRC--------------~
ADDRESS

~---------

14----------

tAA ------------t

tAcs-----+----t

1.-------- tCLZ (5) _ _ _~
DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.

2(1,2,4)

~~~--------------tRC--------------~~
ADDRESS

DATAoUT

---Jli:~-=~- =~:~ :~-t~O-H_-~tA ~ ~-=-~ -=-.:-I-=- =- =- =- =- =- =-~·-1-----'~t-t-OH---PREVIOUS DATA VALID

DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.3 (1,3,4)

DATA OUT

NOTES:
1. VIr=. is High for Read Cycle.
2. Device is continuously selected, CS = V1L •
3. Address valid prior to or coincident with CS transition low.
4.
= V1L
5. Transition is measured ±2oomVfrom steady state. This parameter is sampled and not 100% tested.

rn=

13-38

IDT7MP40084 MEGABIT (S12K x 8-BIT)
CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,7)
twe
ADDRESS

~

---./

)(

K

/V'
tAW
~

~,

'"

~tAS

t

"",

-t

tOHZ

(7)

tWR

WP

I-

~'fI'

:---- t

(6)-

(6)_

~tOw-1

(6)

(4)

DATA OUT

OHZ

WHZ

(4)

tow _

____________~~-----~~L---------tOH

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 2, 3, 5)

twc
ADDRESS

~
~

)K

K
tAW

f4--

t AS

'" '"

/V
tWR

tew

tow

I'

I'

~

tOH

"

'1

NOTES:
1. M or CS must be high during all address transitions.
2. A write occurs during the overlap (twFl of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input Signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a WE controlled write cycle, write pulse (twPl > tWHZ + tow) to allow the I/O drivers totum off and data to be placed on the bus for the required tow. 11
DE" is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wP .

13-39

IDT7MP40084 MEGABIT (S12K x 8-Bln
CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TRUTH TABLE
PARAMETER(1)

DE

WE

OUTPUT

POWER

Standby

H

X

X

HighZ

Standby

CIN

Input Capacitance

Read

L

L

H

DATA OUT

Active

COUT

Output Capacitance

Read

L

H

H

HighZ

ACtive

Write

L

X

L

DATA IN

Active

CS

MODE

SYMBOL

CONDITIONS

TYP.

VIN = OV

96

pF

VOUT= OV

128

pF

NOTE:
1. This parameter is sampled and not 100% tested.

ORDERING INFORMATION
IDT

XXXX

A

Device Type Power

A

A

Package

Process!
Temperature
Range

yBLANK

L...---------I S

'--------------1

45
55

' - - - - - - - - - - - - - - - - - - - - - - ; 7MP4008

+ 70°C)

SIP

} Speed in Nanoseconds

70

L...-_ _ _ _ _ _ _ _ _ _ _ _ _ _- j S

13-40

Commercial (O°C to

Standard Power

(512K x 8-bit)

UNIT

FEATURES:

DESCRIPTION:

• High-density 1024K-bit CMOS static RAM module
• Customer-configured to 64K x 16, 128K x 8 or 256K x 4

The IDT7M624 is a 1024K-bit high-speed CMOS static RAM
constructed on a multi-layered ceramic substrate using 16
IDT7187 64K x 1 static RAMs in leadless chip carriers. Making four
chip select lines available (one for each group of 4 RAMs) allows
the user to configure the memory into a 64K x 16, 128K x 8 or 256K x
4 organization. In addition, extremely high speeds are achievable
by the use of IDT7187s fabricated in IDT's high-performance, highreliability technology, CEMOS. This state-of-the-art technology,
combined with innovative circuit design techniques, provides the
fastest 64K static RAMs available.
The IDT7M624 Is available with access times as fast as 25ns
commercial and 35ns military temperature range, with maximum
operating power consumption of only 12.3W (significantly less if
organized 128K x 8 or 256K x 4). The module also offers a standby
power mode of 5.7W (max.) and a full standby mode of 1.7W
(max.).
The IDT7M624 is offered in a 40-pin, 900 mil center sidebraze
DIP to take advantage of the compact IDT7187s in leadless chip
carriers.
All inputs and outputs ofthe IDT7M624 are TIL-compatible and
operate from a single 5V supply. (NOTE: Both GND pins need to be
grounded for proper operation.) Fully asynchronous circuitry is
used, requiring no clocks or refreshing for operation, and providing "equal access times for ease of use.
AIiIDT military module semiconductor components are compliant with the latest revision of MIL-STD-883, Class B, making them
ideally suited to applications demanding the highest level of
performance and reliability.

• Fast access times
- Military: 35ns (max.)
- Commercial: 25ns (max.)
• Low power consumption
- Active: 4.8W (typ. in 64K x 16 organization)
- Standby: 1.6mW (typ.)
• Utilizes 16 IDT7187 high-performance 64K x 1 CMOS static
RAMs produced with IDT's advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Offered in 40-pin, 900 mil center sidebraze DIP, achieving
very high memory density
• Pin-compatible with IDT7M656 (256K RAM module)
• Single 5V(±10%} power supply
• Dual GND pins for maximum noise immunity
• Inputs and outputs directly TIL-compatible
• Modules available with semiconductor components compliant to MIL-STD-883, Class B '
• Finished modules tested at Room, Hot and Cold temperatures for all AC and DC parameters

PIN CONFIGURATION
(llGND
0 15
CS'(12-15)
04

Vee
011

~(6-11)

Do
Ao
A 13
0 10
A12
01
All
A 10
09
A9
O2
Ae
A7
0

~

Al
014
A2
05
A3
A4
013
A5
De"
As
A14
0 12
CS'(4-7)
07
A15

FUNCTIONAL BLOCK DIAGRAM

PIN NAMES
AO-le

Address

0 0- 15

Data Input/Output

~

Chip Select

~

Write Enable

\be

Power

GND

Ground

Ao-A 1e

--~~---------.--------~--------,

~o-3-+~rlH------~++------~rr------~

~~~====~~==~~====~
-+h...+4------_++-------.H-------....,

~6-11

0"

~(O-3)
03
GND(I)

DIP
TOP VIEW
NOTES:

1. Both GND pins need to be grounded for proper operation.
2.

For module dimensions, please refer to module drawing M6 in the
packaging section.

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DECEMBER 1987
OSC-7011/-

© 1967 Integrated Device Technology, Inc,

13-41

m

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM

RATING
Terminal Voltage
with Respect to
GND

COMMERCIAL
-0.5 to +7.0

MILITARY
-0.5 to +7.0

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

UNIT

GRADE

V

Military

TA

Operating
Temperature

Oto +70

-55 to +125

°C

T81AS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

Tsm

Storage
Temperature

-55 to + 125

-65 to +155

°C

Commercial

SYMBOL

PARAMETER

GND
OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V ± 10%

Vcc

RECOMMENDED DC OPERATING CONDITIONS
MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

PARAMETER

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH
VIL

Input High Voltage

2.2

-

6.0

V

0.8

V

SYMBOL

50
DC Output Current
mA
50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATIN GS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS

AMBIENT
TEMPERATURE
-55°C to + 125°C

Input Low Voltage

-0.5(1)

NOTE:
1. VIL = -3.0V for pulse width less than 20ns.

(Vce= 50V -+10% TA = -55°C to + 125°C and O°C to + 70°C)
TEST CONDITIONS

MIN.

IDT7M624S
TYP.!l)
MAXJ3)

MAX,<4)

UNIT

Ilu l

Input Leakage Current

:go

Output Leakage Current

'te = 5.5V, CSXX = VIH , \bur = GND to\6e

-

-

20

IILOI

20

;:gQ

~A

leex16

Operating Current in X16 mode

CS xx = \lL, Output Open, Vee = 5.5V, f=f MAX

-

960

1950

~~~O

mA

leexa

Operating Current in X8 mode

720

1380

1§40

mA

Operating Current in X4 mode

-

600

1100

13.40

mA

IS8

Standby Power Supply Current

CSxx = VIL, Output Open, Min. Duty Cycle = 100%
CSxx = VIL, Output Open, Min. Duty Cycle = 100%
CSxx ~ VIH (TTL Level), Vec =5.5V, Output Open

-

leex4

-

480

820

1:\,*0

mA

IS81

Full Standby Power Supply
Current

0.32

320(2)

:3~0

mA

0.5

Output Low Voltage

0.4

JM
:Q;1

V

VOL

-

f+::

V

Vee = 5.5V, VIN = GND to Vee

CSxx ~ Vce -0.2V,

-

VIN ~ Vee -0.2V or::; 0.2V (CMOS Level)

-

10L = 10mA, \Ce = 4.5V

-

10L = 8mA, Vec = 4.5V

Output High Voltage
10L = -4mA, \be = 4.5V
VOH
NOTES:
1. Typical limits are at Vee = 5.0V, + 25°C.
2. IS81 max. at commercial temperature = 240mA.
3. tM = 30, 35, 45, 55, 65ns
4. tM = 25ns

13-42

2.4

-

~A

V

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE

AC TEST CONDITIONS

5V

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATAoUT

~
2550

5V

~

4800
DATAoUT
30pF*

2550

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for t HZ' tLZ. twz and tow)

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%, TA = -55°C to

+ 125°C and O°C to 70°C)

PARAMETER

SYMBOL

7M624S45
7M624S55
7M624S65
7M624S25
7M624S30
7M624S35
COM'LONLY COM'LONL
MAX. MIN. MAX. MIN. MAX. MIN.
MAX.
MIN.
MAX. MIN.
MAX. MIN.

UNIT

READ CYCLE
....

30

-

35

-

45

-

55

-

65

-

ns

-

"'::'::::;::25

-

30

-

35

-

45

55

ns

;.:,.::::;:::= 25

-

30

-

35

-

45

-

65

-

-

65

ns

5

5

-

5

-

5

-

5

-

5

5

-

ns

5

-

5

5

-

ns

-

25

-

30

-

30

-

30

-

30

ns

-

0

-

0

-

0

-

0

-

0

-

ns

25

-

30

-

35

-

35

-

35

-

35

ns

:;

.........

-

Read Cycle Time

25

tAA

Address Access Time

tAcs

Chip Select Access Time

tOH

Output Hold from Address Change

tLZ

Chip Selection to Output in Low Z

-

tHZ

Chip Deselection to Output in High Z

-;:;:.:.:..(

20

tpu

Chip Selection to Power Up Time

O:::;{:~::;

t po

Chip Selection to Power Down Time

-}}.;.;:

t RC

5 ':';'.'
5::::::::::;:'

-

55

AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ±10%, TA = -55°C to + 125°C and O°C to 70°C)
SYMBOL

PARAMETER

7M624S45
7M624S25
7M624S30
7M624S35
COM'L.ONL COM'LONL
MIN.
MAX. MIN.
MAX. MIN.
MAX. MIN. MAX.

7M624S55

7M624S65
UNIT

MIN.

MAX. MIN.

MAX.

WRITE CYCLE
55

-

65

50

-

55

50

-

55

5

-

10

-

35

-

0

5

-

25

0

-

5

-

45

30

25

-

30

-

40

3

-

5

5

20

25

30
0

20

-

20

-

5

-

5

-

-

O:{lii'

20

0

25

0

5 It::;:;·

-

5

-

5

twc

Write Cycle Time

25

)}::,::7

30

tcw

Chip Selection to End of Write·

22

{it>·

25

tAW

Address Valid to End of Write

22

.;:;.;.:.:;::-

t AS

Address Set-up Time

twp

Write Pulse Width

2 :2:@::::::
20 .:::::::::;:::::

tWR

Write Recovery Time

o ::::it\ -

0

tow

Data Valid to End of Write

15::::::

.;.:

-

tOH

Data Hold Time

5 {:.;:;:

:.:

twz

Write Enable to Output in High Z

tow

Output Active from End of Write

-

13-43

35

0

40

25

-

ns
ns

40

-

-

0

-

ns

25

-

30

-

ns

5

-

5

-

ns

30

0

30

0

35

ns

-

5

-

5

-

ns

ns
ns
ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE

TIMING WAVEFORM OF READ CYCLE NO.1

(1,2)
tRC(5) _ _ _~t=

ADDRESS
tAA ------i.~'

DATAoUT

DATA VALID

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

2(1,3)

~--------

t+------

tAcs

t RC (5)

---------.1

-------t

DATAoUT

DATA VALID
HIGH IMPEDANCE

Vee SUPPLY
CURRENT

~----~~~~~~~~~~~~

NOTES:

1.
2.
3.
4.
5.

wr=. Is high for READ cycle.
CSxx is low for READ cycle.
Address valid prior to or coincident with CS'xx transition low.
Transition Is measured ±2oomV from steady state voltage with specified loading In Figure 2. This parameter is sampled, not 100% tested.
All READ cycle timings are referenced from the last valid address to the first transitioning address.

13-44

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS

~

-./

<

)(
)1'

~

tAW

~I'

~
t

- tAS

(7)

tWR

Wp

.,""

~,

-t
tOHZ

-

(6)-

I--- t OHZ ( 6 ) _

WHZ

~tOW-1

(6)

(4)

DATA OUT

(4)

____________~~----~~~L---------tow_

tOH

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)

twc
ADDRESS

~K

)(
tAW

,~

i'4-- t AS

/V
tWR

tcw

,

tow

I'

r-tOH

,
'1

NOTES:

1. ~ or cg must be high during all address transitions.
2. A write occurs during the over1ap (twFl of a low cg and a low ~.

3. tWR is measured from the earlier of cg or ~ going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.

,
5. If the cg low transition occurs simultaneously with or after the ~ low transition, the outputs remain in a high impedance state.
6. Transition is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a ~ controlled write cycle, write pulse (twp) > tWHZ + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If
DE is high during a ~ controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp .

13-45

IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

TRUTH TABLE

(TA= +25°C, f = 1.0MHz)

-e"Sxx

WE

OUTPUT

POWER

Standby

H

X

HighZ

Standby

C IN

Input Capacitance

Read

L

H

DATA OUT

Active

COUT

Output Capacitance

Write

L

L

HighZ

Active

MODE

SYMBOL

TEST

CONDITIONS

TYP.

UNIT

V IN = OV

130

pF

VOUT= OV

35

pF

NOTE:

1. This parameter is sampled and not 100% tested.

IDT7M624
64K X 16 CONFIGURATION
A o -A 15 - - - Ao -A15 ---1~_----_----

__------'

~0-3

~4-7
~

~--~------~~~======~======~======~
~8-11

NOTE:
All chip selects tied together since, in a by 16 configuration, all chips are either on or off.

IDT7M624
128Kx 8 CONFIGURATION
Ao -A 1S

-----------------

~----I

Do

Dl

D2

D3

D4

Ds

D6

D7

Ao -A 15

CSO- 3

Vcc - - - ' "

CS4- 7

CSS- 11
CS12- 15

NOTE:
The chip selects are tied together in groups of two. The decoder uses the new higher order address pin (A 16 ) to determine which of the two banks of memory
are enabled.

13-46

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M624S 1 MEGABIT CMOS STATIC RAM MODULE

IDT7M624
256K X 4 CONFIGURATION
Ao -A 15 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - WF:.----'
Vee - - - ,
Vee ~8

AOB AlB OOB 01B 02B

03B

Do
NOTE:
Each ehip is now controlled by the two higher order address pins A16 and A 17 •

ORDERING INFORMATION
lOT

xxxxx

A

A

Device Type

Package

Process!
Temperature
Range

y:,"k

~--------------~C

25
30
35

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Semiconductor Components Compliant to
MIL-STD-883, Class B
Sidebraze DIP
Commercial Only
Commercial Only

} Speed;n Nona""","'"

~----------------------~45

55
65
~----------------------------~S
~--------------------------------------_i 7M624

13-47

Standard Power
1 Megabit (1024K-Bit)

FEATURES:

DESCRIPTION:

• High-density 256K-bit CMOS static RAM module
• Customer-configured to 16Kx16, 32Kx8 or 64Kx4
• Fast access times
- Military: 20ns
-Commercial: 15ns

The I0T7M656 Is a 256K-bit high-speed CMOS static RAM constructed on a multilayered ceramic substrate using 16 IOT6167
(16Kx1) static RAMs in leadless chip carriers. Making 4 chip select
lines available (one for each group of 4 RAMs) allows the user to
configure the memory into a 16Kx16, 32Kx8 or 64Kx4 organization.
In addition, extremely high speeds are achievable by the use of
IOT6167s fabricated in lOT's high-performance, high-reliability
technology, CEMOS. This state-of-the-art technology, combined
with innovative circuit design techniques, provides some of the
fastest 16K static RAMs available.
The IDT7M656 is available with access times as fast as 15ns
commerCial and 20ns military temperature range, with maximum
operating power consumption of only 7.9W (significantly less if
organized 32Kx8 or 64Kx4). The RAM module also offers a
maximum standby power mode of 3.0W and a maximum full
standby mode of 176mW.
The IDT7M656 is offered in a high-density 40-pin, 900 mil center
sidebraze DIP to take full advantage of the compact IDT6167s in
lead less chip carriers.
All inputs and outputs ofthe IDT7M656 are TTL-compatible and
operate from a single 5V supply. (NOTE: Both Vee pins need to be
connected to the 5V supply and both GND pins need to be
grounded for proper operation.) Fully asynchronous circuitry is
used requiring no clocks or refreshing for operation, and providing
equal access and cycle times for ease of use.
AIiIDT military module semiconductor components are manufactured in compliance with the latest revision of MIL-STD-883,
Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

• Low power consumption
- Active: 3.2mW (typ.) (in 16K x 16 organization)
- Standby: 0.16mW (typ.)
• Utilizes 16 IOT6167s high-performance 16K x 1 CMOS static
RAMs produced with lOT's advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with lOT's high-reliability vapor phase solder reflow
process
.
• Offered in 40-pin, 900 mil center sidebraze DIP, achieving very
high memory density
• Single 5V (±10%) power supply
• Dual Vee and GNO pins for maximum noise Immunity
• Inputs and outputs directly TTL-compatible
• Module available with semiconductor components compliant
to MIL-STO-883, Class B.

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM
Ao-A13---~~~----~----~-----'

*GNO

WE"-TOP---~~--------~--------H-------~
CSO- 3 ---++-ffil------..++----_+4--------.

°lS

CS(12-1S)
04

WE"(BOT)
A1
014
A2

Os
A3

A4

WE"-BOT·--~~~======~======~======~
CS8_11 ---f.+-ffil------..++-----t+------,

013

As
Oe
Ae

WE"(TOP)

0 12
CS(4-7)

07
*Vcc

-.-L;;.;;...._ _ _____

DIP

TOP VIEW

PIN NAMES

1. For module dimensions, please refer to module drawing M5 in the
packaging section.

A '¥X
CS'¥X
M'¥X

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

Addresses
Chip Selects
Write Enable

D'¥X
Vcc
GND

DATAIN/OUT
Power
Ground

DECEMBER 1987
DSC-7012/-

1987 Integrated Device Technology, Inc.

13-48

------.~----

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M656L 256K CMOS STATIC RAM MODULE

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL

RATING

-0.5 to +7.0

Operating
Temperature

TA

RECOMMENDED DC OPERATING CONDITIONS

COMMERCIAL

Terminal Voltage
with Respect to
GND

VTERM

o to

MILITARY

UNIT

-0.5 to +7.0

+70

SYMBOL

V

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-55 to +135

TSTG

Storage
Temperature

-55 to +125

-55 to +150

°C

50

50

mA

DC Output Current

..- - - - - .

MIN.

TYP.

MAX.

Vcc

Supply Voltage

PARAMETER

4.5

5.0

5.5

UNIT
V

GND

Supply Voltage

0

0

0

V

\'IH

Input High Voltage

2.2

-

5.0

V

\'IL

Input Low Voltage

-0.5(1)

-

0.8

V

NOTE:
1. VIL (min.) = -'-3.0V for pulse width less than 20ns.

°C

lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc= 5.0V +10%,
TA = -55°C to + 125°C and O°C to + 70°C)
-

PARAMETER

TEST CONDITIONS

Ilu l

Input Leakage Current

IILol

Output Leakage Current

MIN.

Vcc = 5.5V, VIN = OV to Vcc

IDT7M656L
TYP.(l)
MAXP)

UNIT

MAX,C4)

-

-

20

?O

~A

-

-

20

M

~A

Icex16

Operating Current in X15 mode

CS = \'IH' VOUT = OV to Vcc
CSxx = VIL , Output Open, Vee = 5.5V, f=fMAX

-

540

1280

1440

mA

leexa

Operating Current in X8 mode

CSxx = VIL , Output Open, Vee = 5.5V, f=fMAX

-

420

840

Q~b

mA

Iccx4

Operating Current in X4 Mode

CSxx = VIL • Output Open, Vee = 5.5V, f=fMAX

-

310

520

6.§P

mA

ISB

Standby Power Supply Current

CSxx

~Vec(TTL

-

200

400

ISBl

Full Standby Power Supply
Current

CSxx

~ Vee

-

0.032

VOL

Output Low Voltage

IOL =8mA

Level), Vee =5.5V, Output Open

-O.2V (CMOS Level
VIN ~ Vee -O.2V or < 0.2V

Output High Voltage
VOH
10H =-4mA
NOTES:
1.Vcc = 5V,TA=+25°C
2. ISBl max. at commercial temperature = 5.0mA
3. tAA = 25, 35, 55, 55ns
4. tAA = 15, 20ns

MODE

CS

WE

OUTPUT

POWER

Standby

H

X

High Z

Standby

Read

L

H

DATA OUT

Active

Write

L

L

High Z

Active

SYMBOL
CIN

PARAMETER(1)

CONDITIONS
\'IN = OV

:~?

rnA.

-

-

0.4

PA

V

2.4

-

-

·::ia

V

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

;.;.;.;.:.

DATAoUT
MAX.

UNIT

200

pF

GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

wlBJ

5V

(TA= +25°C, f = 1.0MHz)

Input Capacitance

mA

AC TEST CONDITIONS

TRUTH TABLE

CAPACITANCE

15(2)

s60

~
2550

COUT (2) Output Capacitance
50
pF
VOUT= OV
NOTE:
1. This parameter is determined by device characterization, but is not
100% tested.
2. For each output, 15K x 15 mode.

4800

DATAmrr

30pF*

Figure 1. Output Load

4800

Ei5

W

Figure 2. Output Load
(for t HZ' tu. twz and tow)

* Including scope and jig.

13-49

--r---f

IDT7M656L 256K CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
SYMBO

PARAMETER

tYcc = 5V ±10%, All Temperature Ranges)

IDT7M656L15 IDT7M656L20 IDT7M656L25 IDT7M656L35
(COM'L ONLy)
MAX. MIN.
MAX.
MIN.
MAX. MIN.
MAX. MIN.

IDT7M656L55
MIN.

IDT7M656L65

MAX.

MIN.

MAX.

UNIT

READ CYCLE
t Rc

Read Cycle Time

15

-

tAA

Address Access Time

-

15

20 ....
::"

25

-

35

-

55

-

65

-

ns

25

-

35

-

65

ns

20

25

-

35

-

55

- .. ....

-

t AcS

Chip Select Access Time

-

15

55

-

65

tOH

Output Hold from
Address Change

3

ns

~.ii:::::;:::·

-

5

-

5

-

5

-

5

-

-

ns

tLZ

Chip Selection to
Output in Low Z

5

-

tHz

Chip Deselect to
Output in High Z

i~::i:j::::{

-

5

-

5

-

5

-

5

-

ns

-

10

::nt::::::::::

15

-

15

-

20

-

40

-

40

ns

tpu

Chip Select to
Power Up Time

0

tpD

Chip Select to
Power Down Time

-

C

-

0

-

0

-

0

-

0

-

ns

-

:::
15 .....

1::::::2

20

-

25

-

35

-

55

-

65

ns

- /\::::~O

-

25

-

35

-

55

-

ns

-

30

45

-

65

20

55

ns

45

-

55

5

-

5

-

35

-

40
0

./:::::}i)} 20
:

WRITE CYCLE
twc

Write Cycle Time

15

tcw

Chip Select to End of Write

15

-

25

-

35

2

-

5

-

5

:::::'-

17

20

-

30

)\f::)/

0

-

0

-

0

-

0

-

-

15

-

20

-

25

5

-

5

-

5

-

30

5

5

-

-

10

-

10

-

15

-

40

-

40

ns

0

-

0

-

0

-

0

-

0

-

ns

- ':::::::':::::20

tAW

Address Valid to End of Write

15

t AS

Address Set-up Time

2

twp

Write Pulse Width

13

tWR

Write Recovery Time

0

tDW

Data Valid to End of Write

13

tDH

Data Hold Time

t ly

Write Enable to
Output in HIGH Z

/::':):2':::
- : : i; :;.i · :~:t: :

twv

Output Active from
End of Write

.:,?:::::::::::
.'.:.::

.J:'::::':::::::

5

0

':'::20

-

::::.:.:....

::::::::}{([

15

13-50

ns
ns
ns
ns
ns
ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M656L 256K CMOS STATIC RAM MODULE

TIMING WAVEFORM OF READ CYCLE NO.1

ADDRESS

DATAoUT

(1,2)

tRC(S)-----------i~~......_ _

--E

tM ------~.'

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.2

DATA VALID

(1,3)

)0+--------- tRC(S) ---------~

tLZ
DATAoUT

DATA VALID
HIGH IMPEDANCE

Vcc SUPPLY
CURRENT

~----:~~~~~~~~~~~~

NOTES:
1.
2.
3.
4.
5.
6.

~xx is High for READ cycle.

CSxx is low for READ cycle.
Address valid prior to or coincident with CSxx transition low.
Transition is measured ±500mV from steady state voltage with specified loading in Figure 2. This parameter is sampled and not 100% tested.
All READ cycle timings are referenced from the last valid address to the first transitioning address.
For any given speed grade. operating voltage. and temperature. 1Hz will be less than or equal to tLZ.

13-51

IDT7M656L256KCMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS

~

---.-/

)(

K

/'
tAW
~

~V

"

- tAS

tWR

twf)

""',

f-

"fi'

-t

-t
(6)WHZ

tOHZ

(6)_

(6)

~tow

(4)

DATA OUT

OHZ

(4)

tow_

-------+CE-~)+---tOH

TIMING WAVEt:0RM OF WRITE CYCLE NO. 2 ~ CONTROLLED TIMING)(1,2,3,5)

twc
ADDRESS

~

-.-/(

)(
tAW

~~

'I\..
_ t AS

tWR

tcw

tow
'/

I"

tOH

"

II

NOTES:
1. M or CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS and a low M.
3. tWR is measured from the earlier of CS or M going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the Wi: low transition, the outputs remain in a high impedance state.
6. Transition is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During aM controlled write cycle, write pulse (twP) > tWHZ + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If
DE" is high during a M controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp •

13-52

._._._--_._--_.__ ... _...- - - - - - - - - - - - -

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M656L 256K CMOS STATIC RAM MODULE

DATA RETENTION CHARACTERISTICS
SYMBOL
VDR
lecDR

(Vee= 50V +10%
TA = -55°C to + 125°C and O°C to + 70°C)
TEST CONDITION

PARAMETER
Vee for Retention Data
Data Retention Current

CS xx ~ Vee - 0.2V

\tiN
teDR·
tR

~

Vcc - 0.2V or ~ 0.2V

Chip Deselect to Data Retention Time
Operation Recovery Time

NOTES:
1. TA = +25°C.
2. atVcc = 2V
3. atVcc = 3V
4. t RC = Read Cycle Time.

LOW Vee DATA RETENTION WAVEFORM

DATA RETENTION MODE

Vee

13-53

MAX.
COM'L

MAX.
MIL

UNIT

-

V

MIN.

TYP.

2.0

-

-

.01(2)

2.0(2)

6.0

-

.02(3)

3.0(3)

9.0

0

-

t RC (4)

-

-

-

mA

-

ns

-

ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M656L 256K CMOS STATIC RAM MODULE

NORMALIZED TYPICAL PERFORMANCE CHARACTERISTICS

1.6

1.6

~A= +2JOC

1.4

12
.

o

z

1.0

./

0.8

V

V

V

'"

~
N
~

o

]

:!l

4.75

5.0
5.25
Vee (volts)

5.5

1.0

0.6
-75

~ 1.4

:!l

/

E
1.2
o
m

1.0

E

0

~
a:

5.25

5.5

0.6
-75

-25

25
TA (0C)

~
Q)

~ 1.1

V
~

~

./

~
o

-25

25
75
TA (0C)

125

Full Stand-by Power Supply Current
Data Retention Current vs.
Ambient Temperature

~
Q)

1
J.
TA= +25°C

E
o

/

1000

'a

Address Access Time vs.
Capacitive Load

~

0.6
-75

125

/'

I

0.8

5.0

0.8

~

Vee =5.5V

~

Vee (volts)

1.2

75

'"~~

/~
4.75

............

./

N

0.6
4.5

~ 1.0

1.4

/

/

0.8

25

1.6

V

~

-25

o

Stand-by-Power Supply Current
vs. Ambient Temperature

t=+ 2J OC/

'a

'"'"

E 1.2

~

TA (0C)

Stand-by-Power Supply
Current vs. Voltage
1.6

'a

"-

1.2

0.8

0.6

~

~1.4
"0

~

V"
4.5

.1

Vee =4.5V

1.4

:!l

]

1.6

I.

Vee =5.5V

~

1

Address Access Time vs.
Ambient Temperature

Supply Current vs.
Ambient Temperature

Supply Current vs. Voltage

50
Capacitive Load (pf)

100

13-54

0
0

.!J

~

75

J

100

,

10

,

co
..!2

1/

f

0.1
125

-50

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M656L 256K CMOS STATIC RAM MODULE

IDT7M656

16K x 16 cONFIGURATION(1,2)
Ao -A 13 - - - Ao -A 15 --'---1~----"""-----11-------,
~-TOP--~H-~--------~--------~------~

CSO- 3
CS4- 7
CS

~

~-BOT--~~~======~======~======~
CSS- 11

NOTES:

1. All chip selects tied together since, in a by-16 configuration, all chips are either on or off.
2. The two write enables are tied together allowing control of the write enable for entire memory at one time (necessary) in a by-16 organization
since all chips are either writing or reading at any given time.
Do

32K X 8 CONFIGURATION (1,2)
Ao -A 13 - - - - - - - - - - - - - - - - - - ~---..J

Dl

D2

D3

A o -A 15

~-TOP

CSo--3

Vcc - - - - - - .

CS4- 7
~

CSS- 11
CS1A AOA AlA OOA 01A 02A 03A GND

CS12- 15

cs~l-=

A14
D4
D5
De
D7
NOTES:
1. All chip selects tied together in groups of two. The decoder uses the new higher order address pin (A14) to determine which of the two banks of
memory are diSabled.
2. The two write enables are tied together for ease of layout. They could be controlled by the decoder similar to the chip selects but would save only a
minimal amount of power and add complexity to the layout.

64K X 4 CONFIGURATION (1,2)
A

A

A o -A 15
r-----------------~-~-TOP--~~-----~~-------,~--------,

0- 13

we ------'

CSO- 3

Vcc~
Vcc

CSts AOB

AlB OOB 01B 02B 03B

CS'4-7
~-BOT-~~~====~~====~~~====~~
CSS- 11

CS1A AOA AlA 00A 01A 02A 03A GND

~ ----"

I

I I

'I r

L..1_::==:--=~--=~~=~--=~--=~-·:-·~.--11

7'<'i'<"

v·'2-15

Do
NOTES:
1. Each chip select is now controlled by the two higher order address pins A 14(necessary in 64K deep memory).
2. Again the two write enables are tied together for ease of layout (the megabit part will only have one write enable pin).

13-55

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M656L 256K CMOS STATIC RAM MODULE

ORDERING INFORMATION
lOT

xxxxx
Device Type

999
Speed .

A

A

Package

Process!
Temperature

Y

RM

~

____________________

~

:

' Mk

.

C

15
20
25
35
55
65
L

~--------------------------------------~ 7M656

13-56

Commercial (O°C to + 70°C)
Military (-55°C to + 125 l 'C)
Semiconductor Components Compliant
to MIL-STO-883
Sidebraze DIP
Commercial onlY}
Speed in Nanoseconds

Low Power

256K

FEATURES:

DESCRIPTION:

• High-density 512K-bit CMOS static RAM module

The IDT7M8121IDT7M912 are 512K-bit high-speed CMOS
static RAMs constructed on a multi-layered ceramic substrate using8IDT718764Kx 1 static RAMs (IDT7M812) or9lDT7187static
RAMs (IDT7M912) In lead less chip carriers. Extremely high speeds
are achievable by the use of IDT71S7s fabricated in IDT's highperformance, high-reliability technology, CEMOS. This state-ofthe-art technology, combined with Innovative circuit deSign techniques, provides the fastest 64K static RAMs available.
The IDT7M8121IDT7M912 are available with access times as
fast as 25ns commercial and 35ns military temperature range, with
maximum operating power consumption of only 6.9W (IDT7M912,
64K x 9 option). The module also offers a standby power mode of
less than 3.2W (max.) and a full standby mode of 1.2W (max.).
The IDT7M8121IDT7M912 are offered in a high-density 40-pin,
600 mil center sidebraze DIP to take full advantage of the compact
IDT7187s in lead less chip carriers. The IDT7M912 (64K x 9) option
can provide more flexibility in system application for error detection, parity bit, etc.
All inputs and outputs of the IDT7M8121IDT7M912 are TTLcompatible and operate from a single 5V supply. (NOTE: Both Vee
pins need to be connected to the 5V supply and both GND pins
need to be grounded for proper operation.) Fully asynchronous circuitry is used, requiring no clocks or refreshing for operation, and
providing access and cycles times for ease of use.
All IDT military module semiconductor components are compliant to the latest revision of MIL-STD-883, Class B, making them
ideally suited to applications demanding the highest level of
performance and reliability.
-

• 64K x 8 (IDT7M812) or 64K x 9 (IDT7M912) configuration
• Fast access times
- Military: 35ns (max.)
-Commercial: 25ns (max.)
• Low power consumption
- Active: 2.4W (typ. in 64K x 8 organization)
- Standby: 240~W (typ. in 64K x 8 organization)
• Utilizes 8 (IDT7M812) or 9 (IDT7M912) IDT7187 highperformance 64K x 1 CMOS static RAMs produced with IDT's
advanced CEMOS TM technology
.
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Available in 40-pln, 600 mil center sidebraze DIP, achieving
very high memory density
• Single 5V(±10%) power supply
• Dual Vee and GND pins for maximum noise immunity
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components
compliant to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold
temperatures for all AC and DC parameters

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM
Ao -A I5
CS
WE

----.-~~------.-------~-------,
--~+-~------~------~r-----,
~~r.++----~r+----~r+----~

PIN NAMES
Ao-AIS
DIP
TOP VIEW
NOTES:
1. Both Vee pins need to be connected to the 5V supply and both GND pins need to be grounded for proper
operation.
2. Pin 18 is 08 and pin 23 is Y8 in 64K x 9 (IDT7M912) option and both 18 and 23 are NC in 64K x 8
(IDT7M812) option.
3. For module dimensions, please refer to module drawing M4 in the packaging section.

Address

Do- D8

Data Input

YO-Y8

Data Output

CS"

Chip Select

WE

Write Enable

Vee

Power

GND

Ground

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated DevIce Technology, Inc.

DECEMBER 1987
DSC-7013/-

13-57

IDT7M812/IDT7M912 512K(64Kx8-BIT or 64Kx9-BIT)
CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM

RATING

COMMERCIAL

Terminal Voltage
with Respect to
GND

-0.5 to +7.0

MILITARY

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

UNIT

-0.5 to +7.0

GRADE

V

Military

TA

Operating
Temperature

Oto +70

-55 to +125

°C

T81AS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +155

°C

Commercial

SYMBOL

SYMBOL

lIu l

PARAMETER
Input Leakage Current

Illol

Output Leakage Current

leel

Operating Power Supply
Current

Vee

CS
CS

OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V ± 10%

Vcc

PARAMETER

MIN.

TYP.

MAX.

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

V

Input Low Voltage

-

6.0

Vil

0.8

V

-0.5(1)

UNIT

NOTE:
1. Vil = -3.0V for pulse width less than 20ns.

+ 70°C)

TEST CONDITIONS
Vee

GND

RECOMMENDED DC OPERATING CONDITIONS

DC Output Current
50
50
mA
lOUT
NOTE.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating ~on­
ditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS
Nee = 5.0V ±10%, TA = -55°C to + 125°C and O°C to

AMBIENT
TEMPERATURE
-55°C to + 125°C

MIN.

IDT7M912
TYP. MAX.(3) MAi4 MIN.

= 5.5V; \iN = GND to \be
= 5.5V
= ViH, VOUT

20

= GND to Vee

= Vll, Output Open

Min. Duty Cycle

lee2

Dynamic Operating Current

Min. Duty Cycle
Output Open

IS8

Standby Power Supply
Current

CS2:\IH
Min.-outy Cycle

IS81

Full Standby Power Supply
Current

CS 2: Vee

VOL

Output Low Voltage

540

= 100%
= 100%

540

10S0
10S0

IDT7M812 (3)
(4 UNIT
TYP. MAX. MAX.

{~g;:;::

=r~~:

4S0

::::::::::;:::::.;.
:::;:;:;:;:;.;.;.;.

,gp::;::;::

~A

960

n:~d::;:

mA

:::;:;:;:;:;.;.;.;.

,1530
"

20

480

960

1360::

mA

'"

= 100%

270

450

",:Sw.:

240

400

,scit:

mA

-0.2V
VIN 2: Vee -0.2V or:5 0.2V

0.2

180(2) :::::~~:

0.05

160 (2) ::?QQ:{

mA

IOl
10l

= 10mA, Vee = Min.
= SmA, Vee = Min.
= -4mA, Vee = Min.

VOH
Output High Voltage
10H
NOTES:
1. Typicallimits are at Vee = 5.0V, + 25°C.
2. IS81 (max.) of IDT7MS12/912 at commercial temperature = SOmA/90mA.
3. tAA = 30, 35, 45, 55ns
4. tAA = 25ns

13-58

0.5
0.4
2.4

-

(:::0:5
I:jf4
(,:,1""",:

2.4

0.5

,,'tIt):'

0.4

:tD~4;:

V

- (,::h::::

V

V

IDT7M812/1 DT7M912 512K (64K x 8-BIT or 64K x 9-BIT)
CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1, 2 and 3

DATA OUT

~

255!l

5V

48on
DATA OUT
30pF

~

255!l

Figure 1. Output Load

48on
5pF*

Figure 2. Output Load
(for tHZ. tLZ. two and tow>

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
(Vcc = 5V +10% TA = -55°C to + 125°C and O°C to + 70°C)
SYMBOL

PARAMETER

7M912S35
7M912S45
7M912S65
7M912S25
7M912S30
7M912S55
7M812S45
7M812S55
7M812S65
7M812S35
7M812S25
7M812S30
COM'LONLY COM'L. ONLY
MIN.
MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
MAX. MIN.

UNIT

READ CYCLE
t RC

Read Cycle Time

tAA

Address Access Time

tAcs

Chip Select Access Time

tOH

Output Hold from Address Change

tLZ

Chip Selection to Output in Low Z

tHZ

Chip Deselection to Output in High Z

t pu

Chip Selection to Power Up Time

t po

Chip Selection to Power Down Time

-

30

-

35

-

45

-

55

-

65

-

25

-

30

-

35

-

45

-

55

65

ns

35

-

45

-

55

-

65

ns

2&::::::....
~t::::::::·:·····

.:.;::;'",

":::::::::::"

;:;::"

..:;.:.:.:;:.....

~

d:::\:::::i\::::::::::

30

ns

5

-

5

-

5

-

5

-

5

-

5

-

5

-

5

-

5

-

ns

5

- ······::::;.::::-"-20

-

25

-

25

-

30

-

30

-

30

ns

(j::::}\):-

0

-

0

-

0

-

0

-

0

-

ns

-

30

-

35

-

35

-

35

-

35

ns

30

-

35

-

45

-

55

-

65

35

-

40

55

-

ns

35

5

5

-

..... ::.:.:::::::{
"'.:.:::: ...... :;:.::
I';:

~::::::-:.:

'25

ns

WRITE CYCLE
twc

Write Cycle Time

tcw

Chip Selection to End of Write

tAW

Address Valid to End of Write

2M?}}:
?~:::::::::::::::::::::::;.:-

-

28

50

40

50

5

-

55

-

ns

tow

Data Valid to End of Write

tOH

Data Hold Time

f'U:'

5

-

twz

Write Enable to Output in High Z

0:»:

0

25

0

25

0

30

0

30

0

35

ns

tow

Output Active from End of Write

0

-

0

-

0

-

0

-

0

-

ns

23....

t AS

Address Set-up Time

:3

twp

Write Pulse Width

20::

tWR

Write Recovery Time

6

..

28
3

':\'}~{:~

25

)r-

0

1:::::::::::::::::::::::::::::-

20

(:;:.;./:::.:.:::::.:.:

20

13-59

30
0
20

5
30
0
25

ns

5

-

5

-

ns

35

-

40

0

0

ns

30

-

ns

5

-

-

5

-

ns

25

ns

IDT7M812/IDT7M912512K(64KxB-BITor64Kx9-BIT)
CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1

(1,2)

f=14----tRC(5)---.t~
ADDRESS

DATAoUT

-------'1==

lOll

1M

-------4.~'

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.2

DATA VALID

(1,3)

....- - - - - - - - t RC (5)

---------+1

DATAoUT

DATA VALID
HIGH IMPEDANCE

Vee SUPPLY
CURRENT

~----~~~~~~~~~~~~

NOTES:
1. WE is high for READ cycle.
2. ~ is low for READ cycle.
3. Address valid prior to or coincident with ~ transition low.
4. Transition is measured ±2oomV from steady state voltage with specified loading in Figure 2. This parameter is sampled, not 100% tested.
5. All READ cycle timings are referenced from the last valid address to the first transitioning address.

13-60

---------------------------.
IDT7M812/IDT7M912 S12K(64Kx 8-BITor 64Kx 9-BIT)
CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twe
ADDRESS

~

-----./

<

)(
/'

~

,

tAW
~,

t

- tAS

(7)

.... ~

wr=.

:.-

tWR

WP

./~

_t

-t
(6)WHZ
tOHZ

(6)_

(6)

-tow

(4)

DATA OUT

OHZ

(4)

tow_

tOH

----------~E---->~~-----TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)

twe
ADDRESS

=:) (

)(
"-

_t

,

tAW

/'
tWR

tew

As

,
I'

tow

tOH

'"

./1

NOTES:
1.
or ~ must be high during all address transitions.
2. A write occurs during the overlap (wp) of a low ~ and a low
3. tWR is measured from the earlier of ~ or
going high to the end of write cycle_
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the ~ low transition occurs simultaneously with or after the
low transition, the outputs remain in a high impedance state.
6. Transition is measured ±500mV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a
controlled write cycle, write pulse (twp) > tWHZ + taw) to allow the I/O drivers to tum off and data to be placed on the bus for the required t ow - If
DE" is high during a ~ controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wP '

wr=.

wr=.

wr=..

wr=.

wr=.

13-61

IDT7M812/IDT7M912 512K (64Kx 8-BITor64Kx 9-BIT)
CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE

CAPACITANCE

(TA= +25°C, f = 1.0MHz)

CS

WE

Standby

H

X

HighZ

Standby

CIN

Input Capacitance

Read

L

H

DATA OUT

Active

C OUT

Output Capacitance

Write

L

L

HighZ

Active

MODE

OUTPUT

SYMBOL

POWER

TEST

CONDITIONS

TYP.

UNIT

VIN = OV

80

pF

VOUT= OV

15

pF

NOTE:
1. This parameter is sampled and not 100% tested.

ORDERING INFORMATION
lOT

xxxxx

999

A

A

Device Type

Speed

Package

Process/
Temperature
Range

y~ank
'-----------1 C
25
~

___________

30
~

35

Commercial (O°C to

Military (-55°C to + 125°C)
Semiconductor Components Compliant to
MIL-STD-883, Class B
Sidebraze DIP
Commercial Only
Commercial Only

} Speed in Nan"","ond,

45
55
65

~----------------------------~
~

S

________________________--; 7M812
7M912

13-62

+ 70°C)

Standard Power
64K x 8-Bit
64Kx9-Bit

FEATURES:

DESCRIPTION:

• High-density 256K (32K x 8-bit) CMOS static RAM module
• Equivalent to JEDEC standard for future monolithic 32K x 8
static RAMs

The IDT7M856 is a 256K (32,768 x 8-bit) high-speed static RAM
constructed on a co-fired ceramic substrate using four IDT7198
(16,384 x 4) static RAMs in lead less chip carriers, Functional
equivalence to proposed monolithic 256K static RAMs is
achieved by utilization of an on-board decoder, used as an
inverter, that interprets the higher order address A14 to select two
of the four 16K x 4 RAMs. Extremely fast speeds can be achieved
with this technique due to use of 64K static RAMs and the
decoder fabricated in IDT's high-performance, high-reliability
CEMOS technology.
The I DT8M856 is available with maximum access times as fast
as 40ns for commercial and 55ns for military temperature ranges,
with maximum power consumption of only 2 watts. The circuit
also offers a reduced power standby mode. When CS goes high,
the circuit will automatically go to a standby mode with power
consumption of only 1.1mW (max.). Substantially lower power
levels can be achieved in a full standby mode (440mW max.).
The IDT8M856 is offered in a 28-pin, 600 mil center sidebraze
DIP. This provides four times the densityofthe IDT7M864 (8Kx 8
module) in the same socket with only minor pin assignment
changes. In addition, the JEDEC standard for 256K monolithic
pinouts has been adhered to, allowing for compatibility with
future monolithics.
All inputs and outputs of the IDT7M856 are TTL-compatible
and operate from a single 5V supply. Fully asynchronous
circuitry is used requiring no clocks or refreshing for operation,
and provides equal access and cycle times for ease of use.
All IDT military module semiconductor components are 100%
processed to the test methods of MIL-STD-883 Class B, making
them ideally suited to applications demanding the highest level
of performance and reliability.

• High-speed - 40ns (max.) commercial; 55ns (max.) military
• Low-power consumption; typically less than 1W operating,
less than 1mW in standby
• Utilizes IDT7198s-high-performance 64K static RAMs
produced with advanced CEMOS™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with lOT's high-reliability vapor phase solder
reflow process
• Pin compatible with IDT7M864 (8K x 8 SRAM module)
• Offered in the JEDEC standard 28-pin, 600 mil wide ceramic
sidebraze DIP
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components 100%
screened to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold
temperatures for all AC and DC parameters as per
customer requirements

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

AO-A13---__- - - - - - - - - ,

PIN NAMES
AO- A14

--_-t-----------,

1/01-1/04
1/05 -1/08 ----~~------tOH

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 2, 3, 5)

twe
ADDRESS

~

-----./

)K

K
tAW

I - - - tAS

'"

~I/
tWR

tew

I--

tOH

tow

""'

1-'

-'I

I"

NOTES:
1. WE or 'CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the 'CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig), This parameter is sampled and not 100% tested.
7. During a WE controlled write cycle, write pulse (twP) > tWHZ + tow) to allow the I/O drivers to tum off and data to be placed on the bus for the required tow· If
at: is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wP '

13-78
-

-----.----------.-----

~~~

IDT8MP624S/IDTSMP612S 1024K (64Kx 16-BIT) &
512K (32K x 16-BIT) CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

CAPACITANCE(TA= +25°C, f = 1.0MHz)

TRUTH TABLE
MODE

CS UB LB

OE WE

OUTPUT

POWER

Standby

H

X

X

X

X

HighZ

Standby

L

H

H

X

X

HighZ

Standby

Read

L

L

L

L

H

Lower Byte Read

L

H

L

L

H

DOUT 1-16
DOUT1 _8

Active

Upper Byte Read

L

L

H

L

H

DoUTg_16

Active (X8)

Read

L

L

L

H

H

HighZ

Active

Lower Byte Read

L

H

L

H

H

HighZ

Active (X8)

Upper Byte Read

L

L

H

H

H

HighZ

Active (X8)

Write

L

L

L

X

L

~N 1-16

Active

Lower Byte Write

L

H

L

X

L

~N 1-8

Active (X8)

Upper Byte Write

L

L

H

X

L

DINg_16

Active (X8)

Standby

SYMBOL

PARAMETER

CIN
COUT

Input Capacitance

(1)

Output Capacitance

CONDITIONS

35

Vour= OV

40

NOTE:
1. This parameter is sampled and not 100% tested.

Active (X8)

ORDERING INFORMATION
IDT

XXXX
A
Device Type Power

999
Speed

A

A

Package

Process!
Temperature
Range

Y

1 . -_ _ _ _ _ _ _- /

L.....------------l

BLANK

CommerclaJ(O'Cto +70°C}

S

Plastic SIP

40
45
~

}
Speed in Nanoseconds

70
L----------------~S

L.....__________________--I

13-79

~~~~~~

Standard Power

~~ ~ ~~=~~

TYP.

VIN = OV

UNIT
. pF
pF

FEATURES:

DESCRIPTION:

• High-density 256K/12SK CMOS static RAM modules

The IDTSMP656S/IDTSMP62SS are 256K/12SK-bit high-speed
CMOS static RAMs constructed on an epoxy laminate substrate
using four IDT7164 SK x S static RAMs (IDTSMP656S) or two
IDT7164 static RAMs (I DTSMP62SS) in plastic surface mount
packages.
Functional equivalence to proposed monolithic static RAMs is
achieved by utilization of an on-board decoder that interprets the
higher order address A'3 to select one of the two SK x 16 RAMs as
the by-16 output and using LB and UB as two extra chip select
functions for lower byte (l/O,-e) and upper byte (1/09-16) control,
respectively. (On the IDTSMP62SS SK x 16 option, A 13 needs to be
externally grounded for proper operation.) Extremely high speeds
are achievable by the use of IDT7164s, fabricated in IDT's highperformance, high-reliability CEMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides the fastest 256K/12SK static RAMs available.
The IDT8MP656S/IOT8MP628S are available with maximum
operating power consumption of only 1.SW (IDTSMP656S 16K x 16
option). The modules also offer a full standby mode of 330mW
(max.).
The IDTSMP656S/IDTSMP62SS are offered in a 40-pin plastic
SIP. For the JEDECstandard 40-pin DIP, refer to the IDTSM656S1
IDTSM62SS.
All inputs and outputs of the IOT8MP656S/IDT8MP628S are
lTL-compatible and operate from a single 5V supply. (NOTE: Both
GND pins need to be grounded for proper operation.) Fully asynchronous circuitry is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of

• 16K x 16 organization (IDTSMP656S) with S!< x 16 option
(IDTSMP62S)
• Upper byte (1I09-1S) and lower byte (1/0,-8) separated control
- Flexibility in application
• Fast access times
- 40ns (max.)
• Low power consumption
- Active: less than S25mW (typ. in 16K x 16 organization)
- Standby: less than 20mW (typ.)
• Cost-effective plastic surface mounted RAM packages on an
epoxy laminate (FR4) substrate
• Offered in an SIP (single in-line) package for maximum
space-savings
• Utilizes 1DT7164s-high-performance 64K static RAMs
produced with advanced CEMOS 1M technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly lTL-compatible

use.

FUNCTIONAL BLOCK DIAGRAM
AO-12

1/09-16
WE
OE

'---

"'-----<

t:

11

1017164
8Kx8
CMOS
STATIC
RAM

1017164
8Kx8
CMOS
STATIC
RAM
(

'---

1017164
8Kx8
CMOS
STATIC
RAM

1017164
8Kx8
CMOS
STATIC
RAM
()

()

()

1/2 FCT139
I DECODER I'"

-t?

L=t

P.

1/2 FCT139 'L..
DECODER

\(

CEMOS is a trademark of Integrated Device Technology, Inc.

DECEMBER 1987

COMMERCIAL TEMPERATURE RANGE
©

19S71n1egrated DevIce Technology. Inc.

DSC-7016/-

13-80

IDTSMP656S/IDTSMP62SS CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16K x 16-BIT) & 12SK (SK x 16-BIT)

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION

PIN NAMES

M13*
1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031323334353637383940

A5

A3

~

As

Al
A2

[B Vee VOl V03 V0 5

Ao

VCr

CS

V09 V0 11

va.

V015

GND Us'

"e Al0 A12 A14

WE GNo!l) V02 V04 V06 V0 8 OE V010 V012 V014 V016 A15 A7

A9

All A13

NOTE:
• For module dimensions, please refer to module drawing M13 in the packaging section.

SYMBOL
VTERM
TA

Data Input/Output

CS

Chip Select

Vec

Power

WE

Write Enable

OE

Output Enable

GND

Ground

UB

Upper Byte Control

LB

Lower Byte Control

RECOMMENDED DC OPERATING CONDITIONS

(1)

RATING
Terminal Voltage with Respect
toGND

Addresses

1/01-16

NOTES:
1. Both Vee pins need to be connected to the 5V
supply and both GND pins need to be
grounded for proper operation.
2. On IDTSMP628S, 12SK (SK x 16-Bit) option,
A 13(Pin 35) is required extemal grounding for
proper operation.

SIP
FRONT VIEW

ABSOLUTE MAXIMUM RATINGS

AO-13

VALUE

UNIT

MIN,

TYP.

MAX.

UNIT

-0.5 to +7.0

V

Vec

Supply Voltage

4.5

5.0

5.5

V

Oto +70

DC

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

6.0

V

VIL

Input Low Voltage

-0.5(1)

-

O.S

V

Operating Temperature

TBIAS

Temperature Under Bias

-10 to +S5

DC

TSTG

Storage Temperature

-55 to +125

DC

loUT

DC Output Current

50

SYMBOL

PARAMETER

NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Vee
5.0V ± 10%

DC ELECTRICAL CHARACTERISTICS

-

Vee = 5 OV + 10% Vcc (Min.) = 4.5V, Vee (Max) = 5 5V VLC = 0.2V, VHC = Vee = - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS

IDTSMP656S
MIN. TYP. MAX.

IDTSMP62SS
MIN. TYP. MAX.

-

-

15

-

-

15

Operating Current In X16 Mode

CS, UB & LB = "'L
Vee = Max., Output Open
f = fMAX

-

165

leex8

Operating Current In X8 Mode

CS = "'L, UB or LB = "'L
Vec = Max., Output Open
f = fMAX

-

ISB&
ISBl

Standby Power Supply Current

CS ~ "'H or
US ~ "'H and [8
Vee = Max.
Output Open

-

Input Leakage Current

Vee = Max.; "'N = GND to Vee

Output Leakage Current

Vee = Max.
CS = "'H, VOUT = GND to Vec

leex16

Ilul
IILol

~ ~H

15

J.LA

-

15

J.LA

330

-

150

300

mA

100

200

-

SO

170

mA

4

60

-

2

30

rnA

-

0.4

V

-

V

VOL

Output Low Voltage

10L = SmA, Vee = Min.

-

-

0.4

VOH

Output High Voltage

10H = -4mA, Vee = Min.

2.4

-

-

13-S1

UNIT

-'
-

2.4

IDT8MP656S/IDT8MP628S CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16K x 16-BIT) & 12SK (SK x 16-BIT)

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

~

5V48on

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

DATA OUT

255fl

5V48on

~

DATA OUT
30pF

255fl

Figure 1. Output Load

5pF*

Figure 2. Output Load
(for tCU1 ,2' tau. t CHZ1 ,2' toHz.
tow.tWHZ )

*Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETERS

(Vcc= 5V ±10%, TA = O°C to +70°C)
IDTSMP656S40
IDT8MP628S40
MIN.
MAX.

IDTSMP656S50
IDTSMP62SS50
MIN.
MAX.

IDT8MP656S70
I DT8M P628S70
MIN.
MAX.

IDT8MP656S85
IDT8MP62SSS5
MIN.
MAX.

UNIT

READ CYCLE
t Rc

Read Cycle Time

40

-

50

-

70

-

85

-

ns

tM
t Acs

Address Access Time

-

40

-

50

-

70

85

ns

Chip Select Access Time

-

40

-

50

-

70

-

85

ns

t cLZ1 .2 (1)

Chip Select to Output in Low Z

5

-

5

-

5

-

5

-

ns

tOE
t
(l)
oLZ
t
(l)
cHZ
t OHZ (l)

Output Enable to Output Valid

-

25

-

30

-

40

-

50

ns

Output Enable to Output in Low Z

5

-

5

-

5

-

5

-

ns

Chip Select to Output in High Z

15

-

20

-

30

-

35

ns

35

ns

5

-

ns

0

-

ns
ns

Output Disable to Output in High Z

-

15

-

20

t

Output Hold from Address Change

5

-

5

5

t pU (l)

Chip Select to Power Up Time

0

-

0

-

0

-

t pO (l)

Chip Deselect to Power Down Time

-

40

-

50

-

70

-

85

50

-

70

-

85

-

ns

45

-

65

-

75

-

ns

45

-

65

-

75

10

-

10

55

-

65

5

-

-

ns

5

5

-

10

-

ns

25

-

30

ns

35

ns

5

-

5

-

ns

30

WRITE CYCLE

tAW

Address Valid to End of Write

35

t AS

Address Set-up Time

5

twp

Write Pulse Width

30

tWR
t WHZ (l)

Write Recovery Time

5

-

Write Enable to Output in High Z

-

15

-

20

-

tow

Data to Write Time Overlap

15

-

20

-

30

tOH

Data Hold from Write Time

5

5

Output Active from End of Write

5

-

5

t oW (1)

-

-

5

-

two

Write Cycle Time

40

tcw

Chip Selection to End of Write

5

40

5

NOTE:
1. This parameter guaranteed but not tested.

13-82

ns
ns

ns

IDT8MP656S/IDT8MP628S CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16K x 16-BIT) & 128K (8K x 16-BIT)

TIMING WAVEFORM OF READ CYCLE NO.

COMMERCIAL TEMPERATURE RANGE

1(1)

~-----------------tRC--------------~

ADDRESS

OE

UB,LB &CS
,......- - - - - tAcs------+--.......r
1 _ - - - - - - - tCLZ (5),------J

DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.

ADDRESS

=f:
....

DATAoUT

2(1,2,4)

t RC

•I

tAA

.1

taH

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

DATA VALID

3(1,3,4)

Us,LB &CS

DATAoUT

NOTES:
1.
2.
3.
4.
5.

WE is High for Read Cycle.
_
_ _
Device is continuously selected, CS =
and US, LS =
for 16 output active.
Address valid prior to or coincident with ~ transition low.
DE = V1L
Transition is measured ±2oomV from steady state. This parameter is sampled and not 100% tested.

"'L

E~

"'L

13-83

IDTSMP656S/IDTSMP62SS CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16K x 16-BIT) & 12SK (SK x 16-BIT)

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1, 2,3,7)
twc
ADDRESS

~

---./

)(

K

~~
~

tAW

~~

'"

- tAS

.....

'"

-t
tOHZ

r-

tWR

twf)

WE

~"

i4-- t OHZ ( 6 ) _

(6)-

WHZ

(6)

- tOW

-1

(4)

DATA OUT

(4)

tow_

----------~E---->~~-----tOH

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3, 5)

twc
ADDRESS

=>K

)K
tAW

'~
~tAS

/V
tWR

tcw

tow

f--

tOH

1/

,

I'

"1

NOTES:
1. WE or 'CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a WE controlled write cycle, write pulse (twp) > tWHZ + tow) to allow the I/O drivers to tum off and data to be placed on the bus for the required tow. If
~ is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wP '

13-S4

IDT8MP656S/IDT8MP628S CMOS STATIC RAM
PLASTIC SIP MODULE 256K (16K x 16-BIT) & 12SK (SK x 16-BIT)

COMMERCIAL TEMPERATURE RANGE

CAPACITANCE (TA= +25°C, f

TRUTH TABLE
CS UB LB

MODE

OE WE

OUTPUT

Standby

H

X

X

X

X

High Z

Standby

Standby

L

H

H

X

X

HighZ

Standby

Read

L

L

L

L

H

L

H

L

L

H

DOUTH6
DOUT1 _8

Active

Lower Byte Read
Upper Byte Read

L

L

H

L

H

DoUTg_16

Active (X8)

Read

L

L

L

H

H

HighZ

Active

qN

Lower Byte Read

L

H

L

H

H

HighZ

Active (X8)

L

L

H

H

H

HighZ

Active (X8)

Write

L

L

L

X

L

D1NH6

Active

Lower Byte Write

L

H

L

X

L

D1N1_B

Active (X8)

Upper Byte Write

L

L

H

X

L

DIN9_16

Active (X8)

Input Capacitance

= 1.0MHz)

CONDITIONS
V1N = OV

COUT
Output Capacitance
VOUT= OV
NOTE:
1. This parameter is sampled and not 100% tested.

Active (X8)

Upper Byte Read

PARAMETER(1)

SYMBOL

POWER

TYP.

pF

40

pF

Address Access Time vs.
Capacitive Load
1.2

I
(TA= +25°C)

""
~
]

1.1

...
o

Z

/~

1-=

/
o

i-"

XXXX

A

Device Type Power

999

A

A

Speed

Package

Process/
Temperature
Range

yBLANK

L-----------tS

~

__________

50
Capacitive Load (pF)

+ 70°C)

Plastic SIP

40
~50

70
85

~---------------1S

~-------------------1~~~~~~

13-85

Commercial (O°C to

} Speed In Nonosecond,

Standard Power

16K x 16-Bit
8K x 16-Bit

~

./

ORDERING INFORMATION
IDT

UNIT

35

100

FEATURES:

DESCRIPTION:

• High-density 1024K (12SK x S) CMOS static RAM module

The IDTSMPS24S is a 1024K (131,072 x S-bit) high-speed static
RAM constructed on an epoxy laminate substrate using four
ID171256 32K x S static RAMs in plastic surface mount packages.
Functional equivalence to proposed monolithic one megabit static
RAMs is achieved by utilization of an on-board decoder that interprets the higher order address A15 and A16 to select one of the four
32K x S RAMs. Extremely fast speeds can be achieved with this
technique due to use of 256K static RAMs and the decoder fabricated in IDT's high-performance, high-reliability CEMOS technology.
The IDTSMPS24S is available with maximum access times as
fast as 40ns over the commercial temperature range, with maximum operating power consumption of S25mW. The module also
offers a full standby mode of 330mW (max.).
The IDTSMPS24S is offered in a 30-pin SIP. For the 32-pin
JEDEC standard DIP, refer to the IDTSMS24S.
All inputs and outputs of the IDTSMPS24S are ITL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of use.

• Fast access time
- 40ns (max.) over commercial temperature range
• Low power consumption
- Active: less than 500mW (typ.)
- Standby: less than SmW (typ.)
• Cost-effective plastic surface-mounted RAM packages on an
epoxy laminate (FR4) substrate
• Offered in a SIP (single in-line package) for maximum spacesaving
• Utilizes ID171256s-high-performance 256K static RAMs produced with advanced CEMOS ™ technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Single 5V (±10%) power supply
• Inputs and outputs directly ITL-compatible

PIN CONFIGURATION

10
11
12
13
14
M12(1) ::
17
18
19
20

21
22

23
24
25
26

27
28
29

30

A7
A6
A5
A4
A3
A2
Al
Ao
WE
Vce
GND
1/°1
1/°2
1/°3
1/°4
1/°5
1/°6
1/07
1/°8
CS
OE
A8
A9
Al0
All
A12
A13
A14
A15
A16

FUNCTIONAL BLOCK DIAGRAM

-

-

L..~

-

...
...
...
r--'

IDT71256
32Kx8
t:MOS
STATIC
RAM

IDT71256
32Kx8
CMOS
STATIC
RAM
~

CS~

L-

CS~

IDT71256
32Kx8
CMOS
STATIC
RAM

IDT71256
32Kx8
CMOS
STATIC
RAM
CS~

CS

FCT139
DECODER r--'

...

I"

-C

PIN NAMES
,

A O- 16

\

1/°1-8
CS
Vcc
WE
OE
GND

SIP
SIDE VIEW

Addresses
Data Input/Output
Chip Select
Power
Write Enable
Output Enable
Ground

1. For module dimensions, please refer to module drawing M12 in the packaging section.
CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

DECEMBER 1987

© 1987 Inlegrated DevIce Technology, Inc.

DSC-7015/13-86

IDTSMPS24S 1 MEGABIT
(12SK x S-BIT) CMOS STATIC RAM PLASTIC SIP MODULE

ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM

COMMERCIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING CONDITIONS

(1)

RATING
Terminal Voltage with Respect
to GND

VALUE

UNIT

-0.5 to +7.0

V

MIN.

TYP,

MAX.

UNIT

Vcc

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

-

6.0

V

O.S

V

SYMBOL

PARAMETER

TA

Operating Temperature

Oto +70

°C

TBIAS

Temperature Under Bias

-10 to +S5

°C

VIH

Input High Voltage

2.2

°C

Vil

Input Low Voltage

-0.5(1)

TSTG
10LIT

Storage Temperature

-55 to +125

50

DC Output Current

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

NOTE:
1. Vil (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
AMBIENT
TEMPERATURE

Vcc
5.0V ±10%

DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V +10%, Vcc (Min.) = 4.5V, Vcc (Max.) = 5.5V, VlC = 0.2V, VHC = Vcc - 0.2V
SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

UNIT

-

15

J.l.A

-

15

j.J.A

-

60

150

mA

CS = ~l
Vcc = Max., Output Open
f = fMAX

-

100

200

mA

Standby Power Supply Current

CS ~ ~H or (TTL Level)
Vcc= Max.
Output Open

-

2

80

rnA

ISBl

Full Standby Power Supply Current

CS ~ VHC. ~N ~ VHC or S VlC
Vcc = Max., Output Open

-

1.6

60

rnA

VOL

Output Low Voltage

10l = SmA, Vcc = Min.

-

-

0.4

V

10H = -4mA, Vcc' = Min.

2.4

-

-

V

lIu l

Input Leakage Current

Vcc = Max.; ~N = GND to Vcc

IIlol

Output Leakage Current

Vcc = Max.
CS = ~H' VOLIT = GND to Vcc

ICCI

Operating Power Supply Current

CS =~l
Vcc = Max., Output Open
f= 0

ICC2

Dynamic Operating Current

ISB

VOH
Output High Voltage
NOTE:
1.Vcc = 5V,TA=+25°C

-

IDTSMPS24S
TYP.(l) MAX.

AU lD it 9~ 9c53SC(
~ ~Co(j @ I I~
~vr'(fq;

~~~

13-S7 .

(goB
.

IBJ

IDT8MP824S 1 MEGABIT
(128Kx 8-BIT) CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
In Pulse levels
Input Rise/Fall Times
Input Timing Reference levels
Output Reference levels
Output Load

5V
GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATAoUT

~

255fl

5V

48on

DATAoUT

30pF

~

255fl

Figure 1. Output load

48on
5pF*

Figure 2. Output load
(for tCLZl ,2' tQlZ' t CHZ1 ,2' t OHZ '
tOW.tWHZ)

*Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vce

= 5V

± 10%. 1A

8MP824S40
MAX.
MIN.

PARAMETERS

= O°C to + 70°C)

8MP824S45
MIN.
MAX.

8MP824S50
MIN.
MAX.

8MP824S60
MIN.
MAX.

8M824S70
MIN.
MAX.

UNIT

READ CYCLE
t RC

Read Cycle Time

40

:=:::;~;;;\>::.:..::-

45

-

50

-

60

-

70

-

ns

tAA
t ACS

Address Access Time

-

::};);}::':"""4(f

45

-

50

ns

45

-

50

60

-

70

-

-

60

Chip Select Access Time

-

70

ns

5

-

5

-

5

-

5

-

ns

::{}}\::..:/W
5 t\~;~;~/::{;::;:::m

t CLZ1 ,2 (1) Chip Select to Output in low Z
tOE
t
(l)
OLZ
t
(l)
cHZ
t
(l)
oHZ

Output Enable to Output Valid

-

:?E.l

-

25

-

30

-

35

-

40

ns

Output Enable to Output in low Z

5

-

5

-

5

-

5

-

ns

Chip Select to Output in High Z

5 (((::;:::::::://
- .... "':'::::2'0

20

-

20

ns

20

-

20

25

-

30

-

-

25

Output Disable to Output in High Z

-

30

ns

5

-

5

5

-

5

0

-

0

0

-

0

-

ns

:~{:~{{:~:tt~\-

-

,n

-

45

-

50

-

60

-

70

ns

45

50

60

5

-

ns

5

-

70

5

-

40

-

50

-

60

-

ns

3::::::::::::;:;:;:;:;:;:;:;:;:;:;;L

Output Hold from Address Change

tOH
t pU (l)

Chip Select to Power Up Time

t po (l)

Chip Deselect to Power Down Time

..:.::::::::;::;};;;:;::::20

0:

':':'.'

.~~

WRITE CYCLE

ns

-

40

::::? -

40

-

5

Write Pulse Width

~9;:':tr:w-

35

-

tWR
t
(l)
wHZ

Write Recovery Time

:1f:;::;:{{:)~{?

5

-

5

-

5

-

5

-

ns

-

15

-

20

-

25

-

30

ns

tow

Data to Write Time Overlap

1'''To:::;:::;:::::;:::;::::::

tOH

Data Hold from Write Time

I~:::if:\~::::

-

5

-

5

-

5

-

5

-

ns

Output Active from End of Write

i:::5:::))}tt~:

-

5

-

5

-

5

-

5

-

ns

twc

Write Cycle Time

tcw

Chip Selection to End of Write

3~~\{:;:;:;:;: ;.::::::::

tAW

Address Valid to End of Write

35

t AS

Address Set-up Time

5<~t):\)):}

twp

t

oW

(l)

Write Enable to Output in High Z

I

-

;:iF:\:}:):~~{? 15

20

NOTE:
1. This parameter guaranteed but not tested.

13-88

45
45

20

55
55

25

65
65

30

ns
ns
ns

ns

IDTSMPS24S 1 MEGABIT
(12SK x S-BIT) CMOS STATIC RAM PLASTIC SIP MODULE

TIMING WAVEFORM OF READ CYCLE NO.

COMMERCIAL TEMPERATURE RANGE

1(1)

14---------tRC

--------+1

ADDRESS

DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.

ADDRESS

DATA OUT

~

2(1,2,4)

t RC

.1

tAA

.'

tOH

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

DATA VALID

3(1,3,4)

DATAoUT

NOTES:

1. WE is High for Read Cycle.
2. Device is continuously selected, CS = V IL '.
3. Address valid prior to or coincident with "OS transition low.
4. OE = V1L
5. Transition is measured ±2oomV from steady state. This parameter is sampled and not 100% tested.

13-S9

------------

IDT8MP824S 1 MEGABIT
(128K x 8-Bm CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,7)
twc
ADDRESS

~

----./

<

)K:
/'

~

tAW

)~

~

f4--

t As
.....

t

,
-t

tOHZ

(7)

tWR

WP

f-

~,.,.

14--- tOHZ ( 6 ) _
(6)-

WHZ

(6)

-tow

(4)

DATA OUT

(4)

tow_

----------~E--~>~~-----tOH

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)

ADDRESS

twc

=>K

)(
tAW

~tAS

"

/'1'
tWR

tcw

tow
1/

I"

~

tOH

"/1

NOTES:
1. WE or ~ must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low ~ and a low
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
S. If the CS" low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter Is sampled and not 100% tested.
7. During a WE controlled write cycle, write pulse (twPl > tWHZ + tow) to allow the I/O drivers to tum off and data to be placed on the bus for the required tow. If
DE" is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp •

vrc..

13-90

IDT8MP824S 1 MEGABIT
(128K x 8-BIT) CMOS STATIC RAM PLASTIC SIP MODULE

COMMERCIAL TEMPERATURE RANGE

CAPACITANCE(TA =+25°C, f =

TRUTH TABLE
CS

OE

WE

OUTPUT

POWER

SYMBOL

Standby

H

X

X

HighZ

Standby

Read

L

L

H

DoUT

Active

CIN
COUT

Read

L

H

H

HighZ

Active

Write

L

X

L

DIN

Active

MODE

PARAMETER(1) .
Input Capacitance
Output Capacitance

1.0MHz)

CONDITIONS

TYP.

UNIT

VIN = OV

35

pF

VOUT= OV

40

pF

NOTE:
1. This parameter is sampled and not 100% tested.

ORDERING INFORMATION
lOT

XXXX
A
Device Type Power

A

A

Package

Process/
Temperature
Range

Y

L-_ _ _ _ _ _ _~

BLANK

Comme_ (DOC to +70°C)

S

Plastic SIP

40
45

L..-_ _ _ _ _ _ _ _ _ _- - j ~

}

Speed in Nanoseconds

70

L.. -. ______________-I S
L...-..-------------------t 8MP824

13-91

Standard Power

1 Megabit

FEATURES:

DESCRIPTION:

• Hlgh-density 1024K/512K-bit CMOS static RAM module

The IDT8M624S/IDT8M612S are 1024K/512K-bit high-speed
CMOS static RAMs constructed on a multi-layered ceramicsubstrate using four IDT71256 32K x 8 static RAMs (IDT8M624S) or
two IDT71256 static RAMs (IDT8M612S) In lead less chip carriers.
Functional equivalence to proposed monolithic static RAMs Is
achieved by utilization of an on-board decoder that Interprets the
higher order address A15 to select one ofthe two 32K x 16 RAMs as
the by-16 output and using LB and UB as two extra chip select
functions for lower byte (1/01-8) and upper byte (1109-16) control,
respectively. (On the IDT8M612S 32K x 16 option, A15 needs to be
externally grounded for proper operation.) Extremely high speeds
are achievable by the use of IDT71256s fabricated In lOT's hlghperformance, high-reliability technology, CEMOS. This state-ofthe-art technology, combined with Innovative circuit design techniques, provides the fastest 1024K/512K static RAMs available.
The IDT8M624S/1DT8M612S are available with access times as
fast as 40ns commercial and 60ns military temperature range, with
maximum operating power consumption of only 1.8W (max.IDT8M624S 64K x 16 option). The module also offers a full standby
mode of 440mW (max.).
The IDT8M624S/IDT8MP612S are offered In a high-density
40-pln, 600 mil center sidebraze DIP to take full advantage of the
compact IDT71256s in leadless chip carriers.
All inputs and outputs of the IDT8M624S/IDT8M612S are TTLcompatible and operate from a single 5V supply. (NOTE: Both
GND pins need to be grounded for proper operation.) FUllyasynchronous circuitry is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of
use.
All lOT military module semiconductor components are manufactured In compliance with the latest revision of MIL-STD-883,
Class B, making them ideally suited to applications demanding the
highest level of performance and reliability.

• 64K x 16 organization (IDT8M624S) with 32K x 16 option
(IDT8M612S)
• Upper byte (1109-16) and lower byte (I/O 1-8) separated control
- Allows flexibility In application
• Equivalent to JEDEC standard for future monolithic 64K x 16/
32K x 16 static RAMs
• High speed, 40ns (max.) over commercial temperature range
• Low power consumption
• CEMOS TM process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with lOT's high-reliability vapor phase solder reflow
process
• Offered In the JEDEC standard 40-pin, 600 mil wide ceramic
sldebraze DIP
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components compliant
to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold temperatures
for all AC and DC parameters

FUNCTIONAL BLOCK DIAGRAM
Ao-14
1/0 -1/08
1

1/09 -1/016

WE

0......-.

nI

IDT71256
32Kx8
CMOS
STATIC
RAM

~

L.--

IDT71256
32Kx8
CMOS
STATIC
RAM

;>

;>

C}

112 FCT139 L
DECODER

IDT71256
32Kx8
CMOS
STATIC
RAM

IDT71256
32Kx8
CMOS
STATIC
RAM

I'-'

Y

Y

~t8b13~ L..
I""
Y

CEMOS Is a trademark of Integrated Device Technology, Inc.

MILITARVAND COMMERCIAL TEMPERATURE RANGES
© 1987lntegraled DevIce Technology. Inc.

DECEMBER 1987
050-7017/-

13-92

IDT8M624S/IDT8M612S 1024K (64K x 16-BIT) &
512K (32K x 16-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION

PIN NAMES

A15(2)
~

1/°16

1/015
1/0 14

1/°13
1/°12
1/011

1/0 10
I/Og
GND(l)

Addresses

I/OH6

Data Input/Output

CS

Chip Select

WE

Write Enable

Vee

Power

GND

Ground

OE

Output Enable

UB

Upper Byte Control

Lower Byte Control
LB
NOTES:
1. Both GND pins need to be grounded for proper operation.
2. On IDTSM612S, 512K (32Kx 16-bit) option, A15 (pin 1) requiresextemal
grounding for proper operation.

. 110 8

1/0 7

1/0 6
1/0 5

1/0 4

1/0 3
1/° 2

RECOMMENDED DC OPERATING CONDITIONS

1/0 1

rrE'

MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

PARAMETER

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

6.0

V

VIL

Input Low Voltage

-

O.S

V

SYMBOL
DIP
TOP VIEW

NOTE:
* For module dimensions, please refer to module drawing M3 in the packaging section.

RATING

VTERM

Terminal Voltage
with Respect to
GND

TA

COMMERCIAL

-0.5(1)

NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL

AO- 15

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
GRADE
Military
Commercial

mA
DC Output Current
50
50
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

13-93

AMBIENT
TEMPERATURE
-55°C to 125°C

GND
OV

5.0V

± 10%

O°C to+70°C

OV

5.0V

±

Vee

10%

IDT8M624S/IDT8M612S 1024K (64K x 16-BIT) &
512K (32K x 16-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
Vee = 50V ±10% Vee (Min) = 45V Vee (Max) = 55V
SYMBOL

Ilu l

Iccx16

PARAMETER

TEST CONDITIONS

Input Leakage Current

Vee = Max.; "'IN = GND tOVee

Output Leakage Current

Vee= Max.
cs = "'IH VOUT = GND toVee

Operating Current In X16 Mode

CS, US & LS = V1L
Vee= Max., Output Open
f = fMAX

Operating Current In XS Mode

cs= "'IL ,US or LS ="'IL
Vee= Max., Output Open
f = fMAX

Standby Power Supply CUrrent

IDT8M624S
IDT8M612S
MIN. TYP.(l) MAX. MIN. TYP.(l) MAX.

-

cs C!: "'IH or _
US ~ V1H and LS ~ ~H

IOL = SmA, Vee= Min.

Output High Voltage

IOH= -4mA, Vee= Min.

NOTES:

1.Vee = 5V, TA =+25°C
2.ls8 and IS81 of IDTSM624S/IDTSM612S at commercial temperature = 6OmA/30mA.

13-94

15

-

-

15

-

15

-

-

15

175

340

-

100

200

4

Vee= Max.
Output Open

Output Low Voltage

-

SO(2)

300

mA

SO

170

mA

mA
0.4

2.4

J.1.A

150

2

0.4
2.4

UNIT

V
V

IDT8M624S/IDT8M612S 1024K (64K x 16-BIT) &
512K(32Kx 16-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V

GND to3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATA OUT

~

2550.

5V

4800
DATA OUT

~

2550

30pF

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for t CLZ1 .2 •t OLZ ' tCHZ1.2 •t OHZ '
tOW.tWHZ)

*Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(Vcc;: 5V ±10%. All Temperature Ranges)

8M624S40 ·8M624S45 8M624S50 8M624S60 8M624S70 8M624S85 8M624S100
8M612S40 8M612S45 8M612S50 8M612S60 8M612S70 8M612S85 8M612S100
(COM'L)
(COM'L)
(COM'L)
(MIL)
(MIL)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

UNIT

READ CYCLE

-

50

-

60

-

70

-

85

-

100

-

ns

/45

-

50

-

60

70

-

100

ns

-

50

-

60

70

-

85

45

-

85

-

100

ns

5

-

5

-

5

-

5

-

5

-

ns

- "25
-} 5 / -

-

30

-

35

-

40

-

50

-

60

ns

5

-

5

-

5

-

5

-

5

-

ns

~<20

-

20

-

25

30

ns

20

-

25

30

-

40

-

-

35

20

-

40

ns

5

-

5

-

0

0

-

ns

0

-

5

0

-

5

0

-

5

.<.0>:"

-

........

45

-

50

-

60

-

70

-

85

-

100

ns

50

-

60

-

70

100

75

65

10

-

ns

65

-

85

55

5

-

-

15

-

40

t RC

Read Cycle Time

40

-

tAA

Address Access Time

-

40

t ACS

Chip Select Access Time

-

40

5

-

-

25

t CLZ1.2(1) Chip Select to Output in Low Z

4Ei...
"':~::::::::::

.....

\5 .•\ • •••••·•· ·

tOE
t OLZ (l)

Output Enable to Output Valid
Output Enable to Output in Low Z

5

t CHZ (l)

Chip Select to Output in High Z

t OHZ (l)

Output Disable to Output in High Z

-

20

tOH

Output Hold from Address Change

3

-. ·is

20

t pU (l)

Chip Select to Power Up Time

0

tpd 1)

Chip Deselect to Power Down Time

-

..

40

'Pi

35

ns

WRITE CYCLE
twe

Write Cycle Time

40

:8

45

tew

Chip Selection to End of Write

35

.:::.::-:.;~:::.

40

tAW

Address Valid to End of Write

35

t AS

Address Set-up Time

5

- Ao
is

.;::::::::::.::~::::

twp

Write Pulse Width

30 (::. ....

tWR

Write Recovery Time

5

t WHZ (l)

Write Enable to Output in High Z

tDw

Data to Write Time Overlap

tDH

Data Hold from Write Time

~:\

tow (1)

Output Active from End of Write

5«/2

•••• 35

::H\ i:
.::'.....:\ ,".
...... ...... .'..

.....

-

75

-

70

5

10

-

30

-

35

55
5

-

5

40

-

50

-

5

-

60

5

-

20

-

25

45
5

20

-

-

-

45

20

25

5

-

5

-

5

5

-

5

-

5

NOTE:
1. This parameter guaranteed but not tested.

13-95

35

30

-

5
5

5

-

5
5

90
90
5
80

40

-

ns
ns
ns
ns
ns
ns
ns

5

-

ns

5

-

ns

IDT8M624S/IDT8M612S 1024K (64K x 16-BIT) &
512K (32Kx 16-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

~----------------tRC---------------~

ADDRESS

1...._ - - - - - - - - - t Acs -------4---.-!

1..-------- tCLZ (5) -------~
DATAOUT

TIMING WAVEFORM OF READ CYCLE NO.

ADDRESS

={
~

DATAOUT

2(1,2,4)

t RC

.1

tAA

.. I

tOH

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

Et~

DATA VALID

3(1,3,4)

UB, LB&CS

DATAOUT

NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = ~L and UB, LB = V1L for 16 output active.
3. Address valid prior to or coincident with CS transition low.
4. OE = V1L
5. Transition is measured ±2oomV from steady state. This parameter is sampled and not 100% tested.

13-96

IDT8M624S/IDT8M612S 1024K (64K x 16-BIT) &
512K (32K x 16-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS

~

--./

~

<

)K:

)'

,

tAW

~V
t

- tAS

(7)

tWR

Wp

""',,-t
tOHZ

I-

~"

f4---

(6)-

OHZ

(6)-

(6)

r--

tOW-j

(4)

DATA OUT

t

WHZ

(4)

____________~~-----~~L------tow_

tOH

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 2, 3, 5)

twc
ADDRESS

~K

)(
tAW

,~
~tAS

/~
tWR

tcw

tow

-'
1'-

+-

tOH

'II

NOTES:
1. ~ or CS' must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS' and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input Signals must not be applied.
5. If the CS' low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a WE controlled write cycle, write pulse (twp) > tWHZ + tow) to allow the I/O drivers to tum off and data to be placed on the bus for the required tow. If
DE is high during a ~ controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wP '

13-97

IDT8M624S/IDT8M612S 1024K (64K x 16-BIT) &
512K (32K x 16-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE

CAPACITANCE(TA = +25°C, f = 1.0MHz)

CS UB LB

MODE

OE WE

OUTPUT

SYMBOL

POWER

PARAMETER(1)

Standby

H

X

X

X

X

High'Z

Standby

CIN

Input Capacitance

Standby

L

H

H

X

X

HighZ

Standby

COUT

Output Capacitance

Read

L

L

L

L

H

Active

Lower Byte Read

L

H

L

L

H

Upper Byte Read

L

L

H

L

H

o OUT 1-16
o OUT 1-8
o OUT 9-16

Read

L

L

L

H

H

HighZ

Active

Lower Byte Read

L

H

L

H

H

HighZ

Active (X8)

Upper Byte Read

L

L

H

H

H

HighZ

Active (X8)

Write

L

L

L

X

L

DIN 1-16

Active

Lower Byte Write

L

H

L

X

L

DIN 1-8

Active (X8)

Upper Byte Write

L

L

H

X

L

DIN 9-16

Active (X8)

CONDITIONS

TYP.

UNIT

VIN= OV

35

pF

VOUT= OV

40

pF

NOTE:
1. This parameter Is sampled and not 100% tested.

Active (X8)
Active (X8)

ORDERING INFORMATION
lOT

XXXX

A

Device Type Power

A

A

Package

Process/
Temperature

RMy:'Mk

~---------------------~ C
40
45
50

Commercial (O°C to

Sidebraze DIP
Commercial onlY)
Commercial Only
Commercial Only

~---------------------------------~ 00

70
85
100

~------------------------------------------~ S
~

___________________________________________________~ 8M624
8M612

13-98

+ 70°C)

Military (55°C to + 125°C)
Semiconductor Components Compliant to
the latest revision of MIL-STO-883, Class B

Speed in Nanoseconds
Military Only
Military Only
Standard Power
64Kx 16-Bit
32Kx 16-Bit

FEATURES:

DESCRIPTION:

• High-density 256K1128K-bit CMOS static RAM modules
• 16K x 16 organization (IDT8M656) with 8K x 16 option
(IDT8M628)

The IDT8M656S/IDT8M628S are 256K1128K-bit high-speed
CMOS static RAMs constructed on a multi-layered ceramic substrate using four IDT7164 8K x 8 static RAMs (IDT8M656S) or two
IDT7164 static RAMs (IDT8M628S) in lead less chip carriers.
Functional equivalence to proposed monolithic static RAMs is
achieved by utilization of an on-board decoder that interprets the
higher order address A13 to select one of the two 8K x 16 RAMs as
the by-16 output and using LB and UB as two extra chip select
functions for lower byte (1/01-8) and upper byte (1/09-16) control,
respectively. (On the IDT8M628S 8K x 16 option, A13 needs to be
externally grounded for proper operation.) Extremely high speeds
are achievable by the use of IDT7164s fabricated in IDT's highperformance, high-reliability CEMOS technology. This state-ofthe-art technology, combined with innovative circuit design techniques, provides the fastest 256K1128K static RAMs available.
The IDT8M656S/IDT8M628S are available with access times as
fast as 40ns over the commercial temperature range, with maximum operating power consumption of only 1.98W (IDT8M656S
16K x 16 option). The module also offers a full standby mode of
440mW (max.).
The IDT8M656S/IDT8M628S are offered in a high-density
40-pin, 600 mil center sidebraze DIP to take full advantage of the
compact IDT7164s in leadless Chip carriers.
All inputs and outputs of the IDT8M656S/IDT8M628S are TTLcompatible and operate from a single 5V supply. (NOTE: Both VCC
pins need to be connected to the 5V supply and both GND pins
need to be grounded for proper operation.) Fully asynchronous
circuitry is used, requiring no clocks or refreshing for operation,
and providing equal access and cycle times for ease of use.
AIiIDT military module semiconductor components are manufactured in compliance with the latest revision of MIL-STD-883,
Class B, making them ideally suited to applications demanding the
highest level of performance and reliability.

• Upper byte (1/09-16) and lower byte (1101-8) separated control
- Flexibility in application
• Equivalent to JEDEC standard for future monolithic
16K x 16/8K x 16 static RAMs
• High-speed
- Military: 50ns (max.)
- Commercial: 40ns (max.)
• Low power consumption: typically less than 825mW
operating (IDT8M656), less than 40mW in standby
• Utilizes IDT7164s-high-performance 64K static RAMs
produced with advanced CEMOS TM technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder
reflow process
• Offered in the JEDEC standard 40-pin, 600 mil wide ceramic
sidebraze DIP
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Modules available with semiconductor components
compliant to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold temperatures for all AC and DC parameters

FUNCTIONAL BLOCK DIAGRAM
Ao-12

1/0 1_8
1/09-16
WE

-

'-----

HI 1/2
FCT139 ~
DECODER :::

IDT7164
8Kx8
CMOS
STATIC
RAM
()

IDT7164
8Kx8
CMOS
STATIC
RAM
~

.......
'--

IDT7164
8Kx8
CMOS
STATIC
RAM

IDT7164
8Kx8
CMOS
STATIC
RAM
()

)

y
~ 1/2 FCT139

r:-

DECODER :::

y
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Inlegraled DevI.C8 Technology. Inc.

DECEMBER 1987
DSC-7018/-

13-99

IDTSM656S/IDTSM62SS CMOS STATIC RAM
MODULE 256K (16K x 16-BIT) & 12SK (SK x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN NAMES

PIN CONFIGURATION
Vee(l)
WE
UB
LB
NC
A 13 (2)
A12

All

A10
Ag

GND(l)
As

A4
A3
Al

Ao

1. For module dimensions, please refer to module drawing M3 in the
packaging section.

VTERM

COMMERCIAL
-0.5 to +7.0

Power

WE

Write Enable

OE

Output Enable

GND

Ground

UB

Upper Byte Control

LB

Lower Byte Control

MIN.

TYP.

MAX.

UNIT

Vee

Supply Voltage

PARAMETER

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H

Input High Voltage

2.2

6.0

V

V1L

Input Low Voltage

-0.5(1)

-

0.8

V

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

ABSOLUTE MAXIMUM RATINGS (1)
RATING

Chip Select

SYMBOL

DIP
TOP VIEW

Terminal Voltage
with Respect to
GND

CS
Vcc

RECOMMENDED DC OPERATING CONDITIONS

A2

SYMBOL

Addresses
Data InpuVOutput

NOTES:
1. Both Vec pins need to be connected to the 5V supply and both GND
pins need to be grounded for proper operation.
2. On IDT8M628S, 128K (8Kx 16-Bit) option, A 13 (pin 35) is required external grounding for proper operation.

A7
A6
A5

a..;;;.;..._ _ _ _ _ _r-

Ao-13

1/01-16

MILITARY
-0.5 to +7.0

UNIT
V

TA

Operating
Temperature

Oto +70

-55 to +0125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTa

Storage
Temperature

-55 to +125

-65 to +150

°C

lOUT

DC Output Current

50

50

mA

AMBIENT
TEMPERATURE

GND

Military

-55°C to 125°C

OV

5.0V

± 10%

Commercial

O°Cto +70°C

OV

5.0V

±

GRADE

NOTE.
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

13-100

Vee

10%

IDTSM656S/IDTSM62SS CMOS STATIC RAM
MODULE 256K (16Kx 16-BIT) & 12SK (SKx 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

-

Vee - 50V +10% Vee (Min ) - 45V Vee (Max) -- 55V VLC = 02VVHC =Vee -- - 02V
SYMBOL

PARAMETER

TEST CONDITIONS

"'N = GND tOVce

IDTSM656S
IDTSM62SS
MIN. TYP.!1) MAX. MIN. TYP,<1) MAX.

UNIT

-

-

15

-

-

15

J1A

-

15

-

-

15

J1A

Operating Current In X16 Mode

CS, OS & [§ =
Vee = Max., Output Open
f = fMAX

-

165

360

-

160

320

mA

ICCX6

Operating Current In X8 Mode

CS ="'L ,US or LS =ML
Vee= Max., Output Open
f = ft.1AX

-

100

220

-

82

180

mA

ISB&
ISBI

Standby Power Supply Current

-

8

SO (2)

-

4

40(2)

-

0.4

V

-

V

Ilu l

Input Leakage Current

Vee = Max.;

IILol

Output Leakage Current

Vee = Max.
CS = V1H , VOUT = GND to Vee

leex16

VOL
VOH

"'L

f§ ~ "'H or
US ~ "'H and [§ ~ "'H
Vee = Max.
Output Open

Output Low Voltage

10L = SmA, Vee = Min.

-

Output High Voltage

10H = -4mA, Vee = Min.

2.4

-

0.4

-

-

2.4

rnA

NOTE:
1.Vee = 5V, TA =+25°C
2. ISB and ISBI of IDTSM656S/IDTSM628S at commercial temperature = 6OmA/30mA.

13-101

- - - - - - - - - - - - - _ ..__._.._ _
...

..

IDTSM656S/IDTSM62SS CMOS STATIC RAM
MODULE 256K (16K x 16-BIT) & 12SK (SK x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

DATA OUT

~

2550

5V

4800
DATA OUT

~

255Q

30pF

Figure 1. Output Load

4800
5pF*

Figure 2. Output load
(for t eLZ1.2' t OLZ ' tCHZ1.2 •t OHZ •
tOW.tWHZ)

*Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(Vce= 5V±10%.TA= O°Cto +70°C)
IDTSM656S40
IDTSM628S40
MIN.
MAX

IDTSM656S50
IDT8M628S50
MIN.
MAX

IDTSM656S70
IDT8M628S70
MIN.
MAX.

IDTSM628S85
IDTSM656S85
MIN.
MAX.

UNIT

t Ac

Read Cycle Time

40

-

50

-

70

-

85

-

ns

tAA
t Acs

Address Access Time

-

40

-

50

-

70

-

85

ns

Chip Select Access Time

-

40

-

50

-

70

-

85

ns

t eLZ1 .2(1)

Chip Select to Output in low Z

5

-

5

-

5

-

5

-

ns

tOE

Output Enable to Output Valid

-

25

-

30

-

40

-

50

ns

tOLZ
t
(l)
CHZ
t OHZ(l)

Output Enable to Output in low Z

5

-

5

-

5

-

5

-

ns

Chip Select to Output in High Z

15

-

20

ns

-

20

-

35

15

-

30

Output Disable to Output in High Z

-

35

ns

tOH

Output Hold from Address Change

5

5

-

ns

0

0

0

-

5

Chip Select to Power Up Time

-

5

t pJl)

-

0

-

ns

t poll)

Chip Deselect to Power Down Time

-

40

-

50

-

70

-

85

ns

-

50

-

70

-

ns

75

-

ns

45

-

65

-

85

45

ns

5

-

10

-

10

40

-

55

-

65

5

-

5

-

10

-

30

twc

Write Cycle Time

40

tew

Chip Selection to End of Write

35

tAW

Address Valid to End of Write

35

t AS

Address Set-up Time

5

twp

Write Pulse Width

30

tWA
t WHZ (1)

Write Recovery Time

5

-

Write Enable to Output in High Z

-

15

-

20

-

30

-

35

ns

tow

Data to Write Time Overlap

15

-

ns

5

tow (1)

Output Active from End of Write

5

-

35

5

-

30

Data Hold from Write Time

-

20

tOH

5

-

ns

NOTE:
1. This parameter guaranteed but not tested.

13-102

5
5

65

5
5

75

ns
ns
ns

ns

IDT8M656S/IDT8M628S CMOS STATIC RAM
MODULE 256K (16K X 16-BI1) & 128K (8K X 16-BI1)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(Vee= 5V ±10%, TA= -55°C to +125°C)

IDT8M656SSO
IDT8M628S50
MIN.
MAX.

PARAMETER

IDTBM656S60
IDT8M628S60
MAX
MIN.

IDT8M656S70
IDT8M628S70
MIN.
MAX.

IDT8M656S85
IDT8M628S85
MIN.
MAX.

UNIT

READ CYCLE
tAO

Read Cyole Time

50

-

60

-

70

-

85

-

ns

tAA

Address Access Time

50

ns

60

70

-

85

50

-

70

Chip Select Access Time

-

60

tAOS

-

85

ns

5

-

5

-

5

-

5

-

ns
ns

t o[21.2(1) Chip Select to Output in Low Z
tOE
t o[2(I)

Output Enable to Output Valid

-

30

-

35

-

40

-

50

Output Enable to Output in Low Z

5

-

5

-

5

-

5

-

ns

t

Chip Select to Output in High Z

20

25

-

30

-

35

ns

30

-

35

ns

5

-

5

ns

0

-

0

-

-

85

ns

ns

10

-

t OHZ (I)

Output Disable to Output in High Z

-

20

-

tOH
t pu (1)

Output Hold from Address Change

5

-

5

Chip Select to Power Up Time

0

-

0

-

t po (1)

Chip Deselect to Power Down Time

-

50

-

60

-

70

60

-

70

-

85

65

-

75

65

45

-

5

-

5

-

OHZ

(I)

25

ns

WRITE CYCLE
two

Write Cycle Time

50

tow

Chip Selection to End of Write

45

tAW

Address Valid to End of Write

45

t As

Address Set-up Time

5

twp

Write Pulse Width

40

tWA
t WHZ (I)

Write Recovery Time

5

-

Write Enable to Output in High Z

-

20

-

20

-

25

-

30

ns

tow

Data to Write Time Overlap

20

25

-

30

5

5

-

5

Output Active from End of Write

5

5

-

5

-

ns

Data Hold from Write Time

-

35

tOH
t ow (l)

-

55
55
10

10
55

NOTE:
1. This parameter guaranteed but not tested.

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

~------------------tAC----------------~
ADDRESS

UB, LB&CS

DATAOUT

13-103

75
10
65

5
5

ns
ns
ns
ns
ns

ns
ns

IDT8M656S/IDT8M628S CMOS STATIC RAM
MODULE 256K (16K X 16-BIT) & 128K (8K X 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.

~

ADDRESS

DATAoUT

2(1,2,4)

t RC

.1

tM

.. '

tOH

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

DATA VALID

3(1,3,4)

UB, LB &CS

DATA OUT
NOTES:

1.
2.
3.
4.
5.

WE Is High for Read Cycle.
Device is continuously selected, CS = \iL and UB, LB = V1L for 16 output active.
Address valid prior to or coincident with CS transition low.
OE = V1L
Transition Is measured ± 200mV from steady state. This parameter is sampled and not 100% tested.

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
twc
ADDRESS

~
~

)(

K

/'
tAW
~

...IV'

~
t wp(7)

I---tAS
-..-.~

f4--tOHZ
DATA OUT

tWA
~~

It---

t

OHZ

(6)_

tWHl)-

(6)

I'--- tow
(4)

(4)

____________~~----~~~L---------_
tow _____

13-104

tOH

IDTSM656S/IDTSM62SS CMOS STATIC RAM
MODULE 256K (16Kx 16-BIT) & 12SK (SKx 16-BIT)

TIMING WAVEFORM OF WRITE CYCLE NO.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

2 ~ CONTROLLED TIMING)(1, 2,3, 5)

twc
ADDRESS

~

-./

)(

K.
tAW

/'

'I\..
!4"--tAS

-

tWR

tcw

tow

,

tOH
'-!

I'-!

'1

NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low cg and a low WE.
3. tWR is measured from the earlier of cg or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition Is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
7. During a WE controlled write cycle, write pulse (twP) > tWHZ + tow) to allow the I/O drivers to tum off and data to be placed on the bus for the required tow. If
DE' is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp •

TRUTH TABLE

CAPACITANCE(TA= +25°C, f = 1.0MHz)
PARAMETER (1)

TYP.

UNIT

Standby

H

X

X

X

X

High Z

Standby

CIN

Input CapaCitance

VIN = OV

35

pF

Standby

L

H

H

X

X

HighZ

Standby

COUT

Output Capacitance

VOUT= OV

40

pF

Read

L

L

L

L

H

DATA OUT 1-16

Active

Lower Byte Read

L

H

L

L

H

DATA OUT 1-8

Active (X8)

Upper Byte Read

L

L

H

L

H

DATA oUT 9-16

Active (X8)
Active

MODE

CS UB LB

OE WE

OUTPUT

POWER

Read

L

L

L

H

H

HighZ

Lower Byte Read

L

H

L

H

H

HighZ

Active (X8)

Upper Byte Read

L

L

H

H

H

HighZ

Active (X8)

Write

L

L

L

X

L

DATA IN 1-16

Active

Lower Byte Write

L

H

L

X

L

DATA IN 1-8

Active (X8)

Upper Byte Write

L

L

H

X

L

DATAIN9_16

Active (X8)

13-105

SYMBOL

CONDITIONS

NOTE:
1. This parameter is sampled and not 100% tested.

IDT8M656S/IDT8M628S CMOS STATIC RAM
MODULE 256K (16K x 16-BIT) & 128K (SK x 16-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XXX><

. A

Device Type Power

A

A

Package

Process/
Temperature
Range

Y:LANK

Commercial (O°C to

+ 70°C)

Military (-55°C to + 125°C)
Compliant to MIL-STO-883, Class B

Sidebraze DIP

40

50
~------------------------------~ 00
70

} Speed In

N"""'ooonds

85

~------------------------~IS

I

8M656
8M628

13-106
--

-

-------------

Standard Power

16K x 16 - Bit
8K x 16 - Bit

FEATURES: '
• High-density 1024K (128K x 8) CMOS static RAM module
• Equivalent to JEDEC standard for future monolithic 128K x 8
static RAMs
• High-speed
- Military: 60ns (max.)
- Commercial: 40ns (max.)
• Low power consumption
- Active: less than 550mW (typ.)
- Standby: less than 20mW'(typ.)
• CEMOS TM process virtually eliminates alpha particle soft
error rates (with no organic die coating)
• Assembled with lOT's high-reliability vapor phase solder
reflow process
• Offered in the JEDEC standard 32-pin, 600 mil wide ceramic'
sidebraze DIP
• Single 5V (±10%) power supply
• Inputs and outputs directly TT:L-compatible
• Modules available with semiconductor components compliant to MIL-STD-883, Class B
• Finished modules tested at Room, Hot and Cold temperatures for all AC and DC parameters

PIN CONFIGURATION
NC
Ale
A14

A7
Ae
A5

As
Ag

A4
A3

AI,
OE

A2

AlO

Ao

1/08

A,

The IDT8M824S is a1024K (131,072 x a-bit) high-speed static
RAM constructed on a co-fired ceramic substrate using four
IDT71256 32K x a static RAMs In leadless chip carriers. Functional
equivalence to proposed monolithic one megabit static RAMs is
achieved by utilization of an on-board decoder that interprets the
higher order address A15 and Ale to select one of the four 32K x 8
RAMs. Extremely fast speeds can be achieved with this technique
due to use of 256K static RAMs and the decoder fabricated in lOT's
high-performance, high-reliability CEMOS technology.
The IDT8M824S is available with maximum access times as fast
as 40ns for commercial temperature range, with maximum power
consumption of 1.2 watts. The module offers a full standby mode of
440mW (max.).
The IDT8M824S is offered in a 32-pin, 600 mil centersidebraze
DIP, adhering to JEDEC standards for one megabit monolithic
pinouts, allowing for compatibility with future monolithics.
All inputs and outputs of the IDT8M824S are TTL-compatible
and operate from a single 5V supply. Fully asynchronous circuitry
is used, requiring no clocks or refreshing for operation, and providing equal access and cycle times for ease of use.
, All lOT military module semiconductor components are manufactured in compliance to the latest revision of MIL-STD-883, Class
B, making them ideally suited to applications demanding the highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM
Vee
A15
NC
WE
A13

A12

DESCRIPTION:

A0-14
1/0,-8

WE

-

DE

-

-

CS

110,

1/07

1/°2

I/0e
1/05
1/04

1/03
GND

-

I'-'

IDT71256
32Kx8
CMOS
STATIC
RAM

~?

~.~

-

-

L....-

IDT71256
32Kx8
CMOS
STATIC
RAM

IDT71256
32Kx8
CMOS
STATIC
RAM

cg (,)

~.\

IDTFCT139 I'-'
DECODER ~
I'-'

--C

DIP
TOP VIEW

L-...

IDT71256
32Kx8
CMOS
STATIC
RAM

I'-'

1. For module dimensions, please refer to module
drawing M2 in the packaging section.

PIN NAMES
AO-le

Addresses

WE

1/00-8

Data Input/Output

OE

Write Enable
Output Enable

CS
Vee

Chip Select

GND

Ground

Power

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCiAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER'1987
·PSC-70191-

IDT8M824S 1 MEGABIT
(128Kx 8-BIT) CMOS STATIC RAM MODULE

. MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM· RATINGS (1)
COMMERCIAL

SYMBOL
MILITARY

UNIT

SYMBOL

RATING

VTERM ·

Tenninal Voltage .
with Respect to
GND

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TeJAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTa

Storage
Temperature

-55 to +125

-65 to +150

°C

-0.5 to +7.0 . -0.5 to +7.0

DC Output Current

V

PARAMETER

TYP.

MAX.

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H

Input High Voltage

2.2

V

Input Low Voltage

-0.5(1)

-

6.0

V1L

0.8

V

NOTE:
1. V1L (min.) = -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLYVOLTAGE

50

50
mA
10llT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause·pennanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those Indicated In the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

GRADE
Military
Commercial

AMBIENT
TEMPERATURE

GND

-55°C to +125°C

OV

5.0V ±10%

O°Cto +70°C

OV

5.0V ±10%

Vee

DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V +10%, Vee (Min.) = 4.5V Vee (Max.) = 55V
SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

IDT8MS24S
TYP.(l)
MAX.

UNIT

-

-

15

IJ.A

15

IJ.A

Operating Power Supply Current

CS ="'IL
Vee = Max., Output Open
f = 0

-

60

160

mA

ICC2

Dynamic Operating Current

CS="'IL
Vee = Max., Output Open
f = fMAX

-

110

210

mA

158&
1581

Standby Power Supply Current

CS ~"'IH .
Vee = Max.
Output Open

4

SO(2)

rnA

-

0.4

V

-

V

lIu l

Input Leakage Current

Vee = Max.: V1N = GND to Vee

Output Leakage Current

Vee = Max.
CS = "'IH , VOllT = GND to Vee

ICCI

IlLOI

UNIT

MIN.

Vee

VOL

Output Low Voltage

10L = SmA, Vcc = Min.

-

VOH

Output High Voltage

10H = -4mA, Vcc= Min.

2.4

NOTES:
1.Vee = 5V,TA= +25°C
2. Ise and 1581 of IDT8M824S at commercial temperature = 6OmA.

13-108

-

IDT8MS24S 1 MEGABIT
(12SK x S-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V

5V

GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATA OUT

~

2550

4800
DATA OUT
30pF

~

2550.

Figure 1. Output Load

4800
5pF*

Figure 2. Output Load
(for t cLZ1 .2 •t OLZ •tCHZ1.2 .t OHZ '
tOW.tWHz)

*Including scope and jig.

AC ELECTRICAL CHARACTERISTICS

(Vee= 5V ±10%.1A= O°Cto +70°Cand-55°Cto +125°C)

8MS24S40
PARAMETERS

SYMBOL

SMS24S45

8M824S50 8MS24S60 8M824S70

(COM'L. ONLy) (COM'L. ONLy) (COM'L. ONLy)

8M824SS5 8MS24S100
(MIL. ONLy)

(MIL. ONLy)

UNIT

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE
t RC

Read Cycle Time

40

tAA
t ACS

Address Access Time

-

t cLZ1 .2(1)

Chip Select to Output in Low Z

5

{{::::::::t::::::::

5

tOE
t
(l)
oLZ
t
(l)
CHZ
t
(l)
OHZ

Output Enable to Output Valid

-

{::::::::::~if:::;

-

Output Enable to Output in Low Z

5 :::::::::::::::::4(::'

5

Chip Select Access Time

Chip Select to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change

tOH
t pU (l)

Chip Select to Power Up Time

t pO (l)

Chip Deselect to Power Down Time

;:::::::::;;::4l:f':::

-

50

45
;: :··.·..40

·····:·::::~(f,:,

~~

-

-

60

70

85

100

ns

45

50

60

70

85

100

ns

45

50

60

70

85

100

ns

5
25

5
30

5

5
35

5

5

5

50

40
5

ns

60
5

5

ns
ns

20

20

25

30

35

40

ns

20

20

25

30

35

40

ns

5

5

5

5

5

5

0

0

0

0

0

0

0

- ;::,::/::t:::49:::

-

50

45

60

85

70

ns
ns
100

ns

::m}}::::::,:,:,:::::,

WRITE CYCLE
twc

Write Cycle Time

4Q;l:t:}}%:::

45

50

60

70

85

100

ns

tcw

Chip Selection to End of Write

35

40

45

55

65

75

90

ns

tAW

Address Valid to End of Write

3$::::: ::;:;:;:;:;::i

40

45

55

65

75

90

ns

t AS

Address Set-up Time

5::::::::):::::::::::1::

5

5

5

5

5

5

ns

twp

Write Pulse Width

35

40

50

60

70

80

ns

tWR
t WHZ (l)

Write Recovery Time

S:::::;:::{{:tf!

5

5

5

5

10

10

Write Enable to Output in High Z

+:::::::::im: .. 15

tow

Data to Write Time Overlap

1"5':':':':

tOH

Data Hold from Write Time

t ow (l)

Output Active from End of Write

39":

*"::

:::::"':'::*-

;.;.;::::::;::

15

20

35

30

25

ns
40

ns

20

20

25

30

35

40

ns

3

5

5

5

5

5

5

ns

5

5

5

5

5

5

5

ns

NOTE:
1. This parameter guaranteed but not tested.

13-109

ID

IDT8M824S 1 MEGABIT
(128K x 8-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

~-----------------------------tRC----------------------------~

ADDRESS

14------------------ tAA -------t

1••~-----tA~---------4-~~
1••1 - - - - - - - - - - tCLZ (5) _ _ _-..1
DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)

ADDRESS

=1
...

DATAoUT

t RC

.1

tOH

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.

E.oo

.1

tAA

DATA VALID

3(1,3,4)

DATA our

NOTES:

1. WE Is High for Read Cycle.
_
2. Device Is continuously selected, CS = V IL •
3. Address valid prior to or coincident with CS transition low.
4. OE = V1L
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

13-110

IDT8M824S 1 MEGABIT
(128Kx8-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)

ADDRESS

--~------ t wp(7)

------.1

----+---------~I

tWR

~--------~-------------

DATA OUT

______________________________

~~-t-ow--------tO-H,>~r:_--.----------------__

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)

two
ADDRESS

~

--.-/

~K

K
tAW

",,I---tAS

~V
tWR

tow

tow

",

I'

I--

tOH

"II

NOTES:
1. WE" or ~ must be high during all address transitions.
2. A write occurs during the overlap (twR of a low ~ and a low WE".
3. tWR is measured from the earlier of ~ or WE" going high to the end of write cycle.
4. During this period, I/O pins are In the output state, and input signals must not be applied.
5. If the ~ low transition occurs simultaneously with or after the WE" low transition, the outputs remain in a high impedance state.
6. Transition is measured ±2OOmV from steady state with a 5pF load Oncluding scope and jig). This parameter is sampled and not 100% tested.
7. During a WE" controlled write cycle, write pulse (lwP) > tWHZ + tow) to allow the I/O drivers to tum off and data to be placed on the bus for the required tow. If
'OE' is high during a WE" controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp .

13-111

IDT8M824S 1 MEGABIT
(128K x 8-BIT) CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE
MODE

CAPACITANCE
SYMBOL

(TA= +25°C f = 10MHz)

PARAMETER

(1)

CS

OE

WE

OUTPUT

POWER

Standby

H

X

X

HighZ

Standby

CIN

Input Capacitance

Read

L

L

H

DoUT

Active

COUT

Output Capacitance

Read

L

H

H

HlghZ

Active

Write

L

X

L

DIN

Active

CONDITIONS

TYP.

UNIT

VIN = OV

35

pF

Vour= OV

40

pF

NOTE:
1. This parameter Is sampled and not 100% tested.

ORDERING INFORMATION
lOT

XXX)(

A

Device Type Power

A

A

Package

Process!
Temperature
Range

y:LANK

Commercial (O°C to

C

Sidebraze DIP

40·

Commercial Only
Commercial Only
Commercial Only

45
50
60
70

85
100

Military Only
Military Only

S

Standard Power

1..---------------------1 8M824

13-112

+ 70°C)

Military (-55°C to + 125°C)
Semiconductor Components Compliant to
MIL-STD-883, Class B

}_,nN~

Megabit Static RAM Module

FEATURES:

DESCRIPTION:

• High-density 256K (32K x B-bit) CMOS static RAM module
• Equivalent to JEDEC standard for future monolithic 32K x B
static RAMs

The IDTBMB56 is a 256K (32,76B x B-bit) high-speed static RAM
constructed on a co-fired ceramic substrate using four IDT7164
(B,192 x B) static RAMs in leadless chip carriers. Functional equivalence to proposed monolithic 256K static RAMs is achieved by
utilization of an on-board decoder circuit that interprets the higher
order address A13 and A14 to select one of the four BK x B RAMs.
Extremely fast speeds can be achieved with this technique due to
use of 64K static RAMs and the decoder fabricated in IDT's highperformance, high-reliability CEMOS technology.
The IDTBMB56 is available with maximum access times as fast
as 45ns for commercial and 55ns for military temperature ranges,
with maximum power consumption of only B25mW. The circuit
also offers a substantially low-power standby mode. When CS
goes high, the circuit will automatically go to a standby mode with
power consumption of only 83mW (max.).
The IDTBMB56 is offered in a 2B-pin, 600 mil center sidebraze
DIP. This provides four times the density of the IDT7MB64 (BK x B
module) in the same socket, with only minor pin assignment
changes. In addition, the JEDEC standard for 256K monolithic
pinouts has been adhered to, allowing for compatibility with 256K
monolithics.
All inputs and outputs of the IDTBM856 are TTL-compatible and
operate from a single 5V supply. Fully asynchronous circuitry is
used, requiring no clocks or refreshing for operation, and providing
equal access and cycle times for ease of use .
. All IDT military module semiconductor components are manufactured in compliance with the latest revision of MIL-STD-B83,
Class 8, making them ideally suited to applications demanding the
highest level of performance and reliability.

• . High-speed-45ns (max.) commercial; 55ns (max.) military
• Low power consumption; typically less than 225mW operating,
less than 500}JW in full standby
• Utilizes IDT7164s-high-performance 64K static RAMs
produced with advanced CEMOS TM technology
• CEMOS process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Assembled with IDT's high-reliability vapor phase solder reflow
process
• Pin-compatible with IDT7MB64 (BK x B SRAM module)
• Offered in the JEDEC standard 2B-pin, 600 mil wide ceramic
sidebraze DIP
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL~ompatible
• Modules available with semiconductor components compliant
to MIL-STD-883, Class 8
• Finished modules tested at Room, Hot and Cold temperatures
for all AC and DC parameters

PIN CONFIGURATION
2S

vee

27

WE'

FUNCTIONAL BLOCK DIAGRAM

A13
As
Ag
All

~

ID17164
8Kx8
CMOS
r - - - - .... STATIC
RAM
ID17164
' - - - 8Kx8
CSl~;J
CMOS
~ STATIC
RAM

-

DE'
Al

-

9

-

~

1/0 1
1/02
1/03
GND ---.
14 _ _ _ _..-rDIP
TOP VIEW

-

h.

-

~

-

'--

~

-

~

ID17164
8Kx8
CMOS
STATIC
RAM

ID17164
8Kx8
CMOS
STATIC
RAM

=:-tr

CS 1

CS/

h.

DECODER
r-'

-C

r-'

PIN NAMES

CS

Addresses
Data Input/Output
Chip Select

Vee

Power

Ao- A14
I/Ol-I/OS

NOTE:

* For module dimensions, please refer to module
drawing M1 in the packaging section.
CEMOS Is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Inlegrated DevIce Technology. Inc.

WE

OE

Write Enable
Output Enable

GND

Ground

DECEMBER 1987
DSC-7020/-

13-113

IDT8M856L 256K (32K x S-BIT)
CMOS STATIC RAM MODULE (loW-Power Veralon)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM

RATING
Tennlnal Voltage
with Respect to
GND

COMMERCIAL
-0.5 to +7.0

RECOMMENDED OPERATING CONDITIONS
MILITARY

Oto +70

TBIAS

Temperature
Under Bias

-55 to +125

TSTo

Storage
Temperature

-55 to +125. -65 to +150

MAX.

Supply VQltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0,

V

2.2

-

6.0

V

0.8

V

. V,H

DC

-55 to +125

TYP.,

Vee

SYMBOL

V

-0.5 to +7.0

Operating
Temperature

TA

UNIT

V,l

DC Output Current

DC

-65 to +135

50

50

PARAMETER

Input High Voltage
Input Low Voltage '

MIN.

-0.5(1)

UNIT

NOTE:
1. V,l (min.) = -3.0V for pulse width less than 2Ons.

DC
mA

lour
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause pennanent damage to the device. This Is a stress ratIng only and functional operation of the device at these or any other
conditions above those Indicated In the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

(Vee = 5.OV ±10%. TA = -55 DC to + 125DC and ODC to + 70 DC)

DC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

TEST CONDITIONS

= OV to Vee

Ilul

Input leakage Current

Vee

Illol

Output Leakage Current

Iccl

Operating Power Supply Current

Vee = 5.5V. CS = V,H • Vour == OV to Vee
Vee = 5.5V. CS = V,l• Output Open. f = 0

1cc2

Dynamic Operating Current

Vee = 5.5V. CS =

ISB

Standby Power Supply CUrrent

CS 2: V,H (TTL Level). Vee = 5.5V. Output Open

ISBl

Full Starldby Power Supply Current

VOL

Output Low Voltage

VOH

Output High Voltage

= 5.5V. Y,N

V,l • Output Open. f = fMAX

Vcc - 0.2V (CMOS Level)
Y'N 2: Vcc - 0.2V or ~ 0.2V
10l = 10mA. Vee = 4.5V
10l = 8mA. Vee = 4.5V
IOH = -4mA. Vee = 4.5V
~ 2:

NOTE:
1. Vee = 5V. TA = +25 DC

13-114

MIN.

TYP.(l)

COM'L
MAX.

MIL
MAX.

UNIT

-

-

5

10

~

5

10

~

-

45

90

100

mA

70

140

150

mA

-

2.5

15

20

mA

-

0.1

1

4.5

mA

-

0.5
0.4

0.5
0.4

V

-

-

V

2.4

\\
IDT8M856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (Low-Power Version)

DATA RETENTION CHARACTERISTICS
SYMBOL
VDR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(TA = -55°C to + 125°C and O°C to + 70°C)
TEST CONDITIONS

PARAMETER

MIN.

TYP.(1)

2.0

-

-

Vcc for Retention Data

-

ICCDR

Data Retention Current

tCDR

Chip Deselect to Data Retention Time

tR

Operation Recovery Time

CS ~ Vcc -0.2V

-

-

\1N

0

-

~ Vee -O.2V or ~ O.2V

tRC(4)

COM'L
MAX.

1000(2)
1500(3)

-

-

NOTES:
1. TA = +25°C
2. @Vcc = 2V
3. @Vcc = 3V
4. tRC = Read Cycle Time

LOWVCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VDR ~ 2V

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to3.0V
5ns
1.5V
1.5V
See Figures 1 and 2

5V

5V

DATA OUT

~

255i1

Figure

48o.n

DATA OUT

~

255!l

30pF*

1. Output Load

48on
5pF*

Figure 2. Output Load
(for tHZ.tLZ.twz. and tow)

* Including scope and jig.

13-115

MIL
MAX.

4000(2)
6000(3)

-

UNIT
V

J.LA
ns
ns

IDT8M856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (loW-Power Version)

AC ELECTRICAL CHARACTERISTICS
PARAMETER

SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES
(Vee = 5V ±10%. TA = O°C to + 70°C)

IDT8M856L45
MAX.
MIN.

IDT8M856L50
MAX.
MIN.

IDT8M856L60
MIN.
MAX.

IDT8M856L70
MIN.
MAX.

IDT8M856L85
UNIT
MIN.
MAX.

READ CYCLE
t RC

Read Cycle Time

45

-

50

-

60

-

70

-

85

-

ns

tAA

Address Access Time

45

ns

55

65

-

85

50

-

70

45

-

60

Chip Select Access Time

-

50

tAOS

-

85

ns

tCll

Chip Select to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tOE

Output Enable to Output Valid

-

25

-

35

-

40

-

45

-

65

ns

tOll

Output Enable to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tCHZ

Chip Select to Output In High Z

20

-

20

-

20

-

30

ns

Output Disable to Output in High Z

20

-

20

-

20

-

25

tOHZ

-

25

-

30

ns

tOH

Output Hold from Address Change

5

5

0

0

0

-

ns

0

-

5

0

-

5

Chip Select to Power Up Time

-

5

tpu

-

tpo

Chip Deselect to Power Down Time

-

45

-

50

-

60

-

70

-

85

ns

50

60

-

85

-

70

-

ns

60
60

-

70

-

ns

10

-

15

-

50

0

-

0

-

ns

45

0

-

70

0

-

ns

WRITE CYCLE
twc

Write Cycle Time

45

tcw

Chip Select to End of Write

40

tAW

Address Valid to End of Write

40

tAS

Address Set-up Time

5

twp

Write Pulse Width

35

tWA

Write Recovery Time

0

-

tWHZ

Write Enable to Output High Z

-

20

-

20

-

25

-

30

-

40

ns

tow

Data to Write Time Over1ap

20

20

-

25

-

ns

5

5

5

5

Output Active from End of Write

5

5

-

5

-

ns

tow

-

-

40

Data Hold from Write Time

-

30

tOH

-

45
45
5
35

5

13-116

50
50
10
40

5

5

ns

ns
ns

ns

IDTSM856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (loW-Power Version)

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(Vee

= 5V ±10%, TA = -55°C to

IDT8M856L55
MIN.
MAX.

IDT8M856L65
MIN.
MAX.

+125°C)
IDT8M856L75
MAX.
MIN.

IDT8M856L90 IDT8M856L100
UNIT
MIN.
MAX. MIN.
MAX

READ CYCLE
tRC

Read Cycle Time

55

-

65

-

75

-

90

-

100

-

ns

tM

Address Access Time

55

ns

65

80

-

100

55

-

90

55

-

75

Chip Select Access Time

-

65

tAOS

-

90

ns

tCLZ

Chip Select to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tOE

Output Enable to Output Valid

-

40

-

45

-

50

-

60

-

65

ns

toLZ

Output Enable to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tCHZ

Chip Select to Output in High Z

20

-

30

-

35

ns

30

-

35

-

40

Output Disable to Output in High Z

-

25

tOHZ

-

40

ns

tOH

Output Hold from Address Change

5

5

0

0

0

-

ns

0

-

5

0

-

5

Chip Select to Power Up Time

-

5

tpu

-

tpo

Chip Deselect to Power Down Time

-

55

-

65

-

75

-

90

-

100

ns

-

65

75

-

90

-

100

ns

65

75

-

85

65

-

75

-

85

10

-

15

-

15

45

-

50

55

20

25

ns

WRITE CYCLE
twc

Write Cycle Time

55

tcw

Chip Select to End of Write

50

tAW

Address Valid to End of Write

50

t AS

Address Set-up Time

5

twp

Write Pulse Width

40

tWA

Write Recovery Time

0

-

0

-

0

-

0

-

0

-

tWHZ

Write Enable to Output High Z

-

25

-

30

-

40

-

50

-

50

ns

tow

Data to Write Time Overlap

25

30

-

45

5

5

-

5

Output Active from End of Write

5

-

5

5

-

5

-

ns

Data Hold from Write Time

-

45

tow

-

35

tOH

-

55
55
10

45

5

13-117

5
5

ns
ns
ns
ns
ns

ns
ns

IDT8M856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (Low-Power Version)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1 (1)
~-------------tRC------------~
ADDRESS

DATAoUT

TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)

ADDRESS

-----1=-;

-----Jf~~~_~-------~~-tO-H--~-------~-·:I--------------'~-t-OH-,---.--xxxx
1M -----+l11IC
.'

DATAoUT

PREVIOUS DATA VALID

}-

DATA VALID

TIMING WAVEFORM OF READ CYCLE NO.3 (1,3,4)

NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected,
= "'IL.
3. Address valid prior to or coincident with
transition low.
4.
= "'IL
5. Transition is measured ±2oomV from steady state. This parameter is sampled and not 100% tested.

rn

rn:

rn

13-118

IDT8M856L 256K (32K x 8-811)
CMOS STATIC RAM MODULE (Low. Power Version)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (1)
~----------------~twc----------------~

ADDRESS

--------~

\4--------

tAW

,------------

---------------.l

14------lwP (2) -------+/
DATA OUT

r-TIMING WAVEFORM OF WRITE CYCLE NO.2

tow

--._114--

tOH

--I

(1,.)

14-------------------twc-----------------~

ADDRESS

~-----~W------~

14-------------=------------------..-..1
14----twp
tAW

(2), ________~

------~--~~~~~-

I.~~----~-----

DATA OUT

NOTES:
1. WE or ~ must be high during all address transitions.
2. A write occurs during the overlap (tw~ of a low CS'.
3. tWR Is measured from the earlier of CS' or WE going high to the end of the write cycle.
.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
5. If the CS low transition occurs simultaneously
the WE low transitions or after the WE transition, outputs remain in a high impedance state.
6. DE Is continuously low (DE = \'Id.
7. DATAoUT is the same phase of write data of this write cycle.
8. If CS' is low during this period, 110 pins are in the output state. Then the data input signals of opposite phase to the outputs must not be
applied to them.
9. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

with

13-119

IDT8M856L 256K (32K x 8-BIT)
CMOS STATIC RAM MODULE (low-Power Ver~lon)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE
MODE

Address Access Time vs.
CS

OE

WE

Standby

H

X

Read

L

L

OUTPUT

POWER

X

HighZ

Standby

H

DoUT

Active

Read

L

H

H

HighZ

Active

Write

L

X

L

DIN

Active

CAPACITANCE
SYMBOL

Capacitive Load
1.2

T~

(TA= +25°C, f = 1.0MHz)

PARAMETER(1)

CONDITIONS

TYP.

UNIT

CIN

Input Capacitance

'VIN = OV

35

pF

COUT

Output Capacitance

VOUT= OV

26

pF

./

V

NOTE:
1. This parameter is sampled and not 100% tested.

= +25°C

Y

~

/

~

o

50

100

Capacitive Load (pF)

ORDERING INFORMATION
lOT

XXXX
Device Type

A

"POW8r

A

A

Package

Processl
Temperature

~y~k
~--------------~C

Commercial (O°C to + 70°C)
Military (-55°C to + 125°C)
Semiconductor Components Compliant to
MIL-STO-883, Class B
Sidebraze DIP

COM'L

45

50
60
70
85

~----------------------------~

L

~----------------------------------~8M~

13..,120

~

MIL}

Speed In Nanos"""nd.

100

Low Power
32Kx 8-Bit

FEATURES:

outputs of the RAM are connected to the D Inputs of an
IDT49FCT818 in the normal fashion. The device has the serial
data-In and serial data-output bits connected to form a 112-bit Serial Protocol Channel register. The command/data (C/O) and Serial Shift Clock (SCLK) are all bus organized across the fourteen
IDT49FCT818 registers. The 112 register output bits, 8 from each
device, are separately brought out to form a 112-bit wide pipeline
register on the Writable Control Store.
In normal operation, data from the 112-bit wide memory is
loaded into the IDT49FCT818 registers on the low-te-high transition of PCLK. Reading and writing of the memory by means of the
Serial Protocol Channel are performed using the protocol of the
IDT49FCT818. (For details of this operation, please refer to the
IDT49FCT818 data sheet.) The data to be loaded can be shifted in
the serial data input by using the SCLK and a load command executed by shif!!ng the proper command word in the serial data input
when the C/D line is in the command mode. This command will
then be executed by manipulating the C/O line and SCLK line in
the desired fashion. Data is then written into the RAM by bringing
the write enable line on the RAM memory from the high state to the
low state and back to the high state.
The IDl7MBS042 is offered as a compact, cost-effective plastic
quad In-line module and occupies less than 9 square inches of
board space.

• 8K x 112 high-performance Writable Control Store (WCS)
• Serial Protocol Channel (SPC TN ) - reading, writing and
interrogation
• High fanout pipeline register
• Width expandable
• Designed for high-speed writable control store applications
• Assembled with IDT's high-reliability vapor phase solder reflow
process
• Compact quad in-line module
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible

DESCRIPTION:
The IDl7MBS042 is an 8K x 112-bit Writable Control Store
(WCS) RAM and pipeline register. It features fourteen 8K x 8
IDl7164 high-performance static RAMs and fourteen
IDT49FCT818 Serial Protocol Channel (SPC) registers. These devices are arranged to form the 8K x 112 Writable Control Store RAM
with Serial Protocol Channel for loading ofthe memory. Each eight

FUNCTIONAL BLOCK DIAGRAM

ADDRESS
A 12 -A o
13
~

WE
OE

3
2

A

~

8Kx 112 RAM
14 - IDT7164s

WE
OE
I/O

I/O

I/O

I/O

SOl

SOO

C/t5

SOl

SClK

o

SOO
IOT49FCT818

Y

PClK

OE

SOl

o

o

IOT49FCT818

Y

OE

Y95 -Yss

Ylll- Y l04

CEMOS and SPC are trademarks of Integrated Device Technology, Inc.

DECEMBER 1987

COMMERCIAL TEMPERATURE RANGE
©

DSC-7021/-

1987 Integrated DevIce Technology. Inc.

13-121
- - - - - - - - - - ..._ - _ . _ . _ - - - - - - - - - -

IDT7MB6042 SK x 112 WRITABLE
CONTROL STORE STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

PACKAGE OUTLINE
164-PIN DIP

:::::::::::::::::::::T

I·

4.090
4.110

[lUI
y w

·1

DuUliDI
~ 9mmoiF ~DiF EfiowmF

rr:n rr:n rr:n rr:n rr:n rr:n rr:n rr:n rr:n rr:n rr:n rr:n rr:n rr:n

1.990
2.010

n~nnnlfiiiFlll
~~~§~~~~~~

··.......................................
...................................... ...
PIN#l

: : : : : : : : : : : : : : : : : : : :.: : : : : : : : : : : : : : : : : : : : :

··.......................................
...................................... . ..

13-122

1.S90
1.920

~~?

I

*-+l
t
0.016
0.026

FEATURES:

clock enables, as well as address and data inputs, must meet the
appropriate set-up and hold times with respect to the clock.
The eight data output bits are enabled when the output enable is
low and are in the high-impedance state when the output enable is
high. The chip select and write enable signals are also registered in
D flip-flops. These two flip-flops are loaded with new data on each
low-te-high transition of the clock. The chip select is passed directly from the Q output of the D-type flip-flop to the 64K x a RAM.
The write enable signal is gated with the clock signal to generate a
delayed write enable pulse. In essence, this gives the output of the
address register time to settle and internally select the appropriate
byte of RAM before the write enable gooslow to write new data into
the RAM. Thus, the low-te-high transition of the clock causes the
chip select and write enable flip-flops to be loaded with new data
and immediately deselects a previous write by means of the clock
going high. The data lines to the RAM and the address lines to the
RAM may indeed change to new values based on the low-te-high
transition ofthe clock. When the clock goes from high-te-Iow, ifthe
chip select is low and the write enable is low, a write cycle is begun
and the data at the RAM data inputs will be written into the selected
address. If the write enable is high or the chip enable is high, data
will not be written into the memory.
One of the features of this configuration of memory that have
registers on all of the address lines, data input lines and data output
lines as well as the control lines, is to provide the highest possible
clock rate in the system. All that is necessary is that the data, address, chip select, write enable and clock enables signals meet the
required set-up and hold time with respect to the clock. In this
manner, fully asynchronous· operation is achieved. The
IDT7MP6025 is offered as a compact, cost-effective 43-pin plastic
SIP module. t

• 64K x a fully synchronous memory
• High-speed-20MHz read cycle time
• 16-bit synchronous address input
• a-bit synchronous data input
• Synchronous chip select and write enable
• Separate clock enable for each register
• Low standby power

.

• Onboard decoupling capacitors
• Available in 43-pin SIP (single in-line package) configuration
• 2 Ground and 2 Vee pins

DESCRIPTION:
The IDT7MP6025 is a 64K x a synchronous RAM with edge triggered registers on the address lines, data-in bus, data-out bus,
chip select and write enable. The edge triggered register of the 16
address lines features an independent clock enable that allows the
address register to be selectively loaded. The address register will
be loaded on the low-te-high transition of the clock when the clock
enable line is low and will hold its current contents on the low-tehigh transition ofthe clock when the clock enable is high. Similarly,
the a-bit data-in register will be loaded with new data on the low-tehigh transition of the clock when the data-in clock enable is low
and will hold its contents when the data-in clock enable is high. The
data-out register will receive new data from the 64K x a RAM when
the clock enable line is low and will hold its data when the clock
enable line is high at the low-te-high transition of the clock. All

FUNCTIONAL BLOCK DIAGRAM

~15}

16

I - - - - r . - - - - -..... ADDRESS

Ao

64Kx8
RAM
~----------4CS

WE

WE
DATA IN

DATA OUT

CLOCK

D~7 }

8

Dlo

DJ-cLREN

CEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
©

DECEMBER 1987

1987 Integrated DevIce Technology. Inc.

DSC-7022j-

13-123

IDT7MP6025 512K (64K x 8) SYNCHRONOUS
STATIC RAM PLASTIC SIP MODULE

PIN CONFIGURATION

COMMERCIAL TEMPERATURE RANGE

PIN.NAMES
A O- 15
1

Addresses

CK

Clock

Dl0--7

Data Input

6
7

D°0--7

Data Output

8

OI-<:;CRE:f\J

Data Input Clock Enable

2

3
4
5

9
10
11

'A-'CC'I twz + tow) to allow the I/O drivers to tum off and data to be placed on the bus for the required tow. If
is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp •

rn:

13-130

IDT7M134S/IDT7M135S CMOS DUAL-PORT
RAM MODULE 64K (SK x S-BIT) & 12SK (16K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF CONTENTION CYCLE NO.1, CE ARBITRATION
CE L VALID FIRST:
ADDR
LAND R

~

>C

ADDRESSES MATCH

~t~l [t=_*_

~R

CE R VALID FIRST:
ADDR
LAND R

~

>C

ADDRESSES MATCH

~t~l

[t,oc=;_

TIMING WAVEFORM OF CONTENTION CYCLE NO.2, ADDRESS VALID ARBITRATION(S)
LEFT ADDRESS VALID FIRST:
14----

t~CJ?

OR

two ----~

ADDRESSES MATCH

ADDRESSES DO NOT MATCH

tAPS

t~

BOSYR

9 _______

~~------

tB_DA_-______

RIGHT ADDRESS VALID FIRST:
1 4 - - - - t RO

OR two - - - - - - t
ADDRESSES DO NOT MATCH

ADDRESSES MATCH
tAPS

t~

9 _______

...,~------

tB_DA_-______

13-131

IDT7M134S/IDT7M135S CMOS DUAL-PORT
RAM MODULE 64K (SKx B-BIT) & 12SK (16Kx B-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ WITH BUSY(S)

ADDRSl(R)

~~

~{.

ADDRESSES MATCH

---l"

ADDRESSES 00 NOT MATCH

J\

14- tAPS·
~(.

ADDRSR(L)

J\

_ t BAA -

, . . - t BoA -

.J-

~r-

BUS'Y'R(L)

J

\

tAW
-

tAS---i

f4-

tw p -

\'\~
I

.,l
J
_

toH

tow

... t
Bo

-;~

DATAINl(R)

-'r-

d11 )_

~t
J\

oATAVAUo

d

t oO 1O)

~(j ~ oATAVAUo ~

HIGH IMPEDANCE

DATA OUT R(L)

t

(10)
WOO

TIMING WAVEFORM OF WRITE WITH BUSY(S)

R/W

NOTES:
1. Rm is high for Read Cycles.
2. Device is continuously enabled.
= VIL.
3. Addresses valid prior to or coincident with
transition low.
4. If
goes high simultaneously with R/W high. the outputs remain in the high impedance state.

cr

cr
crL = crR = \'IL

cr

5.
6. (5'E = \'IL
7. R/W = \'IH during address transition.
8. Transition is measured at +500mV from low or high impedance voltage with load (Figures 1. 2 & 3). This parameter is guaranteed by design. but
not tested.
9. For SLAVE port (IDT7M144/1DT7M14S) only.
10. Port·tOoport delay through RAM cells from writing port to reading port.
11. This parameter guaranteed by design. but not tested.

13-132

IDT7M134S/IDT7M135S CMOS DUAL-PORT
RAM MODULE 64K (8Kx 8-BIT) & 128K (16K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION
The ID17M134/135 provide two ports with separate control,
address and I/O pins that permit independent access for reads or
writes to any location in memory. The ID17M 134/135 have an automatic power down feature controlled by CEo The CE controls on- .
chip power down circuitry that permits the respective port to go into
a standby mode when not selected (CE high). When a port is enabled, access to the entire memory arra.Y.ls permitted. Each port
has its oW!LOutput Enable control (OE). In the read mode,
the port's OE turns on the output drivers when set LOW.
Non-contention READ/WRITE conditions are illustrated in Table I.

ARBITRATION LOGIC,
FUNCTIONAL DESCRIPTION
The arbitration logic will resolve an address match or a chip
enable match down to 10ns minimum and determine which port
has access. In all cases, an active BUSY flag will be set for the
delayed port.
The BUSYfiags are provided for the situation when both ports
simultaneously access the same memory location. When this situation occurs, on-chip arbitration logic will determine which port
has access and set the delayed port's BUSY flag. BUSY is set at
speeds that permit the processor to hold the operation and its
respective address and data. It is important to note that the
operation is invalid for the port that has BUSY set LOW. The
delayed port will have access when BUSYgoes inactive.
Contention occurs when both left and right ports are active and
both addresses match. When this situation occurs, the on-chip
arbitration logic determines access. Two modes of arbitration are
provided: (1) if the addresses match and are valid before CE,
on-chip control logic arbitrates between CE Land CE R for access;

or (2) if the CEs are low before an address match, on-chip control
logic arbitrates between the left and right addresses for access
(refer to Table III, Address Arbitration). In either mode of arbitration,
the delayed port's BUSY flag is set and will reset when the port
granted access completes its operation.

DATA BUS WIDTH EXPANSION,
MASTERISLAVE DESCRIPTION
Expanding the data bus width to sixteen-or-more-bits in a dualport RAM system implies that several chips will be active at the
same time. If each chip includes a hardware arbitrator, and the
addresses for each Chip arrive at the same time, it is possible that
one will activate its BUSYL while another activates its BUSYR
Signal. Both sides are now busy and the CPUs will wait indefinitely
for their port to become free.
To avoid this "busy lock-out" problem, IDT has developed a
MASTER/SALVE approach where only one hardware arbitrator, In
the MASTER, is used. The SLAVE has BUSY inputs which allow an
interface to the MASTER with no extemal components and with a
speed advantage over other systems.
When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed until after the BUSY input has settled. Otherwise, the SLAVE Chip may begin a write cycle during a
contention situation. Conversely, the write pulse must extend a
hold time past BUSY to ensure that a write cycle takes place atter
the contention is resolved. This timing is inherent in all dual-port
memory systems where more than one chip is active at the same
time.
The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs,
the write to the SLAVE will be inhibited due to BUSY from the
MASTER.

TRUTH TABLES
TABLE I-NON-CONTENTION READ/WRITE CONTROL,
LEFT OR RIGHT PORT (1)
CE

"OE

X

H

X

X

H

X

L

L

X

DATA IN

Data on Port Written into Memory (2)

H

L

L

DATA OUT

Data in Memory Output on Port (3)

H

L

H

R/W

FUNCTION

1/0 0- 7
Z

Port Disabled and in Power Down Mode, IS9

Z

CE: R = CEL = H, Power Down Mode, IS9 or IS92

Z

High Impedance Outputs

NOTE:
1. A OL -A'3L" AOR - A'3R
2. If SUS'i' = L, data is not written.
3. If ~ = L, data may not be Valid, see tWDD and toDD timing.
4. H=HIGH, L=LOW, X=DON'T CARE, Z=HIGH IMPEDANCE

13-133

IDT7M134S/IDT7M13SS CMOS DUAL-PORT
RAM MODULE 64K (8K x 8-BIT) & 128K (16K x 8-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE III-ARBITRATION
LEFT PORT

CE L

AOL - A 13L

CER

H

X
Any

H

L

FLAGS (1)

RIGHT PORT

FUNCTION

trosVL

AOL - A13R

H

X
X

H
H

X
Any
L
L
L
t- AOR-AI3R
t- AOL -AI3L
ADDRESS ARBITRATION WITH CE LOW BEFORE ADDRESS MATCH
H

L
LV10R
LV10R
L
RV10L
L
LV10L
L
L
Same
Same
L
Same
L
Same
L
CE ARBITRATION WITH ADDRESS MATCH BEFORE CE
LL10R
LL10R
= AOR-A13R
= AOL -A13L
RL10L
RL10R
= AOR-AI3R
= AOL -AI3L
LW10R
LW10R
= AOR-A13R
= AOL-AI3L
LW10R
LW10R
= AOR-AI3R
= AOL -AI3L

trosVR
H
H

No Contention
No Contention
No Contention
No Contention

H

H

H

H

H
L

L
H
L
H

H
L

Left-Port Wins
Right-Port Wins
Arbitration Resolved
Arbitration Resolved

H

L

L
H

H
L

Arbitration Resolved

L

H

Arbitration Resolved

Left-Port Wins
Right-Port Wins

NOTE:
1. X = DON'T CARE. L = LOW. H = HIGH. Same = Left and Right Addresses match within 10ns of each other.
LV10R = Left Address Valid ~ 10ns before Right Address.
RV10L = Right Address Valid ~ 10ns before Left Address.
LL10R = Left cr = LOW;:: 10ns before Right cr.
RL1OL = Right cr = LOW_> 10ns before Left cr.
LW10R = Left and Right cr = LOW within 10ns of each other.

ORDERING INFORMATION
lOT

XXXX
A
Device Type Power

999
Speed

A
Package

A
Process!
Temperature
Range

y:~NK

L..--------------f

~---------------~

L..--__________________________________

13-134

Commercial (O°C to + 70 0 C)
Military (-55°C to + 125" C)
Semiconductor components compliant
to MIL-STO-883. Class B

C

Sidebraze DIP

45
50
60
70
.90
100

Commercial onlY}
Commercial Only

S

Standard Power

~~~~~~

Speed in Nanoseconds

64K (8K x 8-bitl
128K (16K x 8-bit)

----_ .._ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

FEATURES:

DESCRIPTION:

• High-density 256K-bit CMOS dual-port RAM module

The IDT7M137 .Is a 256K-bit high-speed CMOS dual-port static
RAM module constructed on a multi-layered ceramic substrate using eight IDT7134 dual-port RAMs in leadless chip carriers. The full
32K bytes of dual-port RAM are directly addressable by utilization
of the two on-board IDT54/74FCT138 decoder circuits that interpret the higher order addresses At.12-14 and AR12-14to select one of
the eight 4K x 8 dual-port RAMs. Extremely high speeds are
achieved in this fashion due to the use of the IDT7134 dual-port
RAM, fabricated in IDT's high-performance CEMOS technology.
The IDT7M137 provides two ports with separate control, address and I/O pins that permit independent, asynchronous access
for reads or writes to any location in the memory. The IDT7M 137 is
deSigned to be used in systems where on-chip hardware port arbitration is not needed. It is the user's responsibility to ensure data
integrity when simultaneously accessing the same memory location from both ports.
The IDT7M137 is available with access times as fast as 55ns
commercial and 60ns military temperature range, with operating
pOwer consumption of only 4W (max.) The modules also offer a
standby power mode of 3.6W (max.) and full standby mode of 1.3W
(max.).
All IDT military module semiconductor components are manufactured in compliance to the latest revision of MIL-STD-883, Class
8, making them ideally suited to applications demanding the highest level of performance and reliability;

• 32K x 8 organization
• Low power consumption
• CEMOS 1101 process virtually eliminates alpha particle soft error
rates (with no organic die coating)
• Battery backup operation - 2V data retention
• Fully asynchronous operation from either port
• Single 5V(±10%) power supply
• Dual Vee and GND pins for maximum noise Immunity
• Inputs and outputs directly TTL-compatible
• Fully static operation
• Modules available with semiconductor components compliant
to MIL-STD-883, Class 8

PIN CONFIGURATION

PIN NAMES
LEFTPORT

RIGHT PORT

NAMES

crL

crR

Rfifh

R/WR

ReadNJrite Enable

OEL
AOL-14L

OER
AOR-14R

Output Enable
Address

Il00L-7L

IIOoR-7R

Data Input/Output

Chip Enable

Vee

Power

GND

Ground

NOTES:
1. Both \be pins need to be connected to the 5V supply and both GND
pins need to be grounded for proper operation.
2. On16Kx8IDT7M136option,A,4L andAl4R needtobeextemallyconnected to ground for proper operation.
3. For module dimensions, please refer to module drawing M7 in the
packaging section.

DIP
TOP VIEW

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987lntegraled Devk:e Technology. Inc.

DECEMBER 1987
DSC-70241-

13-135

m

IDT7M137 256K (32K x S-BIT)
DUAL-PORT CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAM
IDT7M137 (32K x a-BIT)

R/WR

I

l

. '---

-

IDT7134

CE'L

CE'R

(')( ') (

J
-

l
'--

- -

0

:J
1/0t.0-7

IDT7134

CE'L

~
I-

l
'--

I--

r--

CE'R

IDT7134

CE'L

CE'R

J
-

-

'--

-

~(

~

') (

') 0

IDTFCT138
DECODER h
040 5 06 ~ ~

~

y\

~l ~ ) ~

. A12-14R

)

n

n

CE'R

GEL

'"7->
'----

-

I--

0001 0 2 0 3

IDTFCT138
DECODER

CE'L

UE'R

t----

y

')A

J

CE'R

I

,.., 0 0 .0 0
0 1 2
3

0405 06

IDT7134

CE'L

Y y

Y I

I

LI

.'-"

A12-14L

AO-llR

1

IDT7134

r

I-I--

~

I

~

~

~

GER

GEL

GER

'--

r--

r

IDT7134

-

1

-

IDT7134

r

~
I-I--

~

--r--

r

GEL

"

l)
GER

IDT7134

I

,J

1

r-I-

1

FUNCTIONAL DESCRIPTION:
The IDT7M137 provides two ports with separate controls, address and I/O that permit independent access for reads or writes to
any location in memory. Th~T7M137 has an automatic power
down feature controlled by CE. The CE controls on-chip power
down circuitry that permits the respective port to go into a standby

mode when not selected (CE high). When a port is enabled, access to the entire mem~array is permitted. Each port has its own
Output Enable control (DE }.In the read mode, the port's DE tums
on the output drivers when set LOW.

13-136

IDT7M137 256K (32K x B-BIT)
DUAL-PORT CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM

RATING

COMMERCIAL

Tenninal Voltage
with Respect to
GND

-0.5 to +7.0

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

UNIT

MILITARY
-0.5 to +7.0

GRADE

V

Military

TA

Operating
Temperature

Oto +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

Commercial

AMBIENT
TEMPERATURE
-55°C to + 125°C

GND
OV

S.OV ± 10%

O°Cto +70°C

OV

5.0V ± 10%

Vee

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

DC Output Current
50
50
mA
10LIT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause pennanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

MIN.

TYP.

MAX.

Vee

Supply Voltage

PARAMETER

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V1H

Input High Voltage

2.2

V

Input Low Voltage

-

6.0

V1L

0.8

V

-0.5(1)

NOTE:
1. V1L = -3.5V for pulse width less than 30ns.

DC ELECTRICAL CHARACTERISTICS
(Vee

= 5.0V ±10%, TA = -55°C to

SYMBOL

+ 125°C and O°C to + 70°C)

PARAMETER

TEST CONDITIONS

MIN.

lIu l

Input Leakage Current

Vee = 5.5V. VIN = OV to Vee

-

IILol

Output Leakage Current

cr. = "'H' VOLrr = OV to Vee

-

IDT7M137
TYP.
MAX.

-

UNIT

20

jJA

20

jJA

6.0

V

0.8

V

'-"H

Input High Voltage

2.2

'-"L

Input Low Voltage

-1.0(2)

lee

Dynamic Operating Current
(Both Ports Active)

CE = V1L• Outputs Open

-

275

730

mA

IS8

Standby Current
(Both Ports Standby)

ct:L and ct:R ~ "'H

-

200

560

mA

IS81

Standby Current
(One Port Standby)

eEL or ct: R ~ V1H
Active Port Outputs Open

-

225

650

mA

IS8
2

Full Standby Current
(Both Ports Full Standby)

Both Ports
ct:L and ct:R ~ Vee -0.2V
VIN ~ Vee -0.2V or ~N < 0.2V

-

8

24013)

mA

Output Low Voltage
(1/0 0 -I/Dr )

-

-

0.4

V

VOL

-

0.5

V

-

V

10L = 8mA
10L = 10mA

VOH
Output High Voltage
10H = -4mA
NOTES:
1. Vee = 5V, TA = +25°C
2. V1L min. = -3.5V for pulse width less than 30ns.
3. ISB2 max. of IDT7M137 at commercial temperature = 150mA.

2.4

13-137

UNIT

IDT7M137 256K (32K x 8-BIT)
DUAL-PORT CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
N,..,.. - 5V -+:10%. T A
SYMBOL

-

-55°C to ± 125°C and 0°CJ070°C}
PARAMETER

IDT7M137S55
(COM'L ONLy)
MIN.
MAX.

IDT7M137S60

IDT7M137S70

IDT7M137S90

MIN.

MIN.

MIN.

MAX.

MAX.

IDT7M137S100
(MIL ONLy)
MAX. MIN.
MAX.

UNIT

READ CYCLE

-

ns

100

ns

100

ns

40

ns

10

-

ns

5

-

ns

40

-

40

ns

5

-

5

-

ns

40

-

40

-

40

ns

0

-

0

-

0

-

ns

60

-

60

-

60

-

60

ns

-

90

-

100

90

-

10

-

t RC

Read Cycle Time

55

-

60

-

70

-

90

-

100

tM

Address Access Time

55

Output Enable Access Time

35

-

90

t AoE

-

70

Chip Enable Access Time

-

60

t AcE

-

-

tOH

Output Hold From Address Change

0

-

0

0

Chip Select to Output in Low Z

15

-

15

15

-

10

tcLZ

-

5

-

tCHZ

Chip Select to Output in High Z

-

35

-

40

-

40

-

toLZ

Output Enable to Output in Low Z

5

-

5

-

5

-

tOHZ

Output Enable to Output in High Z

-

30

-

35

-

tpu

Chip Enable to Power Up Time

0

-

0

-

tpo

Chip Disable to Power Down Time

-

60

-

55

60
35

70
40

90
40

WRITE CYCLE
twc

Write Cycle Time

55

-

70

Chip Enable to End of Write

50

-

60

tEW

55

-

60

tAW

Address Valid to End of Write

50

-

55

-

60

t AS

Address Set-up Time

5

5

5

twp

Write Pulse Width

45

50

tWA

Write Recovery Time

5

-

tow

Data Valid to End of Write

25

-

30

tOH

Data Hold Time

5

-

5

-

tOHZ

Output Enable to Output in High Z

-

35

-

40

twz

Write Enabled to Output in High Z

0

35

0

40

tow

Output Active From End of Write

0

-

0

-

5

13-138

80

45

5

-

10

-

-

40

-

40

0

40

0

-

0

55
5
35

·0

-

80
10
70
10

90

ns
ns
ns
ns

10

-

-

50

ns

40

0

50

ns

-

0

-

ns

80
10

50

ns
ns
ns
ns

IDT7M137 256K (32K x 8-BIT)
DUAL-PORT CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1 EITHER SIDE

(1,2,8)

ADDRESS

DATA OUT

TIMING WAVEFORM OF READ CYCLE NO.2 EITHER SIDE

(1,3)

r..----- tAce----.1
CE"

DE"

DATA OUT

Icc
Vcc

__
tPU--;.,-::L~_ _
tpD=1

~

J_ 50%

_ _ _C_U_R_R_EN_T_ _ _
IS8

13-139

IDT7M137 256K (32K x a-BIT)
DUAL-PORT CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1,2,3,7)
two
ADDRESS

~

----I

)

K

1/

~

..JV
~

tAW

..;V

r\..
~tAS

t

WE

""",_
tOHZ

I-

tWR

(7)

WP

r--- t OHZ

..;V
tWZ(6~

(6)

I 4 - tow

• (4)

DATA OUT

(6)_

(4)

tow_

tOH

----------~E---->~~-----TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,3,5)

two
ADDRESS

)K

=:) (
tAW

..JV

'",
f---tAS

tWR

tEW

tow
I.;'

"

I--

tOH
~

II

NOTES:

1.
2.
3.
4.
5.
6.
7.

WE or'O'S must be high during all address transitions.
A write occurs during the" overlap (t~ of a 10w'O'S and a low WE.
tWR Is measured from the ear1ier of 'O'S or WE going high to the end of write cycle.
During this period. 1/0 pins are in the output state, and Input signals must not be applied.
If the 'O'S low transition occurs simultaneously with or after the WE low transition, the outputs remain In a high Impedance state.
Transition Is measured ±2oomV from steady state with a 5pF load (including scope and jig). This parameter is sampled and not 100% tested.
During a WE controlled write cycle, write pulse (twP) > twz + tow) to allow the 110 drivers to tum off and data to be placed on the bus for the required tow. If
'OE" is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp •

13-140

IDT7M137 256K (32K x S-BIT)
DUAL-PORT CMOS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

CAPACITANCE

. AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND t03.0V
10ns
1.SV
1.SV
See Figures 1, 2 and 3

SV

DATAoUT

~

nso

.

SYMBOL

(TA= +2SOC, f = 1.0MHz)

TEST

C OUT

Output Capacitance

CIN

Input Capacitance

CONDITIONS

TYP.

UNIT

VIN = OV

120

pF

VOUT= OV

50

pF

NOTE:
1. This parameter is sampled and not 100% tested.

SV12500

12500
DATA OUT

~

nso

30pF*

Figure 1.
Output Load

SpF*

Figure 2.
Output Load

(for ltiz. tu. twz, and tow)
* Including scope and jig.

ORDERING INFORMATION
IDT

, xxxx
Device Type

999

A

A

Speed

Package

Process/
Temperature

L _ fMk

RM

'---......,...-------i

Commercial (O°C to + 70°C)
Military (-55°C to +12S°C)
Semiconductor components
compliant to MIL-STD-883, Class B

C

Sidebraze

55
60

Commercial Only

} Speed In Nanosecond.

'-----------------------~70

90
100

~----------------------------~S
~--------------------------------------~7M137

13-141

Military Only
Standard Power
32Kx 8-Bit

FEATURES:

DESCRIPTION:

• High-density 64K/12eK-bit CMOSSLAVE dual-port RAM
modules

The 10T7M144/145 are 64K/128K-bit high-speed CEMOS TM
SLAVE dual-port static RAM modules constructed on a multilayered, co-fired, ceramic substrate using four IDT7142 2K x 8
SLAVE dual-port RAMs (IDT7M 144) or eight IDT7142 SLAVE dualport RAMs (IDT7M145) in lead less chip carriers. Dual-port function
Is achieved by utilization of the two on-board IDT54/74FCT138 decoder circuits that interpret the higher order addresses ALll-13 and
ARll-13 to select one of the eight 2K x 8 dual-port RAMs. (On
10T7M144 8K x 8 option, the AL13 and AR13 need to be externally
grounded and the selection becomes one of the four 2K x 8
dual-port RAMs.)
The IDT7M1441145 are designed as "SLAVE" dual-port RAM
modules to be used together with the IDT7M135/135 "MASTER"
dual-port RAM modules In 16-0r-more-bit systems, whereas the
IDT7M134/135 are designed to be used as stand-alone 8-bit dualport RAM modules. USing the lOT MASTER/SLAVE dual-port RAM
module approach in 16-0r-more-bit memory system applications
results in full speed operation without the need for additional discrete logic.
Both SLAVE 10T7M1441145 and MASTER IDT7M1341135 modules provide two ports with separate control, address and I/O pins
that permit independent asynchro~ccess for reads or writes
to any location in the memory. The BUSY flags are provided for the
situation when both ports simultaneously access the same memory location. BUSY is set at speeds that permit the processor to
hold the operation and its res~tive address and data. The delayed port will have access when BUSY goes high (inactive). The
BUSY pins are outputs on the MASTER and inputs on the SLAVE.

• Easily expands data bus width to 16-0r-more-bits when used
with MASTER IDT7M134 or IDT7M135
• 16K x 8 organization (IDT7M145) or 8K x 8 option (IDT7M144)
• High-speed access
- Military: 60ns (max.)
- Commercial: 45ns (max.)
• Low power operation
- Active: 950mW (typ.) (IDT7M144)
- Standby: 20mW (typ.) (IDT7M144)
•
•
•
•
•
•

BUSY Input flags
Fully asynchronous operation from either port
Fully static operation
Dual Vee and GND pins for maximum noise immunity
Inputs and outputs directly TTL-compatible
Single 5V(±10%) power supply

• Modules available with semiconductor components compliant
to MIL-STD-883, Class B

PIN CONFIGURATION

PIN NAMES
LEFTPORT

RIGHT PORT

~L

~R

NAMES
Chip Enable

Rfifh

R/WR

Read/write Enable

t5E'J.

t5E'R

Output Enable

tmsVl

tmsVR

Busy Flag

AOL -A 13L

AOR-A13R
I/OOR-I/0 7R

Address

I/CoL -I/OrL

Data Input/Output

Vee

Power

GND

Ground

NOTES:
1. Both Vee pins need to be connected to the 5V supply and both GND pins need to be grounded for
proper operation.
2. On 8K x 8 IDT7M134 option, A13L and A13R need to be extemally connected to ground for proper
operation.
3. IDT7M134~ll:~MASTER): tmsV is open drain output and requires pull up resistor.IDT7M144/145
(SLAVE):
is input.
4. For module dimensions, ptease refer to module drawing M7 in the packaging section.

','",

DIP
TOP VIEW
CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
@19871n1egratedDevlceTechnoiogy. Inc.

DECEMBER 1987
OSC-7025/-

13-142

IDT7M144S/IDT7M145S CMOS SLAVE DUAL-PORT
RAM MODULE 64K (SKx 8-BIT) & 12SK (16K x S-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAMS
(A) IDT7M145 (16K x 8-BIT)
R/WR
AO-l0R

OE'R
~

f--

13OS?L --I-+-I-H~-fCE'L

,..-

f--

CE'R

CE'L

r-

eER

I--

CE'L

t--

r-

CE'L

CE'R

eER '---1-+-+-1--

""'-+-)---H-I-I---f-I_Ii--H-t-i-'1 Ir-+Y-t-t-t-t-"-Y ~

j

1000

1/~7 -+-t-~f----t
C')-+C~-Cl-)-tn-t-i-t-t-----t-r.--t-----t-H
eEL -++H-H~nlOoOl O2 0 3
IDTFCT138
DECODER
Al1-13L -++++-~0405 0 6 0,.
I ) \)

00010203'-~~~­

IDTFCT138
DECODER

0 4 0 5 0 6 0,.

Y

y\,J\,J

"'}-I-+-+++t-'

,J

I
~
' - - CE'L

CE'R

L.--

IDT7142

r-

r

CE'L
I--

......

I--

,..-

~

CE'R

CE'L

CE'R

t- '-IDT7142

r

I--

t"1

r-

CE'L
I--

IDT7142

r

~

!)
CE'R t - -

t---

r

'--

;DT7142

~
j

(B) IDT7M144 (8K x 8-BIT)

I

l
'---

J

IDT7142

reEL
()

1/~7

P

()

CE'R
0

()

-ct <:\, 0, l:l, <:\,
IDTFCT138
DECODER

-

l

l

'--

r

IDT7142

rn;L rn;.
U

\)

~

'"-

~

l

-

r

IDT7142

~

r-

Y~

rn;L rn;.

Y

I

-

L

I

I

IDT7142

r_l

J
-

() ~

rn;L rn;.

6

(')

1<:\,0, l:l, l:l,

p--

IDTFCT138 ~
DECODER

(A13R

(A13W

(GROUND A 13L AND A 13R EXTERNALLY)

13-143

IDT7M144S/IDT7M145S CMOS SLAVE DUAL-PORT
RAM MODULE 64K (SK x 8-BIT) & 128K (16K X 8-BIn

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(DC electricals for the IDT7M144/IDT7M145 SLAVE dual-port are identical to the IDT7M134/IDT7M135 MASTER dual-port. Reference the
IDT7M134/IDT7M135 CMOS dual-port RAM data sheet.)

AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(AC electricals for the IDT7M144/IDT7M145 SLAVE dual-port are Identical to the IDT7M134/IDT7M135 MASTER dual-port except where
noted below.)

J

SYMBOL

PARAMETER

7M144S45
7M144S50
7M145S45
7M145S50
(COM'L ONLy)
MIN. MAX.
MIN. MAX.

7M144S60
7M145S60

7M144S70
7M145S70

7M144S90
7M145S90

7M144S100
7M145S100

MIN. MAX.

MIN. MAX.

MIN. MAX.

MIN.

MAX.

60

-

ns

0
20

-

ns

UNIT

twp

Write Pulse Width

35

-

40

-

45

-

45

Writeto~

0

-

0

-

0

0

0

-

tWH

Write Hold After ~

20

-

20

-

20

-

-

50

tWB

20

-

20

-

16-81T MASTERISLAVE DUAL-PORT MEMORY SYSTEM

RIGHT
LEFT
IDT7M134/5
.
.
.
R/W
R/W
14---+-R/W
MASTER
--r-.---I~

+5V

NOTE:
1. No arbitration in IDT7M144/IDT7M145 (SLAVE):

~

I---..-+--

+5V

.

~ IN inhibits write in IDT7M144/1DT7M145.

13-144

R/W

ns

IDT7M144S/IDT7M145S CMOS SLAVE DUAL-PORT
RAM MODULE 64K (SK x 8-BIT) & 12SK (16K x S-BIT)

.

.

..

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xxxx

A

Device Type

Process!
Temperature

~y:rMk

Commercial (O°C to

+70°C)

Military (-55°C to + 125°C)
Semiconductor Components
Compliant to MIL-STD-883, Class B
45

Commercial Only }
Commercial Only

50
I -.............................................-l

60

70

Speed in Nanoseconds

90
100
L-------------------------~S

Standard Power
64K (SK x 8-bit) SLAVE Dual~Port RAM
128K (16K x 8-bit) SLAVE Dual-Port RAM

7M144
~..........................................................................................~7M145

13-145

._.-_..

_ _-_.........._ - ..

FEATURES:

DESCRIPTION:

•
•
•
•
•
•
•

The IDT7M203/204 are FIFO memory modules that utilize a
special First-In, First-Out algorithm that loads and empties data
on a first-in, first-out basis. The device uses full and empty flags
to prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
The reads and writes are internally sequential through the use
of ring pointers, with no address information required to load and
unload data. Data is toggled in and out of the device through the
use of the WRITE (W) and READ (R) pins. The device has a
read/write cycle time of 65ns (15MHz) for commercial and 70ns
(14MHz) for military temperature ranges.
The device utilizes a 9-bit wide data array to allow for control
and parity bits at the user's option. This feature is especially
useful in data communications applications where it is necessary
to use a parity bit for transmission/reception error checking.
The IDT7M203/204 are constructed on a multi-layered ceramic
substrate using four IDT7201 (512x9) or four IDT7202 (1 Kx9)
FIFOs in leadless chip carriers. Extremely high speeds are
achieved in this fashion due tothe use of IDT7201 sand IDT7202s
fabricated in lOT's high-performance CEMOS technology.
lOT's military FIFO modules have semiconductor components
100% processed to the test methods of MIL-STD-883, Class B,
making them ideally suited to applications demanding the
highest level of performance and reliability.

First-In, First-Out memory module
2K x 9 organization (IDT7M203S)
4K x 9 organization (lDT7M204S)
Low-power consumption
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Assembled with lOT's high-reliability vapor phase solder reflow
process
-Single 5V (±10%) power supply
.' Master/slave multiprocessing applications
• Bidirectional and rate buffer applications
• Empty and full warning flags
• High-performance CEMOSTM technology
• Pin compatible with IDT7201 and Mostek MK4501, but with four
times word depth (IDT7M203S) or eight times (IDT7M204S)
• Module available with semiconductor components 100%
screened to MIL-STD-883, Class B

PIN CONFIGURATION
Vcc
04

FUNCTIONAL BLOCK DIAGRAM

05
06
07

02
01

00

.F[

Xi

RS

00- 08
00-08

W

EF

FF
00

XO

Xo

07

01
02
03

\06
05

08

04

R

1~ ~~

I II
l~~u

IDT7201/2

IDT7201/2

RS
XI-

XI

R

GNO

F[

XI

DIP
L...

TOP VIEW

PIN NAMES

L...-

W=
WRITE

FL =
FIRST ~OAD

XI =
EXPANSION IN

EF =
EMPTY FLAG

R=
READ

0=
DATA IN

XO =
EXPANSION
OUT

Vee =
5V

RS =
RESET

Q=
DATA OUT

FF =
FULL FLAG

GND =
GROUND

F[

Vcc
FF

-

Xo

IDT7201/2

IDT7201/2

F[

~n
I

~U

-~
-

"-

Xo

XI

F[

..F~

~~~

~ X, Fi: ~

~~

I

-

I-<

L.....--

DUAL 4-INPUT OR GATE

CEMOS is a trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1986 Integrated Device Technology. Inc.

13-146

JULY 1986
Printed in U.S.A.

IDT7M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATING(1)
SYMBOL

RATING

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-D.5 to +7.0

V

VTERM

Terminal Voltage
with Respect
toGND

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-10 to +S5

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

4.0

4.0

W

lOUT

DC Output Current

50

50

mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or anyotherconditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

MIN. TYP. MAX. UNIT

PARAMETER

Vee

Military Supply Voltage

4.5

5.0

5.5

V

Vee

Commercial Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage
Commercial

2.0

-

-

V

VIH

Input High Voltage
Military

2.2

-

-

V

VIL (1)

Input Low Voltage
Commercial & Military

-

-

O.S

V·

NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS
(Vee = 5V

SYMBOL

± 10%, TA = -55°C to +125°C and O°C to +70°C)
IDT7M203S
IDT7M204S
COMMERCIAL
MIN.
TYP.
MAX.

PARAMETER

MIN.

IDT7M203S
IDT7M204S
MILITARY
TYP.

MAX.

UNIT

NOTES

IlL

Input Leakage Current (Any Input)

-5

-

5

-10

-

10

}.LA

1

IOL

Output Leakage Current

-10

-

10

-10

-

10

}.LA

2

VOH

Output Logic "1" Voltage 'H

2.4

-

-

2.4

-

-

V

-

VOL

Output Logic "0" Voltage I L =SmA

-

-

0.4

-

-

0.4

V

-

lec1

Average Vee Power Supply Current

-

110

176

-

155

230

mA

3

Average Standby Current
(R =W = RS =IT =VIH)
Power Down Current
(All Input =Vee -0.2V)

-

20

33

-

30

60

mA

3

-

-

20

-

-

36

mA

3

lee2
lec3

=-2mA

NOTES:
1. Measurements with 0.4 ::; VIN:'O Vcc.
2. FL:: V1H , 0.4:'0 VOUT:'O Vec.
3. I cc measurements are made with outputs open.

13-147

I DT7M203S/1DT7M204S
,
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)

CAPACITANCE

(TA

=+25°C, f =1.0MHz)

PARAMETER(1)

CONDITIONS

TYP.

UNIT

C IN

Input Capacitance

35

pF

C OUT

Output Capacitance

=OV
VOUT =OV

40

pF

SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

VIN

NOTE:
1. This parameter is sampled and not 100% tested.

AC CHARACTERISTICS(1)
(VCC =5V ± 10%, TA =-55°C to +125°C and O°C to +70°C)
SYMBOL

PARAMETER

7M203/4S40
7M203/4SS0
COM'L. ONLY
MIN. MAX. MIN. MAX.

7M203/4SS5

7M203/4S6S

7M203/4S100 7M203/4S140

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

UNIT

MAX.

t Re

Read Cycle Time

50

-

65

-

70

-

85

-

125

-

165

-

ns

tA

Access Time

-

40

-

50

-

55

-.

65

-

100

-

140

ns

tRR

Read Recovery Time

10

15

-

15

-

20

-

25

40

50

-

55

-

65

100

140

tRLZ

Read Pulse Low to
Data Bus at Low Z(3)

5

-

10

-

10

-

10

-

10

-

-

ns

Read Pulse Width(2)

-

25

t RPW

-

10

-

ns

tWLZ

Write Pulse High to
Data Bus at Low Z(3.4)

10

-

15

-

15

-

15

-

20

-

20

-

ns

tov

Data Valid from
Read Pulse High

5

-

5

-

5

-

5

-

5

-

5

-

ns

tRHZ

Read Pulse High to
Data Bus at High Z(3)

-

25

-

30

-

30

-

35

-

40

-

50

ns

65

-

70

-

85

165

-

55

-

65

-

125

50

100

140

-

tWR

Write Recovery Time

10

-

15

15

-

20

-

25

tos

Data Setup Time

20

25

-

-

30

40

-

50

-

50

tOH

Data Hold Time

0

5

-

10

10

-

10

-

70

85

-

125

50

55

-

65

15

-

20

-

100

15

-

25

-

10

65

-

twe

Write Cycle Time

50

t wpw

Write Pulse Width(2)

40

-

25

t Rse

Reset Cycle Time

50

t RS

Reset Pulse Width(2)

40

tRSR

Reset Recovery Time

10

-

tEFL

Reset to Empty Flag Low

-

45

-

65

-

70

-

85

-

125

tREF

Read Low to Empty Flag Low

-

45

-

50

-

55

-

60

-

95

tRFF

Read High to Full Flag High

-

45

50

-

95

-

45

50

55

60

Write Low to Full Flag Low

-

45

50

-

55

-

95

tWFF

-

60

Write High to Empty Flag High

-

55

tWEF

-

-

95

-

60

165
140
25

NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design. not currently tested.
4.. Only applies to read data flow-through mode.

AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

SV
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1

DoU.T.TI

o

}' ' .

NOTE:
Generating R/W Signals - When using these high-speed FIFO devices. it is
necessary to have clean inputs on the R andW signals. It is important to not have
glitches. spikes or ringing on the R. W lines (violates the V1H • V1L requirements);
although the minimum pulse width low for the Rand Ware specified in tens of
nanosecond. a glitch of 5ns can affect the read or write pointer and cause it to
increment.

Lr~p

"Includes jig and scope capacitances.
Figure 1. Output Load.

13-148

ns

ns
ns
ns
ns
ns
ns
ns
ns

165

ns

135

ns

135

ns

135

ns

135

ns

IDT7M203S/lDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K

x 9-BIT & 4K x 9-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

been read from the FIFO, the EMPTY FLAG (EF) will go low,
allowing the "final" read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance
state. Once a valid write operation has been accomplished, the
EMPTY FLAG (EF) will go high after tWEF. and a valid READ can
then begin. When the FIFO is empty, the internal read pointer is
blocked from A; so external changes in R will not affect the FIFO
when it is empty.

SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (00-08)
Data inputs for 9-bit wide data.

CONTROLS:
RESET (RS)

FIRST LOAD (FL)

Reset is accomplished whenever the RESET (RS) input is
taken to a low state. During reset, both internal read and write
pointers are set to the first location. A reset is required after
power up before a write operation can take place. Both the
READ ENABLE (R) and WRITE ENABLE (W) inputs must be in
the high state during the window shown in Figure 2: i.e., tRPW
or t wpw before the rising edge of RS, and W should not change
until tRS R after the rising edge of RS.

WRITE ENABLE (W)
A write cycle is initiated on the falling edge of this input if the
FULL FLAG (FF) is not set. Data setup and hold times must be
adhered to with respect to the rising edge of the WRITE ENABLE
(W). Data is stored in the RAM array sequentially and independently of any ongoing read operation.
To prevent data overflow, the FULL FLAG (FF) will go low,
inhibiting further write operations. Upon the completion of a valid
read operation, the FULL FLAG (FF) will go high after tRFF,
allowing a valid write to begin. When the FI FO is full, the internal
write pointer is blocked from W, so external changes in Wwill not
affect the FIFO when it is full.

READ ENABLE (R)
A read cycle is initiated on the falling edge of the READ
ENABLE (R) provided the EMPTY FLAG (EF) is not set. The data
is accessed on a First-In, First-Out basis independent of any
ongoing write operations. After READ ENABLE (A) goes high, the
data outputs (00 through 08) will return to a high impedance
condition until the next READ operation. When all the data has

This pin is grounded to indicate that it is the first device. In the
multiple mode (depth expansion mode) application, this pin on
the rest of the devices should connect to Vee for proper operation.

EXPANSION IN (XI)
EXPANSION IN (xT) is connected to EXPANSION OUT (XO) of
the previous (in depth expansion) or same device for proper
application.

OUTPUTS:
FULL FLAG (FF)
The FULL FLAT (FF) will go low, inhibiting further write
operation, when the write pointer is one location from the read
pointer, indiciating that the device is full. If the read pointer is not
moved after RESET (RS), the FULL FLAG (FF) will go low after
2048 writes forthe IDT7M203 and 4096 writes forthe IDT7M204.

EXPANSION OUT (XO)
EXPANSION OUT (XO) is connected to the EXPANSION IN

(XI) of the same device (single device mode) or the EXPANSION
IN (XI) of the next device (multiple device, depth expanion mode)
for proper operation. This output acts as a signal to the next
device by providing a pulse to the next device when the current
device reaches the last location of memory.

DATA OUTPUTS (aO-a8)
Data outputs for 9-bit wide data. This output is in a high
impedance condition whenever READ (A) is in a high state.

f---------IRS-------~

NOTES:
1. t RSC = tRS +t RSR '

2. Wand

R =V1H around the rising edge of AS.
Figure 2. Reset

13-149

IDT7M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(,;4)
i------tRC-----t----tRPW---

tA--

----'-----C(

DATAIN VALID

DATA'N VALID

Figure 3. Asynchronous Write and Read Operation
LAST WRITE

FIRST READ

ADDITIONAL
READS

FIRST WRITE

~~
~~

W

F

I-tWFF

~

-- tRFF

j~

Figure 4. Full Flag From Last Write to First Read
LAST READ

FIRST WRITE

ADDITIONAL
WRITES

w

Figure 5. Empty Flag From Last Read to First Write
13-150

FIRST READ

)>----

IDT7M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IRPE: EFFECTIVE READ PULSE WIDTH AFTER EMPTY FLAG HIGH

w----"""""

SF ______________________________________________

~------J

NOTE:
1. (t RPE

=t RPW)
Figure 6. Empty Flag Timing

IWPF: EFFECTIVE WRITE PULSE WIDTH AFTER FULL FLAG HIGH

R----~

FF----------------------------------------------------------------------------------------~------J

NOTE:
1. (t WPF

=t wpw ).

Figure 7. Full Flag Timing

OPERATING MODES:
SINGLE DEVICE MODE

EXPANSION OUT (XO)

A single IDT7M203/IDT7M204 may be used when the application requirements are for 2048/4096 words or less. The
I DT7M203/1 DT7M204 is a Single Device Configuration when the
EXPANSION IN (xi') control input is connected to the
EXPANSION OUT (XO) of the device and the FIRST LOAD (FL)
control pin is grounded (see Figure 8).

WIDTH EXPANSION MODE

I
WRITE

DATAIN

13-151

/

FULL FLAG

(R)

~

9

RESET

Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags
(EF. FF) can be detected from anyone device. Figure 9 demonstrates an 18-bit word width by using two IDT7M2031 IDT7M204s.
Any word width can be attained by adding additional
I DT7M203/1 DT7M204s.

(Vi)

(D)

~

9#

)

(FF)r

READ

lOT
7M203/4

DATAoUT

(EF) EMPTY FLAGY

hFI)

(AS)

EXPANSION IN (XI )

(0) /

FIRST LOAD

•

Figure 8. Block Diagram of Single IDT7M203/1DT7M204 FIFO

IDT7M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 90BIT & 4K x 9-BIT)

DEPTH EXPANSION (DAISY CHAIN) MODE
The IDT7M203/IDT7M204 can easily be adapted to applications when the requirements are for greater than 2048/4096
words. Figure 10 demonstrates Depth Expansion using three
IDT7M203/IDT7M204s. Any depth can be attained by adding
additional I DT7M203/1 DT7M204s. The I DT7M203/1 DT7M204
operates in the Depth Expansion configuration when the
following conditions are met:
1. The first device must be designed by grounding the FIRST
LOAD (FL.) control input.
2. All other devices must have FL in the high state.
3. The EXPANSION OUT (XO) pin of each device must be tied to
the EXPANSION IN (XI) pin of the next device. See Figure 10.
4. External logic is needed to generate a composite FULL FLAG
(FF) and EMPTY FLAG (EF). This requires the ORing of all EFs
and ORing of all FFs (Le. all must be set to generate the
correct composite FF or EF). See Figure 10.

COMPOUND EXPANSION MODE
The two expansion techniques described above can be appl ied
together in a straightforward manner to achieve large FIFO
arrays. (See Figure 11.)

BIDIRECTIONAL MODE
Applications which require data buffering between two systems (each system capable of READ and WRITE operations) can
be achieved by pairing IDT7M203/1DT7M204s as is shown in
Figure 12. Care must be taken to assure that the appropriate flag

MILITARY AND COMMERCIAL TEMPERATURE RANGES

is monitored by each system (Le. IT is monitored on the device
where W is used; EF is monitored on the device where Ris used).
Both Depth Expansion and Width Expansion may be used in this
mode.

DATA FLOW-THROUGH MODES
Two types of flow-through modes are permitted with the
IDT7M203/IDT7M204: a read flow-through and write flowthrough mode. For the read flow-through mode (Figure 13), the
FIFO permits a reading of a single word after writing one word of
data into an empty FIFO. The data is enabled onthe bus in (twEF+
tA)ns after the rising edge ofW, called the first write edge, and it
remains on the bus until the R line is raised from low-ta-high,
after which the bus would go into a three-state mode after tRHZns.
The EF line would have a pulse showing temporary deassertion
and then would be asserted. In the interval oftime that R was low,
more words can be written to the FIFO (the subsequent writes
after the first write edge would deassert the empty flag); however,
the same word (written on the first edge), presented to the output
bus as the read pointer, would not be incremented whenR is low.
On toggling R, the other words that were written to the FIFO will
appear on the output bus as in the read cycle timings.
In a write flow-through mode (Figure 14), the FIFO permits the
writing of a single word of data immediately after reading one
word of data from a full FIFO. The R line causes the FF to be
deasserted, but the W line being low causes it to be asserted
again in anticipation of a new data word. On the rising edge of TN,
a new word is loaded in the FIFO. The W line must be toggled
when FF is not asserted to write new data in the FIFO and
increment the write pOinter.

DATA1N(D)

(R)

FULL FLAG

READ

1 - - - - -__ (EF) EMPTY FLAG

---....:......~-I-i

RESET - - ( A S )

(Q) DATAoUT

NOTES:
Flag detection Is accomplished by monitoring the FF and EF signals on either
(any) device used in the width expansion configuration. Do not connect any
output control signals together.

Figure 9. Block Diagram of 2048x18/4096x18 FIFO Memory
Used In Width Expansion Mode

13-152

IDT7M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TABLE I - RESET SINGLE DEVICE CONFIGURATIONIWIDTH EXPANSION MODE
INTERNAL STATUS

INPUT

MODE

Read Pointer

RS

OUTPUTS
EF

Write Pointer

FF

Reset

0

Location Zero

Location Zero

0

1

Read/Write

1

Increment(1)

Increment(1)

X

X

"

NOTE:'

1. Pointer will increment if flag is high.

TABLE II - RESET AND FIRST LOAD TRUTH TABLE DEPTH EXPANSION/COMPOUND EXPANSION MODE
OUTPUTS

INTERNAL STATUS

INPUTS
MODE

RS

FL

XI

Read Pointer

Write Pointer

EF

FF

Reset-First Device

0

0

(1)

Location Zero

Location Zero

0

1

Reset all Other Devices

0

1

(1)

Location Zero

Location Zero

0

1

Read/Write

1

X

(1)

X

X

X

X

NOTES:

1.

Xi is connected to XO of previous device. See Figure 10.
RS = Reset Input, FL = First Load, EF =Empty Flag Output, FF =Full Flag Output, Xi =Expansion

Input.

w
D

Figure 10. Block DIagram of 6144x9/12288x9 FIFO Memory (Depth ExpansIon)

13-153

IDT7M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

09-017

OO-OS

O(N-S)-ON

IDT7M203/4
DEPTH
EXPANSION
BLOCK

AS

DO-OS

•••

09-017

D9-DN

DO-ON

OCN-S)-ON

'

09-017

OO-OS

R, Vi,

...

D1S-DN

D(N-S)-DN'

•••

D(N-S)-DN

NOTES:
1. For depth expansion block see DEPTH EXPANSION Section and Figure 10.
2. For flag detection see WIDTH expansion Section and Figure 9.

Figure 11. Compound FIFO Expansion

Rs
EFs
-) OF THE
XOs (TO (XI
SAME DEVICE)

WA
FFA

,

~
DAO-S

lOT
7M203/4

OsO-S

J

r

*F[

A
SYSTEM A

SYSTEM B

~

A

11~

OAO-S
lOT
RA
(TO (Xi) OF THE SAME DEVICE) XO A
EFA

7M203/4

DsO-S

~

Ws
FFs

.iF[
Figure 12. Bidirectional FIFO Mode

13-154

IDT7M203S/IDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2K x 9-BIT & 4K x 9-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATAIN

_

--_+-----.. .
3V

W

_ OV

R

---+-------------------+-------4-----------J/

_ OV
EF

--r------------------+------J

DATAoUT----+-------------------------------+~

NOTE:
(TRPE =TRPW)

Figure 13. Read Data Flow-Through Mode

_ 3V

R

_

OV

W ---+------------~-----_+---------'/
_ OV
FF

---+-----------------r-------J

DATAIN---~---------------------------------------------~I. ""::s~

DATAoUT

·~I
------~~ DATAOUT

VALID

~------------

NOTE:
(TWPF =T wPw)

Figure 14. Write Data Flow-Through Mode

13-155

IDT7M203SIIDT7M204S
CMOS PARALLEL IN-OUT FIFO MODULE (2Kx 9-BIT " 4K x 9-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

xxxx

Power

Speed

A

A

Device Type

Power

Speed

Package

Process/
Temperature
Range

II

i8

13-156

8,,,k

Commercial
(O°C to +70°C)
Military
(-55°C to +125°C)
Semiconductor Components
Screened to MIL-STD-883,
Method 5004, Class B

C

Sidebraze

40
50
55
65
100
140

Commercial Only

S

Standard-Power

7M203
7M204

2K x 9-Bit
4K x 9-Bit

}

Speed
in
Nanoseconds

FEATURES:

DESCRIPTION:

• First-In/First-Out memory module

The ID17M20SS/206S are FIFO memory modules constructed
on a multi-layered ceramic substrate using four 1017203 (2K x 9) or
four ID17204 (4K x 9) FIFOs in lead less chip carriers. Extremely
high speeds are achieved in this fashion due to the use of ID17203s
and ID17204s fabricated in IDT's high·performance CEMOS technology. These qevices utilize a special First-In/First-Out algorithm
that loads and empties data on a first-in/first-out basis. The device
uses Full and Empty flags to prevent data overflow and underflow
and expansion logic to allow for unlimited expansion capability in
both word size and depth.
The reads and writes are internally sequential through the use of
ring pointers, with no address information required to load and unload data. Data is toggled in and out of the device through the use
of the WRITE (W) and READ (R) pins. The devices have a read/
write cycle time of SOns (2SMHz) for commercial and 6Sns (lSMHz)
for military temperature ranges.
The devices utilize a 9-bit wide data array to allow for control and
parity bits at the user's option. This feature is especially useful in
data communications applications where it is necessary to use a
parity bit for transmission/reception error checking.
IDT's Military FIFO modules have semiconductor components
manufactured in compliance with the latest revision of MILSTD-883, Class B, making them ideally suited to applications demanding the highest level of performance and reliability.

• 8K x 9 organization (ID17M20SS)
• 16K x 9 organization (ID17M206S)
• Low power consumption
- Active: 840mW (typ. Com'l.)
- Power Down: 176mW (max. Com'l)
• Asynchronous and simultaneous read and write
• Fully expandable by both word depth and/or bit width
• Assembled with IDT's high-reliability vapor phase solder reflow
process
• Single SV (t10%) power supply
• MASTER/SLAVE multiprocessing applications
• Bidirectional and rate buffer applications
• Empty and Full waming flags
• High-performance CEMOS 1M technology
• Pin-compatible with ID17201 and Mostek MK4S01, but with.16
times word depth (ID17M20SS) or 32 times (ID17M206S)
• Module available with semiconductor components compliant to
MIL-STD-883, Class B

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM

W
~

08
03
02
01
Do

l~..LJ..
XOr-

I II
l..L.~u

~

10T7203/4

10T7203/4

FF

~

~
~-

00

"Fl

Xl"

-1L~

01

O2

03
08

n

....E""UE
~

XO

XO
10T7203/4

GND

~Xl" "Fl ~

4¥I

DIP
TOP VIEW

_oj

FL =
FIRST LOAD

XI =
EXPANSION IN

EF =
EMPlY FLAG

R=
READ

0=
DATA IN

XO =
EXPANSION OUT

RS =
RESET

0=
DATA OUT

FF =
FULL FLAG

Vee =
5V
GND =
GROUND

~xr

1'Ll

....EF~~

~-a-

PIN NAMES
W=
WRITE

10T7203/4

-

DUAL 4-INPUT OR GATE

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCiAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology, Inc.

DECEMBER 1987
DSC-7027/-

13-157

IDT7M205S/IDT7M206S CMOS PARALLEL
IN-OUT FIFO MODULE 8K x 9-BIT & 16K x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
RATING

SYMBOL
VTERM

Terminal Voltage
with Respect to
GND

TA

COMMERCIAL

MILITARY

UNIT

-0.5 to +7.0

-0.5 to +7.0

V

Operating
Temperature

Oto +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

. °C

DC Output Current
50
50
mA
lOUT
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS
SYMBOL

MIN.

TYP.

MAX.

UNIT

VCCM

Military Supply
Voltage

PARAMETER

4.5

5.0

5.5

V

Vccc

Commercial
Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

~H(l)

Input High Voltage
Commercial

2.0

-

-

V

~H

Input High Voltage
Military

2.2

-

-

V

~L(1)

Input Low Voltage
Commercial &
Military

-

-

0.8

V

NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc= 5.OV ±10%, TA = O°C to + 70°C; Military: Vcc = 5V ±10%, TA = -55°C to + 125°C)
SYMBOL

PARAMETER

IDT7M205S
IDT7M206S
COMMERCIAL
MIN.
TYP.
MAX.

UNIT
MAX.

5

-10

-

10

J.l.A

10

-10

-

10

J..lA

2.4

-

-

2.4

-

-

V

Output Logic "0· Voltage lOUT = 4mA

-

-

0.4

-

0.4

V

ICCl (3)

Average Vcc Power Supply Current

-

168

264

-

224

350

mA

ICC2 (3)

Average Standby Current
(R = W = RST = FlIRT = VIH)

-

32

48

-

48

100

mA

ICC3 (3)

Power Down Current
(All Input = Vcc = -0.2V)

-

-

32

-

-

48

mA

IIL(l)

Input Leakage Current (Any Input)

10L (2)

Output Leakage Current

-10

VOH

Output Logic "1" Voltage lOUT = -lmA

VOL

-5

NOTES:
1.
2.
3.

MIN.

IDT7M205S
IDT7M206S
MILITARY
TYP.

Measurements with 0.4 S "IN S VOUT '
R <::: "iH, 0.4 S VOUT S Vcc
Icc measurements are made with outputs open.

13-158

IDT7M205S/IDT7M206S CMOS PARALLEL
IN-OUT FIFO MODULE BKx 9-BIT & 16Kx 9-BIT

CAPACITANCE
SYMBOL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(TA= +25°C, f = 1.0MHz)

PARAM ETER (1)

C1N

Input Capacitance

COUT

Output Capacitance

CONDITIONS

MAX.

UNIT

V1N = OV

40

pF

VOUT= OV

60

pF

NOTE:
1. This parameter is sampled and not 100% tested.

AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee= 5V ±10%, TA = O°C to

SYMBOL

(1)

+ 70°C; Military: Vee= 5V ±10%, TA = -55°C to + 125°C)
7M205S40
7M205S50
7M205S60
7M205S70
7M205SB5
7M205S120
7M206S40
7M206S50
7M206S60
7M206S70
7M206SB5
7M206S120
(COM'L ONLy)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

PARAMETER

t RC

Read Cycle Time

tA

Access Time

tRR

Read Recovery Time

10

tRPW (2)

Read Pulse Width

40

t RLZ (3)
t WlZ (3)

Read Pulse Low to Data Bus at Low Z

5

Write Pulse High to Data Bus at Low Z

10

tov
t
(3)
RHZ

Data Valid from Read Pulse High

5

twc
t wpw (2)

Write Cycle Time

50

Write Pulse Width

40

65::\):::.

50

::::::::::::::::::

40

~:.:.:.:.""""

i$?f:::::::::::;::::::g(f: Ii~:~:::::: -

tWA

Write Recovery Time

10

Data Set-up Time

20

105
70

140
85

ns
120

ns

15

15

20

20

ns

60

70

85

120

ns

10

10

10

10

ns

15

15

20

20

ns

5

30

}~S:.,

:~%~ ::::::::)~O

::)::::::15

::::::\1}::"

60

tSt:::\.
_ i::: i:=:::~::::::::::::'

...;.;::....:.

85

75

::::::1:9::::::::::::::

25I\ :r:;;:::

Read Pulse High to Data Bus at High Z

tos

::::'56

UNIT

\:30

5
30

5
30

5
30

ns
35

ns

75

85

105

140

ns

60

70

85

120

ns

15

15

20

20

ns

30

30

40

40

ns

:::}}'B}\: k 5

5

10

10

10

ns

. i}: 65

75

85

105

140

ns

50

60

70

85

120

ns

15

15

15

20

20

ns

tOH

Data Hold Time

0

t RSC

Reset Cycle Time

50

t RS (2)

Reset Pulse Width

40::::::;':':':::::::::2:\::'

t RSR

Reset Recovery Time

1ot:;:::::.::':::::: ~}

tEFL

Reset to Empty Flag Low

tREF

Read Low to Empty Flag Low

tRFF

:::::::::.:.

P

65

75

85

105

140

ns

50

60

70

85

120

ns

Read High to Full Flag High

·~t:O
::ff::::::} 40

50

60

70

85

120

ns

tWEF

Write High to Empty Flag High

::::~:::;t~t:tt 40

50

60

70

85

120

ns

tWFF

Write Low to Full Flag Low

40

50

60

70

85

120

ns

'WC

NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by deSign, not currently tested.

5V

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

D.U.T

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1, 2 & 3

~

6800

l'lK
30pF*

Figure 1. Output Load
*Includes jig and scope capacitances.

13-159

IDT7M20SS/IDT7M206S CMOS PARALLEL
IN-OUT FIFO MODULE 8Kx 9-BIT & 16Kx 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FIRST LOAD (Fr.)
This pin is grounded to Indicate that it Is the first device. In the
multiple module (depth expansion mode) application, this pin
on the rest of devices should connect to Vee for proper
operation.

SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (00- 08)
Data Inputs for 9-bit wide data.

EXPANSION IN (Xi)
EXPANSION IN (Xi) Is connected to EXPANSION OUT (XO)
of the previous (in depth expansion) or same device for proper
application.

CONTROLS:
RESET (RS)
Reset Is accomplished whenever the RESET (RS) input is
taken to a low state. During RESET, both internal read and write
pointers are set to the first location. A reset Is required after
power up before~ write operation can t~e place. Both the
READ ENABLE (R) and WRITE ENABLE cYV) inputs must be in
the high state during reset.

OUTPUTS:
FULL FLAG (FF)
The FULL FLAG (FF) will go low, inhibiting further write operation, when the write pointer is one location from the read
pointer, indicating that the device is full. If the read pointer is not
moved after RESET (RS), the FULL FLAG (FF) will go low after
8,192 writes for the IDT7M205 and 16,384 writes for the
IDT7M206.

WRITE ENABLE (Vi)
A write cycle is initiated on the falling edge of this input if the
FULL FLAG (FF) is not set. Data set-up and hold times must be
adhered towith respect to the rising edge ofthe WRITE ENABLE
CN). Data is stored in the RAM array sequentially and independently of any ongoing read operation.
To prevent data overflow, the FULL FLAG (FF) will go low, inhibiting further write operations. J!pon the completion of a valid
read operation, the FULL FLAG (FF) will go high after t RFF, allowing a valid write to begin.
READ ENABLE (R)
A re~ cycle is initiated on the fallin~ge of the READ ENABLE (R) provided the EMPTY FLAG (EF) is not set. The data is
accessed on a first-in/first-out basis independent of any ongoing write operations. After READ ENABLE (R) goes high, the
Data Outputs (00 through 08) will return to a high impedance
condition until the next READ operation. When all the data has
been read from the FIFO, the EMPTY FLAG (EF) will go low, inhibiting further read operations with the data outputs remaining
In a high impedance state. Once a valid write operation has
been accomplished, the EMPTY FLAG (EF) will go high after
tWEF and a valid READ can then begin.

EXPANSION OUT (XO)
. EXPANSION OUT (XO) is connected to the EXPANSION IN
(Xi) ofthesame device (single device mode) orthe EXPANSION
IN (xi) of the next device (multiple device, depth expansion
mode) for proper operation. This output acts as a signal to the
next device by providing a pulse to the next device when the current device reaches the last location of memory.
DATA OUTPUTS (00- 08)
Data outputs for 9-bit wide data. This output is in a high impedance condition whenever READ (R) is in a high state.

t RS

~\

w

I'.

I

JtEFL

t

)\.
- t RSR -

NOTES:

1. t RSC = t RS + t RSR
2. Vii and A = V IH during RESET.

Figure 2. RESET

13-160

(1,2)

I

r--

IDT7M205S/IDT7M206S CMOS PARALLEL
IN-OUT FIFO MODULE BK x 9-BIT & 16K X 9-BIT

tRL

MILITARY AND COMMERCIAL TEMPERATURE RANGES

1

tov

-I

tRHZ

-------OO(,....-D-AT-A-o-UT
-·-V-AL-I-D~~ DATA OUT VALID

~

'1:1;)1-----

.........................--twc ..............................~

~

1 4 - - - - twpw .....--~--

Vi

r,:

---------«

tos

tOH

=j

))------«

DATAIN VALID

DATA IN VALID

)>----

Figure 3. Asynchronous Write and Read Operation

LAST WRITE

FIRST READ

ADDITIONAL
READS

FIRST WRITE

\...-.-J~

Vi

-

-'r-

/
-

-

tWFF

-~

tRFF

-:

-~

Figure 4. Full Flag From Last Write to First Read

LAST READ

FIRST WRITE

ADDITIONAL
WRITES

FIRST READ

Vi

DATAOUT---1-1r-~~~~~~-1---------1-----t-~~~V~A~LI~D>K~
Figure 5. Empty Flag From Last Read to First Write

13-161

IDT7M205S/IDT7M206S CMOS PARALLEL
IN-OUT FIFO MODULE 8Kx 9-BIT & 16Kx 90BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

t RPE :EFFECTIVE READ PULSE WIDTH AFTER FULL FLAG HIGH (1)

w

NOTE:
(t RPE = t RPW )

1.

Figure 6. Empty Flag Timing

t RPE EFFECTIVE READ PULSE WIDTH AFTER FULL FLAG HIGH

w
NOTE:

1.

(tWPF = t wpw)
Figure 7. Full Flag Timing

13-162

(1)

IDT7M205S/IDT7M206S CMOS PARALLEL
IN-OUT FIFO MODULE 8K x 9-BIT & 16K x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DEPTH EXPANSION (DAISY CHAIN) MODE

OPERATING MODES:
SINGLE DEVICE MODE
A single IDT7M20S/206 may be used when the application requirements are for 8,192116,384 words or less. The IDT7M20S/206
is in a Single Device Configuration when the EXPANSION IN (xi)
control input is connected to the EXPANSION OUT (XO) of the device and the FIRST LOAD (FL.) control pin is grounded (see
Figure 8).

The IDT7M20S/206 can easily be adapted to applications when
the requirements are for greater than 8,192116,384 words. Figure
10 demonstrates Depth Expansion using three IDT7M205/206.
Any depth can be attained by adding additional IDT7M205/206s.
The IDT7M20S/206 operate in the Depth Expansion configuration
when the following conditions are met:
1. The first device must be designated by grounding the FIRST
LOAD (FL.) control input.
2. All other devices must have

FL in the high state.

3. The EXPANSION OUT (XO) pin of each device must be tied to
the EXPANSION IN (Xi) pin of the next device. (See Figure 10.)

EXPANSION OUT 0(0)

WRITE

4. External logic is needed to generate a composite FULL FLAG
(Fl2End EMPTY FLAG (EF). This requires the logical ANDing of
all EFs and logical ANDing of all FF..§ji.e. all must be set to generate the correct composite FF or EF). (See Figure 10.)

_D_AT_A_IN_--1_ _--W/17~~Js/6 1--'1----.1
FULL FLAG

COMPOUND EXPANSION MODE

RESET

The two expansion techniques described above can be applied
together in a straightforward manner to achieve large FIFO arrays.
(See Figure 11.)

(Fe) FIRST LOAD

BIDIRECTIONAL MODE

EXPANSION IN (>U)

Applications which require data buffering between two systems
(each system capable of READ and WRITE operations) can be
achieved by pairing IDT7M20S/206s as shown in Figure 12. Care
must be taken to assure that the appropriate flag is monitored by
each system (Le. FF is monitored on the device where W is used;
EF is monitored on the device where R is used). 80th Depth Expansion and Width Expansion may be used in this mode.

Figure 8. Block Diagram of Single IDT7M205206 FIFO

DATA FLOW-THROUGH MODES
WIDTH EXPANSION MODE
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF
and FF) can be detected from anyone device. Figure 9 demonstrates an 18-bit word width by using two IDT7M20S/206s. Any
word width can be attained by adding additionaIIDT7M205/206s.

Two types of flow-through modes are permitted with the
IDT7M20S/206: a read flow-through mode and write flow-through
mode. For the read flow-through mode (Figure 13), the FIFO permits a reading of a single word of data immediately after writing one
word of data into the completely empty FIFO.
In the write flow-through mode (Figure 14), the FIFO permits a
writing of a single word of data immediately after reading one word
of data from a completely full FIFO.

DATAIN (D)

WRITE--....
FU~L_L_F_LA_G_ _ _(l!F----'")_-+_-I

(R") READ

7~~Js/6

lOT
7M205/6

1-------.-

~) EMPTY FLAG

RESET - - - (RS)--+-~I-

(0) DATAoUT
NOTE:
Flag detection is accomplished by monitoring the
output control signals together.

FF and EF signals on either (any) device used in the width expansion configuration. Do not connect any

Figure 9. Block Diagram of 8,192 x 18/16,384 x 18 FIFO Memory Used In Width Expansion Mode

13-163

IDT7M205S/IDT7M206S CMOS PARALLEL
IN-OUT FIFO MODULE 8K x 9-BIT & 16K x 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLES
TABLE I-RESETSINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
INPUTS

MODE

INTERNAL STATUS

OUTPUTS

RS

XI

Read Pointer

Write Pointer

EF

FF

Reset

0

0

Location Zero

Location Zero

0

Read/Write

1

0

Increment(1)

Increment(1 )

X

1
X

NOTE:

1. Pointer will Increment Hflag Is high.

TABLE II-RESET AND FIRST LOAD TRUTH TABLEDEPTH EXPANSION/COMPOUND EXPANSION MODE
INPUTS

MODE

INTERNAL STATUS

OUTPUTS

AS

FL

XI

Read Pointer

Write Pointer

EF

FF

Reset-First Device

0

0

(1)

Location Zero

Location Zero

0

1

Reset all Other Devices

0

1

(1)

Location Zero

Location Zero

0

1

Read/Write

1

X

(1)

X

X

X

X

NOTES:

1.
2.

Xi is connected to XO of previous device. See Figure 10.
RS = Reset Input F[ = First Load, EF = Empty Flag Output, FF = Full Flag Output, Xi = Expansion Input.

w
D

~~~r-r-------------------------------Vcc

Figure 10. Block Diagram of 24,576 x 9/49,152 x 9 FIFO Memory (Depth expansion)

13-164

IDT7M205S/IDT7M206S CMOS PARALLEL
IN·OUT FIFO MODULE 8K X 9·BIT & 16K X 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

0 0 -0 0

Oe- 0

0 0 -0 0

R:W, AS

...

Oe- 0

.

IDT7M205/6
DEPTH
EXPANSION
BLOCK

-

.....::: .......... ;::...

IDT7M205/6
DEPTH
EXPANSION
BLOCK

.....:::

17

••• - -........

0(N-8)-ON

17

-

0(N-8)-ON

IDT7M205/6
DEPTH
EXPANSION
BLOCK

•••

;::...

Do-Do

De -D17

D(N-8)-DN

___
D,.;;0_-_D.;.;,N_ _ _ _ _ _ _ _
D,;;.e_-D....:.:.N_ _ _ _ _
D.;,;10;.,-_D.;,;N:..,.. • • •

D(N-8)-DN

NOTES:
1. For depth expansion block see DEPTH EXPANSION Section and Figure 10.
2. For Flag detection see WIDTH EXPANSION Section and Figure 9.
Figure 11. Compound FIFO Expansion

....----Re
1-----~EFe

I-----~ XoB (TO (XI) OF THE SAME DEVICE)

SYSTEM A

SYSTEM B

De O- 8

R A - - - -. . .
(TO

IDT
7M205/6

....----we

(Xi) OF THE SAME DEVICE) XoA ....: - - - - - - 1
EFA ...- - - - I

Figure 12. Bidirectional FIFO Mode

13-165

IDT7M20SS/IDT7M206S CMOS PARALLEL
IN-OUT FIFO MODULE 8Kx 9-BIT & 16Kx 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DATA IN

W

3V

OV

11

OV
~

DATA OUT

NOTE:

1.

tRPE = tRPW

Figure 13. Read Data Flow-Through Mode

3V

OV

OV

DATA OUT

~J

---....-oi~DATAOUT VALID '@~--------

Figure 14. Write Data Flow-Through Mode

13-166

IDT7M205S/IDT7M206S CMOS PARALLEL
IN-OUT FIFO MODULE 8Kx 9-BIT & 16Kx 9-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

DeV~pe

A

A

Package

Processl
Temperature
Range

y:~k
~--------------~C

'-----------I

~

70 }
85
120

L-------------------------------~S
~

______________________________________

~7M205

7M206

13-167

Commercial (O°C to

+70°C)

Militruy -55°C to + 125°C
Compliant to MIL-STD-883, Class B

Sidebraze DIP

Speed in Nanoseconds

Standard Power
8Kx 9-Bit
16Kx 9-Bit

FEATURES:

DESCRIPTION:

• High-density 1024K-bit (128K x 8-bit) CMOS static RAM
modules with registeredlbuffered/latched addresses and I/Os
• High-speed registered access time:
- Military temperature range: SOns (max.)
- Commercial temperature range: 50ns (max.)

The IDT7M824 family is a set of 1024K-bit (128K x 8-bit) highspeed CMOS static !;lAM modules with registered/buffered/
latched addresses and I/Os. They are constructed on co-fired,
multi-layered ceramic substrates with sidebrazed leads using
16 IDT71981 (16K x 4) static RAMs, lOT logic devices and decoupiing capacitors. Devices in leadless chip carriers are mounted top
and bottom for maximum density.
Extremely high speeds are achievable by the use of IDT71981s
and logiC devices fabricated in lOT's high-performance, highreliability CEMOS ™ technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides the
fastest circuits possible. The IDT7M824 has registered access
times of 50ns (max.) over the commercial temperature range and
can be operated with cycle times as fast as 20MHz.
Designing with this device can be very flexible because of such
features as module select output and clock enables on all registers, registered write enable and 8-bit separate inputs and outputs.
Because of the proprietary IDT49C801, the modules are cascadable in terms of depth with no additional external decoding.
The write enable can be turned off when the module is deselected.
Immunity to noise has been extended with such features as 8-bit
separate inputs and outputs; addresses, inputs, and outputs on
separate clocks; internal decoupling capacitors; five ground pins
and five Vee pins.
The semiconductor components used on all lOT military modules are manufactured in/compliance with the latest revision of
MIL-STD-883, Class B, ma}I

Min. = 4.50V

Max. = 5.50V (Military)

=

SYMBOL

TEST CONDITIONS (1)

PARAMETER

MIN.

TYP.(2)

MAX.

UNIT

-

V

\'IH

Input HIGH Level

Guaranteed Logic High Level

2.0

\'IL

Input LOW Level

Guaranteed Logic Low Level

IIH

Input HIGH Current

Vee = Max.• VIN =\tc

IlL

Input LOW Current

Vec = Max., VIN = GND

-

-

-5

jJA

Isc

Short Circuit Current

Vec=MaxP)

-50

-120

-

mA

-

Output HIGH Voltage

Vcc = Min.
VIN = \'IH or\'lL
Vce = 3V, \'IN

VOL

Output LOW Voltage

Vee

VHC

Vec

IoH = -12mA MIL.

2.4

4.3

IoH= -15mA COM'L.

2.4

4.3

-

-

GND

VLC

GND

VLe

-

0.4

-

300

600

mA

-

320

650

mA

-

15

330

mA

IoL = 300jJA
IoL = 32mA MIL.

"'IN = "'IHor"'lL

IoL = 48mA COM'L.
ICCl

Operating Power Supply Current

ICC2

Dynamic Operating Current

ISB

Standby Power Supply Current

CS = VIL

Vcc = Max., Output Open
f = 0

CS = VIL

Vcc= Max., Output Open
f = fMAX

CS:2: VIH

Vcc= Max.
Output Open, f = fMAX

NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

13-170

jJA

VHC

= VLC or VHe , 10L = 3ooj.iA

Vcc = Min.

V

5

IoH= -3OOjJA

Vcc = 3V, \'IN = VLC or VHC ' 10H = -32j.iA
VOH

0.8

-

V

V

0.5

IDT7M824 FAMILY 1 MEGABIT (128Kx 8) REGISTERED/BUFFERED/
LATCHED CMOS STATIC RAM SUBSYSTEMS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

that meets the required set-up time is latched. The WE input is not
latched but it is gated by the result of the three chip select inputs.
With the IDT49C801 in the Register mode, the three address and·
chip select inputs are registered by a 377-type register. All data that
meets the set-up time requirements before the rising edge of CP
will be transferred to the output of the register provided Clock Enable (CE) is asserted. In this mode, WE is also registered but the
output of its register is gated with CP so that when CP goes low, the
output of WE is applied to the RAMs.

IDT49C801
REGISTERED/LATCHED DECODER
The IDT49C801 is a proprietary IDT gate array that includes a
138-type 1-of-8 decoder, as well as latches and registers for all inputs and controls for WRITE ENABLE ( WEi l l e latch or register
mode is controlled by a single input, REG/tAT.
With the IDT49C801 in the Latch mode, the three address and
the three chip select inputs are latched by a 373-type latch. When
LE is high, the latch is transparent and, when LE goes low, all data

r-----------------------------,

I

....,r-t-+--+-~~-l

I

D

Q

'373
LATCH
LE

A
B
A

MUX

B

D

Y

J-;.I~-+-l

s

Q

CS1
CS2

'377
REG

CP

'138
01
TYPE
0
DECODER

C

cr

CS3

0:

04
05
06
~

SIT

REG/CAT ~~~+--+~----------------__--------~

~ _----+11.....-+-+--1

~I

D

Q

'377
REG
CP

B

I
I

I
I

cr

I
IDT49C801
L _____________________________
-lI

IDT49C802

these parts. The purpose of the pull-down resistor, as used in these
parts, is to prevent the RAM DO pins from floating when the RAM
array is deselected. When the RAM array is selected, the pull-down
resistor is inhibited. The value of the resistors is approximately
15Kn.

UNIVERSAL PULL-UP/DOWN RESISTORS
The IDT49C802 is a proprietary gate array that has 18 selectable
pull-up or pull-down resistors, only eight of which are used on

Ro-R17

13-171

DATA IN is controlled by its own enable, LEDIN. With this line in
the high state, the latch Is in the transparent or buffer mode. All
DATA IN that meets the specified set-up time will be latched when
LEDIN goes low. PREDIN and CLRDIN are asynchronous controls
that can be used to preset or clear the DATAIN latch. The preset
function overrides the clear so that, with both asserted, the latch
will be preset.
DATA OUT is controlled by its own enable, LEDOUT. With this
line in the high state, the latch is in the transparent or buffer
mode. DATA OUT of the RAM array that meets the set-up time
reguirements will be latched when LEDOUT goes low.
PREDOUTand CLRDOUT are asynchronous controls that can be
used to preset or clear the DATA OUT latch. The preset function
overrides the clear so that, with both asserted, the latch will be
preset. There are three active low output enables for DATA OUT.
Unless all three of these lines are asserted, the output will be in the
high impedance state.
The SEL signal is an output that can be used to monitor the state
of the internal RAM array output bus.

FEATURES:
• Latched and buffered address lines
• Latched and buffered input data lines
• Latched and buffered output data lines
• Separate I/O
• High-speed access time:
- Military temperature range: 55ns (max.)
- Commercial temperature range: 45ns (max.)
• 20MHz read/write cycle time

DESCRIPTION:
The IDT7M820 Is a 128K x 8 RAM with latched address, latched
DATA IN and latched DATA OUT lines. Each of the three buses has
its own Latch Enable (LE) , allowing the latch to be used as a buffer
by connecting the appropriate LE to Vee.
Address, Write Enable and the three chip select lines are controlled by LE. When LE Is high, the address latches and decoder
a~ transparent, or in the buffer mode. All address, Chip Select
(CS) and Write Enable (WE) data that meets the specified set-up
time will be latched when LE goes low.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

AD (0' 13)
GND
Ao
At
A2
A3
GND
A4
As
Ae
A7
GND
As

WE'
"C"St
"C"S2

GND

eS 3

GND
GND

crnt5TN
LEDIN
GND
~

010
Dl t
0 12
DI3
01 4
Dis
Ole
01 7
GND

1
2

Vee

3
4
5
6

Ato
All
At2

I
I

Ag

Vee

7

M8

Vee

PREDOOT

18
19

LEOOUT

20
21
22
23
24
25
26
27
28
29
30
31
32

'OE"2
'OE"t

DIP
TOP VIEW

CLRDOOT

004
DOs

-"

RAM 3

wrn

A (14: 16) - Ao-2

~

~
...:!!!..

-"

RAM 6

DECODER

RAM 9

RAM 11
RAM 12

RAM 5

I

RAM 13

16 x IDT719
t16K x 4s
S ATIC RA
ARRAY

RAM 14

RAM 7

-"

RAM 15

RAM 8

-"

RAM 16

CSt

~2
CS3

00-7

RAMSEL
(0:7)

WE
R/[

~

002
DCa

RAM 2

LE

'OE"

Vee

000
DOt

~

,.. RAM 10

RAM 4

Vee
LE
GNO
GNO
'OE"3

RAM 1

A (0: 13) - DO-t3 00-t3

At3
At4
At5
Ate

8
9
10
11
12
13
14
15
16
17

14-BIT
LATCH

GND
~

t

~

GNO

JY(0:7)

1

~

I
: PULLUP

GNO
LE

DOe
007
Vee

0(0:7)

LE

I

00-7
LE J5RE"

Do-> LATCH

yo-,~ D~

LE J5"R"E". crR
01 (0:7)

LEtlN

I

i~

~

LATCH

Y0-7

crR "ET "E2

DO (0: 7)

~

LEOOUT

'OE"3

PREDout
CLRDOOT

'OE"t

'OE"2

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© t967 Integrated DevIce Technology. Inc.

DECEMBER 1987
DSC-70001-

13-172

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M820 1 MEGABIT (128Kx 8) CMOS STATIC RAM SUBSYSTEM

AC"TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V

5V

.

GND t03.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATA OUT

~

2550

4800
DATA OUT

~

2550

30pF

Figure 1. Output Load

4800

5pF*

Figure 2. Output Load
(for t oHZ )

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vce = 5V±10%, TA =ooe to

PARAMETER

IDT7M820S45
(eOM'L ONLy)
MIN.
MAX.

+ 70 0 e and -55°e to + 125°C)
IDT7M820S55

1-'

IDT7M820S70
UNIT

MIN.

MAX.

MIN.

MAX.

READ CYCLE
tAA

Address, ~ Access Time

-

45

-

55

-

70

ns

t ADS

Address, ~ to LE Set-up Time

2

2

2

-

ns;,

Address, ~ from LE Hold Time

-

2

tADH

-

t LEOO (2)

DATAoUT Latch Enable from Address, ~

-

36

55

ns

tOE
t OHZ (3)

OE' to Data Valid

-

8

15

ns

OE'to High Z

-

7

-

15

ns

31

-

ns

2

3

9

-

9

-

41

-

55

37

-

50

40

ns

WRITE CYCLE

cg to End of Write

tAW

Address,

twp

Write Pulse Width

27

tADS

Address, ~ to LE Set-up Time

2

-

tADH

Address, ~ from LE Hold Time

2

-

2

tDw

Data Valid to End of Write

26

-

36

2

NOTES:
1. WE Must be high for read cycles.
2. Latch Enable signal arriving after this maximum wIll delay overall access time (tAA)
3. Transition is measured -200mV from steady state voltage with specified loading in Figure 2.

13-173

-

2
3
50

ns
ns
ns
ns

IDT7M820 1 MEGABIT (128K x 8) CMOS STATIC RAM SUBSYSTEM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE

ADDR.

ADDRVALID

'C"S

tADH

LE

LEDOUT

t LEDO

tAA

tOHZ

tOE

DATA OUT

TIMING WAVEFORM OF WRITE CYCLE

ADDR.

CS

'"JI\
I-

LE

'II

ADDRVALID
t ADs

,

JI\

tADH

1\
tAw

VIr=.

twp

LEDIN

DATA IN

*
13-174

DATA VALID

\

Address, Write Enable (WE) and the three Chip Select (CS)
lines are controlled by LE. When LE is 'high, the address latches
and decoder are transparent or in the buffer mode. All address, CS
and WE data that meets the specified set-up time will be latched
when LE goes low.
DATAIN is controlled by its own clock, CPDIN. When ENDIN
(clock enable) is asserted, all DATA IN data that meets the specified set-up time will be registered on the rising edge of CPDIN.
CLRDIN is an asynchronous control that can be used to clear the
DATA IN register.
DATA OUT is controlled by its own enable, CPDOUT. When
ENDOUT (clock enable) is asserted, all data out of the RAM array
that meets the set-up time requirements will be registered on the
rising edge of CPDOUT. CLRDOUT is an asynchronous control
that can be used to clear the DATA OUT register. There are three
active low output enables for DATAoUT. Unless all three of these
lines are asserted, the output will be in the high impedance state.
The SEL signal is an output that can be used to monitor the state
of the internal RAM array output bus.

FEATURES:
• Latched/buffered address lines
• Registered input data lines
• Registered output data lines
• Separate I/O
• High-speed access time:
- Military temperature range: 55ns (max.)
- Commercial temperature range: 45ns (max.)
• 20MHz read/write cycle time

DESCRIPTION:
The IDT7M821 is a 128K x 8 RAM with latched address, registered DATAIN and registered DATA OUT lines. The address latch
can be used as a buffer by connecting its Latch Enable LE to Vee.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

AD (0: 13)
GND
Ao
At
A2
A3
GND
A4
As
Ae
A7
GND
A8

WE
CSt
CS2

GND
CS3
GND
GND

COtl5I"N
CPDIN
GND

ENl5lN
Dlo
DI1
DI2
DI3
DI4
Dis
Die
DI7
GND

1

Vee

2

A9

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

AlO
Att
At2
Vee
At3
At4
Ats
Ate
Vee
LE
GND
GND
'C5E"3
M8

Vee

rnr50UT
CPOUT

CLADOUT
0E2

I
I

14-BIT
LATCH

22

Vee

'SIT
DOc
DOt
D02
D03
D04
DOs

28

29
30
31
32

LE
L-..

I

wrn

A (14: 16) - Ao-2

RAM 13

RAM 6

RAM 14

RAM 7

RAM 15

RAM 8

RAM 16

16 x IDT71
t16KX4S
S ATIC R
ARRAY

RA~5~~

"CSt
0 0- 7

"CS2
CS3

~ WET

D (0: 7)

SEI

R/[
GND

srr

f

Iy

LE

GND

1

t--

I
: PULL UP

GND
LE

DOe

DOr
DO-7

Vee

REGISTER

DI (0:7)

rn ern

CP~IN

i

CL!DIN
ENDIN

(0:7)

I

+__

Yo-7

CP

DIP

TOP VIEW

RAM 12
,.

RAM 5

DECODER

RAM 10
RAM 11

RAM 3
RAM 4

DE"

'C5E" t

23
24
25
26
27

RAM 9

,.

RAM 2

A (0: 13) - Do-t3 00-t3

~
~
~

I

RAM 1

Do-7
CP EN

CPD~

~

CLADOuT

REGISTER

YO- 7

DO

ern 'ET E2 E3

(O:7)1H)

~3

'C5E"2
~t

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© t987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-7ooo/-

13-175

IDT7M821 1 MEGABIT (128K x 8) CMOS STATIC RAM SUBSYSTEM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
Input Pulse levels
Input Rise/Fall Timss
Input Timing Reference levels
Output Reference levels
Output load

5V

5V
GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATA OUT

~

2550

480Q
DATA OUT

~

2550

30pF

4800

5pF*

Figure 2. Output Load
(for tOHZ)

Figure 1. Output Load

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS

(Vce = 5V±10%, TA = ooc to

PARAMETER

SYMBOL

IDT7M821S45
(COM'L ONLy)
MIN.
MAX.

+ 70°C and -55°C to + 125°C)
IDT7M821 S55

IDT7M821 S70
UNIT

MIN.

MAX.

MIN.

MAX.

READ CYClE(1)
Address, ~ Access Time

45

55

/l-

70

ns

Address, ~ to lE Set-up Time

2

2

Address, ~ from lE Hold Time

2

2

DATAoUT Clock from Address, ~

36

45

57

ns

t EOS

DATAoUT Clock Enable to Clock Set-up Time

3

3

3

ns

DATAoUT Clock Enable from Clock Hold Time

o

tOE

rn: to Data Valid

8

9

15

ns

rn:to High Z

7

9

15

ns

DATAoUT Clock to Data Valid

8

10

13

ns

t CPD

o

2

ns

3

ns

2

ns

WRITE CYCLE
Address, ~ to End of Write

31

45

55

ns

Write Pulse Width

27

35

45

ns

Address, ~ to lE Set-up Time

2

2

2

ns

Address, ~ from lE Hold Time

2

2

3

ns

DATAIN Clock Enable to Clock Set-up Time

3

3

3

ns

DATAIN Clock Enable from Clock Hold Time

.0

o

2

ns

DATAIN to DATA IN Clock Set-up Time

3

5

5

ns

DATAIN from DATA IN Clock Hold Time

2

2

3

ns

DATAIN Clock to End of Write Cycle
31
27
tcow
NOTES:
1. WE' Must be high for read cycles.
2. Transition is measured -200mV from steady state voltage with specified loading in Figure 2.

40

ns

13-176

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M8211 MEGABIT (128Kx 8) CMOS STATIC RAM SUBSYSTEM

TIMING WAVEFORM OF READ CYCLE

ADDR,CS, WE

''I

I+-

"

ADDRVALID

/~

,

tADS

LE

j\

t ADH -

~

CPDOUT

,

tCPO

J
t EDS
t EDH -

!

, "
\

'I

~

J

tOE

:--

~

~.•.••..

DATA OUT

t CPD

,

I--

,

DATA VALID

tOHZ

J

tAA

TIMING WAVEFORM OF WRITE CYCLE

ADDR,

CS

''I
I~

"

ADDRVALID

~tADs

LE

,

J~

tADH

~

I.

tAW

~

twp

tCDW

CPDIN

13-177

f

CS and WE data that meets the specified set-up time will be
latched when LE goes low.
DATA IN is controlled by its own clock, CPDIN. When ENDIN
(clock enable) is asserted, all DATAIN data that meets the specified set-up time requirements will be registered on the rising edge
of CPDIN. CLRDIN is an asynchronous control that can be used to
clear the DATA IN register.
DATA OUT is controlled by its own enable, LEDOUT. With this
line in the high state, the latch is in the transparent or buffer mode.
Data out of the RAM array that meets the set-up time requirements
will be latched when LEDOUT goes low. PREDOUT and
CLRDOUT are asynchronous controls that can be used to preset or
clear the DATA OUT latch. The preset function overrides the clear so
that, with both asserted, the latch will be preset. There are three active low output enables for DATA OUT • Unless all three of these lines
are asserted, the output will be in the high impedance state.
The SEL signal is an output that can be used to monitor the state
of the internal RAM array output bus.

FEATURES:
• Latched and buffered address lines
• Registered input data lines
• Latched and buffered output data lines
• Separate I/O
• High-speed access time:
- Military temperature range: 55ns (max.)
- Commercial temperature range: 45ns (max.)
• 20MHz read/write cycle time

DESCRIPTION:
The IDT7M822 is a 128K x 8 RAM with latched address, registered DATA IN and latched DATA OUT lines. The address and
DATAIN latches have independent latch enables (LE) allowing the
latch to be used as a buffer by connecting its Latch Enable LE to

Vee.
Address, Write Enable (WE) and the three Chip Select (CS)
lines are controlled by LE. When LE is high, the address latches
and decoder are transparent or in the buffer mode. All address,

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

AD (0: 13)
GNO
Ao

Vee

Al

Al0

A2

A11

A3
GNO

Vee

I

A9
A12

14-BIT
LATCH
A (0: 13) - 00-13 00-13

A13

A4
A5

~

A14
A15

Ae

Vee

A8

LE
GND
GND

~

"C'S1
"C'S2

CJE3

GNO
CS3
GNO
GNO

Vee

PREDOUT
LEDOUT

CLRDOUT
CJE2
CJEl

comTf\J
CPDIN
GNO

~

010
011
0 12
01 3
01 4
01 5
Ole
01 7
GNO

000
DOl
002

0D3

D04
D0 5

L--

DECODER
WEO

A (14: 16) - Ao-2

~

7~

~

RAM 10

RAM 3

RAM 11

RAM 4

RAM 12

RAM 5

RAM 13

RAM 6

RAM 14

RAM 7

RAM 15

RAM 8

RAM 16

16 x 10T71981
.p6K x 4s)
S ATIC RA M
ARRAY

0 0- 7

CS3

WET

D (0:7)

R/[
GNO
~

t

LE

GNO

IY(0:7)

1

I

~

I PULLUpJ

GND
LE

D~

'r-cp~

00-7
LE ~

DOe

LATCH

YO- 7

DO (0: 7)

CI:R 'ET E2 E3

0 0- 7REGISTERYO- 7

Vee
DIP
TOP VIEW

RAM 9

RAM 2

RA~~~~

CSl
CS2

~

Vee

EJW1N

LE

I

Ale

A7
GNO

I
I
RAM 1

rn

CP
01 (0: 7)

CP~IN

CI:R

1CL~DIN

rnrnN

PREDOUT
CLRDOUT

~3

0E"2
~1

CEMOS is a trademark of Integrated OevieeTechnology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
ose-7000/-

13-178

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M8221 MEGABIT (128Kx 8) CMOS STATIC RAM SUBSYSTEM

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V

5V
GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATA OUT

~

2550

4800
DATA OUT

~

2550

30pF

4800

5pF*

Figure 2. Output Load
(for t OHZ )

Figure 1. Output Load

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc = 5V±10%, TA =O°C to

PARAMETER

IDT7M822S45
(COM'L. ONLy)
MAX.
MIN.

+ 70°C and -55°C to + 125°C)
IDT7M822S55

IDT7M822S70
UNIT

MIN.

MAX.

MIN.

MAX.

READ CYCLE(1)

-

45

-

55

-

70

ns

2

2

-

2

-

ns

2

-

2

-

3

-

ns

DATAoUT Latch from Address, CS

-

36

-

40

-

55

ns

GE to Data Valid

-

8

-

9

-

15

ns

7

-

9

-

15

ns

55

CS Access Time

tM

Address,

tAOS

Address, CS to LE Set-up Time

tADH
t LEOO (2)

Address,

tOE
t OHZ (3)

CS from

LE Hold Time

GEto High Z

WRITE CYCLE
tAW
. twp

2

-

2

-

2

-

2

-

3

-

DATAIN Clock Enable to Clock Set-up Time

3

-

ns

2

-

ns

3

5

-

ns

2

-

2

-

3

0

-

3

DATAIN Clock Enable from Clock Hold Time

3

-

ns

40

-

ns

Address, CS to End of Write

31

-

45

Write Pulse Width

27

-

35

CS to LE Set-up Time
CS from LE Hold Time

tAOS

Address,

tADH
t EDS

Address,

tEDH
tos

DATAIN to DATA IN Clock Set-up Time

tOH

DATAIN from DATAIN Clock Hold Time

0
3

31
DATAIN Clock to End of Write Cycle
27
tcow
NOTES:
1. ~ Must be high for read cycles.
2. Latch Enable signal arriving after this maximum will delay overall access time (tAAJ.
3. Transition is measured -200mV from steady state voltage with specified loading in Figure 2.

13-179

45
2

ns
ns
ns
ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7MB221 MEGABIT (128KxB) CMOS STATIC RAM SUBSYSTEM·

TIMING WAVEFORM OF READ CYCLE

-

ADDR.

ADDRVALID

CS

-.1--- t ADH - - - - 1
LE

LEDOUT

104---- t LEOO - - - W
1 0 4 - - - - - - tAA

------.1

DATAoUT

TIMING WAVEFORM OF WRITE CYCLE

ADDR. CS

ADDRVALID

_014---- tADH --~
LE

CPDIN

DATA IN

13-180

DATA IN is controlled by its own enable, LEDIN. With this line in
the high state, the latch is in the transparent or buffer mode. All
DATA IN data that meets the specified set-up time will be latched
when LEDIN goes low. PREDIN and CLRDIN are asynchronous
controls that can be used to preset or clear the DATA IN latch. The
preset function overrides the clear so that, with both asserted, the
latch will be preset.
DATA OUT is controlled by its own clock, CPDOUT. When
ENDOUT (clock enable) is asserted, all data out of the RAM array
that meets the set-up time requirements will be registered on the
rising edge of CPDOUT. CLRDOUT is an asynchronous control
that can be used to clear the DATA OUT register. There are three active low output enables for DATA OUT • Unless all three of these lines
are asserted, the output will be in the high impedance state.
The SEL signal is an output that can be used to monitor the state
of the internal RAM array output bus.

FEATURES:
•
•
•
•
•

Latched and buffered address lines
Latched and buffered input data lines
Registered output data lines
Separate I/O
High-speed access time:
- Military temperature range: 55ns (max.)
- Commercial temperature range: 45ns (max.)
• 20MHz read/write cycle time

DESCRIPTION:
The IDT7M823 is a 128K x 8 RAM with latched address, latched
DATA IN and registered DATA OUT lines. The address and DATA OUT
latches have independent latch enables, allowing the latch to be
used as a buffer by connec~ its Latch Enable (LE) to Vee. _
Address, Write Enable (WE) and the three Chip Select (CS)
lines are controlled by LE. When LE is high, the address latches
and decoder are transparent, or in the buffer mode. All address,
CS and WE data that meets the specified set-up time will be
latched when LE goes low.

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM
AD (0: 13)

GNO

1

Ao

Vee

2
3
4
5

Ag

Al
A2

A3
GNO
A4
A5

As
A7
GNO
As

WrE

~1
~2

GNO
CS3
GNO
GNO

~

LEDIN
GNO

l5"FfEtm\l
010
011
012
01 3
01 4
01 5
Dis
01 7
GNO

Al0
All
A12

6

Vee

7
8
9
10

A13

A1S

11

Vee

12
13

LE
GNO
GNO

I

A (0: 13) - 00-13 00-13

A14

O"E'

A15

14
15
16
17

I
14-BIT
LATCH

·~3

M8

18
19
20
21
22

23
24
25
26
27
28
29
30

31
32

DIP
TOP VIEW

Vee
ENOOUT
CPOUT

CLRDOOr

~2
~1

I
DECODER
A (14: 16) - Ao-2
wrn

~
~
~

004
005

RAM 10

RAM 3

RAM 11

RAM 4

RAM 12

RAM 5

RAM 13

RAM 6

RAM 14

RAM 7

RAM 15

RAM 8

RAM 16

16x 10T?1
.p6KX 4s
S ATICRA
ARRAV

00-7

~2

CS3

~ WET

0(0: 7)

S"E[
LE
R/[ GNO

S"E[

0D3

RAM 9

RAM 2

RA~5:~

~l

Vee

000
001
002

LE

RAM 1

GNO
S"E[

f

1

JV(O:7)

~

I
PULL UP

GNO
LE

DOe

007

Vee

LATCH

00-7

LE 1'l!E
01 (0: 7)
LEblN

+__

V0-7

-ern

1CL~OIN

l5"FfEtm\l

I
REGISTER
V0-7
00-7
CP EN 'COt ~ ~ n

DO (0: 7)

CP~

~3

ENI50UT
CLRDOOr

~1

~2

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated Devtce Technology. Inc.

DECEMBER 1987
DSC-70001-

13-181

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M823 1 MEGABIT (128K x 8) CMOS STATIC RAM SUBSYSTEM

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

-.--f

5V

5V
GND to 3.0V
10ns
1.5V
1.5V
'See Figures 1 and 2

DATA OUT

~

255Cl

480Cl

4800

DATA~2550~5PF'

30pF

Figure 1. Output Load

Figure 2. Output Load
(for t oHZ )

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc = 5V±10%, TA =O°C to

PARAMETER

IDT7M823S45
(COM'L ONLy)
MAX.
MIN.

+ 70°C and -55°C to + 125°C)
IDT7M823S55

IDT7M823S70
UNIT

MIN.

MAX.

MIN.

MAX.

READ CYCLE(1)
tAA

Address,

-

45

-

55

-

70

ns

tAOS

Address,

2

-

2

2

-

ns

2

-

3

-

57

-

ns

45

-

3

-

3

-

ns

0

-

2

-

ns

8

-

9

ns

9

-

15

7

15

ns

8

-

10

-

13

ns

41

55

-

ns

50

ns

2

-

tcpo

CS Access Time
CS to LE Set-up Time
Address, CS from LE Hold Time
DATAoUT Clock from Address, CS

36

t EDS

DATAoUT Clock Enable to Clock Set-up Time

3

t EOH

DATAoUT Clock Enable from Clock Hold Time

0

tOE

ot: to Data Valid

t OHZ (2)

ot:to High Z

tepo

DATAoUT Clock to Data Valid

-

tADH

2

ns

WRITE CYCLE
tAW

Address,

twp

Write Pulse Width

27

-

37

tAOS

Address, ~ to LE Set-up Time

2

-

2

-

t AOH

Address,

2

-

2

-

3

-

ns

tow
Data Valid to End of Write
26
36
NOTES:
1.
Must be high for read cycles.
2. Transition is measured -200mV from steady state voltage with specified loading in Figure 2.

-

50

-

ns

CS to

End of Write

CS from LE Hold Time

31

wr:.

13-182

ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M8231 MEGABIT (128K x 8) CMOS STATIC RAM SUBSYSTEM

TIMING WAVEFORM OF READ CYCLE

ADDR, CS,

wr=.

'If

~V

ADDRVALID

jr\.

~tADS

,

LE

JI\

tADH

1\

CPDOUT

f

tcpo

j
t EDS
t EDH -

\

,

jV

\

'I

t\

j

tOE
~

~ t CPD

I--

I

DATA VALID

DATAoUT
tAA

TIMING WAVEFORM OF WRITE CYCLE

ADDR, CS

'II
JI\
1+ tADS

LE

~V

ADDRVALID

,

)1\

tADH

1\
tAW

wr=.

twp

LEDIN

DATA IN

*
13-183

DATA VALID

~

)

tOHZ

\

Address, Write Enable (WE) and the three Chip Select (CS)
lines are controlle@y CPo When CE (clock enable) is asserted, all
address, CS and WE data that meets the specified set-up time will
be registered on the rising edge of CPo
DATAIN is controlled by its own clock, CPDIN. When ENDIN
(clock enable) is asserted, all DATAIN data that meets the specified set-up time will be registered on the rising edge of CPDIN.
CLRDIN is an asynchronous control that can be used to clear the
DATAIN register.
DATA OUT is controlled by its own clock, CPDOUT. When
ENDOUT (clock enable) is asserted, all data out of the RAM array
that meets the set-up time reqUirements will be registered on the
rising edge of CPDOUT. CLRDOUT is an asynchronous control
that can be used to clear the DATA OUT register. There are three active low output enables for DATA OUT • Unless all three of these lines
are asserted, the output will be in the high impedance state.
The SEL signal is an output that can be used to monitor the state
of the internal RAM array output bus.

FEATURES:
• Registered address lines
• Registered input data lines
• Registered output data lines
• Separate I/O
• High-speed access time:
- Military temperature range: 60ns (max.)
- Commercial temperature range: 50ns (max.)
• 20MHz read/write cycle time

DESCRIPTION:
The IDT7M825 is a 128K x 8 RAM with registered address, registered DATA IN and registered DATA OUT lines. Each of the three
buses has its own Independent clock.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

AD (0: 13)

Vee'

GND

I

Ag

Ao
Al
A2
A3
GND

I

Al0
All
A12

Vee
A13

A4
A5

14-BIT
REGISTER

A (0: 13) -

A14
A15

Ae
A7
GND
As

Do- 13 00-13
~

Ale

Vee

~3

GND

Vee
rnoouT

CS3
GND
GND

CPDOUT

CLADOOr

~

nl:2
nl:l

CPDIN
GND

DECODER

~
~
~

DOo

Dll
DI2

DOl

DI 3
DI4
DI5

DD3

004
D05

Die
DI7
GND

DOe
DCr
Vee

D02

RAM 9

--

RAM 10

RAM 3

~

.r

RAM 11

RAM 4

~

.r

RAM 12

RAM 5

RAM 13

RAM 6

h--- 1-..£ RAM 14

RAM 7

~

RAM 15

RAM 8

~

RAM 16

16 x IDT719
.p6K x 4s
S ATIC RA
ARRAY

CSl
00-7

CS2

RAMSEL
(0: 7)

CS3

~ WEl

D (0:7)

~
CP
R/[
~

~

Dlo

WEO

A (14: 16) - Ao-2

Vee

rnI5TN

CP

I

CP

WE

"'"

RAM 2

Vee

CSl
CS2

I

RAM 1

Vee
~

f

1

IY(0:7)

~

I
: PULL UP

~

REGISTER

CP

+__

o0-7REGISTER Yo0-7

DIP

EN crR

CP

TOP VIEW
DI (0: 7)

I

CptDIN

f cJmm.

rnI5TN

DO-7
CP EN

~
CPDOUT

YO- 7

DO (0:7)

crR 'ET 'E2 E3
nl:3

~

0E"2

CLRDOOr

nl:l

CEMOS is a trademark of Integrated Device Technology: Il')c.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
DSC-7000/-

13-184

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M8251 MEGABIT (128K x 8) CMOS STATIC RAM SUBSYSTEM

AC TEST CONDITIONS

5V
GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

~

DATA OUT

2550

5V

4800
DATA OUT

~

2550

30pF

4800

5pF*

FIgure 2. Output Load
(for t OHZ )

Figure 1. Output Load

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS

(Vcc = 5V±10%, TA =O°C to

PARAMETER

SYMBOL

+ 70°C and -55°C to + 125°C)

IDT7M825S50
(COM'L ONLy)
MAX.
MIN.

IDT7M825S60

IDT7M825S70

MIN.

MAX.

MIN.

UNIT
MAX.

READ CYCLE(1)
t RCC

Min. Clock to Clock Time

40

-

50 "---

-

60

-

ns

t ACp (2)

Address, CS Clock to Data Valid

-

48

-

58

-

67

ns

tADS

Address,

2

2

-

ns

Address, CS from Address Clock Hold Time

2

2

-

3

tADH

3

-

ns

t CES

Address Clock Enable to Address Clock Set-up Time

2

-

2

-

3

-

ns

tCEH

Address Clock Enable from Address Clock Hold Time

2

2

-

ns

DATAoUT Clock Enable to DATAoUT Clock Set-up Time

3

3

5

-

ns

tEDH

DATAoUT Clock Enable from DATAoUT Clock Hold Time

0

-

0

-

5

t EDS

-

3

-

ns

tOE

Output Enable to Output Data Valid

8

ns

18

ns

tcpo

DATA OUT Clock CPDOUT to Data Valid

-

20

Output Enable to Output in High Z

-

9

t OHZ (3)

-

15

ns

45

-

60
35

-

ns

30

-

ns

-

ns

cs to Address Clock Set-up Time

7
8

8

9

WRITE CYCLE
tAW

Write Cycle Time

35

t CWPL

Address Clock Low Pulse Width

20

t CWPH

Address Clock High Pulse Width

7

-

tADS, t wES

Address, CS,

wr=. to Address Clock Set-up Time

2

-

2

-

t ADH , tWEH

Address, CS,

wr:. from Address Clock Hold Time

2

-

2

-

3

t cEs

Address Clock Enable to Address Clock Set-up Time

2

-

2

-

3

tCEH

Address Clock Enable from Address Clock Hold Time

2

-

2

-

3

t EDS

DATAIN Clock Enable to DATAIN Clock Set-up Time

3

3

-

5

tEDH

DATAIN Clock Enable from DATAIN Clock Hold Time

0

0

-

3

tos

DATAIN to DATA IN Clock Set-up Time

3

3

DATAIN from DATA IN Clock Hold Time

2

-

5

tOH

-

DATAIN Clock to End of Write Cycle
27
tCDW
NOTES:
1.
Must be high for read cycles.
2. Assumes min tRce is observed.
3. Transition is measured -200mV from steady state voltage with specified loading in Figure 2.

wr:.

13-185

10

2
35

10
3

3
50

ns
ns
ns
ns
ns

ns

ns
ns
ns

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M825 1 MEGABIT (128K x 8) CMOS STATIC RAM SUBSYSTEM

TIMING WAVEFORM OF READ CYCLE
'"

ADDR,CS, ~

j~

ADDR VALID

'II
)1\.

tAOS ~

,r+1/

CP

tCES'

t AOH -

tCEH7

1\

j

CPDOUT

II

t EDS
t EOH -

,

!

"
\.

tRCC

,

1/

~

~

DATAoUT

r-:::

\.

f--

tcpo

DATA VALID

,

tOHZ

~

t AcP
tM

TIMING WAVEFORM OF WRITE CYCLE
tAW

ADDR, CS

~II

~II

ADDRVALID

)1\

----'1\
t CWPH

tAOS

CP

)

t

V

,"..1

t CWPL

,
i\

~

t AOH

1--1c

t WES

\

\

tWEH-i
tcow

II

CPDIN
)
\. t EOS

\
j4- t os -

'LI
)1\

13-186

tEOH-f

~tOH-

DATA VALID

'II
)~

V--

Address, Write Enable (WE) and the three Chip Select (CS)
lines are controlleQ.Qy CPo When CE (clock enable) is asserted, all
address, CS and WE data that meets the specified set-up time will
be registered on the rising edge of CPo
DATAIN is controlled by its own clock, CPDIN. When ENDIN
(clock enable) is asserted, all DATAIN data that meets the specified set-up time will be registered on the rising edge of CPDIN.
CLRDIN is an asynchronous control that can be used to clear the
DATAIN register.
DATA OUT is controlled by its own enable, LEDOUT. With this
line in the high state, the latch is in the transparent or buffer mode.
Data out of the RAM array that meets the set-up time requirements
will be latched when LEDOUT goes low. PREDOUTand
CLRDOUT are asynchronous controls that can be used to clear the
DATA OUT latch. The presetfunction overrides the clear so that, with
both asserted, the latch will be preset. Unless all three of these lines
are asserted, the output will be in the high impedance state.
The SEL signal is an output that can be used to monitor the state
of the internal RAM array output bus.

FEATURES:
• Registered address lines
• Registered input data lines
• Latched and buffered output data lines
• Separate I/O
• High-speed access time:
- Military temperature range: 55ns (max.)
- Commercial temperature range: 45ns (max.)
• 20MHz read/write cycle time

DESCRIPTION:
The IDT7M826 is a 128K x 8 RAM with registered address, registered DATA IN and latched DATA OUT lines. The DATA OUT latch can
be used as a buffer by connecting its Latch Enable (LE) to Vee.

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM
AD (a: 13)

GND
Ao

Vee

I

A9
Al0

Al

A2
A3
GND

T

14-81T
REGISTER

All

A12
Vee

A4

A13

As
Ae
A7
GND

A14
A1S

A8

CP

CSl

cr

A {a: 13) - DO-13 0 0 - 13

cr

Ale
Vee

we.

Vee

CS2
GND
CS3
GND
GND

01:3

Vee

PREDOUT
LEDOUT

CLRDOuf
0E"2

crnr5TN
CPDIN
GND

OJ:1

I
DECODER
A {14: 16) - AO-2
wrn

~
~
~
~

Dlo
Dll
DI2
DI3

DOo
DOl

D02
D03
D04

DI4

Dis
Die
DI7
GND

DOs

DOe
DCr

0 0- 7

~

SIT

sa

R/[
Vee

SIT

t

I

cr

..--

I

CP
REGISTER

DO-7
CP
DI

(a: 7)

'C[R"

CP~IN 1CL~DIN
rnr5iN

1

+__

VO-7

rn

RAM 16

Iv (a: 7)

: PULL UP

Vee

RAMS

16x IDT71
t16KX 4s
S ATIC R
ARRAV

D (a: 7)

CP

C1:

DIP
TOP VIEW

RAM 9
RAM 10
RAM 11
RAM 12
RAM 13
RAM 14
RAM 15

RA~~~~

CSl
CS2
CS3

Vee

ENDIN

CP

1

RAM 1
RAM 2
RAM 3
RAM 4
RAM 5
RAM 6
RAM?

DO-7
LE J5"I1E"

LATCH

ern n

VO-7
E2 E3

Do (a: 7)

LED~

OJ:3

PREDOOf

OJ:2

CLRDOOf

OJ:1

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1987 Integrated Device Technology, Inc.

DECEMBER 1987
DSC-7000/-

13-187

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M8261 MEGABIT (128Kx 8) CMOS STATIC RAM SUBSYSTEM

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

5V

5V
GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

~

~4800

.
DATA OUT

2550

DATA~50

30pF

Figure 1. Output Load

*

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(ycc = 5V±10%, TA =O°C to

5pF'

Figure 2. Output Load
(for t OHZ )

Including scope and jig.

+70°C and -55°C to + 125°C)

IDT7M826S45
(COM'L ONLy)
MIN.
MAX.

PARAMETER

L---I

4000

IDT7M826S55

IDT7M826S70

MIN.

MAX.

MIN.

MAX.

UNIT

READ CYCLE(1)
t ACP

Address,

45

-

55

-

70

ns

Address,

2

-

2

-

ns

2

-

2

3

-

ns

t cES

Address Clock Enable to Address Clock Set-up Time

2

-

2

-

3

t AOH

CS Clock to Data Valid
CS to Address Clock Set-up Time
Address, CS from Address Clock Hold Time

-

tAOS

3

-

ns

tCEH

Address Clock Enable from Address Clock Hold Time

2

-

2

-

5

-

ns

t LEDO

DATAoUT LE from Address Clock

tOE

c:5E to Data Valid
c:5E to High Z

t OHZ (2)

-

39

-

46

-

55

ns

-

8

-

9

15

ns

-

7

-

9

-

13

ns

-

60

-

ns

WRITE CYCLE
tAW

Write Cycle Time

35

-

45

t CWPL

Address Clock Low Pulse Width

20

-

30

tCWPH

Address Clock High Pulse Width

7

-

10

tAOS, tWEH

Address,

to Address Clock Set-up Time

2

t AOH , tWEH

CS, M
Address, CS, M

from Address Clock Hold Time

2

t CES

Address Clock Enable to Address Clock Set-up Time

2

tCEH

Address Clock Enable from Address Clook Hold Time

2

t EOS

DATAIN Clock Enable to DATAIN Clock Set-up Time

3

-

t EOH

DATAIN Clock Enable from DATAIN Clock Hold Time

0

-

tos

DATAIN to DATAIN Clock Set-up Time

3

tOH

DATAIN from DATAIN Clock Hold Time

tcow

DATAIN Clock to End of Write Cycle

2
27

NOTES:
1. M Must be high for read cycles.
2. Transition is measured -200mV from steady state voltage with specified loading in Figure 2.

13-188

-

2
2
2
2
3
0
3
2
35

35

ns

3

-

ns

3

-

ns

3

~

ns

3

-

ns

5

-

ns

3

-

ns

5

-

ns

3

-

ns

50

-

ns

10

ns

\

\

IDT1M8261 MEGABIT (128K x 8) CMOS STATIC RAM SUBSYSTEM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE.

ADDR, CS,

''I
A\

WE

J\

t AOH

~~

CP

"

ADDRVALID

j

tCES

~

:------ tCEH -

'I

J

I

t LEDO

I

LEDOUT

,
1\

.~

f+-+
tOE

DATAoUT

1777\.11
,:::.:::::::<::,.,:::

DATA VALID

\.....2..11"

,
J

t AcP
tAA

TIMING WAVEFORM OF WRITE CYCLE
tAW

ADDR, CS

X

'If
J\

ADDRVALID
t CWPH

tAOS

CP

J

t

'I

,

t CWPL

,V--

i\
t AOH

~tCEH

t WES

\

\

tWEH7
tcow

CPDIN

I

'I

\. t Eos
tEDH-f

'\
I+-

''I
j~

13-189

t os -

f--

t DH

DATA VALID

-

'If

I~

address, CS and WE data that meets the specified set-up time will
be registered on the rising edge of CPo
DATA IN is controlled by its own enable, LEDIN. With this line in
the high state, the latch is in the transparent or buffer mode. All
DATA IN data that meets the specified set-up time will be latched
when LEDIN goes low. PREOIN and CLRDlN are asynchronous
controls that can be used to preset or clear the DATA IN latch. The
preset function overrides the clear so that, with both asserted, the
latch will be preset.
DATA OUT is controlled by its own clock, CPOOUT. When
ENOOUT (clock enable) is asserted, all data out of the RAM array
that meets the set-up time requirements will be registered on the
rising edge of CPOOUT. CLROOUT is an asynchronous control
that can be used to clear the DATA OUT register. There are three active low output enables for DATA OUT • Unless all three of these lines
are asserted, the output will be in the high impedance state.
The SEL signal is an output that can be used to monitor the state
of the intemal RAM array output bus.

FEATURES:
• Registered address lines
• Latched and Buffered input data lines
• Registered output data lines
• Separate I/O
• High-speed access time:
- Military temperature range: 60ns (max.)
- Commercial temperature range: 50ns (max.)
• 20MHz read/write cycle time

DESCRIPTION:
The IDT7M827 is a 128K x 8 RAM with registered address,
latched DATA IN and registered DATA OUT lines. The DATA IN latch
can be used as a BUFFER by connecting its Latch Enable (LE) to
Vee.
Address, Write Enable (WE) and the three Chip Select (CS)
lines are controlled by CPo When CE (clock enable) is asserted, all

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

AD (0: 13)

I

Vee

GND

Ao

A9

Al
A2
A3

Al0

GND

Vee

A4

A13
A14
A15

I

14-BIT
REGISTER

A11
A12

As
A6

A7
GND
As

Vee

CS"1
CS"2

CE:

GND

Vee
rnrmoT

A (0: 13) -

00-13

CP
Vee

WE

~3

CS3
GND
GND
C'OmlN
LEDIN
GND

CPOOUT

C[RDOUT
~2
~1

~

Vee
'SEL

010

000

011

001

012

002

01 3

DD3

01 4

004

DIs

005

01 6

RAM 11

RAM 4

RAM 12

RAM 5

RAM 13

RAM 6

RAM 14

RAM 7

RAM 15

RAM 8

RAM 16

L--

Ao-2

A (14: 16) -

WED t-t-t----'

~~1

-=--

16x IDT71981
V6KX 4s)
S ATIC RA M
ARRAV

RAMSEL
(0: 7)

IJ.;)

~ CS"2

~7~~--~~~~~~

~CS3
~WET

0(0: 7)

'SEL

R/[

~

f

CE:

CP

Iv
I...-......-~

1 --

(0:7)

: PULL UP]

CE:

r-

CP

LATCH
0 0- 7
V0-7
CP J5FiE" crR

DIP

TOP VIEW

RAM 3

DECODER

OCr
Vee

GND

RAM 10

CP

I

DOe

01 7

RAM 9

RAM 2

0 0- 13 ....- -...

CE:

A16

RAM 1

01 (0:7)

LEJIN

1~

~

00-7

REGISTER

V0-

7

DO (0: 7)

CP EN crR ET E2 'E3

t

CP~

rnrmoT
C[RDOUT

--------'

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©

1967 Integrated DevIce Technology. Inc.

DECEMBER 1987
0$0-7000/-

13-190

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT1M8271 MEGABIT (128Kx 8) CMOS STATIC RAM SUBSYSTEM

AC TEST CONDITIONS

5V

5V
GND t03.0V
10ns
1.5V
1.5V
See Figures 1 and 2

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

DATA OUT

~

2550

4800
DATA OUT
30pF

~

2550

Figure 1. Output Load

4800

5pF*

Figure 2. Output Load
(for t OHZ )

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS

(VCC

= 5V±10%, TA =O°C to + 70°C and -55°C to + 125°C)
IDT1M827S50
(COM'L ONLy)
MAX.
MIN.

PARAMETER

SYMBOL

IDT1M827S60

IDT7M827S70

MIN.

MAX.

MIN.

UNIT
MAX.

READ CYCLE(1)
tRCC
t ACp (2)

Min. Clock to Clock Time

40

-

50

-

60

-

ns

Address, CS Clock to Data Valid

-

48

-

58

-

67

ns

3

ns

3

-

5

-

ns

5

-

ns

t ADS

Address, CS to Address Clock Set-up Time

2

Address, CS from Address Clock Hold Time

2

-

2

tADH
tCES

Address Clock Enable to Address Clock Set-up Time

2

-

2

tCEH

Address Clock Enable from Address Clock Hold Time

2

2

-

t EDS

DATAoUT Clock Enable to DATA OUT Clock Set-up Time

3

3

-

2

3

ns
ns

tEDH

DATAoUT Clock Enable from DATAoUT Clock Hold Time

0

-

0

-

3

-

ns

tOE

Output Enable to Output Data Valid

-

8

-

9

20

ns

t OHZ (3)

Output Enable to Output in High Z

-

7

-

8

-

18

ns

t CPD

DATAoUT Clock CPDOUT to Data Valid

-

8

-

9

-

15

ns

WRITE CYCLE
tAW

Write Cycle Time

35

-

45

-

60

-

ns

t CWPL

Address Clock Low Pulse Width

20

-

27

35

Address Clock High Pulse Width

7

-

10

t ADS ' t WES

Address, CS,

VIr:. to Address Clock Set-up Time

2

2

-

3

t ADH , tWEH

Address, CS,

wr:. from Address Clock Hold Time

2

2

-

3

t CES

Address Clock Enable to Address Clock Set-up Time

2

2

Address Clock Enable from Address Clock Hold Time

2

3

-

ns

tDW

Data Valid to End of Write

26

-

3

tCEH

-

-

ns

t CWPH

-

45

-

ns

NOTES:
1. WE Must be high for read cycles.
2. Assumes min tRcC is observed.
3. Transition is measured -200mV from steady state voltage with specified loading in Figure 2.

13-191

2
32

10

ns
ns
ns
ns

IDT7M827 1 MEGABIT (128K x 8) CMOS STATIC RAM SUBSYSTEM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE
ADDR.CS. ~

CP

CPDOUT

1 + - - - - tRCC

--=::;t----.1

DATAoUT

DATA VALID
~----

~-----

t AcP - - - - - . I
tAA - - - - - - . I

TIMING WAVEFORM OF WRITE CYCLE
~-------------- tAW-----------------------~
ADDR. CS

ADDRVALID
I+----I~-- t cwPH ----I~---------- t CWPL ------~

CP

LEDIN

1+-----tDW------~

DATA VALID

13-192

Address, Write Enable (WE) and the three Chip Select (CS)
lines are controlle~ CP. When CE (clock enable) is asserted, all
address, CS and WE data that meets the specified set-up time will
be registered on the rising edge of CPo
DATA IN is controlled by its own enable, LEDIN. With this line in
the high state, the latch is in the transparent or buffer mode. All
DATA IN data that meets~ified set-up time will be latched
when LEDIN goes low. PREDIN and CLRDIN are asynchronous
controls that can be used to preset or clear the DATA IN latch. The
preset function overrides the clear so that, with both asserted, the
latch will be preset.
.
DATAoUT is controlled by its own enable, LEDOUT. With this
line in the high state, the latch is in the transparent, or buffer mode.
Data out of the RAM array that meets the set-up time requirements
will be latched when LEDOUT goes low. PREDOUT and
CLRDOUT are asynchronous controls that can be used to clear the
DATA OUT latch. The preset function overrides the clear so that, with
both asserted, the latch will be preset. There are three active low
output enables for DATAoUT. Unless all three of these lines are
asserted, the output will be in the high impedance state.

FEATURES:
• Registered address lines
• Latched and buffered input data lines
• Latched and buffered output data lines
• Separate I/O
• High-speed access time:
- Military temperature range: 55ns (max.)
- Commercial temperature range: 45ns (max.)
• 20MHz read/write cycle time

DESCRIPTION:
The IDT7M828 is a 128K x 8 RAM with registered address,
latched DATA IN and latched DATA OUT lines. The two data buses
have independent latch enables and this allows the latch to be
used as a buffer by connecting the appropriate Latch Enable (LE)
to Vee.

PIN CONFIGURATION

FUNCTIONAL BLOCK DIAGRAM
AD (0: 13)

GND
Ao

I

Al

•

14-BIT
REGISTER

RAM 1

RAM 9

RAM 2

RAM 10

A4

RAM 3

RAM 11

As
Ae
A7
GND
Ae

RAM 4

RAM 12

RAM 5

RAM 13

RAM 6

RAM 14

RAM 7

RAM 15

RAMS

RAM 16

A2
A3
GND

A (0: 13) - 00-13 00-13

CE

CP

I

WE

DECODER-

~1
~2

A (14: 16) - Ao-2

GND

~1

CS3

PREDOOT

GND
GND

LEDOUT

C::CRDOOT

'CIJ1L)JN

C5E'2
C5E'1
Vee

LEDIN
GND

l5IirnIN

~
~
~

RAMSEL
(0:7)

CS3

SIT

RIC

000
001

GND

002
DDJ

SIT

004

CE

DOs
DOe

00-7

~2

~ WET

SIT

01 0
011
01 2
01 3
01 4
015
Ole
01 7
GND

wrn

f

0(0: 7)

CP

Iv (0:7)

GND

1

16x 10171
V6KX4S
S ATICR
ARRAV

I

~

: PULL UP

I
LATCH
V0-7
00-7
LE 15R'E erR n ~ 1:3

CP

D~

DO (0: 7)

Y(>-7~ D~

Vee

D(>-7 LATCH
LE PRE" ~

DIP
TOP VIEW

LE~IN

01 (0: 7)

1cJrnm

J5tirnIN

LEDOUT

C5E'3

PREDOOT
C::CRDOOT

C5E'1

C5E'2

CEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Integrated DevIce Technology. Inc.

DECEMBER 1987
DSC-7000/-

13-193

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M828 1 MEGABIT (128K x 8) CMOS STATIC RAM SUBSYSTEM

AC TEST CONDITIONS

5V

5V

Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

DATA OUT

~

2550

~

4800

DATA"";55Q

30pF

Figure 1. Output Load

L--4

4800
SpF'

Figure 2. Output Load
(for t OHZ )

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

(Vcc = 5V±10%, TA =O°C to

+ 70°C and -55°C to + 125°C)

IDT7M828S45
(COM'L ONLy)
MAX.
MIN.

PARAMETER

IDT7M828S55

IDT7M828S70

MIN.

MAX.

MIN.

MAX.

UNIT

READ CYCLE(1)

-

45

-

55

-

70

ns

2

-

2

-

3

-

ns

Address, CS from Address Clock Hold Time

2

-

3

-

ns

2

2

-

3

-

ns

tCEH

Address Clock Enable from Address Clock Hold Time

2

-

2

Address Clock Enable to Address Clock Set-up Time

2

-

5

-

ns

t LEDO

DATAoUT LE from Address Clock

39

-

46

-

55

ns

tOE
t oHZ (2)

01: to Data Valid
01: to High Z

-

8

-

9

-

15

ns

9

-

13

ns

ns

t ACP

Address, ~ Clock to Data Valid

tAOS

Address,

t AoH
t CES

cs to Address Clock Set·up Time

7

WRITE CYCLE
tAW

Write Cycle Time

35

-

45

-

60

-

t CWPL

Address Clock Low Pulse Width

20

27

-

35

-

ns

t CWPH

Address Clock High Pulse Width

7

10

-

10

-

ns

2

-

2

-

3

-

ns

2

-

2

-

3

-

ns

wr:. to Address Clock Set-up Time
wr:. from Address Clock Hold Time

tAOS, t wEs

Address, CS,

t AoH , tWEH

Address, CS,

t cEs

Address Clock Enable to Address Clock Set-up Time

2

-

3

-

ns

Address Clock Enable from Address Clock Hold Time

2

-

2

tCEH

2

-

3

-

ns

tow

Data Valid to End of Write

26

-

32

-

45

-

ns

NOTES:
1.
Must be high for read cycles.
2. Transition is measured -200mV from steady state voltage with specified loading in Figure 2.

wr:.

13-194

IDT7M8281 MEGABIT (128Kx 8) CMOS STATIC RAM SUBSYSTEM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE

ADDR, CS, ~

CP

1 4 - - - - - t LEDO - - - . - . I _ - - - - - - _
LEDOUT

DATAoUT
~------- t AcP

-------..1

~--------tAA-------~

TIMING WAVEFORM OF WRITE CYCLE
~------------- tAW-------------~
ADDR, CS

ADDRVALID

tAOS .....---1~-- t CWPH ----I~------- t CWPL - - - - - - - - -

CP

LEDIN
~----

tow - - - -..

DATA VALID

13-195

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7M828 1 MEGABIT (128K X 8) CMOS STATIC RAM SUpSYSTEM

ORDERING INFORMATION
lOT

XXX><
Device Type

A
Power

999
Speed

A
Package

A
Process!
Temperature

y~k

Commercial (O°C to + 70°C)
Military (-55°C to +125°C)
Semiconductor Components Screened to
MIL-STD-883, Class B

L-...---------I C
~------------i

45
55
70
S

~----------------l L

~--------------------I 7M820-828

13-196

Sidebraze DIP

I

Speed in Nanoseconds

Standard-Power
Low-Power

different address. This allows systems to be built that can perform
fast Fourier Transforms in either a decimation-in-time or a decima- .
tion-in-frequency configuration. Data read from Memory 1 can be
synchronously loaded into its output register, while data can be
written into a different location in Memory 2. Similarly, data can be
read from Memory 1 and Memory 2 in parallel from two different
addresses and can be written into Memory 1 and Memory 2 at
unique addresses. Registers at the data input and data output provide fully synchronous pipelined operation. The two memory systems are 20 bits wide and have multiplexed data input and data
output bits from the module data pins. By taking advantage of the
speed of the'registers, data on the pins can run at a speed twice that
of the memory. That is, both output registers can be read or both
input registers can be loaded in a single memory cycle.
Two address sources are available to each address register to
the RAM. Address Source A or Address Source B may be selected
to load the edge triggered register for the 16K x 20-bit memory. The
IDT54/74FCT399 is used for the two Input multiplexer and address
registers for each 16K x 20 memory. All inputs and outputs of the
IDT7M4017 are TTL-compatible and operate from a single 5V
supply.
The IDT7M6001 is offered as a compact 92-pin quad In-line
(QIP) ceramic module. It is constructed using ceramic LCC components on a multilayer co-fired ceramic substrate and occupies
only 4.2 square inches of board space.
AIIIDT military module semiconductor components are compliant to the latest revision of MIL-STD-883, Class B, making them
ideally suited to applications demanding the highest level of
performance and reliability.

FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•

Dual 16K x 20 synchronous RAM
Edge triggered data input and data output registers
Edge triggered data address registers
Two address register sources individually selectable
Separate chip select and write enables to each memory array
Individual clock lines to each register
Dual high-performance 16K x 20 memories
Unique ping-pong operation capability
Assembled with IDT's high-reliability vapor phase solder reflow
process
Available in compact 92-pin ceramic sidebraze QIP (quad
in-line) package
Single 5V (±10%) power supply
Inputs and outputs directly TTL-compatible
Military modules available with semiconductor components
compliant to MIL-STD-883, Class B

DESCRIPTION:
The IDT7M6001 is a dual multiplexed 16K x 20 synchronous
RAM module. It utilizes ten IDT71981 high-speed synchronous
memories, along with the appropriate input data, output data and
address registers. The device features the ability to be used in a
ping-pong mode. That is, data can be loaded into one memory array at one address and be read from the other memory array at a

FUNCTIONAL BLOCK DIAGRAM
REG
Dl0- 19 20/

D

"',

CKl 1

a~

CP

eEl
WE" 1

"""---- D

REG

a

~

rr~
r--

20

~~

CP

16Kx2O
RAM
A

'"

ICP~

20/

'"

DOO- 19

GEl
CK0 1

16Kx 20
RAM
A

REG

20/

DO

D

'"

a~

ICP~

114

CP

a
REG

D

REG

a
82

a

D

114

a
ACK 2

REG

20/

DO

A

CP

D

ACK 1

a

MUX

B

A

I
1
.1 14

.1/14

ADAO- 13

ADBO- 13

MUX

B

81

I
'~

CEM08 is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMRERATURE RANGES
© 1987 Integraled DevIce Technology. Inc.

DECEMBER 1987
DSC-7028/-

13-197

IDT7M6001 DUAL MULTIPLEXED 16X x 20
SYNCHRONOUS STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATION
GND
ADAo
ADAl
ADA2
ADA3
ADA4
ADA5
ADAe
ADA7
ADA6
ADA g
ADA l o
ADA 11
ADA12
ADA 13
CKl l
CKO l
OEl
Sl
ACK l
eEl
WE: 1
Vee

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

PIN NAMES

47
48
49
50
51
52
53
54
55
56
57
58
59

GND
ADBo
ADBl
ADB2
ADB3
ADB4
ADB5
ADBe
ADB7
ADB6
ADBg
ADB l o
ADBll
60 ADB12
61 ADB13

62
63
64
65
66
67
68
69

Vee
Dlo
Dll
DI2
DI3
DI4
DI5
Die
DI7
DI6
Dig
GND
DllO
Dill
DI12
DI 13
DI14
DI 15
Dl le
DI17
DI 16
Dl1g
GND

~°2
OE2
~
ACK 2

~2

Vee

92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70

Vee
DOo
DOl
D0 2
D0 3
D0 4
D0 5
DOe
D0 7
D06
DOg
GND
DOlO
DOll
D012
D0 13
D0 14
D0 15
D0 16
D0 17
D0 16
D019
GND

0E'1-N 2

Data Out Register Output Enable

ADAo-ADA 13

Address Inputs

ADB o-ADB 13
DI O-DI19

Data Inputs

DOO-D019

Data Outputs

CKI 1-CLl 2

Data In Register Clock Input (Active Rising Edge)

ACK 1-ACK2

Address Clock Input (Active Rising Edge)

SI-S2

Address MUX Select Input

WEl-WE2

Write Enable

eE l -eE2

RAM Select

CK0 1-CK0 2

Data Out Register Clock Input (Active Rising Edge)

PACKAGE OUTLINE

DDDDD

DDDD
DDDDD

~1~(5~~~
.050
.100 TYP

.035
.060

.175

.015
.022

DDDDDODi
DDDDD

a:::::Ila:::::Ila:::::Ila:::::Ila:::::Ila:::::Ila:::::Ila:::::Ila:::::Il

I
•

~

1.510

----------------------2.765

2.835

..

13-198

1.470

I

fashion. The device has the serial data-in and serial data-output
bits connected to form a 32-bit Serial Protocol Channel register.
The module features four separate output enables, one for each of
the IDT49FCT818 registers. Thus, the Y outputs from the
IDT49FCT818 registers may be enabled or put into the high-impedance state on individual8-bit boundaries. The Command/Data
(C/O), Serial Shift Clock (SCLK) and Parallel Clock (PCLK) are all
bus organized across the four IDT49FCT818 registers. The thirtytwo register output bits, eight from each device, are separately
brought out to form a 32-bit wide pipeline register on the Writable
Control Store.
In normal operation, data from the 32-bit wide memory is loaded
into the IDT49FCT818 registers on the low-to-high transition of
PCLK. Reading and writing of the memory by means of the Serial
Protocol Channel is performed in the normal fashion using the
IDT49FCT818. That is, the data to be loaded can be shifted in the
serial data input by using the SCLK and a load command executed
by shifting the proper command word in the serial data input when
the C/O line is in the command mode. This command will then be
executed by manipulating the C/O line and SCLK line in the desired fashion. Data is then written into the RAM by bringing the write
enable line on the RAM memory from the high state to the low state
and back to the high state.
The IDT7M6032 is offered in a compact 64-pin 600 mil wide ceramic dual in-line module. It is constructed using ceramic LCC
components on a multilayer co-fired ceramic substrate and occupies less than 2 square inches of board space.
The semiconductor components used on all IDT military modules are manufactured in compliance with the latest revision of
MIL-STD-883, Class S, making them ideally suited to applications
demanding the highest level of performance and reliability.

FEATURES:
• 16K x 32 high-performance Writable Control Store (WCS)
• Serial Protocol Channel (SPC TM ) - reading, writing and
interrogation
• 4 byte/wide output enables
• Separate chip select, write enable and output enable memory
controls
• High fanout pipeline register
• Fully width expandable
• Designed for high-speed writable control store applications
• Assembled with IDT's high-reliability vapor phase solder reflow
process
• Compact 64-pin ceramic sidebraze DIP
• Single 5V (±10%) power supply
• Inputs and outputs directly TTL-compatible
• Military modules available with semiconductor components
manufactured in compliance to MIL-STD-883, Class S

DESCRIPTION:
The IDT7M6032 is a 16K x 32-bit Writable Control Store (WCS)
RAM and pipeline register. It features eight IDT719816K x 4 highperformance static RAMs and four IDT49FCT818 Serial Protocol
Channel (SPC) registers. These devices are arranged to form the
16K x 32 Writable Control Store RAM with Serial Protocol Channel
for loading of the memory. The address lines, chip select, write
enable and output enable of the RAMs are all bused together to
form one large 16K x 32 memory. Each eight outputs of the RAM
are connected to the D inputs of an IDT49FCT818 in the normal

FUNCTIONAL BLOCK DIAGRAM

A
16Kx32 RAM
8 -10T7198s

I/O

I/O

I/O

I/O

SOl

.----SOO

Ci[5

SCLK

IDT49FCT818

PCLK

Y

IOT49FCT818

~

Y

~

CEMOS and SPC are trademarks of Integrated Oevice Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
© 1987 Imegrated DevIce Technology. Inc.

13-199

DECEMBER 1987
DSC-7030/-

IDT7M6032 512K (16Kx 32) WRITABLE
CONTROL STORE STATIC RAM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PACKAGE OUTLINE

64-PIN DIP

-I

~

14

O'2Jgg.PDDDDD.I.~ ~f
T~~

~ g:g~

0.035
0.060

0.100

TYP.

0.015
0.022

13-200

g:~~

Application and Technical Notes

TABLE OF CONTENTS
CONTENTS
Application and Technical Notes
Application Notes
Understanding the IDT7201/7202 FIFO .................................................. .
AN-01
Dual-Port RAMs Simplify Communications in Computer Systems (Rev. 1) ...................... .
AN-02
Trust Your Data with a High-Speed CMOS 16-,32- or 64-Bit EDC ............................ .
AN-03
AN-04
High-Speed CMOS TIL-Compatible Number-Crunching Elements for Fixedand Floating-Point Arithmetic ......................................................... .
Separate I/O RAMs Increase Speed and Reduce Part Count ................................. .
AN-05
16-Bit CMOS Slices-New Building Blocks Maintain Microcode Compatibility
AN-06
Yet Increase Performance ............................................................ .
Cache Tag RAM Chips Simplify Cache Memory Design .................................... .
AN-07
AN-08
CMOS Breathes New Life Into Bit-Slice .................................................. .
AN-09
Dual-Port RAMs Yield Bit-Slice Designs Without Microcode ................................. .
AN-10
Low-Power and Battery BaCk-Up Operation of CMOS Static RAMs ............................ .
AN-11
A Powerful New Architecture for a 32-Bit Bit-Slice Microprocessor ............................ .
AN-12
Using the IDT721264/65 Floating-Point Chip Set .......................................... .
The IDT49C404 32-Bit Microprogram Microprocessor ...................................... .
AN-13
AN-14
Dual-Port RAMs with Semaphore Arbitration .............................................. .
AN-15
Using the IDT72103/04 Serial-Parallel FIFO ............................................... .
AN-16
SPC Provides Board and System Level Testing Through a Serial Scan Technique ............... .
AN-17
FIR Filter Implementation Using FIFOs & MACs ........................................... .
AN-18
High-Performance Controllers Need Microprogramming .................................... .
Technical Notes
Build a 20 MIP Data Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TN-02
TN-03
Using the IDT49C402A ALU ............................................................
TN-04
Using High-Speed 8K x 8 RAMs. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ..
TN-05
FCT - Fast, CMOS, TIL-Compatible Logic ................................................
TN-06
Designing with FIFOs .................................................................
TN-07
Fast RAMs Give Lowest Power. . . . . .. .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ..
TN-08
Operating FIFOs on Full and Empty Boundary Conditions ...................................
TN-09
Cascading FIFOs or FIFO Modules. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ..
TN-10
Dual-Port RAM Address Arbitration Metastability Testing .....................................
TN-11
Cache Timing for the 68020 ............................................................
TN-12
Using lOT's Video DACs in 5V Only Systems. ... .......... . . ... .... ... ....... . ......... . ..
TN-13
Cache Timing for the 80386 ............................................................

PAGE

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By Michael J. Miller

INTRODUCTION
This article discusses several different types of FI FO queues,
their implementation, their performance and their use. Data, or
information in computers, is processed as words or bytes in a
predominantly serial fashion. There lire producers and consumers of information that are connected by busses. Often there
is a mismatch in the rate at which data is produced and the rate at
which it can be accepted. The data is therefore buffered in serial
lists until it can be used. The serial lists are stored in memory and
require overhead to maintain them. These First-In-First-Out
(FIFO) structures can be implemented at many levels from all
software to all hardware. The software implementations are often
the most flexible but yield the lowest performance. The hardware
implementations, while less flexible, give the highest performance.

QUEUES
The elements of any computer or controller can be divided into
three categories in relation to information: transformation, storage
and transfer. Logic gates transform and combine information,
memory elements store information and wires transfer information between the other elements.
Memory can be viewed as an element which transfers information with respect to time. The simplest of memory elements are
latches an~ registers. RAMs are dense arrays of latches. While
RAMs allow for dense information storage, they require an
address to access individual pieces of information in the array.
Therefore, addresses (information) must be generated and
stored in orderto access the desired information. The'addresses
are stored in programs and data structures such as linked lists.
Queues are a special organization of dense arrays of latches.
Queues are a linear organization of groups of latches. Access to
the linear string is restricted to either end. While RAMs allow for
random access of any data in the array at any point in time, they
require address inputs. Queues on the other hand, don't have an
address thus avoiding the address generation and storage
overhead. Queues can be divided into two categories: FIFOs and
UFOs.
Queues can be observed in the world about us. FIFO is an
acronym for "First-In-First-Out". They can be observed in a bank
line-up where customers enter at the end of a line and, after some
wait, are serviced at the other end. The FIFO queue provides a
mechanism by which customers, which arrive at an erratic rate,
can wait until a teller can accommodate them.
UFO is an acronym for "Last-In-First-Out". We can observe this
phenomenon in the work place. As a person is working at a desk,
interrupts occur. A higher priority interrupt such as a phone call
or a request from people higher in management will cause the
person to drop the work on the desk and start a new task. When
the higher priority task is accomplished, the interrupted task on
the desk is resumed. Depending on how many interrupts of
sequentially higher priority tasks come in during the day, the
stack of tasks on the desk grows. Another time honored example
is the stacks of trays at the cafeteria. As trays are washed they are
placed on a spring loaded elevator which sinks down to accommodate the new trays. When new customers enter the food line,
trays are removed from the stack.

As can be seen in the above examples, queues are used to
bufter between the flows of consumers and distributors of
services. Groups of computing elements can be divided into
consumers and producers of information with rates that must be
matched. For example, a rotating Winchester disk is a source of
information that must be serviced at a rate that may not be easily
matched by the CPU which is consuming the information
through the use of a data bus.

SIMPLE FIFO
The implementation of FIFOs is varied and presents many
trade-ofts. The simplest design treats the FIFO as a fixed number
of memory elements in a linear array. When data is written
(pushed) in at one end, all of the rest of the elements shift their
data over to their neighbor at the same time. One can visualize
(Figure 1) the structure as a shift register. The same structure can
. be implemented in software where the program manages an
array of memory locations in RAM. To push data into the queue
the program must first start by moving the contents of the next to
the last location into the last location. The algorithm continues
from the last to the first location. When all of the data has been
rippled down, the first location in the queue will be vacated. The
data to be pushed into the queue is written into that vacated
location.
An improvement in the software solution could be made with
the introduction of a pointer. A pointer is a variable which
contains an address. The pOinter would identify a location from
Which to read the output of the FIFO. When a new piece of

2

Latch

3
4

5

19

N-1
N

Figure 1. Hardware implementation of a fixed length FIFO.
Prinled in U.SA

CI985In'egr.'ed Device Technology, Inc.

14-1

UNDERSTANDING THE IDT7201/7202 FIFO

information is written, it would go into the location identified by
the pointer after which the pointer would be incremented. The
pointer now points at the new output data. When the pointer
reaches the end of the array, the next increment would be
replaced by setting the pointer to the beginning of the array. The
obvious advantage is that the program does less work and
therefore is faster. This software technique is called a circular
queue with one pointer. (See Figure 2.)

FIXED LENGTH FIFO: NO FALL-THROUGH
The FIFO described previously is called a Fixed Length FIFO
and has the characteristic that it takes N cycles for a piece of
information that was placed into it to emerge out of it. The
number N is the number of locations in the FIFO. This implementation also has the characteristic that, when first started
after power up, it will produce unknown data for N cycles until the
first valid data arrives at the output. The latency is therefore N
read/write cycles. The fixed length FIFO does not allow for
differences between the rate of input and output rates. This type
of FIFO is used where the arrival of data at the output is delayed
to match parallel paths in a pipelined system.

VARIABLE LENGTH FIFO
Thevariable length FIFO solves the rate mismatch problem but
requires more overhead to implement. Where the fixed length
FIFO is like a steel pipe which informatiori is fed through and has
a fixed number of locations, the variable length FIFO is like a
rubber hose that can stretch, holding from one to many items.
The items are removed at will instead of being required to at write
time. Every variable length system has a limit and therefore must
signal when it is at capacity and must be serviced before bursting.

APPLICATION NOTE

shift register that functions in parallel. The second shift register
contains flags that indicate whether the associated data element
at the same chronological position in the data queue is valid data
or not. When data is written into the top location of the data
queue, a true flag is placed into the "valid bit" queue. The variable
length quality is achieved by allowing the data and its associated
valid bit to "sink down" into the next location below it if there is no
valid data in that location (see Figure 3). In this way valid data
"sinks" to the bottom of the queue and stacks up in much the
same way as pearls being dropped into a narrow tube filled with
oil. The clocking of data down through the queue is controlled by
an internal self-generated clock. The maximum latency or fallthrough time is a product of the number of cells in the queue and
the internal clock cycle length. This approach meets the requirement that differing rates may be accommodated. The valid bit
data is brought out in parallel with the queue data. The valid bit
data tells the consumer when valid data is present, thus avoiding
the start-up period of invalid data as in the previous implementation of the fixed length FIFO. Examples of this approach are the
shorter FIFOs such as the MMI6740l Fall-through FIFOs tend to
have very long undesirable fall-through times if the FIFO is deep.
The software approach could be designed to mirror the typical
hardware approach by working with two arrays. One for the data
and one of the valid bits. That approach uses too much memory.
An alternate could use a wider array which carried the valid bit
with the data. The algorithm would then start at the end of the
array and pass to the front, advancing all elements which were
valid to the end of the array until all valid data was collected at the
end of the array. This approach would be very costly in terms of
CPU cycles for what is achieved. There is a fall-through latency
which is a product of the time to execute the updated software
loop times the number of locations in the queue.

FALL-THROUGH FIFOs
In the real world of silicon and aluminum there is no such thing
as rubber. Variable length FI FOs must therefore be implemented
using fixed length queues. This fact creates some limitations
which translate into trade-offs. The traditional hardware implementation uses two sets of shift registers. One set is used to hold
the data in much the same way as in the fixed length FIFO. Data
that is placed in the top emerges at the bottom. There is a second

TWO-POINTER FIFO
A more economical approach would utilize two pointers and
one array that was as wide as the data. One pointer would point to

Pointer

2
3

1000
1001

4

1002
1003

5

1004

N-1
1100

N
(b)

(a)

Figure 2. Circular queue with one pointer
a) As it is in memory.
b) Logical view.

Figure 3. Classical FIFO architecture.

14-2

APPLICATION NOTE

UNDERSTANDING THE IDT7201/7202 FIFO

the location at which new data is written into. The second pointer
identifies where data is to be read from for output from the queue
(see Figure4). When either pointer is used to access a location, it
is incremented. When a pointer is incremented to the last location
in the array, the next increment will be substituted with a reset of
the pointer to the beginning of the array. The logical view of this
structure is a circular queue with a read and a write pointer. This
approach results in a much shorter fall-through time while still
achieving the variable length feature. The fall-through time is the
time that it takes to invoke the software to write the data into the
queue, plus the time that it takes to invoke the software to read

W Pointer
R Pointer

1000
1001
1002
1003
1004

1010

1100

(a)

the data out of the queue. While this is much better than the
previous approach, it still requires a reasonable amount of time to
accomplish.

TODAY'S HIGH SPEED FIFOs
The hardware approach, which is used by the IDT7201 and
I DT7202 devices, uti lizes the software concepts demonstrated in
the previous approach but at very fast hardware speeds (50ns
typical military). The block diagram in Figure 5 shows the two
pointers which locate where reading and writing is to take place
in the queue (RAM Array). There is added logic which provides
status about the queue: empty (EF), half full (HF) and full (FF)
(-means an active LOW signal). Two pins, one input (Xi) and one
output (XO), provide for unlimited expansion while still maintaining the 50ns fall-through time. This part functions identically
to the software approach utilizing the two pointers. When either
pointer reaches the last location, it is reset to the first location
thus achieving a circular queue via a wraparound approach. The
status flags reflect the count of how many valid pieces of data are
in the queue. After the device is reset, the empty flag (EF) is
asserted. As soon as a datum is written into the queue, the empty
flag is deasserted. The empty flag is not asserted again until all
pieces of data have been read from the queue. When the count of
data elements reaches one-half the number of locations in the
RAM array, the half full flag (HF) is asserted. If a read is performed
which reduces the count to just below the half way count, then
the (HF) is deactivated. The full flag is asserted when the count of
data elements is exactly equal to the number of locations in the
RAM array, thus flagging that there are no more empty locations
in the queue.

WIDER FIFOs
Figure 4. Circular queue with two pointers
a) As it is in memory.
b) Logical view.

DATA INPUTS
(00- 08)

Vi

Applications may vary widely as to the width and depth of the
FIFO required. If an application's maximum requirement is 1024
locations or less and 9 bits in width or less, then the I DT7202 will
fit. Wider word widths can be achieved by connecting two or
more devices in parallel (control signals). The status flags can be
detected from anyone device because each device is working in
lock step parallel. Figure 6 shows an example of an 18 bit-word
composed of two IDT7201/7202 devices. The older classical
architecture would require more external circuitry to match the
I nput Ready and Output Ready signals to accou nt for differences
in the internal self-generated clock frequencies. RAM-based
FIFOs, such as the IDT7201/7202, do not have this problem.

DEEPER FIFOs

1 - - - + - - " EF
~~~r---t---- ff

Xi

----~L--_ _....J1 - - - - - -

XCIHi'

Some applications require deeper FIFOs. I n the older architecture, deeper FI FOs mean longer fall-through times because they
are connected end to end. The time increases in direct proportion
to the number of devices. For example two devices yield a
maximum fall-through time of twice that of one device. This can
make some applications of FI FOs impractical or totally unusable.
With the two pointer approach used in the IDT720117202, the
data input busses are connected together and the data output
busses are common. This produces a parallel architecture (see
Figure 7) as opposed to the serial approach above. The parallel
structure is analogous to cascading standard RAM devices to
achieve deeper memories.
Since FIFOs do not have chip selects and external decoding
mechanisms, the task of choosing which device is selected must
be provided for internally. The control (in the IDT7201/7202) is
achieved through a unique serial structure. The first (or master)

Figure 5. Functional Block diagram of IDT720117202 FIFO.

14-3

iII
~

UNDERSTANDING THE IDT720117202 FIFO

APPLICATION NOTE

FIFO is identified by grounding the FL input. All other FIFOs in
the structure must have the IT input pulled up to Vee. The XO
output of the first FIFO is connected to the Xi input on the next
FIFO in the queue. The XO output of that FIFO is connected to
the Xi input of the next and so on until the XO output of the last
FIFO is connected to the Xi input of the first FIFO (see Figure 7).

After reset,the active read and write pointers are in the first
device. When the write pointer has progressed to the end of the
first FIFO device, it outputs a pulse on XO which activates the
write pointer at the beginning of the next device and simultaneously deactivates the write pointer in the first device. Thus,
write enable control is passed to the second device. When the

HF

HF

DATA
IN (D)
WRITE
FULL FLAG
RESET

(R) READ

FF

(EF) EMPTY FLAG

IDT7201/2

AS

IDT7201/2

(AT) RETRANSMIT

Figure 6. 10T7201/7202 FIFO Word-Width Expansion.

w----------------~--------~
D

Other Devices
Tied High

OR'ed Full
and Empty Flags
First Device
10 Be Loaded

RS----------------------~~--~

Figure 7. IOT7201/7202 FIFO Word-Depth Expansion.

14-4

UNDERSTANDING THE IDT720117202 FIFO

APPLICATION NOTE

active read pointer reaches the end of the first device, it
terminates and activates the read pointer in the next device with
another pulse on the XO output of the first device. Figure 8 shows
the progression of read and write pointers across two devices. In
this ring structure, the read pointer is always chasing the write
pointer. The pointer enable crosses the device boundaries via
sending an XO pulse onto the next device. This continues in a
circular queue fashion.

specified in the data sheet. During this period the XO output,
which went high at the end of the write enable pulse, has lowered
again. When the read enable is raised by the consumer, the XO
output goes high. In this way two pulses on XO are assured (see
Figure 9).

w
EF

R

a) After reset.
R

W

XO

b) Further reads
and writes.

I I

tJ

U

LJ

I

I

I

a) Regular case.

W
EF

RI
xo

~

:

b) The read-flow through case.

e) Read of last
location initiates
pulse on Xo.

Figure 9. Generation on XO output when the FIFO is empty.
a) Regular case. b) The read-flow through case.

f) Further reads
and writes.

Two examples of the I DT720117202 in expanded depth configuration are available from lOT commercially. The IDT7M203/204
are Subsystems modules which incorporate onto one ceramic
substrate four FIFO Lees and the EF & FF "OR" gating to
produce 2Kx9 and 4Kx9 FIFOs. The Subsystem module has a
lead frame which pins out like the 28-pin 0.6 inch IDT720117202.
This allows for a plug compatible 4Kx9 FIFO in one socket.

g) Write of last
location initiates
pulse on XO.

I) Back in first
device.

~

~L...-

fj

SPECIAL FEATURES OF IDT720117202

_ _.....

The architecture used in the IDT720117202 provides some
features that distinguish it from FIFOs with other architectures.
One outstanding feature is the dual port implementation of the
RAM array. The RAM is designed in such a way that the read and
write ports are separate, allowing for simultaneous asynchronous
reads and writes with no hand shaking or arbitration. In the
classical architecture the consumer and producer circuits must
monitor ready flags for each access.
The IDT7201/7202 support a retransmit function. In the single
device solution, the FLIRT input may be pulsed low signaling a
retransmit.
A retransmit operation will set the internal read pointerto the
first location and will not affect the write pointer. READ ENABLE
(R) and WRITE ENABLE (IN) must be in the high state during
retra. nsmit. This feature is useful when less than 512/1024 writes
are performed between resets. The retransmit feature is not
compatible with Depth Expansion Mode and will affect HALF
FULL FLAG (HF) depending on the relative locations of the read
and write pointers. For example in a communications application,
during transmission of a message, the receiver may request a
retral'lsmit of the message. This can be accomplished by always
starting new messages at the beginning of the queue via a pulse
on the reset input. If and when the retransmit request arrives, the
FLIRT line is pulsed. The read pointer is repositioned at the
beginning of the queue. The message producer may continue to
write more of the same message into the queue as the retransmit

Figure 8. Example on XOIXl expansion scheme.
The IDT720117202 has been designed such that the read and
write pointer can never cross over each other even in the cascade
mode. The XO pulse is synchronous with read and write. When
the last location is read or written, the XO output goes low with
the read or write enable input and back high with the read or write
enable. To see why there is no conflict even though reads and
writes are asynchronous, the usage must be examined. The case
of concern is when the FIFO is empty and the read and write
pointers are at the last location. It must be realized that the
consumer will not read until the empty flag is deasserted. The
empty flag output will go high after the write pulse has gone high
again thus ensuring that the XO pulse, indicating the write
pointer, has been passed on to the next device. The consumer
will then read the last location causing another pulse on XO
which will transfer the read pointer (see Figure 9).
There is one special case regarding read flow-through mode
(discussed below). In this mode the consumer can anticipate the
write, by producer, by lowering the read enable input. In this case
the XO input does not go low with read enable. When write
enable is lowered, XO goes low. XO goes high with write enable.
At this point the empty flag is cleared, thus signaling to the
consumer to terminate the read after the appropriate period

14-5

19
~

UNDERSTANDING THE IDT7201/7202 FIFO

of the message continues. The retransmit can happen as many
times as desired. At the start of the next complete message, the
reset line (RS) must be pulsed after the successful acknowledge
by the receiver. The reset ensures that the new message will be
placed in the FIFO at the start of internal queue. It should be
noted that, when retransmit is possible, messages cannot be
bigger than the maximum size of the queue. If the message is
longer than the queue, even though the read pointer has
progressed far enough to accommodate the extra data, resetting
the read pointer back to the beginning with retransmit will
produce data from the end of message instead of the beginning.
This architecture supports flow-through modes. In the read
flow-through mode, when the buffer is empty, the consumer
can anticipate the write, by the producer at th~ther end, by
lowering the read input. When the empty flag (EF) goes false,
the consumer circuitry can terminate the early read cycle by
reading the data and deasserting the read signal. The read
input must go high for a brief period in order to clock the read
pointer. The read flow-through mode avoids the standard
sequence of monitoring flag going high before hitting a read
cycle.
The write flow-through mode is a mode that is employed when
the FIFO is full. The producer can anticipate a read by the
consumer by lowering the write input before the read. When the
full flag (FF) raises, the producer knows that the consumer has
read a location, thus freeing up a iocation that can receive the
new data. The producer then raises the write input which actually
writes the data into the RAM array. This flow-through mode
avoids the overhead of monitoring the full flag before initiating a
write cycle.
The IOT7201 is pin and functionally compatible with the
Mostek MK4501, thus serving as an alternate source. The
10T7202 gives the same functionality as the IDT7201 but is twice
as deep (1024x9). The 10T7202 is the largest FIFO made with the
zero fall-through time architecture making it the logical choice
for FIFO applications.

SOFTWARE VERSUS
HARDWARE SOLUTIONS
With every application involving a computer or programmed
controller, the designer can trade off between performing certain
functions in software or hardware. In general, the software
solution is a more flexible design (easily changed) but performs
the task more slowly. The hardware solution is less flexible but
performs the task very fast.
To clarify these concepts, a discussion of an application and
how it could be solved at the various levels from software to
hardware is beneficial. A good example is a file server. The server
could be connected to a Local Area Network (LAN) and, on the
other side, to a Winchester disk drive. Both 1/0 connections
demand attention at unpredictable intervals and must be serviced
on demand or data is lost.
If the data rate of both interfaces is sufficiently low, a total
software solution might be considered. The data rate would have
to be low enough such that the software code could poll the
status of either 1/0 port. As data arrives it could be placed into
software FIFO queues. When a full record is buffered, then
processing would commence. During the processing, the I/O
ports must still be monitored as another user on the LAN might
make a request (see Figure 10). It is doubtful that a total software
solution could be designed for the server application that would
have acceptable system performance.

APPLICATION NOTE

The next approach to consider might be to include hardware
interrupts. Interrupts allow for one task to be running and almost
immediately switching to an 1/0 service routine. Interrupts are
something like a hardware subroutine call. This scheme would
use the interrupt mechanism to call routines to move data to and
from the 1/0 ports and the software FIFO queues. The overhead
of constantly polling the 1/0 port status flags would be eliminated,
thus allowing for higher system performance. An asynchronoustype problem is introduced with interrupts. To use interrupts
properly, the 1/0 service routines may be called at any instance.
Therefore, the interrupt routines must be designed in such a way
that they do not destroy data that the interrupted task might be
using. Usually, the routines must be careful to save the state of
the machine, perform their task and restore the state of the
machine. The extra code to maintain the state of the machine is
an overhead that is not in the polled solution. Worse yet, saving
the state of the machine may be too much overhead to allow for
an interrupt during a time-critical piece of code. Because
interrupts may not be acceptable at certain points in the code, the
programmer must insert code to disable and re-enable interrupts
around the critical sections.
Where the polling scheme provides a solution which has a
more easily definable sequence of execution, the interrupt
solution is indefinite. The programmer must spend a lot more
time proving that all possible sequences caused by random
interrupts will produce desirable results. Because interrupts may
not be acceptable at certain points in the code, the programmer
must insert code to disable and re-enable interrupts around the
critical sections. The interrupt disable solution not only cuts
performance by not accepting 1/0 during some periods, but also
adds more overhead with the maintenance of the interrupt enable
mechanism. In some sense, interrupts can be to software what
the meta-stable flip-flop problem is to hardware.
The interrupt solution can be moved out of the software and
more into the hardware realm through the use of a technique
called Direct Memory Access (OMA). The DMA solution is
provided by a block of circuitry which monitors the 1/0 ports.
When the port requires attention, the DMA logic interrupts the
current task at the bus transfer level and steals a memory cycle to
transfer the data to or from the port and the FIFO queue in
memory. The task that is running on the processor misses only a
few memory cycles now and again which is much less than in the
interrupt scheme where a whole subroutine of many memory
cycles was executed to transfer each element of data. The OMA
solution is not for free. OMA controllers are complex devices
which must be programmed as well as designed into the bus
structure. The OMA mechanism can only serve one source at any
given instance in time thus still being a bottleneck in throughput.
So far, each solution proposed has moved the mechanism that
feeds data to or from FIFOs in program memory away from the
software and closer to the 1/0 port. The memory bus still remains
the bottleneck because both FIFO queues are in memory. To
simplify and improve performance, hardware FIFOs such as the
IOT7201/7202 can be used. The processor would interface to the
FIFO through an 1/0 port as before, but the FIFO would now be
between the 1/0 port and the rest of the hardware. The software
could then service the data at a steady rate and be sure that data
was not lost without the problems or overhead of more complicated schemes such as interrupts or OMA.
Because the queues are between the controller and the
peripheral, the peripheral can load or read the queue without
interrupting the controller. Since the controller is not involved

14-6

APPLICATION NOTE

UNDERSTANDING THE IDT720117202 FIFO

with maintaining both queues, there is no possibility of lost data
because one queue was being serviced while data for the other
queue arrived. For these reasons the hardware FIFO represents
the highest performance solution.
If the designer uses large FIFOs like the IDT7202, there is a
minimum of device count. Assuming 2 FIFOs (transmit and
receive) for each I/O port gives a count of four 28-pin devices for

a) The total
software solution. [

the FIFO solution. The DMA solution would at least be one 40-pin
device and several bus buffer/control devices. The interrupt
solution would require a similar parts count to the DMA solution.
Therefore, the FIFO solution is not only the highest performance
solution but usually has the lowest part count of the hardware
solutions.

I
Memory

Interrupt

tt

~0
~

b) The interrupt
solution.

c) The Direct
Memory Access
solution.

d) The FIFO
solution.

Figure 10. Example solutions for File Servers.

14-7

APPLICATION NOTE

UNDERSTANDING THE IDT720117202 FIFO

minimal device count, it presents the problem of which character
belongs to which UART. The solution is to make a wider FIFO
which is 18 bits wide; thus using 4 devices instead of 16 devices
for8 UARTs. This would allow fora UART numberto be placed in
the FIFO along side each character. The remainder of the word
could be used for flag, status and command information between
the CPU and the controller. For example, several of the bits in the
FIFO word could indicate whether the character information was
a character to send or BAUD change rate information.
The empty and full flags of the IDT7201/7202 FIFO would be
used as status flags. For example, the transmit buffer must be
monitored from both sides. As the CPU prepares a character to
transmit, it would first examine the full flag (FF) to see ifthe FIFO
is full. If the FIFO was full, it would delay outputting the character.
If the buffer is not full then it would place the character in the
FIFO. The empty flag (EF) would be monitored by the controller.
As soon as the CPU places a character into an empty FIFO, the
empty flag would change to not true. At this point the controller
would know there was a character in the buffer which could be
transmitted. The controller would read characters from the buffer
as long as the empty flag was not true (buffer contains more than
one character).

COMMUNICATIONS-MULTIPLEXOR
.APPLICATION
Another example of a rate mismatch problem is shown in a
CRT terminal and CPU interface. In order to not load the CPU
wi~h the burden of monitoring the UARTs of multiple CRTs and
printers, a communications controller is employed. The controller
can serve as a communications multiplexor and data concentrator (see Figure 11).
As the controller receives characters it must buffer them such
that if multiple characters are received close together from
several terminals, they will not be lost as more characters come
in. The natural structure to store them in is a queue of the FIFO
type. The CPU will then need to respond to the characters. If the
controller is inputing other characters, the CPU should not have
to wait until the controller is done. Therefore, a FIFO can be
employed on the transmit side as well as the receive side. To
make the design simple, two sets of FIFOs could be placed
between the CPU and controller. When characters are received
they are placed in one end of a FI FO and read from the other end
by the CPU. As the CPU prepares characters for transmission, it
places them in a FIFO going the other direction. The controller
then reads them from the other end of the transmit FIFO and
sends them out through the UART.
Conceivably, there could be a pair of FIFOs for each UART.
That way it would be easy for both the controller and the CPU to
keep straight which characters correspond with which UART.
~.hile this provides for a large total of buffer space for characters,
It IS more than needed when using a part like the IDT7201/7202.
For eight UARTs, this scheme would require a minimum of
sixteen FI FO devices. A better solution would be to use one FIFO
device in either direction. If an IDT7202 were used, it could
provide a maximum of up to 128 characters per UART if all the
UARTs input at the same time and rate. While the two FIFO
techniques would most likely provide plenty of buffering at a

CONCLUSION
Hardware FIFOs are an economical memory organization to
use when lists of data items are to be buffered. Because they do
not require an address to access items in the list, there is less
overhead in terms of circuitry and access time. The FIFO buffer is
most often used as a "system rubber band" to stretch between
the differing and fluctuating rates of different elements in a
system. The IDT720117202 FIFO device features the newest
RAM-based architecture and provides the latest in technology in
terms of access time, fall-through time and size, thus providing
the most economical solution for today's design needs.

Communications
Controller

Main CPU

Main Memory

Figure 11. Communications Controller example.

14-8

By David C. Wyland

allows the same memory to be used for both working storage and
communication by both devices and avoids the need for any special data communication hardware between the devices. The latest
development in dual-port RAMs has been the appearance of high
speed dual-port RAM Chips. These chips allow high speed access
by both devices with the minimum amount of Interference and delay. Integrated Device Technology offers a family of these devices
as shown in Table 1.
(

INTRODUCTION
Dual-port RAMs allow two Independent devices to have simultaneous read and write access to the same memory. This allows the
two devices to communicate with each other by passing data
through the common memory. These devices might be a CPU and
a disc controller or twa CPUs working on different but related tasks.
The dual-port memory approach is useful and popular because it

Support logic
Width

Size

Part

Interrupt

IDT7130

X

IDT7140

X

1K

Busy Logic
MASTER

X
X

IDT7142
2K

Comments

Semaphore

X

IDT7132

X8

SLAVE

X

IDT71321

X

IDT71421

X

X

52-pin
X

ID171322

52-pin
X

IDT7134
4K

IDT71342

X

IDT7133
X16

2K

52-pin

X

IDT7143

X

,

Table 1. Dual-Port RAMs Available from Integrated Device Technology

DUAL-PORT RAMS: SIMULTANEOUS ACCESS

memory location atthe same time. Up to this time, there have been
very few true dual-port memories available. Memories have a single set of controls for address, data and read/write logic and are
single-port RAMs. If you wanted a dual-port RAM function, you had
to design special logic to make the single-port RAM simulate a
dual-port RAM in operation.

A dual-port memory has two sets of address, data and read!
write control signals, each of which access the same set of memory
cells. This is shown in Figure 1. Each set of memory controls can
independently and simultaneously access any word in the memory including the case where both sides are accessing the same

DUAL-PORT MEMORY

DATA
CPU
OR
I/O DEVICE
"L"

L
DATA
I/O

R
DATA
I/O

1 1

ADDRESS

ANI

DATA~

ADDRESS
L
ADDRESS
DECODE

DUAL-PORT
RAM
MEMORY
CELLS

R
ADDRESS
DECODE

1

1

CPU
OR
I/O DEVICE
"R"

ANI
j

CONTROL LOGIC
BUSY, INTERRUPT,
SEMAPHORE

BUSY, INTERRUPT,
SEMAPHORE
Figure 1. Dual-Port Memory Block Diagram
© 1817 Integrated DevIce Technology, Inc.

14-9

Prtnted In the U.S.A.

Rev. 1-.,87

DUAL-PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN-02

beginning. It is known under the name Direct Memory Access, or
DMA. In the DMA concept, a single memory is shared between the
CPU and one or more I/O devices as shown in Figure 2.

Direct Memory Access (DMA) as a Dual-Port
Memory Simulation
The concept of using a conventional memory to simulate a dualport RAM has been common in computer systems almost from the
CPU

I/O DEVICE #1

I/O DEVICE

DISK CONTROLLER

GRAPHICS DISPLAY

I , I

I-

en
w

:>
0

w
c:

~ ~\\
~ ~
~
-

z

~

I , I

,....

I , I

~\\

- ~\\
!

~

ADDRESS
DATA

MEMORY

~

~

...

RNI

DMA MEMORY ARBITRATION LOGIC
Figure 2. DMA Memory System Block Diagram

Each device wishing to use memory submits a request to the
arbitration logic. The arbitration logic responds by connecting the
memory address, data and control lines to one of the requesters
and tells any other requesting devices to wait by issuing a busy signal. The busy signal causes the memory access logic in the device
to wait until busy has gone away before performing a memory
transfer.

CPU/CPU communication only, in an attempt to reduce the time
impact of DMA waiting, or 2) you can provide true hardware dualport memory between the CPUs and all simultaneous high-speed
access by both CPUs to the same memory without waiting. The
introduction of high-speed dual-port RAM chips now makes the
second option practical.

DMA Limitations: Waiting for the Bus

A true dual-port memory allows independent and simultaneous
access of the same memory cells by both devices. This means two
complete and independent sets of address, data and read/write
logic and memory cells that are capable of being read and written
by two different sources. An example of the dual-port memory cell
is shown in Figure 3. In this cell both the left and right hand select
lines can independently and simultaneously select the cell for read
out. In addition,. either side can write data into the cell independent
of the other side. The only problem would be when both sides try to
write into the same cell at the same time. We will discuss this in a
moment.

Dual-Port RAM Chips: How They Work

In a computer system with DMA, the CPU must stop and wait
while an 1/0 device is doing DMA transfers to memory. This works
well in typical systems where the I/O devices are transferring data
only a small percentage of the time and the impact on CPU processing time is minimal. These assumptions do not hold where you
have two CPUs trying to use the same memory. In this case, one
CPU must wait while the other uses the memory. As a result, the
average speed of the CPUs will typically be cut in half.
There are two solutions to this problem: 1) You can provide local
memory for both CPUs and limit use of the common memory to
LSIDE
WRITE DRIVERS

RSIDE
WRITE DRiVERS

R SELECT
(DECODED
ADDRESS)

L SELECT --4--.-H.._-4-----.:-----./
(DECODED
ADDRESS)
L WRITE - - - i -.............+----i

RWRITE

RAM CELL
LATCH

LSIDE
READ DRIVERS

Figure 3. Dual-Port RAM Cell

14-10

RSIDE
READ DRIVERS

DUAL-PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN·02

DUAL-PORT RAM CONTROL LOGIC

sor. This allows the receiving processor to be informed of a communication without having to constantly check for it.
Hardware supportforthis signaling function is provided by interrupt logic, available on certain lOT dual-port RAM chips. A block
diagram of this logic is shown in Figure 4. In these chips, the top
two addresses of the memory chip also serve as interrupt generators for each of the ports. If the left side CPU writes into the evon
address of this pair (3FF in a 1K RAM) an interrupt latch is set and
the interrupt line to the right hand port is activated. This interrupt
latch is cleared when the right hand CPU reads from the even address. A similar set of logic is provided to allow the right hand CPU
to interrupt the left hand one. This logic is associated with the odd
address of the pair (3FE in a 1K memory). Providing this logic on
chip saves the system designer from having to design in extra logic
to allow one CPU to interrupt the other.

Dual-port RAM chips include control logic to solve three common application problems: signaling between processors, timing
interactions when both are using the same location and hardware
support for temporary assignment (ca"ed allocation) of a block of
memory to one side only.

Interrupt Logic For Signaling
A common problem in dual-processor systems is signaling between the processors. For example, processor A needs to signal
processor B to request a task to be performed, as defined by data in
the common memory. When processor B has completed the task,
it needs to signal processor A that the task is done. Note that the
signaling must occur in both directions. A common form of signaling is for one processor to cause an interrupt on the other procesLSIDE
WRITE

INTERRUPT
TO RSIDE

ADDRESS =
LSIDE
ADDRESS

3FF
ADDRESS =

3FE

RSIDE
READ

LSIDE
READ

ADDRESS =

3FF

RSIDE
ADDRESS

ADDRESS =

3FE

INTERRUPT
TO LSIDE
RSIDE
WRITE

Figure 4. IDT7130 Interrupt Logic

Busy Logic Solves Interaction Problems

access of these locations by either side, the probability of a given
location being accessed by one side is of the order of one part of a
thousand. The probability of both sides accessing the same location at the same time is, therefore, of the order of one part in a million. As a result, the average throughput of the system is reduced
by only one part per million due to dual-port RAM access contention (again, assuming uniform random address access by both

A problem can occur with dual-port memories when both ports
attempt to access the same address at the same time. There are
two significant cases: when one port is trying to read the same data
that the other port is writing and when both ports attempt to write to
the same word at the same time. If one port is reading while the
other port is writing, the data on the read side wi" be changing during the read and a read error can be caused. If both ports attempt to
write at the same time, the memory cell is being driven by both
sides and the result can be a random combination of both data
words rather than the data word from one side or the other. Busy
logic solves this problem by detecting when both sides are using
the same location at the same time and causing one side to wait
until the other side is done.
Note that although one or the other processor may have to wait
occasionally, the throughput loss is minimal, typically less than
0.1 %. This is because the probability of both processors using the
same location at the same time is sma". For example, if there are a
thousand words in memory with a relatively uniform and random

sides).

Busy Logic Design
Busy logic is called hardware address arbitration logic because
it consists of hardware that decides which side wi" receive a busy
signal if the addresses are equal. It consists of common address
detection logic and a cross coupled arbitration latch. A logic diagram of the type of busy logic used in the lOT dual-port RAM chips
is shown in Figure 5. The purpose of this logic is to provide a busy
Signal for the address that arrived last, to inhibit writing to the busy
pert and to make a decision in favor of one side or the other when
both addresses arrive at the same time. This logic consists of a pair

14-11

HI
~

DUAL-PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN-02

lines and the comparators. If we assume that the L address is stable
and the R address changes to match the L address, the R address
comparator will go true immediately while the L address comparator will become active some time later as determined by the time
delay gates.

of address comparators, a pair of delay buffers, a cross-coupled
latch and a set of busy output drivers. The address comparator output goes true when the addresses at its inputs are equal.
In the logic shown in Figure 5, the ability to detect which address
arrived last is provided by the time delay buffers between address
ADDRESS (L)

ADDRESS (R)

ADRESS
EQUAL
COMPARATOR

ADRESS
EQUAL
COMPARATOR

CE (R)

CE (L)

" - - - - . - - - - . WRITE INHIBIT (RI

WRITE INHIBIT (LI

B

A

Figure 5. Dual-Port Busy Logic Design

sometimes you need to update a data table as whole and you cannot allow the other processor to use the table until you are done.
This is called block allocation of the memory.
Block allocation can also be used to avoid the address arbitration problem since it is a way of ensuring that both sides do not
use the same address at the same time. This method is also called
software arbitration because the software on both sides decides
and agrees as to who has permission to use a given portion of the
memory. Software allocation has the advantage of not requiring
busy logic, which is useful in systems which cannot accommodate
a busy signal.
The design problem with block allocation is communication of
the assignments between the CPUs. A simple but time consuming
method is to pass messages between the CPUs, perhaps aided by
interrupt logic. In the message method, processor A requests use
of a block from processor B. Processor B agrees and sends permission back to processor A. When A is finished it sends a release
message to B which responds with a release acknowledge to A. In
this system, four messages are sent for each block assigned and
released.

The arbitration latch formed by the Land R gates reflects the address comparator output timing. This latch has three stable states,
both latch outputs A and B high, A 10w/B high and A high/B low.
Initially, both A and B are high because the outputs of both address
comparators are low. We start with the L address stable and the
R address arriving later. When the R comparator becomes active
its output will go high and B will go low. The A output will remain
high because its address comparator input will go high sometime
later and the L gate input from B output will go low before this occurs. The result is that the R gate B output will be active inhibiting
writing to the R side of the dual-port RAM and activating the busy
signal to the R port.
The extreme case of busy logic decision making is when both
addresses arrive at exactly the same time. In this case, the outputs
of both address comparators go high at the same time activating
both sides of the arbitration latch. The latch will settle into one of
two states with either the A or the B latch output being active. The
latch design ensures that a decision will be made in favor of one
side or the other.
The chip enable lines come directly into the arbitration latch,
although they could have been brought into the address comparators along with the other address lines. This is because if the
Chip enable for one side is inactive, both reading and writing for
that side is automatically inhibited andlor arbitration is not needed.
If the addresses are equal, the chip enable that arrives last will lose
the arbitration. If both chip enables are active then arbitration will
be determined by the settling of the address lines.

Semaphore Logic Support for Memory
Assignment
Although block allocation is a software technique, it can benefit
from hardware support. In message passing allocation, four messages must be passed to assign and release a block of memory.
Semaphore logic, available in certain IDT dual-port RAMs, can be
used to eliminate this message passing and its associated overhead. Semaphore logic provides a set offlags especially designed
for the block assignment function. Each flag is used as a token to
indicate which CPU has permission to use a block of memory.

Temporary Assignment of Memory to One Side
A common problem in dual-port RAM application is the need to
temporarily assign a block of memory to one side. Forexample,

14-12

DUAL·PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN·02

Each semaphore flag can be set to one side or the other but not
both. This ensures that only one side has permission to use the
block of memory.
The lOT semaphore logic bits are designed to be used in a
set-and-test sequence. Each bit is normally in the logic one state,
indicating that it is not assigned to either side. A processor, desiring to assign a bit and, therefore, its associated block of memory,
attempts to write a zero into the bit. It then reads the bit to see if it
was successful. If it was, the bit will read zero, and the processor
has use of the block. If it reads a one, it was unsuccessful, and the
block is in use by the other side. The processor must then wait until
the bit becomes zero, indicating that the other side has released it.

Semaphore flags have a particular requirement: a given flag can

be assigned to only one side at a time. Specifically, you must
not have a situation where both sides simultaneously think they
have permiSSion to use a block. Semaphore logic is designed to
resolve this problem. If both sides attempt to set a semaphore flag
at exactly the same time, only one side sees it set.
Semaphore flags consist of eight individually addressable dualport latches. Each latch can be read and written by either side.
They are selected by a separate chip enable, addressed by the
three last significant bits of the address lines and are read and written through the Do data bit. Except for sharing the address, data
and read/write pins of the RAM, the semaphore latches are completely independent, as shown in Figure 6.

DUAL-PORT MEMORY

DATA
CPU
OR
I/O DEVICE
"L"

L
DATA
I/O

1

R
DATA
I/O

1

DATA

ADDRESS

R/W

ADDRESS
DUAL-PORT
RAM
MEMORY
CELLS

L
ADDRESS
DECODE

i

R
ADDRESS
DECODE

ANI
SEMAPHORE
SELECT

SEMAPHORE
CELLS

SEMAPHORE
SELECT

CPU
OR
I/O DEVICE
"R"

i

Figure 6. Dual-Port RAM Semaphore Logic

A logic diagram of a semaphore logic flag is shown in Figure 7.
In this logic, both flip-flops are initially at logic one and both Grant
outputs are high. If only one flip-flop is set to zero, its corresponding Grant output will go to zero. If the other flip-flop is set later, this

will have no effect. If both flip-flops are set at the same time however, the latch will settle so that only one Grant output goes
low, ensuring that only one side receives permiSSion to use the
resource.

L FLIP-FLOP

R FLIP-FLOP

L REQUEST

D

D

R REQUEST

LWRITE
SEMAPHORE

E

E

RWRITE
SEMAPHORE

SEMAPHORE
ARBITRATION
LATCH

~-------.------.~

Figure 7. Semaphore logic Design

and busy signals for a dual-port RAM chip and busy logic. In this
diagram, the chip select is used to enable the chip for a read or
write operation after the addresses have settled. An arbitration is
performed at the leading edge of the chip select.

DUAL-PORT RAM CHIP TIMING
The dual-port RAM has a simple static RAM interface and timing
requirements. There are some special requirements associated
with Busy, however. A timing diagram, shown in Figure 8, shows
the relationships between address, data, read/write, chip select

14-13

m

DUAL-PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN-02

ADDRESS

CHIP SELECT (R)

READ DATA (R)

eUSY {Rl

teoo

R/W (L)
~.........................~......... twoo----""''''''''''''''''''''''''''~

WRITE DATA (R)

.....-+----------.....-tooo""'---------------""'~

~

Figure 8. Dual-Port RAM Timing Diagram

Busy Logic Timing
In the case of address contention, the busy signal from the losing RAM port stabilizes some time after the leading edge of its chip
select (or after its address settles, whichever comes last). If the
busy Signal is gOing to become active, it will become active during
this time or not at all. If the busy signal is generated, the CPU must
wait for busy to go away before completing the read or write cycle.
Once the busy signal has gone high the memory read or write cycle
can proceed to completion.
Note that during the arbitration time following the chip select the
busy signal may be changing. Since it is possible to have a glich on
the busy line during this indeterminate period, the busy line should
be sensed as a level rather than as an edge.
Busy arbitration will be somewhat slower in the extreme case
where both addresses arrive at exactly the same time. This is because both gates of the arbitrator latch are initially inactive and
must settle into a state where only one of them is active. There will
be a period of time when both gates are in transition. This is called
the metastable condition and is a classic and unavoidable problem
in latch and flip-flop design. As a result, the busy settling time
is somewhat longer In the low probability worst case than in the
commonly observed typical case. The maximum arbitration times,
tBM and tBAC' on the data sheet give the worst case values, including metastability setting, for these times.

Read/Write Timing with Busy
The read and write timing for either port of the dual-port RAM
chip is the same as a simple static RAM in the absence of address
contention. All the standard timing measures apply: read data address access time is tM' etc.
Dual-port RAMs have additional timing specifications for the
case of address contention where one port is busy and waiting for

access. For the most general and conservative case, the read or
write cycle for the waiting side should begin after the busy signal
goes away. The actual timing can be somewhat shorter than this in
most cases.
For the case where the waiting side is waiting to write, the write
timing requirement is that the write pulse width be measured from
busy going away. For the case where both sides are reading, the
data will be available at the outputs one access time after the address/chip select lines settle even though the busy line is active. In
the most common case, the trailing edge of busy will occur more
than one access time after the address and data for the busy side
have settled. As a result, the read access time as measured from
the trailing edge of busy, for this case tBDD' is effectively zero.
The write/read case, waiting to read while the other side is writing to the same location, has some additional timing specifications. Since writing to a location by the L side, for example, will
involve changing the data the cell being read by the R side, there
is a write-ta-read propagation delay time. This time is tWDD for the
delay for constant write data from the leading of the write pulse to
. the read data, and tODD for the delay for changing write data from a
change of the write data to the read data.
If the writing side is running at minimum values for the write
pulse or write data set-up times, the read access time, tBDD' will
no longer be zero. The actual tBDD will be equal to tWOD minus the
actual write pulse width or tODD minus the actual write data set-up
time, which ever is larger (andgreaterthanzero). Note: tBDD is
always less than tAA for the worst case of minimum write values.
This is why the read or write cycle is begun from the trailing edge of
busy for the most conservative case recommended above.

14-14

DUAL-PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN-02

memories. Expansion in memory depth with dual-port RAMs is
similar to expansion in depth for conventional RAMs. An example
of this kind of expansion is shown in Figure 9 where and 8K x 8
dual-port RAM has been made out of 2K x 8 dual-port RAM chips.

DUAL-PORT MEMORY EXPANSION: MAKING BIG
ONES OUT OF LITTLE ONES
Dual-port RAM chips can be combined to form large dual-port

--------.....-1
--------+4-1

DUAL-PORT A(R) ~t----------- A l0 -A o (R)
A(L)
D(L)
R~~ ~~IP
D(R)
D7 -Do (R)
WE(L)
WliITE" (L)
ID17132 WE(R) ~
WliITE" (R)
ffEAl) (L)
OE(R) :::::
~.(R)
-r==~~=tt=tt~~
OE(L)
o oJ
~ CE(L)
CE(R) h
~ 0
-'-'-'-l..r"'\..,. BUSY(L)
BUSY(R) ~l-+--+-+--+-'
A lO -A o (L)

D7 -Do (L)

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IX)

CE(L) BLOCK SELECT

~

~
~

A(L)

DUAL-PORT

A(R) I D(R) f ~
WE(L)
ID17132 • WE(R)
~
... 1- ~ OE(L)
OE(R) h
1 p")'--+-+4~I-l,-"'I CE(L)
CE(R) ~1+-+4~~~<: 1
~-I-I-I-,-("1 BUSY(L)
BUSY(R) I'-'

R~~~~IP

I- D(L)

k

e-

IX)

C')

~

I+--

CE(R)
BLOCK SELECT

'designed dual-port RAM SLAVE chips which are part of lOT's product
line. These SLAVE chips incorporate the SLAVE disable logic internally so that no additional logic is required to make a MASTER!
SLAVE combination. In the SLAVE chip, the busy pin serves as an
input rather than an output. If the MASTER chip activates busy, the

SLAVE chip will sense this busy state and intemally disable its
write enable. SLAVE Chips provide a speed advantage
over systems which use extemallogic to implement the SLAVE
,- function. Since the SLAVE logic is built into the SLAVE RAM chip, it
can be designed so that there is no speed penalty when using
SLAVE chips to expand the dual-port RAM width.

14-16

DUAL-PORT.RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN-02

Width Expansion: Write Timing

with SLAVE logic. This delay can be accomplished by delaying the
write enable to the SLAVE by the arbitration time of the MASTER.
This is shown in Figure 11.

When expanding dual-port RAMs in width, the writing of the
SLAVE RAMs must be delayed until after the busy input at the
SLAVE has settled. Otherwise, the SLAVE chip may begin writing
while the busy signal is settling. This is true for systems using
SLAVE chips and for systems using conventional dual-port RAMs

ADDRESS LINES

~

I
R!W

...

I
~

I

I
....
....

WRITE
DELAY

Jr-

r

WRITE
DELAY
.. ARBITRATION
DELAY

Figure 11. MASTER/SLAVE Write Timing

Note that the write delay is required only in width expanded
systems which use SLAVE RAMs, not in single chip or depth expanded systems where only one chip is active at a time. This is
because the individual chips have a built-in delay between the chip
select and write enable inputs and the internal write enable to the

RAM. Separate timing must be supplied in the SLAVE case because this internal delay time can be balanced to the arbitration
time only within a Chip and can vary from chip to chip. If the delay
time for the SLAVE is less than the arbitration time ofthe MASTER,
writing could begin before busy became active, as above.

14-17

DUAL-PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN-02

example, an 8K x 16 dual-port memory is made from 2K x 8 chips in
MASTER/SLAVE combination.

Width and Depth Expansion: An Example
These techniques for expanding dual-port memories in width
and depth are combined in the example shown In Figure 12. In this

A 10 -A o (R)
D I5 -De (R)

)
)
10- A(L)

)

S

... ~"l
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OIL)
WE(l)
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r-

r--C

OUAlPORT
RAM CHIP
MASTER
2K x e

A(R)

~

~ A(l)

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f-+-<

10-

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~

WEll)

rC

BUSY(L) 10T7132 BUSY(R)

WE(R)
CE(R)

BUSY(l) 10T7132 BUSY(R)

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r-r-

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)

CEll
BLOC
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co
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f=
()
u.

~1

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II

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DUAL·
PORT
RAM CHIP
SLAVE
2Kx e

A(R)

.--

WE(R)
CE(R)

......
~

O-r- r-

L~
'"'

10- A(l)
~-

O(L)

r--S

WEll)

:::
""'

DUAL·
PORT
RAM CHIP
MASTER
2Kx8

A(R)

H

~ A(l)

O(R)

r-

r-

WE(R)

CE(R)
CEIL)
BUSY(l) 10T7132 BUSY(R)

~

.... ~

r1

h

/I

I'-'

.... r-

~

OIL)
WEll)
CEIL)

DUAL·
PORT
RAM CHIP
SLAVE
2K x 8

A(R)

~

O(R)

r-f--<

WE(R)
CE(R)

BUSY(l) 10T7132 BUSY(R)

p.r-

a:

w

10- A(l)

0

W

...J
III

~2

w

... 1

A(R)

~

O(R)

r-

WEll)

DUAL·
PORT
RAM CHIP
MASTER

WE(R)

CEIL)

2K x e

CE(R)

~

~-

OIL)

r--S

:::
""

BUSY(l) 10T7132 BUSY(R)

P-

~ A(l)

~r-

r-<

II

.... - ~
;::
r"'-'

OIL)
WEll)
CEIL)

DUAL·
PORT
RAM CHIP
SLAVE
2Kx e

A(R)

~.

O(R)

r-r-<

WE(R)

D-r-

CE(R)

BUSY(l) 10T7132 BUSY(R)

C')

r-<

L

~

I

~

-

is

A(l)
' - - - OIL)

~""
3

BUSY(L)

h1

WE(L)
CEIL)

DUAL·
PORT
RAM CHIP
MASTER
2Kxe

A(R)

r-

O(R)

f---

WE(R)
CE(R)

-

~

g-::::

~ BUSY(l) 10T7132 BUSY(R) ......

Ir

~

A(l)
OIL)
WE(L)
CEIL)

DUAL·
PORT
RAM CHIP
SLAVE
2Kx e

-

WE(R)
CE(R)

~ BUSY(l) 10T7132 BUSY(R)

I

I'"

A(R)
O(R)

+5

+5

-.r

I"-

a:

~
0

L

-

w
...J

~
-a..
W

is

~

~
...,

L3
""'

: 330 OHMS

0
u.

W

'"' 2

a..

-

1

~

::::

-

co

'"'

§
w

f-

CECR)
BLOCK
SELECT

g- r--1

I

~

D7 -Do (R)
WE(R)
TIMING

O(R)

BUSY (R)

330 OHMS:

Figure 12. Width and Depth Expansion of Dual-Port RAMs

14-18

DUAL-PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN-02

a-bit processor communicating with a 16-bit processor through
two 2K x a dual-port RAMs.
In Figure 13, two zao microprocessors communicate using a
single 1017132 dual-port RAM chip. The 1017132 is controlled by
the chip enable. The write enable is set up in advance by the WR
signal from the zao and the chip enable is used to write data into
the RAM or to gate the read data onto the zao bus. The output enable (not shown) is tied to ground (continuous enable). The write
enable is used to disable the output drivers.

USING THEM: DUAL-PORT RAM APPLICATION
EXAMPLES
Examples of dual-port RAMs used for CPU-ta-CPU communication are shown in Figures 13, 14 and 15. In Figure 11, a pair of
8-bit processors communicate using a single 2K x a dual-port RAM
chip. In Figure 12, there is a similar system where a pair of 16-bit
processors communicate using a pair of dual-port RAM chips and
a MASTER/SLAVE configuration. Finally, in Figure 13, we have an

!Q-I.---..----.....---1

A(L)
DUAL-PORT A(R)
~---+----....-If-.... D(L)
RAM CHIP
D(R)
,..
2Kx8
I - - - - I - - -.......-+-I--n
..... WE(L) ID17132 WE(R)
......---I--+-...----+-----I

'-PJ--+-+-t-,

. BI)SY(R) rr~r-.
l-l--+-+--t---+---~

BUSY(L)

r-<:
330 OHMS

L...Q..

ADDRS

ADDRS f - -

L.....1-I--4S'..... WE
CE

RAM

~---I--+-~~

RAM

D~~ r::;>--+-+-'

w

Lc

,..
r:::>--t--t----u

1000-_ _
--..1
CE

-

~

0

W
...J

m
' - - ADDRS
' - - DATA

~

ADDRS t DATA

EPROM
~----~:, CE

EPROM

Figure 13. 8-blt to 8-bit CPU Communication

14-19

w

a.

-

0
"'" ' - ' -

,..
r::;>------a

CE
1000-_ _
--..1

~

D?S
CX)a:
.. a.

~~

NU

..._ _ _ _---1

+5
I------

WAlT

~~

-w

:E

330 OHMS}--J

.-t---i DATA

WR"

DUAL·PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN-02

In Figure 14. two 68000 microprocessors communicate through
a pair of dual-port RAMs. A 1017132/7142 MASTER/SLAVE pair Is
used to avoid the busy lock-up problem. Note that the Address
Strobe (AS) from each 68000 Is used with an address decoder to

enable the dual-port RAM chips. This is to maintain the address for
read-modify-write cycles so that arbitration is not lost between the
read and the write. This Is Important for test and set instructions. for
example.

DATA BITS8-15
ADDRS
DATA

t--------4~-I

!: ~
In

;:

en

A(L)
D(L)

DUAL-PORT
RAM CHIP

WE(L)

MASTER
2Kx8
IDT7132

::: OE(L)
..:;. CE(L)

JJ ~

.... ~

BUSY(L)

I'-

A(R) t - - - . . - - - - - - - - I ADDRS
D(R)
DATA a:

WE(R) ~
OE(R) ~
CE(R) ~
BUSY(R) ~

!:: @
In
0

00

o~

g~

co ()

g5

DATA BITS7-O

CD _

:E

CD -

rC R/W

k
I-k
r-

rC

:E

A(L)
DUAL-PORT A(R)
D(L)
RAM CHIP
D(R)
.-----+-f-+-C~~lI WE(L) MASTER WE(R)
..... OE(L)
2K x 8
OE(R)
.-+-+-+-I--4-H...."O CE(L)
IDT7132
CE(R)
r-- BUSY(L)
BUSY(R)

tt-

UDS
LOS
AS

C

DTACK

1
DTACK
LOGIC

~

*- 8g:

I-

R/W

t-- r- II

UDS
LOS
AS

l....~H-t-t-:-----,

L.;~I-H~-"

PP-IP-I-IP-

l....t)->-+-++--+--+-.-+--.

~
I'-""'

DTACK

1

b

:330 OHMS

330

OHMS~

DTACK
LOGIC

+5
DATA BITSa-15

l(

ADDRESS
DECODE

I - ( READ/WRITE
L--(

CHb~g~~~LE
UPPER

PP--

~

ADDRS
I - - DATA
,.
;:: WE RAM
+
'" CE EPROM

PP-

DATA BITS7-O

..-

ADDRS
~
DATA
"'" WE RAM
+
CE
EPROM

l....~>----+--+-'

-Lc

DATA BITS8-15
ADDRS l DATA I tRAM WE
+ CE rEPROM

R-

P-

--

DATA BITS7-O

ADDRS
DATA
.....
RAM WE
+ CE
EPROM

5-

-< READ/wRITEl::~)----...J

--C

ADDRESS
DECODE

C

CHIP ENABLE l....~)------I
DECODE
LOWER
LPr-----~

L..-_ _~"(")

.....
L..-_ _ _ _ _~.~~

Figure 14. 16-blt to 16-blt CPU Communication

14-20

READ/WRITE
CHIP ENABLE
DECODE
LOWER

P-

p--

DUAL·PORT RAMS SIMPLIFY
COMMUNICATION IN COMPUTER SYSTEMS

APPLICATION NOTE AN·02

In Figure 15, a Z80 and a 68000 communicate using a pair of
1017132 dual-port RAMs. No SLAVE logic is required because the
Z80 side chip enable decode ensures that only one RAM chip will

be enabled at a time. Otherwise, this figure is a combination of the
logic from Figures 13 and 14.
.

DATA BITSs-15

5

I-(/)

-(/)

mW

.b8
.. a:

ADDRS
DATA

Wli

,...

h

.~~

I'""

00.

coO

N5
-

:E

WAIT ~
~

'"'

pr-O-

DUAL-PORT A(R)
A(L)
RAM CHIP
D(L)
D(R)
h.
WE(L)
MASTER WE(R)
OE(L)
OE(R) ~
2Kx8
~
CE(L)
CE(R)
IDT7132
BUSY(L)
BUSY(R)

ADDRS
DATA

m(/)

w

...cb a:8

5-

00.

oD
oa:

coO
<0:E

DATA BITS7-0

p!,..

I'""

"

~

~

DUAL-PORT A(R) I A(L)
RAM CHIP
D(L)
D(R) f h.
WE(L)
MASTER WE(R)
OE(R)
OE(L)
2Kx8
~
CE(L)
IDT7132
CE(R)
BUSY(L)
BUSY(R)

"

R!W
UDS
LDS

h.

AS

P-

~

~3300HMS

0

DATA BITSs-15

~

ADDRS

w
o.

-

0

330 OHMS:
+5

,.. DATA

!,..

;:::

I'-'

'-

WE RAM
CE
+
EPROM
DATA BITS7-0

,..
......

-

~

ADDRS
DATA

,.. WE RAM
+
..... CE
EPROM
'-

P-

~

II-f-

P-

DTACK

W

W
..J

5

!:(/)

,J

1

T
DTACK
LOGIC

DATA BITSs-15
ADDRS t--<
DATA t - RAM WE
CE r+
EPROM

~

DATA BITS7-0
ADDRS
DATA
RAM WE
+
CE
EPROM

--

::>- r--<
::>-

Lc

ADDRESS
DECODE

P-

L...(:

L--c

L--c:
J'"'

.....

READ/WRITE
CHIP ENABLE
DECODE
UPPER

J'"'

.....

-

"

,..

-

READ/WRITE
CHIP ENABLE
DECODE
LOWER

~
~-+-

~
~

Figure 15. 8·blt to 16·blt CPU Communication

the form of OMA, the new dual-port ICs can provide this function
at very high speeds and without the delays associated with earlier
designs. Because of the utility of the dual-port memory concept
these chips should come into wide spread use and become one of
the standard components used by the computer designer.

SUMMARY AND CONCLUSION
The development of true dual-port memories in integrated circuit form provides the designer with the ability to set up communication between components of a computer system while avoiding
many of the problems of prior systems. While the concept of dualport memory has been with us from the early days of computing in

14-21

By Suneel RaJpal and John R. Mlck

INTRODUCTION

TYPICAL
ERROR
RATE

As a computer-science corollary to Parkinson's First Law, "Work
expands to fill the time available," it is observably always true that
"Computer software expands to fill the memory available." There Is
an insatiable demand for higher speed and denser memory, be it
dynamic RAM or static RAM. However, there are reliability considerations that have to be made in large memory systems that must
always provide correct data. This application note deals with methods of enhancing data integrity and system performance by using
Error Detection and Correction (EDC) logic circuits.

% PER
1.000 HRS.

•

SOFT ERRORS DUE TO ALPHA
PARTICLES ONLY

o

HARD ERRORS

0.1
0.01
0.001
0.0001

TYPES AND SOURCES OF ERROR
In memory systems, two types of errors can occur - hard errors
orsoft errors. A hard error is a permanent error and it occurs when a
memory location is stuck-at-one or stuck-at-zero. A soft error is
temporary, random and correctable. As these errors are non-recurring and non-destructive they can be corrected using EDC logic.
Hard errors are caused by factors such as interconnect failures,
intemal shorts and open leads. Soft errors can be caused by system noise, power surges, pattern sensitivity and alpha particle radiation. The charge of an alpha particle can become comparable
to the charge on memory cells as geometries shrink. This implies
that susceptibility to alpha particle radiation is likely to increase as
memory densities increase; however, memory manufacturers try
to reduce or eliminate the problem through deSign or packaging
techniques.
In spite of that, there is a probability offaiJure or error, especially
where large systems are concerned. A graph that shows the trend
of error rate versus chip density for dynamic RAMs is presented in
Figure 1. One can calculate the Mean Time Between Failures
(MTBF) for a DRAM system quite easily based on such data from a
DRAM manufacturer.
A common method to examine data integrity is to incorporate
parity. In asimple case ofa three-bit number and one parity bit, the
following relationship exists as shown in Table 1:

Figure 1: Typical Error Rates

ity bits represent a valid code; "probably" is mentioned, and will be
explained in the following lines. However, if the exclusive-OR result
was a zero, then it can only be identified that an error occurred and
the combination of the data and parity bits represent an invalid
code.
Another interesting aspect of Table 1 is the fact that to go from
one valid code, say 0001, to another valid code, 0100, at least two
bits have to change. This is called a distance of two. If only one bit
changed on the code, it could be used to identify an error, but it
could not point to the correct valid code. For example, if an invalid
code of 0011 is seen, it lies between 0001 and 0010 and it is not
possible to tell if the last data bit is in error or the parity bit is in error.
Now, back to the mention of the word "probably". Iftwo bits in the
data changed erroneously, the parity tree performing the exclusive-OR would not be able to catch that kind of an error. Detection
codes using parity are therefore limited and useful only in detecting one bit in error (or any number of odd errors), and they cannot
provide any correction. Unfortunately, they cannot detect two errors (or any even number or errors).
The detection capability of the codes with different distances
are shown in Figure 2. An invalid code that occurs in the distance of
two cannot tell which bit was erring as outlined in the previous
paragraph. Codes that keep a distance of three (or least 3-bits have
to change to go from one valid code to another) can detect single
bit errors and also correct them. However, codes with a distance of
three cannot detect two failing bits. As shown in the distance of
three examples, if a two-bit error occurs, it would be identified as if
one bit failed. An invalid code associates detection/correction with
the valid code adjacent to it rather than the other valid code that is a
distance of two from it. Codes with a distance of four can detect all
single-bit errors, detect all double-bit errors and also correct all single-bit errors. Double-bit errors are equidistant from two valid
codes as shown by the central invalid code in Figure 2. The Single
Error Correction and Double Error Detection (SECDED) capability
is highly desirable for data integrity in high-reliability ··computer
systems.

TABLE 1
DATA

ODD PARITY

000

1

001

0

010

0

011

1

100

0

101

1

110

1

111

0

The odd parity Is generated by an exclusive-NOR operation of
the data bits. An error can be identified by taking the entire word
and the parity bit, called a code, and performing an exclusive-OR
operation. If the exclusive-OR result was a one, it indicates that the
data was probably correct and the combination of the data and par-

© 19871nt&grated Device Technology,lnc.

14-22

Prtnted In the U.S.A.

8/87 Rev. 1

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-,32- OR
64-BIT EDC

APPLICATION NOTE AN-03

--101----_

regenerated check bits would be 000111 (based on FFFE). The
syndrome bits are the ex-OR of the two sets of check bits and are
001011. Referring to Table 3, a syndrome of 001 011 indicates bit 15
is in error and has to be flipped.
The internal hardware of the IDT39C60 16-bit EDC, shown in
Figure 3A, consists of ex-OR trees that can generate check bits and
syndromes and also contains hardware to correct data. In addition,
two or four IDT39C60s and some SSI, MSI can be connected to
form 32-bit or 64-bit EDC systems. The IDT39C60 is a functional
and pin-compatible replacement of the 16-bit 2960, and runs at a
quarter of the power. Faster versions, such as the IDT39C60 and
the IDT39C60A (the IDT39C60-1 replaces the Am2960-1 and the
IDT39C60A is the fastest 16-bit EDC available), demonstrate that
CMOS circuits can not only run cooler than their equivalent bipolar
circuits, but also run faster with higher output drive.
The architecture of a 32-bit EDC, the IDT49C460, is shown in
Figure 38. The IDT49C460 provides efficient means of generating
check bits, calculating syndrome bits and correcting data bits on a
32-bit data path. In addition, diagnostic capability is provided to
verify data operations in the memory system and verify that the
EDC IC is functional too.

__
II _

VALID CODE

INVALID CODE

VALID CODE

DISTANCE OF TWO - DETECTS SINGLE BIT ERRORS

0-_

_-0
VALID

INVALID
INVALID
VALID
DISTANCE OF THREE - DETECTS AND CORRECTS
SINGLE BIT ERRORS

o

_-0
VALID

INVALID

INVALID
INVALID
VALID
DISTANCE OF FOUR
- DETECTS AND CORRECTS SINGLE BIT ERRORS
- DETECTS DOUBLE BIT ERRORS

Figure 2: Codes of Various Distances and Their Effectiveness

EDC ICs TO THE RESCUE
Codes with the distance of four are used in the
IDT39C60/IDT49C460 Error Detection and Correction ICs. The
overhead in the EDC implementation is additional check bits to the
words in memory. For example, 6 bits are needed for 16-bit data, 7
bits for 32-bit data, and 8 bits for 64-bit data to generate a distance
of four. The code formed is a catenation of the word bits and the
check bits and, as in the parity case, the code can be valid or invalid. The valid codes are a distance of four apart from the next valid
code. Valid codes are implemented by generating check bits
based on the data word and writing the check bits with the data bits
to the memory. On reading the data and check bits from memory, a
possibly valid or invalid code could have been read. The determination of whether the code was valid or not is done by regenerating
check bits using the data bits; these are compared (ex-ORed) to
the check bits that were read and the result is syndrome bits. These
syndrome bits are indicative of an error-free Situation, or a single or
double-bit error, and are used to determine validity of a code, and
also to point to single-bit errors and identify the occurrence of two
or more bits in error.
As an example, let us write (FFFF) H as the data word. The corresponding check bits that will be written in the memory are 001100
and can be computed using Table 2 which is based on a modified
Hamming code. On reading back, if the data was FFFE and the
data in position 15 had erroneously flipped from a "1" to a "0", the

TABLE 3.
SYNDROME DECODE TO ERROR LOCATION/

TYPE
SYNDROME
BITS

S8
S4
S2

0
0
0

1
0
0

0
1
0

1
1
0

0
0
1

1
0
1

0
1
1

1
1
1

*

C8
T

C4
T

T
15

C2
T

T
13

T
10
T

T
4
T

M
T
14

T
0
T

12
T
11

T
7
6
T
5

M
T
T
M
T

9

3
2
T

T
T

M

T
T

T
T

M

M

M

SX SO Sl

0
0

0
0

0
1

0
0
1

1
1
0

0
1
0

C1
CO
T
CX

1
1
1

0
1
1

1
0

T
T

1

M

8
T

1
T

M

M
T

NOTES:
* = No errors detected
Number= Number of the single bit-in-error
T = Two errors detected
M = Three or more errors detected

TABLE 2. 16-BIT MODIFIED HAMMING CODE CHECK BIT GENERATION
GENERATED
CHECK BITS

PARITY

CX

Even (XOR)

0

CO

Even (XOR)

X

C1

Odd (XNOR)

X

C2

Odd (XNOR)

X

C4

Even (XOR)

C8

Even (XOR)

1

2

3

X

X

X

X

X

4

X
X

X

X
X

PARTICIPATING DATA BITS
9
6
7
8
10

X
X

X
X

5

X

X
X

X

X

X

X

X

X

The check bit is generated as either an XOR or XNOR of the eight data bits noted by an 'X" in the table.

14-23

X

12

13

15

X

X

X

X
X

X

X

X

X

X

14

X

X
X

X

11

X

X

X

X

X

X

X

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-,32- OR
64-BIT EDC

APPLICATION NOTE AN-03

Another necessary operation that is required is byte handling.
When the memory is organized as a 32-bit word and an 8-bit update Is being performed, it requires a 2-step operation. The first
step Is to read the 32-bit data and check bits, and correct any erroneous single bit failure. The second step is to write the new byte
with the three unmodified bytes back to the system memory. The
check bits corresponding to the newly formed 32-bit word are generated and also written to the memory. This operation is supported
by having four separate output byte enables in the IDT49C460. The
two-step process is shown in Figures 5A and 5B.

Figures 4A and 4B show the dataflow for the generate and error
detecVcorrect operations In the IDT49C460. In Figure 4A, check
bits based on input data are generated by the EDC and are written
to the check-bit memory along with the data. In Figure 4B, the data
and check bits are read from the memory. Based on their values,
the syndrome bits are generated inside the I DT49C460. If the EDC
is In the correct mode, any single-bit error Is corrected and the corrected data is placed In the output data latch. The syndrome bits
are also available If error logging is done.

LEoUT

or BYTE 0 ~>------,
CBO_6'-~~~------4---4-----------------------------~

DATAo_7
DATAs_15
~BYTE1 ~~-r~~----~

SC O_6
OEsc

LE DIAG
CODE 10
DIAG MODE
PASSTHRU
GENERATE L ) - - - - - t
CORRECT I----:~------~

CONTROL
LOGIC

Figure 3A: The IDT39C60 16-Blt EDC Architecture

LEoUT /GENERATE L · ) - - - - : - 4 - - - - - .
OE BYTEo-3 r->---..:;---,
CBo-7L~~~------;---;-----------------------------~

DATAo-31

SCo-7
OEsc

LE IN L ) - - - - - + - - - - - - - - '

LE DIAG
CODE 10
DIAG MODE
CONTROL
LOGIC
LEoUT /GENERATE L ) - - - - - t
CORRECT I~~------~
Figure 3B: The IDT49C460 32-Blt EDC Architecture

14-24

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-,32- OR
64-BIT EDC

APPLICATION NOTE AN-03

LE our/GENERATE
6EBYTE~3~~-----~~-----~
CB~7

DATA~31 ~~~-.-.~~~~

LEO~GC=~------------;=~!-__~
CODE 10
DIAG MODE I.>-=~------~
LEour/GENERATE
CORRECT ~~---.-4

Figure 4A. Check Bit Generation in the IDT49C460

LE our /GENERATE
OE BYTE~3
CBo-7
DATAo-31

K"""~~--4""'..r;:::;:;-;~:,

LE IN '--:~-------I------..-_-_-:.-:'_ _~

LEO~G

CODE 10
DIAG MODE '--:>-=~-------I'"
LEour/GENERATE
CORRECT '--:~------------I'"

Figure 4B. Error Detection and Correction Data Flow in the IDT49C460

MEMORY LOCATION
HOST CO MMANDTO
WRITE BYTE "E"
AT MEMO RY LOCATION

A
B

~

A

-

E

B

IDT49C460

C

~

o

i

CHECK

Figure 5A. Byte-Write Operation, Step 1. Read 32-Bit Word
and Correct Any Single-Bit Error

0

m

CHECK

Figure 5B. Byte-Write Operation, Step 2. Newly Generated
Check Bits Corresponding to Bytes A, B, E, and D
Are Written To Memory Along With Bytes A, B, E, and 0

14-25

- - _ . _ - - - - - _ ..._ - - - - - -

TRUST YOUR DATA WITH A HIGH·SPEED CMOS 16-, 32· OR
64·BIT EDC

APPLICATION NOTE AN-03

The IOT49C460 is expandable to 64-bit word lengths as shown
in Figure 6A. The external buffer may not be required if the path
from the memory already has a three-state buffer in its output stage
or externally in the data path to the EOC. Figure 68 shows a 2·step
operation when an error detection and correction occurs in bit
32·63 of the 64·bit word. The IC on the first level, with the code
10 = 10, receives the data bits 0-31 and all the check bits. In the example shown, bit 63 has erroneously flipped from a "1" to a "0".
The partial syndrome bits are passed from the first device to the
second. (The actual syndrome bits are generated from a table not
shown in this article but are In the IOT49C460 data sheet.) The
check input latch of the second device is open, due to its code
10 = 11, and the partial syndrome bits are combined with the data
bits to generate the final syndrome bits. The final syndrome bits indicate that bit 63 is in error and it is inverted to produce a correct
result. The final syndrome bits are also sent back to the first device,
but the resulting syndrome does not alter any data bits in the first
device. Therefore, the error correction is a 2-step process. In Figure
6C, an error occurs in the bits 0-31. In this case, the partial syndrome is sent to the second device. The second device generates
the final syndrome and sends it back to the first device. Finally the
erroneous bit is flipped over. In this case, a 3-step operation takes
place.

DATA

CODE

CODE

OUTPUT SYNDROME/CHECK BITS
Figure 6A. The IDT49C460 In a 64-Blt Configuration

CODE

= 10

CHECK
WRITE
READ

FFFFi'FFF(BITS0--31)

3O(INPUT CHECK BITS)

FFFFFFFF(BITS 32-63)

2F(PARTIAL SYNDROME)

FFFFFFFF(BITS 32-63)

2F(FINAL SYNDROME)

= 10 FFFFFFFF(CORRECTED BITS 0-31)

>
>

ADRS

STEP 1

OO(PARTIAL SYNDROME)
CODE

= 11

FFFFFFFE(BITS 32-63)

OO(PARTIAL SYNDROME)

CODE

=

2F(FINAL SYNDROME)

-

'"

MEMORY

"

HOST

STEP 2

FFFFFFFFF(CORRECTED 32-63)

STEP 1

STEP 3

8y virtue of their function, EOC ICs tie in closely with system
memory architecture. Figure 7 shows a host that generates addresses and accesses a memory system. The memory contains
memory elements, error detection logic and interface circuits.
These are needed to start a memory cycle, to send/receive data on
the system bus, and to inform the host that it has completed the
memory operation.
One may use EDC for dynamic RAM memories or static RAM
memories. Figures 8A and 88 show general configurations for
DRAM arrays. Normally, in DRAM systems, separate pins exist for
the DATAOUT and OATAIN.Therefore, lOT FCT244s can be used to
provide an isolation between the DATA port of the EDC and the
OATAoUT from the RAM. This isolation may be required after a
read operation, and the EDC provides corrected data to the system
and the DRAM. Another buffer is needed between the DATA port of
the EOC and the system data bus to allow the corrected data to be
placed on the system bus. The DRAM controller can be implemented using standard off-the-shelf products. An important operation that has to be supported is byte or word handling. The
IDT49C460 EDC configuration shown in Figure 8A has four individual byte enable controls going to the lOT FCT244s and their complementstothe IOT49C460. The IDT39C60shown in Figure 88has
two individual byte controls to the lOT FCT244s and their complements going to the IOT39C60.
In static RAM systems, as shown in Figure 9, there is no need for
a dynamic memory array controller; however, bidirectional buffers
are required on the ports of the static RAMs as RAMs have common
I/O lines for data. If the SRAMs had separate I/O pins for the data,
the buffer configuration of the DRAM array could be used.
The timing controller, common to both DRAM and SRAM systems, controls the buffers and the EDC ICs. This is an interesting
task to the memory system deSigner, as a choice of EOC architectures are available.

CODE ID = 11

30

= 11

>
>

HOW THE IDT49C460 FITS IN A SYSTEM

SCo-7

FFFFFFFFFFFFFFFE

READ

3O(INPUT CHECK BITS)

Figure 6C. Error Correction on a 64·Blt Word,
With Error In Bits 0-31

IDT49C460 OEsc

30

WRITE

3O(CHECK)

STEP 2

~

DATA

3O(CHECK)

FFFFFFFEFFFFFFFF

2F(PARTIAL SYNDROME)

riI~~M4~__~OSEs~c~~

FFFFFFFFFFFFFFFF

FFFFFFFFFFFFFFFF

CODE = 10 FFFFFFFE(BITS 0-31)

INPUT CHECK BITS
DATA 32 - 63 DATA 0--31

CHECK/SYNDROME

A

AE(FINAL SYNDROME)

DATA '"

"CONTROLSv

10 FFFFFFFF(UNCHANGED 0-31)

Figure 6B. Error Correction on a 64·Bit Word,
When Error is In Bits 32·63

INTERFACE

EDC

Figure 7. A Typical Hlgh·Reliability Memory System

14-26

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-,32- OR
64-BIT EDC

APPLICATION NOTE AN-03

DRAM ARRAY

~ Fc!g14S

IDT49C460

DATA
OEO-3
CB

OUT
CHECK BITS
IN

~8

IDT
..---- FCT245s

r--

RAS
CAS, WE

"---

TIMING
CONTROLLER
(PAL-BASED)
DATA BUS

HIGH ADRS

LOWADRS

The architecture of EDC ICs can be categorized as Bus-Watch
and Flow-Through as shown in Figure 10. In a bus-watch architecture, there is only one bus to handle the data and one set of pins that
handle incoming data from the memory, corrected data from the
EDC, and incoming data from the system to be written to the memory. The IDT39C60 and IDT49C460 are based on a bus-watch architecture. In a flow-through architecture, such as Intel's 8206,
there are two ports that handle data movement. The
WDIWDOUT handle incoming data from the system so that the
EDC can generate check bits. The second function of the
WDIWDOUT is to supply the corrected data to the system and the
memory. The second set of pins, DIN, only handle incoming data
from the RAM. These architectures lend themselves to MCheck
Only" and MCorrect Always" configurations.
The MCheck Only" method is used in high-performance systems. The memory system always sends data directly to the host
when a read is requested. In the event a single bit error occurs, one
approach is that the read cycle is delayed and a correction is performed. The corrected data is sent to the host and written into the
memory. In this case, the timing control circuit would disable the
Memory Data Out Buffer (the lOT FCT244 for the DRAM case and
the lOT FCT245 for the SRAM case) and put corrected data from
the EDC IC onto the system data bus, also writing the corrected
data back into the memory array. Forthe MCheck Only" method, a
DATA TO ERR parameter is of key concern to designers as this can
be used to generate the DTACK, READY or BERR signals to the
host.

...----1.1
CHECK BITS
OUT/IN

lJERR"ERR"

DATA BUS
HIGH ADRS

ADDRESS BUS

BUS-WATCH AND FLOW-THROUGH EDC
ARCHITECTURE.

DATAoUT/lN

CONTROL BUS

DRAM
CONTROLLER

Figure SB.EDC Logic In 16-Blt DRAM-Base~ Memory Systems

DATA BITS

SC

tV

ADRS CONTROLS

tt

STATIC RAM ARRAY

CB 14_---a...--1I---i

RAL
CAS, WE

I,CONTROLLER
TlMING
1

CONTROL BUS

ADDRESS BUS

Figure SA. EDC Logic In 32-Bit DRAM-Based Memory Systems

DATA

-

DATA BUS

LOWADRS

tt

IDT39C60
OR
IDT49C460

IDT
FCT245s f-

(PAL-BASED)

HIGH ADRS

CONTROL BUS

DATA IN

4
BYTE
HANDLING
CONTROLS

'---7

.--

,
'16

DATA OUT

OUT
CHECK BITS
IN

-

DRAM
CONTROLLER

tV

16

'2

t

ADRS CONTROLS

,

IDT
FCT244s

~

SC
MERR ERR

BYTE
HANDLING
CONTROLS

r------7

r--

DATA
OEO-l
CB

DATA IN

'4

•

IDT39C60

DATA OUT

'32

~-

MERR "'ERR
I

DATA BITS
r---"7

32

SC

DRAM ARRAY

DATA BITS

r------7
7'

LOW
ADRS

ADDRESS BUS

Figure 9. EDC logic In 16-, 32- or 64-Blt Static RAM-Based Systems

14-27

19
~

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-,32- OR
64-BIT EDC

APPLICATION NOTE AN-03

The other option is that a "Correct Always" method is used. In
this case, the EDC always corrects data (regardless of the fact that
it may be error-free), sends it on the system data bus and writes it
back to the memory. In this case, the cycle time for the data read
includes the "DATAIN TO CORRECTED DATAOUi parameter for
the EDC. The IDT49C460 and the IDT39C60 provide the fastest
timings for the "DATAIN to ERR" and "DATAIN TO CORRECTED
DATAoul' parameters when compared to other currently available
32-bit and 16-bit EDCs. This was made possible by using lOT's
CEMOS™ technology.
The lOT49C460B dissipates only 95mA and the IDT39C60A dissipates only 85mA over the commercial temperature range. The
quiescent power consumption is only 5mA for the IDT49C460B
and the IDT39C60A.
The delay for the DATAIN to ERR is only 25ns for the standalone 32-bit IDT49C460B (worst case commercial) and 42ns for
the 64-bit cascaded case. The delay in DATAINTO CORRECTED
DATAOuris only 32ns for the stand-alone case and 57ns for the
64-bit cascaded case. These parameters are very important when
considering EDC ICs discussed further in a later section. They are,
however, shown in Tables 4 and 5 for the 16-bit IDT39C60 and
,
32-bit IDT49C460, respectively.
The acid test is how a flow-through architecture compares in
performance to a bus-watch architecture in the "Check Only"
mode and the "Correct Always" mode. In Figure 11, a flow-through
EDC device Is connected to a DRAM array system for "Check
Only" operations. Data from the memory goes through the
lOT FCT244 buffer to the system bus directly and simultaneously
to the EOC device. Within the DATAIN to ERR of the device, it is determined if a single-bit error occurred and, if so, a timing controller
would disable the lOT FCT244 and allow corrected data to be sent
on the system bus via the lOT FCT245.

A bus-watch EDC In a "Check Only" configuration is shown in
Figure 12. The data path from the DRAM to the EDC goes through
one lOT FCT244 delay and is Identical to the flow-through case. Afterthat, the DATAINto ERR delay determines whether ornotthe cycle would be stretched. The data from the DRAM goes through an
lOT FCT244 buffer and an lOT FCT245 buffer in the bus-watch
case. One emerging fact is that the time it takes to make a decision
to stretch a memory cycle is the same for bus-watch and flowthrough EDC parts and is determined by the DATAINto ERR of the
respective devices.
In the flow-through "Correct Always" configuration, as shown in
Figure 13, data has to always pass through the EDC and any
lOT FCT245 and then go on to the system bus. In the case of buswatch ICs, data from the DRAM goes through an lOT FCT244, in
and out the EDC device and through an lOT FCT245, as shown in
Figure 12. A bus switch has to take place every cycle as memory
data comes into the EDC, is corrected and then transferred to the
system bus. In a practical design this bus switch may be the longest delay path for "Correct Always".

TABLE 4:
KEY PARAMETERS FOR THE
IDT39C60/-1/A FOR COMMERCIAL RANGE

DATA

SYSTEM DATA BUS

CHECK

Dour

1

DIN

DATA

25ns

20ns

DATAIN TO
CORRECTED DATAoUT

65ns

52ns

30ns

Dour

IDT39C60A

CBour CB IN

BUS-WATCH EDC

2-49C460Bs
FOR
64-BIT EOC

lOT
49C460

lOT
49C460A

IDT
49C460B

DATA IN
TO ERR

40ns

30ns

25ns

42ns

DATAINTO
CORRECTED
DATAour

49ns

36ns

30ns

57ns

CONDITIONS

~

t

IDT39C60-1

32ns

TABLE 5:
KEY PARAMETERS FOR THE
IDT49C460/A/B FOR COMMERCIAL RANGE

MEMORY

DIN

IDT39C60
DATA IN TO ERR

MEMORY
MEMORY
SYSTEM DATA BUS
DATA
DIN

Dour

1

CHECK
DIN

Dour

DATA IN

SYSTE M DATA BUS

CBour
CB IN

lOT
FCT245
WD INI DIN
Dour

I--

Dour

DIN
DIN
Dour

ERR
DATAourlWDlN

CBour CB IN

1

FLOW-THROUGH EDC
Figure 10. Architecture of Bua Watch and
Flow-Through EDC logic

lOT
FCT244

ERR
Figure 11. The "Check Only" ConfiguraUon for Flow-Through EDC ICa

14-28

TRUST YOUR DATA WITH A HIGH-SPEED CMOS 16-, 32- OR
64-BIT EDC

L..-_ _ _ _ _...

CB IN

APPLICATION NOTE AN-03

EDC is going to send corrected data to the host. The EDC also
writes back the corrected data and the newly generated check bits
to the memory. The memory buffers shown in Figure 8A are threestated, as the OE MEM BUFF is high from state 7 onwards and the
EDC would be enabling data on the bus. The timing diagram in
Figure 14 explains a typical case and the users will have to customize it based on their memory speeds and the time the system has
for receiving valid data.
Other factors that may be a consideration are package count
and board space. The number of packages used in flow-through
and bus-watch implementations are the same for "Check Only"
configurations. In "Correct Always" configurations the bus-watch
implementation requires four more IDT FCT244s than the flowthrough implementation. Flow-through ICs have more pins and
therefore leave a larger footprint on the PC. However, in terms of
board space, since the footprint of the flow-through EDC is larger
that the bus-watch, the bus-watch approach takes less space for
"Check Only" configurations and there is a tie for the "Correct Always" configuration.

DOUT
DATA
DIN

....---------i DOUT

CHECK
CB OUT I - - - - - - - - - - t . - t DIN

Figure 12. The Bus-Watch EDC In "Check Only" or
"Correct Always" Configurations

WD IN /
o OUT

DIN
DATA
DIN

o OUT

CBo

DIN
CHECK
o OUT

CBI

o

1 2 3 4 5 6 7 8 9 10 1112 13 14 15 0

STATE i i i
RAS

iii

i

I

Iii

iii

~

ROW/COL ~
CAS _ _--.,

,-,--

=::::-'----.1--:=====--

OE MEM BUFF
Figure 13. Flow-Through EDC In "Correct Always" Mode

iii

,--

DATA

><::::::::)16 bits). For
example, if fixed-point 32-bit operands are to be multiplied, four
partial products have to be added, as shown in Figure 9. The four
partial products can be generated in parallel using four multipliers
and adding the partial products at their appropriate binary
weighting. Alternately, the partial products can be added using
one multiplier while doing shift and add operations in the
IDT49C402, using the register space efficiently.

Pipeline register ClK-Q
Condition MUX (74F251)
IDT49C410: CC to Y
WCS RAM; IDT71682
Pipeline Register Set-Up

10ns
13ns
16ns
25ns
2ns

Total

64ns

Figure 4. The Control Path Delay

Pipeline register ClK-Q
IDT49C402:A/B to F = 0
Status Register Set-Up

10ns
37ns
2ns

Total

49n5

ClK-Q,IDT7216/IDT7217
Data to RAM, Set-Up

25ns
20ns

Total

45ns

Figure 5. The Data Path Delay

DATAIN

t

I

RAM SHIFTER

B DATAIN

DATA BUS

ADD~~~~- ~

A
tRE~~RRJ~~- ~ B

STATUSRGTR
(TO SEQUENCER
VIA MUX)

I

+

.--

IQSHIFTERI

64 WORD RAM
(64 REGISTERS)

I

A LATCH

A

0

B LATCH

I

I

I

+
QREGISTER

I LOGIC 0 I

B

t
0

1

I

1
Q

ALU DATA SOURCE SELECTOR
R

+

RINPUT

I

S

I

SINPUT

+

a-FUNCTION
ALU

1

t

I OUTPUT DATA SELECTOR AND DRIVERS I

!

DSPAN04-{)Q3

DATAOUT(Y)
D5PAN04-Q06

Figure 3. The Address and Data Calculations Unit

Figure 6. The IDT49C402 Block Diagram

14-31

HIGH-SPEED CMOS TTL-COMPATIBLE NUMBER-CRUNCHING ELEMENTS
FOR FIXED- AND FLOATING-POINT ARITHMETIC

APPLICATION NOTE AN-04

the additional ofthe MS part of the XB'YA and XA·YB. This result
is added to the LS part of XA·YA. Finally, the sign extension of the
previous operation is added to the MS part of XA·YA. By using the
register file of the IDT49C402 efficiently, one does not have to
perform 16-bit shifts with each partial product addition, resulting
in a fairly efficient 32 x 32 multiplication.
A high-speed 12MHz fixed-point processor can be built
using the parts shown in Figures 2 and 3-namely the I DT39C10
12-bit sequencer or the IDT49C410 16-bit sequencer, the
IDT49C40216-bit ALU, the IDTFCT374, the IDT71682 RAMs, the
I DT7216/1DT7217 multipliers or the I DT721 011 DT7243 multiplieraccumulators.

In the example shown in Figure 9, the partial product XA'YA is
stored in two locations of the register file. The Most Significant
(MS) part of XB'YB is added to the Least Significant (LS) part of
XA'YB; the carry-out is saved for the next addition to the LS part
of XB·YA. The carry-out again is saved for the next operation for

FLOATING-POINT PROCESSORS
In applications that need a larger dynamic range, floating-point
number representation is used. A discrete solution to a 32-bit
floating-point processor can be at least one board of SSI and MSI.
Most designers prefer an IC or an IC set that implements the IEEE
standard over a discrete solution. The implementation problem
only worsens for double precision 64-bit floating point processors. The IDT72064/IDT72065 and IDT72264/IDT72265 provide
compact, low-powered high-speed solutions to single-, and
double-precision IEEE standard 754 version 10.0 calculations.
The IDT72064/1DT72264 are floating-point multipliers; the
IDT72065/IDT72265 are floating point ALUs. All the parts have
similar lID structures. Data input and output transfers may occur
at twice the maximum pipeline rate, allowing the devices to be
used in a variety of bus configurations without degrading performance. The detailed block diagram of the IDT72264 is shown
in Figure 10. The detailed block diagram for the IDT72265 is
shown in Figure 11. Note that, in Figure 10, the IDT72264 takes
two cycles for 32-bit operations and four cycles for 64-bit
operations. The IDT72064, very similar to the IDT72264, takes
four cycles for a 32-bit operation and eight cycles for a 64-bit
operation.
The multiplier and ALU can operate in two modes: one with
pipelined levels and the other with the pipelined registers made
transparent (called the flow-through operation in the data sheets).
For example, the multiplier in Figure 10 can have the following
registers made transparent: PIPE1 and theSTREG (Status Register), DM and DL registers. This allows the operands to "ripple"
through the logic circuitry at a slower time, as compared to the
pipelined case. A similar configuration is possible for the ALU,

IDT7216 HAS SEPARATE CLOCKS FOR THE REGISTERS.
IDT7217 HAS A COMMON CLOCK AND SEPARATE ENABLES.
DSPAN04-OO7

Figure 7. The IDT7216/IDT7217 Multiplier Block Diagram

x =32-bits XA =X3",6' Xa =X15-0
V = 32-bits VA = V31 • 16 , Va = V1S-D

(UNSIGNED)

I

J

I

+

Xa·Va
r-----~--~~--~

(SIGNED)
(SIGNED)
(SIGNED) 1-.
r __
XA,V
A _ _....
_
THE IDT 7243 DOES NOT HAVE THIS
PATH AND THE PRELOAD FEATURE
WHEN COMPARED TO THE IDT7210.
DSPAN04-009

DSPAN04-OOS

Figure 9. Partial Products for a 32 x 32 Multiply

Figure 8. The Block Diagram of the IDT7210/IDT7243

14-32

HIGH-SPEED CMOS TTL-COMPATIBLE NUMBER-CRUNCHING ELEMENTS
FOR FIXED- AND FLOATING- POINT ARITHMETIC

APPLICATION NOTE AN-04

MUXAM
MUXAL
MUXBM
MUX BL·

AREG

BREG

LOAD
PIPE
PIPELINED DATA PATH
STAGE 1
(USED 1 X FOR 32-BIT, 2 X FOR 64-BIT)

LOAD
ACCUMULATOR

PIPE.1
PIPELINED DATA PATH
STAGE 2

~
~
DSPAN04-Ql0

Figure 10. The IDT72264 Floating-Point Multiplier

14-33

HIGH-SPEED CMOS TTL-COMPATIBLE NUMBER-CRUNCHING ELEMENTS
FOR FIXED- AND FLOATING-POINT ARITHMETIC

APPLICATION NOTE AN-04

3

MUXAM
MUXAL
MUXBM
MUXBL

6
fAEG

32

32
BREG

AREG

PIPELINED DATA PATH STAGE 1
LOAD
PIPE

PIPE 1
PIPELINED DATA PATH STAGE 2
PIPE2
PIPELINED DATA PATH STAGE 3
PIPE 3
PIPELINED DATA PATH STAGE 4

~
~
DSP72265-001

Figure 11. The IDT72265 Floating-Point ALU

14-34

HIGH-SPEED CMOS TTL-COMPATIBLE NUMBER-CRUNCHING ELEMENTS
FOR FIXED- AND FLOATING-POINT ARITHMETIC

shown in Figure 11, where the following registers can be made
transparent: PIPE1, PIPE2, PIPE3, and STREG, OM and OLregisters. The tradeoff in using pipelining is that one result is available
every (pipeline) cycle once the pipe is full. Often this is a preferred
method of computing if the pipe is not flushed. In the flow-through
situation, one does not present any new operands to the inputs
during the duration of the operating time. In a pipelined system,
new values of X and Yare loaded every cycle and new results are
read every cycle, with an understanding that the result being read
cu rrently is from operands loaded "n" cycles ago. "N" depends on
the operation being performed and can range from 6 to 14.
The input stage allows easy interfacing to 16-bit, 32-bit, and

TABLE 1.
IDT49C402 16-Bit ALU Destination Functions
RAM

2901
Functions
(3-Bits
16- I S
IgHIGH

Added
IDT
Functions
(1 Additional
Bit Ig)
IgLOW

F-Up
F-Up
F-Down
F-Down

-

Load F
Load F
Load
Load
Load
Load

-

D
D
F
F

Load D

-

a
a-up

-

a-Down

-

Load F
-

Load F
Load F
Load D
Load D
a-up
a-Down

-

Load D

V-OUT
F
F
F
F
F
F
F
A

IDT7216/IDT7217
16 x 16 Multiply
Clocked Times
I DT721 0/1 DT7243
Multiply-Accumulate
Clocked Times

64-bit buses. The instruction set of the multipliers include singleand Qouble-precision multiply and handling of wrapped multiply.
A wrapped number is one that is smaller than the smallest representable number that is normally used. The ALU has a wide
'variety of instruction including add, subtract, convert, compare,
negate, pass, wrap and unwrap for both single-precision and
double precision operands.
The performance for these devices for the pipelined and flowthrough operations are listed in Tables 3 and 4. These timings
are based on a 50ns clock time. The IOT72064 and IOT72065
are compatible with Weitek's 1064 and 1065 in the IEEE mode.
The I OT72264 and I OT72265 rep/ace Weitek's 1264 and 1265. The
performance is expected to be 20% faster when compared to
currently available Weitek parts.

CONCLUSION
As the need for high-speed computing increases, so does
the expected throughput of number-crunching chips. The availability of efficient building blocks from lOT allows users to
build a 12MHz fixed-point processor and a 10MHz floatingpoint processor.

TABLE 3.
The IDT72065/1DT72265 Performance

F
A
F
A
F
F
F
F

TABLE 2.
MUltiplier and MAC Performances
Commercial

Military

35ns

40ns

35ns

40ns

APPLICATION NOTE AN-04

Single-Precision Pipelined Throughput

100ns

Single-Precision Latency

450ns

Double-Precision Pipelined Throughput

100ns

Double-Precision Latency

450ns

ALU Operations

TABLE 4.
The IDT72064/1DT72264 Performance

14-35

Single-Precision Pipelined Throughput

100ns

200ns

Single-Precision Latency

300ns

500ns

Double-Precision Pipelined Throughput

200ns

400ns

Double-Precision Latency

450ns

700ns

INTRODUCTION:
Static RAMs with separate data inputs and data outputs, such as
the IDT71681171682 4K x 4-bit RAMs and the IDT71982171982
16K x 4-bit RAMs, provide memory organizations that can improve
system architecture in many applications. IDT makes a series of
separate liD RAMs, as shown in Table 1. In this application note,
we will demonstrate several system ideas where RAMs with
separate data inputs and data outputs offer improved system performance. Typically, the separate data inputs and data outputs
eliminate the need for multiplexing of demultiplexing in the data
path. Thus, not only is the output enable or disable time eliminated
in a critical speed path, but a potential additional element (multiplexer or demultiplexer) may also be eliminated.

"

12

From Load.,
Microprocessor

TABLE 1: lOT Separate I/O RAM CHIPS
Size

16K

Organization

Outputs
High Imped.
During Write

16K x 1

-

IDT6167

x4
64K x 1
16K x 4

IDT71681

IDT71682

4K

64K

Outputs
Track Inputs
During Write

-

IDT7187

IDT71981

IDT71982

SEPARATE I/O RAM APPLICATION EXAMPLES
MICROPROGRAM MEMORY

I.

Separate liD RAMs can be used in a high-speed writeable
control store application and offer both speed improvement and a
significant parts count reduction in the interface to a MOS microprocessor used to initialize the RAM at power up. Figure 1 shows a
typical writeable control store design for a microprogrammed
machine. Here we see an IDT39C10 microprogram sequencer
driving the 12-address lines of the I DT71681 171682 4K word array.
If we assume a microcode width of 96 bits, this design will use 24
of the IDT71681171682 24-pin, 300 mil packages. As shown in
Figure 1, the 12 address lines to all 24 packages are connected in
parallel and are driven by the Y outputs of the IDT39C10 microprogram sequencer. This gives a total microcode depth of 4K
words, which is sufficient for most microprogram applications.
The four data outputs from each device provide microcode bits to
the pipeline registerto overlap the microinstruction fetching with
the microinstruction execution. The pipeline register always contains the microinstruction currently executing, while the
IDT39C10 is generating the next address to the RAM and the
RAM is accessing the next microinstruction to be set up at the
input to the pipeline register.
The advantages of using the I DT71681 171682 RAM in this application come from the speed of this device and from the parts
savings associated with not having to demultiplex the data to be
loaded into the memory. If the data path were to be bidirectional,
such as would be required if we used the IDT6116 (2K x 8-bit
RAM) on the IDT6168 (4Kx 4-bit RAM), itwould be necessary to
demultiplex a MOS microprocessor data bus that provides the
microcode at power up. This would require one 8-bit driver for
each 8 bits of RAM to interface between the various RAMs and
the 8-bit microprocessor data bus-an additional 12 parts in this
case.
~1986

Integrated Device Technology. Incorporated.

Figure 1. Typical Wrlteable Control Store In a Microprogrammed
Machine.

In a typical system, such as isshown in Figure 1, the microcode
is read from a floppy disk and loaded into the writeable control
store. An example of this type of microcode loading architecture
as shown in Figure 2. The microprocessor system shown in
Figure 2 requires three interface points to the writeable control
store. First, you must define the address for the write operation.
This is provided by means of a WCS address register to select
which word in the writeable control store will be written into.
Second, you must define the data you are going to write. This is
provided by a data register which defines the data for a specific
eight bits of the 96-bit word of the control store shown in Figure 1.
A total of 12 bytes are required to load one microcode word into
the writeable control store depicted in Figure 1. The specific byte
to be written is selected by four additional address bits from the
WCS address register which are directed to the decoder so that
one of the 12 bytes can be selected for loading. Third, a control
register is then used to select between the WCS load and operate
modes and to manipulate the write enable (WRITE") line connected to the decoder.

Figure 2. Autoload of the Wrlteable Control Store.
Printed in the U.S.A.

14-36

7/86

APPLICATION NOTE AN-OS

SEPARATE 1/0 RAMS INCREASE SPEED AND REDUCE PART COUNT

The complete cycle required can be described as follows. First,
set up the control register to select the WCS address register
onto the address bus and disable the IDT39C10 Y outputs.
Second, move the address of the first byte to be loaded to the
WCS address register. Third, move the data byte to be loaded to
the data register. Fourth, change the WRITE' line from high-tolow-to-high by means of two MaS microprocessor I/O cycles.
This will write one byte of data to the writeable control store
memory. Continue by repeating the steps of loading the WCS
address register, data register and then "writing" the data into the
writeable control store memory.
A detailed connection diagram ofthe IDT71681/71682 interface
to the MaS microprocessor is shown in Figure 3. Only 10 of the
24 devices are shown, but the connection scheme is similar for all
24-devices. The important point to recognize from the diagram is
that the data-in lines are connected on a byte-wide basis. One
IDT71681171682 is connected to the Doto D3data inputs and the
second IDT71681171682 is connected to the 04 through 07
inputs. This means that each two devices are connected so as to
accept one byte of data from the MaS microprocessor system.
The 12 address lines to IDT71681171682 are connected in parallel
and are driven by a register with three state outputs such as the
IDT74FCT374. The remaining address lines from the 29825 WCS
address register are connected to decoders such as the
IDT74FCT138. Each outputforthe IDT74FCT138 is connected to
two write enable inputs on the IDT71681171682 memories. This
allows one byte to be written when the WRITE' line is changed
high-low-high. The chip select line is simply grounded and not
used in this application. As can be seen, the IDT71681171682
offers a convenient interface in a writeable control store for
external loading of the data. This connection concept can be
extended and changed such that the writeable control store
could be loaded with data provided by the host execution CPU
itself, rather than the floppy disk.

is provided by a 12-bit offset address. As shown in Figure 4, the
12-bit virtual page address can be connected to the page mapping memory and the resultant output will be a physical page
address and status information. A detailed connection diagram is
shown in Figure 5.

Figure 4. Memory Mapping.

68000
Microprocessor

,------Figure 5. Memory Mapping.

'----+-----------j ..

::!

'----+-------------~. ~

'--~------------__i .. ~

Figure 3. Detail of the MOS Microprocessor Interface to a Wrlteable
Control Store.

VIRTUAL MEMORY AND MEMORY MAPPING
Separate I/O RAMs are ideally suited for use with MaS microprocessors to provide the memory mapping function associated
with today's complex microprocessor operating systems. As
shown in Figure 4, the IDT71681/71682 can be used to provide
mapping from a microprocessor virtual address to a microprocessor physical address in main memory. In addition, status
information about the map can also be present in the page table.
In this example, a 24-bit virtual address is divided into a 12-bit
virtual page consisting of 4K words per page. Depth into the page

A computer that provides any form of mapping other than the
identity map between the central processing unit generated
addresses and the physical memory address satisfies the most
general definition of virtual memory. In Figure 5, we see the
IDT71681171682 address lines connected to the upper 12 bits of
an address bus, such as those provided by the 68000 microprocessor. Here, the separate data output lines are used to
provide mapped addresses as well as exception bit status
vectors. The separate data-in lines can be connected to the data
bus so that the page table provided by this memory is easily
updated.
Many use the terminology of virtual memory in a more
restrictive fashion. That is, a virtual memory is one where the
actual physical memory is smaller than the total memory
addressing capability of the machine. A page table memory map,
such as that shown in Figure 5, is used to provide a translation
from the virtual address to the physical address in such a
memory. In a related definition called memory mapping, the
physical memory is larger than the logical address space of the
machine. This is often applied to such microprocessors as the
8085 and Z80. Here, the machine's logical address space is
limited to 64K bytes, but it may be desirable to have a larger
physical memory available to the machine. The connection
scheme shown in Figure 6 can be used to perform this memory
mapping. Some number of address lines, eight in this example,

14-37

191
~

I

SEPARATE I/O RAMS INCREASE SPEED AND REDUCE PART COUNT

are connected to eight of the 12 IDT71681/71682 RAM address
lines. The additional four RAM address lines are provided by a
register and perform an additional mapping select function. The
12 RAM data output lines of the RAM are used in conjunction
with the 8 remaining address lines from the microprocessor to
provide a total of 20 address lines (1 megabyte) in this example.
The 12 RAM data-in lines are connected to the data bus for easy
loading of the page table.

APPLICATION NOTE AN-OS

One of the most common cache memory organizations used is
called the direct mapped cache memory. Figure 7 shows the
block diagram for the implementation of the typical direct
mapped cache. In this implementation, the cache memory
consists of three main parts. These are the tag store, the data
store and the match comparator. In the example shown in Figure
7, the tag buffer and data RAM are each 4K words deep using one
row of the IDT71681171682 static RAMs. The high order 12 bits of
the address can be stored in the tag RAM so as to specify the
unique memory space for which the data corresponds. The tag
RAM usually contains additional bits which represent data validity and parity.
Microprocesor

Oat.
Microprocessor

Add!,,,

Hi9;;.----...~w

Figure 6. Z80 Memory Mapping.
,2

Figures 5 and 6 indicate that some thought must be given to the
exact mechanism for the address to be provided to the mapping
RAM while it is being loaded. This can be handled in one of two
ways. The simplest way is to provide an address register on one
of the microprocessor I/O. ports that is loaded with the target
address, and then this address is used when the mapping
memory is being written into. A more clever technique is to
provide a control register that disables the main memory write
and enables the mapping memory write such that no additional
address register is required. Instead, data to be loaded into the
mapping memory is simply moved to the address in the virtual
space and is redirected to the mapping memory rather than the
main memory.
Again, the examples of Figure 3 through 5 demonstrate the
advantage of the IDT71681171682 in having separate data inputs
and data outputs.

CACHE MEMORY
A cache memory is a high-speed memory that is placed
between the CPU and the main system bus. The purpose of a
cache memory is to make a slow memory look like a fast memory.
This is done by using two memories. The first is a sma", highspeed memory called a cache memory, and the second is a large,
slow memory called the main memory. Both memories are
attached to the system bus which is connected to the CPU. The
cache memory holds a copy of the most frequently used data in
the main memory. If data requested by the CPU is in the cache
memory, it responds first; if not, the CPU waits for the data from
the slower main memory. If the data and instructions being
executed most of the time are in the cache memory, a performance
improvement is realized. This is commonly the case because
most programs consist of loops and sma" pieces of code which
are executed repetitively, and these occupy a sma" number of
memory locations. The hardware associated with the cache
memory attempts to keep this data in the high-speed memory.
The term "hit ratio" is used to describe the number of times the
data or instructions are in the cache memory versus the total
number of memory accesses. It is not unusual to find hit ratios in
the 90 percent range for some cache memory designs.

Control
(To Main Memory)

Address
(To Main Memory)

Figure 7. Direct Mapped Cache Memory.

The operation of such a cache memory is as follows. The
microprocessor puts out an address on the address bus. The
lower 12 bits are connected to the address inputs of the data and
tag RAMs and cause the data and tag RAMs to begin fetching the
word at the location. Then, the actual data value stored in the tag
RAM is compared against the upper 12 address bits to look for a
match. If a match is found, the valid bit is true and the data in the
data RAM corresponds to the address on the address bus, we
have a cache "hit" and the data in the data RAM is placed onto the
microprocessor data bus. If no match is found or the valid bit is
false, then a cache "miss" occurs and the data must be fetched
from the main memory. As the data is brought in from the main
memory to the microprocessor, it is also written into the data
RAM and, at the same time, the tag RAM is loaded with the high
order 12 address bits that represent the tag number from which
the data was taken. Hopefu"y, the next time this address is used,
it wi" still be in the cache memory.

STACK MACHINES AND
HIGH-PERFORMANCE ALUS
A bit-slice microprocessor design can utilize separate I/O
RAMs in the ALU architecture in several ways. A typical bit-slice
microprocessor ALU configuration is shown in Figure 8. Here we
seethe IDT71681/71682 configured with its data inputs connected
to the Y output of the 2903 bit-slice, and its data outputs
connected to the DA input of the 2903 bit-slice. Two uses for such
a connection are obvious. First, it is possible to use the tightly
coupled RAM to increase the number of registers available to the

14-38

SEPARATE 1/0 RAMS INCREASE SPEED AND REDUCE PART COUNT

ALU. This could be used in certain high-performance algorithms
such as floating point, Fast Fourier Transforms (FFTs), etc. Similarly, this register set might be used to allow very high-speed
context switching of the processor ALU section. In this fashion,
no register would have to be updated during the handling of
interrupts or other system/user context switches.

APPLICATION NOTE AN-OS

display controller, the character generator, uses two IDT71681/
71682s to hold 512 different 5-by-7 dot characters. In this
configuration, the CRT controller provides the address to the
cha~acter generator which generates the dot pattern for a
particular line in the selected character. By using RAM in the
character generator, the character font can be controlled by the
host microprocessor and changed as often as desired. Two
additional IDT71681171682s are used for the screen refresh
RAM. In this application, two RAM chips provide the local
storage for the characters on the screen. Since a standard 24row-by-80-column CRT display represents almost 2K bytes of
data, the screen refresh RAM shown can store up to two pages of
information for display.

Figure 8. Stack Machines and High-Performance ALUs.

Another use for the I DT71681 171682 RAM shown in Figure 8
would be to provide a local stack for the ALU. This could be
implemented using an up-down counter to drive the address
lines to the RAM and the appropriate microcode to control
pushing and popping of the stack. One or more such stacks
could be very useful in high level language machines. For
example, two such stacks might be used in a FORTH machine.
One stack would be the operand stack, while the second stack
would be the return stack.
A typical TTL ALU implementation is shown in Figure 9. Here,
an MSI ALU, such as the 74S181, is used in a microprogrammed
environment. Local register/accumulator storage is provided by
IDT71681171682 memories. The A and B inputs to the ALU are
driven by the accumulator A and accumulator B RAM register/
stack, respectively. Again, the advantage of the separate data
inputs and data outputs is well displayed.

Figure 9. TTL ALU Implementation.

VIDEO DISPLAY CONTROLLER
The video display controller shown in Figure 10 can utilize
separate I/O RAMs in two different ways. One area of the video

Figure 10. Video Display Controller.

DIGITAL FILTERS
The four-sample non-recursive digital filter in Figure 11 is
another application which demonstrates the importance of
separate data inputs and data outputs in the RAM memory. In this
example, a 4096 word range-gated filter is shown. Digital filters
consist primarily of memory, multipliers and adders. Rangegated filters are used in systems that quantify and otherwise
process distance-related measurements such as radar, sonar and
ultrasonic medical diagnostic instruments. Typically, the return
signal is divided into increments of time (or distance) where each
increment is to be individually processed. Thus, many different
elements are to be processed and all may share the same
multipliers and adders. However, different memory locations are
needed for each time-sequential element. The example shown in
Figure 11 can best be understood with the following description:
the current output is equal to the sum of the present sample times
the constant A o, plus previous sample times the constant A 1, plus
the second previous sample times the constant A 2, plus the third
previous sample times the constant A 3. Foursamples participate
in generating each output, and because only input samples contribute to the output, the filter is said to have a finite impulse
response.
Similarly, Figure 12 shows a range-gated recursive digital filter.
It is similar in concept to that shown in Figure 11, except that a
recursive filter contains feedback. Because feedback terms
contribute to the output, it has an infinite impulse response.
Again, separate I/O RAMs provide a unique performance advantage in this application.

14-39

rn
~

SEPARATE 1/0 RAMS INCREASE SPEED AND REDUCE PART COUNT

APPLICATION NOTE AN-OS

Depending on the write timing, it may be necessary to place
either latches or registers at the input or output of the RAMs
shown in Figure 11 and 12.

with different transformations on each pass. This requires at least
two RAMs. It is desirable to use a single bus system to tie the
RAMs to the transformation logic, so that only one set of transformation logic is required.
DATArN

DATA OUT

Figure 13. Pin Pong RAM.
Figure 11. Four-Sample Non-Recursive Digital Filter.

EOUT

EOUT ~ Ao+A,z·'+Aaz·:r

E1N

•

1" B,Z·'B aZ- 2

B,

Figure 12. Recursive Digital Filter.

PING PONG RAM
A common problem in digital signal processing is the word-byword transformation of a block of data, such as adding a constant
to each word. This tranformation is usually done by reading each
word from on RAM, modifying the data and writing the word into
a second RAM. This type of operation may be done several times,

A significant speed improvement in a common bus design can
be realized by using two separate I/O RAMs in an alternate
read/write mode, as shown in Figure 13.ln this approach, data is
initially read from the first RAM while transformed data is being
stored in the second. Then, by changing the state of the WE
input, data is read from the second RAM and new data can be
written into the first RAM. In this fashion, one RAM is always in
the read mode and the other is in the write mode. The CS can be
used to remove both RAMs from the DATAoUT bus so it can be
used by other devices. The CS line MUST be set inactive during a
change of address to the RAM in the example shown in Figure 13.
A speed improvement is realized in this configuration because
the "data valid to end of write" ti me is faster than the "write cycle"
time. This allows external logic to be performed on the DATAoUT
and the result to be written back into the RAM at an overall higher
system speed. In some designs, timing advantages can be realized by separating CS, WE, or both.

SUMMARY
Separate I/O CMOS static RAMs can provide the system
designer with increased speed and reduced part count and their
versatility will be demonstrated by creative design engineers in
numerous applications beyond those discussed in this application
note. These devices offer high-speed access times and highspeed cycle times. The low power inherent in CMOS allows new
levels of performance to be achieved in small, compact designs
without the thermal problems of earlier bipolar designs. Certainly,
these devices offer the system design engineer another tool in
the search for improved system performance.

14-40

by Michael J. Miller

INTRODUCTION

RE-EMERGENCE OF MICROPROGRAMMING

The electronics industry has been an evolutionary succession
of dominating technologies. This has been true for semiconductor devices in general, as well as the product family
called bit-slice microprocessors. With the extinction of each
technology and the emergence of the new, there is an associated
transition for both the manufacturer and the consumer. Each
company seeks to minimize the effort of this transition.
In the 1950s it was a generation of germanium diodes and
transistors. During the 1960s, silicon transistors and bipolar
ICs dominated. The last decade saw the emergence of the
NMOS microprocessor and dynamic memories. This decade
will be dominated by very high-speed CMOS as the primary
volume process. This evolution is not only taking place with
the industry but, in specific, with the microprogrammed bit-slice
microprocessors. Today very high-speed, low-power CMOS is
taking the place of high-speed bipolar. CMOS is capable of
operating faster and at 1/5 to 1/10 the power of bipolar
technologies. Because of this, CMOS is becoming the technology of choice for bit-slice microprocessors.
In the past, technological changeovers have been expensive to the manufacturer as well as the consumer. The
MICROSLICE'" Family from IDT seeks to facilitate this transition
by offering two families of CMOS bit-slice devices: IDT39COOO,
IDT49COOO. The IDT39COOO family provides high-speed
CMOS devices that fit into the sockets of current designs
which utilize the 2900 family of bit-slice devices. The IDT39COOO
family is pin-for-pin compatible to the 2900 family as well as
compatible with its highest speed grade. An easy upgrade path
is provided by the IDT49COOO family of bit-slice devices. This
family starts off by providing higher densities (families of
16- and 32-bitl, improved architecture and progresses on into
innovative architectures of the future.

As a result of CMOS, bit-slice microprogram designs are
experiencing a new renaissance. In the mid-70s, the emergence
of the 2900 family, as heralded by the 2901, was designed
entirely using TTL bipolar technology. The 2901 has progressed
from a propagation time - A/B to 'G/P equal to SOns - to the
2901C which sports 37ns. To achieve these final speeds though,
the total TTL design had to be abandoned and ECl was
substituted for the inner workings of the 2901, with TTL buffers
interfacing to the outside world. Today at IDT, very high-speed
CMOS is being used to produce an IDT39C01 E with A/B to
'GIP of 21 ns, at 1/S the power of the bipolar 2901 C.
In parallel with the evolution of the 2901 has been the
blossoming of the 2900 family to a multi-device product family.
All of the latest designs use ECl internally. The trend in this
family has been to add more and more gates on chip. To
achieve this, though, more current has been consumed by
each of the ICs starting with the 2901 at 1.25W to the 29300
family at approximately Sw. To handle the SW, new packaging
technology was developed which incorporates heat spreaders
and cooling towers mounted on top.
Within the limits of maximum speed and density, tradeoffs
can be made. For a given package, more speed can be achieved
with less gates; or conversely, more gates can be incorporated
at the expense of overall speed in critical paths. This relationship
is referred to as the speed/power product of a given technology.
The bipolar 2900 family has been extended to the limit of
feasible packaging and cooling technology because of the
density and speed requirements of today's applications. Very
high-speed CMOS, in contrast, has a speed/power product an
order-of-magnitude smaller than bipolar for the same speed.
Therefore, CMOS requires less expensive packages and
cooling systems.

COMPARISON OF FAMILY PERFORMANCE(1)
BIPOLAR

MICROSLICE
SPEED (ns)

DYNAMIC POWER (mA)

SPEED (ns)

DYNAMIC POWER (mA)

SPEED PATH

IDT39C01C

37,25

30

37,25

265

IDT39C01D

28,17

35

-

-

AlB - G/P, C n - F = 0

IDT39C01E

21,14

40

-

-

AlB - G/P, C n - F = 0

IDT39C03A

52,35

60

52,35

350

AlB - G/P, C n - Z

IDT39C10B

30

80

30

340

CC- y

IDT39C10C

16

80

-

340

CC- Y

IDT39C203

52,35

60

52,35

350

AlB - G/P, C n - Z

AlB - G/P, C n - F = 0

NOTE:
1. Reflects performance over commercial temperature and voltage range.

MICROSLICE and CEMOS are trademarks of Integrated Device Technology. Inc.
C1986 Integrated Device Technology. Inc.

Printed in the U.S.A.

14-41

7/86

16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROSLICE COMPATIBILITY YET INCREASE PERFORMANCE

A decade ago, CMOS was noted for lower power and lowperformance. Today, CMOS is capable of running at s~eeds
faster than bipolar at 1/5 to 1/10 the power. Dramatically
smaller power consumption and smaller gate sizes allow for
even higher levels of integration to be achieved. In previous
bipolar designs, an ALU, a barrel shifter and a multiplier each
required a package of their own for heat dissipation, whereas
CMOS can incorporate them all on one piece of silicon while
still having room to include a reasonable amount of RAM. This
means that CMOS has room to grow, thus providing for new
innovative architectures in the future.
While the lower power consumption allows for more gates in
the same package, there is also freedom to shrink the size of
the packages because the package is being used less as a
means of dissipating the heat. This is timely because consumers are requesting more and more in smaller volumes
of space.

THE LATEST IN CMOS TECHNOLOGY
CEMOST • is used to produce the MICROSLICE family with its
two sub-familes - named, respectively, the IDT39COOO Family
and the IDT49COOO Family. These families address microprogrammable designs of the present and future. CEMOS is a
trademark for the proprietary CMOS process technology of lOT.
CEMOS is an enhanced CMOS technology which includes
such features as high ESD protection, latch-up protection and
high alpha particle immunity.

MICROSLICE IN EXISTING DESIGNS
The IDT39COOO family allows the designer to take advantage
of very high-speed CMOS in existing designs. This family is a
pin-for-pin compatible family with the 2900 counterparts. By
replacing the current 2900 parts with IDT39COOO parts in
existing sockets, the power consumption of that portion of the
circuitry may be reduced down to 1/5 to 1110 of the bipolar
power consumption at full operating speeds. The IDT39COOO
family is specified around the highest speed grade versions of
the current bipolar devices. Currently in the IDT39COOO family
are two of the common ALU architectures, the IDT39C01 and
the IDT39C03/203. Included in the family are the sequencers
IDT39C10 and IDT39C09/11. The IDT39C705/707 are registered
file expansions for the IDT39C03/203. The family also includes
the 16 x 16 multipliers, IDT39C516/517, and the 16 x 16
multiplier-accumulator, IDT39C510. Not to be ignored, the
IDT39C60 family is available for high-performance error
correcting memory designs. This family also includes the first
speed upgrade beyond the bipolar technology. The IDT39C01 0
is 25% faster than the 2901C, while the IDT39C01E exhibits
speeds 40% faster than the 2901 C.

APPLICATION NOTE AN-OS

THE IDT49COOO FAMILY, THE NEXT GENERATION
The IDT49COOO family takes advantage of all the benefits that
CEMOS has to offer: high-speed, low-power, very large scale
integration and smaller packages. Because of the new freedoms
imparted by CEMOS, the IDT49COOO family is the next family of
innovation for bit-slice microprogrammed designs.
While the IDT39COOO family minimizes upgrade costs by being
pin-compatible, the IDT49COOO family addresses the aspect by
providing parts in the family which are code-compatible, thus
achieving conservation of previously written code. This is significant because, in the last decade, the cost of the software portion
of the system has surpassed the hardware. The IDT49COOO family, however, is not limited to code-compatible devices and will, in
the future, include devices with new and wider architectures.

THE IDT49C402A 16-BIT ALU PLUS
The first ALU in the IDT49COOO family is the IDT49C402A
which is a 16-bit ALU and register file. This device is a superset
of the 2901 architecture. It is a very high-speed, fully-cascadable
16-bit CMOS microprocessor slice, which combines the standard
functions of four 2901 s and one 2902 with additional control
features aimed at enhancing the performance of bit-slice
microprocessor designs. The IDT49C402A includes all of the
normal functions associated with the standard 2901 bit-slice
operation: (A) a 3-bit instruction field (1o, 11, 12) which controls
the source operands selection of the ALU; (B) a 3-bit
microinstruction field (13' 14 , 15) used to control the eight
possible functions of the ALU; (C) eight destination control
functions which are selected by the microcode inputs (16, 17 , 18);
and (D) a tenth instruction input (19) offering eight additional
designation and control functions. This 19 input, in conjunction
with 16, 17 and 18 allows for shifting the Q Register up and
down, loading the RAM or Q Register directly from the
D inputs without going through the ALU, and new combinations
of destination functions with the RAM A-port output available
at the Y output pins of the device. This eliminates bottlenecks
of inputting data into the on-chip RAM.
The block diagram on page 3 shows the familiar architectures
of the 2901 with register files which have both A and B data
feeding into an ALU data source selector. This combines
together the data from the register file along with direct data
input (D) and the Q Register. The output of the ALU data
source selector produces two operands, Rand S. Rand S are
fed into an eight-function ALU, the output of which can go to
the data output pins or be fed back into the register file and/or
Q Register.

14-42

16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROSLICE COMPATIBILITY YET INCREASE PERFORMANCE

APPLICATION NOTE AN-06

~)'r--------'

H RAM SHIFT

RAMo -

0
1
2
3
4
5

CLOCK~

w

ALU
SOURCE

0

0
U

B DATA IN

0

64 ADDRESSABLE
REGISTERS

0

;:::
U
:::l

a:

l-

...

7
a
9

DESTINATION
CONTROL

z
0

a:

U

:E

"" .".

_--,-,R;.;;;;EA;...;;D;;...;..;A~D~D~R;;;;;ES;;,;S~I"IA ADDRESS

ycP

r

I I

A

r

{J.

0 REGISTER

B

015

I

-=R'-::E~A=D/w=R""'IT=E"':A""D~D::-:R=-=E::O::S~S"IB ADDRESS ~~: ~~:

'"

I/)

6

00 0 SHIFT

CPr-

w

z

ALU
FUNCTION

RAM15

~

I

I

. b-:=,---L=::::;---,
----=D~IR::-!ECT DATAIN
I I
V
{>'''Ii >'

~OGIC
0
r::=r------__

ABO

O

...J

{yQ

ALU DATA SOURCE SELECTOR
R
S

R
CARRYIN-

-

MSS-

-

S

a-FUNCTION ALU

r-G/FIS
r--P/OVR

r- C n + 16
r--F=O

OUTPUT ENABLE

~

DATAoUT
IDT49C402A 16-Bil Microprocessor Slice.

WHERE THE IDT49C402A EXCELS
The IDT49C402A, however, differs from the regular 2901
architecture by the addition of a new data bus that goes from
the direct data input pins (D) into the register file and the Q
Register, thus providing a data path directly into the register
file and Q Register rather than passing through the ALU block.
With conventional 2901 architecture, in order to get data into
the register file the ALU must be placed in the pass mode
taking data directly from the D inputs through the ALU and
around to the register file. With this new architecture, data can
be operated on out of the register file and the Q Register and
the result placed back in the Q Register while new direct data
is being brought into the register file. Conversely, the Q
Register can be loaded while operations are being performed
on the register file and placed back into the register file.
Whereas the 2901 has a 16-deep register file, the IDT49C402A
has 64 addressable registers. The 2901 architecture does not
allow for direct cascading of the register file. Dead cycles can be
eliminated because 4 times more data can be cached on-chip
with the ALU. Other applications may use the 64 registers as four
banks of 16 registers. The bank selection could be thought of as
task switching for interrupt-driven multi-tasked applications.
The third difference from the 2901 is the ALU expansion
mechanism. The IDT49C402A incorporates an MSS input which

programs the device, being the most significant device or not.
When not the most significant slice, the P & G signals are
brought out. When the most significant slice, the sign and
overflow are brought out on the P & G.

IDT49C402A 16-Bit ALU Destination Functions
RAM

2901
Functions
(3-Bits

16- 18

-

IgHIGH

Load F
Load F

Added
IDT
Functions
(1 Additional
Bit Ig)
IgLOW

14-43

F-Up
F-Up
F-Down
F-Down
-

Load
Load
Load
Load

-

D
D
F
F

Y-OUT

-

F
F
F
F
F
F
F
A

Load F
Load F
Load D
Load D
a-up
a-Down
Load D

F
A
F
A
F
F
F
F

-

a-Down
-

Load F

Load D

-

0
a-up

-

16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROSLICE COMPATIBILITY YET INCREASE PERFORMANCE

APPLICATION NOTE AN-06

CODE CONSERVATION

THE IDT49C402A IS COOL

The microinstruction word of the IDT49C402A looks the
same as the 2901 with the exception of the additional destination control line called 19 , Conservation of microcode can be
achieved via two methods. The first and the most simple
method is to tie the instruction line 19 high on the socket and
not connect it to the microcode. In this way, the remaining
destination control lines la, 17 and 16 are compatible to the 2901.
For those systems that intend to add morecode, or rewrite
code for' performance optimization, the second method is
performed by making minor alterations on the microcode. For
many designers this can be a fairly easily-achieved task by
making minor alterations in the meta assembler used to compile
the microcode source. The alteration in the meta assembler
would add 19 such that all previously written code would have
this signal default to a Don't Care state of high, thus enabling
the standard destination instructions (the traditional 2901 codes).
Additional code could then be written which utilizes this
instruction line and the extra features provided in the IDT49C402.
An alternative to the second method for achieving microcode
compatibility would take the already-compiled microcode. and
run it through a simple program, written in another language,
which would spread the microcode apart and introduce in this
additional instruction bit. This method is used for microcode
which no longer has existing source.

Even though the IDT49C402 has five times the circuitry
on-chip as does the 2901, it is 1/2 the power of just one 2901.
The 16-bit solution of the IDT49C402A is 1/8 the power of
four 2901Cs and one 2902A. While total power consumption is
the concern of many designers because it has impact on power
supplies and cooling systems, the lower power consumption
also provides other benefits. Because less power is being
consumed less of the package is needed as a heat sink. This
allows for packages with much smaller outlines. Besides being
offered in a standard 68-pin PGA, the IDT49C402A comes in a
68-pin dual in-line package with pins on 70 mil centers, 600 mils
wide, which yields a package with an outline of 2.5 x 0.6 inches.
A 68-pin LCC with pad spacing of 25 mil centers, as well as a
standard 68-pin LCC with pad spacing of 50 mil centers, are
offered. When the board space taken up by just the packages
are added up, the LCC version of the IDT49C402A is
0.32 square inches, as opposed to 1.8 square inches for four
2901Cs and a 2902A. Respectively, the IDT49C402A in the
SHRI NK-DI P package (70 mil centers) is 1.5 square inches as
opposed to 5 square inches for four 2901 Cs and a 2902A. Not
included in the calculations for the multi-chip solutions is the
spacing between the ICs.
The next ALU, soon to be introduced in the IDT49COOO
family, is the IDT49C403 which will be a 16-bit version of the
2903/203. This device will be at least as fast as the four 2903s
and a 2902A. and will consume 1/5 to 1/10 the power of the
multi-chip solution.

ONE IDT49C402A WINS
RACE AGAINST FOUR 2901s
While the IDT49C402A seeks to improve performance
through architectural enhancements, it also achieves improved
performance through raw technology. The IDT49C402A
achieves an A and B address to Y output of 41 ns for military
and 37ns for commercial temperature ranges, as compared to
four 2901Cs and a 2902A which have A and B to Y and flag of
80ns for military and 68ns for commercial. Thus the
IDT49C402A is 45% faster than five discrete parts of the older
2900 family. the IDT49C402A could achieve processing of
approximately 15 MIPS.

COMPARISON OF 1S-BIT
MICROPROGRAMMED SOLUTIONS
IDT49C402A
CMOS

4 - 2901C
& 2902A
BIPOLAR

29116
BIPOLAR

Dynamic
Power(l)

125mA

1049mA

735mA

ABI- Y/FLAG(l)

37ns

68ns

84ns

Package
Space
Sq. Inches

0.32 LCC
1.5 DIP

1.8 LCC
5.04 DIP

0.56 LCC
2.08 DIP

Features

ALU
64 RAM
Q REG
SHIFTER

ALU
16RAM
Q REG
SHIFTER

ALU
32 RAM
ACCUM
BAR. SHIFT

.-

NOTE:
1. Reflects performance over commercial temperature and voltage range.

A 1S-BIT SEQUENCER TO MATCH A 1S-BIT ALU
While ALUs provide the data path for performing computations, the sequencer is another important building block which
orchestrates the entire machine. The first sequencer in the
IDT49COOO family is the IDT49C410. The IDT49C410 is
architecture- and function code-compatible to the 2910A, with
an expanded 16-bit address path which allows for programs up
to 64K words in length.
The IDT49C410 is a microprogram address sequencer
intended for controlling the sequence of execution of microinstructions stored in microprogram memory. Besides the
sequential accesses, it provides conditional branching to any
microinstruction within its 64K word range.
While the 2910A incorporates a 9-deep stack, the IDT49C410
has a 33-deep stack which provides micro subroutine return
linkage and looping capability. This deep stack can be used for
highly nested microcode applications.
'Referring to the block diagram on page 5, it can be observed
that, during each microinstruction, the microprogram controller
provides a 16-bit address from one of four sources: 1) the
microprogram address register (,.lPC) which usually contains
an address one greater than the previous address; 2) an
internal direct input (D); 3) a register/counter (R) retaining data
loaded during a previous microinstruction; or 4) a last-in firstout stack (F).
The IDT49C410 is completely code-compatible with the
2910A. This allows the IDT49C410 to execute previously written

14-44

16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN'
MICROSLICE COMPATIBILITY YET INCREASE PERFORMANCE

APPLICATION NOTE AN-OS

CP

RLDC:>~-----------------I

33-WORD
X
1S-BIT
STACK
r---r------,-~_I OUT

IN
DECREMENT!
HOLD!LOAD

II

4

R

=0

INSTRUCTION
PLA

CI

IDT49C410 1S-BII Microprogram Sequencer.

microcode, while allowing for more microcode to be added to
the application and taking the program beyond the 4K word
boundary. Because the IDT49C410 is microcode-compatible,
older microcode routines can be incorporated in new designs
utilizing the IDT49C410.
The 16-bit IDT49C410 uses approximately 1/4 the power
consumption of the 2910A (which is a 12-bit sequencer), thus
maintaining the 1/5 power consumption on a bit-by-bit basis.
The IDT49C410 consumes, over frequency and temperature
ranges, 75mA for commercial and 90mA for military. The
2910A compares with 340mA for military and 344mA for
commercial. Because of the lower power consumption, smaller
packaging may be utilized. While the IDT49C410 is offered in a
standard 600 mil wide package with pins on tenth inch spaces,

it is also offered in a package which is 400 mils wide with pins
on 70 mil centers. This is roughly 1/2 the standard package
with regards to area taken up by each package.

COMPARISON OF
MICROPROGRAM SEQUENCERS
IDT49C410A

IDT49C410

2910A

CC-Y(1)

15ns

24ns

24ns

Stack Deplh

33

33

9

Address Range

64K

64K

4K

Dynamic Power(l)

75mA

75mA

340mA

NOTE:

1. Reflects performance over commercial temperature and voltage range.

19
I

t

14-45

16-BIT CMOS SLICES - NEW BUILDING BLOCKS MAINTAIN
MICROSLICE COMPATIBILITY YET It~CREASE PERFORMANCE

WORKING TOGETHER
The simplified block diagram of an example Central Processing Unit (CPU) is shown below using devices manufactured
by IDT. This CPU architecture can be viewed as two major
sections which have a MICROSLICE family part at the heart of
each. The major section of the left hand side of the diagram is
the control path. The microprogram sequencer at the heart is
the IDT49C410 which generates the address for the microprogram stored in the writeable control store (WCS). The
output of the WCS is registered by the pipeline register.
Together, the sequencer, WCS and pipeline register make up a
state machine which controls the operation of the entire CPU.
In this CPU, the state machine first fetches a machine instruction and captures it in the instruction register. The instruction
register determines the starting address for each sequence of
microinstructions associated with each machine opcode.
In this example, both the microprogram store and the
instruction mapping memory are formed using RAM. The RAM
has separate DATAIN and DATAoUT buses (IDT71682). This
allows the input side to be connected conveniently to an 8-bit
bus for initialization at power up.
The second major section is on the right hand side. This
section is called the data path. The heart of this section is the

APPLICATION NOTE AN-06

IDT49C402A. In it is contained all of the working registers and
the arithmetic logic unit for performing data computations.
One of the internal registers always contains the value of the
program ~ounter (PC) which is the address at which the
opcode for the machine instruction is fetched. When an opcode
is fetched, the memory address register (MAR) is loaded with
the value of the PC while, at the same time, the value of the PC
plus one is loaded back into the internal register file. The
DATAIN and DATAoUT registers are used to buffer data coming
from and going to the memory during execution of the machine
instruction.

CONCLUSION
The MICROSLICE family from lOT provides high-performance
CMOS solutions for microprogrammed applications. Not only
does the family provide for yesterday's designs with plugcompatible devices of the IDT39COOO family, it also provides
solutions for future applications. With the IDT49COOO family, the
designer can take advantage not only of the lower power consumption of CMOS, but utilize higher speeds and smaller board
spacing, yielding smaller packaging concepts required by
today's customers. In the future, the IDT49COOO MICROSLICE
family will provide alternative architectures which will provide
for yet higher performance solutions.

D
ALU
AND
REGISTER
FILE
IDT49C402
Y

IDT49C410
16
ADDR
WRITABLE CONTROL STORE
1DT71682

CONTROL BUS

14-46

By David C. Wyland

ABSTRACT

DESIGN OF A CACHE MEMORY

Cache memories are a widely used tool for increasing the
throughput of computer systems. The I 0T717 4 Cache Tag RAM is
a new component designed to support direct mapped cache
designs by providing the tag comparison on-chip. This allows.
relatively large cache memories to be designed with low chip
count. The application of the I OT717 4 to cache memory design is
explored by designing a simple cache memory, reviewing its
operation and performance, discussing methods of extending the
design, and then reviewing the theory behind the design of cache
memories in general.

To understand the application of the IOT7174 to cache memories, we will begin by designing one. A block diagram of a cache
memory system using IOT7174 Cache Tag memory chips is
shown in Figure 2. The cache memory serves a 16-bit microprocessor with a 24-bit address bus and a main memory. In this
system, the 13 least significant bits of the address bus are connected to the address inputs of both the cache tag and the cache
data RAM chips. The upper 11 bits of the address bus are connected to the data liD pins of the cache tag RAMs. The remaining
five I/O pins of the cache tag RAMs are connected to a logic
1 (+5).

INTRODUCTION
Cache memories are an important design tool for increasing
computer performance by increasing the effective speed of the
memory. Computer memories are usually implemented with slow,
inexpensive devices such as dynamic RAMs. A cache memory is a
small, high-speed memory that fits between the CPU and the main
memory in a computer system. It increases the effective speed of
the main memory by responding quickly with a copy of the most
frequently used main memory data. When the CPU tries to read
data from the main memory, the high-speed cache memory will
respond first if it has a copy of the requested data. Otherwise, a
normal main memory cycle will take place. In typical systems, the
read data will be supplied by the cache memory over 90% of the
time. The result is that the large main memory appears to the CPU
to have the high speed of the cache memory.
The 10T7174 Cache Tag RAM introduced by lOT simplifies the
design of high-speed cache memories. It can be used to make a
high-performance cache memory with a low part count. The
I OT717 4 Cache Tag RAM consists of a 64K-bit static RAM organCache
Word Address
RAM Write
RAMCloar

Output

Enable

-----+-----1...(Data Input Pins.
RAM Data Output)

each. Address
Compare Jnpul

Figure 1: IDT7174 Cache Tag RAM Block Diagram

ized as 8K x 8 and an 8-bit comparator, as shown in Figure 1. The
comparator is used in direct mapped cache memories to perform
the address tag comparison, and allows a 16K byte cache for a
68000 microprocessor to be built with four memory chips. The
I OT717 4 also provides a single pin RAM clear control which clears
all words in the internal RAM to zero when activated. This control
is used to clear the tag bits for all locations at power-on or
system-reset when the cache is empty of data. This allows one of
the comparison bits to be used as a cache data valid bit.

Cl

~--:'::"'-------'""'I"--"I"""---.I Data

I---r---..:::,...-"""'T--r-----+--+----.I

Addrs

I
Figure 2: Cache Memory System Block Diagram

The MATCH outputs of the cache tag rams are tied together
and connected to the WAIT input of the microprocessor. A 330
ohm pull-up resistor is used because the MATCH outputs are
open-drain type. The MATCH outputs are positive-active. The
MATCH output goes high when the contents of the internal RAM
are equal to the data on the liD pins. When several cache tag
RAMs have their MATCH outputs connected together, a wireANO function results: all of the comparators must each register a
match before the common MATCH signal can go high.
In the system shown, the state of the WAIT input to the microprocessor determines whether the memory data is to come from
the cache or the main memory. If the WAIT input to the microprocessor is high, the microprocessor will accept data immediately from the cache data RAMs; if the WAIT input is low, the
microprocessor will wait for the slower main memory to respond
with the data.
To understand how the cache memory operates, we will follow
its operation from start-up in an initially empty state. When the
system is powered-up, the cache tag RAMs are cleared to zero by
a pulsetothe initialize pins of the IOT7174 RAMs. This causes all
cells in the RAM to be simultaneously cleared to logic zero. When
the microprocessor begins its first read cycle, the 13 least significant bits of the address bus select a location in the cache tag
RAMs. The location in the cache tag RAMs is compared against
the upper bits of the address bus and against five bits of logic one;

Printed in the U.S.A.

t986 tntegrated Device Technology. Incorporated

14-47

7/86

[9
~

APPLICATION NOTE AN-07

CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN

The MATCH output of the cache tag RAMs will be low because all
cache tag RAM cells were reset to zero, and the zeros from the
selected cell are being compared against the five bits of logic
one. In this case, the microprocessor waits for the slower main
memory to respond. This is called a cache miss.
When the main memory responds with read data for the
microprocessor, this data is also written into the cache data
memory at the address defined by the 13 least significant bits of
the address bus. At the same time, the upper 11 bits of the
address bus and the five bits of logic one are written into the
cache tag memory. This 11-bit address tag, in combination with
the 13 bits of RAM address select, uniquely identify the copy of
the main memory data that was stored. The five logic one bits
serve as a data valid bits which indicate that the data in the cell is a
valid copy of main memory data.
When the microprocessor requests data from the same location that has been written into the cache, the upper address bits
on the address bus will be the same as the bits which were
previously written into the cache tag RAM an d the MATCH signal
will go high. This is called a cache hit. In this case, the cache data
is gated onto the data bus and the memory cycle is complete.
If the microprocessor requests data from an address with the
same 13 least significant bits as a word in the cache, but with
different upper address bits, a cache miss will result and the
current (more recent) data will be written into the cache. In this
manner, the cache is continuously updated with the most
recently used data.
Memory write cycles are treated differently from read cycles.
On write cycles, data is written directly into main memory and
into the cache. This is called the write-through method of cache
updating. Since all data is written immediately into main memory,
it always contains current information. Data is written into the
cache on full word writes or on byte (Le. partial word) writes if a
match occurred. Writing bytes into the cache only if a cache
match occurs ensures that the full word in the cache is valid. For
example, this ensures valid data for a byte write followed by a
word read.
The design in Figure 2 uses unbuffered writes. In unbuffered
writes, all write cycles occur at main memory speeds. This slows
down the system for all write cycles at the expense of simple
memory controls; however, this may be acceptable since only
15% of all memory cycles are write cycles in typical programs.
Buffered write is a slightly more complicated method which
improves performance. In buffered write cycles, the write data
and address are loaded into registers, and the main memory write
cycle proceeds in overlap with other processor operations. Since
the next few cycles will probably be read cycles and their data will
come from the cache, the result is that buffered write cycles are
as short as cache read cycles.

CACHE MEMORY DESIGN: PERFORMANCE
Even a simple cache memory can improve system performmance. For a simple, 16-bit cache system such as described
above: a hit rate (percentage of 'read cycles that are from the
cache) of 68% can be expected. If IDT7174 Cache Tag RAMs and
IDT7164 cache data RAMs are used, an access time at the chip
level of 35ns results and a corresponding system cache read or
write cycle time of 50ns is practical. Assuming a system cact)e
access time of 50ns and a main memory system access time of
250ns, the average access time of an unbuffered cache would be
134ns and the average access time of a buffered cache would be
104ns. This corresponds to an improvement in access time of
1.9:1 and 2.4:1, respectively.

CACHE DESIGN DETAILS: CONTROL LOGIC
Figure 3 shows a block diagram of a control logic design and a
typical timing diagram for the cache memory of Figure 2. The
vertical lines in the timing diagram represent 50ns timing intervals. The microprocessor is assumed to have a 50ns clock and a
100ns memory cycle time. In the timing diagram and associated
logic, a Read/Write Timing signal is used to determine whether to
use the cache data or to start the main memory. This timing signal
is the memory read/write request signal from the CPU delayed by
37ns; the address-to-match time of the IDT7174.lf main memory
is used, this timing signal is used to write the main memory data
into the cache RAMs on both the main memory read and write
cycles. Data is written into the cache on write cycles only if there
is a match or if it is a word write operation. The state of the
MATCH line is latched by the Read/write Timing signal so that it
remains stable during cache write operations.

~ReadlWrile nming

Start Main Memory

~-

---'

~ ===

Main Memory Busy

RAM

Wr~a

-

Enable

OE· Data RAM
OulputEnable
R8adN.Jf~8 Timing

--'----if---t---.-L.I

Main Memory B u s y - - - - - - 1 r - - + - - + - L J

WrileWord - - - - - - - '

m1i(IOuP)

WSWr~eloTag
and Data RAMs

Figure 3: Cache Memory Control Timing and
Logic Block Diagrams

CACHE DESIGN DETAILS:
UNCACHED ADDRESSES
In the above cache design, we have assumed that all parts of
memory are cached; however, there are significant exceptions to
this assumption. Hardware I/O addresses should not be cached
because they do not respond in the same way as normal memory
locations. Bits in an I/O register can and must change at anytime,
asynchronously, with respect to the rest of the system. A cache
copy of an earlier I/O state is clearly not a valid response to an I/O
read request under these conditions. Also, an I/O register
address may be used for different functions for read and write, so
that what is read will not be the same as what was written. For
example, write-only control bits will not appear when read, and
read-only bits will not be affected by write operations. For these
reasons, hardware I/O addresses must always force cache
misses. This can be accomplished by adding an I/O address
decoder to the memory address bus to force a cache miss. (This
decoder aleady exists in many systems to enable the I/O
subsystem.)

CACHE DESIGN DETAILS: DMA ADDRESSES
Direct Memory Access (DMA) allows I/O devices such as disk
controllers to have direct access to main memory by temporarily
stopping the CPU and taking control of the memory address and
data busses. If DMA devices are allowed to write into main
memory without updating the cache memory, cache data could
become invalidated because it would no longer be a copy of the

14-48

CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN

APPLICATION NOTE AN-07
'11<

contents of main memory. The simplest solution to this problem
is to have the cache monitor the memory bus and be updated if an
address match occurs in the same manner as CPU write-through
operations. Otherwise, the liD DMA buffer areas of memory must
be forced to be uncached in the same manner as hardware liD
addresses.

CACHE DESIGN DETAILS:
EXPANDING THE CACHE IN WIDTH
The cache as described above, can be expanded in both width
and depth. For a 32-bit system, two additional IDT7164 cache
data RAMs (for a total of 4 chips) will be required to store the
32-bit data words. A block diagram of a 32-bit cache system, with
a 32-bit address bus, is shown in Figure 4. Compared with Figure
2, the number of cache data RAMs has been expanded from two
to four to handle the expansion of the data bus from 16 to 32 bits,
and the number of cache tag RAMs has been expanded from two
to three to handle the expansion of the address bus from 24 to 32
bits.

doubled the effective access time of the main memory but have
cut the miss rate by less than half, yielding a net decrease in
performance.

CACHE DESIGN DETAILS:
EXPANDING THE CACHE IN DEPTH
The cache memory can be expanded in depth by adding
copies of the cache tag and data chips and using upper bits of the
address bus for chip enable selection. An example of an
expanded cache is shown in Figure 5. The primary reason for
increasing the size of the cache memory is to decrease the miss
rate percentage. For example, increasing the cache size from
8Kx 16 to 16Kx 16 decreases the estimated miss rate from 32%
to 22%.

Tag BM from AddreSS Brrs

Data to! from pata RI 'S

A14-A23. Logic 1

:!----r-t~

BKx16

H----~~

Cach.
Tag RAM
2x

I0T7174
A13---r-t--~E

t+-----~I

t--'---------.MATCH

Figure 5: Depth Expanded Cache Memory System
Figure

4: 32-81t Cache Memory System

Note that the cache memory system uses the memory address
lines corresponding to the 32-bit words stored in the cache. If a
byte addressing memory address convention is used, the least
significant bit of the address lines going to the cache RAM chips
is A2, with A 1 and AO used to select the byte(s) within the word to
be read or written in the cache data RAMs.
There is a benefit to expanding the cache width by adding data
RAMs: the miss rate improves. The miss rate improves because of
the increase in width, as well as in the amount of data stored. The
miss rate for a 8K x 32-bit cache is estimated at 12.4%, as compared to 32% for a 8Kx 16-bit cache. Doubling the cache width
by adding RAM chips doubles the amount of data stored. We
would expect an improvement in miss rate due to the increased
probability of finding the data in the cache.
There is an additional improvement in miss rate, however,
specifically due to the increase in width. This is because there is a
high probability that the next word the CPU wants is the next
word after the current one. If the cache width is doubled, there is
a 50% probability that the next word is already in the cache,
fetched from main memory along with the current word.
Studies have shown that the miss rate is cut almost in half for
each doubling of the cache data word width - called line size in
cache theory - up to 16 bytes and larger (Smith 85). The disadvantage of very wide cache data word width is either a wide main
memory data bus or complex logic to transfer the word to the
cache in a high-speed serial burst. Simply doubling the number
of main memory cycles does not work well because you have

CACHE DESIGN DETAILS:
SET ASSOCIATIVE EXPANSION
A better way to expand the cache memory in depth is called set
associative expansion (shown in Figure 6), and its control logic
(shown in Figure 7). In this example, we have two independent
cache memories which results in a two-way set associative
cache. If a match is found in one of the memories, its data is gated
to the data bus. If no match is found, one of the two memories is
selected and updated. Selection of one of the two memories for
cache write update is done by using an additional8K x 1 memory
to hold a flag for each cache word, indicating which memory was
read last. This way, the least recently used cache word of the pair
is updated.
The cache system described above attacks the problem of
having two frequently used words mapped to the same cache
word. For example, if a program loop included an instruction at
20082 (hexadecimal) and called a subroutine at 80092, the cache
word 0082 would be alternately registered as a cache miss and
updated with memory data from each of these two addresses.
The above design solves this problem by having two independent
memories. One would cache the instruction at 20082 and the
other would cache 80082.
Two way set associative expansion, while more complex in
control logic, achieves a better miss rate. For example, the estimated miss rate for a 16K x16 set associative cache is 18% versus
22% for a simple 16K x 16 cache.

14-49

19
~

APPLICATION NOTE AN-07

CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN

nata tpl fmm Data e.lS

Tag enS from Address 6,IS

AO-AI2

Cache
Control
Logic
Read ------~

WrtteEnable
to TaO'Data RAMs
Write Enable
toLRU RAM

Wrtte ------~
WriteWord

called fully associative because access to the data in each
memory cell is through its associated, stored address. This type
of memory is expensive to build because the address cell and
address comparator are generally several times larger, in terms of
chip area or part count, than the data cell. Also, the address
comparator required for each associative memory cell makes the
design of the cell different from that of standard RAM memory
cells. This makes a fully associative memory a custom design,
precluding the use of efficient standard RAM designs.

- - - - - - - t_____..J

Figure 6: 2-Way Set Associative Cache Memory System

Write Enable

Figure 8: Cache Memory Cell Block Diagram
ACTlON

FUNCTION

MATCH

Read

Y..

Writ_

Y..

Enable corresponding data RAM for writ.

No

Writ. main memory data Into LRU RAM

No

Wrt. data into LRU RAM

Read
Writ. Word

CACHE THEORY: WHY IT WORKS

Enable corresponding data RAM for read

ReadIWrita-,,-----------,
TIming

Writ. Word

-j--r.:J')..I:=:::;::R-""1

~o

All Upper RAMs

~o
All Lower RAMs
LowerWu
Read Last

--"1---+-+--++'-1

MATCH

UpporRAM

MATCH
lower RAM

~~~ ==:t::=====lJ

~to
Upper Data RAMs

~to

L.owet Data RAMs

cmpEi1a6Ti"
Tming to
All RAMs

Figure 7: 2-Way Set Associative Cache Control Logic
Block Diagram

CACHE THEORY: HOW IT WORKS
A cache memory cell holds a copy of one word of data corresponding to a particular address in main memory. It will respond
with this word if the address on the main memory address bus
matches the address of the word stored. A cache memory cell
therefore has three components. These components are an
address memory cell, an address comparator, and a data memory
cell, as shown in Figure 8. The data and address memory cells
record the cached data and its corresponding address in main
memory. The address comparator checks the address cell contents against the address on the memory address bus. If they
match, the contents of the data cell are placed on the data bus.
An ideal cache memory would have a large number of cache
memory cells with each of them holding a copy of the most
frequently used main memory data. This type of cache memory is

Cache memories work because computer programs spend
most of their memory cycles accessing a very small part of the
memory. This is because most of the time the computer is executing instructions in program loops and using local variables for
calculation. Because of this observation, a 64K byte cache can
have a 90+% hit rate on programs that are megabytes in size.

HOW THE DIRECT MAPPED CACHE WORKS
The direct mapped cache memory is an alternative to the
associative cache memory which uses a single address comparator for the cache memory system and standard RAM cells for the
address and data cells. The direct mapped cache is based on an
idea borrowed from software called hash coding which is a
method for simulating an associative memory. In a hash coding
approach, the memory address space is divided into a number of
sets of words with the goal of each set having no more than one
word of most-frequently-used data. In our case, there are 8K sets
of 2048 words each.
Each set is assigned an index number derived from the main
memory address by a calculation which is called the hashing
algorithm. This algorithm is chosen to maximize the probability
that each set has no more than one word of most-frequently-used
data. In the direct mapped cache, the hashing algorithm uses the
least significant bits of the memory address as the set number.
This uses the concept of locality, which assumes that the most
often used instructions and data are clustered in memory. If
locality holds, the least Significant bits of the address should be
able to divide this cluster into individual words and assign each
one to a separate set.
A memory map of a direct mapped cache of Figure 2 is shown
in Figure 9 as an example of how the main memory words are
related to the cache words. The 16M Word main memory is
divided into 8K word pages, a total of 2048 pages. Each word
within each 8K page is mapped to its corresponding word in the
8K words of the cache; i.e., word 0 of the cache corresponds to
word 0 in each of the 2048 pages (8K sets at 2048 words/set).

14..;.50

\

APPLICATION NOTE AN-07

CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN

Each word in the cache stores one word out of its set of 2048
corresponding to one of the 2048 possible pages. Both the data
word and the page number (Le. upper address bits), are stored.
Since only one word in each set (one of 2048 words in our
case) is assumed to be one of the most-frequently-used words,
each set has a single cache memory cell associated with it. This
cache cell consists of an address cell and a data cell, but no
comparator. One comparator is used for the cache memory system since only one set can be selected for a given memory cycle
and only one comparison need be made. In a memory cycle, one
set is selected, and the single cache address cell for that set is
read and compared against the memory address, and the data
from the cache data cell is placed on the bus if there is a match.
The advantage of this scheme is that a single comparator is used,
allowing standard RAM memories to be used to store the cache
address and data for each set.
MAIN

\

100% cache miss or 100% cache hit for the unbuffered and
buffered cases, respectively.

CACHE SYSTEM PERFORMANCE: MISS RATE
One of the key parameters in a cache memory system is the
miss rate. Miss rate figures are estimates derived from statistical
studies of cache memory systems. The miss rate is an estimate
because it varies, often significantly, with the program being run.
Miss rate estimates for various cache memory configurations are
given in Table 1. Miss rates for one example of two-way set
associative expansion are also shown in this table.
Size:
WordsfTag RAM

Miss Rate for Cache Data Word Width - Bits
16

32

64

2K

0.57

0.23

0.10

0.04

4K

0.40

0.18

0.07

<0.04
<0.04

8K

0.32

0.12

0.05

16K

0.22

0.09

<0.04

<0.04

16K (8K + 8K)

0.18

0.07

<0.04

<0.04

MEMORY

Notes

128

2-way Set Assoc

Table 1.

DIRECT MAPPED
CACHE
ADDRESS TAG
RAM PAGE

DATA
RAM PAGE

The miss rate estimates given in Table 1 are derived from
simulation studies. (See references.) These studies covered
cache sizes of up to 32K bytes and cache data word widths
(called line sizes in cache terminology) from 4 bytes through 64
bytes. In the case of 16-bit word width caches, the figures given
are extrapolations from the 32-bit data. Also, the figures for
cache sizes above 32K bytes (Le., 16K x 32, etc.) are extrapolations
from 32K byte data.

CACHE SYSTEM PERFORMANCE FOR
READ CYCLES
CACHE DEPTH = PAGE SIZE
DATA STORED AT SAME PAGE
OFFSET IN CACHE AS IN MAIN
MEMORY

Cache memory system performance is determined by the
access time of the main memory, the access time of the cache,
the miss rate (the percentage of memory cycles that are not
serviced by the cache) and the write time. The effective access
time of a cache memory system can be expressed as a fraction of
the main memory access time. This dimensionless number, Ps, is
a measure of cache performance. If we consider read cycles only,
the access time of a cache memory system is:

Figure 9: Cache System Memory Map

The cache cell for each set should hold the data that was most
frequently used. However, since we do not know which data was
the most frequently used until after the program is run, we
approximate it by storing the most recently used data and replacing the least recently used (oldest) data. In the direct mapped
cache, this is done by replacing the cache cell contents with the
newer main memory data in the case of a cache miss.

CACHE PERFORMANCE
A cache memory improves a system by making data available
from a small, high-speed memory sooner than would otherwise
be possible from a larger, slower main memory. The performance
of a cache memory system depends upon the speed of the cache
memory relative to the speed of the main memory and on the hit
rate or percentage of memory cycles that are serviced by the
cache.
The cache performance equations below express the idea that
the average speed of the cache memory is the weighted average
of the cycle times for cache hits plus the main memory time for
cache misses, with memory writes dealt with as a special case of

Ts

= (1

Ps

= Ts/Tm = (1

- M)Tc + MTm

= (1

- M)Tc + MTm

- M) (Tc/Tm) + M

= (1

- M)Pc + M

Where:
Ts = Cache average system cycle time, averaged over read
and write
M = Miss rate of cache
Tc = Cache cycle time, read or write (assumed to be
equal)
Tm = Main memory cycle time, read or write (assumed to
i9~
be equal)
Pc = Cache memory access time as a fraction of main
memory cycle time
Ps = Cache system access time as a fraction of main
memory access time
If the miss rate of a cache memory is 100%, Pc =1.00. If the
cache memory is infinitely fast corresponding to a cache access
time of zero, Pc will be equal to the miss rate, M. For real cache
memories, the access ti me of the cache is finite. This means that
the cache system access time will approach the cache access
time as the miss rate approaches zero. This is shown in
Figure 10.

14-51

CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN

CACHE SYSTEM PERFORMANCE IN TERMS OF
AVERAGE MEMORY ACCESS TIME

1.000
Curve tor 'Cache system
wtth Pc-O.l00

Althoughcache memory systems can be evaluated in terms of
the dimensionless performance parameter, Ps, you often need to
calculate the actual access time for a specific system. This is
expressed by:

0.100

~
~

APPLICATION NOTE AN-07

~

B.I.tI2.....f.I
0.010

Ts = R((1 - M) Tcr + MTmr) + WTw
Curve for ideal cache system
wtthPc_O
(zero access time cache)

Where:
Ts = Cache average system cycle time, averaged over
read and write
R = Percentage of memory cycles which are read cycles
= 85% typical
W = Percentage of memory cycles which are write cycles
= 15% typical
M =Miss rate of cache = 10+% typical
Tcr = Cache read cycle time
Tmr = Main memory read cycle time
Tw = Write cycle time: main memory for unbuffered write,
cache for buffered

0.001 '--------1I-----t----~
0.100

1.00

0.010

0.001

Figure 10: Cache Access Time vs Miss Rate for Read Cycles

CACHE SYSTEM PERFORMANCE FOR
READ AND WRITE CYCLES
Memory write cycles affect the average access time of the
cache system. In a write-through design, unbuffered write cycles
are equivalent to cache misses, while buffered write cycles are
equivalent to cache hits. Unbuffered write cycles take a main
memory cycle to write data for every write. If the main memory
write cycle time is the same as the read cycle time, this is equivalent to a cache miss. In buffered write, data is written into the
cache and into a register for later off-line write into the memory.
Thus, the write cycle in the buffered write case is equivalent to a
cache cycle. Each write cycle in the buffered case is, therefore,
equivalent to a cache hit. The performance equations for this
case are:

For. typical values:

= 0.85(0.9Tcr + 0.1%mr)

Ts

+ 0.15Tw
= 0.765Tcr + 0.085Tmr + 0.15Tw

=50ns, Tmr =Tw =250ns:
=97.0ns
For buffered write and Tcr =Tw = 50ns, Tmr =250ns:
Ts =0.765(50) + 0.085(250) + 0.15(50) =67.0ns
For unbuffered write and Tcr

=0.765(50)

Ts

+ 0.085(250) + 0.15(250)

Ps = R((1 - M)Pc + M) + W(TwITm)

CACHE SYSTEM PERFORMANCE IN
TERMS OF CPU WAIT STATES

For unbuffered writes:
Ps = R((1 - M)Pc + M) + W
For buffered writes:
Ps = R((1 - M)Pc + M) + WPc
Where:
R = Fraction of total memory cycles that are read cycles
W = Fraction of total memory cycles that are write cycles
Tw =Write time =Tm for unbuffered, Tc for buffered writes
The effect of unbuffered write cycles is to limit the maximum
performance of the cache system. For the average case where
write cycles are approximately 15% of the total number of
memory cycles, this is approximately equivalent to a cache
memory performance of 0.15, as shown in Figure 11.

In many computer and microprocessor systems, the purpose
of the cache memory system is to eliminate CPU wait states,
clock periods where the processor is stopped waiting for the
memory. The cache performance calculations for this condition
are more properly expressed in terms of processor wait states as
follows:
Ncw = R((1 - M) Ncr + (1 - H)Nmr) + WNw

= RMNmr + WNw

~ 0.100

~
~

f!Ill2.....e.I.
0.010

For unbuffered write and Ncr = 0 wait states, Nmr = 3 wait states:

Curve for ideal cache system
wtthPc-O

Ncw

(zero access time cache)

0.001 '--------1I-----t----~
0.100

=0 (no wait states for cache)

Ncw = CPU average number of wait states, averaged over
read and write
R = Percentage of memory cycles which are read cycles
= 85% typical
W = Percentage of memory cycles which are write cycles
= 15% typical
M =Miss rate of cache = 10+% typical
Ncr = Cache read cycle time wait states (typically 0)
Nmr = Main memory read cycle wait states
Nw = Write cycle wait states: main memory wait states for
unbuffered write, cache wait states for buffered

1.000

1.00

If: Ncr

Where:

0.010

0.001

=0.085(3)

1m1 .15(3)

For buffered write and Ncr
states:
Ncw

Figure 11: Cache Access Time vs Miss Rate
for Buffered and Unbuffered Write Cycles

14-52

=0.085(3)

+ .15(0)

=0.535 wait states
= Nw =0 wait states,

=0.255 wait states

Nmr

=3 wait

APPLICATION NOTE AN-07

CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN

CACHE SYSTEM PERFORMANCE IN
TERMS OF CPU THROUGHPUT

Throughput Relative to Uncached System
Miss Rate

The reason for adding a cache to a CPU is to improve throughput by eliminating wait states. CPU throughput improvement, as
a result of adding a cache, can be expressed as the ratio of the
speeds before and after adding the cache. For our purposes,
CPU throughput improvement can be equated to memory
throughput improvement. CPU throughput for this case can be
defined as the CPU clock frequency divided by the number of
clock states per memory cycle. The speed improvement provided
by the cache can therefore be expressed as the ratio of the
throughput with the reduced number of wait states provided by
the cache to the throughput with full wait states:

Fc

= fclk/(No + Ncw)
fclk/(No + Nm)

= (No + Nm)/(No + Ncw)

Where:
fclk = Frequency of processor clock
N = Number of clock cycles per memory cycle
Ncw = Number of wait states for cache system (average)
Nm = Number of wait states for main memory
No = Number of processor states per memory cycle with
no wait states
Fc = Processor throughput relative to throughput without
cache

=

(4 + 2)/(4 + 0.535) =6/4.535 =
1.32 = 32% throughput increase

This is equivalent to increasing the CPU clock speed from
12.5MHz to 16.5MHz.

CACHE MEMORY PERFORMANCE:
HOW MUCH DO YOU NEED?
A simple, direct mapped cache memory system, as described
above, is often the most cost effective design. In many cases, the
effort to decrease the miss rate beyond that of a simple design
may not be worth the increase in system performance.
For example, if Pc is greater than 0.20 corresponding to a
cache access time greater than 20% of the main memory access
time, it may not be cost effective to improve the hit rate above
90%. This is because there is a knee in the curve of performance
improvement versus miss rate at the point where Pc = miss rate,
as shown in Figure 10.ln some cases, even the added expense of
buffered write may not be justified. To examine the relationship
between CPU throughput and miss rate, CPU thorughput
improvement versus miss rate for various microprocessors is
shown in Table 2.

68020
Buffered

RISC
Buffered

1.00

1.00

1.00

1.00

1.00

1.06

1.12

1.19

1.27
1.49

0.60

1.13

1.20

1.32

0.40

1.20

1.28

1.49

1.79

0.20

1.29

1.38

1.71

2.24

0.10

1.34

1.44

1.84

2.56

0.05

1.37

1.47

1.92

2.76

0.00

1.40

1.50

2.00

3.00

Table 2.

The data shown is for three CPU/cache systems. The 68010
microprocessor system has a 12.5MHz clock and a cache with
unbuffered write. The 68020 system has a 16MHz clock and a
buffered write cache. The RISC CPU assumes a 10MHz RISC
computer with a 10MHz clock and a buffered write cache, and
assu mes one clock per memory cycle with wait states equal to an
integral number of clock cycles.
Using the data in Table 2, we can make an interesting comparison between chip count and performance gained over an
uncached system. Table 3 gives this comparison, showing the
chip counts, miss ratios, and performance improvement gain for
simple, depth expanded, and two-way set associative expanded
caches. The chip counts given are for the cache tag and data
RAM chips required, but do not include chip counts for the
control log it. One RAM chip is added for the two-way set associative case for the least-recentry-used cache flag RAM.
68010 Unbuffered

RISC Buffered

68020 Buffered

Chips

Miss

Perf

Chips

Miss

Perf

Chips

Miss

Perf

4

0.32

1.24

7

0.12

1.81

7

0.12

2.49

16K

8

0.22

1.28

14

0.09

1.86

14

0.09

2.60

8K+8K S.A.

9

0.17

1.31

15

0.07

1.89

15

0.07

2.68

8K

Fc

68010
Buffered

0.80

Tag RAM
Size

A 68010 microprocessor requires four clock states per memory cycle, i.e. No =4. Assuming a 12.5MHz clock and 250ns main
memory access time, Nm = 2 wait states. If we use the unbuffered write case from the clock state analysis above, Ncw = 0.535.
The throughput improvement provided by the cache is therefore:

68010
Unbuffered

Table 3.

Table 3 shows that the throughput improvement created by
expanding the cache above a minimum chip count design is
small. This table can be interpreted in two ways. In small systems
where the goal is to achieve high-performance at minimum chip
count, the table indicates that a mimum chip count cache is best
since it buys the most performance improvement per chip; doubling the cache chip count purchased less than 10% further
increase in performance in all cases. In larger systems where the
goal is to achieve maximum performance at moderate chip
count, the table indicates that a further increase in performance
of 5-8% can be obtained by adding fewer than ten chips.

CACHE DESIGNS:
DIFFERENT WAYS TO MAKE ONE

~.
.......~,;

The cache memory described above is a direct mapped cache. ;1::: . ~~~r:
It is a simple, commonly used design with respectable perfor- '.,'
..
mance. Further investigation into the technology of cache
memories will reveal a wealth of other approaches to cache
design. Much of the variety comes from attempts to maximize the
performance of relatively small cache memories typical of earlier
technology. Fortunately, there exists some data to help sort out
the relative value of the various approaches. This data is in the
form of studies on cache memory performance as a function of
cache size, organization, word width, etc., such as the excellent
work done by Prof. Alan Jay Smith of the University of California

14-53

APPLICATION NOTE AN-07

CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN

at Berkeley (see references). These studies provide background
and insight on how to achieve the highest performance out of
cache memory systems, as well as documentation of a wide
variety of cache schemes which do and do not work. The following comments are intended to provide a simplified guide to, and
summary of, some of this data. The following comments are, in
large part, judgments and opinions derived from the data in
various reports and do not necessarily reflect the opinions of the
original authors of the data.

WHAT WE HAVE LEARNED ABOUT
CACHE MEMORY DESIGN
A simple, direct mapped cache as discussed above will give
good performance if it is large enough. The ultimate measure of
cache memory performance is its effect on system cycle time,
which is a function of cache cycle time relative to main memory
cycle ti me and the hit rate of the cache. Given a cache cycle time,
miss rate becomes the measure of cache performance. Improving cache perfomrance, therefore, means improving the hit rate.
However, a simple design with a moderate miss rate may be
sufficient for many applications, giving most of the performance
improvement that could be achieved by a more sophisticated
design.
Much of the work that has been done on cache architecture
and design was aimed at maximizing the performance of relatively small caches, consistent with the capabilities of earlier
technologies. With today's technology, in the form of chips such
as the IOT7174, we can easily make large cache memories at low
chip counts that are atthe upper limit of the earlier technologies.
As a result, much of the sophistication required in smaller cache
designs, in order to achieve an acceptable hit rate, is not required
in today's large cache designs.

CACHE ARCHITECTURE: DIRECT MAPPED
vs SET ASSOCIATIVE
A pure cache memory should be an associative memory, where
the cache contains all of the most recently used data words. The
direct mapped and set associative designs are approximations to
this which sometimes exclude recently used words when there is
more than one frequently used word per set. Fortunately, the
difference between associative, set associative and direct mapped
can be quantified. The ratios of miss rates for set associative and
fully associative, relative to the direct mapped case, are shown in
Table 3A. For example, if the miss rate for a direct mapped design
is estimated at 0.20, the miss rate for a two-way set associative
design of the same size would be (0.78)(0.20) = 0.156.
What this chart tells us is that two-way set associative caches
have a significant performance improvement over simple direct
mapped caches, but there is little additional improvement
beyond four-way set associative designs. As was noted earlier,
the set associative method can often be included in depth
expanded cache designs where the two (or more) sets of cache
hardware required for the expansion can be arranged to work in a
set associative manner.
Cache Type

Ratio of Miss Rate to
Direct Mapped

Direct Mapped

1.00

2-Way Set Assoc

0.78

4-Way Set Assoc

0.70

a-Way Set Assoc

0.67

Fully Associative

0.66

Table 3a.

CACHE SIZE
Cache sizes on commercial systems have tended to range
from 16K to 64K bytes. Caches smaller than 16K can have significantly hi9her miss rates, while caches larger than 64K may not
significantly improve the miss rate. This is shown above in Table
1. Much work has been done on the relationship between cache
size and miss rate; however, most of this work is concerned with
small caches, 32K bytes and under. The IDT7164/1DT7174 combination allows 16K byte cache memory design for 16-bit systems and a 32K-byte design for 32-bit systems using a minimum
number of chips, and can be easily expanded to 64K and larger if
desired.

WRITE THROUGH vs COpy BACK
There are two general approaches to handling the memory
write problem: write through and copy back. I n the write through
approach, memory data is written into main memory as it is
received from the CPU. In the copy back mode, memory data is
written into the cache and flagged with a "dirty write" bit which
indicates that the word has been written into the cache but not
into the main memory. The cache data is copied into main
memory as a separate operation at some later time, and the dirty
write bit is cleared. There appears to be little performance difference between the write through and copy back approaches.
Since the write through approach is simpler in concept and
easier to implement, it is the most often used method.

WRITE BUFFERING
A significant performance increase can be achieved with a
single level of write buffering. Complete write buffering requires
more than one level of buffering to cover the case of two write
cycles closer together than the main memory write cycle time. A
FIFO can be used to buffer more than one word of write data'
however, the FIFO need be no deeper than four words, since n~
further performance results from making it deeper.

SPLITTING THE CACHE:
INSTRUCTION/DATA, SUPERVISOR/USER
Splitting the cache into two smaller caches, one for instructions and one for data, seems like it would improve the hit rate;
however, it doesn't. In theory, the CPU spends most of its instruction cycles in a small part of the program. By caching these
separately from the more random data memory, the hit rate on
the instruction portion should be improved. Alas, the studies
show that splitting the cache into two pieces typically does no
better - and in some cases does a lot worse - than leaving the
cache in one piece. This is, perhaps, because the miss rate for
data is degraded by more than the hit rate for instructions is
improved.

LINE SIZE: MAIN MEMORY WORD WIDTH
vs CACHE WORD WIDTH
We have considered cache sizes where the CPU word width
memory word width and cache data word width are the sam~
size. Performance improvement can result if the main memory
and cache words are wider than the CPU word. If the cache word
width (called the line size) is doubled the miss rate is cut almost in
half. This is because the next word the CPU wants from memory
is often the word adjacent to the one it just used. Increasing the

14-54

APPLICATION NOTE AN-07

CACHE TAG RAM CHIPS SIMPLIFY CACHE MEMORY DESIGN

line size by a factor of two will lower the miss rate by almost a
factor of two up to line sizes of 16 bytes and beyond. This is shown
in Table 4.

Cache Size
in Bytes

Miss Ratio Reduction for Increasing line Size
Une Size (Size of Block From Main Mem to Cache)
4 bytes

8 bytes

16 bytes

32 bytes

4K

1.00

0.586

0.364

0.262

8K

1.00

0.581

0.345

0.222

16K

1.00

0.569

0.330

0.203

32K

1.00

0.564

0.324

0.194

Table 4.

There are two approaches to increasing line size in order to
reduce miss rate: by increasing the memory data bus width, and
by fetching a block rather than a word of data from memory.
Increasing the data bus width (from 16 to 32 bits, for example)
may be practical in some systems where additional performance
is desired.
The other alternative is to transfer a block of bytes to the cache
instead of a single word. This becomes significant in systems
where there is a delay before data transfer from main memory,
but where several words can be transferred quickly after the
initial delay. An example of this concept is the page mode in
dynamic RAM designs. In such a system, there may be an initial
latency of 200ns to begin a memory read cycle but, once started,
the memory may be able to transfer wordS at 1OOns per word for
blocks of up to 256 words. In this case, a line (block) size of 2-4
words may be used to significantly reduce the miss rate with
moderate increase in the main memory cycle time.

SUMMARY
Cache memories have been extensively used in large computer
systems to improve performance. Cache tag RAM chips allow
this technology to be adapted to the small-to-medium system
design at reasonable cost. Simple, direct mapped cache designs
with low chip counts can be used to achieve significant performance improvements. High-performance and low miss rates
are possible with simple designs due to the high speed and
relatively large cache sizes possible with high-speed CMOS
technology.

REFERENCES
[Smith82] Alan Jay Smith, "Cache Memories," Computing Surveys, 14,3, September 1982, pp. 473-530.
[Smith84] Alan Jay Smith, "CPU Cache Memories," April 1986. To
appear in Handb.ook for Computer Designers, ed. Flynn and
Rossman.
[Smith85] Alan Jay Smith, "Line (Block) Size Selection in CPU
Cache Memories," June 1985. Available as UC Berkeley CS
Report UCB/CSD 85/239.
[Smith86] Alan Jay Smith, "The Memory Architecture and the
Cache and Memory Management Unit forthe Fairchild CLJPPER™
Processor," April 1986. Available as UC Berkeley CS Report
UCB/CSD 86/289.
[Smith86b] Alan Jay Smith, "Bibliography and Readings on'CPU
Cache Memories and Related Topics," 1986. from Computer
Science Division, EECS Department, University of California,
Berkeley, CA 94720.

14-55

By Michael J. Miller

INTRODUCTION
is directly related to the speed/power ratio of the technology
used. For several years the speed/power performance advances
in the bipolar bit-slice world have slowed to a mere crawl while
other families have moved ahead. The new wave of very highspeed CMOS has entered the bit-slice world, thereby offering
ever faster and denser functions.
At the current level of technology, the number of gates, or
the speed at which the gates can run in bipolar ICs is limited
by the heat dissipation capabilities of the package which
houses the individual piece of silicon on which the gates are
fabricated. If the speed/power product is lowered, more speed
can be gained from the same number of gates in the package
or more gates can be packaged inside the device at the same
speed. Because high-speed CMOS has a speed/power product
almost an order of magnitude better than bipoloar TTl-ECl
internal, it is becoming the technology of choice for new bitslice functions today. Many more gates, running at higher
speeds than the conventional bipolar technologies, may be
contained in inexpensive packages. This provides more freedom
for new architectures running at higher performance levels.
Therefore, very high-speed CMOS is here just in time to breath
new life into bit-slice ICs.

Today's high-performance systems are composed of multiple
processors and controllers working together. Several decades
ago, in all but the most sophisticated designs, there was one
processor doing everything. Now, the descendants of these
systems are more like multi-cell organisms where each cell is
interacting with other cells and performing a specialized task.
For example, a work station today is composed of a central
processor (80286), a graphic/video controller, a communications controller for ETHERNET or token ring, a mathematics
accelerator and a disk controller (Figure 1). Except for the
main CPU, all of the other elements are dedicated controllers.
When performance counts, microprogram designs today can
provide controller solutions that operate at more than 15 MIPS,
which is an order of magnitude over what a fixed instruction
set processor can provide.
The requirement for many of today's system designs to
provide the highest performance possible means there is a
requirement for high-performance solutions such as microprogram architectures. The performance benefit, however, must
always be traded off with the cost in terms of power consumed
and number of parts In the design solution. The power and
parts count for a solution provided by a given family of devices

ACCELERATOR

COMMUNICATIONS
CONTROLLER

MAIN CPU

GRAPHICS
CONTROLLER

SYSTEM
MEMORY

DISK
CONTROLLER

Figure 1: Work Station with Floating Point Math Accelerator
MICROSLICE is a trademark of Integrated Device Technology, Inc.
c 1986 Integrated Device Technology. Inc.

14-56
-------------- - - - - - -

Printed in U.S.A.

11/86

APPLICATION NOTE AN-oS

CMOS BREATHES NEW LIFE INTO BIT-SLICE

results in approximately 1 to 1.5 MIPS which is a theoretical
number that exceeds actual benchmarks for the 68000. Through
many years of optimizing the architecture and the instruction
set, the fixed instruction microprocessors have become very
good at performing general purpose-typ~ computations. Because
the instruction set is fixed and has been added to over the
years, previous software written from these processors has
been brought forward, creating a very rich base of application
software to solve all sorts of applications such as operating
sytems, compilers, editors, data base programs, etc. Use of
high level languages has made this much easier.
The microprogram architecture can be thought of as a
Harvard class architecture. This architecture allows instructions
to be fetched at the same time that data is fetched, thus over. lapping instruction fetch and decode along with data operations.
The heart of the bit-slice architecture is found in the sequencer.
The sole purpose of the sequencer is to generate a new
address on every clock cycle. These addresses are fed into a
programmed memory whose result is stored in an instruction
register referred to as the pipeline register. The pipeline register
and memory are very wide - anywhere from 32 bits to as large
as 256 bits. The width of this register is tailored in each design
in order to control a few or many operations in parallel, tuning
the pertormance to the required application. The instruction
register holds the instruction for the sequencer which is
generating the next address. With a 20MHz signal clocking the
sequencer, a new instruction can be fetched 20 million times
per second. This sets an upper end performance level for the
bit-slice architecture at 20 MIPS. This very high rate of
instruction stream can be used to control such applications as
disc controllers, high-speed graphics engines, dedicated DSP
architectures for radar/sonar, imaging devices, communications,
robotics and so on.

COMPARISON OF
MICROPROCESSOR ARCHITECTURES
In order to understand why microprogramming is still a very
important architecture for today's designer, one must compare
the fixed instruction set (8086, 68000) versus bit-slice microprocessor architectures. These two different approaches have
their major strengths in different areas. The fixed instruction
set processors have mainly filled the niche of lower parts count
solutions and general purpose computation. In the controller
area they have serviced the 10w-to-lT!edium performance solutions. On the other hand, the microprogram bit-slice products
have been utiliied in very high-performance control applications and emulation of specialized computer architectures. To
see why this is, one must inspect the architectures (shown in
Figure 2) more closely.
. The fixed instruction set processors, like the 68000, fall into
a class of machines referred to as the Von Neumann-type
architecture which has an address bus and a data bus linking
together the processor and the memory. These two buses are
sometimes referred to as the Von Neumann bottleneck. This is
because all data and program instructions must pass through
the address and data bus between the memory and processor.
This limits the bandwidth because at any give time, only data
or program instructions can be fetched or written. The
performance is therefore directly related to the bandwidth of
this data path. For example, in a 16MHz 68000 for one memory
access, the clock must cycle three times, yielding 5 million
data transfers in one second. To perform any instruction the
processor must fetch' the op code, source and destination
designators, and the data. This can be anywhere from two
memory cycles to many memory cycles and averages out
around 3 to 5 memory cycles. At a bus cycle rate of 5MHz, this

CONTROLLER

I

I

68020 & 80386

+

I

,

I

ADDRESS
DATA
MEMORY
(DTA& PROG)

CONTROLLER

PERFORMANCE

DEDICATED
HARDWARE
SPECIFIC TO
APPLICATION

1.5 MIPS

~

~r--

gr--

I

l

COMPUTATION UNIT

~r--

I

"-

COMPUTATION UNIT

SEQ

•

DEDICATED
HARDWARE
SPECIFIC TO
APPLICATION

ADDRESS
PROGRAM
MEMORY
DATA

,

INSTRUCTION
REG

+

ADDRESS

20 MIPS

~
DATA

DATA MEMORY

Figure 2: Comparison of Microprocessors as Controllers

14-57

CMOS BREATHES NEW LIFE INTO BIT-SLICE

APPLICATION NOTE AN-OS

The other half of the Harvard architecture is the portion which
processes data (shown in Figure 2) as the computation. This
section is typically composed of RAM, arithmetic logic units,
multipliers and data conversion elements (for DSP applications).
This portion of the architecture can have local memory which is
used directly in the computation path, as well as larger more bulky
memory. This architecture may be highly pipelined to get maximum performance or it may be very simple small architectures.
The 2900 family is a group of LSIIVLSI building blocks
which provide such functions as sequencers, address generators and data path elements. Typically, devices like the 2910
are used for the sequencer and devices like the 2903 or 2901
are used for the ALUs and the data paths of microprogrammedtype machines. Because the microprogram devices are thought
of more as building blocks, they therefore have the capability
and flexibility to emulate many different types of structures,
just as the NAND-gate is the ultimate in flexibility. For example,
the 2901 is often used as a sophisticated, dedicated address
generator which can perform PC relative operations, calculate
pointers into complex data structures, etc. Because of the

flexibility and instruction rate, the microprogram architecture is
very suitable for high-performance controllers and the emulation of speoial purpose computer architectures not available as
fixed instruction set machines.

NEW AND MORE POWERFUL
BIT-SLICE DEVICES AS A RESULT OF CMOS
Because CMOS consumes an order of magnitude less power
for the same speed as bipolar, many more gates may be packed
into the same package and still have room to reduce the size of
that package. This allows forever increasing levels of integration.
IDT has designed a new family of bit-slice devices which can
execute the already-existing microcode of the AMD 2900 family,
but at more than four times the integration level. This family is
referred to as the I DT49COOO family, and the heart of it is made up
of ALUs and sequencers. Three key devices in this family are the
IDT49C410, the IDT49C402 and the IDT49C403. These parts
characteristically have wider data paths, more internal paths,
larger RAM and support much higher clock rates than their
bipolar predecessors.
CP

DECREMENT/
HOLD/LOAD

CI

OE

Figure 3: IDT49C410 16-Blt Microprogram Sequencer

The IDT49C410, shown in Figure3, is architecture and function
code compatible to the 2910A, with an extended 16-bit address
path which allows for programs up to 64K words in length. It is a
microprogram address sequencer intended for controlling the
sequence of execution of microinstruction stored in microprogram memory. Besides the capability of sequential access, it
provides conditional branching to any microinstruction within
the 64K microword range. Unlike the 2910 which has a 9 deep
stack, the IDT49C410 has a 33 deep stack which provides
microsubroutine linkage and looping capability. This deep stack
can be used for highy nested microcode applications, as well as

microprogram loop control. At the center of the IDT49C410 is a
multiplexer which selects the address for the next instruction to
be executed. During each microinstruction, the microprogram
controller provides a 16-bit address from one of four sources: 1)
the microprogram address register VolPC) which usually contains
an address one greater than the previous address; 2) an external
direct input used for branching; 3) a register counter (R) which is
used to retain data loaded during a previous microinstruction; or
4) the return stack which is a last-in first-out organization (F).
In a typical application, the worst-case performance path for
the sequencer is from a pipeline register through the condition
14-58

--_......._ - - - - - - - - - - - - -----_....._--_._---_.__..

APPLICATION NOTE AN-D8

CMOS BREATHES NEW LIFE INTO BIT-SLICE

20 MIPS operation is twice as fast as what was realistically
achievable (10 MIPS) using the 2900 family's corresponding
support devices. This will allow designers to achieve performance
levels never dreamed of before. Because of the enhanced
CEMOSTM technology used to fabricate this device, the I DT49C41 0
draws no more than 80 milliamps commerical in the worst-case
system configuration which is approximately 1/5 the power of its
12-bit predecessor, the 2910A, which is 344 milliamps.

code mux and on into the instruction decoder of the sequencer
which selects the next address. The address then passes through
into the microprogram memory which must set up the next
instruction into the pipeline register. Using the highest performance devices, this consists of a 6.5ns clocked Q pipeline register
(I DT74FCT374A) , 12ns condition code MUX (IDT74FCT153),
13ns through the sequencer (IDT49C410A), 15ns access time for
16Kx1 static RAM (IDT6168A) and 3ns set up to the pipeline
register (IDT74FCT374A), thus yielding a 49.5ns cycle time. The

DATA
IN

READ
ADDR
CP

READ/
WRITE
ADDR
12- 0
15- 3
18- 6
19
MSS
G/F1S
P/OVR

Cn +16

F=O

DATA OUT
Figure 4: IDT49C402 - 16-Bit CMOS Microprocessor Slice
(Quad 2901 Plus Extra Destination Functions)

The IDT49C402, shown in Figure 4, is a very high-speed, fully
cascadeable, 16-bit CMOS microprocessor slice unit which
combines the standard functions of four 2901s and a 2902 with
additional control features aimed at enhancing the performance
of bit-slice microprocessor designs.
The IDT49C402 includes all the normal functions associated
with the standard 2901 bit-slice operation: 1) a 3-bit instruction
field composed of 10 ,11,1 2 which controls the source operand
selection of the ALU: 2) a 3-bit microinstruction field composed of
13.14.15 used to control the 8 possible functions of the ALU; 3) 8
destination control function lines which are selected by the
microcode inputs 16h,ls;and 4) a tenth microinstruction input, 19,
offering 8 additional destination control functions. This 19 input,
which is above and beyond the standard 2901 instruction lines, is
used in conjunction with 16,17,ls and allows for shifting the Q
register up and down, loading the RAM or Q registers directly
from the D inputs without going through the ALU, and new
combinations of destination functions with RAM A-port output

14-59

available at the Y output pins of the device. The new ability to load
the RAM or the Q register directly forthe D inputs without having
to pass through the ALU means that new operands may be
brought into the register file in parallel with ALU operations in
critical sections of algorithms. Where thearchitecture used to take
two cycles to load and operate, it now can be done in one cycle,
providing twice the performance in critical portions of the code.
Also featured in the IDT49C402 is an on-chip dual-port RAM
that contains 64 words by 16 bits. This isfourtimes the numberof
working registers in the 2901. Because the on-board register file
in the 2901 architecture is not readily cascadeable, the large
memory is a significant advantage to the designer. The register
file can be thought of as a high-speed cache on-board the device.
The more room that is available to the programmer, the higher
the hit ratio is for desired data.
The 64 on-board registers in the IDT49C402 can be alternately
used in a bank selected architecture to yield four sets of 16
working registers. Each bank can then be set aside for one of four

eJ
~

APPLICATION NOTE AN-08

CMOS BREATHES NEW LIFE INTO BIT-SLICE

microprogram tasks, thus making it easy to write multi-tasking
microcode where anyone of four tasks can be executed in each
clock cycle. This means that the time to switch between tasks is
one clock cycle for the ALU section of the circuitry. This can be
very important in highly interrupt-driven controller-type architectures. For fixed instruction set processors (like the 68020 or
80386), a context switch requires the execution of multiple
instructions.
The critical path through the I DT49C402 on most applications is
the A and B addresses and instruction to the data output. This
path in the IDT49C402A is 37ns commerical. In a typical
application this means that, if the addresses come from the
pipeline register which has a clocked Q of 10ns and the data

output of the I DT49C402A goes into another register with a set-up
of 3ns, the full cycle time of that portion of the circuitry is 50ns,
thus yielding an operation of20 MIPS. Thiscan be compared with
four 2901 Cs (bipolar competitor) which require a system cycle
time of 80ns, resulting in a maximum rate of 12 MIPS.
While the 2901l49C402 architecture can be thought of as a
2-bus architecture with 1 bus into the ALU and 1 bus out of the
ALU, the 2903/203/49C403 is thought of as a 3-bus architecture.
The IDT49C403 is a high-speed, fully cascadeable, 16-bit CMOS
microprocessor slice unit which combines the standard functions of four 2903s and a 2902 - with additional control features
aimed at enhancing the performance of classic bit-slice microprocessor designs.

ADD~ESS 1'----;"7'/""6--0 8 5_0

A
ADDRESS

A 5-0 D>--~~\""'---I

64 x 16
RAM

WE
lEN
CP

OEA

D>------'

DA5-0

Cn + 1 O f - - - - - I

-Dcn

Gf-----I
PIOVR G f - - - - - I
GIN

-oSIOO

SI0 15

DI------I

QI0 15

Df-----I

-oQIOO

-Dz

19-0

DATA OUT
LSS
MSS

INSTRUCTION
DECODE

WRIT

WIB
Figure 5: IDT49C403 16-Blt CMOS Microprocessor Slice
(Quad 2903/203 Plus Expanded RAM)

14-60

APPLICATION NOTE AN-08

CMOS BREATHES NEW LIFE INTO BIT-SLICE

Included in the extremely low-powered yet fast IOT49C403
device (shown in Figure 5) are three bi-directional data buses, 64
word x 16-bit dual-port expandable RAM, 4 word x 16-bit Q
register, parity generation,sign extension, multiplication, division
and normalization logic. Additionally, the IOT49C403 offers the
special feature of enhanced byte support through both word/byte
control and byte swap control. The IOT49C403A will support
cycle times as fast as 65ns and will enhance the speed of all
existing quad 2903A and 29203 systems by 40%. Being specified
at an extremely low 185 milliamp maximum commercial power
consumption, the lOT device offers an immediate system power
savings and improved reliability over the existing designs. This
device is packaged in either 108-pin PGA or a 144-pin leaded chip
carrier.
The functional block diagram of the I OT49C403 shows that not
only has the data path been widened to 16 bits, but the RAM and
the Q registers are four times as deep. Thus, the IOT49C403 has
been expanded in depth as well as in width, giving a two-fold
improvement in performance. Not only can the expanded RAM
and Q registers be used to provide more room for caching
intermediate operands, they can also be thought of in bankselected architectures as providing room for a least four tasks in a
multi-task environment. Therefore, in a highly interrupt-driven
application, the overhead to switch between one task and the
next is zero.
Because the width of the IOT49C403 is 16 bits, a control line
called W/S is provided to switch the IOT49C403 between working
on 8 bits or 16 bits. When in the byte mode, the RAM location
being written into has only the lower 8 bits enabled, leaving the
upper 8 bits intact. All of the status flags coming out of the
IOT49C403 come from the intermediate boundary between the
8th and the 9th bit of the ALU, all of which makes it convenient for
the designerto operate on 8 bits at a time. The word/byte control,
taken in conjunction with the instruction enable, allows the
designer to cascade the IOT49C403 into larger words such as 32
bits or 64 bits by controlling each of the instruction enables and
the word/byte line on the least significant device operand links of
8, 16, 32, and 64 bits. The additional instruction added to the
instruction set with an IOT49C403 can be used to swap upper
and lower bytes inside each IOT49C403 device.

CONSERVATION OF MICROCODE
lOT provides a solution that minimizes the total redesign cost
of transition from bipolar technologies to CMOS technologies.
This is achievedby having a series of parts designed in CMOS
taking advantage of the VLSI capabilities yet utilizing the same
instruction set as devices in the 2900 family. Each of the three
devices mentioned above is capable of executing microcode
previously written for their bipolar counterparts.
In the case of the IOT49C410 sequencer, the old microcode
may be run with no alterations. For the two ALUs, the I DT49C402
and IOT49C403, compatibility can be handled at several levels.
The simplest solution is to connect only the instruction lines
which correspond to the 2901 or the 2903/203, respectively, and

tie the remaining inputs to their respective default levels. In this
way, the design can execute the previously assembled
microcodes.
Ifthe design requires the designer to take advantage of some of
the new features in the ALU such as deeper register files or new
data paths, microcode must be modified to control the additional
instruction lines. This can be achieved by modifying the
assembler and reassembling the old microcode.
Because each microprogram design is different, the microprogram control word is different. This requires that microprogram assemblers have the ability to define mnemonics and
relationships to define microprogram instructions and then
assemble the user's microprogram written in the design's unique
instructions. When upgrading from four 2901 s to one lOT49C402,
for example, the designer can add new mnemonics for the new
operations to the definition phase of the microprogram assembler.
At this point, consideration for .the additional instruction input
lines are made by simply widening the subfields. After the
definitions have been modified, the older microcode can be
reassembled along with new code using the new operations.

GRAPHICS ACCELERATOR EXAMPLE
Today's high-end work stations use a processor like the 68020
or 8386 as the main CPU. Often augmenting the processing
capability of the main CPU is a floating point math accelerator.
While in some cases the floating point units are connected to the
main CPU as a co-processor, in other cases the floating point isa
separate processor itself. If the floating point processor is
isolated from the main CPU through the use of a dual-port,
higher overall system performance can be achieved because the
accelerator can process in parallel to the main CPU.
In a graphics-type application, it is conceivable that the dualport could contain a link list of data elements containing three
dimensional point values and transformation instructions which
are composed of 4 x 4 matrix. The floating point processor then
could have the capability of traversing the link list and multiplying
each point with the transformation matrice. This scenario could
be used not only to rotate three dimensional objects, but also
transformation of three dimensional objects onto two dimensional surfaces and performing clipping algorithms for final display on the video graphics terminal. Figure 6 shows how a cube
might appear to a viewer of the work station and how it might be
represented internally in memory.
The floating point accelerator can be broken into three main
functional blocks: dual-port RAM, controller and floating point
ALU, and multiplier. A block of dual-port RAMs is used as the
interface between the global system bus and a local system bus
used by the floating point processor. The control section
generates sequences of instructions for a floating point ALU as
well as the address generator indexing into the dual-port. The
performance of the floating point accelerator is determined by
how fast the controller can generate instructions for the ALU and
the data band width of the ALU.

14-61

III
~

APPLICATION NOTE AN-08

CMOS BREATHES NEW LIFE INTO BIT-SLICE

F
A

G

a11
a21
a31
a41

C

a12
a22
a32
a42

a13
a23
a33
a43

a14
a24
a34
a44

The User's View
Dual-Port RAM

The Processor's View
Figure 6

There are various floating point ALU devices on the market
today. These devices can be grouped by the number of data
buses used to get data in and out of them and the number of
operations that can be performed at any given time (pipelining
stages). The 1164/65 from Weitek each have one data bus in and
out. These devices are meant to be connected to a common data
bus which eventually is tied to the data bus of a fixed instruction
set processor.
The 1264/65 floating point devices from Weitek and the
IDT721264/1265 pin compatible CMOS versions have two data
buses in and one data bus out, thus supporting the three bustype architecture. Unlike the 1164/65, these devices can be
operating on various pieces of data in several stages of completion
through the use of pipeline registers, thus having a higher
throughput. Both the IDT721264 and IDT721265 have a clock
rate of 20M Hz. The three data buses and pipelining makes the
1264/65 a very good match for high-performance bit-slice
solutions.
The following is a discussion and comparison between two
different types of solutions: the first being a fixed instruction set
processor controlling the 1164/65 and the second solution being
a 1264/65 controlled by bit-slice. The detailed description of the
1164/65 and 1264/65 are beyond the scope of this article, but
Figures 8 and 10 show timing sequences of parameters, instructions and results.

In keeping with the possible structure for the floating point
accelerator previously discussed, the 80386 serves the purpose
of controlling the overall operation of the accelerator, shown in
Figure 7. It serves the purpose of fetching data from the dual-port
RAM. Through address decode circuitry and bus transceivers,
the 386 sends commands as well as data to the ALU. The
instructions are encoded as addresses in the 386's memory map
where each address corresponds to a unique instruction for the
1164/65. While the address map is a clever concept, and probably
the most efficient implementation, the decode and bus transceiver
circuitry numbers more than a dozen parts.
To understand the performance, bus cycles must be counted
and multiplied times the clock frequency. To perform one floating
point operation, data must be fetched from the dual-port into the
80386 registers and then written out to the floating point chip. At
this point, the floating point chips must be clocked multiple times
to accomplish the desired operation. Finally, the 80386 must read
the results into its register file where it might be saved as a
temporary value or moved back to the dual-port.
The memory-to-register move instruction of the 386 requires
four clock cycles. The register-to-memory move instruction
requires two clock cycles. Therefore, to read data from the dualport RAM into the floating point ALU requires six clock cycles.
Instructions are passed from the 386 to the 1164/65 via the
address bus. Each time the memory map is written to or read
from, a clock is generated to the 1164/65. After placing the two
operands in the floating point ALU, they must be clocked five
times (shown in Figure 8), thus using ten clock cycles. Finally, to
get data out of the floating point ALU, a memory-to-register
move must be performed using four clock cycles. Therefore, to
perform a floating point single precision floating point operation,
38 clock cycles must be utilized. In order to perform a three
dimensional transformation requiring that a vector be multiplied
by a matrix of 4 x 4 elements, 1,064 clock cycles must be utilized.
At a clock rate of 16M Hz, this means that a transformation can be
done every 66 microseconds. This does not include the instructions to manage the linked lists and housekeeping.

FIXED INSTRUCTION PROCESSOR
As with any design problem, there are various solutions which
present trade-offs in parts count and performance. The fixed
instruction set processors provide solutions that are typically the
lowest parts count but, when applied to dedicated control
applications, do not provide the highest performance. The Intel
80386 i!> an example of a fixed instruction set processor that is
popular as a general purpose CPU. Figure 7 shows a block
diagram of how it would be used to control the 1164/65. While one
approach could use a co-processor, the Weitek 1164/65 provides
a higher performance solution.

~4-62

CMOS BREATHES NEW LIFE INTO BIT-SLICE

APPLICATION NOTE AN-08

LOCAL
SYSTEM
BUS

CONTROL

FLOATING POINT ALU

ADS
CS WTL 1164
RESET
ADDRESS/
W/R
INSTRUCTION
MULTIPLIER
READY
DECODE
t-L--,......... CONTROL
CS
CLK2
INSTRUCTION
CONTROL CLK1

CONTROL
ADDRESS
DATA

80386

PROGRAM/
DATA RAM
8 x IDT7198

CONTROL
ADDRESS
DATA

CLK
82384
CLK

GLOBAL SYSTEM BUS

Figure 7: Floating Point Accelerator Using Fixed Instruction Set Processor

CLK+

x+
L+, CSLF+
U+, CSUS+

Figure 8: Single Precision Multiply for WTL 1164

14-63

WTL 1165

ALU

CMOS BREATHES NEW LIFE INTO BIT-SLICE

APPLICATION NOTE AN-08

acteristic of microprogram solutions is that multiple devices can
be controlled in parallel. The third advantage of microprogram
solutions is that multiple buses can be utilized and controlled in
parallel, thereby allowing the designer to tailor the performance
of the design to match the requirements of the application.
The MICROSLlCE'M family is very well suited for controlling
such devices as the floating point ALU or multiplier, like the
IDT721264/1265, both of which are pin and functionally compatible with the 1264 and 1265. The control section of the floating
point accelerator (shown in Figure 9) can be composed of the
I DT49C41 0 which generates addresses to the writeable control
store of the IDT71681. This, in turn, produces an instruction
which is held in a pipeline register. The pipeline register is the
current instruction being executed. From this register, control
lines fan out to all instruction lines and control inputs of every
device in the accelerator subsystem.

The need was recognized for a higher performance solution
utilizing a processor like a 386. A product from Weitek, the 1163,
replaces the address and instruction decode in the block
diagram. The 1163 is a small sequencer and RAM which takes
instructions from the 386's address bus and translates them into a
series of instructions to the 1165 and 1165, thus reducing a
floating point operation to 13 cycles. This results in a floating
point transformation being done in 256 cycles which, with 16MHz
clock, yields a transformation every 15.5 microseconds - a 5 fold
improvement.
MICROSLIC~M

SOLUTION

While a six fold increase in performance can be achieved using
a special purpose sequencer like the 1163, by using general
purpose sequencers (like the IDT49C410), another order of
magnitude in improvement can be achieved. This improvement
in performance is the direct result of three major characteristics
of microprogram solutions. The first characteristic is that on
every clock cycle a new instruction is fetched and executed,
producing a sequence of very rapid fire instructions. The width of
these instructions is chosen at design time to maximize the
controllability of multiple devices. Therefore, the second char-

IDT49C402 AS AN ADDRESS GENERATOR
While most designers would think of the IDT49C402 and its
class of devices only as ALUs with register files for data paths, it
can be used for a larger variety of tasks. In the accelerator
applications, it is used as an address generator. The data for a

CONTROL

FLOATING POINT ALU

+

IR
IDT39C825

I

0
IDT49C410
Y

r-

,

+
WCS
A

24 x I~T71681

......

I

PIPELINE REG;
12 x IDT39C825

B

A

I

~
+

LA

RA

~t

~

+

CONTROL
IDT7132/42
DUAL-PORT
RAM
CONTROL

t
I
I

!

I

CD

0
en
M

--'<3'

~7

LD

RD

GLOBAL SYSTEM BUS

~

Figure 9: Floating Point Accelerator Using MICROSLICE™ Approach

14-64

DB

Y

e><

*

DA

C
N

I-

I

~

2 x IDT49C403

-;;;

I

B

IDT721265

C

~

0
IDT49C402
Y

A

IDT721264

~LI.d

I

I

~~

J

-

APPLICATION NOTE AN-OS

CMOS BREATHES NEW LIFE INTO BIT-SLICE

4 x 4 matrice can be stored in the dual-port memory as a
sequential list of 16 values. Any element can be located byadding
together the address pointer to the start of the matrix, the row
offset and the column offset. To perform a matrix multiplicaton
with a vector, a column of values out of the matrix is individually
multipled with the corresponding values in the vector and then
the four products are summed. One way of efficiently generating
the addresses using the IDT49C402, is to have the address
pointer to the matrix and vector stored in the register file. To start,
the address pointer of the matrix could be summed with a
constant corresponding to the column to be operated on. This
operation can be accomplished in one cycle by bringing the
constant in through the "D" bus from the pipeline register,
addressing the pointer with the A address and storing the result
at a location specified by the B address. In the same cycle the
new address could be output from the ALU through the Y port
and placed in the MAR register. In this way, the MAR register
would supply the dual-port RAM address on the next cycle,thus
forming a pipeline mode of operation. On the next three cycles,
the new address stored in the register file could be incremented
and the respective calculated addresses passed on to the MAR.
Therefore, in four cycles four addresses can be generated in
rapid fire that correspond to four values in the column of the
matrix. All of this function can be independent of, and working in
parallel with, what is happening in the computation unit. With
proper orchestration, address can be fed into the dual-port RAM
and values read out in succession into the computation unit on
every cycle. The minimum time from register file address tothe Y
output is 37ns, which is one of the fastest ways to generate
complex 16-bit address.
Just as the IDT49C402 can be used to compute offsets into
matrices, it can also be used to keep track of linked lists of
complex data structures. The register file could be used to retain
pointers of various lists, as well as intermediate pointers. In the
accelerator described earlier, there are several required pointers:
one pointer to the head of a list of XYZW points, an intermediate
pointer to the current XYZW and a pointer to the transformation
matrix.

The multiply of a column with a vector is a sum of four
products. The multiply of an XYZW vector with a 4 x 4 matrix is,
therefore, 4 sums of products. Because it takes 8 clock cycles to
perform the multiply and 12 clock cycles (shown in Figure 10) for
the add operation (IDT721264), it is impractical to contemplate
doing one sum of product in sequential cycles if the goal is to
feed the multiplier and ALU on every cycle. To this end, the
algorithm (pictured in Figure 11) works on all four sums of
products in parallel.
To implement the parallel scheme the X,Y,Z and W must be
multiplied in succession with each row of values in the matrix.
When the four products of X with the first row of the matrix come
out of the multiplier (a11, a12, a13, a14), they must be temporarily
stored in the IDT49C403s until the four products of Y with the
second row (a21, a22, a23, a24) start to come out. When the result
of the first product of Y comes out (y. a21), it can be immediately
fed into the floating pointALU (IDT721265) with the first product
of X (X, a11) which is stored in the register file ofthe IDT49C403s.
As the results of the sum of X and Y vectors come out, they must
be stored until the corresponding sums come out of the Z and W
vectors. When the corresponding sums are available, the final
sum of all four vectors may be computed.
Figure 12 shows how the parallel algorithm can be implemented while taking into account pipelining of the floating point
devices. The block is a graph which represents time as clock
cycles on the horizontal axis and pipeline stages on the vertical
axis. The input values start atthetop and flow down to the bottom
of the chart. Intermediate val ues out of the multiplier and the ALU
are stored in the IDT49C403 and are reinserted into the floating
point ALU in the middle of overall pipeline.
Since this is a pipelined parallel architecture, a new matrix
multiply can be started every 32 clock cycles. This results in a
matrix multiply every 2 microseconds, given a 16MHz system
clock which is more than a 33 fold increase in performance over
the 386 solution. One of the tradeoffs is that there is a 40 clock
cycle latency to complete the matrix multiply after the last values
are put into the top of the pipeline. This is not a technical problem
because the dual-port memory can contain a complete list of
XYZW vectors and be processing them in sequence.

HIGH-PERFORMANCE COMPUTATION
The computation portion of the accelerator is composed of the
floating point devices and some local storage. The most efficient
approach for multiplying a series of vectors with a transformation
matrix is to start out by fetching the matrix from the dual-port
RAM into local memory connected to the floating point chips. For
this purpose, two IDT49C403s are incorporated as a 32-bit
register file and ALU. Since the IDT49C403 has 64 registers, there
is plenty of room to store the 4 x 4 matrix and still be able to
accommodate temporary variables. The 32-bit ALU portion of
the IDT49C403s can then be conveniently used to perform fixed
point arithmetic and logic functions.
The IDT49C403 is a three bus architecture which allows for
both of the output ports of register file to come off-chip and drive
inputs into the floating point devices. In this way, two operands
can come from the IDT49C403s and one from the dual-port
addressed by the IDT49C402 each clock cycle. The results of the
floating point multiplier or ALU can be stored back into the
register file using the Y bus.
Once the transformation matrix is stored in the IDT49C403
registers, consecutive XYZW point values can be brought from
the dual-port. In this way, a value from the XYZW vector and
transformation matrix can be fed to the multiplier (IDT721265) on
every cycle, thus keeping the multiplier constantly busy.

FIXED INSTRUCTION SET VERSUS MICROSLICE
As can be seen, different solutions to the same application can
result in a broad range of performances of much more than an
order of magnitude, 1 to 33. The larger increase in performance
must be viewed from the perspective of the tradeoff in hardware.
On the level of VLSI devices, the control section of the 80386
solution uses one device, whereas the MICROSLICE solution
uses two devices: the IDT49C410 for overall control and the
IDT49C402 for operand address generation. The computation
section maintains the one-to-two ratio with two devices for the
80386 solution (the 1164 and 1165) as opposed to the bit-slice ~
solution which uses four devices (the I DT721264, I DT721265 and . . . ..~.,.<.;.','~•. '
two IDT49C403s). In 1985, the disparity in the parts count of " ",,:,
these areas would have been much greater because only 4-bit
ALU slices were available, making the count for the control
section 5 devices and the computation 6 devices.
The two areas where these solutions differ the most is in the
control word formation forthe floating point chip and the number
of buses. For the 80386 solution, control signals are derived from
the execution of a program stored in a 32-bit cycle wide memory
which generates a succession of addresses which in turn are
decoded into control words for the 1164/65. The decode logic is

14-65

APPLICATION NOTE AN-OS

CMOS BREATHES NEW LIFE INTO BIT-SLICE

XIV OPR
L+, CSLF+
U+,CSU-r----r----r_--~----r_--~~

S+~--~----+_--_+----+_--_+----+_--_+~

ZRESULT~--~----~--~----~--~----~--~~

Plpellned Single Precision Multiply for IDT721264

XIV OPR
L+, CSLF+

S+r---~----r_--~----r_--~----+_--~----+_--~----+_--~_<

ZRESULT~--~----~--~----~--~----~--~----~--~----r---~-<

FIGURE 10: Plpellned Single Precision Add for IDT721265

~'

a21

a12 a13

.~

X' = X • a11 + V • a21 + Z • a31 + W • a41

a22 a23 a24

x

a31 a32 a33 a34

a41

y' = X • a12 + V • a22 + Z • a32 + W • a42

~YZwJ

Z· = X • a13 + V • a23 + Z • a33 + W • a43
W· = X· a14 + y. a24 + Z· a34 + W· a44

a42 a43 a44

X a11 X a12 X a13 X a14 V a21 V a22 V a23 V a24 Z a31 Z a32 Z a33 Z a34 W a41 W a42 W a43 Wa44

\/ \/ \/ \/
x

)(

)(

\/ \/ \/ \/ \/ \/ \/ \/

x

x

x

x

x

)(

)(

\/ \/ \/ \/
)(

)(

x

~~/~~/
+

+

+

+

+

+

+

+

~~-:::;:,~---~
+

+

+

j

X'

y'

z·

W'

I

Figure 11: Mathematics of Matrix Multiply with Rearranged Order of Scalar Multiplies and Summations

14-66

)(

CMOS BREATHES NEW LIFE INTO BIT-SLICE

APPLICATION NOTE AN-08

--l""

1--_ _ _ _ _
IN_P_U_T_R_1l.R_A_M_E_T_E_R_S_FO_R_C_U_RR_E_N_T_(..:...N_)M_A_:r_R_IC_E_M_U_l:_:r_IP_LY
____

!NPUT PARAMETERS FOR NEXT (N+l) MATRICE MULTIPLY,

SYSTEM
CLOCK

RESULTS OF ~INTERMEDIATE-FNUSUED MULT~PLlERINTERMEDIAT~
RESULTS
~NTERMEDIATH
PREVIOUS (N-2)
RESULTS (N-l)
CYCLES
RESULTS (N)
PREVIOUS (N-l)
RESULTS (N)
MATRIX MULTIPLY
TO BE USED IN
TO BE USED IN
MATRIX MULTIPLY
TO BE USED IN
6 CYCLES
22 CYCLES
6 CYCLES

h

Figure 12: Pipeline of Matrix Multiply Using IDT721264/1DT721265

approximately a dozen devices which includes address buffers,
address decode, transfer acknowledge, etc. The microprogram
solution generates the control signals directly from a program
memory of 16 bits wide which is stored in an instruction register
called the pipeline register (12 IDT39C825A octal registers).
The area which has the largest variation in parts count is the
bus structure. The 80386 has one address bus which it uses for
control and one data bus which ties together the 80386, program
RAM, dual-port RAM and the computation unit. There is one set
of four bus transceivers required to isolate the floating point
chips from the local data bus.
In contrast, the microprogram solution has numerous short
buses which require interconnecting. One data bus comes from
the dual-port RAM which ties together the control section as well
as providing parameters to the computation section. The computation section, however, has four short buses which require
four sets of four bus buffers (16 octal buffers) plus four octal
registers for storing an intermediate value. The table in Figure 13
shows a summary of the performance and parts count of the two
solutions. The total at the bottom is a sum of the sections
compared. While it is not a total parts count, the ratio will be
representative of the relation between the two solutions.

it utilizes single 32 address and data buses with one 32-bit wide
memory, but has the disadvantage of requiring many clock
cycles to perform a control operation. The advantage of the
MICROSLICE solution is that it can control multiple devices in
parallel at the cost of wider control memory and multiple bus
interface parts. The speed/power product provided by very highspeed CMOS today offers the designer bit-slice tools fordesigning
control structures and computation units which are on a comparable level of integration with fixed instruction set processors,
but can offer significantly more than an order of magnitude in
performance.

I-

14-67

15K

MICROSLICE

SOaK

VLSI

3

6

In Control

-12

12

8 (32-Bits)

24 (96)

Z

Memory
(Width)

en

In Bus
Interfact

4

20

Total
Compared
Sections

27

62

~

0

I-

<
Q,

It can be concluded on a comparison basis that the
MICROSLICE solution provides 33 times the performance of a
fixed instruction set procressor like the 80386 for about 2 to 3
times the parts count. The advantage of the 80386 solution is that

80386

0

a:

CONCLUSION

Solution
Number of
Floating Point
Matrix Multiplies
Per Second

Figure 13: Comparison of Different Solutions

Q1I,

lUi!]

By DAVID C. WYLAND

ABSTRACT

control memory. The data flow section has a register and ALU element-the bit-slice-plus a data memory and I/O registers on a
data bus. Note that the control and data memories are separate.
The use of separate data and instruction memories is called the
Harvard architecture. The separate control memory provides some
of the speed associated with bit-slice designs because it operates
In parallel with the data memory. This allows the next microinstruction to be fetched from the control memory, while data for the current Instruction may be read from the data memory. This contrasts
with conventional microprocessors which alternately get instructions and data from the same memory. This use of a single memory
for instructions and data is called the Von Neumann architecture.
There Is a remarkable Similarity between the block diagram in
Figure 1 and the block diagrams of RISC computers, as can be
noted by comparing the block diagram In Figure 1 with the block
diagram of a RISC CPU shown In Figure 2. The difference Is that the
control memory and the data memory of the controller have been
replaced by an instruction cache memory and a data cache memory in the RISC CPU. The instruction and data cache memories
work the same as their microcode counterparts except that they
both contain copies of data In the common main memory. The programmer sees a single memory-the main memory-while the
hardware works as if It has two Independent memories. In this manner, the RISC computer has the speed advantage of the Harvard
architecture and the single memory for programs and data of the
Von Neumann architecture.

High-performance controller designs use bit-slice components
for their speed and design flexibility. Speeds of 10-20 million Instructions per second (MIPS) are common and the designer can
use bit-slice design flexibility to perform speed-critical operations
in one Instruction. Bit-slice designs have the drawback, however, of
requiring microcode design for their implementation, often with a
long development cycle. The problem Is that the microcode resides in a separate, stand-alone control memory which prevents
use of the kind of Interactive prototyplng and debugging tools associated with conventional microprocessors. The problem can be
eliminated by using a dual-port RAM for the control memory, making It part of the data memory address space, and converting the
controller to a CPU by borrowing some techniques from Reduced
Instruction Set Computer (RISC) designs. The result is a RISC controller where the microinstructions of the bit-slice approach
become the instructions of a computer. The design approach provides all the speed and architectural flexibility of microcoded bitslice designs, while allowing the use of Interactive debugging
methods associated with mlcroprocssors.

BIT·SLlCE VERSUS RISC ARCHITECTURES
An example of a typical bit-slice controller design is shown In
Figure 1.lt consistS of a control flow section and a data flow section.
The control flow section has a microinstruction counter and the

DATA FLOW SECTION

r---------------,
CONTROL FLOW SECTION

~

_______________ J

. Figure 1. BH-Sllce Controller Block Diagram

© 11117 Integrated DevIce TechnoIogy,lnc.

14-68

Prtnted In the U.S.A.

5/17

DUAL-PORT RAMs YIELD BIT-SLICE DESIGNS WITHOUT MICROCODE

APPLICATION NOTE AN-09

MAIN MEMORY
DATA FLOW SECTION

CONTROL FLOW SECTION

r--------------,I
I
I
I

I
I

IL

_______________

J

Figure 2. RISC CPU Block Diagram

The instruction and data caches of the RISC architecture are
equivalent to having two ports on one memory. We can apply this
concept to bit-slice controllers by using a high-speed dual-port
memory in place of the cache memories, as shown in Figure 3. The
dual-port RAM allows the instruction and data ports to be active simultaneouslyand independently, while providing both sides access to a common set of RAM cells. Since both ports are working
from the same memory, the data flow section can load and move
both data and instructions in the same manner as a conventional
microprocessor. As a result, this design functions as a conventional
CPU with a long instruction word. This allows conventional interactive software tools, such as interpreters and monitors, to be used in
system development and debugging.

DESIGN OF A RiSe CONTROLLER
The design of a RISC controller using a dual-port control memory is similar to a conventional bit-slice design except for inclusion
of a minimum set of operations for a CPU. This allows use as a conventional computer for software coding and debugging. In ordinary
bit-slice controller designs, the minimal CPU operation set already
exists as a subset of the data flow and control operations already
present.
A minimal set of CPU operations, suitable for bit-slice designs,
can be derived from the instruction set of a RISC-like computer
such as the Data General Nova minicomputer. It is a useful example
because it is a 16-bit general register design having approximately
20 instructions and three addressing modes, yet is fully functional
as a computer. From its instruction set, the list of 21 operations
shown in Table 1 can be derived as a representative minimum

working set. If the design includes these operations, it will function
asa CPU.
Table 1. Minimal CPU Instruction Set
1. Load register from memory at immediate address
(address in instruction).
2. Load register from memory at address in a register.
3. Store register to memory at immediate address (address
in instruction).
4. Store register to memory at address in a register.
5-11. Move/combine registers: move, negate, invert, add,
subtract, AND, OR.
12-13. Shift: rotate left through sign, rotate right through sign.
14. Read status register.
15. Write status register.
16. Jump absolute: load program counter with immediate
address.
17. Jump register: load program counter with register
contents.
18-20. Jump absolute conditional: if zero result, if sign, if carry.
21. Jump and save retum (Program Counter) in a register.
This instruction set assumes a set of general purpose registers
(typically 16 or more in bit-slice designs), a memory which contains
both instructions and data and a status register which records the
result of register-ta-register operations. I/O registers are assumed
to be mapped into the memory space so that separate instructions
for them are not required.

14-69

HI
~

DUAL·PORT RAMs YIELD BIT·SLlCE DESIGNS WITHOUT MICROCODE

APPLICATION NOTE AN·09
DATA FLOW SECTION

r---------------,
I
I
CONTROL FLOW SECTION

r------------,

I
I
I
I
I

I
I
I

I
I
I

I
I

1.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Figure 3. Blt·Sllce Controller With Dual-Port Control Store

Some of the above operations are automatically included in bit·
slice controllers as a result of staightforward design. The register
combination operations are provided by the bit·slice RALUs and
the jump operations are commonly required as part of the control
flow design. All that is required to complete the set is the ability to
transfer registers to and from memory, to save and restore the
status register and to save the Program Counter in a register in
Jump and Save Return instructions.
Figure 4 shows a block diagram of a general purpose bit·slice
controller design, based on the RISC controller architecture in Fig·
ure 3, and capable of implementing the minimal instruction set.
This is a 16·bit controller design using an IDT49C402 16·bit RALU
and a 64-bit instruction word. The control flow section is fully
pipelined for maximum speed and uses a simple counter as the
Program Counter (PC). As a result, branch execution is delayed by
one instruction: the instruction following the branch is executed before the branch takes effect. This method allows maximum speed
in the control flow section and is commonly used in RISC designs.
A path is provided from the PCtothe data inputs of the IDT49C402
for saving the PC in a register during Jump and Save Return operations. Also shown in the block diagram is an initial-load EPROM.
This EPROM holds the non-volatile copy of the program to be
loaded at power up. A power up flip-flop and some sequencing
logic cause the contents of this EPROM to be loaded into the RAM
at power up.

Figure 4. Dual·Port Bit·Sllce RISC Controller Design
Block Diagram

14-70

DUAL·PORT RAMs YIELD BIT·SLlCE DESIGNS WITHOUT MICROCODE

In the design in Figure 4, the instructions and data share the
same memory. The mapping for instructions and the mapping for
, data are different, however, as is shown in Figure 5. The eight dualport RAM chips are mapped as 2K words of 64 bits/word on the
instruction port and as 8K words of 16 bits/word on the data port.
Each 64·bit instruction word corresponds to four sequential 16-bit
data words. The instruction at address 0000 on the instruction port
corresponds to locations 0000, 0001, 0002 and 0003 on the data
port. On the instruction port, all eight chips are enabled, resulting in
64 bits of instruction output. Only the upper 14 bits of the PC are
used to address the RAM so that the address in the PC is consistent
with the addressing on the data side. On the data port, the least significant two bits of the address in MAR select the appropriate 16-bit
word by selecting the chip enable for the appropriate one of four
pairs of chips.

APPLICATION NOTE AN·09

ing this data into the memory and/or MAR from the bus. The bus
read bit disables the IDT49C402 outputs and gates an I/O register
onto the bus as determined by the 6-bit A field. The bus write bit
causes bus data to be written into an I/O register selected by the B
field.
Branch operations are controlled by the Jump and A fields. The
Jump field enables loading of the PC from the bus, which is the
branch operation. The A field provides the 6-bit condition select
code for conditional branch operations.
The Misc Control field provides 14 bits for direct control of additional devices. This field would typically be used for gates and
strobes to additional devices such as parallel multipliers, FIFOs,
disk controller chips and other devices which communicate with,
and are controlled by, the RISC controller.

IMPLEMENTING THE MINIMAL INSTRUCTION SET

RISC CONTROLLER INSTRUCTION FORMAT
The 64-bit instruction word is shown in Figure 6. Fifty of the
64 bits are used to control the basic data and control flow of the
controller and 14 bits are available as additional control bits for the
specific controller application. Each 64-bit instruction word from
the control port of the RAM is mapped as four 16·bit words on the
data memory port. A larger instruction word can be used in the
same manner as in microcoded designs. It is convenient if the word
width is a power of two, such as 64 or 128 bits, so that there are no
gaps in the memory space as seen from the data flow side.
The IDT49C402 is controlled by the A and B fields, 10-9, CN ,Stat
Enable field and the Shift Gating field. The A and B fields provide
the 6-bit addresses for the A and B register inputs on the
IDT49C402. The 10-9, CN and Stat EN field provide the 10 control
bits to the IDT49C402, the carry-in bit and a status register load enable, respectively, and the Shift Gating field controls the shift-in/
shift·out gating for shift operations. The data source forthe DIN pins
of the IDT49C402 is selected by the DIN field. This field can choose
the data bus, the immediate data field or the PC as the data source.
The data bus is controlled by the A and B fields as well, which
provide 6-bit select codes for bus read and write operations, respectively, and by the bus read/write, memory write and load MAR
bits. The default operation is to gate the data from the IDT49C402
onto the data bus. The load MAR and memory write bits allow writ-

14-71

The RISC controller design must now be checked to ensure that
it implements each instruction in the minimal instruction set.

Load and Store
Load and Store register operations are done in two instructions:
load MAR and load or store register. The load MAR instruction
places register data from the IDT49C402 or data from the immediate data field on the bus and enables MAR load. The load register
instruction gates memory data into the data inputs of the
IDT49C402. The store register instruction gates register data onto
the bus and writes it into memory.

Move, Combine and Shift Register
Register-ta-register and shift operations are performed directly
by the IDT49C402 bit-slice.

Status Register Read/Write
Read and Write Status register operations select the Status RegIster and bus read and write, respectively.

Jump and Conditional Jump
Jump operations are done by enabling the PC to be loaded from
the bus using either immediate or register data for the jump address. Conditional Jump is done by enabling a conditions select
multiplexer to conditionally enable the PC load.

DUAL-PORT RAMs YIELD BIT-SLICE DESIGNS WITHOUT MICROCODE

APPLICATION NOTE AN-09

ADDRESS
(FROM MAR)

ADDRESS
(FROM PC)

0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOB

INSTRUCTION PORT: 2K X 64

0000

1A

1B

1C

10

0004

2A

2B

2C

2D

0008

3A

3B

3C

3D

DATA PORT:
8K X 16
1A
1B
1C
1D
2A
2B
2C
2D
3A
3B
3C
3D

Figure 5. Dual-Port Controller Memory Map

6 BITS

6 BITS

12 BITS

10 BITS

14 BITS

16 BITS
FIELD

FUNCTION

B
10-9
Stat EN
DIN
BusRNJ
MW, MAR
_Jump
Shift
Imm Data
Misc Control

402 reg address, bus read
select, or jump condition select
402 reg address or bus write select
49C402 instructions + carry-in
Enable Status reg load
402 D Bus: Memorv. PC Bus I field
Gate Bus read @ A, write @ B
Memory write enable, Id MAR enable
Enable Pl; loao, enable condition test
402 shifVrotate gating
Immediate Data - addresses, etc.
Misc bits for controller functions

A

BUS
RNJ
2 BITS 2 BITS

MW,
MAR
2 BITS

2 BITS

2 BITS

Figure 6. Dual-Port Controller Instruction Format

14-72

APPLICATION NOTE AN-09

DUAL-PORT RAMs YIELD BIT-SLICE DESIGNS WITHOUT MICROCODE

Jump and Save Return

Rise CONTROLLER TIMING

The Jump and Save Retum operation is performed by using the
immediate data field to provide the jump address and simultaneously storing the pe in a register selected by the B field. The immediate data field is gated to the bus, the pe is gated to the IDT49C402
data inputs and the IDT49C402 is instructed to perform a D-inputto-register-Ioad operation.

The design in Figure 4 is capable of a 55ns cycle time. A timing
diagram for a 55ns cycle time, assuming the 35ns dual~port RAMs,
is shown in Figure 7. The critical timing path, in this case, is the data
path from the Memory Address Register (MAR) through the data
port of the memory into the IDT49C402. If the dual-port RAMs are
slower than 35ns, the cycle is extended proportionately.

o

~o

I

~o

~o

5.0

55/0

I

"""-------..i

CLOCK

L

PC VALID
INSTR. RAM ACCESS
INSTRUCTION REG
SET-UP

~~____~~______~_3~5~n~s~t~A~A~:________~

I

--

~~-~-~---~_~---~'~~~
...

I

I

MAR SETTLE
DATA RAM ACCESS
402 D TO B SET-UP
A, B SETTLE
At B TO Y OR F = 0
WRITE DATA VALID
402 A TO Y PATH
CJUMP SET-UP TIME
2 x 74151 + F161

Figure 7. RISC Controller Timing Diagram

Table 2. Critical Path Timing
CONTROL PATH
PC settle: FCT161A
RAM Access
I reg set-up: FCT374A
Total

DATA PATH
6.5ns

MAR settle: FCT161A

35.0
2.5
44.0ns

RISC CONTROLLER APPLICATION

6.5ns

RAM Access

35.0

IDT49C402A. Din Set-up

10.0

Total

51.5ns

The RiSe controller's ability to load programs also means that
diagnostics can be loaded from the initial load EPROM. The initial
load EPROM can hold both the normal control program and various
test programs. The controller can load diagnostic programs from
the EPROM for board and system test without requiring permanent
space for them in the control memory. This allows self-diagnostics
at the hardware level with minimum cost impact on the hardware.

The utility of the RiSe controller design approach is that it allows
interactive system development, debugging and diagnostic testing. It also provides the potential for high-level language support of
the bit-slice design. Powerful interactive access to the RiSe controller can be provided by an RS-232 interface and a FORTH language interpreter program. This allows interactive coding and testing of the system, speeding up the test-and-analyze debug cycles.
This RS-232 interface can exist on a separate board extemal to the
RiSe controller, connected to the bus by a connector on the controller board. No additional hardware is required for access by the
designer to the system and this access can allow direct activation
and sensing of controller hardware, setting up timing loops for oscilloscope checks and on-line development of routines. If a floppy
disk controller is included in the extemall/O board, the RiSe controller can function as a stand-alone development system in the
same fashion as other stand-alone FORTH systems.

SUMMARY
The Rise controller uses high-speed dual-port RAMs to blend
the features of a bit-slice controller with the capabilities of a RISC
computer, allowing the microinstructions of the bit-slice approach
to become the instructions of a computer. This design approach
provides all the speed and architectural flexibility of microcoded
bit-slice designs, while allowing the use of interactive debugging
methods associated with microprocessors to shorten development
time.

14-73

m
",'
,",'
','

"
W*'

\

,' ~

"""

"~

By DAVID C. WYLAND

trol Inputs at TTL levels, either static or cycling at the rated cycle
time. In the CMOS standby region, the RAM is disabled and all inputs are at CMOS levels (i.e., within 0.20 volts of ground or
Vcc).The battery backup standby region is similar to the CMOS
standby region, but with a reduced power supply voltage of 2.0 or
3.0 volts rather than the normal 5.0 volts. The five regions of operation are shown in Figure 1. It shows a plot of Icc versus operating
region for an IDT7187L25, a 64Kx1 CMOS static RAM with a 25ns
access time. The highest current, ICC2, occurs under dynamic operating conditions where the part is cycling at its access time, a frequency equal to 1/tAA. The device current decreases linearly with
frequency to the static operating current, ICC1 . When the chip is
disabled, current drops immediately to ISB , the TIL standby current, or below. ISB corresponds to the current drawn by the chip
when it is disabled and with all inputs at TIL high or with all inputs
changing at the rated cycle time. With the inputs at TTL high, each
input circuit is in its linear threshold determining region and drawing supply current. The device current linearly decreases from
ISB to ISB1 as the various inputs are changed from TTL high levels
to CMOS levels which are within 0.20 volts ofVCCor ground. ISB1 is
the full CMOS standby current for 5.0 voltVcc. There are two other
CMOS standby cases, specified by ICCDR. ICCDR corresponds to
IS81 but is measured at two other power supply voltages, 2.0 and
3.0 volts. The ICCDRSpecification is used in battery backup applications to calculate the battery size required for a given battery lifetime. The 2.0 or 3.0 voit power supply voltages correspond to those
typically available from battery systems in battery backed applications.

INTRODUCTION
High-speed CMOS static RAMs are capable of very low-power
operation In the standby mode when the chip is disabled. In a properly designed circuit, the standby power may be a few microwatts,
as compared with several hundred milliwatts when the RAM is operating. This low-power capability can be used by the designer to
reduce system power and heat loading. It also makes these parts
suitable for battery backed permanent storage applications. In
these applications, power is kept on the RAM at all times to avoid
the loss of data when power is removed from the part. This is done
by using a battery to supply power to the RAM when system power
is shut off. In these applications, low standby power drain is important In order to achieve long battery life with a reasonably sized battery. In this application note, we study the operating and standby
power modes of the CMOS static RAM, the methods for achieving
low-power standby operation and some of the methods for implementing battery backup operation.

CMOS RAM Power Consumption
CMOS RAMs have five regions of operation with a different
power consumption for each region. These regions are: dynamic
operating, DC operating, TTL standby, CMOS standby and battery
backup standby .In the dynamic operating region, the RAM is reading and writing at speeds up to its rated read/write cycle time. In the
DC operating region, the RAM is enabled but not cycling: its address, data and control inputs do not change. In the TTL standby
mode, the RAM is disabled with its various address, data and con-

ICC (max.), rnA
for
IDT7187L25
64Kx1
CMOS RAM
25nstAA

100

100

70

10

..........

~

'"

o.~

0.100

0.225

O.15C

0.010
0.001
ICC2
Dynamic
Operating
f=1/tAA

ICC1
Static
Operating
f=O

ISB
TIL
Standby
All Inputs
TIL High
s= 1/tAA

ISB1
CMOS
Standby
All Inputs
CMOS
Leveis

ICCDR (3V)
Battery
Backup:
CMOS
Standby
VCC =3V

I CCDR (2V)
Battery
Backup:
CMOS
Standby
VCC =2V

Figure 1. CMOS RAM OperaUng Regions

© 1887 Integrated DevIce Technology, Inc.

14-74

PrInted In the U.S.A.

8/87

\
LOW-POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN-10

Components of Power Dissipation

The dynamic current component of ICC2 Is the result of transient currents in the intemal CMOS gates when they switch. These
transient currents can be understood by examining the switching
behavior of CMOS circuits. The basic building block of CMOS circuits, including RAMs, Is the CMOS logic gate. An example of a
simple CMOS gate, an inverter, is shown in Figure 2. It consists of
an N-channel device, 01, and a P channel device, 02. Ifthe input is
high, 01 will be on, 02 will be off and the output will be low. Ifthe
input is low, 02 will be on, 01 will be off and the output will be high.

There are five major sources of power dissipation In CMOS
RAMs:
• The RAM array
• The sense amplifiers
• The input buffers
• Dynamic switching
• Diode leakage
The RAM array power is that required to power the RAM cells
that hold the data. It is continuously drawn and is required to keep
data stored in the RAM. The sense amplifier power is that required
to read the data from the RAM array. It is drawn only when the chip
is enabled. Each input to the RAM chip has a buffer which draws
power when its input voltage is between 0.5 and 4.0 volts. In this
region, the input buffer operates as a linear device, performing a
logic threshold comparison. If the input is within 0.20 volts of VCC
or ground, the input buffer draws no power. Static RAMs draw additional power if they are cycled continuously at high speed. The additional power required is the dynamic switching power. It rises
linearly with the average frequency of read/write cycles. Diode
leakage is the current drawn by reversed biased diodes on the
chip, such as CMOS gates that are not switching. It is a small value
at room temperature, but it is strongly temperature-dependent,
doubling approximately every + 10°C. Because of its strong temperature dependence, it is usually the dominant component in
CMOS standby power specifications, such as the I CCDR specification used in battery backed RAM calculations. Diode leakage
and RAM array power are two unavoidable components of RAM
power dissipation.

VCC

INP~

OUTPUT

Figure 2. CMOS Inverter

This CMOS gate draws momentary current only when it
changes state. It draws no current when its input is at ground or
VCC because one ofthe two transistors will be off, eliminating a direct path from VCC to ground. This is what makes CMOS an inherently low-power technology - it draws no static current. However, it
does draw current momentarily when it changes state. When the
input transitions from low-te-high or high-te-Iow, it will pass
through the middle region where both 01 and 02 are on. During
this transition time, current will flow through 01 and 02. Since the
current flows only during the transition time, there is a fixed amount
of charge transferred from VCC to ground for each transition. This
results in a frequency-dependent current consisting of the sum of
all the charges transferred for all the gates on the chip times thefrequency of the charge transfers-I.e., the frequency of cycling the
RAM.

Standard and Low-Power RAMS
lOT RAM chips are divided into two types, standard power and
low power. This is indicated by a letter suffix to the part number, S
or L, respectively. These part types are power dissipation test selections from a single product, similar to speed grade selections.
The low:'power part is selected for low-power standby operation
and fully specified for the battery backup mode. The standardpower part has relaxed power specifications in the form of higher
limits on all I CC specifications, particularly the standby power
modes, and it is not specified for battery backed operation. Because of its relaxed power specifications, it is usually less expensive. The standard-power part is used where very low standby
power is not required, such as applications where the part is continuously enabled.

Static Operating Current-I CCl
The static current specification applies when the RAM is enabled but with its various inputs not changing and held at a TTL
high. In this condition, the RAM array, sense amplifiers and input
buffers are all drawing current. For the case ofthe IDT7187L25, this
is 70 milliamperes.

Dynamic Operating Current -I CC2

TTL Standby Current -I SB

The dynamic operating current specification applies when the
RAM is cycling at its specified access time. In the case of the
IDT7187L25, the access time is 25ns and the frequency at which
ICC2 is measured is 1/25 = 40MHz. ICC2 consists of two components: the DC operating component, ICC1 , and a frequency dependent component equal to (ICC2 - ICC1 ). In the case of the
IDT7187L25, the ICC2 value is 100 milliamperes and the frequency
dependent component is 100 - 70 = 30 milliamperes. Note that, as
the specified access time goes down, the specified dynamic operating current goes up. This is because the dynamic operating current is measured at a frequency equal to the inverse of the access
time. Fast access RAMs are measured at higher frequencies than
slow ones and have higher frequency dependent current components.

The TTL standby current specification applies when the chip is
disabled but its inputs are at TTL levels or changing at the rated
cycle time. Since a TTL high represents the worst case condition,
I SB is specified for the case of all inputs at TTL high.
In the TTL standby mode, the RAM array and input buffers draw
current, with the input buffers drawing the majority. The input buffers are CMOS circuits similarto the CMOS inverter shown in Figure
2, but with the geometry of the transistors designed so that the input
threshold is at a TTL-compatible threshold voltage of approximately 1.40 volts. Adiagramofthe device current versus input voltage for one input is shown in Figure 3. When the input is within 0.20
volts of ground or VCC, one of the two transistors is tumed off and
no current flows. Very little current flows even for the TTL low case
of 0.50 volts input. However, for the TTL high case of 3.0 volts typi-

14-75

m
~

LOW-POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN-10

cal, both transistors will be on and approximately 1.50 milliamperes, typical, will flow through them.

ture. At +25°C, the total current for an IDT7187L25 consists primarily of RAM array current, which may be 25J.LA. However, at
+70°C for commercial parts, the total current is specified at
300J.LA and is mostly leakage current. This rises to 1500J.lA at
+ 125°C for military parts. A plot of IS81 versus temperature is
shown in Figure 4.

10,000 ,-----,----r----,----r----,

lee for
One Input,
J.LA

1,000

t---+-I--40d---j---t----i

100

I-----I----t----I--+--t---f

Battery Backed CMOS Standby Current -I CCDR
The battery backed CMOS standby current speCification applies when the chip is disabled and all its inputs are at CMOS levels
(Le. within 0.20 volts of Vee or ground) and when Vee is at a reduced voltage of 2.0 or 3.0 volts. It is the same as IS81 except it is
measured at Vee voltages of 2.0 and 3.0 volts. In this state, only
the RAM array and leakage currents are drawn.
When Vee is reduced to 2.0 or 3.0 volts, the RAM is guaranteed
to retain data stored at 5.0 volts, but may not function: Le. it mayor
may not read or write reliably at these voltages. For this reason, the
chip is kept disabled while Vee is below 5.0 volts. When Vee is
restored to 5.0 volts, full functional operation is restored and the
data will remain as it was before vee was reduced.

10 t--~--~--jr_~rr---i
1.0
0.10

t--lf-+--~---If_--t-----I

.......,.._-.I

"--L.-........_ _"""---_........_ _

o

4
2
3
Input Voltage, Volts

5

Figure 3. Icc vs VIN for One Input

CMOS Standby Current-ISB1

DESIGN OF A HIGH-SPEED CMOS RAM MEMORY
ARRAY

The CMOS standby current specification applies when the chip
is disabled and all its inputs are static (Le., nonchanging) at CMOS
levels-within 0.20 volts of Vee or ground. In this state, only the
RAM array and leakage currents are drawn. The RAM array current
Is relatively independent of temperature, while the diode leakage is
strongly temperature dependent, riSing dramatically with tempera-

CMOS RAMs are often used in memory arrays. Figure 5 shows a
CMOS RAM array used as high-speed main memory for a 32-bit
microprocessor. The high speed of the CMOS devices allows operation of the microprocessor at full speed without wait states. Figure 6 shows an example of a design of such a memory array using
techniques which allow high-speed operation at low power.

100~--r--r---r--r--~--r--~-~

ISB1, leeDR 10
Relative to
1.0 I---t---+---+--=-~=!----I---+----+----I

+ 25°C

0.10 c:;;;._--'-_ _.!.-_--'-_ _l....-_-'-_ _l....-_-'-_----I
-60

-35

-10

15

40

65

90

140

115

Ambient Temperature, °C
Figure 4. ISB1 and ICCDR vs Temperature

32-BIT
MICROPROCESSOR

DATA BUS

,
~

h

"
CMOS RAM
MEMORY
ARRAY
512K x 32

I/O
DEVICES

Figure 5. CMOS RAM Array with 32-blt Microprocessor

14-76

,
,..
I/O
DEVICES

lOW-POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

ADDRESS
19 BITS

--~io'---IIDT74FCT244A

3

ARRAY
ENABLE

WRITE
ENABLE

APPLICATION NOTE AN-10

-"""'-r---t:~

3:8 DECODER
IDT74FCT138A

IDT74FCT244A

32-BIT DATA I/O
Figure 6. CMOS RAM Array Design

The 512Kx32 memory array of Figure 5 consists of 256 RAM
chips, each 64Kx1, arranged as an array of eight rows of 32 devices. The array is driven by CMOS devices capable of driving the
RAM inputs to CMOS levels within 0.2 volts of VCC or ground. An
IDT74FCT138A 3-to-8line decoder enables one row at a time. Ifthe
decoder is disabled, all RAM chips are disabled. The address and
write enable inputs are driven by IDT74FCT244A non-inverting
buffers and the data lines are buffered by a set of IDT74FCT245A
transceivers. Four sets of IDT74FCT244A buffers are used for the

address and write enable inputs, with each buffer driving 64 Chips.
This reduces the capacitive loading on each buffer to maintain
high speed. One set of IDT74FCT245A transceivers is used since
each one drives only eight RAM data inputs.
CMOS RAM arrays draw significantly less power in standby
mode if the RAM inputs are driven to CMOS levels. This is shown in
Table 1 for the RAM array of Figure 6. In this table, the total current
of the RAM array is shown for the case of TTL and CMOS drivers for
the address and control lines.

Dynamic OperaUng Power for TTL vs CMOS Drivers
Part

Qty.

Icc Using
74F Bipolar

Icc Using
FCTACMOS

Comments

IDT7187l25

32

3200

3200

Enabled, ICC2

IDT7187l25

224

10,080

10,080

Disabled, ISB

244

9

810

116

74F244174FCT244A

245

4

440

52

74F245174FCT245A

138

1

5

74F138174FCT138A

Total

20
14,550 rnA

13,453 rnA

Standby (non-operating) Power for TTL vs CMOS
Part
IDT7187l25

Qty.

Icc Using
74F Bipolar

IccUslng
FCTACMOS

Comments

256

11,520

77

Disabled, ISBllsBl

244

9

810

116

7 4F244174FCT244A

245

4

440

52

74 F245174FCT245A

138

1.

2

74F138174FCT138A

Total

20
12,790 rnA

247 rnA

Table 1. CMOS RAM Array Power

14-77

LOW-POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN-10
The speed of the array is a combination of the propagation delay
of the RAM chips, the circuits driving them and the time delay
caused by driving the capacitance of the array. The time delay
caused by driving the capacitance depends on the design of the
array. This delay is proportional to the capacitance being driven by
each IC output, with a typical design value of 3.0ns/1 OOpF for FCT
logic and 6.0ns/100pF for RAM outputs. This delay applies to capacitance above the rated load capacitance for the device, which
is 50pF for FCT devices and 30pF for the IDT7187 RAM. This delay
applies for address and write enable drivers driving the RAM chip
inputs and for each RAM chip driving other RAM outputs and its
IDT74FCT245 input. In this design, the RAM chip input capacitance is 5.0pF/input, and the output capacitance is 7.0pF/output.
Since the RAM data input and output pins are connected together,
the total capacitance is (5.0 + 7.0) = 12.0pF/RAM chip. Thus, each
RAM output must drive seven RAM outputs, eight RAM inputs and
one IDT74FCT245 input for a total of (7*7+8*5+5=5)=94pF.
The net capacitance used in the delay calculation is (94-30) =
64pF and the corresponding delay is (6*64/100) = 3.84ns.
If one set of drivers is used to drive all the devices, the capacitance can be high and the delay can be significant compared to the
delay of the RAM chips. In high-speed designs, several drivers are
used so that the capacitance seen by each driver is moderate and
the speed delay is small. A comparison of the total propagation delay of a RAM array for various combinations of drivers is shown in
Table 2.
To design a RAM array for high speed, both the address and
chip select paths must be considered. In Table 2, the propagation
delay with capacitive loading is calculated for both paths and the
larger of the two numbers is used to calculate the access time ofthe
array as a whole. Note that the critical path changes from address
to chip select as the capacitive loading of the address drivers is reduced.

The power savings from using CMOS drivers can be dramatic,
as shown in Table 1. The difference between the CMOS and bipolar current is only 7.6% in the dynamic case but, in the standby,
non-operating case, the current differs by a factor of 51.8. The
lower standby current with CMOS drivers occurs because the RAM
inputs are kept at CMOS levels, putting them into the I SB1 ' CMOS
standby region. USing CMOS drivers does not, however, put the
unselected rows into the I SB1 region during dynamic operation of
the array. This is because the address and data inputs to the
unselected RAM chips are changing rather than being held at
static levels. Thus, I SB must be used instead of I SB1 in these
calculations.
The dynamic and standby I CC specifications assume that the
RAM is cycling at its rated cycle time. The cycle time of the RAM
array will be longer than the rated cycle time of the RAM chips. This
will reduce both the dynamiC operating current of the enabled row
and the standby power of the disabled rows. A conservative estimate of the current requirement reduction can be made by reducing the current of the disabled rows by the ratio of the RAM chip
rated cycle time to the RAM array cycle time. If the RAM chip cycle
time is 25ns and the RAM array cycle time is 100ns, the current required by the disabled rows will be (0.25*10,080 + 0.75*67) =
2,570mA. The current savings will be (10,080-2,570) = 7,510mA.
The RAM array operating current will therefore be (13,453 -7,510)
= 5,943mA, a reduction of 56%.

RAM Array Speed Considerations
CMOS RAM arrays can achieve low power while maintaining
high speed. This Is done by using the high speed of the CMOS
RAM chips and taking care that speed is not lost in the surrounding
logic. The primary problem in driving large RAM arrays is driving
the capacitance of the address and data inputs.

Address and Chip Select Path Delays vs Capacitive Drive
Delay Source

256/Driver
Cap
Delay

64/Driver
Cap
Delay

32/Driver
Cap
Delay

16/Driver
Cap
Delay

-

4.3

8

4.3

16

4.3

32

4.3

Addr Cap Delay'"

1280

36.9

320

8.1

160

3.3

80

0.9

IDT7187L25 - tAA

-

25.0

25.0

-

25.0

-

25.0

Addrs Path Delay

-

66.2

37.4

32.6

30.2

iDT74FCT244A

IDT74FCT138A

-

5.8

-

5.8

-

5.8

-

CS Cap Delay'"

160

3.3

160

3.3

160

3.3

80

0.9

IDT7187L25 - tACS

-

25.0

256

25.0

256

25.0

256

25.0

CS Path Delay

-

34.1

-

34.1

-

34.1

-

31.7

5.8

'" 3ns/100pF - 50pF
RAM Array Access Time vs Capacitive Drive
Delay Source

256/Driver
Chips
Delay

64/Driver
Chips
Delay

32/Driver
Chips
Delay

16/Driver
Chips
Delay

-

-

8

-

16

256

256

-

256

-

256

-

2

-

2

-

2

-

4

-

Path Delay

-

66.2

-

37.4

-

34.1

-

31.7

IDT74FCT245A

4

4.6

4

4.6

4

4.6

4

4.6

Out Cap Delay"''''

-

3.8

-

3.8

-

3.8

-

3.8

264

74.6

270

45.8

278

42.5

296

40.1

IDT74FCT244A
IDT7187L25
IDT74FCT138A

TOTAL

2

"'''' 6ns/100pF - 30pF
Table 2. CMOS RAM Array Speed vs Drive
14-78

32

\

LOW-POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN-l0

Using RAM Modules to Save PC Board Space

ARRAY DESIGN FOR LOW POWER

RAM modules can be used to significantly reduce the printed
circuit (PC) board area required for a RAM array. A RAM array using
256 chips (ofthe IDT7187 type) will require approximately (0.4 * 1.2
* 256) = 122.88 square inches of board space, assuming 24-pin,
300 mil DIP devices with 0.1 inch spacing. RAM modules, such as
the IDT7M624, use surface mounting to fit sixteen of the IDT7187
RAM chips on a 2.0 x 0.9 inch DIP module. Sixteen of these modules could directly replace the 256 RAM chips in the array. The PC
board area using these modules would be (16*2.0*1.0) = 32
square inches, assuming 0.1 inch spacing, a savings of approximately a factor of four over mounting individual chips.

The RAM array design of Figure 6 can be redesigned for lower
operating power by using CMOS RAM chips with input gating,
such as the IDT7164, 8K x 8 RAM. An example of such a design is
shown in Figure 7. Table 3 compares the characteristics of the lowpower design in Figure 7 against the high-speed design in Figure

6.
In parts with input gating, the input circuits are powered down
when the chip is disabled. These parts have very low TTL standby
IS8 values because only the chip select inputs are on in the TTL
standby case. In RAM array design, this means that the disabled
rows have very low standby power when compared to RAMs with
conventional inputs, as used in the design of Figure 6.

ADDRESS
19 BITS

ARRAY _-=+:.-:~
ENABLE
WRITE
ENABLE -.;,L-,,--:I>/L..-_ _ _ _- - '

32-BIT DATA I/O
Figure 7.

Function
RAM Chip Type
Chip Organization
Speed: tM
Operating Power
Standby Power

Low-Power CMOS RAM Array Design

High-Speed
Design

Low-Power
DeSign

IDT7187

10T7164

64Kx1

8Kx8

42.5

64.7

ns

13,453

853

rnA

247

81

rnA

Units

Comments

32/driver

Part Count

278

276

ICs

32/driver

Battery Power. 3.0 V

81.6

30.5

rnA

at +70°C

Table 3. Comparison of High-Speed vs Low-Power Array Designs

14-79

LOW·POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN·l0

The 512K x 32 memory array In the low·power design shown In
Figure 7 consists of 256 RAM chips, each 8K x 8, arranged as an
array of 64 rows of 8 devices. The array is driven by CMOS devices
capable of driving the RAM inputs to CMOS levels, within 0.2 volts
of VCC or ground. Two IDT74FCT138A, 3-t0-8 line decoders are
used with the two RAM chip selects to enable only one row at a
time. An IDT74FCT240A inverter is used between one decoder and
the RAM array to drive the positive active RAM chip enable. If either
decoder Is disabled, all RAM chips are disabled. The address and
write enable inputs are driven by IDT74FCT244A non·inverting
buffers and the data lines are buffered by a set of IDT74FCT245A
transceivers. Four sets of IDT74FCT244A buffers are used for the
address and write enable inputs, with each buffer driving 64 chips.
This reduces the capacitive loading on each buffer in order to
maintain high speed. Two sets of IDT74FCT245A transceivers are
used to reduce the loading on the RAM output pins so that each
RAM drives only 32 outputs.
The CMOS RAM array in Figure 7 draws significantly less power
than the design in Figure 6, as is shown in Table 4. The primary
reasons for this reduction are that the rows that are disabled draw
very little power due to their gated inputs and only four RAMs in a
row are enabled at anyone time rather than 32. The result is that the
dynamiC power is reduced by a factor of 15.7 and the standby
power is reduced by a factor of 3.0. Note that I SB1 is used in calculating the power of the disabled rows. This is because there is no
dynamic standby effect with input gated RAMs since the input buffers are tumed off. Also, since the chip enables are driven to CMOS

levels by CMOS devices, there is no TTL standby current drawn by
the chip select inputs.

Low-Power RAM Array Speed Considerations
RAM array speed considerations for the low-power deSign in
Figure 7 are similar to those of the design in Figure 6. The delay for
the address and chip select paths are calculated and the larger of
the two numbers is used in calculating the total delay. The total delay for various combinations of driver loading is shown in Table 5.
RAMs with gated inputs (i.e., input buffers powered up by chip
select) trade speed for low power. Gating the inputs with the chip
select means that the chip select access time is equal to, or longer
than, the address access time. This means that the chip select decode propagation delay is no longer hidden by a fast chip select
access time. As a result, the chip select path is usually the critical
path in gated input designs.
The design in Figure 7 is somewhat slower than the design in
Figure 6 because x8 RAMs rather than x1 RAMs are used. In the
minimum chip count configuration, each RAM output in Figure 6
drives seven other RAM outputs, plus an IDT74FCT245A input. In
the minimum chip count design in Figure 7, each RAM output
drives 63 other RAM outputs, plus an IDT74FCT245A input. This is
the source of another tradeoff of speed versus chip count in the
RAM output path. The output drive problem is helped by the fact
that the IDT7164 RAMs are common I/O devices with a capacitance of7 .0pF per I/O pin, rather than the combined capacitance of
12.0pF for the IDT7187 design which ties the Input and output pins
together.

Dynamic Operating Power for Low·Power RAM Array

Oty.

Part

Icc Using
FCTCMOS

Comments

IDT7164L30

4

560

Enabled, ICC2

IDT7164L30

252

50

Disabled, IS81

IDT74FCT244A

8

103

IDT74FCT245A

8

103

IDT74FCT138A

2

11

2

26

IDT74FCT240A
Total

853mA

13,453mA for Fig, 6.

Standby Power for Low·Power RAM Array
Part
IDT7164L30

Oty.

Icc USing
FCTCMOS

256

51

IDT74FCT244A

8

12

IDT74FCT245A

8

12

IDT74FCT138A

2

3

IDT74FCT240A

2

3

Total

81mA

Comments
Disabled, IS81

247mA for Figure 6

Table 4. CMOS RAM Array Power

14-80

LOW-POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN-10

Address and Chip Select Path Delays vs Capacitive Drive
256/Drlver
Delay
Cap

Delay Source

*

32/Drlver
Delay
Cap

16/Drlver
Cap
Delay

-

4.3

8

4.3

16

4.3

32

4.3

1280

36.9

320

8.1

160

3.3

80

0.9

IDT74FCT244A
Addr Cap Delay

64/Drlver
Delay
Cap

IDT7164L30 - tAA

-

30.0

-

30

-

30

-

30

Addrs Path Delay

-

71.2

42.4

37.6

-

5.8

-

35.2

IDT74FCT138A

-

IDT74FCT244A

-

4.3

-

4.3

-

4.3

-

4.3

CS Cap Delay *

160

3.3

160

3.3

160

3.3

80

0.9

IDT7164L30 - tAcs

-

35.0

256

35.0

256

35.0

256

35.0

OS Path Delay

-

48.4

-

48.4

-

48.4

-

46.0

5.8

5.8

5.8

* 3ns/1oopF - 50pF
RAM Array Access Time vs Capacitive Drive
Dolay Source
IDT74FCT244A

256/Drlver
Chips
Delay

64/Driver
Chips
Delay

32/Driver
Chips
Delay

16/Driver
Chips
Delay

2

-

8

-

8

-

8

-

256

256

-

256

-

256

-

2

-

2

-

4

-

IDT74FCT138A

2

IDT74FCT240A

2

-

2

-

2

-

3

-

Path Delay

-

71.2

-

48.4

-

48.4

-

46.0

IDT74FCT245A

4

4.6

4

4.6

8

4.6

16

4.6

Out Cap Delay **

-

25.1

-

25.1

-

11.7

-

4.9

266

100.9

272

78.1

276

64.7

287

55.5

IDT7164L30

TOTAL

** 6nsl1oopF - 30pF
Table 5. CMOS RAM Array Speed vs Drive

BATTERY BACKUP OPERATION OF CMOS RAMS

Driving the RAM Inputs to CMOS Levels During
Battery Operation

Because of their low standby power, CMOS RAMs are often
used as permanent memory where a battery is used to maintain
data in the RAM by supplying power when the system power is off.
These are called battery backup applications. In battery backup
applications, the battery supplies a lower voltage-2.0 to 3.0 volts
versus the 5.0 volts of normal operation. This lower voltage allows
use of a smaller battery, both because of the lower voltage for the
same ampere-hour rating and because the RAM draws less current
at the lower voltage.
The design of a battery backed RAM array includes consideration of the following problems:
• Driving the RAM inputs to CMOS levels during battery
operation

In order to achieve the low power levels specified for battery
backup operation, the RAM inputs must be driven to CMOS levels.
In the array design of Figure 6, this is done by driving the RAM
chips with FCT CMOS drivers for the 5.0 volt Vcc case. These levels must also be guaranteed for the 3.0 volt VCC, battery backed
case. In the case of the FCT CMOS devices, the output drive is also
specified to be at CMOS levels for the 3.0 volt VCC case.
The RAM array drivers must be able to maintain CMOS output

• Determining the power drain in battery backup mode

levels with 3.0 volt VCC and maximum leakage from the RAM inputs and/or outputs. CMOS FCT drivers are used for the address,
write enable, chip select and data inputs of the design in Figure 6.
The worst case leakage will be for 64 address inputs being driven
by a single driver. The maximum specified leakage for any input of

• Switching from the system supply to/from the battery supply while maintaining VCC at the RAM

the IDT7187l25 RAM chips is 2.0 microamperes at 3.0 volts VCC
over the temperature range. The maximum total leakage for 64 in-

14-81

W"
~

LOW-POWER AND BATIERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN-10

puts will then be 128 microamperes. The IDT74FCT244A drivers
are rated at an I OL of 300j.lA and an IOH of 32j.lA at 3.0 volts Vee.
If the address drivers are kept in the low state, the 300~A I OL specification is more than enough to keep the outputs at a CMOS low
level.
Additional drivers are required to keep the write enable and chip
select Inputs in the CMOS high state. The write enable drivers can
be kept in the low state if the RAM chips are kept disabled; however, it would be more prudent to keep them in the high state to ensure that no write can possibly occur. This requires more drivers
for these lines than the address lines. With a 32j.lA I OH specification, each CMOS FCT part can drive a maximum of 16 inputs.
Since each IDT74FCT244A supplies eight drivers, this would
mean two chips instead of one for the write enable input. Two

IDT74FCT138A decoders will also be required in order to have
each decoder output drive only 16 RAM enable inputs. A drawing
of the RAM array with this implementation is shown in Figure 8.
The FCT CMOS drivers will keep the RAM inputs at CMOS levels during battery backup mode; however, the inputs to the FCT
devices must also be kept at CMOS levels during this mode. If the
rest of the system which communicates with the RAM array is powered down, these inputs should be at or near zero volts, which
solves this problem. To ensure this case, a resistor to ground
should be added to the input of each FCT CMOS device to provide
a path for the input leakage of these devices. A 10K resistor will
support the input leakage of ten FCT devices at 2j.lA per device and
a VOL of 0.20 volts.

14-82

LOW·POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN·10

ADDRESS __H:~{:H______- T_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
0-15

ADDRESS
16-19

IDT74FCT138A

IDT74FCT138A

WRITE
ENABLE ------------~

DATA
BITS 0-15

IE] = 10K resistor to ground on these lines
Figure 8. Hlgh·Speed CMOS RAM Array Design for Battery Standby

14-83

DATA
BITS 0-15

m

LOW-POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN-10

Determining the Current Drain in Battery Backup
Mode

rent for the array drivers. A calculation of the current required for the
RAM array of Figure 6 in the battery backup mode, including the
additional drivers for write enable and chip select, is shown In
Table 6.

The RAM array standby current in battery backup can be calculated by adding the current required for the RAM chips and the cur-

Battery Backed Standby Current at 3.0 Volts
Part

Oty.

IDT7187L25

256

IDT74FCT244A

10

IDT74FCT245A

4

0.004

IDT74FCT138A
Total

2
272

Typ., +25°C

Max., +70°C

Max., + 125°C

3.84

57.6

230.4

0.010

15.0*

15.0

6.0*

6.0

0.002
3.9mA

3.0

3.0*
81.6mA

254.4mA

..

* Max. for commerCially rated parts. MIlitary rated parts will have lower values at + 70°C .
Table 6. High-Speed CMOS RAM array Battery Standby Current

Battery Backed Operation of the Low-Power RAM
Array Design

ilydrive its 32 inputs to VIL. Only the RAM chips, the IDTFCT138A
decoders and the IDTFCT240A drivers need be powered by the
battery.
The RAM array standby current in battery backup can be calculated by adding the current required for the RAM chips and the current for the array drivers. A calculation of the current required forthe
RAM array in Figure 7 in the battery backup mode, including the
additional chip select decoders, Is shown in Table 7.

The low-power RAM array design in Figure 7 is well suited to
battery backed operation. Because of the gated Input design of the
RAM chips, only the chip select inputs of the RAM need be driven
to CMOS levels. This means Increasing the number of decoders for
the low active chip select from two to three so that each decoder
drives a maximum of 16 inputs to V IH . The non-inverting chip select input is not a problem because the IDTFCT240A driver will eas-

Battery Backed Standby Current at 3.0 Volts
Part

Oty.

IDT7164L30

Typ., +25°C

Max., +70°C

Max., +125°C

256

3.84

23.0

76.8

IDT74FCT138A

3

0.003

4.5*

4.5

IDT74FCT240A

2

Total

0.002
3.9mA

3.0*
30.SmA

3.0
84.3mA

* Max. for commerCially rated parts. Military rated parts will have lower values at + 70°C.
Table 7. LOW-Power CMOS RAM Array Battery Standby Current

Switching Between System V cc and the Battery

be met by the circuit shown in Figure 9. In this circuit, the silicon
diodes perform a smooth transfer of power from the system Vce to
the battery backed Vee and vice-versa. The diode to Vee is not
strictly required because of the FET switch; however, it can reduce
the switching transient when the FET turns on by reducing the voltage that must be switched, assuming that Vee comes up slowly
before the FET tums on.
The P-channel power FET is used to reduce the drop across the
diode to 0.10 volt during normal operation so that the RAM array
Vee Is kept within specifications. The IDT74FCT240A inverting
driver is used to drive the gate of the P-channel power FET. When
the power down signal is high, indicating normal system operation,
the IDT74FCT240A output is low and the P-channel FET is on.
When the power down signal is low, indicating that the power
is going down or isalready down, the IDT74FCT240A drives the

In a battery backup system, VCC forthe RAM array must switch
between the battery and the system VCC without causing the RAM
to lose data in the battery backup mode and allowing the RAM to
achieve full speed In the normal operation mode. This requires a
switch design for VCC. Also, the RAM array must be disabled during the battery backup mode and during switching between the
battery and normal VCC. This is done by using a power-down detect signal from the power supply which forces the RAM to be disabled.
When switching from the system to the battery, VCC must be
kept above the 2.0 volt minimum guaranteed data maintenance
voltage at all times. When switching from the battery to the system,
Vce at the part must be within the Vee specifications for nomal
operation, (I.e., 4.5 volts minimum). These two requirements can

14-84

LOW-POWER AND BATTERY BACKUP OPERATION OF
CMOS STATIC RAMS

APPLICATION NOTE AN-10

differ depending on system requirements. For example. a PNP
transistor or an N-channel FET with a gate drive to + 12 volts could
be used instead of the P-channel FET.

P-channel FET gate high to tum it off. When the battery is supplying the \te. the FET gate will be driven to the most positive voltage
on either of its two terminals. ensuring that it will be off. Note that
the circuit of Figure 1 is a typical example only - actual designs will

SYSTEM Vee

P-CHANNEL
POWER FET

SILICON
DIODES
1N5400.
ETC.
POWER DOW

BATTERY
LITHIUM OR
NICAD·
3.6 VOLTS

IDT74FCT240A
INVERTING DRIVER
VecTO RAM ARRAY
Figure 9. Battery Power Switch Circuit

CONCLUSION
CMOS RAMs have the capability of high speed and low power.
In this application note. some of the possibilities for using these capabilities have been explored in the hope that the designer may
use them to good advantage in new designs.

14-85

By Michael J. Miller

INTRODUCTION

An upgraded architecture, the 2903, was introduced in 1978 and
is shown in Figure 2. The 2903 features a three-bus architecture for
the data paths. Like the 2901, this slice contains a 16-word-by-4-bit
dual-port RAM connected to an ALU which performs arithmetic
and logic operations. This architecture, however, has the added
capability of bringing extemal operands to the ALU via the DA and
DB buses. The ALU can perform 16 different arithmetic and logic
operations in all. Its output can be written shifted up or unshifted to
either the RAM or the Y outputs. The 2903 architecture also
I~c?rporates .several special functions which facilitate multiply,
diVide and sign magnitude to two's complement conversion. A
special.version of this architecture, known as the 29203, features
both BCD and binary arithmetic capability. In addition, the DA, DB
and Y buses are all bi-directional. Both the 2903 and 29203 also
contain the Intemal 0 Register used to perform double-length
operations.

Micr9program architectures are capable of meeting many of
today's system design requirements. Nevertheless, trade-offs exist
between performance and cost In terms of power consumption
. and the total number of parts needed to satisfy design functionality.
For a given device family, cost considerations are directly related
to the speed/power ratio. In recent years, advancements In
speed/power performance for bipolar bit-slice technologies have
slowed considerably while, at the same time, very high-speed
, CMOS has directly impacted the bit-slice world, offering greater
functional speed and an Increased level of Integration.
Currently, packing density and the ultimate speed of performing
a function in Integrated circuits is limited by the heat dissipation
capabilities of the chip package. Since CMOS has a speed/power
ratio almost an order of magnitude higher than conventional
bipolar device families, It Is rapidly becoming the technology of
choice for new bit-slice functions. Denser device packing at higher
speeds gives CMOS technology more freedom for creating new
high-performance architecture.

Historical Perspective
The most traditional bit-slice microprocessor architecture for
the data path portion of the machine is the 2901 architecture
developed in the mid-seventies. A simplified diagram is shown i~
Figure 1. Here we see a tightly coupled RAM and ALU architecture
which contains single Input and output data paths. The 2901 Is a
4-bit microprocessor slice that features 16 words of intemal4-bit
wide RAM and an eight-function ALU capable of performing both
arithmetic and logic operations on two operands. The ALU output
can be loaded Into the RAM, shifted up, shifted down or unshifted.
Also Included is an additional temporary register normally called
the "0 Register". It Is capable of performing double-length shift
operations and facilitating multiplication and division. The 2901
has become the industry standard for bit-slice microprocessor
architectures.

V
Figure 2. 2903/203 Architecture

A third architecture of historical Importance is the
29116/29117. This architecture, shown in Figure 3, features a
32-vyord 16-bit single-port RAM, a 16-bit accumulator and a 16-bit
o Input latch. These three possible operand sources are
connected to the ALU through a multiplexer. One path into the ALU
contains a barrel shifter capable of rotating the 16-bit operand. The
ALU can perform various combinations of operations on one ortwo
operands. The three operand Instructions are primarily rotateand-merge or rotate-and-compare. The ALU output is fed back to
both the RAM and the accumulator. In the 29116, the Y output is
intemally connected to the 0 Input, forming a 16-bit bidirectional
data bus. In the 29117, they remain separate and there is a 16-bit 0
input and a 16-bit Youtput bus similar to the structure of the 2901.
The 29116 contains an Internal status register for the carry,
overflOW, sign and zero flags. Microinstruction to the 29116 Is an
encoded field Instruction set.

D

V
Figure 1. 2901 Architecture

CEMOS and MICROSLICE are trademarks of Integrated Device Technology. Inc.
© 1S87 Integrated DevIce Technology, Inc.

14-86

PrInted In the U.S.A.

10,87

A·POWERFUL NEW ARCHITECTURE FOR A
32·BIT BIT·SLlCE MICROPROCESSOR

APPLICATION NOTE AN·11

D

out of the ALU. The lOT49C403, incorporating a three-bus architecture, combines the standard functions of four 2903s and a 2902.
Both,parts have additional control features aimed at enhancing the
performance of traditional bit-slice microprocessor designs.

Conservation of Microcode

V (29117)
Figure 3. 29116/7 Architecture

New Technology for Bit-Slice
Integrated Oevice Technology's CEMOS TM technology offers
greater speed and output drive at lower power levels. It was only
natural to incorporate this technology into new bit-slice designs,
thus offering improvements over the traditional Mindustry standards."
The IOT39C01 is totally pin-compatible and functionally identical to the 2901. The MC" grade version is equal to the fastest bipolar
4-bit slice and, in addition, lOT offers a MO" grade slice which is
25% faster than its MC" speed grade. Recently, lOT introduced an
ME" grade which is 25% faster than the MO" grade.
The IOT39C03 and IOT39C203 are pin-compatible and functionally identical to the 2903 and 29203, respectively. IOT39C03
MB" grade and IOT39C203 MA" grade slices are also available.
Again, these devices are about 25% faster and offer considerably
higher output drive at lower operating power than their equivalent
bipolar counterparts.

lOT has minimized bit-slice redesign cost in the CMOS·to-bipolar transition through Mconservation of microcode". This is
achieved by taking full advantage of CMOS Integration capabilities
while utilizing pre-existent 2900 family instruction sets.
The IOT49C410 sequencer is capable of executing old
microcode with no alterations. The IDT49C402 and IDT49C403
ALUs can resolve compatibility issues at several levels. The simplest solution involves connecting only the instruction lines which
correspond to the 2901 or the 2903/203, respectively, and tying the
remaining inputs to their respective default levels. This permits the
design to execute previously assembled microcode.
In some design instances, it may be advantageous to utilize
some of the new features of the lOT ALUs-deeper register files or
new data paths, for example. This involves changing microcode to
control the additional instruction lines and can be achieved by
modifying the assembler and reassembling the old microcode.
The design of new high-performance products may require writing new, more robust microcode. This should come as no surprise
when considering the architectural complexity of modern state-ofthe-art designs. A good example is the next generation of 32-bit
processors capable of working on bit fields.

32-Bit Microprocessor Slice
Perhaps the best known architecture in the 32-bit microprocessor slice arena is the 29300 family of devices, illustrated in Figure 4.
It is a non-cascadable architecture which involves multiple chips.
This family contains an ALU and a RAM register, but multiple RAM
register devices must be used to build a 32-bit microprocessor
slice. This approach is most likely due to the relatively high power
consumption inherent to bipolar technology. It is interesting to note
that there are three tightly coupled buses (OA, OB and Y) with the
ALU and, since the design uses multiple chips, we see a four-port
RAM and a three-port ALU.
'

D

New and More Powerful Bit-Slice Devices
The order of magnitude difference in speed/power ratios between CMOS and bipolar technologies is leading to ever-increasing levels of CMOS integration. lOT has designed a new bit-slice
family (the IOT49COOO) which executes standard AMO 2900
microcode, but at greater than four times the circuit density. The
key devices in this family are the IOT49C410, IOT49C402,
IOT49C403 and IOT49C404. In general, these parts have wider
data paths, more internal paths, larger RAM and support higher
clock rates than their bipolar predecessors.
The IOT49C410 is architecture and function code-compatible
with the 291 OA and features an extended 16-bit address path which
allows for programs upto 64K words in length. It is a microprogram
address sequencer intended for controlling the execution sequence of microinstruction stored in microprogram memory.
Thus, the IOT49C410 can be used at the heart of next generation
designs to orchestrate the operation of other parts in lOT's
MICROSLICE™ family of bit-slice devices.
The IOT49C402 and IOT49C403 are very-high-speed, fully
cascadable 16-bit CMOS microprocessor slice units. The
IOT49C402 performs the standard functions of four 2901s and a
2092 with a 2-bus architecture: one bus into the ALU and one bus

14-87

DA~+---~--r-----~

L...------~~-DB

v
Figure 4. 29300 ALU & RAM Family Architecture
(2 x 16-Bit RAMs Plus ALU)

A POWERFUL NEW ARCHITECTURE FOR A
32-BIT BIT-SLICE MICROPROCESSOR

APPLICATION NOTE AN-11
Identical data when the same address is applied to all of the four
address inputs. As in all other bit-slice microprocessor devices, the
Internal latches are transparent at the output ports during a high
clock signal. Data Is held In the latches when the clock signal is
low. As Figure 6 indicates, each data input path has a multiplexer
which selects data from either the ALU/Y bus, the DNDB bus or, in
the case of the T input, the Internal counter.
The Funnel Shifter is a powerful 32-bit shift unit which operates
on two 32-bit inputs and generates a 32-bit output. It is capable of
implementing all basic 32-bit barrel shift functions including shift
up, shift down, rotate up and rotate down In any number of
positions. Sixty-four-bit operations are performed by cascading
devices. This high-speed shifting Is particularly useful in
operations such as mantissa normalization for floating-point
arithmetic or In schemes which involve frequent packing and
unpacking of data. The Funnel Shifter can also be used to extract
32-bit output from a sliding window applied to 64-bit input. Control
can be supplied from a number of sources and can be either a
32-bit word or an encoded 7-bit start position and 7-bit shift select
function. A positive start position moves the sliding window
towards the least significant bit. Conversely, a negative start
position moves the window towards the most significant bit. In
addition, the Funnel Shifter can perform various types of sign
extension and 0, 1 or M-link fills as required by the user.
The eight-function ALU has three arithmetic, four logic and one
special opcode function. Arithmetic functions are R + S, R - Sand
S - R. The logic functions are OR, AND, exclusive-OR and
exclusive-NOR. The eighth function places the IDT490404 in a
special opcode mode. These special Instructions might Include
unsigned and two's complement conversion. The device is
capable of performing two's complement multiply or divide on
either 32-bit or 64-bit operands.
A 32-bit Merge Logic block Is under the control of the 32-bit
mask generator. Normally, the merge operation involves selecting
bits from either the V or W operand and presenting a final 32-bit
word to the Y bus (see Figure 6). The 32-bit mask Is generated by
the mask generator which is controlled by a 2-blt mask select field.
Mask selection may occur in several different fashions In
conjunction with the various RAM outputs and the start position
and width input fields. The W operand can be selected from a
number of different sources including all ones and zeros. The
Merge Logic block also features a priority encoder conceptually
similar to the 29116. It is valuable in floating-point operations, as
well as various types of polled interrupt systems.

The IDT49C404 Enhances 32-Bit Architecture
The lOT490404 microprocessor architecture exploitS advanced
CMOS technology to Implement maximum functionality on a
single chip. Figure 5 Is a simplified block diagram of this slice. The
IDT490404 features a powerful seven-port 64-word-by-32-bit
registerfile containing four output ports and three Input ports under
the control of four 6-bit address fields. The lower half of the block
diagram shows the FS/ALUlML portion of the IDT490404 for
manipulating 32-bit data. Figure 5 also shows a 32-bit Funnel
Shifter which is capable of driving the multi-function 32-bit ALU
whose output can be merged with another operand under the
control of a merge mask. This is called Merge Logic. In this case,
the ALU can perform operations on bit fields In 32-bit words.
Applications are far-reaching and Include graphics, communications, field searching, packed data operations, etc.

DA

DB

y
Figuro 5. Tho IDT49C404A
32-Blt Caseadablo RAM and ALU Sileo

Detailed Description of the IDT49C404
The IDT490404 is shown in more detail in Figure 6. This device
is an expandable microprogram mabie 32-bit microprocessor slice
fabricated using advanced high-speed, low-power CMOS
technology. This monolithic three-port (DA, DB and y) slice
contains a seven-port 64-word-by-32-bit RAM, 32-bit cascadable
Funnel Shifter, 32-bit wide ALU, 32-bit wide Merge Logic block and
a 32-bit mask generator. The IDT49C404 is capable of 32-bit
counting for matrix operations as well as byte, word and
double-word operations. This architecture and its instruction set
are optimized for use in microprogram mabie microprocessors,
high-speed communications, graphics and disk controllers and
digital signal processing algorithms. It also provides advanced
intemal diagnostics capabilities for detecting and locating hardware system failures. The versatility of these capabilities allows test
and error detection during engineering development, in the
manufacturing cycle or at the customer facility after delivery of the
part.
The 64-word-by-32-bit working RAM has seven ports: three
dedicated input ports (A-IN, B-IN and T-IN) and four dedicated
output ports (A-OUT, B-OUT, T-OUT and Q-OUT). Each port
output is latched. Any four RAM locations can be accessed at the
address ports by using the A, B, T and Q address fields. Data can
be read simultaneously from all four ports and each will contain

Diagnostic Capability
The IDT490404 employs a diagnostic scheme involving data
entry and extraction through serial input and output pins. This
approach .allows diagnostic evaluation at any stage of the
development, manufacture and utilization cycle. In general,
access to test debug points has become more and more difficult
because board level packing densities have increased dramatically. For this reason, customers will find serial diagnostiCS to be of
significant benefit. This is especially true in double-sided surface
mount technologies.
lOT's method of employing serial diagnostics maintains
maximum flexibility while using a minimum number of pins. The
data is passed in and out on single pins, while transfer is controlled
by a diagnostics clock and a command/data mode input. Thus,
only four pins are required. Systems level diagnostics involves the
serial connection of output and input of adjacent devices. In effect,
this cascades devices into one long serial shift register. The
diagnostics clock and command/data mode lines for the devices
are connected in parallel. This approach minimizes the number of
device connections required for diagnostics.

14-88

A POWERFUL NEW ARCHITECTURE FOR A
32-BIT BIT-SLICE MICROPROCESSOR

APPLICATION NOTE AN-11

DB BUS

DB BUS

AADDR

BADDR

QADDR

TADDR

OPERAND
SELECT

START/wIDTH
FUNNEL
SHIFT
CONTROL

ALU
CONTROL

MERGE
CONTROL

YBUS

FIgure 6. Detailed Block DIagram of the IDT49C404

14-89

A POWERFUL NEW ARCHITECTURE FOR A
32-BIT BIT-SLICE MICROPROCESSOR

APPLICATION NOTE AN-11
block are brought out separately to achieve an orthogonal
Instruction set. This allows the highest degree of performance and
flexibility. The unencoded control lines are especially useful to
designers of RISC-type architectures.

Serial diagnostics capability allows data to be read from, or
inserted to, the seven-port register file. Additionally, various Input
pins and output pins can be observed and some break-point
capability is implemented. Figure 7 lists all of the instruction fields
and their associated opcodes. The control lines of each functional

49C404 Instruction Fields
30 29

2423

1716

[8J N.C. ON 32 BIT SYSTEM
49C404 Instruction Fields Opcodes
Mask Src
Code

Source

Start and Width
0 0
from Instruction
0 1

T & 0 supply
Start and Width

1 0

Tasa
32-Bit Mask

1 1

Oasa
32-Bit Mask

X Source Selection
OEA XSrc X Source
RAM A
0
0
RAMT
0
1
1
RAM A
0
1
DA
1

Y Source Selection

Merge Control
MRG

Function

00
01
10
11

Pass F
Pass V
Merge FN
MergeV/F

'O'm YSrc Y Source
0
0
1
1

Funnel Shift Operations
Code
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11

000
001
010
01 1
100
1 01
110
111
000
001
010
01 1
100
1 01
110
111
000
001
010
01 1
100
101
110
111
000
001
010
01 1
100
1 01
110
111

Function
Shift X and fill with 0
Shift Y and fill with 0
Shift X and fill with M
Shift Y and fill with M
Extract field from
Extract field from
Shift X arithmetic and fill 0
Shift Y arithmetic and fill 0
Shift X arithmetic and fill M
Shift Y arithmetic and fill M
Barrel shift X
Barrel shift Y
Pass X
PassY
Pass all O's
Pass all1's
Shift X and fill with 0, Bypass ALU
Shift Y and fill with 0, Bypass ALU
Shift X and fill with M, Bypass ALU
Shift Y and fill with M, Bypass ALU
Extract field from Y & X, Bypass ALU
Extract field from X & y, Bypass ALU
Shift X arith. and fill 0, Bypass ALU
Shift Y arith. and fill 0, Bypass ALU
Shift X arith. and fill M, Bypass ALU
Shift Y arith. and fill M, Bypass ALU
Barrel shift X, Bypass ALU
Barrel shift y, Bypass ALU
Pass 1's Complement of X
Pass 1's Complement of Y
Pass X and meroe Cin from BitO to SP
Pass X and merge Cin from BitO to SP

0
1
0
1

RAM B
RAM 0
RAM B
DB

S Source Selection
Code

Source

000
o0 1
o10
o1 1
1 0 0
1 0 1
1 1 0
1 1 1

DA
RAM A
RAMO
RAMT
RAM B
DB
Y
MASK
ALU

V Source Selection
Operands

VSEL

Selection

Code

Function

O,X
O,Y
M,X
M,Y
Y,X
X,Y
Sign, X,
Sign, y,
Sign, X,
Sign, Y,
X
Y

000
o 01
01 0
01 1
100
1 01
110
111

DA
A

000
o0 1
o1 0
o1 1
1 0 0
1 0 1
1 1 0
1 1 1

R+S
S-R
R-S
RorS
Rand S
Special Instruction
R exorS
R exnorS

0
0
M
M

X
Y
0
1
O,X
0, Y
M,X
M,Y
Y,X
X,Y
Sign, X, 0
Sign, y, 0
Sign, X M
Sign, y, M
X
Y
X
Y
X
Y

Figure 7. The IDT49C404
Instruction Fields and Opcodes
14-90

0
T
B
DB
O's
1's

Z BUS Control
Code
000
o0 1
o1 0
o1 1
1 0 0
1 o1
1 1 0
1 1 1

Zero
RAM DEST
A
B Test Src
F
DA
F
F
DA
Y
F
F
DB
F
Y
DB
Y
DA
F
DA
Y
Y
F
Y
DB
Y
Y
DB
T Source

Code

Source

00
o1
1 0
1 1

ZBUS
YBUS
T + C1
T + C2

A POWERFUL NEW ARCHITECTURE FOR A
32·81T BIT·SLlCE MICROPROCESSOR

APPLICATION NOTE AN·11

APPLICATIONS:

Consider a graphics application. Conceivably, the dual-port
RAM could contain a link list of data elements containing
three-dimensional point values and transformation instructions
which are composed of 4x4 matrices. The floating-point processor
could be capable of traversing the link list and multiplying each
point with the transformation matrices. This approach could be
used to rotate three-dimensional objects, transform them into
two-dimensional surfaces and perform clipping algorithms forfinal
display on a graphics terminal. Figure 8 compares a possible
display representation and how it might be stored in memory
internally.

Floating-Point Math Accelerator
Modem work stations often use a processor such as the 68020
or 80386 as the main CPU. In many cases, the processing
capability of the CPU is extended with the use of a floating-point
math accelerator. Ifthe floating-point processor is isolated from the
main CPU through the use of a dual-port RAM, higher overall
system per- formance can be achieved because the accelerator
can process in parallel to the main CPU.

THE USER'S VIEW

THE PROCESSOR'S VIEW

Figure 8. Different Views of the Same Cube

14-91

A POWERFUL NEW ARCHITECTURE FOR A
32-BIT BIT-SLICE MICROPROCESSOR

APPLICATION NOTE AN-11

The MICROSLICE family contains a number of well-suited
control devices. As shown In Figure 9, the control section of a
floating-point accelerator can be composed on an IOT49C41 0 that
generates addresses to the writable control store of an 10171681
which, in tum, produces an instruction to be held in a pipeline
register. The contents of the pipeline register are the current
Instructions being executed. Control lines can be fanned out to
instruction lines and control inputs of every device in the
accelerator subsystem.

The floating-point math accelerator consists of a dual-port RAM,
a controller and floating-point ALU and a multiplier. A block of
dual-port RAMs serves as the interface between the global system
bus and the local system bus used by the floating-point processor.
The control section generates sequences of instructions for a
floating-point ALU, as well as address generator indexing into the
dual-port. The performance of the accelerator depends on the
speed at which the controller can generate instructions and on the
bandwidth of the ALU.

A
WCS
24 x IDT71681

Y

LA

Control

LD

IDT7132/42
DUAL PORT
RAM

RA

Control

RD

GLOBAL SYSTEM BUS

Figure 9. Floating-Point Math Accelerator Using the MICROS LICE Family

14-92

\
A POWERFUL NEW ARCHITECTURE FOR A
32·BIT BIT·SLlCE MICROPROCESSOR

APPLICATION NOTE AN·11

Most designers think of the IDT49C402 (and others in its class)
only as an ALU with register flies for data paths. However, It can be
used for a larger variety of tasks. In the accelerator example, it is
used as an address generator. Data for a 4x4 matrix can be stored
in the dual-port memory as a sequential list of 16 values. Any
element can be located by adding the address pointer to the start of
the matrix, the row offset and the column offset. To multiply a matrix
by a vector, a column of matrix elements Is individually multiplied
by the corresponding vector values and the four products are
added together. One way to efficiently generate addresses with the
IDT49C402 is to store the matrix address pointer and vector in the
register file. To begin, the address pointer of the matrix can be
added to a constant corresponding to the column to be operated
on. This operation can be completed in a single cycle by bringing
the constant from the pipeline register through the 0 bus,
addressing the pointer with the A address and storing the result in a
location specified by the B address. In the same cycle, the new
address could be output from the ALU through the Y port and
placed in the MAR register. In this way, the MAR register would
supply the dual-port RAM address on the next cycle, forming a
pipeline mode of operation. On the next three cycles, the new
address in the register file could be incremented and the
respective calculated addresses passed to the MAR.
Consequently, it would require only four cycles to generate four
addresses that correspond to four values in the matrix column. In
addition, this entire process can be performed while the
computation unit attends to other tasks. With proper design,
addresses can be fed into the dual-port RAM and values can be
read into the computation unit on every clock cycle. With the
IDT49C402A, the minimum time from register file address to the Y
output is only 37ns. This Is one of the fastest ways to generate a
complex 16-bit address.
The IDT49C402 can also be used to keep track of linked lists of
complex data structures. The register file is capable of retaining
pointers of various lists, as well as intermediate pointers. The
accelerator described previously requires a pointer to the head of a
list of 'X:'(])N values, an .intermediate pointer to the current 'X:'(])N
value and a pointer to the transformation matrix.
The computation portion of the accelerator is composed of
floating-point devices and local storage elements. The most
efficient way to multiply a series of vectors by a transformation
matrix is to begin by fetching the matrix from the dual-port RAM into
local memory connected to the floating-point chips. The register
file of the IDT49C404 can be used to hold the matrix variables, as
well as intermediate results. This poses no problem since the
IDT49C404 has 64 registers-enough room to store the 4x4 matrix

and any temporary variables. The 32-bit ALU portion of the chip
can then be used to perform fixed-point arithmetic and logic
functions.
The IDT49C404's three-bus architecture allows both output
ports of the register file to come off-chip and drive inputs to the
floating-point devices. Thus, two operands can come from the
IDT49C404 and one from the dual-port RAM addressed by the
lOT49C402 on each clock cycle. The Y bus can be used to put the
results of the floating-point multiplier or ALU back into the register
file.
Once the transformation matrix is stored in the IDT49C404
registers, consecutive 'X:'fZW point values can be brought in from
the dual-port RAM. Consequently, values from the 'X:'(])N vector
and transformation matrix can be delivered to the IDT721265
multiplier on every cycle.

Graphics Accelerator Example
Figure 10 shows the block diagram for a graphics accelerator.
Once again, this scheme uses a dual-port RAM as the communication device between the main processor and the accelerator.
The accelerator is composed of two blocks: a control unit
containing the IDT49C410 sequencer and an image computation
unit which utilizes the IDT49C404 as the main image computing
processor. Both blocks use the lOT49C402 to generate addresses.
In the control unit, the IDT49C402 can be used to generate link
list addresses, as well as indexes into complex data structures. The
IDT49C402 is used in the computation unit to generate addresses
into the video frame buffer. The video frame addresses might be
used for bit block moves or for drawing complex line algorithms.
Within the computation unit, the IDT49C404 is used for
performing mask and merge operations with data in the frame
buffer. The Funnel Shifter rotates and aligns data and the ALU
merge unit takes new data and merges it into old data in the frame
buffer. The three-bus structure ofthe IDT49C404 is very useful. The
DA bus may be used to bring icon and bit pattern data in from the
dual-port memory on the system bus. The DB bus is used to bring
in data from the video frame buffer. These two buses can be
merged together using the Funnel Shifter, ALU and Merge Logic
block to compute output which is the Y bus. The Y bus can then be
used to write the result back Into the frame buffer. Since address
computation and data manipulation are done on separate chips,
read modify writes can be performed very easily by holding the
address steady. Data is read from the frame buffer and then the
buffer write control line is brought low as data is delivered through
the IDT49C404 and back into the frame buffer.

14-93

A POWERFUL NEW ARCHITECTURE FOR A
32·BIT BIT·SLlCE MICROPROCESSOR

APPLICATION NOTE AN·11

VIDEO FRAME BUFFER

IDT7132142
DUAL PORT
RAM

RA

Control

RD

CRT

GLOBAL SYSTEM BUS
Figure 10. Graphics Accelerator Using the MICROSLICE Family

The previous examples of the IDT49C404 are two of many
possible applications. This device is very well-suited for any
operation which requires 1-bit to 32-bit data manipulation on any
type of boundary. Other examples include business automation
projects such as data base manipulation, graphics and special
purpose CPUs. Industrial automation efforts like robotics and
artificial intelligence could benefit from the IDT49C404.
Telecommunications is another fast-paced application segment
where bit field manipulation is of paramount importance,
especially in video control strategies. Peripheral controls for
high-speed communications and disk drives is yet another area
where high-performance bit field processing is very important.

SUMMARY
Integrated Device Technology's 32-bit IDT49C404 cascadable bit-slice microprocessor is the most powerful introduced to
date. It offers technical features which maximize system throughput and performance in a tremendously wide variety of applications. The 64-word-by-32-bit register file represents 2K bits of
total mUlti-port memory. The Funnel ShifVALU/Merge arrangement provides maximum data manipulation in a single clock cycle.
Together with other IDT49COOO devices, the MICROSLICE family
offers a complete set of building blocks for high-performance
system solutions.

14-94

By DANH LE NGOC

INTRODUCTION
This article discusses floating-point in general terms: IEEE
floating-point format, the pipelined architecture of IDT721264/65,
how to perform division-algorithms and several DSP applications
such as FIR, FFT and graphics accelerators.

Floating-Point Versus Fixed-Point
There are three major types of number representations:
decimal, fixed-point and floating-point. The discussion here
concentrates on fixed-point and floating-point. In the fixed-point
data notation, data is represented with a radix point which remains
in a fixed position within the number. The fixed-point data can be
subdivided into two categories: integer number and fractional
number. An integer number represented in the fixed-point notation
has an implied radix pointto the right of the number. The radix point
is to the left of the number in the fixed fractional data
representation. Figure 1 illustrates the two different fixed-point
representations.

o

23 22

30

SIGN

I

EXPONENT

FRACTION

In the single precision format, the floating-point number is
divided into three fields: the sign-bit, an 8-bit exponent and a 23-bit
fraction. The floating point value is determined by the following
table:

E

F

Value

Name

255

Not All Zero

-

NotA Number

NaN

255

All Zeros

(_1)s (Infinity)

Infinity

INF

Normalized
Number

NOR

Denormalized
Number

DNRM

Zero

ZERO

Any

I.

a

NatAli Zeros

RADIX-POINT3

a

Zero

s
E·127
(-1) (1.F)2

s

(-1) (0.F)2

-126

(_1)s 0.0

Mnemonic

- Approximate Maximum positive number: 2 128 = 1.7 X 1038
- Approximate Minimum positive normalized number: 2- 126 = 1.2
X 10-38
.
- Precision: 2-23 = 10-7 (7 decimal places)

FRACTION FORMAT

RADIX-POINT--..1
Figure 1.

NaN
As the table indicates, the exponent values E = 0 and E = 255
are reserved to specify the special numbers in the IEEE format.
When the exponent E equals 255 and the fractional part F is not
zero, the number is called "Not a Number" (NaN). NaN does not
represent a numeric value, but it represents a symbol in the IEEE
format. This special data format is usually used as a flag for data
flow control, for uninitialized variables or to indicate an invalid
operation such as 0 x INFINITY.

Users of fixed-point processors have to maintain the correct
position ofthe radix point at all times, resulting in scaling problems
such as shifting the number in one direction or another to avoid the
overflow or loss of precision. For example, a 32-bit fixed-point
number can represent all integers roughly between -2x109 and
+2x109 -1. An overflow or underflow occurs when a number is
larger or smaller than this range. A fractional number like 4.25 can
be represented as a integer number by scaling down by 0.25. The
scaling process is also referred to as rounding. The scaling or
rounding is normally fixed in the arithmetic operations. Therefore,
the number of data bits of each fixed-point processor determines
the magnitude (range of values) and precision of values (how
accurately a number can be represented). These restrictions can
cause some errors in the digital signal processing computations
which result in a noise-like source in the digital systems.
Floating-point processors handle scaling automatically and
expand the range of values represented by fixed-point processors.
For example, a 32-bit floating-point number in the IEEE format can
represent all numbers from roughly 1.2x1Q-38 to 1.7x1Q38. A
floating-point number consists of two parts: a fraction and an
exponent. The fractional and exponent parts of a floating-point
number can also be referred to as the mantissa and the
characteristic, respectively. The IDT721264/65 chip set supports the ANSI/IEEE standard 754 version 1985 floating-point
notation which consists of two formats: single precision (32-bit)

© 1817 lnIegrllted DevIce Tecllnology, Inc.

31

I I

1-254

INTEGER FORMAT

.1

and double precision (64-bit). These two formats are described
below:
- IEEE standard single precision:

Infinity and Zero
When exponent E =255 and fraction F =0, this number defines
INFINITY. When exponent E = 0 and fraction F = 0, the value is zero
in the IEEE format.

Normalized Number and Denormallzed Number
A floating-point number is called normalized when the
hidden-bit is one. When the hidden-bit of a floating-point number is
zero and the fractional part F is not zero, this number is called a
denormalized number.

Hidden Bit and Biased Exponent
There are two additional significant items In the single precision
floating-point format. The assumed "1" preceding the fraction is
called the hidden bit which increases the precision of the fraction
from 23 bits to 24 bits. The biased exponent representation,
e =E-127, makes all of the exponents larger than zero, simplifying
the hardware logic implementation for the floating-point numbers.
This is illustrated in the two examples below:

14-95

PrInted In the U.S.A.

8/87

m
:4

APPLICATION NOTE AN-12

USING THE IDT721264/65 FLOATING-POINT CHIP SET
Floating-Point Operand 1
Examples:

o 10110111.01000000000000000
sign=

+

E= 183

Floating-Point Operand 2

f1

f2

~

~

F=1.25

1 10110111.1000000000000000

sign= -

E=183

F=1.50

For applications requiring larger precision, the double precision
IEEE format Is preferred:
- IEEE standard double precision:

I

63

SIGN

62

I

o

52 51

I

EXPONENT

Floating-Paint Result
Figure 2. Floating-Point Multiplication Data Flow

FRACTION

The range of values Is defined by the following table:

Floating-Point Operand 1
f1

E

F

Value

Name

2047

Not All Zero

-

NotA Number

NaN

2047

All Zeros

(-1)s (Infinity)

1-2046

Any

s
E·1023
(-1) (1.F)2

0

NatAli Zeros

-1022
s
(-1) (0.F)2

0

Zero

(_1)s 0.0

~

Mnemonic

Infinity

INF

Normalized
Number

NOR

Denormalized
Number

DNRM

Zero

ZERO

Floating-Point Operand 2
12

+

The key differences between the single precision and double
precision are the number of bits for the exponent and the fraction.
In the double precision, the exponent Is eleven bits and the fraction
is fifty-two bits, which provides a larger dynamic range and greater
accuracy.
- Approximate maximum positive number: 2 1024 = 9x10307
- Approximate minimum positive normalized number:
Z-1022 = 2.2x10-308

Exponent Adjust

_. Precision: Z-S2= 10-15 (15 decimal places)
Exponent

Architectural Overview of the lOT Floating-Point
Chip Set
The floating-point hardware Implementation is inherently more
complex than the fixed-point processor. Generally, the floatingpoint arithmetic processor consists of four basic elements:
fixed-point logic to perform the fixed-point operation on the
fraction, fixed-point logic to perform calculation on the exponent
part of the floating-point format, logic to perform the rounding and
format-adjustment to the floating-point formats and logic to detect
and handle the exceptions. Figures 2 and 3 illustrate the data-flows
for the multiplication and addition of two floating-point numbers,
respectively.

Fraction

Floating-Point Result
Figure 3. Floating-Point Addition Data Flow

As the data flow in Figures 2 and 3 demonstrates, performing a
floating-point multiplication or addition will take a longer system
clock-cycle than fixed-point operations. To reduce the long clock
cycle, the pipelined approach is implemented in the IDT floatingpoint chip set.

14-96

. APPUCATION NOTE AN·12

USING THE IDT721264/65 FLOATING·POINT CHIP SET

three-bus devices. There are two dedicated 32-blt Input ports (X
and Y) to load the two operands, and one dedicated output port (Z)
to unload the result of floating-point operations.

The 101721264/65 chip set consists of two devices: a
floating-point multiplier and an AlU (see Figures 4 and 6).
The floating-point multiplier and AlU are archltectured as
FO-5

XO-31

YO-31

Figure 4. IDT721264 Floatlng·Polnt Multiplier

Five bits (l0-4) are used to specify the load operations. The
result can be read on the Z bus under control of the 3-bit U0-2 in
parallel with the 4-bit status S0-3. The 6-bit function controls FO-5
are used to select the opcodes for the floating-point multiplier and
AlU. They are also used to load data into the mode register which
specifies the different operating modes: flowthrough, pipellned,
IEEE standard mode, fast mode and all rounding modes. The
ID1721264 and ID1721265 provide a very flexible input/output
structure which can be easily interfaced with a 16-bit, 32-bit or
64-bit bus. The two input buses X and Y can be configured as two
independent 16-bit or 32-bit buses or as a Single 64-bit bus under
control of two mode-bits: MOOE15, MOOE14. In the 16-bit mode
configuration, when MODE15 is high, two consecutive clocks are
required to load a 32-bit number into the X1 and Y1 registers. In the
single precision mode, the 32-bit operands must be loaded into the
most significant bits of the AREG and BREG because the least
significant 32 bits of the AREG and BREG are filled in with logic
zeros by the hardware. Data on the X and Y buses are loaded into
the X1 and Y1 registers on the low-te-high transition of the clock.

From there the data is moved into the AM, Al, BM, BL, AREG and
BREG registers on the low-te-high transition of the clock signal.
When lO Is high, the two operands stored In the registers AM, AL,
BM, Bl, X1 and Y1, as well as the function-code in F1, are
transferred to the first pipellned stage ofthe floating-point multiplier
or AlU. At the same time, the pipe advance timer and accumulate
timer are also reset to indicate the beginning of a new operation.

(seem

The Internal architecture of the floating-point multiplier
Figure 4) consists of five basic elements: a front end circuit to
detect exceptions, a synchronous multiplier array, a circuit for
handling the exponents, a shifter to normalize the result of the
fixed-point multiplication and IEEE rounding circuitry. The five
basic elements are partitioned Into two plpelining stages. Under
control of two mode bits MODE5/MODE4, the first pipe/second
pipe of the floating-point multiplier can be made transparent.
Making pipeline registers transparent reduces the worst-case
latency of operation, but it also reduces the maximum throughput.
This mode is also called the flowthrough mode.

14-97

~

APPLICATION NOTE AN-12

USING THE IDT721264/65 FLOATING-POINT CHIP SET

the double precision multiplication. Figure 5 Illustrates the intemal
architecture of the fixed-point multiplier array:

A 56-blt-by-28-bit multiplier array Is used to perform the
fixed-point multiplication. One pass Is required to perform the
single precision multiplication. Two passes are required to perform

CP

F0-5

Pass Control by
Hardware
Sing. Pre: bYRass ACC
Double Pre.: One ACC

Figure 5. Multiplier Array of IDT721264

The floating-point ALU also consists of five basic elements: a
front end circuit to detect the exceptions, a shifter to align the two
operands, a 57-bit adder, a shifter to renormalize the results and a
circuit to produce the IEEE format. These five basic elements are
FO-5

partitioned into five pipelined stages. The last four pipeline
registers can be made transparent under control of four mode bits:
MODE7, MODE6, MODE5 and MODE4. Figure 6 illustrates the
simplified block diagram of the IDT721265.
YO-31

CSL -

LO-4

CSU- UO-2

3

ZO-31

Figure 6. IDT721265 Floating-Point ALU

14-98

CLK

USING THE IDT721264/65 FLOATING-POINT CHIP SET

APPLICATION NOTE AN-12

Flowthrough and Pipelining Modes

high. The example below illustrates two typical selections for two
different system clocks:

The IDT floating-point chips are architectured as pipelinlng
devices which are well suited for pipelined signal processing
applications such as FFT, FIR and Matrix multiplications. The
ID1721264 floating-point multiplier consists of two pipeline stages
which can be made transparent under control of two mode bits
(MODES and MODE4) as follows:
MODE5

Examples:
Accumulator
MODE7 &6

IDT721264 System Clock
Single 40ns
Single 80ns

MODE4

Pipeline
MODE11-8

01 -- > SOns

0010 -->
(N=2)

SOns

00 -- > SOns

0001
-->
(N=1)

80ns

Pipe1

STREG & DM, DL

o - > Transparent

o - > Transparent

Double 40ns

01 -- > SOns

0100
--> 160ns
(N=4)

1 - > Register

1 - > Register

Double 80ns

00 -- > 80ns

0010 --> 160ns
(N=2)

In the single precision multiplication, the minimum pipeline
clock is twice the system clock. However, the pipeline clock forthe
double preCision multiplication is four times that of the system
clock. To optimize the throughput in the pipeline mode, the
multiplier also contains two timers: the accumulator advance
control and pipeline advance control. For a given system clock, the
accumulator timer control is used mainly to select the number of
clocks required to perform the 24-bit-by-24-bit or S4-bit-by-S4-bit
fixed-point multiplication under control of the two mode bits
MODE? and MODE6:
MODE7

MODE6

Accumulate Rate

0
0
1
1

0
1
0
1

Clock/1
Clock/2
Clock/3
Clock/4

The table below summarizes the performance of the IDT chip set:
Operation

ID1721264
Multiplier

IDT721265
ALU

Single-Precision
Pipelined-Throughput

80ns

SOns

Single-Precision
Latency

240ns

360ns

Double-Precision
Pipelined-Throughput

160ns

SOns

Double-Precision
Latency

360ns

360ns

Figure 7.IDT Floating-Point Chip Set Performance

Figure 8 shows the timing for the pipelined single precision
multiplication. To achieve the maximum pipelined throughput in
the single precision multiplication, the accumulator advance timer,
pipeline advance timer and pipeline configuration control are
selected as follows:

Under control of the four mode bits MODE11-8, the pipeline
advance timer controls when the pipeline registers are clocked
after the start of an operation. If all zeros are loaded into M 11-8, the
pipeline registers are latched only at the beginning of an operation.
When M11-8 are loaded with a non-zero value N, the pipeline
registers are clocked at the beginning of every operation and N
clock cycles after the beginning of every operation. Both the
accumulator advance timer and pipeline advance timer are reset at
the beginning of each operation, namely every time the bit LO is

Clock

MODE5

MODE4

40ns

1

1

CLK+
X/Y Opr 1---4--<

L+, CSL

F+
U+, CSU

Z Result

r--+---r-~---~--4---~~f

t---+--I---t---\---+---4---i---4---<

Figure 8. Pipelined Single Precision MultiplyTiming for IDT721264

14-99

Accumulator
MODE7-6
01 -> 80ns

Pipeline
MODE11-8
0010 -> SOns
(N=2)

APPLICATION NOTE AN-12

USING THE IDT121264/65 FLOATING-POINT CHIP SET

On the low-te-hlgh transition of clock #3, the operands as well as
the function are loaded Into the AR, BR and F registers. In the next
clock cycle (#4) the operation Is started. It takes two clock cycles to
finish the partial product of the 24-bit-by-24-bit multiplication. Then
the partial product Is loaded into pipe1 .. On the next two clock
cycles (#Sand'7), the final result of the multiplication is generated
and pipelined into the last pipe. On the low-te-hlgh transition of
clock #8, the unload-opcode can be loaded. The result, as well as
status, can be read on clock #1 0 and remains for two clock cycles
(pipeline clock). The TLATENCY specifies the Initial total latency of
the plpelined mode. After the pipe Is full, the result can be read on
the Z bus every two system clock cycles.
Figure 9 shows the timing for the pipeline double precision
multiplication. In this mode, four clock cycles are required to
perform the fixed-point multiplication. Therefore, the accumulator

timer Is set to clock/2 (two clock cycles) and the plpelined advance
control Is set to clock/4 which provides two passes required for the
accumulations. To maximize the throughput, the OM and OL
registers are made transparent, since the last pipe requires only
two clock cycles (see table belOW).
Clock

MODE5

MODE4

40ns

0

0

MODE7-6
01 -> SOns

Pipeline
MODE11-8
0100 _> 160ns
(N=4)

Similar to pipellned single precision multiplication, the result
and status can be read on the Z bus and S0-3 lines every four
system clock cycles after the first initial pipeline delay is filled In.

~------Top------~

CLK+

X/Y Opr
L+, CSL-

F+

Z Result

Accumulator

I---+---If---+---+--+-~-+--+---+---If----+----{:

(DM. DL Transparent)
Figure 9. Plpellned Double Precision for IDT121264

14-100

APPLICATION NOTE AN-12

USING THE IDT721264/65 FLOATING-POINT CHIP SET

ID1721265 ALU has only the pipeline advance control. The
pipeline clock for the ALU operation is twice the system clock for
both the single and double precision operations.

Likewise, the floating-point ALU consists of four pipeline stages
which can be made transparent under control of the four mode bits:
MODE7, MODE6, MODES and MODE4 (see Figure 10). The
MODE7
Pipe1

MODE4
STREG & DM, DL

MODE5
Pipe3

MODE6
Pipe2

o - > Transparent

o - > Transparent

o - > Transparent

o - > Transparent

1 - > Register

1 - > Register

1 - > Register

1 - > Register

Figure 10. Pipeline Configuration for IDT721265

The ID1721265 ALU has the same throughput for the single and
double precision operations. The pipeline clock must be twice the
system clock. Therefore the pipeline advance control is set to two
and all the pipelined stages are enabled (see Figure 11).

Clock

MODE7

MODE6

MODE5

MODE4

40ns

1

1

1

1

CLK+
XNOpr

L+,CSL
F+

s+
Z Result

I----+----I--+_--+---+_--+---+---+----I~-+_-_+--+_-f

Figure 11. Plpellned Single and Double Precision ALU for IDT721265

14-101

Pipeline
MODE11-8
2

-> 80ns

APPLICATION NOTE AN-12

USING THE IDT721264/65 FLOATING-POINT CHIP SET

For applications requiring a single clock execution time, such
as In a general purpose computer, the pipelining stage can be
made transparent to reduce the total latency using the four mode
bits: MODE4, MODES, MODE6 and MODE7.
In the flowthrough mode for single preciSion multiplication
(Figure 12), the accumulative control is set to one, pipeline control
is set to zero and the pipeline1 and DM, DL registers are made

transparent In order to achieve the minimum total latency (see
table belOW).
MODE5

MODE4

Accumulator
MODE7-6

MODEll-8

40ns

0

0

01 -> SOns

0000

CLK+
XIV Opr

1-----1--(::

L+, CSL-

I---t--{:

F + 1-----1--<,
U+,CSU-r---~---r---;----r---~~[

s+

r---~---+----r---~---+----~---r<.

Z Result

r---~---+----r----+----+----~---H

~---------T~rrNCY----------~
Figure 12. Flowthrough Single Precision Multiply for IDT721264

14-102

Pipeline

Clock

\

\

APPLICATION NOTE AN-12

USING THE IDT721264/65 FLOATING-POINT CHIP SET

In the flowthrough mode for the double precision multiplication
(Figure 13), the accumulator timer is set to clock/2, because two
clock cycles are required to perform the partial product for each
pass. To minimize the total latency, the pipeline advance control is
set to zero and the OM, OL registers are made transparent.

Clock

MODE5

MODE4

40ns

0

0

Accumulator
MODE7-6

Pipeline
MODE11-8

-> BOns

0000 (N=O)

01

CLK+
XIY Opr

1---4_--{::

L+, CSL-

t----t---<::

F+
U+,CSU-I---~---r--~----~--~---r--~----~

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