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Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
microcomputers. Whether used as microcontrol/ers in automobiles or microwave
ovens, or as personal computers or supercomputers, Intel's microcomputers
have always offered leading-edge technology. In the second half of the 1980s, Intel
architectures have held at least a 75% market share of microprocessors at 16 bits and above.
Intel continues to strive for the highest standards in memory, microcomputer components,
modules, and systems to give its customers the best possible competitive advantages.

EMBEDDED CONTROLLER
HANDBOOK

1988

Intel Corporation makes .no warranty. for .the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
herein.
'
.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH,
GENIUS, i, t, ICE, iCEL, iCS, iDBP, iDIS, 121CE, iLBX, im, iMDDX, iMMX,
Inboard, Insite, Intel, intel, intelBOS, Intel Certified, Intelevision,
inteligent Identifier, inteligent Programming, Inte"ec, Intellink, iOSP,
iPDS, iPSC, iRMK, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, Library
Manager, MAP-NET, MCS, Megachassis, MICROMAINFRAME,
MULTIBUS, MULTICHANNEL, MULTIMODULE, MultiSERVER, ONCE,
OpenNET, OTP, PC-BUBBLE, Plug-A-Bubble, PROMPT, Promware,
QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80, RUPI,
Seamless, SLD, SugarCube, SupportNET, UPI, and VLSiCEL, and the
combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a
numerical suffix, 4-SITE.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered
trademark of Mohawk Data Sciences Corporation.
*MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature D.istribution
Mail Stop SC6-59
3065 Bowers Avenue
Santa Clara, CA 95051
@ INTEL CORPORATION 1987

Table of Contents
Alphanumeric Index .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii
xiii

8·BIT PRODUCTS
MCS®·48 FAMILY
Chapter 1
MCS®-48 Single Component System ........................................

1-1

Chapter 2
MCS®-48 Expanded System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

Chapter 3
MCS®-48 Instruction Set.. . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .

3-1

Chapter 4
DATA SHEETS
8243 MCS®~48InputlOutput Expander. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .
P87 48H/P87 49H/8048AH/8035AH L/8049AH/8039AHLl8050AH/8040AHL
HMOS Single-Component 8-Bit Production Microcontroller ........ . . . . . . . . . . .
D8748H/8749H HMOS-E Single-Component 8-Bit Microcomputer. . . . . .. . .. . . . . .
MCS®-48 Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCS®-48 INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1
4-8
4-21
4-33
4-36

MCS®·51 FAMILY
Chapter 5
MCS®-51 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . .. . .. . .. . . . . .

5-1

Chapter 6
Hardware Description of the 8051,8052 and 80C51 ...........................

6-1

Chapter 7
Hardware Description of the 83C51 FA (83C252) ............................. ;

7-1

Chapter 8
Hardware Description of the 83C152 .................................. ; . . . . . .

8-1

Chapter 9
MCS®-51 Programmer's Guide and Instruction Set. .. . . . . .. . . . .. . . . . . . . . . . . . . .

9-1.

Chapter 10
DATA SHEETS
8031/8051 /8031AH/8051AH/8032AH/8052AH/8751 H/8751 H-8 8-Bit HMOS
and HMOS EPROM Microcontrollers.......................................
8051 AHP 8-Bit Control-Oriented Microcontroller with Protected ROM .. . . . . . . . . ..
8031 AH/8051AH/8032AH/8052AH/8751 H/8751 H~8 Express. . . . . . . . . . .. . . .. ..
8751 BH 8-Bit HMOS EPROM Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8032BH/8052BH 8-Bit HMOS Microcontrollers .............................. ;
8752BH 8-Bit HMOS EPROM Microcontroller.................................
80C31 BH/80C51 BH 8-Bit CHMOS Microcontrollers ...........................
80C31 BH/80C51 BH Express ................. : .............................
87C51 8-Bit CHMOS EPROM Microcontroller.................................
87C51 Express ...........................................................
87C51 FA (87C252) CHMOS Single-Chip 8-Bit Microcontroller . . . . . . . . . . . . . . . . . •.
83C152A180C152A Universal Communications Controller ....... '............ ; ..
80C152JAl83C152JAl80C152JB Universal Communications Controller .........
27C64/87C64 64K (8K x 8) CHMOS Production and UV Erasable PROMs ........
87C257 256K'(32K x 8) CHMOS UV Erasable PROM ..........................
UPITM-452 CHMOS Programmable I/O Processor .............................
APPLICATION NOTES
AP-70 Using the Intel MCS®-51 Boolean Processing Capabilities ................
AP-125 Designing Microcontroller Systems for Electrically Noisy Environments ....
AP-155 Oscillators for Microcontrollers .......................................
v

10-1
10-15
10-25
10-27
10-38
10-46
10-57
10-69
10-71
10-84
10-87
10-102
10-117
10-133
10-146
10-157
10-211
10-256
10-278

Table of Contents (Continued)
AP-252 Designing with the 80C51 BH ........................................ 10-310
AP-281 UPITM-452 Accelerates iAPX 286 Bus Performance ........•............ 10-334
ARTICLE REPRINTS
AR-409 Increased Functions in Chip Result in Lighter, Less Costly Portable
Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-354
AR-517 Using the 8051 Microcontroller with Resonant Transducers ............. 10-359
DEVELOPMENT SUPPORT TOOLS
8051 Software Packages. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . • . . . . 10-364
iDCX 51 Distributed Control Executive ....................................... 10-372
ICETM 5100/252 In-Circuit Emulator for the MCS@-51 Family ................... 10-380
MCS@-51 INDEX ................................................... ; ........ 10-390
80C152 INDEX .................................•............................ 10-392

THE RUPITM FAMILY
Chapter 11
The RUPITM-44 Family.....................................................

11-1

Chapter 12
8044 Architecture ........................................... , . . . . . . . . . . . . .

12-1

Chapter 13
8044 Serial Interface ......................................................

13-1

Chapter 14
8044 Application Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-1

Chapter 15
DATA SHEET
8044AH/8344AH/8744H High Performance 8-Bit Microcontrollerwith On-Chip
15-1
Serial Communication Controller..........................................
APPLICATION NOTE
AP-283 Flexibility in Frame Size with the 8044. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-27
ARTICLE REPRINT
AR-307 Microcontroller with Integrated High Performance Communications
Interface .........................'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-57
.
DEVELOPMENT SUPPORT TOOLS
ICETM51 00/044 In-Circuit Emulator for the RUPITM-44 Family. . . . . . . . . . . . . . . . . .. 15-66

MCS®-80/85 FAMILY
. Chapter 16
DATA SHEETS
8080A/8080A-1 /80BOA-2 8-Bit N-Channel Microprocessor. . . . . . . . . . . . .. . . . . . . .
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . . . . . . . . . . . . . . . ..
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and
Timer. .. . . . . .. .. .. . . . .. . . .. .. . .. . . . . .. . . . .. . . . . . .. . . . .• . . . . . . . . . . .. ....
8185/8185-21024 x 8-Bit Static RAM for MCS@-85. ... . .. . . . .. . . . . .•. .. . .. ....
8224 Clock Generator and Driver for 8080A CPU ........... ~ ............. '. . . ..
8228 System Controller and Bus Driver for 8080A CPU. . . . . . . . . . . . . . . . . . . . . . . ..
8755A 16,384-Bit EPROM with I/O..........................................

16-1
16-11
16-31
16-45
16-50
16-55
16-59

16-BIT PRODUCTS
MCS®-96 FAMILY
Chapter 17
MCS@-96 Architectural Overview. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 18

17-1

,

MCS@-96InstructionSet...................................................

18-1

Chapter 19
MCS@-96 Hardware Design Information. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .

vi

19-1

Table of Contents (Continued)
Chapter 20
80C196KA Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20-1

Chapter 21
DATA SHEETS
809XBH/839XBH/879XBH with 8 or 16-Bit External Bus.......................
21-1
809XBH-10 Advanced 16-Bit Microcontroller with 8 or 16-Bit External Bus . . . . . . .. 21-44
809X-90, 839X-90 . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . .. 21-59
809XBH/839XBH/879XBH Express......................................... 21-78
809X-90, 839X-90 Express. . . . . . . . . . . . . . . . . . . .. . . .. .. .. . ... . . . . . . . . . . . . . . .. 21-87
80C196KA 16-Bit High Performance.CHMOS Microcontroller ................... 21-92
APPLICATION NOTES .
AP-248 Using the 8096 .................................................... 21-119
AP-275 An FFT Algorithm for MCS®-96 Products Including Supporting Routines
and Examples· .......................................................... 21-222
DEVELOPMENT SUPPORT TOOLS
MCS®-96 Software Development Packages .................................. 21-297
iDCX 96 Distributed Control Executive ....................................... 21-307
iSBE-96 Development Kit Single Board Emulator and Assembler for MCS®-96 .... 21-315
VLSICETM-96 In-Circuit Emulator for the MCS®-96 ............................. 21-323
ICETM-196 Real-Time Transparent 80C196 In-Circuit Emulator .................. 21-333
!'v1CS®-96 INDEX ............................................................ 21-335
80C196 INDEX ............................................................... 21-341

80186 FAMILY
Chapter 22
DATA SHEETS
80186 High Integration 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80C186 High Integration 16TBit Microprocessor . . . . . . . .. . . . . . . . . . . . . . . . . . . . . ..
80188 High Integration 16-Bit Microprocessor .................................
80C188 High Integration 16-Bit Microprocessor ...............................
82188 Integrated Bus Controller for 8086, 8088, 80186, 80188 Processors .......
APPLICATION NOTES
AP-186 Introduction to the 80186 Microprocessor .............................
AP-258 High Speed Numerics with the 80186,80188 and 8087 .................
AP-286 80186/188 Interface to Intel Microcontrollers ..........................
DEVELOPMENT SUPPORT TOOLS
8086/80186 Software Packages ............................................
VAXIVMS Resident 8086/8088/80186 Software Development Packages ........
8087 Support Library ......................................................
80287 Support Library .....................................................
iPAT Performance Analysis Tool ............................................
12 1CETM Integrated Instrumentation and In-Circuit Emulation System .............
ICETM-186 In-Circuit Emulator ..............................................

vii

22-1
22-53
22-111
22-165
22-225
22-241
22-316
22-332
22-362
22-383
22-391
22-395
22-399
22-412
22-424

Alphanumeric Index
27C64/87C64 64K (8K x 8) CHMOS Production and UV Erasable PROMs ............... 10-133
80C152JAl83C152JAl80C152JB Universal Communications Controller ............ , ... 10-117
80C186 High Integration 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 22-53
80C188 High Integration 16-Bit Microprocessor ...................................... 22-165
80C196KA Architectural Overview ................................................. 20-1
80C196KA 16-Bit High Performance CHMOS MiGrocontrolier . . . . . . . . . . . . . . . . . . . . . . . . .. 21-92
80C31 BH/80C51 BH Express ...................................................... 10-69
80C31 BH/80C51 BH 8-Bit CHMOS Microcontrollers . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 10-57
22-1
80186 High Integration 16-Bit Microprocessor.......................................
80188 High Integration 16-Bit Microprocessor ....................................... 22-111
80287 Support Library ..................... '....................................... 22-395
8031/8051 /8031AH/8051AH/S032AH/8052AH/8751 H/8751 H-8 8-Bit HMOS and HMOS
1O~ 1
EPROM Microcontrollers ...................................... '. . . . . . . .. . . . . . . . . .
8031 AH/8051 AH/8032AH/8052AH/8751 H/8751 H-8 Express .... . . . . . . . . . . . . . . . . . . .. 10-25
8032BH/8052BH 8-Bit HMOS Microcontrollers ....................... : . . . . . . . . . . . . .. 10-38
8044 Application Examples ...................................... ,................
14-1
8044 Architecture. ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-1
8044 Serial Interface ............................ ~ . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-1
8044AH/8344AH/8744H High Performance 8-Bit Microcontroller with On-Chip Serial
Communication Controller ...................................................... 15-1
8051 Software Packages ............ '............................................. 10-364
8051 AHP 8-Bit Control-Oriented Microcontroller with Protected ROM. . . . . . . . . . . . . . . . . .. 10-15
8080Al8080A-1 /8080A-2 8-Bit N-Channel Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . . . . . . . . . . . . . . . . . . . . . . .. 16-11
8086/80186 Software Packages .................................................. ; 22-362
8087 Support Library ................... '.......................................... 22-391
809X-90, 839X-90 ...................................... ;........................ 21-59
809X-90, 839X-90 Express ...... : ...... ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21-87
809XBH-10 Advanced 16-Bit Microcontroller with 8 or 16-Bit External Bus. . . . . . . .. . . . ... 21-44
809XBH/839XBH/879XBH with 8 or 16-Bit External Bus.............................. 21-1
809XBH/839XBH/879XBH Express ................................................ 21-78
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer.. 16-31
8185/8185-2 1024 x 8-Bit Static RAM for MCS®-85 ........ . . . . . . . . . . . . . . . . . . . . . . . . .. 16-45
82188 Integrated Bus Controller for 8086,8088,80186,80188 Processors .............. 22-225
8224 Clock Generator and Driver for 8080A CPU. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ... 16-50
8228 System Controller and Bus Driver for 8080A CPU ............................... 16-55
4-1
8243 MCS®-48 Input/Output Expander. .. . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .
83C152A180C152A Universal Communications Controller ............................ 10-102
87C257 256K (32K x 8) CHMOS UV Erasable PROM ................................. 10-146
87C51 Express .. ; .....................................................'. . ..... . . . .. 10-84
87C51 8-Bit CHMOS EPROM Microcontroller ..................................... ,.. 10-71
87C51 FA (87C252) CHMOS Single-Chip 8-Bit Microcontroller ......................... 10-87
8751 BH 8-Bit HMOS EPROM Microc~mtroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-27
8752BH 8-Bit HMOS EPROM Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-46
8755A 16,384-Bit EPROM with I/O. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16-59
AP-275 An FFT Algorithm for MCS®-96 Products Including Supporting Routines and
Examples ...................... -......' ................................ '......... 21-222
AP-125 Designing Microcontroller Systems for Electrically Noisy Environments .......... 10-256
AP-155 Oscillators for Microcontrollers .......................................... , .. 10-278
AP-186 Introduction to the 80186 Microprocessor ................................... 22-241
AP-248 Using the 8096 ........................................................... 21-119
AP-252 Designing with the 80C51 BH ............................................... 10-310
AP-258 High Speed Numerics with the 80186, 80188 and 8087 ........................ 22-316
AP-281 UPITM-452 Accelerates iAPX 286 Bus Performance ........................... 10-334
viii

Alphanumeric Index (Continued)
AP-283 Flexibility in Frame Size with the 8044 ....................................... 15-27
AP-286 80186/188 Interface to Intel Microcontrollers ................................. 22-332
AP-70 Using the Intel MCS®"51 Boolean Processing Capabilities ....................... 10-211
AR-409 Increased Functions in Chip Result in Lighter, Less Costly Portable Computer .... 10-354
AR-307 Microcontroller with Integrated High Performance Communications Interface. . . .. 15-57
AR-517 Using the 8051 Microcontroller with Resonant Transducers .................... 10-359
D8748H/8749H HMOS-E Single-Component 8-Bit Microcomputer. . . . . . . . . . . . . . . . . . . . .
4-21
Hardware Description of the 8051, 8052 and 80C51 ..................................
6-1
Hardware Description of the 83C152 ...............................................
8-1
Hardware Description of the 83C51 FA (83C252) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
7-1
12 1CETM Integrated Instrumentation and In-Circuit Emulation System .................... 22-412
iDCX 51 Distributed Control Executive .............................................. 10-372
iDCX 96 Distributed Control Executive .............................................. 21-307
iPAT Performance Analysis Tool ................................................... 22-399
iSBE-96 Development Kit Single Board Emulator and Assembler for MCS®-96 ........... 21-315
ICETM 5100/252 In-Circuit Emulator for the MCS®-51 Family .......................... 10-380
ICETM-186 In-Circuit Emulator ..................................................... 22-424
ICErM-196 Real-Time Transparent 80C196 In-Circuit Emulator ......................... 21-333
ICETM51 001044 In-Circuit Emulator for the RUPITM-44 Family ......................... 15-66
MCS®-48 Expanded System ......................................................
2-1
MCS®-48 Express ........................ , ..... ,., .. , ........ , ............. ,.....
4-33
MCS®-48 Instruction Set",·,',.".,"", .. " .. " .. ,',.,",." .. ,',.".,.,',., ... ,.
3-1
MCS®-48 Single Component System .. , ........ , .. , .. , . , ... , ..... , , . , .. , , . . . . . . . . . .
1-1
MCS®-51 Architectural Overview"" ... " .. " .. ,' .. ",.,", ...... ,"',.,." .. ,.....
5-1
MCS®-96 Architectural Overview ., .. , ... " .. , .. , .... ,., .. "." .. " ... ,., .. "......
17-1
MCS®-96 Hardware Design Information",.", .. ,"",., ..... ".,", .. ".,., ... , •. ,'
19-1
MCS®-96 Instruction Set. .... , ... ,.,..............................................
18-1
MCS®-96 Software Development Packages, .... , ... , .... , ... , ... , ............ , ..... 21-297
P8748H/P87 49H/8048AH/8035AHL/8049AH/8039AHLl8050AH/8040AHL HMOS
Single-Component 8-Bit Production Microcontroller ,."', ... , ....... , ... ,, ...... ,..
4-8
The RUPITM-44 Family , .... , .. " ... ,.,"""""',.,',.,.,',.,"',.,', .. ".,"'"
11-1
UPITM-452 CHMOS Programmable I/O Processor .. , ......... , .. , , •.. , ... , ........ , .. 10-157
VAXIVMS Resident 8086/8088/80186 Software Development Packages, ........... , , . 22-383
VLSICETM-96 In-Circuit Emulator for the MCS®-96 " " " " " , .. , , .. , . , , , . , . , ..... , ... 21-323

ix

CUSTOMER SUPPORT
CUSTOMER SUPPORT
Customer Support is Intel's complete support service that provides Intel customers with hardware support, software
support, customer training, and consulting services. For more information contact your local sales offices.·
After a customer purchases any system hardware or software product, service and support become major factors in
determining whether that product will continue to meet a customer's expectations. Such support requires an international support organization and a breadth of programs to meet a variety of customer needs. As you might expect,
Intel's customer support is quite extensive. It includes factory repair services and worldwide field service offices
providing hardware repair services, software support services, customer training classes, and consulting services. .

HARDWARE SUPPORT SERVICES
Intel is committed to providing an international service support package through a wide variety of service offerings
available from Intel Hardware Support.

SOFrWARE SUPPORT SERVICES
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information
Phone Service), updates and subscription service (product-specific troubleshooting guides and COMMENTS Magazine). Basic support includes updates and the subscription service. Contracts are sold in environments which represent product groupings (i.e., iRMX environment).

CONSULTING SERVICES
Intel provideS field systems engineering services for any phase of your development or support effort. You can use
our systems engineers in a variety of ways ranging from assistance in using a new product, developing an application,
personalizing training, and customizing or tailoring an Intel product to providing technical and management consulting. Systems Engineers are well versed in technical areas such as microcommunications, real-time applications,
embedded microcontrollers, and network services. You know your application needs; we know our products. Workingtogether we can help you get a successful product to market in the least possible time.

CUSTOMER TRAINING
,
Intel offers a wide rimge of instructional programs covering various aspects of system design and implementation. In
just three to ten days a limited number of individuals learn more in a single workshop than in weeks of self-study.
For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we can take our
.workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course categories include:
architecture and assembly language, programming and operating systems, bitbus and LAN applications.

x

Preface

PREFACE
Computer systems can be characterized as being. "reprogrammable" or "embedded". Reprogrammable systems are those that look and behave like computers to
the ultimate user. An obvious example is the personal
computer. These systems contain some form of mass
storage device which stores a number o( different computer programs that the user may call up and use as
required. The input and output devices attached to
these systems are there to communicate with the user.
Embedded systems, as the name implies, are contained
within a final product which inay not look or feel like a
computer to the end user. An example here is a computer which controls the ubiquitous office copier machine. These systems rarely contain mass storage; the
programs are stored in ROM or EPROM devices. The
input and output devices attached are not limited to
communication with the user (e.g. the control panel);
they also monitor and control mechanisms and processes within the device (e.g. the paper feed mechanism).

data storage onboard. The maximum program size is
4 Kbytes.
.
MCS@-51: Designed for advanced 8-bit sequential control applications. These parts are similar to the
MCS@-48 family parts but operate from 2 to 5 times
faster and include more on-board peripherals. A unique
feature of the MCS@-51 family is a built in Boolean
processor which performs calculations on Boolean (one
bit) variables. The maximum program size is
64 Kbytes.
.
MCS@-96: Designed for advanced 16-bit closed loop
control applications. These parts include a processor
capable of high performance integer arithmetic and 232
bytes of general purpose registers which can be used for
byte, word, or double-word operands. A separate subsystem manages timer functions. Versions are available
with on-board A/D conversion and 8 Kbytes of onboard program memory. A unique feature of the newer
(BH) members of the family is dynamic bus sizing
which allows the parts to operate on both 8-bit and 16bit busses. The maximum program size is 64 Kbytes.

Embedded control applications can be broken into
three broad categories; sequential control, closed loop
control, and data control. Sequential control deals with
the control and monitoring of a system as a sequence of
events; activate the paper feed roller, wait for the paper
feed indicator then activate the drum mechanism.
Closed loop control involves closely monitoring the
output of process or device and altering its inputs to
achieve the desired output; if the feed roller motor is
turning too slowly or is decelerating then increase the
drive to the motor to compensate. These two categories
involve fixed programs that interface directly with the
,outside world. The data structures involved are normally small and simple. The third category of embedded
control (data control) still runs fixed programs but the
interface to the outside word becomes more indirect
and the data structures become larger and more complex. A high end copier might digitize an image and
then use image processing techniques to enhance contrast and then scale and rotate the image to fit the paper being used.

80186/80188: These parts are highly integrated versions of the 8086 microprocessor intended for data control applications. They combine 15 to 20 of the most
common 8086.system components onto one device. Included with the CPU is the clock generator, an interrupt controller; timers, DMA channels and chip. select
logic. The 80186 operates on a 16-bit bus and the 80188
operates on an 8-bit bus. Both parts operate on a 16-bit
bus internally.
.
.
Part of the motivation for combining all of these products into one handbook was the realization that,
although the categorization of embedded control applications into the three segments (sequential, closed loop,
and data control) is useful for conceptualizing application requirements, real applications of these parts
contain attributes from all three categories. Combining
these product lines into one handbook will make it easier for customers involved with embedded applications
to find the information they require.

Intel has consolidated four of its product families intended for embedded control applications into the Embedded Control Operation.

The remainder of this chapter will give a very brief
overview of each of the four products discussed. The
remainder of this book is intended to provide detailed
technical information on Intel's embedded control
product line.

MCS@-48: Designed for general purpose 8-bit sequential control applications. Versions of these parts are
available with program storage and up to 256 bytes of

xiii

intJ

PREFACE

MCS®-48 MICROCONTROLLERS

MCS®-S1 MICROCONTROLLERS

Intel's MCS-48 family of 8-bit microcontrollers has become a world standard and has been in production for
10 years. They are available in several versions: with on
board ROM, on board EPROM, or CPU only, to better
fit specific application needs. MCS-48 products are now
fabricated. on advanced HMOS processes offering higher performance and reliability with less power consumption.

Intel's MCS-5l family is the Industry standard for 8-bit
high performancemicrocontrollers. The -family architecture is optimized for sequential real-time control applications. They are available in several versions -with
on-board ROM, on-board EPROM, l!lld CPU only to
better -fit specific application needs. MCS-51- products
are available on adv~riced HMOS and CHMOS processes.

Features common to all members of this family are:
• 8-bit CPU with 1.36 microsecond instruction cycle

Features common to all members of this family are:
• 8-bit CPU optimized for control applications
• ,Extensive Boolean processing (single-bit logic) capabilities
• 32 bidirectional and individually addressable I/O
lines
-

•
•
•
•
•
•

27 I/O lines
8-bit bit timer/counter
2 interrupts
4 Kbyte maximum program size
256 byte maximum on-board RAM size
256 -byte maximum off-board RAM size

• Fuil-Duplex UART
• 5 source interrupt structure with 2 priority levels (6
sources on parts with 3 timer/counters)
• 64 Kbyte maximum program size
• 256 byte maximum on-board RAM size
• 64 Kbyte maximum off-board RAM size
• Po~er gown/Idle modes forCHMOS parts

Intel has over ten years of experience in manufacturing
both the EPROM and ROM versions of this chip. It
provides a low cost solution to applications such as keyboards, low end printers, and electronic carburator control.
Table 1. MCS®·48 Microcontrollers

Device
Name

ROMless
Version

EPROM
Version

ROM
Bytes

RAM
Bytes

8048AH

8035AHL

8748H

1K

_64

8049AH

8039AHL

8749H

2K

128

8050AH

8040AHL

-

4K

256

270253-1

Figure 1. MCS®·48 Block Diagram

xiv

inter

PREFACE

The MCS-51 family has found wide acceptance
throughout a wide range of applications, ranging from
those slightly more complex than a typical MCS-48 application through medical instrumentation and antiskid braking modules for automobiles.

capability. The 80C51FA contains, in addition to the
standard timer counters, a programmable counter array
(PCA) capable of measuring and generating pulse information on five I/O pins.

This year Intel added two new base products to the
MCS-51 family, the 80C152 and the 80C51FA. The
80C152 contains, in addition to a UART, a Global
Serial Channel capable of CSMA/CD and SDLC synchronous communication. It also has two DMA channels, the first member of the MCS-51 to have such

MSC®-51 FAMILY DEVELOPMENT
TOOLS
ICETM-5100 emulators give design engineers fullspeed, real-time, nonintrusive control over 8051 family
system debugging at clock speeds up to 16 MHz. Each

Table 2. Advanced 8-Bit Microcontrollers
Device
Name

ROMless
Version

EPROM
Version

ROM
Bytes

RAM
Bytes

16-Bit
Timers

Circuit
Type

B051

B031

(B751)

4K

12B

2

HMOS

B051AH

B031AH

B751H

4K

12B

2

HMOS

B052AH

B032AH

B752BH

BK

256

3

HMOS

4K

.128

2

CHMOS

BK

256

2

CHMOS

256

4

CHMOS

BOC51BH

BOC31BH

83C152

80C152

83C51FA

80C51FA

B7C51

87C51FA

8K

i -- -----.

,,
,,
,,
,,

,,,
,,
,,
,

EXTERNAL
INTERRUPTS

,-------.

8K ROM
IN 8052 ;--_ • • • • • ,

,,

4K
ROM

TIMER 2

'

I

'

'

256 RAM
IN 8052

:~:::)1 ,~- --]

P2

Pl

COUNTER
INPUTS'

TXD
PO

I

RXD

P3

ADDRESS/DATA
270253-2

Figure 2. Block Diagram of the 8051/8052AH

intJ

PREFACE

Features common to all members of this family are:

emulator lets the user view and modify system activity
at a symbolic, high-level language' level, speeding and
simplifying the development and debug phases of microcontroller system design, All of the ICE-5100 emulators can be hosted on IBM PC Ars or compatibles,
or Intellec® Series III/IV development systems. Three
versions of ICE-5tOO are available today. ICE-5100252 supports HMOS and CHMOS versions of the following components: 8031, 8051, 8751, 8032, 8052,
8752, 80C31, 80C51, 87C51, 83C51FA, 80C51FA, and
87C51FA. ICE-5100/452 supports: 80C452, 83C452,
87C452. The ICE 5100/044 supports: 8344, 8044, 8744,
and BITBUSTM components.

• 16-bit timer (Timerl)
• 16-bit counter (Timer2)
• Full-Duplex UART with independent baud-rate
generator
• Watchdog timer
• 8-bit resolution Pulse Width Modulator (PWM)
• 48 I/O lines (33 for 48-pin parts)
'. HSIO unit
The HSIO (High Speed Input/Output) unit is an independent timer subsystem which manages Timer1 and
Timer2 for the programmer. Events (e.g. setting an I/O
pin) can be scheduled to occur automatically when either of the two timers reaches a preset value. External
events can be recorded in a FIFO along with the value
of Timerl when the event occurred. The HSIO is connected to eight pins on the 8096 and can generate and
monitor events with a 2 microsecond resolution (12
MHz crystal).

Available for the 51 family, ASM-51 and PL/M-51
both contain a relocation and linkage utility and are
available for the IBM PC and Intel Microcomputer Development Systems running either iNDX or ISIS operating systems.
This complete, integrated design-in solution for the
MCS-51 family of microcontrollers speeds product development, and improves design team productivity.

In addition to an EPROM version, the 8X9XBH offer
several improvements over the non BH parts:
• Dynamic selection of 8-/16-bit bus operation (versus
fixed 16-bit bus)

MCS®-96 MICROCONTROLLERS
The MCS-96 Family of microcontrollers was designed
for applications which combine high performance 16bit fixed-point arithmetic with an immediate interface
to real world devices and events. The architecture is
based on a single 64 Kbyte address space. In addition to
. being accessable as memory, the first 256 bytes of this
space are also' directly addressable as registers. These
locations are on-chip for high performance and can be
treated as byte, word, or double-word, operands by the
programme!'. Twenty-four bytes of these registers are
used to control the on-board peripherals; the remaining
232 bytes are usuable by the programmer as general
purpose registers. The combination of a register file, onboard I/O, and a high performance 16-bit CPU .makes
the MCS-96 family well matched to closed loop control
applications.

• Programmable READY logic
• Sample and Hold input to the AID converter
During 1987 Intel added a new series to the MCS-96
family, the 80C196KA. This part is implemented on a
high performance CMOS process and offers significantly more performance and reduced power levels. The
design also includes many detail improvements while
sti11 retaining compatibility with the NMOS versions of
the MCS-96 family.
The MCS-96 family is being used now in a wide variety
of complex control tasks such as robotics, motor con-

Table 3 Advanced i6-Bit Microcontrollers
Device
Name

ROMless
Version

EPROM
Version

ROM
Bytes

RAM
Bytes

I/O
Pins

A/D
Channels

8395

8095

232

29

4

8096

-

8K

8396

8K

232

48

8397

8097 .

-

8K

232

40

8

8395BH

8095BH

8795BH

8K

232

29

4

8396BH

8096BH

8796BH

8K

232

48

8397BH

8097BH

8797BH

8K

232

40

8

83C196KB

80C196KA

87C196KB

8K

232

48

8

• AT is a registered trademark of IBM Corporation.

xvi

intJ

PREFACE

VREF ANGND

POWER
DOWN

-t

FREQUENCY
REFERENCE

m___ __ m
~

CLOCK
GEN

8

Uu:_~- Uj
ROM OR EPROM I
(OPTIONAL):

....."T"--r...... :
I
I

PORTO PORT 1

PORT 2
ALT FUNCTIONS

CONTROL
SIGNALS

HSI HSO

270253-3

'Sample and Hold is only present on BX9XBH devices.

Figure 3. MCS®-96 Block Diagram
trol, hard disk mechanisms, printers, modems, automotive engine control and high performance anti-skid
braking applications.

cations. Six of the most often used functions of an 8086
system have been integrated ---4S

~-,~,

-------4 S.

EN TCNTI
EXECUTED

DIS TCNT!' --lr"'\~~--I
EXECUTED
R

Q

INTERRUPT
IN
'.
PROGRESS'
FF

R

TIMER
INT
ENABLE

Q

RESET

INTcr-------4 D
PIN
RESET

INT
FF

RETR
EXECUTED

CLK

·ALE.~~r-~___~:::]

,

~~~~;;CLE._-t._'
ENI
----Is
EXECUTED

DISI

EXECUTED--l~~_-I R .
RESET

INT
ENABLE

1. WHEN INTERRUPT IN PROGRESS FLIP-FLOP IS SET
ALL FURTHER INTERRUPTS ARE LOCKED OUT
INDEPENDENT OF STATE OF EITHER INTERRUPT
ENABLE FLIP-FLOP.
2. WH!LE TI~ER INTERRUPTS ARE DISABLED TIMER
OVERFLOW III WILL NOT STORE ANY OVERFLOW
'THAT OCCURS. TIMER FLAG WILL BE SET, HOWEVER ..

Figure 8. Interrupt Logic

1-8

SINGLE COMPONENT MCS®-48 SYSTEM

PRESCALER

XTAL + 15 -

+32
LOAD OR READ

I

CLEARED ON START TIMER

r------..... START
EDGE
DETECTOR

COUNTER

JUMP ON
TIMER FLAG

8BITTIMERI
EVENT COUNTER

o

OVERFLOW
FLAG

STOPT

ENABLE--------~___ '

INT

Figure 9. Timer/Event Counter

location 3. Since the timer interrupt is latched it will remain pending until the external device is serviced and
immediately be recognized upon return from the service
routine. The pending timer interrupt is reset by the Call
to location 7 or may be removed by executing a DIS
TCNT! instruction.

olution less than I count an external clock can be applied
to. the TI input and the counter operated in the event
counter'mode. ALE divided by 3 or more can serve as
this external clock. Very small delays or "fine tuning"
of larger delays can be easily accomplished. by software
delay loops.
.

AS AN EVENT COUNTER

Often a serial link is desirabl~ ill an MCSA8 family mem~
ber..Thble 2 lists the timer counts and cycles needed
for a specific baud rate given a crystal frequency.

Execution of a START CNT instruction connects the T!
input pin to the counter input and enables the counter.
The T! input is sampled at the beginning of state 3 or in
later MCS-48 devices in state time 4. Subsequent high to
low transitions on TI will cause the counter to increment.
T! must be held low for at least I machine cycle to insure
it won't be missed. The maximum rate at which the
counter may be incremented is once per three instruction
cycles (every 5.7 f.Lsec when using an 8 MHz crystal)-there is no minimum frequency. TI input must remain
high for at least 1/5 machine cycle after each transition.
AS A TIMER

Eexcution of a START T instruction connects an internal
clock to the counter input and enables the counter. The
internal clock is derived bypassing the basic machine cycle
clock through a + 32 prescaler. The prescaler is reset
during the START T instruction. The resulting clock increments the counter every 32 machine cycles. Various
delays from I to 256 counts can be obtained by presetting
the counter and detecting overflow. Times longer than 256
counts may be achieved by accumulating multiple overflows in a register under software control. For time res1-9

2.11 Clock

and Timing Circuits

Timing generation for the 8048AH is completely selfcontained with the exeception of a frequency reference which
can be XTAL, ceramic resonator, or external clock source.
The Clock and Timing circuitry can be divided into the
following functional blocks.
OSCILLATOR

The on-board oscillator is a high' gain piiU'aUel resonant
circuit with a frequency range of I to 11 MHz .. The XI
external pin is the input to the amplifier stage \:yhile X2
is the output. A crystal or ceramic resonator connected
between XI and X2 provides the feedback and phase shift
required for oscillation. If an accurate frequency reference
is not required, ceramic resonator may be used in place
of the crystal.
.
For accurate clocking, a crystal should be used. An externally generated clock may also be applied to XI-X2
as the frequency source. See the data sheet for more
infermation.

SINGLE COMPONENT MCS®-48 SYSTEM

Table 2. Baud Rate Generation

Baud
Rate

Frequency
(MHz)

Tey

TO Prr(1/5 Tey)

Timer Presealer
(32 Tey)

4
6
8
11

3.751LS
2.501LS
1.881LS
1.361LS

750ns
500ns
375ns
275ns

120ILS
801LS
60.21LS
43.51LS

4 MHz
Timer Counts +
Instr. Cycles

6 MHz
Timer Counts +
Instr. Cycles

8 MHz
Timer Counts +
Instr. Cycles

11 MHz
Timer Counts +
Instr. Cycles

151 + 3 Cycles
.01% Error

208 + 28 Cycles
.01% Error

110

75

+ 24 Cycles
.01% Error

113 + 20 Cycles
.01% Error

300

27

+ 24 Cycles
.1% Error

41

+ 21 Cycles
.03% Error

55

+ 13 Cycles
.01% Error

1200

6

+

30 Cycles
.1% Error

10

+ 13 Cycles
.1% Error

12

+ 27 Cycles
.06% Error

19 + 4 Cycles
.12% Error

1800

4

+

20 Cycles
.1% Error

6

+

30 Cycles
.1% Error

9

+ 7 Cycles
;17% Error

12

+ 24 Cycles
.12% Error

2400

3

+

15 Cycles
.1% Error

5

+ 6 Cycles
.4% Error

6

+ 24 Cycles
.29% Error

9

+ 18 Cycles
.12% Error

4800

1

+ 23 Cycles
1.0% Error

2

+

3

+ 14 Cycles
.74% Error

4

+ 25 Cycles
.12% Error

19 Cycles
.4% Error

STATE COUNTER

76

+ 18 Cycles
.04% Error

power supply is within tolerance. Only 5 machine cycles
(6.8 !J.S @ 11 MHz) are required if power is already on
and the oscillator has stabilized. ALE and PSEN (if EA
= 1) are active while in Reset.

The output of the oscillator is divided by 3 in the State
Counter to create a clock which defines the state times of
the machine (CLK). CLK can be made available on the
external pin TO by executing an ENTO CLK instruction.
The output of CLK on TO is disabled by Reset of the
processor.

Reset performs -the following functions:
1) Sets program counter to zero.

CYCLE COUNTER

2) Sets stack pointer to zero.

CLK is then divided by 5. in the Cycle Counter to provide a clock which defines a machine cycle consisting
of 5 machine states as sho",on in Figure 10. Figure 11
shows the different internal operations as divided into
the machine states. This clock is called Address Latch
Enable (ALE) because of its function in MCS-48. systems with external memory. It is provided continuouslyon the ALE output pin.

3) Selects register bank O.

4) Selects memory bank O.
·5) Sets BUS to high impedance state (except when
EA = 5V).

6) Sets Ports 1 and 2 to input mode.

2.12 Reset

7) Disables interrupts (timer and external).

The reset input provides a means for initialization for the
processor. This Schmitt-trigger input has an internal pullup device which in combination with an external 1 !J. fd
capacitor provides an internal reset pulse of sufficient
length to guarantee all circuitry is reset, as shown in Figure
12. If the reset pulse is generated externally the RESET
pin must be held low for at least 10 milliseconds after the

8) Stops timer.
9) Clears timer flag.
10) Clears FO and Fl.
11) Disables clock output from TO.
1-10

SINGLE COMPONENT MCS®-48 SYSTEM

JUMP ON
TEST = 1 OR 0
XTAL2 . - - - - - . ,
+3
11
STATE
MHzCJ
COUNTER
XTAL 1 L..._ _ _ _..I

.273

~sec

(3.67 MHz)

DIAGRAM OF 8048AH CLOCK UTILITIES

.
55

1.36
51

~sec

52

53

INPUT DECODE
I NST.

I

54

55

51

EXECUTION

INPUT

OUTPUT
ADDRESS

INC. PC

I

~

I

.

CYCLE

I

I

INSTRUCTION CYCLE
(1 BYTE, 2 CYCLE INSTRUCTION ONLY)
PREVIOUS CYCLE-"'~'f-o.
__- - - 1 S T CYCLE----I.......,....
_ - - - 2 N D CYCLE----l...
~1
STATE TIME:
52

I

53

I

54

I

55

I

51

I

52

I

53

I

54

55

I

51

55

I

51

I

52

(02)"TO

~~--------~~----------~~--------

ALE
PSEN' - _ _ _ __,

RD,WR _ _ _ _ _ _ _ _ _ _ _ _ _

~

_ _ _ _ __,

'-------'I

PROG - - - - - - - - - - - - - - - - - - ,
'EXTERNAL MODE
"IF ENABLED

8048AH/8049AH TIMING

Figure 10. MCS®-48 Timing Generation and Cycle Timing

2.13 Single-Step
This feature,· as pictured in Figure 13, provides the
user with a debug capability in that the processor can be
stepped through the program one instruction at a time.
While stopped, the address of the next instruction to be
fetched is available concurrently on BUS and the lower

1-11

half of Port 2. The user can therefore follow the program
through each of the instruction steps. A timing diagram,
showing the interaction between output ALE and input
SS, is shown. The BUS buffer contents are lost during
single step; however, a latch may be added to reestablish
the lost I/O capability if needed. Data is valid at the leading
edge of ALE.

CYCLE 1
INSTRUCTION

I£i
c
iiJ

~

-

-

OUTPUT
TO PORT

-

INCREMENT
PROGRAM COUNTER

'OUTPUT
TO PORT
'OlirPUT
TO PORT

INCReMENT
FETCH
INSTRUCTION PROGRAM COUNTER

-

OUTL P,A

FETCH
INCRleMENT
INSTRUCTION PROGRAM COUNTER

ORL P,= DATA

INCReMENT
FETCH
INSTRUCTION PROGRAM COUNTER

INSA,BUS

FETCH
INCReMENT
INSTRUCTION PROGRAM COUNTER

'INCREMENT
TIMER

READ PORT

FETCH
IMMEDIATE DATA

-

INCREMENT
PROGRAM COUNTER

INCREMENT
TIMER

-

-

READ
PORT

INCREMENT
TIMER

OUTPUT
TO PORT

-

-

-

'INCREMENT
TIMER

READ PORT

FETCH
IMMEDIATE. DATA

-

INCREMENT
PROGRAM COUNTER

'OUTPUT
TO PORT

-

'INCREMENT
TIMER

READ PORT

FETCH
IMMEDIATE DATA

-

INCREMENT
PROGRAM COUNTER

'OUTPUT
TO PORT

READ
DATA

-

-

ORL BUS, = DATA

INCREMENT
FETCH
INSTRUCTION PROGRA'. COUNTER

MOVX@R,A

FETCH
INCREMENT
INSTRUCTION PROGRAII COUNTER

OUTPUT RAM
ADDRESS

INCREMENT
TIMER

OUTPUT·
DATA TO RAM

MOVXA,@R

FETCH
INCREMENT
INSTRUCTION PROGRAII COUNTER

OUTPUT RAM
ADDRESS

INCREMENT
TIMER

-

MOVDA,PI

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

-

MOVDPI,A

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

OUTPUT DATA
TOP2LOWER

ANLDP,A

INCREMENT
FETCH
INSTRUCTION PROGRAM COU·NTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

OUTPUT
DATA

ORLDP,A

FETCH
INCR:EMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODEIADDRESS

INCREMENT
TIMER

. OUTPUT
DATA

SAMPLE
CONDITION

'INCREMENT
SAMPLE

-

..

5'
!!I.
c

-....
n
0"

:::s

3"

5'

ICI

C

iii"

ICI

iii
:I

INCR:EMENT
FETCH
J(CONDITIONAL)
INSTRUCTION PROGRAM COUNTER
STRTT
STRTCNT

FETCH
INCFIEMENT
INSTRUCTION PROGRAM COUNTER

STOP TCNT

FETCH
INCFIEMENT
INSTRUCTION PROGRAM COUNTER

ENI

FETCH
INCFIEMENT
INSTRUCTION PROGRA'M COUNTER

DISI

INCFlEMENT
FETCH
INSTRUCTION PROGRAM COUNTER

ENTOCLK

FETCH
INCIIEMENT
INSTRUCTION PROGRAM COUNTER

·

-

L- ___

-

START
COUNTER

-

• ENABLE
INTERRUPT

-

• DISABLE.
INTERRUPT

-

·

------

-

READ PORT

• ENABLE
CLOCK

FETCH
IMMEDIATE DATA

READP2
LOWER

-

-

UPDATE
PROGRAM COUNTER

·
..

-

-

·······

-

-

-

-

STOP
COUNTER

·VALID INSTRUCTION ADDRESSES ARE OUTPUT
AT THIS TIME IF EXTERNAL PROGRAM MEMORY IS
BEING ACCESSED.
(1) IN LATER MC5-48 DEVICES T1 IS SAMPLED IN S4.

-

!

-

'INCREMENT
TIMER

-

%

-

FETCH
IMMEDIATE DATA

INCREMENT
FETCH
INSTRUCTION PROGRAM COUNTER

~

-

-

'INCREMENT
TIMER

ANL BUS, = DATA

...

··-

-

FETCH
INCRIEMENT
INSTRUCTION PROGRAM COUNTER

CD

~
%
CD
0

55

READ
PORT

OUTL BUS, A

...

54

S3

'INCREMENT
TIMER

...:-"
0

....

54

S2

INA,P

"II

S3

S1

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

ANLP,=DATA

CYCLE 2

~)2

S5

S1

UI

Z

C)

rm

I

o
o

i:
"U

oZ

m
Z
-t
i:

tl
@

.~

~

m
i:

SINGLE COMPONENT MCS®-4B SYSTEM

clear input. ALE should be buffered since the clear input
of an SN7474 is the equivalent of 3 TTL loads. The
processor is now in the stopped state. The next instruction
is initiated by clocki!!g a "1" into the flip-flop. This "1"
will not appear on SS unless ALE is high removing clear
from the flip-flop. In response to SS going high the processor be~s an instruction fetch which brings ALE low
resetting SS through the clear input and causing the processor to again enter the stopped state.

EXTERNAL RESET

Vcc

ACTIVE
PULLUP

2.14 Power Down Mode
(B048AH, B049AH, 8050AH,
B039AHL, 8035AHL, B040AHL)

POWER ON RESET

Extra circuitry has been added to the 8048AHl8049AHI
8050AH ROM version to allow power to be removed from
all but the data RAM array for low power standby oper~
ation. In the power down mode the contents of data RAM
can be maintained while drawing typically 10% to 15%
of normal operating power requirements.

.J:L 1K

f

Vee serves as the 5V supply pin for the bulk of circuitry
while the VDD pin supplies only the RAM array. In normal
operation both pins are a 5V while in standby, Vee is at
ground and VDD is maintained at its standby value. Applying Reset to the processor through the RESET pin
inhibits any access to the RAM by the processor and
guarantees that RAM cannot be inadvertently altered as
power is removed from Vcc.

Figure 12.

TIMING
The 8048AH operates in a single-step mode as follows:
I) The processor is requested to stop by applying a low
level on SS.

A typical power down sequence (Figure 14) occurs as
follows:

2) The processor responds by stopping during the address
fetch portion of the next instruction. -If a double cycle
instruction is in' progress when the single step command is received, both cycles will be completed before
stopping.

1) Imminent power supply failure is detected by user defined circuitry. Signal must be early enough to allow
8048AH to save all necessary data before Vee falls
below normal operating limits.

3) The proc~ssor acknowledges it has entered the stopped
state by raising ALE high. In this state (which can be
maintained indefinitely) the address of the next instruction to be fetched is present on BUS and the lower
half of port 2.
4) ss is then raised high to bring the processor out of the
stopped mode allowing it to fetch the next instruction.
The exit from stop is indicated by the processor bringing ALE low.

2) Power fail signal is used to interrupt processor and
vector it to a power fail service routine.
3) Power fail routine saves all important data and machine
status in the internal data RAM array. Routine may
also initiate transfer of backup supply to the VDD pin
and indicate to external circuitry that power fail routine
is complete.

5) To stop the processor at the next instruction SS must
be brought low again soon after ALE goes low. If SS
is left high the processor remains in a "Run" mode,

4) Reset is applied to. guarantee data will not be altered
as the power supply falls out of limits. Reset must be
held low until Vee is at ground level.

A. diagram for implementing the single-step function of
the 8748H is shown in Figure 13. D.:!}'pe flip-flop with
preset and clear is used to generate SS. In the run mode
SS is held high by keeping the flip-flop preset (preset has
precedence over the clear input). To enter single step,
preset is removed allowing ALE to bring SS low via the

Recovery from the Power Down mode can occur as any
other power-on sequence with an external capacitor on
the Reset input providing the necessary delay. See the
previous section on Reset.

1-13

SINGLE COMPONENT MCS®-48 SYSTEM

+5V

SINGLE

+5V

MOMENTARY
PUSHBUTTON

10K

~u~PN--~-----------'

10K

PRESET
+5V

D

Q

+5V
,..--------(> CLOCK

10K

DEBOUNCE
LATCH
1/27400
ALE
SINGLE STEP CIRCUIT

1

S3

1

54

1

S5

I

S1

1

S2

1 S3

1 • •

·IS3154IS51

1 S2

1

ALE~

n

SS

BUS

P2D-23

PCD-7

1/0

: :

PC 8-11

S

:

SINGLE STEP TIMING

Figure 13. Single Step Operation

1·14

C
1/0

SINGLE COMPONENT MCS®-48 SYSTEM

reset the prescaler and time state generators. TO may then
be brought down with the rising edge of Xl. Two clock
cycles later, with the rising edge of X I, the device enters
into Time State 1, Phase 1, SS' is then brought down to
5 volts 4 clocks later after TO. RESET' is allowed to go
high 5 tCY (75 clocks) later for nonnal execution of code.
See Figure 15.

POWER~
SUPPLY

PROCESSOR;

INTE~RUPTED I

"--:

POWER ~
I
I
SUPPLY
·_ _ _' _ _ I_ _ _
FAIL SIGNAL
I
I
I
I
I
RESET

NORMAL
POWERON
SEQUENCE
FOLLOWS

LJ ___ _

:
i

DATA SAVE
ROUTINE
EXECUTED

i

ACCESS TO
DATA RAM
INHIBITED

Figure 14. Power Down Sequence

2.15 External Access Mode
Nonnally the first IK (8048AH), 2K (8049AH), or 4K
(8050AH) words of program memory are automatically
fetched from internal ROM or EPROM. The EA input pin
however allows the user to effectively disable internal
program memory by forcing all program memory fetches
to reference external memory. The following chapter explains how access to external program memory is
accomplished.
The External Access mode is very useful in system test
and debug because it allows the user to disable his internal
applications program and substitute an external program
of his choice - a diagnostic routine for instance. In ad- .
dition, the date sheet shows how internal program memory can be read externally, independent of the processor:
A "1" level on EA initiates the external accesss mode.
For proper operation, Reset should be applied while the
EA input is changed.

2.16 Sync Mode
The 8048AH, 8049AH, 8050AH has incorporated a new
SYNC mode. The Sync mode is provided to ease the
design of mUltiple controller circuits by allowing the designer to force the device into known phase and state time.
The SYNC mode may also be utilized by automatic test
equipment (ATE) for quick, easy, and efficient synchronizing between the tester and the OUT (device under test).
SYNC mode is enabled when SS' pin is raised to high
voltage level of + 12 volts. To begin synchronization, TO
is raised to 5 volts at least four clocks cycles after SS'.
TO must be high for at least four X I clock cycles to fully

1-15

SINGLE COMPONENT MCS®-48 SYSTEM

X1

PHASE 1- -

-

-

-

-- -

-

--"'-:""

PHASE 2- -

-

-

-

-

-

-

-

-

-

-

-

TIME STATE
SS

2

3

4

1~~----.J
OV
5V

TO

OV--------------------~

5V
5V

ALE

RESET

OV--------------------------------------------------~

OV--------------------------------------------~------~---------------

SYNC MODE TIMING

Figure 15. Sync Mode Timing

3.0 PIN DESCRIPTION

8

PORT
#1

8

PORT
#2

The MCS-48 processors are packaged iii 40 pin Dual InLine Packages (DIP's). Thble 3 is a summary of the
functions of each pin. Figure 16 is the logic symbol
for the 8048AH product family. Where it exists, the second paragraph describes each pin's function in an expanded MCS-48 system. Unless ·otherwise specified, each
input is TIL compatible and each output will drive one
standard TIL load.
.

RESET
SINGLE STEP
EXTERNAL
MEM
TEST {
INTERRUPT
BUS

8

B048AH
B049AH
BOSOAH

READ
WRITE
PROGRAM
STORE ENABLE
ADDRESS
LATCH ENABLE

Figure 16. 8048AH and 8049AH Logic Symbol

1-16

SINGLE COMPONENT MCS®-48 SYSTEM

Table 3. Pin Description
Designation

Pin
Number*

Function

Vss

20

Circuit OND potential

VDD

26

Programming power supply; 2lV during program for the 8748H/8749H; + 5V during
operation for both ROM and EPROM. Low power standby pin in 8048AH and
8049AH/8050AH ROM versions.

Vee

40

Main power supply; +5V during operation and during 8748H and 8749H programming.

PROG

25

Program pulse; + 18V input pin during 8748H /8749H programming. Output strobe
for 8243 I/O expander.

PIO-PI7
(Port I)

27-34

8-bit quasi-bidirection,aI port. (Inte~nal Pullup= 50KH)

P20-P27
(Port 2)

21-24
35-38

8-bit quasi-bidirectional port. (Internal Pullup = 50KH)
P20-P23 contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit I/O expander bus for 8243.

DO-D7
(BUS)

12-19

True bidirectional port which can be, written or read synchronously using the RD.
WR strobes. The port can also be statically latched.
Contains the 810w 'order program counter bits during an external program memory fetch. and receives the addressed instruction under the control of PSEN. Also
, contains the address and data during, an external RAM data store instruction.
, under ,control of ALE, RD, and WR.

TO

I

Input pin testable using the conditional transfer instructions JTO and JNTO. TO
can be designated as a clock output using ENTO CLK instruction. TO is also used
during programming and sync mode.

TI

39

Input pin testable using the JT I, and JNTI 'instructions. Can be design~ted the
event counter input using the STRT CNT instruction., (See Section 2.10).

IN'f

6

Interrupt input. Initiates an in'terrupt' if interrupt is enabled. Interrupt is disabled
after a reset. (Active low)

-RD

8

Output strobe activated during a BUS read. Can be used to enable data onto the
BUS from an external device. (Active low)

Interrupt must remain low for at least 3 machine cycles to ensure proper operation.

Used as a Read Strobe to External Data Memory.
RESET

4

Input which is used, to initialize the processor. Also used during EPROM programming
and verification. (Active low) (Internal pullup =80K fi)

WR

10

Output strobe during a BUS write. (Active low) Used llS write strobe to external
data memory.

ALE

II

Address 'Latch Enable. This signal occurs once during each cycle and is useful as
a clock output.
The negative edge of A LE strobes address into external data and program memory.

1-17

SINGLE COMPONENT MCS®-48 SYSTEM'

lllble 3. 'Pin Description (Continued)
Designation

Pin
Number·

PSEN

9

SS

5

EA

7

Function
Program Store Enable. This output 'occurs only during a fetch to external program
memory. (A~tive low)
Single step input cari be used i~ c~njunction with ALE to "single step" the processor
through each instruCiion. (Active low) (Internal imllup 300Kn) +12V for sync
modes (See 2.16).

=

External Access input which forces all program memory fetches to reference external memory. Useful for emulation and debug; and essential for testing and program verification. (Active high) +12V for8048AH/8049AH/8050AH program
xerification and +18V for 8748H/8749H program verification (Internal pullup
IOMn on 8048AH/8049AH/8035AHL/8039AHL/8050AH/8040AHL)

=

XTALI

2

XTAL2

3

, One side of cryst~1 input for internal oscillator. Also input for external source.
Other side of crystal/external source input.

;

'Unless otherwise stated, inputs dO,not have internal pullup resistors. 8048AH, 8748H, 8049AH, 8050AH, 8040AHL

4.0 PROGRAMMING, VERIFYING AND
'ERASING EPROM

8748H AND 8749H ERASURE
,,CHARACTERISTICS

The internal Pmliram Memory of the 8748H and the
8749H may be erased and reprogrammed by the user as
explained in the following sections. See also the 8748H
and 8749H data sheets.

The erasure characteristics of the 8748H and 8749H are
such that erasure begl.ns'to occur when exposed to light
with wavelengths shorter than approximately 4000 Angs"
troms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data show that constant exposure to
level fluorescent: lighting could erase the typical
8748H'and 8749H in approximately 3 years while it would
take approxima1l1ly I week to cause erasure when exposed
to direct sunlight. If the 8748H or 8749H is to be exposed
to these types, of lighting conditions for extended periods
of time,' opaque labels should be placed over the 8748H

4.1 ProgrammlngNerlflcatlon

room

In brief, the programming process consists of: activating
the program mode, applying an address, latching the address, applying data, and applying a programming pulse.
This programming algorithm applies to both the 8748H
and 8749H. Each word is programmed completely before
mOv1-!!g on to the next and is followed by a verificatiQn
step. The following is a list of the pins used for program~
ming and a descsription of their functions:

Pin
XTAL 1
Reset
Test 0

EA
BUS
P20-1
P20-2
Voo
PROG
PIO-Pll

windo,: to prevent unintentional erasure.
When erased, bits of the 8748H and 8749H Program Memory are in the logic "0" state.

Function
Clock Input (3 to 4 MHz)
,
Initialization and Address Latching
Selection of Program (OV) or Verify
'
(5V) Mode
Activation of Program/Verify Modes
Address and Data Input Data' Output
During Verify
Address Input for 8748H
Address Input for 8749H
Programming Power Supply
Program Pulse Input
Tied to ground (8749H only)

,The 'recommended erasure procedure for the 8748H and
8749H is exposure to shortwave ultraviolet light which
has a wavelength of 2537 Angstroms (A). The integrated
dose (i.e., UV intensitY X exposure time) for erasure
should be, a minimum of 15W-sec/cm2 • The erasure time
with this dosage is approximately IS to 20 minutes'using
an ultraviolet lamp with a 12000p'w/cm2 power rating.
The 8748H ,and 8749H should be placed within one inch
from the lamp tubes during erasure. Some lamps have a
filter in their tubes ,and this filter should be removed before
erasure.

1·18

SINGLE COMPONENT MCS-48 SYSTEM

COMBINATION PROGRAMIVERIFY MODE (EPROM. ONLY)

lav

/

EA 5V _ _ _ _- J

I--------PROGRAM--------!---VERIFY---!-----PROGRAMITW-TO

tww-----,--RESET
tAW+---t-~+- tWA
~

DBO-DB7

r-~D~AT~A~T~O~BE~~

--F - -

P20-P22

PROGRAMMED VALID

LAST
ADDRESS

NEXT
ADDRESS
tVDDWffttvD?H
_
WT

+21
vDD

+5--------------

PROG+:: ____________

------------------------------

~:£V____\tt~W:

__

-- - - - - - =--,.:-"'. . _---

+0

, VERIFY MODE (ROM/EPROM)
EA

*TO,
RESET

DBO-DB7

_-oJ/
~'-____________---.JI

J--

P20-P22

\ . . . ._ _---JI

__ -<

ADDRESS
(0-7) VALID

NEXT

X

~,__.;..A;;;;D.;;;D.;..R.;;;E,;;,SS;;......J.

ADDRESS (8-10) VALID

I\IEXT DATA)- __ _
. OUT VALID.

NEXT ADDRESS VALID

NOTES:
1. PROG MUST FLOAT IF EA IS LOW (I.E., "" leV).

"TO ON EPROM ONLY.

Figure 17. Pl'9gramlVerify Sequence for 8749H18748H

1·19

MCS®,.48 Expanded System

2

EXPANDED MCS®-48 SYSTEM
1'.0 INTRODUCTION

1) The contents of the 12-bit program counter will be
output on BUS and the lower half of port 2.
2) Address Latch Enable (ALE) will indicate the time at
which address is valid. The' trailing edge of ALE is
used to latch the address externally.
3) Program Store Enable (PSEN) indicates that an external instruction fetch is in progress and serves to enable
the external memory device.
4) BUS reverts to input (floating) mode and the processor
accepts its 8-bit contents as im instruction word.

If the capabilities resident on the single-chip S04SAHI

S74SH/S035AHUS049AH/S749H/S039AHL are not sufficieflt for your system requirements, special on-board circuitry allows the addition of a wide variety of external
memory, 110, or special peripherals you may require. The
processors can be directly and simply expanded in the
foilowing areas:
• Program Memory to 4K words
• Data Memory to 320 words (3S4 words with
S049AH)
• 110' by unlimited amount
• Special Functions uSingSOSO/SOS5AH peripherals

ALE

By using bank switching techniques, maximum capability
is essentially unlimited. Bank switching is discussed later
in the chapter. Expansion is accomplished in two ways:
1) Expander 110 - A special 110 Expander circuit, the
S243 , provides for the addition of four 4-bit Input!
Output ports with the sacrifice of only the lower half
(4-bits) of port 2 for inter-device communication. Multiple S243's may be added to this 4-bit bus by generating the required .. chip select" lines.
2) Standard SOS5 Bus - One port of the S04SAHI
S049AH is like the S-bit bidirectional data bus of the
: SOS5 microcomputer system allowing interface to the
numerous standard memories and peripherals of the
MCS@-SO/S5 microcomputer family.

L

PSEN
FLOATING
BUS

~FLOATINGO FLOATING
ADDRESS

INSTRUCTION

Figure 1. Instruction Fetch from
External Program Memory
All inStruction fetches, including internal addresses, caD. be
forced to be external by activating the EA pin of the 8048AH1
8049AH18050AH. The 8035AHU8039AHUS04OAHL processors without program memory always operate in the external program memory mode (EA = 5V).

MCS-4S systems can be configured using either or both
of these expansion features to optimize system capabilities
to the application.

2.2 Extended. Program Memory
AddreSSing (Beyond 21<)

Both expander devices and standard memories and peripherals can be added in virtually any number and combmation required.
,

J

For programs of 2K words or less, the 8048AH/8049AH
addresses program memory in the conventional manner.
Addresses beyond 2047 can be reached by executing a
program memory bank switch instruction (SEL MBO, SEL
MBI) followed by a branch instruction (JMP or CALL).
The bank switch feature extends the range of branch instructions beyond their normal 2K range and at the same
time prevents the user from inadvertently crossing the 2K
boundary ..

.

'. 2.0 EXPANSION OF PROGRAM MEMORY
Program Memory is expanded beyond the resident IK or
2K words by using the SOS5 BUS feature of the MCS@48. All program memory fetches from the addresses less
. than 1024 on the S04SAH and less than 204S on the
. S049AH occur internally with no external signals being
generated (except ALE which is always present). At address 1024 on the S04SAH, the processor automatically
initiates external program memory fetches.

PROGRAM MEMORY BANK SWITCH

The switching of 2K program memory banks is accomplished by directly setting or resetting the most significant
bit 'of the program counter (bit 11); see Figure 2. Bit
II is not altered by nQrmal incrementing of the program
counter but is loaded with the contents of a special flipflop each time a JMP or CALL instruction is executed.
This special flip-flop is set by executing an SEL MBI

2.1 Instruction Fetch Cycle (External)
As shown in Figure 1, for all insinicti~n fetches from
addresses of 1024 (2048) or greater, the following will
occur:

2-1

EXPANDED MCS®-48 SYSTEM

instruction and reset by SEL MBO. Therefore, the SEL
MB instruction may be executed at any time prior to the
actiJal bank switch which occurs during the next branch
instruction encountered. Since all twelve bits of the program counter; including bit 11, are stored in the. stack,
when a Call is executed, the user may jump·to subroutines
across the 2K boundary and the proper bank will be restored upon return. However, the bank switch flip-flop
will not' be altered on return.

counter is held at "0" during the interrupt service routine.
The end of the service routine is signalled by the execution
of an RETR instruction. Interrupt service routines should
therefore be contained entirely in the lower 2K words of
program memory. The execution of a SEL MBO or SEL
MB I instruction within an interrupt routine is nOt recommended since it will not alter PCII while in the routine,
but will change the internal flip-flop~

2.3 Restoring 110 Port Information
,Although the lower half of Port 2 is u~ to output the
four most significant bits of address during an external
program memory fetch, the 110 information is still ootputed during certain portions of each machine cycle. 110
information is always present on Port 2's lower 4 bits at
the rising edge of ALE and can be sampled or latched at
this time.

IAnIAwl~I~I~I~I~I~I~I~I~I~1
Conventional pr~gram Counter
'

C

• Counts OOOH to 7FFH
• Overflows 7FFH to OOOH
JMP or CALL Instructions transfer contents
ofinternallllpflop.to A11
• Flipflop set by SEL MB1
• Flipflop reset by SEL MBO
or by RESET

2.4, Expansion Examples

During interrupt service routine
A11 i. forced to "0"
All 12 bits are saved in stack

Shown in Figure 3 is the addition· of 2K words of
program memory using an 2716A 2K x 8 ROM to give
a total of 3K words of program mem0!I:...!!!.'this case no
chip select decoding is required and PSEN enables the
memory directly through the chip select input. If the system requires only 2K of progra!ll memory, the same configuration can be used with an 803SAHL substituted for
the. S04SAH. The 8049AH would provide 4K of program
memory with the same configuration.

Figure 2. Program Counter
INTERRUPT ROUTINES
. Interrupts always vector the program counter tO'location
3 or 7 iii 'the first 2K bank, 'and bit II of the program

3

II

~.,
8048AH

ALE

,irV

A

,74LS373
LATCH

"
n)

ADDRESS

v

2718
EPROM
DATA
OUT

BUS r'--8
PSEN

CiS

.'

USING 2K

x

8 EPROM

Figure 3. Expa~ding MCSC!l~48 Program Memory Using Standard Memory Products

2-2

EXPANDED MCS®-48 SYSTEM

Figure 4 shows how the 8755/8355 EPROM/ROM with

lio interfaces directly to the 8048AH without the need
for an address latch. The 8755/8355 contains an internal
8-bit address latch eliminating the need for an 8212 latch.
In addition to a 2K x 8 program memory. the 8755/8355
also contains 16 110 lines addres.sable as two 8-bit ports.
These ports are addressed as external RAM; therefore the
RD and WR outputs of the 8048AH are required. See the
following section on data memory expansion for more
detail. The subsequent section on 110 expansion explains
the operation of the 16 I/O lines .

ALE

RD
lOW
lOR

8048AH
8049AH

AlDO_7

2K x 8
ROMI
EPROM
WITH

1/0

8~~1
8755

.A8-Al0. CS

3.0 EXPANSION OF DATA MEMORY
Data Memory is expanded beyond the resident 64 words
by using the 8085AH type bus feature of the MCS®-48.

3

TEST
INPUTS

3.1 Read/Write Cycle

1/0

All address and data is transferred over the 8 lines of
BUS. As shown in Figure 5, a read or write cycle
occurs as follows:

Figure 4. External Program Memory Interface

ALE

J.

L
I

BUS

FLOATING XADDRESSX

7' ~___FL_O_A_TI_N_G_ __

FLOATING

READ FROM EXTERNAL DATA MEMORY

ALE

J

L
I

BUS

FLOATING

FLOATING

WRITE TO EXTERNAL DATA MEMORY

Figure 5. External Data Memory Timings

2-3

EXPANDED MCS®-48 SYSTEM

I) The contents of register RO or RI is outputed on BUS.

4.0 EXPANSION OF INPUT/OUTPUT

2) Address Latch Enable (ALE) indicates addre.sss is
valid. The· trailing edge of ALE is used to latch the
address externally.
3) A read (RD) or write (WR) pulse on the corresponding
output pms of the 8048AH indicates the type of data
memory access ~gress. Output data is valid at the
trailing edge of WR and input data must be valid at
the trailing edge of RD;

There are four possible modes of II() expansion with the
8048AH: one using a special low-cost expander, the 8243;
another using standard MCS~80/85110 devices; and a third
using the combination memory 110 expander devices the
8155, 8355, and 8755. It is also possible to expand using
standard TTL devices.

·4.1 I/O Expander Device

4) Oat (8 bits) is transferred in or out over BUS.

3.2 Addressing External Data Memory
ExternBI Data Memory is accessed with its own two-cycle
move instructions. MOVXA, @R and MOVX@R, A,
which transfer 8 bits of data between the accumulator and
the external memory location addressed by the. contents
of one of the RAM Pointer Registers RO and RI. This
allows 256 locations to be addressed in addition to the
resident locations. Additional pages may be added by'
"bank switching" with extra output lines of the 8048AH.

The most efficient means of 110 expansion for small systems is the 8243 110 Expander Device which requires only
4 port lines (lower half of Port 2) for communication with
the 8048AH. The 8243 contains four 4-bit 110 ports which
serve as an extension of the on-chip 110 and are addressed
. as ports #4-7 (see Figure 13-7). The following operations
may be performed on these ports:
• Transfer Accumulator to Port
• Transfer Port to Accumulator·
• AND Accumulator to Port

3.3 Examples of Data Memory Expansion

• OR Accumulator to Port
Figure 6 shows how the 8048-AH can be expanded
using the 8155 memory and 110 expanding device. Since
the 8155 has an internal8-bit address latch, it can interface
directly to the 8048AH without the use of an external
latch. The 8155 provides an additional 256 words ofstatic
data memory and also includes 22 110 lines and a 14-bit
timer. See the following section on 110 expansion and the
8155 data sheet for more details on these additional
features.

A 4-bit transfer from a port to the lower half of the Accumulator sets the most significant four bits to zero. All
communication between the 8048AH and the 8243 occurs
over Port 2 lower (P20-P23) with timing provided by an
output pulse on the PROG pin of the processor. Each transfer consists of two 4-bit nibbles: The first containing the
"op code'.'and port address, and t\le second containing
the actual 4 bits of data ..

Busk'------;;8,-----~
ADO_7
v
ALE

8048AH

"

WR

ALE 8155
256x8
ViR RAM

AD

iii>

PORT

3

TEST
INPUTS

18

1/0

22

1/0
TIMER IN
TIMER OUT

101M

Figure 6. 8048AH Interface to 256 x8 Standard Memories

··2-4

EXPANDED MCS®-48 SYSTEM

fl
-=~I/O
"

CHIP SELECT CONNECTIO NIFMORE
THAN ONE EXPANDER IS USED

CS
P4

V

4

1/0
or

PROG

PROG

A

2

8050AH
8049AH
8048AH

P5

J i::JTS

"

4

1/0
v

8243

t-.
"-

4.

P20-P23

v

"

P6

4

P7

4

v

DATA IN
P2

1/0

1/0
v

EXPANDER INTERFACE

PROG

P20-P23

\

BITS 0, 1

' - . _ _ _- - I/

--<'-___X'-_____),..---

BITS 2, 3

OO}

00}
01
PORT
01
10
ADDRESS 10
11
11

READ
WRITE
OR
AND

DATA (4-BITS)

ADDRESS
ANDOPCODE
(4-BITS)

OUTPUT EXPANDER TIMING

Figure 7. 8243 Expander I/O Interface

3

Nibble I
2 I 0

3

I I I I IA IA I
Instruction
Code

4.2 1/0 Expansion with Standard
Peripherals

Nibble 2
2 I 0

I did IdId I
Port
Address

Standard MCS-80/85 type 110 devices may be added to
the MCSIII>-48 usinl!; the same bus and timinl!; used for Data
Memory expansion. Figure 8 shows an example of how
an 8048AH can be connected to an MCS-85 peripheral.
110 devices reside on the Data Memory bus and in the
data memory address space and are accessed with the same
MOVX instructions. (See the previous section on data
memory expansion for a description of timing.) The following are a few 9f the Standard MCS-80 devices which
are very useful in MCSIII>-48 systems:
• 8214 Priority Interrupt Encoder
• 8251 Serial Communications Interface
• 8255 General Purpose Programmable 110
• 8279 Keyboard/Display In~erface
• 8254 Interval Timer

data

II

AA

00 Read
01 Write
10 OR
II AND

00 - Port #4
01 - Port #5
10- Port #6
II-Port#7

A high to low transition of the PROG line indicates that
address is present, while allow to high transition indicates
the presence of data. Additional 8243's may be added to
the four-bit bus and chip selected using additional output
lines from the 8048AH/8748H.
1/0 PORT CHARACTERISTICS

4.3 Combination Memory and
110 Expanders

Each of the four4-bit ports of the 8243 can serve as either
input or output and can provide high drive capability in
both the high and low state.

As mentioned in the sections on program and data memory
expansion, the 8355/8755 and 8155 expanders also contain
I/O capability;

2-5

EXPANDED MCS®-48 SYSTEM

8
INT

INT

P20

c/o
8279
KEYBOARD
DISPLAY

8048AH
RD

RD

WR

WR

BUS

8

KEYBOARD
INPUTS

SCAN
OUTPUTS
(A) DISPLAY
OUTPUT

DATA
BUS

Cs

(B) DISPLAY
OUTPUT

Figure 8. Keyboard/Display Interface
port. These three registers and aControllStatus register
are accessible as external data memory with the MOVX
instructions. The contents of the control register determines the mode of the three ports. The ports can be programmed as input or output with or without associated
handshake communication lines. In the handshake mode,
lines of the six-bit port become input and output strobes
for the two 8-bit ports. Also included in the 8155 is a
14-bit programmable timer. The clock input to the timer
and the timer overflow output are available on external
pins. The timer can be programmed to stop on tenninal
count or to continuously reload itself. A square wave or
pulse output on terminal count can also be specified.

8355/8755: These two parts of ROM and EPROM equivalents and therefore contain the same 110 structure. 110
eonsists of two 8-bit ports which nonnally reside in the
external data memory address space and are accessed with
MOVX instructions. Associated with each port is an 8"it Data Direction Register which defines each bit in the
port as either an input or an output. The data direction
registers are directly addressable, thereby allowing the'
user to define under software control each individual bit
of the ports as either input or output. All outputs. are
statiCally latched and double buffered. Inputs
not
latched.
8155/8156: 110 on the 815518156 is configured 'as two
8-bit programmable 1/0 ports and one 6-bit programmable

are

Figure 9. Low Cost 110 Expansion

2-6

EXPANDED MCS®-48 SYSTEM

1/0 EXPANSION EXAMPLES

Figure 10 shows the 8048AH interface to a standard
MCS®-80 peripheral; in this case, the 8255 Programmable
Peripheral Interface, a 40-pin part which provides three
8-bit programmable I/O ports. The 8255 bus interface is
typical of programmable MCS®-80 peripherals with an
8-bit bidirectional data bus, a RD and WR input for Read/
Write control, a CS (chip select) input used to enable the
Read/Write control logic and the address inputs used to
select various internal registers.

Figure 9 shows the expansion of 110 using multiple
8243's. The only difference from a single 8243 system is
the addition of chip selects provided by additional8048AH
output lines: Two output liens and a decoder could also
be used to address the four chips. Large numbers of 8243' s
would require a chip select decoder chip such as the 8205
to save I/O pins.

8048AH ALE
RO

AD
8255
A1 PROGRAMMABLE
PERIPHERAL
INTERFACE

PORT
A

P20
P21

PORT
B

8048AH _
RO

PORT
C

WR
BUS

Ao

8255
A1 PROGRAMMABLE
PERIPHERAL
INTERFACE
RO

Wii
8

PORT
B
PORT
C

00-7

CS
OPTION #1

PORT
A

CS

-=

OPTION #2

-=

Figure 10. Interface to MCS®-BO Peripherals
Interconnection to the 8048AH is very straightforward
with BUS, RD, and WR connecting directly to the corresponding pins on the 8255. The only design consideration is the way in which the internal registers of the 8255
are to be addressed. If the registers are to be addressed
as external data memory using the MOVX instructions,
the appropriate number of address bits (in this case, 2)
must be latched on BUS using ALE as described in the
section on external data memories. If only a single device
is connected to BUS, the 8255 may be continuously selected by grounding CS. If multiple 8255's are used, additional address bits can be latched and used as chip'
selects.

addressing of the various memories and 110 ports. Note
that in this configuration address lines A 10 and A 11 have
been ORed to chip select the 8355. This ensures that the
chip is active for all external program memory fetches in
the lK to 3K range and is disabled for all other addresses.
This gating has been added to allow the 110 port of the
8355 to be used. If the chip was left selected all the time,
there would be conflict between these ports and the RAM
and I/O of the 8156. The NOR gate could be eliminated
and Al1 connected directly to the CE (instead of CE) input
ofthe 8355; however, this would create a lK word "hole"
in the program memory by causing the 8355 to be active
in the 2K and 4K range instead of the normal lK to 3K
range.

A second addressing method eliminates external latches
and chip select decoders by using output port lines as address and chip select lines dircctly.r'his method. of
course, requires the setting oran output port with address
information prior to executing a MOVX instruction.

In this system the various locations are addressed as
follows:'
• Data RAM - Addresses 0 to 255 when Port 2 Bit
o has been previously set = 1 and Bit I' set = 0
Addresses 0 to 3 when Port 2 Bit 0 =
1 and Bit 1 = 1

• RAM 110 -

5.0 MULTI-CHIP MCS®-48 SYSTEMS

• ROM I/O Bit 3 = 1

Figure 11 shows the addition of two memory expanders
to the 8048AH, one 8355/8755 ROM and one 8156 RAM.
The mirin consideration in designing such a system is the

Addresses 0 to 3 when Port 2 Bit 2 or

See the memory map in Figure 12.

2-7

EXPANDED MCS®-48 SYSTEM

8156/8355
A8-10

PORT
83551

8755
ROM
EPROM

ALE
PSEN
8048AH RD
WR

BUS

8

PORT

ADO-7
101M

-=PORT
A

8

8156
RAM
A9

101M

PORT
B
PORT

c

Figure 11. The Three-Component MCS®-48 System

6.0 MEMORY BANK SWITCHING

Jumping to subroutines across the boundary should be
avoided when possible since the programmer must keep
track of which bank to return to after completion of the
subroutine. If these subroutines are to be nested and accessed from either bank, a software "stack" should be
implemented to save the bank switch bit just as if it were
another bit of the program counter.

Certain systems may require more than the 4K words of
program memory which are directly addressable by the
program counter or more than the 256 data memory and
110 locations directly addressable by the pointer registers
RO and Rl. These systems can be achieved using "bank
switching" techniques. Bank switching is merely the selection of vari()US blocks of "banks" of memory using
dedicated output port lines from the processor. In the case
of the 8048AH, program memory is selected in blocks of
4K words at a time, while data memory and 110 are en. abled 256 words at a time.

From a hardware standpoint bank switching is very
straightforward and involves only the connection of an
110 line or lines as bank enable signals. These enables are
ANDed with normal memory and 110 chip select signals
to activate the proper bank.

The most important consideration in implementing two or
more banks is the software required to cross the bank
boundaries. Each crossing of the boundary requires that
the processor first write a control bit to an output port
before accessing memory or 110 in the new bank. If program memory is being switched, programs should be organized to keep boundary crossings to a minimum.

7.0 CONTROL SIGNAL SUMMARY
Table 1 summarizes the instructions which activate the
various control outputs of the MCS®-48 processors. During all other' instructions these outputs are driven to the
active state.

2-8

EXPANDED MCS®·48 SYSTEM

Table 1. MCS®-48 Control Signals
Control
Signal
RD
WR
ALE
PSEN
PROG

The latched mode (INS, OUTL) is intended for use in the
single-chip configuration where BUS is not begin used as
an expander port. OUTL and MOVX instructions can be
mixed if necessary. However, a previously latched output
will be· destroyed by executing a MOVX instruction and
BUS will be left in the high impedance state. INS does
not put the BUS in a high impedance state. Therefore,
the use of MOVX after OUTL to put the BUS in a high
impedance state is necessary before an INS instruction
intended to read an external word (as opposed to the previously latched value).

When Active
During MOVX, A, @R or INs Bus
During MOVX @R, A or OUTL Bus
Every Machine Cycle
During Fetch of external program memory (instruction or immediate data)
During MOVD, A,P ANLD P,A MOVD
P,AORLDP,A

OUTL should· never be used in a system with external
program memory, since latching BUS can cause the next
instruction, if external, to be fetched improperly.

8.0 PORT CHARACTERISTICS

8.1 BUS Port Operations·

8.2 Port 2 Operations

The BUS port can operate in three different modes: as a
latched 110 port, as a bidirectional bus port, or as a program memory address output when external memory is
used. The BUS port lines are either active high, active
low, or high impedance (floating).

The lower half of Port 2 can be used in three different
ways: as a quasi-bidirectional static port, as an 8243 expander port, and to adddress external program memory.

PROGRAM MEMORY
SPACE
.-----'BFFH
I

I

:

MB1

I

8355
(2K)

:

I

I

I
I

I
:
MBO I - - - - - j 400H

EXTERNAL DATA
MEMORY SPACE

I
I

I ~~5
I

- - - - - - - - 300H
8155
RESIDENT
I
I 10
RESIDENT DATA
--(1K)-- 200H I -______---i
MEMORY
- - - - - - - - 100H ~--'-"":""-!
(64)
' - - - - - - ' OOOH 1--:-------1
SECTION
PROG.MEM
DATAMEM
8155 PORTS

8355 PORTS

ADDRESS

DESIGNATION

OOO-BFF
100-IFF
300
301
302
303
304
305
400
401
402
403

CMD/STATUS
PORTA
PORTB
PORTC
TIMER LOW
TIMER HI
PORTA
PORTB
DORA
DDR B

Figure 12. Memory Map for Three-Component MCS®-48 Family

2-9

EXPANDED MCSIiil-48 SYSTEM

viously latched will be automatically removed temporarily
'while address is present, then retored when the fetch is
complete. However, if lower Port 2 is used to communicate with ,iIIi 8243, previously latched 110 information
, will be removed and not restored. After
input from th~
8243~ P20-3 will be left in the input mode (ftoating).After
an output to the 8243, P20-3 will contain the value written,
AN~, or ORed' to the 8243 port.

In all c,ases' outputs are driven low by an active device
and,driven high momentarily by a low impedance device
and held high bY a high impedan~ device to vee.

an

The port may contain latched 110 data prjor to its use in
another mode without affecting operation of either:, If
lower, ,Port 2 (P20-3) is IIsed ,to output address for an
external program memory fetch. the 110 information pre-

1/0

1/0

8749H
8049AH'
8048AH
8748H
8035AHL
8039AHL

D
D

Figure 13.

MCSC!l~8

Expansion Capability

2·10

MCS®..,48 Instruction Set

3

MCS®-48 INSTRUCTION SET
1.0 INTRODUCTION

1.1 Data Transfers

The MCS®-48 instruction set is extensive for a machine
of its size and has been tailored to be straightforward and
very efficient in its use of program memory. All instructions are either one or two bytes in length and over 80%
are only one byte long. Also, all instructions execute in
either one or two cycles and over 50% of all instructions
execute in a single cycle. Double cycle instructions include all immediate instructions, and all 110 instructions.

As can be seen in Figure I the 8-bit accumulator is
the central point for all data transfers within the 8048.
Data can be transferred between the 8 registers of each .
working register bank and the accumulator directly, Le.,
the source or destination register is specified by the instruction. The remaining locations of the internal RAM
array are referred to as Data Memory and are addressed
indirectly via an address stored in either RO or R I of the
active register bank. RO and RI are also used to indirecly
address external data memory when it is present. Transfers
to and from internal RAM require one cycle; while transfers to external RAM require two. Constants stored in
Program Memory can be loaded directly to the accumulator and to the 8 working registers. Data can also be
transferred directly between the accumulator and the on-

The MCS-48 microcomputers have been designed to handle arithmetic operations efficiently in both binary and
BCD as well as handle the single-bit operations required
in control applications. Special instructions have also been
included to simplify loop counters, table look-up routines,
and N-way branch routines.

r----------l
I
I
I

I

PROGRAM
MEMORY
(#DI\.TA)

I
I

DATA
MEMORY
MOV
WORKING REG

ADD
MOV
MOVP
MOVP3
ANL
ORL
XRL

I

MOV
ADD
ANL
ORL
XRL
XCH

I

EXTERNAL
EXPANDER /111-_=---'-', ,....:>"-''----------....:..'-----....:..'-,
1/0 PORTS
/,:=:-=,.-1-""
MEMORY
4-7
~_ _ _~~_ _~~---~---~~cr-~~r -,,~~. <::X

2.4 - - - . . . . , .

0.45

,...._ _ _ _ _ _ _ _ _ _ _ __

" ' . - -_ _

270161-3
A.C. Testing: Inputs are driven at 2.4V fora Logic "1" and 0.45V for a logic "0". Output timing measurements are made at2.0V for logic "1"
and O.BV for a logic "0".

4·4

inter

8243

WAVEFORMS

PROG

~~

PORT2

______________ IK ________________

~

FLOAT

FLOAT

PORT 2

IpO

PORTS 4·7

OUTPUT
VALID

PREVIOUS OUTPUT VALlO

lIP

PORTS 4·7

INPUT VALlO

ICS

ICS

270161-4

4-5

inter

8243

125

100

C

!

:;
5}

~

...Z
"'.
'"'"

75

III

GUARANTEED WORST CASE
CURRENT SINKING CAPABILITIES
OF ANY 1/0 PORT PIN YO. TOTAL
SINK CURRENT OF ALI. PINS

..
U

Z

...iii

50

~

...0

25

4

10

11

13

12

MAXIMUM SINK CURRENT ON ANY PIN @ .45V
MAXIMUM 101. WORST CASE PIN (mA)

270161-5

Figure 3. 8243 Current Sink Capability
NOTE:
A 10 to 50 Kn pullup resistor to + 5V should be
added to 8243 outputs when driving to 5V CMOS
directly.

Sink Capability .
The 8243 can sink 5 rnA @ 0.45V on each of its 16
liD lines simultaneously. If, however, all lines are
not sinking simultaneously or all lines are not fully
loaded, the drive capability of any individual line increases as is shown by the accompanying curve.

Example: This example shows how the use of the
20 rnA sink capability of Port 7 affects the
sinking capability of the. other liD lines.
An 8243 will drive the following loads
simultaneously.

For example, if only 5 of the 16 lines are to sink
CUii6nt at one time, the cur.;e ShO\NS that· each of
those 5 lines is capable of sinking 9 rnA @ 0.45V (if
any lines are to sink 9 rnA the total IOL must not
.
exceed 45 rnA or five 9 rnA loads).

2 loads-20 rnA
8 10ads-4 rnA

6 loads-3.2 rnA

Example: How many pins can drive 5 TIL loads
(1.6 rnA) assuming remaining pins are un~
,loaded?
IOL

@

@

1V (Port 7 only)

0.45V
@

0.45V

Is this within the specified limits?
EIOL = (2 X 20)
= 91.2 rnA.

= 5 x 1.6 rnA = 8 rnA

+

(8

x

4)

+

(6

x

3.2)

EIOL = 60 rnA from curve
# pins = 60 rnA -7- 8 rnA/pin = 7.5 = 7

From the curve': for loi. = 4 rnA, EIOL ~
93 rnA. Since 91.2 rnA < 93 rnA the loads
are within specified limits.

In this case, 7 lines can sink 8 rnA for a
total of 56 rnA. This leaves 4 rnA sink current capability which can be divided in any
way among the remaining 8 liD lines of
the 8243.

Although the 20 rnA @ 1V loads are used
in calculating eIOL' it is the largest current
. required @ 0.45V which determines the
maximum allowable eIOL.

4-6

inter

8243

-=CS

liD
PROG
TEST
INPUTS

8048

P4

110

P5

110

PROG

8243
P6

4

110

DATA IN
P2

P20-P23

P7

110

270161-6

Figure 4. Expander Interface

P20·P23

~'-_---JX'--ADDRESS (4·8ITSI

__--J)>---

BITS 3,2
00 } READ
01
WRITE
10 OR
11
AND

BITS 1,0
00
01 } PORT
10 ADDRESS
11

DATA (4·8ITSI

270161-7

Figure 5. Output Expander Timing

PORT 1

0048

PORT2
PROG~--------------+---------------~--------~------~--------------~

270161-8.

Figure 6. Using Multiple 8243'5

4-7

P8748H/P8749H
8048AH/8035AHL/8049AH/8039AHL/8050AH/8040AHL
HMOS SINGLE-COMPONENT 8-BIT
PRODUCTION MICROCONTROLLER

•
•
•
•
•

Programmable ROMs Using 21V
• Easily
Memory and I/O
• Up to 1Expandable
IJ-s Instruction Cycle All
• Instructions 1 or 2 Cycles

High Performance HMOS II
Interval Time/Event Counter
Two Single Level Interrupts
Single 5-Volt Supply
Over 96 Instructions; 90% Single Byte

~36

The Intel MCS®-48 family are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS process.

The family contains 27 I/O lines, an 8-bit timer/counter, and on-board oscillator/clock circuits. For systems
that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcontrollers are available in both masked ROM and ROMless versions as well as a neW version,
The Programmable ROM. The Programmable ROM provides the user with the capability of a masked ROM
while providing the flexibility of a device that can be programmed at the time of-requirement and to the desired
data. Programmable ROM's allow the user to lower inventory levels while at the same time decreasing delay
'
,times and code risks.
These microcomputers are d,esigned to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting of mostly, single byte instructions and no instruc'
tions over 2 bytes in length.
Memory

RAM STANDBY

B050AH

Device

4KxBROM

256xBRAM

yes

B049AH

2KxBROM

12BxBRAM

yes

B04BAH

1KxBROM

64xBRAM

yes

B040AHL

None

256xBRAM

yes

B039AHL

None

12BxBRAM

yes

B035AHL

None

64xBRAM

yes

PB749H

2K x B Programmable ROM

12BxBRAM

no

PB74BH

1K x B Programmable ROM

64xBRAM

no

• CLOCK

Internal

I I

PROGRAM

I,

r~Po.RT

DATA

XTALt

P

,

270053-1

Figure 1. Block Diagram
270053-2

Figure 2. Logic Symbol

4-8

November 1987
Order Number: 270053-002

intJ

MCS®-48

I~ ~ ~

wee

I~
en a::
TO

0

r--

CD

II)

0 0z u
- ~
~ a..
~ D~
....
> ~

Vee

,

T1
P27
P26
P2S
P2'
PI7
P'6

XTAL 1
XTAL2
RESET'

SS
INT
EA

AD

P2.4
PL7
PI.6

EA

Rii
PSEN

p,s

PSEN

•

iNT

WR

WR

Ne

ALE

B049AH/B039AHL
B050AH/B040AHl
44- PIN
Plee

PI.S
PI.4
Ne

ALE

DBO
DB,
DB2
DB3
DB.
DBS
DB6
DB7

PI.3

090
091
092

PI.2
PI.I

Top View
looking down on PC Boord

PCO
VOO

093

VSS " - _ - - - ' ' ' '

270053-3
270053-14

Figure 3. Pin Configuration

Figure 4. Pad Configuration
Table 1. Pin Description

Symbol

Pin
No.

Function

Device

VSS

20

Circuit GND potential.

All

VDD

26

+ 5V during normal operation.

All

low power standby pin.

8048AH
8035AHl
8049AH
8039AHl
8050AH
8040AHl

Programming power supply (+ 21 V).

P8748H
P8749H

+ 5V during operation and programming.

Vee

40

Main power supply;

PROG

25

Output strobe for 8243 110 expander.

All
All

Program pulse ( + 18V) input pin During Programming.

P8748H
P8749H

P10-P17
Port 1

27-34

8-bit quasi-bidirectional port.

All

P20-P23
P24-P27
Port 2

21-24
35-38

8-bit quasi-bidirectional port. P20-P23 contain the four high order
program counter bits during an external program memory fetch and
serve as a 4-bit 1/0 expander bus for 8243.

All

DBO-DB7
BUS

12-19

True 'bidirectional port which can be written or read synchronously
using the RD, WR strobes. The port can also be statically latched.
Contains the 8 low order program counter bits during an external
program memory fetch, and receives the addressed instruction under
the control of PSEN. Also contains the address and data during an
external RAM data store instruction, under control of ALE, RD, and
WR.

All

Input pin testable using the conditional transfer instruction JTO and
JNTO. TO can be designated as a clock output using ENTO ClK
instruction.

All

Used during programming.

P8748H
P8749H

TO

1

4-9

intJ

MCS®·48

Table 1. Pin Description (Continued)
Symbol
T1

Pin
No.
39

INT

6

RD

S

RESET

4

Function

Device

Input pin testable using the JT1, and JNT1 instructions. Can be
designated the timer/counter input !,Ising the STRT CNT instruction.
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is
disabled after a reset. Also testable with conditional jump instruction.
(Active low) interrupt must remain low for at least 3 machine cycles for
proper operation.
Output strobe activated during a BUS read. Can be used to enable
data onto the bus from an external device.
Used as a read strobe to external data memory. (Active low)
Inputwhich is used to initialize the processor. (Active low) (Non TTL
VIH)
Used during power down.

I.

.

Used during programming.
Used during ROM verification.

WR

10

ALE

11

PSEN

9

SS

5

Output strobe during a bus write. (Active low)
Used as write strobe to external data memory.
Address latch enable. This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into external data and
program memory.
Program store enable. This output occurs only during a fetch to
external program memory. (Active low)
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruction.
(Active low) Used in sync mode.

All
All

All

All
S04SAH
S035AHL
S049AH
S039AHL
S050AH
S040AHL
PS74SH
PS749H
S04SAH
PS74SH
S049AH
PS749H
S050AH
All
All

All
All
S04SAH
8035AHL

EA

7

External access input which forces all program memory fetches to
reference external memory. Useful for emulation and debug. (Active
high)
Used during (1SV) programming.
Used during ROM verification (12V).

XTAL1

2

XTAL2

3

One side of crystal input for internal 'oscillator. Also input for external
source. (Non TTL VIH)
Other side of crystal input.
4-10

S049AH
S039AHL
S050AH
S040AHL
All

PS74SH
PS749H
S04SAH
S049AH
S050AH
All
All

MCS®-48

Table 2. Instruction Set
Accumulator
Mnemonic
ADDA,R
ADDA,@R

Input/Output
Description

Add register to A
Add data memory
toA
ADD A, #data Add immediate to A
AD DC A, R
Add register with
carry
AD DC A, @R
Add data memory
with carry
ADDC A, # data Add immediate with
carry
ANLA, R
And register to A
ANLA,@R
And data memory
toA
ANLA, #data And immediate to A
ORLA, R
Or register to A
ORLA,@R
Or data memory
toA
ORLA, #data Or immediate to A
XRLA, R
Exclusive or register
toA
XRLA, @R
Exclusive or data
memory to A
XRLA, #data Exclusive or
immediate to A
INCA
IncrementA
DECA
Decrement A
CLRA
Clear A
CPLA
Complement A
DAA
Qecimal adjust A
SWAP A
Swap nibbles of A
RLA
Rotate A .left
RLCA
Rotate A left
through carry
RRA
Rotate A right
RRCA
Rotate A right
through carry

Bytes Cycles
1
1

1
1

2

2

1

1

1

1

2

2

1
1

1
1

2

2

1
1

1
1

2

2

1

1

1

1

2

2

1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

Mnemonic

Bytes Cycles

Description

Input port to A
Output A to port
And immediate to
port
ORL P, #data
Or immediate to
port
Input BUS to A
INS A, BUS
OUTLBUS,A
Output Ato BUS
ANL BUS, #data And immediate to
BUS
ORL BUS, # data Or immediate to
BUS
MOVDA, P
Input expander port
toA
MOVDP,A
Output A to
expander port
ANLD P,A
And A to expander
port
ORLDP,A
Or A to expander
port

INA,P
OUTLP,A
f.NL P, #data

2

2
2
2

2

2

2

2
2
2

2

2

1
1

2
2
2
2

Registers
Mnemonic
INCR
INC@R
DECR

Description
Increment register
Increment data memory
Decrement register

Bytes Cycles
1

1

Branch
Mnemonic

Description

JMP addr
Jump unconditional
JMPP@A
Jump indirect
DJNZ R, addr Decrement register
and skip
JCaddr
Jump on carry = 1
JNC addr
Jump on carry = 0
JZaddr
Jump on A zero
JNZaddr
Jump on A not zero
JTO addr
Jump on TO = 1
JNTO addr
Jump on TO = 0
Jump on T1 = 1
JT1 addr
JNT1 addr
JumponT1 = 0
JFO addr·
Jump on FO = 1
JF1 addr
Jump on F1 = 1
JTF addr
Jump on timer flag
JNI addr
Jump on INT = 0
JBb addr
Jump on accumulator
bit

1
1

4-11

Bytes Cycles

2
2

2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

1

MCS®-48

Table 2. Instruction Set (Continued)
.-----~------~------------------~

r--------------------------------~

Subroutine
Mnemonic

Description

CALLaddr
RET
RETR

Jump to subroutine
Return
Return and restore
status

Timer/Counter

Bytes Cycles

2

2
2
2

1
1

Flags
Mnemonic
CLRC
CPLC
CLRFO
CPLFO
CLR F1
CPLF1

Description

1
1
1
1
1
1

1
1
1
1
1
1

Mnemonic

Description

Move register to A
Move data memory
toA
MOVA, #data Move immediate to
A
MOVA,A
Move A to register
MOV@A,A
Move A to data
memory
MOVR, #data Move immediat~ to
register
MOV @A, #data Move immediate to
data memory
MOVA,PSW
MovePSWtoA
MOVPSW,A
MoveAtoPSW
XCHA, A
Exchange A and
register
XCHA,@R.
Exchange A and
data memory
XCHDA,@A
Exchange nibble of
A and data memory
MOVXA,@A
Move external data.
memoiytoA
MOVX@A,A
Move A to external
data memory
MOVPA,@A
Move to A from
current page
MOVP3A,@A Move to A from
page 3

1
1

2

2

2

2

2

2

Mnemonic

1
1
1
1
1

Description

1
1
1
1
1

Bytes Cycles

Enable external
. interrupt
DISI
Disable external
interrupt
Select register bank 0
SELABO
Select register bank 1
SELAB1
SELMBO Select memory bank 0
SELMB1
Select memory bank 1
ENTOCLK Enable clock output
onTO

2
2
2
1.

Bytes Cycles

EN I

Bytes Cycles
1
1

Aead timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/
counter interrupt
Disable timer/
counter interrupt

Control

Data Moves

MOVA,A
MOVA,@R

Description

MOVA, T
MOVT,A
STATT
STATCNT
STOP TCNT
EN TCNTI
DIS TCNTI

Bytes Cycles

Clear carry .
Complement carry
Clear flag 0
, Complement flag 0
Clear flag 1
Complement flag 1

Mnemonic

2

4-12

1

1

Mnemonic

Description

Bytes

Cycles

NOP

No operation

1

1

MCS®·48

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

+ 70·C
+ 150·C

Case Temperature Under Bias ...•..• O·C to
Storage Temperature .•.•..•... - 65°C to

Voltage on any Pin with Respect
to Ground ...................... - 0.5V to

+ 7V

Power Dissipation .............•.....•...... 1.5W

NOTICE: Specifications contained within the'
following tables are subject to change.

D.C. CHARACTERISTICS
Symbol

TA

=

O·C to

+ 70·C; Vee =

Voo

limits

Parameter
Min

Typ

=

5V

Unit

± 10%; Vss = OV
Test Conditions

Device

Max

-0.5

0.8

V

All

Input Low Voltage
(RESET, X1, X2)

-5

0.6

V

All

VIH

Input High Voltage
(All Except XTAL 1,
XTAL2, RESET)

2.0

Vee

V

All

VIH1

Input High Voltage
(X1, X2, RESET)

3.8

Vee

V

All

VOL

Output Low Voltage
(BUS)

0.45

V

IOL

=

2.0 rnA

All

VOL1

Output Low Voltage
(RD, WR, PSEN, ALE)

0.45

V

IOL

=

1.8 rnA

All

VOL2

Output Low Voltage
(PROG)

0.45

V

IOL

=

1.0 rnA

All

VOL3

Output Low Voltage
(All Other Outputs)

0.45

V

IOL

=

1.6 rnA

All

VOH

Output High Voltage
(BUS)

2.4

V

IOH = - 400 /LA

All

VOH1

Output High Voltage
(RD, WR, PSEN, ALE)

2.4

V

IOH

=

-100

!LA

All

VOH2

Output High Voltage
(All Other Outputs)

2.4

V

IOH

=

-40/LA

VIL

Input Low Voltage (All
Except RESET, X1, X2)

VIL1

4-13

All

inter

MCS®-48

D.C. CHARACTERISTICS
Symbol

TA

=

0·Cto+70·C;Vee

Parameter
Min
Leakage Current
(T1,INT) ,

ILl
IUl

Input Leakage Current
(P10-P17, P20-P27,
EA, SS)
,

IU2

Input Leakage Current
RESET

ILO

Leakage Current
(BUS, TO) (High
Impedance State)

100

Voo Supply Current
(RAM Standby)

100 +

=

Limits
Typ

Voo

=

5V ±10%;Vss= OV(Continued)

Unit,

Test Conditions

Device

Max

s

±10

p.A

Vss

-500

p.A

Vss + 0.45

-SOO

p.A

Vss

±10

p.A

Vsss VIN sVee

S

5

,mA'

B04BAH
BOS5AHL

4

7

mA

8049AH
BOS9AHL

5

10

mA

SO

65

mA

B048AH
BOS5AHL

35

70

mA

B049AH
BOS9AHL

40

BO

mA

B050AH
B040AHL

SO

100

mA

PB74BH

50

110

mA

PB749H

, ,2.2

5.5

V

2.2

5.5

V

2.2

5.5

\I

All

VINs Vee

,

-10

Total Supply Current"

s

VIN

s

s

VIN

s

All

Vee

All

S.B

All

8050AH
B040AHL

.,;

lee

Voo

'Icc

+

RAM Standby Voltage

I

v

Standby Mode Reset
sVILl

B04BAH
8035AH
B049AH
BOS9AH

I

8050AH
B040AHL

100 are measured with all outputs in their high impedance state; RESET low; 11 MHz crystal applied; INT, 55, and EA floating.

I

intJ

MCS®-48

A.C. CHARACTERISTICS
Symbol

TA

=

O·Cto +70·C;Vcc

Parameter

=

voo

=

5V ±10%;Vss
11 MHz

f (t)
(Note 3)

Min

Max
1000

=

ov

Unit

Conditions
(Note 1)

ns

(Note 3)

t

Clock Period

1 /xtal freq

90.9

tLL

ALE Pulse Width

3.5t-170

150

ns

tAL

Addr Setup to ALE

2t-110

70

ns

tLA

Addr Hold from ALE

tCC1

Control Pulse Width (RD, WR)

tCC2

Control Pulse Width (PSEN)

tow

Data Setup before WR

two

Data Hold after WR

tOR

Data Hold (RD, PSEN)

t-40

50

ns

7.5t-200

480

ns

6t-200

350

ns

6.5t-200

390

ns

t-50

40

1.5t-30

0

ns
110

ns

tR01

RD to Data in

tR02

PSEN to Data in

tAW

Addr Setup to WR

tA01

Addr Setup to Data (RD)

10.5t-220

tA02

Addr Setup to Data (PSEN)

7.5t-200

tAFC1

Addr Float to RD, WR

tAFC2

Addr Float to PSEN

tLAFC1

ALE to Control (RD, WR)

tLAFC2

ALE to Control (PSEN)

tCA1

Control to ALE (RD, WR, PROG)

tCA2

Control to ALE (PSEN)

tcp

Port Control Setup to PROG

1.5t-80

50

ns

tpc

Port Control Hold to PROG

4t-260

100

ns

tpR

PROG to P2 Input Valid

tpF

Input Data Hold from PROG

top
tpo
tpp

PROG Pulse Width

tpL

Port 2 110 Setup to ALE

6t-170

375

ns

4.5t-170

240

ns

5t-150

(Note 2)

300

ns'
730

ns

460

ns

2t-40

140

ns

(Note 2)

0.5t-40

10

ns

(Note 2)

3t-75

200

ns

1.5t-75

60

ns

t-65

25

ns

4t-70

290

ns

8.5t-120

650

ns

140

ns

1.5t

0

Output Data Setup

6t-290

250

ns

Output Data Hold

1.5t-90

40

ns

10.5t-250

700

ns

4t-200

160

ns

15

tLP

Port 2 110 Hold to ALE

0.5t-30

tpv

Port Output from ALE

4.5t+ 100

tOPRR

TO Rep Rate

3t

270

tCY

Cycle Time

15t

1.36

ns
5.0

ns

15.0

p.s

ns

NOTES:

1. Control outputs: CL = 80 pF. BUS Outputs: CL = 150 pF.
2. BUS High Impedance Load 20 pF
3. f(t) assumes 50% duty cycle on X1, X2. Max clock period is for a 1 MHz crYstal input.

4-15

inter

MCS®·48

WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM
MEMORY

READ FROM EXTERNAL DATA MEMORY

-..j .LAFC1rALE

RD
'DR
FLOAT.NG

270053-5

INPUT AND OUTPUT FOR A.C. TESTS

WRITE TO EXTERNAL DATA MEMORY

...

2.4Y -----X~.Q TEST
OA5V----J. .0.8""

POINTSt'2.0~
.... 0 . 8 " - - - -

270053-7
A.C. testing inputs are driven at 2.4V lor a logic "1" and 0,45V lor
a logic "0". Output timing measurements are made at 2.0V lor a
logic "1" and 0.8V lor a logic "0".

270053-6

PORT 1/PORT 2 TIMING

ALE
PSEN

I

I

P2~-23

OUTPUT

~

P24-21
P10-17
OUTPUT

__

r-----P-~~R-T-~-~--i-O-A--'A--~\lr-h-·E-W-·F-.U----~-O-A-~~--

PCH
~----------J

PORT 24-21. PORT 10-17 DATA

'LP
EXPANDER
PORT
OUTPUT

---l

I~

I

··LA---...........-

,..----'------->.1 r------;,

;-------' -_ _ _ _ _ _...J

I

'NPUT

I

"
r-~-~

I

I~'
'PF

i---

I
~--PC-H--~I

OUTPUT DATA

'PR~

j-.cp+.PC.j ' - - _ . J I
PROG

'-'CA1

,'DP-----r1

PCH

EXPANDER
PORT

NEW PORT 9ATA

I

---.,.--------------....,~r-.PP_r_
270053-8

4-16

MCS®-48

CRYSTAL OSCILLATOR MODE

CERAMIC RESONATOR MODE

Cl

~,-C_2_--,L, ,- -"-_~_~_!- -:2:-1
__

-:b

Cl

f------""""""f"---=2'-l

~(
XTALl

J-

XTAL2

C3

XTALl

1-11

C""""~ ~

XTAL2

C3

270053-9
Cl = 5 pF ±% pF + (STRAY < 5 pF)
C2 = (CRYSTAL + STAY) < 8 pF
C3 = 20 pF ±1 pF + (STRAY < 5 pF)
Crystal series resistance should be less than 3011 at 11 MHz; less
than 7511 at 6 MHz; less than 18011 at 3.6 MHz.

270053-10

DRIVING FROM EXTERNAL SOURCE
+SV

47011

»-.----'=-1 XTAL1
+5V

TTL OPEN
COLLECTOR
GATES

47011
'----..L---;;1 XTAL2

270053-11
For XTALl and XTAL2 define "high" as voltages above 1.6V and
"low" as vOltages below 1.6V. The duty cycle requirements for
externally driving XTAL 1 and XTAL2 using the circuits shown
above are as follows: XTAL1 must be high 35-65% of the period
and XTAL2 must be high 35-65% of the period. Rise and fall times
must be faster than 20 ns.

4-17

inter

MCS®-48

PROGRAMMING AND VERIFYING THE
P8749H/48H PROGRAMMABLE ROM

WARNING:
An attempt to program a missocketed P8749H/48H
will result in severe damage to the part. An indication
of a properly socketed part is the appearance of the
ALE clock output. The lack of this clock may be
used to disable the programmer.

Programming Verification
In brief, the programming process consists of: activating the program mode, applying an address,
latching the address, applying data, and applying a
programming pulse. Each word is programmed completely before moving on to the next and is followed
by a verification step. The following is a list of the
pins used for programming and a description of their
functions:

Pin

The ProgramlVerify sequence is:
1. Voo = 5V, Clock applied or internal oscillator
operating, RESET = OV, TO = SV, EA = SV,
BUS and PROG floating. P10 and P11 must be
tied to ground.
2. Insert P8749H/48H in programming socket
3. TO = OV (select program mode)

Function

XTAL1
XTAL2
RESET
.... ...
TO
EA
BUS

4. EA

Clock Input (3 to 4.0 MHz)

= 18V (activate program mode)

S. Address applied to BUS and P20-22
6. RESET = SV (latch address)

Initialization and Address Latching
Selection of Program or Verifying Mode
Activation of ProgramlVerify Modes
Address and Data Input
'Data Output During Verify
P20-P22 Address Input
Programming Power Supply
Voo
Program Pulse Input
PROG
,

7. Data applied to BUS
8. Voo = 21V (programming power)
9. PROG = Vee or float followed by one SO ms
pulse to 18V
10. Voo = 5V
11. TO

= SV (verify mode)

12. Read and verify data on BUS
13. TO

= OV

14. RESET

= OV and repeat from step S

1S. Programmer should be at conditions of step 1
when P8749H/48H is removed from socket.

NOTE:
Once programmed the P8749H/48H cannot be
erased.

4-18

MCS®-48

A.C. TIMING SPECIFICATION FOR PROGRAMMING P8748H/P8749H ONLY
TA

=

25°C ±5°C; VCC

=

Symbol

5V ±5%; VOO

=

21 ±0.5V

Parameter

Min

tAW

Address Setup Time to RESET

4tCY
4tcy

Max

Unit

tWA

Address Hold Time After RESET

tow

Data in Setup Time to PROG

4tCY

two

Data in Hold Time After PROG

4tCY

tpH

RESET Hold Time to Verify

4tCY

tVOOW

Voo Hold Time Before PROG

0

1.0

ms

tvoOH
tpw

Voo Hold Time After PROG

0

1.0

ms

Program Pulse Width

50

60

ms

trw

TO Setup Time for Program Mode

4tCY

tWT

TO Hold Time After Program Mode

4tcy

too

TO to Data Out Delay

tww

RESET Pulse Width to Latch Address

tr, tl

Voo and PROG Rise and Fall Times

0.5

100

J.Ls

tCY

CPU Operation Cycle Time

3.75

5

J.Ls

tRE

RESET Setup Time before EA

4tCY

Test Conditions

4tCY
4tcy

NOTE:

II Test 0 is high, too can be triggered by RESET.

D.C. CHARACTERISTICS FOR PROGRAMMING P8748H/P8749H ONLY
TA

=

25°C ±5°C; Vcc

Symbol

=

5V ±5%; Voo

=

21 ±0.5V

Parameter

Min

Max

Unit

VOOH

Voo Program Voltage High Level

20.5

21.5

V

VOOL

Voo Voltage Low Level

4.75

5.25

V

VPH

PROG Program Voltage High Level

17.5

18.5

V

VPL

PROG Voltage Low Level

4.0

EA Program or Verify Voltage High Level

17.5

Vcc
18.5

V

VEAH
100

Voo High Voltage Supply Current

20.0

rnA

IpROG

PROG High Voltage Supply Current

1.0

rnA

lEA

EA High Voltage Supply Current

1.0

rnA

4-19

V

Test Conditions

MCS®·48

SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY
INITIAL ROM DUMP CYCLE

SUBSEQUENT ROM DUMP CYCLES

ALE
(NOTE 1)

E« ....:J.

I

: (INPUT)
I
I

,,

I

DB----i

ROM DATA

.....-(~IN:-::P::-U':':T::-)---'

H
I

H

ADDRESS

(OUTPUT)

,

ADDRESS
(INPUT)

~----------------­
(OUTPUT)'

I

~,

RESET _ _ _ _ _ _....

I

.

(INPUT)

.

! - - i-

,,

-

-

,
PZ~PZ3---_L_ _ _ _A_DD_R_E_S_S_ _ _~~~---A-D-D-RE-S-S----Jr--____________
I

: (INPUT)

270053-12
Vee = Veo
Vss = OV

50H
ADDR
ADDR

Al0
All

= +5V

NOTE:

ALE is function of X1, X2 inputs.

COMBINATION PROGRAM/VERII=Y MODE (PROGRAMMABLE ROMS ONLY)
VEAH
EA
Vee

TO

---+---'
I_ _ _ _ _ _ _

PROGRAM--------II--~VERIFY-~~---PROGRAM-

Vee

VIL1
Vee

RESET
VIL1

DBa-DB7

iAw-+i--t--i-1 twA

J --.

-

-tcc~

DATA TO BE
PROGRAMMED VALID

NEXT
ADDRESS

LAST
ADDRESS

VDDH - - - - - - - - - - - VDD
.Vee------------

lOw

VPH -----------------+-t-i--_\.
PROG
VPL---------------

------,-- --.-----------270053-13

4-20

inter

D8748H/D8749H
HMOS-E SINGLE-COMPONENT 8-BIT MICROCOMPUTER
with 8080/8085 Peripherals
• Compatible
Easily Expandable Memory and 110
• Up to 1.35 p,s Instruction Cycle;
• All Instructions 1 or 2 Cycles

Performance HMOS-E
• High
Interval Timer/Event Counter
• Two Single Level Interrupts
• Single 5-Volt Supply
• Over 96 Instructions; 90% Single Byte
•

The Intel D8749H/D8748H are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS-E process.
The family contains 27 I/O lines, an 8-bit timer/counter, on-chip RAM and on-board oscillator/clock circuits.
For systems that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting mostly of single byte instructions and no instructions over 2 bytes in length.
Device

Internal Memory

D8749H

' 2Kx8 EPROM

D8748H

1Kx8 EPROM

I
I

128 x8 RAM
64x8 RAM

PORT
I

PORT

D8748H

2

D87-49H

READ
WRITE

PROGRALi
STORE

ENABLE
ADDRESS
LATCH

. ENABLE
PORT
EXPANDER
STROBE

210983-1

Figure 1.
Block Diagram

210983-2

Figure 2.
Logic Symbol

4-21

October 1987
Order Number: 210983-003

D8748H/D8749H

Vee

Tl
P27
P26

RESET

55

P25
P2.
P17

Ro

P16

PSEN

P15

Wi!

P14

08.

P12

DB,

P11

P13

08 2

Pl.

DB.

VOO

PROG

P23
P22
P21

DB7
VSS

210983-3

Figure 3. Pin Configuration
. Table 1. Pin Description (40-Pin DIP)
Symbol
Vss
VDD

Pin No.
20
26

Function
Circuit GND potential.

+ 5V during normal operation.
Programming power supply (+ 21 V).

Vee
PROG

40
'25

Main power supply;

+ 5V during operation and programming.

Output strobe for 8243 I/O expander.
Program pulse ( + 18V) input pin during programming.

P10-P17
Port 1

27-34

8·bit quasi·bidirectional port.

P20-P23

21-24

8·bit quasi-bidirectional port. P20-P23 contain the four high order program
counter bits during an external program memory fetch and serve as a 4·bit
I/O expander bus for 8243.

P24-P27
Port 2

35-38

DBO-DB7

·12-19

~II""

True bidirectional port which can be written or read synchronously using the

RD, 'yAJR stiobes. The port can also be statically !atc.hed. Contains the 8 !O\&,

OUi:)

order program counter bits during an eXternal program memory tetch, and
receives the addressed instruction under the control of PSEN. Also contains
the address and data du~ an external RAM data store instruction, under
control of ALE, RD; and WR.
TO

1

Input pin tesliible using the conditional transfer instructions JTO and JNTO.
TO can be designated as a clock output using ENTO CKL instruction.

T1

39

Input pin testable using the JT1, and JNT1 instructions. Can be designated
the timer/counter input using the STRT CNT instruction.

INT

6

Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is
disabled after a reset. Also testable with conditional jump instruction. (Active
low) interrupt must remain low for at least 3 machine cycles for proper
operation.

RD

8

Output strobe activated during a BUS read. Can be used to enable data onto
the bus from an external device.
Used as a read strobe to external data memory. (Active low)

Used during programming.

4·22

intJ

D8748H/D8749H

Table 1 Pin Description (40-Pin DIP) (Continued)
Symbol

Pin No.

RESET

4

Input which is used to initialize the processor. (Active low) (Non TTL VI H)

WR

10

Output strobe during a bus write. (Active low)
Used as write strobe to external data memory.

ALE

11

Address latch enable. This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into external data and program
memory.

PSEN

9

Program store enable. This output occurs only during a fetch to external
program memory. (Active low.)

SS

5

Single step input can be used in conjunction with ALE to "single step" the
processor through each instruction.

EA

7

.External access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug. (Active high.)

XTAL1

2

One side of crystal input for internal oscillator. Also input for external source.
(Non TTL VIH.)

XTAL2

3

Oth~r

Function
Used during programming.

Used during (1 BV) programming.

side of crystal input.
Table 2. Instruction Set

Mnemonic
Description
ACCUMULATOR
Add register to A
ADD A, R
ADDA,@R
Add data
memory to A
ADDA, #data
Add immediate
toA
ADDCA,R
Add register with
carry
ADDCA,@R
Add data
memory with
carry
ADDC A, #data Add immediate
with carry
ANLA,R
And register to A
ANLA,@R
And data
memory to A
ANLA, #data
And immediate
toA
ORLA, R
Or register to A
ORLA,@R
Or data memory
toA
ORLA, #data
Or immediate to
A
XRLA, R
Exclusive or
register to A
XRLA,@R
Exclusive or
data memory to
A
XRLA, #data
Exclusive or
imniediate to A

Bytes

Cycles

2

2

2

2

2

2

Description
Mnemonic
ACCUMULATOR (Continued)
IncrementA
INCA
DECA
Decrement A
Clear A
GLRA
GPLA
Compleinent A
DAA
Decimal adjust A
SWAP A
Swap nibbles of
A
RLA
Rotate A left
RLCA
Rotate A left
through carry
RRA
Rotate A right
RRGA
Rotate A right
through carry
INPUTIOUTPUT
INA,P
OUTLP, A
ANLP, #data
ORLP, #data

2

2

INSA,BUS
OUTLBUS,A
ANL BUS, #data
ORL BUS, #data

2

MOVDA, P

2

4-23

Input port to A
Output A to port
And immediate
to port
Or immediate to
port
Input BUS to A
Output A to BUS
And immediate
to BUS
Or immediate to
BUS
Input expander
port to A

Bytes

Cycles

1
1
2

2

2

2

1
1
2

2
2
2

2

2

2
2

2

inter

D8748H/D8749H

~OOjgILOIMIOOO£OOW

Table 2. Instruction Set (Continued)
Mnemonic
Description
INPUTIOUTPUT (Continued)
MOVDP,A
Output A to
expander port
ANLDP,A
And A to expander
port
ORLDP,A
Or A to expander
port
REGISTERS
INCR
INC@R

DECR
BRANCH
JMPaddr
JMPP@A
DJNZR,addr
JCaddr
JNCaddr
JZaddr
JNZaddr
JTOaddr
JNTOaddr
JT1 addr
JNT1 addr
JFOaddr
JF1 addr
JTFaddr
JNI addr
JBb addr

SUBROUTINE
CALLaddr
RET
RETR

FLAGS
CLRC
CPLC
CLRFO
CPLFO
CLRF1
CPLFI
DATA MOVES
MOVA,R
MOVA,@R

MOVA, "'data

Bytes

Mnemonic
Description
DATA MOVES (Continued)
MOVR,A
Move A to register
Move A to data
.MOV@R,A
memory
MOVR, #data
Move immediate to
register
MOV @R, "'data Move immediate to
data memory
MOVA,PSW
MovePSWtoA
MOVPSW,A
MoveAtoPSW
XCHA, R
Exchange A and
register
XCHA,@R
Exchange A and
data memory
XCHDA,@R
Exchange nibble
of A and register
MOVXA,@R
Move external
data memory to A
MOVX@R,A
Move A to external
data memory
MOVPA,@A
Move to A from
current page
MOVP3A,@A
Move to A from
page 3

Cycles

2
2
1.

2

Increment register
Increment data
memory
Decrement register
Jump unconditional
Jump indirect
Decrement register
and skip
Jump on carry = 1
Jump on carry = 0
Jump on A zero
Jump ·on A not zero
Jump onTO = 1
Jump on TO = 0
JumponT1 = 1
JumponT1 = 0 .
Jump on FO = 1
JumponF1 = 1
Jump on timer flag
Jump on INT = 0
Jump on
accumulator bit

Jump to subroutine
Return
Return and restore
status

2
1
2

2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

2
1
1

2
2
2

TIMER/COUNTER
Read
MOVA,T
timer/counter
MOVT,A
Load
timer/counter
Start timer
STRTT
STRTCNT
Start counter
STOP TCNT
Stop timer/counter
EN TCNTI
Enable timer/
counter interrupt
DIS TCNTI
Disable timer!
counter interrupt
CONTROL
ENI
D!S!

Clear carry
Complement carry
Clear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
Move register to A
Move data memory
toA
Move immediate
toA

SELRBO
1
1
1

SELRB1
SELMBO
SELMB1
ENTOCLK

2

2
NOP

4-24

Enable external
interrupt
Disable external
interrupt
Select register
bank 0
Select register
bank 1
Select memory
bank 0
Select memory
bank 1
Enable clock
output on TO
No operation

Bytes Cycles

2

2

2

2

2
2
2
2

inter

087 48H/087 49H

'Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

+ 70°C
+ 150°C

Ambient Temperature Under Bias .... O°C to
Storage Temperature .......... - 65°C to

Voltage On Any Pin With Respect
to Ground ...................... - 0.5V to

+ 7V

Power Dissipation ....................... 1.0 Watt

NOTICE Specifications contained within the
fol/owing tables are subject to change.

D.C. CHARACTERISTICS

TA

=

Parameter

Symbol

O°C to

+ 70°C·, Vee =

Voo

Limits
Min

Typ

Max

=

5V+ 10%·, Vss

-

Unit

=

OV

Test Conditions

Device

VIL

Input Low Voltage (All
Except RESET, X1, X2)

-0.5

0.8

V

All

VIL1

Input Low Voltage
(RESET, X1, X2)

-0.5

0.6

V

All

VIH

Input High Voltage
(All Except XTAL1,
XTAL2, RESET

2.0

Vee

V

All

VIH1

Input High Voltage
(X1, X2, RESET)

3.8

Vee

V

All

VOL

Output Low Voltage (BUS)

0.45

V

IOL

All

~ut

Low Voltage
(RD, WR, PSEN, ALE)

0.45

V

IOL

=
=

2.0mA

Vou

1.8 mA

All

VOL2

Output Low Voltage
(PROG)

0.45

V

IOL

=

1.0 mA

All

VOL3

Output Low Voltage
(All Other Outputs)

0.45

V

IOL

=

1.6 mA

All

VOH

Output High Voltage (BUS)

2.4

V

IOH

All

~ut

High Voltage
(RD, WR, PSEN, ALE)

2.4

V

IOH

=
=

-400 p.A

VOH1

-100 p.A

All

VOH2

Output High Voltage
(All Other Outputs)

2.4

V

IOH

=

-40 p.A

All

±10

p.A

Vss

S;

VIN

All

-500

/A-A

Vss

+ 0.45 .:::; VIN

-300

/A-A

Vss

S;

VIN

S;

3.8V

All

±10

/A-A

Vss

S;

VIN

S;

Vee

All

Leak~

lu

Current

S;

Vee

(T1,INT)
IU1

Input Leakage Current
(P10-P17, P20-P27,
EA,SS)

IU2

Input Leakage Current
RESET

ILO

Leakage Current
(BUS, TO) (High
Impedance State)

100

+

lee

Total Supply Current'

-10

S;

Vee

All

80

100

mA

8748H

95

110

mA

8749H

NOTE:

'Icc + IDD is measured with all outputs disconnected; ss, RESET, and INT equal

4-25

'0 Vee; EA equal to Vss.

intJ

D8748H/D8749H

A.C. CHARACTERISTICS
Symbol

TA

=

O·Cto +70·C;Vcc

Parameter

=

voo

=

5V ±10%;Vss
11 MHz

f(t)
(Note 3)

Min

Max
1000

=

OV

Unit

Conditions
(Note 1)

ns

(Note 3)

t

Clock Period

1/xtal freq

90.9

tLL

ALE Pulse Width

3.5t - 170

150

ns

tAL

Addr Setup to ALE

2t - 110

70

ns

tLA

Addr Hold from ALE

t - 40

50

ns

7.5t - 200

480

ns

6t - 200

350

ns

6.5t - 200

390

ns

t - .50

40

ns

1.5t - 30

0

tCC1

Control Pulse Width (RD, WR)

tcC2

Control Pulse Width (PSEN)

tow

Data Setup before WR

two

Data Hold after WR

tOR

Data Hold (RD, PSEN)

tR01

RDto Data In

tR02

PSEN to Data In

tAW

Addr Setup to WR

tA01

Addr Setup to Data (RD)

10.5t - 220

tA02

Addr Setup to Data (PSEN)

7.5t - 200

tAFC1

Addr Float to RD, WR

tAFC2

Addr Float to PSEN

tLAFC1

ALE to Control (RD, WR)

tLAFC2

ALE to Control (PSEN)

tCA1

Control to ALE (RD, WR, PROG)

tcA2

Control to ALE (PSEN)

tcp

Port Control Setup to PROG

tpc

Port Control Hold to PROG

tpR

PROG to P2 Input Valid

110

ns

6t - 170

375

ns

4.5t - 170

240

ns

5t - 150

300

(Note 2)

ns
730

ns

460

ns

140

ns

(Note 2)

0.5t - 40

10

ns

(Note 2)

3t - 75

200

ns

1.5t - 75

60

ns

t - 65

25

ns

2t - 40

4t - 70

290

ns

1.5t - 80

50

ns

4t - 260

100

8.5t - 120

tpF

Input Data Hold from PROG

top

Output Data Setup

C:+ _

1.5t
')on

VL

"'''''''

tpo

Output Data Hold

tpp

PROG Pulse Width

ns
650

0

140

ns
ns

250

ns

1.5t - 90

40

ns

10.5t - 250

700

ns

tpL

Port 2 1/0 Setup to ALE

4t - 200

160

ns

tLP

Port 2 1/0 Hold to ALE

0.5t - 30

15

ns

+ 100

510

tpv

Port Output from ALE

IoPRR

TO Rep Rate

3t

270

tcv

Cycle Time

15t

1.36

4.5t

NOTES:

ns
15.0

1. Control outputs CL = 80 pF; BUS outputs CL = 150 pF.
2. BUS High Impedance Load 20 pF.
3. f(t) assumes 50% duty cycle on X1, X2. Max clock period is for a 1 MHz crystal input.

4-26

ns

/los

inter

D8748H/D8749H

WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM
MEMORY

1== --I ILAFcl~IY
ILL

J

WRITE TO EXTERNAL DATA MEMORY

'1

L________~I~--~L

ALE.

IAFd2

ALE

.

1- ICC2 --l

f-

J

L

ICA2

PSEN
ADDRESS

210983-6
210983-4

READ FROM EXTERNAL DATA MEMORY

INPUT AND OUTPUT FOR A.C. TESTS

--/tLAFC1L

ALE

Jr-----,IL...----:1_ _ _ _-'

l

2.4V - - - - - . .
O.45V _ _ _

tCA11RD

, - -_ _

----'X~:~: TEST POtNTS::~:~X,-_ _ __
210983-7

A.C. testing inputs are driven at 2.4V for a Logic "I" and 0.45V
for a Logic "0". Output timing measurements are made at 2.0V
for a Logic "I" and 0.8V for a Logic "0."
210983-5

4-27

D8748H/D8749H
PORT 1/PORT 2 TIMING
2ND
I~.IPL --l- I· CYCLE
ALE
1

PSEN

I

P20-23
OUTPUT

PCH

NEW P20-23 DATA

P,?RT 20-23 DATA

-t--'------'--'------------7----.-!.--____

I

PCH

'-------~I

P24-27
P10-17
PORT 24-27, PORT 10-17 DATA
NEW PORT DATA
OUTPUT. -t---~-----------~-------f~-------~I---

--1

ILP

~
- 1 - - - - I L A - - - " + '..
"-IPL~

EXPANDER
PORT
OUTPUT

1 rp-O-R-T-20--2-3-D-A-TA-;'1

PCH

~

_ _ _ _ _ _ _- J

'I

r------,.
PCH

INPUT

~IDP

I"

I-ICA1

IIPD

I

"'" "'
OUTPUT DATA
I

I,

I
,

EXPANDER
PORT

I PORT CONTROL

.

IPR -----I"~I

I;)

Fl

PROG
210983-8

CRYSTAL OSCILLATOR MODE

CERAMIC RESONATOR MODE

C1

~
=-

~_-r-_----1_ _---j2 XTAL1

.

C2

L--.jl

I

:::;o~-::,::
II

11-11
c!:3HZ

T
I

31 XTA!..:!

C3

210983-9
Cl = S pF ±% pF + (STRAY < S pF)
C2 = (CRYSTAL + STRAY) < 8 pF
C3 = 20 pF ±1 pF (STRAY < S pF)

210983-10

Crystal series resistance should be less than 301l at 11 MHz; less
than 7SIl at 6 MHz; less than 1801l at 3.6 MHz.

4-28

inter

D8748H/D8749H

DRIVING FROM EXTERNAL SOURCE

WARNING
An attempt to program a missocketed 8749H
(8748H) will result in severe damage to the part. An
indication of a properly socketed part is the appearance of the ALE clock output. The lack of this clock
may be used to disable the programmer.

+5V
47011
2 XTAL1
)0-+----=-1

The ProgramlVerify sequence is:

47011

1) Voo = 5V, Clock applied or internal oscillator operating. RESET = OV, TEST 0 = 5V, EA = 5V,
BUS and PROG floating. P10 and P11 must be
.
.
tied to ground.

'-----'--,3;;-1 XTAL2

210983-11
For XTAL1 and XTAL2 define "high" as voltages above 1.6Vand
"low" as voltages below 1.6V. The duty cycle requirements for
externally driving XTAL1 and XTAL2 using the circuit shown
above are as follows: XTAL1 must be high 35-65% of the period
and XTAL2 must be high 36-65% of the period. Rise and fall
times must be faster than 20 ns.

2) Insert 8749H (8748H) in programming socket.
3) TEST 0

= OV (select program mode)

4) EA = 18V (activate program mode)
5) Address applied to BUS and P20-22

PROGRAMMING, VERIFYING AND
ERASING THE 8749H (8748H) EPROM

6) RESET = 5V (latch address)
7) Data applied to BUS
8) Voo = 21V (programming power)

Programming Verification

9) PROG = Vee or float followed by one 50 ms
pulse to 18V

In brief, the programming process consists of: activating the program mode, applying an address,
latching the address, applying data, and applying a
programming pulse. Each word is programmed completely before moving on to the next and is followed
by a verification step. The following is a list of the
pins used for programming and a description of their
functions:

Pin
XTAL 1
XTAL2
RESET
TEST 0
EA
BUS
P20-P22
Voo·
PROG

10) Voo = 5V
11) TEST 0 = 5V (verify mode)
12) Read and verify data on BUS
13) TEST 0 = OV
14) RESET = OV and repeat from step 5
15) Programmer should be at conditions of step 1
when 8749H (8748H) is removed from socket.

Function
Clock Input (3 to 4.0 MHz)
Initialization and Address Latching
Selection of Program or Verify Mode
Activation of ProgramlVerify Modes
Address and Data Input
Data Output During Verify
Address Input
Programming Power Supply
Program Pulse Input

4-29

D8748H/D8749H
A.C. TIMING SPECIFICATION FOR PROGRAMMING 8748H/8749H
TA= 25°C ±5°C; VCC = 5V ±5%; VOO = 21V ±0.5V
Symbol

Parameter

Min

t

tAW

Address Setup Time to RESET

tWA

Address Hold Time after RESET
Data in Setup Time to PROG

two

Data il"! Hold Time after PROG

tpH

RESET Hold Time to Verify

tvoow

Voo Hold Time before PROG

tVOOH

J..

Voo Hold Time after PROG

Unit

0

1.0

ms

0

1.0

ms

50

60

ms

4tCY
4tCY

J.. .

4tCY
4tCY

t

tpw

Program Pulse Width

tTW

TEST 0 Setup Time for Program Mode

4tCY

twr

TEST 0 Hold Time after Program Mode

4tCY

too

TEST 0 to Data Out Delay

tww

RESET Pulse Width to Latch Address

t r• tl

Voo and PROG Rise and Fall Times

0.5

100

/ks

tCY

CPU Operation Cycle Time

3.75

5

/ks

tRE

RESET Setup Time before EA

t

If TEST 0 is high, too can be triggered by RESET· t

.

..

NOTE:

Test Conditions

4tCY

t

t

tow

Max

4tCY·
4tCY

4tCY

D.C. SPECIFICATION FOR PROGRAMMING 8748H/8749H
TA = 25°C ±5°C; Vcc = 5V ±5%; Voo = 21V ±0.5V
Symbol

Parameter

Min

Max

Unit

VOOH

Voo Program Voltage High Level

20.5

21.5

V

VOOL

VOO Voltage Low Level

4.75

5.25

V

VPH

PROG Program Voltage High Level

17.5 .

18.5

V

VPL

PROG Voltage Low Level

4.0

Vcc

V

VEAH

EA Program or Verify Voltage High Level

17.5

100

VOO High Voltage Supply Current

18.5

V

20.0

mA

IpROG

PROG High Voltage Supply Current

1.0

mA

lEA

EA High Voltage Supply Current

1.0

mA

4-30

Test Conditions

intJ

D8748H/D8749H

WAVEFORMS
COMBINATION PROGRAM/VERIFY'MODE (EPROMs ONLY)
VEAH
EA

Vee __+_J
I-------PROGRAM-------t--VERIFY--t----PROGRAM-

TO

Vee
VIL1

Vee
RESET
VIL1

DBO-DB7

IAW+----r~+IWA

==>---

DATA TO BE
PROGRAMMED VALID

__ -{NEXT AODRX=
VALID

LAST
ADDRESS

NEXT
ADDRESS

tyDDW~r~~

V;:'DH

VDDL----------~~
PRoi:: _ _ _ - _______

I I ~-------------------------------:~EV__TI~:

__________________.
210983-12

VERIFY MODE

\~ __--J/
DBO-DB7

==>---

ADDRESS
(0-7) VALID

- -

____-J)('-____

A_D_D_RE_S_S_(_8-_9_)V_A_L_ID_ _ _

-<

\~-

X

NI:XT
,-_ _
A_DD_R...;.E",;S;,;;S_J

NEXT DATA)OUT VALID

~)(~_ _ _ _ _N_E_X_T_A_D_D_R_E_SS_V_A_L_ID_ __
210983-13

4·31

intJ

D8748H/D8749H

SUGGESTED EPROM VERIFICATION ALGORITHM FOR HMOS-E DEVICE ONLY
INITIAL.EPROM DUMP CYCLE
ALE
,(NOTE1)

SUBSEQUENT EPROM DUMP CYCLES
: (OUTPUT)

+18V

,
,
: (INPUT)
,,

I

EA-----.J

DB----I

ADDRESS

,I

H

L....--'("'"IN"'"P""UT=-)-..1

I
,,,

ROM DATA
(OUTPUT)

H

ADDRESS

,

(INPUT)

~-~------(OUTPUT):

I

, TO, RESET - - - - - - - - '

P20·P23

, (INPUT)

,,

---i.____A_D_D_R_ES_S_ _ _--4Hl__--=A::DD:R:E::S:S_'_~..t-----~-: (INPUT)

210983-14

A10
A11

48H

49B

o
o

ADDR

Vee = Vee = +5V
Vss = OV

o

NOTE:
ALE is function of X1. X2 inputs.

4-32

MCS®-48
EXPRESS

•

O°C to 70°C Operation

•

- 40°C to

•

168 Hr. Burn-In

+ 85°C Operation

•

8048AH/8035AHL

•

8748H

•

8049AH/8039AHL

•

8243

•

8050AH/8040AHL

•

8749H

The new Intel EXPRESS family of single-component 8-bit microcomputers offers enhanced processing options
to the familiar 8048AH/8035AHL. 8748H. 8049AH/8039AHL. 8749H. 8050AH/8040AHL Intel components.
These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. but fall short of military conditions.
The EXPRESS options include the commercial standard and -40·C to + 85°C operation with or without 168
±8 hours of dynamic burn-in at 125·C per MIL-STD-883. method 1015. Figure 1 summarizes the option
marking designators and package selections.
For a complete description of 8048AH/8035AHL. 8748H. 8049AH/8309AHL. 8749H. 8040AHL and 8050AH
features and operating characteristics, refer to the respective standard commercial grade data sheet. This
document highlights only the electrical specifications which differ from the respective commercial part.

I
I

Temp Range ·C

0-70

-40-+85

0-70

-40-+85

Burn In

OHrs

OHrs

168 Hrs

168 Hrs

P8048AH
D8048AH
D8748H
P8035AHL
D8035AHL
P8049AH
D8049AH
D8749H
P8039AHL
D8039AHL
P8050AH
D8050AH
P8040AHL
D8040AHL
P8243
D8243

TP8048AH
TD8048AH
TD8748H
TP8035AHL
TD8035AHL
TP8049AH
TD8049AH
TD8749AH
TP8039AHL
TD8039AHL
TP8050AH
TD8050AH
TP8040AHL
TD8040AHL
TP8243
TD8243

QP8048AH
QD8048AH
QD8748H
QP8035AHL
QD8035AHL
QP8049AH
QD8049AH
QD8749H
QP8039AHL
QD8039AHL
QP8050AH
QD8050AH
QP8040AHL
QD8040AHL
QP8243
QD8243

LP8048AH
LD8048AH
LD8748H
LP8035AHL
LD8035AHL
LP8049AH
LD8049AH
LD8749AH·
LP8039AHL
LD8039AHL
LP8050AH
LD8050AH
LP8040AHL
LD8040AHL

LD8243

• Commercial Grade
P Plastic Package
o Cerdip Package

4-33

September 1987
Order Number: 270225-002

MCS@·48 EXPRESS

Extended Temperature ElectrIcal Specification Deviations·

TP8048AH/TP8035AHL/LP8048AH/LP8035AHL
TD8048AH/TDB035AHL/LD8048AH/LD8035AHL

D.C. CHARACTERISTICS TA = -40·Cto +8S·C;Vee = Voo =
Symbol

Limits

Parameter
Min

VIH

Input High Voltage (All Except
XTAL1, XTAL2, RESEn

sv ±10%;Vss = OV

Typ

2.2

Unit

Test Conditions

Max
Vee

V

100

Voo Supply Current

4

8

rnA

100 + Icc

Total Supply Current

40

80

rnA

TP8049AH/TP8039AHL/LP8049AH/LP8039AHL
TD8049AH/TD8039AHL/LD8049AH/LD8039AHL

D.C. CHARACTERISTICS TA = -40·Cto +8S·C; Vee = Voo = SV ±10%; Vss = OV
Symbol

Limits

Parameter
Min

VIH

Input High Voltage (All Except
XTAL 1, )ITAL2, RESET)

Typ

2.2

Unit

Test Conditions

Max
Vee

V

100

Voo Supply Current

S

10

rnA

100 + Icc

Total Supply Current

SO

100

rnA

. TP8050AH/TP8040AHL/LP8050AHL/LP8040AHL
TD8050AH/TD8040AHL/LD8050AH/LD8040AHL

D.C. CHARACTERISTICS TA = -40·Cto +8S·C;Vee = Voo = 5V ±10%;Vss = OV
Symbol

Limits

Parameter
Min

VIH

Input High Voltage (All Except
XTAL1, XTAL2, RESEn

Typ

2.2

Unit
Max
Vee

V

100

Voo Supply Current

10

20

rnA

100 + Icc

Total Supply Current

7S

120

rnA

4-34

Test Conditions

MCS®-48 EXPRESS

Extended Temperature Electrical Specification Deviations'

TD8748H/LD8748H

D.C. CHARACTERISTICS TA = -40·Cto + 85·C; vee = voo = 5V ±10%;Vss = OV
Symbol

Limits

Parameter
Input High Voltage (All Except
XTAL1, XTAL2, RESET)

VIH
100

+

lee

Unit

Typ

Min
2.2

Total Supply Current

Test Conditions

Max

50

Vee

V

130

mA

TD8749H/LD8749H·

D.C. CHARACTERISTICS TA = -40·C to + 85·C; Vee = Voo = 5V ± 10%; Vss = OV
Symbol

Limits

Parameter
Input High Voltage (All Except
XTAL 1, XTAL2, RESET)

VIH
100

+ lee

Unit

Typ

Min
2.2

Total Supply Current

Test Conditions

Max

75

Vee

V

150

mA

TP8743/TD8243/LD8243

D.C. CHARACTERISTICS TA = -40·Cto + 85·C; Vee = 5V ±10%;Vss = OV
Symbol

limits

Parameter
Min

lee

. ..

Vee Supply Current

I
I

Typ
15

I
I
..

Unit
Max

• Refer to ind,v,dual commercIal grade data sheet for complete operatIng characteristIcs.

4-35

25

rnA

Test Conditions

MCS®-48 INDEX
8
8243 Expander, 2-4
8243 Port Characteristics, 2-5

A
Accumulator, 1-1
Addressing Beyond 2K, 2-1
Addressing External Data Memory, 2-4
ALE, 1-17,2-9
ALU, 1-1
Arithmetic Logic Unit, 1-1

I/O Expander Device (8243), 2-4
I/O Expansion, 2-4; 2-5
I/O Port Characteristics,.2-5
I/O Port Restore, 2-2
Instruction Decoder, 1-1
Instruction Fetch (External), 2-1
INT, 1-17
Interrupt, 1-5, 1-7
Interrupt Routines, 2-2
'Interrupt Timing, 1-7

M

Memory Bank Switch, 2-1
Memory Bank Switching, 2-8
Memory Expansion; 2-5
Multi-Chip Systems, 2-7

B
Bus, 1-5, 1-17, 2-9

c

o

Clock Circuits, 1-9
Conditional Branches, .1-6
Control Signals, 2-8
Counter, 1-7
Cycle Counter, 1-10

Oscillator, 1-9

p

Pin Description, 1-16
Port 1, 1-5, 1-17
Port 2, 1-5, 2-9
Port Characteristics, 2-9
Power Down, 1-13
PROG, 1-17,2-9
Program Counter, 1-5
Program Memory, 1-1
Program Status Word; i-6
Programming EPROM, 1-18
PSEN,2-9
PSW, 1-6

D

Data Memory, 1-3

E
EA, 1-15
Erasing EPROM, 1-18
Erasure Characteristics, 1-18
Event Counter, 1-9
Expansion of Data Memory, 2-3
Expansion of I/O, 2-4
Expansion of Program Memory, 2-1
Extended Addressing, 2-1
External Access Mode, 1-15
External Data Memory Addressing, 2-4
External Instruction Fetch, 2-1

R
RD, 1-17, 2-9
Read Cycle, 2-3
Reset, 1-10, 1-17
Restoring I/O Ports, 2-2

4-36

s

v

Single Step, 1-11, 1-14
Stack, 1-5
State Counter, 1-10
Sync Mode, 1-15

Vee, 1-17
VDD,I-17
Verifying EPROM, 1-18
VSS, 1-17

T

W

TO, 1-5, 1-17
TI, 1-5, 1-17
Test Inputs, 1-5
Timer, 1-7, 1-9
Timing, 1-13
Timing Circuits, 1-9

WR, 1-17,2-9
Write Cycle, 2-3

4-37

MCS® . . 51 Architectural
Overview

5

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ARCHITECTURAL OVERVIEW
OF THE MCS®-S1 FAMILY OF MICROCONTROLLERS
MEMBERS OF THE FAMILY
The MCS®-Sl family of microcontrollers consists of the devices listed in Table 1. The basic architectural structure of
these devices is shown in Figure 1.
.

i-------.

I

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EXTERNAL
INTERRUPTS

8K ROM
IN 8052

I
I
I

4K
ROM

1-------·

j-·------I

~~----l

(8052)
TIMER2

I

256 BYTES
RAM IN 8052

I

COUNTER
INPUTS

TIMER 1

128 BYTES
RAM

TIMER 0

TXD

RXD

ADDRESS/DATA
270251-1

Figure 1. Block Diagram of the 8051/8052AH
Table 1. The MCS®-51 Family of Microcontrollers
Device
Name

ROMless
Version

EPROM
Version

ROM
Bytes

RAM
Bytes

16-Bit
Timers

Ckt
Type

8051

8031

(8751)

4K

128

2

HMOS

8051AH

8031AH

8751H

4K

128

2

HMOS

8052AH

8032AH

8752BH

8K

256

3

HMOS

80C51BH

80C31BH

87C51

4K

128

2

CHMOS

83C51FA

80C51FA

87C51FA

8K

256

4

CHMOS

83C152

80C152

87C152

8K

256

2

CHMOS

5-1

intJ

MCS®·51 ARCHITECTURAL OVERVIEW

8051

80C51BH

The 8051 is the original member of the MCS-51 Family, and has been in production since 1981. Among the
features of the 8051 are:

The 80C51BH is the CHMOS verSion of the 8051.
Functionally, it is fully compatible with the 8051, but
being CMOS it draws less current than its HMOS
counterpart. To further exploit the power savings available in CMOS circuitry, two reduced power modes are
added:

• 8-bit CPU optimized for control applications
• Extensive Boolean processing (single-bit logic)
capabilities

• Software-invoked Idle Mode, during which the CPU
is turned off while the RAM and other. on-chip
peripherals continue operating. In this mode, current draw is reduced to about 15% of the current
drawn when the device is fully active.-

• 32 bidirectional and individually addressable I/O
lines
• 128 bytes of on-chip Data RAM
• Two 16-bit timer/counters
•
•
•
•
•
•

• Software-invoked Power Down Mode, during which
all on-chip activities are suspended. The on-chip
RAM continues to hold its data. In this mode the
device typically draws less than 10 p.A.

Full duplex UART
5-source interrupt structure with 2 priority levels
On-chip clock oscillator
4K bytes of on-chip Program Memory
64K Program Memory address space
64K Data Memory address space

Although the 80C51BH is functionally compatible with
its HMOS counterpart, specific differences between the
two types of devices must be considered in the design of
an application circuit if one wishes to ensure complete
interchangeability between the HMOS and .CHMOS
devices. These considerations are discussed in the Application Note AP-252, "Designing with the
8OC51BH".

The 8031 differs from the 8051 in not having the onchip Program ROM. Instead, the 8031 fetches all instructions from external memory.
The EPROM version of the 8051, the 8751, is no longer
in production. It has been superseded by the 8751H.

The ROMIess version of the 80C5IBH is the
80C3IBH. The EPROM version is the 87C51.

8051AH

83C51FA

The 8051AH is identical to the 8051, but is fabricated
with HMOS II technology. It is pin-for-pin compatible
with the 8051.

The 83C51FA is an enhanced version of the 80C51BH
and is backwards compatible with the 80C51BH. The
new features which have been incorporated are as follows:
• Programmable Counter Array with
Compare/Capture
High Speed Output
Pulse Width Modulator
Watchdog Timer

The ROMless version of the 8051AH is the 8031AH.
The EPROM version is the 8751H.

8052AH
~ The 8052AH is an enhanced 8051. It is fabricated with

• Programmable Serial Channel
Automatic Address Recognition
Framing Error Detection

HMOS II technology, and is backwards compatible
with the 8051. Its enhancements over the 8051 are as
follows:

•
•
•
•
•

• 256 bytes of on-chip Data RAM
• Three timer/counters
• 6-source interrupt structure
• 8K bytes of on-chip Program ROM
The ROMless version of the 8052AH is the 8032AH.
The EPROM version is the 8752BH.

Enhanced Power Down Mode
Up/down timer/counter
8 Kbytes of on-chip Program ROM
256 bytes of on-chip Data RAM
7-source interrupt structure

For further information on these new features, refer to
the "Hardware Description of the 83C51FA" chapter.

A separate product, the 8052AH-BASIC, is an
8052AH with a full BASIC interpreter in the on-chip
ROM. .

The ROMless version of the 83C51FA is the80c51FA.
The EPROM version is the 87C51FA.

5-2

inter

MCS®-51 ARCHITECTURAL OVERVIEW

________ _ DATA MEMORY __ ______ _

PROGRAM MEMORY
(READ ONLY)

'<~~2~~~T:t

.-----------------------FFFFH: ...---.,

FFFFH:
EXTERNAL

EXTERNAL

INTERNAL

FFH.tp-----,,
,,
"

EA=O

EXTERNAL

EA=1

INTERNAL

1-"""2:--'+- 0000 -+L-_ _..1

00

0000 L...,..---r...J

.--.--~------------------270251-2

Figure 2. MCS®·51 Memory Structure

The ROMless version of the 83ClS2 is the 80ClS2.
There is no EPROM version for the 83ClS2 but a version is offered which has an additional two ports which
can be connected to an EPROM for ROM development.

83C152
The 83C152 is an enhanced version of the 80CSIBH
and is 100% compatible with code written for the
80CSIBH. Some of the new features which have been
incorporated are:
• Global Serial Channel (GSC)A high speed serial communication link capable of
transmitting data in excess of 2 Mbps in either
HDLC or CSMA/CD protocols.
• Two DMA ChannelsEach DMA channel is capable of transferring
64 Kbytes of data. Options include: automatic ad·
dressing, automatic servicing of the GSC or UART,
alternate cycle transfers, and burst data transfers.
The source andlor destination can be internal
RAM, external RAM, or SFR memory space. Most
DMA transfers take 1 machine cycle to complete.
• Port 4-:The 83ClS2 has added an additional port called
port 4. Because of the added port, the 83ClS2 is
available in 48·pin DIP or 68·pin PLCC packages.
• 8 Kbytes of on-chip program ROM
• 2S6 bytes of on-chip data RAM
• 11 interrupt vectors

MEMORY ORGANIZATION IN
MCS®·51 DEVICES

Logical Separation of Program and
Data Memory
All MCS-Sl devices have separate address spaces for
Program and Data Memory, as shown in Figure 2. The
logical separation of Program and Data Memory allows
the Data Memory to be accessed by 8-bit addresses,
which can be more quickly stored and manipulated by
an 8-bit CPU. Nevertheless, 16-bit Data Memory addresses .can also be generated through the DPTR regis·
ter.
Program Memory can only be read, not written to.
There can be up to 64K bytes of Program Memory. In
the 80S1, 80S1AH,80C5IBH, and their EPROM versions, the lowest 4K bytes of Program Memory are on·
chip. The 80S2AH, 83CSIFA, and .83ClS2 provide 8
Kbytes of on-chip Program Memory storage. In the

For more information oli the 83ClS2 please refer to the
"Hardware Description" chapter on this product.

5-3

MCS®-51 ARCHITECTURAL OVERVIEW

ROMless versions all Program Memory is' external.
The read strobe for external Program Memory is the
signal PSEN (Program Store Enable).

The lowest 4K (or 8K, in the 8052AH, 83C51FA and
83CI5~) bytes of Program Memory can be either in the
on-chip ROM or in an external ROM. This selection is
made by strapping the EA (External Access) pin to
either Vee or Vss.

Data Memory occupies a separate address space from
Program Memory. Up to 64K bytes of external RAM
can be addressed in the external Data Memo~ace.
The CPU generates read and write signals, RD and
WR, as needed during external Data Memory accesses.

In the 8051 and its derivatives, if the EA pin is strapped
to Vco then program fetches' to addresses OOOOH
through OFFFH are directed to the internal ROM. Program fetches to addresses l000H through FFFFH are
directed to external ROM.

External Program Memory and external Data Memory
may be combined if desired by applying the RD and
PSEN signals to the inputs of an AND gate and using
the output of the gate as the read strobe to the external
Program/Data memory.

In the 8052AH and the other 8K ROM parts, EA =
Vee selects addresses OOOOH through lFFFH to be internal, and addresses 2000H through FFFFH to be externai.

Program Memory

If the EA pin is strapped to Vss, then all program
fetches are directed to external ROM. The ROMless
parts (8031, 8032AH, etc.) must have this pin externally strapped to Vss to enable them to execute from external Program Memory.

Figure 3 shows a map of the lower part ofthe Program
Memory. After reset, the CPU begins execution from
location OOOOH.
As shown in Figure 3, each interrupt is assigned a fixed
location in Program Memory. The interrupt causes the,
CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for
example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service routine must
begin at location 0003H. If the interrupt is not going to
be used, its service location is available as general purpose Program Memory.

The read strobe to external ROM, PSEN, is used for all
external program fetches. PSEN is not activated for internal program fetches.

EPROM

LATCH

P2~=====:;)f

(0033H)

INTERRUPT
LOCATIONS [

iJ

002BH

270251-4

0023H

Figure 4. Executing from External
Program Memory

00' BH

:::::=t

,

0003H

RESET ,

OOOOH

8

BYTES

The hardware configuration for external program execution is shown in Fignre 4. Note that 16 I/O lines
(Ports 0 and 2) are dedicated to bus functions during
external Program Memory fetches., Port 0 (pO in Figure
4) serves as a multiplexed' address/data bus. It emits
the low byte of the Program Counter (PCL) as an address, and then goes into a float state awaiting the arrival of the code byte from the Program Memory. During
the time that the low byte of the Program Counter is'
valid on PO, the signal ALE (Address Latch Enable)
clocks this byte into an address latch. Meanwhile, Port
2 (P2 in Figure 4) emits the high byte of the Program
Counter (pCR). Then PSEN strobes the EPROM and
'
the code byte is read into the microcontroller.

270251-3

Figure 3. MCS®-51 Program Memory

The interrupt service locations are spaced at 8--byte intervals: 0003H for External Interrupt 0, OOOBH for
Timer 0, OO13H for External Interrupt 1, 001BH for
Timer 1, etc. If an interrupt service routine is short
enough (as is often the case in control applications), it
can reside entirely within that 8-byte interval. Longer
service routines can use it jump instruction to skip over
subsequent interrupt locations, if other interrupts are in
use.
5-4

MCS®-51 ARCHITECTURAL OVERVIEW

Program Memory addresses are always 16 bits wide,
even though the actual amount of Program Memory
used may be less than 64K bytes. External program
execution sacrifices two of the 8-bit ports, PO and P2, to
the function of addressing the Program Memory.

Internal Data Memory is mapped in Figure 6. The
memory space is shown divided into three blocks,
which are generally referred to as the Lower 128, the
Upper 128, and SFR space.
Internal Data Memory addresses are always one byte
wide, which implies an address space of only 256 bytes.
However, the addressing modes for internal RAM can
in fact accommodate 384 bytes, using a simple trick.
Direct addresses higher than 7FH access one memory
space, and indirect addresses higher than 7FH access a
different memory space. Thus Figure 6 shows the Upper 128 and SFR space occupying the same block of
addresses, 80H through FFH, although they are physically separate entities.

Data Memory
The right half of Figure 2 shows the internal and external Data Memory spaces available to the MCS-51 user.
Figure 5 shows a hardware configuration for accessing
up to 2K bytes of external RAM. The CPU in this case
is executing from internal ROM. Port 0 serves as a
multiplexed address/data bus to the RAM, and 3 lines
of Port 2 are being used to page the RAM. The CPU
generates RD and WR signals as needed during external RAM accesses.

,...------./1

7FH

BANK
SELECT
BITS IN

DATA

2FH

PSW~

11{
10{
01 {
00 {

T-ADDRESSABLE SPACE
} BI
(B IT ADDRESSES 0-7F)
20H
lFH
18H
17H
10H
OFH
08H
07H
0

4 BANKS OF
8 REGISTERS
R0-R7

-

RESET VALUE OF
STACK POINTER

270251-7

Figure 7. The Lower 128 Bytes of Internal RAM

270251-5

Figure 5. Accessing External Data Memory.
If the Program Memory Is Internal, the Other
Bits of P2 are Available as 110.

The Lower 128 bytes of RAM are present in all
MeS-51 devices as mapped in Figure 7. The lowest 32
bytes are grouped into 4 banks of 8 registers. Program
instructions callout these registers as RO through R7.
Two bits in the Program Status Word (PSW) select
which register bank is in use. This allows more efficient
use of code space, since register instructions are shorter
than instructions that use direct addressing.

There can be up to 64K bytes of external Data Memory. External Data Memory addresses can be either 1 or
2 bytes wide. One-byte addresses are often used in conjunction with one or more other I/O lines to page the
RAM, as shown in Figure 5. Two-byte addresses can
also be used, in which case the high address byte is
emitted at Port 2.

FFH

FFHP--------r----., FFH
: ACCESSIBLE
ACCESSIBLE
UPPER I BY INDIRECT
BY DIRECT
128
I ADDRESSING
ADDRESSING
80H:
ONLY
80H
7FH ACCESSIBLE
LOWER
BY DIRECT
128
AND INDIRECT
ADDRESSING
OL-_ _- - '

~ SPECIAL

FUNCTION
REGISTERS

NO BIT-ADDRESSABLE
SPACES
AVAILABLE AS STACK
SPACE IN 8052AH.
83C51 FA. 83C152

} PORTS
STATUS AND
CONTROL BITS
TIMER
REGISTERS
STACK POINTER
ACCUMULATOR
(ETC.)

NOT IMPLEMENTED IN 8051

80H

270251-8

270251-6

Figure 8. The Upper 128 Bytes of Internal RAM

Figure 6. Internal Data Memory

5·5

inter

MCS®-51 ARCHITECTURAL OVERVIEW

I

CY

I

AC

I

Fa

I RSll RSO I

ov

Ip I

I

,J

L

PSW 7
CARRY FLAG RECEIVES CARRY OUT
FROM BIT 1 OF ALU OPERANDS

-

PSW 6i AUXILIARY CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERANDS
PSW 5
GENERAL PURPOSE STATUS FLAG

PSW 1
USER DEFINABLE FLAG

PSW 2
OVERFLOW FLAG SET BY
ARITHMETIC OPERATIONS

PSW 4
REGISTER BANK SELECT BIT 1

,

PSW 0
PARITY OF ACCUMULATOR SET
BY HARDWARE TO 1 IF IT CONTAINS
AN ODD NUMBER OF 1S, OTHERWISE
IT IS RESET TO 0

PSW 3
REGISTER BANK SELECT BIT 0

270251-10

Figure 10, PSW (Program Status Word) Register in MCS®·51 Devices

Sixteen addresses in SFR space are both byte- and bitaddressable. The bit-addressable SFRs are those whose
address ends in OOOB. The bit addresses in this area are
80H through FFH.

The next 16 bytes above the register banks form a block
of bit-addressable memory space. The MCS-51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this
area are OOH through 7FH.

THE MCS®·51 INSTRUCTION SET
All of the bytes in the Lower 128 can be accessed by
either direct or indirect addressing. The Upper 128
(Figure 8) can only be accessed by indirect addressing.
The Upper 128 bytes of RAM are not implemented in
the 8051, but are in the 8052AH, 83C51FA, and
83C152.

All members of the MCS-51 family execute the same
instruction set. The MCS-51 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal
RAM to facilitate byte operations on smaIl data structures. The instruction set provides extensive support for
one-bit variables as a separate data type, allowing direct
bit manipulation in control and logic systems that require Boolean processing.

Figure 9 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, timers, peripheral controls, etc. These registers can only be
accessed by direct addressing. In general, all MCS-51
microcontrollers have the same SFRs as the 8051, and
at the same addresses in SFR space. However, enhancements to the, 8051 have additional SFRs that are not
present in the 8051, nor perhaps in other proliferations
of the family.

rrH

,,

EOH

ACC

,
BOH

An overview of the MCS-51 instruction set is presented
below, with a brief description of how certain instructions might be used. References to "the assembler" in
this discussion are to Intel's MCS-51 Macro Assembler,
ASM51. More detailed information on the instruction
set can be found in the MCS-51 Macro Assembler User's Guide (Order No. 9800937 for ISIS Sysiems, Ordet
No. 122752 for DOS Systems).

REGISTER-MAPPED PORTS

Program Status Word

ADDRESSES THAT END IN
OH OR 8H ARE ALSO
BIT-ADDRESSABLE '

The Program Status Word (pSW) ,contains several
status bits that reflect the current state of the CPU. The
PSW, shown in Figure 10, resides in SFR space. It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow
flag, a Parity bit, and two user-defmable status flags.

PORT 3

,
AOH

PORT 2

90H

PORT 1

-PORT PINS
-ACCUMULATOR
-PSW
'(ETC.)

The Carry bit, other than serving the functions of a
Carry bit in arithmetic operations, also serves as the
"Accumulator" for a number of Boolean operations.

I

SOH

PORT 0

270251-9

Figure 9. SFR Space

5-6

MCS®-51 ARCHITECTURAL OVERVIEW

The bits RSO and RSI are used to select one of the four
register banks shown in Figure 7. A number of instructions refer to these RAM locations as RO through R7.
The selection of which of the four banks is being referred to is made on the basis of the bits RSO and RS 1
at execution time.

IMMEDIATE CONSTANTS

The value of a constant can follow the opcode in Program Memory. For example,
MOV A, #100

The Parity bit reflects the number of Is in the Accumulator: P = 1 if the Accumulator contains an odd number of Is, and P = 0 if the Accumulator contains an
even number of Is. Thus the number of Is in the Accumulator plus P is always even.

loads the Accumulator with the decimal number 100.
The same number could be specified in hex digits as
64H.

Two bits in the PSW are uncommitted and may be used
as general purpose status flags.

Only Program Memory can be accessed with indexed
addressing, and it can only be read. This addressing
mode is intended for reading look-up tables in Program
Memory. A 16-bit base register (either DPTR or the
Program Counter) points to the base of the table, an.d
the Accumulator is set up with the table entry number.
The address of the table entry in Program Memory is
formed by adding the Accumulator data to the base
pointer.

INDEXED ADDRESSING

Addressing Modes
The addressing modes in the MCS-51 instruction set
are as follows:
DIRECT ADDRESSING

Another type of indexed addressing is used in the "case
jump" instruction. In this case the destination address
of a jump instruction is computed as the sum of the
base pointer and the Accumulator data.

In direct addressing the operand is specified by an 8-bit
address field in the instruction. Only internal Data
RAM and SFRs can be directly addressed.
INDIRECT ADDRESSING

Arithmetic Instructions

In indirect addressing the instruction specifies a register
which contains the address of the operand. Both internal and external RAM can be indirectly addressed.

The menu of arithmetic instructions is listed in Table 2.
The table indicates the addressing modes that can be
used with each instruction to access the  operand. For example, the ADD A,  instruction can
be written as:

The address register for 8-bit addresses can be RO or
RI of the selected register bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the
16-bit "data pointer" register, DPTR.

ADD
ADD
ADD
ADD

REGISTER INSTRUCTIONS

The register banks, containing registers RO through R7,
can be accessed by certain instructions which carry a
3-bit register specification within the opcode of the instruction. Instructions that access the registers this way
are code efficient, since this mode eliminates an address
byte. When the instruction is executed, one of the eight
registers in the selected bank is accessed. One of four
banks is selected at execution time by the two bank
seleCt bits in the PSW.

A,7FH
A,@RO
A,R7
A,#127

(direct addressing)
(indirect addressing)
(register addressing)
(immediate constant)

The execution times listed in Table 2 assume a 12 MHz
clock frequency. All of the arithmetic instructions execute in 1 ,""S except the INC DPTR instruction, which
takes 2 '""~, and the Multiply and Divide instructions,
which take 4 ,""s.
Note that any byte in the internal Data Memory space
can be incremented or decremented without going
through the Accumulator.
One of the INC instructions operates on the 16-bit
Data Pointer. The Data Pointer is used to generate
16-bit addresses for external memory, so being able to
increment.it in one 16-bit operation is a useful feature.

REGISTER-5PECIFIC INSTRUCTIONS

Some instructions are specific to a certain register. For
example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is
needed to point to it. The opcode itself does that. Instructions that refer to the Accumlator as A assemble
as accumulator-specific opcodes.

The MUL AB instruction multiplies the Accumulator
by the data in the B register and puts the 16-bit product
into the concatenated B and Accumulator registers.
5-7

intJ

MCS®-51 ARCHITECTURAL OVERVIEW

Table 2. A Li~t of the MCS®-51 Arithmetic Instructions
Mnemonic

Olr

Addressing Modes
Ind

Reg

Imm

Execution
Time (/Ls)

Operation
A = A + 

X

X

X

X

1

ADDC A, < byte>

A = A +  + C

X

X

X

X

1

SUBB A, 

A = A -  - C

X

X

X

X

INC

A

A=A+1

INC



 =  + 1

ADD

A,

1

Accumulator only

X

X

1

X

1

INC

DPTR

DPTR = DPTR + 1

Data POinter only

2

DEC

A

A=A-1

Accumulator only

1

DEC



 =  - 1

MUL

AB

B:A = BxA

ACC and B only

DIV

AB

A = Int [AlB]
B = Mod [AlB]

ACC and B only

DA

A

Decimal Adjust

Accumulator only

X

The DIV AB instruction divides the Accumulator by
the data in the B register and leaves the 8-bit quotient
in the Accumulator, and the 8-bit remainder in the B
register.

X

X

1
4

4
1

completes the shift in 4 /Ls and leaves the B register
holding the bits that were shifted out.
The DA A instruction is for BCD arithmetic operations. In BCD arithmetic, ADD and ADDC instructions should always be followed by a DA A operation,
to ensure that the result is also in BCD. Note that DA
A will not convert a binary number to BCD. The DA
A operation produces a meaningful result only as the
second step in the addition of two BCD bytes.

Oddly enough, DIV AB finds less use in arithmetic
"divide" routines than in radix conversions and pro-·
grammable shift operations. An example of the use of
DIV AB in a radix conversion will be given later. In
shift operations, dividing a number by 2n shifts its n
bits to the right. Using DIV AB to perform the division

Table 3. A List of the MCS®-51 Logical Instructions
Mnemonic

Addressing Modes
Oir

Ind

Reg

Imm

Execution
Time (/Ls)

X

X

X

1

Operation

ANL

A,

A = A .AND. 

X

ANL
ANL

 ,A
,#data

 =  .AND. A
 =  .AND. #data

X
X
X

A, 
ORL  ,A
ORL  ,#data
XRL A,
XRL  ,A
XRL < byte> , # data
CRL A
CPL A
RL
A
RLC A
RR
A
RRC A
SWAP A
ORL

A _
1"\ -

A

'"'0

.......... .+ ...........

n .vn ........ uy ..' C '

 =  .OR. A

)(

 =  .OR. #data

X

A = A .XOR. 

X
X

 = .XOR.A

1
2

X

X

X

X

X

1

X

1
2
.1

Rotate Left through Carry

Accumulator only

Rotate ACC Right 1 bit
Rotate Right through Carry

Accumulator only·
Accumulator only

1
2
1
1
1
1
1
1

Swap Nibbles in A

Accumulator only.

1

 =  .XOR. #data
A = OOH
A = .NOT.A

X
Accumulator only
Accumulator only
Accumulatoronly

Rotate ACC Left 1 bit

5-8

..

inter

MCS®-51 ARCHITECTURAL OVERVIEW

The SWAP A instru.:;tion interchanges the high and
low nibbles within the Accumulator. This is a useful
operation in BCD manipulations. For example, if the
Accumulator contains a binary number which is known
to be less than 100, it can be quickly converted to BCD
by the following code:

Logical Instructions
Table 3 shows the list of MCS-51 logical instructions.
The instructions that perform Boolean operations
(AND, OR, Exclusive OR, NOT) on bytes perform the
operation on a bit-by-bit basis. That is, if the Accumulator contains OOllOlOlB and  contains
OlOlOOllB, then
ANL

B,#l0
AB
SWAP A
ADD A,B
MOY

DIY

A, 

will leave the Accumulator holding OOOlOOOlB.
Dividing the number by 10 leaves the tens digit in the
low nibble of the Accumulator, and the ones digit in the
B register. The SWAP and ADD instructions move the
tens digit to the high nibble of the Accumulator, and
the ones digit to the low nibble.,

The addressing modes that can be used to access the
 operand are listed in Table 3. Thus, the ANL
A,  instruction may take any of the forms
ANL
ANL
ANL
ANL

A,7FH
A,@RI
A,R6
A,#53H

(direct addressing)
(indirect addressing)
(register addressing)
(immediate constant)

Data Transfers
INTERNAL RAM

All of the logical instructions that are Accumulatorspecific execute in I/Ls (using a 12 MHz clock). The
others take 2 /Ls.

Table 4 shows the menu of instructions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used,
with each one. With a 12 MHz dock, all of these instructions execute in either I or 2 /Ls.

Note that Boolean operations can be performed on any
byte in the internal Data Memory space without going
through the Accumulator. The XRL , #data
instruction, for example, offers a quick and easy way to
invert port bits, as in
XRL

The MOY ,  instruction allows data to
be transferred between any two internal RAM or SFR
locations without going through the Accumulator. Remember the Upper 128 byes of data RAM can be accessed only by indirect addressing, and SFR space only
by direct addressing.

PI,#OFFH

If the operation is in response to an interrupt, not using

the Accumulator saves the time and effort to stack it in
the service routine.

Note that in all MCS-51 devices, the stack resides in
on-chip RAM, and grows upwards. The PUSH instruction first increments the Stack Pointer (SP), then copies
the byte into the stack. PUSH and POP use only direct
'addressing to identify the byte being saved or restored,

,

The Rotate instructions (RL A, RLC A, etc.) shift the
Accumulator 1 bit to the left or right. For a left rotation, the MSB rolls into the LSB position. For a right
rotation, the LSB rolls into the MSB position.

Table 4. A List of the MCS®-S1 Data Transfer Instructions that Access Internal Data Memory Space
Mnemonic

Addressing Modes

Operation

Dir

-

Ind

Reg

Imm

Execution
Time (/Ls)

X

1

MOV

A, 

A"C 

X

X

X

MOV

,A

 = A

X

X

X

MOV

, 

 = 

X

X

X

MOV

DPTR,#data16

DPTR = 16-bit immediate constant.

PUSH 

INC SP: MOV "@SP",

X

POP



MOV , "@SP" : DEC SP

X

XCH

A, 

ACC and  exchange data

X

XCHD A,@Ri

ACC and @Ri exchange low nibbles

5-9

1
X

2

X

2
2
2

X
X

X

1
1

inter

MCS®-51 ARCHITECTURAL OVERVIEW

but the stack itself is accessed by indirect addressing
using the SP register. This means the stack can go into
the Upper 128, if they are implemented, but not into
SI:R space.

After the routine has been executed, the Accumulator
contains the two digits that were shifted out on the
right. Doing the routine with direct MOYs uses 14 code
bytes and 9 ,""S of execution time (assuming a 12 MHz
clock). The same operation with XCHs uses less code
and executes almost twice as fast.

The Upper 128 are not implemented in the 8051,
8051AH, or 8OC51BH, nor in their ROMless or
EPROM counterparts. With these devices, if the SP
points to the Upper 128, PUSHed bytes are lost, and
POPped bytes are indeterminate.

To right-shift by an odd number of digits, a one-digit
shift must be executed. Figure 12 shows a sample of
code that will right-shift a BCD number one digit, using the XCHD instruction. Again, the contents of the
registers holding the number and of the Accumulator
are shown alongside each instruction.

The Data Transfer instructions include a 16-bit MOY
that can be used to initialize the Data Pointer (DPTR)
for look-up tables in Program Memory, or for 16-bit
external Data Memory accesses.

MOV R1.#2EH
MOV RO.#2DH
loop for R1 = 2EH:
LOOP: MOV A.@R1
00 12 34 56 78 78
XCHD A.@RO
00 12 34 58 7876
SWAP A
00 12 34 58 78 67
MOV @R1;A
00 12 34 58 67 67
DEC R1
00 12 34 58, 67 67
DEC RO
00 12 34 58 67 67
CJNE R1.#2AH.LOOP
loop for R1 = 2DH:
00112138145167145
loop for R1 = 2CH:
100 18 23 45 67 23
loop for R1 = 28H:
08 01 23 45 67 01
CLR A
081 01 1231451671 00
00 01 23 45 67 08
XCH A.2AH

The XCH A, , instruction causes the Accumulator and addressed byte to exchange data. The XCHD
A,@Ri instruction is similar, but only the low nibbles
are involved in the exchange.
To see how XCH and XCHD can be used to facilitate
data manipulations, consider first the problem of shifting an 8-digit BCD number two digits to the right. Figure 11 shows how this can be done using direct MOYs,
and for comparison how it can be done using XCH
instructions. To aid in understanding how the code
works, the contents of the registers that are holding the
BCD number and the content of the Accumulator are
shown alongside each instruction to indicate their
status after the instruction has been executed.
2A 28 2C
MOV A,2EH
00 12 34
MOV 2EH,2DH 00 12 34
MOV 2DH,2CH 00 12 34
MOV 2CH,28H 00 12 12
MOV 28H,#0
00 00 12
(a) Using direct MOVs: 14 bytes, 9 p.s

20
56
56
34
34
34

2E
78
56
56
56
56

I

Figure 12. Shifting a BCD Number
One Digit to the Right

ACC
78
78
78
78
78

First, pointers Rl and RO are set up to point to the two
bytes containing the last four BCD digits. Then a loop
is executed which leaves the last byte, location 2EH.
holding the last two digits of the shifted nuthber. The
pointers are decremented, and the loop is repeated for
location 2DH. The CJNE instruction (Compare and
Jump if Not Equal) is a loop control that will be described later.

I 2A I 28 I 2C I 20 I 2E I ACC

CLR
XCH

A

I 00 112 1 34 1 56

A.2BH I 00
A.2CH
00 I 00
00 1 34
12

1

78

I

55 1 78
78 I
56

XCH
XCH A.2DH
00
00
12 1 34
XCH A.2EH
00
00
12
34
(b) Using XCHs: 9 bytes. 5 p.s

78
56

00
12

34
56
78

The loop is executed from LOOP to CJNE for Rl =
2EH, 2DH, 2CH and 2BH. At that point the digit that
was originally shifted out on the right has propagated
to location 2AH. Since that location should be left with
Os, the lost digit is moved to the Accumulator.

Figure 11. Shifting a BCD Number
Two Digits to the Right

5-10

MCS®-51 ARCHITECTURAL OVERVIEW

Table 6. The MCS®-51 Lookup
Table Read Instructions

EXTERNAL RAM

Table 5 shows a list of the Data Transfer instructions
that access external Data Memory. Only indirect addressing can be used. The choice is whether to use a
one-byte address, @Ri, where Ri can be either RO or
Rl of the selected register bank, or a two-byte address,
@DPTR. The disadvantage to using l6-bit addresses if
only a few K bytes of external RAM are involved is
that l6-bit addresses use all 8 bits of Port 2 as address
bus. On the other hand, 8-bit addresses allow one to
address a few K bytes of RAM, as shown in Figure 5,
without having to sacrifice all of Port 2.
All of these instructions execute in 2 /Ls, with a
12 MHz clock.
Table 5. A List of the MCS®-51 Data
Transfer Instructions that Access
External Data Memory Space
Address
Width

Mnemonic

Operation

Execution
Time (ILS)

8 bits

MOVXA,@Ri

Read external
RAM@Ri

2

8 bits

MOVX@Ri,A

Write external
RAM@Ri

2

16 bits

MOVX A,@DPTR

Read external
RAM@DPTR

2

16 bits

MOVX @DPTR,A

Write external
RAM@DPTR

2

Mnemonic

Operation

Execution
Time (ILS)

MOVC

A,@A+DPTR

Read Pgm Memory
aI(A+DPTR)

2

MOVC

A,@A+PC

Read Pgm Memory
at (A+PC)

2

The first MOVC instruction in Table 6 can accommodate a fable of up to 256 entries, numbered 0 through
255. The number of the desired entry is loaded into the
Accumulator, and the Data Pointer is set up to point to
beginning of the table. Then
MOVC

A,@A+DPTR

copies the desired table entry into the Accumulator.
The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table
base, and the table is accessed through a subroutine.
First the number of the desired entry is loaded into the
Accumulator, and the subroutine is called:
MOV
CALL

A,ENTRY_NUMBER
TABLE

The subroutine "TABLE" would look like this:
TABLE:

Note that in all external Data RAM accesses, the Accumulator is always either the destination or source of
the data.

MOVC
RET

A,@A + PC

The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
have up to 255 entries, numbered 1 through 255. Number 0 can not be used, because at the time the MOVC
instruction is executed, the PC contains the address of
the RET instruction. An entry numbered 0 would be
the RET opcode itself.

The read and write strobes to external RAM are activated only during the execution of a MOVX instruction. Normally these signals are inactiye, and in fact if
they're not going to be used at all, their pins are available as extra 110 lines. More about that later.
LOOKUP TABLES

Boolean Instructions

Table 6 shows the two instructions that are available
for reading lookup tables in Program Memory. Since
thesC1 instructions access only Program Memory, the
lookup tables can only be read, not updated. The mnemonic is MOVC for "move constant".

MCS-51 devices contain a complete Boolean (single-bit)
processor. The internal RAM contains 128 addressable
bits, and the SFR space can support up to 128 other
addressable bits. AIl of the port lines are bit-addressable, and each one can be, treated as a separate singlebit port. The instructions that access these bits are not
just conditional branches, but a complete menu of
move, set, clear, complement, OR, and AND instructions. These kinds of bit operations are not easily obtained in other architectures with any amount of byteoriented software.

'If the table access is to external Program Memory, then
the read strobe is PSEN.

5-11

MCS®-51 ARCHITECTURAL OVERVIEW

Note that the Boolean instruction set includes ANL
and ORL operations, but not the XRL (Exclusive OR)
operation. An XRL operation is simple to implement in
software. Suppose, for example, it is required to form
the Exclusive OR of two bits:

Table 7. A List of the MCS®-S1
Boolean Instructions
Mnemonic

Operation

ANL

C,bit

C = C .AND. bit

ANL

C,/bit

C = C .AND .. NOT. bit

ORL

C,bit

C = C.OR. bit

ORL

C,/bit

C = C .OR. .NOT. bit

MOV

C,bit

C = bit

Execution
Time (,....s)

MOV

bit,C

bit = C

2
2
2
2
'1
2

CLR

C

C=O

1

CLR

bit

bit = 0

1

C=1

1

SETS C
SETS bit

bit = 1

1

CPL

C

C = .NOT.C

1

CPL

bit

bit = .NOT. bit

1

JC

rei

JumpifC

=1

JNC

rei

JumpifC = 0

JB

bit,rel

Jump if bit

JNS

bit, rei

Jump if bit

JSC

bit,rel

Jump if bit

2
2
2
2
2

=1
=0
= 1; CLR bit

C = bit! .xRL. bit2
The software to do that could be as follows: C,bitl
MOV
bit2,OVER
JNB
CPL
C
OVER: (continue)
First, bit! is moved to the Carry. If bit2 = 0, then _C
now contains the correct result. That is, bit! .xRL. bit2
= bit! if bit2 = O. On the other hand, if bit2 = 1 C
now contains the complement of the correct result. I(
need only be inverted (CPL C) to complete the operation;
This code uses the JNB instruction, one of -a series of
bit-test instructions which execute a jump if the addressed bit is set (JC, JB, JBC) or if the addressed bit is
not set (JNC, JNB). In the above case, bit2 is being
tested, and if bit2 = 0 the CPL C instruction is jumped
over.
JBC executes the jump if the addressed bit is set, and
also clears the bit. Thus a flag can be tested and cleared
in one operation.

The instruction set for the Boolean processor is shown
in Table 7. All bit accesses are by direct addressing. Bit
addresses OOH through 7FH are in the Lower 128, and
bit addresses 80H through FFH are in SFR space.

All the PSW bits are directly addressable, so the Parity
bit, or the general purpose flags, for example, are also
available to the bit-test instructions.

Note how easily an internal flag can be moved to a port
pin:
MOV
MOV

RELATIVE OFFSET

C,FLAG
P1.0,C

The destination address for these jumps is specified to
the assembler by a label or by an actual address in
Program Memory.' However, the destination address
aSSembleS to a relative offSet byte. This is a signed
(two's complement) offset byte which is added to the
PC in two's complement arithmetic if the jump is executed.

In this example, FLAG is the name of any addressable
bit in the Lower 128 or SFR space. An 110 line (the
LSB of Port 1, in this case) is set or cleared depending
on whether the flag bit is 1 or O.
The Carry bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instructions that
refer to the Carry bit as C assemble as Carrycspecific
instructions (CLR C, etc). The Carry bit also has a
direct address, since it resides in the PSW register,
which is bit-addressable.

The range of the jump is therefore -128 to + 127 Program Memory bytes relative to the first byte following
the instruction.

5-12

intJ

MCS®-51 ARCHITECTURAL OVERVIEW

the Accumulator. Typically, DPTR is set up with the
address of a jump table, and the Accumulator is given
an index to the table. In a 5-way branch, for example,
an integer 0 through 4 is loaded into the Accumulator.
The code to be executed might be as follows:

Jump Instructions
Table 8 shows the list of unconditional jumps.
Table 8. Unconditional Jumps
in MCS®-S1 Devices

Mnemonic

Operation

Jump to addr
JMP addr
JMP @A+DPTR Jump to A+ DPTR
CALL addr
Call subroutine at addr
RET
Return from subroutine
RETI
Return from interrupt
No operation
NOP

MOY
MOY

Execution
Time (p.s)

RL
, JMP

2

DPTR,#JUMP_TABLE
A,INDE~NUMBER

A

@A+DPTR

2

The RL A instruction converts the index number (0
through 4) to an even number on the range 0 through 8,
because each entry in the jump table is 2 bytes long:

2
2
2

JUMP_TABLE:
AJMP
AJMP
AJMP
AJMP
AJMP

1

The Table lists a single "JMP addr" instruction, but in
fact there are three-SJMP, UMP and AJMP-which
differ in the format of the destination address. JMP is a
generic mnemonic which can be used if the programmer does not care which way the jump is encoded.

CASE_O
CASE_I
CASE~

CASE..;...3
CASE_4

Table 8 shows a single "CALL addr" instruction, but
there are two of them-LCALL and ACALL-which
differ in the format in which the subroutine address is
given to the CPU. CALL is a generic mnemoni~ which
can be used ifthe programmer does not care which way
the address is encoded.

The SJMP instruction encodes the destination address
as a relative offset, as described above. The instruction
is 2 bytes long, consisting of the opcode and the relative
offset byte. The jump distance is limited to a range of
-128 to + 127 bytes relative to the instruction following the SJMP.

The LCALL instruction uses the 16-bit address format,
and the subroutine can be anywhere in the 64K Program Memory space. The ACALL'instruction uses the
II-bit format, and the subroutine must be in the same
2K block as the instruction following the ACALL.

The UMP instruction encodes the destination address
as a 16-bit constant. The instruction' is 3 bytes long,
consisting of the opcode and two address bytes. The
destination address can be anywhere in the 64K Program Memory space.

In any case the programmer specifies the subroutine
address to the assembler in the same way: as a label or
as a 16-bit constant. The assembler will put the address
into the correct forinat for the given instructions.

The AJMP instruction encodes the destination address
as an ll-bit constant. The instruction is 2 bytes long,
consisting of the opcode, which itself contains 3 of the
II address bits, followed by another byte containing the
low 8 bits of the destination address. When the instruction is executed, these II bits are simply substituted for
the low II bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same 2K
block as the instruction following the AJMP.

Subroutines should end with a RET instruction, which'
returns execution to the instruction following the
CALL.
RETI is' used to return from an interrupt service routine. The only difference between RET and RETI is
that RET! tells the interrupt control system that the
interrupt in progress is done. If there is no interrupt in
progress at the time RETI is executed, then the RET!
is functionally identical to RET.

In all cases the programmer specifies the destination
address to the assembler in the same way: as a label or
as a 16-bit constant. The assembler will put the destination address into the correct format for the given instruction. If the format required by the instru, ,rei

Decrement and jump if not zero

CJNE A, < byte> ,rei

Jump if A"* 

CJNE < byte> , # data,rel

Jump if  "* #data

X
X

Execution
Time (,...s)

Imm

2
2
2
2
2

X
X
X

X

There is no Zero bit in the PSW. The, JZ and JNZ
instructions test the Accumulator data for that condition.

Ill>
IICS -51
HIIOS
OR CHIIOS
.....-t---jXTAL2

The DJNZ instruction (Decrement and Jump if Not
Zero) is for loop control. To execute a loop N times,
load a counter byte with N and terminate the loop with
a DJNZ to the beginning, of the loop, as shown below
for N = 10:

QUA~~ ~~~~~ '

....

RESONATOR

'--~-+-I XTAL 1
VSS

-= '-----...,J
270251-11

MOY
COUNTER,# 10
LOOP: (begin loop)

Figure 13. Using the On-Chip OSCillator

•

Ill>

(end loop)
DJNZ
COUNTER,LOOP
(continue)

IICS -51
HIIOS
OR CHIIOS

XTAL2

The CJNE instruction (Compare and Jump if Not
Equal) can also be used for loop control as in Figure 12.
Two bytes are speCified in the operand field of the instruction. The jump is 'executed only if the two bytes
are not equal. In the example of Figure 12, the two
bytes were the data in RI and the constant 2AH. The
initial data in RI was 2EH. Every time the loop was
executed, RI was decremented, and the looping was to
continue until the RI data reached 2AH. '

EXTERNAL
CLOCK
SIGNAL

XTAL1
VSS

270251-12

A. HMOS or CHMOS

EXTERNAL

~

, CLOCK
SIGNAL,

Another application of this instruction is in "greater
than, less than" comparisons. The two bytes in the operand fieid are iaken as unsigned iniegers. If the first is
less than the second, then the Carry bit is se~ (I). If the
frrst is greater than or equal to the second, then the
Carry bit is cleared.

IICS":.'51
HIIOS
ONLY
XTAL2

270251-13

B.HMOSOnly

CPU TIMING

Ill>

All MCS-51 microcontrollers have an on-chip oscillator
which can be used, if desired as the clock source for the ,
CPU. To use the on-chip oscillator, connect a crystal or
ceramic resonator between the XTALl and XTAL2
pins of the microcontroller, and Capacitors to ground as
shown in Figure 13.

IICS -51
CHIIOS
ONLY
(NC)

XTAL2

EXTERNAL
CLOCK
SIGNAL

XTAL1
VSS

,270251-14

C. CHMOS Only
Figure 14. Using an External Clock
5-14

inter

MCS®~51

ARCHITECTURAL OVERVIEW

Examples of how to drive the clock with an external
oscillator are shown in Figure 14. Note that in the
HMOS devices (8051, etc.) the signal at the XTAL2 pin
actually drives the internal clock generator. In the
CHMOS devices (80C51BH, etc.) the signal at the
XTALl pin drives the internal clock generator. If only
one pin is going to be driven with the external oscillator
signal, make sure it is the right pin.

Machine Cycles
A machine cycle consists' of a sequence of 6 states,
numbered SI through S6. Each state time lasts for two
oscillator periods. Thus a machine cycle takes 12 oscil-'
lator periods or 1 JLs if the oscillator frequency is
12 MHz.
Each state is divided into a Phase 1 half and a'Phase 2
half. Figure 15 shows the fetch/execute sequences in

The internal clock generator defines the sequence of
states that make up the MCS-51 machine cycle.

OSC.
(XTAL2)

I

Sl

1 S21 S3

I I
54

S5

1 56 1 Sl

I I
S2

53

1 54

I I
55

S6

1

Sl

1

~~~~~~~~~~~~~~~~~~~~~~~~~~

ALE

_[

-- - - - -

______

_R:~D NEXT OPCODE AGAI,!,

.----I~--r---r-..L.-._-,r---,
~~_-L_~_~~~~

(A) 1-byle. 1-cyclelnstruc"on. e.g., INC A.

I

I

READ OPCODE.

I
:

_

[_R:~D NEXT OPCODE.

--------~~-~-_r~.--r_~
________

L-:..:.....J--=:......L.~-'-

_

_'___'----j

(8) 2-byte, 1-cycle Instruction, e.g" ADD A, #data

READ OPCODE.
READ NEXT
OPCODE (DISCARD),

(C) 1-byle, 2-cyclolnatuctlon, •.g.,.INC DPTR.
READ NEXT OPCODE AGAIN.

READOPCODE
(MOYX).

. NO
NO FETCH,

l

______

D
I

I

L-~_~_~_~~~~

_

_'__

I
I ____ _

_'___~~--~--~------

DATA
(D) MOYX (l-byle, 2-cycle)
ACCESS EXTERNAL MEMORY

270251-15

Figure 15. State Sequences in MCS®-51 Devices
5-15

intJ

MCS®·51 ARCHITECTURAL OVERVIEW

states and phases for various kinds of instructions. Normally two program fetches are generated during each
machine cycle, even if the instruction being executed
doesn't require it. If the instruction being executed
doesn't need more code bytes, the CPU simply ignores
the extra fetch, and the Program Counter is not incremented.

The fetch/execute sequences are the same whether the
Program Memory is internal or external ,to the chip.
Execution· times do not depend on whether the Program Memory is internal or external.
Figure 16 shows the signals an~ timing involved in program fetches when the Program Memory is external. If
Program Memory is external, then the Program Memory read strobe PSEN is normally activated twice per
machine cycle, as shown in Figure 16(A).

Execution of a one-cycle instruction (Figure l5A and
B) begins during State 1 ofthe machine cycle, when the
opcode is latched into the Instruction Register. A second fetch occurs during S4 of the same machine cycle.
Execution is complete at the end of State 6 of this machine cycle.

If an access to external Data Memory occurs, as shown
in. Figure 16(B), two PSENs are skipped, because the
address and data bus are being used for the Data Memory access.

The MOVX instructions take two machine cycles to
execute. No program fetch is generated during the second cycle of a MOVX instruction. This is the only time
program fetches are skipped. The fetch/execute sequence for MOVX instructions is shown in Figure
15(D).

Note that a Data Memory bus cycle takes twice as
much time as a Program Memory bus cycle. Figure 16
shows the relative timing of the addresses being emitted
at Ports'O and 2, and of ALE and PSEN. ALE is used
to latch the low address byte from PO into the address
latch.

ALE

PsEN

AD

-------+----------~---------4----------~----~----~--PCHOUT

X

PCHOUT

X

PCHOUT

(A)

WITHOUT A
MOVX.

X

PCHOUT

PO

,

I
I

I

tPCLOUT
VALID

bCLouT
VALID

lpCLOUT
VALID

CYCLE 1

I

I

-------"""1.------,

1~lulas

CYCLE 2,

lpCLOUT
VALID

.

"'

~1~1~1~lulasl~1

ALE

PSEN

AD

-------+-----------l-----,

(8)

WITH A
MOVX.

270251-16

Figure 16. Bus Cycles In MCS@·51 Devices Executing from External

5-16

Pr~gram

Memory

inter

MCS®-S1 ARCHITECTURAL OVERVIEW

When the CPU is executing from internal Program
Memory, PSEN is not activated, and program addresses are not emitted. However, ALE continues to be activated twice per machine cycle and so is available as a
clock output signal. Note, however, that one ALE is
skipped during the execution of the MOVX instruction.

named IE (Interrupt Enable). This register also contains a global disable bit, which can be cleared to disable all interrupts at once. Figure 17 shows the IE register for the 8052AH.
INTERRUPT PRIORITIES

Each interrupt source can also be individually programmed to one of two priority levels by setting or
cl~aring a bit in the SFR named IP (Interrupt Priority).
Figure 18 shows the IP register in the 8052AH.

Interrupt Structure
The 8051, 8051AH, and 80C51BH, and their ROMless
and EPROM versions, provide 5 interrupt sources: 2
external interrupts, 2 timer interrupts, and the serial
p.ort i!lterrupt. The 8052AH provides these 5 plus a
Sixth mterrupt that is associated with the third timer!
counter which is present in this device. Additional interrupts are available on the 83C51FA and 83C152.
Refer to the appropriate chapters on these devices for
further information on their interrupts.

A low-priority interrrupt can be interrupted by a highpriority interrupt, but not by another low-priority inter- '
rupt. A high-priority interrupt can't be interrupted by
any other interrupt source.
If two interrupt requests of different priority levels are
received simultaneously, the request of higher priority
level is serviced. Ifinte~rupt requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. Thus
within each priority level there is a second priority
structure determined by the polling sequence.

What follows is an overview of the interrupt structure
for these devices. More detailed information for specific
members .of the MCS-51 family is provided in the chapters of thiS handbook that describe the specific devices.

Figure 19 shows, for the 8052AH, how the IE and IP
registers and the polling sequence work to determine
which if any interrupt will be serviced.

INTERRUPT ENABLES

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the SFR
(MSB)

(MSB)

(LSB)

Symbol
EA

Position
IE.7

ET2

IE.6'
IE5

ES

lEA

ETI

IE.3

EXI

IE.2

ETO

lEI

EXO

lEO

(LSB)

I-I -I PT2 I PS I PTt I PXl I PTO I PXO I

IEA I-I ET2 I ES I ETI I EXI I ETO I EXO I
Function
disables all interrupts. If EA = O. no
interrupt will be acknowledged. If EA
=
1. each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
reserved
enables or disables the Timer 2
overflow or capture interrupt. If ET2
= O. the Timer 2 interrupt is disabled.
enables m disables the Serial Port
interrupt. If ES = 0, the Serial Port
interrupt is disabled.
enables or disables the Timer 1
Overflow interrupt. If ETI = O. the
Timer 1 interrupt is disabled.
enables or disables External Interrupt
1. If EXI = 0, Exlernal Interrupt t is
disabled.
enables or disables the Timer 0
Overflow interrupt If ETO = O. the
Timer 0 interrupt is disabled.
enables or disables Exlernal Interrupt
O. If EXO = 0, Exlernal Interrupt 0 is
disabled.

Symbol

Position

PT2

IP.7
IP.6
IP.5

PS

IP.4

PTt

IP.3

PXl

IP.2

, PTO

IP.l

PXO

IP.O

Function
reserved
reserved
defines the Timer 2 interrupt priority
level. PT2 = 1 programs it to the
higher priority level.
defines the Serial Port interrupt
priority level. PS = 1 programs it to
the higher priority level.
defines the Timer 1 interrupt priority
level. PTI = 1 programs it to the
higher priority level.
defines the Exlernai Interrupt 1
priority level. pxi = t programs it to
the higher priority level.
defines the Timer 0 interrupt priority
level. PTO = 1 programs it to the
higher priority level.
defines the Exlernal Interrupt 0
priority level. PXO = 1 programs it to
the higher priority level.

Figure 18. IP(lnterrupt Priority)
Register in the 8052AH

Figure 17. IE (Interrupt Enable)
Register In the 8052AH

5-17

inter

MCS@·51 ARCHITECTURAL OVERVIEW

HIGH PRIORITY
INTERRUPT

IP REGISTER

I
I
I
I

T F O - - - - -......t-CI""

~>t-I-<>-~_l_--+-+I

INTERRUPT
POLLING
SEQUENCE

I

I
I

O-o%c>t--r~-I--++I
I
I
I
I

*'"""0' ~>t--jO-c,..-l---41

T f 1 - - - - - -.......

I

I
I

I

RI
TI

Tf2
EXf2

").---"*-0'

~>t--r~-l--W

(8052 ONLY)

INDIVIDUAL
ENABLES

LOW PRIORITY
INTERRUPT

GLOBAL
DISABLE

270251-17

Figure 19. 8052 Interrupt Control System

pleted in less time than it takes other architectures to
commence them.

In operation, all the interrupt flags are latched into the
interrupt control system during State 5 of every machine cycle. Th~ samples are polled during ~he follo~­
ing machine cycle. If the flag for an enabled mterrupt IS
found to be set (I), the interrupt system generates an
LCALL to the appropriate location in Program Memory, unless some other condition blocks the interrupt.
Several conditions can block an interrupt, among them
that an interrupt of equal or higher priority level is
already in progress. I

SIMULATING A THIRD PRIORITY LEVEL IN
SOFTWARE

Some appli~ations require more than the two priority
levels that are provided by on-chip hardware in
MCS-SI devices. In these cases, relatively simple soft-:
ware can be written to produce the same effect as a
third priority leveL

The hardware-generated LCALL causes the contents of
the Program Counter to be pushed onto the stack, a~d
reloads the PC with the beginning address of the service
routine. As previously noted (Figure 3), the service rou-.
tine for each interrupt begins at a fixed location.

First, interrupts that are to have higher priority ~ha~ 1
are assigned to priority 1 in the IP (Interrupt Pnonty)
register. The service routines for priority 1 interrupts
that are supposed" to be interruptible by "priority 2"
interrupts are written to include the following code:

Only the Program Counter is automatically pushed
onto the stack, not the PSW or any other register. Havingonly the PC be automatically saved allows the p~o­
grammer to deCide how much time to spend savmg
which other registers. This enhances the interrupt response time, albeit at the expense of increasing the programmer's burden of responsibility. As a result, many
interrupt functions that are typical in control applications--':'toggling a port pin, for example, or reloading a
timer, or unloading a serial buffer--can often be com-

PUSH
IE
MOV
IE,#MASK
CALL . LABEL
._ •••• *
(execute service routine)

•••••••

POP
RET
LABEL: RET!
5-18

IE

MCS®-51 ARCHITECTURAL OVERVIEW

As soon as any priority 1 interrupt is acknowledged,
the IE (Interrupt Enable) register is re-defined so as to
disable all but "priority 2" interrupts. Then, a CALL to
LABEL executes the RETI instruction, which clears
the priority 1 interrupt-in-progress flip-flop. At this
point any priority 1 interrupt that is enabled can be
serviced, but only "priority 2" interrupts are enabled.

POPping IE restores the original enable byte. Then a
normal RET (rather than another RET!) is used to
terminate the service routine. The additional software
adds 10 ,...S ~at 12 MHz) to priority 1 interrupts.

5-19

Hardware Description of the
8051,8052 and 80e51

6

intJ

HARDWARE DESCRIPTION
OF THE 8051, 8052 AND 80C51
• The EPROM versions of the 80SIAH, 80S2AH,
and 80CSIBH

INTRODUCTION
This chapter presents a comprehensive description of
the on-chip hardware features of the MCS®-SI microcontrollers. Included in this description are

The devices under consideration are listed in Table 1.
As it becomes unwieldy to be constantly referring to
"each of these devices by their individual names, we will
adopt a convention of referring to them generically as
80S Is and 80S2s, unless a specific member of the group
is being referred to, in which case it will be specifically
named. The "80S Is" include the 8051, 8051AH, and"
80CSlBH, and their ROMless and EPROM versions.
The "80S2s" are the 80S2AH, 8032AH, and 87S2BH.

• The port drivers and how they function both as
ports and, for Ports 0 and 2, in bus operations
• The Timer/Counters
• The Serial Interface
• The Interrupt System
• Reset
• The Reduced Power Modes in the CHMOS devices

Figure I shows a functional block diagram of the 80SIs
and 8052s.

Table 1. The MCS-51 Family of Microcontrollers
Device
Name
8051
8051AH
8052AH
80C51BH

ROM less
Version
8031 "
8031AH
8032AH
80C31BH

EPROM
Version

ROM
Bytes

RAM
Bytes

16-bit
Timers

Ckt
Type

(8751)
8751H
8752BH
87C51

4K
4K
8K
4K

128
128
256
128

2
2
3
2

HMOS
HMOS
HMOS
CHMOS

SpeCial Function Registers
/

A map of the on-chip memory area called SFR (Special Function Register) space is shown in Figure 2. SFRs marked
by parentheses are resident in the 8052s but not in the 80S Is.

,--------

~

r

....

..

AU;

·R ....... lnIQUJID32on1'.

270252-1

Figure 1. MCS-51 Architectural Block Diagram
6-1

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
8 Bytes
F8

FO

FF

B

F7

EF

E8

EO

ACC

E7

OF

08

DO

C8

co
B8

BO
A8

AO
98
90
88

80

PSW
(T2CON)

07

(RCAP2L)

(RCAP2H)

(TL2)

CF

(TH2)

C7

IP
P3
IE
P2
SCON
P1
TCON
PO

BF
B7

AF
..

A7

SBUF

9F

97

TMOO
SP

TLO
OPL

THO

Tl1
OPH

TH1

8F

PCON

87

Figure 2. SFR Map. ( ... ) Indicates Resident in 8052s, not in 8051s
Note that not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect.

to hold a 16-bit address. It may be manipulated as a
16-bit register or as two independent 8-bit registers.

User software should not write Is to these unimplemented locations, since they may be used in future
MCS-51 products to invoke new features. In that case
the reset or inactive values of the new bits will always
be 0, and their active values will be 1.

PO, PI, P2 and P3 are the SFR latches of Ports 0, I, 2
and 3, respectively.

The functions of the SFRs are outlined below.
ACCUMULATOR
ACC is the Accumulator register. The mnemonics for
Accumulator-Specific instructions, however, refer to
the Accumulator simply as A.

PORTS 0 T03

SERIAL DATA BUFFER
The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive· buffer register.
When data is moved to SBUF, it goes to the transmit
buffer where it is held for serial transmission. (Moving
. a byte to SBUF is what initiates the transmission.)
When data is moved from SBUF, it comes from the
receive buffer.

B REGISTER

TIMER REGISTERS

The B register is used during mUltiply and divide operations, For other instructions it can be treated as another scratch pad register.

Register pairs (THO, TLO), (THI, TLI), and (TH2,
TL2) are the 16-bit Counting registers for Timer/Counters 0, I, and 2, respectively.

PROGRAM STATUS WORD

CAPTURE REGISTERS

The PSW register contains program status information
as detailed in Figure 3.

The register pair (RCAP2H, RCAP2L) are the. Capture registers for the Timer 2 "Capture Mode." In this
mode, in response to a transition at the 8052's T2EX
pin, TH2 and TL2 are copied into RCAP2H and
RCAP2L. Timer 2 also has a 16-bit auto-reload mode,
and RCAP2H and RCAP2L hold the reload value for
this mode. More about Timer 2's features in a later
section.

STACK POINTER
The Stack Pointer Register is 8 bits wide. It is incremented before data is stOred during PUSH and CALL
executions. While the stack may reside anywhere in onchip RAM, the Stack Pointer is initialized to 07H after
a reset. This causes the stack to begin at location 08H.

CONTROL REGISTERS

DATA POINTER

Special Function Registers IP, IE, TMOD, TCON,
T2CON, SOON, and PCON contain control and status
bits for the interrupt system, the Timer/Counters, and
the seri?-, port. They are described in later sections.

The Data Pointer (DPTR) consists of a high byte
(DPH) and a low byte (DPL). Its intended function is

6-2

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

(MSB)

(LSB)

CY
Symbol

Position

CY
AC

PSW.7
PSW.6

FO

PSW.5

RSI
RSO

PSW.4
PSW.3

AC

FO

RSI

RSO

Name and Significance
Carryllag.
Auxiliary Carry flag.
(For BCD operations.)
Flag 0
(Available to the user for general
purposes.)
Register bank select control bits I &
O. Sellcleared by software to
determine working register bank (see
Note).

P

OV

Symbol

Position

OV

PSW.2
PSW.I
PSW.O

P

Name and Significance
Overflow flag.
User definable lIag.
Parity flag.
Sell cleared by hardware each
instruction cycle to indicate an odd/
even number of "one" bits in the
Accumulator, i.e., even parity.

NOTE:
The contents of (RSI, RSO) enable the working register banks as
follows:
(O.O)-Bank 0
(00H-07H)
(OBH-OFH)
(0.1 )-Bank I
(I.O)-Bank 2
(IOH-17H)
(I. I)-Bank 3
(IBH-IFH)

Figure 3. PSW: Program Status Word Register
READ
.LATCH

ADDR/DATA
CONTROL

VCC

WRITE
TO
LATCH

INT. ",BU::.::S,--+~
WRITE
TO
LATCH

READ
PIN

READ
PIN

270252-3
270252-2

B. Port 1 Bit

A. PortO Bit

ALTERNATE
OUTPUT
FUNCTION

ADDR
READ

LATCH

READ
LATCH

INT. BUS
INT. BUS

WRITE
TO
LATCH

WRITE
TO
LATCH

READ
PIN

ALTERNATE
INPUT
FUNCTION

270252-4

270252-5

C. Port 2 Bit

D. Port 3 Bit

Figure 4. 8051 Port Bit Latches and 1/0 Buffers
'See Figure 5 for details of the internal pullup.

external memory address, time-multiplexed with the
byte being written or read. Port 2 outputs the high byte
of the external memory address when the address is 16
bits wide. Otherwise the Port 2 pins continue to emit
the P2 SFR content.

PORT STRUCTURES AND
OPERATION
All four, ports in the 8051 are bidirectional. Each eon-'
sists of a latch (Special Function Registers PO through
P3), an output driver, and an input buffer.

All the Port 3 pins, and (in the 8052) two Port 1 pins
are multifunctional. They are not only port pins, but
also serve the functions of various special features as
listed on the following page.

The output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to external memory.
In this application, Port 0 outputs the low byte of the

6·3

inter
Port Pin
·Pl.0
·P1.l
P3.0
P3.l
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

ADDR/DATA BUS). To be used as an input, the port
bit latch must contain a I, which tums off the output
driver PET. Then, for Ports I, 2, and 3, the pin is
pulled high by the internal pullup, but can be pulled
low by an external source.

Alternate Function
T2 (Timer/Counter 2
external input)
T2EX (Timer/Counter 2
Capture/Reload trigger)
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt)
INT1 (external interrupt)
TO (Timer/Counter 0 external
input)
Tl (Timer/Counter 1 external
input)
WR (external Data Memory
write strobe)
RD (external Data Memory
read strobe)

Port 0 differs in not having internal pull ups. The pullup
FET in the PO output driver (see Figure 4) is used only
when the Port is emitting Is during external memory
accesses. Otherwise the pullup PET is off. Consequently PO lines that are being used as output port lines are
open drain. Writing a 1 to the bit latch leaves both
output PETs off, so the pin floats. In that condition it
can be used a high-impedance input.
Because Ports 1, 2, and 3 have fixed internal pullups
they are sometimes called "quasi-bidirectional" ports.
When configured as inputs they pull high and will
source current (ilL, in the data sheets) when externally
pulled low. Port 0, on the other hand, is considered
"true" bidirectional, because when configured as an input it floats.

·Pl.O and P1.l serve these alternate functions only on
the 8052.
The alternate functions can only be activated if the corresponding bit ,latch in the port SFR,contains a 1. Otherwise the porl pin is stuck at O.

All the port latches in the 8051 have Is written to them
by the reset function. If a 0 is subsequently written to a
port latch, it can be reconfigured as an input by writing
altoit.

1/0 Configurations
Writing to a Port

Figure 4 shows a functional diagram of a typical bit
latch and I/O buffer in each of the four ports. The bit
latch (one bit in the port's SFR) is represented as a
Type D flip-flop, which will clock in a value from the
internal bus in response to a "write to latch" signal
from the CPU. The Q output of the flip-flop is placed
on the internal bus in response to a "read latch" signal
from the CPU. The level of the port pin itself is placed
on the internal bus in response to a "read pin" signal
from the CPU. Some instructions that read a port activate the "read latch"signal, and others activate the
"read pin" signal. More about that later.

In the execution of an instruction that changes the value in a port latch, the new value arrives at the latch
during S6P2 of the final cycle of the instruction. However, port latches are in fact sampled by their output
buffers only during Phase 1 of any clock period. (During Phase 2 the output buffer holds the value it saw
during the previous Phase 1). Consequently, the new
value in the port latch won't actually appear at the
output pin until the next Phase I, which will be at SIPI
of the next machine cycle.

As shown in Figure 4, the output drivers of Ports 0 and
2 are switchable to an internal ADDR and ADDR/
DATA bus by an internal CONTROL signal for use in
external memory accesses. During external memory accesses, the P2 SFR remains unchanged, but the PO SFR
gets Is written to it:

If the change requires a O-to-l transition in Port I, 2, or
3, an additional puiiup is turned on during SiPi and
SIP2 of the cycle in which the transition occurs. This is
done to increase the transition speed. The extra pullup
can source about 100 times the current that the normal
pullup can. It should be noted thaf the internal pull ups
are field-effect transistors, not linear resistors. The pullup arrangements are shown in Figure 5.

Also shown in Figure 4, is that if a P3 bit latch contains
a I, then the output level is controlled by the signal
labeled "alternate output function." The actual P3.x
pin level is always available to the pin's alternate input
function, if any.

In HMOS versions of the 8051, the fixed part of the
pullup is a depletion-mode transistor with the gate
wired to the source. This transistor will allow the pin to
source about 0.25 mA when shorted to ground. In
parallel with the fixed pullup is an enhancement-mode
transistor, which is activated during SI whenever the
port bit does a O-to-I transition. During this interval, if
the port pin is shorted to ground, this extra transistor
will allow the pin to source an additional 30 mAo

Ports 1,2, and 3 have internal pullups. Port 0 has open
drain outputs. Each I/O line can be independently used
as an' input or an output. (Ports 0 and 2 may not be
used as general purpose I/O when being used as the
6-4

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

VCC
2 OSC. PERIODS

aD

ENHANCEMENT MODE FET

~
270252-6

A. HMOS Configuration. The enhancement mode transistor
is turned on for 2 osc. periods after Q makes a 1-to-0 transition.
Vcc

Vcc

Vcc

a

FROM PORT
LATCH

READ
PORT PIN

270252-7

B. CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after Q
makes a 1-to-0 transition. During this time, pFET 1 also turns on pFET 3
through the inverter to form a latch which holds the 1. pFET 2 is also on.
Figure 5. Ports 1 And 3 HMOS And CHMOS Internal Pullup Configurations.
Port 2 is Similar Except That It Holds The Strong Pull up On While Emitting
1s That Are Address Bits. (See Text, "Accessing External Memory".)

In the CHMOS versions, the pullup consists of three
pFETs. It should be noted that an n-channel FET
(nFEl) is turned on when a logical 1 is applied to its
gate, and is turned off when a logical 0 is applied to its
gate. A p-channel FET (PFET) is the opposite: it is on
when its gate sees a 0, and off when its gate sees a 1.

Port Loading and Interfacing
The output buffers of Ports 1,2, and 3 can each drive 4
LS TIL inputs. These ports on HMOS versions can be
driven in a normal manner by any TIL or NMOS circuit. Both HMOS and CHMOS pins can be driven by
open-collector and open-drain outputs, but note that 0to-1 transitions will not be fast. In the HMOS device, if
the pin is driven by an open-collector output, a 0-tO-1
transition will have to be driven by the relatively weak
depletion mode FET in Figure 5(A). In the CHMOS
device, an input 0 turns off pullup pFET3, leaving only
the very weak pullup pFET2 to drive the transition.

pFETl in Figure 5 is the transistor that is turned on for
2 oscillator periods after a 0-to-1 transition in the port
latch. While it's on, it turns on pFET3 (a weak pullup), through the inverter. This inverter and pFET form
a latch which hold the 1.
Note that ifthe pin is emitting a 1, a negative glitch on
the pin from some external source can turn off pFET3,
causing the pin to go into a float state. pFET2 is a very
weak pullup which is on whenever the nFET is off, in
traditional CMOS style. It's only about Y,0 the strength
of pFET3. Its function is to restore a 1 to the pin in the
event the pin had a 1 and lost it to a glitch.

Port 0 output buffers can each drive 8 LS TIL inputs.
They do, however, require external pullups to drive
NMOS inputs, except when being used as the
ADDRESS/DATA bus.

6-5

HARDWARE DESCRIPTION OFTHE 8051, 8052 AND 80C51

Whenever a 1'6-bit address is used, the high byte of the
address comes out on Port 2, where it is held for the
duration of the read or write cycle. Note that the Port 2
drivers use the strong pullups during the entire time
that they are emitting address bits that are Is. This is
during the execution of a MOVX @DPTR instruction.
During this time the Port 2 latch (the Special Function'
Register) does not have to contain Is, and the contents
of the Port 2 SFR are not modified. If the external
memory cycle is not immediately followed by another
external memory cycle, the undisturbed contents of the
Port ~ SFR will reappear in the next cycle.

Read-Modify-Write Feature
Some instructions that read a port read the latch and
others read the pin. Which ones do which? The instructions that read the latch rather than the pin are the ones
that read a value, possibly change it, and then rewrite it
to the latch. These are called "read-modify-write" instructions. The instructions listed below are read-modify-write instructions. When the destination operand is
a port, or a port bit, these instructions read the latch
rather than the pin:
ANL
(logical AND, e.g., ANL.PI, A)
(logical OR, e.g., ORL P2, A)
ORL
XRL
(logical EX-OR, e.g., XRL P3, A)
JBC
(jump if bit = I and clear bit, e.g.,
JBC Pl.l, LABEL)
CPL
(complement bit, e.g., CPL P3.0)
INC
(increment, e.g., INC P2)
(decrement, e.g., DEC P2)
DEC
(decrement and jump if not zero, e.g.,
DJNZ
DJNZ P3, LABEL)
MOV, PX.Y, C (move carry bit to bit-Y of Port X)
CLR PX. Y
(clear bit Y of Port X)
SETB PX. Y
(set bit Y of Port X)

If an 8-bit address is being used (MOVX @Ri), the
contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. This will facilitate paging.

In any case, the low byte of the address is time-multiplexed with the data byte on Port O. The ADDR/
DATA signal drives both FETs in the Port 0 output
buffers. Thus, in this application the Port 0 pins are not
open-drain outputs, and do' not require external pullups. Signal ALE (Address Latch Enable) should be
used to capture the address byte into an extemallatch.
The address byte is valid at the negative transition of
ALE. Then, in a write cycle, the data byte to be written
appears on Port 0 just before WR is ·activated, and remains there until after WR is deactivated. In a read
cycle, the incoming byte is accepted at Port 0 just before the read strobe is deactivated.

It is not obvious that the last three instructions in this
list are read-modify-write instructions, but they are.
They read the port byte, all 8 bits, modify the addressed
bit, then write the new byte back to the latch.

The reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a
possible misinterpretation of the voltage level at the
pin. For example, a port bit might be used to drive the
base of a transistor. When a 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same
port bit at the pin rather than the latch, it will read the
base voltage of the transistor and interpret it as a O.
Reading the latch rather than the pin will return the
correct value of 1. ' .

During any access to external memory, the CPU writes
OFFH to the Port 0 latch (the Special Function Register), thus obliterating whatever information the Port 0
SFR may have been holding.
External Program Memory is accessed under two conditions:
• 1) Whenever signal EA is· active; or
2) Whenever the program counter (PC) contains a
number that is larger than OFFFH (IFFFH for the
8052).
This requires that the ROMless versions have EA wired
low to enable the lower 4K (8K for the 8032) program
bytes to be fetched from external memory.

ACCESSING EXTERNAL MEMORY

When the CPU is executing out of external Program
Memory, all 8 bits of Port 2 are dedicated to an output
function and may not be used for general purpose I/O.
During external program fetches they output the high
byte of the PC. During this time the Port 2 drivers use
the strong pullups to emit PC bits that are Is.

Accesses to external memory are of two types: accesses
to external Program Memory and accesses to external
Data Memory. Accesses to external Program Memory
use signal PSEN (program store enable) as the read
strobe. AccesseS to external Data Memory use RD or
WR (alternate functions of P3.7 and P3.6) to strobe the
memory..

TIMER/COUNTERS

Fetches from external Program Memory always use a
16-bit address. Accesses to external Data Memory can
use either a 16-bit address (MOVX @DPTR) or an
8-bit address (MOVX @Ri).

The 8051 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. The 8052 has these two plus one
mOt;"e: Timer 2. All three can be configured to operate
either as timers or event counters.
6-6

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

In the "Timer" function, the register is incremented
every machine cycle. Thus, one can think of it as counting machine cycles. Since a !llachine cycle consists of 12
oscillator periods, the count rate is '112 of the oscillator
frequency.

MODE 0

Putting either Timer into Mode 0 makes it look like an
8048 Timer, which is an 8-bit Counter with a divide-by32 prescaler. Figure 7 shows the Mode 0 operation as it
applies to Timer 1.

, In the "Counter" function, the register is incremented
in response to a I-to-O transition at its corresponding
external input pin, TO, TI or (in the 8052) T2. In this
function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in
one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register
during S3PI of the cycle following the one in which the
transition was detected. Since it takes 2 machine cycles
(24 oscillator periods) to recognize a I-to-O transition,
the maximum count rate is '1.4 of the oscillator frequency. There are no restrictions on the duty cycle of
the external input signal, but to ensure that a given
level is sampled at least once before it changes, it
should be held for at least one full machine cycle.

In this mode, the Timer register is configured as a
13-Bit register. As the count rolls over from allis to all
Os, it sets the Timer interrupt flag TF1. The counted
input is enabled to the Timer when TRI = I and either
GATE = 0 or INTI = 1. (Setting GATE = I allows
the Timer to be controlled by external input INTI, to
facilitate pulse width measurements.) TRI is a control
bit in the Special Function Register TeON (Figure 8).
GATE is in TMOD.
The 13-Bit register consists of all 8 bits ofTHI and the
lower 5 bits of TL1. The upper 3 bits of TLI are indeterminate and should be ignored. Setting the run flag
(TR I) does not clear the registers.

In addition to the "Timer" or "Counter" selection,
Timer 0 and Timer I have four operating modes from
which to select. Timer 2, in the 8052, has three modes
of operation: "Capture," "Auto-Reload" and "baud
rate generator."

Mode 0 operation is the same for Timer 0 as for Timer
1. Substitute TRO, TFO and INTO for the corresponding Timer I signals in Figure 7. There are two different
GATE bits, one for Timer I (TMOD.7) and one for
Timer 0 (TMOD.3).

Timer 0 and Timer 1

MODE 1

Mode I is the same as Mode 0, except that the Timer
register is being run with all 16 bits.

These Timer/Counters are present in both the 8051 and
the 8052. The "Timer" or "Counter" function is selected by control bits ciT in the Special Function Register
TMOD (Figure 6). These two Timer/Counters have
four operating modes, which are selected by bit-pairs
(MI, MO) in TMOD. Modes 0, I, and 2 are the same
for both Timer/Counters. Mode 3 is different. The four
operating modes are described in the following text.

l

(MSB)

GATE

CIT

Ml

MO

MODE 2

Mode 2 configures the Timer register as an 8-bit Counter (TLJ) with automatic reload, as shown in Figure 9.
Overflow from TLI not only sets TFI, but also reloads

1

(LSB)

GATE

CIT

Ml

MO

J

T

Timer 1
GATE

cli'

Timer 0

Gating control when set. Timer /CoUl;ter '"x'" is enabled
only while '"INTx'" pin is high and '"TRx'" control pin is
set. When cleared Timer '"x" is enabled whenever
'"TRx'" control bit is set.
Timer or Counter Selector cleared for Timer operation
(input from internal system clock). Set for Counter
operation (input from '"Tx" input pin).

Ml

MO

o
o

o

Operating Mode
MCS-48 Timer '"TLx" serves as 5-bit prescaler.
IS-bit Timer/Counter '"THx" and '"TLx" are
cascaded; there is no prescaler.

o

8-bit auto-reload Timer/Counter '"THx'" holds a
value which is to be reloaded into '"TLx" each
time it overflows.
(Timer 0) TLO is an 8-bit Timer/Counter
controlled by the standard Timer 0 control bits.
THO is an 8-bittimer only controlled by Timer 1
)
control bits.
(Timer 1) Timer/Counter 1 stopped.

Figure 6. TMOD: Timer/Counter Mode Control Register

6-7

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

cif= 0
INTERRUPT

Tt PIN

__ ---,___---'t clf =1

CONTROL

-

GATE

270252-9

Figure 7. Timer/Counter 1 Mode 0: 13-Blt Counter

(MSB)
TFI

(LSB)
TRI

TFO

TRO

lEI

ITt

lEO

ITO

Symbol

Position

Name and Significance

Symbol

Position

Name,and Significance

TFI

TCON.7

Timer I overflow Flag. Set by
hardware on TImer/Counter overflow.
Cleared by hardware lNhen processor
vectors to inter!'IJpt routine.

lEI

TCON.3

Interrupt I Edge flag. Set by hardware
when external interrupt edge
detected. Cleared when interrupt
processed.

TRI

TCON.6

Timer I Run control bit. Sell cleared
by software to turn Timer/Counter on/
off.

ITt

TCON.2

TFO

TCON.5

Timer 0 overflow Flag. Set by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.

Interrupt I Type control bit. Sell
cleared by soltware to specify falling
edge/low level triggered external
interrupts.

lEO

TCON.I

Interrupt 0 Edge lIag. Set by hardware
when external Interrupt edge
detected. Cleared when interrupt
processed.

ITO

TCON.O

Interrupt 0 Type control bit. Set!
cleared by software to specify falling
edge/low level triggered external
interrupts.

TRO

TCON.4

Timer 0 Run control bit. Set/cleared
by software to turn Timer/Counter on/
off.

Figuie a.TeON: Timer/Counter Centro! Register

CIT, GATE, TRO, INTO, and TFO. THO is locked into

TLl with the contents ofTHI, which is preset by software. The reload leaves THI unchanged.

a timer function (counting machine cycles) and takes
over the use ofTRI and TFI from Timer 1. Thus, THO
now controls the "Timer I" interrupt.

Mode 2 operation is the same for Timer/Copnter O.

Mode 3 is provided for applications requiring an extra
8-bit timer or counter. With Timer 0 in Mode 3, an
8051 can look like it has three Timer/Counters, and an
8052, like it has four. When Timer 0 is in Mode 3,
Timer 1'can be turned on and offby switching it out of
and into its own Mode 3, or can still be used by the
serial port as a baud rate generator, or in fact, in any
application not requiring an interrupt.

MODE 3

Timer I in Mode 3 simply holds its count. The effect is
the same as setting TRI = O.
Timer 0 in Mode 3 establishes TLO and THO as two
separate counters. The logic for Mode 3 on Timer 0 is
shown in Figure 10. TLO uses the Tinier 0 control bits:

6-8

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

INTERRUPT

270252-10

Figure 9. Timer/Counter 1 Mode 2: a-Bit Auto-Reload

osc

~B-

1112 lose

1/12 lose - - - - - - - ,

INTERRUPT

TO

PIN-----~

CONTROL

1112 lose

I· L.1_(_~_I_~) HL._TF_1-.1~'INTERRUPT

--------'-'--:---+1---<1
_ __
'TR1

.....

~____~=ieoNTRoL
-

270252-1,1

Figure 10. Timer/Counter 0 Mode 3: Two a-Bit Counters

Timer 2
Table 2. Timer 2 Operating Modes
Timer 2 is a 16-bit Timer/Counter which is present
only in the 8052. Like Timers 0 and I, it can operate
either as a timer or as an event counter. This is selected .
by bit C/T2 in the Special Function Register T2CON
(Figure 11). It has three operating modes: "capture,"
"auto-load" and, "baud rate generator," which are selected by bits in T2CON as shown in Table 2.

6-9

RCLK

+ TCLK CP/RL2 TR2
0
0
1
X

0
1
X
X

1
1
1
0

Mode
16-bit Auto~Reload
16-bit Capture
Baud Rate Generator
(off)

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

(MSB)
TF2

(LSB)
EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

cPlFi1:2

Symbol

Position

TF2

T2CON.7

TImer 2 overflow flag set by a Timer 2 overflow and must be cleared by software.
TF2 will not be set when eHher RCLK = 1 or TCLK = 1.

Name and Significance

EXF2

T2CON.6

Timer 2 external flag set when either a capture or reload Is caused by a negative
transition on T2EX and EXEN2 = 1. When TImer 2 Interrupt is enabled, EXF2 = 1
will cause the CPU to vector to the TImer 2 Interrupt routine. EXF2 must be
cleared by software.

RCLK

T2CON.5

Receive clock flag. When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock In Modes 1 and 3. RCLK = 0 causes TImer 1 overflow
to be used for the receive clock.

TCLK

T2CON.4

TransmH clock fleg. When set, causes the serial port to use TImer 2 overflow
pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1
overflows to be used for the transmit clock.

EXEN2

T2CON.3

TImer 2 external enable flag. When set, allows a capture or reload to occur as a
result of a negative transition on T2EX nTimer 2 is not being used to clock the
serial port. EXEN2 = 0 causes TImer 2 to Ignore events at T2.EX.

TR2

T2CON.2

Start/stop control for TImer 2. A logic 1 starts the timer.

C/T2

T2CON.1

Timer or counter select. (TImer 2)
o = Internal timer (OSC/12)
1 = External event counter (falling edge triggered) ..

CP/RL2

T2CON.O

Capture/Reload flag. When set captures will occur on negatiVe transitions at
T2EX,if EXEN2 = 1. When cleared, auto-reloads will occur either with TImer 2
overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK
= 1 or TCLK = 1, this bit Is ignored and the timer Is forced to auto-reload on
TImer 2 overflow.

FIgure 11. T2CON: TImer/Counter 2 Control RegIster
In the Capture Mode there are two options which are
selected by bit EXEN2 in T2CON. If EXEN2 = 0,
then Timer 2 is a 16-bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit,
which can be used to generate an interrupt. If EXEN2
= 1, then Timer 2 still does the above, but with the
added feature that a 1-to-O transition at external input
T2EX causes the current value in the Timer 2 registers,
TL2 and TH2, to be captured into registers RCAP2L
and RCAP2H, respectively. (RCAP2L and RCAP2H
are new Special Function Registers in the 8052.) In
addition, the transition at T'2EX causes bit EXF2 in
T2CON to be set, and EXF2, like TF2, can generate an
interrupt.
The Capture Mode is illustrated in Figure 12.
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0, then when Timer 2 rolls over it not only
sets TF2 but also causes the Timer 2 registers to be
reloaded with the 16-bit value in registers RCAP2L
and RCAP2H, which are preset by software. IfEXEN2
= I, then Timer 2 still does the above, but with the

added feature that a 1-to-0 transition at external input
T2EX.will also trigger the 16"bit reload and set EXF2.
The auto-reload mode is illustrated in Figure 13.
The baud rate generator mode is selected by RCLK =
1 andlor TCLK = 1. It will be described in conjunction with the serial port.

SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit
.and receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
before a previously received byte has been read from
the receive register. (However, if the first byte still
hasn't been read by the time reception of the second
byte is complete, one of the bytes will be lost). The
serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to
SBUF loads the transmit register, and reading SBUF
accesses a physically separate receive register.

6-10

intJ

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

nMER2
INTERRUPT

EXEN2

270252-12

Figure 12. Timer 2 in Capture Mode

The serial port can operate in 4 modes:

Multiprocessor Communications

Mode 0: Serial data enters and exits through RXD.
TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at
1/12 the oscillator frequency.

Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are
received. The 9th one goes into RB8. Then comes a
stop bit. The port can be programmed such that when
the stop bit is received, the serial port interrupt will be
activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in
multiprocessor systems is as follows.

Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit goes
into RB8 in Special Function Register SCON. The
baud rate is variable.

When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address byte which identifies the target slave. An address
byte differs from a data byte in that the 9th bit is 1 in an
address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address
byte, however, will interrupt all slaves, so that each
slave can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit
and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their
SM2s set and go on about their business, ignoring the
coming data bytes.

Mode 2: 11 bits are transmitted (through TXD) or received (throughRXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit (1).
On Transmit, the 9th data bit (TB8 in SCON) can be
assigned the value of 0 or 1. Or, for example, the parity
bit (p, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Functon
Register SCON, while the stop bit is ignored. The baud
rate is programmable to either '132 or '164 the oscillator
frequency.
Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit and a stop bit (1). In
fact, Mode 3 is the same as Mode 2 in all respects
except the baud rate. The baud rate in Mode 3 is variable.

SM2 has no effect in Mode 0, and in Mode 1 can be
used to check the validity of the stop bit. In a Mode 1
reception, if SM2 = 1, the receive interrupt will not be
activated unless a valid stop bit is received.

Serial Port Control Register
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0
and REN = 1. Reception is initiated in the other
modes by the incoming start bit if REN = 1.

The serial port control and status register is the Special
Function Register SCON, shown in Figure 14. This
register contains not orily the mode selection bits, but
also the 9th data bit for transmit and receive (TB8 and
RB8), and the serial port interrupt bits (TI and RI).

6-11

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

TIMER 2
INTERRUPT

EXEN2

270252-13

Figure 13. Timer 2 in Auto-Reload Mode

(MSB)
SMO

SMI

I SM2

(LSB)
REN

Where SMO, SMI specify the serial port mode, as follows:
SMO
0
0

SMI
0
0

Mode
0
1
2

3
•

•

SM2

REN

TB8

RB8
•

Description
shift register
8·bitUART
9-bitUART

Baud Rate
fose/12
variable
fose/64
or
fose/32
9-bit UART variable

TI

TB8

is the 9th data bit that will be
transmitted in Modes 2 and 3. Set or
clear by software as desired.
In Modes 2 and 3, is the 9th data bit
that was received. In Mode I, if SM2
= 0, RB8 is the stop bit that was
received. In Mode 0, RBS is not used.

.
.

TI

is transmit interrupt flag. Set by
hardware at the end of the Sth bit time
In Mode 0, or at the beginning of the
stop bit in the other modes, in any
serial transmission. Must be cleared
by software.

•

RI

is receive interrupt flag. Set by
hardware at the end of the 8th bit time
in Mode 0, or halfway through the stop
bn time in the other modes, in any
serial reception (except see 8M2).
Must be cleared by software.

RB8

enables the multiprocessor
communication feature in Modes
2 and 3. In Mode 2 or 3, if 8M2 Is
setto 1 then RI will no! be
activated if the received 9th data
bit (RBS) is O. In Mode I, if 8M2
= 1 then RI will not be activated
if a valid stop bit was not
received. In Mode 0, 8M2 should
beO.
enables serial receotion. Set bv
software to enable reception. .
Clear by software to disable
reception.

RI

Figure 14. SCON: Serial Port Control Register

Baud Rates
The baud rate in Mode 0 is fixed:

Mode 2 Baud Rate =

Oscillator Frequency
Mode 0 Baud Rate = ---'._---''---'12

SMOD

2
64X
(Oscillator Frequency)

In the 8051, the'baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. In the 8052, these
baud rates can be determined by Timer 1, or by Timer
2, or by both (one for transmit and the other for receive).

The baud rate in Mode 2 depends on the value of bit
SMOD in Special Function Register peON. If SMOD
= 0 (which is the value on reset), the baud rate %4 the
oscillator frequency. If SMOD
1, the baud rate is
'1.2 the oscillato.r frequency.
6-12

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

Using Timer 1 to Generate Baud Rates

mode (high nibble of TMOD = OOIOB). In that case,
the baud rate is given by the formula

When Timer 1 is used as the baud rate generator, the
baud rates in Modesl and 3 are determined by the
Timer 1 overflow rate and the value of SMOD as fol~
lows:

Modes 1, 3 2SMOD Oscillator Frequency
Baud Rate = - - - X - - - - - - - - ' ' - - - - : = 32
12x [256 - (THl)l
One can achieve very low baud rates with Timer 1 by
leaving the Timer 1 interrupt enabled, and configuring
the Timer to run as a l6-bit timer (high nibble of
TMOD = OOOlB), and using the Timer 1 interrupt to
do a 16-bit software reload.

Modes 1,3 2SMOD
Baud Rate =
X (Timer 1 Overflow Rate)

----n-

The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either
"timer" or "counter" operation, and in any of its 3
. running modes. In the most typical applications, it is
configured for "timer" operation, in the auto-reload

Figure 15 lists various commonly used baud rates and
how they can be obtained from Timer 1.

Baud Rate

fosc

SMOD

Mode 0 Max: 1 MHZ
Mode 2 Max: 375K
Modes 1, 3: 62.5K
19.2K
9.6K
4.8K
2.4K
1.2K
137.5K
110K
110K

12MHZ
12MHZ
12MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.986 MHZ
6MHZ
12MHZ

X
1
1
1

a
a
a
a
a
a
a

clf
X
X
0

a
a
a
a
a
a
a
a

Timer 1
Reload
Mode
Value
X
X
X
X
2
FFH
FDH
2
2
FDH
2
FAH
F4H
2
2
E8H
2
1DH
2
72H
1
FEEBH

Figure 15. Timer 1 Generated Commonly Used Baud Rates
Using Timer 2 to Generate Baud Rates

In the 8052, Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Figure

11). Note then the' baud rates for transmit and receive
can be simultaneously different. Setting RCLK and/or
TCLK puts Timer 2 into its baud rate generator mode,
as shown in Figure 16.
nMER 1

OVERFLOW

AX CLOCK

TXCLOCK

"TIMER 2"

T2EX PIN

INTERRUPT

EX""

L

NOTE AYAILAIIU.rTY OF ADDmoNAL EXTERNAL INTERRUPT

270252-14

Figure 16. Timer 2 in Baud Rate Generator Mode
6-13

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal at S6P2 also loads a I into the 9th position ofthe
transmit shift register and tells the TX Control block to
commence a transmission. The internal timing is such
that one full machine cycle will elapse between "write
to SBUF," and activation of SEND.

The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2
registers to be reloaded with the 16-bit value in registers
RCAP2H and RCAP2L, which are preset by software.
Now, the baud rates in Modes I and 3 are determined
by Timer 2's overflow rate as follows:
Modes I, 3 Baud Rate =

SEND enables the output of the shift register to the
alternate output function line of P3.0, and also enables
SHIFT CLOCK to the alternate output function line of
P3.1. SHIFT CLOCK is low during S3, S4, and S5 of
every machine cycle, and high during S6, SI and S2. At
S6P2 of every machine cycle in which SEND is active,
the contents of the transmit shift register are shifted to
the right one position.

Timer 2 Overflow Rate
16"

The Timer can be configured for either "timer" or
"counter" operation. In the most typical applications, it
is configUred for "timer" operation (C/T2 = 0). "Timer" operation is a little different for Timer 2 when it's
'being used as a baud rate generator. Normally, as a
timer it would increment every machine cycle (thus at
'112 the oscillator frequency). As a baud rate generator,
however, it increments every state time (thus at '!. the
oscillator frequency). In that case the baud rate is given
by the formula

As data bits shift out to the right, zeroes come in from
the left. When the MSB of the data byte is at the output
position of the shift register, then the I that was initially loaded into the 9th position, is just to the left of the
MSB, and all positions to the left ofthat contain zeroes.
This condition flags the TX Control block to do one
last shift and then deactivate SEND and set TI. Both of
these actions occur at SIPI of the 10th machine cycle
after "write to SBUF."

Modes I, 3
Oscillator Frequency
Baud Rate = 32x [65536 - (RCAP2H, RCAP2L)1
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2J:, taken as a 16-bit unsigned integer.

Reception is initiated by the condition REN = I and
Rl. = O. At S6P2 of the next machine cycle, the RX
Control unit writes the bits 11111110 to the receive
shift register, and in the next clock phase activates RECEIVE.

Timer 2 as a baud rate generator is shown in Figure 16.
This Figure is valid only if RCLK + TCLK = I in
T2CON. Note that a rollover in TH2 does not setTF2,
and will not generate an interrupt. Therefore, the Timer
2 interrupt does not have to be disabled when Timer 2
is in the baud rate generator mode. Note too" that if
EXEN2 is set, a I-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
as ,a baud rate generator, T2EX can be used as an extra
external interrupt, if desired.

RECEIVE enables SHIFT CLOCK to the alternate
output function line of P3.1. SHIFT CLOCK makes
transitions at S3Pl and S6Pl of every machine cycle.
At S6P2 of every machine cycle in which RECEIVE is
active, the contents of the receive shift register are shifted to the left one position. The value that comes in
from the right is the value that was sampled at the P3.0
pin at S5P2 of the same machine cycle. '
As data bits come in from the right, Is shift out to the
left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift
register, it flags the RX Control block to do one last
shift and load SBUF. At SIP I of the 10th machine
cycle after the write to SCON that cleared RI, RECEIVE is cleared and'RI is set.

It should be noted that when Timer 2 is running (TRZ
= I) in "timer" function in the baud rate generator
mode, one should not try to read or write TH2 or TL2.
Under these conditions the Timer is being incremented
every state time, and the results of a read or write may
not be accurate. The RCAP registers may be read, but
shouldn't be written to, because a write might overlap a
reload and cause write and/or reload errors. Tum the
Timer off (clear TR2) before accessing the Timer 2 or
RCAP registers, in this case.

More About Mode '1
Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSD first),
and a stop bit (1), On receive, the stop bit goes into
RB8 in SCON. In the 8051 the'baud rate is determined
by the Timer 1 overflow rate. In the 8052 it is determined either by the Timer 1 overflow rate, or the Timer
2 overflow rate, or both (one for transmit and the other
for receive).

More About Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/received: 8
data bits (LSB first). The baud rate is fixed at 1/12 the
oscillator frequency.
Figure 17 shows a simplified functional diagram of the
serial port in Mode 0, and associated timing.

Figure 18 shows a simplified functional diagram of the
serial port in Mode 1, and associated timings for transmit receive.
6-14

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

WRITE
SBUF
TO

---'--=~~~r:--~~----1---------r-,

RXD
P3.0ALT
OUTPUT
FUNCTION

56.-_.------1
TXD
P3.1 ALT
OUTPUT
FUNCTION

' - - - - - I RX CLOCK
RX CONTROL

REN--...r--l--_ _.j START

Ri-"'~

SHIFT

L..._--i........,...-.-T""'!,......,-i---.J

RXD
P3.0ALT
INPUT
FUNCTION

READ
SBUF

ALE
4WRITE TO SBUF
SEND 88P2'
I
SHIFT
TRANSMIT

RXD (DATA OUT) \
TXD (SHIFT CLOCK)

n
-1l WRITE TO SCON (CLEAR RI)

~RIi~~~==j=::::::::::::::::::::::::::::::::::::::::::::::::::::~r----­
L-

'!!'CEIVE
SHIFT

RECEIVE

RXD (DATA IN)---.....,[}':'~---{}.!'r.!----o=-----[i=----LJ='''-----[}''~--o=-----[F-­
TXD (SHIFT CLOCK)
270252-15

Figure 17. Serial Port Mode 0

inter

HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

TIM·ER2
OVERFLOW

TIMER 1
OVERFLOW

TO
WRIT~E-r-:=jrot:m::;r~;""'~~_":-'"~_-r"""'\~;.....r-,
SBUF
TXD

RECEIVE

..

!

R";~LOC

fiTART BITI

DO

0'

62

tilT DETECTOR SAMPLE TIMES

oj

D4

..

DI

D)

SHIFT
'
___________________________________________________
~R~I

STOP BIT
~r----

270252-16

Figure 18. Serial Port Mode 1. TCLK, RCLK and timer 2 are Present in the 8052/8032 Only.

Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads a 1 into the 9th bit position of the
transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission actually
commences at SIPI of the machine cycle following the
next rollover in the divide-by-16 counter. (Thus, the bit

times are synchronized to the divide-by-16 counter, not
to the "write to SBUF" signal).
The tra:!lsinission begins with activation of SEND,
which puts the start bit at TXD. One bit time later,
DATA is activated, which enables the output bit· of the
transmit shift register to TXD. The first shift pulse occurs one bit time after that.
6-16

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

As data bits shift out to the right, zeroes are clocked in
from the left. When the MSB of the data byte is at the
output position of the shift register, then the 1 that was
initially loaded into the 9th position is just to the left of
the MSB, and all positions to the left of that contain
zeroes. This condition flags the TX Control unit to do
one last shift and then deactivate SEND and set TI.
This occurs at the 10th divide-by-16 rollover after
"write to SBUF."
Reception is initiated by a detected I-to-O transition at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and IFFH is written into the input shift
register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.

mit, the 9th data bit (TB8) can be assigned the value of
1. On receive, the 9th data bit goes into RB8 in
SCON. The baud rate is programmable to either Yo. or
'164 the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from either Timer 1
or 2 depending on the state of TCLK and RCLK.

o or

Figures 19 and 20 show a functional diagram of the
serial port in Modes 2 and 3. The receive portion is
exactly the same as in Mode I: The transmit portion
differs from Mode 1 only in the 9th bit of the transmit
shift register.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads TB8 into the 9th pit position of the
transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission commences at SIPl of the machine cycle following the next
rollover in the divide-by-16 counter. (Thus, the bit
times are synchronized to the divide-by-16 counter, not
to the "write to SBUF" signal.)

The 16 states of the counter divide each bit time into
16ths. At the 7th, 8th, and 9th counter states of each bit
time, the bit detector samples the value of RXD. The
value accepted is the value that was seen in at least 2 of
the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not 0, the
receive circuits are reset and the unit goes back to looking for another I-to-O transition. This is to provide rejection of false start bits. If the start bit proves valid, it
is shifted into the input shift register, and reception of
the rest of the frame will proceed.

The transmission begins with activation of SEND,
which puts the start bit at TXD. One bit time later,
DATA is activated, which enables the output bit of the
transmit shift register to TXD. The first shift pulse occurs one bit time after that. The first shift clocks a 1
(the stop bit) into the 9th bit position of the shift register. Thereafter, only zeroes are clocked in. Thus, as
data bits shift out to the right, zeroes are clocked in
from the left. When TB8 is at the output position of the
shift register, then the stop bit is just to the left of TB8,
and all positions to the left of that contain zeroes. This
condition flags the TX Control unit to do one last shift
and then deactivate SEND and set TI. This occurs at
the lIth divide-by-16 rollover after "write to SBUF."

As data bits come in from the right, Is shift out to the
left. When the start bit arrives at the leftmost position
in the shift register, (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift,
load SBUF and RB8, and set RI. The signal to load
SBUF and RB8, and to set RI, will be generated if, and
only if, the following conditions are met at the time the
final shift pulse is generated.

Reception is initiated by a detected I-to-O transition at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and IFFH is written to the input shift
register.

1) RI = 0, and
2) Either 5M2 = 0, or the received stop bit = 1

If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met,
the stop bit goes into RB8, the 8 data bits go into
SBUF, and RI is activated. At this time, whether the
above conditions are met or not, the unit goes back to
looking for a 1-to-0 transItion in RXD.

At the 7th, 8th and 9th counter states of each bit time,
the bit detector samples the value of RXD. The valueaccepted is the value that was seen in at least 2 of the 3
samples. If the value accepted during the first bit time
is not 0, the receive circuits are reset and the unit goes
back to looking for another I-to-O transition. If the
start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame will proceed.
.
.

More About Modes 2 and 3
Eleven bits are transmitted (through TXD), or received
(throughRXD): a start bit (0),8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On trans-

6-17

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

WRITE
TO
SBUF
TXD

PHASE 2 CLOCK
('hfosc)

MODE2
TI

SMOD=l

(SMOD IS PCON.7)

SERIAL
PORT
INTERRUPT

1..-_--....
LOAD
SBUF

RXD

READ _ _......"
SBUF

:~~T~XD~}~T}A~RT~.~IT/~P~D~==~=~==~=~=~:;:;~:;~:;~C::::

)\TRANSMIT

TI

~------~------------------------------

____________~r--270252-17

Figure 19. Serial Port Mode 2

6-18

infef

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

TIMER"
OVERFLOW

TIMER 2
OVERFLOW

TXD

TCLK -

SEND

LOAD
SBUF
SHIFT

1------...,

RXD

TX
~FLOC~~~~~=-~L-~L--IL--~L-~L-~I--JL--~L-~L-~.L--­

---A WRITE TO SBUF

~

DATA
SHIFT

L

SEND
S1P1 I

----riD\'TARTBIT/

TRANSMIT
DO

TI

I

STOP BIT GEN
RX
CLOCK

RECEIVE

RXD BIT DETECTORI START BIT /
SAMPLE TIMES
~ __~'L__~L_ _~L_ _"L_~L-_~L_ _~L___JL-__~L-_ _ _
SHIFT
_______________________________
~RI~

~r-----

270252-18

Figure 20. Serial Port Mode 3. TCLK, RCLK, and Timer 2 are Present in the 8052/8032 Only.

6-19

, intJ

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

was transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware.

As data bits come in from the right, Is shift out to the
left. When the start bit arrives at the leftmost position
in the shift register (which in Modes 2 and 3 is a 9-bit
register), it flags the RX Control block to do one last
shift, load SBUF and RB8, and set RI. The signal to
load SBUF and RB8, and to set RI, will be generated if,
and only if, the following conditions are met at the time
the final shift pulse is generated:
1) RI = 0, and
2) Either 5M2 = 0 or the received 9th data bit

The Timer 0 and Timer 1 Interrupts are generated by
TFO and TFI, which are set by a rollover in theirrespective Timer/Counter registers (except see Timer 0 in
Mode 3). When a timer interrupt is generated, the flag
that generated it is cleared by the on-chip hardware
when the service routine is vectored to.

=1

If either of these conditions is not met, the received
frame is irretrievably lost, and RI is not set. If both
conditions are met, the received 9th data bit goes into
RB8, and the first 8 data bits go into SBUF. One bit
time later, whether the above conditions were met or
not, the unit goes back to looking for a I-to-O transition
at the RXD input.

.The Serial Port Interrupt is generated by the logical OR
of RI and TI. Neither of these flags is Cleared by hardware when the service routine is vectored to. In fact,
the service routine will normally have to determine
whether it was RI or TI that generated the interrupt,
and the bit will have to be Cleared in software.
In the 8052, the Timer 2 Interrupt is generated by the
logical OR of TF2 and EXF2. Neither of these flags is
Cleared by hardware when the service routine is vec-.
tored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the
interrupt, and the -bit will have to be cleared in 80ftware.

Note that the value of the received stop bit is irrelevant
to SBUF, RB8, or RI.

INTERRUPTS
The 8051 provides 5 interrupt sources. The 8052 provides 6. These are shown in Figure 21.

All of the bits that generate interrupts can be set or
Cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts
can be generated or pending interrupts can be canceled
in software.

The External Interrupts INTO and INTI can each be
either level-activated or transition-activated, depending
on bits ITO and ITI in Register TCON. The flags that
actually generate these interrupts are bits lEO and lEI
in TCON. When an external interrupt is generated, the
flag that generated it is cleared by the hardware when
the service routine is vectored to only if the interrupt

(MSB)

(LSB)

1~1-1~1~lml~I~I~1
Symbol
~

Position
IE.7

IE.6

reserved.

ET2

IE.5

enables or disables the Timer 2
Overflow or caoture interruot. If ET2
= 0, the Timer 2 Interrupt is disabled.

ES

IE.4

enables or disables the Serial Port
interrupt. If ES = O. the Serial Port
interrupt is disabled.

ETI

IE.3

enables or disables the Timer 1
Overflow interrupt. If En = O. the
Timer 1 interrupt Is disabled:

EXI

IE.2

enables. or disables External Interrupt
1. If EXI = O. External Interrupt 1 is
disabled.

ETO

IE.l

enables or disables the Timer 0
Overflow interrupt. If ETO = 0, the
Timer 0 interruptis disabled.

EXO

lE.O

enables or disables External Interrupt
O. If EXO = 0, External Interrupt 0 is
disabled.

TFO'---------·
INTERRUPT
SOURCES

~,--------~~

Function
disables all interrupts. If EA = 0, no
interrupt will be acknowledged. .If EA
= 1. each interrupt source Is
individually enabled or disabled by
selling or clearing its enable bH.

User sdftware should never write 1s to unimplemented bits,
since they [!lay be used in future MC5-51 products.

270252-19

Figure 21. MCS®·51 Interrupt Sources

Figure 22. IE: Interrupt Enable Register
6-20

intJ

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence, as follows:

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special
Function Register IE (Figure 22). IE contains also a
global disable bit, EA, which disables all interrupts at
once.
Note in Figure 23 that bit position IE.6 is unimplemented. In the 805 Is, bit position IE.5 is also unimplemented. User software should not write Is to these bit
positions, since they may be used in future MCS-51
products.

1.
2.

3.
4.
5.
6.

Priority Level Structure
Each interrupt source can also be individually programmed to one of two priority levels by setting or
clearing a bit in Special Function Register IP (Figure
23). A low-priority interrupt can itself be interrupted
by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source.
(MSB)

reserved

IP.6

reserved

PT2

IP.5

defines the Timer 2 interrupt priority
level. PT2 = 1 programs it to the
higher priOrity level.

PS

IP.4

defines the Serial Port interrupt priority
level. PS = 1 programs it to the
higher priority level.

PTl

IP.3

defines the Timer 1 interrupt priority
level. PTl = 1 programs it to the
higher priority level.

PTO

IP.l

defines the Timer 0 interrupt priority
level. PTO = 1 programs it to the
higher priority level.

PXO

IP.O

defines the External Interrupt 0 priority
level. PXO = 1 programs it to the
higher priority level.

(highest)

(lowest)

The IP register contains a number of unimplemented
bits. IP.7 and IP.6 are vacant in the 8052s, and in the
8051s these and IP.5 are vacant. User software should
not write Is to these bit positions, since they may be
used in future MCS-51 products.

(LSB)

Position
IP.7

Priority Within Level

lEO
TFO
IE1
TF1
RI +TI
TF2 + EXF2

Note that the "priority within level" structure is only
used to resolve simultaneous requests of the same priority leveL

1-1-1~1~lrnl~I~I~1
Symbol

Source

Function

How Interrupts Are Handled
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle
will find it and the interrupt system will generate an
LCALL to the appropriate service routine, provided
this hardware-generated LCALL is not blocked by any
of the following conditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The cUrrent (polling) cycle is not the final cycle in
the execution of the instruction in progress.
3. The instruction in progress is RET! or any write to
the IE or IP registers.

User software should never write 1s to unimplemented bits,
since they may be used in future MCS·51 products.

Any of these three conditions will block the generation
of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be

Figure 23. IP: Interrupt Priority Register

· · · · · · · · - - C l -...._1" ' - - C 2 - -••+I---C3--~I".--C4--'_1. - - C 5 - - · · · ..
IS5P21

5&

········~'\---'-----=l.llli---L---l'l:l-----L----

f'7't

INTERRUPT
GOES
ACTIVE

INTERRUPT
LATCHEO

LONG CALL TO
INTERRUPT
VECTOR AOORESS

INTERRUPTS
ARE POLLED

INTERRUPT ROUTIN.E

270252-20

This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.

Figure 24. Interrupt Response Timing Diagram
6-21

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is
RETI or any access to IE or IP, then at least one more
instruction will be executed before any interrupt is vectored to.

External Interrupts
The external sources can be programmed to be level-activated or transition-activated by setting or clearing bit
ITt or ITO in Register TCON. If ITx = 0, external
interrupt x is triggered by a detected low at the INTx
pin. If ITx = 1, external interrupt x is edge-triggered.
In this mode if successive samples of the INTx pin
show a high in one cycle and a low in the next cycle,
interrupt request flag lEx in TCON is set. Flag bit lEx
then requests the interrupt.

The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at
S5P2 of the previous machine cycle. Note then that if
an interrupt flag is active but not being responded to for
one of the above conditions, if the flag is not still active
when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact
that the interrupt flag was once active but not serviced
is not remembered. Every polling cycle is new.

Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at
least 12 oscillator periods to ensure sampling. If the
external interrupt is transition-activated, the external
source has to hold the request pin high for at least one
cycle, and then hold it low for at least one cycle to
ensure that the transition is seen so that interrupt request flag lEx will be set. lEx wiil be automatically
cleared by the CPU when the service routine is called.

The polling cycle/LCALL sequence is illustrated in
Figure 24.
Note that if an interrupt of higher priority level goes
active prior to S5P2 of the machine cycle labeled C3 in
Figure 24, then in accordance with the above rules it
will be vectored to during C5 and C6, without any instruction of the lower priority routine having been executed.
'

If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is
completed, or else another interrupt will be generated.

Thus the processor acknowledges an interrupt request
by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears
the flag that generated the interrupt, and in other cases
it doesn't. It never clears the Serial Pcirt or Timer 2
flags. This has to be done in the user's software. It
clears an external interrupt flag (lEO or lEI) only if it
was transition-activated. The hardware-generated
LCALL pushes the contents of the Program Counter
onto the stack (but it does not,save the PSW) and reloads the PC with an address that depends on the
source of the interrupt being vectored to, as shown below.
'

lEO

Vector
Address
0003H

TFO

OOOBH

IE1
TF1
RI + TI
. TF2 + EXF2

0013H
001BH
0023H
002BH

Source

Response Time
The INTO and INTI levels are inverted and latched
into lEO and lEI at S5P2 of every machine cycie. The
values are not actually polled by the circuitry until the
next machine cycle. If a request is active and conditions
are right for it to be acknowledged, a, hardware subroutine call to the requested service routine will be the next
instruction to be executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapse between activation of an external interrupt
request and the beginning of execution of the first instruction of the service routine. Figure 24 shows interrupt response timings.

Execution proj::eeds from that location until the RET!
instruction is encountered. The RETI instruction in-'
forms the processor that this interrupt routine is no
longer in progress, then pops the top two bytes from the
stack and reloads the Program Counter. Execution of
the interrupted program continues from where it left
otT.
Note that a simple RET instruction would also have
returned execution to the interrupted program, but it
would have left the interrupt control system thinking
an interrupt was still in progress.

A longer response time would result if the request is
blocked by one of the 3 previously listed conditions. If
an interrupt of equal or higher priority level is already
in progress, the additional wait time obviously depends
on the nature of the other interrupt's service routine. If
the instruction in progress is not in its final cycle, the
additional'wait time cannot be more than 3 cycles, since
the longest instructions (MUL and DIY) are OIily 4
cycles long, and if the instruction in progress is RET!
or an access to IE or IP, the additional wait time cannot be inore than 5 cycles (a maximum of one more
cycle to complete the instruction in progress, plus 4
cycles to complete the next instruction if the instruction
is MUL or DIY).
Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 9 cycles.

6-22

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

SINGLE-STEP OPERATION

RESET

The 8051 interrupt structure allows single-step execution with very little software overhead. As previously
noted, an interrupt request will not be responded to
while an interrupt of equal priority level is still in progress, nor will it be responded to after RET! until at
least one other instruction has been executed. Thus,
once an interrupt routine has been entered, it cannot be
re-entered until at least one instruction of the interrupted program is executed. One way to use this feature for
single-stop operation is to program one of the external
interrupts (say, INTO) to be level-activated. The service
routine for the interrupt will terminate with the following code:

The reset input is the RST pin, which is the input to a
Schmitt Trigger.
A reset is accomplished by holding the RST pin high
for at least two machine cycles (24 oscillator periods),
while the oscillator is running. The CPU responds by
generating an internal reset, with the timing shown in
Figure 25.
The external reset signal is asynchronous to the internal
clock. The RST"pin is sampled during State 5 Phase 2
of every machine cycle. The port pins will maintain
their current activities for 19 oscillator periods after a
logic 1 has been sampled at the RST pin; that is, for 19
to 31 oscillator periods after the external reset signal
has been applied to the RST pin.

JNB P3.2,$ ;Wait Here Till INTO Goes High
"JB
P3.2,$ ;Now Wait Here Till it Goes Low
RETI
:Go Back and Execute One Instruction

While the RST pin is high, ALE and PSEN are weakly
pulled high. After RST is pulled low, it will take 1 to 2
machine cycles for ALE and PSEN to start clocking.
For this reason, other devices can not be synchronized
to the internal timings of the 8051.

Now if the INTO pin, which is also the P3.2 pin, is held
normally low, the CPU will go right into the External
Interrupt 0 routine and stay there until INTO is pulsed
(from low to high to low). Then i~ will execute RET!,
go back to the task program, execute one instruction,
and immediately re-enter the External Interrupt 0 routine to await the next pulsing of P3.2. One step of the
task program is executed each time P3.2 is pulsed.

The internal reset algorithm writes Os to all the SFRs
except the port latches, the Stack Pointer, and SBUF.
The port latches are initialized to FFH, the Stack
Pointer to 07H, and SBUF is+indeterminate. Table 3
lists the SFRs and their reset values.
The internal RAM is not affected by reset. On power
up the RAM content is indeterminate.

1---12 05C. PERIOD5

---I

1 55 1 56 1 51 1 52 1 53 1 54 1 55 1 56 1 51 1 52 1 53 -1 54 1 55 1 561 51 1 52 1 53 1 541
R5T:

~L IIIIIIIII /~
,

,

5AMPLE R5T

5AMPLE R5T

CINTERNAL RE5ET 51GNAL
-

P5EN:

po:

,
- - 1 1 05C. PERIOD5 -

........, ...- - - - - 1 9 05C. PERIOD5

-----<....,
270252-33

Figure 25. Reset Timing

6-23

intJ

HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Table 3 Reset Values of the SFRs
SFRName

PC
ACC
B
PSW
SP
DPTR
PO-P3
IP (8051)
IP (8052)
IE (8051)
IE (8052)
TMOD
TCON
THO
TLO
TH1
TL1
TH2 (8052)
TL2 (8052)'
RCAP2H (8052)
RCAP2L (8052)
SCON
'SBUF
PCON (HMOS)
PCON(CHMOS)

Reset Value
OOOOH
OOH
OOH
OOH
07H
OOOOH
FFH
XXXOOOOOB
XXOOOOOOB
OXXOOOOOB
oxOOqOOOB
OOH
OOH
OOH
OOH
OOH
OOH
DOH
OOH
OOH
OOH
OOH
Indeterminate
OXXXXXXXB
OXXXOOOOB

POWER-ON RESET
An automatic reset can be obtained when VCC is
turned on by connecting the RST pin to VCC through a
10 /Lf capacitor and to VSS through an 8.2 Kn resistor,
providing the VCC risetime does not exceed a millisecond and the oscillator start-up time does not exceed 10
milliseconds. This power-on reset circuit is shown in
Figure 26. The CHMOS devices do not require the
8.2K pulldown resistor, although its presence does no
harm.
When power is turned on the circuit holds the RST pin
high for an amount of time that depends on the value of
the capacitor and the rate at which it charges. To ensure a good, reset the RST pin must be high long
enough to allow the oscillator time to start up (normally a few msec) plus two machine cycles.
Note that the port pins will be in a random state until the
oscillator has started and the internal reset algorithm
has written Is to them.

With this circuit, reducing VCC quickly to 0 causes the
RSTpin voltage to momentarily fall below OV. Howev, er, this voltage is internally limited, and will not harm
the device.

POWER-SAVING MODES OF
OPERATION
For appiications where power consumption is critical
the CHMOS version provides power reduced modes of
operation as a standard feature. The power down mode
in HMOS devices is no longer it standard feature and is.
being phased out.

CHMOS Power Reduction Modes
CHMOS versions' have two power-reducing modes,
Idle and Pciwer Down. The input through which backup power is supplied during these operations is VCC.
Figure 27 shows the internal circuitry which implelllents these featureS. In the Idle mode (IDL = 1), the
oscillator continues to run and the Interrupt, Serial
Port, and Timer blocks continue to be clocked, but the
clock signal is gated off to the CPU. In Power Down
(PD = I), the oscillator is frozen. The Idle and Power
Down modes are activated by setting bits in Special
Function Register PCON. The address of this register
is 87H. Figure 26 details its contents.

8051

.---,--1 RST
8.2Kll

In the HMOS devices the PCON register only contains
SMOD. The other four bits are implemented only in
the CHMOS devices. User software should never write
Is to unimplemented bits, since they may be used in
future MCS-51 products.

~---;VSS

270252-21

IDLE MODE

Figure 26. Power on ResetClrcult

An instruction that sets PCON.O causes that to be the
last instruction executed before going into the Idle
6-24

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

mode. In the Idle mode, the internal clock signal is
gated off to the CPU, but not to the Interrupt, Timer,
and Serial Port functions. The CPU status is preserved
in its entirety: the Stack Pointer, Program Counter,
Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins
hold the logical states they had at the time Idle was
activated. ALE and PSEN hold at logic high levels.

The flag bits GFO and GFI can be used to give an
indication if an interrupt occurred during normal operation or during an Idle. For example, an instruction
that activates Idle can also set one or both flag bits.
When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.

There are two ways to terminate the Idle. Activation of
any enabled interrupt will cause PCON.O to be cleared
by hardware, terminating the Idle mode. The interrupt
will be serviced, and following RETI the next instruction to' be executed will be the one following the instruction that put the device into Idle.

~

XTAL 2

=

XTAL 1

INTERRUPT,
i-r-C>SERIAL PORT,
TIMER BLOCKS
CPU

POWER DOWN MODE

Figure 27. Idle and Power Down Hardware
(MSB)

(LSB)
GF1

GFO

PD

IDL

Symbol

Posltlo'n

Name and Function

SMOD

PCON.7

Double Baud rate bit. When set to a 1
and Timer 1 is used to generate baud
rate, and the Serial Port is used in
modes 1, 2, or 3.

PCON.S

(Reserved)

PCON.5

(Reserved)

PCON.4

(Reserved)

GF1

PCON.3

General-purpose flag bit.

GFO

PCON.2

General-purpose flag bit.

PD

PCON.1

Power Down bit. Setting this bit
activates power down operation.

IDL

PCON.O

Idle mode bit. Setting this bit activates
idle mode operation.

The signal at the RST pin clears the IDL bit directly
and asynchronously. At this time the CPU resumes
program execution from where it left off; that is, at the
instruction following the one that invoked the Idle
Mode. As shown in Figure 25, two or three machine
cycles of program execution may take place before the
internal reset algorithm takes control. On-chip hardware inhibits access to the internal RAM during this
time, but access to the port pins is not inhibited. To,
eliminate the possibility of unexpected outputs at the
port pins, the instruction following the one that invokes
Idle should not be one that writes to a port pin or to
external Data RAM.

An instruction that sets PCON.l causes that to be the
last instruction executed' before going into the Power
Down mode: In the Power Down mode, the on-chip
oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Special
Function Registers are. held. The port pins output the
values held by their respective SFRs. ALE and PSEN
output lows.

270252-22

SMOD

The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only
two machine cycles (24 oscillatoi- periods) to complete
the reset.

The only exit from Power Down for the 80C5l is a
hardware reset. Reset redefines all. the SFRs, but does
not change the on-chip RAM.
In the Power Down mode of operation, VCC can be
reduced to as low as 2V. Care must be taken, however,
to ensure that VCC is not reduced before the Power
Down mode is invoked, and that VCC is restored to its
normal operating level, before the Power Down mode is
terminated. The reset that terminates Power Down also
frees the' oscillator. The reset should not be activated
before VCC is restored to its normal ,operating level,
and must be held active long enough to allow the oscillator to restart and stahilize (normally less than 10
msec).
'
,

If 1s are written to PD and IDL at the same time, PD takes
Precedence. The reset value of PCON is (OXXXOOOO).
In the HM0S devices the PCON register only contains
SMOD. The other four bits are implemented only in the
CHMOS devices. User software should never write 1s to
unimplemented bits, since they may be used in future MCS51 products.

EPROM VERSIONS
The EPROM versions of these devices are listed in Table 4. The 8751H programs at VPP = 21V using one
50 msec PROG pulse per byte programmed. This results in at6tal programming time (4K bytes) of approximately 4 minutes.

Figure 28. PCON: Power Control Register
6-25

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

Table 4. EPROM Versions of the 8051 and 8052
Device
Name

EPROM
Version

EPROM
Bytes

Ckt
Type

VPP

Time Required to
Program Entire Array

B051

(B751)

4K

HMOS

.21.0V

4 minutes

B051AH

B751H

4K

HMOS

21.0V

4 minutes

BOC51BH

B7C51

4K

CHMOS

12.75V:

13 seconds

B052AH

B752BH

BK

HMOS

12.75V

26 seconds

The 87S2BH and 87CS1 use the faster "Quick-Pulse"
programming™ algorithm. These devices program at
VPP = 12.7SV using a series of twenty-five 100 p.s
PROG pulses per byte programmed. This results in a
total programming time of approximately 26 seconds
for the 87S2BH (8K bytes) and 13 seconds for the
87CS1 (4K bytes).

87C51 AND 8752BH

The 87CS1 and 87S2BH contain two Program Memory
locking schemes: Encrypted Verify and Lock Bits.
Encrypted Verify: These devices implement a 32-byte
EPROM array that can be programmed by the customer, and which can then be used to encrypt the program
code bytes during EPROM verification. The EPROM
verification procedure is performed as usual, except
that each code byte comes out X-NORed ~th one of
the 32 key bytes. The key bytes are gone through in
sequence. Therefore, to read the ROM code, one has to
know the 32 key bytes in their proper sequence.

Detailed procedures for programming and verifying
each device are given in the data sheets.
EXPOSURE TO LIGHT

It is good practice to cover the EPROM window with
an opaque label when the device is in operation. This is
not so much to protect the EPROM array·from inadvertent erasure, but to protect the RAM and other onchip logic. Allowing light to impinge on the silicon die
while the device is operating can cause logical malfunction.

Unprogrammed bytes have the value FFH. Therefore,
if the Encryption Array is lc;ft unprogrammed all the
key bytes have the value FFH. Since any code byte
X-NORed with FFH leaves the code byte. unchanged,
leaving the Encryption Array unprogrammed in effect
bypasses the encryption feature.
LOck Bits: Also on the chip are two Lock Bits which
can be left unprogrammed (U) or programmed (P) to
obtain the following features:

Program Memory Locks
In some micro controller applications it is desirable that
the Program Memory be secure from software piracy.
Intel has responded to this. need by implementing a
Program Memory locking scheme in some of the MCSSl devices. While it is impossible· for anyone to guarantee absolute security against all levels of technological
sophistication, the Program Memory locks in the MCSSI devices will present a formidable barrier against Hiegal readout of protected software.
8751H

The 87S1H contains· a lock bit which, once programmed, denies electrical access by any external
means to.the on-chip Program Memory. The effect .of
this lock bit is that while it is programmed the internal
Program Memory can not be read out, the device can
not be further programmed, and it can not execute external Program Memory. Erasing the EPROM array
deactivates the lock bit and restores the device's full
functionality. It can then be r~programmed.

Bit 2

Bit 1

Additional Features

U

U

None

U

P

• Externally fetched code can not
access internal Program Memory.
• Further programming disabled.

P

U

(Reserved for Future definition.)

P

P

• Externally fetched code can not
access internal Program Memory.
• Further programming disabled. .
• Program verification is disabled.

When Lock Bit 1 is programmed, the logic level at the
EA pin is sampled and latched during reset. If the d~
vice is powered up without a reset, the latch initializes
to a random value, and holds that value until reset is
activated. It is necessary that the latched value of EA
be in agreement with the current logic level at that pin
in order for the device to function properly.

The procedure·for programming the lock bit is detailed
in the 87S1H data sheet.
6-26

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

ONCE Mode in the 87C51

Normal operation is restored after a normal reset is
applied.

The ONCE ("on-circuit emulation") mode facilitates
testing and debugging of systems using the 87C51 without the 87C51 having to be removed from the circuit.
The ONCE mode is invoked by:

THE ON-CHIP OSCILLATORS
HMOS Versions

1. Pull ALE low while the device is in reset and PSEN
is high;

The on-chip oscillator circuitry for the HMOS
(HMOS-I and HMOS-II) members of the MCS-51 family is a single stage linear inverter (Figure 29), intended
for use as a crystal-controlled, positive reactance oscillator (Figure 30). In this application the crystal is operated in its fundamental response mode as an inductive
reactance in parallel resonance with capacitance external to the crystal.

2. Hold ALE low as RST is deactivated.
While the device is in ONCE mode, the Port 0 pins go
into a float state, and the other port pins and ALE and
PSEN are weakly pulled high. The oscillator circuit
remains active. While the 87C51 is in this mode, an
emulator or test CPU can be used to drive the circuit.

Vee

TO INTERNAL
TIMINGCKTS

XTAL2
XTAL1

if

SUBST.

270252-23

Figure 29. On-Chip Oscillator Circuitry in the HMOS Versions of the MCS®-51 Family

Q2
TO INTERNAL
TIMING CKTS

Vss

~-t---QUARTZ

CRYSTAL
OR CERAMIC RESONATOR

270252-24

Figure 30. Using the HMOS On-Chip Oscillator

6-27

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

The crystal specifications and capacitance values (Cl
and C2 in Figure 30) are not critical. 30 pF can be used
in these positions at any frequency with good quality
crystals. A ceramic resonator can be used in place of
the crystal iii cost-sensitive applications. When a ceramic resonator is used, Cl and C2 are normally selected to be of somewhat higher values, typicaIly, 47 pF.
The manufacturer of the ceramic resonator should be
consulted for recommendations on the values of these
capacitors.

To drive the HMOS parts with an external .clock
source, apply the external clock signal to XTAL2, and
ground XTALl, as shown in Figure 31. A pullup resistor may be used (to increase noise margin), but is optional if VOH of the driving gate exceeds the VlH MIN
specification of XTAL2.

CHMOS VERSIONS
The on-chip oscillator circuitry for the 80C5IBH,
shown in Figure 32, consists of a single stage linear
inverter intended for use as a crystal-controlled, positive reactance oscillator in the same manner as the
HMOS parts. However, there are some important differences.

A more in-depth discussion of crystal specifications, ceramic resonators, and the selection of values for Cl and
C2 can be found in Application Note AP-155, "Oscillators for Microcontrollers," which is included in this
manual.

One difference is that the 80C5IBH is able to tum off
its oscillator under software control (by writing a 1 to
the PO bit in PCON). Another difference is that in the
80C51BH the internal clocking circuitry is driven by
the signal at XTALl, whereas in the HMOS versions it
is by the signal at XTAL2.

Vcc
r
8051
EXTERNAL
OSCILLATOR
SIGNAL

t

::>0-...- - 1 XTAL2

The feedback resistor Rr in Figure 32 consists of paralleled n- and p- channel FETs controlled by the PO bit,
such that Rr is opened when PO = 1. The diodes 01
and 02, which act as clamps to VCC and VSS, are
parasitic to the Rr FETs.

r-- XTAL1

TTL
GATE

~ VSS

WITH
TOTEM-POLE
OUTPUT

270252-25

Figure 31. Driving the HMOS MCS®-S1
Parts with an External Clock Source

Vcc

TO INTERNAL
TIMING CKTS

1

01

4000
XTAL1

XTAL2
D2

PD -----II+---.

270252-26

Figure 32. On-Chip Oscillator Circuitry in the CHMOS Versions of the MCS®-S1 Family
6-28

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

VCC
TO INTERNAL
TIMING CKTS

Rt

VSS
-------80CS1

XTAL1-----

XTAL2------

~--r--QUARTZ

CRYSTAL
OR CERAMIC
RESONATOR

270252-27

Figure 33_ Using the CHMOS On-Chip Oscillator

Rise and fall times are dependent on the external loading that each pin must drive. They are often taken to be
something in the neighborhood of 10 nsec, measured
between 0.8V and 2.0V.

The oscillator can be used with the same external components as the HMOS versions, as shown in Figure 33.
Typically, CI = C2 = 30 pF when the feedback element is a quartz crystal, and CI = C2 = 47 pF when a
ceramic resonator is used.

Propagation delays are different for different pins. For
a given pin they vary with pin loading, temperature,
VCC, and manufacturing lot. If the XTAL2 waveform
is taken as the timing reference, prop delays may vary
from 25 to 125 nsec.

To drive the CHMOS parts with an external clock
source, apply the external clock signal to XTALl, and
leave XTAL2 float, as shown in Figure 34.
The reason for this change from the way the HMOS
part is driven can be seen by comparing Figures 29 and
32. In the HMOS devices the internal timing circuits
are driven by the signal at XTAL2. In the CHMOS
devices the internal timing circuits are driven by the
signal at XTALI.

The AC Timings section of the data sheets do not reference any timing to the XTAL2 waveform. Rather, they
relate the critical edges of control and input signals to
each other. The timings published in the data sheets
include the effects of propagation delays under the
specified test conditions.

80CS1
NC
EXTERNAL
OSCILLATOR
SIGNAL

MCS®-S1 PIN DESCRIPTIONS

XTAL2

VCC: Supply voltage.

t

:>O------i XTAL1

VSS: Circuit ground potential.
VSS

CMOS GATE

Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an open drain output port it can sink 8 LS
TTL loads. Port 0 pins that have Is written to them
float, and in that state will function as high-impedance
imputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external memory. In
this application it uses strong internal pullups when
emitting Is. Port 0 also emits code bytes during program verification. In that application, external pullups
are required.

270252-28

Figure 34. Driving the CHMOS MCS®-51
Parts with an External Clock Source

INTERNAL TIMING
Figures 35 through 38 show when the various strobe
and port signals are clocked internally. The figures do
not show rise and fall times of the signals, nor do they
show propagation delays between the XTAL2 signal
and events at other pins.

Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can sink/
source 4 LS TTL loads. Port 1 pins that have Is written
6-29

HARDWARE DESCRIPTION OF THE.8051, 8052 AND 80C51

to them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1 pins
that are externally being pulled low will source current
(ilL, on the data sheet) because ofthe internal pullups.
In the 8052, pins P1.0 and Pl.l also serve the alternate
functions of T2 and T2EX. T2 is the Timer 2 external
input. T2EX is the input through which a Timer 2
"capture" is triggered.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can sink/
~ource 4 LS TTL loads. Port 2 emits the high-order
address byte during accesses to external meniory that
use 16-bit addresses. In this application it uses the
strong internal pullups when emitting Is. Port 2 also
receives the high-order address and control bits during
8751H programming and verification, and during program verification in the 8051AH.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. It also serves the functions of various
special features of the MCS-51 Family, as listed below:

Port Pin

Alternate Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6

RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory
write strobe)
RD (external data memory
read strobe)

P3.7

The Port 3 output buffers can source/sink 4 LS TTL
loads.
RST: Reset input. A high on this pin for two machine
cycles while' the oscillator is' running resets the device.
ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses to
external memory. ALE is emitted at a constant rate of
'I. of the oscillator frequency, for external timing or
clocking purposes, even when there are no accesses to
external memory. (However, one ALE pulse is skipped
during each access to external Data Me~ This pin
is also the program pulse input (pROG during
EPROM programming.
PSEN: Program Store Enable is the read strobe to external Program Memory. When the device is executing
out of external Program Memory, PSEN is activated
twice each machine cycle (except that two PSEN activations are~ed during accesses to external Data
Memory). PSEN is not activated when the device is
executing out of internal Program Memory.
EA/VPP: When EA is held high the CPU executes out
of internal Program Memory (unless the Program
Counter exceeds OFFFH in the 8051AH, or IFFFH in
the 8052). Holding EA low forces the CPU to execute
out of externlll memory regardless of the Program
Counter value. In the 8031AH and 8032, EA must be
extremely wired low. In the EPROM devices, this pin
also receives the programming supply voltage (VPP)
during EPROM programming. .
XTALl: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier..

I

STATE

11 STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE 1ISTATE 21

~I~

~I~

~I~

~I~ ~I~

~I~

~I~ ~I~

~~nnnnnnnnnnnnnnnnn

~UUUUUUUUUUUUUUUU~

ALE:

P2:

PCHOUT

PCHOUT

Figure 35. External Program Memory Fetches
6-30

I

PCHOUT

270252-29

intJ

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

I

I

STATE 41 STATE 51 STATE 81 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51

~1P2

~1P2

~1P2

~1P2

~In ~1P2

~1P2

~1P2

XTAL2:

ALE:

RD:

PO:

P2:

PCH OR
P2SFR

PCH OR
P2SFR

DPH OR P2 SFR OUT

270252-30

Figure 36. External Data Memory Read Cycle

I

I

STATE 41 STATE 5 STATE

~1P2

61 STATE 1 ISTATE 2.1 STATE 3.1 STATE 41 STATE 51

~1P2 ~1P2

~1P2

~1P2

~1P2

~1P2 ~1P2

XTAL2:

ALE:

jr-PCLOUTIF

ViR:

IS EXTERNAL

po:

P2

- - - - - I DPL OR RI
OUT

PCH OR
P2SFR

DATA OUT

~f

DPH OR P2 SFR OUT

~

PCH OR
P2SFR
270252-31

Figure 37. External Data Memory Write Cycle.

6-31

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

I

I

STATE 41 STATE 51 STATE 81 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51

~I~

~I~ ~I~ ~I~ ~I~

~I~ ~I~

~I~

XTAL2:

-

PO'P1~.

-YZ,P1

INPUTS S A M P L E D : .

.

~,P3, R S T = r l -

P2, P3, RST

MOY PORT, SRC:

SERIAL PORT
SHIFT CLOCK
(MODE 0)'

NEW DATA

OLD DATA

---+I

r-- RXD PIN SAMPLED

RXD SAMPLED

--.j

~
270252-32

Figure 38. Port Operation

6-32

Hardware Description of the
83C51FA

7

HARDWARE DESCRIPTION
OF THE 83C51FA (83C252)
INTRODUCTION

Port
Name
Pin

The 83C51FA is an 8-bit control-oriented microcontroller based on the 8051 architecture. The 83C51FA is
an enhanced version of the 80C51BH and incorporates
many new features. These features include:
• Programmable Counter Array with
- Compare/Capture
- High Speed Output
- Pulse Width Modulator
- Watchdog Timer
• Programmable Serial Channel
- Automatic Address Recognition
- Framing Error Detection
• Enhanced Power Down Mode
• 16-Bit Up/Down Timer/Counter
• 8K Factory Mask ROM
• 256 Bytes of On-Chip Data RAM
• 7 Interrupt Sources

P1.2 ECI

Function

External Count Input to the PCA

P1.S CEXO External 110 for Compare/Capture
Module 0
P1.4 CEX1 External I/O for Comparel.Capture
Module 1
P1.5 CEX2 External I/O for Compare/Capture
Module 2
P1,6 CEXS External I/O for Compare/Capture
ModuleS
P1.7 CEX4 External I/O for Compare/Capture
Module 4

The time-base for the PCA is a programmable 16-bit
timer/counter. This timer is the only one that can serve
the PCA. This timer is started or stopped by setting or
clearing bit CR in the Special Function Register
CCON, and can be programmed to count any of the
following signals (where Fosc is the 83C51FA oscillator frequency):

The 83C51FA uses the standard 8051 instruction set
and is pin for pin compatible with the existing
MCS®-5l products, However, the numbering system
for the 83C51FA is slightly different. The 83C51FA is
the factory masked ROM device; the 80C51FA is the
ROMless device; and the 87C51FA is the EPROM device.

• Fosc/12
The Counter increments once per machine cycle.
• Fosc/4
With a 16 MHz crystal, the counter increments once
every 250 ns.

It is assumed that the reader is familiar with the 8051

architecture. For more detailed information on the
8051, consult the "Hardware Description of the 8051
and 8052" chapter.

• Timer 0 overflow
The counteds incremented whenever Timer 0 overflows. This mode allows a programmable input frequency to the PCA.
• External input on ECI pin
The counter is incremented when a I-to-O transition
is detected on the ECI pin. The counter is limited to
input frequencies of Fosc/8 in this mode.

OVERVIEW OF THE PCA
The Programmable Timer/Counter Array (PCA) consists of a 16-bit counter and five 16-bit compare/capture modules. Each compare/capture module has its
own mode register, CCAPMn, which is used to configure the module. The compare/capture modules and the
PCA counter share Port 1 pins for hardware interfacing
as shown below:

The 16-bit PCA timer/counter can also be programmed to either run or pause when the CPU is in
Idle mode.

7-1

intJ

HARDWARE DESCRIPTION OF THE 83C51FA

High speed output mode, an interrupt can be generated
when the module executes its function.

Each of the five 16-bit compare/capture modules can
be programmed to do one of the following:
• 16-bit capture; positive edge activated.
• 16-bit capture, negative edge activated.
• 16-bit capture, both positive and negative edge activated.
• 16-bit software timer.
• High-speed output.
• 8-bit Pulse Width Modulator (PWM).

DESCRIPTION OF THE PCA
HARDWARE
The time base for the PCA is a 16-bit timer/counter
consisting of registers CH and CL (high and low bytes
of the count value), controlled by Special Function
Register CCON (Figure 1) and a mode register CMOD
(Figure 2).

In addition, Compare/Capture module 4 can be used as
a Watchdog Timer.

CCON contains bits CF (Counter Flag) which gets set
by hardware when the counter rolls over and CR
(Counter Run) which is used to tum the counter on
and off. It also contains interrupt flags from each of the
five PCA modules.

When any o.f the compare/capture modules. are programmed to the capture mode or the 16-bit .Timer/

CF

CR

CCF4

CCF3

CCF2

CCF1

CCFO·

Reset Value = OOXOOOOOB

Address = OD8H

Symbol

Position

CF

CCON.7

Function

CR

CCON.S

Counter Run control bit. Set by software to turn the PCA
counter on. Clear by software to turn the PCA counter off.

PCA Counter Overflow flag. Set by hardware when the
counter rolls over. CF flags an interrupt if bit ECF in CMOD is
. set. CF may be set by either hardware or software. It can only
be cleared by software.

-

CCON.5

Not implemented, reserved for future use. •

CCF4

CCON.4

PCA Module 4 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.

CCF3

CCON.3

PCA Module 3 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.

CCF2

CCON.2

PCA Module 2 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.

CCF1

CCON.1

PCA Module 1 interrupt flag. Set by hardware when a match or
capture occurs. Must be cieared by sonware.

CCFO

CCON.O

PCA Module 0 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.

Figure 1. CCON: Counter Control Register
NOTE:
'User software should not write'1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
reserved bit is indeterminate.

7-2

inter

HARDWARE DESCRIPTION OF THE 83C51FA

CMOD contains the following bits:
CIDL- selects whether the PCA counter continues to
run in Idle Mode
WDTE- enables the Watchdog Timer function
CIDL

CPS! and CPSO-select the counter input
ECF- enables CF to generate an interrupt.

WDTE
Address

=

CPS1

OD9H

CPSO

ECF

Reset Value = OOXXXOOOB

Symbol

Position

Function

CIDL

CMOD.7

Counter Idle control: CIDL = 0 programs PCA Counter to continue
functioning during Idle mode. CIDL = 1 programs it to be gated off during
Idle.

WDTE

CMOD.6

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function.
WDTE = 1 enables it.

-

CMOD.5

Not implem~nted, reserved for future use. •

-

CMODA

Not implemented, reserved for future use.'

-

CMOD.3

Not implemented, reserved for future use.'

CPS1

CMOD.2

Count Pulse Select bit 1.

CPSO

CMOD.1

Count Pulse Select bit

ECF

CMOD.O

o.

CPS1

CPSO

0
0
1
1

0
1
0
1

PCA Count Pulse Selected
Internal clock, Fosc/12
Internal clock, Fosc/4
Timer 0 overflow
External clock at ECI pin (P1.2)
(maximum rate = Fosc/a)

Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to
generate an interrupt. ECF = 0 disables that function of CF.
Figure 2. CMOD: Counter Mode Register

NOTE:

'User software should not write 1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
reserved bit is indeterminate.

Each of the five PCA modules has a Compare/Capture
Mode register, CCAPMn, n = 0 through 4 (Figure 3).
The following bits in each CCAPMn register define
that module's function.
ECOMn- enables that module's comparator function
CAPPn- enables the capture function on positive
transitions at theCEXn pin
CAPNn- enables the capture function on negative
transitions at the CEXn pin

MATn-

enables a comparator match to set the corresponding CCFn flag
TOGn- enables a comparator match to toggle the
CEXnpin
PWMn- enables the PWM output at the CEXn pin
ECCFn- enables any Compare/Capture event to flag
an interrupt

7-3

intJ

HARDWARE DESCRIPTION OF THE 83C51FA

ECOMn

CAPPn

CAPNn

TOGn

MATn

Addresses = OOAH (n = 0)
OOBH (n= 1)
OOCH(n=2)
OOOH (n=3)
OOEH (n=4)

PWMn

ECCFn

Reset Value = XOOOOOOOB

Symbol

Position

ECOMn

CCAPMn.7
CCAPMn.6

Function
Not implemented, reserved for future use.·
ECOMn = 1 enables the comparator function. This bit is
automatically cleared by any write to the CCAPnL register,
and automatically set by any write to the CCAPnH register.
This prevents unintended matches from occurring during
writes to the 16:bit Compare/Capture register.

CAPPn

CCAPMn.5

Positive edge capture enable. When CAPPn = 1, a positive
transition at the CEXn pin triggers a 16-bit capture from the
PCA counter to this module'S Compare/Capture register.

CAPNn

CCAPMn.4

MATn

CCAPMn.3

TOGn

CCAPMn.2

PWMn

CCAPMn.1

Negative edge capture enable. When CAPNn = 1, a negative
transition at the CEXn pin triggers a 16-bit capture from the
PCA counter to this module's Compare/Capture register.
When MATn = 1, a match of the PCA Counter with this
module'S Compare/Capture register causes the CCFn bit in
.. CCON to be set, flagging an interrupt.
When TOGn = 1, a match of the PCA Counter with this
module's Compare/Capture register causes the CEXn pin to
toggle.
When PWMn = 1, CEXn is driven high when the low byte of
the PCA Counter (CL) matches the low byte of this module's
Compare/Capture register (CCAPnL). When CL rolls over to
OOH, the CEXn pin is driven low and CCAPnL is updated with
the valLie in CCAPnH. This enables the CEXn pin to be used
as a pulse width modulated output. Software varies the pulse
. width by writing to CCAPnH,

ECCFn

CCAPMn.O

-

Enables Compare/Capture Flag CCFn in the CCON register to
generate an interrupt.

Figure 3. CCAPMn: Compare/Capture Mode Register for PCA Module n
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future MCS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
i6served bit is indateimlnate.

There are 6 modes of operation for each of the 5. PCA
modules: Shown below are the combinations of bits in
the CCAPMn register that are valid and have a

defined function. Invalid combinations will produce undefined results.

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

0

0
1

0
0

0
0

0
0

0

X

0
0

X

X

0

1

0

0

0

X

X

1

1

0

0

0

X

1
1
1

0
0
0

0
0
0

1
1

0
1

0
0

.x

0

0

1

0

x=

Don't Care

7-4

X

Module Function
No operation
16-bit capture by a positive-edge
trigger on CEXn
16-bit capture by a negativecedge
trigger on CEXn
16-bit capture by a transition
on CEXn
16-bit software timer
High Speed Output
a-bit PWM

inter

HARDWARE DESCRIPTION OF THE 83C51FA

16-Bit TimerICounter

16-Bit Capture Mode

The 5 Compare/Capture modules share a 16-bit timer/
counter as their "time base". The timer/counter, shown
in Figure 4, can be programmed to increment in 4 different ways. The modes are shown below with the setup
values in the CMOD register:

Setting CAPPn and/or CAPNn puts Compare/Capture module n into Input Capture mode, as shown in
Figure 5. The external input pins CEXO through CEX4
are sampled for a transition. When a valid transition is
detected for the current mode of operation (rising edge,
falling edge, or either edge), CL is transferred into the
CCAPnL register, and CH is transferred into
CCAPnH. The resulting value in the Capture Registers, CCAPnL and CCAPnH, reflect the values in CL
and CH at the time a transition was detected on the
CEXn pin. The event flags an interrupt if bit ECCFn is
set.

CPS1 CPSO

Method of Incrementing

0

0

Internally clocked at Oscillator
Frequency 112

0

1

Internally clocked at Oscillator
Frequency 14

1

0

Incremented when Timer 0 overflows

1

1

Externally clocked on Pin P1.2/ECI.
(Limited to Oscillator Frequency 18)

TO PCA MODULES 0-4

COUNT

INTERRUPT

ENABLE

Fosc/12
Fosc/4
TIMER 0
OVERFLOW

'-t===:..:::::t-----[]ECI

270421-1

Figure 4. PCA Timer/Counter

7-5

HARDWARE DESCRIPTION OF THE 83C51FA

PCA TIMER / COUNTER VALUE

CEXn

CCAPMn REGISTER
270421-2

n = 0, 1, 2, 3 or 4
x = Don'l Care

Figure 5. 16-Blt Capture Mode

with the count value of the counter module. When they
are equal, a match signal is generated which can set the
status bit CCFn in· the PCA COntrol register CCON
and/or toggle the corresponding CEXn pin.

16 Bit Timer
Setting bit ECOMn in the Compare/Capture. Mode
Register (CCAPMn) enables the Comparator function
as shown in Figure 6. The Comparator compares a
16-bit value stored in the compare/capture register

WOTE
(MODULE 4 ONLY)
_

PCA TIMER

I

. L____-

r-----------,

COUNTER VALUE
16

II

CAUSE
RESET

r----------~---------_1---------~

WRITE TO
. CCAPnL
RESET

------L..;

WRITE TO
CCAPnH

270421-3

n = 0, 1, 2, 3 or 4
x = Don'l Care

Figure 6. 16-Bit Comparator Mode

7-6

inter

HARDWARE DESCRIPTION OF THE 83C51FA

reverses the logic level of its" I/O pin, and/or can generate an interrupt as shown in Figure 6. When the PCA
module is configured in this manner as a High Speed
Output, the user, by setting or clearing the pin in software, can select whether the module's output pin will
change from a logical 0 to a logical 1 or vice versa.

Bit ECOMn is set by software and is initially cleared
during reset. It also gets cleared when a write to
CCAPnL register happens and is set if CCAPnH is
written to. This feature prevents ·action until the complete 16-bit value is loaded into the CCAPnH/L register if the low value is written to the 16-bit register first.
When the MATn (Match) bit is set in the Compare/
Capture Mode Register, the corresponding module in
the PCA is configured as a 16-bit timer. When the value in the 16-bit Compare/Capture register is equal to
the 16-bit value on the Count Bus, the hardware sets
the CCFn flag. This bit flags an interrupt if ECCFn is
also set.

Pulse Width Modulator Mode
Any or all of the 5 modules of the PCA can be programmed to be a Pulse Width Modulator as shown in
Figure 7. In this mode, the PWM output can be used to
convert digital data to an analog signal by simple external circuitry. The frequency of the PWM depends on
which of the four clock sources is selected for the PCA
Timer. With a 16 MHz crystal the maximum frequency
of the output waveform/of the PWM is 15.6 KHz. The
duty cycle of the waveform is controlled by the contents of an 8-bit register (CCAPnH) that can be programmed to be any integer" from 0 to 255.

High Speed Output
When programmed as a timer, the PCA module, during every cycle, compares the contents of the 16-bit
timer with the preset value of its Compare registers.
When a match" occurs, if bit TOGn is set, the module"

270421-4

n = 0, 1, 2, 3 or 4

x

=

Don't Care
Figure 7. 8-Bit PWM Mode

7-7

intJ

HARDWARE DESCRIPTION OF THE 83C51FA

not activated unless the received byte is an address byte
(9th data bit = I), and the address corresponds to either a Given Address or a Broadcast Address.

Watch Dog Timer Mode
A Watchdog Timer js a circuit that automatically invokes a reset unless the system being watched sends
regular hold-off signals to the Watchdog. These circuits
are used in applications that are subject to electrical
noise, power glitches, electrostatic discharges, etc., or
where high reliability is required with hands-off operation.

The feature works the same way in the 8-bit mode
(mode I) as in the 9-bit modes, except that the stop bit
takes the place of the 9th data bit. That is, if SM2 is set,
RI is not activated unless the received byte agrees with
either the Given or Broadcast address and is terminated
by a valid stop bit.

In this mode, every time the count in the PCA counter
module matches the value 'stored in compare/capture
module 4, an internal reset is generated. The' bit that
selects this mode is WDTE in the CMOD register.
Compare/capture module 4 should be set up to be a
16-bit timer or a High Speed Output in the Watchdog
Timer mode.
'

The Given Address is specified by the contents of two
new SFRs: SADDR and SADEN. The 83C51FA's individual address is defined in SADDR. SADEN is a
mask byte that defines don't-cares in SADDR to form '
the Given Address. For example,
SADDR = 01010110
SADEN = 11111100

To hold off the reset, the user's software can:
• Continually reset the PCA 16-bit timer value to a
lower value than the reset value in module 4.
• Clear the WDTE bit when a match is about to occur, and then set the WDTE bit just after the match
condition (temporarily disabling the feature).
or
• Continually change the CCAP4H and CCAP4L value to one that is "far" from a match value.

spec,ify the Given Address to be OIOIOIXX.
The Broadcast. Address is formed from the logical OR
of SADDR and SADEN. Zeros in the logical OR are
don't-cares. For example, the values given above for
SADDR and SADEN defme the broadcast address to
be 11 111 11X.
Automatic Address Recognition allows a host processor to establish communication -with an addressed
slave, without all the other slave controllers having to
respond to the transmission. The addressed slave then
clears its SM2 bit to enable reception of data bytes (9th
data bit = 0) from the host.

Finally, the Watchdog Timer can be used to program a
reset by allowing a match to occur.

EXTENDED SERIAL PORT FEATURES

The Given and Broadcast addresses allow each microcontroller to have its own (Given) address and a common (Broadcast) address. A "host" on the serial channel can selectively address single 83C51FA's using the
'Given Address or all 83C51FA's using the Broadcast
Address.

The full duplex serial port of the 83C51FA is the same
as the serial port of the 8052 but with two added features: Automatic Address Recognition and Framing
Error Detection.

On reset, the SADDR and SADEN registers are initialized to OOH. This defines the Given and Broadcast addresses to be XXXXXXXX (all don't-cares) for backwards compatibility with the MCS®-51 family.

Automatic Address Recognition
Automatic Address Recognition is useful in multi-processor applications in which the CPUs communicate
through the serial channel. Using this feature, the
83C51FA's Serial Port refrains from interrupting the
CPU unless it receives its own address. Automatic Address Recognition is enabled by setting the SM2 bit in
SCON.
-

Framing Error Detection
Another new feature of the Serial Port is Framing Error Detection. This allows the receiving controller to
check the stop bit in modes I, 2, or 3. A missing stop
bit causes a Framing Error bit, FE, to be set. The FE
bit can then be checked in software immediately after
each reception to detect the lack of a valid stop bit. A
missing stop bit can be caused, for example, by noise on
the serial lines, or by two CPUs trying to transmit at
the same time.

Normally the Serial Port would be configured into either of the 9-bit modes (modes 2 and 3). In these
modes, if SM2 is set, the Receive Interrupt flag RI is

7-8

inter

HARDWARE DESCRIPTION OF THE 83C51FA

The FE bit, once set, must be cleared in software. A
valid stop bit does not cause the FE bit to be cleared.

iced, the next instruction executed after RETI will be
the one following the instruction that put the device in
Power Down.

The FE bit resides in SCON, and has the same bit address as the SMO bit. A new control bit in the PCON
register determines if accesses to the SMO/FE bit address are to SMO or to FE. The new control bit in
PCON is called SMODO, and resides at PCON.6 (Figure 8). IfSMODO = 0, then accesses to SCON.7 are to
SMO. IfSMODO = I, then accesses to SCON.7 are to
FE.

Power Off Flag
A Power Off Flag, POF, has been added to the PCON
register (Figure 8). This flag is set by hardware when
VCC comes up, and can be set or cleared by software.
This allows one to distinguish between a "cold start"
reset and a "warm start" reset.

REDUCED POWER MODES
Idle Mode
Idle Mode is the same in the 83C51FA as in the
80C5IBH. Note that the PCA can be programmed to·
either pause or continue operations during Idle.

Power Down Mode
The Power Down Mode on the 83C51FA differs from
the SOC5IBH in one respect: the 83C51FA can exit
Power Down with either a hardware Reset or an External Interrupt. (The 80C5IBH can only exit Power
Down with a hardware Reset.) An exit with an External Interrupt allows not only the on-chip RAM to be
saved but also the Special Function Registers.

SMOOO

x

To use the feature, one checks the POF bit in software
immediately after reset. POF = I would indicate a
cold start. The software then clears POF, and commences its tasks. POF = 0 immediately after reset
would indicate a warm start.
VCC must remain above 3 volts for POF to retain a

o.

TIMER 2 AS AN UP/DOWN COUNTER
Timer 2 is a general purpose 16-bit timer/counter
which is present in the 8052 and in the 83C51FA. Timer 2 has the same functionality in both of these devices
except that in the 8052 Timer 2 can only count up, and
in the 83C51FA Timer 2 can be programmed to count
up or down. The option to count up or down becomes
available when the Timer is configured to its 16-bit
auto-reload mode.

The External Interrupt, INTO or INTI, must be enabled and configured as level-sensitive to properly terminate Power Down. Also the interrupt should not be
executed before Vee is restored to its normal operating
level, and must be held down long enough for the oscillator to restart and stabilize. Once the interrupt is servSM001

A cold start reset is one that is coincident with VCC
being turned on to the device after it was turned off. A
warm start reset is one that. occurs after the device has
already been powered up and running. A warm start
reset could be generated, for example, by a Watchdog
Timer, or as an exit from Power Down Mode.

POF

GF1

Address = 087H

GFO

PO

IOL

. Reset Value = OOXXOOOOB

POF

Power Off Flag. Set by hardware on the rising edge of Vee. Set or cleared by software. This flag allows
detection.of a power failure caused reset. Vee must remain above 3V to retain this bit.
SMODO When set, Read/Writc:: accesses to SCON.7 are to the FE bit. When clear, Read/Write. accesses to
SCON.7 are to the SMO bit.
SMODI Same as the SMOD bit in the MSC-51 architecture. The additional bits are defined to be compatible with
the 8052 and 80C51BH.
Figure 8. PCON: Power Control Register

7-9

inter
x

HARDWARE DESCRIPTION OF THE 83C51FA

x

x

x

x

x

x

DCEN

Reset Value = XXXX XXXOB
Address = OC9H
When set, this bit allows Timer 2 to be configured as an up/down counter.
Figure 9. T2MOD: Timer 2 Mode Control Register

DCEN

~
~

.~

!C/f2=o

T2 PIN ------~

T2EX PIN

TIMER 2
INTERRUPT

------+1
EXEN2

270421-5

Figure 10. Timer 2 Auto-Reload Mode when DCEN = 0
The Special Function Register T2MOD (present in the
83C51FA but not in the 8052) contains a bit named
DCEN (Down Counter Enable). T2MOD is shown in
Figure 9. When this bit is clear (0), the Timer 2 AutoReload Mode in the 83C51FA is exactly the same as iii
the 8052. Figure,IO shows Timer 2 in Auto-Reload
Mode with DCEN = o.

When DCEN is set (I), the Timer 2 Auto-Reload Mode
takes the form shown in Figure 11. The T2EX pin now
controls the direction of count. A logic 1 at T2EX
makes Timer 2 count up. A logic 0 at T2EX makes
Timer 2 count down. Also, the EXF2 bit toggles every
time Timer 2 overflows or underflows. In this operating
mode, the EXF2 bit does not flag an interrupt.

270421-6

Figure 11. Timer 2 Auto-Reload Mode when DC EN
7-10

=:'

1

HARDWARE DESCRIPTION OF THE 83C51FA

UPPER 128 BYTES OF RAM

FUNCTIONS OF PORT 1 PINS

The 83C51FA implements a full 256 bytes of on-chip
data RAM. As in the 8052, the upper 128 bytes occupy
a parallel address space to the Special Function Registers. That means they have the same addresses, but they
are physically separate from SFR space.

P1.0/T2 may be used as an external count input to
Timer 2.
Pl.l/T2EX can be used to trigger a capture if Timer 2
is in the Capture Mode, or to trigger a reload if Timer 2
is in the Auto-Reload Mode and DCEN is set to O.
T2EX can also control the count direction if Timer 2 is
in the Auto-Reload Mode and DCEN set to 1. Finally,
T2EX can be used as an external interrupt if Timer 2 is
being used as a baud-rate generator.

When an instruction accesses an internal location above
address 7FH, the CPU knows whether the access is to
the upper 128 bytes of data RAM or to SFR space by
the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For
example,
MOV OAOH, # data

P1.2/ECI takes the external signal to the PCA counter.
The frequency of the external signal is limited to one
eighth of the oscillator frequency or less. The PCA
count is incremented every time the ECI pin makes a
1-0 transition.
.

accesses the SFR at location OAOH (which is P2). Instructions that use indirect addressing access the upper
128 bytes of data RAM. For example,
MOV @RO,#data

P1.3 through P1.7/CEXn functions depend on the configuration of their corresponding Compare/Capture
modules in the PCA. They can be configured to be a
rising edge, falling edge, or an "either edge" trigger
input to a Compare/Capture module. They can also be
high speed outputs which toggle every time the PCA
count matches the value in the corresponding Compare/Capture register. Finally, any of these pins can be
configured as an 8-bit Pulse Width Modulated (PWM)
output. In the PWM mode, the pin will be in the logical
"0" state for a programmable length of time, and will
be in the logical "1" state for· the remainder of the
PWM duty cycle. The PWM duty cycle is variable between 1/256 and 256/256.

~here RO contains OAOH, accesses the data byte at address OAOH, rather than P2 (whose address is OAOH).

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

PIN DESCRIPTION
The 83C51FA is Pin-for-Pin compatible with the
80C51BH. Port 1 on the 83C51FA has 8052 functionality and additionally serves the PCA as shown below.

Detailed descriptions of the functions of the PCA pins
can also be found in section 1.2, PCA feature description.

Port 1 pins and Alternate Functions.
Port
Name
Pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

Function

INTERRUPT STRUCTURE

T2
External Count Input to Timer 2
T2EX Timer 2 Capture/Reload Trigger
ECI
External Count Input to the PCA
CEXO External 1/0 for Compare/Capture
Module 0
CEX1 External 1/0 for Compare/Capture
Module 1
CEX2 External 1/0 for Compare/Capture
Module 2
CEX3 External 110 for Compare/Capture
Module 3
CEX4 External 110 for Compare/Capture
Module 4

The 83C51FA provides 7 interrupt sources. Five of
them (INTO/ and INTI/, Timer 0 and Timer I, and
the Serial Port) are identical with those provided in the
80C51BH. The 83C51FA also provides a Timer 2 interrupt which is identical with the Timer 2 interrupt in the
8052, and a PCA interrupt which is only found in the
83C51FA. These interrupt sources are shown in Figure
12.

7-11

HARDWARE DESCRIPTION OF THE 83C51FA

INTO---cY

ITO

TFO-------------------------.~

INT1,...---<:r-

TF1------------------------.~

INTERRUPT
SOURCES
CF-3ECF

5

~\--------..,D)--------------+~

...,D.·. ____________•

TF2 _ _ _ _ _ _ _ _
EXF2-

~

,-

270421-7

(Sea oxceptions ,,·,hen Timer 2 is used as baud rate gl3l"!Aratnr or an up/down counter.)

Figure 12. 83C51FA Interrupt Sources

The Timer 2 interrupt is generated by the logical OR of
TF2 and EXF2. Neither of these flags is cleared by
hardware when the service routine is vectored to. In
fact, the service routine may have to determine whether
it was TF2 or EXF2 that generated the interrupt, and
the bit will have to be cleared in software.

All of the bits that generate interrupts can be set or
cleared in software, with the same result as though it
had been set or Cleared by hardware. That is, interrupts
can be generated or pending interrupts can be cancelled
in software. .
.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special
Function Register IE (Figure 13). Note that IE also
contains a global disable bit, EA. If EA is set (I), the
interrupts· are individually enabled or disabled by their
corresponding bits in IE. If EA is clear (0), all interrupts are disabled.

The PCA interrupt is generated by the logical OR of
CF, CCFO, CCF1, CCF2, CCF3, and CCF4. None of
these flags is Cleared by hardware when the service routine is vectored to. In fact, normally the service routine
will have to determine which bit flagged the interrupt
and clear that bit in software.

7-12

1
\

HARDWARE DESCRIPTION OF THE 83C51FA
I

EA

EC

ET2

ES

ET1

Address = OASH

EX1

EXO

ETO

Reset Value = OOOOOOOOB

Symbol

Position

Function

EA

1E.7

Disables all interrupts. If EA = 0, all interrupts are disabled. If
EA = 1, each interrupt can be individually enabled or disabled
by setting or clearing its enable bit.

EC

IE.6

Enables or disables the PCA interrupt. EC = 1 enables it.
EC = 0 disables it.

ET2

IE.5

Enables or disables the Timer 2 interrupt. ET2 = 1 enables it.
ET2 = 0 disables it.

ES

lEA

Enables or disables the Serial Port interrupt. ES = 1 enables
it. ES = 0 disables it.

ET1

1E.3

Enables or disables the Timer 1 interrupt. ET1 = 1 enables it.
ET1 = 0 disables it.

EX1

IE.2

Enables or disables External Interrupt 1. EX1 = 1 enables it.
EX1 = 0 disables it.

ETO

IE.1

Enables or disables the Timer 0 interrupt. ETO = 1 enables it.
ETO = 0 disables it.

EXO

IE.O

Enables or disables External Interrupt O. EXO = 1 enables it.
EXO = 0 disables it.
Figure 13. IE: Interrupt Enable Register

PRIORITY LEVEL STRUCTURE

priority interrupt can be interrupted by a high-priority
interrupt, but not by another low-priority interrupt. A
high-priority interrupt can't be interrupted by any other interrupt source.

Each interrupt source can be individually programmed
to one of two priority levels by setting or clearing a bit
in Special Function Register IP (Figure 14). A low-

PPC

PT2

PS

PT1

Address = OBSH

PX1

PXO

PTO

Reset Value = XOOOOOOOB

Symbol

Position

-

IP.7

Not implemented, reserved for future use. •

PPC

IP.6

Defines the PCA interrupt priority level. PPC = 1 programs it
to the high priority level.

PT2

IP.5

Defines the Timer 2 interrupt priority level. PT2 = 1 programs
it to the high priority level.

PS

IPA

Defines the Serial Port interrupt priority level. PS = 1
programs it to the high priority level.

PT1

IP.3

Defines the Timer 1 interrupt priority level. PT1 = 1 programs
it to the high priority level.

PX1

IP.2

Defines the External Interrupt 1 priority level. PX1
programs it to the high priority level.

PTO

IP.1

Defines the Timer 0 interrupt priority level. PTO
it to the high priority level.

PXO

IP.O

Defines the External Interrupt 0 priority level. PXO
programs it to the high priority level.

Function

=1

= 1 programs
=1

NOTE:
·User software should not write 1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
reserved bit is indeterminate.

Figure 14. IP: Interrupt Priority Register
7-13

intJ

HARDWARE DESCRIPTION OF THE 83C51FA

If two interrupts of different priority levels are flagged
simultaneously, the interrupt request of the higher priority level is serviced. If interrupts of the same priority
level are flagged simultaneously, an internal polling sequence determines which interrupt request is serviced.
Thus within each priority level there is a second priori- .
ty structure determined by the following polling sequence:

SOURCE
1. lEO
2. TFO
3. lEI
4. TFI
5.PCA
6.RI+TI
7. TF2+ EXF2

location of the interrupt service routine as shoWn below.
SOURCE
STARTING ADDRESS OF
SERVICE ROUTINE
0003H
lEO
TFO
OOOBH
0013H
IE1
001BH
TF1
0023H
RI+TI
TF2+EXF2
002BH
0033H
PCA

PRIORITY WITHIN LEVEL
(highest)

(lowest)

Note that the "priority within level" structure is only
used to resolve simultaneous requests of the same priority level.

Execution proc~eds from that location until the RETI
instruction is encountered, which terminates the interrupt service routine. Note that the starting addresses of
consecutive interrupt service routines are only 8 bytes
apart. That means if consecutive interrupts are being
used (lEO and TFO, for example, or. TFO and lEI), and
if the first interrupt routine is more than 7 bytes long,
then that routine will have to execute a jump out to
some other memory location where the service routine
can be completed without overlapping the starting ad·dress of the next interrupt routine.
.

LOCATION OF INTERRUPT SERVICE .
ROUTINES

Note that, although the polling position of the PCAgenerated interrilpt is higher than that of the Serial
Port, the starting address of the Serial Port interrupt
routine is unchanged from the 8051. This is for backwards software compatibility. Similarly, the Timer 2
interrupt 'starting addreSs is compatible with the 8052.
This allows conversion of 8052 (HMOS) designs to the
83C51FA (CHMOS) with no software modification.

The Interrupt Control System acknowledges an interrupt request by executing a hardware-generated
LCALL to the appropriate service routine. The hardware-generated LCALL pushes the contents of the Program Counter onto the stack (but it does not'save the
PSW) and reloads the PC with the starting

7-14

inter

HARDWARE DESCRIPTION OF THE 83C51FA

SPECIAL FUNCTION REGISTERS
A map of the Special Function Register (SFR) space is
shown in Table 1.

User software should not write Is to these unimplemented locations, since they may be used in future
MCS-51 products to invoke new features. In that case
the reset or inactive values of the new bits will always
be 0, and their active values will be I.

Note that not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect.

Table 1. Special Function Register Memory Map and Values After Reset

CH
CCAP3H
CCAP4H
CCAPOH
CCAP1H
CCAP2H
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

F8

FO *S
00000000

F7

CL
CCAPOL
CCAP1L
CCAP2L
CCAP3L
CCAP4L
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

E8

FF

EO 'ACC
00000000
08 CCON
CMOO
CCAPMO
OOXOOOOO OOXXXOOO XOOOOOOO

EF
E7

CCAPM1
XOOOOOOO

CCAPM2 CCAPM3
XOOOOOOO XOOOOOOO

CCAPM4
XOOOOOOO

OF
07

DO • PSW

00000000
C8 T2CON
T2MOO
RCAP2L
00000000 XXXXXXXO 00000000

RCAP2H
00000000

TL2
00000000

TH2
00000000

co

CF
C7

S8 • IP

SF

So

S7

A8

SAOEN
XOOOOOOO 00000000
* P3
11111111
SAOOR
• IE
00000000 00000000

AF

AO • P2
11111111
* SSUF
98 'SCON
00000000 XXXXXXXX

A7

90 • P1

97

11111111
88 " TCON
00000000
80 " PO
11111111

9F

*TMOO
• THO,
• TL1
• TH1
• TLO
00000000 00000000 00000000 00000000 00000000
• OPL
• OPH
• SP
00000111 00000000 00000000

• = Found In the 8051 core (See 8051 Hardware Description for explanations of these SFRs).
•• = See description of PCON SFR. Bit PCON.4 is not affected by reset.

X = Undefined.

7-15

8F

'PCON •• 87
OOXXOOOO

Hardware Description of the
83C152

8'

HARDWARE DESCRIPTION
OF THE 83C152
use of external program memory. The second difference
is that RESET is active low in the 83CI52 and active
high in the 80C51BH. This is very important to designers who may currently be using the 80C51BH and planning to use the 83C152, or are planning on using both
devices on the same board. The third difference is that
GFO and GFI, general purpose flags in PCON, have
been renamed GFIEN and XRCLK. GFIEN enables
idle flags to be generated in SDLC mode, and XRCLK
enables the receiver to be externally clocked. All of the
previously unused bits are now being used and interrupt vectors have been added to support the new enhancements. Programmers using old code generated for
the 80C51BH will have to examine their programs to
ensure that new bits are properly loaded, and that the
new interrupt vectors will not interfere with their program.

1.0 INTRODUCTION
The 83CI52 Universal Communications Controller is
an 8-bit microcontroller designed for the intelligent
management of peripheral systems or components. The
83CI52 is a derivative of the 80C51BH and retains the
same functionality. The 83CI52 is fabricated on the
same CHMOS III process as the 80C51BH. What
makes the 83CI52 different is that it has added functions and peripherals to the basic 80C5IBH architecture that are supported by new Special Function Registers (SFRs). These enhancements include: a high speed
multi-protocol serial communication interface, two
channels for DMA transfers, HOLD/HLDA bus control, a fifth I/O port, expanded data memory, and expanded program memory.
In addition to a standard UART, referred to here as
Local Serial Channel (LSC) , the 83Cl52 has an onboard multi-protocol communication controller called
the Global Serial Channel (GSC). The GSC interface
supports SDLC, CSMA/CD, user definable protocols,
and a subset of HDLC protocols. The GSC capabilities
include: address recognition, collision resolution, CRC
generation, flag generation, automatic retransmission,
and a hardware based acknowledge feature. This high
speed serial channel is capable of implementing the
Data Link Layer and the Physical Link Layer as shown
in the OSI open systems communication model. This
model can be found in the document "Reference Model
for Open Systems Interconnection Architecture",
ISO/TC97/SCI6 N309.

Throughout the rest of this manual the 80CI52 and the
83CI52 will be referred to generically as the "CI52".
The CI52 is based on the 80C51BH architecture and
utilizes the same 80C5IBH instruction set. Figure 1.1 is
a block diagram of the C152. Readers are urged to
compare this block diagram with the 80C51BH block
diagram. There have been no new instructions added.
All the new features and peripherals are supported by
an extension of the Special Function Registers (SFRs).
Very little of the information pertaining specifically to
the 80C5IBH core will be discussed in this chapter.
The detailed information on such functions as: the instruction set, port operation, timer/counters, etc., can
be found in the MCS®-51 Architecture chapter in the
Intel Embedded Controller Handbook. Knowledge of
the 80C5IBH is required to fully understand this manual and the operation of the C152. To gain a basic understanding on the operation of the 80C51BH, the
reader should familiarize himself with the entire MCS51 chapter of the Embedded Controller Handbook.

The DMA circuitry consists of two 8-bit DMA channels with 16-bit addressability. The control signals;
Read (RD), Write (WR), hold and hold acknowledge
(HOLD/HLDA) are used to access external memory.
The DMA channels are capable of addressing up to
64K bytes (16 bits). The destination or source address
!;an be automatically incremented. The lower 8 bits of
the address are multiplexed on the data bus Port 0 and
the upper eight bits of address will be on Port 2. Data is
transmitted over an 8-bit address/data bus. Up to 64K
bytes of data may be transmitted for each DMA activation.

Another source of information that the reader may find
helpful is Intel's LAN Components User's Manual, or. der number 230814. Inside are descriptions of various
protocols, application examples, and application notes
dealing with different serial communication environments.

The new I/O port (P4) functions the same as Ports 1-3,
found on the 80C51BH.

2.0 COMPARISON OF 80C152 AND
80C51BH FEATURES

Internal memory has been doubled in the 83C152. Data
memory has been expanded to 256 bytes, and internal
program memory has been expanded to 8K bytes.

2.1 Memory Space

There are also some specific differences between the
83CI52 and the 80C51BH. The first is that the numbering system between the 83CI52 and the 80C5IBH is
slightly different. The 83CI52 and the 80C5IBH are
factory masked ROM devices. The 80CI52 and the
80C3IBH are ROMless devices which require the

A good understanding of the memory space and how it
is used in the operation of MCS-51 products is essential. All the enhancements on the CI52 are implemented by accessing Special Function Registers (SFRs),
added data memory, or added program memory.

8-1

P4.0-P4.7

l

PO .0- PO.7

SARLI
SARHI
DARL1
DARHI

:t:

BCRL1

~

::u
c

:e~
"'1'1

::u

III

m

m

c·
c::

......

C

en
n
::u

:..

(Xl

ID

=ti

N n0"

-4

(5

7<:

C

Z

..

iii'

o."

eD

III

3

-4
:t:

~"

m
CI)
Co)

....n
U1
N

CRC
GENERATOR
ADRO-3
BAUD

Pl.O- Pl.7

TCDCNT

P3.0- P3.7

270427-7

HARDWARE DESCRIPTION OF THE 83C152

(IDA), Source Address Space bit (SAS). Increment
~ource Address bit (ISA), DMA Channel Mode bit
(DM), Transfer Mode bit (TM), DMA Done bit
(DONE), and the GO bit (GO). DCONO is used to
control DMA Channel O.

2.1.1 SPECIAL FUNCTION REGISTERS (SFRs)
The following list contains all the SFRs, their names
and function. All of the SFRs of the 80C51BH are reo
tained and for a detailed explanation of their operation,
please refer to the chapter, "Hardware Description of
the 8051 and 8052" that is found in the Embedded
Controller Handbook. An overview of the new SFRs is
found in Section 2.2.1.1, with a detailed explanation in
Section 3.7 and Section 4.5.

DCONI - (93H) Same as DCONO except this is for
DMA Channel 1.
GMOD - (84H) Contains the Protocol bit (PR). the
Preamble Length (PLI.O), CRC Type (CT). Address
Length (AL). Mode select (Ml.0), and External Transmit Clock (TXC). This register is used for GSC operation only.

2.1.1.1 New SFRs
The following descriptions are quick overviews of the
new SFRs, and not intended to give a complete understanding of their use. The reader should refer to the
detailed explanation in Section 3 for the GSC SFRs,
and Section 4'for the DMA SFRs.

IENI - (OC8H) Interrupt enable register for DMA and
GSC interrupts.
.
IFS - (OA4H) Determines the number of bit times separating transmitted frames.

ADR 0,1,2,3 - (95H, OA5H, OBSH, OCSH) Contains
the four bytes for address matching during GSC operation.

IPNI - (OF8H) Interrupt priority register for DMA
and GSC interrupts.

AMSKO - (OD5H) Selects "don't care" bits to be used
with ADRO.

MYSLOT - (OFSH) Contains the Jamming mode bit
(DCJ). the Deterministic Collision Resolution Algorithm bit (DCR). and the DCR slot address for the
GSC.

AMSKI - (OESH) Selects "don't care" bits to be used
with ADRI.

P4 - (OCOH) Contains the memory "image" of Port 4.

BAUD - (94H) Contains the programmable value for
the baud rate generator for the GSC. The baud rate will
equal (fosc)/«BAUD + I) X 8).

PRBS - (OE4H) Contains a pseudo-random number to
be used in CSMA/CD backoff algorithms. May be read
or written to by user software.

BCRLO - (OE2H) Contains the low byte of a countdown counter that determines when the DMA access
for Channel 0 is complete.

RFIFO - (F4H) RFIFO is used to access a 3-byte FIFO
that contains the receive data from the GSC.

BCRHO - (OE3H) Contains the high byte for countdown counter for Channel O.

BCRHI - (OF3H) Same as BCRHO except for DMA
Channell.

RSTAT - (OE8H) Contains the Hardware Based Ac·
knowledge Enable bit (HABEN), Global Receive Enable bit (GREN). Receive FIFO Not Empty bit
(RFNE). Receive Done bit (RDN). CRC Error bit
(CRCE). Alignment Error bit (AE), Receiver Collision!Abort detect· bit (RCABT), and the Overrun bit
(OVR). used with both DMA and GSC.

BKOFF - (OC4H) An 8-bit count-down timer used
with the CSMA/CD resolution algorithm.

SARLO - (OA2H) Contains the low byte of the source
address for DMA transfers.

DARLO - (OC2H) Contains the low byte of the destination address for DMA Channel O.

SARHO - (OA3H) Contains the high byte of the source
address for DMA transfers.

DARHO - (OC3H) Contains the high byte of the destination address for DMA Channel O.

SARLI - (OB2H) Saine as SARLO but for DMA Chan-.
nell.

DARLI - (OD2H) Same as DARLO except for DMA
Channell.

SARHI - (OB3H) Same as SARHI but for DMA Channel I.

DARHI - (OD3H) Same as DARHO except for DMA
Channell.

SLOTTM - (OB4H) Determines the length of the slot
time in CSMA/CD.

DCONO - (92H) Contains the Destination Address
Space bit (DAS). Increment Destination Address bit

TCDCNT - (OD4H) Contains the number of collisions
in the current frame if using CSMA/CD GSC.

BCRLl - (OF2H) Same as BCRLO except for DMA
Channell.

8-3

inter

HARDWARE DESCRIPTION OF THE 83C152

Old(O)/New(N)

0
N
N
N
N
N
N

0
N
N
N
N
N
N
N
N
N
N
N
N

0
0
N

0
N
N

0
N
N"

0
0
0
0
N

0
N

0
N
N
N
N
N
N

.0
0
N

0
N

0
N

0

ci
0
0
0
N

Name
'A
ADRO
ADR1
ADR2
ADR3
AMSKO
AMSK1
B
BAUD
BCRLO
BCAHO
BCRL1
BCRH1
BKOFF
DARLO
DARHO
DARL1
DARH1
DCONO
DCON1
DPH
DPL
GMOD
IE
IEN1
IFS
IP
IPN1
MYSLOT
PO
P1
P2
P3
P4
PCON
PRBS
PSW
RFIFO
RSTAT
SARLO
SARHO
SARL1
SARH1
SBUF
SCON
SLOTTM
SP
TCDCNT
TCON
TFIFO
THO
TH1
TLO
TL1
TMOD
TSTAT

. Function

Addr
OEoH.
095H
OA5H
OB5H
OC5H
OD5H
OE5H
OFOH
094H
OE2H
OE3H
OF2H
OF3H
OC4H
OC2H
OC3H
OD2H
OD3H
092H
093H
083H
082H
084H
OA8H
OC8H
OA4H
OB8H
OF8H
OF5H
b80H
090H
OAOH
bBOH
OCOH
087H
·OE4H
ODOH
OF4H
OE8H
OA2H
OA3H
OB2H
OB3H
099H
098H
OB4H
08tH
OD4H
088H
085H
08CH
08DH
08AH
08BH
089H
OD8H

ACCUMULATOR
GSC MATCH ADDRESS 0
GSC MATCH ADDRESS 1
GSC MATCH ADDRESS 2
GSC MATCH ADDRESS 3
GSC ADDRESS MASK 0
GSC ADDRESS MASK 1
B REGISTER
GSC BAUD RATE
DMA BYTE COUNT 0 (LOW)
DMA BYTE COUNT 0 (HIGH)
DMA BYTE COUNT 1 (LOW)
DMA BYTE COUNT 1 (HIGH)
GSC BACKOFF TIMER
DMA DESTINATION ADDR 0 (LOW)
DMA DESTINATION AD DR 0 (HIGH)
DMA DESTINATION ADDR 1 (LOW)
DMA DESTINATION ADDR 1 (HIGH)
. DMA CONTROL 0
DMA CONTROL 1
DATA POINTER (HIGH)
DATA POINTER (LOW)
GSCMODE
INTERRUPT ENABLE REGISTER 0
INTERRUPT ENABLE REGISTER 1
GSC INTER FRAME SPACING
INTERRUPT PRIORITY REGISTER 0
INTERRUPT PRIORITY REGISTER 1
GSC SLOT ADDRESS
PORTO
PORT 1
PORT 2
PORTa
PORT 4
POWER CONTROL
GSC PSEUDO-RANDOM SEQUENCE
PROGRAM STATUS WORD
GSC RECEIVE BUFFER
RECEIVE STATUS (DMA & GSC)
DMA SOURCE ADDR 0 (LOW)
DMA SOURCE ADDR 0 (HIGH)
DMA SOURCE AD DR i (LOW;
DMA SOURCE ADDR 1 (HIGH)
LOCAL SERIAL CHANNEL (LSC) BUFFER
LOCAL SERIAL CHANNEL (LSC) CONTROL
GSC SLOT TIME
STACK POINTER
GSC TRANSMIT COLLISION COUNTER
TIMER CONTROL
GSC TRANSMIT BUFFER
TIMER 0 (HIGH)
TIMER 1 (HIGH)
TIMER 0 (LOW)
TIMER 1 (LOW)
TIMER MODE
TRANSMIT STATUS (DMA & GSC)

8-4

inter

HARDWARE DESCRIPTION OF THE'S3C152

TFIFO - (85H) TFIFO is used to access a 3-byte FIFO
that contains the transmission data for the GSC.

The addresses of-the second 128 bytes of data memory
happen to overlap the SFR addresses. The SFRs and
their memory locations are shown in Figure 2.2. This
means that. internal data memory spaces have the same
address as the SFR address. However, each type of
memory is addressed differently. To access data memory above 80H, indirect addressing or the DMA channels must be used. To access the SFRs, direct addressing is used. When direct addressing is used, the address
is the source or destination, e.g. MOY A, IOH, moves
the contents of location IOH into the accumulator.
When indirect addressing is used, the address of the
destination or source exists within another register, e.g.
MOY A, @RO. This instruction moves the contents of
the memory location addressed by RO into the accumulator. Directly addressing the locations 80H to OFFH
will access the SFRs. Another form of indirect addressing is with the use of Stack Poillter Operations. If the
Stack Pointer contains an address and a PUSH or POP
instruction is executed, indirect addressing is actually
used. Directly accessing an unused SFR address will
give undefined results.

TSTAT - (OD8H) Contains the DMA Service bit
(DMA), Transmit Enable bit (TEN), Transmit FIFO
Not Full bit (TFNF), Transmit Done bit (TDN),
Transmit Collision Detect bit (TCDT), Underrun bit
(UR), No Acknowledge bit (NOACK), and the Receive oata Line Idle bit (LNI). This register is used
with both DMA and GSC.
The general purpose flag bits (GFO and GFl) that exist
on the 80C51BH are no longer available on the C152.
GFO has been renamed GFIEN (GSC Flag Idle Enable) and IS used to enable idle fill flags. Also GFI has
been renamed XRCLK (External Receive Clock Enable) and is used to enable the receiver to be clocked
externally.
2.1.2 DATA MEMORY

Internal data memory consists of 256 bytes as shown in
Figure 2.1. The first 128 bytes are addressed exactly
like an 80C51BH, using direct addressing.

Physically, there are separate SFR memory and data
memory spaces allocated on the chip. Since·there are
separate spaces, the SFRs do not diminish the available
data memory space.

rv
OffH

OfFH

(0)

OVERLAPPING
MEMORY
ADDRESSES

A

oaOH

(0)

(0)

SPECIAL FUNCTION REGISTER
SPACE

02fH
BIT ADDRESSABLE
MEMORY SPACE
020H
01FH

.,

REGISTER BANK 3
017H
REGISTER BANK 2
010H
REGISTER BANK 1
007H
REGISTER BANK 0

..

OOOH
USER DATA MEMORY SPACE

270427-1

°NOTE:
User data memory above BOH must be addressed indirectly. Using direct addressing above BOH accesses 'the Special
Function Registers.

Figure 2.1. Data Memory Map

8-5

inter

HARDWARE DESCRIPTION OF THE 83C152

External data memory is accessed like an SOC51BH,
with "MOVX" instructions. Addresses up to 64K may
be accessed when using the Data Pointer (DPTR).
When accessing external data memory with the DPTR,
the address appears on Port 0 and 2. When using the
DPTR, if less, than 64K of external data memory is
used, the address is emitted on all sixteen pins. This
means that when using the DPTR, the pins of Port 2
not used for addresses cannot be used for general purpose VO. An alternative to using 16-bit addresses with
the DPTR is to use RO or Rl to address the external
data memory. When using the registers to address external data memory, the address range is limited to 256
bytes. However, software manipulation of VO Port 2
pins as normal I/O, allows this 256 bytes restriction to
be expanded via bank switching. When using RO or Rl
as data pointers, Port 2 pins that'are not used for addressing, can be used as general purpose I/O.

2.1.2.1 Bit Addressable Memory
The C152 has several memory spaces in which the bits
are directly addressed by their location. The directly
addressable bits and their symbolic names are shown in
Figure 2.3A, 2.3B, and 2.3C.
Bit addresses 0 to 7FH reside in on-board user data
RAM in byte addresses 20H to 2FH (see Figure 2.3A).
Bit addresses SOH to.OFFH reside in the SFR memory
space, but not every SFR is bit addressable, see Figure
2.3B. The addressable bits are scattered throughout the
SFRs. The addressable bits occur every eighth SFR address starting at SOH and occupy the entire byte. Most
of the bits that are addressable in the SFRs have been
given symbolic names. These names will often be referred to in this or other documentation on the C152.
Most assemblers also allow the use of the symbolic
names when writing in assembly language. These
names are shown in Figure 2.3C.

PGSlE POIIA 1 PGSlV PDllAO PGSRE PGSRV OFBH

1

ADR2
SLOmA
SARHl
SARLl

'I I I I. 'II I. 'I I I I, 'I I I II. 'I I I I, 'II I II,
MYSLOT DCJ
RFIFO
BCRH 1
'BCRL 1

OCR

'//1,

SAS

SM

s.u

SA3

SAl

SAO

'II. 'III. '1111, 'III,

OF5H
OF4H
OF3H
OF2H

RDN

(0) IE

'I.

'I.

OESH

'I. 'II, 'III,

'II. '1111. 'III.

'III.
OE4H
OOH
OE2H

'I.

'I.

LNI NOACK UR

TCDT

TON

'II,

TFNF

TEN

OMA

OOSH
OOSH
OD4H
OD3H
002H

DARHl

DARL·I

'II,
ev
'II,

'I,

'II/I.

AC

FO

'I,

RSl

'I.

'11.'1111, 'III,
RSO

OV

'II. 'III, 'III,
'I.

ODOH

'I.
DC4H
OC3H
OC2H

'I.

OCOH

'IL

PTl

'I.
PXl

'I,
PTO

'II,
PXO

'I,

'//1,

OB8H

'IlL 'I, '1.'1111. 'III. '11/1.'11,

'I.
099H
098H
09SH
094H
093H
092H

REN

TB8

RB8

n

RI

IDA
IDA

SAS
SAS

!SA

!SA

OM
OM

TM
TM

DONE
DONE

GO
GO

DEiI

GTXD GRXD 090H

RD5A

TFlFO
GlAOD CTCLK
DPH
DPL
SP
(')PO

'I.
'I.

OA8H

'I,

SM2

THl
THO
TLl
TLO
TMOD GATE C
(')TCON TFl lRl
PCON SMOD ARB

OCSH

PS

OBOH

EXO

SMl

HLD

'i/i.

'ii.

loll
MO GATE ejl
TFO lRO
IEl
1T1
REQ GAREN XRCLK GFiEN

'II, 'II,
loll

'I,

!'"
'" > z Z z

INDEX
CORNER'\..



Q.

...

on
N
c..i c..i c..i 0
oi Q.
ci Q.
ci ci
oi
Z ,z Z oi
Q.
Q.
Q.

0.

'"

270427-6

Figure 2.58. PLCCPin Out.

2.7 Pin Desc.ription
The pin description for the 80C5lBH also applies to the C152 and is listed below. Changes have been made to the
. descriptions as they apply to the C152.

PIN DESCRIPTION
Pin
Name

Description

VSS

Circuit ground potential.

VCC

Supply voltage during normal, Idle, and Power down operation.' Nominally

+ 5V

...L 04nOI

.L lV-tO.

XTAL1
XTAL2

Input to the inverting oscillator amplifier. Also serves as the input for using an
external Clock signal.
Output from the oscillator amplifier.

PORTO

' Port 0 is an 8-bit open drain bi-directional 1/0 port. Port 0 pins that have 1s written to
them float and in that state can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external Program
and Data Memory: In this application it uses strong internal pullups when emitting
1s. Port 0 also outputs the code bytes during program verification in the 83C152.
External pullups are required during program verification.

PORT 1

Port 1 is an 8-bit bi-directionall/O port with internal pullups. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current because of the internal pull ups. Port 1 also has the following special
functions and for the special functions to operate a "1" has to be written to that pin
first.
8-12

inter

HARDWARE DESCRIPTION OF THE 83C152

2.7 PIN DESCRIPTION (Continued)
Pin
Name

Description
Port
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7

Alternate Function
GSC receiver data input (GR x D)
GSC transmitter data output (GT x D)
Drive Enable to enable external drivers (DEN)
GSC external transmit clock input (T x C)
GSC external receive clock input (Rx C)
DMA hold request 1/0 (HOlD_)_
DMA hold acknowledge I/O (HlDA)
none

PORT 2

Port 2 is an 8-bit bi-directionall/O port with internal pullups. Port 2 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 2 pins that are externally being pulled low will source
current because of the internal pull ups. Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external Data
Memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong
internal pullups when emitting 1s and cannot be used as inputs. During accesses to
external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the
contents of the P2 SFR. Port 2 receives the high-order address bits during program
verification of the ROM device.

PORT 3

Port 3 is an 8-bit bi-directionall/O port with internal pull ups. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the pull ups. Port 3 also has the following special functions and for the
special functions to operate that pin must be programmed to a "1" first.

Port
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7

Alternate Function
RXD (lSC serial data input port)
I
TXD (lSC serial data output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
I!JTimer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

PORT 4

Port 4 is an 8-bit bi-directionall/O port with 40 internal pullups. Port 4 pins that have
1s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 4 pins that are externally pulled-low will source
current because of the pullups. Port 4 also receives the low-order address bytes
during program verification in the 83C152.

RESET

Reset input. A low level on this pin for two machine cycles while the oscillator is
running resets the device. An internal diffused resistor to VCC permits Power-On
.
reset using only an external capacitor to VSS.

EA

External Access enable. EA must be externally held low in order to enable the
device to fetch code from external Program Memory locations OOOOH to 1FFFH.

ALE

Address latch Enable output pulse for latching the low byte of the address during
accesses to external memory. In normal operation ALE is emitted at a constant rate
of % the oscillator frequency, and may be used for external timing or clocking
purposes. Note, however, that one ALE pulse is skieP.ed during each access to
external Data Memory. (Including DMAs where no RD/WR generated for internal
source/destination.)

PSEN

Program Store Enable is the read strobe to external Program Memory. When the
C152 is executing code from external Program Memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each
access to external Data Memory.
8-13

intJ

HARDWARE DESCRIPTION OF THE 83C152

2.8 Power Down and Idle

2.9 Local Serial Channel

Both of these operations function identically as in the
80C51BH. Application Note 252, "Designing with the
80C5IBH" gives an excellent explanation on the use of
the reduced power consumption .modes. Some of the
items not covered in AP-252 are the considerations that
are applicable when using the GSC or DMA· in conjunction with the power saving modes.

The Local Serial Channel (LSC) is the name given to
the UART that exists on all MCS-51 devices. The
LSC's function and operation is exactly the same as on
the 80C51BH. For a description on the use of the LSC,
refer to the 8051/52 Hardware Description Chapter in
the Intel Embedded Controller Handbook, under Serial
Interface.

The GSC continues to operate normally in Idl~ as long
as the interrupts are enabled. The interrupts need to be
enabled, so that the CPU can service the FIFO's and
terminate transmission or reception when appropriate.
After servicing the. GSC, user software. will need to
again invoke the Idle command as the CPU does not
automatically re-enter the Idle mode after servicing the
interrupts.

3.0 GLOBAL SERIAL CHANNEL

3.1 Introduction

The GSC does not operate while in Power Down so the
steps required prior to entering Power Down become
more complicated. The sequence when entering Power
Down and the status of the I/O is of major importance
in preventing damage to the C152 or other components
in the system. Since the only way to exit Power Down
is with a Reset, several problem areas become very significant. Some of the problems that merit careful consideration are cases where the Power Down occurs during the middle of a transmission; and the possibility
that other stations are not or cannot enter this same
mode. The state of the GSC I/O pins becomes critical
and the GSC status will need to be saved before power .
down is entered. There will also need to be some method of identifying to the CPU that the following Reset is
probably not a cold start and that other stations on the
link may have already been initialized.
The DMA circuitry stops operation in both Idle and
Power Down modes. Since operation is stopped' in both
modes, the process should be similar in each case. Specific steps that need to be taken include: notification to
other devices that DMA operation is about to cease for
a particular station or network, proper withdrawal
from DMA operation, and saving the status' of the
DMA channels. Again, the status of the I/O pins during Power Down needs careful consideration to avoid
damage to the C152 or other components.

The Global Serial Channel (GSC) is a multi-protocol,
high performance serial interface targeted for data rates
up to 2 MBPS with on-chip clock recovery, and 2.4
MBPS using the external clock options. In applications
using the serial channel, the GSC implements the Data
Link Layer and Physical Link Layer as described in the
ISO reference model for open systems interconnection.
The GSC is designed to meet the requirements of a
wide range of serial communications applications and is
optimized to implement Carrier-Sense Multi-Access
with Collision Detection (CSMA/CD) and Synchronous Data Link Control (SDLC) protocols. The GSC
architecture is also designed to provide flexibility in defining non-standard protocols. This provides the ability
to retrofit new products into older serial technologies,
as well as the development of proprietary interconnect
schemes for serial backplane environments.
The versatility of the GSC is demonstrated by the wide
range of choices available to the user. The various
modes of operation are summarized in Table 3.1. In
subsequent sections, each available choice of operation
will be explained in detail.
In using Table 3.1, the parameters listed vertically (on
the left hand side) represent an option that is selected
(X). The parameters listed horizontally (along the top
of the table) are all the parameters that could. theoretically be selected (Y). The symbol at the junction of
both X and Y determines the applicability of the option

Y.

Port 4 returns to its input state, which is high level
using weak pullup devices.

Note, that not all combinations are backwards compati~
ble. For example, Manchester encoding requires half
duplex, but half duplex does not .require Manchester
encoding.

8-14

HARDWARE DESCRIPTION OF THE 83C152

Table 3.1
DATA
ENCODING

N=NOT AVAILABLE
M=MANDATORV
O=OPTIONAL
P = NORMALLV PREFERRED
X=N/A

M
A
N
C
H
E

FLAGS

N

N

0

R

R

Z

Z
I

1
1
1
1
1
1

S
T

DU·
PLEX

CRC

1
1

N

1

0

/
I

N
E

6
B
I
T

D

L

C
C

E

I
T

0

E
R

3
2
B
I
T
A

H
A
L
F

ACKNOWLEDGE

N

F
U

0

L
L

N
E

H
A

U

N

S

0

R
D
W

E

N
E

A
R
E

U

T
0

ADDRESS
RECOGNITION

R
D
E
F

I
N
E
D

8'
B
I

T

1
6
B
I

T

/
A
L
L

BACKOFF

N

A

0

L
T

R

M
A
L

D
E

T

E
R

E
R

N
A

M
I
N
I

T
E

PREAMBLE

N

0
N
E

8
B
I

T

S
T
I
C

DATA ENCODING:
MANCHESTER(CSMA/CD)

X

N

N

1

P

1

0

0

M

N

0

0

0

0

0

0

0

0

0

N

0

NRZI (SDLC)

N

X

N

P

1

1

0

0

0

0

0

N

P

0

0

0

N

N

N

0

0

'. NRZ (EXT CLK)

N

N

X

0

0

1

0

0

0

0

0

N

0

0

0

0

0

0

0

0

0

N

P

0

X

1

1

0

0

0

0

0

N

P

0

0

0

N

N

N

0

0

P

N

0

1

X

1

0

0

0

N

0

0

0

0

0

0

0

0

0

1

0

1

1

1

1

1

X

N

N

1

N

1

1

1

1

1

1

N

N

N

1

1

0

0

0

0

0

N

X

N

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

N

N

X

0

N

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

X

N

0

0

0

0

0

0

0

0

0

0

0
0

FLAGS:Ollllll0 (SDLC)
11/IDLE
CRC:NONE
l6-BITCCITI
32-BIT AUTODIN II
DUPLEX:HALF

N

0

0

M

N

N

M

N

N

X

0

N

P

0

0

0

N

N

N

0

0

0

0

0

0

1

0

0

0

0

X

N

N

0

0

0

0

0

0

0

0

HARDWARE

0

N

N

N

0

1

0

0

0

N

N

X

N

0

0

0

N

0

0

N

0

USER DEFINED

0

P

0

0

0

1

0

0

0

P

N

N

X

0

0

0

0

0

0

0

0

FULL
ACKNOWLEDGEMENT:NONE

ADDRESS RECOGNITION:
NONE/ALL

0

0

0

0

0

1

0

0

0

0

0

0

0

X

N

N

0

0

0

0

0

8-BIT

0

0

0

0

0

1

0

0

0

0

0

0

0

N

X

N

0

0

0

0

0

l6-BIT

0

0

0

0

0

1

0

0

0

0

0

0

0

N

N

X

0

0

0

0

0

COLLISION RESOLUTION:

0

N

0

N

0

N

0

0

M

N

0

N

0

0

0

0

X

N

N

N

0

ALTERNATE

O'

N

0

N

0

N

0

0

M

N

0

0

0

0

0

0

N

X

N

N

0

DETERMINISTIC

0

N

0

N

0

N

0

0

M

N

0

0

0

0

0

0

N

N

X

N

0

N

0

0

0

1

1

0

0

0

0

0

N

0

0

0

0

N

N

N

X

N

8-BIT

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

N

X

32-BIT

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

N

N

NORMAL

PREAMBLE:NONE

\

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

N

N

JAM:D.C.

M

N

N

N

0

N

0

0

M

N

0

0

0

0

0

0

0

0

0

N

0

CRC

M

N

N

N

0

N

0

0

M

N

0

0

0

0

0

0

0

0

0

N

0

N

M

.N

0

0

N

0

0

0

0

0

N

0

0

0

0

N

N

N

0

0

0

0

N

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0
0

64-BIT

CLOCKING:EXTERNAL
INTERNAL
CONTROL: CPU

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RAW RECEIVE:

1

1

1

1

1

1

1

1

1

N

1

1

1

1

1

1

0

0

0

1

1

RAW TRANSMIT:

1

1

1

1

1

1

1

1

1

N

1

1

1

1

1

1

N

N

N

1

1

CSMAlCD:

0

N

2

1

P

1

0

0

M

N

0

0

0

0

0

0

0

0

0

N

0

SDLC:

N

0

0

P

1

1

0

0

0

0

0

N

0

0

0

0

N

N

N

P

0

DMA

8-15

HARDWARE DESCRIPTION OF THE 83C152

Table 3.1 (Continued)
PRE·
AMBLE

2

6
4

B
I
T

B
I
T

3
N= NOT AVAILABLE
M=MANDATORY
0= OPTIONAL
P= NORMALLY PREFERRED
X=N/A

JAM
D
C

CLOCK
C
R
C

E
X
T
E
R
N
A
L

I

I
N
T
E
R
N
A
L

CONTROL
C
P
U

D
M
A

R
A

R
A

C

W

W

R
E
C
E
I
V
E

T
R
A
N

M
A

5

5
D
L
C

I
C
D

S
M
I
T

DATA ENCODING:
MANCHESTER

0

0

0

0

N

M

0

0

0

0

M

N

NRZI

0

0

N

N

N

M

0

0

0

0

N

M

NRZ

0

0

0

0

M

N

0

0

0

0

0

0

FLAGS:01111110

0

0

N

N

0

0

0

0

0

1

1

P

1111DLE

0

0

0

0

0

0

0

0

0

1

P

1

1

1

N

N

1

1

1

1

1

1

1

1

CRC:NONE
16·BIT CCITT

0

0

-0

0

0

0

0

0

1

1

0

0

32·BIT AUTODIN "

0

O.

0

0

0

0

0

0

1

1

0

0

DUPLEX:HALF

0

0

0

0

0

0

0

0

0

0

0

0

FULL

0

0

N

N

0

0

0

0

N

N

N

P

0

0

0

0

0

0

0

0

0

0

0

0

HARDWARE

0

0

0

0

N

0

0

0

N

N

0

N

USER DEFINED

0

0

0

0

0

0

0

0

0

0

0

1

ACKNOWLEDGEMENT:NONE

ADDRESS RECOGNITION:
NONE

0

0

0

_0

0

0

0

0

0

0

0

0

8·BIT

0

0

.0

0

0

0

0

0

1

1

0

0

16·BIT

0

0

0

0

0

0

0

0

1

1

0

0

COLLISION RESOLUTION:
NORMAL

0

0

0

0

N

0

0

0

0

N

M

N

ALTERNATE

0

0

0

0

N

0

0

,0

0

N

M

N

DETERMINISTIC

O.

0

0

0

N

0

0

0

0

N

M

N

N

N

N

N

0

0

0

0

0

0

N

P

N

N

0

0

0

0

0

0

1

1

0

0

32·BIT

X

N

0

0

0

0

0

0

1

1

0

0

64·BIT

N

X

0

0

0

0

0

0

1

1

0

0

JAM:D.C.

0

0

X

N

2

0

0

0

0

N

M

N

CRC

0

0

N

X

2

0

0

0

0

N

M

N

0

0

N

N

X

N

0

0

0

0

2

0

INTERNAL

0

0

0

0

N

X

0

0

0

0

0

0

CONTROL:CPU

0

0

0

0

0

0

X

N

0

0

0

0

0

0

(j

0

0

0

N

X

0

0

0

0

RAW RECEIVE:

1

1

0

0

1 '

1

1

1

X

N

1

1

RAW TRANSMIT:

1

1

N

N

1

1

1

1

N

X

1

1

CSMAlCD:

0

0

0

0

2

0

0

0

0

0

X

N

SDLC:

0

0

N

N

0

0

0

0

0

0

N

X

PREAMBLE:NONE

8·BiT

CLOCKING:EXTERNAL

DMA

8·16

HARDWARE DESCRIPTION OF THE 83C152

of collision resolution made available to the user on the
C152. Re-transmission is attempted when a resolution
algorithm indicates that a station's opportunity has arrived.

Note 1: Programmable in Raw transmit or receive
mode.
Note 2: When CSMA/CD is enabled, an external clock
can be used on the transmitter, but not the receiver.
Since the receiver monitors the link for Manchester violations, external hardware would be required to reformat the data from NRZ to Manchester on the transmitter. These hardware requirements go beyond the expectations of this table for implementation. For that reason
it was assumed that the external clock cannot be used
at all with CSMA/CD protocol, although it is actually
possible to do so.
Almost all the options available from Table 3.1 can be
implemented with the proper software to perform the
functions that are necessary for the options selected. In
Table 3.1, a judgment has been made by the authors on
which options are practical and which are not. What
this means is that in Table 3.1, an UN" should be interpreted as meaning that the option is either not practical
when implemented with user software or that it cannot
be done. An "0" is used when that function is one of
several that can be implemented with the GSC without
additional user software.
The GSC is targeted to operate at bit rates up to 2.4
MBps using the external clock options and up to 2
MBps using the internal baud rate generator, internal
data formatting and on-chip clock recovery. The baud
rate generator allows most standard rates to be
achieved. These standards include the proposed
IEEE802.3 LAN standard (1.0MBps) and the T1 standard (1.544MBps). The baud rate is derived from the
crystal frequency. This makes crystal selection important when determining the frequency and accuracy of
the baud rate.

3.2 CSMA/CD Operation
3.2.1 CSMA/CD OVERVIEW
CSMA/CD operates by sensing the transmission line
for a carrier, which indicates link activity. At the end of
link activity, a station must wait a period of time, called
the deference period, before transmission may begin.
The deference period is also known as the interframe
space. The interframe space is explained in Section
3.2.3.
With this type of operation, there is always the possibility of a collision occurring after the deference period
due to line delays. If a collision is detected after transmission is started, a jamming mechanism is used to ensure that all stations monitoring the line are awar,e of
the collision. A resolution algorithm is then executed to
resolve the contention. There are three different modes

Normally, in CSMA/CD, re-transmission slot assignments are intended to be random. This method gives all
stations an equal opportunity to utilize the serial communication link but also leaves the possibility of another collision due to two stations having the same slot
assignment. There is an option on the C152 which allows all the stations to have their slot assignments previously determined by user software. This pre-assignment of slots is called the deterministic resolution
mode. This method allows resolution after the first collision and ensures the access of the link to each station
during the resolution. Deterministic resolution can be
advantageous when the link is being heavily used and
collisions are frequently occurring and in real time applications where determinism is required. Deterministic
resolution may also be desirable if it is known beforehand that a certain station's communication needs to be
prioritized over those of other stations if it is involved
in a collision.
3.2.2 CSMAlCD FRAME FORMAT
The frame format in CSMA/CD consists of a preamble, Beginning of Frame flag (BOF), address field, information field, CRC, and End of Frame flag (EOF) as
shown in Figure 3.1.

IPREAMBLE IBOF IADDRESS IINFO ICRC IEOF I
Figure 3.1 Typical CSMA/CD Frame

PREAMBLE - The preamble is a series of alternating
Is and Os. The length of the preamble is programmable
to be 0, 8, 32, or 64 bits. The purpose of the preamble is
to allow all the receivers to synchronize to the same
clock edges and identifies to the other stations on-line
that there is activity indicating the link is being used.
For these reasons zero preamble length is not compatible with standard CSMAlCD, protocols. When using
CSMAlCD, the BOF is considered part of the preamble compared to SDLC, where the BOF is not part of
the preamble. This means that if zero preamble length
were to be used in CSMA/CD mode, no BOF would be
generated. It is strongly recommended that zero preamble length never be used in CSMA/CD mode. If the
preamble contains two consecutive Os, the preamble is
considered invalid. If the C152 detects an invalid preamble, the frame is ignored.
BOF - In CSMA/CD the Beginning-Of-Frame is a part
of the preamble and consists of two sequential Is. The
purpose of the BOF is to identify the end of the preamble and indicate to the receiver(s) that the address will
immediately follow.

8-17

HARDWARE DESCRIPTION OF THE 83C152

ADDRESS - The address field is used to identify which
messages are iIi.tended for which stations. The user
must assign addresses to each destination and source.
How the addresses are assigned, how they are maintained, and how each transmitter is made aware of
which addresses are available is an issue that is left to
the user. Some suggestions are discussed in Section
3.5.5. Generally, each address is unique to each station
but there are special cases where this is not true. In
these special cases, a message is intended for more than
one station. These multi-targeted messages are called
broadcast or multicast-group addresses. A broadcast
address consisting of all Is will always be received by
all stations. A multicast-group address usually is indicated by using a las the first address bit. The user can
choose to mask off all or selective bits of the address so
that the GSC receives all messages or multicast-group
messages. The address length is programmable to be 8
or 16 bits. An address consisting of all Is will always be
received by the GSC on the C152. The address bits are
always passed from the GSC to the CPU. With user
software, the address can be extended beyond 16 bits,
but the automatic address recognition will only work
on a maximum of 16 bits. User software will have to
resolve any remaining address bits.

algorithm can be used but IEEE 802.3 uses a 32-bit
CRC. The generation polynomial the CI52 uses with
the 32-bit CRC is:
G(X) = X32 + X26 + X23 + X22 +X16 + XI2 +
,
. XII + XIO + X8 + X7 + X5 + X4 + X2
.+ X + I
The CRC generator, as shown in Figure 3.2, operates
, by taking each bit as it is received and XOR'ing it with
bit 31 of the current eRC. This result is then placed in
temporary storage. The result of XOR'ing bit 31 with
the received bit is then XOR'd with bits 0, I, 3, 4, 6, 7,
9, 10, 11, 15,21,22,25 as the CRC is shifted right one
position. When the CRC is shifted right, the temporary
storage space holding the result of XOR'ing bit 31 and
the incoming bit is shifted into position O. The whole
process is then repeated with the next incoming or out.
going bit.
The usei' has no access to the CRC generator or the bits
which constitute the CRC while in CSMAlCD. On
transmission, the CRC is automatically appended to
the data being sent, and on reception, the CRe bits are
not normally loaded into the receive FIFO. Instead,
they are automatically stripped. The only indication the
user has for the status of the eRC is a pass/fail flag.
The pass/fail flag only operates during reception. A
CRC is considered as passing when the the CRC generator has 1100011100000100 11011010 011110IlB as a
remainder after all of the data, including the CRe
checksum, from the transmitting station has been cycled through the CRC generator. The preamble, BOF
and EOF are not included as part of the CRC algorithm. An interrupt is available that will interrupt the
CPU if the CRC of the receiver is invalid. The user can
enaole the CRC to be passed to the CPU by placing the
receiver in the raw receive mode.

INFO - This is the information field and contains the
data that one device on the link wishes to transmit to
another device. It can be of any length the user wishes
but needs to be in multiples of 8 bits. This is because
multiples of 8 bits are used to transfer data into or out
of the GSC FIFOs. The information field is delineated
from the rest of the components of the frame by the
preceding address field and the following CRC.. The
receiver determines the position of the end of the information field by passing the bytes through a temporary
storage space. When the EOF is received the bytes in
temporary storage are the CRC, and the last bit received previous to the CRC constitute the end of the
information field.

This method of calculating the CRC is compatible with
IEEE 802.3.

CRC - The Cyclic Redundancy Check (CRC) is an error checking algorithm commonly used in serial communicationS. The CI52 offers two types of CRC algorithms, a 16-bit and a 32-bit. The 16-bit algorithm is
normally ~sed in the SDLC mode and will be described
in the SDLC section. In CSMAlCD applications either

EOF - The End Of Frame indicates when the transmis,ion i, comnleted. The end flag in CSMA/CD consists
~i an idle c~ndition. An idle c;ndition is assumed when
there is no transitions and the link remains high for 2 or
more bit times.

8-18

HARDWARE DESCRIPTION OF THE 83C152

270427-8

Figure 3.2. CRC Generator

around period is the amount of time that is needed by
user software to complete the handling of a received
frame and be prepared to receive the next frame. An
interframe space smaller than the required tum-around
period could be used, but would allow some frames to
be missed.

3.2.3 INTER FRAME SPACE

The interframe space is the amount of time that transmission is delayed after the link is sensed as being idle
and is used to separate transmitted frames. In alternate
backoff mode, the interframe space may also be included in the determination of when retransmissions may
actually begin. The C152 allows programmable interframe spaces of even numbers of bit times from 2 to
256.

When a GSC transmitter has a new message to send, it
will first sense the link. If activity is detected, transmission will be deferred to allow the frame in progress to
complete. When link activity ceases, the station continues deferring for one interframe space period.

The period of the interframe space is determined by the
contents of IFS. IFS is an SFR that is programmable
from 0 to 254. The interframe space is measured in bit
times. The value in IFS mUltiplied by the bit time
equals the interframe space unless IFS equals O. If IFS
does equal 0, then the interframe space will equal 256
bit times. One of the considerations when loading the
IFS is that only even numbers (LSB must be 0) can be
used because only the 7 most significant bits are loaded
into IFS. The LSB is controlled by the GSC and determines which half of the IFS is currently being used. In
some modes, the interframe space timer is re-triggered
if activity is detected during the first half of the period.
The GSC determines which half of the interframe space
is currently being used by examining the LSB. A one
indicates the first half and zero indicates the second
half of the IFS.

As mentioned earlier, the interframe space is used during the collision resolution period as well as during normal transmission. The backoff method selected affects
how the deference period is handled during normal
transmission. If normal backoff mode is selected, the
interframe space timer is reset if activity occurs during
approximately the first half of the interframe space. If
alternate backoff or. deterministic backoff is selected,
the timer is not reset. in all cases whe~ the interframe
space timer expires, transmission may begin, regardless
if there is activity 'on the link or not. Although the
C152 resets the interframe space timer if activity is detected during the first one-half of the interframe space,
this is not necessarily true of all CSMA/CD systems.
(IEEE 802.3 recommends that the interframe space be
reset if activity is detected during the first two-thirds or
less of the interframe space.)

After reset IFS is 0, which delays the first transmission
for both SDLC and CSMA/CD by 256 bit times (after
reset, a bit time equals 8 oscillator clock periods).

3.2.4 COLLISION RESOLUTION

In most applications, the period of the interframe space
will be equal to or greater than the amount of time
needed to tum-around the' received frame. The turn-

The method used to resolve a collision is called the
backoff algorithm.
8-19

HARDWARE DESCRIPTION OF THE 83C152

How the backoff algorithm executes is dependent on
which part of the frame the collision was detected in.
How collisions are detected is shown in Figure 3.3. If
the collision occurred before data has been loaded into
the Receive FIFO, then reception' is simply stopped.

A collision is assumed if a pulse is less than three sample periods in length or if an. expected transition is
missed. Figures 3.3A and B show where transition must
occur and where transitions are invalid. The sample
. periods occur at a rate that is 8 times the baud rate as
determined by the SFR BAUD.

The time when the first byte is loaded into the Receive
FIFO is dependent on the CRC length. After detection
of the BOF flag, all subsequent data is passed through.
the CRC stripping/generation hardware. Also,there is
an additional delay of 8 bit times, as the Receive FIFO
operates with only eight bit quantities. This means that
after the BOF, there is a 24(40) bit time delay before
data is loaded into the Receive FIFO if the 16(32) bit
CRC is selected. If the collision occurs after data has
been loaded into the receive FIFO, then .the error flag
Receiver Abort (RCABT) is set and REN cleared. This
prevents another reception while the CPU tries to figure out what to do next. If the Enable Global Serial
(channel) Receive Error (EGSRE) interrupt (IENl.l)
is enabled the CPU is interrupted. At this time user
software must decide what actions to take to assure a
proper recovery.

LOGICAL
VALUE

1.

During transmission, each device monitors its own
transmission pin with its receive circuitry. A collision is
assumed if the receiver detects Manchester encoding
violations as defined in Figures 3.3A and B.
Where the collision occurs determines what actions are
taken. If the collision occurs after the preamble, the
Timer Collision Detect (TCDT) bit is set. If the Enable
Global Serial Transmit Error (EGSTE) interrupt
(lEN 1. 5) is enabled, the CPU is interrupted. If this type
of collision occurs, user software must determine what
actions to take for a proper recovery.
If the transmitting station detects the collision during

the preamble or BOF, the actions taken are automatic.
The transmitter will attempt resolution up to eight
tries. After the eighth attempt, the error flag (TCDT) is
set. If EGSTE is enabled, the CPU is then interrupted.

o

o

o

MANCHESTER
ENCODING

.

".,. - - - "1" BIT, TIME - - - -.....
".:..'- - "0" BIT TIME - - - -..
"
(8 X BAUD)
R.ECEIVt
SAMPLING
RATE

,

INVALID

MANDATORY TRANSITION
270427-9

Figure 3.3A. CSMA/CD COllisions
8~20

HARDWARE DESCRIPTION OF THE 83C152

LOGICAL
VALUE

o

o

MANCHESTER
ENCODING

,,>---...

.

"1" BIT TIME - - - - - - - - - - "1" BIT TIME - - - -..
"

,

(8 X BAUD)
RECEIVE
SAMPLING'
RATE

INVALID

MANDATORY TRANSITION

OPTIONAL TRANSITION
270427-10

Figure 3.3B. CSMAlCD Collisions

When a transmitting GSC detects a collision, the first
action taken is to apply a jamming signal to the link.
The jam is sent following the end of the preamble, or
immediately if the preamble has already .been completed. This action is taken to insure that other stations on
the link are aware that a collision has occurred.

algorithm is used. These methods are .named: "Normal
Backoff", "Alternate Backoff", and "Deterministic
Backoff".
Before going into detail on the various backoff schemes,
there is a parameter called the slot time that must be
understood by the user. The slot time is used during the
collision resolution and is the basic scheduling quantum
for retransmission once a collision is detected. The slot
time also represents the maximum length of a collision
fragment and the upper bound on the acquisition time
of the network. The value of the slot time is determined
by the contents of SLOTTM. SLOTTM is programmable from b to 255. A slot time is equal to 256-SLOTTM
multiplied by the bit time,unless SLOTTM equals o. If
o is used in SLOTTM, th~n the slot time period will
equal 256 bit times.· A bit time is equal to Ilbaud rate.
The timing requirements on the slot time is that it be
equal to, or greater than the longest round-trip propagation time of the signal plus the jam time. The jam
time is equal to the CRC length.

The jamming signal can be one of two types, D.C. or
CRC. D.C. jam is selected by setting the DCI bit
(MYSLOT.7). The D.C. jam applies a continuous low
level signal for a duration equal to the CRC length. To
select the CRC type of jam, the DCJ bit needs to be
cleared. CRC is selected after the C152 is reset. The
CRC,jam operates by taking the current CRC calculated up to that point, inverting the data and applying that
signal to the. link.
After applying the jam, the resolution phase is next.
This phase will effect the throughput and efficiency of
the link once a collision is detected. There are three
methods to choose from that determine which backoff
8-21

intJ

HARDWARE DESCRIPTION OF THE 83C152

In alternate mode the backoff time begins immediately
at the end of an interframe space after the jam. If alternate backoff is used then the slot time does not occur
unin after the interframe space expires as shown in Figure 3.4. This mode will usually be used when the interframe space is longer than the slot time. This prevents
the situation where the slot time expires before the interframe space period. This preserves the bandwidth of
the collision resolution by insuring that each station is
allowed up to 8 re-attempts at transmission. Networks
where the slot time is less than the interframe space
generally exist where there is a short topology, or high
data rates are used.

Normal and Alternate CSMA/CD Modes
In the Normal and Alternate Normal resolution modes,
the slot position assigned .to a station is determined by
the SFR, Pseudo Random Binary Sequence (PRBS).
The PRBS generates a random number by using a series of feedback shift registers that are clocked by the
CPU phase clocks.
There is a maximum physical limit of 256 slot positions
available. The slot assigned is derived from PRBS during the resolution phase of a collision. But the value in
PRBS is ANDed' with the contents of TCDCNT. The
way TCDCNT operates is that as collisions occur,
TCDCNT shifts left one bit position and a 1 is shifted
into the LSB. As TCDCNT is filled with Is from collisions, the maximum range of slot assignments also increases by powers of 2. This variable upper limit is determined by the number of collisions, but can never be
greater than 255. The PRBS maximum value will be
(2**n)-I, where n is the number. of pre~?usly a~­
tempted transmissions that resulted In a colliSion. This
means that on the first re-transmission, the PRBS value
could be 0 or I, on the second re-transmission the
PRBS could be any value from 0 to 3, and on the eighth
collision PRBS could be any value from 0 to 255. There
is no way that the user software can get access to the
slot position assigned to a station once the backoff process has started.

Deterministic Collision Resolution
In Deterministic Collision Resolution, when a collision
occurs, all stations enter a special mode, whether or not
they were involved in the collision. The resolution p~ri­
od is divided into a programmable number of slots With
each station having a unique slot assignment. The first
slot starts after one interframe space. A station is allowed to start transmitting only during its own slot and
will transmit as long as it needs to unless some error
occurs. After any transmission, one interframe expires
before the next slot begins. If no collision occurs, the
protocol operates as in regular CSMA/CD mode.

The backoff can be programmed to start either at the
end of the jam, as in Ethernet, or at the end of the
interframe space.
In normal mode the backoff time begins immediately at
the end of the jam. The slot time begins as soon as the .
jam is completed but must wait until at le~t one int~r­
frame space has completed before attemptIng transnussion. Slot 0 is the first to occur, followed by Slot 1 and
so on. This means the lowest slot number assigned will
win control of the link as long as the slot time ends
after the the interframe space expires. In networks
where the slot time is longer than the interframe space,
normal backoff will usually be implemented. This is
because the interframe space time will expire before
Slot 0 is complete. This is shown in Figure 3.4. In net- .
works where the interframe space is longer than the slot
time, Slot 0 will expire before the interframe space and
will not be able to transmit during that resolution attempt. Taken to an extreme where the interframe space
is much larger than the slot time, it is possible that
there will be no resolution during the first couple of
collisions because the possible number of slot times
available will still be less than the interframe space.
This would waste the bandwidth of the resolution by
not allowing all stations the opportunity of 8 attempts
at retransmission.

8-22

This method operates as follows. The user software assigns each station its own slot position and loads it in
the SFR, MYSLOT. That station has to wait a number
of slot times equal to (maximum number of slots) (MYSLOT). Only the lower six bits of MYSLOT are
used for slot assignment. This means that when using
deterministic resolution, a maximum of 63 stations in
the network can participate in any collision resolution.
Another station may be added to the network, but not
allowed to participate in a resolution. That station
should have 0 as its assigned slot. This prevents the
station from attempting to retransmit during the collision resolution. When using deterministic resolution,
the PRBS must be disabled. By writing OFFH into the
PRBS, it is frozen into an all Is st.at.e. The maximum
number of stations that may be involved in the resolution is loaded into TCDCNT. The slot count does not
begin until the receiver senses that the line is idl~ and
one interframe space expires. At the end of the Interframe space the GSC starts counting the slots. Alternate backoff mode should be selected whenever deterministic backoff mode is being used. Then, if activity is
detected on the link with deterministic backoff mode
selected, the GSC first waits uhtil the link is idle and
then waits until the end of the interframe space before
the slot timer continues counting the slots. This allows
another station to transmit a pending message in its
proper slot and 'each station gets an opportunity to
transmit when the slot time equals the value in its
MYSLOT register.

HARDWARE DESCRIPTION OF THE 83C152

The bottom diagram of Figure 3.4 illustrates this mechanism for a number of stations (MAX). It shows stations with slot numbers (MAX-2), 2 and I transmitting
during the resolution period. Note the interframe space
after the jam and after each transmission. After all the
slot positions have been exercised, normal CSMA/CD
operation resumes. Unless deterministic resolution is
selected, it is possible that stations not involved in the

collision may attempt transmission during the resolution period after an interframe space period. Deterministic mode prevents this from happening because all
stations on the link are required to enter into the resolution phase, whether or not they are involved in the
collision. Then, a station is either allowed to transmit
during its assigned slot or is prevented from transmitting during the resolution period.

Normal 8ackoff

Alternate 8ackoff

~.
SLOT TIME

FIRST

IFS
FIRST

~.
SLOT TIME
SECOND

IFS

ST

IFS
IFS ST

SLOT TIME

SLOT TIME

SLOT TIME

SLOT TIME

SECOND
SLOT TIME

COLLISION-

IFS

ST ST

IFS

ST Sf. ST

COLLISION

270427-11

Normal 8ackoff Mode
(CURRENT
BACKOFF
VALUE=) ~.- - - - - - ( 5 ) . (4) (3) (2) (.) (0)

(lN~IAL =><+!_+_--:)>.j..:~:,-:-----~:~-:-:-:-::-:-:-:-:
j

BACKOFF

I

I

: :.... : :
I

I
:

I

I

VALUE=5):
...

I

It-,

I

I

I

I

I

~ :~: :I!!: ~ : r:: :'~ : ~ : ~

,

(CURRENT
BACKOFF

VALUE=)~'------' (3) (2) (') (0)

-V:

)::::

:
Ie,

(INI~IAL -"...c:""_+-_J.""'''' "

9ACKOFF
.,
VALUE=3):

: :.... : :
1,1-,

~ :12:

;::
T1
T2
T3
T4
T5

=
=
=
=

=

I

:I!!:

I

I

I

~: J:::: ~:

270427-12

T6 = Slot A(#4) or 8(#2) Occurring
T7 = Slot A( # 3) or 8( # 1) Occurring
T8 = Slot A( # 2) Occurring
T8 = Station 8 8egins Transmission
T10 = Station A Loses Slot Assignment

Collision Detected
Jam Applied
Idle Detected
Interframe Space Period
Slot A( # 5) or 8( # 3) Occurring

Deterministic 8ackoff .Mode

,,
,
, ,, ,

,,
,
, ,, ,
;::
T1
T2
T3
T4
T5
T6
T7

~

,

~

1.... '&1')1
11-11-1

~

~

'00 10'1'
11-11-1

= Collision Detected
= Jam Applied
= 1 IFS, No Activity

0

;::

,

;::

;::

;::
'"

...

;::
270427-13

T8 = Assume Slot Time 4 Occurring
T9 = Slot Time 3 Occurring
T1 0 = Slot Time 2 Occurs with Activity
T11 = IFS for Slot Time 2
T12 = Slot Time 1 Occurs with Activity
T13 = IFS for Slot Time 1
T14 = Normal CSMAlCD Activity

Slot Time for Maximum Available Slot Occurring
Slot Time for (MAX·1) Occurring
= Slot Time for (MAX·2) Occurs with Activity
= IFS for Slot Time (MAX·2)
=
=

. Figure 3.4. Slot Time Resolution
8-23

inter

HARDWARE DESCRIPTION OF THE 83C152

A transmitting station with HABEN enabled expects
an acknowledge. It must receive one prior to the end of
the interframe space, or else an error is assumed and
the NOACK bit is set. Setting of the TON bit is also
delayed until the end of the interframe space. Collisions
detected during the interframe space will also cause
NOACK to be set.

3.2.5 CSMA/CD DATA ENCODING
Manchester encoding/decoding is automatically selected when the user software selects CSMA/CO transmission mode (See Figure 3.5). In Manchester encoding
the value of the bit is determined by the transition in
the middle of the bit time, a positive transition is decoded as a 1 and a negative transition is decoded as a O.

The user software may enable the interrupt so that the
CPU is notified when TON is set. If the OSC is serviced by OMA, the user must time out one interframe
space and then check the NOACK bit or the TON bit.

If the external IX clock feature is chosen the transmission mode is always NRZ (see Section 3.5.11). Using
CSMA/CO with the external clock option is not supported because the data needs reformatting from NRZ
to Manchester for the receiver to be able to detect code
violations and collisions.

3.3 SOLe Operation

3.2.6 HARDWARE BASED ACKNOWLEDGE

3.3.1 SDLC OVERVIEW

Hardware Based Acknowledge (HBA) is a data link
packet acknowledging scheme that the user software
can enable with CSMA/CO protocol. It is not an option with SOLC protocol however.

SOLC is a communication protocol developed by IBM
and widely used in industry. It is based on a primary/
secondary architecture and requires that each secondary station have a unique address. The secondary stations can only communicate to the primary station, and
then, only when the primary station allows communication to take place. This eliminates the possibility of
contention on the serial line caused by the secondary
station'S trying to transmit simultaneously.

In general HBA can give improved system response

time and increased effective transmission rates over acknowledge schemes implemented in higher layers of the
network architecture. Another benefit is the possibility
of early release of the transmit buffer as soon as the
acknowledge is received.

In the CIS2, SOLC can be configured to work in either
full or half duplex. When adhering to strict SOLC protocol, full duplex is required. Full duplex is selected
whenever a 16-bit CRC is selected. At the end of a valid
reset thel6"bit CRC is selected. To select half duplex
with a 16-bit CRC, the receiver must be turned off by
user software before transmission. The receiver is
turned off by clearing the OREN bit (RSTAT.l). The
receiver needs to be turned off because the address that
is transmitted is the address. of the secondary station'S
receiver. If not turned off, the receiver could mistake
the outgoing message as being intended for itself. When
32-bit CRCs are used, half duplex is the only method
available for transmission.

The acknowledge consists of a preamble followed by an
idle condition. A receiving station with HABEN enabled will send an acknowledge only if the in"oming
address is unique to the receiving station and if the
frame is determined to be correct with no errors. 'For
the acknowledge to be sent, ten must be set. For the
transmitting· station to recognize the acknowledge
OREN must be set. A zero as the LSB of the address
indicates that the address is unique and not a group or
broadcast address. Errors can be caused by collisions,
incorrect CRC, misalignment, or FIFO overflow. The
receiver sends the acknowledge as soon as the line is
sensed to be idle. The l!~cr must progI1h~ the interframe
space and the preamble length such that the acknowledge is completed before IFS expires. This is normally
done by programming IFS larger than the preamble.

o

o

I
BIT
I
- - TIME--+;

o

270427-14

Figure 3.5. Manchester Encoding

8-24

inter

HARDWARE DESCRIPTION OF THE 83C152

3.3.2 SOLC Frame Format
The format of an SOLC frame is shown in Figure 3.6.
The frame consists of a Beginning of Frame flag, Address field, Control Field, Information field (optional),
a CRC, and the End of Frame flag.

IBOF IADDRESS ICONTROL IINFO ICRC IEOF I
Figure 3.6. Typical SOLC Frame

BOF - The begin of frame flag for SOLC is 01111110.
It is only one of two possible combinations that have six

consecutive ones in SOLC. The other possibility is an
abort character which consists of eight or more consecutive ones. This is because SOLC utilizes a process
called bit stuffing. Bit stuffing is the insertion of a 0 as
the next bit every time a sequence of five consecutive Is
is detected. The receiver automatically removes a 0 after every consecutive group of five ones. This removal
of the 0 bit is referred to as bit stripping. Bit stuffing is
discussed in Section 3.3.4. All the procedures required
for bit stuffing and bit stripping are automatically han. died by the GSC.
In standard SOLC protocol the BOF signals the start of
a frame and is limited to 8 bits in length. Since there is
no preamble in SOLC the BOF is considered an entire
separate field and marks the beginning of the frame.
The BOF also serves as the clock synchronization
mechanism and the reference point for determining the
position of the address and control fields.
AOORESS - The address field is used to identify which
stations the message is intended for. Each secondary
station must have a unique address. The primary station must then be made aware of which addresses are
assigned to each station. The address length is specified
as 8-bits in standard SOLC protocols but it is expandable to 16-bits in the C152. User software can further
expand the number of address bits, but the automatic
address recognition feature works on a maximum of 16bits.

CONTROL - The control field is used for initialization
of the system, identifying the sequence of a frame, to
identify if the message is complete, to tell secondary
stations if a response is expected, and acknowledgement
of previously sent frames. The user software is responsible for insertion of the control field as the .GSC hardware has no provisions for the management· of this
field. The interpretation and formation of the control
field must also be handled by user software. The information following the control field is typically used for
information transfer, error reporting, and various other
functions. These functions are accomplished by the format of the control field. There are three formats available. The types of formats are Informational, Supervisory, or Unnumbered. Figure 3.7 shows the various format types and how to identify them.
Since the user software is responsible for the implementation of the control field, what follows is a simple explanation on the control field and its functions. For a
complete understanding and proper implementation of
SOLC, the user should refer to the IBM document,
GA27-3093-2, IBM Synchronous Oata Link Control
General Information. Within that document, is another
list of IBM documents which go into detail on the
SOLC protocol and its use.
The control field is eight bits wide and the format is
determined by bits 0 and 1. If bit 0 is a zero, then the
frame is an informational frame. If bit 0 is a one and bit
1 a zero, then it is a supervisory frame, and if bit 0 is a
one and bit I a one then the frame is an unnumbered
frame.
In an informational frame bits 3,2,1 contain the sequence count of the frame being sent.
Bit 4 is the P IF (Poll/Final) bit. If bit 4 equals 1 and
originates from the primary, then the secondary station
is expected to initiate a transmission. If bit 4 equals 1
and originates from a secondary station, then the frame
is t~e final frame in a transmission.

In SOLC the addresses are normally unique for each
station. However, there are several classes of messages
that are intended for more than one station. These messages are called broadcast and group addressed frames.
An address consisting of allIs will always be automatically received by the GSC, this is defined as the broadcast address in SOLC. A group address is an address
that is common to more than one station. The GSC
provides address masking bits to provide the capability
of receiving group addresses.
If desired, the user software can mask off all the bits of

the address. This type of masking puts the GSC in a·
promiscuous mode so that all addresses are received.

8-25

Bits 7,6,5 contain the sequence count a station expects·
on the next transmission to it. The sequence count can
vary from OOOB to 11 lB. The count then starts over
again at OOOB after the value IliB is incremented. The
acknowledgement is recognized by the receiving station
when it decodes bits 7,6,5 of an incoming frame. The
station sending the transmission is acknowledging the
frames received up to the count represented in bits 7,6,5
(sequence count-I). With this method, up to seven sequential frames may be transmitted prior to an acknowledgement being received. If eight frames were allowed to pass before an acknowledgement, the sequence
count would roll over and this would negate the purpose of the sequence numbers.

HARDWARE DESCRIPTION OF THE 83C152

BIT
POSITIONS-

7

65
.

4

o

321

SENDING
SEQUENCE

RE¢'EPTjlON
SEQUENCE

270427-15

RECEPTION SEQUENCE - The sequence expected in (the SENDING SEQUENCE portion of the control byte
in the next received frame. This also confirms correct reception of up to seven frames prior to the sequence given.
POLL/FINAL - Identifies the frame as being a polling request from the master station or the last in a series of
frames from the master or secondary;
SENDING SEQUENCE- Identifies the sequence of the frame being transmitted.
o - If bit 0 = 0 the frame. is identified as a informational format type.

INFORMATION FORMAT

-----------------~----------------------------~--------M
POSITIONS-

7

6

5

4

3

o

.2

~R-E~C-E-P-T~:IO-N-,-po-LL-/~~--~--~~

SEQ UEN CE

FINAL

270427-16

RECEPTION SEQUENCE - Expected sequenceofframe for next reception.
POLL/FINAL - Identifies frame as being a polling request from the' master station or the last in a series of
frames from the master or secondary.
.
MODE - Identifies whether receiver is ready (00), not ready (10) or a frame was rejected (Oi). The rejected frame
is identified by the reception sequence.
.
0,1 - If bits I,D = 0,1 the frame is identified as a supervisory format type.

SUPERVISORY FORMAT

-------------~--------------------------------~-~------. M
7
6
5
432
1 0
POSITIONS-.--_ _·..,.--_ _,--_ _- - - . . - - - - , - -___- - - - . . . - -.....

,I.

.

COMMAND/ IpOLL/ICOMMAND/1
R~sPoNsE ViNAl·1 RESPONSE I

1 1
I

I

II

270427-17

COMMAND/RESPONSE - Identifies the type of command. or response.
POLL/FINAL - Identifies frame as being a polling request from the master station or the last in a series of
frames from the master or secondary.
1,1 - If bits I,D == 1,1 the 'frame is identified as an unnumbered format type.

NONSEQU'ENCED FO'RMAT
,

Figure 3.7. SDLC Control Field

8-26

270427-18

inter

HARDWARE DESCRIPTION OF THE 83C152

Following the informational control field comes the information to be transferred.

When the mode is 10, the sending station is indicating
that its receiver is not ready to accept frames.

In the supervisory format (bits 1,0 = 0,1) bits 3,2 determine which mode is being used.

Mode 11 is an illegal mode in SDLe protocol.

When the mode is 00 it indicates that the receive line of
the station that sent the supervisory frame is enabled
and ready to accept frames.

Bits 7,6,5 represent the value of the sequence the station expects when the next transfer occurs for that station. There is no information following the control field
when the supervisory format is used.

When the mode is 01, it indicates that previously a
received frame was rejected. The value in the receive
count identifies which frame(s) need to be retransmitted.

In the unnumbered format (bits 1,0 = 1,1) bits 7, 6, 5,
3, 2 (notice bit 4 is missing) indicate commands from
the primary to secondary stations or requests of secondary stations to the pritnary.

The standard commands are:
BITS 7 6 5 3 2 Command
0 0 0 0 0 Unnumbered Information (UI)
0 0 0 0 1 Set initialization mode (SIM)
0 1 0 0 0 Disconnect (DISC)
0 0 1 0 0 Response optional (UP)
1 1 0 0 1 Function descriptor in
information field (CFGR)
1 1 Identification in information field. (XID)
0
1
0 0 Test pattern in information field. (TEST)

The standard responses are:
BITS 7 6 5 3 2 Command
0 0 0 0 0 Unnumbered information (UI)
0 0 0 0 1 Request for initialization (RIM)
0 0 0 1 1 Station in disconnected mode (OM)
1 0 0 0 1 Invalid frame received (FRMR)
0 1 1 0 0 Unnumbered acknowledgement (UA)
1 1 1 1 1 Signal loss of input (BCN)
1 1 0 0 1 Function descriptor in information field (CFGR)
0 1 0 0 0 Station wants to disconnect (RD)
1 0 1 1 1 Identification in information field (XID)
1 1 1 0 0 Test pattern in information field (TEST)

8-27

HARDWARE 'DESCRIPTION OF THE 83C152

rithms, a 16-bit and a 32-bit. The 32-bit algorithm is
normally used in. CSMAlCD applications and is described in section 3.2.2. In most SDLC applications a
16-bit CRC is used and the hardware configuration that
supports 16-bit CRC is shown in Figure 3.8; The generating polynomial that the CRC generator uses with the
16-bit CRC is:

In an unnumbered frame, information of variable
length may follow the control field if UI is, used, or
information of fixed length may follow if FRMR is
used.
As stated earlier, the user software is responsible for the

proper management of the control field. This portion of
the frame is passed to or from the GSCFIFOs as basic
informational type data.

G(X)

=

X"16

+ X"12 + X"5 +

1

The way the CRC operates is that as a bit is received it
is XOR'd with bit 15 of the current CRC and placed in
temporary storage. The result of XOR'ing bit 15 with
the received bit is then XOR'dwith bit 4 and bit 11 as
the CRC is shifted one position to the right. The bit in
temporary storage is shifted into position O.

INFO - This is the information field and contains ,the
data that,one device on the 'link' wishes to transmit to
another device. It can be of any length the user wishes,
but must be a multiple of 8 bits. It is possible that some
frames may contain no information field. The information field is identified to the receiving stations by the
preceding control field and the following CRC. The
GSC determines where the last of the information field
is by passing the bits through the CRC generator.
When the last bit or BOF is received the bits that remain constitute the CRC.

The required CRC length for SDLC is' 16 bits. The
CRC is automatically stripped from the frame and not
passed on: to the CPU. The last 16 bits ,are then run
though the CRC generator to insure that the correct
remainder is left. The remainder that is checked for is
001110100001111B (lDOF Hex). If there is a mismatch, an error is generated. The user software has the
optiqn of enabling this interrupt so the CPU is notified.

CRC - The Cyclic Redundancy Check (CRC) is an error checking sequence commonly used in serial communications. The C152 offers two types of CRC algo-

270427-19

Figure3_8_16-BitCRC

8-28

inter

HARDWARE DESCRIPTION OF THE 83C152

EOF - The End Of Frame (EOF) indicates when the
transmission is complete. The EOF is identified by the
end flag. An end flag consists of the bit pattern
01111110. The EOF can also serve as the BOF for the
next frame.

3.3.5 SENDING ABORT CHARACTER
An abort character is one of the exceptions to the rule
that disallows more than 5 consecutive Is. The abort
character consists of any occurrence of seven or more
consecutive ones. The simplest way for the CI52 to
send an abort character is to clear the TEN bit. This
causes the output to be disabled which, in turn, forces it
to a constant high state. The delay necessary to insure
that the link is high for seven bit times, is a task that
needs to be handled by user software. Other methods of
sending an abort character are using the IFS register or
using the Raw Transmit mode. Using IFS still entails
clearing the TEN bit, but TEN can be immediately reenabled. The next message will not begin until the IFS
expires. The IFS begins timing out as soon as DEN
goes high which identifies the end of transmission. This
also requires that IFS contain a value equal to or greater than 8. This method may have the undesirable effect
that DEN goes high and disables the external drivers.
The other alternative is to switch to Raw Transmit
mode. Then, writing OFFH to TFIFO would generate a
high output for 8 bit times. This method would leave
DEN active during the transmission of the abort character.

3.3.3 DATA ENCODING
The transmission of data in SDLC mode is done via
NRZI encoding as shown in Figure 3.9. NRZI encoding transmits data by changing the state of the output
whenever a 0 is being transmitted. Whenever a I is
transmitted the state of the output remains the same as
the previous bit and remains valid for the entire bit
time. When SDLC mode is selected it automatically
enables the NRZI encoding on the transmit line and
NRZI decoding on the receive line.
3.3.4 BIT STUFFING/STRIPPING
In SDLC mode one of the primary rules of the protocol
is that in any normal data transmission, there will never
be an occurrence of more than 5, consecutive Is. The
GSC takes care of this housekeeping chore by automatically inserting a 0 after every occurrence of 5 consecutive Is and the receiver automatically removes a zero
after receiving 5 consecutive Is. All the necessary steps
required for implementing bit stuffing and stripping are
incorporated into the GSC hardware. This makes the
operation transparent to the user. About the only time
this operation becomes apparent to the user, is if the
actual data on the transmission medium is being monitored by a device that 'is not aware of the automatic
insertion of Os. The bit stuffing/stripping guarantees
that there will be at least one transition every 6 bit
times while the line is active.

o

BIT

When the receiver detects seven or more consecutive Is
and data has been loaded into the receive FIFO, the
RCABT flag is set in RSTAT and that frame is ignored. If no data has been loaded into the receive
FIFO, there are no abort flags set and that fraine is just
ignored. A retransmitted frame may immediately folIowan abort character, provided the proper flags are
used.

,

,

o

o

'

-TIME~

270427-20

Figure 3.9. NRZI Encoding

8-29

inter

HARDWARE DESCRIPTION OF THE 83C152

passing the message to the downstream· station. This
delay is necessary so that a station can decode its own
address before the message is passed on. The various
networks are shown in Figure 3.10.

3.3.6 LINE IDLE
If 15 or more consecutive Is are detected by the receiver the Line Idle bit (LNI) in TSTAT is set. The seven
Is from the abort character may be included when sensing for a line idle condition. The same methods used for
sending the Abort character can be used for creating
the Idle condition. However, the values would need to
be changed to reflect 15 bit times, instead of seven bit
times.

3.3.9 HDLC/SDLC COMPARISON
HDLC (High level Data Link Control) is a standard
adopted by the International Standards Organization
(ISO). The HDLC standard is defined in theISO document #ISO 6159 - HDLC unbalanced classes ofprocedures. IBM developed the SDLC protocol as a subset of
HDLC. SDLC conforms to HDLC protocol requirements, but is more restrictive. SDLC contains a more
precise definition on the modes of operation.

3.3.7 ACKNOWLEDGEMENT
Acknowledgment in SDLC is an implied acknowledge
/ and is contained in the controi field. Part of the control
frame is the sequence number .of the next expected
frame. This sequence number is caUed the Receive
Count. In transmitting the Receive Count, the receiver
is in fact acknowledging aU the previous frames prior to
the count that was transmitted. This allows for the
transmission of up to seven frames before an acknowledge is required back to the transmitter. The limitation
of seven frames is necessary because the Receive Count
in the control field is limited to three binary diiits. This
means that if an eighth transmission occurred this
would cause the next Receive Count to repeat the first
count that still is waiting for an acknowledge. This
would defeat the purpose of the acknowledgement. The
processing and general maintenance of the sequence
cOunt must be done by the user software. The Hardware Based Acknowledge option that is provided in the
Cl52 is not compatible with standard SDLC protocol.

Some of the major differences between SDLC and
HDLCare:
SDLC
HDLC
Unbalanced (primary/
secondary)
Modulo 8 (no extensions
allowed, up to 7 outstanding frames before
acknowledge is required)
8-bit addressing only
Byte aligned data

Balanced
(peer to peer)
Modulo 128 (up to 127
outstanding frames
before acknowledge
is required)
Extended addressing
Variable size of data

The C152 does not support HDLC implementation requiring data alignment other than byte alignment. The
user wiU find that many of the protocol parameters are
programmable in the Cl52 which allows easy implementation of proprietary or standard HDLC network.
User software needs to implement the control field
functions.

3.3.8 PRIMARY/SECONDARY STATIONS
All SDLC networks are based upon a primary/secondary station relationship. There can be only one primary
station in a network and aU the other stations are considered secondary. All communication is between the
primary and secondary station. Secondary station to
secondary station direct communication is prohibited.

3.4 User Defined Protocols
The explanation on the implementation of user defined
protocols would go beyond the scope of this manual,
but examining Table 3.1 should give the reader a consolidated list of niost of the possibilities. In this manual,
any deviation from the documents that cover the implementation of CSMA/CD or SDLC are considered user
defmed protocols. Examples of this would be the use of
SDLC with the 32-bit CRC selected or CSMA/CD
with hardware based acknowledge.

If there is a need for secundary to secondary COfliiliuni-

cation, the user software will have to make aUowances
for the master to act as an intermediary. Secondary
stations are aUowed use of the serial line only when the
master permits them. This is done by the master polling
the secondary stations to see if they have a need to
access the serial line: This should prevent any collisions
from occurring, provided each secondary station has its
own unique address. This arrangement also partiaUy
determines the types of networks supported. Normal
SDLC networks consist of point-to-point, multi·drop,
or ring configurations and the Cl52 supports aU of
these. However, some SDLC processors support an automatic one bit delay at each node that is not supported
by the C152. In a "Loop Mode" configuration, is is
necessary that the transmission be delayed from the reception of the frames from the upstream station before

3.5 Using the GSC
3.5.1 LINE DISCIPLINE
Line discipline is how the management of the transfer
of data over the physical medium is controlled. Two
types of line discipline will be discussed in this section:
full duplex and half duplex.
8-30

HARDWARE DESCRIPTION OF THE 83C152

Point-to-Point Network

270427-21

Multi-Drop Network

270427-22

Ring Network

270427-23

Figure 3.10. SOLe Networks

8-31

inter

HARDWARE DESCRIPTION OF THE 83C152

Full duplex is the simultaneous transmission and reception of data. Full duplex uses anywhere from two to
four wires. At least one wire is needed for transmission
and one wire for reception. Usually there will also be a
ground reference on each signal if the distance from
station to station is relatively long. Full-duplex operation in the C152 requires that both the receive and the
transmit portion ,of the GSC are functioning at the
same time. Since both the transmitter and receiver are
operating, two CRC generators are also needed. The
C152 handles this problem by having one 32-bit CRC
generator and one 16-bit CRC generator. When supporting full-duplex operation, the 32-bit CRC generator
is modified to work as a 16-bit CRC generator. Whenever the 16-bit CRC is selected, the GSC automatically
enters the full duplex mode. Half duplex with a 16-bit
CRC is discussed in the following paragraph.

Some of the general areas that will impact the overall
scheme on how to incorporate future changes to the
system are:
1) Communication of the change to all the stations or
the primary station.
2) Maximum distance for communication. This will affect the drivers used and the slot time.
3) More stations may be on the line at one time. This
may impact the interframe space or the collision resolution used.

Half duplex is the alternate transmission and reception
of data over a single cornmon wire. Only one or two
wires are needed in half-duplex systems. One wire is
needed for the signal and if the distance to be covered is
long there will also. be a wire for the ground reference.
In half-duplex mode, only the receiver or- transmitter
can operate at one time. When the receiver or transmitter operates is determined by user software, but typically the receiver will always be enabled unless the GSC is
transmitting. Whenever half duplex is being used the
software must insure that only the receiver or transmit- .
ter is enabled at any given time. This is particularly
important when using SDLC, so that the receiver will
not recognize its own address when the transmitter is
operating. Half-duplex operation in the C152 is supported with either 16-bit or 32-bit CRCs. Whenever a
32-bit CRC is selected, only half-duplex operation can
be supported by the GSC. It is possible to simulate fullduplex operation with a 32-bit CRC, but this would
require that the CRC be performed with software. CaIculating the CRC with the CPU would greatly reduce
the data rates that could be used with the GSC. Whenever a 16-bit CRC is selected, full-duplex operation is
automatically chosen and the GSC must be reconfig-

ured if half-duplex operation is preferred.

4) If using CSMAlCD without deterministic resolution, any increase in network size will have a negative
impact on the average throughput of the network and
lower the efficiency. The user will have to give careful
consideration when deciding how large a system can
ultimately be and still maintain adequate performance.
3.5.3 DMA SERVICING OF GSC CHANNELS

There are two sources that can be used to control the
GSC. The first is CPU control and the second is DMA
control.
CPU control is used when user software takes care of
the tasks such as: loading the TFIFO, reading the RFIFO, checking the status flags, and general tracking of
the transmission process. As the number of tasks grow
and higher data transfer rates are used, the overhead
required by the CPU becomes the dominant consumption of time. Eventually, a point is reached where the
CPU is spending 100% of its time responding to the
needs of the GSC. An alternative is to have the DMA
channels control the GSC.
A detailed explanation on the general use of the DMA
channels is covered in Section 4. In this section only
those details required for the use of the DMA channels
with the GSC will be covered.
The DMA channels can be configured by user software
so that the GSC data transfers are serviced by the
DMA controller. Since there are two DMA channels,
one channel can be used to service the receiver, and one
channel can. be used to service the transmitter. In using
the DMA channels, the CPU is relieved of much of the
time required to do the basic servicing ofthe GSC buffers. The types of servicing that the DMA channels can
provide are: loading of the transmit FIFO, removing.
data from the receive FIFO, notification of the CPU
when the transmission or reception has ended, and response to certain error conditions. When using the

3.5.2 PLANNING FOR NETWORK CHANGES
AND EXPANSIONS

A complete explanation on how to plan for network
expansion will not be covered in this manual as there
are far too many possibilities that would need to be
discussed. But there are several areas that will have
major impact when allowing for changes in the system.
In cases where there will never be any changes allowed,
expansion plans become a mute issue. However, it is
strongly suggested that there always be some allowance
for future modifications.

8-32

inter

HARDWARE DESCRIPTION OF THE 83C152

that will be received, up to 64K. If not using the Done
flag, then GSC servicing would be driven by the receive
Done (RDN) flag and/or interrupt. RDN is set when
the EOF is detected. When using the RDN flag, RFNE
should also be checked to insure that all the data has
been emptied out of the receive FIFO.

DMA channels the source or destination of the data
intended for serial transmission can be internal data
memory, external data memory, or any of the SFRs.
The only tasks required after initialization of the DMA
and GSC registers are enabling the proper interrupts
and informing the DMA controller when to start. After
the DMA channels are started all that is required of the
CPU is to respond to error conditions or wait until the
end of transmission.

The byte count register is used for all transmissions and
this means that all packets going out will have to be of
the same length or the length of the packet to be sent
will have to be known prior to the start of transmission.
When using the DMA channels to service the GSC
transmitter, there is no practical way to disable the
Done flag. This is because the transmit done flag
(TDN) is set when the transmit FIFO is empty and the
last message bit has been transmitted. But, when using
the DMA channel to service the transmitter, loads to
the TFIFO continue to occur until the byte count
reaches O. This makes it impossible to use TDN as a
flag to stop the DMA transfers to TFIFO. It is possible
to examine some other registers or conditions, such as
the current byte count, to determine when to stop the
DMA transfers to TFIFO, but this is not recommended
as a way to service the DMA and GSC when transmitting because frequent reading of the DMA registers will
cause the effective DMA transfer rate to slow down.

Initialization of the DMA channels requires setting up
the control, source, and destination address registers.
On the DMA channel servicing the receiver, the control register needs to be loaded as follows: DCONn.2 =
0, this sets the transfer mode so that response is to GSC
interrupts and put the DMA control in alternate cycle
mode; DCONn.3 = 1, this enables the demand mode;
DCONnA = 0, this clears the automatic increment
option for the source address; and DCONn.5 = I, this
defines the source as SFR: The DMA channel servicing
the receiver also needs its source address register to
contain the address of RFIFO (SARHN = XXH,
SARLN = OF4H). On the DMA channel servicing the
transmitter, the control register needs to be loaded as
follows: DCONn.2 = 0; DCONn.3 = I; DCONn.6 =
0, this clears the automatic increment option for the
destination address; and DCONn.7 = I, this sets the
destination as SFR. The DMA channel serving the
transmitter also requires that its destination address
register contains the address of TFIFO (DARHN =
XXH, DARLN = 85H). Assuming that DCONO
would be serving the receiver and DCONI the transmitter, DCONO would be loaded with XXIOIOXOB
and DCONI would be loaded with IOXXIOXOB. The
contents of SARRO and DARHI do not have any impact when using internal SFRs as the source or destination.

When using the DMA channels, initialization of the
GSC would be exactly the same as normal except that
TSTAT.O = I (DMA), this informs the GSC that the
DMA channels are going to he lIsed to service the GSC.
Although only TSTAT is written to, hoth the receiver
and transmitter use this sallie DMA hit.

When using the DMA channels to service the GSC, the
byte count registers will also need to be initialized.
The Done flag for the DMA channel servicing the receiver should be used if fixed packet lengths only are
being transmitted or to insure that memory is not overwritten by long received data packets. Overwriting of
data can occur when using a smaller buffer than the.
packet size. In these cases the servicing of the DMA
and/or GSC would be in response to the DMA Done
flag when the byte ~ount reaches zero.
In some cases the buffer size is not the limiting factor
and the packet lengths will be unknown. In these cases
it would be desirable to eliminate the function of the
Done flag. To effectively disable the Done flag for the
DMA channel servicing the receiver, the byte count
should be set to some number larger than any packet

8-33

The interrupts EGSTE (IEN1.5), GSC transmit error;
EGSTV (lEN 1.3), GSC transmit valid; EGSRE
(IENl.l), GSC receive error; and EGSRV (IENl.O),
GSC receive valid; need to be enabled. The DMA interrupts are normally not used when servicing the GSC
with the DMA channels. To ensure that the DMA interrupts are not responded to is a function of the user
software and should be checked by the software to
make sure they are not enabled. Priority for these interrupts can also be set at this time. Whether to use high
or low priority needs to be decided by the user. When
responding'to the GSC interrupts, if a buffer is being
used to store the GSC information, then the DMA registers used for the buffer will probably need updating.
After this initialization, all that needs to be done when
the GSC is actually going to be used is: load the byte
count, set-up the source addresses for the DMA channei servicing the transmitter, set-up the destination addresses for the DMA channel servicing the receiver,
and start the DMA transfer. The GSC enable bits
should be set first and then the GO bits for the DMA.
This initiates the data transfers.

intJ

HARDWARE DESCRIPTION OF THE 83C152

This simplifies the maintenance of the GSC and can
make the implementation of an external buffer for
packetized information automatic.

Initialization of the system can be broken down into
several steps. First, are the assumptions of each network station.

An external buffer can be used as the source of data for
transmission, or the destination of data from the receiver. In this arrangement, the message size is limited to
the RAM size or 64K, whichever is smaller. By using
an external buffer, the data can be accessed by other
devices which may want access to the serial data. The
amount of time required for the external data moves
will also decrease. Under CPU control, a "MOVX"
command would take 24 oscillator periods to complete.
Under DMA control, external to internal, or internal to
external, data moves take only 12 oscillator periods.

The first assumption is that the type of data encoding
to be used is predetermined for the system and that
each station will adhere to the same basic rules defining
that encoding. The second assumption is that the basic
protocol and line discipline is predetermined and
known. This means that all stations.are using CSMAI
CD or SDLC or whatever, and that all stations are
either full or half duplex. The third assumption is that
the baud rate is preset for the whole system. Although
the baud rate could probably be determined by the microprocessor just by monitoring the link, it will make it
much simpler if the baud rate is known in advance.

3.5.4 BAUD RATE

One of the first things that will be required during system initialization is the assignment of unique addresses
for each station. In a two-station only environment this
is not necessary and can be ignored. However, keep in
mind, that all systems should be constructed for easy
future expansions. Therefore, even in only a two station
system, addresses should be assigned. There are three
basic ways in which addresses can be assigned. The
first, and most common is preassigned addresses that
are loaded into the station by the user. This could be
done with a DIP-switch, through a keyboard. The second method of assigning addresses is to randomly assign an address and, then check for its uniqueness
throughout the system, and the third method is to
make an inquiry to the system for the assignment of a
unique address. Once the method of address assignment
is determined, the method should become part of the
specifications for the system to which all additions will
have to adhere. This, then, is the final assumption.

The GSC baud rate is determined by the contents of the
SFR, BAUD, or the external clock. The formula used
to determine the baud rate when using the internal
clock is:
(fosc)/«BAUD+ 1)*8)
For example if a 12 MHz oscillator is used the baud
rate can vary from:
12,000,000/«0-1- 1)'8)

=

1.5 MBPS

to:
12.000.000/«255+1)'8) ='5.859 KBPS

There are certain requirements that the external clock
will need to meet. These requirements are specified in
the data sheet. For a description of the use of the GSC
with external clock please read Section 3.5.11.

The negotiation process may not be clear for some
readers. The following two procedures are given as a'
guideline for dynamic address assignment.

3.5.5 INITIALIZATION

In the first procedure, a station assumes a random address and then checks for its uniqueness throughout the
system. As a station is initialized into the system it
sends out a message containing its assumed address.
The format of the message should be such that any
station decoding the address recognizes it as a request
for initialization. If that address is already used, the
receiving station returns a message, with its own address stating that the address in question is already taken. The initializing station then picks another address.
When the initializing station sends its inquiry for the
address check, a timer is also started. If the timer expires before the iilquiry is responded to, then that station assumes the address chosen is okay.

Initialization can be broken down into two major' components, i) iniiiaiizaiion of the component so that its
serial port is capable of proper communication; and 2)
initialization of the system or a station so that intelligible communication can take place.
Most of the initialization of the component has already
been discussed in the previous sections. Those items not
covered are the parameters required for the component
to effectively communicate with other components.
These types of issues are common to both system and
component initialization and will be covered in the following text.

8-34

inter

HARDWARE DESCRIPTION OF THE 83C152

In the second procedure, an initializing station asks for
an address assignment from the system. This requires
that some station on the link take care of the task of
maintaining a record of which addresses are used. This
station will be called station-I. When the initializing
station, called station-2, gets on the link, it sends out a
message with a broadcast address. The format of the
message should be such that all other stations on the
link recognize it as a request for address assignment.
Part of the message from station-2 is a random number
generated by the station requesting the address. Station-2 then examines all received messages for this random number. The random number could be the address
of the received message or could be within the information section of a broadcast frame. All the stations, except station-I, on the link should ignore the initialization request. Station-I, upon receiving the initialization
request, assigns an address and returns it to station-2.
Station-l will be required to format the message in such
a manner so that all stations on the link recognize it as
a response to initialization. This means that all stations
except station-2 ignore the return message.

In Raw Receive, the transmitter should be externally
connected to the receiver. To do this a port pin should
be used to enable an external device to connect the two
pins together. In Raw Receive mode the receiver acts as
normal except that all bytes following the BOF are
loaded into the receive FIFO, including the CRC. Also
address recognition is not active but needs to be performed in software. IfSDLC is selected as the protocol,
zero-bit deletion is still enabled. The transmitter still
operates as normal and in this mode most of the transmitter functions and an external transceiver can be tested. This is also the only way that the CRC can be read
by the CPU, but the CRC error bit will not be set.
3.5.7 EXTERNAL DRIVER INTERFACE

A signal is provided from the CI52 to enable transmitter drivers for the serial link. This is provided for systems that require more than what the GSC ports are
capable of delivering. The voltage and currents that the
GSC is capable of providing are the saine levels as those
for normal port operation. The signal used to enable the
external drivers is DEN. No similar signal is needed for
the receiver.

3.5.6 TEST MODES

There are two test modes associated with the GSC that
are made available to the user. The test modes are
named Raw Receive and Raw Transmit. The test
modes are selected by the proper setting of the two
mode bits in GMOD (MO = GMOD.5, MI =
GMOD.6). If Ml,MO = 0,1 then Raw Transmit is selected. If MI,MO = 1,0 then Raw Receive is enabled.

3.5.8 JITTER (RECEIVE)

Datajitter is the difference between the actual transmitted waveform and the exact calculated value(s). In
NRZI, data jitter would be how much the actual waveform exceeds or falls short of one calculated bit time. A
bit time equals l/baud rate. If using Manchester encoding, there can be two transitions during one bit time as
shown in Figure 3.11. This causes a second parameter
to be considered when trying to figure out the complete
data jitter aniount. This other parameter is the half-bit
jitter. The half-bit jitter is comprised of the difference in
time that the half-bit transition actually occurs and the
calculated value. Jitter is important because if the transition occurs too soon it is considered noise, and if the
transition occurs too late, then either the bit is missed
or a collision is assumed.

In Raw Transmit, the transmit output is internally connected to the Receiver input. This is intended to be
used as a local loop-back test mode, so that all data
written to the transmitter will be returned by the receiver. Raw Transmit can also be used to transmit user
data. If Raw Transmit is used in this way the data is
emitted with no preamble, flag, address, CRC, and no
bit insertion. The data is still encoded with whatever
format is selected, Manchester with CSMA/CD, NRZI
with SDLC or as NRZ if external clocks are used. The
receiver still operates as normal and in this mode most
of the receive functions can be tested.

8-35

inter

HARDWARE DESCRIPTION OFTHE 83C152

LOGICAL
VALUE

o

o

o

MANCHESTER
ENCODING
'I

'f

f

(8 X BAUD
RECEIV
SAMPLING
RATE
RECEIVED
DATA

"1" BIT TIME

"1" BIT TIME

a'

"0" BIT TIME

.,

I
I

I
I

I

.. -

I
I
I

I
I
I

....

I
I
I

I
I
I

I

'1

RECEIVED
DATA

"1" BIT TIME

...

I
I

.. -

.1

1'1

I

I
I
I
I

I

I

I
, I
I
I

I

Figure 3.11. Jitter

8-36

I

I

.----I
I.
I

I
I

---- ..
270427-24

inter

HARDWARE DESCRIPTION OF THE 83C152

I

BIT
I
:~ TIME ---..:

I

I

a

a

a

L

NRZ

270427-25

Figure 3.12. Transmit Waveforms

has to be set to a 1. To select external clocking for'the
receiver, XRCLK (PCON.3) has to be set to a 1. Setting both bits to I forces external clocking for the receiver and transmitter.

3.5.9 Transmit Waveforms

The GSC is capable of three types of data encoding,
Manchester, NRZI, and NRZ. Figure 3.12 shows examples of all three types of data encoding.

The external transmit clock is applied to pin 4 (TXC),
P1.3. The external receive clock is applied to pin 5
(RXC), PI.4. To enable the external clock function on
the port pin, that pin has to be set to a 1 in the appropriate SFR, PI.

3.5.10 Receiver Clock Recovery

The receiver is always monitored at eight times the
baud rate frequency, except when an external clock is
used. When using an external clock the receiver is loaded during the clock cycle.

Whenever the external clock option is used, the format
of the transmitted and received data is restricted to
NRZ encoding and the protocol is restricted to SOLC;
With external clock, the bit stuffing/stripping is still
active with SOLC pr~.tocoI.

In CSMA/CO mode the receiver synchronizes to the
transmitted data during the preamble. If a pulse is detected as being too short it is assumed to be noise or a
collision. If a pulse is too long it is assumed to be, a
collision or an idle condition.

3.6 GSC Operation

In SOLC the synchronization takes place during the
BOF flag. In addition, pulses less than four sample periods are ignored, and assumed to be noise. This sets a
lower limit on the pulse size of received zeros.

3.6.1 Determining Line Discipline

In normal operation the GSC uses full or half duplex
operation. When using a 32-bit CRC (GMOO.3 = I),
operation can only be half duplex. If using a 16-bit
CRC (GMOO.3 = 0), full duplex is selected by default. When using a 16-bit CRC the receiver can be
turned off while transmitting (RSTAT.I = 0), and the
transmitter can be turned off during reception
(TSTAT.I = 0). This simulates half-duplex operation
when using a 16-bit CRC.

In CSMA/CO the preamble consists of alternating Is
and Os. Consequently, the preamble looks like the
waveform in Figure 3.13A and 3.13B.
3.5.11 External Clocking

To select external clocking, the user is given three
choices. External clocking.can be used with the transmitter, with the receiver, or with both. To select external clocking for the tran~mitter, XTCLK (GMOO.7)

Normally, HOLC uses a 16-bit CRC, so half duplex is
determined by turning off the receiver or transmitter.
This is so that the receiver will not detect its own ad-

8-37

inter

HARDWARE DESCRIPTION OF THE 83C152

CSMAICO Clock Recovery

o,

1 , 0

1 , 0

1 ,0

,1

0

0',

0

IDEAL WAVEFORM

.,
ax

I

I

I

I

I

,
I

I

I

I

I

I

I

I

I

I

I

I

SAMPLING RATE 111111111111111111111111111111111111111111111111111111\1111111111111111.11111111,11111I11j11l1l11l11l11l1Ul1l111j111l1l1l11l11l1l1l11111111l1111

, ACTUAL WAVEFORM

RECOVERED BIT
STREAM CLOCK

270427-26

Figure 3.13A. Clock Recovery

SOLC Clock Recoyery

o

0: 0:

o

000

IDEAL WAVEFORM

,
ax SAMPLING RATE

I

I

I

I

I

I

I

I

I

I

I

I

I

,
I

I

I

I

1111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111

ACTUAL WAVEFORM

RECOVERED BIT
STREAM CLOCK

270427-27

Figure 3.138. Clock Recovery

8-38

infef

HARDWARE DESCRIPTION OF THE 83C152

dress as transmission takes place. This also needs to be
done when using CSMA/CD with a 16-bit CRC for the
same reason.

multi-cast address. The user software can enable the
interrupt for RDN to determine when a frame is completed.
In DMA mode the interrupts are generated by the internal "transmit/receive done" (TDN,RDN) conditions. When the CPU responds to TDN or RDN,
checks are performed to see if the transmit underrun
error has occurred. The underrun condition is only
checked when using the DMA channels.

3.6.2 CPU/DMA CONTROL OF THE GSC

The data for transmission or reception can be 'handled
by either the CPU (TSTAT.O = 0) or DMA controller
(TSTAT.O = I). This allows the user two sets of flags
to control the FIFO. Associated with these flags are
interrupts, which may be enabled by the user software.
Either one or both sets of flags may be used at the same
time.

Upon power up the CPU mode is initialized. General
DMA control is covered in Section 4.0. DMA control
of the GSC is covered in Section 3.5.4. IfDMA is to be
used for serving the GSC, it must be configured into the
serial channel demand mode and the DMA bit in
TSTAT has to be set.

In CPU control mode the flags (RFNE,TFNF) are generated by the condition of the receive or transmit FIFO's. After loading a byte into the transmit FIFO,
there is a one machine cycle latency until the TFNF
flag is updated. Because of this latency, the status of
TFNF should not be checked immediately following
the instruction to load the transmit FIFO. If using the
interrupts to service the transmit FIFO,the one machine cycle of latency must be considered if the TFNF
flag is checked prior to leaving the subroutine.

3.6.3 COLLISIONS AND BACK OFF

The actions that are taken by the GSC if a collision
occurs while transmitting depend on where the collision occurs. If a collision occurs in CSMA/CD mode
following the preamble and BOF flag, the TCDT flag is
set and the transmit hardware completes a jam. Whcn
this type of collision occurs, there will be no automatic
retry at transmission. After the jam, control is returncd
to the CPU and user software must then initiate whatever actions are necessary for a proper recovery. The
possibility that data might have been loaded into or
from the GSC deserves special consideration. If these
fragments of a message have been passed on to other
devices, user software may have to perform some extensive error handling or notification. Before starting a
new message, the transmit and receive FIFOs will need
to be cleared. IfDMA servicing is being used the pointers must also be reinitialized. It should be noted that a
collision should never occur after the BOF flag in a well
designed system, since the system slot time will likely
be . less than the preamble length. The occurrence of
such a situation is normally due to a station on the link
that is not adhering to proper CSMA/CD protocol or
is not using the same timings as the rest of the network.

When using the CPU for control, transmission normally is initiated by setting the TEN bit (TSTAT.l) and
then writing to TFIFO. TEN must be set before loading the transmit FIFO, as setting TEN "clears the transmit FIFO. TCDCNT should also be checked by user
software and cleared if a collision occurred on a prior
transmission.
To enable the receiver, GREN (RSTAT.l) is set. After
GREN is set, the GSC begins to look for a valid BOF.
After detecting a valid BOF the GSC attempts to
match the received address byte(s) against the address
match registers. When a match occurs the frame is
loaded into the GSC. Due to the CRC strip hardware,
there is a 40 or 24 bit time delay following the BOF
until the first data byte is loaded into RFIFO if the 32
or 16 bit CRC is chosen. If the end of frame is detected
before data is loaded into the receive FIFO, the receiver
ignores that frame.
If the receiver detects a collision during reception in

CSMA/CD mode and if any bytes have been loaded
into the receive FIFO, the RCABT flag is set. The GSC
hardware then halts reception and resets GREN. The
user software needs to filter any collision fragment data
which may have been received. If the collision occurred
, prior to the data being loaded into RFIFO the CPU is
not notified and the receiver is left enabled. At the end
of a reception the RDN bit is set and GREN is cleared.
In HABEN mode this causes an acknowledgement to
be transmitted if the frame did not have a broadcast or

A collision occurring during the preamble or BOF flag
is the nonnal type of collision that is expected. When
this type of collision occurs the GSC automatically
handles the retransmission attempts for as many as
eight tries. If on the eighth attempt a collision occurs,
the transmitter is disabled, although the jam and backoff are performed. If enabled, the CPU is then interrupted. The user software should then determine what
, action to take. The possibilities range from just reporting the error and aborting' transmission to reinitializing
the serial channel registers and attempt retransmission.

8-39

inter

HARDWARE DESCRIPTION OF THE 83C152

If less than eight attempts are desired TCDCNT can be
loaded with some value which will reduce the number
of collisions possible before TCDCNT overflows. The
value loaded should consist of all 1s as the least significant bits, e.g. 7, OFH, 3FH. A solid block of Is is suggested because TCDCNT is used as a mask when generating the random slot number assignment. The
TCDCNT register operates by shifting the contents one
bit position to the left as each collision is detected. As
each shift occurs a 1 is loaded into the LSB. When
tCDCNT overflows, GSC operation stops and the
CPU is notified by the setting of the TCDT bit which
can flag an interrupt.

The amount of time that the GSC has before it must be
ready to retransmit after a collision is determined by
the mode which is selected. The mode is determined
MO (GMOD.5) and Ml (GMOD.6). If MO and Ml
equal 0,0 (normal backoff) then the minimum period
before retransmission will be either the interframe
space or the backoff period, whichever is longer. If MO
and Ml equal 1,1 (alternate backoff) then the minimum
period before retransmission will be the interframe
space plus the backoff period. Both of these are shown
in Figure 3.4. Alternate backoff must be enabled if using deterministic resolution. If the GSC is not ready to
retransmit by the time its assigned slot becomes available, the slot time is lost and the station must wait until
the collision resolution time period has' passed.
Instead of waiting for the collision resolution to pass,
the transmission could be aborted. The decision to
abort is usually dependent on the number of stations on
the link and how many collisions have already occurred. The number of collisions can be obtained by
examining the register, TCDCNT. The abort is normally implemented by clearing TEN. The new transmission begins by setting TEN and loading TFIFO. The
minimum amount of time available to initiate a retransmission would be one interframe space period after the
line is sensed as being idle.

As the nUfiibef of stations approach 256 the probability
of a successful transmission decreases rapidly. If there
are more than 256 stations involved in the collision
there would be nb resolution since at least two of the
stations will always have the same backoff interval selected.

All the stations monitor the link as long as that station
is active, even if not attempting to transmit. This is to
ensure that each station always defers the minimum
amount oftime before attempting a transmission and so
that addresses are recognized. However, the collision
detect circuitry operates slightly differently.
In normal back-off mode, a transmitting station always
monitors the link while transmitting. If a collision is
detected one or more of the transmitting stations apply
the jam signal and all transmitting stations enter the
back-off algorithm. The receiving stations also cop.stantly monitor for a collision but do not take part in
the resolution phase. This allows a station to try to
transmit in the middle of a resolution period. This in
turn mayor may not cause another collision. If the new
station trying to transmit on the link does so during an
unused slot time then there will probably not be a collision. If trying to transmit during a used slot time, then
there will probably be a collision. The actions the receiver does take when detecting a collision is to just
stop receiving data if data has 110t been loaded into
RFIFO or to stop reception, clear receiver enable
(REN) and set the receiver abort flag (RCABT RSTAT.6).
If deterministic resolution is used, the transmitting stations go through pretty much the same process as in
normal back-off, except that the slots are predetermined. All the receivers go through the back-off algo.rithm and may only transmit during their assigned slot.
3.6.4 SUCCESSFUL ENDING OF
TRANSMISSIONS AND RECEPTIONS

In both CSMA/CD and SDLC modes, the TDN bit is
set and TEN cleared at the end of a successful transmission. The end of the transmission occurs when the
TFIFO is empty and the last byte has been transmitted.
In CSMAlCD the user should clear the TCDCNT register after successful transmission.
At the end of a successfui reception, me RDN bit is set
. and GREN is cleared. The end of reception occurs
when the EOF flag is detected by the GSC hardware.

8-40

inter

HARDWARE DESCRIPTION OF THE 83C152

The length includes the two bit Begin Of Frame (BOP) .
flag in CSMA/CD but does not include the SDLC flag.
In SDLC mode, the BOF is an SDLC flag, otherwise it
is two consecutive ones. Zero length is not compatible
in CSMA/CD mode. The user software is responsible
for setting or clearing these bits.

3.7 Register Descriptions
ADRO,I,2,3 (95H, OA5H, OB5H, OC5H) - Address
Match Registers 0,1,2,3 - Contains the address match
values which determines which data will be accepted as
valid. In 8 bit addressing mode, a match with any of the
four registers will trigger acceptance. In 16 bit addressing mode a match with ADR1:ADRO or ADR3:ADR2
will be accepted. Addressing mode is determined in
GMOD (AL).

GMOD.3 (CT) - CRC Type - If set, 32 bit AUTODINlI-32 is used. If cleared, 16 bit CRC-CCITT is used.
The user software is responsible for setting or clearing
this flag.

AMSKO,1 (OD5H, OE5H) - Address Match Mask 0,1 Identifies which bits in ADRO,1 are "don't care" bits.
Writing a one to a bit in AMSKO,1 masks out that
corresponding bit in ADDRO,l.

GMOD.4 (AL) - Address Length - If set, 16 bit addressing is used. If cleared, 8 bit addressing is used. In 8
bit mode a match with any of the 4 address registers
will be accepted (ADRO, ADR1, ADR2, ADR3).
"Don't Care" bits may be masked in ADRO and ADRI
with AMSKO and AMSKI. In 16 bit mode, addresses
are matched against "ADR1:ADRO" or "ADR3:
ADR2". Again, "Don't Care" bits in ADR1:ADRO
can be masked in AMSK1:AMSKO. A received address
of all ones will always be recognized in any mode. The
user software is responsible for setting or clearing this
flag.

BAUD (94H) - GSC Baud Rate Generator - Contains
the value of the programmable baud rate. The data rate
will equal (frequency of the oscillator)/«BAUD + 1)
X (8)). Writing to BAUD actually stores the value in a
reload register. The reload register contents are copied
into the BAUD register when the Baud register decrements to OOH. Reading BAUD yields the current timer
value. A read during GSC operation will give a value
that may not be current because the timer could decrement between the time it is read by the CPU and by the
time the value is loaded into its destination.

GMOD.5,6 (MO,Ml) - Mode Select - Two test modes,
an optional "alternate backoff" mode, or normal backoff can be enabled with these two bits. The user software is responsible for setting or clearing the mode bits.

BKOFF (OC4H) - BackoffTimer - The backofftimer is
an eight bit count-down timer with a clock period equal
to one slot time. The backoff time is used in the
CSMA/CD collision resolution algorithm. The user
software may read the timer but the value may be invalid. as the timer is clocked asynchronously to the CPU.
Writing to OC4H will have no effect.

I

7
XTCLK

6

5

GMOD(84H)
4
3

o

2

I I MO I AL I CT I PL1
M1

Ml MO Mode
0
0 Normal
0
1 Raw Transmit
0 Raw Receive
1
1
1 Alternate Backoff

PLO

I PR I

Figure 3.14. GMOD

In raw receive mode, the receiver operates as normal
except that all the bytes following the BOF are loaded
into the receive FIFO, including the CRC. The transmitter operates as normal.

GMOD.O (PR) - Protocol- If set, SDLC protocols with
NRZI encoding and SDLC flags are used. If cleared,
CSMA/CD link access with Manchester encoding is
used. The user software is responsible for setting or
clearing this flag.

In raw transmit. mode the transmit output is internally
connected to the receiver input. The internal connection is not at the actual port pin, but inside the port
latch. All data transmitted is done without a preamble,
flag or zero bit insertion, and without appending a
CRC. The receiver operates as normal. Zero bit deletion is performed.

GMOD.I,2 (PLO,I) - Preamble length
PLl PLO LENGTH (BITS)
o 0
0
o
1
8
0
32
1
1
1
64

In alternate backoff mode the standard backoff process
is modified so the the backoff is delayed until the end of
the IFS. This should help to prevent collisions constantly happening because the IFS time is usually larger
than the slot time.

8-41

HARDWARE DESCRIPTION OF THE 83C152

GMOD.7 (XTCLK) - External Transmit Clock - If set
an external IX clock is used for the transmitter. If
cleared the internal baud rate generator provides the
transmit clock. The input clock is applied to P1.3
(T x C). The user software is responsible for setting or
clearing 'this flag. External receive clock is enabled by
setting PCON.3.

PCON(087H)
76543210

PCON contains bits for power control, LSC control,
DMA control, and GSC control. The bits used for the
GSC are PCON.2, PCON.3, and PCONA.

IFS (OA4H) - Interframe Spacing - Determines the
number of bit times separating transmitted frames in
CSMA/CD. A bit time is equal to I/baud rate. Only
even interframe space periods can be used. The number
written into this register is divided by two and loaded in
the most significant seven bits. Complete interframe
space is obtained by counting this seven bit number
down to zero twice. A user software read of this register
will give a value where the seven most significant bits
gives the current count value and the least significant
bit shows a one for the first count-down and a zero for
the second count. The value read may not be valid 'as
the timer is clocked in' periods not necessarily associated with the CPU read of IFS. Loading this register with
zero results in 256 bit times.

PCON.2 (GFIEN) - GSC Flag Idle Enable - Setting
GFIEN to a I caused idle flags to be generated between
transmitted frames in SDLC mode. SDLC idle flags
consist of 01111110 flags creating the sequence
01111110011111110 ...... 01l'1111 10. A possible side
effect of enabling GFIEN is that the maximum possible
latency from writing to TFIFO until the first bit is
transmitted increased from approximately 2 bit-times
to around 8 bit-times. GFIEN has no effect with
CSMA/CD.
PCON.3 (XRCLK) - GSC External Receive Clock Enable - Writing a I to XRCLK ,enables an external clock
to be applied to pin 5 (Port IA). The external clock is
used to determine when bits are loaded into the receiver.
PCONA (GAREN) - GSC Auxiliary Receiver Enable
Bit - This bit needs to be set to a 1 to enable the recep-

MYSLOT.O, I, 2, 3, 4, 5 -Slot Address - The six address bits choose 1 of 64 slot addresses. Address 63 has
the highest priority and address 1 has the lowest. A
value of zero will prevent a station froni transmitting
during the collision resolution period by waiting until
all the possible slot times have elapsed. The user software normally initializes this address in the operating
software.

tion of back-to~back SDLC frames. A back-to-back
SDLC frame is when the EOF and BOF is shared between two sequential frames intended for the same station on the link. If GAREN contains a 0 then the receiver will be disabled upon reception of the EOF and
by the time user software' re-enables the receiver the
first bit(s) may have already passed, in the case of backto-back frames. Setting GAREN to a 1, prevents the
receiver from being disabled by the EOF but GREN
will be cleared and can be checked by user software to
determine that an EOF has been received. GAREN has
no effect if the GSC is in CSMA/CDmode.

MYSLOT.6 (DCR) - Deterministic Collision Resolution A hJOrithm - When set. the alternate collision resoiuti~~-;;}gorithm is selected. Retriggering of the IFS on
reappearance of the carrier is also disabled. When using
this feature Alternate Backoff Mode must be selected
and several other registers must be initialized. User
. software must initialize TCDCNT with the maximum
number of slots that are most appropriate for a particular application. The PRBS register must be set to all
ones. This disables the PRBS by freezing it's contents at
OFFH. The backoff timer is used to count down the
number of slots based on the slot timer value setting the
period of one slot. The user software is responsible for
setting or clearing this flag.

PRBS (OE4H) - Pseudo-Random Binary Sequence This register contains apselldo-random number to be
used in the CSMA/CD backoff algorithm. The number
is generated by using a' feedback shift register clocked
by the CPU phase clocks. Writing all ones to the PRBS
will freeze the value at all ones. Writing any other value
to it will restart the PRBS generator. The PRBS is initialized to all zero's during RESET. A read of location
OE4H will not necessarily give the seed, used. in ,the
backoff algorithm because the PRBS counters are
clocked by internal CPU phase clocks. This means the
contents of the PRBS may have been altered between
the time when the seed was generated and before a
READ has been internally executed.

Figure 3.15. MYSLOT

MYSLOT.7 (DCJ) - D.C. Jam - When set selects D.C.
type jam, when clear, selects A.C. type jam. The user
software is responsible for setting or clearing this flag.

8-42

HARDWARE DESCRIPTION OF THE 83C152

RFIFO (OF4H) - Receive FIFO - RFIFO is a 3 byte
buffer that is loaded each time the GSC receiver has a
byte of data. Associated with RFIFO is a pointer that is
automatically updated with each read of the FIFO. A
read of RFIFO fetches the oldest data in the FIFO.

had been loaded into the receive FIFO in CSMA/CD
mode. In SDLC mode, RCABT indicates that 7 consecutive ones were detected prior to the end flag but after
data has been loaded into the receive FIFO. The status
of this flag is controlled by the GSC.

RSTAT (OESH) - Receive Status Register
76543210

IORIRCABTIAElcRCEIRDNIRFNEIGRENIHABENI
Figure 3.16. RSTAT

RSTAT.7 (OVR) - Overrun - If set, indicates that the
receive FIFO was full and new shift register data was
written into it. The setting of this flag is controlled by
the GSC and it is cleared by user software.
SLOTTM (OBH) - Slot Time - Determines the length of
the slot time used in CSMAlCD. A slot time equals
(256 - SLOTTM) X (I / baud rate). A read of
SLOTTM will give the value of the slot time timer but
the value may be invalid as the timer is clocked asynchronously to the CPU. Loading SLOTTM with 0 results in 256 bit times.

RSTAT.O (HABEN) - Hardware Based Acknowledge
Enable - If set, enables the hardware based acknowledge feature. The user software is responsible for setting
or clearing this flag.
RSTAT.I (GREN) - Receiver Enable - When set, the
receiver is enabled to accept incoming frames. This also
clears RDN, CRCE, AE, RCABT, and the receive
FIFO. It is cleared by the receiver at the end of a reception or if any errors occurred. The user software is responsible for setting this flag and the GSC or user software can clear it. The status of GREN has no effect on
whether the receiver detects a collision in CSMAlCD
mode as the receiver input circuitry always monitors
the receive pin.

TCDCNT (OD4H) - Transmit Collision Detect Count Contains the number of collisions that have occurred if
probabilistic CSMAlCD is used. The user software
must clear this register before transmitting a new frame
so that the GSC backoff hardware can accurately distinguish a new frame from a retransmit attempt.
In deterministic backoff mode, TCDCNT is used to
hold the maximum number of slots.

RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set,
indicates that the receive FIFO contains data. The receive FIFO is a three byte buffer into which the receive
data is loaded. A CPU read of the FIFO retrieves the
oldest data and automatically updates the FIFO pointers. Setting GREN to a one will clear the receive FIFO.
The status of this flag is controlled by the GSC. It is
cleared if user empties receive FIFO.

TFIFO (S5H) - GSC Transmit FIFO - TFIFO is a 3
byte buffer with an associated pointer that is automatically updated for each write by user software. Writing a
byte to TFIFO loads the data into the next available
location in the transmit FIFO. Setting TEN clears the
transmit FIFO so the transmit FIFO should not be
written to prior to setting TEN. If TEN is already set
transmission begins as soon as data is written to TFIFO.

RSTAT.3 (RDN) - Receive Done - If set, indicates the
successful completion of a receiver operation. Will not
be set if a CRC, alignment, abort, or FIFO overrun
error occurred. The status of this flag is controlled by
the GSC.

TSTAT (ODS) - Transmit Status Register
76543210

LNI I NOACK I UR I TCDT I TDN I TFNF I TEN I DMA I
Figure 3.17. TSTAT

RSTAT.4 (CRCE) - CRC Error - If set, indicates that a
properly aligned frame was received with a mismatched
CRC. The status of this flag is controlled by the GSC.

TSTAT.O (DMA) - DMA Select - If set, indicates that
DMA channels are used to service the GSC FIFO's and
GSC interrupts occur on TDN and RDN, and also enables UR to become set. If cleared, indicates that the
GSC is operating in its normal mode and interrupts
occur on TFNF and RFNE. For more information On
DMA servicing please refer to the DMA section on
DMA serial demand mode (4.2.2.3). The user software
is responsible for setting or clearing this flag.

RSTAT.5 (AE) - Alignment Error - If set, indicates
that the line went idle when the receiver shift register
was not full and the resulting CRC was bad in the
CSMAlCD mode. If a correct CRC was valid. then AE
is not set. In SDLC mode, AE indicates that a nonbyte-aligned flag was received. The status of this flag is
controlled by the GSC.
RSTAT.6 (RCABT) - Receiver Collision/Abort Detect
- If set, indicates that a collision was detected after data

8-43

HARDWARE DESCRIPTION, OF THE 83C152

TSTAT.l (TEN) - Transmit Enable - When set causes
TDN,UR, TCDT, and NOACK flag to be ,reset and
the TFIFO cleared. The transmitter will clear TEN after a successful transmission, a collision during the
data, CRC, or end flag. The user software is responsible
for setting but the GSC or user software may clear this
flag. If cleared during a transmission the GSC transmit
pin goes to a steady state high level. .This is the method
used to send an abort character in SDLC., Also DEN is'
forced to a high level. The end of transmission occurs
whenever the TFIFO is emptied.

3.8 Serial Backplane VS. Network
Environment
The C152 GSC port is intended to fulfill the needs of
both serial backplane environment and the serial communication network environment. The serial backplane
is where typically, only processor to processor communications take place within a self contained box. The
communication usually only encompasses those items
which are necessary to accomplish the dedicated task
for the box. In these types of applications there may not
be a need for line drivers as the distance between the
transmitter and receiver is relatively short. The network environment; however, usually requires transmission of data over large distances and requires drivers
and/or repeaters to ensure the data is received on both
ends.

TSTAT.2 (TFNF) - Transmit FIFO not full - When
set, indicates that new data may be written into the
transmit FIFO. The transmit FIFO is a three byte buffer that loads the transmit shift register with data. The
status of this flag is controlled by the GSC.
TSTAT.3 (TDN) - Transmit Done - When set, indicates the successfu1.completion ofa frame transmission:
If HABEN is set, TDN will not be set until ,the end of
the IFS following the, transmitted message, so that the
acknowledge can be checked. If an acknowledge is expected and not received, TDN'is not set. An acknowledge is not expected following a broadcast or multi-cast
packet. The status of this flag is controlled by the GSC.

4.0 DMA Operation
The C152 contains DMA (Direct Memory Accessing)
logic to peiform high speed data tran'sfers between any
two of
Internal Data RAM
Internal SFRs
External Data RAM

TSTAT.4 (TCDT) - Transmit Collision Detect - If set,
indicates that the transmitter halted due to a collision.
It is set if a collision occurs during the data or CRC or
ifthere are more than eight collisions. The status of this
flag is ~ontrolled by the GSC.

If external ,RAM is involved, the Port 2 and Port 0 ~

are used as the address/data bus, and RD and WR
'
signals are generated as required.

TSTAT.5 (UR) - Underrun - If set, indicates that in
DMA mode the last bit was shifted out of the transmit
register and that the DMA byte count did not equal
zero. When an underrun occurs, the transmitter, halts
without sending the CRC or the end flag. The status of
this flag is controlled by the GSC.

Hardware is also implemented to generate a Hold Request signal and await a Hold Acknowledge response
before commencing a DMA that involves external
RAM.
Alternatively, the Hold/Hold Acknowledge hardware
can be programmed to 'accept a Hold Request signal
from an external device and generate a Hold Acknowledge signal in response, to indicate to the requesting
device that the C152 will not commence a DMA to or
from external RAM while the Hold Request is active. ,

TSTAT.6 (NOACK) - No Acknowledge - If set, indicates that no acknowledge was received fodhe previous
frame. Will be set only if HABEN is set and no acknowledge is received prior to the end of the IFS.
NOACK is not set following a broadcast or a multicast packet. The status of this flag is controlled by the
GSC.
'

4.1 DMA with the 80C152

TSTAT. 7 (LNI) - Line tdle - If set, indicates' the receive line is idle. In SDLC protocol it is set if 15 consecutive 'ones are' received. In CSMA/CD protocol, line
idle is set if no transitio~s occ~r on GR X D for approximately 1.6 bit times after a r~uired transition. LNI is
cleared after a transition on GRXD.The status of this
flag is controlledby the GSC.

The C152 contains two identical general purPose 8-bit
DMA channels with 16-bit addressability: DMAO and
be executed by either chanDMAI. DMA transfers
nel independent of the other, but only by one channel at
a time. During the time that a DMA transfer is being
executed, program execution is suspended. A DMA
transfer takes one machine cycle (12 oscillator

can

8-44

intJ

HARDWARE DESCRIPTION OF THE 83C152

DMA CHANNEL 0
DARHO

I I

DARlO

DMA CHANNEL 1

I,

DESTINATION ADDRESS

.I

SARHO

II

SARLO

SOURCE ADDRESS
BCRHO

II

BCRlO

.I

DARH1

I. .I

SARH1

DCONO

DARL1

I,

BCRH1

I I

SARL1

I.
I,

SOURCE ADDRESS

BYTE COUNT

I

II

DESTINATION ADDRESS

II

BCRL1

BYTE COUNT

I

I

DCON1

I.

I

DMA 1 CONTROL

DMAO CONTROL
PCON
'-'

"-- Two new bits In PCON control
Hold/Hold Acknowledge logic

270427-28

Figure 4.1. DMA Registers

periods) per byte transferred, except when the destination and source are both in External Data RAM. In
that case the transfer takes two 'machine cycles per
byte. The term DMA Cycle will be used to mean the
transfer of a single data byte, whether it takes 1 or 2
machine cycles.

Two other bits in DCONn specify the physical source
of the data to be transferred. These are SAS (Source
Address Space) and ISA (Increment Source Address).
If SAS = 0, the source is in data memory extern;i1 to
the CIS2. If SAS = 1, the source is internal. If SAS =
1 and ISA = 0, the internal source is an SFR. If SAS
= 1 and ISA = 1, the internal source is in the 256-byte
data RAM.

Associated with each channel are seven SFRs, shown in
Figure 4.1. SARLn and SARHn holds the low and high
bytes of the' source address. Taken together they form a
16-bit Source Address Register. DARLn and DARHn
hold the low and high bytes of the destination address,
and together form the Destination Address Register.
BCRLn and BCRHn hold the low and high bytes of the
number of bytes to be transferred, and together form
the Byte Count Register. DCONn contains control and
flag bits.

In any case, if ISA = 1, the source address is automatically incremented after each byte transfer. If ISA = 0,
it is not.
The functions of these four control bits are summarized
below:
DAS

IDA

°° °1
1
1

Two bits in DCONn are used to specify the physical
destination of the data transfer. These bits are DAS
(Destination Address Space) and IDA (Increment Destination Address). If DAS = 0, the destination is in
data memory external to the C152. If DAS = 1, the
destination is internal to the CIS2. If DAS·= 1 and
IDA = 0, the internal destination is a Special Function
Register (SFR). If DAS = 1 and IDA = 1, the internal destination is in the 256-byte data RAM.

0

1

8-45

Auto-Increment

External RAM
External RAM
SFR
Internal RAM

no
yes
no
yes

ISA

Source

Auto-Increment

0
0

°1

1
1

0

External RAM
External RAM
SFR
Internal RAM

no
yes
no
yes

SAS

In any case, if IDA = 1, the destination address is
automatically incremented after each byte transfer. If
IDA = 0, it is not.

Destination

1

HARDWARE DESCRIPTION OF THE 83C152

dress. On-chip hardware then clears the flag (RI, TI,
RFNE, or TFNF) that initiated the DMA, and decrements BCRn. Note that since the flag that initiated the
DMA is cleared, it will not generate an interrupt unless
DMA servicing is held off or the byte count equals O.
DMA servicing may be held off when alternate cycle is
being used or by the status of the HOLD/HLDA logic.
In these situations the interrupt for the LSC may occur
before the DMA can clear the RI or TI flag. This is
because the LSC is serviced according to the status of
RI and TI, whether or not the DMA channels are being
used for the transferring of data. The GSC does not use
RFNE or TFNF flags when using the DMA channels
so these do not need to be disabled. When using the
DMA channels to service the LSC it is recommended
that the interrupts (RI and TI) be disabled. If the decremented BCRn is OOOOH, on-chip hardware then
clears the GO bit and sets the DONE bit. The DONE
bit flags an interrupt.

There are four modes in which the DMA channel can
operate. These are selected by the bits DM and TM
(Demand Mode and Transfer Mode) in DCONn:

OM

TM

Operating Mode

0
0

0

1
1

0

Alternate Cycles Mode
Burst Mode
Serial Port Demand Mode
External Demand Mode

1
1

The operating modes are described below.
4.1.1 ALTERNATE CYCLE MODE
In Alternate Cycles Mode the DMA is initiated by setting the GO bit in DCONn. Following the instrnction
that set the GO bit, one more instruction is executed,
and then the first data byte is transferred from the
source address to the destination address. Then another
instruction is executed, and then another byte of data is
transferred, and so on in this manner.

4.1.4 EXTERNAL DEMAND MODE
In External Demand Mode the DMA is initiated by
one of the External Interrupt pins, provided the GO bit
is set. INTO initiates a Channel 0 DMA, and INTI
initiates a Channel 1 DMA.

Each time a data byte is transferred, ,BCRn (Byte
Count Register for DMA Channel n) is decremented.
When it reaches OOOOH, on-chip hardware clears the
GO bit and sets the DONE bit, and the DMA ceases.
The DONE bit flags an interrupt.

If the external interrupt is configured to be transitionactivated, then each I-to-O transition at the interrupt
pin sets the corresponding external interrupt flag, and
generates one DMA Cycle. Then, BCRn is decremented. No more DMA Cycles take place until another
I-to-O transition is seen at the external interrupt pin. If
the decremented BCRn = OOOOH, on-chip hardware
clears the GO bit and sets the DONE bit. If the external interrupt is enabled, it will be serviced.

4.1.2 BURST MODE
Burst Mode differs from Alternate Cycles mode only in
that once the data transfer has begun, program execution is entirely suspended until BCRn reaches OOOOH,
indicating that all data bytes that were to be transferred
have been transferred. The interrupt control hardware
remains active during the DMA, so interrupt flags may
get set, but since program execution is suspended, the
interrupts will not be serviced while the DMA is in
progress.

If the external interrupt is configured to be level-activated, then DMA Cycles commence when the interrupt
pin is pulled low, and continue for as long as the pin is
held low and BCRn is not OOOOH. If BCRn reaches 0
while the interrupt pin is still low, the GO bit is cleared,
the DONE bit is set, and the DMA ceases. If the external interrupt is enabled, it will be serviced.

4.i.3 SERiAL FORi DEiviAND MOCE
In this mode-the DMA can be used to service the Local
Serial Channel (LSC) or the Global Serial Channel
(GSC).
-

If the interrupt pin is pulled up before BCRn reaches
OOOOH, then the DMA ceases, but the GO bit is still 1
and the DONE bit is still O. An external interrupt is not
generated in this case, since in level-activated mode,
pulling the pin to a logical 1 clears the interrupt flag. If
the interrupt pin is then pulled low again, DMA transfers will continue from where they were previously
stopped.

In Serial Port Demand Mode the DMA is initiated by
any of the following conditiollS, if the GO bit is set:
Source Address = SBUF
.AND. AI = 1
Destination Address = SBUF .AND. TI = 1
Source Address = AFIFO
.AND. AFNE = 1
Destination Address = TFIFO .AND. TFNF = 1

The timing for the DMA Cycle in the transition-activated mode, or for the first DMA Cycle in the level-activated mode is as follows: If the I-to-O transition is

Each time one of the above conditions is met, one
DMA Cycle is executed; that is, one data byte is transferred from the source address to the destination ad-

8-46

HARDWARE DESCRIPTION OF THE 83C152

detected before the final machine cycle of the instruction in progress, then the DMA commences as soon as
the instruction in progress is completed. Otherwise, one
more instruction will be executed before the DMA
starts. No instruction is executed during any DMA Cycle.

4.2 Timing Diagrams
Timing diagrams for single-byte DMA transfers are
shown.in Figures 4.2 through 4.5 for four kinds of
DMA Cycles: internal memory to internal memory, internal memory to external memory, external memory
to internal memory, and external memory to external
memory. In each case we assume the Cl52 is executing
out of external program memory. If the C152 is executing out of internal program memory, then PSEN is inactive, and the Port 0 and Port 2 pins emit PO and P2
SFR data. If External Data Memory is involved, the
Port 0 and Port 2 pins are used as the address/data bus,

1~- - - - - - 1 2 osc.

and RD and/or WR signals are generated as needed, in
the same manner as in the execution of a MOVX
@DPTR instruction.

4.3 Hold/Hold Acknowledge
Two operating modes of Hold/Hold Acknowledge logic are available, and either or neither may be invoked
by software. In one mode, the C152 generates a Hold
Request signal and awaits a Hold Acknowledge response before commencing' a DMA that involves external RAM. This is called the Requester Mode.
In the other mode, the C152 accepts a Hold Request
signal from an external device and generates a Hold
Acknowledge signal in response, to indicate to the requesting device that the C 152 will not commence a
DMA to or from external RAM while the Hold Request is active. This is called the Arbiter mode,

PERIODS

-----""11

--,f\.,__ __

ALE ~ _ _ _ _ _ _ _ _ _

""iN'ST1--- - - - - - - - -- - - - - -

___ _
PO ...,;;;;;;.,J __________________________________
FLOAT - - - - - - -- - - -- -"\iPcl'FLOA~INST
~

-JX

P2~~__________~p~2~sr_R________~__
_ _ _ _ _ _ _ DMA
-

CYCLE------~I. _

PCH

RESUME PROGRAM
EXECUTION

270427-29

Figure 4.2. DMA Transfer from Internal Memory to Internal Memory

- - - - - - 1 2 osc. PERIODS------li

1+1

-'f\.'_.___

ALE~_ _ _ _ _ _ _ _ _

PO

INST

::1.<

DARLn

X

'-DMA DATA OUT

P2~~____________~DA~R~Hn~____________JX~
WR

__~PC~H~

___

\1..._ _ _ _- - J1 ,
- - - - - - - D M A C Y C L E - - - - - - - . ! - RESUME PROGRAM
EXECUTION

Figure 4.3. DMA Transfer from Internal Memory to External Memory

8-47.

270427-30

HARDWARE DESCRIPTION OF THE 83C152

~I'-----12

ALE

osc. PERIOOS ------+j'1

----f\'--________~r_\......_ __

I'WlJ
P2

'---

~...._ _ _ _ _ _ _S_AR_H_n_ _ _ _ _ _

\'-----~/

- - I . - - - - - - O M A CYCLE _ _ _ _ _ _ _ 1
,, -

_'X

PCH

RESUME PROGRAM
EXECUTION

270427-31

Figure 4.4. DMA Transfer from External Memory to Internal Melflory

,------12

osc.

PERIODS

----+f"'~---12

osc.

PERIODS - - - - 1

ALE

'P2~~_ _ _ _~SA...R...
Hn~_ _ _ _Jx~

_____..... .

~ R...
Hn~_ ___JX~

__...Pc...H___

\ ....------1/
\ .....-----...1/
f-I,----------OMA CyCLE------------I-

RES~~E~~~g~RAM
270427-32

Figure 4.5. DMA Transfer from External Memory to External Memory
4.3.1 REQUESTER MODE

4.3.2 ARBITER MODE

The Requester Mode is selected by setting the control
bit REQ, which resides in PCON. In that mode, when
the C152 wants to do a DMA to External Daia Memory, it first generates a Hold Request signal, HLD, and
waits for a Hold Acknowledge signal, HLDA, before
. commencing the DMA operation. Note that program
execution continues while HLDA is awaited. The
DMA is not begun until a logical 0 is detected at the
HLDA pin. Then, once the DMA has begun, it goes to
completion regardless of the logic level at HLDA.
The protocol is activated only for DMAs (not for program fetches or MOVX operations), and only for
DMAs to or from External Data Memory. If the data
destination and source are both internal to the C152,
the HLD/HLDA protocol is not used.
The HLD output is an alternate function of port pin
P1.5, and the HLDA input is an alternate function of
port pin 1>1.6.
,8-48

For DMAs that are to be driven by some device other
than the C152, a different version of the Hold/Hold
Acknow"lcdgc protocol is available. In this version the
device which is to drive the DMA sends a Hold Request signal, HLD, to the C152. If the C152 is currently performing a DMA to or from External Data Memory, it will complete this DMA before responding to the
Hold Request. When the C152 responds to the Hold
Request, it 'does so by activating a Hold Acknowledge
signal, HLDA. This indicates that the C152 will not
commence a new DMA to or from External Data
Memory while HLD remains active.
j

Note that in the Arbiter Mode the C152 does not suspend program execution at all, even if it is executing
from external program memory. It does not surrender
use of its own bus.
The Hold Request input, HLD, is at P1.5. The Hold
Acknowledge output, HLDA, is at P1.6. This

inter

HARDWARE DESCRIPTION OF THE 83C152

version of the Hold/Hold Acknowledge feature is selected by setting the.control bit ARB in PCON.
The functions of the ARB and REQ bits in PCON,
then, are
ARB

REQ

Hold/Hold Acknowledge Logic

0
0
1
1

0
1
0
1

Disabled
C152 generates HLD, detects HLDA
C152 detects HLD, generates HLDA
Invalid

ALE (ARB)

IF

270427-34

Figure 4.7. ALE Switch Select

The ALE Switch logic can be implemented by a single
74HCOO, as shown in Figure 4.7.

The HOLD/HOLDA logic only affects DMA operation with external RAM and doesn't affect other operations with external RAM, such as MOVX instruction.

Figure 4.8 shows the additional gating that is required
when one of the CPUs is executing from external
ROM. In this case the CPU has constant access to its
own local bus, and accesses the global RAM only after
gaining access to a global address/data bus.

Figure 4.6 shows a system in which two 83C152s are
sharing a global RAM. In this system, both CPUs are
executing from internal ROM. Neither CPU uses the
bus except to access the shared RAM, and such accesses are done only through DMA operations, not by
MOVX instructions.

If the CPU is programmed to be a Requester, as shown
in Figure 4.8, then when it wants to access the global
RAM it first activates HLD, and continues program
execution on its own local bus while awaiting an active
level at HLDA.

One CPU is programmed to be the Arbiter and the
other, to be the Requester. The ALE Switch selects
which CPU's ALE signal will be directed to the address
latch.
Arbiter's ALE is selected if HLDA is high,
and the Requester's ALE is selected if HLDA is low .

An active level at HLDA enables the local bus to the
global bus, and signals the !!:9uester to proceed with
its DMA. The Requester's RD signal, rather than its

The

.. Vee
A l8Xl0kll
PO
83C152
P2
ARB

Viii

.-7

ALE I - -

U

r- RD
HLD

HLD

r-v

HLDA

~

HLDA

•
§I3

7
3

~

ALE
SWITCH

ALE

83C152
REa

I'- Viii

PO

RD

P2

~

=0

ALE
(REO) -----...--J

4.3.3 USING THE HOLD/HOLD ACKNOWLEDGE

..-

ilLiiii =1

ALE (REO)

IF IlIJlA

l-

.P

DATA

,
OE
WE

LOW

HIGH

'------'
SHARED
RAM

ADDR

270427-33

Figure 4.6. Two 83C152s Sharing External RAM

8-49

intJ

HARDWARE DESCRIPTION OF THE 83C152

LOCAL BUS
ROM
PO \ r - - - ; - - ,
BOC152
REQ
P2

ViR

PSEN

rrn

ALE

HLD

SHARED BUS"

HLDA

, ).-

...

\

\

,
,

\

LOW

,

,

ADDR~

:

I

,

I

,
,

HIGH

,

~-~--~

I

I

I

I
I
I
I

,,,
,
t-......-OE

,'

WE
\

...

,

I
~

T,

THLDA
SYSTEM ARBITER

270427-35

Figure 4.8. Separation of Local and Global Busses

8-50

inter

HARDWARE DESCRIPTION OF THE 83C152

WR signal, is used to control the direction of the transceiver. This is to ensure that the transceiver will not try
to drive the local bus before the DMA has actually
begun.

Figure 4.9 shows the three tasks to which the internal
bus of the CI52 can be dedicated. In this figure, Instruction Cycle means the complete execution of a single instruction, whether it takes 1,2 or 4 machine cycles. DMA Cycle means the transfer of a single data
byte from source to destination, whether it takes 1 or 2
machine cycles. (It takes 2 machine cycles.jf the destination and source are both external to the CI52.) Onchip arbitration logic determines which type of cycle is
executed, according to the. following rules.

RD from the Requester is ~cally ANDed with RD
from the Arbiter to activate OE to the RAM. WR from
the Requester can normally be hard-wired to WR from
the Arbiter to activate WE to the RAM.

4.4 DMA Arbitration

If the HLD/HLDA logic is disabled (ARB = 0, REQ
= 0):
• A write to any DMA address or control register is
always followed by an Instruction Cycle. If the next
instruction is a read or write to a DMA address or
control register, the DMA cycle is held off one more
instruction cycle.
• A DMAO Cycle is called for if GOO = 1 and any of
the following conditions are satisfied:
1. Channel 0 Burst Mode is selected;
2. Channel 0 is in SP Demand Mode. and a SP Demand flag is up (but see • *);

The DMA Arbitration described in this section is not
arbitration between two devices wanting to access a
shared RAM, but rather on-chip arbitration between
the two DMA channels on the C152.
The CI52 provides two DMA channels, either of which
may be called into operation at any time in response to
real time conditions in the application circuit. However, only one DMA channel can be serviced during a
single DMA cycle.
In the event that both DMA channels request service at
the same time, DMA Channel 0 takes precedence.

270427-36

Figure 4.9. Internal Bus Tasks

8-51

HARDWARE DESCRIPTION OF THE 83C152

IDA (Increment Destination Address) If IDA = 1, the
destination address' is automatically incremented after
each byte transfer. IfiDA =0, it is not..

3. Channel 0 is in External .Demand Mode and an
External Demand flag is up;
4. Channel 0 is ·in Alternate Cycles Mode and Channel 1 isn't, and the previous cycle was not a DMA
Cycle;
5. Channel 0 and Channell are both in Alternate
Cycles Mode, and the previous cycle was not a
DMA Cycle, and the previous DMA Cycle was
not a DMAO cycle.
'
• A DMAI Cycle is called for if GOI = 1 and no
condition for a DMAO Cycle is satisfied, and any of
the following conditions are satisfied:
1. Channel 1 Burst Mode is selected;
2~ Channel 1 is in SP Demand Mode and a SP Demand flag is up (but see "*);
3. Channel 1 is in External Dem~nd Mode and an
External Demand flag is up;
4. Channel 1 is in Alternate Cycles Mode and Channel 0 isn't, and the previous cyCle was not a DMA
Cycle;
5. Channel 1 and Channel 0 are both in Alternate
, Cycles Mode, and the previous cycle was not a
DMA Cycle, and the previous DMA Cycle was
not a DMAI cycle.
"If a DMA Cycle is not called for, then an Instruction Cycle is executed.
A Special Case: Because of internal timing conflicts,
a SP Demand Mode DMA Cycle in which the destination address is TFIFO will not be generated unless the previous cycle was an Instruction Cycle.

SAS specifies the Source Address Space. If SAS = 0,
the source is in External Data Memory. If SAS = 1
and ISA = 0, the source is an SFR. If SAS = 1 and
ISA = 1, the source is Internal Data RAM.
ISA (Increment Source Address) If ISA = 1, the
source address is automatically incremented after each
byte transfer. If ISA.= 0, it is not.
DM (Demand Mode) If DM = 1, the DMA Channel
operates in Demand Mode. .In Demand Mode the
DMA is initiated either by an external signal or by a
Serial Port flag, depending on the value of the TM bit.
If DM = 0, the DMA is requested by setting the GO
bit in software.
TM (Transfer'Mode) If DM = 1 then TM selects
whether a DMA is initiated by an external signal (TM
= I) or by a Serial Port flag (TM = 0). If DM = 0
then TM selects whether the data transfers are to be in
bursts (TM = 1) or in alte~ate cycles (TM = 0).
DONE indicates the completion of a DMA operation
and flags an interrupt. It is set to 1 by on-chip hardware
when BeRn = 0, and is cleared to 0 by on-chip hardware when the interrupt is vectored to. It can also be
set or cleared by software.

*.

GO is the enable bit for the DMA Channel itself. The
DMA Channel is inactive if GO = O.

Note that any time conditions are satisfied for a DMAO
Cycle, the DMAO Cycle will be executed, even if the
DMAI Channel is active. That is not to say a DMAI
Cycle will be interrupted once it has begun. However,
once a cycle has begun, be it,an'Instruction Cycle or a
DMA Cycle, it will be completed without interruption.

PCON I SMOD I ARB I REQ I GAREN I XRCLK I GFIEN I PDN IIDL I

ARB enables the DMA logic to detect HLD and generate HLDA. After it has activated HLDA, the CI52 will
not begin a new DMA to or from External Data Memory as long as HLD is seen to be active. This logic is
disabled when ARB = 0, and enabled when ARB = 1.

If the HLD/HLDA logic is not disabled (either ARB
= i or REQ = i), then the HoidiHoid Acknowiedge

REQ enables the DMA logic to generate HLD and detect HLDA before performing a DMA to or from External Data Memory. After it has activated HLD, the
C152 will not begin the DMA until HLDA is seen to be
active. This logic is disabled when REQ = 0, and enabled when REQ = 1.

protocol will also be observed, as previously described,
for DMAs to or from external RAM.

4.5 Summary of DMA Control Bits
DCONn I DAS I IDA I SAS liSA I OM I TM I DONE I GO I

5.0 GLOSSARY

DAS specifies the Destination Address Space. If DAS
= 0, the destination is in External Data Memory: If
DAS = 1 and IDA = 0, the destination is a Special
Function Register (SFR). If DAS = 1 and IDA = 1,
the destination is in Internal Data RAM.

ADRO,I,2,3 (95H, OA5H, OB5H, OC5H) - Address
Match Registers 0,1,2,3 - The contents of these SFRs
are compared against the address bits from the serial

8-52

inter

HARDWARE DESCRIPTION OF THE 83C152

data on the GSC. If the address matches the SFR, then
the ClS2 accepts that frame. If in 8 bit addressing
mode, a match with any of the four registers will trigger
acceptance. In 16 bit addressing mode, a match with
ADRl:ADRO or ADR3:ADR2 will be accepted. Address length is determined, by GMOD, (AL).

DCI - D.C. Jam, see MYSLOT.

AE - Alignment Error, see RSTAT.

The DCON registers control the operation of the DMA
channels by determining the source of data to be transferred, the destination of the data to be transfer, and the
various modes of operation.

DCONO/I (092H,093H)
76543210

AL - Address Length, see GMOD.
AMSKO,l (ODSH, OESH) - Address Match Mask 0,1 Identifies which bits in ADRO,l are "don't care" bits.
Setting a bit to 1 in AMSKO,l identifies the corresponding bit in ADDRO,1 as not to be examined when
comparing addresses.

DCON.O (GO) - Enables DMA Transfer - When set it
enables a DMA channel. If block mode is set then
DMA transfer starts as soon as possible under CPU
control. If demand mode is set then DMA transfer
starts when a demand is asserted and recognized.

BAUD - (94H) Contains the programmable value for
the baud rate generator for the GSC. The baud rate will
equal (fosc)/«BAUD+ 1) X 8).

DCON.l (DONE) - DMA Transfer is Complete When set the DMA transfer is complete. It is set when
BCR equals 0 and is automatically reset when the
DMA vectors to its interrupt routine. If DMA interrupt is disabled and the user software executes a jump
on the DONE bit, then the user software must also
reset the done bit. If DONE is not set, then the DMA
transfer is not complete.

BCRLO,l (OE2H, OF2H) - Byte Count Register Low
0,1 - Contains the lower byte of the byte count. Used
during DMA transfers to identify to the DMA chan.
nels when the transfer is complete.
BCRHO,l (OE3H, OF3H) - Byte Count Register High
0,1 - Contains the upper byte of the byte. count.

DCON.2 (TM) - Transfer Mode - When set, DMA
burst transfers are used if the DMA channel is configured in block mode or external interrupts are used to
initiate a transfer if in Demand Mode. When TM is
cleared, Alternate Cycle Transfers are used if DMA is
in the Block Mode, or Local Serial channel/GSC interrupts are used to initiate a transfer if in Demand Mode.

BKOFF (OC4H) - Backoff Timer - The backoff timer is
an eight bit count-down timer with a clock period equal
to one slot time. The backoff time is used in the
CSMA/CD collision resolution algorithm.
BOF - Beginning of Frame flag -. A term commonly
used when dealing with packetized data. Signifies the
beginning of a frame.

DCON.3 (DM) - DMA Channel Mode - When set,
Demand Mode is used and when cleared, Block Mode
is used.

CRC - Cyclic Redundancy Check - An error checking
routine that mathematically manipulates a value dependent on the incoming data. The purpose is to identify
when a frame has been received in error.

DCON.4 (ISA) - Increment Source Address - When
set, the source address registers are automatically incremented during each transfer. When cleared, the source
address registers are not incremented.

CRCE - CRC Error, see RSTAT.

DCON.S (SAS) - Source Address Space - When set, the
source of data for the DMA transfers is internal data
memory if autoincrement is also set. If autoincrement is
not set but SAS is, then the source for data will be one
of the Special Function Registers. When SAS is cleared,
the source for data is external data memory.

CSMA/CD - Stands for Carrier Sense, Multiple Access, with Collision Detection.
CT - CRC Type, see GMOD.
DARLO/l (OC2H, OD2H) - Destination Address Register Low 0/1 - Contains the lower byte of the destinations' address when performing DMA transfers.

DCON.6 (IDA) -' Increment Destination Address
Space - When set, destination address registers are incremented once after each byte is transferred. When
cleared, the destination address registers are not automatically incremented.

DARHO/I (OC3H, OD3H) - Destination Address Register Low 0/1 - Contains the upper byte of the destinations' address when performing DMA transfers.
DAS - Destination Address Space, see DCON.

8-53

inter

HARDWARE DESCRIPTION OF THE 83C152

DCON.7 (DAS) - Destination Address Space - When
set, destination of data to be transferred is internal data
memory if autoincrement mode is also set. If autoincrement is not set the destinationwill be one of the Special
Function Registers. When DAS is cleared then the destination is external data memory.

GMOD(84H)

7

4

3

210

The bits in this SFR, perform most of the configuration
on the type of data transfers to be used with the GSC.
Determines the mode, address length, preamble length,
protocol select, and enables the external clocking of the
transmit data.

DEN - An alternate function of one of the port I pins
(p1.2). Its purpose is to enable external drivers when
the GSC is transmitting data. This function is always
active when using the GSC and if P1.2 is programmed
to a 1.

GMOD.O (PR) - Protocol- If set, SDLC protocols with
NRZI encoding, zero bit insertion, and SDLC flags are
used. If cleared, CSMAlCD link access with Manchester encoding is used.

DM - DMA Mode, see DCONO.

GMOD.l,2 (pLO, 1) - Preamble length

DMA - Direct Memory Access mode, see TSTAT.

PLI PLO LENGTH (BITS)

DONE - DMA done bit, see DCONO.

000
o
1
8
1
0
32
1
1
64

DPH -Data Pointer High, an SFR that contains the
high order byte of a general purpose pointer called the
data pointer (DPTR).

The length includes the two bit Begin Of frame (BOF)
flag in CSMAlCD but does not include the SDLC flag.
In SDLC mode, the BOF is an SDLC flag, otherwise it
is two consecutive ones. Zero length is not compatible
in CSMAlCD mode.

DPL - Data Pointer Low, an SFR that contains the low
order bytc of the data pointer.
~

5

IXTCLK I M1 I MO I AL I CT I PL1 I PLO I PR I

DCR - Deterministic Resolution, see MYSLOT.

EDMAO
IENl.

6

Enable DMA Channel 0 interriJpt, see

GMOD.3 (CT) - CRC Type - If set, 32-bit AUTODIN11-32 is used. If cleared, 16-bit CRC-CCITT is used.

EDMAI - Enable DMA Channel 1 interrupt, see
IENl.

GMOD.4 (AL) - Address Length - If set, 16-bit addressing is used. If cleared, 8-bit addressing is used. In
8-bit mode, a match with any of the 4 address registers
will allow that frame to be accepted (ADRO, ADRl,
ADR2, ADR3). "Don't Care" bits may be masked in
ADRO and ADRI with AMSKO and AMSKl. In 16bit mode,
addresses
are
matched
against
"ADRl:ADRO" or "ADR3:ADR2". Again, "Don't
Care" bits in ADRl:ADRO can be masked in
AMSKi:AMSKO. A received address of an ones win
always be recognizCd in any mode.

EGSRE - Enable GSC Receive Error interrupt, see
IENl.
EGSRV - Enable GSC Receive Valid interrupt, see
IENl.
.
EGSTE - Enable GSC Transmit Error interrupt, see
IENl.
EGSTV - Enable GSC Transmit Valid internipt, see
IENl.

GMOD.5, 6 (MO,Ml) -Mode Select- Two test modes,
an optional "alternate backofl" mode, or normal backoff can be enabled with these two bits.

EOF - A general term used in serial communications.
EOF stands for End Of Frame and signifies when the
last bits of data are transmitted when using packetized
data.

Ml

MO
·0
o 1
1
0
1
1

o

ES - Enable LSC Service interrupt, see IE.
ETO - Enable Timer 0 interrupt, see IE.
ETl - Enable Timer 1 interrupt, see IE.

Mode
Normal
Raw Transmit
Raw Receive
Alternate Backoff

GMOD.7 (XTCLK) - External Transmit Clock - If set
an external IX clock is used for the transmitter. If
cleared the internal baud rate generator provides the

EXO - Enable External interrupt 0, see IE.
EXI - Enable External interrupt 1, see IE.
8-54

inter

HARDWARE DESCRIPTION OF THE 83C152

transmit clock. The input clock is applied to Pl.3
(TxC). The user software is responsible for setting or
clearing this flag. External receive clock is enabled by
setting PCON.3.

IE.2 (EXl) - Enables the external interrupt INTI on
P3.3.

GO - DMA Go bit, see DCONO.

IE.4 (ES) - Enables the Local Serial Channel interrupt.

GRxD - GSC Receive Data input, an alternate function
of one of the port I pins (P 1.0). This pin is used as the
receive input for the GSC. PLO must be programmed
to a 1 for this function to operate.

IE.7 (EA) - The global interrupt enable bit. This bit
must be set to a 1 for any other interrupt to be enabled.

GSC - Global Serial Channel - A high-level, multi-protocol, serial communication controller added to the
SOC5lBH core to accomplish high-speed transfers of
packetized serial data.
GTxD - GSC Transmit Data output, an alternate function of one of the port I pins (P 1.1). This pin is used as
the transmit output for the GSC. Pl.l must be programmed to a I for this function to operate.
HBAEN - Hardware Based Acknowledge Enable, see
RSTAT.
HLDA - Hold Acknowledge, an alternate function of
one of the port 1 pins (Pl.6). This pin is used to perform the "HOLD ACKNOWLEDGE" function for
DMA transfers. HLDA can be an input or an output,
depending on the configuration of the DMA channels.
PI.6 must be programmed to a 1 for this function to
operate.
HOLD - Hold, an alternate function of one of the port
1 pins (P1.5). This pin is used to perform the "HOLD"
function for DMA transfers. HOLD can be an input or
an output, depending on the configuration of the DMA
channels. Pl.5 must be programmed to a 1 for this
function to operate.
IDA - Increment Destination Address, see DCONO.

IB.3 (ETI) - Enables the Timer 1 interrupt.

IENl - (OCSH)
76

EA

I ES I ET1 I EX1 I ETO

3

2

1

0

Interrupt enable register for DMA and GSC interrupts.
A 1 in any bit position enables that interrupt.
IENI.O (EGSRV) - Enables the GSC valid receive interrupt.
IEN1.1 (EGSRE) - Enables the GSC receive error interrupt.
IENl.2 (EDMAO) - Enables the DMA done interrupt
for Channel O.
IEN1.3 (EGSTV) - Enables the GSC valid transmit interrupt.
IENl.4 (EDMAl) - Enables the DMA done interrupt
for Channel 1.
IEN1.5 (EGSTE) - Enables the GSC transmit error interrupt
IFS - (OA4H) Interframe Space, determines the number
of bit tiflles separating transmitted frames.

7

6
I

5

4

IP (OBSH)
3
2

PS I PT1 I PX1

1

0

PTO

PXO

0
EXO

Interrupt Enable SFR, used to individually enable the
Timer and Local Serial Channel interrupts. Also con~
tains the global enable bit which must be set to a 1 to
enable any interrupt to be automatically recoguized by
the CPU.
IE.O (EXO) - Enables the external interrupt INTO on
P3.2.
IE.l (ETO) - Enables the Timer 0 interrupt.

4

IIIEGSTEIEDMA11EGSTVIEDMAOIEGSREIEGSRVI

IE (OASH)
765432

5

Allows the user software two levels of prioritization to
be assigned to each of the interrupts in IE. A 1 assigns
the corresponding interrupt in IE a higher interrupt
than an interrupt with a corresponding O.
IP.O (PXO) - Assigns the priority of external interrupt,
INTO.
.
IP.1 (PTO) - Assigns the priority of Timer 0 interrupt,
TO.

inter

HARDWARE DESCRIPTION OF THE 83C152

Determines which type of Jam is used, which backoff
algorithm is used, and the DCR slot address for the
.
GSC.

IP.2 (PXI)- Assigns the priority of external interrupt,
INTl.
IP.3 (PTl) - Assigns the priority of Timer I interrupt,
Tl.

MYSLOT.O,I,2,3,4,5 (SAO,I,2,3,4,5) - These bits determine which slot address is assigned to the CI52 when
using deterministic backoff during CSMA/CD operations on the GSC. Maximum slots available is 63. An
address of OOH prevents that station from participating
in the backoff process.

IP.4 (PS) - Assigns the priority of the LSC interrupt,
SBUF.
IPNI - (OFSH)
76

I I I

5
PGSTE

I

4
PDMA1

3

2

1

0

I PGSTV I PDMAO I PGSRE I PGSRV I

MYSLOT.6 (DCR) - Determines which collision resolution algorithm is used. If set to a I, then the deterministic backoff is used. If cleared, then a random slot
assignment is used.

Allows the user software two levels of prioritization to
be assigned to each of the interrupts in IENl. A I assigns the corresponding interrupt in IENI a higher interrupt than an interrupt with a corresponding O.

MYSLOT.7 (DCJ) - Determines the type of Jam used
during CSMA/CD operation when a collision occurs.
If set to a I then a low D.C. level is used as the jam
signal. If cleared, then CRC is used as the jam signal.
The jam is applied for a length of time equal to the
CRC length.

IPNl.O (PGSRV) - Assigns the priority ofGSC receive
valid interrupt.
IPNl.l (PGSRE) - Assigns the priority of GSC error
receive iriterrupt.

NOACK - No Acknowledgment error bit, see TSTAT.

IPN1.2 (PDMAO) - Assigns the priority of DMA done
interrupt for Channel O.

NRZI - Non-Return to Zero inverted, a type of data
encoding where a 0 is represented by a change in the
level of the serial link. A I is represented by no change.

IPNl.3 (pGSTV) - Assigns the priority of GSC transmit viilid interrupt.

OVR - Overrun error bit, see RSTAT.

IPNl.4 (PDMAI) - Assigns the priority ofDMA done
interrupt for Channel 1.
IPNI.5 (pGSTE) - Assigns the priority of GSC transmit error interrupt.

PR - Protocol select bit, see GMOD. PCON (S7H)
76543210
ISMoolARSIREOIGARENIXRCLKIGFIENlpollOLI

ISA - Increment Source Address, see DCONO.

PCON.O (IDL) -Idle bit, used to place the CI52 into
the idle power saving mode.

LNI - Line Idle, see TSTAT.
PCON.I (PD) - Power Down bit, used to place the
CI52 into the power down power saving mode.

LSC - Local Serial Channel - The as¥nchronous serial
MCS-51
devices. Uses start/stop bits
port
found onL'__
all __
__ .l __
1._ 1 L __ ... _ _ ... _ ...: __ _
0_

~_:' _ _

FCON.2 (GFIEN) - GSC Fiag Idie Enabie bit, when
set, enables idle flags (01111110) to be generated between transmitted frames in SDLC mode.

i1UU t,;UU UUUMCJ UJUY 1 UyLC ilL i1 LlIUt:.

MO - One of two GSC mode bits, see TMOD.
MI - One of two GSC mode bits, see TMOD

PCON.3 (XRCLK) - External.Receive Clock bit, used
to enable an external clock to be used for only the receiver portion of the GSC.

MYSLOT - (OF5H)
76543210

PCON.4 (GAREN) - GSC Auxiliary Receive Enable
bit, used to enable the GSC to receive back-to-back
SDLC frames. This bit has no effect in CSMA/CD
mode.

8-56

HARDWARE DESCRIPTION OF THE 83C152

PCON.5 (REQ) - Requester mode bit, set to a I when
CI52 is to be operated as the requester station during
DMA transfers.

RFIFO - (F4H) RFIFO is a 3-byte FIFO that contains
the receive data from the GSC.

PCON.6 (ARB) - Arbiter mode bit, set to a I when
CI52 is to be operated as the arbiter during DMA
transfers.
PCON.7 (SMOD) - LSC mode bit, used to double the
baud rate on the LSC.

RSTAT (OE8H) - Receive Status Register
76543210

RSTAT.O (HBAEN) - Hardware Based Acknowledge
Enable - If set, enables the hardware based acknowledge feature.

PDMAO - Priority bit for DMA Channel 0 interrupt,
see IPNl.
'

RSTAT.I (GREN) - Receiver Enable - When set, the
receiver is enabled to accept incoming frames. This also
clears RDN, CRCE, AE, RCABT and the receive
FIFO. It is cleared by the receiver at the end of a reception or if any errors occurred: The status of GREN has
no effect on whether the receiver detects a collision in
CSMA/CD mode as the receiver input circuitry always
monitors the receive pin.

PDMAI - Priority bit for DMA Channel I interrupt,
see IPNl.
PGSRE - Priority bit for GSC Receive Error interrupt,
see IPNl.
PGSRV - Priority bit for GSC Receive Valid interrupt,
see IPNl.

RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set,
indicates that the receive FIFO contains data. The receive FIFO is a three byte buffer into which the receive
data is loaded. A CPU read of the FIFO retrieves the
oldest data and automatically updates the FIFO pointers. Setting GREN t9 a one will clear the receive FIFO.
The status of this flag is controlled by the GSC. This bit
is cleared if user S/W empties receive FIFO.

PGSTE - Priority bit for GSC Transmit Error interrupt, see IPNl.
PGSTV - Priority bit for GSC Transmit Valid interrupt, see IPNl.
PLO - One of two bits that determines the Preamble
Length, see GMOD.
PLI - One of two bits that determines the Preamble
Length, see GMOD.

RSTAT.3 (RDN) - Receive Done - If set, indicates the
successful completion of a receiver operation. Will not
be set if a CRC, alignment, abort, or FIFO overrun
error occurred.

PRBS - (OE4H) Pseudo-Random Binary Sequence, generates the pseudo-random number to be used in
CSMA/CD backoff algorithms.

RSTATA (CRCE) - CRC Error - Ifset, indicates that a
properly aligned frame was received with a mismatched
CRC.

PS - Priority bit for the LSC service interrupt, see IP.

RSTAT.5 (AE) - Alignment Error - If set, indicates
that the line went idle when the receiver shift register
was not full and the resulting CRC was bad in the
CSMA/CD mode. If a correct CRC was valid then AE
is not set. In SDLC mode, AE indicates that a nonbyte-aligned flag was received.

PTO - Priority bit for Timer 0 interrupt, see IP.
PTl - Priority bit for Timer I interrupt, see IP.
PXO - Priority bit for External interrupt 0, see IP.

RSTAT.6 (RCABT) - Receiver Collision/Abort Detect
- If set, indicates that a collision was detected after data
had been loaded into the receive FIFO in CSMA/CD
mode. In SDLC mode, RCABT indicates that 7 consecutive ones were detected prior to the end flag but after
data has been loaded into the receive FIFO.

PXI - Priority bit for External interrupt I, see IP.
RCABT - GSC Receiver Abort error bit, see RSTAT.
RDN - GSC Receiver Done bit, see RSTAT.
GREN - GSC Receiver Enable bit, see RSTAT.

RSTAT.7 (OVR) - Overrun - If set, indicates that the
receive FIFO was full and new shift register data was
written into it. It is cleared by user S/W.

RFNE - GSC Receive FIFO Not Empty bit, see
RSTAT.
RI - LSC Receive Interrupt bit, see SCON.

8-57

inter

HARDWARE DESCRIPTION OF THE 83C152

SARHO (OA3H) - Source Address Register High 0,
contains the high byte of the source address for DMA
Channel O.

SP (OSIH) - Stack Pointer, an eight bit pointer register
used during a PUSH, POP, CALL, RET, or RETI.
TCDCNT - (OD4H) Contains the number of collisions
in the current frame if using probabilistic CSMA/CD
and contains the maximum number of slots in the deterministic mode.

SARHI (OB3H) - Source Address Register High I,
contains the high byte of the source address for DMA
Channell.
SARLO (OA2H) - Source Address Register Low 0, contains the low. byte of the source address for DMA
Channel O.

TCDT - Transmit Collision Detect, see TSTAT.
TCON(OSSH)
76543210

SARLI (OB2H) - Source Address Register Low I, contains the low byte of the source address for DMA
Channell.

I TF1 I TA1 I TFO I TAO IIE1 IIT1 I lEO liTO I
TCON.O (ITO) - Interrupt 0 mode control bit.

SAS - Source Address Space bit, see DCONO.

TCON.I (lEO) - External interrupt 0 edge flag.

SBUF (099H) - Serial Buffer, both the receive and
transmit SFR location for the LSC.

TCON.2 (IT!) - Interrupt I mode control bit.

SCON(09SH)
76543210

TCON.3 (lEI) - External interrupt I edge flag.

I SMO I SM1 15M2 I AENI TB8 I AB8 I TI I AI I

TCON.4 (TRO) - Timer 0 run controi bit.
CON.5 (TFO) - Timer 0 overflow flag.

SCON.O (RI) - Receive Interrupt flag.
TCON.6 (TRI) - Timer I run control bit.
SCON.I (TI) - Transmit Interrupt flag.
TCON.7 (TFI) - Timer I overflow flag.
SCON.2 (RBS) - Receive Bit S, contains the ninth bit
that was received in Modes 2 and 3 or the stop bit in
Mode I if SM20. Not used in Mode O.

TDN.- Transmit Done flag, see TSTAT.
TEN - Transmit Enable bit, see TSTAT.

SCON.3 (TBS) - Transmit Bit S, the ninth bit to be
transmitted in Modes 2 and 3. .

TFNF - Transmit FIFO Not Full flag, see TSTAT.

SCON.4 (REN) - Receiver Enable, enables reception
for the LSC.

TFIFO - (S5H) TFIFO is a 3-byte FIFO that contains
the transmission data for the GSC.

SCON.5 (SM2) - Enables the multiprocessor communication feature in Modes 2 and 3 for the LSC.

THO (OSCH) - Timer 0 High byte, contains the high
byte for timer/counter O.

ScON.6 (SMI) - LSC mode specifier.

THI (OSDH) - Timer I High byte, contains the high
byte for timer/counter 1.
.

SCON.7 (SM2) - LSC mode specifier.
TI - Transmit Interrupt, see SCON.
SDLC - Stands for Synchronous Data Link Communication and is a protocol developed by IBM.

TLO (OSAH) - Timer 0 Low byte, coptains the low byte
for timer/counter O.

SLOTTM - (OB4H) Determines the length of the slot
time in CSMA/CD.

TLI (OSBH) - Timer I Low byte, contains the low byte
for timerlCounter 1.
TM - Transfer Mode, see, DCONO.

8-58

inter

HARDWARE DESCRIPTION OFTHE 83C152

TMOD(OS9H)
76543210

IGATE ICIT I M1 I MO I GATE I CIT I M1 I MO I

TSTAT.3 (TDN) - Transmit Done - When set, indicates the successful completion of a frame ttansmission.
If HBAEN is set, TDN will not be set until the end of
the IFS following the transmitted message, so that the
acknowledge can be checked. If an acknowledge is expected and not received, TDN is not set. An acknowledge is not expected following a broadcast or multi-cast
packet.

TMOD.O (MO) - Mode selector bit for Timer O.
TMOD.l (Ml) - Mode selector bit for Timer O.
TMOD.2 (CIf) - Timer/Counter selector bit for
TimerO.
TMOD.3 (GATE) - Gating Mode bit for Timer O.

TSTAT.4 (TCDT) - Transmit Collision Detect - If set,
indicates that the transmitter halted due to a collision.
It is set if a collision occurs during the data or CRC or
if there are more than eight collisions.

TMOD.4 (MO) - Mode selector bit for Timer 1.
TMOD.5 (Ml) - Mode selector bit for Timer 1.
TMOD.6 (C/T) - Timer/Counter selector bit for
Timer L

TSTAT.5 (UR) - Underrun - If set, indicates that in
DMA mode the last bit was shifted out of the transmit
register and that the DMA byte count did not equal
zero. When an underrun occurs, the transmitter halts
without sending the CRC or the end flag.

TMOD.7 (GATE) - Gating Mode bit for Timer 1.

7

TSTAT (ODS) - Transmit Status Register
6
5
4
32
1

TSTAT.2 (TFNF) - Transmit FIFO not full - When
set, indicates that new data may be written into the
transmit FIFO. The transmit FIFO is a three byte butTer that loads the transmit shift register with data.

0

ILNII NOACK I UR I TCOT ITON I TFNF I TEN IOMA I
TSTAT.O (DMA) - DMA Select - If set, indicates that
'DMA channels are used to service the GSC FIFO's and
GSC interrupts occur on TDN and RDN, and also enables UR to become set. If cleared, indicates that the
GSC is operating in it normal mode and interrupts occur on TFNE and RFNE.For more information on
DMA servicing please refer to the DMA section on
DMA serial demand mode (4.2.2.3).
TSTAT.l (TEN) - Transmit Enable - When set causes
TDN, UR, TCDT, and NOACK flags to be reset and
the TFIFO cleared. The transmitter will clear TEN after a successful transmission, a collision during the
data, CRC, or end flag. If cleared during a transmission
the GSC transmit pin goes to a steady state high level.
This is the method used to send an abort character in·
SDLC. Also DEN is forced to a high level. The end of
transmission is occurs whenever the TFIFO is emptied.

8-59

TSTAT.6 (NOACK) - No Acknowledge - If set, indicates that no acknowledge was received for the previous
frame. Will be set only if HBAEN is set and no acknowledge is received prior to the end of the IFS.
NOACK is not set following a broadcast or a multicast packet.
TSTAT.7 (LNI) - Line Idle - If set, indicates the receive line is idle. In SDLC protocol it is set if 15 consecutive ones are received. In CSMA/CD protocol, line
idle is set if no transitions occur on GR X D for 1.6 bit
times after a required transition. LNI is cleared after a
transition on GRXD.
TxC - External Clock input for GSC transmitter.
UR - Underrun flag, see TSTAT.
XRCLK - External GSC Receive Clock Enable bit, see
peON.
XTCLK - External GSC Transmit Clock Enable bit,
seeGMOD.

MCS® . . 51 Programmer's Guide
and Instruction Set

9

MCS®-S1 PROGRAMMER'S GUIDE
AND INSTRUCTION SET
The information presented in this chapter is collected from the previous MCS®-51 chapters of this book. The
material has been selected and rearranged to form a quick and convenient reference for the programmers of the
MCS-51. This guide pertains specifically to the 8051, 8052 and 80C51.
The following list should make it easier to find a subject in this chapter.
Memory Organization
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-2
Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-3
Direct and Indirect Address Area ........................................................ 9-5
Special Function Registers ............... ................................................. 9-7
Contents of SFRs after Power-On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-8
SFR Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-9
Program Status Word (PSW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-10
Power Control Register (PCON) . . :. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. 9-10
Interrupts. . .. .. . .. .. .. . ... .. . . .. .. . .. .. .. . . . . . . . .. . ... .. . . .. .. .. .. . .. .. . . . .. .. .. ... . . . ... 9-11
Interrupt Enable Register (IE) ............................................................. : 9-11
Assigning Priority Level .......................... "......................................... 9-12
Interrupt Priority Register . ..................................................... , .. ... . . . . .. 9-12
Timer/Counter Control Register (TCON) ................................................... 9-13
Timer/Counter Mode Control Register {TMOD} ............................................. 9-13
Timer Set-Up . ....................... ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-14
Timer/Counter 0 .............................................. ...... ; ................... 9-14
Timer/Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-15
Timer/Counter 2 Control Register (T2CON). . . ... .. . . .. .. .. .. .. . . . . .. .. . .. .. . .. .. .. ... ...... 9-16
Timer/Counter 2 Set-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-17
Serial Port Control Register. . . . . . .. .... . . . . . . .. .. .. . . .. .. .. .. .. . . .. . . . .... . .. .. . . ... ... ... 9-18
Serial Port Set-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-18
Generating Baud Rates ................................................................... 9-19
MCS-51 Instruction Set . ...... "................ ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-20
Instruction Definitions .................................................................... 9-24

9-1

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MEMORY ORGANIZATION
PROGRAM MEMORY
The 8051 has separate address spaces for Program Memory and Data Memory. The Program Memory can be up to
64K bytes long. The lower 4K (8K for the 8052) may reside on-chip.
Figure I shows a map of the 8051 program memory, and Figure 2 shows a map of the 8052 program memory.
FFFF r - - - - - - - - - - - . ,

"FFr-----------~

&OK
BYTES

EXTERNAL
-OR

14K
BYTES

EXTERNAL

1~~---------~
AND
4KBYTES

INTERNAL
0000 ~---------~

270249-1

Figure 1. The 8051 Program Memory

9-2

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

FFFF , - - - - - - - - - - -....

FFFF,-----------~

56 K
BYTES

EXTERNAL
64K
BYTES

--OR-.....,.....

EXTERNAL

~~--------------~
AND
1 F F F r - - - - - - - - - - -....
8KBYTES

INTERNAL

~L-----------------~

0000

L-_________

..J

270249-2

Figure 2. The 8052 Program Memory

Data Memory:
The 8051 can address up to 64K bytes of Data Memory to the chip. The "MOVX" instruction is used to access the
external data memory. (Refer to the MeS-51 Instruction Set, in this chapter, for detailed description of instructions).
The 8051 has 128 bytes of on-chip RAM (256 bytes in the 8052) plus a number of Special Function Registers (SFRs).
The lower 128 bytes of RAM can be accessed either by direct addressing (MOV data addr) or by indirect addressing
(MOV @Ri). Figure 3 shows the 8051 and the 8052 Data Memory organization.

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

OFFFr------------------,

INTERNAL

FF..-------------,
SFR.

84K
BYTES
EXTERNAL

DIRECT
ADDRESSING
ONLY

~~--------~
7F

- - AND

-----l.,..

DIRECT.
INDIRECT
ADDRESSING

oo~--------~

ooooL-------------~
270249-3

Figure 3a. The 8051 Data Memory

FFFFr--------------------,
INTERNAL

f

INDIRECT
ADDRESSING ONLY

1,---1------, '"
~HTOFFH

FF

FF..---=-~------......,

84K
SFR.
DIRECT
ADDRESSING
ONLY

BYTES
EXTERNAL

1--AND . . . . . . .

~

7Fr--------------------i
DIRECT.
INDIRECT
ADDRESSING

oo~--------~

J

270249-4

Figure 3b. The 8052 Data Memory

9·4'

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

INDIRECT ADDRESS AREA:
Note that in Figure 3b the SFRs and the indirect address RAM have the same addresses (80H-OFFH). Nevertheless, they are two separate areas and are accessed in two different ways.
For example the instruction
MOV

80H,#OAAH

writes OAAH to Port 0 which is one of the SFRs and the instruction
MOV

RO,#80H

MOV

@RO,#OBBH

writes OBBH in location 80H of the data RAM. Thus, after execution of both of the above instructions Port 0 will
contain OAAH and location 80 of the RAM will contain OBBH.

DIRECT AND INDIRECT ADDRESS AREA:
The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments
as listed below and shown in Figure 4.
1. Register Banks 0-3: Locations 0 through IFH (32 bytes). ASM-51 and the device after reset default to register
bank O. To use the other register banks the user must select them in the software (refer to the MeS-5l Micro
Assembler User's Guide); Each register bank contains 8 one-byte registers, 0 through 7.
Reset initializes the Stack Pointer to location 07H and it is incremented once to start from location 08H which is the
first register (RO) of the second register bank. Thus, in order to use more'than one register bank, the SP should be
intialized to a different location of the RAM where it is not used for data storage (ie, higher part of the RAM).
2. Bit Addressable Area: 16 bytes have been assigned for this segment, 20H-2FH. Each one of the 128 bits of this
'
segment can be directly, addressed (0-7FH).
The bits can be referred to in two ways both of which are acceptable by the ASM-51. One way is'to refer to their
addresses, ie. 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0-7 can also be referred to
as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7 and so on.
'
Each of the 16 bytes in this segment can also be addressed as a byte.
3. Scratch Pad Area: Bytes 30H through 7FH are available to the user as data RAM. However, if ~he stack pointer
has been initialized to this area, enough number of bytes should be left aside to prevent SP data destruction.

9-5

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Figure 4 shows the different segments of the on-chip RAM.

II-------8BylW

11.......

- - - - - - - 1...1

78

7F

70

77

88

6F

60

67

58

5F

50

57

48

4F

40

47

SCRATCH
PAD

,

38

3F

30

37

... 7F

28
20

AREA

O•••

2F

BIT
ADDRESSABLE
SEGMENT
27

18

3

1F

10

2

17

REGISTER

08

1

OF

BANKS

0

07
270249:"5

Figure 4. ·128 Bytes of RAM Direct and Indirect Addressable

9-6

infef

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

SPECIAL FUNCTION REGISTERS:
Table 1 contains a list of all the SFRs and their addresses.
Comparing Table 1 and Figure 5 shows that all of the SFRs that are byte and bit addressable are located on the first
column of the diagram in Figure 5.
Table 1
Symbol
'ACC
'B
'PSW
SP
DPTR
DPL
DPH
*PO
*P1
*P2
'P3
*IP
'IE
TMOD
*TCON
'+ T2CON
THO
TLO
TH1
TL1
+TH2
+ TL2
+ RCAP2H
+ RCAP2L
'SCON
SBUF
PCON

Name
Accumulator
B Register
Program Status Word
Stack Pointer
Data Pointer 2 Bytes
Low Byte
High Byte
PortO
Port 1
Port 2
Port 3
Interrupt Priority Control
Interrupt Enable Control
Timer/Counter Mode Control
Timer/Counter Control
Timer/Counter 2 Control
Timer/Counter 0 High Byte
Timer/Counter 0 Low Byte
Timer/Counter 1 High Byte
Timer/Counter 1. Low Byte
Timer/Counter 2 High Byte
Timer/Counter 2 Low Byte
T /C 2 Capture Reg. High Byte
T /C 2 Capture Reg. Low Byte
Serial Control
Serial Data Buffer
Power Control

addressable
8052 only

• = Bit

+

=

9-7

Address
OEOH
OFOH
ODOH
B1H
B2H
B3H
BOH
90H
OAOH
OBOH
OBBH
OA8H
89H
B8H
OC8H
8CH
8AH
BDH
BBH
OCDH
OCCH
OCBH
OCAH
98H
99H
B7H

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

WHAT DO THE SFRs CONTAIN JUST AFTER POWER-ON OR A RESET?
Table -2 li$ts the contents of each SFR after power-on or a hardware reset.
Table 2. Contents of the SFRs after reset '
Register

Value in Binary

00000000
00000000
00000000
00000111

°ACC
oS
°pSW
Sp
DPTR
DPH
DPL
'PO
'P1
'P2
'P3
"P

00000000
00000000
11111111
11111111
11111111
11111111
8051 XXXOOOOO,
8052 XXOOOOOO
80510XXOOOOO,
8052 OXOOOOOO
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

'IE

TMOD
'TCON
*+ T2CON
THO
TLO
TH1
TL1
+TH2
+TL2
+ RCAP2H
+ RCAP2L
'SCON
SBUF
PCON

x

Indeterminate

HMOS OXXXXXXX
CHMOS OXXXOOOO

= Undefined

• = Bit Addressable
+ = 8052on!y

9-8

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

SFR MEMORY MAP
8 Bytes

FB
FO
EB
EO
DB
DO
CB
CO
BB
BO
AB
AO
98
90
B8

BO

FF
B

F7

EF
ACC

E7

DF
PSW
T2CON

D7

RCAP2L

RCAP2H

TL2

TH2

CF
C7

IP
P3
IE
P2
SCON
P1
TCON
PO

t

BF
B7

AF
A7

SBUF

9F
97

TMOD
SP

TLO
DPL

TL1
DPH
Figure 5

Bit
Addressable

9-9

THO

TH1

BF
PCON

B7

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Those SFRs that have their bits assigned for various functions are listed in this section. A brief description of each bit
is provided for quick reference. For more detailed information refer to the Architecture Chapter of this book.

PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.

CY

AC
PSW.7
PSW.6

CY
AC
FO
RSI
RSO
OV

psw.s
PSW.4
PSW.3
PSW.2
PSW.I

psw.o

P

FO

RS1

RSO

P

OV

Carry Flag.
Auxiliary Carry Flag.
Flag 0 available to the user for general purpose.
Register Bank selector bit I (SEE NOTE I).
Register Bank selector bit 0 (SEE NOTE I).
Overflow Flag.
Not implemented, reserved for future use.'
Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of
'I' bits in the accumulator.
.

NOTE:
1. The value presented by RSO and RS1 selects the corresponding register bank.

RS1

RSO

Register Bank

Address

0
1
0
1

0
1
2
3

OOH-07H
OBH-OFH
10H-17H
1BH-1FH

0
0
1
1

'User software should not write 1s to reserved bits. These bits may be used in future MCS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.

PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.
SMOO

I _. I

GF1

GFO

PO

IOL

SMOD Double baud rate bit. If Timer I is used to generate baud rate and SMOD = I, the baud rate is doubled
when the Serial Port is used in modes I, 2, or 3.
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
GFI
General purpose flag bit.
GFO
General purpose flag bit.
PD
Power Down bit. Setting this bit activates Power Down operation in the 80CSIBH. (Available only in
CHMOS).
IDL
Idle Mode bit. Setting this bit activates Idle Mode operation in the 80CSIBH. (Available only in CHMOS).
If Is are written to PD and IDL at the same time, PD takes precedence.
'User software should not write 1s to reserved bits. These bits may be used in future MCS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.

9-10

infef

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

INTERRUPTS:
In order to use any of the interrupts in the MCS-SI, the following three steps must be taken.
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the corresponding individual interrupt enable bit in the IE register to 1.
3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See Table below.
Interrupt
Source

Vector
Address

lEO
TFO
IE1
TF1
RI&TI
TF2 & EXF2

0003H
OOOBH
0013H
001BH
0023H
002BH

In addition, for external interrupts, pins INTO and INTI (P3.2 and P3.3) must be set to I, and depending on whether
the interrupt is to be level or transition activated, bits ITO or ITI in the TCON register may need to be set to 1.
ITx = 0 level activated
ITx = 1 transition activated

IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled.

EA

ET2

EA

IE.7

ET2
ES
ETI
EXI
ETO
EXO

IE.6
IE.S
IE.4
IE.3
IE.2
IE. 1
IE.O

ES

ET1

EX1

ETO

EXO

Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
Not implemented, reserved for future use.·
Enable or disable the Timer 2 overflow or capture interrupt (80S2 only).
Enable or disable the serial port interrupt.
Enable or disable the Timer I overflow interrupt.
Enable or disable External Interrupt 1.
Enable or disable the Timer 0 overflow interrupt.
Enable or disable External Interrupt O.

·User software should not write Is to reserved bits. These bits may be used in future MCS-SI products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.

9-11

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:
In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1.
Remember"that while an interrupt service is in progress, it cannot be interrupted tJy a lower or same level interrupt.

PRIORITY WITHIN LEVEL:
Priority within level is only to resolve simultaneous requests of the same priority level.
From high to low, interrupt sources are listed below:
lEO
TFO
lEI
TFI
RI or TI
TF2 or EXF2

IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a
higher priority.

I
PT2
PS
PTl
PXl
PTO
PXO

PT2

IP. 7
IP.6
IP.S
IP.4
"IP. 3
IP.2
IP. 1
IP. 0

PS

PT1

PX1

PTO

PXO

Not implemented, reserved for future use.·
Not implemented, reserved for future use.'
Defines the Timer 2 interrupt priority level (8052 only).
Defines the" Serial Port interrupt priority level.
Defines the Timer 1 interrupt priority level.
Defines External Interrupt 1 priority level.
Defines the" Timer 0 interrupt priority level.
Defines th~ External Interrupt 0 priority level.

'User software should'not 'write Is to reserved bits. These bits may be used in future MeS-51 products to invoke
new features. In that case, 'the reset or inactive value of the new bit will be 0, and its active value will be 1.

•

:.0\

9-12

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

TeON: TIMER/COUNTER CONTROL REGISTER. BIT ADDRESSABLE.
TF1

TFI

TR1

TRI
TFO

TCON. 7
.
TCON.6
TCON. 5

TRO
lEI

TCON. 4
TCON. 3

IT!

TCON. 2

lEO

TCON. 1

ITO

TCON. 0

TFO

TRO

IE1

IT1

lEO

ITO

Timer I overflow flag. Set by hardware when the Timer/Counter I overflows. Cleared by hardware as processor vectors to the interrupt service routine.
Timer I run control bit. Set/cleared by software to turn Timer/Counter ION/OFF.
Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the service routine.
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF.
External Interrupt I edge flag. Set by hardware when External Interrupt edge is detected.
Cleared by hardware when interrupt is processed.
Interrupt I type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared
by hardware when interrupt is processed.
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.

TMOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT
ADDRESSABLE.

I\: GATE
GATE

ciT
MI
MO

CIT

M1

MO

I

GATE

CIT

)\:

M1

MO
)

I

TIMER 1
TIMER 0
When TRx (in TCON) is set and GATE = I, TIMER/COUNTERx will run only while INTx pili is high
(hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = I (software
control).
Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin).
Mode selector bit. (NOTE 1)
Mode selector bit. (NOTE 1)

NOTE 1:

M1

MO

o

o

o

1

o
1

Operating Mode
o
13-bit Timer (MCS-48 compatible)
1
16-bit Timer/Counter
2
8-bit Auto-Reload TimerlCounter
(Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0
3
control bits, THO is an 8-bit Timer and is controlled by Timer 1 control bits.
(Timer 1) Timer/Counter 1 stopped.
3

9-13

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

TIMER SET·UP
Tables 3 through 6 give some values for TMOD which can be used to set up Timer 0 in different modes.
It is assumed that only one timer is being used at a time. If it is desired to run Timers 0 and 1 simultaneously, in any
mode, the value in TMOD for Timer 0 must be ORed .with the value shown for Timer 1 (Tables 5 and 6).

For example, if it is desired to run Timer 0 in mode 1 GATE (external control), and Timer 1 in mode 2 COUNTER,
then the value that must be loaded into TMoD is 69H (09H from Table 3 ORed with 60H from Table 6).
Moreover, it'is assumed that the user, at this point,. is not ready to tum the timers on and will do that at a different
point in the program by setting bit TRx (in TCON) to 1.

TIMER/COUNTER 0

As a Timer:
Table 3
TMOD
MODE

TIMER 0
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

0
1
2
3

13-bit Timer
16-bit Timer
8-bit Auto-Reload
two 8-bit Timers

OOH
01H
02H
03H

08H
09H
OAH
OSH

As a Counter:
Table 4
TMOD
MODE

COUNTER 0
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

0
1
2
3

13-bit Timer
16-bit Timer
8-bit Auto-Reload
one 8-bit Counter

04H
05H
OSH
07H

OCH
ODH

OEH
OFH

NOTES:

1. The Timer is turned ON/OFF by setting/clearing bit TRO in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INTO (P3.2) when TRO = 1
(hardware control).

9-14

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

TIMER/COUNTER 1
As a Timer:
TableS
TMOD
MODE

TIMER 1
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

0
1
2
3

13-bit Timer
16-bit Timer
B-bit Auto-Reload
does not run

OOH
10H
20H
30H

BOH
90H
AOH
BOH

As a Counter:

TableS
TMOD

MODE

0
.1

2

3

COUNTER 1
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

13-bit Timer
16-bit Timer
B-bit Auto-Reload
not available

40H
50H
60H

COH
DOH
EOH

-

-

NOTES:

1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1 (P3.3) when TR1 = 1
(hardware control).

9-15

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

T2CON: TIMER/COUNTER 2 CONTROL REGISTER. BIT ADDRESSABLE
8052 Only
1 TF2 1 EXF2

RCLK

TCLK

.1

EXEN2

TR2

TF2

C/T2.1 CP/RL2

T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when
.
either RCLK = I or CLK = I
EXF2
T2CON. 6 Timer 2 externa!. flag set when either a capture or reload is caused by a negative transition on
T2EX, and EXEN2= 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK
nCON. 5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
receive clock in modes I & 3. RCLK = 0 causes Timer I overflow to be used for the receive
clock.
TLCK
T2CON. 4 Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
transmit clock in modes I & 3. TCLK = 0 causes Timer I overflows to be used for the
transmit clock.
EXEN2 T2CON. 3 Timer 2 external enable flag. When set,' allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2 Software START/STOP control for. Timer 2. A logic I starts the Timer.
C/T2
T2CON. 1 Timer or Counter select.
o = Internal Timer. I = External Event Counter (falling edge triggered).
CP/RL2 T2CON.O Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, Auto-Reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when' EXEN2 = 1. When either RCLK = 1 or TCLK = I,
this bit is ignored and the Timer is forced to Auto-Reload on Timer 2 overflow.

9-16

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

TIMER/COUNTER 2 SET-UP
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit.
Therefore, bit TR2 must be set, separately, to turn the Timer on.

As a Timer:
Table 7
T2CON
MODE

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

16-bit Aulo-Reload

OOH

OSH

16-bit Capture

01H

09H

BAUD rate generator receive &
transmit same baud rate

34H

36H

receive only

24H

26H

transmit only

14H

16H

As a Counter:
TableS
TMOD
MODE

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

16-bit Auto-Reload
16-bit Capture

02H
03H

OAH
OBH

NOTES:
1. Capture/Reload occurs only on Timer/Counter overflow.
2. Capture/Reload occurs on Timer/Counter overflow and a 1 to 0 transition on T2EX
(P1.1) pin except when Timer 2 is used in the baud rate generating mode.

9-17

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

SCON: SERIAL PORT CONTROL REGISTER. BIT ADDRESSABLE.

I

SMO

SM1

SM2

REN

TB8

RB8

TI

RI

SMO
SMI
SM2

SCON.7 Serial Port mode specifier. (NOTE 1).
SCON. 6 Serial Port mode specifier. (NOTE 1).
SCON.5 Enables the multiprocessor communication feature in modes 2 & 3. In mode 2 or 3, ifSM2 is set
to 1 then RI will not be activated if the received 9th data bit (RB8) is O. In mode I, if SM2 = 1
then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be O.
(See Table 9).
.

REN
TB8
RB8

SCON. 4 Set/Cleared by software to Enable/Disable reception.
SCON. 3 The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software.
SCON. 2. In modes 2 & 3, is the 9th data bit that was received. In mode 1, ifSM2 = 0, RB8 is the stop bit
that was received. In mode 0, RB8 is not used.
. .
SCON. 1 Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the
beginning of the stop bit in the other modes. Must be cleared by software.
SCON. 0 Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway
through the stop bit time in the other modes (except see SM2). Must be cleared by software.

TI
RI
NOTE 1:

SMO

SM1

Mode

Description

Baud Rate

o
o

0
1
0

0
1
2

SHIFT REGISTER
8-Bit UART
9-Bit UART

3

9-Bit UART

Fo.sc.l12
Variable
Fosc.l64 OR
Fosc.l32
Variable

1

SERIAL PORT SET·UP:
Table 9
MODE

SCON

5M2 VARIATION

0
1
2
3

10H
50H
90H
DOH

Single Processor
Environment
(SM2 = 0)

0

NA
70H
BOH
FOH

Multiprocessor
EnVironment
(SM2 = 1)

•
I

2
3

GENERATING BAUD RATES
Serial Port in Mode 0:
Mode 0 has a fixed baud rate which is 1/12 of the oscillator frequency. To run the serial port in this mode none of
the Timer/Counters need to be set up. Only the SCON register needs to be defined.
Osc Freq
Baud Rate = - - 12

Serial Port in Mode 1:
Mode 1 has a variable baud rate. The baud rate can be generated by either Timer 1 or Timer 2 (8052 only).
9-18

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

USING TIMER/COUNTER 1 TO GENERATE BAUD RATES:
For this purpose, Timer 1 is used in mode 2 (Auto-Reload). Refer to Timer Setup section of this chapter.
B d R te =
K x Oscillator Freq.
au
a
32 x 12 x [256 - (TH111

If SMOD = 0, then K = 1.
If SMOD = I, then K = 2. (SMOD is the PCON register).
Most of the time the user knows the baud rate and needs to know the reload value for THI.
Therefore, the equation to calculate THI can be written as:
TH1 = 256 _ K x Ose Freq.
384 x baud rate

THI must be an integer value. Rounding off THI to the nearest integer may not produce the desired baud rate. In
this case, the user may have to choose another crystal frequency.
Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register. (ie, ORL
PCON,#80H). The address of PCON is 87H.

USING TIMER/COUNTER 2 TO GENERATE BAUD RATES:
For this purpose, Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this
chapter. If Timer 2 is being clocked through pin T2 (PI.O) the baud rate is:
Timer 2 Overflow Rate
B d
au Rate =
16

And if it is being clocked internally the baud rate is:
Osc Freq
Baud Rate = 32 x [65536 - (RCAP2H, RCAP2L))

To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as:
. RCAP2H, RCAP2L = 65536 - 3 O~c F~e~
2x au
ate

SERIAL PORT IN MODE 2:
The baud rate is fixed in this mode and is
bit in the PCON register.

Va. or '1.4 of the oscillator frequency depending on the value of the SMOD

In this mode none of the Timers are used and the clock
SMOD = I, Baud Rate =
SMOD

Va.

co~es

from the internal phase 2 clock.

Osc Freq.

= 0, Baud Rate = '1.4 Osc Freq.

To set the SMOD bit: ORL

PCON, # 80H. The address of PCON is 87H.

SERIAL PORT IN MODE 3:
The baud rate in mode 3 is variable and sets up exactly the same as in mode 1.

9-19

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MCS®-S1 INSTRUCTION SET
Table 10.8051 Instruction Set Summary
Interrupt Response Time: Refer to Hardware Description Chapter.

Mnemonic'

ARITHMETIC OPERATIONS
ADD
A,Rn
Add register to
Accumulator
A,direct Add direct byte to
ADD
Accumulator
A,@Ri
Add indirect RAM
ADD
to Accumulator
A,#data Add immediate
ADD
data to
Accumulator
Add register to
AD DC A,Rn
Accumulator
with Carry
ADDC A,direct Add direct byte to
Accumulator'
with Carry
ADDC A,@Ri
Add indirect
RAM to
Accumulator
with Carry
ADDC A,#data Add immediate
data toAcc
with Carry
SUBB A,Rn
Subtract Register
from Acc with
borrow
SUBB A,direct Subtract direct
byte from Acc
with borrow
SUBB A,@Ri
Subtract indirect
RAMfromACC
with borrow
SUBB .A,#data Subtract
immediate data
from Acc with
borrow

Instructions that Affect Flag Settings(1)
Instruction
ADD
ADDC
SUBB
MUl
DIV
DA
RRC
RlC
SETBC

C
X
X
X
0
0
X
X
X

Flag
OV
X
X
X
X
X

Instruction
AC
X ClRC
X CPlC
X ANlC,bit
ANlC,/bit
ORlC,bit
ORlC,bit
MOVC,bit
CJNE
/

Description

Flag
C OV AC
0
X
X
X
X
X
X
X

(I)Note that operations on SFR byte address 208 or
bit addresses 209-215 (i.e., the PSW or bits in the
PSW) will also affect flag settings.
Note on instruction set and ad,dressing modes:
- Register R7-RO of the currently seRn
lected Register Bank..
direct
- 8-bit- internal data location's address.
This could be an Internal Data RAM
location (0-127) or a SFR [i.e., I/O
port, control register, status register,
etc. (128-255)J.
@Ri
- 8-bit internal data RAM location (0255) addressed indirectly through register Rl orRO.
#data
- 8-bit constant included in instruction.
#data 16 - 16-bit constant included in instruction.
addr 16 - 16-bit destination address. Used by
LCALL & LJMP. A branch ,can be
anywhere within the 64K-byte Program Memory address space.
addr 11 - II-bit destination address. Used by
ACALL & AJMP. The branch will be
within the same 2K-byte page of program memory as the first byte of the
following instruction.
rei
- Signed (two's complement) 8-bit offset
byte. Used by SJMP and all conditional jumps. Range is -128 to + 127
bytes relative to first byte of the following instruction.
- Direct Addressed bit in Internal Data
bit
RAM or Special Function Register.
-New operation not provided by
8048AH/8049AH.

Byte

Oscillator
Period

12
2

12
12

2

12
12

2

12
12

'2

12
12

2

12
12

2

12

increment
12
Accumulator
INC
Rn
Increment register
12
INC
direct
Increment direct
2
12
byte
@Ri
INC
Increment direct
12
RAM
DEC
A
Decrement
12
Accumulator
DEC
Rn
Decrement
12
Register
DEC
direct
Decrement direct
2
12
byte
DEC . @Ri
Decrement
12
indirect RAM
All mnemonics copyrighted @Intel Corporation 1980

iNC

9-20

A

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Table 10. 8051 Instruction Set Summary (Continued)
Mnemonic

Description

Byte

ARITHMETIC OPERATIONS (Continued)
Increment Data
INC DPTR
Pointer
Multiply A & B
MUL AB
Divide A by B
DIV AB
DA
A
Decimal Adjust
Accumulator
LOGICAL OPERATIONS
ANL A,Rn
AND Register to
Accumulator
ANL A,direct
AND direct byte
to Accumulator
AND indirect
ANL A,@Ri
RAM to
Accumulator
AND immediate
ANL A,#data
data to
Accumulator
ANL direct,A
AND Accumulator
to direct byte
ANL direct, # data AND immediate
data to direct byte
OR register to
ORL A,Rn
Accumulator
ORL A,direct
OR direct byte to
Accumulator
ORL A,@Ri
OR indirect RAM
to Accumulator
ORL A,#data
OR immediate
data to
Accumulator
ORL direct,A
OR Accumulator
to direct by1e
ORL direct, # data OR immediate
data to direct byte
XRL A,Rn
Exclusive·OR
register to
Accumulator
Exciusive·OR
XRL A,direct
direct byte to
Accumulator
Exciusive·OR
XRL A,@Ri
indirect RAM to
Accumulator
Exciusive·OR
XRL A,#data
immediate data to
Accumulator
Exclusive·OR
XRL direct,A
Accumulator to
direct byte
XRL direct, # data Exclusive·OR
immediate data
to direct byte
Clear
CLR A
Accumulator
CPL A
Complement
Accumulator

Oscillator
Period

Mnemonic

LOGICAL OPERATIONS (Continued)
Rotate
RL
A
Accumulator Left
Rotate
RLC
A
Accumulator Left
through the Carry
Rotate
RR
A
Accumulator
Right
Rotate
RRC
A
Accumulator
Right through
the Carry
Swap nibbles
SWAP A
within the
Accumulator
DATA TRANSFER
Move
MOV A,Rn
register to
Accumulator
MOV A,direct
Move direct
byte to
Accumulator
MOV A,@Ri
Move indirect
RAM to
Accumulator
Move
MOV A,#data
immediate
data to
Accumulator
MOV Rn,A
Move
Accumulator
to register
Move direct
MOV Rn,direct
byte to
register
Move
MOV Rn,#data
immediate data
to register
Move
MOV direct,A
Accumulator
to direct by1e
Move register
MOV direct,Rn
to direct by1e
MOV direct, direct Move direct
byte to direct
Move indirect
MOV direct,@Ri
RAM to
direct byte
MOV direct, # data Move
immediate data
to direct byte
Move
MOV @Ri,A
Accumulator to
indirect RAM

24
48
48
12

12
2

12
12

2

12

2

12

3

24
12

2

12
12

2

12

2

12

3

24
12

2

12

12

2

12

2

12

3

24

Description

12
12

Byte

Oscillator
Period
12
12

12

12

12

12

2

12

12

2

12

12

2

24

2

12

2

12

2

24

3

24

2

24

3

24

12

All mnemonics copyrighted ® Intel Corporation 1980

9-21

inter

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Table 10.8051 Instruction Set Summary (Continued)
Mnemonic

Description

Byte

Oscillator
Period

2

24

2

12

3

24

Mnemonic

DATA TRANSFER (Continued)
Move direct
byte'to '
indirect RAM
Move
MOV @Ri,#data
immediate
data to
indirect RAM
MOV DPTR,#dataI6 Load Data
Pointer with a
16-bit constant
MOVC A,@A+DPTR
Move Code
byte relative to
DPTRtoAcc
MOVC A,@A+PC
Move Code
byte relative to
PC to Acc
MOVX A,@Ri
Move
External
RAM (8-bit
addr) toAcc
MOVX A,@DPTR
Move
External
, RAM (16-bit
addr) toAcc
MOVX @Ri,A
Move Acc to
External RAM
(8-bit addr)
MOVX @DPTR,A
Move Accto
External RAM
(16-bit addr)
PUSH direct
Push direct
byte onto
MOV

@Ri,direct

XCH

XCH

XCH

direct

A,Rn

A,direct

A,@Ri

XCHD A,@Ri

Pop direct
byte from
stack
Exchange
register with
Accumulator
Exchange
direct byte
with
Accumulator
Exchange ,
indirect RAM
with
Accumulator
Exchange loworder Digit
indirect RAM
withAcc

Byte

Oscillator
Period

BOOLEAN VARIABLE MANIPULATION
CLR
CLR
SETB
SETB
CPL

C
bit
C
bit
C

CPL

bit

ANL

C,bit

24

ANL

C,/bit

24

ORL

C,bit

ORL

C,/bit

MOV

C,bit

MOV

bit,C

JC

rei

JNC

rei

JB

bit,rel

JNB

bit,rel

JBC

, bit,rel

24

24

24

24

2

24

2

24

stac~

POP

Description

1
2
1
2

12
12
12
12
12

2

12

2

24

2

24

2

24

2

24

2

12

2

24

2

24

2

24

3

24

3

24

3

24

2

24

3

24

PROGRAM BRANCHING
ACALL

addrll

LCALL

addr16

12

2

Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement
Carry
Complement
direct bit
AND direct bit
to CARRY
AND complement
of direct bit
to Carry
OR direct bit
to Carry
OR complement
of direct bit
to Carry
Move direct bit
to Carry
Move Carry to
direct bit
Jump if Carry
is set
Jump if Carry
not set
Jump if direct
Bit is set
Jump if direct
Bit is Not set
Jump if direct
Bit is set &
clear bit

12
RET
RETI
12

12

AJMP

addrll

LJMP
SJMP

addr16
rei

Absolute
Subroutine
Call
Long
Subroutine
Call
Return from
Subroutine
Return from
interrupt
Absolute
Jump
Long Jump
Short Jump
(relative addr)

24
24
2

24

3

24
24

2

All mnemonics copyrighted ©Intel Corporation 1980

9-22

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Table 10.8051 Instruction Set Summary (Continued)
Mnemonic

Description

PROGRAM BRANCHING (Continued)
@A+DPTR Jump indirect
JMP
relative to the
DPTR
JZ
rei
Jump if
Accumulator
is Zero
JNZ
rei
Jump if
Accumulator
is Not Zero
CJNE A,direct,rel
Compare
direct byte to
Acc and Jump
if Not Equal
CJNE A,#data,rel Compare
immediate to
Acc and Jump
if Not Equal

Byte

Oscillator
Period

Mnemonic

PROGRAM BRANCHING (Continued)
Compare
CJNE Rn, # data,rel
immediate to
register and
·JumpifNot
Equal
CJNE @Ri,#data,rel Compare
immediate to
indirect and
Jump if Not
Equal
DJNZ Rn,rel
Decrement
register and
Jump if Not
Zero
Decrement
DJNZ direct,rel
direct byte
and Jump if
Not Zero
NOP
No Operation

24

2

24

2

24

3

24

3

Description

24

Byte

Oscillator
Period

3

24

3

24

2

24

3

24

12

All mnemonics copyrighted @lIntel Corporation 1980

9-23

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

INSTRUCTION DEFINITIONS
ACALL

addr11

Function:

Absolute Call

Description:

ACALL unconditionally calls a subroutine located at the indicated address. The instruction
increments the PC twice to obtain the address of the following instruction, then pushes the
I6-bit result onto the,stack (low-order byte first) and increments the Stack Pointer twice. The
destination address is obtained by successively concatenating the, five high-order bits of the
incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called
must therefore start within the same 2K block of the program memory as the first byte of the
instruction following ACALL. No flags are affected.

Example:

Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345 H. After
executing the instruction,
ACALL SUBRTN '
at location OI23H, SP will contain 09H, internal RAM locations OSH and 09H will contain
25H and OIH, respectively, and the PC will contain 0345H.

Bytes:

2

Cycles:

2

Encoding:
Operation:

I a10 a9 a8 1

0 0 0

11

a7 a6 a5 a4

ACALL
(PC) - (PC) + 2
(SP) - (SP) + 1
«SP» - (PC7-O)
(SP) - (SP) + 1
«SP» - (PCIS-S)
(PCw_o) - page address

9-24

a3' a2 a1 aO

inter
ADD

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A, < src-byte >
Function:

Description:

Add
ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or
bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an
overflow occured..
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6;
otherwise OV is cleared. When adding signed integers, OV indicates a negative number pro-

duced as the sum of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
Example:

The Accumulator holds OC3H (llOOOO1IB) and register 0 holds OAAH (10 10 10 lOB). The
instruction,
ADD

A,RO

will leave 6DH (01 101 101B) in the Accumulator with the AC flag cleared and both the carry
flag and OV set to I.
ADD

A,Rn
Bytes:
Cycles:

ADD

Encoding:

I0

Operation:

ADD
(A) ~ (A)

o

1 r r r

1 0

+

(Rn)

A,direct
Bytes:

2

Cycles:
Encoding:

I0

Operation:

ADD
(A) ~ (A)

010

o1
+

0 1

direct address

(direct)

9-25

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

ADD A,@RI
Bytes:
Cycles:
Encoding:

100 1 0

Operation:

ADD
(A) -

(A)

011

+ «R0)

ADD A,#data
Bytes:

2

Cycles:
Encoding:

1 00 1 0

Operation:

ADD
(A)-(A)

o1 0
+

0

immediate data

# data

ADDC A, 
Function:
Description:

Add with Carry
ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator
contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set,
respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding
unsigned integers, the carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out ofbit.7 but not out of
bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number
produced as the sum of two positive operands or a positive sum from two negative operands.

Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.

Example:

The Accumulatpr holds OC3H (1 100001 IB) and register 0 holds OAAH (lOlOlOlOB) with the
carry flag set. The instruction,
ADDC

A,RO

will leave 6EH (01101 1lOB) in the Accumulator with AC cleared and both the Carry flag and
OV set to 1.
.

9-26

inter
ADDC

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,Rn
Bytes:
Cycles:

Encoding:

1,--0_O_l_-,--_l_r_r_r--l1

Operation:

ADDC
(A) ~ (A)

+

(C)

+ (Rn)

AD DC A,direct
Bytes:

2

Cycles:
Encoding:
Operation:

ADDC

L..1_o_o_1_~0_1_0_1-,
ADDC
(A) ~ (A)

+

(C)

+

direct address

(direct)

A,@Ri
Bytes:
Cycles:

Encoding:

10 0 1 1

Operation:

ADDC
(A) ~ (A)

0 1 1 i

+

(C)

+

«Ri»

AD DC A,#data
Bytes:

2

Cycles:
Encoding:

1-1_0_0_1_-,--0_1_0_0-,

Operation:

ADDC
(A) ~ (A)

+

(C)

+

immediate data

#data

9-27

I

inter
AJMP

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

addr11
Function:

Description:

Example:·

Absolute Jump
AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits
7-5, and the second byte of the instruction. The destination must therefore be within the same
2K block of program memory as the first byte of the instruction following AJMP.
The label "JMPADR" is at program memory location 0123H. The instruction,
AJMP JMPADR
is at location 0345H and will load the PC with 0123H.

Bytes:

2

Cycles:

2

Encoding:
Operation:

ANL

I a10 a9 a8 0

0 0 0 1

a7 a6 a5 a4

a3 a2 a1 aO

AJMP
(PC) +- (PC) + 2
(PCIO-O) +- page address

< dest-byte > , < src-byte >
Function:

Description:

Logical-AND for byte variables
ANL performs the bitwise logical-AND operation between the variables indicated and stores
the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

If the Accumulator holds OC3H (110000 11 B) and register 0 holds 55H (OlOlOlOlB) then the
instruction,
"A...NL

LA..,RO

will leave 41H (OlOOOOOlB) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of
bits in any RAM location or hardware register. The mask byte determining the pattern of bits
to be cleared would either be a constant contained in the instruction or a value computed in
'
the Accumulator at run-time. The instruction,
ANL

Pl,#OlllOOllB

will clear bitS 7, 3, and 2 of output port 1.

9-28

intJ
ANL

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,Rn
Bytes:
Cycles:
Encoding:
Operation:

ANL

1 01

o1

1 r r r

ANL
(A) ~ (A) A (Rn)

A,direct
Bytes:

2

Cycles:
Encoding:

I0 1 o1

Operation:

ANL
(A)

ANL

~

o1

0 1

direct address

(A) A (direct)

A,@Ri
Bytes:
Cycles:
Encoding:

1 01

. Operation:

ANL
(A)

ANL

o1

~

o1

1

(A) A «Ri»

A, # data
Bytes:

2

Cycles:

ANL

o1

o10

Encoding:

1 01

Operation:

ANL
(A) ~ (A) A #data

0

immediate data

direct,A
Bytes:

2

Cycles:
Encoding:
Operation:

1 01

o1

ANL
(direct)

~

001 0

direct address

(direct) A (A)

9-29

inter
ANL

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

direct, # data
Bytes:

3

Cycles:

2

Encoding:
Operation:

ANL

Function:

.Example:

ANL

0 0 1 1

direct address

I

immediate data

ANL
(direct) +- (direct) " #data

C,

Description:

ANL

I 0 .1 0 1

Logical-AND for bit variables
If the Boolean value of the source bit is a logical 0 then clear the carry flag; otherwise leave the
carry flag in its current state. A slash ("/") preceding the operand in the assembly language
indicates that the logical complement of the addressed bit is used as the source value, but the
source bit itself is not affected. No other flags are affected.

Only direct addressing is allowed for the source operand.
Set the carry flag if, and only if, PI.O = 1, ACC. 7 = 1, and OV = 0:
MOV C,Pl.O

;LOAD CARRY WITH INPUT PIN STATE

ANL C,ACC.7

;AND CARRY WITH ACCUM. BIT 7

ANL C,/OV

;AND WITH INVERSE OF OVERFLOW FLAG

C,bit
Bytes:

2

Cycles:

2

Encoding:

11 000

Operation:

ANL
(C) +- (C) " (bit)

001 0

bit address

C,/bit
Bytes:

2

Cycles:

2

Encoding:

I1o1

Operation:

ANL
(C) +- (C) " I (bit)

0000

bit address

9-30

inter
CJNE

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

< dest-byte > , < src-byte > , rei
Function:

Description:

Compare and Jump if Not Equal.
CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
The carry flag is set if the unsigned integer value of  is less than the unsigned
integer value of ; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the Accumulator may be
compared with any directly addressed byte or immediate data, and any indirect RAM location
or working register can be compared with an immediate constant.

Example:

The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,
CJNE

R7,#60H, NOT_EQ
R7 = 60H.
IFR7 < 60H.
R7> 60H.

JC

sets the carry flag anc;l branches to the instruction at label NOT_EQ. By testing the carry flag,
this instruction determines whether R 7 is greater or less than 60H.
If the data being presented to Port I is also 34H, then the instruction,
WAIT:

CJNE A,PI,WAIT

clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the data read from Pl. (If some other value was being input on PI, the program
will loop at this point until the PI data changes to 34H.)
CJNE

A,direct,rel
Bytes:

3

Cycles:

2

Encoding:
Operation:

I1 0 1 1
(PC) IF (A)
THEN

0 1 0 1

(PC) + 3
(direct)

<>

(PC) IF (A)
THEN

direct address

<

(PC)

+ relative offset

(direct)

(C)-l
ELSE

(C)-O

9-31

reI. address

infef

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

CJNE A,#data,rel
Bytes:

3

Cycles:

2

Encoding:
Operation:

. 11 011

o1 0

0

immediate data

reI. address

(PC) - (PC) + 3
IF (A) < > data

THEN
(PC) -

(PC)

+

relative offset

IF (A) < data

THEN
(C)-l

ELSE
(C)-O

CJNE

Rn,#data,rel
Bytes:

3

Cycles:

2

Encoding:

110 1 1

1 r r r

Operation:

(PC) - (PC) + 3
IF (Rn) < > data

THEN
(PC) -

(PC)

immediate data

+

rei. address

relative offset

IF (Rn) < data

THEN"
(C)-l

ELSE
(C)-O

CJNE

@Ri,#data,rel
Bytes:

3

Cycles:

2

Encoding:

11 0 1 1

0 1 1

Operation:

(PC) IF

+

«Ri»

(PC)

3

< > data

THEN

(PC) -

IF

«Ri»

immediate data

(PC)

+

relative offset

< data

THEN

(C)-l

ELSE
(C)-O

9-32

rei. address

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

CLR

A
Function:

Description:
Example:

Clear Accumulator
The Accumulator is cleared (all bits set on zero). No flags are affected.
The Accumulator contains SCH (0101 I 100B). The instruction,
CLR

A

will leave the Accumulator set to OOH (OOOOOOOOB).
Bytes:
Cycles:
Encoding:

11

Operation:

CLR

1 1

0 1 0 0

(A)~O

CLR

bit
Function:

Description:
Example:

Clear bit
The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the
carry flag or any directly addressable bit.
Port I has previously. been written with SDH (OlOllIOIB). The instruction,
CLR

P1.2

will leave the port set to S9H (OIOIIOOIB).
CLR

C
Bytes:
Cycles:
Encoding:

11

Operation:

CLR

0 0

0 0 1 1

(C)~O

CLR

bit
Bytes:

2

Cycles:
Encoding:

1 1 1 0 0.1 0 0 1 0

Operation:

CLR
(bit) ~O

bit address

9-33

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

CPL A
Function:
Description:
Example:

Complement Accumulator

. Each bit of the Accumulator is logically complemented (one's complement). Bits which previously contained a one are changed to a zero and vice-versa. No flags are affected.
The Accumulator contains 5CH (01011100B). The instruction,
CPL A
will leave the Accumulator set to OA3H (10100011B).

Bytes:
Cycles:
Encoding:
Operation:

I1

1 1

0 1 0 0

CPL
(A) ..... -, (A)

CPL bit
Function:
Description:

Complement bit
The bit variable specified is complemented. A bit which had been a one is changed to zero and
vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit.

Note: When this instruction is used to modify an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example:

Port 1 has previously been written with 5BH (Ol011101B). The instruction sequence,
CPL Pl.l
CPL P1.2
will leave the port set to 5BH (01011011B).

CFL C

Bytes:
Cycles:
Encoding:
Operation:

I1 0 1 1

0 0 1 1

CPL
(C) ..... -, (C)

9-34

intJ
CPL

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

bit
Bytes:

2

Cycles:
Encoding:

1-1_1_0_1_1----'-_0_0_1_0--'

Operation:

CPL
(bit) -

bit address

-, (bit)

DA A
Function:
Description:

Decimal-adjust Accumulator for Addition
DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC
instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxxx 10 IO-xxxxi II 1), or if the AC flag is one,
six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This
internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (1OIOxxxx-l1 lxxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order
nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but
wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD
variables is greater than 100, allowing multiple precision decimal addition. OV is not affected.

All of this occurs during the one instruction cycle. Essentiilily, this instruction performs the
decimal conversion by adding OOH, 06H, 60H, or 66H to the Accumulator, depending on
initial Accumulator and PSW conditions.

Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DA A apply to decimal subtraction.

9-35

inter

MCS®·S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Example:

The Accumulator holds the "value 56H (01010110B) representing the packed "BCD digits of the
decimal number 56. Register 3 contains the value 67H (OllOOllIB) representing the packed
BCD digits of the decimal number 67. The carry flag is set. The instruction sequence.
ADDC
DA

A,R3
A

will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10111110) in the Accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the Accumulator to the value 24H
(OOI00I00B), indicating "the packed BCD digits of the decimal number 24, the low-order two
digits of the decimal sum of 56, 67, and the carry-in. The carry flag will be set by the Decimal
Adjust'instruction, indicating that a decimal overflow occurred. The true sum 56, 67, and "1 is
124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator
initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD

A,#99H

DA

A

will leave the carry set and 29H in the Accumulator, since 30
byte of the sum can be interpreted to mean 30 - 1 = 29.

Bytes:
Cycles:
Encoding:
Operation:

I1 1 0 1

0 1 0 0

DA
-contents of Accumulator are BCD
IF
[[(A3-O) > 9] V [(AC) = III
THEN(A3_0) +- (A3-0) + 6
AND
IF

[[(A7-4) > 9] V [(C) =
THEN (A7-4) +- (A7-4)

III

+

6

9-36

+

99 = 129. The low-order

intJ
DEC

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

byte
Function:

Description:

Decrement
The variable indicated is decremented by 1. An original value of DOH will underflow to OFFH.
No flags are affected. Four operand addressing modes are allowed: accumulator, register,
direct, or register-indirect. .
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.

Example:

°

Register contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain DOH
and 4OH, respectively. The instruction sequence,
DEC

@RO

DEC

RO

DEC

@RO

will leave register
3FH.

DEC

°

set to 7EH and internal RAM locations 7EH and 1FH set to OFFH and

A
Bytes:
Cycles:
Encoding:
Operation:

DEC

_O_O_O_..L.0_ 1_ O
_ 0--l

L...I

DEC
(A) +- (A) - 1

Rn
Bytes:
Cycles:
Encoding:
Operation:

I °°°1

1 rr r

DEC
(Rn) +- (Rn) - 1

9-37

inter
DEC

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

direct
Bytes:

2

Cycles:
Encoding:
Operation:

DEC

1 000 1

DEC
(direct) -

o1

0.1

direct address

(direct) - 1

@RI
Bytes:
Cycles:
Encoding:
Operation:

1 000 1

DEC
«Ri» -

o 11

«Ri» - 1

DIV AB
Function:
Description:

Divide
DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit
integer in register B. The Accumulator receives the integer part of the quotient; register B
receives the integer remainder. The carry and OV flags will be cleared.

Exception: if B had originally contained OOH, the values returned in the Accumulator and Bregister will be undefined and the overflow flag will be set. The carry flag is cleared in any
case.
Example:

The Accumulator contains 251 (OFBH or 1111101lB) and B contains 18 (l2H or 0OOI00lOB).
The instruction,

DIV AB
will leave 13 in the Accumulator (ODH or 0000llOlB) and the value 17 (11H or 00010001B) .
in B, since 251 = (13 X 18) + 17. Carry and OV will both be cleared.
Bytes:
Cycles:
Encoding:
Operation:

4

11

0 0 0

DIV
(Ah5-8 _
(Bh.o

0 1 0 0

I·

(A)/(B)

9-38

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

DJNZ

< byte> , < rel-addr >
Function:

Description:

Decrement and Jump if Not Zero
DJNZ decrements the location indicated by 1, and branches to the address indicated by the
second operand if the resulting value is not zero. An original value of OOH will underflow to
OFFH. No flags are affected. The branch destination would be computed by adding the signed
relative-displacement value in the last instruction byte to the PC, after incrementing the PC to
the first byte of the following instruction.
The location decremented may be a register' or directly addressed byte.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

Internal RAM locations 40H, SOH, and 60H contain the values 01H, 70H, and ISH, respectively. The instruction sequence,
DJNZ 40H,LABEL_l
DJNZ 50H,LABEL_2
DJNZ 60H,LABEL_3
will cause a jump to the instruction at label LABEL_2 with the values OOH, 6FH, and ISH in
the three RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times,
or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction.
The instruction sequence,
TOGGLE:

R2,#8
P1.7
R2,TOGGLE

MOV
CPL
DJNZ

will toggle Pl.7 eight times, causing four output pulses to appear at bit 7 of output Port 1.
Each pulse will last three machine cycles; two for DJNZ and one to alter the pin.
DJNZ

Rn,rel
Bytes:

2

Cycles:

2

Encoding:

L.1_1_1_0_1-,-_1_r_r_r..J

Operation:

DJNZ
(PC) +- (PC) + 2
(Rn) +- (Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN
(PC) +- (PC)

'I

reI. address

+ rei

9-39

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

DJNZ

direct,rel
Bytes:

3

Cycles:

2

Encoding:
Operation:

I1 1 0 1

0 1 0 1

direct address

reI. address

DJNZ
(PC) - (PC) + 2
(direct) - (direct) - 1
IF (direct) > 0 or (direct) < 0
THEN
(PC) - (PC) + rei

INC


Function:

Description:

Increment
INC increments the indicated variable by 1. An original value ofOFFH will overflow to OOH.
No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

Register 0 contains 7EH (011 11 11 lOB). Internal RAM locations 7EH and 7FH contain OFFH
and 4OH, respectively. The instruction sequence,
INC @RO
INC RO
INC @RO
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) OOH and 4lH.

INC

A
Bytes:
Cycles:
I

I

Encoding:

I0

Operation:

INC
(A) -

0 0 0

(A)

I

0 1 0 0

+

1

9-40

inter
INC

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Rn
Bytes:
Cycles:
Encoding:
Operation:

INC

I 00 0 0 I 1 r r r
INC
(Rn)

~

+

(Rn)

1

direct
Bytes:

2

Cycles:
Encoding:
Operation:

INC

I 0 000 I o 1 0 1
INC
(direct)

~

(direct)

direct address

+

@Ri
Bytes:
Cycles:
Encoding:
Operation:

INC

I 000 0 I 011
INC
«Ri» ~ «Ri»

+

DPTR
Function:
Description:

Increment Data Pointer
Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an
overflow of the low-order byte of the data pointer (DPL) from OFFH to OOH will increment
the high-order byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.

Example:

Registers DPH and DPL contain 12H 'and OFEH, respectively. The instruction sequence,
INC
INC
INC

DPTR
DPTR
DPTR

will change DPH and DPL to 13H and OlH.

'Bytes:
Cycles:
Encoding:
Operation:

2

I1 0 1 0
INC
(DPTR)

~

0 0 1 1

(DPTR)

+

1
9-41

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

JB blt,rel
Function:

Jump if Bit set

Description:

If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC, after incrementing the PC to the first byteofthe next
instruction. The bit tested is not modified. No flags are affected.

Example:

The data present at input port 1 is 110010 lOB. The Accumulator holds 56 (010101 lOB). The
instruction sequence,
JB

P1.2,LABELl

JB

ACC.2,LABEL2

will cause program execution to branch to the instruction at label LABEL2.
Bytes:

3

Cycles:

2

Encoding:
Operation:

JBC

I0 0 1 0

bit address

0 0 0 0

JB
(PC) - (PC) + 3
IF (bit) = 1
THEN
(PC) -

reI. address
/

(PC)

+

rei

bit,rel
Function:

Description:

Jump if Bit is set and Clear bit

If the indicated bit is one, branch to the address indicated; otherwise proceed with the next
instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed rehitive-displacement in the third instruction byte to the PC, after
incrementing the PC to the first byte of the next instruction. No flags are affected.

Note: When this instruction is used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example:

The Accumulator holds 56H (0 10 10 1l0B). The instruction sequence,
JBC ACC.3,LABELl
JBC ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2,
with the Accumulator modified to 52H (0 10 1OOlOB).

9-42

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Bytes:

3

Cycles:

2

Encoding:

LI_o_o_o_-,---o_o_o_o--,

Operation:

mc

(PC) -_O_O_1_0...J

addr15-addrB

addr7-addrO

LCALL
(PC) ~ (PC) + 3
(SP) ~ (SP) + I
«SP» ~ (PC7-0)
(SP) ~ (SP) + I
«SP» ~ (PCI5-S)
(PC) ~ addrl5_0

addr16
Function:

Long Jump

Description:

LJMP causes an unconditional branch to the indicated address, by loading the high-order and
low-order bytes of the PC (respectively) with the second and third instruction bytes. The
destination may therefore be anywhere in the full 64K program memory address space. No
flags are affected.
.

Example:

The label "JMPADR" is assigned to the instruction at program memory location 1234H. The
instruction,
UMP

JMPADR

at location 0123H will load the program counter with 1234H.
Bytes:

3

Cycles:

2

Encoding:

1

Operation:

LJMP
(PC) ~ addft5_0

° °0·1 °° °
0

1

addr15-addrB

9-47

addr7 -addrO

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MOV

< dest-byte> , < src-byte >
Function:

Description:

Move byte variable
The byte variable indicated by the second operand is copied into the location specified by the
first operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination
addressing modes are allowed.

Example:

Internal RAM location 30H holds 40H. The value of RAM location 40H is IOH. The data
present at input port I is 1100 10 lOB (OCAH).
MOY
MOY
MOY
MOY
MOY
MOY

;RO <= 30H
;A <= 40H
;Rl <= 40H
;B <= lOH
;RAM (40H) < = OCAH
;P2 #OCAH

RO,#30H
A,@RO
Rl,A
B,@Rl
@Rl,PI
P2,PJ

leaves the value 30H in register 0, 40H in both the Accumulator and register 1, lOR in register
B, and OCAR (llOOIOIOB) both in RAM location 40R and output on port 2.

MOV A,Rn
Bytes:
Cycles:
Encoding:

11 1 1 0

Operation:

MOY
(A) -(Rn)

1 r r r

·MOV A,dlrect
Bytes:

2

Cycles:

o1

Encoding:

11 1 1 0

Operation:

MOY
(A) - (direct)

0 1

direct address

MOV A,ACC Is not a valid Instruction.

9-48

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MOV A,@Ri
Bytes:
Cycles:
Encoding:
Operation:

I1 1 1 0

o1

MOV
(A) -- «Ri»

MOV A, # data
Bytes:

2

Cycles:
Encoding:
Operation:

I0 1 1 1

o1 0

0

immediate data

MOV
(A) -- #data

MOV Rn,A
Bytes:
Cycles:
Encoding:
Operation:

I 1 111

1 r r r

MOV

(Rn) -- (A)

MOV Rn,direct
Bytes:

2

Cycles:

2

Encoding:
Operation:

I 1 010

1 r r r

direct addr.

MOV

(Rn) -- (direct)

MOV Rn, # data
Bytes:

2

Cycles:
Encoding:
Operation:

1 01

11

1 r r r

immediate data

MOV
(Rn) -- #data

9-49

inter
MOV

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

dlrect,A
Bytes:

2

Cycles:

MOV

MOV

MOV

11 1 1

Operation:

MOV
(direct) +- (A)

0 1

I

direct address

direct,Rn
Bytes:

2

Cycles:

2

Encoding:

11 000

Operation:

MOV
(direct) +- (Rn)

1 r r r

direct address

dlrect,direct
Bytes:

3

Cycles:

2

o1

Encoding:

1 1 000

Operation:

MOV
(direct) +- (direct)

0 1

dir. addr. (src)

dir. addr. (dest)

direct,@Ri
Bytes:

2

Cycles:

2

Encoding:

Operaiiuii:

1 1 000

011

direct addr.

1I.'1"'\.T.7

IVIVY

(direct) +MOV

o1

Encoding:

«Ri»

direct,#data
Bytes:

3

Cycles:

2

Encoding:
Operation:

I· 0 .1

o1

0 1

direct address

MOV
(direct) +- #data

9-50

immediate data

inter
MOV

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

@Ri,A
Bytes:
Cycles:

MOV

MOV

Encoding:

I111

Operation:

MOV
«Ri» ~ (A)

011

@RI,dlrect
Bytes:

2

Cycles:

2

Encoding:

I1 o1 0

Operation:

MOV
«Ri» ~ (direct)

011

direct addr.

@Ri,#data
Bytes:

2

Cycles:

MOV

Encoding:

101

Operation:

MOV
«RI»

o1
~

immediate data

#data

< dest·bit > , 
Function:

Move bit data

Description:

The Boolean variable indicated by the second operand is copied into the location specified by
the first operand. One of the operands must be the carry flag; the other may be any directly
addressable bit. No other register or flag is affected.

Example:

The carry flag is originally set. The data present at input Port 3 is llOOOlOlB. The data
previously written to output Port 1 is 35H (OOllOlOlB).
I

MOV pl.3,e
MOV e,P3.3
MOV p1.2,e
will leave the carry cleared and change Port 1 to 39H (OOlllOOlB).

9-51

inter
MOV

MOV

MOV

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

C,bit
Bytes:

2

Cycles:

. 1

Encoding:

11 010

Operation:

MOV
(C) +- (bit)

001 0

bit address

001 0

bit address

bit,C
Bytes:

2

Cycles:

2

Encoding:

1 1 001

Operation:

MOV
. (bit) +- (C)

DPTR,#data16
Function:

Description:

Load Data

Poin~er

with a 16-bit constant

The Data Pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded
into the second and third bytes of the instruction. The second byte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16 bits of data at once.

Example:

The instruction,
MOV DPTR, # 1234H
will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.

Bytes:

3

Cycles:

2

Encoding:

11 0 0 1

0 0 0 0

immed. data 15-8

Operation:

MOV
(DPTR) +- #data15.0
DPH 0 DPL +- #data15_8 0 #data7.Q

9-52

immed. data7-0

inter
MOVC

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,@A+ 
Function:

Move Code byte

Description:

The MOVC instructions load the Accumulator with a code byte, or constant from program
memory. The address of the byte fetched is the sum of the original unsigned eight-bit Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data
Pointer or the PC. In the latter case, the PC is incremented to the address of the following
instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may
propagate through higher-order bits. No flags are affected.

Example:

A value between 0 and 3 is in the Accumulator. The following instructions will translate the
value in the Accumulator to one of four values defined by the DB (define byte) directive.
REL_PC:

INC

A

MOVC A,@A+PC
RET
DB

66H

DB

77H

DB

88H

DB

99H

If the subroutine is called with the Accumulator equal to OlH, it will return with 77H in the
Accumulator. The INC A before the MOVC instruction is needed to "get around" the RET
instruction above the table. If several bytes of code separated the MOVe from the table, the
corresponding number would be added to the Accumulator instead ..

MOVC A,@A+DPTR
Bytes:
Cycles:
Encoding:
Operation:

MOVC

2

I1 0 0 1

0 0 1 1

MOVC
(A) +- «A) + (DPTR»

A,@A + PC
Bytes:
Cycles:

Encoding:
Operation:

2

I1 0 0 0

0 0 1 1

MOVC
(PC) +- (PC) + 1
(A) +- «A) + (PC»

9-53

inter
MOVX

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

 , < src-byte >
Function:

Description:

Move External
The MOVX instructions transfer data between the Accumulator and a byte of external data
,memory, hence the "X" appended to MOV. There are two types of instructions, differing in
whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of Rq or Rl in the current register bank provide an eight-bit
address multiplexed with data on PO. Eight bits are sufficient for external I/O expansion
decoding or for a relatively small RAM array. For somewhat larger arrays, any output port
pins can be used to output higher-order address bits. These pins would be controlled by an
, .output instruction preceding the MOVX.
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2
outputs the high-order eight address bits (the contents of DPH) while PO multiplexes the loworder eight bits (DPL) with data., The P2 Special Function Register retains its previous contents while the P2,output buffers are emitting the contents of DPH. This form is faster and
more efficient when accessing very large data arrays (up to 64K bytes), since no additional ,
instructions are needed to set up the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with its
high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to
, output high-order address bits to P2 followed by a MOVX instruction using RO or Rl.

Example:

An external 256 byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/
I/O/Timer) is connected to the 8051 Port O. Port 3 provides control lines for the external
RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and' 1 contain 12H and 34H.
Location 34H,of the external RAM holds the value 56H. The instruction sequence,
MOVX A,@Rl
MOVX

@RO,A

copies the value 56H into both the Accumulator and external RAM location 12H.

9-54

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MOVX

A,@Ri
Bytes:
Cycles:

2

Encoding:

I 1 110

Operation:

MOVX
(A) - «Ri»

MOVX

001

A,@DPTR
Bytes:
Cycles:

2

Encoding:

I 1 110

Operation:

MOVX
(A) - «DPTR»

MOVX

0000

@Ri,A
Bytes:
Cycles:

2

Encoding:

I1 1 1 1

Operation:

MOVX
«Ri» -

MOVX

001

(A)

@DPTR,A
Bytes:
Cycles:

2

Encoding:

I 1 1 1 1 o0 0 0

Operation:

MOVX
(DPTR)-(A)

9-55

inter

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

NOP
Function:

No Operation

Description:

Execution continues at the following instruction. Other than the PC, no registers or flags are
affected.
.

Example:

It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A

simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must
be inserted. This may be done (assuming no interrupts are enabled) with the instruction
sequence,
CLR
NOP
NOP
NOP
NOP
SETB

P2.7

P2.7

Bytes:
Cycles:
Encoding:

1

Operation:

NOP
(pC)-(PC)

0 0 0 0 1- 0 0 0 0 1

+

MUL AB

Function:

Multiply

Description:

MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The
low-order byte of the sixteen-bit product is left inthe Accumulator, and the high-order byte in
B. If the product is greater than 255 (OFFH) the overflow flag is set; otehrwise it is cleared.
The carry flag is always cleared.

Example:

Originally the Accumulator holds the value 80 (50H). Register. B holds the value 160 (OAOH).
The instruction,
MUL AB
will give the product 12,800 (32ooH), so B is changed to 32H (ooIIOOlOB) and the Accumulator is cleared. The overflow flag is set, carry is cleared.

Bytes:
Cycles:

4

Encoding:

1 1 0 1 0

Operation:

MUL
(Ah-o (BhS-8

0 1 0 0

(A) X (B)

9-56

intJ
ORL

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

 
Function:

Description:

Logical-OR for byte variables
ORL performs the bitwise logical-OR operation between the indicated variables, storing the
results in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

If the Accumulator holds OC3H (l 100001 IB) and RO holds 55H (OlOlOIOIB) then the instruction,
ORL A,RO
will leave the Accumulator holding the value OD7H (1IOIOl1IB).
When the destination is a directly addressed byte, the instruction can set combinations of bits
. in any RAM location or hardware register. The pattern of bits to be set is determined by a
mask byte, which may be either a constant data value in the instruction or a variable computed
in the Accumulator at run-time. The instruction,
ORL, PI,#OOIIOOIOB
will set bits 5, 4, and I of output Port 1.

ORL

A,Rn
Bytes:
Cycles:
Encoding:
Operation:

I0 1 0 0

1 r r r

ORL
(A) ~ (A) V (Rn)

9-57

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

ORL A,dlrect
Bytes:

2

Cycles:
Encoding:
Operation:

I 0 1 00

o1 0

1

direct address

ORL
(A) -

(A) V (direct)

ORL A,@Ri
Bytes:
Cycles:
Encoding:

00
1 01

Operation:

ORL
(A) -

o1

(A) V

1 i

«Ri»

ORL A, # data
. Bytes:

2

Cycles:
Encoding:

I0 1 o0 I o 1 0 0

Operation:

ORL
(A) -

".

immediate data

I

(A) V #data

ORL dlrect,A
Bytes:

2

Cycles:
Encoding:
Operation:

I 0 1 00
ORL
(direct) -

001 0

direct address

(direct) V (A)

ORL direct, # data
Bytes:

3

Cycles:

2

Encoding:

1 01

Operation:

ORL

o0

(direct) -

001 1

direct addr.

(direct) V #data

9-58

immediate data

inter
ORL

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

C,
Function:

Description:

Example:

ORL

ORL

Logical-OR for bit variables
Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state·
otherwise. A slash ("I") preceding the operand in the assembly language indicates that the
logical complement of the addressed bit is used as the source value, but the source bit itself is
not affected. No other flags are affected.
Set the carry flag if and only if P1.0

=

1, ACC. 7 = 1, or OV

= 0:

MOV

C,P1.0

;LOAD CARRY WITH INPUT PIN PIO

ORL

C,ACC.7

;OR CARRY WITH THE ACC. BIT 7

ORL

C,/OV

;OR CARRY WITH THE INVERSE OF OV.

C,bit
Bytes:

2

Cycles:

2

Encoding:

1 1
1 01

Operation:

ORL
(C) -- (C) V (bit)

001 0

bit address

C,Ibit
_ Bytes:

2

Cycles:

2

Encoding:

I 1 010

Operation:

ORL
(C) -- (C) V (bit)

0000

bit address

9-59

intJ
POP

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

direct
Function:

Pop from stack.

Description:

The contents of the internal RAM location addressed by the Stack Pointer is read, and the
Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected.

Example:

The Stack Pointer originally contains the value' 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and OlH, respectively. The instruction sequence,
POP DPH
POP DPL
will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this
point the instruction,
POP SP
will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was
decremented to 2FH before being loaded with the value popped (20H).

Bytes:

2

Cycles:

2

Encoding:
Operation:

PUSH

_1_1_0_1-L_O_'_0_0_0---,

LI

direct address

POP
(direct) -+-- «SP»
(SP) -+-- (SP) - 1

direct
Function:

Push onto stack

Description:

The Stack Pointer is incremented by one. The contents of the indicated variable is then copied
into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected.

Example:

On entering an interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the
value 0123H. The instrnction sequence,
PUSH DPL
PUSH DPH
will leave the Stack Pointer set to OBH and store 23H and OlH in internal RAM locations
OAH and OBH, respectively.

Bytes:

2

Cycles:

2

Encoding:

11100

0000

Operation:

PUSH
(SP) -+-- (SP) + 1
«SP» -+-- (direct)

direct address

9-60

inter

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

RET
Function:

Return from subroutine

Description:

RET pops the high- and low-order bytes of the PC successively from the stack, decrementing
the Stack Pointer by two. Program execution continues at the resulting address, generally the
instruction immediately following an ACALL or LCALL. No flags are affected.

Example:

The Stack Pointer originally contains the value OBH. Internal RAM locations OAH and OBH
contain the values 23H and OlH, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at
location 0123H.

Bytes:
Cycles:
Encoding:
Operation:

2

I0

0 1 0

0 0 1 0

RET
(PCIS-S) +- «SP»
(SP) +- (SP) - 1
(PC7-0) +- «SP»
(SP) +- (SP) - 1

RETI
FunctIon:

Return from interrupt

Description:

RETI pops the high- and low-order bytes of the PC successively from the stack, and restores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed. The Stack Pointer is left decremented by two. No other registers are affected; the
PSW is not automatically restored to its pre-interrupt status. Program execution continues at
the resulting address, which is generally the instruction immediately after the point at which
the interrupt request was detected. If a lower- or same-level interrupt had been pending when
the RETI instruction is executed, that one instruction will be executed before the pending
interrupt is processed.

Example:

The Stack Pointer originally contains the value OBH. An interrupt was detected during the
instruction ending at location 0122H. Internal RAM locations OAH and OBH contain the
values 23H and OlH, respectively. The instruction,
RET!

will leave the Stack Pointer equal to 09H and return program execution to location 0123H.

Bytes:
Cycles:
Encoding:
Operation:

2
,-1_O_O
_ _~_O_O_1_0--,
RET!
(PCIS-S) +- «SP»
(SP) +- (SP) - 1
(PC7-0) +- «SP»
(SP) +- (SP) - 1

9-61

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

RL A
Function:
Description:
Example:

Rotate Ac.cumulator Left
The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0
position. No flags are affected.
The Accumulator holds the value OC5H (1IOOOlOlB). The instruction.

RLA
leaves the Accumulator holding the value 8BH (IOOOlOllB) with -the carry unaffected.
Bytes:
Cycles:
Encoding:
Operation:

RLC

I °0 1 0

0 0 1 1

RL
(An + I) - (An)
(AO) - (A7)

n

= 0 - 6

A
Function:

Rotate Accumulator Left through the Carry flag

Description:

The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit
7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No
other flags are affected.
.

Example:

The Accumulator holds the value OC5H (1IOOOlOlB). and the carry is zero. The instruction.
RLC

A

leaves the Accumulator holding the value 8BH (IOOOIOlOB) with the carry set.
Bytes:
Cycles:
Encoding:

LI_o_O_1_--,-_O_O_1_1....J

Operation:

RLC
(An + 1) - (An)
(AO) - (C)
(C) -(A7)

n

=

0 -:- 6

9-62

intJ
RR

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTIO!ll SET

A

Function:
Description:
Example:

Rotate Accumulator Right
The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7
position. No flags are affected.
The Accumulator holds the value OC5H (I 1000 10 lB). The instruction,
RR A
leaves the Accumulator holding the value OE2H (11 1000 lOB) with the carry unaffected.

Bytes:
Cycles:
Encoding:
Operation:

RRC

I0 0 0 0 I0 0 1 1
RR
(An) +- (An + I) n
(A7)+- (AO)

=

0 - 6

A

Function:
Description:

Example:

Rotate Accumulator Right through Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the right.
Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7
position. No other flags are affected.
The Accumulatorholds the value OC5H (llOOOlOlB), the carry is zero. The instruction,
RRC A
.leaves the Accumulator holding the value 62 (01 1000 lOB) with the c!lrry set.

Bytes:
Cycles:
Encoding:
Operation:

I0 0 0

1

RRC
(An) +- (An
(A7) +- (C)
(C) +- (AO)

O. 0 1 1

t

I) n = 0 - 6

9-63

inter
SETB

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET


Function:

Set Bit

Description:

SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressable bit. No other flags are affected.

Example:

The carry flag is cleared. Output Port I has been written with the value 34H (OOllOlOOB). The
instructions,
SETB C
SETB

Pl.O

wi11leave the carry flag set to 1 and change the data output on Port 1 to 3SH (OOllOlOlB).

SETB C
Bytes:
Cycles:
Encoding:

I110 1

Operation:

SETB
(C)~

001 1

1

SETB bit
Bytes:

2,

Cycles:
Encoding:

I1101

Operation:

SETB
(bit) +- 1

001 0

bit address

9-64

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

SJMP

rei
Function:

Short Jump

Description:

Program control branches unconditionally to the address indicated. The branch destination is
computed by adding the signed displacement in the second instruction byte to the PC, after
incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes
preceding this instruction to 127 bytes following it.

Example:

The label "RELADR" is assigned to an instruction at program memory location 0123H. The
instruction,
SJMP

RELADR

will assemble into location OlOOH. After the instruction is executed, the PC will contain the
value 0123H.
(Note: Under the above conditions the instruction following SJMP will be at 102H. Therefore,
the displacement byte of the instruction will be the relative offset (OI23H-OI02H) = 21H. Put
another way, an SJMP with a displacement ofOFEH would be a one-instruction infinite loop.)
Bytes:

2

Cycles:

2

Encoding:
Operation:

I1 0

0 0

SJMP
(PC) +- (PC)
. (PC) +- (PC)

0 0 0 0

+

reI. address

2

+ rei

,9-65

inter
SUBB

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,
Function:

Description:

Subtract with. borrow
SUBB subtracts the indicated variable and the carry flag together from the Accumulator,
leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed
for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction, so
the carry is subtracted from the Accumulator along with the source operand.) AC is set if a
borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but
not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is
subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or immediate.

Exarriple:

The Accumulator holds OC9H (llOOlOOlB), register 2 holds S4H (0 10 10 1OOB), and the carry
flag is set. The instruction,
SUBB

A,R2

will leave the value 74H (01 110100B) in the accumulator, with the carry flag and AC cleared
but OV set.
Notice that OC9H minus S4H is 7SH. The difference between this and the above result is due
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or multiple-precision subtraction, it should be explicitly cleared by a
CLR C instruction. .
SUBB

A,Rn
Bytes:
Cycles:

Encoding:

LI_1_0_0_1...J.._1_r_r_r..j

Operation:

SUBB
(A) ~ (A) - (C) - (Rn)

9-66

intJ
SUBB

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,direct
Bytes:

2

Cycles:

o1

Encoding:

1 1 001

Operation:

SUBB
(A) - (A) - (C) - (direct)

SUBB

0 1

direct address

A,@Ri
Bytes:
Cycles:

Encoding:

11 001

Operation:

SUBB
(A) - (A) - (C) - «Ri»

SUBB

011

A, # data
Bytes:

2

Cycles:

o1

Encoding:

11 001

Operation:

SUBB
(A) - (A) - (C) - #data

SWAP

0 0

immediate data

1

A
Function:

Description:

Example:

Swap nibbles within the Accumulator
SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator
(bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No
flags are affected.
The Accumulator holds the value OC5H (lJOOO101B). The instruction,
SWAP

A

leaves the Accumulator holding the value 5CH (0101 1100B).
Bytes:
Cycles:
Encoding:
Operation:

I1 1 0 0

0 1 0 0

SWAP
(A3-O) ~ (A7-4)

9-67

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

XCH

A,
Function:

Exchange Accumulator with byte variable

Description:

XCH loads the Accumulator with the contents of the indicated variable, at the same time
writing the original Accumulator contents to the indicated variable. The source/destination
operand can use register, direct; or register-indirect addressing.

Example:

RO contains the address 20H. The Accumulator holds the value 3FH (OOlllllIB). Internal
RAM location 20H holds the'value 75H (Ol1lOlOlB). The instruction,
XCH A,@RO
will leave RAM location 20H holding the values 3FH (0011 11 11 B) and 75H (Ol1lOlOlB) in
the accumulator.

XCH

A,Rn
Bytes:
Cycles:

XCH

Encoding:

1 1 100

Operation: ,

XCH
(A) -;. (Rn)

1, r r r

A,direct
Bytes:

2

Cycles:

XCH

o1

Encoding:

11 100

Operation:

XCH
(A) -;. (direct)

0 1

direct address

A,@Ri
Bytes:
Cycles:
Encoding:

1 1 100

Operation:

XCH
(A) -;.

011

«Ri»

9-68

inter
XCHD

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,@RI
Function:

Exchange Digit

Description:

XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing a
hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the
specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags
are affected.

Example:

RO contains the address 20H. The Accumulator holds the value 36H (001101 lOB). Internal
RAM location 20H holds the value 75H (OllIOlOIB). The instruction,
XCHD A,@RO
will leave RAM location 20H holding the value 76H (Oil 101 lOB) and 35H (OOllOlOlB) in the
Accumulator.

Bytes:
Cycles:
Encoding:
Operation:

XRL

_1_1_0_1--,-_0_1_1--,

LI

XCHD
(A3.Q) ~

«Ri3.Q»

,
Function:

Description:

Logical Exclusive-OR for byte variables
XRL performs the bitwise logical Exclusive-OR operation between the indicated variables,
storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.

(Note: When this illstruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.)
Example:

If the Accumulator holds OC3H (IlOOOOllB) and register 0 holds OAAH (10 1010 lOB) then
the instruction,
.

XRL A,RO
will leave the Accumulator holding the value 69H (OllOlOOlB).
When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a
variable computed in the Accumulator at run-time. The instruction,
XRL Pl,#OOllOOOlB
will complement bits 5, 4, and 0 of output Port 1.

9-69

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

XRL A,Rn
Bytes:
Cycles:
Encoding:
Operation:

'1 01 1 0

1 'r r r

XRL
(A) +- (A) ¥ (Rn)

XRL A,direct
Bytes:

2

Cycles:
Encoding:
Operation:

I0 1 1 0

o1

0 1

direct address

XRL
(A) +- (A) ¥ (direct)

XRL A,@RI
Bytes:
Cycles:
Encoding:

I0 1 1 0

Operation:

XRL

o1

1 i

(A) +- (A) ¥«Ri»

XRL A,#data
Bytes:

2

Cycles:
Encoding:
Operation:

1 01 1 0

o1

0 0

immediate data

XRL
(A) +- (A) ¥ #data

XRL dlrect,A'
Bytes:

2

Cycles:
Encoding:
Operation:

I0 1 1 0

001 0

direct address

XRL
(direct) +- (direct) ¥ (A)

9-70

I

inter
XRL

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

direct,#data
Bytes:

3

Cycles:

2

Encoding:
Operation:

I0 1 1 0
XRL
(direct)

 Do a. D. Go a.

Do D..

><><

270048-3

Pad

270048-2

Pin
Figure 2. MCS®-51 Connections
ing accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.

Port 1
Port 1 is an 8-bit bidirectional I/O port with internal
pullups. The Port 1 'output buffers can sink/source 4
LS TTL inputs. Port 1 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low wiii source
current (ilL on the data sheet) because of the internal pullups.

Port 2 also receives the high-order address bits during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.

Port 3
Port 3 is an 8·bit bidirectional I/O port with internal
pullups. The Port 3 output buffers can sink/source 4
lS TTL inputs. Port 3 pins that have 1s written to
them are pulled high by the internal pullups" and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low wiii source
current (ill on the data sheet) because of the pullups.

Port 1 also receives the low-order address bytes
during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.
In the 8032AH and B052AH, Port 1 pins P1.0 and
P1.1 also serve the T2 and T2EX functions, respectively.

Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:

Port 2
Port 2 is an 8~bit bidirectional 1/0 port with internal
pullups. The Port 2 output buffers can sink/source 4
lS TTL inputs. Port 2 pins that have 1s written to
them are pulled high by the internal pull ups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low wiii source
current (ill on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. Dur10-3

Port
Pin

Alternative Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
I!JTimer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

intJ
Note, however, that if the Security Bit in the EPROM
devices is programmed, the device will not fetch
code from any location in external Program Memory.

RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

This pin also receives the 21 V programming supply
voltage (VPP) during programming of the EPROM
parts.

ALE/PROG
Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
memory. This pin is also the program pulse input
(PROG) during programming of the EPROM parts.

XTAL1
Input to the inverting oscillator amplifier.

In normal operation ALE is emitted' at a constant
,rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

XTAL2
Output from the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAl2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator .
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155,"Oscillators for Microcontrollers."

Program Store Enable is the read strobe to external
Program Memory.
When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memo:
ry.

To drive the device from an external clock source,
XTAl1 should be grounded, while XTAl2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock Signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
.
be observed.

EA/VPP
External Access enable EA must be strapped to
VSS in order to enable any MeS-51 device to fetch
code froiT) external Program memory locations 0 to
OFFFH (0 to 1FFFH, in the 8032AH and 8052AH).
C2

r--11

, I

EXTERNAL
OSCILLATOR
SIGNAL

XTAL2

-L

---i

XTAL2

____--I

XTAL 1

D

XTAL1
Cl

"'---1 vss

vss

_L.

Cl , C2 ~ 30 pF ± 10 pF for Crystals
~ 40 pF ± 10 pF for Ceramic Resonators

270048-5

270048-4

Figure 4. External Drive Configuration

Figure 3. Oscillator Connections

10-4

inter

MCS®·51

"Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ...... O·C to 70·C

+ 150·C
+ 21.5V
0.5V to + 7V

Storage Temperature .......... - 65·C to

Voltage on EAIVpp Pin to Vss ... -0.5V to
Voltage on Any Other Pin to Vss .... -

Power Dissipation ..............•........... 1.5W

D.C. CHARACTERISTICS
Symbol

TA

=

,
0·Ct070·C·Vee

Parameter

=

5V ±10%;Vss

= ov

Min

Max

Units

-0.5

0.8

V

0

0.7

V

VIL

Input Low Voltage (Except EA Pin of
8751 H & 8751 H-8)

VIL1

Input Low Voltage to EA Pin of
8751 H & 8751H-8

VIH

Input High Voltage (Except XTAL2,
RST)

2.0

Vee

+ 0.5

VIH1

Input High Voltage to XTAL2, RST

2.5

Vee

+ 0.5

VOL

Output Low Voltage (Ports 1, 2, 3)"

VOL1

Output Low Voltage (Port 0, ALE, PSEN)*
8751 H, 8751 H-8
All Others

Test Conditions

V
V

XTAL1

0.45

V

IOL

0.60
0.45

V
V

IOL
IOL

0.45

V

VOH

Output High Voltage (Ports 1, 2, 3, ALE, PSEN)

2.4

V

VOH1

Output High Voltage (Port 0 in
External Bus Mode)

2.4

V

IlL

Logical 0 Input Current (Ports 1, 2, 3,
RST) 8032AH, B052AH
All Others

-800
-500

=

=

VSS

1.6 mA

= 3.2mA
= 2.4 mA
IOL = 3.2mA
IOH = -80/LA
IOH = -400/LA

VIN
VIN

= 0.45V
= 0.45V
=

Logical 0 Input Current to EA Pin of
B751 H & 8751 H-8 Only

-15

/LA
/LA
mA

1112

Logical 0 Input Current (XTAL2)

-3.2

mA

VIN

III

Input Leakage Current (Port 0)
B751 H & 8751 H-8
All Others

±100
±10

/LA
/LA

0.45
0-45

Logical 1 Input Current to EA Pin Qf
8751 H & 8751 H-B

500

/LA

IIH1

Input Current to RST to Activate Reset

500

/LA

VIN

Icc

Power Supply Current:
8031/8051
8031AH/8051AH
8032AH/B052AH
8751 H/8751 H-8

160
125
175
250

mA
mA
mA
mA

All Outputs
Disconnected;
EA = Vee

10

pF

Test freq

11L1

IIH

Cia

Pin CapaCitance

s

s

0.45V
VIN
VIN

< (Vee

=

s

s

Vee
Vee

- 1.5V)

1 MHz

• NOTE:

Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make .1-to-O
transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may
exceed o.av. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.

10-5

inter

MCS®·51

A.C. CHARACTERISTICS TA

= O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;
load Capacitance for Port 0, ALE, and PSEN = 100 pF;
load Capacitance for All Other Outputs = 80 pF

Symbol

Parameter

1/TClCl
TlHll
TAVll
TllAX
TlLlV

Oscillator Frequency
ALE Pulse Width
Address Valid to ALE low
Address Hold after ALE low
ALE low to Valid Instr In
8751H
All Others
ALE low to PSEN low
PSEN Pulse Width
8751H
All Others
PSEN Low to Valid Instr In
8751H
All Others
Input Instr Hold after PSEN
Input Instr Float after PSEN
PSEN to Address Valid
Address to Valid Instr In
8751H
All Others
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
RD low to Vafid Data In
Data Hold after RD
Data Float after RD
ALE low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR low
Data Valid to WR Transition
8751H
All Others
Data Valid to WR High
Data Hold after WR
AD low to Address Float
RD or WR High to ALE High
8751H
All Others

TLLPl
TPLPH

TPLIV

TPXIX
TPXIZ
TPXAV
TAVIV

TPLAZ
TRLRH
TWlWH
TRLDV
TRHDX
TRHDZ
TllDV
TAVDV
TllWl
TAVWL
TQVWX

TQVWH
TWHQX
TRlAZ
TWHlH

Variable Oscillator
Min
Max

12 MHz Oscillator
Min
Max

3.5
2TClCl-40
TClCl-40
TClCl-35

127
43
48
183
233

Units

12.0

MHz
ns
ns
ns

4TClCl-150
4TClCl":'100

58

TClCL-25

ns
ns
ns

190
215

3TClCl-60
3TClCl-35

ns
ns
3TClCL-150
3TCLCl-'125

100
125
0

0
63

TClCL-20

75

TCLCl-8
5TCLCL-150
5TClCl-115

267
302
20

20
6TClCL-100
6TClCL-100

400
400

5TCLCL-165

252
0

0
97
517
585
300

200
203

2TCLCL-70
8TCLCl-150
3TCLCl-50
' 4TClCL -130

9TCLCl-165
3TClCL+50

TClCL-70
TClCL-60
7TCLCL-150
TClCl-50

13
23
433
33
20
33
43

133
123

NOTE:
'This table does not include the B751-BAC. characteristics (see next page).

10-6

TClCL-50
TClCL-40

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

20

ns
ns
ns
ns
ns

TClCl+50
TCLCL+40

ns
ns

intJ

MCS®·51

This Table is only for the 8751H·8

A.C. CHARACTERISTICSTA

= O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF

Symbol

Parameter

8 MHz Oscillator
Min

Max

Variable Oscillator
Min

Max

3.5

8.0

Units

1/TCLCL

Oscillator Frequency

TLHLL

ALE Pulse Width

210

2TCLCL-40

ns

TAVLL

Address Valid to ALE Low

85

TCLCL-40

ns

TLLAX

Address Hold after ALE Low

90

TLLlV

ALE Low to Valid Instr In

TLLPL

ALE Low to PSEN Low

100

TCLCL-25

TPLPH

PSEN Pulse Width

315

3TCLCL-60

TPLIV

PSEN Low to Valid Instr In

TPXIX

Input Instr Hold after PSEN

TPXIZ

Input Instr Float after PSEN

TPXAV

PSEN to Address Valid

TAVIV

Address to Valid Instr In

TCLCL-35

ns

TCLCL-20

ns

5TCLCL-150

ns

20

ns

TCLCL-8

117
475

ns
ns

0
105

ns
ns

3TCLCL-150

225
0

ns·
4TCLCL-150

350

MHz

ns

TPLAZ

PSEN Low to Address Float

TRLRH

RD Pulse Width

650

TWLWH

WR Pulse Width

650

TRLDV

AD Low to Valid Data In

TAHDX

Data Hold after RD

TRHDZ

Data Float after RD

180

2TCLCL-70

ns

20
6TCLCL-100

ns

6TCLCL-100

0

ns
5TCLCL-165

460

ns
ns

0

TLLDV

ALE Low to Valid Data In

850

8TCLCL-150

ns

TAVDV

Address to Valid Data In

960

9TCLCL-165

ns

TLLWL

ALE Low to RD or WR Low

325

3TCLCL+50

ns

TAVWL

Address to RD or WR Low

370

TQVWX

Data Valid to WA Transition

TQVWH

Data Valid to WR High

TWHQX

Data Hold after WR

TRLAZ

RD Low to Address Float

TWHLH

AD or WR High to ALE High

425

3TCLCL-50
4TCLCL-130

ns

55

TCLCL-70

ns

125

7TCLCL-150

ns

TCLCL-50

75
20
75

175

10-7

TCLCL-50

ns
20

ns

TCLCL+50

ns

inter

MCS®-S1

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE

PORTO

PORT 2

270048-6

10-8

inter

MCS®·51

EXTERNAL DATA MEMORY READ CYCLE

ALE

1 - - - - - T L L O y ------<~

PORTO

PORT 2

P2.0-P2.7 OR A8-A1S FROM DPH

A8-A 15 FROM PCH

270048-7

EXTERNAL DATA MEMORY WRITE CYCLE
I+--~

TWHLH

T,LHLL

ALE

TLLWL-<~·"o----TWLWH---"""'~

Tavwx
I+-_I-':':;;'~ 1--+---TaVWH----~

PORTO

PORT 2

DATA OUT

P2.0-P2.7 OR A8-Ais FROM DPH

A8-A1S FROM PCH

270048-8

10-9

inter
SERIAL PORT TIMING-SHIFT REGISTER MODE
= O·C to 70·C; VCC = 5V ±10%; VSS = OV;

Test Conditions: TA
Symbol

12 MHz Oscillator

Parameter

Min
TXLXL

Serial Port Clock Cycle Time

Max

Load Capacitance

=

80 pF .

Variable Oscillator
Min

Units

Max

1.0

12TCLCL

,...s
ns

TQVXH

Output Data Setup to Clock Rising
Edge

700

1OTCLCL -133

TXHQX

Output Data Hold after Clock
Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold after Clock Rising
Edge

0

0

ns

TXHDV

Clock Rising Edge to Input Data
Valid

700

1OTCLCL -133

ns

..

SHIFT REGISTER TIMING WAVEFORMS

I

1-4-'OVI!H+1 ~UHQII
-------r\----~X

~

WAITE TO SBUf

I·

X~~~X~___JX~__~X~~-JX~·---JX~--~7

..
j
I
""D' --l I-""D'

t
SETlI

t

~

SET AI

ClUA __ r

270048-9

10-10

inter

MCS®-51

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TClCl

Oscillator Frequency (except 8751 H-8)
8751H-8

3.5
3.5

12
8

MHz
MHz

TCHCX

High Time

20

TClCX

low Time

20

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

ns
ns

EXTERNAL CLOCK DRIVE WAVEFORM

I.------TCLCL

-------<~

270048-10

A.C. TESTING INPUT, OUTPUT WAVEFORM

2.4=X >
20

TEST POINTS

045

0.8

<

2.0

)C

08

270048-11
A.C. Tesling: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".

10-11

MCS®-51

EPROM CHARACTERISTICS
Table 3 EPROM Programming Modes
. EA
. PSEN
P2.7
ALE

Mode

RST

P2.6

P2.S

P2.4

Program
Inhibit

1

0

O·

VPP

1

0

0
0

1
1

X

1

0

Verify

1
1

1

Security Set

1

0

O·

VPP

0
1

0
1

X
X
X
X

X
X
X
X

NOTE.

"VPP" = + 21V ± 0.5V
·ALE is pulsed low for 50 ms.

"1" = logic high for that pin
"0" = logic low for that pin

"X" = "don't care"

Programming the EPROM
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.0-P2.3 of Port 2, while the code byte to be
programmed into that location is applied to Port o.
other Port 2 pins, and RST, PSEN, and EA
should be held at the "Program" levels indicated in
Table 3. ALE is pulsed low for 50 ms to program the
code byte into the addressed EPROM location. The
setup is shown in Figure 5.

The

Normally EA is held at a logic high until just before
ALE is to be pulsed. Then EA is raised to + 21 V,
ALE is pulsed, and then EA is returned to a logic
high. Waveforms and detailed timing specifications
are shown in later sectio,ns of this data sheet.

+SV

Note that the EAIVPP pin must not be allowed to go
above the maximum specified VPP level of 21.5V for .
any amount of time. Even a narrow glitch above that
voltage level can cause permanent damage to the
device. The VPP source should be well regulated
and free of glitches.

Program Verification
If the Security Bit has not been programmed, the onchip Program Memory can be read out for verification purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port 1 and
pins P2.0-P2.3. The other pins should be held atthe
"Verify" levels indicated in Table 3. The contents of
the addressed location will come out on Port O. External pullups are required on Port 0 for this operation.
The setup, which is shown in Figure 6, is the· same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an activelow read strobe.
+5V

8751H

PH
P2.S
P2.6
P2.7

.--_---1

XTAL2

L--'+-H XTAL1
VSS

VSS

270048-12

Figure 5. Programming Configuration

270048-13

Figure 6. Program Verification
10-12

inter

MCS®-51

EPROM Security

+SV

X = "DON'T CARE"

The security feature consists of a "locking" bit which
when programmed denies electrical access by any
external means to the on-chip Program Memory.
The bit is programmed as shown in Figure 7. The
setup and procedure are the same as for normal
EPROM programming, except that P2.6 is held at a
logic high. Port 0, Port 1, and pins P2.0-P2.3 may be
in any state. The other pins should be held at the
"Security" levels indicated in Table 3.

VCC
PI
PO
P2.0P2.3
P2.4

X

8751H
ALE

ALEIPROG

P2.5
P2.6

Once the Security Bit h~s been programmed, it can
be cleared only by full erasure of the Program Memory. While it is programmed, the internal Program
Memory can not be read out, the device can not be
further programmed, and it can not execute out of
external program memory. Erasing the EPROM,
thus clearing the Security Bit, restores the device's
full functionality. It can then be reprogrammed.

P2.7

Eli

EA.'VPP

XTAL2
RST

VIHI

XTAL1
VSS

PSEN

270048-14

Figure 7. Programming the Security Bit

Erasure Characteristics
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.

The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm 2 . Exposing the
EPROM to an ultraviolet lamp of 12,000 /kW/cm 2
rating for 20 to 30 minutes, at a distance of about 1
inch, should be sufficient.
Erasure leaves the array in an all 1s state.

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
= 21°C to 27°C; VCC = 5V ±10%; VSS = OV

TA

Symbol

Parameter
Programming Supply Voltage
Programming Supply Current

Min
20.5

Max
21.5
30

Units
V
mA

4

6

MHz

VPP
IPP
1/TCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG Low

48TCLCL

TGHAX
TDVGL
TGHDX

Address Hold after PROG
Data Setup to PROG Low

48TCLCL
48TCLCL
48TCLCL

TEHSH

Data Hold after PROG
P2.7 (ENABLE) High to VPP

TSHGL

VPP Setup to PROG Low

10

TGHSL

10

TGLGH

VPP Hold after PROG
PROGWidth

TAVQV

Address to Data Valid

TELQV

ENABLE Low to Oata Valid
Data Float after ENABLE

TEHQZ

48TCLCL

45

/ks
55
48TCLCL
48TCLCL

0

10-13

48TCLCL

/ks
ms

inter

MCS@·51

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

Pl.0-fll.7
P2.0-fl2.3

VERIFICATION

ADDRESS

ADDRESS

-

PORTO

TAVGL

~

'LE/PROG

DATA OUT

I- _

.• _TGHDX
I-

TGHAX

,~
TSHGL

TGHSL

TGLGH
21V:t .SV

~

\

TTL HIGH

TTL HIGH

TTL HIGH

, --

TEHSH

IP2.7
(ENABLE)

"\.

/

_TAVQV

DATA IN
TDVGL

Ei./vpp

PROGRAMMING

TELQV_

J

_TEHQZ

J

270048-15
For programming conditions see Figure 5.

For verification conditions see Figure 6.

10-14

8051AHP
MCS®-51 FAMILY
8-BIT CONTROL-ORIENTED MICROCONTROLLER
WITH PROTECTED ROM
•

High Performance HMOS Process

• .Boolean Processor

•

Internal Timers/Event Counters

•

Bit-Addressable RAM

•

2-Level Interrupt Priority Structure

•

•

32 I/O Lines (Four 8-Bit Ports)

Programmable Full Duplex Serial
Channel

•

4K Program Memory Space

•

111 Instructions (64 Single-Cycle)

•

• .Protection Feature Protects ROM Parts
Against Software Piracy

•

4K Data Memory Space*
*Expandable to 64K
Available in 40 Pin Plastic and CERDIP
Packages
(See Packaging Outlines and Dimensions Order #231369)

The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instructions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
MCS-51 HMOS
Family Device

8051AH
8051AHP

Internal Memory
Program

Data

4Kx 8 ROM
4Kx8 ROM

128 x 8 RAM
128 x 8 RAM

Timers!
Event Counters

Interrupts

2 x 16-Bit
2 x 16-Bit

5
5

The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
to 4K.

10-15

September 1987
Order Number: 270279-002

8051AHP

P2o-P21

PQ O-PO 1

Yee

r --- - -- - ---~tttt;-

rl±!t~-

- - ----------,

~

I
I
I

I

I
I
I
I

.tiI

I

I
I
I

I
I

I
I
I
I

I
I
I

I
I
I
I
I

I
I
I

I

"E.

I r-----,,----,

ALE

P3.0-P37

PI.D-P1.1

270279-1

Figure 1. MCS®·51 Block Diagram
Port 0 is also the multiplexed low·order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups v-when emitting 1s and can SOUiC6 and
sink a LS TTL inputs.

PIN DESCRIPTIONS

Vee
Supply Voltage.

Circuit ground.

Port 0 also receives the code bytes during programming of the EPROM parts, and outputs the code
bytes during program verification of the ROM and
EPROM parts. External pullups are required during
program verification.

Port 0

Port 1

Port 0 is an a-bit open drain bidirectional 1/0 port. As
an output port each pin can sink a LS TTL inputs.

Port 1 is an a-bit bidirectional I/O port with internal
pullups. The Port 1 output buffers can sink source 4
LS TTL inputs. Port 1 pins that have 1s written to

Vss

Port 0 pins that have 1s written to them float, and in
that state can be used as high-impedance inputs.

10-16

intJ

8051AHP

P1.0
Pl.l
P1.2
P1.3
Pl.4
P1.S
Pl.6
P1.7
RST
RXD P3.0
TXD P3.1
INTO P3.2
INTI P3.3
TO P3.4
TI P3.S
WR P3.6
Rii P3.7
XTAL2
XTALI
VSS

vee
PO.O ADO
PO.l ADI
PO.2 AD2
PO.3 AD3
PO.4 AD4
PO.S ADS
PO.6 AD6
PO.7 AD7
EAlVpp
ALE'PROG
PSEN
P2.7 AIS
P2.6A14
P2.S A13
P2.4 A12
P2.3 Al1
P2.2 Al0
P2.1 A9
P2.0 AS

10
11
12
13

270279-2

Pin
Figure 2. MCS®-51 Connections
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.

Port 2
Port 2 is an S-bit bidirectional I/O port with internal
pullups. The Port 2 output buffers can sink/source 4
LS TTL inputs. Port 2 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IlL on the data sheet) because of the internal pullups.

Port 3
Port 3 is an S-bit bidirectional I/O port with internal
pullups. The Port 3 output buffers can sink/source 4
LS TTL inputs. Port 3 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IlL on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
'addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. Bits
P2.4 through P2.7 are forced to 0, effectively limiting
external Data and Code space to 4K each in the
S051AHP during external accesses'. During accesses to external Data Memory that use S-bit addresses
(MOVX @Ri), Port 2 emits the contents of the P2
Special Function Register.
Port 2 also receives the high-order address bits during programming of the EPROM parts and during
program verification of the ROM and EPROM parts .
• Protection feature

10-17

Port
Pin

Alternative Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external'input)
WR (external data memory write strobe)
RD (external data memory read strobe)

B051AHP

RST

XTAL1

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

Input to the inverting oscillator amplifier.

XTAL2

ALE/PROG

Output from the inyerting oscillator amplifier.
Address Latch Enable output pulse for latching the
low byte of the' address during accesses to external
memory.

OSCILLATOR CHARACTERISTICS

In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillatbr, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."

Program Store Enable is the read strobe to external
Program Memory.

To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle 'of the external clock Signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum ,and maximum
high and low times specified on the Data Sheet must
be observed.

When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.

EA/Vpp

EXTERNAL
OSCILLATOR ---...,.....f ,XTAL2
SIGNAL

External Access enable EA should be strapped to
Vee for internal program executions. EA must be
strapped to Vss in order to enable any MeS-51 device to fetch code from external Program memory
locations 0 to OFFFH.

~

C2

rl

T

I

XTAL1

....-...,.....f vss

XTAL2

..L

270279-5

0

Figure 4. External Drive Configuration
XTAL1
C1

DESIGN CONSIDERATION
vss

C1. C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators

270279-4

The 8051AHP cannot access external program or
Data memory above 4K. This means that the following instructions that use the Data Pointer only read/
write data at address locations below 4K:

MOVX A, @DPTR
MOVX @DPTR, A

Figure 3. Oscillator Connections

When the Data Pointer contains an address above
the 4K limit, those locations will not be accessed.
10-18

inter

8051AHP

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O'C to + 70'C
Storage Temperature .......... - 65'C to + 150'C
Voltage on EAlVpp Pin to Vss ... -0.5V to + 21.5V
Voltage on Any Other Pin to Vss .... -0.5V to + 7V
Power Dissipation .......................... 1.5W

D.C. CHARACTERISTICS
Symbol

TA

=

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

O'Cto +70'C;Vee

Parameter

=

5V ±10%;Vss

=

OV

Min

Max

Units

-0.5

0.8

V

Test Conditions

VIL

Input Low Voltage

VIH

Input High Voltage (Except XTAL2, RST)

2.0

Vee + 0.5

V

VIH1

Input High Voltage to XTAL2, RST

2.5

Vee + 0.5

V

XTAL1

VOL

Output Low Voltage (Ports 1, 2, 3)'

0.45

V

0.45

V

=

Vss

Vou

Output Low Voltage (Port 0, ALE, PSEN)*

VOH

Output High Voltage (Ports 1, 2, 3, ALE, PSEN)

2.4

V

VOH1

Output High Voltage (Port 0 in External Bus Mode)

2.4

V

IlL

Logical 0 Input Current

-500

p.A

IIL2

Logical 0 Input Current (XTAL2)

-3.2

mA

= 1.6 mA
= 3.2 mA
IOH = -80 p.A
IOH = - 400 p.A
VIN = 0.45V
VIN = 0.45V

III

Input Leakage Current (Port 0)

±10

p.A

0.45

IIH

Input Current to RST to Activate Reset

500

p.A

VIN

Icc

Power Supply Current

125

mA

All Outputs
Disconnected;
EA = VCC

CIO

Pin Capacitance

10

pF

Test freq

IOL
IOL

S;

<

VIN

S;

Vee

(Vee - 1.5V)

=

1 MHz

'NOTE:
Capacitive loading on Ports a and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port a and Port 2 pins when these pins make 1·to-0
transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.

10-19

8051AHP

A.C. CHARACTERISTICS TA

= O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF

Symbol

Parameter

12 MHz Oscillator
Min

1/TCLCL

Oscillator Frequency

TLHLL

ALE Pulse Width

TAVLL
TLLAX
TLLlV

ALE Low to Valid Instr In

TLLPL

ALE Low to PSEN Low

58

TPLPH

PSENPulse Width

215

TPLIV

PSEN Low to Valid Instr In

Max

Variable Oscillator

Units

Min.

Max

"

3.5

12.0

MHz

127

2TCLCL-40

ns

Address Valid to ALE Low

43

TCLCL-40

ns

Address Hold after ALE Low

48

TCLCL-35

ns

TPXIX

Input Instr Hold after PSEN

TPXIZ

Input Instr Float after PSEN

4TCLCL-100

233
TCLCL-25
3TCLCL-35
125
0

TPXAV

PSEN to Address Valid

TAVIV

Address to Valid Instr In

TPLAZ

PSEN Low to Address Float

TALAH

AD Pulse Width

400

TWLWH

WA Pulse Width

400

TALDV

AD Low to Valid Data In

ns
3TCLCL-125

0

TCLCL.,...8

75
302
20

ns
ns

20

ns
ns

6TCLCL-100

0

ns

5TCLCL-115

6TCLCL-100

252

ns
ns

TCLCL-20

63

ns·
ns

ns
5TCLCL-165

0

ns

TAHDX

Data Hold after AD

TAHDZ

Data Float after AD

97

2TCLCL-70

ns

TLLDV

ALE Low to Valid Data In

517

8TCLCL-150

ns

TAVDV

Address to Valid Data In

585

9TCLCL-165

ns

TLLWL

ALE Low to AD or WA Low

200

3TCLCL+50

ns

TAVWL

Address to AD or WA Low

203

4TCLCL-130

ns

TOVWX

Data Valid to WA Transition

23

TCLCL-60

ns

TOVWH

Data Valid to WA High

433

7TCLCL-150

ns

TWHOX

Data Hold after WA

33

TCLCL-50

ns

.TALAZ

AD Low to Address Float

TWHLH

AD or WA High to ALE High

300

3TCLCL-50

20
43

123

10-20

TCLCL-40

ns

20

ns

TCLCL+40

ns

inter

8051AHP

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE

PORTO

PORT 2

270279-6

EXTERNAL DATA MEMORY READ CYCLE
""-_~TLHLL

ALE

f4-----TLLDY - - - - . - j
--I.---TRLRH

+----1

PORTO

I-~----TAYDY

PORT 2

------t

P2.0-P2.7 OR A8-A 15 FROM DPH

A8-A 15 FROM PCH

270279-7

8051AHP

EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE

TLLW·L--I~".""---TWLWH -----<~

TQVWX
~-'~--~~-+-----TQVWH------~

PORTO

PORT 2

DATA OUT

P2.0-P2.7 OR A8-A15 FROM DPH

A8-A15 FROM PCH

270279-8

10-22

inter

8051AHP

SERIAL PORT TIMING-SHIFT REGISTER MODE
= O·C to + 70·C; Vee = 5V ± 10%; Vss = OV;

Test Conditions: TA
Symbol

12 MHz Oscillator

Parameter

Min

Max

Load Capacitance

=

80 pF

Variable Oscillator
Min

Units

Max

TXLXL

Serial Port Clock Cycle Time

1.0

12TCLCL

,...s

TOVXH

Output Data Setup to Clock Rising
Edge

700

1OTCLCL -133

ns

TXHOX

Output Data Hold after Clock
. Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold after Clock Rising
Edge

0

0

ns

TXHDV

Clock Rising Edge to Input Data
Valid

700

1OTCLCL -133

ns

SHIFT REGISTER TIMING WAVEFORMS

'~fXLIL~

-------,

t"4-,QVIH ...

\
~

,

X
. I

WAITE TO SBUF

I""UT OA'..

1 ~TlHQ.

_____

""D' ~

I

j

X

X~

__~X~__~X~__~X~__~x~__~1
t

SET II

I-""D'

J~_J'~~

t

SET RI

CLEAR RI

270279-9

10-23

inter

8051AHP

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TClCl

Oscillator Frequency

3.5

12

MHz

TCHCX

High Time

20

ns

TClCX

low Time

20.

ns

TClCH

Rise Time

20

os

TCHCl

Fall Time

20

ns

EXTERNAL CLOCK DRIVE WAVEFORM

....- - - - T C l C l - - - - - . . - j

270279-10

. . .> < x=
u=x

A.C. TESTING INPUT, OUTPUT WAVEFORM
2.0

2.0

TEST POINTS

0.45

0.8

0.8

270279-11
A.C. Testing: Inputs are driven at 2.4V for a Logic "'1" and 0.45V
. for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".

Program Verification
The program verification test mode has been eliminated on the 8051 AHP. It is not possible to verify the
ROM contents using this mode, the way EPROM
programmers typically do. Also, the ROM contents
cannot be verified by a program executing out of
external program memory due to the restricted ad-dressing on the 8051AHP.

10-24

8031 AH/8051 AH
8032AH/8052AH
8751 H/8751 H-8
EXPRESS
•

Extended Temperature Range

•

Burn-In

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125·C with Vee
guidelines in MIL-STD-883, Method 1015.

= 5.5V ± 0.25V, following

Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.

Electrical Deviations from Commercial
Specifications for Extended
Temperature Range
D.C. and A.C. parameters not included here are the
same as in the commercial temperature range data
sheets.

D_C. CHARACTERISTICS TA = -40·Cto + 85·C; Vee = 5V ±10%; Vss =
Symbol

Parameter

Min

Max

Unit

-0.5

0.75

V

ov
Test Conditions

VIL

Input Low Voltage

VIH

Input High Voltage (Except
XTAL2, RST)

lee

Power Supply Current:
8051AH,8031AH
8052AH, 8032AH
8751H,8751H-8

135
175
265

mA
mA
mA

All Outputs
Disconnected;
EA = Vee

Logic 0 Input Current (XTAL2)

-4.0

mA

Vin

IIL2

2.1

10-25

Vee

+ 0.5·

V

= 0.45V

October 1987
Order Number: 270007-002

intJ

MCS®·51 EXPRESS

Table 1. Prefix Identification
Prefix

Package Type

Temperature Rlmge

Burn·ln

P

plastic

commercial

no

D

cerdip

commercial

no

C

ceramic

commercial

no

N

PLCC

commercial

no

R

LCC

commercial

no

TP

plastic

extended

no

TO

cerdip

extended

no

TC

ceramic

extended

no

QP

plastic

.commercial .

yes

QD

cerdip

commercial

yes

QC

ceramic

commercial

yes

LP

plastic

extended

yes

LD

cerdip

extended

yes

LC

ceramic

extended

yes

Please note:
• Commercial temperature range is O·C to 70·C. Extended temperature range is .,..40·C to +85·C.
• Burn-in is dynamic, for a minimum time of 160 hours at 125·C, Vee = 5.5V ±0.25V, following guidelines in
MIL-STD-883 Method 1015 (Test Condition D).
• The following devices are not available in ceramic packages:
8051AH,8031AH
8052AH, 8032AH
• The following devices are not available in extended temperature range:
8751 H, 8751 H-8
Examples: P8031AH indicates 8031AH in a plastic package and specified for commercial temperature range,
without burn-in. LD8051 AH indicates 8051 AH in a cerdip package and specified for extended temperature
range with burn-in.

10-26

intJ

8751BH
SINGLE-CHIP 8-BIT MICROCOMPUTER
WITH 4K BYTES OF EPROM PROGRAM MEMORY

• Program Memory Lock

• Two 16·Bit Timer/Counters

• 128 Bytes Data Ram
• Quick Pulse Programming™ Algorithm
• 12.75 Volt Programming Voltage

•
•
•
•

• Boolean Processor
• 32 Programmable I/O Lines
PO.O- PO.7

5 Interrupt Sources
Programmable Serial Channel
64K External Program Memory Space
64K External Data Memory Space

P2.0-P2.7

....

r---------- ~
-:F
~~

Vss

~

-----------,

PSEN
ALE/1'IW1l

D/Vpp
RST

Pl.0-P1.7

P3.0-P3.7

270248-1

Figure 1. 8751BH Block Diagram

10-27

August 1987
Order Number: 270248-002

inter

8751BH

inputs, Port 1 pins that are externally being pulled
low will source current (I,L, on the data sheet) because of the internal pullups.

PIN DESCRIPTIONS

PLO
PLI
PL2
PL3
PL4
PLS
PL6
PL7
RESET
(RXD) P3.0
(TXD) P3.1
(INTO) P3.2
(iNTl) P3.3
(TO) P3.4
(Tl ) P3.S
(Wil) P3.6
(iID) P3.7

XTAL2
XTALI
VSS

Port 1 also receiveS! the low-order address bytes
during EPROM programming and program verification.

Vee
PO.O (ADO)
PO.l (AD1)
PO.2
PO.3
PO.4
PO.S
PO.6

(AD2)
(AD3)
(AD4)
(ADS)
(AD6)

Port 2: Port 2 is an 8-bit bidirectional liD port with
internal pull ups. The Port 2 output buffers can sinkl
source 4 LS TIL inputs. Port 2 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 2 pins that are externally being pulled
low will' source current (I,L, on the data sheet) because of the internal pullups.

PO.7 (AD7)
EA!VPP
ALE/PROG
PSEN
P2.7 (A1S)
P2.6 (AI4)

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory'that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullupswhen emitting 1s. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.

P2.S (AI3)
(AI2)

P2.4
P2.3
P2.2
P2.1

(All)
(Al0)

(A9)
P2.0 (AB)

Port 2 also receives the high-order address bits during EPROM programming and program verification.

270248-2

Figure 2. Pin Connections
Port 3: Port 3 is an 8-bit bidirectional liD port with

Vee: Supply voltage.

Vss: Circuit ground.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an output port each pin can sink 8 LS TIL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.

Port 0 is also the multiplexed low-order address and
data bus during' accesses to external Program and
Data Memorv. In this application it uses stronQ internal pullups when emitting 1s, and can source and
sink 8 LS TIL inputs.

internal pullups. The Port 3 output buffers can sinkl
source 4 LS TIL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port. 3 pins that are externally being pulled
low will source current (I,L, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the MCS®-51 Family, as listed below:

I::: IRXD (Sefi~li:~;~ia;:~unction
Pin

P3.1
P3.2
P3.3
P3.4
P3.5.
P3.6
P3.7

Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
Port 1: Port 1 is an 8-bit bidirectional liD port with

internal pull ups. The Port 1 output buffers can sinkl
source 4 'LS TIL inputs. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As

TXD (seriai output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
AD (external data memory read strobe)

RST: Reset input. A high on this pin for two machine

cycles while the oscillator is running resets the device.

10-28

inter

8751BH

ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. Thi~ pin is also the program
pulse input (PROG) during EPROM programming.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.

To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
be observed.

C2
I - - p - - - j XTAL2

PSEN: Program Store Enable is the Read strobe to
External Program Memory.

o

When the 8751 BH is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to External Data Memory.

I-_~--j

XTAL 1

t - - - - - - - - - I vss
270248-3
Cl, C2

EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to
fetch code from External Program Memory locations
OOOOH to OFFFH. Note, however, that if either of the
Lock Bits are programmed, EA will be internally
latched on reset.

= 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators

Figure 3_ Oscillator Connections

EXTERNAL
OSCILLATOR----j XTAL2
SIGNAL

EA should be strapped to Vee for internal program
executions.

-

This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming.

XTALl

XTAL 1: Input to the inverting oscillator amplifier.
270248-4

XTAL2: Output from, the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS

Figure 4. External Clock Drive Configuration

DESIGN CONSIDERATIONS

XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-Chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Applications Note AP-155, "Oscillators for Microcontrollers."

Exposure to light when the device is in operation
may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window
when the die is exposed to ambient light.

10-29

intJ

8751BH

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O·C to + 70·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on EAlVpp Pin to Vss .•. - 0.5V to + 13.0V
Voltage on Any Other Pin to Vss .. ;. -0.5V to + 7V
Power Dissipation ..•....................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)

• Notice: Stresses above those listed under '~bso­
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE Specifications contained within the
following tables are subject to change.

ADVANCE INFORMATION-8EE INTEL FOR DESIGN-IN INFORMATION
D.C. CHARACTERISTICS
Symbol

(TA = O·Cto +70·C;Vcc = 5V ±10%;Vss = OV)

Min

Max

Unit

V,L

Input Low Voltage (Except EA)

Parameter

-0.5

O.S

V

Test Conditions

V,L1

Input Low Voltage EA

Vss

0.7

V.

V,H

Input High Voltage
(Except XTAL2, RST, EA)

2.0

Vcc+ 0.5

V

V,H1

Input High Voltage XTAL2, RST

2.5

Vcc+ 0.5

V

V,H2

Input High Voltage to EA

4.5

5.5

V

VOL

Output Low Voltage
(Ports 1, 2 and 3)

0.45

V

IOL = 1.6 rnA (Note 1)

VOL1

Output Low Voltage
(Port 0, ALE/PROG, PSEN)

0.45

V

IOL = 3.2 rnA (Notes 1, 2)

VOH

Output High Voltage
(Ports 1, 2, 3, ALE/PROG and PSEN)

2.4

V

IOH = -SOtJoA

VOH1

Output High Voltage
(Port 0 in External Bus Mode)

2.4

V

IOH = - 4OO tJoA

I,L

Logical 0 Input Current
(Ports 1, 2, 3 and RST)

I'L1

XTAL1 = VSS

-1

rnA

Y,N = 0.45V

Logical 0 Input Current (EA)

-10

rnA

Y,N = VSS

I'L2

Logical 0 Input Current (XTAL2)

-3.2

rnA

V'N= 0.45 VXTAL1 = Vss

III

Input Leakage Current (Port 0)

±10

tJo A

I'H

Logical 1 Input Current (EA)

1

rnA

I'H1

Input Current to RST
to Activate Reset

500

tJo A

< Y,N < Vcc
4.5V < Y,N < 5.5V
Y,N < (Vcc - 1.5V)

Icc

Power Supply Current

175

rnA

All Outputs Disconnected

C,O

Pin Capacitance

10

pF

Test Freq = 1MHz

0.45

NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make 1·to-O transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALEI
PROG pin may exceed O.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch
with a Schmitt Trigger STROBE input.
2. ALE/PROG refers to a pin on the 8751BH. ALE refers to a timing signal that is output on the ALE/PROG pin.

10-30

inter

8751BH

A.C. CHARACTERISTICS (TA = O°C to + 70°C; Vee = 5V ± 10%; VSS = OV); Load Capacitance for
Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
ADVANCE INFORMATION-SEE INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol

Parameter

12 MHzOsc
Min

1/TCLCL

Max

Oscillator Frequency

Variable Oscillator
Min

Max

3.5

12.0

Units
MHz

TLHLL

ALE Pulse Width

127

2TCLCL-40

ns

TAVLL

Address Valid to ALE Low

43

TCLCL-40

ns

48

TLLAX

Address Hold After ALE Low

TLLlV

ALE Low to Valid Instruction In

TLLPL

ALE Low to PSEN Low

TPLPH

PSEN Pulse Width

TPLIV

PSEN Low to Valid Instruction In

TPXIX

Input Instr Hold After PSEN

TCLCL-35
233

ns
4TCLCL-100

ns

58

TCLCL-:-25

ns

215

3TCLCL-35

ns
3TCLCL-125

125
0

0

ns
ns

TPXIZ

Input Instr Float After PSEN

TPXAV

PSEN to Address Valid

TCLCL-20

TAVIV

Address to Valid Instruction In

302

5TCLCL-115

ns

TPLAZ

PSEN Low to Address Float

20

20

ns

63
TCLCL-8

75

ns
ns

TRLRH

RD Pulse Width

400

6TCLCL-100

ns

TWLWH

WR Pulse Width

400

6TCLCL-100

ns

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold After RD

252
0

5TCLCL-165
0

ns
ns

TRHDZ

Data Float After RD

97

2TCLCL-70

ns

TLLDV

ALE Low to Valid Data In

517

8TCLCL-150

ns

TAVDV

Address to Valid Data In

585

9TCLCL-165

ns

TLLWL

ALE Low to RD or WR Low

3TCLCL+50

ns

TAVWL

Address to RD or WR Low

TQVWX

Data Valid to WR Transition

TQVWH

200

300

3TCLCL-50

203

4TCLCL-130

ns

23

TCLCL-60

ns

Data Valid to WR High

433

7TCLCL-150

ns

TWHQX

Data Held After WR

33

TCLCL-50

ns

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

0
43

10-31

123

TCLCL-40

0

ns

TCLCL+40

ns

inter

8751BH

ALE

PORT 0

_ _J

---

PORT 2 _ _ _J

270248-5

External Program Memory Read Cycle

ALE

PSEN
i-----TLLDV

'I

- - - < - t - - - TRLRH -----+I

PORTO

INSTR. IN

PORT2

P2.0-P2.7 OR AB-A15 FROM DPH

AB-A 15 FROM PCH

270248-6

External Data Memory Read Cycle

\

ALE-{
-TLHLL-

....i-TWHLH

PSEN

1
~TLLWL

-

PORTO

PORT2

:::r
=>

TAVLL I--TLLAX-

,.

TWLWH

TQVWH

FRol~i~~ DPL

J

~
DATA OUT

I-TWHQX

K

AO-A7 FROM PCL

INSTR. IN

TAVWL
P2.0-P2.7 OR AB-A15 FROM DPH

AB-A 15 FROM PCH

270248-7

External Data Memory Write Cycle

10-32

infef

8751BH

SERIAL PORT TIMING -

SHIFT REGISTER MODE

TEST CONDITIONS (TA = O·C to + 70·C; Vee = 5V ± 10%; Vss = OV; Load Capacitance = 80 pF)
Symbol

12MHzOsc

Parameter

Min

Variable Oscillator

Max

Units

Max

Min

TXLXL

Serial Port Clock Cycle Time

1.0

12TCLCL

f-Ls

TOVXH

Output Data Setup to
Clock Rising Edge

700

1OTCLCL - 133

ns

TXHOX

Output Data Hold After
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

INSTRUCTION

I

0

1OTCLCL -133

700

2

4

3

5

ns

7

6

8

ALE

CLOCK

OUTPUT DATA

I

\

~j-TXHQX
0
IX
1 IX
2
X
j.TXHDV I:-IrTXHDX

3

X

4

X

5

X ·6 X

I

7

t

SET TI
WRITE TO SBUF
INPUT DATA - - - -......r.:'AL~,.....W:ALI~D.-""'Y::::ALI:-::D,.,..-I:';A':':'U:v-.r.:'~,....."\I:';~.-""'Y~,.,..-r.:':~
ALID
ALID
ALID
ALID

t

I

SET RI

CLEAR RI

270248-8

Shift Register Mode Timing Waveforms

_--TCLCL--~

ExternalClock Drive Waveforms

10·33

270248-9

8751BH

EXTERNAL CLOCK DRIVE
Symbol

Parameter

2.4=X

Min Max Units

1/TClCl Oscillator Frequency 3.5
TCHCX

AC TESTING INPUT/OUTPUT WAVEFORMS

12

MHz

High Time

20

ns

TClCX

low Time

20

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

.

0.45 V

Programming the EPROM

)C

2.0'

O.B

TEST POINTS

O.B

270248-10
AC inputs during testing are driven at 2.4V for a logic "1" and
0.45V for a logic "0". Timing measurements are made at 2.0V for
a logic "1" and 0.8V for a logic "0".

ns

EPROM CHARACTERISTICS

2.0

-

a

amount of time. Even narrow glitch above that voltage level can cause permanent damage to the device. The Vpp source should be well regulated and
free of glitches.

To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.0 - P2.3 of Port 2, while the code byte to be
programmed into that location is applied to Port O.
The other Port 2 and 3 pins, and RST, PSEN, and
EAIVpp should be held at the "Program" levels indicated in Table 3. AlE/PROG is pulsed low to program the code byte into the addressed EPROM location. The setup is shown in Figure 5.

AOOR.
OOOOH/orrrH

--+
--+

P3.6

87518H

P3.7

,..-......- - 1 XTAL 2

Normally EA~is held at a logic high-'!ntil just
before AlE/PROG is to be pulsed. Then EAIVpp is
raised to Vpp, AlE/PROG is pulsed low,and then
EAIVpp is returned to a valid high voltage. The voltage on the EAIVpp pin must be at the valid EAIVpp
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.

'--+--+-1 XTAL 1
Vss
270248-11

Figure 5. Programming the EPROM

Note that the EAIVpp pin must not be allowed to go
above the maximum specified Vpp level for any

10-34

8751BH

Table 3. EPROM Programming Modes
RST

PSEN

ALEI
PROG

EAI
Vpp

P2.7

P2.6

P3.6

P3.7

1

0

O'

Vpp

1

0

1

1

Verify Code Data

1

0

1

1

0

0

1

1

Program Encryption Table
Use Addresses 0-1 FH

1

0

O'

Vpp

1

0

0

1

1
1

0
0

O'
O'

Vpp
Vpp

1
1

1
1

1
0

1
0

MODE
Program Code Data

Program Lock
Bits (LBx)

x=1
x=2

NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"Vpp" = + 12. 75V ± 0.25V
• ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming™)

QUICK-PULSE PROGRAMMINGTM
ALGORITHM
The 8751 BH can be programmed using the QuickPulse Programming Algorithm for microcontrollers.
The features of the new programming method are a .
lower Vpp (12.75 volts as compared to 21 volts) and
a shorter programming pulse. It is possible to program the entire 4K Bytes of EPROM memory in less
than 13 seconds with this algorithm
To program the part using the new algorithm, Vpp
must be 12.75 ±0.25 Volts. ALE/PROG is pulsed
low for 100 ftseconds, 25 times. Then, the byte just
programmed may be verified. After programming,
the entire array should be verified. The Program
Lock features are programmed using the same
method, but with the setup as shown in Table 3. The
only difference in programming Lock features is that
the Lock features cannot be directly verified. Instead, verification of programming is by observing
that their features are enabled.

tents of the addressed location will come out on Port
O. External pullups are required on Port 0 for this
operation. (If the Encryption Array in the EPROM
has been programmed, the data present at Port 0
will be Code Data XNOR Encryption Data. The user
must know the Encryption Array contents to manually "unencrypt" the data during verify.)
The setup, which is shown in Figure 6, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
low read strobe.

ADDR.

PGM DATA
(USE 10K
PULLUPS)

OOOOH/OFFF

SEE
TABLE 3

8751BH

VIH
_P3.7

...--..---1

PROGRAM VERIFICATION
If the Lock Bits have not been programmed, the onchip Program Memory can be read out for verification .purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port 1 and
pins P2.0 - P2.3. The other pins should be held at
the "Verify" ,levels indicated in Table 3. The con-

10-35

XTAL 2

'--"'-+--IXTAL 1

VIHI

Vss

270248-12

Figure 6. Verifying the EPROM

inter

8751BH

PROGRAM MEMORY LOCK
The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against software piracy.

ENCRYPTION ARRAY
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NORed
(XNOR) with the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its
original, unmodified form.
It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.

LOCK BITS·
Also included in the,EPROM Program Lock scheme
are two Lock Bits which function as shown in Table

Erasing the EPROM also erases the Encryption Array and the Lock Bits, returning the part to full unlocked functionality.
To ensure proper functionality of the chip, the internally latched value of the EA pin must agree with its
external state.

ERASURE CHARACTERISTICS
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to anintegrated dose of at lease 15. W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 !J-W/cm rating for 20 to 30 minutes, at a distance of about 1
inch, should be sufficient.
Erasure leaves the array in an all 1s state.

4.
Table 4. Lock Bits and their Features
Lock Bits

Logic Enabled

LB1

LB2

U

U

Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)

P

U

MOVC instructions executed from
external program memory are
disabled from fetching code b~'!es
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled

P

P

Same as above, but Verify is also
disabled

U

P

Reserved for Future Definition

P = Programmed
U = Unprogrammed

10-36

inter

8751BH

ADVANCE INFORMATION-SEE INTEL FOR DESIGN-IN INFORMATION
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C, Vee = 5.0V ±10%, vss = OV)
Symbol

Units

Parameter

Min

Max

Vpp

Programming Supply Voltage

12.5

13.0

V

IPP

Programming Supply Current

50

mA

6

MHz

1/TCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG Low

48TCLCL

4

TGHAX

Address Hold After PROG

48TCLCL

TOVGL

Data Setup to PROG Low

48TCLCL

TGHDX

Data Hold After PROG

48TCLCL

TEHSH

P2.7 (ENABLE) High to Vpp

48TCLCL

TSHGL

Vpp Setup to PROG Low

10

TGHSL

Vpp Hold After PROG

10

TGLGH

PROGWidth

90

TAVQV

Address to Data Valid

48TCLCL

TELQV

ENABLE Low to Data Valid

48TCLCL

TEHQZ

Data Float After ENABLE

0

TGHGL

PROG High to PROG Low

10

J..Lsec
110

J..Lsec

48TCLCL
J..Lsec

VERIFICATION

PROGRAMMING
PI.O-PI.7
P2.0-P2.3

J..Lsec

-----{=:::!AO~D~R~ES~S~

ADDRESS
-TAVQV

PORT 0

.-----1{=~~~

DATA OUT

TDVGL
ALE/PROG

------,,1

)""I__

TELQVll'-_ _ _
P2.7

---

T_EH_Q_Z_ __

270248-13

EPROM Programming and Verification Waveforms

10-37

8052BH
SINGLE-CHIP 8-BIT MICROCOMPUTER
WITH FACTORY MASK-PROGRAMMABLE ROM
8032BH
.
SINGLE-CHIP 8-BIT CONTROL-ORIENTED
CPU WITH RAM AND I/O
8032BH-ROMless
8052BH-8K Bytes of Factory Mask-Programmed ROM
•
•
•
•

• Programmable Serial Channel
• Separate Transmit/Receive Baud Rate
Capability

256 Bytes Data Ram
Boolean Processor
32 Programmable I/O Lines
Three 16-Blt Timer/Counters

• 64K External Program Memory Space
• 64K External Data Memory Space .

• 6 Interrupt Sources
PO.O-PO.7

P2.0-P2.7

-----------,

r---------. ~~~

v~

~

PORT 0

PORT 2

DRIVERS

DRIVERS

I'ml

'L~~
RST

PI.0-P1.7

P3.0- P3.7

Figure 1. Block Diagram

10-38

270192-1

October 1987
Order Number: 270192-1103

inter

8052BH/8032BH

In addition, P1.0 and P1.1 serve the functions of the
following speCial features of the MCS®-51 Family:

PIN DESCRIPTIONS
(T2) PI.O

Port Pin

Vee

(T2EX) PI.I
PI.2

PO.I (ADI)

PI.3

PO.2 (AD2)

PI.4

PO.3 (AD3)

PI.S

PO.4 (AD4)

PI.6

PO.S (ADS)

PI.7

PO.6 (AD6)

RESET

P1.0
P1.1

PO.O (ADO)

9

Port 2: Port 2 is an a-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Port 2 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 2 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pullups.

PO.7 (AD7)

(RXD) P3.0

(TXD) P3.1

ALE

(INTO) P3.2

PSEN

(INTI) P3.3

P2.7 (AIS)

(TO) P3.4

P2.6 (AI4)

(TI) P3.S

P2.S (AI3)

(ViR) P3.6
(iW) P3.7

P2.4 (AI2)

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use a-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.

P2.3 (All)

XTAL2

P2.2 (AIO)

XTAL1

P2.1 (A9)

VSS

P2.0 (AS)

Alternate Function
T2 (Timer/Counter 2 External Input)
T2EX (Timer/Counter 2
Capture/Reload Trigger)

270192-2

Figure 2. Pin Connections
Vee: Supply voltage.
Vss: Circuit ground.
Port 0: Port 0 is an a-bit open drain bidirectional I/O
port. As an output port each pin can sink a LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.
Port 0 is also the multiplexed low-order address and'
data bus during accesses to external Program and
Data Memory; In this application it uses strong internal pullups when emitting 1s, and can source and
sink a LS TTL.inputs.

Port 3: Port 3 is an a-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 3 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the MCS®-51 Family, as listed below:

Port 1: Port 1 is an a-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 1 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pullups.

10-39

Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

inter

8052BH/8032BH

RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory;
.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.

Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Applications Note AP-155, "O~cillators for Microcontrollers."
To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
.
be observed.

PSEN: Program Store Enable is the Read strobe to
External Program Memory.
C2

When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to External Data Memory.
EA: External Access enable. EA must be strapped to .

1 - -.....--1

XTAL2

o
1 - -.....--1

XTAL 1

t - - - - - - - - 1 vss

Vss in order to enable the device to fetch code from
External Program Memory locations OOOOH to
1FFFH. Note, however, that if either of the Lock Bits
are programmed, EA will be internally latched on reset.
.
EA should be strapped to
executions.

270192-3
Cl, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators

Figure 3. Oscillator Connections

Vee for internal program
EXTERNAL
OSCILLATOR----I XTAL2
SIGNAL

XTAL 1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.

,..-- XTAL 1

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configuredfor use as an on-chip oscillator, as shown in

10-40

270192-4
CiftllPA
A Cvt"""'I!II1
I ."WI'"" .....
_ ...."" ••• u. 1"1ft,,...,
_1_"",",

=-_._ .. _..

n.i
t"ftftfi"'II.a.t;"""
_ • •..
• .a.
__
........

intJ

8052BH/8032BH

Voltage on Any Other Pin to Vss .... -O.SV to + 7V

• Notice: Stresses above those listed under '~bso­
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Power Dissipation .......................... 1.SW
(based on PACKAGE heat transfer limitations, not
device, power consumption)

NOTICE' Specifications contained within the
following tables are subject to change.

ABSOLUTE MAXIMUM RATINGS*
AmbientTemperature Under Bias .... O·C to + 70·C
Storage Temperature, .......... - 6S·C to + 1S0·C
Voltage on EA Pin
to Vss ...................... -O.SV to + 13.0V

ADVANCE INFORMATION. Contact Intel for Design-In Information.
D.C. CHARACTERISTICS (TA
Symbol

= O·Cto +70·C;Vcc

Parameter

. Min

=

sv ±10%;Vss =

OV)
Test Conditions .

Max

Unit

O.B

V

Vss

0.7

V

2.0

Vee+ 0.5

V

Input High Voltage XTAL2, RST

2.5

Vee+ 0.5

V

Input High Voltage to EA

4.5

5.5

V

Output Low Voltage
(Ports 1, 2 and 3)

0.45

V

IOL = 1.6 mA (Note 1)

VOL1

Output Low Voltage
(Port 0, ALE, PSEN)

0.45

V

IOL = 3.2 mA (Note 1) .

VOH

Output High Voltage
(Ports 1, 2, 3, ALE and PSEN)

2.4

V

IOH = -BO",A

VOH1

Output High Voltage
(Port 0 in External Bus Mode)

2.4

V

IOH = -400 ",A

IlL

Logical 0 Input Current
(Ports 1, 2, 3 and RSn

IIL1

' Logica(O Input Current (EA)

Input Low Voltage (Except EA)

-0.5

VIL1

Input Low Voltage EA

VIH

Input High Voltage
(Except XTAL2, RST, EA)

VIH1
VIH2
VOL

VIL

XTAL1 = Vss

-500

",A

VIN = 0.45 V

mA
",A

VIN = VSS

500

VIN = 0.45V XTAL1 = Vss

-10

IIL2

Logical 0 Input Current (XTAL2)

-3.2

mA

III

Input Leakage Current (Port 0)

±10

",A

0.45 < VIN  100 pF), the noise pulse on the ALE 'pin may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use·an address latch with a Schmitt
Trigger STROBE input.

10-41

inter

8052BH/8032BH

L:Logic level LOW, or ALE.
P:PSEN.
O:Output data.
R:RD signal.
T:Time.
V:Valid.
W:WR signal.
X:No longer a valid logic level. .
Z:Float.

EXPLANATION OF THE AC 'SYMBOLS
Each timing symbol has 5 characters. The first character is always a, "T" (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following isa I.ist of all the characters and
what they stand f o r . '
.'
A:Address ..
C:Clock.
D:lnput data.
H:Logic level HIGH.
1:lnstruction (program memory contents).

For example;
TAVLL = Time from Address Valid to ALE 'Low.
TLLPL = Time from ALE Low to PSEN Low.

A_C. CHARACTERISTICS (TA = O·C to 70·C; Vee = 5V ± 10%; Vss = OV); Load Capacitance for
Port 0, ALE and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)

ADVANCE INFORMATION. Contact Intel for Design-In Information.
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12MHz9sc
Min
Max

1/TCLCL

Oscillator Frequency

TLHLL

ALE Pulse Width

127

Variable· OSCillator •
Max
Min
3.5
12.0
2TCLCL-40

TAVLL

Address Valid to ALE Low

43

TCLCL-40

TLLAX

Address Hold After ALE Low

48

TLLlV

ALE Low to Valid Instruction In

TLLPL

ALE Low to PSEN Low

TPLPH

PSENPulse,Width

TPLIV

PSEN Low to Valid Instruction In

TPXIX

Input Instr Hold After PSEN

TPXIZ

Input Instr Float After PSEN

TPXAV

PSEN to Address Valid '

TAVIV

Address to Valid Instruction In

Symbol

Parameter

I

TCLCL-25

215

3TCLCL-35
125

0

ns
ns

TCLCL-20

63

FI~at

ns
3TCLCL -1.25

TCLCL-8
..

302'
20

ns
ns

0

75

ns
ns

4TCLCL-100

58

MHz
ns

TCLCL-35
233

Units

5TCLCL-115

ns
ns
ns .

TPLAZ

PSEN Low to Address

TRLRH

RD Pulse Width

400

6TCLCL-100

IWLWH

WR Pulse Width

400

6TCLCL-100

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

97

2TCLCL-70

ns

TLLDV

ALE Low toValid Data In

517

8TCLCL-150

ns

TAVDV

Address to Valic! Data In

585

9TCLCL-165

ns

TLLWL'

ALE Low to RD or WR Low

200

TAVWL

Address to RD or WR Low .

203
23 '.

TOVWX
Data Valid to WR Transition
TOVWH' , Data Valid to WR High
TWHOX

Data Held After WR

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

20

0

ns
ns
5TCLCL-165

252

3TCLCL-50

ns
ns

0

300

ns

3TCLCL+50

4TCLCL-130

ns
ns'

TCLCL-60

, ns

,433

7TCLCL-150

ns

33

TCLCL-50
0

43
10-42

123

TCLCL-40

ns
0

ns

TCLCL+40

ns

intJ

8052BH/8032BH

_ _...J

~LE

PSEN _ _..I
TPXAV
TPXIZ
PORT 0 _ _ _..1

PORT 2

AO-.A7

----

AB-AI5
270192-5

External Program Memory Read Cycle

ALE

PSEN
i-----TLLDV

'

I

-----0-1---- TRLRH -----+l

RD

----+-----~

~-----------------INSTR. IN

PORTO

P2.0-P2.7 OR AB-AI5 FROM DPH

PORT2

AB-A 15 FROM PCH
270192-6

External Data Memory Read Cycle

,

ALE

I

-TLHLL-

J

=L-TWHLH
~

~TLLWL

-.

TAVLL !-TLLAX-

,

TWLWH

~
TQVWH

PORTO

~

FRoll~i~h DPL
TAVWL

PORT2

:::::>

-

-

DATA OUT

P2.0-P2.7 OR AB-A 15 FROM DPH

'-TWHQX
XAO-A7 FROM PCL

INSTR. IN

AB-AI5 FROM PCH
270192-7

External Data Memory Write Cycle

10-43

8052BH/8032BH

SERIAL PORT TIMING -

SHIFT REGISTER MODE

.TEST CONDITIONS TA = 0·Ct070·C;"Vcc =5V ± 10%;Vss = OV; Load Capacitance = 80pF
Symbol

12MHzOsc

..

Parameter

Min

Variable Oscillator

Max

Units

Max

Min

TXLXL

Serial Port Clock Cycle Time

1.0

12TCLCL

/Ls

TOVXH

Output Data Setup ~o
Clock Rising Edge

700

10TCLCL"'-133

ns

TXHOX

Output Data Hold After
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

INSTRUCTION

I

c

1OTCLCL -133

700

0

3

2

4

7

6

5

ns

8

ALE

CLOCK

I TOVXH

OUTPUT DATA

I

r-TXHOX

---"'I:\~--:O~""-:-\IX

SBUF"

.J

INPUT DATA

~L

t
WRITE TO

t

CL~R

1

I"

IXr--:2~""\Xr-~~
3
X

X

4

~r~~
TXHDV I:
~u

5

-X

6

X

I

7

I

SET TI
~Il

~LIIl

~Ull

~

~

I

SET RI

RI

270192-8

Shift Register Mode Timing Waveforms

14-TCHCX-+I

TCLCH-I

14-

-+I

J+- TCHCL

-~-TCLCL---+I

External Cloc~ Drive Waveforms

10-44

270192-9

8052BH/8032BH

EXTERNAL CLOCK DRIVE
Symbol

Parameter

AC TESTING INPUT/OUTPUT WAVEFORMS

2.4=X

Min Max Units

1/TCLCL Oscillator Frequency 3.5

12

MHz

TCHCX

High Time

20

ns

TCLCX

Low Time

20

ns

TCLCH

Rise Time

20

ns

TCHCL

Fall Time

20

ns

2.0
o~

2.0
TEST POINTS

o~

)C
.

.

0.4SV
270192-10
AC inputs during testing are driven at 2.4V for a logic 'T' and
0.45V for a logic "0". Timing measurements are made at 2.0V for
a logic '"1" and O.BV for a logic "0".

Table 1_ Lock Bits and their Features

Lock Bits

PROGRAM MEMORY LOCK
The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against software piracy. The following description applies to the
8752BH. The same options are also available on the
8052BH, mask-programmed at the factory.

LB2

U

U

Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)

P

U

MOVC instructions executed from
external program memory are
disabled from fetching code bytes
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled

P

P

Same as above, but Verify is also
disabled

U

P

Reserved for Future Definition

ENCRYPTION ARRAY
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NORed
(XNOR) with ·the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its
original, unmodified. form.
.
It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.

Logic Enabled'

LB1

P = Programmed
U = Unprogrammed

To ensure proper functionality of the chip, the internally latched value of the EA pin must agree with its .
extern~l.state.

LOCK BITS
Also included in the Program Lock scheme are two
Lock Bits which function as shown in Table 1.

10-45

8752B'H
SINGLE-CHIP8-BIT MICROCOMPUTER,
WITH 8K BYTES OF EPROM PROGRAM,MEMORY
..'
• Program Memory Lock
• 256 Bytes Data Ram'
• Quick Pulse Programming™ Algorithm

• 6 Interrupt Sources
• Programmable Serial Cliannel
• Separate Transmit/Receive Baud Rate
Capability
.64K External Program Memory Space

• .12:75 Volt Programming Voltage
• Boolean Processor
• 32 Programmable I/O Lines
• Three 16·Bit Timer/Counters

• 64K External Data Memory Space

PO.O-PO.7

r -

~~

-

-

-

-

-,- -

-

P2.0-P2.7

-

. p..~t..I.lI~

:--:---------,

Vss

-F

i'S£iI
AU:/1'RllC

£A'Yitr ::I~ CO'NTRO>L\

P1.0-Pl.7

P3.0-P3.7

270429-1

Figure 1. Block Diagram

10-46

October 1987
Order Number: 270429-001

inter

8752BH

Port 1 also receives the low-order address bytes
during EPROM programming and program verification.

PIN DESCRIPTIONS

(T2) PLO

Vee

(T2EX) Pl.l,

PO.O (ADO)

Pl.2

PO.l (AD1)

Pl.3

PO.2 (AD2)

Pl.4
Pl.S

PO.3 (AD3)

In addition, P1.0 and P1.1 serve the functions of the
following special features of the MCS®-S1 Family:

Port Pin
P1.0
P1.1

PO.4 (AD4)

Pl.S

PO.S (ADS)

Pl.7

PO.S (ADS)

RESET

PO.7 (AD7)

(RXD) P3.0

EA/Vpp

(TXD) P3.1

ALE/PROG

(INTO) P3.2

PSEN

{lNT1) P3.3

P2.7 (A lS)

(TO) P3.4

P2.S (A14)

(T1 ) P3.S
(WR) P3.S

P2.S (A13)
P2.4 (A12)

(RO) P3.7

P2.3 (All)

XTAL2

P2.2 (Al0)

XTALl

P2.1 (A9)

Vss

P2.0 (A8)

Alternate Function
T2 (Timer/Counter 2 External Input)
T2EX (Timer/Counter 2
Capture/Reload Trigger)

Port 2: Port 2 is an a-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Port 2 pins that have 1s
written to them are pulled high by the. internal pullups, and in that state can be used as inputs. As
inputs, Port 2 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use a-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.

270429-2

Figure 2. Pin Connections

Port 2 also receives the high-order address bits during EPROM programming and program verification.

Vee: Supply voltage.
Vss: Circuit ground.

Port 0: Port 0 is an a-bit open drain bidirectional 110
port. As an output port each pin can sink a LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
.
inputs.
Port 0 is also the multipl~xed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emittill9 1s, and can source and
sink a LS TTL input~ ..

Port 3: Port 3 is an a-bit bidirectional I/O port with
intermil pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 3 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the pull ups.
Port 3 also serves the functions of various special
features of the MCS®-S1 Family, as listed below:

Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.S
P3.6
P3.7

Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.

Port 1: Port 1 is an a-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 1 pins that are externally being pulled
low will source current .(IIL' on the data sheet) because of the internal pullups.

Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.

10-47

8752BH

ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming on
the 8752BH.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.

cations Note AP-155, "Oscillators for Microcontrollers."
To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
be observed.

PSEN: Program Store Enable is the Read strobe to
External Program Memory:

C2

r---1I--.---f XTAL2
When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access ~o External Data Memory.

t--.....--I XTAL 1
.....~-----I Vss

EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to
fetch code from External Program Memory locations_
OOOOH to 1FFFH. Note, however, that if either of the
Lock B.its are programmed, EA will be internally
latched on reset.

270429-3
C1. C2 = 30 pF ± 10 pF for prystals
= 40 pF ± 10 pF for Caramic Resonators

Figure 3. Oscillator Connections

EA sh.ould be strapped to Vee for internal program
executions.
.
.

EXTERNAL
OSCILLATOR~---I

XTAL2

SIGNAL

This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.

-

XTAL1

_

Vss

XTAL2: Output from the inverting oscillator amplifier.
270429-4

Figure 4. External Clock Drive Configuration

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured .for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-

DESIGN .CONSIDERATIONS
Exposure to light when tlie 8752BH is in operation
may cause logic errors. For this reason, it is suggested that an opaque label be placed over. the window
of the 8752BH when the die is exposed to ambient
light.

10-48

inter

8752BH

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...... ODC to 70DC
Storage Temperature .......... -6SDC to + 1S0DC
Voltage on EAlVpp Pin to Vss ... -O.SV to + 13.0V
Voltage on Any Other Pin to Vss .... -O.SV to + 7V
Power Dissipation .......................... 1.SW
(based on PACKAGE heat transfer limitations, not
device power consumption)

NOTICE Specifications contained within the
fol/owing tables are subject to change.

sv

±10%;Vss = OV)

Min

Max

Units

Input Low Voltage (Except EA)

-0.5

0.8

V

VILl

Input Low Voltage EA

Vss

0.7

V

VIH

Input High Voltage
(Except XTAL2, RST, EA)

2.0

Vee+ 0.5

V

VIH1

Input High Voltage XTAL2, RST

2.5

Vec+ 0.5

V

VIH2

Input High Voltage to EA

4.5

5.5

V

VOL

Output Low Voltage
(Ports 1, 2 and 3)

0.45

V

IOL

= 1.6 mA (Note 1)

Vall

Output Low Voltage
(Port 0, ALE/PROG, PSEN)

0.45

V

10L

= 3.2 mA (Note 1, 2)

VOH

Output High Voltage
(Ports 1, 2, 3, ALE/PROG and PSEN)

2.4

V

IOH

= -80/LA

VOH1

Output High Voltage
(Port 0 in External Bus Mode)

2.4

V

IOH

= -

IlL

Logical 0 Input Current
(Ports 1, 2, 3 and RST)

/LA

VIN

= 0.45V

IIL1

Logical 0 Input Current (EA)

mA

VIN

=

Vss

=

0,45V XTAL1

D.C. CHARACTERISTICS
Symbol
VIL

(TA = ODCto +70DC;Vcc =

Parameter

-500
-10
500

/LA

Test Conditions

XTAL1

IIL2

Logical 0 Input Current (XTAL2)

-3.2

mA

VIN

III

Input Leakage Current (Port 0)

±10

/LA

0.45

= Vss

400 /LA

=

Vss

< VIN < Vee
4.5V < VIN < 5.5V
VIN < (Vee - 1.5V)

IIH

Logical 1 Input Current (EA)

1

mA

IIH1

Input Current to RST
to activate Reset

500

/LA

lee

Power Supply Current

175

mA

All Outputs Disconnected

Cia

Pin Capacitance

10

pF

Test freq

=

1 MHz

NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make 1-\0-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the
ALE/PROG pin may exceed O.SV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address
latch with a Schmitt Trigger STROBE input.
2. ALE/PROG refers to a pin on the device. ALE refers to a timing signal that is output on the ALE/PROG pin.

10-49

8752BH

L:Logic level LOW, or ALE
P:PSEN
..
Q:Output data
.' R:RD signal
T:Time
V:Valid
W:WR signal
X:No longer a valid logic level
Z:Float

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name. of a signal or the logical status of that
signal. The following is a,list of all the ch!lracters and
what they stand for.
A:Address
C:Clock'
D:lnput Data
H:Logic level HIGH
1:lnstruction (program memory contents)

For example,
TAVLL
TLLPL

= Time from Address Valid to ALE Low.
=

Time from ALE Low to PSEN Low.

A.C. CHARACTERISTICS (TA = O°C to + 70°C; Vcc. = 5V ± 10%; Vss = OV); Load Capacitance for
Port 0, ALE/PROG, and PSEN

= 100 pF; Load Capacitance for All Other OutpLits = 80 pF)

EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol

Parameter

12MHzOsc
Min

Variable Oscillator

Max

Min'

Max

3.5

12.0

Units

l/TCLCL

OsCiliator Frequency

TLHLL

ALE Pulse Width

127

2TCLCL-40

ns

TAVLL

Address Valid to ALE Low

43

TCLCL-40

ns

TLLAX

Address Hold After ALE Low

48

TCLCL-35

TLLlV

ALE Low to Valid Instruction In

TLLPL

ALE Low to PSEN Low

58

TCLCL-25

TPLPH

PSEN Pulse Width

215

3TCLCL-35

TPLIV

PSEN Low to Valid Instruction In

TPXIX

.input Instr Hold After PSEN

TPXIZ

Input Instr Float After PSEN

TPXAV

PSEN to Address Valid

TAVIV

Address to Valid Instruction In

302

5TCLCL-115

ns

TPLAZ

PSEN Low to Address Float

20

20

ns,

TRLRH

RD Pulse Width

400

6TCLCL-100

TWLWH

WR Pulse Width

400

6TCLCL-100

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

97

2TCLCL-70

ns

TLLDV

ALE Low to Valid Data In

517

8TCLCL-150

ns

TAVDV

Address to Valid Data In

585

9TCLCL-165

ns

TLLWL

ALE Low to RD or WR Low.

200

3TCLCL+50

ns

TAVWL

Address to RD or WR Low

203

4TCLCL-130

ns

TOVWX

Data Valid to WR Transition

23

TCLCL-60

ns

TOVWH

Data Valid to WR High

433

7TCLCL-150

ns

TWHOX

Data Held After WR

33

TCLCL-50

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

233

ns
4TCLCL-100

0

ns

TCLCL-20

.

TCLCL-8

75

252

300

ns
ns
5TCLCL-165

3TCLCL-50

0
43

123

10-50

TCLCL-40

ns
ns

.0

0

ns
ns

0
63

ns
ns

3TCLCL-125

125

MHz'

ns
ns

ns
0

ns

TCLCL+40

ns

8752BH

ALE _ _J

PSEN _ _J

]I--!----Ji"_____.

TPXAV
TPXIZ

PORT

a _ _J

AO-A7

AB-AI5

PORT 2 _ _.....J

270429-5

External Program Memory Read Cycle

ALE

PSEN

'I

i------TLLDV

--+---

TRLRH

---~

PORTO

INSTR. IN

P2.0-P2.7 OR AB-AI5 FROM DPH

PORT2

AB-AI5 FROMPCH

270429-'6

External Data Memory Read Cycle

ALE

-1:.-TLHLL~

I

~

4TWHLH
~
~TLLWL

.PORTO

PORT2

:::r
:::::>

TAVLL -TLLAX-

,

TWLWH

TQVWH

FRoIAA~i~~

DPL

J

~
DATA OUT

--TWHQX

1\

AO-A7 FROM PCL

INSTR. IN

TAVWL
P2.0-P2.7 OR AB-A 15 FROM DPH

X

AB-A 15 FROM PCH

270429-7

External Data Memory Write Cycle

10-51

8752BH

SERIAL PORT TIMING-SHIFT REGISTER MODE
TEST CONDITIONS
Symbol

TA

=

o·c to + 70·C; vee =

5V ± 10%; vss

Parameter

Min

=

OV; Load Capacitance

=

80 pF

Variable Oscillator

12MHzOsc
Max

Units

Max

Min

TXLXL

Serial Port Clock Cycle Time

.1.0

12TCLCL

TOVXH

Output Data Setup to
Clock Rising Edge

700

10rCLCL --.: 133.

ns

TXHOX

Output Data Hold After .
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

INSTRUCTION

I

10TCLCL-133

700

2·

·1

0

. /Ls

7

6

4

3

ns

8

ALE

CLOCK

OUTPUT DATA·

t

\

~!-TXHQX
0
IX
1
I

X

2

3

X

4

X

5

X 6X

r.: . ....

7/
I

-lrTXHDX

SET TI
WRITE TO SBUF
-l TXHDV
INPUT DATA -.,.....----\r.:AJ~,....-w:AlI~·~-\r.:A-:-::U)J'"-,.r.:':AL'::!ID.;--V~AIJ~,...."'\r.~AIJ'="-\r.:AIJ":':D)J'"-,.r.:':":!J

I

t

SET RI.

CLEAR RI

270429-8

Shift Register Mode Timing Waveforms

270429-9

External Clock Drive Waveforms

10-52

inter

8752BH

EXTERNAL CLOCK DRIVE
Symbol

Parameter

A.C. TESTING INPUT/OUTPUT WAVEFORMS

Min Max Units

'1/TClCl Oscillator Frequency 3.5

12

2 . 4 = X 2.0
O.B

MHz

TCHCX

High Time

20

ns

TClCX

low Time

20

ns

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

TEST POINTS

2.0
0.8

)C

0.45V

270429-10
AC inputs during testing are driven ,at 2.4V.for a logic "1" and
O.4SV for a logic "0". Timing measurements are made at 2.0V for
a logic "1" and O.BV for a logic "0".

EPROM CHARACTERISTICS
Table 1 shows the logic levels for programming the
Program Memory, the Encryption Table, and the
lock Bits and for reading the Signature bytes.

Programming the EPROM
To be programmed, the 8752BH must be running
with a 4 to 6 MHz oscillator. (The reason the oscillator needs to be running is that the internal bus is
being used to transfer address and program data to
appropriate internal registers.) The address of an
EPROM location to be programmed is applied to
Port 1 and pins P2.0 - P2.4 of Port 2, while the code
byte to be programmed into that location is applied
to Port O. The other Port 2 and 3 pins, and RST,
PSEN, and EAlVpp should be held at the "Pro-

gram" levels indicated in Table 1. AlE/PROG is
pulsed low to program the code byte into the addressed EPROM location. The setup is shown in Figure 5.
Normally EAlVpp is held at a logic high..J!.ntil just
before AlE/PROG is to be pulsed. Then EAlVpp is
raised to Vpp, AlE/PROG is pulsed low, and then
EAlVpp is returned to a valid high voltage. The voltage on the EAlVpp pin must be at the valid EAlVpp
high level before a verify is attempted. Waveforms
and detailed· timing specifications are shown in later
sections of this data sheet.
Note that the EAlVpp pin must not be allowed to go
above the maximum specified Vpp level for any
amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The Vpp source should be well regulated and
free of glitches.

+5V

25 100!-'. PULSES TO GND
8752BH

.--_--IXTAL2

L -......-+-IXTAL 1

Vss

270429-11

Figure 5. Programming the EPROM

10-53

inter

8752BH

Table 1 EPROM Programming Modes
MODE

RST

PSEN

ALEI
PROG

EAI
Vpp'

P2.7

P2.6

P3.6

P3.7

Program Code Data

1

0

O'

Vpp

1

0

1

1

Verify Code Data

1

0

1

1

0

0

1

1

Program Encryption Table
Use Addresses 0-1 FH

1

0

O'

Vpp

1

0

0

1

1
1

0
0

O·

O'

Vpp
Vpp

1
1

1
1

1
0

1
0

1

0

1

1

0

0

0

0

Program Lock
Bits (LBx)
Read Signature

x=1
x=2

NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"Vpp" = + 12.75V ±0.25V
*ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming™)

QUICK-PULSE PROGRAMMINGTM
ALGORITHM

PROGRAM VERIFICATION
If the Lock Bits have not been programmed, the onchip Program Memory can be read out for verification purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port .1 and
pins P2.0 - P2.4. The other pins should be held at
the "Verify" levels indicated in Table 1. The contents of the addressed location will come out on Port
O. External pullups are required on Port 0 for this
operation. (If the Encryption Array in the EPROM
has been programmed, the data present at Port 0
will be Code Data XNOR Encryption Data. The user
must know the Encryption Array contents to manually "unencrypt" the data during verify.)

The 8752BH can be programmed using the QuickPulse Programming™ Algorithm for microcontrollers. The features of the new programming method
are a lower Vpp (12.75 volts as compared to 21
volts) and a shorter programming pulse. It is possible to program the entire 8K Bytes of EPROM memory in less than 25 seconds with this algorithm!
To program the part using the new algorithm, Vpp
must be 12.75 ±0.25 Volts. ALE/PROG is pulsed
low for 100 fLseconds, 25 times as shown in Figure
6. Then, the byte just programmed may be verified.
After programming, the entire array should be verified. The Program Lock features are programmed
using the same method, but with the setup as shown
in Table 1. The only difference in programming Lock
features is that the Lock features cannot be directly
verified. Instead, verification of programming is by
observing that their features are enabled.

The setup, which is shown in Figure 7, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
low read strobe.

11~, - - - - - - 2 5

'I

PULSES

ALE/PROG:~-----~
'----.---J .

'-.~

10)'.

MIN1 I'

ALE/PROG :---...:...,\

n

o L._ _ _ _ _ _ _..J

100,u'
:1:10)'.

'I

n

'-_ _ _ _ _ _..... '-._ __
270429-12

Figure 6. PROG Waveforms

10-54

8752BH

270429-13

Figure 7. Verifying the EPROM
Table 2. Lock Bits and their Features

PROGRAM MEMORY LOCK

Lock Bits

The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against software piracy.

Logic Enabled

LB1

LB2

U

U

Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)

P

U

MOVC instructions executed from
external program memory are
disabled from fetching code bytes
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled

P

P

Same as above, but Verify is also
disabled

U

P

Reserved for Future Definition

ENCRYPTION ARRAY
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NORed
(XNOR) with the code !:Iyte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its
original, unmodified form.
It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.

P = Programmed
U = Unprogrammed

LOCK BITS

READING THE SIGNATURE BYTES·

Also included in the EPROM Program Lock scheme
are two Lock Bits which function as shown in Table

The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031 H,
except that P3.6 and P3.7 need to be pulled to a
logic low. Thevalues returned are:

2.
Erasing the EPROM also erases the Encryption Array and the Lock Bits, returning the part to full unlocked functionality.
To ensure proper functionality of the chip, the internally latched value of the EA pin must agree with its
external state.

10-55

(030H)
(031 H)

= 86H indicates manufactured by Intel
= 52H indicates 8752BH

8752BH

ERASURE CHARACTERISTICS

this type of exposure, it is suggested that an opaque
label be placed over the window.

Erasure of the EPROM begins to occur when the
8752BH is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to

The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at lease 15 W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 jJ-W/cm rating for 30 minutes, at a distance of about 1 inch;
should be sufficient.
Erasure leaves the array in an all 1s state.

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C, Vee = 5.0V ±10%, Vss = OV)
Symbol

Units

Parameter

Min

Max

Vpp

Programming Supply Voltage

12.5

13.0

V

Ipp

Programming Supply Current

50

rnA

-6

1/TCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG Low

TGHAX

Address Hold After PROG

48TCLCL

TDVGL

Data Setup to PROG Low

48TCLCL

4

MHz

48TCLCL

TGHDX

Data Hold After PROG

48TCLCL

TEHSH

P2.7 (ENABLE) High to Vpp

48TCLCL

TSHGL

Vpp Setup to PROG Low

10

jJ-s

TGHSL

Vpp Hold After PROG

10

jJ-s

TGLGH

PROGWidth

90

TAVaV

Address to Data Valid

TELaV

ENABLE Low to Data Valid

TEHaZ

Data Float After ENABLE

0

TGHGL

PROG High to PROG Low

10

jJ-s

48TCLCL

PROGRAMMING
PI.a-pI.7
p2.a-p2.4

110
48TCLC;L

48TCLCL.
jJ-s

VERIFICAnON

---:----{=:A~D~DR~ES~S~~=~--~-__;=:::!A~DD~RE~SS~J----TAVQV

PORT a

----H:=~~~:=H_-----:--_{~DA~TA~O~U~T::Jf-----:-TDVGL

ALE/PROG

-----""\1
TSHGLj-_

fA/vpp

_

_ TGLGH

~lI---"'vp-p---'i!-----.ll'---:;::t,.:;::::::-_ _.f-____I - - - - -

--J

="!T_EHSH

P2.7

~.~----~-------

TEHQZ

~-~

270429-14

EPROM Programming and Verification Waveforms
10-56

SOC51 BH/SOC51 BH-1 /SOC51 BH-2
CHMOS SINGLE-CHIP S-BIT MICROCOMPUTER
WITH FACTORY MASK-PROGRAMMABLE ROM
SOC31 BH/SOC31 BH-1/S0C31 BH-2
CHMOS SINGLE-CHIP S-BIT CONTROL-ORIENTED
CPU WITH RAM AND I/O
SOC51BH/SOC31BH-3.5 to 12 MHz, Vee = 5V ± 20%
SOC51BH-1/S0C31BH-1-3.5 to 16 MHz, Vee = 5V ±20%
SOC51BH-2/S0C31BH-2-0.5 to 12 MHz, Vee = 5V ± 20%

•

Power Control Modes

•

High Performance CHMOS Process

•
•

128 x 8-Bit RAM
32 Programmable I/O Lines

• Boolean Processor
_ 5 Interrupt Sources

•

Two 16-Bit Timer/Counters

•

Programmable Serial Port

•

64K Program Memory Space

•

64K Data Memory Space

The MCS®-51 CHMOS products are fabricated on Intel's CHMOS III process and are functionally compatible
with the standard MCS-51 HMOS and EPROM products. CHMOS III is a technology which combines the high
speed and density characteristics of HMOS with the low power attributes of CHMOS. This combination expands the effectiveness of the powerful MCS-51 architecture and instruction set.
Like the MCS-51 HMOS versions, the MCS-51 CHMOS products have the following features: 4K byte of ROM
(80C51 BH/80C51 BH-1/80C51BH-2 only); 128 bytes of RAM; 32 I/O lines; two 16-bit timer/counters; a fivesource two-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuitry. In
addition, the MCS-51 CHMOS products have two software selectable modes of reduced activity for further
power reduction-Idle and Power Down.
The Idle mode freezes the CPU while allowing the RAM, timer/counters serial port and interrupt system to
continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.

-IVSS~

-

-

I

I
I

270064-1

Figure 1. Block Diagram

10-57

September 1987
Order Number: 270064·005

inter

80C51BH, -1, -2/80C31BH, -1,-2

IDLE MODE

Vss

In the Idle mode; the CPU puts itself to sleep while
all the on chip peripherals stay active. The instruction that invokes the Idle mode is the last instruction
executed in the normal operating mode before Idle
mode is activated. The content of CPU, the on chip
RAM, and all the Special Function Registers remain
intact during this mode. The Idle mode can be terminated either by any enabled interrupt, at which time
the process is picked up at the interrupt service routine and continued, or by a hardware reset which
starts the processor the same as a power on reset.

Circuit ground.

POWER DOWN MODE
In the Power Down mode the oscillator is stopped,
and the instruction that invokes Power Down is the
last instruction executed. The· on-chip. RAM and
Special Function Registers retain their values until
the Power Down mode is terminated.
The only exit from Power bown is a hardware reset.
Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before Vee is restored to its normal operating level and
must be held active long enough to allow the oscillator to restart and stabilize.
The control bits for the reduced power modes are in
the Special Function Register PCON.

PortO
Port Ois an 8-bit open drain bi-directional 1/0 port.
Port 0 pins that have 1's written to them float, and in
that state can be used .as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1s; Port 0 al~9 outputs the
code bytes during program verification in the
80C51 SH. External pullups are required during program verification.

Port 1
Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are
pulled high by the internal pull ups, and in that state
can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (ilL,
on the data sheet) because of the internal pullups.

Port 2

NOTE:
For more detailed information on these reduced
power modes refer to Application Note AP-252,
"Designing with the 80C51 SH".

Port 2 is an 8-bit bidirectional 1/0 port with'internal
pullups. Port 2 pins that have 1s written to them are
pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (ilL,
on the data sheet) because of the internal pull ups.

PIN DESCRIPTIONS

Port 2 emits the high-order address byte during
fetches from external Program Memory and during

Vee
Supply voltage during normal, Idle, and Power Down
operations.
Table 1. Status of the external pins during Idle and Power Down modes
Mode
Idle

Program
Memory

ALE

PSEN

PORTO

PORT 1

PORT 2

PORT 3

Internal

1

1

Data

Data

Data

Data

, Idle

External

1

1

Float

Data

Address

Data

Power Down

Internal

0

0

Data

Data

Data

Data

Power Down

External

0

0

Float

Data

Data

Data

10-58

intJ

80C51BH, -1, -2/80C31BH, -1,-2

INDEX
CORNER

VCC
PO.O
PO.l
PO.2
PO.3
PO.4
PO.5 '
PO.I
PO.7

Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.5
Pl.6
Pl.7
RST
P3.0/RXD
P3.1/TXD
P3.2/iN'fii
P3.3INTl
P3.4/TO
P3.S/Tl
P3.6/WR
P3.7/iii)
XTAL2
XTALl
VSS

P1.5
Pl.6
Pl.7
RST
P3.0
NC
P3.1
P3.2
P3.3
P3.4
P3.S

EA
ALE

iiSEN
P2.7
'P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0

~(~

~~

)=~

:~ PO.S

PO.4

:.: ~

~~! PO.6

!~1

~H PO.7

H]

~~

1~ ~

r~ NC

EA

~~~

~~ ALE

!! ~

~}~

~~!

r~! P2.7

!!;

rM P2.6
r~ P2.S

j!]

:~: ;~:

:2: :;;: ;R:

270064-2

:A~

:::

r~;

;i: ;s;;

PSEN

:~:

270064-3

Pin

Pad

Diagrams are for pin reference only.
Package sizes ,are not to scale.

Figure 2. Connection Diagrams
accesses to external Data Memory' that use 16-bit
addresses (MOVX @DPTR). In this, application it
uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use S-bit
addresses (MOVX @Ri), Port 2 emits the conten(s of
the P2 Special Function Register.

RST

Reset input. A high on this pin for two machine cycles whiie the oscillator is running resets the device.
An internal diffused resistor to Vss permits PowerOn reset using only an external capacitor to Vee.

Port 3

ALE

Port 3 is an S-bit bidirectional 110 port with internal
pullups. Port 3 pins that have 1s written to them are
pulled high by the internal pullups, and in that state.
can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (ilL,
on the data sheet) because of the pullups.

Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
memory.

Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:

Port Pin
P3.0
P3.1

P3.2

P3.3
P3.4

P3.5

P3.6
P3.7

In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however,that one ALE pulse is skipped during each'
access to external Data Memory.

Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write
strobe)
RD (external data memory read
strobe)

Program Store Enable is the read strobe to external
Program Memory.

10-59

inter

80C51BH, ~1, -2/80C31BH, -1,-2

When the 80C51 BH is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory. PSEN is not activated during fetches from internal program memory.

EA
External Access enable. EA must be strapped to
Vss in order to enable the device to fetch code from
external Program Memory locations· OOOOH to
OFFFH. If EA is strapped to Vee the device executes
from internal Program Memory unless the program
counter contains an address greater than. OFFFH.

ured for use as an on-chip oscillator, as shown in
Figure 3. More detailed information concerning the
use of the on-chip oscillator is available in Application Note AP-155,. "Oscillator for Microcontr'ollers".
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide~by-two flip"flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.
.

Design Considerations

XTAL1

• At power on, the voltage on Vee and RST must
come up at the same time for proper start-up.

Input to the inverting oscillator amplifier and input to.
the internal clock generator circuits.

• Before entering· the Power Down mode the contents oUhe Carry Bit and B.7 must be equal.

a

• When the Idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it .left off, up to two machine
cycles before the internal reset algorithm takes
control: On-chip hardware inhjbits access to internal RAM in this event, but access to the port pins
is, not inhibited. To elimin.ate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the .one that invokes
Idle should not be on~ that writes to a port pin or
to external memory.
..

XTAL2
Output from the inverting oscillator amplifier.

30pF"

t - - - - - - - - I vss
NC

270064-4

Figure 3. Crystal OSCillator

XTAL2

EXTERNAL
OSCILLATOR --~----------1 XTAL 1
SIGN~L

':,: .

Oscillator, Characteristics

VSS

XTAL 1 and XTAL2 are the inpl,lt and output, respectively, of an inverting ,amplifier which can be config-

270064-5.

Figure 4. External Drive Configuration

10-60

inter

80C51BH, -1, -2/80C31BH, -1,-2

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... o'e to + 70'e
Storage Temperature .......... - 65'e to + 150~e
Voltage on any
Pin to Vss ................ -0.5V to Vcc

+ 0.5V

Voltage on Vcc to Vss ............. -0.5V to 6.5V

• Notice: Stresses above those listed under '~bso­
lute Maximum Ratings" may caU.se permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability..

Power Dissipation ......................... 1.0W·
"This value is based on the maximum allowable die temperature and
the thermal resistance of the package.

D.C. CHARACTERISTICS
Symbol

= o'e to 70'e; Vcc = 5V ± 20%; Vss = OV)
Typ(3)

Max

Unit

VIL

Input Low Voltage
(ExceptEA)

-0.5

0.2 Vee -0.1

V

VIL1

Input Low Voltage (EA)

-0.5

0.2 Vee - 0.3

V

VIH

Parameter

(TA

NOTICE Specifications contained within the
following tables are subject to change.

,Input High Voltage
(Except XT AL 1, RST)

Min

0.2 Vee

+ 0.9

Vee

+ 0.5

V

Vee

+ 0.5

V

Test Conditions

VIH1

Input High Voltage
(XTAL1, RSn

VOL

Output Low Voltage
(Ports 1. 2. 3)

0.45

V

IOL = 1.6mA(1)

VOL1

Output Low Voltage
, (Port 0, ALE, PSEN)

0.45

'V

IOL = 3.2 mA (1)

Output High Voltage
(Ports 1, 2, 3, ALE, PSEN)

VOH

Output High Voltage
(Port 0 in External Bus
Mode)

VOH1

0.7 Vee

2.4

V

IOH = -60 /LA Vee = 5V ±10%

0.75 Vee

V

IOH = -25/LA

0.9 Vee

V

IOH= -10/LA

2.4

V

IOH = -800 /LA Vee = 5V ± 10%

0.75 Vee

V

IOH = -300/LA

V

0.9 Vee

IOH = -80 /LA (2)

IlL

Logical 0 Input Current
(Ports 1, 2, 3)

-50

/LA

VIN = 0.45V

ITL

Logical 1 to 0 Transition
Current (Ports 1, 2, 3)

-650

/LA

VIN = 2V

III

Input Leakage Current
(PortO, EA)

±10

/LA

0.45

RRST

Reset Pulidown Resistor

150 .

KO

CIO

Pin Capacitance

10

pF

Icc

Power Supply Current:
Active Mode, 12 MHz (4)
Idle Mode, 12 MHz (4)
Power Down Mode

20
5
50

mA
mA

I

50

11
1.7
5

10-61

/LA

< VIN < Vee

Test Freq = 1 MHz, T A = 25'C

(5)

80C51BH, -1, -2/80C31BH, -1,

~2

NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vou; of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pil')s make 1to-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input. ,
'
2. Capacitive loading on PO,rts 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 Vcc
specification when the address bits are stabilizing.
3. "Typicals" are based on limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temperature,'5V.
'
4. ICCMAX at other frequencies is given by
Active Mode: ICCMAX = 1.47'X FREQ + 2.35
Idle Mode:
ICCMAX = 0.33 x FREQ + 1.05
,
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mAo See Figure 5.
5. See Figures 6 through 9 for Icc test conditions.

a

2S

1

,--""r--,--...,-"T1 ~~~VE

MODE

TYP(3)

151---+-----ifr-+-----..I ACTIVE MODE
XTAL2
XTAL1

10r---+-~___i-~+--~

vss
MAX
IDLE MODE

270064-15

Figure 7. Icc Test Condition, Idle Mode.
All other pins are disconnected.

TYP(3)

L:~d:::::::t:=:t=~ IDLE MODE
4MHz

BMHz

12MHz

16MHz

FREQ AT XTAL 1

270064-13

Figure 5. Icc vs. Frequency.
Valid only within frequency specifications of
the device under test.

XTAL2
XTALI

vss
270064-14

Figure 6. Icc Test Condition, Active Mode.
All other pins are disconnected.
"

I

10-62

inter

80C51BH, -1, -2/80C31BH, -1,-2

O.S • - - - - - -~~---Vce. .
0.7 Vee
0.4SV
0.2 Vce -O.l
TCHCL
270064-16

Figure 8. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.

Vce
lee~

",---vee...

vce

PO
RST

Eli

XTAL2
XTALl

vss
270064-17

Figure 9. Icc Test Condition, Power Down Mode. All other pins are disconnected. Vcc = 2V to 6V.
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that .
signal. The following is a list of all the characters and
.
what they stand for.
A:
C:
D:
H:
I:
L:

Address.
Clock.
Input data.
Logic level HIGH.
Instruction (program memory contents).
Logic level LOW, or ALE.

P:
Q:
A:
T:
V:
W:
X:
Z:

PSEN.
Output data.
AD signal.
Time.
Valid.
WA signal.
No longer a valid logic level.
Float.

EXAMPLE:
TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.

10-63

80C51BH, -1, -2/80C31BH, -1,-2

A.C. CHARACTERISTICS
(TA = O·C to 70·C, Vee =. 5V ± 20%, Vss = OV, Load Capacitance for Port 0, ALE, and PSEN = 100 pF,
Load Capacitance for All Other Outputs = 80 pF)

EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol

Parameter

12MHzOsc
Min

1/TCLCL

Max

Oscillator Frequency
80C51 BH/80C31 BH
80C51 BH-1 /80C31BH-1
80C51 BH-2/80C31 BH-2

Variable OSCillator

Units

Min

Max

3.5
3,5
0.5

12
16
12

MHz

TLHLL

ALE Pulse Width

127

2TCLCL - 40

ns

TAVLL

Address Valid to ALE Low

28

TCLCL - 55

ns

48

TCLCL - 35

TLLAX

Address Hold After ALE Low

TLLlV

ALE Low to Valid Instr In

TLLPL

ALE Low to PSEN Low

43

TCLCL - 40

ns

TPLPH

PSEN Pulse Width

205

3TCLCL - 45

ns

TPLIV

PSEN Low to Valid Instr In

TPXIX

Input Instr Hold After PSEN

TPXIZ

Input Instr Float After PSEN

TAVIV

Address to Valid Instr In

234

.3TCLCL - 105

145
0

ns
4TCLCL - 100

0

ns

ns
ns

59

TCLCL - 25

ns

312

5TCLCL - 105

ns

10

ns

TPLAZ

PSEN Low to Address Float

TRLRH

RD Pulse Width

400

TWLWH

WR Pulse Width

400

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

97

2TCLCL - 70

TLLDV

ALE Low to Valid Data In

517

8TCLCL- 150

ns

TAVDV

Address to Valid Data In

585

9TCLCL - 165

ns

TLLWL

ALE Low to RD or WR Low

200

TAVWL

Address Valid to RD or WR Low

203

4TCLCL - 130

ns

TOVWX

Data Valid to WR Transition

23

TCLCL - 60

ns

TWHOX

Data Hold After WR

33

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

10
6TCLCL - 100

ns

6TCLCL - 100

0

ns
5TCLCL - 165

252
0

300

3TCLCL - 50

43

10-64

ns

3TCLCL

+ 50

TCLCL - 50
0
123

ns

ns

ns
0

TCLCL - 40

.ns

TCLCL

ns

+ 40

ns

intJ

80C51BH, -1, -2/80C31BH, -1,-2

EXTERNAL DATA MEMORY READ CYCLE
TWHLH

ALE

---- ---TLLDy----

--TLLWl.-!----TRLAH-t----

------~------,

Ir----------------TAHDZ

-

TRHD. -

-TRLAZ

PORTO

I

--::

DATA IN

------TAyDy-------

AI·A1S FROM PCH

P2.0·P2.7 OR A8·A15 FAOM DPH

PORT 2

270064-6

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE
-TAYLL- - - - - - T P l P H - - -

TLLPL

TLUV

TPXIZI-TPIII-

-

INSTR
IN

POATD

AI-AtS

PORT 2

270064-7

10-65

intJ

80C51BH, "1, -2/80C31BH, -1,-2

EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH

ALE

-TLLWL--j----TWLWH-----

TWHQX

..L
PORTO

PORT 2

DATA OUT

P2.0 - P2.7 OR AI - A15 FROM DPH

INSTR
IN

AI - A15 FROM PCH

270064-8

10-66

inter

80C51BH, -1, -2/80C31BH, -1,-2

.

-

i

L
W
z
§

0

...t.
cO

I

!

I!l

:!

I

]-i!i ]-i

Shift Register Mode Timing Waveforms

10·67

intJ

80C51BH, -1, -2/80C31BH, -1, ~2

EXTERNAL CLOCK DRIVE
"

Symbol

Parameter

1/TCLCL

Min

Max

Oscillator Frequency
80C51 BH/80C31 BH
80C51 BH-1/80C31 BH-1
80C51 BH-2/80C31 BH-2 .

3.5
3.5
0.5

12
16
12

20

Units
MHz

ns

TCHCX

High Time

TCLCX

LciwTime

TCLCH

Rise Time

20

ns

TCHCL

Fall Time

20

ns

..

ns

20

SERIAL TIMING-SHIFT REGISTER MODE
Test Conditions: TA

=

O·C to 70·C; Vee

=

5V ±20%; Vss

Parameter···

Symbol

Min
TXLXL

==

OV; Load Capacitance

12 MHzOsc
Max

=

80 pF

Variable Oscillator
Min

Units

Max

1.0

12TCLCL

p.s

700

10TCLCL - 133

ns

TXHQX Output Data Hold After Clock Rising Edge

50

2TCLCL - 117

ns

TXHDX Input Data Hold After Clock Rising Edge

0

0

ns

Serial Port Clock Cycle Time

TQVXH Output Data Setup to Clock Rising Edge

TXHDV Clock Rising Edge to Input Data Valid

700

10TCLCL - 133

ns

EXTERNAL CLOCK DRIVE WAVEFORM.

270064-10

x=.

AC TESTING INPUT, OUTPUT WAVEFORMS

=>(

vee- o.s
0.45 V

0.2 VCC·+O.9
0.2 VCC-O.l

.

FLOAT WAVEFORMS
VOH-O.l V
TIMING REFERENCE
POINTS
'--_ _ _---,_....J~ VOL +0.1 V

-.-=:.::..------

270064-12

270064-11

For liming purposes a port pin is no longer floating when a
100 mV change .from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH ;;, ± 20 rnA. .

AC Inpuls during testing are driven at Vee -.0.5 for a logic "1"
and 0.45 V for a logic "0". Timing measurements are made at VIH
min. for a logic "1" and Vil max. for a logic "0". .

10-68

80C31 BH/80C51 BH
EXPRESS
•

Extended Temperature Range

•

Burn-In

•

3.5 to 12 MHz Vee = 5V± 20%

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS, products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O°C to 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125°C with Vee = '6.9V ±0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheelspecifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed' here.

10-69

September 1987
Order Number: 270218-002

inter

80C31BH/80C51BH EXPRESS

Electrical Deviations from Commercial Specifications for Extended Temperature.
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.

D.C. CHARACTERISTICS TA = -40'C to + 85'C; Vcc = 5V ± 20%; Vss = OV
Symbol
VIL
VIL1
VIH
VIH1
IlL
ITL

LImits

Parameter
Input Low Voltage (Except EA)
EA.
Input High Voltage (Except XTAL1, RST)
Input High Voltage to XTAL 1, RST
Logical 0 Input Current (Port 1, 2, 3)
Logical 1 to 0 transition
Current (Ports 1, 2, 3)

Prefix
P
D
N
TP
TO
TN
OP
OD
ON
LP
LD
LN

Min
-0.5
-0.5V

Max
0.2Vcc - 0.15
0.2Vcc - 0.35

0.2Vcc + 1
0.7Vcc + 0.1

VCC + 0.5
Vcc + 0.5
-75
-750

Table 1 Prefix Identification
Package Type
Temperature Range
Plastic
Commercial
Cerdip
Commercial
PLCC
Commercial
Plastic
Extended
Cerdip
Extended
PLCC
Extended
Plastic
Commercial
Cerdip
Commercial
PLCC
Commercial
Plastic
Extended
Cerdip
Extended
PLCC
Extended

Unit

Test
C~mdltlons

V
V
V
,.
V
jJ-A Vin = 0.45V
jJ-A. Yin = 2.0V

Burn-In
No
No
NoNo
No
No
Yes
Yes
Yes
Yes
Yes
Yes

NOTE:
• Commercial temperature range Is O'C to 70'C. Extended temperature range is -40'C to +85'C.
• Burn·in is dynamic for a minimum time of 160 hours at 125'C. Vee = 6.9V ±0.25V. following guidelines in MIL·STO·883 .
Method 1015 (Test Condition OJ.
Examples:
P80C31 BH indicates 80C31 BH in a plastic package and specified for commercial temperature range, without
burn·in.
LD80C51 BH indicates 80C51 BH in a cerdip package and specified for extended temperature range with burn·
in.

. 10·70

87C51/87C51-1/87C51-2
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 4K BYTES OF EPROM PROGRAM MEMORY
87CS1-3.S to 12 MHz, Vee = sv ± 10%
87CS1-1-3.S to 16 MHz, Vee = SV ± 10%
87CS1-2-0.S to 12 MHz, Vee = SV ± 10%

• High Performance CHMOS EPROM

• Programmable Serial Channel

•

Quick-Pulse Programming™ Algorithm

•

2-Level Program Memory Lock

• TTL- and CMOS-Compatible Logic
Levels

•

Boolean Processor

• 64K External Program Memory Space

• 128-Byte Data RAM
• 32 Programmable I/O Lines
• Two 16-Bit Timer/Counters
•

5 Interrupt Sources

•

64K External Data Memory Space

• IDLE and POWER DOWN Modes
• ONCETM Mode Facilitates System
Testing
•

LCC, PLCC, and DIP Packaging
Available

The 87C51 is the EPROM version of the 80C51 BH. It is fabricated on Intel's CHMOS II-E process. It contains
4K bytes of on-chip Program memory that can be electrically programmed, and can be erased by exposure to
ultraviolet light.
The 87C51 EPROM array uses a modified Quick-Pulse programming algorithm, by which the entire 4K-byte
array can be programmed in about 12 seconds.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue. functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.

r----------

~

270147-1

Figure 1. MCS®-S1 Architectural Block Diagram

10-71

October 1987
Order Number: 270147-004

87C51/87C51-1/87C51-2

P"O

vee

P",

PO.O (AOO)

P"2
P,,3

PO.l (ADI)

P"4

PO.3 (AD3)

P"S

PD.4 (AD4)

PO.2 (AD2)

INDEX
CORNER

"": "! "!

"l u

g"l

ii: ii: ii: ii: ii: z > ~

g

.. ..'"
N

d d

P"6

PO.S (ADS)

PO.4

P"7
RESET

PO.6 (AD6)

PO.S

PO.7 (AD7)

(RXD) P3.0

EA/VPP

(TXD) P3.1

ALE/PROG

(INTO) P3.2

PSEN

(INTI) P3.3

P2.7 (A1S)

(TO) P3.4

P2.6 (AI4)

(T1) P3.S

P2.S (AI3)

(Wil) P3.6

P2.4 (AI2)

(Rli) P3.7

P2.3 (All)

PO.7

EA/Vpp

P3.0
NC

XTAL2

P2.2 (AID)

XTALI

P2.1

VSS

PO.6
RST

Ne

P3.1

ALE/PROG

P3.2

PSEN

P3.3

P2.7'

P3~4

P2.6

P3.S

P2.S

(A9)

.'" ..'"

P2.D (AS)

..;

270147-2

~

N

...J

::;

'"'"

>
~ ~
x

x

u

z

o "-:

..

'"
~ ~ N N
N

270147-21

DIP
LCC/PLCC
Figure 2. Pin Connections .

PIN DESCRIPTION·
Vee: Supply voltage during normal, Idle, and Power
Down operations.
Vss: Circuit ground.
Port 0: Port 0 is an a-bit open drain bidirectional 110
port. As an output port each pin can sink a LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this
application it uses strong internal pullups when emitting 1s.
Port 0 also receives the code bytes'during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
Port 1: Port 1 is an a-bit bidirectional I/O port with
internal pullups. Port 1 pins that have .1 s written to
them are pulled high by the internal pullups,and in
that state can be used as inputs. As inputs, Port 1"
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.

Port 2: Port 2 is an a-bit b.idirectional 110 port with
internal pullups. Port 2 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs.. As inputs, Port 2
pins that are externally being pulled IQw will source
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
address (MOVX @DPTR). In this application it uses
strong internal pullups when emitting 1s.
During accesses to external Data Memory that use
a-bit addresses (MOVX @Ri), Port 2 emits the conter)ts of the P2 Special Function Register.
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification.
Port 3: Port 3 is an a-bit bidirectional 110 port with
internal pullups. Port 3 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups..

Port 1 also receives the low-order address bytes
during EPROM programming and program verification.

10-72

inter

87C51/87C51-1/87C51-2

Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Pin

Name

Alternate Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RXD
TXD
INTO
INT1
TO
T1
WR
RD

Serial input line
Serial output line
External Interrupt 0
External Interrupt 1
Timer 0 external input
Timer 1 external input
External Data Memory Write strobe
External Data Memory Read strobe

XTAL2
XTAL 1

...------t vss
270147-3

Figure 3. Using the On-Chip Oscillator

Port 3 also receives some control signals for
EPROM programming and program verification.
RST: Reset input. A logic high on this pin for two
machine cycles while the oscillator is running resets
the device. An internal pulldown resistor permits a
power-on reset to be generated using only an external capacitor to Vee.

EXTERNAL
OSCILLATOR
SIGNAL

ALE/PROG: Address Latch Enable output signal for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
PSEN: Program Store Enable is the Read strobe to
External Program Memory. When the 87C51 is executing from Internal Program Memory, PSEN is inactive (high). When the device is executing code from
External Program Memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to External
Data Memory.
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the 87C51 to
fetch code from External Program Memory locations
OOOOH to OFFFH. Note, however, that if either of the
Lock Bits is programmed, the logic level at EA is
internally latched during reset.
EA must be strapped to Vee for internal program
execution.
This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier and
input to the internal clock generating circuits.
XTAL2: Output from the inverting oscillator amplifier.

NC -

XTAL2

----I

XTAL 1

270147-4

Figure 4. External Clock Drive

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3.
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.

IDLE MODE
In Idle Mode, the CPU puts itself to sleep while all
the on-chip peripherals remain active. The mode is
invoked by software. The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode. The Idle Mode can be
terminated by any enabled interrupt or by a hardware reset.
It should be noted that when Idle is terminated by a
hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm
takes control. On-Chip hardware inhibits access to
internal RAM in this event, but access to the port

10-73

infef

87C51/87C51-1/87C51-2

Table 1 Status of the external pins during Idle and Power Down
Program
Memory

ALE

PSEN

Idle

Internal

1

1

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Power Down

Internal

0

0

Data

Data

Data

Data

Power Down

External

0

0

Float

Data

Data

Data

Mode

PORTO

PORT1

PORT2

PORT3

NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Application Note AP-252, "Designing with the 80C51BH."

pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that
invokes Idle should not be one that writes to a port
pin or to external memory.

Lock Bits: Also on th'e chip are two Lock Bits which
can be left unprogrammed (U) or can be programmed (P) to obtain the following additional features:
Bit 1

Bit2

Additional Features

POWER DOWN MODE

U

U

none

In the Power Down mode the oscillator is stopped,
and the instruction that invokes Power Down is the
last instruction executed. The on-chip RAM and
Special Function Registers retain their values until
the Power Down mode is terminated.

P

U

• Externally fetched code can not
access internal Program Memory.
• Further programming disabled.

U

P

(Reserved for Future definition.)

P

P

• Externally fetched code can not
access internal Program Memory.
• Further programming disabled.
• Program verification is disabled.

a

The only exit from Power Down is hardware reset.
Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and
must be held active long enough to allow the oscillator to restart and stabilize.

When Lock Bit 1 is programmed, the logic level at
the EA pin is sampled and latched during reset. If
the device is powered up without a reset, the latch
initializes to a random value, and holds that value
until reset is activated. It is necessary that the
latched value of EA be in agreement with the current
logic level at that pin in order for the device to function properly.

DESIGN CONSIDERATIONS
Exposure to light when the device is in operation
may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window
when the die is exposed to ambient light.
If using the 87C51 to prototype for the 80C51 BH,
consult the Design Considerations section of the
80C51 BH data sheet.

ONCETM MODE

PROGRAM MEMORY LOCK
The 87C51 contains two program memory lock
schemes: Encrypted Verify and Lock Bits.
Encrypted Verify: The 87C51 implements a 32byte EPROM array that can be programmed by the
customer, and which can then be used to encrypt
the program code bytes during EPROM verification.
The EPROM verification procedure is performed as
usual, except that each code byte comes out logically X-NORed with one of the 32 key bytes. The key
bytes are gone through in sequence. Therefore, to
read the ROM code, one has to know the 32 key
bytes in their proper sequence.

The ONCE ("on-circuit emulation") mode facilitates
testing and debugging of systems using the 87C51
without the 87C51 having to be removed from the
circuit. The ONCE mode is invoked by:
1. Pull ALE low while the device is in reset and
PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE mode, the PortO pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87C51 is in this mode,
an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal
reset is applied.

10-74

inter

87C51/87C51-1/87C51-2

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O°C to + 70°C
Storage Temperature , ......... - 65°C to + 150°C
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. -0.5V to +6.5V
Power Dissipation .......................... 1.5W
(Based on package heat transfer limitations, not device power consumption).

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE Specifications contained within the
following tables are subject to change.

D.C. CHARACTERISTICS: (TA = O°Cto +70°C;Vcc = 5V ±10%;Vss = OV)
Symbol

Parameter

VIL

Input Low Voltage (Except EA)

VILl

Input Low Voltage to EA

VIH

Input High Voltage (Except XTAL 1, RST)

VIHl

Input High Voltage (XTAL1, RST)

VOL

Max

Unit

-0.5

Min

Typ(1)

.2Vcc-· 1

V

0

.2Vcc-·3

V

.2Vcc+·9

Vcc+·5

V

0.7Vcc

Vcc+·5

V

Output Low Voltage (Ports 1,2, 3)

0.45

V

VOLl

Output Low Voltage (Port 0, ALE, PSEN)

0.45

V

VOH

Output High Voltage (Ports 1. 2. 3, ALE. PSEN)

Test Conditions

IlL

Logical 0 Input Current (Ports 1. 2. 3)

-50

p.A

= 1.6 rnA (2)
= 3.2 rnA (2)
IOH = -60p.A
IOH = -25p.A
IOH = -10 p.A
IOH = -BOO p.A
IOH = - 300 p.A
IOH = -BO p.A (3)
VIN = 0.45 V

IlL

Logicall-to-O transition current
(Ports 1, 2. 3)

-650

p.A

(4)

ILl

Input Leakage Current (Port 0)

±10

p.A

Icc

Power Supply Current:
Active Mode @ 12 MHz (5)
Idle Mode @ 12 MHz (5)
Power Down Mode

25
4
50

rnA
rnA
p.A

300

kfl

_10

pF

VOHl

Output High Voltage (Port 0 in
External Bus Mode)

2.4

V

.75Vcc

V

.9Vcc

V

2.4

V

.75Vcc

V
V

.9Vcc

RRST

Internal Reset Pulldown Resistor

CIO

Pin Capacitance

11.5
1.3
3
50

IOL
IOL

VIN

= VIL or VIH
(6)

NOTES:
1. "Typicals" are based on a limited 'number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp. 5V.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1to-O transitions during bus operations. In the worst cases (capacitive loading> 100pF). the noise pulse on the ALE pin may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger. or use an address latch with a Schmitt
Trigger STROBE input.
'
,
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vcc specification when the address bits are stabilizing.
4. Pins of Ports 1. 2. and 3 source a transition current when they are being externally driven from 1 to O. The transition
current reaches its maximum value when VIN is approximately 2V.
5. IccMAX at other frequencies is given by:

Active Mode: IccMAX = 0.94 x FREQ
Idle Mode:
IccMAX = 0.14 x FREQ

+ 13.71
+ 2.31

where FREQ is the external oscillator frequency in MHz. IccMAX is given in mAo See Figure 5.
6. See Figures 6 through 9 for Icc test conditions.

10-75

87C51/87C51·1/87C51·2

30

IIAX
ACTIVE IIODE

25
RST
20
XTAL2
XTALI

I

VSS

'"E

u
!.!

270147-18
10

Figure 7. Icc Test Condition, Idle Mode.
All other pins are disconnected.

5~--~~+---+---~

TYP(1)

~=±::::::::±:=:t:=J IDLE MODE
4_

SMHz

1211Hz 16MHz

FREQ AT XTAL1 .

270147-16
RST

Figure 5. Icc vs. FREQ. Valid only
within frequency specifications of the
device under test.

XTAL2
XTALI
VSS

270147-20

Figure 9. Icc Test Condition, Power Down
Mode. All other pins are disconnected.
Vce = 2V to 5.5V.
RST

XTAL2
XTALI

Vss
270147-17

Figure 6. Icc Test Condition, Active Mode.
All other pins are disconnected.

270147-19

Figure 8. Clock Signal Waveform for
Icc tests In Active and Idle Modes.
TCLCH = TCHCL = 5 ns.

10-76

inter

87C51/87C51-1/87C51-2

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'r (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they ~tand for.
A:Address.
C:Clock.
D:lnput data.
, H:Logic level HIGH.
1:lnstriJction (program memory contents).

L:Logic level LOW, or ALE.
P:PSEN.
O:Output data.
R:RD signal.
T:Time.
V:Valid.
W:WR signal.
X:No longer a valid logic level.
Z:Float.
For example,
TAVLL
TLLPL

= Time from Address Valid to ALE Low.
=

Time from ALE Low to PSEN Low.

A.C. CHARACTERISTICS: (TA = O°C to + 70°C; Vee = 5V ± 10%; Vss = OV; Load Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol

Parameter

1/TCLCL

Oscillator Frequency
87C51
87C51-1
87C51-2
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instr In
Input Instr Hold After PSEN
Input Instr Float After PSEN
Address to Valid Instr In
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD
Data Float After RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Hold After WR
RD Low to Address Float
RD or WR High to ALE High

TLHLL
TAVLL
TLLAX
TLLlV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TAVIV
TPLAZ
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TWHOX
TRLAZ
TWHLH

12 MHz Oscillator
Max
Min

Variable Oscillator
Min
Max

3.5
3.5
0.5
2TCLCL:"-40
TCLCL-55
TCLCL-35

127
28
48

12
16
12

4TCLCL-100

234
TCLCL-40
3TCLCL-45

43
205

3TCLCL-105

145
0

0

TCLCL-25
5TCLCL-105
10

59
312
10
6TCLCL-100
6TCLCL-100

400
400

5TCLCL-165

252
0

0
97
517
585
300

200
203
23
33

0
123·

43

10-77

3TCLCL-50
4TCLCL-130
TCLCL-60
TCLCL-50
TCLCL-40

2TCLCL-70
8TCLCL-150
9TCLCL-165
3TCLCL+50

0
TCLCL+40

Units

MHz

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

inter

87C51/87CS1-1/87C51-2

ALE _ _J

PSEiii

---

PORT 0

......._ - - '

PORT 2

_ _ _J

AB-A15
270147-5

External Program Memory Read Cycle

ALE

PSEN

I------TLLDV----I'I
----I~---

TRLRH

-----I

PORTO

INSTR. IN
TAVDV

PORT2

P2.0-P2.7 OR AB-A15 FROM DPH

AB-A15 FROM PCH
270147-6

External Data Memory Read Cycle

ALE

PSEN
TLLWL ----1"'1---- TWLWH

PORTO

-

--'----I

DATA OUT

FROM RI OR DPL

INSTR. IN

~---TAVWL---~

PORT 2

P2.0-P2.7 ORAB-A15 FROM DPH

A8-A 15 FROM PCH
270147-7

External Data Memory Write Cycle

10-78

intJ

87C51/87C51-1/87C51-2

EXTERNAL CLOCK DRIVE
Symbol

Parameter

EXTERNAL CLOCK DRIVE WAVEFORM
Min Max Units

1/TCLCL Oscillator Frequency
87CS1
87CS1-1
87CS1-2

3.S
3.S
O.S

12
16
12

MHz

TCHCX

High Time

20

ns

TCLCX

Low Time

20

ns

TCLCH

Rise Time

20

ns

TCHCL

Fall Time

20

ns

270147-8

SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol

12 MHz
Oscillator

Parameter

Min

Variable Oscillator

Max

Min

Units

Max

TXLXL

Serial Port Clock Cycle Time

1.0

12TCLCL

/ls

TOVXH

Output Data Setup to Clock Rising Edge

700

1OTCLCL -133

ns

TXHOX

Output Data Hold After Clock Rising Edge

SO

2TCLCL-117

ns

TXHDX

Input Data Hold After Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to Input Data Valid

1OTCLCL - 133

700

ns

SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION

I

4

5

7.

ALE

CLOCK

OUTPUT DATA

"-----.,."'-----rJ "----_...JX....._-...JX....._-...JX....._-...JX....._-...JX"----_...J!

10

WRITE
'SBUF
INPUT DATA -----"'""'\.,-'"""\,,-"""1... C":":':'r-'r,.,..",'r---,.r:-:-=\,,...-...r:-~~--...r-c:""',,.-. .

I

SET TI
,,.,,.,.:=...,-.. . .,.,,.,.,=",

I.

I

CLEAR RI

SET RI
270147-9

A.C. TESTING:
INPUT, OUTPUT WAVEFORMS

VCC-0.5~ 0.2Vcc+0.9
_ 0.2 Vce-0.1
0.45V ,

FLOAT WAVEFORM

>C
•

~.....;;.;.....-----....

270147-10

270147-11
For timing purposes a port pin is no longer floating when a 100
mV change from load voltage occurs, and begins to float when a
100 mV change from the loaded VOHIVOL level occurs. IOLlioH
;, ±20 rnA.

AC inputs during testing are driven at Vee - 0.5 for a Logic "1"
and 0.45V for a Logic "0." Timing measurements are made at VIH
min for a Logic "I" and VIL max for a Logic "0".

10-79

inter

87C51/87C51-1/87C51-2

to identify the device. The Signature bytes identify
the device as an 87C51 manufactured by Intel.

EPROM CHARACTERISTICS
The 87C51 is programmed by a modified QuickPulse Programming™ algorithm. It differs from Older
methods in the value used for Vpp (Programming
Supply Voltage) and in the width and number of the
ALE/PROG pulses.

Table 2 shows the logic levels for reading the signature byte, and for programming the Program Memory, the Encryption Table, and the Lock Bits. The circuit configuration and waveforms for Quick-Pulse
Programming™ are shown in Figures 10 and 11.
Figure 12 shows the circuit configuration for· normal
Program Memory verification.

The 87C51 contains two signature bytes that can be
read and used by an EPROM programming system

Table 2. EPROM Programming Modes
MODE

RST

PSEN

ALEI
PROG

EAI
Vpp

P2.7

P2.6

P3.7

P3.6

Read Signature

1

0

1

1

0

0

0

0

Program Code Data

1

0

O·

Vpp

1

0

1

1

Verify Code Data

1

0

1

1

0

0

1

1

Pgm Encryption Table

1

0

O·

Vpp

1

0

1

0

Pgm Lock Bit 1

1

0

o·

Vpp

1

1

1

1

Pgm Lock Bit 2

1

0

O·

Vpp

1

1

0

0

NOTES:

(

,

"1" = Valid high for that pin
"0" = Valid low for that pin
Vpp = 12.7SV ± 0.2SV
Vcc = SV ± 10% during programming and verification
*ALE/PROG receives 25 programming pulses while Vpp is held at 12.75V. Each programming pulse is low for 100 ILS{± 10
ILS) and high for a minimum of 10 ILS,

+5V

vee
AO-A7

Pl

PO

RST

P3.6

EA/Vpp
ALE/PROG
87C51

P3.7

PSEN

PGM DATA

+12.75V
25 100)'$ PULSES TO GND
0

P2.7

XTAL2

P2.6

XTAL 1

P2.0
-P2.3

0

A8-All

Vss
270147-12

Figure 10. Programming Configuration

10-80

inter

87C51/87C51-1/87C51-2

,'------25 PULSES

"

1 ..

ALE/PROG:~-----~
'-----'

1'-..
ALE/PROG:

10}'s

I.41N1 "

100!:!s
:t 10}'s

n

aI

"

n

270147-13

Figure 11. PROG Waveforms

Quick-Pulse Programming™
The setup for Microcontroller Quick-Pulse ProgrammingTM is shown in Figure 10. Note that the 87C51
is running with a 4 to 6 MHz oscillator. The reason
the oscillator needs to be running is that the device
is executing internal address and program data
transfers.
The address of the EPROM location to be programmed is applied to Ports 1 and 2, as shown in
Figure 10. The code byte to be programmed into
that location is applied to Port O. RST, PSEN, and
pins of Ports 2 and 3 specified in Table 2 are held at
the "Program Code Data" levels indicated in Table
2. Then ALE/PROG is pulsed low 25 times as
shown in Figure 11.

through 1FH, using the "Pgm Encryption Table" levels. Don't forget that after the Encryption Table is
programmed, verify cycles will produce only encrypted data.
To program the Lock Bits, repeat the 25-pulse programming sequence using the "Pgm Lock Bit" levels. After one Lock Bit is programmed, further programming of the Code Memory and Encryption Table is disabled. However, the other Lock Bit can still
be programmed.
Note that the EA/vpp pin must not be allowed to go
above the maximum specified Vpp level for any
amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The Vpp source should be well regulated and
free of glitches and overshoot.

To program the Encryption Table, repeat the 25pulse programming sequence for addresses 0

10-81

intJ

87C51/87C51-1/87C51-2

+sv

AO-A7

1---1-1' PGt.!

PI

1 - - - . / DATA

RST

EA/Vpp
ALE/PROG

P3.6

B7CSI
P3.7

PSEN 1+---0
P2.7 ....- - 0

(ENABLE)

P2.6 ....- - 0

XTAL2

""''''-r-l XTAL 1
vSS
270147-14

Figure 12. Program Verification

Program Verification

Program/Verify. Algorithms

If Lock Bit 2 has not been programmed, the on-chip
Program Memory can be read out for program verification. The address of the Program Memory location
to be read is applied to Ports 1 ·and 2 as shown in
Figure 12. The other· pins are held at the "Verify
Code Data" levels indicated in Table 2. The contents of the addressed location will be emitted on
Port O. External pullups ·are required on Port 0 for
this operation. Detailed timing specifications are
shown in later sections of this data sheet.

Any algorithm in agreement with the conditions listed in Table 2, and wliich satisfies the timing specifi.
cations, is suitable.

Erasure Character.istics
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.

If the Encryption Table has been programmed, the
data presented at Port 0 will be the Exclusive NOR
of the program byte with one of the encryption bytes.
The user will have to know the Encryption Table
contents in order to correctly decode the verification
data. The Encryption Table itself can not be read
out.

Reading the Signature Bytes
The Signature bytes are read by the same procedure
as a normal verification of locations 030H and 031 H,
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
(030H)

=

(031 H)

= 57H indicates 87C51

The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm 2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all 1s state..

89H indicates manufactured by Intel

10·82

inter

87C51/87C51-1/87C51-2

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS:
(TA = 21°C to 27°C, vee = 5V ±10%, VSS = OV)

Symbol

Parameter

Min

Max

Vpp

Programming Supply Voltage

12.5

13.0

V

Ipp

Programming Supply Current

50

mA

6

MHz

1/TCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG Low

TGHAX

Address Hold After PROG

48TCLCL

TDVGL

Data Setup to PROG Low

48TCLCL

4

Units

48TCLCL

TGHDX

Data Hold After PROG

48TCLCL

TEHSH

P2.7 (ENABLE) High to Vpp

48TCLCL

TSHGL

Vpp Setup to PROG Low

10

fJ-s

TGHSL

Vpp Hold After PROG

10

fJ-s

TGLGH

PROGWidth

90

TAVQV

Address to Data Valid

48TCLCL

TELQV

ENABLE Low to Data Valid

48TCLCL

TEHQZ

Data Float After ENABLE

0

TGHGL

PROG High to PROG Low

10

110

fJ-s

48TCLCL
fJ-s

EPROM Programming and Verification Waveforms
PROGRAMMING-

Pl.0-Plo7
P2.D-P2.3

VERIFICATION-

ADDRESS

ADDRESS
-TAVQY

PORT 0

DATA IN

-I

TDVGL

DATA OUT

~ TGHDX

~

TAVGL ALE/Pi!OO

t-

TSHGL-~:"
-

- TGLGH

TGHAX

_TGHGL
1 _ TGHSL

J
----P2.7
(ENABLE)

LOGIC I
________

LOGIC 1
____

~G~Q

·1. -TEHSH

TELQV-

----,--If

---- ------

-

I-TEHQZ

270147-15
'FOR PROGRAMMING CONDITIONS SEE FIGURE 10.
FOR VERIFICATION CONDITIONS SEE FIGURE 12.

10-83

inter

87C51

EXPRESS
•

Extended Temperature Range

•

Burn-In

•

3.S MHz to 12 MHz Vee

=

SV

± 10%

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O'C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range' of - 40'C to + 85·C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125'C with Vee
guidelines in MIL-STD-883, Method 1015.

= 6.0V ± 0.25V, following

Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.

10-84

October 1987
Order Number: 270430-001

87C51 EXPRESS

Electrical Deviations from Commercial Specifications
for Extended Temperature Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.

D.C. CHARACTERISTICS
Symbol

TA

=

-40·Cto

+ 85·C; Vee =

5V ±10%;Vss

=

OV

Limits

Parameter

VIL

Input Low Voltage (Except EA)

VIL1

EA

VIH

Input High Voltage (Except XTAL 1, RST)

VIH1

Input High Voltage to XTAL 1, RST

Unit

Min

Max

-0.5

0.2Vee - 0.15

V

0

0.2Vee - 0.35

V

+1
+ 0.1

0.2Vee
0.7Vee

Vee
Vee

+ 0.5
+ 0.5

Test
Conditions

V
V

IlL

Logical 0 Input Current (Port 1, 2, 3)

-75

/LA

VIN

ITL

Logical 1 to 0 transition
Current (Ports 1, 2, 3)

-750

/LA

VIN

Icc

Power Supply Current
Active Mode
Idle Mode
Power Down Mode

35

mA
mA
/LA

= 0.45V
= 2.0V

(Note 1)

6
50

NOTE:
1. Vee = 4.5V-5.5V, Frequency Range = 3.5 MHz-12 MHz.

10-85

87C51 EXPRESS

Table 1 Prefix Identification
Prefix

Package Type

Temperature Range(2)

Burn-ln(3)

P

Plastic

Commercial

No

D

Cerdip

Commercial

No

N

PLCC

Commercial

No

R

LCC

Commercial

No

TP

Plastic

Extended

No

TO

Cerdip

Extended

No

TN

PLCC

Extended

No

TR

LCC

Extended

No

OP

Plastic

Commercial

Yes

OD

Cerdip

Commercial

Yes

ON

PLCC

Commercial

Yes

OR

LCC

Commercial

Yes

LP

Plastic

Extended

Yes

LD

Cerdip

Extended

Yes

LN

PLCC

Extended

Yes·

LR

LCC

Extended

Yes

NOTES:
2. Commercial temperature range is O'C to + 70'C. Extended temperature range is - 40'C to + 85'C.
3. Burn-in is dynamic for a minimum time of 160 hours at .+ 125'C, Vee = 6.0V ±0.25V, following guidelines in MIL-STD883 Method 1015 (Test Condition D).

Examples:
P87C51 indicates 87C51 in a plastic package and specified for commercial temperature range, without burn-in.
LD87C51 indicates 87C51 in a cerdip package and specified for extended temperature range with burn-in.
/

10-86

inter

87C51FA (87C252)
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH
PROGRAMMABLE COUNTER ARRAY, UP/DOWN
COUNTER, 8K BYTES USER PROGRAMMABLE EPROM

•
•
•
•

•
•
•
•
•
•

High Performance CHMOS EPROM.
Power Control Modes
Three 16-Bit Timer/Counters
Programmable Counter Array with:
- High Speed Output,
- Compare/Capture,
- Pulse Width Modulator,
- Watchdog Timer capabilities
Up/Down Timer/Counter
Two Level Program Lock System
8K On-Chip EPROM
256 Bytes of On-Chip Data RAM
Quick Pulse Programming™ Algorithm
Boolean Processor

•

32 Programmable I/O Lines

• Programmable Serial Channel with:
• - Framing Error Detection
7 Interrupt Sources

- Automatic Address Recognition

•
•
•
•
•
•

TTL Compatible Logic Levels
64K External Program Memory Space
64K External Data Memory Space
MCS®-51 Fully Compatible Instruction
Set
Power Saving Idle and Power Down
Modes
ONCETM (On-Circuit Emulation) Mode

MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8K bytes of the program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
.
The Intel 87C51 FA is a single-chip control oriented microcontroller which is fabricated on Intel's reliable
CHMOS II-E technology .. Being a member of the MCS®-51 family, the 87C51 FA uses the same powerful
instruction set, has the same architecture, and is pin for pin compatible with the existing MCS-51 products. The
87C51 FA is an enhanced version of the 87C51. It's added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O, and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multi-processor communications.

10-87 .

October 1987
Order Number: 270258-002

87C51FA

PO.0-PO.7

,.----------~~~..:..~

~~

-------- ..

VSS

..r

Pmi
ALE/I'l!l!ll
£A/VPP
RST

z
TIMING

~

~IC==~~=~====~:;:=~==::::===::;::~==J
p::

AND
::>
CONTROL
~
~

;:;

P1.0- P1.7

P3.0-P3.7

270258-1

Figure 1. 87C51FA Block Diagram

10·88

inter

87C51FA

In addition, Port 1 serves the functions of the following special features of the a7C51 FA:

PIN DESCRIPTIONS
(T2) PLO

Port Pin

Vee

(T2EX) Plol

PO.O (ADO)

(ECI) Plo2

PO.l (AD1)

(CEXO) Pl.3

PO.2 (AD2)

(CEX1) Plo4

PO.3 (AD3)

(CEX2) Pl.S

PO.4 (AD4)

(CEX3) Pl.S

PO.S (ADS)

(CEX4) Pl.7

PO.S (ADS)

RESET

PO.7 (AD7)

(RXD) P3.0

EA/Vpp

(TXD) P3.l

ALE/PROG

(iNTO) P3.2

PSEN

(iNT1) P3.3

P2.7 (A1S)

(TO) P3.4

P2.S (A14)

(n) P3.S

P2.S (A13)

(ViR) P3.S

P2.4 (A12)

(Rii) P3.7

P2.3 (All)

XTAL2

P2.2 (Al0)

XTALl

P2.l

Vss

Alternate Function

P1.0

T2 (External Count Input to Timerl
Counter 2)

P1.1

T2EX (Timer/Counter 2 Capturel
Reload Trigger and Direction Control)

P1.2

ECI (External Count Input to the PCA)

P1.3

CEXO (External 1/0 for Comparel
Capture Module 0)

P1.4

CEX1 (External 1/0 for Compare/
Capture Module 1)

P1.5

CEX2 (External 1/0 for Comparel
Capture Module 2)

P1.6

CEX3 (External I/O for Comparel
Capture Module 3)

P1.7

CEX4 (External 1/0 for Comparel
Capture Module 4)

Port 1 receives the low-order address bytes during
EPROM programming and verifying.

(A9)

P2.0 (AB)

Port 2: Port 2 is an a-bit bidirectional 1/0 port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.

270258-2

Figure 2. Pin Connections

Vee: Supply voltage.
Vss: Circuit ground.
Port 0: Port 0 is an a-bit, open drain, bidirectional 1/0
port. As an output port each pin can sink several LS
TIL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting1's, and can source and
sink several LS TIL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistor~ are required during program verification.
Port 1: Port 1 is an a-bit bidirectional 1/0 port with
internal pullups. The Port 1 output buffers can drive
LS TIL inputs. Port 1. pins that have 1's written to
them are pulled high by the internal pull ups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use a-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an a-bit bidirectional 1/0 port with
internal pullups. The Port 3 output buffers can drive
LS TIL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.

10-a9

intJ

87C51FA

Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port Pin

Alternate Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

QSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information. concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrolc
lers."
To drive the device from an external clock source,
XTAL1 should be driven, whileXTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.

RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. An internal pulldown resistor permits a poweron reset with only a capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C51 FA.

C2

I - - t - - - I XTAL2.

1 - -.....--1

In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

XTAL 1

t - - - - - - - I Vss
270258-3
C1, C2 = 30 pF ± 10 pF for Crystals
= 10 pF for Ceramic Resonators

Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.

Figure 3. Oscillator Connections

PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the 87C51FA is executing code from external
Program Memory, PSEN is activated twice.each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.

N/C

XTAL2

EXTERNAL
OSCILLATOR
SIGNAL

XTAL 1

Vss

EAlVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to 1FFFH. Note, however, that if either of the
Program Lock bits are programmed, EA will be internally latched on reset. .
EA should be strapped to Vee for internal program
executions.
.
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.

270258-4

Figure 4. External Clock .Drive Configuration

IDLE MODE
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops execiJting instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.

XTAL2: Output from the inverting oscillator amplifier.
10-90

intJ

87C51FA

POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
On the 87C51 FA either a hardware reset or an external interrupt can cause an exit from Power Down.
Reset redefines all the SFRs but does not change
the on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values.
The interrupt must be enabled and configured as
level sensitive. To properly terminate Power Down
the reset or external interrupt should not be executed before Vee is restored to its normal operating
level, and must be held active long enough for the
oscillator to restart and stabilize.

DESIGN CONSIDERATION
• Ambient light is known to affect the internal RAM
contents during operation. If the 87C51 FA application requires the part to be run under ambient
lighting, an opaque label should,be placed over
the window to exclude light.

• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.

ONCETM MODE
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
87C51 FA without the 87C51 FA having to be removed from the circuit. The ONCE Mode is invoked
by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87C51 FA is in this
mode, an emulator or test CPU can be used to drive
the circuit. Normal operation is restored when a normal reset is applied.

Table 1. Status of the External Pins during Idle and Power Down
Program
Memory

ALE

PSEN

Idle

Internal

1

1

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Mode

PORTO

PORT1

PORT2

PORT3

Power Down

Internal

0

0

Data

Data

Data

Data

Power Down

External

0

0

Float

Data

Data

Data

NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Application Note AP-252, "Designing with the 80C51BH."

10-91

inter

87C51FA

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage t'o the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O°C to + 70°C
Storage Temperature .......... - 65°C to + 150°C
Voltage on EAlVpp Pin to VSS ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. - 0.5V to + 6.5V
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)

NOTICE Specifications contained within the
. following tables are subject to change.

ADVANCED INFORMATION-CONTACT
INTEL FOR DESIGN-IN INFORMATION
.
.
.
D.C. CHARACTERISTICS:
Symbol

(TA

=

,
O°Cto +70°C'Vcc

Parameter

=

Min

,
5V +10%'VsS
-

=

OV)

Max

Unit

-0.5

0.2Vcc-0.1

V

0

0.2 Vcc-0.3

V

0.2Vcc+0.9

Vcc+0.5

V

0.7Vcc

Vcc+ 0.5

V

Test Conditions

VIL

Input Low Voltage

VIL1

Input Low Voltage EA

VIH

Input High Voltage
(Except XTAL2, RST, EA)

VIH1

Input High Voltage
(XTAL, RST)

VOL

Output Low Voltage
(Ports 1 , 2 and 3)

0.45

V

IOL

=

1.6 mA(1)

VOL1

Output Low Voltage _ _
(Port 0, ALE/PROG, PSEN)

0.45

V

IOL

=

3.2 mA(1)

VOH

Output High Voltage
(Ports 1 , 2 and 3
ALE/PROG and PSEN)

2.4

V

IOH

=

-60,..,A

0.9Vcc

V

IOH

VOH1

2.4

V

IOH

0.9VCC

V

IOH

=
=
=
=

-10,..,A(2)

Output High Voltage

0.45V

(Port 0 in Exfernal Bus Mode)

-800,..,A
-80,..,A(2)

IlL

Logical 0 Input Current
(Ports 1 , 2, and 3)

-50

,..,A

VIN

III

Input leaka~Current
(Port 0 and EA)

±10

,..,A

VIN

=

VIL or VIH

ITL

Logical 1 to 0 Transition Current
(Ports 1, 2, and 3)

-650

,..,A

VIN

=

2V

225

KO

10

pF

RRST

RST Pulldown Resistor

CIO

Pin Capacitance

Icc

Power Supply Current:
Running at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode

40

@1MHz, 25°C
(Note 3)

30
7.5
100

rnA
mA
,..,A

NOTES:

1. Capacitive loading on Ports a and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port a and Port 2 pins when these pins make 1 to
a transitions during bus operations. In applications where capacitance loading exceeds 1aa pFs, the noise pulse on the ALE
signal may exceed a.BV. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger. or use an Address Latch
with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports a and 2 cause the VOH on ALE and PSEN to drop below the a.9 Vee specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions.
10-92

intJ

87C51FA

40mA

"'AX.

30mA

ACTIVE
20mA

V

V_ V -

RST
TYPICAL
B7C51FA

....

--

IOmA

r-'DLE

OmA

OMHz

4t.1Hz

XTAL2
XTALl

MAX.
TYPICAL

vss
StAHz

12MHz

16MHz

270258-5

270258-6

ICC Max at other frequencies is given by:
Active Mode
Icc MAX = 2.2 X FREQ + 3.1
Idle Mode
Icc MAX = 0.49 x FREQ + 1.6
Where FREQ is in MHz, IccMAX is given in rnA.

All other pins disconnected
TCLCH = TCHCL = 5 ns

Figure 6. Icc Test Condition, Active Mode

Figure 5. Icc vs Frequency

RST
B7C252
XTAL2
XTALf

Vss

270258-7

270258-8

All other pins disconnected
TCLCH = TCHCL = 5 ns

All other pins disconnected

Figure 9. Icc Test Condition, Power Down Mode.
Vcc = 2.0V to 5.5V.

Figure 7. ICC Test Condition Idle Mode

Vee· a.s • - - - - - -~~----..,.
a.7 vee
a.4SV ---1(a;2 vce-a.t
TCHCL

270258-19

Figure S. Clock Signal Waveform for Icc Tests In Active and Idle Modes. TClCH

10-93

=

TCHCl

=

5 ns.

inter

87C51FA

L: Logic level LOW, or ALE
P:PSEN
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
0: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)

For example,
TAVLL
TLLPL

= Time from Address Valid to ALE Low
= Time from ALE Low to PSEN Low

A.C. CHARACTERISTICS (TA = o·C to + 70·C, Vee = 5V ± 10%, Vss = OV, Load Capacitance for
Port 0, ALE/PROG and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)

ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol

Parameter

12 MHz Oscillator
Min
Max

1/TCLCL Oscillator Frequency

Variable Oscillator
Min
Max
3.5

TLHLL

ALE Pulse Width

127

TAVLL

Address Valid to ALE Low

28

2TCLCL-40
TCLCL-55

~LLAX

Address Hold After ALE Low

48

TCLCL-35

~LLlV

ALE Low to Valid Instruction In

TLLPL

ALE Low to PSEN Low

43

TCLCL-40

~PLPH

PSEN Pulse Width

205

3TCLCL""""45

TPLIV

PSEN Low!o Valid Instruction In

~PXIX
~PXIZ
TAVIV
TPLAZ
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX

Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Address to Valid Instruction In
PSEN Low to Address Float

ns
ns
ns
ns
ns

59

TCLCL-25

ns

312

5TCLCL-105

ns

10

10

ns

6TCLCL-100

WR Pulse Width

400

6TCLCL-100

Data Hold After RD

ns

0

400

RD Low to Valid Data In

ns

3TCLCL-105

RD Pulse Width

ns
5TCLCL-165

252
0

ns

0

ns
ns

Data Float After RD

97

2TCLCL-70

ns

ALE Low to Valid Data In

517

8TCLCL-150

ns

Address to Valid Data In

585

9TCLCL-165

ns

300

3TCLCL-50 3TCLCL+50

ns

ALE Low to RD or WR Low

200

Address Valid to WR Low

203

4TCLCL-130

ns

Address Valid before WR

23

TCLCL-60

ns

~WHQX Data Hold after WR
TRLAZ

145

MHz
ns

4TCLCL-100

234

0

12

Units

TWHLH RD or WR High to ALE High

TCLCL-50

33

RD Low to Address Float

0
43

10-94

123

TCLCL-40

ns
0

ns

TCLCL+40

ns

inter

87C51FA

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE _ _J

PSEN

PORT

a

_ _J

----'

PORT 2 _ _ _J

AB-A15

270258-9

EXTERNAL DATA MEMORY READ CYCLE
ALE

PSEN

1 - - - - - - TLLDV
'I
---0-1---- TRLRH _ - - - I

RD

PORTO

PORT2

INSTR. IN

P2.0-P2.7 OR AB-A15 FROM DPH

AB-A15 FROM PCH

270258-10

EXTERNAL DATA MEMORY WRITE CYCLE
ALE

TLLWL--~---TWLWH---I

I---+---TQVWH - - - - - i
PORTO

PORT2

],--~~-""""Ii.

DATA OUT

P2.0-P2.7 OR AB-A15 FROM DPH

INSTR. IN

AB-A 1 5 FROM PCH

270258-11

10-95

inter

87C51FA

SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: TA = O·C to + 70·C; vee = 5V +
- 10%; Vss = OV; Load Capacitance = 80 pF
Symbol

Variable Oscillator
Max
Min

12 MHz Oscillator
Min
Max

Parameter

Units

TXLXL

Serial Port Clock Cycle Time

1

12TCLCL

TQVXH

Output Data Setup to Clock
RiSing Edge

700

1OTCLCL -133

IJ.s
ns

TXHQX

Output Data Hold after
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After Clock
Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to Input
Data Valid

1OTCLCL -133

700

SHIFT REGISTER MODE TIMING WAVEFORMS

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TCLCL

Oscillator Frequency

3.5

12

MHz

TCHCX

High Time

20

ns

TCLCX

Low Time

20

ns

TCLCH

Rise Time

20

ns

TCHCL

Fall Time

20

ns

EXTERNAL CLOCK DRIVE WAVEFORM

270258-13

10-96

ns

inter

87C51FA

A.C. TESTING INPUT
Input, Output Waveforms

>C

VCC-0.5-=::X: 0.2 VCC+0.9
0.45 V

Float Waveforms

0.2 VCC-O.l

VOH-D.l V

TIMING REFERENCE
POINTS

VOL +0.1 V
270258-15
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH ;, ± 20 mA.

270258-14
AC Inputs during testing are driven at Vee-0.5V for a Logic "1"
and 0.45V for a Logic "0". Timing measurements are made at V,H
min for a Logic "1" and VOL max for a Logic "0".

EPROM CHARACTERISTICS
Table 2 shows the logic levels for programming the
Program' Memory, the Encryption Table, and the
Lock Bits and for reading the signature bytes.
Table 2. EPROM Programming Modes
Mode

RST

PSEN

ALEI
PROG

EAI
Vpp

P2.7

P2.6

P3.6

P3.7

Program Code Data

1

0

O·

Vpp

1

0

1

1

Verify Code Data

1

0

1

1

0

0

1

1

Program Encryption Table
Use Addresses 0-1 FH

1

0

O'

Vpp

1

0

0

1

Program Lock
Bits (LBx)

1
1

0
0

O'
O'

Vpp
Vpp

1
1

1
1

1
0

1
0

1

0

1

1

0

0

0

0

Read Signature

x=1
x=2

NOTES:
"1" = Valid high for that pin
'0" = Valid low for that pin
"VPP" = +12.75V ±0.25V
• ALE/PROG is pulsed low for 100 /Jos for programming. (Quick·PulseProgramming™)

PROGRAMMING THE EPROM
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appro·
priate internal EPROM locations.) The address of an
EPROM location to be programmed is applied to
Port 1 and pins P2.0 • P2.4 of Port 2, while the code
byte to be programmed into that location is applied
to Port O. The other Port 2 and 3 pins, RST PSEN,
and EAIVpp should be held at the "Program" levels
indicated in Table 2. ALE/PROG is pulsed low to
program the code byte into the addressed EPROM
location. The setup is shown in Figure 10.

Normally EAIVpp is held at logic high un_!!!...iust before ALE/PROG is to be pulsed. Then EAIVpp is
raised to Vpp, ALE/PROG is pulsed low, and then
EAIVpp is returned to a valid high Voltage. The volt·
age on the EAIVpp pin must be at the valid EAIVpp
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.
Note that the EAIVpp pin must not be allowed to go
above the maximum specified Vpp level for any
amount of time. Even a narroW glitch above that voltage level can cause permanent damage to the de·
vice. The Vpp source should be well regulated and
free of glitches.

10·97

intJ

87C51FA

+5V
Vee
AO-A7

P1

PO

RST

PGM DATA

EA/Vpp ....--+12.75V
ALE/PROG ....- - 2 5 100}-" PULSES TO GND

P3.6

87C51FA
P3.7

PSEN 1+---0
P2.7
P2:6 ....- - 0

XTAL2

\
P2.0
-P2.4

. XTAL 1.
Vss

270258-20

Figure 10. Programming the EPROM

Quick-Pulse Programming™ Algorithm

Program Verification

The 87C51 FA can be programmed using the Quick. Pulse Programming™ Algorithm for microcontrollers. The fe.?tures of the new programming method
area lower Vpp (12.75V as compared to 21V) and a
shorter programming pulse. It is possible to program
the entire 8K Bytes of EPROM memory in less than
25 seconds with this algorithm!
To program the part using the new algorithm, Vpp
must be 12.75V ±0.25V. ALE/PROG is pulsed low
for 100 ,..,S, 25 times as shown in Figure 11. Then,
the byte just programmed may be verified. After programming, the entire array should be ver.ified. The
Program Lock features are programmed using the
same method, but with the setup aS,shown in Table
2. The only difference in programming Program Lock
features is that the Program Lock features cannot be
directly verified. Instead, verification of programming
is by observing that their features are enabled.

If the Program Lock. Bits have not been programmed, the on-chip Program Memory can be read
out for verification purposes, if desired, either during
or after the programming operation. The address of
the Program Memory location to be read is applied
to Port 1 and pins P2.0 - P2.4. The other pins should
be held at the "Verify" levels indicated in Table 3.
The contents of the addressed locations
come
out on Port O. External pullups are required on Port 0
for this operation.
.

will

If the Encryption Array in the EPROM has been programmed, the data present at Port 0 will be Code
Data. XNOR Encryption Data. The user must know
the Encryption Array contents to manually "unencrypt" the data during verify.
The.setup, which is shown in Figure 12, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an activelow read strobe.

10-98

intJ

87C51FA

1 ~I'------2S PULSES - - - - - . - J ' I

ALE/PROG:---:utJLllJt - - - - -

ULWu-

'--'

1 "-.

ALE/PROG:---":o~I

10}'! MIN1

I'

!~~'t:

'I

nL_____--In. .___

_ _ _ _ _ _...

270258-21

Figure 11. PROG Waveforms

Vee
AD-A7

PO

PI

EA/Vpp

RST
P3.6

ALE/PROG
87CSIFA

P3.7

PSEN ....- - 0
P2.7 1 + - - 0

(ENABLE)

P2.6 1+---0

XTAL2

'--'-"'-:1---1

I-_LJ\. PGM
t - - - - . / DATA

P2.0 1/L--A8-_A 12
-P2.4 \.~-:.;;;....

XTAL 1

Vss
270258-22

Figure 12. Verifying the EPROM

10-99

87C51FA

EPROM Program Lock

Reading the Signature Bytes

The two-level Program Lock system consists of two
Program Lock bits and a 32 byte Encryption Array
which are used to protect the .program memory
.
against software piracy.

The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031 H,
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
(030H) = 89H indicates manufacture by Intel
(031H) = 50H indicates 87C51FA

Encryption Array
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1's), will return the code in it's
original, unmodified form.

Program Lock Bits
Also included in the EPROM Program Lock scheme
are two Program Lock Bits which are programmed
as shown in Table 2.
Table 3 outlines the features of programming the
Lock Bits.
Erasing the EPROM also erases the Encryption Array and the Program Lock Bits, returning the part to
full functionality.

Erasure Characteristics
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it i~ suggested that an opaque label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat"
ed dose of at least 15 W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 p..W/cm rating for 30 minutes, at
distance of about 1 inch,
should be sufficient.

a

Erasure leaves the all EPROM Cells in a 1's state.

Table 3 Program Lock Bits and their Features
Program Lock Bits
LB1
LB2

Logic Enabled

U

U

No Program Lock features enabled. (Code Verify will still be
encrypted by the Encryption Array.)

P

U

MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further programming
of the EPROM is disabled.

P

P

Same as above, but Verify is also disabled

U

P

Reserved for Future Definition

10-100

inter

87C51FA

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
= 21°C to 2rc; Vee = 5V±0.25V; vss = OV)

(TA

ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Units

Symbol

Parameter

Min

Max

Vpp

Programming Supply Voltage

12.5

13.0

V

Ipp

Programming Supply Current

50

mA

6

MHz

1/TCLCL

Oscillator Frequency

4

TAVGL

Address Setup to PROG Low

TGHAX

Address Hold after PROG

48TCLCL

TDVGL

Data Setup to PROG Low

48TCLCL

TGHDX

Data Hold after PROG

48TCLCL

TEHSH

P2.7 (ENABLE) High to Vpp

48TCLCL

TSHGL

Vpp Setup to PROG Low

10

/Ls

TGHSL

Vpp Hold after PROG

10

/Ls

TGLGH

PROG Width

90

TAVOV

Address to Data Valid

48TCLCL

TELOV

ENABLE Low to Data Valid

48TCLCL

TEHOZ

Data Float after ENABLE

0

TGHGL

PROG High to PROG Low

10

48TCLCL

110

/Ls

48TCLCL
/Ls

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING

VERIFICATION

ADDRESS

ADDRESS

Pl.0-Pl.?
P2.0-P2.4

-TAVQV
DATA OUT

PORT 0
TGHDX
TAVGL
ALE/PROG
TSHGLr--TGLGH

EIi/vpp

1
~.-:.-,,","

Vpp

EA/HIGH
TELQVl

P2.?

}

TEHQZ

270258-18

10-101.

83C152A
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER WITH FACTORY

MASK PROGRAMMABLE ROM

80C152A
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER
Data Memory Addressing
• 64KB
256 Bytes On-Chip RAM
• Dual On-Chip DMA Channels
• Hold/Hold Acknowledge
• Two General Purpose Timer/Counters
• 56 Special Function Registers
• 11 Interrupt Sources
• Available in 48 Pin Dual-in-Line Package
• and
68 Pin Surface Mount PLCC

of 80C51BH Architecture
• Superset
Multi-Protocol Serial Communication
• 1/0 Port (1.5 Mbps/2.4 Mbps Max)

•
•
•
•
•

-SDLC
-HDLC
-CSMA/CD
- User Definable Protocols
Full Duplex/Half Duplex
MCS®-51 Compatible UART
12 MHz Maximum Clock Frequency
Multiple Power Conservation Modes
64KB Program Memory Addressing

Package
(See Packaging Spec. Order # 231369)

The 80C152, which is based on the MCS®-51 CPU, is a highly integrated single-chip 8-bit microcontroller
designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated
Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applications. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller
features for peripheral 1/0 interface and control.
Silicon implementations are much more cost effective than multiwire cables found in board level parallel-to-serial and serial-to-parallel converters. The 83C152 contains, in silicon, all the features needed for the serial-toparallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or
fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modularity of hardware and software designs. All of these-cost, network parameter and real estate improvements
apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.
(GRXO)

no

I

(GTDX) Pl.!

2

(DEN) P1.2
(i'Xc) PI.3

:3

(m) PI.4

5

04

P4.6

PO

(RIB) P1.5
(HLDA) PloG

RESET

13

P3.D

14

P3.3

18

Pl.4

19

(TXD) P3.1

(imo)
(iNTi)

P3.2
P3.3

13

N.C.

80C152A

83C152A

N.C.

P2.7
P3.S

P2.6

P3.6

P2.S

P3.7

270188-3
270188-2

Figure 1. Connection Diagrams

10-102

September 1987
Order Number: 270188-003

P4.0-P4.7

P2.0-P2.7

-----"

r

I
I
I
I
I
I

~
c

...CD

~

o m
~·o
oc.J :III"
n

(

SARL1
SARHl
DARLl
DARHl
BCRL1

CD

0

....

0
en
N
l>

C

iii·

...

(Q

DI

TLO

IPNl

THO

IENl

TL1

IP

THl

IE

.....
CD

SBUf(RX)

Co)

~~~f~Tit~

....0en

SCON

N

l>

3

~
'lEJ

aID
Iiiiil
IF'

ADRO-3
BAUD

P1.0- P1.7

_-.J
P3.0- P3.7

270188-1

~
~
~

aID
~

inter

80C152A/83C152A

Pin #
PLCC(1)
DIP
48
2
3,33(2)
24
18-21, 27-30,
25-28
34-37

1-8

4-11

29-36

41-48

10-17

14-16,
18,19,
23-25

Pin Description
Vcc-Supply voltage.
Vss-Circuit ground.
Port O-Port 0 is an 8-bit open drain bidirectional 110 port. As an output port each pin
can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external memory. In this application it uses strong internal pullups when emitting 1s.
Port 0 also outputs the code bytes during program verification. External pull ups are
.
required during program verification.
Port 1-Port 1 is an 8-bit bidirectional 1/0 port with internal pullups. Port 1 pins that
have 1s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
Port 1 also serves the functions of various special features of the 8XC152, as listed
below:
Pin
Name
Alternate Function
P1.0
GRXD
GSC data input pin
P1.1
GTXD
GSC data output pin
P1.2
DEN
GSC enable signal for an external driver
P1.3
TXC
GSC input pin for external transmit clock
P1.4
RXC
GSC input pin for external receive clock
P1.5
HLD
DMA hold input/output
P1.6
HLDA
DMA hold acknowledge input/output
Port 2-Port 2 is an 8~bit bidirectional 1/0 port with internal pullups. Port 2 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally being pulled IQw will source
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program
Memory and during accesses to external Data Memory that use 16-bit addresses
(MOVX @ DPTR and DMAoperations). In this application it uses strong internal pullups
when emitting 1s.
During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program verification.
Port 3-Port 3 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 3 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special features of the MCS-51 Family, as
listed below:
Pin
Name
Alternate Function
P3.0.
Serial input line
RXD
P3;1
TXD
Serial output line
P3.2
INTO
External Interrupt 0
P3.3
INT1
External Interrupt 1
P3.4
Timer 0 external input
TO
P3.5
T1
Timer 1 external input
P3.6
WR
External Data Memory Write strobe
P3.7
RD
External Data Memory Read strobe

NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.

10-104

intJ

80C152A/83C152A

Pin Description (Continued)
Pin #

Pin Description

47-40

65-58

Port 4-Port 4 is an 8-bit bidirectional 1/0 port with internal pullups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups. In addition,
Port 4 also receives the low-order address bytes during program verification.

9

13

RST-Reset input. A logic low on this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a power-on
reset to be generated using only an external capacitor to Vss. Although the GSC
recognizes the reset after three machine cycles, data may continue to be
transmitted for up to 4 machine cycles after Reset is first applied.

38

55

ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory.
.
In normal operation ALE is emitted at a constant rate of % the oscillator
frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data
Memory. While in Reset, ALE remains at a constant high level.

37

54

PSEN-Program Store Enable is the Read strobe to External Program Memory.
When the 8XC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.

39

56

EA-External Access enable. EA must be externally pulled low in order to enable
the 8XC152 to fetch code from External Program Memory locations OOOOH to
OFFFH.
EA must be connected to Vee for internal program execution.

23

32

XTAL 1-lnput to the inverting oscillator amplifier and input to the internal clock
generating circuits.

22

31

XTAL2-0utput from the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.
.

XTAL2
XTAL 1

t - - - - - - I Vss

,270188-4
Figure 3. Using the On-Chip Oscillator

NC
EXTERNAL
OSCILLATOR
SIGNAL

XTAL2
XTAL 1

Vss

270188-5

Figure 4. External Clock Drive

10-105

.

infef

80C152A/83C152A

IDLE MODE

POWER DOWN MODE

In Idle Mode, the CPU puts itself to sleep while most
of the on-chip peripherals remain active. The major
peripherals that do not remain active during Idle, are
the DMA channels. The Idle Mode is invoked by
software. The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode. The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset.

In Power Down Mode, the oscillator is stopped and
. all on-chip functions cease except that the on-chip
RAM contents are maintained. The mode Power
Down is invoked by software.. The Power Down
Mode can be terminated only by a hardware reset.

Table 1. Status of the external pins during Idle and Power Down modes
Mode

Program
Memory

,
. ALE

PSEN

PortO

Port 1

Port 2

Port 3

Port 4

Idle

Internal

1

1

Data

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Data

Power Down

Internal

0

0

Data

Data

Data

Data

Data

Power Down

External

0

0

Float'

Data

Data

Data

Data

NOTE:
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application
Note AP-252, "DeSigning with the 80C51BH."

10-106

intJ

80C152A183C152A

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O·C to + 70·C
Storage Temperature .......... - 6S·C to + 1S0·C
Voltage on Any pin to Vss .. - O.SV to (Vee + O.SV)
Voltage on Vee to VSS ........... -O.SVto +6.SV
Power Dissipation ....................... 1.0 W(7)

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE: Specifications contained within the
following tables are subject to change.

D.C. CHARACTERISTICS
Symbol

(TA = O·C to + 70·C; Vee = SV ± 10%; Vss = OV)

Parameter

Typ
(Note 1)

Max

Unit

-O.S

0. 2Vee- 0.1

V

-O.S

0.2Vee- 0.3

V

0.2Vee+ 0.9

Vee+ O.S

V

0.7Vee

Vee+ O.S

V

Min

Test Conditions

V,L

Input Low Voltage
(All Except EA)

V,L1

Input Low Voltage
(EA)

V,H

Input High Voltage
(Except XTAL 1, RST)

V,H1

Input High Voltage
(XTAL 1, RST)

VOL

Output Low Voltage
(Ports 1, 2, 3, 4)

0.45

V

IOL = 1.6 mA
(Note 2)

VOL1

Output Low Voltage
(Port 0, ALE, PSEN)

0.45

V

IOL =3.2mA
(Note 2)

VOH

Output High Voltage
(Ports 1, 2, 3, 4,
ALE, PSEN)

V

IOH = -60p..A
Vee = SV ±10%

V

IOH = -10 p..A

V

IOH = -400 p..A
Vee = SV ±10%

-

2.4
0.9Vee •

VOH1

Output High Voltage
(Port 0 in External
Bus Mode)

2.4

V

IOH = -40 p..A (Note 3)

I,L

Logical 0 Input
Current (Ports 1, 2, 3, 4)

-so

p.A

V,N = O.4SV

ITL

Logical 1 to 0
Transition Current
(Ports 1, 2, 3, 4)

-6S0

p.A

V,N = 2V

III

Input Leakage
(PortO, EA)

±10

p.A

O.4S.100 pF), the noise pulse on the ALE pin may
exceed o.av. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
S. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vcc specification when the address bits are stabilizing.
4. Icc is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, ~ = VSS + 0.5V, VIH =
~ - 0.5V; XTAL2 N.C.; Port 0 pins connected tei Vc~'Operating" current is measured with EA connected to Vee and
RST connected to Vss. "Idle" current is measured with EA connected to Vss, RST connected to Vcc and GSC inactive.
5. The specifications relating to external data memory characteristics are also applicable to DMA operations.
6. TOVWX should not be confused with TOVWX as specified for aOC51BH. On aOC152, TOVWX is measured from data
valid to rising edge of WR. On aOC51BH, TOVWX is measured from data valid to falling edge of WR. See timing diagrams.
7. This value is based on the maximum allowable die temperature and the thermal resistance of the package.

.

.

MAX Icc (ACTIVE) =(2.24 X FREQ) + 4.16 (Note 4)
MAX Icc (IDLE) = (0.8 X FREQ) + 2.2 (Note 4)
where FREQ is the external oscillator Frequency in Megahertz and Icc is in Milliamps
45
40

35
30

'<

.§.
~

25
20
15
10
5
0

./

'"

/"

/ " ......
./'

~4

MAX Icc
(ACTIVE) (NOTE 4)

~

--

TYPICAL Icc
(ACTIVE) (NOTE 1)
MAX Icc
(IDLE) (NOTE 4)
TYPICAL Icc
IDLE (NOTE 1)

12

8

FREQUENCY (MHz)

270188-17

Figure 5. icc vs Frequency

EXPLANATION OF THE AC SYMBOLS

I: Instruction (program memory contents).
L: Logic level LOW, or ALE.
P: PSEN.
Q: Output data.
R: READ signal.
T: Time.
V: Valid.
W: WRITE signal.
X: No longer a valid logic level.
Z: Float.

Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
, the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A:
C:
0:
H:

Address;
Clock
Input data.
Logic level HIGH.

For example,
TAVLL = Time for Address Valid to ALE Low..
TLLPL = Time for ALE Low to PSEN Low.

10-108

intJ

80C152A183C152A

A.C. CHARACTERISTICS (TA = O·C to + 70·C; Vee = 5V ± 10%; Vss = OV; Load Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol

12MHz

Parameter

Min

Max

(Note 5)

Variable Oscillator
Min

Max

3.5

12

Unit
MHz

1/TCLCL

Oscillator Frequency

TLHLL

ALE Pulse Width

126

2TCLCL-40

ns

TAVLL

Address Valid to ALE Low

28

TCLCL-55

ns

TLLAX

Address Hold After ALE Low

48

TLLlV

ALE Low to Valid
Instruction In

TLLPL

ALE Low to PSEN Low

43

TCLCL-40

ns

TPLPH

PSEN Pulse Width

205

3TCLCL-45

ns

TPLIV

PSEN Low to Valid
Instruction In

TPXIX

Input Instruction
Hold After PSEN

TPXIZ

Input Instruction
Float After PSEN

58

TCLCL-25

ns

TAVIV

Address to Valid
Instruction In

311

5TCLCL-105

ns

TPLAZ

PSEN Low to Address
Float

10

10

ns

TCLCL-35
233

145
0

ns
4TCLCL-100

3TCLCL-105

AD Pulse Width

400

6TCLCL-100

TWLWH

WA Pulse Width

400

6TCLCL-100

TALDV

AD Low to Valid
Data In

TAHDX

Data Hold After AD

TAHDZ

Data Float After AD

251
0

ns
ns

0

TALAH

ns

ns
ns
5TCLCL-165

ns
ns

0
96

2TCLCL-70

ns

TLLDV

ALE Low to Valid
'Data In

516

8TCLCL-150

ns

TAVDV

Address to Valid
Data In

585

9TCLCL-165

ns

TLLWL

ALE Low to AD or
WALow

200

3TCLCL+50

ns

TAVWL

Address to RD or
WALow

203

4TCLCL-130

ns

TOVWX
(Note 6)

Data Valid to WA
Transition

333

6TCLCL-167

ns

TWHOX

Data Hold After WA

33

TALAZ

AD Low to Address
Float

TWHLH

RD or WR High to
ALE High

300

3TCLCL-50

TCLCL-50
0

43

10-109

123

TCLCL-40

ns
0

ns

TCLCL+40

ns

inter

80C152A/83C152A

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE

_ _J

rssEN

_ _J

PORT 0 _ _..I

PORT 2

___

,~

______

~~~

_______

n~

______
AB-A'15 _____
~

270188-6

EXTERNAL DATA MEMORY READ CYCLE

ALE

PSEN

,

I-----TLLDV------l.,

- - i - - - TRLRH - - - I

PORTO'

PORT2

INSTR. IN

P2.0-P2.7 OR AB-A15 FROt.! DPH

A8-A 15 FROt.! PCH
270188-7

10-110

80C152A/83C152A

EXTERNAL DATA MEMORY WRITE CYCLE

,

ALE

I

\.

P

TWHlH

\.

PSEN

I+-- TlLWL

~

WR

,I

TOVWX

--

PORTO

~

TWlWH

::::r

- r-

TAVll ~TLLAX~
AO-A7 FROM R. OR DPL )

TWHOX

X XAO-A7 FROM PCl

DATA OUT

INSTR. IN

TAVWl
'PORT 2

-

~

P2.0-P2.7 OR A8-A15 FROM DPH

A8-A15 FROM PCH

X

270188-8

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max·

Units

1/TClCl

Oscillator Frequency

3.5

12

MHz

TCHCX

High Time

20

ns

TClCX

low Time

20

ns

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

EXTERNAL CLOCK DRIVE WAVEFORM

270188-9

10-111

inter

80C152A183C152A

LOCAL SERIAL CHANNEL TIMING":"SHIFT REGISTER MODE
Symbol

12MHz

Parameter

Min.

Variable Oscillator

Max

Units

Max

Min

TXLXL

Serial Port Clock Cycle
Time

1000

12TCLCL

ns

TQVXH

Output Data Setup to
Clock Rising Edge

700

10TCLCL-133

ns

TXHQX

Output Data Hold After
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

700

10TCLCL-133

ns

SHIFT REGISTER MODE TIMING WAVEFORMS

ALE

CLOCK

'--_~ '----r' '--_--'X'-__.JX

OUTPUT DATA

4

X

t

x...._--IX....

1

--.;..-J

t

SET TI

WRITE TO SBur
INPUT DATA

5

_____

--'~J~--'

t

t

CLEAR RI

SET RI

270188-10

A.C. TESTING:
INPUT, OUTPUT WAVEFORMS

VCC-o.S =X0.2VCC+O.9
0.4SV

FLOAT WAVEFORM

)C,

0.2Vcc-O.l

~.....;;;;:..------

270188-11

270188-12
For Timing Purposes a Port Pin is no Longer Floating when a 100
mV change from Load Voltage Occurs, and Begins to Float when·
a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH ~ ± 20 rnA

AC Inputs During Testing are Driven at Vee-O.S for a Logic "1"
and O.4SV for a Logic "0". Timing Measurements are made at VIH
Min for a Logic "1" and Vil Max'for a Logic '~O".

10-112

inter

80C152A/83C152A

GLOBAL SERIAL PORT TIMINGS-Internal Baud Rate Generator
,
Symbol

12 MHz (BAUD = 0)

Parameter

Min

Variable Oscillator

Max

Min

Unit

Max

HBTJR

Allowable jitter on
the Receiver for %
bit time (Manchester
encoding only)

0.058

(0.125 x
(BAUD+1)X
8TCLCL)
-25 ns

fJ.s

FBTJR

Allowable jitter on
the Receiver for one
full bit time (NRZI
and Manchester)

0.142

(0.25 x
(BAUD+1)X
8TCLCL)
-25 ns

fJ.s

HBTJT

Jitter of data from
Transmitterfor %
bit time (Manchester
encoding only)

±35

±35

ns

FBTJT

Jitter of c;lata from
Transmitter for one
full bit time (NRZI
and Manchester)

±70

±70

ns

DRTR

Data rise time for
Receiver (Note 8)

20

20

ns

DFTR

Data fall time for
Receiver (Note 9)

20

20

ns

NOTES:
8. Same as TCLCH, use External Clock Drive Waveform.
9. Same as TCHCL, use External Clock Drive Waveform.

GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR)

BT

II
I

MANCHESTER

:::::x:
I
I

NRZ1:::::X:

~i~
:-~
I

I

HBTJR

I
I

'I
I

~~-+
X ~

I

I

~,
I

~

t,1

,~

I

FBTJR

I

C::::

GRXD

I
I

GRxD

I

FBTJR
270188-13

10-113

intJ

80C152A/83C152A

GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR)
t+'----

I'

MANCHESTER.

*
BT

----~·I

I

I

1......1.....

I

x::::
4$::,==.~~:==.$r'______. . . x::::

::::l---.. .$~,. . ~'lo...----i--"""jolo"--.J.I~1
$
$ *$

GTxD

I

I _ _ _ _~HB~T~JT~~~__....I~-~-~FB~T~JT----....I
NRZI=::J!(_ _ _ _ _ _ _

GTxD

FBTJT
270188-14

GLOBAL SERIAL PORT TIMINGS-External Clock
Symbol

12MHz

Parameter'

Variable OSCillator

Min

Max

Min

Max

0.009

2.4

0.009

1/5TClCl

Unit

1/ECBT

GSC Frequency with an
External Clock

ECH

External Clock High

197

2TClCl
+ 30ns

ns

ECl

External Clock low

197

2TClCL
+ 30ns

ns

ECRT

External Clock Rise
Time (Note 8)

20

20

ns

ECFT

External Clock Fall
Time (Note 9)

20

20

ns

ECDVT

External Clock to Data
Valid Out - Transmit
(to External Clock
Negative Edge)

150

150

ECDHT

External Clock Data
Hold - Transmit
, (to External Clock
Negative Edge)

MHz

ns

,
ns
0

0

ECDSR

External Clock Data
Set-up - Receiver
(to External Clock
Positive Edge)

45

45

ns

ECDHR

External Clock to Data
Hold - Receiver
(to External Clock
Positive Edge)

50

50

ns

10-114

inter

SOC152A1S3C152A

GSC TIMINGS (EXTERNAL CLOCK)
t+·----ECBT----~·1

-----x

1

EXTERNAL CLOCK

1

'X

f.

I

t---ECL-----::--- ECH ----.: 1
_ _...;...1
~ : - ECDVT
TRANSMIT DATA
:

:x:r--.;;..;..;.------.;....,;.-.-

X

ECDHT ~
141· - - - - E C B T
1
EXTERNAL CLOCK -----X""I_ _ _ _
1

'I

1

Ji:,-----X

--' ECDSR '-ECDHR--'

_ _"""1"'_ _ '

RECEIVE DATA

X

_ _....._....J,

:+
1

I~---"""''----

'--_ _ _..J

,

Xr...,..---------.....;i--, _ " -_ _ _ _ _ _ _ _ _......_ _
270188-15

10-115

80C152A/83C152A

NOTES ON THE OPERATION OF THE
80C152A
1. Current in Power Down Mode
Typically, Icc in Power Down Mode is about
·10 ""A. However, you may note under certain conditions an abnormally high Icc, about 600 ""A, in
Power Down. This is caused by an interaction between internal signals local to the interrupt control
system. The problem disappears once an interrupt, any interrupt, is requested and serviced.
Therefore, if Icc in Power Down is critical to the
application, it is suggested that an interrupt be
generated and exercised before Power Down is
invoked.

2. SDLe Flags While Idling
In SDLC Mode, the GSC can be programmed to
transmit SDLC flags between transmission
frames. This is done by setting the GFIEN bit in
PCON. When the GSC is so programmed, the
DEN signal is asserted only during the actual
transmission frame, not during the idle fill flags. In
this case the DEN signal will normally not be used
to enable the line driver, but is available for use as
a positive indication that a transmission frame is
in progress.
3. Immediate Deactivation of DEN in CSMAlCD
Mode
CSMAlCD protocols typically require two bittimes .of inactivity in the line to indicate an idle
condition. Note, however, that the 80C152A deac. tivates DEN immediately at the end of the transmission frame.

10-116

83C 152JA/83C 152JA-1
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER WITH FACTORY MASKED
PROGRAMMABLE ROM
80C152JA/80C152JA-1
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER
80C152JB/80C152JB-1
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER WITH EXTENDED 1/0
•

Superset of 80C51 Architecture

•

64KB Data Memory Addressing

•

Multi-Protocol Serial Communication
I/O Port (2.048 Mbps/2.4 Mbps Max)
-SDLC
-HDLC
-CSMAlCD
- User Definable Protocols

•

256 Bytes On-Chip RAM

•

Dual On-Chip DMA Channels

•

Hold/Hold Acknowledge

•

Two General Purpose Timer/Counters

•

56 Special Function Registers

•

Full Duplex/Half Duplex

•

MCS®-51 Compatible UART

•

16.5 MHz Maximum Clock Frequency

•

Multiple Power Conservation Modes

•

64KB Program Memory Addressing

•

11 Interrupt Sources

•

Available in 48 Pin Dual-in-Line Package
and 68 Pin Surface Mount PLCC
Package
(See Packaging Spec. Order #231369)

The 80C152, which is based on the MCS®-51 CPU, is a highly integrated single·chip 8·bit microcontroller
designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated
Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applications. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller
features for peripheral 1/0 interface and control.
Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-toserial and serial-to-parallel ~onverters. The 83C152 contains, in silicon, all the features needed for the serialto-parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or
fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modularity of hardware and software designs. All of these-cost, network parameter and real estate improvementsapply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.

10-117

September 1987
Order Number: 270431-001

inter

~[Q)W~OO©[§ OOOIP@OOINl~"iiO@OO

80C152JAl83C152JA/80C152JB

(GRXO)

vee

(GTOX)

P4.0

(DEN)

P4.1

(TXC)
(RxC) P1.4

P4.3

INDEX
CORNER'\,.

: i. :. i
N

.,

P"',5
P4.6

N.C.

P4.7

(HLO) P1.S

P4.4

P4.5

Pl.7

P4.6

P3.1

P4.7

P3.2

N.C.

EA

P3.0

EA

(TXO) P3.1

~

Pl.7

(HLOA) P1.6
RESET

q 

~

.,.

P2.4
P2.3

i;; :ll III ~ :;; ~ ~

....

"~ ~ d ~ ~

"! C!
~ .~

~

Figure 1. Connection Diagrams

10·118

OJ

~

270431-3

·P6.0-P6.7

P4.0-P4.7

PO.O-PO.7

P2.0-P2.7

-----11

t

SARL1
SARHI
OARL1
OARHI
CI)

BCRL1

o

....CJI

(")

~

l>
......
CI)

."

Co)

iD:
c

...CD

1.£1

!'l
UJ
'?
..... 0'
n

CO

;I;'

C

iii"
ce

...
DI

3

....CJI

(")
N
Co.

em
,

·EBEN

l>

~

~

......
CI)
o

I"~

THO

....(")CJI

TLI

~

THI

a:J

~

~
l§!

~

;:;g

©

IiiiiI

~

'liil

©

ADRD-3
BAUD

Pl.0- P1.7

'On 80C152JB Only

_-.J
P3.0-P3.7

270431-4

2&
~
~
~

<=

©

~

intJ

80C152JAl83C152JA/80C152JB

80C152JB General Description
The 80C152JB is a ROM less extension of the
aOC152 Universal Communication controller. The
80C152JB has the same five 8-bit I/O ports of the
80C152, plus an additional two 8-bit 1/0 ports, Port 5
, and Port 6. The 80C152JB also has two additional
control pins, EBEN (EPROM Bus ENable), and
EPSEN (EPROM bus Program Store ENable).
EBEN selects the functionality of Port 5 and Port 6.
When EBEN is low, these ports are strictly I/O, similar to Port 4. The SFR location for Port 5 is 91 Hand
Port 6 is OA 1H. This means Port 5 and Port 6 are not
bit addressable. With EBEN low, all program memorY fetches take place via Port 0 and Port 2. (The
80C152 is a ROMless only product). When EBEN is
high, Port 5 and Port 6 form an address/data bus
called the E-Bus (EPROM-Bus) for program memory
'
operations.

~@w~oo©~ DOOIP©OOIMl~'jj'D©OO

EPSEN is used in conjunction with Port 5 and Port 6
program memory operations. EPSEN functions like
PSEN during program memory operation, but supports Port 5 and Port 6. EPSEN is the read strobe to
externai program memory for Port 5 and Port 6.
EPSEN is activated twice during each machine cycle
unless an external data memory operation occurs on
Port(s) 0 and Port 2. When external data memory is
accessed the second activation of EPSEN is
skipped, which is the same as when using PSEN.
Note that data memory fetches cannot be' made
through Ports 5 and 6.
When EBEN is high and EA is low, all program memory operations take place via Ports 5 and 6. The high
byte of the address goes out on Port 6, and the low
byte is output on Port 5. ALE is still used to latch the
address on Port 5. Next, the op code is read on Port
5. The timing is the same as when using Ports 0 and
2 for external program memory operations.

Table 1. Program Memory Fetches
EBEN

EA

Program
Fetch via

0

0

PO,P2

PSEN

EPSEN

Comments

Active

Inactive

Addresses O-OFFFFH

0

1

N/A

N/A

N/A

1

0

P5,P6

Inactive

Active

Addresses O-OFFFFH

1

1

P5,P6
PO,P2

Inactive
Active

Active
Inactive

Addresses 0-1 FFFH
Addresses :?: 2000H

10-120

Invalid Combination

inter

SOC 152JAlS3C 152JAlSOC152JB

Pin #
PLCC(1)

DIP
48

~@W~OO©[§ OOO[F@OOIM]~'iiO@OO

Pin Description

2
3,33(2)

Vee-Supply voltage.

24
18-21,
25-28

27-30,
34-37

Port O-:-Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin
can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled low. During accesses to external Data
Memory, Port 0 always emits the low-order address byte and serves as the multiplexed
data bus. In these applications it uses strong internal pullups when emitting 1s.
Port 0 also outputs the code bytes during program verification. External pullups are
required during program verification~

1-8

4-11

Port 1-Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pull ups.
Port 1 also serves the functions of various special features of the 8XC152, as listed
below:

Vss-Circuit ground.

Pin
P1.0
P1.1
P1.2
P1.3
P1,4
P1.5
P1.6

Name

Alternate Function
GSC data input pin
GSC data output pin
GSC enable signal for an external driver
GSC input pin for external transmit clock
GSC input pin for external receive clock
DMA hold input/ output
DMA hold acknowledge input/output

GRXD
GTXD
DEN
TXC
RXC
HLD
HLDA

29-36

41-48

Port 2-Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that
have 1 s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 2. pins that are externally being pulled low will source.
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled low. During accesses to external Data Memory that use 16bit addresses (MOVX @ DPTR and DMA operations), Port 2 emits the high-order
address byte. In these applications it uses strong internal pullups when emitting 1s.
During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program verification.

10-17

14-16,
18,19,
23-25

Port 3-Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that
have 1s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special features of the MCS-51 Family, as
listed below:
Pin

..

P3.0
P3.1
P3.2
P3.3
P3,4
P3.5
P3.6
P3.7

Name

Alternate Function
Serial input line
Serial output line
External Interrupt 0
External Interrupt 1
Timer 0 external input
Timer 1 external input
External Data Memory Write strobe
External Data Memory Read strobe

RXD
TXD
INTO
INT1
TO
T1
WR
RD

NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.

10-121

.

inter

80C152JAl83C152JA/80C 152JB

~1ID\Yl~OO©[§ OOO!F©OO!MI~ii"O©OO

Pin Description (Continued)
Pin #

Pin Description

47-40

65-58

Port 4-Port 4 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (Ill, on the data sheet) because of the internal pullups. In addition,
Port 4 also receives the low-order address bytes during program verification.

9

13

RST-Reset input. A logic low on this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a power-on
reset to be generated using only an external capacitor to Vss. Although the GSC
recognizes the reset after three machine cycles, data may continue to be
transmitted for up to 4 machine cycles after Reset is first applied.

38

55

ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory.
In normal operation ALE is emitted at a constant rate of % the oscillator
frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data
Memory. While in Reset, ALE remains at a constant high level.

37

54

PSEN-Program Store Enable is the Read strobe to External Program Memory.
When the 8XC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.

39

56

EA-External Access enable. EA must be externally pulled low in order to enable
the 8XC152 to fetch code from External Program Memory locations OOOOH to
OFFFH.
EA must be connected to Vee for internal program execution.

23

32

XTAL 1-lnput to the inverting oscillator amplifier and input to the internal clock
generating circuits.

22

31

XTAL2-0utput from the inverting oscillator amplifier.

N/A

17,20
21,22
38,39
40,49

Port 5-Port 5 is an 8-bit bidirectional 1/0 port with internal pullups. Port 5 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 5 pins that are externally being pulled low will
source current (Ill, on the data sheet) because of the internal pullups.
Port 5 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled high. In this application it uses strong
pull ups when emitting 1s.

N/A

67,66
52,57
50,68
1,51

Port 6-Port 6 is an 8-bit bidirectional 1/0 port with internal pullups. Port 6 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 6 pins that are externally pulled low will source
current (Ill, on the data sheet) because of the internal pullups.
Port 6 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled high. In this application it uses strong pull ups when
emitting 1s.

N/A

12

EBEN-E-Bus Enable input that designates whether program memory fetches take
place via Ports O.and 2 or Ports 5 and 6. Table 1 shows how the ports are used-in
conjunction with EBEN.

53

EPSEN-E-bus Pr9gram Store Enable is the Read strobe to external program
__
memory when EBEN is high. Table 2,shows when EPSEN is used relative to PSEN
depending on the status of EBEN and EA.

,

10-122

80C152JA/83C152JA/80C152JB

~(Q)W~OO©~ OOOIF@OOIMl~liO@OO

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3.

NC -

XTAL2

EXTERNAL
OSCILLATOR - - - - I XTAL 1
SIGNAL

To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.

~L.v_s_s__
270431-6

Figure 4. External Clock Drive

IDLE MODE
In Idle Mode, the CPU puts itself to sleep while most
of the on-chip peripherals remain active. The major
peripherals that do not remain active during Idle, are
the DMA channels. The Idle Mode is invoked by
software. The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode. The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset.

XTAL2
XTAL 1

+-------1 vss
270431-5

POWER DOWN MODE

Figure 3. Using the On-Chip Oscillator

In Power Down Mode, the oscillator is stopped and
all on-chip functions cease except that the on-chip
RAM contents are maintained. The mode Power
Down is invoked by software. The Power Down
Mode can be terminated only by a hardware reset.
Table 2. Status of the External Pins During Idle and Power Down Modes

80C152JAl83C152JA
Program
Memory

ALE

Idle

Internal

1

1

Data

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Data

Power Down

Internal

0

0

Data

Data

Data

Data

Data

Power Down

External

0

0

Float

Data

Data

Data

Data

Mode

PSEN

Porta

Port 1

Port 2

Port 3

Port 4

80C152JB
Mode

Instruction
ALE PSEN EPSEN Porta Port 1
Bus

Idle

PO,P2

1

1

1

Port 2

Port 3 Port 4 Port 5

Float

Data

Address

Data

Data

OFFH

Port 6
OFFH

Idle

P5,P6

1

1

1

Data

Data

Data

Data

Data

OFFH Address

Power Down

PO,P2

0

0

1

Float

Data

Data

Data

Data

OFFH

OFFH

Power Down

P5,P6

0

1

0

Data

Data

Data

Data

Data

OFFH

OFFH

NOTE:
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application
Note AP-252, "Designing with the 80C51BH."

10-123

intJ

80C152JA/83C152JA/80C152JB

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O·C to

+ 70·C

Storage Temperature .......... - 65·C to + 150·C
Voltage on Any pin to Vss .. -0.5\.1 to (Vee + 0.5V)
Voltage on Vee to VSS ........... -0.5V to + 6.5V
Power Dissipation ....................... 1.0W(9)

~@W~OO©[§ OOO!P@!ru!Ml~iiO@OO

*Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
.other conditions above those indicated in the operational sections of this specification is not implied. Exposure io absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE' Specifications contained within the
following tables are subject to change.

D.C. CHARACTERISTICS
Symbol

(TA

=

Parameter

O·Cto +70·C;Vee

=

5V ±10%;Vss

Typ
(Note 3)

Min

=

OV)

Max

Unit

Vil

Input Low Voltage
(All E~cept EA, EBEN)

-0.5

0.2Vec- 0.1

V

VIl1

Input LowVoltage
(EA, EBEN)

-0.5

0.2Vee- 0.3

V

VII-i

Input High Voltage·
(Except XTAL 1, RST)

0.2Vee+ 0.9

Vee+ 0.5

V

VIH1

Input High Voltage
(XTAL1, RST)

0.7Vee

Vee+ 0.5.

V

Test Conditions

,

VOL

Output Low Voltage
(Ports 1, 2, 3, 4, 5, 6)

0.45

V

IOl = 1.6 mA
(Note 4)

Vou

Output Low Voltage
(Port 0, ALE, PSEN, EPSEN)

0.45

V

IOl = 3.2mA
(Note 4)

VOH

Output High Voltage
(Ports 1, 2, 3, 4, 5, 6 COMM9
ALE, PSEN, EPSEN)

V

IOH = -60p..A
Vee = 5V ±to%

VOH1

Output High Voltage
(Port 0 in External
Bus Mode)

III

Logical 0 Input
Current (Ports 1, 2, 3, 4, 5, 6)

ITl

Logiqal 1 to 0
Transition Current
(Poits 1, 2, 3, 4, 5, 6)

III

Input Leakage
(portO, EA)

RRST

Reset Pullup Resistor

IIH

Logical 1 Input Current (EBEN)

Icc

Power Supply Current:
Active (i 6.5 MHz)
Idle (16.5 MHz)
Power Down Mode

2.4
0.9Vee

V

2.4

V

0.9Vee,

V
·-50

p..A

-650

p..A

= -10'p..A
= -400;UA
= 5V ±10% .
= - 40 p..A (Note 5)
VIN = O.4SV
IOH

IOH
Vee
IOH

VIN

=

2V

..
±10
40

p..A

0.45  100 pF), the noise pulse on the ALE pin may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
5. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vee specification when the address bits are stabilizing.
6. lee is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, V,L = Vss + 0.5V, V,H =
Vee - 0.5V; XTAL2 N.C.; Port 0 pins connected to Vee. "Operating" current is measured with EA connected to Vee and
RST connected to Vss. "Idle" current is measured with EA connected to Vss, RST connected to Vee and GSC inactive.
7. The specifications relating to external data memory characteristics are also applicable to DMA operations.
B. TQVWX should not be confused with TQVWX as specified for BOC51BH. On BOC152, TQVWX is measured from data
valid to rising edge of WR. On BOC51 BH, TQVWX is measured from data valid to falling edge of WR. See timing diagrams.
9. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
10. All specifications relating to external program memory characteristics are applicable to:
EPSEN for PSEN
Port 5 for Port 0
Port 6 for Port 2
when EBEN is at a Logical 1 on the BOC152JB.

MAX Icc (ACTIVE) = (2_24 X FREQ) + 4_16 (Note 6)
MAX Icc (IDLE) = (0_8 X FREQ) + 2.2 (Note 6)
45
MAX Icc (ACTIVE)

40
35

'/

30
~

5u
2

25

.... v

20

/'" V

15
10
5
0

/'"

/"

_/

- :::---

TYPICAL Icc
(ACTIVE) (NOTE 1)

/""

--

/'"

....-

...-:::

4

/'

8

12

MAX Icc (IDLE)
TYPICAL Icc
IDLE (NOTE 1)
16

FREQUENCY (MHz)

270431-7

Figure 5. Icc vs Frequency
I: Instruction (program memory contents).
L: Logic level LOW, or ALE.
P: PSEN.
Q: Output data.
R: READ signal.
T: Time.
V: Valid.
W: WRITE signal.
X: No longer a valid logic level.
Z: Float.

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.

A:
C:
D:
H:

Address.
Clock
Input data.
Logic level HIGH.

For example,
TAVLL
TLLPL

10-125

=
=

Time for Address Valid to ALE Low.
Time for ALE Low to PSEN Low.

SOC152JA/S3C 152JAlSOC152JB

~[Q)W~OO©[§ OOO~@OOIMl~iiO@OO

A.C. CHARACTERISTICS (TA = O·C to + 70·C; Vee = 5V ± 10%; Vss = OV; Lqad Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
ADVANCE INFORMATION: SEE INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
1/TCLCL

TLHLL
TAVLL
TLLAX

Unit

Oscillator Frequency
80C152JA
83C152JA
80C152JB

3.5

12

MHz

80C152JA-1
83C152JA·1
80C152JB-1
ALE Pulse Width

3.5

16.5

MHz

16.5 MHz

Parameter

Min

Address Valid to ALE Low

TLLPL

Address Hold After ALE Low
ALE Low to Valid
Instruction In
ALE Low to PSEN Low

TPLPH

PSEN Pulse Width

TPLIV

PSEN Low to Valid
Instruction In

TPXIX

Input Instruction
Hold After PSEN

TPXIZ

Input Instruction
Float After PSEN

TLLlV

(Note 7,10)

. Variable Oscillator
Min
Max

Max

81

2TCLCL-40

ns

5
25

TCLCL-55

ns
ns

TCLCL-35
142

4TCLCL-100

20'

TCLCL-40

137

3TCLCL-45

77
0

ns
ns
ns

3TCLCL-105

ns
ns

0
35

TCLCL-25

ns

,

TAVIV

Address to Valid
Instruction In

198

5TCLCL-105

ns

TPLAZ

PSEN Low to Address
Float

10

10

ns

TRLRH

RD Pulse Width
WR Pulse Width

TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV

RD Low to Valid
Data In
Data Hold After RD
Data Float After RD

263

6TCLCL-100

263

6TCLCL-100
138

0

ALE Low to Valid
Data In
Address to Valid
Data In

ns
- ns
5TCLCL-165

ns
ns

0
51

2TCLCL-70

ns

335

8TCLCL-150

ns

380

9TCLCL-165

ns

3TCLCL+50

ns

TLLWL

ALE Low to RD or
WRLow

132

TAVWL

Address to RD or
WRLow

112

4TCLCL-130

ns

TQVWX(8)

Data Valid to WR
Transition

196

6TCLCL-167

ns

TWHQX

Data Hold After WR
RD Low to Address
Float

10

RD or WR High to
ALE High

20

TRLAZ
TWHLH

232

3TCLCL-50

TCLCL-50

o '

10-126

100

TCLCL-40

ns
0

ns

TCLCL+40

ns

inter

80C152JAl83C152JAl80C152JB

~[Q)WbW~'J©[g O~IP@rnl[i'li]~iJO@~

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE _ _oJ

PORT O/PORT 5

PORT 2/PORT 6

----'
AB-A15

----'

270431-8

EXTERNAL DATA MEMORY READ CYCLE

ALE

PSEN

I-----TLLDV-----I'I
TRLRH

---I

RD

INSTR. IN

PORTO

PORT2

P2.0-P2.7 OR A8-A 15 FROM DPH

A8-A 15 FROM PCH
270431-9

10-127

infef

80C152JA/83C152JA/80C1 ~2JB

~[Q)\Yl~OO©~. oOO!r@OO[MJ~'U'O@OO

EXTERNAL DATA MEMORY WRITE CYCLE

I

ALE

i=4-

\.
TWHLH

\.

PSEN
-TLLWL
WR

,

TWLWH

J

TQVWX

-.
PORTO

::::r

TAVLL

-.

I-- TLLAX---j

AO-A7 FROM R, OR DPL )

-'

1

r-

TWHQX

X X AO- A7 FROM PCL

DATA OUT

INSTR. IN

TAVWL
PORT2

=>

A8-A15 FROM PCH

P2.0-P2.7 OR A8-A15 FROM DPH

270431-10

'EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TClCL

Oscillator Frequency

3.5

16.5

MHz

TCHCX

High Time

20

ns

TClCX

low Time

20

ns

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

EXTERNAL CLOCK DRIVE WAVEFORM

270431-11

10-128

inter

SOC 152JA/S3C152JA/SOC152JB

~[Q)W~OO©~ OOOIF@OOIMl~'ifO@OO

LOCAL SERIAL CHANNEL TIMING-SHIFT REGISTER MODE
Symbol

Variable OSCillator

16.5 MHz

Parameter

Min

Max

Min

Units

Max

TXLXL

Serial Port Clock Cycle
Time

727

12TCLCL

ns

TOVXH

Output Data Setup to
Clock Rising Edge

473

10TCLCL-133

ns

TXHOX

Output Data Hold After
Clock Rising Edge

4

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

10TCLCL-133

473

ns

SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION

I

7

ALE

CLOCK

r- TQVXH~ r-

TXHQX

'''---'''''---r' '-----rJ "---""'--..JX'-_---JX

OUTPUT OATA

4

X'-_---JX"---_-'x"---""'--..JI

t

t

WRITE TO SSUF

SET TI

INPUT OATA _ _ _ _ _...J'\;;;;;J',_,,'I;.;.;.:;;;"-.....J'=~'--..J'.;;.;:;;,\,_I'I;..=''_.....J'I;...;;J'I_J,;.;.;;;;;;(,,_,'I;...;;;;J''

t

t

CLEAR RI

SET RI

270431-12

A.C. TESTING:
INPUT, OUTPUT WAVEFORMS

vce-O.s===>(
0,45 V

0.2Vcc+0.9

FLOAT WAVEFORM

L

_;..0_.2_V.,;;CC;,.-_0_.1_ _ __
270431-13

270431-14
For Timing Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs, and Begins to Float
when a 100 mV change from the Loaded VOHIVOL Level occurs
IOLIiOH ;, ± 20 rnA.

AC Inputs During Testing are Driven at Vcc-O,5 for a Logic "1"
and 0.45V for a Logic "0", Timing Measurements are made at VIH
Min for a LogiC "1" and VIL Max for a Logic "0",

10-129

intJ

80C152JA/83C152JA/80C152JB

~[Q)W~OO©~ OOOIF@OOIMl~ii"O@OO

GLOBAL SERIAL PORT TIMINGS-Internal Baud Rate ,Generator
Symbol

16.5 MHz (BAUD

Parameter

Min

=

0)

Variable Oscillator
IIIlIn

Max

Unit

Max

HBTJR

Allowable jitter on
the Receiver for %
bit time (Manchester
encoding only)

0.0375

,(0.125 x
(BAUD+1)X
8TCLCL)
--:25,ns

,.,.s

FBTJR

Allowable jitter on
the Receiver for one
full bit time (NRZI
and Manchester)

0.10

(0.25 x
(BAUD+1)X
8TCLCL)
-25 ns

,.,.s

HBTJT

Jitter of data from
Transmitter for %
bit time (Manchester
encoding only)

±35

±35

ns

FBTJT

Jitter of data from
Transmitter for one
full bit time (NRZI
and Manchester)

±70

±.70

ns

DRTR

Data rise time for
Receiver(11 )

20

20

ns

DFTR

Data fall time for
Receiver!1'2)

20

20

ns

~OTES:

'11. Same as TCLCH, use External Clock Drive Waveform.
12. Same as TCHCL, use External Clock Drive Waveform.

GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR)
II

BT

'I

1

MANCHESTER

=::J(
1
1

NRzr=:::X

1

~I~;'-------'I
X.' ~

~X~
~I
HBTJR'

I......

~
I

~

FBTJR

1

)K
'I'

I

~

c::::

GRxD

1

'I

:

GRxD

FBTJR
270431-15

10-130

intJ

~[Q)\\7~OO©~ OOOI?@OOIMl~ii'O@OO

SOC152JAlS3C152JAlSOC152JB

GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR)

I

~I'--------BT--------~'I

=::x
I

MANCHESTER

I

? X, ?

I

?

X,..-~?r--x:::: GTxD
'----"""Tl~..,,_"':'+~"'------''--''''~~,'---'I :~~
I

I_----H-B-TJ-T-~-~I~-~--F-BT-JT---~I
NRZ1=::X

~.

~

.~

~ GTxD

ai'

FBTJT
270431-16

GLOBAL SERIAL PORT TIMINGS-External Clock
Symbol

Parameter

16.5 MHz

. Variable Oscillator

Min

Max

Min

0.009

2.4

0.009

Unit

Max

x

1/ECBT

GSC Frequency with an
External Clock

ECH

External Clock High

15.5

2TClCl
+ 30ns

ns

ECl

External Clock low

155

2TClCl
+ 30 ns

ns

ECRT

External Clock Rise
Time(11)

20

20

ns

ECFT

External Clock Fall
Time(12)

20

20

ns

ECDVT

External Clock to Data
Valid Out - Transmit
(to External Clock
Negative Edge)

150

150

ECDHT

External Clock Data
Hold - Transmit
(to External Clock
Negative Edge)

Fosc

0.145

MHz

ns

ns
0

0

ECDSR

External Clock Data
Set-up - Receiver
(to External Clock
Positive Edge)

45

45

ns

ECDHR

External Clock to Data
Hold - Receiver
(to External Clock
Positive Edge)

50

50

ns

10-131

intJ

80C152JA/83C152JA/80C152JB

~IQ)\YI~OO©[§ OOOIr@OO[M)~'iiO@OO

GSC TIMINGS (EXTERNAL CLOCK)
f4"I'----ECBT ------+1'1

----x

1

EXTERNAL CLOCK

1

1.
~ECL----:

:

/

: - - - ECH - . : "'I_ _ _--J
-+j
:-- ECDVT

_ _....;...1

TRANSMIT DATA

'X

:X,.-.;;...;.------...;....--

X

ECDHT -+t

;....~--------....- -

f4"I'----ECBT------+t·1
1
1

EXTERNAL CLOCK

----x'--___J/:,-----..,.
1

1

RECEIVE DATA

I~______

- : ECDSR '--ECDHR-:

-~'''':--X

,

1

J

/,-----.. .X

~

1

Xr -;---......------..:.:.-,~~--------~~--

270431-17

10-132 .

inter

27C64/S7C64

64K (SK

x S) CHMOS PRODUCTION AND
UV ERASABLE PROMS

•

•
•

CHMOS Microcontroller and
Microprocessor Compatible
- 87C64-lntegrated Address Latch
- Universal 28 Pin Memory Site, 2-line
Control
Low Power Consumption
-100}J-A Maximum Standby Current

•

High Performance Speeds
- 150 ns Maximum Access Time

•

New Quick-Pulse Programming™
Algorithm (1 second programming)

•

Available in 28-Pin Cerdip and Plastic
DIP Package and 32-Lead PLCC
Package.

Noise Immunity Features
± 10% Vee Tolerance
- Maximum Latch-up Immunity
Through EPI Processing

(See Packaging Spec, Order #231369)

-

Intel's 27C64 and 87C64 CHMOS EPROMs are 64K bit 5V only memories organized as 8192 words of 8 bits.
They employ advanced CHMOS*II-E circuitry for systems requiring low power, high performance speeds, and
immunity to noise. The 87C64 has been optimized for multiplexed bus microcontroller and microprocessor
compatibility while the 27C64 has a non-multiplexed addressing interface and is plug compatible with the
standard Intel 2764A (HMOS II-E).
The 27C64 and 87C64 are offered in both a ceramic DIP, Plastic DIP, and Plastic Leaded Chip Carrier (PLCC)
Packages. Cerdip packages provide flexibility in prototyping and R&D environments; whereas Plastic DIP and
PLCC EPROMs provide optimum cost effectiveness in production environments. A new Quick-Pulse ProgrammingTM Algorithm is employed which can speed up programming by as much as one hundred times.
The 87C64 incorporates an address latch on the address pins to minimize chip count in multiplexed bus
systems. Designers can eliminate an external address latch by tieing address and data pins of the 87C64
directy to the processor's multiplexed address/data pins. On the falling edge of the ALE input (ALE/CE),
address information at the address inputs (Ao-A12) of the 87C64 is latched internally. The address inputs are
then ignored as data information is passed on th~ same bus.
The highest degree of protection against latch·up is achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mAon address and data pins from -1V to Vcc + 1V.
'liMOS and CHMOS are patented processes of Intel Corporation.

DATA OUTPUTS
0 0-07

OUTPUT ENABLE
PROG LOGIC

OUTPUT BUffERS.

Y-GATING

65,536 BIT
CELL MATRIX

Shaded 'Areas' i> .:::';,:;:::represent the 87C64 version

290000-1

Figure 1. Block Diagram

10-133

October 1987
Order Number: 290000-007

27C64/87C64

27256

27128

Vpp

Vpp

2732A

2716

A'2
A7
A6
As
A4
AS
A2
A,

A'2
A7
A6
As

A7
A6
As

A4

A4

As
A2
A,

An

An

00
0,
02

00
0,
02

AS
A2
A,
AD
00
0,
02

A7
A6
As
A4
Aa
A2
A,
AD
00
0,
~

Gnd

Gnd

Gnd

Gnd

27C64/87C64
P27C64/P87C64

2716

2732A

Vee
PCM
N.C.

27128

27256

Vee

Vee

J5GlVl
A,s
As
As
All

..'.

Vee

As
As

A"

Vpp

at'

DE

As
As
All
DENpp

DE

A,o

A,o

A,o

A,o

06
Os
04
Os

07
Os
Os
04
Os

07
Os
Os
04
. Os

~
06
Os
04
Oa

c.._
A,.

~

~
~

~

290000-2

NOTE:
Intel "Universal Site" Compatible EPROM Pin Confi~urations are shown in the adjacent blocks to 27C64 Pins,
Shaded Areas 1u!!L~represenllhe 87C64 version

Figure 2. Pin Configuration

A6

0

All

U

A2
A,

AS

AI

A'

A~

32 PIN PLCC

Ne

0.450" X 0.550"
(11.430 X 13.970)
(MILLIMETERS)
TOP VIEW

AD

Ne
00

290000-11

Figure 3. PLCC(N) Lead Configuration
10-134

A'4
A,s

Vee

As
As
All

DE
~,

27C64/87C64

EXPRESS EPROM Product Family

Extended Temperature (Express)
EPROMs
The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications.
EXPRESS EPROM products are available with 168
± 8 hour, 125°C dynamic burn-in using Intel's standard bias configuration. This process exceeds or
meets most industry specifications of burn-in. The
standard EXPRESS EPROM operating temperature
range is O°C to 70°C. Extended operating temperature range (- 40°C to + 85°C) EXPRESS products
are available along with automotive temperature
range (- 40°C to + 125°C) products. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AaL. This may allow the user to
reduce or eliminate incoming inspection testing.

PRODUCT DEFINITIONS
Operating
Type
Temperature eC)
Oto +70
a
-40 to +85
T
L
-40 to +85
A
-40 to + 125
B
-40 to + 125

Burn-in 125°C (hr)
168 ±8
NONE
168 ±8
NONE
168 ±8

EXPRESS Options

READ OPERATION

27C64/87C64 Versions
Packaging Options
Speed
Versions
-1
-15
-2
-20
-STD
-25
-3
-30

Cerdip

PLCC

T,L,a
T, L,a
T,L,a,A,B
T,L,a,A·
T, L,a,A, B
T,L,a,A
T,L,a,A,B
T,L,a,A

T
T
T,A
T
T,A
T
T,A
T

Plastic
DIP
T
T
T,A
T
T,A
T
T,A
T

D.C. CHARACTERISTICS
Electrical Parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for:
27C64
87C64
Symbol
Parameter
Test Conditions
Min
Max
Vee Standby Current (mA)
CMOS
0.1
CE = Vee,OE = VIL
ISB
TTL
1.0
CE = VIH, OE = VIL
lee1(1)
Vee Active Current (mA)
TIL
20,30
OE = CE = VIL
Vee Active Current at
TIL
20,30
OE = CE = VIL
High Temperature
Vpp = Vee, Tambient = 85°C
NOTE:

1. See notes 4 and 6 of Read Operation D.C. Characteristics.

30~s

H

AOruLJ
:'rLS
Vee

A'2

°00,
°2
290000-13

= +sv
vpp = +sv
DE

290000-14

Binary Sequence from Ao to A12

= 1 Kfl
vee = +sv
GND = OV
CE = 33.3 KHz
PGM = +sv
R

Burn·ln Bias and Timing Diagrams
10-135

intJ

27C64/87C64

ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
_
During Read ............. ~ .... O°C to + 70°C(2)
Temperature Under Bias ......... -lO°C to + 80·C
Storage Temperature .......... - 65°C to + 150·C
Voltage on Any Pin with
Respect to Ground .............. - 2~OV to 7V(1)

• Notice: Stresses above those listed under ':Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Voltage on Pin Ag with
Respect to Ground ......... -2.0V to + 13.5V(1)
Vpp Supply Voltage with Respect to Ground
During Programming ......... - 2.0V to + 14V(1)
Vcc Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.OV(1)

READ OPERATION D.C. CHARACTERISTICS O°C s TA S + 70°C
Symbol

Typ(3)

Max

Unit

Test Condition

0.01

1.0

,."A VIN

=

±10

,."A VOUT

6

100

,."A

ICMOS

5

100

ITTL

4

1.0

,."A
mA

4,6

20,30

mA

Parameter

III

Input Leakage Current

ILO

Output Leakage Current

IpP1

Vpp Current Read

ISB

Vcc Current Standby
with Inputs-

Notes

Min

ICC1

Vcc Current Active

VIL

Input Low Voltage (± 10% Supply)
(TTL)

-0.5

0.8

Input Low Voltage
(CMOS)

-0.2

0.2

2.0

Vcc+ 0.5

Vcc- 0.2

Vcc+ 0.2

VIH

f = 5 MHz, lOUT = 0 mA

Input High Voltage(± 10% Supply)
(TTL)
Input High Voltage
(CMOS)

VOL

Output LOw Voltage

VOH

Output High Voltage

los
Vpp

Output Short Circuit Current

7

Vpp Read Voltage

8

,

OV to 5.5V

= OV to 5.5V
Vpp = Vcc
CE = Vcc
CE = VIH
CE = VIL

0.45
3.5
Vcc- 0.7 _

V Vpp = Vcc

V Vpp = Vcc
V 10L =2.1 mA
V

100

mA

Vce

V

10H= -2.5mA

NOTES:
1. Minimum D.C. input voltage is -0.5V. During transitions.
the inputs may undershoot to - 2.0V for periods less than
20 ns. Maximum D.C. Voltage on output pins is
Vce + 0.5V which may overshoot to Vee + 2V for periods
less than 20 ns.
2. Operating temperature is for commercial product definedby this specification. Extended temperature options are
available in EXPRESS and Military version.
S. Typical limits are at Vee = 5V; TA = + 25°C.
4. 20 mA forSTD and -3 versions; 30 mA for -2 and
150 ns version-!!.
VIL. VIH levels at TTL inputs.

5. ALE ICE or CE is Vee ± 0.2V. All other inputs can have
any value within spec.
6. Maximum Active power usage is the sum Ipp + Icc. The
maximum current value is with Outputs 00 to 07 unloaded.
7. Output shorted _for no more than one second. No- more
than one output shorted at a time. los is sampled but not
100% tested.
8. Vpp may be one diode voltage drop below Vee. It may
be connected directly to Vee.

10-136

intJ

27C64/87C64

READ OPERATION

+ 70·G

A.C. CHARACTERISTICS 27C64(1) O·G ~ TA ~
Vee ±5%

27C64-1
N27C64-1
P27C64-1

27C64-2
N27C64-2
P27C64-2

27C64
N27C64

27C64-3
N27C64-3

27C64-15
N27C64-15
P27C64-15

27C64-20
N27C64-20
P27C64-20

27C64-25
N27C64-25

27C64-30
N27C64·30

Versions (3)
Vee ±10%

Symbol

Characteristic

Min

Max

Min

Max

Min

Max

Min

Unit

Max

tACC

Address to Output Delay

150

200

250

300

ns

tCE

CE to Output Delay

150

200

250

300

ns

tOE

OE to Output Delay

75

75

100

120

ns

tDF(2)

OE High to Output High Z

35

55

60

105

ns

tOH(2)

Output Hold from Addresses, CE
or OE Change·Whichever is First

0

0

0

0

ns

NOTES:
1. A.C. characteristics tested at VIH = 2.4V and VIL = 0.45V.
Timing measurements made at VOL = O.SV and VOH = 2.0V.
2. Guaranteed and sampled.
3. Model Number Prefixes: No prefix = Cerdip; P = Plastic DIP; N = PLCC.

A.C. WAVEFORMS 27C64
V,H-----"\
ADDRess
VALID.

ADDRESSES
VIL _ _ _ _ _J

V,H

-------+-,.

V,H

-------+----""

_--ICEI31~

~-----t.cc-------<·I

+H++<

OUTPUT _ _ _ _ _~H;,;;IG;,;;H;,;;Z_ _ _ _ _

HIGHZ

290000-5
NOTES:
1. Typical values are for T A = 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-toE after the falling edge of CE without impact on tCE.

10-137

27C64/87C64

A.C. CHARACTERISTICS

1II«llo·c:5: T A :5: + 70·C

Vee ±5%

87C64-1
N87C64-1
P87C64-1

87C64-2
N87C64-2
P87C64-2

87C64
N87C64

87C64-3
N87C64-3

Vee ±10%

87C64-15
N87C64-15
P87C64-15

87C64-20
N87C64-20
P87C64-20

87C64-25
N87C64-25

87C64-30
N87C64-30

Versions (3)

Symbol

Parameter

Max

Min

Min

. Min

Max

Max

Min

Unit

Max

tLL

Chip Deselect Width

50

50

60

75

ns

tAL

Address.to CE-Latch Set-up

7

20

25

30

ns

tLA

Address Hold from CE-LATCH

.45

50

60

ns

tACL

CE-Latch Access Time

tOE

Output Enable to Output Valid

tCOE

ALE ICE to Output Enable

tCHZ(2)

Chip Deselect to Output in High Z

45

50

tOHZ(2)

Output Disable to Output
in HighZ

35

50

30
150

200

75

75
45

30.

250

300

ns

100

120

ns

60

75

ns

60

75

ns

60

50

ns

NOTES:
1. A.C. characteristics tested at VIH = 2.4V and VIL = 0.45V.
Timing measurements made at VOL = O.BV and VOH = 2.0V.
2. Guaranteed and sampled.
3. Model Number Prefixes: No prefix = Cerdip; P = Plastic DIP; N = PLCC.

A.C. WAVEFORMS .....•!

ALE/CE

tACL
OUTPUTS

-tCOE--t+----IOE

......_ _ _

OE----~

__J

290000-6

CAPACITANCE(1)
Symbol

f = 1.0 MHz

TA = 25·C.

Parameter

Max Unit Conditions

=

CIN

Address/Control Capacitance

6

pF

VIN

COUT

Output Capacitance

12

pF

VOUT

OV

=

OV

NOTE:
1. Sampled. Not 100% tested.
A_C_ TESTING INPUT/OUTPUT WAVEFORM

2.4
0.45

2.0>
0.8

____

TEST POINTS _ _

2.0

A.C. TESTING LOAD CIRCUIT

f

il-'N9"

OUTPUT

~0.8;....

__

3.3Kn

DEVICE
UNDER
TEST

290000-10

~DUT

.l

A.C. Testing: Inputs are driven at 2.4V for a Logic "1 "and 0.45V
'for a Logic "a". Timing measurements are made at 2.0V for a
logic "I" and O.BV for a Logic "0".

CL= 100 pF

290000-3
CL ;= 100 pF
CL Includes Jig Capacitance

10-138

27C64/87C64

DEVICE OPERATION
The modes of operation of the 27C64/87C64 are
listed in Table 1. A single SV power supply is required in the read mode. All inputs are TIL levels
except for VPP and 12V on A9 for inteligent Identifier
mode.
Table 1. Mode Selection for 27C64 and 87C64
Pins

. Vpp

A,LE/CE
CE

OE

PGM
(7)

Ag

Ao

Mode
Read

VIL

VIL

VIH

X(l)

X

Vee

S.OV

DOUT

Output Disable

VIL

VIH

VIH

X

X

Vee

S.OV

HighZ

Standby

VIH

X

X

X

X

Vee

S.OV

HighZ

Programming

VIL

VIH

VIL

X

X

(4)

(4)

DIN

(7)

Vee

Outputs

Program Verify

VIL

VIL

VIH

X

X

(4)

(4)

DOUT

Program Inhibit

VIH

X

X

X

X

(4)

(4)

HIGHZ

inteligent Identifier(3)
-Manufacturer

VIL

VIL

VIH

VH(2)

VIL

Vee

Vee

89 H (6)
88 H (6)

inteligent Identifier(3)
-27C64

VIL

VIL

VIH

VH(2)

VIH

Vee

Vee

07 H

inteligent Identifier(3, 5)
-87C64

VIL

VIL

VIH

VH(2)

VIH

Vee

Vee

37 H

NOTES:

1.
2.
3.
4.
5.
6.
7.

X can be VIL or VIH.
VH = 12.0V ± O.5V.
A1-Aa, A10-12 = VIL.
See Table 2 for Vcc and Vpp voltages.
ALE ICE has to be toggled in order to latch in the addresses and read the signature codes.
The Manufacturer's identifier reads 89H for Cerdip devices; 88H for Plastic DIP and PLCC devices. _
In Read Mode tie PGM and Vpp to Vee.

Read Mode: 27C64

Read Mode: 87C64

The 27C64 has two control functions, both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output enable
(OE) is the output control and should be used to
gate data from the output pins. Assuming that addresses are stable, the address access time (tAee)
is equal to the delay from CE to output (teE). Data is
available at the outputs after a del~f tOE from the
falling edge of OE, assuming that CE has been low
and addresses have been stable for at least
tAee-tOE·

The 87C64 was designed to reduce the hardware
interface requirements when incorporated in processor systems with multiplexed address-data busses.
Chip count (and therefore power and board space)
can be minimized when the 87C64 is designed as
shown in Figure 4. The processor's multiplexed bus
(ADo-7) is tied to both address and data pins of the
87C64. All address inputs of the 87C64 are latched
when ALE/CE is brought low, thus eliminating the
need for a separate address latch.

10-139

inter

27C64/87C6:4

The 87C64 internal address latch is directly enabled
through the use of the ALE/CE line. As the transition
occurs on the ALE/CE from the TTL high to the low
state, the last address presented at the address pins
is retained. Data is then enabled onto the bus from
the EPROM by the OE pin.

Vss Vee RST

Vee Vss

290000-4

Figure 4. 80C31 with 87C64
System Configuration

Standby !\/lode
The 27C64 and 87C64 have Standby modes which
reduce the maximum Vee current to 100 p..A. Both
are placed in the Standby m'ode when CE or
ALE/CE are in the CMOS-high state. When in the
Standby mode, the outputs are in a high impedance
state, independent of the OE input.

Two Line Output Control
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 control lines which
accommodate this multiple memory connection. The
two control lines allow for:
a) the lowest possible memory power dissipation,
and
b) complete assurance that output. bus .contention
will not occur.
To use these two control lines most efficiently, CE
(or 'ALE/CE) should be decoded and used' as the
primary device selecting function, while OE should
be made a common connection to all devices in the
array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low power standby
mode and that the output pins are active only when
data is desired from a particular memory device.

SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
. edges of Chip Enable. The magnitude of these transient and inductive current peaks is dependent on
the output capacitive and inductive loading of the
device. The associated transient voltage peaks can
be. suppressed by complying with Intel's Two-Line
Control; and by properly selected decoupling capacitors. It is recommended that a 0.1 p..F ceramic capacitor be used on every device between Vee and
GND. This should be a high frequency capaCitor for
low inherent inductance and should be placed as
clo.se to the device as possible. In addition, a 4.7 p..F
bulk electrolytic capacitor should be used between
Vee and GND for every eight devices. The bulk capacitor should be located near where tlie power supply is connected to the array. The purpose of the
,bulk capacitor is to overcome the voltage droop
caused by the inductive effect of PC board-traces.

PROGRAMMING MODES
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations. Although. only "Os" will be programmed;
both "1 s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.
The device is in the programming mode when Vpp is
raised to its programming voltage (See Table 2) and
CE (or ALE/CE) and PGM are both at TTL low and
OE = VIH. The data to be programmed is applied 8
, bits in parallel' to the data output pins. The levels
required for the address and data inputs are TTL:

Program Inhibit
Programming of multiple EPROMSin parallel with
different data is easily accomplished by using ·the
Program Inhibit mode. A high-level CE (or ALE/CE)
or PGM input inhibits the other devices from being
programmed.

10-140

inter

27C64/87C64

Except for CE (or ALE/CE), all like inputs (including
OE) of the parallel EPROMs may be common. A TTL
low-level pulse applied to the £9lM input with Vpp at
its programming voltage and CE (or ALE/CE) = VIL
will program the selected device.

Program Verify
A verify (read) should be performed on the programmed bits to determine that they have been correctly programme!LThe verify is performed with OE
and CE (or ALE/CE) at VIL, PGM at VIH, and Vee
and Vpp at their programming voltages. Data should
be verified a minimum of tOE after the falling edge of
OE.

inteligent Identifier™ Mode
The inteligent Identifier Mode allows the. r~adin~ ~ut
of a binary code from an EPROM that will Identify Its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
Mode.
Byte 0 (AO = VIL) represents the manufacturer code
and byte 1 (AO = VIH) the device identifier code.
These two identifier bytes are given in Table 1.
ALE/CE of the 87C64 has to be toggled in order to
latch in the addresses and read the Signature
Codes.

ERASURE CHARACTERISTICS (FOR
CERDIP EPROMS)
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluprescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
.this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 )J-W/cm2 power rating. The EPROM should be placed withi~ 1 in~h of
the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000 )J-W/
cm 2). Exposure of the device to high intensity UV
light for longer periods may cause permanent damage.

CHMOS NOISE CHARACTERISTICS
Special EPI processing techniques have enabled Intel to build CHMOS with features adding to system
reliability. These include input/output protection to
latch-up. Each of the data and address pins will not
latch-up with currents up to 100 mA and voltages
from -1V to Vee + 1V.
Additionally, the Vpp (programming) pin is designed
to resist latch-up to the 14V maximum device limit.

10-141

27C64/87C64

290000-12

Figure 5. Quick-Pulse Programming™ Algorithm

Quick-Pulse Programming™ Algorithm
Intel's 27C64 and 87C64 EPROMs can now be programmed using the Quick-Pulse Programming Algorithm, developed by Intel to substantially reduce the
throughput time in the production environment. This
algorithm allows these devices to be programmed in
under one second, almost a hundred fold improvement over previous algorithms. Actual programming
time is a function of the PROM programmer being
used.

fication to determine when the address byte has
been successfully programmed. Up to 25 100 /Jos
pulses per byte are provided before a failure is recognized. A flowchart of the Quick-Pulse Programming Algorithm is shown in Figure 5.
For the Quick Pulse Programming Algorithm, the entire sequence of programming pulses and byte verifications is performed at Vee = 6.25V and Vpp at
12.75V. When programming of the EPROM has
been completed, all bytes should be compared to
the original data with Vee = Vpp = 5.0V.

The Quick-Pulse Programming Algorithm uses initial
pulses of 100 microseconds followed by a byte veri-

10-142

inter

27C64/87C64

D.C. PROGRAMMING CHARACTERISTICS

(27C64/87C64) T A = 25°C ± 5°C

Table 2
Symbol

Limits

Parameter

III

Input Current (All Inputs)

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

Min

Max

Unit

1.0

p.A

-0.1

0.8

V

2.0

Vee

+ 0.5

0.45
3.5

Test Conditions
(Note 1)
VIN

= VIL or VIH

V

IOL

V

IOH

= 2.1 mA
= -2.5 mA

CE

= VIL

V

lee2(3)

Vee Supply Current

IpP2(3)

VPP Supply Current (Program)

VIO

Ag inteligent Identifier Voltage

11.5

Vpp

Programming Voltage

12.5

13.0

V

Vee

Supply Voltage During Programming

6.0

6.5

V

30

mA

30

mA

12.5

V

A.C. PROGRAMMING CHARACTERISTICS 27C64
T A = 25°C
Symbol

± 5°C,

See Table 2 for Vee and Vpp Voltages
Limits

Parameter
Min

Typ

Max

Unit

tAS

Address Setup Time

2

p.s

toES

OE Setup Time

2

p.s

tos

Data Setup Time

2

p.s

tAH

Address Hold Time

0

p.s

tOH

Data Hold Time

2

tOFP

OE High to Output Float Delay

0

tvps

Vpp Setup Time

2

p.s

tves

Vee Setup Time

2

p.s

teEs

CE Setup Time

2

p.s

tpw

PGM Program Pulse Width

95

toE

Data Valid from OE

A_C_ CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) ...... 20 ns
Input Pulse Levels ...•.............. 0.45V to 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 3.5V '

Conditions
(Note 1)

p.s
130

100

ris

105

p.s

150

ns

(Note'2)

Quick-Pulse

N'OTES: .
1. Vee must be applied simultaneously or before Vpp and
removed Simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longer driven-see timing diagram.
3. The maximum current value is with outputs 00 to 07 Unloaded.

10-143

intJ

27C64/87C64

PROGRAMMING WAVEFORMS 27C64
.PRDGRAM

'~

ADDRESSES

VERIFY

-

ADDRESS STABLE

_IA' __
~

DATA IN STABLE

DATA
~ID'

__

~

HIGHZ

DATA OUT

f+'DH.,

_'AH

vlLlD

-

It'

L
~

'OF,!»

12.75V

.-.-/ _'VP'__

Vpp

5.0V

,

8.25V

Vee
5.0V

V,H

CE

,

-.-/ _'ve,_

-

\

V"

_'e,,_
V'H
PGM
V"

V'H

DE
V"

-

~
I,.

topw

,

l-

-

i--

'OES1
\

'OE(2)

I--

-

290000-9

NOTES: "
1. The Input Timing Reference Level is 0.8V for VIL and 2V for a VIH.
2. toE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the 27C64, a 0.1 ,.F capacitor is required across Vpp and ground to suppress spurious voltage
transients which can damage the device.

10-144

intJ

27C64/87C64

A.C. PROGRAMMING CHARACTERISTICS 87C64:
= 25°C ±5°C, See Table 2 for Vee and Vpp Voltages: .
. ..

TA

Lilnits

..Parameter

Symbol

Min
tvps

Vpp Setup Time

Typ

Unit

2

p.s

tves

Vee Setup Time

2

p's

tLL

Chip Deselect Width

2

p.s

tAL

Address to Chip Select Setup

1

p.s

tLA

Address Hold from Chip Select

1

p.s

tpw

PGM Pulse Width

95

tos

Data Setup Time

2

tOFP

OE High to Data Float

0

tOES

Output Enable Setup Time

2

tOE

Data Valid from Output Enable

tOH

Data Hold Time

2

tJ. s

teEs

CE Setup Time

2

p.s

100

Conditions

Max

105

p.s

Quick-Pulse

p.s
130

ns
p.s

150

ns

NOTE:
1. Programming tolerances and test conditions are the same as 27C64.

PROGRAMMING WAVEFORMS :etc6~1
)I( ADDRESSES (

ADDRESS

, !-=tAL+ -tLA-

-

DATA

I-

ALE/CE

HD~~tOES-r--J:OE

I-tDS "

XI-tDf:J-

tLL(1)

Vpp

~
(1)

Vee

t vps
- - tves

tCES-

~
~

tpw"

-;~;w
\-..J

290000-8

NOTE:
1. 12.75V Vpp & 6.25V Vee for Quick-Pulse Programming Algorithm.

10-145

inter

·87C257
256K (32Kx 8) CHMOS UV ERASABLE PROM

•

CHMOS/NMOS Microcontroiler and
Mlcroproce$sor Compatible
- 87C257-1ntegrated Address Latch
- Universal 28 Pin Memory Site, 2·line
Control
.

•

Noise Immunity Features

- ± 10% Vee Tolerance
- Maximum Latch·up Immunity
Through EPI Processing

'., Low Power Consumption
• High Performance Speeds
- 170 ns Maximum Access Time

•

New Quick·Pulse Programming™
Algorithm
- 4 Second Programming

•

Available in 28·Pln Cerdip Package
(See Packaging Spec .• Order '" 231369)

Intel's 87C257 CHMOS EPROM is a 256K-bit 5V only memory organized as 32,768 8-bit words. It employs
advanced CHMOS*II-E circuitry for systems requiring low power, high speed performance, and noise immunity. The 87C257 is optimized for compatibility with multiplexed address/data bus microcontrollers such as
Intel's 16 MHz 80.51- and 80.96- families.
The 87C257 incorporates latches on all address inputs to minimize chip count, reduce cost, and simplify
design of multiplexed bus systems. The 87C257's internal address latch allows address and data pins to be
tied directly to the processor's multiplexed address/data pins. Address information (inputs Ao-A14) is latched
early in the memory-fetch cycle by the falling edge of the ALE input. Subsequent address information is
ignored while ALE remains low. The EPROM can then pass data (from pins 00-07) on the same bus during
the last part of the memory-fetch cycle.
The 87C257 is offered in a ceramic DIP package, providing flexibility in prototyping and R&D environments.
The 87C257 employs the Quick-Pulse Programming™ Algorithm for fast and reliable programming.
Intel's EPI processing achieves the highest degree of latch-up protection. Address and data pin latch-up
prevention is provided for stressesup to 10.0. mA from -1V to Vcc + 1V.
'HMOS and, CHMOS are patented processes of Intel Corporation.

DATA OUTPUTS

0 0-07

5E

CE
ALE

OUTPUT ENABLE
PROG LOGIC

OUTPUT BUffERS

CHIP ENABLE
ADDRESS LATCH ENABLE
Y DECODE

Y-GATING

X DECODE

262,144 BIT
CELL MATRIX

:>:

~

Ao-A I4
ADDRESS
INPUTS

In
In

'"'"
Q
Q

..:
290135-1

Figure 1. Block Diagram

10.-146

October 1987
Order Number: 290135-002

87C257

Pin Names
Ao-A14
00-0 7

OUTPUTS

OE

OUTPUT ENABLE

CE

CHIP ENABLE

ALE/vpp

Address Latch
Enable/Vpp

N.C.

NO CONNECT
87C257

87C64
Vpp
A12
A7
As
As
A4
As
A2
A1
Ao
00
01
02
Gnd

ADDRESSES

ALE/Vpp
A12
A7
As
As
A4

87C64

vee
A14
A13

As
A9
All
OE
AID
CE

A,

A2
AI
AD
00
01
02

~

06
Os
04
03

GND

Vee
PGM
N.C
As
Ag
An
OE
A10
ALE/CE
07
Os
Os
04
Os

290135-2

Figure 2. DIP Pin Configuration

NOTE:
Intel "Universal Site"-Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent.

10~147

inter

87C257

. EXTENDED TEMPERATURE
(EXPRESS) EPROMs The Intel EXPRESS EPROM family receives additional processing to enhance product characteristics. EXPRESS processing is available for several
EPROM densities allowing the appr-opriate memory
size to match system applications. EXPRESS
EPROMs are available with 168 ±8 hour, 125·C dynamic burn-in using Intel's standard bias configuration. This process meets or exceeds most industry
burn-in specifications. The standard EXPRESS
EPROM operating temperature range is O·C to
+ 70·C. Extended operating temperature range
(-40·C to +85·C) EXPRESS and automotive temperature range (- 40·C to + 125·C) products are
also available. Like all Intel EPROMs, the EXPRESS
EPROM family is inspected to 0.1 % electrical AQL.
This allows reduction or elimination of incoming testing.

Vee

07
06
05

°4
°3
29013S-4
OE = SVR = 1 KflVcc= +SV
ALElVpp = + SV Vss = GND CE = GND

AUTOMOTIVE AND EXPRESS
OPTIONS
Versions
Speed
Versions

Packaging Options

-200V05

A

-250V10

A

-250V05

A

Cerdlp

•
29013S-S
Binary Sequence from AD 10 A14

AUTOMOTIVE AND EXPRESS EPROM
PRODUCT FAMILY

Burn-In Bias and Timing Diagrams

PRODUCT DEFINITIONS
Type

Operating
Temperature ("C)

Burn-in 125·C
(hr)

Q

O·Cto +70·C

168 ±8

T

- 40·C to + 85·C

NONE

L

- 40·C to + 85·C

168 ±8

A

- 40·C to + 125·C

NONE

B

- 40·C to + 125·C

168 ±8

10-148

infef

87C257

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
ex/ended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Operating Temperature, During
Read .....••••••.••.•••....•. O'C to + 70'C(2)
Temperature Under Bias ..••... -1 O'C to + 80'C(2)
Storage Temperature .......... - 65'C to + 150'C
Voltage on any Pin with
Respectto Ground ........••••• - 2V to + 7V(1)
Voltage on Ag with
Respect to Ground ....•..••. - 2V to + 13.5V(1)
Vpp Supply Voltage with Respect to Ground
During Programming •.•.•.•.. - 2V to + 14.0V(1)
Vcc Supply Voltage with
.
Respectto Ground ....•......• -2V to +7.0V(1)

NOTICE Specifications contained within the
following tables are subject to change.

READ OPERATION
D.C. CHARACTERISTICS TTL and NMOS Inputs
Symbol

Parameter

III

Input Load Current

ILO

Output Leakage Current

158

Vee Current Standby
with Inputs-

Notes

Max

Units

0.Q1

1.0

".A

I Stable

Vee Current Active

5

VIL

Input Low Voltage ( ± 10% Supply)

1

VIH

Input High Voltage (± 10% Supply)

VOL

Output Low Voltage

VOH

Output High Voltage

los

Output Short Circuit Current

-0.5
2.0

".A

VOUT = OV to 5.5V

10

mA

CE

1.0

mA

CE = VIH. ALE = VIL

30

mA

CE = VIL. ALE = VIH
f = 5 MHz. lOUT = 0 mA

O.B

V

Vee

+ 0.5

2.4

6

Test Condition
VIN = OV to 5.5V

±10

0.45

D.C. CHARACTERISTICS
III

Typ(3)

I' Switching

leel

Symbol

Min

100

= ALE = VIH

V
V

10L = 2.1 mA

V

10H = -400".A

mA

CMOS Inputs

Parameter

Notes

Min

Input Load Current

ILO

Output Leakage Current

158

Vee Current Standby
with Inputs-

leel

Vee Current Active

VIL

Input Low Voltage (± 10% Supply)

-0.2

VIH

Input High Voltage (± 10% Supply)

0.7 Vee

VOL

Output Low Voltage

VOH

Output High Voltage

los

Output Short Circuit Current

1 Switching

Typ(3)

Max

Units

0.01

1.0

".A

±10

".A

VOUT = OV to 5.5V

6

mA

CE = ALE = Vee

100

".A

CE

15

mA

CE = VIL. ALE = VIH
f = 5 MHz. lOUT = 0 mA

0.8

V

4

1 Stable

5

Vee

+ 0.2

0.4
Vee - O.B

6

Test Condition
VIN = OV to 5.5V

100

= Vec. ALE = GND

V
V

10L = 2.1 mA

'V

10H = -2.5 mA

mA

NOTES:
1. Minimum D.C. input voltage is -0.5V. During transitions. the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum D.C. voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. Typical limits are at Vee = 5V. TA = + 25'C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
10-149

87C257

READ OPERATION

A.C. CHARACTERISTICS(1) O·C s: TA s: + 70·C
Verslons(3)
Symbol

I Vee ±5%
I Vee ±10%

87C257·170V05

Characteristic

Min

Max

87C257-200V05

87C257-250V05

87C257-200V10

87C257-250V10

Min

Max

Min

Units

Max

tACC

Address to Output Delay

170

200

250

ns

tCE

CE to Output Delay

170

200

250

ns

tOE

OE to Output Delay

70

75

100

ns

tOF(2)

OE High to Output High Z

35

40

55

ns

toH(2)

Output Hold from Addresses, CE or
OE Change·Whichever is First

0

0

0

ns

tLL

Latch Deselect Width

35

55

60

ns

tAL(2)

Address to Latch Set·Up

7

15

25

ns

tLA

Address Hold from LATCH

20

30

40

ns

tLOE

ALE to Output Enable

20

30

.40

ns

NOTES:
1. See A.C. Testing Input/Output Waveforms for timing
measurements.
.
,
2. Guaranteed and sampled.
3. Model Number Prefixes: No Prefix = CERDIP.

A.C. CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) ....•. 10 ns
Input Pulse Levels., ................... VOL to VOH
Input Timing Reference Level ..•.........•... 1.5V
Output Timing Reference Level ........ VIL and VIH

A.C. WAVEFORMS

V1H

ALE
V1L
VIH _ _ _ _~~--+_

CE

V1L
V ____
IH

(2)
+ _________
_
t LOE --~-tOE

Of

V1L

~~~---~cc------~

OUTPUT VIH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..!i!:~L._t:§~~~~§:~~
HIGH Z
V1L

290135-6

NOTES:
1. This parameter is only sampled and is not 100% tested.
2. DE may be delayed up to IcE:"tOE after the falling edge of CE without impact on tCE'

10-150

inter

87C257

CAPACITANCE(1}
Symbol

=

TA

25°C. f

=

1.0 MHz

Parameter

Max Units Conditions

=

CIN

Address/Control Capacitance

6

pF

VIN

COUT

Output Capacitance

12

pF

VOUT

OV

=

OV

NOTE:
1. Sampled. Not 100% tested.

A.C. TESTING INPUT/OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

1.:~

~~IN914
1.5 -lEST POINlS ::::::

IH OUTPUT

V1L

-

3.3k.D.

DEVICE
UNDER
TEST

290135-7

A.C. testing inputs are driven at VOH for a Logic "I"
and VOL for a Logic "a". Timing measurements are
made-at VIH for a Logic "1" and VIL for a Logic "a".

:e--

OUT
CL
290135-S

CL = 100 pF
CL Includes Jig Capacitance

DEVICE OPERATION
Table 1 lists 87C257 operating modes. Read mode requires a single 5V power supply. All input. levels are TTL
or CMOS except A9 in inteligent Identifier mode and Vpp.
Table 1. Mode Selection
Pins

ALE/
Vpp

Vee

X

X

5.0V

DOUT

X

X

5.0V

HighZ

X

5.0V

HighZ

(Note 4)

(Note 4)

DIN

CE

OE

As

Ao

Read

VIL

VIL

X(1)

Output Disable -

VIL

VIH

X

Standby

VIH

X

X

X

Programming

VIL

VIH

X

X

Mode

Outputs

Program Verify

VIH

VIL

X

X

(Note 4)

(Note 4)

DOUT

Optional Program
Verify

VIL

VIL

X

X

Vee
(Note 4)

(Note 4)

DCUT

Program Inhibit

VIH

VIH

X

X

(Note 4)

(Note 4)

HighZ

VIL

X

Vec

89H

VIH

X

VCC

24H

inteligent Identifier(3)
-Manufacturer

VIL

VIL

VH(2)

inteligent Identifier(3)
-87C257

VIL

VIL

VH(2)

NOTES:
1. X can be VIL or VIH.
2. VH = 12.0V ±0.5V.
3. AI-As. AlO-12 = VIL. A13-14 = X.
4. See Table 2 for Vee and Vpp programming voltages.

10-151

inter

87C257

Read Mode

Two Line Output Control

The 87C257 has two control functions; both must be
logica"y active to obtain data at the outputs. Chip
Enable (CE) is the power control and the device-select. Output enable (OE) gates data to. the output
pins by controlling the output buffer. When the address is stable (ALE = VIH) or latched (ALE = VII),
the address access time (tACe) equals the delay
from CE to output (teE). Ou~ts display valid data
tOE after the falling edge of OE, assuming tACC and
teE times are met.

EPROMs are often used in larger memory arrays.
Intel provides two contol inputs to acCommodate
multiple memory connections. Two-line control provides for:
a) the lowest possible memory power dissipation,

The 87C257 reduces the hardware interface in multiplexed address-data bus systems. Figure 4 shows a
low power, sma" board space, minimal chip
87C257/microcontro"er design. The processor's
multiplexed bus (ADo.7) is tied to the 87C257's address and data pins. No separate. address latch is
needed because the 87c257 latches a" address inpilts when ALE is low.
The ALE input controls the 87C257's internal address latch. As ALE transitions from VIH to VIL, the
last address present at the address pins is retained.
The OE control can then enable EPROM data onto
the bus.

vss vee RST

290135-9

Md

.

b) complete assurance that output bus contention
will not occur.
To efficiently ·use these two control inputs, an address decoder should enable CE, while OE should
be connected to a" memory-array devices and the
system's READ control line. This assures that only
selected memory devices have active outputs while
deselected memory devices are in low-poWer standby mode.

SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in three supply current (ICC) issue!r-standby current levels, active current levels, and transient
current peaks produced by falling and rising edges
. of Chip Enable. Transient current magnitudes depend on the device outputs' capacitive and inductive
loading. Two-Line Control and proper decoupling ca'
pacitor selection will suppress transient voltage
peaks. Each device should have a 0.1 IlF ceramic
'capacitor connected between its Vcc and GND. This
high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device.
Additiona"y, for every eight devices, a 4.7 IlF electrolytic capacitor should be placed between Vcc.and
GND at the array's power supply connection. The
bulk capacitor will overcome voltage slumps caused
by PC board trace inductances.

PROGRAMMING MODES'

Figure 4. 80C31 with 87C257
System Configuration

Caution: Exceeding 14Von Vpp will permanently
damage the devIce.

Standby Mode
The standbLmode substantially reduces Vcc current. When CE = VIH, the standby mode places the
outputs in a high impedance state, independent of
the OE input.

Initia"y, and after each erasure, a" EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word

10-152

intJ

87C257

can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
The programming mode is entered when Vpp is
raised to its programming voltage (see Table 2).
Data is programmed by applyil]Lan 8-bit word to the
output pins (00-7). Pulsing CE to TTL-low while
OE = VIH will program data. TTL levels are required
for address and data inputs.

Program Inhibit
The Program Inhibit mode allows parallel programming of multiple EPROMs with different data. With
Vpp at its programming voltage, a CE-Iow pulse programs the desired EPROM. CE-high inputs inhibit
programming of non-targeted devices. Except for CE
and OE, parallel EPROMs may have common inputs.

Program Verify
With Vpp and Vee at their programming voltages, a
verify (read) determines that bits are correctly programmed. The verify is performed with CE = ~
and OE = VIL. Valid data is available tOE after OE
falls low.

Optional Program Verify
The optional verify allows parallel programming and
verification when several devices share a common
bus. It is performed with CE = OE = VIL and Vpp =
Vee = 6.25V. The normal read mode is then used
for .E!:9gram~erify. Outputs will tri-state depending
on OE and CEo

inteligent Identifier™ Mode
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type. Programming equipment can automatically match a device
with its proper programming algorithm.
This mode is activated when programming equipment forces 12V ±0.5V on the EPROM's Ag address line. With A1-Aa, A1O-A12 = VIL (A13-14 are
don't care), address line Ao = VIL will present the
manufacturer's code and Ao = VIH'the device code
(see Table 1). When Ag = VH, ALE need not be
toggled to latch each identifier address. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

ERASURE CHARACTERISTICS (FOR
CERDIP EPROMS)
Exposure to light of wavelength shorter than 4000
Angstroms (A) begins EPROM erasure. Sunlight and
some fluorescent lamps have wavelengths in the
3000.,...4000A range. Constant exposure to room-Iev-'
el fluorescent light can erase an EPROM in about 3
years (about 1 week for direct sunlight). Opaque labels over the window will prevent unintentional erasure under these lighting conditions.
The recommended erasure procedure is exposure,
to 2537A ultraviolet light. The minimum integrated
dose (intensity x exposure time) is 15 Wsec/cm 2.
Erasure time using a'12000 p.W/cm2 ultraviolet
lamp is approximately 15 to 20 minutes. The
EPROM should be placed about 1 inch from the
lamp. The maximum integrated dose is 7258
Wsec/cm 2 (1 week @ 12000 p.W/cm 2 ). High intensity UV light exposure for longer periods can cause
permanent damage.

10-153

inter

87C257

290135'-10

Figure 5. Qulck·Pulse Programmlng™ Algorithm

CHMOS NOISE CHARACTERISTICS
System reliability is enhanced by Intel's CHMOS
EPI-process techniques. Protection on each data
and address pin prevents latch-up; even with 100
mA currents and voltages from -1V to Vee + 1V.
Additionally, the Vpp pin is designed to resist latchup to the 14V maximum device limit.
.

Quick-Pulse Programmlng™ Algorithm
The Quick-Pulse Programming algorithm programs
Intel's 87C257 EPROM. Developed to substantially
reduce production programming throughput time,
this algorithm can program a 87C257 in under four
seconds. Actual programming time depends on the
PROM programmer used.
.
The Quick-Pulse Programming algorithm uses a 100
microsecond initial-pulse followed by a byte verifica-

tion to determine when the addressed byte is correctly programmed. The algorithm terminates if 25
100/kS pulses fail to program a byte. Figure 5 shows
the Quick-Pulse Programming algorithm flowchart.
The entire program-pulse/byte-verify sequence is
performed with Vee = 6.25V and Vpp = 12.75V.
When programming is complete, all bytes should be
compared to the original data with Vee = 5.0V.

Alternate Programming
Intel's 27C256 and 27256 Quick-Pulse Programming
algorithms will also program the 87C257. By overrid. ing a check for the inteligent Identifier, older or nonupgraded PROM programmers can program the
87C257. See Intel's 27C256 and 27256 data sheets
for programming waveforms of these alternate algorithms.

10-154

intJ

87C257

D.C. PROGRAMMING CHARACTERISTICS

=

TA

25°C ±SoC

Table 2

Symbol

limits

Parameter
Min

III

Unit

1.0

).tA

0.8

V

Input Current (All Inputs)
-0.2

Test Conditions

Max

VIN

=

V

IOL

V

IOH

= 2.1 rnA
= -400).tA

CE

=

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

lee2(3)

Vee Supply Current

IpP2(3)

Vpp Supply Current (Program)

VIO

Ag inteligent Identifier Voltage

11.5

Vpp(1)

Programming Voltage

12.5

13.0

V

Ved 1)

Supply Voltage During Programming

6.0

6.5

V

2.0

Vee

+ 0.5

0.4
Vee - 0.8

VIL or VIH

V

30

rnA

50

rnA

12.5

V

VIL

A.C. PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C; see Table 2 for Vee and Vpp voltages.

Symbol

Limits

Parameter
Min

tAS

Address Setup Time

Typ

Conditions

Max

Unit

2

).ts

tOES

OE Setup Time

2

).ts

tos

Data Setup Time

2

).ts

tAH

Address Hold Time

0

).ts

tOH

Data Hold Time

2

).ts

tOFP(2)

OE High to
Output Float Delay

0

tVPS(1)

Vpp Setup Time

2

tves(1)

Vee Setup Time

2

tpw

CE Program Pulse Width

toE

Data Valid from OE

95

130

ns
).ts
).ts

100

105

).ts

150

ns

NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
3. The maximum current value is with outputs 00 to 07 unloaded.

10-155

'V

I

1

1"ta lig ent Identifier. • 1"ta ng ent identifier

I

Manufacturer

Ag

12.0 V . - - - - -

Address~::==>f

AO=VIL

=12.0V

JJ

I "

Dey;ce

Blank Check
Illegal Bit Check

'""'Z:AI-8'Al0-12=VIL~

ADDRESSVALID

I

I'

)~

Pro rom
g

ADDRESS STABLE

I

I

•

I

Program
Verify

I

I

.n;

•

Re~d

I

I

Verify

oC)
JJ
l>

"uun~JJ

,"",u

~

s:
s:

l

Z

Q

VIH

~

Data

VIL '

ALE;::el~ : ~ ~ -

- - - - - - - -

-1-- ~ ~ --~ -----t

<
m

."

oJJ

i

s:

65~~~

en

. --; - ---- --- T -----~ -----

Vee

..,.
01)

~

~
(J1

en

o
N

VIH

cr

..,.CI1

VIL
VIH

~

OE
VIL

290135-11

NOTES:
1. The input timing reference level is VIL = 0.8V and VIH = 2V.
2. toE and tOFP are device characteristics but must be accommodated by the programmer.
,
3. To prevent device damage durir]g programming, a 0.1 ,..F capacitor is required between Vpp and ground to suppress spurious voltage transients.
4. During programming, the address latch function is bypassed whenever Vpp = 12.75V or A9 = VH. When Vpp and A9 are at TTL levels, the address'latch function is
enabled, and the device functions in read mode.
'
'
'
5. Vpp can be 12.75V during Blank Check and Final Verify; if so, CE must be VIH.

~

aID
Iffiil
F

~
~

~
~

C:g

UPI-4S2
CHMOS PROGRAMMABLE 1/0 PROCESSOR
83C452 - 8K x 8 Mask Programmable Internal ROM
87C452P - 8K

x

8 Piggyback EPROM

80C452 - External ROM/EPROM

•
•
•
•
•
•
•

83C452/87C452P/80C452:3.5 to 16 MHz
Clock Rate
Software Compatible with the MCS-51
Family
128-Byte Bi-Directional FIFO Slave
Interface
Two DMA Channels
256 X 8-Bit Internal RAM
34 Additional Special Function
Registers
40 Programmable I/O Lines

•
•

Two 16-Bit Timer/Counters

•
•
•

64K Program Memory Space

Boolean Processor

Addressable RAM
• 8BitInterrupt
Sources
• Programmable
• Channel Full Duplex Serial
64K Data Memory Space
68-Pin PGA
(See Packaging Spec" Order: #231369)

,The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave 1/0 Processor with a sophisticated
bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip, The UPI-452
is the newest member of Intel's UPI family of products, It is a general-purpose slave 1/0 Processor that allows
the deSigner to grow a customized interface solution.
The UPI-452 contains 'a complete 80C51 with twice the on-chip data and program memory. The sophisticated
slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU. To both the
external host and the internal CPU, the FIFO module looks like a bi-directional bottomless buffer that can both
read and write data. The FIFO manages the transfer of data independent of the UPI-4S2 core CPU and
generates an interrupt or DMA request to either CPU, host or internal, as a FIFO service request.
The FIFO consists of two channels:the Input FIFO and the Output FIFO. The division of the FIFO module
array, 128 bytes, between Input channel and Output channel is programmable by the user. Each FIFO byte
has an additional logical ninth bit to distinguish between a data byte and a Data Stream Command byte.
Additionally, Immediate Commands allow direct, interrupt driven, bi-directional communication between the
UPI-452 internal CPU and external host CPU, bypassing the FIFO.
The on-chip DMA processor allows high speed data transfers from one writeable memory space to another.
As many as 64K bytes can be transferred in a, single DMA operation. Three distinct memory spaces may be
used in DMA operations; Internal Data Memory, External Data Memory, and the Special Function Registers
(including the FIFO IN, FIFO OUT, and Serial Channel Special Functions Registers).

10-157

September 1987
Order Number: 231428-003

l

o

o'"
00

,Q
c'"

_z

~":::"

C

!1;

!II

o

01 ~I'"
~ ~I

.....

"II

I

illi
o

Z

o»o::::!;;Itn
~z!:"''i:

iiii
r:::

...

~c~~~

ID

...

:-"
:I>

...n

'"

~

~

41>-

FIFO
INPUT
CHANNEL

FIFO
MODULE
SLAVE-

U1
CX>

"

FIFO
OUTPUT
CHANNEL

-

HOSTFIFO
INTERFACE

~m

:::T

.....
~

-

-fl- ---------ft --- i:~
"

;::;:

srn~

INTERFACE

ID

HCON

2r:::

HSTAT

., '."

et

~

"'z

:::a 00

it

0

AO~Z

- - - - - - - - - -l} - -

NfAf'TIC

r-

o~I

I

...:',

-

-

-

~
IMMEDIATE
COMMAND

-I

I

~I~

,

HOST DMA
AND
INTERRUPT
REQUEST

Iroo; I

II

,,~

: ;

m
0'
n

: i
:J.r.::. __ .JL_-,
#"

~

~

C

iii"

ea

ii1

•

....

•

I

I

I

•

~
~

DMA TIMING
AND CONTROL

",L
~

~

co

.!..

@

~

1,/

DAR 0
BCRO

~@

-

--

PI)

~
l§!

TI

3

~

~

~
©

DCON1
SAR1
DAR 1
BCR 1

'iiiI

22J
oJ

~
~
~

@
~

inter

UPI·452

~-----------------~------,

i>sEN
ALE

EA
RST

231428-2

Figure 1. Architectural Block Diagram (Continued)

10-159

UPI-4S2

TABLE OF CONTENTS
Introduction
Table of Contents
List of Tables and Figures
Pin Description
Architectural Overview
Introduction
FIFO Buffer Interface
FIFO Programmable Features
Immediate Commands
DMA
FIFO/Slave Interface Functional Description
Overview
Input FIFO Channel
Output FIFO Channel
Immediate Commands
Host & Slave Interface Special Function Registers
Slave Interface Special Function Registers
External Host Interface Special FunctionRegisters
FIFO Module-External Host Interface .
Overview
Slave Interface Address Decodin£ .
Interrupts to the Host
DMA Requests to the Host
FIFO Module-Internal CPU Interface
Overview
Internal CPU Access to FIFO via Software Instructions
General Purpose DMA Channels
Overview
Architecture
DMA Special Function Registers
DMA Transfer Modes
External Memory DMA
Latency
DMA Interrupt Vectors
Interrupts When DMA is Active
DMA Arbitration
Interrupts
Overview
FIFO Module Interrupts to Internal CPU
Interrupt Enabling and Priority
FIFO-External Host Interface FIFO DMA Freeze Mode
Overview.
Initialization
Invoking FIFO DMA Freeze Mode During Normal Operation
. FIFO Module Special Function Register Operation During FIFO DMA Freeze Mode
Internal CPU Read & Write of the FIFO During FIFO DMA Freeze Mode
Memory Organization
Accessing External Memory
Miscellaneous Special Function Register Descriptions

10-160 .

intJ

UPI-452

LIST OF TABLES AND FIGURES
Figures:

1.
2.
3.
4.
5.
6.
7a.
7b.
8.
9.
10.
11.
12.

Tables:

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11 a.
11 b.
12.
13.

Architectural Block Diagram
UPI-452 68-Pin PGA Pinout Diagram
UPI-452 Conceptual Block Diagram
UPI-452 Functional Block Diagram
Input FIFO Channel Functional Block Diagram
Output FIFO Channel Functional Block Diagram
Handshake Mechanisms for Handling Immediate Command IN Flowchart
Handshake Mechanisms for Handling Immediate Command OUT Flowchart
DMA Transfer from: External to External Memory
DMA Transfer from: External to Internal Memory
DMA Transfer from: Internal to External Memory
DMA Transfer Waveform: Internal to Internal Memory
Disabling FIFO to Host Slave Interface Timing Diagram

Input FIFO Channel Registers
Output FIFO Channel Registers
UPI-452 Address Decoding
DMA Accessible Special Function Registers
DMA Mode Control - PCON SFR
Interrupt Priority
Interrupt Vector Addresses
Slave Bus Interface Status During FIFO DMA Freeze Mode
FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Threshold SFRs Range of Values and Number of Bytes to be Transferred
80C51 Special Function Registers
UPI-452 Additional Special Function Registers
Program Status Word (PSW)
PCON Special Function R~gister

10-161

inter

UPI-452

t

..
.... ....'"

..:

~

0..

@)

@@
@@

®

'0
Q)

~
1:
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c

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8

P4.S

P4.6

~

°...

N

...

C!

0..

0..

0..

OJ

0..

~

::l
0..

"!

"!

0..

0..

OJ

"1
OJ

0..

OJ

.,
N
0..

@ @ @ @ @

@ @ @ @ @

.

'"
... ~'"....
III

'"

.<

...N

~
@@
@@
0..

@

Pmi

EA

P4.7

XTAL1

@

@ @

PO.7

PO.6

. XTAL2

AO

@ @

@ @

PO.S

PO.4·

Al

A2

@ @

@ @

PO.3

PO.2

@

PO.l

Vss

po.o

PLO

Q)

=-E
,g
'C

·1

1~

>'E
'E~
... .0

Vss

ell

@ @

~

READ

@ @

WRITE

DRQOUT/
INTRQOUT

@ @

DRQIN/
INTRQIN

INTRQ

@) @

DB7

DBS

.!!ti
.n.

€D @@

@ @ @ @ @ @

®
® 0
® ®
0 0
®  C

€D @@

..
..'" ..'"
"1

'" '"

..;

":

..;

"!

"'!

C!

"1
0:

u

....

0..

'"
0..

0..

0:

'\(

@ @

PO.3

PO.2
PO.4
PO.6

@) @

DRQOUTj
INTRQOUT

@ @

~

READ

@ @

@ @ @ @ @ @

Pl.S

Pl.6

Pl.3

Pl.4

Pl.l

Pl.2

PO.O

PLO

PO.l

Vss

Al

A2

XTAL2

AO

@ @

@ @

po.s

P4.7

XTAL1

@ @

@ @

PO.7

P4.S

P4.6

0>"

>~

PIN NO.1
MARK

@ @

INTRQ

WiiiTE

Vss

PIN NO.1
MARK

0:'

0..

,;'

III 0

1~

Pl.6

cs @ @

DRQIN/
INTRQIN

_01

-g.8

Pl.S

®  c

c

Q)

o c

c,o

ec'
o E
1J8

@)

@@
@@
.... ..."1

..

0..

...
...

.

~

0..

@@ @ @ @
@ @ @ @ @
"1
:.;: C! ....
0..

...
0

0..

OJ

0..

..
N

N
0..

~u
u

>

.'"

N

...
N
0..

N
0..

..
N
0..

@@
@@
":

OJ
0..

...

EA

I~

..

'" ~'"'"

III

....
<

Figure 2. UPI-4S2 68-Pin PGA Pinout Diagram

10-162

@ Pmi

231428-18

inter

UPI-452

UPI MICROCONTROLLER FAMILY

Packaging

The UPI-452 joins the current members of the UPI
microcontroller family. UPl's are derivatives of the
MCSTM family of microcontrollers. Because of their
on-chip system bus interface, UPl's are designed to
be system bus "slaves", while their microcontroller
counterparts are intended as system bus "masters".

The 80C452 comes in a 68-pin PGA (Pin Grid Array)
package, while the 87C452P will be offered in a piggyback package. This piggyback package will consist of the standard 68-pin PGA package with a
2764A EPROM soldered on top. These two packages allow designers to use either on-chip EPROM
or external memory for their initial designs. The
83C452 (ROM version) will come in the standard 68pin PGA package. A complete description of
87C452P programming can be found at the end of
this data sheet.

These UPI Microcontrollers are fully supported by
Intel's EPROM programmers (iUP-201) and development tools (ICE, ASM and PLM).

UPI Family
(Slave
Configuration)

MCSFamily
(Master
Configuration)

Speed

RAM
(Bytes)

ROM
(Bytes)

EPROM
(Bytes)

80C452

80C51

12MHz

256

-

83C452

80C51

12 MHz

256

8K

-

87C452P

80C51

12 MHz

256

-

8K

80C452-1

80C51

16MHz

256

-

83C452-1

80C51

16 MHz

256

8K

-

87C452P-1

80C51

16 MHz

256

-

8K

UPI-4S2 PIN DESCRIPTIONS
Symbol

Pin #
9/43
60

Type
I
I

XTAL1

38

I

XTAL2
PortO
(ADO-AD7)
PO.O
.1
.2
.3
.4
.5
.6
PO.7

39

Vss
Vee

0
I/O

8
10
11
12
13
14
15
16

Name and Function
Circuit Ground.
+ 5V power supply during normal, idle, programming and
verification operation. It is also the standby power pin for power
down mode.
..
Input to the oscillator's high gain amplifier. A crystal or external
source can be used.
Output from the high gain amplifier.
Port 0 is an 8-bit open drain bi-directional I/O port. It is used for data
input and output during programming and verification. External
pull ups are required during program verification. Port 0 can sink
eight LS TIL inputs. It is also the multiplexed low-order address and
data local expansion bus during accesses to external memory.

10-163

inter

UPI-452

UPI-452 PIN DESCRIPTIONS (Continued)
Symbol
Port 1

Pin #

Type
1/0

Name and Function
Port 1 is an 8-bit quasi-bi-directionaII/O-port.lt is used for low-order
address byte during programming and verification. Port 1 can sink
four LS TIL inputs. The alternate functions can only be activated if
the corresponding bit latch in the port SFR contains a 1. Otherwise,
the port pin is stuck at O. Pins P1.5 and P1.6 are multiplexed with
HLD and HLDA respectively whose functions are defined as below:
Port Pin
Alternate Function
P1.5
HLD -Local bus hold
input/output signal
HLDA -Local bus hold
P1.6
acknowledge input

1/0

Port 2 is an 8-bit quasi-bi-directionaII/O port. It also emits the high- order 8 bits of address when accessing local expansion bus
external memory (or during 87C452P programming and verification) .
Port 2 can sink four LS TIL inputs .

1/0

Port 3 is an 8-bit quasi-bi-directionaII/O port. It is also multiplexed
with the interrupt, timer, local serial channel, RDI and WRI
functions that are used by various options. The alternate functions
can only be activated if the corresponding bit latch in the port SFR
contains a 1. Otherwise, the port pin is stuck at O. Port 3 can sink
four LS TIL inputs. The alternate functions assigned to the pins of
Port 3 areas follows:
Port Pin
Alternate Function
P3.0
RxD
- Serial input port
P3.1
TxD
- Serial output port
P3.2·
INTO
- Interrupt 0 Input
P3.3
INT1
- Interrupt 1 Input
P3.4
TO
- Input to counter 0
P3.5
T1
- Input to counter 1
P3.6
WRI
- The write control signal latches the
data from Port 0 outputs into the
External Data Memory on the
local bus.
RDI
- The read control signal latches the
P3.7
data from Port 0 outputs on the
local bus.

(AO-A~

(HLD, HLDA)
P1.0

.1
.2 _
,.3
.4
.5
.6
P1.7
Port 2
(AS-A15)
P2.0
.1
.2
.3
.4
.5
.6
.7
Port 3
P3.0
.1

.2
.3
.4
.5
.6
P3.7

7

.6
5
4
3
2
1
68

29
28
27
25
24
23
22
21
67
66

65
6463
62
61
59

10-164

intJ

UPI·452

UPI·452 PIN DESCRIPTIONS (Continued)
Symbol
Port 4
P4.0
.1
.2
.3

Pin #

Type
I/O

Name and Function
Port 4 is an 8-bit quasi-bi-directionall/O port. Port 4 can sink/source
four TIL inputs. It is also used as the control signals during EPROM
programming and verification drive pins as follows:
Port Pin
Alternate Function
P4.5
'1' during program and verify
P4.6
'0' during program and verify
'0' during verify - used as output enable
P4.7
'1' during programming w/ ALE = 0
Note: see Programming and Verification Characteristics in AC/DC
Specification section.

.5
.6
.7

30
31
32
33
34
35
36
37

RST

20

I

ALE/PGM

18

110

PSEN

19

0

EA

17

I

DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7

110

CS

58
57
56
55
54
53
52
51
44

I

This pin is the Chip Select of the UPI-452.

AO
A1
A2

40
41
42

I

These three address lines are used to interface with the host system.
They define the UPI-452 operations. The interface is compatible with
.
the Intel microprocessors and the MULTIBUS.

READ

46

I

WRITE

47

I

DRaiN/
INTRalN

49

0

DRaOUT/
INTRaOUT

48

0

.4

A high level on this pin for two machine cycles while the oscillator is
running resets the device. An internal pulldown resistor permits Poweron reset using only a capacitor connected to Vee.
This pin does not receive the power down voltage as is the case for
HMOS MCS-51 family members. This function has been transferred to
the Vee pin.
Provides Address Latch Enable output used for latching the address
into external memory during normal operation. Receives the program
pulse input during EPROM programming. ALE can sink/source eight LS
TIL inputs.
The Program Store Enable output is a control signal that enables the
external Program Memory to the bus during normal fetch operation.
PSEN can sink/source eight LS TIL inputs.
When held at TIL high level, the UPI-452 executes instructions from the
internal ROM/EPROM when the PC is less than 8192 (8K, 2000H).
When held at a TTL low level, the UPI-452 fetches all instructions from
external Program Memory.
Host Bus Interface is an 8-bit bi-directional bus. It is used to transfer
data and commands between the UPI-452 and the host processor. This
bus can sink/source eight LS TIL inputs.

This pin is the read strobe from the host CPU. Activating this pin causes
the UPI-452 to place the contents of the Output FIFO (either a
command or data) or the Host Status/Control Special Function Register
on the Slave Data Bus.
.This pin is the write strobe from the host. Activating this pin will cause
the value on the Slave Data Bus to be written into the register specified
by AO-A2.
This pin requests an input transfer from the host system whenever the
Input Channel requires data.
This output pin requests an output transfer whenever the Output
Channel requires service. If the external host to UPI-452 DMA is
enabled, and a Data Stream Command is at the Output FIFO, DRaOUT
is deactivated and INTRa is activated (see 'GENERAL PURPOSE DMA
CHANNELS' section).

10-165

intJ

UPI·452

UPI·452 PIN DESCRIPTIONS (Continued)
Symbol

Pin #

INTRQ

50

Type
0

DACK

45

I

VeelVpp

26

I

Name and Function
This output pin is used to interrupt the host processor when an
Immediate Command Out or an error condition is encountered. It is
also used to interrupt the host processor when the FIFO requests
service if the DMA is disabled and INTRQIN and INTRQOUT are
not used.
This pin is the DMA acknowledge for the host bus interface Input
and Output Channels. When activated, a write command will cause
the data on th~ Slave Data Bus to be written as data to the Input
Channel (to the Input FIFO). A read command will cause the Output
Channel to output data (from the Output FIFO) on to the Slave Data
Bus. This pin should be driven high (+ 5V) in systems which do not
have a DMA controller (see Address Decoding).

+ 5V power supply during operation. The Vee pin receives the
+ 12V EPROM programming and verification supply voltage.
scription of the UPI-4S2's core CPU functional
blocks including;

ARCHITECTURAL OVERVIEW

-

Introduction

Timers/Counters

-I/O Ports

The UPI-452 slave microcontroller incorporates an
80C51 with double the program and data memory, a
slave interface which allows it to be connected directly to the host system bus as a peripheral, a FIFO
buffer module, a two channel OMA processor, and a
fifth I/O port (Figure 3). The UPI-452 retains all of
the 80C51 architecture, and is fully compatible with
the MCS-51 instruction set.
The Special Function Register (SFR) interface concept introduced in the MCS-51 family of .microcontrollers has been expanded in the UPI-452. To the
20 Special Function Registers of the MCS-51, the
UPI-452 adds 34 more. These additional Special
Function Registers, like those of the MCS-5.1, provide access to the UPI-452 functional elements including the FIFO, DMA and added interrupt capabilities. Several of the 80C51 core Special Function
Registers have also been expanded to support added features of the UPI-4S2.
This data sheet describes the unique features of the
UPI-452. Refer to the 80C51 data sheet for a de-

-

Interrupt timing and control (other than FIFO and
DMA interrupts)

-

Serial Channel

=

Local Expansion Bus

-

Program/Data Memory structure

-

Power-Saving Modes of Operation •

-

CHMOS Features

-

Instruction Set

• except 87C452P piggyback package
Figure 3 contains a'conceptual block diagram of the
UPI-452. Figure 4 provides a functional block diagram.

FIFO Buffer Interface
A unique feature of the UPI-452 is the incorporation
of a 128 byte FIFO array at the host-slave interface.
The FIFO allows asynchronous bi-directional transfers between the host CPU and the internal CPU.

231428-7

Figure 3. UPI-452 Conceptual Block Diagram
10-166

UPI·452

F-.?"=:::":";

ADDITIONAL FEATURES: I
-SERIAL CHANNEL
I
-EXTERNAL INTERRUPTS I

~~~~ . :~~g{~~~~~~SION

~

BUS
-RD
-WR
-EXTERNAL
COUNTER INPUT
-EPROM PROGRAM
AND VERIFY
_ ..c~~~O_L __ • ___ _

231428-8

Figure 4. UPI-452 Functional Block Diagram
The division of the 128 bytes between Input and
Output channels is user programmable allowing
maximum flexibility. If the entire 128 byte FIFO is
allocated to the Input channel, a high performance
Host can transfer up to 128 bytes at one time, then
dedicate its resources to other functions while the
internal CPU processes the data in the FIFO. Various handshake signals allow the external Host to
operate independently and without frequent monitoring of the UPI-452 internal CPU. The FIFO Buffer
insures that the slave processor receives data in the
same order that it was sent by the host without the
need to keep track of addresses. Three slave bus
interface handshake methods are supported by the
UPI-452: DMA, Interrupt and Polled.
The FIFO is nine bits wide. The ninth bit acts as a
command/data flag. Commands written to the FIFO
by either the host or internal CPU are called Data
Stream Commands or DSCs. DSCs are written to
t~e input FIFO by the Host via a unique external
address. DSCs are written to the output FIFO by the
internal CPU via the COMMAND OUT Special Function Register (SFR). When encountered by the host
or internal CPU a Data Stream Command can be
used as an address vector to user defined service
routines, DSCs provide synchronization of data and
commands between the Host and internal CPU.

nel Boundary Pointer (CBP) SFR. This register contains the number of address locations assigned to
the Input channel. The remaining address locations
are automatically assigned to the Output FIFO. The
CBP SFR can only be programmed by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-External. Host Interface FIFO DMA Freeze Mode description). The CBP is initialized to 40H (64 bytes)
upon reset.
The number in the Channel Boundary Pointer SFR is
actually the first address location of the Output
FIFO. Writing to the CBP SFR reassigns the Input
and Output FIFO address space. Whenever the CBP
is written, the Input FIFO pointers are reset to zero
and the Output FIFO pointers are set to the value in
the CBP SFR.
All of the FIFO space may be assigned to one channel. In such a situation the other channel's data path
consists of a single SFR (FIFO IN/COMMAND IN or
FIFO OUT/COMMAND OUT SFR) location. .
CBP
Register

Size of Input/Output Channels
The 128 bytes of FIFO space can be allocated between the Input and Output channels via the Chan10-167

Output FIFO
Size

3
4

1
1
2
3
4

128
128
126
125
124

7B
7C
7D
7E
7F

123
124
125
128
128

5
4
3
1
1

0
1

2

•

FIFO PROGRAMMABLE FEATURES

InputF.IFO
Size

•

•

UPI-452

FIFO Read/Write Pointers
These normally operate in auto-increment (and autorollover) mode, but can be reassigned by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-External Host Interface FIFO DMA Freeze Mode de.
scription).

Threshold Register
The Input FIFO Threshold SFR contains the number
of empty bytes that must be available in the Input
FIFO to generate a Host interrupt. The Output FIFO
Threshold SFR' contains the number of bytes, data
and/or DSC(s), that must be in the FIFO before an
interrupt is generated. The Threshold feature prevents the Host from being interrupted each time the
FIFO needs to load or unload one byte of data. The
thresholds, therefore, allow the FIFO's operation to
be adjusted to the speed of the Host, optimizing the
overall interface performance.

of the three·writeable memory spaces: Internal Data
Memory, External Load Expansion Bus Data Memory and the Special Function Register array. The Special Function Register array appears as a set of
unique dedicated memory addresses which may be
used as either the source or destination address of a
DMA transfer. Each DMA channel is independently
programmable via dedicated Special Function Registers for mode, source and destination addresses,
and byte count to be transferred. Each DMA channel
has four programmable modes:
.
-

Alternate Cycle Mode

--, Burst Mode
-

FIFO or Serial Channel Demand Mode

-

External Demand Mode

A complete description of each mode and DMA operation m~y be found in the section titled "General
Purpose DMA Channels".

FIFO/SLAVE INTERFACE
FUNCTIONAL DESCRIPTION

Immediate Commands
The UPI-452 provides, in addition to data and DSCs,
a third direct means of communication between the
external Host and internal CPU called Immediate
C-ommends. As the name implies, an !mmediate.
Command is available to the receiving'CPU immediately, via an interrupt, without being entered into the
FIFO as are Data Stream Commands. Like Data
Stream Commands, Immediate Commands are written either via a unique external address by the host
CPU, or via dedicated SFR by the internal CPU.
The DSC and/or Immediate Command interface
may be defined as either Interrupt or Polled under
user program control via the Interrupt Enable (IE),
Slave Control Register (SLCON), and, Interrupt Enable Priority (IEP) Special Function Registers, for the
internal CPU and via the Host Control SFR for the.
external Host CPU.

DMA
The UPI-452 contains a two channel internal DMA
controller which allows transfer of data between any

Overview
The FIFO is a 128 Bvte RAM arrav with recirculatina
pointers to manage- the read and write accesseS.
The FIFO consists of an Input and an Output channel. Access cycles to the FIFO by the internal CPU
and external Host are interleaved and appear to be
occurring concurrently to both the internal CPU and
external Host. Interleaving access cycles ensures
efficient use of this shared resource. The internal
CPU accesses the FIFO in the same way it would
access any of the Special Function Registers e.g.,
direct and register indirect addressing as well as arithmetric and logical instructions.

Input FIFO Channel
The. Input FIFO Channel provides for data transfer
from the external Host to the internal CPU (Figure 5).
The registers associated with the Input Channel during normal operation are listed in Table 1*.

Table 1. Input FIFO Channel Registers'

1)
2)
3)
4)
.5)
6)

Register Name

Description

Input Buffer Latch
FIFO IN SFR
COMMAND IN SFR
Input FIFO Read Pointer SFR
Input FIFO Write Pointer SFR
Input FIFO Threshold SFR

Host CPU Write only
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only

..

..

'See "'FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE" section for FIFO DMA Freeze Mode SFR charactenstlcs deSCription .

10-168

inter

UPI-4S2

EXTERNAL HOST
CPU
EXTERNAL
ADDRESS

HOST DATA
BUS

INPUT WRITE
POINTER (IWPR)
!::
ID

THRESHOLD SFR
(ITHR)

INPUT FIFO

i!:

'"
z

INPUT READ
POINTER (IRPR)

231428-9

Figure 5. Input FIFO Channel Functional Block Diagram

The host CPU writes data and Data Stream Com·
mands into the Input Buffer Latch on the rising edge
of the external WR signal. External addressing de·
termines whether the byte is a data byte or Data
Stream Command and the FIFO logic sets the ninth
bit of the FIFO accordingly as the byte is moved
from the Input Buffer Latch into the FIFO. A "1" in
the ninth bit indicates that the incoming byte is a
Data Stream Command. The internal CPU reads
data bytes via the FIFO IN SFR, and Data Stream
Commands via the COMMAND IN SFR.
A Data Stream Command will generate an interrupt
to the internal CPU prior to being read and after
completion of the previous operation. The DSC can
then be read via the COMMAND IN SFR. Data can
only be read via the FIFO IN SFR and Data Stream
Commands via the COMMAND IN SFR. Attempting
to read Data Stream Commands as data by address·
ing the FIFO IN SFR will result in '~OFFH" being
read, and -the Input FIFO Read Pointer will remain
intact. (This prevents accidental misreadin,9 of Data
Stream Commands.) Attempting to read data as
Data Stream Commands will have the same conse·
quence.

The Inl'lut FIFO Channel addressing is controlled by
the Input FIFO Read and Write Pointer SFRs. These
SFRs are read only registers during normal opera·
tion. However, during FIFO DMA Freeze Mode (See
FIFO·External Host Interface FIFO DMA Freeze
Mode description),. the internal CPU has write access to them. Any write to these registers in normal
mode will have no effect. The Input Write Pointer
SFR contains the address location to which datal
commands are written from the Input Buffer Latch.
The write pointer is automatically incremented after
each write and is reset to zero if equal to the CBP,
as the- Input FIFO operates as a circular buffer.
If a write is performed on an empty FIFO, the first
byte is also written into the FIFO IN or COMMAND
IN SFR. If the Host continues writing while the Input
FIFO is full, an external interrupt, if enabled, is sent
to the host to Signal the overrun condition. The
writes are ignored by the FIFO control logic. Similar·
Iy, an internal CPU read of an empty FIFO will cause
an underrun error interrupt to be generated to the
internal CPU and a value of "OFFH" will be read by
the internal CPU.

10·169

UPI-452

The Read Pointer SFR holds the address of the next
byte to be read from the Input FIFO. An Input FIFO
read operation post-increments the Input Read
Pointer SFR and loads a new data byte into the
FIFO IN SFR or a Data Stream Command into the
COMMAND IN SFR at the end of the read cycle.
An Input FIFO Request for Service (via DMA, Interrupt or a flag) is generated to the Host whenever
more data can be written into the Input FIFO. For
efficient utilization of the Host, a "threshold" value
can be programmed into the Input FIFO Threshold
SFR. The range of values of the Input FIFO Threshold SFR can be from 0 to (CBP-2). The Request for
Service Interrupt is generated only after the Input
FIFO has room to accommodate a threshold number
of bytes or more. The threshold is equal to the total'

number of bytes assigned to the Input FIFO (CBP)
minus the number of bytes programmed in the Input
FIFO Threshold SFR. With this feature the Host is
assured that it can write at least a threshold number
of bytes to the Input FIFO channel without worrying
about an overrun condition. Once the Request for
Service is generated it remains active until the Input
FIFO becomes full.

Output FIFO Channel
The Output FIFO Channel provides data transfer
from the UPI-452 internal CPU to the external Host
(Figure 6).
The registers associated with the Output Channel
during normal operation are listed in Table 2*.

231428-10

Figure 6. Output FIFO Channel Functional Block Diagram
Table 2. Output FIFO Channel Registers

1)

2)
3)

4)
5)
6)

Register Name

Description

Output Buffer Latch
FIFO OUT SFR
COMMAND OUT SFR
Output FIFO Read Pointer SFR
Output FIFO Write Pointer SFR
Output FIFO Threshold SFR

Host CPU Read only
Internal CPU Read and Write
Internal CPU Read and Write
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only

'See "'FIFO·EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE"' section for FIFO DMA Freeze Mode register characteristics description.

10-170

inter

UPI-4S2

The UPI-452 internal CPU transfers data to the Output FIFO via the FIFO OUT SFR and commands via
the COMMAND OUT SFR. If the byte is written to
the COMMAND OUT SFR, the ninth bit is automatically set (= 1) to indicate a Data Stream Command.
If the byte is written to the FIFO OUT SFR the ninth
bit is cleared (=0). Thus the FIFO OUT and COMMAND OUT SFRs are the same but the address determines whether the byte entered in the FIFO is a
DSC or data byte.
The Output FIFO preloads a byte into the Output
Buffer Latch. When the Host issues a RD/ signal,
the data is immediately read from the Output Buffer
Latch. The next data byte is then loaded into the
Output Buffer Latch, a flag is set and an interrupt, if
enabled, is generated if the byte is a DSC (ninth bit
is set). The operation is carefully timed such that an
interrupt can be generated in time for it to be recognized by the Host before its next read instruction.
Internal CPU write and external Host read operations are interleaved at the FIFO so that they appear
to be occurring concurrently.
The Output FIFO read and write pointer operation is
the same as for the Input Channel. Writing to the
FIFO OUT or COMMAND OUT SFRs will increment
the Output Write Pointer SFR but reading from it will
leave the write pointer unchanged. A rollover of the
Output FIFO Write Pointer causes the pointer to be
reset to the value in the Channel Boundary Pointer
(CBP) SFR.
.
If the external host attempts to read a Data Stream
Command as a data byte it will result ,in invalid data
(OFFH) being read. The DSC is not lost because the
invalid read does not increment the pointer. Similarly
attempting to read a data byte as a Data Stream
Command has the same result.
A Request for Service is generated to the external
Host under the following two conditions:
1.) Whenever the internal CPU has written a threshold number of bytes or more intothe Output FIFO
(threshold = (OTHR) + 1). The threshold number should be chosen such that the bus latency
time for the external Host does not result in a
FIFO overrun error condition on the internal CPU
side. The threshold limit should be large enough
to make a bus request by the UPI-452 to the external host CPU worthwhile. Once a request for
service is generated, the request remains active
until the Output FIFO becomes empty. The range
of values of the FIFO Output Threshold (OTHR)
SFR is from 1 to the Output FIFO Size. The
threshold number can be programmed via the
OTHR SFR.

2.) The second type of Request for Service is called
"Flush Mode" and occurs when the internal CPU
writes a Data Stream Command into the Output
FIFO. Its purpose is to ensure that a data block
entered into the Output FIFO, which is less than
the programmed threshold, will generate a Request for Service interrupt, if enabled, and be
read, or "Flushed" from the Output FIFO, by the
external host CPU regardless of the status of the
OTHR SFR.

Immediate Commands
Immediate Commands provide direct communication between the external Host and UPI-452. Unlike
Data Strearri Commands which are entered into the
FIFO, the Immediate Command is available to the
receiving CPU directly, bypassing the FIFO. The Immediate Command can serve as a program vector
pOinting into a jump table in the recipients software.
Immediate Command Interrupts are generated, if enabled, and a bit in the appropriate Status Register is
set when an Immediate Command is input or output.
A similar bit is provided to acknowledge when an
Immediate Command has been read and whether
the register is available to receive another command. The bits are reset when the Immediate Commands are read. Two Special Function Registers are
dedicated to the Immediate Command interface. External addressing determines whether the Host is
accessing the Input FIFO or the Immediate Command IN (IMIN) SFR. The internal CPU writes Immediate Commands to the Immediate Command OUT
(IMOUT) SFR.
Both processors have the ability to enable or disable
Immediate Command Interrupts. By disabling the interrupt, the recipient of the Immediate Command
can poll the status SFR and read the Immediate
Command at its convenience. Immediate Commands should only be written when the appropriate
Immediate Command SFR is empty (as indicated in
the appropriate status SFR:HSTAT/SSTAT). Similarly, the Immediate Command SFR should only be
read when there is data in the Register.
The flowcharts in Figure 7a and 7b illustrate the
proper handshake mechanisms between the external Host and internal CPU when handling Immediate
Commands.

10-171

infef

UPI-4S2

r----------------

SET

SET

a

\:V
,

....

.oil
GENERATES INTERRUPT
TO INTE.RNAL CPU

GENERATES
INTERRUrT TO HOST

,

,

,,

)

)

• 4

SET

SET

a

\:V
,

,

.oil

.oil

GENERATES
INTERRUPT TO HOST

GENERATES INTERRUPT
TO INTE.RNAL CPU

,,

,,

-----------------~

231428-11

Figure 7a. Handshake Mechanisms for Handling
Immediate Command IN Flowchart

...

_----231428-12

Figure 7b. Handshake Mechanisms for Handling
Immediate Command OUT Flowchart

10-172

inter

UPI-4S2

HOST & SLAVE INTERFACE SPECIAL FUNCTION REGISTERS
Slave Interface Special Function Registers
The Internal CPU interfaces with the FIFO slave module via the following registers:
1) Mode Special Function Register (MODE)
2) Slave Control Special Function Register (SLCON)
3) Slave Status Special Function Register (SSTAT)
Each register resides in the SFR Array and is accessible via all direct addressing modes except bit. Only the
Slave Control Register (SLCON) is bit addressable.

1) MODE Special Function Register (MODE)
The MODE SFR provides the primary control of the external host-FIFO interface. It is included in the SFR
Array so that the internal CPU can configure the external host-FIFO interface should the user decide that the
UPI-452 slave initialize itself independent of the external host CPU.
The MODE SFR can be directly modified by the internal CPU through direct address instructions. It can also be
indirectly modified by the external host CPU by setting up a MODE SFR service routine in the UPI-452 program
memory and having the host issue a Command, either Immediate or DSC, to vector to that routine.

Symbolic
Address

Physical
Address

MODE

MD6

MD5

OF9H

MD4

(MSB)
Status On Reset:

1"

o

(LSB)

o

o

1*

1"

MD7

(reserved)"'

MD6

Request for Service to external CPU via;
1 = DMA (DRQIN/DRQOUT) request to external host when the Input or Output FIFO channel requests service

o

MD5

= Interrupt (INTRQIN/INTRQOUT or INTRQ) to external host when the Input or Output FIFO
channel requests service or a DSC is encountered in the I/O Buffer Latch
Configure DRQIN/INTRQIN and DRQOUT/INTRQOUT to be either;
1 = Enable (Actively driven)

o=
MD4

Disable (Tri-state)

Configure INTRQ to be either;
1

= Enable (Actively driven)

o=

Disable (Tri-state)

MD3

(reserved)' *

MD2

(reserved)"

MD1

(reserved)"

MDO

(reserved)"

2) Slave Control SFR (SLCON)
The Slave Control SFR is used to configure the FIFO-internal CPU interface. All interrupts are to the internal
CPU.

10-173

inter

UPI-452

Symbolic
Address
SLCON

IFI

OFI

ICII

I'

Physical
Address
ICOI

FRZ

IFRS

o
IFI

OFI

ICII

ICOI

FRZ

SC2
IFRS

OFRS

o

·OFRS

OE8H

(LSB)

(MSB)
Status On Reset:

o

o

o

1"

o

o

Enable Input FIFO Interrupt (due to Underrun Error Condition, Data Stream Command or Request
Service)
1 = Enable
0= Disable
Enable Output FIFO Interrupt (due to Overrun Error Condition or Request Service)
1 = Enable
0= Disable
Note: If the DMA ill configured to service a FIFO demand, then the Request for Service Interrupt is
not generated.
Generate Interrupt when a command is written to the Immediate Command in Register
1 = Enable
0= Disable
Generate Interrupt when Immediate Command Out Register is Available
1 = Enable
0= Disable
Enable FIFO DMA Freeze Mode
1 = Normal operation
o = FIFO DMA Freeze Mode
(reserved) ••
Input FIFO Channel Request for Service
1, = Request when Input FIFO not empty
o = Request when Input FIFO full
Output FIFO Channel Request for Service
1 = Request when Output FIFO not full
o = Channel Request when Output FIFO empty
NOTES:

°A '1' will be read from all SFR reserved locations except HCON SFR,HCO and HC2.
"'reserved'-these locations are reserved for future use by Intel Corporation.

3) Slave Status SFR (SSTAT)
The bits in the Slave Status SFR reflect the status of the FIFO-internal CPU interface. It can be read during an
internal interrupt service routine to determine the nature of the interrupt or read during a polling sequence to
determine a course of action.

Symbolic
Address

Physical
Address

, SSTAT

OE9H

o

o

o

(MSB)

(LSB)

10-174

inter
SST7

UPI-452

Output FIFO Overrun Error Condition
1 = No Error

o=
SSTS

Error (latched until Slave Status SFR is read)
Immediate Command Out Register Status
1 = Full (Le. Host CPU has not read previous Immediate Command Out sent by internal CPU)

0= Available
SST5

FIFO DMA Freeze Mode Status
1 = Normal Operation
FIFO DMA Freeze Mode in Progress

o=
SST4

Output FIFO Request for Service Flag
1 = Output FIFO does not request service
Output FIFO requests service

o=
SST3

Input FIFO Underrun Error Condition Flag
1 = No Underrun Error

o=
SST2

Underrun Error (latched until Slave Status SFR is read)

Immediate Command In SFR Status
1 = Empty
Immediate Command received from host CPU

o=
SST1

Data Stream Command/Data at Input FIFO Flag
1 = Data (not DSC)

o=
SSTO

DSC (at COMMAND IN SFR)

Input FIFO Request For Service Flag
1 = Input FIFO Does Not Request Service

o=

Input FIFO Request for Service

EXTERNAL HOST INTERFACE SPECIAL FUNCTION REGISTERS
The external host CPU has direct access to the following SFRs:
1) Host Control Special Function Register
2) Host Status Special Function Register
It can also access other SFRs by commanding the internal CPU to change them accordingly via Data Stream
Commands or Immediate Commands. The protocol for implementing this is entirely determined by the user.

1) Host Control SFR (HCON)
By writing to the Host Control SFR, the host can enable or disable FIFO interrupts and DMA requests and can
reset the UPI-452.
Symbolic
Address

HCON

Physical
Address

HC7

HCS

HC5

HC4

HC3

HC1

(MSB)
Status On Reset:
0

0

OE7H
(LSB)

0

0

10-175

0

O'

0

O'

intJ
HC7

HC6

HCS

HC4

HC3

HC2
HC1

UPI-452

Enabie Output FIFO Interrupt due to Underrun Error Condition, Data Stream Command or Service
Request
1 = Enable
0= Disable
Enable Input FIFO Interrupt due to Overrun Error Condition, or Service Request
1 = Enable
0= Disable
Enable the generation of the Interrupt due to Immediate Command Out being present
1 = Enable
0= Disable
Enable the Interrupt due to the Immediate Command In Register being Available for a new Immediate
Command byte
1 = Enable
o = Disable
Reset UPI-4S2
1 = Software RESET
o = Normal Operation
(reserved)"
Select between INTRQ and INTRQINIINTRQOUT as Request for.5ervice interrupt signal when DMA is
disabled
.
1 = INTRQ
INTRQIN or INTRQOUT
(reserved)"

o=
HCO

. NOTES:
'A '1' will be read from all SFR reserved locations except HCON SFR, HCO and HC2.
"'reserved'-these locations are reserved for future use by Intel Corporation.

2) Host Status SFR (HSTAT)
The Host Status SFR provides information on the FIFO-Host Interface and can be used to determine the
source of an external interrupt during polling. Like the Slave Status SFR, the Host Status SFR reflects the
current status of the FIFO-external host interface.
..
Symbolic

Physical

Address

Address

HSTAT

OE6H
Output FIFO Status -+
Status On Reset:
1/0'
(MSB)

(LSB)

10-176

infef

UPI-4S2

HST7 Output FIFO Underrun Error Condition
1 = No Underrun Error
o = Underrun Error (latched until Host
Status Register is read)
HST6 Immediate Command Out SFR Status
1 = Empty
o = Immediate Command Present
HST5 Data Stream Command/Data at Output
FIFO Status
1 = Data (not DSC)
o = DSC (present at Output FIFO COMMAND OUT SFR)
(Note: Only if HST4 = 0, if HST4 = 1 then undetermined)
HST4 Output FIFO Request for Service Status
1 = No Request for Service
o = Output FIFO Request for Service due to:
a. Output FIFO containing the threshold
number of bytes or more
b. Internal CPU sending a block of data terminated by a DSC (DSC Flush Mode)
HST3 Input FIFO Overrun Error Condition
1 = No Overrun Error
o = Overrun Error (latched until Host Status
Register is read)
HST2 Immediate Command In SFR Status
1 = Full (i.e. Internal CPU has not read previous Immediate Command sent by Host)
o = Empty

* Reset value;
'1' - if read by the external Host
'0' - if read by internal CPU (reads shadow
latch - see FIFO DMA Freeze Mode description)
HST1 FIFO DMA Freeze Mode Status
1 = Freeze Mode in progress.
(In Freeze Mode, the bits of the Host Status
SFR are forced to a '1' initially to prevent the
external Host from attempting to access the
FIFO. The definition of the Host Status SFR
bits during FIFO DMA Freeze Mode can be
found in FIFO DMA Freeze Mode description)
o = Normal Operation
HSTO Input FIFO Request Service Status
1 = Input FIFO does not request service
o = Input FIFO request service due to the
Input FIFO containing enough space for the
host to write the threshold number of bytes
or more

FIFO MODULE - EXTERNAL HOST
INTERFACE
Overview
The FIFO-external Host interface supports high
speed asynchronous bi-directional 8-bit data transfers. The host interface is fully compatible with Intel
microprocessor local busses and with MULTIBUS.
The FIFO has two specialized DMA request pins for
Input and Output FIFO channel DMA requests.
These are multiplexed to provide a dedicated Request for Service interrupt (DRQINIINTRQIN,
DRQOUT /INTRQOUT).
The external Host can program, under user defined
protocol, thresholds into the FIFO Input and Output
Threshold SFRs which determine when the FIFO
Request for Service interrupt is generated to the
Host CPU. The FIFO module external Host interface
is configured by the internal CPU via the MODE
SFR. "The external Host can enable and disable
Host interface interrupts via the Host Control SFR."
Data Stream Commands in the Input FIFO channel
allow the Host to influence the processing of data
blocks and are sent with the data flow to maintain
synchronization. Data Stream Commands in the
Output FIFO Channel allow the internal CPU to perform the same function, and also to set the Output
FIFO Request Service status logic to the host CPU
regardless of the programmed value in the Threshold SFR.

Slave Interface Address Decoding
The UPI-452 determines the desired Host function
through address decoding. The lower three bits of
the address as well as the READ, WRITE, Chip Select (CS) and DMA Acknowledge (DACK) are used
for decoding. Table 3 shows the pin states and the
Read or Write operations associated with each configuration.

Interrupts to the Host
The UPI-452 interrupts the external Host via the
INTRQ pin. In addition, the DRQIN and DRQOUT
pins can be multiplexed as interrupt request lines,
INTRQIN and INTRQOUT respectively, when DMA
is disabled. This provides two special FIFO "Request for Service" interrupts.
There are eight FIFO-related interrupt sources; two
from The Input FIFO; three from The Output FIFO;
one from the Immediate Command Out SFR; one
from the Immediate Command IN SFR; and one due
to FIFO DMA Freeze Mode.
INPUT FIFO: The Input FIFO interrupt is generated
whenever:
a. The Input FIFO contains space for a threshold
number of bytes.

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intJ

UPI·452

Table 3. UPI·452 Address Decoding
DACK CS A2 A1 AD

Write

Read

1

1

X

X

X No Operation

No Operation

1

0

0

0

0

Data or DMA from Output FIFO Channel

Data or DMA to Input FIFO Channel

1

0

0

0

1

Data Stream Command from Output FIFO Channel Data Stream Command to Input FIFO Channel

1

0

0

1

0

Host Status SFR Read

Reserved

1

0

0

1

1

Host Control SFR Read

Host Control SFR Write

1

0

1

0

0

Immediate Command SFR Read

Immediate Command to SFR Write

1

0

1

1

X Reserved

0

X

X

X

X DMA Data from Output FIFO Channel

DMA Data to Input FIFO Channel

1

0

1

0

1

Reserved

Reserved

Reserved

NOTES:
1. Attempting to read a DSC as a data byte will result in invalid data being read. The read pointers are not incremented so
that the DSC is not lost. Attempting to read a data byte as a DSC has the same result.
2. If DACK is active the UPI-452 will attempt a DMA operation when RD or WR becomes active regardless of the DMA
enable bit (MD6) in the MODE SFR. Care should be taken when using DACK. For proper operation, DACK must be driven
high (+5V) when not using DMA.

b. When an Input FIFO overrun error condition exists. The appropriate bits in the Host Status SFR
are set and the interrupt is generated only if enabled.
OUTPUT FIFO: The Output FIFO Request for S'ervjt"'o Intorr'l""t

..... ..., I I . "...... U .......

,,"t"\,...,+,...,..
...,t'vl~U.Q~

in ... ,..i ...... il,.. ........ _""" ......... _ ...

III CI .:Jlllllial

IllClr II 10'

Qo:t

+UIG
........

I_

111-

put FIFO interrupt:
a. When the FIFO contains the threshold number of
bytes or more.
b. Output FIFO error condition interrupts are generated when the Output FIFO is underrun.
c. Data Stream Command present in the Output
Buffer Latch.
'
A Data Stream Command interrupt is used to halt
normal processing, using the command as a vector
to a service routine. When DMA is disabled, the user
may program (through HC1) INTRa to include FIFO
Request for Service Interrupts or use INTRalN and
INTRaOUT as Request for Service Interrupts.'
,
IMMEDIATE COMMAND INTERRUPTS:
a. An Immediate Command Out Interrupt is generated, if enabled, to the Host and the corresponding
Host Status SFR bit (HSTAT HST6) is cleared,
when the internal CPU writes to the Immediate
Command OUT (IMOUT) SFR. When the Host
reads the Immediate Command OUT (IMOUT)
SFR the corresponding" bit in the Host Status
(HSTAT) SFR is set. This causes the Slav,e Status
Immediate Command OUT Status bit (SSTAT
SST6) to be cleared indicating that the Immediate
Command OUT (IMOUT) SFR is empty. If enabled, a FIFO-Slave Interface will also begenerated to the internal CPU. (See Figure 7b, Immediate Command OUT Flowchart.)

b. An Immediate Command IN interrupt is generated, if enabled, to the Host when the internal CPU
has read a byte from the Immediate Command IN
(IMIN) SFR. The read operation clears the Host
Status SFR Immediate Command IN Status bit
(HSTAT HST2) indicating that the' Immediate
Comrnand iN SFR is empty. The corresponding
Slave Status (SSTAT) SFR bit is also set to indicate an empty status. Setting the Slave Status
SFR bit generates a FIFO-Slave Interface interrupt, if enabled, to the internal CPU. (See Figure
7a, Immediate Command IN Flowchart.)
NOTE:
Immediate Command IN and OUT interrupts are actually specific Request For Service interrupts to the
Host.
FIFO DMA FREEZE MODE: When the internal CPU
invokes FIFO DMA Freeze Mode, for example at reset or to reconfigure the FIFO interface, INTRa is
activated. The INTRa can only be deactivated by
the external Host reading the Host Status SFR
(HST1 remains active until FIFO DMA Freeze Mode
is disabled by the internal CPU).
Once an interrupt is generated, INTRa will remain
high until no interrupt generating condition exists.
For a FIFO underrun/overrun error interrupt, the interrupt condition is deactivated by the external Host
reading the Host Status SFR. An interrupt is serviced by reading the Host Status SFR to determine
the source of the interrupt and vectoring the appropriate service routine.

10-178

UPI-4S2

DMA Requests to the Host
The UPI-452 generates two DMA requests, DRQIN
and DRQOUT, to facilitate data transfer between the
Host and the Input and Output FIFO channels. A
DMA acknowledge, DACK, is used as a chip select
and initiates a data transfer. The external READ and
WRITE signals select the Input and Output FIFO respectively. The CS and address lines can also be
used as a DMA acknowledge for processors with
onboard DMA controllers which do not generate a
DACK signal.
The internal CPU can configure the UPI-452 to request service from the external host via DMA or interrupts by programming Mode SFR MD6 bit. In addition the external Host enables DMA requests
through bits 6 and 7 of the Host Control SFR. When
a DMA request is invoked the number of bytes transferred to the Input FIFO is the total number of bytes
in the Input FIFO (as determined by the CBP SFR)
minus the value programmed in the Input FIFO
Threshold SFR. The DMA request line is activated
only when the Input FIFO has a threshold number of
bytes that can be transferred.

nation via the DMAO/DMA 1 Source Address or Destination Address Special Function Registers. The
FIFO module manages the transfer of data between
the external host and FIFO SFRs.

Internal CPU Access to FIFO Via
Software Instructions
The internal CPU has access to the Input and Output FIFOs via the FIFO IN/COMMAND IN and FIFO
OUT/COMMAND OUT SFRs which reside in the
Special Function Register Array. At the end of every
instruction that involves a read of the FIFO IN/COMMAND IN SFR, the SFR is written over by a new
byte from the Input FIFO channel when available. At
the end of every instruction that involves a write to
the FIFO OUT/COMMAND OUT SFR, the new byte
is written into the Output FIFO channel and the write
pointer is incremented after the write operation (post
incremented).
The internal CPU reads the Input FIFO by using the
FIFO IN/COMMAND IN SFR as the source register
in an instruction. Those instructions which read the
Input FIFO are listed below:

The Output FIFO DMA request is activated when a
DSC is written by the internal CPU at the end of a
less than threshold size block of data (Flush Mode)
or when the Output FIFO threshold is reached. The
request remains active until the Input FIFO becomes
full or the Output FIFO becomes empty. If a DSC is
encountered during an Output FIFO DMA transfer,
the DMA request is dropped until the DSC is read.
The DMA request will be reactivated after the DSC is
read and remains active until the Output FIFO becomes empty or another DSC is encountered.

ADD A,FIFO IN/COMMAND IN
AD DC A,FIFO IN/COMMAND IN
PUSH FIFO IN/COMMAND IN
ANL A,FIFO IN/COMMAND IN
ORL A,FIFO IN/COMMAND IN
XRL A,FIFO IN/COMMAND IN
CJNE A,FIFO IN/COMMAND IN, rei
SUBB A,FIFO IN/COMMAND IN
MOV direct,FIFO IN/COMMAND IN
MOV @Ri,FIFO IN/COMMAND IN
MOV Rn,FIFO IN/COMMAND IN
MOV A,FIFO IN/COMMAND IN

FIFO MODULE - INTERNAL CPU
INTERFACE

After each access to these registers, they are overwritten by a new byte from the FIFO.

Overview
The Input and Output FIFOs are accessed by the
internal CPU through direct addressing of the FIFO
IN/COMMAND IN and FIFO OUT/COMMAND OUT
Special Function Registers. All of the 80C51 instructions involving direct addressing may be used to access the FIFO's SFRs. The FIFO IN, COMMAND IN
and Immediate Command In SFRs are actually read
only registers, and their Output counterparts are
write only. Internal DMA transfers data between Internal memory, External Memory and the Special
Function Registers. The Special Function Registers
appear as another group of dedicated memory addresses and are programmed as the source or desti-

NOTE:

Instructions which use the FIFO IN or COMMAND
IN SFR as both a source and destination register
will have the data destroyed as the next data byte
is rewritten into the FIFO IN register at the end of
the instruction. These instructions are not supported by the UPI-452 FIFO. Data can only be read
through the FIFO IN SFR and DSCs through the
COMMAND IN SFR. Data read through the COMMAND IN SFR will be read as OFFH, and DSCs
read through the FIFO IN SFR will be read as
OFFH. The Immediate Command in SFR is read
with the same instructions as the FIFO IN and
COMMAND IN SFRs.

10-179

inter

UPI-4S2

The FIFO IN, COMMAND IN and Immediate Command In SFRs are read only registers. Any write operation performed on these registers will be ignored
and the FIFO pOinters will remain intact.

dress Register (DAR). (Note: Since the FIFO IN SFR
is a read only register, the DMA transfer will be ignored if it is used asa DMA DAR. This is also true if
the FIFO OUT SFR is used as a DMA SAR.)

The internal CPU uses the FIFO OUT SFR to write
to the Output FIFO and any instruction which uses
the FIFO OUT or COMMAND OUT SFR as a destination will invoke a FIFO write. DSCs are differentiated from data by writing to the COMMAND OUT
SFR. In the FIFO, Data Stream Commands have the
ninth bit assoCiated with the command byte set to
"1". The instructions used to write to the Output
FIFO are listed below:

Each DMA channel is software programmable to operate in either Block Mode or Demand Mode. In the
Block Mode, DMA transfers can be further .programmed to take place in Burst Mode or Alternate
Cycle mode. In Burst Mode, the processor halts its
execution and dedicates its resources to the DMA
transfer. In Alternate Cycle Mode, DMA cycles and
instruction cycles occur alternately.

MOV
MOV
. MOV
POP
MOV
MOV

FIFO
FIFO
FIFO
FIFO
FIFO
FIFO

OUT /COMMOUt, A
OUT/COMMOUT, direct
OUT /COMMOUT, Rn
OUT /COMMOUT
OUT/COMMOUT, #data
OUT/COMMOUNT, @Ri

NOTE:
Instructions which use the FIFO OUT/COMMAND
OUT SFRs as both a source and destination register cause invalid data to be written into the Output
'FIFO. These instructions are not supported by the
UPI-4S2 FIFO.

In Demand Mode, a DMA transfer occurs only when
it is demanded. Demands can be accepted from an
external device (through External Interrupt pins,
EXTO/EXT1) or from either the Serial Channel or
FIFO flags. In this way, a DMA transfer can be synchronized to an external device, the FIFO or the Serial Port. If the External Interrupt is configured in
Edge Mode, a single byte transfer occurs per transition. The external interrupt itself will occur if enabled. If the External Interrupt is configured in Level
Mode, DMA transfers continue until the External Interrupt request goes inactive or the byte count becomes zero. The following flags activate Demand
Mode transfers of one byte to/from the FIFO or Serial Channel:
RI - Serial Channel Receiver Buffer Full
TI - Serial Channel Transm!tter Buffer Empty

GENERAL PURPOSE DMA CHANNELS
Overview

Architecture

There are two identical General Purpose DMA Channels on the UPI-4S2 which allow high speed data
transfer from one writeable memory space to another. As many as 64K bytes can be transferred in a
single DMA operation. The following memory
spaces can be used with DMA channels:

There are three 16 bit and one 8 bit Special Function
Registers associated with each DMA channel.

• Internal Data Memory

• The 16 bit Source Address SFR (SAR) points to
the source byte.
• The 16 bit Destination Address SFR (DAR) points
to the destination.
• The 16 bit Byte Count SFR (BCR) contains the
number of bytes to be transferred and is decremented when a byte transfer is accomplished.

• External Data Memory
• Special Function Registers
The Special Function Register array appears as a
limited group of dedicated memory addresses. The
Special Function Registers may be used in DMA
transfer operations by specifying the SFR as the
sourCe or destination address. The Special Function
Registers which may be used in DMA transfers are
listed in Table 4. Table 4 also shows whether the
SFR may be used as Source or Destination only, or
.
.
both.
The FIFO can be accessed during DMA by using the
FIFO IN SFR as the DMA Source Address Register
(SAR) or the FIFO OUT SFR as the Destination Ad-

• The DMA Control SFR (DCON) is eight bits wide
and specifies the source memory space, destination memory space and the mode of operation.
In Auto Increment mode, the Source Address and/
or Destination Address is incremented when a byte
is transferred. When a DMA transfer is complete
(BCR = 0), the DONE bit is set and a maskable
interrupt is generated. The GO· bit must be set to
start any DMA transfer (also, the Slave Control SFR
FRZ bit must be set to disable FIFO DMA Freeze
Mode). The two DMA channels are deSignated as
DMAO and DMA 1, and their corresponding registers
are suffixed by 0 or 1; e.g. SARO, DAR 1, etc.

10-1BO

UPI-4S2

Table 4 DMA Accessible Special Function Registers
SFR

Symbol

Address

Accumulator
B Register
FIFO IN
COMMAND IN
FIFO OUT
COMMAND OUT
Serial Data Buffer
PortO
Port 1
Port 2
Port 3
Port 4

AlACC
B
FIN
CIN
FOUT
COUT
SBUF
PO
P1
P2
P3
P4

OEOH
OFOH
OEEH
OEFH
OFEH
OFFH
099H
080H
090H
OAOH
OBOH
OCOH

Source
Only

Destination
Only

Either

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

DMA Special Function Registers
DMA Control SFR: DCONO, DCON1
Symbolic
Address

Physical
Address

DCONO

092H

DCON1

093H
Reset Status: DCONO and DCON1 = OOH

Bit Definition:

DAS

IDA

0
0
1
1

0
1
0
1

SAS

ISA

0
0
1
1

0
1
0
1

DM

TM

0
0
1
1

0
1
0
1

Destination Address Space
External Data Memory without Auto-Increment
External Data Memory with Auto-Increment
Special Function Register
Internal Data Memory

Source Address Space
External Data Memory without Auto-Increment
External Data Memory with Auto-Increment
Special Function Register
Internal Data Memory

DMA Transfer Mode
Alten1ate-Cycle Transfer Mode
Burst Transfer Mode
FIFO or Serial Channel Demand Mode
External Demand Mode

10-181

intJ
DONE

UPI-452

DMA transfer Flag:

service request is generated. DMA transfer cycles
are alternated with instruction execution cycles.
DMA transfers are terminated as in FIFO Demand
Mode.

o .DMA transfer .is not completed.
DMA transfer is complete.

NOTE:
This flag is set when contents of the Byte Count
SFA decrements to zero. It is reset automatically
when the DMA vectors to its interrupt routine.
GO

Enable DMA Transfer:

o

Disable DMA transfer (in all modes).
Enable DMA transfer. If the DMA is in
the Block mode, start DMA transfer if
possible. If it is in the Demand mode,
enable the channel and wait for a demand.
.

NOTE:
The GO bit is reset when the BCA decrements to
zero.

DMA Transfer Modes
The following four modes of DMA operation are possible in the UPI-4S2.

1. ALTERNATE=CYCLE P.10CE

Output Channel
The DMA is configured as in FIFO Demand Mode
and transfers are initiated whenever an Output FIFO
requests service. DMA transfer cycles are alternated
with instruction execution cycles. DMA transfers are
terminated as in FIFO Demand Mode.
The FIFO logic resets the interrupt flag after transferring the byte, so the interrupt is never generated.
Once the DMA is programmed to service the FIFO,
the request for service interrupt for the FIFO is inhibited until the DMA is done (BCA = 0).
.

2. BURST MODE
In BUAST mode the DMA is initiated by setting the
GO bit in the DCON SFR. The DMA operation continues until BCA decrements to zero (zero byte
count), then an interrupt is generated (if enabled).
No interrupts are recognized during a DMA operation once started.

General

Input Channel

Alternate cycle mode is useful when CPU processing must occur during the DMA transfers. In this
mode, a DMA cycle and an instruction cycle occur
alternately. The interrupt request is generated (if enabled) at the end of the process; i.e. when BCA decrements to zero. The transfer is init