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Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
microcomputers. Whether used as microcontrol/ers in automobiles or microwave
ovens, or as personal computers or supercomputers, Intel's microcomputers
have always offered leading-edge technology. In the second half of the 1980s, Intel
architectures have held at least a 75% market share of microprocessors at 16 bits and above.
Intel continues to strive for the highest standards in memory, microcomputer components,
modules, and systems to give its customers the best possible competitive advantages.

EMBEDDED CONTROLLER
HANDBOOK

1988

Intel Corporation makes .no warranty. for .the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
herein.
'
.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH,
GENIUS, i, t, ICE, iCEL, iCS, iDBP, iDIS, 121CE, iLBX, im, iMDDX, iMMX,
Inboard, Insite, Intel, intel, intelBOS, Intel Certified, Intelevision,
inteligent Identifier, inteligent Programming, Inte"ec, Intellink, iOSP,
iPDS, iPSC, iRMK, iRMX, iSBC, iSBX, iSDM, iSXM, KEPROM, Library
Manager, MAP-NET, MCS, Megachassis, MICROMAINFRAME,
MULTIBUS, MULTICHANNEL, MULTIMODULE, MultiSERVER, ONCE,
OpenNET, OTP, PC-BUBBLE, Plug-A-Bubble, PROMPT, Promware,
QUEST, QueX, Quick-Pulse Programming, Ripplemode, RMX/80, RUPI,
Seamless, SLD, SugarCube, SupportNET, UPI, and VLSiCEL, and the
combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a
numerical suffix, 4-SITE.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered
trademark of Mohawk Data Sciences Corporation.
*MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature D.istribution
Mail Stop SC6-59
3065 Bowers Avenue
Santa Clara, CA 95051
@ INTEL CORPORATION 1987

Table of Contents
Alphanumeric Index .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii
xiii

8·BIT PRODUCTS
MCS®·48 FAMILY
Chapter 1
MCS®-48 Single Component System ........................................

1-1

Chapter 2
MCS®-48 Expanded System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

Chapter 3
MCS®-48 Instruction Set.. . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . .

3-1

Chapter 4
DATA SHEETS
8243 MCS®~48InputlOutput Expander. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .
P87 48H/P87 49H/8048AH/8035AH L/8049AH/8039AHLl8050AH/8040AHL
HMOS Single-Component 8-Bit Production Microcontroller ........ . . . . . . . . . . .
D8748H/8749H HMOS-E Single-Component 8-Bit Microcomputer. . . . . .. . .. . . . . .
MCS®-48 Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCS®-48 INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1
4-8
4-21
4-33
4-36

MCS®·51 FAMILY
Chapter 5
MCS®-51 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . .. . .. . .. . . . . .

5-1

Chapter 6
Hardware Description of the 8051,8052 and 80C51 ...........................

6-1

Chapter 7
Hardware Description of the 83C51 FA (83C252) ............................. ;

7-1

Chapter 8
Hardware Description of the 83C152 .................................. ; . . . . . .

8-1

Chapter 9
MCS®-51 Programmer's Guide and Instruction Set. .. . . . . .. . . . .. . . . . . . . . . . . . . .

9-1.

Chapter 10
DATA SHEETS
8031/8051 /8031AH/8051AH/8032AH/8052AH/8751 H/8751 H-8 8-Bit HMOS
and HMOS EPROM Microcontrollers.......................................
8051 AHP 8-Bit Control-Oriented Microcontroller with Protected ROM .. . . . . . . . . ..
8031 AH/8051AH/8032AH/8052AH/8751 H/8751 H~8 Express. . . . . . . . . . .. . . .. ..
8751 BH 8-Bit HMOS EPROM Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8032BH/8052BH 8-Bit HMOS Microcontrollers .............................. ;
8752BH 8-Bit HMOS EPROM Microcontroller.................................
80C31 BH/80C51 BH 8-Bit CHMOS Microcontrollers ...........................
80C31 BH/80C51 BH Express ................. : .............................
87C51 8-Bit CHMOS EPROM Microcontroller.................................
87C51 Express ...........................................................
87C51 FA (87C252) CHMOS Single-Chip 8-Bit Microcontroller . . . . . . . . . . . . . . . . . •.
83C152A180C152A Universal Communications Controller ....... '............ ; ..
80C152JAl83C152JAl80C152JB Universal Communications Controller .........
27C64/87C64 64K (8K x 8) CHMOS Production and UV Erasable PROMs ........
87C257 256K'(32K x 8) CHMOS UV Erasable PROM ..........................
UPITM-452 CHMOS Programmable I/O Processor .............................
APPLICATION NOTES
AP-70 Using the Intel MCS®-51 Boolean Processing Capabilities ................
AP-125 Designing Microcontroller Systems for Electrically Noisy Environments ....
AP-155 Oscillators for Microcontrollers .......................................
v

10-1
10-15
10-25
10-27
10-38
10-46
10-57
10-69
10-71
10-84
10-87
10-102
10-117
10-133
10-146
10-157
10-211
10-256
10-278

Table of Contents (Continued)
AP-252 Designing with the 80C51 BH ........................................ 10-310
AP-281 UPITM-452 Accelerates iAPX 286 Bus Performance ........•............ 10-334
ARTICLE REPRINTS
AR-409 Increased Functions in Chip Result in Lighter, Less Costly Portable
Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-354
AR-517 Using the 8051 Microcontroller with Resonant Transducers ............. 10-359
DEVELOPMENT SUPPORT TOOLS
8051 Software Packages. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . • . . . . 10-364
iDCX 51 Distributed Control Executive ....................................... 10-372
ICETM 5100/252 In-Circuit Emulator for the MCS@-51 Family ................... 10-380
MCS@-51 INDEX ................................................... ; ........ 10-390
80C152 INDEX .................................•............................ 10-392

THE RUPITM FAMILY
Chapter 11
The RUPITM-44 Family.....................................................

11-1

Chapter 12
8044 Architecture ........................................... , . . . . . . . . . . . . .

12-1

Chapter 13
8044 Serial Interface ......................................................

13-1

Chapter 14
8044 Application Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14-1

Chapter 15
DATA SHEET
8044AH/8344AH/8744H High Performance 8-Bit Microcontrollerwith On-Chip
15-1
Serial Communication Controller..........................................
APPLICATION NOTE
AP-283 Flexibility in Frame Size with the 8044. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-27
ARTICLE REPRINT
AR-307 Microcontroller with Integrated High Performance Communications
Interface .........................'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-57
.
DEVELOPMENT SUPPORT TOOLS
ICETM51 00/044 In-Circuit Emulator for the RUPITM-44 Family. . . . . . . . . . . . . . . . . .. 15-66

MCS®-80/85 FAMILY
. Chapter 16
DATA SHEETS
8080A/8080A-1 /80BOA-2 8-Bit N-Channel Microprocessor. . . . . . . . . . . . .. . . . . . . .
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . . . . . . . . . . . . . . . ..
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and
Timer. .. . . . . .. .. .. . . . .. . . .. .. . .. . . . . .. . . . .. . . . . . .. . . . .• . . . . . . . . . . .. ....
8185/8185-21024 x 8-Bit Static RAM for MCS@-85. ... . .. . . . .. . . . . .•. .. . .. ....
8224 Clock Generator and Driver for 8080A CPU ........... ~ ............. '. . . ..
8228 System Controller and Bus Driver for 8080A CPU. . . . . . . . . . . . . . . . . . . . . . . ..
8755A 16,384-Bit EPROM with I/O..........................................

16-1
16-11
16-31
16-45
16-50
16-55
16-59

16-BIT PRODUCTS
MCS®-96 FAMILY
Chapter 17
MCS@-96 Architectural Overview. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 18

17-1

,

MCS@-96InstructionSet...................................................

18-1

Chapter 19
MCS@-96 Hardware Design Information. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .

vi

19-1

Table of Contents (Continued)
Chapter 20
80C196KA Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20-1

Chapter 21
DATA SHEETS
809XBH/839XBH/879XBH with 8 or 16-Bit External Bus.......................
21-1
809XBH-10 Advanced 16-Bit Microcontroller with 8 or 16-Bit External Bus . . . . . . .. 21-44
809X-90, 839X-90 . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . .. 21-59
809XBH/839XBH/879XBH Express......................................... 21-78
809X-90, 839X-90 Express. . . . . . . . . . . . . . . . . . . .. . . .. .. .. . ... . . . . . . . . . . . . . . .. 21-87
80C196KA 16-Bit High Performance.CHMOS Microcontroller ................... 21-92
APPLICATION NOTES .
AP-248 Using the 8096 .................................................... 21-119
AP-275 An FFT Algorithm for MCS®-96 Products Including Supporting Routines
and Examples· .......................................................... 21-222
DEVELOPMENT SUPPORT TOOLS
MCS®-96 Software Development Packages .................................. 21-297
iDCX 96 Distributed Control Executive ....................................... 21-307
iSBE-96 Development Kit Single Board Emulator and Assembler for MCS®-96 .... 21-315
VLSICETM-96 In-Circuit Emulator for the MCS®-96 ............................. 21-323
ICETM-196 Real-Time Transparent 80C196 In-Circuit Emulator .................. 21-333
!'v1CS®-96 INDEX ............................................................ 21-335
80C196 INDEX ............................................................... 21-341

80186 FAMILY
Chapter 22
DATA SHEETS
80186 High Integration 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80C186 High Integration 16TBit Microprocessor . . . . . . . .. . . . . . . . . . . . . . . . . . . . . ..
80188 High Integration 16-Bit Microprocessor .................................
80C188 High Integration 16-Bit Microprocessor ...............................
82188 Integrated Bus Controller for 8086, 8088, 80186, 80188 Processors .......
APPLICATION NOTES
AP-186 Introduction to the 80186 Microprocessor .............................
AP-258 High Speed Numerics with the 80186,80188 and 8087 .................
AP-286 80186/188 Interface to Intel Microcontrollers ..........................
DEVELOPMENT SUPPORT TOOLS
8086/80186 Software Packages ............................................
VAXIVMS Resident 8086/8088/80186 Software Development Packages ........
8087 Support Library ......................................................
80287 Support Library .....................................................
iPAT Performance Analysis Tool ............................................
12 1CETM Integrated Instrumentation and In-Circuit Emulation System .............
ICETM-186 In-Circuit Emulator ..............................................

vii

22-1
22-53
22-111
22-165
22-225
22-241
22-316
22-332
22-362
22-383
22-391
22-395
22-399
22-412
22-424

Alphanumeric Index
27C64/87C64 64K (8K x 8) CHMOS Production and UV Erasable PROMs ............... 10-133
80C152JAl83C152JAl80C152JB Universal Communications Controller ............ , ... 10-117
80C186 High Integration 16-Bit Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 22-53
80C188 High Integration 16-Bit Microprocessor ...................................... 22-165
80C196KA Architectural Overview ................................................. 20-1
80C196KA 16-Bit High Performance CHMOS MiGrocontrolier . . . . . . . . . . . . . . . . . . . . . . . . .. 21-92
80C31 BH/80C51 BH Express ...................................................... 10-69
80C31 BH/80C51 BH 8-Bit CHMOS Microcontrollers . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. 10-57
22-1
80186 High Integration 16-Bit Microprocessor.......................................
80188 High Integration 16-Bit Microprocessor ....................................... 22-111
80287 Support Library ..................... '....................................... 22-395
8031/8051 /8031AH/8051AH/S032AH/8052AH/8751 H/8751 H-8 8-Bit HMOS and HMOS
1O~ 1
EPROM Microcontrollers ...................................... '. . . . . . . .. . . . . . . . . .
8031 AH/8051 AH/8032AH/8052AH/8751 H/8751 H-8 Express .... . . . . . . . . . . . . . . . . . . .. 10-25
8032BH/8052BH 8-Bit HMOS Microcontrollers ....................... : . . . . . . . . . . . . .. 10-38
8044 Application Examples ...................................... ,................
14-1
8044 Architecture. ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-1
8044 Serial Interface ............................ ~ . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-1
8044AH/8344AH/8744H High Performance 8-Bit Microcontroller with On-Chip Serial
Communication Controller ...................................................... 15-1
8051 Software Packages ............ '............................................. 10-364
8051 AHP 8-Bit Control-Oriented Microcontroller with Protected ROM. . . . . . . . . . . . . . . . . .. 10-15
8080Al8080A-1 /8080A-2 8-Bit N-Channel Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors. . . . . . . . . . . . . . . . . . . . . . . . .. 16-11
8086/80186 Software Packages .................................................. ; 22-362
8087 Support Library ................... '.......................................... 22-391
809X-90, 839X-90 ...................................... ;........................ 21-59
809X-90, 839X-90 Express ...... : ...... ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21-87
809XBH-10 Advanced 16-Bit Microcontroller with 8 or 16-Bit External Bus. . . . . . . .. . . . ... 21-44
809XBH/839XBH/879XBH with 8 or 16-Bit External Bus.............................. 21-1
809XBH/839XBH/879XBH Express ................................................ 21-78
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer.. 16-31
8185/8185-2 1024 x 8-Bit Static RAM for MCS®-85 ........ . . . . . . . . . . . . . . . . . . . . . . . . .. 16-45
82188 Integrated Bus Controller for 8086,8088,80186,80188 Processors .............. 22-225
8224 Clock Generator and Driver for 8080A CPU. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ... 16-50
8228 System Controller and Bus Driver for 8080A CPU ............................... 16-55
4-1
8243 MCS®-48 Input/Output Expander. .. . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .
83C152A180C152A Universal Communications Controller ............................ 10-102
87C257 256K (32K x 8) CHMOS UV Erasable PROM ................................. 10-146
87C51 Express .. ; .....................................................'. . ..... . . . .. 10-84
87C51 8-Bit CHMOS EPROM Microcontroller ..................................... ,.. 10-71
87C51 FA (87C252) CHMOS Single-Chip 8-Bit Microcontroller ......................... 10-87
8751 BH 8-Bit HMOS EPROM Microc~mtroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-27
8752BH 8-Bit HMOS EPROM Microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-46
8755A 16,384-Bit EPROM with I/O. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16-59
AP-275 An FFT Algorithm for MCS®-96 Products Including Supporting Routines and
Examples ...................... -......' ................................ '......... 21-222
AP-125 Designing Microcontroller Systems for Electrically Noisy Environments .......... 10-256
AP-155 Oscillators for Microcontrollers .......................................... , .. 10-278
AP-186 Introduction to the 80186 Microprocessor ................................... 22-241
AP-248 Using the 8096 ........................................................... 21-119
AP-252 Designing with the 80C51 BH ............................................... 10-310
AP-258 High Speed Numerics with the 80186, 80188 and 8087 ........................ 22-316
AP-281 UPITM-452 Accelerates iAPX 286 Bus Performance ........................... 10-334
viii

Alphanumeric Index (Continued)
AP-283 Flexibility in Frame Size with the 8044 ....................................... 15-27
AP-286 80186/188 Interface to Intel Microcontrollers ................................. 22-332
AP-70 Using the Intel MCS®"51 Boolean Processing Capabilities ....................... 10-211
AR-409 Increased Functions in Chip Result in Lighter, Less Costly Portable Computer .... 10-354
AR-307 Microcontroller with Integrated High Performance Communications Interface. . . .. 15-57
AR-517 Using the 8051 Microcontroller with Resonant Transducers .................... 10-359
D8748H/8749H HMOS-E Single-Component 8-Bit Microcomputer. . . . . . . . . . . . . . . . . . . . .
4-21
Hardware Description of the 8051, 8052 and 80C51 ..................................
6-1
Hardware Description of the 83C152 ...............................................
8-1
Hardware Description of the 83C51 FA (83C252) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
7-1
12 1CETM Integrated Instrumentation and In-Circuit Emulation System .................... 22-412
iDCX 51 Distributed Control Executive .............................................. 10-372
iDCX 96 Distributed Control Executive .............................................. 21-307
iPAT Performance Analysis Tool ................................................... 22-399
iSBE-96 Development Kit Single Board Emulator and Assembler for MCS®-96 ........... 21-315
ICETM 5100/252 In-Circuit Emulator for the MCS®-51 Family .......................... 10-380
ICETM-186 In-Circuit Emulator ..................................................... 22-424
ICErM-196 Real-Time Transparent 80C196 In-Circuit Emulator ......................... 21-333
ICETM51 001044 In-Circuit Emulator for the RUPITM-44 Family ......................... 15-66
MCS®-48 Expanded System ......................................................
2-1
MCS®-48 Express ........................ , ..... ,., .. , ........ , ............. ,.....
4-33
MCS®-48 Instruction Set",·,',.".,"", .. " .. " .. ,',.,",." .. ,',.".,.,',., ... ,.
3-1
MCS®-48 Single Component System .. , ........ , .. , .. , . , ... , ..... , , . , .. , , . . . . . . . . . .
1-1
MCS®-51 Architectural Overview"" ... " .. " .. ,' .. ",.,", ...... ,"',.,." .. ,.....
5-1
MCS®-96 Architectural Overview ., .. , ... " .. , .. , .... ,., .. "." .. " ... ,., .. "......
17-1
MCS®-96 Hardware Design Information",.", .. ,"",., ..... ".,", .. ".,., ... , •. ,'
19-1
MCS®-96 Instruction Set. .... , ... ,.,..............................................
18-1
MCS®-96 Software Development Packages, .... , ... , .... , ... , ... , ............ , ..... 21-297
P8748H/P87 49H/8048AH/8035AHL/8049AH/8039AHLl8050AH/8040AHL HMOS
Single-Component 8-Bit Production Microcontroller ,."', ... , ....... , ... ,, ...... ,..
4-8
The RUPITM-44 Family , .... , .. " ... ,.,"""""',.,',.,.,',.,"',.,', .. ".,"'"
11-1
UPITM-452 CHMOS Programmable I/O Processor .. , ......... , .. , , •.. , ... , ........ , .. 10-157
VAXIVMS Resident 8086/8088/80186 Software Development Packages, ........... , , . 22-383
VLSICETM-96 In-Circuit Emulator for the MCS®-96 " " " " " , .. , , .. , . , , , . , . , ..... , ... 21-323

ix

CUSTOMER SUPPORT
CUSTOMER SUPPORT
Customer Support is Intel's complete support service that provides Intel customers with hardware support, software
support, customer training, and consulting services. For more information contact your local sales offices.·
After a customer purchases any system hardware or software product, service and support become major factors in
determining whether that product will continue to meet a customer's expectations. Such support requires an international support organization and a breadth of programs to meet a variety of customer needs. As you might expect,
Intel's customer support is quite extensive. It includes factory repair services and worldwide field service offices
providing hardware repair services, software support services, customer training classes, and consulting services. .

HARDWARE SUPPORT SERVICES
Intel is committed to providing an international service support package through a wide variety of service offerings
available from Intel Hardware Support.

SOFrWARE SUPPORT SERVICES
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information
Phone Service), updates and subscription service (product-specific troubleshooting guides and COMMENTS Magazine). Basic support includes updates and the subscription service. Contracts are sold in environments which represent product groupings (i.e., iRMX environment).

CONSULTING SERVICES
Intel provideS field systems engineering services for any phase of your development or support effort. You can use
our systems engineers in a variety of ways ranging from assistance in using a new product, developing an application,
personalizing training, and customizing or tailoring an Intel product to providing technical and management consulting. Systems Engineers are well versed in technical areas such as microcommunications, real-time applications,
embedded microcontrollers, and network services. You know your application needs; we know our products. Workingtogether we can help you get a successful product to market in the least possible time.

CUSTOMER TRAINING
,
Intel offers a wide rimge of instructional programs covering various aspects of system design and implementation. In
just three to ten days a limited number of individuals learn more in a single workshop than in weeks of self-study.
For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we can take our
.workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course categories include:
architecture and assembly language, programming and operating systems, bitbus and LAN applications.

x

Preface

PREFACE
Computer systems can be characterized as being. "reprogrammable" or "embedded". Reprogrammable systems are those that look and behave like computers to
the ultimate user. An obvious example is the personal
computer. These systems contain some form of mass
storage device which stores a number o( different computer programs that the user may call up and use as
required. The input and output devices attached to
these systems are there to communicate with the user.
Embedded systems, as the name implies, are contained
within a final product which inay not look or feel like a
computer to the end user. An example here is a computer which controls the ubiquitous office copier machine. These systems rarely contain mass storage; the
programs are stored in ROM or EPROM devices. The
input and output devices attached are not limited to
communication with the user (e.g. the control panel);
they also monitor and control mechanisms and processes within the device (e.g. the paper feed mechanism).

data storage onboard. The maximum program size is
4 Kbytes.
.
MCS@-51: Designed for advanced 8-bit sequential control applications. These parts are similar to the
MCS@-48 family parts but operate from 2 to 5 times
faster and include more on-board peripherals. A unique
feature of the MCS@-51 family is a built in Boolean
processor which performs calculations on Boolean (one
bit) variables. The maximum program size is
64 Kbytes.
.
MCS@-96: Designed for advanced 16-bit closed loop
control applications. These parts include a processor
capable of high performance integer arithmetic and 232
bytes of general purpose registers which can be used for
byte, word, or double-word operands. A separate subsystem manages timer functions. Versions are available
with on-board A/D conversion and 8 Kbytes of onboard program memory. A unique feature of the newer
(BH) members of the family is dynamic bus sizing
which allows the parts to operate on both 8-bit and 16bit busses. The maximum program size is 64 Kbytes.

Embedded control applications can be broken into
three broad categories; sequential control, closed loop
control, and data control. Sequential control deals with
the control and monitoring of a system as a sequence of
events; activate the paper feed roller, wait for the paper
feed indicator then activate the drum mechanism.
Closed loop control involves closely monitoring the
output of process or device and altering its inputs to
achieve the desired output; if the feed roller motor is
turning too slowly or is decelerating then increase the
drive to the motor to compensate. These two categories
involve fixed programs that interface directly with the
,outside world. The data structures involved are normally small and simple. The third category of embedded
control (data control) still runs fixed programs but the
interface to the outside word becomes more indirect
and the data structures become larger and more complex. A high end copier might digitize an image and
then use image processing techniques to enhance contrast and then scale and rotate the image to fit the paper being used.

80186/80188: These parts are highly integrated versions of the 8086 microprocessor intended for data control applications. They combine 15 to 20 of the most
common 8086.system components onto one device. Included with the CPU is the clock generator, an interrupt controller; timers, DMA channels and chip. select
logic. The 80186 operates on a 16-bit bus and the 80188
operates on an 8-bit bus. Both parts operate on a 16-bit
bus internally.
.
.
Part of the motivation for combining all of these products into one handbook was the realization that,
although the categorization of embedded control applications into the three segments (sequential, closed loop,
and data control) is useful for conceptualizing application requirements, real applications of these parts
contain attributes from all three categories. Combining
these product lines into one handbook will make it easier for customers involved with embedded applications
to find the information they require.

Intel has consolidated four of its product families intended for embedded control applications into the Embedded Control Operation.

The remainder of this chapter will give a very brief
overview of each of the four products discussed. The
remainder of this book is intended to provide detailed
technical information on Intel's embedded control
product line.

MCS@-48: Designed for general purpose 8-bit sequential control applications. Versions of these parts are
available with program storage and up to 256 bytes of

xiii

intJ

PREFACE

MCS®-48 MICROCONTROLLERS

MCS®-S1 MICROCONTROLLERS

Intel's MCS-48 family of 8-bit microcontrollers has become a world standard and has been in production for
10 years. They are available in several versions: with on
board ROM, on board EPROM, or CPU only, to better
fit specific application needs. MCS-48 products are now
fabricated. on advanced HMOS processes offering higher performance and reliability with less power consumption.

Intel's MCS-5l family is the Industry standard for 8-bit
high performancemicrocontrollers. The -family architecture is optimized for sequential real-time control applications. They are available in several versions -with
on-board ROM, on-board EPROM, l!lld CPU only to
better -fit specific application needs. MCS-51- products
are available on adv~riced HMOS and CHMOS processes.

Features common to all members of this family are:
• 8-bit CPU with 1.36 microsecond instruction cycle

Features common to all members of this family are:
• 8-bit CPU optimized for control applications
• ,Extensive Boolean processing (single-bit logic) capabilities
• 32 bidirectional and individually addressable I/O
lines
-

•
•
•
•
•
•

27 I/O lines
8-bit bit timer/counter
2 interrupts
4 Kbyte maximum program size
256 byte maximum on-board RAM size
256 -byte maximum off-board RAM size

• Fuil-Duplex UART
• 5 source interrupt structure with 2 priority levels (6
sources on parts with 3 timer/counters)
• 64 Kbyte maximum program size
• 256 byte maximum on-board RAM size
• 64 Kbyte maximum off-board RAM size
• Po~er gown/Idle modes forCHMOS parts

Intel has over ten years of experience in manufacturing
both the EPROM and ROM versions of this chip. It
provides a low cost solution to applications such as keyboards, low end printers, and electronic carburator control.
Table 1. MCS®·48 Microcontrollers

Device
Name

ROMless
Version

EPROM
Version

ROM
Bytes

RAM
Bytes

8048AH

8035AHL

8748H

1K

_64

8049AH

8039AHL

8749H

2K

128

8050AH

8040AHL

-

4K

256

270253-1

Figure 1. MCS®·48 Block Diagram

xiv

inter

PREFACE

The MCS-51 family has found wide acceptance
throughout a wide range of applications, ranging from
those slightly more complex than a typical MCS-48 application through medical instrumentation and antiskid braking modules for automobiles.

capability. The 80C51FA contains, in addition to the
standard timer counters, a programmable counter array
(PCA) capable of measuring and generating pulse information on five I/O pins.

This year Intel added two new base products to the
MCS-51 family, the 80C152 and the 80C51FA. The
80C152 contains, in addition to a UART, a Global
Serial Channel capable of CSMA/CD and SDLC synchronous communication. It also has two DMA channels, the first member of the MCS-51 to have such

MSC®-51 FAMILY DEVELOPMENT
TOOLS
ICETM-5100 emulators give design engineers fullspeed, real-time, nonintrusive control over 8051 family
system debugging at clock speeds up to 16 MHz. Each

Table 2. Advanced 8-Bit Microcontrollers
Device
Name

ROMless
Version

EPROM
Version

ROM
Bytes

RAM
Bytes

16-Bit
Timers

Circuit
Type

B051

B031

(B751)

4K

12B

2

HMOS

B051AH

B031AH

B751H

4K

12B

2

HMOS

B052AH

B032AH

B752BH

BK

256

3

HMOS

4K

.128

2

CHMOS

BK

256

2

CHMOS

256

4

CHMOS

BOC51BH

BOC31BH

83C152

80C152

83C51FA

80C51FA

B7C51

87C51FA

8K

i -- -----.

,,
,,
,,
,,

,,,
,,
,,
,

EXTERNAL
INTERRUPTS

,-------.

8K ROM
IN 8052 ;--_ • • • • • ,

,,

4K
ROM

TIMER 2

'

I

'

'

256 RAM
IN 8052

:~:::)1 ,~- --]

P2

Pl

COUNTER
INPUTS'

TXD
PO

I

RXD

P3

ADDRESS/DATA
270253-2

Figure 2. Block Diagram of the 8051/8052AH

intJ

PREFACE

Features common to all members of this family are:

emulator lets the user view and modify system activity
at a symbolic, high-level language' level, speeding and
simplifying the development and debug phases of microcontroller system design, All of the ICE-5100 emulators can be hosted on IBM PC Ars or compatibles,
or Intellec® Series III/IV development systems. Three
versions of ICE-5tOO are available today. ICE-5100252 supports HMOS and CHMOS versions of the following components: 8031, 8051, 8751, 8032, 8052,
8752, 80C31, 80C51, 87C51, 83C51FA, 80C51FA, and
87C51FA. ICE-5100/452 supports: 80C452, 83C452,
87C452. The ICE 5100/044 supports: 8344, 8044, 8744,
and BITBUSTM components.

• 16-bit timer (Timerl)
• 16-bit counter (Timer2)
• Full-Duplex UART with independent baud-rate
generator
• Watchdog timer
• 8-bit resolution Pulse Width Modulator (PWM)
• 48 I/O lines (33 for 48-pin parts)
'. HSIO unit
The HSIO (High Speed Input/Output) unit is an independent timer subsystem which manages Timer1 and
Timer2 for the programmer. Events (e.g. setting an I/O
pin) can be scheduled to occur automatically when either of the two timers reaches a preset value. External
events can be recorded in a FIFO along with the value
of Timerl when the event occurred. The HSIO is connected to eight pins on the 8096 and can generate and
monitor events with a 2 microsecond resolution (12
MHz crystal).

Available for the 51 family, ASM-51 and PL/M-51
both contain a relocation and linkage utility and are
available for the IBM PC and Intel Microcomputer Development Systems running either iNDX or ISIS operating systems.
This complete, integrated design-in solution for the
MCS-51 family of microcontrollers speeds product development, and improves design team productivity.

In addition to an EPROM version, the 8X9XBH offer
several improvements over the non BH parts:
• Dynamic selection of 8-/16-bit bus operation (versus
fixed 16-bit bus)

MCS®-96 MICROCONTROLLERS
The MCS-96 Family of microcontrollers was designed
for applications which combine high performance 16bit fixed-point arithmetic with an immediate interface
to real world devices and events. The architecture is
based on a single 64 Kbyte address space. In addition to
. being accessable as memory, the first 256 bytes of this
space are also' directly addressable as registers. These
locations are on-chip for high performance and can be
treated as byte, word, or double-word, operands by the
programme!'. Twenty-four bytes of these registers are
used to control the on-board peripherals; the remaining
232 bytes are usuable by the programmer as general
purpose registers. The combination of a register file, onboard I/O, and a high performance 16-bit CPU .makes
the MCS-96 family well matched to closed loop control
applications.

• Programmable READY logic
• Sample and Hold input to the AID converter
During 1987 Intel added a new series to the MCS-96
family, the 80C196KA. This part is implemented on a
high performance CMOS process and offers significantly more performance and reduced power levels. The
design also includes many detail improvements while
sti11 retaining compatibility with the NMOS versions of
the MCS-96 family.
The MCS-96 family is being used now in a wide variety
of complex control tasks such as robotics, motor con-

Table 3 Advanced i6-Bit Microcontrollers
Device
Name

ROMless
Version

EPROM
Version

ROM
Bytes

RAM
Bytes

I/O
Pins

A/D
Channels

8395

8095

232

29

4

8096

-

8K

8396

8K

232

48

8397

8097 .

-

8K

232

40

8

8395BH

8095BH

8795BH

8K

232

29

4

8396BH

8096BH

8796BH

8K

232

48

8397BH

8097BH

8797BH

8K

232

40

8

83C196KB

80C196KA

87C196KB

8K

232

48

8

• AT is a registered trademark of IBM Corporation.

xvi

intJ

PREFACE

VREF ANGND

POWER
DOWN

-t

FREQUENCY
REFERENCE

m___ __ m
~

CLOCK
GEN

8

Uu:_~- Uj
ROM OR EPROM I
(OPTIONAL):

....."T"--r...... :
I
I

PORTO PORT 1

PORT 2
ALT FUNCTIONS

CONTROL
SIGNALS

HSI HSO

270253-3

'Sample and Hold is only present on BX9XBH devices.

Figure 3. MCS®-96 Block Diagram
trol, hard disk mechanisms, printers, modems, automotive engine control and high performance anti-skid
braking applications.

cations. Six of the most often used functions of an 8086
system have been integrated ---4S

~-,~,

-------4 S.

EN TCNTI
EXECUTED

DIS TCNT!' --lr"'\~~--I
EXECUTED
R

Q

INTERRUPT
IN
'.
PROGRESS'
FF

R

TIMER
INT
ENABLE

Q

RESET

INTcr-------4 D
PIN
RESET

INT
FF

RETR
EXECUTED

CLK

·ALE.~~r-~___~:::]

,

~~~~;;CLE._-t._'
ENI
----Is
EXECUTED

DISI

EXECUTED--l~~_-I R .
RESET

INT
ENABLE

1. WHEN INTERRUPT IN PROGRESS FLIP-FLOP IS SET
ALL FURTHER INTERRUPTS ARE LOCKED OUT
INDEPENDENT OF STATE OF EITHER INTERRUPT
ENABLE FLIP-FLOP.
2. WH!LE TI~ER INTERRUPTS ARE DISABLED TIMER
OVERFLOW III WILL NOT STORE ANY OVERFLOW
'THAT OCCURS. TIMER FLAG WILL BE SET, HOWEVER ..

Figure 8. Interrupt Logic

1-8

SINGLE COMPONENT MCS®-48 SYSTEM

PRESCALER

XTAL + 15 -

+32
LOAD OR READ

I

CLEARED ON START TIMER

r------..... START
EDGE
DETECTOR

COUNTER

JUMP ON
TIMER FLAG

8BITTIMERI
EVENT COUNTER

o

OVERFLOW
FLAG

STOPT

ENABLE--------~___ '

INT

Figure 9. Timer/Event Counter

location 3. Since the timer interrupt is latched it will remain pending until the external device is serviced and
immediately be recognized upon return from the service
routine. The pending timer interrupt is reset by the Call
to location 7 or may be removed by executing a DIS
TCNT! instruction.

olution less than I count an external clock can be applied
to. the TI input and the counter operated in the event
counter'mode. ALE divided by 3 or more can serve as
this external clock. Very small delays or "fine tuning"
of larger delays can be easily accomplished. by software
delay loops.
.

AS AN EVENT COUNTER

Often a serial link is desirabl~ ill an MCSA8 family mem~
ber..Thble 2 lists the timer counts and cycles needed
for a specific baud rate given a crystal frequency.

Execution of a START CNT instruction connects the T!
input pin to the counter input and enables the counter.
The T! input is sampled at the beginning of state 3 or in
later MCS-48 devices in state time 4. Subsequent high to
low transitions on TI will cause the counter to increment.
T! must be held low for at least I machine cycle to insure
it won't be missed. The maximum rate at which the
counter may be incremented is once per three instruction
cycles (every 5.7 f.Lsec when using an 8 MHz crystal)-there is no minimum frequency. TI input must remain
high for at least 1/5 machine cycle after each transition.
AS A TIMER

Eexcution of a START T instruction connects an internal
clock to the counter input and enables the counter. The
internal clock is derived bypassing the basic machine cycle
clock through a + 32 prescaler. The prescaler is reset
during the START T instruction. The resulting clock increments the counter every 32 machine cycles. Various
delays from I to 256 counts can be obtained by presetting
the counter and detecting overflow. Times longer than 256
counts may be achieved by accumulating multiple overflows in a register under software control. For time res1-9

2.11 Clock

and Timing Circuits

Timing generation for the 8048AH is completely selfcontained with the exeception of a frequency reference which
can be XTAL, ceramic resonator, or external clock source.
The Clock and Timing circuitry can be divided into the
following functional blocks.
OSCILLATOR

The on-board oscillator is a high' gain piiU'aUel resonant
circuit with a frequency range of I to 11 MHz .. The XI
external pin is the input to the amplifier stage \:yhile X2
is the output. A crystal or ceramic resonator connected
between XI and X2 provides the feedback and phase shift
required for oscillation. If an accurate frequency reference
is not required, ceramic resonator may be used in place
of the crystal.
.
For accurate clocking, a crystal should be used. An externally generated clock may also be applied to XI-X2
as the frequency source. See the data sheet for more
infermation.

SINGLE COMPONENT MCS®-48 SYSTEM

Table 2. Baud Rate Generation

Baud
Rate

Frequency
(MHz)

Tey

TO Prr(1/5 Tey)

Timer Presealer
(32 Tey)

4
6
8
11

3.751LS
2.501LS
1.881LS
1.361LS

750ns
500ns
375ns
275ns

120ILS
801LS
60.21LS
43.51LS

4 MHz
Timer Counts +
Instr. Cycles

6 MHz
Timer Counts +
Instr. Cycles

8 MHz
Timer Counts +
Instr. Cycles

11 MHz
Timer Counts +
Instr. Cycles

151 + 3 Cycles
.01% Error

208 + 28 Cycles
.01% Error

110

75

+ 24 Cycles
.01% Error

113 + 20 Cycles
.01% Error

300

27

+ 24 Cycles
.1% Error

41

+ 21 Cycles
.03% Error

55

+ 13 Cycles
.01% Error

1200

6

+

30 Cycles
.1% Error

10

+ 13 Cycles
.1% Error

12

+ 27 Cycles
.06% Error

19 + 4 Cycles
.12% Error

1800

4

+

20 Cycles
.1% Error

6

+

30 Cycles
.1% Error

9

+ 7 Cycles
;17% Error

12

+ 24 Cycles
.12% Error

2400

3

+

15 Cycles
.1% Error

5

+ 6 Cycles
.4% Error

6

+ 24 Cycles
.29% Error

9

+ 18 Cycles
.12% Error

4800

1

+ 23 Cycles
1.0% Error

2

+

3

+ 14 Cycles
.74% Error

4

+ 25 Cycles
.12% Error

19 Cycles
.4% Error

STATE COUNTER

76

+ 18 Cycles
.04% Error

power supply is within tolerance. Only 5 machine cycles
(6.8 !J.S @ 11 MHz) are required if power is already on
and the oscillator has stabilized. ALE and PSEN (if EA
= 1) are active while in Reset.

The output of the oscillator is divided by 3 in the State
Counter to create a clock which defines the state times of
the machine (CLK). CLK can be made available on the
external pin TO by executing an ENTO CLK instruction.
The output of CLK on TO is disabled by Reset of the
processor.

Reset performs -the following functions:
1) Sets program counter to zero.

CYCLE COUNTER

2) Sets stack pointer to zero.

CLK is then divided by 5. in the Cycle Counter to provide a clock which defines a machine cycle consisting
of 5 machine states as sho",on in Figure 10. Figure 11
shows the different internal operations as divided into
the machine states. This clock is called Address Latch
Enable (ALE) because of its function in MCS-48. systems with external memory. It is provided continuouslyon the ALE output pin.

3) Selects register bank O.

4) Selects memory bank O.
·5) Sets BUS to high impedance state (except when
EA = 5V).

6) Sets Ports 1 and 2 to input mode.

2.12 Reset

7) Disables interrupts (timer and external).

The reset input provides a means for initialization for the
processor. This Schmitt-trigger input has an internal pullup device which in combination with an external 1 !J. fd
capacitor provides an internal reset pulse of sufficient
length to guarantee all circuitry is reset, as shown in Figure
12. If the reset pulse is generated externally the RESET
pin must be held low for at least 10 milliseconds after the

8) Stops timer.
9) Clears timer flag.
10) Clears FO and Fl.
11) Disables clock output from TO.
1-10

SINGLE COMPONENT MCS®-48 SYSTEM

JUMP ON
TEST = 1 OR 0
XTAL2 . - - - - - . ,
+3
11
STATE
MHzCJ
COUNTER
XTAL 1 L..._ _ _ _..I

.273

~sec

(3.67 MHz)

DIAGRAM OF 8048AH CLOCK UTILITIES

.
55

1.36
51

~sec

52

53

INPUT DECODE
I NST.

I

54

55

51

EXECUTION

INPUT

OUTPUT
ADDRESS

INC. PC

I

~

I

.

CYCLE

I

I

INSTRUCTION CYCLE
(1 BYTE, 2 CYCLE INSTRUCTION ONLY)
PREVIOUS CYCLE-"'~'f-o.
__- - - 1 S T CYCLE----I.......,....
_ - - - 2 N D CYCLE----l...
~1
STATE TIME:
52

I

53

I

54

I

55

I

51

I

52

I

53

I

54

55

I

51

55

I

51

I

52

(02)"TO

~~--------~~----------~~--------

ALE
PSEN' - _ _ _ __,

RD,WR _ _ _ _ _ _ _ _ _ _ _ _ _

~

_ _ _ _ __,

'-------'I

PROG - - - - - - - - - - - - - - - - - - ,
'EXTERNAL MODE
"IF ENABLED

8048AH/8049AH TIMING

Figure 10. MCS®-48 Timing Generation and Cycle Timing

2.13 Single-Step
This feature,· as pictured in Figure 13, provides the
user with a debug capability in that the processor can be
stepped through the program one instruction at a time.
While stopped, the address of the next instruction to be
fetched is available concurrently on BUS and the lower

1-11

half of Port 2. The user can therefore follow the program
through each of the instruction steps. A timing diagram,
showing the interaction between output ALE and input
SS, is shown. The BUS buffer contents are lost during
single step; however, a latch may be added to reestablish
the lost I/O capability if needed. Data is valid at the leading
edge of ALE.

CYCLE 1
INSTRUCTION

I£i
c
iiJ

~

-

-

OUTPUT
TO PORT

-

INCREMENT
PROGRAM COUNTER

'OUTPUT
TO PORT
'OlirPUT
TO PORT

INCReMENT
FETCH
INSTRUCTION PROGRAM COUNTER

-

OUTL P,A

FETCH
INCRleMENT
INSTRUCTION PROGRAM COUNTER

ORL P,= DATA

INCReMENT
FETCH
INSTRUCTION PROGRAM COUNTER

INSA,BUS

FETCH
INCReMENT
INSTRUCTION PROGRAM COUNTER

'INCREMENT
TIMER

READ PORT

FETCH
IMMEDIATE DATA

-

INCREMENT
PROGRAM COUNTER

INCREMENT
TIMER

-

-

READ
PORT

INCREMENT
TIMER

OUTPUT
TO PORT

-

-

-

'INCREMENT
TIMER

READ PORT

FETCH
IMMEDIATE. DATA

-

INCREMENT
PROGRAM COUNTER

'OUTPUT
TO PORT

-

'INCREMENT
TIMER

READ PORT

FETCH
IMMEDIATE DATA

-

INCREMENT
PROGRAM COUNTER

'OUTPUT
TO PORT

READ
DATA

-

-

ORL BUS, = DATA

INCREMENT
FETCH
INSTRUCTION PROGRA'. COUNTER

MOVX@R,A

FETCH
INCREMENT
INSTRUCTION PROGRAII COUNTER

OUTPUT RAM
ADDRESS

INCREMENT
TIMER

OUTPUT·
DATA TO RAM

MOVXA,@R

FETCH
INCREMENT
INSTRUCTION PROGRAII COUNTER

OUTPUT RAM
ADDRESS

INCREMENT
TIMER

-

MOVDA,PI

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

-

MOVDPI,A

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

OUTPUT DATA
TOP2LOWER

ANLDP,A

INCREMENT
FETCH
INSTRUCTION PROGRAM COU·NTER

OUTPUT
OPCODE/ADDRESS

INCREMENT
TIMER

OUTPUT
DATA

ORLDP,A

FETCH
INCR:EMENT
INSTRUCTION PROGRAM COUNTER

OUTPUT
OPCODEIADDRESS

INCREMENT
TIMER

. OUTPUT
DATA

SAMPLE
CONDITION

'INCREMENT
SAMPLE

-

..

5'
!!I.
c

-....
n
0"

:::s

3"

5'

ICI

C

iii"

ICI

iii
:I

INCR:EMENT
FETCH
J(CONDITIONAL)
INSTRUCTION PROGRAM COUNTER
STRTT
STRTCNT

FETCH
INCFIEMENT
INSTRUCTION PROGRAM COUNTER

STOP TCNT

FETCH
INCFIEMENT
INSTRUCTION PROGRAM COUNTER

ENI

FETCH
INCFIEMENT
INSTRUCTION PROGRA'M COUNTER

DISI

INCFlEMENT
FETCH
INSTRUCTION PROGRAM COUNTER

ENTOCLK

FETCH
INCIIEMENT
INSTRUCTION PROGRAM COUNTER

·

-

L- ___

-

START
COUNTER

-

• ENABLE
INTERRUPT

-

• DISABLE.
INTERRUPT

-

·

------

-

READ PORT

• ENABLE
CLOCK

FETCH
IMMEDIATE DATA

READP2
LOWER

-

-

UPDATE
PROGRAM COUNTER

·
..

-

-

·······

-

-

-

-

STOP
COUNTER

·VALID INSTRUCTION ADDRESSES ARE OUTPUT
AT THIS TIME IF EXTERNAL PROGRAM MEMORY IS
BEING ACCESSED.
(1) IN LATER MC5-48 DEVICES T1 IS SAMPLED IN S4.

-

!

-

'INCREMENT
TIMER

-

%

-

FETCH
IMMEDIATE DATA

INCREMENT
FETCH
INSTRUCTION PROGRAM COUNTER

~

-

-

'INCREMENT
TIMER

ANL BUS, = DATA

...

··-

-

FETCH
INCRIEMENT
INSTRUCTION PROGRAM COUNTER

CD

~
%
CD
0

55

READ
PORT

OUTL BUS, A

...

54

S3

'INCREMENT
TIMER

...:-"
0

....

54

S2

INA,P

"II

S3

S1

FETCH
INCREMENT
INSTRUCTION PROGRAM COUNTER

ANLP,=DATA

CYCLE 2

~)2

S5

S1

UI

Z

C)

rm

I

o
o

i:
"U

oZ

m
Z
-t
i:

tl
@

.~

~

m
i:

SINGLE COMPONENT MCS®-4B SYSTEM

clear input. ALE should be buffered since the clear input
of an SN7474 is the equivalent of 3 TTL loads. The
processor is now in the stopped state. The next instruction
is initiated by clocki!!g a "1" into the flip-flop. This "1"
will not appear on SS unless ALE is high removing clear
from the flip-flop. In response to SS going high the processor be~s an instruction fetch which brings ALE low
resetting SS through the clear input and causing the processor to again enter the stopped state.

EXTERNAL RESET

Vcc

ACTIVE
PULLUP

2.14 Power Down Mode
(B048AH, B049AH, 8050AH,
B039AHL, 8035AHL, B040AHL)

POWER ON RESET

Extra circuitry has been added to the 8048AHl8049AHI
8050AH ROM version to allow power to be removed from
all but the data RAM array for low power standby oper~
ation. In the power down mode the contents of data RAM
can be maintained while drawing typically 10% to 15%
of normal operating power requirements.

.J:L 1K

f

Vee serves as the 5V supply pin for the bulk of circuitry
while the VDD pin supplies only the RAM array. In normal
operation both pins are a 5V while in standby, Vee is at
ground and VDD is maintained at its standby value. Applying Reset to the processor through the RESET pin
inhibits any access to the RAM by the processor and
guarantees that RAM cannot be inadvertently altered as
power is removed from Vcc.

Figure 12.

TIMING
The 8048AH operates in a single-step mode as follows:
I) The processor is requested to stop by applying a low
level on SS.

A typical power down sequence (Figure 14) occurs as
follows:

2) The processor responds by stopping during the address
fetch portion of the next instruction. -If a double cycle
instruction is in' progress when the single step command is received, both cycles will be completed before
stopping.

1) Imminent power supply failure is detected by user defined circuitry. Signal must be early enough to allow
8048AH to save all necessary data before Vee falls
below normal operating limits.

3) The proc~ssor acknowledges it has entered the stopped
state by raising ALE high. In this state (which can be
maintained indefinitely) the address of the next instruction to be fetched is present on BUS and the lower
half of port 2.
4) ss is then raised high to bring the processor out of the
stopped mode allowing it to fetch the next instruction.
The exit from stop is indicated by the processor bringing ALE low.

2) Power fail signal is used to interrupt processor and
vector it to a power fail service routine.
3) Power fail routine saves all important data and machine
status in the internal data RAM array. Routine may
also initiate transfer of backup supply to the VDD pin
and indicate to external circuitry that power fail routine
is complete.

5) To stop the processor at the next instruction SS must
be brought low again soon after ALE goes low. If SS
is left high the processor remains in a "Run" mode,

4) Reset is applied to. guarantee data will not be altered
as the power supply falls out of limits. Reset must be
held low until Vee is at ground level.

A. diagram for implementing the single-step function of
the 8748H is shown in Figure 13. D.:!}'pe flip-flop with
preset and clear is used to generate SS. In the run mode
SS is held high by keeping the flip-flop preset (preset has
precedence over the clear input). To enter single step,
preset is removed allowing ALE to bring SS low via the

Recovery from the Power Down mode can occur as any
other power-on sequence with an external capacitor on
the Reset input providing the necessary delay. See the
previous section on Reset.

1-13

SINGLE COMPONENT MCS®-48 SYSTEM

+5V

SINGLE

+5V

MOMENTARY
PUSHBUTTON

10K

~u~PN--~-----------'

10K

PRESET
+5V

D

Q

+5V
,..--------(> CLOCK

10K

DEBOUNCE
LATCH
1/27400
ALE
SINGLE STEP CIRCUIT

1

S3

1

54

1

S5

I

S1

1

S2

1 S3

1 • •

·IS3154IS51

1 S2

1

ALE~

n

SS

BUS

P2D-23

PCD-7

1/0

: :

PC 8-11

S

:

SINGLE STEP TIMING

Figure 13. Single Step Operation

1·14

C
1/0

SINGLE COMPONENT MCS®-48 SYSTEM

reset the prescaler and time state generators. TO may then
be brought down with the rising edge of Xl. Two clock
cycles later, with the rising edge of X I, the device enters
into Time State 1, Phase 1, SS' is then brought down to
5 volts 4 clocks later after TO. RESET' is allowed to go
high 5 tCY (75 clocks) later for nonnal execution of code.
See Figure 15.

POWER~
SUPPLY

PROCESSOR;

INTE~RUPTED I

"--:

POWER ~
I
I
SUPPLY
·_ _ _' _ _ I_ _ _
FAIL SIGNAL
I
I
I
I
I
RESET

NORMAL
POWERON
SEQUENCE
FOLLOWS

LJ ___ _

:
i

DATA SAVE
ROUTINE
EXECUTED

i

ACCESS TO
DATA RAM
INHIBITED

Figure 14. Power Down Sequence

2.15 External Access Mode
Nonnally the first IK (8048AH), 2K (8049AH), or 4K
(8050AH) words of program memory are automatically
fetched from internal ROM or EPROM. The EA input pin
however allows the user to effectively disable internal
program memory by forcing all program memory fetches
to reference external memory. The following chapter explains how access to external program memory is
accomplished.
The External Access mode is very useful in system test
and debug because it allows the user to disable his internal
applications program and substitute an external program
of his choice - a diagnostic routine for instance. In ad- .
dition, the date sheet shows how internal program memory can be read externally, independent of the processor:
A "1" level on EA initiates the external accesss mode.
For proper operation, Reset should be applied while the
EA input is changed.

2.16 Sync Mode
The 8048AH, 8049AH, 8050AH has incorporated a new
SYNC mode. The Sync mode is provided to ease the
design of mUltiple controller circuits by allowing the designer to force the device into known phase and state time.
The SYNC mode may also be utilized by automatic test
equipment (ATE) for quick, easy, and efficient synchronizing between the tester and the OUT (device under test).
SYNC mode is enabled when SS' pin is raised to high
voltage level of + 12 volts. To begin synchronization, TO
is raised to 5 volts at least four clocks cycles after SS'.
TO must be high for at least four X I clock cycles to fully

1-15

SINGLE COMPONENT MCS®-48 SYSTEM

X1

PHASE 1- -

-

-

-

-- -

-

--"'-:""

PHASE 2- -

-

-

-

-

-

-

-

-

-

-

-

TIME STATE
SS

2

3

4

1~~----.J
OV
5V

TO

OV--------------------~

5V
5V

ALE

RESET

OV--------------------------------------------------~

OV--------------------------------------------~------~---------------

SYNC MODE TIMING

Figure 15. Sync Mode Timing

3.0 PIN DESCRIPTION

8

PORT
#1

8

PORT
#2

The MCS-48 processors are packaged iii 40 pin Dual InLine Packages (DIP's). Thble 3 is a summary of the
functions of each pin. Figure 16 is the logic symbol
for the 8048AH product family. Where it exists, the second paragraph describes each pin's function in an expanded MCS-48 system. Unless ·otherwise specified, each
input is TIL compatible and each output will drive one
standard TIL load.
.

RESET
SINGLE STEP
EXTERNAL
MEM
TEST {
INTERRUPT
BUS

8

B048AH
B049AH
BOSOAH

READ
WRITE
PROGRAM
STORE ENABLE
ADDRESS
LATCH ENABLE

Figure 16. 8048AH and 8049AH Logic Symbol

1-16

SINGLE COMPONENT MCS®-48 SYSTEM

Table 3. Pin Description
Designation

Pin
Number*

Function

Vss

20

Circuit OND potential

VDD

26

Programming power supply; 2lV during program for the 8748H/8749H; + 5V during
operation for both ROM and EPROM. Low power standby pin in 8048AH and
8049AH/8050AH ROM versions.

Vee

40

Main power supply; +5V during operation and during 8748H and 8749H programming.

PROG

25

Program pulse; + 18V input pin during 8748H /8749H programming. Output strobe
for 8243 I/O expander.

PIO-PI7
(Port I)

27-34

8-bit quasi-bidirection,aI port. (Inte~nal Pullup= 50KH)

P20-P27
(Port 2)

21-24
35-38

8-bit quasi-bidirectional port. (Internal Pullup = 50KH)
P20-P23 contain the four high order program counter bits during an external program memory fetch and serve as a 4-bit I/O expander bus for 8243.

DO-D7
(BUS)

12-19

True bidirectional port which can be, written or read synchronously using the RD.
WR strobes. The port can also be statically latched.
Contains the 810w 'order program counter bits during an external program memory fetch. and receives the addressed instruction under the control of PSEN. Also
, contains the address and data during, an external RAM data store instruction.
, under ,control of ALE, RD, and WR.

TO

I

Input pin testable using the conditional transfer instructions JTO and JNTO. TO
can be designated as a clock output using ENTO CLK instruction. TO is also used
during programming and sync mode.

TI

39

Input pin testable using the JT I, and JNTI 'instructions. Can be design~ted the
event counter input using the STRT CNT instruction., (See Section 2.10).

IN'f

6

Interrupt input. Initiates an in'terrupt' if interrupt is enabled. Interrupt is disabled
after a reset. (Active low)

-RD

8

Output strobe activated during a BUS read. Can be used to enable data onto the
BUS from an external device. (Active low)

Interrupt must remain low for at least 3 machine cycles to ensure proper operation.

Used as a Read Strobe to External Data Memory.
RESET

4

Input which is used, to initialize the processor. Also used during EPROM programming
and verification. (Active low) (Internal pullup =80K fi)

WR

10

Output strobe during a BUS write. (Active low) Used llS write strobe to external
data memory.

ALE

II

Address 'Latch Enable. This signal occurs once during each cycle and is useful as
a clock output.
The negative edge of A LE strobes address into external data and program memory.

1-17

SINGLE COMPONENT MCS®-48 SYSTEM'

lllble 3. 'Pin Description (Continued)
Designation

Pin
Number·

PSEN

9

SS

5

EA

7

Function
Program Store Enable. This output 'occurs only during a fetch to external program
memory. (A~tive low)
Single step input cari be used i~ c~njunction with ALE to "single step" the processor
through each instruCiion. (Active low) (Internal imllup 300Kn) +12V for sync
modes (See 2.16).

=

External Access input which forces all program memory fetches to reference external memory. Useful for emulation and debug; and essential for testing and program verification. (Active high) +12V for8048AH/8049AH/8050AH program
xerification and +18V for 8748H/8749H program verification (Internal pullup
IOMn on 8048AH/8049AH/8035AHL/8039AHL/8050AH/8040AHL)

=

XTALI

2

XTAL2

3

, One side of cryst~1 input for internal oscillator. Also input for external source.
Other side of crystal/external source input.

;

'Unless otherwise stated, inputs dO,not have internal pullup resistors. 8048AH, 8748H, 8049AH, 8050AH, 8040AHL

4.0 PROGRAMMING, VERIFYING AND
'ERASING EPROM

8748H AND 8749H ERASURE
,,CHARACTERISTICS

The internal Pmliram Memory of the 8748H and the
8749H may be erased and reprogrammed by the user as
explained in the following sections. See also the 8748H
and 8749H data sheets.

The erasure characteristics of the 8748H and 8749H are
such that erasure begl.ns'to occur when exposed to light
with wavelengths shorter than approximately 4000 Angs"
troms (A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data show that constant exposure to
level fluorescent: lighting could erase the typical
8748H'and 8749H in approximately 3 years while it would
take approxima1l1ly I week to cause erasure when exposed
to direct sunlight. If the 8748H or 8749H is to be exposed
to these types, of lighting conditions for extended periods
of time,' opaque labels should be placed over the 8748H

4.1 ProgrammlngNerlflcatlon

room

In brief, the programming process consists of: activating
the program mode, applying an address, latching the address, applying data, and applying a programming pulse.
This programming algorithm applies to both the 8748H
and 8749H. Each word is programmed completely before
mOv1-!!g on to the next and is followed by a verificatiQn
step. The following is a list of the pins used for program~
ming and a descsription of their functions:

Pin
XTAL 1
Reset
Test 0

EA
BUS
P20-1
P20-2
Voo
PROG
PIO-Pll

windo,: to prevent unintentional erasure.
When erased, bits of the 8748H and 8749H Program Memory are in the logic "0" state.

Function
Clock Input (3 to 4 MHz)
,
Initialization and Address Latching
Selection of Program (OV) or Verify
'
(5V) Mode
Activation of Program/Verify Modes
Address and Data Input Data' Output
During Verify
Address Input for 8748H
Address Input for 8749H
Programming Power Supply
Program Pulse Input
Tied to ground (8749H only)

,The 'recommended erasure procedure for the 8748H and
8749H is exposure to shortwave ultraviolet light which
has a wavelength of 2537 Angstroms (A). The integrated
dose (i.e., UV intensitY X exposure time) for erasure
should be, a minimum of 15W-sec/cm2 • The erasure time
with this dosage is approximately IS to 20 minutes'using
an ultraviolet lamp with a 12000p'w/cm2 power rating.
The 8748H ,and 8749H should be placed within one inch
from the lamp tubes during erasure. Some lamps have a
filter in their tubes ,and this filter should be removed before
erasure.

1·18

SINGLE COMPONENT MCS-48 SYSTEM

COMBINATION PROGRAMIVERIFY MODE (EPROM. ONLY)

lav

/

EA 5V _ _ _ _- J

I--------PROGRAM--------!---VERIFY---!-----PROGRAMITW-TO

tww-----,--RESET
tAW+---t-~+- tWA
~

DBO-DB7

r-~D~AT~A~T~O~BE~~

--F - -

P20-P22

PROGRAMMED VALID

LAST
ADDRESS

NEXT
ADDRESS
tVDDWffttvD?H
_
WT

+21
vDD

+5--------------

PROG+:: ____________

------------------------------

~:£V____\tt~W:

__

-- - - - - - =--,.:-"'. . _---

+0

, VERIFY MODE (ROM/EPROM)
EA

*TO,
RESET

DBO-DB7

_-oJ/
~'-____________---.JI

J--

P20-P22

\ . . . ._ _---JI

__ -<

ADDRESS
(0-7) VALID

NEXT

X

~,__.;..A;;;;D.;;;D.;..R.;;;E,;;,SS;;......J.

ADDRESS (8-10) VALID

I\IEXT DATA)- __ _
. OUT VALID.

NEXT ADDRESS VALID

NOTES:
1. PROG MUST FLOAT IF EA IS LOW (I.E., "" leV).

"TO ON EPROM ONLY.

Figure 17. Pl'9gramlVerify Sequence for 8749H18748H

1·19

MCS®,.48 Expanded System

2

EXPANDED MCS®-48 SYSTEM
1'.0 INTRODUCTION

1) The contents of the 12-bit program counter will be
output on BUS and the lower half of port 2.
2) Address Latch Enable (ALE) will indicate the time at
which address is valid. The' trailing edge of ALE is
used to latch the address externally.
3) Program Store Enable (PSEN) indicates that an external instruction fetch is in progress and serves to enable
the external memory device.
4) BUS reverts to input (floating) mode and the processor
accepts its 8-bit contents as im instruction word.

If the capabilities resident on the single-chip S04SAHI

S74SH/S035AHUS049AH/S749H/S039AHL are not sufficieflt for your system requirements, special on-board circuitry allows the addition of a wide variety of external
memory, 110, or special peripherals you may require. The
processors can be directly and simply expanded in the
foilowing areas:
• Program Memory to 4K words
• Data Memory to 320 words (3S4 words with
S049AH)
• 110' by unlimited amount
• Special Functions uSingSOSO/SOS5AH peripherals

ALE

By using bank switching techniques, maximum capability
is essentially unlimited. Bank switching is discussed later
in the chapter. Expansion is accomplished in two ways:
1) Expander 110 - A special 110 Expander circuit, the
S243 , provides for the addition of four 4-bit Input!
Output ports with the sacrifice of only the lower half
(4-bits) of port 2 for inter-device communication. Multiple S243's may be added to this 4-bit bus by generating the required .. chip select" lines.
2) Standard SOS5 Bus - One port of the S04SAHI
S049AH is like the S-bit bidirectional data bus of the
: SOS5 microcomputer system allowing interface to the
numerous standard memories and peripherals of the
MCS@-SO/S5 microcomputer family.

L

PSEN
FLOATING
BUS

~FLOATINGO FLOATING
ADDRESS

INSTRUCTION

Figure 1. Instruction Fetch from
External Program Memory
All inStruction fetches, including internal addresses, caD. be
forced to be external by activating the EA pin of the 8048AH1
8049AH18050AH. The 8035AHU8039AHUS04OAHL processors without program memory always operate in the external program memory mode (EA = 5V).

MCS-4S systems can be configured using either or both
of these expansion features to optimize system capabilities
to the application.

2.2 Extended. Program Memory
AddreSSing (Beyond 21<)

Both expander devices and standard memories and peripherals can be added in virtually any number and combmation required.
,

J

For programs of 2K words or less, the 8048AH/8049AH
addresses program memory in the conventional manner.
Addresses beyond 2047 can be reached by executing a
program memory bank switch instruction (SEL MBO, SEL
MBI) followed by a branch instruction (JMP or CALL).
The bank switch feature extends the range of branch instructions beyond their normal 2K range and at the same
time prevents the user from inadvertently crossing the 2K
boundary ..

.

'. 2.0 EXPANSION OF PROGRAM MEMORY
Program Memory is expanded beyond the resident IK or
2K words by using the SOS5 BUS feature of the MCS@48. All program memory fetches from the addresses less
. than 1024 on the S04SAH and less than 204S on the
. S049AH occur internally with no external signals being
generated (except ALE which is always present). At address 1024 on the S04SAH, the processor automatically
initiates external program memory fetches.

PROGRAM MEMORY BANK SWITCH

The switching of 2K program memory banks is accomplished by directly setting or resetting the most significant
bit 'of the program counter (bit 11); see Figure 2. Bit
II is not altered by nQrmal incrementing of the program
counter but is loaded with the contents of a special flipflop each time a JMP or CALL instruction is executed.
This special flip-flop is set by executing an SEL MBI

2.1 Instruction Fetch Cycle (External)
As shown in Figure 1, for all insinicti~n fetches from
addresses of 1024 (2048) or greater, the following will
occur:

2-1

EXPANDED MCS®-48 SYSTEM

instruction and reset by SEL MBO. Therefore, the SEL
MB instruction may be executed at any time prior to the
actiJal bank switch which occurs during the next branch
instruction encountered. Since all twelve bits of the program counter; including bit 11, are stored in the. stack,
when a Call is executed, the user may jump·to subroutines
across the 2K boundary and the proper bank will be restored upon return. However, the bank switch flip-flop
will not' be altered on return.

counter is held at "0" during the interrupt service routine.
The end of the service routine is signalled by the execution
of an RETR instruction. Interrupt service routines should
therefore be contained entirely in the lower 2K words of
program memory. The execution of a SEL MBO or SEL
MB I instruction within an interrupt routine is nOt recommended since it will not alter PCII while in the routine,
but will change the internal flip-flop~

2.3 Restoring 110 Port Information
,Although the lower half of Port 2 is u~ to output the
four most significant bits of address during an external
program memory fetch, the 110 information is still ootputed during certain portions of each machine cycle. 110
information is always present on Port 2's lower 4 bits at
the rising edge of ALE and can be sampled or latched at
this time.

IAnIAwl~I~I~I~I~I~I~I~I~I~1
Conventional pr~gram Counter
'

C

• Counts OOOH to 7FFH
• Overflows 7FFH to OOOH
JMP or CALL Instructions transfer contents
ofinternallllpflop.to A11
• Flipflop set by SEL MB1
• Flipflop reset by SEL MBO
or by RESET

2.4, Expansion Examples

During interrupt service routine
A11 i. forced to "0"
All 12 bits are saved in stack

Shown in Figure 3 is the addition· of 2K words of
program memory using an 2716A 2K x 8 ROM to give
a total of 3K words of program mem0!I:...!!!.'this case no
chip select decoding is required and PSEN enables the
memory directly through the chip select input. If the system requires only 2K of progra!ll memory, the same configuration can be used with an 803SAHL substituted for
the. S04SAH. The 8049AH would provide 4K of program
memory with the same configuration.

Figure 2. Program Counter
INTERRUPT ROUTINES
. Interrupts always vector the program counter tO'location
3 or 7 iii 'the first 2K bank, 'and bit II of the program

3

II

~.,
8048AH

ALE

,irV

A

,74LS373
LATCH

"
n)

ADDRESS

v

2718
EPROM
DATA
OUT

BUS r'--8
PSEN

CiS

.'

USING 2K

x

8 EPROM

Figure 3. Expa~ding MCSC!l~48 Program Memory Using Standard Memory Products

2-2

EXPANDED MCS®-48 SYSTEM

Figure 4 shows how the 8755/8355 EPROM/ROM with

lio interfaces directly to the 8048AH without the need
for an address latch. The 8755/8355 contains an internal
8-bit address latch eliminating the need for an 8212 latch.
In addition to a 2K x 8 program memory. the 8755/8355
also contains 16 110 lines addres.sable as two 8-bit ports.
These ports are addressed as external RAM; therefore the
RD and WR outputs of the 8048AH are required. See the
following section on data memory expansion for more
detail. The subsequent section on 110 expansion explains
the operation of the 16 I/O lines .

ALE

RD
lOW
lOR

8048AH
8049AH

AlDO_7

2K x 8
ROMI
EPROM
WITH

1/0

8~~1
8755

.A8-Al0. CS

3.0 EXPANSION OF DATA MEMORY
Data Memory is expanded beyond the resident 64 words
by using the 8085AH type bus feature of the MCS®-48.

3

TEST
INPUTS

3.1 Read/Write Cycle

1/0

All address and data is transferred over the 8 lines of
BUS. As shown in Figure 5, a read or write cycle
occurs as follows:

Figure 4. External Program Memory Interface

ALE

J.

L
I

BUS

FLOATING XADDRESSX

7' ~___FL_O_A_TI_N_G_ __

FLOATING

READ FROM EXTERNAL DATA MEMORY

ALE

J

L
I

BUS

FLOATING

FLOATING

WRITE TO EXTERNAL DATA MEMORY

Figure 5. External Data Memory Timings

2-3

EXPANDED MCS®-48 SYSTEM

I) The contents of register RO or RI is outputed on BUS.

4.0 EXPANSION OF INPUT/OUTPUT

2) Address Latch Enable (ALE) indicates addre.sss is
valid. The· trailing edge of ALE is used to latch the
address externally.
3) A read (RD) or write (WR) pulse on the corresponding
output pms of the 8048AH indicates the type of data
memory access ~gress. Output data is valid at the
trailing edge of WR and input data must be valid at
the trailing edge of RD;

There are four possible modes of II() expansion with the
8048AH: one using a special low-cost expander, the 8243;
another using standard MCS~80/85110 devices; and a third
using the combination memory 110 expander devices the
8155, 8355, and 8755. It is also possible to expand using
standard TTL devices.

·4.1 I/O Expander Device

4) Oat (8 bits) is transferred in or out over BUS.

3.2 Addressing External Data Memory
ExternBI Data Memory is accessed with its own two-cycle
move instructions. MOVXA, @R and MOVX@R, A,
which transfer 8 bits of data between the accumulator and
the external memory location addressed by the. contents
of one of the RAM Pointer Registers RO and RI. This
allows 256 locations to be addressed in addition to the
resident locations. Additional pages may be added by'
"bank switching" with extra output lines of the 8048AH.

The most efficient means of 110 expansion for small systems is the 8243 110 Expander Device which requires only
4 port lines (lower half of Port 2) for communication with
the 8048AH. The 8243 contains four 4-bit 110 ports which
serve as an extension of the on-chip 110 and are addressed
. as ports #4-7 (see Figure 13-7). The following operations
may be performed on these ports:
• Transfer Accumulator to Port
• Transfer Port to Accumulator·
• AND Accumulator to Port

3.3 Examples of Data Memory Expansion

• OR Accumulator to Port
Figure 6 shows how the 8048-AH can be expanded
using the 8155 memory and 110 expanding device. Since
the 8155 has an internal8-bit address latch, it can interface
directly to the 8048AH without the use of an external
latch. The 8155 provides an additional 256 words ofstatic
data memory and also includes 22 110 lines and a 14-bit
timer. See the following section on 110 expansion and the
8155 data sheet for more details on these additional
features.

A 4-bit transfer from a port to the lower half of the Accumulator sets the most significant four bits to zero. All
communication between the 8048AH and the 8243 occurs
over Port 2 lower (P20-P23) with timing provided by an
output pulse on the PROG pin of the processor. Each transfer consists of two 4-bit nibbles: The first containing the
"op code'.'and port address, and t\le second containing
the actual 4 bits of data ..

Busk'------;;8,-----~
ADO_7
v
ALE

8048AH

"

WR

ALE 8155
256x8
ViR RAM

AD

iii>

PORT

3

TEST
INPUTS

18

1/0

22

1/0
TIMER IN
TIMER OUT

101M

Figure 6. 8048AH Interface to 256 x8 Standard Memories

··2-4

EXPANDED MCS®-48 SYSTEM

fl
-=~I/O
"

CHIP SELECT CONNECTIO NIFMORE
THAN ONE EXPANDER IS USED

CS
P4

V

4

1/0
or

PROG

PROG

A

2

8050AH
8049AH
8048AH

P5

J i::JTS

"

4

1/0
v

8243

t-.
"-

4.

P20-P23

v

"

P6

4

P7

4

v

DATA IN
P2

1/0

1/0
v

EXPANDER INTERFACE

PROG

P20-P23

\

BITS 0, 1

' - . _ _ _- - I/

--<'-___X'-_____),..---

BITS 2, 3

OO}

00}
01
PORT
01
10
ADDRESS 10
11
11

READ
WRITE
OR
AND

DATA (4-BITS)

ADDRESS
ANDOPCODE
(4-BITS)

OUTPUT EXPANDER TIMING

Figure 7. 8243 Expander I/O Interface

3

Nibble I
2 I 0

3

I I I I IA IA I
Instruction
Code

4.2 1/0 Expansion with Standard
Peripherals

Nibble 2
2 I 0

I did IdId I
Port
Address

Standard MCS-80/85 type 110 devices may be added to
the MCSIII>-48 usinl!; the same bus and timinl!; used for Data
Memory expansion. Figure 8 shows an example of how
an 8048AH can be connected to an MCS-85 peripheral.
110 devices reside on the Data Memory bus and in the
data memory address space and are accessed with the same
MOVX instructions. (See the previous section on data
memory expansion for a description of timing.) The following are a few 9f the Standard MCS-80 devices which
are very useful in MCSIII>-48 systems:
• 8214 Priority Interrupt Encoder
• 8251 Serial Communications Interface
• 8255 General Purpose Programmable 110
• 8279 Keyboard/Display In~erface
• 8254 Interval Timer

data

II

AA

00 Read
01 Write
10 OR
II AND

00 - Port #4
01 - Port #5
10- Port #6
II-Port#7

A high to low transition of the PROG line indicates that
address is present, while allow to high transition indicates
the presence of data. Additional 8243's may be added to
the four-bit bus and chip selected using additional output
lines from the 8048AH/8748H.
1/0 PORT CHARACTERISTICS

4.3 Combination Memory and
110 Expanders

Each of the four4-bit ports of the 8243 can serve as either
input or output and can provide high drive capability in
both the high and low state.

As mentioned in the sections on program and data memory
expansion, the 8355/8755 and 8155 expanders also contain
I/O capability;

2-5

EXPANDED MCS®-48 SYSTEM

8
INT

INT

P20

c/o
8279
KEYBOARD
DISPLAY

8048AH
RD

RD

WR

WR

BUS

8

KEYBOARD
INPUTS

SCAN
OUTPUTS
(A) DISPLAY
OUTPUT

DATA
BUS

Cs

(B) DISPLAY
OUTPUT

Figure 8. Keyboard/Display Interface
port. These three registers and aControllStatus register
are accessible as external data memory with the MOVX
instructions. The contents of the control register determines the mode of the three ports. The ports can be programmed as input or output with or without associated
handshake communication lines. In the handshake mode,
lines of the six-bit port become input and output strobes
for the two 8-bit ports. Also included in the 8155 is a
14-bit programmable timer. The clock input to the timer
and the timer overflow output are available on external
pins. The timer can be programmed to stop on tenninal
count or to continuously reload itself. A square wave or
pulse output on terminal count can also be specified.

8355/8755: These two parts of ROM and EPROM equivalents and therefore contain the same 110 structure. 110
eonsists of two 8-bit ports which nonnally reside in the
external data memory address space and are accessed with
MOVX instructions. Associated with each port is an 8"it Data Direction Register which defines each bit in the
port as either an input or an output. The data direction
registers are directly addressable, thereby allowing the'
user to define under software control each individual bit
of the ports as either input or output. All outputs. are
statiCally latched and double buffered. Inputs
not
latched.
8155/8156: 110 on the 815518156 is configured 'as two
8-bit programmable 1/0 ports and one 6-bit programmable

are

Figure 9. Low Cost 110 Expansion

2-6

EXPANDED MCS®-48 SYSTEM

1/0 EXPANSION EXAMPLES

Figure 10 shows the 8048AH interface to a standard
MCS®-80 peripheral; in this case, the 8255 Programmable
Peripheral Interface, a 40-pin part which provides three
8-bit programmable I/O ports. The 8255 bus interface is
typical of programmable MCS®-80 peripherals with an
8-bit bidirectional data bus, a RD and WR input for Read/
Write control, a CS (chip select) input used to enable the
Read/Write control logic and the address inputs used to
select various internal registers.

Figure 9 shows the expansion of 110 using multiple
8243's. The only difference from a single 8243 system is
the addition of chip selects provided by additional8048AH
output lines: Two output liens and a decoder could also
be used to address the four chips. Large numbers of 8243' s
would require a chip select decoder chip such as the 8205
to save I/O pins.

8048AH ALE
RO

AD
8255
A1 PROGRAMMABLE
PERIPHERAL
INTERFACE

PORT
A

P20
P21

PORT
B

8048AH _
RO

PORT
C

WR
BUS

Ao

8255
A1 PROGRAMMABLE
PERIPHERAL
INTERFACE
RO

Wii
8

PORT
B
PORT
C

00-7

CS
OPTION #1

PORT
A

CS

-=

OPTION #2

-=

Figure 10. Interface to MCS®-BO Peripherals
Interconnection to the 8048AH is very straightforward
with BUS, RD, and WR connecting directly to the corresponding pins on the 8255. The only design consideration is the way in which the internal registers of the 8255
are to be addressed. If the registers are to be addressed
as external data memory using the MOVX instructions,
the appropriate number of address bits (in this case, 2)
must be latched on BUS using ALE as described in the
section on external data memories. If only a single device
is connected to BUS, the 8255 may be continuously selected by grounding CS. If multiple 8255's are used, additional address bits can be latched and used as chip'
selects.

addressing of the various memories and 110 ports. Note
that in this configuration address lines A 10 and A 11 have
been ORed to chip select the 8355. This ensures that the
chip is active for all external program memory fetches in
the lK to 3K range and is disabled for all other addresses.
This gating has been added to allow the 110 port of the
8355 to be used. If the chip was left selected all the time,
there would be conflict between these ports and the RAM
and I/O of the 8156. The NOR gate could be eliminated
and Al1 connected directly to the CE (instead of CE) input
ofthe 8355; however, this would create a lK word "hole"
in the program memory by causing the 8355 to be active
in the 2K and 4K range instead of the normal lK to 3K
range.

A second addressing method eliminates external latches
and chip select decoders by using output port lines as address and chip select lines dircctly.r'his method. of
course, requires the setting oran output port with address
information prior to executing a MOVX instruction.

In this system the various locations are addressed as
follows:'
• Data RAM - Addresses 0 to 255 when Port 2 Bit
o has been previously set = 1 and Bit I' set = 0
Addresses 0 to 3 when Port 2 Bit 0 =
1 and Bit 1 = 1

• RAM 110 -

5.0 MULTI-CHIP MCS®-48 SYSTEMS

• ROM I/O Bit 3 = 1

Figure 11 shows the addition of two memory expanders
to the 8048AH, one 8355/8755 ROM and one 8156 RAM.
The mirin consideration in designing such a system is the

Addresses 0 to 3 when Port 2 Bit 2 or

See the memory map in Figure 12.

2-7

EXPANDED MCS®-48 SYSTEM

8156/8355
A8-10

PORT
83551

8755
ROM
EPROM

ALE
PSEN
8048AH RD
WR

BUS

8

PORT

ADO-7
101M

-=PORT
A

8

8156
RAM
A9

101M

PORT
B
PORT

c

Figure 11. The Three-Component MCS®-48 System

6.0 MEMORY BANK SWITCHING

Jumping to subroutines across the boundary should be
avoided when possible since the programmer must keep
track of which bank to return to after completion of the
subroutine. If these subroutines are to be nested and accessed from either bank, a software "stack" should be
implemented to save the bank switch bit just as if it were
another bit of the program counter.

Certain systems may require more than the 4K words of
program memory which are directly addressable by the
program counter or more than the 256 data memory and
110 locations directly addressable by the pointer registers
RO and Rl. These systems can be achieved using "bank
switching" techniques. Bank switching is merely the selection of vari()US blocks of "banks" of memory using
dedicated output port lines from the processor. In the case
of the 8048AH, program memory is selected in blocks of
4K words at a time, while data memory and 110 are en. abled 256 words at a time.

From a hardware standpoint bank switching is very
straightforward and involves only the connection of an
110 line or lines as bank enable signals. These enables are
ANDed with normal memory and 110 chip select signals
to activate the proper bank.

The most important consideration in implementing two or
more banks is the software required to cross the bank
boundaries. Each crossing of the boundary requires that
the processor first write a control bit to an output port
before accessing memory or 110 in the new bank. If program memory is being switched, programs should be organized to keep boundary crossings to a minimum.

7.0 CONTROL SIGNAL SUMMARY
Table 1 summarizes the instructions which activate the
various control outputs of the MCS®-48 processors. During all other' instructions these outputs are driven to the
active state.

2-8

EXPANDED MCS®·48 SYSTEM

Table 1. MCS®-48 Control Signals
Control
Signal
RD
WR
ALE
PSEN
PROG

The latched mode (INS, OUTL) is intended for use in the
single-chip configuration where BUS is not begin used as
an expander port. OUTL and MOVX instructions can be
mixed if necessary. However, a previously latched output
will be· destroyed by executing a MOVX instruction and
BUS will be left in the high impedance state. INS does
not put the BUS in a high impedance state. Therefore,
the use of MOVX after OUTL to put the BUS in a high
impedance state is necessary before an INS instruction
intended to read an external word (as opposed to the previously latched value).

When Active
During MOVX, A, @R or INs Bus
During MOVX @R, A or OUTL Bus
Every Machine Cycle
During Fetch of external program memory (instruction or immediate data)
During MOVD, A,P ANLD P,A MOVD
P,AORLDP,A

OUTL should· never be used in a system with external
program memory, since latching BUS can cause the next
instruction, if external, to be fetched improperly.

8.0 PORT CHARACTERISTICS

8.1 BUS Port Operations·

8.2 Port 2 Operations

The BUS port can operate in three different modes: as a
latched 110 port, as a bidirectional bus port, or as a program memory address output when external memory is
used. The BUS port lines are either active high, active
low, or high impedance (floating).

The lower half of Port 2 can be used in three different
ways: as a quasi-bidirectional static port, as an 8243 expander port, and to adddress external program memory.

PROGRAM MEMORY
SPACE
.-----'BFFH
I

I

:

MB1

I

8355
(2K)

:

I

I

I
I

I
:
MBO I - - - - - j 400H

EXTERNAL DATA
MEMORY SPACE

I
I

I ~~5
I

- - - - - - - - 300H
8155
RESIDENT
I
I 10
RESIDENT DATA
--(1K)-- 200H I -______---i
MEMORY
- - - - - - - - 100H ~--'-"":""-!
(64)
' - - - - - - ' OOOH 1--:-------1
SECTION
PROG.MEM
DATAMEM
8155 PORTS

8355 PORTS

ADDRESS

DESIGNATION

OOO-BFF
100-IFF
300
301
302
303
304
305
400
401
402
403

CMD/STATUS
PORTA
PORTB
PORTC
TIMER LOW
TIMER HI
PORTA
PORTB
DORA
DDR B

Figure 12. Memory Map for Three-Component MCS®-48 Family

2-9

EXPANDED MCSIiil-48 SYSTEM

viously latched will be automatically removed temporarily
'while address is present, then retored when the fetch is
complete. However, if lower Port 2 is used to communicate with ,iIIi 8243, previously latched 110 information
, will be removed and not restored. After
input from th~
8243~ P20-3 will be left in the input mode (ftoating).After
an output to the 8243, P20-3 will contain the value written,
AN~, or ORed' to the 8243 port.

In all c,ases' outputs are driven low by an active device
and,driven high momentarily by a low impedance device
and held high bY a high impedan~ device to vee.

an

The port may contain latched 110 data prjor to its use in
another mode without affecting operation of either:, If
lower, ,Port 2 (P20-3) is IIsed ,to output address for an
external program memory fetch. the 110 information pre-

1/0

1/0

8749H
8049AH'
8048AH
8748H
8035AHL
8039AHL

D
D

Figure 13.

MCSC!l~8

Expansion Capability

2·10

MCS®..,48 Instruction Set

3

MCS®-48 INSTRUCTION SET
1.0 INTRODUCTION

1.1 Data Transfers

The MCS®-48 instruction set is extensive for a machine
of its size and has been tailored to be straightforward and
very efficient in its use of program memory. All instructions are either one or two bytes in length and over 80%
are only one byte long. Also, all instructions execute in
either one or two cycles and over 50% of all instructions
execute in a single cycle. Double cycle instructions include all immediate instructions, and all 110 instructions.

As can be seen in Figure I the 8-bit accumulator is
the central point for all data transfers within the 8048.
Data can be transferred between the 8 registers of each .
working register bank and the accumulator directly, Le.,
the source or destination register is specified by the instruction. The remaining locations of the internal RAM
array are referred to as Data Memory and are addressed
indirectly via an address stored in either RO or R I of the
active register bank. RO and RI are also used to indirecly
address external data memory when it is present. Transfers
to and from internal RAM require one cycle; while transfers to external RAM require two. Constants stored in
Program Memory can be loaded directly to the accumulator and to the 8 working registers. Data can also be
transferred directly between the accumulator and the on-

The MCS-48 microcomputers have been designed to handle arithmetic operations efficiently in both binary and
BCD as well as handle the single-bit operations required
in control applications. Special instructions have also been
included to simplify loop counters, table look-up routines,
and N-way branch routines.

r----------l
I
I
I

I

PROGRAM
MEMORY
(#DI\.TA)

I
I

DATA
MEMORY
MOV
WORKING REG

ADD
MOV
MOVP
MOVP3
ANL
ORL
XRL

I

MOV
ADD
ANL
ORL
XRL
XCH

I

EXTERNAL
EXPANDER /111-_=---'-', ,....:>"-''----------....:..'-----....:..'-,
1/0 PORTS
/,:=:-=,.-1-""
MEMORY
4-7
~_ _ _~~_ _~~---~---~~cr-~~r -,,~~. <::X

2.4 - - - . . . . , .

0.45

,...._ _ _ _ _ _ _ _ _ _ _ __

" ' . - -_ _

270161-3
A.C. Testing: Inputs are driven at 2.4V fora Logic "1" and 0.45V for a logic "0". Output timing measurements are made at2.0V for logic "1"
and O.BV for a logic "0".

4·4

inter

8243

WAVEFORMS

PROG

~~

PORT2

______________ IK ________________

~

FLOAT

FLOAT

PORT 2

IpO

PORTS 4·7

OUTPUT
VALID

PREVIOUS OUTPUT VALlO

lIP

PORTS 4·7

INPUT VALlO

ICS

ICS

270161-4

4-5

inter

8243

125

100

C

!

:;
5}

~

...Z
"'.
'"'"

75

III

GUARANTEED WORST CASE
CURRENT SINKING CAPABILITIES
OF ANY 1/0 PORT PIN YO. TOTAL
SINK CURRENT OF ALI. PINS

..
U

Z

...iii

50

~

...0

25

4

10

11

13

12

MAXIMUM SINK CURRENT ON ANY PIN @ .45V
MAXIMUM 101. WORST CASE PIN (mA)

270161-5

Figure 3. 8243 Current Sink Capability
NOTE:
A 10 to 50 Kn pullup resistor to + 5V should be
added to 8243 outputs when driving to 5V CMOS
directly.

Sink Capability .
The 8243 can sink 5 rnA @ 0.45V on each of its 16
liD lines simultaneously. If, however, all lines are
not sinking simultaneously or all lines are not fully
loaded, the drive capability of any individual line increases as is shown by the accompanying curve.

Example: This example shows how the use of the
20 rnA sink capability of Port 7 affects the
sinking capability of the. other liD lines.
An 8243 will drive the following loads
simultaneously.

For example, if only 5 of the 16 lines are to sink
CUii6nt at one time, the cur.;e ShO\NS that· each of
those 5 lines is capable of sinking 9 rnA @ 0.45V (if
any lines are to sink 9 rnA the total IOL must not
.
exceed 45 rnA or five 9 rnA loads).

2 loads-20 rnA
8 10ads-4 rnA

6 loads-3.2 rnA

Example: How many pins can drive 5 TIL loads
(1.6 rnA) assuming remaining pins are un~
,loaded?
IOL

@

@

1V (Port 7 only)

0.45V
@

0.45V

Is this within the specified limits?
EIOL = (2 X 20)
= 91.2 rnA.

= 5 x 1.6 rnA = 8 rnA

+

(8

x

4)

+

(6

x

3.2)

EIOL = 60 rnA from curve
# pins = 60 rnA -7- 8 rnA/pin = 7.5 = 7

From the curve': for loi. = 4 rnA, EIOL ~
93 rnA. Since 91.2 rnA < 93 rnA the loads
are within specified limits.

In this case, 7 lines can sink 8 rnA for a
total of 56 rnA. This leaves 4 rnA sink current capability which can be divided in any
way among the remaining 8 liD lines of
the 8243.

Although the 20 rnA @ 1V loads are used
in calculating eIOL' it is the largest current
. required @ 0.45V which determines the
maximum allowable eIOL.

4-6

inter

8243

-=CS

liD
PROG
TEST
INPUTS

8048

P4

110

P5

110

PROG

8243
P6

4

110

DATA IN
P2

P20-P23

P7

110

270161-6

Figure 4. Expander Interface

P20·P23

~'-_---JX'--ADDRESS (4·8ITSI

__--J)>---

BITS 3,2
00 } READ
01
WRITE
10 OR
11
AND

BITS 1,0
00
01 } PORT
10 ADDRESS
11

DATA (4·8ITSI

270161-7

Figure 5. Output Expander Timing

PORT 1

0048

PORT2
PROG~--------------+---------------~--------~------~--------------~

270161-8.

Figure 6. Using Multiple 8243'5

4-7

P8748H/P8749H
8048AH/8035AHL/8049AH/8039AHL/8050AH/8040AHL
HMOS SINGLE-COMPONENT 8-BIT
PRODUCTION MICROCONTROLLER

•
•
•
•
•

Programmable ROMs Using 21V
• Easily
Memory and I/O
• Up to 1Expandable
IJ-s Instruction Cycle All
• Instructions 1 or 2 Cycles

High Performance HMOS II
Interval Time/Event Counter
Two Single Level Interrupts
Single 5-Volt Supply
Over 96 Instructions; 90% Single Byte

~36

The Intel MCS®-48 family are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS process.

The family contains 27 I/O lines, an 8-bit timer/counter, and on-board oscillator/clock circuits. For systems
that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcontrollers are available in both masked ROM and ROMless versions as well as a neW version,
The Programmable ROM. The Programmable ROM provides the user with the capability of a masked ROM
while providing the flexibility of a device that can be programmed at the time of-requirement and to the desired
data. Programmable ROM's allow the user to lower inventory levels while at the same time decreasing delay
'
,times and code risks.
These microcomputers are d,esigned to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting of mostly, single byte instructions and no instruc'
tions over 2 bytes in length.
Memory

RAM STANDBY

B050AH

Device

4KxBROM

256xBRAM

yes

B049AH

2KxBROM

12BxBRAM

yes

B04BAH

1KxBROM

64xBRAM

yes

B040AHL

None

256xBRAM

yes

B039AHL

None

12BxBRAM

yes

B035AHL

None

64xBRAM

yes

PB749H

2K x B Programmable ROM

12BxBRAM

no

PB74BH

1K x B Programmable ROM

64xBRAM

no

• CLOCK

Internal

I I

PROGRAM

I,

r~Po.RT

DATA

XTALt

P

,

270053-1

Figure 1. Block Diagram
270053-2

Figure 2. Logic Symbol

4-8

November 1987
Order Number: 270053-002

intJ

MCS®-48

I~ ~ ~

wee

I~
en a::
TO

0

r--

CD

II)

0 0z u
- ~
~ a..
~ D~
....
> ~

Vee

,

T1
P27
P26
P2S
P2'
PI7
P'6

XTAL 1
XTAL2
RESET'

SS
INT
EA

AD

P2.4
PL7
PI.6

EA

Rii
PSEN

p,s

PSEN

•

iNT

WR

WR

Ne

ALE

B049AH/B039AHL
B050AH/B040AHl
44- PIN
Plee

PI.S
PI.4
Ne

ALE

DBO
DB,
DB2
DB3
DB.
DBS
DB6
DB7

PI.3

090
091
092

PI.2
PI.I

Top View
looking down on PC Boord

PCO
VOO

093

VSS " - _ - - - ' ' ' '

270053-3
270053-14

Figure 3. Pin Configuration

Figure 4. Pad Configuration
Table 1. Pin Description

Symbol

Pin
No.

Function

Device

VSS

20

Circuit GND potential.

All

VDD

26

+ 5V during normal operation.

All

low power standby pin.

8048AH
8035AHl
8049AH
8039AHl
8050AH
8040AHl

Programming power supply (+ 21 V).

P8748H
P8749H

+ 5V during operation and programming.

Vee

40

Main power supply;

PROG

25

Output strobe for 8243 110 expander.

All
All

Program pulse ( + 18V) input pin During Programming.

P8748H
P8749H

P10-P17
Port 1

27-34

8-bit quasi-bidirectional port.

All

P20-P23
P24-P27
Port 2

21-24
35-38

8-bit quasi-bidirectional port. P20-P23 contain the four high order
program counter bits during an external program memory fetch and
serve as a 4-bit 1/0 expander bus for 8243.

All

DBO-DB7
BUS

12-19

True 'bidirectional port which can be written or read synchronously
using the RD, WR strobes. The port can also be statically latched.
Contains the 8 low order program counter bits during an external
program memory fetch, and receives the addressed instruction under
the control of PSEN. Also contains the address and data during an
external RAM data store instruction, under control of ALE, RD, and
WR.

All

Input pin testable using the conditional transfer instruction JTO and
JNTO. TO can be designated as a clock output using ENTO ClK
instruction.

All

Used during programming.

P8748H
P8749H

TO

1

4-9

intJ

MCS®·48

Table 1. Pin Description (Continued)
Symbol
T1

Pin
No.
39

INT

6

RD

S

RESET

4

Function

Device

Input pin testable using the JT1, and JNT1 instructions. Can be
designated the timer/counter input !,Ising the STRT CNT instruction.
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is
disabled after a reset. Also testable with conditional jump instruction.
(Active low) interrupt must remain low for at least 3 machine cycles for
proper operation.
Output strobe activated during a BUS read. Can be used to enable
data onto the bus from an external device.
Used as a read strobe to external data memory. (Active low)
Inputwhich is used to initialize the processor. (Active low) (Non TTL
VIH)
Used during power down.

I.

.

Used during programming.
Used during ROM verification.

WR

10

ALE

11

PSEN

9

SS

5

Output strobe during a bus write. (Active low)
Used as write strobe to external data memory.
Address latch enable. This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into external data and
program memory.
Program store enable. This output occurs only during a fetch to
external program memory. (Active low)
Single step input can be used in conjunction with ALE to "single step"
the processor through each instruction.
(Active low) Used in sync mode.

All
All

All

All
S04SAH
S035AHL
S049AH
S039AHL
S050AH
S040AHL
PS74SH
PS749H
S04SAH
PS74SH
S049AH
PS749H
S050AH
All
All

All
All
S04SAH
8035AHL

EA

7

External access input which forces all program memory fetches to
reference external memory. Useful for emulation and debug. (Active
high)
Used during (1SV) programming.
Used during ROM verification (12V).

XTAL1

2

XTAL2

3

One side of crystal input for internal 'oscillator. Also input for external
source. (Non TTL VIH)
Other side of crystal input.
4-10

S049AH
S039AHL
S050AH
S040AHL
All

PS74SH
PS749H
S04SAH
S049AH
S050AH
All
All

MCS®-48

Table 2. Instruction Set
Accumulator
Mnemonic
ADDA,R
ADDA,@R

Input/Output
Description

Add register to A
Add data memory
toA
ADD A, #data Add immediate to A
AD DC A, R
Add register with
carry
AD DC A, @R
Add data memory
with carry
ADDC A, # data Add immediate with
carry
ANLA, R
And register to A
ANLA,@R
And data memory
toA
ANLA, #data And immediate to A
ORLA, R
Or register to A
ORLA,@R
Or data memory
toA
ORLA, #data Or immediate to A
XRLA, R
Exclusive or register
toA
XRLA, @R
Exclusive or data
memory to A
XRLA, #data Exclusive or
immediate to A
INCA
IncrementA
DECA
Decrement A
CLRA
Clear A
CPLA
Complement A
DAA
Qecimal adjust A
SWAP A
Swap nibbles of A
RLA
Rotate A .left
RLCA
Rotate A left
through carry
RRA
Rotate A right
RRCA
Rotate A right
through carry

Bytes Cycles
1
1

1
1

2

2

1

1

1

1

2

2

1
1

1
1

2

2

1
1

1
1

2

2

1

1

1

1

2

2

1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

Mnemonic

Bytes Cycles

Description

Input port to A
Output A to port
And immediate to
port
ORL P, #data
Or immediate to
port
Input BUS to A
INS A, BUS
OUTLBUS,A
Output Ato BUS
ANL BUS, #data And immediate to
BUS
ORL BUS, # data Or immediate to
BUS
MOVDA, P
Input expander port
toA
MOVDP,A
Output A to
expander port
ANLD P,A
And A to expander
port
ORLDP,A
Or A to expander
port

INA,P
OUTLP,A
f.NL P, #data

2

2
2
2

2

2

2

2
2
2

2

2

1
1

2
2
2
2

Registers
Mnemonic
INCR
INC@R
DECR

Description
Increment register
Increment data memory
Decrement register

Bytes Cycles
1

1

Branch
Mnemonic

Description

JMP addr
Jump unconditional
JMPP@A
Jump indirect
DJNZ R, addr Decrement register
and skip
JCaddr
Jump on carry = 1
JNC addr
Jump on carry = 0
JZaddr
Jump on A zero
JNZaddr
Jump on A not zero
JTO addr
Jump on TO = 1
JNTO addr
Jump on TO = 0
Jump on T1 = 1
JT1 addr
JNT1 addr
JumponT1 = 0
JFO addr·
Jump on FO = 1
JF1 addr
Jump on F1 = 1
JTF addr
Jump on timer flag
JNI addr
Jump on INT = 0
JBb addr
Jump on accumulator
bit

1
1

4-11

Bytes Cycles

2
2

2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

1

MCS®-48

Table 2. Instruction Set (Continued)
.-----~------~------------------~

r--------------------------------~

Subroutine
Mnemonic

Description

CALLaddr
RET
RETR

Jump to subroutine
Return
Return and restore
status

Timer/Counter

Bytes Cycles

2

2
2
2

1
1

Flags
Mnemonic
CLRC
CPLC
CLRFO
CPLFO
CLR F1
CPLF1

Description

1
1
1
1
1
1

1
1
1
1
1
1

Mnemonic

Description

Move register to A
Move data memory
toA
MOVA, #data Move immediate to
A
MOVA,A
Move A to register
MOV@A,A
Move A to data
memory
MOVR, #data Move immediat~ to
register
MOV @A, #data Move immediate to
data memory
MOVA,PSW
MovePSWtoA
MOVPSW,A
MoveAtoPSW
XCHA, A
Exchange A and
register
XCHA,@R.
Exchange A and
data memory
XCHDA,@A
Exchange nibble of
A and data memory
MOVXA,@A
Move external data.
memoiytoA
MOVX@A,A
Move A to external
data memory
MOVPA,@A
Move to A from
current page
MOVP3A,@A Move to A from
page 3

1
1

2

2

2

2

2

2

Mnemonic

1
1
1
1
1

Description

1
1
1
1
1

Bytes Cycles

Enable external
. interrupt
DISI
Disable external
interrupt
Select register bank 0
SELABO
Select register bank 1
SELAB1
SELMBO Select memory bank 0
SELMB1
Select memory bank 1
ENTOCLK Enable clock output
onTO

2
2
2
1.

Bytes Cycles

EN I

Bytes Cycles
1
1

Aead timer/counter
Load timer/counter
Start timer
Start counter
Stop timer/counter
Enable timer/
counter interrupt
Disable timer/
counter interrupt

Control

Data Moves

MOVA,A
MOVA,@R

Description

MOVA, T
MOVT,A
STATT
STATCNT
STOP TCNT
EN TCNTI
DIS TCNTI

Bytes Cycles

Clear carry .
Complement carry
Clear flag 0
, Complement flag 0
Clear flag 1
Complement flag 1

Mnemonic

2

4-12

1

1

Mnemonic

Description

Bytes

Cycles

NOP

No operation

1

1

MCS®·48

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

+ 70·C
+ 150·C

Case Temperature Under Bias ...•..• O·C to
Storage Temperature .•.•..•... - 65°C to

Voltage on any Pin with Respect
to Ground ...................... - 0.5V to

+ 7V

Power Dissipation .............•.....•...... 1.5W

NOTICE: Specifications contained within the'
following tables are subject to change.

D.C. CHARACTERISTICS
Symbol

TA

=

O·C to

+ 70·C; Vee =

Voo

limits

Parameter
Min

Typ

=

5V

Unit

± 10%; Vss = OV
Test Conditions

Device

Max

-0.5

0.8

V

All

Input Low Voltage
(RESET, X1, X2)

-5

0.6

V

All

VIH

Input High Voltage
(All Except XTAL 1,
XTAL2, RESET)

2.0

Vee

V

All

VIH1

Input High Voltage
(X1, X2, RESET)

3.8

Vee

V

All

VOL

Output Low Voltage
(BUS)

0.45

V

IOL

=

2.0 rnA

All

VOL1

Output Low Voltage
(RD, WR, PSEN, ALE)

0.45

V

IOL

=

1.8 rnA

All

VOL2

Output Low Voltage
(PROG)

0.45

V

IOL

=

1.0 rnA

All

VOL3

Output Low Voltage
(All Other Outputs)

0.45

V

IOL

=

1.6 rnA

All

VOH

Output High Voltage
(BUS)

2.4

V

IOH = - 400 /LA

All

VOH1

Output High Voltage
(RD, WR, PSEN, ALE)

2.4

V

IOH

=

-100

!LA

All

VOH2

Output High Voltage
(All Other Outputs)

2.4

V

IOH

=

-40/LA

VIL

Input Low Voltage (All
Except RESET, X1, X2)

VIL1

4-13

All

inter

MCS®-48

D.C. CHARACTERISTICS
Symbol

TA

=

0·Cto+70·C;Vee

Parameter
Min
Leakage Current
(T1,INT) ,

ILl
IUl

Input Leakage Current
(P10-P17, P20-P27,
EA, SS)
,

IU2

Input Leakage Current
RESET

ILO

Leakage Current
(BUS, TO) (High
Impedance State)

100

Voo Supply Current
(RAM Standby)

100 +

=

Limits
Typ

Voo

=

5V ±10%;Vss= OV(Continued)

Unit,

Test Conditions

Device

Max

s

±10

p.A

Vss

-500

p.A

Vss + 0.45

-SOO

p.A

Vss

±10

p.A

Vsss VIN sVee

S

5

,mA'

B04BAH
BOS5AHL

4

7

mA

8049AH
BOS9AHL

5

10

mA

SO

65

mA

B048AH
BOS5AHL

35

70

mA

B049AH
BOS9AHL

40

BO

mA

B050AH
B040AHL

SO

100

mA

PB74BH

50

110

mA

PB749H

, ,2.2

5.5

V

2.2

5.5

V

2.2

5.5

\I

All

VINs Vee

,

-10

Total Supply Current"

s

VIN

s

s

VIN

s

All

Vee

All

S.B

All

8050AH
B040AHL

.,;

lee

Voo

'Icc

+

RAM Standby Voltage

I

v

Standby Mode Reset
sVILl

B04BAH
8035AH
B049AH
BOS9AH

I

8050AH
B040AHL

100 are measured with all outputs in their high impedance state; RESET low; 11 MHz crystal applied; INT, 55, and EA floating.

I

intJ

MCS®-48

A.C. CHARACTERISTICS
Symbol

TA

=

O·Cto +70·C;Vcc

Parameter

=

voo

=

5V ±10%;Vss
11 MHz

f (t)
(Note 3)

Min

Max
1000

=

ov

Unit

Conditions
(Note 1)

ns

(Note 3)

t

Clock Period

1 /xtal freq

90.9

tLL

ALE Pulse Width

3.5t-170

150

ns

tAL

Addr Setup to ALE

2t-110

70

ns

tLA

Addr Hold from ALE

tCC1

Control Pulse Width (RD, WR)

tCC2

Control Pulse Width (PSEN)

tow

Data Setup before WR

two

Data Hold after WR

tOR

Data Hold (RD, PSEN)

t-40

50

ns

7.5t-200

480

ns

6t-200

350

ns

6.5t-200

390

ns

t-50

40

1.5t-30

0

ns
110

ns

tR01

RD to Data in

tR02

PSEN to Data in

tAW

Addr Setup to WR

tA01

Addr Setup to Data (RD)

10.5t-220

tA02

Addr Setup to Data (PSEN)

7.5t-200

tAFC1

Addr Float to RD, WR

tAFC2

Addr Float to PSEN

tLAFC1

ALE to Control (RD, WR)

tLAFC2

ALE to Control (PSEN)

tCA1

Control to ALE (RD, WR, PROG)

tCA2

Control to ALE (PSEN)

tcp

Port Control Setup to PROG

1.5t-80

50

ns

tpc

Port Control Hold to PROG

4t-260

100

ns

tpR

PROG to P2 Input Valid

tpF

Input Data Hold from PROG

top
tpo
tpp

PROG Pulse Width

tpL

Port 2 110 Setup to ALE

6t-170

375

ns

4.5t-170

240

ns

5t-150

(Note 2)

300

ns'
730

ns

460

ns

2t-40

140

ns

(Note 2)

0.5t-40

10

ns

(Note 2)

3t-75

200

ns

1.5t-75

60

ns

t-65

25

ns

4t-70

290

ns

8.5t-120

650

ns

140

ns

1.5t

0

Output Data Setup

6t-290

250

ns

Output Data Hold

1.5t-90

40

ns

10.5t-250

700

ns

4t-200

160

ns

15

tLP

Port 2 110 Hold to ALE

0.5t-30

tpv

Port Output from ALE

4.5t+ 100

tOPRR

TO Rep Rate

3t

270

tCY

Cycle Time

15t

1.36

ns
5.0

ns

15.0

p.s

ns

NOTES:

1. Control outputs: CL = 80 pF. BUS Outputs: CL = 150 pF.
2. BUS High Impedance Load 20 pF
3. f(t) assumes 50% duty cycle on X1, X2. Max clock period is for a 1 MHz crYstal input.

4-15

inter

MCS®·48

WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM
MEMORY

READ FROM EXTERNAL DATA MEMORY

-..j .LAFC1rALE

RD
'DR
FLOAT.NG

270053-5

INPUT AND OUTPUT FOR A.C. TESTS

WRITE TO EXTERNAL DATA MEMORY

...

2.4Y -----X~.Q TEST
OA5V----J. .0.8""

POINTSt'2.0~
.... 0 . 8 " - - - -

270053-7
A.C. testing inputs are driven at 2.4V lor a logic "1" and 0,45V lor
a logic "0". Output timing measurements are made at 2.0V lor a
logic "1" and 0.8V lor a logic "0".

270053-6

PORT 1/PORT 2 TIMING

ALE
PSEN

I

I

P2~-23

OUTPUT

~

P24-21
P10-17
OUTPUT

__

r-----P-~~R-T-~-~--i-O-A--'A--~\lr-h-·E-W-·F-.U----~-O-A-~~--

PCH
~----------J

PORT 24-21. PORT 10-17 DATA

'LP
EXPANDER
PORT
OUTPUT

---l

I~

I

··LA---...........-

,..----'------->.1 r------;,

;-------' -_ _ _ _ _ _...J

I

'NPUT

I

"
r-~-~

I

I~'
'PF

i---

I
~--PC-H--~I

OUTPUT DATA

'PR~

j-.cp+.PC.j ' - - _ . J I
PROG

'-'CA1

,'DP-----r1

PCH

EXPANDER
PORT

NEW PORT 9ATA

I

---.,.--------------....,~r-.PP_r_
270053-8

4-16

MCS®-48

CRYSTAL OSCILLATOR MODE

CERAMIC RESONATOR MODE

Cl

~,-C_2_--,L, ,- -"-_~_~_!- -:2:-1
__

-:b

Cl

f------""""""f"---=2'-l

~(
XTALl

J-

XTAL2

C3

XTALl

1-11

C""""~ ~

XTAL2

C3

270053-9
Cl = 5 pF ±% pF + (STRAY < 5 pF)
C2 = (CRYSTAL + STAY) < 8 pF
C3 = 20 pF ±1 pF + (STRAY < 5 pF)
Crystal series resistance should be less than 3011 at 11 MHz; less
than 7511 at 6 MHz; less than 18011 at 3.6 MHz.

270053-10

DRIVING FROM EXTERNAL SOURCE
+SV

47011

»-.----'=-1 XTAL1
+5V

TTL OPEN
COLLECTOR
GATES

47011
'----..L---;;1 XTAL2

270053-11
For XTALl and XTAL2 define "high" as voltages above 1.6V and
"low" as vOltages below 1.6V. The duty cycle requirements for
externally driving XTAL 1 and XTAL2 using the circuits shown
above are as follows: XTAL1 must be high 35-65% of the period
and XTAL2 must be high 35-65% of the period. Rise and fall times
must be faster than 20 ns.

4-17

inter

MCS®-48

PROGRAMMING AND VERIFYING THE
P8749H/48H PROGRAMMABLE ROM

WARNING:
An attempt to program a missocketed P8749H/48H
will result in severe damage to the part. An indication
of a properly socketed part is the appearance of the
ALE clock output. The lack of this clock may be
used to disable the programmer.

Programming Verification
In brief, the programming process consists of: activating the program mode, applying an address,
latching the address, applying data, and applying a
programming pulse. Each word is programmed completely before moving on to the next and is followed
by a verification step. The following is a list of the
pins used for programming and a description of their
functions:

Pin

The ProgramlVerify sequence is:
1. Voo = 5V, Clock applied or internal oscillator
operating, RESET = OV, TO = SV, EA = SV,
BUS and PROG floating. P10 and P11 must be
tied to ground.
2. Insert P8749H/48H in programming socket
3. TO = OV (select program mode)

Function

XTAL1
XTAL2
RESET
.... ...
TO
EA
BUS

4. EA

Clock Input (3 to 4.0 MHz)

= 18V (activate program mode)

S. Address applied to BUS and P20-22
6. RESET = SV (latch address)

Initialization and Address Latching
Selection of Program or Verifying Mode
Activation of ProgramlVerify Modes
Address and Data Input
'Data Output During Verify
P20-P22 Address Input
Programming Power Supply
Voo
Program Pulse Input
PROG
,

7. Data applied to BUS
8. Voo = 21V (programming power)
9. PROG = Vee or float followed by one SO ms
pulse to 18V
10. Voo = 5V
11. TO

= SV (verify mode)

12. Read and verify data on BUS
13. TO

= OV

14. RESET

= OV and repeat from step S

1S. Programmer should be at conditions of step 1
when P8749H/48H is removed from socket.

NOTE:
Once programmed the P8749H/48H cannot be
erased.

4-18

MCS®-48

A.C. TIMING SPECIFICATION FOR PROGRAMMING P8748H/P8749H ONLY
TA

=

25°C ±5°C; VCC

=

Symbol

5V ±5%; VOO

=

21 ±0.5V

Parameter

Min

tAW

Address Setup Time to RESET

4tCY
4tcy

Max

Unit

tWA

Address Hold Time After RESET

tow

Data in Setup Time to PROG

4tCY

two

Data in Hold Time After PROG

4tCY

tpH

RESET Hold Time to Verify

4tCY

tVOOW

Voo Hold Time Before PROG

0

1.0

ms

tvoOH
tpw

Voo Hold Time After PROG

0

1.0

ms

Program Pulse Width

50

60

ms

trw

TO Setup Time for Program Mode

4tCY

tWT

TO Hold Time After Program Mode

4tcy

too

TO to Data Out Delay

tww

RESET Pulse Width to Latch Address

tr, tl

Voo and PROG Rise and Fall Times

0.5

100

J.Ls

tCY

CPU Operation Cycle Time

3.75

5

J.Ls

tRE

RESET Setup Time before EA

4tCY

Test Conditions

4tCY
4tcy

NOTE:

II Test 0 is high, too can be triggered by RESET.

D.C. CHARACTERISTICS FOR PROGRAMMING P8748H/P8749H ONLY
TA

=

25°C ±5°C; Vcc

Symbol

=

5V ±5%; Voo

=

21 ±0.5V

Parameter

Min

Max

Unit

VOOH

Voo Program Voltage High Level

20.5

21.5

V

VOOL

Voo Voltage Low Level

4.75

5.25

V

VPH

PROG Program Voltage High Level

17.5

18.5

V

VPL

PROG Voltage Low Level

4.0

EA Program or Verify Voltage High Level

17.5

Vcc
18.5

V

VEAH
100

Voo High Voltage Supply Current

20.0

rnA

IpROG

PROG High Voltage Supply Current

1.0

rnA

lEA

EA High Voltage Supply Current

1.0

rnA

4-19

V

Test Conditions

MCS®·48

SUGGESTED ROM VERIFICATION ALGORITHM FOR ROM DEVICE ONLY
INITIAL ROM DUMP CYCLE

SUBSEQUENT ROM DUMP CYCLES

ALE
(NOTE 1)

E« ....:J.

I

: (INPUT)
I
I

,,

I

DB----i

ROM DATA

.....-(~IN:-::P::-U':':T::-)---'

H
I

H

ADDRESS

(OUTPUT)

,

ADDRESS
(INPUT)

~----------------­
(OUTPUT)'

I

~,

RESET _ _ _ _ _ _....

I

.

(INPUT)

.

! - - i-

,,

-

-

,
PZ~PZ3---_L_ _ _ _A_DD_R_E_S_S_ _ _~~~---A-D-D-RE-S-S----Jr--____________
I

: (INPUT)

270053-12
Vee = Veo
Vss = OV

50H
ADDR
ADDR

Al0
All

= +5V

NOTE:

ALE is function of X1, X2 inputs.

COMBINATION PROGRAM/VERII=Y MODE (PROGRAMMABLE ROMS ONLY)
VEAH
EA
Vee

TO

---+---'
I_ _ _ _ _ _ _

PROGRAM--------II--~VERIFY-~~---PROGRAM-

Vee

VIL1
Vee

RESET
VIL1

DBa-DB7

iAw-+i--t--i-1 twA

J --.

-

-tcc~

DATA TO BE
PROGRAMMED VALID

NEXT
ADDRESS

LAST
ADDRESS

VDDH - - - - - - - - - - - VDD
.Vee------------

lOw

VPH -----------------+-t-i--_\.
PROG
VPL---------------

------,-- --.-----------270053-13

4-20

inter

D8748H/D8749H
HMOS-E SINGLE-COMPONENT 8-BIT MICROCOMPUTER
with 8080/8085 Peripherals
• Compatible
Easily Expandable Memory and 110
• Up to 1.35 p,s Instruction Cycle;
• All Instructions 1 or 2 Cycles

Performance HMOS-E
• High
Interval Timer/Event Counter
• Two Single Level Interrupts
• Single 5-Volt Supply
• Over 96 Instructions; 90% Single Byte
•

The Intel D8749H/D8748H are totally self-sufficient, 8-bit parallel computers fabricated on single silicon chips
using Intel's advanced N-channel silicon gate HMOS-E process.
The family contains 27 I/O lines, an 8-bit timer/counter, on-chip RAM and on-board oscillator/clock circuits.
For systems that require extra capability, the family can be expanded using MCS®-80/MCS®-85 peripherals.
These microcomputers are designed to be efficient controllers as well as arithmetic processors. They have
extensive bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient use of
program memory results from an instruction set consisting mostly of single byte instructions and no instructions over 2 bytes in length.
Device

Internal Memory

D8749H

' 2Kx8 EPROM

D8748H

1Kx8 EPROM

I
I

128 x8 RAM
64x8 RAM

PORT
I

PORT

D8748H

2

D87-49H

READ
WRITE

PROGRALi
STORE

ENABLE
ADDRESS
LATCH

. ENABLE
PORT
EXPANDER
STROBE

210983-1

Figure 1.
Block Diagram

210983-2

Figure 2.
Logic Symbol

4-21

October 1987
Order Number: 210983-003

D8748H/D8749H

Vee

Tl
P27
P26

RESET

55

P25
P2.
P17

Ro

P16

PSEN

P15

Wi!

P14

08.

P12

DB,

P11

P13

08 2

Pl.

DB.

VOO

PROG

P23
P22
P21

DB7
VSS

210983-3

Figure 3. Pin Configuration
. Table 1. Pin Description (40-Pin DIP)
Symbol
Vss
VDD

Pin No.
20
26

Function
Circuit GND potential.

+ 5V during normal operation.
Programming power supply (+ 21 V).

Vee
PROG

40
'25

Main power supply;

+ 5V during operation and programming.

Output strobe for 8243 I/O expander.
Program pulse ( + 18V) input pin during programming.

P10-P17
Port 1

27-34

8·bit quasi·bidirectional port.

P20-P23

21-24

8·bit quasi-bidirectional port. P20-P23 contain the four high order program
counter bits during an external program memory fetch and serve as a 4·bit
I/O expander bus for 8243.

P24-P27
Port 2

35-38

DBO-DB7

·12-19

~II""

True bidirectional port which can be written or read synchronously using the

RD, 'yAJR stiobes. The port can also be statically !atc.hed. Contains the 8 !O\&,

OUi:)

order program counter bits during an eXternal program memory tetch, and
receives the addressed instruction under the control of PSEN. Also contains
the address and data du~ an external RAM data store instruction, under
control of ALE, RD; and WR.
TO

1

Input pin tesliible using the conditional transfer instructions JTO and JNTO.
TO can be designated as a clock output using ENTO CKL instruction.

T1

39

Input pin testable using the JT1, and JNT1 instructions. Can be designated
the timer/counter input using the STRT CNT instruction.

INT

6

Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is
disabled after a reset. Also testable with conditional jump instruction. (Active
low) interrupt must remain low for at least 3 machine cycles for proper
operation.

RD

8

Output strobe activated during a BUS read. Can be used to enable data onto
the bus from an external device.
Used as a read strobe to external data memory. (Active low)

Used during programming.

4·22

intJ

D8748H/D8749H

Table 1 Pin Description (40-Pin DIP) (Continued)
Symbol

Pin No.

RESET

4

Input which is used to initialize the processor. (Active low) (Non TTL VI H)

WR

10

Output strobe during a bus write. (Active low)
Used as write strobe to external data memory.

ALE

11

Address latch enable. This signal occurs once during each cycle and is
useful as a clock output.
The negative edge of ALE strobes address into external data and program
memory.

PSEN

9

Program store enable. This output occurs only during a fetch to external
program memory. (Active low.)

SS

5

Single step input can be used in conjunction with ALE to "single step" the
processor through each instruction.

EA

7

.External access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug. (Active high.)

XTAL1

2

One side of crystal input for internal oscillator. Also input for external source.
(Non TTL VIH.)

XTAL2

3

Oth~r

Function
Used during programming.

Used during (1 BV) programming.

side of crystal input.
Table 2. Instruction Set

Mnemonic
Description
ACCUMULATOR
Add register to A
ADD A, R
ADDA,@R
Add data
memory to A
ADDA, #data
Add immediate
toA
ADDCA,R
Add register with
carry
ADDCA,@R
Add data
memory with
carry
ADDC A, #data Add immediate
with carry
ANLA,R
And register to A
ANLA,@R
And data
memory to A
ANLA, #data
And immediate
toA
ORLA, R
Or register to A
ORLA,@R
Or data memory
toA
ORLA, #data
Or immediate to
A
XRLA, R
Exclusive or
register to A
XRLA,@R
Exclusive or
data memory to
A
XRLA, #data
Exclusive or
imniediate to A

Bytes

Cycles

2

2

2

2

2

2

Description
Mnemonic
ACCUMULATOR (Continued)
IncrementA
INCA
DECA
Decrement A
Clear A
GLRA
GPLA
Compleinent A
DAA
Decimal adjust A
SWAP A
Swap nibbles of
A
RLA
Rotate A left
RLCA
Rotate A left
through carry
RRA
Rotate A right
RRGA
Rotate A right
through carry
INPUTIOUTPUT
INA,P
OUTLP, A
ANLP, #data
ORLP, #data

2

2

INSA,BUS
OUTLBUS,A
ANL BUS, #data
ORL BUS, #data

2

MOVDA, P

2

4-23

Input port to A
Output A to port
And immediate
to port
Or immediate to
port
Input BUS to A
Output A to BUS
And immediate
to BUS
Or immediate to
BUS
Input expander
port to A

Bytes

Cycles

1
1
2

2

2

2

1
1
2

2
2
2

2

2

2
2

2

inter

D8748H/D8749H

~OOjgILOIMIOOO£OOW

Table 2. Instruction Set (Continued)
Mnemonic
Description
INPUTIOUTPUT (Continued)
MOVDP,A
Output A to
expander port
ANLDP,A
And A to expander
port
ORLDP,A
Or A to expander
port
REGISTERS
INCR
INC@R

DECR
BRANCH
JMPaddr
JMPP@A
DJNZR,addr
JCaddr
JNCaddr
JZaddr
JNZaddr
JTOaddr
JNTOaddr
JT1 addr
JNT1 addr
JFOaddr
JF1 addr
JTFaddr
JNI addr
JBb addr

SUBROUTINE
CALLaddr
RET
RETR

FLAGS
CLRC
CPLC
CLRFO
CPLFO
CLRF1
CPLFI
DATA MOVES
MOVA,R
MOVA,@R

MOVA, "'data

Bytes

Mnemonic
Description
DATA MOVES (Continued)
MOVR,A
Move A to register
Move A to data
.MOV@R,A
memory
MOVR, #data
Move immediate to
register
MOV @R, "'data Move immediate to
data memory
MOVA,PSW
MovePSWtoA
MOVPSW,A
MoveAtoPSW
XCHA, R
Exchange A and
register
XCHA,@R
Exchange A and
data memory
XCHDA,@R
Exchange nibble
of A and register
MOVXA,@R
Move external
data memory to A
MOVX@R,A
Move A to external
data memory
MOVPA,@A
Move to A from
current page
MOVP3A,@A
Move to A from
page 3

Cycles

2
2
1.

2

Increment register
Increment data
memory
Decrement register
Jump unconditional
Jump indirect
Decrement register
and skip
Jump on carry = 1
Jump on carry = 0
Jump on A zero
Jump ·on A not zero
Jump onTO = 1
Jump on TO = 0
JumponT1 = 1
JumponT1 = 0 .
Jump on FO = 1
JumponF1 = 1
Jump on timer flag
Jump on INT = 0
Jump on
accumulator bit

Jump to subroutine
Return
Return and restore
status

2
1
2

2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

2
1
1

2
2
2

TIMER/COUNTER
Read
MOVA,T
timer/counter
MOVT,A
Load
timer/counter
Start timer
STRTT
STRTCNT
Start counter
STOP TCNT
Stop timer/counter
EN TCNTI
Enable timer/
counter interrupt
DIS TCNTI
Disable timer!
counter interrupt
CONTROL
ENI
D!S!

Clear carry
Complement carry
Clear flag 0
Complement flag 0
Clear flag 1
Complement flag 1
Move register to A
Move data memory
toA
Move immediate
toA

SELRBO
1
1
1

SELRB1
SELMBO
SELMB1
ENTOCLK

2

2
NOP

4-24

Enable external
interrupt
Disable external
interrupt
Select register
bank 0
Select register
bank 1
Select memory
bank 0
Select memory
bank 1
Enable clock
output on TO
No operation

Bytes Cycles

2

2

2

2

2
2
2
2

inter

087 48H/087 49H

'Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

+ 70°C
+ 150°C

Ambient Temperature Under Bias .... O°C to
Storage Temperature .......... - 65°C to

Voltage On Any Pin With Respect
to Ground ...................... - 0.5V to

+ 7V

Power Dissipation ....................... 1.0 Watt

NOTICE Specifications contained within the
fol/owing tables are subject to change.

D.C. CHARACTERISTICS

TA

=

Parameter

Symbol

O°C to

+ 70°C·, Vee =

Voo

Limits
Min

Typ

Max

=

5V+ 10%·, Vss

-

Unit

=

OV

Test Conditions

Device

VIL

Input Low Voltage (All
Except RESET, X1, X2)

-0.5

0.8

V

All

VIL1

Input Low Voltage
(RESET, X1, X2)

-0.5

0.6

V

All

VIH

Input High Voltage
(All Except XTAL1,
XTAL2, RESET

2.0

Vee

V

All

VIH1

Input High Voltage
(X1, X2, RESET)

3.8

Vee

V

All

VOL

Output Low Voltage (BUS)

0.45

V

IOL

All

~ut

Low Voltage
(RD, WR, PSEN, ALE)

0.45

V

IOL

=
=

2.0mA

Vou

1.8 mA

All

VOL2

Output Low Voltage
(PROG)

0.45

V

IOL

=

1.0 mA

All

VOL3

Output Low Voltage
(All Other Outputs)

0.45

V

IOL

=

1.6 mA

All

VOH

Output High Voltage (BUS)

2.4

V

IOH

All

~ut

High Voltage
(RD, WR, PSEN, ALE)

2.4

V

IOH

=
=

-400 p.A

VOH1

-100 p.A

All

VOH2

Output High Voltage
(All Other Outputs)

2.4

V

IOH

=

-40 p.A

All

±10

p.A

Vss

S;

VIN

All

-500

/A-A

Vss

+ 0.45 .:::; VIN

-300

/A-A

Vss

S;

VIN

S;

3.8V

All

±10

/A-A

Vss

S;

VIN

S;

Vee

All

Leak~

lu

Current

S;

Vee

(T1,INT)
IU1

Input Leakage Current
(P10-P17, P20-P27,
EA,SS)

IU2

Input Leakage Current
RESET

ILO

Leakage Current
(BUS, TO) (High
Impedance State)

100

+

lee

Total Supply Current'

-10

S;

Vee

All

80

100

mA

8748H

95

110

mA

8749H

NOTE:

'Icc + IDD is measured with all outputs disconnected; ss, RESET, and INT equal

4-25

'0 Vee; EA equal to Vss.

intJ

D8748H/D8749H

A.C. CHARACTERISTICS
Symbol

TA

=

O·Cto +70·C;Vcc

Parameter

=

voo

=

5V ±10%;Vss
11 MHz

f(t)
(Note 3)

Min

Max
1000

=

OV

Unit

Conditions
(Note 1)

ns

(Note 3)

t

Clock Period

1/xtal freq

90.9

tLL

ALE Pulse Width

3.5t - 170

150

ns

tAL

Addr Setup to ALE

2t - 110

70

ns

tLA

Addr Hold from ALE

t - 40

50

ns

7.5t - 200

480

ns

6t - 200

350

ns

6.5t - 200

390

ns

t - .50

40

ns

1.5t - 30

0

tCC1

Control Pulse Width (RD, WR)

tcC2

Control Pulse Width (PSEN)

tow

Data Setup before WR

two

Data Hold after WR

tOR

Data Hold (RD, PSEN)

tR01

RDto Data In

tR02

PSEN to Data In

tAW

Addr Setup to WR

tA01

Addr Setup to Data (RD)

10.5t - 220

tA02

Addr Setup to Data (PSEN)

7.5t - 200

tAFC1

Addr Float to RD, WR

tAFC2

Addr Float to PSEN

tLAFC1

ALE to Control (RD, WR)

tLAFC2

ALE to Control (PSEN)

tCA1

Control to ALE (RD, WR, PROG)

tcA2

Control to ALE (PSEN)

tcp

Port Control Setup to PROG

tpc

Port Control Hold to PROG

tpR

PROG to P2 Input Valid

110

ns

6t - 170

375

ns

4.5t - 170

240

ns

5t - 150

300

(Note 2)

ns
730

ns

460

ns

140

ns

(Note 2)

0.5t - 40

10

ns

(Note 2)

3t - 75

200

ns

1.5t - 75

60

ns

t - 65

25

ns

2t - 40

4t - 70

290

ns

1.5t - 80

50

ns

4t - 260

100

8.5t - 120

tpF

Input Data Hold from PROG

top

Output Data Setup

C:+ _

1.5t
')on

VL

"'''''''

tpo

Output Data Hold

tpp

PROG Pulse Width

ns
650

0

140

ns
ns

250

ns

1.5t - 90

40

ns

10.5t - 250

700

ns

tpL

Port 2 1/0 Setup to ALE

4t - 200

160

ns

tLP

Port 2 1/0 Hold to ALE

0.5t - 30

15

ns

+ 100

510

tpv

Port Output from ALE

IoPRR

TO Rep Rate

3t

270

tcv

Cycle Time

15t

1.36

4.5t

NOTES:

ns
15.0

1. Control outputs CL = 80 pF; BUS outputs CL = 150 pF.
2. BUS High Impedance Load 20 pF.
3. f(t) assumes 50% duty cycle on X1, X2. Max clock period is for a 1 MHz crystal input.

4-26

ns

/los

inter

D8748H/D8749H

WAVEFORMS
INSTRUCTION FETCH FROM PROGRAM
MEMORY

1== --I ILAFcl~IY
ILL

J

WRITE TO EXTERNAL DATA MEMORY

'1

L________~I~--~L

ALE.

IAFd2

ALE

.

1- ICC2 --l

f-

J

L

ICA2

PSEN
ADDRESS

210983-6
210983-4

READ FROM EXTERNAL DATA MEMORY

INPUT AND OUTPUT FOR A.C. TESTS

--/tLAFC1L

ALE

Jr-----,IL...----:1_ _ _ _-'

l

2.4V - - - - - . .
O.45V _ _ _

tCA11RD

, - -_ _

----'X~:~: TEST POtNTS::~:~X,-_ _ __
210983-7

A.C. testing inputs are driven at 2.4V for a Logic "I" and 0.45V
for a Logic "0". Output timing measurements are made at 2.0V
for a Logic "I" and 0.8V for a Logic "0."
210983-5

4-27

D8748H/D8749H
PORT 1/PORT 2 TIMING
2ND
I~.IPL --l- I· CYCLE
ALE
1

PSEN

I

P20-23
OUTPUT

PCH

NEW P20-23 DATA

P,?RT 20-23 DATA

-t--'------'--'------------7----.-!.--____

I

PCH

'-------~I

P24-27
P10-17
PORT 24-27, PORT 10-17 DATA
NEW PORT DATA
OUTPUT. -t---~-----------~-------f~-------~I---

--1

ILP

~
- 1 - - - - I L A - - - " + '..
"-IPL~

EXPANDER
PORT
OUTPUT

1 rp-O-R-T-20--2-3-D-A-TA-;'1

PCH

~

_ _ _ _ _ _ _- J

'I

r------,.
PCH

INPUT

~IDP

I"

I-ICA1

IIPD

I

"'" "'
OUTPUT DATA
I

I,

I
,

EXPANDER
PORT

I PORT CONTROL

.

IPR -----I"~I

I;)

Fl

PROG
210983-8

CRYSTAL OSCILLATOR MODE

CERAMIC RESONATOR MODE

C1

~
=-

~_-r-_----1_ _---j2 XTAL1

.

C2

L--.jl

I

:::;o~-::,::
II

11-11
c!:3HZ

T
I

31 XTA!..:!

C3

210983-9
Cl = S pF ±% pF + (STRAY < S pF)
C2 = (CRYSTAL + STRAY) < 8 pF
C3 = 20 pF ±1 pF (STRAY < S pF)

210983-10

Crystal series resistance should be less than 301l at 11 MHz; less
than 7SIl at 6 MHz; less than 1801l at 3.6 MHz.

4-28

inter

D8748H/D8749H

DRIVING FROM EXTERNAL SOURCE

WARNING
An attempt to program a missocketed 8749H
(8748H) will result in severe damage to the part. An
indication of a properly socketed part is the appearance of the ALE clock output. The lack of this clock
may be used to disable the programmer.

+5V
47011
2 XTAL1
)0-+----=-1

The ProgramlVerify sequence is:

47011

1) Voo = 5V, Clock applied or internal oscillator operating. RESET = OV, TEST 0 = 5V, EA = 5V,
BUS and PROG floating. P10 and P11 must be
.
.
tied to ground.

'-----'--,3;;-1 XTAL2

210983-11
For XTAL1 and XTAL2 define "high" as voltages above 1.6Vand
"low" as voltages below 1.6V. The duty cycle requirements for
externally driving XTAL1 and XTAL2 using the circuit shown
above are as follows: XTAL1 must be high 35-65% of the period
and XTAL2 must be high 36-65% of the period. Rise and fall
times must be faster than 20 ns.

2) Insert 8749H (8748H) in programming socket.
3) TEST 0

= OV (select program mode)

4) EA = 18V (activate program mode)
5) Address applied to BUS and P20-22

PROGRAMMING, VERIFYING AND
ERASING THE 8749H (8748H) EPROM

6) RESET = 5V (latch address)
7) Data applied to BUS
8) Voo = 21V (programming power)

Programming Verification

9) PROG = Vee or float followed by one 50 ms
pulse to 18V

In brief, the programming process consists of: activating the program mode, applying an address,
latching the address, applying data, and applying a
programming pulse. Each word is programmed completely before moving on to the next and is followed
by a verification step. The following is a list of the
pins used for programming and a description of their
functions:

Pin
XTAL 1
XTAL2
RESET
TEST 0
EA
BUS
P20-P22
Voo·
PROG

10) Voo = 5V
11) TEST 0 = 5V (verify mode)
12) Read and verify data on BUS
13) TEST 0 = OV
14) RESET = OV and repeat from step 5
15) Programmer should be at conditions of step 1
when 8749H (8748H) is removed from socket.

Function
Clock Input (3 to 4.0 MHz)
Initialization and Address Latching
Selection of Program or Verify Mode
Activation of ProgramlVerify Modes
Address and Data Input
Data Output During Verify
Address Input
Programming Power Supply
Program Pulse Input

4-29

D8748H/D8749H
A.C. TIMING SPECIFICATION FOR PROGRAMMING 8748H/8749H
TA= 25°C ±5°C; VCC = 5V ±5%; VOO = 21V ±0.5V
Symbol

Parameter

Min

t

tAW

Address Setup Time to RESET

tWA

Address Hold Time after RESET
Data in Setup Time to PROG

two

Data il"! Hold Time after PROG

tpH

RESET Hold Time to Verify

tvoow

Voo Hold Time before PROG

tVOOH

J..

Voo Hold Time after PROG

Unit

0

1.0

ms

0

1.0

ms

50

60

ms

4tCY
4tCY

J.. .

4tCY
4tCY

t

tpw

Program Pulse Width

tTW

TEST 0 Setup Time for Program Mode

4tCY

twr

TEST 0 Hold Time after Program Mode

4tCY

too

TEST 0 to Data Out Delay

tww

RESET Pulse Width to Latch Address

t r• tl

Voo and PROG Rise and Fall Times

0.5

100

/ks

tCY

CPU Operation Cycle Time

3.75

5

/ks

tRE

RESET Setup Time before EA

t

If TEST 0 is high, too can be triggered by RESET· t

.

..

NOTE:

Test Conditions

4tCY

t

t

tow

Max

4tCY·
4tCY

4tCY

D.C. SPECIFICATION FOR PROGRAMMING 8748H/8749H
TA = 25°C ±5°C; Vcc = 5V ±5%; Voo = 21V ±0.5V
Symbol

Parameter

Min

Max

Unit

VOOH

Voo Program Voltage High Level

20.5

21.5

V

VOOL

VOO Voltage Low Level

4.75

5.25

V

VPH

PROG Program Voltage High Level

17.5 .

18.5

V

VPL

PROG Voltage Low Level

4.0

Vcc

V

VEAH

EA Program or Verify Voltage High Level

17.5

100

VOO High Voltage Supply Current

18.5

V

20.0

mA

IpROG

PROG High Voltage Supply Current

1.0

mA

lEA

EA High Voltage Supply Current

1.0

mA

4-30

Test Conditions

intJ

D8748H/D8749H

WAVEFORMS
COMBINATION PROGRAM/VERIFY'MODE (EPROMs ONLY)
VEAH
EA

Vee __+_J
I-------PROGRAM-------t--VERIFY--t----PROGRAM-

TO

Vee
VIL1

Vee
RESET
VIL1

DBO-DB7

IAW+----r~+IWA

==>---

DATA TO BE
PROGRAMMED VALID

__ -{NEXT AODRX=
VALID

LAST
ADDRESS

NEXT
ADDRESS

tyDDW~r~~

V;:'DH

VDDL----------~~
PRoi:: _ _ _ - _______

I I ~-------------------------------:~EV__TI~:

__________________.
210983-12

VERIFY MODE

\~ __--J/
DBO-DB7

==>---

ADDRESS
(0-7) VALID

- -

____-J)('-____

A_D_D_RE_S_S_(_8-_9_)V_A_L_ID_ _ _

-<

\~-

X

NI:XT
,-_ _
A_DD_R...;.E",;S;,;;S_J

NEXT DATA)OUT VALID

~)(~_ _ _ _ _N_E_X_T_A_D_D_R_E_SS_V_A_L_ID_ __
210983-13

4·31

intJ

D8748H/D8749H

SUGGESTED EPROM VERIFICATION ALGORITHM FOR HMOS-E DEVICE ONLY
INITIAL.EPROM DUMP CYCLE
ALE
,(NOTE1)

SUBSEQUENT EPROM DUMP CYCLES
: (OUTPUT)

+18V

,
,
: (INPUT)
,,

I

EA-----.J

DB----I

ADDRESS

,I

H

L....--'("'"IN"'"P""UT=-)-..1

I
,,,

ROM DATA
(OUTPUT)

H

ADDRESS

,

(INPUT)

~-~------(OUTPUT):

I

, TO, RESET - - - - - - - - '

P20·P23

, (INPUT)

,,

---i.____A_D_D_R_ES_S_ _ _--4Hl__--=A::DD:R:E::S:S_'_~..t-----~-: (INPUT)

210983-14

A10
A11

48H

49B

o
o

ADDR

Vee = Vee = +5V
Vss = OV

o

NOTE:
ALE is function of X1. X2 inputs.

4-32

MCS®-48
EXPRESS

•

O°C to 70°C Operation

•

- 40°C to

•

168 Hr. Burn-In

+ 85°C Operation

•

8048AH/8035AHL

•

8748H

•

8049AH/8039AHL

•

8243

•

8050AH/8040AHL

•

8749H

The new Intel EXPRESS family of single-component 8-bit microcomputers offers enhanced processing options
to the familiar 8048AH/8035AHL. 8748H. 8049AH/8039AHL. 8749H. 8050AH/8040AHL Intel components.
These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. but fall short of military conditions.
The EXPRESS options include the commercial standard and -40·C to + 85°C operation with or without 168
±8 hours of dynamic burn-in at 125·C per MIL-STD-883. method 1015. Figure 1 summarizes the option
marking designators and package selections.
For a complete description of 8048AH/8035AHL. 8748H. 8049AH/8309AHL. 8749H. 8040AHL and 8050AH
features and operating characteristics, refer to the respective standard commercial grade data sheet. This
document highlights only the electrical specifications which differ from the respective commercial part.

I
I

Temp Range ·C

0-70

-40-+85

0-70

-40-+85

Burn In

OHrs

OHrs

168 Hrs

168 Hrs

P8048AH
D8048AH
D8748H
P8035AHL
D8035AHL
P8049AH
D8049AH
D8749H
P8039AHL
D8039AHL
P8050AH
D8050AH
P8040AHL
D8040AHL
P8243
D8243

TP8048AH
TD8048AH
TD8748H
TP8035AHL
TD8035AHL
TP8049AH
TD8049AH
TD8749AH
TP8039AHL
TD8039AHL
TP8050AH
TD8050AH
TP8040AHL
TD8040AHL
TP8243
TD8243

QP8048AH
QD8048AH
QD8748H
QP8035AHL
QD8035AHL
QP8049AH
QD8049AH
QD8749H
QP8039AHL
QD8039AHL
QP8050AH
QD8050AH
QP8040AHL
QD8040AHL
QP8243
QD8243

LP8048AH
LD8048AH
LD8748H
LP8035AHL
LD8035AHL
LP8049AH
LD8049AH
LD8749AH·
LP8039AHL
LD8039AHL
LP8050AH
LD8050AH
LP8040AHL
LD8040AHL

LD8243

• Commercial Grade
P Plastic Package
o Cerdip Package

4-33

September 1987
Order Number: 270225-002

MCS@·48 EXPRESS

Extended Temperature ElectrIcal Specification Deviations·

TP8048AH/TP8035AHL/LP8048AH/LP8035AHL
TD8048AH/TDB035AHL/LD8048AH/LD8035AHL

D.C. CHARACTERISTICS TA = -40·Cto +8S·C;Vee = Voo =
Symbol

Limits

Parameter
Min

VIH

Input High Voltage (All Except
XTAL1, XTAL2, RESEn

sv ±10%;Vss = OV

Typ

2.2

Unit

Test Conditions

Max
Vee

V

100

Voo Supply Current

4

8

rnA

100 + Icc

Total Supply Current

40

80

rnA

TP8049AH/TP8039AHL/LP8049AH/LP8039AHL
TD8049AH/TD8039AHL/LD8049AH/LD8039AHL

D.C. CHARACTERISTICS TA = -40·Cto +8S·C; Vee = Voo = SV ±10%; Vss = OV
Symbol

Limits

Parameter
Min

VIH

Input High Voltage (All Except
XTAL 1, )ITAL2, RESET)

Typ

2.2

Unit

Test Conditions

Max
Vee

V

100

Voo Supply Current

S

10

rnA

100 + Icc

Total Supply Current

SO

100

rnA

. TP8050AH/TP8040AHL/LP8050AHL/LP8040AHL
TD8050AH/TD8040AHL/LD8050AH/LD8040AHL

D.C. CHARACTERISTICS TA = -40·Cto +8S·C;Vee = Voo = 5V ±10%;Vss = OV
Symbol

Limits

Parameter
Min

VIH

Input High Voltage (All Except
XTAL1, XTAL2, RESEn

Typ

2.2

Unit
Max
Vee

V

100

Voo Supply Current

10

20

rnA

100 + Icc

Total Supply Current

7S

120

rnA

4-34

Test Conditions

MCS®-48 EXPRESS

Extended Temperature Electrical Specification Deviations'

TD8748H/LD8748H

D.C. CHARACTERISTICS TA = -40·Cto + 85·C; vee = voo = 5V ±10%;Vss = OV
Symbol

Limits

Parameter
Input High Voltage (All Except
XTAL1, XTAL2, RESET)

VIH
100

+

lee

Unit

Typ

Min
2.2

Total Supply Current

Test Conditions

Max

50

Vee

V

130

mA

TD8749H/LD8749H·

D.C. CHARACTERISTICS TA = -40·C to + 85·C; Vee = Voo = 5V ± 10%; Vss = OV
Symbol

Limits

Parameter
Input High Voltage (All Except
XTAL 1, XTAL2, RESET)

VIH
100

+ lee

Unit

Typ

Min
2.2

Total Supply Current

Test Conditions

Max

75

Vee

V

150

mA

TP8743/TD8243/LD8243

D.C. CHARACTERISTICS TA = -40·Cto + 85·C; Vee = 5V ±10%;Vss = OV
Symbol

limits

Parameter
Min

lee

. ..

Vee Supply Current

I
I

Typ
15

I
I
..

Unit
Max

• Refer to ind,v,dual commercIal grade data sheet for complete operatIng characteristIcs.

4-35

25

rnA

Test Conditions

MCS®-48 INDEX
8
8243 Expander, 2-4
8243 Port Characteristics, 2-5

A
Accumulator, 1-1
Addressing Beyond 2K, 2-1
Addressing External Data Memory, 2-4
ALE, 1-17,2-9
ALU, 1-1
Arithmetic Logic Unit, 1-1

I/O Expander Device (8243), 2-4
I/O Expansion, 2-4; 2-5
I/O Port Characteristics,.2-5
I/O Port Restore, 2-2
Instruction Decoder, 1-1
Instruction Fetch (External), 2-1
INT, 1-17
Interrupt, 1-5, 1-7
Interrupt Routines, 2-2
'Interrupt Timing, 1-7

M

Memory Bank Switch, 2-1
Memory Bank Switching, 2-8
Memory Expansion; 2-5
Multi-Chip Systems, 2-7

B
Bus, 1-5, 1-17, 2-9

c

o

Clock Circuits, 1-9
Conditional Branches, .1-6
Control Signals, 2-8
Counter, 1-7
Cycle Counter, 1-10

Oscillator, 1-9

p

Pin Description, 1-16
Port 1, 1-5, 1-17
Port 2, 1-5, 2-9
Port Characteristics, 2-9
Power Down, 1-13
PROG, 1-17,2-9
Program Counter, 1-5
Program Memory, 1-1
Program Status Word; i-6
Programming EPROM, 1-18
PSEN,2-9
PSW, 1-6

D

Data Memory, 1-3

E
EA, 1-15
Erasing EPROM, 1-18
Erasure Characteristics, 1-18
Event Counter, 1-9
Expansion of Data Memory, 2-3
Expansion of I/O, 2-4
Expansion of Program Memory, 2-1
Extended Addressing, 2-1
External Access Mode, 1-15
External Data Memory Addressing, 2-4
External Instruction Fetch, 2-1

R
RD, 1-17, 2-9
Read Cycle, 2-3
Reset, 1-10, 1-17
Restoring I/O Ports, 2-2

4-36

s

v

Single Step, 1-11, 1-14
Stack, 1-5
State Counter, 1-10
Sync Mode, 1-15

Vee, 1-17
VDD,I-17
Verifying EPROM, 1-18
VSS, 1-17

T

W

TO, 1-5, 1-17
TI, 1-5, 1-17
Test Inputs, 1-5
Timer, 1-7, 1-9
Timing, 1-13
Timing Circuits, 1-9

WR, 1-17,2-9
Write Cycle, 2-3

4-37

MCS® . . 51 Architectural
Overview

5

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ARCHITECTURAL OVERVIEW
OF THE MCS®-S1 FAMILY OF MICROCONTROLLERS
MEMBERS OF THE FAMILY
The MCS®-Sl family of microcontrollers consists of the devices listed in Table 1. The basic architectural structure of
these devices is shown in Figure 1.
.

i-------.

I

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EXTERNAL
INTERRUPTS

8K ROM
IN 8052

I
I
I

4K
ROM

1-------·

j-·------I

~~----l

(8052)
TIMER2

I

256 BYTES
RAM IN 8052

I

COUNTER
INPUTS

TIMER 1

128 BYTES
RAM

TIMER 0

TXD

RXD

ADDRESS/DATA
270251-1

Figure 1. Block Diagram of the 8051/8052AH
Table 1. The MCS®-51 Family of Microcontrollers
Device
Name

ROMless
Version

EPROM
Version

ROM
Bytes

RAM
Bytes

16-Bit
Timers

Ckt
Type

8051

8031

(8751)

4K

128

2

HMOS

8051AH

8031AH

8751H

4K

128

2

HMOS

8052AH

8032AH

8752BH

8K

256

3

HMOS

80C51BH

80C31BH

87C51

4K

128

2

CHMOS

83C51FA

80C51FA

87C51FA

8K

256

4

CHMOS

83C152

80C152

87C152

8K

256

2

CHMOS

5-1

intJ

MCS®·51 ARCHITECTURAL OVERVIEW

8051

80C51BH

The 8051 is the original member of the MCS-51 Family, and has been in production since 1981. Among the
features of the 8051 are:

The 80C51BH is the CHMOS verSion of the 8051.
Functionally, it is fully compatible with the 8051, but
being CMOS it draws less current than its HMOS
counterpart. To further exploit the power savings available in CMOS circuitry, two reduced power modes are
added:

• 8-bit CPU optimized for control applications
• Extensive Boolean processing (single-bit logic)
capabilities

• Software-invoked Idle Mode, during which the CPU
is turned off while the RAM and other. on-chip
peripherals continue operating. In this mode, current draw is reduced to about 15% of the current
drawn when the device is fully active.-

• 32 bidirectional and individually addressable I/O
lines
• 128 bytes of on-chip Data RAM
• Two 16-bit timer/counters
•
•
•
•
•
•

• Software-invoked Power Down Mode, during which
all on-chip activities are suspended. The on-chip
RAM continues to hold its data. In this mode the
device typically draws less than 10 p.A.

Full duplex UART
5-source interrupt structure with 2 priority levels
On-chip clock oscillator
4K bytes of on-chip Program Memory
64K Program Memory address space
64K Data Memory address space

Although the 80C51BH is functionally compatible with
its HMOS counterpart, specific differences between the
two types of devices must be considered in the design of
an application circuit if one wishes to ensure complete
interchangeability between the HMOS and .CHMOS
devices. These considerations are discussed in the Application Note AP-252, "Designing with the
8OC51BH".

The 8031 differs from the 8051 in not having the onchip Program ROM. Instead, the 8031 fetches all instructions from external memory.
The EPROM version of the 8051, the 8751, is no longer
in production. It has been superseded by the 8751H.

The ROMIess version of the 80C5IBH is the
80C3IBH. The EPROM version is the 87C51.

8051AH

83C51FA

The 8051AH is identical to the 8051, but is fabricated
with HMOS II technology. It is pin-for-pin compatible
with the 8051.

The 83C51FA is an enhanced version of the 80C51BH
and is backwards compatible with the 80C51BH. The
new features which have been incorporated are as follows:
• Programmable Counter Array with
Compare/Capture
High Speed Output
Pulse Width Modulator
Watchdog Timer

The ROMless version of the 8051AH is the 8031AH.
The EPROM version is the 8751H.

8052AH
~ The 8052AH is an enhanced 8051. It is fabricated with

• Programmable Serial Channel
Automatic Address Recognition
Framing Error Detection

HMOS II technology, and is backwards compatible
with the 8051. Its enhancements over the 8051 are as
follows:

•
•
•
•
•

• 256 bytes of on-chip Data RAM
• Three timer/counters
• 6-source interrupt structure
• 8K bytes of on-chip Program ROM
The ROMless version of the 8052AH is the 8032AH.
The EPROM version is the 8752BH.

Enhanced Power Down Mode
Up/down timer/counter
8 Kbytes of on-chip Program ROM
256 bytes of on-chip Data RAM
7-source interrupt structure

For further information on these new features, refer to
the "Hardware Description of the 83C51FA" chapter.

A separate product, the 8052AH-BASIC, is an
8052AH with a full BASIC interpreter in the on-chip
ROM. .

The ROMless version of the 83C51FA is the80c51FA.
The EPROM version is the 87C51FA.

5-2

inter

MCS®-51 ARCHITECTURAL OVERVIEW

________ _ DATA MEMORY __ ______ _

PROGRAM MEMORY
(READ ONLY)

'<~~2~~~T:t

.-----------------------FFFFH: ...---.,

FFFFH:
EXTERNAL

EXTERNAL

INTERNAL

FFH.tp-----,,
,,
"

EA=O

EXTERNAL

EA=1

INTERNAL

1-"""2:--'+- 0000 -+L-_ _..1

00

0000 L...,..---r...J

.--.--~------------------270251-2

Figure 2. MCS®·51 Memory Structure

The ROMless version of the 83ClS2 is the 80ClS2.
There is no EPROM version for the 83ClS2 but a version is offered which has an additional two ports which
can be connected to an EPROM for ROM development.

83C152
The 83C152 is an enhanced version of the 80CSIBH
and is 100% compatible with code written for the
80CSIBH. Some of the new features which have been
incorporated are:
• Global Serial Channel (GSC)A high speed serial communication link capable of
transmitting data in excess of 2 Mbps in either
HDLC or CSMA/CD protocols.
• Two DMA ChannelsEach DMA channel is capable of transferring
64 Kbytes of data. Options include: automatic ad·
dressing, automatic servicing of the GSC or UART,
alternate cycle transfers, and burst data transfers.
The source andlor destination can be internal
RAM, external RAM, or SFR memory space. Most
DMA transfers take 1 machine cycle to complete.
• Port 4-:The 83ClS2 has added an additional port called
port 4. Because of the added port, the 83ClS2 is
available in 48·pin DIP or 68·pin PLCC packages.
• 8 Kbytes of on-chip program ROM
• 2S6 bytes of on-chip data RAM
• 11 interrupt vectors

MEMORY ORGANIZATION IN
MCS®·51 DEVICES

Logical Separation of Program and
Data Memory
All MCS-Sl devices have separate address spaces for
Program and Data Memory, as shown in Figure 2. The
logical separation of Program and Data Memory allows
the Data Memory to be accessed by 8-bit addresses,
which can be more quickly stored and manipulated by
an 8-bit CPU. Nevertheless, 16-bit Data Memory addresses .can also be generated through the DPTR regis·
ter.
Program Memory can only be read, not written to.
There can be up to 64K bytes of Program Memory. In
the 80S1, 80S1AH,80C5IBH, and their EPROM versions, the lowest 4K bytes of Program Memory are on·
chip. The 80S2AH, 83CSIFA, and .83ClS2 provide 8
Kbytes of on-chip Program Memory storage. In the

For more information oli the 83ClS2 please refer to the
"Hardware Description" chapter on this product.

5-3

MCS®-51 ARCHITECTURAL OVERVIEW

ROMless versions all Program Memory is' external.
The read strobe for external Program Memory is the
signal PSEN (Program Store Enable).

The lowest 4K (or 8K, in the 8052AH, 83C51FA and
83CI5~) bytes of Program Memory can be either in the
on-chip ROM or in an external ROM. This selection is
made by strapping the EA (External Access) pin to
either Vee or Vss.

Data Memory occupies a separate address space from
Program Memory. Up to 64K bytes of external RAM
can be addressed in the external Data Memo~ace.
The CPU generates read and write signals, RD and
WR, as needed during external Data Memory accesses.

In the 8051 and its derivatives, if the EA pin is strapped
to Vco then program fetches' to addresses OOOOH
through OFFFH are directed to the internal ROM. Program fetches to addresses l000H through FFFFH are
directed to external ROM.

External Program Memory and external Data Memory
may be combined if desired by applying the RD and
PSEN signals to the inputs of an AND gate and using
the output of the gate as the read strobe to the external
Program/Data memory.

In the 8052AH and the other 8K ROM parts, EA =
Vee selects addresses OOOOH through lFFFH to be internal, and addresses 2000H through FFFFH to be externai.

Program Memory

If the EA pin is strapped to Vss, then all program
fetches are directed to external ROM. The ROMless
parts (8031, 8032AH, etc.) must have this pin externally strapped to Vss to enable them to execute from external Program Memory.

Figure 3 shows a map of the lower part ofthe Program
Memory. After reset, the CPU begins execution from
location OOOOH.
As shown in Figure 3, each interrupt is assigned a fixed
location in Program Memory. The interrupt causes the,
CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for
example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service routine must
begin at location 0003H. If the interrupt is not going to
be used, its service location is available as general purpose Program Memory.

The read strobe to external ROM, PSEN, is used for all
external program fetches. PSEN is not activated for internal program fetches.

EPROM

LATCH

P2~=====:;)f

(0033H)

INTERRUPT
LOCATIONS [

iJ

002BH

270251-4

0023H

Figure 4. Executing from External
Program Memory

00' BH

:::::=t

,

0003H

RESET ,

OOOOH

8

BYTES

The hardware configuration for external program execution is shown in Fignre 4. Note that 16 I/O lines
(Ports 0 and 2) are dedicated to bus functions during
external Program Memory fetches., Port 0 (pO in Figure
4) serves as a multiplexed' address/data bus. It emits
the low byte of the Program Counter (PCL) as an address, and then goes into a float state awaiting the arrival of the code byte from the Program Memory. During
the time that the low byte of the Program Counter is'
valid on PO, the signal ALE (Address Latch Enable)
clocks this byte into an address latch. Meanwhile, Port
2 (P2 in Figure 4) emits the high byte of the Program
Counter (pCR). Then PSEN strobes the EPROM and
'
the code byte is read into the microcontroller.

270251-3

Figure 3. MCS®-51 Program Memory

The interrupt service locations are spaced at 8--byte intervals: 0003H for External Interrupt 0, OOOBH for
Timer 0, OO13H for External Interrupt 1, 001BH for
Timer 1, etc. If an interrupt service routine is short
enough (as is often the case in control applications), it
can reside entirely within that 8-byte interval. Longer
service routines can use it jump instruction to skip over
subsequent interrupt locations, if other interrupts are in
use.
5-4

MCS®-51 ARCHITECTURAL OVERVIEW

Program Memory addresses are always 16 bits wide,
even though the actual amount of Program Memory
used may be less than 64K bytes. External program
execution sacrifices two of the 8-bit ports, PO and P2, to
the function of addressing the Program Memory.

Internal Data Memory is mapped in Figure 6. The
memory space is shown divided into three blocks,
which are generally referred to as the Lower 128, the
Upper 128, and SFR space.
Internal Data Memory addresses are always one byte
wide, which implies an address space of only 256 bytes.
However, the addressing modes for internal RAM can
in fact accommodate 384 bytes, using a simple trick.
Direct addresses higher than 7FH access one memory
space, and indirect addresses higher than 7FH access a
different memory space. Thus Figure 6 shows the Upper 128 and SFR space occupying the same block of
addresses, 80H through FFH, although they are physically separate entities.

Data Memory
The right half of Figure 2 shows the internal and external Data Memory spaces available to the MCS-51 user.
Figure 5 shows a hardware configuration for accessing
up to 2K bytes of external RAM. The CPU in this case
is executing from internal ROM. Port 0 serves as a
multiplexed address/data bus to the RAM, and 3 lines
of Port 2 are being used to page the RAM. The CPU
generates RD and WR signals as needed during external RAM accesses.

,...------./1

7FH

BANK
SELECT
BITS IN

DATA

2FH

PSW~

11{
10{
01 {
00 {

T-ADDRESSABLE SPACE
} BI
(B IT ADDRESSES 0-7F)
20H
lFH
18H
17H
10H
OFH
08H
07H
0

4 BANKS OF
8 REGISTERS
R0-R7

-

RESET VALUE OF
STACK POINTER

270251-7

Figure 7. The Lower 128 Bytes of Internal RAM

270251-5

Figure 5. Accessing External Data Memory.
If the Program Memory Is Internal, the Other
Bits of P2 are Available as 110.

The Lower 128 bytes of RAM are present in all
MeS-51 devices as mapped in Figure 7. The lowest 32
bytes are grouped into 4 banks of 8 registers. Program
instructions callout these registers as RO through R7.
Two bits in the Program Status Word (PSW) select
which register bank is in use. This allows more efficient
use of code space, since register instructions are shorter
than instructions that use direct addressing.

There can be up to 64K bytes of external Data Memory. External Data Memory addresses can be either 1 or
2 bytes wide. One-byte addresses are often used in conjunction with one or more other I/O lines to page the
RAM, as shown in Figure 5. Two-byte addresses can
also be used, in which case the high address byte is
emitted at Port 2.

FFH

FFHP--------r----., FFH
: ACCESSIBLE
ACCESSIBLE
UPPER I BY INDIRECT
BY DIRECT
128
I ADDRESSING
ADDRESSING
80H:
ONLY
80H
7FH ACCESSIBLE
LOWER
BY DIRECT
128
AND INDIRECT
ADDRESSING
OL-_ _- - '

~ SPECIAL

FUNCTION
REGISTERS

NO BIT-ADDRESSABLE
SPACES
AVAILABLE AS STACK
SPACE IN 8052AH.
83C51 FA. 83C152

} PORTS
STATUS AND
CONTROL BITS
TIMER
REGISTERS
STACK POINTER
ACCUMULATOR
(ETC.)

NOT IMPLEMENTED IN 8051

80H

270251-8

270251-6

Figure 8. The Upper 128 Bytes of Internal RAM

Figure 6. Internal Data Memory

5·5

inter

MCS®-51 ARCHITECTURAL OVERVIEW

I

CY

I

AC

I

Fa

I RSll RSO I

ov

Ip I

I

,J

L

PSW 7
CARRY FLAG RECEIVES CARRY OUT
FROM BIT 1 OF ALU OPERANDS

-

PSW 6i AUXILIARY CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERANDS
PSW 5
GENERAL PURPOSE STATUS FLAG

PSW 1
USER DEFINABLE FLAG

PSW 2
OVERFLOW FLAG SET BY
ARITHMETIC OPERATIONS

PSW 4
REGISTER BANK SELECT BIT 1

,

PSW 0
PARITY OF ACCUMULATOR SET
BY HARDWARE TO 1 IF IT CONTAINS
AN ODD NUMBER OF 1S, OTHERWISE
IT IS RESET TO 0

PSW 3
REGISTER BANK SELECT BIT 0

270251-10

Figure 10, PSW (Program Status Word) Register in MCS®·51 Devices

Sixteen addresses in SFR space are both byte- and bitaddressable. The bit-addressable SFRs are those whose
address ends in OOOB. The bit addresses in this area are
80H through FFH.

The next 16 bytes above the register banks form a block
of bit-addressable memory space. The MCS-51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this
area are OOH through 7FH.

THE MCS®·51 INSTRUCTION SET
All of the bytes in the Lower 128 can be accessed by
either direct or indirect addressing. The Upper 128
(Figure 8) can only be accessed by indirect addressing.
The Upper 128 bytes of RAM are not implemented in
the 8051, but are in the 8052AH, 83C51FA, and
83C152.

All members of the MCS-51 family execute the same
instruction set. The MCS-51 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal
RAM to facilitate byte operations on smaIl data structures. The instruction set provides extensive support for
one-bit variables as a separate data type, allowing direct
bit manipulation in control and logic systems that require Boolean processing.

Figure 9 gives a brief look at the Special Function Register (SFR) space. SFRs include the Port latches, timers, peripheral controls, etc. These registers can only be
accessed by direct addressing. In general, all MCS-51
microcontrollers have the same SFRs as the 8051, and
at the same addresses in SFR space. However, enhancements to the, 8051 have additional SFRs that are not
present in the 8051, nor perhaps in other proliferations
of the family.

rrH

,,

EOH

ACC

,
BOH

An overview of the MCS-51 instruction set is presented
below, with a brief description of how certain instructions might be used. References to "the assembler" in
this discussion are to Intel's MCS-51 Macro Assembler,
ASM51. More detailed information on the instruction
set can be found in the MCS-51 Macro Assembler User's Guide (Order No. 9800937 for ISIS Sysiems, Ordet
No. 122752 for DOS Systems).

REGISTER-MAPPED PORTS

Program Status Word

ADDRESSES THAT END IN
OH OR 8H ARE ALSO
BIT-ADDRESSABLE '

The Program Status Word (pSW) ,contains several
status bits that reflect the current state of the CPU. The
PSW, shown in Figure 10, resides in SFR space. It contains the Carry bit, the Auxiliary Carry (for BCD operations), the two register bank select bits, the Overflow
flag, a Parity bit, and two user-defmable status flags.

PORT 3

,
AOH

PORT 2

90H

PORT 1

-PORT PINS
-ACCUMULATOR
-PSW
'(ETC.)

The Carry bit, other than serving the functions of a
Carry bit in arithmetic operations, also serves as the
"Accumulator" for a number of Boolean operations.

I

SOH

PORT 0

270251-9

Figure 9. SFR Space

5-6

MCS®-51 ARCHITECTURAL OVERVIEW

The bits RSO and RSI are used to select one of the four
register banks shown in Figure 7. A number of instructions refer to these RAM locations as RO through R7.
The selection of which of the four banks is being referred to is made on the basis of the bits RSO and RS 1
at execution time.

IMMEDIATE CONSTANTS

The value of a constant can follow the opcode in Program Memory. For example,
MOV A, #100

The Parity bit reflects the number of Is in the Accumulator: P = 1 if the Accumulator contains an odd number of Is, and P = 0 if the Accumulator contains an
even number of Is. Thus the number of Is in the Accumulator plus P is always even.

loads the Accumulator with the decimal number 100.
The same number could be specified in hex digits as
64H.

Two bits in the PSW are uncommitted and may be used
as general purpose status flags.

Only Program Memory can be accessed with indexed
addressing, and it can only be read. This addressing
mode is intended for reading look-up tables in Program
Memory. A 16-bit base register (either DPTR or the
Program Counter) points to the base of the table, an.d
the Accumulator is set up with the table entry number.
The address of the table entry in Program Memory is
formed by adding the Accumulator data to the base
pointer.

INDEXED ADDRESSING

Addressing Modes
The addressing modes in the MCS-51 instruction set
are as follows:
DIRECT ADDRESSING

Another type of indexed addressing is used in the "case
jump" instruction. In this case the destination address
of a jump instruction is computed as the sum of the
base pointer and the Accumulator data.

In direct addressing the operand is specified by an 8-bit
address field in the instruction. Only internal Data
RAM and SFRs can be directly addressed.
INDIRECT ADDRESSING

Arithmetic Instructions

In indirect addressing the instruction specifies a register
which contains the address of the operand. Both internal and external RAM can be indirectly addressed.

The menu of arithmetic instructions is listed in Table 2.
The table indicates the addressing modes that can be
used with each instruction to access the  operand. For example, the ADD A,  instruction can
be written as:

The address register for 8-bit addresses can be RO or
RI of the selected register bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the
16-bit "data pointer" register, DPTR.

ADD
ADD
ADD
ADD

REGISTER INSTRUCTIONS

The register banks, containing registers RO through R7,
can be accessed by certain instructions which carry a
3-bit register specification within the opcode of the instruction. Instructions that access the registers this way
are code efficient, since this mode eliminates an address
byte. When the instruction is executed, one of the eight
registers in the selected bank is accessed. One of four
banks is selected at execution time by the two bank
seleCt bits in the PSW.

A,7FH
A,@RO
A,R7
A,#127

(direct addressing)
(indirect addressing)
(register addressing)
(immediate constant)

The execution times listed in Table 2 assume a 12 MHz
clock frequency. All of the arithmetic instructions execute in 1 ,""S except the INC DPTR instruction, which
takes 2 '""~, and the Multiply and Divide instructions,
which take 4 ,""s.
Note that any byte in the internal Data Memory space
can be incremented or decremented without going
through the Accumulator.
One of the INC instructions operates on the 16-bit
Data Pointer. The Data Pointer is used to generate
16-bit addresses for external memory, so being able to
increment.it in one 16-bit operation is a useful feature.

REGISTER-5PECIFIC INSTRUCTIONS

Some instructions are specific to a certain register. For
example, some instructions always operate on the Accumulator, or Data Pointer, etc., so no address byte is
needed to point to it. The opcode itself does that. Instructions that refer to the Accumlator as A assemble
as accumulator-specific opcodes.

The MUL AB instruction multiplies the Accumulator
by the data in the B register and puts the 16-bit product
into the concatenated B and Accumulator registers.
5-7

intJ

MCS®-51 ARCHITECTURAL OVERVIEW

Table 2. A Li~t of the MCS®-51 Arithmetic Instructions
Mnemonic

Olr

Addressing Modes
Ind

Reg

Imm

Execution
Time (/Ls)

Operation
A = A + 

X

X

X

X

1

ADDC A, < byte>

A = A +  + C

X

X

X

X

1

SUBB A, 

A = A -  - C

X

X

X

X

INC

A

A=A+1

INC



 =  + 1

ADD

A,

1

Accumulator only

X

X

1

X

1

INC

DPTR

DPTR = DPTR + 1

Data POinter only

2

DEC

A

A=A-1

Accumulator only

1

DEC



 =  - 1

MUL

AB

B:A = BxA

ACC and B only

DIV

AB

A = Int [AlB]
B = Mod [AlB]

ACC and B only

DA

A

Decimal Adjust

Accumulator only

X

The DIV AB instruction divides the Accumulator by
the data in the B register and leaves the 8-bit quotient
in the Accumulator, and the 8-bit remainder in the B
register.

X

X

1
4

4
1

completes the shift in 4 /Ls and leaves the B register
holding the bits that were shifted out.
The DA A instruction is for BCD arithmetic operations. In BCD arithmetic, ADD and ADDC instructions should always be followed by a DA A operation,
to ensure that the result is also in BCD. Note that DA
A will not convert a binary number to BCD. The DA
A operation produces a meaningful result only as the
second step in the addition of two BCD bytes.

Oddly enough, DIV AB finds less use in arithmetic
"divide" routines than in radix conversions and pro-·
grammable shift operations. An example of the use of
DIV AB in a radix conversion will be given later. In
shift operations, dividing a number by 2n shifts its n
bits to the right. Using DIV AB to perform the division

Table 3. A List of the MCS®-51 Logical Instructions
Mnemonic

Addressing Modes
Oir

Ind

Reg

Imm

Execution
Time (/Ls)

X

X

X

1

Operation

ANL

A,

A = A .AND. 

X

ANL
ANL

 ,A
,#data

 =  .AND. A
 =  .AND. #data

X
X
X

A, 
ORL  ,A
ORL  ,#data
XRL A,
XRL  ,A
XRL < byte> , # data
CRL A
CPL A
RL
A
RLC A
RR
A
RRC A
SWAP A
ORL

A _
1"\ -

A

'"'0

.......... .+ ...........

n .vn ........ uy ..' C '

 =  .OR. A

)(

 =  .OR. #data

X

A = A .XOR. 

X
X

 = .XOR.A

1
2

X

X

X

X

X

1

X

1
2
.1

Rotate Left through Carry

Accumulator only

Rotate ACC Right 1 bit
Rotate Right through Carry

Accumulator only·
Accumulator only

1
2
1
1
1
1
1
1

Swap Nibbles in A

Accumulator only.

1

 =  .XOR. #data
A = OOH
A = .NOT.A

X
Accumulator only
Accumulator only
Accumulatoronly

Rotate ACC Left 1 bit

5-8

..

inter

MCS®-51 ARCHITECTURAL OVERVIEW

The SWAP A instru.:;tion interchanges the high and
low nibbles within the Accumulator. This is a useful
operation in BCD manipulations. For example, if the
Accumulator contains a binary number which is known
to be less than 100, it can be quickly converted to BCD
by the following code:

Logical Instructions
Table 3 shows the list of MCS-51 logical instructions.
The instructions that perform Boolean operations
(AND, OR, Exclusive OR, NOT) on bytes perform the
operation on a bit-by-bit basis. That is, if the Accumulator contains OOllOlOlB and  contains
OlOlOOllB, then
ANL

B,#l0
AB
SWAP A
ADD A,B
MOY

DIY

A, 

will leave the Accumulator holding OOOlOOOlB.
Dividing the number by 10 leaves the tens digit in the
low nibble of the Accumulator, and the ones digit in the
B register. The SWAP and ADD instructions move the
tens digit to the high nibble of the Accumulator, and
the ones digit to the low nibble.,

The addressing modes that can be used to access the
 operand are listed in Table 3. Thus, the ANL
A,  instruction may take any of the forms
ANL
ANL
ANL
ANL

A,7FH
A,@RI
A,R6
A,#53H

(direct addressing)
(indirect addressing)
(register addressing)
(immediate constant)

Data Transfers
INTERNAL RAM

All of the logical instructions that are Accumulatorspecific execute in I/Ls (using a 12 MHz clock). The
others take 2 /Ls.

Table 4 shows the menu of instructions that are available for moving data around within the internal memory spaces, and the addressing modes that can be used,
with each one. With a 12 MHz dock, all of these instructions execute in either I or 2 /Ls.

Note that Boolean operations can be performed on any
byte in the internal Data Memory space without going
through the Accumulator. The XRL , #data
instruction, for example, offers a quick and easy way to
invert port bits, as in
XRL

The MOY ,  instruction allows data to
be transferred between any two internal RAM or SFR
locations without going through the Accumulator. Remember the Upper 128 byes of data RAM can be accessed only by indirect addressing, and SFR space only
by direct addressing.

PI,#OFFH

If the operation is in response to an interrupt, not using

the Accumulator saves the time and effort to stack it in
the service routine.

Note that in all MCS-51 devices, the stack resides in
on-chip RAM, and grows upwards. The PUSH instruction first increments the Stack Pointer (SP), then copies
the byte into the stack. PUSH and POP use only direct
'addressing to identify the byte being saved or restored,

,

The Rotate instructions (RL A, RLC A, etc.) shift the
Accumulator 1 bit to the left or right. For a left rotation, the MSB rolls into the LSB position. For a right
rotation, the LSB rolls into the MSB position.

Table 4. A List of the MCS®-S1 Data Transfer Instructions that Access Internal Data Memory Space
Mnemonic

Addressing Modes

Operation

Dir

-

Ind

Reg

Imm

Execution
Time (/Ls)

X

1

MOV

A, 

A"C 

X

X

X

MOV

,A

 = A

X

X

X

MOV

, 

 = 

X

X

X

MOV

DPTR,#data16

DPTR = 16-bit immediate constant.

PUSH 

INC SP: MOV "@SP",

X

POP



MOV , "@SP" : DEC SP

X

XCH

A, 

ACC and  exchange data

X

XCHD A,@Ri

ACC and @Ri exchange low nibbles

5-9

1
X

2

X

2
2
2

X
X

X

1
1

inter

MCS®-51 ARCHITECTURAL OVERVIEW

but the stack itself is accessed by indirect addressing
using the SP register. This means the stack can go into
the Upper 128, if they are implemented, but not into
SI:R space.

After the routine has been executed, the Accumulator
contains the two digits that were shifted out on the
right. Doing the routine with direct MOYs uses 14 code
bytes and 9 ,""S of execution time (assuming a 12 MHz
clock). The same operation with XCHs uses less code
and executes almost twice as fast.

The Upper 128 are not implemented in the 8051,
8051AH, or 8OC51BH, nor in their ROMless or
EPROM counterparts. With these devices, if the SP
points to the Upper 128, PUSHed bytes are lost, and
POPped bytes are indeterminate.

To right-shift by an odd number of digits, a one-digit
shift must be executed. Figure 12 shows a sample of
code that will right-shift a BCD number one digit, using the XCHD instruction. Again, the contents of the
registers holding the number and of the Accumulator
are shown alongside each instruction.

The Data Transfer instructions include a 16-bit MOY
that can be used to initialize the Data Pointer (DPTR)
for look-up tables in Program Memory, or for 16-bit
external Data Memory accesses.

MOV R1.#2EH
MOV RO.#2DH
loop for R1 = 2EH:
LOOP: MOV A.@R1
00 12 34 56 78 78
XCHD A.@RO
00 12 34 58 7876
SWAP A
00 12 34 58 78 67
MOV @R1;A
00 12 34 58 67 67
DEC R1
00 12 34 58, 67 67
DEC RO
00 12 34 58 67 67
CJNE R1.#2AH.LOOP
loop for R1 = 2DH:
00112138145167145
loop for R1 = 2CH:
100 18 23 45 67 23
loop for R1 = 28H:
08 01 23 45 67 01
CLR A
081 01 1231451671 00
00 01 23 45 67 08
XCH A.2AH

The XCH A, , instruction causes the Accumulator and addressed byte to exchange data. The XCHD
A,@Ri instruction is similar, but only the low nibbles
are involved in the exchange.
To see how XCH and XCHD can be used to facilitate
data manipulations, consider first the problem of shifting an 8-digit BCD number two digits to the right. Figure 11 shows how this can be done using direct MOYs,
and for comparison how it can be done using XCH
instructions. To aid in understanding how the code
works, the contents of the registers that are holding the
BCD number and the content of the Accumulator are
shown alongside each instruction to indicate their
status after the instruction has been executed.
2A 28 2C
MOV A,2EH
00 12 34
MOV 2EH,2DH 00 12 34
MOV 2DH,2CH 00 12 34
MOV 2CH,28H 00 12 12
MOV 28H,#0
00 00 12
(a) Using direct MOVs: 14 bytes, 9 p.s

20
56
56
34
34
34

2E
78
56
56
56
56

I

Figure 12. Shifting a BCD Number
One Digit to the Right

ACC
78
78
78
78
78

First, pointers Rl and RO are set up to point to the two
bytes containing the last four BCD digits. Then a loop
is executed which leaves the last byte, location 2EH.
holding the last two digits of the shifted nuthber. The
pointers are decremented, and the loop is repeated for
location 2DH. The CJNE instruction (Compare and
Jump if Not Equal) is a loop control that will be described later.

I 2A I 28 I 2C I 20 I 2E I ACC

CLR
XCH

A

I 00 112 1 34 1 56

A.2BH I 00
A.2CH
00 I 00
00 1 34
12

1

78

I

55 1 78
78 I
56

XCH
XCH A.2DH
00
00
12 1 34
XCH A.2EH
00
00
12
34
(b) Using XCHs: 9 bytes. 5 p.s

78
56

00
12

34
56
78

The loop is executed from LOOP to CJNE for Rl =
2EH, 2DH, 2CH and 2BH. At that point the digit that
was originally shifted out on the right has propagated
to location 2AH. Since that location should be left with
Os, the lost digit is moved to the Accumulator.

Figure 11. Shifting a BCD Number
Two Digits to the Right

5-10

MCS®-51 ARCHITECTURAL OVERVIEW

Table 6. The MCS®-51 Lookup
Table Read Instructions

EXTERNAL RAM

Table 5 shows a list of the Data Transfer instructions
that access external Data Memory. Only indirect addressing can be used. The choice is whether to use a
one-byte address, @Ri, where Ri can be either RO or
Rl of the selected register bank, or a two-byte address,
@DPTR. The disadvantage to using l6-bit addresses if
only a few K bytes of external RAM are involved is
that l6-bit addresses use all 8 bits of Port 2 as address
bus. On the other hand, 8-bit addresses allow one to
address a few K bytes of RAM, as shown in Figure 5,
without having to sacrifice all of Port 2.
All of these instructions execute in 2 /Ls, with a
12 MHz clock.
Table 5. A List of the MCS®-51 Data
Transfer Instructions that Access
External Data Memory Space
Address
Width

Mnemonic

Operation

Execution
Time (ILS)

8 bits

MOVXA,@Ri

Read external
RAM@Ri

2

8 bits

MOVX@Ri,A

Write external
RAM@Ri

2

16 bits

MOVX A,@DPTR

Read external
RAM@DPTR

2

16 bits

MOVX @DPTR,A

Write external
RAM@DPTR

2

Mnemonic

Operation

Execution
Time (ILS)

MOVC

A,@A+DPTR

Read Pgm Memory
aI(A+DPTR)

2

MOVC

A,@A+PC

Read Pgm Memory
at (A+PC)

2

The first MOVC instruction in Table 6 can accommodate a fable of up to 256 entries, numbered 0 through
255. The number of the desired entry is loaded into the
Accumulator, and the Data Pointer is set up to point to
beginning of the table. Then
MOVC

A,@A+DPTR

copies the desired table entry into the Accumulator.
The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table
base, and the table is accessed through a subroutine.
First the number of the desired entry is loaded into the
Accumulator, and the subroutine is called:
MOV
CALL

A,ENTRY_NUMBER
TABLE

The subroutine "TABLE" would look like this:
TABLE:

Note that in all external Data RAM accesses, the Accumulator is always either the destination or source of
the data.

MOVC
RET

A,@A + PC

The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
have up to 255 entries, numbered 1 through 255. Number 0 can not be used, because at the time the MOVC
instruction is executed, the PC contains the address of
the RET instruction. An entry numbered 0 would be
the RET opcode itself.

The read and write strobes to external RAM are activated only during the execution of a MOVX instruction. Normally these signals are inactiye, and in fact if
they're not going to be used at all, their pins are available as extra 110 lines. More about that later.
LOOKUP TABLES

Boolean Instructions

Table 6 shows the two instructions that are available
for reading lookup tables in Program Memory. Since
thesC1 instructions access only Program Memory, the
lookup tables can only be read, not updated. The mnemonic is MOVC for "move constant".

MCS-51 devices contain a complete Boolean (single-bit)
processor. The internal RAM contains 128 addressable
bits, and the SFR space can support up to 128 other
addressable bits. AIl of the port lines are bit-addressable, and each one can be, treated as a separate singlebit port. The instructions that access these bits are not
just conditional branches, but a complete menu of
move, set, clear, complement, OR, and AND instructions. These kinds of bit operations are not easily obtained in other architectures with any amount of byteoriented software.

'If the table access is to external Program Memory, then
the read strobe is PSEN.

5-11

MCS®-51 ARCHITECTURAL OVERVIEW

Note that the Boolean instruction set includes ANL
and ORL operations, but not the XRL (Exclusive OR)
operation. An XRL operation is simple to implement in
software. Suppose, for example, it is required to form
the Exclusive OR of two bits:

Table 7. A List of the MCS®-S1
Boolean Instructions
Mnemonic

Operation

ANL

C,bit

C = C .AND. bit

ANL

C,/bit

C = C .AND .. NOT. bit

ORL

C,bit

C = C.OR. bit

ORL

C,/bit

C = C .OR. .NOT. bit

MOV

C,bit

C = bit

Execution
Time (,....s)

MOV

bit,C

bit = C

2
2
2
2
'1
2

CLR

C

C=O

1

CLR

bit

bit = 0

1

C=1

1

SETS C
SETS bit

bit = 1

1

CPL

C

C = .NOT.C

1

CPL

bit

bit = .NOT. bit

1

JC

rei

JumpifC

=1

JNC

rei

JumpifC = 0

JB

bit,rel

Jump if bit

JNS

bit, rei

Jump if bit

JSC

bit,rel

Jump if bit

2
2
2
2
2

=1
=0
= 1; CLR bit

C = bit! .xRL. bit2
The software to do that could be as follows: C,bitl
MOV
bit2,OVER
JNB
CPL
C
OVER: (continue)
First, bit! is moved to the Carry. If bit2 = 0, then _C
now contains the correct result. That is, bit! .xRL. bit2
= bit! if bit2 = O. On the other hand, if bit2 = 1 C
now contains the complement of the correct result. I(
need only be inverted (CPL C) to complete the operation;
This code uses the JNB instruction, one of -a series of
bit-test instructions which execute a jump if the addressed bit is set (JC, JB, JBC) or if the addressed bit is
not set (JNC, JNB). In the above case, bit2 is being
tested, and if bit2 = 0 the CPL C instruction is jumped
over.
JBC executes the jump if the addressed bit is set, and
also clears the bit. Thus a flag can be tested and cleared
in one operation.

The instruction set for the Boolean processor is shown
in Table 7. All bit accesses are by direct addressing. Bit
addresses OOH through 7FH are in the Lower 128, and
bit addresses 80H through FFH are in SFR space.

All the PSW bits are directly addressable, so the Parity
bit, or the general purpose flags, for example, are also
available to the bit-test instructions.

Note how easily an internal flag can be moved to a port
pin:
MOV
MOV

RELATIVE OFFSET

C,FLAG
P1.0,C

The destination address for these jumps is specified to
the assembler by a label or by an actual address in
Program Memory.' However, the destination address
aSSembleS to a relative offSet byte. This is a signed
(two's complement) offset byte which is added to the
PC in two's complement arithmetic if the jump is executed.

In this example, FLAG is the name of any addressable
bit in the Lower 128 or SFR space. An 110 line (the
LSB of Port 1, in this case) is set or cleared depending
on whether the flag bit is 1 or O.
The Carry bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instructions that
refer to the Carry bit as C assemble as Carrycspecific
instructions (CLR C, etc). The Carry bit also has a
direct address, since it resides in the PSW register,
which is bit-addressable.

The range of the jump is therefore -128 to + 127 Program Memory bytes relative to the first byte following
the instruction.

5-12

intJ

MCS®-51 ARCHITECTURAL OVERVIEW

the Accumulator. Typically, DPTR is set up with the
address of a jump table, and the Accumulator is given
an index to the table. In a 5-way branch, for example,
an integer 0 through 4 is loaded into the Accumulator.
The code to be executed might be as follows:

Jump Instructions
Table 8 shows the list of unconditional jumps.
Table 8. Unconditional Jumps
in MCS®-S1 Devices

Mnemonic

Operation

Jump to addr
JMP addr
JMP @A+DPTR Jump to A+ DPTR
CALL addr
Call subroutine at addr
RET
Return from subroutine
RETI
Return from interrupt
No operation
NOP

MOY
MOY

Execution
Time (p.s)

RL
, JMP

2

DPTR,#JUMP_TABLE
A,INDE~NUMBER

A

@A+DPTR

2

The RL A instruction converts the index number (0
through 4) to an even number on the range 0 through 8,
because each entry in the jump table is 2 bytes long:

2
2
2

JUMP_TABLE:
AJMP
AJMP
AJMP
AJMP
AJMP

1

The Table lists a single "JMP addr" instruction, but in
fact there are three-SJMP, UMP and AJMP-which
differ in the format of the destination address. JMP is a
generic mnemonic which can be used if the programmer does not care which way the jump is encoded.

CASE_O
CASE_I
CASE~

CASE..;...3
CASE_4

Table 8 shows a single "CALL addr" instruction, but
there are two of them-LCALL and ACALL-which
differ in the format in which the subroutine address is
given to the CPU. CALL is a generic mnemoni~ which
can be used ifthe programmer does not care which way
the address is encoded.

The SJMP instruction encodes the destination address
as a relative offset, as described above. The instruction
is 2 bytes long, consisting of the opcode and the relative
offset byte. The jump distance is limited to a range of
-128 to + 127 bytes relative to the instruction following the SJMP.

The LCALL instruction uses the 16-bit address format,
and the subroutine can be anywhere in the 64K Program Memory space. The ACALL'instruction uses the
II-bit format, and the subroutine must be in the same
2K block as the instruction following the ACALL.

The UMP instruction encodes the destination address
as a 16-bit constant. The instruction' is 3 bytes long,
consisting of the opcode and two address bytes. The
destination address can be anywhere in the 64K Program Memory space.

In any case the programmer specifies the subroutine
address to the assembler in the same way: as a label or
as a 16-bit constant. The assembler will put the address
into the correct forinat for the given instructions.

The AJMP instruction encodes the destination address
as an ll-bit constant. The instruction is 2 bytes long,
consisting of the opcode, which itself contains 3 of the
II address bits, followed by another byte containing the
low 8 bits of the destination address. When the instruction is executed, these II bits are simply substituted for
the low II bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same 2K
block as the instruction following the AJMP.

Subroutines should end with a RET instruction, which'
returns execution to the instruction following the
CALL.
RETI is' used to return from an interrupt service routine. The only difference between RET and RETI is
that RET! tells the interrupt control system that the
interrupt in progress is done. If there is no interrupt in
progress at the time RETI is executed, then the RET!
is functionally identical to RET.

In all cases the programmer specifies the destination
address to the assembler in the same way: as a label or
as a 16-bit constant. The assembler will put the destination address into the correct format for the given instruction. If the format required by the instru, ,rei

Decrement and jump if not zero

CJNE A, < byte> ,rei

Jump if A"* 

CJNE < byte> , # data,rel

Jump if  "* #data

X
X

Execution
Time (,...s)

Imm

2
2
2
2
2

X
X
X

X

There is no Zero bit in the PSW. The, JZ and JNZ
instructions test the Accumulator data for that condition.

Ill>
IICS -51
HIIOS
OR CHIIOS
.....-t---jXTAL2

The DJNZ instruction (Decrement and Jump if Not
Zero) is for loop control. To execute a loop N times,
load a counter byte with N and terminate the loop with
a DJNZ to the beginning, of the loop, as shown below
for N = 10:

QUA~~ ~~~~~ '

....

RESONATOR

'--~-+-I XTAL 1
VSS

-= '-----...,J
270251-11

MOY
COUNTER,# 10
LOOP: (begin loop)

Figure 13. Using the On-Chip OSCillator

•

Ill>

(end loop)
DJNZ
COUNTER,LOOP
(continue)

IICS -51
HIIOS
OR CHIIOS

XTAL2

The CJNE instruction (Compare and Jump if Not
Equal) can also be used for loop control as in Figure 12.
Two bytes are speCified in the operand field of the instruction. The jump is 'executed only if the two bytes
are not equal. In the example of Figure 12, the two
bytes were the data in RI and the constant 2AH. The
initial data in RI was 2EH. Every time the loop was
executed, RI was decremented, and the looping was to
continue until the RI data reached 2AH. '

EXTERNAL
CLOCK
SIGNAL

XTAL1
VSS

270251-12

A. HMOS or CHMOS

EXTERNAL

~

, CLOCK
SIGNAL,

Another application of this instruction is in "greater
than, less than" comparisons. The two bytes in the operand fieid are iaken as unsigned iniegers. If the first is
less than the second, then the Carry bit is se~ (I). If the
frrst is greater than or equal to the second, then the
Carry bit is cleared.

IICS":.'51
HIIOS
ONLY
XTAL2

270251-13

B.HMOSOnly

CPU TIMING

Ill>

All MCS-51 microcontrollers have an on-chip oscillator
which can be used, if desired as the clock source for the ,
CPU. To use the on-chip oscillator, connect a crystal or
ceramic resonator between the XTALl and XTAL2
pins of the microcontroller, and Capacitors to ground as
shown in Figure 13.

IICS -51
CHIIOS
ONLY
(NC)

XTAL2

EXTERNAL
CLOCK
SIGNAL

XTAL1
VSS

,270251-14

C. CHMOS Only
Figure 14. Using an External Clock
5-14

inter

MCS®~51

ARCHITECTURAL OVERVIEW

Examples of how to drive the clock with an external
oscillator are shown in Figure 14. Note that in the
HMOS devices (8051, etc.) the signal at the XTAL2 pin
actually drives the internal clock generator. In the
CHMOS devices (80C51BH, etc.) the signal at the
XTALl pin drives the internal clock generator. If only
one pin is going to be driven with the external oscillator
signal, make sure it is the right pin.

Machine Cycles
A machine cycle consists' of a sequence of 6 states,
numbered SI through S6. Each state time lasts for two
oscillator periods. Thus a machine cycle takes 12 oscil-'
lator periods or 1 JLs if the oscillator frequency is
12 MHz.
Each state is divided into a Phase 1 half and a'Phase 2
half. Figure 15 shows the fetch/execute sequences in

The internal clock generator defines the sequence of
states that make up the MCS-51 machine cycle.

OSC.
(XTAL2)

I

Sl

1 S21 S3

I I
54

S5

1 56 1 Sl

I I
S2

53

1 54

I I
55

S6

1

Sl

1

~~~~~~~~~~~~~~~~~~~~~~~~~~

ALE

_[

-- - - - -

______

_R:~D NEXT OPCODE AGAI,!,

.----I~--r---r-..L.-._-,r---,
~~_-L_~_~~~~

(A) 1-byle. 1-cyclelnstruc"on. e.g., INC A.

I

I

READ OPCODE.

I
:

_

[_R:~D NEXT OPCODE.

--------~~-~-_r~.--r_~
________

L-:..:.....J--=:......L.~-'-

_

_'___'----j

(8) 2-byte, 1-cycle Instruction, e.g" ADD A, #data

READ OPCODE.
READ NEXT
OPCODE (DISCARD),

(C) 1-byle, 2-cyclolnatuctlon, •.g.,.INC DPTR.
READ NEXT OPCODE AGAIN.

READOPCODE
(MOYX).

. NO
NO FETCH,

l

______

D
I

I

L-~_~_~_~~~~

_

_'__

I
I ____ _

_'___~~--~--~------

DATA
(D) MOYX (l-byle, 2-cycle)
ACCESS EXTERNAL MEMORY

270251-15

Figure 15. State Sequences in MCS®-51 Devices
5-15

intJ

MCS®·51 ARCHITECTURAL OVERVIEW

states and phases for various kinds of instructions. Normally two program fetches are generated during each
machine cycle, even if the instruction being executed
doesn't require it. If the instruction being executed
doesn't need more code bytes, the CPU simply ignores
the extra fetch, and the Program Counter is not incremented.

The fetch/execute sequences are the same whether the
Program Memory is internal or external ,to the chip.
Execution· times do not depend on whether the Program Memory is internal or external.
Figure 16 shows the signals an~ timing involved in program fetches when the Program Memory is external. If
Program Memory is external, then the Program Memory read strobe PSEN is normally activated twice per
machine cycle, as shown in Figure 16(A).

Execution of a one-cycle instruction (Figure l5A and
B) begins during State 1 ofthe machine cycle, when the
opcode is latched into the Instruction Register. A second fetch occurs during S4 of the same machine cycle.
Execution is complete at the end of State 6 of this machine cycle.

If an access to external Data Memory occurs, as shown
in. Figure 16(B), two PSENs are skipped, because the
address and data bus are being used for the Data Memory access.

The MOVX instructions take two machine cycles to
execute. No program fetch is generated during the second cycle of a MOVX instruction. This is the only time
program fetches are skipped. The fetch/execute sequence for MOVX instructions is shown in Figure
15(D).

Note that a Data Memory bus cycle takes twice as
much time as a Program Memory bus cycle. Figure 16
shows the relative timing of the addresses being emitted
at Ports'O and 2, and of ALE and PSEN. ALE is used
to latch the low address byte from PO into the address
latch.

ALE

PsEN

AD

-------+----------~---------4----------~----~----~--PCHOUT

X

PCHOUT

X

PCHOUT

(A)

WITHOUT A
MOVX.

X

PCHOUT

PO

,

I
I

I

tPCLOUT
VALID

bCLouT
VALID

lpCLOUT
VALID

CYCLE 1

I

I

-------"""1.------,

1~lulas

CYCLE 2,

lpCLOUT
VALID

.

"'

~1~1~1~lulasl~1

ALE

PSEN

AD

-------+-----------l-----,

(8)

WITH A
MOVX.

270251-16

Figure 16. Bus Cycles In MCS@·51 Devices Executing from External

5-16

Pr~gram

Memory

inter

MCS®-S1 ARCHITECTURAL OVERVIEW

When the CPU is executing from internal Program
Memory, PSEN is not activated, and program addresses are not emitted. However, ALE continues to be activated twice per machine cycle and so is available as a
clock output signal. Note, however, that one ALE is
skipped during the execution of the MOVX instruction.

named IE (Interrupt Enable). This register also contains a global disable bit, which can be cleared to disable all interrupts at once. Figure 17 shows the IE register for the 8052AH.
INTERRUPT PRIORITIES

Each interrupt source can also be individually programmed to one of two priority levels by setting or
cl~aring a bit in the SFR named IP (Interrupt Priority).
Figure 18 shows the IP register in the 8052AH.

Interrupt Structure
The 8051, 8051AH, and 80C51BH, and their ROMless
and EPROM versions, provide 5 interrupt sources: 2
external interrupts, 2 timer interrupts, and the serial
p.ort i!lterrupt. The 8052AH provides these 5 plus a
Sixth mterrupt that is associated with the third timer!
counter which is present in this device. Additional interrupts are available on the 83C51FA and 83C152.
Refer to the appropriate chapters on these devices for
further information on their interrupts.

A low-priority interrrupt can be interrupted by a highpriority interrupt, but not by another low-priority inter- '
rupt. A high-priority interrupt can't be interrupted by
any other interrupt source.
If two interrupt requests of different priority levels are
received simultaneously, the request of higher priority
level is serviced. Ifinte~rupt requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. Thus
within each priority level there is a second priority
structure determined by the polling sequence.

What follows is an overview of the interrupt structure
for these devices. More detailed information for specific
members .of the MCS-51 family is provided in the chapters of thiS handbook that describe the specific devices.

Figure 19 shows, for the 8052AH, how the IE and IP
registers and the polling sequence work to determine
which if any interrupt will be serviced.

INTERRUPT ENABLES

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the SFR
(MSB)

(MSB)

(LSB)

Symbol
EA

Position
IE.7

ET2

IE.6'
IE5

ES

lEA

ETI

IE.3

EXI

IE.2

ETO

lEI

EXO

lEO

(LSB)

I-I -I PT2 I PS I PTt I PXl I PTO I PXO I

IEA I-I ET2 I ES I ETI I EXI I ETO I EXO I
Function
disables all interrupts. If EA = O. no
interrupt will be acknowledged. If EA
=
1. each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
reserved
enables or disables the Timer 2
overflow or capture interrupt. If ET2
= O. the Timer 2 interrupt is disabled.
enables m disables the Serial Port
interrupt. If ES = 0, the Serial Port
interrupt is disabled.
enables or disables the Timer 1
Overflow interrupt. If ETI = O. the
Timer 1 interrupt is disabled.
enables or disables External Interrupt
1. If EXI = 0, Exlernal Interrupt t is
disabled.
enables or disables the Timer 0
Overflow interrupt If ETO = O. the
Timer 0 interrupt is disabled.
enables or disables Exlernal Interrupt
O. If EXO = 0, Exlernal Interrupt 0 is
disabled.

Symbol

Position

PT2

IP.7
IP.6
IP.5

PS

IP.4

PTt

IP.3

PXl

IP.2

, PTO

IP.l

PXO

IP.O

Function
reserved
reserved
defines the Timer 2 interrupt priority
level. PT2 = 1 programs it to the
higher priority level.
defines the Serial Port interrupt
priority level. PS = 1 programs it to
the higher priority level.
defines the Timer 1 interrupt priority
level. PTI = 1 programs it to the
higher priority level.
defines the Exlernai Interrupt 1
priority level. pxi = t programs it to
the higher priority level.
defines the Timer 0 interrupt priority
level. PTO = 1 programs it to the
higher priority level.
defines the Exlernal Interrupt 0
priority level. PXO = 1 programs it to
the higher priority level.

Figure 18. IP(lnterrupt Priority)
Register in the 8052AH

Figure 17. IE (Interrupt Enable)
Register In the 8052AH

5-17

inter

MCS@·51 ARCHITECTURAL OVERVIEW

HIGH PRIORITY
INTERRUPT

IP REGISTER

I
I
I
I

T F O - - - - -......t-CI""

~>t-I-<>-~_l_--+-+I

INTERRUPT
POLLING
SEQUENCE

I

I
I

O-o%c>t--r~-I--++I
I
I
I
I

*'"""0' ~>t--jO-c,..-l---41

T f 1 - - - - - -.......

I

I
I

I

RI
TI

Tf2
EXf2

").---"*-0'

~>t--r~-l--W

(8052 ONLY)

INDIVIDUAL
ENABLES

LOW PRIORITY
INTERRUPT

GLOBAL
DISABLE

270251-17

Figure 19. 8052 Interrupt Control System

pleted in less time than it takes other architectures to
commence them.

In operation, all the interrupt flags are latched into the
interrupt control system during State 5 of every machine cycle. Th~ samples are polled during ~he follo~­
ing machine cycle. If the flag for an enabled mterrupt IS
found to be set (I), the interrupt system generates an
LCALL to the appropriate location in Program Memory, unless some other condition blocks the interrupt.
Several conditions can block an interrupt, among them
that an interrupt of equal or higher priority level is
already in progress. I

SIMULATING A THIRD PRIORITY LEVEL IN
SOFTWARE

Some appli~ations require more than the two priority
levels that are provided by on-chip hardware in
MCS-SI devices. In these cases, relatively simple soft-:
ware can be written to produce the same effect as a
third priority leveL

The hardware-generated LCALL causes the contents of
the Program Counter to be pushed onto the stack, a~d
reloads the PC with the beginning address of the service
routine. As previously noted (Figure 3), the service rou-.
tine for each interrupt begins at a fixed location.

First, interrupts that are to have higher priority ~ha~ 1
are assigned to priority 1 in the IP (Interrupt Pnonty)
register. The service routines for priority 1 interrupts
that are supposed" to be interruptible by "priority 2"
interrupts are written to include the following code:

Only the Program Counter is automatically pushed
onto the stack, not the PSW or any other register. Havingonly the PC be automatically saved allows the p~o­
grammer to deCide how much time to spend savmg
which other registers. This enhances the interrupt response time, albeit at the expense of increasing the programmer's burden of responsibility. As a result, many
interrupt functions that are typical in control applications--':'toggling a port pin, for example, or reloading a
timer, or unloading a serial buffer--can often be com-

PUSH
IE
MOV
IE,#MASK
CALL . LABEL
._ •••• *
(execute service routine)

•••••••

POP
RET
LABEL: RET!
5-18

IE

MCS®-51 ARCHITECTURAL OVERVIEW

As soon as any priority 1 interrupt is acknowledged,
the IE (Interrupt Enable) register is re-defined so as to
disable all but "priority 2" interrupts. Then, a CALL to
LABEL executes the RETI instruction, which clears
the priority 1 interrupt-in-progress flip-flop. At this
point any priority 1 interrupt that is enabled can be
serviced, but only "priority 2" interrupts are enabled.

POPping IE restores the original enable byte. Then a
normal RET (rather than another RET!) is used to
terminate the service routine. The additional software
adds 10 ,...S ~at 12 MHz) to priority 1 interrupts.

5-19

Hardware Description of the
8051,8052 and 80e51

6

intJ

HARDWARE DESCRIPTION
OF THE 8051, 8052 AND 80C51
• The EPROM versions of the 80SIAH, 80S2AH,
and 80CSIBH

INTRODUCTION
This chapter presents a comprehensive description of
the on-chip hardware features of the MCS®-SI microcontrollers. Included in this description are

The devices under consideration are listed in Table 1.
As it becomes unwieldy to be constantly referring to
"each of these devices by their individual names, we will
adopt a convention of referring to them generically as
80S Is and 80S2s, unless a specific member of the group
is being referred to, in which case it will be specifically
named. The "80S Is" include the 8051, 8051AH, and"
80CSlBH, and their ROMless and EPROM versions.
The "80S2s" are the 80S2AH, 8032AH, and 87S2BH.

• The port drivers and how they function both as
ports and, for Ports 0 and 2, in bus operations
• The Timer/Counters
• The Serial Interface
• The Interrupt System
• Reset
• The Reduced Power Modes in the CHMOS devices

Figure I shows a functional block diagram of the 80SIs
and 8052s.

Table 1. The MCS-51 Family of Microcontrollers
Device
Name
8051
8051AH
8052AH
80C51BH

ROM less
Version
8031 "
8031AH
8032AH
80C31BH

EPROM
Version

ROM
Bytes

RAM
Bytes

16-bit
Timers

Ckt
Type

(8751)
8751H
8752BH
87C51

4K
4K
8K
4K

128
128
256
128

2
2
3
2

HMOS
HMOS
HMOS
CHMOS

SpeCial Function Registers
/

A map of the on-chip memory area called SFR (Special Function Register) space is shown in Figure 2. SFRs marked
by parentheses are resident in the 8052s but not in the 80S Is.

,--------

~

r

....

..

AU;

·R ....... lnIQUJID32on1'.

270252-1

Figure 1. MCS-51 Architectural Block Diagram
6-1

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51
8 Bytes
F8

FO

FF

B

F7

EF

E8

EO

ACC

E7

OF

08

DO

C8

co
B8

BO
A8

AO
98
90
88

80

PSW
(T2CON)

07

(RCAP2L)

(RCAP2H)

(TL2)

CF

(TH2)

C7

IP
P3
IE
P2
SCON
P1
TCON
PO

BF
B7

AF
..

A7

SBUF

9F

97

TMOO
SP

TLO
OPL

THO

Tl1
OPH

TH1

8F

PCON

87

Figure 2. SFR Map. ( ... ) Indicates Resident in 8052s, not in 8051s
Note that not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect.

to hold a 16-bit address. It may be manipulated as a
16-bit register or as two independent 8-bit registers.

User software should not write Is to these unimplemented locations, since they may be used in future
MCS-51 products to invoke new features. In that case
the reset or inactive values of the new bits will always
be 0, and their active values will be 1.

PO, PI, P2 and P3 are the SFR latches of Ports 0, I, 2
and 3, respectively.

The functions of the SFRs are outlined below.
ACCUMULATOR
ACC is the Accumulator register. The mnemonics for
Accumulator-Specific instructions, however, refer to
the Accumulator simply as A.

PORTS 0 T03

SERIAL DATA BUFFER
The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive· buffer register.
When data is moved to SBUF, it goes to the transmit
buffer where it is held for serial transmission. (Moving
. a byte to SBUF is what initiates the transmission.)
When data is moved from SBUF, it comes from the
receive buffer.

B REGISTER

TIMER REGISTERS

The B register is used during mUltiply and divide operations, For other instructions it can be treated as another scratch pad register.

Register pairs (THO, TLO), (THI, TLI), and (TH2,
TL2) are the 16-bit Counting registers for Timer/Counters 0, I, and 2, respectively.

PROGRAM STATUS WORD

CAPTURE REGISTERS

The PSW register contains program status information
as detailed in Figure 3.

The register pair (RCAP2H, RCAP2L) are the. Capture registers for the Timer 2 "Capture Mode." In this
mode, in response to a transition at the 8052's T2EX
pin, TH2 and TL2 are copied into RCAP2H and
RCAP2L. Timer 2 also has a 16-bit auto-reload mode,
and RCAP2H and RCAP2L hold the reload value for
this mode. More about Timer 2's features in a later
section.

STACK POINTER
The Stack Pointer Register is 8 bits wide. It is incremented before data is stOred during PUSH and CALL
executions. While the stack may reside anywhere in onchip RAM, the Stack Pointer is initialized to 07H after
a reset. This causes the stack to begin at location 08H.

CONTROL REGISTERS

DATA POINTER

Special Function Registers IP, IE, TMOD, TCON,
T2CON, SOON, and PCON contain control and status
bits for the interrupt system, the Timer/Counters, and
the seri?-, port. They are described in later sections.

The Data Pointer (DPTR) consists of a high byte
(DPH) and a low byte (DPL). Its intended function is

6-2

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

(MSB)

(LSB)

CY
Symbol

Position

CY
AC

PSW.7
PSW.6

FO

PSW.5

RSI
RSO

PSW.4
PSW.3

AC

FO

RSI

RSO

Name and Significance
Carryllag.
Auxiliary Carry flag.
(For BCD operations.)
Flag 0
(Available to the user for general
purposes.)
Register bank select control bits I &
O. Sellcleared by software to
determine working register bank (see
Note).

P

OV

Symbol

Position

OV

PSW.2
PSW.I
PSW.O

P

Name and Significance
Overflow flag.
User definable lIag.
Parity flag.
Sell cleared by hardware each
instruction cycle to indicate an odd/
even number of "one" bits in the
Accumulator, i.e., even parity.

NOTE:
The contents of (RSI, RSO) enable the working register banks as
follows:
(O.O)-Bank 0
(00H-07H)
(OBH-OFH)
(0.1 )-Bank I
(I.O)-Bank 2
(IOH-17H)
(I. I)-Bank 3
(IBH-IFH)

Figure 3. PSW: Program Status Word Register
READ
.LATCH

ADDR/DATA
CONTROL

VCC

WRITE
TO
LATCH

INT. ",BU::.::S,--+~
WRITE
TO
LATCH

READ
PIN

READ
PIN

270252-3
270252-2

B. Port 1 Bit

A. PortO Bit

ALTERNATE
OUTPUT
FUNCTION

ADDR
READ

LATCH

READ
LATCH

INT. BUS
INT. BUS

WRITE
TO
LATCH

WRITE
TO
LATCH

READ
PIN

ALTERNATE
INPUT
FUNCTION

270252-4

270252-5

C. Port 2 Bit

D. Port 3 Bit

Figure 4. 8051 Port Bit Latches and 1/0 Buffers
'See Figure 5 for details of the internal pullup.

external memory address, time-multiplexed with the
byte being written or read. Port 2 outputs the high byte
of the external memory address when the address is 16
bits wide. Otherwise the Port 2 pins continue to emit
the P2 SFR content.

PORT STRUCTURES AND
OPERATION
All four, ports in the 8051 are bidirectional. Each eon-'
sists of a latch (Special Function Registers PO through
P3), an output driver, and an input buffer.

All the Port 3 pins, and (in the 8052) two Port 1 pins
are multifunctional. They are not only port pins, but
also serve the functions of various special features as
listed on the following page.

The output drivers of Ports 0 and 2, and the input buffers of Port 0, are used in accesses to external memory.
In this application, Port 0 outputs the low byte of the

6·3

inter
Port Pin
·Pl.0
·P1.l
P3.0
P3.l
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

ADDR/DATA BUS). To be used as an input, the port
bit latch must contain a I, which tums off the output
driver PET. Then, for Ports I, 2, and 3, the pin is
pulled high by the internal pullup, but can be pulled
low by an external source.

Alternate Function
T2 (Timer/Counter 2
external input)
T2EX (Timer/Counter 2
Capture/Reload trigger)
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt)
INT1 (external interrupt)
TO (Timer/Counter 0 external
input)
Tl (Timer/Counter 1 external
input)
WR (external Data Memory
write strobe)
RD (external Data Memory
read strobe)

Port 0 differs in not having internal pull ups. The pullup
FET in the PO output driver (see Figure 4) is used only
when the Port is emitting Is during external memory
accesses. Otherwise the pullup PET is off. Consequently PO lines that are being used as output port lines are
open drain. Writing a 1 to the bit latch leaves both
output PETs off, so the pin floats. In that condition it
can be used a high-impedance input.
Because Ports 1, 2, and 3 have fixed internal pullups
they are sometimes called "quasi-bidirectional" ports.
When configured as inputs they pull high and will
source current (ilL, in the data sheets) when externally
pulled low. Port 0, on the other hand, is considered
"true" bidirectional, because when configured as an input it floats.

·Pl.O and P1.l serve these alternate functions only on
the 8052.
The alternate functions can only be activated if the corresponding bit ,latch in the port SFR,contains a 1. Otherwise the porl pin is stuck at O.

All the port latches in the 8051 have Is written to them
by the reset function. If a 0 is subsequently written to a
port latch, it can be reconfigured as an input by writing
altoit.

1/0 Configurations
Writing to a Port

Figure 4 shows a functional diagram of a typical bit
latch and I/O buffer in each of the four ports. The bit
latch (one bit in the port's SFR) is represented as a
Type D flip-flop, which will clock in a value from the
internal bus in response to a "write to latch" signal
from the CPU. The Q output of the flip-flop is placed
on the internal bus in response to a "read latch" signal
from the CPU. The level of the port pin itself is placed
on the internal bus in response to a "read pin" signal
from the CPU. Some instructions that read a port activate the "read latch"signal, and others activate the
"read pin" signal. More about that later.

In the execution of an instruction that changes the value in a port latch, the new value arrives at the latch
during S6P2 of the final cycle of the instruction. However, port latches are in fact sampled by their output
buffers only during Phase 1 of any clock period. (During Phase 2 the output buffer holds the value it saw
during the previous Phase 1). Consequently, the new
value in the port latch won't actually appear at the
output pin until the next Phase I, which will be at SIPI
of the next machine cycle.

As shown in Figure 4, the output drivers of Ports 0 and
2 are switchable to an internal ADDR and ADDR/
DATA bus by an internal CONTROL signal for use in
external memory accesses. During external memory accesses, the P2 SFR remains unchanged, but the PO SFR
gets Is written to it:

If the change requires a O-to-l transition in Port I, 2, or
3, an additional puiiup is turned on during SiPi and
SIP2 of the cycle in which the transition occurs. This is
done to increase the transition speed. The extra pullup
can source about 100 times the current that the normal
pullup can. It should be noted thaf the internal pull ups
are field-effect transistors, not linear resistors. The pullup arrangements are shown in Figure 5.

Also shown in Figure 4, is that if a P3 bit latch contains
a I, then the output level is controlled by the signal
labeled "alternate output function." The actual P3.x
pin level is always available to the pin's alternate input
function, if any.

In HMOS versions of the 8051, the fixed part of the
pullup is a depletion-mode transistor with the gate
wired to the source. This transistor will allow the pin to
source about 0.25 mA when shorted to ground. In
parallel with the fixed pullup is an enhancement-mode
transistor, which is activated during SI whenever the
port bit does a O-to-I transition. During this interval, if
the port pin is shorted to ground, this extra transistor
will allow the pin to source an additional 30 mAo

Ports 1,2, and 3 have internal pullups. Port 0 has open
drain outputs. Each I/O line can be independently used
as an' input or an output. (Ports 0 and 2 may not be
used as general purpose I/O when being used as the
6-4

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

VCC
2 OSC. PERIODS

aD

ENHANCEMENT MODE FET

~
270252-6

A. HMOS Configuration. The enhancement mode transistor
is turned on for 2 osc. periods after Q makes a 1-to-0 transition.
Vcc

Vcc

Vcc

a

FROM PORT
LATCH

READ
PORT PIN

270252-7

B. CHMOS Configuration. pFET 1 is turned on for 2 osc. periods after Q
makes a 1-to-0 transition. During this time, pFET 1 also turns on pFET 3
through the inverter to form a latch which holds the 1. pFET 2 is also on.
Figure 5. Ports 1 And 3 HMOS And CHMOS Internal Pullup Configurations.
Port 2 is Similar Except That It Holds The Strong Pull up On While Emitting
1s That Are Address Bits. (See Text, "Accessing External Memory".)

In the CHMOS versions, the pullup consists of three
pFETs. It should be noted that an n-channel FET
(nFEl) is turned on when a logical 1 is applied to its
gate, and is turned off when a logical 0 is applied to its
gate. A p-channel FET (PFET) is the opposite: it is on
when its gate sees a 0, and off when its gate sees a 1.

Port Loading and Interfacing
The output buffers of Ports 1,2, and 3 can each drive 4
LS TIL inputs. These ports on HMOS versions can be
driven in a normal manner by any TIL or NMOS circuit. Both HMOS and CHMOS pins can be driven by
open-collector and open-drain outputs, but note that 0to-1 transitions will not be fast. In the HMOS device, if
the pin is driven by an open-collector output, a 0-tO-1
transition will have to be driven by the relatively weak
depletion mode FET in Figure 5(A). In the CHMOS
device, an input 0 turns off pullup pFET3, leaving only
the very weak pullup pFET2 to drive the transition.

pFETl in Figure 5 is the transistor that is turned on for
2 oscillator periods after a 0-to-1 transition in the port
latch. While it's on, it turns on pFET3 (a weak pullup), through the inverter. This inverter and pFET form
a latch which hold the 1.
Note that ifthe pin is emitting a 1, a negative glitch on
the pin from some external source can turn off pFET3,
causing the pin to go into a float state. pFET2 is a very
weak pullup which is on whenever the nFET is off, in
traditional CMOS style. It's only about Y,0 the strength
of pFET3. Its function is to restore a 1 to the pin in the
event the pin had a 1 and lost it to a glitch.

Port 0 output buffers can each drive 8 LS TIL inputs.
They do, however, require external pullups to drive
NMOS inputs, except when being used as the
ADDRESS/DATA bus.

6-5

HARDWARE DESCRIPTION OFTHE 8051, 8052 AND 80C51

Whenever a 1'6-bit address is used, the high byte of the
address comes out on Port 2, where it is held for the
duration of the read or write cycle. Note that the Port 2
drivers use the strong pullups during the entire time
that they are emitting address bits that are Is. This is
during the execution of a MOVX @DPTR instruction.
During this time the Port 2 latch (the Special Function'
Register) does not have to contain Is, and the contents
of the Port 2 SFR are not modified. If the external
memory cycle is not immediately followed by another
external memory cycle, the undisturbed contents of the
Port ~ SFR will reappear in the next cycle.

Read-Modify-Write Feature
Some instructions that read a port read the latch and
others read the pin. Which ones do which? The instructions that read the latch rather than the pin are the ones
that read a value, possibly change it, and then rewrite it
to the latch. These are called "read-modify-write" instructions. The instructions listed below are read-modify-write instructions. When the destination operand is
a port, or a port bit, these instructions read the latch
rather than the pin:
ANL
(logical AND, e.g., ANL.PI, A)
(logical OR, e.g., ORL P2, A)
ORL
XRL
(logical EX-OR, e.g., XRL P3, A)
JBC
(jump if bit = I and clear bit, e.g.,
JBC Pl.l, LABEL)
CPL
(complement bit, e.g., CPL P3.0)
INC
(increment, e.g., INC P2)
(decrement, e.g., DEC P2)
DEC
(decrement and jump if not zero, e.g.,
DJNZ
DJNZ P3, LABEL)
MOV, PX.Y, C (move carry bit to bit-Y of Port X)
CLR PX. Y
(clear bit Y of Port X)
SETB PX. Y
(set bit Y of Port X)

If an 8-bit address is being used (MOVX @Ri), the
contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. This will facilitate paging.

In any case, the low byte of the address is time-multiplexed with the data byte on Port O. The ADDR/
DATA signal drives both FETs in the Port 0 output
buffers. Thus, in this application the Port 0 pins are not
open-drain outputs, and do' not require external pullups. Signal ALE (Address Latch Enable) should be
used to capture the address byte into an extemallatch.
The address byte is valid at the negative transition of
ALE. Then, in a write cycle, the data byte to be written
appears on Port 0 just before WR is ·activated, and remains there until after WR is deactivated. In a read
cycle, the incoming byte is accepted at Port 0 just before the read strobe is deactivated.

It is not obvious that the last three instructions in this
list are read-modify-write instructions, but they are.
They read the port byte, all 8 bits, modify the addressed
bit, then write the new byte back to the latch.

The reason that read-modify-write instructions are directed to the latch rather than the pin is to avoid a
possible misinterpretation of the voltage level at the
pin. For example, a port bit might be used to drive the
base of a transistor. When a 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same
port bit at the pin rather than the latch, it will read the
base voltage of the transistor and interpret it as a O.
Reading the latch rather than the pin will return the
correct value of 1. ' .

During any access to external memory, the CPU writes
OFFH to the Port 0 latch (the Special Function Register), thus obliterating whatever information the Port 0
SFR may have been holding.
External Program Memory is accessed under two conditions:
• 1) Whenever signal EA is· active; or
2) Whenever the program counter (PC) contains a
number that is larger than OFFFH (IFFFH for the
8052).
This requires that the ROMless versions have EA wired
low to enable the lower 4K (8K for the 8032) program
bytes to be fetched from external memory.

ACCESSING EXTERNAL MEMORY

When the CPU is executing out of external Program
Memory, all 8 bits of Port 2 are dedicated to an output
function and may not be used for general purpose I/O.
During external program fetches they output the high
byte of the PC. During this time the Port 2 drivers use
the strong pullups to emit PC bits that are Is.

Accesses to external memory are of two types: accesses
to external Program Memory and accesses to external
Data Memory. Accesses to external Program Memory
use signal PSEN (program store enable) as the read
strobe. AccesseS to external Data Memory use RD or
WR (alternate functions of P3.7 and P3.6) to strobe the
memory..

TIMER/COUNTERS

Fetches from external Program Memory always use a
16-bit address. Accesses to external Data Memory can
use either a 16-bit address (MOVX @DPTR) or an
8-bit address (MOVX @Ri).

The 8051 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. The 8052 has these two plus one
mOt;"e: Timer 2. All three can be configured to operate
either as timers or event counters.
6-6

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

In the "Timer" function, the register is incremented
every machine cycle. Thus, one can think of it as counting machine cycles. Since a !llachine cycle consists of 12
oscillator periods, the count rate is '112 of the oscillator
frequency.

MODE 0

Putting either Timer into Mode 0 makes it look like an
8048 Timer, which is an 8-bit Counter with a divide-by32 prescaler. Figure 7 shows the Mode 0 operation as it
applies to Timer 1.

, In the "Counter" function, the register is incremented
in response to a I-to-O transition at its corresponding
external input pin, TO, TI or (in the 8052) T2. In this
function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in
one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register
during S3PI of the cycle following the one in which the
transition was detected. Since it takes 2 machine cycles
(24 oscillator periods) to recognize a I-to-O transition,
the maximum count rate is '1.4 of the oscillator frequency. There are no restrictions on the duty cycle of
the external input signal, but to ensure that a given
level is sampled at least once before it changes, it
should be held for at least one full machine cycle.

In this mode, the Timer register is configured as a
13-Bit register. As the count rolls over from allis to all
Os, it sets the Timer interrupt flag TF1. The counted
input is enabled to the Timer when TRI = I and either
GATE = 0 or INTI = 1. (Setting GATE = I allows
the Timer to be controlled by external input INTI, to
facilitate pulse width measurements.) TRI is a control
bit in the Special Function Register TeON (Figure 8).
GATE is in TMOD.
The 13-Bit register consists of all 8 bits ofTHI and the
lower 5 bits of TL1. The upper 3 bits of TLI are indeterminate and should be ignored. Setting the run flag
(TR I) does not clear the registers.

In addition to the "Timer" or "Counter" selection,
Timer 0 and Timer I have four operating modes from
which to select. Timer 2, in the 8052, has three modes
of operation: "Capture," "Auto-Reload" and "baud
rate generator."

Mode 0 operation is the same for Timer 0 as for Timer
1. Substitute TRO, TFO and INTO for the corresponding Timer I signals in Figure 7. There are two different
GATE bits, one for Timer I (TMOD.7) and one for
Timer 0 (TMOD.3).

Timer 0 and Timer 1

MODE 1

Mode I is the same as Mode 0, except that the Timer
register is being run with all 16 bits.

These Timer/Counters are present in both the 8051 and
the 8052. The "Timer" or "Counter" function is selected by control bits ciT in the Special Function Register
TMOD (Figure 6). These two Timer/Counters have
four operating modes, which are selected by bit-pairs
(MI, MO) in TMOD. Modes 0, I, and 2 are the same
for both Timer/Counters. Mode 3 is different. The four
operating modes are described in the following text.

l

(MSB)

GATE

CIT

Ml

MO

MODE 2

Mode 2 configures the Timer register as an 8-bit Counter (TLJ) with automatic reload, as shown in Figure 9.
Overflow from TLI not only sets TFI, but also reloads

1

(LSB)

GATE

CIT

Ml

MO

J

T

Timer 1
GATE

cli'

Timer 0

Gating control when set. Timer /CoUl;ter '"x'" is enabled
only while '"INTx'" pin is high and '"TRx'" control pin is
set. When cleared Timer '"x" is enabled whenever
'"TRx'" control bit is set.
Timer or Counter Selector cleared for Timer operation
(input from internal system clock). Set for Counter
operation (input from '"Tx" input pin).

Ml

MO

o
o

o

Operating Mode
MCS-48 Timer '"TLx" serves as 5-bit prescaler.
IS-bit Timer/Counter '"THx" and '"TLx" are
cascaded; there is no prescaler.

o

8-bit auto-reload Timer/Counter '"THx'" holds a
value which is to be reloaded into '"TLx" each
time it overflows.
(Timer 0) TLO is an 8-bit Timer/Counter
controlled by the standard Timer 0 control bits.
THO is an 8-bittimer only controlled by Timer 1
)
control bits.
(Timer 1) Timer/Counter 1 stopped.

Figure 6. TMOD: Timer/Counter Mode Control Register

6-7

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

cif= 0
INTERRUPT

Tt PIN

__ ---,___---'t clf =1

CONTROL

-

GATE

270252-9

Figure 7. Timer/Counter 1 Mode 0: 13-Blt Counter

(MSB)
TFI

(LSB)
TRI

TFO

TRO

lEI

ITt

lEO

ITO

Symbol

Position

Name and Significance

Symbol

Position

Name,and Significance

TFI

TCON.7

Timer I overflow Flag. Set by
hardware on TImer/Counter overflow.
Cleared by hardware lNhen processor
vectors to inter!'IJpt routine.

lEI

TCON.3

Interrupt I Edge flag. Set by hardware
when external interrupt edge
detected. Cleared when interrupt
processed.

TRI

TCON.6

Timer I Run control bit. Sell cleared
by software to turn Timer/Counter on/
off.

ITt

TCON.2

TFO

TCON.5

Timer 0 overflow Flag. Set by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.

Interrupt I Type control bit. Sell
cleared by soltware to specify falling
edge/low level triggered external
interrupts.

lEO

TCON.I

Interrupt 0 Edge lIag. Set by hardware
when external Interrupt edge
detected. Cleared when interrupt
processed.

ITO

TCON.O

Interrupt 0 Type control bit. Set!
cleared by software to specify falling
edge/low level triggered external
interrupts.

TRO

TCON.4

Timer 0 Run control bit. Set/cleared
by software to turn Timer/Counter on/
off.

Figuie a.TeON: Timer/Counter Centro! Register

CIT, GATE, TRO, INTO, and TFO. THO is locked into

TLl with the contents ofTHI, which is preset by software. The reload leaves THI unchanged.

a timer function (counting machine cycles) and takes
over the use ofTRI and TFI from Timer 1. Thus, THO
now controls the "Timer I" interrupt.

Mode 2 operation is the same for Timer/Copnter O.

Mode 3 is provided for applications requiring an extra
8-bit timer or counter. With Timer 0 in Mode 3, an
8051 can look like it has three Timer/Counters, and an
8052, like it has four. When Timer 0 is in Mode 3,
Timer 1'can be turned on and offby switching it out of
and into its own Mode 3, or can still be used by the
serial port as a baud rate generator, or in fact, in any
application not requiring an interrupt.

MODE 3

Timer I in Mode 3 simply holds its count. The effect is
the same as setting TRI = O.
Timer 0 in Mode 3 establishes TLO and THO as two
separate counters. The logic for Mode 3 on Timer 0 is
shown in Figure 10. TLO uses the Tinier 0 control bits:

6-8

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

INTERRUPT

270252-10

Figure 9. Timer/Counter 1 Mode 2: a-Bit Auto-Reload

osc

~B-

1112 lose

1/12 lose - - - - - - - ,

INTERRUPT

TO

PIN-----~

CONTROL

1112 lose

I· L.1_(_~_I_~) HL._TF_1-.1~'INTERRUPT

--------'-'--:---+1---<1
_ __
'TR1

.....

~____~=ieoNTRoL
-

270252-1,1

Figure 10. Timer/Counter 0 Mode 3: Two a-Bit Counters

Timer 2
Table 2. Timer 2 Operating Modes
Timer 2 is a 16-bit Timer/Counter which is present
only in the 8052. Like Timers 0 and I, it can operate
either as a timer or as an event counter. This is selected .
by bit C/T2 in the Special Function Register T2CON
(Figure 11). It has three operating modes: "capture,"
"auto-load" and, "baud rate generator," which are selected by bits in T2CON as shown in Table 2.

6-9

RCLK

+ TCLK CP/RL2 TR2
0
0
1
X

0
1
X
X

1
1
1
0

Mode
16-bit Auto~Reload
16-bit Capture
Baud Rate Generator
(off)

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

(MSB)
TF2

(LSB)
EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

cPlFi1:2

Symbol

Position

TF2

T2CON.7

TImer 2 overflow flag set by a Timer 2 overflow and must be cleared by software.
TF2 will not be set when eHher RCLK = 1 or TCLK = 1.

Name and Significance

EXF2

T2CON.6

Timer 2 external flag set when either a capture or reload Is caused by a negative
transition on T2EX and EXEN2 = 1. When TImer 2 Interrupt is enabled, EXF2 = 1
will cause the CPU to vector to the TImer 2 Interrupt routine. EXF2 must be
cleared by software.

RCLK

T2CON.5

Receive clock flag. When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock In Modes 1 and 3. RCLK = 0 causes TImer 1 overflow
to be used for the receive clock.

TCLK

T2CON.4

TransmH clock fleg. When set, causes the serial port to use TImer 2 overflow
pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1
overflows to be used for the transmit clock.

EXEN2

T2CON.3

TImer 2 external enable flag. When set, allows a capture or reload to occur as a
result of a negative transition on T2EX nTimer 2 is not being used to clock the
serial port. EXEN2 = 0 causes TImer 2 to Ignore events at T2.EX.

TR2

T2CON.2

Start/stop control for TImer 2. A logic 1 starts the timer.

C/T2

T2CON.1

Timer or counter select. (TImer 2)
o = Internal timer (OSC/12)
1 = External event counter (falling edge triggered) ..

CP/RL2

T2CON.O

Capture/Reload flag. When set captures will occur on negatiVe transitions at
T2EX,if EXEN2 = 1. When cleared, auto-reloads will occur either with TImer 2
overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK
= 1 or TCLK = 1, this bit Is ignored and the timer Is forced to auto-reload on
TImer 2 overflow.

FIgure 11. T2CON: TImer/Counter 2 Control RegIster
In the Capture Mode there are two options which are
selected by bit EXEN2 in T2CON. If EXEN2 = 0,
then Timer 2 is a 16-bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit,
which can be used to generate an interrupt. If EXEN2
= 1, then Timer 2 still does the above, but with the
added feature that a 1-to-O transition at external input
T2EX causes the current value in the Timer 2 registers,
TL2 and TH2, to be captured into registers RCAP2L
and RCAP2H, respectively. (RCAP2L and RCAP2H
are new Special Function Registers in the 8052.) In
addition, the transition at T'2EX causes bit EXF2 in
T2CON to be set, and EXF2, like TF2, can generate an
interrupt.
The Capture Mode is illustrated in Figure 12.
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0, then when Timer 2 rolls over it not only
sets TF2 but also causes the Timer 2 registers to be
reloaded with the 16-bit value in registers RCAP2L
and RCAP2H, which are preset by software. IfEXEN2
= I, then Timer 2 still does the above, but with the

added feature that a 1-to-0 transition at external input
T2EX.will also trigger the 16"bit reload and set EXF2.
The auto-reload mode is illustrated in Figure 13.
The baud rate generator mode is selected by RCLK =
1 andlor TCLK = 1. It will be described in conjunction with the serial port.

SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit
.and receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
before a previously received byte has been read from
the receive register. (However, if the first byte still
hasn't been read by the time reception of the second
byte is complete, one of the bytes will be lost). The
serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to
SBUF loads the transmit register, and reading SBUF
accesses a physically separate receive register.

6-10

intJ

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

nMER2
INTERRUPT

EXEN2

270252-12

Figure 12. Timer 2 in Capture Mode

The serial port can operate in 4 modes:

Multiprocessor Communications

Mode 0: Serial data enters and exits through RXD.
TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at
1/12 the oscillator frequency.

Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are
received. The 9th one goes into RB8. Then comes a
stop bit. The port can be programmed such that when
the stop bit is received, the serial port interrupt will be
activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in
multiprocessor systems is as follows.

Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit goes
into RB8 in Special Function Register SCON. The
baud rate is variable.

When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address byte which identifies the target slave. An address
byte differs from a data byte in that the 9th bit is 1 in an
address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address
byte, however, will interrupt all slaves, so that each
slave can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit
and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their
SM2s set and go on about their business, ignoring the
coming data bytes.

Mode 2: 11 bits are transmitted (through TXD) or received (throughRXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit (1).
On Transmit, the 9th data bit (TB8 in SCON) can be
assigned the value of 0 or 1. Or, for example, the parity
bit (p, in the PSW) could be moved into TB8. On receive, the 9th data bit goes into RB8 in Special Functon
Register SCON, while the stop bit is ignored. The baud
rate is programmable to either '132 or '164 the oscillator
frequency.
Mode 3: 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit and a stop bit (1). In
fact, Mode 3 is the same as Mode 2 in all respects
except the baud rate. The baud rate in Mode 3 is variable.

SM2 has no effect in Mode 0, and in Mode 1 can be
used to check the validity of the stop bit. In a Mode 1
reception, if SM2 = 1, the receive interrupt will not be
activated unless a valid stop bit is received.

Serial Port Control Register
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0
and REN = 1. Reception is initiated in the other
modes by the incoming start bit if REN = 1.

The serial port control and status register is the Special
Function Register SCON, shown in Figure 14. This
register contains not orily the mode selection bits, but
also the 9th data bit for transmit and receive (TB8 and
RB8), and the serial port interrupt bits (TI and RI).

6-11

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

TIMER 2
INTERRUPT

EXEN2

270252-13

Figure 13. Timer 2 in Auto-Reload Mode

(MSB)
SMO

SMI

I SM2

(LSB)
REN

Where SMO, SMI specify the serial port mode, as follows:
SMO
0
0

SMI
0
0

Mode
0
1
2

3
•

•

SM2

REN

TB8

RB8
•

Description
shift register
8·bitUART
9-bitUART

Baud Rate
fose/12
variable
fose/64
or
fose/32
9-bit UART variable

TI

TB8

is the 9th data bit that will be
transmitted in Modes 2 and 3. Set or
clear by software as desired.
In Modes 2 and 3, is the 9th data bit
that was received. In Mode I, if SM2
= 0, RB8 is the stop bit that was
received. In Mode 0, RBS is not used.

.
.

TI

is transmit interrupt flag. Set by
hardware at the end of the Sth bit time
In Mode 0, or at the beginning of the
stop bit in the other modes, in any
serial transmission. Must be cleared
by software.

•

RI

is receive interrupt flag. Set by
hardware at the end of the 8th bit time
in Mode 0, or halfway through the stop
bn time in the other modes, in any
serial reception (except see 8M2).
Must be cleared by software.

RB8

enables the multiprocessor
communication feature in Modes
2 and 3. In Mode 2 or 3, if 8M2 Is
setto 1 then RI will no! be
activated if the received 9th data
bit (RBS) is O. In Mode I, if 8M2
= 1 then RI will not be activated
if a valid stop bit was not
received. In Mode 0, 8M2 should
beO.
enables serial receotion. Set bv
software to enable reception. .
Clear by software to disable
reception.

RI

Figure 14. SCON: Serial Port Control Register

Baud Rates
The baud rate in Mode 0 is fixed:

Mode 2 Baud Rate =

Oscillator Frequency
Mode 0 Baud Rate = ---'._---''---'12

SMOD

2
64X
(Oscillator Frequency)

In the 8051, the'baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. In the 8052, these
baud rates can be determined by Timer 1, or by Timer
2, or by both (one for transmit and the other for receive).

The baud rate in Mode 2 depends on the value of bit
SMOD in Special Function Register peON. If SMOD
= 0 (which is the value on reset), the baud rate %4 the
oscillator frequency. If SMOD
1, the baud rate is
'1.2 the oscillato.r frequency.
6-12

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

Using Timer 1 to Generate Baud Rates

mode (high nibble of TMOD = OOIOB). In that case,
the baud rate is given by the formula

When Timer 1 is used as the baud rate generator, the
baud rates in Modesl and 3 are determined by the
Timer 1 overflow rate and the value of SMOD as fol~
lows:

Modes 1, 3 2SMOD Oscillator Frequency
Baud Rate = - - - X - - - - - - - - ' ' - - - - : = 32
12x [256 - (THl)l
One can achieve very low baud rates with Timer 1 by
leaving the Timer 1 interrupt enabled, and configuring
the Timer to run as a l6-bit timer (high nibble of
TMOD = OOOlB), and using the Timer 1 interrupt to
do a 16-bit software reload.

Modes 1,3 2SMOD
Baud Rate =
X (Timer 1 Overflow Rate)

----n-

The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either
"timer" or "counter" operation, and in any of its 3
. running modes. In the most typical applications, it is
configured for "timer" operation, in the auto-reload

Figure 15 lists various commonly used baud rates and
how they can be obtained from Timer 1.

Baud Rate

fosc

SMOD

Mode 0 Max: 1 MHZ
Mode 2 Max: 375K
Modes 1, 3: 62.5K
19.2K
9.6K
4.8K
2.4K
1.2K
137.5K
110K
110K

12MHZ
12MHZ
12MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.059 MHZ
11.986 MHZ
6MHZ
12MHZ

X
1
1
1

a
a
a
a
a
a
a

clf
X
X
0

a
a
a
a
a
a
a
a

Timer 1
Reload
Mode
Value
X
X
X
X
2
FFH
FDH
2
2
FDH
2
FAH
F4H
2
2
E8H
2
1DH
2
72H
1
FEEBH

Figure 15. Timer 1 Generated Commonly Used Baud Rates
Using Timer 2 to Generate Baud Rates

In the 8052, Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Figure

11). Note then the' baud rates for transmit and receive
can be simultaneously different. Setting RCLK and/or
TCLK puts Timer 2 into its baud rate generator mode,
as shown in Figure 16.
nMER 1

OVERFLOW

AX CLOCK

TXCLOCK

"TIMER 2"

T2EX PIN

INTERRUPT

EX""

L

NOTE AYAILAIIU.rTY OF ADDmoNAL EXTERNAL INTERRUPT

270252-14

Figure 16. Timer 2 in Baud Rate Generator Mode
6-13

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal at S6P2 also loads a I into the 9th position ofthe
transmit shift register and tells the TX Control block to
commence a transmission. The internal timing is such
that one full machine cycle will elapse between "write
to SBUF," and activation of SEND.

The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2
registers to be reloaded with the 16-bit value in registers
RCAP2H and RCAP2L, which are preset by software.
Now, the baud rates in Modes I and 3 are determined
by Timer 2's overflow rate as follows:
Modes I, 3 Baud Rate =

SEND enables the output of the shift register to the
alternate output function line of P3.0, and also enables
SHIFT CLOCK to the alternate output function line of
P3.1. SHIFT CLOCK is low during S3, S4, and S5 of
every machine cycle, and high during S6, SI and S2. At
S6P2 of every machine cycle in which SEND is active,
the contents of the transmit shift register are shifted to
the right one position.

Timer 2 Overflow Rate
16"

The Timer can be configured for either "timer" or
"counter" operation. In the most typical applications, it
is configUred for "timer" operation (C/T2 = 0). "Timer" operation is a little different for Timer 2 when it's
'being used as a baud rate generator. Normally, as a
timer it would increment every machine cycle (thus at
'112 the oscillator frequency). As a baud rate generator,
however, it increments every state time (thus at '!. the
oscillator frequency). In that case the baud rate is given
by the formula

As data bits shift out to the right, zeroes come in from
the left. When the MSB of the data byte is at the output
position of the shift register, then the I that was initially loaded into the 9th position, is just to the left of the
MSB, and all positions to the left ofthat contain zeroes.
This condition flags the TX Control block to do one
last shift and then deactivate SEND and set TI. Both of
these actions occur at SIPI of the 10th machine cycle
after "write to SBUF."

Modes I, 3
Oscillator Frequency
Baud Rate = 32x [65536 - (RCAP2H, RCAP2L)1
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2J:, taken as a 16-bit unsigned integer.

Reception is initiated by the condition REN = I and
Rl. = O. At S6P2 of the next machine cycle, the RX
Control unit writes the bits 11111110 to the receive
shift register, and in the next clock phase activates RECEIVE.

Timer 2 as a baud rate generator is shown in Figure 16.
This Figure is valid only if RCLK + TCLK = I in
T2CON. Note that a rollover in TH2 does not setTF2,
and will not generate an interrupt. Therefore, the Timer
2 interrupt does not have to be disabled when Timer 2
is in the baud rate generator mode. Note too" that if
EXEN2 is set, a I-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
as ,a baud rate generator, T2EX can be used as an extra
external interrupt, if desired.

RECEIVE enables SHIFT CLOCK to the alternate
output function line of P3.1. SHIFT CLOCK makes
transitions at S3Pl and S6Pl of every machine cycle.
At S6P2 of every machine cycle in which RECEIVE is
active, the contents of the receive shift register are shifted to the left one position. The value that comes in
from the right is the value that was sampled at the P3.0
pin at S5P2 of the same machine cycle. '
As data bits come in from the right, Is shift out to the
left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift
register, it flags the RX Control block to do one last
shift and load SBUF. At SIP I of the 10th machine
cycle after the write to SCON that cleared RI, RECEIVE is cleared and'RI is set.

It should be noted that when Timer 2 is running (TRZ
= I) in "timer" function in the baud rate generator
mode, one should not try to read or write TH2 or TL2.
Under these conditions the Timer is being incremented
every state time, and the results of a read or write may
not be accurate. The RCAP registers may be read, but
shouldn't be written to, because a write might overlap a
reload and cause write and/or reload errors. Tum the
Timer off (clear TR2) before accessing the Timer 2 or
RCAP registers, in this case.

More About Mode '1
Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSD first),
and a stop bit (1), On receive, the stop bit goes into
RB8 in SCON. In the 8051 the'baud rate is determined
by the Timer 1 overflow rate. In the 8052 it is determined either by the Timer 1 overflow rate, or the Timer
2 overflow rate, or both (one for transmit and the other
for receive).

More About Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/received: 8
data bits (LSB first). The baud rate is fixed at 1/12 the
oscillator frequency.
Figure 17 shows a simplified functional diagram of the
serial port in Mode 0, and associated timing.

Figure 18 shows a simplified functional diagram of the
serial port in Mode 1, and associated timings for transmit receive.
6-14

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

WRITE
SBUF
TO

---'--=~~~r:--~~----1---------r-,

RXD
P3.0ALT
OUTPUT
FUNCTION

56.-_.------1
TXD
P3.1 ALT
OUTPUT
FUNCTION

' - - - - - I RX CLOCK
RX CONTROL

REN--...r--l--_ _.j START

Ri-"'~

SHIFT

L..._--i........,...-.-T""'!,......,-i---.J

RXD
P3.0ALT
INPUT
FUNCTION

READ
SBUF

ALE
4WRITE TO SBUF
SEND 88P2'
I
SHIFT
TRANSMIT

RXD (DATA OUT) \
TXD (SHIFT CLOCK)

n
-1l WRITE TO SCON (CLEAR RI)

~RIi~~~==j=::::::::::::::::::::::::::::::::::::::::::::::::::::~r----­
L-

'!!'CEIVE
SHIFT

RECEIVE

RXD (DATA IN)---.....,[}':'~---{}.!'r.!----o=-----[i=----LJ='''-----[}''~--o=-----[F-­
TXD (SHIFT CLOCK)
270252-15

Figure 17. Serial Port Mode 0

inter

HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

TIM·ER2
OVERFLOW

TIMER 1
OVERFLOW

TO
WRIT~E-r-:=jrot:m::;r~;""'~~_":-'"~_-r"""'\~;.....r-,
SBUF
TXD

RECEIVE

..

!

R";~LOC

fiTART BITI

DO

0'

62

tilT DETECTOR SAMPLE TIMES

oj

D4

..

DI

D)

SHIFT
'
___________________________________________________
~R~I

STOP BIT
~r----

270252-16

Figure 18. Serial Port Mode 1. TCLK, RCLK and timer 2 are Present in the 8052/8032 Only.

Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads a 1 into the 9th bit position of the
transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission actually
commences at SIPI of the machine cycle following the
next rollover in the divide-by-16 counter. (Thus, the bit

times are synchronized to the divide-by-16 counter, not
to the "write to SBUF" signal).
The tra:!lsinission begins with activation of SEND,
which puts the start bit at TXD. One bit time later,
DATA is activated, which enables the output bit· of the
transmit shift register to TXD. The first shift pulse occurs one bit time after that.
6-16

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

As data bits shift out to the right, zeroes are clocked in
from the left. When the MSB of the data byte is at the
output position of the shift register, then the 1 that was
initially loaded into the 9th position is just to the left of
the MSB, and all positions to the left of that contain
zeroes. This condition flags the TX Control unit to do
one last shift and then deactivate SEND and set TI.
This occurs at the 10th divide-by-16 rollover after
"write to SBUF."
Reception is initiated by a detected I-to-O transition at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and IFFH is written into the input shift
register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.

mit, the 9th data bit (TB8) can be assigned the value of
1. On receive, the 9th data bit goes into RB8 in
SCON. The baud rate is programmable to either Yo. or
'164 the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from either Timer 1
or 2 depending on the state of TCLK and RCLK.

o or

Figures 19 and 20 show a functional diagram of the
serial port in Modes 2 and 3. The receive portion is
exactly the same as in Mode I: The transmit portion
differs from Mode 1 only in the 9th bit of the transmit
shift register.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads TB8 into the 9th pit position of the
transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission commences at SIPl of the machine cycle following the next
rollover in the divide-by-16 counter. (Thus, the bit
times are synchronized to the divide-by-16 counter, not
to the "write to SBUF" signal.)

The 16 states of the counter divide each bit time into
16ths. At the 7th, 8th, and 9th counter states of each bit
time, the bit detector samples the value of RXD. The
value accepted is the value that was seen in at least 2 of
the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not 0, the
receive circuits are reset and the unit goes back to looking for another I-to-O transition. This is to provide rejection of false start bits. If the start bit proves valid, it
is shifted into the input shift register, and reception of
the rest of the frame will proceed.

The transmission begins with activation of SEND,
which puts the start bit at TXD. One bit time later,
DATA is activated, which enables the output bit of the
transmit shift register to TXD. The first shift pulse occurs one bit time after that. The first shift clocks a 1
(the stop bit) into the 9th bit position of the shift register. Thereafter, only zeroes are clocked in. Thus, as
data bits shift out to the right, zeroes are clocked in
from the left. When TB8 is at the output position of the
shift register, then the stop bit is just to the left of TB8,
and all positions to the left of that contain zeroes. This
condition flags the TX Control unit to do one last shift
and then deactivate SEND and set TI. This occurs at
the lIth divide-by-16 rollover after "write to SBUF."

As data bits come in from the right, Is shift out to the
left. When the start bit arrives at the leftmost position
in the shift register, (which in mode 1 is a 9-bit register), it flags the RX Control block to do one last shift,
load SBUF and RB8, and set RI. The signal to load
SBUF and RB8, and to set RI, will be generated if, and
only if, the following conditions are met at the time the
final shift pulse is generated.

Reception is initiated by a detected I-to-O transition at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and IFFH is written to the input shift
register.

1) RI = 0, and
2) Either 5M2 = 0, or the received stop bit = 1

If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met,
the stop bit goes into RB8, the 8 data bits go into
SBUF, and RI is activated. At this time, whether the
above conditions are met or not, the unit goes back to
looking for a 1-to-0 transItion in RXD.

At the 7th, 8th and 9th counter states of each bit time,
the bit detector samples the value of RXD. The valueaccepted is the value that was seen in at least 2 of the 3
samples. If the value accepted during the first bit time
is not 0, the receive circuits are reset and the unit goes
back to looking for another I-to-O transition. If the
start bit proves valid, it is shifted into the input shift
register, and reception of the rest of the frame will proceed.
.
.

More About Modes 2 and 3
Eleven bits are transmitted (through TXD), or received
(throughRXD): a start bit (0),8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On trans-

6-17

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

WRITE
TO
SBUF
TXD

PHASE 2 CLOCK
('hfosc)

MODE2
TI

SMOD=l

(SMOD IS PCON.7)

SERIAL
PORT
INTERRUPT

1..-_--....
LOAD
SBUF

RXD

READ _ _......"
SBUF

:~~T~XD~}~T}A~RT~.~IT/~P~D~==~=~==~=~=~:;:;~:;~:;~C::::

)\TRANSMIT

TI

~------~------------------------------

____________~r--270252-17

Figure 19. Serial Port Mode 2

6-18

infef

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

TIMER"
OVERFLOW

TIMER 2
OVERFLOW

TXD

TCLK -

SEND

LOAD
SBUF
SHIFT

1------...,

RXD

TX
~FLOC~~~~~=-~L-~L--IL--~L-~L-~I--JL--~L-~L-~.L--­

---A WRITE TO SBUF

~

DATA
SHIFT

L

SEND
S1P1 I

----riD\'TARTBIT/

TRANSMIT
DO

TI

I

STOP BIT GEN
RX
CLOCK

RECEIVE

RXD BIT DETECTORI START BIT /
SAMPLE TIMES
~ __~'L__~L_ _~L_ _"L_~L-_~L_ _~L___JL-__~L-_ _ _
SHIFT
_______________________________
~RI~

~r-----

270252-18

Figure 20. Serial Port Mode 3. TCLK, RCLK, and Timer 2 are Present in the 8052/8032 Only.

6-19

, intJ

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

was transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware.

As data bits come in from the right, Is shift out to the
left. When the start bit arrives at the leftmost position
in the shift register (which in Modes 2 and 3 is a 9-bit
register), it flags the RX Control block to do one last
shift, load SBUF and RB8, and set RI. The signal to
load SBUF and RB8, and to set RI, will be generated if,
and only if, the following conditions are met at the time
the final shift pulse is generated:
1) RI = 0, and
2) Either 5M2 = 0 or the received 9th data bit

The Timer 0 and Timer 1 Interrupts are generated by
TFO and TFI, which are set by a rollover in theirrespective Timer/Counter registers (except see Timer 0 in
Mode 3). When a timer interrupt is generated, the flag
that generated it is cleared by the on-chip hardware
when the service routine is vectored to.

=1

If either of these conditions is not met, the received
frame is irretrievably lost, and RI is not set. If both
conditions are met, the received 9th data bit goes into
RB8, and the first 8 data bits go into SBUF. One bit
time later, whether the above conditions were met or
not, the unit goes back to looking for a I-to-O transition
at the RXD input.

.The Serial Port Interrupt is generated by the logical OR
of RI and TI. Neither of these flags is Cleared by hardware when the service routine is vectored to. In fact,
the service routine will normally have to determine
whether it was RI or TI that generated the interrupt,
and the bit will have to be Cleared in software.
In the 8052, the Timer 2 Interrupt is generated by the
logical OR of TF2 and EXF2. Neither of these flags is
Cleared by hardware when the service routine is vec-.
tored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the
interrupt, and the -bit will have to be cleared in 80ftware.

Note that the value of the received stop bit is irrelevant
to SBUF, RB8, or RI.

INTERRUPTS
The 8051 provides 5 interrupt sources. The 8052 provides 6. These are shown in Figure 21.

All of the bits that generate interrupts can be set or
Cleared by software, with the same result as though it
had been set or cleared by hardware. That is, interrupts
can be generated or pending interrupts can be canceled
in software.

The External Interrupts INTO and INTI can each be
either level-activated or transition-activated, depending
on bits ITO and ITI in Register TCON. The flags that
actually generate these interrupts are bits lEO and lEI
in TCON. When an external interrupt is generated, the
flag that generated it is cleared by the hardware when
the service routine is vectored to only if the interrupt

(MSB)

(LSB)

1~1-1~1~lml~I~I~1
Symbol
~

Position
IE.7

IE.6

reserved.

ET2

IE.5

enables or disables the Timer 2
Overflow or caoture interruot. If ET2
= 0, the Timer 2 Interrupt is disabled.

ES

IE.4

enables or disables the Serial Port
interrupt. If ES = O. the Serial Port
interrupt is disabled.

ETI

IE.3

enables or disables the Timer 1
Overflow interrupt. If En = O. the
Timer 1 interrupt Is disabled:

EXI

IE.2

enables. or disables External Interrupt
1. If EXI = O. External Interrupt 1 is
disabled.

ETO

IE.l

enables or disables the Timer 0
Overflow interrupt. If ETO = 0, the
Timer 0 interruptis disabled.

EXO

lE.O

enables or disables External Interrupt
O. If EXO = 0, External Interrupt 0 is
disabled.

TFO'---------·
INTERRUPT
SOURCES

~,--------~~

Function
disables all interrupts. If EA = 0, no
interrupt will be acknowledged. .If EA
= 1. each interrupt source Is
individually enabled or disabled by
selling or clearing its enable bH.

User sdftware should never write 1s to unimplemented bits,
since they [!lay be used in future MC5-51 products.

270252-19

Figure 21. MCS®·51 Interrupt Sources

Figure 22. IE: Interrupt Enable Register
6-20

intJ

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence, as follows:

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special
Function Register IE (Figure 22). IE contains also a
global disable bit, EA, which disables all interrupts at
once.
Note in Figure 23 that bit position IE.6 is unimplemented. In the 805 Is, bit position IE.5 is also unimplemented. User software should not write Is to these bit
positions, since they may be used in future MCS-51
products.

1.
2.

3.
4.
5.
6.

Priority Level Structure
Each interrupt source can also be individually programmed to one of two priority levels by setting or
clearing a bit in Special Function Register IP (Figure
23). A low-priority interrupt can itself be interrupted
by a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source.
(MSB)

reserved

IP.6

reserved

PT2

IP.5

defines the Timer 2 interrupt priority
level. PT2 = 1 programs it to the
higher priOrity level.

PS

IP.4

defines the Serial Port interrupt priority
level. PS = 1 programs it to the
higher priority level.

PTl

IP.3

defines the Timer 1 interrupt priority
level. PTl = 1 programs it to the
higher priority level.

PTO

IP.l

defines the Timer 0 interrupt priority
level. PTO = 1 programs it to the
higher priority level.

PXO

IP.O

defines the External Interrupt 0 priority
level. PXO = 1 programs it to the
higher priority level.

(highest)

(lowest)

The IP register contains a number of unimplemented
bits. IP.7 and IP.6 are vacant in the 8052s, and in the
8051s these and IP.5 are vacant. User software should
not write Is to these bit positions, since they may be
used in future MCS-51 products.

(LSB)

Position
IP.7

Priority Within Level

lEO
TFO
IE1
TF1
RI +TI
TF2 + EXF2

Note that the "priority within level" structure is only
used to resolve simultaneous requests of the same priority leveL

1-1-1~1~lrnl~I~I~1
Symbol

Source

Function

How Interrupts Are Handled
The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle
will find it and the interrupt system will generate an
LCALL to the appropriate service routine, provided
this hardware-generated LCALL is not blocked by any
of the following conditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The cUrrent (polling) cycle is not the final cycle in
the execution of the instruction in progress.
3. The instruction in progress is RET! or any write to
the IE or IP registers.

User software should never write 1s to unimplemented bits,
since they may be used in future MCS·51 products.

Any of these three conditions will block the generation
of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be

Figure 23. IP: Interrupt Priority Register

· · · · · · · · - - C l -...._1" ' - - C 2 - -••+I---C3--~I".--C4--'_1. - - C 5 - - · · · ..
IS5P21

5&

········~'\---'-----=l.llli---L---l'l:l-----L----

f'7't

INTERRUPT
GOES
ACTIVE

INTERRUPT
LATCHEO

LONG CALL TO
INTERRUPT
VECTOR AOORESS

INTERRUPTS
ARE POLLED

INTERRUPT ROUTIN.E

270252-20

This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.

Figure 24. Interrupt Response Timing Diagram
6-21

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is
RETI or any access to IE or IP, then at least one more
instruction will be executed before any interrupt is vectored to.

External Interrupts
The external sources can be programmed to be level-activated or transition-activated by setting or clearing bit
ITt or ITO in Register TCON. If ITx = 0, external
interrupt x is triggered by a detected low at the INTx
pin. If ITx = 1, external interrupt x is edge-triggered.
In this mode if successive samples of the INTx pin
show a high in one cycle and a low in the next cycle,
interrupt request flag lEx in TCON is set. Flag bit lEx
then requests the interrupt.

The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at
S5P2 of the previous machine cycle. Note then that if
an interrupt flag is active but not being responded to for
one of the above conditions, if the flag is not still active
when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact
that the interrupt flag was once active but not serviced
is not remembered. Every polling cycle is new.

Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at
least 12 oscillator periods to ensure sampling. If the
external interrupt is transition-activated, the external
source has to hold the request pin high for at least one
cycle, and then hold it low for at least one cycle to
ensure that the transition is seen so that interrupt request flag lEx will be set. lEx wiil be automatically
cleared by the CPU when the service routine is called.

The polling cycle/LCALL sequence is illustrated in
Figure 24.
Note that if an interrupt of higher priority level goes
active prior to S5P2 of the machine cycle labeled C3 in
Figure 24, then in accordance with the above rules it
will be vectored to during C5 and C6, without any instruction of the lower priority routine having been executed.
'

If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is
completed, or else another interrupt will be generated.

Thus the processor acknowledges an interrupt request
by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears
the flag that generated the interrupt, and in other cases
it doesn't. It never clears the Serial Pcirt or Timer 2
flags. This has to be done in the user's software. It
clears an external interrupt flag (lEO or lEI) only if it
was transition-activated. The hardware-generated
LCALL pushes the contents of the Program Counter
onto the stack (but it does not,save the PSW) and reloads the PC with an address that depends on the
source of the interrupt being vectored to, as shown below.
'

lEO

Vector
Address
0003H

TFO

OOOBH

IE1
TF1
RI + TI
. TF2 + EXF2

0013H
001BH
0023H
002BH

Source

Response Time
The INTO and INTI levels are inverted and latched
into lEO and lEI at S5P2 of every machine cycie. The
values are not actually polled by the circuitry until the
next machine cycle. If a request is active and conditions
are right for it to be acknowledged, a, hardware subroutine call to the requested service routine will be the next
instruction to be executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapse between activation of an external interrupt
request and the beginning of execution of the first instruction of the service routine. Figure 24 shows interrupt response timings.

Execution proj::eeds from that location until the RET!
instruction is encountered. The RETI instruction in-'
forms the processor that this interrupt routine is no
longer in progress, then pops the top two bytes from the
stack and reloads the Program Counter. Execution of
the interrupted program continues from where it left
otT.
Note that a simple RET instruction would also have
returned execution to the interrupted program, but it
would have left the interrupt control system thinking
an interrupt was still in progress.

A longer response time would result if the request is
blocked by one of the 3 previously listed conditions. If
an interrupt of equal or higher priority level is already
in progress, the additional wait time obviously depends
on the nature of the other interrupt's service routine. If
the instruction in progress is not in its final cycle, the
additional'wait time cannot be more than 3 cycles, since
the longest instructions (MUL and DIY) are OIily 4
cycles long, and if the instruction in progress is RET!
or an access to IE or IP, the additional wait time cannot be inore than 5 cycles (a maximum of one more
cycle to complete the instruction in progress, plus 4
cycles to complete the next instruction if the instruction
is MUL or DIY).
Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 9 cycles.

6-22

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

SINGLE-STEP OPERATION

RESET

The 8051 interrupt structure allows single-step execution with very little software overhead. As previously
noted, an interrupt request will not be responded to
while an interrupt of equal priority level is still in progress, nor will it be responded to after RET! until at
least one other instruction has been executed. Thus,
once an interrupt routine has been entered, it cannot be
re-entered until at least one instruction of the interrupted program is executed. One way to use this feature for
single-stop operation is to program one of the external
interrupts (say, INTO) to be level-activated. The service
routine for the interrupt will terminate with the following code:

The reset input is the RST pin, which is the input to a
Schmitt Trigger.
A reset is accomplished by holding the RST pin high
for at least two machine cycles (24 oscillator periods),
while the oscillator is running. The CPU responds by
generating an internal reset, with the timing shown in
Figure 25.
The external reset signal is asynchronous to the internal
clock. The RST"pin is sampled during State 5 Phase 2
of every machine cycle. The port pins will maintain
their current activities for 19 oscillator periods after a
logic 1 has been sampled at the RST pin; that is, for 19
to 31 oscillator periods after the external reset signal
has been applied to the RST pin.

JNB P3.2,$ ;Wait Here Till INTO Goes High
"JB
P3.2,$ ;Now Wait Here Till it Goes Low
RETI
:Go Back and Execute One Instruction

While the RST pin is high, ALE and PSEN are weakly
pulled high. After RST is pulled low, it will take 1 to 2
machine cycles for ALE and PSEN to start clocking.
For this reason, other devices can not be synchronized
to the internal timings of the 8051.

Now if the INTO pin, which is also the P3.2 pin, is held
normally low, the CPU will go right into the External
Interrupt 0 routine and stay there until INTO is pulsed
(from low to high to low). Then i~ will execute RET!,
go back to the task program, execute one instruction,
and immediately re-enter the External Interrupt 0 routine to await the next pulsing of P3.2. One step of the
task program is executed each time P3.2 is pulsed.

The internal reset algorithm writes Os to all the SFRs
except the port latches, the Stack Pointer, and SBUF.
The port latches are initialized to FFH, the Stack
Pointer to 07H, and SBUF is+indeterminate. Table 3
lists the SFRs and their reset values.
The internal RAM is not affected by reset. On power
up the RAM content is indeterminate.

1---12 05C. PERIOD5

---I

1 55 1 56 1 51 1 52 1 53 1 54 1 55 1 56 1 51 1 52 1 53 -1 54 1 55 1 561 51 1 52 1 53 1 541
R5T:

~L IIIIIIIII /~
,

,

5AMPLE R5T

5AMPLE R5T

CINTERNAL RE5ET 51GNAL
-

P5EN:

po:

,
- - 1 1 05C. PERIOD5 -

........, ...- - - - - 1 9 05C. PERIOD5

-----<....,
270252-33

Figure 25. Reset Timing

6-23

intJ

HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Table 3 Reset Values of the SFRs
SFRName

PC
ACC
B
PSW
SP
DPTR
PO-P3
IP (8051)
IP (8052)
IE (8051)
IE (8052)
TMOD
TCON
THO
TLO
TH1
TL1
TH2 (8052)
TL2 (8052)'
RCAP2H (8052)
RCAP2L (8052)
SCON
'SBUF
PCON (HMOS)
PCON(CHMOS)

Reset Value
OOOOH
OOH
OOH
OOH
07H
OOOOH
FFH
XXXOOOOOB
XXOOOOOOB
OXXOOOOOB
oxOOqOOOB
OOH
OOH
OOH
OOH
OOH
OOH
DOH
OOH
OOH
OOH
OOH
Indeterminate
OXXXXXXXB
OXXXOOOOB

POWER-ON RESET
An automatic reset can be obtained when VCC is
turned on by connecting the RST pin to VCC through a
10 /Lf capacitor and to VSS through an 8.2 Kn resistor,
providing the VCC risetime does not exceed a millisecond and the oscillator start-up time does not exceed 10
milliseconds. This power-on reset circuit is shown in
Figure 26. The CHMOS devices do not require the
8.2K pulldown resistor, although its presence does no
harm.
When power is turned on the circuit holds the RST pin
high for an amount of time that depends on the value of
the capacitor and the rate at which it charges. To ensure a good, reset the RST pin must be high long
enough to allow the oscillator time to start up (normally a few msec) plus two machine cycles.
Note that the port pins will be in a random state until the
oscillator has started and the internal reset algorithm
has written Is to them.

With this circuit, reducing VCC quickly to 0 causes the
RSTpin voltage to momentarily fall below OV. Howev, er, this voltage is internally limited, and will not harm
the device.

POWER-SAVING MODES OF
OPERATION
For appiications where power consumption is critical
the CHMOS version provides power reduced modes of
operation as a standard feature. The power down mode
in HMOS devices is no longer it standard feature and is.
being phased out.

CHMOS Power Reduction Modes
CHMOS versions' have two power-reducing modes,
Idle and Pciwer Down. The input through which backup power is supplied during these operations is VCC.
Figure 27 shows the internal circuitry which implelllents these featureS. In the Idle mode (IDL = 1), the
oscillator continues to run and the Interrupt, Serial
Port, and Timer blocks continue to be clocked, but the
clock signal is gated off to the CPU. In Power Down
(PD = I), the oscillator is frozen. The Idle and Power
Down modes are activated by setting bits in Special
Function Register PCON. The address of this register
is 87H. Figure 26 details its contents.

8051

.---,--1 RST
8.2Kll

In the HMOS devices the PCON register only contains
SMOD. The other four bits are implemented only in
the CHMOS devices. User software should never write
Is to unimplemented bits, since they may be used in
future MCS-51 products.

~---;VSS

270252-21

IDLE MODE

Figure 26. Power on ResetClrcult

An instruction that sets PCON.O causes that to be the
last instruction executed before going into the Idle
6-24

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

mode. In the Idle mode, the internal clock signal is
gated off to the CPU, but not to the Interrupt, Timer,
and Serial Port functions. The CPU status is preserved
in its entirety: the Stack Pointer, Program Counter,
Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins
hold the logical states they had at the time Idle was
activated. ALE and PSEN hold at logic high levels.

The flag bits GFO and GFI can be used to give an
indication if an interrupt occurred during normal operation or during an Idle. For example, an instruction
that activates Idle can also set one or both flag bits.
When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.

There are two ways to terminate the Idle. Activation of
any enabled interrupt will cause PCON.O to be cleared
by hardware, terminating the Idle mode. The interrupt
will be serviced, and following RETI the next instruction to' be executed will be the one following the instruction that put the device into Idle.

~

XTAL 2

=

XTAL 1

INTERRUPT,
i-r-C>SERIAL PORT,
TIMER BLOCKS
CPU

POWER DOWN MODE

Figure 27. Idle and Power Down Hardware
(MSB)

(LSB)
GF1

GFO

PD

IDL

Symbol

Posltlo'n

Name and Function

SMOD

PCON.7

Double Baud rate bit. When set to a 1
and Timer 1 is used to generate baud
rate, and the Serial Port is used in
modes 1, 2, or 3.

PCON.S

(Reserved)

PCON.5

(Reserved)

PCON.4

(Reserved)

GF1

PCON.3

General-purpose flag bit.

GFO

PCON.2

General-purpose flag bit.

PD

PCON.1

Power Down bit. Setting this bit
activates power down operation.

IDL

PCON.O

Idle mode bit. Setting this bit activates
idle mode operation.

The signal at the RST pin clears the IDL bit directly
and asynchronously. At this time the CPU resumes
program execution from where it left off; that is, at the
instruction following the one that invoked the Idle
Mode. As shown in Figure 25, two or three machine
cycles of program execution may take place before the
internal reset algorithm takes control. On-chip hardware inhibits access to the internal RAM during this
time, but access to the port pins is not inhibited. To,
eliminate the possibility of unexpected outputs at the
port pins, the instruction following the one that invokes
Idle should not be one that writes to a port pin or to
external Data RAM.

An instruction that sets PCON.l causes that to be the
last instruction executed' before going into the Power
Down mode: In the Power Down mode, the on-chip
oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Special
Function Registers are. held. The port pins output the
values held by their respective SFRs. ALE and PSEN
output lows.

270252-22

SMOD

The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only
two machine cycles (24 oscillatoi- periods) to complete
the reset.

The only exit from Power Down for the 80C5l is a
hardware reset. Reset redefines all. the SFRs, but does
not change the on-chip RAM.
In the Power Down mode of operation, VCC can be
reduced to as low as 2V. Care must be taken, however,
to ensure that VCC is not reduced before the Power
Down mode is invoked, and that VCC is restored to its
normal operating level, before the Power Down mode is
terminated. The reset that terminates Power Down also
frees the' oscillator. The reset should not be activated
before VCC is restored to its normal ,operating level,
and must be held active long enough to allow the oscillator to restart and stahilize (normally less than 10
msec).
'
,

If 1s are written to PD and IDL at the same time, PD takes
Precedence. The reset value of PCON is (OXXXOOOO).
In the HM0S devices the PCON register only contains
SMOD. The other four bits are implemented only in the
CHMOS devices. User software should never write 1s to
unimplemented bits, since they may be used in future MCS51 products.

EPROM VERSIONS
The EPROM versions of these devices are listed in Table 4. The 8751H programs at VPP = 21V using one
50 msec PROG pulse per byte programmed. This results in at6tal programming time (4K bytes) of approximately 4 minutes.

Figure 28. PCON: Power Control Register
6-25

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

Table 4. EPROM Versions of the 8051 and 8052
Device
Name

EPROM
Version

EPROM
Bytes

Ckt
Type

VPP

Time Required to
Program Entire Array

B051

(B751)

4K

HMOS

.21.0V

4 minutes

B051AH

B751H

4K

HMOS

21.0V

4 minutes

BOC51BH

B7C51

4K

CHMOS

12.75V:

13 seconds

B052AH

B752BH

BK

HMOS

12.75V

26 seconds

The 87S2BH and 87CS1 use the faster "Quick-Pulse"
programming™ algorithm. These devices program at
VPP = 12.7SV using a series of twenty-five 100 p.s
PROG pulses per byte programmed. This results in a
total programming time of approximately 26 seconds
for the 87S2BH (8K bytes) and 13 seconds for the
87CS1 (4K bytes).

87C51 AND 8752BH

The 87CS1 and 87S2BH contain two Program Memory
locking schemes: Encrypted Verify and Lock Bits.
Encrypted Verify: These devices implement a 32-byte
EPROM array that can be programmed by the customer, and which can then be used to encrypt the program
code bytes during EPROM verification. The EPROM
verification procedure is performed as usual, except
that each code byte comes out X-NORed ~th one of
the 32 key bytes. The key bytes are gone through in
sequence. Therefore, to read the ROM code, one has to
know the 32 key bytes in their proper sequence.

Detailed procedures for programming and verifying
each device are given in the data sheets.
EXPOSURE TO LIGHT

It is good practice to cover the EPROM window with
an opaque label when the device is in operation. This is
not so much to protect the EPROM array·from inadvertent erasure, but to protect the RAM and other onchip logic. Allowing light to impinge on the silicon die
while the device is operating can cause logical malfunction.

Unprogrammed bytes have the value FFH. Therefore,
if the Encryption Array is lc;ft unprogrammed all the
key bytes have the value FFH. Since any code byte
X-NORed with FFH leaves the code byte. unchanged,
leaving the Encryption Array unprogrammed in effect
bypasses the encryption feature.
LOck Bits: Also on the chip are two Lock Bits which
can be left unprogrammed (U) or programmed (P) to
obtain the following features:

Program Memory Locks
In some micro controller applications it is desirable that
the Program Memory be secure from software piracy.
Intel has responded to this. need by implementing a
Program Memory locking scheme in some of the MCSSl devices. While it is impossible· for anyone to guarantee absolute security against all levels of technological
sophistication, the Program Memory locks in the MCSSI devices will present a formidable barrier against Hiegal readout of protected software.
8751H

The 87S1H contains· a lock bit which, once programmed, denies electrical access by any external
means to.the on-chip Program Memory. The effect .of
this lock bit is that while it is programmed the internal
Program Memory can not be read out, the device can
not be further programmed, and it can not execute external Program Memory. Erasing the EPROM array
deactivates the lock bit and restores the device's full
functionality. It can then be r~programmed.

Bit 2

Bit 1

Additional Features

U

U

None

U

P

• Externally fetched code can not
access internal Program Memory.
• Further programming disabled.

P

U

(Reserved for Future definition.)

P

P

• Externally fetched code can not
access internal Program Memory.
• Further programming disabled. .
• Program verification is disabled.

When Lock Bit 1 is programmed, the logic level at the
EA pin is sampled and latched during reset. If the d~
vice is powered up without a reset, the latch initializes
to a random value, and holds that value until reset is
activated. It is necessary that the latched value of EA
be in agreement with the current logic level at that pin
in order for the device to function properly.

The procedure·for programming the lock bit is detailed
in the 87S1H data sheet.
6-26

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

ONCE Mode in the 87C51

Normal operation is restored after a normal reset is
applied.

The ONCE ("on-circuit emulation") mode facilitates
testing and debugging of systems using the 87C51 without the 87C51 having to be removed from the circuit.
The ONCE mode is invoked by:

THE ON-CHIP OSCILLATORS
HMOS Versions

1. Pull ALE low while the device is in reset and PSEN
is high;

The on-chip oscillator circuitry for the HMOS
(HMOS-I and HMOS-II) members of the MCS-51 family is a single stage linear inverter (Figure 29), intended
for use as a crystal-controlled, positive reactance oscillator (Figure 30). In this application the crystal is operated in its fundamental response mode as an inductive
reactance in parallel resonance with capacitance external to the crystal.

2. Hold ALE low as RST is deactivated.
While the device is in ONCE mode, the Port 0 pins go
into a float state, and the other port pins and ALE and
PSEN are weakly pulled high. The oscillator circuit
remains active. While the 87C51 is in this mode, an
emulator or test CPU can be used to drive the circuit.

Vee

TO INTERNAL
TIMINGCKTS

XTAL2
XTAL1

if

SUBST.

270252-23

Figure 29. On-Chip Oscillator Circuitry in the HMOS Versions of the MCS®-51 Family

Q2
TO INTERNAL
TIMING CKTS

Vss

~-t---QUARTZ

CRYSTAL
OR CERAMIC RESONATOR

270252-24

Figure 30. Using the HMOS On-Chip Oscillator

6-27

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

The crystal specifications and capacitance values (Cl
and C2 in Figure 30) are not critical. 30 pF can be used
in these positions at any frequency with good quality
crystals. A ceramic resonator can be used in place of
the crystal iii cost-sensitive applications. When a ceramic resonator is used, Cl and C2 are normally selected to be of somewhat higher values, typicaIly, 47 pF.
The manufacturer of the ceramic resonator should be
consulted for recommendations on the values of these
capacitors.

To drive the HMOS parts with an external .clock
source, apply the external clock signal to XTAL2, and
ground XTALl, as shown in Figure 31. A pullup resistor may be used (to increase noise margin), but is optional if VOH of the driving gate exceeds the VlH MIN
specification of XTAL2.

CHMOS VERSIONS
The on-chip oscillator circuitry for the 80C5IBH,
shown in Figure 32, consists of a single stage linear
inverter intended for use as a crystal-controlled, positive reactance oscillator in the same manner as the
HMOS parts. However, there are some important differences.

A more in-depth discussion of crystal specifications, ceramic resonators, and the selection of values for Cl and
C2 can be found in Application Note AP-155, "Oscillators for Microcontrollers," which is included in this
manual.

One difference is that the 80C5IBH is able to tum off
its oscillator under software control (by writing a 1 to
the PO bit in PCON). Another difference is that in the
80C51BH the internal clocking circuitry is driven by
the signal at XTALl, whereas in the HMOS versions it
is by the signal at XTAL2.

Vcc
r
8051
EXTERNAL
OSCILLATOR
SIGNAL

t

::>0-...- - 1 XTAL2

The feedback resistor Rr in Figure 32 consists of paralleled n- and p- channel FETs controlled by the PO bit,
such that Rr is opened when PO = 1. The diodes 01
and 02, which act as clamps to VCC and VSS, are
parasitic to the Rr FETs.

r-- XTAL1

TTL
GATE

~ VSS

WITH
TOTEM-POLE
OUTPUT

270252-25

Figure 31. Driving the HMOS MCS®-S1
Parts with an External Clock Source

Vcc

TO INTERNAL
TIMING CKTS

1

01

4000
XTAL1

XTAL2
D2

PD -----II+---.

270252-26

Figure 32. On-Chip Oscillator Circuitry in the CHMOS Versions of the MCS®-S1 Family
6-28

inter

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

VCC
TO INTERNAL
TIMING CKTS

Rt

VSS
-------80CS1

XTAL1-----

XTAL2------

~--r--QUARTZ

CRYSTAL
OR CERAMIC
RESONATOR

270252-27

Figure 33_ Using the CHMOS On-Chip Oscillator

Rise and fall times are dependent on the external loading that each pin must drive. They are often taken to be
something in the neighborhood of 10 nsec, measured
between 0.8V and 2.0V.

The oscillator can be used with the same external components as the HMOS versions, as shown in Figure 33.
Typically, CI = C2 = 30 pF when the feedback element is a quartz crystal, and CI = C2 = 47 pF when a
ceramic resonator is used.

Propagation delays are different for different pins. For
a given pin they vary with pin loading, temperature,
VCC, and manufacturing lot. If the XTAL2 waveform
is taken as the timing reference, prop delays may vary
from 25 to 125 nsec.

To drive the CHMOS parts with an external clock
source, apply the external clock signal to XTALl, and
leave XTAL2 float, as shown in Figure 34.
The reason for this change from the way the HMOS
part is driven can be seen by comparing Figures 29 and
32. In the HMOS devices the internal timing circuits
are driven by the signal at XTAL2. In the CHMOS
devices the internal timing circuits are driven by the
signal at XTALI.

The AC Timings section of the data sheets do not reference any timing to the XTAL2 waveform. Rather, they
relate the critical edges of control and input signals to
each other. The timings published in the data sheets
include the effects of propagation delays under the
specified test conditions.

80CS1
NC
EXTERNAL
OSCILLATOR
SIGNAL

MCS®-S1 PIN DESCRIPTIONS

XTAL2

VCC: Supply voltage.

t

:>O------i XTAL1

VSS: Circuit ground potential.
VSS

CMOS GATE

Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an open drain output port it can sink 8 LS
TTL loads. Port 0 pins that have Is written to them
float, and in that state will function as high-impedance
imputs. Port 0 is also the multiplexed low-order address
and data bus during accesses to external memory. In
this application it uses strong internal pullups when
emitting Is. Port 0 also emits code bytes during program verification. In that application, external pullups
are required.

270252-28

Figure 34. Driving the CHMOS MCS®-51
Parts with an External Clock Source

INTERNAL TIMING
Figures 35 through 38 show when the various strobe
and port signals are clocked internally. The figures do
not show rise and fall times of the signals, nor do they
show propagation delays between the XTAL2 signal
and events at other pins.

Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can sink/
source 4 LS TTL loads. Port 1 pins that have Is written
6-29

HARDWARE DESCRIPTION OF THE.8051, 8052 AND 80C51

to them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1 pins
that are externally being pulled low will source current
(ilL, on the data sheet) because ofthe internal pullups.
In the 8052, pins P1.0 and Pl.l also serve the alternate
functions of T2 and T2EX. T2 is the Timer 2 external
input. T2EX is the input through which a Timer 2
"capture" is triggered.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can sink/
~ource 4 LS TTL loads. Port 2 emits the high-order
address byte during accesses to external meniory that
use 16-bit addresses. In this application it uses the
strong internal pullups when emitting Is. Port 2 also
receives the high-order address and control bits during
8751H programming and verification, and during program verification in the 8051AH.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. It also serves the functions of various
special features of the MCS-51 Family, as listed below:

Port Pin

Alternate Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6

RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory
write strobe)
RD (external data memory
read strobe)

P3.7

The Port 3 output buffers can source/sink 4 LS TTL
loads.
RST: Reset input. A high on this pin for two machine
cycles while' the oscillator is' running resets the device.
ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses to
external memory. ALE is emitted at a constant rate of
'I. of the oscillator frequency, for external timing or
clocking purposes, even when there are no accesses to
external memory. (However, one ALE pulse is skipped
during each access to external Data Me~ This pin
is also the program pulse input (pROG during
EPROM programming.
PSEN: Program Store Enable is the read strobe to external Program Memory. When the device is executing
out of external Program Memory, PSEN is activated
twice each machine cycle (except that two PSEN activations are~ed during accesses to external Data
Memory). PSEN is not activated when the device is
executing out of internal Program Memory.
EA/VPP: When EA is held high the CPU executes out
of internal Program Memory (unless the Program
Counter exceeds OFFFH in the 8051AH, or IFFFH in
the 8052). Holding EA low forces the CPU to execute
out of externlll memory regardless of the Program
Counter value. In the 8031AH and 8032, EA must be
extremely wired low. In the EPROM devices, this pin
also receives the programming supply voltage (VPP)
during EPROM programming. .
XTALl: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier..

I

STATE

11 STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE 1ISTATE 21

~I~

~I~

~I~

~I~ ~I~

~I~

~I~ ~I~

~~nnnnnnnnnnnnnnnnn

~UUUUUUUUUUUUUUUU~

ALE:

P2:

PCHOUT

PCHOUT

Figure 35. External Program Memory Fetches
6-30

I

PCHOUT

270252-29

intJ

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

I

I

STATE 41 STATE 51 STATE 81 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51

~1P2

~1P2

~1P2

~1P2

~In ~1P2

~1P2

~1P2

XTAL2:

ALE:

RD:

PO:

P2:

PCH OR
P2SFR

PCH OR
P2SFR

DPH OR P2 SFR OUT

270252-30

Figure 36. External Data Memory Read Cycle

I

I

STATE 41 STATE 5 STATE

~1P2

61 STATE 1 ISTATE 2.1 STATE 3.1 STATE 41 STATE 51

~1P2 ~1P2

~1P2

~1P2

~1P2

~1P2 ~1P2

XTAL2:

ALE:

jr-PCLOUTIF

ViR:

IS EXTERNAL

po:

P2

- - - - - I DPL OR RI
OUT

PCH OR
P2SFR

DATA OUT

~f

DPH OR P2 SFR OUT

~

PCH OR
P2SFR
270252-31

Figure 37. External Data Memory Write Cycle.

6-31

HARDWARE DESCRIPTION OF THE 8051, 8052 AND 80C51

I

I

STATE 41 STATE 51 STATE 81 STATE 1 STATE 21 STATE 31 STATE 41 STATE 51

~I~

~I~ ~I~ ~I~ ~I~

~I~ ~I~

~I~

XTAL2:

-

PO'P1~.

-YZ,P1

INPUTS S A M P L E D : .

.

~,P3, R S T = r l -

P2, P3, RST

MOY PORT, SRC:

SERIAL PORT
SHIFT CLOCK
(MODE 0)'

NEW DATA

OLD DATA

---+I

r-- RXD PIN SAMPLED

RXD SAMPLED

--.j

~
270252-32

Figure 38. Port Operation

6-32

Hardware Description of the
83C51FA

7

HARDWARE DESCRIPTION
OF THE 83C51FA (83C252)
INTRODUCTION

Port
Name
Pin

The 83C51FA is an 8-bit control-oriented microcontroller based on the 8051 architecture. The 83C51FA is
an enhanced version of the 80C51BH and incorporates
many new features. These features include:
• Programmable Counter Array with
- Compare/Capture
- High Speed Output
- Pulse Width Modulator
- Watchdog Timer
• Programmable Serial Channel
- Automatic Address Recognition
- Framing Error Detection
• Enhanced Power Down Mode
• 16-Bit Up/Down Timer/Counter
• 8K Factory Mask ROM
• 256 Bytes of On-Chip Data RAM
• 7 Interrupt Sources

P1.2 ECI

Function

External Count Input to the PCA

P1.S CEXO External 110 for Compare/Capture
Module 0
P1.4 CEX1 External I/O for Comparel.Capture
Module 1
P1.5 CEX2 External I/O for Compare/Capture
Module 2
P1,6 CEXS External I/O for Compare/Capture
ModuleS
P1.7 CEX4 External I/O for Compare/Capture
Module 4

The time-base for the PCA is a programmable 16-bit
timer/counter. This timer is the only one that can serve
the PCA. This timer is started or stopped by setting or
clearing bit CR in the Special Function Register
CCON, and can be programmed to count any of the
following signals (where Fosc is the 83C51FA oscillator frequency):

The 83C51FA uses the standard 8051 instruction set
and is pin for pin compatible with the existing
MCS®-5l products, However, the numbering system
for the 83C51FA is slightly different. The 83C51FA is
the factory masked ROM device; the 80C51FA is the
ROMless device; and the 87C51FA is the EPROM device.

• Fosc/12
The Counter increments once per machine cycle.
• Fosc/4
With a 16 MHz crystal, the counter increments once
every 250 ns.

It is assumed that the reader is familiar with the 8051

architecture. For more detailed information on the
8051, consult the "Hardware Description of the 8051
and 8052" chapter.

• Timer 0 overflow
The counteds incremented whenever Timer 0 overflows. This mode allows a programmable input frequency to the PCA.
• External input on ECI pin
The counter is incremented when a I-to-O transition
is detected on the ECI pin. The counter is limited to
input frequencies of Fosc/8 in this mode.

OVERVIEW OF THE PCA
The Programmable Timer/Counter Array (PCA) consists of a 16-bit counter and five 16-bit compare/capture modules. Each compare/capture module has its
own mode register, CCAPMn, which is used to configure the module. The compare/capture modules and the
PCA counter share Port 1 pins for hardware interfacing
as shown below:

The 16-bit PCA timer/counter can also be programmed to either run or pause when the CPU is in
Idle mode.

7-1

intJ

HARDWARE DESCRIPTION OF THE 83C51FA

High speed output mode, an interrupt can be generated
when the module executes its function.

Each of the five 16-bit compare/capture modules can
be programmed to do one of the following:
• 16-bit capture; positive edge activated.
• 16-bit capture, negative edge activated.
• 16-bit capture, both positive and negative edge activated.
• 16-bit software timer.
• High-speed output.
• 8-bit Pulse Width Modulator (PWM).

DESCRIPTION OF THE PCA
HARDWARE
The time base for the PCA is a 16-bit timer/counter
consisting of registers CH and CL (high and low bytes
of the count value), controlled by Special Function
Register CCON (Figure 1) and a mode register CMOD
(Figure 2).

In addition, Compare/Capture module 4 can be used as
a Watchdog Timer.

CCON contains bits CF (Counter Flag) which gets set
by hardware when the counter rolls over and CR
(Counter Run) which is used to tum the counter on
and off. It also contains interrupt flags from each of the
five PCA modules.

When any o.f the compare/capture modules. are programmed to the capture mode or the 16-bit .Timer/

CF

CR

CCF4

CCF3

CCF2

CCF1

CCFO·

Reset Value = OOXOOOOOB

Address = OD8H

Symbol

Position

CF

CCON.7

Function

CR

CCON.S

Counter Run control bit. Set by software to turn the PCA
counter on. Clear by software to turn the PCA counter off.

PCA Counter Overflow flag. Set by hardware when the
counter rolls over. CF flags an interrupt if bit ECF in CMOD is
. set. CF may be set by either hardware or software. It can only
be cleared by software.

-

CCON.5

Not implemented, reserved for future use. •

CCF4

CCON.4

PCA Module 4 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.

CCF3

CCON.3

PCA Module 3 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.

CCF2

CCON.2

PCA Module 2 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.

CCF1

CCON.1

PCA Module 1 interrupt flag. Set by hardware when a match or
capture occurs. Must be cieared by sonware.

CCFO

CCON.O

PCA Module 0 interrupt flag. Set by hardware when a match or
capture occurs. Must be cleared by software.

Figure 1. CCON: Counter Control Register
NOTE:
'User software should not write'1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
reserved bit is indeterminate.

7-2

inter

HARDWARE DESCRIPTION OF THE 83C51FA

CMOD contains the following bits:
CIDL- selects whether the PCA counter continues to
run in Idle Mode
WDTE- enables the Watchdog Timer function
CIDL

CPS! and CPSO-select the counter input
ECF- enables CF to generate an interrupt.

WDTE
Address

=

CPS1

OD9H

CPSO

ECF

Reset Value = OOXXXOOOB

Symbol

Position

Function

CIDL

CMOD.7

Counter Idle control: CIDL = 0 programs PCA Counter to continue
functioning during Idle mode. CIDL = 1 programs it to be gated off during
Idle.

WDTE

CMOD.6

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function.
WDTE = 1 enables it.

-

CMOD.5

Not implem~nted, reserved for future use. •

-

CMODA

Not implemented, reserved for future use.'

-

CMOD.3

Not implemented, reserved for future use.'

CPS1

CMOD.2

Count Pulse Select bit 1.

CPSO

CMOD.1

Count Pulse Select bit

ECF

CMOD.O

o.

CPS1

CPSO

0
0
1
1

0
1
0
1

PCA Count Pulse Selected
Internal clock, Fosc/12
Internal clock, Fosc/4
Timer 0 overflow
External clock at ECI pin (P1.2)
(maximum rate = Fosc/a)

Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to
generate an interrupt. ECF = 0 disables that function of CF.
Figure 2. CMOD: Counter Mode Register

NOTE:

'User software should not write 1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
reserved bit is indeterminate.

Each of the five PCA modules has a Compare/Capture
Mode register, CCAPMn, n = 0 through 4 (Figure 3).
The following bits in each CCAPMn register define
that module's function.
ECOMn- enables that module's comparator function
CAPPn- enables the capture function on positive
transitions at theCEXn pin
CAPNn- enables the capture function on negative
transitions at the CEXn pin

MATn-

enables a comparator match to set the corresponding CCFn flag
TOGn- enables a comparator match to toggle the
CEXnpin
PWMn- enables the PWM output at the CEXn pin
ECCFn- enables any Compare/Capture event to flag
an interrupt

7-3

intJ

HARDWARE DESCRIPTION OF THE 83C51FA

ECOMn

CAPPn

CAPNn

TOGn

MATn

Addresses = OOAH (n = 0)
OOBH (n= 1)
OOCH(n=2)
OOOH (n=3)
OOEH (n=4)

PWMn

ECCFn

Reset Value = XOOOOOOOB

Symbol

Position

ECOMn

CCAPMn.7
CCAPMn.6

Function
Not implemented, reserved for future use.·
ECOMn = 1 enables the comparator function. This bit is
automatically cleared by any write to the CCAPnL register,
and automatically set by any write to the CCAPnH register.
This prevents unintended matches from occurring during
writes to the 16:bit Compare/Capture register.

CAPPn

CCAPMn.5

Positive edge capture enable. When CAPPn = 1, a positive
transition at the CEXn pin triggers a 16-bit capture from the
PCA counter to this module'S Compare/Capture register.

CAPNn

CCAPMn.4

MATn

CCAPMn.3

TOGn

CCAPMn.2

PWMn

CCAPMn.1

Negative edge capture enable. When CAPNn = 1, a negative
transition at the CEXn pin triggers a 16-bit capture from the
PCA counter to this module's Compare/Capture register.
When MATn = 1, a match of the PCA Counter with this
module'S Compare/Capture register causes the CCFn bit in
.. CCON to be set, flagging an interrupt.
When TOGn = 1, a match of the PCA Counter with this
module's Compare/Capture register causes the CEXn pin to
toggle.
When PWMn = 1, CEXn is driven high when the low byte of
the PCA Counter (CL) matches the low byte of this module's
Compare/Capture register (CCAPnL). When CL rolls over to
OOH, the CEXn pin is driven low and CCAPnL is updated with
the valLie in CCAPnH. This enables the CEXn pin to be used
as a pulse width modulated output. Software varies the pulse
. width by writing to CCAPnH,

ECCFn

CCAPMn.O

-

Enables Compare/Capture Flag CCFn in the CCON register to
generate an interrupt.

Figure 3. CCAPMn: Compare/Capture Mode Register for PCA Module n
NOTE:
'User software should not write 1s to reserved bits. These bits may be used in future MCS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
i6served bit is indateimlnate.

There are 6 modes of operation for each of the 5. PCA
modules: Shown below are the combinations of bits in
the CCAPMn register that are valid and have a

defined function. Invalid combinations will produce undefined results.

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

0

0
1

0
0

0
0

0
0

0

X

0
0

X

X

0

1

0

0

0

X

X

1

1

0

0

0

X

1
1
1

0
0
0

0
0
0

1
1

0
1

0
0

.x

0

0

1

0

x=

Don't Care

7-4

X

Module Function
No operation
16-bit capture by a positive-edge
trigger on CEXn
16-bit capture by a negativecedge
trigger on CEXn
16-bit capture by a transition
on CEXn
16-bit software timer
High Speed Output
a-bit PWM

inter

HARDWARE DESCRIPTION OF THE 83C51FA

16-Bit TimerICounter

16-Bit Capture Mode

The 5 Compare/Capture modules share a 16-bit timer/
counter as their "time base". The timer/counter, shown
in Figure 4, can be programmed to increment in 4 different ways. The modes are shown below with the setup
values in the CMOD register:

Setting CAPPn and/or CAPNn puts Compare/Capture module n into Input Capture mode, as shown in
Figure 5. The external input pins CEXO through CEX4
are sampled for a transition. When a valid transition is
detected for the current mode of operation (rising edge,
falling edge, or either edge), CL is transferred into the
CCAPnL register, and CH is transferred into
CCAPnH. The resulting value in the Capture Registers, CCAPnL and CCAPnH, reflect the values in CL
and CH at the time a transition was detected on the
CEXn pin. The event flags an interrupt if bit ECCFn is
set.

CPS1 CPSO

Method of Incrementing

0

0

Internally clocked at Oscillator
Frequency 112

0

1

Internally clocked at Oscillator
Frequency 14

1

0

Incremented when Timer 0 overflows

1

1

Externally clocked on Pin P1.2/ECI.
(Limited to Oscillator Frequency 18)

TO PCA MODULES 0-4

COUNT

INTERRUPT

ENABLE

Fosc/12
Fosc/4
TIMER 0
OVERFLOW

'-t===:..:::::t-----[]ECI

270421-1

Figure 4. PCA Timer/Counter

7-5

HARDWARE DESCRIPTION OF THE 83C51FA

PCA TIMER / COUNTER VALUE

CEXn

CCAPMn REGISTER
270421-2

n = 0, 1, 2, 3 or 4
x = Don'l Care

Figure 5. 16-Blt Capture Mode

with the count value of the counter module. When they
are equal, a match signal is generated which can set the
status bit CCFn in· the PCA COntrol register CCON
and/or toggle the corresponding CEXn pin.

16 Bit Timer
Setting bit ECOMn in the Compare/Capture. Mode
Register (CCAPMn) enables the Comparator function
as shown in Figure 6. The Comparator compares a
16-bit value stored in the compare/capture register

WOTE
(MODULE 4 ONLY)
_

PCA TIMER

I

. L____-

r-----------,

COUNTER VALUE
16

II

CAUSE
RESET

r----------~---------_1---------~

WRITE TO
. CCAPnL
RESET

------L..;

WRITE TO
CCAPnH

270421-3

n = 0, 1, 2, 3 or 4
x = Don'l Care

Figure 6. 16-Bit Comparator Mode

7-6

inter

HARDWARE DESCRIPTION OF THE 83C51FA

reverses the logic level of its" I/O pin, and/or can generate an interrupt as shown in Figure 6. When the PCA
module is configured in this manner as a High Speed
Output, the user, by setting or clearing the pin in software, can select whether the module's output pin will
change from a logical 0 to a logical 1 or vice versa.

Bit ECOMn is set by software and is initially cleared
during reset. It also gets cleared when a write to
CCAPnL register happens and is set if CCAPnH is
written to. This feature prevents ·action until the complete 16-bit value is loaded into the CCAPnH/L register if the low value is written to the 16-bit register first.
When the MATn (Match) bit is set in the Compare/
Capture Mode Register, the corresponding module in
the PCA is configured as a 16-bit timer. When the value in the 16-bit Compare/Capture register is equal to
the 16-bit value on the Count Bus, the hardware sets
the CCFn flag. This bit flags an interrupt if ECCFn is
also set.

Pulse Width Modulator Mode
Any or all of the 5 modules of the PCA can be programmed to be a Pulse Width Modulator as shown in
Figure 7. In this mode, the PWM output can be used to
convert digital data to an analog signal by simple external circuitry. The frequency of the PWM depends on
which of the four clock sources is selected for the PCA
Timer. With a 16 MHz crystal the maximum frequency
of the output waveform/of the PWM is 15.6 KHz. The
duty cycle of the waveform is controlled by the contents of an 8-bit register (CCAPnH) that can be programmed to be any integer" from 0 to 255.

High Speed Output
When programmed as a timer, the PCA module, during every cycle, compares the contents of the 16-bit
timer with the preset value of its Compare registers.
When a match" occurs, if bit TOGn is set, the module"

270421-4

n = 0, 1, 2, 3 or 4

x

=

Don't Care
Figure 7. 8-Bit PWM Mode

7-7

intJ

HARDWARE DESCRIPTION OF THE 83C51FA

not activated unless the received byte is an address byte
(9th data bit = I), and the address corresponds to either a Given Address or a Broadcast Address.

Watch Dog Timer Mode
A Watchdog Timer js a circuit that automatically invokes a reset unless the system being watched sends
regular hold-off signals to the Watchdog. These circuits
are used in applications that are subject to electrical
noise, power glitches, electrostatic discharges, etc., or
where high reliability is required with hands-off operation.

The feature works the same way in the 8-bit mode
(mode I) as in the 9-bit modes, except that the stop bit
takes the place of the 9th data bit. That is, if SM2 is set,
RI is not activated unless the received byte agrees with
either the Given or Broadcast address and is terminated
by a valid stop bit.

In this mode, every time the count in the PCA counter
module matches the value 'stored in compare/capture
module 4, an internal reset is generated. The' bit that
selects this mode is WDTE in the CMOD register.
Compare/capture module 4 should be set up to be a
16-bit timer or a High Speed Output in the Watchdog
Timer mode.
'

The Given Address is specified by the contents of two
new SFRs: SADDR and SADEN. The 83C51FA's individual address is defined in SADDR. SADEN is a
mask byte that defines don't-cares in SADDR to form '
the Given Address. For example,
SADDR = 01010110
SADEN = 11111100

To hold off the reset, the user's software can:
• Continually reset the PCA 16-bit timer value to a
lower value than the reset value in module 4.
• Clear the WDTE bit when a match is about to occur, and then set the WDTE bit just after the match
condition (temporarily disabling the feature).
or
• Continually change the CCAP4H and CCAP4L value to one that is "far" from a match value.

spec,ify the Given Address to be OIOIOIXX.
The Broadcast. Address is formed from the logical OR
of SADDR and SADEN. Zeros in the logical OR are
don't-cares. For example, the values given above for
SADDR and SADEN defme the broadcast address to
be 11 111 11X.
Automatic Address Recognition allows a host processor to establish communication -with an addressed
slave, without all the other slave controllers having to
respond to the transmission. The addressed slave then
clears its SM2 bit to enable reception of data bytes (9th
data bit = 0) from the host.

Finally, the Watchdog Timer can be used to program a
reset by allowing a match to occur.

EXTENDED SERIAL PORT FEATURES

The Given and Broadcast addresses allow each microcontroller to have its own (Given) address and a common (Broadcast) address. A "host" on the serial channel can selectively address single 83C51FA's using the
'Given Address or all 83C51FA's using the Broadcast
Address.

The full duplex serial port of the 83C51FA is the same
as the serial port of the 8052 but with two added features: Automatic Address Recognition and Framing
Error Detection.

On reset, the SADDR and SADEN registers are initialized to OOH. This defines the Given and Broadcast addresses to be XXXXXXXX (all don't-cares) for backwards compatibility with the MCS®-51 family.

Automatic Address Recognition
Automatic Address Recognition is useful in multi-processor applications in which the CPUs communicate
through the serial channel. Using this feature, the
83C51FA's Serial Port refrains from interrupting the
CPU unless it receives its own address. Automatic Address Recognition is enabled by setting the SM2 bit in
SCON.
-

Framing Error Detection
Another new feature of the Serial Port is Framing Error Detection. This allows the receiving controller to
check the stop bit in modes I, 2, or 3. A missing stop
bit causes a Framing Error bit, FE, to be set. The FE
bit can then be checked in software immediately after
each reception to detect the lack of a valid stop bit. A
missing stop bit can be caused, for example, by noise on
the serial lines, or by two CPUs trying to transmit at
the same time.

Normally the Serial Port would be configured into either of the 9-bit modes (modes 2 and 3). In these
modes, if SM2 is set, the Receive Interrupt flag RI is

7-8

inter

HARDWARE DESCRIPTION OF THE 83C51FA

The FE bit, once set, must be cleared in software. A
valid stop bit does not cause the FE bit to be cleared.

iced, the next instruction executed after RETI will be
the one following the instruction that put the device in
Power Down.

The FE bit resides in SCON, and has the same bit address as the SMO bit. A new control bit in the PCON
register determines if accesses to the SMO/FE bit address are to SMO or to FE. The new control bit in
PCON is called SMODO, and resides at PCON.6 (Figure 8). IfSMODO = 0, then accesses to SCON.7 are to
SMO. IfSMODO = I, then accesses to SCON.7 are to
FE.

Power Off Flag
A Power Off Flag, POF, has been added to the PCON
register (Figure 8). This flag is set by hardware when
VCC comes up, and can be set or cleared by software.
This allows one to distinguish between a "cold start"
reset and a "warm start" reset.

REDUCED POWER MODES
Idle Mode
Idle Mode is the same in the 83C51FA as in the
80C5IBH. Note that the PCA can be programmed to·
either pause or continue operations during Idle.

Power Down Mode
The Power Down Mode on the 83C51FA differs from
the SOC5IBH in one respect: the 83C51FA can exit
Power Down with either a hardware Reset or an External Interrupt. (The 80C5IBH can only exit Power
Down with a hardware Reset.) An exit with an External Interrupt allows not only the on-chip RAM to be
saved but also the Special Function Registers.

SMOOO

x

To use the feature, one checks the POF bit in software
immediately after reset. POF = I would indicate a
cold start. The software then clears POF, and commences its tasks. POF = 0 immediately after reset
would indicate a warm start.
VCC must remain above 3 volts for POF to retain a

o.

TIMER 2 AS AN UP/DOWN COUNTER
Timer 2 is a general purpose 16-bit timer/counter
which is present in the 8052 and in the 83C51FA. Timer 2 has the same functionality in both of these devices
except that in the 8052 Timer 2 can only count up, and
in the 83C51FA Timer 2 can be programmed to count
up or down. The option to count up or down becomes
available when the Timer is configured to its 16-bit
auto-reload mode.

The External Interrupt, INTO or INTI, must be enabled and configured as level-sensitive to properly terminate Power Down. Also the interrupt should not be
executed before Vee is restored to its normal operating
level, and must be held down long enough for the oscillator to restart and stabilize. Once the interrupt is servSM001

A cold start reset is one that is coincident with VCC
being turned on to the device after it was turned off. A
warm start reset is one that. occurs after the device has
already been powered up and running. A warm start
reset could be generated, for example, by a Watchdog
Timer, or as an exit from Power Down Mode.

POF

GF1

Address = 087H

GFO

PO

IOL

. Reset Value = OOXXOOOOB

POF

Power Off Flag. Set by hardware on the rising edge of Vee. Set or cleared by software. This flag allows
detection.of a power failure caused reset. Vee must remain above 3V to retain this bit.
SMODO When set, Read/Writc:: accesses to SCON.7 are to the FE bit. When clear, Read/Write. accesses to
SCON.7 are to the SMO bit.
SMODI Same as the SMOD bit in the MSC-51 architecture. The additional bits are defined to be compatible with
the 8052 and 80C51BH.
Figure 8. PCON: Power Control Register

7-9

inter
x

HARDWARE DESCRIPTION OF THE 83C51FA

x

x

x

x

x

x

DCEN

Reset Value = XXXX XXXOB
Address = OC9H
When set, this bit allows Timer 2 to be configured as an up/down counter.
Figure 9. T2MOD: Timer 2 Mode Control Register

DCEN

~
~

.~

!C/f2=o

T2 PIN ------~

T2EX PIN

TIMER 2
INTERRUPT

------+1
EXEN2

270421-5

Figure 10. Timer 2 Auto-Reload Mode when DCEN = 0
The Special Function Register T2MOD (present in the
83C51FA but not in the 8052) contains a bit named
DCEN (Down Counter Enable). T2MOD is shown in
Figure 9. When this bit is clear (0), the Timer 2 AutoReload Mode in the 83C51FA is exactly the same as iii
the 8052. Figure,IO shows Timer 2 in Auto-Reload
Mode with DCEN = o.

When DCEN is set (I), the Timer 2 Auto-Reload Mode
takes the form shown in Figure 11. The T2EX pin now
controls the direction of count. A logic 1 at T2EX
makes Timer 2 count up. A logic 0 at T2EX makes
Timer 2 count down. Also, the EXF2 bit toggles every
time Timer 2 overflows or underflows. In this operating
mode, the EXF2 bit does not flag an interrupt.

270421-6

Figure 11. Timer 2 Auto-Reload Mode when DC EN
7-10

=:'

1

HARDWARE DESCRIPTION OF THE 83C51FA

UPPER 128 BYTES OF RAM

FUNCTIONS OF PORT 1 PINS

The 83C51FA implements a full 256 bytes of on-chip
data RAM. As in the 8052, the upper 128 bytes occupy
a parallel address space to the Special Function Registers. That means they have the same addresses, but they
are physically separate from SFR space.

P1.0/T2 may be used as an external count input to
Timer 2.
Pl.l/T2EX can be used to trigger a capture if Timer 2
is in the Capture Mode, or to trigger a reload if Timer 2
is in the Auto-Reload Mode and DCEN is set to O.
T2EX can also control the count direction if Timer 2 is
in the Auto-Reload Mode and DCEN set to 1. Finally,
T2EX can be used as an external interrupt if Timer 2 is
being used as a baud-rate generator.

When an instruction accesses an internal location above
address 7FH, the CPU knows whether the access is to
the upper 128 bytes of data RAM or to SFR space by
the addressing mode used in the instruction. Instructions that use direct addressing access SFR space. For
example,
MOV OAOH, # data

P1.2/ECI takes the external signal to the PCA counter.
The frequency of the external signal is limited to one
eighth of the oscillator frequency or less. The PCA
count is incremented every time the ECI pin makes a
1-0 transition.
.

accesses the SFR at location OAOH (which is P2). Instructions that use indirect addressing access the upper
128 bytes of data RAM. For example,
MOV @RO,#data

P1.3 through P1.7/CEXn functions depend on the configuration of their corresponding Compare/Capture
modules in the PCA. They can be configured to be a
rising edge, falling edge, or an "either edge" trigger
input to a Compare/Capture module. They can also be
high speed outputs which toggle every time the PCA
count matches the value in the corresponding Compare/Capture register. Finally, any of these pins can be
configured as an 8-bit Pulse Width Modulated (PWM)
output. In the PWM mode, the pin will be in the logical
"0" state for a programmable length of time, and will
be in the logical "1" state for· the remainder of the
PWM duty cycle. The PWM duty cycle is variable between 1/256 and 256/256.

~here RO contains OAOH, accesses the data byte at address OAOH, rather than P2 (whose address is OAOH).

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

PIN DESCRIPTION
The 83C51FA is Pin-for-Pin compatible with the
80C51BH. Port 1 on the 83C51FA has 8052 functionality and additionally serves the PCA as shown below.

Detailed descriptions of the functions of the PCA pins
can also be found in section 1.2, PCA feature description.

Port 1 pins and Alternate Functions.
Port
Name
Pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

Function

INTERRUPT STRUCTURE

T2
External Count Input to Timer 2
T2EX Timer 2 Capture/Reload Trigger
ECI
External Count Input to the PCA
CEXO External 1/0 for Compare/Capture
Module 0
CEX1 External 1/0 for Compare/Capture
Module 1
CEX2 External 1/0 for Compare/Capture
Module 2
CEX3 External 110 for Compare/Capture
Module 3
CEX4 External 110 for Compare/Capture
Module 4

The 83C51FA provides 7 interrupt sources. Five of
them (INTO/ and INTI/, Timer 0 and Timer I, and
the Serial Port) are identical with those provided in the
80C51BH. The 83C51FA also provides a Timer 2 interrupt which is identical with the Timer 2 interrupt in the
8052, and a PCA interrupt which is only found in the
83C51FA. These interrupt sources are shown in Figure
12.

7-11

HARDWARE DESCRIPTION OF THE 83C51FA

INTO---cY

ITO

TFO-------------------------.~

INT1,...---<:r-

TF1------------------------.~

INTERRUPT
SOURCES
CF-3ECF

5

~\--------..,D)--------------+~

...,D.·. ____________•

TF2 _ _ _ _ _ _ _ _
EXF2-

~

,-

270421-7

(Sea oxceptions ,,·,hen Timer 2 is used as baud rate gl3l"!Aratnr or an up/down counter.)

Figure 12. 83C51FA Interrupt Sources

The Timer 2 interrupt is generated by the logical OR of
TF2 and EXF2. Neither of these flags is cleared by
hardware when the service routine is vectored to. In
fact, the service routine may have to determine whether
it was TF2 or EXF2 that generated the interrupt, and
the bit will have to be cleared in software.

All of the bits that generate interrupts can be set or
cleared in software, with the same result as though it
had been set or Cleared by hardware. That is, interrupts
can be generated or pending interrupts can be cancelled
in software. .
.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special
Function Register IE (Figure 13). Note that IE also
contains a global disable bit, EA. If EA is set (I), the
interrupts· are individually enabled or disabled by their
corresponding bits in IE. If EA is clear (0), all interrupts are disabled.

The PCA interrupt is generated by the logical OR of
CF, CCFO, CCF1, CCF2, CCF3, and CCF4. None of
these flags is Cleared by hardware when the service routine is vectored to. In fact, normally the service routine
will have to determine which bit flagged the interrupt
and clear that bit in software.

7-12

1
\

HARDWARE DESCRIPTION OF THE 83C51FA
I

EA

EC

ET2

ES

ET1

Address = OASH

EX1

EXO

ETO

Reset Value = OOOOOOOOB

Symbol

Position

Function

EA

1E.7

Disables all interrupts. If EA = 0, all interrupts are disabled. If
EA = 1, each interrupt can be individually enabled or disabled
by setting or clearing its enable bit.

EC

IE.6

Enables or disables the PCA interrupt. EC = 1 enables it.
EC = 0 disables it.

ET2

IE.5

Enables or disables the Timer 2 interrupt. ET2 = 1 enables it.
ET2 = 0 disables it.

ES

lEA

Enables or disables the Serial Port interrupt. ES = 1 enables
it. ES = 0 disables it.

ET1

1E.3

Enables or disables the Timer 1 interrupt. ET1 = 1 enables it.
ET1 = 0 disables it.

EX1

IE.2

Enables or disables External Interrupt 1. EX1 = 1 enables it.
EX1 = 0 disables it.

ETO

IE.1

Enables or disables the Timer 0 interrupt. ETO = 1 enables it.
ETO = 0 disables it.

EXO

IE.O

Enables or disables External Interrupt O. EXO = 1 enables it.
EXO = 0 disables it.
Figure 13. IE: Interrupt Enable Register

PRIORITY LEVEL STRUCTURE

priority interrupt can be interrupted by a high-priority
interrupt, but not by another low-priority interrupt. A
high-priority interrupt can't be interrupted by any other interrupt source.

Each interrupt source can be individually programmed
to one of two priority levels by setting or clearing a bit
in Special Function Register IP (Figure 14). A low-

PPC

PT2

PS

PT1

Address = OBSH

PX1

PXO

PTO

Reset Value = XOOOOOOOB

Symbol

Position

-

IP.7

Not implemented, reserved for future use. •

PPC

IP.6

Defines the PCA interrupt priority level. PPC = 1 programs it
to the high priority level.

PT2

IP.5

Defines the Timer 2 interrupt priority level. PT2 = 1 programs
it to the high priority level.

PS

IPA

Defines the Serial Port interrupt priority level. PS = 1
programs it to the high priority level.

PT1

IP.3

Defines the Timer 1 interrupt priority level. PT1 = 1 programs
it to the high priority level.

PX1

IP.2

Defines the External Interrupt 1 priority level. PX1
programs it to the high priority level.

PTO

IP.1

Defines the Timer 0 interrupt priority level. PTO
it to the high priority level.

PXO

IP.O

Defines the External Interrupt 0 priority level. PXO
programs it to the high priority level.

Function

=1

= 1 programs
=1

NOTE:
·User software should not write 1s to reserved bits. These bits may be used in future MeS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a
reserved bit is indeterminate.

Figure 14. IP: Interrupt Priority Register
7-13

intJ

HARDWARE DESCRIPTION OF THE 83C51FA

If two interrupts of different priority levels are flagged
simultaneously, the interrupt request of the higher priority level is serviced. If interrupts of the same priority
level are flagged simultaneously, an internal polling sequence determines which interrupt request is serviced.
Thus within each priority level there is a second priori- .
ty structure determined by the following polling sequence:

SOURCE
1. lEO
2. TFO
3. lEI
4. TFI
5.PCA
6.RI+TI
7. TF2+ EXF2

location of the interrupt service routine as shoWn below.
SOURCE
STARTING ADDRESS OF
SERVICE ROUTINE
0003H
lEO
TFO
OOOBH
0013H
IE1
001BH
TF1
0023H
RI+TI
TF2+EXF2
002BH
0033H
PCA

PRIORITY WITHIN LEVEL
(highest)

(lowest)

Note that the "priority within level" structure is only
used to resolve simultaneous requests of the same priority level.

Execution proc~eds from that location until the RETI
instruction is encountered, which terminates the interrupt service routine. Note that the starting addresses of
consecutive interrupt service routines are only 8 bytes
apart. That means if consecutive interrupts are being
used (lEO and TFO, for example, or. TFO and lEI), and
if the first interrupt routine is more than 7 bytes long,
then that routine will have to execute a jump out to
some other memory location where the service routine
can be completed without overlapping the starting ad·dress of the next interrupt routine.
.

LOCATION OF INTERRUPT SERVICE .
ROUTINES

Note that, although the polling position of the PCAgenerated interrilpt is higher than that of the Serial
Port, the starting address of the Serial Port interrupt
routine is unchanged from the 8051. This is for backwards software compatibility. Similarly, the Timer 2
interrupt 'starting addreSs is compatible with the 8052.
This allows conversion of 8052 (HMOS) designs to the
83C51FA (CHMOS) with no software modification.

The Interrupt Control System acknowledges an interrupt request by executing a hardware-generated
LCALL to the appropriate service routine. The hardware-generated LCALL pushes the contents of the Program Counter onto the stack (but it does not'save the
PSW) and reloads the PC with the starting

7-14

inter

HARDWARE DESCRIPTION OF THE 83C51FA

SPECIAL FUNCTION REGISTERS
A map of the Special Function Register (SFR) space is
shown in Table 1.

User software should not write Is to these unimplemented locations, since they may be used in future
MCS-51 products to invoke new features. In that case
the reset or inactive values of the new bits will always
be 0, and their active values will be I.

Note that not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect.

Table 1. Special Function Register Memory Map and Values After Reset

CH
CCAP3H
CCAP4H
CCAPOH
CCAP1H
CCAP2H
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

F8

FO *S
00000000

F7

CL
CCAPOL
CCAP1L
CCAP2L
CCAP3L
CCAP4L
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

E8

FF

EO 'ACC
00000000
08 CCON
CMOO
CCAPMO
OOXOOOOO OOXXXOOO XOOOOOOO

EF
E7

CCAPM1
XOOOOOOO

CCAPM2 CCAPM3
XOOOOOOO XOOOOOOO

CCAPM4
XOOOOOOO

OF
07

DO • PSW

00000000
C8 T2CON
T2MOO
RCAP2L
00000000 XXXXXXXO 00000000

RCAP2H
00000000

TL2
00000000

TH2
00000000

co

CF
C7

S8 • IP

SF

So

S7

A8

SAOEN
XOOOOOOO 00000000
* P3
11111111
SAOOR
• IE
00000000 00000000

AF

AO • P2
11111111
* SSUF
98 'SCON
00000000 XXXXXXXX

A7

90 • P1

97

11111111
88 " TCON
00000000
80 " PO
11111111

9F

*TMOO
• THO,
• TL1
• TH1
• TLO
00000000 00000000 00000000 00000000 00000000
• OPL
• OPH
• SP
00000111 00000000 00000000

• = Found In the 8051 core (See 8051 Hardware Description for explanations of these SFRs).
•• = See description of PCON SFR. Bit PCON.4 is not affected by reset.

X = Undefined.

7-15

8F

'PCON •• 87
OOXXOOOO

Hardware Description of the
83C152

8'

HARDWARE DESCRIPTION
OF THE 83C152
use of external program memory. The second difference
is that RESET is active low in the 83CI52 and active
high in the 80C51BH. This is very important to designers who may currently be using the 80C51BH and planning to use the 83C152, or are planning on using both
devices on the same board. The third difference is that
GFO and GFI, general purpose flags in PCON, have
been renamed GFIEN and XRCLK. GFIEN enables
idle flags to be generated in SDLC mode, and XRCLK
enables the receiver to be externally clocked. All of the
previously unused bits are now being used and interrupt vectors have been added to support the new enhancements. Programmers using old code generated for
the 80C51BH will have to examine their programs to
ensure that new bits are properly loaded, and that the
new interrupt vectors will not interfere with their program.

1.0 INTRODUCTION
The 83CI52 Universal Communications Controller is
an 8-bit microcontroller designed for the intelligent
management of peripheral systems or components. The
83CI52 is a derivative of the 80C51BH and retains the
same functionality. The 83CI52 is fabricated on the
same CHMOS III process as the 80C51BH. What
makes the 83CI52 different is that it has added functions and peripherals to the basic 80C5IBH architecture that are supported by new Special Function Registers (SFRs). These enhancements include: a high speed
multi-protocol serial communication interface, two
channels for DMA transfers, HOLD/HLDA bus control, a fifth I/O port, expanded data memory, and expanded program memory.
In addition to a standard UART, referred to here as
Local Serial Channel (LSC) , the 83Cl52 has an onboard multi-protocol communication controller called
the Global Serial Channel (GSC). The GSC interface
supports SDLC, CSMA/CD, user definable protocols,
and a subset of HDLC protocols. The GSC capabilities
include: address recognition, collision resolution, CRC
generation, flag generation, automatic retransmission,
and a hardware based acknowledge feature. This high
speed serial channel is capable of implementing the
Data Link Layer and the Physical Link Layer as shown
in the OSI open systems communication model. This
model can be found in the document "Reference Model
for Open Systems Interconnection Architecture",
ISO/TC97/SCI6 N309.

Throughout the rest of this manual the 80CI52 and the
83CI52 will be referred to generically as the "CI52".
The CI52 is based on the 80C51BH architecture and
utilizes the same 80C5IBH instruction set. Figure 1.1 is
a block diagram of the C152. Readers are urged to
compare this block diagram with the 80C51BH block
diagram. There have been no new instructions added.
All the new features and peripherals are supported by
an extension of the Special Function Registers (SFRs).
Very little of the information pertaining specifically to
the 80C5IBH core will be discussed in this chapter.
The detailed information on such functions as: the instruction set, port operation, timer/counters, etc., can
be found in the MCS®-51 Architecture chapter in the
Intel Embedded Controller Handbook. Knowledge of
the 80C5IBH is required to fully understand this manual and the operation of the C152. To gain a basic understanding on the operation of the 80C51BH, the
reader should familiarize himself with the entire MCS51 chapter of the Embedded Controller Handbook.

The DMA circuitry consists of two 8-bit DMA channels with 16-bit addressability. The control signals;
Read (RD), Write (WR), hold and hold acknowledge
(HOLD/HLDA) are used to access external memory.
The DMA channels are capable of addressing up to
64K bytes (16 bits). The destination or source address
!;an be automatically incremented. The lower 8 bits of
the address are multiplexed on the data bus Port 0 and
the upper eight bits of address will be on Port 2. Data is
transmitted over an 8-bit address/data bus. Up to 64K
bytes of data may be transmitted for each DMA activation.

Another source of information that the reader may find
helpful is Intel's LAN Components User's Manual, or. der number 230814. Inside are descriptions of various
protocols, application examples, and application notes
dealing with different serial communication environments.

The new I/O port (P4) functions the same as Ports 1-3,
found on the 80C51BH.

2.0 COMPARISON OF 80C152 AND
80C51BH FEATURES

Internal memory has been doubled in the 83C152. Data
memory has been expanded to 256 bytes, and internal
program memory has been expanded to 8K bytes.

2.1 Memory Space

There are also some specific differences between the
83CI52 and the 80C51BH. The first is that the numbering system between the 83CI52 and the 80C5IBH is
slightly different. The 83CI52 and the 80C5IBH are
factory masked ROM devices. The 80CI52 and the
80C3IBH are ROMless devices which require the

A good understanding of the memory space and how it
is used in the operation of MCS-51 products is essential. All the enhancements on the CI52 are implemented by accessing Special Function Registers (SFRs),
added data memory, or added program memory.

8-1

P4.0-P4.7

l

PO .0- PO.7

SARLI
SARHI
DARL1
DARHI

:t:

BCRL1

~

::u
c

:e~
"'1'1

::u

III

m

m

c·
c::

......

C

en
n
::u

:..

(Xl

ID

=ti

N n0"

-4

(5

7<:

C

Z

..

iii'

o."

eD

III

3

-4
:t:

~"

m
CI)
Co)

....n
U1
N

CRC
GENERATOR
ADRO-3
BAUD

Pl.O- Pl.7

TCDCNT

P3.0- P3.7

270427-7

HARDWARE DESCRIPTION OF THE 83C152

(IDA), Source Address Space bit (SAS). Increment
~ource Address bit (ISA), DMA Channel Mode bit
(DM), Transfer Mode bit (TM), DMA Done bit
(DONE), and the GO bit (GO). DCONO is used to
control DMA Channel O.

2.1.1 SPECIAL FUNCTION REGISTERS (SFRs)
The following list contains all the SFRs, their names
and function. All of the SFRs of the 80C51BH are reo
tained and for a detailed explanation of their operation,
please refer to the chapter, "Hardware Description of
the 8051 and 8052" that is found in the Embedded
Controller Handbook. An overview of the new SFRs is
found in Section 2.2.1.1, with a detailed explanation in
Section 3.7 and Section 4.5.

DCONI - (93H) Same as DCONO except this is for
DMA Channel 1.
GMOD - (84H) Contains the Protocol bit (PR). the
Preamble Length (PLI.O), CRC Type (CT). Address
Length (AL). Mode select (Ml.0), and External Transmit Clock (TXC). This register is used for GSC operation only.

2.1.1.1 New SFRs
The following descriptions are quick overviews of the
new SFRs, and not intended to give a complete understanding of their use. The reader should refer to the
detailed explanation in Section 3 for the GSC SFRs,
and Section 4'for the DMA SFRs.

IENI - (OC8H) Interrupt enable register for DMA and
GSC interrupts.
.
IFS - (OA4H) Determines the number of bit times separating transmitted frames.

ADR 0,1,2,3 - (95H, OA5H, OBSH, OCSH) Contains
the four bytes for address matching during GSC operation.

IPNI - (OF8H) Interrupt priority register for DMA
and GSC interrupts.

AMSKO - (OD5H) Selects "don't care" bits to be used
with ADRO.

MYSLOT - (OFSH) Contains the Jamming mode bit
(DCJ). the Deterministic Collision Resolution Algorithm bit (DCR). and the DCR slot address for the
GSC.

AMSKI - (OESH) Selects "don't care" bits to be used
with ADRI.

P4 - (OCOH) Contains the memory "image" of Port 4.

BAUD - (94H) Contains the programmable value for
the baud rate generator for the GSC. The baud rate will
equal (fosc)/«BAUD + I) X 8).

PRBS - (OE4H) Contains a pseudo-random number to
be used in CSMA/CD backoff algorithms. May be read
or written to by user software.

BCRLO - (OE2H) Contains the low byte of a countdown counter that determines when the DMA access
for Channel 0 is complete.

RFIFO - (F4H) RFIFO is used to access a 3-byte FIFO
that contains the receive data from the GSC.

BCRHO - (OE3H) Contains the high byte for countdown counter for Channel O.

BCRHI - (OF3H) Same as BCRHO except for DMA
Channell.

RSTAT - (OE8H) Contains the Hardware Based Ac·
knowledge Enable bit (HABEN), Global Receive Enable bit (GREN). Receive FIFO Not Empty bit
(RFNE). Receive Done bit (RDN). CRC Error bit
(CRCE). Alignment Error bit (AE), Receiver Collision!Abort detect· bit (RCABT), and the Overrun bit
(OVR). used with both DMA and GSC.

BKOFF - (OC4H) An 8-bit count-down timer used
with the CSMA/CD resolution algorithm.

SARLO - (OA2H) Contains the low byte of the source
address for DMA transfers.

DARLO - (OC2H) Contains the low byte of the destination address for DMA Channel O.

SARHO - (OA3H) Contains the high byte of the source
address for DMA transfers.

DARHO - (OC3H) Contains the high byte of the destination address for DMA Channel O.

SARLI - (OB2H) Saine as SARLO but for DMA Chan-.
nell.

DARLI - (OD2H) Same as DARLO except for DMA
Channell.

SARHI - (OB3H) Same as SARHI but for DMA Channel I.

DARHI - (OD3H) Same as DARHO except for DMA
Channell.

SLOTTM - (OB4H) Determines the length of the slot
time in CSMA/CD.

DCONO - (92H) Contains the Destination Address
Space bit (DAS). Increment Destination Address bit

TCDCNT - (OD4H) Contains the number of collisions
in the current frame if using CSMA/CD GSC.

BCRLl - (OF2H) Same as BCRLO except for DMA
Channell.

8-3

inter

HARDWARE DESCRIPTION OF THE 83C152

Old(O)/New(N)

0
N
N
N
N
N
N

0
N
N
N
N
N
N
N
N
N
N
N
N

0
0
N

0
N
N

0
N
N"

0
0
0
0
N

0
N

0
N
N
N
N
N
N

.0
0
N

0
N

0
N

0

ci
0
0
0
N

Name
'A
ADRO
ADR1
ADR2
ADR3
AMSKO
AMSK1
B
BAUD
BCRLO
BCAHO
BCRL1
BCRH1
BKOFF
DARLO
DARHO
DARL1
DARH1
DCONO
DCON1
DPH
DPL
GMOD
IE
IEN1
IFS
IP
IPN1
MYSLOT
PO
P1
P2
P3
P4
PCON
PRBS
PSW
RFIFO
RSTAT
SARLO
SARHO
SARL1
SARH1
SBUF
SCON
SLOTTM
SP
TCDCNT
TCON
TFIFO
THO
TH1
TLO
TL1
TMOD
TSTAT

. Function

Addr
OEoH.
095H
OA5H
OB5H
OC5H
OD5H
OE5H
OFOH
094H
OE2H
OE3H
OF2H
OF3H
OC4H
OC2H
OC3H
OD2H
OD3H
092H
093H
083H
082H
084H
OA8H
OC8H
OA4H
OB8H
OF8H
OF5H
b80H
090H
OAOH
bBOH
OCOH
087H
·OE4H
ODOH
OF4H
OE8H
OA2H
OA3H
OB2H
OB3H
099H
098H
OB4H
08tH
OD4H
088H
085H
08CH
08DH
08AH
08BH
089H
OD8H

ACCUMULATOR
GSC MATCH ADDRESS 0
GSC MATCH ADDRESS 1
GSC MATCH ADDRESS 2
GSC MATCH ADDRESS 3
GSC ADDRESS MASK 0
GSC ADDRESS MASK 1
B REGISTER
GSC BAUD RATE
DMA BYTE COUNT 0 (LOW)
DMA BYTE COUNT 0 (HIGH)
DMA BYTE COUNT 1 (LOW)
DMA BYTE COUNT 1 (HIGH)
GSC BACKOFF TIMER
DMA DESTINATION ADDR 0 (LOW)
DMA DESTINATION AD DR 0 (HIGH)
DMA DESTINATION ADDR 1 (LOW)
DMA DESTINATION ADDR 1 (HIGH)
. DMA CONTROL 0
DMA CONTROL 1
DATA POINTER (HIGH)
DATA POINTER (LOW)
GSCMODE
INTERRUPT ENABLE REGISTER 0
INTERRUPT ENABLE REGISTER 1
GSC INTER FRAME SPACING
INTERRUPT PRIORITY REGISTER 0
INTERRUPT PRIORITY REGISTER 1
GSC SLOT ADDRESS
PORTO
PORT 1
PORT 2
PORTa
PORT 4
POWER CONTROL
GSC PSEUDO-RANDOM SEQUENCE
PROGRAM STATUS WORD
GSC RECEIVE BUFFER
RECEIVE STATUS (DMA & GSC)
DMA SOURCE ADDR 0 (LOW)
DMA SOURCE ADDR 0 (HIGH)
DMA SOURCE AD DR i (LOW;
DMA SOURCE ADDR 1 (HIGH)
LOCAL SERIAL CHANNEL (LSC) BUFFER
LOCAL SERIAL CHANNEL (LSC) CONTROL
GSC SLOT TIME
STACK POINTER
GSC TRANSMIT COLLISION COUNTER
TIMER CONTROL
GSC TRANSMIT BUFFER
TIMER 0 (HIGH)
TIMER 1 (HIGH)
TIMER 0 (LOW)
TIMER 1 (LOW)
TIMER MODE
TRANSMIT STATUS (DMA & GSC)

8-4

inter

HARDWARE DESCRIPTION OF THE'S3C152

TFIFO - (85H) TFIFO is used to access a 3-byte FIFO
that contains the transmission data for the GSC.

The addresses of-the second 128 bytes of data memory
happen to overlap the SFR addresses. The SFRs and
their memory locations are shown in Figure 2.2. This
means that. internal data memory spaces have the same
address as the SFR address. However, each type of
memory is addressed differently. To access data memory above 80H, indirect addressing or the DMA channels must be used. To access the SFRs, direct addressing is used. When direct addressing is used, the address
is the source or destination, e.g. MOY A, IOH, moves
the contents of location IOH into the accumulator.
When indirect addressing is used, the address of the
destination or source exists within another register, e.g.
MOY A, @RO. This instruction moves the contents of
the memory location addressed by RO into the accumulator. Directly addressing the locations 80H to OFFH
will access the SFRs. Another form of indirect addressing is with the use of Stack Poillter Operations. If the
Stack Pointer contains an address and a PUSH or POP
instruction is executed, indirect addressing is actually
used. Directly accessing an unused SFR address will
give undefined results.

TSTAT - (OD8H) Contains the DMA Service bit
(DMA), Transmit Enable bit (TEN), Transmit FIFO
Not Full bit (TFNF), Transmit Done bit (TDN),
Transmit Collision Detect bit (TCDT), Underrun bit
(UR), No Acknowledge bit (NOACK), and the Receive oata Line Idle bit (LNI). This register is used
with both DMA and GSC.
The general purpose flag bits (GFO and GFl) that exist
on the 80C51BH are no longer available on the C152.
GFO has been renamed GFIEN (GSC Flag Idle Enable) and IS used to enable idle fill flags. Also GFI has
been renamed XRCLK (External Receive Clock Enable) and is used to enable the receiver to be clocked
externally.
2.1.2 DATA MEMORY

Internal data memory consists of 256 bytes as shown in
Figure 2.1. The first 128 bytes are addressed exactly
like an 80C51BH, using direct addressing.

Physically, there are separate SFR memory and data
memory spaces allocated on the chip. Since·there are
separate spaces, the SFRs do not diminish the available
data memory space.

rv
OffH

OfFH

(0)

OVERLAPPING
MEMORY
ADDRESSES

A

oaOH

(0)

(0)

SPECIAL FUNCTION REGISTER
SPACE

02fH
BIT ADDRESSABLE
MEMORY SPACE
020H
01FH

.,

REGISTER BANK 3
017H
REGISTER BANK 2
010H
REGISTER BANK 1
007H
REGISTER BANK 0

..

OOOH
USER DATA MEMORY SPACE

270427-1

°NOTE:
User data memory above BOH must be addressed indirectly. Using direct addressing above BOH accesses 'the Special
Function Registers.

Figure 2.1. Data Memory Map

8-5

inter

HARDWARE DESCRIPTION OF THE 83C152

External data memory is accessed like an SOC51BH,
with "MOVX" instructions. Addresses up to 64K may
be accessed when using the Data Pointer (DPTR).
When accessing external data memory with the DPTR,
the address appears on Port 0 and 2. When using the
DPTR, if less, than 64K of external data memory is
used, the address is emitted on all sixteen pins. This
means that when using the DPTR, the pins of Port 2
not used for addresses cannot be used for general purpose VO. An alternative to using 16-bit addresses with
the DPTR is to use RO or Rl to address the external
data memory. When using the registers to address external data memory, the address range is limited to 256
bytes. However, software manipulation of VO Port 2
pins as normal I/O, allows this 256 bytes restriction to
be expanded via bank switching. When using RO or Rl
as data pointers, Port 2 pins that'are not used for addressing, can be used as general purpose I/O.

2.1.2.1 Bit Addressable Memory
The C152 has several memory spaces in which the bits
are directly addressed by their location. The directly
addressable bits and their symbolic names are shown in
Figure 2.3A, 2.3B, and 2.3C.
Bit addresses 0 to 7FH reside in on-board user data
RAM in byte addresses 20H to 2FH (see Figure 2.3A).
Bit addresses SOH to.OFFH reside in the SFR memory
space, but not every SFR is bit addressable, see Figure
2.3B. The addressable bits are scattered throughout the
SFRs. The addressable bits occur every eighth SFR address starting at SOH and occupy the entire byte. Most
of the bits that are addressable in the SFRs have been
given symbolic names. These names will often be referred to in this or other documentation on the C152.
Most assemblers also allow the use of the symbolic
names when writing in assembly language. These
names are shown in Figure 2.3C.

PGSlE POIIA 1 PGSlV PDllAO PGSRE PGSRV OFBH

1

ADR2
SLOmA
SARHl
SARLl

'I I I I. 'II I. 'I I I I, 'I I I II. 'I I I I, 'II I II,
MYSLOT DCJ
RFIFO
BCRH 1
'BCRL 1

OCR

'//1,

SAS

SM

s.u

SA3

SAl

SAO

'II. 'III. '1111, 'III,

OF5H
OF4H
OF3H
OF2H

RDN

(0) IE

'I.

'I.

OESH

'I. 'II, 'III,

'II. '1111. 'III.

'III.
OE4H
OOH
OE2H

'I.

'I.

LNI NOACK UR

TCDT

TON

'II,

TFNF

TEN

OMA

OOSH
OOSH
OD4H
OD3H
002H

DARHl

DARL·I

'II,
ev
'II,

'I,

'II/I.

AC

FO

'I,

RSl

'I.

'11.'1111, 'III,
RSO

OV

'II. 'III, 'III,
'I.

ODOH

'I.
DC4H
OC3H
OC2H

'I.

OCOH

'IL

PTl

'I.
PXl

'I,
PTO

'II,
PXO

'I,

'//1,

OB8H

'IlL 'I, '1.'1111. 'III. '11/1.'11,

'I.
099H
098H
09SH
094H
093H
092H

REN

TB8

RB8

n

RI

IDA
IDA

SAS
SAS

!SA

!SA

OM
OM

TM
TM

DONE
DONE

GO
GO

DEiI

GTXD GRXD 090H

RD5A

TFlFO
GlAOD CTCLK
DPH
DPL
SP
(')PO

'I.
'I.

OA8H

'I,

SM2

THl
THO
TLl
TLO
TMOD GATE C
(')TCON TFl lRl
PCON SMOD ARB

OCSH

PS

OBOH

EXO

SMl

HLD

'i/i.

'ii.

loll
MO GATE ejl
TFO lRO
IEl
1T1
REQ GAREN XRCLK GFiEN

'II, 'II,
loll

'I,

!'"
'" > z Z z

INDEX
CORNER'\..



Q.

...

on
N
c..i c..i c..i 0
oi Q.
ci Q.
ci ci
oi
Z ,z Z oi
Q.
Q.
Q.

0.

'"

270427-6

Figure 2.58. PLCCPin Out.

2.7 Pin Desc.ription
The pin description for the 80C5lBH also applies to the C152 and is listed below. Changes have been made to the
. descriptions as they apply to the C152.

PIN DESCRIPTION
Pin
Name

Description

VSS

Circuit ground potential.

VCC

Supply voltage during normal, Idle, and Power down operation.' Nominally

+ 5V

...L 04nOI

.L lV-tO.

XTAL1
XTAL2

Input to the inverting oscillator amplifier. Also serves as the input for using an
external Clock signal.
Output from the oscillator amplifier.

PORTO

' Port 0 is an 8-bit open drain bi-directional 1/0 port. Port 0 pins that have 1s written to
them float and in that state can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external Program
and Data Memory: In this application it uses strong internal pullups when emitting
1s. Port 0 also outputs the code bytes during program verification in the 83C152.
External pullups are required during program verification.

PORT 1

Port 1 is an 8-bit bi-directionall/O port with internal pullups. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current because of the internal pull ups. Port 1 also has the following special
functions and for the special functions to operate a "1" has to be written to that pin
first.
8-12

inter

HARDWARE DESCRIPTION OF THE 83C152

2.7 PIN DESCRIPTION (Continued)
Pin
Name

Description
Port
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7

Alternate Function
GSC receiver data input (GR x D)
GSC transmitter data output (GT x D)
Drive Enable to enable external drivers (DEN)
GSC external transmit clock input (T x C)
GSC external receive clock input (Rx C)
DMA hold request 1/0 (HOlD_)_
DMA hold acknowledge I/O (HlDA)
none

PORT 2

Port 2 is an 8-bit bi-directionall/O port with internal pullups. Port 2 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 2 pins that are externally being pulled low will source
current because of the internal pull ups. Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external Data
Memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong
internal pullups when emitting 1s and cannot be used as inputs. During accesses to
external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the
contents of the P2 SFR. Port 2 receives the high-order address bits during program
verification of the ROM device.

PORT 3

Port 3 is an 8-bit bi-directionall/O port with internal pull ups. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used
as inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the pull ups. Port 3 also has the following special functions and for the
special functions to operate that pin must be programmed to a "1" first.

Port
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7

Alternate Function
RXD (lSC serial data input port)
I
TXD (lSC serial data output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
I!JTimer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

PORT 4

Port 4 is an 8-bit bi-directionall/O port with 40 internal pullups. Port 4 pins that have
1s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 4 pins that are externally pulled-low will source
current because of the pullups. Port 4 also receives the low-order address bytes
during program verification in the 83C152.

RESET

Reset input. A low level on this pin for two machine cycles while the oscillator is
running resets the device. An internal diffused resistor to VCC permits Power-On
.
reset using only an external capacitor to VSS.

EA

External Access enable. EA must be externally held low in order to enable the
device to fetch code from external Program Memory locations OOOOH to 1FFFH.

ALE

Address latch Enable output pulse for latching the low byte of the address during
accesses to external memory. In normal operation ALE is emitted at a constant rate
of % the oscillator frequency, and may be used for external timing or clocking
purposes. Note, however, that one ALE pulse is skieP.ed during each access to
external Data Memory. (Including DMAs where no RD/WR generated for internal
source/destination.)

PSEN

Program Store Enable is the read strobe to external Program Memory. When the
C152 is executing code from external Program Memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each
access to external Data Memory.
8-13

intJ

HARDWARE DESCRIPTION OF THE 83C152

2.8 Power Down and Idle

2.9 Local Serial Channel

Both of these operations function identically as in the
80C51BH. Application Note 252, "Designing with the
80C5IBH" gives an excellent explanation on the use of
the reduced power consumption .modes. Some of the
items not covered in AP-252 are the considerations that
are applicable when using the GSC or DMA· in conjunction with the power saving modes.

The Local Serial Channel (LSC) is the name given to
the UART that exists on all MCS-51 devices. The
LSC's function and operation is exactly the same as on
the 80C51BH. For a description on the use of the LSC,
refer to the 8051/52 Hardware Description Chapter in
the Intel Embedded Controller Handbook, under Serial
Interface.

The GSC continues to operate normally in Idl~ as long
as the interrupts are enabled. The interrupts need to be
enabled, so that the CPU can service the FIFO's and
terminate transmission or reception when appropriate.
After servicing the. GSC, user software. will need to
again invoke the Idle command as the CPU does not
automatically re-enter the Idle mode after servicing the
interrupts.

3.0 GLOBAL SERIAL CHANNEL

3.1 Introduction

The GSC does not operate while in Power Down so the
steps required prior to entering Power Down become
more complicated. The sequence when entering Power
Down and the status of the I/O is of major importance
in preventing damage to the C152 or other components
in the system. Since the only way to exit Power Down
is with a Reset, several problem areas become very significant. Some of the problems that merit careful consideration are cases where the Power Down occurs during the middle of a transmission; and the possibility
that other stations are not or cannot enter this same
mode. The state of the GSC I/O pins becomes critical
and the GSC status will need to be saved before power .
down is entered. There will also need to be some method of identifying to the CPU that the following Reset is
probably not a cold start and that other stations on the
link may have already been initialized.
The DMA circuitry stops operation in both Idle and
Power Down modes. Since operation is stopped' in both
modes, the process should be similar in each case. Specific steps that need to be taken include: notification to
other devices that DMA operation is about to cease for
a particular station or network, proper withdrawal
from DMA operation, and saving the status' of the
DMA channels. Again, the status of the I/O pins during Power Down needs careful consideration to avoid
damage to the C152 or other components.

The Global Serial Channel (GSC) is a multi-protocol,
high performance serial interface targeted for data rates
up to 2 MBPS with on-chip clock recovery, and 2.4
MBPS using the external clock options. In applications
using the serial channel, the GSC implements the Data
Link Layer and Physical Link Layer as described in the
ISO reference model for open systems interconnection.
The GSC is designed to meet the requirements of a
wide range of serial communications applications and is
optimized to implement Carrier-Sense Multi-Access
with Collision Detection (CSMA/CD) and Synchronous Data Link Control (SDLC) protocols. The GSC
architecture is also designed to provide flexibility in defining non-standard protocols. This provides the ability
to retrofit new products into older serial technologies,
as well as the development of proprietary interconnect
schemes for serial backplane environments.
The versatility of the GSC is demonstrated by the wide
range of choices available to the user. The various
modes of operation are summarized in Table 3.1. In
subsequent sections, each available choice of operation
will be explained in detail.
In using Table 3.1, the parameters listed vertically (on
the left hand side) represent an option that is selected
(X). The parameters listed horizontally (along the top
of the table) are all the parameters that could. theoretically be selected (Y). The symbol at the junction of
both X and Y determines the applicability of the option

Y.

Port 4 returns to its input state, which is high level
using weak pullup devices.

Note, that not all combinations are backwards compati~
ble. For example, Manchester encoding requires half
duplex, but half duplex does not .require Manchester
encoding.

8-14

HARDWARE DESCRIPTION OF THE 83C152

Table 3.1
DATA
ENCODING

N=NOT AVAILABLE
M=MANDATORV
O=OPTIONAL
P = NORMALLV PREFERRED
X=N/A

M
A
N
C
H
E

FLAGS

N

N

0

R

R

Z

Z
I

1
1
1
1
1
1

S
T

DU·
PLEX

CRC

1
1

N

1

0

/
I

N
E

6
B
I
T

D

L

C
C

E

I
T

0

E
R

3
2
B
I
T
A

H
A
L
F

ACKNOWLEDGE

N

F
U

0

L
L

N
E

H
A

U

N

S

0

R
D
W

E

N
E

A
R
E

U

T
0

ADDRESS
RECOGNITION

R
D
E
F

I
N
E
D

8'
B
I

T

1
6
B
I

T

/
A
L
L

BACKOFF

N

A

0

L
T

R

M
A
L

D
E

T

E
R

E
R

N
A

M
I
N
I

T
E

PREAMBLE

N

0
N
E

8
B
I

T

S
T
I
C

DATA ENCODING:
MANCHESTER(CSMA/CD)

X

N

N

1

P

1

0

0

M

N

0

0

0

0

0

0

0

0

0

N

0

NRZI (SDLC)

N

X

N

P

1

1

0

0

0

0

0

N

P

0

0

0

N

N

N

0

0

'. NRZ (EXT CLK)

N

N

X

0

0

1

0

0

0

0

0

N

0

0

0

0

0

0

0

0

0

N

P

0

X

1

1

0

0

0

0

0

N

P

0

0

0

N

N

N

0

0

P

N

0

1

X

1

0

0

0

N

0

0

0

0

0

0

0

0

0

1

0

1

1

1

1

1

X

N

N

1

N

1

1

1

1

1

1

N

N

N

1

1

0

0

0

0

0

N

X

N

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

N

N

X

0

N

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

X

N

0

0

0

0

0

0

0

0

0

0

0
0

FLAGS:Ollllll0 (SDLC)
11/IDLE
CRC:NONE
l6-BITCCITI
32-BIT AUTODIN II
DUPLEX:HALF

N

0

0

M

N

N

M

N

N

X

0

N

P

0

0

0

N

N

N

0

0

0

0

0

0

1

0

0

0

0

X

N

N

0

0

0

0

0

0

0

0

HARDWARE

0

N

N

N

0

1

0

0

0

N

N

X

N

0

0

0

N

0

0

N

0

USER DEFINED

0

P

0

0

0

1

0

0

0

P

N

N

X

0

0

0

0

0

0

0

0

FULL
ACKNOWLEDGEMENT:NONE

ADDRESS RECOGNITION:
NONE/ALL

0

0

0

0

0

1

0

0

0

0

0

0

0

X

N

N

0

0

0

0

0

8-BIT

0

0

0

0

0

1

0

0

0

0

0

0

0

N

X

N

0

0

0

0

0

l6-BIT

0

0

0

0

0

1

0

0

0

0

0

0

0

N

N

X

0

0

0

0

0

COLLISION RESOLUTION:

0

N

0

N

0

N

0

0

M

N

0

N

0

0

0

0

X

N

N

N

0

ALTERNATE

O'

N

0

N

0

N

0

0

M

N

0

0

0

0

0

0

N

X

N

N

0

DETERMINISTIC

0

N

0

N

0

N

0

0

M

N

0

0

0

0

0

0

N

N

X

N

0

N

0

0

0

1

1

0

0

0

0

0

N

0

0

0

0

N

N

N

X

N

8-BIT

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

N

X

32-BIT

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

N

N

NORMAL

PREAMBLE:NONE

\

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

N

N

JAM:D.C.

M

N

N

N

0

N

0

0

M

N

0

0

0

0

0

0

0

0

0

N

0

CRC

M

N

N

N

0

N

0

0

M

N

0

0

0

0

0

0

0

0

0

N

0

N

M

.N

0

0

N

0

0

0

0

0

N

0

0

0

0

N

N

N

0

0

0

0

N

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0
0

64-BIT

CLOCKING:EXTERNAL
INTERNAL
CONTROL: CPU

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

RAW RECEIVE:

1

1

1

1

1

1

1

1

1

N

1

1

1

1

1

1

0

0

0

1

1

RAW TRANSMIT:

1

1

1

1

1

1

1

1

1

N

1

1

1

1

1

1

N

N

N

1

1

CSMAlCD:

0

N

2

1

P

1

0

0

M

N

0

0

0

0

0

0

0

0

0

N

0

SDLC:

N

0

0

P

1

1

0

0

0

0

0

N

0

0

0

0

N

N

N

P

0

DMA

8-15

HARDWARE DESCRIPTION OF THE 83C152

Table 3.1 (Continued)
PRE·
AMBLE

2

6
4

B
I
T

B
I
T

3
N= NOT AVAILABLE
M=MANDATORY
0= OPTIONAL
P= NORMALLY PREFERRED
X=N/A

JAM
D
C

CLOCK
C
R
C

E
X
T
E
R
N
A
L

I

I
N
T
E
R
N
A
L

CONTROL
C
P
U

D
M
A

R
A

R
A

C

W

W

R
E
C
E
I
V
E

T
R
A
N

M
A

5

5
D
L
C

I
C
D

S
M
I
T

DATA ENCODING:
MANCHESTER

0

0

0

0

N

M

0

0

0

0

M

N

NRZI

0

0

N

N

N

M

0

0

0

0

N

M

NRZ

0

0

0

0

M

N

0

0

0

0

0

0

FLAGS:01111110

0

0

N

N

0

0

0

0

0

1

1

P

1111DLE

0

0

0

0

0

0

0

0

0

1

P

1

1

1

N

N

1

1

1

1

1

1

1

1

CRC:NONE
16·BIT CCITT

0

0

-0

0

0

0

0

0

1

1

0

0

32·BIT AUTODIN "

0

O.

0

0

0

0

0

0

1

1

0

0

DUPLEX:HALF

0

0

0

0

0

0

0

0

0

0

0

0

FULL

0

0

N

N

0

0

0

0

N

N

N

P

0

0

0

0

0

0

0

0

0

0

0

0

HARDWARE

0

0

0

0

N

0

0

0

N

N

0

N

USER DEFINED

0

0

0

0

0

0

0

0

0

0

0

1

ACKNOWLEDGEMENT:NONE

ADDRESS RECOGNITION:
NONE

0

0

0

_0

0

0

0

0

0

0

0

0

8·BIT

0

0

.0

0

0

0

0

0

1

1

0

0

16·BIT

0

0

0

0

0

0

0

0

1

1

0

0

COLLISION RESOLUTION:
NORMAL

0

0

0

0

N

0

0

0

0

N

M

N

ALTERNATE

0

0

0

0

N

0

0

,0

0

N

M

N

DETERMINISTIC

O.

0

0

0

N

0

0

0

0

N

M

N

N

N

N

N

0

0

0

0

0

0

N

P

N

N

0

0

0

0

0

0

1

1

0

0

32·BIT

X

N

0

0

0

0

0

0

1

1

0

0

64·BIT

N

X

0

0

0

0

0

0

1

1

0

0

JAM:D.C.

0

0

X

N

2

0

0

0

0

N

M

N

CRC

0

0

N

X

2

0

0

0

0

N

M

N

0

0

N

N

X

N

0

0

0

0

2

0

INTERNAL

0

0

0

0

N

X

0

0

0

0

0

0

CONTROL:CPU

0

0

0

0

0

0

X

N

0

0

0

0

0

0

(j

0

0

0

N

X

0

0

0

0

RAW RECEIVE:

1

1

0

0

1 '

1

1

1

X

N

1

1

RAW TRANSMIT:

1

1

N

N

1

1

1

1

N

X

1

1

CSMAlCD:

0

0

0

0

2

0

0

0

0

0

X

N

SDLC:

0

0

N

N

0

0

0

0

0

0

N

X

PREAMBLE:NONE

8·BiT

CLOCKING:EXTERNAL

DMA

8·16

HARDWARE DESCRIPTION OF THE 83C152

of collision resolution made available to the user on the
C152. Re-transmission is attempted when a resolution
algorithm indicates that a station's opportunity has arrived.

Note 1: Programmable in Raw transmit or receive
mode.
Note 2: When CSMA/CD is enabled, an external clock
can be used on the transmitter, but not the receiver.
Since the receiver monitors the link for Manchester violations, external hardware would be required to reformat the data from NRZ to Manchester on the transmitter. These hardware requirements go beyond the expectations of this table for implementation. For that reason
it was assumed that the external clock cannot be used
at all with CSMA/CD protocol, although it is actually
possible to do so.
Almost all the options available from Table 3.1 can be
implemented with the proper software to perform the
functions that are necessary for the options selected. In
Table 3.1, a judgment has been made by the authors on
which options are practical and which are not. What
this means is that in Table 3.1, an UN" should be interpreted as meaning that the option is either not practical
when implemented with user software or that it cannot
be done. An "0" is used when that function is one of
several that can be implemented with the GSC without
additional user software.
The GSC is targeted to operate at bit rates up to 2.4
MBps using the external clock options and up to 2
MBps using the internal baud rate generator, internal
data formatting and on-chip clock recovery. The baud
rate generator allows most standard rates to be
achieved. These standards include the proposed
IEEE802.3 LAN standard (1.0MBps) and the T1 standard (1.544MBps). The baud rate is derived from the
crystal frequency. This makes crystal selection important when determining the frequency and accuracy of
the baud rate.

3.2 CSMA/CD Operation
3.2.1 CSMA/CD OVERVIEW
CSMA/CD operates by sensing the transmission line
for a carrier, which indicates link activity. At the end of
link activity, a station must wait a period of time, called
the deference period, before transmission may begin.
The deference period is also known as the interframe
space. The interframe space is explained in Section
3.2.3.
With this type of operation, there is always the possibility of a collision occurring after the deference period
due to line delays. If a collision is detected after transmission is started, a jamming mechanism is used to ensure that all stations monitoring the line are awar,e of
the collision. A resolution algorithm is then executed to
resolve the contention. There are three different modes

Normally, in CSMA/CD, re-transmission slot assignments are intended to be random. This method gives all
stations an equal opportunity to utilize the serial communication link but also leaves the possibility of another collision due to two stations having the same slot
assignment. There is an option on the C152 which allows all the stations to have their slot assignments previously determined by user software. This pre-assignment of slots is called the deterministic resolution
mode. This method allows resolution after the first collision and ensures the access of the link to each station
during the resolution. Deterministic resolution can be
advantageous when the link is being heavily used and
collisions are frequently occurring and in real time applications where determinism is required. Deterministic
resolution may also be desirable if it is known beforehand that a certain station's communication needs to be
prioritized over those of other stations if it is involved
in a collision.
3.2.2 CSMAlCD FRAME FORMAT
The frame format in CSMA/CD consists of a preamble, Beginning of Frame flag (BOF), address field, information field, CRC, and End of Frame flag (EOF) as
shown in Figure 3.1.

IPREAMBLE IBOF IADDRESS IINFO ICRC IEOF I
Figure 3.1 Typical CSMA/CD Frame

PREAMBLE - The preamble is a series of alternating
Is and Os. The length of the preamble is programmable
to be 0, 8, 32, or 64 bits. The purpose of the preamble is
to allow all the receivers to synchronize to the same
clock edges and identifies to the other stations on-line
that there is activity indicating the link is being used.
For these reasons zero preamble length is not compatible with standard CSMAlCD, protocols. When using
CSMAlCD, the BOF is considered part of the preamble compared to SDLC, where the BOF is not part of
the preamble. This means that if zero preamble length
were to be used in CSMA/CD mode, no BOF would be
generated. It is strongly recommended that zero preamble length never be used in CSMA/CD mode. If the
preamble contains two consecutive Os, the preamble is
considered invalid. If the C152 detects an invalid preamble, the frame is ignored.
BOF - In CSMA/CD the Beginning-Of-Frame is a part
of the preamble and consists of two sequential Is. The
purpose of the BOF is to identify the end of the preamble and indicate to the receiver(s) that the address will
immediately follow.

8-17

HARDWARE DESCRIPTION OF THE 83C152

ADDRESS - The address field is used to identify which
messages are iIi.tended for which stations. The user
must assign addresses to each destination and source.
How the addresses are assigned, how they are maintained, and how each transmitter is made aware of
which addresses are available is an issue that is left to
the user. Some suggestions are discussed in Section
3.5.5. Generally, each address is unique to each station
but there are special cases where this is not true. In
these special cases, a message is intended for more than
one station. These multi-targeted messages are called
broadcast or multicast-group addresses. A broadcast
address consisting of all Is will always be received by
all stations. A multicast-group address usually is indicated by using a las the first address bit. The user can
choose to mask off all or selective bits of the address so
that the GSC receives all messages or multicast-group
messages. The address length is programmable to be 8
or 16 bits. An address consisting of all Is will always be
received by the GSC on the C152. The address bits are
always passed from the GSC to the CPU. With user
software, the address can be extended beyond 16 bits,
but the automatic address recognition will only work
on a maximum of 16 bits. User software will have to
resolve any remaining address bits.

algorithm can be used but IEEE 802.3 uses a 32-bit
CRC. The generation polynomial the CI52 uses with
the 32-bit CRC is:
G(X) = X32 + X26 + X23 + X22 +X16 + XI2 +
,
. XII + XIO + X8 + X7 + X5 + X4 + X2
.+ X + I
The CRC generator, as shown in Figure 3.2, operates
, by taking each bit as it is received and XOR'ing it with
bit 31 of the current eRC. This result is then placed in
temporary storage. The result of XOR'ing bit 31 with
the received bit is then XOR'd with bits 0, I, 3, 4, 6, 7,
9, 10, 11, 15,21,22,25 as the CRC is shifted right one
position. When the CRC is shifted right, the temporary
storage space holding the result of XOR'ing bit 31 and
the incoming bit is shifted into position O. The whole
process is then repeated with the next incoming or out.
going bit.
The usei' has no access to the CRC generator or the bits
which constitute the CRC while in CSMAlCD. On
transmission, the CRC is automatically appended to
the data being sent, and on reception, the CRe bits are
not normally loaded into the receive FIFO. Instead,
they are automatically stripped. The only indication the
user has for the status of the eRC is a pass/fail flag.
The pass/fail flag only operates during reception. A
CRC is considered as passing when the the CRC generator has 1100011100000100 11011010 011110IlB as a
remainder after all of the data, including the CRe
checksum, from the transmitting station has been cycled through the CRC generator. The preamble, BOF
and EOF are not included as part of the CRC algorithm. An interrupt is available that will interrupt the
CPU if the CRC of the receiver is invalid. The user can
enaole the CRC to be passed to the CPU by placing the
receiver in the raw receive mode.

INFO - This is the information field and contains the
data that one device on the link wishes to transmit to
another device. It can be of any length the user wishes
but needs to be in multiples of 8 bits. This is because
multiples of 8 bits are used to transfer data into or out
of the GSC FIFOs. The information field is delineated
from the rest of the components of the frame by the
preceding address field and the following CRC.. The
receiver determines the position of the end of the information field by passing the bytes through a temporary
storage space. When the EOF is received the bytes in
temporary storage are the CRC, and the last bit received previous to the CRC constitute the end of the
information field.

This method of calculating the CRC is compatible with
IEEE 802.3.

CRC - The Cyclic Redundancy Check (CRC) is an error checking algorithm commonly used in serial communicationS. The CI52 offers two types of CRC algorithms, a 16-bit and a 32-bit. The 16-bit algorithm is
normally ~sed in the SDLC mode and will be described
in the SDLC section. In CSMAlCD applications either

EOF - The End Of Frame indicates when the transmis,ion i, comnleted. The end flag in CSMA/CD consists
~i an idle c~ndition. An idle c;ndition is assumed when
there is no transitions and the link remains high for 2 or
more bit times.

8-18

HARDWARE DESCRIPTION OF THE 83C152

270427-8

Figure 3.2. CRC Generator

around period is the amount of time that is needed by
user software to complete the handling of a received
frame and be prepared to receive the next frame. An
interframe space smaller than the required tum-around
period could be used, but would allow some frames to
be missed.

3.2.3 INTER FRAME SPACE

The interframe space is the amount of time that transmission is delayed after the link is sensed as being idle
and is used to separate transmitted frames. In alternate
backoff mode, the interframe space may also be included in the determination of when retransmissions may
actually begin. The C152 allows programmable interframe spaces of even numbers of bit times from 2 to
256.

When a GSC transmitter has a new message to send, it
will first sense the link. If activity is detected, transmission will be deferred to allow the frame in progress to
complete. When link activity ceases, the station continues deferring for one interframe space period.

The period of the interframe space is determined by the
contents of IFS. IFS is an SFR that is programmable
from 0 to 254. The interframe space is measured in bit
times. The value in IFS mUltiplied by the bit time
equals the interframe space unless IFS equals O. If IFS
does equal 0, then the interframe space will equal 256
bit times. One of the considerations when loading the
IFS is that only even numbers (LSB must be 0) can be
used because only the 7 most significant bits are loaded
into IFS. The LSB is controlled by the GSC and determines which half of the IFS is currently being used. In
some modes, the interframe space timer is re-triggered
if activity is detected during the first half of the period.
The GSC determines which half of the interframe space
is currently being used by examining the LSB. A one
indicates the first half and zero indicates the second
half of the IFS.

As mentioned earlier, the interframe space is used during the collision resolution period as well as during normal transmission. The backoff method selected affects
how the deference period is handled during normal
transmission. If normal backoff mode is selected, the
interframe space timer is reset if activity occurs during
approximately the first half of the interframe space. If
alternate backoff or. deterministic backoff is selected,
the timer is not reset. in all cases whe~ the interframe
space timer expires, transmission may begin, regardless
if there is activity 'on the link or not. Although the
C152 resets the interframe space timer if activity is detected during the first one-half of the interframe space,
this is not necessarily true of all CSMA/CD systems.
(IEEE 802.3 recommends that the interframe space be
reset if activity is detected during the first two-thirds or
less of the interframe space.)

After reset IFS is 0, which delays the first transmission
for both SDLC and CSMA/CD by 256 bit times (after
reset, a bit time equals 8 oscillator clock periods).

3.2.4 COLLISION RESOLUTION

In most applications, the period of the interframe space
will be equal to or greater than the amount of time
needed to tum-around the' received frame. The turn-

The method used to resolve a collision is called the
backoff algorithm.
8-19

HARDWARE DESCRIPTION OF THE 83C152

How the backoff algorithm executes is dependent on
which part of the frame the collision was detected in.
How collisions are detected is shown in Figure 3.3. If
the collision occurred before data has been loaded into
the Receive FIFO, then reception' is simply stopped.

A collision is assumed if a pulse is less than three sample periods in length or if an. expected transition is
missed. Figures 3.3A and B show where transition must
occur and where transitions are invalid. The sample
. periods occur at a rate that is 8 times the baud rate as
determined by the SFR BAUD.

The time when the first byte is loaded into the Receive
FIFO is dependent on the CRC length. After detection
of the BOF flag, all subsequent data is passed through.
the CRC stripping/generation hardware. Also,there is
an additional delay of 8 bit times, as the Receive FIFO
operates with only eight bit quantities. This means that
after the BOF, there is a 24(40) bit time delay before
data is loaded into the Receive FIFO if the 16(32) bit
CRC is selected. If the collision occurs after data has
been loaded into the receive FIFO, then .the error flag
Receiver Abort (RCABT) is set and REN cleared. This
prevents another reception while the CPU tries to figure out what to do next. If the Enable Global Serial
(channel) Receive Error (EGSRE) interrupt (IENl.l)
is enabled the CPU is interrupted. At this time user
software must decide what actions to take to assure a
proper recovery.

LOGICAL
VALUE

1.

During transmission, each device monitors its own
transmission pin with its receive circuitry. A collision is
assumed if the receiver detects Manchester encoding
violations as defined in Figures 3.3A and B.
Where the collision occurs determines what actions are
taken. If the collision occurs after the preamble, the
Timer Collision Detect (TCDT) bit is set. If the Enable
Global Serial Transmit Error (EGSTE) interrupt
(lEN 1. 5) is enabled, the CPU is interrupted. If this type
of collision occurs, user software must determine what
actions to take for a proper recovery.
If the transmitting station detects the collision during

the preamble or BOF, the actions taken are automatic.
The transmitter will attempt resolution up to eight
tries. After the eighth attempt, the error flag (TCDT) is
set. If EGSTE is enabled, the CPU is then interrupted.

o

o

o

MANCHESTER
ENCODING

.

".,. - - - "1" BIT, TIME - - - -.....
".:..'- - "0" BIT TIME - - - -..
"
(8 X BAUD)
R.ECEIVt
SAMPLING
RATE

,

INVALID

MANDATORY TRANSITION
270427-9

Figure 3.3A. CSMA/CD COllisions
8~20

HARDWARE DESCRIPTION OF THE 83C152

LOGICAL
VALUE

o

o

MANCHESTER
ENCODING

,,>---...

.

"1" BIT TIME - - - - - - - - - - "1" BIT TIME - - - -..
"

,

(8 X BAUD)
RECEIVE
SAMPLING'
RATE

INVALID

MANDATORY TRANSITION

OPTIONAL TRANSITION
270427-10

Figure 3.3B. CSMAlCD Collisions

When a transmitting GSC detects a collision, the first
action taken is to apply a jamming signal to the link.
The jam is sent following the end of the preamble, or
immediately if the preamble has already .been completed. This action is taken to insure that other stations on
the link are aware that a collision has occurred.

algorithm is used. These methods are .named: "Normal
Backoff", "Alternate Backoff", and "Deterministic
Backoff".
Before going into detail on the various backoff schemes,
there is a parameter called the slot time that must be
understood by the user. The slot time is used during the
collision resolution and is the basic scheduling quantum
for retransmission once a collision is detected. The slot
time also represents the maximum length of a collision
fragment and the upper bound on the acquisition time
of the network. The value of the slot time is determined
by the contents of SLOTTM. SLOTTM is programmable from b to 255. A slot time is equal to 256-SLOTTM
multiplied by the bit time,unless SLOTTM equals o. If
o is used in SLOTTM, th~n the slot time period will
equal 256 bit times.· A bit time is equal to Ilbaud rate.
The timing requirements on the slot time is that it be
equal to, or greater than the longest round-trip propagation time of the signal plus the jam time. The jam
time is equal to the CRC length.

The jamming signal can be one of two types, D.C. or
CRC. D.C. jam is selected by setting the DCI bit
(MYSLOT.7). The D.C. jam applies a continuous low
level signal for a duration equal to the CRC length. To
select the CRC type of jam, the DCJ bit needs to be
cleared. CRC is selected after the C152 is reset. The
CRC,jam operates by taking the current CRC calculated up to that point, inverting the data and applying that
signal to the. link.
After applying the jam, the resolution phase is next.
This phase will effect the throughput and efficiency of
the link once a collision is detected. There are three
methods to choose from that determine which backoff
8-21

intJ

HARDWARE DESCRIPTION OF THE 83C152

In alternate mode the backoff time begins immediately
at the end of an interframe space after the jam. If alternate backoff is used then the slot time does not occur
unin after the interframe space expires as shown in Figure 3.4. This mode will usually be used when the interframe space is longer than the slot time. This prevents
the situation where the slot time expires before the interframe space period. This preserves the bandwidth of
the collision resolution by insuring that each station is
allowed up to 8 re-attempts at transmission. Networks
where the slot time is less than the interframe space
generally exist where there is a short topology, or high
data rates are used.

Normal and Alternate CSMA/CD Modes
In the Normal and Alternate Normal resolution modes,
the slot position assigned .to a station is determined by
the SFR, Pseudo Random Binary Sequence (PRBS).
The PRBS generates a random number by using a series of feedback shift registers that are clocked by the
CPU phase clocks.
There is a maximum physical limit of 256 slot positions
available. The slot assigned is derived from PRBS during the resolution phase of a collision. But the value in
PRBS is ANDed' with the contents of TCDCNT. The
way TCDCNT operates is that as collisions occur,
TCDCNT shifts left one bit position and a 1 is shifted
into the LSB. As TCDCNT is filled with Is from collisions, the maximum range of slot assignments also increases by powers of 2. This variable upper limit is determined by the number of collisions, but can never be
greater than 255. The PRBS maximum value will be
(2**n)-I, where n is the number. of pre~?usly a~­
tempted transmissions that resulted In a colliSion. This
means that on the first re-transmission, the PRBS value
could be 0 or I, on the second re-transmission the
PRBS could be any value from 0 to 3, and on the eighth
collision PRBS could be any value from 0 to 255. There
is no way that the user software can get access to the
slot position assigned to a station once the backoff process has started.

Deterministic Collision Resolution
In Deterministic Collision Resolution, when a collision
occurs, all stations enter a special mode, whether or not
they were involved in the collision. The resolution p~ri­
od is divided into a programmable number of slots With
each station having a unique slot assignment. The first
slot starts after one interframe space. A station is allowed to start transmitting only during its own slot and
will transmit as long as it needs to unless some error
occurs. After any transmission, one interframe expires
before the next slot begins. If no collision occurs, the
protocol operates as in regular CSMA/CD mode.

The backoff can be programmed to start either at the
end of the jam, as in Ethernet, or at the end of the
interframe space.
In normal mode the backoff time begins immediately at
the end of the jam. The slot time begins as soon as the .
jam is completed but must wait until at le~t one int~r­
frame space has completed before attemptIng transnussion. Slot 0 is the first to occur, followed by Slot 1 and
so on. This means the lowest slot number assigned will
win control of the link as long as the slot time ends
after the the interframe space expires. In networks
where the slot time is longer than the interframe space,
normal backoff will usually be implemented. This is
because the interframe space time will expire before
Slot 0 is complete. This is shown in Figure 3.4. In net- .
works where the interframe space is longer than the slot
time, Slot 0 will expire before the interframe space and
will not be able to transmit during that resolution attempt. Taken to an extreme where the interframe space
is much larger than the slot time, it is possible that
there will be no resolution during the first couple of
collisions because the possible number of slot times
available will still be less than the interframe space.
This would waste the bandwidth of the resolution by
not allowing all stations the opportunity of 8 attempts
at retransmission.

8-22

This method operates as follows. The user software assigns each station its own slot position and loads it in
the SFR, MYSLOT. That station has to wait a number
of slot times equal to (maximum number of slots) (MYSLOT). Only the lower six bits of MYSLOT are
used for slot assignment. This means that when using
deterministic resolution, a maximum of 63 stations in
the network can participate in any collision resolution.
Another station may be added to the network, but not
allowed to participate in a resolution. That station
should have 0 as its assigned slot. This prevents the
station from attempting to retransmit during the collision resolution. When using deterministic resolution,
the PRBS must be disabled. By writing OFFH into the
PRBS, it is frozen into an all Is st.at.e. The maximum
number of stations that may be involved in the resolution is loaded into TCDCNT. The slot count does not
begin until the receiver senses that the line is idl~ and
one interframe space expires. At the end of the Interframe space the GSC starts counting the slots. Alternate backoff mode should be selected whenever deterministic backoff mode is being used. Then, if activity is
detected on the link with deterministic backoff mode
selected, the GSC first waits uhtil the link is idle and
then waits until the end of the interframe space before
the slot timer continues counting the slots. This allows
another station to transmit a pending message in its
proper slot and 'each station gets an opportunity to
transmit when the slot time equals the value in its
MYSLOT register.

HARDWARE DESCRIPTION OF THE 83C152

The bottom diagram of Figure 3.4 illustrates this mechanism for a number of stations (MAX). It shows stations with slot numbers (MAX-2), 2 and I transmitting
during the resolution period. Note the interframe space
after the jam and after each transmission. After all the
slot positions have been exercised, normal CSMA/CD
operation resumes. Unless deterministic resolution is
selected, it is possible that stations not involved in the

collision may attempt transmission during the resolution period after an interframe space period. Deterministic mode prevents this from happening because all
stations on the link are required to enter into the resolution phase, whether or not they are involved in the
collision. Then, a station is either allowed to transmit
during its assigned slot or is prevented from transmitting during the resolution period.

Normal 8ackoff

Alternate 8ackoff

~.
SLOT TIME

FIRST

IFS
FIRST

~.
SLOT TIME
SECOND

IFS

ST

IFS
IFS ST

SLOT TIME

SLOT TIME

SLOT TIME

SLOT TIME

SECOND
SLOT TIME

COLLISION-

IFS

ST ST

IFS

ST Sf. ST

COLLISION

270427-11

Normal 8ackoff Mode
(CURRENT
BACKOFF
VALUE=) ~.- - - - - - ( 5 ) . (4) (3) (2) (.) (0)

(lN~IAL =><+!_+_--:)>.j..:~:,-:-----~:~-:-:-:-::-:-:-:-:
j

BACKOFF

I

I

: :.... : :
I

I
:

I

I

VALUE=5):
...

I

It-,

I

I

I

I

I

~ :~: :I!!: ~ : r:: :'~ : ~ : ~

,

(CURRENT
BACKOFF

VALUE=)~'------' (3) (2) (') (0)

-V:

)::::

:
Ie,

(INI~IAL -"...c:""_+-_J.""'''' "

9ACKOFF
.,
VALUE=3):

: :.... : :
1,1-,

~ :12:

;::
T1
T2
T3
T4
T5

=
=
=
=

=

I

:I!!:

I

I

I

~: J:::: ~:

270427-12

T6 = Slot A(#4) or 8(#2) Occurring
T7 = Slot A( # 3) or 8( # 1) Occurring
T8 = Slot A( # 2) Occurring
T8 = Station 8 8egins Transmission
T10 = Station A Loses Slot Assignment

Collision Detected
Jam Applied
Idle Detected
Interframe Space Period
Slot A( # 5) or 8( # 3) Occurring

Deterministic 8ackoff .Mode

,,
,
, ,, ,

,,
,
, ,, ,
;::
T1
T2
T3
T4
T5
T6
T7

~

,

~

1.... '&1')1
11-11-1

~

~

'00 10'1'
11-11-1

= Collision Detected
= Jam Applied
= 1 IFS, No Activity

0

;::

,

;::

;::

;::
'"

...

;::
270427-13

T8 = Assume Slot Time 4 Occurring
T9 = Slot Time 3 Occurring
T1 0 = Slot Time 2 Occurs with Activity
T11 = IFS for Slot Time 2
T12 = Slot Time 1 Occurs with Activity
T13 = IFS for Slot Time 1
T14 = Normal CSMAlCD Activity

Slot Time for Maximum Available Slot Occurring
Slot Time for (MAX·1) Occurring
= Slot Time for (MAX·2) Occurs with Activity
= IFS for Slot Time (MAX·2)
=
=

. Figure 3.4. Slot Time Resolution
8-23

inter

HARDWARE DESCRIPTION OF THE 83C152

A transmitting station with HABEN enabled expects
an acknowledge. It must receive one prior to the end of
the interframe space, or else an error is assumed and
the NOACK bit is set. Setting of the TON bit is also
delayed until the end of the interframe space. Collisions
detected during the interframe space will also cause
NOACK to be set.

3.2.5 CSMA/CD DATA ENCODING
Manchester encoding/decoding is automatically selected when the user software selects CSMA/CO transmission mode (See Figure 3.5). In Manchester encoding
the value of the bit is determined by the transition in
the middle of the bit time, a positive transition is decoded as a 1 and a negative transition is decoded as a O.

The user software may enable the interrupt so that the
CPU is notified when TON is set. If the OSC is serviced by OMA, the user must time out one interframe
space and then check the NOACK bit or the TON bit.

If the external IX clock feature is chosen the transmission mode is always NRZ (see Section 3.5.11). Using
CSMA/CO with the external clock option is not supported because the data needs reformatting from NRZ
to Manchester for the receiver to be able to detect code
violations and collisions.

3.3 SOLe Operation

3.2.6 HARDWARE BASED ACKNOWLEDGE

3.3.1 SDLC OVERVIEW

Hardware Based Acknowledge (HBA) is a data link
packet acknowledging scheme that the user software
can enable with CSMA/CO protocol. It is not an option with SOLC protocol however.

SOLC is a communication protocol developed by IBM
and widely used in industry. It is based on a primary/
secondary architecture and requires that each secondary station have a unique address. The secondary stations can only communicate to the primary station, and
then, only when the primary station allows communication to take place. This eliminates the possibility of
contention on the serial line caused by the secondary
station'S trying to transmit simultaneously.

In general HBA can give improved system response

time and increased effective transmission rates over acknowledge schemes implemented in higher layers of the
network architecture. Another benefit is the possibility
of early release of the transmit buffer as soon as the
acknowledge is received.

In the CIS2, SOLC can be configured to work in either
full or half duplex. When adhering to strict SOLC protocol, full duplex is required. Full duplex is selected
whenever a 16-bit CRC is selected. At the end of a valid
reset thel6"bit CRC is selected. To select half duplex
with a 16-bit CRC, the receiver must be turned off by
user software before transmission. The receiver is
turned off by clearing the OREN bit (RSTAT.l). The
receiver needs to be turned off because the address that
is transmitted is the address. of the secondary station'S
receiver. If not turned off, the receiver could mistake
the outgoing message as being intended for itself. When
32-bit CRCs are used, half duplex is the only method
available for transmission.

The acknowledge consists of a preamble followed by an
idle condition. A receiving station with HABEN enabled will send an acknowledge only if the in"oming
address is unique to the receiving station and if the
frame is determined to be correct with no errors. 'For
the acknowledge to be sent, ten must be set. For the
transmitting· station to recognize the acknowledge
OREN must be set. A zero as the LSB of the address
indicates that the address is unique and not a group or
broadcast address. Errors can be caused by collisions,
incorrect CRC, misalignment, or FIFO overflow. The
receiver sends the acknowledge as soon as the line is
sensed to be idle. The l!~cr must progI1h~ the interframe
space and the preamble length such that the acknowledge is completed before IFS expires. This is normally
done by programming IFS larger than the preamble.

o

o

I
BIT
I
- - TIME--+;

o

270427-14

Figure 3.5. Manchester Encoding

8-24

inter

HARDWARE DESCRIPTION OF THE 83C152

3.3.2 SOLC Frame Format
The format of an SOLC frame is shown in Figure 3.6.
The frame consists of a Beginning of Frame flag, Address field, Control Field, Information field (optional),
a CRC, and the End of Frame flag.

IBOF IADDRESS ICONTROL IINFO ICRC IEOF I
Figure 3.6. Typical SOLC Frame

BOF - The begin of frame flag for SOLC is 01111110.
It is only one of two possible combinations that have six

consecutive ones in SOLC. The other possibility is an
abort character which consists of eight or more consecutive ones. This is because SOLC utilizes a process
called bit stuffing. Bit stuffing is the insertion of a 0 as
the next bit every time a sequence of five consecutive Is
is detected. The receiver automatically removes a 0 after every consecutive group of five ones. This removal
of the 0 bit is referred to as bit stripping. Bit stuffing is
discussed in Section 3.3.4. All the procedures required
for bit stuffing and bit stripping are automatically han. died by the GSC.
In standard SOLC protocol the BOF signals the start of
a frame and is limited to 8 bits in length. Since there is
no preamble in SOLC the BOF is considered an entire
separate field and marks the beginning of the frame.
The BOF also serves as the clock synchronization
mechanism and the reference point for determining the
position of the address and control fields.
AOORESS - The address field is used to identify which
stations the message is intended for. Each secondary
station must have a unique address. The primary station must then be made aware of which addresses are
assigned to each station. The address length is specified
as 8-bits in standard SOLC protocols but it is expandable to 16-bits in the C152. User software can further
expand the number of address bits, but the automatic
address recognition feature works on a maximum of 16bits.

CONTROL - The control field is used for initialization
of the system, identifying the sequence of a frame, to
identify if the message is complete, to tell secondary
stations if a response is expected, and acknowledgement
of previously sent frames. The user software is responsible for insertion of the control field as the .GSC hardware has no provisions for the management· of this
field. The interpretation and formation of the control
field must also be handled by user software. The information following the control field is typically used for
information transfer, error reporting, and various other
functions. These functions are accomplished by the format of the control field. There are three formats available. The types of formats are Informational, Supervisory, or Unnumbered. Figure 3.7 shows the various format types and how to identify them.
Since the user software is responsible for the implementation of the control field, what follows is a simple explanation on the control field and its functions. For a
complete understanding and proper implementation of
SOLC, the user should refer to the IBM document,
GA27-3093-2, IBM Synchronous Oata Link Control
General Information. Within that document, is another
list of IBM documents which go into detail on the
SOLC protocol and its use.
The control field is eight bits wide and the format is
determined by bits 0 and 1. If bit 0 is a zero, then the
frame is an informational frame. If bit 0 is a one and bit
1 a zero, then it is a supervisory frame, and if bit 0 is a
one and bit I a one then the frame is an unnumbered
frame.
In an informational frame bits 3,2,1 contain the sequence count of the frame being sent.
Bit 4 is the P IF (Poll/Final) bit. If bit 4 equals 1 and
originates from the primary, then the secondary station
is expected to initiate a transmission. If bit 4 equals 1
and originates from a secondary station, then the frame
is t~e final frame in a transmission.

In SOLC the addresses are normally unique for each
station. However, there are several classes of messages
that are intended for more than one station. These messages are called broadcast and group addressed frames.
An address consisting of allIs will always be automatically received by the GSC, this is defined as the broadcast address in SOLC. A group address is an address
that is common to more than one station. The GSC
provides address masking bits to provide the capability
of receiving group addresses.
If desired, the user software can mask off all the bits of

the address. This type of masking puts the GSC in a·
promiscuous mode so that all addresses are received.

8-25

Bits 7,6,5 contain the sequence count a station expects·
on the next transmission to it. The sequence count can
vary from OOOB to 11 lB. The count then starts over
again at OOOB after the value IliB is incremented. The
acknowledgement is recognized by the receiving station
when it decodes bits 7,6,5 of an incoming frame. The
station sending the transmission is acknowledging the
frames received up to the count represented in bits 7,6,5
(sequence count-I). With this method, up to seven sequential frames may be transmitted prior to an acknowledgement being received. If eight frames were allowed to pass before an acknowledgement, the sequence
count would roll over and this would negate the purpose of the sequence numbers.

HARDWARE DESCRIPTION OF THE 83C152

BIT
POSITIONS-

7

65
.

4

o

321

SENDING
SEQUENCE

RE¢'EPTjlON
SEQUENCE

270427-15

RECEPTION SEQUENCE - The sequence expected in (the SENDING SEQUENCE portion of the control byte
in the next received frame. This also confirms correct reception of up to seven frames prior to the sequence given.
POLL/FINAL - Identifies the frame as being a polling request from the master station or the last in a series of
frames from the master or secondary;
SENDING SEQUENCE- Identifies the sequence of the frame being transmitted.
o - If bit 0 = 0 the frame. is identified as a informational format type.

INFORMATION FORMAT

-----------------~----------------------------~--------M
POSITIONS-

7

6

5

4

3

o

.2

~R-E~C-E-P-T~:IO-N-,-po-LL-/~~--~--~~

SEQ UEN CE

FINAL

270427-16

RECEPTION SEQUENCE - Expected sequenceofframe for next reception.
POLL/FINAL - Identifies frame as being a polling request from the' master station or the last in a series of
frames from the master or secondary.
.
MODE - Identifies whether receiver is ready (00), not ready (10) or a frame was rejected (Oi). The rejected frame
is identified by the reception sequence.
.
0,1 - If bits I,D = 0,1 the frame is identified as a supervisory format type.

SUPERVISORY FORMAT

-------------~--------------------------------~-~------. M
7
6
5
432
1 0
POSITIONS-.--_ _·..,.--_ _,--_ _- - - . . - - - - , - -___- - - - . . . - -.....

,I.

.

COMMAND/ IpOLL/ICOMMAND/1
R~sPoNsE ViNAl·1 RESPONSE I

1 1
I

I

II

270427-17

COMMAND/RESPONSE - Identifies the type of command. or response.
POLL/FINAL - Identifies frame as being a polling request from the master station or the last in a series of
frames from the master or secondary.
1,1 - If bits I,D == 1,1 the 'frame is identified as an unnumbered format type.

NONSEQU'ENCED FO'RMAT
,

Figure 3.7. SDLC Control Field

8-26

270427-18

inter

HARDWARE DESCRIPTION OF THE 83C152

Following the informational control field comes the information to be transferred.

When the mode is 10, the sending station is indicating
that its receiver is not ready to accept frames.

In the supervisory format (bits 1,0 = 0,1) bits 3,2 determine which mode is being used.

Mode 11 is an illegal mode in SDLe protocol.

When the mode is 00 it indicates that the receive line of
the station that sent the supervisory frame is enabled
and ready to accept frames.

Bits 7,6,5 represent the value of the sequence the station expects when the next transfer occurs for that station. There is no information following the control field
when the supervisory format is used.

When the mode is 01, it indicates that previously a
received frame was rejected. The value in the receive
count identifies which frame(s) need to be retransmitted.

In the unnumbered format (bits 1,0 = 1,1) bits 7, 6, 5,
3, 2 (notice bit 4 is missing) indicate commands from
the primary to secondary stations or requests of secondary stations to the pritnary.

The standard commands are:
BITS 7 6 5 3 2 Command
0 0 0 0 0 Unnumbered Information (UI)
0 0 0 0 1 Set initialization mode (SIM)
0 1 0 0 0 Disconnect (DISC)
0 0 1 0 0 Response optional (UP)
1 1 0 0 1 Function descriptor in
information field (CFGR)
1 1 Identification in information field. (XID)
0
1
0 0 Test pattern in information field. (TEST)

The standard responses are:
BITS 7 6 5 3 2 Command
0 0 0 0 0 Unnumbered information (UI)
0 0 0 0 1 Request for initialization (RIM)
0 0 0 1 1 Station in disconnected mode (OM)
1 0 0 0 1 Invalid frame received (FRMR)
0 1 1 0 0 Unnumbered acknowledgement (UA)
1 1 1 1 1 Signal loss of input (BCN)
1 1 0 0 1 Function descriptor in information field (CFGR)
0 1 0 0 0 Station wants to disconnect (RD)
1 0 1 1 1 Identification in information field (XID)
1 1 1 0 0 Test pattern in information field (TEST)

8-27

HARDWARE 'DESCRIPTION OF THE 83C152

rithms, a 16-bit and a 32-bit. The 32-bit algorithm is
normally used in. CSMAlCD applications and is described in section 3.2.2. In most SDLC applications a
16-bit CRC is used and the hardware configuration that
supports 16-bit CRC is shown in Figure 3.8; The generating polynomial that the CRC generator uses with the
16-bit CRC is:

In an unnumbered frame, information of variable
length may follow the control field if UI is, used, or
information of fixed length may follow if FRMR is
used.
As stated earlier, the user software is responsible for the

proper management of the control field. This portion of
the frame is passed to or from the GSCFIFOs as basic
informational type data.

G(X)

=

X"16

+ X"12 + X"5 +

1

The way the CRC operates is that as a bit is received it
is XOR'd with bit 15 of the current CRC and placed in
temporary storage. The result of XOR'ing bit 15 with
the received bit is then XOR'dwith bit 4 and bit 11 as
the CRC is shifted one position to the right. The bit in
temporary storage is shifted into position O.

INFO - This is the information field and contains ,the
data that,one device on the 'link' wishes to transmit to
another device. It can be of any length the user wishes,
but must be a multiple of 8 bits. It is possible that some
frames may contain no information field. The information field is identified to the receiving stations by the
preceding control field and the following CRC. The
GSC determines where the last of the information field
is by passing the bits through the CRC generator.
When the last bit or BOF is received the bits that remain constitute the CRC.

The required CRC length for SDLC is' 16 bits. The
CRC is automatically stripped from the frame and not
passed on: to the CPU. The last 16 bits ,are then run
though the CRC generator to insure that the correct
remainder is left. The remainder that is checked for is
001110100001111B (lDOF Hex). If there is a mismatch, an error is generated. The user software has the
optiqn of enabling this interrupt so the CPU is notified.

CRC - The Cyclic Redundancy Check (CRC) is an error checking sequence commonly used in serial communications. The C152 offers two types of CRC algo-

270427-19

Figure3_8_16-BitCRC

8-28

inter

HARDWARE DESCRIPTION OF THE 83C152

EOF - The End Of Frame (EOF) indicates when the
transmission is complete. The EOF is identified by the
end flag. An end flag consists of the bit pattern
01111110. The EOF can also serve as the BOF for the
next frame.

3.3.5 SENDING ABORT CHARACTER
An abort character is one of the exceptions to the rule
that disallows more than 5 consecutive Is. The abort
character consists of any occurrence of seven or more
consecutive ones. The simplest way for the CI52 to
send an abort character is to clear the TEN bit. This
causes the output to be disabled which, in turn, forces it
to a constant high state. The delay necessary to insure
that the link is high for seven bit times, is a task that
needs to be handled by user software. Other methods of
sending an abort character are using the IFS register or
using the Raw Transmit mode. Using IFS still entails
clearing the TEN bit, but TEN can be immediately reenabled. The next message will not begin until the IFS
expires. The IFS begins timing out as soon as DEN
goes high which identifies the end of transmission. This
also requires that IFS contain a value equal to or greater than 8. This method may have the undesirable effect
that DEN goes high and disables the external drivers.
The other alternative is to switch to Raw Transmit
mode. Then, writing OFFH to TFIFO would generate a
high output for 8 bit times. This method would leave
DEN active during the transmission of the abort character.

3.3.3 DATA ENCODING
The transmission of data in SDLC mode is done via
NRZI encoding as shown in Figure 3.9. NRZI encoding transmits data by changing the state of the output
whenever a 0 is being transmitted. Whenever a I is
transmitted the state of the output remains the same as
the previous bit and remains valid for the entire bit
time. When SDLC mode is selected it automatically
enables the NRZI encoding on the transmit line and
NRZI decoding on the receive line.
3.3.4 BIT STUFFING/STRIPPING
In SDLC mode one of the primary rules of the protocol
is that in any normal data transmission, there will never
be an occurrence of more than 5, consecutive Is. The
GSC takes care of this housekeeping chore by automatically inserting a 0 after every occurrence of 5 consecutive Is and the receiver automatically removes a zero
after receiving 5 consecutive Is. All the necessary steps
required for implementing bit stuffing and stripping are
incorporated into the GSC hardware. This makes the
operation transparent to the user. About the only time
this operation becomes apparent to the user, is if the
actual data on the transmission medium is being monitored by a device that 'is not aware of the automatic
insertion of Os. The bit stuffing/stripping guarantees
that there will be at least one transition every 6 bit
times while the line is active.

o

BIT

When the receiver detects seven or more consecutive Is
and data has been loaded into the receive FIFO, the
RCABT flag is set in RSTAT and that frame is ignored. If no data has been loaded into the receive
FIFO, there are no abort flags set and that fraine is just
ignored. A retransmitted frame may immediately folIowan abort character, provided the proper flags are
used.

,

,

o

o

'

-TIME~

270427-20

Figure 3.9. NRZI Encoding

8-29

inter

HARDWARE DESCRIPTION OF THE 83C152

passing the message to the downstream· station. This
delay is necessary so that a station can decode its own
address before the message is passed on. The various
networks are shown in Figure 3.10.

3.3.6 LINE IDLE
If 15 or more consecutive Is are detected by the receiver the Line Idle bit (LNI) in TSTAT is set. The seven
Is from the abort character may be included when sensing for a line idle condition. The same methods used for
sending the Abort character can be used for creating
the Idle condition. However, the values would need to
be changed to reflect 15 bit times, instead of seven bit
times.

3.3.9 HDLC/SDLC COMPARISON
HDLC (High level Data Link Control) is a standard
adopted by the International Standards Organization
(ISO). The HDLC standard is defined in theISO document #ISO 6159 - HDLC unbalanced classes ofprocedures. IBM developed the SDLC protocol as a subset of
HDLC. SDLC conforms to HDLC protocol requirements, but is more restrictive. SDLC contains a more
precise definition on the modes of operation.

3.3.7 ACKNOWLEDGEMENT
Acknowledgment in SDLC is an implied acknowledge
/ and is contained in the controi field. Part of the control
frame is the sequence number .of the next expected
frame. This sequence number is caUed the Receive
Count. In transmitting the Receive Count, the receiver
is in fact acknowledging aU the previous frames prior to
the count that was transmitted. This allows for the
transmission of up to seven frames before an acknowledge is required back to the transmitter. The limitation
of seven frames is necessary because the Receive Count
in the control field is limited to three binary diiits. This
means that if an eighth transmission occurred this
would cause the next Receive Count to repeat the first
count that still is waiting for an acknowledge. This
would defeat the purpose of the acknowledgement. The
processing and general maintenance of the sequence
cOunt must be done by the user software. The Hardware Based Acknowledge option that is provided in the
Cl52 is not compatible with standard SDLC protocol.

Some of the major differences between SDLC and
HDLCare:
SDLC
HDLC
Unbalanced (primary/
secondary)
Modulo 8 (no extensions
allowed, up to 7 outstanding frames before
acknowledge is required)
8-bit addressing only
Byte aligned data

Balanced
(peer to peer)
Modulo 128 (up to 127
outstanding frames
before acknowledge
is required)
Extended addressing
Variable size of data

The C152 does not support HDLC implementation requiring data alignment other than byte alignment. The
user wiU find that many of the protocol parameters are
programmable in the Cl52 which allows easy implementation of proprietary or standard HDLC network.
User software needs to implement the control field
functions.

3.3.8 PRIMARY/SECONDARY STATIONS
All SDLC networks are based upon a primary/secondary station relationship. There can be only one primary
station in a network and aU the other stations are considered secondary. All communication is between the
primary and secondary station. Secondary station to
secondary station direct communication is prohibited.

3.4 User Defined Protocols
The explanation on the implementation of user defined
protocols would go beyond the scope of this manual,
but examining Table 3.1 should give the reader a consolidated list of niost of the possibilities. In this manual,
any deviation from the documents that cover the implementation of CSMA/CD or SDLC are considered user
defmed protocols. Examples of this would be the use of
SDLC with the 32-bit CRC selected or CSMA/CD
with hardware based acknowledge.

If there is a need for secundary to secondary COfliiliuni-

cation, the user software will have to make aUowances
for the master to act as an intermediary. Secondary
stations are aUowed use of the serial line only when the
master permits them. This is done by the master polling
the secondary stations to see if they have a need to
access the serial line: This should prevent any collisions
from occurring, provided each secondary station has its
own unique address. This arrangement also partiaUy
determines the types of networks supported. Normal
SDLC networks consist of point-to-point, multi·drop,
or ring configurations and the Cl52 supports aU of
these. However, some SDLC processors support an automatic one bit delay at each node that is not supported
by the C152. In a "Loop Mode" configuration, is is
necessary that the transmission be delayed from the reception of the frames from the upstream station before

3.5 Using the GSC
3.5.1 LINE DISCIPLINE
Line discipline is how the management of the transfer
of data over the physical medium is controlled. Two
types of line discipline will be discussed in this section:
full duplex and half duplex.
8-30

HARDWARE DESCRIPTION OF THE 83C152

Point-to-Point Network

270427-21

Multi-Drop Network

270427-22

Ring Network

270427-23

Figure 3.10. SOLe Networks

8-31

inter

HARDWARE DESCRIPTION OF THE 83C152

Full duplex is the simultaneous transmission and reception of data. Full duplex uses anywhere from two to
four wires. At least one wire is needed for transmission
and one wire for reception. Usually there will also be a
ground reference on each signal if the distance from
station to station is relatively long. Full-duplex operation in the C152 requires that both the receive and the
transmit portion ,of the GSC are functioning at the
same time. Since both the transmitter and receiver are
operating, two CRC generators are also needed. The
C152 handles this problem by having one 32-bit CRC
generator and one 16-bit CRC generator. When supporting full-duplex operation, the 32-bit CRC generator
is modified to work as a 16-bit CRC generator. Whenever the 16-bit CRC is selected, the GSC automatically
enters the full duplex mode. Half duplex with a 16-bit
CRC is discussed in the following paragraph.

Some of the general areas that will impact the overall
scheme on how to incorporate future changes to the
system are:
1) Communication of the change to all the stations or
the primary station.
2) Maximum distance for communication. This will affect the drivers used and the slot time.
3) More stations may be on the line at one time. This
may impact the interframe space or the collision resolution used.

Half duplex is the alternate transmission and reception
of data over a single cornmon wire. Only one or two
wires are needed in half-duplex systems. One wire is
needed for the signal and if the distance to be covered is
long there will also. be a wire for the ground reference.
In half-duplex mode, only the receiver or- transmitter
can operate at one time. When the receiver or transmitter operates is determined by user software, but typically the receiver will always be enabled unless the GSC is
transmitting. Whenever half duplex is being used the
software must insure that only the receiver or transmit- .
ter is enabled at any given time. This is particularly
important when using SDLC, so that the receiver will
not recognize its own address when the transmitter is
operating. Half-duplex operation in the C152 is supported with either 16-bit or 32-bit CRCs. Whenever a
32-bit CRC is selected, only half-duplex operation can
be supported by the GSC. It is possible to simulate fullduplex operation with a 32-bit CRC, but this would
require that the CRC be performed with software. CaIculating the CRC with the CPU would greatly reduce
the data rates that could be used with the GSC. Whenever a 16-bit CRC is selected, full-duplex operation is
automatically chosen and the GSC must be reconfig-

ured if half-duplex operation is preferred.

4) If using CSMAlCD without deterministic resolution, any increase in network size will have a negative
impact on the average throughput of the network and
lower the efficiency. The user will have to give careful
consideration when deciding how large a system can
ultimately be and still maintain adequate performance.
3.5.3 DMA SERVICING OF GSC CHANNELS

There are two sources that can be used to control the
GSC. The first is CPU control and the second is DMA
control.
CPU control is used when user software takes care of
the tasks such as: loading the TFIFO, reading the RFIFO, checking the status flags, and general tracking of
the transmission process. As the number of tasks grow
and higher data transfer rates are used, the overhead
required by the CPU becomes the dominant consumption of time. Eventually, a point is reached where the
CPU is spending 100% of its time responding to the
needs of the GSC. An alternative is to have the DMA
channels control the GSC.
A detailed explanation on the general use of the DMA
channels is covered in Section 4. In this section only
those details required for the use of the DMA channels
with the GSC will be covered.
The DMA channels can be configured by user software
so that the GSC data transfers are serviced by the
DMA controller. Since there are two DMA channels,
one channel can be used to service the receiver, and one
channel can. be used to service the transmitter. In using
the DMA channels, the CPU is relieved of much of the
time required to do the basic servicing ofthe GSC buffers. The types of servicing that the DMA channels can
provide are: loading of the transmit FIFO, removing.
data from the receive FIFO, notification of the CPU
when the transmission or reception has ended, and response to certain error conditions. When using the

3.5.2 PLANNING FOR NETWORK CHANGES
AND EXPANSIONS

A complete explanation on how to plan for network
expansion will not be covered in this manual as there
are far too many possibilities that would need to be
discussed. But there are several areas that will have
major impact when allowing for changes in the system.
In cases where there will never be any changes allowed,
expansion plans become a mute issue. However, it is
strongly suggested that there always be some allowance
for future modifications.

8-32

inter

HARDWARE DESCRIPTION OF THE 83C152

that will be received, up to 64K. If not using the Done
flag, then GSC servicing would be driven by the receive
Done (RDN) flag and/or interrupt. RDN is set when
the EOF is detected. When using the RDN flag, RFNE
should also be checked to insure that all the data has
been emptied out of the receive FIFO.

DMA channels the source or destination of the data
intended for serial transmission can be internal data
memory, external data memory, or any of the SFRs.
The only tasks required after initialization of the DMA
and GSC registers are enabling the proper interrupts
and informing the DMA controller when to start. After
the DMA channels are started all that is required of the
CPU is to respond to error conditions or wait until the
end of transmission.

The byte count register is used for all transmissions and
this means that all packets going out will have to be of
the same length or the length of the packet to be sent
will have to be known prior to the start of transmission.
When using the DMA channels to service the GSC
transmitter, there is no practical way to disable the
Done flag. This is because the transmit done flag
(TDN) is set when the transmit FIFO is empty and the
last message bit has been transmitted. But, when using
the DMA channel to service the transmitter, loads to
the TFIFO continue to occur until the byte count
reaches O. This makes it impossible to use TDN as a
flag to stop the DMA transfers to TFIFO. It is possible
to examine some other registers or conditions, such as
the current byte count, to determine when to stop the
DMA transfers to TFIFO, but this is not recommended
as a way to service the DMA and GSC when transmitting because frequent reading of the DMA registers will
cause the effective DMA transfer rate to slow down.

Initialization of the DMA channels requires setting up
the control, source, and destination address registers.
On the DMA channel servicing the receiver, the control register needs to be loaded as follows: DCONn.2 =
0, this sets the transfer mode so that response is to GSC
interrupts and put the DMA control in alternate cycle
mode; DCONn.3 = 1, this enables the demand mode;
DCONnA = 0, this clears the automatic increment
option for the source address; and DCONn.5 = I, this
defines the source as SFR: The DMA channel servicing
the receiver also needs its source address register to
contain the address of RFIFO (SARHN = XXH,
SARLN = OF4H). On the DMA channel servicing the
transmitter, the control register needs to be loaded as
follows: DCONn.2 = 0; DCONn.3 = I; DCONn.6 =
0, this clears the automatic increment option for the
destination address; and DCONn.7 = I, this sets the
destination as SFR. The DMA channel serving the
transmitter also requires that its destination address
register contains the address of TFIFO (DARHN =
XXH, DARLN = 85H). Assuming that DCONO
would be serving the receiver and DCONI the transmitter, DCONO would be loaded with XXIOIOXOB
and DCONI would be loaded with IOXXIOXOB. The
contents of SARRO and DARHI do not have any impact when using internal SFRs as the source or destination.

When using the DMA channels, initialization of the
GSC would be exactly the same as normal except that
TSTAT.O = I (DMA), this informs the GSC that the
DMA channels are going to he lIsed to service the GSC.
Although only TSTAT is written to, hoth the receiver
and transmitter use this sallie DMA hit.

When using the DMA channels to service the GSC, the
byte count registers will also need to be initialized.
The Done flag for the DMA channel servicing the receiver should be used if fixed packet lengths only are
being transmitted or to insure that memory is not overwritten by long received data packets. Overwriting of
data can occur when using a smaller buffer than the.
packet size. In these cases the servicing of the DMA
and/or GSC would be in response to the DMA Done
flag when the byte ~ount reaches zero.
In some cases the buffer size is not the limiting factor
and the packet lengths will be unknown. In these cases
it would be desirable to eliminate the function of the
Done flag. To effectively disable the Done flag for the
DMA channel servicing the receiver, the byte count
should be set to some number larger than any packet

8-33

The interrupts EGSTE (IEN1.5), GSC transmit error;
EGSTV (lEN 1.3), GSC transmit valid; EGSRE
(IENl.l), GSC receive error; and EGSRV (IENl.O),
GSC receive valid; need to be enabled. The DMA interrupts are normally not used when servicing the GSC
with the DMA channels. To ensure that the DMA interrupts are not responded to is a function of the user
software and should be checked by the software to
make sure they are not enabled. Priority for these interrupts can also be set at this time. Whether to use high
or low priority needs to be decided by the user. When
responding'to the GSC interrupts, if a buffer is being
used to store the GSC information, then the DMA registers used for the buffer will probably need updating.
After this initialization, all that needs to be done when
the GSC is actually going to be used is: load the byte
count, set-up the source addresses for the DMA channei servicing the transmitter, set-up the destination addresses for the DMA channel servicing the receiver,
and start the DMA transfer. The GSC enable bits
should be set first and then the GO bits for the DMA.
This initiates the data transfers.

intJ

HARDWARE DESCRIPTION OF THE 83C152

This simplifies the maintenance of the GSC and can
make the implementation of an external buffer for
packetized information automatic.

Initialization of the system can be broken down into
several steps. First, are the assumptions of each network station.

An external buffer can be used as the source of data for
transmission, or the destination of data from the receiver. In this arrangement, the message size is limited to
the RAM size or 64K, whichever is smaller. By using
an external buffer, the data can be accessed by other
devices which may want access to the serial data. The
amount of time required for the external data moves
will also decrease. Under CPU control, a "MOVX"
command would take 24 oscillator periods to complete.
Under DMA control, external to internal, or internal to
external, data moves take only 12 oscillator periods.

The first assumption is that the type of data encoding
to be used is predetermined for the system and that
each station will adhere to the same basic rules defining
that encoding. The second assumption is that the basic
protocol and line discipline is predetermined and
known. This means that all stations.are using CSMAI
CD or SDLC or whatever, and that all stations are
either full or half duplex. The third assumption is that
the baud rate is preset for the whole system. Although
the baud rate could probably be determined by the microprocessor just by monitoring the link, it will make it
much simpler if the baud rate is known in advance.

3.5.4 BAUD RATE

One of the first things that will be required during system initialization is the assignment of unique addresses
for each station. In a two-station only environment this
is not necessary and can be ignored. However, keep in
mind, that all systems should be constructed for easy
future expansions. Therefore, even in only a two station
system, addresses should be assigned. There are three
basic ways in which addresses can be assigned. The
first, and most common is preassigned addresses that
are loaded into the station by the user. This could be
done with a DIP-switch, through a keyboard. The second method of assigning addresses is to randomly assign an address and, then check for its uniqueness
throughout the system, and the third method is to
make an inquiry to the system for the assignment of a
unique address. Once the method of address assignment
is determined, the method should become part of the
specifications for the system to which all additions will
have to adhere. This, then, is the final assumption.

The GSC baud rate is determined by the contents of the
SFR, BAUD, or the external clock. The formula used
to determine the baud rate when using the internal
clock is:
(fosc)/«BAUD+ 1)*8)
For example if a 12 MHz oscillator is used the baud
rate can vary from:
12,000,000/«0-1- 1)'8)

=

1.5 MBPS

to:
12.000.000/«255+1)'8) ='5.859 KBPS

There are certain requirements that the external clock
will need to meet. These requirements are specified in
the data sheet. For a description of the use of the GSC
with external clock please read Section 3.5.11.

The negotiation process may not be clear for some
readers. The following two procedures are given as a'
guideline for dynamic address assignment.

3.5.5 INITIALIZATION

In the first procedure, a station assumes a random address and then checks for its uniqueness throughout the
system. As a station is initialized into the system it
sends out a message containing its assumed address.
The format of the message should be such that any
station decoding the address recognizes it as a request
for initialization. If that address is already used, the
receiving station returns a message, with its own address stating that the address in question is already taken. The initializing station then picks another address.
When the initializing station sends its inquiry for the
address check, a timer is also started. If the timer expires before the iilquiry is responded to, then that station assumes the address chosen is okay.

Initialization can be broken down into two major' components, i) iniiiaiizaiion of the component so that its
serial port is capable of proper communication; and 2)
initialization of the system or a station so that intelligible communication can take place.
Most of the initialization of the component has already
been discussed in the previous sections. Those items not
covered are the parameters required for the component
to effectively communicate with other components.
These types of issues are common to both system and
component initialization and will be covered in the following text.

8-34

inter

HARDWARE DESCRIPTION OF THE 83C152

In the second procedure, an initializing station asks for
an address assignment from the system. This requires
that some station on the link take care of the task of
maintaining a record of which addresses are used. This
station will be called station-I. When the initializing
station, called station-2, gets on the link, it sends out a
message with a broadcast address. The format of the
message should be such that all other stations on the
link recognize it as a request for address assignment.
Part of the message from station-2 is a random number
generated by the station requesting the address. Station-2 then examines all received messages for this random number. The random number could be the address
of the received message or could be within the information section of a broadcast frame. All the stations, except station-I, on the link should ignore the initialization request. Station-I, upon receiving the initialization
request, assigns an address and returns it to station-2.
Station-l will be required to format the message in such
a manner so that all stations on the link recognize it as
a response to initialization. This means that all stations
except station-2 ignore the return message.

In Raw Receive, the transmitter should be externally
connected to the receiver. To do this a port pin should
be used to enable an external device to connect the two
pins together. In Raw Receive mode the receiver acts as
normal except that all bytes following the BOF are
loaded into the receive FIFO, including the CRC. Also
address recognition is not active but needs to be performed in software. IfSDLC is selected as the protocol,
zero-bit deletion is still enabled. The transmitter still
operates as normal and in this mode most of the transmitter functions and an external transceiver can be tested. This is also the only way that the CRC can be read
by the CPU, but the CRC error bit will not be set.
3.5.7 EXTERNAL DRIVER INTERFACE

A signal is provided from the CI52 to enable transmitter drivers for the serial link. This is provided for systems that require more than what the GSC ports are
capable of delivering. The voltage and currents that the
GSC is capable of providing are the saine levels as those
for normal port operation. The signal used to enable the
external drivers is DEN. No similar signal is needed for
the receiver.

3.5.6 TEST MODES

There are two test modes associated with the GSC that
are made available to the user. The test modes are
named Raw Receive and Raw Transmit. The test
modes are selected by the proper setting of the two
mode bits in GMOD (MO = GMOD.5, MI =
GMOD.6). If Ml,MO = 0,1 then Raw Transmit is selected. If MI,MO = 1,0 then Raw Receive is enabled.

3.5.8 JITTER (RECEIVE)

Datajitter is the difference between the actual transmitted waveform and the exact calculated value(s). In
NRZI, data jitter would be how much the actual waveform exceeds or falls short of one calculated bit time. A
bit time equals l/baud rate. If using Manchester encoding, there can be two transitions during one bit time as
shown in Figure 3.11. This causes a second parameter
to be considered when trying to figure out the complete
data jitter aniount. This other parameter is the half-bit
jitter. The half-bit jitter is comprised of the difference in
time that the half-bit transition actually occurs and the
calculated value. Jitter is important because if the transition occurs too soon it is considered noise, and if the
transition occurs too late, then either the bit is missed
or a collision is assumed.

In Raw Transmit, the transmit output is internally connected to the Receiver input. This is intended to be
used as a local loop-back test mode, so that all data
written to the transmitter will be returned by the receiver. Raw Transmit can also be used to transmit user
data. If Raw Transmit is used in this way the data is
emitted with no preamble, flag, address, CRC, and no
bit insertion. The data is still encoded with whatever
format is selected, Manchester with CSMA/CD, NRZI
with SDLC or as NRZ if external clocks are used. The
receiver still operates as normal and in this mode most
of the receive functions can be tested.

8-35

inter

HARDWARE DESCRIPTION OFTHE 83C152

LOGICAL
VALUE

o

o

o

MANCHESTER
ENCODING
'I

'f

f

(8 X BAUD
RECEIV
SAMPLING
RATE
RECEIVED
DATA

"1" BIT TIME

"1" BIT TIME

a'

"0" BIT TIME

.,

I
I

I
I

I

.. -

I
I
I

I
I
I

....

I
I
I

I
I
I

I

'1

RECEIVED
DATA

"1" BIT TIME

...

I
I

.. -

.1

1'1

I

I
I
I
I

I

I

I
, I
I
I

I

Figure 3.11. Jitter

8-36

I

I

.----I
I.
I

I
I

---- ..
270427-24

inter

HARDWARE DESCRIPTION OF THE 83C152

I

BIT
I
:~ TIME ---..:

I

I

a

a

a

L

NRZ

270427-25

Figure 3.12. Transmit Waveforms

has to be set to a 1. To select external clocking for'the
receiver, XRCLK (PCON.3) has to be set to a 1. Setting both bits to I forces external clocking for the receiver and transmitter.

3.5.9 Transmit Waveforms

The GSC is capable of three types of data encoding,
Manchester, NRZI, and NRZ. Figure 3.12 shows examples of all three types of data encoding.

The external transmit clock is applied to pin 4 (TXC),
P1.3. The external receive clock is applied to pin 5
(RXC), PI.4. To enable the external clock function on
the port pin, that pin has to be set to a 1 in the appropriate SFR, PI.

3.5.10 Receiver Clock Recovery

The receiver is always monitored at eight times the
baud rate frequency, except when an external clock is
used. When using an external clock the receiver is loaded during the clock cycle.

Whenever the external clock option is used, the format
of the transmitted and received data is restricted to
NRZ encoding and the protocol is restricted to SOLC;
With external clock, the bit stuffing/stripping is still
active with SOLC pr~.tocoI.

In CSMA/CO mode the receiver synchronizes to the
transmitted data during the preamble. If a pulse is detected as being too short it is assumed to be noise or a
collision. If a pulse is too long it is assumed to be, a
collision or an idle condition.

3.6 GSC Operation

In SOLC the synchronization takes place during the
BOF flag. In addition, pulses less than four sample periods are ignored, and assumed to be noise. This sets a
lower limit on the pulse size of received zeros.

3.6.1 Determining Line Discipline

In normal operation the GSC uses full or half duplex
operation. When using a 32-bit CRC (GMOO.3 = I),
operation can only be half duplex. If using a 16-bit
CRC (GMOO.3 = 0), full duplex is selected by default. When using a 16-bit CRC the receiver can be
turned off while transmitting (RSTAT.I = 0), and the
transmitter can be turned off during reception
(TSTAT.I = 0). This simulates half-duplex operation
when using a 16-bit CRC.

In CSMA/CO the preamble consists of alternating Is
and Os. Consequently, the preamble looks like the
waveform in Figure 3.13A and 3.13B.
3.5.11 External Clocking

To select external clocking, the user is given three
choices. External clocking.can be used with the transmitter, with the receiver, or with both. To select external clocking for the tran~mitter, XTCLK (GMOO.7)

Normally, HOLC uses a 16-bit CRC, so half duplex is
determined by turning off the receiver or transmitter.
This is so that the receiver will not detect its own ad-

8-37

inter

HARDWARE DESCRIPTION OF THE 83C152

CSMAICO Clock Recovery

o,

1 , 0

1 , 0

1 ,0

,1

0

0',

0

IDEAL WAVEFORM

.,
ax

I

I

I

I

I

,
I

I

I

I

I

I

I

I

I

I

I

I

SAMPLING RATE 111111111111111111111111111111111111111111111111111111\1111111111111111.11111111,11111I11j11l1l11l11l11l1Ul1l111j111l1l1l11l11l1l1l11111111l1111

, ACTUAL WAVEFORM

RECOVERED BIT
STREAM CLOCK

270427-26

Figure 3.13A. Clock Recovery

SOLC Clock Recoyery

o

0: 0:

o

000

IDEAL WAVEFORM

,
ax SAMPLING RATE

I

I

I

I

I

I

I

I

I

I

I

I

I

,
I

I

I

I

1111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111

ACTUAL WAVEFORM

RECOVERED BIT
STREAM CLOCK

270427-27

Figure 3.138. Clock Recovery

8-38

infef

HARDWARE DESCRIPTION OF THE 83C152

dress as transmission takes place. This also needs to be
done when using CSMA/CD with a 16-bit CRC for the
same reason.

multi-cast address. The user software can enable the
interrupt for RDN to determine when a frame is completed.
In DMA mode the interrupts are generated by the internal "transmit/receive done" (TDN,RDN) conditions. When the CPU responds to TDN or RDN,
checks are performed to see if the transmit underrun
error has occurred. The underrun condition is only
checked when using the DMA channels.

3.6.2 CPU/DMA CONTROL OF THE GSC

The data for transmission or reception can be 'handled
by either the CPU (TSTAT.O = 0) or DMA controller
(TSTAT.O = I). This allows the user two sets of flags
to control the FIFO. Associated with these flags are
interrupts, which may be enabled by the user software.
Either one or both sets of flags may be used at the same
time.

Upon power up the CPU mode is initialized. General
DMA control is covered in Section 4.0. DMA control
of the GSC is covered in Section 3.5.4. IfDMA is to be
used for serving the GSC, it must be configured into the
serial channel demand mode and the DMA bit in
TSTAT has to be set.

In CPU control mode the flags (RFNE,TFNF) are generated by the condition of the receive or transmit FIFO's. After loading a byte into the transmit FIFO,
there is a one machine cycle latency until the TFNF
flag is updated. Because of this latency, the status of
TFNF should not be checked immediately following
the instruction to load the transmit FIFO. If using the
interrupts to service the transmit FIFO,the one machine cycle of latency must be considered if the TFNF
flag is checked prior to leaving the subroutine.

3.6.3 COLLISIONS AND BACK OFF

The actions that are taken by the GSC if a collision
occurs while transmitting depend on where the collision occurs. If a collision occurs in CSMA/CD mode
following the preamble and BOF flag, the TCDT flag is
set and the transmit hardware completes a jam. Whcn
this type of collision occurs, there will be no automatic
retry at transmission. After the jam, control is returncd
to the CPU and user software must then initiate whatever actions are necessary for a proper recovery. The
possibility that data might have been loaded into or
from the GSC deserves special consideration. If these
fragments of a message have been passed on to other
devices, user software may have to perform some extensive error handling or notification. Before starting a
new message, the transmit and receive FIFOs will need
to be cleared. IfDMA servicing is being used the pointers must also be reinitialized. It should be noted that a
collision should never occur after the BOF flag in a well
designed system, since the system slot time will likely
be . less than the preamble length. The occurrence of
such a situation is normally due to a station on the link
that is not adhering to proper CSMA/CD protocol or
is not using the same timings as the rest of the network.

When using the CPU for control, transmission normally is initiated by setting the TEN bit (TSTAT.l) and
then writing to TFIFO. TEN must be set before loading the transmit FIFO, as setting TEN "clears the transmit FIFO. TCDCNT should also be checked by user
software and cleared if a collision occurred on a prior
transmission.
To enable the receiver, GREN (RSTAT.l) is set. After
GREN is set, the GSC begins to look for a valid BOF.
After detecting a valid BOF the GSC attempts to
match the received address byte(s) against the address
match registers. When a match occurs the frame is
loaded into the GSC. Due to the CRC strip hardware,
there is a 40 or 24 bit time delay following the BOF
until the first data byte is loaded into RFIFO if the 32
or 16 bit CRC is chosen. If the end of frame is detected
before data is loaded into the receive FIFO, the receiver
ignores that frame.
If the receiver detects a collision during reception in

CSMA/CD mode and if any bytes have been loaded
into the receive FIFO, the RCABT flag is set. The GSC
hardware then halts reception and resets GREN. The
user software needs to filter any collision fragment data
which may have been received. If the collision occurred
, prior to the data being loaded into RFIFO the CPU is
not notified and the receiver is left enabled. At the end
of a reception the RDN bit is set and GREN is cleared.
In HABEN mode this causes an acknowledgement to
be transmitted if the frame did not have a broadcast or

A collision occurring during the preamble or BOF flag
is the nonnal type of collision that is expected. When
this type of collision occurs the GSC automatically
handles the retransmission attempts for as many as
eight tries. If on the eighth attempt a collision occurs,
the transmitter is disabled, although the jam and backoff are performed. If enabled, the CPU is then interrupted. The user software should then determine what
, action to take. The possibilities range from just reporting the error and aborting' transmission to reinitializing
the serial channel registers and attempt retransmission.

8-39

inter

HARDWARE DESCRIPTION OF THE 83C152

If less than eight attempts are desired TCDCNT can be
loaded with some value which will reduce the number
of collisions possible before TCDCNT overflows. The
value loaded should consist of all 1s as the least significant bits, e.g. 7, OFH, 3FH. A solid block of Is is suggested because TCDCNT is used as a mask when generating the random slot number assignment. The
TCDCNT register operates by shifting the contents one
bit position to the left as each collision is detected. As
each shift occurs a 1 is loaded into the LSB. When
tCDCNT overflows, GSC operation stops and the
CPU is notified by the setting of the TCDT bit which
can flag an interrupt.

The amount of time that the GSC has before it must be
ready to retransmit after a collision is determined by
the mode which is selected. The mode is determined
MO (GMOD.5) and Ml (GMOD.6). If MO and Ml
equal 0,0 (normal backoff) then the minimum period
before retransmission will be either the interframe
space or the backoff period, whichever is longer. If MO
and Ml equal 1,1 (alternate backoff) then the minimum
period before retransmission will be the interframe
space plus the backoff period. Both of these are shown
in Figure 3.4. Alternate backoff must be enabled if using deterministic resolution. If the GSC is not ready to
retransmit by the time its assigned slot becomes available, the slot time is lost and the station must wait until
the collision resolution time period has' passed.
Instead of waiting for the collision resolution to pass,
the transmission could be aborted. The decision to
abort is usually dependent on the number of stations on
the link and how many collisions have already occurred. The number of collisions can be obtained by
examining the register, TCDCNT. The abort is normally implemented by clearing TEN. The new transmission begins by setting TEN and loading TFIFO. The
minimum amount of time available to initiate a retransmission would be one interframe space period after the
line is sensed as being idle.

As the nUfiibef of stations approach 256 the probability
of a successful transmission decreases rapidly. If there
are more than 256 stations involved in the collision
there would be nb resolution since at least two of the
stations will always have the same backoff interval selected.

All the stations monitor the link as long as that station
is active, even if not attempting to transmit. This is to
ensure that each station always defers the minimum
amount oftime before attempting a transmission and so
that addresses are recognized. However, the collision
detect circuitry operates slightly differently.
In normal back-off mode, a transmitting station always
monitors the link while transmitting. If a collision is
detected one or more of the transmitting stations apply
the jam signal and all transmitting stations enter the
back-off algorithm. The receiving stations also cop.stantly monitor for a collision but do not take part in
the resolution phase. This allows a station to try to
transmit in the middle of a resolution period. This in
turn mayor may not cause another collision. If the new
station trying to transmit on the link does so during an
unused slot time then there will probably not be a collision. If trying to transmit during a used slot time, then
there will probably be a collision. The actions the receiver does take when detecting a collision is to just
stop receiving data if data has 110t been loaded into
RFIFO or to stop reception, clear receiver enable
(REN) and set the receiver abort flag (RCABT RSTAT.6).
If deterministic resolution is used, the transmitting stations go through pretty much the same process as in
normal back-off, except that the slots are predetermined. All the receivers go through the back-off algo.rithm and may only transmit during their assigned slot.
3.6.4 SUCCESSFUL ENDING OF
TRANSMISSIONS AND RECEPTIONS

In both CSMA/CD and SDLC modes, the TDN bit is
set and TEN cleared at the end of a successful transmission. The end of the transmission occurs when the
TFIFO is empty and the last byte has been transmitted.
In CSMAlCD the user should clear the TCDCNT register after successful transmission.
At the end of a successfui reception, me RDN bit is set
. and GREN is cleared. The end of reception occurs
when the EOF flag is detected by the GSC hardware.

8-40

inter

HARDWARE DESCRIPTION OF THE 83C152

The length includes the two bit Begin Of Frame (BOP) .
flag in CSMA/CD but does not include the SDLC flag.
In SDLC mode, the BOF is an SDLC flag, otherwise it
is two consecutive ones. Zero length is not compatible
in CSMA/CD mode. The user software is responsible
for setting or clearing these bits.

3.7 Register Descriptions
ADRO,I,2,3 (95H, OA5H, OB5H, OC5H) - Address
Match Registers 0,1,2,3 - Contains the address match
values which determines which data will be accepted as
valid. In 8 bit addressing mode, a match with any of the
four registers will trigger acceptance. In 16 bit addressing mode a match with ADR1:ADRO or ADR3:ADR2
will be accepted. Addressing mode is determined in
GMOD (AL).

GMOD.3 (CT) - CRC Type - If set, 32 bit AUTODINlI-32 is used. If cleared, 16 bit CRC-CCITT is used.
The user software is responsible for setting or clearing
this flag.

AMSKO,1 (OD5H, OE5H) - Address Match Mask 0,1 Identifies which bits in ADRO,1 are "don't care" bits.
Writing a one to a bit in AMSKO,1 masks out that
corresponding bit in ADDRO,l.

GMOD.4 (AL) - Address Length - If set, 16 bit addressing is used. If cleared, 8 bit addressing is used. In 8
bit mode a match with any of the 4 address registers
will be accepted (ADRO, ADR1, ADR2, ADR3).
"Don't Care" bits may be masked in ADRO and ADRI
with AMSKO and AMSKI. In 16 bit mode, addresses
are matched against "ADR1:ADRO" or "ADR3:
ADR2". Again, "Don't Care" bits in ADR1:ADRO
can be masked in AMSK1:AMSKO. A received address
of all ones will always be recognized in any mode. The
user software is responsible for setting or clearing this
flag.

BAUD (94H) - GSC Baud Rate Generator - Contains
the value of the programmable baud rate. The data rate
will equal (frequency of the oscillator)/«BAUD + 1)
X (8)). Writing to BAUD actually stores the value in a
reload register. The reload register contents are copied
into the BAUD register when the Baud register decrements to OOH. Reading BAUD yields the current timer
value. A read during GSC operation will give a value
that may not be current because the timer could decrement between the time it is read by the CPU and by the
time the value is loaded into its destination.

GMOD.5,6 (MO,Ml) - Mode Select - Two test modes,
an optional "alternate backoff" mode, or normal backoff can be enabled with these two bits. The user software is responsible for setting or clearing the mode bits.

BKOFF (OC4H) - BackoffTimer - The backofftimer is
an eight bit count-down timer with a clock period equal
to one slot time. The backoff time is used in the
CSMA/CD collision resolution algorithm. The user
software may read the timer but the value may be invalid. as the timer is clocked asynchronously to the CPU.
Writing to OC4H will have no effect.

I

7
XTCLK

6

5

GMOD(84H)
4
3

o

2

I I MO I AL I CT I PL1
M1

Ml MO Mode
0
0 Normal
0
1 Raw Transmit
0 Raw Receive
1
1
1 Alternate Backoff

PLO

I PR I

Figure 3.14. GMOD

In raw receive mode, the receiver operates as normal
except that all the bytes following the BOF are loaded
into the receive FIFO, including the CRC. The transmitter operates as normal.

GMOD.O (PR) - Protocol- If set, SDLC protocols with
NRZI encoding and SDLC flags are used. If cleared,
CSMA/CD link access with Manchester encoding is
used. The user software is responsible for setting or
clearing this flag.

In raw transmit. mode the transmit output is internally
connected to the receiver input. The internal connection is not at the actual port pin, but inside the port
latch. All data transmitted is done without a preamble,
flag or zero bit insertion, and without appending a
CRC. The receiver operates as normal. Zero bit deletion is performed.

GMOD.I,2 (PLO,I) - Preamble length
PLl PLO LENGTH (BITS)
o 0
0
o
1
8
0
32
1
1
1
64

In alternate backoff mode the standard backoff process
is modified so the the backoff is delayed until the end of
the IFS. This should help to prevent collisions constantly happening because the IFS time is usually larger
than the slot time.

8-41

HARDWARE DESCRIPTION OF THE 83C152

GMOD.7 (XTCLK) - External Transmit Clock - If set
an external IX clock is used for the transmitter. If
cleared the internal baud rate generator provides the
transmit clock. The input clock is applied to P1.3
(T x C). The user software is responsible for setting or
clearing 'this flag. External receive clock is enabled by
setting PCON.3.

PCON(087H)
76543210

PCON contains bits for power control, LSC control,
DMA control, and GSC control. The bits used for the
GSC are PCON.2, PCON.3, and PCONA.

IFS (OA4H) - Interframe Spacing - Determines the
number of bit times separating transmitted frames in
CSMA/CD. A bit time is equal to I/baud rate. Only
even interframe space periods can be used. The number
written into this register is divided by two and loaded in
the most significant seven bits. Complete interframe
space is obtained by counting this seven bit number
down to zero twice. A user software read of this register
will give a value where the seven most significant bits
gives the current count value and the least significant
bit shows a one for the first count-down and a zero for
the second count. The value read may not be valid 'as
the timer is clocked in' periods not necessarily associated with the CPU read of IFS. Loading this register with
zero results in 256 bit times.

PCON.2 (GFIEN) - GSC Flag Idle Enable - Setting
GFIEN to a I caused idle flags to be generated between
transmitted frames in SDLC mode. SDLC idle flags
consist of 01111110 flags creating the sequence
01111110011111110 ...... 01l'1111 10. A possible side
effect of enabling GFIEN is that the maximum possible
latency from writing to TFIFO until the first bit is
transmitted increased from approximately 2 bit-times
to around 8 bit-times. GFIEN has no effect with
CSMA/CD.
PCON.3 (XRCLK) - GSC External Receive Clock Enable - Writing a I to XRCLK ,enables an external clock
to be applied to pin 5 (Port IA). The external clock is
used to determine when bits are loaded into the receiver.
PCONA (GAREN) - GSC Auxiliary Receiver Enable
Bit - This bit needs to be set to a 1 to enable the recep-

MYSLOT.O, I, 2, 3, 4, 5 -Slot Address - The six address bits choose 1 of 64 slot addresses. Address 63 has
the highest priority and address 1 has the lowest. A
value of zero will prevent a station froni transmitting
during the collision resolution period by waiting until
all the possible slot times have elapsed. The user software normally initializes this address in the operating
software.

tion of back-to~back SDLC frames. A back-to-back
SDLC frame is when the EOF and BOF is shared between two sequential frames intended for the same station on the link. If GAREN contains a 0 then the receiver will be disabled upon reception of the EOF and
by the time user software' re-enables the receiver the
first bit(s) may have already passed, in the case of backto-back frames. Setting GAREN to a 1, prevents the
receiver from being disabled by the EOF but GREN
will be cleared and can be checked by user software to
determine that an EOF has been received. GAREN has
no effect if the GSC is in CSMA/CDmode.

MYSLOT.6 (DCR) - Deterministic Collision Resolution A hJOrithm - When set. the alternate collision resoiuti~~-;;}gorithm is selected. Retriggering of the IFS on
reappearance of the carrier is also disabled. When using
this feature Alternate Backoff Mode must be selected
and several other registers must be initialized. User
. software must initialize TCDCNT with the maximum
number of slots that are most appropriate for a particular application. The PRBS register must be set to all
ones. This disables the PRBS by freezing it's contents at
OFFH. The backoff timer is used to count down the
number of slots based on the slot timer value setting the
period of one slot. The user software is responsible for
setting or clearing this flag.

PRBS (OE4H) - Pseudo-Random Binary Sequence This register contains apselldo-random number to be
used in the CSMA/CD backoff algorithm. The number
is generated by using a' feedback shift register clocked
by the CPU phase clocks. Writing all ones to the PRBS
will freeze the value at all ones. Writing any other value
to it will restart the PRBS generator. The PRBS is initialized to all zero's during RESET. A read of location
OE4H will not necessarily give the seed, used. in ,the
backoff algorithm because the PRBS counters are
clocked by internal CPU phase clocks. This means the
contents of the PRBS may have been altered between
the time when the seed was generated and before a
READ has been internally executed.

Figure 3.15. MYSLOT

MYSLOT.7 (DCJ) - D.C. Jam - When set selects D.C.
type jam, when clear, selects A.C. type jam. The user
software is responsible for setting or clearing this flag.

8-42

HARDWARE DESCRIPTION OF THE 83C152

RFIFO (OF4H) - Receive FIFO - RFIFO is a 3 byte
buffer that is loaded each time the GSC receiver has a
byte of data. Associated with RFIFO is a pointer that is
automatically updated with each read of the FIFO. A
read of RFIFO fetches the oldest data in the FIFO.

had been loaded into the receive FIFO in CSMA/CD
mode. In SDLC mode, RCABT indicates that 7 consecutive ones were detected prior to the end flag but after
data has been loaded into the receive FIFO. The status
of this flag is controlled by the GSC.

RSTAT (OESH) - Receive Status Register
76543210

IORIRCABTIAElcRCEIRDNIRFNEIGRENIHABENI
Figure 3.16. RSTAT

RSTAT.7 (OVR) - Overrun - If set, indicates that the
receive FIFO was full and new shift register data was
written into it. The setting of this flag is controlled by
the GSC and it is cleared by user software.
SLOTTM (OBH) - Slot Time - Determines the length of
the slot time used in CSMAlCD. A slot time equals
(256 - SLOTTM) X (I / baud rate). A read of
SLOTTM will give the value of the slot time timer but
the value may be invalid as the timer is clocked asynchronously to the CPU. Loading SLOTTM with 0 results in 256 bit times.

RSTAT.O (HABEN) - Hardware Based Acknowledge
Enable - If set, enables the hardware based acknowledge feature. The user software is responsible for setting
or clearing this flag.
RSTAT.I (GREN) - Receiver Enable - When set, the
receiver is enabled to accept incoming frames. This also
clears RDN, CRCE, AE, RCABT, and the receive
FIFO. It is cleared by the receiver at the end of a reception or if any errors occurred. The user software is responsible for setting this flag and the GSC or user software can clear it. The status of GREN has no effect on
whether the receiver detects a collision in CSMAlCD
mode as the receiver input circuitry always monitors
the receive pin.

TCDCNT (OD4H) - Transmit Collision Detect Count Contains the number of collisions that have occurred if
probabilistic CSMAlCD is used. The user software
must clear this register before transmitting a new frame
so that the GSC backoff hardware can accurately distinguish a new frame from a retransmit attempt.
In deterministic backoff mode, TCDCNT is used to
hold the maximum number of slots.

RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set,
indicates that the receive FIFO contains data. The receive FIFO is a three byte buffer into which the receive
data is loaded. A CPU read of the FIFO retrieves the
oldest data and automatically updates the FIFO pointers. Setting GREN to a one will clear the receive FIFO.
The status of this flag is controlled by the GSC. It is
cleared if user empties receive FIFO.

TFIFO (S5H) - GSC Transmit FIFO - TFIFO is a 3
byte buffer with an associated pointer that is automatically updated for each write by user software. Writing a
byte to TFIFO loads the data into the next available
location in the transmit FIFO. Setting TEN clears the
transmit FIFO so the transmit FIFO should not be
written to prior to setting TEN. If TEN is already set
transmission begins as soon as data is written to TFIFO.

RSTAT.3 (RDN) - Receive Done - If set, indicates the
successful completion of a receiver operation. Will not
be set if a CRC, alignment, abort, or FIFO overrun
error occurred. The status of this flag is controlled by
the GSC.

TSTAT (ODS) - Transmit Status Register
76543210

LNI I NOACK I UR I TCDT I TDN I TFNF I TEN I DMA I
Figure 3.17. TSTAT

RSTAT.4 (CRCE) - CRC Error - If set, indicates that a
properly aligned frame was received with a mismatched
CRC. The status of this flag is controlled by the GSC.

TSTAT.O (DMA) - DMA Select - If set, indicates that
DMA channels are used to service the GSC FIFO's and
GSC interrupts occur on TDN and RDN, and also enables UR to become set. If cleared, indicates that the
GSC is operating in its normal mode and interrupts
occur on TFNF and RFNE. For more information On
DMA servicing please refer to the DMA section on
DMA serial demand mode (4.2.2.3). The user software
is responsible for setting or clearing this flag.

RSTAT.5 (AE) - Alignment Error - If set, indicates
that the line went idle when the receiver shift register
was not full and the resulting CRC was bad in the
CSMAlCD mode. If a correct CRC was valid. then AE
is not set. In SDLC mode, AE indicates that a nonbyte-aligned flag was received. The status of this flag is
controlled by the GSC.
RSTAT.6 (RCABT) - Receiver Collision/Abort Detect
- If set, indicates that a collision was detected after data

8-43

HARDWARE DESCRIPTION, OF THE 83C152

TSTAT.l (TEN) - Transmit Enable - When set causes
TDN,UR, TCDT, and NOACK flag to be ,reset and
the TFIFO cleared. The transmitter will clear TEN after a successful transmission, a collision during the
data, CRC, or end flag. The user software is responsible
for setting but the GSC or user software may clear this
flag. If cleared during a transmission the GSC transmit
pin goes to a steady state high level. .This is the method
used to send an abort character in SDLC., Also DEN is'
forced to a high level. The end of transmission occurs
whenever the TFIFO is emptied.

3.8 Serial Backplane VS. Network
Environment
The C152 GSC port is intended to fulfill the needs of
both serial backplane environment and the serial communication network environment. The serial backplane
is where typically, only processor to processor communications take place within a self contained box. The
communication usually only encompasses those items
which are necessary to accomplish the dedicated task
for the box. In these types of applications there may not
be a need for line drivers as the distance between the
transmitter and receiver is relatively short. The network environment; however, usually requires transmission of data over large distances and requires drivers
and/or repeaters to ensure the data is received on both
ends.

TSTAT.2 (TFNF) - Transmit FIFO not full - When
set, indicates that new data may be written into the
transmit FIFO. The transmit FIFO is a three byte buffer that loads the transmit shift register with data. The
status of this flag is controlled by the GSC.
TSTAT.3 (TDN) - Transmit Done - When set, indicates the successfu1.completion ofa frame transmission:
If HABEN is set, TDN will not be set until ,the end of
the IFS following the, transmitted message, so that the
acknowledge can be checked. If an acknowledge is expected and not received, TDN'is not set. An acknowledge is not expected following a broadcast or multi-cast
packet. The status of this flag is controlled by the GSC.

4.0 DMA Operation
The C152 contains DMA (Direct Memory Accessing)
logic to peiform high speed data tran'sfers between any
two of
Internal Data RAM
Internal SFRs
External Data RAM

TSTAT.4 (TCDT) - Transmit Collision Detect - If set,
indicates that the transmitter halted due to a collision.
It is set if a collision occurs during the data or CRC or
ifthere are more than eight collisions. The status of this
flag is ~ontrolled by the GSC.

If external ,RAM is involved, the Port 2 and Port 0 ~

are used as the address/data bus, and RD and WR
'
signals are generated as required.

TSTAT.5 (UR) - Underrun - If set, indicates that in
DMA mode the last bit was shifted out of the transmit
register and that the DMA byte count did not equal
zero. When an underrun occurs, the transmitter, halts
without sending the CRC or the end flag. The status of
this flag is controlled by the GSC.

Hardware is also implemented to generate a Hold Request signal and await a Hold Acknowledge response
before commencing a DMA that involves external
RAM.
Alternatively, the Hold/Hold Acknowledge hardware
can be programmed to 'accept a Hold Request signal
from an external device and generate a Hold Acknowledge signal in response, to indicate to the requesting
device that the C152 will not commence a DMA to or
from external RAM while the Hold Request is active. ,

TSTAT.6 (NOACK) - No Acknowledge - If set, indicates that no acknowledge was received fodhe previous
frame. Will be set only if HABEN is set and no acknowledge is received prior to the end of the IFS.
NOACK is not set following a broadcast or a multicast packet. The status of this flag is controlled by the
GSC.
'

4.1 DMA with the 80C152

TSTAT. 7 (LNI) - Line tdle - If set, indicates' the receive line is idle. In SDLC protocol it is set if 15 consecutive 'ones are' received. In CSMA/CD protocol, line
idle is set if no transitio~s occ~r on GR X D for approximately 1.6 bit times after a r~uired transition. LNI is
cleared after a transition on GRXD.The status of this
flag is controlledby the GSC.

The C152 contains two identical general purPose 8-bit
DMA channels with 16-bit addressability: DMAO and
be executed by either chanDMAI. DMA transfers
nel independent of the other, but only by one channel at
a time. During the time that a DMA transfer is being
executed, program execution is suspended. A DMA
transfer takes one machine cycle (12 oscillator

can

8-44

intJ

HARDWARE DESCRIPTION OF THE 83C152

DMA CHANNEL 0
DARHO

I I

DARlO

DMA CHANNEL 1

I,

DESTINATION ADDRESS

.I

SARHO

II

SARLO

SOURCE ADDRESS
BCRHO

II

BCRlO

.I

DARH1

I. .I

SARH1

DCONO

DARL1

I,

BCRH1

I I

SARL1

I.
I,

SOURCE ADDRESS

BYTE COUNT

I

II

DESTINATION ADDRESS

II

BCRL1

BYTE COUNT

I

I

DCON1

I.

I

DMA 1 CONTROL

DMAO CONTROL
PCON
'-'

"-- Two new bits In PCON control
Hold/Hold Acknowledge logic

270427-28

Figure 4.1. DMA Registers

periods) per byte transferred, except when the destination and source are both in External Data RAM. In
that case the transfer takes two 'machine cycles per
byte. The term DMA Cycle will be used to mean the
transfer of a single data byte, whether it takes 1 or 2
machine cycles.

Two other bits in DCONn specify the physical source
of the data to be transferred. These are SAS (Source
Address Space) and ISA (Increment Source Address).
If SAS = 0, the source is in data memory extern;i1 to
the CIS2. If SAS = 1, the source is internal. If SAS =
1 and ISA = 0, the internal source is an SFR. If SAS
= 1 and ISA = 1, the internal source is in the 256-byte
data RAM.

Associated with each channel are seven SFRs, shown in
Figure 4.1. SARLn and SARHn holds the low and high
bytes of the' source address. Taken together they form a
16-bit Source Address Register. DARLn and DARHn
hold the low and high bytes of the destination address,
and together form the Destination Address Register.
BCRLn and BCRHn hold the low and high bytes of the
number of bytes to be transferred, and together form
the Byte Count Register. DCONn contains control and
flag bits.

In any case, if ISA = 1, the source address is automatically incremented after each byte transfer. If ISA = 0,
it is not.
The functions of these four control bits are summarized
below:
DAS

IDA

°° °1
1
1

Two bits in DCONn are used to specify the physical
destination of the data transfer. These bits are DAS
(Destination Address Space) and IDA (Increment Destination Address). If DAS = 0, the destination is in
data memory external to the C152. If DAS = 1, the
destination is internal to the CIS2. If DAS·= 1 and
IDA = 0, the internal destination is a Special Function
Register (SFR). If DAS = 1 and IDA = 1, the internal destination is in the 256-byte data RAM.

0

1

8-45

Auto-Increment

External RAM
External RAM
SFR
Internal RAM

no
yes
no
yes

ISA

Source

Auto-Increment

0
0

°1

1
1

0

External RAM
External RAM
SFR
Internal RAM

no
yes
no
yes

SAS

In any case, if IDA = 1, the destination address is
automatically incremented after each byte transfer. If
IDA = 0, it is not.

Destination

1

HARDWARE DESCRIPTION OF THE 83C152

dress. On-chip hardware then clears the flag (RI, TI,
RFNE, or TFNF) that initiated the DMA, and decrements BCRn. Note that since the flag that initiated the
DMA is cleared, it will not generate an interrupt unless
DMA servicing is held off or the byte count equals O.
DMA servicing may be held off when alternate cycle is
being used or by the status of the HOLD/HLDA logic.
In these situations the interrupt for the LSC may occur
before the DMA can clear the RI or TI flag. This is
because the LSC is serviced according to the status of
RI and TI, whether or not the DMA channels are being
used for the transferring of data. The GSC does not use
RFNE or TFNF flags when using the DMA channels
so these do not need to be disabled. When using the
DMA channels to service the LSC it is recommended
that the interrupts (RI and TI) be disabled. If the decremented BCRn is OOOOH, on-chip hardware then
clears the GO bit and sets the DONE bit. The DONE
bit flags an interrupt.

There are four modes in which the DMA channel can
operate. These are selected by the bits DM and TM
(Demand Mode and Transfer Mode) in DCONn:

OM

TM

Operating Mode

0
0

0

1
1

0

Alternate Cycles Mode
Burst Mode
Serial Port Demand Mode
External Demand Mode

1
1

The operating modes are described below.
4.1.1 ALTERNATE CYCLE MODE
In Alternate Cycles Mode the DMA is initiated by setting the GO bit in DCONn. Following the instrnction
that set the GO bit, one more instruction is executed,
and then the first data byte is transferred from the
source address to the destination address. Then another
instruction is executed, and then another byte of data is
transferred, and so on in this manner.

4.1.4 EXTERNAL DEMAND MODE
In External Demand Mode the DMA is initiated by
one of the External Interrupt pins, provided the GO bit
is set. INTO initiates a Channel 0 DMA, and INTI
initiates a Channel 1 DMA.

Each time a data byte is transferred, ,BCRn (Byte
Count Register for DMA Channel n) is decremented.
When it reaches OOOOH, on-chip hardware clears the
GO bit and sets the DONE bit, and the DMA ceases.
The DONE bit flags an interrupt.

If the external interrupt is configured to be transitionactivated, then each I-to-O transition at the interrupt
pin sets the corresponding external interrupt flag, and
generates one DMA Cycle. Then, BCRn is decremented. No more DMA Cycles take place until another
I-to-O transition is seen at the external interrupt pin. If
the decremented BCRn = OOOOH, on-chip hardware
clears the GO bit and sets the DONE bit. If the external interrupt is enabled, it will be serviced.

4.1.2 BURST MODE
Burst Mode differs from Alternate Cycles mode only in
that once the data transfer has begun, program execution is entirely suspended until BCRn reaches OOOOH,
indicating that all data bytes that were to be transferred
have been transferred. The interrupt control hardware
remains active during the DMA, so interrupt flags may
get set, but since program execution is suspended, the
interrupts will not be serviced while the DMA is in
progress.

If the external interrupt is configured to be level-activated, then DMA Cycles commence when the interrupt
pin is pulled low, and continue for as long as the pin is
held low and BCRn is not OOOOH. If BCRn reaches 0
while the interrupt pin is still low, the GO bit is cleared,
the DONE bit is set, and the DMA ceases. If the external interrupt is enabled, it will be serviced.

4.i.3 SERiAL FORi DEiviAND MOCE
In this mode-the DMA can be used to service the Local
Serial Channel (LSC) or the Global Serial Channel
(GSC).
-

If the interrupt pin is pulled up before BCRn reaches
OOOOH, then the DMA ceases, but the GO bit is still 1
and the DONE bit is still O. An external interrupt is not
generated in this case, since in level-activated mode,
pulling the pin to a logical 1 clears the interrupt flag. If
the interrupt pin is then pulled low again, DMA transfers will continue from where they were previously
stopped.

In Serial Port Demand Mode the DMA is initiated by
any of the following conditiollS, if the GO bit is set:
Source Address = SBUF
.AND. AI = 1
Destination Address = SBUF .AND. TI = 1
Source Address = AFIFO
.AND. AFNE = 1
Destination Address = TFIFO .AND. TFNF = 1

The timing for the DMA Cycle in the transition-activated mode, or for the first DMA Cycle in the level-activated mode is as follows: If the I-to-O transition is

Each time one of the above conditions is met, one
DMA Cycle is executed; that is, one data byte is transferred from the source address to the destination ad-

8-46

HARDWARE DESCRIPTION OF THE 83C152

detected before the final machine cycle of the instruction in progress, then the DMA commences as soon as
the instruction in progress is completed. Otherwise, one
more instruction will be executed before the DMA
starts. No instruction is executed during any DMA Cycle.

4.2 Timing Diagrams
Timing diagrams for single-byte DMA transfers are
shown.in Figures 4.2 through 4.5 for four kinds of
DMA Cycles: internal memory to internal memory, internal memory to external memory, external memory
to internal memory, and external memory to external
memory. In each case we assume the Cl52 is executing
out of external program memory. If the C152 is executing out of internal program memory, then PSEN is inactive, and the Port 0 and Port 2 pins emit PO and P2
SFR data. If External Data Memory is involved, the
Port 0 and Port 2 pins are used as the address/data bus,

1~- - - - - - 1 2 osc.

and RD and/or WR signals are generated as needed, in
the same manner as in the execution of a MOVX
@DPTR instruction.

4.3 Hold/Hold Acknowledge
Two operating modes of Hold/Hold Acknowledge logic are available, and either or neither may be invoked
by software. In one mode, the C152 generates a Hold
Request signal and awaits a Hold Acknowledge response before commencing' a DMA that involves external RAM. This is called the Requester Mode.
In the other mode, the C152 accepts a Hold Request
signal from an external device and generates a Hold
Acknowledge signal in response, to indicate to the requesting device that the C 152 will not commence a
DMA to or from external RAM while the Hold Request is active. This is called the Arbiter mode,

PERIODS

-----""11

--,f\.,__ __

ALE ~ _ _ _ _ _ _ _ _ _

""iN'ST1--- - - - - - - - -- - - - - -

___ _
PO ...,;;;;;;.,J __________________________________
FLOAT - - - - - - -- - - -- -"\iPcl'FLOA~INST
~

-JX

P2~~__________~p~2~sr_R________~__
_ _ _ _ _ _ _ DMA
-

CYCLE------~I. _

PCH

RESUME PROGRAM
EXECUTION

270427-29

Figure 4.2. DMA Transfer from Internal Memory to Internal Memory

- - - - - - 1 2 osc. PERIODS------li

1+1

-'f\.'_.___

ALE~_ _ _ _ _ _ _ _ _

PO

INST

::1.<

DARLn

X

'-DMA DATA OUT

P2~~____________~DA~R~Hn~____________JX~
WR

__~PC~H~

___

\1..._ _ _ _- - J1 ,
- - - - - - - D M A C Y C L E - - - - - - - . ! - RESUME PROGRAM
EXECUTION

Figure 4.3. DMA Transfer from Internal Memory to External Memory

8-47.

270427-30

HARDWARE DESCRIPTION OF THE 83C152

~I'-----12

ALE

osc. PERIOOS ------+j'1

----f\'--________~r_\......_ __

I'WlJ
P2

'---

~...._ _ _ _ _ _ _S_AR_H_n_ _ _ _ _ _

\'-----~/

- - I . - - - - - - O M A CYCLE _ _ _ _ _ _ _ 1
,, -

_'X

PCH

RESUME PROGRAM
EXECUTION

270427-31

Figure 4.4. DMA Transfer from External Memory to Internal Melflory

,------12

osc.

PERIODS

----+f"'~---12

osc.

PERIODS - - - - 1

ALE

'P2~~_ _ _ _~SA...R...
Hn~_ _ _ _Jx~

_____..... .

~ R...
Hn~_ ___JX~

__...Pc...H___

\ ....------1/
\ .....-----...1/
f-I,----------OMA CyCLE------------I-

RES~~E~~~g~RAM
270427-32

Figure 4.5. DMA Transfer from External Memory to External Memory
4.3.1 REQUESTER MODE

4.3.2 ARBITER MODE

The Requester Mode is selected by setting the control
bit REQ, which resides in PCON. In that mode, when
the C152 wants to do a DMA to External Daia Memory, it first generates a Hold Request signal, HLD, and
waits for a Hold Acknowledge signal, HLDA, before
. commencing the DMA operation. Note that program
execution continues while HLDA is awaited. The
DMA is not begun until a logical 0 is detected at the
HLDA pin. Then, once the DMA has begun, it goes to
completion regardless of the logic level at HLDA.
The protocol is activated only for DMAs (not for program fetches or MOVX operations), and only for
DMAs to or from External Data Memory. If the data
destination and source are both internal to the C152,
the HLD/HLDA protocol is not used.
The HLD output is an alternate function of port pin
P1.5, and the HLDA input is an alternate function of
port pin 1>1.6.
,8-48

For DMAs that are to be driven by some device other
than the C152, a different version of the Hold/Hold
Acknow"lcdgc protocol is available. In this version the
device which is to drive the DMA sends a Hold Request signal, HLD, to the C152. If the C152 is currently performing a DMA to or from External Data Memory, it will complete this DMA before responding to the
Hold Request. When the C152 responds to the Hold
Request, it 'does so by activating a Hold Acknowledge
signal, HLDA. This indicates that the C152 will not
commence a new DMA to or from External Data
Memory while HLD remains active.
j

Note that in the Arbiter Mode the C152 does not suspend program execution at all, even if it is executing
from external program memory. It does not surrender
use of its own bus.
The Hold Request input, HLD, is at P1.5. The Hold
Acknowledge output, HLDA, is at P1.6. This

inter

HARDWARE DESCRIPTION OF THE 83C152

version of the Hold/Hold Acknowledge feature is selected by setting the.control bit ARB in PCON.
The functions of the ARB and REQ bits in PCON,
then, are
ARB

REQ

Hold/Hold Acknowledge Logic

0
0
1
1

0
1
0
1

Disabled
C152 generates HLD, detects HLDA
C152 detects HLD, generates HLDA
Invalid

ALE (ARB)

IF

270427-34

Figure 4.7. ALE Switch Select

The ALE Switch logic can be implemented by a single
74HCOO, as shown in Figure 4.7.

The HOLD/HOLDA logic only affects DMA operation with external RAM and doesn't affect other operations with external RAM, such as MOVX instruction.

Figure 4.8 shows the additional gating that is required
when one of the CPUs is executing from external
ROM. In this case the CPU has constant access to its
own local bus, and accesses the global RAM only after
gaining access to a global address/data bus.

Figure 4.6 shows a system in which two 83C152s are
sharing a global RAM. In this system, both CPUs are
executing from internal ROM. Neither CPU uses the
bus except to access the shared RAM, and such accesses are done only through DMA operations, not by
MOVX instructions.

If the CPU is programmed to be a Requester, as shown
in Figure 4.8, then when it wants to access the global
RAM it first activates HLD, and continues program
execution on its own local bus while awaiting an active
level at HLDA.

One CPU is programmed to be the Arbiter and the
other, to be the Requester. The ALE Switch selects
which CPU's ALE signal will be directed to the address
latch.
Arbiter's ALE is selected if HLDA is high,
and the Requester's ALE is selected if HLDA is low .

An active level at HLDA enables the local bus to the
global bus, and signals the !!:9uester to proceed with
its DMA. The Requester's RD signal, rather than its

The

.. Vee
A l8Xl0kll
PO
83C152
P2
ARB

Viii

.-7

ALE I - -

U

r- RD
HLD

HLD

r-v

HLDA

~

HLDA

•
§I3

7
3

~

ALE
SWITCH

ALE

83C152
REa

I'- Viii

PO

RD

P2

~

=0

ALE
(REO) -----...--J

4.3.3 USING THE HOLD/HOLD ACKNOWLEDGE

..-

ilLiiii =1

ALE (REO)

IF IlIJlA

l-

.P

DATA

,
OE
WE

LOW

HIGH

'------'
SHARED
RAM

ADDR

270427-33

Figure 4.6. Two 83C152s Sharing External RAM

8-49

intJ

HARDWARE DESCRIPTION OF THE 83C152

LOCAL BUS
ROM
PO \ r - - - ; - - ,
BOC152
REQ
P2

ViR

PSEN

rrn

ALE

HLD

SHARED BUS"

HLDA

, ).-

...

\

\

,
,

\

LOW

,

,

ADDR~

:

I

,

I

,
,

HIGH

,

~-~--~

I

I

I

I
I
I
I

,,,
,
t-......-OE

,'

WE
\

...

,

I
~

T,

THLDA
SYSTEM ARBITER

270427-35

Figure 4.8. Separation of Local and Global Busses

8-50

inter

HARDWARE DESCRIPTION OF THE 83C152

WR signal, is used to control the direction of the transceiver. This is to ensure that the transceiver will not try
to drive the local bus before the DMA has actually
begun.

Figure 4.9 shows the three tasks to which the internal
bus of the CI52 can be dedicated. In this figure, Instruction Cycle means the complete execution of a single instruction, whether it takes 1,2 or 4 machine cycles. DMA Cycle means the transfer of a single data
byte from source to destination, whether it takes 1 or 2
machine cycles. (It takes 2 machine cycles.jf the destination and source are both external to the CI52.) Onchip arbitration logic determines which type of cycle is
executed, according to the. following rules.

RD from the Requester is ~cally ANDed with RD
from the Arbiter to activate OE to the RAM. WR from
the Requester can normally be hard-wired to WR from
the Arbiter to activate WE to the RAM.

4.4 DMA Arbitration

If the HLD/HLDA logic is disabled (ARB = 0, REQ
= 0):
• A write to any DMA address or control register is
always followed by an Instruction Cycle. If the next
instruction is a read or write to a DMA address or
control register, the DMA cycle is held off one more
instruction cycle.
• A DMAO Cycle is called for if GOO = 1 and any of
the following conditions are satisfied:
1. Channel 0 Burst Mode is selected;
2. Channel 0 is in SP Demand Mode. and a SP Demand flag is up (but see • *);

The DMA Arbitration described in this section is not
arbitration between two devices wanting to access a
shared RAM, but rather on-chip arbitration between
the two DMA channels on the C152.
The CI52 provides two DMA channels, either of which
may be called into operation at any time in response to
real time conditions in the application circuit. However, only one DMA channel can be serviced during a
single DMA cycle.
In the event that both DMA channels request service at
the same time, DMA Channel 0 takes precedence.

270427-36

Figure 4.9. Internal Bus Tasks

8-51

HARDWARE DESCRIPTION OF THE 83C152

IDA (Increment Destination Address) If IDA = 1, the
destination address' is automatically incremented after
each byte transfer. IfiDA =0, it is not..

3. Channel 0 is in External .Demand Mode and an
External Demand flag is up;
4. Channel 0 is ·in Alternate Cycles Mode and Channel 1 isn't, and the previous cycle was not a DMA
Cycle;
5. Channel 0 and Channell are both in Alternate
Cycles Mode, and the previous cycle was not a
DMA Cycle, and the previous DMA Cycle was
not a DMAO cycle.
'
• A DMAI Cycle is called for if GOI = 1 and no
condition for a DMAO Cycle is satisfied, and any of
the following conditions are satisfied:
1. Channel 1 Burst Mode is selected;
2~ Channel 1 is in SP Demand Mode and a SP Demand flag is up (but see "*);
3. Channel 1 is in External Dem~nd Mode and an
External Demand flag is up;
4. Channel 1 is in Alternate Cycles Mode and Channel 0 isn't, and the previous cyCle was not a DMA
Cycle;
5. Channel 1 and Channel 0 are both in Alternate
, Cycles Mode, and the previous cycle was not a
DMA Cycle, and the previous DMA Cycle was
not a DMAI cycle.
"If a DMA Cycle is not called for, then an Instruction Cycle is executed.
A Special Case: Because of internal timing conflicts,
a SP Demand Mode DMA Cycle in which the destination address is TFIFO will not be generated unless the previous cycle was an Instruction Cycle.

SAS specifies the Source Address Space. If SAS = 0,
the source is in External Data Memory. If SAS = 1
and ISA = 0, the source is an SFR. If SAS = 1 and
ISA = 1, the source is Internal Data RAM.
ISA (Increment Source Address) If ISA = 1, the
source address is automatically incremented after each
byte transfer. If ISA.= 0, it is not.
DM (Demand Mode) If DM = 1, the DMA Channel
operates in Demand Mode. .In Demand Mode the
DMA is initiated either by an external signal or by a
Serial Port flag, depending on the value of the TM bit.
If DM = 0, the DMA is requested by setting the GO
bit in software.
TM (Transfer'Mode) If DM = 1 then TM selects
whether a DMA is initiated by an external signal (TM
= I) or by a Serial Port flag (TM = 0). If DM = 0
then TM selects whether the data transfers are to be in
bursts (TM = 1) or in alte~ate cycles (TM = 0).
DONE indicates the completion of a DMA operation
and flags an interrupt. It is set to 1 by on-chip hardware
when BeRn = 0, and is cleared to 0 by on-chip hardware when the interrupt is vectored to. It can also be
set or cleared by software.

*.

GO is the enable bit for the DMA Channel itself. The
DMA Channel is inactive if GO = O.

Note that any time conditions are satisfied for a DMAO
Cycle, the DMAO Cycle will be executed, even if the
DMAI Channel is active. That is not to say a DMAI
Cycle will be interrupted once it has begun. However,
once a cycle has begun, be it,an'Instruction Cycle or a
DMA Cycle, it will be completed without interruption.

PCON I SMOD I ARB I REQ I GAREN I XRCLK I GFIEN I PDN IIDL I

ARB enables the DMA logic to detect HLD and generate HLDA. After it has activated HLDA, the CI52 will
not begin a new DMA to or from External Data Memory as long as HLD is seen to be active. This logic is
disabled when ARB = 0, and enabled when ARB = 1.

If the HLD/HLDA logic is not disabled (either ARB
= i or REQ = i), then the HoidiHoid Acknowiedge

REQ enables the DMA logic to generate HLD and detect HLDA before performing a DMA to or from External Data Memory. After it has activated HLD, the
C152 will not begin the DMA until HLDA is seen to be
active. This logic is disabled when REQ = 0, and enabled when REQ = 1.

protocol will also be observed, as previously described,
for DMAs to or from external RAM.

4.5 Summary of DMA Control Bits
DCONn I DAS I IDA I SAS liSA I OM I TM I DONE I GO I

5.0 GLOSSARY

DAS specifies the Destination Address Space. If DAS
= 0, the destination is in External Data Memory: If
DAS = 1 and IDA = 0, the destination is a Special
Function Register (SFR). If DAS = 1 and IDA = 1,
the destination is in Internal Data RAM.

ADRO,I,2,3 (95H, OA5H, OB5H, OC5H) - Address
Match Registers 0,1,2,3 - The contents of these SFRs
are compared against the address bits from the serial

8-52

inter

HARDWARE DESCRIPTION OF THE 83C152

data on the GSC. If the address matches the SFR, then
the ClS2 accepts that frame. If in 8 bit addressing
mode, a match with any of the four registers will trigger
acceptance. In 16 bit addressing mode, a match with
ADRl:ADRO or ADR3:ADR2 will be accepted. Address length is determined, by GMOD, (AL).

DCI - D.C. Jam, see MYSLOT.

AE - Alignment Error, see RSTAT.

The DCON registers control the operation of the DMA
channels by determining the source of data to be transferred, the destination of the data to be transfer, and the
various modes of operation.

DCONO/I (092H,093H)
76543210

AL - Address Length, see GMOD.
AMSKO,l (ODSH, OESH) - Address Match Mask 0,1 Identifies which bits in ADRO,l are "don't care" bits.
Setting a bit to 1 in AMSKO,l identifies the corresponding bit in ADDRO,1 as not to be examined when
comparing addresses.

DCON.O (GO) - Enables DMA Transfer - When set it
enables a DMA channel. If block mode is set then
DMA transfer starts as soon as possible under CPU
control. If demand mode is set then DMA transfer
starts when a demand is asserted and recognized.

BAUD - (94H) Contains the programmable value for
the baud rate generator for the GSC. The baud rate will
equal (fosc)/«BAUD+ 1) X 8).

DCON.l (DONE) - DMA Transfer is Complete When set the DMA transfer is complete. It is set when
BCR equals 0 and is automatically reset when the
DMA vectors to its interrupt routine. If DMA interrupt is disabled and the user software executes a jump
on the DONE bit, then the user software must also
reset the done bit. If DONE is not set, then the DMA
transfer is not complete.

BCRLO,l (OE2H, OF2H) - Byte Count Register Low
0,1 - Contains the lower byte of the byte count. Used
during DMA transfers to identify to the DMA chan.
nels when the transfer is complete.
BCRHO,l (OE3H, OF3H) - Byte Count Register High
0,1 - Contains the upper byte of the byte. count.

DCON.2 (TM) - Transfer Mode - When set, DMA
burst transfers are used if the DMA channel is configured in block mode or external interrupts are used to
initiate a transfer if in Demand Mode. When TM is
cleared, Alternate Cycle Transfers are used if DMA is
in the Block Mode, or Local Serial channel/GSC interrupts are used to initiate a transfer if in Demand Mode.

BKOFF (OC4H) - Backoff Timer - The backoff timer is
an eight bit count-down timer with a clock period equal
to one slot time. The backoff time is used in the
CSMA/CD collision resolution algorithm.
BOF - Beginning of Frame flag -. A term commonly
used when dealing with packetized data. Signifies the
beginning of a frame.

DCON.3 (DM) - DMA Channel Mode - When set,
Demand Mode is used and when cleared, Block Mode
is used.

CRC - Cyclic Redundancy Check - An error checking
routine that mathematically manipulates a value dependent on the incoming data. The purpose is to identify
when a frame has been received in error.

DCON.4 (ISA) - Increment Source Address - When
set, the source address registers are automatically incremented during each transfer. When cleared, the source
address registers are not incremented.

CRCE - CRC Error, see RSTAT.

DCON.S (SAS) - Source Address Space - When set, the
source of data for the DMA transfers is internal data
memory if autoincrement is also set. If autoincrement is
not set but SAS is, then the source for data will be one
of the Special Function Registers. When SAS is cleared,
the source for data is external data memory.

CSMA/CD - Stands for Carrier Sense, Multiple Access, with Collision Detection.
CT - CRC Type, see GMOD.
DARLO/l (OC2H, OD2H) - Destination Address Register Low 0/1 - Contains the lower byte of the destinations' address when performing DMA transfers.

DCON.6 (IDA) -' Increment Destination Address
Space - When set, destination address registers are incremented once after each byte is transferred. When
cleared, the destination address registers are not automatically incremented.

DARHO/I (OC3H, OD3H) - Destination Address Register Low 0/1 - Contains the upper byte of the destinations' address when performing DMA transfers.
DAS - Destination Address Space, see DCON.

8-53

inter

HARDWARE DESCRIPTION OF THE 83C152

DCON.7 (DAS) - Destination Address Space - When
set, destination of data to be transferred is internal data
memory if autoincrement mode is also set. If autoincrement is not set the destinationwill be one of the Special
Function Registers. When DAS is cleared then the destination is external data memory.

GMOD(84H)

7

4

3

210

The bits in this SFR, perform most of the configuration
on the type of data transfers to be used with the GSC.
Determines the mode, address length, preamble length,
protocol select, and enables the external clocking of the
transmit data.

DEN - An alternate function of one of the port I pins
(p1.2). Its purpose is to enable external drivers when
the GSC is transmitting data. This function is always
active when using the GSC and if P1.2 is programmed
to a 1.

GMOD.O (PR) - Protocol- If set, SDLC protocols with
NRZI encoding, zero bit insertion, and SDLC flags are
used. If cleared, CSMAlCD link access with Manchester encoding is used.

DM - DMA Mode, see DCONO.

GMOD.l,2 (pLO, 1) - Preamble length

DMA - Direct Memory Access mode, see TSTAT.

PLI PLO LENGTH (BITS)

DONE - DMA done bit, see DCONO.

000
o
1
8
1
0
32
1
1
64

DPH -Data Pointer High, an SFR that contains the
high order byte of a general purpose pointer called the
data pointer (DPTR).

The length includes the two bit Begin Of frame (BOF)
flag in CSMAlCD but does not include the SDLC flag.
In SDLC mode, the BOF is an SDLC flag, otherwise it
is two consecutive ones. Zero length is not compatible
in CSMAlCD mode.

DPL - Data Pointer Low, an SFR that contains the low
order bytc of the data pointer.
~

5

IXTCLK I M1 I MO I AL I CT I PL1 I PLO I PR I

DCR - Deterministic Resolution, see MYSLOT.

EDMAO
IENl.

6

Enable DMA Channel 0 interriJpt, see

GMOD.3 (CT) - CRC Type - If set, 32-bit AUTODIN11-32 is used. If cleared, 16-bit CRC-CCITT is used.

EDMAI - Enable DMA Channel 1 interrupt, see
IENl.

GMOD.4 (AL) - Address Length - If set, 16-bit addressing is used. If cleared, 8-bit addressing is used. In
8-bit mode, a match with any of the 4 address registers
will allow that frame to be accepted (ADRO, ADRl,
ADR2, ADR3). "Don't Care" bits may be masked in
ADRO and ADRI with AMSKO and AMSKl. In 16bit mode,
addresses
are
matched
against
"ADRl:ADRO" or "ADR3:ADR2". Again, "Don't
Care" bits in ADRl:ADRO can be masked in
AMSKi:AMSKO. A received address of an ones win
always be recognizCd in any mode.

EGSRE - Enable GSC Receive Error interrupt, see
IENl.
EGSRV - Enable GSC Receive Valid interrupt, see
IENl.
.
EGSTE - Enable GSC Transmit Error interrupt, see
IENl.
EGSTV - Enable GSC Transmit Valid internipt, see
IENl.

GMOD.5, 6 (MO,Ml) -Mode Select- Two test modes,
an optional "alternate backofl" mode, or normal backoff can be enabled with these two bits.

EOF - A general term used in serial communications.
EOF stands for End Of Frame and signifies when the
last bits of data are transmitted when using packetized
data.

Ml

MO
·0
o 1
1
0
1
1

o

ES - Enable LSC Service interrupt, see IE.
ETO - Enable Timer 0 interrupt, see IE.
ETl - Enable Timer 1 interrupt, see IE.

Mode
Normal
Raw Transmit
Raw Receive
Alternate Backoff

GMOD.7 (XTCLK) - External Transmit Clock - If set
an external IX clock is used for the transmitter. If
cleared the internal baud rate generator provides the

EXO - Enable External interrupt 0, see IE.
EXI - Enable External interrupt 1, see IE.
8-54

inter

HARDWARE DESCRIPTION OF THE 83C152

transmit clock. The input clock is applied to Pl.3
(TxC). The user software is responsible for setting or
clearing this flag. External receive clock is enabled by
setting PCON.3.

IE.2 (EXl) - Enables the external interrupt INTI on
P3.3.

GO - DMA Go bit, see DCONO.

IE.4 (ES) - Enables the Local Serial Channel interrupt.

GRxD - GSC Receive Data input, an alternate function
of one of the port I pins (P 1.0). This pin is used as the
receive input for the GSC. PLO must be programmed
to a 1 for this function to operate.

IE.7 (EA) - The global interrupt enable bit. This bit
must be set to a 1 for any other interrupt to be enabled.

GSC - Global Serial Channel - A high-level, multi-protocol, serial communication controller added to the
SOC5lBH core to accomplish high-speed transfers of
packetized serial data.
GTxD - GSC Transmit Data output, an alternate function of one of the port I pins (P 1.1). This pin is used as
the transmit output for the GSC. Pl.l must be programmed to a I for this function to operate.
HBAEN - Hardware Based Acknowledge Enable, see
RSTAT.
HLDA - Hold Acknowledge, an alternate function of
one of the port 1 pins (Pl.6). This pin is used to perform the "HOLD ACKNOWLEDGE" function for
DMA transfers. HLDA can be an input or an output,
depending on the configuration of the DMA channels.
PI.6 must be programmed to a 1 for this function to
operate.
HOLD - Hold, an alternate function of one of the port
1 pins (P1.5). This pin is used to perform the "HOLD"
function for DMA transfers. HOLD can be an input or
an output, depending on the configuration of the DMA
channels. Pl.5 must be programmed to a 1 for this
function to operate.
IDA - Increment Destination Address, see DCONO.

IB.3 (ETI) - Enables the Timer 1 interrupt.

IENl - (OCSH)
76

EA

I ES I ET1 I EX1 I ETO

3

2

1

0

Interrupt enable register for DMA and GSC interrupts.
A 1 in any bit position enables that interrupt.
IENI.O (EGSRV) - Enables the GSC valid receive interrupt.
IEN1.1 (EGSRE) - Enables the GSC receive error interrupt.
IENl.2 (EDMAO) - Enables the DMA done interrupt
for Channel O.
IEN1.3 (EGSTV) - Enables the GSC valid transmit interrupt.
IENl.4 (EDMAl) - Enables the DMA done interrupt
for Channel 1.
IEN1.5 (EGSTE) - Enables the GSC transmit error interrupt
IFS - (OA4H) Interframe Space, determines the number
of bit tiflles separating transmitted frames.

7

6
I

5

4

IP (OBSH)
3
2

PS I PT1 I PX1

1

0

PTO

PXO

0
EXO

Interrupt Enable SFR, used to individually enable the
Timer and Local Serial Channel interrupts. Also con~
tains the global enable bit which must be set to a 1 to
enable any interrupt to be automatically recoguized by
the CPU.
IE.O (EXO) - Enables the external interrupt INTO on
P3.2.
IE.l (ETO) - Enables the Timer 0 interrupt.

4

IIIEGSTEIEDMA11EGSTVIEDMAOIEGSREIEGSRVI

IE (OASH)
765432

5

Allows the user software two levels of prioritization to
be assigned to each of the interrupts in IE. A 1 assigns
the corresponding interrupt in IE a higher interrupt
than an interrupt with a corresponding O.
IP.O (PXO) - Assigns the priority of external interrupt,
INTO.
.
IP.1 (PTO) - Assigns the priority of Timer 0 interrupt,
TO.

inter

HARDWARE DESCRIPTION OF THE 83C152

Determines which type of Jam is used, which backoff
algorithm is used, and the DCR slot address for the
.
GSC.

IP.2 (PXI)- Assigns the priority of external interrupt,
INTl.
IP.3 (PTl) - Assigns the priority of Timer I interrupt,
Tl.

MYSLOT.O,I,2,3,4,5 (SAO,I,2,3,4,5) - These bits determine which slot address is assigned to the CI52 when
using deterministic backoff during CSMA/CD operations on the GSC. Maximum slots available is 63. An
address of OOH prevents that station from participating
in the backoff process.

IP.4 (PS) - Assigns the priority of the LSC interrupt,
SBUF.
IPNI - (OFSH)
76

I I I

5
PGSTE

I

4
PDMA1

3

2

1

0

I PGSTV I PDMAO I PGSRE I PGSRV I

MYSLOT.6 (DCR) - Determines which collision resolution algorithm is used. If set to a I, then the deterministic backoff is used. If cleared, then a random slot
assignment is used.

Allows the user software two levels of prioritization to
be assigned to each of the interrupts in IENl. A I assigns the corresponding interrupt in IENI a higher interrupt than an interrupt with a corresponding O.

MYSLOT.7 (DCJ) - Determines the type of Jam used
during CSMA/CD operation when a collision occurs.
If set to a I then a low D.C. level is used as the jam
signal. If cleared, then CRC is used as the jam signal.
The jam is applied for a length of time equal to the
CRC length.

IPNl.O (PGSRV) - Assigns the priority ofGSC receive
valid interrupt.
IPNl.l (PGSRE) - Assigns the priority of GSC error
receive iriterrupt.

NOACK - No Acknowledgment error bit, see TSTAT.

IPN1.2 (PDMAO) - Assigns the priority of DMA done
interrupt for Channel O.

NRZI - Non-Return to Zero inverted, a type of data
encoding where a 0 is represented by a change in the
level of the serial link. A I is represented by no change.

IPNl.3 (pGSTV) - Assigns the priority of GSC transmit viilid interrupt.

OVR - Overrun error bit, see RSTAT.

IPNl.4 (PDMAI) - Assigns the priority ofDMA done
interrupt for Channel 1.
IPNI.5 (pGSTE) - Assigns the priority of GSC transmit error interrupt.

PR - Protocol select bit, see GMOD. PCON (S7H)
76543210
ISMoolARSIREOIGARENIXRCLKIGFIENlpollOLI

ISA - Increment Source Address, see DCONO.

PCON.O (IDL) -Idle bit, used to place the CI52 into
the idle power saving mode.

LNI - Line Idle, see TSTAT.
PCON.I (PD) - Power Down bit, used to place the
CI52 into the power down power saving mode.

LSC - Local Serial Channel - The as¥nchronous serial
MCS-51
devices. Uses start/stop bits
port
found onL'__
all __
__ .l __
1._ 1 L __ ... _ _ ... _ ...: __ _
0_

~_:' _ _

FCON.2 (GFIEN) - GSC Fiag Idie Enabie bit, when
set, enables idle flags (01111110) to be generated between transmitted frames in SDLC mode.

i1UU t,;UU UUUMCJ UJUY 1 UyLC ilL i1 LlIUt:.

MO - One of two GSC mode bits, see TMOD.
MI - One of two GSC mode bits, see TMOD

PCON.3 (XRCLK) - External.Receive Clock bit, used
to enable an external clock to be used for only the receiver portion of the GSC.

MYSLOT - (OF5H)
76543210

PCON.4 (GAREN) - GSC Auxiliary Receive Enable
bit, used to enable the GSC to receive back-to-back
SDLC frames. This bit has no effect in CSMA/CD
mode.

8-56

HARDWARE DESCRIPTION OF THE 83C152

PCON.5 (REQ) - Requester mode bit, set to a I when
CI52 is to be operated as the requester station during
DMA transfers.

RFIFO - (F4H) RFIFO is a 3-byte FIFO that contains
the receive data from the GSC.

PCON.6 (ARB) - Arbiter mode bit, set to a I when
CI52 is to be operated as the arbiter during DMA
transfers.
PCON.7 (SMOD) - LSC mode bit, used to double the
baud rate on the LSC.

RSTAT (OE8H) - Receive Status Register
76543210

RSTAT.O (HBAEN) - Hardware Based Acknowledge
Enable - If set, enables the hardware based acknowledge feature.

PDMAO - Priority bit for DMA Channel 0 interrupt,
see IPNl.
'

RSTAT.I (GREN) - Receiver Enable - When set, the
receiver is enabled to accept incoming frames. This also
clears RDN, CRCE, AE, RCABT and the receive
FIFO. It is cleared by the receiver at the end of a reception or if any errors occurred: The status of GREN has
no effect on whether the receiver detects a collision in
CSMA/CD mode as the receiver input circuitry always
monitors the receive pin.

PDMAI - Priority bit for DMA Channel I interrupt,
see IPNl.
PGSRE - Priority bit for GSC Receive Error interrupt,
see IPNl.
PGSRV - Priority bit for GSC Receive Valid interrupt,
see IPNl.

RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set,
indicates that the receive FIFO contains data. The receive FIFO is a three byte buffer into which the receive
data is loaded. A CPU read of the FIFO retrieves the
oldest data and automatically updates the FIFO pointers. Setting GREN t9 a one will clear the receive FIFO.
The status of this flag is controlled by the GSC. This bit
is cleared if user S/W empties receive FIFO.

PGSTE - Priority bit for GSC Transmit Error interrupt, see IPNl.
PGSTV - Priority bit for GSC Transmit Valid interrupt, see IPNl.
PLO - One of two bits that determines the Preamble
Length, see GMOD.
PLI - One of two bits that determines the Preamble
Length, see GMOD.

RSTAT.3 (RDN) - Receive Done - If set, indicates the
successful completion of a receiver operation. Will not
be set if a CRC, alignment, abort, or FIFO overrun
error occurred.

PRBS - (OE4H) Pseudo-Random Binary Sequence, generates the pseudo-random number to be used in
CSMA/CD backoff algorithms.

RSTATA (CRCE) - CRC Error - Ifset, indicates that a
properly aligned frame was received with a mismatched
CRC.

PS - Priority bit for the LSC service interrupt, see IP.

RSTAT.5 (AE) - Alignment Error - If set, indicates
that the line went idle when the receiver shift register
was not full and the resulting CRC was bad in the
CSMA/CD mode. If a correct CRC was valid then AE
is not set. In SDLC mode, AE indicates that a nonbyte-aligned flag was received.

PTO - Priority bit for Timer 0 interrupt, see IP.
PTl - Priority bit for Timer I interrupt, see IP.
PXO - Priority bit for External interrupt 0, see IP.

RSTAT.6 (RCABT) - Receiver Collision/Abort Detect
- If set, indicates that a collision was detected after data
had been loaded into the receive FIFO in CSMA/CD
mode. In SDLC mode, RCABT indicates that 7 consecutive ones were detected prior to the end flag but after
data has been loaded into the receive FIFO.

PXI - Priority bit for External interrupt I, see IP.
RCABT - GSC Receiver Abort error bit, see RSTAT.
RDN - GSC Receiver Done bit, see RSTAT.
GREN - GSC Receiver Enable bit, see RSTAT.

RSTAT.7 (OVR) - Overrun - If set, indicates that the
receive FIFO was full and new shift register data was
written into it. It is cleared by user S/W.

RFNE - GSC Receive FIFO Not Empty bit, see
RSTAT.
RI - LSC Receive Interrupt bit, see SCON.

8-57

inter

HARDWARE DESCRIPTION OF THE 83C152

SARHO (OA3H) - Source Address Register High 0,
contains the high byte of the source address for DMA
Channel O.

SP (OSIH) - Stack Pointer, an eight bit pointer register
used during a PUSH, POP, CALL, RET, or RETI.
TCDCNT - (OD4H) Contains the number of collisions
in the current frame if using probabilistic CSMA/CD
and contains the maximum number of slots in the deterministic mode.

SARHI (OB3H) - Source Address Register High I,
contains the high byte of the source address for DMA
Channell.
SARLO (OA2H) - Source Address Register Low 0, contains the low. byte of the source address for DMA
Channel O.

TCDT - Transmit Collision Detect, see TSTAT.
TCON(OSSH)
76543210

SARLI (OB2H) - Source Address Register Low I, contains the low byte of the source address for DMA
Channell.

I TF1 I TA1 I TFO I TAO IIE1 IIT1 I lEO liTO I
TCON.O (ITO) - Interrupt 0 mode control bit.

SAS - Source Address Space bit, see DCONO.

TCON.I (lEO) - External interrupt 0 edge flag.

SBUF (099H) - Serial Buffer, both the receive and
transmit SFR location for the LSC.

TCON.2 (IT!) - Interrupt I mode control bit.

SCON(09SH)
76543210

TCON.3 (lEI) - External interrupt I edge flag.

I SMO I SM1 15M2 I AENI TB8 I AB8 I TI I AI I

TCON.4 (TRO) - Timer 0 run controi bit.
CON.5 (TFO) - Timer 0 overflow flag.

SCON.O (RI) - Receive Interrupt flag.
TCON.6 (TRI) - Timer I run control bit.
SCON.I (TI) - Transmit Interrupt flag.
TCON.7 (TFI) - Timer I overflow flag.
SCON.2 (RBS) - Receive Bit S, contains the ninth bit
that was received in Modes 2 and 3 or the stop bit in
Mode I if SM20. Not used in Mode O.

TDN.- Transmit Done flag, see TSTAT.
TEN - Transmit Enable bit, see TSTAT.

SCON.3 (TBS) - Transmit Bit S, the ninth bit to be
transmitted in Modes 2 and 3. .

TFNF - Transmit FIFO Not Full flag, see TSTAT.

SCON.4 (REN) - Receiver Enable, enables reception
for the LSC.

TFIFO - (S5H) TFIFO is a 3-byte FIFO that contains
the transmission data for the GSC.

SCON.5 (SM2) - Enables the multiprocessor communication feature in Modes 2 and 3 for the LSC.

THO (OSCH) - Timer 0 High byte, contains the high
byte for timer/counter O.

ScON.6 (SMI) - LSC mode specifier.

THI (OSDH) - Timer I High byte, contains the high
byte for timer/counter 1.
.

SCON.7 (SM2) - LSC mode specifier.
TI - Transmit Interrupt, see SCON.
SDLC - Stands for Synchronous Data Link Communication and is a protocol developed by IBM.

TLO (OSAH) - Timer 0 Low byte, coptains the low byte
for timer/counter O.

SLOTTM - (OB4H) Determines the length of the slot
time in CSMA/CD.

TLI (OSBH) - Timer I Low byte, contains the low byte
for timerlCounter 1.
TM - Transfer Mode, see, DCONO.

8-58

inter

HARDWARE DESCRIPTION OFTHE 83C152

TMOD(OS9H)
76543210

IGATE ICIT I M1 I MO I GATE I CIT I M1 I MO I

TSTAT.3 (TDN) - Transmit Done - When set, indicates the successful completion of a frame ttansmission.
If HBAEN is set, TDN will not be set until the end of
the IFS following the transmitted message, so that the
acknowledge can be checked. If an acknowledge is expected and not received, TDN is not set. An acknowledge is not expected following a broadcast or multi-cast
packet.

TMOD.O (MO) - Mode selector bit for Timer O.
TMOD.l (Ml) - Mode selector bit for Timer O.
TMOD.2 (CIf) - Timer/Counter selector bit for
TimerO.
TMOD.3 (GATE) - Gating Mode bit for Timer O.

TSTAT.4 (TCDT) - Transmit Collision Detect - If set,
indicates that the transmitter halted due to a collision.
It is set if a collision occurs during the data or CRC or
if there are more than eight collisions.

TMOD.4 (MO) - Mode selector bit for Timer 1.
TMOD.5 (Ml) - Mode selector bit for Timer 1.
TMOD.6 (C/T) - Timer/Counter selector bit for
Timer L

TSTAT.5 (UR) - Underrun - If set, indicates that in
DMA mode the last bit was shifted out of the transmit
register and that the DMA byte count did not equal
zero. When an underrun occurs, the transmitter halts
without sending the CRC or the end flag.

TMOD.7 (GATE) - Gating Mode bit for Timer 1.

7

TSTAT (ODS) - Transmit Status Register
6
5
4
32
1

TSTAT.2 (TFNF) - Transmit FIFO not full - When
set, indicates that new data may be written into the
transmit FIFO. The transmit FIFO is a three byte butTer that loads the transmit shift register with data.

0

ILNII NOACK I UR I TCOT ITON I TFNF I TEN IOMA I
TSTAT.O (DMA) - DMA Select - If set, indicates that
'DMA channels are used to service the GSC FIFO's and
GSC interrupts occur on TDN and RDN, and also enables UR to become set. If cleared, indicates that the
GSC is operating in it normal mode and interrupts occur on TFNE and RFNE.For more information on
DMA servicing please refer to the DMA section on
DMA serial demand mode (4.2.2.3).
TSTAT.l (TEN) - Transmit Enable - When set causes
TDN, UR, TCDT, and NOACK flags to be reset and
the TFIFO cleared. The transmitter will clear TEN after a successful transmission, a collision during the
data, CRC, or end flag. If cleared during a transmission
the GSC transmit pin goes to a steady state high level.
This is the method used to send an abort character in·
SDLC. Also DEN is forced to a high level. The end of
transmission is occurs whenever the TFIFO is emptied.

8-59

TSTAT.6 (NOACK) - No Acknowledge - If set, indicates that no acknowledge was received for the previous
frame. Will be set only if HBAEN is set and no acknowledge is received prior to the end of the IFS.
NOACK is not set following a broadcast or a multicast packet.
TSTAT.7 (LNI) - Line Idle - If set, indicates the receive line is idle. In SDLC protocol it is set if 15 consecutive ones are received. In CSMA/CD protocol, line
idle is set if no transitions occur on GR X D for 1.6 bit
times after a required transition. LNI is cleared after a
transition on GRXD.
TxC - External Clock input for GSC transmitter.
UR - Underrun flag, see TSTAT.
XRCLK - External GSC Receive Clock Enable bit, see
peON.
XTCLK - External GSC Transmit Clock Enable bit,
seeGMOD.

MCS® . . 51 Programmer's Guide
and Instruction Set

9

MCS®-S1 PROGRAMMER'S GUIDE
AND INSTRUCTION SET
The information presented in this chapter is collected from the previous MCS®-51 chapters of this book. The
material has been selected and rearranged to form a quick and convenient reference for the programmers of the
MCS-51. This guide pertains specifically to the 8051, 8052 and 80C51.
The following list should make it easier to find a subject in this chapter.
Memory Organization
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-2
Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-3
Direct and Indirect Address Area ........................................................ 9-5
Special Function Registers ............... ................................................. 9-7
Contents of SFRs after Power-On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-8
SFR Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-9
Program Status Word (PSW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-10
Power Control Register (PCON) . . :. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. 9-10
Interrupts. . .. .. . .. .. .. . ... .. . . .. .. . .. .. .. . . . . . . . .. . ... .. . . .. .. .. .. . .. .. . . . .. .. .. ... . . . ... 9-11
Interrupt Enable Register (IE) ............................................................. : 9-11
Assigning Priority Level .......................... "......................................... 9-12
Interrupt Priority Register . ..................................................... , .. ... . . . . .. 9-12
Timer/Counter Control Register (TCON) ................................................... 9-13
Timer/Counter Mode Control Register {TMOD} ............................................. 9-13
Timer Set-Up . ....................... ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-14
Timer/Counter 0 .............................................. ...... ; ................... 9-14
Timer/Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-15
Timer/Counter 2 Control Register (T2CON). . . ... .. . . .. .. .. .. .. . . . . .. .. . .. .. . .. .. .. ... ...... 9-16
Timer/Counter 2 Set-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-17
Serial Port Control Register. . . . . . .. .... . . . . . . .. .. .. . . .. .. .. .. .. . . .. . . . .... . .. .. . . ... ... ... 9-18
Serial Port Set-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-18
Generating Baud Rates ................................................................... 9-19
MCS-51 Instruction Set . ...... "................ ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-20
Instruction Definitions .................................................................... 9-24

9-1

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MEMORY ORGANIZATION
PROGRAM MEMORY
The 8051 has separate address spaces for Program Memory and Data Memory. The Program Memory can be up to
64K bytes long. The lower 4K (8K for the 8052) may reside on-chip.
Figure I shows a map of the 8051 program memory, and Figure 2 shows a map of the 8052 program memory.
FFFF r - - - - - - - - - - - . ,

"FFr-----------~

&OK
BYTES

EXTERNAL
-OR

14K
BYTES

EXTERNAL

1~~---------~
AND
4KBYTES

INTERNAL
0000 ~---------~

270249-1

Figure 1. The 8051 Program Memory

9-2

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

FFFF , - - - - - - - - - - -....

FFFF,-----------~

56 K
BYTES

EXTERNAL
64K
BYTES

--OR-.....,.....

EXTERNAL

~~--------------~
AND
1 F F F r - - - - - - - - - - -....
8KBYTES

INTERNAL

~L-----------------~

0000

L-_________

..J

270249-2

Figure 2. The 8052 Program Memory

Data Memory:
The 8051 can address up to 64K bytes of Data Memory to the chip. The "MOVX" instruction is used to access the
external data memory. (Refer to the MeS-51 Instruction Set, in this chapter, for detailed description of instructions).
The 8051 has 128 bytes of on-chip RAM (256 bytes in the 8052) plus a number of Special Function Registers (SFRs).
The lower 128 bytes of RAM can be accessed either by direct addressing (MOV data addr) or by indirect addressing
(MOV @Ri). Figure 3 shows the 8051 and the 8052 Data Memory organization.

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

OFFFr------------------,

INTERNAL

FF..-------------,
SFR.

84K
BYTES
EXTERNAL

DIRECT
ADDRESSING
ONLY

~~--------~
7F

- - AND

-----l.,..

DIRECT.
INDIRECT
ADDRESSING

oo~--------~

ooooL-------------~
270249-3

Figure 3a. The 8051 Data Memory

FFFFr--------------------,
INTERNAL

f

INDIRECT
ADDRESSING ONLY

1,---1------, '"
~HTOFFH

FF

FF..---=-~------......,

84K
SFR.
DIRECT
ADDRESSING
ONLY

BYTES
EXTERNAL

1--AND . . . . . . .

~

7Fr--------------------i
DIRECT.
INDIRECT
ADDRESSING

oo~--------~

J

270249-4

Figure 3b. The 8052 Data Memory

9·4'

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

INDIRECT ADDRESS AREA:
Note that in Figure 3b the SFRs and the indirect address RAM have the same addresses (80H-OFFH). Nevertheless, they are two separate areas and are accessed in two different ways.
For example the instruction
MOV

80H,#OAAH

writes OAAH to Port 0 which is one of the SFRs and the instruction
MOV

RO,#80H

MOV

@RO,#OBBH

writes OBBH in location 80H of the data RAM. Thus, after execution of both of the above instructions Port 0 will
contain OAAH and location 80 of the RAM will contain OBBH.

DIRECT AND INDIRECT ADDRESS AREA:
The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments
as listed below and shown in Figure 4.
1. Register Banks 0-3: Locations 0 through IFH (32 bytes). ASM-51 and the device after reset default to register
bank O. To use the other register banks the user must select them in the software (refer to the MeS-5l Micro
Assembler User's Guide); Each register bank contains 8 one-byte registers, 0 through 7.
Reset initializes the Stack Pointer to location 07H and it is incremented once to start from location 08H which is the
first register (RO) of the second register bank. Thus, in order to use more'than one register bank, the SP should be
intialized to a different location of the RAM where it is not used for data storage (ie, higher part of the RAM).
2. Bit Addressable Area: 16 bytes have been assigned for this segment, 20H-2FH. Each one of the 128 bits of this
'
segment can be directly, addressed (0-7FH).
The bits can be referred to in two ways both of which are acceptable by the ASM-51. One way is'to refer to their
addresses, ie. 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0-7 can also be referred to
as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7 and so on.
'
Each of the 16 bytes in this segment can also be addressed as a byte.
3. Scratch Pad Area: Bytes 30H through 7FH are available to the user as data RAM. However, if ~he stack pointer
has been initialized to this area, enough number of bytes should be left aside to prevent SP data destruction.

9-5

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Figure 4 shows the different segments of the on-chip RAM.

II-------8BylW

11.......

- - - - - - - 1...1

78

7F

70

77

88

6F

60

67

58

5F

50

57

48

4F

40

47

SCRATCH
PAD

,

38

3F

30

37

... 7F

28
20

AREA

O•••

2F

BIT
ADDRESSABLE
SEGMENT
27

18

3

1F

10

2

17

REGISTER

08

1

OF

BANKS

0

07
270249:"5

Figure 4. ·128 Bytes of RAM Direct and Indirect Addressable

9-6

infef

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

SPECIAL FUNCTION REGISTERS:
Table 1 contains a list of all the SFRs and their addresses.
Comparing Table 1 and Figure 5 shows that all of the SFRs that are byte and bit addressable are located on the first
column of the diagram in Figure 5.
Table 1
Symbol
'ACC
'B
'PSW
SP
DPTR
DPL
DPH
*PO
*P1
*P2
'P3
*IP
'IE
TMOD
*TCON
'+ T2CON
THO
TLO
TH1
TL1
+TH2
+ TL2
+ RCAP2H
+ RCAP2L
'SCON
SBUF
PCON

Name
Accumulator
B Register
Program Status Word
Stack Pointer
Data Pointer 2 Bytes
Low Byte
High Byte
PortO
Port 1
Port 2
Port 3
Interrupt Priority Control
Interrupt Enable Control
Timer/Counter Mode Control
Timer/Counter Control
Timer/Counter 2 Control
Timer/Counter 0 High Byte
Timer/Counter 0 Low Byte
Timer/Counter 1 High Byte
Timer/Counter 1. Low Byte
Timer/Counter 2 High Byte
Timer/Counter 2 Low Byte
T /C 2 Capture Reg. High Byte
T /C 2 Capture Reg. Low Byte
Serial Control
Serial Data Buffer
Power Control

addressable
8052 only

• = Bit

+

=

9-7

Address
OEOH
OFOH
ODOH
B1H
B2H
B3H
BOH
90H
OAOH
OBOH
OBBH
OA8H
89H
B8H
OC8H
8CH
8AH
BDH
BBH
OCDH
OCCH
OCBH
OCAH
98H
99H
B7H

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

WHAT DO THE SFRs CONTAIN JUST AFTER POWER-ON OR A RESET?
Table -2 li$ts the contents of each SFR after power-on or a hardware reset.
Table 2. Contents of the SFRs after reset '
Register

Value in Binary

00000000
00000000
00000000
00000111

°ACC
oS
°pSW
Sp
DPTR
DPH
DPL
'PO
'P1
'P2
'P3
"P

00000000
00000000
11111111
11111111
11111111
11111111
8051 XXXOOOOO,
8052 XXOOOOOO
80510XXOOOOO,
8052 OXOOOOOO
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

'IE

TMOD
'TCON
*+ T2CON
THO
TLO
TH1
TL1
+TH2
+TL2
+ RCAP2H
+ RCAP2L
'SCON
SBUF
PCON

x

Indeterminate

HMOS OXXXXXXX
CHMOS OXXXOOOO

= Undefined

• = Bit Addressable
+ = 8052on!y

9-8

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

SFR MEMORY MAP
8 Bytes

FB
FO
EB
EO
DB
DO
CB
CO
BB
BO
AB
AO
98
90
B8

BO

FF
B

F7

EF
ACC

E7

DF
PSW
T2CON

D7

RCAP2L

RCAP2H

TL2

TH2

CF
C7

IP
P3
IE
P2
SCON
P1
TCON
PO

t

BF
B7

AF
A7

SBUF

9F
97

TMOD
SP

TLO
DPL

TL1
DPH
Figure 5

Bit
Addressable

9-9

THO

TH1

BF
PCON

B7

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Those SFRs that have their bits assigned for various functions are listed in this section. A brief description of each bit
is provided for quick reference. For more detailed information refer to the Architecture Chapter of this book.

PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.

CY

AC
PSW.7
PSW.6

CY
AC
FO
RSI
RSO
OV

psw.s
PSW.4
PSW.3
PSW.2
PSW.I

psw.o

P

FO

RS1

RSO

P

OV

Carry Flag.
Auxiliary Carry Flag.
Flag 0 available to the user for general purpose.
Register Bank selector bit I (SEE NOTE I).
Register Bank selector bit 0 (SEE NOTE I).
Overflow Flag.
Not implemented, reserved for future use.'
Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of
'I' bits in the accumulator.
.

NOTE:
1. The value presented by RSO and RS1 selects the corresponding register bank.

RS1

RSO

Register Bank

Address

0
1
0
1

0
1
2
3

OOH-07H
OBH-OFH
10H-17H
1BH-1FH

0
0
1
1

'User software should not write 1s to reserved bits. These bits may be used in future MCS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.

PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.
SMOO

I _. I

GF1

GFO

PO

IOL

SMOD Double baud rate bit. If Timer I is used to generate baud rate and SMOD = I, the baud rate is doubled
when the Serial Port is used in modes I, 2, or 3.
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
Not implemented, reserved for future use.'
GFI
General purpose flag bit.
GFO
General purpose flag bit.
PD
Power Down bit. Setting this bit activates Power Down operation in the 80CSIBH. (Available only in
CHMOS).
IDL
Idle Mode bit. Setting this bit activates Idle Mode operation in the 80CSIBH. (Available only in CHMOS).
If Is are written to PD and IDL at the same time, PD takes precedence.
'User software should not write 1s to reserved bits. These bits may be used in future MCS-51 products to invoke new
features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.

9-10

infef

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

INTERRUPTS:
In order to use any of the interrupts in the MCS-SI, the following three steps must be taken.
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the corresponding individual interrupt enable bit in the IE register to 1.
3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt. See Table below.
Interrupt
Source

Vector
Address

lEO
TFO
IE1
TF1
RI&TI
TF2 & EXF2

0003H
OOOBH
0013H
001BH
0023H
002BH

In addition, for external interrupts, pins INTO and INTI (P3.2 and P3.3) must be set to I, and depending on whether
the interrupt is to be level or transition activated, bits ITO or ITI in the TCON register may need to be set to 1.
ITx = 0 level activated
ITx = 1 transition activated

IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled.

EA

ET2

EA

IE.7

ET2
ES
ETI
EXI
ETO
EXO

IE.6
IE.S
IE.4
IE.3
IE.2
IE. 1
IE.O

ES

ET1

EX1

ETO

EXO

Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt
source is individually enabled or disabled by setting or clearing its enable bit.
Not implemented, reserved for future use.·
Enable or disable the Timer 2 overflow or capture interrupt (80S2 only).
Enable or disable the serial port interrupt.
Enable or disable the Timer I overflow interrupt.
Enable or disable External Interrupt 1.
Enable or disable the Timer 0 overflow interrupt.
Enable or disable External Interrupt O.

·User software should not write Is to reserved bits. These bits may be used in future MCS-SI products to invoke
new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1.

9-11

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:
In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1.
Remember"that while an interrupt service is in progress, it cannot be interrupted tJy a lower or same level interrupt.

PRIORITY WITHIN LEVEL:
Priority within level is only to resolve simultaneous requests of the same priority level.
From high to low, interrupt sources are listed below:
lEO
TFO
lEI
TFI
RI or TI
TF2 or EXF2

IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.
If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a
higher priority.

I
PT2
PS
PTl
PXl
PTO
PXO

PT2

IP. 7
IP.6
IP.S
IP.4
"IP. 3
IP.2
IP. 1
IP. 0

PS

PT1

PX1

PTO

PXO

Not implemented, reserved for future use.·
Not implemented, reserved for future use.'
Defines the Timer 2 interrupt priority level (8052 only).
Defines the" Serial Port interrupt priority level.
Defines the Timer 1 interrupt priority level.
Defines External Interrupt 1 priority level.
Defines the" Timer 0 interrupt priority level.
Defines th~ External Interrupt 0 priority level.

'User software should'not 'write Is to reserved bits. These bits may be used in future MeS-51 products to invoke
new features. In that case, 'the reset or inactive value of the new bit will be 0, and its active value will be 1.

•

:.0\

9-12

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

TeON: TIMER/COUNTER CONTROL REGISTER. BIT ADDRESSABLE.
TF1

TFI

TR1

TRI
TFO

TCON. 7
.
TCON.6
TCON. 5

TRO
lEI

TCON. 4
TCON. 3

IT!

TCON. 2

lEO

TCON. 1

ITO

TCON. 0

TFO

TRO

IE1

IT1

lEO

ITO

Timer I overflow flag. Set by hardware when the Timer/Counter I overflows. Cleared by hardware as processor vectors to the interrupt service routine.
Timer I run control bit. Set/cleared by software to turn Timer/Counter ION/OFF.
Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the service routine.
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF.
External Interrupt I edge flag. Set by hardware when External Interrupt edge is detected.
Cleared by hardware when interrupt is processed.
Interrupt I type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared
by hardware when interrupt is processed.
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.

TMOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT
ADDRESSABLE.

I\: GATE
GATE

ciT
MI
MO

CIT

M1

MO

I

GATE

CIT

)\:

M1

MO
)

I

TIMER 1
TIMER 0
When TRx (in TCON) is set and GATE = I, TIMER/COUNTERx will run only while INTx pili is high
(hardware control). When GATE = 0, TIMER/COUNTERx will run only while TRx = I (software
control).
Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin).
Mode selector bit. (NOTE 1)
Mode selector bit. (NOTE 1)

NOTE 1:

M1

MO

o

o

o

1

o
1

Operating Mode
o
13-bit Timer (MCS-48 compatible)
1
16-bit Timer/Counter
2
8-bit Auto-Reload TimerlCounter
(Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0
3
control bits, THO is an 8-bit Timer and is controlled by Timer 1 control bits.
(Timer 1) Timer/Counter 1 stopped.
3

9-13

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

TIMER SET·UP
Tables 3 through 6 give some values for TMOD which can be used to set up Timer 0 in different modes.
It is assumed that only one timer is being used at a time. If it is desired to run Timers 0 and 1 simultaneously, in any
mode, the value in TMOD for Timer 0 must be ORed .with the value shown for Timer 1 (Tables 5 and 6).

For example, if it is desired to run Timer 0 in mode 1 GATE (external control), and Timer 1 in mode 2 COUNTER,
then the value that must be loaded into TMoD is 69H (09H from Table 3 ORed with 60H from Table 6).
Moreover, it'is assumed that the user, at this point,. is not ready to tum the timers on and will do that at a different
point in the program by setting bit TRx (in TCON) to 1.

TIMER/COUNTER 0

As a Timer:
Table 3
TMOD
MODE

TIMER 0
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

0
1
2
3

13-bit Timer
16-bit Timer
8-bit Auto-Reload
two 8-bit Timers

OOH
01H
02H
03H

08H
09H
OAH
OSH

As a Counter:
Table 4
TMOD
MODE

COUNTER 0
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

0
1
2
3

13-bit Timer
16-bit Timer
8-bit Auto-Reload
one 8-bit Counter

04H
05H
OSH
07H

OCH
ODH

OEH
OFH

NOTES:

1. The Timer is turned ON/OFF by setting/clearing bit TRO in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INTO (P3.2) when TRO = 1
(hardware control).

9-14

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

TIMER/COUNTER 1
As a Timer:
TableS
TMOD
MODE

TIMER 1
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

0
1
2
3

13-bit Timer
16-bit Timer
B-bit Auto-Reload
does not run

OOH
10H
20H
30H

BOH
90H
AOH
BOH

As a Counter:

TableS
TMOD

MODE

0
.1

2

3

COUNTER 1
FUNCTION

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

13-bit Timer
16-bit Timer
B-bit Auto-Reload
not available

40H
50H
60H

COH
DOH
EOH

-

-

NOTES:

1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1 (P3.3) when TR1 = 1
(hardware control).

9-15

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

T2CON: TIMER/COUNTER 2 CONTROL REGISTER. BIT ADDRESSABLE
8052 Only
1 TF2 1 EXF2

RCLK

TCLK

.1

EXEN2

TR2

TF2

C/T2.1 CP/RL2

T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when
.
either RCLK = I or CLK = I
EXF2
T2CON. 6 Timer 2 externa!. flag set when either a capture or reload is caused by a negative transition on
T2EX, and EXEN2= 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU
to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK
nCON. 5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
receive clock in modes I & 3. RCLK = 0 causes Timer I overflow to be used for the receive
clock.
TLCK
T2CON. 4 Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
transmit clock in modes I & 3. TCLK = 0 causes Timer I overflows to be used for the
transmit clock.
EXEN2 T2CON. 3 Timer 2 external enable flag. When set,' allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2 Software START/STOP control for. Timer 2. A logic I starts the Timer.
C/T2
T2CON. 1 Timer or Counter select.
o = Internal Timer. I = External Event Counter (falling edge triggered).
CP/RL2 T2CON.O Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, Auto-Reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when' EXEN2 = 1. When either RCLK = 1 or TCLK = I,
this bit is ignored and the Timer is forced to Auto-Reload on Timer 2 overflow.

9-16

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

TIMER/COUNTER 2 SET-UP
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit.
Therefore, bit TR2 must be set, separately, to turn the Timer on.

As a Timer:
Table 7
T2CON
MODE

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

16-bit Aulo-Reload

OOH

OSH

16-bit Capture

01H

09H

BAUD rate generator receive &
transmit same baud rate

34H

36H

receive only

24H

26H

transmit only

14H

16H

As a Counter:
TableS
TMOD
MODE

INTERNAL
CONTROL
(NOTE 1)

EXTERNAL
CONTROL
(NOTE 2)

16-bit Auto-Reload
16-bit Capture

02H
03H

OAH
OBH

NOTES:
1. Capture/Reload occurs only on Timer/Counter overflow.
2. Capture/Reload occurs on Timer/Counter overflow and a 1 to 0 transition on T2EX
(P1.1) pin except when Timer 2 is used in the baud rate generating mode.

9-17

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

SCON: SERIAL PORT CONTROL REGISTER. BIT ADDRESSABLE.

I

SMO

SM1

SM2

REN

TB8

RB8

TI

RI

SMO
SMI
SM2

SCON.7 Serial Port mode specifier. (NOTE 1).
SCON. 6 Serial Port mode specifier. (NOTE 1).
SCON.5 Enables the multiprocessor communication feature in modes 2 & 3. In mode 2 or 3, ifSM2 is set
to 1 then RI will not be activated if the received 9th data bit (RB8) is O. In mode I, if SM2 = 1
then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be O.
(See Table 9).
.

REN
TB8
RB8

SCON. 4 Set/Cleared by software to Enable/Disable reception.
SCON. 3 The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software.
SCON. 2. In modes 2 & 3, is the 9th data bit that was received. In mode 1, ifSM2 = 0, RB8 is the stop bit
that was received. In mode 0, RB8 is not used.
. .
SCON. 1 Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the
beginning of the stop bit in the other modes. Must be cleared by software.
SCON. 0 Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway
through the stop bit time in the other modes (except see SM2). Must be cleared by software.

TI
RI
NOTE 1:

SMO

SM1

Mode

Description

Baud Rate

o
o

0
1
0

0
1
2

SHIFT REGISTER
8-Bit UART
9-Bit UART

3

9-Bit UART

Fo.sc.l12
Variable
Fosc.l64 OR
Fosc.l32
Variable

1

SERIAL PORT SET·UP:
Table 9
MODE

SCON

5M2 VARIATION

0
1
2
3

10H
50H
90H
DOH

Single Processor
Environment
(SM2 = 0)

0

NA
70H
BOH
FOH

Multiprocessor
EnVironment
(SM2 = 1)

•
I

2
3

GENERATING BAUD RATES
Serial Port in Mode 0:
Mode 0 has a fixed baud rate which is 1/12 of the oscillator frequency. To run the serial port in this mode none of
the Timer/Counters need to be set up. Only the SCON register needs to be defined.
Osc Freq
Baud Rate = - - 12

Serial Port in Mode 1:
Mode 1 has a variable baud rate. The baud rate can be generated by either Timer 1 or Timer 2 (8052 only).
9-18

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

USING TIMER/COUNTER 1 TO GENERATE BAUD RATES:
For this purpose, Timer 1 is used in mode 2 (Auto-Reload). Refer to Timer Setup section of this chapter.
B d R te =
K x Oscillator Freq.
au
a
32 x 12 x [256 - (TH111

If SMOD = 0, then K = 1.
If SMOD = I, then K = 2. (SMOD is the PCON register).
Most of the time the user knows the baud rate and needs to know the reload value for THI.
Therefore, the equation to calculate THI can be written as:
TH1 = 256 _ K x Ose Freq.
384 x baud rate

THI must be an integer value. Rounding off THI to the nearest integer may not produce the desired baud rate. In
this case, the user may have to choose another crystal frequency.
Since the PCON register is not bit addressable, one way to set the bit is logical ORing the PCON register. (ie, ORL
PCON,#80H). The address of PCON is 87H.

USING TIMER/COUNTER 2 TO GENERATE BAUD RATES:
For this purpose, Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this
chapter. If Timer 2 is being clocked through pin T2 (PI.O) the baud rate is:
Timer 2 Overflow Rate
B d
au Rate =
16

And if it is being clocked internally the baud rate is:
Osc Freq
Baud Rate = 32 x [65536 - (RCAP2H, RCAP2L))

To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as:
. RCAP2H, RCAP2L = 65536 - 3 O~c F~e~
2x au
ate

SERIAL PORT IN MODE 2:
The baud rate is fixed in this mode and is
bit in the PCON register.

Va. or '1.4 of the oscillator frequency depending on the value of the SMOD

In this mode none of the Timers are used and the clock
SMOD = I, Baud Rate =
SMOD

Va.

co~es

from the internal phase 2 clock.

Osc Freq.

= 0, Baud Rate = '1.4 Osc Freq.

To set the SMOD bit: ORL

PCON, # 80H. The address of PCON is 87H.

SERIAL PORT IN MODE 3:
The baud rate in mode 3 is variable and sets up exactly the same as in mode 1.

9-19

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MCS®-S1 INSTRUCTION SET
Table 10.8051 Instruction Set Summary
Interrupt Response Time: Refer to Hardware Description Chapter.

Mnemonic'

ARITHMETIC OPERATIONS
ADD
A,Rn
Add register to
Accumulator
A,direct Add direct byte to
ADD
Accumulator
A,@Ri
Add indirect RAM
ADD
to Accumulator
A,#data Add immediate
ADD
data to
Accumulator
Add register to
AD DC A,Rn
Accumulator
with Carry
ADDC A,direct Add direct byte to
Accumulator'
with Carry
ADDC A,@Ri
Add indirect
RAM to
Accumulator
with Carry
ADDC A,#data Add immediate
data toAcc
with Carry
SUBB A,Rn
Subtract Register
from Acc with
borrow
SUBB A,direct Subtract direct
byte from Acc
with borrow
SUBB A,@Ri
Subtract indirect
RAMfromACC
with borrow
SUBB .A,#data Subtract
immediate data
from Acc with
borrow

Instructions that Affect Flag Settings(1)
Instruction
ADD
ADDC
SUBB
MUl
DIV
DA
RRC
RlC
SETBC

C
X
X
X
0
0
X
X
X

Flag
OV
X
X
X
X
X

Instruction
AC
X ClRC
X CPlC
X ANlC,bit
ANlC,/bit
ORlC,bit
ORlC,bit
MOVC,bit
CJNE
/

Description

Flag
C OV AC
0
X
X
X
X
X
X
X

(I)Note that operations on SFR byte address 208 or
bit addresses 209-215 (i.e., the PSW or bits in the
PSW) will also affect flag settings.
Note on instruction set and ad,dressing modes:
- Register R7-RO of the currently seRn
lected Register Bank..
direct
- 8-bit- internal data location's address.
This could be an Internal Data RAM
location (0-127) or a SFR [i.e., I/O
port, control register, status register,
etc. (128-255)J.
@Ri
- 8-bit internal data RAM location (0255) addressed indirectly through register Rl orRO.
#data
- 8-bit constant included in instruction.
#data 16 - 16-bit constant included in instruction.
addr 16 - 16-bit destination address. Used by
LCALL & LJMP. A branch ,can be
anywhere within the 64K-byte Program Memory address space.
addr 11 - II-bit destination address. Used by
ACALL & AJMP. The branch will be
within the same 2K-byte page of program memory as the first byte of the
following instruction.
rei
- Signed (two's complement) 8-bit offset
byte. Used by SJMP and all conditional jumps. Range is -128 to + 127
bytes relative to first byte of the following instruction.
- Direct Addressed bit in Internal Data
bit
RAM or Special Function Register.
-New operation not provided by
8048AH/8049AH.

Byte

Oscillator
Period

12
2

12
12

2

12
12

2

12
12

'2

12
12

2

12
12

2

12

increment
12
Accumulator
INC
Rn
Increment register
12
INC
direct
Increment direct
2
12
byte
@Ri
INC
Increment direct
12
RAM
DEC
A
Decrement
12
Accumulator
DEC
Rn
Decrement
12
Register
DEC
direct
Decrement direct
2
12
byte
DEC . @Ri
Decrement
12
indirect RAM
All mnemonics copyrighted @Intel Corporation 1980

iNC

9-20

A

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Table 10. 8051 Instruction Set Summary (Continued)
Mnemonic

Description

Byte

ARITHMETIC OPERATIONS (Continued)
Increment Data
INC DPTR
Pointer
Multiply A & B
MUL AB
Divide A by B
DIV AB
DA
A
Decimal Adjust
Accumulator
LOGICAL OPERATIONS
ANL A,Rn
AND Register to
Accumulator
ANL A,direct
AND direct byte
to Accumulator
AND indirect
ANL A,@Ri
RAM to
Accumulator
AND immediate
ANL A,#data
data to
Accumulator
ANL direct,A
AND Accumulator
to direct byte
ANL direct, # data AND immediate
data to direct byte
OR register to
ORL A,Rn
Accumulator
ORL A,direct
OR direct byte to
Accumulator
ORL A,@Ri
OR indirect RAM
to Accumulator
ORL A,#data
OR immediate
data to
Accumulator
ORL direct,A
OR Accumulator
to direct by1e
ORL direct, # data OR immediate
data to direct byte
XRL A,Rn
Exclusive·OR
register to
Accumulator
Exciusive·OR
XRL A,direct
direct byte to
Accumulator
Exciusive·OR
XRL A,@Ri
indirect RAM to
Accumulator
Exciusive·OR
XRL A,#data
immediate data to
Accumulator
Exclusive·OR
XRL direct,A
Accumulator to
direct byte
XRL direct, # data Exclusive·OR
immediate data
to direct byte
Clear
CLR A
Accumulator
CPL A
Complement
Accumulator

Oscillator
Period

Mnemonic

LOGICAL OPERATIONS (Continued)
Rotate
RL
A
Accumulator Left
Rotate
RLC
A
Accumulator Left
through the Carry
Rotate
RR
A
Accumulator
Right
Rotate
RRC
A
Accumulator
Right through
the Carry
Swap nibbles
SWAP A
within the
Accumulator
DATA TRANSFER
Move
MOV A,Rn
register to
Accumulator
MOV A,direct
Move direct
byte to
Accumulator
MOV A,@Ri
Move indirect
RAM to
Accumulator
Move
MOV A,#data
immediate
data to
Accumulator
MOV Rn,A
Move
Accumulator
to register
Move direct
MOV Rn,direct
byte to
register
Move
MOV Rn,#data
immediate data
to register
Move
MOV direct,A
Accumulator
to direct by1e
Move register
MOV direct,Rn
to direct by1e
MOV direct, direct Move direct
byte to direct
Move indirect
MOV direct,@Ri
RAM to
direct byte
MOV direct, # data Move
immediate data
to direct byte
Move
MOV @Ri,A
Accumulator to
indirect RAM

24
48
48
12

12
2

12
12

2

12

2

12

3

24
12

2

12
12

2

12

2

12

3

24
12

2

12

12

2

12

2

12

3

24

Description

12
12

Byte

Oscillator
Period
12
12

12

12

12

12

2

12

12

2

12

12

2

24

2

12

2

12

2

24

3

24

2

24

3

24

12

All mnemonics copyrighted ® Intel Corporation 1980

9-21

inter

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Table 10.8051 Instruction Set Summary (Continued)
Mnemonic

Description

Byte

Oscillator
Period

2

24

2

12

3

24

Mnemonic

DATA TRANSFER (Continued)
Move direct
byte'to '
indirect RAM
Move
MOV @Ri,#data
immediate
data to
indirect RAM
MOV DPTR,#dataI6 Load Data
Pointer with a
16-bit constant
MOVC A,@A+DPTR
Move Code
byte relative to
DPTRtoAcc
MOVC A,@A+PC
Move Code
byte relative to
PC to Acc
MOVX A,@Ri
Move
External
RAM (8-bit
addr) toAcc
MOVX A,@DPTR
Move
External
, RAM (16-bit
addr) toAcc
MOVX @Ri,A
Move Acc to
External RAM
(8-bit addr)
MOVX @DPTR,A
Move Accto
External RAM
(16-bit addr)
PUSH direct
Push direct
byte onto
MOV

@Ri,direct

XCH

XCH

XCH

direct

A,Rn

A,direct

A,@Ri

XCHD A,@Ri

Pop direct
byte from
stack
Exchange
register with
Accumulator
Exchange
direct byte
with
Accumulator
Exchange ,
indirect RAM
with
Accumulator
Exchange loworder Digit
indirect RAM
withAcc

Byte

Oscillator
Period

BOOLEAN VARIABLE MANIPULATION
CLR
CLR
SETB
SETB
CPL

C
bit
C
bit
C

CPL

bit

ANL

C,bit

24

ANL

C,/bit

24

ORL

C,bit

ORL

C,/bit

MOV

C,bit

MOV

bit,C

JC

rei

JNC

rei

JB

bit,rel

JNB

bit,rel

JBC

, bit,rel

24

24

24

24

2

24

2

24

stac~

POP

Description

1
2
1
2

12
12
12
12
12

2

12

2

24

2

24

2

24

2

24

2

12

2

24

2

24

2

24

3

24

3

24

3

24

2

24

3

24

PROGRAM BRANCHING
ACALL

addrll

LCALL

addr16

12

2

Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement
Carry
Complement
direct bit
AND direct bit
to CARRY
AND complement
of direct bit
to Carry
OR direct bit
to Carry
OR complement
of direct bit
to Carry
Move direct bit
to Carry
Move Carry to
direct bit
Jump if Carry
is set
Jump if Carry
not set
Jump if direct
Bit is set
Jump if direct
Bit is Not set
Jump if direct
Bit is set &
clear bit

12
RET
RETI
12

12

AJMP

addrll

LJMP
SJMP

addr16
rei

Absolute
Subroutine
Call
Long
Subroutine
Call
Return from
Subroutine
Return from
interrupt
Absolute
Jump
Long Jump
Short Jump
(relative addr)

24
24
2

24

3

24
24

2

All mnemonics copyrighted ©Intel Corporation 1980

9-22

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Table 10.8051 Instruction Set Summary (Continued)
Mnemonic

Description

PROGRAM BRANCHING (Continued)
@A+DPTR Jump indirect
JMP
relative to the
DPTR
JZ
rei
Jump if
Accumulator
is Zero
JNZ
rei
Jump if
Accumulator
is Not Zero
CJNE A,direct,rel
Compare
direct byte to
Acc and Jump
if Not Equal
CJNE A,#data,rel Compare
immediate to
Acc and Jump
if Not Equal

Byte

Oscillator
Period

Mnemonic

PROGRAM BRANCHING (Continued)
Compare
CJNE Rn, # data,rel
immediate to
register and
·JumpifNot
Equal
CJNE @Ri,#data,rel Compare
immediate to
indirect and
Jump if Not
Equal
DJNZ Rn,rel
Decrement
register and
Jump if Not
Zero
Decrement
DJNZ direct,rel
direct byte
and Jump if
Not Zero
NOP
No Operation

24

2

24

2

24

3

24

3

Description

24

Byte

Oscillator
Period

3

24

3

24

2

24

3

24

12

All mnemonics copyrighted @lIntel Corporation 1980

9-23

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

INSTRUCTION DEFINITIONS
ACALL

addr11

Function:

Absolute Call

Description:

ACALL unconditionally calls a subroutine located at the indicated address. The instruction
increments the PC twice to obtain the address of the following instruction, then pushes the
I6-bit result onto the,stack (low-order byte first) and increments the Stack Pointer twice. The
destination address is obtained by successively concatenating the, five high-order bits of the
incremented PC, opcode bits 7-5, and the second byte of the instruction. The subroutine called
must therefore start within the same 2K block of the program memory as the first byte of the
instruction following ACALL. No flags are affected.

Example:

Initially SP equals 07H. The label "SUBRTN" is at program memory location 0345 H. After
executing the instruction,
ACALL SUBRTN '
at location OI23H, SP will contain 09H, internal RAM locations OSH and 09H will contain
25H and OIH, respectively, and the PC will contain 0345H.

Bytes:

2

Cycles:

2

Encoding:
Operation:

I a10 a9 a8 1

0 0 0

11

a7 a6 a5 a4

ACALL
(PC) - (PC) + 2
(SP) - (SP) + 1
«SP» - (PC7-O)
(SP) - (SP) + 1
«SP» - (PCIS-S)
(PCw_o) - page address

9-24

a3' a2 a1 aO

inter
ADD

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A, < src-byte >
Function:

Description:

Add
ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or
bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an
overflow occured..
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6;
otherwise OV is cleared. When adding signed integers, OV indicates a negative number pro-

duced as the sum of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
Example:

The Accumulator holds OC3H (llOOOO1IB) and register 0 holds OAAH (10 10 10 lOB). The
instruction,
ADD

A,RO

will leave 6DH (01 101 101B) in the Accumulator with the AC flag cleared and both the carry
flag and OV set to I.
ADD

A,Rn
Bytes:
Cycles:

ADD

Encoding:

I0

Operation:

ADD
(A) ~ (A)

o

1 r r r

1 0

+

(Rn)

A,direct
Bytes:

2

Cycles:
Encoding:

I0

Operation:

ADD
(A) ~ (A)

010

o1
+

0 1

direct address

(direct)

9-25

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

ADD A,@RI
Bytes:
Cycles:
Encoding:

100 1 0

Operation:

ADD
(A) -

(A)

011

+ «R0)

ADD A,#data
Bytes:

2

Cycles:
Encoding:

1 00 1 0

Operation:

ADD
(A)-(A)

o1 0
+

0

immediate data

# data

ADDC A, 
Function:
Description:

Add with Carry
ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator
contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set,
respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding
unsigned integers, the carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out ofbit.7 but not out of
bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number
produced as the sum of two positive operands or a positive sum from two negative operands.

Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.

Example:

The Accumulatpr holds OC3H (1 100001 IB) and register 0 holds OAAH (lOlOlOlOB) with the
carry flag set. The instruction,
ADDC

A,RO

will leave 6EH (01101 1lOB) in the Accumulator with AC cleared and both the Carry flag and
OV set to 1.
.

9-26

inter
ADDC

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,Rn
Bytes:
Cycles:

Encoding:

1,--0_O_l_-,--_l_r_r_r--l1

Operation:

ADDC
(A) ~ (A)

+

(C)

+ (Rn)

AD DC A,direct
Bytes:

2

Cycles:
Encoding:
Operation:

ADDC

L..1_o_o_1_~0_1_0_1-,
ADDC
(A) ~ (A)

+

(C)

+

direct address

(direct)

A,@Ri
Bytes:
Cycles:

Encoding:

10 0 1 1

Operation:

ADDC
(A) ~ (A)

0 1 1 i

+

(C)

+

«Ri»

AD DC A,#data
Bytes:

2

Cycles:
Encoding:

1-1_0_0_1_-,--0_1_0_0-,

Operation:

ADDC
(A) ~ (A)

+

(C)

+

immediate data

#data

9-27

I

inter
AJMP

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

addr11
Function:

Description:

Example:·

Absolute Jump
AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits
7-5, and the second byte of the instruction. The destination must therefore be within the same
2K block of program memory as the first byte of the instruction following AJMP.
The label "JMPADR" is at program memory location 0123H. The instruction,
AJMP JMPADR
is at location 0345H and will load the PC with 0123H.

Bytes:

2

Cycles:

2

Encoding:
Operation:

ANL

I a10 a9 a8 0

0 0 0 1

a7 a6 a5 a4

a3 a2 a1 aO

AJMP
(PC) +- (PC) + 2
(PCIO-O) +- page address

< dest-byte > , < src-byte >
Function:

Description:

Logical-AND for byte variables
ANL performs the bitwise logical-AND operation between the variables indicated and stores
the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

If the Accumulator holds OC3H (110000 11 B) and register 0 holds 55H (OlOlOlOlB) then the
instruction,
"A...NL

LA..,RO

will leave 41H (OlOOOOOlB) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of
bits in any RAM location or hardware register. The mask byte determining the pattern of bits
to be cleared would either be a constant contained in the instruction or a value computed in
'
the Accumulator at run-time. The instruction,
ANL

Pl,#OlllOOllB

will clear bitS 7, 3, and 2 of output port 1.

9-28

intJ
ANL

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,Rn
Bytes:
Cycles:
Encoding:
Operation:

ANL

1 01

o1

1 r r r

ANL
(A) ~ (A) A (Rn)

A,direct
Bytes:

2

Cycles:
Encoding:

I0 1 o1

Operation:

ANL
(A)

ANL

~

o1

0 1

direct address

(A) A (direct)

A,@Ri
Bytes:
Cycles:
Encoding:

1 01

. Operation:

ANL
(A)

ANL

o1

~

o1

1

(A) A «Ri»

A, # data
Bytes:

2

Cycles:

ANL

o1

o10

Encoding:

1 01

Operation:

ANL
(A) ~ (A) A #data

0

immediate data

direct,A
Bytes:

2

Cycles:
Encoding:
Operation:

1 01

o1

ANL
(direct)

~

001 0

direct address

(direct) A (A)

9-29

inter
ANL

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

direct, # data
Bytes:

3

Cycles:

2

Encoding:
Operation:

ANL

Function:

.Example:

ANL

0 0 1 1

direct address

I

immediate data

ANL
(direct) +- (direct) " #data

C,

Description:

ANL

I 0 .1 0 1

Logical-AND for bit variables
If the Boolean value of the source bit is a logical 0 then clear the carry flag; otherwise leave the
carry flag in its current state. A slash ("/") preceding the operand in the assembly language
indicates that the logical complement of the addressed bit is used as the source value, but the
source bit itself is not affected. No other flags are affected.

Only direct addressing is allowed for the source operand.
Set the carry flag if, and only if, PI.O = 1, ACC. 7 = 1, and OV = 0:
MOV C,Pl.O

;LOAD CARRY WITH INPUT PIN STATE

ANL C,ACC.7

;AND CARRY WITH ACCUM. BIT 7

ANL C,/OV

;AND WITH INVERSE OF OVERFLOW FLAG

C,bit
Bytes:

2

Cycles:

2

Encoding:

11 000

Operation:

ANL
(C) +- (C) " (bit)

001 0

bit address

C,/bit
Bytes:

2

Cycles:

2

Encoding:

I1o1

Operation:

ANL
(C) +- (C) " I (bit)

0000

bit address

9-30

inter
CJNE

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

< dest-byte > , < src-byte > , rei
Function:

Description:

Compare and Jump if Not Equal.
CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
The carry flag is set if the unsigned integer value of  is less than the unsigned
integer value of ; otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the Accumulator may be
compared with any directly addressed byte or immediate data, and any indirect RAM location
or working register can be compared with an immediate constant.

Example:

The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence,
CJNE

R7,#60H, NOT_EQ
R7 = 60H.
IFR7 < 60H.
R7> 60H.

JC

sets the carry flag anc;l branches to the instruction at label NOT_EQ. By testing the carry flag,
this instruction determines whether R 7 is greater or less than 60H.
If the data being presented to Port I is also 34H, then the instruction,
WAIT:

CJNE A,PI,WAIT

clears the carry flag and continues with the next instruction in sequence, since the Accumulator does equal the data read from Pl. (If some other value was being input on PI, the program
will loop at this point until the PI data changes to 34H.)
CJNE

A,direct,rel
Bytes:

3

Cycles:

2

Encoding:
Operation:

I1 0 1 1
(PC) IF (A)
THEN

0 1 0 1

(PC) + 3
(direct)

<>

(PC) IF (A)
THEN

direct address

<

(PC)

+ relative offset

(direct)

(C)-l
ELSE

(C)-O

9-31

reI. address

infef

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

CJNE A,#data,rel
Bytes:

3

Cycles:

2

Encoding:
Operation:

. 11 011

o1 0

0

immediate data

reI. address

(PC) - (PC) + 3
IF (A) < > data

THEN
(PC) -

(PC)

+

relative offset

IF (A) < data

THEN
(C)-l

ELSE
(C)-O

CJNE

Rn,#data,rel
Bytes:

3

Cycles:

2

Encoding:

110 1 1

1 r r r

Operation:

(PC) - (PC) + 3
IF (Rn) < > data

THEN
(PC) -

(PC)

immediate data

+

rei. address

relative offset

IF (Rn) < data

THEN"
(C)-l

ELSE
(C)-O

CJNE

@Ri,#data,rel
Bytes:

3

Cycles:

2

Encoding:

11 0 1 1

0 1 1

Operation:

(PC) IF

+

«Ri»

(PC)

3

< > data

THEN

(PC) -

IF

«Ri»

immediate data

(PC)

+

relative offset

< data

THEN

(C)-l

ELSE
(C)-O

9-32

rei. address

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

CLR

A
Function:

Description:
Example:

Clear Accumulator
The Accumulator is cleared (all bits set on zero). No flags are affected.
The Accumulator contains SCH (0101 I 100B). The instruction,
CLR

A

will leave the Accumulator set to OOH (OOOOOOOOB).
Bytes:
Cycles:
Encoding:

11

Operation:

CLR

1 1

0 1 0 0

(A)~O

CLR

bit
Function:

Description:
Example:

Clear bit
The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the
carry flag or any directly addressable bit.
Port I has previously. been written with SDH (OlOllIOIB). The instruction,
CLR

P1.2

will leave the port set to S9H (OIOIIOOIB).
CLR

C
Bytes:
Cycles:
Encoding:

11

Operation:

CLR

0 0

0 0 1 1

(C)~O

CLR

bit
Bytes:

2

Cycles:
Encoding:

1 1 1 0 0.1 0 0 1 0

Operation:

CLR
(bit) ~O

bit address

9-33

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

CPL A
Function:
Description:
Example:

Complement Accumulator

. Each bit of the Accumulator is logically complemented (one's complement). Bits which previously contained a one are changed to a zero and vice-versa. No flags are affected.
The Accumulator contains 5CH (01011100B). The instruction,
CPL A
will leave the Accumulator set to OA3H (10100011B).

Bytes:
Cycles:
Encoding:
Operation:

I1

1 1

0 1 0 0

CPL
(A) ..... -, (A)

CPL bit
Function:
Description:

Complement bit
The bit variable specified is complemented. A bit which had been a one is changed to zero and
vice-versa. No other flags are affected. CLR can operate on the carry or any directly addressable bit.

Note: When this instruction is used to modify an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example:

Port 1 has previously been written with 5BH (Ol011101B). The instruction sequence,
CPL Pl.l
CPL P1.2
will leave the port set to 5BH (01011011B).

CFL C

Bytes:
Cycles:
Encoding:
Operation:

I1 0 1 1

0 0 1 1

CPL
(C) ..... -, (C)

9-34

intJ
CPL

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

bit
Bytes:

2

Cycles:
Encoding:

1-1_1_0_1_1----'-_0_0_1_0--'

Operation:

CPL
(bit) -

bit address

-, (bit)

DA A
Function:
Description:

Decimal-adjust Accumulator for Addition
DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC
instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxxx 10 IO-xxxxi II 1), or if the AC flag is one,
six is added to the Accumulator producing the proper BCD digit in the low-order nibble. This
internal addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (1OIOxxxx-l1 lxxxx),
these high-order bits are incremented by six, producing the proper BCD digit in the high-order
nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but
wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD
variables is greater than 100, allowing multiple precision decimal addition. OV is not affected.

All of this occurs during the one instruction cycle. Essentiilily, this instruction performs the
decimal conversion by adding OOH, 06H, 60H, or 66H to the Accumulator, depending on
initial Accumulator and PSW conditions.

Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor does DA A apply to decimal subtraction.

9-35

inter

MCS®·S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Example:

The Accumulator holds the "value 56H (01010110B) representing the packed "BCD digits of the
decimal number 56. Register 3 contains the value 67H (OllOOllIB) representing the packed
BCD digits of the decimal number 67. The carry flag is set. The instruction sequence.
ADDC
DA

A,R3
A

will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10111110) in the Accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the Accumulator to the value 24H
(OOI00I00B), indicating "the packed BCD digits of the decimal number 24, the low-order two
digits of the decimal sum of 56, 67, and the carry-in. The carry flag will be set by the Decimal
Adjust'instruction, indicating that a decimal overflow occurred. The true sum 56, 67, and "1 is
124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumulator
initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD

A,#99H

DA

A

will leave the carry set and 29H in the Accumulator, since 30
byte of the sum can be interpreted to mean 30 - 1 = 29.

Bytes:
Cycles:
Encoding:
Operation:

I1 1 0 1

0 1 0 0

DA
-contents of Accumulator are BCD
IF
[[(A3-O) > 9] V [(AC) = III
THEN(A3_0) +- (A3-0) + 6
AND
IF

[[(A7-4) > 9] V [(C) =
THEN (A7-4) +- (A7-4)

III

+

6

9-36

+

99 = 129. The low-order

intJ
DEC

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

byte
Function:

Description:

Decrement
The variable indicated is decremented by 1. An original value of DOH will underflow to OFFH.
No flags are affected. Four operand addressing modes are allowed: accumulator, register,
direct, or register-indirect. .
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.

Example:

°

Register contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain DOH
and 4OH, respectively. The instruction sequence,
DEC

@RO

DEC

RO

DEC

@RO

will leave register
3FH.

DEC

°

set to 7EH and internal RAM locations 7EH and 1FH set to OFFH and

A
Bytes:
Cycles:
Encoding:
Operation:

DEC

_O_O_O_..L.0_ 1_ O
_ 0--l

L...I

DEC
(A) +- (A) - 1

Rn
Bytes:
Cycles:
Encoding:
Operation:

I °°°1

1 rr r

DEC
(Rn) +- (Rn) - 1

9-37

inter
DEC

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

direct
Bytes:

2

Cycles:
Encoding:
Operation:

DEC

1 000 1

DEC
(direct) -

o1

0.1

direct address

(direct) - 1

@RI
Bytes:
Cycles:
Encoding:
Operation:

1 000 1

DEC
«Ri» -

o 11

«Ri» - 1

DIV AB
Function:
Description:

Divide
DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit
integer in register B. The Accumulator receives the integer part of the quotient; register B
receives the integer remainder. The carry and OV flags will be cleared.

Exception: if B had originally contained OOH, the values returned in the Accumulator and Bregister will be undefined and the overflow flag will be set. The carry flag is cleared in any
case.
Example:

The Accumulator contains 251 (OFBH or 1111101lB) and B contains 18 (l2H or 0OOI00lOB).
The instruction,

DIV AB
will leave 13 in the Accumulator (ODH or 0000llOlB) and the value 17 (11H or 00010001B) .
in B, since 251 = (13 X 18) + 17. Carry and OV will both be cleared.
Bytes:
Cycles:
Encoding:
Operation:

4

11

0 0 0

DIV
(Ah5-8 _
(Bh.o

0 1 0 0

I·

(A)/(B)

9-38

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

DJNZ

< byte> , < rel-addr >
Function:

Description:

Decrement and Jump if Not Zero
DJNZ decrements the location indicated by 1, and branches to the address indicated by the
second operand if the resulting value is not zero. An original value of OOH will underflow to
OFFH. No flags are affected. The branch destination would be computed by adding the signed
relative-displacement value in the last instruction byte to the PC, after incrementing the PC to
the first byte of the following instruction.
The location decremented may be a register' or directly addressed byte.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

Internal RAM locations 40H, SOH, and 60H contain the values 01H, 70H, and ISH, respectively. The instruction sequence,
DJNZ 40H,LABEL_l
DJNZ 50H,LABEL_2
DJNZ 60H,LABEL_3
will cause a jump to the instruction at label LABEL_2 with the values OOH, 6FH, and ISH in
the three RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times,
or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction.
The instruction sequence,
TOGGLE:

R2,#8
P1.7
R2,TOGGLE

MOV
CPL
DJNZ

will toggle Pl.7 eight times, causing four output pulses to appear at bit 7 of output Port 1.
Each pulse will last three machine cycles; two for DJNZ and one to alter the pin.
DJNZ

Rn,rel
Bytes:

2

Cycles:

2

Encoding:

L.1_1_1_0_1-,-_1_r_r_r..J

Operation:

DJNZ
(PC) +- (PC) + 2
(Rn) +- (Rn) - 1
IF (Rn) > 0 or (Rn) < 0
THEN
(PC) +- (PC)

'I

reI. address

+ rei

9-39

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

DJNZ

direct,rel
Bytes:

3

Cycles:

2

Encoding:
Operation:

I1 1 0 1

0 1 0 1

direct address

reI. address

DJNZ
(PC) - (PC) + 2
(direct) - (direct) - 1
IF (direct) > 0 or (direct) < 0
THEN
(PC) - (PC) + rei

INC


Function:

Description:

Increment
INC increments the indicated variable by 1. An original value ofOFFH will overflow to OOH.
No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

Register 0 contains 7EH (011 11 11 lOB). Internal RAM locations 7EH and 7FH contain OFFH
and 4OH, respectively. The instruction sequence,
INC @RO
INC RO
INC @RO
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) OOH and 4lH.

INC

A
Bytes:
Cycles:
I

I

Encoding:

I0

Operation:

INC
(A) -

0 0 0

(A)

I

0 1 0 0

+

1

9-40

inter
INC

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Rn
Bytes:
Cycles:
Encoding:
Operation:

INC

I 00 0 0 I 1 r r r
INC
(Rn)

~

+

(Rn)

1

direct
Bytes:

2

Cycles:
Encoding:
Operation:

INC

I 0 000 I o 1 0 1
INC
(direct)

~

(direct)

direct address

+

@Ri
Bytes:
Cycles:
Encoding:
Operation:

INC

I 000 0 I 011
INC
«Ri» ~ «Ri»

+

DPTR
Function:
Description:

Increment Data Pointer
Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an
overflow of the low-order byte of the data pointer (DPL) from OFFH to OOH will increment
the high-order byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.

Example:

Registers DPH and DPL contain 12H 'and OFEH, respectively. The instruction sequence,
INC
INC
INC

DPTR
DPTR
DPTR

will change DPH and DPL to 13H and OlH.

'Bytes:
Cycles:
Encoding:
Operation:

2

I1 0 1 0
INC
(DPTR)

~

0 0 1 1

(DPTR)

+

1
9-41

intJ

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

JB blt,rel
Function:

Jump if Bit set

Description:

If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the third instruction byte to the PC, after incrementing the PC to the first byteofthe next
instruction. The bit tested is not modified. No flags are affected.

Example:

The data present at input port 1 is 110010 lOB. The Accumulator holds 56 (010101 lOB). The
instruction sequence,
JB

P1.2,LABELl

JB

ACC.2,LABEL2

will cause program execution to branch to the instruction at label LABEL2.
Bytes:

3

Cycles:

2

Encoding:
Operation:

JBC

I0 0 1 0

bit address

0 0 0 0

JB
(PC) - (PC) + 3
IF (bit) = 1
THEN
(PC) -

reI. address
/

(PC)

+

rei

bit,rel
Function:

Description:

Jump if Bit is set and Clear bit

If the indicated bit is one, branch to the address indicated; otherwise proceed with the next
instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed rehitive-displacement in the third instruction byte to the PC, after
incrementing the PC to the first byte of the next instruction. No flags are affected.

Note: When this instruction is used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example:

The Accumulator holds 56H (0 10 10 1l0B). The instruction sequence,
JBC ACC.3,LABELl
JBC ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2,
with the Accumulator modified to 52H (0 10 1OOlOB).

9-42

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

Bytes:

3

Cycles:

2

Encoding:

LI_o_o_o_-,---o_o_o_o--,

Operation:

mc

(PC) -_O_O_1_0...J

addr15-addrB

addr7-addrO

LCALL
(PC) ~ (PC) + 3
(SP) ~ (SP) + I
«SP» ~ (PC7-0)
(SP) ~ (SP) + I
«SP» ~ (PCI5-S)
(PC) ~ addrl5_0

addr16
Function:

Long Jump

Description:

LJMP causes an unconditional branch to the indicated address, by loading the high-order and
low-order bytes of the PC (respectively) with the second and third instruction bytes. The
destination may therefore be anywhere in the full 64K program memory address space. No
flags are affected.
.

Example:

The label "JMPADR" is assigned to the instruction at program memory location 1234H. The
instruction,
UMP

JMPADR

at location 0123H will load the program counter with 1234H.
Bytes:

3

Cycles:

2

Encoding:

1

Operation:

LJMP
(PC) ~ addft5_0

° °0·1 °° °
0

1

addr15-addrB

9-47

addr7 -addrO

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MOV

< dest-byte> , < src-byte >
Function:

Description:

Move byte variable
The byte variable indicated by the second operand is copied into the location specified by the
first operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and destination
addressing modes are allowed.

Example:

Internal RAM location 30H holds 40H. The value of RAM location 40H is IOH. The data
present at input port I is 1100 10 lOB (OCAH).
MOY
MOY
MOY
MOY
MOY
MOY

;RO <= 30H
;A <= 40H
;Rl <= 40H
;B <= lOH
;RAM (40H) < = OCAH
;P2 #OCAH

RO,#30H
A,@RO
Rl,A
B,@Rl
@Rl,PI
P2,PJ

leaves the value 30H in register 0, 40H in both the Accumulator and register 1, lOR in register
B, and OCAR (llOOIOIOB) both in RAM location 40R and output on port 2.

MOV A,Rn
Bytes:
Cycles:
Encoding:

11 1 1 0

Operation:

MOY
(A) -(Rn)

1 r r r

·MOV A,dlrect
Bytes:

2

Cycles:

o1

Encoding:

11 1 1 0

Operation:

MOY
(A) - (direct)

0 1

direct address

MOV A,ACC Is not a valid Instruction.

9-48

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MOV A,@Ri
Bytes:
Cycles:
Encoding:
Operation:

I1 1 1 0

o1

MOV
(A) -- «Ri»

MOV A, # data
Bytes:

2

Cycles:
Encoding:
Operation:

I0 1 1 1

o1 0

0

immediate data

MOV
(A) -- #data

MOV Rn,A
Bytes:
Cycles:
Encoding:
Operation:

I 1 111

1 r r r

MOV

(Rn) -- (A)

MOV Rn,direct
Bytes:

2

Cycles:

2

Encoding:
Operation:

I 1 010

1 r r r

direct addr.

MOV

(Rn) -- (direct)

MOV Rn, # data
Bytes:

2

Cycles:
Encoding:
Operation:

1 01

11

1 r r r

immediate data

MOV
(Rn) -- #data

9-49

inter
MOV

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

dlrect,A
Bytes:

2

Cycles:

MOV

MOV

MOV

11 1 1

Operation:

MOV
(direct) +- (A)

0 1

I

direct address

direct,Rn
Bytes:

2

Cycles:

2

Encoding:

11 000

Operation:

MOV
(direct) +- (Rn)

1 r r r

direct address

dlrect,direct
Bytes:

3

Cycles:

2

o1

Encoding:

1 1 000

Operation:

MOV
(direct) +- (direct)

0 1

dir. addr. (src)

dir. addr. (dest)

direct,@Ri
Bytes:

2

Cycles:

2

Encoding:

Operaiiuii:

1 1 000

011

direct addr.

1I.'1"'\.T.7

IVIVY

(direct) +MOV

o1

Encoding:

«Ri»

direct,#data
Bytes:

3

Cycles:

2

Encoding:
Operation:

I· 0 .1

o1

0 1

direct address

MOV
(direct) +- #data

9-50

immediate data

inter
MOV

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

@Ri,A
Bytes:
Cycles:

MOV

MOV

Encoding:

I111

Operation:

MOV
«Ri» ~ (A)

011

@RI,dlrect
Bytes:

2

Cycles:

2

Encoding:

I1 o1 0

Operation:

MOV
«Ri» ~ (direct)

011

direct addr.

@Ri,#data
Bytes:

2

Cycles:

MOV

Encoding:

101

Operation:

MOV
«RI»

o1
~

immediate data

#data

< dest·bit > , 
Function:

Move bit data

Description:

The Boolean variable indicated by the second operand is copied into the location specified by
the first operand. One of the operands must be the carry flag; the other may be any directly
addressable bit. No other register or flag is affected.

Example:

The carry flag is originally set. The data present at input Port 3 is llOOOlOlB. The data
previously written to output Port 1 is 35H (OOllOlOlB).
I

MOV pl.3,e
MOV e,P3.3
MOV p1.2,e
will leave the carry cleared and change Port 1 to 39H (OOlllOOlB).

9-51

inter
MOV

MOV

MOV

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

C,bit
Bytes:

2

Cycles:

. 1

Encoding:

11 010

Operation:

MOV
(C) +- (bit)

001 0

bit address

001 0

bit address

bit,C
Bytes:

2

Cycles:

2

Encoding:

1 1 001

Operation:

MOV
. (bit) +- (C)

DPTR,#data16
Function:

Description:

Load Data

Poin~er

with a 16-bit constant

The Data Pointer is loaded with the 16-bit constant indicated. The 16-bit constant is loaded
into the second and third bytes of the instruction. The second byte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16 bits of data at once.

Example:

The instruction,
MOV DPTR, # 1234H
will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.

Bytes:

3

Cycles:

2

Encoding:

11 0 0 1

0 0 0 0

immed. data 15-8

Operation:

MOV
(DPTR) +- #data15.0
DPH 0 DPL +- #data15_8 0 #data7.Q

9-52

immed. data7-0

inter
MOVC

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,@A+ 
Function:

Move Code byte

Description:

The MOVC instructions load the Accumulator with a code byte, or constant from program
memory. The address of the byte fetched is the sum of the original unsigned eight-bit Accumulator contents and the contents of a sixteen-bit base register, which may be either the Data
Pointer or the PC. In the latter case, the PC is incremented to the address of the following
instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may
propagate through higher-order bits. No flags are affected.

Example:

A value between 0 and 3 is in the Accumulator. The following instructions will translate the
value in the Accumulator to one of four values defined by the DB (define byte) directive.
REL_PC:

INC

A

MOVC A,@A+PC
RET
DB

66H

DB

77H

DB

88H

DB

99H

If the subroutine is called with the Accumulator equal to OlH, it will return with 77H in the
Accumulator. The INC A before the MOVC instruction is needed to "get around" the RET
instruction above the table. If several bytes of code separated the MOVe from the table, the
corresponding number would be added to the Accumulator instead ..

MOVC A,@A+DPTR
Bytes:
Cycles:
Encoding:
Operation:

MOVC

2

I1 0 0 1

0 0 1 1

MOVC
(A) +- «A) + (DPTR»

A,@A + PC
Bytes:
Cycles:

Encoding:
Operation:

2

I1 0 0 0

0 0 1 1

MOVC
(PC) +- (PC) + 1
(A) +- «A) + (PC»

9-53

inter
MOVX

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

 , < src-byte >
Function:

Description:

Move External
The MOVX instructions transfer data between the Accumulator and a byte of external data
,memory, hence the "X" appended to MOV. There are two types of instructions, differing in
whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of Rq or Rl in the current register bank provide an eight-bit
address multiplexed with data on PO. Eight bits are sufficient for external I/O expansion
decoding or for a relatively small RAM array. For somewhat larger arrays, any output port
pins can be used to output higher-order address bits. These pins would be controlled by an
, .output instruction preceding the MOVX.
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2
outputs the high-order eight address bits (the contents of DPH) while PO multiplexes the loworder eight bits (DPL) with data., The P2 Special Function Register retains its previous contents while the P2,output buffers are emitting the contents of DPH. This form is faster and
more efficient when accessing very large data arrays (up to 64K bytes), since no additional ,
instructions are needed to set up the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with its
high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to
, output high-order address bits to P2 followed by a MOVX instruction using RO or Rl.

Example:

An external 256 byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/
I/O/Timer) is connected to the 8051 Port O. Port 3 provides control lines for the external
RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and' 1 contain 12H and 34H.
Location 34H,of the external RAM holds the value 56H. The instruction sequence,
MOVX A,@Rl
MOVX

@RO,A

copies the value 56H into both the Accumulator and external RAM location 12H.

9-54

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

MOVX

A,@Ri
Bytes:
Cycles:

2

Encoding:

I 1 110

Operation:

MOVX
(A) - «Ri»

MOVX

001

A,@DPTR
Bytes:
Cycles:

2

Encoding:

I 1 110

Operation:

MOVX
(A) - «DPTR»

MOVX

0000

@Ri,A
Bytes:
Cycles:

2

Encoding:

I1 1 1 1

Operation:

MOVX
«Ri» -

MOVX

001

(A)

@DPTR,A
Bytes:
Cycles:

2

Encoding:

I 1 1 1 1 o0 0 0

Operation:

MOVX
(DPTR)-(A)

9-55

inter

MCS®-S1 PROGRAMMER'S GUIDE AND INSTRUCTION SET

NOP
Function:

No Operation

Description:

Execution continues at the following instruction. Other than the PC, no registers or flags are
affected.
.

Example:

It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A

simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must
be inserted. This may be done (assuming no interrupts are enabled) with the instruction
sequence,
CLR
NOP
NOP
NOP
NOP
SETB

P2.7

P2.7

Bytes:
Cycles:
Encoding:

1

Operation:

NOP
(pC)-(PC)

0 0 0 0 1- 0 0 0 0 1

+

MUL AB

Function:

Multiply

Description:

MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The
low-order byte of the sixteen-bit product is left inthe Accumulator, and the high-order byte in
B. If the product is greater than 255 (OFFH) the overflow flag is set; otehrwise it is cleared.
The carry flag is always cleared.

Example:

Originally the Accumulator holds the value 80 (50H). Register. B holds the value 160 (OAOH).
The instruction,
MUL AB
will give the product 12,800 (32ooH), so B is changed to 32H (ooIIOOlOB) and the Accumulator is cleared. The overflow flag is set, carry is cleared.

Bytes:
Cycles:

4

Encoding:

1 1 0 1 0

Operation:

MUL
(Ah-o (BhS-8

0 1 0 0

(A) X (B)

9-56

intJ
ORL

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

 
Function:

Description:

Logical-OR for byte variables
ORL performs the bitwise logical-OR operation between the indicated variables, storing the
results in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example:

If the Accumulator holds OC3H (l 100001 IB) and RO holds 55H (OlOlOIOIB) then the instruction,
ORL A,RO
will leave the Accumulator holding the value OD7H (1IOIOl1IB).
When the destination is a directly addressed byte, the instruction can set combinations of bits
. in any RAM location or hardware register. The pattern of bits to be set is determined by a
mask byte, which may be either a constant data value in the instruction or a variable computed
in the Accumulator at run-time. The instruction,
ORL, PI,#OOIIOOIOB
will set bits 5, 4, and I of output Port 1.

ORL

A,Rn
Bytes:
Cycles:
Encoding:
Operation:

I0 1 0 0

1 r r r

ORL
(A) ~ (A) V (Rn)

9-57

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

ORL A,dlrect
Bytes:

2

Cycles:
Encoding:
Operation:

I 0 1 00

o1 0

1

direct address

ORL
(A) -

(A) V (direct)

ORL A,@Ri
Bytes:
Cycles:
Encoding:

00
1 01

Operation:

ORL
(A) -

o1

(A) V

1 i

«Ri»

ORL A, # data
. Bytes:

2

Cycles:
Encoding:

I0 1 o0 I o 1 0 0

Operation:

ORL
(A) -

".

immediate data

I

(A) V #data

ORL dlrect,A
Bytes:

2

Cycles:
Encoding:
Operation:

I 0 1 00
ORL
(direct) -

001 0

direct address

(direct) V (A)

ORL direct, # data
Bytes:

3

Cycles:

2

Encoding:

1 01

Operation:

ORL

o0

(direct) -

001 1

direct addr.

(direct) V #data

9-58

immediate data

inter
ORL

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

C,
Function:

Description:

Example:

ORL

ORL

Logical-OR for bit variables
Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state·
otherwise. A slash ("I") preceding the operand in the assembly language indicates that the
logical complement of the addressed bit is used as the source value, but the source bit itself is
not affected. No other flags are affected.
Set the carry flag if and only if P1.0

=

1, ACC. 7 = 1, or OV

= 0:

MOV

C,P1.0

;LOAD CARRY WITH INPUT PIN PIO

ORL

C,ACC.7

;OR CARRY WITH THE ACC. BIT 7

ORL

C,/OV

;OR CARRY WITH THE INVERSE OF OV.

C,bit
Bytes:

2

Cycles:

2

Encoding:

1 1
1 01

Operation:

ORL
(C) -- (C) V (bit)

001 0

bit address

C,Ibit
_ Bytes:

2

Cycles:

2

Encoding:

I 1 010

Operation:

ORL
(C) -- (C) V (bit)

0000

bit address

9-59

intJ
POP

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

direct
Function:

Pop from stack.

Description:

The contents of the internal RAM location addressed by the Stack Pointer is read, and the
Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected.

Example:

The Stack Pointer originally contains the value' 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and OlH, respectively. The instruction sequence,
POP DPH
POP DPL
will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this
point the instruction,
POP SP
will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was
decremented to 2FH before being loaded with the value popped (20H).

Bytes:

2

Cycles:

2

Encoding:
Operation:

PUSH

_1_1_0_1-L_O_'_0_0_0---,

LI

direct address

POP
(direct) -+-- «SP»
(SP) -+-- (SP) - 1

direct
Function:

Push onto stack

Description:

The Stack Pointer is incremented by one. The contents of the indicated variable is then copied
into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected.

Example:

On entering an interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the
value 0123H. The instrnction sequence,
PUSH DPL
PUSH DPH
will leave the Stack Pointer set to OBH and store 23H and OlH in internal RAM locations
OAH and OBH, respectively.

Bytes:

2

Cycles:

2

Encoding:

11100

0000

Operation:

PUSH
(SP) -+-- (SP) + 1
«SP» -+-- (direct)

direct address

9-60

inter

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

RET
Function:

Return from subroutine

Description:

RET pops the high- and low-order bytes of the PC successively from the stack, decrementing
the Stack Pointer by two. Program execution continues at the resulting address, generally the
instruction immediately following an ACALL or LCALL. No flags are affected.

Example:

The Stack Pointer originally contains the value OBH. Internal RAM locations OAH and OBH
contain the values 23H and OlH, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at
location 0123H.

Bytes:
Cycles:
Encoding:
Operation:

2

I0

0 1 0

0 0 1 0

RET
(PCIS-S) +- «SP»
(SP) +- (SP) - 1
(PC7-0) +- «SP»
(SP) +- (SP) - 1

RETI
FunctIon:

Return from interrupt

Description:

RETI pops the high- and low-order bytes of the PC successively from the stack, and restores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed. The Stack Pointer is left decremented by two. No other registers are affected; the
PSW is not automatically restored to its pre-interrupt status. Program execution continues at
the resulting address, which is generally the instruction immediately after the point at which
the interrupt request was detected. If a lower- or same-level interrupt had been pending when
the RETI instruction is executed, that one instruction will be executed before the pending
interrupt is processed.

Example:

The Stack Pointer originally contains the value OBH. An interrupt was detected during the
instruction ending at location 0122H. Internal RAM locations OAH and OBH contain the
values 23H and OlH, respectively. The instruction,
RET!

will leave the Stack Pointer equal to 09H and return program execution to location 0123H.

Bytes:
Cycles:
Encoding:
Operation:

2
,-1_O_O
_ _~_O_O_1_0--,
RET!
(PCIS-S) +- «SP»
(SP) +- (SP) - 1
(PC7-0) +- «SP»
(SP) +- (SP) - 1

9-61

inter

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

RL A
Function:
Description:
Example:

Rotate Ac.cumulator Left
The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0
position. No flags are affected.
The Accumulator holds the value OC5H (1IOOOlOlB). The instruction.

RLA
leaves the Accumulator holding the value 8BH (IOOOlOllB) with -the carry unaffected.
Bytes:
Cycles:
Encoding:
Operation:

RLC

I °0 1 0

0 0 1 1

RL
(An + I) - (An)
(AO) - (A7)

n

= 0 - 6

A
Function:

Rotate Accumulator Left through the Carry flag

Description:

The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit
7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No
other flags are affected.
.

Example:

The Accumulator holds the value OC5H (1IOOOlOlB). and the carry is zero. The instruction.
RLC

A

leaves the Accumulator holding the value 8BH (IOOOIOlOB) with the carry set.
Bytes:
Cycles:
Encoding:

LI_o_O_1_--,-_O_O_1_1....J

Operation:

RLC
(An + 1) - (An)
(AO) - (C)
(C) -(A7)

n

=

0 -:- 6

9-62

intJ
RR

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTIO!ll SET

A

Function:
Description:
Example:

Rotate Accumulator Right
The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7
position. No flags are affected.
The Accumulator holds the value OC5H (I 1000 10 lB). The instruction,
RR A
leaves the Accumulator holding the value OE2H (11 1000 lOB) with the carry unaffected.

Bytes:
Cycles:
Encoding:
Operation:

RRC

I0 0 0 0 I0 0 1 1
RR
(An) +- (An + I) n
(A7)+- (AO)

=

0 - 6

A

Function:
Description:

Example:

Rotate Accumulator Right through Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the right.
Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7
position. No other flags are affected.
The Accumulatorholds the value OC5H (llOOOlOlB), the carry is zero. The instruction,
RRC A
.leaves the Accumulator holding the value 62 (01 1000 lOB) with the c!lrry set.

Bytes:
Cycles:
Encoding:
Operation:

I0 0 0

1

RRC
(An) +- (An
(A7) +- (C)
(C) +- (AO)

O. 0 1 1

t

I) n = 0 - 6

9-63

inter
SETB

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET


Function:

Set Bit

Description:

SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressable bit. No other flags are affected.

Example:

The carry flag is cleared. Output Port I has been written with the value 34H (OOllOlOOB). The
instructions,
SETB C
SETB

Pl.O

wi11leave the carry flag set to 1 and change the data output on Port 1 to 3SH (OOllOlOlB).

SETB C
Bytes:
Cycles:
Encoding:

I110 1

Operation:

SETB
(C)~

001 1

1

SETB bit
Bytes:

2,

Cycles:
Encoding:

I1101

Operation:

SETB
(bit) +- 1

001 0

bit address

9-64

MCS®·51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

SJMP

rei
Function:

Short Jump

Description:

Program control branches unconditionally to the address indicated. The branch destination is
computed by adding the signed displacement in the second instruction byte to the PC, after
incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes
preceding this instruction to 127 bytes following it.

Example:

The label "RELADR" is assigned to an instruction at program memory location 0123H. The
instruction,
SJMP

RELADR

will assemble into location OlOOH. After the instruction is executed, the PC will contain the
value 0123H.
(Note: Under the above conditions the instruction following SJMP will be at 102H. Therefore,
the displacement byte of the instruction will be the relative offset (OI23H-OI02H) = 21H. Put
another way, an SJMP with a displacement ofOFEH would be a one-instruction infinite loop.)
Bytes:

2

Cycles:

2

Encoding:
Operation:

I1 0

0 0

SJMP
(PC) +- (PC)
. (PC) +- (PC)

0 0 0 0

+

reI. address

2

+ rei

,9-65

inter
SUBB

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,
Function:

Description:

Subtract with. borrow
SUBB subtracts the indicated variable and the carry flag together from the Accumulator,
leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed
for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction, so
the carry is subtracted from the Accumulator along with the source operand.) AC is set if a
borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6, but
not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is
subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or immediate.

Exarriple:

The Accumulator holds OC9H (llOOlOOlB), register 2 holds S4H (0 10 10 1OOB), and the carry
flag is set. The instruction,
SUBB

A,R2

will leave the value 74H (01 110100B) in the accumulator, with the carry flag and AC cleared
but OV set.
Notice that OC9H minus S4H is 7SH. The difference between this and the above result is due
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or multiple-precision subtraction, it should be explicitly cleared by a
CLR C instruction. .
SUBB

A,Rn
Bytes:
Cycles:

Encoding:

LI_1_0_0_1...J.._1_r_r_r..j

Operation:

SUBB
(A) ~ (A) - (C) - (Rn)

9-66

intJ
SUBB

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,direct
Bytes:

2

Cycles:

o1

Encoding:

1 1 001

Operation:

SUBB
(A) - (A) - (C) - (direct)

SUBB

0 1

direct address

A,@Ri
Bytes:
Cycles:

Encoding:

11 001

Operation:

SUBB
(A) - (A) - (C) - «Ri»

SUBB

011

A, # data
Bytes:

2

Cycles:

o1

Encoding:

11 001

Operation:

SUBB
(A) - (A) - (C) - #data

SWAP

0 0

immediate data

1

A
Function:

Description:

Example:

Swap nibbles within the Accumulator
SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator
(bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No
flags are affected.
The Accumulator holds the value OC5H (lJOOO101B). The instruction,
SWAP

A

leaves the Accumulator holding the value 5CH (0101 1100B).
Bytes:
Cycles:
Encoding:
Operation:

I1 1 0 0

0 1 0 0

SWAP
(A3-O) ~ (A7-4)

9-67

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

XCH

A,
Function:

Exchange Accumulator with byte variable

Description:

XCH loads the Accumulator with the contents of the indicated variable, at the same time
writing the original Accumulator contents to the indicated variable. The source/destination
operand can use register, direct; or register-indirect addressing.

Example:

RO contains the address 20H. The Accumulator holds the value 3FH (OOlllllIB). Internal
RAM location 20H holds the'value 75H (Ol1lOlOlB). The instruction,
XCH A,@RO
will leave RAM location 20H holding the values 3FH (0011 11 11 B) and 75H (Ol1lOlOlB) in
the accumulator.

XCH

A,Rn
Bytes:
Cycles:

XCH

Encoding:

1 1 100

Operation: ,

XCH
(A) -;. (Rn)

1, r r r

A,direct
Bytes:

2

Cycles:

XCH

o1

Encoding:

11 100

Operation:

XCH
(A) -;. (direct)

0 1

direct address

A,@Ri
Bytes:
Cycles:
Encoding:

1 1 100

Operation:

XCH
(A) -;.

011

«Ri»

9-68

inter
XCHD

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

A,@RI
Function:

Exchange Digit

Description:

XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing a
hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the
specified register. The high-order nibbles (bits 7-4) of each register are not affected. No flags
are affected.

Example:

RO contains the address 20H. The Accumulator holds the value 36H (001101 lOB). Internal
RAM location 20H holds the value 75H (OllIOlOIB). The instruction,
XCHD A,@RO
will leave RAM location 20H holding the value 76H (Oil 101 lOB) and 35H (OOllOlOlB) in the
Accumulator.

Bytes:
Cycles:
Encoding:
Operation:

XRL

_1_1_0_1--,-_0_1_1--,

LI

XCHD
(A3.Q) ~

«Ri3.Q»

,
Function:

Description:

Logical Exclusive-OR for byte variables
XRL performs the bitwise logical Exclusive-OR operation between the indicated variables,
storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the Accumulator, the source can use register, direct, register-indirect, or immediate addressing; when
the destination is a direct address, the source can be the Accumulator or immediate data.

(Note: When this illstruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.)
Example:

If the Accumulator holds OC3H (IlOOOOllB) and register 0 holds OAAH (10 1010 lOB) then
the instruction,
.

XRL A,RO
will leave the Accumulator holding the value 69H (OllOlOOlB).
When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a
variable computed in the Accumulator at run-time. The instruction,
XRL Pl,#OOllOOOlB
will complement bits 5, 4, and 0 of output Port 1.

9-69

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

XRL A,Rn
Bytes:
Cycles:
Encoding:
Operation:

'1 01 1 0

1 'r r r

XRL
(A) +- (A) ¥ (Rn)

XRL A,direct
Bytes:

2

Cycles:
Encoding:
Operation:

I0 1 1 0

o1

0 1

direct address

XRL
(A) +- (A) ¥ (direct)

XRL A,@RI
Bytes:
Cycles:
Encoding:

I0 1 1 0

Operation:

XRL

o1

1 i

(A) +- (A) ¥«Ri»

XRL A,#data
Bytes:

2

Cycles:
Encoding:
Operation:

1 01 1 0

o1

0 0

immediate data

XRL
(A) +- (A) ¥ #data

XRL dlrect,A'
Bytes:

2

Cycles:
Encoding:
Operation:

I0 1 1 0

001 0

direct address

XRL
(direct) +- (direct) ¥ (A)

9-70

I

inter
XRL

MCS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET

direct,#data
Bytes:

3

Cycles:

2

Encoding:
Operation:

I0 1 1 0
XRL
(direct)

 Do a. D. Go a.

Do D..

><><

270048-3

Pad

270048-2

Pin
Figure 2. MCS®-51 Connections
ing accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.

Port 1
Port 1 is an 8-bit bidirectional I/O port with internal
pullups. The Port 1 'output buffers can sink/source 4
LS TTL inputs. Port 1 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low wiii source
current (ilL on the data sheet) because of the internal pullups.

Port 2 also receives the high-order address bits during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.

Port 3
Port 3 is an 8·bit bidirectional I/O port with internal
pullups. The Port 3 output buffers can sink/source 4
lS TTL inputs. Port 3 pins that have 1s written to
them are pulled high by the internal pullups" and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low wiii source
current (ill on the data sheet) because of the pullups.

Port 1 also receives the low-order address bytes
during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.
In the 8032AH and B052AH, Port 1 pins P1.0 and
P1.1 also serve the T2 and T2EX functions, respectively.

Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:

Port 2
Port 2 is an 8~bit bidirectional 1/0 port with internal
pullups. The Port 2 output buffers can sink/source 4
lS TTL inputs. Port 2 pins that have 1s written to
them are pulled high by the internal pull ups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low wiii source
current (ill on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. Dur10-3

Port
Pin

Alternative Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
I!JTimer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

intJ
Note, however, that if the Security Bit in the EPROM
devices is programmed, the device will not fetch
code from any location in external Program Memory.

RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

This pin also receives the 21 V programming supply
voltage (VPP) during programming of the EPROM
parts.

ALE/PROG
Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
memory. This pin is also the program pulse input
(PROG) during programming of the EPROM parts.

XTAL1
Input to the inverting oscillator amplifier.

In normal operation ALE is emitted' at a constant
,rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

XTAL2
Output from the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAl2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator .
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155,"Oscillators for Microcontrollers."

Program Store Enable is the read strobe to external
Program Memory.
When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memo:
ry.

To drive the device from an external clock source,
XTAl1 should be grounded, while XTAl2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock Signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
.
be observed.

EA/VPP
External Access enable EA must be strapped to
VSS in order to enable any MeS-51 device to fetch
code froiT) external Program memory locations 0 to
OFFFH (0 to 1FFFH, in the 8032AH and 8052AH).
C2

r--11

, I

EXTERNAL
OSCILLATOR
SIGNAL

XTAL2

-L

---i

XTAL2

____--I

XTAL 1

D

XTAL1
Cl

"'---1 vss

vss

_L.

Cl , C2 ~ 30 pF ± 10 pF for Crystals
~ 40 pF ± 10 pF for Ceramic Resonators

270048-5

270048-4

Figure 4. External Drive Configuration

Figure 3. Oscillator Connections

10-4

inter

MCS®·51

"Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ...... O·C to 70·C

+ 150·C
+ 21.5V
0.5V to + 7V

Storage Temperature .......... - 65·C to

Voltage on EAIVpp Pin to Vss ... -0.5V to
Voltage on Any Other Pin to Vss .... -

Power Dissipation ..............•........... 1.5W

D.C. CHARACTERISTICS
Symbol

TA

=

,
0·Ct070·C·Vee

Parameter

=

5V ±10%;Vss

= ov

Min

Max

Units

-0.5

0.8

V

0

0.7

V

VIL

Input Low Voltage (Except EA Pin of
8751 H & 8751 H-8)

VIL1

Input Low Voltage to EA Pin of
8751 H & 8751H-8

VIH

Input High Voltage (Except XTAL2,
RST)

2.0

Vee

+ 0.5

VIH1

Input High Voltage to XTAL2, RST

2.5

Vee

+ 0.5

VOL

Output Low Voltage (Ports 1, 2, 3)"

VOL1

Output Low Voltage (Port 0, ALE, PSEN)*
8751 H, 8751 H-8
All Others

Test Conditions

V
V

XTAL1

0.45

V

IOL

0.60
0.45

V
V

IOL
IOL

0.45

V

VOH

Output High Voltage (Ports 1, 2, 3, ALE, PSEN)

2.4

V

VOH1

Output High Voltage (Port 0 in
External Bus Mode)

2.4

V

IlL

Logical 0 Input Current (Ports 1, 2, 3,
RST) 8032AH, B052AH
All Others

-800
-500

=

=

VSS

1.6 mA

= 3.2mA
= 2.4 mA
IOL = 3.2mA
IOH = -80/LA
IOH = -400/LA

VIN
VIN

= 0.45V
= 0.45V
=

Logical 0 Input Current to EA Pin of
B751 H & 8751 H-8 Only

-15

/LA
/LA
mA

1112

Logical 0 Input Current (XTAL2)

-3.2

mA

VIN

III

Input Leakage Current (Port 0)
B751 H & 8751 H-8
All Others

±100
±10

/LA
/LA

0.45
0-45

Logical 1 Input Current to EA Pin Qf
8751 H & 8751 H-B

500

/LA

IIH1

Input Current to RST to Activate Reset

500

/LA

VIN

Icc

Power Supply Current:
8031/8051
8031AH/8051AH
8032AH/B052AH
8751 H/8751 H-8

160
125
175
250

mA
mA
mA
mA

All Outputs
Disconnected;
EA = Vee

10

pF

Test freq

11L1

IIH

Cia

Pin CapaCitance

s

s

0.45V
VIN
VIN

< (Vee

=

s

s

Vee
Vee

- 1.5V)

1 MHz

• NOTE:

Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make .1-to-O
transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may
exceed o.av. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.

10-5

inter

MCS®·51

A.C. CHARACTERISTICS TA

= O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;
load Capacitance for Port 0, ALE, and PSEN = 100 pF;
load Capacitance for All Other Outputs = 80 pF

Symbol

Parameter

1/TClCl
TlHll
TAVll
TllAX
TlLlV

Oscillator Frequency
ALE Pulse Width
Address Valid to ALE low
Address Hold after ALE low
ALE low to Valid Instr In
8751H
All Others
ALE low to PSEN low
PSEN Pulse Width
8751H
All Others
PSEN Low to Valid Instr In
8751H
All Others
Input Instr Hold after PSEN
Input Instr Float after PSEN
PSEN to Address Valid
Address to Valid Instr In
8751H
All Others
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
RD low to Vafid Data In
Data Hold after RD
Data Float after RD
ALE low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR low
Data Valid to WR Transition
8751H
All Others
Data Valid to WR High
Data Hold after WR
AD low to Address Float
RD or WR High to ALE High
8751H
All Others

TLLPl
TPLPH

TPLIV

TPXIX
TPXIZ
TPXAV
TAVIV

TPLAZ
TRLRH
TWlWH
TRLDV
TRHDX
TRHDZ
TllDV
TAVDV
TllWl
TAVWL
TQVWX

TQVWH
TWHQX
TRlAZ
TWHlH

Variable Oscillator
Min
Max

12 MHz Oscillator
Min
Max

3.5
2TClCl-40
TClCl-40
TClCl-35

127
43
48
183
233

Units

12.0

MHz
ns
ns
ns

4TClCl-150
4TClCl":'100

58

TClCL-25

ns
ns
ns

190
215

3TClCl-60
3TClCl-35

ns
ns
3TClCL-150
3TCLCl-'125

100
125
0

0
63

TClCL-20

75

TCLCl-8
5TCLCL-150
5TClCl-115

267
302
20

20
6TClCL-100
6TClCL-100

400
400

5TCLCL-165

252
0

0
97
517
585
300

200
203

2TCLCL-70
8TCLCl-150
3TCLCl-50
' 4TClCL -130

9TCLCl-165
3TClCL+50

TClCL-70
TClCL-60
7TCLCL-150
TClCl-50

13
23
433
33
20
33
43

133
123

NOTE:
'This table does not include the B751-BAC. characteristics (see next page).

10-6

TClCL-50
TClCL-40

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

20

ns
ns
ns
ns
ns

TClCl+50
TCLCL+40

ns
ns

intJ

MCS®·51

This Table is only for the 8751H·8

A.C. CHARACTERISTICSTA

= O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF

Symbol

Parameter

8 MHz Oscillator
Min

Max

Variable Oscillator
Min

Max

3.5

8.0

Units

1/TCLCL

Oscillator Frequency

TLHLL

ALE Pulse Width

210

2TCLCL-40

ns

TAVLL

Address Valid to ALE Low

85

TCLCL-40

ns

TLLAX

Address Hold after ALE Low

90

TLLlV

ALE Low to Valid Instr In

TLLPL

ALE Low to PSEN Low

100

TCLCL-25

TPLPH

PSEN Pulse Width

315

3TCLCL-60

TPLIV

PSEN Low to Valid Instr In

TPXIX

Input Instr Hold after PSEN

TPXIZ

Input Instr Float after PSEN

TPXAV

PSEN to Address Valid

TAVIV

Address to Valid Instr In

TCLCL-35

ns

TCLCL-20

ns

5TCLCL-150

ns

20

ns

TCLCL-8

117
475

ns
ns

0
105

ns
ns

3TCLCL-150

225
0

ns·
4TCLCL-150

350

MHz

ns

TPLAZ

PSEN Low to Address Float

TRLRH

RD Pulse Width

650

TWLWH

WR Pulse Width

650

TRLDV

AD Low to Valid Data In

TAHDX

Data Hold after RD

TRHDZ

Data Float after RD

180

2TCLCL-70

ns

20
6TCLCL-100

ns

6TCLCL-100

0

ns
5TCLCL-165

460

ns
ns

0

TLLDV

ALE Low to Valid Data In

850

8TCLCL-150

ns

TAVDV

Address to Valid Data In

960

9TCLCL-165

ns

TLLWL

ALE Low to RD or WR Low

325

3TCLCL+50

ns

TAVWL

Address to RD or WR Low

370

TQVWX

Data Valid to WA Transition

TQVWH

Data Valid to WR High

TWHQX

Data Hold after WR

TRLAZ

RD Low to Address Float

TWHLH

AD or WR High to ALE High

425

3TCLCL-50
4TCLCL-130

ns

55

TCLCL-70

ns

125

7TCLCL-150

ns

TCLCL-50

75
20
75

175

10-7

TCLCL-50

ns
20

ns

TCLCL+50

ns

inter

MCS®-S1

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE

PORTO

PORT 2

270048-6

10-8

inter

MCS®·51

EXTERNAL DATA MEMORY READ CYCLE

ALE

1 - - - - - T L L O y ------<~

PORTO

PORT 2

P2.0-P2.7 OR A8-A1S FROM DPH

A8-A 15 FROM PCH

270048-7

EXTERNAL DATA MEMORY WRITE CYCLE
I+--~

TWHLH

T,LHLL

ALE

TLLWL-<~·"o----TWLWH---"""'~

Tavwx
I+-_I-':':;;'~ 1--+---TaVWH----~

PORTO

PORT 2

DATA OUT

P2.0-P2.7 OR A8-Ais FROM DPH

A8-A1S FROM PCH

270048-8

10-9

inter
SERIAL PORT TIMING-SHIFT REGISTER MODE
= O·C to 70·C; VCC = 5V ±10%; VSS = OV;

Test Conditions: TA
Symbol

12 MHz Oscillator

Parameter

Min
TXLXL

Serial Port Clock Cycle Time

Max

Load Capacitance

=

80 pF .

Variable Oscillator
Min

Units

Max

1.0

12TCLCL

,...s
ns

TQVXH

Output Data Setup to Clock Rising
Edge

700

1OTCLCL -133

TXHQX

Output Data Hold after Clock
Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold after Clock Rising
Edge

0

0

ns

TXHDV

Clock Rising Edge to Input Data
Valid

700

1OTCLCL -133

ns

..

SHIFT REGISTER TIMING WAVEFORMS

I

1-4-'OVI!H+1 ~UHQII
-------r\----~X

~

WAITE TO SBUf

I·

X~~~X~___JX~__~X~~-JX~·---JX~--~7

..
j
I
""D' --l I-""D'

t
SETlI

t

~

SET AI

ClUA __ r

270048-9

10-10

inter

MCS®-51

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TClCl

Oscillator Frequency (except 8751 H-8)
8751H-8

3.5
3.5

12
8

MHz
MHz

TCHCX

High Time

20

TClCX

low Time

20

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

ns
ns

EXTERNAL CLOCK DRIVE WAVEFORM

I.------TCLCL

-------<~

270048-10

A.C. TESTING INPUT, OUTPUT WAVEFORM

2.4=X >
20

TEST POINTS

045

0.8

<

2.0

)C

08

270048-11
A.C. Tesling: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".

10-11

MCS®-51

EPROM CHARACTERISTICS
Table 3 EPROM Programming Modes
. EA
. PSEN
P2.7
ALE

Mode

RST

P2.6

P2.S

P2.4

Program
Inhibit

1

0

O·

VPP

1

0

0
0

1
1

X

1

0

Verify

1
1

1

Security Set

1

0

O·

VPP

0
1

0
1

X
X
X
X

X
X
X
X

NOTE.

"VPP" = + 21V ± 0.5V
·ALE is pulsed low for 50 ms.

"1" = logic high for that pin
"0" = logic low for that pin

"X" = "don't care"

Programming the EPROM
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.0-P2.3 of Port 2, while the code byte to be
programmed into that location is applied to Port o.
other Port 2 pins, and RST, PSEN, and EA
should be held at the "Program" levels indicated in
Table 3. ALE is pulsed low for 50 ms to program the
code byte into the addressed EPROM location. The
setup is shown in Figure 5.

The

Normally EA is held at a logic high until just before
ALE is to be pulsed. Then EA is raised to + 21 V,
ALE is pulsed, and then EA is returned to a logic
high. Waveforms and detailed timing specifications
are shown in later sectio,ns of this data sheet.

+SV

Note that the EAIVPP pin must not be allowed to go
above the maximum specified VPP level of 21.5V for .
any amount of time. Even a narrow glitch above that
voltage level can cause permanent damage to the
device. The VPP source should be well regulated
and free of glitches.

Program Verification
If the Security Bit has not been programmed, the onchip Program Memory can be read out for verification purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port 1 and
pins P2.0-P2.3. The other pins should be held atthe
"Verify" levels indicated in Table 3. The contents of
the addressed location will come out on Port O. External pullups are required on Port 0 for this operation.
The setup, which is shown in Figure 6, is the· same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an activelow read strobe.
+5V

8751H

PH
P2.S
P2.6
P2.7

.--_---1

XTAL2

L--'+-H XTAL1
VSS

VSS

270048-12

Figure 5. Programming Configuration

270048-13

Figure 6. Program Verification
10-12

inter

MCS®-51

EPROM Security

+SV

X = "DON'T CARE"

The security feature consists of a "locking" bit which
when programmed denies electrical access by any
external means to the on-chip Program Memory.
The bit is programmed as shown in Figure 7. The
setup and procedure are the same as for normal
EPROM programming, except that P2.6 is held at a
logic high. Port 0, Port 1, and pins P2.0-P2.3 may be
in any state. The other pins should be held at the
"Security" levels indicated in Table 3.

VCC
PI
PO
P2.0P2.3
P2.4

X

8751H
ALE

ALEIPROG

P2.5
P2.6

Once the Security Bit h~s been programmed, it can
be cleared only by full erasure of the Program Memory. While it is programmed, the internal Program
Memory can not be read out, the device can not be
further programmed, and it can not execute out of
external program memory. Erasing the EPROM,
thus clearing the Security Bit, restores the device's
full functionality. It can then be reprogrammed.

P2.7

Eli

EA.'VPP

XTAL2
RST

VIHI

XTAL1
VSS

PSEN

270048-14

Figure 7. Programming the Security Bit

Erasure Characteristics
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.

The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm 2 . Exposing the
EPROM to an ultraviolet lamp of 12,000 /kW/cm 2
rating for 20 to 30 minutes, at a distance of about 1
inch, should be sufficient.
Erasure leaves the array in an all 1s state.

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
= 21°C to 27°C; VCC = 5V ±10%; VSS = OV

TA

Symbol

Parameter
Programming Supply Voltage
Programming Supply Current

Min
20.5

Max
21.5
30

Units
V
mA

4

6

MHz

VPP
IPP
1/TCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG Low

48TCLCL

TGHAX
TDVGL
TGHDX

Address Hold after PROG
Data Setup to PROG Low

48TCLCL
48TCLCL
48TCLCL

TEHSH

Data Hold after PROG
P2.7 (ENABLE) High to VPP

TSHGL

VPP Setup to PROG Low

10

TGHSL

10

TGLGH

VPP Hold after PROG
PROGWidth

TAVQV

Address to Data Valid

TELQV

ENABLE Low to Oata Valid
Data Float after ENABLE

TEHQZ

48TCLCL

45

/ks
55
48TCLCL
48TCLCL

0

10-13

48TCLCL

/ks
ms

inter

MCS@·51

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

Pl.0-fll.7
P2.0-fl2.3

VERIFICATION

ADDRESS

ADDRESS

-

PORTO

TAVGL

~

'LE/PROG

DATA OUT

I- _

.• _TGHDX
I-

TGHAX

,~
TSHGL

TGHSL

TGLGH
21V:t .SV

~

\

TTL HIGH

TTL HIGH

TTL HIGH

, --

TEHSH

IP2.7
(ENABLE)

"\.

/

_TAVQV

DATA IN
TDVGL

Ei./vpp

PROGRAMMING

TELQV_

J

_TEHQZ

J

270048-15
For programming conditions see Figure 5.

For verification conditions see Figure 6.

10-14

8051AHP
MCS®-51 FAMILY
8-BIT CONTROL-ORIENTED MICROCONTROLLER
WITH PROTECTED ROM
•

High Performance HMOS Process

• .Boolean Processor

•

Internal Timers/Event Counters

•

Bit-Addressable RAM

•

2-Level Interrupt Priority Structure

•

•

32 I/O Lines (Four 8-Bit Ports)

Programmable Full Duplex Serial
Channel

•

4K Program Memory Space

•

111 Instructions (64 Single-Cycle)

•

• .Protection Feature Protects ROM Parts
Against Software Piracy

•

4K Data Memory Space*
*Expandable to 64K
Available in 40 Pin Plastic and CERDIP
Packages
(See Packaging Outlines and Dimensions Order #231369)

The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instructions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
MCS-51 HMOS
Family Device

8051AH
8051AHP

Internal Memory
Program

Data

4Kx 8 ROM
4Kx8 ROM

128 x 8 RAM
128 x 8 RAM

Timers!
Event Counters

Interrupts

2 x 16-Bit
2 x 16-Bit

5
5

The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
to 4K.

10-15

September 1987
Order Number: 270279-002

8051AHP

P2o-P21

PQ O-PO 1

Yee

r --- - -- - ---~tttt;-

rl±!t~-

- - ----------,

~

I
I
I

I

I
I
I
I

.tiI

I

I
I
I

I
I

I
I
I
I

I
I
I

I
I
I
I
I

I
I
I

I

"E.

I r-----,,----,

ALE

P3.0-P37

PI.D-P1.1

270279-1

Figure 1. MCS®·51 Block Diagram
Port 0 is also the multiplexed low·order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups v-when emitting 1s and can SOUiC6 and
sink a LS TTL inputs.

PIN DESCRIPTIONS

Vee
Supply Voltage.

Circuit ground.

Port 0 also receives the code bytes during programming of the EPROM parts, and outputs the code
bytes during program verification of the ROM and
EPROM parts. External pullups are required during
program verification.

Port 0

Port 1

Port 0 is an a-bit open drain bidirectional 1/0 port. As
an output port each pin can sink a LS TTL inputs.

Port 1 is an a-bit bidirectional I/O port with internal
pullups. The Port 1 output buffers can sink source 4
LS TTL inputs. Port 1 pins that have 1s written to

Vss

Port 0 pins that have 1s written to them float, and in
that state can be used as high-impedance inputs.

10-16

intJ

8051AHP

P1.0
Pl.l
P1.2
P1.3
Pl.4
P1.S
Pl.6
P1.7
RST
RXD P3.0
TXD P3.1
INTO P3.2
INTI P3.3
TO P3.4
TI P3.S
WR P3.6
Rii P3.7
XTAL2
XTALI
VSS

vee
PO.O ADO
PO.l ADI
PO.2 AD2
PO.3 AD3
PO.4 AD4
PO.S ADS
PO.6 AD6
PO.7 AD7
EAlVpp
ALE'PROG
PSEN
P2.7 AIS
P2.6A14
P2.S A13
P2.4 A12
P2.3 Al1
P2.2 Al0
P2.1 A9
P2.0 AS

10
11
12
13

270279-2

Pin
Figure 2. MCS®-51 Connections
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.

Port 2
Port 2 is an S-bit bidirectional I/O port with internal
pullups. The Port 2 output buffers can sink/source 4
LS TTL inputs. Port 2 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IlL on the data sheet) because of the internal pullups.

Port 3
Port 3 is an S-bit bidirectional I/O port with internal
pullups. The Port 3 output buffers can sink/source 4
LS TTL inputs. Port 3 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IlL on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
'addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. Bits
P2.4 through P2.7 are forced to 0, effectively limiting
external Data and Code space to 4K each in the
S051AHP during external accesses'. During accesses to external Data Memory that use S-bit addresses
(MOVX @Ri), Port 2 emits the contents of the P2
Special Function Register.
Port 2 also receives the high-order address bits during programming of the EPROM parts and during
program verification of the ROM and EPROM parts .
• Protection feature

10-17

Port
Pin

Alternative Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external'input)
WR (external data memory write strobe)
RD (external data memory read strobe)

B051AHP

RST

XTAL1

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

Input to the inverting oscillator amplifier.

XTAL2

ALE/PROG

Output from the inyerting oscillator amplifier.
Address Latch Enable output pulse for latching the
low byte of the' address during accesses to external
memory.

OSCILLATOR CHARACTERISTICS

In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillatbr, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrollers."

Program Store Enable is the read strobe to external
Program Memory.

To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle 'of the external clock Signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum ,and maximum
high and low times specified on the Data Sheet must
be observed.

When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.

EA/Vpp

EXTERNAL
OSCILLATOR ---...,.....f ,XTAL2
SIGNAL

External Access enable EA should be strapped to
Vee for internal program executions. EA must be
strapped to Vss in order to enable any MeS-51 device to fetch code from external Program memory
locations 0 to OFFFH.

~

C2

rl

T

I

XTAL1

....-...,.....f vss

XTAL2

..L

270279-5

0

Figure 4. External Drive Configuration
XTAL1
C1

DESIGN CONSIDERATION
vss

C1. C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators

270279-4

The 8051AHP cannot access external program or
Data memory above 4K. This means that the following instructions that use the Data Pointer only read/
write data at address locations below 4K:

MOVX A, @DPTR
MOVX @DPTR, A

Figure 3. Oscillator Connections

When the Data Pointer contains an address above
the 4K limit, those locations will not be accessed.
10-18

inter

8051AHP

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O'C to + 70'C
Storage Temperature .......... - 65'C to + 150'C
Voltage on EAlVpp Pin to Vss ... -0.5V to + 21.5V
Voltage on Any Other Pin to Vss .... -0.5V to + 7V
Power Dissipation .......................... 1.5W

D.C. CHARACTERISTICS
Symbol

TA

=

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

O'Cto +70'C;Vee

Parameter

=

5V ±10%;Vss

=

OV

Min

Max

Units

-0.5

0.8

V

Test Conditions

VIL

Input Low Voltage

VIH

Input High Voltage (Except XTAL2, RST)

2.0

Vee + 0.5

V

VIH1

Input High Voltage to XTAL2, RST

2.5

Vee + 0.5

V

XTAL1

VOL

Output Low Voltage (Ports 1, 2, 3)'

0.45

V

0.45

V

=

Vss

Vou

Output Low Voltage (Port 0, ALE, PSEN)*

VOH

Output High Voltage (Ports 1, 2, 3, ALE, PSEN)

2.4

V

VOH1

Output High Voltage (Port 0 in External Bus Mode)

2.4

V

IlL

Logical 0 Input Current

-500

p.A

IIL2

Logical 0 Input Current (XTAL2)

-3.2

mA

= 1.6 mA
= 3.2 mA
IOH = -80 p.A
IOH = - 400 p.A
VIN = 0.45V
VIN = 0.45V

III

Input Leakage Current (Port 0)

±10

p.A

0.45

IIH

Input Current to RST to Activate Reset

500

p.A

VIN

Icc

Power Supply Current

125

mA

All Outputs
Disconnected;
EA = VCC

CIO

Pin Capacitance

10

pF

Test freq

IOL
IOL

S;

<

VIN

S;

Vee

(Vee - 1.5V)

=

1 MHz

'NOTE:
Capacitive loading on Ports a and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port a and Port 2 pins when these pins make 1·to-0
transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.

10-19

8051AHP

A.C. CHARACTERISTICS TA

= O·Cto +70·C;Vcc = 5V ±10%;Vss = OV;
Load Capacitance for Port 0, ALE, and PSEN = 100 pF;
Load Capacitance for All Other Outputs = 80 pF

Symbol

Parameter

12 MHz Oscillator
Min

1/TCLCL

Oscillator Frequency

TLHLL

ALE Pulse Width

TAVLL
TLLAX
TLLlV

ALE Low to Valid Instr In

TLLPL

ALE Low to PSEN Low

58

TPLPH

PSENPulse Width

215

TPLIV

PSEN Low to Valid Instr In

Max

Variable Oscillator

Units

Min.

Max

"

3.5

12.0

MHz

127

2TCLCL-40

ns

Address Valid to ALE Low

43

TCLCL-40

ns

Address Hold after ALE Low

48

TCLCL-35

ns

TPXIX

Input Instr Hold after PSEN

TPXIZ

Input Instr Float after PSEN

4TCLCL-100

233
TCLCL-25
3TCLCL-35
125
0

TPXAV

PSEN to Address Valid

TAVIV

Address to Valid Instr In

TPLAZ

PSEN Low to Address Float

TALAH

AD Pulse Width

400

TWLWH

WA Pulse Width

400

TALDV

AD Low to Valid Data In

ns
3TCLCL-125

0

TCLCL.,...8

75
302
20

ns
ns

20

ns
ns

6TCLCL-100

0

ns

5TCLCL-115

6TCLCL-100

252

ns
ns

TCLCL-20

63

ns·
ns

ns
5TCLCL-165

0

ns

TAHDX

Data Hold after AD

TAHDZ

Data Float after AD

97

2TCLCL-70

ns

TLLDV

ALE Low to Valid Data In

517

8TCLCL-150

ns

TAVDV

Address to Valid Data In

585

9TCLCL-165

ns

TLLWL

ALE Low to AD or WA Low

200

3TCLCL+50

ns

TAVWL

Address to AD or WA Low

203

4TCLCL-130

ns

TOVWX

Data Valid to WA Transition

23

TCLCL-60

ns

TOVWH

Data Valid to WA High

433

7TCLCL-150

ns

TWHOX

Data Hold after WA

33

TCLCL-50

ns

.TALAZ

AD Low to Address Float

TWHLH

AD or WA High to ALE High

300

3TCLCL-50

20
43

123

10-20

TCLCL-40

ns

20

ns

TCLCL+40

ns

inter

8051AHP

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE

PORTO

PORT 2

270279-6

EXTERNAL DATA MEMORY READ CYCLE
""-_~TLHLL

ALE

f4-----TLLDY - - - - . - j
--I.---TRLRH

+----1

PORTO

I-~----TAYDY

PORT 2

------t

P2.0-P2.7 OR A8-A 15 FROM DPH

A8-A 15 FROM PCH

270279-7

8051AHP

EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH
ALE

TLLW·L--I~".""---TWLWH -----<~

TQVWX
~-'~--~~-+-----TQVWH------~

PORTO

PORT 2

DATA OUT

P2.0-P2.7 OR A8-A15 FROM DPH

A8-A15 FROM PCH

270279-8

10-22

inter

8051AHP

SERIAL PORT TIMING-SHIFT REGISTER MODE
= O·C to + 70·C; Vee = 5V ± 10%; Vss = OV;

Test Conditions: TA
Symbol

12 MHz Oscillator

Parameter

Min

Max

Load Capacitance

=

80 pF

Variable Oscillator
Min

Units

Max

TXLXL

Serial Port Clock Cycle Time

1.0

12TCLCL

,...s

TOVXH

Output Data Setup to Clock Rising
Edge

700

1OTCLCL -133

ns

TXHOX

Output Data Hold after Clock
. Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold after Clock Rising
Edge

0

0

ns

TXHDV

Clock Rising Edge to Input Data
Valid

700

1OTCLCL -133

ns

SHIFT REGISTER TIMING WAVEFORMS

'~fXLIL~

-------,

t"4-,QVIH ...

\
~

,

X
. I

WAITE TO SBUF

I""UT OA'..

1 ~TlHQ.

_____

""D' ~

I

j

X

X~

__~X~__~X~__~X~__~x~__~1
t

SET II

I-""D'

J~_J'~~

t

SET RI

CLEAR RI

270279-9

10-23

inter

8051AHP

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TClCl

Oscillator Frequency

3.5

12

MHz

TCHCX

High Time

20

ns

TClCX

low Time

20.

ns

TClCH

Rise Time

20

os

TCHCl

Fall Time

20

ns

EXTERNAL CLOCK DRIVE WAVEFORM

....- - - - T C l C l - - - - - . . - j

270279-10

. . .> < x=
u=x

A.C. TESTING INPUT, OUTPUT WAVEFORM
2.0

2.0

TEST POINTS

0.45

0.8

0.8

270279-11
A.C. Testing: Inputs are driven at 2.4V for a Logic "'1" and 0.45V
. for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".

Program Verification
The program verification test mode has been eliminated on the 8051 AHP. It is not possible to verify the
ROM contents using this mode, the way EPROM
programmers typically do. Also, the ROM contents
cannot be verified by a program executing out of
external program memory due to the restricted ad-dressing on the 8051AHP.

10-24

8031 AH/8051 AH
8032AH/8052AH
8751 H/8751 H-8
EXPRESS
•

Extended Temperature Range

•

Burn-In

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of O·C to 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40·C to + 85·C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125·C with Vee
guidelines in MIL-STD-883, Method 1015.

= 5.5V ± 0.25V, following

Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.

Electrical Deviations from Commercial
Specifications for Extended
Temperature Range
D.C. and A.C. parameters not included here are the
same as in the commercial temperature range data
sheets.

D_C. CHARACTERISTICS TA = -40·Cto + 85·C; Vee = 5V ±10%; Vss =
Symbol

Parameter

Min

Max

Unit

-0.5

0.75

V

ov
Test Conditions

VIL

Input Low Voltage

VIH

Input High Voltage (Except
XTAL2, RST)

lee

Power Supply Current:
8051AH,8031AH
8052AH, 8032AH
8751H,8751H-8

135
175
265

mA
mA
mA

All Outputs
Disconnected;
EA = Vee

Logic 0 Input Current (XTAL2)

-4.0

mA

Vin

IIL2

2.1

10-25

Vee

+ 0.5·

V

= 0.45V

October 1987
Order Number: 270007-002

intJ

MCS®·51 EXPRESS

Table 1. Prefix Identification
Prefix

Package Type

Temperature Rlmge

Burn·ln

P

plastic

commercial

no

D

cerdip

commercial

no

C

ceramic

commercial

no

N

PLCC

commercial

no

R

LCC

commercial

no

TP

plastic

extended

no

TO

cerdip

extended

no

TC

ceramic

extended

no

QP

plastic

.commercial .

yes

QD

cerdip

commercial

yes

QC

ceramic

commercial

yes

LP

plastic

extended

yes

LD

cerdip

extended

yes

LC

ceramic

extended

yes

Please note:
• Commercial temperature range is O·C to 70·C. Extended temperature range is .,..40·C to +85·C.
• Burn-in is dynamic, for a minimum time of 160 hours at 125·C, Vee = 5.5V ±0.25V, following guidelines in
MIL-STD-883 Method 1015 (Test Condition D).
• The following devices are not available in ceramic packages:
8051AH,8031AH
8052AH, 8032AH
• The following devices are not available in extended temperature range:
8751 H, 8751 H-8
Examples: P8031AH indicates 8031AH in a plastic package and specified for commercial temperature range,
without burn-in. LD8051 AH indicates 8051 AH in a cerdip package and specified for extended temperature
range with burn-in.

10-26

intJ

8751BH
SINGLE-CHIP 8-BIT MICROCOMPUTER
WITH 4K BYTES OF EPROM PROGRAM MEMORY

• Program Memory Lock

• Two 16·Bit Timer/Counters

• 128 Bytes Data Ram
• Quick Pulse Programming™ Algorithm
• 12.75 Volt Programming Voltage

•
•
•
•

• Boolean Processor
• 32 Programmable I/O Lines
PO.O- PO.7

5 Interrupt Sources
Programmable Serial Channel
64K External Program Memory Space
64K External Data Memory Space

P2.0-P2.7

....

r---------- ~
-:F
~~

Vss

~

-----------,

PSEN
ALE/1'IW1l

D/Vpp
RST

Pl.0-P1.7

P3.0-P3.7

270248-1

Figure 1. 8751BH Block Diagram

10-27

August 1987
Order Number: 270248-002

inter

8751BH

inputs, Port 1 pins that are externally being pulled
low will source current (I,L, on the data sheet) because of the internal pullups.

PIN DESCRIPTIONS

PLO
PLI
PL2
PL3
PL4
PLS
PL6
PL7
RESET
(RXD) P3.0
(TXD) P3.1
(INTO) P3.2
(iNTl) P3.3
(TO) P3.4
(Tl ) P3.S
(Wil) P3.6
(iID) P3.7

XTAL2
XTALI
VSS

Port 1 also receiveS! the low-order address bytes
during EPROM programming and program verification.

Vee
PO.O (ADO)
PO.l (AD1)
PO.2
PO.3
PO.4
PO.S
PO.6

(AD2)
(AD3)
(AD4)
(ADS)
(AD6)

Port 2: Port 2 is an 8-bit bidirectional liD port with
internal pull ups. The Port 2 output buffers can sinkl
source 4 LS TIL inputs. Port 2 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 2 pins that are externally being pulled
low will' source current (I,L, on the data sheet) because of the internal pullups.

PO.7 (AD7)
EA!VPP
ALE/PROG
PSEN
P2.7 (A1S)
P2.6 (AI4)

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory'that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullupswhen emitting 1s. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.

P2.S (AI3)
(AI2)

P2.4
P2.3
P2.2
P2.1

(All)
(Al0)

(A9)
P2.0 (AB)

Port 2 also receives the high-order address bits during EPROM programming and program verification.

270248-2

Figure 2. Pin Connections
Port 3: Port 3 is an 8-bit bidirectional liD port with

Vee: Supply voltage.

Vss: Circuit ground.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an output port each pin can sink 8 LS TIL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.

Port 0 is also the multiplexed low-order address and
data bus during' accesses to external Program and
Data Memorv. In this application it uses stronQ internal pullups when emitting 1s, and can source and
sink 8 LS TIL inputs.

internal pullups. The Port 3 output buffers can sinkl
source 4 LS TIL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port. 3 pins that are externally being pulled
low will source current (I,L, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the MCS®-51 Family, as listed below:

I::: IRXD (Sefi~li:~;~ia;:~unction
Pin

P3.1
P3.2
P3.3
P3.4
P3.5.
P3.6
P3.7

Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
Port 1: Port 1 is an 8-bit bidirectional liD port with

internal pull ups. The Port 1 output buffers can sinkl
source 4 'LS TIL inputs. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As

TXD (seriai output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
AD (external data memory read strobe)

RST: Reset input. A high on this pin for two machine

cycles while the oscillator is running resets the device.

10-28

inter

8751BH

ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. Thi~ pin is also the program
pulse input (PROG) during EPROM programming.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.

To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
be observed.

C2
I - - p - - - j XTAL2

PSEN: Program Store Enable is the Read strobe to
External Program Memory.

o

When the 8751 BH is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to External Data Memory.

I-_~--j

XTAL 1

t - - - - - - - - - I vss
270248-3
Cl, C2

EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to
fetch code from External Program Memory locations
OOOOH to OFFFH. Note, however, that if either of the
Lock Bits are programmed, EA will be internally
latched on reset.

= 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators

Figure 3_ Oscillator Connections

EXTERNAL
OSCILLATOR----j XTAL2
SIGNAL

EA should be strapped to Vee for internal program
executions.

-

This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming.

XTALl

XTAL 1: Input to the inverting oscillator amplifier.
270248-4

XTAL2: Output from, the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS

Figure 4. External Clock Drive Configuration

DESIGN CONSIDERATIONS

XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-Chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Applications Note AP-155, "Oscillators for Microcontrollers."

Exposure to light when the device is in operation
may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window
when the die is exposed to ambient light.

10-29

intJ

8751BH

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O·C to + 70·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on EAlVpp Pin to Vss .•. - 0.5V to + 13.0V
Voltage on Any Other Pin to Vss .. ;. -0.5V to + 7V
Power Dissipation ..•....................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)

• Notice: Stresses above those listed under '~bso­
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE Specifications contained within the
following tables are subject to change.

ADVANCE INFORMATION-8EE INTEL FOR DESIGN-IN INFORMATION
D.C. CHARACTERISTICS
Symbol

(TA = O·Cto +70·C;Vcc = 5V ±10%;Vss = OV)

Min

Max

Unit

V,L

Input Low Voltage (Except EA)

Parameter

-0.5

O.S

V

Test Conditions

V,L1

Input Low Voltage EA

Vss

0.7

V.

V,H

Input High Voltage
(Except XTAL2, RST, EA)

2.0

Vcc+ 0.5

V

V,H1

Input High Voltage XTAL2, RST

2.5

Vcc+ 0.5

V

V,H2

Input High Voltage to EA

4.5

5.5

V

VOL

Output Low Voltage
(Ports 1, 2 and 3)

0.45

V

IOL = 1.6 rnA (Note 1)

VOL1

Output Low Voltage
(Port 0, ALE/PROG, PSEN)

0.45

V

IOL = 3.2 rnA (Notes 1, 2)

VOH

Output High Voltage
(Ports 1, 2, 3, ALE/PROG and PSEN)

2.4

V

IOH = -SOtJoA

VOH1

Output High Voltage
(Port 0 in External Bus Mode)

2.4

V

IOH = - 4OO tJoA

I,L

Logical 0 Input Current
(Ports 1, 2, 3 and RST)

I'L1

XTAL1 = VSS

-1

rnA

Y,N = 0.45V

Logical 0 Input Current (EA)

-10

rnA

Y,N = VSS

I'L2

Logical 0 Input Current (XTAL2)

-3.2

rnA

V'N= 0.45 VXTAL1 = Vss

III

Input Leakage Current (Port 0)

±10

tJo A

I'H

Logical 1 Input Current (EA)

1

rnA

I'H1

Input Current to RST
to Activate Reset

500

tJo A

< Y,N < Vcc
4.5V < Y,N < 5.5V
Y,N < (Vcc - 1.5V)

Icc

Power Supply Current

175

rnA

All Outputs Disconnected

C,O

Pin Capacitance

10

pF

Test Freq = 1MHz

0.45

NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make 1·to-O transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALEI
PROG pin may exceed O.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch
with a Schmitt Trigger STROBE input.
2. ALE/PROG refers to a pin on the 8751BH. ALE refers to a timing signal that is output on the ALE/PROG pin.

10-30

inter

8751BH

A.C. CHARACTERISTICS (TA = O°C to + 70°C; Vee = 5V ± 10%; VSS = OV); Load Capacitance for
Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
ADVANCE INFORMATION-SEE INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol

Parameter

12 MHzOsc
Min

1/TCLCL

Max

Oscillator Frequency

Variable Oscillator
Min

Max

3.5

12.0

Units
MHz

TLHLL

ALE Pulse Width

127

2TCLCL-40

ns

TAVLL

Address Valid to ALE Low

43

TCLCL-40

ns

48

TLLAX

Address Hold After ALE Low

TLLlV

ALE Low to Valid Instruction In

TLLPL

ALE Low to PSEN Low

TPLPH

PSEN Pulse Width

TPLIV

PSEN Low to Valid Instruction In

TPXIX

Input Instr Hold After PSEN

TCLCL-35
233

ns
4TCLCL-100

ns

58

TCLCL-:-25

ns

215

3TCLCL-35

ns
3TCLCL-125

125
0

0

ns
ns

TPXIZ

Input Instr Float After PSEN

TPXAV

PSEN to Address Valid

TCLCL-20

TAVIV

Address to Valid Instruction In

302

5TCLCL-115

ns

TPLAZ

PSEN Low to Address Float

20

20

ns

63
TCLCL-8

75

ns
ns

TRLRH

RD Pulse Width

400

6TCLCL-100

ns

TWLWH

WR Pulse Width

400

6TCLCL-100

ns

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold After RD

252
0

5TCLCL-165
0

ns
ns

TRHDZ

Data Float After RD

97

2TCLCL-70

ns

TLLDV

ALE Low to Valid Data In

517

8TCLCL-150

ns

TAVDV

Address to Valid Data In

585

9TCLCL-165

ns

TLLWL

ALE Low to RD or WR Low

3TCLCL+50

ns

TAVWL

Address to RD or WR Low

TQVWX

Data Valid to WR Transition

TQVWH

200

300

3TCLCL-50

203

4TCLCL-130

ns

23

TCLCL-60

ns

Data Valid to WR High

433

7TCLCL-150

ns

TWHQX

Data Held After WR

33

TCLCL-50

ns

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

0
43

10-31

123

TCLCL-40

0

ns

TCLCL+40

ns

inter

8751BH

ALE

PORT 0

_ _J

---

PORT 2 _ _ _J

270248-5

External Program Memory Read Cycle

ALE

PSEN
i-----TLLDV

'I

- - - < - t - - - TRLRH -----+I

PORTO

INSTR. IN

PORT2

P2.0-P2.7 OR AB-A15 FROM DPH

AB-A 15 FROM PCH

270248-6

External Data Memory Read Cycle

\

ALE-{
-TLHLL-

....i-TWHLH

PSEN

1
~TLLWL

-

PORTO

PORT2

:::r
=>

TAVLL I--TLLAX-

,.

TWLWH

TQVWH

FRol~i~~ DPL

J

~
DATA OUT

I-TWHQX

K

AO-A7 FROM PCL

INSTR. IN

TAVWL
P2.0-P2.7 OR AB-A15 FROM DPH

AB-A 15 FROM PCH

270248-7

External Data Memory Write Cycle

10-32

infef

8751BH

SERIAL PORT TIMING -

SHIFT REGISTER MODE

TEST CONDITIONS (TA = O·C to + 70·C; Vee = 5V ± 10%; Vss = OV; Load Capacitance = 80 pF)
Symbol

12MHzOsc

Parameter

Min

Variable Oscillator

Max

Units

Max

Min

TXLXL

Serial Port Clock Cycle Time

1.0

12TCLCL

f-Ls

TOVXH

Output Data Setup to
Clock Rising Edge

700

1OTCLCL - 133

ns

TXHOX

Output Data Hold After
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

INSTRUCTION

I

0

1OTCLCL -133

700

2

4

3

5

ns

7

6

8

ALE

CLOCK

OUTPUT DATA

I

\

~j-TXHQX
0
IX
1 IX
2
X
j.TXHDV I:-IrTXHDX

3

X

4

X

5

X ·6 X

I

7

t

SET TI
WRITE TO SBUF
INPUT DATA - - - -......r.:'AL~,.....W:ALI~D.-""'Y::::ALI:-::D,.,..-I:';A':':'U:v-.r.:'~,....."\I:';~.-""'Y~,.,..-r.:':~
ALID
ALID
ALID
ALID

t

I

SET RI

CLEAR RI

270248-8

Shift Register Mode Timing Waveforms

_--TCLCL--~

ExternalClock Drive Waveforms

10·33

270248-9

8751BH

EXTERNAL CLOCK DRIVE
Symbol

Parameter

2.4=X

Min Max Units

1/TClCl Oscillator Frequency 3.5
TCHCX

AC TESTING INPUT/OUTPUT WAVEFORMS

12

MHz

High Time

20

ns

TClCX

low Time

20

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

.

0.45 V

Programming the EPROM

)C

2.0'

O.B

TEST POINTS

O.B

270248-10
AC inputs during testing are driven at 2.4V for a logic "1" and
0.45V for a logic "0". Timing measurements are made at 2.0V for
a logic "1" and 0.8V for a logic "0".

ns

EPROM CHARACTERISTICS

2.0

-

a

amount of time. Even narrow glitch above that voltage level can cause permanent damage to the device. The Vpp source should be well regulated and
free of glitches.

To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.0 - P2.3 of Port 2, while the code byte to be
programmed into that location is applied to Port O.
The other Port 2 and 3 pins, and RST, PSEN, and
EAIVpp should be held at the "Program" levels indicated in Table 3. AlE/PROG is pulsed low to program the code byte into the addressed EPROM location. The setup is shown in Figure 5.

AOOR.
OOOOH/orrrH

--+
--+

P3.6

87518H

P3.7

,..-......- - 1 XTAL 2

Normally EA~is held at a logic high-'!ntil just
before AlE/PROG is to be pulsed. Then EAIVpp is
raised to Vpp, AlE/PROG is pulsed low,and then
EAIVpp is returned to a valid high voltage. The voltage on the EAIVpp pin must be at the valid EAIVpp
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.

'--+--+-1 XTAL 1
Vss
270248-11

Figure 5. Programming the EPROM

Note that the EAIVpp pin must not be allowed to go
above the maximum specified Vpp level for any

10-34

8751BH

Table 3. EPROM Programming Modes
RST

PSEN

ALEI
PROG

EAI
Vpp

P2.7

P2.6

P3.6

P3.7

1

0

O'

Vpp

1

0

1

1

Verify Code Data

1

0

1

1

0

0

1

1

Program Encryption Table
Use Addresses 0-1 FH

1

0

O'

Vpp

1

0

0

1

1
1

0
0

O'
O'

Vpp
Vpp

1
1

1
1

1
0

1
0

MODE
Program Code Data

Program Lock
Bits (LBx)

x=1
x=2

NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"Vpp" = + 12. 75V ± 0.25V
• ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming™)

QUICK-PULSE PROGRAMMINGTM
ALGORITHM
The 8751 BH can be programmed using the QuickPulse Programming Algorithm for microcontrollers.
The features of the new programming method are a .
lower Vpp (12.75 volts as compared to 21 volts) and
a shorter programming pulse. It is possible to program the entire 4K Bytes of EPROM memory in less
than 13 seconds with this algorithm
To program the part using the new algorithm, Vpp
must be 12.75 ±0.25 Volts. ALE/PROG is pulsed
low for 100 ftseconds, 25 times. Then, the byte just
programmed may be verified. After programming,
the entire array should be verified. The Program
Lock features are programmed using the same
method, but with the setup as shown in Table 3. The
only difference in programming Lock features is that
the Lock features cannot be directly verified. Instead, verification of programming is by observing
that their features are enabled.

tents of the addressed location will come out on Port
O. External pullups are required on Port 0 for this
operation. (If the Encryption Array in the EPROM
has been programmed, the data present at Port 0
will be Code Data XNOR Encryption Data. The user
must know the Encryption Array contents to manually "unencrypt" the data during verify.)
The setup, which is shown in Figure 6, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
low read strobe.

ADDR.

PGM DATA
(USE 10K
PULLUPS)

OOOOH/OFFF

SEE
TABLE 3

8751BH

VIH
_P3.7

...--..---1

PROGRAM VERIFICATION
If the Lock Bits have not been programmed, the onchip Program Memory can be read out for verification .purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port 1 and
pins P2.0 - P2.3. The other pins should be held at
the "Verify" ,levels indicated in Table 3. The con-

10-35

XTAL 2

'--"'-+--IXTAL 1

VIHI

Vss

270248-12

Figure 6. Verifying the EPROM

inter

8751BH

PROGRAM MEMORY LOCK
The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against software piracy.

ENCRYPTION ARRAY
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NORed
(XNOR) with the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its
original, unmodified form.
It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.

LOCK BITS·
Also included in the,EPROM Program Lock scheme
are two Lock Bits which function as shown in Table

Erasing the EPROM also erases the Encryption Array and the Lock Bits, returning the part to full unlocked functionality.
To ensure proper functionality of the chip, the internally latched value of the EA pin must agree with its
external state.

ERASURE CHARACTERISTICS
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to anintegrated dose of at lease 15. W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 !J-W/cm rating for 20 to 30 minutes, at a distance of about 1
inch, should be sufficient.
Erasure leaves the array in an all 1s state.

4.
Table 4. Lock Bits and their Features
Lock Bits

Logic Enabled

LB1

LB2

U

U

Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)

P

U

MOVC instructions executed from
external program memory are
disabled from fetching code b~'!es
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled

P

P

Same as above, but Verify is also
disabled

U

P

Reserved for Future Definition

P = Programmed
U = Unprogrammed

10-36

inter

8751BH

ADVANCE INFORMATION-SEE INTEL FOR DESIGN-IN INFORMATION
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C, Vee = 5.0V ±10%, vss = OV)
Symbol

Units

Parameter

Min

Max

Vpp

Programming Supply Voltage

12.5

13.0

V

IPP

Programming Supply Current

50

mA

6

MHz

1/TCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG Low

48TCLCL

4

TGHAX

Address Hold After PROG

48TCLCL

TOVGL

Data Setup to PROG Low

48TCLCL

TGHDX

Data Hold After PROG

48TCLCL

TEHSH

P2.7 (ENABLE) High to Vpp

48TCLCL

TSHGL

Vpp Setup to PROG Low

10

TGHSL

Vpp Hold After PROG

10

TGLGH

PROGWidth

90

TAVQV

Address to Data Valid

48TCLCL

TELQV

ENABLE Low to Data Valid

48TCLCL

TEHQZ

Data Float After ENABLE

0

TGHGL

PROG High to PROG Low

10

J..Lsec
110

J..Lsec

48TCLCL
J..Lsec

VERIFICATION

PROGRAMMING
PI.O-PI.7
P2.0-P2.3

J..Lsec

-----{=:::!AO~D~R~ES~S~

ADDRESS
-TAVQV

PORT 0

.-----1{=~~~

DATA OUT

TDVGL
ALE/PROG

------,,1

)""I__

TELQVll'-_ _ _
P2.7

---

T_EH_Q_Z_ __

270248-13

EPROM Programming and Verification Waveforms

10-37

8052BH
SINGLE-CHIP 8-BIT MICROCOMPUTER
WITH FACTORY MASK-PROGRAMMABLE ROM
8032BH
.
SINGLE-CHIP 8-BIT CONTROL-ORIENTED
CPU WITH RAM AND I/O
8032BH-ROMless
8052BH-8K Bytes of Factory Mask-Programmed ROM
•
•
•
•

• Programmable Serial Channel
• Separate Transmit/Receive Baud Rate
Capability

256 Bytes Data Ram
Boolean Processor
32 Programmable I/O Lines
Three 16-Blt Timer/Counters

• 64K External Program Memory Space
• 64K External Data Memory Space .

• 6 Interrupt Sources
PO.O-PO.7

P2.0-P2.7

-----------,

r---------. ~~~

v~

~

PORT 0

PORT 2

DRIVERS

DRIVERS

I'ml

'L~~
RST

PI.0-P1.7

P3.0- P3.7

Figure 1. Block Diagram

10-38

270192-1

October 1987
Order Number: 270192-1103

inter

8052BH/8032BH

In addition, P1.0 and P1.1 serve the functions of the
following speCial features of the MCS®-51 Family:

PIN DESCRIPTIONS
(T2) PI.O

Port Pin

Vee

(T2EX) PI.I
PI.2

PO.I (ADI)

PI.3

PO.2 (AD2)

PI.4

PO.3 (AD3)

PI.S

PO.4 (AD4)

PI.6

PO.S (ADS)

PI.7

PO.6 (AD6)

RESET

P1.0
P1.1

PO.O (ADO)

9

Port 2: Port 2 is an a-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Port 2 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 2 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pullups.

PO.7 (AD7)

(RXD) P3.0

(TXD) P3.1

ALE

(INTO) P3.2

PSEN

(INTI) P3.3

P2.7 (AIS)

(TO) P3.4

P2.6 (AI4)

(TI) P3.S

P2.S (AI3)

(ViR) P3.6
(iW) P3.7

P2.4 (AI2)

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use a-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.

P2.3 (All)

XTAL2

P2.2 (AIO)

XTAL1

P2.1 (A9)

VSS

P2.0 (AS)

Alternate Function
T2 (Timer/Counter 2 External Input)
T2EX (Timer/Counter 2
Capture/Reload Trigger)

270192-2

Figure 2. Pin Connections
Vee: Supply voltage.
Vss: Circuit ground.
Port 0: Port 0 is an a-bit open drain bidirectional I/O
port. As an output port each pin can sink a LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.
Port 0 is also the multiplexed low-order address and'
data bus during accesses to external Program and
Data Memory; In this application it uses strong internal pullups when emitting 1s, and can source and
sink a LS TTL.inputs.

Port 3: Port 3 is an a-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 3 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special
features of the MCS®-51 Family, as listed below:

Port 1: Port 1 is an a-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 1 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pullups.

10-39

Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

inter

8052BH/8032BH

RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory;
.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.

Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Applications Note AP-155, "O~cillators for Microcontrollers."
To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
.
be observed.

PSEN: Program Store Enable is the Read strobe to
External Program Memory.
C2

When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to External Data Memory.
EA: External Access enable. EA must be strapped to .

1 - -.....--1

XTAL2

o
1 - -.....--1

XTAL 1

t - - - - - - - - 1 vss

Vss in order to enable the device to fetch code from
External Program Memory locations OOOOH to
1FFFH. Note, however, that if either of the Lock Bits
are programmed, EA will be internally latched on reset.
.
EA should be strapped to
executions.

270192-3
Cl, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators

Figure 3. Oscillator Connections

Vee for internal program
EXTERNAL
OSCILLATOR----I XTAL2
SIGNAL

XTAL 1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.

,..-- XTAL 1

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configuredfor use as an on-chip oscillator, as shown in

10-40

270192-4
CiftllPA
A Cvt"""'I!II1
I ."WI'"" .....
_ ...."" ••• u. 1"1ft,,...,
_1_"",",

=-_._ .. _..

n.i
t"ftftfi"'II.a.t;"""
_ • •..
• .a.
__
........

intJ

8052BH/8032BH

Voltage on Any Other Pin to Vss .... -O.SV to + 7V

• Notice: Stresses above those listed under '~bso­
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Power Dissipation .......................... 1.SW
(based on PACKAGE heat transfer limitations, not
device, power consumption)

NOTICE' Specifications contained within the
following tables are subject to change.

ABSOLUTE MAXIMUM RATINGS*
AmbientTemperature Under Bias .... O·C to + 70·C
Storage Temperature, .......... - 6S·C to + 1S0·C
Voltage on EA Pin
to Vss ...................... -O.SV to + 13.0V

ADVANCE INFORMATION. Contact Intel for Design-In Information.
D.C. CHARACTERISTICS (TA
Symbol

= O·Cto +70·C;Vcc

Parameter

. Min

=

sv ±10%;Vss =

OV)
Test Conditions .

Max

Unit

O.B

V

Vss

0.7

V

2.0

Vee+ 0.5

V

Input High Voltage XTAL2, RST

2.5

Vee+ 0.5

V

Input High Voltage to EA

4.5

5.5

V

Output Low Voltage
(Ports 1, 2 and 3)

0.45

V

IOL = 1.6 mA (Note 1)

VOL1

Output Low Voltage
(Port 0, ALE, PSEN)

0.45

V

IOL = 3.2 mA (Note 1) .

VOH

Output High Voltage
(Ports 1, 2, 3, ALE and PSEN)

2.4

V

IOH = -BO",A

VOH1

Output High Voltage
(Port 0 in External Bus Mode)

2.4

V

IOH = -400 ",A

IlL

Logical 0 Input Current
(Ports 1, 2, 3 and RSn

IIL1

' Logica(O Input Current (EA)

Input Low Voltage (Except EA)

-0.5

VIL1

Input Low Voltage EA

VIH

Input High Voltage
(Except XTAL2, RST, EA)

VIH1
VIH2
VOL

VIL

XTAL1 = Vss

-500

",A

VIN = 0.45 V

mA
",A

VIN = VSS

500

VIN = 0.45V XTAL1 = Vss

-10

IIL2

Logical 0 Input Current (XTAL2)

-3.2

mA

III

Input Leakage Current (Port 0)

±10

",A

0.45 < VIN  100 pF), the noise pulse on the ALE 'pin may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use·an address latch with a Schmitt
Trigger STROBE input.

10-41

inter

8052BH/8032BH

L:Logic level LOW, or ALE.
P:PSEN.
O:Output data.
R:RD signal.
T:Time.
V:Valid.
W:WR signal.
X:No longer a valid logic level. .
Z:Float.

EXPLANATION OF THE AC 'SYMBOLS
Each timing symbol has 5 characters. The first character is always a, "T" (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following isa I.ist of all the characters and
what they stand f o r . '
.'
A:Address ..
C:Clock.
D:lnput data.
H:Logic level HIGH.
1:lnstruction (program memory contents).

For example;
TAVLL = Time from Address Valid to ALE 'Low.
TLLPL = Time from ALE Low to PSEN Low.

A_C. CHARACTERISTICS (TA = O·C to 70·C; Vee = 5V ± 10%; Vss = OV); Load Capacitance for
Port 0, ALE and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)

ADVANCE INFORMATION. Contact Intel for Design-In Information.
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
12MHz9sc
Min
Max

1/TCLCL

Oscillator Frequency

TLHLL

ALE Pulse Width

127

Variable· OSCillator •
Max
Min
3.5
12.0
2TCLCL-40

TAVLL

Address Valid to ALE Low

43

TCLCL-40

TLLAX

Address Hold After ALE Low

48

TLLlV

ALE Low to Valid Instruction In

TLLPL

ALE Low to PSEN Low

TPLPH

PSENPulse,Width

TPLIV

PSEN Low to Valid Instruction In

TPXIX

Input Instr Hold After PSEN

TPXIZ

Input Instr Float After PSEN

TPXAV

PSEN to Address Valid '

TAVIV

Address to Valid Instruction In

Symbol

Parameter

I

TCLCL-25

215

3TCLCL-35
125

0

ns
ns

TCLCL-20

63

FI~at

ns
3TCLCL -1.25

TCLCL-8
..

302'
20

ns
ns

0

75

ns
ns

4TCLCL-100

58

MHz
ns

TCLCL-35
233

Units

5TCLCL-115

ns
ns
ns .

TPLAZ

PSEN Low to Address

TRLRH

RD Pulse Width

400

6TCLCL-100

IWLWH

WR Pulse Width

400

6TCLCL-100

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

97

2TCLCL-70

ns

TLLDV

ALE Low toValid Data In

517

8TCLCL-150

ns

TAVDV

Address to Valic! Data In

585

9TCLCL-165

ns

TLLWL'

ALE Low to RD or WR Low

200

TAVWL

Address to RD or WR Low .

203
23 '.

TOVWX
Data Valid to WR Transition
TOVWH' , Data Valid to WR High
TWHOX

Data Held After WR

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

20

0

ns
ns
5TCLCL-165

252

3TCLCL-50

ns
ns

0

300

ns

3TCLCL+50

4TCLCL-130

ns
ns'

TCLCL-60

, ns

,433

7TCLCL-150

ns

33

TCLCL-50
0

43
10-42

123

TCLCL-40

ns
0

ns

TCLCL+40

ns

intJ

8052BH/8032BH

_ _...J

~LE

PSEN _ _..I
TPXAV
TPXIZ
PORT 0 _ _ _..1

PORT 2

AO-.A7

----

AB-AI5
270192-5

External Program Memory Read Cycle

ALE

PSEN
i-----TLLDV

'

I

-----0-1---- TRLRH -----+l

RD

----+-----~

~-----------------INSTR. IN

PORTO

P2.0-P2.7 OR AB-AI5 FROM DPH

PORT2

AB-A 15 FROM PCH
270192-6

External Data Memory Read Cycle

,

ALE

I

-TLHLL-

J

=L-TWHLH
~

~TLLWL

-.

TAVLL !-TLLAX-

,

TWLWH

~
TQVWH

PORTO

~

FRoll~i~h DPL
TAVWL

PORT2

:::::>

-

-

DATA OUT

P2.0-P2.7 OR AB-A 15 FROM DPH

'-TWHQX
XAO-A7 FROM PCL

INSTR. IN

AB-AI5 FROM PCH
270192-7

External Data Memory Write Cycle

10-43

8052BH/8032BH

SERIAL PORT TIMING -

SHIFT REGISTER MODE

.TEST CONDITIONS TA = 0·Ct070·C;"Vcc =5V ± 10%;Vss = OV; Load Capacitance = 80pF
Symbol

12MHzOsc

..

Parameter

Min

Variable Oscillator

Max

Units

Max

Min

TXLXL

Serial Port Clock Cycle Time

1.0

12TCLCL

/Ls

TOVXH

Output Data Setup ~o
Clock Rising Edge

700

10TCLCL"'-133

ns

TXHOX

Output Data Hold After
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

INSTRUCTION

I

c

1OTCLCL -133

700

0

3

2

4

7

6

5

ns

8

ALE

CLOCK

I TOVXH

OUTPUT DATA

I

r-TXHOX

---"'I:\~--:O~""-:-\IX

SBUF"

.J

INPUT DATA

~L

t
WRITE TO

t

CL~R

1

I"

IXr--:2~""\Xr-~~
3
X

X

4

~r~~
TXHDV I:
~u

5

-X

6

X

I

7

I

SET TI
~Il

~LIIl

~Ull

~

~

I

SET RI

RI

270192-8

Shift Register Mode Timing Waveforms

14-TCHCX-+I

TCLCH-I

14-

-+I

J+- TCHCL

-~-TCLCL---+I

External Cloc~ Drive Waveforms

10-44

270192-9

8052BH/8032BH

EXTERNAL CLOCK DRIVE
Symbol

Parameter

AC TESTING INPUT/OUTPUT WAVEFORMS

2.4=X

Min Max Units

1/TCLCL Oscillator Frequency 3.5

12

MHz

TCHCX

High Time

20

ns

TCLCX

Low Time

20

ns

TCLCH

Rise Time

20

ns

TCHCL

Fall Time

20

ns

2.0
o~

2.0
TEST POINTS

o~

)C
.

.

0.4SV
270192-10
AC inputs during testing are driven at 2.4V for a logic 'T' and
0.45V for a logic "0". Timing measurements are made at 2.0V for
a logic '"1" and O.BV for a logic "0".

Table 1_ Lock Bits and their Features

Lock Bits

PROGRAM MEMORY LOCK
The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against software piracy. The following description applies to the
8752BH. The same options are also available on the
8052BH, mask-programmed at the factory.

LB2

U

U

Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)

P

U

MOVC instructions executed from
external program memory are
disabled from fetching code bytes
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled

P

P

Same as above, but Verify is also
disabled

U

P

Reserved for Future Definition

ENCRYPTION ARRAY
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NORed
(XNOR) with ·the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its
original, unmodified. form.
.
It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.

Logic Enabled'

LB1

P = Programmed
U = Unprogrammed

To ensure proper functionality of the chip, the internally latched value of the EA pin must agree with its .
extern~l.state.

LOCK BITS
Also included in the Program Lock scheme are two
Lock Bits which function as shown in Table 1.

10-45

8752B'H
SINGLE-CHIP8-BIT MICROCOMPUTER,
WITH 8K BYTES OF EPROM PROGRAM,MEMORY
..'
• Program Memory Lock
• 256 Bytes Data Ram'
• Quick Pulse Programming™ Algorithm

• 6 Interrupt Sources
• Programmable Serial Cliannel
• Separate Transmit/Receive Baud Rate
Capability
.64K External Program Memory Space

• .12:75 Volt Programming Voltage
• Boolean Processor
• 32 Programmable I/O Lines
• Three 16·Bit Timer/Counters

• 64K External Data Memory Space

PO.O-PO.7

r -

~~

-

-

-

-

-,- -

-

P2.0-P2.7

-

. p..~t..I.lI~

:--:---------,

Vss

-F

i'S£iI
AU:/1'RllC

£A'Yitr ::I~ CO'NTRO>L\

P1.0-Pl.7

P3.0-P3.7

270429-1

Figure 1. Block Diagram

10-46

October 1987
Order Number: 270429-001

inter

8752BH

Port 1 also receives the low-order address bytes
during EPROM programming and program verification.

PIN DESCRIPTIONS

(T2) PLO

Vee

(T2EX) Pl.l,

PO.O (ADO)

Pl.2

PO.l (AD1)

Pl.3

PO.2 (AD2)

Pl.4
Pl.S

PO.3 (AD3)

In addition, P1.0 and P1.1 serve the functions of the
following special features of the MCS®-S1 Family:

Port Pin
P1.0
P1.1

PO.4 (AD4)

Pl.S

PO.S (ADS)

Pl.7

PO.S (ADS)

RESET

PO.7 (AD7)

(RXD) P3.0

EA/Vpp

(TXD) P3.1

ALE/PROG

(INTO) P3.2

PSEN

{lNT1) P3.3

P2.7 (A lS)

(TO) P3.4

P2.S (A14)

(T1 ) P3.S
(WR) P3.S

P2.S (A13)
P2.4 (A12)

(RO) P3.7

P2.3 (All)

XTAL2

P2.2 (Al0)

XTALl

P2.1 (A9)

Vss

P2.0 (A8)

Alternate Function
T2 (Timer/Counter 2 External Input)
T2EX (Timer/Counter 2
Capture/Reload Trigger)

Port 2: Port 2 is an a-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Port 2 pins that have 1s
written to them are pulled high by the. internal pullups, and in that state can be used as inputs. As
inputs, Port 2 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use a-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.

270429-2

Figure 2. Pin Connections

Port 2 also receives the high-order address bits during EPROM programming and program verification.

Vee: Supply voltage.
Vss: Circuit ground.

Port 0: Port 0 is an a-bit open drain bidirectional 110
port. As an output port each pin can sink a LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
.
inputs.
Port 0 is also the multipl~xed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emittill9 1s, and can source and
sink a LS TTL input~ ..

Port 3: Port 3 is an a-bit bidirectional I/O port with
intermil pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 3 pins that are externally being pulled
low will source current (IlL, on the data sheet) because of the pull ups.
Port 3 also serves the functions of various special
features of the MCS®-S1 Family, as listed below:

Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.S
P3.6
P3.7

Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.

Port 1: Port 1 is an a-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1s
written to them are pulled high by the internal pullups, and in that state can be used as inputs. As
inputs, Port 1 pins that are externally being pulled
low will source current .(IIL' on the data sheet) because of the internal pullups.

Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.

10-47

8752BH

ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming on
the 8752BH.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.

cations Note AP-155, "Oscillators for Microcontrollers."
To drive the device from an external clock source,
XTAL 1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the Data Sheet must
be observed.

PSEN: Program Store Enable is the Read strobe to
External Program Memory:

C2

r---1I--.---f XTAL2
When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access ~o External Data Memory.

t--.....--I XTAL 1
.....~-----I Vss

EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the device to
fetch code from External Program Memory locations_
OOOOH to 1FFFH. Note, however, that if either of the
Lock B.its are programmed, EA will be internally
latched on reset.

270429-3
C1. C2 = 30 pF ± 10 pF for prystals
= 40 pF ± 10 pF for Caramic Resonators

Figure 3. Oscillator Connections

EA sh.ould be strapped to Vee for internal program
executions.
.
.

EXTERNAL
OSCILLATOR~---I

XTAL2

SIGNAL

This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.

-

XTAL1

_

Vss

XTAL2: Output from the inverting oscillator amplifier.
270429-4

Figure 4. External Clock Drive Configuration

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured .for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Appli-

DESIGN .CONSIDERATIONS
Exposure to light when tlie 8752BH is in operation
may cause logic errors. For this reason, it is suggested that an opaque label be placed over. the window
of the 8752BH when the die is exposed to ambient
light.

10-48

inter

8752BH

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...... ODC to 70DC
Storage Temperature .......... -6SDC to + 1S0DC
Voltage on EAlVpp Pin to Vss ... -O.SV to + 13.0V
Voltage on Any Other Pin to Vss .... -O.SV to + 7V
Power Dissipation .......................... 1.SW
(based on PACKAGE heat transfer limitations, not
device power consumption)

NOTICE Specifications contained within the
fol/owing tables are subject to change.

sv

±10%;Vss = OV)

Min

Max

Units

Input Low Voltage (Except EA)

-0.5

0.8

V

VILl

Input Low Voltage EA

Vss

0.7

V

VIH

Input High Voltage
(Except XTAL2, RST, EA)

2.0

Vee+ 0.5

V

VIH1

Input High Voltage XTAL2, RST

2.5

Vec+ 0.5

V

VIH2

Input High Voltage to EA

4.5

5.5

V

VOL

Output Low Voltage
(Ports 1, 2 and 3)

0.45

V

IOL

= 1.6 mA (Note 1)

Vall

Output Low Voltage
(Port 0, ALE/PROG, PSEN)

0.45

V

10L

= 3.2 mA (Note 1, 2)

VOH

Output High Voltage
(Ports 1, 2, 3, ALE/PROG and PSEN)

2.4

V

IOH

= -80/LA

VOH1

Output High Voltage
(Port 0 in External Bus Mode)

2.4

V

IOH

= -

IlL

Logical 0 Input Current
(Ports 1, 2, 3 and RST)

/LA

VIN

= 0.45V

IIL1

Logical 0 Input Current (EA)

mA

VIN

=

Vss

=

0,45V XTAL1

D.C. CHARACTERISTICS
Symbol
VIL

(TA = ODCto +70DC;Vcc =

Parameter

-500
-10
500

/LA

Test Conditions

XTAL1

IIL2

Logical 0 Input Current (XTAL2)

-3.2

mA

VIN

III

Input Leakage Current (Port 0)

±10

/LA

0.45

= Vss

400 /LA

=

Vss

< VIN < Vee
4.5V < VIN < 5.5V
VIN < (Vee - 1.5V)

IIH

Logical 1 Input Current (EA)

1

mA

IIH1

Input Current to RST
to activate Reset

500

/LA

lee

Power Supply Current

175

mA

All Outputs Disconnected

Cia

Pin Capacitance

10

pF

Test freq

=

1 MHz

NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
make 1-\0-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the
ALE/PROG pin may exceed O.SV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address
latch with a Schmitt Trigger STROBE input.
2. ALE/PROG refers to a pin on the device. ALE refers to a timing signal that is output on the ALE/PROG pin.

10-49

8752BH

L:Logic level LOW, or ALE
P:PSEN
..
Q:Output data
.' R:RD signal
T:Time
V:Valid
W:WR signal
X:No longer a valid logic level
Z:Float

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name. of a signal or the logical status of that
signal. The following is a,list of all the ch!lracters and
what they stand for.
A:Address
C:Clock'
D:lnput Data
H:Logic level HIGH
1:lnstruction (program memory contents)

For example,
TAVLL
TLLPL

= Time from Address Valid to ALE Low.
=

Time from ALE Low to PSEN Low.

A.C. CHARACTERISTICS (TA = O°C to + 70°C; Vcc. = 5V ± 10%; Vss = OV); Load Capacitance for
Port 0, ALE/PROG, and PSEN

= 100 pF; Load Capacitance for All Other OutpLits = 80 pF)

EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol

Parameter

12MHzOsc
Min

Variable Oscillator

Max

Min'

Max

3.5

12.0

Units

l/TCLCL

OsCiliator Frequency

TLHLL

ALE Pulse Width

127

2TCLCL-40

ns

TAVLL

Address Valid to ALE Low

43

TCLCL-40

ns

TLLAX

Address Hold After ALE Low

48

TCLCL-35

TLLlV

ALE Low to Valid Instruction In

TLLPL

ALE Low to PSEN Low

58

TCLCL-25

TPLPH

PSEN Pulse Width

215

3TCLCL-35

TPLIV

PSEN Low to Valid Instruction In

TPXIX

.input Instr Hold After PSEN

TPXIZ

Input Instr Float After PSEN

TPXAV

PSEN to Address Valid

TAVIV

Address to Valid Instruction In

302

5TCLCL-115

ns

TPLAZ

PSEN Low to Address Float

20

20

ns,

TRLRH

RD Pulse Width

400

6TCLCL-100

TWLWH

WR Pulse Width

400

6TCLCL-100

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

97

2TCLCL-70

ns

TLLDV

ALE Low to Valid Data In

517

8TCLCL-150

ns

TAVDV

Address to Valid Data In

585

9TCLCL-165

ns

TLLWL

ALE Low to RD or WR Low.

200

3TCLCL+50

ns

TAVWL

Address to RD or WR Low

203

4TCLCL-130

ns

TOVWX

Data Valid to WR Transition

23

TCLCL-60

ns

TOVWH

Data Valid to WR High

433

7TCLCL-150

ns

TWHOX

Data Held After WR

33

TCLCL-50

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

233

ns
4TCLCL-100

0

ns

TCLCL-20

.

TCLCL-8

75

252

300

ns
ns
5TCLCL-165

3TCLCL-50

0
43

123

10-50

TCLCL-40

ns
ns

.0

0

ns
ns

0
63

ns
ns

3TCLCL-125

125

MHz'

ns
ns

ns
0

ns

TCLCL+40

ns

8752BH

ALE _ _J

PSEN _ _J

]I--!----Ji"_____.

TPXAV
TPXIZ

PORT

a _ _J

AO-A7

AB-AI5

PORT 2 _ _.....J

270429-5

External Program Memory Read Cycle

ALE

PSEN

'I

i------TLLDV

--+---

TRLRH

---~

PORTO

INSTR. IN

P2.0-P2.7 OR AB-AI5 FROM DPH

PORT2

AB-AI5 FROMPCH

270429-'6

External Data Memory Read Cycle

ALE

-1:.-TLHLL~

I

~

4TWHLH
~
~TLLWL

.PORTO

PORT2

:::r
:::::>

TAVLL -TLLAX-

,

TWLWH

TQVWH

FRoIAA~i~~

DPL

J

~
DATA OUT

--TWHQX

1\

AO-A7 FROM PCL

INSTR. IN

TAVWL
P2.0-P2.7 OR AB-A 15 FROM DPH

X

AB-A 15 FROM PCH

270429-7

External Data Memory Write Cycle

10-51

8752BH

SERIAL PORT TIMING-SHIFT REGISTER MODE
TEST CONDITIONS
Symbol

TA

=

o·c to + 70·C; vee =

5V ± 10%; vss

Parameter

Min

=

OV; Load Capacitance

=

80 pF

Variable Oscillator

12MHzOsc
Max

Units

Max

Min

TXLXL

Serial Port Clock Cycle Time

.1.0

12TCLCL

TOVXH

Output Data Setup to
Clock Rising Edge

700

10rCLCL --.: 133.

ns

TXHOX

Output Data Hold After .
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

INSTRUCTION

I

10TCLCL-133

700

2·

·1

0

. /Ls

7

6

4

3

ns

8

ALE

CLOCK

OUTPUT DATA·

t

\

~!-TXHQX
0
IX
1
I

X

2

3

X

4

X

5

X 6X

r.: . ....

7/
I

-lrTXHDX

SET TI
WRITE TO SBUF
-l TXHDV
INPUT DATA -.,.....----\r.:AJ~,....-w:AlI~·~-\r.:A-:-::U)J'"-,.r.:':AL'::!ID.;--V~AIJ~,...."'\r.~AIJ'="-\r.:AIJ":':D)J'"-,.r.:':":!J

I

t

SET RI.

CLEAR RI

270429-8

Shift Register Mode Timing Waveforms

270429-9

External Clock Drive Waveforms

10-52

inter

8752BH

EXTERNAL CLOCK DRIVE
Symbol

Parameter

A.C. TESTING INPUT/OUTPUT WAVEFORMS

Min Max Units

'1/TClCl Oscillator Frequency 3.5

12

2 . 4 = X 2.0
O.B

MHz

TCHCX

High Time

20

ns

TClCX

low Time

20

ns

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

TEST POINTS

2.0
0.8

)C

0.45V

270429-10
AC inputs during testing are driven ,at 2.4V.for a logic "1" and
O.4SV for a logic "0". Timing measurements are made at 2.0V for
a logic "1" and O.BV for a logic "0".

EPROM CHARACTERISTICS
Table 1 shows the logic levels for programming the
Program Memory, the Encryption Table, and the
lock Bits and for reading the Signature bytes.

Programming the EPROM
To be programmed, the 8752BH must be running
with a 4 to 6 MHz oscillator. (The reason the oscillator needs to be running is that the internal bus is
being used to transfer address and program data to
appropriate internal registers.) The address of an
EPROM location to be programmed is applied to
Port 1 and pins P2.0 - P2.4 of Port 2, while the code
byte to be programmed into that location is applied
to Port O. The other Port 2 and 3 pins, and RST,
PSEN, and EAlVpp should be held at the "Pro-

gram" levels indicated in Table 1. AlE/PROG is
pulsed low to program the code byte into the addressed EPROM location. The setup is shown in Figure 5.
Normally EAlVpp is held at a logic high..J!.ntil just
before AlE/PROG is to be pulsed. Then EAlVpp is
raised to Vpp, AlE/PROG is pulsed low, and then
EAlVpp is returned to a valid high voltage. The voltage on the EAlVpp pin must be at the valid EAlVpp
high level before a verify is attempted. Waveforms
and detailed· timing specifications are shown in later
sections of this data sheet.
Note that the EAlVpp pin must not be allowed to go
above the maximum specified Vpp level for any
amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The Vpp source should be well regulated and
free of glitches.

+5V

25 100!-'. PULSES TO GND
8752BH

.--_--IXTAL2

L -......-+-IXTAL 1

Vss

270429-11

Figure 5. Programming the EPROM

10-53

inter

8752BH

Table 1 EPROM Programming Modes
MODE

RST

PSEN

ALEI
PROG

EAI
Vpp'

P2.7

P2.6

P3.6

P3.7

Program Code Data

1

0

O'

Vpp

1

0

1

1

Verify Code Data

1

0

1

1

0

0

1

1

Program Encryption Table
Use Addresses 0-1 FH

1

0

O'

Vpp

1

0

0

1

1
1

0
0

O·

O'

Vpp
Vpp

1
1

1
1

1
0

1
0

1

0

1

1

0

0

0

0

Program Lock
Bits (LBx)
Read Signature

x=1
x=2

NOTES:
"1" = Valid high for that pin
"0" = Valid low for that pin
"Vpp" = + 12.75V ±0.25V
*ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming™)

QUICK-PULSE PROGRAMMINGTM
ALGORITHM

PROGRAM VERIFICATION
If the Lock Bits have not been programmed, the onchip Program Memory can be read out for verification purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port .1 and
pins P2.0 - P2.4. The other pins should be held at
the "Verify" levels indicated in Table 1. The contents of the addressed location will come out on Port
O. External pullups are required on Port 0 for this
operation. (If the Encryption Array in the EPROM
has been programmed, the data present at Port 0
will be Code Data XNOR Encryption Data. The user
must know the Encryption Array contents to manually "unencrypt" the data during verify.)

The 8752BH can be programmed using the QuickPulse Programming™ Algorithm for microcontrollers. The features of the new programming method
are a lower Vpp (12.75 volts as compared to 21
volts) and a shorter programming pulse. It is possible to program the entire 8K Bytes of EPROM memory in less than 25 seconds with this algorithm!
To program the part using the new algorithm, Vpp
must be 12.75 ±0.25 Volts. ALE/PROG is pulsed
low for 100 fLseconds, 25 times as shown in Figure
6. Then, the byte just programmed may be verified.
After programming, the entire array should be verified. The Program Lock features are programmed
using the same method, but with the setup as shown
in Table 1. The only difference in programming Lock
features is that the Lock features cannot be directly
verified. Instead, verification of programming is by
observing that their features are enabled.

The setup, which is shown in Figure 7, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
low read strobe.

11~, - - - - - - 2 5

'I

PULSES

ALE/PROG:~-----~
'----.---J .

'-.~

10)'.

MIN1 I'

ALE/PROG :---...:...,\

n

o L._ _ _ _ _ _ _..J

100,u'
:1:10)'.

'I

n

'-_ _ _ _ _ _..... '-._ __
270429-12

Figure 6. PROG Waveforms

10-54

8752BH

270429-13

Figure 7. Verifying the EPROM
Table 2. Lock Bits and their Features

PROGRAM MEMORY LOCK

Lock Bits

The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against software piracy.

Logic Enabled

LB1

LB2

U

U

Minimum Program Lock features
enabled. (Code Verify will still be
encrypted by the Encryption
Array)

P

U

MOVC instructions executed from
external program memory are
disabled from fetching code bytes
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled

P

P

Same as above, but Verify is also
disabled

U

P

Reserved for Future Definition

ENCRYPTION ARRAY
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NORed
(XNOR) with the code !:Iyte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its
original, unmodified form.
It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.

P = Programmed
U = Unprogrammed

LOCK BITS

READING THE SIGNATURE BYTES·

Also included in the EPROM Program Lock scheme
are two Lock Bits which function as shown in Table

The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031 H,
except that P3.6 and P3.7 need to be pulled to a
logic low. Thevalues returned are:

2.
Erasing the EPROM also erases the Encryption Array and the Lock Bits, returning the part to full unlocked functionality.
To ensure proper functionality of the chip, the internally latched value of the EA pin must agree with its
external state.

10-55

(030H)
(031 H)

= 86H indicates manufactured by Intel
= 52H indicates 8752BH

8752BH

ERASURE CHARACTERISTICS

this type of exposure, it is suggested that an opaque
label be placed over the window.

Erasure of the EPROM begins to occur when the
8752BH is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to

The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at lease 15 W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 jJ-W/cm rating for 30 minutes, at a distance of about 1 inch;
should be sufficient.
Erasure leaves the array in an all 1s state.

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA = 21°C to 27°C, Vee = 5.0V ±10%, Vss = OV)
Symbol

Units

Parameter

Min

Max

Vpp

Programming Supply Voltage

12.5

13.0

V

Ipp

Programming Supply Current

50

rnA

-6

1/TCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG Low

TGHAX

Address Hold After PROG

48TCLCL

TDVGL

Data Setup to PROG Low

48TCLCL

4

MHz

48TCLCL

TGHDX

Data Hold After PROG

48TCLCL

TEHSH

P2.7 (ENABLE) High to Vpp

48TCLCL

TSHGL

Vpp Setup to PROG Low

10

jJ-s

TGHSL

Vpp Hold After PROG

10

jJ-s

TGLGH

PROGWidth

90

TAVaV

Address to Data Valid

TELaV

ENABLE Low to Data Valid

TEHaZ

Data Float After ENABLE

0

TGHGL

PROG High to PROG Low

10

jJ-s

48TCLCL

PROGRAMMING
PI.a-pI.7
p2.a-p2.4

110
48TCLC;L

48TCLCL.
jJ-s

VERIFICAnON

---:----{=:A~D~DR~ES~S~~=~--~-__;=:::!A~DD~RE~SS~J----TAVQV

PORT a

----H:=~~~:=H_-----:--_{~DA~TA~O~U~T::Jf-----:-TDVGL

ALE/PROG

-----""\1
TSHGLj-_

fA/vpp

_

_ TGLGH

~lI---"'vp-p---'i!-----.ll'---:;::t,.:;::::::-_ _.f-____I - - - - -

--J

="!T_EHSH

P2.7

~.~----~-------

TEHQZ

~-~

270429-14

EPROM Programming and Verification Waveforms
10-56

SOC51 BH/SOC51 BH-1 /SOC51 BH-2
CHMOS SINGLE-CHIP S-BIT MICROCOMPUTER
WITH FACTORY MASK-PROGRAMMABLE ROM
SOC31 BH/SOC31 BH-1/S0C31 BH-2
CHMOS SINGLE-CHIP S-BIT CONTROL-ORIENTED
CPU WITH RAM AND I/O
SOC51BH/SOC31BH-3.5 to 12 MHz, Vee = 5V ± 20%
SOC51BH-1/S0C31BH-1-3.5 to 16 MHz, Vee = 5V ±20%
SOC51BH-2/S0C31BH-2-0.5 to 12 MHz, Vee = 5V ± 20%

•

Power Control Modes

•

High Performance CHMOS Process

•
•

128 x 8-Bit RAM
32 Programmable I/O Lines

• Boolean Processor
_ 5 Interrupt Sources

•

Two 16-Bit Timer/Counters

•

Programmable Serial Port

•

64K Program Memory Space

•

64K Data Memory Space

The MCS®-51 CHMOS products are fabricated on Intel's CHMOS III process and are functionally compatible
with the standard MCS-51 HMOS and EPROM products. CHMOS III is a technology which combines the high
speed and density characteristics of HMOS with the low power attributes of CHMOS. This combination expands the effectiveness of the powerful MCS-51 architecture and instruction set.
Like the MCS-51 HMOS versions, the MCS-51 CHMOS products have the following features: 4K byte of ROM
(80C51 BH/80C51 BH-1/80C51BH-2 only); 128 bytes of RAM; 32 I/O lines; two 16-bit timer/counters; a fivesource two-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuitry. In
addition, the MCS-51 CHMOS products have two software selectable modes of reduced activity for further
power reduction-Idle and Power Down.
The Idle mode freezes the CPU while allowing the RAM, timer/counters serial port and interrupt system to
continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.

-IVSS~

-

-

I

I
I

270064-1

Figure 1. Block Diagram

10-57

September 1987
Order Number: 270064·005

inter

80C51BH, -1, -2/80C31BH, -1,-2

IDLE MODE

Vss

In the Idle mode; the CPU puts itself to sleep while
all the on chip peripherals stay active. The instruction that invokes the Idle mode is the last instruction
executed in the normal operating mode before Idle
mode is activated. The content of CPU, the on chip
RAM, and all the Special Function Registers remain
intact during this mode. The Idle mode can be terminated either by any enabled interrupt, at which time
the process is picked up at the interrupt service routine and continued, or by a hardware reset which
starts the processor the same as a power on reset.

Circuit ground.

POWER DOWN MODE
In the Power Down mode the oscillator is stopped,
and the instruction that invokes Power Down is the
last instruction executed. The· on-chip. RAM and
Special Function Registers retain their values until
the Power Down mode is terminated.
The only exit from Power bown is a hardware reset.
Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before Vee is restored to its normal operating level and
must be held active long enough to allow the oscillator to restart and stabilize.
The control bits for the reduced power modes are in
the Special Function Register PCON.

PortO
Port Ois an 8-bit open drain bi-directional 1/0 port.
Port 0 pins that have 1's written to them float, and in
that state can be used .as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1s; Port 0 al~9 outputs the
code bytes during program verification in the
80C51 SH. External pullups are required during program verification.

Port 1
Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are
pulled high by the internal pull ups, and in that state
can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (ilL,
on the data sheet) because of the internal pullups.

Port 2

NOTE:
For more detailed information on these reduced
power modes refer to Application Note AP-252,
"Designing with the 80C51 SH".

Port 2 is an 8-bit bidirectional 1/0 port with'internal
pullups. Port 2 pins that have 1s written to them are
pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (ilL,
on the data sheet) because of the internal pull ups.

PIN DESCRIPTIONS

Port 2 emits the high-order address byte during
fetches from external Program Memory and during

Vee
Supply voltage during normal, Idle, and Power Down
operations.
Table 1. Status of the external pins during Idle and Power Down modes
Mode
Idle

Program
Memory

ALE

PSEN

PORTO

PORT 1

PORT 2

PORT 3

Internal

1

1

Data

Data

Data

Data

, Idle

External

1

1

Float

Data

Address

Data

Power Down

Internal

0

0

Data

Data

Data

Data

Power Down

External

0

0

Float

Data

Data

Data

10-58

intJ

80C51BH, -1, -2/80C31BH, -1,-2

INDEX
CORNER

VCC
PO.O
PO.l
PO.2
PO.3
PO.4
PO.5 '
PO.I
PO.7

Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.5
Pl.6
Pl.7
RST
P3.0/RXD
P3.1/TXD
P3.2/iN'fii
P3.3INTl
P3.4/TO
P3.S/Tl
P3.6/WR
P3.7/iii)
XTAL2
XTALl
VSS

P1.5
Pl.6
Pl.7
RST
P3.0
NC
P3.1
P3.2
P3.3
P3.4
P3.S

EA
ALE

iiSEN
P2.7
'P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0

~(~

~~

)=~

:~ PO.S

PO.4

:.: ~

~~! PO.6

!~1

~H PO.7

H]

~~

1~ ~

r~ NC

EA

~~~

~~ ALE

!! ~

~}~

~~!

r~! P2.7

!!;

rM P2.6
r~ P2.S

j!]

:~: ;~:

:2: :;;: ;R:

270064-2

:A~

:::

r~;

;i: ;s;;

PSEN

:~:

270064-3

Pin

Pad

Diagrams are for pin reference only.
Package sizes ,are not to scale.

Figure 2. Connection Diagrams
accesses to external Data Memory' that use 16-bit
addresses (MOVX @DPTR). In this, application it
uses strong internal pullups when emitting 1s. During accesses to external Data Memory that use S-bit
addresses (MOVX @Ri), Port 2 emits the conten(s of
the P2 Special Function Register.

RST

Reset input. A high on this pin for two machine cycles whiie the oscillator is running resets the device.
An internal diffused resistor to Vss permits PowerOn reset using only an external capacitor to Vee.

Port 3

ALE

Port 3 is an S-bit bidirectional 110 port with internal
pullups. Port 3 pins that have 1s written to them are
pulled high by the internal pullups, and in that state.
can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (ilL,
on the data sheet) because of the pullups.

Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
memory.

Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:

Port Pin
P3.0
P3.1

P3.2

P3.3
P3.4

P3.5

P3.6
P3.7

In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however,that one ALE pulse is skipped during each'
access to external Data Memory.

Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write
strobe)
RD (external data memory read
strobe)

Program Store Enable is the read strobe to external
Program Memory.

10-59

inter

80C51BH, ~1, -2/80C31BH, -1,-2

When the 80C51 BH is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory. PSEN is not activated during fetches from internal program memory.

EA
External Access enable. EA must be strapped to
Vss in order to enable the device to fetch code from
external Program Memory locations· OOOOH to
OFFFH. If EA is strapped to Vee the device executes
from internal Program Memory unless the program
counter contains an address greater than. OFFFH.

ured for use as an on-chip oscillator, as shown in
Figure 3. More detailed information concerning the
use of the on-chip oscillator is available in Application Note AP-155,. "Oscillator for Microcontr'ollers".
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide~by-two flip"flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.
.

Design Considerations

XTAL1

• At power on, the voltage on Vee and RST must
come up at the same time for proper start-up.

Input to the inverting oscillator amplifier and input to.
the internal clock generator circuits.

• Before entering· the Power Down mode the contents oUhe Carry Bit and B.7 must be equal.

a

• When the Idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it .left off, up to two machine
cycles before the internal reset algorithm takes
control: On-chip hardware inhjbits access to internal RAM in this event, but access to the port pins
is, not inhibited. To elimin.ate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the .one that invokes
Idle should not be on~ that writes to a port pin or
to external memory.
..

XTAL2
Output from the inverting oscillator amplifier.

30pF"

t - - - - - - - - I vss
NC

270064-4

Figure 3. Crystal OSCillator

XTAL2

EXTERNAL
OSCILLATOR --~----------1 XTAL 1
SIGN~L

':,: .

Oscillator, Characteristics

VSS

XTAL 1 and XTAL2 are the inpl,lt and output, respectively, of an inverting ,amplifier which can be config-

270064-5.

Figure 4. External Drive Configuration

10-60

inter

80C51BH, -1, -2/80C31BH, -1,-2

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... o'e to + 70'e
Storage Temperature .......... - 65'e to + 150~e
Voltage on any
Pin to Vss ................ -0.5V to Vcc

+ 0.5V

Voltage on Vcc to Vss ............. -0.5V to 6.5V

• Notice: Stresses above those listed under '~bso­
lute Maximum Ratings" may caU.se permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability..

Power Dissipation ......................... 1.0W·
"This value is based on the maximum allowable die temperature and
the thermal resistance of the package.

D.C. CHARACTERISTICS
Symbol

= o'e to 70'e; Vcc = 5V ± 20%; Vss = OV)
Typ(3)

Max

Unit

VIL

Input Low Voltage
(ExceptEA)

-0.5

0.2 Vee -0.1

V

VIL1

Input Low Voltage (EA)

-0.5

0.2 Vee - 0.3

V

VIH

Parameter

(TA

NOTICE Specifications contained within the
following tables are subject to change.

,Input High Voltage
(Except XT AL 1, RST)

Min

0.2 Vee

+ 0.9

Vee

+ 0.5

V

Vee

+ 0.5

V

Test Conditions

VIH1

Input High Voltage
(XTAL1, RSn

VOL

Output Low Voltage
(Ports 1. 2. 3)

0.45

V

IOL = 1.6mA(1)

VOL1

Output Low Voltage
, (Port 0, ALE, PSEN)

0.45

'V

IOL = 3.2 mA (1)

Output High Voltage
(Ports 1, 2, 3, ALE, PSEN)

VOH

Output High Voltage
(Port 0 in External Bus
Mode)

VOH1

0.7 Vee

2.4

V

IOH = -60 /LA Vee = 5V ±10%

0.75 Vee

V

IOH = -25/LA

0.9 Vee

V

IOH= -10/LA

2.4

V

IOH = -800 /LA Vee = 5V ± 10%

0.75 Vee

V

IOH = -300/LA

V

0.9 Vee

IOH = -80 /LA (2)

IlL

Logical 0 Input Current
(Ports 1, 2, 3)

-50

/LA

VIN = 0.45V

ITL

Logical 1 to 0 Transition
Current (Ports 1, 2, 3)

-650

/LA

VIN = 2V

III

Input Leakage Current
(PortO, EA)

±10

/LA

0.45

RRST

Reset Pulidown Resistor

150 .

KO

CIO

Pin Capacitance

10

pF

Icc

Power Supply Current:
Active Mode, 12 MHz (4)
Idle Mode, 12 MHz (4)
Power Down Mode

20
5
50

mA
mA

I

50

11
1.7
5

10-61

/LA

< VIN < Vee

Test Freq = 1 MHz, T A = 25'C

(5)

80C51BH, -1, -2/80C31BH, -1,

~2

NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vou; of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pil')s make 1to-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input. ,
'
2. Capacitive loading on PO,rts 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 Vcc
specification when the address bits are stabilizing.
3. "Typicals" are based on limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temperature,'5V.
'
4. ICCMAX at other frequencies is given by
Active Mode: ICCMAX = 1.47'X FREQ + 2.35
Idle Mode:
ICCMAX = 0.33 x FREQ + 1.05
,
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mAo See Figure 5.
5. See Figures 6 through 9 for Icc test conditions.

a

2S

1

,--""r--,--...,-"T1 ~~~VE

MODE

TYP(3)

151---+-----ifr-+-----..I ACTIVE MODE
XTAL2
XTAL1

10r---+-~___i-~+--~

vss
MAX
IDLE MODE

270064-15

Figure 7. Icc Test Condition, Idle Mode.
All other pins are disconnected.

TYP(3)

L:~d:::::::t:=:t=~ IDLE MODE
4MHz

BMHz

12MHz

16MHz

FREQ AT XTAL 1

270064-13

Figure 5. Icc vs. Frequency.
Valid only within frequency specifications of
the device under test.

XTAL2
XTALI

vss
270064-14

Figure 6. Icc Test Condition, Active Mode.
All other pins are disconnected.
"

I

10-62

inter

80C51BH, -1, -2/80C31BH, -1,-2

O.S • - - - - - -~~---Vce. .
0.7 Vee
0.4SV
0.2 Vce -O.l
TCHCL
270064-16

Figure 8. Clock Signal Waveform for Icc Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.

Vce
lee~

",---vee...

vce

PO
RST

Eli

XTAL2
XTALl

vss
270064-17

Figure 9. Icc Test Condition, Power Down Mode. All other pins are disconnected. Vcc = 2V to 6V.
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that .
signal. The following is a list of all the characters and
.
what they stand for.
A:
C:
D:
H:
I:
L:

Address.
Clock.
Input data.
Logic level HIGH.
Instruction (program memory contents).
Logic level LOW, or ALE.

P:
Q:
A:
T:
V:
W:
X:
Z:

PSEN.
Output data.
AD signal.
Time.
Valid.
WA signal.
No longer a valid logic level.
Float.

EXAMPLE:
TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.

10-63

80C51BH, -1, -2/80C31BH, -1,-2

A.C. CHARACTERISTICS
(TA = O·C to 70·C, Vee =. 5V ± 20%, Vss = OV, Load Capacitance for Port 0, ALE, and PSEN = 100 pF,
Load Capacitance for All Other Outputs = 80 pF)

EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol

Parameter

12MHzOsc
Min

1/TCLCL

Max

Oscillator Frequency
80C51 BH/80C31 BH
80C51 BH-1 /80C31BH-1
80C51 BH-2/80C31 BH-2

Variable OSCillator

Units

Min

Max

3.5
3,5
0.5

12
16
12

MHz

TLHLL

ALE Pulse Width

127

2TCLCL - 40

ns

TAVLL

Address Valid to ALE Low

28

TCLCL - 55

ns

48

TCLCL - 35

TLLAX

Address Hold After ALE Low

TLLlV

ALE Low to Valid Instr In

TLLPL

ALE Low to PSEN Low

43

TCLCL - 40

ns

TPLPH

PSEN Pulse Width

205

3TCLCL - 45

ns

TPLIV

PSEN Low to Valid Instr In

TPXIX

Input Instr Hold After PSEN

TPXIZ

Input Instr Float After PSEN

TAVIV

Address to Valid Instr In

234

.3TCLCL - 105

145
0

ns
4TCLCL - 100

0

ns

ns
ns

59

TCLCL - 25

ns

312

5TCLCL - 105

ns

10

ns

TPLAZ

PSEN Low to Address Float

TRLRH

RD Pulse Width

400

TWLWH

WR Pulse Width

400

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold After RD

TRHDZ

Data Float After RD

97

2TCLCL - 70

TLLDV

ALE Low to Valid Data In

517

8TCLCL- 150

ns

TAVDV

Address to Valid Data In

585

9TCLCL - 165

ns

TLLWL

ALE Low to RD or WR Low

200

TAVWL

Address Valid to RD or WR Low

203

4TCLCL - 130

ns

TOVWX

Data Valid to WR Transition

23

TCLCL - 60

ns

TWHOX

Data Hold After WR

33

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

10
6TCLCL - 100

ns

6TCLCL - 100

0

ns
5TCLCL - 165

252
0

300

3TCLCL - 50

43

10-64

ns

3TCLCL

+ 50

TCLCL - 50
0
123

ns

ns

ns
0

TCLCL - 40

.ns

TCLCL

ns

+ 40

ns

intJ

80C51BH, -1, -2/80C31BH, -1,-2

EXTERNAL DATA MEMORY READ CYCLE
TWHLH

ALE

---- ---TLLDy----

--TLLWl.-!----TRLAH-t----

------~------,

Ir----------------TAHDZ

-

TRHD. -

-TRLAZ

PORTO

I

--::

DATA IN

------TAyDy-------

AI·A1S FROM PCH

P2.0·P2.7 OR A8·A15 FAOM DPH

PORT 2

270064-6

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE
-TAYLL- - - - - - T P l P H - - -

TLLPL

TLUV

TPXIZI-TPIII-

-

INSTR
IN

POATD

AI-AtS

PORT 2

270064-7

10-65

intJ

80C51BH, "1, -2/80C31BH, -1,-2

EXTERNAL DATA MEMORY WRITE CYCLE
TWHLH

ALE

-TLLWL--j----TWLWH-----

TWHQX

..L
PORTO

PORT 2

DATA OUT

P2.0 - P2.7 OR AI - A15 FROM DPH

INSTR
IN

AI - A15 FROM PCH

270064-8

10-66

inter

80C51BH, -1, -2/80C31BH, -1,-2

.

-

i

L
W
z
§

0

...t.
cO

I

!

I!l

:!

I

]-i!i ]-i

Shift Register Mode Timing Waveforms

10·67

intJ

80C51BH, -1, -2/80C31BH, -1, ~2

EXTERNAL CLOCK DRIVE
"

Symbol

Parameter

1/TCLCL

Min

Max

Oscillator Frequency
80C51 BH/80C31 BH
80C51 BH-1/80C31 BH-1
80C51 BH-2/80C31 BH-2 .

3.5
3.5
0.5

12
16
12

20

Units
MHz

ns

TCHCX

High Time

TCLCX

LciwTime

TCLCH

Rise Time

20

ns

TCHCL

Fall Time

20

ns

..

ns

20

SERIAL TIMING-SHIFT REGISTER MODE
Test Conditions: TA

=

O·C to 70·C; Vee

=

5V ±20%; Vss

Parameter···

Symbol

Min
TXLXL

==

OV; Load Capacitance

12 MHzOsc
Max

=

80 pF

Variable Oscillator
Min

Units

Max

1.0

12TCLCL

p.s

700

10TCLCL - 133

ns

TXHQX Output Data Hold After Clock Rising Edge

50

2TCLCL - 117

ns

TXHDX Input Data Hold After Clock Rising Edge

0

0

ns

Serial Port Clock Cycle Time

TQVXH Output Data Setup to Clock Rising Edge

TXHDV Clock Rising Edge to Input Data Valid

700

10TCLCL - 133

ns

EXTERNAL CLOCK DRIVE WAVEFORM.

270064-10

x=.

AC TESTING INPUT, OUTPUT WAVEFORMS

=>(

vee- o.s
0.45 V

0.2 VCC·+O.9
0.2 VCC-O.l

.

FLOAT WAVEFORMS
VOH-O.l V
TIMING REFERENCE
POINTS
'--_ _ _---,_....J~ VOL +0.1 V

-.-=:.::..------

270064-12

270064-11

For liming purposes a port pin is no longer floating when a
100 mV change .from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH ;;, ± 20 rnA. .

AC Inpuls during testing are driven at Vee -.0.5 for a logic "1"
and 0.45 V for a logic "0". Timing measurements are made at VIH
min. for a logic "1" and Vil max. for a logic "0". .

10-68

80C31 BH/80C51 BH
EXPRESS
•

Extended Temperature Range

•

Burn-In

•

3.5 to 12 MHz Vee = 5V± 20%

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS, products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O°C to 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125°C with Vee = '6.9V ±0.25V, following
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheelspecifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed' here.

10-69

September 1987
Order Number: 270218-002

inter

80C31BH/80C51BH EXPRESS

Electrical Deviations from Commercial Specifications for Extended Temperature.
Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.

D.C. CHARACTERISTICS TA = -40'C to + 85'C; Vcc = 5V ± 20%; Vss = OV
Symbol
VIL
VIL1
VIH
VIH1
IlL
ITL

LImits

Parameter
Input Low Voltage (Except EA)
EA.
Input High Voltage (Except XTAL1, RST)
Input High Voltage to XTAL 1, RST
Logical 0 Input Current (Port 1, 2, 3)
Logical 1 to 0 transition
Current (Ports 1, 2, 3)

Prefix
P
D
N
TP
TO
TN
OP
OD
ON
LP
LD
LN

Min
-0.5
-0.5V

Max
0.2Vcc - 0.15
0.2Vcc - 0.35

0.2Vcc + 1
0.7Vcc + 0.1

VCC + 0.5
Vcc + 0.5
-75
-750

Table 1 Prefix Identification
Package Type
Temperature Range
Plastic
Commercial
Cerdip
Commercial
PLCC
Commercial
Plastic
Extended
Cerdip
Extended
PLCC
Extended
Plastic
Commercial
Cerdip
Commercial
PLCC
Commercial
Plastic
Extended
Cerdip
Extended
PLCC
Extended

Unit

Test
C~mdltlons

V
V
V
,.
V
jJ-A Vin = 0.45V
jJ-A. Yin = 2.0V

Burn-In
No
No
NoNo
No
No
Yes
Yes
Yes
Yes
Yes
Yes

NOTE:
• Commercial temperature range Is O'C to 70'C. Extended temperature range is -40'C to +85'C.
• Burn·in is dynamic for a minimum time of 160 hours at 125'C. Vee = 6.9V ±0.25V. following guidelines in MIL·STO·883 .
Method 1015 (Test Condition OJ.
Examples:
P80C31 BH indicates 80C31 BH in a plastic package and specified for commercial temperature range, without
burn·in.
LD80C51 BH indicates 80C51 BH in a cerdip package and specified for extended temperature range with burn·
in.

. 10·70

87C51/87C51-1/87C51-2
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 4K BYTES OF EPROM PROGRAM MEMORY
87CS1-3.S to 12 MHz, Vee = sv ± 10%
87CS1-1-3.S to 16 MHz, Vee = SV ± 10%
87CS1-2-0.S to 12 MHz, Vee = SV ± 10%

• High Performance CHMOS EPROM

• Programmable Serial Channel

•

Quick-Pulse Programming™ Algorithm

•

2-Level Program Memory Lock

• TTL- and CMOS-Compatible Logic
Levels

•

Boolean Processor

• 64K External Program Memory Space

• 128-Byte Data RAM
• 32 Programmable I/O Lines
• Two 16-Bit Timer/Counters
•

5 Interrupt Sources

•

64K External Data Memory Space

• IDLE and POWER DOWN Modes
• ONCETM Mode Facilitates System
Testing
•

LCC, PLCC, and DIP Packaging
Available

The 87C51 is the EPROM version of the 80C51 BH. It is fabricated on Intel's CHMOS II-E process. It contains
4K bytes of on-chip Program memory that can be electrically programmed, and can be erased by exposure to
ultraviolet light.
The 87C51 EPROM array uses a modified Quick-Pulse programming algorithm, by which the entire 4K-byte
array can be programmed in about 12 seconds.
The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make
this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue. functioning. The Power Down mode saves the
RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.

r----------

~

270147-1

Figure 1. MCS®-S1 Architectural Block Diagram

10-71

October 1987
Order Number: 270147-004

87C51/87C51-1/87C51-2

P"O

vee

P",

PO.O (AOO)

P"2
P,,3

PO.l (ADI)

P"4

PO.3 (AD3)

P"S

PD.4 (AD4)

PO.2 (AD2)

INDEX
CORNER

"": "! "!

"l u

g"l

ii: ii: ii: ii: ii: z > ~

g

.. ..'"
N

d d

P"6

PO.S (ADS)

PO.4

P"7
RESET

PO.6 (AD6)

PO.S

PO.7 (AD7)

(RXD) P3.0

EA/VPP

(TXD) P3.1

ALE/PROG

(INTO) P3.2

PSEN

(INTI) P3.3

P2.7 (A1S)

(TO) P3.4

P2.6 (AI4)

(T1) P3.S

P2.S (AI3)

(Wil) P3.6

P2.4 (AI2)

(Rli) P3.7

P2.3 (All)

PO.7

EA/Vpp

P3.0
NC

XTAL2

P2.2 (AID)

XTALI

P2.1

VSS

PO.6
RST

Ne

P3.1

ALE/PROG

P3.2

PSEN

P3.3

P2.7'

P3~4

P2.6

P3.S

P2.S

(A9)

.'" ..'"

P2.D (AS)

..;

270147-2

~

N

...J

::;

'"'"

>
~ ~
x

x

u

z

o "-:

..

'"
~ ~ N N
N

270147-21

DIP
LCC/PLCC
Figure 2. Pin Connections .

PIN DESCRIPTION·
Vee: Supply voltage during normal, Idle, and Power
Down operations.
Vss: Circuit ground.
Port 0: Port 0 is an a-bit open drain bidirectional 110
port. As an output port each pin can sink a LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this
application it uses strong internal pullups when emitting 1s.
Port 0 also receives the code bytes'during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
Port 1: Port 1 is an a-bit bidirectional I/O port with
internal pullups. Port 1 pins that have .1 s written to
them are pulled high by the internal pullups,and in
that state can be used as inputs. As inputs, Port 1"
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.

Port 2: Port 2 is an a-bit b.idirectional 110 port with
internal pullups. Port 2 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs.. As inputs, Port 2
pins that are externally being pulled IQw will source
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
address (MOVX @DPTR). In this application it uses
strong internal pullups when emitting 1s.
During accesses to external Data Memory that use
a-bit addresses (MOVX @Ri), Port 2 emits the conter)ts of the P2 Special Function Register.
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification.
Port 3: Port 3 is an a-bit bidirectional 110 port with
internal pullups. Port 3 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups..

Port 1 also receives the low-order address bytes
during EPROM programming and program verification.

10-72

inter

87C51/87C51-1/87C51-2

Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Pin

Name

Alternate Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RXD
TXD
INTO
INT1
TO
T1
WR
RD

Serial input line
Serial output line
External Interrupt 0
External Interrupt 1
Timer 0 external input
Timer 1 external input
External Data Memory Write strobe
External Data Memory Read strobe

XTAL2
XTAL 1

...------t vss
270147-3

Figure 3. Using the On-Chip Oscillator

Port 3 also receives some control signals for
EPROM programming and program verification.
RST: Reset input. A logic high on this pin for two
machine cycles while the oscillator is running resets
the device. An internal pulldown resistor permits a
power-on reset to be generated using only an external capacitor to Vee.

EXTERNAL
OSCILLATOR
SIGNAL

ALE/PROG: Address Latch Enable output signal for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during EPROM programming.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
PSEN: Program Store Enable is the Read strobe to
External Program Memory. When the 87C51 is executing from Internal Program Memory, PSEN is inactive (high). When the device is executing code from
External Program Memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to External
Data Memory.
EA/Vpp: External Access enable. EA must be
strapped to Vss in order to enable the 87C51 to
fetch code from External Program Memory locations
OOOOH to OFFFH. Note, however, that if either of the
Lock Bits is programmed, the logic level at EA is
internally latched during reset.
EA must be strapped to Vee for internal program
execution.
This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier and
input to the internal clock generating circuits.
XTAL2: Output from the inverting oscillator amplifier.

NC -

XTAL2

----I

XTAL 1

270147-4

Figure 4. External Clock Drive

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3.
To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.

IDLE MODE
In Idle Mode, the CPU puts itself to sleep while all
the on-chip peripherals remain active. The mode is
invoked by software. The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode. The Idle Mode can be
terminated by any enabled interrupt or by a hardware reset.
It should be noted that when Idle is terminated by a
hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm
takes control. On-Chip hardware inhibits access to
internal RAM in this event, but access to the port

10-73

infef

87C51/87C51-1/87C51-2

Table 1 Status of the external pins during Idle and Power Down
Program
Memory

ALE

PSEN

Idle

Internal

1

1

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Power Down

Internal

0

0

Data

Data

Data

Data

Power Down

External

0

0

Float

Data

Data

Data

Mode

PORTO

PORT1

PORT2

PORT3

NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Application Note AP-252, "Designing with the 80C51BH."

pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that
invokes Idle should not be one that writes to a port
pin or to external memory.

Lock Bits: Also on th'e chip are two Lock Bits which
can be left unprogrammed (U) or can be programmed (P) to obtain the following additional features:
Bit 1

Bit2

Additional Features

POWER DOWN MODE

U

U

none

In the Power Down mode the oscillator is stopped,
and the instruction that invokes Power Down is the
last instruction executed. The on-chip RAM and
Special Function Registers retain their values until
the Power Down mode is terminated.

P

U

• Externally fetched code can not
access internal Program Memory.
• Further programming disabled.

U

P

(Reserved for Future definition.)

P

P

• Externally fetched code can not
access internal Program Memory.
• Further programming disabled.
• Program verification is disabled.

a

The only exit from Power Down is hardware reset.
Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and
must be held active long enough to allow the oscillator to restart and stabilize.

When Lock Bit 1 is programmed, the logic level at
the EA pin is sampled and latched during reset. If
the device is powered up without a reset, the latch
initializes to a random value, and holds that value
until reset is activated. It is necessary that the
latched value of EA be in agreement with the current
logic level at that pin in order for the device to function properly.

DESIGN CONSIDERATIONS
Exposure to light when the device is in operation
may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window
when the die is exposed to ambient light.
If using the 87C51 to prototype for the 80C51 BH,
consult the Design Considerations section of the
80C51 BH data sheet.

ONCETM MODE

PROGRAM MEMORY LOCK
The 87C51 contains two program memory lock
schemes: Encrypted Verify and Lock Bits.
Encrypted Verify: The 87C51 implements a 32byte EPROM array that can be programmed by the
customer, and which can then be used to encrypt
the program code bytes during EPROM verification.
The EPROM verification procedure is performed as
usual, except that each code byte comes out logically X-NORed with one of the 32 key bytes. The key
bytes are gone through in sequence. Therefore, to
read the ROM code, one has to know the 32 key
bytes in their proper sequence.

The ONCE ("on-circuit emulation") mode facilitates
testing and debugging of systems using the 87C51
without the 87C51 having to be removed from the
circuit. The ONCE mode is invoked by:
1. Pull ALE low while the device is in reset and
PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE mode, the PortO pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87C51 is in this mode,
an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal
reset is applied.

10-74

inter

87C51/87C51-1/87C51-2

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O°C to + 70°C
Storage Temperature , ......... - 65°C to + 150°C
Voltage on EAlVpp Pin to Vss ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. -0.5V to +6.5V
Power Dissipation .......................... 1.5W
(Based on package heat transfer limitations, not device power consumption).

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE Specifications contained within the
following tables are subject to change.

D.C. CHARACTERISTICS: (TA = O°Cto +70°C;Vcc = 5V ±10%;Vss = OV)
Symbol

Parameter

VIL

Input Low Voltage (Except EA)

VILl

Input Low Voltage to EA

VIH

Input High Voltage (Except XTAL 1, RST)

VIHl

Input High Voltage (XTAL1, RST)

VOL

Max

Unit

-0.5

Min

Typ(1)

.2Vcc-· 1

V

0

.2Vcc-·3

V

.2Vcc+·9

Vcc+·5

V

0.7Vcc

Vcc+·5

V

Output Low Voltage (Ports 1,2, 3)

0.45

V

VOLl

Output Low Voltage (Port 0, ALE, PSEN)

0.45

V

VOH

Output High Voltage (Ports 1. 2. 3, ALE. PSEN)

Test Conditions

IlL

Logical 0 Input Current (Ports 1. 2. 3)

-50

p.A

= 1.6 rnA (2)
= 3.2 rnA (2)
IOH = -60p.A
IOH = -25p.A
IOH = -10 p.A
IOH = -BOO p.A
IOH = - 300 p.A
IOH = -BO p.A (3)
VIN = 0.45 V

IlL

Logicall-to-O transition current
(Ports 1, 2. 3)

-650

p.A

(4)

ILl

Input Leakage Current (Port 0)

±10

p.A

Icc

Power Supply Current:
Active Mode @ 12 MHz (5)
Idle Mode @ 12 MHz (5)
Power Down Mode

25
4
50

rnA
rnA
p.A

300

kfl

_10

pF

VOHl

Output High Voltage (Port 0 in
External Bus Mode)

2.4

V

.75Vcc

V

.9Vcc

V

2.4

V

.75Vcc

V
V

.9Vcc

RRST

Internal Reset Pulldown Resistor

CIO

Pin Capacitance

11.5
1.3
3
50

IOL
IOL

VIN

= VIL or VIH
(6)

NOTES:
1. "Typicals" are based on a limited 'number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp. 5V.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1to-O transitions during bus operations. In the worst cases (capacitive loading> 100pF). the noise pulse on the ALE pin may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger. or use an address latch with a Schmitt
Trigger STROBE input.
'
,
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vcc specification when the address bits are stabilizing.
4. Pins of Ports 1. 2. and 3 source a transition current when they are being externally driven from 1 to O. The transition
current reaches its maximum value when VIN is approximately 2V.
5. IccMAX at other frequencies is given by:

Active Mode: IccMAX = 0.94 x FREQ
Idle Mode:
IccMAX = 0.14 x FREQ

+ 13.71
+ 2.31

where FREQ is the external oscillator frequency in MHz. IccMAX is given in mAo See Figure 5.
6. See Figures 6 through 9 for Icc test conditions.

10-75

87C51/87C51·1/87C51·2

30

IIAX
ACTIVE IIODE

25
RST
20
XTAL2
XTALI

I

VSS

'"E

u
!.!

270147-18
10

Figure 7. Icc Test Condition, Idle Mode.
All other pins are disconnected.

5~--~~+---+---~

TYP(1)

~=±::::::::±:=:t:=J IDLE MODE
4_

SMHz

1211Hz 16MHz

FREQ AT XTAL1 .

270147-16
RST

Figure 5. Icc vs. FREQ. Valid only
within frequency specifications of the
device under test.

XTAL2
XTALI
VSS

270147-20

Figure 9. Icc Test Condition, Power Down
Mode. All other pins are disconnected.
Vce = 2V to 5.5V.
RST

XTAL2
XTALI

Vss
270147-17

Figure 6. Icc Test Condition, Active Mode.
All other pins are disconnected.

270147-19

Figure 8. Clock Signal Waveform for
Icc tests In Active and Idle Modes.
TCLCH = TCHCL = 5 ns.

10-76

inter

87C51/87C51-1/87C51-2

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'r (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they ~tand for.
A:Address.
C:Clock.
D:lnput data.
, H:Logic level HIGH.
1:lnstriJction (program memory contents).

L:Logic level LOW, or ALE.
P:PSEN.
O:Output data.
R:RD signal.
T:Time.
V:Valid.
W:WR signal.
X:No longer a valid logic level.
Z:Float.
For example,
TAVLL
TLLPL

= Time from Address Valid to ALE Low.
=

Time from ALE Low to PSEN Low.

A.C. CHARACTERISTICS: (TA = O°C to + 70°C; Vee = 5V ± 10%; Vss = OV; Load Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol

Parameter

1/TCLCL

Oscillator Frequency
87C51
87C51-1
87C51-2
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instr In
Input Instr Hold After PSEN
Input Instr Float After PSEN
Address to Valid Instr In
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD
Data Float After RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Hold After WR
RD Low to Address Float
RD or WR High to ALE High

TLHLL
TAVLL
TLLAX
TLLlV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TAVIV
TPLAZ
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TWHOX
TRLAZ
TWHLH

12 MHz Oscillator
Max
Min

Variable Oscillator
Min
Max

3.5
3.5
0.5
2TCLCL:"-40
TCLCL-55
TCLCL-35

127
28
48

12
16
12

4TCLCL-100

234
TCLCL-40
3TCLCL-45

43
205

3TCLCL-105

145
0

0

TCLCL-25
5TCLCL-105
10

59
312
10
6TCLCL-100
6TCLCL-100

400
400

5TCLCL-165

252
0

0
97
517
585
300

200
203
23
33

0
123·

43

10-77

3TCLCL-50
4TCLCL-130
TCLCL-60
TCLCL-50
TCLCL-40

2TCLCL-70
8TCLCL-150
9TCLCL-165
3TCLCL+50

0
TCLCL+40

Units

MHz

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

inter

87C51/87CS1-1/87C51-2

ALE _ _J

PSEiii

---

PORT 0

......._ - - '

PORT 2

_ _ _J

AB-A15
270147-5

External Program Memory Read Cycle

ALE

PSEN

I------TLLDV----I'I
----I~---

TRLRH

-----I

PORTO

INSTR. IN
TAVDV

PORT2

P2.0-P2.7 OR AB-A15 FROM DPH

AB-A15 FROM PCH
270147-6

External Data Memory Read Cycle

ALE

PSEN
TLLWL ----1"'1---- TWLWH

PORTO

-

--'----I

DATA OUT

FROM RI OR DPL

INSTR. IN

~---TAVWL---~

PORT 2

P2.0-P2.7 ORAB-A15 FROM DPH

A8-A 15 FROM PCH
270147-7

External Data Memory Write Cycle

10-78

intJ

87C51/87C51-1/87C51-2

EXTERNAL CLOCK DRIVE
Symbol

Parameter

EXTERNAL CLOCK DRIVE WAVEFORM
Min Max Units

1/TCLCL Oscillator Frequency
87CS1
87CS1-1
87CS1-2

3.S
3.S
O.S

12
16
12

MHz

TCHCX

High Time

20

ns

TCLCX

Low Time

20

ns

TCLCH

Rise Time

20

ns

TCHCL

Fall Time

20

ns

270147-8

SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol

12 MHz
Oscillator

Parameter

Min

Variable Oscillator

Max

Min

Units

Max

TXLXL

Serial Port Clock Cycle Time

1.0

12TCLCL

/ls

TOVXH

Output Data Setup to Clock Rising Edge

700

1OTCLCL -133

ns

TXHOX

Output Data Hold After Clock Rising Edge

SO

2TCLCL-117

ns

TXHDX

Input Data Hold After Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to Input Data Valid

1OTCLCL - 133

700

ns

SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION

I

4

5

7.

ALE

CLOCK

OUTPUT DATA

"-----.,."'-----rJ "----_...JX....._-...JX....._-...JX....._-...JX....._-...JX"----_...J!

10

WRITE
'SBUF
INPUT DATA -----"'""'\.,-'"""\,,-"""1... C":":':'r-'r,.,..",'r---,.r:-:-=\,,...-...r:-~~--...r-c:""',,.-. .

I

SET TI
,,.,,.,.:=...,-.. . .,.,,.,.,=",

I.

I

CLEAR RI

SET RI
270147-9

A.C. TESTING:
INPUT, OUTPUT WAVEFORMS

VCC-0.5~ 0.2Vcc+0.9
_ 0.2 Vce-0.1
0.45V ,

FLOAT WAVEFORM

>C
•

~.....;;.;.....-----....

270147-10

270147-11
For timing purposes a port pin is no longer floating when a 100
mV change from load voltage occurs, and begins to float when a
100 mV change from the loaded VOHIVOL level occurs. IOLlioH
;, ±20 rnA.

AC inputs during testing are driven at Vee - 0.5 for a Logic "1"
and 0.45V for a Logic "0." Timing measurements are made at VIH
min for a Logic "I" and VIL max for a Logic "0".

10-79

inter

87C51/87C51-1/87C51-2

to identify the device. The Signature bytes identify
the device as an 87C51 manufactured by Intel.

EPROM CHARACTERISTICS
The 87C51 is programmed by a modified QuickPulse Programming™ algorithm. It differs from Older
methods in the value used for Vpp (Programming
Supply Voltage) and in the width and number of the
ALE/PROG pulses.

Table 2 shows the logic levels for reading the signature byte, and for programming the Program Memory, the Encryption Table, and the Lock Bits. The circuit configuration and waveforms for Quick-Pulse
Programming™ are shown in Figures 10 and 11.
Figure 12 shows the circuit configuration for· normal
Program Memory verification.

The 87C51 contains two signature bytes that can be
read and used by an EPROM programming system

Table 2. EPROM Programming Modes
MODE

RST

PSEN

ALEI
PROG

EAI
Vpp

P2.7

P2.6

P3.7

P3.6

Read Signature

1

0

1

1

0

0

0

0

Program Code Data

1

0

O·

Vpp

1

0

1

1

Verify Code Data

1

0

1

1

0

0

1

1

Pgm Encryption Table

1

0

O·

Vpp

1

0

1

0

Pgm Lock Bit 1

1

0

o·

Vpp

1

1

1

1

Pgm Lock Bit 2

1

0

O·

Vpp

1

1

0

0

NOTES:

(

,

"1" = Valid high for that pin
"0" = Valid low for that pin
Vpp = 12.7SV ± 0.2SV
Vcc = SV ± 10% during programming and verification
*ALE/PROG receives 25 programming pulses while Vpp is held at 12.75V. Each programming pulse is low for 100 ILS{± 10
ILS) and high for a minimum of 10 ILS,

+5V

vee
AO-A7

Pl

PO

RST

P3.6

EA/Vpp
ALE/PROG
87C51

P3.7

PSEN

PGM DATA

+12.75V
25 100)'$ PULSES TO GND
0

P2.7

XTAL2

P2.6

XTAL 1

P2.0
-P2.3

0

A8-All

Vss
270147-12

Figure 10. Programming Configuration

10-80

inter

87C51/87C51-1/87C51-2

,'------25 PULSES

"

1 ..

ALE/PROG:~-----~
'-----'

1'-..
ALE/PROG:

10}'s

I.41N1 "

100!:!s
:t 10}'s

n

aI

"

n

270147-13

Figure 11. PROG Waveforms

Quick-Pulse Programming™
The setup for Microcontroller Quick-Pulse ProgrammingTM is shown in Figure 10. Note that the 87C51
is running with a 4 to 6 MHz oscillator. The reason
the oscillator needs to be running is that the device
is executing internal address and program data
transfers.
The address of the EPROM location to be programmed is applied to Ports 1 and 2, as shown in
Figure 10. The code byte to be programmed into
that location is applied to Port O. RST, PSEN, and
pins of Ports 2 and 3 specified in Table 2 are held at
the "Program Code Data" levels indicated in Table
2. Then ALE/PROG is pulsed low 25 times as
shown in Figure 11.

through 1FH, using the "Pgm Encryption Table" levels. Don't forget that after the Encryption Table is
programmed, verify cycles will produce only encrypted data.
To program the Lock Bits, repeat the 25-pulse programming sequence using the "Pgm Lock Bit" levels. After one Lock Bit is programmed, further programming of the Code Memory and Encryption Table is disabled. However, the other Lock Bit can still
be programmed.
Note that the EA/vpp pin must not be allowed to go
above the maximum specified Vpp level for any
amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The Vpp source should be well regulated and
free of glitches and overshoot.

To program the Encryption Table, repeat the 25pulse programming sequence for addresses 0

10-81

intJ

87C51/87C51-1/87C51-2

+sv

AO-A7

1---1-1' PGt.!

PI

1 - - - . / DATA

RST

EA/Vpp
ALE/PROG

P3.6

B7CSI
P3.7

PSEN 1+---0
P2.7 ....- - 0

(ENABLE)

P2.6 ....- - 0

XTAL2

""''''-r-l XTAL 1
vSS
270147-14

Figure 12. Program Verification

Program Verification

Program/Verify. Algorithms

If Lock Bit 2 has not been programmed, the on-chip
Program Memory can be read out for program verification. The address of the Program Memory location
to be read is applied to Ports 1 ·and 2 as shown in
Figure 12. The other· pins are held at the "Verify
Code Data" levels indicated in Table 2. The contents of the addressed location will be emitted on
Port O. External pullups ·are required on Port 0 for
this operation. Detailed timing specifications are
shown in later sections of this data sheet.

Any algorithm in agreement with the conditions listed in Table 2, and wliich satisfies the timing specifi.
cations, is suitable.

Erasure Character.istics
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.

If the Encryption Table has been programmed, the
data presented at Port 0 will be the Exclusive NOR
of the program byte with one of the encryption bytes.
The user will have to know the Encryption Table
contents in order to correctly decode the verification
data. The Encryption Table itself can not be read
out.

Reading the Signature Bytes
The Signature bytes are read by the same procedure
as a normal verification of locations 030H and 031 H,
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
(030H)

=

(031 H)

= 57H indicates 87C51

The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 p.W/cm 2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all 1s state..

89H indicates manufactured by Intel

10·82

inter

87C51/87C51-1/87C51-2

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS:
(TA = 21°C to 27°C, vee = 5V ±10%, VSS = OV)

Symbol

Parameter

Min

Max

Vpp

Programming Supply Voltage

12.5

13.0

V

Ipp

Programming Supply Current

50

mA

6

MHz

1/TCLCL

Oscillator Frequency

TAVGL

Address Setup to PROG Low

TGHAX

Address Hold After PROG

48TCLCL

TDVGL

Data Setup to PROG Low

48TCLCL

4

Units

48TCLCL

TGHDX

Data Hold After PROG

48TCLCL

TEHSH

P2.7 (ENABLE) High to Vpp

48TCLCL

TSHGL

Vpp Setup to PROG Low

10

fJ-s

TGHSL

Vpp Hold After PROG

10

fJ-s

TGLGH

PROGWidth

90

TAVQV

Address to Data Valid

48TCLCL

TELQV

ENABLE Low to Data Valid

48TCLCL

TEHQZ

Data Float After ENABLE

0

TGHGL

PROG High to PROG Low

10

110

fJ-s

48TCLCL
fJ-s

EPROM Programming and Verification Waveforms
PROGRAMMING-

Pl.0-Plo7
P2.D-P2.3

VERIFICATION-

ADDRESS

ADDRESS
-TAVQY

PORT 0

DATA IN

-I

TDVGL

DATA OUT

~ TGHDX

~

TAVGL ALE/Pi!OO

t-

TSHGL-~:"
-

- TGLGH

TGHAX

_TGHGL
1 _ TGHSL

J
----P2.7
(ENABLE)

LOGIC I
________

LOGIC 1
____

~G~Q

·1. -TEHSH

TELQV-

----,--If

---- ------

-

I-TEHQZ

270147-15
'FOR PROGRAMMING CONDITIONS SEE FIGURE 10.
FOR VERIFICATION CONDITIONS SEE FIGURE 12.

10-83

inter

87C51

EXPRESS
•

Extended Temperature Range

•

Burn-In

•

3.S MHz to 12 MHz Vee

=

SV

± 10%

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-51 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in and an extended
temperature range with or without burn-in.
With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of O'C to + 70·C. With the extended temperature range option, operational characteristics are
guaranteed over the range' of - 40'C to + 85·C.
The optional burn-in is dynamic for a minimum time of 160 hours at 125'C with Vee
guidelines in MIL-STD-883, Method 1015.

= 6.0V ± 0.25V, following

Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this data sheet specifies the parameters which deviate from their
commercial temperature range limits. The commercial temperature range data sheets are applicable for all
parameters not listed here.

10-84

October 1987
Order Number: 270430-001

87C51 EXPRESS

Electrical Deviations from Commercial Specifications
for Extended Temperature Range
D.C. and A.C. parameters not included here are the same as in the commercial temperature range data
sheets.

D.C. CHARACTERISTICS
Symbol

TA

=

-40·Cto

+ 85·C; Vee =

5V ±10%;Vss

=

OV

Limits

Parameter

VIL

Input Low Voltage (Except EA)

VIL1

EA

VIH

Input High Voltage (Except XTAL 1, RST)

VIH1

Input High Voltage to XTAL 1, RST

Unit

Min

Max

-0.5

0.2Vee - 0.15

V

0

0.2Vee - 0.35

V

+1
+ 0.1

0.2Vee
0.7Vee

Vee
Vee

+ 0.5
+ 0.5

Test
Conditions

V
V

IlL

Logical 0 Input Current (Port 1, 2, 3)

-75

/LA

VIN

ITL

Logical 1 to 0 transition
Current (Ports 1, 2, 3)

-750

/LA

VIN

Icc

Power Supply Current
Active Mode
Idle Mode
Power Down Mode

35

mA
mA
/LA

= 0.45V
= 2.0V

(Note 1)

6
50

NOTE:
1. Vee = 4.5V-5.5V, Frequency Range = 3.5 MHz-12 MHz.

10-85

87C51 EXPRESS

Table 1 Prefix Identification
Prefix

Package Type

Temperature Range(2)

Burn-ln(3)

P

Plastic

Commercial

No

D

Cerdip

Commercial

No

N

PLCC

Commercial

No

R

LCC

Commercial

No

TP

Plastic

Extended

No

TO

Cerdip

Extended

No

TN

PLCC

Extended

No

TR

LCC

Extended

No

OP

Plastic

Commercial

Yes

OD

Cerdip

Commercial

Yes

ON

PLCC

Commercial

Yes

OR

LCC

Commercial

Yes

LP

Plastic

Extended

Yes

LD

Cerdip

Extended

Yes

LN

PLCC

Extended

Yes·

LR

LCC

Extended

Yes

NOTES:
2. Commercial temperature range is O'C to + 70'C. Extended temperature range is - 40'C to + 85'C.
3. Burn-in is dynamic for a minimum time of 160 hours at .+ 125'C, Vee = 6.0V ±0.25V, following guidelines in MIL-STD883 Method 1015 (Test Condition D).

Examples:
P87C51 indicates 87C51 in a plastic package and specified for commercial temperature range, without burn-in.
LD87C51 indicates 87C51 in a cerdip package and specified for extended temperature range with burn-in.
/

10-86

inter

87C51FA (87C252)
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH
PROGRAMMABLE COUNTER ARRAY, UP/DOWN
COUNTER, 8K BYTES USER PROGRAMMABLE EPROM

•
•
•
•

•
•
•
•
•
•

High Performance CHMOS EPROM.
Power Control Modes
Three 16-Bit Timer/Counters
Programmable Counter Array with:
- High Speed Output,
- Compare/Capture,
- Pulse Width Modulator,
- Watchdog Timer capabilities
Up/Down Timer/Counter
Two Level Program Lock System
8K On-Chip EPROM
256 Bytes of On-Chip Data RAM
Quick Pulse Programming™ Algorithm
Boolean Processor

•

32 Programmable I/O Lines

• Programmable Serial Channel with:
• - Framing Error Detection
7 Interrupt Sources

- Automatic Address Recognition

•
•
•
•
•
•

TTL Compatible Logic Levels
64K External Program Memory Space
64K External Data Memory Space
MCS®-51 Fully Compatible Instruction
Set
Power Saving Idle and Power Down
Modes
ONCETM (On-Circuit Emulation) Mode

MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 8K bytes of the program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64K bytes of
external data memory.
.
The Intel 87C51 FA is a single-chip control oriented microcontroller which is fabricated on Intel's reliable
CHMOS II-E technology .. Being a member of the MCS®-51 family, the 87C51 FA uses the same powerful
instruction set, has the same architecture, and is pin for pin compatible with the existing MCS-51 products. The
87C51 FA is an enhanced version of the 87C51. It's added features make it an even more powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O, and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multi-processor communications.

10-87 .

October 1987
Order Number: 270258-002

87C51FA

PO.0-PO.7

,.----------~~~..:..~

~~

-------- ..

VSS

..r

Pmi
ALE/I'l!l!ll
£A/VPP
RST

z
TIMING

~

~IC==~~=~====~:;:=~==::::===::;::~==J
p::

AND
::>
CONTROL
~
~

;:;

P1.0- P1.7

P3.0-P3.7

270258-1

Figure 1. 87C51FA Block Diagram

10·88

inter

87C51FA

In addition, Port 1 serves the functions of the following special features of the a7C51 FA:

PIN DESCRIPTIONS
(T2) PLO

Port Pin

Vee

(T2EX) Plol

PO.O (ADO)

(ECI) Plo2

PO.l (AD1)

(CEXO) Pl.3

PO.2 (AD2)

(CEX1) Plo4

PO.3 (AD3)

(CEX2) Pl.S

PO.4 (AD4)

(CEX3) Pl.S

PO.S (ADS)

(CEX4) Pl.7

PO.S (ADS)

RESET

PO.7 (AD7)

(RXD) P3.0

EA/Vpp

(TXD) P3.l

ALE/PROG

(iNTO) P3.2

PSEN

(iNT1) P3.3

P2.7 (A1S)

(TO) P3.4

P2.S (A14)

(n) P3.S

P2.S (A13)

(ViR) P3.S

P2.4 (A12)

(Rii) P3.7

P2.3 (All)

XTAL2

P2.2 (Al0)

XTALl

P2.l

Vss

Alternate Function

P1.0

T2 (External Count Input to Timerl
Counter 2)

P1.1

T2EX (Timer/Counter 2 Capturel
Reload Trigger and Direction Control)

P1.2

ECI (External Count Input to the PCA)

P1.3

CEXO (External 1/0 for Comparel
Capture Module 0)

P1.4

CEX1 (External 1/0 for Compare/
Capture Module 1)

P1.5

CEX2 (External 1/0 for Comparel
Capture Module 2)

P1.6

CEX3 (External I/O for Comparel
Capture Module 3)

P1.7

CEX4 (External 1/0 for Comparel
Capture Module 4)

Port 1 receives the low-order address bytes during
EPROM programming and verifying.

(A9)

P2.0 (AB)

Port 2: Port 2 is an a-bit bidirectional 1/0 port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.

270258-2

Figure 2. Pin Connections

Vee: Supply voltage.
Vss: Circuit ground.
Port 0: Port 0 is an a-bit, open drain, bidirectional 1/0
port. As an output port each pin can sink several LS
TIL inputs. Port 0 pins that have 1's written to them
float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting1's, and can source and
sink several LS TIL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistor~ are required during program verification.
Port 1: Port 1 is an a-bit bidirectional 1/0 port with
internal pullups. The Port 1 output buffers can drive
LS TIL inputs. Port 1. pins that have 1's written to
them are pulled high by the internal pull ups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.

Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use a-bit
addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an a-bit bidirectional 1/0 port with
internal pullups. The Port 3 output buffers can drive
LS TIL inputs. Port 3 pins that have 1's written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.

10-a9

intJ

87C51FA

Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port Pin

Alternate Function

P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INT1 (external interrupt 1)
TO (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)

QSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information. concerning
the use of the on-chip oscillator is available in Application Note AP-155, "Oscillators for Microcontrolc
lers."
To drive the device from an external clock source,
XTAL1 should be driven, whileXTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.

RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. An internal pulldown resistor permits a poweron reset with only a capacitor connected to Vee.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C51 FA.

C2

I - - t - - - I XTAL2.

1 - -.....--1

In normal operation ALE is emitted at a constant
rate of % the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

XTAL 1

t - - - - - - - I Vss
270258-3
C1, C2 = 30 pF ± 10 pF for Crystals
= 10 pF for Ceramic Resonators

Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.

Figure 3. Oscillator Connections

PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the 87C51FA is executing code from external
Program Memory, PSEN is activated twice.each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.

N/C

XTAL2

EXTERNAL
OSCILLATOR
SIGNAL

XTAL 1

Vss

EAlVpp: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
OOOOH to 1FFFH. Note, however, that if either of the
Program Lock bits are programmed, EA will be internally latched on reset. .
EA should be strapped to Vee for internal program
executions.
.
This pin also receives the programming supply voltage (Vpp) during EPROM programming.
XTAL 1: Input to the inverting oscillator amplifier.

270258-4

Figure 4. External Clock .Drive Configuration

IDLE MODE
The user's software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops execiJting instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.

XTAL2: Output from the inverting oscillator amplifier.
10-90

intJ

87C51FA

POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
On the 87C51 FA either a hardware reset or an external interrupt can cause an exit from Power Down.
Reset redefines all the SFRs but does not change
the on-chip RAM. An external interrupt allows both
the SFRs and on-chip RAM to retain their values.
The interrupt must be enabled and configured as
level sensitive. To properly terminate Power Down
the reset or external interrupt should not be executed before Vee is restored to its normal operating
level, and must be held active long enough for the
oscillator to restart and stabilize.

DESIGN CONSIDERATION
• Ambient light is known to affect the internal RAM
contents during operation. If the 87C51 FA application requires the part to be run under ambient
lighting, an opaque label should,be placed over
the window to exclude light.

• When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.

ONCETM MODE
The ONCE ("On-Circuit Emulation") Mode facilitates
testing and debugging of systems using the
87C51 FA without the 87C51 FA having to be removed from the circuit. The ONCE Mode is invoked
by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87C51 FA is in this
mode, an emulator or test CPU can be used to drive
the circuit. Normal operation is restored when a normal reset is applied.

Table 1. Status of the External Pins during Idle and Power Down
Program
Memory

ALE

PSEN

Idle

Internal

1

1

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Mode

PORTO

PORT1

PORT2

PORT3

Power Down

Internal

0

0

Data

Data

Data

Data

Power Down

External

0

0

Float

Data

Data

Data

NOTE:
For more detailed information on the reduced power modes refer to current Embedded Controller Handbook, and Application Note AP-252, "Designing with the 80C51BH."

10-91

inter

87C51FA

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage t'o the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O°C to + 70°C
Storage Temperature .......... - 65°C to + 150°C
Voltage on EAlVpp Pin to VSS ....... OV to + 13.0V
Voltage on Any Other Pin to Vss .. - 0.5V to + 6.5V
Power Dissipation .......................... 1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)

NOTICE Specifications contained within the
. following tables are subject to change.

ADVANCED INFORMATION-CONTACT
INTEL FOR DESIGN-IN INFORMATION
.
.
.
D.C. CHARACTERISTICS:
Symbol

(TA

=

,
O°Cto +70°C'Vcc

Parameter

=

Min

,
5V +10%'VsS
-

=

OV)

Max

Unit

-0.5

0.2Vcc-0.1

V

0

0.2 Vcc-0.3

V

0.2Vcc+0.9

Vcc+0.5

V

0.7Vcc

Vcc+ 0.5

V

Test Conditions

VIL

Input Low Voltage

VIL1

Input Low Voltage EA

VIH

Input High Voltage
(Except XTAL2, RST, EA)

VIH1

Input High Voltage
(XTAL, RST)

VOL

Output Low Voltage
(Ports 1 , 2 and 3)

0.45

V

IOL

=

1.6 mA(1)

VOL1

Output Low Voltage _ _
(Port 0, ALE/PROG, PSEN)

0.45

V

IOL

=

3.2 mA(1)

VOH

Output High Voltage
(Ports 1 , 2 and 3
ALE/PROG and PSEN)

2.4

V

IOH

=

-60,..,A

0.9Vcc

V

IOH

VOH1

2.4

V

IOH

0.9VCC

V

IOH

=
=
=
=

-10,..,A(2)

Output High Voltage

0.45V

(Port 0 in Exfernal Bus Mode)

-800,..,A
-80,..,A(2)

IlL

Logical 0 Input Current
(Ports 1 , 2, and 3)

-50

,..,A

VIN

III

Input leaka~Current
(Port 0 and EA)

±10

,..,A

VIN

=

VIL or VIH

ITL

Logical 1 to 0 Transition Current
(Ports 1, 2, and 3)

-650

,..,A

VIN

=

2V

225

KO

10

pF

RRST

RST Pulldown Resistor

CIO

Pin Capacitance

Icc

Power Supply Current:
Running at 12 MHz (Figure 5)
Idle Mode at 12 MHz (Figure 5)
Power Down Mode

40

@1MHz, 25°C
(Note 3)

30
7.5
100

rnA
mA
,..,A

NOTES:

1. Capacitive loading on Ports a and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port a and Port 2 pins when these pins make 1 to
a transitions during bus operations. In applications where capacitance loading exceeds 1aa pFs, the noise pulse on the ALE
signal may exceed a.BV. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger. or use an Address Latch
with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports a and 2 cause the VOH on ALE and PSEN to drop below the a.9 Vee specification when the
address lines are stabilizing.
3. See Figures 6-9 for test conditions.
10-92

intJ

87C51FA

40mA

"'AX.

30mA

ACTIVE
20mA

V

V_ V -

RST
TYPICAL
B7C51FA

....

--

IOmA

r-'DLE

OmA

OMHz

4t.1Hz

XTAL2
XTALl

MAX.
TYPICAL

vss
StAHz

12MHz

16MHz

270258-5

270258-6

ICC Max at other frequencies is given by:
Active Mode
Icc MAX = 2.2 X FREQ + 3.1
Idle Mode
Icc MAX = 0.49 x FREQ + 1.6
Where FREQ is in MHz, IccMAX is given in rnA.

All other pins disconnected
TCLCH = TCHCL = 5 ns

Figure 6. Icc Test Condition, Active Mode

Figure 5. Icc vs Frequency

RST
B7C252
XTAL2
XTALf

Vss

270258-7

270258-8

All other pins disconnected
TCLCH = TCHCL = 5 ns

All other pins disconnected

Figure 9. Icc Test Condition, Power Down Mode.
Vcc = 2.0V to 5.5V.

Figure 7. ICC Test Condition Idle Mode

Vee· a.s • - - - - - -~~----..,.
a.7 vee
a.4SV ---1(a;2 vce-a.t
TCHCL

270258-19

Figure S. Clock Signal Waveform for Icc Tests In Active and Idle Modes. TClCH

10-93

=

TCHCl

=

5 ns.

inter

87C51FA

L: Logic level LOW, or ALE
P:PSEN
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
0: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)

For example,
TAVLL
TLLPL

= Time from Address Valid to ALE Low
= Time from ALE Low to PSEN Low

A.C. CHARACTERISTICS (TA = o·C to + 70·C, Vee = 5V ± 10%, Vss = OV, Load Capacitance for
Port 0, ALE/PROG and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF)

ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol

Parameter

12 MHz Oscillator
Min
Max

1/TCLCL Oscillator Frequency

Variable Oscillator
Min
Max
3.5

TLHLL

ALE Pulse Width

127

TAVLL

Address Valid to ALE Low

28

2TCLCL-40
TCLCL-55

~LLAX

Address Hold After ALE Low

48

TCLCL-35

~LLlV

ALE Low to Valid Instruction In

TLLPL

ALE Low to PSEN Low

43

TCLCL-40

~PLPH

PSEN Pulse Width

205

3TCLCL""""45

TPLIV

PSEN Low!o Valid Instruction In

~PXIX
~PXIZ
TAVIV
TPLAZ
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX

Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Address to Valid Instruction In
PSEN Low to Address Float

ns
ns
ns
ns
ns

59

TCLCL-25

ns

312

5TCLCL-105

ns

10

10

ns

6TCLCL-100

WR Pulse Width

400

6TCLCL-100

Data Hold After RD

ns

0

400

RD Low to Valid Data In

ns

3TCLCL-105

RD Pulse Width

ns
5TCLCL-165

252
0

ns

0

ns
ns

Data Float After RD

97

2TCLCL-70

ns

ALE Low to Valid Data In

517

8TCLCL-150

ns

Address to Valid Data In

585

9TCLCL-165

ns

300

3TCLCL-50 3TCLCL+50

ns

ALE Low to RD or WR Low

200

Address Valid to WR Low

203

4TCLCL-130

ns

Address Valid before WR

23

TCLCL-60

ns

~WHQX Data Hold after WR
TRLAZ

145

MHz
ns

4TCLCL-100

234

0

12

Units

TWHLH RD or WR High to ALE High

TCLCL-50

33

RD Low to Address Float

0
43

10-94

123

TCLCL-40

ns
0

ns

TCLCL+40

ns

inter

87C51FA

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE _ _J

PSEN

PORT

a

_ _J

----'

PORT 2 _ _ _J

AB-A15

270258-9

EXTERNAL DATA MEMORY READ CYCLE
ALE

PSEN

1 - - - - - - TLLDV
'I
---0-1---- TRLRH _ - - - I

RD

PORTO

PORT2

INSTR. IN

P2.0-P2.7 OR AB-A15 FROM DPH

AB-A15 FROM PCH

270258-10

EXTERNAL DATA MEMORY WRITE CYCLE
ALE

TLLWL--~---TWLWH---I

I---+---TQVWH - - - - - i
PORTO

PORT2

],--~~-""""Ii.

DATA OUT

P2.0-P2.7 OR AB-A15 FROM DPH

INSTR. IN

AB-A 1 5 FROM PCH

270258-11

10-95

inter

87C51FA

SERIAL PORT TIMING - SHIFT REGISTER MODE
Test Conditions: TA = O·C to + 70·C; vee = 5V +
- 10%; Vss = OV; Load Capacitance = 80 pF
Symbol

Variable Oscillator
Max
Min

12 MHz Oscillator
Min
Max

Parameter

Units

TXLXL

Serial Port Clock Cycle Time

1

12TCLCL

TQVXH

Output Data Setup to Clock
RiSing Edge

700

1OTCLCL -133

IJ.s
ns

TXHQX

Output Data Hold after
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After Clock
Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to Input
Data Valid

1OTCLCL -133

700

SHIFT REGISTER MODE TIMING WAVEFORMS

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TCLCL

Oscillator Frequency

3.5

12

MHz

TCHCX

High Time

20

ns

TCLCX

Low Time

20

ns

TCLCH

Rise Time

20

ns

TCHCL

Fall Time

20

ns

EXTERNAL CLOCK DRIVE WAVEFORM

270258-13

10-96

ns

inter

87C51FA

A.C. TESTING INPUT
Input, Output Waveforms

>C

VCC-0.5-=::X: 0.2 VCC+0.9
0.45 V

Float Waveforms

0.2 VCC-O.l

VOH-D.l V

TIMING REFERENCE
POINTS

VOL +0.1 V
270258-15
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOl level occurs.
IOl/lOH ;, ± 20 mA.

270258-14
AC Inputs during testing are driven at Vee-0.5V for a Logic "1"
and 0.45V for a Logic "0". Timing measurements are made at V,H
min for a Logic "1" and VOL max for a Logic "0".

EPROM CHARACTERISTICS
Table 2 shows the logic levels for programming the
Program' Memory, the Encryption Table, and the
Lock Bits and for reading the signature bytes.
Table 2. EPROM Programming Modes
Mode

RST

PSEN

ALEI
PROG

EAI
Vpp

P2.7

P2.6

P3.6

P3.7

Program Code Data

1

0

O·

Vpp

1

0

1

1

Verify Code Data

1

0

1

1

0

0

1

1

Program Encryption Table
Use Addresses 0-1 FH

1

0

O'

Vpp

1

0

0

1

Program Lock
Bits (LBx)

1
1

0
0

O'
O'

Vpp
Vpp

1
1

1
1

1
0

1
0

1

0

1

1

0

0

0

0

Read Signature

x=1
x=2

NOTES:
"1" = Valid high for that pin
'0" = Valid low for that pin
"VPP" = +12.75V ±0.25V
• ALE/PROG is pulsed low for 100 /Jos for programming. (Quick·PulseProgramming™)

PROGRAMMING THE EPROM
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appro·
priate internal EPROM locations.) The address of an
EPROM location to be programmed is applied to
Port 1 and pins P2.0 • P2.4 of Port 2, while the code
byte to be programmed into that location is applied
to Port O. The other Port 2 and 3 pins, RST PSEN,
and EAIVpp should be held at the "Program" levels
indicated in Table 2. ALE/PROG is pulsed low to
program the code byte into the addressed EPROM
location. The setup is shown in Figure 10.

Normally EAIVpp is held at logic high un_!!!...iust before ALE/PROG is to be pulsed. Then EAIVpp is
raised to Vpp, ALE/PROG is pulsed low, and then
EAIVpp is returned to a valid high Voltage. The volt·
age on the EAIVpp pin must be at the valid EAIVpp
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.
Note that the EAIVpp pin must not be allowed to go
above the maximum specified Vpp level for any
amount of time. Even a narroW glitch above that voltage level can cause permanent damage to the de·
vice. The Vpp source should be well regulated and
free of glitches.

10·97

intJ

87C51FA

+5V
Vee
AO-A7

P1

PO

RST

PGM DATA

EA/Vpp ....--+12.75V
ALE/PROG ....- - 2 5 100}-" PULSES TO GND

P3.6

87C51FA
P3.7

PSEN 1+---0
P2.7
P2:6 ....- - 0

XTAL2

\
P2.0
-P2.4

. XTAL 1.
Vss

270258-20

Figure 10. Programming the EPROM

Quick-Pulse Programming™ Algorithm

Program Verification

The 87C51 FA can be programmed using the Quick. Pulse Programming™ Algorithm for microcontrollers. The fe.?tures of the new programming method
area lower Vpp (12.75V as compared to 21V) and a
shorter programming pulse. It is possible to program
the entire 8K Bytes of EPROM memory in less than
25 seconds with this algorithm!
To program the part using the new algorithm, Vpp
must be 12.75V ±0.25V. ALE/PROG is pulsed low
for 100 ,..,S, 25 times as shown in Figure 11. Then,
the byte just programmed may be verified. After programming, the entire array should be ver.ified. The
Program Lock features are programmed using the
same method, but with the setup aS,shown in Table
2. The only difference in programming Program Lock
features is that the Program Lock features cannot be
directly verified. Instead, verification of programming
is by observing that their features are enabled.

If the Program Lock. Bits have not been programmed, the on-chip Program Memory can be read
out for verification purposes, if desired, either during
or after the programming operation. The address of
the Program Memory location to be read is applied
to Port 1 and pins P2.0 - P2.4. The other pins should
be held at the "Verify" levels indicated in Table 3.
The contents of the addressed locations
come
out on Port O. External pullups are required on Port 0
for this operation.
.

will

If the Encryption Array in the EPROM has been programmed, the data present at Port 0 will be Code
Data. XNOR Encryption Data. The user must know
the Encryption Array contents to manually "unencrypt" the data during verify.
The.setup, which is shown in Figure 12, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an activelow read strobe.

10-98

intJ

87C51FA

1 ~I'------2S PULSES - - - - - . - J ' I

ALE/PROG:---:utJLllJt - - - - -

ULWu-

'--'

1 "-.

ALE/PROG:---":o~I

10}'! MIN1

I'

!~~'t:

'I

nL_____--In. .___

_ _ _ _ _ _...

270258-21

Figure 11. PROG Waveforms

Vee
AD-A7

PO

PI

EA/Vpp

RST
P3.6

ALE/PROG
87CSIFA

P3.7

PSEN ....- - 0
P2.7 1 + - - 0

(ENABLE)

P2.6 1+---0

XTAL2

'--'-"'-:1---1

I-_LJ\. PGM
t - - - - . / DATA

P2.0 1/L--A8-_A 12
-P2.4 \.~-:.;;;....

XTAL 1

Vss
270258-22

Figure 12. Verifying the EPROM

10-99

87C51FA

EPROM Program Lock

Reading the Signature Bytes

The two-level Program Lock system consists of two
Program Lock bits and a 32 byte Encryption Array
which are used to protect the .program memory
.
against software piracy.

The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031 H,
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
(030H) = 89H indicates manufacture by Intel
(031H) = 50H indicates 87C51FA

Encryption Array
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1's). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR'ed
(XNOR) with the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1's), will return the code in it's
original, unmodified form.

Program Lock Bits
Also included in the EPROM Program Lock scheme
are two Program Lock Bits which are programmed
as shown in Table 2.
Table 3 outlines the features of programming the
Lock Bits.
Erasing the EPROM also erases the Encryption Array and the Program Lock Bits, returning the part to
full functionality.

Erasure Characteristics
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it i~ suggested that an opaque label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat"
ed dose of at least 15 W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 p..W/cm rating for 30 minutes, at
distance of about 1 inch,
should be sufficient.

a

Erasure leaves the all EPROM Cells in a 1's state.

Table 3 Program Lock Bits and their Features
Program Lock Bits
LB1
LB2

Logic Enabled

U

U

No Program Lock features enabled. (Code Verify will still be
encrypted by the Encryption Array.)

P

U

MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
EA is sampled and latched on reset, and further programming
of the EPROM is disabled.

P

P

Same as above, but Verify is also disabled

U

P

Reserved for Future Definition

10-100

inter

87C51FA

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
= 21°C to 2rc; Vee = 5V±0.25V; vss = OV)

(TA

ADVANCED INFORMATION-CONTACT INTEL FOR DESIGN-IN INFORMATION
Units

Symbol

Parameter

Min

Max

Vpp

Programming Supply Voltage

12.5

13.0

V

Ipp

Programming Supply Current

50

mA

6

MHz

1/TCLCL

Oscillator Frequency

4

TAVGL

Address Setup to PROG Low

TGHAX

Address Hold after PROG

48TCLCL

TDVGL

Data Setup to PROG Low

48TCLCL

TGHDX

Data Hold after PROG

48TCLCL

TEHSH

P2.7 (ENABLE) High to Vpp

48TCLCL

TSHGL

Vpp Setup to PROG Low

10

/Ls

TGHSL

Vpp Hold after PROG

10

/Ls

TGLGH

PROG Width

90

TAVOV

Address to Data Valid

48TCLCL

TELOV

ENABLE Low to Data Valid

48TCLCL

TEHOZ

Data Float after ENABLE

0

TGHGL

PROG High to PROG Low

10

48TCLCL

110

/Ls

48TCLCL
/Ls

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING

VERIFICATION

ADDRESS

ADDRESS

Pl.0-Pl.?
P2.0-P2.4

-TAVQV
DATA OUT

PORT 0
TGHDX
TAVGL
ALE/PROG
TSHGLr--TGLGH

EIi/vpp

1
~.-:.-,,","

Vpp

EA/HIGH
TELQVl

P2.?

}

TEHQZ

270258-18

10-101.

83C152A
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER WITH FACTORY

MASK PROGRAMMABLE ROM

80C152A
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER
Data Memory Addressing
• 64KB
256 Bytes On-Chip RAM
• Dual On-Chip DMA Channels
• Hold/Hold Acknowledge
• Two General Purpose Timer/Counters
• 56 Special Function Registers
• 11 Interrupt Sources
• Available in 48 Pin Dual-in-Line Package
• and
68 Pin Surface Mount PLCC

of 80C51BH Architecture
• Superset
Multi-Protocol Serial Communication
• 1/0 Port (1.5 Mbps/2.4 Mbps Max)

•
•
•
•
•

-SDLC
-HDLC
-CSMA/CD
- User Definable Protocols
Full Duplex/Half Duplex
MCS®-51 Compatible UART
12 MHz Maximum Clock Frequency
Multiple Power Conservation Modes
64KB Program Memory Addressing

Package
(See Packaging Spec. Order # 231369)

The 80C152, which is based on the MCS®-51 CPU, is a highly integrated single-chip 8-bit microcontroller
designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated
Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applications. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller
features for peripheral 1/0 interface and control.
Silicon implementations are much more cost effective than multiwire cables found in board level parallel-to-serial and serial-to-parallel converters. The 83C152 contains, in silicon, all the features needed for the serial-toparallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or
fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modularity of hardware and software designs. All of these-cost, network parameter and real estate improvements
apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.
(GRXO)

no

I

(GTDX) Pl.!

2

(DEN) P1.2
(i'Xc) PI.3

:3

(m) PI.4

5

04

P4.6

PO

(RIB) P1.5
(HLDA) PloG

RESET

13

P3.D

14

P3.3

18

Pl.4

19

(TXD) P3.1

(imo)
(iNTi)

P3.2
P3.3

13

N.C.

80C152A

83C152A

N.C.

P2.7
P3.S

P2.6

P3.6

P2.S

P3.7

270188-3
270188-2

Figure 1. Connection Diagrams

10-102

September 1987
Order Number: 270188-003

P4.0-P4.7

P2.0-P2.7

-----"

r

I
I
I
I
I
I

~
c

...CD

~

o m
~·o
oc.J :III"
n

(

SARL1
SARHl
DARLl
DARHl
BCRL1

CD

0

....

0
en
N
l>

C

iii·

...

(Q

DI

TLO

IPNl

THO

IENl

TL1

IP

THl

IE

.....
CD

SBUf(RX)

Co)

~~~f~Tit~

....0en

SCON

N

l>

3

~
'lEJ

aID
Iiiiil
IF'

ADRO-3
BAUD

P1.0- P1.7

_-.J
P3.0- P3.7

270188-1

~
~
~

aID
~

inter

80C152A/83C152A

Pin #
PLCC(1)
DIP
48
2
3,33(2)
24
18-21, 27-30,
25-28
34-37

1-8

4-11

29-36

41-48

10-17

14-16,
18,19,
23-25

Pin Description
Vcc-Supply voltage.
Vss-Circuit ground.
Port O-Port 0 is an 8-bit open drain bidirectional 110 port. As an output port each pin
can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external memory. In this application it uses strong internal pullups when emitting 1s.
Port 0 also outputs the code bytes during program verification. External pull ups are
.
required during program verification.
Port 1-Port 1 is an 8-bit bidirectional 1/0 port with internal pullups. Port 1 pins that
have 1s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pullups.
Port 1 also serves the functions of various special features of the 8XC152, as listed
below:
Pin
Name
Alternate Function
P1.0
GRXD
GSC data input pin
P1.1
GTXD
GSC data output pin
P1.2
DEN
GSC enable signal for an external driver
P1.3
TXC
GSC input pin for external transmit clock
P1.4
RXC
GSC input pin for external receive clock
P1.5
HLD
DMA hold input/output
P1.6
HLDA
DMA hold acknowledge input/output
Port 2-Port 2 is an 8~bit bidirectional 1/0 port with internal pullups. Port 2 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 2 pins that are externally being pulled IQw will source
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program
Memory and during accesses to external Data Memory that use 16-bit addresses
(MOVX @ DPTR and DMAoperations). In this application it uses strong internal pullups
when emitting 1s.
During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program verification.
Port 3-Port 3 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 3 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special features of the MCS-51 Family, as
listed below:
Pin
Name
Alternate Function
P3.0.
Serial input line
RXD
P3;1
TXD
Serial output line
P3.2
INTO
External Interrupt 0
P3.3
INT1
External Interrupt 1
P3.4
Timer 0 external input
TO
P3.5
T1
Timer 1 external input
P3.6
WR
External Data Memory Write strobe
P3.7
RD
External Data Memory Read strobe

NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.

10-104

intJ

80C152A/83C152A

Pin Description (Continued)
Pin #

Pin Description

47-40

65-58

Port 4-Port 4 is an 8-bit bidirectional 1/0 port with internal pullups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (IlL, on the data sheet) because of the internal pullups. In addition,
Port 4 also receives the low-order address bytes during program verification.

9

13

RST-Reset input. A logic low on this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a power-on
reset to be generated using only an external capacitor to Vss. Although the GSC
recognizes the reset after three machine cycles, data may continue to be
transmitted for up to 4 machine cycles after Reset is first applied.

38

55

ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory.
.
In normal operation ALE is emitted at a constant rate of % the oscillator
frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data
Memory. While in Reset, ALE remains at a constant high level.

37

54

PSEN-Program Store Enable is the Read strobe to External Program Memory.
When the 8XC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.

39

56

EA-External Access enable. EA must be externally pulled low in order to enable
the 8XC152 to fetch code from External Program Memory locations OOOOH to
OFFFH.
EA must be connected to Vee for internal program execution.

23

32

XTAL 1-lnput to the inverting oscillator amplifier and input to the internal clock
generating circuits.

22

31

XTAL2-0utput from the inverting oscillator amplifier.

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.
.

XTAL2
XTAL 1

t - - - - - - I Vss

,270188-4
Figure 3. Using the On-Chip Oscillator

NC
EXTERNAL
OSCILLATOR
SIGNAL

XTAL2
XTAL 1

Vss

270188-5

Figure 4. External Clock Drive

10-105

.

infef

80C152A/83C152A

IDLE MODE

POWER DOWN MODE

In Idle Mode, the CPU puts itself to sleep while most
of the on-chip peripherals remain active. The major
peripherals that do not remain active during Idle, are
the DMA channels. The Idle Mode is invoked by
software. The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode. The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset.

In Power Down Mode, the oscillator is stopped and
. all on-chip functions cease except that the on-chip
RAM contents are maintained. The mode Power
Down is invoked by software.. The Power Down
Mode can be terminated only by a hardware reset.

Table 1. Status of the external pins during Idle and Power Down modes
Mode

Program
Memory

,
. ALE

PSEN

PortO

Port 1

Port 2

Port 3

Port 4

Idle

Internal

1

1

Data

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Data

Power Down

Internal

0

0

Data

Data

Data

Data

Data

Power Down

External

0

0

Float'

Data

Data

Data

Data

NOTE:
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application
Note AP-252, "DeSigning with the 80C51BH."

10-106

intJ

80C152A183C152A

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O·C to + 70·C
Storage Temperature .......... - 6S·C to + 1S0·C
Voltage on Any pin to Vss .. - O.SV to (Vee + O.SV)
Voltage on Vee to VSS ........... -O.SVto +6.SV
Power Dissipation ....................... 1.0 W(7)

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE: Specifications contained within the
following tables are subject to change.

D.C. CHARACTERISTICS
Symbol

(TA = O·C to + 70·C; Vee = SV ± 10%; Vss = OV)

Parameter

Typ
(Note 1)

Max

Unit

-O.S

0. 2Vee- 0.1

V

-O.S

0.2Vee- 0.3

V

0.2Vee+ 0.9

Vee+ O.S

V

0.7Vee

Vee+ O.S

V

Min

Test Conditions

V,L

Input Low Voltage
(All Except EA)

V,L1

Input Low Voltage
(EA)

V,H

Input High Voltage
(Except XTAL 1, RST)

V,H1

Input High Voltage
(XTAL 1, RST)

VOL

Output Low Voltage
(Ports 1, 2, 3, 4)

0.45

V

IOL = 1.6 mA
(Note 2)

VOL1

Output Low Voltage
(Port 0, ALE, PSEN)

0.45

V

IOL =3.2mA
(Note 2)

VOH

Output High Voltage
(Ports 1, 2, 3, 4,
ALE, PSEN)

V

IOH = -60p..A
Vee = SV ±10%

V

IOH = -10 p..A

V

IOH = -400 p..A
Vee = SV ±10%

-

2.4
0.9Vee •

VOH1

Output High Voltage
(Port 0 in External
Bus Mode)

2.4

V

IOH = -40 p..A (Note 3)

I,L

Logical 0 Input
Current (Ports 1, 2, 3, 4)

-so

p.A

V,N = O.4SV

ITL

Logical 1 to 0
Transition Current
(Ports 1, 2, 3, 4)

-6S0

p.A

V,N = 2V

III

Input Leakage
(PortO, EA)

±10

p.A

O.4S.100 pF), the noise pulse on the ALE pin may
exceed o.av. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
S. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vcc specification when the address bits are stabilizing.
4. Icc is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, ~ = VSS + 0.5V, VIH =
~ - 0.5V; XTAL2 N.C.; Port 0 pins connected tei Vc~'Operating" current is measured with EA connected to Vee and
RST connected to Vss. "Idle" current is measured with EA connected to Vss, RST connected to Vcc and GSC inactive.
5. The specifications relating to external data memory characteristics are also applicable to DMA operations.
6. TOVWX should not be confused with TOVWX as specified for aOC51BH. On aOC152, TOVWX is measured from data
valid to rising edge of WR. On aOC51BH, TOVWX is measured from data valid to falling edge of WR. See timing diagrams.
7. This value is based on the maximum allowable die temperature and the thermal resistance of the package.

.

.

MAX Icc (ACTIVE) =(2.24 X FREQ) + 4.16 (Note 4)
MAX Icc (IDLE) = (0.8 X FREQ) + 2.2 (Note 4)
where FREQ is the external oscillator Frequency in Megahertz and Icc is in Milliamps
45
40

35
30

'<

.§.
~

25
20
15
10
5
0

./

'"

/"

/ " ......
./'

~4

MAX Icc
(ACTIVE) (NOTE 4)

~

--

TYPICAL Icc
(ACTIVE) (NOTE 1)
MAX Icc
(IDLE) (NOTE 4)
TYPICAL Icc
IDLE (NOTE 1)

12

8

FREQUENCY (MHz)

270188-17

Figure 5. icc vs Frequency

EXPLANATION OF THE AC SYMBOLS

I: Instruction (program memory contents).
L: Logic level LOW, or ALE.
P: PSEN.
Q: Output data.
R: READ signal.
T: Time.
V: Valid.
W: WRITE signal.
X: No longer a valid logic level.
Z: Float.

Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
, the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A:
C:
0:
H:

Address;
Clock
Input data.
Logic level HIGH.

For example,
TAVLL = Time for Address Valid to ALE Low..
TLLPL = Time for ALE Low to PSEN Low.

10-108

intJ

80C152A183C152A

A.C. CHARACTERISTICS (TA = O·C to + 70·C; Vee = 5V ± 10%; Vss = OV; Load Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol

12MHz

Parameter

Min

Max

(Note 5)

Variable Oscillator
Min

Max

3.5

12

Unit
MHz

1/TCLCL

Oscillator Frequency

TLHLL

ALE Pulse Width

126

2TCLCL-40

ns

TAVLL

Address Valid to ALE Low

28

TCLCL-55

ns

TLLAX

Address Hold After ALE Low

48

TLLlV

ALE Low to Valid
Instruction In

TLLPL

ALE Low to PSEN Low

43

TCLCL-40

ns

TPLPH

PSEN Pulse Width

205

3TCLCL-45

ns

TPLIV

PSEN Low to Valid
Instruction In

TPXIX

Input Instruction
Hold After PSEN

TPXIZ

Input Instruction
Float After PSEN

58

TCLCL-25

ns

TAVIV

Address to Valid
Instruction In

311

5TCLCL-105

ns

TPLAZ

PSEN Low to Address
Float

10

10

ns

TCLCL-35
233

145
0

ns
4TCLCL-100

3TCLCL-105

AD Pulse Width

400

6TCLCL-100

TWLWH

WA Pulse Width

400

6TCLCL-100

TALDV

AD Low to Valid
Data In

TAHDX

Data Hold After AD

TAHDZ

Data Float After AD

251
0

ns
ns

0

TALAH

ns

ns
ns
5TCLCL-165

ns
ns

0
96

2TCLCL-70

ns

TLLDV

ALE Low to Valid
'Data In

516

8TCLCL-150

ns

TAVDV

Address to Valid
Data In

585

9TCLCL-165

ns

TLLWL

ALE Low to AD or
WALow

200

3TCLCL+50

ns

TAVWL

Address to RD or
WALow

203

4TCLCL-130

ns

TOVWX
(Note 6)

Data Valid to WA
Transition

333

6TCLCL-167

ns

TWHOX

Data Hold After WA

33

TALAZ

AD Low to Address
Float

TWHLH

RD or WR High to
ALE High

300

3TCLCL-50

TCLCL-50
0

43

10-109

123

TCLCL-40

ns
0

ns

TCLCL+40

ns

inter

80C152A/83C152A

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE

_ _J

rssEN

_ _J

PORT 0 _ _..I

PORT 2

___

,~

______

~~~

_______

n~

______
AB-A'15 _____
~

270188-6

EXTERNAL DATA MEMORY READ CYCLE

ALE

PSEN

,

I-----TLLDV------l.,

- - i - - - TRLRH - - - I

PORTO'

PORT2

INSTR. IN

P2.0-P2.7 OR AB-A15 FROt.! DPH

A8-A 15 FROt.! PCH
270188-7

10-110

80C152A/83C152A

EXTERNAL DATA MEMORY WRITE CYCLE

,

ALE

I

\.

P

TWHlH

\.

PSEN

I+-- TlLWL

~

WR

,I

TOVWX

--

PORTO

~

TWlWH

::::r

- r-

TAVll ~TLLAX~
AO-A7 FROM R. OR DPL )

TWHOX

X XAO-A7 FROM PCl

DATA OUT

INSTR. IN

TAVWl
'PORT 2

-

~

P2.0-P2.7 OR A8-A15 FROM DPH

A8-A15 FROM PCH

X

270188-8

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max·

Units

1/TClCl

Oscillator Frequency

3.5

12

MHz

TCHCX

High Time

20

ns

TClCX

low Time

20

ns

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

EXTERNAL CLOCK DRIVE WAVEFORM

270188-9

10-111

inter

80C152A183C152A

LOCAL SERIAL CHANNEL TIMING":"SHIFT REGISTER MODE
Symbol

12MHz

Parameter

Min.

Variable Oscillator

Max

Units

Max

Min

TXLXL

Serial Port Clock Cycle
Time

1000

12TCLCL

ns

TQVXH

Output Data Setup to
Clock Rising Edge

700

10TCLCL-133

ns

TXHQX

Output Data Hold After
Clock Rising Edge

50

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

700

10TCLCL-133

ns

SHIFT REGISTER MODE TIMING WAVEFORMS

ALE

CLOCK

'--_~ '----r' '--_--'X'-__.JX

OUTPUT DATA

4

X

t

x...._--IX....

1

--.;..-J

t

SET TI

WRITE TO SBur
INPUT DATA

5

_____

--'~J~--'

t

t

CLEAR RI

SET RI

270188-10

A.C. TESTING:
INPUT, OUTPUT WAVEFORMS

VCC-o.S =X0.2VCC+O.9
0.4SV

FLOAT WAVEFORM

)C,

0.2Vcc-O.l

~.....;;;;:..------

270188-11

270188-12
For Timing Purposes a Port Pin is no Longer Floating when a 100
mV change from Load Voltage Occurs, and Begins to Float when·
a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH ~ ± 20 rnA

AC Inputs During Testing are Driven at Vee-O.S for a Logic "1"
and O.4SV for a Logic "0". Timing Measurements are made at VIH
Min for a Logic "1" and Vil Max'for a Logic '~O".

10-112

inter

80C152A/83C152A

GLOBAL SERIAL PORT TIMINGS-Internal Baud Rate Generator
,
Symbol

12 MHz (BAUD = 0)

Parameter

Min

Variable Oscillator

Max

Min

Unit

Max

HBTJR

Allowable jitter on
the Receiver for %
bit time (Manchester
encoding only)

0.058

(0.125 x
(BAUD+1)X
8TCLCL)
-25 ns

fJ.s

FBTJR

Allowable jitter on
the Receiver for one
full bit time (NRZI
and Manchester)

0.142

(0.25 x
(BAUD+1)X
8TCLCL)
-25 ns

fJ.s

HBTJT

Jitter of data from
Transmitterfor %
bit time (Manchester
encoding only)

±35

±35

ns

FBTJT

Jitter of c;lata from
Transmitter for one
full bit time (NRZI
and Manchester)

±70

±70

ns

DRTR

Data rise time for
Receiver (Note 8)

20

20

ns

DFTR

Data fall time for
Receiver (Note 9)

20

20

ns

NOTES:
8. Same as TCLCH, use External Clock Drive Waveform.
9. Same as TCHCL, use External Clock Drive Waveform.

GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR)

BT

II
I

MANCHESTER

:::::x:
I
I

NRZ1:::::X:

~i~
:-~
I

I

HBTJR

I
I

'I
I

~~-+
X ~

I

I

~,
I

~

t,1

,~

I

FBTJR

I

C::::

GRXD

I
I

GRxD

I

FBTJR
270188-13

10-113

intJ

80C152A/83C152A

GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR)
t+'----

I'

MANCHESTER.

*
BT

----~·I

I

I

1......1.....

I

x::::
4$::,==.~~:==.$r'______. . . x::::

::::l---.. .$~,. . ~'lo...----i--"""jolo"--.J.I~1
$
$ *$

GTxD

I

I _ _ _ _~HB~T~JT~~~__....I~-~-~FB~T~JT----....I
NRZI=::J!(_ _ _ _ _ _ _

GTxD

FBTJT
270188-14

GLOBAL SERIAL PORT TIMINGS-External Clock
Symbol

12MHz

Parameter'

Variable OSCillator

Min

Max

Min

Max

0.009

2.4

0.009

1/5TClCl

Unit

1/ECBT

GSC Frequency with an
External Clock

ECH

External Clock High

197

2TClCl
+ 30ns

ns

ECl

External Clock low

197

2TClCL
+ 30ns

ns

ECRT

External Clock Rise
Time (Note 8)

20

20

ns

ECFT

External Clock Fall
Time (Note 9)

20

20

ns

ECDVT

External Clock to Data
Valid Out - Transmit
(to External Clock
Negative Edge)

150

150

ECDHT

External Clock Data
Hold - Transmit
, (to External Clock
Negative Edge)

MHz

ns

,
ns
0

0

ECDSR

External Clock Data
Set-up - Receiver
(to External Clock
Positive Edge)

45

45

ns

ECDHR

External Clock to Data
Hold - Receiver
(to External Clock
Positive Edge)

50

50

ns

10-114

inter

SOC152A1S3C152A

GSC TIMINGS (EXTERNAL CLOCK)
t+·----ECBT----~·1

-----x

1

EXTERNAL CLOCK

1

'X

f.

I

t---ECL-----::--- ECH ----.: 1
_ _...;...1
~ : - ECDVT
TRANSMIT DATA
:

:x:r--.;;..;..;.------.;....,;.-.-

X

ECDHT ~
141· - - - - E C B T
1
EXTERNAL CLOCK -----X""I_ _ _ _
1

'I

1

Ji:,-----X

--' ECDSR '-ECDHR--'

_ _"""1"'_ _ '

RECEIVE DATA

X

_ _....._....J,

:+
1

I~---"""''----

'--_ _ _..J

,

Xr...,..---------.....;i--, _ " -_ _ _ _ _ _ _ _ _......_ _
270188-15

10-115

80C152A/83C152A

NOTES ON THE OPERATION OF THE
80C152A
1. Current in Power Down Mode
Typically, Icc in Power Down Mode is about
·10 ""A. However, you may note under certain conditions an abnormally high Icc, about 600 ""A, in
Power Down. This is caused by an interaction between internal signals local to the interrupt control
system. The problem disappears once an interrupt, any interrupt, is requested and serviced.
Therefore, if Icc in Power Down is critical to the
application, it is suggested that an interrupt be
generated and exercised before Power Down is
invoked.

2. SDLe Flags While Idling
In SDLC Mode, the GSC can be programmed to
transmit SDLC flags between transmission
frames. This is done by setting the GFIEN bit in
PCON. When the GSC is so programmed, the
DEN signal is asserted only during the actual
transmission frame, not during the idle fill flags. In
this case the DEN signal will normally not be used
to enable the line driver, but is available for use as
a positive indication that a transmission frame is
in progress.
3. Immediate Deactivation of DEN in CSMAlCD
Mode
CSMAlCD protocols typically require two bittimes .of inactivity in the line to indicate an idle
condition. Note, however, that the 80C152A deac. tivates DEN immediately at the end of the transmission frame.

10-116

83C 152JA/83C 152JA-1
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER WITH FACTORY MASKED
PROGRAMMABLE ROM
80C152JA/80C152JA-1
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER
80C152JB/80C152JB-1
UNIVERSAL COMMUNICATION CONTROLLER
8-BIT MICROCOMPUTER WITH EXTENDED 1/0
•

Superset of 80C51 Architecture

•

64KB Data Memory Addressing

•

Multi-Protocol Serial Communication
I/O Port (2.048 Mbps/2.4 Mbps Max)
-SDLC
-HDLC
-CSMAlCD
- User Definable Protocols

•

256 Bytes On-Chip RAM

•

Dual On-Chip DMA Channels

•

Hold/Hold Acknowledge

•

Two General Purpose Timer/Counters

•

56 Special Function Registers

•

Full Duplex/Half Duplex

•

MCS®-51 Compatible UART

•

16.5 MHz Maximum Clock Frequency

•

Multiple Power Conservation Modes

•

64KB Program Memory Addressing

•

11 Interrupt Sources

•

Available in 48 Pin Dual-in-Line Package
and 68 Pin Surface Mount PLCC
Package
(See Packaging Spec. Order #231369)

The 80C152, which is based on the MCS®-51 CPU, is a highly integrated single·chip 8·bit microcontroller
designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated
Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applications. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller
features for peripheral 1/0 interface and control.
Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-toserial and serial-to-parallel ~onverters. The 83C152 contains, in silicon, all the features needed for the serialto-parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or
fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modularity of hardware and software designs. All of these-cost, network parameter and real estate improvementsapply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.

10-117

September 1987
Order Number: 270431-001

inter

~[Q)W~OO©[§ OOOIP@OOINl~"iiO@OO

80C152JAl83C152JA/80C152JB

(GRXO)

vee

(GTOX)

P4.0

(DEN)

P4.1

(TXC)
(RxC) P1.4

P4.3

INDEX
CORNER'\,.

: i. :. i
N

.,

P"',5
P4.6

N.C.

P4.7

(HLO) P1.S

P4.4

P4.5

Pl.7

P4.6

P3.1

P4.7

P3.2

N.C.

EA

P3.0

EA

(TXO) P3.1

~

Pl.7

(HLOA) P1.6
RESET

q 

~

.,.

P2.4
P2.3

i;; :ll III ~ :;; ~ ~

....

"~ ~ d ~ ~

"! C!
~ .~

~

Figure 1. Connection Diagrams

10·118

OJ

~

270431-3

·P6.0-P6.7

P4.0-P4.7

PO.O-PO.7

P2.0-P2.7

-----11

t

SARL1
SARHI
OARL1
OARHI
CI)

BCRL1

o

....CJI

(")

~

l>
......
CI)

."

Co)

iD:
c

...CD

1.£1

!'l
UJ
'?
..... 0'
n

CO

;I;'

C

iii"
ce

...
DI

3

....CJI

(")
N
Co.

em
,

·EBEN

l>

~

~

......
CI)
o

I"~

THO

....(")CJI

TLI

~

THI

a:J

~

~
l§!

~

;:;g

©

IiiiiI

~

'liil

©

ADRD-3
BAUD

Pl.0- P1.7

'On 80C152JB Only

_-.J
P3.0-P3.7

270431-4

2&
~
~
~

<=

©

~

intJ

80C152JAl83C152JA/80C152JB

80C152JB General Description
The 80C152JB is a ROM less extension of the
aOC152 Universal Communication controller. The
80C152JB has the same five 8-bit I/O ports of the
80C152, plus an additional two 8-bit 1/0 ports, Port 5
, and Port 6. The 80C152JB also has two additional
control pins, EBEN (EPROM Bus ENable), and
EPSEN (EPROM bus Program Store ENable).
EBEN selects the functionality of Port 5 and Port 6.
When EBEN is low, these ports are strictly I/O, similar to Port 4. The SFR location for Port 5 is 91 Hand
Port 6 is OA 1H. This means Port 5 and Port 6 are not
bit addressable. With EBEN low, all program memorY fetches take place via Port 0 and Port 2. (The
80C152 is a ROMless only product). When EBEN is
high, Port 5 and Port 6 form an address/data bus
called the E-Bus (EPROM-Bus) for program memory
'
operations.

~@w~oo©~ DOOIP©OOIMl~'jj'D©OO

EPSEN is used in conjunction with Port 5 and Port 6
program memory operations. EPSEN functions like
PSEN during program memory operation, but supports Port 5 and Port 6. EPSEN is the read strobe to
externai program memory for Port 5 and Port 6.
EPSEN is activated twice during each machine cycle
unless an external data memory operation occurs on
Port(s) 0 and Port 2. When external data memory is
accessed the second activation of EPSEN is
skipped, which is the same as when using PSEN.
Note that data memory fetches cannot be' made
through Ports 5 and 6.
When EBEN is high and EA is low, all program memory operations take place via Ports 5 and 6. The high
byte of the address goes out on Port 6, and the low
byte is output on Port 5. ALE is still used to latch the
address on Port 5. Next, the op code is read on Port
5. The timing is the same as when using Ports 0 and
2 for external program memory operations.

Table 1. Program Memory Fetches
EBEN

EA

Program
Fetch via

0

0

PO,P2

PSEN

EPSEN

Comments

Active

Inactive

Addresses O-OFFFFH

0

1

N/A

N/A

N/A

1

0

P5,P6

Inactive

Active

Addresses O-OFFFFH

1

1

P5,P6
PO,P2

Inactive
Active

Active
Inactive

Addresses 0-1 FFFH
Addresses :?: 2000H

10-120

Invalid Combination

inter

SOC 152JAlS3C 152JAlSOC152JB

Pin #
PLCC(1)

DIP
48

~@W~OO©[§ OOO[F@OOIM]~'iiO@OO

Pin Description

2
3,33(2)

Vee-Supply voltage.

24
18-21,
25-28

27-30,
34-37

Port O-:-Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin
can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled low. During accesses to external Data
Memory, Port 0 always emits the low-order address byte and serves as the multiplexed
data bus. In these applications it uses strong internal pullups when emitting 1s.
Port 0 also outputs the code bytes during program verification. External pullups are
required during program verification~

1-8

4-11

Port 1-Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can be
used as inputs. As inputs, Port 1 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the internal pull ups.
Port 1 also serves the functions of various special features of the 8XC152, as listed
below:

Vss-Circuit ground.

Pin
P1.0
P1.1
P1.2
P1.3
P1,4
P1.5
P1.6

Name

Alternate Function
GSC data input pin
GSC data output pin
GSC enable signal for an external driver
GSC input pin for external transmit clock
GSC input pin for external receive clock
DMA hold input/ output
DMA hold acknowledge input/output

GRXD
GTXD
DEN
TXC
RXC
HLD
HLDA

29-36

41-48

Port 2-Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that
have 1 s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 2. pins that are externally being pulled low will source.
current (IlL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled low. During accesses to external Data Memory that use 16bit addresses (MOVX @ DPTR and DMA operations), Port 2 emits the high-order
address byte. In these applications it uses strong internal pullups when emitting 1s.
During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri),
Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits during program verification.

10-17

14-16,
18,19,
23-25

Port 3-Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that
have 1s written to them are pulled high by the internal pull ups, and in that state can be
used as inputs. As inputs, Port 3 pins that are externally being pulled low will source
current (IlL, on the data sheet) because of the pullups.
Port 3 also serves the functions of various special features of the MCS-51 Family, as
listed below:
Pin

..

P3.0
P3.1
P3.2
P3.3
P3,4
P3.5
P3.6
P3.7

Name

Alternate Function
Serial input line
Serial output line
External Interrupt 0
External Interrupt 1
Timer 0 external input
Timer 1 external input
External Data Memory Write strobe
External Data Memory Read strobe

RXD
TXD
INTO
INT1
TO
T1
WR
RD

NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be used in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLCC devices.

10-121

.

inter

80C152JAl83C152JA/80C 152JB

~1ID\Yl~OO©[§ OOO!F©OO!MI~ii"O©OO

Pin Description (Continued)
Pin #

Pin Description

47-40

65-58

Port 4-Port 4 is an 8-bit bidirectional 1/0 port with internal pull ups. Port 4 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 4 pins that are externally being pulled low will
source current (Ill, on the data sheet) because of the internal pullups. In addition,
Port 4 also receives the low-order address bytes during program verification.

9

13

RST-Reset input. A logic low on this pin for three machine cycles while the
oscillator is running resets the device. An internal pullup resistor permits a power-on
reset to be generated using only an external capacitor to Vss. Although the GSC
recognizes the reset after three machine cycles, data may continue to be
transmitted for up to 4 machine cycles after Reset is first applied.

38

55

ALE-Address Latch Enable output signal for latching the low byte of the address
during accesses to external memory.
In normal operation ALE is emitted at a constant rate of % the oscillator
frequency, and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external Data
Memory. While in Reset, ALE remains at a constant high level.

37

54

PSEN-Program Store Enable is the Read strobe to External Program Memory.
When the 8XC152 is executing from external program memory, PSEN is active
(low). When the device is executing code from External Program Memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped
during each access to External Data Memory. While in Reset, PSEN remains at a
constant high level.

39

56

EA-External Access enable. EA must be externally pulled low in order to enable
the 8XC152 to fetch code from External Program Memory locations OOOOH to
OFFFH.
EA must be connected to Vee for internal program execution.

23

32

XTAL 1-lnput to the inverting oscillator amplifier and input to the internal clock
generating circuits.

22

31

XTAL2-0utput from the inverting oscillator amplifier.

N/A

17,20
21,22
38,39
40,49

Port 5-Port 5 is an 8-bit bidirectional 1/0 port with internal pullups. Port 5 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 5 pins that are externally being pulled low will
source current (Ill, on the data sheet) because of the internal pullups.
Port 5 is also the multiplexed low-order address and data bus during accesses to
external program memory if EBEN is pulled high. In this application it uses strong
pull ups when emitting 1s.

N/A

67,66
52,57
50,68
1,51

Port 6-Port 6 is an 8-bit bidirectional 1/0 port with internal pullups. Port 6 pins that
have 1s written to them are pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 6 pins that are externally pulled low will source
current (Ill, on the data sheet) because of the internal pullups.
Port 6 emits the high-order address byte during fetches from external Program
Memory if EBEN is pulled high. In this application it uses strong pull ups when
emitting 1s.

N/A

12

EBEN-E-Bus Enable input that designates whether program memory fetches take
place via Ports O.and 2 or Ports 5 and 6. Table 1 shows how the ports are used-in
conjunction with EBEN.

53

EPSEN-E-bus Pr9gram Store Enable is the Read strobe to external program
__
memory when EBEN is high. Table 2,shows when EPSEN is used relative to PSEN
depending on the status of EBEN and EA.

,

10-122

80C152JA/83C152JA/80C152JB

~(Q)W~OO©~ OOOIF@OOIMl~liO@OO

OSCILLATOR CHARACTERISTICS
XTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3.

NC -

XTAL2

EXTERNAL
OSCILLATOR - - - - I XTAL 1
SIGNAL

To drive the device from an external clock source,
XTAL 1 should be driven, while XTAL2 is left unconnected, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data
Sheet must be observed.

~L.v_s_s__
270431-6

Figure 4. External Clock Drive

IDLE MODE
In Idle Mode, the CPU puts itself to sleep while most
of the on-chip peripherals remain active. The major
peripherals that do not remain active during Idle, are
the DMA channels. The Idle Mode is invoked by
software. The content of the on-chip RAM and all
the Special Function Registers remain unchanged
during this mode. The Idle Mode can be terminated
by any enabled interrupt or by a hardware reset.

XTAL2
XTAL 1

+-------1 vss
270431-5

POWER DOWN MODE

Figure 3. Using the On-Chip Oscillator

In Power Down Mode, the oscillator is stopped and
all on-chip functions cease except that the on-chip
RAM contents are maintained. The mode Power
Down is invoked by software. The Power Down
Mode can be terminated only by a hardware reset.
Table 2. Status of the External Pins During Idle and Power Down Modes

80C152JAl83C152JA
Program
Memory

ALE

Idle

Internal

1

1

Data

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Data

Power Down

Internal

0

0

Data

Data

Data

Data

Data

Power Down

External

0

0

Float

Data

Data

Data

Data

Mode

PSEN

Porta

Port 1

Port 2

Port 3

Port 4

80C152JB
Mode

Instruction
ALE PSEN EPSEN Porta Port 1
Bus

Idle

PO,P2

1

1

1

Port 2

Port 3 Port 4 Port 5

Float

Data

Address

Data

Data

OFFH

Port 6
OFFH

Idle

P5,P6

1

1

1

Data

Data

Data

Data

Data

OFFH Address

Power Down

PO,P2

0

0

1

Float

Data

Data

Data

Data

OFFH

OFFH

Power Down

P5,P6

0

1

0

Data

Data

Data

Data

Data

OFFH

OFFH

NOTE:
For more detailed information on the reduced power modes refer to the Embedded Controller Handbook, and Application
Note AP-252, "Designing with the 80C51BH."

10-123

intJ

80C152JA/83C152JA/80C152JB

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... O·C to

+ 70·C

Storage Temperature .......... - 65·C to + 150·C
Voltage on Any pin to Vss .. -0.5\.1 to (Vee + 0.5V)
Voltage on Vee to VSS ........... -0.5V to + 6.5V
Power Dissipation ....................... 1.0W(9)

~@W~OO©[§ OOO!P@!ru!Ml~iiO@OO

*Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
.other conditions above those indicated in the operational sections of this specification is not implied. Exposure io absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE' Specifications contained within the
following tables are subject to change.

D.C. CHARACTERISTICS
Symbol

(TA

=

Parameter

O·Cto +70·C;Vee

=

5V ±10%;Vss

Typ
(Note 3)

Min

=

OV)

Max

Unit

Vil

Input Low Voltage
(All E~cept EA, EBEN)

-0.5

0.2Vec- 0.1

V

VIl1

Input LowVoltage
(EA, EBEN)

-0.5

0.2Vee- 0.3

V

VII-i

Input High Voltage·
(Except XTAL 1, RST)

0.2Vee+ 0.9

Vee+ 0.5

V

VIH1

Input High Voltage
(XTAL1, RST)

0.7Vee

Vee+ 0.5.

V

Test Conditions

,

VOL

Output Low Voltage
(Ports 1, 2, 3, 4, 5, 6)

0.45

V

IOl = 1.6 mA
(Note 4)

Vou

Output Low Voltage
(Port 0, ALE, PSEN, EPSEN)

0.45

V

IOl = 3.2mA
(Note 4)

VOH

Output High Voltage
(Ports 1, 2, 3, 4, 5, 6 COMM9
ALE, PSEN, EPSEN)

V

IOH = -60p..A
Vee = 5V ±to%

VOH1

Output High Voltage
(Port 0 in External
Bus Mode)

III

Logical 0 Input
Current (Ports 1, 2, 3, 4, 5, 6)

ITl

Logiqal 1 to 0
Transition Current
(Poits 1, 2, 3, 4, 5, 6)

III

Input Leakage
(portO, EA)

RRST

Reset Pullup Resistor

IIH

Logical 1 Input Current (EBEN)

Icc

Power Supply Current:
Active (i 6.5 MHz)
Idle (16.5 MHz)
Power Down Mode

2.4
0.9Vee

V

2.4

V

0.9Vee,

V
·-50

p..A

-650

p..A

= -10'p..A
= -400;UA
= 5V ±10% .
= - 40 p..A (Note 5)
VIN = O.4SV
IOH

IOH
Vee
IOH

VIN

=

2V

..
±10
40

p..A

0.45  100 pF), the noise pulse on the ALE pin may
exceed O.BV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
5. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9Vee specification when the address bits are stabilizing.
6. lee is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, V,L = Vss + 0.5V, V,H =
Vee - 0.5V; XTAL2 N.C.; Port 0 pins connected to Vee. "Operating" current is measured with EA connected to Vee and
RST connected to Vss. "Idle" current is measured with EA connected to Vss, RST connected to Vee and GSC inactive.
7. The specifications relating to external data memory characteristics are also applicable to DMA operations.
B. TQVWX should not be confused with TQVWX as specified for BOC51BH. On BOC152, TQVWX is measured from data
valid to rising edge of WR. On BOC51 BH, TQVWX is measured from data valid to falling edge of WR. See timing diagrams.
9. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
10. All specifications relating to external program memory characteristics are applicable to:
EPSEN for PSEN
Port 5 for Port 0
Port 6 for Port 2
when EBEN is at a Logical 1 on the BOC152JB.

MAX Icc (ACTIVE) = (2_24 X FREQ) + 4_16 (Note 6)
MAX Icc (IDLE) = (0_8 X FREQ) + 2.2 (Note 6)
45
MAX Icc (ACTIVE)

40
35

'/

30
~

5u
2

25

.... v

20

/'" V

15
10
5
0

/'"

/"

_/

- :::---

TYPICAL Icc
(ACTIVE) (NOTE 1)

/""

--

/'"

....-

...-:::

4

/'

8

12

MAX Icc (IDLE)
TYPICAL Icc
IDLE (NOTE 1)
16

FREQUENCY (MHz)

270431-7

Figure 5. Icc vs Frequency
I: Instruction (program memory contents).
L: Logic level LOW, or ALE.
P: PSEN.
Q: Output data.
R: READ signal.
T: Time.
V: Valid.
W: WRITE signal.
X: No longer a valid logic level.
Z: Float.

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.

A:
C:
D:
H:

Address.
Clock
Input data.
Logic level HIGH.

For example,
TAVLL
TLLPL

10-125

=
=

Time for Address Valid to ALE Low.
Time for ALE Low to PSEN Low.

SOC152JA/S3C 152JAlSOC152JB

~[Q)W~OO©[§ OOO~@OOIMl~iiO@OO

A.C. CHARACTERISTICS (TA = O·C to + 70·C; Vee = 5V ± 10%; Vss = OV; Lqad Capacitance for
Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
ADVANCE INFORMATION: SEE INTEL FOR DESIGN-IN INFORMATION
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
1/TCLCL

TLHLL
TAVLL
TLLAX

Unit

Oscillator Frequency
80C152JA
83C152JA
80C152JB

3.5

12

MHz

80C152JA-1
83C152JA·1
80C152JB-1
ALE Pulse Width

3.5

16.5

MHz

16.5 MHz

Parameter

Min

Address Valid to ALE Low

TLLPL

Address Hold After ALE Low
ALE Low to Valid
Instruction In
ALE Low to PSEN Low

TPLPH

PSEN Pulse Width

TPLIV

PSEN Low to Valid
Instruction In

TPXIX

Input Instruction
Hold After PSEN

TPXIZ

Input Instruction
Float After PSEN

TLLlV

(Note 7,10)

. Variable Oscillator
Min
Max

Max

81

2TCLCL-40

ns

5
25

TCLCL-55

ns
ns

TCLCL-35
142

4TCLCL-100

20'

TCLCL-40

137

3TCLCL-45

77
0

ns
ns
ns

3TCLCL-105

ns
ns

0
35

TCLCL-25

ns

,

TAVIV

Address to Valid
Instruction In

198

5TCLCL-105

ns

TPLAZ

PSEN Low to Address
Float

10

10

ns

TRLRH

RD Pulse Width
WR Pulse Width

TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV

RD Low to Valid
Data In
Data Hold After RD
Data Float After RD

263

6TCLCL-100

263

6TCLCL-100
138

0

ALE Low to Valid
Data In
Address to Valid
Data In

ns
- ns
5TCLCL-165

ns
ns

0
51

2TCLCL-70

ns

335

8TCLCL-150

ns

380

9TCLCL-165

ns

3TCLCL+50

ns

TLLWL

ALE Low to RD or
WRLow

132

TAVWL

Address to RD or
WRLow

112

4TCLCL-130

ns

TQVWX(8)

Data Valid to WR
Transition

196

6TCLCL-167

ns

TWHQX

Data Hold After WR
RD Low to Address
Float

10

RD or WR High to
ALE High

20

TRLAZ
TWHLH

232

3TCLCL-50

TCLCL-50

o '

10-126

100

TCLCL-40

ns
0

ns

TCLCL+40

ns

inter

80C152JAl83C152JAl80C152JB

~[Q)WbW~'J©[g O~IP@rnl[i'li]~iJO@~

EXTERNAL PROGRAM MEMORY READ CYCLE

ALE _ _oJ

PORT O/PORT 5

PORT 2/PORT 6

----'
AB-A15

----'

270431-8

EXTERNAL DATA MEMORY READ CYCLE

ALE

PSEN

I-----TLLDV-----I'I
TRLRH

---I

RD

INSTR. IN

PORTO

PORT2

P2.0-P2.7 OR A8-A 15 FROM DPH

A8-A 15 FROM PCH
270431-9

10-127

infef

80C152JA/83C152JA/80C1 ~2JB

~[Q)\Yl~OO©~. oOO!r@OO[MJ~'U'O@OO

EXTERNAL DATA MEMORY WRITE CYCLE

I

ALE

i=4-

\.
TWHLH

\.

PSEN
-TLLWL
WR

,

TWLWH

J

TQVWX

-.
PORTO

::::r

TAVLL

-.

I-- TLLAX---j

AO-A7 FROM R, OR DPL )

-'

1

r-

TWHQX

X X AO- A7 FROM PCL

DATA OUT

INSTR. IN

TAVWL
PORT2

=>

A8-A15 FROM PCH

P2.0-P2.7 OR A8-A15 FROM DPH

270431-10

'EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TClCL

Oscillator Frequency

3.5

16.5

MHz

TCHCX

High Time

20

ns

TClCX

low Time

20

ns

TClCH

Rise Time

20

ns

TCHCl

Fall Time

20

ns

EXTERNAL CLOCK DRIVE WAVEFORM

270431-11

10-128

inter

SOC 152JA/S3C152JA/SOC152JB

~[Q)W~OO©~ OOOIF@OOIMl~'ifO@OO

LOCAL SERIAL CHANNEL TIMING-SHIFT REGISTER MODE
Symbol

Variable OSCillator

16.5 MHz

Parameter

Min

Max

Min

Units

Max

TXLXL

Serial Port Clock Cycle
Time

727

12TCLCL

ns

TOVXH

Output Data Setup to
Clock Rising Edge

473

10TCLCL-133

ns

TXHOX

Output Data Hold After
Clock Rising Edge

4

2TCLCL-117

ns

TXHDX

Input Data Hold After
Clock Rising Edge

0

0

ns

TXHDV

Clock Rising Edge to
Input Data Valid

10TCLCL-133

473

ns

SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION

I

7

ALE

CLOCK

r- TQVXH~ r-

TXHQX

'''---'''''---r' '-----rJ "---""'--..JX'-_---JX

OUTPUT OATA

4

X'-_---JX"---_-'x"---""'--..JI

t

t

WRITE TO SSUF

SET TI

INPUT OATA _ _ _ _ _...J'\;;;;;J',_,,'I;.;.;.:;;;"-.....J'=~'--..J'.;;.;:;;,\,_I'I;..=''_.....J'I;...;;J'I_J,;.;.;;;;;;(,,_,'I;...;;;;J''

t

t

CLEAR RI

SET RI

270431-12

A.C. TESTING:
INPUT, OUTPUT WAVEFORMS

vce-O.s===>(
0,45 V

0.2Vcc+0.9

FLOAT WAVEFORM

L

_;..0_.2_V.,;;CC;,.-_0_.1_ _ __
270431-13

270431-14
For Timing Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs, and Begins to Float
when a 100 mV change from the Loaded VOHIVOL Level occurs
IOLIiOH ;, ± 20 rnA.

AC Inputs During Testing are Driven at Vcc-O,5 for a Logic "1"
and 0.45V for a Logic "0", Timing Measurements are made at VIH
Min for a LogiC "1" and VIL Max for a Logic "0",

10-129

intJ

80C152JA/83C152JA/80C152JB

~[Q)W~OO©~ OOOIF@OOIMl~ii"O@OO

GLOBAL SERIAL PORT TIMINGS-Internal Baud Rate ,Generator
Symbol

16.5 MHz (BAUD

Parameter

Min

=

0)

Variable Oscillator
IIIlIn

Max

Unit

Max

HBTJR

Allowable jitter on
the Receiver for %
bit time (Manchester
encoding only)

0.0375

,(0.125 x
(BAUD+1)X
8TCLCL)
--:25,ns

,.,.s

FBTJR

Allowable jitter on
the Receiver for one
full bit time (NRZI
and Manchester)

0.10

(0.25 x
(BAUD+1)X
8TCLCL)
-25 ns

,.,.s

HBTJT

Jitter of data from
Transmitter for %
bit time (Manchester
encoding only)

±35

±35

ns

FBTJT

Jitter of data from
Transmitter for one
full bit time (NRZI
and Manchester)

±70

±.70

ns

DRTR

Data rise time for
Receiver(11 )

20

20

ns

DFTR

Data fall time for
Receiver!1'2)

20

20

ns

~OTES:

'11. Same as TCLCH, use External Clock Drive Waveform.
12. Same as TCHCL, use External Clock Drive Waveform.

GSC RECEIVER TIMINGS (INTERNAL BAUD RATE GENERATOR)
II

BT

'I

1

MANCHESTER

=::J(
1
1

NRzr=:::X

1

~I~;'-------'I
X.' ~

~X~
~I
HBTJR'

I......

~
I

~

FBTJR

1

)K
'I'

I

~

c::::

GRxD

1

'I

:

GRxD

FBTJR
270431-15

10-130

intJ

~[Q)\\7~OO©~ OOOI?@OOIMl~ii'O@OO

SOC152JAlS3C152JAlSOC152JB

GSC TRANSMIT TIMINGS (INTERNAL BAUD RATE GENERATOR)

I

~I'--------BT--------~'I

=::x
I

MANCHESTER

I

? X, ?

I

?

X,..-~?r--x:::: GTxD
'----"""Tl~..,,_"':'+~"'------''--''''~~,'---'I :~~
I

I_----H-B-TJ-T-~-~I~-~--F-BT-JT---~I
NRZ1=::X

~.

~

.~

~ GTxD

ai'

FBTJT
270431-16

GLOBAL SERIAL PORT TIMINGS-External Clock
Symbol

Parameter

16.5 MHz

. Variable Oscillator

Min

Max

Min

0.009

2.4

0.009

Unit

Max

x

1/ECBT

GSC Frequency with an
External Clock

ECH

External Clock High

15.5

2TClCl
+ 30ns

ns

ECl

External Clock low

155

2TClCl
+ 30 ns

ns

ECRT

External Clock Rise
Time(11)

20

20

ns

ECFT

External Clock Fall
Time(12)

20

20

ns

ECDVT

External Clock to Data
Valid Out - Transmit
(to External Clock
Negative Edge)

150

150

ECDHT

External Clock Data
Hold - Transmit
(to External Clock
Negative Edge)

Fosc

0.145

MHz

ns

ns
0

0

ECDSR

External Clock Data
Set-up - Receiver
(to External Clock
Positive Edge)

45

45

ns

ECDHR

External Clock to Data
Hold - Receiver
(to External Clock
Positive Edge)

50

50

ns

10-131

intJ

80C152JA/83C152JA/80C152JB

~IQ)\YI~OO©[§ OOOIr@OO[M)~'iiO@OO

GSC TIMINGS (EXTERNAL CLOCK)
f4"I'----ECBT ------+1'1

----x

1

EXTERNAL CLOCK

1

1.
~ECL----:

:

/

: - - - ECH - . : "'I_ _ _--J
-+j
:-- ECDVT

_ _....;...1

TRANSMIT DATA

'X

:X,.-.;;...;.------...;....--

X

ECDHT -+t

;....~--------....- -

f4"I'----ECBT------+t·1
1
1

EXTERNAL CLOCK

----x'--___J/:,-----..,.
1

1

RECEIVE DATA

I~______

- : ECDSR '--ECDHR-:

-~'''':--X

,

1

J

/,-----.. .X

~

1

Xr -;---......------..:.:.-,~~--------~~--

270431-17

10-132 .

inter

27C64/S7C64

64K (SK

x S) CHMOS PRODUCTION AND
UV ERASABLE PROMS

•

•
•

CHMOS Microcontroller and
Microprocessor Compatible
- 87C64-lntegrated Address Latch
- Universal 28 Pin Memory Site, 2-line
Control
Low Power Consumption
-100}J-A Maximum Standby Current

•

High Performance Speeds
- 150 ns Maximum Access Time

•

New Quick-Pulse Programming™
Algorithm (1 second programming)

•

Available in 28-Pin Cerdip and Plastic
DIP Package and 32-Lead PLCC
Package.

Noise Immunity Features
± 10% Vee Tolerance
- Maximum Latch-up Immunity
Through EPI Processing

(See Packaging Spec, Order #231369)

-

Intel's 27C64 and 87C64 CHMOS EPROMs are 64K bit 5V only memories organized as 8192 words of 8 bits.
They employ advanced CHMOS*II-E circuitry for systems requiring low power, high performance speeds, and
immunity to noise. The 87C64 has been optimized for multiplexed bus microcontroller and microprocessor
compatibility while the 27C64 has a non-multiplexed addressing interface and is plug compatible with the
standard Intel 2764A (HMOS II-E).
The 27C64 and 87C64 are offered in both a ceramic DIP, Plastic DIP, and Plastic Leaded Chip Carrier (PLCC)
Packages. Cerdip packages provide flexibility in prototyping and R&D environments; whereas Plastic DIP and
PLCC EPROMs provide optimum cost effectiveness in production environments. A new Quick-Pulse ProgrammingTM Algorithm is employed which can speed up programming by as much as one hundred times.
The 87C64 incorporates an address latch on the address pins to minimize chip count in multiplexed bus
systems. Designers can eliminate an external address latch by tieing address and data pins of the 87C64
directy to the processor's multiplexed address/data pins. On the falling edge of the ALE input (ALE/CE),
address information at the address inputs (Ao-A12) of the 87C64 is latched internally. The address inputs are
then ignored as data information is passed on th~ same bus.
The highest degree of protection against latch·up is achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mAon address and data pins from -1V to Vcc + 1V.
'liMOS and CHMOS are patented processes of Intel Corporation.

DATA OUTPUTS
0 0-07

OUTPUT ENABLE
PROG LOGIC

OUTPUT BUffERS.

Y-GATING

65,536 BIT
CELL MATRIX

Shaded 'Areas' i> .:::';,:;:::represent the 87C64 version

290000-1

Figure 1. Block Diagram

10-133

October 1987
Order Number: 290000-007

27C64/87C64

27256

27128

Vpp

Vpp

2732A

2716

A'2
A7
A6
As
A4
AS
A2
A,

A'2
A7
A6
As

A7
A6
As

A4

A4

As
A2
A,

An

An

00
0,
02

00
0,
02

AS
A2
A,
AD
00
0,
02

A7
A6
As
A4
Aa
A2
A,
AD
00
0,
~

Gnd

Gnd

Gnd

Gnd

27C64/87C64
P27C64/P87C64

2716

2732A

Vee
PCM
N.C.

27128

27256

Vee

Vee

J5GlVl
A,s
As
As
All

..'.

Vee

As
As

A"

Vpp

at'

DE

As
As
All
DENpp

DE

A,o

A,o

A,o

A,o

06
Os
04
Os

07
Os
Os
04
Os

07
Os
Os
04
. Os

~
06
Os
04
Oa

c.._
A,.

~

~
~

~

290000-2

NOTE:
Intel "Universal Site" Compatible EPROM Pin Confi~urations are shown in the adjacent blocks to 27C64 Pins,
Shaded Areas 1u!!L~represenllhe 87C64 version

Figure 2. Pin Configuration

A6

0

All

U

A2
A,

AS

AI

A'

A~

32 PIN PLCC

Ne

0.450" X 0.550"
(11.430 X 13.970)
(MILLIMETERS)
TOP VIEW

AD

Ne
00

290000-11

Figure 3. PLCC(N) Lead Configuration
10-134

A'4
A,s

Vee

As
As
All

DE
~,

27C64/87C64

EXPRESS EPROM Product Family

Extended Temperature (Express)
EPROMs
The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications.
EXPRESS EPROM products are available with 168
± 8 hour, 125°C dynamic burn-in using Intel's standard bias configuration. This process exceeds or
meets most industry specifications of burn-in. The
standard EXPRESS EPROM operating temperature
range is O°C to 70°C. Extended operating temperature range (- 40°C to + 85°C) EXPRESS products
are available along with automotive temperature
range (- 40°C to + 125°C) products. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AaL. This may allow the user to
reduce or eliminate incoming inspection testing.

PRODUCT DEFINITIONS
Operating
Type
Temperature eC)
Oto +70
a
-40 to +85
T
L
-40 to +85
A
-40 to + 125
B
-40 to + 125

Burn-in 125°C (hr)
168 ±8
NONE
168 ±8
NONE
168 ±8

EXPRESS Options

READ OPERATION

27C64/87C64 Versions
Packaging Options
Speed
Versions
-1
-15
-2
-20
-STD
-25
-3
-30

Cerdip

PLCC

T,L,a
T, L,a
T,L,a,A,B
T,L,a,A·
T, L,a,A, B
T,L,a,A
T,L,a,A,B
T,L,a,A

T
T
T,A
T
T,A
T
T,A
T

Plastic
DIP
T
T
T,A
T
T,A
T
T,A
T

D.C. CHARACTERISTICS
Electrical Parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for:
27C64
87C64
Symbol
Parameter
Test Conditions
Min
Max
Vee Standby Current (mA)
CMOS
0.1
CE = Vee,OE = VIL
ISB
TTL
1.0
CE = VIH, OE = VIL
lee1(1)
Vee Active Current (mA)
TIL
20,30
OE = CE = VIL
Vee Active Current at
TIL
20,30
OE = CE = VIL
High Temperature
Vpp = Vee, Tambient = 85°C
NOTE:

1. See notes 4 and 6 of Read Operation D.C. Characteristics.

30~s

H

AOruLJ
:'rLS
Vee

A'2

°00,
°2
290000-13

= +sv
vpp = +sv
DE

290000-14

Binary Sequence from Ao to A12

= 1 Kfl
vee = +sv
GND = OV
CE = 33.3 KHz
PGM = +sv
R

Burn·ln Bias and Timing Diagrams
10-135

intJ

27C64/87C64

ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
_
During Read ............. ~ .... O°C to + 70°C(2)
Temperature Under Bias ......... -lO°C to + 80·C
Storage Temperature .......... - 65°C to + 150·C
Voltage on Any Pin with
Respect to Ground .............. - 2~OV to 7V(1)

• Notice: Stresses above those listed under ':Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Voltage on Pin Ag with
Respect to Ground ......... -2.0V to + 13.5V(1)
Vpp Supply Voltage with Respect to Ground
During Programming ......... - 2.0V to + 14V(1)
Vcc Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.OV(1)

READ OPERATION D.C. CHARACTERISTICS O°C s TA S + 70°C
Symbol

Typ(3)

Max

Unit

Test Condition

0.01

1.0

,."A VIN

=

±10

,."A VOUT

6

100

,."A

ICMOS

5

100

ITTL

4

1.0

,."A
mA

4,6

20,30

mA

Parameter

III

Input Leakage Current

ILO

Output Leakage Current

IpP1

Vpp Current Read

ISB

Vcc Current Standby
with Inputs-

Notes

Min

ICC1

Vcc Current Active

VIL

Input Low Voltage (± 10% Supply)
(TTL)

-0.5

0.8

Input Low Voltage
(CMOS)

-0.2

0.2

2.0

Vcc+ 0.5

Vcc- 0.2

Vcc+ 0.2

VIH

f = 5 MHz, lOUT = 0 mA

Input High Voltage(± 10% Supply)
(TTL)
Input High Voltage
(CMOS)

VOL

Output LOw Voltage

VOH

Output High Voltage

los
Vpp

Output Short Circuit Current

7

Vpp Read Voltage

8

,

OV to 5.5V

= OV to 5.5V
Vpp = Vcc
CE = Vcc
CE = VIH
CE = VIL

0.45
3.5
Vcc- 0.7 _

V Vpp = Vcc

V Vpp = Vcc
V 10L =2.1 mA
V

100

mA

Vce

V

10H= -2.5mA

NOTES:
1. Minimum D.C. input voltage is -0.5V. During transitions.
the inputs may undershoot to - 2.0V for periods less than
20 ns. Maximum D.C. Voltage on output pins is
Vce + 0.5V which may overshoot to Vee + 2V for periods
less than 20 ns.
2. Operating temperature is for commercial product definedby this specification. Extended temperature options are
available in EXPRESS and Military version.
S. Typical limits are at Vee = 5V; TA = + 25°C.
4. 20 mA forSTD and -3 versions; 30 mA for -2 and
150 ns version-!!.
VIL. VIH levels at TTL inputs.

5. ALE ICE or CE is Vee ± 0.2V. All other inputs can have
any value within spec.
6. Maximum Active power usage is the sum Ipp + Icc. The
maximum current value is with Outputs 00 to 07 unloaded.
7. Output shorted _for no more than one second. No- more
than one output shorted at a time. los is sampled but not
100% tested.
8. Vpp may be one diode voltage drop below Vee. It may
be connected directly to Vee.

10-136

intJ

27C64/87C64

READ OPERATION

+ 70·G

A.C. CHARACTERISTICS 27C64(1) O·G ~ TA ~
Vee ±5%

27C64-1
N27C64-1
P27C64-1

27C64-2
N27C64-2
P27C64-2

27C64
N27C64

27C64-3
N27C64-3

27C64-15
N27C64-15
P27C64-15

27C64-20
N27C64-20
P27C64-20

27C64-25
N27C64-25

27C64-30
N27C64·30

Versions (3)
Vee ±10%

Symbol

Characteristic

Min

Max

Min

Max

Min

Max

Min

Unit

Max

tACC

Address to Output Delay

150

200

250

300

ns

tCE

CE to Output Delay

150

200

250

300

ns

tOE

OE to Output Delay

75

75

100

120

ns

tDF(2)

OE High to Output High Z

35

55

60

105

ns

tOH(2)

Output Hold from Addresses, CE
or OE Change·Whichever is First

0

0

0

0

ns

NOTES:
1. A.C. characteristics tested at VIH = 2.4V and VIL = 0.45V.
Timing measurements made at VOL = O.SV and VOH = 2.0V.
2. Guaranteed and sampled.
3. Model Number Prefixes: No prefix = Cerdip; P = Plastic DIP; N = PLCC.

A.C. WAVEFORMS 27C64
V,H-----"\
ADDRess
VALID.

ADDRESSES
VIL _ _ _ _ _J

V,H

-------+-,.

V,H

-------+----""

_--ICEI31~

~-----t.cc-------<·I

+H++<

OUTPUT _ _ _ _ _~H;,;;IG;,;;H;,;;Z_ _ _ _ _

HIGHZ

290000-5
NOTES:
1. Typical values are for T A = 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-toE after the falling edge of CE without impact on tCE.

10-137

27C64/87C64

A.C. CHARACTERISTICS

1II«llo·c:5: T A :5: + 70·C

Vee ±5%

87C64-1
N87C64-1
P87C64-1

87C64-2
N87C64-2
P87C64-2

87C64
N87C64

87C64-3
N87C64-3

Vee ±10%

87C64-15
N87C64-15
P87C64-15

87C64-20
N87C64-20
P87C64-20

87C64-25
N87C64-25

87C64-30
N87C64-30

Versions (3)

Symbol

Parameter

Max

Min

Min

. Min

Max

Max

Min

Unit

Max

tLL

Chip Deselect Width

50

50

60

75

ns

tAL

Address.to CE-Latch Set-up

7

20

25

30

ns

tLA

Address Hold from CE-LATCH

.45

50

60

ns

tACL

CE-Latch Access Time

tOE

Output Enable to Output Valid

tCOE

ALE ICE to Output Enable

tCHZ(2)

Chip Deselect to Output in High Z

45

50

tOHZ(2)

Output Disable to Output
in HighZ

35

50

30
150

200

75

75
45

30.

250

300

ns

100

120

ns

60

75

ns

60

75

ns

60

50

ns

NOTES:
1. A.C. characteristics tested at VIH = 2.4V and VIL = 0.45V.
Timing measurements made at VOL = O.BV and VOH = 2.0V.
2. Guaranteed and sampled.
3. Model Number Prefixes: No prefix = Cerdip; P = Plastic DIP; N = PLCC.

A.C. WAVEFORMS .....•!

ALE/CE

tACL
OUTPUTS

-tCOE--t+----IOE

......_ _ _

OE----~

__J

290000-6

CAPACITANCE(1)
Symbol

f = 1.0 MHz

TA = 25·C.

Parameter

Max Unit Conditions

=

CIN

Address/Control Capacitance

6

pF

VIN

COUT

Output Capacitance

12

pF

VOUT

OV

=

OV

NOTE:
1. Sampled. Not 100% tested.
A_C_ TESTING INPUT/OUTPUT WAVEFORM

2.4
0.45

2.0>
0.8

____

TEST POINTS _ _

2.0

A.C. TESTING LOAD CIRCUIT

f

il-'N9"

OUTPUT

~0.8;....

__

3.3Kn

DEVICE
UNDER
TEST

290000-10

~DUT

.l

A.C. Testing: Inputs are driven at 2.4V for a Logic "1 "and 0.45V
'for a Logic "a". Timing measurements are made at 2.0V for a
logic "I" and O.BV for a Logic "0".

CL= 100 pF

290000-3
CL ;= 100 pF
CL Includes Jig Capacitance

10-138

27C64/87C64

DEVICE OPERATION
The modes of operation of the 27C64/87C64 are
listed in Table 1. A single SV power supply is required in the read mode. All inputs are TIL levels
except for VPP and 12V on A9 for inteligent Identifier
mode.
Table 1. Mode Selection for 27C64 and 87C64
Pins

. Vpp

A,LE/CE
CE

OE

PGM
(7)

Ag

Ao

Mode
Read

VIL

VIL

VIH

X(l)

X

Vee

S.OV

DOUT

Output Disable

VIL

VIH

VIH

X

X

Vee

S.OV

HighZ

Standby

VIH

X

X

X

X

Vee

S.OV

HighZ

Programming

VIL

VIH

VIL

X

X

(4)

(4)

DIN

(7)

Vee

Outputs

Program Verify

VIL

VIL

VIH

X

X

(4)

(4)

DOUT

Program Inhibit

VIH

X

X

X

X

(4)

(4)

HIGHZ

inteligent Identifier(3)
-Manufacturer

VIL

VIL

VIH

VH(2)

VIL

Vee

Vee

89 H (6)
88 H (6)

inteligent Identifier(3)
-27C64

VIL

VIL

VIH

VH(2)

VIH

Vee

Vee

07 H

inteligent Identifier(3, 5)
-87C64

VIL

VIL

VIH

VH(2)

VIH

Vee

Vee

37 H

NOTES:

1.
2.
3.
4.
5.
6.
7.

X can be VIL or VIH.
VH = 12.0V ± O.5V.
A1-Aa, A10-12 = VIL.
See Table 2 for Vcc and Vpp voltages.
ALE ICE has to be toggled in order to latch in the addresses and read the signature codes.
The Manufacturer's identifier reads 89H for Cerdip devices; 88H for Plastic DIP and PLCC devices. _
In Read Mode tie PGM and Vpp to Vee.

Read Mode: 27C64

Read Mode: 87C64

The 27C64 has two control functions, both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output enable
(OE) is the output control and should be used to
gate data from the output pins. Assuming that addresses are stable, the address access time (tAee)
is equal to the delay from CE to output (teE). Data is
available at the outputs after a del~f tOE from the
falling edge of OE, assuming that CE has been low
and addresses have been stable for at least
tAee-tOE·

The 87C64 was designed to reduce the hardware
interface requirements when incorporated in processor systems with multiplexed address-data busses.
Chip count (and therefore power and board space)
can be minimized when the 87C64 is designed as
shown in Figure 4. The processor's multiplexed bus
(ADo-7) is tied to both address and data pins of the
87C64. All address inputs of the 87C64 are latched
when ALE/CE is brought low, thus eliminating the
need for a separate address latch.

10-139

inter

27C64/87C6:4

The 87C64 internal address latch is directly enabled
through the use of the ALE/CE line. As the transition
occurs on the ALE/CE from the TTL high to the low
state, the last address presented at the address pins
is retained. Data is then enabled onto the bus from
the EPROM by the OE pin.

Vss Vee RST

Vee Vss

290000-4

Figure 4. 80C31 with 87C64
System Configuration

Standby !\/lode
The 27C64 and 87C64 have Standby modes which
reduce the maximum Vee current to 100 p..A. Both
are placed in the Standby m'ode when CE or
ALE/CE are in the CMOS-high state. When in the
Standby mode, the outputs are in a high impedance
state, independent of the OE input.

Two Line Output Control
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 control lines which
accommodate this multiple memory connection. The
two control lines allow for:
a) the lowest possible memory power dissipation,
and
b) complete assurance that output. bus .contention
will not occur.
To use these two control lines most efficiently, CE
(or 'ALE/CE) should be decoded and used' as the
primary device selecting function, while OE should
be made a common connection to all devices in the
array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low power standby
mode and that the output pins are active only when
data is desired from a particular memory device.

SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
. edges of Chip Enable. The magnitude of these transient and inductive current peaks is dependent on
the output capacitive and inductive loading of the
device. The associated transient voltage peaks can
be. suppressed by complying with Intel's Two-Line
Control; and by properly selected decoupling capacitors. It is recommended that a 0.1 p..F ceramic capacitor be used on every device between Vee and
GND. This should be a high frequency capaCitor for
low inherent inductance and should be placed as
clo.se to the device as possible. In addition, a 4.7 p..F
bulk electrolytic capacitor should be used between
Vee and GND for every eight devices. The bulk capacitor should be located near where tlie power supply is connected to the array. The purpose of the
,bulk capacitor is to overcome the voltage droop
caused by the inductive effect of PC board-traces.

PROGRAMMING MODES
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations. Although. only "Os" will be programmed;
both "1 s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.
The device is in the programming mode when Vpp is
raised to its programming voltage (See Table 2) and
CE (or ALE/CE) and PGM are both at TTL low and
OE = VIH. The data to be programmed is applied 8
, bits in parallel' to the data output pins. The levels
required for the address and data inputs are TTL:

Program Inhibit
Programming of multiple EPROMSin parallel with
different data is easily accomplished by using ·the
Program Inhibit mode. A high-level CE (or ALE/CE)
or PGM input inhibits the other devices from being
programmed.

10-140

inter

27C64/87C64

Except for CE (or ALE/CE), all like inputs (including
OE) of the parallel EPROMs may be common. A TTL
low-level pulse applied to the £9lM input with Vpp at
its programming voltage and CE (or ALE/CE) = VIL
will program the selected device.

Program Verify
A verify (read) should be performed on the programmed bits to determine that they have been correctly programme!LThe verify is performed with OE
and CE (or ALE/CE) at VIL, PGM at VIH, and Vee
and Vpp at their programming voltages. Data should
be verified a minimum of tOE after the falling edge of
OE.

inteligent Identifier™ Mode
The inteligent Identifier Mode allows the. r~adin~ ~ut
of a binary code from an EPROM that will Identify Its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
Mode.
Byte 0 (AO = VIL) represents the manufacturer code
and byte 1 (AO = VIH) the device identifier code.
These two identifier bytes are given in Table 1.
ALE/CE of the 87C64 has to be toggled in order to
latch in the addresses and read the Signature
Codes.

ERASURE CHARACTERISTICS (FOR
CERDIP EPROMS)
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluprescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
.this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 )J-W/cm2 power rating. The EPROM should be placed withi~ 1 in~h of
the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000 )J-W/
cm 2). Exposure of the device to high intensity UV
light for longer periods may cause permanent damage.

CHMOS NOISE CHARACTERISTICS
Special EPI processing techniques have enabled Intel to build CHMOS with features adding to system
reliability. These include input/output protection to
latch-up. Each of the data and address pins will not
latch-up with currents up to 100 mA and voltages
from -1V to Vee + 1V.
Additionally, the Vpp (programming) pin is designed
to resist latch-up to the 14V maximum device limit.

10-141

27C64/87C64

290000-12

Figure 5. Quick-Pulse Programming™ Algorithm

Quick-Pulse Programming™ Algorithm
Intel's 27C64 and 87C64 EPROMs can now be programmed using the Quick-Pulse Programming Algorithm, developed by Intel to substantially reduce the
throughput time in the production environment. This
algorithm allows these devices to be programmed in
under one second, almost a hundred fold improvement over previous algorithms. Actual programming
time is a function of the PROM programmer being
used.

fication to determine when the address byte has
been successfully programmed. Up to 25 100 /Jos
pulses per byte are provided before a failure is recognized. A flowchart of the Quick-Pulse Programming Algorithm is shown in Figure 5.
For the Quick Pulse Programming Algorithm, the entire sequence of programming pulses and byte verifications is performed at Vee = 6.25V and Vpp at
12.75V. When programming of the EPROM has
been completed, all bytes should be compared to
the original data with Vee = Vpp = 5.0V.

The Quick-Pulse Programming Algorithm uses initial
pulses of 100 microseconds followed by a byte veri-

10-142

inter

27C64/87C64

D.C. PROGRAMMING CHARACTERISTICS

(27C64/87C64) T A = 25°C ± 5°C

Table 2
Symbol

Limits

Parameter

III

Input Current (All Inputs)

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

Min

Max

Unit

1.0

p.A

-0.1

0.8

V

2.0

Vee

+ 0.5

0.45
3.5

Test Conditions
(Note 1)
VIN

= VIL or VIH

V

IOL

V

IOH

= 2.1 mA
= -2.5 mA

CE

= VIL

V

lee2(3)

Vee Supply Current

IpP2(3)

VPP Supply Current (Program)

VIO

Ag inteligent Identifier Voltage

11.5

Vpp

Programming Voltage

12.5

13.0

V

Vee

Supply Voltage During Programming

6.0

6.5

V

30

mA

30

mA

12.5

V

A.C. PROGRAMMING CHARACTERISTICS 27C64
T A = 25°C
Symbol

± 5°C,

See Table 2 for Vee and Vpp Voltages
Limits

Parameter
Min

Typ

Max

Unit

tAS

Address Setup Time

2

p.s

toES

OE Setup Time

2

p.s

tos

Data Setup Time

2

p.s

tAH

Address Hold Time

0

p.s

tOH

Data Hold Time

2

tOFP

OE High to Output Float Delay

0

tvps

Vpp Setup Time

2

p.s

tves

Vee Setup Time

2

p.s

teEs

CE Setup Time

2

p.s

tpw

PGM Program Pulse Width

95

toE

Data Valid from OE

A_C_ CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) ...... 20 ns
Input Pulse Levels ...•.............. 0.45V to 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 3.5V '

Conditions
(Note 1)

p.s
130

100

ris

105

p.s

150

ns

(Note'2)

Quick-Pulse

N'OTES: .
1. Vee must be applied simultaneously or before Vpp and
removed Simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longer driven-see timing diagram.
3. The maximum current value is with outputs 00 to 07 Unloaded.

10-143

intJ

27C64/87C64

PROGRAMMING WAVEFORMS 27C64
.PRDGRAM

'~

ADDRESSES

VERIFY

-

ADDRESS STABLE

_IA' __
~

DATA IN STABLE

DATA
~ID'

__

~

HIGHZ

DATA OUT

f+'DH.,

_'AH

vlLlD

-

It'

L
~

'OF,!»

12.75V

.-.-/ _'VP'__

Vpp

5.0V

,

8.25V

Vee
5.0V

V,H

CE

,

-.-/ _'ve,_

-

\

V"

_'e,,_
V'H
PGM
V"

V'H

DE
V"

-

~
I,.

topw

,

l-

-

i--

'OES1
\

'OE(2)

I--

-

290000-9

NOTES: "
1. The Input Timing Reference Level is 0.8V for VIL and 2V for a VIH.
2. toE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the 27C64, a 0.1 ,.F capacitor is required across Vpp and ground to suppress spurious voltage
transients which can damage the device.

10-144

intJ

27C64/87C64

A.C. PROGRAMMING CHARACTERISTICS 87C64:
= 25°C ±5°C, See Table 2 for Vee and Vpp Voltages: .
. ..

TA

Lilnits

..Parameter

Symbol

Min
tvps

Vpp Setup Time

Typ

Unit

2

p.s

tves

Vee Setup Time

2

p's

tLL

Chip Deselect Width

2

p.s

tAL

Address to Chip Select Setup

1

p.s

tLA

Address Hold from Chip Select

1

p.s

tpw

PGM Pulse Width

95

tos

Data Setup Time

2

tOFP

OE High to Data Float

0

tOES

Output Enable Setup Time

2

tOE

Data Valid from Output Enable

tOH

Data Hold Time

2

tJ. s

teEs

CE Setup Time

2

p.s

100

Conditions

Max

105

p.s

Quick-Pulse

p.s
130

ns
p.s

150

ns

NOTE:
1. Programming tolerances and test conditions are the same as 27C64.

PROGRAMMING WAVEFORMS :etc6~1
)I( ADDRESSES (

ADDRESS

, !-=tAL+ -tLA-

-

DATA

I-

ALE/CE

HD~~tOES-r--J:OE

I-tDS "

XI-tDf:J-

tLL(1)

Vpp

~
(1)

Vee

t vps
- - tves

tCES-

~
~

tpw"

-;~;w
\-..J

290000-8

NOTE:
1. 12.75V Vpp & 6.25V Vee for Quick-Pulse Programming Algorithm.

10-145

inter

·87C257
256K (32Kx 8) CHMOS UV ERASABLE PROM

•

CHMOS/NMOS Microcontroiler and
Mlcroproce$sor Compatible
- 87C257-1ntegrated Address Latch
- Universal 28 Pin Memory Site, 2·line
Control
.

•

Noise Immunity Features

- ± 10% Vee Tolerance
- Maximum Latch·up Immunity
Through EPI Processing

'., Low Power Consumption
• High Performance Speeds
- 170 ns Maximum Access Time

•

New Quick·Pulse Programming™
Algorithm
- 4 Second Programming

•

Available in 28·Pln Cerdip Package
(See Packaging Spec .• Order '" 231369)

Intel's 87C257 CHMOS EPROM is a 256K-bit 5V only memory organized as 32,768 8-bit words. It employs
advanced CHMOS*II-E circuitry for systems requiring low power, high speed performance, and noise immunity. The 87C257 is optimized for compatibility with multiplexed address/data bus microcontrollers such as
Intel's 16 MHz 80.51- and 80.96- families.
The 87C257 incorporates latches on all address inputs to minimize chip count, reduce cost, and simplify
design of multiplexed bus systems. The 87C257's internal address latch allows address and data pins to be
tied directly to the processor's multiplexed address/data pins. Address information (inputs Ao-A14) is latched
early in the memory-fetch cycle by the falling edge of the ALE input. Subsequent address information is
ignored while ALE remains low. The EPROM can then pass data (from pins 00-07) on the same bus during
the last part of the memory-fetch cycle.
The 87C257 is offered in a ceramic DIP package, providing flexibility in prototyping and R&D environments.
The 87C257 employs the Quick-Pulse Programming™ Algorithm for fast and reliable programming.
Intel's EPI processing achieves the highest degree of latch-up protection. Address and data pin latch-up
prevention is provided for stressesup to 10.0. mA from -1V to Vcc + 1V.
'HMOS and, CHMOS are patented processes of Intel Corporation.

DATA OUTPUTS

0 0-07

5E

CE
ALE

OUTPUT ENABLE
PROG LOGIC

OUTPUT BUffERS

CHIP ENABLE
ADDRESS LATCH ENABLE
Y DECODE

Y-GATING

X DECODE

262,144 BIT
CELL MATRIX

:>:

~

Ao-A I4
ADDRESS
INPUTS

In
In

'"'"
Q
Q

..:
290135-1

Figure 1. Block Diagram

10.-146

October 1987
Order Number: 290135-002

87C257

Pin Names
Ao-A14
00-0 7

OUTPUTS

OE

OUTPUT ENABLE

CE

CHIP ENABLE

ALE/vpp

Address Latch
Enable/Vpp

N.C.

NO CONNECT
87C257

87C64
Vpp
A12
A7
As
As
A4
As
A2
A1
Ao
00
01
02
Gnd

ADDRESSES

ALE/Vpp
A12
A7
As
As
A4

87C64

vee
A14
A13

As
A9
All
OE
AID
CE

A,

A2
AI
AD
00
01
02

~

06
Os
04
03

GND

Vee
PGM
N.C
As
Ag
An
OE
A10
ALE/CE
07
Os
Os
04
Os

290135-2

Figure 2. DIP Pin Configuration

NOTE:
Intel "Universal Site"-Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent.

10~147

inter

87C257

. EXTENDED TEMPERATURE
(EXPRESS) EPROMs The Intel EXPRESS EPROM family receives additional processing to enhance product characteristics. EXPRESS processing is available for several
EPROM densities allowing the appr-opriate memory
size to match system applications. EXPRESS
EPROMs are available with 168 ±8 hour, 125·C dynamic burn-in using Intel's standard bias configuration. This process meets or exceeds most industry
burn-in specifications. The standard EXPRESS
EPROM operating temperature range is O·C to
+ 70·C. Extended operating temperature range
(-40·C to +85·C) EXPRESS and automotive temperature range (- 40·C to + 125·C) products are
also available. Like all Intel EPROMs, the EXPRESS
EPROM family is inspected to 0.1 % electrical AQL.
This allows reduction or elimination of incoming testing.

Vee

07
06
05

°4
°3
29013S-4
OE = SVR = 1 KflVcc= +SV
ALElVpp = + SV Vss = GND CE = GND

AUTOMOTIVE AND EXPRESS
OPTIONS
Versions
Speed
Versions

Packaging Options

-200V05

A

-250V10

A

-250V05

A

Cerdlp

•
29013S-S
Binary Sequence from AD 10 A14

AUTOMOTIVE AND EXPRESS EPROM
PRODUCT FAMILY

Burn-In Bias and Timing Diagrams

PRODUCT DEFINITIONS
Type

Operating
Temperature ("C)

Burn-in 125·C
(hr)

Q

O·Cto +70·C

168 ±8

T

- 40·C to + 85·C

NONE

L

- 40·C to + 85·C

168 ±8

A

- 40·C to + 125·C

NONE

B

- 40·C to + 125·C

168 ±8

10-148

infef

87C257

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
ex/ended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Operating Temperature, During
Read .....••••••.••.•••....•. O'C to + 70'C(2)
Temperature Under Bias ..••... -1 O'C to + 80'C(2)
Storage Temperature .......... - 65'C to + 150'C
Voltage on any Pin with
Respectto Ground ........••••• - 2V to + 7V(1)
Voltage on Ag with
Respect to Ground ....•..••. - 2V to + 13.5V(1)
Vpp Supply Voltage with Respect to Ground
During Programming •.•.•.•.. - 2V to + 14.0V(1)
Vcc Supply Voltage with
.
Respectto Ground ....•......• -2V to +7.0V(1)

NOTICE Specifications contained within the
following tables are subject to change.

READ OPERATION
D.C. CHARACTERISTICS TTL and NMOS Inputs
Symbol

Parameter

III

Input Load Current

ILO

Output Leakage Current

158

Vee Current Standby
with Inputs-

Notes

Max

Units

0.Q1

1.0

".A

I Stable

Vee Current Active

5

VIL

Input Low Voltage ( ± 10% Supply)

1

VIH

Input High Voltage (± 10% Supply)

VOL

Output Low Voltage

VOH

Output High Voltage

los

Output Short Circuit Current

-0.5
2.0

".A

VOUT = OV to 5.5V

10

mA

CE

1.0

mA

CE = VIH. ALE = VIL

30

mA

CE = VIL. ALE = VIH
f = 5 MHz. lOUT = 0 mA

O.B

V

Vee

+ 0.5

2.4

6

Test Condition
VIN = OV to 5.5V

±10

0.45

D.C. CHARACTERISTICS
III

Typ(3)

I' Switching

leel

Symbol

Min

100

= ALE = VIH

V
V

10L = 2.1 mA

V

10H = -400".A

mA

CMOS Inputs

Parameter

Notes

Min

Input Load Current

ILO

Output Leakage Current

158

Vee Current Standby
with Inputs-

leel

Vee Current Active

VIL

Input Low Voltage (± 10% Supply)

-0.2

VIH

Input High Voltage (± 10% Supply)

0.7 Vee

VOL

Output Low Voltage

VOH

Output High Voltage

los

Output Short Circuit Current

1 Switching

Typ(3)

Max

Units

0.01

1.0

".A

±10

".A

VOUT = OV to 5.5V

6

mA

CE = ALE = Vee

100

".A

CE

15

mA

CE = VIL. ALE = VIH
f = 5 MHz. lOUT = 0 mA

0.8

V

4

1 Stable

5

Vee

+ 0.2

0.4
Vee - O.B

6

Test Condition
VIN = OV to 5.5V

100

= Vec. ALE = GND

V
V

10L = 2.1 mA

'V

10H = -2.5 mA

mA

NOTES:
1. Minimum D.C. input voltage is -0.5V. During transitions. the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum D.C. voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. Typical limits are at Vee = 5V. TA = + 25'C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
10-149

87C257

READ OPERATION

A.C. CHARACTERISTICS(1) O·C s: TA s: + 70·C
Verslons(3)
Symbol

I Vee ±5%
I Vee ±10%

87C257·170V05

Characteristic

Min

Max

87C257-200V05

87C257-250V05

87C257-200V10

87C257-250V10

Min

Max

Min

Units

Max

tACC

Address to Output Delay

170

200

250

ns

tCE

CE to Output Delay

170

200

250

ns

tOE

OE to Output Delay

70

75

100

ns

tOF(2)

OE High to Output High Z

35

40

55

ns

toH(2)

Output Hold from Addresses, CE or
OE Change·Whichever is First

0

0

0

ns

tLL

Latch Deselect Width

35

55

60

ns

tAL(2)

Address to Latch Set·Up

7

15

25

ns

tLA

Address Hold from LATCH

20

30

40

ns

tLOE

ALE to Output Enable

20

30

.40

ns

NOTES:
1. See A.C. Testing Input/Output Waveforms for timing
measurements.
.
,
2. Guaranteed and sampled.
3. Model Number Prefixes: No Prefix = CERDIP.

A.C. CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) ....•. 10 ns
Input Pulse Levels., ................... VOL to VOH
Input Timing Reference Level ..•.........•... 1.5V
Output Timing Reference Level ........ VIL and VIH

A.C. WAVEFORMS

V1H

ALE
V1L
VIH _ _ _ _~~--+_

CE

V1L
V ____
IH

(2)
+ _________
_
t LOE --~-tOE

Of

V1L

~~~---~cc------~

OUTPUT VIH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..!i!:~L._t:§~~~~§:~~
HIGH Z
V1L

290135-6

NOTES:
1. This parameter is only sampled and is not 100% tested.
2. DE may be delayed up to IcE:"tOE after the falling edge of CE without impact on tCE'

10-150

inter

87C257

CAPACITANCE(1}
Symbol

=

TA

25°C. f

=

1.0 MHz

Parameter

Max Units Conditions

=

CIN

Address/Control Capacitance

6

pF

VIN

COUT

Output Capacitance

12

pF

VOUT

OV

=

OV

NOTE:
1. Sampled. Not 100% tested.

A.C. TESTING INPUT/OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

1.:~

~~IN914
1.5 -lEST POINlS ::::::

IH OUTPUT

V1L

-

3.3k.D.

DEVICE
UNDER
TEST

290135-7

A.C. testing inputs are driven at VOH for a Logic "I"
and VOL for a Logic "a". Timing measurements are
made-at VIH for a Logic "1" and VIL for a Logic "a".

:e--

OUT
CL
290135-S

CL = 100 pF
CL Includes Jig Capacitance

DEVICE OPERATION
Table 1 lists 87C257 operating modes. Read mode requires a single 5V power supply. All input. levels are TTL
or CMOS except A9 in inteligent Identifier mode and Vpp.
Table 1. Mode Selection
Pins

ALE/
Vpp

Vee

X

X

5.0V

DOUT

X

X

5.0V

HighZ

X

5.0V

HighZ

(Note 4)

(Note 4)

DIN

CE

OE

As

Ao

Read

VIL

VIL

X(1)

Output Disable -

VIL

VIH

X

Standby

VIH

X

X

X

Programming

VIL

VIH

X

X

Mode

Outputs

Program Verify

VIH

VIL

X

X

(Note 4)

(Note 4)

DOUT

Optional Program
Verify

VIL

VIL

X

X

Vee
(Note 4)

(Note 4)

DCUT

Program Inhibit

VIH

VIH

X

X

(Note 4)

(Note 4)

HighZ

VIL

X

Vec

89H

VIH

X

VCC

24H

inteligent Identifier(3)
-Manufacturer

VIL

VIL

VH(2)

inteligent Identifier(3)
-87C257

VIL

VIL

VH(2)

NOTES:
1. X can be VIL or VIH.
2. VH = 12.0V ±0.5V.
3. AI-As. AlO-12 = VIL. A13-14 = X.
4. See Table 2 for Vee and Vpp programming voltages.

10-151

inter

87C257

Read Mode

Two Line Output Control

The 87C257 has two control functions; both must be
logica"y active to obtain data at the outputs. Chip
Enable (CE) is the power control and the device-select. Output enable (OE) gates data to. the output
pins by controlling the output buffer. When the address is stable (ALE = VIH) or latched (ALE = VII),
the address access time (tACe) equals the delay
from CE to output (teE). Ou~ts display valid data
tOE after the falling edge of OE, assuming tACC and
teE times are met.

EPROMs are often used in larger memory arrays.
Intel provides two contol inputs to acCommodate
multiple memory connections. Two-line control provides for:
a) the lowest possible memory power dissipation,

The 87C257 reduces the hardware interface in multiplexed address-data bus systems. Figure 4 shows a
low power, sma" board space, minimal chip
87C257/microcontro"er design. The processor's
multiplexed bus (ADo.7) is tied to the 87C257's address and data pins. No separate. address latch is
needed because the 87c257 latches a" address inpilts when ALE is low.
The ALE input controls the 87C257's internal address latch. As ALE transitions from VIH to VIL, the
last address present at the address pins is retained.
The OE control can then enable EPROM data onto
the bus.

vss vee RST

290135-9

Md

.

b) complete assurance that output bus contention
will not occur.
To efficiently ·use these two control inputs, an address decoder should enable CE, while OE should
be connected to a" memory-array devices and the
system's READ control line. This assures that only
selected memory devices have active outputs while
deselected memory devices are in low-poWer standby mode.

SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in three supply current (ICC) issue!r-standby current levels, active current levels, and transient
current peaks produced by falling and rising edges
. of Chip Enable. Transient current magnitudes depend on the device outputs' capacitive and inductive
loading. Two-Line Control and proper decoupling ca'
pacitor selection will suppress transient voltage
peaks. Each device should have a 0.1 IlF ceramic
'capacitor connected between its Vcc and GND. This
high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device.
Additiona"y, for every eight devices, a 4.7 IlF electrolytic capacitor should be placed between Vcc.and
GND at the array's power supply connection. The
bulk capacitor will overcome voltage slumps caused
by PC board trace inductances.

PROGRAMMING MODES'

Figure 4. 80C31 with 87C257
System Configuration

Caution: Exceeding 14Von Vpp will permanently
damage the devIce.

Standby Mode
The standbLmode substantially reduces Vcc current. When CE = VIH, the standby mode places the
outputs in a high impedance state, independent of
the OE input.

Initia"y, and after each erasure, a" EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word

10-152

intJ

87C257

can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
The programming mode is entered when Vpp is
raised to its programming voltage (see Table 2).
Data is programmed by applyil]Lan 8-bit word to the
output pins (00-7). Pulsing CE to TTL-low while
OE = VIH will program data. TTL levels are required
for address and data inputs.

Program Inhibit
The Program Inhibit mode allows parallel programming of multiple EPROMs with different data. With
Vpp at its programming voltage, a CE-Iow pulse programs the desired EPROM. CE-high inputs inhibit
programming of non-targeted devices. Except for CE
and OE, parallel EPROMs may have common inputs.

Program Verify
With Vpp and Vee at their programming voltages, a
verify (read) determines that bits are correctly programmed. The verify is performed with CE = ~
and OE = VIL. Valid data is available tOE after OE
falls low.

Optional Program Verify
The optional verify allows parallel programming and
verification when several devices share a common
bus. It is performed with CE = OE = VIL and Vpp =
Vee = 6.25V. The normal read mode is then used
for .E!:9gram~erify. Outputs will tri-state depending
on OE and CEo

inteligent Identifier™ Mode
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type. Programming equipment can automatically match a device
with its proper programming algorithm.
This mode is activated when programming equipment forces 12V ±0.5V on the EPROM's Ag address line. With A1-Aa, A1O-A12 = VIL (A13-14 are
don't care), address line Ao = VIL will present the
manufacturer's code and Ao = VIH'the device code
(see Table 1). When Ag = VH, ALE need not be
toggled to latch each identifier address. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

ERASURE CHARACTERISTICS (FOR
CERDIP EPROMS)
Exposure to light of wavelength shorter than 4000
Angstroms (A) begins EPROM erasure. Sunlight and
some fluorescent lamps have wavelengths in the
3000.,...4000A range. Constant exposure to room-Iev-'
el fluorescent light can erase an EPROM in about 3
years (about 1 week for direct sunlight). Opaque labels over the window will prevent unintentional erasure under these lighting conditions.
The recommended erasure procedure is exposure,
to 2537A ultraviolet light. The minimum integrated
dose (intensity x exposure time) is 15 Wsec/cm 2.
Erasure time using a'12000 p.W/cm2 ultraviolet
lamp is approximately 15 to 20 minutes. The
EPROM should be placed about 1 inch from the
lamp. The maximum integrated dose is 7258
Wsec/cm 2 (1 week @ 12000 p.W/cm 2 ). High intensity UV light exposure for longer periods can cause
permanent damage.

10-153

inter

87C257

290135'-10

Figure 5. Qulck·Pulse Programmlng™ Algorithm

CHMOS NOISE CHARACTERISTICS
System reliability is enhanced by Intel's CHMOS
EPI-process techniques. Protection on each data
and address pin prevents latch-up; even with 100
mA currents and voltages from -1V to Vee + 1V.
Additionally, the Vpp pin is designed to resist latchup to the 14V maximum device limit.
.

Quick-Pulse Programmlng™ Algorithm
The Quick-Pulse Programming algorithm programs
Intel's 87C257 EPROM. Developed to substantially
reduce production programming throughput time,
this algorithm can program a 87C257 in under four
seconds. Actual programming time depends on the
PROM programmer used.
.
The Quick-Pulse Programming algorithm uses a 100
microsecond initial-pulse followed by a byte verifica-

tion to determine when the addressed byte is correctly programmed. The algorithm terminates if 25
100/kS pulses fail to program a byte. Figure 5 shows
the Quick-Pulse Programming algorithm flowchart.
The entire program-pulse/byte-verify sequence is
performed with Vee = 6.25V and Vpp = 12.75V.
When programming is complete, all bytes should be
compared to the original data with Vee = 5.0V.

Alternate Programming
Intel's 27C256 and 27256 Quick-Pulse Programming
algorithms will also program the 87C257. By overrid. ing a check for the inteligent Identifier, older or nonupgraded PROM programmers can program the
87C257. See Intel's 27C256 and 27256 data sheets
for programming waveforms of these alternate algorithms.

10-154

intJ

87C257

D.C. PROGRAMMING CHARACTERISTICS

=

TA

25°C ±SoC

Table 2

Symbol

limits

Parameter
Min

III

Unit

1.0

).tA

0.8

V

Input Current (All Inputs)
-0.2

Test Conditions

Max

VIN

=

V

IOL

V

IOH

= 2.1 rnA
= -400).tA

CE

=

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

lee2(3)

Vee Supply Current

IpP2(3)

Vpp Supply Current (Program)

VIO

Ag inteligent Identifier Voltage

11.5

Vpp(1)

Programming Voltage

12.5

13.0

V

Ved 1)

Supply Voltage During Programming

6.0

6.5

V

2.0

Vee

+ 0.5

0.4
Vee - 0.8

VIL or VIH

V

30

rnA

50

rnA

12.5

V

VIL

A.C. PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C; see Table 2 for Vee and Vpp voltages.

Symbol

Limits

Parameter
Min

tAS

Address Setup Time

Typ

Conditions

Max

Unit

2

).ts

tOES

OE Setup Time

2

).ts

tos

Data Setup Time

2

).ts

tAH

Address Hold Time

0

).ts

tOH

Data Hold Time

2

).ts

tOFP(2)

OE High to
Output Float Delay

0

tVPS(1)

Vpp Setup Time

2

tves(1)

Vee Setup Time

2

tpw

CE Program Pulse Width

toE

Data Valid from OE

95

130

ns
).ts
).ts

100

105

).ts

150

ns

NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
3. The maximum current value is with outputs 00 to 07 unloaded.

10-155

'V

I

1

1"ta lig ent Identifier. • 1"ta ng ent identifier

I

Manufacturer

Ag

12.0 V . - - - - -

Address~::==>f

AO=VIL

=12.0V

JJ

I "

Dey;ce

Blank Check
Illegal Bit Check

'""'Z:AI-8'Al0-12=VIL~

ADDRESSVALID

I

I'

)~

Pro rom
g

ADDRESS STABLE

I

I

•

I

Program
Verify

I

I

.n;

•

Re~d

I

I

Verify

oC)
JJ
l>

"uun~JJ

,"",u

~

s:
s:

l

Z

Q

VIH

~

Data

VIL '

ALE;::el~ : ~ ~ -

- - - - - - - -

-1-- ~ ~ --~ -----t

<
m

."

oJJ

i

s:

65~~~

en

. --; - ---- --- T -----~ -----

Vee

..,.
01)

~

~
(J1

en

o
N

VIH

cr

..,.CI1

VIL
VIH

~

OE
VIL

290135-11

NOTES:
1. The input timing reference level is VIL = 0.8V and VIH = 2V.
2. toE and tOFP are device characteristics but must be accommodated by the programmer.
,
3. To prevent device damage durir]g programming, a 0.1 ,..F capacitor is required between Vpp and ground to suppress spurious voltage transients.
4. During programming, the address latch function is bypassed whenever Vpp = 12.75V or A9 = VH. When Vpp and A9 are at TTL levels, the address'latch function is
enabled, and the device functions in read mode.
'
'
'
5. Vpp can be 12.75V during Blank Check and Final Verify; if so, CE must be VIH.

~

aID
Iffiil
F

~
~

~
~

C:g

UPI-4S2
CHMOS PROGRAMMABLE 1/0 PROCESSOR
83C452 - 8K x 8 Mask Programmable Internal ROM
87C452P - 8K

x

8 Piggyback EPROM

80C452 - External ROM/EPROM

•
•
•
•
•
•
•

83C452/87C452P/80C452:3.5 to 16 MHz
Clock Rate
Software Compatible with the MCS-51
Family
128-Byte Bi-Directional FIFO Slave
Interface
Two DMA Channels
256 X 8-Bit Internal RAM
34 Additional Special Function
Registers
40 Programmable I/O Lines

•
•

Two 16-Bit Timer/Counters

•
•
•

64K Program Memory Space

Boolean Processor

Addressable RAM
• 8BitInterrupt
Sources
• Programmable
• Channel Full Duplex Serial
64K Data Memory Space
68-Pin PGA
(See Packaging Spec" Order: #231369)

,The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave 1/0 Processor with a sophisticated
bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip, The UPI-452
is the newest member of Intel's UPI family of products, It is a general-purpose slave 1/0 Processor that allows
the deSigner to grow a customized interface solution.
The UPI-452 contains 'a complete 80C51 with twice the on-chip data and program memory. The sophisticated
slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU. To both the
external host and the internal CPU, the FIFO module looks like a bi-directional bottomless buffer that can both
read and write data. The FIFO manages the transfer of data independent of the UPI-4S2 core CPU and
generates an interrupt or DMA request to either CPU, host or internal, as a FIFO service request.
The FIFO consists of two channels:the Input FIFO and the Output FIFO. The division of the FIFO module
array, 128 bytes, between Input channel and Output channel is programmable by the user. Each FIFO byte
has an additional logical ninth bit to distinguish between a data byte and a Data Stream Command byte.
Additionally, Immediate Commands allow direct, interrupt driven, bi-directional communication between the
UPI-452 internal CPU and external host CPU, bypassing the FIFO.
The on-chip DMA processor allows high speed data transfers from one writeable memory space to another.
As many as 64K bytes can be transferred in a, single DMA operation. Three distinct memory spaces may be
used in DMA operations; Internal Data Memory, External Data Memory, and the Special Function Registers
(including the FIFO IN, FIFO OUT, and Serial Channel Special Functions Registers).

10-157

September 1987
Order Number: 231428-003

l

o

o'"
00

,Q
c'"

_z

~":::"

C

!1;

!II

o

01 ~I'"
~ ~I

.....

"II

I

illi
o

Z

o»o::::!;;Itn
~z!:"''i:

iiii
r:::

...

~c~~~

ID

...

:-"
:I>

...n

'"

~

~

41>-

FIFO
INPUT
CHANNEL

FIFO
MODULE
SLAVE-

U1
CX>

"

FIFO
OUTPUT
CHANNEL

-

HOSTFIFO
INTERFACE

~m

:::T

.....
~

-

-fl- ---------ft --- i:~
"

;::;:

srn~

INTERFACE

ID

HCON

2r:::

HSTAT

., '."

et

~

"'z

:::a 00

it

0

AO~Z

- - - - - - - - - -l} - -

NfAf'TIC

r-

o~I

I

...:',

-

-

-

~
IMMEDIATE
COMMAND

-I

I

~I~

,

HOST DMA
AND
INTERRUPT
REQUEST

Iroo; I

II

,,~

: ;

m
0'
n

: i
:J.r.::. __ .JL_-,
#"

~

~

C

iii"

ea

ii1

•

....

•

I

I

I

•

~
~

DMA TIMING
AND CONTROL

",L
~

~

co

.!..

@

~

1,/

DAR 0
BCRO

~@

-

--

PI)

~
l§!

TI

3

~

~

~
©

DCON1
SAR1
DAR 1
BCR 1

'iiiI

22J
oJ

~
~
~

@
~

inter

UPI·452

~-----------------~------,

i>sEN
ALE

EA
RST

231428-2

Figure 1. Architectural Block Diagram (Continued)

10-159

UPI-4S2

TABLE OF CONTENTS
Introduction
Table of Contents
List of Tables and Figures
Pin Description
Architectural Overview
Introduction
FIFO Buffer Interface
FIFO Programmable Features
Immediate Commands
DMA
FIFO/Slave Interface Functional Description
Overview
Input FIFO Channel
Output FIFO Channel
Immediate Commands
Host & Slave Interface Special Function Registers
Slave Interface Special Function Registers
External Host Interface Special FunctionRegisters
FIFO Module-External Host Interface .
Overview
Slave Interface Address Decodin£ .
Interrupts to the Host
DMA Requests to the Host
FIFO Module-Internal CPU Interface
Overview
Internal CPU Access to FIFO via Software Instructions
General Purpose DMA Channels
Overview
Architecture
DMA Special Function Registers
DMA Transfer Modes
External Memory DMA
Latency
DMA Interrupt Vectors
Interrupts When DMA is Active
DMA Arbitration
Interrupts
Overview
FIFO Module Interrupts to Internal CPU
Interrupt Enabling and Priority
FIFO-External Host Interface FIFO DMA Freeze Mode
Overview.
Initialization
Invoking FIFO DMA Freeze Mode During Normal Operation
. FIFO Module Special Function Register Operation During FIFO DMA Freeze Mode
Internal CPU Read & Write of the FIFO During FIFO DMA Freeze Mode
Memory Organization
Accessing External Memory
Miscellaneous Special Function Register Descriptions

10-160 .

intJ

UPI-452

LIST OF TABLES AND FIGURES
Figures:

1.
2.
3.
4.
5.
6.
7a.
7b.
8.
9.
10.
11.
12.

Tables:

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11 a.
11 b.
12.
13.

Architectural Block Diagram
UPI-452 68-Pin PGA Pinout Diagram
UPI-452 Conceptual Block Diagram
UPI-452 Functional Block Diagram
Input FIFO Channel Functional Block Diagram
Output FIFO Channel Functional Block Diagram
Handshake Mechanisms for Handling Immediate Command IN Flowchart
Handshake Mechanisms for Handling Immediate Command OUT Flowchart
DMA Transfer from: External to External Memory
DMA Transfer from: External to Internal Memory
DMA Transfer from: Internal to External Memory
DMA Transfer Waveform: Internal to Internal Memory
Disabling FIFO to Host Slave Interface Timing Diagram

Input FIFO Channel Registers
Output FIFO Channel Registers
UPI-452 Address Decoding
DMA Accessible Special Function Registers
DMA Mode Control - PCON SFR
Interrupt Priority
Interrupt Vector Addresses
Slave Bus Interface Status During FIFO DMA Freeze Mode
FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Threshold SFRs Range of Values and Number of Bytes to be Transferred
80C51 Special Function Registers
UPI-452 Additional Special Function Registers
Program Status Word (PSW)
PCON Special Function R~gister

10-161

inter

UPI-452

t

..
.... ....'"

..:

~

0..

@)

@@
@@

®

'0
Q)

~
1:
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c

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8

P4.S

P4.6

~

°...

N

...

C!

0..

0..

0..

OJ

0..

~

::l
0..

"!

"!

0..

0..

OJ

"1
OJ

0..

OJ

.,
N
0..

@ @ @ @ @

@ @ @ @ @

.

'"
... ~'"....
III

'"

.<

...N

~
@@
@@
0..

@

Pmi

EA

P4.7

XTAL1

@

@ @

PO.7

PO.6

. XTAL2

AO

@ @

@ @

PO.S

PO.4·

Al

A2

@ @

@ @

PO.3

PO.2

@

PO.l

Vss

po.o

PLO

Q)

=-E
,g
'C

·1

1~

>'E
'E~
... .0

Vss

ell

@ @

~

READ

@ @

WRITE

DRQOUT/
INTRQOUT

@ @

DRQIN/
INTRQIN

INTRQ

@) @

DB7

DBS

.!!ti
.n.

€D @@

@ @ @ @ @ @

®
® 0
® ®
0 0
®  C

€D @@

..
..'" ..'"
"1

'" '"

..;

":

..;

"!

"'!

C!

"1
0:

u

....

0..

'"
0..

0..

0:

'\(

@ @

PO.3

PO.2
PO.4
PO.6

@) @

DRQOUTj
INTRQOUT

@ @

~

READ

@ @

@ @ @ @ @ @

Pl.S

Pl.6

Pl.3

Pl.4

Pl.l

Pl.2

PO.O

PLO

PO.l

Vss

Al

A2

XTAL2

AO

@ @

@ @

po.s

P4.7

XTAL1

@ @

@ @

PO.7

P4.S

P4.6

0>"

>~

PIN NO.1
MARK

@ @

INTRQ

WiiiTE

Vss

PIN NO.1
MARK

0:'

0..

,;'

III 0

1~

Pl.6

cs @ @

DRQIN/
INTRQIN

_01

-g.8

Pl.S

®  c

c

Q)

o c

c,o

ec'
o E
1J8

@)

@@
@@
.... ..."1

..

0..

...
...

.

~

0..

@@ @ @ @
@ @ @ @ @
"1
:.;: C! ....
0..

...
0

0..

OJ

0..

..
N

N
0..

~u
u

>

.'"

N

...
N
0..

N
0..

..
N
0..

@@
@@
":

OJ
0..

...

EA

I~

..

'" ~'"'"

III

....
<

Figure 2. UPI-4S2 68-Pin PGA Pinout Diagram

10-162

@ Pmi

231428-18

inter

UPI-452

UPI MICROCONTROLLER FAMILY

Packaging

The UPI-452 joins the current members of the UPI
microcontroller family. UPl's are derivatives of the
MCSTM family of microcontrollers. Because of their
on-chip system bus interface, UPl's are designed to
be system bus "slaves", while their microcontroller
counterparts are intended as system bus "masters".

The 80C452 comes in a 68-pin PGA (Pin Grid Array)
package, while the 87C452P will be offered in a piggyback package. This piggyback package will consist of the standard 68-pin PGA package with a
2764A EPROM soldered on top. These two packages allow designers to use either on-chip EPROM
or external memory for their initial designs. The
83C452 (ROM version) will come in the standard 68pin PGA package. A complete description of
87C452P programming can be found at the end of
this data sheet.

These UPI Microcontrollers are fully supported by
Intel's EPROM programmers (iUP-201) and development tools (ICE, ASM and PLM).

UPI Family
(Slave
Configuration)

MCSFamily
(Master
Configuration)

Speed

RAM
(Bytes)

ROM
(Bytes)

EPROM
(Bytes)

80C452

80C51

12MHz

256

-

83C452

80C51

12 MHz

256

8K

-

87C452P

80C51

12 MHz

256

-

8K

80C452-1

80C51

16MHz

256

-

83C452-1

80C51

16 MHz

256

8K

-

87C452P-1

80C51

16 MHz

256

-

8K

UPI-4S2 PIN DESCRIPTIONS
Symbol

Pin #
9/43
60

Type
I
I

XTAL1

38

I

XTAL2
PortO
(ADO-AD7)
PO.O
.1
.2
.3
.4
.5
.6
PO.7

39

Vss
Vee

0
I/O

8
10
11
12
13
14
15
16

Name and Function
Circuit Ground.
+ 5V power supply during normal, idle, programming and
verification operation. It is also the standby power pin for power
down mode.
..
Input to the oscillator's high gain amplifier. A crystal or external
source can be used.
Output from the high gain amplifier.
Port 0 is an 8-bit open drain bi-directional I/O port. It is used for data
input and output during programming and verification. External
pull ups are required during program verification. Port 0 can sink
eight LS TIL inputs. It is also the multiplexed low-order address and
data local expansion bus during accesses to external memory.

10-163

inter

UPI-452

UPI-452 PIN DESCRIPTIONS (Continued)
Symbol
Port 1

Pin #

Type
1/0

Name and Function
Port 1 is an 8-bit quasi-bi-directionaII/O-port.lt is used for low-order
address byte during programming and verification. Port 1 can sink
four LS TIL inputs. The alternate functions can only be activated if
the corresponding bit latch in the port SFR contains a 1. Otherwise,
the port pin is stuck at O. Pins P1.5 and P1.6 are multiplexed with
HLD and HLDA respectively whose functions are defined as below:
Port Pin
Alternate Function
P1.5
HLD -Local bus hold
input/output signal
HLDA -Local bus hold
P1.6
acknowledge input

1/0

Port 2 is an 8-bit quasi-bi-directionaII/O port. It also emits the high- order 8 bits of address when accessing local expansion bus
external memory (or during 87C452P programming and verification) .
Port 2 can sink four LS TIL inputs .

1/0

Port 3 is an 8-bit quasi-bi-directionaII/O port. It is also multiplexed
with the interrupt, timer, local serial channel, RDI and WRI
functions that are used by various options. The alternate functions
can only be activated if the corresponding bit latch in the port SFR
contains a 1. Otherwise, the port pin is stuck at O. Port 3 can sink
four LS TIL inputs. The alternate functions assigned to the pins of
Port 3 areas follows:
Port Pin
Alternate Function
P3.0
RxD
- Serial input port
P3.1
TxD
- Serial output port
P3.2·
INTO
- Interrupt 0 Input
P3.3
INT1
- Interrupt 1 Input
P3.4
TO
- Input to counter 0
P3.5
T1
- Input to counter 1
P3.6
WRI
- The write control signal latches the
data from Port 0 outputs into the
External Data Memory on the
local bus.
RDI
- The read control signal latches the
P3.7
data from Port 0 outputs on the
local bus.

(AO-A~

(HLD, HLDA)
P1.0

.1
.2 _
,.3
.4
.5
.6
P1.7
Port 2
(AS-A15)
P2.0
.1
.2
.3
.4
.5
.6
.7
Port 3
P3.0
.1

.2
.3
.4
.5
.6
P3.7

7

.6
5
4
3
2
1
68

29
28
27
25
24
23
22
21
67
66

65
6463
62
61
59

10-164

intJ

UPI·452

UPI·452 PIN DESCRIPTIONS (Continued)
Symbol
Port 4
P4.0
.1
.2
.3

Pin #

Type
I/O

Name and Function
Port 4 is an 8-bit quasi-bi-directionall/O port. Port 4 can sink/source
four TIL inputs. It is also used as the control signals during EPROM
programming and verification drive pins as follows:
Port Pin
Alternate Function
P4.5
'1' during program and verify
P4.6
'0' during program and verify
'0' during verify - used as output enable
P4.7
'1' during programming w/ ALE = 0
Note: see Programming and Verification Characteristics in AC/DC
Specification section.

.5
.6
.7

30
31
32
33
34
35
36
37

RST

20

I

ALE/PGM

18

110

PSEN

19

0

EA

17

I

DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7

110

CS

58
57
56
55
54
53
52
51
44

I

This pin is the Chip Select of the UPI-452.

AO
A1
A2

40
41
42

I

These three address lines are used to interface with the host system.
They define the UPI-452 operations. The interface is compatible with
.
the Intel microprocessors and the MULTIBUS.

READ

46

I

WRITE

47

I

DRaiN/
INTRalN

49

0

DRaOUT/
INTRaOUT

48

0

.4

A high level on this pin for two machine cycles while the oscillator is
running resets the device. An internal pulldown resistor permits Poweron reset using only a capacitor connected to Vee.
This pin does not receive the power down voltage as is the case for
HMOS MCS-51 family members. This function has been transferred to
the Vee pin.
Provides Address Latch Enable output used for latching the address
into external memory during normal operation. Receives the program
pulse input during EPROM programming. ALE can sink/source eight LS
TIL inputs.
The Program Store Enable output is a control signal that enables the
external Program Memory to the bus during normal fetch operation.
PSEN can sink/source eight LS TIL inputs.
When held at TIL high level, the UPI-452 executes instructions from the
internal ROM/EPROM when the PC is less than 8192 (8K, 2000H).
When held at a TTL low level, the UPI-452 fetches all instructions from
external Program Memory.
Host Bus Interface is an 8-bit bi-directional bus. It is used to transfer
data and commands between the UPI-452 and the host processor. This
bus can sink/source eight LS TIL inputs.

This pin is the read strobe from the host CPU. Activating this pin causes
the UPI-452 to place the contents of the Output FIFO (either a
command or data) or the Host Status/Control Special Function Register
on the Slave Data Bus.
.This pin is the write strobe from the host. Activating this pin will cause
the value on the Slave Data Bus to be written into the register specified
by AO-A2.
This pin requests an input transfer from the host system whenever the
Input Channel requires data.
This output pin requests an output transfer whenever the Output
Channel requires service. If the external host to UPI-452 DMA is
enabled, and a Data Stream Command is at the Output FIFO, DRaOUT
is deactivated and INTRa is activated (see 'GENERAL PURPOSE DMA
CHANNELS' section).

10-165

intJ

UPI·452

UPI·452 PIN DESCRIPTIONS (Continued)
Symbol

Pin #

INTRQ

50

Type
0

DACK

45

I

VeelVpp

26

I

Name and Function
This output pin is used to interrupt the host processor when an
Immediate Command Out or an error condition is encountered. It is
also used to interrupt the host processor when the FIFO requests
service if the DMA is disabled and INTRQIN and INTRQOUT are
not used.
This pin is the DMA acknowledge for the host bus interface Input
and Output Channels. When activated, a write command will cause
the data on th~ Slave Data Bus to be written as data to the Input
Channel (to the Input FIFO). A read command will cause the Output
Channel to output data (from the Output FIFO) on to the Slave Data
Bus. This pin should be driven high (+ 5V) in systems which do not
have a DMA controller (see Address Decoding).

+ 5V power supply during operation. The Vee pin receives the
+ 12V EPROM programming and verification supply voltage.
scription of the UPI-4S2's core CPU functional
blocks including;

ARCHITECTURAL OVERVIEW

-

Introduction

Timers/Counters

-I/O Ports

The UPI-452 slave microcontroller incorporates an
80C51 with double the program and data memory, a
slave interface which allows it to be connected directly to the host system bus as a peripheral, a FIFO
buffer module, a two channel OMA processor, and a
fifth I/O port (Figure 3). The UPI-452 retains all of
the 80C51 architecture, and is fully compatible with
the MCS-51 instruction set.
The Special Function Register (SFR) interface concept introduced in the MCS-51 family of .microcontrollers has been expanded in the UPI-452. To the
20 Special Function Registers of the MCS-51, the
UPI-452 adds 34 more. These additional Special
Function Registers, like those of the MCS-5.1, provide access to the UPI-452 functional elements including the FIFO, DMA and added interrupt capabilities. Several of the 80C51 core Special Function
Registers have also been expanded to support added features of the UPI-4S2.
This data sheet describes the unique features of the
UPI-452. Refer to the 80C51 data sheet for a de-

-

Interrupt timing and control (other than FIFO and
DMA interrupts)

-

Serial Channel

=

Local Expansion Bus

-

Program/Data Memory structure

-

Power-Saving Modes of Operation •

-

CHMOS Features

-

Instruction Set

• except 87C452P piggyback package
Figure 3 contains a'conceptual block diagram of the
UPI-452. Figure 4 provides a functional block diagram.

FIFO Buffer Interface
A unique feature of the UPI-452 is the incorporation
of a 128 byte FIFO array at the host-slave interface.
The FIFO allows asynchronous bi-directional transfers between the host CPU and the internal CPU.

231428-7

Figure 3. UPI-452 Conceptual Block Diagram
10-166

UPI·452

F-.?"=:::":";

ADDITIONAL FEATURES: I
-SERIAL CHANNEL
I
-EXTERNAL INTERRUPTS I

~~~~ . :~~g{~~~~~~SION

~

BUS
-RD
-WR
-EXTERNAL
COUNTER INPUT
-EPROM PROGRAM
AND VERIFY
_ ..c~~~O_L __ • ___ _

231428-8

Figure 4. UPI-452 Functional Block Diagram
The division of the 128 bytes between Input and
Output channels is user programmable allowing
maximum flexibility. If the entire 128 byte FIFO is
allocated to the Input channel, a high performance
Host can transfer up to 128 bytes at one time, then
dedicate its resources to other functions while the
internal CPU processes the data in the FIFO. Various handshake signals allow the external Host to
operate independently and without frequent monitoring of the UPI-452 internal CPU. The FIFO Buffer
insures that the slave processor receives data in the
same order that it was sent by the host without the
need to keep track of addresses. Three slave bus
interface handshake methods are supported by the
UPI-452: DMA, Interrupt and Polled.
The FIFO is nine bits wide. The ninth bit acts as a
command/data flag. Commands written to the FIFO
by either the host or internal CPU are called Data
Stream Commands or DSCs. DSCs are written to
t~e input FIFO by the Host via a unique external
address. DSCs are written to the output FIFO by the
internal CPU via the COMMAND OUT Special Function Register (SFR). When encountered by the host
or internal CPU a Data Stream Command can be
used as an address vector to user defined service
routines, DSCs provide synchronization of data and
commands between the Host and internal CPU.

nel Boundary Pointer (CBP) SFR. This register contains the number of address locations assigned to
the Input channel. The remaining address locations
are automatically assigned to the Output FIFO. The
CBP SFR can only be programmed by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-External. Host Interface FIFO DMA Freeze Mode description). The CBP is initialized to 40H (64 bytes)
upon reset.
The number in the Channel Boundary Pointer SFR is
actually the first address location of the Output
FIFO. Writing to the CBP SFR reassigns the Input
and Output FIFO address space. Whenever the CBP
is written, the Input FIFO pointers are reset to zero
and the Output FIFO pointers are set to the value in
the CBP SFR.
All of the FIFO space may be assigned to one channel. In such a situation the other channel's data path
consists of a single SFR (FIFO IN/COMMAND IN or
FIFO OUT/COMMAND OUT SFR) location. .
CBP
Register

Size of Input/Output Channels
The 128 bytes of FIFO space can be allocated between the Input and Output channels via the Chan10-167

Output FIFO
Size

3
4

1
1
2
3
4

128
128
126
125
124

7B
7C
7D
7E
7F

123
124
125
128
128

5
4
3
1
1

0
1

2

•

FIFO PROGRAMMABLE FEATURES

InputF.IFO
Size

•

•

UPI-452

FIFO Read/Write Pointers
These normally operate in auto-increment (and autorollover) mode, but can be reassigned by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-External Host Interface FIFO DMA Freeze Mode de.
scription).

Threshold Register
The Input FIFO Threshold SFR contains the number
of empty bytes that must be available in the Input
FIFO to generate a Host interrupt. The Output FIFO
Threshold SFR' contains the number of bytes, data
and/or DSC(s), that must be in the FIFO before an
interrupt is generated. The Threshold feature prevents the Host from being interrupted each time the
FIFO needs to load or unload one byte of data. The
thresholds, therefore, allow the FIFO's operation to
be adjusted to the speed of the Host, optimizing the
overall interface performance.

of the three·writeable memory spaces: Internal Data
Memory, External Load Expansion Bus Data Memory and the Special Function Register array. The Special Function Register array appears as a set of
unique dedicated memory addresses which may be
used as either the source or destination address of a
DMA transfer. Each DMA channel is independently
programmable via dedicated Special Function Registers for mode, source and destination addresses,
and byte count to be transferred. Each DMA channel
has four programmable modes:
.
-

Alternate Cycle Mode

--, Burst Mode
-

FIFO or Serial Channel Demand Mode

-

External Demand Mode

A complete description of each mode and DMA operation m~y be found in the section titled "General
Purpose DMA Channels".

FIFO/SLAVE INTERFACE
FUNCTIONAL DESCRIPTION

Immediate Commands
The UPI-452 provides, in addition to data and DSCs,
a third direct means of communication between the
external Host and internal CPU called Immediate
C-ommends. As the name implies, an !mmediate.
Command is available to the receiving'CPU immediately, via an interrupt, without being entered into the
FIFO as are Data Stream Commands. Like Data
Stream Commands, Immediate Commands are written either via a unique external address by the host
CPU, or via dedicated SFR by the internal CPU.
The DSC and/or Immediate Command interface
may be defined as either Interrupt or Polled under
user program control via the Interrupt Enable (IE),
Slave Control Register (SLCON), and, Interrupt Enable Priority (IEP) Special Function Registers, for the
internal CPU and via the Host Control SFR for the.
external Host CPU.

DMA
The UPI-452 contains a two channel internal DMA
controller which allows transfer of data between any

Overview
The FIFO is a 128 Bvte RAM arrav with recirculatina
pointers to manage- the read and write accesseS.
The FIFO consists of an Input and an Output channel. Access cycles to the FIFO by the internal CPU
and external Host are interleaved and appear to be
occurring concurrently to both the internal CPU and
external Host. Interleaving access cycles ensures
efficient use of this shared resource. The internal
CPU accesses the FIFO in the same way it would
access any of the Special Function Registers e.g.,
direct and register indirect addressing as well as arithmetric and logical instructions.

Input FIFO Channel
The. Input FIFO Channel provides for data transfer
from the external Host to the internal CPU (Figure 5).
The registers associated with the Input Channel during normal operation are listed in Table 1*.

Table 1. Input FIFO Channel Registers'

1)
2)
3)
4)
.5)
6)

Register Name

Description

Input Buffer Latch
FIFO IN SFR
COMMAND IN SFR
Input FIFO Read Pointer SFR
Input FIFO Write Pointer SFR
Input FIFO Threshold SFR

Host CPU Write only
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only

..

..

'See "'FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE" section for FIFO DMA Freeze Mode SFR charactenstlcs deSCription .

10-168

inter

UPI-4S2

EXTERNAL HOST
CPU
EXTERNAL
ADDRESS

HOST DATA
BUS

INPUT WRITE
POINTER (IWPR)
!::
ID

THRESHOLD SFR
(ITHR)

INPUT FIFO

i!:

'"
z

INPUT READ
POINTER (IRPR)

231428-9

Figure 5. Input FIFO Channel Functional Block Diagram

The host CPU writes data and Data Stream Com·
mands into the Input Buffer Latch on the rising edge
of the external WR signal. External addressing de·
termines whether the byte is a data byte or Data
Stream Command and the FIFO logic sets the ninth
bit of the FIFO accordingly as the byte is moved
from the Input Buffer Latch into the FIFO. A "1" in
the ninth bit indicates that the incoming byte is a
Data Stream Command. The internal CPU reads
data bytes via the FIFO IN SFR, and Data Stream
Commands via the COMMAND IN SFR.
A Data Stream Command will generate an interrupt
to the internal CPU prior to being read and after
completion of the previous operation. The DSC can
then be read via the COMMAND IN SFR. Data can
only be read via the FIFO IN SFR and Data Stream
Commands via the COMMAND IN SFR. Attempting
to read Data Stream Commands as data by address·
ing the FIFO IN SFR will result in '~OFFH" being
read, and -the Input FIFO Read Pointer will remain
intact. (This prevents accidental misreadin,9 of Data
Stream Commands.) Attempting to read data as
Data Stream Commands will have the same conse·
quence.

The Inl'lut FIFO Channel addressing is controlled by
the Input FIFO Read and Write Pointer SFRs. These
SFRs are read only registers during normal opera·
tion. However, during FIFO DMA Freeze Mode (See
FIFO·External Host Interface FIFO DMA Freeze
Mode description),. the internal CPU has write access to them. Any write to these registers in normal
mode will have no effect. The Input Write Pointer
SFR contains the address location to which datal
commands are written from the Input Buffer Latch.
The write pointer is automatically incremented after
each write and is reset to zero if equal to the CBP,
as the- Input FIFO operates as a circular buffer.
If a write is performed on an empty FIFO, the first
byte is also written into the FIFO IN or COMMAND
IN SFR. If the Host continues writing while the Input
FIFO is full, an external interrupt, if enabled, is sent
to the host to Signal the overrun condition. The
writes are ignored by the FIFO control logic. Similar·
Iy, an internal CPU read of an empty FIFO will cause
an underrun error interrupt to be generated to the
internal CPU and a value of "OFFH" will be read by
the internal CPU.

10·169

UPI-452

The Read Pointer SFR holds the address of the next
byte to be read from the Input FIFO. An Input FIFO
read operation post-increments the Input Read
Pointer SFR and loads a new data byte into the
FIFO IN SFR or a Data Stream Command into the
COMMAND IN SFR at the end of the read cycle.
An Input FIFO Request for Service (via DMA, Interrupt or a flag) is generated to the Host whenever
more data can be written into the Input FIFO. For
efficient utilization of the Host, a "threshold" value
can be programmed into the Input FIFO Threshold
SFR. The range of values of the Input FIFO Threshold SFR can be from 0 to (CBP-2). The Request for
Service Interrupt is generated only after the Input
FIFO has room to accommodate a threshold number
of bytes or more. The threshold is equal to the total'

number of bytes assigned to the Input FIFO (CBP)
minus the number of bytes programmed in the Input
FIFO Threshold SFR. With this feature the Host is
assured that it can write at least a threshold number
of bytes to the Input FIFO channel without worrying
about an overrun condition. Once the Request for
Service is generated it remains active until the Input
FIFO becomes full.

Output FIFO Channel
The Output FIFO Channel provides data transfer
from the UPI-452 internal CPU to the external Host
(Figure 6).
The registers associated with the Output Channel
during normal operation are listed in Table 2*.

231428-10

Figure 6. Output FIFO Channel Functional Block Diagram
Table 2. Output FIFO Channel Registers

1)

2)
3)

4)
5)
6)

Register Name

Description

Output Buffer Latch
FIFO OUT SFR
COMMAND OUT SFR
Output FIFO Read Pointer SFR
Output FIFO Write Pointer SFR
Output FIFO Threshold SFR

Host CPU Read only
Internal CPU Read and Write
Internal CPU Read and Write
Internal CPU Read only
Internal CPU Read only
Internal CPU Read only

'See "'FIFO·EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE"' section for FIFO DMA Freeze Mode register characteristics description.

10-170

inter

UPI-4S2

The UPI-452 internal CPU transfers data to the Output FIFO via the FIFO OUT SFR and commands via
the COMMAND OUT SFR. If the byte is written to
the COMMAND OUT SFR, the ninth bit is automatically set (= 1) to indicate a Data Stream Command.
If the byte is written to the FIFO OUT SFR the ninth
bit is cleared (=0). Thus the FIFO OUT and COMMAND OUT SFRs are the same but the address determines whether the byte entered in the FIFO is a
DSC or data byte.
The Output FIFO preloads a byte into the Output
Buffer Latch. When the Host issues a RD/ signal,
the data is immediately read from the Output Buffer
Latch. The next data byte is then loaded into the
Output Buffer Latch, a flag is set and an interrupt, if
enabled, is generated if the byte is a DSC (ninth bit
is set). The operation is carefully timed such that an
interrupt can be generated in time for it to be recognized by the Host before its next read instruction.
Internal CPU write and external Host read operations are interleaved at the FIFO so that they appear
to be occurring concurrently.
The Output FIFO read and write pointer operation is
the same as for the Input Channel. Writing to the
FIFO OUT or COMMAND OUT SFRs will increment
the Output Write Pointer SFR but reading from it will
leave the write pointer unchanged. A rollover of the
Output FIFO Write Pointer causes the pointer to be
reset to the value in the Channel Boundary Pointer
(CBP) SFR.
.
If the external host attempts to read a Data Stream
Command as a data byte it will result ,in invalid data
(OFFH) being read. The DSC is not lost because the
invalid read does not increment the pointer. Similarly
attempting to read a data byte as a Data Stream
Command has the same result.
A Request for Service is generated to the external
Host under the following two conditions:
1.) Whenever the internal CPU has written a threshold number of bytes or more intothe Output FIFO
(threshold = (OTHR) + 1). The threshold number should be chosen such that the bus latency
time for the external Host does not result in a
FIFO overrun error condition on the internal CPU
side. The threshold limit should be large enough
to make a bus request by the UPI-452 to the external host CPU worthwhile. Once a request for
service is generated, the request remains active
until the Output FIFO becomes empty. The range
of values of the FIFO Output Threshold (OTHR)
SFR is from 1 to the Output FIFO Size. The
threshold number can be programmed via the
OTHR SFR.

2.) The second type of Request for Service is called
"Flush Mode" and occurs when the internal CPU
writes a Data Stream Command into the Output
FIFO. Its purpose is to ensure that a data block
entered into the Output FIFO, which is less than
the programmed threshold, will generate a Request for Service interrupt, if enabled, and be
read, or "Flushed" from the Output FIFO, by the
external host CPU regardless of the status of the
OTHR SFR.

Immediate Commands
Immediate Commands provide direct communication between the external Host and UPI-452. Unlike
Data Strearri Commands which are entered into the
FIFO, the Immediate Command is available to the
receiving CPU directly, bypassing the FIFO. The Immediate Command can serve as a program vector
pOinting into a jump table in the recipients software.
Immediate Command Interrupts are generated, if enabled, and a bit in the appropriate Status Register is
set when an Immediate Command is input or output.
A similar bit is provided to acknowledge when an
Immediate Command has been read and whether
the register is available to receive another command. The bits are reset when the Immediate Commands are read. Two Special Function Registers are
dedicated to the Immediate Command interface. External addressing determines whether the Host is
accessing the Input FIFO or the Immediate Command IN (IMIN) SFR. The internal CPU writes Immediate Commands to the Immediate Command OUT
(IMOUT) SFR.
Both processors have the ability to enable or disable
Immediate Command Interrupts. By disabling the interrupt, the recipient of the Immediate Command
can poll the status SFR and read the Immediate
Command at its convenience. Immediate Commands should only be written when the appropriate
Immediate Command SFR is empty (as indicated in
the appropriate status SFR:HSTAT/SSTAT). Similarly, the Immediate Command SFR should only be
read when there is data in the Register.
The flowcharts in Figure 7a and 7b illustrate the
proper handshake mechanisms between the external Host and internal CPU when handling Immediate
Commands.

10-171

infef

UPI-4S2

r----------------

SET

SET

a

\:V
,

....

.oil
GENERATES INTERRUPT
TO INTE.RNAL CPU

GENERATES
INTERRUrT TO HOST

,

,

,,

)

)

• 4

SET

SET

a

\:V
,

,

.oil

.oil

GENERATES
INTERRUPT TO HOST

GENERATES INTERRUPT
TO INTE.RNAL CPU

,,

,,

-----------------~

231428-11

Figure 7a. Handshake Mechanisms for Handling
Immediate Command IN Flowchart

...

_----231428-12

Figure 7b. Handshake Mechanisms for Handling
Immediate Command OUT Flowchart

10-172

inter

UPI-4S2

HOST & SLAVE INTERFACE SPECIAL FUNCTION REGISTERS
Slave Interface Special Function Registers
The Internal CPU interfaces with the FIFO slave module via the following registers:
1) Mode Special Function Register (MODE)
2) Slave Control Special Function Register (SLCON)
3) Slave Status Special Function Register (SSTAT)
Each register resides in the SFR Array and is accessible via all direct addressing modes except bit. Only the
Slave Control Register (SLCON) is bit addressable.

1) MODE Special Function Register (MODE)
The MODE SFR provides the primary control of the external host-FIFO interface. It is included in the SFR
Array so that the internal CPU can configure the external host-FIFO interface should the user decide that the
UPI-452 slave initialize itself independent of the external host CPU.
The MODE SFR can be directly modified by the internal CPU through direct address instructions. It can also be
indirectly modified by the external host CPU by setting up a MODE SFR service routine in the UPI-452 program
memory and having the host issue a Command, either Immediate or DSC, to vector to that routine.

Symbolic
Address

Physical
Address

MODE

MD6

MD5

OF9H

MD4

(MSB)
Status On Reset:

1"

o

(LSB)

o

o

1*

1"

MD7

(reserved)"'

MD6

Request for Service to external CPU via;
1 = DMA (DRQIN/DRQOUT) request to external host when the Input or Output FIFO channel requests service

o

MD5

= Interrupt (INTRQIN/INTRQOUT or INTRQ) to external host when the Input or Output FIFO
channel requests service or a DSC is encountered in the I/O Buffer Latch
Configure DRQIN/INTRQIN and DRQOUT/INTRQOUT to be either;
1 = Enable (Actively driven)

o=
MD4

Disable (Tri-state)

Configure INTRQ to be either;
1

= Enable (Actively driven)

o=

Disable (Tri-state)

MD3

(reserved)' *

MD2

(reserved)"

MD1

(reserved)"

MDO

(reserved)"

2) Slave Control SFR (SLCON)
The Slave Control SFR is used to configure the FIFO-internal CPU interface. All interrupts are to the internal
CPU.

10-173

inter

UPI-452

Symbolic
Address
SLCON

IFI

OFI

ICII

I'

Physical
Address
ICOI

FRZ

IFRS

o
IFI

OFI

ICII

ICOI

FRZ

SC2
IFRS

OFRS

o

·OFRS

OE8H

(LSB)

(MSB)
Status On Reset:

o

o

o

1"

o

o

Enable Input FIFO Interrupt (due to Underrun Error Condition, Data Stream Command or Request
Service)
1 = Enable
0= Disable
Enable Output FIFO Interrupt (due to Overrun Error Condition or Request Service)
1 = Enable
0= Disable
Note: If the DMA ill configured to service a FIFO demand, then the Request for Service Interrupt is
not generated.
Generate Interrupt when a command is written to the Immediate Command in Register
1 = Enable
0= Disable
Generate Interrupt when Immediate Command Out Register is Available
1 = Enable
0= Disable
Enable FIFO DMA Freeze Mode
1 = Normal operation
o = FIFO DMA Freeze Mode
(reserved) ••
Input FIFO Channel Request for Service
1, = Request when Input FIFO not empty
o = Request when Input FIFO full
Output FIFO Channel Request for Service
1 = Request when Output FIFO not full
o = Channel Request when Output FIFO empty
NOTES:

°A '1' will be read from all SFR reserved locations except HCON SFR,HCO and HC2.
"'reserved'-these locations are reserved for future use by Intel Corporation.

3) Slave Status SFR (SSTAT)
The bits in the Slave Status SFR reflect the status of the FIFO-internal CPU interface. It can be read during an
internal interrupt service routine to determine the nature of the interrupt or read during a polling sequence to
determine a course of action.

Symbolic
Address

Physical
Address

, SSTAT

OE9H

o

o

o

(MSB)

(LSB)

10-174

inter
SST7

UPI-452

Output FIFO Overrun Error Condition
1 = No Error

o=
SSTS

Error (latched until Slave Status SFR is read)
Immediate Command Out Register Status
1 = Full (Le. Host CPU has not read previous Immediate Command Out sent by internal CPU)

0= Available
SST5

FIFO DMA Freeze Mode Status
1 = Normal Operation
FIFO DMA Freeze Mode in Progress

o=
SST4

Output FIFO Request for Service Flag
1 = Output FIFO does not request service
Output FIFO requests service

o=
SST3

Input FIFO Underrun Error Condition Flag
1 = No Underrun Error

o=
SST2

Underrun Error (latched until Slave Status SFR is read)

Immediate Command In SFR Status
1 = Empty
Immediate Command received from host CPU

o=
SST1

Data Stream Command/Data at Input FIFO Flag
1 = Data (not DSC)

o=
SSTO

DSC (at COMMAND IN SFR)

Input FIFO Request For Service Flag
1 = Input FIFO Does Not Request Service

o=

Input FIFO Request for Service

EXTERNAL HOST INTERFACE SPECIAL FUNCTION REGISTERS
The external host CPU has direct access to the following SFRs:
1) Host Control Special Function Register
2) Host Status Special Function Register
It can also access other SFRs by commanding the internal CPU to change them accordingly via Data Stream
Commands or Immediate Commands. The protocol for implementing this is entirely determined by the user.

1) Host Control SFR (HCON)
By writing to the Host Control SFR, the host can enable or disable FIFO interrupts and DMA requests and can
reset the UPI-452.
Symbolic
Address

HCON

Physical
Address

HC7

HCS

HC5

HC4

HC3

HC1

(MSB)
Status On Reset:
0

0

OE7H
(LSB)

0

0

10-175

0

O'

0

O'

intJ
HC7

HC6

HCS

HC4

HC3

HC2
HC1

UPI-452

Enabie Output FIFO Interrupt due to Underrun Error Condition, Data Stream Command or Service
Request
1 = Enable
0= Disable
Enable Input FIFO Interrupt due to Overrun Error Condition, or Service Request
1 = Enable
0= Disable
Enable the generation of the Interrupt due to Immediate Command Out being present
1 = Enable
0= Disable
Enable the Interrupt due to the Immediate Command In Register being Available for a new Immediate
Command byte
1 = Enable
o = Disable
Reset UPI-4S2
1 = Software RESET
o = Normal Operation
(reserved)"
Select between INTRQ and INTRQINIINTRQOUT as Request for.5ervice interrupt signal when DMA is
disabled
.
1 = INTRQ
INTRQIN or INTRQOUT
(reserved)"

o=
HCO

. NOTES:
'A '1' will be read from all SFR reserved locations except HCON SFR, HCO and HC2.
"'reserved'-these locations are reserved for future use by Intel Corporation.

2) Host Status SFR (HSTAT)
The Host Status SFR provides information on the FIFO-Host Interface and can be used to determine the
source of an external interrupt during polling. Like the Slave Status SFR, the Host Status SFR reflects the
current status of the FIFO-external host interface.
..
Symbolic

Physical

Address

Address

HSTAT

OE6H
Output FIFO Status -+
Status On Reset:
1/0'
(MSB)

(LSB)

10-176

infef

UPI-4S2

HST7 Output FIFO Underrun Error Condition
1 = No Underrun Error
o = Underrun Error (latched until Host
Status Register is read)
HST6 Immediate Command Out SFR Status
1 = Empty
o = Immediate Command Present
HST5 Data Stream Command/Data at Output
FIFO Status
1 = Data (not DSC)
o = DSC (present at Output FIFO COMMAND OUT SFR)
(Note: Only if HST4 = 0, if HST4 = 1 then undetermined)
HST4 Output FIFO Request for Service Status
1 = No Request for Service
o = Output FIFO Request for Service due to:
a. Output FIFO containing the threshold
number of bytes or more
b. Internal CPU sending a block of data terminated by a DSC (DSC Flush Mode)
HST3 Input FIFO Overrun Error Condition
1 = No Overrun Error
o = Overrun Error (latched until Host Status
Register is read)
HST2 Immediate Command In SFR Status
1 = Full (i.e. Internal CPU has not read previous Immediate Command sent by Host)
o = Empty

* Reset value;
'1' - if read by the external Host
'0' - if read by internal CPU (reads shadow
latch - see FIFO DMA Freeze Mode description)
HST1 FIFO DMA Freeze Mode Status
1 = Freeze Mode in progress.
(In Freeze Mode, the bits of the Host Status
SFR are forced to a '1' initially to prevent the
external Host from attempting to access the
FIFO. The definition of the Host Status SFR
bits during FIFO DMA Freeze Mode can be
found in FIFO DMA Freeze Mode description)
o = Normal Operation
HSTO Input FIFO Request Service Status
1 = Input FIFO does not request service
o = Input FIFO request service due to the
Input FIFO containing enough space for the
host to write the threshold number of bytes
or more

FIFO MODULE - EXTERNAL HOST
INTERFACE
Overview
The FIFO-external Host interface supports high
speed asynchronous bi-directional 8-bit data transfers. The host interface is fully compatible with Intel
microprocessor local busses and with MULTIBUS.
The FIFO has two specialized DMA request pins for
Input and Output FIFO channel DMA requests.
These are multiplexed to provide a dedicated Request for Service interrupt (DRQINIINTRQIN,
DRQOUT /INTRQOUT).
The external Host can program, under user defined
protocol, thresholds into the FIFO Input and Output
Threshold SFRs which determine when the FIFO
Request for Service interrupt is generated to the
Host CPU. The FIFO module external Host interface
is configured by the internal CPU via the MODE
SFR. "The external Host can enable and disable
Host interface interrupts via the Host Control SFR."
Data Stream Commands in the Input FIFO channel
allow the Host to influence the processing of data
blocks and are sent with the data flow to maintain
synchronization. Data Stream Commands in the
Output FIFO Channel allow the internal CPU to perform the same function, and also to set the Output
FIFO Request Service status logic to the host CPU
regardless of the programmed value in the Threshold SFR.

Slave Interface Address Decoding
The UPI-452 determines the desired Host function
through address decoding. The lower three bits of
the address as well as the READ, WRITE, Chip Select (CS) and DMA Acknowledge (DACK) are used
for decoding. Table 3 shows the pin states and the
Read or Write operations associated with each configuration.

Interrupts to the Host
The UPI-452 interrupts the external Host via the
INTRQ pin. In addition, the DRQIN and DRQOUT
pins can be multiplexed as interrupt request lines,
INTRQIN and INTRQOUT respectively, when DMA
is disabled. This provides two special FIFO "Request for Service" interrupts.
There are eight FIFO-related interrupt sources; two
from The Input FIFO; three from The Output FIFO;
one from the Immediate Command Out SFR; one
from the Immediate Command IN SFR; and one due
to FIFO DMA Freeze Mode.
INPUT FIFO: The Input FIFO interrupt is generated
whenever:
a. The Input FIFO contains space for a threshold
number of bytes.

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intJ

UPI·452

Table 3. UPI·452 Address Decoding
DACK CS A2 A1 AD

Write

Read

1

1

X

X

X No Operation

No Operation

1

0

0

0

0

Data or DMA from Output FIFO Channel

Data or DMA to Input FIFO Channel

1

0

0

0

1

Data Stream Command from Output FIFO Channel Data Stream Command to Input FIFO Channel

1

0

0

1

0

Host Status SFR Read

Reserved

1

0

0

1

1

Host Control SFR Read

Host Control SFR Write

1

0

1

0

0

Immediate Command SFR Read

Immediate Command to SFR Write

1

0

1

1

X Reserved

0

X

X

X

X DMA Data from Output FIFO Channel

DMA Data to Input FIFO Channel

1

0

1

0

1

Reserved

Reserved

Reserved

NOTES:
1. Attempting to read a DSC as a data byte will result in invalid data being read. The read pointers are not incremented so
that the DSC is not lost. Attempting to read a data byte as a DSC has the same result.
2. If DACK is active the UPI-452 will attempt a DMA operation when RD or WR becomes active regardless of the DMA
enable bit (MD6) in the MODE SFR. Care should be taken when using DACK. For proper operation, DACK must be driven
high (+5V) when not using DMA.

b. When an Input FIFO overrun error condition exists. The appropriate bits in the Host Status SFR
are set and the interrupt is generated only if enabled.
OUTPUT FIFO: The Output FIFO Request for S'ervjt"'o Intorr'l""t

..... ..., I I . "...... U .......

,,"t"\,...,+,...,..
...,t'vl~U.Q~

in ... ,..i ...... il,.. ........ _""" ......... _ ...

III CI .:Jlllllial

IllClr II 10'

Qo:t

+UIG
........

I_

111-

put FIFO interrupt:
a. When the FIFO contains the threshold number of
bytes or more.
b. Output FIFO error condition interrupts are generated when the Output FIFO is underrun.
c. Data Stream Command present in the Output
Buffer Latch.
'
A Data Stream Command interrupt is used to halt
normal processing, using the command as a vector
to a service routine. When DMA is disabled, the user
may program (through HC1) INTRa to include FIFO
Request for Service Interrupts or use INTRalN and
INTRaOUT as Request for Service Interrupts.'
,
IMMEDIATE COMMAND INTERRUPTS:
a. An Immediate Command Out Interrupt is generated, if enabled, to the Host and the corresponding
Host Status SFR bit (HSTAT HST6) is cleared,
when the internal CPU writes to the Immediate
Command OUT (IMOUT) SFR. When the Host
reads the Immediate Command OUT (IMOUT)
SFR the corresponding" bit in the Host Status
(HSTAT) SFR is set. This causes the Slav,e Status
Immediate Command OUT Status bit (SSTAT
SST6) to be cleared indicating that the Immediate
Command OUT (IMOUT) SFR is empty. If enabled, a FIFO-Slave Interface will also begenerated to the internal CPU. (See Figure 7b, Immediate Command OUT Flowchart.)

b. An Immediate Command IN interrupt is generated, if enabled, to the Host when the internal CPU
has read a byte from the Immediate Command IN
(IMIN) SFR. The read operation clears the Host
Status SFR Immediate Command IN Status bit
(HSTAT HST2) indicating that the' Immediate
Comrnand iN SFR is empty. The corresponding
Slave Status (SSTAT) SFR bit is also set to indicate an empty status. Setting the Slave Status
SFR bit generates a FIFO-Slave Interface interrupt, if enabled, to the internal CPU. (See Figure
7a, Immediate Command IN Flowchart.)
NOTE:
Immediate Command IN and OUT interrupts are actually specific Request For Service interrupts to the
Host.
FIFO DMA FREEZE MODE: When the internal CPU
invokes FIFO DMA Freeze Mode, for example at reset or to reconfigure the FIFO interface, INTRa is
activated. The INTRa can only be deactivated by
the external Host reading the Host Status SFR
(HST1 remains active until FIFO DMA Freeze Mode
is disabled by the internal CPU).
Once an interrupt is generated, INTRa will remain
high until no interrupt generating condition exists.
For a FIFO underrun/overrun error interrupt, the interrupt condition is deactivated by the external Host
reading the Host Status SFR. An interrupt is serviced by reading the Host Status SFR to determine
the source of the interrupt and vectoring the appropriate service routine.

10-178

UPI-4S2

DMA Requests to the Host
The UPI-452 generates two DMA requests, DRQIN
and DRQOUT, to facilitate data transfer between the
Host and the Input and Output FIFO channels. A
DMA acknowledge, DACK, is used as a chip select
and initiates a data transfer. The external READ and
WRITE signals select the Input and Output FIFO respectively. The CS and address lines can also be
used as a DMA acknowledge for processors with
onboard DMA controllers which do not generate a
DACK signal.
The internal CPU can configure the UPI-452 to request service from the external host via DMA or interrupts by programming Mode SFR MD6 bit. In addition the external Host enables DMA requests
through bits 6 and 7 of the Host Control SFR. When
a DMA request is invoked the number of bytes transferred to the Input FIFO is the total number of bytes
in the Input FIFO (as determined by the CBP SFR)
minus the value programmed in the Input FIFO
Threshold SFR. The DMA request line is activated
only when the Input FIFO has a threshold number of
bytes that can be transferred.

nation via the DMAO/DMA 1 Source Address or Destination Address Special Function Registers. The
FIFO module manages the transfer of data between
the external host and FIFO SFRs.

Internal CPU Access to FIFO Via
Software Instructions
The internal CPU has access to the Input and Output FIFOs via the FIFO IN/COMMAND IN and FIFO
OUT/COMMAND OUT SFRs which reside in the
Special Function Register Array. At the end of every
instruction that involves a read of the FIFO IN/COMMAND IN SFR, the SFR is written over by a new
byte from the Input FIFO channel when available. At
the end of every instruction that involves a write to
the FIFO OUT/COMMAND OUT SFR, the new byte
is written into the Output FIFO channel and the write
pointer is incremented after the write operation (post
incremented).
The internal CPU reads the Input FIFO by using the
FIFO IN/COMMAND IN SFR as the source register
in an instruction. Those instructions which read the
Input FIFO are listed below:

The Output FIFO DMA request is activated when a
DSC is written by the internal CPU at the end of a
less than threshold size block of data (Flush Mode)
or when the Output FIFO threshold is reached. The
request remains active until the Input FIFO becomes
full or the Output FIFO becomes empty. If a DSC is
encountered during an Output FIFO DMA transfer,
the DMA request is dropped until the DSC is read.
The DMA request will be reactivated after the DSC is
read and remains active until the Output FIFO becomes empty or another DSC is encountered.

ADD A,FIFO IN/COMMAND IN
AD DC A,FIFO IN/COMMAND IN
PUSH FIFO IN/COMMAND IN
ANL A,FIFO IN/COMMAND IN
ORL A,FIFO IN/COMMAND IN
XRL A,FIFO IN/COMMAND IN
CJNE A,FIFO IN/COMMAND IN, rei
SUBB A,FIFO IN/COMMAND IN
MOV direct,FIFO IN/COMMAND IN
MOV @Ri,FIFO IN/COMMAND IN
MOV Rn,FIFO IN/COMMAND IN
MOV A,FIFO IN/COMMAND IN

FIFO MODULE - INTERNAL CPU
INTERFACE

After each access to these registers, they are overwritten by a new byte from the FIFO.

Overview
The Input and Output FIFOs are accessed by the
internal CPU through direct addressing of the FIFO
IN/COMMAND IN and FIFO OUT/COMMAND OUT
Special Function Registers. All of the 80C51 instructions involving direct addressing may be used to access the FIFO's SFRs. The FIFO IN, COMMAND IN
and Immediate Command In SFRs are actually read
only registers, and their Output counterparts are
write only. Internal DMA transfers data between Internal memory, External Memory and the Special
Function Registers. The Special Function Registers
appear as another group of dedicated memory addresses and are programmed as the source or desti-

NOTE:

Instructions which use the FIFO IN or COMMAND
IN SFR as both a source and destination register
will have the data destroyed as the next data byte
is rewritten into the FIFO IN register at the end of
the instruction. These instructions are not supported by the UPI-452 FIFO. Data can only be read
through the FIFO IN SFR and DSCs through the
COMMAND IN SFR. Data read through the COMMAND IN SFR will be read as OFFH, and DSCs
read through the FIFO IN SFR will be read as
OFFH. The Immediate Command in SFR is read
with the same instructions as the FIFO IN and
COMMAND IN SFRs.

10-179

inter

UPI-4S2

The FIFO IN, COMMAND IN and Immediate Command In SFRs are read only registers. Any write operation performed on these registers will be ignored
and the FIFO pOinters will remain intact.

dress Register (DAR). (Note: Since the FIFO IN SFR
is a read only register, the DMA transfer will be ignored if it is used asa DMA DAR. This is also true if
the FIFO OUT SFR is used as a DMA SAR.)

The internal CPU uses the FIFO OUT SFR to write
to the Output FIFO and any instruction which uses
the FIFO OUT or COMMAND OUT SFR as a destination will invoke a FIFO write. DSCs are differentiated from data by writing to the COMMAND OUT
SFR. In the FIFO, Data Stream Commands have the
ninth bit assoCiated with the command byte set to
"1". The instructions used to write to the Output
FIFO are listed below:

Each DMA channel is software programmable to operate in either Block Mode or Demand Mode. In the
Block Mode, DMA transfers can be further .programmed to take place in Burst Mode or Alternate
Cycle mode. In Burst Mode, the processor halts its
execution and dedicates its resources to the DMA
transfer. In Alternate Cycle Mode, DMA cycles and
instruction cycles occur alternately.

MOV
MOV
. MOV
POP
MOV
MOV

FIFO
FIFO
FIFO
FIFO
FIFO
FIFO

OUT /COMMOUt, A
OUT/COMMOUT, direct
OUT /COMMOUT, Rn
OUT /COMMOUT
OUT/COMMOUT, #data
OUT/COMMOUNT, @Ri

NOTE:
Instructions which use the FIFO OUT/COMMAND
OUT SFRs as both a source and destination register cause invalid data to be written into the Output
'FIFO. These instructions are not supported by the
UPI-4S2 FIFO.

In Demand Mode, a DMA transfer occurs only when
it is demanded. Demands can be accepted from an
external device (through External Interrupt pins,
EXTO/EXT1) or from either the Serial Channel or
FIFO flags. In this way, a DMA transfer can be synchronized to an external device, the FIFO or the Serial Port. If the External Interrupt is configured in
Edge Mode, a single byte transfer occurs per transition. The external interrupt itself will occur if enabled. If the External Interrupt is configured in Level
Mode, DMA transfers continue until the External Interrupt request goes inactive or the byte count becomes zero. The following flags activate Demand
Mode transfers of one byte to/from the FIFO or Serial Channel:
RI - Serial Channel Receiver Buffer Full
TI - Serial Channel Transm!tter Buffer Empty

GENERAL PURPOSE DMA CHANNELS
Overview

Architecture

There are two identical General Purpose DMA Channels on the UPI-4S2 which allow high speed data
transfer from one writeable memory space to another. As many as 64K bytes can be transferred in a
single DMA operation. The following memory
spaces can be used with DMA channels:

There are three 16 bit and one 8 bit Special Function
Registers associated with each DMA channel.

• Internal Data Memory

• The 16 bit Source Address SFR (SAR) points to
the source byte.
• The 16 bit Destination Address SFR (DAR) points
to the destination.
• The 16 bit Byte Count SFR (BCR) contains the
number of bytes to be transferred and is decremented when a byte transfer is accomplished.

• External Data Memory
• Special Function Registers
The Special Function Register array appears as a
limited group of dedicated memory addresses. The
Special Function Registers may be used in DMA
transfer operations by specifying the SFR as the
sourCe or destination address. The Special Function
Registers which may be used in DMA transfers are
listed in Table 4. Table 4 also shows whether the
SFR may be used as Source or Destination only, or
.
.
both.
The FIFO can be accessed during DMA by using the
FIFO IN SFR as the DMA Source Address Register
(SAR) or the FIFO OUT SFR as the Destination Ad-

• The DMA Control SFR (DCON) is eight bits wide
and specifies the source memory space, destination memory space and the mode of operation.
In Auto Increment mode, the Source Address and/
or Destination Address is incremented when a byte
is transferred. When a DMA transfer is complete
(BCR = 0), the DONE bit is set and a maskable
interrupt is generated. The GO· bit must be set to
start any DMA transfer (also, the Slave Control SFR
FRZ bit must be set to disable FIFO DMA Freeze
Mode). The two DMA channels are deSignated as
DMAO and DMA 1, and their corresponding registers
are suffixed by 0 or 1; e.g. SARO, DAR 1, etc.

10-1BO

UPI-4S2

Table 4 DMA Accessible Special Function Registers
SFR

Symbol

Address

Accumulator
B Register
FIFO IN
COMMAND IN
FIFO OUT
COMMAND OUT
Serial Data Buffer
PortO
Port 1
Port 2
Port 3
Port 4

AlACC
B
FIN
CIN
FOUT
COUT
SBUF
PO
P1
P2
P3
P4

OEOH
OFOH
OEEH
OEFH
OFEH
OFFH
099H
080H
090H
OAOH
OBOH
OCOH

Source
Only

Destination
Only

Either

Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y

DMA Special Function Registers
DMA Control SFR: DCONO, DCON1
Symbolic
Address

Physical
Address

DCONO

092H

DCON1

093H
Reset Status: DCONO and DCON1 = OOH

Bit Definition:

DAS

IDA

0
0
1
1

0
1
0
1

SAS

ISA

0
0
1
1

0
1
0
1

DM

TM

0
0
1
1

0
1
0
1

Destination Address Space
External Data Memory without Auto-Increment
External Data Memory with Auto-Increment
Special Function Register
Internal Data Memory

Source Address Space
External Data Memory without Auto-Increment
External Data Memory with Auto-Increment
Special Function Register
Internal Data Memory

DMA Transfer Mode
Alten1ate-Cycle Transfer Mode
Burst Transfer Mode
FIFO or Serial Channel Demand Mode
External Demand Mode

10-181

intJ
DONE

UPI-452

DMA transfer Flag:

service request is generated. DMA transfer cycles
are alternated with instruction execution cycles.
DMA transfers are terminated as in FIFO Demand
Mode.

o .DMA transfer .is not completed.
DMA transfer is complete.

NOTE:
This flag is set when contents of the Byte Count
SFA decrements to zero. It is reset automatically
when the DMA vectors to its interrupt routine.
GO

Enable DMA Transfer:

o

Disable DMA transfer (in all modes).
Enable DMA transfer. If the DMA is in
the Block mode, start DMA transfer if
possible. If it is in the Demand mode,
enable the channel and wait for a demand.
.

NOTE:
The GO bit is reset when the BCA decrements to
zero.

DMA Transfer Modes
The following four modes of DMA operation are possible in the UPI-4S2.

1. ALTERNATE=CYCLE P.10CE

Output Channel
The DMA is configured as in FIFO Demand Mode
and transfers are initiated whenever an Output FIFO
requests service. DMA transfer cycles are alternated
with instruction execution cycles. DMA transfers are
terminated as in FIFO Demand Mode.
The FIFO logic resets the interrupt flag after transferring the byte, so the interrupt is never generated.
Once the DMA is programmed to service the FIFO,
the request for service interrupt for the FIFO is inhibited until the DMA is done (BCA = 0).
.

2. BURST MODE
In BUAST mode the DMA is initiated by setting the
GO bit in the DCON SFR. The DMA operation continues until BCA decrements to zero (zero byte
count), then an interrupt is generated (if enabled).
No interrupts are recognized during a DMA operation once started.

General

Input Channel

Alternate cycle mode is useful when CPU processing must occur during the DMA transfers. In this
mode, a DMA cycle and an instruction cycle occur
alternately. The interrupt request is generated (if enabled) at the end of the process; i.e. when BCA decrements to zero. The transfer is initiated by setting
the GO bit in the DCON SFR.

The FIFO Input Channel can be used in burst mode
by specifying the FIFO IN SFA as the DMA Source·
Address. DMA transfers begin when the GO bit in
the DMA Control SFA is set. The number of bytes to
be transferred must be specified in the Byte Count
SFR (BCA) and auto-incrementing of the SAA must
be disabled. Once the GO bit is set nothing can interrupt the transfer of data until the BCR is zero. In
this mode, a Data Stream Command encountered in
the FIFO will be held in the COMMAND IN SFA with
the pointers frozen, and invalid data (FFH) will be
read through the FIFO IN SFA. If the input FIFO
becomes empty during the block transfer,an OFFH
will be read until BCA decrements to zero.

Alternate-Cycle FIFO Demand Mode
Alternate cycle demand mode is useful for FIFO
transfers of a less urgent nature. As mentioned before, CPU instruction cycles are interleaved with
DMA transfer cycles, allowing true parallel processing.
This mode differs from FIFO Demand Mode in that
.CPU instruction cycles must be interleaved with
DMA transfers, even if the FIFO is demanding DMA.
In FIFO Demand Mode, CPU cycles would never occur if the FIFO demand was present.

Input Channel
The DMA is configured as in FIFO Demand Mode
and transfers are initiated whenever an Input FIFO

Output Channel
The Output FIFO Channel can be used in burst
mode by specifying the FIFO OUT or COMMAND
OUT SFR as the DMA Destination Address. DMA
transfers begin when the GO bit is set. This mode
can be used to send a block of data or a block of
Data Stream Commands. If the FIFO becomes full
during the block transfer, the remaining data will be
lost.

10-182

UPI-452

NOTE:
All interrupts including FIFO interrupts are not recognized in Burst Mode. Burst Mode transfers
should be used to service the FIFO only when the
user is certain that no Data Stream Commands are
in the block to be transferred (Input FIFO) and that
the FIFO contains enough space to store the block
to be transferred. In all other cases Alternate Cycle
or Demand Mode should be used.
3. FIFO AND SERIAL CHANNEL DEMAND
MODES
NOTES:
1. If the output FIFO is configured as a one byte
buffer and the user program consists of two-cycle
instructions only, then Alternate-Cycle Mode should
be used.
2. In non-auto increment mode for internal to external, or external to internal transfers, the lower 8 bits
of the external address should not correspond to
the FIFO or Serial Port address.
FIFO Demand Mode
Although any DMA mode is possible using the FIFO
buffer, only FIFO Demand and Alternate Cycle FIFO
Demand Modes are recommended. FIFO Demand
Mode DMA transfers using the input FIFO Channel
are set-up by setting the GO bit and specifying the
FIFO IN register as the DMA Source Address Register. The BCR should be set to the maximum number
of expected transfers. The user must also program
bit 1 of the Slave Control Register (SC1) to determine whether the Slave Status (SSTAT) SFR FIFO
Request For Service Flag will be activated when the
FIFO becomes not empty or full. Once the Request
For Service Flag is activated by the FIFO, the DMA
transfer begins, and continues u'ntil the request flag
is deactivated. While the request is active, nothing
can interrupt the DMA (Le. it behaves like burst
mode). The DMA Request is held active until one of
the following occurs:
1) The FIFO becomes empty.
2) A Data Stream Command is encountered (this
generates a FIFO interrupt and DMA operation
resumes after the Data Stream Command is
read).
3) BCR = 0 (this generates a DMA interrupt and
sets the DONE bit).
DMA transfers to the Output FIFO Channel are similar. The FIFO OUT or COMMAND OUT SFR is the
DMA Destination Address SFR and a transfer is
started by setting the GO bit. The user programs bit
o of the Slave Control SFR (SCO) to determine
whether a demand occurs when the Output FIFO

is not full or empty. DMA transfers begin when the
Request For Service Flag is activated by the FIFO
logic and continue as long as the flag is active. The
Flag remains active until one of the following occurs:
1) The FIFO becomes full
2) SCR = 0 (this generates a DMA interrupt and
sets the DONE bit).
As in Alternate Cycle FIFO 'Demand Mode, the FIFO
logic resets the interrupt flag after transferring the
byte, so the interrupt is never generated.
After the GO bit is set, the DMA is activated if one of
the following conditions takes place:
SAR(0/1) = FIFO IN and HIFRS flag is set
DAR(0/1) = FIFO OUT and HOFRS flag is set
The HIFRS and HOFRS Signals are internal flags
which are not accessible by software. These flags
are similar to the SSTO and SST4 flags in the Slave
Status Register except that they are of the opposite
polarity and once set they are not cleared until the
Input FIFO becomes empty (HIFRS) or the Output
FIFO becomes full (HOFRS).
Serial Channel Demand Mode
Serial Channel Demand Mode is the logical choice
when using the Serial Port. The OM As can be activated by one of the Serial Channel Flags. Receiver
interrupt (RI) or Transmitter Interrupt (TI).
SAR(0/1) = SBUF and RI flag is set
DAFl(0/1) = SBUF and TI flag is set
NOTE:
TI flag must be set by software to initiate the first
transfer. '
When the DMA transfer begins, only one byte is
transferred at a time. The serial port hardware automatically resets the flag after completion of the
transfer, so an interrupt will not be generated unless
DMA servicing is held off due to the DMA being
done (BCR = 0) or when the Hold/Hold Acknowledge logic is used and the DMA does not own the
bus. In this case a Serial Port interrupt may be generated if enabled because of the status of the RI or
TI flags.
In FIFO demand mode, Alternate cycle FIFO demand mode or Serial Port demand mode only one of
the following registers (SBUF, FIN or FOUT) should
be used- as either the SAR or DAR registers to prevent undesired transfers. For example if SARO =
FIN and DARO = SBUF in demand mode, the DMA
transfer will start if either the HI FRS or TI flags are
set.

10-183

UPI-452

ARBITER MODE: In this mode, the UPI-452 is the
bus master. It configures port pin P1.5 as HLD input
and pin P1.6 as HLDA output. When a device asserts the HLD signal to use the .local bus, the UPI452 asserts the HLDA Signal after current instruction
execution is complete. If the UPI-452 needs an external access via a DMA channel, it waits until the
requester releases the bus, HLD goes inactive.

4. EXTERNAL DEMAND MODE
The DMA can be initiated by an external device via
External interrupt 0 and 1 (INTO/INT1) pins. The
INTO pin demands DMAO (Channel 0) and INT1 demands DMA 1 (Channel 1). If the interrupts are configured in edge mode, a single byte transfer is accomplished for every request. Interrupts also result
(INTO and INT1) after every byte transfer (if enabled). If the interrupts are configured in level mode,
the DMA transfer continues until the request goes
inactive or BCR = o. In either case, a DMA interrupt
is generated (if enabled) when BCR = o. The GO bit
must be set for the transfer to begin.

DISABLE MODE: When external program memory is
accessed by an instruction or by program counter
overflow beyond the internal ROM address or external data memory is accessed by MOVX instructions,
it is a local memory access and the HLD/HLDA logic
is not initiated. When a DMA channel attempts data
transfer to/from the external data memory, the
HLD/HLDA logic is' initiated as described below.
DMA transfers from the internal memory space to
the internal memory space does not initiate the
HLD/HLDA logiC.

EXTERNAL MEMORY DMA
When transferring data to or from external memory
via DMA, the HOLD (HLD) and HOLD-ACKNOWLEDGE (HLDA) signals are used for handshaking;
The HOLD and HOLD-ACKNOWLEDGE are active
low signals which arbitrate control of the local bus.
The UPI-452 can .be used in a system where mUltimasters are connected to a single parallel Address/
Data bus. The HLD/HLDA signals are used to share
resources (memory, peripherals, etc.) among all the
processors on the local bus. The UPI-452 can be
configured in any of three different External Memory
~J.odss controlled by bits 5 and G (REO &.ARSj in
the PCON SFR '(Table 5). Each mode is described
below:

The balance of the PCON SFR bits are described in
the "80C51 Register Description: Power Control
·SFR" section below.

REQUESTER MODE: In this mode, the UPI-452 is
not the bus master, but must request the bus from
another device. The UPI-452 configures port pin
P1.5 as a HLD output and pin P1.6 as a HLDA input.
The UPI-452 issues a HLD signal when it needs external access for a DMA channel. It uses the local
bus after receiving the HLDA signal from the bus
master, and will not release the bus until its DMA
operation is complete.

Latency
When the GO bit is set, the -UPI-452 finishes the
current instruction before starting the DMA operation. Thus the maximum latency is 3.0 microseconds
.'
(at 16 MHz).

DMA Interrupt Vectors
Each DMA channel has a unique vectored interrupt
associated with it. There are two vectored interrupts
associated with the two DMA channels. The DMA
interrupts are enabled and priorities set via the Interrupt Enable and Priority SFR (see "Interrupts" section). The interrupt priority scheme is similar to the
scheme in 80C51.

Table 5. DMA MODE CONTROL - PCON SFR
Symbolic
Address

Physical
Address

-*

PCON

ARB

REQ

-*

-*

(MSB)
. 'Defined as per MLS-51 Data Sheet
Reset Statu!': OOH

-*

-*

-*.
(LSB)

Definition:
ARB

REQ

0
0
1
1

0
1
0
1

HLD/HLDA logic is disabled.
The UPI-452 is in the Requester Mode.
The UPI-452 is in the Arbiter Mode.
Invalid

10-184

87H

infef

UPI-452

When a DMA operation is complete (BCR decrements to zero), the DONE flag in the respective
DCON (DCONO or DCON1) SFR is set. If the DMA
interrupt is enabled, the DONE flag is reset automatically upon vectoring to the interrupt routine.

Interrupts When DMA is Active
If a Burst Mode DMA transfer is in progress, the interrupts are not serviced until the DMA transfer is
complete. This is also true for level activated External Demand DMA transfers. During Alternate Cycle
DMA transfers, however, the interrupts are serviced
at the end of the DMA cycle. After that, DMA cycles
and instruction execution cycles occur alternately. In
the case of edge activated External Demand Mode
DMA transfers, the interrupt is serviced at the end of
DMA transfer of that single byte.

If the UPI-452 (as a Requester) asserts a HLD signal
to request a DMA transfer (see "External Memory
DMA")and its other DMA Channel requests a transfer before the HLDA signal is received, the channel
having higher priority is activated first. A Burst Mode
transfer on channel 0 can not be interrupted since
DMAOhas the highest priority. A Demand Mode
transfer on channel 0 is the only type of activity that
can interrupt a block transfer on DMA 1.
If, while executing a DMA transfer, the Arbiter receives a HLD signal, and then before it can acknowledge, its other DMA Channel requests a transfer, it
then completes the second DMA transfer before
sending the HLDA signal to release the bus to the
HLD request.
DMA transfers may be held off under the following
conditions:
1. A write to any of the DMA registers inhibits the
DMA for one instruction cycle.

DMA Arbitration
Only one of the two DMA channels is active at a
time, except when both are configured in the Alternate Cycle mode. In this case, the DMA cycles and
Instruction Execution cycles occur in the following
order:
1. DMA Cycle o.
2. Instruction execution.
3. DMA Cycle 1.
4. Instruction execution.
DMAO has priority over DMA 1 during simultaneous
activation of the two DMA channels. If one DMA
channel is active, the other DMA channel, if activated, waits until the first one is complete.
If DMAO is already in the Alternate Cycle mode and
DMA 1 is activated in Alternate Cycle Mode, it will
take two instruction cycles before DMA 1 is activated
(due to the priority of DMAO). Once DMA 1 becomes
active, the execution will follow the normal sequence.
If DMAO is already in the Alternate Cycle mode and
DMA 1 is activated in Burst Mode, the DMA 1 Burst
transfer will follow the DMAO Alternate Cycle transfer (after the completion- of the next instruction).

NOTE:
An instruction cycle may be executed in 1, 2 or 4
machine cycles dependent on the instruction being
executed. DMA transfers are only executed after
the completion of an instruction cycle never between machine cycles of a single instruction cycle.
Similarly instruction cycles are only executed upon
completion of a DMA transfer whether it be a one
machine cycle transfer or two machine cycles (for
ext. to ext. memory transfers).
2. A single machine cycle DMA register read operation (Le. MOV A, DCONO) will inhibit the DMA for
one instruction cycle. However a two cycle DMA
register read operation will not inhibit the DMA
(Le. MOV P1, DCONO).
If the HOLD/HOLD Acknowledge logic is enabled in
requestor mode the hold request will go active once
the go bit has been set (for burst mode) and once
the demand flag is set (for demand mode) regardless of whether the DMA is held off by one of the
above conditions.
The DMA Transfer waveforms- are in Figures 8-11.

10-185

intJ

UPI-452

51

52

5.

53

55

56

52

51

5.

53

55

56

05C

Jl.fl.I1.. nsLru-Lfl..I1..ru-Lfl.I1.. n..rLru-L nsLru-L nsLr"'"

ALE

r

PORT2

--

PORTO

r

1\
S URCE ADOR

S

~

AIS-A

OES NATION ADD E55

DATA IN

"7-AO

>--

A7-

Q

X

~ATA

"15 A8

OUT

r
OM" CYCLE

231428-13

Figure 8. DMA Transfer from External Memory to External Memory
OM... CYCLE

51

52

53

55

5'

56

52

51'

53

CLOCK

ALE

PSEN
PORT2

IN51 "DOR

PORTO

INST

SOURCE ADDRESS

"15-A8

DATA IN

A7-AO

iiii
231428-14

Figure 9. DMA Transfer from External Memory to Internal Memory

52

51

53

55

5'

56

51

,I'

52

53

CLOCK

ALE

..JI'_ _-t-_""OES;;;;T~'NA.;.;T;.;.;10.;.;N.;.;AO"'0"iRE;;;.55;....;.A;.;.15;..-'fA8......_ - t -_ _"'i'"_ _+_

PORT2 -:--'-......

PORTO

DATA OUT

I--------O"A CyCLE-------1

231428-15

Figure 10. DMA Transfer from Internal Memory to External Memory

10-186

inter

UPI-452

51

52

53

54

55

56

51

52

53

CLOCK

ALE

P5EN

PORT2

PORTO
IN5TRUCTION
EXECUTION

DMA CYCLE

231428-16

Figure 11. DMA Transfer from Internal Memory to Internal Memory
Table 6. Interrupt Priority
Interrupt Source
Priority Level
(highest)
External Interrupt 0
o
Internal Timer/Counter 0
1
DMA Channel 0 Request
2
External Interrupt 1
3
DMA Channel 1 Request
4
Internal Timer/Counter 1
5
FIFO - Slave Bus Interface
6
Serial Channel
7
(lowest)

INTERNAL INTERRUPTS
Overview
The UPI-452 provides a total of eight interrupt sources (Table 6). Their operation is the same as in the
BOC51 , with the addition of three new interrupt
sources for the UPI-452 FIFO and DMA features.
These added interrupts have their enable and priority bits in the Interrupt Enable and Priority (IEP) SFR.
The IEP SFR is in addition to the BOC51 Interrupt
Enable (IE) and Interrupt Priority (IP) SFRs. The added interrupt sources are also globally enabled or disabled by th~ EA bit in the Interrupt Enable SFR. Table 6 lists the eight interrupt sources in order of priority. Table 7 lists the eight interrupt sources and
their respective address vector location in program
memory. (DMA interrupts are discussed in the "General Purpose DMA Channels" section. Additional interrupt information for Timer/Counter, Serial Channel, External Interrupt may be found in the Microcontroller Handbook for the BOC51.)

Table 7. Interrupt Vector Addresses
Interrupt Source
Starting Address
External Interrupt 0
3 (003H)
Internal Timer/Counter 0
11 (OOBH)
External Interrupt 1
19 (013H)
Internal Timer/Counter 1
27 (01 BH)
Serial Channel
35 (023H)
FIFO - Slave Bus Interface
43 (02BH)
DMA Channel 0 Request
51 (033H)
DMA Channel 1 Request
59 (03BH)

FIFO Module Interrupts to Internal CPU
The FIFO module generates interrupts to the internal CPU whenever the FIFO requests service or
when a Data Stream Command is in the COMMAND
IN SFR. The Input FIFO will request service whenever it becomes full or not empty depending on bit 1 of
the Slave Control SFR (IFRS). Similarly, the Output

FIFO requests service when it becomes empty or
not full as determined by bit 0 of the Slave Control
SFR (OFRS). Request for Service interrupts are
generated only if enabled by the internal CPU via the
Interrupt Enable SFR, and the Slave Control Register.

. 10-1B7

UPI-452

Immediate Command OUT bit (SSTAT SST6) to
be set and the corresponding Host Status bit
(HSTAT HST6) to be cleared indicating the SFR is
empty. When the internal CPU writes to the Imme~
diate Command OUT SFR, the Host Status bit is
set and Slave Status bit is cleared to indicate the
, ~FR isfull. (See Figure 7b, Immediate Command
OUT Flowchart.) ,

A Data Stream Command Interrupt is generated
whenever there is a Data Stream Command in the
COMMAND IN SFR. The interrupt is generated to
ensure that the internal interrupt is recognized before another instruction is executed.

Immediate Command Interrupts
a. An Immediate Command IN interrupt is generated, if enabled, to the internal CPU when the Host
has written to the Immediate Command IN (IMIN)
SFR. The, write operation clears the Slave Status
SFR bit (SSTAT SS:r2) and sets the Host Status
SFR bit (HSTAT HST2) to indicate that a byte is
present in the Immediate Command IN' SFR.
When the internal CPU reads the Immediate Command IN (IMIN) SFR the Slave Status SFR status
bit is set, and the Host Status SFR status bit is
cleared indicating the IMIN SFR is empty. Clearing the Host Status SFR bit will cause a Request
For Service (INTRQ) interrupt, if enabled, to signal
the Host that the IMIN SFR is empty. (See Figure
7a, Immediate Command IN Flowchart.)
b. An Immediate Command OUT interrupt is generated; if enabled, to the internal CPU when the
Host has read the Immediate Command QUT
SFR. The Host read causes the Slave Status

NOTE:
Immediate Command IN and OUT interrupts are actually specific FIFO-Slave Interface interrupts to the
internal CPU.
One instruction from the main program is executed
between two Consecutive interrupt service routines
as in the 80C51. However, if the second interrupt
service routine is due to a Data Stream Command
Interrupt, the main program instruction is not execut~
ed (to prevent misreading of invalid data).

Interrupt Enabling and Priority
Each of the three interrupt special function registers
(IE, IP and IEP) is listed below with its corresponding
bit definitions.

Interrupt Enable SFR (IE)
Symbolic
Address

'

EAI

IE

Physical
Address

I

ES

ET1

,EX1

ETO

(MSB)
Symbol,
EA

ES
ET1
EX1
ETO
EXO

OA8H

(LSB)

P,?sition
IE.7

Function
- Enables all interrupts. If EA = 0, no interrupt will be
acknowledged. If EA = 1, each'interrupt source is
individually enabled or disabfed by setting or clearing its'
-- enable bit.
(reserved)
(reserved)
Serial Channel interrupt enable
Internal Timer/Counter 1 Overflow Interrupt
Externallnterrilpt-Request 1In,ternal Timer/Counter 0 Overflow Interrupt
External Interrupt Request o.
,,'

-

,',EXO

1E.6
1E.5
lEA
1E.3
IE.2
1E.1
lE.O ,

10-188

UPI·452

Interrupt Priority SFR (IP)
A priority level of 0 or 1 may be assigned to each interrupt source, with 1 being higher priority level, through the
IP and the IEP (Interrupt Enable and Priority) SFR. A priority level of 1 interrupt can interrupt a priority level 0
service routine to allow nesting of interrupts.

Symbolic
Address

Physical
Address

IP

PS

PT1

PX1

PTO

Symbol

OB8H

PXO
(LSB)

(MSB)

Position

Function

IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.O

(reserved)
(reserved)
(reserved)
Local Serial Channel
Internal Timer/Counter 1
External Interrupt Request 1
Internal Timer/Counter 0
External Interrupt Request 0

Priority Within
A Level
(lowest)

-

PS
PT1
PX1
PTO
PXO

0.7
0.5
0.3
0.1
0.0
(highest)

Interrupt Enable and Priority SFR (IEP)
The Interrupt Enable and Priority Register establishes the enabling and priority of those resources not covered
in the Interrupt Enable and Interrupt Priority SFRs.

Symbolic
Address

Physical
Address

IEP

I.PFIFO I EDMAO I EDMA1 I PDMAO I PDMA1 I EFIFO I
(MSB)

Symbol

-

-

PFIFO
EDMAO
EDMA1
PDMAO
PDMA1
EFIFO

OF8H

(LSB)

Position

Function

IEP.7
IEP.6
IEP.5
IEP.4
IEP.3
IEP.2
IEP.1
IEP.O

(reserved)
(reserved)
FIFO Slave Bus Interface Interrupt Priority
DMA Channel 0 Interrupt Enable
DMA Channel 1 Interrupt Enable
DMA Channel 0 Priority
DMA Channel 1 Priority
FIFO Slave Bus Interface Interrupt Enable

10-189

Priority
Within a
Level

0.6

0.2
0.4

inter

UPI-452

DMA Freeze Mode bit defaults to FIFO DMA Freeze
Mode (SLCON FRZ = O). Below is a list of the FIFO
Special Function Registers and their default power
on reset values;

FIFO:.EXTERNAL HOST INTERFACE
FIFO DMA FREEZE MODE

Overview
During FIFO DMA Freeze Mode the internal CPU
can reconfigure the FIFO interface. FIFO DMA
Freeze Mode is provided to prevent the Host from
accessing the FIFO during a reconfiguration sequence. The internal CPU invokes FIFO DMA
Freeze MOde by clearing bit 3 of 'the Slave Control
SFR (SC3). INTRQ becomes active whenever FIFO
DMA Freeze Mode is invoked to indicate the freeze
status. The interrupt can only be deactivated by the
Host reading the Host Status SFR.
During FIFO DMA Freeze Mode only two operations
are possible by the Host to the UPI-452 slave, the
balance are disabled, as shown in Table B. The internal DMA is disabled during FIFO DMA Freeze
Mode, and the internal CPU has write access to all
of the FIFO control SFRs (Table 9).

Initialization

SFRName

Label

Value

Channel Boundary Pointer·
Output Channel Read Pointers
Output Channel Write Pointers
Input Channel Read Pointers
Input Channel Write Pointers
Input Threshold
Output Threshold

CBP
ORPR
OWPR
IRPR
IWPR
ITHR
OTHR

40H 164D
40H 164D
40H 164D
OOH 100D
OOH 100D
BOH I 12BD
01H 110

The Input and Output FIFO channels may be reconfigured by programming any of these SFRs while the
FIFO Host interface is in FIFO DMA Freeze Mode.
The UPI-452 also notifies the Host that FIFO DMA
Freeze Mode is in progress by setting the Host
Status SFR FIFO DMA Freeze Mode Status bit,
FIFO DMA Freeze Mode In Progress. The Host interrogates the Host Status SFR to determine the
status of the FIFO Host interface following reset be- .
fore attempting to read ,from or write to the UPI-452
FIFO buffer.

At power on reset the FIFO Host interface is automatica!!y frozen. The Slave Control Enab!e F!FO
Table 8. Slave Bus Interface Status During FIFO DMA Freeze Mode
Operation In
Normal Mode

Interface Pins;
CS A2 A1 AD READ WRITE
DACK

Status In
FIFO DMA Freeze Mode

Read Host Status SFR

Operational

1

Read HostControl SFR

Operational

0

Write Host Control SFR

Disabled

1

Data or DMA Data from
Output Channel

Disabled

1

0

Data or DMA Data to
Input Channel

Disabled

1

0

1

Data Stream Command from Disabled
Output Channel

0

1

1

0

Data Stream Command to
Input Channel

Disabled

1

0

0

0

1

Read Immediate Command
Qut from Output Channel

Disabled

0

1

0

0

1

0

Write Immediate Command
In to Input Channel

Disabled

0

X

X

X

X

0

1

DMA Data from Outp,ut
Channel

Disabled

0

X

X

X

X

1

0

DMA Data to Input Channel

Disabled

1

0

0

1

0

0

1

0

0

1

1

0

1

0

0

1

1

1

1

0

0

0

0

0

1

0

0

0

0

1

0

0

0

1

0

0

1

0

1

1

10-190

inter

UPI·452

FIFO DMA Freeze Mode without first stopping the
external Host from accessing the UPI-452 will not
guarantee a clean break with the external Host.

The UPI-452 can also be programmed to interrupt
the Host following power on reset in order to indicate to the Host that FIFO DMA Freeze Mode is in
progress. This is done by enabling the INTRO interrupt output pin via the MODE SFR (MD4) before the
Slave Control SFR Enable FIFO DMA Freeze Mode
bit is set to Normal Mode. At power on reset the
Mode SFR is forced to zero. This disables all interrupt and DMA output pins (INTRO, DROIN/
INTROIN and DROOUTIINTROOUT). Because the
Host Status SFR FIFO DMA Freeze Mode In Progress bit is set, a Request For Service, INTRO, interrupt is pending until the Host Status SFR is read.
This is because the FIFO DMA Freeze Mode interrupt is always enabled. If the Slave Control FIFO
. DMA Freeze Mode bit (SLCON FRZ) is set to Normal Mode before the MODE SFR INTRO bit is enabled, the INTRO output will not go active when the
MODE SFR INTRO bit is enabled if the Host Status
SFR has been read.

The proper way to invoke FIFO DMA Freeze Mode is
by issuing an Immediate Command to the external
host indicating that FIFO DMA Freeze Mode will be
invoked. Upon receiving the Immediate Command,
the external Host should complete servicing all
pending interrupts and DMA requests, then send an
Immediate Command back to the UPI-452 acknowledging the FIFO DMA Freeze Mode request. After
issuing the first Immediate Command, the internal
CPU should not perform any action on the FIFO until
FIFO DMA Freeze Mode is invoked .
If FIFO DMA Freeze Mode is invoked without stopping the Host during Host transfers, only the last two
bytes of data written into or read from the FIFO will
be valid. The timing diagram for disabling the FIFO
module to the external Host interface is illustrated in
Figure 12. Due to this synchronization sequence, the
UPI-452 might not go into FIFO DMA Freeze Mode
immediately after SC3 is cleared. A special bit in the
Slave Status Register (SST5) is provided to indicate
the status of the FIFO DMA Freeze Mode. The FIFO
DMA Freeze Mode operations described in this section are only valid after SST5 is cleared.

The default values for the FIFO and Slave Interface
represents minimum UPI-452 internal initialization.
No specific Special Function Register initialization is
required to begin operation of the FIFO Slave Interface. The last initialization instruction must always
set the UPI-452 to Normal Mode. This causes the
UPI-452 to exit FIFO DMA Freeze Mode and enables Host read/write access of the FIFO.

As FIFO DMA Freeze Mode is invoked, the DROIN
or DROOUT will be deactivated (stopping the transferring of data), bit 1 of the Host Status SFR will be
set (HST1 = 1), and SST5 will be cleared (SST5 = 0)
to indicate to the external Host and internal CPU
that the slave interface has been frozen. After the
freeze becomes effective, any attempt by the exter.nal Host to access the FIFO will cause the overrun
and underrun bits to be activated (bits HST7 (for
reads) or HST3 (for writes». These two bits, HST3
and HST7, will be set (deactivated) after the Host
Status SFR has been read. If INTRO is used to request service, the FIFO interface is frozen upon
completion of any Host read or write operation in
progress.

Following reset, either hardware (via the RST pin) or
software (via HCON SFR bit HC3) the UPI-452 requires 2 internal machine cycles (24 TCLCL) to update all internal registers.

Invoking FIFO DMA Freeze Mode
During Normal Operation
When the UPI-452 is in normal operation, FIFO DMA
Freeze Mode should not be arbitrarily invoked by
clearing SC3 (SC3 = 0) because the external Host
runs asynchronously to the internal CPU. Invoking

DRQIN/
DRQOUT

..J
~

,
,

~----,
A FIFO RD/WR AFTER INTERFACE
FREEZE IS INVOKED WILL CAUSE
HST 3 OR HST7 TO BE SET

-----55

I' ~.!

5r-------------~~~----~~----~--~~----~

INTRQ

-1_ ---------------------

:FIFO INTERNALLY STOPPED FROM

ACCEPTING OR OUTPUTIING DATA

SC3
HST1 ___________________________

~

231428-17

Figure 12. Disabling FIFO to Host Slave Interface Timing Diagram

10-191

inter

UPI-4S2

External Host writing to the Immediate Command In
SFR and the Host Control SFR is also inhibited
when the .slave bus interface is frozen. Writing to
these two registers after FIFO DMA Freeze Mode is
invoked will also cause HST3 (overrun) to be activated (HST3 = 0). Similarly, reading the Immediate
Command Out Register by the external Host is disabled during FIFO DMA Freeze Mode, and.any attempt to do so will cause the clearing '(deactivating,
"0") of HST7 bit (underrun).
After the slave bus interface is frozen, the internal
CPU can perform the following operations on the
FIFO Special Function Registers (these operations
are allowed only during FIFO DMA Freeze Mode).
For FIFO
Reconfiguration

1. Changing the Channel
Boundary Pointer SFR.
2. Changing the Input and
Output Threshold SFR.

To Enhance the
Testability

3. Writing to ,the read and write
pointers of the Input and
Output FIFO's.
4. Writing to and reading the
Host Control SFRs.
5. Controlling some bits of Host
and Slave Status SFRS.
6. Reading the Immediate
Command Out SFR and
Writing to the Immediate
Comand In SFR.

HCON, the Input Channel error condition flag
(HST3) will be cleared.

Input FIFO Pointer Registers
(IRPR & IWPR)
Once the FIFO module is in FIFO DMA Freeze
Mode, error flags due to overrun and underrun of the
Input FIFO pointers will be dis.abled. Any attempt to
create an overrun or unqerrun condition by changing
the Input FIFO pointers would result in an inconsistency in performance between the status flag and the
threshold counter.
To enhance the speed of the UPI-452, read opera"
tions on the Input FIFO will look ahead by two bytes.
Hence, every time the IRPR is changed during FIFO
DMA Freeze Mode, two NOPs need to be executed
so that the two byte pipeline can be updated with the
new data bytes pointed to by the new IRPR. The
Threshold Counter SFR also needs to change by the
same number of bytes as the IRPR (increase
Threshold Counter if IRPR goes forward or decrease
if IRPR goes backward). This will ensure that future
interrupts will still be generated only after a threshold number of bytes are available. (See "Input and
Output FIFO Threshold SFR" section below.)
In FIFO DMA Freeze Mode, the internal CPU can
also change the content of IWPR, and each change
of IWPR also requires an update. of the Threshold
Counter SPR.

Description of each of these special
functions are as
.. follows:

FIFO Module SFRs During
FIFO DMA Freeze Mode
Table 9 summarizes the characteristics of all the
FIFO Special Function Registers during normal and
FIFO DMA Freeze Modes. Theregisters that require
special treatment in FIFO DMA Freeze Mode are:
HCON, IWPR, IRPR, OWPR, ORPR, HSTAT,
SSTAT, MIN & MOUT SFRs. They can be described
in detail as follows:

Host Control SFR (HCON)
During normal operation, this register is written to or
read by the external Host. However, in FIFO DMA
Freeze Mode (Le. SST5 = 0) the UPI-452 internal
CPU has write access to the Host Control SFR and
write operations to this SFR by the external Host will
not be accepted. If the Host attempts to write to

Normally, the internal CPU cannot write into the Input FIFO. It can, however, during FIFO DMA Freeze
Mode by first reconfiguring the FIFO as an Output
FIFO (Refer to "Input and Output FIFO Threshold
SFR" section below). Changing the IRPR to be
equal to IWPR generates an empty condition while
changing IWPRto be equal to IRPR generates a full
condition. The order in which the pointers are written
determines whether a full or empty condition is generated.

Output.FIFO Pointer SFR
(ORPR and OWPR)
In FIFO DMA Freeze Mode the contents of OWPR
can be changed by the internal CPU, but each.
change of OWPR or ORPR requires the Threshold
Counter SFR to be updated as described in the next
section. A NOP must be executed whenever a new
value is written into ORPR, as just described for
changes to IRPR. As before; changing ORPR to be
equal to OWPR will generate an empty condition,
Output FIFO overrun or underrun condition cannot
be generated though. The FIFO pointers should not
be set to a value outside of its range.

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UPI·452

Table 9. FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Label

Name

Normal
Operation
(SST5 = 1)

FIFO DMA Freeze Mode
Operation
(SST5 = 0)

Read & Write

HCON

Host Control

Not Accessible

HSTAT

Host Status

Read Only

Read & Write 4

Read & Write

Read & Write

SLCON

Slave Control

SSTAT

Slave Status

Read Only

Read & Write 4

IEP

Interrupt Enable & Priority

Read & Write

Read & Write

MODE

Mode Register

Read & Write

Read & Write

IWPR

Input FIFO Write Pointer

ReadOniy

Read & Write 5

IRPR

Input FIFO Read Pointer

Read Qnly

Read & Write 1, 5

OWPR

Output FIFO Write Pointer

Read Only

Read & Write 6

ORPR

Output FIFO Read Pointer

Read Only

Read & Write 2, 6

CBP

Channel Boundary Pointer

Read Only

Read & Write 3

IMIN

Immediate Command In

Read Only

Read & Write

IMOUT

Immediate Command Out

Read & Write

Read & Write

FIN

FIFO IN

Read Only

Read Only

CIN

COMMAND IN

Read Only

Read Only

FOUT

FIFO OUT

Read & Write

Read & Write

COUT

COMMAND OUT

Read & Write

Read & Write

ITHR

Input FIFO Threshold

Read Only

Read & Write

OTHR

Output FIFO Threshold

Read Only

Read & Write

NOTES:
1. Writing of IRPR will automatically cause the FIFO IN SFR to load the contents of the Input FIFO from that location.
2. Writing to ORPR will automatically cause the IOBl SFR to load the contents of the Output FIFO at that ORPR address.
3. Writing to the CBP SFR will cause automatic reset of the four pointers of the Input and Output FIFO channels.
4. The internal CPU cannot directly change the status of these registers. However, by changing the status of the FIFO
channels, the internal CPU can indirectly change the contents of the status registers.
5. Changing the Input FIFO Read/Write Pointers also requires that a consistent update of the Input FIFO Threshold Counter
SFR.
6. Changing the Output FIFO Read/Write Pointers also requires that a consistent update of the Output FIFO Threshold
Counter SFR.

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UPI·452

Input and Output FIFO Threshold SFR
(ITHR & OTHR)

Host Status SFR (HSTAT)

The Input and Output FIFO Threshold SFRs are also
programmable by the internal CPU during FIFO DMA
Freeze Mode. For proper operation of the Threshold
feature, the Threshold SFR should be changed only
when the Input and Output FIFO channels are empty, since they reflect the current number of bytes
available to read/write before an'internipt is generated.
.
Table 10 illustrates the Threshold SFRs range of
values and the number of bytes to be transferred
when the Request For Service Flag is activated:
Table 10. Threshold SFRs Range of Values and
Number of Bytes to be Transferred
ITHR
No. of Bytes
No. of Bytes
OTHR
(lower Available to
(lower
Available to
be Read
~even bits) be Written seven bits
0
1
2

CBP
CBP-1
CBP-2

CBP·3
GBP-2·

,3
2

•
•
•

•
•
•

1
2
3

•
•
•

2
3
4

•
•
•

(80H-CBP)·3 (80H-CBP)-2
(80H-CBP)-2 (80H-CBP)-1
(80H-CBP)·1 (80H-CBP)

The eighth bit of the Input and Output FIFO Threshold SFR indicates the status of the service requests
regardless of the freeze condition. If the eighth bit is
a "1", the FIFO is requesting service from the external Host. In other words, when the Threshold SFR
value goes below zero (2's complement), a service
request is generated". Normally the ITHR SFR is
decremented after each external Host write to the
Input FIFO and incremented after each internal CPU
read of the Input FIFO. The OTHR SFR is decremented by internal CPU writes and incremented by
external Host reads. Thus if the pointers are moved
when the FIFO's are not empty, these relationships
can be used to calculate the offset for the Threshold
SFRs. It is best to change the Threshold SFRs only
when the FIFO's are empty to avoid this complica~
tion. The threshold registers should also be updated
after the pointers have been manipulated.

When in, FIFO DMA Freeze Mode, some bits in the
Host Status SFR are forced high and will not reflect
the new status until the system returns to normal
operation. The definition of the register in FIFO DMA
Freeze Mode is as follows:
NOTE:
The internal CPU reads this shadow latch value
when reading the Host Status SFR. The shadow
latch will keep the information for these bits so normal operation can be resumed with the right status.
The following bits are set (= 1) when FIFO DMA
Freeze Mode is invoked;
HST7 Output FIFO Error Condition Flag,
1 = No error.
o = An invalid read has been done on the
output FIFO or the Immediate Command
Olit Register by the host CPU.
NOTE:
The normal underrun error condition status is disabled. If an Immediate Command Out (IMOUT)
SFR read is attempted during FIFO DMA Freeze
Mode, the contents of the IMOUT SFR is output on
the Data Buffer and the, error status is cleared
(= ~.'
,
HST6 Immediate Command Out SFR Status
During normal operation, this bit is cleared
(= 0) when the IMOUT SFR is written by the
UPI-452 internal CPU and set (= 1) when the
IMOUT SFR is read by the external Host.
Once the host-slave interface is frozen (Le.
SST5 = 0), this bit will be read as a 1 by the
host CPU. A shadow latch will keep the information for this bit so normal operation can be
resumed with the correct status.
Shadow latch:
1 = Internal CPU reads the IMOUT SFR

o = Internal CPU writes to the IMOUT SFR
HST5 Data Stream Command at Output FIFO
This bit is forced to a "1" during FIFO DMA
Freeze Mode to prevent ,the external host
CPU from trying to read the DSC. Once normal. operation is resumed, HST5 will reflect
the Data/Command status of the currentbyte
in the Output FIFO.

NOTE:
When programming the ITHR SFR, the eighth bit
should be set to 1 (OR'd with 80H). This causes
HSTAT SFR HSTO = 0, Input FIFO Request For
Service. If ITHR bit 7 = 0 then HSTAT HSTO = 1,
Input FIFO Does Not Request Service, and no interrupt will be generated.
'The 8th bit of the ITHR SFR must be set during initialization if the
Host interrupt request is desired immediately upon leaving Freeze
Mode,

10-194

Shadow Latch (read by the internal CPU):
1 = No Data Stream Command (DSC)
o = Data Stream Command at Output FIFO

intJ

UPI·452

HST4 Output FIFO Service Request Status
When FIFO DMA Freeze Mode is invoked,
this bit no longer reflects the Output FIFO Request Service Status. This bit wll be forced to
a 111".
HST3 Input FIFO Error Condition Flag
1 = No error.
a = One of the following operations has
been attempted by the external host and
is invalid:
1) Write into the Input FIFO
2) Write into the Host Control SFR
3) Write into the Immediate Command In
SFR

NOTE:
The normal Input FIFO overrun condition is disabled.
HST2 Immediate Command In SFR Status
This bit is normally cleared when the internal
CPU reads the IMIN SFR and set when the
external host CPU writes into the IMIN SFR.
When the host-slave interface is frozen, reading and writing of the IMIN by the internal
CPU will change the shadow latch of this bit.
This bit will be read as a "1" by the external
Host.
Shadow latch.
1 = Internal CPU writes into IMIN SFR
a = Internal CPU reads the IMIN SFR
HST1 FIFO DMA Freeze Mode Status
1 = FIFO DMA Freeze Mode.

a=

Normal Operation
Freeze Mode).

(non-FIFO

DMA

NOTE:
This bit is used to indicate to the external Host that
the host-slave interface has been frozen and hence
the external Host functions are now reduced as
shown in Table 8.
HSTO Input FIFO Request Service Satus
When slave interface is frozen this bit no
longer reflects the Input FIFO Request Service Status. This bit will be forced to a "1".

Slave Status SFR (SSTAT)
The Slave Status SFR is a read-only SFR. However,
once the slave interface is frozen, most of the bits of
this SFR can be changed by the internal CPU by
reconfiguring the FIFO and accessing the FIFO Special Function Registers.

SST? Output FIFO Overrun Error Flag
Inoperative in FIFO DMA Freeze Mode.
SST6 Immediate Command Out SFR Status
In FIFO DMA Freeze Mode, this bit will be
cleared when the internal CPU reads the Immediate Command Out SFR and set when
the internal CPU writes to the Immediate
Command Out Register.
SST5 FIFO-External Interface FIFO DMA Freeze
Mode Status
This bit indicates to the internal CPU that
FIFO DMA Freeze Mode is in progress and
that it has write access to the FIFO Control,
Host control and Immediate Command SFRs.
SST4 Output FIFO Request Service Status
During normal operation, this bit indicates to
the internal CPU that the Output FIFO is
ready for more data. The status of this bit reflects the position of the Output FIFO read
and write pointers. Hence, in FIFO DMA
Freeze Mode, this flag can be changed by the
internal CPU indirectly as the read and write
pointers change.
SST3 Input FIFO Underrun Flag
Inoperative during FIFO DMA Freeze Mode.
During normal operation, a read operation
clears (= 0) this bit when there are no data
bytes in the Input FIFO and deactivated (= 1)
when the Slave Status SFR is read. In FIFO
DMA Freeze Mode, this bit will not be cleared
by an Input FIFO read underrun error condition, nor will it be reset by the reading of the
Slave Status SFR.
SST2 Immediate Command In SFR Status
This bit is normally activated (= 0) when the
external host CPU writes into the Immediate
Command In SFR and deactivated (= 1)
when it is read by the internal CPU. In FIFO
DMA Freeze Mode, this bit will not be activated (= 0) by the external Host's writing of the
Immediate Command IN SFR since this func. tion is disabled. However, this bit will be
cleared (= 0) if the internal CPU writes to the
Immediate Command In SFR and it will be set
= 1) if it reads from the register.
SST1 Data Stream Command at Input FIFO Flag
In FIFO DMA Freeze Mode, this bit operates
normally. It indicates whether the next byte of
data from the Input FIFO is a DSC or data
byte. If it is a DSC byte, reading from the
FIFO IN SFR will result in reading invalid data
(FFH) and vice versa. In FIFO DMA Freeze
Mode, this bit still reflects the type of data
byte available from the Input FIFO.

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UPI-4S2

SSTO Input FIFO Service Request Flag
During normal operation, this bit is activated
(= 0) when the Input FIFO contains bytes that
can be read by the internal CPU and deactivated (= 1) when the Input FIFO does not
need any service from the internal CPU. In
FIFO DMA Freeze Mode, the status of this bit
should not change unless the pointers of the
Input FIFO are changed. In this mode, the internal CPU can indirectly change this bit by
changing the read .and write pointers of the
Input FIFO but cannot change it directly.

changed. (See "Input and Output FIFO Threshold
SFR" section below.)

MEMORY ORGANIZATION
The UPI-452 has separate address spaces for Program Memory and Data Memory like the 80C51. The
Program Memory can be. up to 64K bytes. The lower
8K of Program Memory may reside on-chip. The
Data Memory consists of 256 bytes of on-chip RAM,
up to 64K bytes of off-chip RAM and a number of
"SFRs" (Special Function Registers) which appear
as yet another set of unique memory addresses.

Immediate Command In/Out SFR
(IMIN/IMOUT)

Table 11a_lnternal Memory Addressing
Memory Space

If FIFO DMA Freeze Mode is in progress, writing to
the Immediate Command In SFR by the external
host will be disabled, and any such attempt will
cause HST3 to be cleared (=0). Similarly, the Immediate Command Out SFR read operation (by the
host) will be disabled internally and read attempts
will cause HST7 to be cleared (= 0).

Addressing Method

Lower 128 Bytes of
Internal RAM

Direct or Indirect

Upper 128 Bytes
of Internal RAM

Indirect Only

UPI-452 SFR's

Direct Only

The 80C51 Special Function Registers are listed in
Table 11 a, and the additional UPI-452 SFRs are listed in Table 11 b. A brief description of the 80C51
core SFRs is also provided below.

Internal CPU Read and Write of the
FIFO During FIFO DMA Freeze Mode
In normal operation, the Input FIFO can only be read
by the internal CPU and similarly, the Output FIFO
can only be written by the internal CPU. During FIFO
DMA Freeze Mode, the internal CPU can read the
entire contents of the Input FIFO by programming
the CBP SFR to 7FH, setting the IRPR SFR to zero,
and then the IWPR SFR to zero. Programming the
pointer registers in this order generates a FIFO full
signal to the FIFO logic and enables internal CPU
read operations. If the IWPR and IRPR are already
zero, the write pointer should be changed to a nonzero value to clear the empty status then the pointers can be set to zero. Writing to the IRDR SFR
automatically updates the look ahead registers.
In a similar manner, the internal CPU can write to all
128 bytes of the FIFO by setting the CBP SFR to
zero, setting OWPR SFR to zero, and then setting
ORPR SFR to zero. This generates a FIFO empty
signal and allows internal CPU write operations to all
128 .bytes of the FIFO. The Threshold registers also
need to be adjusted when the pointers are

Accessing External Memory
As in the 80C51, accesses to external memory are
of two types: Accesses to external Program Memory
and accesses to external Data Memory.
External Program Memory is accessed under two
conditions:
1) Whenever signal EA = 0; or
2) Whenever the program counter (PC) contains a
number that is larger than 1FFFH.
This requires that the ROM less versions have EA
wired low to enable the lower 8K program bytes to
be fetched from external memory.
External Data Memory is accessed using either the
MOVX @DPTR (16 bit address) or the MOVX @Ri (8
bit address) instructions, or during external data
memory transfers.

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UPI-4S2

Table 11c. UPI·452 Additional Special
Function Registers (Continued)

Table 11 b. 80C51 Special Function Registers
Symbol

Name

Accumulator
B Register
Program Status
Word
SP
Stack Pointer
DPTR
Data Pointer
(consisting of DPH
and DPL)
PortO
'PO
Port 1
'P1
Port 2
"P2
Port 3
"P3
Interrupt Priority
*IP
Control
Interrupt Enable
"IE
Control
Timer/Counter
TMOD
Mode Control
"TCON Timer/Counter
Control
THO
Timer/Counter
o (high byte) .
TLO
Timer/Counter
o (low byte)
TH1
Timer/Counter
1 (high byte)
TL1
Timer/Counter
.1 (low byte)
"SCON . Serial Control
SBUF
Serial Data Buff
PCON
Power Control
'ACC
'B
'PSW

Address Contents

Symbol

OEOH
OFOH
ODOH

OOH
OOH
OOH

81H
82H

07H
OOOOH

80H
90H
OAOH
OBOH
OB8H

OFFH
OFFH
OFFH
OFFH
OEOH

OA8H

60H

89H

OOH

88H

OOH

8CH

OOH

8AH

OOH

8DH

OOH

8BH

OOH

98H
99H
87H

OOH
I
10H

Symbol

Name

Address Contents

Address Contents
OC2H

I

DARHO Hi Byte/
Channel 0

OC3H

I

DARL1

Low Byte/

OD2H

I

DARH1

Hi Byte/
Channel 1

OD3H

I

DCONO DMAO Control

92H

OOH

DCON1

DMA 1 Control

93H

OOH

FIN

FIFO IN

OEEH

I

FOUT

FIFO OUT

OFEH

I

HCON

Host Control

OE7H

OOH

HSTAT

Host Status

OE6H

OFBH

*IEP

Interrupt Enable
and Priority

OF8H

OCOH

IMIN

Immediate Command
In

OFCH

I

IMOUT

Immediate Command
Out

OFDH

I

IRPR

Input Read
Pointer

OEBH

OOH

ITHR

Input FIFO
Threshold

OF6H

80H

IWPR

Input Write
Pointer

OEAH

OOH

MODE

Mode Register

OF9H

8FH

ORPR

Output Read
Pointer

OFAH

40H

OTHR

Output FIFO
Threshold

OF7H

01H

OWPR

Output Write.
Threshold

OFBH

40H

*P4

Port 4
DMA Source Address

OCOH

OFFH

SARLO

Low Byte/

OA2H

I

SARHO

Hi Byte/
Channel 0

OA3H

I

I = Indeterminate

Table 11c. UPI-452 Additional
Special Function Registers

Name
Low Byte/

DARLO

BCRLO

DMA Byte
Count Low Byte/

OE2H

I

BCRHO

High Byte/
Channel 0

OE3H

I

BCRL1

Low Byte/

OF2H

I

SARL1

Low Byte/

OB2H

I

BCRH1

Hi Byte/
Channel 1

OF3H

I

SARH1

Hi Byte/
Channel 1

OB3H

I

CBP

Channel Boundary
Pointer

OECH

40H

CIN

COMMAND IN

OEFH

I

COUT

COMMAND OUT
DMA Destination
Address

OFFH

I

"SLCON Slave Control
SSTAT

Slave Status

OE8H

04H

OE9H

08FH

I = Indeterminate
The SFRs marked with an asterisk (*) are both bit- and
byte- addressable. The functions of the SFRs are as follows:

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UPI·452

Miscellaneous Special Function
Register Description

DATA POINTER
The Data Pointer (DPTR) consists of a high byte
(DPH) and a low byte (DPL). Its intended function is
to hold a 16-bit address. It may be manipulated as a
16-bit register or as two independent S-bit registers.

SOC51 SFRs

ACCUMULATOR
ACC is the Accumuator SFR. The mnemonics for
accumulator-specific instructions, however, refer to
the accumulator simply as A.

B REGISTER

PORTS 0 TO 4
PO, P1, P2, P3 and P4 are the SFR latches of Ports
0, 1, 2, 3 and 4, respectively.

SERIAL DATA BUFFER

The B SFR is used during multiply and divide operations. For other instructions it can be treated as another scratch pad regster.

PROGRAM STATUS WORD
The PSW SFR contains program status information
as detailed in Table 12.

The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register.
When data is moved to SBUF, it goes to the transmit
buffer where it is held for serial transmission. (Moving a byte to SBUF is what initiates the
transmission.) When data is moved from SBUF, it
comes from the receive buffer.

TIMER/COUNTER SFR
STACK POINTER
The Stack Pointer register is S bits wide. It is incremented before data is stored during PUSH and
CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is.initialized
to 07H after a reset. This causes the stack to begin
at location OSH.

Register pairs (THO, TLO), and (,rH1, TL1) are the
16-bit counting registers for Timer/Counters 0 and 2.

POWER CONTROL SFR (PCON)
The PCON Register (Table 13) controls the power
down and idle modes in the UPI-452, as well as providing the ability to double the Serial Channel baud
rate. There are also two general purpose flag bits
available to the user. Bits 5 and 6 are used to set the
HOLD/HOLD Acknowledge mode (see '~General
Purpose DMA Channels" section), and bit 4 is not
used.

10-19S

inter

UPI·452

Table 12. Program Status Word
Symbolic
Address

Physical
Address

PSW

CY

AC

FO

RS1

RSO

P

OV

(MSB)

ODOH

(LSB)

Symbol

Position

CY
AC
FO
RS1
RSO
OV

PSW.7
PSW.6
PSW.5
PSW.4
PSW.3
PSW.2
PSW.1
PSW.O

P

Name
Carry Flag
Auxiliary Carry (For BCD operations)
Flag 0 (user assignable)
Register Bank Select bit 1"
Register Bank Select bit 0"
Overflow Flag
(reserved)
Parity Flag

'(RS1, RSO) enable Internal RAM register banks as follows:

RS1

RSO

0
0

0

1
1

0

Internal RAM Register Bank
BankO
Bank 1
8ank2
Bank3

1
1

Table 13. peON Special Function Register
Symbolic
Address

Physical
Address
SMOD

PCON

ARB

REO

GF1

(MSB)

GFO

PD

IDL
(LSB)

'Symbol

Position

Function

SMOD

PCON7

ARB
REO
GF1
GFO
PD

PCON6
PCON5
PCON4
PCON3
PCON2
PCON1

IDL

PCONO

Double Baud rate bit. When set to a
1, the baud rate is doubled when the
serial port is being used in either
Mode 1, 2 or 3 ..
HLD/HLDA Arbiter control bit"
HLD/HLDA Requestor control bit"
(reserved)
General-purpose flag bit
General-purpose flag bit
Power Down bit. Setting this bit
activates power down operation.
Idle Mode bit. Setting this bit
activates idle mode operation .

-

..

'See Ext. Memory OM"''' deSCriptIon.

NOTE:
If 1's are written to PO and IOL at the same time, PO takes precedence. The reset value of peON is (OOOXOOOO).

10-199

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UPI-452

• Notice: Stresses above those listed under '~bso­
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ..... o·c to 70'Ct
Storage Temperature .......... - 65'C to

+ 150'C

Voltage on Any
Pin to Vss ............... -0.5V to Vee

+ 0.5V

Voltage on Vee to Vss ............ -0.5V to

+ 6.5V

Power Dissipation ........................ 1.0W··
Vec/Vpp Supply Voltage with
Respect to Ground
During Programming ......... - 0.6V to

NOTICE: Specifications contained within the
following tables are subject to change.

+ 14.0V

D.C. CHARACTERISTICS TA = 0'Ct070'C;Vee = 5V ±10%;Vss =
Symbol

Parameter

Min

Max

Units

0.8

V

Test Conditions

VIL

Input Low Voltage

VIH

Input High Voltage
(except XTAL 1, RST)

2.0

Vee

+ 0.5

V

VIH1

Input High Voltage
(XTAL1, RST)

3.9

Vee

+ 0.5

V

VOL

Output Low Voltage
(Ports 1, 2, 3, 4)

0.45

V

IOL = 1.6 mA (Note 1)

Vou

Output Low Voltage

0.45

V

IOL = 3.2 mA (Note 1)

2.4

V

IOH = -60 /LA, Vee = 5V ±10%

0.75 Vee

V

IOH= -25/LA

0.9 Vee

V

IOH = -10,LA

2.4

V

IOH = -400 /LA, Vee = 5V ±10%

0.75 Vee

V

IOH = -150/LA

0.9 Vee

V

IOH = -40 /LA (Note 2)

2.4

V

IOH = -400 /LA, Vee = 5V

3.0

V

IOH = 1 mA

(.,y,.,.,nt Pnrt
?
_.....- 1., -,
'-.~--I""'.'

VOH

VOH1

VOH2

-0.5

ov

-

~

-, <1\
"

Output High Voltage
(Ports 1, 2, 3, 4)

Output High Voltage
(except Ports 1, 2, 3, 4 and
Host Interface (Slave) Port)
Output High Voltage
(Host Interface (Slave) Port)

V

Vee - 0.4
IlL

Logical 0 Input Current
(Ports 1, 2, 3, 4)

ITL

Logical 1 to 0 Transition
Current (Ports 1, 2, 3., 4)

IOH = -10/LA

-50

/LA

VIN = 0.45V

~650

/LA

VIN = 2V

t Ambient Temperature under Bias for 87e452P IS o'e to 50'e.

10-200

± 10%

UPI-4S2

D.C. CHARACTERISTICS
Symbol

TA

=

O°C to 70°C; VCC

Parameter

Min

=

5V ± 10%; VSS

Max

Units

=

OV (Continued)
Test Conditions

III

Input Leakage Current
(except Ports 1, 2, 3, 4)

±10

p.A

0.45V

< VIN < Vcc

loz

Output Leakage Current
(except Ports 1,2, 3, 4)

±10

p.A

0.45V

< VOUT < Vcc

ICCl

Operating Current (Note 6)

15

mA

Vcc

Icc

Operating Current (Note 7)

50

mA

Vcc

Icci

Idle Mode Current

25

mA

Vcc

Ipo

Power Down Current

100

p.A

Vcc

RRST

Reset Pull down Resistor

150

KO

CIO

Pin Capacitance

20

pF

50

=
=
=
=

5.5V, 16 MHz
5.5V, 16 MHz (Note 4)
5.5V, 16 MHz (Note 5)
2V (Note 3)

1 MHz, TA = 25°C
(sampled, not tested on all parts)

NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1to-O transitions during bus operations. In the worst cases (capacitive loading> 100 pF), the noise pulse on the ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
2. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall before the 0.9 Vee
specification when the address bits are stabilizing.
3. Power DOWN lee is measured with all output pins disconnected; EA = Port 0 = Vee; XTAL2 N.C.; RST = Vss; DB =
Vee; WR = RD = DACK = CS = AO = Al = A2 = Vee. Power Down Mode is not supported on the 87C452P.
4. lee is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH ""
Vee - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = Vee; WR = RD = DACK = CS = AO = A1 = A2 = Vee. lee would be
slightly higher if a crystal oscillator is used.
5. Idle lee is measured with all output pins disconnected; XTAL 1 driven with TCLCH, TCHCL = 5 ns, VIL = Vss + 0.5V,
VIH = Vee - 0.5V; XTAL2 N.C.; Port 0 = Vee: EA = RST = Vss; WR = RD = DACK = CS = AO = A1 = A2 = Vee.
6. 87C452P Piggyback EPROM only.
7. 80C452 and 83C452 only.

EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a 'T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for:
A: Address.

Q: Output data.
R: READ signal.
T: Time.
V: Valid.
W: WRITE signal.

X: No longer a valid logic level.

Z: Float.

C: Clock.
D: Input data.

EXAMPLE

H: Logic level HIGH.

TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.

I:

Instruction (program memory contents).

L: Logic level LOW, or ALE.
P: PSEN.

10-201

UPI-452

A.C. CHARACTERISTICS

TA = O·C to 70·C, Vee = 5V ± 10%, Vss = OV, Load Capacitance for
Port 0, ALE, and PSEN = 100 pF, Load Capacitance for All Other Outputs = 80 pF

EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol

Parameter

16 MHzOsc
Min

Max
16

Variable Oscillator
Min

Units

Max

1/TCLCL

Oscillator Frequency

3.5

TLHLL

ALE Pulse Width

85

2TCLCL-40

MHz
ns

TAVLL

Address Valid to ALE Low

25

TCLCL-55

ns

TLLAX

Address Hold after ALE Low

28

TCLCL-35

ns

TLLlV

ALE Low to Valid Instr In

TLLPL

ALE Low to PSEN Low

22

TPLPH

PSEN Pulse Width

142

TPLIV

PSEN Low to Valid Instr In

4TCLCL-100

185
TCLCL-40

ns

3TCLCL-45

0

ns
3TCLCL-105

110

TPXIX

Inputlnstr Hold after PSEN

TPXIZ

Input Instr Float after PSEN

TAVIV

Address to Valid Instr In

TPLAZ

PSEN Low to Address Float

TRLRH

RD Pulse Width

275

6TCLCL-100

T'vVLVVH

WR Puise Width

275

6TCLCL-iOO

ns

0

ns
ns

57

TCLCL-25

225

5TCLCL-105

ns

10

10

.ns

,

ns
ns

5TCLCL-165

148

ns

TRLDV

RD Low to Valid Data In

TRHDX

Data Hold after RD

TRHDZ

Data Float after RD

TLLDV

ALE Low to Valid Data In

TAVDV

Address to Valid Data In

TLLWL

ALE Low to RD or WR Low

137

TAVWL

Address Valid to Read or Write Low

120

4TCLCL-130

ns

TOVWX

Data Valid to WR Transition

2

TCLCL-60

ns

TWHOX

Data Hold after WR

12

TCLCL-50

ns

0

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High

23

TOVWH

Data Valid to WR (Setup Time)

288

0

ns
2TCLCL-70

ns_

350

8TCLCL-150

ns

398

9TCLCL-165

ns

3TCLCL+50

ns

237

3TCLCL-50

0

10-202

ns

103

TCLCL-40
7TCLCL-150

0

ns

TCLCL+40

ns
ns

inter

UPI-452

EXTERNAL DATA MEMORY READ CYCLE

ALE~

--

TWHLHCJ-----\

r----------------~I~

14
.
1

-

-

-

-

TLLDV - - - - - - I

~

____

I
_J

\\.. _ _- . J1

PORTO

PORT2

P2.0-P2.7 OR A8-A15 FROM DPH

_ _...J

A8-A15 FROM PCH
231428-19

EXTERNAL PROGRAM MEMORY READ CYCLE.

TLHLL ......
ALE
·~~t----TPLPH

----+I

PORTO

PORT2 _ _-'~_ _ _ _~~~_ _ _ _ _J~_ _ _ _~A~8_-~A~1~5________
231428-20

10-203

inter

UPI-452

EXTERNAL DATA MEMORY WRITE CYCLE

.-.rr___________________

~_H_L_H-_L~~

1

ALE.

\...

PSENJ

______

_J

I

'''''_ _-'1

I+---+-~-TOVWH ---f4-I~HOX

r---r~_-"\l

PORTO

PORT2

DATA OUT

A8-A15 FROM PCH

P2.0 - P2.7 OR A8 - A15 FROM DPH

_ _ _J

231428-21

SHIFT REGISTER MODE TIMING WAVEFORMS

I

INSTRUCTION

.,<" .

a

2

4

3

5

7

6

B

n n n n n n n n n n n n n n n n n n

I

-~~~~~~~~~~~~~~~~~~~

_ _ _ _--iI-lXLXL -I
CLOCK

~rlXHOX

\'--__~ ""__~ '-__-JX

OUTPUT DATA

t

3

X

4

X

5

X

6

X

I

7

t

SETTI

WRITE TO SBUF
INPUT DATA _ _ _ _ _J

t

t
CLEAR Rl

SET Rl
231428-22

10-204

inter

UPI-452

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TCLCL

Oscillator Frequency

3.5

16

MHz

TCHCX

High Time

20

TCLCX

Low Time

20

TCLCH

Rise Time

20

ns

TCHCL

Fall Time

20

ns

ns
ns

NOTE:
External clock timings are sampled, not tested on ali parts.

SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: T A
Symbol

=

O·C to 70·C; Vee

=

5V ± 10 %; V55

=

OV; Load Capacitance

16MHzOsc

Parameter

Min

Max

=

80 pF

Variable Oscillator
Min

Max

Units

TXLXL

Serial Port Clock Cycle Time

750

12TCLCL

ns

TOVXH

Output Data Setup to Clock Rising Edge

492

1OTCLCL -133

ns

8

2TCLCL-117

ns

0

0

ns

TXHOX Output Data Hold after Clock Rising Edge
TXHDX

Input Data Hold after Clock Rising Edge

TXHDV

Clock Rising Edge to Input Data Valid

1OTCLCL -133

492

ns

EXTERNAL CLOCK DRIVE WAVEFORM

Vee-0.5 - - - - ~~:-:--"'"

0.45V

231428-23

AC TESTING INPUT, OUTPUT WAVEFORMS

Vee-0.5

--V

0.2 Vee+0.9

FLOAT WAVEFORMS

>C

TIMING REFERENCE
POINTS

1------'.
0.45VJ\_0_.2_V.,,:e::;e_-0_._

.
231428-25
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOHIVOL level occurs.
IOL/IOH <: ± 20 rnA.

231428-24
AC inputs during testing are driven at Vee -0.5V for a logic "1"
and OA5V for a logic "0". Timing measurements are made at VIH
min. for a logic "1" and VIL max. for a logic "0".

10-205

intJ

UPI-4S2

HLD/HLDA WAVEFORMS
Arbiter Mode
HLD

-----.~.

THMIN

V,.....--------=tr-------

----+I.

I - THLAL 114-.----TAMIN I - THHAH

231428-26

j

Requestor Mode

.....If(

HLD _ _ _

,,,..,-----

HLDA _ _~{,~_

I-

TAHHL-----+l-

231428-31

HLD/HLDA TIMINGS
Test Conditions: TA
Symbol

= O·C to

+70·C; Vee

Parameter

= 5V

±10%, Vss

= OV;

16MHzOsc
Min

Load Capacitance

= 80 pF

Variable Oscillator

Max

Min

Max
~I"\'"

Units

TUlAIPt.1

HLD Pulss \Nidth

350

.... lvL.vL.-r: IUU

liS

TAMIN

HLDA Pulse Width

350

4TCLCL+100

ns

THHAH

HLD to HLDA Delay if
HLDA is Granted

I I ItVIII ..

THLAL

HLD to HLDA Delay

TAHHL

HLDA Inactive to
HLDActive

AT"'"

,",I

I

350

4TCLCL-100

4TCLCL+100

ns

350

4TCLCL-100

4TCLCL+100

ns

4TCLCL-100

150

ns

HOST PORT WAVEFORMS

Tee

)

TRV
Tee

TDR

~TDH
DATA
DRQIN
DRQOUT

~

f
)

231428-27

10·206

inter

UPI-4S2

HOST PORT TIMINGS
Test Conditions: TA
Symbol

= O°C to 70·C; Vee = 5V ±10%; Vss = OV; Load Capacitance = 80 pF
Parameter

16 MHzOsc
Max

Min

Variable Oscillator
Min

Max

Units

TCC

Cycle Time

375

6TCLCL

ns

TPW

Command Pulse Width

100

100

ns

TRV

Recovery Time

60

60

ns

TAS

Address Setup Time

5

5

ns

TAH

Address Hold Time

30

30

ns

TOS

Write Data Setup Time

30

30

ns

TOHw

Write Data Hold Time

5

5

ns

TOHR

Read Data Hold Time

5

TOV

READ Active to Read
Data Valid Delay

85

TDR

WRITE Inactive to Read
Data Valid Delay
(Applies only to Host
Control SFR)

300

4.8TCLCL

ns

TRa

READ or WRITE Active
to DRaiN or DRaOUT Delay

150

150

ns

40

5

40

92 nson
12 MHz Part

ns
ns

PROGRAMMING MODES

ERASURE CHARACTERISTICS

Caution: Exceeding 14V on Vpp will permanently
damage the device.

The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately three years, while it
would take approximately one week to cause erasure when exposed to direct sunlight. If the EPROM
is to .be exposed to these types of lighting conditions
for extended periods of time, opaque labels should
be placed over the window to prevent unintentional
erasure.

Initially, all bits of the EPROM are in the "1" state.
Data is introduced by selectively programming "Os"
into the desired bit locations. Although only "Os". will
be programmed, both "1 s" and "Os" can be present
in the data word. The only way to change a "0" to a
"1" is by ultraviolet light exposure (Cerdip
EPROMs).
This device is in the programming mode when Vpp is
raised to its programming voltage and ALE/PGM are
both at TIL-low. The data to be programmed is applied 8 bits in parallel to the Port 0 pins. The levels
required for the address and data inputs are TIL.
The address is applied to Port 1 and 2.

Program Verify
A verify should be performed on the programmed
bits to determine that they have been correctly programmed. The verify is performed with OE at VIL,
PGM at VIH and Vpp and Vee at their programming
voltages.

inteligent IdentifierTM Mode
inteligent IdentifierTM Mode is not supported on the
'
87C452P piggyback EPROM device.

The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a
minimum of fifteen (15) Wsec/cm 2. The erasUre
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 /LW/cm 2
power rating. The EPROM should be placed within
one inch of the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to
without damage is 7258 Wsec/cm 2 (1 week @
12000 /LW/cm2), Exposure of the EPROM to high
intensity UV light for longer periods may cause permanent damage.

10-207

UPI-4S2

DEVICE
FAILED

DEVICE
FAILED

231428-29

Figure 4. inteligent Programming™ Flowchart

inteligent Programming™ Algorithm
The inteligent Programming Algorithm, a standard in
the industry for the past few years, is required for all
of Intel's 12.5V DERDEP EPROMs. Plastic amd
PLCC EPROMs may also be programmed using this
method. A flowchart of the inteligent Programming
Algorithm is shown in Figure 4.

duration of the initial PGM pulse(s) is one millisecond, which will then be followed by a longer overprogram pulse of length 3X ms. X is an iteration counter
and is equal to the number of the initial one millisecond pulses applied to a particular location, before a
correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram
pulse is applied.

The inteligent Programming Algorithm utilizes two
different pulse types: initial and overprogram. The
10-208

UPI-452

The entire sequence of program pulses and byte verifications is performed at Vcc· = 6.0V and Vpp =
12.5V. When the inteligent Programming cycle has been completed, all bytes should be compared to the
. original data with Vee = Vpp = 5.0V.
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING

PORT I.PORT2

VERIFICATION

~C~AgDD~REgSStO~-j'~2=}-----t::!A~DD~R~ES~S~O~-~'2~:>---TAVQV -

PORTO---t-C:JD~~!A~IN=:>-t--------(JD~AT~A~O~UT~1-----

J

I-

TGHDX-

~TDVGl_

_ TAVGl :-

TGHAX

I-

TElQV

I

-

"1

Ll

TEHQZ

----~-I~~~~ I~,--------~--~~TD-H-AX-~---AlE/PGM

-j

I

~,TPHGl

+:~~~l

1-

TDXOl- 1

·1

-ITEHSH

231428-30

A.C. PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C (see EPROM PROGRAMMING D.C. CHARACTERISTICS for Vee and Vpp Voltages)
Symbol

Parameter

12MHzOSC
Min

Max

Unit

2.9

J.l.s

TAVGL

Address Setup to PGM

TDXOL

OE Setup from Data Float

2.0

J.l.s

TDVGL

Data Setup to PGM

3.8

J.l.s

TOHAX

Address Hold after OE

0

J.l.s

TGHDX·

Data Hold after PGM

TEHOZ

Data Float after OE

0

TOHAX

Address Hold after PGM

0

J.l.s

TPHGL

Vpp Setup to PGM

2.0

J.l.s

TCHGL

Vee Setup to PGM

2.0

J.l.s

TEHSH

OE Setup to Vpp and Vee

2.0

TGLGH

PGM Pulse Width

0.95

TAVQV

Address to Data Valid

TOPW

PGM Overprogram Pulse Width

TELOV

Data Valid from OE

2.0

2.85

Test Conditlons*(1)

ns
1.6

J.l.s

(Note 3)

J.l.s
1.05

ms

3.0

J.l.s

78.75

ms

2.0

J.l.s

inteligent Programming
(Note 2)

NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. The length of the overprogram pulse may vary from 2.85 ms to 78.75 ms as a function of the iteration counter value X
(inteligent Programming Algorithm only).
3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
4. The maximum current value is· with Port 0 unloaded.

10-209

intJ

UPI-452

D.C. PROGRAMMING CHARACTERISTICS

TA = 25°C ±5%

Limits
Symbol

Parameter

Min

Max

Test Conditions*(1)
Unit

lee2(4)

Vee Supply Current (Program and Verify)

150

mA

IpP2(4)

Vpp Supply Current (Program)

50

mA

VID

Ag Inteligent Identifier Voltage

11.5

12.5

V

Vpp

inteligent Programming Algorithm

12.0

13.0

V

Vee

inteligent Programming Algorithm

5.75

6.25

V

10-210

CE

= VIL

CE

= PGM = VIL

inter

APPLICATION
NOTE

AP-70

November 1987

Using the Intel MCS®-51 Boolean
Processing Capabilities

JOHN WHARTON
MICROCONTROLLER APPLICATIONS

Order Number: 203830·001
10·211

AP-70

1.0 INTRODUCTION
The Intel microcontroller family now has three new
members: the Intel® 8031, 8051, and 8751 single-chip
microcomputers. These devices, shown in Figure I, will
allow whole new classes of products to benefit from
recent advances in Integrated Electronics. Thanks to
Intel's new HMOS technology, they provide larger program and data memory spaces, more flexible I/O and
peripheral capabilities, greater speed, and lower system
cost than any previous-generation single-chip microcomputer.

- vee

P1.0P1.1-

- po.o

P1.2 -

-

P1.3 -

-

PO.2

P1.4 -

-

PO.3

P1.5 -

- PO.4

PO .. 1

P1.6-

-

PO.5

PH -

-

PO.6

-

PO.7

RST -

- VPP/EA

P3.0/RXD -

-~/ALE

P3.1/TXD -

p3.2iiNTci -

- PSEN

P3.3/iNii -

- P2.7

P3.4/TO -

-

P2.6

P3.51T1 -

-

P2.5

- P2.4

P3.6/WR P3.7/iiii -

- P2.3

XTAL2 -

-

P2.2

XTAL1 -

-

P2.1

VSS -

-

P2.0
203830-1

Figure 1. 8051 Family Pinout Diagram

Table 1 summarizes the quantitative differences between the members of the MCS®-48 and 8051 families.
The 8751 contains 4K bytes of EPROM program memory fabricated on-chip, while the 8051 replaces the
EPROM with 4K bytes of lower-cost maskprogrammed ROM. The 8031 has no program memory
on-chip; instead, it accesses up to 64K bytes of program
memory from external memory. Otherwise, the three
new family membeJ,"S are identical. Throughout this
Note, the term "8051" will represent all members of the
8051 Family, unless specifically stated otherwise.
The CPU in each microcomputer is one of the industry's fastest and most efficient for numerical calculations on byte operands. But controllers often deal with
bits, not bytes: in the real world, switch contacts can
only be open or closed, indicators should be either lit or
dark, motors are either turned on or off; and so forth.
For such control situations the most significant aspect
of the MCS®-51 architecture is its complete hardware
support for one-bit, or /loolean variables (named in
honor of MathematiCian George Boole) as a separate
data type.
The 8051 incorporates a number of special features
which support the direct manipulation and testing of
individual bits and allow the use of single-bit variables
in performing logical operations. Taken together, these
features are referred to as the MCS-Sl Boolean Processor. While the bit-processing capabilities alone would be
adequate to solve many' control applications, their true
power comes when they are used in conjunction with
the microcomputer's byte-processing and numerical capabilities.
Many concepts embodied by the Boolean Processor will
certainly be new even to experienced microcomputer
system designers. The purpose of this Application Note
is to explain these concepts and show how they are
used.
For detailed information on these parts refer to the
Intel Microcontroller Handbook, order number
210918. The instruction set, assembly language, and use
of the 8051 assembler (ASM51) are further described iIi
the MCS®·51 Macro Assembler User's Guide for DOS
Systems, order number 122753.

Table 1. Features of Intel's Single-Chip Microcomputers
EPROM
Program
Memory

ROM
Program
Memory

External
Program
Memory

Program
Memory
(Int/Max)

Data
Memory
(Bytes)

Instr.
Cycle
Time

Input!
Output
Pins

8748

8048
8049
8051

8035
8039
8031

1K4K
2K4K
4K64K

64
128
128

2.5 JLs
1.36 JLs
1.0 JLs

27
27
32

8751

10-212

Interrupt
Sources

Reg.
Banks

2
2

2
2
4

5

inter

AP-70

2.0 BOOLEAN PROCESSOR
OPERATION
The Boolean Processing capabilities of the 8051 are
based on concepts which have been around for some
time. Digital computer systems of widely varying designs all have four functional elements in common (Figure 2):
• a central processor (CPU) with the control, timing,
and logic circuits needed to execute stored instructions:
• a memory to store the sequence of instructions making up a program or algorithm:
• data memory to store variables used by the program:
and
• some means of communicating with the outside
world.
The CPU usually includes one or more accumulators or
special registers for computing or storing values during
program execution. The instruction set of ~uch a
processor generally includes, at a minimum, operation
classes to perform arithmetic or logical functions on
program variables, move variables from one place to
another, cause program execution to jump or conditionally branch based on register or variable states, and
instructions to call and return from subroutines. The
program and data memory functions sometimes share a
single memory space, but this is no~ always the case.
When the address spaces are separated, program and
data memory need not even have the same basic word
width.
A digital computer's flexibility comes in part from
combining simple fast operations to produce more com-

plex (albeit slower) ones, which in tum link together
eventually solving the problem at hand. A four-bit CPU
executing multiple precision subroutines can, for example, perform 64-bit addition and subtraction. The subroutines could in tum be building blocks for floatingpoint multiplication and division routines. Eventually,
the four-bit CPU can simulate a far more complex "'virtual" machine.
In fact, any digital computer with the above four functional elements can (given time) complete any algorithm (though the proverbial room full of chimpanzees
at word processors might first re-create Shakespeare's
classics and this Application Note)! This fact offers little consolation to product designers who want programs to run as quickly as possible. By definition, a
real-time contrql algorithm must proceed quickly
enough to meet the preordained speed constraints of
other equipment.
One of the factors determining how long it will take a
microcomputer to complete a given chore is the number of instructions it must execute. What makes a given
computer architecture particularly well- or poorly-suited for a class of problems is how well its instruction set
matches the tasks to be performed. The better the
"primitive" operations correspond to the steps taken by
the control algorithm, the lower the number of instructions needed, and the quicker the program will run. All
else being equal, a CPU supporting 64-bit arithmetic
directly could clearly perform floating-point math faster than a machine bogged-down by multiple-precision
subroutines. In the same way, direct support for bit
manipulation naturally leads to more efficient pro~
grams handling the binary input and output conditions
inherent in digital control problems.

TIMING &
CONTROL
PROGRAM
MEMORY
ACCUMULATOR
& REGISTERS
INPUTI
OUTPUT
PORTS

DATA
MEMORY

REAL
WORLD

CENTRAL
PROCESSING
UNIT

203830-2

Figure 2. Block Diagram for Abstract Digital Computer
10-213

AP·70

Processing Elements
The introduction stated that the 8051 's bit-handling capabilities alone would be sufficient to solve some control applications. Let's see how the four basic elements
of a digital computer-a CPU with associated registers,
program memory, addressable data RAM, and I/O capability-relate to Boolean variables.
CPU. The 8051 CPU incorporates special logic devoted
to executing several bit-wide operations. All told, there
are 17 such instructions, all listed in Table 2. Not
shown are 94 other (mostly byte-oriented) 8051 instructions.

tions of Table 2, several sophisticated program control
features like multiple addressing modes, subroutine
nesting, and a two-level interrupt structure are useful in
s~ructuring Boolean Processor-based programs.
Boolean instructions are one, two, or three bytes long,
depending on what function they perform. Those involving only the carry flag have either a single-byte
opcode or an opcode followed by a conditional-branch
destination byte (Figure 3a). The more general instructions add a "direct address" byte after the opcode to
specify the bit affected, yielding two or three byte encodings (Figure 3b). Though this format allows potentially 256 directly addressable bit locations, not all of
them are implemented in the 8051 family.

Program Memory. Bit-processing instructions are
fetched from the same program memory as other arithmetic and logical operations. In addition to the instrucTable 2. MCS·S1TM Boolean
Processing Instruction Subset
Byte eyc

Mnemonic

Description

SETB
SETB
CLR
CLR
CPL
CPL

C
bit
C
bit
C
bit

Set Carry flag
Set direct Bit
Clear Carry flag
Clear direct bit
Complement Carry flag
Complement direct bit

1
2
1
2
1
2

1
1
1
1
1
1

MOV
MOV

C.bit
bit.C

Move direct bit to Carry flag
Move Carry flag to direct bit

2
2

1
2

ANL
ANL

C.bit
C.bit

2
2

2
2

ORL
ORL

C.bit
C.bit

AND direct bit to Carry flag
AND complement of direct
bit to Carry flag
OR direct bit to Carry flag
OR complement of direct
bit to Carry flag

2
2

2
2

JC
JNC
JB
JNB
JBC

rei
rei
bit.rel
bit.rel
bit.rel

Jump if Carry is flag is set
Jump if No Carry flag
Jump if direct Bit set
Jump if direct Bit Not set
Jump if direct Bit is set &
Clear bit

2
2
3
3
3

2
2
2
2
2

opcode
SETBC
CLRC
CPLC
opcode
JC

jNC

I displacement I
rei
rei

a.) Carry Control and Test Instructions
opcode

Address mode abbreviations
C-Carry flag.
bit-128 software flags, any 1/0 pin, control or status
bit.
rei-Ali conditional jumps include an 8-bit offset byte.
Range is + 127 -128 bytes relative to first byte of the
following instruction.
All mnemonics copyrighted@ Intel Corporation 1980.

SETB
CLR
CPL
ANLC,
ANL C,/
ORLC,
ORL C,/
MOVC,
MOV
opcode
JB
JNB
JBC

I I bit address
bit
bit
bit
bit
bit
bit
bit
bit
bit,C

I I bit address I displacement I
bit,
bit,
bit,

rei
rei
rei

b.) Bit Manipulation and Test Instructions
Figure 3. Bit Addressing Instruction Formats

10-214

AP-70

Dtrect
RAM
Byte

7FH~
1-";:;'"

Bit Addr•••••

B~te

(LSB)

(MSB)

Addr••• (MSB)

(LSB)

Hardware
Regl.ter
Symbol

OFFH
I~

2FH

7F

7E

7D

7C

7B

7A

79

78

2EH

n

76

75

74

73

72

71

70

2DH

6F

6E

6D

6C

6B

6A

69

68

2CH

67

66

65

64

63

62

61

60

2BH

SF

5E

5D

5C

5B

SA

59

58

2AH

57

56

55

54

53

52

51

50

29H

4F

4E

4D

4C

4B

4A

49

48

28H

47

46

45

44

43

42

41

40

27H

3F

3E

3D

3C

3B

3A

39

38

26H

37

36

35

34

33

32

31

3D

25H

2F

2E

2D

2C

2B

2A

29

28

24H

27

26

25

24

23

22

21

20

23H

IF

IE

lD

lC

lB

lA

19

18

22H

17

16

15

14

13

12

11

10

21H

OF

DE

OD

OC

DB

OA

09

08

20H

07

06

05

04

03

02

01

DO

OFOH

F7

FO

B

OEOH

E7

EO

ACC

ODOH

D7

DO

PSW

B8

tP

OB8H

OBOH

B7

BO

P3

OA8H

AF

A8

tE

OAOH

A7

AO

P2

98H

9F

98

SCON

90H

97

90

PI

88H

8F

88

TCON

80H

87

80

PO

lFH
18H
17H

Bank 3

10H
OFH

Bank 2

D8H

Bank 1

07H

DO

BankO

203830-3

a.):RAM Bit Addresses·

b.) Special Function Register Bit Addresses
Figure 4. Bit Address Maps

Data Memory. The instructions in Figure 3b can operate directly upon 144 general purpose bits forming the
Boolean processor "RAM." These bits can be used as
software flags or to store program variable~. Two operand instructions use the CPU's carry flag ("C") as a
special one-bit register: in a sense, the carry is a "Boolean accumulator" for logical operations and data transfers.

Input/Output. All 32 I/O pins can be addressed as individual inputs, outputs, or both, in any combination.
Any pin can be a control strobe output, status (Test)
input, or serial I/O link implemented via software. An
additional 33 individually addressable bits reconfigure,
control, and monitor the status of the CPU and all onchip peripheral functions (timer counters, serial port
modes, interrupt logic, and so forth).

10-215

inter

AP-70

(MSB)
I CY lAC I FO

(LSB)
RS1

RSO

OV

PSW.2

P

PSW.1
PSW.O

OV

Symbol Position Name and Significance
CY
PSW.7 Carry flag.
Settcleared by hardware· or
software .during certain arithmetic and logical instructions.
AC
PSW.6 Auxiliary Carry flag.
Settcleared by hardware during addition or subtraction instructions to indicate carry or
borrow out of bit S.
FO
PSW.5 Flag O.
Settcleared/tested . by software as a user-defined status
flag.
RS1
PSW.4 Register bank Select control
bits.
RSO
PSW.S 1 & O. Settcleared by software
to determine working register
bank (see Note).

Note-

Overflow flag.
Settcleared by hardware during arithmetic instructions to
indicate overflow conditions.
(reserved)
Parity flag.
Set/cleared by hardware each
instruction cycle to indicate an
odd/even number of "one"
bits in the accumulator, i.e.,
even parity:
the contents of (RS1, RSO)
enable the working register
banks as follows:
(0,0) - Bank 0
(OOH-07H)
(0,1) - Bank 1
(OBH-OFH)
(1,0)-Bank2
(19H-17H)
(1,1) - Bank S
(1BH-1FH)

Figure 5. PSW-Program Status Word Organization

(MSB)

(LSB)

I RD I WR I T1 I TO IINT1 I INTO

I TXD I RXD I

Symbol Position Name and Significance
RD
PS.7
Read data control output.
Active low pulse generated by
hardware when external data
memory is read.
WR
PS.6
Write data control output.
Active low pulse generated by
hardware when external data
memory is written.
T1
PS.5
Timer/counter 1 external input
or test pin.
TO
PS.4
Timer/counter 0 external input
or test pin.

INT1

PS.S

INTO

PS.2

TXD

PS.1

RXD

PS.O

Interrupt 1 input pin.
Low-level or falling-edge triggered.
Interrupt 0 input pin.
Low-level or falling-edge triggered.
Transmit Data pin for serial
port in UART mode. Clock output in shift register mode.
Receive Data pin for serial
port in UART mode. Data I/O
pin in shift register mode.

Figure 6. P3-Alternate I/O Functions of Port 3

Direct Bit Addressing
The most significant bit of the direct address byte selects one of two groups of bits: Values between 0 and
127 (DOH and 7FH) defme bits in a block of 32 bytes of
on-chip RAM, between RAM addresses 20H and 2FH
(Figure 4a). They are numbered consecutively from the
lowest-order byte'S lowest-order bit through the highest-order byte'S highest-order bit.

Bit addresses between 128 and 255 (80H and OFFH)
correspond to bits in a number of special registers,
mostly used for I/O or peripheral control. These positions are numbered with a different scheme than RAM:
the five high-order address bits match those of the register's own address, while the three low-order bits identify the bit position within that register (Figure4b).

10-216

infef

AP-70

Notice the column labeled "Symbol" in Figure 5. Bits
with special meanings in the PSW and other registers
have corresponding symbolic names. General-purpose
(as opposed to carry-specific) instructions may access
the carry like any other bit by using the mnemonic CY
in place of C, PO, PI, P2, and P3 are the 8051's four
I/O ports: secondary functions assigned to each of the
eight pins of P3 are shown in Figure 6.
Figure 7 shows the last four bit addressable registers.
TCON (Timer Control) and SCON (Serial port Control) control and monitor the corresponding peripherals, while IE (Interrupt Enable) and IP (Interrupt Priority) enable and prioritize the five hardware interrupt
sources. Like the reserved hardware register addresses,

the five bits not implemented in IE and IP should not
be accessed: they can not be used as sof~ware flags.
Addressable Register Set. There are 20 special function

registers in the 8051, but the advantages of bit addressing only relate to the II described below. Five potentially bit-addressable register addresses (OCOH, OC8H,
OD8H, OE8H, & OF8H) are being reserved for possible
future expansion in microcomputers based on the
MCS-51 architecture. Reading or writing non-existent
registers in the 8051 series is pointless, and may cause
unpredictable results. Byte-wide logical operations can
be used to manipulate bits in all non-bit addressable
registers and RAM.

10-217

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AP-70

(MSB)

(LSB)

TCON.3 Interrupt 1 Edge flag.
Set by hardware when external interrupt edge detected.
Name and Significance
Cleared when interrupt proTimer 1 overflow Flag.
cessed.
Set by hardware on timer/
TCON.2 Interrupt 1 Type control bit.
In
counter overflow. Cleared
Set/cleared by software to
when interrupt processed.
specify falling edge/low level
triggered external interrupts.
Timer 1 Run control bit.
Set/cleared by software to turn
rCON.1 Interrupt 0 Edge flag:
lEO
timer/counter on/off.
Set by hardware when exterTimer 0 overflow Flag.
nal interrupt edge detected.
Set by hardware on timer/
'Cleared when interrupt proCleared
cessed.
counter overflow.
when interrupt processed.
ITO
TCON.O Interrupt 0 Type control bit.
Timer 0 Run control bit.
Set/cleared by software to
specify falling edge/low level
Set/cleared by software to turn
timer/counter on/off.
triggered external interrupts.
a.) TCON-Timer/Counter Control/Status Register

ITF1 I TR1 I TFO I TRO IIE1 IIT1 I lEO liTO I
Symbol Position
TF1
TCON.7

TR1

TCON.a

TFO

TCON.5

TRO

TCONA

(MSB)

(LSB)

ISMO I SM1 I SM21 REN I TBS I RBSI TI I RI I

IE1

RBB

SCON.2 Receive Bit B.
Set/cleared by hardware to indicate state of ninth data bit

received.
Symbol Position Name and Significance
SMO
SCON.7 Serial port Mode control bit o.
SCON.1 Transmit Interrupt flag.
TI
Set/cleared by software (see
Set by hardware when byte
note).
transmitted. Cleared by software after servicing.
SM1
SCON.a Serial port Mode control bit 1.
Set/cleared by software (see
RI
SCON.O Receive Interrupt flag.
note).
Set by hardware when bytereceived. Cleared by software
SM2
SCON.5 Serial port Mode control bit 2.
after servicing.
Set by software to disable reception of frames for which bit
Notethe state of (SMO, SM1)
B is zero.
selec~s:
(O,O)-Shift register I/O
REN
SCON.4 Receiver Enable control bit.
expansion.
Set/cleared by software to en(0,1 )-8-bit UART, variable
able/disable serial data recepdata rate.
tion.
(1,O)-9-bit UART, fixed data
TBB
SCON.3 Transmit Bit B.
rate.
Set/cleared by hardware to de(1,1 )":"'9-bit UART, variable
terminestate of ninth data bit
data rate.
transmitted in 9-bit UART
mode.
b.) SCON--Serial Port Control/Status Register
Figure 7. Peripheral Configuration Registers

10-21B

AP-70

(MSB)

(lSB)
ES

ET1

EX1

ET1

1

EXO

1

Symbol Position Name and Significance,

EA

IE.?

ES

1E.6
1E.5
IE.4

ET1

IE.3

Enable All control bit.
Cleared by software to disable
all interrupts, independent of
the state of IE.4-IE.O.
(reserved)

EX1

1E.2

ETO

IE.1

Enable Serial port control bit.
EXO
IE.O
Set/cleared by software to enable/disable interrupts from TI
or RI flags.
Enable Timer 1 control bit.
Set!cleared by software to enable/disable interrupts from
timer/counter 1.
c.) IE-Interrupt Enable Register

(MSB)

Enable External interrupt 1
control bit. Set! cleared by
software to enable/disable interrupts from INT1.
Enable Tilller 0 control bit.
Set! cleared by software to enable/disable interrupts from
timer / counter O.
Enable External interrupt 0
control bit. Set/cleared by
software to enable/disable interrupts from INTO.

(lSB)

1-1-1

PS

Symbol Position
IP.?
IP.6
IP.5

PS

IP.4

PT1

IP.3

PT1

PX1

PTO

PXO

PX1

External interrupt 1 Priority
control bit. Set/cleared by
software to specify high/low
priority interrupts for INT1.
Serial port Priority control bit.
PTO
IP.1
Timer 0 Priority control bit.
Set! cleared by software to
Set/ cleared by software to
specify high/low priority interspecify high/low priority interrupts for Serial port.
rupts for timer/counter O.
Timer 1 Priority control bit.
PXO
IP.O
External interrupt 0 Priority
control bit. Set/cleared by
Set/cleared by software to
specify high/low priority intersoftware to specify high/low
rupts for timer/counter 1.
priority interrupts for INTO.
d.) IP-Interrupt Priority Control Register
Name and Significance
(reserved)
(reserved)
(reserved)

IP.2

Figure ? Peripheral Configuration Registers (Continued)

The accumulator and B registers (A and B) are normally involved in byte-wide arithmetic, but their individual
bits can also be used as 16 general software flags. Added with the 128 flags in RAM, this gives 144 general
purpose variables for bit-intensive programs. The program status word (PSW) in Figure 5 is a collection of
flags and machine status bits including the carry flag
itself. Byte operations acting on the PSW can therefore
affect the carry.

Instruction Set
Having looked at the bit variables available to the Boolean Processor, we will now look at the four classes of

instructions that manipulate these bits. It may be helpful to refer back to Table 2 while reading this section.
State Control. Addressable bits or flags may be set,
cleared, or logically complemented in one instruction
cycle with the two-byte instructions SETB, CLR, and
CPL. (The "B" affixed to SETB distinguishes it from
the assembler "SET" directive used for symbol definition.) SETB and CLR are analogous to loading a bit
with a constant: 1 or O. Single byte versions perform the
same three operations on the carry.

The MCS-51 assembly language specifies a bit address
in any of three ways:
• by a number or expression corresponding to the direct bit address (0-255):

10-219

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AP-70

• by the name or address of the register containing the
bit, the dot operator symbol (a period: "."), and the
bit's position in the register (7 -0):
• in the case of control and 'status registers, by the
predefined assembler symbols listed in the first columns'ofFigures 5-7.
Bits may also be given user-defined names with the assembler "BIT" directive and any of the above techniques. For example, bit 5 of the PSW may be cleared
by any of the four instructions.
USR_FLG BIT

PSW.5

User Symbol Definition

CLR
CLR
CLR

OD5H
PSW.5
FO

CLR

USR_FLG

Absolute AddreSSing
Use of Dot Operator
Pre-Defined Assembler
Symbol
User-Defined Symbol

Data Transfers. The two-byte MOV instructions can
transport any addressable bit to the carry in one cycle,
or copy the carry to the bit in two cycles. A bit can be
moved between two arbitrary locations via the carry by
combining the two instructions. (If necessary, push and
pop the PSW to preserve the previous contents of the
carry.) These instructions can replace the multi-instruction sequence of Figure 8, a program structure appearing in controller applications, whenever flags or outputs
are conditionally switched on or off.
-

Bit-test Instructions. The conditional jump instructions
"JC rei" (Jump on Carry) and "JNC rei" (Jump on
Not Carry) test the state of the carry flag, branching if
it is a one or zero, respectively. (The letters "rei" denote relative code addressing.) The three-byte instructions "JB bit.rel" and "JNB bit. rei" (Jump on Bit and
Jump on Not Bit) test the state of any addressable bit in
a similar manner. A fifth instruction combines the
Jump ~m Bit and Clear operations. "JBC bit. rei" conditionally branches to the indicated address, then clears
the bit in the same two cycle instruction. This operation
is the same as the MCS-48 "JTF" instructions.
All 8051 conditional jump instructions use program
counter-relative addressing, and all execute in two cycles. The last instruction byte encodes a signed displacement ranging from -128 to + 127. During execution, the CPU adds this value to the incremented program counter to produce the jump destination. Put another way, a conditional jump to the immediately foliowing instruction wouid encode OOH in the offset byte.
A section of program or subroutine written using only
relative jumps to nearby addresses will have the same
machine code independent of the code's location. An
assembled routine maybe repositioned anywhere in
memory, even crossing memory page boundaries, without having to modify the program or recompute destination addresses. To facilitate this flexibility, there is iui
unconditional "Short Jump" (SJMP) which uses relative addressing as well. Since a programmer would have
quite a chore trying to compute relative offset values
from one instruction to another, ASM51 automatically
computes the displacement needed given only the destination address or label. An error message will alert the
programmer if the destination is "out of range."

ISOLATE
SOURCE
BIT

NO

SET
DESTINATION
BIT

Logical Operations. Four instructions perform the logical-AND and logical-OR operations between the carry
and another bit, and leave the results in the carry. The
instruction mnemonics are ANL and ORL;' the absence
or presence of a slash mark ("/") before the source
operand indicates whether to use the positive-logic value or the logical complement of the addressed bit. (The
source operand itself is never affected.)

CLEAR
DESTINATION
BIT

The so-called "Bit Test" instructions implemented on
many other microprocessors simply perform the logical-AND operation between a byte variable and a constant mask, and set or clear a zero flag depending on
the result. This is essentially equivalent to the 8051
"MOV C.bit" instruction. A second instruction'is then
needed to conditionally branch based on the state of the
zero flag. This does not constitute abstract bit-addressing in the MCS-51 sense. A flag exists only as a field

203830-4

Figure 8. Bit Transfer Instruction Operation

10-220

AP-70

within a register: to reference a bit the programmer
must know and specify both the encompassing register
and the bit's position therein. This constraint severely
limits the flexibility of symbolic bit addressing and reduces the machine's code-efficiency and speed.

Interaction with Other Instructions. The carry flag is
also affected by the instructions listed in Table 3. It can
be rotated through the accumulator, and altered as a
side effect of arithmetic instructions. Refer to the User's Manual for details on how these instructions operate.

Table 3. Other Instructions Affecting
the Carry Flag
Mnemonic

ADD

A,Rn

ADD

A,direct

ADD

A,@Ri

ADD

A,#data

AD DC A,Rn

Simple Instruction Combinations

ADDC A,direct

By combining general purpose bit operations with certain addressable bits, one can "custom build" several
hundred useful instructions. All eight bits of the PSW
can be tested directly with conditional jump instructions to monitor (among other things) parity and overflow status. Programmers can take advantage of 128
software flags to keep track of operating modes, resource usage, and so forth.
The Boolean instructions are also the most efficient
way to control or reconfigure peripheral and I/O registers. All 32 I/O lines become "test pins," for example,
tested by conditional jump instructions. Any output pin
can be toggled (complemented) in a single instruction
cycle. Setting or clearing the Timer Run flags (TRO and
TRI) tum the timer/counters on or off; polling the
same flags elsewhere lets the program determine if a
timer is running. The respective overflow flags (TFO
and TFI) can be tested to determine when the desired
period or count has elapsed, then cleared in preparation
for the next repetition. (For the record, these bits are all
part of the TCON register, Figure 7a. Thanks to symbolic bit addressing, the programmer only needs to remember the mnemonic associated with each function.
In other words, don't bother memorizing control word
layouts.)
In the MCS-48 family, instructions corresponding to
some of the above. functions require specific opcodes.
Ten different opcodes serve to clear complement the
software flags FO and Fl, enable/disable each interrupt, and start/stop the timer. In the 8051 instruction
set, just three opcodes (SETB, CLR, CPL) with a direct
bit address appended perform the same functions. Two
test instructions (JB and JNB) can be combined with
bit addresses to test the software flags, the 8048 I/O
pins TO, TI, and INT, and the eight accumulator bits,
replacing 15' more different instructions.
Table 4a shows how 8051 programs implement software flag and machine control functions associated
with special opcodes in the 8048. In every case the
MCS-51 solution requires the same number of machine
cycles, and executes 2.5 times faster.

ADDC A,@Ri

ADDC A,#data
SUBB A,Rn

SUBB A,direct
SUBB A,@Ri
SUBB A,#data

MUL
DIV
DA

AB
AB
A

RLC

A

RRC

A

CJNE A,direct.rel

Description

Add register to
Accumulator
Add direct byte to
Accumulator
Add indirect RAM to
Accumulator
Add immediate data
to Accumulator
Add register to
Accumulator with
Carry flag
Add direct byte to
Accumulator with
Carry flag
Add indirect RAM to
Accumulator with
Carry flag
Add immediate data
to Acc with Carry flag
Subtract register from
Accumulator with
borrow
Subtract direct byte
from Acc with borrow
Subtract indirect RAM
from Acc with borrow
Subtract immediate
data from Acc with
borrow
Multiply A & B
Divide A by B
Decimal Adjust
Accumulator

Byte eyc

1
2

2

2

2

2

2

4
4

Rotate Accumulator
Left through the Carry
flag
Rotate Accumulator
Right through Carry
flag

Compare direct byte
to Acc &Jump if. Not
Equal
CJNE A,#data.rel
Compare immediate
to Acc &Jump if Not
Equal
CJNE Rn,#data.rel Compare immed to
register &Jump if Not
Equal
CJNE @Ri,#data.rel Compare immed to
indirect & Jump if Not
Equal

3

2

3

2

3

2

3

2

All mnemonics copyrighted © Intel Corporation 1980.

10-221

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AP-70

Table 4a. Contrasting 8048 and 8051 Blt;Control and Testing Instructions
8048
Instruction

8x51
Instruction

Bytes

Cycles Be ""Sec

C
FO

1
2

1
1

JNC
JB
JB

rei
FO.rel
ACC.7.rel

2

3
3

2
2
2

5.0
5.0
5.0

JB
JNB
JBC

TO.rel
INTO.tel
TFO.rel

3
3
3

2
2
2

2.5
2.5
2.5

SETB
. SETB
CLR

TRO
EXO
ETO

2
2
2

1
1
1

Bytes

Cycles

""Sec

Flag Control
CLR
C
CPL
FO

1
1

1
1

2.5
2.5

CLR
CPL

Flag Testing
JNC
offset
JFO
offset
JB7
offset

2
2
2

2
2
2

5.0
5.0
5.0

Peripheral POlling
JTO
offset
JN1
offset
JTF
offset

2
2
2

2
2
2
1
1
1

Machine and Peripheral Control
STRT
T
1
EN
1
1
DIS
TCNT1
1

Table 4b. Replacing 8048 Instruction Sequences with Single 8x51 Instructions
8048
Instruction

Bytes

Cycles

""Sec

8051
Instruction

Bytes

Cycles Be ""Sec

Flag Control
Set carry
CLR
C
CPL
C

=

2

2

5.0

SETB

C

1

1

Set Software Flag
CLR
FO
CPL
FO

=

2

2

5.0

SETB

FO

2

1

Turn Off Output Pin
P1.#OFBH
ANL

=

2

2

5.0

CLR

P1.2

2

1

Complement Output Pin
IN
AP1
A#04H
XRL
OUTL P1.A

=

4

6

15.0

CPL

P1.2

2

1

Clear Flag
MOV
MOV
ANL
MOV

=

6

6

15.0

CLR

·USER_FLG

2

1

in RAM
RO.#FLGADR
A@RO
A#FLGMASK
@RO.A

10-222

AP-70

Table 4b Replacing 8048 Instruction Sequences with Single 8x51 Instructions (Continued)
8048
Instruction

8x51
Instruction

Bytes

Cycles & ,.,.Sec

FO.rel

3

2

JNB

ACC.7.rel

3

2

12.5

JNB

P1.3.rel

3

2

10.0

JB

INTO.rel

3

2

Cycles

,.,.Sec

Flag Testing:
Jump if Software Flag is 0
JFO
$+4
JMP
offset
= 4

4

10.0

JNB

Jump if Accumulator bit is 0
CPL
A
JB7
offset
CPL
A
= 4

4

10.0

Peripheral Polling
Test if Input Pin is Grounded
IN
A.P1
CPL
A
JB3
offset
= 4

5

Test if Interrupt Pin is High
$+4
JN1
JMP
offset
= 4

4

Bytes

3.0 BOOLEAN PROCESSOR
APPLICATIONS
So what? Then what does all this buy you?

Qualitatively, nothing. All the same capabilities could
be (and often have been) implemented on other machines using awkward sequences of other basic operations. As mentioned earlier, any CPU can solve any
problem given enough time.
Quantitatively, the differences· between a solution allowed by the 8051 and those required by previous architectures are numerous. What the S051 Family buys
you is a faster, cleaner, lower-cost solution to microcontroller applications.
The opcode space freed by condensing many specific
S04S instructions into a few general operations has been
used to add new functionality to the MCS-51 architecture-both for byte and bit operations. 144 software
flags replace the S04S's two. These flags (and the carry)
may be directly set, not just cleared and complemented,
and all can be tested for either state, not just one. Operating mode bits previously inaccessible may be read,
tested, or saved. Situations where the· 8051 instruction
set provides new capabilities are contrasted with S04S
instruction sequences in Table 4b. Here the S051 speed
advantage ranges from 5x to l5x!

Combining Boolean and byte-wide instructions can
produce great synergy. An MCS-5l based application
will prove to be:
• simpler to write since the architecture correlates
more closely with the problems being solved:
• easier to debug because more individual instructions
have no unexpected or undesirable side-effects:
• more byte efficient due to direct bit addressing and
program counter relative branching:
• faster running because fewer bytes of instruction
need to be fetched and fewer conditional jumps are
processed:
• lower cost because of the high level of system-integration within one component.
These rather unabashed claims of excellence shall not
go unsubstantiated. The rest of this chapter examines
less trivial tasks simplified by the Boolean processor.
The first three compare the S051 with other microprocessors; the last two go into S051-based system designs in much greater depth.

Design Example # 1-Bit Permutation
First off, we'll use the bit-transfer instructions to permute a lengthy pattern of bits.

10-223

intJ

AP-70

Different microprocessor architectures would best impement this type of permutation in different ways.
Most approaches would share the steps of Figure lOa:
• Initialize the Permutation Buffer to default state
(ones or zeroes):

A steadily increasing number of data communication
products use encoding methods to protect the security
of sensitive information. By law, interstate financial
transactions involving the Federal banking system must
be transmitted using the Federal Information Processing Data Encryption Standard (DES).

• Isolate the state of a bit of a byte from the Key
Buffer. Depending on the CPU, this might be accomplished by rotating a word of the Key Buffer
through a carry flag or testing a bit in memory or an
accumulator against a mask byte:
• Perform a conditional jump based on the carry or
zero flag if the Permutation Buffer default state is
correct:
• Otherwise reverse the corresponding bit in the permutation buffer with logical operations and mask
bytes.

Basically, the DES combines eight bytes of "plaintext"
data (in binary, ASCII, or any other format) with a 56bit "key", producing a 64-bit encrypted value for transmission. At the receiving end the same algorithm is
applied to the incoming data using the same key, reproducing the original eight byte message. The algorithm
used for these permutations is fixed; different user-defined keys ensure data privacy.
It is not the purpose of this note to describe the DES in
any detail. Suffice it to say that encryption/decryption
is a long, iterative process consisting of rotations, exclusive -OR operations, function table look-ups, and an
extensive (and quite bizarre) sequence of bit permutation, packing, and unpacking steps. (For further details
refer to the June 21, 1979 issue of Electronics magazine.) The bit manipulation steps are included, it is rumored, to impede a general purpose digital supercomputer trying to "break" the code. Any algorithm implementing the DES with previous generation microprocessors would spend virtually all of its time diddling
bits.

Each step above may require several instructions. The
last three steps must be repeated for all 48 bits. Most
microprocessors would spend 300 to 3,000 microseconds on each of the 16 iterations.
Notice, though, that this flow chart looks a lot like
Figure 8. The Boolean Processor can permute bits by
simply moving them from the source to the carry to the
destination-a total of two instructions taking four
bytes and three microseconds per bit. Assume the Shifted Key Buffer and Permutation Buffer beth reside.in
bit-addressable RAM, with the bits of the former assigned symbolic name~ SKB_l, SKB_2, ... SKB_
56, and that the bytes of the latter are named PB_I,
... PB_8. Then working from Figure 9, the software
for the permutation algorithm would be that of ExampIela. The total routine length would be 192 bytes,
requiring 144 microseconds.

The bit manipulation performed is typified by the Key
Schedule Calculation represented in Figure 9. This step
is repeated 16 times for each key used in the course of a
transmission. In essence, a seven-byte, 56-bit "Shifted
Key Buffer" is transformed into an eight-byte, "Permutation Buffer" without altering the shifted Key. The
arrows in Figure 9 indicate a few of the translation
steps. Only six bits of each byte of the Permutation
Buffer are used; the two high-order bits of each byte are
cleared. This means only 48 of the 56 Shifted Key Buffer bits are used in anyone iteration.

Permuted and Shifted 56-Bit Key Buffer
~

~

---------------------"--------------------- --------------------"--------------------14151111

PERMUTATION BYTE 1

PERM BYTE 2

21

PERM BYTE 3

2425

""

PERM BYTE 4

"

BYTE 5

3334

BYTE 6

PERM BYTE 7

PERM BYTE 8

203830-5
48-Bit Key KI

Figure 9. DES Key Schedule Transformation

10-224

inter

AP-70

SET PERMUTATION
BUFFER BIT
PC2(1)

(LEAVE PERMUTATION
BUFFER BIT
CLEARED)

REPEAT
FOR EACH
BIT OF
SHIFTED
KEY
BUFFER
(48 TIMES)

203830-6

Figure 10a. Flowchart for Key Permutation Attempted with a Byte Processor

10-225

Ap·70

I

~

I

CLEAR ACCUMULATOR

LOAD BIT MAPPED ONTO BIT 5 OF
PERMUTATION BYTE INTO CARRY

I

I

ROTATE LEFT INTO ACC.

LOAD BIT. MAPPED ONTO BIT 4
OF PERMUTATION BYTE INTO CARRY

I

I

ROTATE LEFT INTO ACC.

REPEAT'
FOR EACH
BYTE OF
PERMUTATION
BUFFER
(8 TIMES)

t

,
,
,

LOAD BIT MAPPED ONTO BIT 0
OF PERMUTATION BYTE INTO CARRY

I

I

. ROTATE LEFT INTO ACC.

STORE ACC. INTO PERMUTATION
BUFFER

I
I

203830-7

Figure 10b. DES Key Permutation With Boolean Processor

10-226

inter

AP-70

The algorithm of Figure lOb is just slightly more efficient in this time-critical application and illustrates the
synergy of an integrated byte and bit processor. The
bits needed for each byte of the Permutation Buffer are
assimilated by loading each bit into the carry (1 Jots.)
and shifting it into the accumulator (1 Jots.). Each byte
is stored in RAM when completed. Forty-eight bits
thus need a total of 112 instructions, some of which are
listed in Example lb.
Worst-case execution time would be 112 microseconds,
since each instruction takes a single cycle. Routine
length would also decrease, to 168 bytes. (Actually, in
the context of the complete encryption algorithm, each
permuted byte would be processed as soon as it is assimilated-saving memory and cutting execution time
by another 8 Jots.)
To date, most banking terminals and other systems using the DES have needed special boards or peripheral
controller chips just for the encryption/decryption process, and still more hardware to form a serial bit stream
for transmission '(Figure l1a). An 8051 solution could
pack most of the entire system onto the one chip (Figure 11b). The whole DES algorithm would require less
than one-fourth of the on-chip program memory, with
the remaining bytes free for operating the banking terminal (or whatever) itself.
Moreover, since transmission and reception of data is
performed through the on-board UART, the unencrypted data (plaintext) never even exists outside the
microcomputer! Naturally, this would afford a high degree of security from data interception.

10-227

Example 1. DES Key Permutation Software.
a.) "Brute Force" technique
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

C,SKB_l
PB_l.l, C
C,SKB_2
PB_4.0,C
C,SKB_3
PB_2.5,C
C,SKB_4
PB_l. 0, C

MOV
MOV
MOV
MOV

C,SKB_55
PB_5.0,C
C,SKB_56
PB_7.2,C

b.) Using Accumulator to Collect Bits
CLR
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
MOV

A
C,SKB_14
A
C,SKB_17
A
C, SKB_ll
A
C,SKB_24
A
C,SKB_l
A
C,SKB_5
A
PB_l,A

MOV
RLC
MOV
RLC
MOV

C,SKB_29
A
C,SKB_32
A
PB_8,A

inter

AP-70

l

CONTROL AND ADDRESS BUSSES

I

I

DISPLAY

CPU

RAM

DATA
ENCRY·
PTION
UNIT

ROM

KEYBOARD

TO
MODEM

UART

I
I
J

SYSTEM DATA BUS

203830-8

a.) Using Multi-Chip Processor Technology

~DISPL_AY----JK'--------ll~
TAO

•

8051
PO

R.D

-y

I ..

TO
MODEM

KEYBOARD
~

P1
I'll

203830-9

b.) Using One Single-Chip Microcomputer
Figure 11. Secure Banking Terminal Block Diagram

Design Example # 2-5oftware
Serial 1/0
An exercise often imposed on beginning microcomputer students is to write a program simulating a UART.
Though doing this with the 8051 Family may appear to
be a moot point (given that the hardware for a full
UART is on-chip), it is still instructive to see how it
would be done, and maintains a product line tradition.
As it turns out, the 8051 microcomputers can receive or
transmit serial data via software very efficiently using
the Boolean instruction set. Since any I/O pin may be a
serial input or output, several serial links could be
maintained at once.

Figures 12a and 12b show algorithms for receiving or
transmitting a byte of data. (Another section of program would invoke this algorithm eight times, synchronizing it with a start bit, clock signal, software delay, or
timer interrupt.) Data is received by testing an input
pin, setting the carry to. the same state, shifting the
carry into a data buffer, and saving the partial frame in
internal RAM. Data is transmitted by shifting an output. buffer through the carry, and generating each bit
on an output pin.
A side-by-side comparison of the software for this common "bit-banging" application with three different microprocessor architectures is shown in Table Sa and 5b.
The 8051 solution is more efficient than the others on
every count!

10-228

AP-70

PIN = 1

CLEAR CARRY

SET CARRY

203830-10

a.) Reception

203830-11

b.) Transmission
Figure 12. Serial 110 Algorithms

10-229

intJ

AP-70

Table 5. Serial 1/0 Programs for Various Microprocessors
a.) Input Routine.

8085
1:-1
A>,; I
.r!.
CMC
1.0: LXI
MOV
RR
MOV

8048
SERI'ORT
MASK
1.0

8051

CI.R C
.I>,;TO 1.0
CI'I.
C
MOV RO.RSFR8l'~
MOV A.@RO
RRC A
MOV @RIl.A

HI..SERBlJF
A.M
M.A

MOV

C.SERPI"

MOV
RRC
MOV

A
SERBl'r.A

A.SERBl:~

RESUlTS:
K I"STRl:CTIO-';S
14 BYTES
5b STATES
19 uSEC

22.5 uSF.e.

41>,;STRl'CTIO>,;S
7 BYTES
4 CYCLES
4 uSEC

8048

8051

71>,;STRlTTIO:-lS
9 BYTES
9 CYCI.F.S

h.) Output Routine.

8085
LXI
MOV
RR
MOV
1-';

.Ie
1.0: A>,; I
.IMP
HI: ORI
CII;T:OlIT

Mov

HI..SERBlI~

RO .• SERBllF
MOV A.@RO
RRC A
MOV @RO.A

A.M
M.A
SERPORT
HI
:-lOT MASK
C:-IT
MASK

HI:

SfRl'ORT

CST:

.Ie
A>,; I.
.IMP
ORI.

HI
SERPRT.R"OT MASK

MOV
RRC
MOV

SERBl'F.A

A.SE R Bl' F

MOV

SfRPI".C

A

C~T

SERPRT.RMASK

RESlILTS:
10lNSTRlJCTI0II;S
20 BYTES
72 STATES
24 uSEC

K Ii'iSTRlJCTIONS
13 BYTES
II CYCLES
27.5 uSEC

4 INSTRlJCTlONS
7 BYTES
5 CYCI.ES
5 uSEC

203830-30

Figure 13 shows TTL and' relay logic diagrams for a
function of the six variables U through Z. Each is a
solution of the equation.

Design Example # 3-Combinatorial
Logic Equations
Next we'll look at some simple uses for bit-test instructions and logical operations. (This example is also presented in Application Note AP-69.)
Virtually all hardware IJesigners have solved complex
functions using combinatorial logic. While the hardware involved may vary from relay logic, vacuum
tubes, or TTL or to more esoteric technologies like fluidics, in each case the goal is the same: to solve a problem represented by a logical function of several Boolean
variables.

Q =

(Ue(V

+ W» + (XeV) + Z

Equations of this sort might be reduced using Karnaugh Maps or algebraic techniques, but that is not the
purpose of this example. As the logic complexity increases, so does the difficulty of the reduction process.
Even a minor change to the function equations as the
design evolves wOjlld require tedious re-reduction from
scratch.

10-230

infef

AP-70

u

v
W ----L__'''

x

}----o

y

z
Q = (U • (V

203830-12

+ W)) + (x. Y) + Z

a.) Using TTL
v
u

x

y

CRI

CR2

o

z

203830-13

. b.) Using Relay Logic
Figure 13. Hardware Implementations of Boolean Functions
For the sake of comparison we will implement this
function three ways, restricting the software to three
proper subsets of the MeS·51 instruction set. We will
also assume that U and V are input pins from different
input ports, Wand X are status bits for two peripheral
controllers, and Y and Z are software flags set up earli·
er in the program. The end result must be written

to an output pin on some third port. The first two implementations follow the flow-chart shown in Figure
14. Program flow would embark on a route down a
test-and-branch tree and leaves either the "True" or
"Not True" exit ASAP-as soon as the proper result
has been determined. These exits then rewrite the output port with the result bit respectively one or zero.

10-231

AP-70

The code which results is cumbersome and error prone.
It would be difficult to prove whether the software
worked for all input combinations in programs of this
sort. Furthermore, execution time will vary widely with
input data.
Thanks to the direct bit-test operations, a single instruction can replace each move mask conditional jump
sequence in Example 2a, but the algorithm would be
equally convoluted (see Example 2b). To lessen the
confusion "a bit" each input variable is assigned a sym. bolic name.
A more elegant and efficient implementation (Example
2c) strings together the Boolean ANL and ORL functions to generate the output function with straight-line
code. When finished, the carry flag contains the result,
which is simply copied out to the destination pin. No
flow chart is needed-code can be written directly from
the logic diagrams in Figure 14. The result is simplicity
itself: fast, flexible, reliable, easy to design, and easy to
debug.

FUNCTION
IS FALSE

An 8051 program can simulate an N-input AND or
OR gate with at most N + 1 lines of source programone for each input and one line to store the results. To
simulate NAND and NOR gates, complement the carry after computing the function. When some inputs to
the gate have "inversion bubbles", perform the ANL or
ORL operation on inverted operands. When the first
input is inverted, either load the operand into the carry .
and then complement it, or use DeMorgan's Theorem
to convert the gate to a different form.

FUNCTION
IS TRUE

Example 2. Software Solutions to Logic Function of
Figure 13.

CLEAR 0

203830-14

Figure 14. Flow Chart for
Tree-Branching Algorithm
Other digital computers must solve equations of this·
type with standard word-wide logical iristructions and
conditional jumps. So for the first implementation, we
won't use any generalized bit-addressing instructions.
As we shall soon see, being constrained to such an instruction subset produces somewhat sloppy software
solutions. MCS-51 mnemonics are used in Example 2a:
other machines might further cloud the situation by
requiring operation-specific mnemonics like INPUT,
OUTPUT, LOAD, STORE, etc., instead of the MOV
mnemonic used for all variable transfers in the 8051
instruction set.

10-232

a.) Using only byte-wide logical instructions
'BFUNCI SOLVE, RANDOM LOGIC
FUNCTION OF 6 VARIABLES
BY LOADING AND MASKING
THE APPROPRIATE BITS IN
THE ACCUMULATOR. THEN
EXECUTING CONDITIONAL
JUMPS BASED ON ZERO
CONDITION. (APPROACH USED
BY BYTE-ORIENTED
ARCHITECTURES.) BYTE AND
MASK VALUES CORRESPOND TO
RESPECTIVE "BYTE ADDRESS
AND BIT POSI;rIONS •.

OUTBUF DATA 22H
.;OUTPUT PIN STATE MAP

inter
TESTV:

TESTU:
TESTX:

TESTZ:
CLRQ.:
SETQ.:
OUTQ.:

Ap·70

MOV
ANL
JNZ
MOV
ANL
JZ
MOV
ANL
JNZ
MOV
ANL
JZ
MOV
ANL
JZ
MOV
ANL
JZ
MOV
ANL
JMP
MOV
ORL
MOV
MOV

A,P2
A,#OOOOOIOOB
TESTU
A,TCON
A,#OOIOOOOOB
TESTX
A,PI
A,#OOOOOOIOB
SETQ.
A,TCON
A,#OOOOIOOOB
TESTZ
A,20H
A,#OOOOOOOIB
SETQ.
A,2lH
A,#OOOOOOIOB
SETQ.
A,OUTBUF
A,#IIIIOIIIB
OUTQ.
A,OUTBUF
A,#OOOOIOOOB
OUTBUF,A
P3,A

U
V
W
X
Y
Z
Q.

BIT
BIT
BIT
BIT
BIT
BIT
BIT

PI.I
P2.2
TFO
lEI
20H.0
2IH.I
P3.3

TEST_V: JB
V,TEST_U
JNB
W,TEST_X
TEST_U: JB
U,SET_Q.
TEST_X: JNB
X,TEST_Z
JNB
Y,SET_Q.
TEST_Z: JNB
Z,SET_Q.
CLR_Q.: CLR
Q.
JMP
NXTTST
SET_Q.: SETB Q.
NXTTST:(CONTINUATION OF
:PROGRAM)
c.) Using logical operations on Boolean variables

:FUNC3 SOLVE A RANDOM LOGIC
FUNCTION OF 6 VARIABLES
USING STRAIGHT __ LINE
LOGICAL INSTRUCTIONS ON
MCS-51 BOOLEAN VARIABLES.

b.) Using only bit-test instructions

:BFUNC2 SOLVE A RANDOM LOGIC
FUNCTION OF 6 VARIABLES
BY DIRECTLY POLLING EACH
BIT. (APPROACH USING
MCS-51 UNIQ.UE BIT-TEST
INSTRUCTION CAPABILITY.)
SYMBOLS USED IN LOGIC
DIAGRAM ASSIGNED TO
CORRESPONDING 'Sx51 BIT
ADDRESSES.

MOV
ORL
ANL
MOV
MOV
ANL
ORL
ORL

C,V
C,W
C,U
FO,C
C,X
C,Y
C,FO
C,Z

MOV Q.,C

10-233

;OUTPUT OF OR GATE
;OUTPUT OF TOP AND GATE
;SAVE INTERMEDIATE STATE
;OUTPUT OF BOTTOM AND GATE
:INCLUDE VALUE SAVED ABOVE
:INCLUDE LAST INPUT
:VARIABLE
:OUTPUT COMPUTED RESULT

intJ

AP-70

An upper-limit can be placed on the complexity of software to simulate a large number of gates by summing
the total number of inputs and outputs. The actual total
should be somewhat shorter, since calculations can be
"chained," as shown. The output of one gate is often
the first input to another; bypassing the intermediate
variable to eliminate two lines of source.

Design Example # ~Automotlve
Dashboard Functions
Now let's apply these techniques to designing the soft.
ware for a complete controller system. This application
is patterned after a familiar real-world application
which isn't nearly as trivial as it might first appear:
automobile tum signals.

Imagine the three position tum lever on the steering
column as a single-pole, triple-throw toggle switch. In
its central position all contacts are open. In the up or
down positions contacts close Causing corresponding
lights in the rear of the car to blink. So far very simple.
Two more tum signals blink in the front ofthe car, and
two others in the dashboard. All six bulbs flash when
an emergency switch is closed; A thermo-mechanical
relay (accessible under the dashboard in case it wears
out) causes the blinking.
Applying the brake pedal turns the tail light filaments
on constantly ... unless a tum is in progress, in which
case the blinking tail light is not affected. (Of course,
the front tum signals and dashboard indicators are not
affected by the brake pedal.) Table 6 summarizes these
operating modes.

Table 6. Truth Table for Turn-Signal Operation
Output Signals

Input Signals
Left
Turn
Switch

Right.
Turn
Switch

Left .
Front
& Dash

Right
Front
& Dash

Off
Off

Off
Blink

Brake
Switch

Emerg.
Sw,ltch

0
0
0

0
0
0

0
0
1

0
1
0

0
0
0

1
1
1

0
0
1

0
1
0

1
1
1

0
0
0

0
0
1

0
1
0

1
1
1

1
1
1

0
0
1

0
1
0

10-234

Left
Rear

Right
Rear

Off

Off
Blink

Blink

Off

Off
Blink

Blink
Blink
Blink
Off
Off
Blink
Blink
Blink
Blink

Blink
Blink
Blink
Off
Blink
Off
Blink
Blink
Blink

Blink
Blink
Blink
On
On
Blink
On
On
Blink

Off·

Blink
Blink
Blink
On
Blink
On
On
Blink
On

inter

AP-70

But we're not done yet. Each of the exterior turn signal
(but not the dashboard) bulbs has a second, somewhat
dimmer filament for the parking lights. Figure 15
shows TTL circuitry which could control all six bulbs.
The signals labeled "High Freq." and "Low Freq." represent two square-wave inputs. Basically, when one of
the turn switches is closed or the emergency switch is
activated the low frequency signal (about 1 Hz) is gated
through to the appropriate dashboard indicator(s) and
turn signal(s). The rear signals are also activated when
the brake pedal is depressed provided a turn is not being made in the same direction. When the parking light
switch is closed the higher frequency oscillator is gated
to each front and rear turn signal, sustaining a low-intensity background level. (This is to eliminate the need
for additional parking light filaments.)
In most cars, the switching logic to generate these functions requires a number of multiple-throw contacts. As
many as 18 conductors thread the steering column of
some automobiles solely for turn-signal and emergency
blinker functions. (The author discovered this recently
to his astonishment and dismay when replacing the
whole assembly because of one burned contact.)
A multiple-conductor wiring harness runs to each corner of the car, behind the dash, up the steering column,
and'down to the blinker relay below. Connectors at

each termination for each filament lead to extra cost
and labor during construction, lower reliability and
safety, and more costly repairs. And considering the
system's present complexity, increasing its reliability or
detecting failures would be quite difficult.
There are two reasons for going into such painful detail
describing this example. First, to show that the messiest
part of many system designs is determining what the
controller should do. Writing the software to solve
these functions will be comparatively easy. Secondly, to
show the many potential failure points. in the system.
Later we'll see how the peripheral functions and intelligence built into a microcomputer (with a little creativity) can greatly reduce external interconnections and
mechanical part count.

The Single-Chip Solution
The circuit shown in Figure 16 indicates five input pins
to the five input variables-left-turn select, right-turn
select, brake pedal down, emergency switch on, and
parking lights on. Six output pins turn on the front,
rear, and dashboard indicators for each side. The microcomputer implements all logical functions through
software, which periodically updates the output signals
as time elapses and input conditions change.

L. TURN

r---....- - - - - -

EMERG

L. DASH

L. FRNT

BRAKE

L. REAR

R. TURN

r---....+-----

R. DASH

R. FRNT

R.REAR

PARK

LO.
FREO.
OSCILLATOR

HI.
FREO.
OSCILLATOR

Figure 15. TTL Logic Implementation of Automotive Turn Signals
10-235

203830-15

intJ

AP-70

+12V
+12V

8051
:"

Pl.0

EMERGENCY
SWITCH

Pl.l

PARKING
LIGHTS

Pl.2

LEn
FRONT

Pl.S
RIGHT
FRONT

P1.I

LEn
DASHBOARD

Pl.7

RIGHT
DASHBO.ARD

Pl.3
TURN
SWITCH

P2.0
P1.4

LEn
REAR

P2,1

RIGHT
REAR

PU

MODE
SENSORS

CONTROLLER

SIGNAL
CONDITIONING

OUTPUT
BUFFERS

SIGNAL
BULBS

203830-16

Figure 16. Microcomputer Turn-Signal Connections.
Design Example # 3 demonstrated that symbolic addressing with user-defined bit names makes code and
documentation easier to write and maintain. Accordingly, we'll assign these I/O pins names for use
throughout the program. (The format of this example
will differ somewhat from the others. Segments of the
overall program will be presented in sequence as each is
described.)

INPUT PIN DECLARATIONS:
;(ALL INPUTS ARE POSITIVE-TRUE LOGIC)
BRAKE

BIT .Pl.O .;BRAKE PEDAL
;DEPRESSED
EMERG BIT Pl.l ;EMERGENCY BLINKER
;ACTIVATED
PARK BIT Pl.2 ;PARKING LIGHTS ON
I_TURN BIT Pl.3 ;TURN LEVER DOWN
R_TURN BIT Pl.4 ;TURN LEVER UP
OUTPUT PIN DECLARATIONS:
I_FRNT BIT Pl.5 ;FRONT LEFT-TURN
;INDICATOR
R_FRNT BIT Pl.6 ;FRONT RIGHT-TURN
;INDICATOR
I_DASH .BIT Pl.7 ;DASHBOARD LEFT-TURN
;INDICATOR

R_DASH BIT P2.0 ;DASHBOARD RIGHT;TURN INDICATOR
I_REAR BIT P2.1 ;REAR LEFT-TURN
;INDICATOR
R_REAR BIT P2.2 ;REAR RIGHT-TURN
;INDICATOR

Another key advantage of symbolic addressing will appear further on in the design cycle. The locations of
cable connectors, signal conditioning. circuitry, voltage
regulators, heat sinks, and the like all affect P.C. board
layout. It's quite likely that the somewhat arbitrary pin
assignment defined early in- the software design cycle
will prove to be less than optimum; rearranging the I/O
pin assignment could well allow a more compact module, or eliminate Costly jumpers on a single-sided board.
(These considerations apply especially to automotive
and other cost-sensitive applications needing singlechip controllers.) Since other architectures mask bytes
or use "clever" algorithms to isolate bits by rotating
them into the carry, re-routing an input signal (from bit
I of port 1, for example, to bit 4 of port 3) could require
extensive modifications throughout the software.
The Boolean Processor's direct bit addressing makes
such changes absolutely trivial. The number of the port
containing the pin is irrelevent, and masks and complex

10-236

AP-70

program structures are not needed. Only the initial
Boolean variable declarations need to be changed;
ASM5l automatically adjusts all addresses and symbolic references to the reassigned variables. The user is
assured that no additional debugging or software verification will be required.

;INTERRUPT RATE SUBDIVIDER
SUB_DIV
DATA
20H
;HIGH-FREQUENCY OSCILLATOR BIT
HI_FREQ
BIT
SUB_DIV,O
:LOW-FREQUENCY OSCILLATOR BIT
LO_FREQ
BIT
SUB_DIV,7
JMP

ORG
INIT

"tuned" to approximately I Hz for the tum- and emergency-indicator blinking rate.
Loading THO with -16 will cause an interrupt after
4.096 ms. The interrupt service routine reloads the
high-order byte of timer 0 for the next interval, saves
the CPU registers likely to be affected on the stack, and
then decrements SUB_DIY. Loading SUB_DIY.
with 244 initially and each time it decrements to zero
will produce a 0.999 second period for the highest-order bit.

ORG
MOV
PUSH
PUSH
PUSH
DJNZ
MOV

OOOOH

ORG
IOOH
;PUT TIMER 0 IN MODE I
INIT;
MOV
TMOD,#OOOOOOOIB
:INITIALIZE TIMER REGISTERS
MOV
TLO,#O
MOV
THO,#-16
;SUBDIVIDE INTERRUPT RATE BY 244
MOV
SUB_DIV,#244
:ENABLE TIMER INTERRUPTS
SETB
ETO
:GLOBALLY ENABLE ALL INTERRUPTS
SETB
EA
;START TIMER
SETB
TRO

OOOBH ;TIMER 0 SERVICE VECTOR
THO,#-16
PSW
ACC
B
SUB_DIV,TOSERV
SUB_DIV,#244

The code to sample inputs, perform calculations, and
update outputs-the real "meat" of the signal controller algorithm-may be performed either as part of the
interrupt service routine or as part of a background
program loop. The only concern is that it must b'e executed at least serveral dozen times per second to prevent parking light flickering. We will assume the for~
mer case, and insert the code into the timer 0 service
routine.
First, notice from the logic diagram (Figure 15) that
the subterm (PARK. H_FREQ), asserted when the
parking lights are to be on dimly, figures into four of
the six output functions. Accordingly, we will first
compute that term and save it in a temporary location
named· "DIM". The PSW contains two general purpose
flags: FO, which corresponds to the 8048 flag of the
same name, and PSW.1. Since the PSW has been saved
and will be restored to its previous state after servicing
the interrupt, we can use either bit for temporary storage.

;(CONTINUE WITH BACKGROUND PROGRAM)
;PUT TIMER 0 IN MODE I
;INITIALIZE TIMER REGISTERS
;SUBDIVIDE INTERRUPT RATE BY 244
;ENABLE TIMER INTERRUPTS
;GLOBALLY ENABLE ALL INTERRUPTS
;START TIMER

DIM BIT
Timer 0 (one of the two on-chip timer counters) replaces the thermo-mechaniCal blinker relay in the dashboard controller. During system initialization it is configured as a timer in mode I by setting the least significant bit of the timer mode register (TMOD). In this
configuration the low-order byte (fLO) is incremented
every machine cycle, overflowing and incrementing the
high-order byte (THO) every 256 /Ls. Timer interrupt 0
is enabled so that a hardware interrupt will occur each
time THO overflows.
An eight-bit variable in the bit-addressable RAM array
will be needed to further subdivide the interrupts via
software. The lowest-order bit of this counter toggles
very fast to modulate the parking lights: bit 7 will be

PSW.I ;DECLARE TEMP
:STORAGE FLAG

MOV C,PARK
ANL HLFREQ
MOV DIM,C

:GATE PARKING
;LIGHT SWITCH
;WITH HIGH
;FREQUENCY
;SIGNAL
;AND SAVE IN
:TEMP. VARIABLE

This simple three-line section of code illustrates are"
markable point. The software indicates in very abstract
terms exactly what function is being performed, inde-

10-237

Ap·70
pendent of the hardware· configuration. The fact that
these three bits include an input pin, a bit within a
program variable, and a software flag in the PSW is
totally invisible to the programmer.

ORL C,DIM
MOV L_REAR, C

Now generate and output the dashboard left turn signal.

MOV C,L_TURN
ORL C,EMERG
. ANL C, LO_FREQ
MOV LDASH,C

Now we have to go through a similar sequence for the
right-hand equivalents to all the left-turn lights. This
also gives us a chance to see how the code segments
above look when combined.

;SET CARRY IF
;TURN
;OR EMERGENCY
; SELECTED
;GATE IN 1 HZ
;SIGNAL
;AND OUTPUT TO
;DASHBOARD

MOV C.R_TURN
ORL C.EMERG
ANL C,LO_FREQ
MOV R_DASH.C

To generate the left front turn signal we only need to
add the parking light function in FO. But notice that the
function· in the carry will also be needed for the rear
signal. We can save effort later by saving its current
state in FO.

MOV.FO.C
ORL C.DIM
MOV R_FRNT.C

MOV FO.C

MOV C.BRAKE

;SAVE FUNCTION
;SO FAR

ORL C,DIM
MOV L_FRNT.C

ANL C. R_ TURN

;ADD IN PARKING
;LIGHT FUNCTION
;AND OUTPUT TO
;TURN SIGNAL

ORL C.FO
ORL C.DIM

Finally, the rear left turn signal should also be on when
.the brake pedal is depressed, provided a left turn is not
in progress.
MOV C,BRAKE
ANL C,L_TURN
ORL C,FO

7
X

6
X

X
X
X
X
X
X
X

X
X
X

X
X

X
X

;GATE BRAKE
;PEDAL SWITCH
;WITH TURN
;LEVER
;INCLUDE TEMP.
;VARIABLE FROM.DASH

Sub_Dlv Bits
5
4
3
2
X X X 0
X X X 0
X X X 0
X X X 0
X X X 1
X X X 1
X X X 1
X X X 1

1
0
0
1
1
0
0
1
1

;AND PARKING
;LIGHT FUNC.TION
;AND OUTPUT TO
;TURN SIGNAL

MOV R_REAR.C

;SET CARRY H; TURN
;OR EMERGENCY
;SELECTED
;IF SO. GATE IN 1
;HZ SIGNAL
;AND OUTPUT TO
;DASHBOARD
;SAVE FUNCTION
;SO FAR
;ADD IN PARKING
.;LIGHT FUNCTION
;AND OUTPUT TO
;TURN SIGNAL
;GATE BRAKE
;PEDAL SWITCH
;WITH TURN
;LEVER
;INCLUDE TEMP.
;VARIABLE FROM
;DASH
;AND PARKING
;LIGHT FUNCTION
;AND OUTPUT TO
;TURN SIGNAL

(The perceptive reader may notice that simply rearranging the steps could eliminate one instruction from
each sequence.)
Now that all six bulbs are in the proper states, we can
return from the interrupt routine, and the program is
finished. This code essentially· needs to reverse the
status saving steps at the beginning of the interrupt.

Table 7 Non-Trivial Duty Cycles
Duty Cycles
12.5% 25.0%
37.5% 50.0%
62.5%
0
Off
Off
0
Off
Off
Off
Off
1
Off
Off
Off
Off
0
Off
Off
Off
Off
Off
1
Off
Off
Off
Off
On
Off
0
Off
Off
On
On
1
Off
Off
On
On
On
On
0
Off
On
On
On
1
On
On
On
On
On
10-238

75.0%

87.5%

Off
Off
On
On
On
On
On
On

Off
On
On
On
On
On
On
On

AP-70

POP

B

driver circuits combining shift-register inputs with high
drive level outputs have been introduced recently.

;RESTORE CPU
;REGI STERS.

POP ACC
POP PSW
RETI

Cascading multiple shift registers end-to-end will expand the number of outputs even further. The data rate
in the I/O expansion mode is one megabaud, or 8 /.I.s.
per byte. This is the mode which the serial port defaults
to following a reset, so no initialization is required.

Program Refinements. The luminescence of an incandescent light bulb filament is generally non-linear: the
50% duty cycle of HI_FREQ may not produce the
desired intensity. If the application requires, duty cycles of 25%, 75%, etc. are easily achieved by ANDing
and ORing in additional low-order bits of SUB_DIY.
For example, 30 H/ signals of seven different duty cycles could be produced by considering bits 2-0 as
shown in Table 7. The only software change required
would be to the code which sets-up variable DIM;

The software for this technique uses the B register as a
"map" corresponding to the different output functions.
The program manipulates these bits instead of the output pins. After all functions have been calculated the B
register is shifted by the serial port to the shift-register
driver. (While some outputs may glitch as data is shifted through them, at 1 Megabaud most people wouldn't
notice. Some shift registers provide an "enable" bit to
hold the output states while new data is being shifted
in.)
This is where the earlier decision to address bits symbolically throughout the program is going to payoff.
This major I/O restructuring is nearly as simple to implement as rearranging the input pins. Again, only the
bit declarations need to be changed.

MOV C,SUB_DIV.l;START WITH 50
;PERCENT
ANL C,SUB_DIV.O;MASK DOWN TO 25
;PERCENT
ORL C,SUB_DIV.2;AND BUILD BACK TO
;62 PERCENT
MOV DIM,C
;DUTY CYCLE FOR
;PARKING LIGHTS.

LFRNT BIT B.O ;FRONT LEFT-TURN
;INDICATOR
R_FRNT BIT B.l ;FRONT RIGHT-TURN
;INDICATOR
LDASH BIT B.2 ;DASHBOARD LEFT-TURN
;INDICATOR
R_DASH BIT B.3 ;DASHBOARD RIGHT-TURN
;INDICATOR
LREAR BIT B.4 ;REAR LEFT-TURN
;INDICATOR
R_REAR BIT B.5 ;REAR RIGHT-TURN
;INDICATOR

Interconnections increase cost and decrease reliability.
The simple buffered pin-per-function circuit in Figure
16 is insufficient when many outputs require higherthan-TTL drive levels. A lower-cost solution uses the
8051 serial port in the shift-register mode to augment
I/O. In mode 0, writing a byte to the serial port data
buffer (SBUF) causes the data to be output sequentially
through the "RXD" pin while a burst of eight clock
pulses is generated on the "TXD" pin. A shift register
connected to these pins (Figure 17) will load the data
byte as it is shifted out. A number of special peripheral

+ 12V

8051

P3.0

r--------"'i

~ATA

P3.1

1 - - - -......,

eLK

05

07

8·BIT SHIFT REGISTER

203830-17

Figure 17. Output Expansion Using Serial Port

10-239

AP-70

The original program to compute the functions need
not change. After computing the output variables, the
control map is transmitted to the buffered shift register
through the serial port.

MOV SBUF,B ;LOAD BUFFER AND TRANSMIT
The Boolean Processor solution holds a number of advantages over older methods. Fewer switches are required. Each is simpler, requiring fewer poles and lower
current contacts. The flasher relay is eliminated entirely. Only six filaments are driven, rather than 10. The
wiring harness is therefore simpler and less expensive-one conductor for each of the six lamps and each of the
five sensor switches. The fewer conductors use far fewer connectors. The whole system is more reliable.
And since the system is much simpler it would be feasible to implement redundancy and or fault detection on
the four main turn indicators. Each could still be a

standard double filament bulb, but with the filaments
driven in parallel to tolerate single-element failures.
Even with redundancy, the lights will eventually fail.
To handle this inescapable fact current or voltage sensing circuits on each main drive wire can verify that
each bulb and its high-current driver is functioning
properly. Figure 18 shows one such circuit.
Assume all of the lights are turned on except one: i.e.,
all but one of the collectors are grounded. For the bulb
which is turned off, if there is continuity from + l2V
through the bulb base and filament, the control wire, all
connectors, and the P.C. board traces, and if the transistor is indeed not shorted to ground, then the collector will be pulled to + l2V. This turns on the base of
Q8 through the corresponding resistor, and grounds the
input pin, verifying that the bulb circuit is operational.
The continuity of each circuit can be checked by software in this ~ay.
+12V

WIRING
HARNESS

I

.. ·1

(Q 1

A

®
17\\

1

Pl.6

Pl.7

P2.0

P2.l

P2.2

=
+5V

TO

203830-18

Figure 18

10-240

AP-70

Now turn all the bulbs on, grounding all the collectors.
Q7 should be turned off, and the Test pin should be
high. However, a control wire shorted to + 12V or an
open-circuited drive transistor would leave one of the
collectors at the higher voltage even now. This too
would turn on Q7, indicating a different type offailure.
Software could perform these checks once per second
by executing the routine every time the software counter SUB_DIY is reloaded by the interrupt routine.

DJNZ SUB_DIV,TOSERV
MOV SUB_DIV,#244
;RELOAD COUNTER
ORL Pl,#lllOOOOOB
;SET CONTROL
;OUTPUTS HIGH
ORL P2,#00000111B
CLR LFRNT
;FLOAT DRIVE
;COLLECTOR
JB TO ,FAULT
;TO SHOULD BE
;PULLED LOW
;PULL COLLECTOR
;BACK DOWN
CLR L_DASH
JB
TO ,FAULT
SETB L_DASH
CLR L_REAR
JB
TO ,FAULT
SETB L_REAR
CLR R_FRNT
JB. TO ,FAULT
SETB R_FRNT
CLR R_DASH
JB
TO ,FAULT
SETB R_DASH
CLR R_REAR
JB
TO ,FAULT
SETB R_REAR
;WITH ALL COLLECTORS GROUNDED. TO
SHOULD BE HIGH
;IF SO. CONTINUE WITH INTERRUPT
ROUTINE.
JB
TO , TOSERV
FAULT:
;ELECTRICAL
;FAILURE
;PROCESSING
;ROUTINE
;(LEFT TO
;READER'S
;IMAGINATION)
TOSERV:
;CONTINUE WITH
; INTERRUPT
. ;PROCESSING

The complete assembled program listing is printed in
Appendix A. The resulting code consists of 67 program
statements, not counting declarations and comments,
which assemble into 150 bytes of object code. Each pass
through the service routine requires (coincidently)
67 /Ls plus 32 /Ls once per second for the electrical test.
If executed every 4 ms as suggested this software would
typically reduce the throughput of the background program by less than 2%.
Once a microcomputer has been designed into a system,
new features suddenly become virtually free. Software
could make the emergency blinkers flash alternately or
at a rate faster than the turn signals. Turn signals could
override the emergency blinkers. Adding more bulbs
would allow multiple taillight sequencing and syncopation-true flash factor, so to speak.

Design Example # 5-Complex Control
Functions
Finally, we'll mix byte and bit operations to extend the
use of 8051 into extremely complex applications.
Programmers can arbitrarily assign I/O pins to input
and output functions only if the· total does not exceed
32, which is insufficient for applications with a very
large number of input variables. One way to expand the
number of inputs is with a technique similar to multi. plexed-keyboard scanning.
Figure 19 shows a block diagram for a moderately complex programmable industrial controller with the fol~
lowing characteristics:
•. 64 input variable sensors:
• 12 output signals:
• Combinational and sequential logic computations:
• Remote operation with communications to a host
processor via a high-speed full-duplex serial link:
• Two prioritized external interrupts:
• Internal real-time and time-of-day clocks.
While many microprocessors could be programmed to
. provide these capabilities with assorted peripheral support chips, an 8051 microcomputer needs no other integrated circuits!
The 64 input sensors are logically arranged as an 8x8
matrix. The pins of Port 1 sequentially enable each column of the sensor matrix: as each is enabled Port 0
reads in the state of each sensor in that column. An
eight-byte block in bit-addressable RAM remembers
the data as it is read in so that after each complete scan
cycle there is an internal map of the current state of all
sensors. Logic functions can then directly address the
elements of the bit map.

10-241

AP-70

+ 5V

r-

It
12M~Z

~

~

,

XTAL1

VCC RST

XTAL2

-

INTO

RXD

SERIAL \
LINK

8051

\
8

16 24 32 40 48 56

PO.O

57

PO.1

1

ASYNCHRONANS
INTERRUPTS

INT1

TXD

RETURN
LINES
0

1.0uF

P3.4
P3.5
P3.6

58

2

'3-

-4

"5-

8.8
SENSOR
MATRIX

- I-rsg

PO.2

60

PO.4

61

PO.5

62

PO.6

PH
PO.3
P2.0
P2.1

6
7

15 23

PO,]

31 39 47. 55 63

I

MACHINE
ACTUATORS

P2.2
P2.3

t

P2.4
~

P1.0

P2.5

P1.1

P2.6

P1.2

P2.7

P1.3
P1.4
P1.5

ALE

PSEN _ N . C .

P1.6

)..J

_ _ N.C.

P1.7
VSS

r

SCAN
LINES

EA

203830-19

Figure 19. Block Diagram of 54-Input Machine Controller

The computer's serial port is configured as a nine-bit
UART, transferring data at 17,000 bytes-per-second.
The ninth bit may distinguish between address and data
bytes.
The 8051 serial port can be configured to detect bytes
with the address bit set, automatically ignoring all others. Pins INTO and INTI are interrupts configured.respectively as high-priority, falling-edge triggered and
low-priority, low-level triggered. The remaining 12 I/O
pins output TTL-level control signals to 12 actuators.

There are several ways to implement the sensor matrix
circuitry, all logically similar. Figure 20a shows one
possibility. Each of the 64 sensors consists of a pair of
simple switch contacts in series with a diode to permit
multiple contact closures throughout the matrix.
The scan lines from Port 1 provide eight un-encoded
active-high scan signals for enabling columns of the
matrix. The return lines on rows where a contact is
closed are pulled high and read as logic ones. Open
return lines are pulled to ground by one of the 40 kn
resistors and are read as zeroes. (The resistor values
must be chosen to ensure all return lines are pulled
above the 2.0V logic threshold, even in the worst-case,

10-242

intJ

AP-70

where all contacts in an enabled column are closed.)
Since PO is provided open-collector outputs and highimpedance MOS inputs its input loading may be considered negligible.
The circuits in Figures 20b-20d are variations on this
theme. When input signals must be electrically isolated
from the computer circuitry as in noisy industrial environments, phototransistors can replace the switch diode
pairs and provide optical isolation as in Figure 20b.
Additional opto-isolators could also be used on the control output and special signal lines.

Example 3.

INPUT_SCAN:

MOV
MOV
MOV
SCAN; MOV

The other circuits assume that input signals are already
at TTL levels. Figure 20c uses octal three-state butTers
enabled by active-low scan signals to gate eight signals
onto Port o. Port 0 is available for memory expansion
or peripheral chip interfacing between sensor matrix
scans. Eight-to-one multiplexers in Figure 20d select
one of eight inputs for each return line as determined
by encoded address bits output on three pins of Port 1.
(Five more output pins are thus freed for more control
functions.) Each output can drive at least one standard
TTL or up to 10 low-power TTL loads without additional butTering.

RR
MOV
MOV
XCH
MOV

Going back to the original matrix circuit, Figure 21
shows the method used to scan the sensor matrix. Two
complete bit maps are maintained in the bit-addressable
region of the RAM: one for the current state and one
for the previous state read for each sensor. If the need
arises, the program could then sense input transitions
and or debounce contact closures by comparing each
bit with its earlier value.

INC
INC
MOV
JNB
RET

The code in Example 3 implements the scanning algorithm for the circuits in Figure 20a. Each column is
enabled by setting a single bit in a field of zeroes. The
bit maps are positive logic: ones represent contacts that
are closed or isolators turned on.

10-243

;SUBROUTINE TO READ
;CURRENT STATE
;OF 64 SENSORS AND
;SAVE IN RAM 20H-27H
;INITIALIZE
RO,#20H
;POINTERS
RI,#28H
;FOR BIT MAP
;BASES
A,#80H
;SET FIRST BIT
;IN ACC
PI,A
;OUTPUT TO SCAN
;LINES
;SHIFT TO ENABLE
A
;NEXT COLUMN
;NEXT
R2,A
;REMEMBER CUR;RENT SCAN
;POSITION
A,PO
;READ RETURN
;LINES
A,@RO
;SWITCH WITH
;PREVIOUS MAP
;BITS
;SAVE PREVIOUS
@RI,A
;STATE AS WELL
RO
;BUMP POINTERS
RI
A,R2
;RELOAD SCAN
;LINE MASK
ACC,7;SCAN;LOOP UNTIL ALL
;EIGHT COLUMNS
;READ

inter

AP-70

...

+5V

.

~

"0"

......
....J-

~

!

~~

+8x4K

8051

"56"

"8"

~~~

~~~

r-

f0-

RETURN
LINES

t---+---+---++-----_~ PO.O

"1"

~....LI-

--+----:r. I~

:

I

-

-+---.....--++----....4-.-1 PO.l

I-~f----:---t-+----.-t-t-I~ PO.2

t-'-t: :

---+----"- -+.-1-+ I
~_L~_ II III ~~~
~-~. - -S!z
I

:~::

::::

I-

PO.7

~----''----+-+---------4

Pl.0

'----:-------++--------1 Pl.l
'---------,--++----------4

Pl.2

'-----------++-----'----l Pl.3
'------------++--------l Pl.4
' - - - - - - - - - - - - - + + - - - - - - - 1 Pl.5
'--------------------4I-+---------l Pl.6
' - - - - - - - - - - - - - - - - - - - - - - + - l > . . - - - - - - - - 1 Pl.7
SCAN II
LINES

203830-20

a.) Using Switch Contact/Diode Matrix
Figure 20. Sensor Matrix Implementation Methods

10·244

AP-70

+SV

+8x4K

-

h
(~,*)

~

..-

()I¥~"

"0"

ll-

l

L-

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.......,

.-

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P"-

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po.o

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1

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(~'~"lS"

T"

r -

PO.l

PO.2
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1+1+'

b.-.rl

~

PO.3

I

PO.4

I

po.s
PO.6

.........
( ~K~"63"
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8x40K

PO.7

t;
Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.S
Pl.6

.:'

Pl.7
'

seA: ....
LINES

203830-21

b.) Using Optically-Coupled Isolators
Figure 20. Sensor Matrix Implementation Methods (Continued)

10·245

AP-70

nlnn!

11111111 Iitttttr
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C

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'--i-+_+_+-+_+_+_+_......-+-+-+-+-+-t-i--+_--<
D) •

INTERNAL VARIABLE DEFINI"rIONS:
SUB DIV DATA
HIJ"REG lilT
LO_FREG BIT

::::J,...
,...0

"'-IZ
OCe
CC
... _

OUTPUT PIN DECLARATIONS:
(ALL OUTPUTS ARE POSITIVI: TRUE LOGIC
BULB IS TURNED ON WHEN OUTPUT PIN IS HIGH.
L1RNT
R_FRNT
L_DASH
R,-DASH
L_REAR
R_REAR

0»
Oc

; =======:::========.==;=============::========:=============:===

$E.JECT

203830-26

~

'U

21

LOC

OD.J

0000 020040
OOOB
OOOD 7:18CFO
OOOE CODO
0010 0.154
0040
0040 758AOO
0043 7:18CFO
0046 758961
0049
004C
004E
0050
0052

7520F4
D2A9
D2AF
D2BC
BOFE

0054 D52038
0057 7520F4

.....

o

ro

(J1
t.)

005A
005D
0060
0062
0065
0067
0069
006C
006E
0070
0073
0075
0077
007A
007C'
007E
0081
00B3
00B5
0088

4390EO
43A007
C295
20D428
D295
C297
20D421
D297
C2Al
20B41A
D2Al
C296
20B413
D296
C2AO
20B40C
D2AO
C2A2
20B405
D2A2

LINE
49
:10
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
·66
67
68
·69
70
71
72
73
74
·75
76
-77
78
79
80
81
82
83
84
85
86
87
88
89
90
91

(

SOURCE

INIT:

UPDATE:

ORG
L.J.MP

OOOOH
INIT

RESET VECTOR

ORG
MOV
PUSH
A.JMP

OOOBH
THO •• -16
PSW
UPDATE

TIMER 0 SERVICE VECTOR
HIGH TIMER BYTE AD.JUSTED TO CONTROL INT RATE
EXECUTE CODE TO SAVE ANY REGISTERS USED BELOW
(CONTINUE WITH REST .OF ROUTINE)

ORG
MOV
MOV
MOV

0040H
TLO •• O
THO •• -16
TMOD •• OI10000IB

MOV
SETB
SETB
SETB
S.JMP

SUD_DIV •• 244
ETO
EA
TRO

D.JNZ
MOV.

SUD_DIV.TOSERV
SUB_DIV •• 244

ORL
ORL
CLR
.JD
SETB
CLR
.JB
SETB
CLR
.JB
SETB
CLR
.JB
SETB
CLR
.JB
SETB
CLR
.JB
SETB

Pl •• 11100000B
P2 •• 000pOll1B
LJRNT
TO. FAULT
L_FRNT
L_DASH
TO. FAULT
L_DASH
L_REAR
TO. FAULT
L_REAR
R_FRNT
TO. FAULT
RjRNT
R_DASH
TO. FAULT
R_DASH
R_REAR
TO. FAULT
R_REAR

S

ZERO LOADED INTO LOW-ORDER BYTE AND
-16 IN HIGH-ORDER BYTE GIVES 4 MSEC PERIOD
8-BIT AUTO RELOAD COUNTER MODE FOR TIMER 1.
16-BIT TIMER MODE FOR T'IMER 0 SELECTED
SUBDIVIDE INTERRUPT RATE BY 244 FOR I HZ
USE TIMER 0 OVERFLOWS TO INTERRUPT PROGRAM
CONFIGURE IE TO GLOBALLY ENABLE INTERRUPTS
KEEP INSTRUCTION CYCLE COUNT UNTIL OVERFLOW
START BACKGROUND PROGRAM EXECUTION
EXECUTE SYSTEM TEST ONLY ONCE PER SECOND
GET VALUE FOR NEXT ONE SECOND DELAY AND
GO THROUGH ELECTRICAL SYSTEM TEST CODE:
SET CONTROL OUTPUTS HIGH

»

l'

......

FLOAT DRIVE COLLECTOR
TO SHOULD BE PULLED LOW
PULL COLLECTOR BACK DOWN
REPEAT SEGUENCE FOR L __ DASH.

o

L REAR.
R_FRNT.
R_DASH.
AND R__REAR.

9;;1

008A 20B402
008D B2A3

93
94
95
96
97
98
99 +1

WITH ALL COLLECTORS GROUNDED. TO SHOULD BE HIGH
IF SO. CONTINUE WITH INTERRUPT ROUTINE.
FAULT_

.JB
CPL

TO. TOSERV
S_FAIL

ELECTRICAL FAILURE PROCESSING ROUTINE
(TOGGLE INDICATOR ONCE PEH SECOND)

SE.JECT
203830-27

LoC

OOBF
0091
0093
0095
0097

0099
009B
009D
009F

DB.!

A201
B200
7202
B292
92DI

A293
7291
B207
9297

LINE
100
101
102
103
104
105
lOb
107
lOB
109
110
III
112
113
114
115

--

SOURCE

II

CONTINUE WITH INTERRUPT I'RoCESSING:
II

COMPUTE LOW BULB INTENSITY WHEN PARKING LIGHTS ARE ON.

TOSERV: l'IOV
ANL
ORL
ANL
1'I0V
21

C.SUB_DIV I
C.SUB_DIV 0
C. SUB_DIV 2
C.PARK
DII'I.i;

cf

START WITH 50 PERCENT.
MASK ·DOWN TO 25· PERCENT.
BUILD BACK TO b2. 5 PERCENT.
GATE WITH PARKING LIGHT SWITCH.
AND SAVE IN TEMP. IIARIABLE.

COMPUTE AND OUTPUT LEFT~iAND DASHBOARD INDICATOR.
1'I0V
ORL
ANL
1'I0V

C. L_TURN
C.EI'IERG
C.Lo_FREG
L_DASH. C

SET CARRY IF TURN
OR EMERGENCY SELECTED.
IF SO. GATE IN I HZ SIGNAL
AND OUTPUT TO DASHBOARD.

lib

OOAI 92D5
00A3 72DI
00A5 9295

.....
9

I\)

....

U1

00A7
00A9
OOAB
OOAD
OOAF

A2'10
BO'13
72D5
72DI
92AI

0081
00B3
00B5
00B7
00B9
OOBB
OOBD
OOBF
OOCI
00C3
DOCS
·00C7

A294
7291
8207
92AO
92D5
72Dl

117
liB
119
120
121
122
123
124
125

31

l'IOV
ORL
l'IOV
41

51

FO.C
C.DII'I
L_FRNT. C

;

SAllE FUNCTION SO FAR.
ADD IN PARKING LIGHT FUNCTION
AND OUTPUT TO TURN .SIGNAL.

COMPUTE AND OUTPUT LEFT-liAND REAR TURN SIGNAL.
1'I0V
ANL
oRL
ORL
1'I0V

126

127
12B
129
130
131

COMPUTE AND OUTPUT LEFT-HAND FRONT TURN SIGNAL.

C.BRAKE
C./L_TURN
C.FO
C.DII'I
L_REAR. C

II

GATE BRAKE PEDAL SWITCH
WITH TURN LEVER.
INCLUDE TEMP. VARIABLE FROM DASH
AND PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.

REPEAT ·ALL OF ABOIIE FOR IUGHT-HAND COUNTERPARTS.

132

929b

A290
B094
72D5
72Dl
92A2

00C9 DODO
OOCB 32

133
134
135
13b
137
13B
139
140
141
142
143
144
145
14b
147
14B
149
150
!51

MOil
ORL
ANL
MOil
MOil
ORL
1'I0V
l'IOV
ANL
oRL
ORL
1'I0V·

C:R_TURN
C"-EI'IERG
C. LO_FREG
R_DASH. C
FO.C
C.DII'I
R_FRNT. C
C.BRAKE
C./R_TURN
C.FO
C.DII'I
R_REAR. C

SET CARRY IF ·TURN
OR EMERGENCY SELECTED.
IF SO; GATE IN I HZ SIGNAL
AND OUTPUT TO DASHBOARD.
SAVE FUNCTION SO FAR.
ADD IN PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
GATE BRAKE PEDAL SWITCH
WITH TURN LEVER.
INCLUDE TEMP. VARIABLE FROM DASI!
AND PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.

RESTOR·E STATUS REGISTER AND RETURN.
POP
RETI

PSW
;

RESTORE PSW
AND RETURN FROM INTERRUPT ROUTINE

END
203830-28

:.
'U
•
....
e

_.

ct

XREF SYMBOL TABLE LISTING


u

20

o

10

20

30

40

50

60

70

80

90

100 110 120

TIME IN NANOSECONDS

210313-2

(a)

Obviously, ESD-sensitivity needs to. be considered in
the design of equipment that is going to be subjected to
it, such as office equipment.
GROUND NOISE

Currents in ground lines are another source of noise.
These can be 60 Hz currents from the power lines, or
RF hash, or crosstalk from other signals that are sharing this particular wire as a signal return line. Noise in
the ground lines is often referred to as a "ground loop" ,
problem. The basic concept of the ground loop is
shown in Figure 3. The problem is that true
earth-ground is not really at the same potential in all
locations. If the two ends of a wire are earth-grounded
at different locations, the voltage difference between the
two "ground" points can drive significant currents (several amperes) through the wire. Consider the wire to be
part of a loop which contains, in addition to the wire, a
voltage source that represents the difference in potential between the two ground points, and you have
10-258

Vert: 5 Amps/DiY
Time: 5 nSec/Diy
Displayed:
Ip: 40 Amps
Tr: 1 nSec

500V

210313-3

(b)

Figure 2. Waveforms of Electrostatic
Discharge Currents From a
Hand-Held Metallic Object

AP-125

suppressors, although layouts and grounding techniques.are important here, too.

Simulating the Environment
Addressing noise problems after the design of a system
has been completed is an expensive proposition. The ill
will generated by failures in the field is not cheap either.
It's cheaper in the long run to invest a little time and
money in learning about noise and noise simulation
equipment, so that controlled tests can be made on the
bench as the design is developing.
Simulating the intended noise environment is a twostep process: First you have to recognize what the noise
environment is, that is, you have to know what kinds of
electrical noises are present, and which of them are going to cause trouble. Don't ignore this first step, because it's important. If you invest in an induction coil
spark generator just because your application is automotive, you'll be straining at the gnat and swallowing
the camel. Spark plug noise is the least of your worries
in that environment.
The second step is to generate the electrical noise in a
controlled manner. This is usually more difficult than
first imagined; one first imagines' the simulation in
terms of a waveform generator and a few spare parts,
and then finds that a wideband power amplifier with a
200V dynamic range is als!, required. A good source of
information on who supplies what noise-simulating
equipment is the 1981 "ITEM" Directory and Design
Guide (Reference 6).

Types of Failures and Failure
Mechanisms
A major problem that EMI can cause in digital systems
is intermittent operational malfunction. These software
upsets occur when the system is in operation at the time
an EMI source is activated, and are' usually characterized by a loss of information or a jump in the execution

of the program to'some random location in memory.
The person who has to iron out such problems is tempted to say the program counter went crazy. There is
usually no damage to the hardware, and normal operation can resume as soon as the EM! has passed or the
source is de-activated. Resuming normal operation usually requires manual or automatic reset, and possibly
re-entering of lost information.
Electrostatic discharges from operating personnel can
cause not only software upsets, .but also permanent
("hard") damage to the system. For this to happen the
system doesn't even have to be in operation. Sometimes
the permanent damage is latent, meaning the initial
damage may be marginal and require further aggravation through operating stress and time before permanent failure takes place. Sometimes too the damage is
. hidden.
One ESD-related failure mechanism that has been identified has to do with the bias voltage on the substrate of
the chip. On some CPU chips the substrate is held at
- 2.5V by a phase-shift oscillator working into a capacitor/diode clamping circuit. This is called a "charge
pump" in chip-design circles. If the substrate wanders
too far in either direction, program read errors are noted. Some designs have been known to allow electrostatic discharge currents to flow directly into port pins of
an 8048. The resulting damage to the oxide causes an
increase in leakage current, which loads down the
charge pump, reducing the substrate voltage to a marginal or unacceptable level. The system is then unreliable or completely inoperative until the CPU chip is
replaced. But if the CPU chip was subjected to a discharge ~park once, it will eventually happen again.
Chips that have a grounded substrate, such as the 8748,
can sometimes sustain some oxide damage without actually becoming inoperative. In this case the damage is
present, and the increased leakage current is noted;
however, since the substrate voltage retains its design
value, the damage is largely hidden.

EARTH-GROUND
ATB

-GROUND LOOP"

\.POTENTIAL DIFFERENCE
BETWEEN A AND B

210313-4

Figure 3. What a Ground Loop Is
10-259

intJ

AP-125

It must therefore, be recognized that connecting port

pins unprotected to a keyboard or to anything else that
is subject to electrostatic discharges, makes an extremelydangerous configuration. It doesn't make any difference what CPU chip is being used, or who makes it. If
it connects unprotected to a keyboard, it will eventually
be destroyed. Designing for an ESD-environment will
be discussed further on.
We might note .here that MOS chips are not the only
components that are susceptible to permanent, ESD
damage. Bipolar and linear chips can also be damaged
in this way. PN junctions are subject to a hard failure
mechanism called thermal secondary breakdown, in
which a current spike, such as from an electrostatic
discharge, causes microscopically localized spots in the
junction to approach melt temperatures. Low power
TIL chips are subject to this tyPe of damage, as are
op-arnps. Op-amps, in addition, often carry on-chip
MOS capacitors which are directly across an external
pin combination, and these are susceptible to dielectric
breakdown.
We return now to the subject of software upsets. Noise
transients can upset the chip through any pin, even an
output pin, because every pin on the chip connects to
the substrate through apnjunction. However, the most
vulnerable pin is probably ,the VCe line, since it has
direct access to all parts of the chip: every register, gate,
flip-flop lind buffer.

to minimize the generation of noise voltages in the circuit. These methods involve grounding, shielding, and
wiring techniques that are directed toward the mechanisms by which noise voltages are generated in the circuit. We'll also discuss methods of decoupling. Then
we'll look at some schemes for making a graceful recovery from upsets that occur in spite of preventive measures. Lastly, we'll take another look at two special
problem areas: electrostatic discharges and the automotive environment.
'

Current Loops
The first thing most people learn about electricity is
that current won't flow unless it can flow in a closed
loop. This simple fact is sometimes temporarily forgotten by the ,overworked engineer who has spent the past
several years mastering the intricacies of the DO loop,
the timing loop, the feedback loop, and maybe even the
ground loop. The simple current loop probably owes its
apparent demise to the invention of the ground symbol.
By a stroke, of the pen one avoids, having to draw the
return paths of most of the current loops in the circuit.
Then "ground" turns into an infinite current sink, so
that any current that flows into it is gone and forgotten.
Forgotten it may be, but it's not gone. It must return to
its source, SO that its path will by all the laws of nature
form a closed loop.

.

The, menu of possible upset mechanisms is quite
lengthy. A transient on the ,substrate at the wrong time
will generally cause a program read error. A false level
at a control input can cause an extraneous or misdirected opcode fetch. A disturbance on the supply line can
flip a bit in the program counter or instruction register.
A short interruption or reversal of polarity 'on the supply line can actually turn the processor off, but not long
enough for the power-up reset capacitor to discharge.
Thus when the transient ends, the chip starts up again
without 'Ii reset.
'.
A common failure mode is for the processor to lock
itself into a tight loop. Here it may be executing the
data in a table, or' the program counter may have
jumped a notch, so that the processor is now executing
operands instead of opcodes, or it may be. trying to
fetch opcodes from a nonexistent external program
memory.
It should be emphasized that mechanisms for upsets
have to do with the arrival of noise-induced transients
at the pins of the chips, rather than with the generation
of noise pulses within the chip itself, that is, it's not the
chip that is picking up noise, it's the circuit.

The Game Plan

The physical geometry of a given current loop is the
key to why it generates EMI, why it's susceptible to
EMI, and how to shield it. Specifically, it's the area of
the loop that matters.
Any flow of current generates a magnetic field whose
intensity varies inversely to the distance from the wire
that carries the current. Two parallel wires conducting
currents + I and - I (as in signal feed and return lines)
would generate a nonzero magnetic field near the wires,
where the distance from a given point to one wire is
noticeably different from the distance to the other wire,
but farther away (relative to the wire spacing), where
the distances from a given point to either wire are about
the saine, the fields from both wires tend to cancel out.
Thus, maintaining proximity between feed and return
paths is an important way to minimize their interference with other signals. The way to maintain their
proximity is essentially to minimize their loop area.
And, because the mutual inductance from current loop
A to current loop B is the same as the mutualinductimce from current loop B to current loop A, a circuit
that doesn't radiate interference doesn't receive it either.
Thus, from the standpoint of reducing both generation
of EMI and susceptibility to EMI, the hard rule is to
keep loop areas small. To say that loop areas should be
minimized is the same as saying the circuit inductance

Prevention is usually cheaper than suppression, so first
we'll consider some preventive methods that might help
10-260

inter

AP-125

should be minimized. Inductance is by definition the
constant of proportionality between current and the
magnetic field it produces: 

0

.J

In the near field of a whip antenna, the E/H ratio is
higher than 3770, which means it's mainly an E-field
generator. A wire-wrap post can be a whip antenna.
Interference from a whip antenna would be by electric
field coupling, which is basically capacitive coupling.
Methods to protect a circuit from capacitive coupling,
such as a Faraday shield, would be effective
10-264

Z
0

;::.

...
..

U

150
125
100
75
50
25

.J

II:

0.01

0.1

1.0

10

100

1000

10.000

FREQUENCY (KILOHERTZ)

210.313-13

Figure 9. E-Field Shielding

inter

AP·125

175.-----------r-------r-r-------~

!

150

300,-----------------------------~

PLANE WAVE

'" 250

III

!

,
,,
,
.,

200 .

'111

~
z

150

I

----""'REFLECTION ----I-,"
,,

Cl

9 100
III

%
~ 50

,.'

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I!

25

f:!

_-----ABSORPTION

O+----.----~-~-~-~--;-~---_.----_r--~
0.01

10

10'

10

1

10~

10$

10'

10'

0.1

1.0

10

100

1000

10.000

.FREQUENCY (KILOHERTZ)

FREQUENCY (HERTZ)

210313-15
210313-14

Figure 10. H·Field Shielding

Figure 11. E· and H·Field Shielding

Copper and aluminum both have the same permeability, but copper is slightly more conductive, and so provides slightly greater reflection loss to an E-field. Steel
is less effective for two reasons. First, it has a somewhat
elevated permeability due to its iron content, and second, as tends to be the case with magnetic materials, it
is less conductive.

rents must be allowed to flow freely. If they have to
detour around slots and holes, as shown in Figure 12,
the shield loses much of its effectiveness.

On the other hand, according to the expression for ab~
sorption loss to an H-field, H-field shielding is more
effective at higher frequencies and with shield material
that has both high conductivity and high permeability.
In practice, however, selecting steel for its high permeability involves some compromise in conductivity. But
the increase in permeability more than makes up for the
decrease in conductivity, as can be seen in Figure 10.
This figure also shows the effect of shield thickness.
A composite of E-field and H-field shielding is shown
in Figure 11. However, this type of data is meaningful
only in the far field. In the near field the EMI could be
90% H-fie1d, in which case the reflection loss is irrelevant. It would be advisable then to beef up the absorption loss, at the expense of reflection loss, by choosing
steel. A better conductor than steel might be less expensive, but quite ineffective.
A different shielding mechanism that can be taken advantage of for low frequency magnetic fields is the ability of a high permeability material such as. mumetal to
divert the field by presenting a very low reluctance path
to the magnetic flux. Above a few kHz, however, the
permeability of such materials is the same as steel.
In actual fact the selection of a shielding material turns
out to be less important than the presence of seams,
joints and holes in the physical structure of the enclosure. The shielding mechanisms are related to the induction of currents in the shield material, but the cur-

As can be seen in Figure 12, the severity of the detour
has less to do with the area of the hole than it does with
the geometry of the hole. Comparing Figure 12c with
12d shows that a long narrow discontinuity such as a
seam can cause more RF leakage than a line of holes
with larger total area. A person who is responsible for
designing or selecting rack or chassis enclosures for an
EMI environment needs to be familiar with the techniques that are available for maintaining electrical continuity across seams. Information on these techniques is
available in the references.

Grounds
There are two kinds of grounds: earth-ground and signal ground. The earth is not an equipotential surface, so
earth ground potential varies. That and its other electrical properties are not conducive to its use as a return
'conductor in a circuit. However, circuits are often connected to earth ground for protection against shock
hazards. The other kind of ground, signal ground, is an
arbitrarily selected reference node in a circuit-the
node with respect to which other node voltages in the
circuit are measured.
SAFETY GROUND

The standard 3-wire single-phase AC power distribution system is represented in Figure 13: The white wire
is earth-grounded at the service entrance. If a load circuit has a metal enclosure or chassis, and if the black
wire develops a short to the enclosure, there will be a
shock hazard to operating personnel, unless the enclosure itself is earth-grounded. If the enclosure is earth-

10-265

intJ

AP-125

__ INDUCED
SHIELD
CURRENTS·

--SECTION OF
SHIELD

~~1

_ - RECT:LNO;ULAR

(b)

(-)

(d)

(e)

210313-16

Figure 12. Effect of Shield Discontinuity on Magnetically Induced Shield Current
grounded, a short results in a blown fuse rather than a
"hot" enclosure. The earth-ground connection to the
enclosure is called a safety ground; The advantage of
the. 3-\...ire power system .is that it distributes a safety
ground along with the power.
Note that the safety-ground wire carries no current,
except in case of a fault, so that at least for low frequencies it's at earth-ground potential. along its entire
length. The white wire, on the other. hand, may be several volts off ground, due to the IR drop along its
length.
SERVICE
(ENTRANCE
(-----:--"

METAL
( ENCLOSURE

BLACK

1'"--------,

I

I
I
I
I
I
I

I
I

LOAD
CKT

:

WHITE·

I
I

GREEN

·1

I~

.....

__ .-

:
I
. I
I
I

----)

___ -

EARTH-GROUND

210313-17

Figure 13. Single-Phase Power Distribution

SIGNAL GROUND

Signal ground is a single point in a' circuit that is designated to pe the reference node for the circuit. Commonly, wires that connect to this single point are also referred to as "signal ground." In some circles "power
supply common" or PSC is the preferred terminology
for these conductors. In any case, the manner in which
these wires connect to the actual reference point is the
basis of distinction among· three kinds of signal-ground
wiring methods: series, parallel, and multipoint. These
methods are shown in Figure 14.
The series connection is pretty common because it's
simple imd economical. It's the noisiest of the three,
however, due to common ground impedance coupling
between the circuits. When several circuits share a
ground wire, currents from one circuit, flowing through
the finite impedance of ihe common ground line, cause
vari/l,tions in the ground potential of the other circuits.
Given that the currents in a digital system tend to be
spiked, and that the common impedance is mainly inductive reactance, the variations could be bad enough
to cause bit errors in high current or particularly noisy
situations.
.
,
The parallel connection eliminates common ground impedanceproblems, but uses a lot of wire. Other disadvantages are ·that the impedance of the individual
ground Jines can be very high, and .the. ground lines
themselves can become sources of EMI, .

10-266

inter

AP-125

In the multipoint system, ground impedance is minimized by using a ground plane with the various circuits
connected to it by very short ground leads. This type of
connection would be used mainly in RF circuits above
10 MHz.

QUIET
SIGNAL
GROUND

PRACTICAL GROUNDING

HARDWARE
GROUND

' - - REF. POINT

A combination of series and parallel ground-wiring
methods can be used to trade off economic and the
various electrical considerations. The idea is to run series connections for circuits that have similar noise
properties, and connect them at a single reference
point, as in the parallel method, as shown in Figure 15.
In Figure 15, "noisy signal ground" connects to things
like motors and relays. Hardware ground is the safety
ground connection to chassis, racks, and cabinets. It's a
mistake to use the hardware ground as a return path for
signal currents because it's fairly noisy (for example,
it's the hardware ground that receives an ESD spark)
and tends to have high resistance. due to joints and
seams.

\GROUNDLINE

NOISY
AND HIGH
CURRENT
SIGNAL
GROUND

\

REF. POINT

210313-18

Series Connection

GREEN·WIRE
GROUND

210313-21

Figure 15. Parallel Connection
of Series Grounds
Screws and bolts don't always make good electrical
connections because of galvanic action, corrosion, and
dirt. These kinds of connections may work well at first,
and then cause mysterious maladies as the system ages.
Figure 16 illustrates a grounding system for a 9-track
digital tape recorder, showing an application of the series/parallel ground-wiring method.
Figure 17 shows a similar separation of grounds at the
PCB leveL Currents in multiplexed LED displays tend
to put a lot of noise on the ground and supply lines
because of the constant switching and changing involved in the scanning process. The segment driver
ground is relatively quiet, since it doesn't conduct the
LED currents. The digit driver ground is noisier, and
should be provided with a separate path to the PCB
ground terminal, even if the PCB ground layout is gridded. The LED feed and return current paths should be
laid out on opposite sides of the board like parallel flat
conductors.
Figure 18 shows right and wrong ways to make ground
connections in racks. Note that the safety ground connections from panel to rack are made through ground
straps, not panel screws. Rack 1 correctly connects sig·
nal ground to rack ground only at the single reference
point. Rack 2 incorrectly connects signal ground to
rack ground at two points, creating a ground loop
around points I, 2, 3, 4, 1.

210313-19

Parallel Connection

Breaking the "electronics ground" connection to point
1 eliminates the ground loop, but leaves signal ground
in rack 2 sharing a ground impedance with the relatively noisy hardware ground to the reference point; in fact,
it may end up using hardware ground as a return path
for signal and power supply currents. This will probably cause more problems than the ground loop.

BRAIDED CABLE
REF. POINT

210313-20

Multipoint Connection
Figure 14. Three Ways to Wire the Grounds

Ground impedance problems can be virtually eliminated by using braided cable. The reduction in impedance
is due to skin effect: At higher frequencies the current
tends to flow along the surface of a conductor rather

10-267

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------------------------1

t( t( t( ~~_~M

1

i
1

I

9 "WRITE" CIRCUITS

.

t

SIGNAL GROUNOS"

GREEN-WIRE
GROUND

210313-22

Figure 16. Ground System in a 9-Track Digital Recorder

CONTROL FUNCTIONS

CONTROLLER

I----.....--~~
'----~--~~----GROUND

210313-23

Figure 17. Separate Ground for Multiplexed LED Display

10-268

AP-125

RACK 2

RACK 1

P:6~~~Y

c'JIf'=-_ _ _ _ _ _ _ _ _ _ _ _-'-ElECTRONICS GROUND

GROUND
GREEN-WIRE GROUND

21.0313-24

Figure 18_ Electronic Circuits Mounted in Equipment Racks Should Have Separate Ground
Connections_ Rack 1 Shows Correct Grounding, Rack 2 Shows Incorrect Grounding_
than uniformly threugh its bulk_ While this effect tends
to increase the impedance of a given conductor, it also
indicates the way to minimize impedance, and that is to
manipulate the shape of the cress-sectien se as te previde mere surface area. Fer its bulk, braided cable is
almost pure surface.

Power Supply Distribution and
Decoupling
The main consideratien for power supply distributien
lines is, as for signal lines, to minimize the areas of the
current loops. But the power supply lines take on an
importance that no signal line has when one censiders
the fact that these lines have access to every PC board
in the system. The very extensiveness of the supply current loops makes it difficult to keep loop areas small.
And, a noise glitch en a supply line is a glitch delivered
to every' board in the system.
The power supply provides low-frequency current to
the load, but the inductance of the board-te-board and
chip-to-chip distribution network makes it difficult for
the power supply to maintain VCC specs on the chip
while providing the current spikes that a digital system
requires. In addition, the power supply current loop is a
very large one, which means there will be a let of noise
pick-up. Figure 19a shows a load circuit trying to draw
current spikes from a supply voltage through the line
impedance. To the VCC waveform shown in that figure
should be added the inductive pick-up associated with a
large loop area.
Adding a decoupling capaciter selves two problems:
The capacitor acts as a nearby source of charge to supply the current spikes through a smaller line impedance, and it defines a much smaller loop area for the

higher frequency cemponents .of EMI. This is illustrated in Figure 19b, which shows the capacitor supplying
the current spike, during which VCC drops from 5V by
the amount indicated in the figure. Between current
spikes the capacitor recovers through the line impedance.
'One should resist the temptation to add a resistor or an
inductor to the decoupler so as to ferm a genuine RC .or
LC low-pass filter because that slows down the speed
with which the decoupler cap can be refreshed. Good
filtering and goed decoupling are not necessarily the
same thing.
The current loop for the higher frequency currents,
then, is defined by the decoupling cap and the load
circuit, rather than by the power supply and the load
circuit. For the decoupling cap to be able to previde the
current spikes required by the load, the inductance of
this current loop must be kept small, which is the same
as saying the leop area must be kept small. This is also
the requirement for minimizing inductive pick-up in
the leop.
There are two kinds of decoupling caps: beard decoupIers and chip deceuplers. A board decoupler will normally be a 10 te 100 p,F electrolytic capacitor placed
near to where the power supply enters the PC board,
but its placement is relatively non-critical. The purpose
of the board decoupler is to refresh the charge on the
chip deceuplers. The chip decouplers are what actually
provide the current spikes to the chips. A chip decoupIer will normally be a 0.1 to 1 ,..,F ceramic capacitor
placed near the chip and connected to the chip by
traces that minimize the area of the loop formed by the
cap and the chip. If a chip decoupler is not properly
placed en the board, it will be ineffective as a decoupler

10-269

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Vcc:
--------~-----------------. t

210313-25

210313-26

(a) Drawing Current Spikes
through the Line Impedance

(b) Drawing Current Spikes
from a Decoupllng Capacitor

Figure 19. What a Decoupling Capacitor Does
and will serve only to increase the cost of the board.
Good and bad placement of decoupling capacitors are
illustrated in Figure 20.
Power distribution traces on the PC board need to be
laid out so as to obtain minimal area (miilimal inductance) in the loops formed by each chip and its decoupier, and by the chip decouplers and the board decoupier. One way to accomplish this goal is to use a power
plane. A power plane is the same as a ground plane, but
at VCC potential. More economically, a power grid
similar to the ground grid previously discussed (Figure
8) can be used. Actually, if the chip decoupling loops
are small, other aspects of the power layout are less .
critical. In other words, power planes and power gridding aren't needed, but power traces should be laid in .
the closest possible proximity to ground traces, preferThere must be a very low Inductance between decoupling capacitor
and the IC.

Poo,PI.cemen,

Better Pllleement

~I

~vcc

.
210313-27
The decreased area of loop between capacitor & IC decreases
,
inductance.

.Figure 20. Placement of Decoupllng Capacitors

ably so that each power trace is on the direct opposite
side of the board from a ground trace.
Special-purpose power supply distribution buses which
mount on the PCB are available. The buses use a parallel flat conductor configuration, one conductor being a
VCC line and the other a ground line. Used in conjunction with a gridded ground layout, they not only provide a' low-inductance distribution system, but can
themselves form part of the ground grid, thus facilitating. the PCB layout. The buses are available with and
without enhanced bus capacitance, under the names
MinilBus® and Q/PAC® from Rogers Corp. (5750 E.
McKellips, Mesa, AZ 85205).
SELECTING THE VALUE OF THE
DECOUPLING CAP

The effectiveness of the decoupling cap has a lot to do
with the way the power and ground traces connect this
capacitor to the chip. In fact; the area formed by this
loop is more important than the value of the capacitance. Then, given that the area of this loop is indeed
miilimal, it can generally be said that the larger the
value of the decoupling cap, the more effective it is, if
the cap has a mica, ceramic, glass, or polystyrene dielectric.
It's often said, and not altogether accurately, that the
chip decoupler shouldn't have too large a value. There
are two reasons for this statement. One is that some
capacitors, because of the nature of their dielectrics,
tend to become inductive or lossy at higher frequencies.
This is true of electrolytic capacitors, but mica, glass,
10-270

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AP-125

ceramic, and polystyrene dielectrics work well to several hundred MHz. The other reason cited for not using
too large a capacitance has to do with lead inductance.
The capacitor with its lead inductance forms a series
LC circuit. Below the frequency of series resonance, the
net impedance of the combination is capacitive. Above
that frequency, the net impedance is inductive. Thus a
decoupling capacitor is capacitive only below the frequency of series resonance. The frequency is given by

CPU chip and the PCB (or between the CPU socket
and the PCB), it makes connection to pins 40 and 20,
forming a leadless decoupling capacitor. It is obviously
a configuration of minimal inductance. Unfortunately,
the particular sample tested had only 0.07 J.tF of capacitance and so was unable to prevent the 1 MHz ripple
as effectively as the configuration of Figure 21 d. It
seems apparent, though, that with more capacitance
this part will alleviate a lot of decoupling problems.
THE CASE FOR ON-BOARD VOLTAGE
REGULATION

1

fo = 21TM
where C is the decoupling capacitance and L is the lead
inductance between the capacitor and the chip. On a
PC board this inductance is determined by the layout,
and is the same whether the capacitor dropped into the
PCB holes is 0.001 J.tF or 1 J.tF. Thus, increasing the
capacitance lowers the series resonant frequency. In
fact, according to the resonant frequency formula, increasing C by a factor of 100 lowers the resonant frequency by a factor of 10.
Figures quoted on the series resonant frequency of. a
0.01 J.tF capacitor run from 10 to 15 MHz, depending
on the lead length. If these numbers were accurate, a
1 J.tF capacitpr in the same position on the board would
have a resonant frequency of 1.0 to 1.5 MHz, and as a
decoupler would do more harm than good. However,
the numbers are based on a presumed inductance of a
given length of wire (the lead length). It should be noted that a "length of wire" has no inductance at all,
strictly speaking. Only a complete current loop has inductance, and the inductance depends on the geometry
of the loop. Figures quoted on the inductance of a
iength of wire are based on a presumably "very large"
loop area, such that the magnetic field produced by the
return current has no cancellation effect on the field
produced by the current in the given length of wire.
Such a loop geometry is not and should not be the case
with the decoupling loop.
Figure 21 shows VCC waveforms, measured between
pins 40 and 20 (VCC and VSS) of an 8751 CPU, for
several conditions of decoupling on a PC board that has·
a decoupling loop area slightly larger ihim necessary.
These photographs show the effects of increasing the
decoupling capacitance and decreasing the area of. the
decoupling loop. The indications are that a 1 J.tF capacitor is better than a 0.1 J.tF capacitor,which in turn is
better than nothing, and that the board should have
been laid out with more attention paid to the ·area of the
decoupling loop.
Figure 21e was obtained using a special-purpose experimental capacitor designed by Rogers Corp. (Q-Pac Division, Mesa, AZ) for use as a decoupler. It consists of
two parallel plates, the length of a 40-pin DIP, separated by a ceramic dielectric. Sandwiched between the

To complicate matters, supply line glitches aren't always picked up in the distribution networks, but can
come from the power supply circuit itself. In that case,
a well-designed distribution network faithfully delivers
the glitch throughout the system. The VCC glitch in
Figure 22 was found to be coming from within a bench
power supply in response to the EMP produced by an
induction coil spark generator that was being used at
Intel during a study ·of noise sensitivity. The VCC
glitch is about 400 mV high and some 20 J.ts in duration. Normal board decoupling techniques were ineffective in removing it, but adding an on-board voltage regulator chip did the job.
Thus, a good case can be made in. favor of using a
voltage regulator chip on each PCB, instead of doing all
the voltage regulation at the supply circuit. This eases
requirements on the heat-sinking· at the supply circuit,
and alleviates much of the distribution and board decoupling headaches. However, it also brings in the possibility that different boards would be operating at
slightly different VCC levels due to tolerance in the
regulator chips; this then leads to slightly different logic
levels from board to board. The implications of that
may vary from nothing to latch-up, depending on what
kinds of chips are on the boards, and how they react to
an input "high" that is perhaps O.4V higher than local
VCC.
.

Recovering Gracefully from a Software
Upset
.
Even when one follows all the best guidelines for designing for a noisy environment, it's always possible for
a noise transient to occur which exceeds the circuit's
immunity level. In that case, one can strive at least for a
graceful recovery.
Graceful recovery schemes involve additional hardware
and/or software which is supposed to return the system
to a normal operating mode after a software upset has
occurred. Two decisions have to be made: How to recognize when an upset has occurred, and what to do
about it.

10-271

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PIN 40
PIN 40

.

.

.
5CtrV

5V

L

ALE

_ "__
210313-28

(a) No Decoupllng Cap

PIN 40

5CmV

5V

501r.V

5V

.
~

210313-'30

210313:'31 '

(c) 0.1 p.F Decoupler Stretched Directly'
from Pin 40 to Pin 20, under the Socket.
(The difference between this and 21b is
due only to the change in loop geometry.
Also shown is the upward slope of a ripple
in VCC. The ripple frequency Is
1 MHz, the same as ALE.)

(d) 1.0 p.F Decoupler Stretched Directly
from Pin 40 to pin 20, under the Socket.
(This prevents the 1 MHz,rlpple, but there's
no reduction In higher frequency components.
Further Increases In capacitance
effected no further Improvement.)

PIN 40

ALE

*'

-~.

SV
210313-32

(e) Special-Purpose Decoupling Cap
under Development by Rogers Corp.
(Further discussion in text.)
Figure 21. Noise on VCC Line

10-272

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I

L

t -f-· - .- - -.:
1
•
i
,
I'
r--.. -T
T
I

r

I

~ -~

.
,

SPARK PROBE

50mV (TRIGGER)

Vee

500mV

210313-33

Figure 22. EMP-Induced Glitch

If the designer knows what kinds and combinations of
outputs can legally be generated by the system, he can
use gates to recognize and flag the occurrence of an
illegal state of affairs. The flag can then trigger a jump
to a recovery routine which then may check or re-initialize data, perhaps output an error message, or generate a simple reset.
The most reliable scheme is to use a so-called watchdog
circuit. Here the CPU is programmed to generate a
periodic signal as long as the system is executing instructionsin an expected manner. The periodic signal is
then used to hold off a circuit that will trigger a jump to
a recovery routine. The periodic signal needs to be ACcoupled to the trigger circuit so that a "stuck-at" fault
won't continue to hold off the trigger. Then, if the processor locks up someplace, the periodic signal is lost and
the watchdog triggers a reset_
In practice, it may be convenient to drive the watchdog
circuit with a signal which is being generated anyway
by the system. One needs to be careful, however, that
an upset does in fact discontinue that signal. Specifically, for example, one could· use one of the digit drive
signals going to a multiplexed display. But display
scanning is often handled in response to a timer-interrupt, whieh may continue operating even though the
main program is in a failure mode. Even so, with a little
extra software, the signal can be used to control the
watchdog (see Reference 8 on this).
Simpler schemes can work well for simpler systems.
For example, if a CPU isn't doing anything but scanning and decoding a keyboard, there's little to lose and
much to gain by simply resetting it periodically with an
astable multivibrator. It only takes about 13 f.Ls (at 6
MHz) to reset an 8048 if the clock oscillator is already
running.
A zero-cost measure is simply to fill all unused program memory with NOPs and JMPs to a recovery routine. The effectiveness of this method is increased by
writing the program in segments that are separated by

NOPs and JMPs. It's still possible, of course, to get
hung up in a data table or something. But you get a lot
of protection, for the cost.
Further discussion of graceful recovery schemes can be
found in Reference 13.

Special Problem Areas
ESD

MOS chips have some built-in protection against a static charge build-up on the pins, as would occur during
normal handling, but there's no protection against the
kinds of current levels and rise times that occur in a
genuine electrostatic spark. These kinds of discharges
can blow a crater in the silicon.
It must be recognized that connecting CPU pins unprotected to a keyboard ()r to anything else that is subject
to electrostatic discharges makes an extremely fragile
configuration. Buffering them is the very least one can
do. But buffering doesn't completely solve the problem,
because then the buffer chips will sustain the damage
(even TTL); therefore, one might consider mounting
the buffer chips in sockets for ease of replacement.
Transient suppressors, such as the TranZorbs® made
by General Semiconductor Industries (Tempe, AZ),
may in the long run provide the cheapest protection if
their "zero inductance" structure is used. The structure
and circuit application are shown in Figure 23.
The suppressor element is a pn junction that operates
like a Zener diode. Back-to-back units are available for
AC operation. The element is more or less an open
circuit at normal system voltage (the standoff voltage
rating for the device), and conducts like a Zener diode
at the clamping voltage.
The lead inductance in the conventional transient suppressor package makes the conventional package essen-

10-273

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AP-125

PULSE DIGITAL
A
H-r~--tB

FUNCTIONAL
H+,..,.--tc DECODER
H+-hr-:--tD

L ____ J

Patent Pending

COMMON

210313-34

(a)

210313-35

(b)

Figure 23. "Zero~lnductance" Structure and Use in Circuit
tially useless' for protection against ESD pulses, owing
to the fast rise of these pulses. The "zero inductance"
units are available singly in a 4-pin DIP, and in arrays
of four to a 16-pin DIP for PCB level protection. In
that application they should be mounted in close proximity to the chips they protect.
In addition,' metal enclosures or frames or parts that
can receive an ESD spark should be connected by
braided cable to the green-wire ground. Because of the
ground impedance, ESD current shouldn't be allowed
to flow through any signal ground, even if the chips are
protected by transient suppressors. A 35 kV ESD spark
can always spare a few hundred volts to drive a fast
current pulse down a signal ground line if it can't find a
braided cable to follow. Think how delighted your 8048
will be to find its VSS pin 250V higher than VCC for a
few lOs of nanoseconds.

THE AUTOMOTIVE ENVIRONMENT
The automobile presents an extremely hostile environment for electronic systems. There are several parts to
it:
1. Temperature extremes from -4Q°C to + 125°C (under the hood) or + 85°C (in the passenger compartment)
2. Electromagnetic pulses from the ignition system
3. Supply line transients that will knock your socks off
One needs to take a long, careful look at the temperature extremes. The allowable storage temperature range
for most Intel MOS chips is -65°t to + 1500C, al"
though some chips have a maximum storage temperature rating of + 125°C. In operation (or "under bias,"
as the data sheets say) the allowable ambient temperature range, depends on the product grade, as follows:

Grade
Commercial
Industrial
Automotive
Military

Ambient Temperature
Min

Max

0
-40
-40
-55

70
+85
+110
+125,

The different product grades are actually the same
chip, but tested according to different standards. Thus,
a given commercial-grade chip might actually pass military temperature requirements, but not have been tested,fcr it. (Of course, there are other differences in 'gruding requirements having to do with packaging, bum-in,
traceability, etc.)
In any case, it's apparent that commercial-grade chips
can't. be used safely in automotive applications, not
even in the passenger compartment. Industrial-grade
chips can be used in the passenger compartment, and
automotive or military chips are required in under-the~
hood applications.
Ignition noise, CB radios, and that sort of thing are
probably the least of your worries. In a poorly designed
system, or in .one that has not been adequately tested
for the automotive environment, ,this type of EMI
might cause a few software upsets, but not destroy
chips.
The major problem, and the one that seems to come as
the biggest surprise to most people, is the line transients. Regrettably, the 12V battery is not. actually the
source of power when the car is running. The charging
system is, and it's not very clean. The only time the
battery is the real source of power is when the car is
first being started, and in that condition the battery
terminals may be delivering about5V or 6V. As follows
is a brief description of the major idiosyncracies of the
"12V" automotive power line.

10·274

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AP-125

60

50

iii'

!:i

40

w

30

ENGINE SPEED 3000 RPM
ALTERNATOR LOAD 55 AMPERES

0
~
Q

:;)

5
Do

::E

'"

20

10

a

a

~

~

~

~

~

~

~

~

~

~

TIME (MILLISECONDS)

210313-36

Figure 24. Typical Load Dump Transients
• An abrupt reduction in the alternator load causes a
positive voltage transient called "load dump." In a
load dump transient the line voltage rises to 20V or
30V in a few /ks, then decays exponentially with a
time constant of about 100 J.Ls, as shown in Figure
24. Much higher peak voltages and longer decay
times have also been reported. The worst case load
dump is caused by disconnecting a low battery from
the alternator circuit while the alternator is running.
NormallY.this would happen intermittently when
the battery terminal connections are defective.
• When the ignition is turned off, as the field excitation decays, the line voltage' can go to between
-40V and -IOOV for 100 J.Ls or more.
• Miscellaneous solenoid switching transients, such as
the one shown in Figure 25, can drive the line to +
or - 200V to 400V for several J.Ls.

• Mutual coupling between unshielded wires in long
harnesses can induce 100V and 200V transients in
unprotected circuits.
What all this adds up to is that people in the business of
building systems for automotive applications need a
comprehensive testing program. An SAE guideline
which describes the automotive environment is available to designers: SAE Jl21l, "Recommended Environmental Practices for Electronic Equipment Design,"
1980 SAE Handbook, Part I, pp. 22.80-22.96.
Some suggestions for protecting circuitry are shown in
Figure 26. A transient suppressor is placed in front of
the regulator chip to protect it. Since the rise times in
these transients are not like those in ESD pulses, lead
inductance is less critical and conventional devices can
be used. The regulator itself is pretty much of a necessity, since a load dump transient is simply not going to be
removed by any conventional LC or RC filter.

OSEe.

t
OVOLTS -

-100 VOLTS/DIV

10ps/DIV

--

210313-37

Figure 25. Transient Created by De-energizing an Air Conditioning Clutch Solenoid

10-275

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AP·125

AUTOMOTIVE ON BOARD COMPUTER

.-.. . -"""'1----ACCESSORY
+12V

-r-t--'VI."'''..---I
.....---...-

o-J'l1J'......

~

+5V

TO" PROCESSOR

115V

DISTANCE
MEASURING COIL

,-0---------""',...._,.",-_

TO" pROCESSOR

5V
210313-38

Figure 26. Use of Transient Suppressors in Automotive Applications
Spe2ial I/O interfacing is aJso required, because of the
need for high tolerance to cvoltage transients, input
noise, input/output isolation, etc. In addition, switches
cthat are being monitored or driven by these buffers are
usually referenced to chassis ground instead of signal
ground) and in a. ca.r there ca..'1 be ma.."lY volts difference
between the two. I/O interfacing is discussed in Reference 2.

The EMC Education committee has available a video
tape: "Introduction to EMC-A Video Training
Tape," by Henry Ott. Don White Consultants offers a
series of training courses on many different aspects of
electromagnetic compatibility. Most organizations that
sponsor El".fC courses also (jff~r in-plant presentatiuns.

Parting Thoughts
The main sources of information cfor this Application
Note were the references by Ott and by White. Reference 5 is probably the finest treatment currently available on the subject. The other references provided specific information as cited in the text.
Courses and seminars on the subject of electromagnetic
interference are given regularly throughout the year.
Information on these can be obtained from:
IEEE Electromagnetic Compatibility Society
EMC Education Committee
345 East 47th Street
New York, NY 10017
Don White Consultants, Inc.
International Training Centre
P.O. BoxD
Gainesville, VA 22065
Phone: (703) 347-0030

10-276

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REFERENCES
1. Clark, O.M., "Electrostatic Discharge Protection
Using Silicon Transient Suppressors," Proceedings of
the Electrical Overstress/Electrostatic Discharge Symposium. Reliability Analysis Center, Rome Air Development Center, 1979.
2. Kearney, M; Shreve, J.; and Vincent, W., "Microprocessor Based Systems in the Automobile: Custom
Integrated Circuits Provide an Effective Interface,"
Electronic Engine Management and Driveline Control
Systems, SAE Publication SP-481, 810160, pp. 93-102.
3. King, W.M. and Reynolds, D., "Personnel Electrostatic Discharge: Impulse Waveforms Resulting From
ESD of Humans Directly and Through Small HandHeld Metallic Objects Intervening in the Discharge
Path," Proceedings of the IEEE Symposium on Electromagnetic Compatibility, pp. 577-590, Aug. 1981.
.
4. Ott, H., "Digital Circuit Grounding and Interconnection," Proceedings of the IEEE Symposium on Elec-·
tromagnetic Compatibility, pp. 292-297, Aug. 1981.
5. Ott, H., Noise Reduction Techniques in Electronic
Systems. New York: Wiley, 1976.

7. SAE J1211, "Recommended Environmental Practices for Electronic Equipment Design," 1980 SAE
Handbook, Part 1, pp. 22.80-22.96.
8. Smith, L., "A Watchdog Circuit for Microcomputer Based Systems," Digital Design, pp. 78, 79, Nov.
1979.
9. TranZorb Quick Reference Guide. General Semiconductor Industries, P.O. Box 3078, Tempe, AZ
85281.

10. Tucker, T.I., "Spark Initiation Requirements of a
Secondary Explosive," Annals of the New York Academy of Sciences, Vol 152, Article I, pp. 643-653, 1968.
11. White, D., Electromagnetic Interference and Compatibility, Vol. 3: EMI Control Methods and Techniques.
Don White Consultants, 1973.
12. White, D., EMI Control in the Design of Printed
Circuit Boards and Backplanes. Don White Consultants, 1981.
13. Yarkoni, B. and Wharton, J., "Designing Reliable
Software for Automotive Applications," SAE Transactions, 790237, July 1979.

6.

1981 Interference Technology Engineers' Master
(ITEM) Directory and Design Guide. R. and B. Enterprises, P.O. Box 328, Plymouth Meeting, PA 19426.

10-277

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APpLICATION
NOTE

AP-155

December 1986

Oscillators
for Microcontrollers

TOM WILLIAMSON
MICROCONTROLLER
TECHNICAL MARKETING

Order Number: 230659-001
10-278

AP-155

INTRODUCTION
Intel's microcontroller families (MCS®-48, MCS®-51,
and iACX-96) contain a circuit that is commonly referred to as the "on-chip oscillator". The on-chip circuitry is not itself an oscillator, of course, but an amplifier that is suitable for use as the amplifier part of a
feedback oscillator. The data sheets and Microcontoller
Handbook show how the on-chip amplifier and several
off-chip components can be used to design a working
oscillator. With proper selection of off-chip components, these oscillator circuits will perform better than
almost any other type of clock oscillator, and by almost
any criterion of excellence. The suggested circuits are
simple, economical, stable, and reliable.
We offer assistance to our customers in selecting suitable off-chip components to work with the on-chip oscillator circuitry. It should be noted, however, that Intel cannot assume the, resp.onsibility of writing specifications for the off-chip components of the complete oscillator circuit, nor of guaranteeing the performance of
the finished design in production, anymore than a transistor manufacturer, whose data sheets show a number
of suggested amplifier circuits, can assume responsibility for the operation, in production, of any of them.

This Application Note is intended to provide such assistance in the design of oscillator circuits for microcontroller systems. Its purpose is to describe in a practical manner how oscillators work, how crystals and ceramic resonators work, (and thus how to spec them),
and what the on-chip amplifier looks like electronically
and what its operating characteristics are. A BASIC
program is provided in Appendix II to assist the designer in determining the effects of changing individual
parameters. Suggestions are provided for establishing a
pre-production test program.

FEEDBACK OSCILLATORS

Loop Gain
Figure I shows an amplifier whose output line goes into
some passive network. If the input signal to the amplifier is VI, then the output signal from the amplifer is v2
= AVI and the output signal from the passive network
is v3 = {3v2 = {3Avl. Thus {3A is the overall gain
from terminal 1 to terminal 3.

We are often asked why we don't publish a list of required crystal or ceramic resonator specifications, and
recommend values for the other off-chip components.
This has been done in the past, but sometimes with
consequences that were not intended.
Suppose we suggest a maximum crystal resistance of 30
ohms for some given frequency. Then your crystal supplier tells you the 30-ohm crystals are going to cost
twice as much as 50-ohm crystals. Fearing that Intel
will not "guarantee operation" with 50-ohm crsytals,
you order the expensive ones. In fact, Intel guarantees
only what is embodied within an Intel product. Besides,
there is no reaSon why 50-ohm crystals couldn't be
used, if the other off-chip components are suitably ad'
justed.
Should we recommend values for the other off-chip
components? Should we do it for 50-ohm crystals or 30- .
ohm crystals? With respect to what should we optimize
their selection?' Should we minimize start-up time or
maximize frequency stability? In many applications,
neither start-up time nor frequency stability are particularly critical, and our "recommendations" are only'restricting your system to unnecessary tolerances. It all
depends on the application.
Although we will neither "specify" nor "recommend"
specific off-chip components, we do offer assistance in
these tasks. Intel application engineers are available to
provide whatever technical assistance may be needed or
desired by our customers in designing with Intel products.

'230659-1

Figure 1. Factors in Loop Gain
Now connect terminal 1 to terminal 3, so that the signalpath forms a loop: 1 to 2 to 3, which is also 1. Now
we have a feedback loop, and the gain factor {3A is
called the loop gain.
Gain factors are complex numbers., That means they
have a magnitude and a phase angle, both of which
vary with frequency. When writing a complex number,
one must specify both quantities, magnitude and angle.
A number whose magnitude is 3, and whose angle is 45
degrees is commonly written this way: 3L45·. The number 1 is, in complex number notation, !LO·, while -1 is
!LI80·.
By closing the feedback loop in Figure 1, we force the
equality

This equation has two solutions:

10-279

1) "1 = 0;
2) fjA = UO·.

inter

AP-155

In a given circuit, either or both of the solutions may be
in effect. In the first solution the circuit is quiescent (no
output signal). If you're trying to make an oscillator, a
no-signal condition is unacceptable. There are ways to
guarantee t,hat the second solution is the one that will
be in effect, and that the quiescent condition will be
excluded.

In order for the loop gain to have zero phase angle it is
necessary that the feedback element Zr have a positive
reactance. That is, it must be inductive. Then, the frequency at which the phase angle is zero is approximately the frequency at which

How Feedback Oscillators Work

where Xr is the reactance of Zr (the total Zr being Rr +
jXr, and C is the series combination of Cx! and CX2.

A feedback oscillator amplifies its own noise and feeds
it back to itself in exactly the right phase, at the oscillation frequency, to build up and reinforce the desired
oscillations. Its ability to do that depends on its loop
gain. First, oscillations can occur only at the frequency
for which the loop gain has a phase angle of 0 degrees.
Second build-up of oscillations will occur only if the
loop gain exceeds I at the frequency. Build-up continues until nonlinearities in the circuit reduce the average
value of the loop gain to exactly 1.
Start-up characteristics depend on the small-signal
properties of the circuit, specifically, the small-signal
loop gain. Steady-state characteristics of the oscillator
depend on the large-signal properties of the circuit,
such as' the transfer curve (output voltage vs. input
voltage) of the amplifier, and the clamping effect of the
input protection devices. These things will be discussed
mere fully further on. First \ve \"/i11 leek nt the basic
operation of the particular oscillator circuit, called the
"positive reactance" oscillator.

The Positive Reactance Oscillator
Figure 2 shows the configuration of the positive reactance oscillator. The inverting amplifier, working into
the impedance of the feedback network,' produces' an
output signal that is nominally 180 degrees out of phase
with its input. The feedback network must provide an
additional 180 degrees phase shift, such that the overall
loop gain has zero (or 360) degrees phase shift at the
oscillation frequency.

I

c=
,

In other words,
cuit.

CXl CX2
CXl + CX2

Zr and C form·a parallel resonant cir-

If Zr is an inductor, then Xr = wL; and the frequency
at which the loop gain has zero phase is the frequency
at which
1
wL=-

wC

or

1
w = .J[C
Noi'm3.lly, Zr is neit an inductor, but it must still have a
positive reactance in order for the circuit to oscillate.
There are some piezoelectric devices on the market that
show a positive reactance, and provide a more stable
oscillation frequency than an inductor will. Quartz
crystals can be, used where the oscillation frequency is
critical, and lower cost ceramic res_onators can be used
w4ere the frequency is less critical.
When the feedback element is a piezoelectric device,
this circuit configuration is called a Pierce oscillator.
The advantage of piezoelectric resonators lies in their
property of providing a wide range of positive teactimce
values over a very narrow range Qf frequencies. The
reactance will equal 1/wC at some frequency within
this range, so the oscillation frequency will be within
the same range. Typically, the width of this range is

230659-2

Figure 2~ Positive Reactance Oscillator

10-280

AP-155

only 0.3% of the nominal frequency of a quartz crystal,
and about 3% of the nominal frequency of. a ceramic
resonator. With relatively little design effort, frequency
accuracies of 0.03% or better -can be obtained with
quartz crystals, and 0.3% or better with ceramic resonators.

QUARTZ CRYSTALS
The crystal resonator is a thin slice of quartz sandwiched between two electrodes. Electrically, the device
looks pretty -much like a 5 or 6 pF capacitor, except
that over certain ranges of frequencies the crystal has a
positive (i.e., inductive) reactance.
The ranges of positive reactance originat~ in the piezoelectric property of quartz: Squeezing the crystal generates an internal E-field. The effect is reversible: Applying an AC E-field causes the crystal to vibrate. At certain vibrational frequencies there is a mechanical resonance. As the E-field frequency approaches a frequency
of mechanical resonance, the measured reactance of the
crystal becomes positive, as shown in Figure 3.

FREQUENCY

Xeo
-JX
FUNDAMENTAL

Crystal Parameters
Equivalent Circuit
Figure 4 shows an equivalent circuit that is used to
represent the crystal for circuit analysis.
The Rl-Ll-Cl branch is called the motivational arm of
the crystal. The values of these parameters derive from
the mechanical properties of the crystal and are constant for a given mode of vibration. Typical values for
various nominal frequencies are shown in Table 1.

SPURIOUS
RESPONSES

-

JX

To assure that an oscillator starts in the desired mode
on power-up, something must be done to suppress the
loop gain in the undesired frequency ranges. The crystal itself provides some protection against unwanted
modes of oscillation; too much resistance in that mode,
for example. Additionally, junction capacitances in the
amplifying devices tend to reduce the gain at higher
frequencies, and thus may discriminate against unwanted modes. In some cases a circuit fix is necessary, such
as inserting a trap, a phase shifter, or ferrite beads to
kill oscillations in unwanted modes.

/

/

---11'01-1- -

\

SYMBOL

-C:t:*J-

FIFTH MECHANICAL
OVERTONE

EQUIVALENT CIRCUIT

230659-4

THIRD MECHANICAL
OVERTONE

Figure 4. Quartz Crystal: Symbol and
Equivalent Circuit

230659-3

Figure 3. Crystal Reactance vs. Frequency
Typically there are several ranges of frequencies wherein the reactance of the crystal is positive. Each range
corresponds to a different mode of vibration in the crystal. The main resonsances are the so-called fundamental resp9nse and the third and fifth overtone responses.
The overtone responses shouldn't be confused with the
harmonics of the fundamental. They're not harmonics,
but different vibrational modes. They're not in general
at exact integer multiples of the fundamental frequency.
There will also be "spurious" responses, occurring typically a few hundred KHz above each main response.

Co is called the shunt capacitance of the crystal. This is
the capacitance of the crystal's electrodes and the mechanical holder. If one were to measure the reactance of
the crystal at a: freuqency far removed from a resonance
frequency, it is the reactance of this capacitance that
would be measured. It's normally 3 to 7 pF.
Table 1. Typical Crystal Parameters

10-281

Frequency
MHz

R1
ohms

L1
mH

C1
pF

Co
pF

2

100

520

0.012

4

4.608

36

117

0.010

2.9

11.25

19

8.38

0.024

5.4

AP-155

The series resonant frequency of the crystal is the frequency at which LI and CI are in resonance. This fre~
quency is given by .

the antiresonant frequency of the parallel combination
of the crystal and CL. This frequency is given by

1
fs=--21T~L1C1

At this frequency the impedance of the crystal is R I in
parallel with the reactance of Co. For most purposes,
this impedance is taken. to be just R J, since the reactance of Co is so much larger than RI.

These frequency formulas are derived (in Appendix A)
from the equivalent circuit of the crystal, using the assumptions that the Q of the crystal is extremely high,
and that the circuit external to the crystal has no effect
on the frequency other than to·.provide the load capacitance CL. The latter assumption is not precisely true,
but it is close enough for present ·purposes.

Load Capacitance
A crystal oscillator circuit such as the one shown in
Figure 2 (redrawn in Figure 5) operates at the frequency for which the crystal is IlIltiresonant (ie, paral1el~res­
onant) ,with the total capacitance across the crystal terminals external to the crystal. This total capacitance
external to the crystal is called the load capacitance.

"Series" vs. "Parallel" Crystals
There is no such thing as a "series cut" crystal as opposed to. a "parallel cut" crystal. There are different
cuts of crystal, having to do with the parameters of its
. motional arm .jn various frequency ranges,. but there is
no special cut for series or parallel operation.

As shown in Figure 5, the load capacitance is given by
CX1 CX2
CL = C
C
X1 + X2

..
+ Cstray

The crystal manufacturer needs to know the value of
CL in order to adjust the crystal to the specified fre.quency.

An oscillator is series resonant if the oscillation frequency is fs of the crystal. To operate the crystal at fs,
the amplifier has to be noninverting. When buying a
crystal for such an oscillator, one does not specify a
load c.apacitance. Rather, one specifies the loading condition as "series."
'
If a "series" crystal is put into an oscillator that has an
.inverting amplifier, it will oscillate in parallel resonance
with the load capacitance presented to the crystal by
the oscillator circuit, at a frequency slightly above fs. In
fact, at approximately
.

r--------c-----------l et

!
I

II

-----------~~,--------~
e"
ex.
I
I

1:

. .,...

)

fa = fs ( 1+ 2(C

iI

This frequency would typically be about 0.02% above
f s·

~--------------------~
.
CRYSTAL
r---------~~---------~

II
I

R,

L,

C,

Equivalent Series Resistance

I

I
I

~--------------~-~--~

C~ C.0»)

L

230659-6

Figure 5. Load CapaCitance
The adjustment involves putting the cryst~l.in .series
with the specified CL, and then "trimming" the crystal
to obtain resonance of the series combination of the
crystal and CL at the specified frequency. Because of
the high Q of the crystal, the resonant frequency of the
series combination of the crystal and CL is the same as

The "series resistance" often listed on quartz' crystal
data sheets is the real part of the crystal impedance at
the crystal's calibration frequency. This will be Rl if
the calibration frequency 18 the series resonant frequency of the crystal. If the crystal is calibrated for parallel
resonance with a load capacitance CL, the equivalent
series resistance will be

\

.

ESR = R1 ( 1

+ ~~r

The crystal manufacturer measures this resistance at
the calibration frequency during the same operation in
which the crystal is adjusted to the calibration frequency.

10-282

inter

AP·155

Frequency Tolerance
Frequency tolerance as discussed here is not a requirement on the crystal, but on the complete oscillator.
There are two types of frequency tolerances on oscillators: frequency acccuracy and frequency stability. Frequency accuracy refers to the oscillator's ability to run
at an exact specified frequency. Frequency stability refers to the constancy of the oscillation frequency.
Frequency accuracy requires mainly that the oscillator
circuit present to the crystal the same load capacitance
that it was adjusted for. Frequency stability requires
mainly that the load capacitance be constant.

In a positive reactance oscillator, if one assumes the
peak voltage across the crystal to be something in the
neighborhood of Vee, the power dissipation can be approximated as

This formula is derived in Appendix A. In a 5V system,
P rarely evaluates to more than a milliwatt. Crystals
with a standard 1 or 2 mW drive level rating can be
used in most digital systems.

MT -

In most digital applications the accuracy and stability
requirements on the oscillator are so wide that it makes
very little difference what load capacitance the crystal
was adjusted to, or what load capacitance the circuit
actually presents to the crystal. For example, if a crystal was calibrated to a load capacitance of 25 pF, and is
used in a circuit whose actual load capacitance is 50 pF,
the frequency error on that account would be less than
0.01%.

100000

10
1

In a positive reactance oscillator, the crystal only needs
to be in the intended response mode for the oscillator to
satisfy a 0.5% or better frequency tolerance. That's because for any load capacitance the oscillation frequency
is certain to be between the crystal's resonant and antiresonant frequencies.
Phase shifts that take place within the amplifier part of
the oscillator will also affect frequency accuracy and
stability. These phase shifts can normally be modeled as
an "output capacitance" that, in the positive reactance
oscillator, parallels CX2. The predictability and constancy of this output capacitance over temperature and
device sample will be the limiting factor in determining
the tolerances that the circuit is capable of holding.

Drive Level
Drive level refers to the power dissipation in the crystal. There are two reasons for specifying it. One is that
the parameters in the equivalent circuit are somewhat
dependent on the drive level at which the crystal is
calibrated. The other is that if the application circuit
exceeds the test drive level by too much, the crystal
may be damaged. Note that the terms "test drive level"
and "rated drive level" both refer to the drive level at
which the crystal is calibrated. Normally, in a microcontroller system, neither the frequency tolerances nor
the power levels justify much concern for this specification. Some crystal manufacturers don't even require it
for microprocessor crystals.

51 R3.58M

':-O-'--2000-'-~4000~"""6000-'--'-""6000"""'~'-.,..JOOOO
FREQUENCY (KHz)

230659-7

Figure 6. Ceramic Resonator Impedance vs.
Frequency (Test Data Supplied by NTK
Technical Ceramics)

CERAMIC RESONATORS
Ceramic resonators operate on the same basic principles as a quartz crsytal. Like quartz crsytals, they are
piezoelectric, have a reactance versus frequency curve
similar to a crystal's, and an equivalent circuit that
looks just like a crystal's (with different parameter values, however).
The frequency tolerance of a ceramic resonator is about
two orders of magnitude wider than a crystal's, but the
ceramic is somewhat cheaper than a crystal. It may be
noted for comparison that quartz crystals with relaxed
tolerances cost about twice as much as ceramic resonators. For purposes of clocking a microcontroller, the
frequency tolerance is often relatively noncritical, and
the economic consideration becomes the dominant factor.
Figure 6 shows a graph of impedance magnitude versus
frequency for a 3.58 MHz ceramic resonator. (Note
that Figure 6 is a graph of Izrl versus frequency, where

10-283

inter

AP-155

as Figure 3 is a'graph ofXrversus frequency.) Anumber of spurious responses are apparent in Figure 6. The
manufacturers state that spurious responses are more
prevalent in the lower frequency resonators (kHz
range) than in the higher frequency units (MHz range).
For our purposes only the MHz range ceramics need to
be considered.

frequency and the chip you want it to work with ..
They'll supply the resonators, a circuit diagram showing the positions and -values of 'other external components that may be required and a: guarantee that the
circuit will work properly at the ,specified frequency.

OSCILLATOR DESIGN
CONSIDERATIONS

----iIOI-I- - -

Designers of microcontroller systems have a number of
options to choose from for clocking the system. The
main decision is whether to use the "on-chip" oscillator
or an external oscillator. If the choice is to use the onchip oscillator, what kinds of external components are
needed to make it operate as advertised? If the choice is
to use an external oscillator, what type of oscillator
should it be?

SYMBOL

EQUIVALENT CIRCUIT

230659-8

Figure 7. Ceramic Resonator: Symbol and
Equivalent Circuit

Figure 7 shows the symbol and equivalent circuit for
the ceramic resonator, both of which are the same as
for the crystal. The parameters have different values,
however, as listed in Table 2.

The decisions have to be based on both economic and
technical requirements. In this section we'll discuss
some of the factors that should be considered.

r.l1..' \i
TALl

Table 2. Typical Ceramic Parameters
Frequency
MHz
3.56
6.0
8.0
11.0

R1
ohms
7.
8
7
10

L1
mH

0.; ;3

C1
pF
,19.6

0.094
0.092
0.057

8.3
4.6
3.9

------1

Co
pF
140
60
40
30

,

'0

c __

T .

.

.

I XTAL2I' ,
.,!,.L..:.,I----.,.-.J

230659-9

Figure 8. Using the "On-Chip" Oscillator

Note that the motional arm of the ceramic resonator
tends to have less resistance than the quartz crystal and
also a vastly reduced L,/C, ratio. This results. in the
motional arm having a Q (given by (l/R,) ~L,/C,) that
is typically two orders of magnitude lower than that of
a quartz crystal. The lower Q makes for a faster startup
of the oscilaltor and for a less closely controlled frequency (meaning that circuitry external to the resonator will have more influence on the frequency than with
a quartz crystal).
Another major difference is that the shunt capacitance
of the ceramic resonator.is an order of magnitude higher than Co of the quartz crystal and more dependent on
the frequency of the resonator.
The implications of these differences are not all obvious, but some will be indicated in the section on Oscillator Calculations.

On-Chip Oscillators
IiI most cases, the on-chip amplifier with the appropriate external components provides the most economical
solution to the clocking problem. Exceptions may arise
in severe environments when frequency tolerances are
tighter than about 0.01 %.
The external components that ,need to be added are a
positive reactance (normally a crystal or ceramic resonator) and the two capacitors Cx, and CX2, as shown
in Figure 8.
.

'

Crystal Specifications

-

Specificati()ns for an appropriate crystal are not ver'l
critical, unless the frequency is. Any fundamental-mode
crystal of med.ium or better quality can be used.

Specifications for Ceramic Resonators
Ceramic resonators are easier to specify than quartz
crystals. All the vendor wants to know is the desired
10-284

AP-155

We are often asked what maximum crystal resistance
should be specified. The best answer to this question is
the lower the better, but use what's available. The crystal resistance will have some effect on start-up time and
steady-state amplitude, but not so much that it can't be
comperisated for by appropriate selection of the capacitances CX! and CX2.
Similar questions are asked about specifications of load
capacitance and shunt capacitance. The best advice we
can give is to understand what these parameters mean
and how they affect the operation of the circuit (that
being the purpose of this Application Note), and then
decide for yourself if such specifications are meaningful
in your application or not. Normally, they're not, unless your frequency tolerances are tighter than about
0.1%.
Part of the problem is that crystal manufacturers are
accustomed to talking "ppm" tolerances with radio engineers and simply won't take your order until you've
filled out their list of specifications. It will help if you
define your actual frequency tolerance requirements,
both for yourself and to the .crystal manufacturer.
Don't pay for 0.003% crystals if your actual frequency
tolerance is 1%.

Oscillation Frequency
The oscillation frequency is determined 99.S% by the
crystal and up to about O.S% by the circuit external to
the crystal. The on-chip amplifier has little effect on the
frequency, which is as it should be, since. the amplifier
parameters are temperature and process dependent.
The influence of the on-chip amplifier on the frequency
is by means of its input and output (pin-to-ground) capacitances, which parallel CX! and CX2, and the
XTALI-to-XTAL2 (pin-to-pin) capacitance, which
parallels the crystal. The input and pin-to-pin capacitances are about 7 pF each. Internal phase deviations
from the nominal 180· can be modeled as an output
capacitance of 2S to 30 pF. These deviations from the
ideal have less effect in the positive reactance oscillator
(with the inverting amplifer) than in a comparable series resonant oscillator (with the noninverting amplifier) for two reasons: first, the effect of the output capacitance is lessened, if not swamped, by the off-chip capacitor; secondly, the positive' reactance oscillator is less
sensitive, frequency-wise, to such phase errors.

tor is being used, and also on application-specific requirements on start-up time and frequency tolerance.
Start-up time is sometimes more critical in microcontroller systems than frequency stability, because ofvarious reset and initialization requirements.
Less commonly, accuracy of the oscillator frequency is
also critical, for example, when the oscillator is being
used as a time base. As a general rule, fast start-up and
stable frequency tend to pull the oscillator design in
opposite directions.
Considerations of both start-up time and frequency stability over temperature suggest that CX! and CX2
should be about equal and at least 20 pF. (But they
don't have to be either.) Increasing the value of these
capacitances above some 40 or SO pF improves frequency stability. It also tends to increase the start-up time.
There is a maximum value (several hundred pF, depending on the value of R! of the quartz or ceramic
resonator) above which the oscillator won't start up at
all.
If the on-chip amplifier is a simple inverter, such as in
. the 80SI, the user can select values for CX!and CX2
between some 20 and 100 pF, depending on whether
start-up time or frequency stability is the more critical
parameter in a specific application. If the on-chip amplifier is a Schmitt Trigger, such as in the 8048, smaller
values of CX! must be used (S to 30 pF), in order to
prevent the oscillator from running in a relaxation
mode.
Later sections in this Application Note will discuss the
effects of varying CX! and CX2 (as well as other parameters), and will have more to say on their selection.
Placement of Components

Noise glitches arriving at XTALI or XTAL2 pins at
the wrong time can cause a miscount in the internal
clock-generating circuitry. These kinds of glitches can
be produced through capacitive coupling between the
oscillator components and PCB traces carrying digital
signals with fast rise and fall times. For this reason, the
oscillator components should be mounted close to the
chip and have short, direct traces to the XTALI,
XTAL2, and VSS pins.
Clocking Other Chips

Selection of CX1 and CX2

There are times when it would be desirable to use the
on-chip oscillator to clock other chips in the system.

Optimal values for the capacitors CX! and CX2 depend
on whether a quartz crystal or ceramic resona-

10-285

inter

AP-155

VCC

CLOCK
OUT
::t-_-'W~-_...j XTAL2

C..
t---iI--4-...jXTALl

230659-10

This can be done if an appropriate buffer is used. A
TTL buffer puts too much load on the on-chip amplifier for reliable start-up. A CMOS buffer (such as the
74HC04) can be used, if it's fast enough and if its VIH
and VIL specs are compatible with the available signal
amplitudes. Circuits such as shown in Figure 9 might
also be considered for these types of applications.
Clock-related signals are available at the TO pin in the
MCS-48 products, at ALE in the MCS-48 and MCS-51
lines, and the iACX-96 controllers provide a CLKOUT
signal.
.

A) DRIVING FROM XTAL2

VCC
lK

CLOCK
OUT

n~
C

-::

12

XTAL2

0

XTALI

C..

230659-11
B) DRIVING FROM XTAL 1

Figure 9. Using the On-Chip Oscillator
to Drive Other Chips

External OSCillators
When technical requirements dictate the use of an external oscillator, the external drive requirements for the
microcontroller, as published in the data sheet, must be
carefully noted. The logic levels are not in general TTLcompatible. And each controller has its idiosyncracies
in this regard. The 8048, for example, re.quires that
both XTAL1 and XTAL2 be driven. The 8051 can be
driven that way, but the data sheet suggest the simpler
method of grounding XTAL1 and driving XTAL2. For
this method, the driving source must be capable of sinking some current when XTAL2 is being driven low.
For the external oscillator itself, there are basically two
choices: ready-made and home-grown.

10-286

inter

AP-155

Frequency Tolerance: ± 0.1 % Overall O·C-70·C

TTL Crystal Clock Oscillator

The HS-l00, HS-200, & HS-500 all-metal package series of oscillators are TTL compatible & fit a DIP
layout. Standard electrical specifications are shown
below. Variations are available for special applications.
Frequency Range: HS-100-3.5 MHz to 30 MHz
HS-200-225 KHz to 3.S MHz
HS-S00-25 MHz to 60 MHz

Hermetically Sealed Package

Mass spectrometer leak rate max.
1 X 10- 8 atmos. cc/sec: of helium
Output Waveform
-[TAt-

-1TF-

- -~

[E-

- - - - ---2.4 VDe

- - - ----14 VDe

=~
----

___

_ ___ 0.4 VDe
--VOL
.0 VDe

60% Max

230659-12

INPUT
HS-100

HS-200

HS-500

3.5 MHz-20 MHz

20 + MHz-30 MHz

225 KHz-4.0 MHz

25 MHz-SO MHz

5V ±10%

5V ±10%

5V ±10%

5V ±10%

40mA

85mA

50mA

Supply Voltage

(Vcd
Supply Current
(Icd max.

30mA

OUTPUT
HS-100

VOH (Logic "1 ")
VOL (Logic "0")
Symmetry
TR, TF (Rise &
Fall Time)
Output Short
Circuit Current
Output Load

HS-200

HS-500

3.5 MHz-20 MHz

20 + MHz-30 MHz

225 KHz-4.0 MHz

25 MHz-SO MHz

+2.4Vmin. 1
+O.4V max. 3
S0/40%5

+2.7Vmin.2
+0.5V max. 4
S0/40%5

+2.4V min.l
+0.4Vmax. 3
55/45%5

+2.7V min. 2
+0.5V max. 4
60/40%5

< 10 ns 6

< 5 ns6

< 15 ns 6

< 5 ns 6

18 mA min.
1 to 10 TTL Loads 7

40 mAmin.
1 t9 10 TTL Loads8

18mAmin.
1 to 10 TTL Loads 7

40mAmin.
1 to 10 TTL Loads 8

CONDITIONS

110 source = - 400 p.A max.
210 source = -1;0 mA max.
310 sink = 1S.0 mA max.

410 sink = 20.00 mA max.
5Vo = 1.4V
6(0.4V to 2.4V)
Figure 10.l;Ire-Packaged Oscillator

"Reprinted with the permission of @Midland·Ross Corporation

1982.

10-287

71.6 mA per load
82.0 mA per load

Data·

inter

Ap·155

Prepackaged oscillators are available from most crystal
manufacturers, and have the advantage that the system
designer can treat the oscillator as a black box whose
performance is guaranteed by, people who carry many
years of experience in designing and' building oscillators. Figure 10 shows a typical' data sheet for some
prepackaged oscillators. Oscillators are also available
with complementary outputs.

The feedback resistance has to be quite low, however,
since it must conduct current sourced by the input pin
without allowing the DC input voltage to get too far
above the DC output voltage. For biasing purposes, the
feedback resistance should not exceed a- few k-ohms.
But shunting the crystal with such a low resistance does
not encourage, start-up:

If the oscillator is to drive the microcontroller directly,
one will want to make a careful comparison between
the external drive requirements in the microcontroller
data sheet and the oscillator's output logic levels and
test conditions.

lK

lK

1.

01 ",
74LS04

OUTPUT

If oscillator stability is less critical than cost, the user
may prefer to go with an in-house design. Not without
some precautions, however.

Rx
(SEVERAL kO)

It's easy to design oscillators that work. Almost all of
them do work, even if the designer isn't too clear on
why. The key point here is that almost all of them
work. The problems begin when the system goes into
production, and marginal units commence malfunctioning in the field. Most digital designers, after all, are
not very adept at designing oscillators lor production.

en

ex.

230659-13
A) TTL OSCILLATOR
lMU
74e04

OUTPUT

Oscillator design is somewhat of a black art, with the
quality of the finished product being very dependent on
the designer's experience and intuition. For that reason
the most important consideration in any design is to
have an adequate preproduction test program. Preproduction tests are discussed later in this Application
Note. Here we will discuss some of the design options
and take a look at some commonly used configurations.

Gate Oscillators versus Discrete
Devices
Digital systems designers are understandably reluctant
to get involved with discrete devices and their peculiarities (biasing techniques, etc.). Besides, the component
count for these circuits tends to be quite a bit higher
than what a digital designer is used to seeing for that
amount of functionality. Nevertheless, if there are unusual requirements on the accuracy and stability of the,
clock frequency, it should be noted that discrete device
oscillators can be tailored to suit the exact needs of the
application and perfected to a level that would be difficult for a gate oscillator to approach.
In most cases, when an external oscillator is needed, the
designer tends to rely on some form of a gate oscillator.
A TTL inverter with a resistor connecting the output to
the input makes a suitable inverting amplifier. The resistor holds the inverter in the transition region between logical high and low, so that at least for start-up
purposes the inverter is a linear amplifier.

230659-14
B) CMOS OSCILLATOR

Figure 11. Commonly Used Gate Oscillators

Consequently, the configuration in Figure llA might
be suggested. By breaking Rr into two parts and ACgrounding the midpoint, one achieves the DC feedback
required to hold the inverter in its active region, but
without the negative signal feedback that is in effect
telling the circuit not to oscillate. However, this biasing
scheme will increase the start-up time, and relaxationtype oscillations are also possible.
A CMOS inverter, such as the 74HC04, might work
better in this application; since a larger Rr can be used
to hold the inverter in its linear region.
, Logic gates tend to have a fairly low output resistance,
which destabilizes the oscillator. For that reason a resistor Rx is often added to the feedback network, as
shown in Figures IIA and B. At higher frequencies a
20 or 30 pF capacitor is sometimes used in the Rx position, to compensate for some of the internal propagation delay.
Reference I contains an excellent discussion of gate oscillators, and a number of design examples.

10-288

AP-155

Fundamental versus Overtone Operation

It's easier to design an oscillator circuit to operate in
the resonator's fundamental response mode than to design one for overtone operation. A quartz crystal whose
fundamental response mode covers the desired frequency can be obtained up to some 30 MHz. For frequencies
above that, the crystal might be used in an overtone
mode.

230659-15

Figure 12. "Series Resonant" Gate Oscillator

Several problems arise in the design of an overtone oscillator. One is to stop the circuit from oscillating in the
fundamental mode, which is what it would really rather
do, for a number of reasons, involving both the amplifying device and the crystal. Ail additional problem with
overtone operation is an increased tendency to spurious
oscillations. That is because the Rl of various spurious
modes is likely to be about the same as Rl of the intended overtone response. It may be necessary, as suggested in Reference I, to specify a "spurious-to-mainresponse" resistance ratio to avoid the possibility of
trouble.
Overtone oscillators are not to be taken lightly. One
would be well advised to consult with an engineer who
is knowledgeable in the subject during the design phase
of such a circuit.
Series versus Parallel Operation

Series resonant oscillators use noninverting amplifiers.
To make a noninverting amplifier out of logic gates
requires that two inverters be used, as shown in Figure
12.
This type of circuit tends to be inaccurate and unstable
in frequency over variations in temperature and Vee. It
has a tendency to oscillate at overtones, and to oscillate
through Co of the crystal or some stray capacitance
rather than as controlled by the mechanical resonance
of the crystal.
The demon in series resonant oscillators is the phase
shift in the amplifier. The series resonant oscillator
wants more than just a "noninverting" amplifier-it
wants a zero phase-shift amplifier. Multistage noninverting amplifiers tend to have a considerably lagging
phase shift, such that the crystal reactance must be capacitive in order to bring the total phase shift around
the feedback loop back up to O. In this mode, a "12
MHz" crystal may be running at 8 or 9 MHz. One can
put a capacitor in series with the crystal to relieve the
crystill of having to produce all of the required phase
shift, and bring the oscillation frequency closer to fs.
However, to further complicate the situation, the amplifier's phase shift is strongly dependent on frequency,
temperature, VCC, and device sample.

Positive reactance oscillators ("parallel resonant") use
inverting amplifiers. A single logic inverter can be used
for the amplifier, as in Figure II. The amplifier's phase
shift is less critical, ,?ompared to a series resonant circuit, and since only one inverter is involved there's less
phase error anyway. The oscillation frequency is effectively bounded by the resonant and antiresonant frequencies of the crystal itself. In addition, the feedback
network includes capacitors that parallel the input and
output terminals of the amplifier, thus reducing the effect of unpredictable capacitances at these points.

MORE ABOUT USING THE "ON-CHIP"
OSCILLATORS
In this section we will describe the on-chip inverters on
selected microcontrollers in some detail, and discuss
criteria for selecting components to work with them.
Future data sheets will supplement this discussion with
updates and information pertinent to the use of each
chip's oscillator circuitry.

Oscillator Calculations
Oscillator design, though aided by theory, is still largely
an empirical exercise. The circuit is inherently nonlinear, and the normal analysis parameters vary with instantaneous voltage. In addition, when dealing with the
on-chip circuitry, we have FETs being used as resistors,
resistors being used as interconnects, distributed delays,
input protection devices, parasitic junctions, and processing variations.
Consequently, oscillator calculations are never very
precise. They can be useful, however, if they will at
least indicate the effects of variations in the circuit parameters on start-up time, oscillation frequency, and
steady-state amplitude. Start-up time, for example, can
be taken as an indication of start-up reliability. If preproduction tests indicate a possible start-up problem, a
relatively inexperienced designer can at least be made
aware of what parameter may be causing the marginality, and what direction to go in to fix it.

10-289

inter

Ap·155

vee

PHASE

.1 00'.j:--:---_
50'
F. MHz
0' ~--+---_\+_----+4.607,
4.609

-50'

XTAL2

XTALl

",
.
230659-16 .
A) 8081-Type Circuit Configuration during Start-Up.
(Excludes Input Protection Devices.) '.

MAGNITUDE
20

15

~~r----~-------I
~
I
Z, ______
-'
Ro

r---------,
I!
'
I

~I'
I

L.._

c..

10

I

I

1
I I'

lit

I

z,---.- :---1
• ..l

I
I

L._

5

I
I

4.607

CXI I
___
..II
I

L. _____________,.JI

4.609

I--lkHz-1

v,

!

4.609

230659-18

Figure 14; Loop Gain versus Frequency
(4.608 MHz Crystal)

230659-17
8) AC-Equlvalent Of (A)

The gain of the feedback network is

Figure 13. Oscillator Circuit Model Used
In Start-Up Calculations

The analysis used here is mathematically straightforward but algebraically intractable. That means it's relatively easy to understand andprogr8.Jll into a computer,
but it will not yield a neat formula that gives, say,
steady-state amplitudl; as ,a function of this or that list
of parameters. A listing of a BASIC program that implements the analysis will be found in Appendix II.
When the circuit is first powered, up, and before' the
oscillations have commenced(and if the oscillations/ail
to commence), the oscillator can be treated as a small
signal linear amplifier with feedback. In that case, standard small-signal analysis techniques can be used to
determine start-up characteristics. The circuit model
used in this analysis is shown in Figure 13.
The circuit approximates that there are no high~f~e­
quency effects within the amplifier itslef, such that. Its
high-frequency behavior is dominated by the load Impedance ZL. This is a reasonable approximation for sin"
gle-stage amplifiers of the type used in BOSl-type devices. Then the gain of the amplifier as 'a function of frequency is

And the loop gain is
,
f3A =

Zj

~j + Zt x

AvZL
ZL + Ro

The impedances ZL, Zr, and Zj are defined in Figure
13B.
.
Figure 14 shows the way the loop gain thus calculated
(using typical 805 I-type parameters and a 4.60~ MHz
crystal) varies with frequency. The frequency ofmterest
is the one for which the phase of the loop gain is zero.
The accepted criterion for start-up is that the magnitude of the loop gain must exceed unity atthis frequency. This is the frequency at which· the circuit is in resonance. It cOrresponds very closely with the antiresonant
frequency of the motional arm of the crystal in parallel
with CL.
'
.
Figure 15 shows the way the loop gain varies with frequency when the parameters of a 3.58 MHz cei'~ic
resonator are used in place of a crystal (the amplifier
parameters being typical 8051, as in Figure 14). Note
the different frequency scales.

10-290

AP-155

PHASE

I...

x

,·pl.".
a

-8
SO'

Af\Of\".1

\]V \TV

4

x

O'+---+--t---<--+",,""+---+--t-__

A) Poles In Ihe Left-Hall Plane:

-50'

1(1) -

230659-20
e- at sin (",I + 8)

J...

'"P"'"
20

X
+a a

MAGNITUDE

X
15

230659-21
B) Poles In Ihe Right-Hail Plane: I(t) - e+ 8t sin (",t

10

+

8)

5

3.55

3.57

3.59

~~

f\f\f\f\f\.t

V VVV \

F,MHz

230659-19

Figure 15. Loop Gain versus Frequency
(3.58 MHz Ceramic)

C) Poles the J", Axis: I(t) - sin (",t

230659-22

+ 8)

Figure 16. Do You Know Where Your
Poles Are Tonight?

Start-Up Characteristics

The gain function of interest in oscillators is 1/(1

It is common, in studies of feedback systems, to examine. the behavior of the closed loop gain as a function of
complex frequency s = CT + jCll; specifically, to determine the location of its poles in the complex plane. A
pole is a point on the complex plane where the gain
function goes to infinity. Knowledge of its location can
be used to predict the response of the system to an
input disturbance.
The way that the response function depends on the location of the poles is shown in Figure 16. Poles in the
left-half plane cause the ·response function to take the
form of a damped sinusoid. Poles in the right-half plane
cause the response function to take the form of an exponentially growing sinusoid. In general,
vet) -

eat sin (wt

+ 8)

where a is the real part of the pole frequency. Thus if
the pole is in the right-half plane, a is positive and the
sinusoid grows. If the pole is in the left-half plane, a is
negative and the sinusoid is damped.
The same type of analysis can usefully be applied to
oscillators. In this case, however, rather than trying to
ensure that the poles are in the left-half plane, we
would seek to ensure that they're in the right-half plane.
An exponentially growing sinusoid is exactly what is
wanted from an oscillator that has just been powered
up.

fJA). Its poles are at the complex frequencies where fJA
= 1LO", because that value of fJA causes the gain func-

tion to go to infinity. The oscillator will start up if the
real part of the pole frequency is positive. More importantly, the rate at which it starts up is indicated by how
much greater than 0 the real part of the pole frequency
is.
The circuit in Figure 13B can be used to find the pole
frequencies of the oscillator gain function. All that
needs to be done is evaluate the impedances at complex
frequencies CT + jCll rather than just at CIl, and find the
value of CT + jCll for which fJA = 1LO·. The larger that
value of CT is, the faster the oscillator will start up.
Of course, other things besides pole frequencies, things
like the VCC rise time, are at work in determining the
start-up time. But to the extend that the pole frequencies do affect start-up time, we can obtain results like
those in Figures 17 and 18.
To obtain these figures the pole frequencies were computed for various values of capacitance Cx from
XTAL1 and XTAL2 to ground (thus CX! = CX2 =
ex). Then a "time constant" for start-up was calculat1
ed as Ts = - where CT is the real part of the pole freCT

quency (rad/sec), and this time constant is plotted versus Cx.

10-291

inter

AP-155

As 'previously mentioned, start-up time can be taken as
an indication of start-up reliability. Start-up problems
are normally associated with CXl and CX2 being too
small or too large for a given resonator. If the parameters of the resonator are known, curves such as in Figure 17 or 18 can be generated to define acceptable
ranges of values for these capacitors.

TB• MILLISECONDS

.5
.4
.3

As the oscillations grow in amplitude, they reach a level at which they undergo severe clipping within the amplifier, in effect reducing the amplifier gain. As the amplifier gain decreases, the poles move towards the jCLI
axis. In steady-state, the poles are on the jCLI axis and
the amplitude of the oscillations is constant. .'

.2
.1

Cx.pF

10

30

IE

50

--~

-

It
I

i
I

X2:

~

[1.

~

III

90

110

230659-23
TB• ,.sEC

c:;

50

.... .... .

...

vee:

70

•

•

--

:40

I

I

30
20

...

··· n
·' ·
II

Cx-pF

10

-

o.~-+

40 ,

230559-24

__

60

~

60

__

+-~

100

__~__~__

120

140

160

230659-26

vec:

X2:

230659-25

Figure 17. Oscillator Start-Up (4;608 MHz Crystal
from Standard Crystal Corp.)

A short time constant means faster: startCup. A long
time constant means slow start-up. Observations of ace
tual start-ups are shown in the figures. Figure 17 is for
a typical 8051 with a 4.608 MHz crystal supplied by
Standard Crystal Corp .• and Figure 18 is for a typical
8051 with a 3.58 MHz ceramic resonator supplied by
NTK Technical Ceramics, Ltd.
.
It can be seen in Figure 17 that, for this crystal, values
of Cx between 30 and 50 pF minimize start-up time,

but that the exact value in this range is not particularly
important, even if the start-up time itself is .critical..

230659-28

Figure 18. Oscillator Start-Up (3.58 MHz Ceramic
. Resonator from NTK Technical Ceramics)

10-292

inter

AP-155

VOLTS

o
1c~a

and source connected to ground (VSS), as shown in
Figure 20 for the 8051, and in Figure 21 for the 8048.
Its function is to limit the positive voltage at the gate of
the input FET to the avalanche voltage of the drain
junction. If the input pin is driven below VSS, the drain
and source of the protection FET interchange roles, so
its gate is connected to what is now the drain. In this
condition the device resembles a diode with the anode
connected to VSS.

XTAL2

8051
XTALI

"::" C.

•
20 40

60

80 100 120 140

There is a parasitic pn junction between the ohmic resistor and the substrate. In the ROM parts (8015, 8048,
etc.) the substrate is held at approximately - 3V by the
on-chip back-bias generator. In the EPROM parts
(8751, 8748, etc.) the substrate is connected to VSS.

·160 180 200 220
-1

Ca-pF

-2
230659-29
A) Signal Levels at XTAL 1
VOLTS
5

__

The effect of the input protection circuitry on the oscillator is that if the XTALI signal goes negative, its negative peak is clamped to - VDS of the protection FET in
the ROM parts, and to about -0.5V in the EPROM
parts. These negative voltages on XTALI are in this
application self-limiting and nondestructive.

calculated

• experimental
pol,n'.

VOL at XTAL2

20 40

60

The clamping action does, however, raise the DC level
at XTALl, which in turn tends to reduce the positive
peak at XTAL2. The waveform at XTAL2 resembles a
sinusoid riding on a DC level, and whose negative
peaks are clipped off at zero.

80 100 120 140 160 180 200 220

-1

230659-30
B) Signal Levels at XTAL2'

Figure 19. Calculated and Experimental SteadyState Amplitudes vs. Bulk Capacitance from
XTAL 1 and XTAL2 to Ground

Steady·State Characteristics
Steady-state analysis is greatly complicated by the fact
that we are dealing with large signals and nonlinear
circuit response. The circuit parameters vary with instantaneous voltage, and a number of clamping and
clipping mechanisms come into play. Analyses that
take all these things into account are too complicated to
be of general use, and analyses that don't take them
into account are too inaccurate to justify the effort.
. There is a steady-state analysis in Appendix B that
takes some of the complications into account and ignores others. Figure 19 shows the way the steady-state
amplitudes thus calculated (using typical 8051 parameters and a 4.608 MHz crystal) vary with equal bulk
capacitance placed from XTALl and XTAL2 to
'ground. Experimental results are shown for comparison.
The waveform at XTALl is a fairly clean sinusoid. Its
negative peak is normally somewhat below zero, at a
level which is determined mainly by the input protection circuitry at XTAL 1.
The input protection circuitry consists of an ohmic resistor and an enhancement-mode FET with the gate

Since it's normally the XTAL2 signal that drives the
internal clocking circuitry, the question naturally arises
as to how large this signal must be to reliably do its job.
In fact, the XTAL2 signal doesn't have to meet the
same VIH and VIL specifications that an external driver would have to. That's because as long as the oscillator is working, the on-chip amplifier is driving itself
through its own 0-to-1 transition region, which is very
nearly the same as the O-to-l transition region in the
internal buffer that follows the oscillator. If some processing variations move the transition level higher or
lower, the on-chip amplifier tends to compensate for it
by the fact that its own transition level is correspondingly higher or lower. (In the 8096, it's the XTAL1
signal that drives the internal clocking circuitry, but the
same concept applies.)
The main concern about the XTAL2 signal amplitude
is an indication of the general health of the oscillator.
An amplitude of less than about 2.5V peak-to-peak indicates that start-up problems could develop in some
units (with low gain) with some crystals (with high R!).
The remedy is to either adjust the values of CX! and/or
CX2 or use a crystal,with a lower R!.
The amplitudes at XTALl and XTAL2 can be adjusted
by changing the ratio of the capacitors from XTAL1
and XTAL2 to ground. Increasing the XTAL2 capacitance, for example, decreases the amplitude at XTAL2
and increases the amplitude at XTALI by about the
same amount. Decreasing both caps increases both amplitudes.

10-293

inter

AP·155

Pin Capacitance

Internal pin-to-ground and pin-to-pin capacitances at
XTALl and XTAL2 will have some effect on the oscillator. These capacitances are normally taken to be in
the range of 5 to 10 pF, but they are extremely difficult
to evaluate. Any measurement of one such capacitance
will necessarily include effects from the others. One advantage of the positive reactance oscillator is that the
pin-to-ground capacitances are paralleled by external
bulk capacitors, so a precise determination of their val~
ue is unnecessary. We would suggest that there is little
justification for more precision than to assign them a
value of 7 pF (XTAL1-to-ground and XTAL1-toXTAL2). This value is probably not in error by J:l1ore
than 3 or 4 pF.
The XTAL2-to-ground capacitance is not entirely "pin
capacitance," but more like an "equivalent output capacitance" of some 25 to 30 pF, having to include the
effect of internal phase delays. This value will vary to
some extent with temperature, processing, and frequency.
MCS®·51 Oscillator

The on-chip amplifier on the HMOS MCS-51 family is
shown in Figure 20. The drain load and feedback "resistors" are seen to be field-effect transistors. The drain
load FET, RD, is typically equivalent to about lK to 3
K-ohms. As an ,amplifier, the low frequency voltage
gain is normally between - 10 and - 20, and the output resistance is effectively RD.

VCC

used than those which minimize start-up time: Larger
values than those can be used in applications where
increased frequency stability is desired, at some sacrifice in start-up time.
Standard Crystal Corp. (Reference B) studied the use of
their crystals with the MCS-51 family using skew sample supplied by Intel. They suggest putting 30 pF ca~
pacitors from XTALl and XTAL2 to ground, if the
crystal is specified as described in Reference B. They
noted that in that configuration and with crystals thus
specified, the frequency accuracy was ± 0.01 % and the
frequency stability was ± 0.005%, and that a frequency
accuracy of ±0.005% could be obtained by substituting a 25 pF fixed cap in parallel with a 5-20 pF trimmer for one of the 30 pF caps.
MCS-51 skew samples have 'also been supplied to a
number of ceramic resonator manufacturers for characterization with their products. These companies should
be contacted for application information on their products. In general, however, ceramics tend to want somewhat larger values for CX! and CX2 than quartz crystals do. As shown in Figure 1B, they start up a lot faster
that way.
In some application the actual frequency tolerance required is only 1% or so, the user being concerned mainly that the circuit will osci!!ate. In that case, eXt and
Cxz can be selected rather freely in the range of 20 to
BOpF.
As you can see, "best" values for these components and
their tolerances are strongly dependent on the applica,tion and its requirements. In any case, their suitability
should be verified by environmental testing before the
design is submitted to production.
MCS®·48 OSCillator "

TO INTERNAL
CIRCUITRY

The NMOS and HMOS MCS-4B oscillator is shown in
Figure 21. It differs from the B051 in that its inverting

VCC
XTAL2

230659-31

TO INTERNAL
CIRCUITRY

Figure 20_ MCS®·51 Oscillator Amplifier

The B0151 oscillator is normally used with equal bulk
capacitors placed externally from XTALl to ground
and from XTAL2 to ground.'To determine a reasonable value of capacitance to use in these positions, given
a crystal of ceramic resonator of known parameters,
one can use the BASIC analysis in Appendix II to generate curves such as in Figures 17 and lB. This procedure will define a range of values that will minimize
start-up time. We don't suggest that smaller values be

10-294

XTAL2

230659-,32

Figure 21. MCS®·48 OSCillator Amplifier

AP-155

v.

more slowly, but it eventually takes over and dominates
the operation of the cirucit. This is shown in Figure
23A.

~ hysteresis

5V

Due to processing variations, some units seem to have a
harder time coming out of the relaxation mode, particularly at low temperatures. In some cases the resonator
oscillations may fail entirely, and leave the device in the
relaxation mode. Most units will stick in the relaxation
mode at any temperature if Cx! is larger than about 50
pF. Therefore, Cx! should be chosen with some care,
particularly if the system must operate at lower temperatures.

.2V

v,
LTP

UTP

230659-33

Figure 22. Schmitt Trigger Characteristic

amplifier is a Schmitt Trigger. This configuration was
chosen to prevent crosstalk from the TO pin, which is
adjacent to the XTALI pin.
All Schmitt Trigger circuits exhibit a hysteresis effect,
as shown in Figure 22. The hysteresis is what makes it
less sensitive to noise. The same hysteresis allows any
Schmitt Trigger to be used as a relaxation oscillator.
All you have to do is connect a resistor from output to
input, and a capacitor from input to ground, and the
circuit oscillates in a relaxation mode as follows.
If the Schmitt Trigger output is at a logic high, the
capacitor commences charging through the feedback
resistor. When the capacitor voltage reaches the upper
trigger point (UTP), the Schmitt Trigger output
switches to a logic low and the capacitor commences
discharging through the same resistor. When the capacitor voltage reaches the lower trigger point (LTP), the
Schmitt Trigger output switches to a logic high again,
and the sequence repeats. The oscillation frequency is
determined by the RC time constant and the hysteresis
voltage, UTP-LTP.
The 8048 can oscillate in this mode. It has an internal
feedback resistor. All that's needed is an external capacitor from XTAL I to ground. In fact, if a smaller
external feedback resistor is added, an 8048 system
could be designed to run in this mode. Do it at your own
risk! This mode of operation is not tested, specified,
documented, or encouraged in any way by Intel for the
8048. Future steppings of the device might have a different type of inverting amplifier (one more like the
8051). The CHMOS members of the MCS-48 family do
not use a Schmitt Trigger as the inverting amplifier.
Relaxation oscillations in the 8048 must be avoided,
and this is the major objective in selecting the off-chip
components needed to complete the oscillator circuit.
When an 8048 is powered up, if VCC has a short rise
time, the relaxation mode starts first. The frequency is
normally about 50 KHz. The resonator mode builds

One method that has proven effective in all units to
-40·C is to put 5 pF from XTALI to ground and 20
pF from XTAL2 to ground. Unfortunately, while this
method does discourage the relaxation mode, it is not
an optimal choice for the resonator mode. For one
thing, it does not swamp the pin capacitance. Also, it
makes for a rather high signal level at XTALI (8 or 9
volts peak-to-peak).
The question arises as to whether that level of signal at
XTLAI might damage the chip. Not to worry. The
negative peaks are self-limiting and nondestructive. The
positive peaks could conceivably damage the oxide, but
in fact, NMOS chips (eg, 8048) and HMOS chips (eg,
8048H) are tested to a much higher voltage than that.
The technology trend, of course, is to thinner oxides, as
the devices shrink in size. For an extra margin of safety,
the HMOS II chips (eg, 8048AH) have an internal diode clamp at XTALI to VCC.
In reality, Cx! doesn't have to be quite so small to
avoid relaxation oscillations, if the minimum operating
temperature is not - 40·C. For less severe temperature
requirements, values of capacitance selected in much
the same way as for an ,80S I can be used. The circuit
should be tested, however, at the system's lowest temperature limit.
Additional security against relaxation oscillations can
be obtained by putting a 1M-ohm (or larger) resistor
from XTALI to VCC. Pulling up the XTALI pin this
way seems to discourage relaxation oscillations as effectively as any other method (Figure 23B).
Another thing that discourages relaxation oscillations is
low VCC. The resonator mode, on the other hand is
much less sensitive to VCC. Thus if VCC comes up
relatively slowly (several milliseconds rise time), the
resonator mode is normally up and running before the
relaxation mode starts (in fact, before VCC has even
reached operating specs). This is shown in Figure 23C.
A secondary effect of the hysteresis is a shift in the
oscillation frequency. At low frequencies, the output
signal from an inverter without hysteresis leads (or
lags) the input by '180 degrees. The hysteresis in a
Schmitt Trigger, however, causes the output to lead the

10-295

inter

AP-155

input by less than 180 degrees (or lag by more than ISO
degrees), by an amount that depends on the signal amplitude, as shown in Figure 24. At higher frequencies,
there are additional phase shifts due to the various reactances in the circuit, but the phase shift due to the hysteresis is still present. Since the total phase shift in the
oscillator's loop gain is necessarily 0 or 360 degrees, it
is apparent that as the oscillations build up, the frequency has to change to allow the reactances to compensate for the hysteresis. In normal operation, this additional phase shift due to hysteresis does not exceed a
few degrees, and the resulting frequency shift is negligible.

Kyocera, a ceramic resonator manufacturer, studied
the use of some of their resonators (at 6.0 MHz, S.O
MHz, and 11.0 MHz) with the S049H. Their conclusion as to the value of capacitance to use at XTAL 1 and
XTAL2 was that 33 pF is appropriate at all three frequencies. One should probably follow the manufacturer's recommendations in this matter, since they will
guarantee operation.
Whether one should accept these recommendations and
guarantees without further testing is, however, another
matter. Not all users have found the recommendations
to be without occasional problems. If you run into diffi-

27pF

h~

XTALI

0

VCC:

8048

XTAL2

230659-34

XTAL2:

A) When VCC Comes Up Fast, Relaxation Oscillations '
Start First. But Then the Crystal Takes Over.

230659-37

vee

h

lMIl

VCC:

27pF

,

XTALI

0

8048

1--6----l

....

XTAL2

XTAL2:

27pF

230659-35
B) Weak Pullup (1 Mn or More) on XTAL 1
Discourages Relaxation Mode.

230659-38

27pF

VCC:

XTALI

h"

0

8048

XTAL2

XTAL2:

230659-36

C) No Relaxation Oscillations When VCC Comes Up
More Slowly.

230659-39

Figure 23. Relaxation Oscillations in the 8048

10-296

inter

AP-155

culties using their recommendations, both Intel and the
ceramic resonator manufacturer want to know about it.
It is to their interest, and ours, that such problems be
resolved.

It will be helpful to build a test jig that will allow the
oscillator circuit to be tested independently of the rest
of the system. Both start-up and steady-state characteristics should be tested. Figure 25 shows the circuit that
A) Software for Oscillator Test

SOURCE
ORG 0000 H
JMP
ORG OOOB H
CPL
RETI
ORG 0001BH
CPL
DJNZ
CPL
RETI
START:
MOV
MOV
MOV

230659-40
A) Inverter Without Hysteresis: Output Leads Input by 180'.

MOV
MOV
JMP

START
Tl

;TlMER 0 INTERRUPT:
; TOGGLE Tl

Pl.l
P2,$
Pl.0

;TIMER 1 INTERRUPT:
TOGGLE CRO TRIGGER
DELAY
TOGGLE VCC CONTROL

TH1, #OFAH ;TIMER 1 RELOAD VALUE
TL1, #OFAH ;START TLl AT RELOAD VALU
TMOD, # 61H ;TlMER 1 TO COUNTER, AUTO
;RELOAD
;TIMER 0 TO TIMER, 16-BIT
IE, # BAH
;ENABLE TIMER. INTERRUPTS
;ONLY
TCON, #50H ;TURN ON BOTH TIMERS
S
;IDLE

END
.+5V

PI.G

vee

P1.1

f

230659-41
B) Inverter With Hysteresis: Output Leads
Input by Less than 180'.

Figure 24. Amplitude-Dependent Phase
Shift in Schmitt Trigger

Preproduction Tests
An oscillator design should never be considered ready

for production until it has proven its ability to function
acceptably well under worst-case environmental conditions and with parameters at their worst-case tolerance
limits. Unexpected temperature effects in parts that
may already be near their tolerance limits can prevent
start-up of an oscillator that works perfectly well on the
bench. For example, designers often overlook temperature effects in ceramic capacitors. (Some ceramics are
down to 50% of their room"temperature values at
- 20"C and + 60°C). The problem here isn't just one of
frequency stability, but also involves start-up time and
steady-state amplitude. There may also be temperature
effects in the resonator and amplifier.

10-297

PI.Gor P1.1
TO
OSCILLOSCOPE
TRIGGER

vee
8051

Ell
ALE
TO FREQ.
COUNTER

230659-42
B) Oscillator Test Circuit (Shown for 8051 Test)

Figure 25. Oscillator Test Circuit and Software

AP-155

was used to obtain the oscillator start-up photographs
in this Application Note. This circuit or a modified
version of it would make a convenient test-vehicle. The
oscillator and its relevant components can be physically
separated from the control circuitry, and placed in a
temperature chamber.
Start-up should be observed under a variety of conditions, including low VCC and using slow and fast VCC
rise times. The oscillator should not be reluctant to
start up even when VCC is below its spec value for the
rest of the chip. (The rest of the chip may not function,
but the oscillator should work.) It should also be verified that start-up occurs when the resonator has more
than its upper tolerance limit of series resistance. (Put
some resistance in series with the resonator for this
test.) The bulk capacitors from XTALI and XTAL2 to
ground should also be varied to their tolerance limits.
The same circuit, with appropriate changes in the software to lengthen the "on" time, can be used to test the
steady-state characteristics of the oscillator, specifically
the frequency, frequency stability, and amplitudes at
XTALl and XTAL2.
As previously noted, the voltage swings at these pins
are not critical, but they should be checked at the syS"
tem's temperature limits to ensure that they are in good
health. ObserVing these signals necessarily changes
them somewhat. Observing the signal at XTAL2 reo.
quires that the capacitor at that pin be reduced to account for the oscilloscope probe capacitance. Observing
the signal at XTALl requires the same consideration,
plus a blocking capacitor (switch the oscilloscope input
to AC), so as to not disturb the DC level at that pin.
Alternatively, a MOSFET buffer such as the one shown
in Figure 26 can be used. It should be verified by direct
measurement that the ground clip on the scope probe is
ohmically cQnnected to the scope chassis (probes are
incredibly fragile in this respect), and the observations
should be made with the ground clip on the VSS pin, or
very close to it. If the probe shield isn't operational and
in use, the observations are worthless.

Ic1MFE3005

,b IL...

c.:::\
or

XTAL2

-5V

I

'0---+--

The operation of the oscillator should then be verified
under actual system running conditions. By this stage
one will be able to have some confidence that the basic
selection of components for the oscillator itself is suit~
able, so if the oscillator appears to malfunction in the
system the fault is not in the selection of these components.

Troubleshooting Oscillator Problems
The first thing to consider in case of difficulty is that
between the test jig and the actual application there
may be significant differences. in stray capacitances,
particularly if the actual application is on a multi-layer
board.
Noise glitches, that aren't present in the test jig but are
in the application board, are another possibility. Capacitive coupling between the oscillator circuitry and other
signal has already been mentioned as a source of miscounts in the internal clocking circuitry. Inductive coupling is also possible, if there are strong currents nearby. These problems are a function of the PCB layout.
Surrounding the oscillator components with "quiet"
traces (VCC and ground, for example) will alleviate capacitive coupling to signals that have fast transition
times. To minimize inductive coupling, the PCB layout
should minimize the areas of the loops formed by the
oscillator components. These are the loops that should
be checked:
XTALl through the resonator to XTAL2;
. XTALl through CX! to the VSS pin;
XTAL2 through CX2 to the VSS pin.

+12V

XTALl

Frequency checks should be made with only the oscillator circuitry connected to XTALI and ·XTAL2. The
ALE frequency can be counted, and the oscillator frequency derived from that. In systems where the frequency tolerance is only "nominal," the frequency
should still be checked to ascertain that the oscillator
isn't running in a spurious resonance or relaxation
mode. Switching VCC off and on ag~n repeatedly will
help reveal a tendency to go into unwanted modes of
oscillation.

TO
OSCILLOSCOPE

JUMPER FOR
GATE PROTECTION

It is not unusual to find that the grounded ends of CX!
and CX2 eventually connect up to the VSS pin only
after looping around the farthest ends ofthe board. Not
good.

Finally, it should not be overlooked that software problems sometimes imitate the symptoms of a slow-starting
oscillator or incorrect frequency. Never underestimate
the perversity of a software problem.

-'-5V

230659-43

Figure 26. MOSFET Buffer for Observing
Oscillator Signals

10-298

inter

AP-155

REFERENCES
1. Frerking, M. E., Crystal Oscillator Design and Temperature Compensation. Van Nostrand Reinhold, 1978.
2. Bottom, V., "The Crystal Unit as a Circuit Component," Ch. 7, Introduction to Quartz Crystal Unit Design. Van Nostrand Reinhold, 1982.
3. Parzen, B., Design oj Crystal and Other Harmonic
Oscillators. John Wiley & Sons, 1983.

7. Eaton, S. S., Micropower Crystal-Controlled Oscillator Design Using RCA COS/MOS Inverters. RCA Application Note ICAN-6539.
8. Fisher, J. B., Crystal Specifications Jor the Intel
8031/8051/8751 Microcontrollers. Standard Crystal
Corp. Design Data Note #2F.
9. Murata Mfg. Co., Ltd.,
"Cera lock " Application Manual

Ceramic Resonator

4. Holmbeck, J. D., "Frequency Tolerance Limitations
with Logic Gate Clock Oscillators, 31st Annual Frequency Control Symposium. June, 1977.

10. Kyoto Ceramic Co., Ltd., Adaptability Test Between
Intel 8049H and Kyocera Ceramic Resonators.

5. Roberge, J. K., "Nonlinear Systems," Ch. 6,
Operational Amplifiers: Theory and Practice. Wiley,
1975.

11. Kyoto Ceramic Co., Ltd., Technical Data on Ceramic Resonator Model KBR-6.0M, KBR-8.0M, KBRl1.0M Application Jar 8051 (Intel).

6. Eaton, S. S. Timekeeping Advances Through
COS/MOS Technology. RCA Application Note ICAN6086.

12. NTK Technical Ceramic Division, NGK Spark
Plug Co., Ltd., NTKK Ceramic Resonator Manual

10-299

intJ

AP-155

APPENDIX A
QUARTZ AND CERAMIC RESONATOR FORMULAS
Based on the equivalent circuit of the crystal, the impedance of the. crystal is
(R1 + jwL1 + 1/jwC1)(1/jwCo)
ZXTAL = R1 + jwL1 + 1/jwC1 + 1/jwCo

After some algebraic manipulation, this calculation can
be written in the form

The impedance of the crystal in parallel with an external load capacitance CL is the same expression, but
with Co + CL substituted for Co:

II
1
1 - w2L1C1 + j ooR 1C1
XTAL CL = jOO(C1 + Co + CLl • 1 - oo2L1C'T + jooR1C'T

where C'T is the capacitance of Cl in series with (Co
Cd:

+

Each of the above 8-expressions contains two arctan
functions. Setting the denominator of the argument of
the first arctan function to zero gives (approximately)
the "series resonant" frequency for that configuration.
Setting the denominator of the argument of the second
arctan function to zero gives (approximately) the "parallel resonant" frequency for that configuration.

1 - oo2L1C1 = 0

The impedance of the crystal in series with the load
capacitance is
+ CL

Thus

1

= ZXTAL + ~C
jW L
=

CL

+ C1

or

+ Co. 1 - oo2L1C'T

jooCL (C1 + Co)

+ jooR1C'T

1 - oo2L1CT + jooR1CT

where CT and C'T are as defined above.
The phase angles of these impedances are readily obtained from the impedance expressions themselves:
8XTAL = arctan

OOR1C1

1

OOR1C'T
2L C'
1 T

1 - 00

For example, the resonant frequency of the crystal is
the frequency at which

C'T';' C1(CO + CLl
C1+ CO+ CL

ZXTAL

o

The resonant ("series· resonant") frequency is the frequency at which the phase angle is zero and the impedance is low. The antiresonant ("parallel resonant") frequency is the frequency at which the phase angle is zero
and the impedance is high.

where CT is the capacitance of Cl in series with Co:

Z

8XTAL +CL = arctan

-w2L1C1

10-300

1
f ----

s - 2'ITA1C1

infef

AP·155

It will be noted that the series resonant frequency of the

"XTAL+ CL" configuration (crystal in series with CL)
is the same as the parallel resonant frequency of the
"XTALllcL" configuration (crystal in parallel with
Cd. This is the frequency at which

Thus

Equivalent Series Resistance
ESR is the real part of ZXTAL at the oscillation frequency. The oscillation frequency is the parallel resonant frequency of the "XTALllcL" configuration
(which is the same as the series resonant frequency of
the "XTAL + CL" configuration). Substituting this frequency into the ZXTAL expression yields, after some
algebraic manipulation,

or

This fact is used by crystal manufacturers in the process of calibrating a crystal to a specified load capacitance.
By subtracting the resonant frequency of the crystal
from its antiresonant frequency, one can calculate the
range of frequencies over which the crystal reactance is
positive:
fa - fs = fs(~1

+ C1/CO -

1

fS(2~J
Given typical values for CI and Co, this range can
hardly exceed 0.5% offs. Unless the inverting amplifier
in the positive reactance oscillator is doing something
very strange indeed, the oscillation frequency is bound
to be accurate to that percentage whether the crystal
was calibrated for series operation or to any unspecified
load capacitance.

"" R1 ( 1

Co)2

+ CL

Drive Level
The power dissipated by the crystal is I~RJ, where II is
the RMS current in the motional arm of the crystal.
This current is given by vx/lz\l, where Vx is the RMS
voltage across the crystal, and Izd is the magnitude of
the impedance of the motional arm. At the oscillation
frequency, the motional arm is a positive (inductive)
. reactance in parallel resonance with (Co + CL)' Therefore IZII is approximately equal to the magnitude of the
reactance of (Co + CL):

IZ 11 =

1
21ff(Co

+ CLl

where f is the oscillation frequency. Then,
p =

I~ R1 = (I~~I

= [21ff (Co

+

r

R1

CLl Vx12 R1

The waveform of the voltage across the crystal
(XTALl to XTAL2) is approximately sinusoidal. If its
peak value is VCC, then Vx is VCCI{i. Therefore,
P = 2R1 [1ff (Co

10-301

+

CLl VCC1 2

AP·155

APPENDIX B
OSCILLATOR ANALYSIS PROGRAM·
The program is written in BASIC. BASIC is excruciatingly slow, but it has some advantages. For one thing,
more people know BASIC than FORTRAN. In addition, a BASIC program is easy to develop, modify, and
"fiddle around" with. Another important advantage is
that a BASIC program can run on practically any small
computer system.
Its slowness is a problem, however. For example, the
routine which calculates the "start-up time constant"
discussed in the text may take several hours to complete. A person who finds this program useful may prefer to convert it to FORTAN, if the facilities are available.

Limitations of the Program
The program was developed with specific reference to
805 I-type oscillator circuitry. That means the on-chip
amplifier is a simple inverter, and not a Schmitt Trigger. The 8096, the 80C51, the 80C48 and 80C49 all
have simple inverters. The 8096 oscillator is almost
identical to the 8051, differing mainly in the input protection circuitry. The CHMOS amplifiers have somewhat different parameters (higher gain, for example),
and different transition levels than the 8051.
The MCS-48 family is specifically included in the program only to the extent that the input-output curve
used in the steady-state analysis is that of a Schmitt
Trigger, if the user identifies the device under analysis
as an MCS-48 device. The analysis does not include the
voltage dependent phase shift of the Schmitt Trigger.
The clamping action of the input protection circuitry is
important in determining the steady-state amplitudes.
The steady-state routine accounts for it by setting the
negative peak of the XTALl signal at a level which
depends on the amplitude of the XTALl signal in accordance with experimental observations. It's an exercise in curve-fitting. A user may fmd a different type of
curve works better. Later steppings of the chips may
behave differently in this respect, having somewhat differenf types of input protection circuitry.

It should be noted that the analysis ignores a number of
important items, such as high-frequency effects in the
on-chip circuitry. These effects are difficult to predict,
and are no doubt dependent on temperature, frequency,
and device sample. However, they can be simulated to a
reasonable degree by adding an "output capacitance" of
about 20 pF to the circuit model (i.e" in parallel with
CX2) as described below.

Notes on Using the Program
The program asks·the user to input values for various
circuit parameters. First the crystal (or ceramic resonator) parameters are asked for. These are RI, LI, CI,
and CO. The manufacturer can supply these values for
selected samples. To obtain any kind of correlation between calculation and experiment,· the values of these
parameters must be known for the specific sample in
the test circuit. The value that should be entered for CO
is the CO of the crystal itself plus an estimated 7 pF to
account for theXTALI-to-XTAL2 pin capacitance,
plus any other stray capacitance paralleling the crystal
that the user may feel is significant enough to beincluded.
Then the program asks for the values of the XTALI-toground and XTAL2-to-ground capacitances. For.
CXTALl, enter the value of the externally connected
bulk capacitor plus an estimated 7 pF for pin capacitance. For CXTAL2, enter the value of the externally
connected bulk capacitor plus an estimated 7 pF for pin
capacitance plus about 20 pF to simulate high-frequency roll-off and phase shifts in the on-chip circuitry.
Next the program asks for values for the small-signal
parameters of the on-chip amplifier. Typically, for the
8051/8751,
Amplifier Gain Magnitude = IS
Feedback Resistance
= 2300 Kn
Output Resistance
= 2 Kn
The same values can be used for MCS-48 (NMOS and
HMOS) devices, but they are difficult to verify, because
the Schmitt Trigger does not lend itself to small-signal
measurements.

10-302

AP-155

100 DEFDBL C.D.F.G.L.P.R.S.X
200 REM

APRIL B. 19B3

300 REM **********.*.*.***.*************** •••• *********** ••• *.**.*** •••••••• ***

400 REM
500 REM
600 REM
700 REM
BOO REM FNZM(R.X)
900 DEF FNZM(R.X)
1000 REr1
1100 REM FNZP(R.X)

FUNCTIONS
MAGNITUDE OF A COMPLEX NUMBER.

:R+jX:

SOR (R····2+X ..... 2)

ANGLE OF A COMPLE~ NUMBER
180/PI*ARCTANIX/R)
IF R)O
REM
180/P I*ARCTANI X/R I + IBO
IF R',O AND X>O
REM
180/PI*ARCTANIX/RI - 180
IF R<:O AND X(O
DEF FNZP(R.X)
180/PI*ATN(X/R) - ISGNIR)-I)*SGNIX)*90
REM
REM
INDUCTIVE IMPEDANCE AT C0I1PLEX FREQUENCY S+jF 1HZ)
REM
Z =- 2*PI*S*L + J2*PI*F*L
REM
FNRL(S.LI + jFNXLIF.L)
DEF FNRLISL.LL) = 2_*PI*SL*LL
DEF FNXLIFL.LL) = 2_*PI*FL*LL
REM
CAPACITIVE IMPEDANCE AT COMPLEX FREQUENCY S+jF 1HZ)
REM
REM
Z = 1/[2*PI*(S+jF)*Cl
= S/C2*PI*CS"2+F"2)*Cl + J(-F)/C2.PI*CS ..... 2+F·..·2)Cl
REM
REM
= FNRCIS.F.C) + jFNXCIS.F.CI
DEF FNRC ISC. FC. CC I = SCI 12_*PI* ISC "'2+FC"'2)*CC I
DEF FNXC ISC. FC. CC) = -FCII2_*PI*(SC"'2+FC"'21*CC I
REM
REM
RATIO OF TWO COMPLEX NUMBERS
REM
RA+jXA
,RA*RB+XA*XB
REM
+ j
REM
RB-2+XB-2
RB-2+XB-2
RB+ .rX3
REM
FNRRIRA.XA.RB.XB) + jFNXR(RA.XA.RB.XB)
DEF FNRR(RA.XA.RB. XB) = (RA*RB+XA*XB)/(RB A 2+XB-2)
DEF FNXR(RA.XA.RB. XBI = IXA*RB-XB*RA)/(RB"2+XB A 2)
REM
REM
PRODUCT OF TWO COMPLEX NUMBERS
(RA+jXA)*IRB+jXB)
REM
RA*RD-XA*XB + jIXA*RB+RA*XB)
REM
FNRM(RA.XA.RB.XB) + jFNXMIRA.XA.RB.XB)
DEF FNRM(RA.XA.RB.XBI
RA*RD - XA*XB
DEF FNXM(RA.XA.RB. XBI
RA*XD + RB*XA
REM
REM
REM
PARALLEL 1I1PEDANCE.S
REM
IRA+jXA): :(RD+jXB)
REM
RA+RD +jIXA+XB)
REM
RE'M
REM
REM
+
REM
(RA+RD) "2 + (XA+XB)-2
REM
REM
FNRPIRA.XA.RD.XDI + jFNXP(RA.XA.RD.XB)
DEF FNRPIRA.XA.RB.XD)
IRA*IRB"2+XB"'21 + RD*(RA"2+XA-211/«RA+RBI-2 + (XA+XBI-21
DEF FNXPIRA. XA. RB. XDI = (XA*(RB"'2+XD"21 + XB*(RA-2+XA-2) 1/( (RA+RBI-2 + (XA+XBI-2)
REM
REM ******** •• ********.***************** •• ************************.******.
REM
REM
BEGIN COMPUTATIONS
REM
LET PI = 3.141592654_
REM
REM
DEFINE CIRCUIT PARAMETERS
Q05UB 14~OO
REM
REM ESTABLISH r~or"INAL RESONANT ANI) ANT I RESONANT CRYSTAL FREGUENCIES
FS = FIX(1/(2*PI-SQR(Ll*Cllll
FA = FIX(1/12*PI*SQR(Ll*CI*CO/(CI'~Oi)l)
PRINT
PRINT "XTAL 15 SERIES RESONANT AT ".FS." HZ"
PRINT"
PARALLEL RESONANT AT ".FA." HZ"
PRINT
PR INT "SELECT: 1. LIST PARAMETERS"
PR INT
2. CIRCUIT ANALYSIS;'
PRINT "
3. OSCILLATION FREQUENC't"
PRINT"
4. START'·UP TiME CONSTANT"
PRINT
5. STEADY-STATE ANAl.YSIS"

1200 REM

1300
1400
1500
1600
1700
IBOO
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600.
4700
4800
4900
5000
5100
5200
5300
5400
5500
5600
5700
~BOO

5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
7100
7200
7300
7400
7500
7600
7700
'800

230659-44

10-303

inter

Ap·155

7900 PRINT
8000 INPUT N
8100 IF N=I THEN PRINT ELSE 8600
8200 REM
8300 REM ------------- ------.- LIST PARAMETERS ---.-----------------------.-8400 (lOSUS 17100
8500 OOTO 6800
8600 IF N-2 THEN PRINT ELSE 9400
8700 REM
8800 REM - --.---------------.--- CIRCUIT ANALYSIS - -------------------------,8900 PRINT " FREQUENCY' S-+,}F TVPE CS I, IF I "
9000 INPUT SQ.FQ
9100 (lOSUS 20200
9200 (lOSUS 26600
9300 (lOTO 6800
9400 IF N=3 THEN 10300 ELSE 11000
9500 REM
9600 REM ------------------ OSCILLATION FREQUENCY -----------------------9700 CL • CX*CY/CCX+C~1 + CO
9800 FO = FIXC I/C2*PI4S0RCL1*CI*CL/CCl-+CU I I)
9900 SO ~ 0
10000 DF
FIXCIO A INTCLOGCFA-FSI/LOOCIOI-2)+. 5)
10100 DS • 0
10200 RETURN
10300 (lOSUS 9700
10400 (lOSUS 30300
10500 PRINT
10600 PRINT
10700 PRINT "FREOUENCY AT WHICH LOOP GAIN HAS ZERO PHASE ANGLE. "
10800 (lOSUB 26600
10900 (lOTO 6800
11000 IF N=4 THEN PRINT ELSE 12200
IIIOO·REM
11200 REM ---------------- START-UP TIME CONSTANT ------------------------11300 PRINT "THIS WILL TAV.E SOME TIME
11400 (lOSUB 9700
11500 (lOSUB 37700
11600 PRINT
11700 PRINT
11800 PRINT "FREQUENCV AT WHICH LOOP GAIN = I AT 0 DEGREES:"
11900 (lOSUB 26600
12000 PRINT: PRINT "THIS YIELDS A START-UP TIME CONSTANT OF "i CSNGCIOOOOOO!/C2*PHSQ))i" MICROSECS"
12100 (lOTO 6800
~
12200 IF N=5 THEN PRINT ELSE 7300
12300 REM
12400 REM ---------------- STEADY-STATE ANALYSIS --------------------------12500 PRINT "STEADY-STATE ANALYSIS"
12600 PRINT
12700 PRINT "SELECT:
1. 803118051"
2. 8751"
12800 PRINT
3. 8035/8039/8040/8048/8049"
12900 PRINT "
13000 PRINT
4. 8748/8749"
13100 INPUT ICiI
13200 IF ICX2 AND VO=5 AND VI'~2 THEN RETURN
13700 VO
-IO*VI + 15
13800 IF va>' THEN va = 5
13900 IF VO<.2 THEN va = 2
14000 IF ICiI>2 AND VO>2 THEN VO = 5
14100 RETURN
14200 REM
14300 REM ******.************************ .... **+ .... ***.*.****.*.*********
14400 REM
14500 REM
DEFINE CIRCUIT PARAMETERS
14600 REM
14700 INPUT" Rl COHMS)"iRI
14800 INPUT" Ll (HENRY) "i Ll
1490'0 INPUT" CI (PF) "i X
15000 Cl • X*IE-12
15100 INPUT" 'CO (PF) "i X
15200 CO = X*IE-12
15300 INPUT" CXTALI (PF)"iX
15400 CX = X*IE-12
15500 INPUT" CXTAL2 (PF)"i X
15600 CV • X*IE-12

=

=

230659-45

10-304

inter
1~700

15800
15900
16000
16100
16200
16300
16400
16500
16600
16700
16800

Ap·155

INPUT" GAIN FACTOR MAGNITUDE";AVII
INPUT" AMP FEEDDACK RESISTANCE CK-OHMs,",X
RX = ~*IOOOII
INPUT" AMP OUTPUT RESISTANCE CK-OHr1s,"; X
RO = ~*IOOOII
REM
REM
REM
L!S! CURRENT PARAMETER VALUES
GOsUD 17100
RETURN
REr1
REM

16900 REM *.*******.*4~.***4**.4~4***~*~*4._~.*********.******** ********

17000
17100
17200
17300
17400
17500
17600
17700
17800
17900
18000
18100
18200
18300
18400
18500
18600
18700
18800
18900
19000
19100
19200
19300
19400
19500
19600
19700
19800
19900
20000

20100
20200
20300
20400
20500
20600
20700
20800
20900
21000
21100
21200
21300
21400
21500
21600
21700
21800
21900
22000
22100
22200
·22300
22400
22500
22600
22700

REI1
LIST CURr~ENT PARAMETER VALUES
REI'o
REM
PRINT
RI
"i RI," OHMS"
PRINT "CURRENT PARAMETER VALUES
PRINT"
2
LI
", CSNGCLI)i" HENRY"
3 CI
"i CsNGCCI*IE+12)i" PF"
PRINT"
4 CO
", CsNGCCO*IE+12)i" PF"
PRINT"
5
CXTAL! = ",CsNG(CX*IE+12)i" PF"
PRINT"
6 CXTAL2 = ",CsNG(CY.IE+12);" PF"
PRINT"
7. AMPLIFIER GAIN MAGNITUDE
"i AVII
PRINT "
PRINT
8.
FEEDBAC" RESISTANCE
"i CsNGCRX* OOI)i" K-OHMS"
9.
OUTPUT RESISTANCE
"i CsNG (RD •. 001) i" K-OHMs"
PRINT
PRINT
PRINT "TO CHANGE A PARAMETER VALUE, TYPE CPARAM NO ), CNEW VALUE>' "
PRINT "OTHEIlWIsE, TYPE O,C- "
INPUT NX,X
IF NX=O THEN RETURN
IF NX=I THEN RI
X
IF NX=2 THEN LI
X
IF NX=3 THEN CI
X*IE-12
IF NX=4 THEN CO
X*IE-12
IF NX=5 THEN CX
X*IE-12
IF NX=6 THEN CV
X*lE-12
IF NX=7 THEN AVII = X
IF NX=8 THEN RX
X*IOOO'
IF NX=9 THEN RO = X*IOOO'
GOTO 17400
REM
REM
REM ***********4******************-*******************************
REM
REM
CIRCUIT ANALYSIS
REM
REM This Tout in. calculate. the loop gain at complex frequenc~ SG+JFG.
REM
REM I. Crystal ,"'pedance RE + JXE
REM
XI = FNXL(FQ,LII + FNXC(SQ,FQ,Cll
RE = FNRP«RI+FNRL(SQ,LI)+FNRCcsQ,FQ,CI»,XI,FNRC(SQ,FQ,CO),FNXC(SQ,FQ,CO»
XE = FNXP«RI+FNRLCSQ,LI)+FNRCCSQ,FQ,CI»,XI,FNRC(SQ,FQ,CO),FNXC(sQ,FQ,CO»
REM
REM 2. RF + JXF
(RE+JXE): :Campli'ler feedback resistance)
REM
RF = FNRP(RX,O,RE,XE'
XF = FNXP(RX,O,RE,XE)
REM
REM 3. Input impedance. 7.l
RI + JXI
impedance of CXTALl
REM
RI
FNRC (sG, FG, C'')
XI = FNXC (sG, FG, C:<.>
REM
REM 4 Load impedance: ZL = Ilmpedance of CXTAL2):: [(RF+RIl+J(XF+XIll
REM
RL = FNRP«RF+RI). (XF+XI),FNRC(SO.FIJ,CY),FNXC(SQ,FG,CY»
XL = FNXP«RF+RIl,(XF+XIl,FNRCCSQ,r'G,CY),F'NXCCsG,FQ,CY»
REM
REM 5 AmpllflOr ga,n A = -AV*ZL/iZL+RO)

22800 REM

=

=

At rlial)

+

JA( Imag Inary)

22900
23000
23100
23200

REM
ARII = -AVII*FNRRCRL, XL, (RO+RL), ~Ll
AlII = -AVII.FNXRCRL, XL, CR(J+RL), 'Ll
REM
23300 REM
6
Feedbatlt ratio
J,t.-?tai
lJiJ+JXlil((RF+RI)-t.tCXF+Xt)J
23400 REM
B'r~alJ ~
JE(lma~ln~ry)
230659-46

10·305

inter
23500
23600
23700
23800
23900
24000
24100
24200
24300
24400
24500
24600
24700
24800
24900
25000

25100
25200
25300
25400
25500
25600
25700
25800
25900
26000
26100

AP-155

REM
DRII = FNRR(RI. XI. IRI+RF). CXI+XF) I
Bill = FNXRCRI.XI. (RI+RFI. (XI+XF))
REM
REM 7. Amplifier gain ill magnitu"de/phase form" AR+JAI
A at AP d~grees
REM
A = FNZMCARII.AIII)
AP = FNZP(ARII.AI.)
REM
REM 8
Cbeta).n magnitude/phase form D~+JBI
B at BP deg . . es
REM
B = FNZMCDR •• DI.)
UP = FNZPCBR •• BI.)
REM
REM 9 Loop ga.n 'G = CB~+JBI).tAR+JAI)
REM
= G(real) • JG( lmag inartj)
REM
GR = FNRMCAR •• AI •• BR •• BI.)
GI = FNXM(AR •• AI •• BR •• BI.)
REM
REM 10. Loop 951n in magnitude/p~ase form. GR+JGI
AL at AB degrees
REM
AL = FNZM(GR.GI)
AO = FNZP(GR.GI!
RETURN
REM
REM

26200 REM

26300
26400
26500
26600
26700
26800
26900
27000
27100
27200
27300
27400
27500
27600
27700

27800 REM

27900
28000
28100
28200
28300
28400
28500
28600
28700
28800
28900
29000
29100
29200
29300
29400
29500
29600
29700
29800
29900
30000
30100
30200
30300
30400
30500
30600
30700
30800
30900
31000
31100
31200

************_**_********._ ••• ****************************** •••

REM
REM
REM
PRINT
PRINT"
PRINT"
PRINT"
PRINT"
PRINT"
PRINT"
PRINT"
PRINT"
RETURN
REM
REM

PRINT CIRCUIT ANALYSIS RESULTS
FREOUENCY = "'SO," + J",FO," HZ"
HAL IMPEDANCE = ".FNZM(RE.XE)," OHMS.AT ",FNZPCRE.XE)," DEGREES"
CRE = ",CSNG(RE)," OHMS)"
(XE = ", CSNG(XE), " OHMS)"
LOAD IMPEDANCE = ",FNZMCRL.Xl), " OHMS AT ",FNZP(RL.XL), " DEGREES"
AMPLIFIER GAIN = ", A," AT ", AP, ,,' DEGREES"
FEEDBACK RATIO = ".D." AT ",BP," DEGREES"
LOOP GAIN = ", AL," AT ",.AQ," DEGREES"

***************************************************.**********

REM
REM
SEARCH FOR FREOUENCY CS+JF)
REM
AT WHICH LOOP GAIN HAS ZERO PHASE ANGLE
REM
REM This routine s.arc~e5 for the fre~uenc~ at which the imaginar~ part
REM of the loop gain is zero. The algorithm is as fDl1a~s:
REM
1. Calculate the sign of the ima91nar~ part of the loop gain (01),
REM
2. Increment the fre~uency.
REM
3. Calculate the sIgn of GI at the incremented frequency.
REM
4. If the sign of GI has not changed. go back to 2.
REM
5. If th@ sign of GI ha!> ct'tanged. and this frequenc~ is lIIithin
REM
1Hz of the previous Sign-change. exit the routine.
REM
6. Otherlilise. divide the frequency increment b~ -10.
REM
7. Go back to 2.
REM The routine is entered lIIlth the starting frequency SO+JFO and
REM starting increment DS+JDF already defined by the calling program.
REM In actual use either DS or DF is·zero. so the routine sear~hes·.fDr
REM a GI=O pOInt by lncrementlng either SO Dr FO while holding the other
REM constant. It returns control to t~e calling program ~ith the
REM increm~nted part of the frequency being within 1Hz of the actual
REM GI=O point.
REM
REM 1. CALCULATE THE SIGN OF THE !l1AGINARY PART OF THE LOOP GAIN (GI).
REM
GOSUU 20200
GOSUB 26600
IF GI=O THEN RETL'RN
SXX = INT(SGNCGI))
IF SXX=+I THEN OS
-OS
REM (REVERSAL OF OS FO~ GIOO IS FOR THE POLE-SEARCH ROUTINE. )
REM
REM 2
INCREMENT THE FREQUENCY.
REM
SP
50

=

230659-47

10,306

AP-155

31300
31400
31500
31600
31700
31800
31900
32000
32100
32200
32300
32400
32~00

32600
32700
32800
32900
33000
33100
33200
33300
33400
33500
33600
33700
33800
33900
34000
34100
34200
34300
34400
34500
34600
34700
34800
34900
35000
35100
35200
3~300
3~400

35500
35600
35700
35800
35900
36000
36100
36200
36300
36400
36500
36600
36700
36800
36900
37000
37100
37200
37300
37400
37500
37600
37700
37800
37900
38000
38100
38200
38300
38400
38500
38600
38700
38800
38900
39000

FP = FQ
Sel = sa ? OS
Fel ~ FQ + OF
REt1
REM 3 CALCULATE THE SIGll OF GI AT THE INCREMENTED FREOUENCY.
REM
GOSUB 20200
GOSUB 26600
IF INTISGNIGI))=O THEN RETURN
REM
REM 4
IF THE SIGN OF III HAS Imr CHANGE!), GO BACK TO 2.
REM
IF SX7.?INT(SGN(GI))=O THEN PRINT ELSE 31400
SX7. = -SX7.
REM
IF THE SIGN OF GI f(AS CHANGED, ANO .IF THIS FREOUENCY IS WITHIN
REM 5
1HZ OF 'T'"4E PREVIOUS SIGN-CHANGE; AND !F G! IS NEGATIVE. THEN
REM
REM
EXIT THE ROUTINE
CTHF ADDITIONAL REClUIREMENT FOR NEGATIVE GI
REM
IS FOR THt:: POLE-SEARCH ROUTINE. t
REt1
IF ABS(5P-50)<:1 AND ADS(FP-FO)<:1 AND 5X'l.=-1 THEN RETURN
REM
REM 6. DIVIDE THE FREQUI::NCY INCREt1ENT BY -10
REM
OS = -05/10.
OF = -DF/IO.
REM
REM 7. GO BACK TO 2
REM
GOTO 31200
REM
REM
REM •• * ••••• ***** ••••• ** ••••• ** ••••• ** •••• **** •• ** ••• ** ••• ********
REM
SEARCH FOR POLE FREQUENCY
REM
REM
REM This routine searches for the frequency at which the loop gain = 1
REM at 0 degrees. That fre~uency 1~ t~e pole frequency of the closedREM loop gain function. The pole frequl"ncy is a complex number, SO+JFG
REM CHz). Oscillator start-up ensues 1f 5Q~O. The algorithm is based on
REM the calculated behaVior of the phase angle of the loop gain in the
REM reglon of interest on the complex plane. The locus of points of zero
REM phase angle crosses the J-axis at the oscillation frequenc~ and at
REM some higher irequency. In between these two crossings of the J-axis.
REM the locus lies in Quadrant I of the comple, plane. forming an
REM approximate parabola which opens to the left. The basic plan is to
REM follow the locus from where, It crosses the J-axis at the oscillation
REM frequenc~. into Quadrant I. and find the point on that locus where
REM the loop gain has a magnltude of 1. The algorithm' is as follows:
1. Find thi' oscillation freQ.uency. O+JFG.
REM
REM
2. At thlS frequenc~ calculate the sign of (AL-l)
(AL = magnitude
of loop gain. )
REM
REM·
3. IneTement FQ.
4. For this value of FQ, find the value of SQ for which the loop
REM
REM
gain has zero phase
REM
5. For this value of SQ+JFQ, calculate the sign of (AL-11.
REM
6. If the sign of (AL-l) t'las not changed, go back to 3.
REM
7. If the sign of CAL-I) has changed. and this value of FO is
REM
within 1Hz of the previous slgn-change, exit the routine.
REM
S. OtherWlse, dIvide the FO-increment by -10.
REM
9. Go bat\!: to 3
REM
REM I. FIND THE OSCILLATION FREQUENCY, O"'JFCl
REM
GOSUB 9700
GOSUB 30300
REM
REM 2. AT THIS FREQUENCY, CA'-CUL.ATE THE SIGN OF (AL··I)
REM
SY7. = INTlSGN(AL··I'))
IF SY7.=-1 THEN STOP
REM ESTABLISH INITIAL INCREMEIHAT ION VALUE FOR FO
FI = FO
OF = (FA-Flt/IO.
GOSUB 30300
DE
(FQ-Flt/IO.
OF
0
FQ
FI

230659-48

10-307

intJ

AP-155

39100 REM
39200 REM 3. INCREMENT FO
39300 REM
39400 Fa - Fa + DE
39:100 REM
39600-REM 4. FOR THIS VALUE OF FO. FIND THE VALUE OF SO FOR WHICH THE LOOP
GAIN HAS ZERO PHASE. CTHE ROUTINE WHICH DOES THAT NEEDS OF • O.
39700 REM
50 THAT IT CAN HOLD FO CONSTAr~T. AND NEEDS AN INITIAL VALUE FOR
39BOO REM
OS. WHICH IS ARBITRARILY SET TO 05 c 1000. I .
39"00 REM
40000 REM
40100 OS c 1000.
40200 SO • 0
40300 GOSUB 30300
40400 IF AL-I! THEN RETURN
40500 REM
40600 REM 5. FOR THIS VALUE OF SO+.iFO. CALCULATE THE SIGN OF CAL-II.
40700 REM 6. IF THE SIGN OF CAL-II HAS NOT CHANGED. GO BACK TO 3.
40BOO REM
40900 IF SYX+INTCSGNCAL-I!II=O THEN PRINT ELSE 39400
41000· REM
41100 REM 7. IF THE SIGN OF CAL-II HAS CHANGED. AND THIS VALUE OF Fa IS WITHIN
1HZ OF THE PREVIOUS SIGN-CHANGE. EXIT THE ROUTINE.
41200 REM
41300 REM
41400 IF ABSCFI-FOI
TLLlV>
TPLlV>
TPXIZ>
270068-12

b. Using a Power MOSFET
Figure 13. Power Switchover Ckts.

80C31BH

+ CHMOS EPROM

The 27C64 and 87C64 are Intel's 8K byte CHMOS
EPROMs. The 27C64 requires an external address
latch, and .can be used with the 80C31BH as. shown in
Figure 14a. In most 8031 + 2764 (HMOS) appli-

tACC
tCE
tOE
tDF

If the application is going to use the Power Down mode
then we have another consideration: In Idle, ALE =
PSEN = 1, and in Power Down, ALE = PSEN = o.
In a realistic application there are likely to be more
chips in the circuit than are shown in Figure 14, and it
is likely that the nonessential ones will have their Vee
removed while the CPU is in Power Down. In that case
the EPROM and the address latch should be among
the chips that have Vee removed, and logic lows are
exactly what are· required at ALE and PSEN.
But if Vee is going to be maintained to the EPROM
during Power Down, then it will be necessary to· de-

27C64

8OC31BH
8

~----------~--------~CE
P~EN~----~--~----------~Oi
270068-26

Figure 14a. 80C31BH

10-322

+ 27C64

inter

AP-252

The 87C64 is like the 27C64 except that it has an onchip address latch. The Port 0 pins are tied to both
address and data pins of the 87C64, as shown in Figure,
16a. ALE drives the EPROM's ALE/CS input. During
ALE high, the address information is allowed to flow
into the EPROM and begin ;lccessing the code byte. On
the falling edge of ALE the address byte is internally
latched. The AO-A7 inputs are then ignored and the
same bus lines are used to transmit the fetched code
byte from the 00-07 pins back to the 80C3lBH.
The timing waveforms for this configuration are shown
in Figure 16b. In Figure 16b the signals and timing
parameters in parentheses are those of the 87C64, and
the others are of the 80C3lBH. The requirements for
timing compatibility are
270066-13

Figure 14b. Timing Waveforms for 80C31BH
27C64

TLHLL> tLL

+

TAVLL> tAL

select the EPROM when the CPU is in Power Down. If
Idle is never invoked, CE of the EPROM can be connected to P2.7 of the 80C3lBH, as shown in Figure
15a. In normal operation, P2.7 will be emitting the
MSB of the Program Counter, which is 0 if the program contains less than 32K of code. Then when the
CPU goes into Power Down, the Port 2 pins emit P2
SFR data, which puts a 1 at P2.7, thus deselecting the
EPROM.
If Idle and Power Down are both going to be used, CE
of the EPROM can be driven by the logical OR of ALE
and P2.7, as shown in Figure 15b. In Idle, ALE = I
will deselect the EPROM, and in Power Down, P2.7 =
1 will deselect it.

TLLAX> tLA
TLLlV> tACL
TPLlV> tOE
TLLPL> tCOE
TPXIZ> tOHZ

The same considerations apply to the 87C64 as to the
27C64 with regards to the Idle and Power Down
modes. Basically you want CS = 1 if Vee is maintained to the EPROM, and CS = OE = 0 if Vee is
removed.

SCANNING A KEYBOARD
P2.7

FE

There are many different kinds of keyboards, but alphanumeric keyboards generally consist of a matrix of 8
scan lines and 8 receive lines as shown in Figure 17.
Each set of lines connects to one port of the microcontroller. The software has written Os to the scan lines,
and Is to the receive lines. Pressing a key connects a
scan line to a receive line, thus pulling the receive line'
to a logic low.

of
- - - - - . . . ; . . . . . of
80C31 BH
27C64

270068-14

a. Power Down Is used but not Idle.
of
80C31BH

_

{ALE~
CE
P2.7~ 27~64
270068-15

b. Idle and Power Down both used.
Figure 15. Modifications to 80C31BH/27C64
Interface

Pulldown resistors are shown in Figure 14a under the
assumption that something on the bus is going to have
its Vee removed during Power Down. If this is not the
case, pullups can be used as well as pulldowns.

The 8 receive lines are ANDed to one of the external
interrupt pins, so that pulling any of the receive lines
low generates an interrupt. The interrupt service routine has to identify the pressed key, if only one key is
down, and convert that information to some useful output. If more than one key in the line matrix is found to
be pressed, no action is taken. (This is a "two key lockout" scheme.)

10-323

inter

AP-252

On some keyboards, certain keys (Shift, Control, Escape, etc.) are not a part of the line matrix. These keys
would connect directly to a port pin on the microcontroller, and would not cause lock-out if pressed simultaneously with a matrix key, nor generate an interrup,t if
pressed singly.
Normally the microcontroller would be in- idle mode
when a key has not been pressed, and another task is
not in progress. Pressing a matrix key generates an in-

r

10K

PO

terrupt, which terminates the Idle. The interrupt service routine would first call a 30 ms (or so) delay to
debounce the key, and then set about the task of identifying which key is down.
First, the current state of the receive lines is latched
into an internal register. If a single key is down, all but
one of the lines would be read as Is. Then Os are written
to the receive lines and 1s to the scan lines, and the scan
lines are read. If a single key is down, all but one of

XI
/8

...

0.-0,
87C64

8OC31BH

ArA,

/8

P2

/5

-I ArAI~

ALE

FE

PSEN

OE
270068-16

Figure 16a. 80C31BH

+ 87C64

270068-17

Figure 16b. Timing Waveforms for 80C31BH

10-324

+ 87C64

intJ

AP-252

RESPONSE_TO_KEY_CLOSURE:
CALL DEB OUNCE_DELAY
.MOV
LINE, P1; ;See Figure 17.
·CALL SCAN
DJNZ ZERO_COUNTER, REJECT
MOV
ADDRESS, ZERO_BIT
MOV
P2,#OFFH; ;See Figure 17.
MOV
P1,#O
MOV
LINE,P2
.CALL SCAN
DJNZ ZERO_COUNTER, REJECT
XCH
A, ZERO_BIT
SWAP A
ORL
ADDRESS,A
XCH
A, ZERO_BIT
MOV
P1,#OFFH
MOV
P2,#O
REJECT: CLR
EXO
RETI

these lines would be read as Is. By locating the single 0
in each set of lines, the pressed key can be identified. If
more than one matrix key is down, one or both sets of
lines will contain multiple Os.
A subroutine is used to determine which of 8 bits in
either set of lines is 0, and whether more than one bit is
O. Figure 18 shows a subroutine (SCAN) which does
that using the 8051 's bit-addressing capability. To use
the subroutine, move the line data into a bit-addressable RAM location named LINE, and call the SCAN
routine. The number of LINE bits which are zero is
returned in ZERO_COUNTER. If only one bit is
zero, its number (1 through 8) is returned in ZERO_
BIT.
The interrupt service routine that is executed in response to a key closure might then be as follows:

SCAN LINES

rC

RECEIVE
LINES

-

'--

aOCSleH

f----"

I-------"
)Pl P2

INTO

270068-18

Figure 17. Scanning a Keyboard

10-325

inter

AP-252

SCAN:

ONE:
TWO:
THREE:
FOUR:
FIVE:
SIX:
SEVEN:
EIGHT:

MOV
JB
INC
MOV
JB
INC
MOV
JB
INC
MOV
JB
INC
MOV
JB
INC
MOV
JB
INC
MOV
JB
INC
MOV
JB
INC
MOV
RET

ZERO_COUNTER. 110
LINE.O.ONE
ZERO_COUNTER
ZERO_BIT. 411
LINE. I. TWO
ZERO_COUNTER
ZERO_BIT. 412
LINE. 2. THREE
ZERO_COUNTER
ZERO_BIT. 413
LINE. 3. FOUR
ZERO_COUNTER
ZERO_BIT. 414
LINE.4.FIVE
ZERO_COUNTER
ZEROJlIT.4IS
LINE.5.SIX
ZERO_COUNTER
ZERO_BIT.4Ib
LINE. b. SEVEN
ZERO_COUNTER
ZERO_BIT. 117
LINE. 7. EIGHT
ZER030UNTER
ZERO_BIT.4Ie

ZERO_COUNTER caunts the number of Os in LINE.
Tnt LINE bit O.
If LINE. 0 ~ O. incre~ent ZERO_COUNTER
and reco'l'd th.t 1 ine numb.r I t. active.
P1'ocedure continues fa,. other LINE bits.

,

Line number 2 is active.

,

Line number 3 is active.

,

Line number 4 is active.
Line number 5 is active.
L.ine number 6

i's

active.

Line number 7 is active.
Line number 8 i'i active.

270068-19

Figure 18. Subroutine SCAN Determines Which of 8 Bits in LINE is Zero
Notice that RESPONSE_TO~EY_CLOSURE
does not change the Accumulator, the PSW, nor any of
the registers RO through R7. Neither do SCAN or DEBOUNCE_DELAY.
What we come out with then is a one-byte key address
(ADDRESS) which identifies the pressed key. The
key's scan line number is in the upper nibble of ADDRESS, and its receive line number is in the lower
nibble. ADDRESS can be used in a look-up table to
generate a key code to transmit to a host computer,
and/or to a display device.
The keyboard interrupt itself'must be edge-triggered,
rather than level-activated, so that the interrupt routine
is invoked when a key is pressed, and is not constantly
being repeated as long as the key is held down. In edgetriggered mode, the on-chip hardware clears the interrupt flag (EXO, in this case) as the service routine is
being vectored to. In this application, however, contact
bounce will cause several more edges to occur after the
service routine has been vectored to,· during the DEBOUNCE_DELAY routine. Consequently it is necessary to clear EXO again in software before executing
RETI.
The debounce delay routine also takes advantage of the
Idle mode. In this routine a timer must be preloaded
with a value appropriate to the desired length of delay.
This would be

For example, with.a 3.58 MHz oscillator frequency, a
30 ms delay could be obtained using a preload value of
- 8950, or DDOA, in hex digits.
In the debounce delay routine (Figure 19), the timer
interrupt is enabled'and set to a higher priority than the
keyboard interrupt, because as we invoke Idle, the keyboard .interrupt is still "in progress". An interrupt of
the same priority will not be acknowledged, and will
not terminate the Idle mode. With the timer interrupt
set to priority 1, while the keyboard interrupt is a priority 0, the timer interrupt, when it occurs, will be acknowledged and will wake up the CPU. The timer interrupt service routine does not itself have to do anything. The service routine might be nothing more than
a single RETI instruction. RETI from the timer interrupt service routine then returns execution to the debounce delay routine, which shuts down the timer and
returns execution to the keyboard service routine.

DRIVING AN LCD
An LCD (Liquid Crystal Display) consists of a backplane arid any number of segments or dots which will
be used to form the image being displayed. Applying a
voltage (nominally 4 or 5V) between any segment and
the backplane causes the segment to darken. The only
catch is that the polarity of the applied voltage has to
be periodically reversed, or else a chemical reac-

.
I d
(ose kHz) x (delay time ms)
timer pre oa =
12

10-326

inter

AP-252

DEBOUNCE_DELAY:
MOV
MDV

SETB
SETB
SETB
ORL

TLI, ..TLI_PRELOAD ; Preload low blJte.
TH1,4tTH1JRELOAD j Preload high byte.
ETI
Enable Timer 1 interrupt.
PTt
Set TimeT' 1 intel'T"upt to high priority.
TR1
Start timer l'unning.
peON. ttl
j
Invoke Idle mode.

The next instruction will not be executed until the delay times out.
CLR
CLR
CLR

RET

TRI

Stop the timer.
Back to priority 0 (if desired).
Disab Ie Timer 1 interrupt (if desired),
Continue keyboard scan.

PT1
ET1
J

270068-20

Figure 19. Subroutine DEBOUNCLDELAY Puts the 80C51BH Into Idle During the Delay Time

tion takes place in the LCD which causes deterioration
and eventual failure of the liquid crystal.
To prevent this happening, the backplane and all the
segments are driven with an AC signal, which is derived from a rectangular voltage waveform. If a segment is to be "off" it is driven by the same waveform as
the backplane. Thus it is always at backplane potential.
If the segment is to be "on" it is driven with a waveform that is the inverse of the backplane waveform.
Thus it has about 5V of periodically changing polarity
between it and the backplane.
With a little software overhead, the 80C51BH can perform this task without the need for additional LCD
drivers. The only drawback is that each LCD segment
uses up one port pin, and the backplane uses one more.
If more than, say, two 7-segment digits are being driven, there aren't many port pins left for other tasks.
Nevertheless, assuming a given application leaves
enough port pins available to support this task, the considerations for driving the LCD are as follows.
Suppose, for example, it is a 2-digit display with a decimal point. One port (TENS_DIGIT) connects to the 7
segments of the tens digit plus the backplane. Another
port (ONES~IGIT) connects to a decimal point plus
.the 7 segments of the ones digit.

tasks are not requiring servicing. When the timer rolls
over it generates an interrupt, which brings the
80C5IBH out of Idle. The service routine reloads the
timer (for the next rollover), and inverts the logic levels
of all the pins that are connected to the LCD. It might
look like this:

LCD_DRIVE_INTERRUPT:
MOV
TL1,#LOW( - XTAL_FREQI
MOV
TH1,#HIGH( - XTAL_FREQI
XRL
TENS_DIGIT,#OFFH
XRL
ONES_DIGIT,#OFFH
RETI
To update the display, one would use a look-up table to
generate the characters. In the table, "on" segments are
represented as Is, and "off" segments as Os. The backplane bit is represented as a O. The quantity to be displayed is stored in RAM as a BCD value. The look-up
table operates on the low nibble of the BCD value, and
produces the bit pattern that is to be written to either
the ones digit or the tens digit. Before the new patterns
can be written to the LCD, the LCD drive interrupt has
to be disabled. That is to prevent a polarity reversal
from taking place between the times the two digits are
written. An update subroutine is shown in Figure 20.

USING AN LCD DRIVER
One of the 80C5IBH's timers is used to mark off halfperiods of the drive voltage waveform. The LCD drive
waveform should have a rep rate between 30 and 100
Hz, but it's not very critical. A half-period of 12 ms will
set the rep rate to about 42 Hz. The preload/reload
value to get 12 ms to rollover is the 2's complement
negative of the oscillator frequency in kHz: if the oscillator frequency is 3.58 MHz, the reload value is
- 3580, or F204 in hex digits.
Now, the 80C51BH would normally be in Idle, to conserve power, during the time that the LCD and other

As was noted, driving an LCD directly with an
80C51BH uses a lot of port pins. LCD drivers are available in CMOS to interface an 80C5IBH to a 4-digit
display using only 7 of the C5IBH's I/O pins. Basically, the C51BH tells the LCD driver what digit is to be
displayed (4 bits) and what position it is to be displayed
in (2 bits), and toggles a Chip Select pin to tell the
driver to latch this information. The LCD driver generates the display characters (hex digits), and takes care
of the polarity reversals using its own RC oscillator to
generate the timing.

10-327

Ap·252

Figure 25 shows an 80C51BH working with an
ICM72llM to drive a 4-digit LCD, and the software
that updates the display.
One could equally well send information to the LCD
driver over the bus. In that case, one would set up the
Accumulator with the digit select and data input bits,
and execute a MOVX@ RO,A instruction. The LCD
driver's chip select would be driven by the CPU's WR
signal. This is a little easier in software than the direct
bit manipulation shown in Figure 21. However, it uses
more I/O pins, unless there is already some external
memory involved. In that case, no extra pins are used
up by adding the LCD driver to the bus.

RESONANT TRANSDUCERS
Analog transducers are often used to convert the value
.of a physical property, such as temperature, pressure,
etc., to an analog voltage. These kinds of transducers
then require an analog-to-digital converter to put the
measurement into a form that is compatible with a digital control system. Another kind of transducer is now
becoming available that encodes the value of the physical property into a signal that can be directly read by a
digital control system. These devices are called resonant transducers.
Resonant transducers are oscillators whose frequency
depends in a known way on the physical property being
IIleasured. These devices output a train of rectangular
pulses whose repetition rate encodes the value of the
quantity being measured. The pulses can in most cases
be fed directly into the 80C51BH,which then measures
either the frequency or period of the incoming signal,
basing the measurement on the accuracy of its own
clock oscillator. The 80C51BH can even do.this in its
sleep; that is, in Idle.

UPDATE_LCD:
CLR
MOV
MOV
SWAP
ANL
MOVC
MOV
MOV
ANL
MOVC
MOV
MOV
MOV
SETB
RET

ETl

When the frequency or period measurement is completed, the C5IBH wakes itself up for a very short time to
perform a sanity check on the measurement and convert it in software to any scaling of the measured quantity that may be desired. The software conversion can
include corrections for nonlinearities in the transducer's transfer function.
Resolution is also controlled by software, and can even
be dynamically varied to meet changing needs as a situation becomes more critical. For example, in a process
controller you can increase your resolution ("fine tune"
the control, as it were) as the process approaches its
target.
The nominal reference frequency of the output signal
from these devices is in the range of 20 Hz to 500 kHz,
depending on the design. Transducers are available that
have a full scale frequency shift 2 to 1. The transducer
operates from a supply voltage range of 3V to 20V,
which means it can operate from the same supply voltage as the 80C51BH. At 5V, the transducer draws less
than 5 rnA (Reference 7). It can normally be connected
directly to one of the C5IBH's port pins, as shown in
Figure 22.

FREQUENCY MEASUREMENTS
Measuring a frequency .means counting pulses for a
known sample time. Two timer/counters can be used,
one to mark off the sample time and one to count pulses. If the frequency being counted doesn't exceed 50
kHz or so, one may equally well connect the transducer
signal to one of the external interrupt pins, and count
pulses in software. That frees up one timer, with very
little cost in CPU time.
The count that is directly obtained is TxF, where T is
the sample time and F is the frequency. The full scale

Disable LCD drive interrupt.

DPTR. !lTABLE_ADDRESS
A. BCD_VALUE
A
A.!lOFH
A.C!!A+DPTR
TENS_DIGIT. A
A. BCD_VALUE

Look-up table begins at TABL.E_ADDRESS

A,4tOFH
C. DECIMAL_POINT
ACC.7.C
ONES_DIGIT. A

Mask off tens digit.
Ones digit pattern to accum'ulator.
Add 'dec 1mal point to segment
pattern.
Update LCD decimal point
and ones di"git.

ETl

Re-enable LCD drive inteT'T'upt.

A,@A+DPTR

Digits to be ,displayed.

Move tens digit to low nibble.
Mask off high nibble.
Tens digit pattl'r" to accumulator:

Update LCD tens digit.
Digits to be displayed.

270068-21

Figure 20. UPDATE_LCD Routine Writes Two Digits to an LCD

10-328

AP-252

For example, 8-bit resolution in the measurement of a
frequency that varies between 7 kHz and 9 kHz would
require, according to this formula; a sample time of 128
ms. The maximum acceptable frequency count would
be 128 ms X 9 kHz = 1152 counts. The minimum
would be 896 counts. Subtracting 896 from each frequency count (or presetting the frequency counter to
- 896 = OFC80H) would allow the frequency to be
reported on a scale of 0 to FF in hex digits.

range is Tx(Fmax-Fmin). For n-bit resolution
1 LSB = Tx(Fmax-Fmin)

2"

Therefore the sample time required for n-bit resolution
is
T

=

2"

::---=-=,---,-Fmax-Fmin

BOC51BH

,.,

PORT

{

)

1 ) DIGIT
2
SELECT

M}

B1
B2

DATA
INPUT

)

-v

B3

v

cs

v

L.
C.
D.

"270068-22

Figure 21a. Using an LCD Driver

UPDATE_LCD:
MOV
SETB
SETB
CALL
CLR

CALL
MOV
CLR
SETB
CALL
CLR
CALL
RET
SHIFT _AND_LOAD:
RLC
MOV
RLC
MOIJ
RLC
MOV
RLC
MOV
CLR
SETB
RET

A. DISPLAY _HI
DIGIT _SELECT _2
DIGIT SELECT 1
SHIFT -AND LOAD
DIGIT:=SELECT_1
SHIFT _AND_LOAD
A. DISPLAY LO
DIGIT _SELECT_2
DIGIT _SELECT_1
SHIFT _AND_LOAD
DIGIT _SELECT_1

SHIFT_AND_LOAD

High

byte of 4-digit display.

Select leftmost digit of LCD,
(Digit address = lIB.)
High nibble of high byte to selected digit
Select second digit of LCD (address = lOB)

Low nibble of high byte to selected digit.
Low byte of 4-digit display.
Select third digit of LCD.
(Digit address = DIE. 1

Hlgh nibble of low byte to selected digit.
Select fourth digit (address = OOBl.
Low nibble of low byte to selected digit.

MSB to carry bit (CY>

A
DATA INPUT _B3. C
A
DATA WPUT_B2. C
A
DATA INPUT _E 1, C
A
DATA_INPUT_BO.C
CHIP _SELECT
CHIP _SELECT

CY to Oata Input pin B3.
Next bit to CY.
CY to Oata Input pin B2.
Next bit to CV
CV to Data Input pln 81.
Last bit to CV.
CV to Data Input pin eo.
Toggle Chip Select.
O-to-1 transition latches info.

-

270068-23

Figure 21b. UPDATE_LCD Routine Writes 4 Digits to an LCD Driver

10-329

inter

AP-252

At this point the value of the frequency of the transducer signal, measured to 8 bit resolution, is contained in
FREQUENCY. Note that the timer can be reloaded on
the fly. Note too that the timer can be reloaded on the
fly. Note too that for 8·bit resolution only the low byte
of the frequency counter needs to be read, since the
high byte is necessarily O. However, one may want to
test the high byte to ensure that it is zero, as a sanity
check on the data. Both bytes, of course must be reloaded.

VCC

VCC
80CS1BH
RESONANT
TRANSDUCER

1-----1

INTO
OR
TO

VSS

PERIOD MEASUREMENTS
270068-24

Figure 22. Resonant Transducer Does Not
Require an AID Converter

To implement the measurement, one timer is used to
establish the sample time. The timer is preset to a value
that causes it to roll over at the end of the sample time,
generating an interrupt and waking the CPU from its
Idle mode. The required preset value is the 2's comple·
ment negative of the sample time measured in machine
cycles. The conversion from sample time to machine
cycles is to multiply it by 1/12 the clock frequency. For
example, if the cloqk frequency is 12 MHz, then a sample time of 128 ms is
(128 ms) x (12000 kHz)/12 = 128000 machine cycles.

Measuring the period of the transducer signal means
measuring the total elapsed time over a known number,
N, of transducer pulses. The quantity that is directly
measured is NT, where T is the period of the transducer signal in machine cycles. The relationship between T
in machine cycles and the transducer frequency F in
arbitrary frequency units is
T

Fxtal
-F- x (1/12).

where Fxtal is the SOCS IBH clock frequency, in the
same units as F.
The full scale range then is Nx (Tmax-Tmin). For
n-bit resolution.
1 LSB = Ns(Tmax-Tmin).

Then the required preset value to cause the timer to roll
'
over in 128 ms is

2n

Therefore the number of periods over which the elapsed
time should be measured is

- 128000 = FEOCOO, in hex digits.

Note that the preset value is 3 bytes wide whereas the
timer is only 2 bytes wide. This means the timer must
be augmented in software in the timer interrupt routine
to three bytes. The SOCS IBH has a DJNZ instruction
(decrement and jump if not zero) that makes it easier to
code the third timer byte to count down instead of up.
If the third timer byte counts down, its reload value is
the 2's complement of what it would be for an up-counter. For example, if the 2's complement of the sample
time is FEOCOO, then the reload value for the third
timer byte would be 02, instead of FE. The timer interrupt routine might then be:
TIMER_INTERRUPT_ROUTINE:
DNJZ
THIRD_TIMER_BYTE,OUT
MOV
TLO,#O
MOV
THO,#OCH
MOV
THIRD_TIMERBYTE,#2
MOV
FREQUENCY,COUNTER_LO
;Preset COUNTER to -896:
MOV
COUNTER_LO,#80H
MOV
COUNTER_HI,#OFCH
OUT:
RETI

=

2n
N = =T-m-ax-.=Tm---:-in

However, N must also be an integer. It is logical to
evaluate the above formula (don't forget Tmax and
Tmin have to be in machine cycles) and select for N the
next higher integer. This selection gives a period measurement that has somewhat more than n-bit resolution, but it can be scaled back if desired.
For example, suppose we want 8-bit resolution in the
measurement of the period of a signal whose frequency
varies from 7.1 kHz to 9 ~Hz. If the clock frequency is
12 MHz, then Tmax is (12000 kHz/1.1 kHz) x (1/12)
= 141 machine cycles. Tmin is 111 machine cycles.
The required value for N, then, is 256/(141-111) =
8.53 periods, according to the formula. Using N = 9
periods will give a maximum NT value of 141 x 9 =
1269 machine cycles. The minimum NT will be III X
9 = 999 machine cycles. A lookup table can be used to

10·330

intJ

AP-252

ADDC
MOV
CLR
MOVC
MOV
POP
POP
RET

scale these values back to a range of 0 to 255, giving
precisely the 8-bit resolution desired.
To implement the measurement, one timer is used to
measure the elapsed time, NT. The transducer is connected to one of the external interrupt pins, and this
interrupt is configured to the transition-activated mode.
In the transition-activated mode every I-to-O transition
in the transducer output will generate an interrupt. The
interrupt routine counts transducer pulses, and when it
gets to the predetermined N, it reads and clears the
timer. For the specific example cited above, the interrupt routine might be:

INTERRUPT_RESPONSE:
DJNZ
N,OUT
MOV
N,#9
CLR
EA
CLR
TRI
MOV
NT_LO,TLI
MOV
NT_HI,THI
MOV
TLl,#9
MOV
THl,#O
SETB
TRI
SETB
EA
CALL
LOOKUP_TABLE
OUT:
RETI

The 80C5lBH timers have an operating mode which is
particularly suited to pulse width measurements, and
will be useful in these applications if the transducer
signal has a fixed duty cycle.

The subroutine LOOKUP_TABLE is used to scale
the measurement back to the desired 8-bit resolution. It
can also include built-in corrections for errors or nonlinearities in the transducer's transfer function.
The subroutine uses the MOVC A, @ A + DPTR
instruction to access the table, which contains 270 entries commencing at the 16-bit address referred to as
TABLE. The subroutine must compute the address of
the table entry that corresponds to the measured value
of NT. This address is

+

NT - NTMIN,

where NTMIN = 999, in this specific example.

LOOKUP_TABLE:
PUSH
PUSH
MOV
ADD
MOV
MOV

At this point the value of the period of the transducer
signal, measured to 8 bit resolution, is contained in PERIOD.

PULSE WIDTH MEASUREMENTS

In this routine a pulse counter N is decremented from
its preset value, 9, to zero. When the counter gets to
zero it is reloaded to 9. Then all interrupts are blocked
for a short time while the timer is read and cleared. The
timer is stopped during the read and clear operations,
so "clearing" it actually means presetting it to 9, to
make up for the 9 machine cycles that are missed while
the timer is stopped.

DPTR = TABL

A,NT_HI
DPH,A
A
A,@A+DTPR
PERIOD,A
PSW
ACC

ACC
PSW
A,#LOWCTABLE-NTMINI
A,NT_LO
DPL,A
A,#HIGHCTABLE-NMTINI

In this mode the timer is turned on by the on-chip
circuitry in response to an input high at the external
interrupt pin, and offby an input low, and it can do this
while the 80C51BH is in Idle. (The "GATE" mode of
timer operation is described in the Intel Microcontroller Handbook.) The external interrupt itself can be enabled, so the same I-to-O transition from the transducer
that turns off the timer also generates an interrupt. The
interrupt routine then reads and resets the timer.
The advantage of this method is that the transducer
signal has direct access to the timer gate, with the result
that variations in interrupt response time have no effect
on the measurement.
Resonant transducers that are designed to fully exploit
the GATE mode have an internal divide-by-N circuit
that fixes the duty cycle at 50% and lowers the output
frequency to the range of 250 to 500 Hz (to control
RFI). The transfer function between transducer period
and measurand is approximately linear, with known
and repeatable error functions.

HMOS/CHMOS Interchangeability
The CHMOS version of the 8051 is architecturally
identical with the HMOS version, but there are nevertheless some important differences between them which
the designer should be aware of. In .addition, some applications require interchangeability between .HMOS
and CHMOS parts. The differences that need to be considered are as follows:
External Clock Drive: To drive the HMOS 8051 with
an external clock signal, one normally grounds the
XTALI pin and drives the XTAL2 pin. To drive the
,CHMOS 8051 with an external clock signal, one must
drive the XTALl pin and leave the XTAL2 pin unconnected. The reason for the difference is that in the

10-331

AP-252

HMOS 8051, it is the XTAL2 pin that drives the internal clocking circuits, whereas in the CHMOS version it
is the XTALI pin that drives the internal clocking circuits.

HMOS

There are several ways to design an external clock drive
to work with both types. For low clock frequencies (below 6 MHz), the HMOS 8051 can be driven in the same
way as the CHMOS version, namely, throu~h XTA~I
with XTAL2 unconnected. Another way IS to dnve
both XTALI and XTAL2; that is, drive XTALI and
use and external inverter to derive from XTALI a signal with which to drive XT AL2.
In either case, a 74HC or 74HCT circuit makes an excellent driver for XTALI and/or XTAL2, because neither the HMOS nor the CHMOS XTAL pins have
TTL-like input logic levels.
Unused Pins: Unused pins of Ports I, 2 and 3 can be
ignored in both HMOS and CHMOS designs. The internal pullups will put them into a defined state. Unused Port 0 pins in 8051 applications can be ignored,
even if they're floating. But in 80C5IBH applications,
these pins should not be left afloat. They can be externally pulled up or down, or they can be internally
pulled down by writing Os to them.
8031180C3IBH designs mayor may not need pullups
on Port O. Pullups aren't needed for program fetches,
because in bus operations the pins are actively pulled
high or low by either the 8031 or the external program
memory. But they are needed for the CHMOS part if
the Idle or Power Down mode is invoked, because in
these modes Port 0 floats.
Logic Levels: If Vee is between 4.5V and 5.5V, an
input signal that meets the HMOS 8051's input logic
levels will also meet the CHMOS 80C5IBH's input logic levels (except for XTALl/XTAL2 and RST). For
the same Vee condition, the CHMOS device will reach
or surpass the output logic levels of the HMOS device.
The HMOS device will not necessarily reach the output
logic levels of the CHMOS device. T~is is an impor~~nt
consideration if HMOS/CHMOS mterchangeablhty
must be maintained in an otherwise CMOS system.
HMOS 8051 outputs that have internal pullups (Ports
1,2, and 3) "typically" reach 4V or more ifiOH i~ zero,
but not fast enough to meet timing specs. Addmg an
external pullup resistor will ensure the logic level, but
still not the timing, as shown in Figure 23. If timing is
an issue, the best way to interface HMOS to CMOS is
through a 74HCT circuit.

270068-25

Figure 23. O-to-1 Transition Shows Unspec'd
Delay (At) in HMOS to 74HC Logic

wishes to preserve the capability of interchanging
HMOS and CHMOS 8051s the software has to be designed so that the HMOS parts will respond in an acceptable manner when a CHMOS reduced power mode
is invoked.
'
For example, an instruction that invokes Power Down
can be followed by a "JMP $":

CLR
ORL

EA
PCON.#2

JMP

$

The CHMOS and HMOS parts will respond to this
sequence of code differently. The CHMOS part: going
into a normal CHMOS Power Down Mode, w!ll stop
fetching instructions until it gets a hardware reset. The
HMOS part. will go through the motions of executing
the ORL instruction, and then fetch the JMP instruction. It will continue fetching and executing JMP $ until hardware reset.
Maintaining HMOS/CHMOS 8051 interchangeability
in response to Idle requires more planning. The HMOS
part will not respond to the instruction that puts the
CHMOS part into Idle, so that instruction needs.to.be
followed by a software idle. This would be an 'Idlmg
loop which would be terminated by the same conditions
that would terminate the CHMOS's hardware Idle.
Then when the CHMOS device goes into Idle, the
HMOS version executes the idling loop, until either a
hardware reset or an enabled interrupt is received. Now
if Idle is terminated by an interrupt, execution for the
CHMOS device will proceed after RETI from the instruction following the one that invoked Idle. The instruction following the one that invoked Idle is the
idling loop that was inserted for the HMOS device. At
this point, both the HMOS and CHMC?S devices ~ust
be able to fall through the loop to contmue execution.

Idle and Power Down: The Idle and Power Down
modes exist only on the CHMOS devices, but if one

10-332

AP-252

One way to achieve the desired effect is to define a
"fake" Idle flag, and set it just before going into Idle.
The instruction that invoked Idle is followed by a software idle:

SETB
ORL

JB

IDLE
PCON,#l
IDLE, $

Now the interrupt that terminates the CHMOS's Idle
must also break the software idle. It does so by clearing
the "Idle" bit:
CLR
RETI

IDLE

Note too that the PCON register in the HMOS 8051
contains only one bit, SMOD, whereas the PCON register in CHMOS contains SMOD plus four other bits.
Two of those other bits are general purpose flags. Maintaining HMOS/CHMOS interchangeability requires
that these flags not be used.

REFERENCES
1. Pawlowski, Moroyan, Alnether, "Inside CMOS'
Technology," BYTE magazine, Sept., 1983. Available as Article Reprint AR-302.
2. Kokkonen, Pashley, "Modular Approach to C-MOS
Technology Tailors Process to Application,"
Electronics, May, 1984. Available as Article Reprint
AR-332.
3. Williamson, T., Designing Microcontroller Systems
for Electrically Noisy Environments. Intel Application Note AP-125, Feb. 1982.
4. Williamson, T., "PC Layout Techniques for Minimizing Noise," Mini-Micro Southeast. Session 9,
Jan., 1984.
5. Alnether, J., High Speed Memory System Design Using 2147H. Intel Application Note AP-74. March
1980.
6. Ott, H., "Digital Circuit Grounding and Interconnection," Proceedings of the IEEE Symposium on
Electromagnetic Compatibility. pp. 292-297, Aug.
1981.
7. Digital Sensors by Technar. Technar Inc., 205 North
2nd Ave.,-Arcadia, CA 91006.

10-333

APPLICATION
NOTE

AP-281

July 1986

UPI-4S2 Accelerates iAPX 286
Bus Performance

CHRISTOPHER SCOTT
TECHNICAL MARKETING ENGINEER
INTEL CORPORATION

Order Number: 292018-001
10-334

AP·281

INTRODUCTION
The UPI-452 targets the leading problem in peripheral
to host interfacing, the interface of a slow peripheral
with a fast Host or "bus utilization". The solution is
data buffering to reduce the delay and overhead of
transferring data between the Host microprocessor and
I/O subsystem. The Intel CMOS UPI-452 solves this
problem by combining a sophisticated programmable
FIFO buffer and a slave interface with an MSC-51
based microcontroller.
The UPI-452 is Intel's newest Universal Peripheral Interface family member. The UPI-452 FIFO buffer enables Host-peripheral communications to be through
streams or bursts of data rather than by individual
bytes. In addition the FIFO provides a means of embedding cpmmands within a stream or block of data.
This enables the system designer to manage data and
commands to further off-load the Host.
The UPI-452 interfaces to the iAPX 286 microprocessor as a standard Intel slave peripheral device. READ,
WRITE, CS and address lines from the Host are used
to access all of the Host addressable UPI-452 Special
Function Registers (SFR).
The UPI-452 combines an MSC-51 microcontroller,
with 256 bytes. of on-chip RAM and 8K bytes of
EPROM/ROM, twice that of the SOC5l, a two channel
DMA controller and a sophisticated 128 byte, two
channel, bidirectional FIFO in a single device. The
UPI-452 retains all of the 80C5l architecture, and is
fully compatible with the MSC-5.1 instruction set.
This application note is a description of an iAPX 286 to
UPI-452 slave interface. Included is a discussion of the
respective timings and design considerations. This application note is meant as a supplement to the UPI-452
Advance Data Sheet. The user should consult the data
sheet for addi·tional details on the various UPI-452
functions and features.

HOST·UPI·452 FIFO SLAVE
INTERFACE
The UPI-452 FIFO acts as a buffer between the external Host 80286 and the internal CPU. The FIFO allows
the Host - peripheral interface to achieve maximum decoupling of the interface. Each of the two FIFO channels is fully user programmable. The FIFO buffer ensures that the respective CPU, Host or internal CPU,
receives data in the same order as transmitted. Three
slave bus interface handshake methods are supported
by the UPI-452; DMA, Interrupt and Polled.
The interface between the Host 80286 and the UPI-452
is accomplished with a minimum of signals. The 8 bit
data bus plus READ, WRITE, CS, and AO-2 provide
access to all of the externally addressable UPI-452 registers including the two FIFO channels. Interrupt and
DMA handshaking pins are tied directly to the interrupt controller and DMA controller respectively.
DMA transfers between the Host and UPI-452 are controlled by the Host processors DMA controller. In the
example shown in Figure I, the Host DMA controller
is the 82258 Advanced DMA Controller. An internal
DMA transfer to or from the FIFO, as well as between
other internal elements, is controlled by the UPI-452
internal DMA processor. The internal DMA processor
can also transfer data between Input and Output FIFO
channels directly. The description that follows details
the UPI-452 interface from both the Host processor's
and the UPI-452's internal CPU perspective.
One of the unique features of the UPI-452 FIFO is its
ability to distinguish between commands and data embedded in the same data block. Both interrupts and
status flags are provided to support this operation in
either direction of data transfer. These flags and interrupts are triggered by the FIFO logic independent of,
and transparent to either the Host or internal CPUs;
Commands embedded in the data block, or stream, are
called Data Stream Commands.
0

UPI·452 iAPX 286 SYSTEM
CONFIGURATION

o

The interface described in this application note is
shown in Figure I, iAPX 286 UPI-452 System Block
Diagram. The iAPX 286 system is configured in a local
bus architecture design. DMA between the Host and
the UPI-452 is supported by the 82258 Advanced
DMA Controller. The Host microprocessor accesses all
UPI-452 externally addressable registers through address decoding (see Table 3, UPI-452 External Address
Decoding). The timings and interface descriptions below are given in equation form with examples of specific calculations. The goal of this application note is a set
of interface analysis equations. These equations are the
tools a system designer can use to fully utilize the features of the UPI-452 to achieve maximum system performance.

Programmable FIFO channel Thr~sholds are another
unique feature of the UPI-452. The Thresholds provide
for interrupting the Host only when the Threshold
number of bytes can be read or written to the FIFO
buffer. This further decouples the Host UPI-452 inter"
face by relieving the Host of polling the buffer to determine the number of bytes that can be read or written. It
also red \Ices the chances of overrun and underrun errors which must be processed.
The UPI-452 also provides a means of bypassing the
FIFO, in both directions, for an immediate interrupt of
either the Host or internal CPU. These commands are
called Immediate Commands. A complete description
of the internal FIFO logic operation is given in the
FIFO Data Structure section.

10-335

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292018-1

AP-281

UPI-4S2 INITIALIZATION
The UPI-4S2 at power-on reset automatically performs
a minimum initialization of itself. The UPI-4S2 notifies
the Host that it is in the process of initialization by
setting a Host Status SFR bit. The user UPI-4S2 program must release the UPI-4S2 from initialization for
the FIFO to be accessible by the Host. This is the minimum Host to UPI-4S2 initialization sequence. All further initialization and configuration of the UPI-4S2, including the FIFO, is done by the internal CPU under
user program control. No interaction or programming
is required by the Host 80286 for UPI-4S2 initialization.

Host read/write access of the FIFO. The internal CPU
sets the Slave Control (SLCON) SFR FIFO DMA
Freeze/Normal Mode (FRZ) bit high (= 1) to activate
Normal Mode. Ths causes the Slave Status (SSTAT)
and Host Status (HSTAT) SFR FIFO DMA Freeze
Mode bits to be set to Normal Mode. Table 2, UPI-4S2
Initialization Event Sequence Example, shows a summary of the initialization events described above.
Table 1. FIFO SpeCial Function
Register Default Values

At power-on reset the UPI-4S2 automatically enters
FIFO DMA Freeze Mode by resetting the Slave Control (SLCON) SFR FIFO DMA Freeze/Normal Mode
bit to FIFO DMA Freeze Mode (FRZ = "0"). This
forces the Slave Status (SSTAT) and Host Status
(HSTAT) SFR FIFO DMA Freeze/Normal Mode bits
to FIFO DMA Freeze Mode In Progress. FIFO DMA
Freeze Mode allows the FIFO interface to be configured, by the internal CPU, while inhibiting Host access
to the FIFO.

SFR Name

Label

Reset
Value

Channel Boundary Pointer
Output Channel Read Pointer
Output Channel Write Pointer
Input Channel Read Pointer
Input Channel Write Pointer
Input Threshold
Output Threshold

CBP
ORPR
OWPR
IRPR
IWPR
ITH
OTH

40H/640
40H/640
40H/640
OOH/DO
DOH/OO
DOH/OO
01 H/1 0

Table 2. UPI-452 Initialization
Event Sequence Example
Event Description

SFR/bit

Power-on Reset

The MODE SFR is forced to zero at reset. This disables, (tri-states) the DRQIN/INTRQIN, DRQOUT/
INTRQOUT and INTRQ output pins. INTRQ is inhibited from going active to reflect the fact that a 'Host
Status SFR bit, FIFO DMA Freeze Mode, is active. If
the MODE SFR INTRQ configure bit is enabled
(= 'I '), before the Slave Control and Host Status SFR
FIFO DMA Freeze/Normal Mode bit is set to Normal
Mode, INTRQ will go active immediately.

UPI-4S2 forces FIFO OMA
Freeze Mode (Host access to
FIFO inhibited)

UPI-4S2 forces Slave Status and SSTAT SSTS
HSTAT HST1
Host Status SFR to FIFO OMA
Freeze Mode In Progress

0

= 0
= 1

UPI-4S2 forces all SFRs,
including FIFO SFRs, to default
values.

The first action by the Host following reset is to read
the UPI-4S2 Host Status SFR Freeze/Normal Mode
bit to determine the status of the interface. This may be
done in response to a UPI-4S2 INTRQ interrupt, or by
polling the Host Status SFR. Reading the Host Status
SFR resets the INTRQ line low.

MOOEM04
• UPI-4S2 user program enables
INTRa, INTRa goes active, high

Any of the five FIFO interface SFRs, as well as a variety of additional features, may be programmed by the
internal CPU following reset. At power-on reset, the
five FIFO Special Function Registers are set to their
default values as listed in Table 1. All reserved location
bits are set to one, all other bits are set to zero in these
three SFRs. The FIFO SFRs listed in Table I can be
programmed only while the UPI-4S2 is in FIFO DMA
Freeze Mode. The balance of the UPI-4S2 SFRs default
values and descriptions are listed in the UPI-4S2 Advance Data Sheet in the Intel Microsystems Component Handbook Volume II and Microcontroller Handbook.

• UPI-4S2 user program initializes
any other SFRs; FIFO, Interrupts,
Timers/Counters, etc.

The above sequence is the minimum UPI-4S2 internal
initialization required. The last initialization instruction
must always set the UPI-4S2 to Normal Mode. This
causes the UPI-4S2 to exit Freeze Mode and enables

=

SLCON FRZ

=

1

=

1

• Host READ's UPI-4S2 Host
Status (HSTAT) SFR to
determine interrupt source,
INTRa goes low

User program sets Slave Control SLCON FRZ
SFR to Normal Mode (Host
access to FIFO enabled)
UPI-4S2 forces Slave and Host
Status $FRs bits to Normal
Operation
• Host polls Host Status SFR to
determine when it can access the
FIFO
-or• Host waits for UPI-4S2 Request
for Service interrupt to access
FIFO

• user option

10-337

SSTAT SST5
HSTAT HST1

=
=

1
0

AP-281

Commands can be used to structure or dispatch the
data by defining the start and end of data blocks or
packets, or how the data following a DSC is to be processed.

FIFO DATA STRUCTURES
Overview
The UPI-4S2 provides three means of communication
between the Host microprocessor and the UPI-4S2 in
either direction;
Data
Data Stream Commands
Immediate Commands
Data and Data Stream Commands (DSC) are transferred between the Host and UPI-4S2 through the UPI4S2 FIFO buffer. The third, Immediate Commands,
provides a means of bypassing the FIFO entirely. These
three data types are in addition to direct access by either Host or Internal CPU of dedicated Status and
Control Special Function Registers (SFR).
The FIFO appears to both the Host 80286 and the internal CPU as 8 bits wide. Internally the FIFO is logically nine bits wide. The ninth bit indicates whether the
byte is a data or a Data Stream Command (DSC) byte;
o = data, 1 = DSC. The ninth bit is set by the FIFO
logic in response to the address specified when writing
to the FIFO by either Host or internal CPU. The FIFO
uses the ninth bit to condition the UPI-4S2 interrupts
and status flags as a byte is made available for a Host or
internal CPU read from the FIFO. Figures 2 and 3
show the structure of each FIFO channel and the logical ninth bit.
It is important to note that both data and DSCs are

actually entered into the FIFO buffer (see Figures 2
and 3). External addressing of the FIFO determines the
state ofthe internal FIFO logic ninth bit. Tabie 3 shows
the UPI-4S2 External Address Decoding used by the
Host and the corresponding action. The internal CPU
interface to the FIFO is essentially identical to the external Host interface. Dedicated internal Special Function Registers provide the interface between the FIFO,
internal CPU and the internal two channel DMA processor. FIFO read and write operations by the Host and
internal CPU are interleaved by the UPI-4S2 so they
appear to be occurring simultaneously.
The ninth bit provides a means of supporting two data
types within the FIFO buffer. This feature enables the
Host and UPI-4S2 to transfer both commands and data
while maintaining the decoupled interface a FIFO buff. er provides. The logical ninth bit provides both a means
of embedding commands within a block of data and a
means for the internal CPU, or external Host, to discriminate between data and commands. Data or DSCs
may be written in any order desired. Data Stream

A Data Stream Command (DSC) acts as an internal
service routine vector. The DSC generates an interrupt
to a service routine which reads the DSC. The DSC
byte acts as an address vector to a user defined service
routine. The address can be any program or data memory location with no restriction on the number of DSCs
or address boundaries.
A Data Stream Command (DSC) can also be used to
clear data from the FIFO or "FLUSH" the FIFO. This
is done by appending a DSC to the end of a block of
data entered in the FIFO which is less than the programmed threshold number of bytes. The DSC will
cause an interrupt, if enabled, to the respective receiving CPU. This ensures that a less than Thresholdnumber of bytes in the FIFO will be read. Two conditions
force a Request for Service interrupt, if enabled, to the
Host. The first is due to a Threshold number of bytes
having been written to the FIFO Output channel; the
second is if a DSC is written to the Output FIFO channel. Ifiess than the Threshold number of bytes are written to the Output FIFO channel, the Host Status SFR
flag will not be set, and a Request for Service interrupt
will not be generated, if enabled. By appending a DSC
to end of the data block, the FIFO Request for Service
flag and/or interrupt will be generated.
An example of a FIFO Flush application is a mass storage subsystem. The UPI-4S2 provides the system interface to a subsystem which supports tape and disk storage. The FIFO size is dynamically changed to provide
the maximum buffer size for the direction of transfer.
Large data blocks are the norm in this application. The
FIFO Flush provides a means of purging the FIFO of
the last bytes of a transfer. This guarantees that the
block, no matter what its size, will be transmitted out of
the FIFO.
Immediate Commands allow more direct communication between the Host processor and the UPI-4S2 by
bypassing the FIFO in either direction. The Immediate
Command IN and OUT SFRs are two more unique
address locations externally and internally addressable.
Both DSCs and Immediate Commands have internal
interrupts and interrupt priorities associated with their
operation. The interrupts are enabled or disabled by
setting corresponding bits in the Slave Control
(SLCON), Interrupt Enable (IEC), Interrupt Priority
(IPC) and Interrupt Enable and Priority (IEP) SFRs. A
detailed description of each of these may be found in
the UPI-4S2 Advance Information Data Sheet.

10-338

AP-281

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INPUT
FIFO
CHANNEL

z
o
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INTERNAL CPU
(DATA PROCESSOR)

292018-2

Figure 2. Input FIFO Channel Functional Diagram

10-339

intJ

AP-281

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292018-3

Figure 3. Output FIFO Channel Functional Diagram

10-340

AP-281

Table 3. UPI-452 External Address Decoding
DACK

CS

A2

A1

AD

1
1

1

0

X
0

X
0

X
0

1

0

0

0

1

0

0

1

0

1
1
0

READ

WRITE

No Operation

No Operation

Data or DMA from
Output FIFO Channel

Data or DMA to
Input FIFO Channel

1

Data Stream Command
from Output FIFO
Channel

Data Stream Command
to Input FIFO
Channel

1

0

Host Status SFR
Read

Reserved

0

1

1

Host Control SFR
Read

Host Control SFR
Write

0

1

0

0

Immediate Command
SFR Read

Immediate Command
SFRWrite

0
X

1

1

Reserved

X

X
X

Reserved

X

DMA Data from
Output FIFO Channel

DMA Data to Input
FIFO Channel

Below is a detailed description of each FIFO channel's
operation, including the FIFO logic response to the
ninth bit, as a byte moves through the channel. The
description covers each of the three data types for each
channel. The details below provide a picture of the various FIFO features and operation. By understanding the
FIFO structure and operation the user can optimize the
interface to meet the requirements of an individual design.

OUTPUT CHANNEL
This section covers the data path from the internal
CPU to the HOST. Data Stream Command or Immediate Command processing during ,Host DMA Operations is covered in the DMA section.

UPI-4S2 Internal Write to the FIFO
The internal CPU writes data and Data Stream Commands into the FIFO through the FIFO OUT (FOUT)
and Command OUT (COUT) SFRs. Wh,~n a Threshold number of bytes has been written, the Host Status
SFR Output FIFO Request for Service bit is set and an
interrupt, if enabled, is generated to the Host. Either
the INTRQ or DRQOUT/INTRQOUT output pins
can be used for this interrupt as determined by the
MODE and Host Control (HCON) SFR setting. The
Host responds to the Request for Service interrupt by
reading the Host Status (HSTAT) SFR to determine
the source of the interrupt. The Host then reads the
Threshold number of bytes from the FIFO. The internal CPU may continue to write to the FIFO during the
Host read of the FIFO Output channel.

10-341

AP-281

Data Stream Commands may be written to the Output
FIFO channel at any time during a write of data bytes.
The write instruction need only specify the Command
Out (coUT) SFR in the direct register instruction
used. Immediate Commands may also be written at any
time to the Immediate Command OUT (IMOUT) SFR.
The Host reads Immediate Commands from the Immediate Command OUT (IMOUT).
The internal CPU can determine the number of bytes to
write to the FIFO Output channel in one of three ways.
The first, and most efficient, is by utilizing the internal
DMA processor which will automatically manage the
writing of data to avoid Underrun or 'Overrun Errors.
The second is for the internal CPU to read the Output
FIFO channels Read and Write Pointers and compare
their values to determine the available space. The third
method for determining the available FIFO space is to
always write the programmed channel size number of
bytes to the Output FIFO. This method would use the
Overrun Error flag and interrupt to halt FIFO writing
whenever the available space was less than the channel
size. The interrupt service routine could read the channel pointers to determine or monitor the available channel space. The time required for the internal CPU to
write data to the Output FIFO channel is a function of
the individual instruction cycle time and the number of
bytes to be written.

Host Read from the FIFO
The Host reads data or Data Stream Commands (DSC)
from the FIFO in response to the Host Status
(HSTAT) SFR flags and interrupts, if enabled. All
Host read operations access the same UPI-452 internal
I/O ButTer Latch. At the end of the previous Host
FIFO read' cycle a byte is loaded from the FIFO into
the I/O Buffer Latch and Host Status (HSTA T) SFR
bit 5 is set or cleared (I = DSC, 0 = data) to reflect
the state of the byte'S FIFO ninth bit. If the FIFO ninth
bit is set (= 1) indicating a DSC, an interrupt is generated to the external Host via INTRQ pin or
INTRQIN/INTRQOUT pins as determined by Host
Control (HCON) SFR bit 1. The Host then reads the
Host Status (HSTAT) SFR to determine the source of
the interrupt.

The most efficient Host read operation of the FIFO
Output channel is through the use of Host DMA. The
UPI-452 fully supports external DMA handshaking.
The MODE and Host Control SFRs control the configuration of UPI-452 Host DMA handshake outputs. If
Host DMA is used the Threshold Request for Service
interrupt asserts the UPI-452 DMA Request
(DRQOUT) output. The Host DMA processor acknowledges with DACK which acts as a chip select of
the FIFO channels. The DMA transfer would stop
when either the threshold byte count had been read, as
programmed in the Host DMA processor, or when the
DRQOUT output is brought inactive by the UPI-452.

INPUT CHANNEL
This section covers the data path from the HOST to the
internal CPU or internal DMA processor. The details
of. Data Stream Command or Immediate Command
processing during internal DMA operations are covered in the DMA section below.

Host Write to the FIFO
The Host writes data and Data Stream Commands into
the FIFO through the FIFO IN (FIN) and Command
IN (CIN) SFRs. When a Threshold number of bytes
has been read out of the Input FIFO channel by the
internal CPU, the Host Status SFR Input FIFO Request for Service bit is set and an interrupt, if enabled,
is generated to the Host. The Input. FIFO Threshold
interrupt tells the Host that it may write the next block
of data into the FIFO. Either the INTRQ or DRQIN/
INTRQIN output pins can be used for this interrupi as
determined by the MODE and Host Control (HCON)
SFR settings. The Host may continue to write to the
FIFO Input channel during the internal CPU read of
the FIFO. Data Stream Commands may be written to
the FIFO Input channel at any time during a write of
data bytes. Immediate Commands may also be written
at any time to the Immediate Command IN (IMIN)
SFR.

10-342

inter

AP-281

The Host also has three methods for determining the
available FIFO space. Two are essentially identical to
that of the internal CPU. They involve reading the
FIFO Input channel pointers and using the Host Status
SFR Underrun and Overrun Error flags and Request
for Service interrupts these would generate, if enabled
in combination. The third involves using the UPI-4S2
Host DMA controller handshake signals and the programmed Input FIFO Threshold. The Host would receive a Request for Service interrupt when an Input
FIFO channel has a Theshold number of bytes able to
be written by the Host. The Host service routine would
then write the Threshold number of bytes to the FIFO.
If a Host DMA is used to write to the FIFO Input
channel, the Threshold Request for Service interrupt
could assert the UPI-4S2 DRQIN output. The Host
DMA processor would assert DACK and the FIFO
write would be completed by Host the DMA processor.
The DMA transfer would stop when either the Threshold byte count had been written or the DRQIN output
was removed by the UPI-4S2. Additional details on
Host and internal DMA operation is given below.

Internal Read of the FIFO
At the end of an internal CPU read cycle a byte is
loaded from the FIFO buffer into the FIFO IN/Command IN SFR and Slave Status (SSTAT) SFR bit lis
set or cleared (I = data, 0 = DSC) to reflect the state
of the FIFO ninth bit. If the byte is a DSC, the FIFO
ninth bit is set (= I) and an interrupt is generated, if
enabled, to the Internal CPU. The internal CPU then
reads the Slave Status (SSTAT) SFR to determine the
source of the interrupt.
Immediate Commands are written by the Host and
read by the internal CPU through the Immediate Command IN (IMIN) SFR. Once written, an Immediate
Command sets the Slave Status (SSTAT) SFR flag bit
and generates an interrupt, if enabled, to the internal
CPU. In response to the interrupt the internal CPU

reads the Slave Status (SSTAT) SFR to determine the
source of the interrupt and service the Immediate Command.

FIFO INPUTIOUTPUT CHANNEL SIZE
Host
The Host does not have direct control of the FIFO
Input or Output channel sizes or configuration. The
Host can, however, issue Data Stream Commands or
Immediate Commands to the UPI-4S2 instructing the
UPI-4S2 to reconfigure the FIFO interface by invoking
FIFO DMA Freeze Mode. The Data Stream Command or Immediate Command would be a vector to a
service routine which performs the specific reconfiguration.

UPI-452 Internal
The default power-on reset FIFO channel sizes are listed in the "Initialization" section and can be set only by
the internal CPU during FIFO DMA Frcczc Mode.
The FIFO channel size is selected 10 ac:hicve Ihe oplimum application performance. The enlirc 12H hyle
FIFO can be allocated to either the Input or Output
. channel. In this case the other channel consists of a
single SFR; FIFO IN/Command IN or FIFO OUT/
Command OUT SFR. Figure 4 shows a FIFO division
with a portion devoted to each channel. Figure 5 shows
a FIFO configuration with a11128 bytes assigned to the
Output channel.
The FIFO channel Threshold feature allows the user to
match the .FIFO channel size and the performance of
the internal and Host data transfer rates. The programmed Threshold provides an elasticity to the data
transfer operation. An example is if the Host FIFO

HOST CPU

FIFO
INPUT
CHANNEL
CHANNEL
BOUNDRY ~.t---"'"
POINTER
FIFO
(CBP)
OUTPUT
CHANNEL

FIFOINSFR

~
INTERNAL
CPU

FIFO OUT SFR

HOST CPU

292018-4

Figure 4. Full Duplex FIFO Operation

10-343

AP-281

HOST
CHANNEL
BOUNDRY
POINTER
(CBP)

-+

cpu-+I

FIFO
INPUT
CHANNEL

FIFO IN SFR

1-+
INTERNAL
CPU

H

fiFO OUT SFR .

J+-

~

HOST CPU

292018-5

Figure 5. Entire FIFO Assigned to Output Channel

data transfer rate is twice as fast as the internal FIFO
DMA data transfer rate. In this example the FIFO Input channel size is programmed to be 64 bytes and the
Input channel Threshold is programmed to be 20 bytes.
The Host writes the first 64 bytes to the Input FIFO.
When the internal DMA processor has read 20 bytes
the Threshold interrupt, or DMA request (DRQIN), is
generated to signal the Host.to begin writing.more data
to the Input FIFO channel. The internal DMA processor continues to read data from the Input channel as
the Host, or Host DMA processor, writes to the FIFO.
The Host can write 40 bytes to the FIFO Input channels in the time it takes for the internal DMA processor
to read 20 more bytes from it. This will keep both the
Host and internal DMA operating at their maximum
rates without forcing one to wait for the other.
Two methods of managing the FIFO size are possible;
fixed and variable channel size. A fixed channel size is
one where the channel is configured at initialization
and remains unchanged throughout program execution.
In a variable FIFO channel size. the configuration is
changed dynamically to meet the data transmission requirements as needed. An example of a variable channel size application is the mass storage subsystem described earlier. To meet the demands of a large data
block transfer the FIFO size could be fully allocated to
the Input or Output channel as needed. The Thresholds
are also reprogrammed to match the respective data
transfer rates.
An example of a fixed channel size application might be
one which uses the UPI-452 to directly control a series
of stepper motors. The UPI-452 manages the motor
operation and status as required. This would include
pulse train, acceleration, deceleration and feedback.
The Host transmits motor commands to the UPI-452 in
blocks of 6-10 bytes. Each block of motor command
data is preceded by a command to the QPI-452 which
selects a specific motor. The UPI-452 transmits blocks
of data to the Host which provides motor and overall
system status. The data and embedded commands
structure, indicating the specific motor, is the same. In

this example the default 64 bytes per channel might be
adequate for both channels.

INTERRUPT RESPONSE TIMING
Interrupts enable the Host UPI"452 FIFO buffer interface and the internal CPU FIFO buffer interface to
operate with a minimum of overhead on the respective
CPU. Each CPU is "interrupted" to service the FIFO
on an as needed basis only. In configuring the FIFO
buffer Thresholds and choosing the appropriate internal DMA Mode the user must take into account the
interrupt response time for both CPUs. These response
times will affect the DMA transfer rates for each channel. By choosing FIFO channel Thresholds which reflect both the respective DMA transfer rate and the
interrupt response time the user will achieve the maximum data throughput and system bus decoupling. This
in turn will mean the overall available system bus bandwidth will increase.
The following section describes the FIFO interrupt interface to the Host and internal CPU. It also describes
an analysis of sample interrupt response times for the
Host and UPI-452 internal cpu. These equations and
the example times shown are then used in the DMA
section to further analyze an optimum Host UPI-452
interface.

HOST
Interrupts to the Host processor are supported by the
three UPI-452 output pins; INTRQ, DRQINI
INTRQIN and DRQOUT/INTRQOUT. INTRQ is a
general purpose Request For Service interrupt output.
DRQIN/INTRQIN and DRQOUT/INRQOUT pins
are multiplexed to provide two special "Request for
Service" FIFO interrupt request lines when DMA is
disabled. A FIFO Input or Output channel Request for
Service interrupt is generated based upon the value programmed in the respective channel's Threshold SFRs;
Input Threshold (ITHR), and Output Threshold

10-344

AP-281

(OTHR) SFRs. Additional interrupts are provided for
FIFO Underrun and Overrun Errors, Data Stream
Commands, and Immediate Commands. Table 4 lis~s
the eight UPI-452 interrupt sources as they appear In
the HSTAT SFR to the Host processor.

To initiate the interrupt the UPI-452 activates the
INTRQ output. The interrupt acknowledge sequence
requires two bus cycles, 400 ns (10 MHz iAPX 286),
for the two INTA pulse sequence.
Equation 1. Host Interrupt Response Time

Table 4 UPI-4S2 to Host Interrupt Sources
HSTAT
SFR Bit

HST7
HST6
HST5
HST4
HST3
HST2
HST1
HSTO

Action

Interrupt Source

Time

Current instruction execution
800 ns
completion
INTA sequence
400 ns
Interrupt service routine (time
to host first READ of UPI-452) 2000 ns
Total Interrupt Response Time
2.3/Ls

Output FIFO Underrun Error
Immediate Command Out SFR Status
Data Stream Command/Data at Output
FIFO Status
Output FIFO Request for Service Status
Input FIFO Overrun Error Condition
Immediate Comamnd In SFR Status
FIFO DMA FreezelNormal Mode
Status
Input FIFO Request for Service

Bus

Cycles'
4
.2
10
16

NOTE:
10 MHz iAPX 286 bus cycle, 200 ns each

UPI-4S2 Internal

. The interrupt response time required by the Host processor is application and system specific. In general, a
typical sequence of Host interrupt response eve~ts a~d
the approximate times associated with each are listed In
Equation 1.
The example assumes the hardware configuration
shown in Fjgure 1, iAPX 286IUPI-452 Block Diagram,
with an 8259A Programmable Interrupt Controller.
The timing analysis in Equation I also assumes the following; no other interrupt is either in process or pending, nor is the 286 in a LOCK condition. The current
instruction completion time is 8 clock cycles (800 ns @
10 MHz), or 4 bus cycles. The interrupt service routine
first executes a PUSHA instruction, PUSH All General
Registers, to save all iAPX 286 internal registers. This
requires 19 clocks (or 2.0 /Ls @ 10 MHz), or 10 bus
cycles (rounded to complete bus cycle). The next service routine instruction reads the UPI-452 Host Status
SFR to determine the interrupt source.
It is important to note that any UPI-452 INTRQ interrupt service routine should ALWAYS mask for the
Freeze Mode bit first. This will insure that Freeze
Mode always has the highest priority. This will also
save the time required to mask for bits which are forced
inactive during Freeze Mode, before checking the
Freeze Mode bit. Access to the FIFO channels by the
Host is inhibited during Freeze Mode. Freeze Mode is
covered in more detail below.

The internal CPU FIFO interrupt interface is essentially identical to that of the Host to the FIFO. T~ree
internal interrupt sources support the FIFO operatIOn;
FIFO-Slave bus Interface Buffer, DMA Channel 0 and
DMA Channell Requests. These interrupts provide a
maximum decoupling of the FIFO buffer and the internal CPU. The four different internal DMA Modes
available add flexibility to the interface.
The FIFO-Slave Bus Interface interrupt response is
also similar to the Host response to an INTRQ Request
for Service interrupt. The internal CPU responds to the
interrupt by reading the Slave Status (SSTAT) SFR to
determine the source of the interrupt. This allows the
user to prioritize the Slave Status flag response to meet
the users application needs.
The internal interrupt response time is dependent on
the current instruction execution, whether the interrupt
is enabled, and the interrupt priority. In general, to finish execution of the current instruction, respond to the
interrupt request,·push the Program Counter (PC) and
vector to the first instruction of the interrupt service
routine requires from 38 to 86 oscillator periods (2.38
to 5.38 /Ls @ 16 MHz). If the interrupt is due to an
Immediate Command or DSC, additional time is required to read t.he Immediate Command or DSC SFR
and vector to the appropriate service routine. This
means two service routines back to back. One service
routine to read the Slave Status (SSTAT) SFR to determine the source of the Request for Service interrupt,
and second the service routine pointed to by the Immediate Command or DSC byte read from the respective
SFR.

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Table 5. Host UPI-452
Data Transfer Performance

DMA
DMA is the fastest and most efficient way for the Host
or internal CPU to communicate with the FIFO buffer.
The UPI-452 provides support for both of these DMA
paths. The two DMA paths and operations are fully
independent of each other and can function simultaneously. While the Host DMA processor is performing
a DMA transfer to Qr from the FIFO, the UPI-452
internal DMA processor can be doing the same.
Below are descriptions of both the Host and internal
DMA operations. Both DMA paths can operate asynchronously and at different transfer rates. In order to
make the most of this simultaneous asynchronous operation it is necessary to calculate the two transfer rates
and accurately match their operations. Matching the
different transfer rates is done by a combination of accurately programmed FIFO channel size and channel
Thresholds. This provid~s the maximum Host and internal CPU to FIFO buffer interface decoupling. Below
is a description of each of the two DMA operations and
sample calculations for determining transfer rates. The
next section of this application note, "Interface Latency", details the considerations involved in analyzing effective transfer rates when the overhead associated with
each transfer is considered.

HOST FIFO· DMA
DMA transfers between the Host and UPI-452 FIFO
buffer are controlled by the Host CPU's DMA controller, and is independent of the UPl c452's internal two
channel DMA processor. The UPI-452's internal DMA
processor supports data transfers between the UPI-452
internal RAM, external RAM (via the Local Expansion
Bus) and the various Special Function Registers including the FIFO Input imd Output channel SFRs.

Wait States:
Processor &
Speed

iAPX-186*

8MHz
10 MHz
12.5 MHz
iAPX-286*' 6 MHz
8MHz
10 MHz

Back to Back
READI
WRITE's

DMA:
Two
Single
Cycie
Cycle

0
0
1
0
1
2

N/A'
N/A'
N/A*
0
1
2

0
0
0
0
0
0

NOTES:
• iAPX 186 On-chip DMA processor is two cycle operation
only.
•• iAPX 286 assumes 82258 ADMA (or other DMA) running 286 bus cycles at 286 clo,ck rate.

In this application note system example, shown in Figure I, DMA operation is assumed to be two bus cycle.
I/O to memory or memory to I/O,' Two cycle DMA
consists of a fetch bus cycle from the source and a store
bus cycle to the destination. The data is stored in the
DMA controller's registers before being sent to the destination. Single cycle DMA transfers involve a simultaneous fetch from the source and store to the destination. As the most common method of I/O-memory
DMA operation, two cycle DMA transfers are the focus of this application note analysis. Equation 2 illustrates a calculation of the overall transfer rate between
the FIFO buffer and external Host for a maximum
FIFO size transfer. The equation does not account for
the latency of initiating the DMA transfer. '
Equation 2. Host FIFO DMA Transfer
Rate--:lnput or Output Channel

2

Cycle DMA Transfer-I/O (UPI-452) to System
Memory
FIFO channel size' (DMA READ/WRITE
FIFO time + DMA WRITE/READ Memory
Time)
128 bytes' (200 ns + 200 ns)
51.2 Jks
256 bus cycles'

The maximum DMA transfer rate is achieved by the
minimum DMA transfer cycle time to accomplish a
source to destination move. The minimum Host UPI452 FIFO DMA cycle time possible is determined by
the READ and WRITE pulse widths, UPI-452 command recovery times in relation to the DMA transfer
timing and DMA controller transfer mode used. Table
5 shows the relationship between the iAPX-286, iAPX186 and UPI-452 for various DMA as well as nonDMA byte by byte transfer modes versus processor frequencies.

NOTES:
'10 MHz iAPX 286, 200 ns bus cycles.

Host processor speed vs wait states required with UPI452 running at 16 MHz:
'

The UPI-452 design is optimized for high speed DMA
transfers between the Host and the FIFO buffer. The

10-346

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AP-281

UPI-452 internal FIFO buffer control logic provides
the necessary synchronization of the external Host
event and the internal CPU machine cycle during
UPI-452 RD/WR accesses. This internal synchronization is addressed by the TCC AC specification of the
UPI-452 shown in Figure 6. TCC is the time from the
leading or trailing edge of a UPI-452 RD/WR to the
same edge of the next UPI-452 RD/WR. The TCC
time is effectively another way of measuring the system
bus cycle time with reference to UPI-452 accesses.
In the iAPX-286 10 MHz system depicted in this application note the bus cycle time is 200 ns. Alternate cycle
accesses of the UPI-452 during two cycle DMA operation yields a TCC time of 400 ns which is more than the
TCC minimum time of 375 ns. Back to back Host
UPI-452 READ/WRITE accesses may require wait
states as shown in Table 5. The difference between 10
MHz iAPX-186 and 10 MHz iAPX 286 required wait
states is due to the number of clock cycles in the respective bus cycle timings. The four clocks in a 10 MHz
iAPX 186 bus cycle means a minimum TCC time of
400 ns versus 200 ns for a 10 MHz iAPX 286 with two
clock cycle zero wait state bus cycle.
DMA handshaking between the Host DMA controller
and the UPI-452 is supported by three pins on the UPI452; DRQIN/INTRQIN, DRQOUT/INTRQOUT
and DACK. The DRQIN/INTRQIN and DRQOUT/
INTRQOUT outputs are two multiplexed DMA or interrupt request pins. The function of these pins is controlled by MODE SFR bit 6 (MD6). DRQIN and
DRQOUT provide a direct interface to the Host system
DMA controller (see Figure 1). In response to a
DRQIN or DRQOUT request, the Host DMA controller initiates control of the system bus using HLD/
HLDA. The FIFO Input or Output channel transfer is
accomplished with a minimum of Host overhead and
system bus bandwidth.

The third handshake signal pin is DACK which is used
as a chip select during DMA data transfers. The UPI452 Host READ and WRITE input signals select the
respective Input and Output FIFO channel during
DMA transfers. The CS and address lines provide
DMA acknowledge for processors with onboard DMA
controllers which do not generate a DACK signal.
The iAPX 286 Block I/O Instructions provide an alternative to two cycle DMA data transfers with approximately the same data rate. The String Input and Output instructions (INS & OUTS) when combined with
the Repeat (REP) prefix, modifies INS and OUTS to
provide a means of transferring blocks of data between
I/O and Memory. The data transfer rate using REP
INS/OUTS instructions is calculated in the same way
as two cycle DMA transfer times. Each READ or
WRITE would be 200 ns in a 10 MHz iAPX 286 system. The maximum transfer rate possible is 2.5
MBytes/second. The Block I/O FIFO data transfer
calculation is the same as that shown in Equation 2 for
two cycle DMA data transfers including TCC timing
effects.

FIFO Data Structure and Host DMA
During a Host DMA write to the FIFO, if a DSC is to
be written, the DMA transfer is stopped, the DSC is
written and the DMA restarted. During a Host DMA
read from the FIFO, if a DSC is loaded into the I/O
Buffer Latch the DMA request, DRQOUT, will be deactivated (see Figure 2 above). The Host Status
(HSTAT) SFR Data Stream Command bit is set and
the INTRQ interrupt output goes active, if enabled.
The Host responds to the interrupt as described above.

1

cs#

1

, \ -_ _---J

, \ -_ _---J

I-I·----TCC----~'I
RD#/WR#

----J-\~

~

I
TRR/TWW \-4t
____T_R_V_~ TRR/TWW, ~
I

292018-6

Symbol

Description

Var.Osc.

@16MHz

TCC

Command Cycle
Time
Command Recovery
Time

6 * Tclcl

375 ns min

75

75 ns min

TRV

Figure 6. UPI-4S2 Command Cycle Timing

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AP-281

Once INTRQ is deactivated and the DSC·has been read
by the Host, the DMA request,DRQOUT, is reasserted by the UPI-452. The DMA request then remains
active until the transfer is complete or another DSC is
loaded into the I/O Buffer Latch.
An Immediate Command written by the internal CPU
during a Host riMA FIFO transfer also causes the
Host- Status flag and INTRQ to go active ifenabled. In
this case the Immediate Command would not terminate
the DMA transfer unless terminated by the Host. The
INTRQ line remains active until the Hostreads the
Host Status (HSTAT) SFR to determine the source of
the interrupt.
The net effect ora Data Stream Command (DSC) on
DMA data transfer rates is to add an additional factor
to the data transfer rate equation. This added factor is
shown in Equation 3. An Immediate Command has the
same effect on the data transfer rate if the Immediate
Command interrupt is recognized by the Host during a
DMA transfer. If the DMA transfer is completed before the Immediate Command interrupt is recognized,
the effect on the DMA transfer rate depends on whether the block being transmitted is larger than the FIFO
channel size. If the block is larger than the programmed FIFO channel size the transfer rate depends
on whether the Immediate Command flag or interrupt
is recognized between partial block transfers.
The FIFO configuration shown in Equation 3 is arbitrary since there is no way of predicting the size relative
to when a DSC would be loaded into the I/O Buffer
Latch. The Host DMA rate shown is for a UPI-452

(Memory Mapped or I/O) to 286 System Memory
transfer as described earlier. The equations do not account for the latency of intiating the DMA transfer.
Equation 3. Minimum host FIFO DMA Transfer
Rate Including Data Stream Command(s)
Minimum Host/FIFO DMA Transfer Rate wI DSC
FIFO size· Host DMA 2 cycle time transfer rate
+ iAPX 286 interrupt response time (Eq. # 1)
(32 bytes· (200 ns + 200ns)) + 2.3 p.s
15.1 p.s
75.5 bus cycles (@10 MHz iAPX286, 200ns
bus cycle)

UPI-4S2 INTERNAL DMA PROCESSORThe two identical internal DMA channels allow high
speed data transfers from one UPI-452 writable memory space to another. The following UPI-452 memory
spaces can be used with internal DMA channels:
Internal Data Memory (RAM)
External Data Memory (RAM)
Special Function Registers (SFR)
The FIFO can be accessed during internal DMA operations by specifying the FIFO IN (FIN) SFR as ti).e
DMA Source Address (SAR) or the FIFO OUT
(FOUT) SFR as the Destination Address (DAR). Table 6 lists the four types of internal DMA transfers and
their respective timings.

Table 6. UPI-452 Internal DMA Controller Cycle Timings
Source

Destination

Internal Data
Mem.orSFR
Internal Data
Mem.orSFR
External Data
Mem.
·External Data
Memory

Internal Data
Mem.orSFR
External Data
Mem.
Internal Data
Mem.orSFR
External Data
Memory

Machine
Cycles'·

@12MHz

@16MHz

1

1 p.s

750 ns

1

1 p.s

750 ns

1

1 p.s

750ns

2

2 p.s

1.5 p.s

. NOTES:

"External Data Memory DMA transfer applies to UPI-4S2 Local Bus only.
··MSC-S1 Machine cycle = 12 clock cycles (TCLCL).

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FIFO Data Structure and Internal DMA

INTERFACE LATENCY

The effect of Data Stream Commands and Immediate
Commands on the internal DMA transfers is essentially
the same as the effect on Host FIFO DMA transfers.
Recognition also depends upon the programmed DMA
Mode, the interrupts enabled, and their priorities. The
net internal effect is the same for each possible internal
case. The time required to respond to the Immediate or.
Data Stream Command is a function of the instruction
time required. This must be calculated by the user
based on the instruction cycle time given in the MSC51 Instruction Set description in the Intel Microcontroller Handbook.

The interface latency is the time required to accommodate all of the overhead associated with an individual
data transfer. Data transfer rates between the Host system and UPI-452 FIFO, with a block size less than or
equal to the programmed FIFO channel size, are calculated using the Host system DMA rate. (see Host
DMA description above). In this case, the entire block
could be transferred in one operation. The total latency
is the time required to accomplish the block DMA
transfer, the interrupt response or poll of the Host
Status SFR response time, and the time required to initate the Host DMA processor~

It is important to note that the internal DMA processor
modes and the internal FIFO logic work together to
automatically manage internal DMA transfers as data
moves into and out of the FIFO.· The two most appropriate internal DMA processor modes for the FIFO are
FIFO Demand Mode and FIFO Alternate Cycle Mode.
In FIFO Demand Mode, once the correct Slave Control and DMA Mode bits are set, the internal Input
FIFO channel DMA transfer occurs whenever the
Slave Control Input FIFO Request for Service flag is
set. The DMA transfer continues until the flag is
cleared or when the Input FIFO Read Pointer SFR
(IRPR) equals zero. If data continues to be entered by
the Host, the internal DMA continues until an internal
interrupt of higher priority, if enabled, interrupts the
DMA transfer, the internal DMA byte count reaches
zero or until the Input FIFO Read Pointer equals zero.
A complete description of interrupts and DMA Modes
can be found in the UPI-452 Data Sheet.

A DMA transfer between the Host and UPI-452 FIFO
with a block size greater than the programmed FIFO
channel size introduces additional overhead. This additional overhead is from three sources; first, is the time
to actually perform the DMA transfer. Second, the
overhead of initializing the DMA processor, third; the
handshaking between each FIFO block required to
transfer the entire data block. This could be time to
wait for the FIFO to be emptied and/or the interrupt
response time to restart the DMA transfer of the next
portion of the block. A fourth component may also be
the time required to respond to Underrun and Overrun
FIFO Errors.
Table 7 shows six typical FIFO Input/Output channel
sizes and the Host DMA transfers times for each. The
timings shown reflect a 10 MHz system bus two cycle
I/O tq Memory DMA transfer rate of 2.5 MBytes/second as shown in Equation 1. The times given would be
the same for iAPX 286 I/O block move instructions
REP INS and REP OUTS as described earlier..

DMAModes
Table 7_ Host DMA FIFO Data Transfer Times

The internal DMA processor has four modes of operation. Each DMA channel is software programmable to
operate in either Block Mode or Demand Mode. Demand Mode may be further programmed to operate in
Burst or Alternate Cycle Mode. Burst Mode causes the
internal processor to halt its execution and dedicate its
resources exclusively to the DMA transfer. Alternate
Cycle Mode causes DMA cycles and instruction cycles
to occur alternately. A detailed description of each
DMA Mode can be found in the UPI-452 Data Sheet.

FIFO Size:
Full or Empty
Time

32

43

64

85

96

128

I bytes

% % % % % Full or Empty
12.8 1i2 25.6 34.0 38.4 51.21 /Ls

Table 8 shows six typical FIFO Input/Output channel
sizes and the internal DMA processor data transfers
times for each. The timings shown are for a UPI-452
single cycle Burst Mode transfer at 16 MHz or 750 ns
per machine cycle in or out of the FIFO channels. The

10-349

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AP-281

machine cycle time is that of the MSC-51 CPU; 6
states, 2 XTAL2 clock cycles each or 12 clock cycles
per machine cycle. Details on the MSC-51 machine cycle timings and operation may be found in the Intel
Microcontroller Handbook.
Table 8. UPI-452 Internal DMA FIFO
Data Transfer Times
FIFO Size:
Full or Empty
Time

32

43

64

85

96

114 113 % % %

I

128 bytes
Full or Empty

24.0 32.3 48.0 64.6 72.0 96.0

I

/Ls

A larger than programmed FIFO channel size data
block internal DMA transfer requires internal arbitration. The UPI-452 provides a variety of features which
support arbitration between the two internal DMA
channels and the FIFO. An example is the internal
DMA processor FIFO Demand Mode described above.
FIFO Demand Mode DMA transfers occur continuously until the Slave Status Request for Service Flag is
deactivated. Demand Mode is especially useful for continuous data transfers requiring immediate attention.
FIFO Alternate Cycle Mode provides for interleaving
DMA transfers and instruction cycles to achieve a
maximum of software flexibility. Both iriternal DMA
channels can be used simultaneously to provide continuous transfer for both Input and Output FIFO channels.
Byte by byte transfers between the FIFO and internal
CPU timing is a function of the specific instruction cycle time. Of the 111 MCS-51 instructions, 64 require 12
clock cycles, 45 require 24 clock cycles and 2 require 48
clock cycles. Most instructions involving SFRs are 24
clock cycles except accumulator (for example, MOV
direct, A) or logical operations (ANL direct, A). Typical instruction imd their timings are shown in Table 9.
Oscillator Period:

@
@

12 MHz = 83.3 ns
16 MHz = 62.5 ns

MOV directt, A
MOV direct, direct

1 /Ls
2/Ls

Equation 4. Effective Internal FIFO
Transfer Time Using Internal DMA
Effective Internal FiFO Transfer Rate with DMA
FiFO channel size • Internal DMA Burst Mode
Single Cycle DMA Time
128 Bytes • 750 ns
96/Ls
Equation 5. Effective FIFO Transfer
Time Using Individual Instructions
Effective Internal FIFO Transfer Rate without DMA
FIFO channel size * Instruction Cycle Time +
Block size calculation Time
128 Bytes • (24 oscillator periods @ 16 MHz) +
20 instructions (24 oscillator period each .
@ 16MHz)
128 *1.5 /Ls + 300 /Ls
492/Ls
.

INTERFACE

OSCillator
@12MHz @16MHz
Periods
12
24

A typical effective internal FIFO channel transfer rate
using internal DMA is shown in Equation 4. Equation
5 shows the latency using byte by byte transfers with an
arbitrary factor added for internal CPU block size calculation. These two equations contrast the effective
transfer rates when using internal DMA versus individual instructions to transfer 128 bytes. The effective
transfer rate is approximately four times as fast using
DMA versus using individual instructions (96 /Ls with
DMA versus 492 /Ls non-DMA).

'FIFO DMA FREEZE MODE

Table 9. Typical Instruction Cycle Timings
Instruction

channel. As described above in the FIFO Data Structure section, the block size would have to be determined by reading the channel read and write pointer
and calculating the space available. Another alternative
uses the FIFO Overrun and Underrun Error flags to
manage the tr~sfers by accepting error flags. In either
case the instructions needed have a significant impact
on the internal FIFO data transfer rate latency equation.

750 ns
1.5/Ls

NOTE:
t Direct = a·bit internal datil locations address. This could
be an Internal Data RAM location (0-255) or a SFR Ii.e., II
port, control register, etc.]

o

Byte by byte FIFO data transfers introduce an additional overhead factor not found in internal DMA operations. This factor is the FIFO block size to be transferred; the number of empty locations in the Output
channel, or the number of bytes in the Input FIFO

FIFO DMA Freeze Mode provides a means of locking
the Host out of the FIFO Input and Output channels.
FIFO DMAFreeze Mode can be invoked for a variety
of reasons, for example, to reconfigure the UPI-452 Local Expansion Bus, or change the baud rate on the serial channel. The primary reason the FIFO DMA Freeze
Mode is provided is to ensure that the Host does not
read from or write to the FIFO while the FIFO interface is being altered. ONLY the internal CPU has the
capability of altering the FIFO Special Function Registers, and these SFRs can ONLY be altered during
FIFO DMA Freeze Mode. FIFO DMA Freeze Mode
inhibits Host access of the FIFO while the internal
CPU reconfigures the FIFO.

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Ap·281

FIFO DMA Freeze Mode should not be arbitrarily invoked while the UPI-452 is in normal operation. Because the external CPU runs asynchronously to the internal CPU, invoking freeze mode without first properly resolving the FIFO Host interface may have serious
consequences. Freeze Mode may be invoked only by
the internal CPU.
The internal CPU invokes Freeze Mode by setting bit 3
of the Slave Control SFR (SC3). This automatically
forces the Slave and Host Status SFR FIFO DMA
Freeze Mode to In Progress (SSTAT SST5 =. 0,
HSTAT SFR HSTl = 1). INTRQ goes active, if enabled by MODE SFR bit 4, whenever FIFO DMA
Freeze Mode is invoked to notify the Host. The Host
reads the Host Status SFR to determine the source of
the interrupt. INTRQ and the Slave and Host Status
FIFO DMA Freeze Mode bits are reset by the Host
READ of the Host Status SFR.
During FIFO DMA Freeze Mode the Host has access
to the Host Status and Control SFRs. All other Host
FIFO interface access is inhibited. Table 10 lists the
FIFO DMA Freeze Mode status of all slave bus interface Special Function Registers. The internal DMA
processor is disabled during FIFO DMA Freeze Mode
and the internal CPU has write access to all of the
FIFO control SFRs (Table 11).
If FIFO DMA Freeze Mode is invoked without stopping the host, only the last two bytes of data written
into or read from the FIFO will be valid. The timing
diagram for disabling the FIFO module to the external
Host interface is illustrated in Figure 7. Due to this
synchronization sequence, the UPI-452 might not go
into FIFO DMA Freeze Mode immediately after the
Slave Control SFR FIFO 7 DMA Freeze Mode bit
(SC3) is set = 0. A special bit in the Slave Status SFR
(SST5) is provided to indicate the status of the FIFO
DMA Freeze Mode. The FIFO DMA Freeze Mode

INTRQ OR
DRaIN/DRaoUT

operations described in this section are only valid after
SST5 is cleared.
Either. the Host or internal CPU can request FIFO
DMA Freeze Mode. The first step is to issue an Immediate Command indicating that FIFO DMA Freeze
Mode will be invoked. Upon receiving the Immediate
Command, the external CPU should complete servicing
all pending interrupts and DMA requests, then send an
Immediate Command back to the internal CPU acknowledging the FIFO DMA Freeze Mode request.
After issuing the first Immediate Command, the internal CPU should not perform any action on the FIFO
until FIFO DMA Freeze Mode is invoked. The handshaking is the same in reverse if the HOST CPU initiates FIFO DMA Freeze Mode.
After the slave bus interface is frozen, the internal CPU
can perform the operations listed below on the FIFO
Special Function Registers. These operations are allowed only during FIFO DMA Freeze Mode. Table 11
summarizes the characteristics of all the FIFO Special
Function Registers during Normal and FIFO DMA
Freeze Modes.
For FIFO
1. Changing the Channel Boundary
Pointer SFR.
Reconfiguration
2. Changing the Input and Output
Threshold SFR.
To Enhance the 3. Writing to the read and write
testability
pointers of the Input and Output
FIFO's.
4. Writing to and reading the Host
Control SFRs.
5. Controlling some bits of Host and
Slave Status SFRs.
6. Reading the Immediate Command
Out SFR and Writing to the 1m,
mediate Command in SFR.

..J

RD#/WR#

INTRa

J .......S.. ____ .. ____ ... _. __

::

:

A FIFO RD/WR AFTER

I

•

INTERFACE FREEZE IS

• -

INVOKED WILL CAUSE
HST3 OR HST7 TO BE SET

SC3

HSTl _ _ _ _ _ _ _ _ _ _ _ _ _ _..1 SET

292018-7

NOTE:
Timing Diagram of disabling of FIFO Module-External Host Interface.

Figure 7. Disabling FIFO to Host Slave Interface Timing Diagram

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AP-281

The sequence of events for invoking FIFO DMA
Freeze Mode are listed in Figure 8.

4. The Immediate Command interrupt is responded to
immediately-highest priority-by Host and internal CPU.

1. Immediate Command to request FIFO DMA
Freeze Mode (interrupt)

5. Respective interrupt response times
a. Host (Equation 3 above)=approximately 1.6 pos
b. Internal CPU is 86 oscillator periods or approximately 5.38 pos worst case.

2. Host/internal CPU interrupt response/service
3. Host/internal CPU clear/service all pending
interrupts and FIFO data

Event

4. Internal CPU sets Slave Control (SLCON)
FIFO DMA
Freeze Mode bit ,:: 0, FIFO DMA Freeze
Mode, Host Status SFR FIFO DMA Freeze
Mode Status bit = 1, INTRQ active (high)
5. Host READ Host Status SFR

Time

Immediate'Command from Host
to UPI-452 to request FIFO DMA Freeze Mode (iAPX286 WRITE)

0.30 pos

Internal CPU interrupt response/
service

5.38 pos

6. Internal CPU reconfigures FIFO SFRs

Internal CPU clears FIFO-128
bytes DMA

7. Internal CPU resets Slave Control (SLCON)
FIFO DMA

Internal CPU sets Slave Control
Freeze Mode bit

0.75 pos

Immediate Command to HostFreeze Mode in progress Host
Immediate Command interrupt
response

2.3 pos

Freeze Mode bit = 1, Normal Mode, Host
Status FIFO DMA Freeze Mode Status bit =

O.
8. Internal CPU issues Immediate Command to
Host indicating that FIFO DMA Freeze Mode is
complete
;

Internal CPU reconfigures FIFO
SFRs
Channel Boundary Pointer SFR
InputThreshold SFR
Output Threshold SFR

or
Host polls Host Status SFR FIFO DMA Freeze
Mode bit to determine end of reconfiguration

Internal CPU resets Slave
Control (SLCON) Freeze Mode
bit = 1, Normal Mode, and
automatically resets Host Status
FIFO DMA Freeze Mode bit

Figure 8. Sequence of Events to Invoke
FIFO DMAFreeze Mode

EXAMPLE CONFIGURATION

Internal CPU writes Immediate
Command Out

An example of the time required to reconfigure the
FIFO 180 degrees, for example from 128 bytes Input to
128 bytes Output, is shown in Figure 9. The example
approximates the time based on several assumptions;

Host Immediate Command
interrupt service -

1. The FIFO Input channel isfull-128 bytes of data

Total Minimum Time to
Reconfigure FIFO

96.00 pos

0.75 pos
0.75 pos
0.75 pos
2.3 pos

0.75 pos
2.3 pos
112.33 pos

Figure 9. Sequence of Events to Invoke FIFO
DMA Freeze Mode and Timings

2. Output FIFO channel is empty-1 byte
3. No Data Stream Commands in the FIFO.

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AP-281

Table 10. Slave Bus Interface Status During FIFO DMA Freezer Mode
. A2

Interface Pins;
A1
AO

DACK

CS

1
1
1
1

0
0
0
0

0
0
0
0

1
1
1
0

1

0

0

1

0

1

READ

WRITE

0
1
1
0

0
0
1
0

1
1
0
1

0

0

1

0

0

1

0

0

0

1

0

1

1

0

0
0

Operation In
Normal Mode

Status In
Freeze Mode

Read Host Status SFR

Operational

Read Host Control SFR

Operational

Write Host Control SFR

Disabled

Data or DMA data from
Output Channel

Disabled

0

Data or DMA data to
Input Channel

Disabled

0

1

Data Stream Command from
Output Channel

Disabled

1

1

0

Data Stream Command to
Input Channel

Disabled

0

0

0

1

Read Immediate Command
Out from Output Channel

Disabled

1

0

0

1

0

Write Immediate Command
In to Input Channel

Disabled

X

X

X

X

0

1

DMA Data from Output
Channel

Disabled

X

X

X

X

1

0

DMA Data to Input Channel

Disabled

NOTE:
X = don't care

Table 11. FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Normal
Operation
(SST5 = 1)

Label

Name

HCON
HSTAT
SLCON
SSTAT
IEP

Host Control
Host Status
Slave Control
Slave Status
Interrupt Enable
& Priority
Mode Register
Input FIFO Write Pointer
Input FIFO Read Pointer
Output FIFO Write Pointer
Output FIFO Read Pointer
Channel Boundary Pointer
Immediate Command In
Immediate Command Out
FIFO IN
COMMAND IN
FIFO OUT
COMMAND OUT
Input FIFO Threshold
Other FIFO Threshold

MODE
IWPR
IRPR
OWPR
ORPR
CBP
IMIN
IMONT
FIN
CIN
FOUT
COUT
ITHR
OTHR

10-353

Freeze Mode
Operation
(SST5 = 0)

Not Accessible
Read Only
Read & Write
Read Only

Read
Read
Read
Read

& Write
& Write
& Write
& Write

Read & Write
Read & Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read & Write
Read Only
Read Only
Read & Write
Read & Write
Read Only
Read Only

Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read

& Write
& Write
& Write
& Write
& Write
& Write
& Write
& Write
& Write
Only
Only
& Write
& Write
& Write
& Write

inter

ARTICLE
REPRINT

AR-409

October 1985

ORDER NUMBER: 270126-001

© INTEL CORPORATION, 1985
Reprinted from Design News, 8-19-85

270126-1

10-354

inter

AR·409

INCREASED FUNCTIONS
IN CHIP RESULt IN
LIGHTER,
LESS COSTLY PORTABLE
COMPUTER
Jafar Modares, Applications Engineer, Intel Corp., Chandler, AZ

Advances in technology have made it
possible to reduce the size and increase
the functionality and performance of
computers and computer peripherals.
With the help of microtechnology it is
possible to construct a computer terminal that is smaller and lighter than a
briefcase, and that can be connected to
a mainframe from almost anywhere.
As more portable computers are introduced to the marketplace, the demand
for lighter and even smaller systems at
a lower cost are inevitable. To meet this
demand changes in the architecture are
necessary.
With Intel's recently introduced
80C51 BH microcontroller several obstacles in the design of the portable computer have been overcome. The
80C51 BH is a single chip 8-bit microcontroller that requires a single 5V
power supply. It has 32 110 lines. Its
functionalities include excellent bit and
byte manipulation capability at
extremely high speeds as well as interfacing flexibilities through the serial and
parallel channels to intelligent and unintelligent devices. It can carry its own
program memory up to 4 Kbytes and has
various tools and support systems.
This article discusses the implementation of a prototype portable terminal
based on Intel's new 8OC51 BH microcontroller, and introduces the tools and
techniques available to build such a computer terminal. In the application discussed. the chip monitors the keyboard.

communicates with the host computer at
very high BAUD rates, and displays
information on the screen at slower rates
for human beings. The chip also monitors the power supply for switching to
the battery in case of power failure to
save valuable data and computer time.
The prototype is currently under futher
development at Intel's Microcontroller
Division.
Introducing the 80C51BH
Very new in the market, the 80CSI 8H
is a member of Intel's MCS-SI family.
The MCS-SI is a group of 8-bit microcontrollers that are extremely powerful
because of their 110 structure and their
bit manipulating capabilities. The
80C51 BH has 4 Kbytes of on-chip program memory with the capability to
address another 60 Kbytes of external
program memory. In addition it has 128
bytes of on-chip RAM and can access
64 Kbytes of external data memory.
Since the 80CSIBH is CMOS. it has
very low power consumption (IS mA at
5V. 12 MHz). In addition, it has two
power saving features not available in
HMOS versions of the family. These are
the Idle and Power Down modes.,which
are controlled by software and further
reduce power comsumption. These
power saving features make it ideal for
battery-operated backed-up systems.
Display device
The display device of this portable terminal'is a 25-line x 80-character Liquid
Crystal Display (LCD). It is capable of

displaying the same number of characters as a typical CRT, and it is not as
bulky or heavy as the latter.
LCDs can be divided into two large
categories: smart LCDs and dumb
LCDs. Those displays that have the
capability to receive a byte of ASCII and
translate it into a displayed character are
considered smart. On the other hand.
dumb displays are only a matrix of dots.
The former type has some kind of controller of its own plus a small memory
to hold the look-up table of characters
(character generator). When using a
dumb display the microcontroller has to
address and tum on the correct dots to
make a character. this means more 1/0
pins will be required. However, it gives
extra capabilities such as graphic displays and special or custom character
generation.
Both types of displays normally
accept data through an 8-bit bus.
Although the LCD is relatively slow. it
can still share the bus with a memory
device without any degradation of the
system performance.
Keyboard
Depending on their task arid purpose.
keyboards vary in shape. size. and the
number of keypads. The keyboard for a
computer terminal, as a minimum.
should have all the alphanumeric keys
(standard typewriter) plus a Control. an
Escape. and optionally. some Function
keys.
As the diagram in Figure I shows a
270126-2

10-355

inter
typical keyboard consists of a matrix of
eight scan lines and eight receive lines.
The scan lim,s are connecied to Port 0
of the microcontroller, and receive lines
are connected to Port I.' The software
writes Os to Port 0 to hold the scan lines
at a logic Low, and it writes I s to Port
I to hold the receive lines at a logic
High. Pressing one of the keys connects
a scan line to receive a line and pulls
that receive line Low .
. Besides being used for the scan lines,
Port 0 is also the bus for the data buffer
RAM and the display unit. While the
controller is talking to the RAM or to
the display, the bus must not be used.by
other devices or bus contention can

occur. Since the microcontoller initiates
the access to the display and to the data
buffer RAM, no conflict can occur
between them. However, if more than
one key on the same receive line is held
down simultaneously while the RAMor
the display is being accessed, it is possible to foul up the information being
transferred. Thus, to avoid bus ~onten­
tion, diodes 0 I through 08 are placed
on the scan lines, as shown in Figure I.
All the receive lines are ANOed to
External Interrupt I, so that pulling any'
of the receive lines Low will generate an
interrupt. The interrupt service routine,
adapts the "two key lock.out." system
and identities the pressed key. This system allows only one key to be pressed
simultaneously, all of them will be
ignored.
On some keyboards, certain keys
(such as Shift, Control or Escape) are
not a part of the line matrix. These keys
connect directly to a port pin on the
microcontroller. They would not cause
lock-out if pressed simultaneously with
a matrix key, nor generate an interrupt
if pressed singly. However, if they are
part of the miltrix, then the software has
to recognize those keys and take proper
action depending on the function of the
pressed key.
Normally, when a key is pressed, the
microcontroller is in the Idle mode and
no other task is in progress. Pressing a
key on the matrix generates an interrupt,
which terminates the Idle mode. The
interrupt service routine tirst calls a sub:
routine to provide a delay of approxi-

AR-409

Vee

RECEIVE LINES

I

SCAN
LINES.

H

l

~

CONTROL KEY

~

-~lr

TO P3.4
ANO P3.S

-I

PORT

(DAT~BUS)

>--~

TO THE EXTERNAL
INTERRUPT PIN

TO PORT 1

Figure 1

mately 25 msec (to debounce the·.key),
and to perform' the task of identifying
which key is down.
There are a number of ways that the
interrupt service routine can identify the
press key. One way is to utilize the bitaddressing capabilities of the 80C51 BH
to test each bit of the receive lines for a
zero, which generated the interrupt, and
records the bit position. Then write Os
to the receive lines, Is to the scan lines,
test the scan lines for a zero, and record
its position. If the controller finds more
than one zero on each port, it will discontinue any further processing and
return to the main program.
Once the bit positions that contain 0
are recorded, they are used as the address
for the characters in the look-up table.
The subroutine tinds the character that
corresponds to' the. pressed key. The
character is represented in ASCII code.
The look-up table is a list of the ASCII
representation of each keypad character,
and is stored in 'the program memory ..
The order in which they sit corresponds
to the address generated by the scan subroutine when that character is pressed on
the keyboard.

Serial communication
Once the 80C51 BH has' the ASCII
code generated from a key closure, it can
send it through its Serial' Channel to the
host computer. The serial port of the
microcontroller can be programmed for
all of the standard rates up to 375K. If

the terminal is to he connected directly
to the mainframe, a simple circuit translates the TTL levels to the RS232 level.
The circuit also eliminates the need for
the - 12V supply required for R02J2.
The circuit diagram is shown in Figure
2.
However, the primary application of
this terminal is to be the traveling person's window to the central system from
any remote location. In this application
a modem is needed. There are many
types of modems available. Some are on
PC boards for OEM use and others arc
ready to connect directly to the telephone
by the user. They also vary in size, petformance, and the way they communicate. A proper modem for the portable
terminal should be small enough to carry
in a briefcase and preferdbly be a lowpower device. When an ASCII code is
received by the host computer, it records
that code and echoes it back to the microcontroller which displays it on the LCD.
The serial port of the 80C51 BH can
generate interrupts every time il receives
or transmils information. The serial port
interrupt must have service priority over
the external interrupt generated by the
keyboard. The high priority enables the
serial port' to receive data any time the
computer addresses the terminal and
transmits data.
,The serial port interrupt service rou:
tine transfers the received data to the
display or to a memory buffer, depend270126-3

10-356

inter

AR-409

ficient for buffering large blocks of data
storage. The serial port interrupt service
routine takes the data from the SBUF
register and writes it to the iRAM. Two
index pointers in the serial port interrupt
service routine help keep track of the
incoming and outgoing iRAM data.
There are times the controller has to
wait for reasons such as the debounce
delay in the scan subroutine or when
writing to the display. and must slow
down. While the 80CSI BH is waiting.
it goes into the Idle mode until one of
the timers. which programmed to run.
times out and generates an interrupt. The
interrupt service routine for this type of
interrupt is a short one. it sets or clears
one or more flags and returns to continue
the task that was in progress before going
into the Idle mode.
The controller is also in the Idle mode
when there is no activity in the terminal.
i.e .• no data is being received or transmitted. and the keyboard is not being
used. Therefore. is is appropriate to say
that when power is applied to the terminal. the controller spends more than
90% of its time in the Idle mode.

MICROCONTROLLER
ing on the mode selected by a function
key. One mode of this function key teUs
the controller to move the received data
directly to the display. The other mode
stores pages of the information in the
buffer RAM. so that the user can edit or
display the data. one page a,t a time. on
the LCD without using the main system's CPU time.

Data buffer memory
The data buffer RAM is temporary'
storage for the information which is
either generated at the terminal or
retrieved from the central system. The
user can display portions of the stored
information or scroll through it. The user
can also alter the data on the terminal
and transmit it back to the computer in
a block form.
A suitable device for this purpose is
the SIC86 iRAM. This device is a
pseudo-static dynamic RAM that has a
built-in address latch. An internal highspeed arbitration circuit resolves any
potential conflict arising between read/
write arid internal refresh cycles.
This iRAM is 8K x 8-bit and is suf-

What is the Idle mode?
When Bit 0 in the Special Function
Register PCON is set. the CPU gates off

+SV

R1

+SV

SERIAL
OUTPUT

RS

02

Figure 2

its own internal clock and goes to sleep.
Since the CPU consumes about 90% of
the chip's power. this process saves a
significant amount of power. More
importantly the on chip peripherals and
the RAM continue their normal functions independently of the CPU. Since
the oscillator is still running. any enabled interrupt (internal or external) will
wake the CPU up from its sleep. and it
will start executing instructions from the
interrupt service routine.
A true portable terminal should be
capable of operating from a battery
source. There are occasions when one
would like to use the terminal at a location where an electric outlet is not readily
available. But the main purpose of the
battery supply is to save the data. which
has been entered and stored in the buffer
RAM. in the case of an unexpected
power failure.
While performing all of the previously
mentioned tasks. the gOCSI B H can
monitor its power supply: detect a power
loss in its earliest stages. and initiate a
power Down to save the data of the internal and external RAM.
One method for the 80CSI BH to monitor its power supply is to have the positive half-cycles of the power supply
transformer fed to the External Interrupt
o pin (Figure 3). In the level activated
mode. this pin generates an interrupt
every time there is a high to low transition. The interrupt service routine
reloads Timer 0 to a value.that will make
it overflow sometime between one and
two periods of the line frequency. As
long as the half cycles keep coming in.
the timer never overflows. because it is
reloaded every half a cycle. If there is a.
single half a cycle in which the line voltage does not reach a high enough level
to generate the interrupt. the timer rolls
over and generates a timer interrupt.
The interrupt service routine for
Timer 0 saves the critical data of some
of the internal registers and puts the controller into a Power down mode. A reset
button restarts the microcontroller to
resume operation when power is
restored.
In this mode the CPU and all of the
on-chip peripherals go to sleep. The
device stops its oscillator. freezes all the
270126-4

10·357

inter

AR·409

AC311

RECTIFIER
AND
REGULATOR

Rl

R2

Vee

Cl

.--It--+--l INT. 0

J

aoC51BH

Figure 3

activities and saves the information in its
internal RAM for as long as the supply
voltage can be reduced to as low· as 2
volts without running any risks of losing
the internal RAM information. Supply

current in this mode is normally 10 to
50 j.LA.
Bit I of the Special Function Register
PCON controls this mode. The instruction that puts the device in the Power

,

II
KEYBOARD

vi

80C51BH

Down mode is the last one executed. The
only way for the part to exit this mode
is with a hardware reset.
A prototype of this terminal was built
and connecled to a MDS 800 developement system. The terminal communicated with the host computer through the
serial channel at the rate of 2400 baud.
The 80C51 BH was emulated using
Intel's ICE-51 in circuit emulator. The
block diagram of the terminal is shown
in Figure 4.
.
The CHMOS controller and LCD
combination provides a system that
requires only a single voltage power supply, and consumes less than 200
mW. The system's low power consumption eliminates the need for complex, voltage-regulating hardware, and
cooling fans. The result is a lighter and
smaller computer terminal at a very low
0
cost.

vJ :::)
I'r

RAM

INT. 1
COMMUNICATION
LINE TO HOST
COMPUTER

I

MODEM

l

SERIAL CHANNEL

t
POWER FAILURE
DETECTOR

INT. 0

I

--)
.,.

DISPLAY

Figure 4

270126-5

10-358

li·I·I· IR,\NSt\t·/lo1\ ....

()~"

1:'>oIH SrRIAI. II.I·C!fW;\.IC\ Veil

II

\~

..... o -I. NOVI MBE·R

I'IH~

Using the 8051 Microcontroller with Resonant
Transducers
TOM WILLIAMSON

Abstract-Having to interface an analog Iransducer 10 a digilal conlrol
system Ihrough an analog-Io-digilal converter represents an expensive
bOllleneck in Ihe development of many systems. Some transducer
companies are addressing this prohlem by developing proprietar) families
of resonant transducers.
Resonant transducers are oscillators whose frequency depends in some
known wa)" on Ihe physical propl."rty being mrasured. The tledrical
output from these devices Is a train of rectangular pulses whose repelition
nte encodes the value of the measurand. Changes in the measurand cause
the frequ"ncy to shifl. The microcontroller detecls the frequency shift,
runs a uhdily check on iI. and cURve rio; it in software to the measurand
nlue.
This paper discusses software interfacing techniques between resonant
transducers and the 8051. Techniques for measuring frequency and
period are diS('ussed and compared for resolution and interrogation time.
The 80~1 is capable of performing these tasks in extremely short CPU
time. Requirements for obtaining n-bit resolution in the measurement are
discussed. It Is determined Ihat it is always faster 10 evaluate the
measurand 10 a jil;inn level of resolution by meMsurinjil; the period rather
than the frequency, even if the me-asurand is_ proportional to the
frequency rather than to th~ period. Numerical and softwar~ ~xamples are
prestnted to illustrate Ihe c·oncepls.

I. RESONANT TRANSDUCERS

M

OST sensing transducers are not directly compatible
with digital controllers. because they generate analog
signals. A few transducer companies are developing proprietary families of sensors which generate signals that are more
directly compatible with digital systems. These are not analog
sensors with built-in A-D conversion. but oscillators whose
frequency depends in some known way on the physical
propeny being measured.
The technology is applicable to vinually any type of
measurand: pressure. gas density. position. temperature.
force. etc. The sensor and microcontroller can operate from
the same supply voltage. so the sensor can in most cases
connect directly to a pon pin on the microcontroller.
The nominal reference frequency of the output signal from·
these devices is in the range of 20 Hz-500 kHz. depending on
the design. A change in the measurand away from the
reference condition causes the frequency to shili by an amount
that is related to the change in the Illeasurand value.
Transducers are available that have a full-scale frequency shift
of 2-1. The microcontroller detects the change in frequency or
period and ,'onvens it in soliware to the Illeasurand value.
II. CONNFl'IINl; IHE DI(;ITAL TRANSIlIIl'rR TO tHE 8051
Normally the transducer output can be connected directly to
one. of the 8051 pon pins. An exception would occur when the
Manu~l.:rip( n!l'eivcd Cktohc:r ~5, 1984.
The authur is with Intel Corporalion. Chandler. AZ 85224.

transducer signal docs not restrict itself to the voltage range of
-0.5 to +5.5 V.
The 8051 is not sensitive to the rise and fall times of its input
signals. It detects transitions by sampling its pon pins at fixed
intervals (once per machine cycle). and responds to a change
in the sequence of samples. If the slew rate of the transducer
signal is extremely slow. noise superimposed on the signal
could cause the sequence of samples to show false transitions.
There could on that account be situations in which the
transducer signal should be buffered through a Schmitt Trigger
to square it up.
III. TIMER/COUNTER STRUCTURE IN THE 8051

The 8051 has two 16-bit timer/counters: Timer 0 and Timer
I. Both can be configured in software to operate either as
timers or as event counters.
In the "timer" function. the register is automatically
incremented every machine cycle. Since a machine cycle in
the 805 I consists of 12 clock periods. the timer is being
incremented at a constant rate of 1/12 the clock frequency.
In the "counter" function. the register is incremented in
response to a I-to-O transition at its corresponding external
input pin (7U or TI). The way this function works is the
external input pin is sampled once each machine cycle (once
every 12 clock periods). and when the samples show a high in
one cycle and a low in the next. the count is incremented.
Note too that since it takes two machine cycles (24 clock
periods) to recognize a I-to-O transition. the maximum count
rate is 1124 the clock frequency. If the clock frequency is 12
MHz. the maximum count rate is 500 kHz. There are no
requirements on the duty cycle of the signal being counted.
The 8052. an enhanced version of the 8051 . has three 16-bit
timer/counters. two of which are identical to those in the 8051.
The third timer/counter can operate either as a 16-bit timer/
counter with automatic reload to a preset 16-bit value on
rollover. or as a 16-bit timer/counter with a "capture" mode.
In the capture mode a I-to-O transition at the T2EX pin causes
the current value in the counting register to the "captured"
into RAM. The third timer makes the 8052 panicularly easy to
interface with resonant transducers.
IV. WHETHER TO MEASURE FREQUENCY OR PERIOO
Measuring the frequency requires counting transducer
pulses for a lixed sample time. Measuring the period requires
measuring elapsed 'time for a fixed number of transducer
pulses. For a given level of accuracy in the determination of
the value of the measurand. it is usually faster to measure the
period. rather than the frequency. even if the measurand is

© 1985 IEEE
270434-1

10-359

intJ

8051 MICROCONTROLLER

WILLIAMSON' USING THE 8051 MICROCONTROLLER
proportional to frequency rather than period. However. both
types of measurements will be discussed here.
Two timer/counters can be used. one to mark time and the
other to count transducer pulses. If the frequency being
counted does not exceed 50 kHz or so. one may equally well
connect the transducer signal to an external interrupt pin. and
count transducer pulses in software. That frees one timer. with
very little cost in CPU time.
V. How TO MEASURE TRANSDUCER FREQUENCY
Measuring the frequency means counting transducer pulses
for some desired sample time. The count that is directly
obtained is T x F, where T is the sample time and F is the
frequency. The full scale range is T x. (Fmax - Fmin). For
n-bit resolution
I LSB = Tx (Fmax - Fmin) .

2"
Therefore. the sample time required for n-bit resolution is
T

2"
Fmax-Fmin

For example, 8-bit resolution in the measurement of a
frequency that varies between 5 and 10 kHz would require,
according to this formula, a sample time of 51.2 ms. The
maximum acceptable frequency count would be 51.2 ms x 10
kHz = 512 counts. The minimum would be 256 counts.
Subtracting 256 from each frequency count would allow the
frequency to be reported on a scale of 0 to FF in hex digits.
If Fmin and Fmax are closer together it takes more time to
resolve them. 8-bit resolution in the measurement of a
frequency that varies between 7 and 9 kHz would require a
sample time of 128 ms. The maximum and minimum
acceptable counts would be 1152 and 896. Subtracting 896
from each frequency count would allow the frequency to be
reported on a: scale of 0 to FF in hex digits.
To implement the measurement, one timer is used to
establish the sample time. In this function it autoincrements
every machine cycle. A machine cycle consists of 12 periods
of the clock oscill~tor. The sample time can be converted to
machine cycles by multiplying it by (Fxtal)/ I2, where Fxtal is
the 805 I clock frequency. The timer needs to be preset so that
it rolls over at the end of each sample time. Then it generates
all interrupt, and the interrupt routine reads and clears the
transducer pulse counter, and then reloads the timer with the
correct preset value.
The preset or reload value is the two's complement negative
of the sample time in machine cycles. For example, with a 12MHz clock frequency, the reload value required to establish a
5 I. 2 ms sample time is
(51.2 ms) x (12000 kHz)
12

-51200=3800 H.

In many cases the required sample time exceeds the capacity of
a 16-bit timer. For example, establishing a 128 ms sample
time with a 12-MHz clock frequency requires a 3-byte timer
with a reload of FEOCOOH. The 8051 timer, being only 2:

bytes wide. can be augmented in software in the timer
interrupt routine to three bytes. The 8051 has a DJNZ
instruction (decrement and jump if not zero) which makes it
easier to code the third timer byte to count down instead of up.
If the third timer byte counts down. its reload value is the
two's complement of what it would be for an up-counter. For
example. if the two's complement of the sample time is
FEOCOOH. then the reload value for the third timer byte would
be 02. instead of FE. The timer interrupt routine might then be
DJNZ THIRn.J'IMER..BYTE.OUT
MOV
TLO.IIO
MOV
THO.IIOCH
MOV
THIRn.J'IMER..BYTE.1I02
(Now read and clear the
transducer pulse counter.)
OUT: RETI
Interrupt latency will have no effect on the measurement if the
latency is the same for every sample time.
The trouble with measuring the frequency is it is not only
slow. but a waste of the resolving power of the 805 I's timers.
A timer with microsecond resolution is being used to mark off
100-ms time periods. The technique is nevertheless useful if
the timer is already serving other purposes (servicing a
display, perhaps), so that the sample time is coming relatively
free of charge. But in most cases it is faster and equally
accurate to measure the frequency by deriving it from a
measurement of the period.
VI. How TO MEASURE THE PERIOD
Measuring the period of the transducer signal means
measuring the total elapsed time over N-transducer pulses ..
The quantity that is directly measured is N x T, where T is
the period of the transducer sig~al in machine cycles. The
relationship between T in machine cycles and the transducer
frequency F in arbitrary frequency units is
Fxtal .

T=--pX(1/12)

where Fxtal is the 805 I clock frequency. in.the same unit as F.
The full scale range then is N x (Tmax - Tmin). For n-bit
resolution
I LSB=·

Nx (Tmax - Tmin)

2"

.

Therefore. the number of periods over which the elapsed time
should be measured is
N

2"
Tmax-Tmin

However. N must also be an integer. It is logical to evaluate
the above formula (do not forget that Tmax and Tmin have to
be in machine cycles) and select for N the next higher integer.
This selection gives a period measurement that has somewhat
more than n-bit resolution. which mayor may not be
acceptable. depending on the overall requirements of the
270434-2

10-360

intJ

8051 MICROCONTROLLER

IEEF. TRANSACTIONS 0'/ INDUSTRIAL ELECTRONICS. VOL. IE·l2. NO.4. NOVEMBER 19R5

system. It can be scaled back to n-bit resolution, if necessary,
by the following computation:
NT-NTmin

reported value = NTmax ~ NTmin
where NT is the elapsed time measured 'over N periods.
The computation can be done in math if a suitable divide
routine is available in the software. For 8-bit resolution it is
entirely reasonable to find the reported value in a look-up
table, which would take up somewhat more than one page in
ROM. In fact, the look-up table would contain NTmax NTmin entries.
For example, suppose we want 8-bit resolution in the
measurement of the period of a signal whose frequency varies
from 5 to 10 kHz. If the clock frequency is 12 MHz, then
Tmax is (12 000 kHz)I(12 x 5 kHz) = 200 machine cycles,
and Tmin is 100 machine cycles. The timer needs to be on then
for N = 2.56 periods, according to the formula. Using N = 3
periods will give maximum and minimum NT values of 600
and 300 machine cycles. This is somewhat more than 8-bit
resolution. It can be scaled to 8 bits with a 300-byte look-up
table, if desired.
To implement the measurement, one timer is used to
measure the elapsed time NT. Enabling its interrupt is
optional. The timer interrupt could be used to indicate a short
or open in the transducer circuit.
Then the transducer is connected to one of the external
interrupt pins (INTO or INTI), and this interrupt is configured'
to the transition-activated mode. In the transition-activated
mode every I-to-O transition in the transducer output will
generate an interrupt. The interrupt routine counts transducer
pulses, and when it gets to the predetermined N. it reads and
clears the timer. For example
DJNZ PULSES ,OUT
MOV
PULSES,fi..PERlODS
(Read and clear timer.)
OUT: RETI

VIII. DERIVING FREQUENCY FROM A PERIOD MEASUREMENT
We now consider the problem of measuring the transducer
frequency to n-bit resolution by deriving it from a direct
measurement of the period. The advantage of this technique is
speed. It is always faster to measure period than frequency.
But il is important 10 end up with a frequency value that has the
same resolution and accuracy as a directly measured frequency. Two questions need to be addressed.
I) To achieve n-bit resolution in the calculated frequency,

how much resolution is required in the period?
2) Having measured the period to the required resolution,
what is the most efficient way to calculate the frequency?
These questions will be addressed one at a time.
IX. RESOLUTION REQUIREMENTS
In general, n-bit resolution in the frequency derivation
requires somewhat more than n-bit resolution in the period
measurement. How much more? It will be demonstrated
presently that if the transducer frequency varies over a 2-to-1
range, the frequency can be calculated with n-bit resolution
from period measurements that have (n + I I-bit resolution.
The more practical form of the question is over how many
periods (N) must the transducer signal be sampled to' obtain
the required resolution in F? And so, we commence a
calculation of N.
The basic calculation of frequency from N x T (which we
shall call NT) is straightforward:
F=N/(NT).

If other interrupts are also to be enabled, the one connected to
the transducer should be set to Priority I, and the others to
Priority O. This is to control the interrupt response time. The
response time will not affect the measurement if it is the same
for every measurement. Variations in the response time will,
however, affect the measurement. Selling the pulse-counter
interrupt to Pnority I and all others to Priority 0 will minimize
variations in the response time. The response time will then be
limited to range from 3 to 8 machine cycles.

VII.

timer also generates an interrupt. The interrupt routine would
then read and reset the timer.
The advantage of this method is thaI the transducer signal
has direct access to the timer gate, with the result that
variations in the interrupt response time cease to be a fact"r
The timer can be read and cleared any time before the next
high in the transducer output.

PuLSEWIDTH MEASUREMENTS

The 80S I timers have an operating mode which is particularly suited' to pulsewidth measurements, and may be useful
here if the transducer has a fix~d duty cycle, or if the
transducer output is pulsewidth modulated instead of frequency modulated by the measurand.
. In this mode the timer is turned on by the on-chip circuitry
in response to an input high at the external interrupt pin, and
off by an input low. The external interrupt itself is enabled, so
the same I-to-O transition from the transducer that turns off the

The relationship between an increment dF in the calculated
frequency due to an increment d(NT) in the measured period
is, therefore,
N
dF= - - - d(NT)
.
(NT)2
F2

=-'N

d(NT).

This equation says the value of an LSB in the calculated
frequency is (F2)/ N x the value of an LSD in NT. Then tile
maximum value that an LSB in the calculated frequency can
have is (Fmax)1/N x the value of an LSB in NT. For the
calculated frequency to have n-bit resolution over the entire
range of frequencies, the value of its LSD must never exceed
(Fmax - Fmin)12". Therefore, the measurement requires
(Fmax)1
.
Fmax - Fmin
--N-X(I LSB in NT)s
2"
270434-3

10-361

8051 MICROCONTROLLER

WILLIAMSON, USING THE BOll MICROCONTROLLER

X. COMPUTING ·THE FREQUENCY FROM THE PERIOD
The periOd measurement leaves one with a 16-bit integer,
which is N x T (or NT) in machine cycles. The conversion to
frequency is straightforward:

The required resolution in NT is. therefore.
I LSD in NTs

Nx (Fmax - Fmin)

2" x (Fmax)

l

.

Now. to say that NTis measured with m-bit resolution means
I LSD in NT= NX(lIFmin-I/Fmax)

.

2m
Substituting. this value for I LSD into the .required resolution
and sol ving for 2m yields
Fmax
Fmm

2m~-.-x2".

F=N/(NT) periods/machine cycle.

The quantity of interest is probably not F, but a normalized
measure of the amount by which F exceeds .its. minimum
acceptable value. This quantity represents, through the transducer's transfer function, the "reported value" of the
measurand, and this quantity is an n-bit integer whose value
ranges from 0 (all bits = 0) to full scale (all bits. = I). This
normalized frequency is
F-Fmin

Then the requirement on m is

f= Fmax-Fmin

m ~ n + _I_n...:(Fi_m_a_x_/Fm_i....:n):....
In (2) .

=

Fmin
x(FIFmin-1\
Fmax-Fmin
.

It can be stated with some certainty. then. that if the transducer

frequency varies over a range of 2-to-I, the frequency can be
calculated with 8~bit resolution from a period measurement
that has 9-bit resolution. If the frequency variation is less than
2-to-I, another full bit of resolution in the period measurement
is not needed.
To obtain m-bit resolution in NT, N must satisfy
.2 m ,
N~ -T!=ma-x--"'"'"-=:Tm,.-:-inSubstituting for 2"', and using Tmax
IIF max, gives the result that

= IIFmin and Tmin =

N~ (Fmax)l. x 2".
Fmax-Fmin
It should be nOted that the units'· of frequency here are
periods/machine cycle, since the 80S I measures time by
counting machine cycles. The conversion factor between Hz
and periods/machine cycle is 12/(c1ock frequency). So the
requirement on N can also be written
.
N~

Fmax
Fmax
x--x 12x2"
Fmax - Fmin Fxtal

where Fxtal is the 80S I clock frequency in the same units as
Fmax and Fmin. This is the number of transducer pulses over
which the transducer signal must be sampled to achieve the
required solution in F.
For example, suppose that 8-bit resolution is required in F,
where Fmax = 10 kHz and Fmin = S kHz, and that Fxtal
= 12 MHz. Then the above calculation shows that N = 6
periods gives sufficient resolution in the periOd measurement
to satisfy the resolution requirement in F. Six periods will take
0.6-1.2 ms of sampling time, on that frequency range. Recall
that the sample time for a direct frequency measurement of the
same signal and to the same resolution was earlier calculated
to be SI.2 ma.
.

Using F = NI(NT) and F min = NI(NT max)
normalized frequency to be written

f

a1low~

the

.

Fmin' x NTmax - NT
Fmax - Fmin
NT

To get a handle on what kinds of numbers are involved here,
consider the situation where 8-bit resolution is required in f,
and in which Fxtal = 12 MHz, Fmax = 10 kHz, and Fmin
= S kHz. We have previously determined that for this set of
conditions, N = 6 periods gives sufficient resolution in the
period measurement to satisfy the resolution requirement in F
.(and inf)o With a 12 MHz clock frequency, Tmax in machine
cycles is (12 000 kHz)/(l2 x S kHz) = 200 machine cycles,
so NTrnax is 6 x 200 = 1200 machine cycles. The
calculation for f then becomes
f= 1200-NT.
NT

The minimum acceptable value that NT can have is (N x
7inin + I), where Tmin = (12000 kHz)/(12 x 10 kHz) =
100 machine cycles. Then N x Tmin ;" 6 x 100 = 600
machine cycles. The allowable values for NT are then 6011200 machine cycles, II total of 599 different values.
The fastest way to "calculate" f would be with a S99-byte
look-up table. This method has the added advantage that
nonlinearities in the transfer function between frequency and
measurand can be built into the table. Look-up tables are
facilitated in the 805 I by the MOVe A,@A+ PC, and Move
A,@A+DPTR instructions. DPTR is a 16-bit "data pointer"
register in the 80S I. Its two bytes can be individually
addressed as DPL (low byte) and DPH (high byte).
.
In the example under discussion, it will be necessary to load
DPTR with the address of the first byte of the look-up table,
less 601, plus ·the 2-byte value of NT. The software that
accesses the table might then take the following form:
'rABLE EQU (address of first table entry)
270434-4

10-362

inter

8051 MICROCONTROLLER

WHo I'RASS,\('fIOSS

os

INUl','iTRIAI. U.J:('TRONICS. VCJI. If:· 1.2. NO ~. ,~OVEMHf-:R I"'H~

c-IVI[)f. HDI)lINf:

·,,;mf"'dt.,.
'lo..ot I",nl
.,.'nUfTllnoit
I"

... tll.n

" .... '"l'r-t~."·

-,
If

oJ"

".nOlftlnator iol'"
dt'nOll'llnat.'Jr
Uu"t.fO"t 1\ c.f

" .."nfOrdtOI

;,.,

;'1"

•

Intll!'~.r •

th.

.. nil

flJrm

III.. mt'roltnr

numl!'rolt(1I
dpnomlflator
'" 0 thlll numpratC'r
2
pi '!.e numf'rotltor
"" 2

4 " " CJ

,; qn

'!'I~.

qn

...

1

nume-ratar
I

nutnf'ratol'"

•

dlo'nOmlnatol

lnrrpmt'nt n
~n~... t'llp

Fig. I.

MOV
ADD
MOV
MOV
ADDC
MOV
CLR
MOVC

A divide algurilhm.

A,NLOW(TABLE-601)
A,N'[J.O
DPL,A
A,NHIGH(TABLE-60I)
A,NUiI
DPH,A
A
A,@A+DPTR_

At this point the accumulator contains the 8-bit value of fIt is perfectly reasonable to decide that a 599-byte look-up
table is unwieldy. Its advantages are speed and built-in error
correction. But a reasonably fast divide algorithm can be
written to this specific purpose, making use of a priori
knowledge about the sizes of the numbers that are involved in
the computation. It helps to know that in this example the
numerator is never going to be larger than 599 and the
denominator is always greater than the numerator.
A complete discusSion of divide routines is beyond the
scope of this paper, but a suitable divide algorithm for this
specific application is shown in Fig. I. Reference [II calls this
the Restoring division algorithm. It is particularly well suite~
to the 8051, because" <" comparisons are greatly facilitated
by the 8051's CJNE (compare and jump if not equal)
instruction. CJNE A ,B,rel, executes a relative jump if A does
not equal B. More importantly to this application, the
instruction sets the carry flag if A < B.

XI.

Since the clock signal is normally generated by a crystal
oscillator, the oscillator accuracy normally far exceeds the
quantizing error inherent in the finite (n-bit) resolution.
As was previously mentioned, interrupt response time does
not introduce an error into the measurement itself, but
variations in the interrupt response time can. Interrupt
response time in the 8051 can vary from 3 to 8 machine cycles,
depending on what instruction is in progress at the time the
interrupt is generated. This would represeill an error of ± 5
counts in the measured value of NT during a period
measurement. An error of ± 5 counts in NT does not
necessarily. translate to ± 5 LSB's in the final result, but it
might still represent an error that exceeds the resolution.
In a direct frequency measurement variations in the interrupt response time would represent an error of ± 5 p.s in the
sample time.
If these kil.ds of errors are unacceptable there are ways to
deal with them. In period measurements, if the duty cycle of
the transducer is constant, the pulsewidth measurement
technique, previously described, can be used. Its advantage is
that it gates the timer off when the interrupt is generated,
rather .than when the interrupt is responded to.
In other cases one can simply increase the sample time
above the minimum required to obtain the desired resolution.
For example, if the measurement requires 8-bit resolution, one
can design the software for an II-bit resolution and truncate
the result to 8 bits.

ACCURACY AND RESOLUTION

The accuracy with which the 8051 will measure the
frequency or period of the transducer signal depends on two
things: the accuracy of the clock oscillator and variations in
the interrupt response time.

R~F~R~Nns

III

Davil' tl al.. 1);l{ilu/ S)'.'i/ems wilh Algorithm Implementation.
New Ynrk: Wiley. 19K.I.

270434-5

10-363

8051
SOFTWARE PACKAGES
• Choice of hosts:
PCDOS 3.0 based IBM* PC XT/AT*,
iRMX®06, iPDSTM System, Series II,
Series III, and Series IV
• Supports all members of the Intel
MCS® -51 architecture

• LlB51 Librarian which lets
programmers create and maintain
libraries of software object modules
0051 Software Development Package
Contains the following:

PL/M51 Software Package Contains the
following:

• 0051 Macro Assembler which gives
symbolic access to 0051 hardware
features

• PL/M51 Compiler which is designed to
support all phases of software
implementation

• RL51 Linker and Relocator program
which links modules generated by the
assembler

.RL5.1 Linker and Relocator,which
enables programmers to develop
software in a. modular fashion

• LlB51 Librarian which lets
programmers create and maintain
libraries of· software object modules

LEGEND

D
-----.
10'
I,, _____ 1I

o

INTEL DEVELOPMENT

TOOLS AHDOTMER
PRODUCTS
MCS"aS1

SOFTWARE TOOLS •

USEA-CODED
SOFTWARE

162771-1

Figure 1. MCS® -51 Program Development Process

·IBM and AT are registered trademarks of International Business Machine Corporation.

10-364

October 1987
Order Number: 162771-005

8051 Software Packages

PL/M 51 SOFTWARE PACKAGE

•

High-level programming language for
the Intel MCS® -51 single-chip
microcomputer family

•
•
•

Compatible with PL/M 80 assuring
MCS® -80/85 design portability

•

Enhanced to support boolean
processing
Tailored to provide an optimum.
balance among on-chip RAM usage,
code size and code execution time
Produces relocatable object code
which is linkable to object modules
generated by all other 8051 translators

•
•
•
•
• MCS®

Allows programmer to have complete
control of microcomputer resources
Extends high-level language
programming advantages to
microcontroller software development

Improved reliability, lower maintenance
costs, increased programmer
productivity and software portability

Includes the linking and relocating
utility and the library manager

Supports all members of the Intel
-51 architecture

PL/M 51 is a structured, high-level programming language for the Intel MCS-51 family of microcomputers. The
PL/M 51 language and compiler have been desi!'jned to support the unique software development requirements of the single-chip microcomputer environment. The PL/M language has been enhanced to support
Boolean processing and· efficient access to the microcomputer functions. New compiler controls allow the
programmer complete control over what microcomputer resources are u~ed by PLIM programs.
PLIM 51 is largely compatible with PL/M 80 and PLIM 86. A significant proportion of existing PLIM software
can be ported to the MCS-51 with modifications to support the MCS-51 architecture. Existing PLIM programmers can start programming for the MCS-51 with a small relearning effort.
PL/M 51 is the high-level alternative to assembly language programmi~g for the MCS-51. When code size and
code execution speed are not critical factors, ·PL/M 51 is the cost-effective approach to developing reliable,
maintainable software.
The PL/M 51 compiler has been designed to support efficiently all phases of software implementation with
features like a syntax checker, multiple levels of optimization, cross-reference generation and debug record
generation.
.
.
ICETM 5100, ICE 51, and EMV51 are available for on-target debugging ..
Software available for PC DOS 3.0 based IBM· PC XT/AT* Systems.

LI!GEND

o

USEA-CODED
SOFlWARE

162771-2

Figure 2: PL/M51 Software Package
10-365

intJ

8051 Software Packages

PL/M 51 COMPILER
FEATURES

Interrupt Handling

Major features of the Intel PLIM 51 compiler and
programming language include:

A procedure may be defined with the INTERRUPT
attribute. The compiler will generate code to save
and restore the processor status, for execution of
the user-defined interrupt handler routines.

Structured Programming
PL/M source code is developed in a series of rriodules, 'procedures, and blocks. Encouraging program
modularity in this manner makes programs more
readable, and easier to, maintain and debug. The
language becomes more flexible, by clearly defining
the scope of user variables (local to a private procedure, for example).

Compiler Controls
The PLIM 51 compiler offers controls that facilitate
such features as:
- Including additional PL/M 51 source files from
disk
- Cross-reference
-

Language Compatibility
PL/M 51 object modules are compatible with object
modules generated by all other MCS-51 'translators.
This means that PLIM programs may be linked to
programs written in any other MCS-51 language.

Corresponding assembly language code in the
listing file

Program Addressing Control

Object modules are compatible with In-Circuit Emulators and Emulation Vehicles for MCS-51 processors: the DEBUG compiler control provides these
tools with symbolic debugging capabilities. '

The PL/M 51 compiler takes full advantage of program addressing with the ROM (SMALL/MEDIUMI
LARGE) control. Programs with less than 2 KB code
space can use the SMALL or MEDIUM option to
generate optimum addressing instructions. Larger
programs can address over the full 64 KB range.

Supports Three Data Types

Code Optimization

PL/M makes use of three data types for various applications. These data types range from one to sixteen bits and facilitate various arithmetic, logic; and
address functions:
- Bit: a binary digit

The PL/M 51 compiler offers four levels of optimization for significantly reducing overall program size.
:..... Combination or "folding" of constant expressions; "Strength reductions" (a shift left rather
than multiply by 2)

-

Byte: 8-bit unsigned number or,

-

-

Word: 16-bit unsigned number.
-

Another powerful facility allows the use of BASED
variables that map !'(lore than one variable to the
same memory location. This is especially useful for
passing parameters, relative and absolute addressing, and memory allocation.

Two Data Structuring Facilities
PLIM 51 supports two data structuring facilities.
These add flexibility to the referencing of data stored
in large groups.
- Array: Indexed list of same type data elements
-

Structure: Named collection of same or different
type data elements

-

Combinations of Both: Arrays of. structures or
structures of arrays.

-

Machine code optimizations;. elimination of superfluous branches
Automatic overlaying of on-chip RAM variables
Register history: an off-chip variable will not be
reloaded if its value is available in a register.

Error Checking
The PLIM 51 compiler has a very powerful feature
to speed up compilations. If a syntax or program error is detected, the compiler will skip the codegeneration and optimization passes. This usually yields
a 2X performance increase for compilation of programs with errors.
A fully detailed set of programming and compilation
error messages is provided by the compiler and user's guide.

10-366

intJ

8051 Software Packages

BENEFITS

Lower Development Cost

PLIM 51 is designed to be an efficient, cost-effective solution to the special requirements of MCS-51
Microsystem Software Development, as illustrated
by the following benefits of PL/M use:

Increases in programmer productivity translate immediately into lower software development costs
because less programming resources are required
for a given programmed function.

Low Learning Effort

Increased Reliability

PLIM 51 is easy to learn and to use, even for the
novice programmer.

PLIM 51 is designed to aid in the development of
reliable software (PL/M programs are. simple statements of the program algorithm). This substantially
reduces the risk of costly correction of errors in systems that have already reached full production
status, as the more simply stated the program is, the
more likely it is to perform its intended function.

Earlier Project Completion
Critical projects are completed much earlier than
otherwise possible because PL/M 51, a structured
high-level language, increases programmer productivity.

Easier Enhancements and
Maintenance
Programs written in PL/M tend to be self-documenting, thus easier to read and understand. This means
it is easier to enhance and maintain PLIM programs
as the system capabilities expand and future prod.
ucts are developed.

RL51 LINKER AND RELOCATOR
•

Links modules generated by the
assembler and the PL/M compiler

•

Locates the linked object to absolute
memory locations·

•

Enables modular programming of
software-efficient program
development

•

Modular programs. are easy to
understand, maintainable and reliable

The MCS-51 linker and relocator (RL51) is a utility which enables MCS-51 programmers to develop software in
a modular fashion. The utility resolves all references between modules and assigns absolute memory locations to all the relocatable segments, combining relocatable partial segments with the same name.
With this utility, software can be developed more quickly because small functional modules are easier to
understand, design and test than large programs.
The total number of allowed symbols in user-developed software is very large because the assembler number
of symbols' limit applies only per module, not to the entire program. Therefore programs can be more readable
and better documented. RL51 can be invoked either manually or through a batch file for improved productivity.
Modules can be saved and used on different programs. Therefore the software investment of the customer is
.
maintained.
RL51 produces two files. The absolute object module file can be directly executed by the MCS-51 family. The
listing file shows the results of the Iink/\locate process.

10-367

inter

8051 Software Packages

LIB51 LIBRARIAN
The LlB51 utility enables MCS-51 programmers to
create and maintain libraries of software object modules. With this utility, the customer can develop standard software modules and place them in libraries,
which programs can access through a standard interface. When using object libraries, the linker will

call only object modules that are required to satisfy
external references.
.Consequently, the librarian enables the customer to
port and reuse software on different projects-thereby maintaining the customer's software investment.

ORDERING INFORMATION

Order Code

Operating Environment

D86PLM51

PL/M51 Software for PC DOS 3.0 Systems

R86PLM51

PL/M51 Software for iRMX 86 Systems

Documentation Package

SUPPORT:

PLIM 51 User's Guide

Hotline Telephone Support, Software Performance
Report (SPR), Software Updates, Technical Reports, and monthly Technical Newsletters are available.

MCS-51 Utilities User's GLiide

10-368

inter

.8051 Software Packages

8051 SOFTWARE DEVELOPMENT PACKAGE
•

Symbolic relocatable assembly
language programming for 8051
microcontrollers

•

Extends Intellec® Microcomputer
Development System to support 8051
program development

•

•

Encourage modular program design for
maintainability and reliability

•

Macro Assembler features conditional
assembly and macro capabilities

•

Supports all members of the Intel
MCS® 51 architecture

Produces Relocatable Object Code
which is linkable to other 8051 Object
Modules

The 8051 software development package provides development system support for the powerful 8051 family
of single chip microcomputers. The package contains a symbolic .macro assembler and relocation/linkage
utilities.
The assembler produces relocatable object modules from 8051 macro assembly language instructions. The
object code modules can be linked and located to absolute memory locations. This absolute object code may
be used to program the 8751 EPROM version of the chip. The assembler output may also be debugged using
the new family of ICE 5100 emulators or with the ICE-51TM in-circuit emulator.
The converter translates 8048 assembly language instructions into 8051 source instructions to provide software compatibility-between the two families of microcontroliers.
Software available for PC DOS 3.0 based IBM" PC XT/AT Systems.

162771-3

10-369

8051 Software Packages

8051·MACRO ASSEMBLER
•

Supports 8051 family program
development on Intellec®
,
Microcomputer Development Systems

•

Gives symbolic access to powerful
8051 hardware features

•

Produces object file, listing file and
error diagnostics

•

Object files are linkable and locatable

•

Provides software support for many
addressing and data allocation
capabilities

•

Symbolic Assembler supports' symbol
table, cross-reference, macro
capabilities, and conditional assembly

The 805.1 Macro Assembler (ASM51) translates symbolic 8051 macro assembly language modules into linkable and locatable object code modules. Assembly language mnemonics are easier to program and are more
readable than binary or hexadecimal machine instructions. By allowing the programmer to give symbolic
names to memory locations rather than absolute addresses, software design and debug are performed more
quickly and reliably. Furthermore, since modules are linkable and relocatable, the programmer can do his
software in modular fashion. This makes programs easy to understand, maintainable and reliable.
The assembler supports macro definitions and calls. This is a convenient way to program a frequently used
.
code sequence only once. The assembler also provides conditional assembly capabilities.
Cross referencing is provided in the symbol table listing, showing the user the lines in which each symbol was
defined and referenced.
ASM51 provides symbolic access to the many useful addressing features of the 8051 architecture. These
features include referencing for bit and byte locations, and for providing 4-bit operations for BCD arithmetic.
The assembler also provides symbolic access to hardware registers, 1/0 ports, control bits, and RAM addresses. ASM51 can support all memberS of the 8051 family.
Math routines are enhanced by the. MUltiply and DIVide instructions.
If an 8051 program contains errors, the assembler provides a comprehensive set of error diagnostics, which
are included in the assembly listing or on another file. Program testing may be performed by using the iUP
Universal Programmer and iUP F87/51 personality module to program the 8751 EPROM version of the chip.
ICE 5100, ICE51

a~d EMV51 are available for program debugging.

RL51 LINKER ANDRELOCATOR PROGRAM
•

Links modules generated by the
assembler

•

Locates the linked object to absolute
memory locations

•

Enables modular programming of
software for efficient program
development

•

Modular programs are easy to
understand, maintainable and reliable

The 8051 linker and relocator (RL51) is a utility which enables 8051 programmers to develop software in a
modular fashion. The linker resolves all references between modules and the relocator assigns absolute
memory locations to all the relocatable segments, combining relocatable partial segments with the same
name.
With this utility, software can be developed more quickly because small functional modules are easier to
understand, design and test than large programs.
The number of symbols in the software is very large because the assembler symbol limit applies only per
module not the entire program. Therefore programs can be more readable and better documented;
Modules can be saved and used on different programs. Therefore the software investment of ·the customer is
maintained.
10-370

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8051 Software Packages

RL51 produces two files. The absolute object module file can be directly executed by the 8051 family. The
listing file shows the results of the link/locate process.

LIB51 LIBRARIAN
The LlB51 utility enables MCS-51 programmers to create and maintain libraries of software object modules.
With this utility, the customer can develop standard software modules and place them in libraries, which
programs can access through a standard interface. When using object libraries, the linker will call only object
modules that are required to satisfy external references.
Consequently, the librarian enables the customer to port and reuse software on different projects-thereby
maintaining the customer's software investment.

ORDERING INFORMATION

Order Code

Operating Environment

D86ASM51

8051 Assembler for PCDOS 3.0 Systems

R86ASM51

8051 Assembler for iRMX 86 Systems

Documentation Package:

SUPPORT:

MeS-51 Macro Assembler User's Guide
MeS-51 Utilities User's Guide for 8080/8085
Based Development System

Hotline Telephone Support, Software Performance
Reporting (SPR), Software Updates, Technical Reports, Monthly Newsletter available.

MeS-51 8048-to-8051 Assembly Language Converter Operating Instructions for ISIS-II Users

10-371

inter
•
•
•

iDCX 51
DISTRIBUTED CONTROL EXECUTIVE

Supports MCS®-S1 and RUPITM-44 ,
Familes of 8-Bit Microcontrollers
.Real-Time, Multitasking Executive
- Supports up to 8 Tasks at Four
Priority Levels
Local and Remote Task Communication

•
•
•
•
•

Small-2.2K Bytes.
Reliable
Simple User Interface
Dynamic Reconflguration Capability
Compatible with BITBU5TM/Distributed
Control Modules (iDCM) Product Line

The iDCX 51 Executive is compact, easy to use software for development and implementation of applications
using the high performance 8-bit family of 8051 microcontrollers, including the 8051,8044, and 8052. Like the
8051 family, the iDCX 51 Executive is tuned for real-time control applications requiring manipulation and
scheduling of more than one task, and fast response to external stimuli.
The MCS-51 microcontroller family coupled with iDCX 51 is a natural combinati(;m for applications such as data
acquisition and monitoring, process control, robotics, and machine control. The iDCX 51 Executive can significantly reduce applications development time; particuladyBITBUS distributed control environments.
.
The iDCX 51 Executive is available in two forms, either as configurable software on diskette or as preconfigured firmware within the 8044 BEM BITBUS microcontroller.

280176-1

Figure 1. iDCX 51 Distributed Control Executive
·XENIXTM is a trademark of Microsoft Corporation.

10-372

October 1987
Order Number: 280176-003

inter

iDCX51

MICROCONTROLLER SUPPORT
The iDCX 51 Executive is designed to support the
MCS-51 and RUPI-44 families of 8-bit microcontrollers. MCS-51 microcontrollers that are supported include the 8051, 80C51 , 8052, 8031, 8032, and 8751
devices. The· RUPI"44 microcontrollers include the
8044, 8344, and 8744 devices. All of these microcontrollers share a common 8051 core.

ARCHITECTURE
Real-time and Multitasking

events: interrupts, timers, and messages ensuring
the application system always responds to the environment appropriately.

Task Management
A task is a program defined by the user to execute a
particular control function or functions. Multiple programs or tasks may be required to implement a particular function such as "controlling Heater 1". The
iDCX 51 Executive recognizes three different task
states as one of the mechanisms to accomplish
scheduling of up to eight tasks. Figure 2 illustrates
the different task states and their relationship to one
another.

Real-time control applications must be responsive to
the external environment and typically involve the
execution of more than one activity (task or set of
tasks) in response to different external stimuli. Control of an industrial drying process is an example.
This process could require monitoring of multiple
temperatures and humidity; control of fans, heaters,
and motors that must respond accordingly to a variety of inputs. The iDCX 51 Executive fully supports
applications requiring response to stimuli as they occur, i.e., in real-time. This real-time response is supported ·for inultiple tasks often needed to implement
a control application.

The scheduling of tasks is priority based. The user
can prioritize tasks to reflect their relative importance within the overall control scheme. For instance, if Heater 1 must go off line prior to Heater 2
then the task associated with Heater 1 shutdown
could be assigned a higher priority ensuring the correct shutdown sequence. The RQ WAIT system call
is also a scheduling tool. In this example the task
implementing Heater 2 shutdown could include an
instruction to wait for completion of the task that implements Heater 1 shutdown.

Some of the facilities precisely tailored for development and implementation of real-time control application systems provided by the iDCX 51 Executive
are: task management, interrupt handling, message
passing, and when integrated with communications
support, message passing with different microcontrollers. Also, the iDCX 51· Executive is driven by

The iDCX 51 Executive allows for PREEMPTION of
a task that is currently being executed. This means
that if some external elient occurs such as a catastrophic failure of Heater 1; a higher priority task associated with the interrupt, message, or timeout resulting from the failure will·preempt the running task.
Preemption ensures the emergency will be responded to immediately. This is crucial for real-time control
application systems.

I

Running Task Executes ROWAIT or RODELETE
READY/+1_--:::--:-'::-_--:--,-_-:-::-::---=--:--:-_ _-11 . RUNNING
Event Occurs Assoc. wi Asleep Task wi
.Higher Priority Than Running Task.

J

Event Occurs Assoc.
wlAsleepTask wi
Lower Priority
Than Running
Task

I

Event Occurs Assoc. wi Asleep Task wi
Higher Priority Than Running Task
ASLEEP

1
Running Task Executes ROWAIT

Figure 2. Task State Transition Diagram

10-373

280176-2

iDCX 51

Interrupt Handling

REMOTE TASK COMMUNICATION

The iDCX 51 Executive supports five interrupt
sources as shown in Table 1. Four of these interrupt
sources, excluding timer 0, can be assigned to a
task. When one of the interrupts occurs the task associated with it becomes a running task (if it were
the highest priority task in a ready state). In this way,
the iDCX 51 Executive responds to a number of internal and external stimuli including time intervals
desig'ned by the user.

The iDCX 51 Executive, system calls can support
communication to tasks on remote controllers. This
feature makes the iDCX 51 Executive ideal for applications using distributed architectures. Providing
communication support saves significant application
development time and allows for more effective use
of this time. Intel's iDCM product line combines
hardware and software to provide this function.
In an iDCM system, communication between nodes
occurs via the BITBUS microcontroller interconnect.
The BITBUS microcontroller interconnect is a high
performance serial control bus specifically intended
for use in applications built on distributed architectures. The iDCX 51 Executive provides BITBUS support.

Table 1.IDCX 51 Interrupt Sources
Interrupt Source

Interrupt Number

External Request 0

OOH

Timer 0

01H

External Request 1

02H

Timer 1

03H

Internal Serial Port 1

04H

BITBUSTM/iDCM COMPATIBLE

Message Passing
The iDCX 51 Executive allows tasks to interface with
one another via a simple message passing facility.
This message passing facility can be extended to
different processors when communications support
is integrated within a BITBUS/iDCM system, for example. This facility provides the user with the ability
to link different functions or tasks. Linkage between
tasks/functions is typically required to support development of complex control applications with multiple sensors (input variables) and drivers (output
variables). For instance, the industrial drying process
might require a dozen temperature inputs, six moisture readings,' and control of: three fans, two con~
veyor motors, a dryer motor, and a pneumatic conveyor. The data gathered from both the temperature
and humidity sensors could be processed. Two
tasks might be required to gather the data and process it. One task could perform a part of the analysis, then include a pointer to the next task to complete the next part of the analysis. The tasks could
continue to move between one another.

A pre-configured version of the iDCX 51 Executive
implements the BITBUS message format and provides all iDCX 51 facilities mentioned previously:
task management, interrupt handling, and message
passing. This version of the Executive is supplied in
firmware on the 8044 BEM with the iDCM hardware
products: the iSBXTM 344A BITBUS Controller MULTIMODULETM; the iDCX 344A BITBUS controller
board for the PC; and the iRCB boards.
DeSigners who want tO',use the iDCX executive on
an Intel BITBUS board should purchase either
DCS110 or DSC120 BITBUS software. Both of these
products include an interface library to iDCX 51 procedures and other development files. It is not necessary to purchase the iDCX 51 Executive.

, SIMPLE USER INTERFACE
The iDCX 51 Executive's capabilities are utlilized
through system calls. These interfaces have been
defined for ease of use and simplicity. Table 2 includes a listing of these calls and their functions.
Note that tasks may be created at system initialization or run-time using the CREATE TASK call.
Other Functions such as GET FUNCTION IDS, ALLOCATE/DEALLOCATE BUFFER, and SEND MESSAGE, support communication for distributed architectures.

10-374

intJ

iDCX 51

Table 2.IDCX 51 System Calls
Call Name

Description

TASK MANAGEMENT CALLS
RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS
RQ$GET$MEM

Get available system memory pool memory.

RQ$RELEASE$MEM

Release system memory pool memory.

INTERRUPT MANAGEMENT CALLS
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS
RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

Another feature that eases application -development
is automatic register bank allocation. The Executive
will assig'n tasks to register banks automatically unless a specific request is made. The iDCX 51 Executive keeps track of the register assignments allowing
the user to concentrate on other activities.

SYSTEM CONFIGURATION
The user configures an iDCX 51 system simply by
specifying the initial set of task descriptors and configuration values, and linking the system via the
RL 51 Linker and Locator Program with user programs.
Each task that will be running under control of the
executive has an Initial Task Description (ITO) that
describes it. The ITO specifies to the executive the
amount of stack space to reserve, the priority level
of the task (1-4), the internal memory register bank
to be associated with the task, the internal or external interrupt associated with the task, and a function
10 (assigned by the user) that uniquely labels the
task. The ITO can also include a pointer to the ITO
for the next task. In this wayan ITO "chain" can be
formed. For example, if four ITO's are chained to-

gether, then when the system is initialized, all four tasks will be put into a READY state. Then, the highest priority task will run.
The DCX 51 user cian control several system constants during the configuration process (Table 3).
Most of these constants are fixed, but by including
an Initial Data Descriptor (100) in an ITO chain, the
system clock priority, clock time unit, and buffer size
can be modified at run-time.
This feature is useful for products that use the same
software core, but need minor modification of the
executive to better match the end application. The
initial data descriptor also allows the designer, who
is using an 8044 BEM BITBUS Microcontroller, to
modify the preconfigured (on-chip) iDCX 51 Executive.
Programs may be written in ASM 51 or PL/M 51.
Intel's 8051 Software Development Package contains both ASM 51 and RL 51. Figure 3 shows the
software generation process.

10-375

inter

IDCX51

Table 3. DCX 51 Configuration Constants
Constant Name

Description

RO CLOCK PRIORITY

The priority level of the system clock.

RO CLOCK TICK

The number of time cycles in the system clock basic time unit (a "tick").

ROFIRSTITD

The absolute address of the first ITO in the ITO chain.

RO MEM POOL ADR

The start address of the System Memory Pool (SMP) in Internal Data RAM.

RO MEM POOL LEN

The length of the SMP.

RORAMIDD

The absolute RAM address of where iDCX 51 checks for an Initial Data
Descriptor (100) during initialization.

RO SYS BUF SIZE

The size, in bytes, of each buffer in the system buffer pool.

WRITE
SOURCE CODE

ASSEMBLE/
COMPILE

LlNK/
LOCATE

LOAD/EXECUTE

AEDIT
INSTALL EMULATOR

r-~---...., PROBE IN
ICETt.l5100 SERIES, MICROCONTROLLER
ICETt.t 44 ,ICE51,
SITE
EMV44,OR EMV51.1--.....,
EMULATORS

TARGET
BOARD
IUP-200A/201A
WITH
UNIVERSAL PROM \-----1I-H MCS® 51/
PROGRAMMER
INSTALL
RUPITII44
EPROM
. MICROIN CODE
CONTROLLER
SITE
INSTALL SRAM
IN CODE SITE

0""'"
D

FILE

SOFTWARE TOOL
280176-3

NOTE:
*RL 51 is included with ASM51 and PLIM 51; OBJHEX and the BITBUS Monitor are part of the DCS100 BITBUS
Toolbox.

Figure 3. Software Generation Process

10-376

inter

iDCX 51

SOPHISTICATED INTERNAL MEMORY
MANAGEMENT
.
The amount of internal memory available ranges
from 128 to 256 bytes depending on the type of microcontroller used.
Internal memory is used for the executive, stack
spare for "running" tasks, space for message buffers, and reserved memory for variables storage.
Other memory is used for register space. Except for
register space, the allocation of internal memory is
controlled by. the executive, user-specified task/data
descriptors and system configuration constants.
To optimize use of this limited resource, iOCX 51
provides dynamic (run-time) memory management.

INITIALIZATION AND DYNAMIC
MEMORY MANAGEMENT
At initialization (see Figure 4), the iOCX 51 Executive
creates the System Memory Pool (SMP) out of the
remaining initial free space (i.e. memory not used by
the iOCX 51 Executive or for register space). Next,
stack space is created for each of the initial tasks
that will be running on the system. If reserved memory is requested (using an 100), that memory is also
set aside. Finally, multiple buffers (size specified duringiOCX 51 configuration or using an 100) are allo-

cated from any remaining memory. These buffers
form the System Buffer Pool (SBP) that can be used
to create additional stack space or to . locate messages sent between tasks.
During run-time, the iOCX 51 Executive dynamically
manages this space. If a task is deleted, its stack
space is returned to the System Buffer Pool for use
by other tasks or as a message buffer.
As new tasks are dynamicallly created, the executive reserves the needed stack space. If no space is
available, the executive deallocates a buffer from
the System Buffer Pool and then allocates the needed stack space.
To send or receive a message, the executive allocates one or more buffers from the SBP for space to
locate the message, With iOCX 51, messages can
be optionally located in external (off-chip) memory.
The pre-configured executive in the 8044 BEM
BITBUS microcontroller, however, always locates
messages in internal memory.

RELIABLE
Real-time control applications require reliability. The
nucleus requires about 2.2K bytes of code space, 40
bytes on-chip RAM, and 218 bytes external RAM.

DCX 51 Initialization
Task 0
Task 1
Task 2

},

Task 3
Unallocated
Initial
Free
Memory
Space

I
SBP

I
I

4

STEPS:
1. Create system memory pool from the initial free memo
ory space.
2. Allocate stack space (space for 4 tasks shown).
3. Allocate user-reserved memory (per the 100).
4. Allocate equal-size buffers to form the system buffer
pool.

User
Memory

Figure 4. iDCX 51 Initialization of Internal Memory

10-377

intJ

iDCX 51

Streamlined code increases performance and reliability, and flexibility is not sacrificed as code may be
added to either on-chip or external memory.
The iDCX 51 architecture and simple user interface
further enhance reliability and lower cost. For example, the straightforward structure of the user interfaces, and the transparent nature of the scheduling
process contribute to reliability of the overall system
by minimizing programming effort. Also, modularity
increases reliability of the system and lowers cost by
allowing user tasks to be refined independent of the
system. In this way, errors are identified earlier and
can be easily corrected in each isolated module.
In addition, users can assign tasks a Function ·ID
that allows tracking of the tasks associated with a
particular control/monitorig function. This feature reduces maintenance and trouble shooting time thus
increasing system run time and decreasing cost.

OPERATING ENVIRONMENT
The iDCX 51 Executive supports applications development based on any member of the ,high performance 8051 family of microcontrollers. The Executive
is available on diskette with user linkable libraries or
in the 8044 BITBUS Enhanced Microcontroller preconfigured in on-chip ROM. (The 8044 BEM is an
8044 component that consists of an 8051 microcontroller and SDLC controller on one chip with integral
firmware.)
When in the iDCM environment (Figure 5), the preconfigured iDCX 51 Executive can communicate
with other BITBUS series controller boards. The
BITBUS board at the master node can be associated with either an iRMXTM, PC-DOS or XENIX· host
system.

DEVELOPMENT ENVIRONMENT
Intel provides a complete development environment
for the MCS-51 and RUPI-44 families of microcon"
trollers. The iDCX 51 Executive is only one of many
of the software development products available. The
executive is compatible with the following software
development utilities available from Intel:
• 8051 Macro Assembler (ASM 51)
• PLIM 51 Compiler
• RL.51 Linker and Relocator Program
• LIB 51
Intel hardware development tools currently available
for MCS-51 and RUPI-44 microcontroller development are:
• ICE-51 00/252 Emulator for the MCS-51 farrlilyof
microcontrollers
• ICE-5100/044 Emulator for the RUPI-44 family of
microcontrollers (8044, 8344, 8744)
• iUP-200A/201A PROM Programmer, 21X software, and iUP programming modules
The DCX 51 Executive is also compatible with older
hardware development tools (no longer available),
which include:
• EMV-51 144 Emulation Vehicles
.• ICE-51/44 In"Circuit Emulators
Table 4 shows the possible MGS-51 and RUPI-44
families development environments: host systems,
operating systems, available software utilities, and
hardware debug tools.

MASTER

REMOTE NODES
(SLAVES)

280176-4

Figure 5. IDeM Operating Environment

10-378

inter

iDCX51

SPECIFICATIONS

Reference Manual (Supplied)

Supported Microcontrollers

460367-001- iDCX 51 Distributes Control Executive User's Guide for Release 2.0.

8031
8051
8032
8744
8344

80C31
80C51
8751
8044
8052

ORDERING INFORMATION
Part Number

Executive for 8051 Family of Microcontrollers. Single User License, Development Only. Media Supplied for
All Host Systems (Table 3).

DCX51RF

Royalty (Incorporation) Fee for iDCX
Executive. Set of 50 incorporations.
IDCX 51 RF does not ship with software (Order DCX 51SU).

Compatible DCM BITBUSTM Software
DCS 100 BITBUS Toolbox Host Software Utilities

Description

DCX51SU

DCS 110 BITWARE DCM44 Code for BITBUS emulation

Table 4. MCS®-S1/RUPITM-44 Families Development Environments
Host Systems
Development Utilities
PC/MS-DOS

iRMX® 86

Intellec®

iPDSTM

Series II

Series III/IV

SOFTWARE
ASM 51
PL/M 51

+ Utilities(1)
+ Utilities(1)

iDCX 51 Executive

",.

",.

",.

",.

",.

",.

",.

",.

",.

",.

",.

",.

",.

",.

HARDWARE
ICE-51 00/044/252

",.

",.

iUP-200Al201 A

",.

",.

EMV-5H2). EMV-44(2)

",.

",.

ICE-51 (2), ICE-44(2)

",.

",.

iPDS

+ iUP-F87/44A PROM Programmer

",.

NOTES:

1. Utilities include RL 51, LIB 51, and AEDIT. Software for Series II systems is down-revision version.
2. These products are no longer available.

10-379

inter

ICETM-5100/252
In,;,Ch"cuit Emulator for the
MCS®-51 Family of Microc()ntrollers

•

Precise, Full-Speed, Real-Time
Emulation of Selected MCS-51
Microcontroller Components at Speeds
Up to and Including 16 MHz

•

Symbolic Debugging Enables Access to
Memory Locations and Program
Variables

•

64 KB of Mappable High-Speed
Emulation Memory

•

Four Address Breakpoints with InRange, Out-Of-Range, and Page Breaks

•

254 24-Bit Frames of Trace Memory (16
Bits Trace Program E,xecution
Addresses and 8 Bits Trace External
Events)
..

•

Serial Li'nk to the IBM* PC AT, PC XT
(and DOS Compatibles), and the
Intellec® Series III/IV '
"

Equipped with the Integrated Command
Directory (ICDTM) that Includes:
- On~Line Help,
.
..:... Syr1tax Guidance arid Checking
- Dynamic Command-Entry
- Error Checking
' - Command Recall

•

•

•

ASM-51 and PL/M-51 'Language
Support

On-Line Disassembler and Single-Line
Assembler to Help with Code Patching

•

Built-In CRT-Oriented Text Editor

I". '

The ICETM-5100i252 in-circuit emulator is a high-level, interactive debugging system that is used to develop
and test the hardware and software of a target system based on the MCS®-51 family of microcontrollers,The
ICE-51 00/252 emulator can be serially linked to an IBM PC AT or PC XT, or an Intellec Series III/IV. The
emulator can communicate with the host system at standard baud rates up to 19.2K. The design of 'the
emulator supports selected MCS-51 microcontroller components at speeds up to and including 16 MHz:

280200-1

·IBM is a registered trademark of International Business Machines Corporation.

10-380

November 1987
Order Number: 280200-002

inter

ICETM·5100/252 EMULATOR

PRODUCT OVERVIEW

System Integration

The ICE-5100/252 emulator provides full emulation
support for the MCS®-51 family members listed in
Table 1.
.

Integration of software and hardware can begin
when the emulator is plugged into the micro controller socket of the prototype system hardware. Hardware can be added, modified, and tested immediately. As each section of the user's hardware is completed, it can be added to the prototype. Thus, the
hardware and software can be system tested in realtime operation as each section becomes available.

The ICE-5100/252 emulator enables hardware and
software development to proceed simultaneously.
With the ICE-5100/252 emulator, prototype hardware can be added to the system as it is designed
and software can be developed prior to the completion of the hardware prototype. Software and hardware integration can occur while the product IS being
developed.
The· ICE-51 00/252 emulator assists four stages of
development:
• Software debugging
• Hardware debugging
• System integration

System Test
When the prototype is complete, it is tested with the
final version of the system software. The ICE-51001
252 emulator is then used for real-time emulation of
the microcontroller to debug the system as a completed unit.
The final product verification test can be performed
using the ROM or EPROM version of the microcontroller. Thus, the ICE-5100/252 emulator provides
the ability to debug a prototype or production system
at any stage in its development without introducing
extraneous hardware or software test tools.

• System test

Software Debugging
The ICE-5100/252 emulator can be operated without being connected to the target system or before
any of the user's hardware is available (provided external data RAM is not needed). In this stand-alone
mode, the ICE-5100/252 emulator can be used to
facilitate program development.

PHYSICAL DESCRIPTION
The ICE-5100/252 emulator consists of the following components (see Figure 1):
• Power supply
• AC and DC power cables

Hardware Debugging
.The ICE-5100/252 emulator'S AC/DC parametric
characteristics match the microcontroller's. The emulator's full-speed operation makes it a valuable tool
for debugging hardware, including time-critical serial
port, timer, and external interrupt interfaces.

• Controller pod
• Serial cable (host-specific)
• User probe assembly (consisting of the processor module and the user cable)
• Crystal power accessory (CPA)

Table 1. MCS®-51 Family Support Offered by the ICETM-5100/252 Emulator
Part

On-Chip Program Memory

On-Chip Data Memory

8031
80C31
8032
8051
80C51
8052
80C252
83C252
8751
87C51
8752
87C252

..
None
. None
None
4 KB-ROM
4KB-ROM
8KB-ROM
None
8 KB-ROM
4 KB-EPROM
4 KB-EPROM
8 KB-EPROM
8 KB-EPROM

128 bytes
128 bytes
256 bytes
128 bytes
128 bytes
256 bytes
256 bytes
256 bytes
128 bytes
128 bytes
256. bytes
256 bytes

10-381

ICETM·5100/252 EMULATOR

• 40-pin DIP target adaptor
• Clips assembly
• Software (includes the ICE-5100/252 emulator
software, diagnostic software, and tutorial)
The controller pod contains 64 K8 of emulation
memory, 254- by 24-bit frames of trace memory, and
the control processor. In addition, the controller pod
houses a 8NC connector that can be used to connect up to 10 multi-ICE compatible emulators together for synchronous starting and stopping of emulation.
The serial cable connects the host system to the
controller pod. The serial cable supports a subset of
the RS-232C signals.
The user probe assembly consists of a user cable
and a processor module. The processor module
houses the emulation processor and the interface
logic. The target adaptor connects to the processor
module and provides an electrical and mechanical
interface to the target microcontroller socket.
The crystal power accessory (CPA) is a small detachable board that connects to the controller pod
and enables the ICE-5100/252 emulator to run in

stand-alone mode. The target adaptor plugs into the
socket on the CPA; the CPA then supplies clock and
power to the user probe.
The clips assembly enables the user to trace external events. Eight bits of data are gathered on the
rising edge of. PSEN during opcode fetches. The
clips information can be displayed using the CLIPS
option with the PRINT command. Trace qualification
input and output lines are also provided on the clips
pod for connection to test equipment.
The ICE-51 00/252 emulator software supports mnemonics, object file formats, and symbolic references
generated by Intel's ASM-51 and PL/M-51 programming languages. Along with the ICE-5100/252 emulator software is a customer confidence test disk
with diagnostic routines that check the operation of
the hardware.
The on~line tutorial is written in the ICE-5100 command language. Thus, the user is ,able to interact
with and use the ICE-51 00/252 emulator while executing the tutorial.
A comprehensive set of documentation is included
with the ICE-51 00/252 emulator.

';,.,,"f

280200-2

Figure 1. The ICETM-5100/252 System Hardware

10-382

inter

ICETM·5100/252 EMULATOR

ICETM·5100/252 EMULATOR
FEATURES

ICE-5100/252 emulator commands that access
memory use one of the special prefixes (e.g., CODE)
to specify the memory space.

The ICE-51 00/252 emulator has been created to assist a product designer in developing,' debugging,
and testing designs incorporating the MCS®-51 family of microcontrollers. The following sections detail
some of the ICE-5100/252 emulator features.

The microcontroller's special function registers and
register bits can be accessed mnemonically (e.g.,
DPL, TCON, CY) with the ICE-5100/252 emulator
software.

Processor Selection
The ICE-51 00/252 emulator emulates the microcontrollers listed in Table 1. Selecting a processor type
changes the following characteristics to match the
microcontroller selected:
• Internal RAM size

Data can be displayed or modified in one of three
bases: hexadecimal, decimal, and binary. Data can
also be displayed or modified in one of two formats:
ASCII and unsigned integer. Program code can be
disassembled and displayed as ASM-51 assembler mnemonics. Code can be modified with standard ASM-51 statements using the built-in singleline assembler.

• Internal ROM size
• Idle and power down mode enable
• Special function register symbolic map

Symbolic references can be used to specify memory
locations. A symbolic reference is a procedure
name, line number, program variable, or label in the
user program that corresponds to a location.

• Memory map
• Latched or unlatched EA
• Serial port framing and error detection

Some typical symbolic functions include:
• Changing or inspecting the value of a program
variable by using the symbolic name to access
the memory location.

Emulation
Emulation is the controlled execution of the user's
software in the target hardware or in an artificial
hardware environment that duplicates the microcontroller of the target system. Emulation is a transparent process that happens in real-time. The execution
of the user software is facilitated with the ICE-51001
252 command language.

Memory Mapping
There is 64 KB of memory that can be _mapped to
the CODE memory space in 4 KB blocks on 4 KB
boundaries. By mapping memory to the ICE-51001
252 emulator, software development can proceed
before the user hardware is available.

, Memory Examination and Modification
The memory space. for the MCS®-51 component(s)
and its target hardware is fully accessible through
the emulator. The ICE-5100/252 emulator refers to
four physically distinct memory spaces, as follows:
• CODE -

references program memory

• IDATA -

references internal data memory

• RDATA -

references special function register
memory

• XDATA -

references external data memory

• Defining break and trace events using symbolic
references.
.
• Referencing variables as primitive data types.
The primitive data types are ADDRESS, BIT.
BOOLEAN, BYTE, CHAR (character), and
WORD.
The ICE-51 00/252 emulator maintains a virtual symbol table (VST) for program symbols. A maximum of
61 KB of host memory space is available for the
VST. If the VST is larger than 61 KB, the excess is
stored on available host system disk space and is
paged in and out as needed. The size of the VST is
limited only by the disk capacity of the host system.

Breakpoint Specifications
Breakpoints are used to halt a user program in order
to examine the effect of the program's execution on
the target system. The ICE-5100/252 emulator supports three different types of break specifications:
• Specific address break - A single address can
be specified to halt emulation.

10-383

inter

ICETM~5100/252

• Range break - An arbitrary range of addresses
can be specified to halt emulation. Program execution within or, optionally, outside the range
halts emulation.
• Page break - Up to 256 page breaks· can be
specified. A page break is defined as a range of
addresses that is 256-bytes long and begins on a
256-byte address boundary.
Break registers are IJs~r-defined debug definitions
used to create and store breakpoint definitions.
Break registers can contain multiple breakpoint definitions and can optionally call debug procedures
when emulation halts.

Trace Specifications
Tracing can be triggered using specifications similar
to those used for breaking. Normally, the ICE-51 001
252 emulator traces program activity while the user
program .is .executing. With a trace specification,
tracing can be triggered to occur only when specific
conditions are met during execution. Up to 254
24-bit frames of trace information are collected in
the buffer during emulation. Sixteen of the 24 bits
trace instruction execution addresses, and 8 bits
capture external events (CLIPS).
The trace buffer display is similar to an ASM-51 program listing shown in Figure 2. The PRINT command
enables the user to selectively display the contents
of the trace buffer. The user has the option of displaying the clips information as well as disassembled instructions.

hlt>PRINT NEWEST 4

EMULATOR

Procedures
Debugging procedures (PROCs) are a user-named
group of ICE-51 00/252 emulator commands that are
executed as one command. PROCs enable the user
to define several commands in a named block structure. The commands are executed by entering the
name of thePROC. The PROC bodies are a simple
DO... END construct.
PROCs can simulate missing hardware or software,
collect debug information, and execute high-level
software patches. PROCs can be copied to text files
on disk, then recalled for use in later test sessions.
PROCs can also serve as program diagnostics, implementing ICE-5100/252 emulator commands or
user-defined definitions for special purposes.
PROCs can also be used to set breakpoints.

On-Line Syntax Menu
A special menu, called the Integrated Command Directory (ICD), similar to the one used for the 121CETM
system and the VLSiCE-96 emulator, aids in creating
syntactically correct command lines. Figure 3 shows
an example of the ICD and how it changes to reflect
the options available for the GO command.

Help
The HELP command provides ICE-51 00/252 emulation command assistance via the host system terminal. On-line HELP is available for the ICE-5100/252
emulator commands shown in Figure 4.

1* Print newest four instructions in
buffer *1
.

INSTRUCTION
FRAME
ADDRESS CODE
(028)
C02A
PUSH 2AH
300A
2532
ADD· A,32H
(03i:J)
300C
(032)
F52A
MOV
2AH,A
300E
853210
CJNE
A,32H,$+10H
(034)
3010
hIt>
hI t>PRINT CLIPS OLDEST 2 1* Buffer display showing clips *1
FRAME
ADDRESS CODE
INSTRUCTION
CLIPS (76543210)
(ODD)
300A
C02A
PUSH 2AH
01110011
300C
2532
ADD
A,32H
11110101
(001)
hIt>
280200-3

Figure 2. Selected Trace Buffer Displays

10-384

intJ

ICETM·5100/252 EMULATOR

Allow at least 1-% inches (3.8 cm) of space to fit the
processor module and target adaptor. Figure 5
shows the dimensions of the processor module.

Design Considerations
The height of the processor module and the target
adaptor need to be considered for target systems.

hI t> GO
FROM ARM

l

FOREVER

TIL

USING

TRACE



hIt> GOFROM


)

---------~
hI t> GO FROM J.3H
 ARM FOREVER

l
l
l

TIL USING

TRACE



hI t> GO FROM J.3H USING
BRKREG 

)

---------~
hI t> GO FROM J.3H USING brl.
~ TRACE
~
< execute>

)

--------~~
hlt> GO FROM J.3H USING brl. TRACE traceit
~


)

---------~
280200-4

Figure 3. The Integrated Command Directory for the GO Command

hlt>HELP
HELP is available for:
ADDRESS
BRKREG
CONSTRUCTS
DCI
DYNASCOPE
GO
KEYS
LSTEP
MTYPE
PROC
REPEAT
SYNCSTART
VERSION
hlt>

APPEND
BYTE
COUNT
DEBUG
EDIT
HELP
LABEL
MAP
NAMESCOPE
PSEUDO_VAR
RESET
TEMPCHECK
WAIT·

ASM
CHAR
CPU
DEFINE
ERROR
IF
LINES
MENU
OPERATOR
PUT
RETURN
TRCREG
WORD

BASE
CI
CURHOME
DIR
EVAL
INCLUDE
LIST
MODIFY
PAGING
REFERENCE
SAVE
TYPES
WRITE

BIT
CNTL_C
CURX
DISPLAY.
EXIT
INVOCATION
LITERALLY
MODULE
PARTITION
REGS
STRING
VARIABLE

BOOLEAN
COMMENTS
CURY
DO
EXPRESSION
ISTEP
LOAD
MSPACE
PRINT
REMOVE
SYMBOLIC
VERIFY

280200-5

Figure 4. HELP Menu

10-385

inter

ICETM·5100/252 EMULATOR

PROCESSOR MODULE~
TOP VIEW

n

H

A

~~ZT

0"

~~:iI
~
gx;

~f ~

--1

m~~ I"~i

.r~. .

.~.&:il!;
0
~.G'I. Z

CABLE BODY
39"
(99 em)

I

PIN 1

.

I
SIDE VIEW

~;.'

4"

(10.2 em)

3 13ft."

(9.7 em)

----I

..,.,

PROCESSOR MODULE
".

~u51X.
~

TARGET
ADAPTOR

~.

280200-6

Figure 5. Processor Module Dimensions

ELECTRICAL CONSIDERATIONS
The emulation processor's user-pin timings and loadings are identical to the 80C252 component except as
follows.
Maximum Operating ICC and Idle ICC (ma)'
Maximum Operating ICC (ma)'

Vee

4V

5V

0.5 MHz

0.87

1.62

Maximum Idle ICC (ma)'

6V

4V

5V

6V

0.58

1.21

2.5

Frequency
3.0

3.5 MHz

4.8

8.0 MHz

10.5

15.0

6.82

20.5

9.76

2.2

4.97

6.33

6.0

8.98-

11.76

12.0 MHz

15.2

22.2

30.2

9.2

13.34

17.46

16.0 MHz

19.4

28.6

38.7

11.8

17.4

23.4

• ICC is measured with all output pins disconnected.
XTAL 1 driven with TCLCH, TCHCL= 10ns,Vn=Vss + .5V, Vih=Vcc-.5V. XTAL2 not connected.
.
For maximum operating ICC
EA = RST = PortO = Vcc.
For maximum idle ICC
• EA=PortO=Vcc;RST=Vcc, internal clock to PCA gated off .

• Up to 25 pf of additional pin capacitance is contributed by the processor module and target
adaptor assemblies.

• Pins 18 and 19, XTAL1 and XTAL2, respectively,
have approximately 15 to 16 pf of additional capacitance when configured for crystal operation.

• Pin 31, EA, has approximately 32 pf of additional
capacitance loading due to sensing circuitry.

10-386

infef

ICETM·5100/252 EMULATOR

Table 2. CHMOS and HMOS Design Differences
Chip Function
RST trigger threshold
RST input impedance
Port Iii
Clock threshold

HMOS Component 8031

CHMOS Component 80C31

2.5V
4K - 10K ohms

70% Vcc (3.5V @ Vcc
50K - 150K ohms

-800/LA

-50/LA

2.5V

70% Vcc (3.5V

The ICE-5100/252 emulator is based on a CHMOS
emulation processor. There are minor differences
between how the ICE-5100/252 emulator supports
CHMOS and HMOS designs as shown in Table 2.
Refer to the Microcontrol/er Handbook, order number 210918, for further information on CHMOS and
HMOS design considerations.

HOST REQUIREMENTS
• IBM PC AT or PC XT (or PC-DOS compatible)
with 512 KB of RAM and a hard disk running under the DOS 3.0 (or later) operating system.

64 KB

Mappable to user or
ICE-51 00/252
emulator memory in
4 KB blocks on
4 KB boundaries.

Trace Buffer

254- by 24- bit frames

Virtual Symbol
Table

A maximum of 61
KB of host memory
space is available
for the Virtual Symbol Table (VST).
The rest of the
VST resides on
disk anct is paged
in and out as needed.

Disk drives - Dual floppy or one hard disk and
one floppy drive required.

• ICE-5100/252 tutorial softy,lare

= 5V)

Memory
Mappable fullspeed emulation
code memory

• Intellec Series III/IV Microcomputer Development
System running under the ISIS or iNDX operating
system respectively, with at least 512 KB of application memory resident.

• ICE-51 00/252 emulator software
• ICE-51 00/252 confidence tests

Vcc

EMULATOR PERFORMANCE

Emulating HMOS Components

ICETM·5100/252 SYSTEM SOFTWARE
PACKAGE

@

= 5V)

PHYSICAL CHARACTERISTICS
Controller Pod
Width
Height
Depth
Weight

8%" (21 cm)
1%" (3.8cm)
13%" (34.3 cm)
4 Ibs (1.85 kg)

User Cable
The user cable is 3 feet (approximately 1 m).

Processor Module
(with the target adaptor attached)
Width
Length
Height

10-387

310/,6" (9.7 cm)
1%" (3.8 cm)
1%" (3.8 cm)

inter

ICETM·5100/252 EMULATOR

pl252KITAs

Power Supply
Width
Height
Depth
Weight

7%"(18.1 cm)
4" (10.06 CITl) .
11" (27.97 cm)
151bs (6.1 kg)

Serial Cable
The serial cable is 12 feet (3.6m).

pl252KITs

ELECTRICAL CHARACTERISTICS

This· kit contains the ICE-51 00/252
user probe assembly~ power supply
and cables, serial cables, target
adaptor, CPA, ICE-5100 controller
pod, software, and documentation for
use with Intel hosts (Series III, IV).
The kit also includes the 8051 Software Development Package and the
AEDIT text editor for use on Series
III/IV. [Requires software license.)
. 'This . kit is the same 'as the
pl252KITAs kit excluding the 8051
Software Development Package and
the AEDIT text edito~. [Requires. software license.)

Power Supply
Software Only

100 - 120V or 200 - 240V (selectable)
50-60Hz
2 amps (AC max) @ 120V
1 amp (AC max) @ 240V

ENVIRONMENTAL
CHARACTERISTICS
Operating temperature
Operating humidity

+ 10° C to + 40°C (50°F to
104°F)
Maximum of 85% relative
humidity, non-condensing

Order Code Description
psA252D
This kit contains the host, probe, diagnostic and tutorial software on
51.4" disks for use on an IBM PC'AT
or PC XT (requires DOS 3.0 or later).
,[Requires software license.)
psA252s
This kit· contains the host, probe, di'. agnostic and tutorial software on 8"
: disks (both single"density and doubledensity) for use on a Series III., and on
51.4" disks for use· on a Series W.
[Requires software license.)

ORDERING INFORMATIO~

Other Useful Intel Debug and
Development SupportPro~ucts

Emulator Hardware and Software

Order Code 'Descrlptlon .

Order Code Description
pl252KITAD This kit contains: ICE-5100/252 user
probe assembly, power supply and
cables, serial cables, target adaptor,
CPA, ICE-5100 controiler pod, software, and documentation for use with
an IBM PC AT or PC XT. The kit also
includes the 8051 Software Development Package and the AEDIT text editor for use' on DOS systems. [Re~
quires software license.)
pl252KITD
This kit is the same as the
pl252KITAD kit excluding the 8051
Software Development Package. and
the AEDIT text editor. [Requires software license.)

pD86AsM51 8051 Software Developm~nt Package (DOS version) - Consists of the
AsM-51 .' macro assembler· which
gives symbolic access to 8051 hardware features; the RL51 linker and relocator program that links modules
generated by AsM-51; CONV51
which enables software written for
the MCs-48 family to be up-graded to
run on the 8051, and the LlB51 librarian which programmers can use
to create and maintain libraries of
software object modules. Use with
the DOS operating system (version
3.0 or later)~

to-388

inter
pD86PLM51

ICETM·5100/252 EMULATOR

PL/M-51 Software Package (DOS
version) - Consists of the PL/M-51
compiler which provides high-level
programming language support; the
LlB51 utility that creates and maintains libraries of software object modules, and the RL51 linker and relocator program that links modules generated by ASM-51 and PL/M-51 and locates the linked object modules to
absolute memory locations. Use the
DOS operating system (version 3.0 or
later).

pl86ASM51

pl86PLM51

pD86EDIEU

10-389

8051 Software Development Package (ISIS version) - Same as the
pD86ASM51 package except this one
is for use with the Series III.
PL/M-51 Software Package - Same
as the pD86PLM51 package except
this one is for use with the Series III
and Series IV.
AEDIT text editor for use with the
DOS operating system.

MCS®-S1 INDEX
8
8031AH,5-2
8032AH,5-2
8051, 5-2
8051AH,5-2
8052AH,5-2
8052AH-BASIC, 5-2
80C31BH, 5-2
80C5IBH, 5-2, 6-28
80C51FA, 5-2, 7-1
83C51FA, 5-2, 7-1
80C152, 5-3
83C152, 5-3
8751H, 5-2, 6-25, 6-26
8752BH, 5-2, 6-26
87C51, 5-2, 6~26, 6-27
87C51FA, 5-2, 7-1

A

AC (Auxiliary Carry) Flag, 6-3, 9-10
ACALL, 5-13, 9-24
Accumulator, 6-2
ADD, 9-25, 9-35
ADDC, 9-26, 9-35
. ADDRESS/DATA Bus, 6-4, 6-5
Addressing
Broadcast, 7-8
Given, 7-8
AJMP, 5-13, 9-28
ALE, 5-16, 6-6, 6-30
ANL, 5-12, 6-6, 9-28
Arithmetic Instructions, 5-7
ASM51,5-6
Automatic Address Recognition, 7-8

B

B Register, 6-2
Baud Rate, 6-12, 6-13, 6-14, 6-17
BCD, 5-8, 5-10
Bit Addressable, 9-5
Boolean Instructions, 5-11, 5-12
Bus Cycle
Data Memory, 5-16
Program Memory, 5-16
Byte Addressable, 9-7

c

C (Carry) Flag, 5-6, 5-12,6-3, 9-10
Capture Mode, 7-4
Capture Registers, 6-2
Case Jump, 5-7, 5-13
Ceramic Resonator, 5-14, 6-28
CINE, 5-14, 9-31
CLR, 5-12, 6-6, 9-33
Compare Mode, 7-6
Control Registers, 6-2

CPL, 5~12, 6-6, 9-34
CPU Timing, 5-14
Crystal, 5-14, 6-27, 6-28

D
DA A, 5-8, 9-35
Data Memory, 5-4, 5-5, 5-11, 6-6, 6-30, 9-3
Read Cycle, 6-31
Write Cycle, 6-31
Data Pointer, 6-2
Data Transfers, 5-9
DEC, 6-6, 9-37
Direct Addressing, 5-7, 9-3, 9-5
DIV AB, 5-8, 6-22, 9-38
DINZ, 5-14, 6-6, 9-39

E

.

EA (External Access), 5-4, 6-6, 6-21, 6-26, 6-30
Encryption Array, 6-26
EPROM Programming, 6-26, 6-30
EPROM Verifying, 6-26
Execution Times, 5-7
External Clock, 6-28, 6-29
External Program Execution, 54
F
.
Fetch/ExecutlOn Sequence, 5-15
Framing Error Detection, 7-8

H
High Speed Output, 7-4, 7-7

I
I/O ButTers, 6-3, 6-4
Idle Mode, 5-2, 6-24, 6-25, 7-9, 9-10
IE (Interrupt Enable), 5-17, 6-2, 6-20, 7-13, 9-11
Immediate Constants, 5-7
INC, 6-6, 9-40
Indexed Addressing, 5-7
Indirect Addressing, 5-7, 9-3, 9-5
Instruction Set, 5-6, 9-20
Interrupt Response Time, 6-21, 6-22
Interrupts, 5-4, 5-17, 6-20,7-11,9-11
External, 6-22, 9-11
IP (Interrupt Priority), 5-17, 6-2, 6-21, 7-13, 9-12
J

.

m, 5-12,

9-42
JBC, 5-12, 6-6, 9-42
JC, 5-12, 9-43
JMP, 5-13, 944

10-390

J (Continued)

JND, 5-12, 9-45
JNC, 5-12, 9-45
JNZ, 9-46
Jump Instructions, 5-13
JZ,9-46

L
LCALL, 5-13, 9-47
UMP, 5-13, 9-47
Lock Bits, 6-26
Logical Instructions, 5-9
Lookup Tables, 5-7, 5-11
M
Machine Cycle, 5-15
MOV, 5-12, 6-6, 9-48
16-Bit, 5-10
MOVC, 5-11, 9-53
MOVX, 5-11, 5-16, 9-54
MUL AB, 5-7, 6-22, 9-56
Multiprocessor Communication, 6-11
N
Ninth Data Bit, 6-11, 6-17
NOP, 9-56

o

ONCE (On-Circuit Emulation) Mode, 6-27
ORL, 5-12, 6-6, 9-57
Oscillator, 5-14, 6-23, 6-27
External, 5-15
Oscillator Frequency, 6-12
OV (Overflow) Flag, 6-3, 9-10

p
P (parity) Flag, 5-7, 6-3, 9-10
PCA Timer/Counter, 7-1, 7-5
PCON, 6-2, 6-12, 6-24, 9-10, 9-19
Polling Sequence, 5-17
POP, 5-9, 9-60
Port Bit Latch, 6-3, 6-4
Ports, 6-2, 6-3, 6-29
Power Down Mode, 5-2,6-24, 6-25, 7-9, 9-10
Power Off Flag, 7-9
PROG,6-30
Program Memory, 5-3, 5-4, 6-6, 6-26, 9-2
Program Memory Locks, 6-26
Programmable Counter Array (PCA), 7-1
PSEN, 5-4, 5-16, 6-6, 6~30
PSW (program Status Word), 5-6, 6-2, 9-10
Pulse Width Modulator (PWM), 7-4, 7-7
PUSH, 5-9, 9-60
Q

Quick-Pulse Programming Algorithm, 6-26

R

RD Signal, 5-4, 6-6
Register Banks, 5-7, 6-3, 9-5, 9-10
Register Instructions, 5-7
Register-Specific Instructions, 5-7
Relative Offset, 5-12
Reset, 6-23, 6-30, 9-8
Power-On, 6-24
RET, 5-13, 6-22, 9-61
RET!, 5-13, 6-21, 6-22, 9-61
RI (Receive Interrupt) Flag, 6-12, 6-14, 6-17, 6-20, 9-18
RL,9-62
RLC, 9-62
RR,9-63
RRC, 9-63

S
SBUF, 6-2, 6-10, 6-14
SCON, 6-2, 6-11, 6-14, 6-17, 9-18
Serial Port, 6-10, 6-15, 7-8, 9-10, 9-12, 9-16, 9-18, 9-19
SET,6-6
SETB, 5-12, 9-64
SFRs, 5-6, 6-1, 6-2, 6-4, 7-15, 9-4, 9-5, 9-7
SJMP, 5-13, 9-65
Software Timer, 7-4, 7-6
Stack Pointer, 6-2, 9-5
Start Bit, 6-11, 6-14, 6-17
State Time, 5-15
Status Flags, 5-7
Stop Bit, 6-11, 6-14, 6-17
SUBB,9-66
SWAP A, 5-9, 9-67

T

T2CON, 6-2, 6-9, 6-10, 6-13, 9-16, 9-17
TCON, 6-2, 6-7, 6-8, 6-22, 9-11, 9-13
Third Priority Level, 5-18
T! (Transmit Interrupt) Flag, 6-12, 6-14, 6-17, 6-20,
9-18
Timer/Counters, 6-2, 6-6, 9-13
Up/Down, 7-9
TMOD, 6-2, 6-7, 9-13, 9-14, 9-17

v

Vpp, 6-26, 6-30

W

Watch Dog Timer, 7-3, 7-8
WR Signal, 5-4, 6-6

X
XCH, 5-10, 9-68
XCHD, 5-10, 9-69
XRL, 5-L2, 6-6, 9-69
XTALl, 5-14, 5-15, 6-28, 6-29, 6-30
XTAL2, 5-14, 5-15, 6-28, 6-29, 6-30

10-391

80C152 INDEX
A

A, 8-4, 8-6
Abort, 8-29, 8-30
Acknowledgement, 8-15, 8-16, 8-24, 8-25, 8-30
Acquisition Time, 8-21
Address, 8-18, 8-25, 8-30, 8-35
Address Assignment, 8-34, 8-35
Address Length
see AL
Address Mask Registers
seeAMSKn
Address Match Registers
see ADRn
Address Negotiation, 8-34
Address Recognition, 8-15, 8-16, 8-18
ADRO, 8-3, 8-4, 8-6, 8-41
ADR1, 8-3, 8-4, 8-6, 8-41
ADR2, 8-3, 8-4, 8-6, 8-41
ADR3, 8-3, 8-4, 8-6, 8-41
AE,8-3, 8-9, 8-43
AL, 8-3, 8-18, 8-41
ALE, 8-13, 8-49
ALE Switch, 8-49
Alignment Error
see AE
Alternate Backoff, 8-15, 8-16, 8-19, 8-21, 8-22, 8-23,
8-40

Alternate Cycle Mode, 8-46, 8-52
AMSKO, 8-3, 8-4, 8-6, 8-41
AMSKl, 8-3, 8-4, 8-6, 8-41
ARB, 8-49, 8-52
Arbiter
see ARB
Arbiter Mode, 8-47, 8-48, 8-49

.

Bit Addressable Memory, 8-6
Bit Addresses, 8-7
Bit Addresses (Symbolic), 8-8
Bit Rate, 8-17
Bit Stripping, 8-25, 8-29, 8-37
Bit Stuffing, 8-25, 8-29, 8-35, 8-37
Bit Time, 8-21
BKOFF, 8-3, 8-4, 8-(;, 8-41
Block Diagram, 8-2
BOF, 8-17, 8-18, 8-20, 8-25, 8-37, 8-39
Broadcast Address, 8-18, 8-25
Burst Mode, 8-46, 8-51, 8-52
Byte Count, 8-33

C

Clock Recovery, 8-17, 8-37, 8-38
Collision, 8-17, 8-20, 8-39
Collision Fragment, 8-21
Collision Resolution, 8-15, 8-16, 8-19, 8-21
Command,8-26
Control Field, 8-25, 8-26, 8-28, 8-30
CRC, 8-3, 8-15, 8-16, 8-18, 8-21, 8-24, 8-25, 8-28, 8-32,
8-35, 8-37, 8-44
CRC Error
see CRCE
CRC Generating Polynomial, 8-18, 8-28
CRC Jam, 8-15, 8-16
CRC Remainder, 8-18, 8-28
CRC Type
see CT
CRCE, 8-3, 8-9, 8-43
Crystal Selection, 8-17
CSMA/CD, 8-14, 8-15, 8-16, 8-17, 8-34, 8-35, 8-37,

8-40
B
B, 8-4, 8-6
Backoff Algorithm, 8-19, 8-20, 8-39, 8-40
Backoff Mode
.
see MO, Ml
Backoff Timer
see BKOFF
Back-to-Back Frames, 8-42
Balanced, 8-30
Baud, 8-3, 8-4, 8-6, 8-20, 8-41
Baud Rate, 8-17, 8-34
Baud Rate Generator
see Baud
BCRHO, 8-3, 8-4, 8-6, 8-45, 8-46
BCRH1, 8-3, 8-4, 8-6, 8-45, 8-46
BCRLO, 8-3, 8-4, 8-6, 8-45, 8-46
BCRL1, 8-3, 8-4, 8-6, 8-45, 8-46
Beginning of Frame Flag
see BOF

CSMA/CD Frame
see Frame Format
CT, 8-3, 8-41
Cyclic Redundancy Check
see CRC

o

DARHO, 8-3, 8-4, 8-6, 8-45
DARH1, 8-3, 8-4, 8-6, 8-45
DARLO, 8-3, 8-4, 8-6, 8-45
DARLl, 8-3, 8-4, 8-6, 8-45
DAS, 8-3, 8-45, 8-52
Data Encoding, 8-15, 8-16, 8-29, 8-34
Data Memory, 8-5
DC Jam, 8-15, 8-16, 8-21
DC Jam (Bit)
see DCJ
DCJ, 8-3, 8-21, 8-42
DCONO, 8-3, 8-4, 8-6, 8-33, 8-45, 8-46, 8-52
DCONl, 8-3, 8-4, 8-6, 8-33, 8-45, 8-46, 8-52
DCR, 8-3, 8-42
10-392

D (Continued)
Deference, 8-17
Demand Mode, 8-46, 8-51, 8-52
Demand Mode (Bit)
seeDM
DEN, 8-11, 8-13, 8-29, 8-35, 8-44
Destination Address Space
see DAS
Deterministic Backoff, 8-15, 8-16, 8-17, 8-19, 8-21,
8-22, 8-23, 8-40, 8-43
Deterministic Collision Resolution (Bit)
see DCR
Direct Memory Access
see DMA
DM, 8-3, 8-46, 8-52
DMA,8-24
DMA Arbitration, 8-51
DMA Control Bits, 8-52
DMA Control Register
see DCONn
DMA Cycle, 8-45, 8-46, 8-47, 8-51
DMA Precedence, 8-51
DMA Register, 8-45
DMA Register Access, 8-51
DMA Select
see DMA (Bit)
DMA Serial Demand Mode
see GSC, Servicing of
DMA Timing, 8-47
DMA Transfer, 8-44, 8-45, 8-47, 8-48
DMA (Bit), 8-9, 8-33, 8-43
DMAO,8-44
DMAI,8-44
DONE, 8-3, 8-9, 8-33,8-46, 8-52
DPH, 8-4, 8-6
DPL, 8-4, 8-6
DPTR,8-6
Duplex
see Full Duplex

L

EA,8-13
EDMAO, 8-9, 8-10
EDMAI, 8-9, 8-10
EGSRE, 8-9, 8-10, 8-20, 8-33
EGSRV, 8-9, 8-10, 8-33
EGSTE, 8-9, 8-10, 8-20, 8-33
EGSTV, 8-9, 8-10, 8-33
End of Frame Flag
- see EOF
Ending Reception, 8-40
Ending Transmission, '8-40
EOF, 8-17, 8-18, 8-25, 8-29, 8-40
Error Reporting, 8-25
ES,8-1O

ETO,8-1O
ETl, 8-10
EXO,8-1O
EXI,8-IO
Extended Address, 8-18
External Clocking of GSC, 8-15, 8-16, 8-17, 8-37
External Demand Mode, 8-46
External Driver, 8-35
External Transmit Clock
seeXTCLK

F
FIFO Pointer, 8-43
Flags, 8-15, 8-16, 8-35
Frame Format, 8-17, 8-25
Full Duplex, 8-15, 8-16, 8-24, 8-30,8-32, 8-34, 8-37
G
Garen, 8-42
GFO, 8-1, 8-5
GFl, 8-1, 8-5
GFIEN, 8-1, 8-5, 8-42
Global Serial Channel
see GSC
Glossary, 8-52
GMOD, 8-3, 8-4, 8-6, 8-41
GO, 8-3, 8-46, 8-52
GREN, 8-3, 8-24, 8-39, 8-40, 8-43
Group Address
see Multicast Address
GRXD,8-13
GSC, 8-14, 8-46
GSC
Servicing of (CPU), 8-32, 8-39
Servicing of (DMA), 8-15, 8-16, 8-32, 8-33, 8-39
Servicing of (GSC), 8-15, 8-16
GSC Auxiliary Receiver Enable
seeGAREN
GSC External Receive Clock Enable
seeXRCLK
GSC Idle Flag Enable
see GFIEN
GSC Mode
see GMOD
GSC Operation, 8-37
GSC Receive Enable
see GREN
GSC Register Descriptions, 8-41
GSC Sampling Rate, 8-20, 8-37
GSC Transmit FIFO
see TFIFO
GTXD,8-13

10-393

H

HABEN, 8-3, 8-24, 8-39, 8-43
Half Duplex, 8-15, 8-16, 8-24, 8-30, 8-32, 8-34, 8-37
Hardware Based Acknowledge Enable
see HABEN
Hardware Based Acknowledgement
see HBA
HBA, 8-15, 8-16, 8-24, 8-30
HDLC, 8-30, 8-37
HLDA, 8-13, 8-44, 8-47,8-48, 8-49, 8-52
HOLD, 8-13, 8-44, 8-47, 8-48, 8-49, 8-52
Hold Acknowledge
see HLDA
Hold Request
see HOLD

I

IDA, 8-3, 8-45, 8-52
Idle, 8-14, 8-40
Idle Fill Flags, 8-42
Idle (GSC), 8-30
IE, 8-4, 8-6, 8-10
IENl, 8-3, 8-4, 8-6, 8-9, 8-10
IFS, 8-3, 8-4, 8-6, 8-19, 8-29, 8-41, 8-42
Increment Destination Address
see IDA
Increment Source Address
see ISA
Information Field, 8-18, 8-25, 8-28
Information Frame, 8-25, 8-26
Initialization (GSC), 8-34, 8-35
INTO, 8-13, 8-46
INTI, 8-13, 8-46
Interframe Space, 8-17, 8-19, 8-22, 8-24, 8-32, 8-40
Interrrame Space (Register),
see IPS
Internal Clocking of GSC, 8-15, 8-16
Interrupt Structure, 8-9
.
IP, 8-4, 8-6, 8-10
IPNl, 8-3, 8-4, 8~6, 8-9, 8-10
ISA, 8-45, 8-52

J

Jam, 8-15, 8-16, 8-17, 8-21, 8-22, 8-40
Jam Time, 8-21
Jitter, 8-35, 8-36

L

Line Discipline, 8-30, 8-34, 8-37
Line Idle
see LNI
LNI, 8-5, 8-30, 8-44
Local Serial Channel
see LSC
Loop Configuration, 8-30
Loopback, 8-35
LSC, 8-14, 8-46

M

.

MO, 8-3, 8-35, 8-40, 8-41
Ml, 8-3, 8-35, 8-40, 8-41
Manchester, 8-15, 8-16, 8-17, 8-20,8-24, 8-35, 8-37
Master Station
see Primary Station
Memory Space, 8-1
Misalignment, 8-24
Mode, 8-26
Modulo, 8, 8-30
Modulo, 128, 8-30
Monitoring Link, 8-40
MOVX, 8-49
Multi-Drop Configuration, 8-30, 8-31
Myslot, 8-3, 8-4, 8-6, 8-22, 8-42

N

Network Changes, 8-32
Network Expansion, 8-32
No Acknowledgement
see NOACK
NOACK, 8-5, 8-9, 8-24, 8-44
Nonsequenced Frame
see Unnumbered Frame
Normal Backoff, 8-15, 8-16, 8-19, 8-21, 8-22, 8-23, 8-40
NRZ, 8-15, 8-16, 8-17, 8-24, 8-35, 8-37
NRZI, 8-15, 8-16, 8-29, 8-35, 8-37
Number of Stations, 8-40

o

Overflow, 8-24
Overrun
see OVR
OVR, 8-3, 8-9, 8-43

P

PO
see PORTO
PI
see PORTI
P2
see PORT2
P3
see PORT3
P4
'
see PORT4
Package, 8-11
PCON, 8-4, 8-6, 8-42, 8-48, 8-49, 8-52
PDMAO, 8-9, 8-10
PDMAl, 8-9, 8-10
PGSRE, 8-9, 8-10
PGSRV, 8-9, 8-10
PGSTE, 8-9, 8-10
PGSTV, 8-9, 8-10
Pin Description, 8-12
Pin Out (DIP), 8-11
Pin Out (PLCC), 8-12
PLO, 8-3, 8-41
PLl, 8-3, 8-41
10-394

RFIFO Time Delay, 8-20
RFNE, 8-3, 8-9, 8-33, 8-39, 8-43, 8-46
RI,8-46
Ring Configuration, 8-30, 8-31
Round-Trip Propagation, 8-21
RSTAT, 8-3, 8-4, 8-6, 8-43
RXC,8-37
RXD,8-13

P (Continued)
Pomt-to-Point Configuration, 8-30, 8-31
PoJl/Final Bit
see P/F Bit
PORTO, 8-4, 8-6, 8-12, 8-44
PORTI, 8-4, 8-6, 8-12
PORT2, 8-4, 8-6, 8-13, 8-44
PORT3, 8-4, 8-6, 8-13
PORT4, 8-3, 8-4, 8-6, 8-11, 8-13
Power Down, 8-14
PR, 8-3, 8-41
PRBS, 8-3, 8-4, 8-6, 8-22, 8-42
Preamble, 8-15, 8-16, 8-17, 8-18, 8-24, 8-35, 8-37
Preamble Length
see PL
Primary Station, 8-24, 8-25, .8-30
Program Memory, 8-8
Program Verification, 8-12, 8-13
Promiscuous Address, 8-25
Protocol (Bit)
see PR
PS,8-1O
PSEN,8-13
Pseudo Random Binary Sequence
see PRBS
PSW, 8-4, 8-6
PTO,8-1O
PT!,8-1O
PXO,8-1O
PXI,8-10
P IF Bit, 8-25, 8-26

R

S

Raw Receive, 8-15, 8-16, 8-17, 8-35
Raw Transmit, 8-15, 8-16, 8-17, 8-29, 8-35
RCABT, 8-3, 8-9, 8-20, 8-29, 8-39, 8-40, 8-43
RD, 8-13, 8-44, 8-47, 8-51
RDN, 8-3, 8-9, 8-33, 8-39, 8-40, 8-43
Receive Count, 8-30
Receive FIFO
see RFIFO
Receive FIFO Not Ready
seeRFNE
Receive Status Register
see RSTAT
Receiver Collision!Abort Detect
see RCABT
Receiver Done
seeRDN
Reception Sequence, 8-26
REN, 8-20, 8-40
REQ, 8-49, 8-52
Requester Mode, 8-47, 8-48, 8-49
Requester (Bit)
see REQ
Reset, 8-1, 8-10, 8-11, 8-13, 8-14, 8-19, 8-42
Resolution Phase, 8-17, 8-21, 8-23
Response, 8-26
Retransmission, 8-39
RFIFO, 8-3, 8-4, 8-6, 8-20, 8-32, 8-33, 8-39, 8-40, 8-43,
8-46

SARHO, 8-3, 8-4, 8-6, 8-33, 8-45
SARHl, 8-~, 8-4, 8-6, 8-45
SARLO, 8-3, 8-4, 8-6, 8-33, 8-45
SARLI, 8-3, 8-4, 8-6, 8-45
SAS, 8-3, 8-45, 8-52
SBUF, 8-4, 8-6, 8-46
SCON, 8-4, 8-6
SDLC, 8-14, 8-15, 8-16, 8-24, 8-30, 8-34, 8-35, 8-37,
8-40
SDLC Commands, 8-27
SDLCFrame
see Frame Format
Secondary Station, 8-24, 8-25, 8-30
Sending Sequence, 8-26
Separation of Busses, 8-50
Sequence Count, 8-25, 8-30
Serial Backplane, 8-44
Serial Port Demand Mode, 8-46
SFRS
see Special Function Registers
Slave Station
see Secondary Station
Slot Address, 8-42
Slot Address Register
see Myslot
Slot Assignment, 8-17
Slot Time, 8-21, 8-22, 8-32, 8-40
Slot Time (Register)
see SLOTTM
SLOTTM, 8-3, 8-4, 8-6, 8-21, 8-43
Source Address Space
see SAS
SP, 8-4, 8-6
Special Function Registers, 8-3, 8-6
Supervisory Frame, 8-25, 8-26

T

TO,8-13
T!, 8-13
TCDCNT, 8-3, 8-4, 8-6, 8-22, 8-39, 8-40, 8-43
TCDT, 8-5, 8-9, 8-20, 8-39, 8-40, 8-44
TCON, 8-4, 8-6
TDN, 8-5, 8-9, 8-24, 8-33, 8-39, 8-40, 8-43, 8-44
TEN, 8-5, 8-29, 8-39, 8-40, 8-43, 8-44
Test Modes, 8-35
TFIFO, 8-4, 8-5, 8-6, 8-29, 8-32, 8-33, 8-39, 8-40, 8-43,
8-44,8-46
TFNF, 8-5, 8-9, 8-39, 8-44, 8-46
THO, 8-4, 8-6
THl, 8-4, 8-6

10-395

T (Continued)

TI,8-46
Timer/Counters, 8-11
TLO, 8-4, 8-6
TL1~ 8-4, 8-6
TM, 8-3,8-46, 8-52
TMOD, 8-4, 8-6
Transfer Mode
seeTM
Transmission During Resolution, 8-40
Transmit Collision Detect
see TCDT
....
Transmit Collision Detect Count
see TCDCNT
.
Transmit Done
see TDN
Transmit Enable
see TEN
Transmit FIFO Not Full
see TFNF
Transmit Status Register
see TSTAT
Transmit Waveforms, 8-37
TSTAT, 8-4, 8-5, 8-6, 8-43
Turn-Around Time, 8-19
TXC, 8-3, 8-37
TXD,8-13

U
UART
see LSC
Unbalanced, 8-30
Underrun
seeUR
Unnumbered Frame, 8-25, 8~26, 8-27, 8-28
Unused SFR Addresses, 8-5
UR, 8-5, 8-9, 8-43, 8-44
User Defined Protocols, 8-30
Using GSC, 8-30
Using HLDA, 8-49
Using HOLD, 8-, 8-49

v

Vee, 8-12
Vss, 8-12
W
WR, 8-13, 8-44, 8-47, 8-51

X

XRCLK, 8-1, 8-5, 8-37, 8-42
XTAL1,8-12
XTAL2,8-12
XTCLK, 8-37, 8-41

10-396

RUPITM..44 Family

.11

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THE RUPITM·44 FAMILY:
MICROCONTROLLER WITH ON·CHIP
COMMUNICATION CONTROLLER
real-time control applications such as instrumentation,
industrial control, and intelligent computer peripherals.
The microcontroller features on-chip peripherals such
The RUPI-44 family is designed for applications reas two 16-bit timer/counters and 5 source interrupt caquiring local intelligence at remote nodes, and commupability with programmable priority levels. The micronication capability among these distributed nodes. The
controller's high performance CPU executes most inRUPI-44 integrates onto a single chip Intel's highest
structions in 1 microsecond, and can perform an 8 X 8
performance microcontroller, the 8051-core, with an
multiply in 4 microseconds. The CPU features a Booleintelligent and high performance Serial communication
an processor that can perform operations on 256 directcontroller, called the Serial Interface Unit, or SIU. See
ly addressable bits. 192 bytes of on-chip data RAM can
Figure 1. This dual controller architecture allows combe extended to 64K bytes externally. 4K bytes of onplex control and high speed data communication func- .
chip program ROM can be extended to 64K bytes extions to be realized cost effectively~
. ternally. The CPU and SIU run concurrently. See Figure 2.
The R~PI-44 family consists of three pin compatible
parts:
The SIU is designed to perform serial communications
• 8344-8051 Microcontroller with SIU
with little or no CPU involvement. The SIU supports
• 8044-An 8344 with 4K bytes of on-chip ROM prodata rates up to 2.4 Mbps, externally clocked, and
gram memory
375 Kbps self clocked (i.e., the data clock is recovered
by an on-chip digital phase locked loop). SIU hardware
• 8744-An 8344 with 4K bytes of on-chip EPROM
supports the HDLC/SDLC protowl: zero bit inserprogram memory
tion/deletion, address recognition, cycli.: rcdundan.:y
. check, aI\d frame number sequence check arc automatically performed.
1.0 ARCHITECTURE OVERVIEW

INTRODUCTION

The 8044's dual controller architecture enables the
RUpj to perform complex control tasks and high speed
communication in a distributed network environment.

The SIU's Auto mode greatly reduces communication
software overhead. The AUTO mode supports the
SDLC Normal Response Mode, by performing secondary station responses in hardware without any CPU
involvement .. The Auto mode's interrupt control and
frame sequence numbering capability eliminates software overhead normally required in conventional systems. By using the Auto mode, the CPU is free to concentrate on real time control of the application_

The 8044 microcontroller is the 805I-core, and maintains complete software compatibility with it. The microcontroller contains a powerful CPU with on-chip
peripherals, making it capable of serving sophisticated

,--------------------,
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296163-1

Figure 1. RUPITM-44 Dual Controller Architecture

11-1

Order Number: 296163-001

THE RUPITM·44 FAMILY

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11-2

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THE RUPITM-44 FAMILY

• EFFICIENT: Well Oefined Message-Level Operation
• RELIABLE: Frame Check Sequence and Frame
Numbering

2.0 THE HOLC/SOLC PROTOCOLS
2.1 HOLC/SOLC Advantages over
Async

The SOLC reduces system complexity. HOLC/SOLC
are "data transparent" protocols. Oata transparency
means that an arbitrary data stream can be sent without concern that some of the data could be mistaken for
a' protocol controller. Data transparency relieves the
communication controller having to detect special
characters.

The High Level Oata Link Control, HOLC, is a standard communication link control established by the International Standards Organization (ISO). SOLC is a
subset of HOLC.
HOLC and SOLC are both well recognized standard
serial protocols. The Synchronous Oata Link Control,
SOLC. is an IBM standard communication protocol.
IBM originally developed SOLC to provide efficient.
reliable and simple communication between terminals
and computers.

SOLC/HOLC provides more data tllroughout than
Async. SOLC/HOLC runs atMessage-leve~ Operation
which transmits multiple l-ytes within the frame.
whereas Async is based on character-level ?peration.
Async transmits or receives a character at a tine. Since
Async requires start and stop bits in every ransmission. there is a considerable waste of overhad compared to SOLC/HOLe.

The major advantages of SOLC/HOLC over Asynchronous communications protocol (Async):
• SIMPLE: Oata Transparency

-

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8044 CONTROLLED
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1044 CONTROLLO
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~
1044 CONTROLLED
SECONDARY

1044 CONTROLLED
SECONDARY

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1044 CONTROLLED
SECONDARY

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1044 CONTROLLED
SECONDARY

296163-5
c) SDLC Loop Configuration

Figure 3. RUPITM-44 Supported Network Configurations

11-3

inter

THE RUPITM-44 FAMILY

Due to SOLC/HOLC's well delineated field (see Figure 4) the CPU does not have to interpret ~haracter.by
character to detcrmine control field and mformatlOn
field. In the case of Async, CPU must look at each
character to interpret what it means. The practical advantage of such feature is straight forward use of OMA
for information transfer.
In addition, SOLC,IHOLCfurther improves Oata
throughput using implied Acknowledgement of trans.
ferred information. A station using SOLC/HOLC may
acknowledge previously received information while
transmitting different information in the same frame.
In addition, up to 7 messages may be outstanding before an acknowledgement is required.
The HOLC/SOLC protocol can be used to realize reliable datalinks. Reliable Oata transmission is ensured at
the bit lerel by sending a frame check sequence, cyclic
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alnkO

296164-6
296164-S

Figure 10. Addressing Operands
in Internal Data Memory

Figure 9. RAM Bit Address
12-7

inter

RUPITM_44

Register-Indirect Addressing using the content of Rl
or RO in the selected Register Bank, or using the content of the Stack Pointer (pUSH and POP only), addresSes the Internal Data RAM. Register-Indirect Addressing is also used for accessing the External Data
Memory. In this case, either Rl or RO in the selected
Register Bank may be used for accessing locations
within a 256-byte block. The block number can be preselected by the contents of a port. The 16-bit Data
Pointer may be used for accessing any location within
the full 64K external address space.

TBS
TBL
TCB
RBS
RBL
RFL
RCB
DMACNT
FIF01
FIF02
FIF03
SIUST
PCON

3.0 RESET
Reset is accomplished by holding the RST pin high for
at least two machine cycles (24 oscillator periods) while
the oscillator is running. The CPU responds by executing an internal reset. It also configures the ALE and
PSEN pins as inputs. (They are quasi-bidirectional.)
The internal reset is executed during the second cycle in
which RST is high and is repeated every cycle until
RSt goes low. It leaves the internal registers as follows:
Register
Content
PC
OOOOH
A
OOH
B
OOH
PSW
OOH
SP
07H
DPTR
OOOOH
PO-P3
OFFH
IP
(XXXOOOOO)
IE
(OXXOOOOO)
TMOD
OOH
TCON
OOH
THO
OOH
TLO
OOH
TH1
OOH
TL1
OOH
SMD
OOH
STS
OOH
NSNR
OOH
STAD
OOH

OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
01H
(OXXXXXXX)

The internal RAM is not affected by reset. When VCC
is turned on, the RAM content is indeterminate unless
VPD was applied prior to VCC being turned off (see
Power Down Operation.)

4.0 RUPITM·44 FAMILY PIN
DESCRIPTION
VSS: Circuit ground potential.
VCC: Supply voltage during programming (of the
8744), verification (of the 8044 or 8744), andnorinal
operation.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. It is also the multiplexed low-order address and
data bus during accessses to external memory (during
which accesses it activates internal pullups). It also outputs instruction bytes during program verification. (External pullups are required during program verification.) Port 0 can sink eight LS TIL inputs.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pUllups. It receives the low-order address byte
during program verification in the 8044 or 8744. Port 1
can sink/source four LS TIL inputs, It can drive MOS
inputs without external pullups.
Two of the Port 1 pins serve alternate functions, as
listed below:
Port Pin
Alternate Function
P1.6
RTS (Request to Send). In a non-loop configuration, RTS signals that the 8044 is ready to
transmit data.

12-8

8044 Serial Interface

13

THE RUPITM-44 SERIAL INTERFACE UNIT
SERIAL INTERFACE

Externally Clocked Mode

The serial interface provides a high-performance communication link. The protocol used for this communication is based on the IBM Synchronous Data Link
Control (SDLC). The serial interface also supports a
subset of the ISO HDLC (International Standards Organization High-Level Data Link Control) protocol.

In the externally clocked mode, a common Serial Data
Clock (SCLK on pin 15) synchronizes the serial bit
stream. This clock signal may come from the master
CPU or primary station, or from an external phaselocked loop local to the 8044. Figure 3 illustrates the
timing relationships for the serial interface signals when
the externally clocked mode is used in point-to-point
and multipoint data link configurations.

The SDLCIHDLC protocols have been accepted as
standard protocols for many high-level teleprocessing
systems. The serial interface performs many of the
functions required to service the data link without intervention from the 8044's own CPU. The programmer
is free to concentrate on the 8044's function as a peripheral controller, rather than having to deal with the details of the communication process.

Incoming data is sampled at the rising edge of SCLK,
and outgoing data is shifted out at the falling edge of
SCLK. More detailed timing information is given in the
8044 data sheet.

Self Clocked (Asynchronous) Mode
Five pins on the 8044 are involved with the serial interface:
Pin 7
RTS/P16
CTS/P17
Pin 8
Pin 10 I/O/RXD/P30
Pin 11
DATA/TXD/P31
Pin 15 SCLK/Tl//P35

The self clocked mode allows data transfer without a
common system data clock. Using an on-chip DPLL
(digital phase locked loop) the serial interface recovers
the data clock from the data stream itself. The DPLL
requires a reference clock equal to either 16 times or 32
times the data rate. This reference clock may be externally supplied or internally generated. When the serial
interface generates this clock internally, it uses either
the 8044's internal logic Clock (half the crystal frequency's PH2) or the "timer 1" overflow. Figure 4 shows
the serial interface signal timing relationships for the
loop configuration, when the unclocked mode is used.

Figure 1 is a functional block diagram of the serial interface unit (SIU). More details on the SIU hardware
are given later in this chapter.

The DPLL monitors the received data in order to derive a data clock that is centered on the received bits.
Centering is achieved by detecting all transitions of the
received data, and then adjusting the clock transition
(in increments of '1.8 bit period) toward the center of
the received bit. The DPLL converges to the nominal
bit center within eight bit transitions, worst case.

1.0 DATA LINK CONFIGURATIONS
The serial interface is capable of operating in three serial data link configurations:
. 1) Half-Duplex, point-to-point
. 2) Half-Duplex, multipoint (with a half-duplex or fullduplex primary)
3) Loop

To aid in the phase locked loop capture process, the
8044 has a NRZI (non-return-to-zero inverted) data encoding and decoding option. NRZI coding specifies
that a signal does not change state for a transmitted
binary 1, but does change state for a binary O. Using the
NRZI coding with zero-bit insertion, it can be guaranteed that an active signal line undergoes a transition at
least every six bit times.

Figure 2 shows these three configurations. The RTS
(Request to Send) and CTS (Clear to Send) hand-shaking signals are available in the point-to~point and multipoint configurations.

2.0 DATA CLOCKING OPTIONS
3.0 DATA RATES

The serial interface can operate in an externally clocked
mode or in a self clocked mode.

The maximum data rate in the externally clocked mode
is 2.4M bits per second (bps) a half-duplex configuration, and l.OM in a loop configuration.
13-1

Order Number: 296165-001

l
BIT PROCESSOR

BYTE PROCESSOR

SYNCHRONIZED

a

DIGITAL
PHASE
LOCI(

Rxe:>

.,

LOOP

CONTROL

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2

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INTERNAL
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PORT

SIU
HARDWARE
REGISTER
(2 PORT)

RAM

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18 \.

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296165-1

RUPITM-44 SIU

8044
CONTROLLED
SECONDARY

MASTERI
PRIMARY

296165-2

1) HALF·DUPLEX, POINT·TO·POINT

MASTERI
PRIMARY

-

~

~

8044
CONTROLLED
SECONDARY

8044
CONTROLLED
SECONDARY

296165-3

2) HALF·DUPLEX, MULTIPOINT

MASTERI
PRIMARY

8044
CONTROLLED
SECONDARY

8044
CONTROLLED
SECONDARY

8044
CONTROLLED
SECONDARY

296165-4

3) LOOP
Figure 2. RUPI-44 Data Link Configurations

13-3

· RUPITM·44SIU

In the self clocked mode with an external reference
dock, the maximum data rate is 375K bps.

4.1 AUTO Mode
To enable the SIU to receive a frame in AUTO mode,
the 8044 CPU sets up a receive buffer. This is done by
writing two registers-Receive Buffer Start (RBS) Address and Receive Buffer Length (RBL).

In the self clocked mode with an internally generated
reference clock, and the 8044 operating With a 12 MHz
crystal, the available data rates are 244 bps ·to 62.5K
bps, 187.5K bps and 375K bps.

The SIU receives the frame, examines the control byte,
and takes the appropriate action. If the frame is an
information frame, the.SIU will load the receive buffer,
interrupt the CPU (to have the receive buffer read), and
make the required acknowledgement to the primary
station. Details on these processes are given in the Operation section, below.

For more details see the table in the SMD register description, below.

4.0 OPERATIONAL MODES
The Serial Interface Unit (SIU) can operate in either of
two response modes:

In addition to receiving the information frames, the
SIU in AUTO mode is capable of responding to the
following commands (found in the control field of supervisory frames) from the primary station:

1) AUTO mode
2) FLEXIBLE (NON-AUTO) mode
In the AUTO mode, the stu performs iIi hardware a
subset of the SDLC protocol called the. normal response mode. The AUTO mode enables the SIU to recognize and respond to certain kinds of SDLC frames
without intervention from the 8044's CPU. AUTO
mode provides a faster turnaround time and a simplified software interface, whereas NON-AUTO mode
provides a greater flexibility with regard to the kinds of
operation permitted.

RR (Receive Ready): Acknowledges that the Primary
station has correctly received numbered frames up
through NR - 1; and that it is ready to receive frame
NR·
RNR (Receive Not Ready): Indicates a temporary busy
condition (at the primary station) due to buffering or
other internal constraints. The quantity NR in the control. field indicates the number of the frame expected
after the busy condition ends, and may be used to acknowledge the correct reception of the frames up
through NR - 1.

In AUTO mode, the 8044 can act only as a normal
response mode secondary station-that is, it can transmit only when instructed to do so by the primary station. All such AUTO mode responses adhere strictly to
IBM's SDLC definitions.

REI (Reject): Acknowledges the correct reception of

frames up through NR - I, and requests transmission
or retransmission starting at frame. NR. The 8044 is
capable of retransmitting at most the previous frame,
and then only if it is still available in the trarismit buffer.

In the FLEXIBLE mode,reception or transmission of
each frame by the SIU is performed under the control
of the CPU. In this mode the 8044 can be either a
primary station or a secondary station.
In both AUTO and FLEXIBLE modes, short frames, .
aborted frames, or frames which have had CRC's are·
ignored by the SIU.
The basic format of an SDLC frame is as follows:
! Flag! Address! Control! Information! FCS ! Flag

I

Format variatio~s consist of omitting one or more of
the fields in the SDLC frame. For example, a supervisory frame is formed by omitting theinformation field.
Supervisory frames are used to confirm received
frames, indicate ready or busy conditions, and to report
errors. More details on frame formats are given in the
SDLC Frame Format Options section, below.

UP (Unnumbered Poll): Also called NSP (Non-Sequenced Poll) or ORP (Optional Response Poll). This
command is used in the loop configuration.
To enable the SIU to transmit an information frame in
AUTO mode, the CPU sets up a transmit buffer. This
is done by writing two registers-Transmit Buffer Start
(TBS) Address and Transmit Buffer Length (TBL), and
filling the transmit buffer with the information to be
transmitted.
When the transmit buffer is full, the SIU can automatically (without CPU intervention) send an information
frame (I-frame) with the appropriate sequence numbers, when the data link becomes available (when the
8044 is polled for information). After the SIU has
transmitted the I-frame, it waits for acknowledgement
from the receiving station. If the acknowledgement is

13-4

RUPITM_44 SIU

negative, the SIU retransmits the frame. If the acknowledgement is positive, the SIU interrupts the

CPU, to indicate that the transmit buffer may be reloaded with new information.

\J
iiTs

7

CTs

TRANSCEIVER/BUFFER

8

8044

I/O

10

J

C>

-

DATA

de control bit when NB = 0, and Address Mode control bit when NB = 1.

Figure 5. Frame Format Options
in the on-chip RAM. No FCS checking is done on the
received frames, and no FCS is generated for the transmitted frames. The No FCS Field option may be used
in conjunction with any of the other options. It is typically used in FLEXIBLE mode, although it does not
strictly include AUTO mode. Use of the No FCS Field
option AUTO Mode may, however, result in SDLC
protocol violations, since the data integrity is not
checked by the sm.

5.4 No FCS Field
In the normal case (NFCS = 0), the last 16 bits before
the closing flag are the Frame Check Sequence (FCS)
field. These bits are not stored in the· 8044's RAM.
Rather, they are used to compute a cyclic redundancy
check (CRC) on the data in the rest of the frame. A
received frame with a CRC error (incorrect FCS) is
ignored. In transmission, the FCS field is automatically
computed by the SIU, and placed in the transmitted
frame just prior to the closing flag.

Formats without an FCS field have the following applications:

The NFCS bit (SMDBit 0) gives the user the capability
of overriding this automatic feature. When this bit is set
(NFCS = I), all bits from the beginning of the information field to the beginning of the closing flag are
treated as part of the information field, and are stored

Receiving and transmitting frames without verifying
data integrity.
Using an alternate data verification algorithm.

13-8

RUPITM·44 SIU

Using an alternate CRC-16 polynomial (such as XI6
XIS + X2 + I), or a 32-bit CRC

+

SMD: SERIAL MODE REGISTER
(BYTE-ADDRESSABLE)
Bit:

Performing data link diagnosis by forcing false CRCs
to test error detection mechanisms

7

6

5

4

3

2

1

0

I SCM21 SCM1 I SCMO I NRZII LOOP I PFS I NB I NFCS I

In addition to the applications mentioned above, all of
the format variations are useful in the support of nonstandard bit-synchronous protocols.

6.0 HOLC
In addition to its support of SDLC communications,
the 8044 also supports some of the capabilities of
HDLC. The following remarks indicate the principal
differences between SDLC and HDLC.
HDLC permits any number of bits in the information
field, whereas SDLC requires a byte structure (multiple
of 8 bits). The 8044 itself operates on byte boundaries,
and thus it restricts fields to multiples of 8 bits.
HDLC provides functional extensions to SDLC: an unlimited address field is allowed, and extended frame
number sequencing.
HDLC does not support operation in loop configurations.

7.0 SIU SPECIAL FUNCTION
REGISTERS
The 8044 CPU communicates with and controls the
SIU through hardware registers. These registers are accessed using direct addressing. The SIU special function registers (SIU SFRs) are of three types:
Control and Status Registers
Parameter Registers
ICE Support Registers

The Serial Mode Register (Address C9H) selects the
operational modes of the SIU. The 8044 CPU can both
read and write SMD. The SIU can read SMD but cannot write to it. To prevent conflict between CPU and
SIU access to SMD, the CPU should write SMD only
when the Request To Send (RTS) and Receive Buffer
Empty (RBE) bits (in the STS register) are both false
(0). Normally, SMD is accessed only during initialization.
The individual bits of the Serial Mode Register are as
follows:
Blt#
Name
Description
SMD.O
NFCS
No FCS field in the SDLC
frame.
SMD.1
NB
Noon-Buffered mode. No
control field in the SDLC
frame.
SMD.2
PFS
Pre-Frame Sync mode. In
this
mode,
the
8044
transmits two bytes before
the first flag of a frame, for·
DPLL synchronization. If
NRZI is enabled, OOH is
sent; otherwise, 55H is sent.
In either case, 16 pre-frame
transitions are guaranteed.
SMD.3
LOOP
Loop configuration.
SMD.4
NRZI
NRZI coding option.
SMD.5
SCMO
Select Clock Mode-Bit 0
Select Clock Mode-Bit 1·
SMD.6
SCM1
SMD.7
SCM2
Select Clock Mode-Bit 2
The SCM bits decode as follows:
SCM

Clock Mode

210
000
001
010
011
1 00
1 0 1
1 1 0
111

7.1 Control and Status Registers
There are three SIU Control and Status Registers:
Serial Mode Register (SMD)
Status/Command Register (STS)
Send/Receive Count Register (NSNR)

Externally clocked
Undefined
Self clocked, timer overflow
Undefined
Self clocked, external 16x
Self clocked, external 32x
Self clocked, internal fixed
Self clocked, internal fixed

·Based on a 12 MHz crystal frequency
• ·0-1 M bps in loop configuration

The SMD, STS, and NSNR registers are all cleared by
system reset. This assures that the SIUwill power up in
an idle state (neither receiving nor transmitting).
These registers and their bit assignments are described
below (see also the More Details on Registers section).

13-9

Data Rate
(Bits/sec)·
0-204M··
244-62.5K
0-375K
0-187.5K
375K
187.5K

intJ

RUPITM_44 SIU

STS: STATUS/COMMAND REGISTER,
(BIT-ADDRESSABLE)
Bit:

7

6

5

4

3

2'

1

Bit#

Name

STS.7

TBF

0

I rBF I RBE I Rrs I 51 I BOV I OPB I AM I RBP I

The Status/Command Register (Address CSH) pro~
vides operational control of the SIU by the S044 CPU,
and enables the SIU to post status information Jor the
CPU's access. 'The SIU can read STS: and can alter
certain bits, as indicated below. The CPU,can both read
and write STS asynchronously. However, 2-cycle instructions that access STS during both cycles ('JBC/B,
REL' and 'MOY /B,C.') should not be used, since the
SIU may write to STS between the two CPU accesses.
The individual bits of the Status/Command Register
are as follows:
Bit#'
Name
Description
STS.O' RBP
Receive Buffer Protect. Inhibits
writing of data into the receive
buffer. In AUTO mode, RBP
forces an RNR response
instead of an RR.
STS.1AM,
AUTO ModelAddressed Mode.
Selects AUTO mode where
AUTO mode is allowed. If NB is
, true; (= 1), the AM bit selects
, the addressed mode. AM may
be cleared by the SIU.
STS.2 OPB
Optional Po" Bit. Determines
whether the SIU will generate
an AUTO response to an
optional po" (UP with P = 0).
OPB may be set or cleared by
the SIU ..
STS.3 BOV
Receive Buffer Overrun. BOV
may be set or cleared by the
SIU.
STS.4 SI
SIU Interrupt This is one of the
five interrupt sources to the
CPU. The vector location =
23H. SI may beset by the SIU.
It should be cleared by the CPU
before returning fron'! an '
interrupt routine.
STS.5 RTS
Request To Send. Indicates
tnat the 8044 is ready to
'
transmit or is transmitting. RTS
may be read or written by the
CPU. RTS may be read by the
SIU, and in AUTO mode may
be written by the SIU.
STS.6 RBEReceive Buffer Empty. RBE
can be thought of as Receive'
Enable. RBE is set to one by
the CPU when it is ready to
receive a frame, or has just
read the buffer, and to zero by
the SIU when a frame has been
received.

Description
Transmit Buffer Fu". Written by
the CPU to indicate that it has ,
filled the transmit buffer. TBF
may be cleared by the SIU.,

NSNR: SEND/RECEIVE COUNT REGISTER
(BIT-ADDRESSABLE)
B~

7

6

5

4

3

2

1

0

INS21 NS1 INSO ISES I NR21 NR1 INRO ISER I

The SendlReceive Count Register (Address DSH) contains the transmit and receive sequence numbers, plus
tally error' indications. The SIU can both read and
write NSNR. The S044CPU can both read and write
NSNR asynchronously. However, 2-cycle instructions
that access NSNR during both cycles (,JBC /B, REL',
and 'MOY /B,C') should not be used, since the SIU
may write to NSNR between the two S044 CPU accesses.
The individual bits of the SendlReceive Count Register
are as follows:
Bit#

Name

Description

NSNR.O SER

Receive Sequence Error:
NS (P)* NR (S)

NSNR.1 NRO

Receive Sequence Counter-Bit 0

NSNR.2 NR1

Receive Sequence Counter-Bit 1

NSNR.3 NR2

Receive Sequence Counter-Bit 2

NSNR.4 SES

NSNR.5 NSO

Send Sequence Error:
NR (P) * NS (S) and
NR (P)* NS (S) + 1
Send Sequence Counter-Bit 0

NSNR.6 NS1

Send Sequence Counter-"-Bit 1

NSNR.7 NS2

Send Sequence Counter-Bit 2

7.2 Parameter Registers
There are eight, parameter registers that are used in
connection, with SIUoperation. All eight registers may,
be read or written by the S044 CPU. RFL and RCB are
normally ,loaded by the, SIU.
The eight parameter registers are as follows:
STAD: STATION ADDRESS REGISTER
(BYTE-ADDRESSABLE)

The Station Address register (Address CEH) cOntains
the station address. To prevent access conflict, the CPU

13-10

RUPITM_44 SIU
should access STAD only when the sm is idle (RTS =
o and RBE = 0). Normally, STAD is accessed only
during initialization.

RFL: RECEIVE FIELD LENGTH REGISTER
(BYTE-ADDRESSABLE)

TBS: TRANSMIT BUFFER START ADDRESS
REGISTER (BYTE-ADDRESSABLE)

The Received Field Length register (Address CDH)
contains the length (in bytes) of the received I-field that
has just been loaded into on-chip RAM. RFL is loaded
by the sm. RFL = 0 is valid. RFL should be accessed
by the CPU only when RBE = O.

The Transmit Buffer Start address register (Address
DCH) points to the location in on-chip RAM for the
beginning of the I-field of the frame to be transmitted.
The CPU should access TBS only when the SIU is not
transmitting a frame (when TBF = 0).

RCB: RECEIVE CONTROL BYTE REGISTER
(BYTE-ADDRESSABLE)

The Received Control Byte register (Address CAH)
contains the control field of the frame that has just been
received. RCB is loaded by the sm. The CPU can only
read RCB, and should only access RCB when RBE =
O.

TBL: TRANSMIT BUFFER LENGTH REGISTER
(BYTE-ADDRESSABLE)

The Transmit Buffer Length register (Address DBH)
contains the length (in bytes) of the I-field to be transmitted. A blank I-field (TBL = 0) is valid. The CPU
should access TBL only when the SIU is not transmitting a frame (when TBF = 0).

7.3 ICE Support Registers
The 8044 In-Circuit Emulator (ICE-44) allows the user
to exercise the 8044 application system and monitor the
execution of instructions in real time.

NOTE:
The transmit and receive buffers are not allowed to
"wrap around" in the on-chip RAM. A "buffer end"
is automatically generated if address 191 (BFH) is
reached.

The emulator operates with Intel's Intellec® development system. The development system interfaces with
the user's 8044 system through an in-cable buffer box.
The cable terminates in a 8044 pin-compatible plug,
which fits into the 8044 socket in the user's system.
With the emulator plug in place, the user can exercise
his system in real time while collecting up to 255 instruction cycles of real-time data. In addition, he can
single-step the program.

TCB: TRANSMIT CONTROL BYTE REGISTER
(BYTE-ADDRESSABLE)

The Transmit Control Byte register (Address DAH)
contains the byte which is to be placed in the control
field of the transmitted frame, during NON-AUTO
mode transmission. The CPU should access TCB only
when the SIU is not transmitting a frame (when TBF
= 0). The Ns and NR counters are not used in the
NON-AUTO mode.
RBS: RECEIVE BUFFER START ADDRESS
REGISTER (BYTE-ADDRESSABLE)

The Receive Buffer Start address register (Address
CCH) points to the location in on-chip RAM where the
beginning of the I-field of the frame being received is to
be stored. The CPU should write RBS only when the
SIU is not receiving a frame (when RBE = 0).

Static RAM is available (in the in-cable buffer box) to
emulate the 8044 internal and external program memory and external data memory. The designer can display
and alter the contents of 'the replacement memory in
the buffer box, the internal data memory, and the internal 8044 registers, including the SFRs.
Among the SIU SFRs are the following registers that
support the operation of the ICE:
DMA CNT: DMA COUNT REGISTER
(BYTE-ADDRESSABLE)

The DMA Count register (Address CFH) indicates the
number of bytes remaining in the information block
that is currently being used.

RBL: RECEIVE BUFFER LENGTH REGISTER
(BYTE-ADDRESSABLE)

The Receive Buffer Length register (A.ddress CBH)
contains the length (in bytes) of the area in on-chip
RAM allocated for the received I-field. RBL = 0 is
valid. The CPU should write RBL only when RBE =
O.

FIFO: THREE-BYTE (BYTE-ADDRESSABLE)

The Three-Byte FIFO (Address DDH, DEH, and
DFH) is used between the eight-bit shift register and
the information buffer when an information block is
received.

13-11

inter

RUPITM_44 SIU

SIUST: SIU STATE COUNTER (BYTEADDRESSABLE)
,

The SIU Suite Counter (Address D9H) reflects the
state of the internal logic which is under SIU control.
Therefore, care must be taken not to write into this
register.

SIUST
Value

Function

2SH

Waiting for I field byte. This state can be
entered from state 20H or from states
01 H, OSH, or 10H depending upon the
SIU's mode configuration. (Each time a
byte is received, it is pushed onto the top
of the FIFO and the byte at the bottom is
put into memory. For no FOS formatted
frames, the FIFO is collapsed into a
single register).

30H

Waiting for the closing flag after having
overflowed the receive buffer. Note that
even if the receive frame overflows the
assigned receive buffer length, the FOS
is still checked.

The SIUST register can serve as a helpful aid to determine which field of a receive frame that the SIU expects next. The table below will help in debugging 8044
reception problems.
SIUST
Value

01H
OSH
10H
lSH

20H

Function
Waiting for opening flag.
Waiting for address field.
Waiting for control field.
Waiting for first byte of I field. This state
is only entered if a FOS is expected. It
pushes the received byte onto the top of
the FIFO.
.
.

Examples of SIUST status sequences for different frame
formats are shown below. Note.that status changes after acceptance of the received field byte.

Waiting for second byte of I field. This
state always follows state lSH.

Table 1 SIUST Status Sequences
Frame Option
NFCS NB AM~
Example 1:
Frame Format
SIUSTValue

I

o

o

Example 2:

I.

Frame Format 1 (Idle) 1 F 1 A 1 I
1 F0 S
F 1
2S
1__
SIUST Value
_0_1:...,..J.L...0-=-1:..L.:.OS::..J....:1~S...JI...:2:.:0:..L1...:2::S:...J,-'::::::"":_L.::0:.:.

o

L,

Example 3:
Frame Format
SIUSTValue

I

o

o

Example 4:
Frame Format
SIUSTValue

I (Idle) I F I A I I I F I
I 01 I 01 I OS I 2S I 01 I

Example 5:
Frame Format t.!.(I"..dl,..;e)+1
_:...1_-I-I_F~I
SIUST Value . L_ _0_1_J...,_01.;....L._~2.:.S_.L-=0~1...J

o

",:-F-+I.;..'

ExampleS:
Frame Format 1 (Idle) -, F
SIUSTValue

1 01

l'

1

I
.'
1 0111s120 12s1

I OVERFLOW

I FOS 1 F 1

30

1 .30 1011

13-12

o

o

intJ

RUPITM-44 SIU

8.0 OPERATION

TBS, TBL - to define the area in RAM allocated for
the Transmit Buffer.

The SIU is initialized by a reset signal (on pin 9), followed by write operations to the SIU SFRs. Once initialized, the SIU can function in AUTO mode or NONAUTO mode. Details are given beiow.
'

Once these registers have been initialized, the user may
write to the STS register to enable the SIU to leave the
idle state, and to begin transmits and/or receives.

8.1 Initialization

Setting RBE to 1 enables the SIU for receive. When
RBE = I, the SIU monitors the received data stream
for a flag pattern. When a flag pattern is found, the SIU
enters Receive mode and receives the frame.

Figure 6 is the SIU. Registers SMD, STS, and NSNR
are cleared by reset. This puts the 8044 into an idle
state-neither receiving nor transmitting. The following registers must be initialized before the 8044 leaves
the idle state:
- to establish the 8044's SDLC station adSTAD
dress.
SMD
- To configure the 8044 for the proper operating mode.
RBS, RBL - to define' the area in RAM allocated for.
.
the Receive Buffer.
.

Setting RTS to 1 enables the SIU for t~ansmit. When
RTS = I, the SIU monitors the received data stream
for a GA pattern (loop configuration) or waits for a
CTS (non-loop configuration). When the GA or CTS
arrives, the SIU ·enters Transmit mode and transmits a
frame.
In AUTO mode, the SIU sets RTS to enable automatic
transmissions of appropriate responses.

END-OFFRAME
FLEXIBLE
MODE

STRTREC

STRTXMIT
FLEXIBLE
MODE

END-OF·FRAME
AUTO MODE

STRT REC = RBE. FLAG
STRT XMIT = RTS. (CTS. LOOP + GA.LOOP)
WAIT
= NOT (STRT REC + STRTXMIT)

Figure 6. SIU State Diagram

13-13

. 296165-9

inter

RUPITM-44 SIU

8.2 AUTO Mode
Figure 7 illustrates the receive operations in AUTO·
mode. The overall operation is shown in Figure 7a. Particular cases are illustrated in Figures 7b through 7j. If
any Unnumbered Command other than UP is received,
the AM bit is cleared and the SIU responds as if in the
FLEXIBLE mode, by interrupting the CPU for supervision. This will also happen if a BOV or SES condition
occurs. If the received. frame contains a poll, the SIU
sets the RTS bit to generate a response.
Figure 8 illustrates the transmit operations in AUTO
mode. When the SIU gets the opportunity to transmit,
and if the transmit buffer is full, it sends an I-frame.
Otherwise, it sends an RR if the buffer is free, or an
RNR if the buffer is protected. The sequence counters
NS and NR are used to construct the appropriate control fields.
Figure 9 shows how the CPU respoilds to an SI (serial
interrupt) in AUTO mode. The CPU tests the AM bit
(in the STS register), If AM = I, it indicates that the
SIU has receivc:d either an I-frame, or a positive response to a previously transmitted I-frame.

2) In a non-loop configuration, one to eight extra dribble bits are transmitted after the closing flag. These
bits are a zero followed by ones.
3) In a loop configuration, when a GA is' received and
the 8044 begins transmitting, the sequence is
01111110101111110 ... (FLAG, I, FLAG, ADDRESS, etc.). The first flag is created from the GA.
The second flag begins the message.
4) CTS is sampled after the rising edge of the serial
data, at about the center of the bit cell, except during a non-loop, externally clocked mode transmit, in
which case it is sampled just after the falling edge.
5) The SIU does not check for illegal I-fields. In particular, if a supervisory command is received in AUTO
mode, and if there is also an I-field, it will be loaded
into the receive buffer (if RBP = 0), but it cannot
cause a BOV.
6) In relation to the Receive Buffer Protect facility, the
user should set RFL to 0 when clearing RBP, such
that, if the SIU is in the process of receiving a
frame, RFL will indicate the proper value when reception of the frame has been completed.

8.5 Turn Around Timing
8.3 FLEXIBLE Mode
Figure 10 illustrates the receive operations in NONAUTO mode. When the SIU successfully completes a
task, it clears RBF and interrupts the CPU by setting
SI to 1. The exact CPU response to SI is determined by
software. A typical response is shown in Figure 11.
Figure 12 illustrates the transmit operations in FLEXIBLE mode. The SIU does not wait for a positive acknowledge response to the transmitted frame. Rather, it
interrupts the CPU (by setting SI to 1) as soon as it
finishes transmitting the frame. The exact CPU response to SI is determined by software. A typical response is shown in Figure 13. This response results in
another transmit frame being set up. The sequence of
operations shown in Figure 13 can also be initi.ated by
. the CPU, without an SI. Thus the CPU can initiate a
transmission in FLEXIBLE mode without a poll, simply by setting the RTS bit in the STS register. The RTS
bit is always used to initiate a transmission, but it is
applied to the RTS pin only when a non-loop configuration is used.

8.4 8044 Data Link Particulars
The following facts should be noted:
1) In a non-loop configuration, one or two bits are
transmitted before -the opening flag. This is necessary for NRZI synchronization.

In AUTO mode, the SIU generates an RTS immediately upon being polled. Assuming that the 8044 sends an
information frame in response to the poll, the primary
station sends back an acknowledgement. If, in this acknowledgement, the 8044 is polled again, a response
may be generated even before the CPU gets around to
processing the interrupt caused by the acknowledge. In
such a case, the response would be an RR (or RNR),
since TBF would have been set to 0 by the SIU, due to
the acknowledge.
IT the system designer does not wish to take up channel
time with RR responses, but prefers to generate a new
I-frame as a response, there are several ways to accomplish this:
1) Operate the 8044 in FLEXIBLE mode.
2) Specify that the master should never acknowledge
and poll in one message. This is typically how a loop
system operates, with the poll operation confined to
the UP command. This leaves plenty of time for the
8044 to get.its transmit buffer loaded with new information after an acknowledge.
3) The 8044 CPU can clear RTS. This will prevent a
response from being sent, or abort it if it is already
in progress. A system using external RTS/CTS
handshaking could use a. one-shot delay RTS or
CTS, thereby giving the CPU more time to disable
the reSponse.

13-14

RUPITM~44

SIU

RECEIVE
NEXTBYTE

NO

AlIORT, SHORT FRAME,
OR INVALID

I FRAME

CTRL FIELD .. RCI

NO

YES

I'IELD .. RFC aUF

lAO

s •• Figure, 7c thru 7)

296165-10

Figure 7a. SIU AUTO Mode Receive Flowchart-General

13-15

inter

RUPITM~44

SIU

uAM" ......
uSI" -4-1
"RBE tI. . - •

..SES......

uSER"~'

296165-11

Figure 7b. SIU AUTO Mode Receive Flowchart-Unknown Command

13-16

RUPITM·44 SIU

.IIAMn~o

"RBE"..-O
"SI" .... 1

296165-12

Figure 7c. SIU AUTO Mode Receive Flowchart-Unnumbered Poll
13-17

inter

RUPITM·44 SIU

NO

296165-13

Figure 7d. SIU AUTO Mode Receive Flowchart--Supervlsory Command

13-18

inter

RUPITM_44 SIU

BAD

I COMMAND

NRi~
NllSl +
N P --NRS

,,~ '- 1,

1

"Na" - •

"RBE"_'
"TBF"_'

Ns-Ns+1

"5ES"_.
"SER"_'
"SI" _1

296165-14

Figure 7e. SIU AUTO Mode Receive Flowchart-I Command: Prior
Transmitted I-Field Confirmed, Current Received I-Field In Sequence

13-19

intJ

RUPITM·44 SIU

BAD

ICpMMAND

NRIP) ~ HsIS)
HsIP) ~ HRIS)
"AM" = ,,"Nan ....

.. RBE...... .
.. SES...... .
.. SER ...... .
"SI" .... 1

296165-15

Figure 7f. SIU AUTO Mode Receive Flowchart-I Command: Prior..
Transmitted I-Field Not Confirmed, Current Received I-Field In Sequence
13-20

intJ

RUPITM·44 SIU

BAD

I COMMAND

NAIP) " NsIS) +
NRIP) '" NsIS)
NsIP) - NAIS)

"AM" - "

"NB"

,

=0

"AM" ....

"SES"-+-'
"SER"-+-O
"RBE"_O
"51" ... ,

296165-16

Figure 7g. SIU AUTO Mode Receive Flowchart-I Command:
Sequence Error S",nd, Current Received I·Fleld In Sequence
13-21

inter

RUPITM-44 SIU

BAD

I COMMAND
NR(P) - NS(S) + 1
NS(P) .. NR(S)
"AM" = 1, "NB" = 0

.. BOV..... 1

"AM" ....

..RBE.. ·....

"TBF"_.

NS~NS+l

"SES"_'

"SER" .... 1
"SI" _1

296165-17

Figure 7h. SIU AUTO Mode Receive Flowchart-I Command:
Prior Transmitted I-Field Confirmed Sequence Error Receive

13-22

RUPITM·44 SIU

BAD

I COMMAND
NRIP) - NsIS)
NsIP) .. NRIS)
"AM" "'" 1,
"NB" = 0

"BOY"_1
"AM" _ _
"RBE" . . _

"AM" _ _

"RBE" _ _
uSI"

SI

-4-1

_1

296165-18

Figure 7i. SIU AUTO Mode Receive Flowchart-I Command:
Prior Transmitted I·Field Not Confirmed, Sequence Error Receive

13-23

inter

RUPITM·44 SIU

BAD

I COMMAND

HAIPI"
Ha\SI + 1
NRP "NaS

NaIP)" NR P)
"AM" - 1. nNB" .. 0

UAM" ....

"RBE"'-'
"SES"'-l

"SER"~1

1181"

..... 1

296165-19

Figure 7J. SIU AUTO Mode Receive Flowchart-I Command:
Sequence Error Send and Sequence Error Receive

13·24

intJ

RUPITM·44 SIU

X MIT
I

FRAME

X MIT
RR
FRAME

X MIT
RNR
FRAME

296165-20

Figure 8. Siu AUTO Mode Transmit Flowchart

13-25

RUPITM-44 SIU

LOAD I-FIELD
INTO
XMITBUFFER

PROCESS
INFORMATION
OR
SET "RBP"

296165-21

Figure 9. AUTO Mode Response to "SI"

13-26

inter

RUPITM_44 SIU

RECEIVE
NEXT BYTE

-----j

NO

YES

ABORT,
SHORT FRAME
OR INVALID I

RECEIVE MESSAGE
CTRL FIELD ....RCB,
I FIELD .... REC BUF,
SET BOV ON OVERRUN

-

-

-

I
I
I
I
I RBE ~.
.... (ABORT FROM CPU)

BAD

GOOD

CLEAR "RBE"
SET "SI"

L----------toII-------...J

296165-22

Figure 10. SIU FLEXIBLE Mode Receive Flowchart

13-27

inter

RUPITM-44 SIU

PROCESS MESSAGE,
SeT UP RESPONSE

IF NECESS;ARY

296165-23

Figure 11. FLEXIBLE Mode Response to Receive "51"
13-28

inter

RUPITM-44 SIU

TRANSMIT MESSAGE
USING TCB FOR
CONTROL FIELD

r - - - - -=.- - -

I
I

TBF
(ABORT FROM CPU)

~UT-OFF - LOOP) +
CTS-LOOP
[ABORT FROM PRIMARY]

----,

I
I
I
I
I

~
CLEAR "TBF"

~=~l_ _~_ _ _ _ _ _ _ _~~~~~

______

J

CLEAR "RTS"
SET "SI"
TRANSMIT
ABORT
SEQUENCE

296165-24

Figure 12. SIU FLEXIBLE Mode Transmit Flowchart

13-29

inter

RUPITM·44 Slu

CLEAR"SI"

lIMIT
= I,PENDING

BUFFULL

TBF INDICATEB
LAST TRANSMIT
ABORTED IV CPU
ORPR_V.

BUFEMPTY

CTRL FIELD . .TCI
I-FIELD .. XMIT aUF
SET"TI"
SET "ATS·

296165-25

FIgure 13" FLEXIBLE Mode Re.ponse to Transmit "SI" .

13·30

intJ

RUPITM-44 SIU

9.0 MORE DETAILS ON SIU
HARDWARE
The SIU divides functionally into two sections-a bit
processor (BIP) and a byte processor (BYP~haring
some common timing and control logic. As shown in
Figure 14, the BIP operates between the serial port pins
and the SIU bus, and performs all functions necessary
to transmit/receive a byte of data to/from the serial
data stream. These operations include shifting, NRZI
encoding/decoding, zero insertion/deletion, and FCS
generation/checking. The BYP manipulates bytes of
data to perform message formatting, and other transmitting and receiving functions. It operates between the
SIU bus (SIB) and the 8044's internal bus (IB). The
interface between the SIU and the CPU involves an
interrupt and some locations in on-chip RAM space
which are managed by the BYP.
The maximum possible data rate for the serial port is
limited to '12 the internal clock rate. This limit is imposed by both the maximum rate of DMA to the onchip RAM, and by the requirements of synchronizing
to an external clock. The internal clock rate for an 8044
running on a 12 MHz crystal is 6 MHz. Thus the maximum· 8044 serial data rate is 3 MHz. This data rate
drops down to 2.4 MHz when time is allowed for external clock synchronization.

9.1 The Bit Processor
In the asynchronous (self clocked) modes the clock is
extracted from the data stream using the on-chip digital
phase-locked-loop (DPLL). The DPLL requires a clock
input at 16 times the data rate. This 16 X clock may
originate from SCLK, Timer 1 Overflow, or PH2 (one
half the oscillator frequency). The extra divide by-two
described above allows these sources to be treated alternatively as 32 X clocks.
The DPLL is a free-running four-bit counter running
off the 16 X clock. When a transition is detected in the
receive data stream, a count is dropped (by suppressing
the carry-in) if the current count value is greater than 8.
A count is added (by injecting a carry into the second
stage rather than the first) if the count is less than 8. No
adjustment is made if the transition occurS at the count
of 8. In this manner the counter locks in on the point at
which transitions in the data stream occur at the count
of 8, and a clock pulse is generated when the count
overflows to O.

The zero insert/delete circuitry (ZID) performs zero
insertion/deletion, and also detects flags, GA's (GoAhead's), and aborts (same as GA's) in· the data
stream. The pattern 1111110 is detected as an early
GA, so that the GA may be turned into a flag for loop
mode transmission.
The shut-off detector monitors the receive data stream
for a sequence of eight zeros, which is a shut-off command for loop mode transmissions. The shut-off detector is a three-bit counter which is cleared whenever a
one is found in the receive data stream. Note that the
ZID logic could not be used for this purpose, because
the receive data must be monitored even when the ZID
is being used for transmission.
As an example of the operation of the bit processor, the
following sequence occurs in relation to the receive
data:
1) RXD is sampled by SCLK, and then synchronized
to the internal processor clock (IPC).
2) If the NRZI mode is selected, the incoming data is
NRZI decoded.
3) When receiving other than the flag pattern, the ZID
deletes the '0' after 5 consecutive 'l's (during transmission this zero is inserted). The ZID locates the
byte boundary for the rest ofthe circuitry. The ZID
deletes the 'O's by preventing the SR (shift register)
from receiving a clocking pulse.
4) The FCS (which is a function of the data between
the flags-notincluding the flags) is initialized and
started at the detection of the byte boundary at the
end of the opening flag. The FCS is computed each
bit boundary until the closing flag is detected. Note
that the received FCS has gone through the ZID
during transmission.

9.2 The Byte Processor
Figure 15 is a block diagram of the byte processor
(BYP). The BYP contains the registers and controllers
necessary to perform the data manipulations associated
with SDLC communications. TheBYP registers may
be read or written by the CPU over the 8044's internal
bus (IB), using standard 8044 hardware register operations. The 8044 register select PLA controls these operations. Three of the BYP registers connect to the IB
through the IBS, a sub-bus which also connects to the
CPU interrupt control registers.

In order to perform NRZI decoding, the NRZI decoder compares each bit of input data to the previous bit.
There are no clock delays in going through the NRZI
decoder.
.

13-31

RUPITM·44 SIU

INTERRUPT
IB'

1
CPU

RAM

r

-

---- ------- i-------------Siij..,

-1
-

SHARED
REGISTERS

~
BIP

BYP
SIB

L _____________

~

_________

I
I
I
I
I
I
I
I

1/01RXD
DA'J:AITXD

~---J

296165-26

Figure 14. The Bit and Byte Processors

Simultaneous access of a register by both the IB and the
SIB is prevented by timing. In particular, RAM access
is restricted to alternate internal processor cycles for
the CPU and the SIU, in such a way that collisions do
not occur.
As an example of the operation of'the byte processor,
the following sequence occurs in relation to the receive
data:
1) Assuming that there is an address field in the frame,
the BYP takes the station address from ihe regist~
me into temporary storage. After the opening flag,
the next field (the address field) is compared to the
station address in the temporary storage. If a match
occurs, the operation continues.

2) Assuming that there is a control field in the frame,
the BYP takes the next byte and loads it into the
RCB register. The RCB register has the logic to
update the NSNR register (increment receive count,
set SES and SER flags, etc.).
3) Assuming thatthere is an information field, the next
byte is dumped into RAM at the RBS location. The
DMA CNT (RBL at the opening flag) is loaded
from the DMA CNT register into the RB register
and decremented. The RFL is then loaded into the
RB register, incremented, and stored back into the
register me.
4) This process continues until the DMA CNT reache~
zero, or until a closing flag is received. Upon either
event, the BYP updates the status, and, if the CRC
is good, the NSNR register.

13·32

intJ

RUPITM·44 SIU

Ir----~----------,

RAM

SIB

BYP

IB

SHARED
REGISTERS

TIMING

AND

CONTROL

I

I
I
~

L ______________

I
I
~~

296165-27

Figure 15. The Byte Processor

10.0 DIAGNOSTICS
An SIU test mode has been provided, so that the onchip CPU can perform limited diagnostics on the SIU.
The test mode utilizes the output latches for P3.0 and
P3.1 (pins 10 and II). These port 3 pins are not useful
as out-put ports, since the pins are taken up by the
serial port functions. Figure 16 shows the signal routing
associated with the SIU test-mode.
Writing a 0 to P3.1 enables the serial test mode (P3.1 is
set to I by reset). In test mode the P3.0 bit is mapped
into the received data stream, and the 'write port 3'
control signal is mapped into the SCLK path in place of
TI. Thus, in test mode, the CPU can send a serial data

stream to the SIU by writing to P3.0. The transmit data
stream can be monitored by reading P3.1. Each successive bit is transmitted from the sm by writing to any
bit in .Port 3, which generates SCLK.
In test mode, the P3.0 and P3.1 pins are placed in a
high voltage, high impedance state; When the CPU
reads P3.0 and P3.1 the logic level applied to the pin
will be returned. In the test mode, when the CPU reads
3.1, the transmit data value will be returned, not the
voltage on the pin. The transmit dilta remains constant
for a bit time. Writing to P3.0 will result in the signal
being outputted for a short period of time. However,
since the signal is not latched, P3.0 will quickly return
to a high voltage, high impedance state.

13-33

.~. ..
!J
'5

SCLKI

~_'_-r_IQ-~~-~-H~DI_·~

1

----'

~.

~

I

SYSCLK

..

/1

,I

L!J
'IN1"

~

I

_,_

~§-

_.-

A
PH

.. RXDI

.~

~n ~

...

~.,..,...

....

__

~ •

c:i!:

w

~

en
2

f

READ PORT 3

PINII
DATAl

TXDI
P31

l

WRITE PORT 3
SlU

TRANSMIT
DATA
STREAM

296165-28

inter

RUPITM_44 SIU

The serial test mode is disabled by writing a I to P3.1.
Care must be taken that a 0 is never written to P3.1 in
the course of normal operation, since this causes the
test mode to be entered.

transmits a supervisory frame. This frame consists of an
opening flag, followed by the station address, a control
field indicat~g that this is a supervisory frame with an
, RNR command, and then a closing flag.

Figure 17 is an example of a simple program segment
that can be imbedded into the user's diagnostic program. That example shows how to put the 8044 into
"Loop-back mode" to test the basic transmitting and
receiving functions of the SIU.

Each byte of the frame is transmitted by writing that
byte into the A register and then calling the subroutine
XMIT8~ Two additional SCLKs are generated to guarantee that the last bits in the frame have been clocked
into the SIU. Finally the CPU reads the status register
(STS). If the operation has proceeded correctly, the
status will be 072H. If it is not, the program jumps to
the ERROR loop and terminates.

Loop-back mode is functionally equivalent to a hardwire connection between pins 10 and 11 on the 8044.
In this example, the 8044 CPU plays the role of the
primary station. The SIU is in the AUTO mode. The
CPU sends the SIU a supervisory frame with the poll
bit set and an RNR command. TheSIU responds with
a supervisory frame with the poll bit set and an RR
command.
The operation proceeds as follows:
Interrupts are disabled, and the self test mode is enabled by writing a zero to P3.1. This establishes P3.0 as
the data path from the CPU to the SIU. CTS (clear-tosend) is enabled by writiIjg a zero to P1.7. The station
address is initialized by writing 08AH into the STAD
(station address register).
The SIU is configured for receive operation in the
clocked mode and in AUTO mode. The CPU then

The SIU generates an SI (SIU interrupt) to indicate
that it has received a frame. The CPU clears this interrupt, and then begins to monitor the data stream that is
being generated by the SIU in response to what it has
received. As each bit arrives (via P3.1), it is moved into
the accumulator, and the CPU compares the byte in the
accumulator with 07EH, which is the opening flag.
When a match occurs, the CPU identifies this as byte
boundary, and thereafter processes the information
byte-to-byte.
The CPU calls the RCV8 subroutine to gct each byte
into the accumulator. The CPU performs compare oper~tions on (successively) the station address, the control field (which contains the RR response), and the
closing flag; If any of 'these do not compare, the program jumps to the ERROR loop. If no error is, found,
the program jumps to the DONE loop.

13-35

inter

RUPITM.-44 SIU

, ISIS-II PICa-51 .....CRD .AS_I-ER 112,.0 .
DI~CT IIODULE PLACED IN· : Fl : DATA, DB"
ASSEttI.LIER 'INVOKED ,IV:
.... 51: ,flo: ... t •. un d.vic.(44)
LDC

0000
. DDQ3
0005
0007

DB"

7SCaOO
C211
C297
7SCEBA

OODA "7'D86~
DODD 7,C901

0010 7'CaC2

0013
0015
oole
OOIA
OOID
OOIF
0022
0024
0027
0029

747E
1200..6
74....
120066
7495
120066
747E
120066
D210
D210

002a E,eB
002D 14722A

0030 ·C2CC
0032 7400.
0034 710C

0036
0038
003A
0031
OOlE
0041
0043

D210
A211
13
147E03
0:10046
DIF3
0200"'"

0046 1200SC
004914_
004C 1200SC
oo4F 141108
0052 I:IOOSC
0055 147E02
005e aOFE
00"," 80FE
OO5C
oo5E
0060
0062
0063
0065

7808
D2ao
A211
13
D8F9
22

0066 780"
0068 13
006" DBOI

0068 22
006C 4004

006E C2BO
0070 BOF6
007~ D280
0074 8OF2

LIN!'
I'
2
'3
4
5
6
,7
8
9
10
11
12
13
14·
15
16
17
18
19
20
21
22
23
24
25
'.26
27
28

SOURCE

INIT:

J'

MOIl
CLR
,CLR
.II1I\I

36
37
38
39
40
41
42
43
44
45
46
47
48
49

11011
II1I\I
ICIII

Int tiel i Ie .eld" •••

NSCS)-3; SES-C. NR(9)-,. SER-O

NBHR • • •AH
BI1D, eolH
aTB. eOC2H

NFee-t
J

TIF-l. RIE-l, Nt-l

TRMSI1IT A _ERIiISORV FR_ FRDI1 THE PRII1M~ STATION WITH.THE POLL.
S~N~:

ICI\I
CALL
11011
CIILL

II1I\I
CIILL
11011
" CIILL
SETa
··8ETI
"Oil
CJNE

A. 17EH
XI1ITS
A. laAH
XI'IIT&
A. 1095H
XI'IIT8
A. 17EH

Th. SIU rec .. i V.I

..

ne. ftT's.'"

,

The .dd" ••• is n •• t

,
,

Receive clasing fie.

RNIt SUP FANE with P/F-l. NRCP)-4

1"IT8

t".

P3,O
P3,O

O.n.".t •••
SCUV. to
Initiate "eceive acUon

It.,i 8T9
A. .72H. ERROR

Chec II '0" .p,,,o,,,i.te st.tus

; PREPIt.RE TO RECEIVE RUP!'. RESPONCE TO PRI"lt.Ry·S RNA

CLA

REClio

Cl •• " II
.Cl •• " ACC
I T"II l2 ti •••

IlO\l
ICI\I
LIIOK. FOR THE OPENING FLAO
WFLIIO I: :SETB

1'1011

. ', RRC

C.JNE
JI'ff'
WFLO I :

D.JNZ
JI1P

CNTINU: CALL

51
52
53
54

C"NE

57
58
5.
60
61
62
63
64
65
66
67
68
6"
70
71
72
73
74
75
76
77
7a
79
80
81
82
83

Enebl. ,.U t •• t Mod.
En.bl. eTa

J

8 IT SET AND A RNA CDI1IIAND

50

"56

I

PI.7
'STAD. lBAH

CONFIGURE RECEIVE OPERATION

29
30
31
32
33
34
35

. BTS.IOOH
P3,I

CALL
C"NE
CALL
C"NE

P3.0

I SCL.M.'

C, P3.1

I

T".n •• itt.1I d.t•

A
AI .07EH. WFLO 1
CNTINU
R3. WFLAOI
ERROR
RCIIB
A. 1000H. ERROR
RCIIB
A. 10BlH. ERROR
RCIIS
A. 107EH. ERROR

DONE:

"11P

DONE

ERROR:

JI1P

ERROR

RCIIB:
OETB I T:

11011
SETB
11011
RRC
DJNZ
RET

RO.108
P3,O
C. P3, I

O.t SIU'. T".n •• itted .dd" ••• U.U

, P"'··"II

e.pect. ta ,..eceiv. RR

'''D.

SIU

Receive clasing fl ••

, In' tieU I. the, b" cDunt."
SCLK
I

T"e".1111 tted d.t.

A
RO.

OETIIT

84

296165-29

Figure 17. Loop-Back Mode S~ftware
13-36

8044 Application Examples .

14

8044 APPLICATION EXAMPLES
ure 3 shows the 8088 and support circuitry; the memory and decoders are not shown. It is a basic 8088 Min
Mode system with an 8237A DMA controller and an
8259A interrupt controller.

1.0 INTERFACING THE 8044 TO A
MICROPROCESSOR
The 8044 is designed to serve as an intelligent controller for remote peripherals. However, it can also be used
as an intelligent HDLC/SDLC front end for a microprocessor, capable of extensively off-loading link control functions for the CPU. In some applications, the
8044 can even be used for communications preprocessing, in addition to data link control.
This section describes a sample hardware interface for
attaching the 8044 to an 8088. It is general enough to
be extended to other microprocessors such as the 8086 .
or the 80186.
OVERVIEW

A sample interface is shown in Figure 1. Transmission
occurs when the 8088 loads a 64 byte block of memory
with some known data. The 8088 then enables the
8237A to DMA this data to the 8044. When the 8044
has received all of the data from the 8237A, it sends the
data in a SDLC frame. The frame is captured by the
Spectron Datascope™* which displays it on a CRT in
hex format.
In reception, the Datascope sends a SDLC information
frame to the 8044. The 8044 receives the SDLC frame,
buffers it, and sends it to the 8088's memory. In this
e~ample the 8044 is being operated in the NON-AUTO
mode; therefore, it does not need to be polled by a primary station in order to transmit.

DMA Channel One transfers a block of memory to the
tri-state latch, while Channel Zero transfers a block of
data from the latch to 8088's memory. The. 8044's Interrupt 0 signal vectors the CPU into a routine which
reads from the internal RAM and writes to the latch.
The 8044's Interrupt 1 signal causes the chip to read
from the latch and write to its on-chip data RAM. Both
DMA requests and acknowledges are active low.
Initially, when the power is applied, a reset pulse coming from the 8284A initializes the SR flip-flops. In this
initialization state, the 8044's transmit interrupt and
the 8088's transmit DMA request are active; however,
the software keeps these signals disabled until either of
the two processors are ready to transmit. The software
leaves the receive signals enabled, unless the receive
buffers are full. In this way either the 8088 or the 8044
are always ready to receive, but they must enable the
transmit signal when they have prepared a block to
transmit. After a block has been transmitted or received, the DMA and interrupt signals return to the
initial state.
The receive and transmit buffer sizes for· the blocks of
data sent between the 8044 and the 8088 have a maximum fixed length. In this case the buffer size was 64
bytes. The buffer size must be less than 192 bytes to
enable 8044 to buffer the data in its on-chip RAM. This
design allows blocks of data that are less than (i4 bytes,
and accommodates networks that allow frames of varying size. The first byte transferred between the 8088
and the 8044 is the byte count to follow; thus the 8044
knows how many bytes to receive before it transmits
the SDLC frame. However, when the 8044 sends data
to the 8088's memory, the .8237A will not know if the
8044 will send less than the count the 8237A was programmed for. To solve this problem, the 8237A is operated in the single mode. The 8044 uses an I/O bit to
generate an interrupt request to the 8259A. In the
8088's interrupt routine, the 8237A's receive DMA
channel is disabled, ~us allowing blocks of data less
than 64 bytes to be received.

THE INTERFACE
The 8044 does not have a parallel slave port. The
8044's 32 I/O lines can be configured as a local micro.processor bus master. In this configuration, the 8044
can expand the ROM and RAM memory, control peripherals, and communicate with a microprocessor.
The 8044, like the 8051, does not have a Ready line, so
there is no way to put the 8044 in wait state. The clock
on the 8044 cannot be stopped. Dual port RAM could
still be used, however, software arbitration would be
the only way to prevent collisions. Another way to interface the 8044 with another CPU is to put a FIFO or
queue between the two processors, and this was the
method chosen for this design.

THE SOFTWARE

The software for the 8044 and the 8088 is shown in
Table 1. The 8088 software was written in PL/M86,
and the 8044. software was written in assembly language.

Figure 2 shows the schematic of the 8044/8088 interface. It involves two 8-bit tri-state latches, two SR flipflops, and some logic gates (6 TTL packs). The circuitry implements a one byte FIFO. RS422 transceivers are
used, which can be connected to a multidrop link. Fig-

The 8044 software begins by initializing the stack, interrupt priorities, and triggering types for the interrupts. At this point, the SIU parameter registers are

*Datascope is a trademark of Spectron Inc.

14-1

inter

RUPITM_44

DATASCOPE
296166-1

Figure 1. Block Diagram of 8088/8044 Interface Test
initialized. The receive and transmit buffer starting addresses and lengths are loaded for the on-chip DMA.
This DMA is for the serial port. The serial station address and the transmit control bytes are loaded too.
Once the initialization has taken place, the SIU interrupt is enabled, and the external interrupt which· receives bytes from the 8088 is enabled. Setting the 8044's
Receive Buffer Empty (RBE) bit enables the receiver. If
thiS bit is reset, no serial data can be received. The 8044
then waits in a loop for either RECEIVE DMA interrupt or the SERIAL INT interrupt.
The RECEIVE DMA interrupt occurs when the
8237A is transferring a block of data to the 8044. The
first time this interrupt occurs, the 8044 reads the latch
and loads the count value into .the R2 register. On subsequent interrupts, the 8044 reads the latch, loads the
data into the transmit buffer, and decrements R2.
When R2 reaches zero, the interrupt routine sends the
data in an SDLC frame, and disables the RECEIVE
DMA interrupt. After the frame has been transmitted,
a serial interrupt is generated. The SERIAL INT routine detects that a frame has been transmitted and reenables the RECEIVE DMA interrupt. Thus, while the
frame is being transmitted through the SIU, the 8237A
is inhibited from sending data to the 8044's transmit
buffer.
.

NormaIly this interrupt remains disabled. However, if a
serial interrupt occurs, and the SERIAL INT routine
detects that a frame has been received, it caIls the
SEND subroutine. The SEND subroutine loads the
. number of bytes which were received in the frame into
the receive buffer. Register RI points to the receive
.buffer and R2 is loaded with the count. The TRANSMIT DMA interrupt is enabled, and immediately upon
returning from the SERIAL INT routine, the interrupt
is acknowledged. Each time the TRANSMIT DMA interrupt occurs, a byte is read from the receive buffer,
written to the latch, and R2 is decremented. When R2
reaches 0, the TRANSMIT DMA interrupt is disabled,
the SIU receiver is re-enabled, and the 8044 interrupts
the 8088.

.CONCLUSION
For the software shown in Table I, the transfer rate
from the 8088's memory to the 8044 was measured at
75K bytes/sec. This transfer rate largely depends upon
the number of instructions in the 8044's interrupt service routine. Fewer instructions result in a higher transfer rate.
There are many ways of interfacing the 8044 loca1ly to
another microprocessor: FIFO's, dual port RAM with
software arbitration, and 8255's are just a few. Alternative approaches, which may be more optimal for certain
applications, are certainly possible.

The TRANSMIT DMA routine sends a block of data
from ·the 8044's receive buffer to the 8088's ~emory.
14-2

l
DACKI

"'II

c'
c
iil

!"

:g .
....
....

:D

-

c:

..... 5'

....•
Co)

'U

~

CD
::l.

~

•••

DACK,

CD

0'

if
CD

g

CD

Vee

RUPI EXPANSION BUS

2128
PI

296166-2

l

·s
CS

"''''''

~

~

OBOOOFOH

B3 6520

rr:==~:j:~
g~03
SEL
A3
04

PCLK

MEMR
lOR
MEMW

M~

CLK

~

"1\

iFi
c

~

+5V

B1 5257
~ 03

~

M~

{~

;

r---~------------------------~8237CS

r----i> +5V

~
CO

- 0 RESET

g
.....
.j>.

.P..

CO

+5

3C
S"

~

g-

j
3

~

...,b-:==.......Ir--.
~ITn~~t~!f::~====~3~~~~ HlDA
HOLO
ALE
CLK

DACK.
DREQt
g~~~
DREQ2
OACK2
OREQ3

Dt
8237-2

RESEli

DACK.
DREQt
g:~~l
DREQ2
OACK2

r

li

r========~STB~-JOE""--'
g:: gg:

AD7

(MIN)

::

B =
TEST

~g~

INTR

A15A~ll1~ADt

017

g:;
gl~

D07

F1
N

AO-A7
J1

~

:s gw,

Ott ..

Dot

-ooo-D7

((((((((

~

•

...J.

OESTB~
~~~

DI7

007

015
014

DOS
004

N

l{

D~M

'

g~; gg~
011

DOl

Ott

Oot1J

~
I

~

8088

"U
01lio
01lio

INTR
NMI

XI

c:

296166-3

intJ

RUPITM-44

37
0058 85CD29
005B 7929
005D AACD
005F OA
0060 D2A8
0062 22

0063
0013
0013 020063
0063

38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
S4
55

;••••••••••••••••••••••••••
SEND:

MOV
MOV
MOV
INC
SETB
RET

41.RFL
RI. '41
R2. RFL
R2
EXO

.;...................
LOLTMPSET
ORG
LJMP
ORG

SUBROUTINES

•••••••••••••••••••••••••••••••

; FIRST BYTE IN BLOCK IS COUNT
; POINT TO BLOCK OF DATA
; LOAD COUNT
; ENABLE DMA TRANSMIT INTERRUPT

INTERRUPT SERVICE ROUTINES

•••••••••••••••••••••

; SET UP INTERRUPT TABLE JUMP

$

.0013H
RECEIVE_DMA
LOLTMP

RECEIVE-DMA:
296166-69

14-5

intJ

RUPITM·44

Table 1. Transmit and Receive Software.for an S044/S0SS·System (Continued)
0063 IOOOOE
0066
0067
0068
0069

EO
F6
08
DA08

006B D2CF
OO6D D2CD
006F D200
0071 C2AA
0073 32
0074 78M

56
57
58
59
60
61
62
63
64
65
66
67
68
69 .
70
71

JBC

FIRSLBYTE. LI ; THE FIRST BYTE TRANSFERRED IS THE COUNT

MOVX A.@DPTR
MOV
@RO.A
INC
RO
DJNZ
R2.L2
SETB
SETB
SETB
CLR

0079
0003
0003 020079
0079

0079
007A
0078
007C

E7
FO
09
DA08

007E
0080
0082
0084

C2A8
C294
D294
D2CE

0086 32

0087
0023
0023 020087
0087

0087 3OCE06·
008A 30CFOB
008D 020056
00902OCBC3
0093 1158
0095 C2CC
0097 32
0098 C2CC

73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110

;SEND DATA

; RO IS A POINTER TO THE TRANSMIT
; BUFFER STARTING ADDRESS
; PUT THE FIRST BYTE INTO
; R2 FOR THE COUNT

L2:

RETI

1I: .

MOY

RO.lI06

.MOYX
MOY
RETI

A.@DPTR
R2. A

. $
LOLTMPSET
ORG
ooom
LJMP
TRANSMILDMA
ORG
LOLTMP

TRANSMILDMA

13:

MOV
A.@RI
MOVX .@DPTR.A
INC
RI
DJNZ
R2.13

; READ BYTE OUT OF THE RECEIVE BUFFER
; WRITE IT TO THE LATCH

ClR
CLR
SETB
SETB

; DISABLE INTERRUPT
; CAUSE 8088 INTERRUPT TO TERMINATE DMA

IE.O
PI.4
PI. 4
RBE

; WHEN ALL 8YTES HAVE. BEEN SENT

; ENABLE RECEIVER AGAIN

RETI

LOC-T~PSET

ORG
LJMP
ORG

S
0023H
SERIALINT
LOC-TMP

SERIALINT:
JNB
JNB
LJMP

RBE.RCV
TBF.XMIT
ERROR

RCV:

JB
CALL
CLR
RETI

BOV.ERROR
SEND.
SI

XMIT:

CLR

SI

III

112
113
114

; AFTER READING BYTES.

TBF
RTS
FIRSLBYTE
EXI

72

0076 EO
0077 FA
0078 32

; READ THE LATCH
; PUT IT IN TRANSMIT BUFFER

; WAS A FRAME RECEIVED
; WAS A FRAME TRANSMITTED
; IF NEITHER ERROR
; IF BUFFER OVERRUN THEN ERROR
. ; SEND THE FRAME TO THE 8088

296166-70

14-6

inter

RUPITM-44

Table 1. Transmit and Receive Software for an 8044/8088 System (Continued)
009A D2AA
009C 32

SETB
RET!

115
116
117
lIB

EXI

END

SYMBOL TABLE LISTING

-

NAME

TYPE

VALUE

BOV
ERROR
EXO
EXI
FIRSLBYTE
IE
INIT
IP

B
C
B
B
B
D
C
D
C
C
C
C
D
B
D
D
C
C
D
B
C
C
B
D
D
D
B
D
D
D
D
D
D
C
C

OOCBH.3
0056H
OOABH.O
OOABH.2
0020H.O
OOABH
0026H
OOBBH
0074H
0073H
00B6H
00B7H
0090H
00CBH.6
OOCBH
OOCCH
0090H
0063H
OOCDH
OOCBH.5
005BH
0087H
OOCBH.4
00C9H
0081H
OOCEH
00C8H.7
OODBH
OODCH
OODAH
0088H
008DH
0089H
0079H
009BH

LI
l2
L3
lOCTMP
PI
RBE
RBl
RBS
RCV
RECEIVLDMA
RFl
RTS
SEND
SERIALINT
SI
SMD
SP
STAD
TBF
TBl
TBS
TCB
TCON
THI
TMOD
TRANSM IT_DMA
XMIT

ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
AD DR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR

ATTRIBUTES

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

A
A
A
A
A
A
A
A
A
A
A
A

REGISTER BANK(S) USED: 0, TARGET MACHINE(S): 8044
ASSEMBLY COMPLETE, NO ERRORS FOUND
296166-71

14-7

inter

RUPITM-44

Table 2. PL/M-86 Compiler RUPI/8088 Interface Example
SERIES-III PL/~-B6 Vl.0 CO~PILATION OF ~ODULE RUPI_BB
OBJECT ~ODULE PLACED IN :Fl:RBB.OBJ
CO~PILER INVOKED BY:
PL~B6.B6 :Fl:RBB.SRC

.DEBUg
.TITLE

C'RUPI/BOBB INTERFACE

EXA~PLE')

DECLARE

2

LIT
TRUE
FALSE

LITERALLY
LIT
LIT

RECV_BUFFER(64)

BYTE,
BYTE,
BYTE,
BYTE,

X~IT_BUFFER(64)

I

WAIT

'LITERALLY',
'01H',

'OOH',

'* 8237 PORTS*'
I'tASTER_CLEAR_37

'OFFDDH',

CLEAR_BYTE.fTR_37

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

CHO_ADDR
CHO_COUNT
CHI_ADDR
CHI_COUNT
CH2_ADDR
CH2_COUNT
CH3_ADDR
CH3_COUNT

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

.'OFFDOH',
'OFFDIH',
'OFFD2H',
'OFFD3H',
'OFFD4H',
'OFFD:»i',
'OFFD6H',

ASSIQN~ENTS

*'

CO~AND_37
ALL_~ASK_37

SINQLE_I'tASK_37
STATUS 37
REQUEST_REg_37
~DE_REg_37

'* S237 BIT
CHO':'SEL
CHI_BEL
CH2_SEL
CH3_SEL
WRITE_XFER
READ_X FER
DEI1ANDJ10DE
SINQLEJ10DE

'OFFDBH',

'OFFDFH',
'OFFDAH',
'OFFDSH',

'OFFD9H',
'OFFDBH',
'OFFDCH',

'OFFD7H',

\ 'OOH'·,

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

BLOCK_~ODE
SET_~ASK

.'OlH',
i02H~,

'03H',

'·04H',
'OSH',

'OOH',
'40H',
'BOH~,

'04H',

,. 8259 PORTS .,

.EJECT

STATUS_POLL_59
ICWl_59
OCWl_59
OCW2_59
OCW3_59
ICW2_59
ICW3_59
ICW4_59

'OFFEOH',
'OFFEOH',
'OFFEIH',

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OFFEOH', "

'OFFEOH',
'OFFEIH',
'OFFEIH',
'OFFEIH',

,. INTERRUPT SERVICE ROUTINE .,
OFF_RECVJ)I'IA:
4

2

5

2

6

2

PROCEDURE

INTERRUPT 32,

OUTPUTCSINQLEJ1ASK_37).40H,
WAIT-FALSE,
END,
296166-4

14-8

RUPITM-44

Table 2. PL/M-86 Compiler RUPII8088 Interface Example (Continued)
7

DISABLE.
'* INITIALIZE 8237 *'

8
9
10
II

12
13
14
1:1
16
17
18
19
20
21

I
I
I
I
I
I
I
I
I
I
I
I
I
I

oUTPUTCMA8TER_CLEAR_37)
OUTPUT CCDHMAND_37)

-04OH,

OUTPUTCALL~ASK_37)

-OFH.

OUTPUTCMDDE_REg_37)
oUTPUTCMODEjREg_37)
oUTPUTCCLEAR_BYTE-PTR_37)

-0.
-C8INQLE~DE OR WRITE_XFER DR CHO_SEL),
-CSINQLE_MDDE DR READ_XFER DR CHI_SEL),
-0.

oUTPUTCCHO~DDR)

-OOH,

oUTPUTCCHO~DDR)

-40H.
-64,

OUTPUTCCHO_COUNT)
OUTPUT CCHO_CoUNT)
OUTPUTCCHI_ADDR)
oUTPUTCCHI_ADDR)
oUTPUTCCHI_COUNT)
OUTPUTCCHI_CoUNT)

-00;

-40H,
-4OH,
-64,
-00.

'* INITIALIZE 82:19 *'
22

oUTPUTCICWI_:l9)

23
24
25

OUTPUT« ICW2_:l9)
OUTPUT« ICW4_'9)
oUTPUTCoCWI_'9)

26

.E.lECT
CALL SET. INTERRUPT

27
28
29
30

-13H. '*SINgLE MODE. EDQE TRIggERED
INPUT. 8086 INTERRUPT TYPE*'
-2OH. '*INTERRUPT TYPE 32*'
-03H. '*AUTo-EoI*'
-OFEH. '*ENABLE INTERRUPT LEYEL 0*'

XMIT_BUFFERCO)-64, '*THE FIR8T BYTE IN THE BLoCK'oF DATA IS THE NUMBER
OF BYTES TO BE TRANSFERED. NOT INCLUDINg THE FIRST BYTE*'
I
2
2

DO I- I TO 64.
'* FILL UP THE XMIT-,UFFER WITH DATA *'
XMIT-,UFFERC I )-1.
END.

31

oUTPUTCALL_MASK_37)-DFCH,

32

ENABLE,

3'

33
34

I
I
2

WAIT-TRUE,
DO WHILE WAIll
END,

36
37

I

2

DO WHILE I,
END,

'*ENABLE CHANNEL I AND 2 *'

'* A BLOCK OF DATA WILL BE TRANSFERRED TO THE RUPI.
WHEN THE RUPI RECEIVES A BLOCK OF DATA IT WILL
SEND IT TO THE SOBS I1EI'IDRY AND INTERRUPT THE 8088.
THE INTERRUPT' SERYICE ROUTINE WILL SHUT OFF THE DMA
CONTROLLER AND SET 'WAIT' FALSE *'

38

CODE AREA SIZE
CONSTANT AREA SIZE
YARIABLE AREA SIZE
MAXIMUM STACK SIZE
124 LINES READ
o PRogRAM WARNINQ8
o PROgRAM ERRORS

- 00D7H
- OOOOH
-'OOS2H
- OOIEH

21:10
00
1300
300

END OF PL'M-86 COMPILATION
296166-5

14-9

inter

RUPITM·44

A HIGH PERFORMANCE NETWORK
USING THE 8044
2.0 INTRODUCTION
This section describes the design of an SOLC data link
using the 8044 (RUPI) to implement a primary station
and a secondary station. The design was implemented
and tested. The following discussion assumes that the
reader understands the 8044 and SOLC. This section is
divided into two parts. First the data link design example is discussed. Second the software modules used to
implement the data link are described. To help the
reader understand the discussion of the software, flow
charts and software listings are displayed in Appendix
A and Appendix B, respectively.

APPLICATION DESCRIPTION
This particular data link design example uses a: two
wire half-duplex multidrop topology as shown in Figure 4. In an SOLC multidrop topology the primary
station communicates with each secOndary station. The
secondary stations communicate only to the primary.
Because of this hierarchial architecture, the logical topology for an SOLC multidrop is a star as shown in
Figure 5. Although the physical topology of this data
link is multidrop, the easiest way to understand the
information flow is to think of the logical (star) topolo'gy. The term data link in this case refers !o the logi.cal
communication pathways between the pnmary station
and the secondary 'stations. The data links are shown in
Figure 5 as two way ~rows.
The application example uses dumb async termina~ to
interface to the SOLC network. Each secondary station
has an async terminal comiected to it. The secondary
stations are in etTect protocol converters which allows
any async terminal to communicate with any other
async terminal on the network. The secondary stations
use an 8044 with a UART to convert SOLC to async.
Figure 6 displays a block diagram of the data link. The
primary station, controls the data link. In addition to
data link control the primary provides a higher level
layer which is a path control function or networking
layer. The primary serves as a message exchange or
switch. It receives information from one secondary station and retransmits it to another secondary station.
Thus a virtual end to end connection is made between
any two secondary stations on the network.
Three separate software modules were.written for this
network. The first module is a Secondary Station Oriver (SSO) which provides an SOLC data link interface
and a user interface. This module is a general purpose
driver which requires application software, to run it.

The user interface to the driver provides four functions:
OPEN, CLOSE, TRANSMIT, and SIU_RECV. Using these four functions properly will allow any application software to communicate over this SOLC data link
without knowing the details of SOLC. The secondary
station driver uses the 8044's AUTO mode.
The second module is ~n example of application software which is linked to the secondary station driver.
This module drives the 8215A, butTers data, and interfaces with the secondary station driver's user interface.
The third module is a primary station, which is a standalone program (i.e., it is not linked to any other module). The primary station uses the 8044's NON-AUTO
or FLEXIBLE mode. In addition to controlling the
data link it acts as a message switch. Each time a secondary station transmits a frame, it places the destination address of the frame in the first byte of the information or I field. When the primary station receives a
frame; it removes the first byte in the I field and retransmits the frame to the secondary station whose address matches this byte.
This network provides two complete layers of the OS1
(Open Systems Interconnection) reference model: the
physical layer and the data link layer. The physical layer implementation uses the RS-422 electrical interface.
The mechanical medium consists of ribbon cable and
connectors. The data link layer is defmed by SOLC.
SOLC's use of acknowledgements and frame number- '
ing guarantees that messages will be received in the
same order in which they were sent. It also guarantees
message integrity over the data link. However this network will not guarantee secondary to secondary message delivery, since there are acknowledgements between secondary stations.

2.1 Hardware
The schematic of the hardware is given in Figure 7. The'
8251A is used as an async conimunications controller"
in support· of the 8044. TxRDY and RxROY on the
8251A are both tied to the two available external interrupts of the 8044 since the secondary station driver is
totally interrupt driven. The 8044 butTers the data and
some variables in a 2016 (2K x 8 static RAM). The
8254 programmable interval timer is employed as a
programmable baud rate generator and system clock
driver for the 8251A. The third output from the 8254
could be used as an external baud rate generator for the
8044. The 2732A shown in the diagram was not used

14-10

inter

RUPITM·44

since the software for both the primary and secondary
stations used far less than the 4K bytes provided on the
8744. For the async interface, the standard RS-232 mechanical and electrical interface was used. For the
SDLe channel, a standard two wire three state RS-422
driver is used. A DIP switch connected to one of the
available ports on the 8044 allows the baud rate, parity,
and stop bits to be changed on the async interface. The
primary station hardware does not use the USART,
8254, nor the RS-232 drivers.

2.2 SOLe Basic Repertoire
The SDLe commands and responses implemented in
the data link include the SDLe Basic Repertoire as
defined in the IBM SDLe General Information manual. Table 3 shows the commands and responses that the
primary and the secondary station in this data link design recognize and send.

PRIMARY
STATION

SECONDARY
STATION

SECONDARY
STATION

SECONDARY
STATION

296166-6

Figure 4. SDLC Multidrop Topology

SECONDARY
STATION

SECONDARY
STATION

PRIMARY
STATION

SECONDARY
STATION

SECONDARY
STATION

296166-.7

Figure 5. SDLC Logical Topology

14-11

RUPITM·44

CD

I

18

~

Figure 6. Block Diagram of the Data Link Application Example

14·12

intJ

RUPITM·44

g'
=

• •

Figure 7. Schematic of Async/SDLC Secondary Station Protocol Converter

14·13

inter

RUPITM·44

naI. The SSD is independent of the main application, it
just provides the SDLC communications. Existing 8051
applications 'could add high performance SDLC communications capability by linking the SSD to the existing software and providing additional software to be
able to communicate with the SSD.

Table 3. Data Link Commands and
Responses Implemented for This Design
Primary Station
Responses
Recognized

Commands
S.ent

UA
DM
FAMA
*AD

SNAM
DISC

Supervisory

AA
ANA

AA
ANA

Information

I

I

Unnumbered

DATA LINK INTERFACE AND USER
INTERFACE STATES
The SSD has two Software interfaces: a data link interface and a user interface as shown in Figure 8. The data
link interface is the part of the software which controls
the SDLC communications. It handles link access,
command recognition/response, acknowledgements,
and. error recovery. The user interface· provides four
functions: OPEN, CLOSE, TRANSMIT, and SIU_
RECV. These are the only four functions which the
application software has to interface in order to communicate using SDLC. These four functions are common to many I/O drivers like floppy and hard disks,
keyboard/CRT, and async communication drivers.

Secondary Station

Unnumbered

Supervisory

Information

Commands
Recognized

Responses
Sent

SNAM
DISC
·TEST

UA
DM
FAMA
*AD
"TEST

AA
ANA
AEJ

AA
ANA

I

I

The data link and the user interface each have their
own states. Each inierface can only be in one state at
any time. The SSD uses the states of these two interfaces to help synchronize the application module to the
data link.

"not included in the SOLe Basic Repertoire

The term command specifically means all frames which
the primary station transmits and the secondary sta.tions receive. Response refers to frames which the secondary stations transmit and the primary station receives.

NUMBER OF OUTSTANDING FRAMES
This particular data link design only allows one outstanding frame before it must receive an acknowledgement. Immediate acknowledgement allows the secondary station drivers to use the AUTO mode. In addition,
one outstanding frame uses less memory for buffering,
and the software becomes easier to manage.

2.3 Secondary Station Driver using
AUTO Mode
The 8044 secondary station driver (SSD) was written as
it general purpose SDLC driver. It was written to be

linked to an application module. The application software implements the actual application in addition to
interfacing to the SSD. The main application could be,
a printer or plotter, a medical instrument, or a termi-

There are three states which the secondary station data
link interface can be in: Logical Disconnect State
(L...J)J), Frame Reject State (FRMRJ), and the
Information Transfer State (I_T_S). The Logical
Disconnect State is when .a station is physically connected to the channel but either the primary or secondary have not agreed to enter the Information Transfer
State. Both the primary and the secondary stations synchronize to enter into the InfOl:mation Transfer State ..
Only when the secondary station is in the I_T_S is it
able to transfer data or information to the primary. The
Frame Reject State (FRMR-S) indicates that the secondary station has lost software synchronization with
the primary or encountered some kind of error condition. When the secondary station is in the FRMRJ,
the primary station must reset the secondary to resyncbronize.
The user interface has two states, open or closed. In the
closed state, the user program does not want to communicate overthe network. The communications chan.'
nel is closed and not available for use. The secondary
station tells the prill1ary this by responding to all commands with DM. The primary continues to poll the
secondary in case it wants to enter the I_T_S state.
When the user program begins communication over the
data link it goes into the open state. It does this by
calling the OPEN procedure. When the user interface is
in the open state it may transfer information to the
primary.

14-14

inter

RUPITM-44

SECONDARY STATION

··SECONDARY
STATION
DRIVER
MODULE

APPLICATION
MODULE

DATA
LINK
INTERFACE
SSD
INTERFACE
A

t

JI.

USER
INTERFACE

r

USER STATES

SSD
INTERFACE
PROCEDURES
OPEN
CLOSE
TRANSMIT
SIU RECV

1. OPEN
2. CLOSED

DATA LINK
STATES
1. LOGICAL
DISCONNECT
STATE
2. INFORMATION
TRANSFER
STATE
3. FRAME
REJECT
STATE

,

296166-10

Figure 8. Secondary Station Software Modules

14-15

inter

RUPITM·44

-

SECONDARY STATION COMMANDS,
RESPONSES AND STATE TRANSITIONS

Table 4 shows the commands which the secondary station recognizes and the responses it generates. The first
row in Table 4 displays commands the secondary station recognizes and each column shows the potential
responses with respect to secondary station. For example, if the secondary is in the Logical Disconnect 'State
it will only respond with DM, unless it receives a
SNRM command and the user state is open. If this is
the case, then the response will be UA and the secondary station will move into the I_T_S.

There is a buffer overrun.
The Nr that was received from the 'primary station
is invalid.

The secondary station cannot leave the FRM~S until
it receives a SNRM or a DISC command.
SOFTWARE DESCRIPTION OF THE SSD

To aid in following the description of the software, the
reader may either look at the flow charts which are
given for each procedure, or read the PL/M-Sl listing
provided in Appendix A.

Figure 9 shows the state diagram of the secondary
station. When power is first applied to the secondary
station, it goes into the Logical Disconnect State. As
mentioned above, the I_T_S is entered when the secondary station receives a SNRM command and the
user state is open. The secondary responds with UA to
let the primary know that it has accepted the SNRM
and is entering the I_T_S. The I_T_S can go into
either the L_D_S or the FRM~S. The I_T_S
goes into the L_D_S if the primary sends the secondary DISC. The secondary has to respond with UA, and
then goes into the L_D....:.S. If the user interface
changes, from open to' close state, then the secondary
. sends RD. This causes the primary to send a DISC.

A block diagram of the software structure of the SSD is
given in Figure 10. A complete module is identified by
the dotted box, and a procedure is identified by the
solid box. Therefore the SIU_RECV procedure is not
included in the SSD module, it exists in the application
software. Two or more procedures connected by a solid
line means the procedure above calls the procedure below. Transmit, Power_on_D, Close, and Open are all
called by the application software. Procedures without
, any solid lines connected above are interrupt procedures. The only interrupt procedure in the SSD module
is the SIU_INT.

The FRMR_S is entered when a secondary station is
in the I"":"T_S and either one of the following condi- ,
tions occurs.
- A command can not be recognized by the secondary station.

The entire SSD module is interrupt driven. Its design
allows the application program to handle real time
events or just dedicate more CPU time to the application program. The SIU_INT is the only interrupt procedure in the SSD. It is automatically entered when an
SIU interrupt occurs. This particular interrupt can be
the lowest priority interrupt in the system.

Table 4. Secondary Station Responses to Primary Station Commands
Data Link
States
Information
Transfer State

Primary Station-Commands

I

RR

RNR

I
RR
RNR
RD
FRMR

I
RR
RNR
RD
FRMR

I
RR
RNR
RD
FRMR

SNRM

DISC

RD

UA

TEST

RD

UA
Test

Logical
Disconnect State

DM

DM

DM

DM

DM

DM

UA
Frame
Reject State

FRMR

FRMR

FRMR

FRMR

UA

14-16

UA

intJ

RUPITM·44

DISC

UA

~~~ER

____________~

296166-11

Figure 9. State Diagram of Secondary Station

14-17

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SIU_RECY

I

SIU_INT

II I

I

I
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I
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COMMAND_DECODE

I
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XMIT_ FRMR

'

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IN_FRMR_STATE

I I

IN_DISCONNECT_STATE

I

I

I

I
SNRM_RESPONSE

I

I

I

I

i-J::i

J

I

II

l:I

c:

XMIT_UNNUMBERED

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ill:

r-------~---------~---------------------~-~

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.--~

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OPEN

I

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296166-12

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inter

RUPITM·44

SSD INITIALIZATION

Upon reset the application software is entered first. The
application software initializes its own variables then
calls Power_On~ which is the SSD's initialization
routine. The SSD's initialization sets up the transmit
and receive data buffer pointers (TBS and RES), the
receive buffer length (RBL), and loads the State variables. The STATION_STATE begins in the L_D_S
state, and the USER--STATE begins in the closed
state. Finally Power_OIL-D initializes XMIT_
BUFFER--EMPTY which is a bit flag. This flag
serves as a semaphore between the SSD and the application software to indicate the status of the on chip
transmit buffer. The SSD does not set' the station address. It is the application software's responsibility to
do this. After initialization, the SSD is read to respond
to all of the primary station commands. Each time a
frame is received with a matching station address and a
good CRC, the SIU_INT procedure is entered.

reasons for the SIU to automatically leave the AUTO
mode. The following is a list of these reasons, and the
responses given by the SSD based on each reason.
1. The SIU has received a command field it does not
recognize.
Response: If the CPU recognizes the command, it
generates the appropriate response. If neither the
SIU nor the CPU recognize the command, then a
FRMR response is sent.
2. The SIU has received a Sequence Error Sent
(SES= 1 in NSNR register). Nr(p);6Ns(S)+ I, and
Nr(P);6Ns(S).
Response: Send FRMR.
3. A buffer overrun has occurred. BOV = 1 in STS register. '
Response: Send FRMR.
4. An I frame with data was received while RPB = 1.
Response: Go back into AUTO mode and send an
AUTO mode response

SIU_INT PROCEDURE

The first thing the SIU_INT procedure clears is the
serial interrupt_bit (SI) in the STS register. If the
SIU_INT procedure returns with this bit set, another
SI interrupt will occur.
The SIU_INT procedure is branches three independent cases. The first case is entered if the STATION_
STATE is not in the 1_TJ . If this is true, then the
SIU is not in the AUTO mode, and the CPU will have
to respond to the primary on its own. (Remember that
the AUTO mode is entered when the STATION_
STATE enters into LTJ.) If the STATION_
STATE is in the I_TJ, then either the SIU has just
left the AUTO mode, or is still in the AUTO mode.
This is the second and third case, respectively.
In the first case, if the STATIONJTATE is not in
the I_T_S, then it must be in either the L~_S or
the FRMR--S. In either case a separate procedure is
called based on which state the station is in. The IlLDisconnect_State procedure sends to the primary a
DM response, unless it received a SNRM command
and the USER--STATE equals open. In that case the
SIU sends a UA and enters into the I_T_S. The IlLFRMR--State procedure will send the primary the
FRMR response unless it received either a DISC or an
SNRM. If the primary's command was a DISC, then
the secondary will send a UA and enter into the L_
D_S. If the primary's command was a SNRM, then
the secondary will send a UA, enter into the LT_S,
and clear NSNR register.
For the second case, if the STATION_STATE is in
the LT_S but the SIU left the AUTO mode, then t\le
CPU must determine why the AUTO mode was exited,
and generate a response to the primary. There are four

In addition to the above reasons, there is one condition
where the CPU forces the SIU out of the AUTO mode.
This is discussed in the SSD's User Interface Procedures section in the CLOSED procedure description
, Finally, case three is when the STATION_STATE is
in the I_T_S and the AUTO mode. The CPU frrst
looks at the TBF bit. If this bit is 0 then the interrupt
may have been caused by a frame which was transmitted and acknowledged. Therefore the XMIT_BUFFER--EMPTY flag is set again, indicating that the application software can transmit another frame.
The other reason this section of code could be entered
is if a valid I frame was received. When a good I frame
is received the RBE bit equals O. This means that the
receiver is disabled. If the primary were to poll the 8044
while'RBE=O, it would time out since no response
would be given. Time outs reduce network throughput.
To improve network performance, the CPU first sets
RBP, then sets RBE. Now when the primary polls the
8044 an immediate RNR response is given. At this
point the SSD calls the application software procedure
SIU~CV and passes the length of the data as a
parameter. The SIU_RECV procedure reads the data
out of the receive buffer then returns to the SSD module. Now that the receive information has been transferred, RBP can be cleared.
COMMAND_DECODE PROCEDURE

The Command~ecode procedure is called from the
SIU_INT procedure when the STATION_STATE
== I_TJ and the SIU left the AUTO mode as a
result of not being able to recognize the receive control
byte. Commands which the SIU AUTO mode does not

14-19

inter

RUPITM·44

C·FIELD OF THE REJECTED COMMAND, AS RECEIVED

r

I

THIS STATION'S PRESENT Ns

,

___

I

THIS STATION'S PRESENT Nr

~

0

,

o

I

HIGH·ORDER

W

X

y

Z

,
o

o

o

o

I

RECEIVED DISAGREES WITH TRA NSMITTED Ns
BUFFER OVERRUN (I·FIELD IS TOo LONG)
PROHIBITED I·FIELD RECEIVED
INVALID OR NONIMPLEMENTED COMMAND
296166-13

Figure 11. Information Field of the FRMR Response, as Transmitted

recognize are handled here. The commands recognized
in this procedure are: SNRM, DISC, and TEST. Any
other command received will generate a Frame Reject
with the nonimplemented command bit set in the third
data byte of the FRMR frame. Any additional unnumbered frame commands which the secondary station is
going to implement, should be implemented in this procedure.
IF an SNRM is received the command_decode procedure calls the SNR~L•.Response procedure. The
SNR~esponse procedure sets the STATION_
STATE = LTJ, clears the NSNR register and responds with a UA frame. If a DISC is received, the
comman~decode procedure sets the STATION_
STATE = L~J, and responds with a UA frame.
When a TEST frame is received, and there is no buffer
overrun, the command_decode procedure responds
with a TEST frame retransmitting the same data it received. However if a TEST frame is received and there
is a buffer overrun, then a TEST frame will be sent
without any data, instead of a FRMR with the buffer
overrun bit set.

fteld. Figure 11 displays the format for the three data
bytes in the I fteld of a FRMR response. The XMIT_
FRMR procedure sets up the Frame Reject response
frame based on the parameter' REASON which is
passed to it. Each place in the SSD code that calls the
XMITJRMR procedure, passes the REASON that
this procedure was called, which in tum is communicated to the primary station. The XMITJRMR procedure uses three bytes of internal RAM which it initializes for the correct response. The TBS and TBL registers are then changed to point to the FRMR buffer so
that when a response is sent these three bytes will be
included in the I fteld.
The INJRMR-STATE procedure is called by the
SIU_INT procedure when the STATION_STATE
already is in the FRMR state and a response is required. The INJRMR-STATE procedure will only
allow two commands to remove the secondary station
from the FRMR state: SNRM and DISC. Any other
command which is received while in the FRMR state
will result in a FRMR response frame.
XMIT_UNNUMBERED PROCEDURE

FRAME REJECT PROCEDURES

There are two .procedures which handle the FRMR
state: XMIT~R and IN_FRMR-STATE.
XMITJRMR is entered when the secondary station
ftrst goes into the FRMR state. The frame reject response frame contains the FRMR response in the command fteld plus three additional data bytes in the I

This is a general purpose transmit procedure, used only
in the FLEXIBLE mode, which sends unnumbered ·responses to the primary. It accepts the control byte as a
parameter, and also expects the TBL register to be set
before the procedure is called. This procedure waits until the frame has been transmitted beforeretuming. If

14-20

RUPITM-44

this procedure returned before the transmit interrupt
was generated, the SIU_INT routine would be entered. The SIU_INT routine would not be able to distinguish this condition.
SSD's User Interface Procedures-OPEN, CLOSE,
TRANSMIT, SIU_RECV-are discussed in the following section.
The OPEN procedure is the simplest of all, it changes
the USE~STATE to OPEN_S then returns. This
lets the SSD know that the user wants to open the
channel for communications. When the SSD receives a
SNRM command, it checks the USE~STATE. If the
USE~STATE is open, then the SSD will respond
with a UA, and the STATION_STATE enters the
I_T_S.
The CLOSE procedure is also simple, it changes the
USE~STATE to CLOSED_S and sets the AM bit
to O. Note that when the CPU sets the AM bit to 0 it
puts the SIU out of the AUTO mode. This event is
asynchronous to the events on the network. As a result
an I frame can be lost. This is what can happen.
1. AM is set to 0 by the CLOSE Procedure.
2. An I frame is received and an SI interrupt occurs.
3. The SIU_INT procedure enters case 2 (STATION_STATE = I_T_S, and AM = 0).
4. Case ~ detects that the USE~STATE =
CLOSED_S, sends an RD response anl.i ignores the
fact that an I frame was received.
Therefore it is advised to never call the CLOSE procedure or take the SIU out of the AUTO mode when it is
receiving I frames or an I frame will be lost.
For both the TRANSMIT and SIU_RECV procedures, it is the application software's job' to put data
into the transmit buffer, and take data out of the receive buffet. The SSD does not transfer data in or out
of its transmit or receive buffers because it does not
know what kind of buffering the application software is
implementing. What the SSD does do is notify the application software when the transmit buffer is empty,
XMIT_BUFFE~MPTY = I, and when the receive buffer is full.

application software thinks that the SDLC channel is
now open and it can transmit. This is not the case. For
the channel to be open, the SSD must receive an
SNRM· from the primary and respond' with a UA.
However; the SSD does not want to hang up the application software waiting for an SNRM from the primary
before returning from the OPEN procedure. When the
TRANSMIT procedure is called, the SSD expects the
STATION_STATE to be in the I_T_S. If it isn't,
the SSD refuses to transmit the data. The TRANSMIT
procedure first checks to see if the USE~STATE is
open. If not, the USE~STATE_CLOSED parameter is passed back to the application module. The next
thing TRANSMIT checks is the STATION_STATE.
If this is not open, then TRANSMIT passes back
LINILJ)ISCONNECTED. This means that the
USE~STATE is open, but the SSD hasn't received
an SNRM command from the primary yet. Therefore,
the application software should wait awhile and try
again. Based on network performance, one knows the
maximum amount of time it will take for a station to be
polled. If the application software waits this length of
time and tries again but still gets a LINILJ)ISCONNECTED parameter passed back, higher level recovery
must be implemented..
Before loading the transmit butTer and calling the
TRANSMIT procedure, the application software must
check to see that XMIT_BUFFE~EMPTY = 1.
This flag tells the application software that it can write
new data into the transmit buffer and call the TRANSMIT procedure. After the application software has verified that XMIT.-BUFFE~EMPTY = I, it fills the
transmit buffer with the data and calls the TRANSMIT procedure passing the length of the buffer as a
parameter. The TRANSMIT procedure checks for
three reasons why it might not be able to transmit the
frame. If any of these three reasons are true, the
TRANSMIT procedure returns a parameter explaining
why it couldn't send the frame. If the application software receives one of these responses, it must rectify the
problem and try again. Assuming these three conditions are false, then the SSD clears XMIT_BUFFE~EMPTY, attempts to send the data and returns
the parameter DAT~TRANSMITTED. XMIT_
BUFFE~EMPTY will not be set to I again until the
data has been transmitted and acknowledged.

One of the functions that the SSD performs to synchronize the application software to the SDLC data link.
However some of the synchronization must also be
done by the application software. Remember that the
SSD does not want to hang up the application software
waiting for some event to occur on the SDLC data link,
therefore the SSD always returns to· the application
software as soon as possible.
For example, when the application software calls the
OPEN procedure, the SSD returns immediately. The

14-21

The SIU.-R,ECV procedure must be incorporated into
the application software module. When a valid I frame
is received by the SIU, it calls the SIU_RECV procedure and passes the length of the received data as a
parameter. The SIU.-R,ECV procedure must remove
all of the data from the receive butTer before returning
to the SIU_INT procedure.

inter

RUPITM-44

LINKING UP TO THE SSD

Figure 12 shows the necessary parts to include in a
PL/M-51 application program that will be linked to the
SSD module. RL51 is used to link and locate the SSD
and application modules. The command line used to do
this is:

$registerbank(O)
user$mod': do;
$include (reg44.dcl)
decl'are
literally 'literally',
lit
buffer_length
lit
'60',
SiU_lODit_buffer
(buffer_length)
byte
external idata,
siu_recv_buffer
(buffer_length)
byte
external,
xmit_buffer_emptybit
external;

After the secondary station powers up, it enters the
'terminal mode', which accepts data from the terminal.
However, before any data is sent, the user must configure the station. The station address and destination
address must be set, and the station must be placed
oli1ine. To configure the station the ESC character is
entered at the terminal which puts the protocol converter into the 'configure mode'. Figure 13 shows the
menu which appears on the terminal screen.

I' external procedures 'I,
external,;

close: procedure
end close;

external using 1;

open: procedure
end open;

external uSing 1;

transmit: proce'dure
(lODit_buffer_length) byte
declare xmit_buffer_length
end transmit;

2.4 Application Module; ASYNC to
SOLC Protocol Converter
One of the purposes of this application module is to
demonstrate how to interface software to the SSD. Another purpose is to implement and test a practical application. This application software performs I/O with an
async terminal through a USART, buffers data, and
also performs I/O with the SSD. In addition, it allows
the user on the async terminal to: set the station address, set the dc:stination address, and go online lind
omine. Setting the station address sets the byte in the
STAD register. The destination address is the first byte
in the I field. Going online or otlline results in either
calling the OPEN or CLOSE procedure respectively.

RL51 SSD.obj ,filename.obj ,PLM51.LIB TO ,,'
filename & RAMSIZE(192)

power _on_d: procedure
end power_on_d;

The SSD module uses the $REGISTERBANK(I) attribute. Some procedures are modified with the USING
attribute based on the register bank Itwei of the calling
procedure.
'

(1)8044 Secondary Station
/
12345-

external;
byte;

/* local procedures' 'I
siu_recv: procedure (length)
public
declare
length byte,-

Set the Station Address
Set the Destination Address
Go Online
Go Omine
Return to terminal mode
Enter option _

uSing 1;

Figure 13. Menu for the Protocol Converter

•
•
•

In the terminal mode data is buffered up in the second~
ary station. A Line Feed character 'LF' tells the secondary station to send an I frame. If more than 60 bytes
are buffered in the secondary station when a 'LF' is
received, the applications software packetizes the data
into 60 bytes or less per frame. If a LF is entered when
the station is omine, an error message comes on the
screen which says 'Unable to Get OIi1ine'.

Figure 12. Applications Module Link Information
PL/M-51 AND REGISTER BANKS

The 8044 has four register banks. PL/M-51 assumes
that an interrupt procedure never uses the same bank as
the procedure it interrupts. The USING attribute of a
procedure, or the $REGISTERBANK control, can be
used to ensure that.

The secondary station also does error checking on the
async interface for Parity, Framing Error, and Overrun
Error. If one of these errors are detected, an error message is displayed on the terminal screen.

14-22

inter

RUPITM·44

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Figure 14. Block Diagram of Secondary Station Protocol Converter illustrating Buffering
14-23

RUPITM.·44

BUFFERING

There are two separate buffers in the application,module: a transmit buffer and a receive buffer; The transmit
buffer receives data from the USART, and sends data
to the SSD. The receive buffer receives data from the
SSD, and transmits data to the USART. Each buffer is
a 256 byte software FIFO. If the transmit FIFO becomes full and no 'LF' character is received, the sec-, ,
ondary station automatically begins sending the data.
In addition, the application modules will shut off the
terminal's transmitter using CTS until the FIFO has
been partially emptied. A block diagram of the buffering for the protocol converter is given in Figure 14.
APPLICATION MODULE SOFTWARE

A block diagram of the application module software is
given in Figure IS. There are three interrupt routines iii
this module: USARTJECV_INT, USART_
XMIT_INT, and TIMER-OjNT. The first two are
for servicing the USART. TIMER-O~INT is used If
the TRANSMIT procedure in the SSD is called and
does not return with the DAT~TRANSMITTED
parameter. TIMER-OjNT employs Timer 0 to wait
a finite amount of time before trying to transmit again.
The highest priority interrupt is, USART_RECV_
INT. The main program and all the procedures it calls
use register bank 0, USART~MITjNT and TIMER-O_INT and FIFO-R-OUT use bank' I, while
USARTJECV_INT and all the proCedures it calls
'
use register bank 2.
POWER-ON PROCEDURE

The Power_On procedure initializes all of the chips in
the system including the 8044. The 8044 is initialized to
use the on-chip DPLL with NRZI coding, PreFrame
Sync, and Timer I auto reload at a baud rate of
62.5 Kbps. The 8254 and the 8251A are initialized next
based on the DIP switch values attached to port I on
the 8044. Variables and pointers are initialized, then the
SSD's Power-Up Procedure, Power_~, is called.
Finally, the interrupt system is enabled and the main
program is entered.
MAIN PROGRAM

The main program is a simple loop which waits for a
frame transmit command. A frame transmit command
is indicated when the variable SEND~ATA is greater than O. The value of SEND~ATA equals the
number of 'LF' characters in the transmit FIFO, hence
it also indicates the number of frames pending transmission. Each time a frame is sent, SEND~ATA is
decremented by one. Thus when SEND~ATA is,
greater than 0, the main program falls down into the

next loop which polls the XMIT_BUFFER-EMPTY bit. When XMIT_BUFFBR-EMPTY equals 1,
the SIU~MITJUFFER can be loaded. The first
byte in the buffer is loaded with the destination address
while the rest of the buffer is loaded with the data.
Bytes are removed from the transmit FIFO and placed'
-into the SIU~MITJUFFER until one of three'
things happen: 1. a 'LF' character is read out of the
FIFO, 2. the number of bytes loaded equals the size of
the SIU_XMITJUFFER, or 3. the transmit FIFO
,is empty.
After the SIU~MITJUFFER is filled, the SSD
TRANSMIT procedure is called and the results from
the procedure are checked. Any result other than
DAT~TRANSMITTED will result in several retries
within a finite amount of time. If all the retries fail,
then the LINICJ)ISC procedure is called which sends
a message to the terminal, 'Unable to Get Online'.

When the 8251A receives a charaCter, the RxRDY pin
on the 82~IA is activated, and this interrupt procedure
is entered: The routine reads the USART status register
to determine if there are any errors in the character
received. If there are, the character is discarded and the
ERROR .procedure is called which prints the type of
error on the screen. If there are no errors, the received
character is checked to see if it's an ESC. If it is an
ESC, the MENU procedure ~s called which allows the
, 'user t6 charige the configuration. If neither one of these
two conditions exists, the received character is inserted
into the transmit FIFO: The received character mayor
may not be echoed back to the terminal based on the
dip switch settings.
TRANSMIT FIFO

The transmit FIFO consists of two' procedures: FIFO_
L,3N and FIFO_T_OUT. FIFO_TjN inserts a
character into the FIFO, and FIFO_T_OUT removes a character from the FIFO. The FIFO itself is,
an array of 256 bytes called FIFO_T. There are two
pointers used as indexes in the array to address the
characters: IN_PTR-T and OUTJTR-T. IN_
PTR-T points to the location in the array which will.
store the next byte of data inserted. OUTJTR-T
points t~ the next byte of data removed from the array.
Both IN",-PTR-T and OUTJTR-T are declared
as bytes. The FIFO_TjN procedure receives a character from the USART~ECV_INT procedure and
stores it in the array location pointed to by IN_PTRT, then INJTR-T is incremented. Similarly, when
FIFO_T~OUT is called by the main program, to
'load the SIU~MITJUFFER, the byte in the array

14-24

r-------~-----------------------I
I

I

I

MAIN_PROGRAM

~----------~I--------~

II

I

I

.

(

I

I

I
FIFO_T_OUT

I
I
I
I

I
I
I
I
I

:!!

ID
C
III

...

I

....

.....
~
N
en

I

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I

m
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I

FIFO_T..JN

:JJ

c:

C

iii"

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...

ID

~

DI

3

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0

C

In

...

III

en
0

-...
~.

...

III·

I

I
I
I
I

IUSART_XMIT_INT I

TIMER_O_INT

I

I

IL ______________________________________________

~

296166-15

intJ

RUPITM·44

pointed to by OUT~~T is read, then OUT_
PT~T is incremented; Since IN_PT~T and
OVTJT~T are always incremented, they must be
able to roll over when they hit the top of the '256 byte
address space. This is done automatically by having
both INJT~T and OUTJT~T declared as
bytes. Each character inserted into the transmit FIFO
is tested to see if it's a LF. If it is a LF, the variable
SEND~ATA is incremented, which lets the main
program know that it is time to send an I frame. Similarly each character removed from the FIFO is tested.
SEND_DATA is decremented for every LF character
removed from the FIFO.

stations and receives responses from them. The primary
station controls link access, link level error recovery,
and the flow of information. Secondaries can only
transmit when polled by the primary.
Most primary stations are either micro/minicomputers,
or front end processors to a mainframe computer. The
example primary station in this design is standalone. It
is possible for the 8044 to be used as an intelligent front
end processor for a microprocessor, implementing the
primary station functions. This latter type of design
would extensively off-load link control functions for the
microprocessor. The code listed in this paper can be
used as the basis for this primary station design. Additional software is required to interface to the microprocessor. A hardware design example for interfacing
the 8044 to a microprocessor can be found in the applications section of this handbook.

INJT~T and OUT_PT~T are also used to indicate how many bytes are in the FIFO, and whether it
is full or empty. When a character is placed into the
FIFO and INJT~T is incremented, the FIFO is
full if INJ~T equals OUTJT~T. When a
character is read from the FIFO and OUTJT~T
is incremented, the FIFO is empty if OUT_PT~T
equals INJT~T. If the FIFO is neither full nor
empty, then it is in use. A byte called BUFFE~
STATUS_T is used to indicate one ofthese three conditions. The application module uses the buffer status
information to control the flow of data into and out of
the FIFO. When the transmit FIFO is empty, the main
program must stop loading bytes into the SIU_
XMITJUFFER. Just before the FIFO is full, the
async input must be shut off using CTS. Also, if the
FIFO is full and SEND~ATA = 0, then SEND_
DATA must be incremented to automatically send the
data without an LF.

From the listing of the software it can be seen that the
variable NUMBE~OF,,-STATIONS is a literal declaration, which is 2 in this design example. There were
three stations tested on this data link, two secondaries
and one primary. Following the NUMBE~OF_
STATIONS declaration is a table, loaded into the object code file at compile time, which lists the addresses
of each secondary station on the network.

RECEIVE FIFO

REMOTE STATION DATABASE

The receive FIFO operates in a fashion similar to the
transmit FIFO. Data is inserted into the receive FIFO
from the SIUJECV procedure. The SIU_RECV
procedure is called by the SIUJNT procedure when a
valid I frame is received. The SIU_RECV procedure
merely polls the receive FIFO status to see if it's full
before transferring each byte from the SIUJECV_
BUFFER into the receive FIFO. If the receive FIFO is
full, the SIU_RECV procedure remains polling the
FIFO status until it can insert the rest of the data. In
the meantime, the SIU AUTO mode is responding to
all polls from the primary with a RNR supervisory
frame. The USART~MIT_INT interrupt procedure removes data from the receive FIFO and transmits it to the terminal. The USART transmit interrupt
remains enabled while the receive FIFO has data in it.
When the receive FIFO becomes empty, the USART
transmit interrupt is disabled.

The primary station keeps a record of each secondary
station on the network. This is called the Remote Station Database (RSD). The RSD in this software is an
array of structures, which can be found in the listing
and also in Figure 16. Each RSD stores the necessary
information about that secondary station.

2.5 Primary Station
The primary station is responsible for controlling the
data link.' It issues commands to the secondary

The primary station must know the addresses of all the
stations which will be on the network. The software for
this primary needs to know this before it is compiled,
however a more flexible system would download these
parameters.
'

To add additional secondary stations to the network,
one simply adjusts the NUMBE~OF_STATIONS
declaration, and adds the additional addresses to th~
SECONDARY~DDRESSES table. The number of
RSDs is automatically allocated at compile time, and
the primary automatically polls each station whose address is in the SECONDARY~DDRESSES table.
Memory for the RSDs reSides in external RAM. Based
on memory requirements for each RSD, the maximum
number of stations can be easily buffered in external
RAM. (254 secondary stations is the maximum number
SDLC will address on the data link; i.e. 8-bit address,
FF H is the broadcast address, and 0 is the null address. Each RSD uses 70 bytes of RAM. 70 x 254 =
17,780.)

14-26

RUPITM·44

The station state, in the RSD structure, maintains the
status of the secondary. If this byte indicates that the
secondary is in the DISCONNECT_S, then the primary tries to put the station in the I_T_S by sending
an SNRM. If the response is a UA then the station
state changes into the I_T_S. Any other frame received results in the station state remaining in the DISCONNECT_S. When the RSD indicates that the station state is in the LT_S, the primary will send either
an I, RR, or RNR command, depending on the local
and remote butTer status. When the station state equals
GO_TO_DISC the primary will send a DISC command. If the response is a UA frame, the station state
will change to DISCONNECT_S, else the station
state will remain in GO_TO_DISC. The station state
is set to GO_TO_DISC when one of the following
responses occur:
I. A receive butTer overrun in the primary.
2. An I frame is received and Nr(P) =P Ns(S).
3. An I frame or a Supervisory frame is received and
Ns(P) + 1 =P Nr(S) and Ns(P) =P Nr(S).
4. A FRMR response is received.
5. An RD response is received.
6. An unknown response is received.
The send count (Ns) and receive count (Nr) are also
maintained in the RSD. Each time an I frame is sent by
the primary and acknowledged by the secondary, Ns is
incremented. Nr is incremented each time a valid I
frame is received. BUFFER-STATUS indicates the
status of the secondary station's butTer. If an RR response is received, BUFFER-STATUS is set to
BUFFER-READY. If a RNR response is received,
BUFFER-STATUS is set to BUFFER-NOT_
READY.
BUFFERING

The butTering for the primary station is as follows:
within each RSD is a 64 byte array butTer which is
initially empty. When the primary receives an I frame,
it looks for a match between the first byte of the I frame
and the addresses of the secondaries on the network. If
a match exists, the primary places the data in the RSD
butTer of the destination station. The INFO_
LENGTH in the RSD indicates how many bytes are in
the butTer. If INFOJENGTH equals 0, then the
butTer is empty. The primary can butTer only one I
frame per station. If a second I frame is received while
the addressed secondary's RSD butTer is full, the primary cannot receive any more I frames. At this point
the primary continues to poll the secondaries using
RNR supervisory frame.
.

PRIMARY STATION SOFTWARE

A block diagram of the primary station software is
shown in Figure 17. The primary station software consists of a main program, one interrupt routine, and several procedures. The POWER-ON procedure begins
by initializing the SIU's DMA and enabling the receiver. Then each RSD is initialized. The DPLL and the
timers are set, and finally the TIMER interrupt is
enabled.

°

The main program consists of an iterative do loop within a do. forever loop. The iterative do loop polls each
secondary station once through the do loop. The variable STATION_NUMBER is the counter for the iterative do statement which is also used as an index to the .
array of RSD structures. The primary station issues one
command and receives one response from every secondary station each time through the loop. The first statement in the loop loads the secondary station address,
indexed by STATION_NUMBER into the array of
the RSD structures. Now when the primary sends a
command, it will have the secondary's address in the
address field of the frame. The automatic address recognition feature is used by the primary to recognize the
response from the secondary.
Next, the main program determines the secondary station's state. Based on this state, the primary knows
what command to send. If the station is in the DISCONNECT_S, the primary calls the SNRM_P procedure to try and put the secondary in the LT_S. If
the station state is in the GO_TO_DISC state, the
DISCJ is called to try and put the secondary in the
L.-D_S. If the secondary is in neither one of the
above two states, then it is in the I_T_S. When the
secondary is in the 1_T_S, the primary could send
one of three commands: I, RR, or RNR. If the RSD's
butTer has data in it, indicated by INFO_LENGTH
being greater than zero, and the secondary's BUFFER-STATUS equals BUFFER-READY, then an I
frame will be sent. Else if RPB = 0, an RR supervisory
frame will be sent. If neither one of these cases is true..
then an RNR will be sent. The last statement in the
main program checks the RPB bit. If set to one, the
BUFFER-TRANSFER procedure is called, which
transfers the data from the SIU receive butTer to the
appropriate RSD butTer.

14-27

intJ

RUPITM_44

RSD

maximum frame length time comes from the fact the
8044 does not generate an interrupt from a received
frame until it has been completely received, and the
CRC is verified as correct. This means that the timeout is bit rate dependent.

STATION-ADDRESS
STATION-STATE
NS
NR
BUFFER-STATUS

Ns AND Nr CHECK PROCEDURES

INFO-LENGTH
DATA (0)

Each time an I frame or supervisory frame is received,
the Nr field in the control byte must be checked. Since
this data link only allows one outstanding frame, a valid Nr would satisfy either one of two equations;
Ns(P) + I = Nr(S) the I frame previously sent by the
primary is acknowledged, Ns(P) = Nr(S) the I frame
previously sent is not acknowledged. If either one of
these two cases is true, the CHECLNR procedure
returns a parameter of TRUE; otherwise a FALSE parameter is returned. If an acknowledgement is received,
the Ns byte in the RSD structure,is incremented, and
the Information buffer may be cleared. Otherwise the
information buffer remains full.

DATA (63)

Figure 16. Remote Station Database Structure
RECEIVE TIME OUT
Each, time a frame is transmitted, the primary sets a
receive time out timer; Timer O. If a response is not
received within a certain time, the primary returns to
the main program and continues polling the rest of the
stations. The minimum length of time the primary
should wait for a response can be calculated as the sum
of the following parameters.
1. Propagation time to the secondary station
2. Clear-to-send at the secondary station's DCE
3. Appropriate time for secondary station processing
4. Propagation time from the secondary station
5. Maximum frame length time
The clear-to-send time and the propagation time are
negligible for a local network at low bit rates. However,
the turnaround time and the maximum frame length
time are significant factors. Using the 8044 secondaries
in the AUTO mode minimizes turnaround time. The

When an I frame is received, the Ns field has to be
checked also. If Nr(p) = Ns(S), then the procedure
returns TRUE, otherwise a FALSE is returned.
RECEIVE PROCEDURE
The receive procedure is called when a supervisory or
information frame is sent, and a response is received
before the time-out period. The RECEIVE procedure
can be broken down into three parts. the first, part is
entered if an I frame is received. When an I frame is
received, Ns, Nr and buffer overrun are checked. If
there is a buffer overrun, or there is an error in either
Ns or Nr, then the station state is set to GO_TO~
DISC. Otherwise Nr in the RSD is incremented, the
receive field length is saved, and the RPB bit is set. By
incrementing the Nr field, the I frame just received is
acknowledged the next time the primary polls the secondary with an I frame or a supervisory frame.' Setting
RBP protects the received data, and also tells the main
program that there is data to transfer to one ofthe RSD
buffers.

14-28

inter

RUPITM·44

MAIN PROGRAM

BUFFER

TRANSFER

296166-16

Figure 17. Block Diagram of Primary Station Software Structure

If a supervisory frame is received, the Nr field is
checked. If a FALSE is returned, then the station state
is set to GO_TO_DISC. If the supervisory frame received was an RNR, buffer status is set to not ready. If
the response is not an I frame, nor a supervisory frame,
then it must be an Unnumbered franie:
The only Unnumbered frames the primary recognizes
are UA, DM, and FRMR. In any event, the ,station

state is set to GO_TO~ISC. However, if the frame
received is a FRMR, Nr in the second data byte of the I
field is checked to see if the secondary acknowledged an
I frame received before it went into the FRMR state. If
this is not done and the secondary acknowledged an I
frame which the primary did not recognize, the primary transmits the I frame when the secondary returns
to the I_T_S. In this case, the secondary would receive duplicate I frames.

14-29

inter

RUPITM·44

APPENDIX A
8044 SOFTWARE FLOWCHARTS
POWER-ON-D PROCEDURE
USER-STATE

STATION-STATION

= CLOSED-S
= DISCONNECT-S

TBS

= S.IU-XMIT-BUFFER STARTING ADDRESS

RBS

= SIU-RECV-BUFFER STARTING ADDRESS

RBl

= BUFFER LENGTH

. ENABLE SIU RECEIVER: RBE

XMIT-BUFFER-EMPTY

=1

=1

RE.TURN

296166-17
CLOSE PROCEDURE
AM=O

RETURN

OPEN PROCEDURE
USER STATE = OPEN_S

RETURN

296166-18

Figure 18. Secondary Station Driver Flow Chart

14-30

infef

RUPITM-44

XMIT-UNNUMBERED PROCEDURE

296166-19
TRANSMIT PROCEDURE

STATUS = USER·STATE·ClOSE

STATUS =
LINK_DISCONNECTED

=

STATUS
?VERFlOW

XMIT·BUFFER·EMPTY

=0

TBl = XMIT·BUFFER·lENGTH

I·FRAME·lENGTH

=

XMIT.BUFFER.lENGTH

STATUS = DATA· TRANSMITTED

296166-20

Figure 19. Secondary Station Driver Flow Chart

14-31

intJ

RUPITM~44

XMIT-FRMR PROCEDURE

FRMR·BUFFER (2)

=

REASON

STATION·STATE = FRMR·S·

N

y

SEND FRMR
FRAME

296166-21

Figure 20. Secondary Station Driver Flow Chart

14-32

intJ

RUPITM·44

IN·DISCONNECT·STATE PROCEDURE

N

296166-22
SNRM·RESPONSE PROCEDURE

296166-23

Figure 21. Secondary Station Driver Flow Chart

14·33

inter

RUPITM-44

IN·FRMR·STATE PROCEDURE

y

y

296166-24

Figure 22. Secondary Station Driver Flow Chart

14·34

inter

RUPITM·44

COMMANO DECODE PROCEDURE

296166-25

Figure 23. Secondary Station Driver Flow Chart
14-35

l

. SIII-INT PROCEDURE

6c

I

~

y

y

iiJ

,.

~

N

Ie

n
0

I CALL COIIMAND-DECODE

XMIT·BUFFER·EMPTY

=1

:=I

a.

CALL XMIT·UNNUMBERED
(REQ.DISC)

DI

.... .c!.

t
<»

Sfl

-

11--------,

y

1

•

1

N

is"

...C
...<"

y

~

..•

CALL XIIIT-FRMR

CD

•~
0

:r
DI
::I.

c:

."

DI

:=I

:II

CALL COMMAND DECODE

296166-26

RUPITM·44

MAIN PROGRAM

LOAD DESTINATION
ADDRESS IN FIRST
BYTE OF SIU-XMIT
BUFFER

LOAD INFORMATION
INTO SIU XMIT-BUFFER
SIU BUFFER LENGTH
OR FIFO-T EMPTY

Y

OUTPUT MESSAGE
TO TERMINAL
'UNABLE TO GET ON LINE'

296166-27

Figure 25. Application Module Flow Chart

14-37

inter

RUPITM·44

USART·RECV·INT INTERRUPT PROCEDURE

N

296166-28

Figure 26. Application Module Flow Chart

14·38

intJ

RUPITM-44

MENU PROCEDURE
OUTPUT MENU
TO TERMINAL

CALL OUTPUT·MESSAGE
'ENTER THE STATION ADDRESS:_'
CALL GET·HEX
SHIFT TO LEFT BY FOUR

LOAD ADDRESS
INTO STAD
CALL OUTPUT·MESSAGE
'THE. NEW STATION ADDRESS:_'

N

CALL OUTPUT·MESSAGE
'ENTER THE DESTINATION ADDRESS:_'
CALL GET·HEX
SHIFT TO LEFT BY FOUR

LOAD ADDRESS
INTO DESTINATION·ADDRESS

CALL OUT·MESSAGE
'THE NEW DESTINATION ADDRESS IS:_'

RETURN

296166-29

Figure 27. Application Module Flow Chart

14-39

RUPITM·44

ERROR PROCEDURE

y

y

RESET ERROR FLAGS ON USART

296166-30

Figure 28. Application Module Flow Chart

14-40

RUPITM-44

FIFO·T-OUT PROCEDURE

296166-31

Figure 29. Application Module Flow Chart

14·41

RUPITM·44

FIFo-T·IN PROCEDURE

N

RETURN
296166-32

Figure 30. Application Module Flow. Chart

14-42

RUPITM·44

SIU·RECV PROCEDURE

296166-33

Figure 31. Application Module Flow Chart
POWER ON

I

INITIALIZE SIU REGISTERSJ

I
FOR EACH STATION
INITIALIZE RSD RECORDS
1. STATlON·ADDRESS
2•.STATIQN·STATE
DISCONNECT
3. BUFFER·STATE
BUFFER·NOT·READY
4. INFO-LENGTH
0

== =

I

I
RETURN

I
296166-34

Figure 32. Primary Station Flow Charts

14·43

inter

RUPITM_44

PRIMARY STATION MAIN PROGRAM

ADDRESS NEXT STATION
SETSTAD

Y

CALL SEND-SNRM

Y

CALL SEND-DISC

CALL XMIT I T S
(T-I-FRAME) -

Y

I---------.,.-C

CALL XMIT-I-T-S
(T-RR)

Y

v

CALL BUFFER-TRANSFER

296166-35

Figure 33. Primary Station Flow Charts

14-44

RUPITM·44

SEND·SNRM PROCEDURE

N

296166-36
SEND-DISC PROCEDURE

N

=

STATION·STATE
DISCONNECT·S
BUFFER·STATUS
BUFFER-NOT·READY

=

296166-37

Figure 34. Primary Station Flow Charts

14·45

inter

RUPITM·44

XMIT·ToS PROCEDURE
BUILD CONTROL
FIELD USING EITHER
I, RR, RNR
AND NR AND/OR NS

CALL RECEIVE

y

296166-38
XMIT PROCEDURE

296166-39

Figure 34. Prlr:nary Station Flow Charts

14-46

RUPITM·44

BUFFER·TRANSFER PROCEDURE

MOYE DATA FROM
SIU·RECY·BUFFER
TO RSD BUFFER

296166-40

Figure 36. Primary Station Flow Charts

14·47

intJ

RUPITM_44

CHECK-NRPROCEDURE

RETURN
TRUE
296166-41

CHECK-NsPROCEDURE

296166':'42

Figure 37. Primary Station Flow Charts

14·48

l
REMOTE BUFFER-sTATUS

=

BUFFER-READY

Y

.,..

ac

a;
Co»

PI

~

:u

~j

J..
<0

c:
'U

se

.

':j
i:

RECEIVE-FIELD-LENGTH

III

g

• RFL -\

~
~

i9
.,

~.

III

STATION-STATE

= Go.TO-OISC

296166-43

RUPITM·44

APPENDIX B
LISTINGS OF SOFTWARE MODULES
PL/....51 COf'PILER
IBIB-U PL/II-51 111.0
CIlI1PILEA INIIOKED BV,

20: 24: 47

09/20/83

PAGE

,Fa, PL"51 ,Fa, APNDTE. SRC
('R"'I-44 Sec and.,., St.UDn DT"iY.,,')

.TITLE

10£1\10
tREOISTERBANKUI
MINtMOD:
___ 1ST DOl

p.p.,.

/. To ••V~
the RUP] ,. •• ht.,. • • r. nat U.t.d, but tbis is the .t.t.... n'
u ••• to inc Iud. the.: .INCLUDE' (:F2: RE044. DCL) . /
5

DECLARE LIT
TRUI!
FALSE

FDREVER

6

DECLARE BNR"
UA
DISC
~

FR""

REG....DISC
UP
TEST

LITERALLV
LIT
LIT
LIT

'WHILE 1"

'73H',

'43H',

'1FH'.
'97H',
'11314."

'33H',

'0E3H' ,

LIT
LIT

CLDSEDJI

'OFFH'.
'OOH',

.'S3H',

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

OPENJI

'LITERALLV',

'OOH',
'01H',

*' . *',

'OOH', , . LOCnCALLY DISCa...e:CTED STATE*'

LIT
LIT
LIT

'OIH', , . FRNE RE..IECT STATE
'02H'.

USERJlTATEj:LOSED

LIT

'DOH',

LINK....DISCDNNECTED
OVERFLOW
DATA_TltANSltJ"r;T&D

LIT
LIT
LIT

'OaH',
'03H',

/. ItrFORPfATION TRANSFER STATE

'OtH',

/. '.,.••• h1'. p...... to XMIT...FRftR ./
UNIIBIIIGNED_C
ND_I../'IELD.J\Ll.DWED
BUFF....DIlERRUN
SEB...ERR

LIT
LIT
LIT
LIT

'OOH',

'OIH',
'021'1',
'03M',

296166-44

14-50

RUPITM-44

PL./tt-:U cOtP ILER

20: 24: 47

BYTE
BVTE
IYTE

USERJlTATE
STATJDNJ1TATE

IjAAMEJ.ENQTH

PAOE

AUXILIARY.
AUXILIARY.
AUXILIARY.

IUFFEAJ.ENOTH
SIU_XHITJlUFFER (IUFFEAJ.ENOTH)
SIUJlECYJlUFFEA (IUFFERJ.ENQTH)
FR""JtUFFER(3)

09/20/93

160',

LIT
IYTE
IYTE

PUBLIC

PUILIC.

BYTE.

/. Ft. • • • /

XHI TJlUFFER.POPTY
7

81T PUILIC.

9

2
2
I

SIUJlECY: PROCEDURE (LENOTH) EXTERNAL,
DECLARE LENGTH IYTE.
END SIUJlECY,

10
II
12

2
2
I

OPEN: PROCEDURE PUBLIC USING 2.
UBERJlTATE-OPENJh
END [PEN,

.3
14

CLOSE: PROCEDURE PUBLIC USING 2.

"

16

2
2
2
I

UBERJlTATE-CLDSEDJI'
END CLOSE.

.7

2

PDWER_ONJ): PROCEDURE

la

2
2
2
2
2
2
2

a

.9

20
21
22

23
24

PUBLIC USINO 0,

USER.:,.sTATE-CL.OSED_S,
BTItTIDN,JITItTE-DISCONNECT _BI
TI&-. SIUJlHITJlUFFEA(O),
AI&-. SIUJlECYJlUFFER(Oh
RIL-IUFFERJ.ENQTH,
ABE-I,
/. En.bl. thl 8IU'. ,..edv.,. .,
X"ITJlUFFERJUPTY-l.
END PDWEA_ONJ),

2'

26

,....·0.

2

TAANSHIT: PADCEDURE CXHITJlUFl'EAJ.ENOTH) IYTE

PUBLIC USINII 0,

/. Uu" .us' chd XHITJlUFFER..,.E. . TY fl •• It •• o,.. C.Uinl this p,-oc.dur.

27

2

DECLARE XHITJlUFFEAJ.ENIITH

28

2

30

2

IF UBERJlTATE-CLDBED_S
THEN STATUs-uBER_BTATE_CLDBED'
ELSE IF STATrONJlTATE-DISCONtECT_S
THEN STATUs-LINKJ)ISCDNNECTED,
ELSE IF XHIT JlUFFERJ.ENIITIOIUFFERJ.ENIITH
THEN STATUS_FLOW,
ELSE DO.

I

STATUS

32

2

34

3

*'

IYTE,

IYTE
IYTE

AUXILIARY.

AUXILIARY,

296166-45

14-51

i2

inter

RUPITM·44

20: 24: 47

35
36
37

38
39
40
41
42

3
3
3
2
I
2

44

2,

45
46'
47
4B
49
iIO

2
2
2
3
3
2

TIF-S.
STATUllaMTA_TRANMITTEDI
END.
RETURN STATUS.

'END TR_IT.
X"IT_IN«IIIIIERED: PROCEDURE (CDNTROLJlVTEI •

DECLARE CDNTRDLJlVTE

. BVTE.

TCB-CDNTRDLJlVTE.
TIF-l.
RTs-1i

DO WHILE MIT 81.
END.
81-0. '
END Xf1IT_UIIN.ItIEREDI

51

52

2

53

2
2
2

57
H
59
60

~"~E.~: PROCE~E •
STATIONJTATE-I_T_BI

NsNR-O,

IF (RCI AND SOH) 0
THEN DO,

62
63
64

i'

polhd . ,

CALL X"lT_UNNUI1IIEREDCUA),

3'
2

0 , . R•• pond

TlL-O,

3
3

ENDI

IF

X"ITJI\FF'ER~TV-o

THEN DO,

65

PAGE

3
3
3

43

54
55

09/20/83

*'

,. If .n I frM • .,.. 1."
th.n r •• tor. U:

p.ndj~.

'".ndt •• tan

rlL.-IJRNEJ..ENQTH,
TlF-1,
ENDI

3
3
3
2

66
X"IT...FR~:

PROCEDURE (REASONI

67

2

68

2

DECLARE REASON

69

2

TC • .p'R""h

70
71
72

2
2

TBg., FR~JlUFFER(OIo

73
74

75

:I

I

IYTE,

T8L-3.
FR~JlUFFER (Ol-RCBI

:I

/ ....., nnu •• In NaIR . /
FRI'tR __ t.PFERU)-CSHLtcNBNR MD 0EH),41 OR

3
3

DO CASE REA. . .,
FR"J:UFFER(2)-oIH,

/. UNASBIONED_C

He (NSNR

*'

AND OEOH)"4»,

296166-46

14-52

3

inter

RUPITM_44

PL/f1-eU CDI1P J: LER

76
77
78
79

3
3
3
3

80
81

a
a

B3
84
8S

3
3
4

B6

87

as

B9

20: 24: 47
FRI1RJUFFER C:2 J -02HI
FRtIR ..... UFFER (2) -o4H,

END.

PAQE

*,- *'

'* BES~RR

1* ND_IJIELD.j&LLDWED
lUFF OVERRUN
*1

FRIIRJlUFFER cal-OSH.

I-

STATIONJJTATE-FRf1RJJ'

IF CRCI AND 10H. <>0

THEN DO.
TIF-I,
RrS-11
DO WHILE NOT 81.
END.

•

SI-O,

3
3
I

END.

'*

'''D.

91

a
a

93

a

9S
96
97
98

3
3
3
I

TIL-a,
CALL. XPtIT_UNt«JMBERED(DttJI
ENO.
END INJllSCClNNECT_STATE.

99

a

INjRKR_STATE: PROCEDURE I /* e.l hd b, SIU_INT .hen ,. , ...... " •• bun ,..cdv.d

100

a

90

09/20/83

INJUSCONNECT_BTATE: PROCEDURE

J

C.U.d

SIU_INT procedure . /

IF CCU8ER_BTATE-OPEN_BJ AND «RCB AND OEFH)-SNRMJ)
THEN CALL SNR"-"EBPONBE,
ELSE IF (RCB AND 10M) 00 0

TtEN DD.

..hen in th FR. . . t.t.

*,

IF CRCB AND OEFH)-SNAtt

TI£N DO,

loa
103
104

3
3
3

lOS

a

107
109
109

3
3
3

III

lIa

CALL BNR"....RESPONSEI

Ta&-. BIU~"ITJlUFFER(OJJ
END.

1* R•• ta .... ''riln •• U

bu"." _,_""

.dd" •••

*'

ELSE IF (RCB AND OEFHJ-DISC
nEN DOl
STATIDNJJTATE-DISCDNNECT_SJ

TlS-. SIU~"ITJUFFERCO)1
IF CRCa AND IOH)<> 0
TtEN DOl

4
4
4

'*

R•• tar. t".n •• U: bu,h" .t."t .dd" . . . .,

TaL-OI
CALL X"IT_UNNUI"I8EREDCUA)J

113
114

3

liS
116

3
3

118
119

4

TIF-.,

4

RT8-S,

END.

END.

ELSE DOl

I . R.ceive cont:rol but. is sa •• thing oth." than D]SC a" SNR" . ,
IF CRCa AND 10tn 0 0
llEN DOl

296166-47

14-53

intJ

RUPITM·44

:20: 24: 47

PL/I'I-51 CDtPILER
I~O
I~I
I~
1~3

••

4
3

1~4

0./20/83

PAGE

DO WHILE NOT BI,

END,
END,
END,
END INJR"'JlTATE,

CO.....NDJlECODE: PROCEDURE ,

I~'

~

126

~

IF (RCB AND OEFHI-sNR"
THEN CALL SNR"JlEBPONBE,
ELSE IF CRCI AND OEFH)-DlSC
THEN DO,

1:111

~

130
131

-3
3

133
134
131
136

4
4
4
3

137

~

139

3

141

4

143
144
141
146
147
14B
14.
ISO
1.1

••
••
••

I'~

4

STATIOtCSTATE-DIBCONNECT_9,
IF CRca AND IOH)OO

THEN DO.

END,
ELSE IF CRCB AND OEFH)-TEST
THEN 001

IF

~-

I~

163

3
3

16.

3

*'

TBL-eJ,

CALL XI'IIT_UNNU...EREDCTEST OR 1OH),

'END,
ELSE DO,

'*

I f no BOY.
TIL....FL'

und received 1 flteld ... ck to pri ••,.,

TBS-R.S,
CALL. K"IT _UNNUPIIEREDCTEBT DR 10M) I
nB-.8IU_X"ITJlUFFERCOh
/. R•• tD,.. TBS

END,

'* I'

an I fir •••

III., p.ndin,.

..t

it

II,

*'

*'

_,.in .,

IF Kf1IT JlUFFER..EftWITV-O

THEN DO,

•

160

An,.nd if ,alhd ./
BOY-I. BEND THe: TEST RESPONSE WITHOUT AN I FJELD

THEN DO,

I
I
I

3
3

i.
/. FOR
caov-iou

IF CRCB AND lOH)>O
THEN 001

1.4
I ••
1.6
117
I.B
II.

'
TBL-o,
CALL X"IT _UNNUIIIIERED (UA I,

END,

TBL-IjRNE.-LENOTHI
TBF-l,
.

I-

•4

END,

ELSE IF CRCB AND OIH) • 0 /. Kich' out o. the AUTO .ode beceu ••
an 1 'ra...... received whUe RPB • 1 ./
llEN DOl
Apt. II
IF X"IT JlUFFER..EIPTV • I
THEN TIL. O.
TBF • I.

'*

Send an AUTO .ad.

1" • • pon ••

*/

296166-48

14-54

RUPITM-44

PL., .... ,' CDI'tPILER

,....

167

3
3

168

2

169

20: 24: 47
RTS -

ELSE CALL X"ITJRf'lRC!JNASBJONED_C),

, . Rec.ived an undwf1n.d Dr nat tllpl ••• nte. co_and

*'

END CDfl'tANDJ)ECODE.

2

a

DECLARE

172
173

2

a

SI-o.
IF STATJONJITATE<> I_T.-s /. Must b. In NON-AUTD,lIoda

175

3

183
184

6

11

170

I.

PAE

END,

171

177
178
179
180
181

09/20/83

StU_tNT: PROCEDURE INTERRUPT 4.

AUXILIARY,

BYTE

THEN DO,

'*

IF R8£-0
Received • •" ••• ?
THEN DO,

,,,
,

*'

Qiv. " •• pon •• _,

DO CASE STATIDNJlTATE.

CALL IN...DISCONNECT ....sTATE.
CALL INJRIIIJlTATE.
END.
R8E-l,
END.

4
4
3
3

RETURN,
END.
/ . %f tt.. P"ol" ....... cb . . 'hie ,oint. STATIONJITATE-I_T...S

which •••na th BtU .Uhe........

01'

still h

in the AUTO I1DDE

A....o

18'

2

187

3

IF (RCB AND OEFH)-UIBC
THEN CALL COfI'IANDJ)ECODE.

189

3

191
. 192
193
194

4
4
4
3

ELSE IF USER....sTATE-CLOSED_S
Tt-EN DO,
T8L-D •
CALL XMIT_UM«JMIEREDCREGJ)ISC),
END.
ELSE IF BEB-I
TIEN CALL X"IT JRIIA(BES..ERRl.
ELSE IF BOY-I

IF

*'

THEN DO.

196

3

198

4

201
202
203
204

aoo

4
4
3
3
3

20'
206

3
3

208

3

THEN DO.,. DON1T SEND FA . . IF A TEST WAS RECEIYED4t1
IF CRCB AND OEFH)-TEST
THEN CALL C~...DECaDE.
a.BE
CALL XMITJRrtR (BUFF_OVERRUN) I
END.
ELSE CALL CDf'l'fANDJ)ECQOE,

RIE-I,
END;
ELSE DO,

'*

PIJ8T STILL. IE IN AUTO t100E . ,
IF TBF-o
THEN X.. ITJlUFFERj:MPTV-I,
, . TRANSI'IITTEO It FRNE . ,
IF RBE-o
THEN DC,

296166-49
PL/tt-DI CCl'lPILER

.210

4

211
212
213
214
215
216

4
4
4
4
3
I

20: 24: 47

09/.20/83

PAQE

RIP-I, I. RNA STATE . ,
RIE-I, , . RE-ENABLE RECE1VEA . ,
CALL 81UJlECVCRFL.J
RIP-O, I. RR STATE . ,

END.
END.

217

_NlNOS:
4 IS TIE HIGHEST USED INTERRUPT

lIIIDULE IN'CRItATlON:
CaDE SIZE
CCNBTANT BIZE
DIRECT YARIABLE SIZE
INDIRECT YARIABLE SIZE

In aUE
BIT-ADORESSABLE SIZE
AUXILIARY YARIABLE 81ZE
MK Utu.. STACK 81 ZE
REOISTER-BANKeSl USED:
460 LINES READ
o PRDaR,," ERRORes)
END .IF PL'"-51 CCllPILATlON

eSTATlC+ClllERLAYABLEl
- O.i28FH
6550

- OOOOH
3FH+02H

OD
63D+

3CH+OOH
OIH+OOH

6OD+
tD+

OOH+OOH

OD+

.OOODH

6D

.OOI7H
01 2

.i23D

aD
00
00
00

296166-50

14-55

7

intJ

RUPITM-44

18,~,

181S-11 PL/....51 Yl.0
CDf'PlLEA INVOKED BY:

09/19/83

PACIE

: '2,: unat. .• T'C'

: '2: pl_"

STITLE
C~Applic.t:lon Module: Alunc/SDLe P"otoeat convert.,.'
t ... ltul
S"".,ilh,.'.n. CO)
5

53

u •• ,. ••ocl: do.
tNDLlBT
DECLARE
LIT
TRUE
F ....SE

FIlREVER

Eac

LF
CR

.8

IEL
EN'TY

INUBE
PULL

UBER_STATE_CLOBEO
LINKJ)ISCONECTED
IlllERFLOW
DATA_TR_ITTED

LITERALLY
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

~

'LITERALLY',
'OFFH'.
'DOH',
'WHILE
,'18H',
'OAH',
'DOH',
'OSH',
'07H',
'DOH',

1':

"OtH'.
'02.4'.

'00II',
'OSH',

'02.4'.

'03H',

/ . BUFFERS . /

.YFFERJ.ENOTH
LIT
8IU-,,"ITJlYFFERCBYFFERJ.ENOTH.
BIU.."RECYJlUFFERCBUFFERJ.ENOTH.
FIFD_Tea",.
BYTE
IN-'TR_T
BYTE
OUT-'TR_T
.YTE
IUFFERJlTATUB_T
BYTE
FIFD.."RCa",.
BYTE
IN-'TR.."R
BYTE
OUT-'TR.."R
.YTE
.UFFERJlT...TU8.."R
BYTE

LENGTH
CHAR
I
UBMT_CHD

DE8T1N1\TlDN~DREBa

IEND......T..
RESULT
PRJEBSAOE_INDEX
ERRJEBBAOE-'TR

IYTE
IYTE
BYTE
BYTE
BYTE
BYTE
.YTE
BYTE
WORD

'60'.
.YTE.
EXTERNAL
BYTE
EXTERNAL.
AUXll.IARY.
AUXILIARY,
AUXILIARY,
AUXILIARY,
MJJClLIMY,

AUXILIARV,
AUXILIARY,
AUXILIARY.

AUXILIARY,
AUXILIARY.
AUXILIARY.

AUXILIARY.
AUXILIARY,
"UXlLIARY,
AUXILIARY,
AUXILIARY.
MJXILJARV.

PMUTVe*) BYTE CCIGTANT(LF.CR. 'Pal'itlJ E,.,.o," netechd'.LF.CR,OOtU.
FRNEC_) BYTE CDNSTNfTCLF. CR. 'F"•• :ln, E""o1' D.tlct.d'. LF. CA. OOln.

296166-51

14-56

inter
PL/tt-!U COI1PJLER

RUPITM·44

Application t1odul.: ",..,nc/SDLt Protocol

canve,.,!".

IS: '0:'3

09/19/83

PAQE

OYERJtUNC.) BYTE CONSTANTCLF, CR. 'Ov.r ... un Error Dehc'hd I, LF. CR. 0)'

LINKe_» BYTE CONBTANTCLF.CR. 'Unable to Oet Onlin.'.LF.CR.OOH),
DE8Tj.DDRC*) BYTE CONSTANTCCR. LF. LF.·

'Ent.,-· the de.tination addre •• : _',

as.

88. 0).

DJliDDRj.lCKC.) BYTE CONBTANT5
Tt£N TEI1P-o.

4

00.

4
4
4

END.

a.,

4
4

37
38

4

39

4

40
41
4"
43

4
4
4
4

44
45
46
47

4
4
4
4

/. 4800./

48
49"

...

4
4
4
4

/. 9600./

52

4
4
4
4

/. 19200

55
56

/. ft •• ,

DO CASE TEI'IP I

32

53
54

TlttER_S-a3H.
TIttER S-2OH,"

-

TlI'IER_1-20H1

TIPIER_l-o'H.
END.

'*

2400./

DO.

TIPIER_I-bOH.
lUtER_I-OaHI

END.
DO.
TII'IER_l-:1OH.
TlI'1ER_l-olH.

END.
DO.

TI"ER_l-o'HI
TII'IER_l-o.

END.

*'

DO.

TlttER_1-33H1

TIPIER_I-O.

END.
END.

So,t.,.,..

*'

57

USMT-.8TATUS-O,

118
59

USMT_BTATUB-O,
USNIT_STATUS-O,

60

UIIMT_STATUB-4OH.

61
62
63

TEJIP~HI
/. D.tel".ln. the per it, end. of stop bU • • /
TE".-TEIF OR (P, AND 3OHl,
IF STOP..In-I
THEN ~.TaP OR oea.."

65

PAGE

, . 300 . /

33
34
35

51

09119/83

.,

on

0"
28
a1'

18: '0: 53

"'pplie.tion P1oduh: "' ... nc/SDLe PTotocal conv."hT

./.

pOIIIII.,.-on r . . . t fot' B25.1'"

ELSE TEtP-TEPIP OR 40H.

'*

*'

66
67

UBART..BTATUS-'EPIP,
USART "0111. Wa'r"cI
USMTJlTATUS. USART_CI'ID-27H'/ttUSMT Co . . . nd Ward RlB. RIE. DTA. l.EN-le,

68

STIID_FH.

296166-54

14-59

4

inter

RUPITM-44

Applie.Uan t1aduh: ,.."nc/SOLC PT'otocol con..,.,.t.,.

69

2

70

2

71

2

BUFFER..8TATUS_', 8UFFER':'STATUS..R- ENt,y,

72

2

CAU.. PDWER_tw_DI

73

2

74

2'

75

2

76

18: 110:'3

09/19/83

PAGE

/* Inti.Un Fh.s ./

SENDJ)ATA-O , . Thn continu. to . . nd the . . . . . . . _,
THEN DO,
USARTJ)ATA. ftESSADECEARJ£SSADE_INDEXJ,
ERR..,.MESSAQE_INDEX-EAR.)IEBSAOE_INDEX+I.

END,

'*

ELSE DO,

I f •••••, . h dan. ,. ••• t ERRORJLAO .nd .hut aff int.,.rupt "
ERADAJLAQ-OI
IF BUFFER_STATUSJI • EMPTY
THEN Ext-O,
ENOl

FIFO,s ...ptU

END.

ELSE UBARTJJATAraFIFO-"_OUT.
END USART..x'UT_INTI

"

SIUJlECY: PROCEDURE (LENGTH) PUBLIC USING I,

.22

2

DECLME LENGTH
I

.23
.24
.25
126
127

3
4

DO 1-0 TO LENOTH-l,

4

3
3

129

END.

BYTE.
BYTE

AUXILIARY,

DO WHILE BUFFER_SrArUSJlaFULL, , . Ch.d to . . . i f fUa h
END.
CALL FIFD..JI_'NCSIU..JIECYJlUFFERU l l.

hll

*'

END SIU..JIECY.

129

2

130

2

DECLARE CHAR

131
132
133

2
2
2

FIFD_TC IN""pTR_Tl-tHAR.

135

2

IF IUFFERJlTATUS_T-E. . TY
TfoEN 8UFFERJlTATUS_T-lNUSE,
ELSE IF CCIUFFER_STATUS_T-INUSE) AND CINJlTR_T+aO-OUT....pTR_T»
THEN DO, '* Stop ,..c.ption udnl eTa */
USAATJlTATUS, USART_CI'1D-USART_CI'1D AND NDT(20H),
IUFFERJJTATUS_T-FULL.
IF SENDJ)ATA-O
THEN SENDJ)ATA-:L,,*U ttl. buff.,. is full .nd na LF

FIFO_T_IN: PROCEDURE (CHAR) USING .2,

BYTE.

INJTR_T-INJlTR_T+:L1
IF CHM-LF

THEN BENDJ)ATA-SENDJ)ATA+l,

137

2

139
140
141

3
3
3

143
144

3
1

h•• b •• n ,..c.iv.d then •• nd d.t.
END.

*'
296166-56

14-61

*'

intJ

RUPITM_44

PL/.... I,. CDI'IP ILEA

FIFD_T _OUT: PROCEDURE 8Y.TE

14'

2

146

2

DECLARE CHAR

147
148
149

2
2
2

CHM-FIFO_T([JUTJTR_T1 J
DUTJlTR_T-ouTJTR_T+11
IF ~T:Oi.INJTR_T

1S1
1'2
153
1'4

3
3
3
3
3
2

ISS

1'6
1118
1'9
160
161
163

09/19/83

PADE

I

,.UXILIARV,

IYTE

'*

Then FI~_T is ••pt'it

*'

E"-O,

IUFFER_STATUB_T-EMPTY,
SEHD.J)ItTA-O.
E~ll

END.

ELSE IF CCIUFFER.-sTATUS_T-FULL) AHD CDUTjTR_T-ao-IN~TR_n)

THEN DO,
USART.-sTATUS. USART_CHD-usART _CHD DR 2OH.
8UFFER-.sTATUB_'-INUSE, '

16~

3
3
3
2
2
1

END FIFO_'_OUT.

16'

2

ERROR: PROCEDURE (STATUS) USINO 21

166

2

DECLARE STATUS

167

2

169

2

IF (STATUS AND OBH)OO
TI£N ERRJlESBAOE-PTR-. PARITY.
ELSE IF (STATUS AND lOH)<>O
TI£N ERRJ£SSAOE..pTR-. OYER-"UN.
ELSE IF CSTATUS AHD 2011)00
TIEN ERR.JIEBSAOE..pTR-. FANE,

ENOl
IF (CHAR-LF AND SENDJ)ATA>O) TIEN SENDJ)ATA-SENDJ)ATA":I.

RETURN CHAR,

BVTE,

171

2

173

2

UBMT_STATUB-CUSART_Ctm OR IOHh

174
175
176

2
2
2

ERR..,.I'IE88AQE_INDEX • O.

'*

ERRDRJ'LAo-l.
Ext-',

/. R••• , .",.01"

TU'f'n on TI Int.rrupt-

"*,. on USMT . ,

*'

END ERRDR.

177
178

2

179

2

180
181
182
183
184

18: :10: 53

AppHe.tio" f1Dduh: .... unc/sDLe P'r'otocol cony_,.t.,.

2
2
2
2
3

LINKJUBC: PROCEDURE

I

DECLARE HESSAOE"pTR
fCESSAOE
oJ
EXl_STORE

WORD

AUXILIARY.

BASED

~8SACIE"pTR C1

BVTE
BlT.

~UXILIARY.

)

BYTE

CONSTANT,

EXl_STOREaEUI
/. Shut; off •• \lnc tr_n,.it int..,. ... upt . /
EXl-OJ
~OEJTR-. LINK,
~-O.

DO YULE (t£SSADE"'?<>O)J

296166-57

14-62

7

inter

RUPITM·44

PL/I1-~l

.e
.BO
.87
.BB
• 89

190

COttPtLER

••

DO WHILE WSART_BTATUS AND 01H)-O,

.92

CD:

3
3
2

PROCEDURE (CHAR) USING 21

DECLARE CHAR

BYTE,

DO WHILE CUBART_BTATUS AND DIH) • 0,

ENOl
UBMT ..DATA-CHAR,

END CO,

.97

CI: PROCEDURE BYTE U91NC1 2.

.98

2
3
3

DO WHILE CUSAAT _STATUS AND Q2H) •

200
20.

2

RETURN USARTJ)AT/u

.....

*'

, . R•• to ........ nc trans.it intnrupt . /

Ext-EX I_STORE,

END LINKJ)lSC.

'9.
'9'
'90

PAGE

END,

'9' •
2
2

/. W.U fa1' TIRDY on USART

END,

09/19/83

UBMTJ)ATA-P£SSAOEeJ) ,
oJ-..,+l •

3
3
3
2

.93

IB: SO: S3

"'ppUCA'tiO" l1oduh: "s .. nc/SDLe Protocol convert.,-

202

01

ENOl
END ell

203

2

204

2

DECLARE CHAR
I

20'

2

LO: CIiNt-CI,

206
207

3
3

209
2.0
211

2
2

2.3

2

OETflX: PROCEDURE BYTE USJNQ 21
BYTE

BYTE

AUXILIARY.
AUXILIARY,

DO 1-0 TO Uh
IF CHAR-HEX_TABLE( I)
lIEN GOTO L1,
END,
Ll: CALL COCHEX_TABLE(I»I

IF 1-14.
THEN OOTO LO,

END GET.} 0,
CALL CQCttEBSAOEC J))J
1-1+1,

296166-58

14-63

8

intJ

RUPITM-44

18: SC!: 53

PL/....II CIM'IU!R

221

3

222

PIICIE

ENDI
END OUTPUTJEftAIlEI

223

2

224

2

f'ENU: PROCEDURE URINQ 2,
DECLARE I

IYTE
CHAR
BYTE
BTIlTlON.JIDIIRESS BYTE

AUXlL.IARY,

AUXIL.IARY,
AUXILIARY,

STMT:

22'

2

226

2

227
228

3
3

DO 1-<1 TO 41

230

3

ENDI

231
232

2
2

"l: CALL COUENU_CHMCI)I
IF 1-'
ntEN IIIITD ItOI

234

3

DO CIISE II

235
236

4
4

DOl

237

4

.STATIDN.,ADDRESS-sHLCOETJEI, 4) I

238

4

STIlTION....ADDIIESSoCBTIlTION....ADDIIEBB DR IlET_HEXII

23'1

4

STAIIoSTIlTlON....ADDIIESSI

240

4

CIILL DUTPUTJEBSllClEC. S.JIDDlljlCKII

241
242

4
4

CALL COCtE'X_TMLE(SHIUSTATION.,.ADDRESS, 4)),
CIILL CDlHEX_TIllLEIOFH lIND BTIlTlON....ADDIIESSI II

243
244

4
4

ENDI

24'

4

DOl

246

4

247

4

DE8T1""TIDN~J)DRESS"""COETjEX,

248

4

DESTlNllTlON.JIDDIIESS-IDESTlNIITION.JIDDIIEBB DR IlETJEX II

249

09/19/83

CIILL OUTPUTJIIEIISIICIE (. BIONJINII

IF CHARof1ENU_CHII/IUI
TlEN ODTO "I.

CIILL DUTPUTJESSIICIEC.BTAT....ADDllII

CIILL DUTPUTJEBSIIOE('IIDDlljlCKJINJI

CIILL DUTPUTJtESSIIIIE(. DEBT.JIDDIIII

4),

CALL OUTPUTJ£B8I\CIE(. D.JIDDlljlCKli

296166-59

14-64

9

inter

RUPITM_44

18:

Appl'catlon Pladul.: " ... ne/BDLC P"o'ocol conv.,.t ...
200
25,1

4
4

252
253

4
4

254
255
256
257

4
4
4
4

258
259
260
261

4
4
4
4

262

3

263

3

53

09/19/83

PAGE

CM.L CDCHEX_TAlLECSHRCDEBTlNllTlDN.J'I)DREBB, 4J J)'

CALL COCHEX_TAIILECOFH AND DEBTINATlDN......DRESSII.
CALL DUTPUTJEBSAGEC, ADDR.J\CKJIN),

END.
DO.

CALL OUTPUT,.HESIlllQE C. FIN).
CALL OPEN,
END.
DQ.

CALL OUTPUT.,JESSAOEC. FIN),
CALL CLOSE'

END.
CALL DUTPUTftBBAGEC. FJN),
END. ,. DO CASE ./

END I'ENU.

264
260

2

266

2

USARTJlECY_INT: PROCEDURE INTERRUPT 0 USING 2,

DECLARE CHAR
STATUS

BYTE

AUXILIARY.

BYTE

AUXlL.IARY,

2
2
2

CHAR-uBARTJlATA.
STATUS-UllllRTJiTATUS AND 38H.
IF STATUSOO
THEN CALL ERRDRCSTATUSt,

271

2

Et.SE IF CHAR-ESC
THEN CALL PlENU.

273
274
275

3
3
3

ELSE DO,

277

3

267
268
269

~Q:

278

CALL FIFO_T_INCCHAR',
IF ECHD-o
THEN CALL COCCHAR),
END.
END USART JlEC":'_INTI

279
2BO

281

2
2

2B3

4

284
285
2B6
287

4
3
3
4

DO FOREVER,
IF SENDJlATA)O
THEN DQ.
DO WHIL.E

END.

NOTCX"IT.JIUFFER~TV)I

I.Wan until BIU_XPlIT_BUFFIf'
is ••

-I.

p'"

*'

LENGTH. CHAR
SIU_X"IT..BUFFER CO'.DEBTIWATIQN..ADOREBB,
DO WHILE I CCHAR<>LFI AND CLENGTHEI1PTYII.

296166-60

14-65

10

intJ

RUPITM·44

18:
_

4

290
291

4
4

:!92

3

Ll:

293

3
3

RETRY:

29.
297
29B
299
300
301

4
4
4
4

302

4
4

~

307
308
309

310
311
312
3'3

0."9/83

PAGE

LENOTH-LENOTH+I.
END,

the ,.".In.1 .is ..... ,." than 8UFFER~NOTH ellar, ••nd the
fh,t IUFFERJ.,ENOTH eb.,., n.n .. nd the " •• t, line. the SIU bu'
:Is an1u 8UFFERJ,.ENOTH ltV'.' . /

/. I f the Un • • nte" ••• ,

303
304

S3

CHAR-FIFO_T_OUT.
.'
SIU_X"ITJlUFFERCLENIITH'oCHAII,

289

294

~O:

4

f.,.

1-0, , . U.. J to cOUnt: the nUllb.,. of un.ute •• lul

tran •• Us ./

'*

JlESULT-TAANSMITCLENOTHJ I
Send th . . . . . . . . . ,
IF REBULT<>IUITA_TRANIIIIITTED

,. w.n

THEN DD,
SO' ..I.e far Un. to connect then
WAIT-I,

*'

TRG-Il
DO WHILE WAIT,
END,

S
S

TRo-O.
1-1+1.
IF 1)100 THEN DO.

S

1,* WaU 5 .. c to , . , on 1:I.n.

et,.

'.nd ."1'01" ••••••• to t.rlllinel
and
all*i" .,"

'''\1'

CALL LINKJ)ISC,

S
S
S

GOTO Ll.

END,

.-4
3

1:", ••• in

THO-3CH,
TLo-CMFlh

ODTO RETRY,

END,
END,

2
1

IIMNINOB:
2 ,IS THE HIOHEST USED INTERRUPT

IIDDULE .NFIIII....TICIN:
CODE B1ZE
CONSTANT SIZE
DIRECT VARIABLE SIZE
INDIRECT VARIABLE B1ZE
lIT S1ZE
IIT-ADDREBBABLE SIZE
AUXILIARY YAlUABLE SIZE
....XlIIUII STACK SIZE
,EOISTER-I_CB' USED:
713 LINES READ
o PRDORN'I ERROR CB.
END OF PL/"-SI CDIII'ILATlDN

(STATIC+OVERLAVAILE)
• 0612H
17141)
• OlC~
4630
OOH+OSH
00+
OOH+OOH
OD+
02H+OIH
2D+
OOH+OOH
OJ)+
.021FH
543D
• OGaBH
400

SD
OD
ID
OD

012

296166-61

14-66

11

RUPITM_44

PL/H-Sl COI'fPILER

RUPI-44

ISIS-II PL/I't-91 YI. 0
CDI'fPILER INYDKED BY;

PrimaT'~

ShUan

.:!O; 47: 13

09/26/83

PAGE

; F2: PLH:51 : F2: PNDTE. SRC

'TITLE

C 'RUPI-44 Prima,,\! ShUon')

.DEBUG
'REQIBTERBANJI,CO)
MAIN'MOD: DOl

*'

/. To •• v. pape,. the RUPI registers are not listed. but this is the statement
und to include thelll:

'JNCLUDE (: f2: REQ44. Del)

aNOLIST

DECLARE LIT

LITERALLY

FOREVER

'*

'LITERALLV',
'OFFH',
'OOH',
'WHILE 1'1

LIT
LIT
LIT

TRUE
FALSE

SDLe COMMANDS AND RESPONSES

DECL.ARE SNRM

LIT

UA
DISC

LIT

*'
'93H',
'73H',
'53H',
'lFH'.
'97H',
'53H',
'33H',

LIT
LIT
LIT
LIT
LIT
LIT

DK

FRMR

REO_DISC
UP
TEST
RR

LIT

'OF3H',
'ItH',

RNR

LIT

'15H'.

1* REMOTE STATION SUFFER STATUS
BUFFER..READY
BUFFER_NOT _READY

'*

LIT
LIT

STATION STATES
DISCONNECT_S
LIT
QO_TOJUSC
L.IT
I_T _S
L.IT

*'

'0',
'1'.

*'

'OOH'.
'01H',
'02H',

1* LOGICALLY DJSCONNECTED STATE*,
/* INFORMATION TRANSFER STATE */

/* PARAMETERS PASSED TO XMIT _I_T _S */
T_I_FRAHE
LIT
'OOH',
T-,RR
LIT
'OIH',
T~NR
L.IT
'02H',
/* SECONDARV STATION IDENTIFICATION */

NUMBER_OF _STATIONS LIT
'2',
SECONDARY _ADDRESSES(NUMBER_OF _STATIONS»
CONSTANT ( ~5H, 43H»,
BYTE

296166-62

14-67

RUPITM·44

PL'f'I-:U COl1PILER

RUPI-44 Prima,." Station'

20: 47: 13

09/26/93

P~gE

RSDCNUI'1BER_OF..sTATIONS) STRUCTURE

(STATION_ADDRESS
STATION_STATE
NS
NR

BYTE.
BYTE.
BYTE.
BYTE.

BUFFER_STATUS
INFO_LENGTH

BYTE.
BVTE.

DATIII(64)

BYTE)

'*

*'

VARIABLES
STATlDN_NUrlBER
IVTE
RECYJ'IELD_LENQTH
BYTE

WAIT

'*

BUFFERS . ,
SIU_XMITJUFFER(04)

POWER_ON:

2

•

2

10
11
12

2
2
2

13

I"
15
16
17

*'

AUXILIARY.
AUXILIARY,

BYTE
BYTE,

IDATA.

J

BYTE

AUXILIARY.

T8S-. SIU_X''lIT_BUFFERCOJi
RaS-. SIU..RECVJlUFFER(O),
R8L-64,
64 a"h reedv. buff.-r

'*/. En.bh tbl' SIU'. receiver*' ./

RBE-l,

00 1- 0 TO NUMBER_OF_STATIONS-I,

3
3
3
3

18

RSDel).

STAT]ON_ADDRESS.SECONDARY~DDRESSES(

I),

RSDC I). STATION_SlATE-DISCONNECT_S;
RBD( I ). DUFFER_STATus-aUFFER_NOT-.READY'
RSD( I ). INFO_LENOTH-O,
ENOl

1.
20

2
2

22
23

2
2

2.

PROCEDURE

DECLARE I

The .. htu .. o. th • • • conh1'V .t.tiDn. bu'''"

AUXILIARY,

BIT.

SIU~ECYJlUFFER(64)

9

'*

"

SMD-54HI 1* Using DPLL, NAZI. PFS. nMER 1, • 62.5 Mltps
TI'IOD-21H;
TH1-OFFHI
U~. timer 0 for receive tim. out. int~r"upt
TCON-4DH,
IE-82H;

'*

*'

*'

END POWER_ON.

2"
25

2

26

2

27
2S

2
2

.MIT: PROCEDURE (CDNTRDL.-BVTE);

DECLARE CONTROL_BYTE

BYTEi

TCa-CONTROL_BYTEi
TBF-ll

296166-63

14-68

2

RUPITM_44

PL/M-51 CDMP ILER

29
30
3'
32

RUPI-44 PrilllArv Station

09/26/93

PAGE

RTS-.,

2
3
3
2

33

20: 47: 13

DC WHILE NOT SI;
ENOl

BI-O,
END )1"11,

34
35
36

2
2

,

TlP1ER_O_INT: PROCEDURE INTERRUPT 1
WAIT-O,
END TIMER_O_INTI

37

2

TIME_OUT: PROCEDURE BYTE,

38

2

DECLARE

BYTE

USING II

'* Tillie_out returns true
AUXILIARY,

if' there .... n't
.. flr.me rllceivlld within 200 m•• c.
If th.re w..... fr.lmll receivlld within
200 1II •• e then time_out returns , .. 1 ••.

*'

DO 1-0 TO 3,

39
40
4,
42
43
44
45

3
3
3
3
4
4

47
48

4
3

WAn-II
THO-3CH,
TLO-OAFH,

TRO-I,
DO WHILE WAITI
IF SI-l
THEN COTD T _0 I,
END;

END,

RETURN TRUE,

49
50

51

2

Sl-Ol
RETURN FAL.Se,

52

END TU1E~OUT;

53

SEND_DISC: PROCEDURE,

54
55
56

2

TBlcO,

2
2

CALL XMIT(DISC),

57
59
60
6'
62

3
3
3
3
2

IF TIME_our-FALSE
THEN IF RCO-UA OR Rca-OM
THEN 001
RSD C9TAT ION_NUt1BER). BUFFER_ST '\TUS·BUFFER~OT.-READY I
RBO( STATION..NUI'1BER). STATION_STATE=-OISCONNECT_51
ENOl

63
64

2

SEND_SNR"':

65

2

TBl-Ol

PROCEDURE;

296166-64

14-69

3

inter

RUPITM-44

Pl/l'l-51 COMPILER
66
67

2
2

69

3

70
71
72
73

3
3
3
2

RUPI-44 PrimarV Station

20: 47: 13

09/;!6/S3

PAGE

CALL XI'IITCSNRI'I).
IF CTIME_our-FALSE> AND CRCa-UA)
THEN DO;
RSDCSTATJON_NUf1BER1. STATION_STATE"'I_T _51
RSD(STATJON_NUf'lDER)' Ns.-OI
RSDCSTATlONJruI'1BER)' NAcO,

ENO,
RBE-',

7.
70

2

7.

2

78

2

79
80

CHECK-fiS: PROCEDURE BYTE,

IF (RSDCSTATION":'NUMBERL NR-(SHRIHCD.l) AND 07H»
THEN RETURN TRUE,
ELSE RETURN FALSEI
END CHECK_NS;

2

CHECK_NR:

PROCEDURE BYTE,

_ls.

,,..me.

/ . Chu.k the Nt' f1hld of the ,.ltc:dvltd
If NsCP)+l-NrCS) then the frame
h •• b •• n acknQlllhdgd.
i f Ns(P)-NT'CS) then the fTame has not blten
ilcknollfledged. ehe r •• et th • • • conda,.v . /

8t

2

83
a.
ae
a.

3
3
3
2

as

2

a9

«

(RSDCSlATION_NUMBER), NS + 1) AND 07H) • SHR(RCB, 5»
THEN DO;
RSD(STATIDN-.NUMBER). NS-' CRSDCSTATION.-NUI'IBER). NS+l) AND 07H),
RSDCSTATlON_NUI'1BER). INFO_LENQTH-O;
ENOl
ELSE IF (RSDCSTATlON_NUf'fBERJ. NS <> SHRCRCB. 5J)
THEN RETURN FALSE,
IF.

RETURN TRUE,
END CHECK-.NR,

90

2

91

2

DECLARE

92

2

RSD (STATlON..NUMBER). BUFFER_STATUS-DUFFER_READV,

RECElVE:

PROCEDURE

I

BYTE

AUXILIARY.

I . If .n RNR III.S ".C.~V.d buff.,. _,t.tus 111111 be ch.nged in the sup.,.viso,. ..
fI,. .... decode s.ction 'uth.,. dOllln in this p,.oc.du,. ••• nlJ oth.,. " •• pon5e
me.ns the r.mDte st.tiDns buff.,. is l'e.dlj *1

93

2

ge

3

97
9S

••

*,"

IF (RCa AND 01H)-O
THEN DOl .1* I F,..me Rec.ived
IF (CHECK_HB-TRUE AND BDV-O AND CHECK.flR-TRUEJ
THEN DOl RSD(STATlON..NUMBERL NR-( CRSDC"STATION_NUMBER). NR+!) AND 07H)1
RDP-1i

296166-65

14-70

intJ

RUPITM-44

PL/M-51 COMPILER

RUP]-44

Pri/llaT'~

Station

••

20: 47: 13

09/26/83

PAQE

RECV-FIELDJ.ENQTH-RFL-l;

ENOl

100
101
102
103

3
3
2

10.

3

107

3

10.

3

110
III

3
3

113

4

114
115
tUt
117

4
4
:3
:3

llS

2

II.

ELSE RSOCSTATION_NUMDER). STATIDN_STATE.aOD_TO_DISCi
END;
ELSE IF CRCB AND 03HI=OlH
THEN DO;
Supervillory Frame received *1
IF CHECK_NR.zFALSE
THEN RSO(STATION_NUHBER I. STATION_STATE-QO_TOJHSCi

'*

ELSE IF «RCB AND OFH)-O'H) 1* thlf" RNR *1
THEN RSDCSTATION_NUMDER). BUFFER_STATUS-BUFFER_NOT _READY;
ENOl

,*

DT' unknown f,. .. m. received
.
I f FRMR was received check NT' for an
ac:knollJledged I frallle
RCB-SIU_RECY_BUFFER( 1) I
I-CHECK_NRI
ENOl
RSO (STATION_NUMBER). STATIDN_STATE"OD_TOJ)I SCi

ELSE DOi

Unnumber.d frame

IF RCB-FRMR
THEN Doi

,*

*'

*'

ENOl

END RECEIVE.

120

2

121

2

DECLARE

BYTE;

TEMP

IF TEl'IP-T_I_FRAME

122

THEN DOl

'* '*

*'

T1"an'lIit 1 frame
Transf.r the station buff.,. into int.rnal ram */

12.
125
126

4

••

DO TEI1P-O TO RBDCSTATIDNJlUI'1BER)' INFO_LENGTH-II
SIU_XMITJiUFFER (TEMP )"'RBOC STATJON-.NUMBER). DATA I TEMP) I
END;

127
129
12.
130

3
3
3
3

TEMP.CSHLCRSOC'STATIONJlUI'IBER).NR.,:U OR SHLCRSDCSTATION_NUMDERI,NS.l1 011 WltI.
rpL=RSO(STATlON_NUMBER). INFOj.ENGTH,
CALL XMlTCTEMPJi
IF TIME_OUT-FALSE
THEN CALL RECEIVE.

132

3

133
13'

3
3

13'

3

, . Build the.l f"alll. control field . ,

END.
ELSE DO;

'*

Transmit RR or RNR.'

IF TEMP=T_RR
THEN TEMP-RRj
ELSE TEHP ..RNRI

296166-66

14-71

inter

RUPITM-44

RUPI-44 Pri ... "u St.tion

PL,I'1-S1 COI1P]LER

20: 47: 13

09/26/83

PAOE

6

TEr1P.(SHL,tRSDCSTATlON_NUPtBEA), HR. 5) OR TEI1P),'
TBL-OJ

137
13B
139
140

3
3
3
3

142
143

3
I

ENDI
END X"lT_I_T_SJ

144

2

BUFFER_TRANSFER: PROCEDURE,

14~

a

DECLARE

146
147

3
3

DO 1-0 TO NUMBER_OF_STATlONB-l J
.
IF RSDe J). BTATIONjlDDREBS-SIU..RECYJlUFFERCO)
THEN OOTO Ttl

149

3

ISO

2

IS2
IS3
ISS

3
3
3
2

IS7
ISB
IS9
160
161
162

3
4
4
4
3
3

CALL Xl'tITnEI'F),
IF T111E_OUT-FALSE
THEN CALL RECEIVEI

I
oJ

BYTE
BYTE

AUXILIARV.
AUXILIARY,

ENDI

n:

IF I-NUI'IBERJlF_STIITIDNS

,_ If th • • dll" . . . . d .t.UDn doe. not: nU ••
tllen diu,lt'd the data */

THEN DOl
1~4

RIP-OJ
RETURNI
ENDI
ELSE IF RSDel), INFDJ.ENOTH-O
liEN DOl
RSDe I). INFD_LENQTH-RECYjIELD..LEHGTHI

DO "-I TO RECYjIELD-.LENOTH,
RSD( I), DATAf.J-l J-SIU..REC"_BUFFERhJ)J
ENOl

RSP-O,
ENDI

163

END BUFFER_TRANSFER I

164

BEOIN:
CALL POWER_ONI

I.'

a

I ••

,.7
16B

3
3
3

170

3

172

3

174

3

176

3

177

3

DO FOREvER I

DO STATlON_NUttBER-D TO NlR'tIER_OF'_STATIDNS-1J
STAD-RSDC STATION.JWt1BER). STATION..ADDRESSJ
IF R9DCSTATION_NUf'IIBER). STATION_STATE. DISCONNECT_S
THEN CALL SEND~"J
.
ELSE IF RSDCSTATIONJW"B~IU. BTATlON_STATE • OD_TOJUSC
THEN CALL SENDJlISC,
.
ELSE IF CCRSDCSTATlDN_NUPlBERL IflFO-.LENQTH>OJ AND
CRSDCSTAnON~UMBER). 8UFFER..BTATUS-BUFFERJ'EADV»
THEN CALL XMIT_I_T_SCT_tJRAl'IEl,
ELSE IF RBP-O
THEN CALL XMJT_I_T_SCT_RR),
ELSE CALL XMIT_I_T_SCT_RNR);
IF RUP-1
THEN CALL BUFFER_TRANSFER,

296166-67
PL/I1-51 COMPILER

20: 47: 13

IBI

PAOE

ENOl

17"
190

09/26/93

02

ENOl
END

MAI~MODI

WARNINgS:
1 IS- THE HIGHEST USED INTERRUPT

MODULE U"IIFORMAT10N:
CODe SIZE
CONSTANT SIZE
DIRECT VARIABLE SIlE
INDIRECT VARIABLE SI ZE
BIT SIZE
DIT-ADDRESSABLE SIZE
AUXILIARV VARIABLE SIlE
MAXIr-ftJM STACK SUE
REC'HSTER-BANK(S) USED:
456 LINES READ

o

(STATIC+OYERLAVADLE)
• 053DH
1341D
• 0002H
2D
40H+OiZH
64D+
4OH+00H
640+
01H+00H
10+
OOH+OOH
OD+
• 0093H
147D
• 0019H
25D

o

iZD
OD

00
00

I

PROORAM ERROR (S)

END OF PL/M-51 COI'IPILATION

296166-68

14-72

7

RUPITM Datasheet,
Application Note, Article
Reprint and Development
Support Tools

15

8044AH/8344AH/8744H
HIGH PERFORMANCE 8-BIT MICROCONTROLLER
WITH ON-CHIP SERIAL COMMUNICATION CONTROLLER
• 8044AH-lncludes Factory Mask Programmable ROM
• 8344AH-For Use with External Program Memory
• 8744H-lncludes User Programmable/Eraseable EPROM
SERIAL INTERFACE UNIT (SIU)

. 8051 MICROCONTROLLER CORE

•

•
•
•
•
•

Optimized for Real Time Control 12
MHz Clock, Priority Interrupts, 32
Programmable I/O Lines, Two .16-bit
Timer/Counters

Processor
• Boolean
4K x 8 ROM, 192 x 8 RAM
• 64K Accessible External Program
• Memory
Accessible External Data Memory
• 64K
4 ,..,s Multiply and Divide
•

Serial Communication Processor that
Operates Concurrently to CPU
2.4 Mbps Maximum Data Rate
375 Kbps using On-Chip Phase Locked
Loop
Communication Software in Silicon:
- Complete Data Link Functions
- Automatic Station Response
Operates as an SDLC Primary or
Secondary Station

The RUPI-44 family integrates a high performance 8-bit Microcontroller, the Intel 8051 Core, with an Intelligent/high performance HDLC/SDLC serial communication controller, called the Serial Interface Unit (SIU).
See Figure 1. This dual architecture allows complex control and high speed data communication functions to
be realized cost effectively.
Specifically, the 8044's Microcontroller features: 4K byte On-Chip program memory space; 32 I/O lines; two
16-bit timer/event counters; a 5-source; 2-level interrupt structure; a full duplex serial channel; a Boolean
processor; and on-chip oscillator and clock circuitry. Standard TTL and most byte-oriented MCS-80 and MCS85 peripherals can be used for 1/0 amd memory expansion.
The Serial Interface Unit (SIU) manages the interface to a high speed serial link. The SIU offloads the On-Chip
8051 Microcontroller of communication tasks, thereby freeing t~e CPU to concentrate on real time control
tasks.
The RUPI-44 family consists of the 8044, 8744, and 8344. All three devices are identical except in respect of
on-chip program memory. The 8044 contains 4K bytes of mask-programmable ROM. User programmable
EPROM replaces ROM in the 8744. The 8344 addresses all program memory externally.
The RUPI-44 devices are fabricated with Intel's reliable
aged in a 40-pin DIP.

+ 5 volt, Silicon-gate HMOSII technology and pack-

The 8744H is available in a hermetically sealed, ceramic, 40-lead dual in-line package which includes a
window that allows for EPROM erasure when exposed to ultraviolet light (See Erasure Characteristics). During
normal op.eration, ambient light may adversely affect the functionality of the chip. Therefore applications which
expose the 8744H to ambient light may require an opaque label over the window.

8044's Dual Controller Architecture
HOLCI
SOLC
port

231663-1

Figure 1. Dual Controller Architecture

15-1

October 1987
Order Number: 231663-004

inter

8044AH/8344AH/8744H

Table 1. RUPITM-44 Family Pin Description

-

vee
+ 5V power supply during operation and program

DATA TxD (P3.1) In point-to-pointor multipoint
configurations, this pin functions as data input!
output. In loop mode, it serves as transmit pin.
A '0' written to this pin enables diagnostic.
mode.

-

INTO (P3.2).lnterrupt 0 input or gate control
input for counter O.

verification.

-

INT1 (P3.3). Interrupt 1 input or gate control
input for counter 1.

-

TO (P3.4): Input to counter O.

-

SCLK T1 (P3.5). In addition to I/O, this pin provides input to counter 1 or serves as SCLK (serial clock) input.

-

WR (P3.6). The write control signal latches the
data byte from Port 0 into the External Data
Memory.

-

RD (P3.7). The read control signal enables External Data Memory to Port O.

VSS

Circuit ground potential.

PORTO
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and
data bus when using external memory. It is used
for data output during program verification. Port 0
can sink/source eight LS TTL loads (six in 8744).
PORT 1

Port 1 is an 8-bit quasi-bidirectional I/O port. It is
used for the low-order address byte during program verification. Port 1 can sink/source four LS
TTL loads.

RST

A high on this pin for two machine cycles while the
oscillator is running resets the device. A small external pulldown ·resistor (::::::8.2K!l) from RST to
Vss permits power-on reset when a capacitor
(:::::: 10p.f) is also connected from this pin to V cc.

In non-loop mode two of the I/O lines serve alternate functions:
-

RTS (P1.6). Request-to-Send output. A low indicates that the RUPI-44 is ready to transmit.

-

CTS (P1.7) Clear-to-Send input. A low indicates
that a receiving station is ready to receive.

ALE/PROG

Provides Address Latch Enable output used for
latching the address into external memory during
normal operation. It is activated every six oscillator
periods except during an external data memory access. It also receives the program pulse input for
programming the EPROM version.

PORT 2
Port 2 is an 8-bit quasi-bidirection I/O port. It also
emits the high-order address byte when accessing
external memory. It is used for the high-order address and the control Signals during program verification. Port 2 can sink/source four LS TTL loads.

PSEN

PORT 3

The Program Store Enable output is a control signal that enables the external Program Memory to
the bus during external fetch operations. It is activated every six oscillator periods, except during
external data memory accesses. Remains high
during internal program execution.

Port 3 is an 8-bit quasi-bidirectional I/O port. It also
contains the interrupt, timer, serial port and RD
and WR pins that are used by various options. The
output latch corresponding to a secondary function
must be programmed to a one (1) for that function
to operate. Port 3 can sink/source four LS LTT
loads.
In addition to I/O, some of the pins also serve alternate functions as follows:
-

I/O RxD (P3.0). In point-to-point or multipoint
configurations, this pin controls the direction of
pin P3.1. Serves as Receive Data input in loop
and diagnostic modes.

EA/VPP

When held at a TTL high level, the RUPI-44 exe. cutes instructions from the internal ROM when the
PC is less than 4096. When held at a TTL low
level, the RUPI-44 fetches all instructions from external Program Memory. The pin also receives the
21V EPROM programming supply voltage on the
8744.

15-2

inter

8044AH/8344AH/8744H

Table 1. RUPITM-44 Family Pin Description (Continued)
XTAL 1

XTAL2

Input to the oscillator's high gain amplifier. Required when a crystal is used. Connect to VSS
when external source is used on XTAL 2.

Output from the oscillator's amplifier. Input to the
internal timing circuitry. A crystal or external source
can be used.

'"

f};
::a
~:: c~

Go

Pl.0

vcc

P1.'

PO.O

ADO

PO.l

AOI

Pl1

PO.2

A02

P1 .•

PO.3

AD3

Pl.S

PO••
PO.S

AOt

Pl.7

PO.I

Alii

PO.7

A07

iiTs

m

'"

AST

l ".
'"
Ii
Z

~
~

i!I

~

~

i[M:

DATA

_CTI

~ -~

DATA

I/O

SCLK

TXD __

INTO_

..

-

=}@},...

iNfi.... ~

RXD

P3.0

Ii ·vpp

TXD

P3.1

ALE

INTO

P3.2

mJii

INTI

PU

P2.7

A15

TO

PU

P2.I

AU

T1

P3.5

P2.5

AU

Wi
iiii

P3.I

P2.•

A12

2 _
"'-'"

TO-., 0
SCLK..!!_ Go
WII_

.

iifi--

_

ADS

~

c

PIIOG

P3.7

P2.3

All

XTAL2

P2.2

XTALI

P2.1

AID
A,

VSS

P2.0

AI

231663-3

'"

231663-2

Figure 3A. DIP Pin Configuration

Figure 2. Logic Symbol
"II;"'l<"'!

C!CJ

()o

Nt')

O::ii:a:a:a::~~g~~~

Pl.S

39

PO.4

P1.6

38

PO.S

P1.7

PO.6

RST/VPD

PO.7

EA

P3.0

N/e

N/e

P3.1

ALE

P3.2

PSEN

P3.3

P2.7

P3.4

P2.6

P3.S

P2.S

231663-21

Figure 38. PLCC Pin Configuration
15-3

.

inter .

8044AH/8344AH/8744H

FREQUENCE
REFERENCE

r-I
I

DATA

I-+I-----<'~~.

I
I .........."r"I'"-.'

,L

I

~g~~DLC
COMMUNICATIONS

~--¥..----.I

I
I
I

TWO 16-BIT
TIMER EVENT
COUNTERS
INTERRUPTS L---,r-T"-...J

L...-r-""'T-'

~---

INTERRUPTS

1/0

I

I
I
I
I

I

L-_~-...J

I~-"'"

..J
CONTROL

COUNTERS

PARALLEL PORTS
ADDRESS DATA BUS
AND 1/0 PINS

231663-4

Figure 4. Block Diagram

FUNCTIONAL DESCRIPTION

• 4K bytes of ROM
• 192 bytes of RAM

General

•
•
•
•

The 8044 integrates the powerful 8051 microcontrollar with an intelligent Serial Communication Controller to provide a single-chip solution which will efficiently implement a distributed processing or distributed control system. The microcontroller is a selfsufficient unit containing ROM, RAM, ALU, and its
own peripherals. The 8044's architecture and instruction set are identical to the 8051's. The 8044
replaces the 8051's serial interface with an intelligent SOLC/HOLC Serial Interface Unit (SIU). 64
more bytes of RAM have been added to the 8051
RAM array. The SIU can communicate at bit rates up
to 2.4 M bps. The SIU works concurrently with the
Microcontroller so that there is no throughput loss in
either unit. Since the SIU possesses its own intelligence, the CPU is off-loaded from many of the communications tasks, thus dedicating more of its com~
puting power to controlling local peripherals or some
'
external process.

32 I/O lines
64K address space for external Data Memoiy
64K address space for external Program Memory
two,fully programmable 16-bit timer/counters

• a five-source interrupt structure with two priority
level,S
• bit addressability for Boolean processing
SPEClAL

FUNCTION

iii

REGISTERS
~

255

241 FlH

Fo.

E••

,

EO.
DB.
DOlt

RAM

ClI.

~iii

{D

INDIRECT.
ADORESS·
ING

co•

••H

.0H
A.H
ADH

.B.
ID.

'

00.

!!!

135

128 IOH

DIRECT
ADDRESS-

127

The Microcontroller

:"~ES",

BITS IN
Bl:A.

The microcontroller is a stand-alone high-performance single-chip computer intended for use in sophisticated real-time application such as instrumentation, industrial control, and intelligent computer peripherals.

(121 BITS)

t!!

32

,

127

120
0

A7
24 AD BANK3

REGISTERS

ING

A7 BANK2

!!.

A7

8' AD BANtU

~ :~

The major features of the microcontroller are:
• 8-bit CPU
• on-chip oscillatOr

.

BANKO

INTERNAL
DATA RAM

SPECIAL FUNCTION
REGISTERS

231663-5

Figure 5. Internal Data Memory Address Space

15-4

8044AH/8344AH/8744H

• 1 p.s instruction cycle time for 60% of the instructions 2 p.s instruction cycle time for 40% of the
instructions

Parallel 1/0
The 8044 has 32 general-purpose I/O lines which
are arranged into four groups of eight lines. Each
group is called a port. Hence there are four ports;
Port 0, Port 1, Port 2, and Port 3. Up to five lines
from Port' 3 are dedicated to supporting the serial
channel when the SIU is invoked. Due to the nature
of the serial port, tWo of Port 3's lID lines (P3.0 and
P3.1) do not have latched outputs. This is true
whether or not the serial channel is used.

• 4 p.s cycle time for 8 by 8 bit unsigned Multiplyl
Divide
INTERNAL DATA MEMORY

Functionally the Internal Data Memory is the most
flexible of the address spaces. The Internal Data
Memory space is subdivided into a 256-byte Internal
Data RAM address space and a 128-bit Special
Function Register address space as shown in Figure

Port 0 and Port 2 also have an alternate dedicated
function. When placed in the external access mode,
Port 0 and Port 2 become the means by which the
8044 communicates with external program memory.
Port 0 and Port 2 are also the means by which the
8044 communicates with external data memory. Peripherals can be memory mapped into the address
space and controlled by the 8044.

5.
The Internal Data RAM address space is 0 to 255.
Four 8-Register Sanks occupy locations 0 through
31. The stack can be located anywhere in the Internal Data RAM address space. In addition, 128 bit
locations of the on-chip RAM are accessible through
Direct Addressing. These bits reside in Internal Data
RAM at byte locations 32 through 47. Currently locations 0 through 191 of the Internal Data RAM address space are filled with on-chip RAM.

Table 2. MCS®-S1Instruction Set Description
Mnemonic

Description

ARITHMETIC OPERATIONS
ADD
A,Rn
Add register to
Accumulator
ADD
A,direct Add direct byte
to Accumulator
A,@Ri
Add indirect
ADD
RAM to
Accumulator
ADD
A,#data Add immediate
data to
Accumulator
ADDC A,Rn
Add register to
Accumulator
with Carry
ADDC A,direct Add direct byte
to A with Carry
flag
ADDC A,@Ri
Add indirect
RAM to A with
Carry flag
AD DC A,#data Add immediate
data to A with
Carry flag
SUBB A,Rn
Subtract register
from A with
Borrow
SUBB A,direct Subtract direct
byte from A with
Borrow

Byte Cyc

Mnemonic

Description

Byte Cyc

ARITHMETIC OPERATIONS (Continued)
SUSS A,@Ri
Subtract indirect
RAM from A with
Sorrow
SUBB A,#data Subtract immed
data from A with
Borrow
2
INC
A
Increment
Accumulator
INC
Rn
Increment
register
INC
direct
Increment direct
byte
2
@Ri
Increment
INC
indirect RAM
DPTR
INC
Increment Data
Pointer
A
Decrement
DEC
Accumulator
Rn
Decrement
DEC
register
DEC
direct
Decrement
direct byte
2
@Ri
DEC
Decrement
indirect RAM
Multiply A & B
MUL
AB
DIV
AB
DivideAbyB
Decimal Adjust
DA
A
Accumulator

2

2

2

2

2

15-5

2

1
4
4

inter

~OOI§Il.DIMJDOO~OOW

.8044AH/8344AH/8744H

Table 2. MCS@-51InstructlonSetDescrlptlon (Continued)
Mnemonic

Description

Byte Cyc

Mnemonic

Description

LOGICAL OPERATIONS

LOGICAL OPERATIONS (Continued)

ANL A,Rn

RL

A

RLC

A

RR

A

2

RRC

A

2

SWAP A

ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL

AND register to
Accumulator
A,direct
AND direct byte
·to Accumulator
A,@RI
AND indirect
RAM to
Accumulator
A,#data
AND immediate
data to
Accumulator
direct,A
AND
Accumulator to
direct byte
direct,#data AND immediate
data to direct
byte
A,Rn
OR register to
Accumulator
A,direct
OR direct byte to
Accumulator
A,@Ri
OR indirect RAM
to Accumulator
A,#data
OR immediate
data to
Accumulator
direct,A
OR Accumulator
to direct byte
direct,#data OR immediate
data to direct
byte
A,Rn
Exclusive-OR
register to Accumulator
A,direct
Exclusive-OR
direct byte to
Accumulator
A,@RI
Exclusive-OR
indirect RAM to
A
A,#data
Exclusive-OR
immediate data
toA
direct,A
Exclusive-OR
Accumulator to
direct byte
direct, # data Exclusive-OR
immediate data
to direct
A
Clear'
. Accumulator
A
Complement
Accumulator

2

3

2

Byte Cyc

Rotate
Accumulator
Left
Rotate A Left
through the
Carry flag
Rotate
Accumulator
Right
Rotate A Right
through Carry
flag
Swap nibbles
within the
Accumulator

DATA TRANSFER

MOV A,Rn
MOV
2

MOV
MOV
2

MOV

2

3

MOV

2

MOV
MOV
2

MOV
MOV
MOV
2

MOV
2

MOV

3

2

MOV

15-6

Move register to
Accumulator
A,direct
Move direct byte
to Accumulator
A,@RI
Move indirect
RAM to
Accumulator
A,#data
Move immediate
data to
Accumulator
Rn,A
Move
Accumulator to
register
Rn,direct
Move direct byte
to register
Rn,#data
Move immediate'
data to register
direct,A
Move
Accumulator to
direct byte
direct,Rn
Move register to
direct byte
direct, direct Move direct byte
to direct
direct,@Ri Move indirect
RAM to direct
byte
direct,#data Move immediate
data to direct
byte
@Ri,A .
Move
Accumulator to
indirect RAM
@Ri,direct Move direct byte
to indirect RAM

2

2

2

2

2

2
2

2

3

2

2

2

3

2

2

2

intJ

~OO~!LOfMlOOO&'OOW

8044AH/8344AH/8744H

Table 2. MCS®-S1Instruction Set Description (Continued)
Mnemonic

Description

DATA TRANSFER (Continued)
MOV @Ri,#data
Move immediate
data to indirect
RAM
MOV DPTR,#data16Load Data
Pointer with a
16-bit constant
MOVCA,@A+ DPTR Move Code byte
relative to DPTR
toA
MOVCA,@A+PC
Move Code byte
relative to PC to
A
MOVXA,@Ri .
Move External
RAM (8-bit addr)
toA
MOVXA,@DPTR
Move External
RAM (16-bit
addr) to A
MOVX@Ri,A
MoveAto
External RAM
(8-bit addr)
MOVX@DPTR,A
Move A to
External RAM
(16-bit) addr
Push direct byte
PUSH direct
onto stack
POP direct
Pop direct byte
from stack
XCH A,Rn
Exchange
register with
Accumulator
XCH A,direct
Exchange direct
byte with
Accumulator
XCH A,@Ri
Exchange
indirect RAM
with A
XCHDA,@Ri
Exchange loworder Digit ind
RAMwA

ByteCyc

Mnemonic

Byte Cyc

BOOLEAN VARIABLE MANIPULATION
(Continued)
ANL
C,/bit
AND
complement of
direct bit to
2
Carry
C/bit
OR direct bit to
ORL
Carry flag
2
OR complement
ORL
C,/bit
of direct bit to
Carry
2
MOV C,/bit
Move direct bit
to Carry flag
2
MOV bit,C
Move Carry flag
2
to direct bit

2
3

Description

2
2
2

2
2
2

2

2
PROGRAM AND MACHINE CONTROL
ACALL addr11
Absolute
Subroutine Cail
Long Subroutine
LCALL addr16
Call
RET
Return from
subroutine
'.
Return from
RETI
interrupt
Absolute Jump
AJMP addr11
LOl']gJump
LJMP addr16
Short Jump
SJMP rei
(relative addr)
@A + DPTR Jump indirect
JMP
relative to the
DPTR
Jump if
JZ
rei
Accumulator is
Zero
Jump if
JNZ
rei
Accumulator is
Not Zero
Jump if Carry
rei
JC
flag is set
Jump if No Carry
rei
JNC
flag
Jump if direct Bit
bit,rel
JB
set
Jump if direct Bit
bit,rel
JNB
Not set
Jump if direct Bit
bit,rel
JBC
is set & Clear bit
CJNE A,direct,rel Compare direct
toA&Jumpif
Not Equal
CJNE A,#data,rel Comp, immed,
to A & Jump if
Not Equal

2
2

"

2
2

2

2

2

2

BOOLEAN VARIABLE MANIPULATION
1
Clear Carry flag
CLR C
CLR bit
Clear direct bit
2
Set Carry Flag
1
SETB C
SETB bit
Set direct Bit
2
Complement
CPL C
Carry Flag
Complement
CPL bit
direct bit
2
ANL C,bit
AND direct bit to
Carry flag
2

2

15-7

2

2

3

2
2

1

2
3
2

2
2

2
2
2

2

2

2

2

2·

2

2

2

3

2

3

2

3

2

3

2

3

2

8044AH/8344AH/8744H

Table 2. MCS®·51 Instruction Set Description (Continued)
Mnemonic

Description
Byte
PROGRAM AND MACHINE CONTROL
(Continued)
CJNE Rn,#data,rel Comp, immed,
to reg & Jump if
Not Equal
3
CJNE @Ri,#.data, rei Comp, immed,
to indo & Jump if
Not Equal
3
DJNZ Rn,rel
Decrement
register & Jump
if Not Zero
2
DJNZ direct,rel
Decrement
direct & Jump if
Not Zero
3
NOP
No operation

eyc

Notes on data addressing modes:
(Continued)
,
# data - 8-bit constant included in instruction
#data16 - 16-bit constant included as bytes 2
& 3 of instruction
bit
-128 software flags, any I/O pin, controll or status bit

2

2

Notes on program addressing modes:
addr16 - Destination address for LCALL &
LJMP may be anywhere within the
64-K program memory address
space
Addr11 - Destination address for ACALL &
AJMP will be within the same 2-K
page of program memory as the first
byte of the following instruction
rei
- SJMP and a/l conditional jumps include an 8~bit offset byte, Range is
+ 127 -128 bytes relative to first
byte of the following instruction

2

2

Notes on da~a addressing modes:
Rn
- Working register RO-R7
direct
- 128 internal RAM locations, any I/O
port, control or status register
@Ri
-Indirect internal RAM location addressed by register RO or R1

All mnemonic copyrighted@ Intel Corporation 1979

Timer/Counters

Serial Interface Unit (SIU)

The 8044 contains two 16-bit counters which can be
used for measuring time intervals, measuring pulse
widths, counting events; generating precise periodic
interrupt requests, and clocking the serial communications. Internally the Timers are clocked at 1/12 of
the crystal frequency, which is the instruction cycle
time. Externally the counters can run up to 500 KHz.

The Serial Interface Unit is used for HDLC/SDLC
communications. It handles Zero Bit Insertion/Deletion, Flags automatic access recognization, and a
16-bit cyclic redundancy check. In addition it implements in hardware a subset of the SDLC protocol
certain applications it is advantageous to have the
CPU control the reception or transmission of every
single frame. For this reason the SIU has two modes
of operation: "AUTO" and "FLEXIBLE" (or "NONAUTO"). It is in the AUTO mode that the SIU responds toSDLG frames without CPU intervention;
whereas, in the FLEXIBLE mode the reception or
transmission of every single frame will be under CPU
control.

Interrupt System
External events and the real-time driven on-chip peripherals require service by the CPU asynchronous
to the execution of any particular section of code. To
tie the asynchronous activities of these functions to
normal program execution, a sophisticated multiplesource,two priority level, nested interrupt system is
provided. Interrupt response latency ranges from 3
,""sec to 7 ,""sec when using a 12 MHz clock.

There are three control registers and eight parameter registers that are used to operate the serial interface. These registers are shown in Figure 5 and Figure 6. The control register set the modes of operation and provide status information. The eight pa·
rameter registers buffer the station address, receive
and transmit control bytes, and point to the on-chip
transmit and receive buffers.

All five'interrupt sources can be mapped into one of
the two priority levels. Each interrupt source can be
enabled or disabled individually or the entire interrupt system can be enabled or disabled. The five
interrupt sources are: Serial Interface Unit, Timer 1,
Timer 2, and two external interrupts. The external
interrupts can be either level or edge triggered.

Data to be received or transmitted by the SIU must
be buffered anywhere within the 192 bytes of onchip RAM. Transmit and receive buffers are not allowed to "wrap around" in RAM; a "buffer end" is
generated after address 191 is reached.

15-8

inter

8044AH/8344AH/8744H

SYMBOLIC
ADDRESS

REGISTER NAMES

BYTE
ADDRESS

BIT ADDRESS

~

B REGISTER
ACCUMULATOR
"THREE BYTE FIFO

B
ACC
FIFO
FIFO
FIFO
TBS
TBL
TCB
SIUST
NSNR
PSW
DMA CNT
STAD
RFL
RBS
RBL
RCB
SMD
STS
IP
P3
IE
P2
PI
THI
THO
TLI

TRANSMIT BUFFER START
TRANSMIT BUFFER LENGTH
TRANSMIT CONTROL BYTE
, SIU STATE COUNTER
SEND CDUNT RECEIVE COUNT
PROGRAM STATUS WORD
'DMA COUNT
STATION ADDRESS
RECEIVE FIELD LENGTH
RECEIVE BUFFER'START
RECEIVE BUFFER LENGTH
RECEIVE CONTROL BYTE
SERIAL MODE
STATUS REGISTER
INTERRUPT PRIORITY CONTROL
PORT 3
INTERRUPT ENABLE CONTROL
PORT 2
PORT 1
TIMER HIGH 1
TIMER HIGH 0
TIMER LOW 1
TIMER LOW 0
TIMER MODE
TIME'R CONTROL
DATA POINTER HIGH
DATA POINTER LOW
STACK POINTER
PORTO

247

throuah
throuah

~

240
224

208

throuah
throuah
throuGh
throuah
throuah

TLO
TMDD
TCON
DPH
DPt.
SP
PO

143

135

throuah

128

240
224
223
222
221
220
219
218
217
216
208
207
206
205
204
203
202
201
200
184
176
168
160
144
141
140
139
138
137
136
131
130
129
128

(FOH)
(EOH)
(DFH)
(DEH)
(DDH)
(DCH)
(DBH)
(DAH)
(D9H)
(D8H)
(DOH)
(CFH)
(CEH)
(CDH)
(CCH)
(CBH)
(CAH)
(C9H)
(C8H)
(B8H)
(BOH)
(A8H)
(AOH)
(90H)
(8DH)
(8CH)
(8BH)
(8AH)
(89H)
(88H)
(83H)
(82H)
(81H)
(80H)

SFR's CONTAINING
D)RECT ADDRESSABLE BITS

231663-6

NOTE:
'ICE Support Hardware registers, Under normal operating conditions there is no need for the CPU to access these
registers,

Figure 5. Mapping of Special Function Registers

SERIAL MODE REGISTER (SMD) SCM2

SCMl

SCMO

NRZI

LOOP

PFS

NB

I

I

OPB

AM

I
STATUS REGISTER (STS)

TBF

RBE

RTS

SI

BOV

I I

I

NFCS

'---

NO FRAME CHECK SEQUENCE
NON· BUFFERED
PRE· FRAME EYNC
LOOP
NON RETURN TO ZERO INVERTED
SELECT CLOCK MODE

RBP
~

RECEIVE BUFFER PROTECT
AUTO MODEIAODRESSED MODE
OPTIONAL POLL BIT
RECEIVE INFORMATION BUFFER OVERRUN
SERIAL INTERFACE UNIT INTERRUPT
REQUEST TO SEND
RECEIVE BUFFER EMPTY
TRANSMIT BUFFER FULL

SEND COUNT RECEIVE
COUNT REGISTER (NSNR) r-:=,.-r-:-::~...-:=,.-r""",,,,.-...-:=,.-r--..:~-r-,=...,.-,;;;:;;-,
SEQUENCE ERROR RECEIVED

L-_...L_---"L.._ _ _ RECEIVE SEQUENCE COUNTER
L-_______________________

SEQUENCEERRORSEND

L-_...L_---"_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SEND SEQUENCE COUNTER

231663-7

Figure 6. Serial Interface Unit Control Registers

15·9

inter

8044AH/8344AH/8744H

With the addition of only a few bytes of code, the
8044's frame size is not limited to the size of its
internal RAM (192 bytes), but rather by the size of
external buffer with no degradation of the RUPI's
features (e.g. NRZI, zero bit insertion/deletion, address recognition, cyclic redundancy check). There
is a special function register called SIUST whose
contents dictates the operation of the SIU. At low
data rates, one section of the SIU (the Byte Processor) performs no function during known intervals.
For a given data rate, these intervals (stand-by
mode) are fixed. The above characteristics make it
possible to program the CPU to move data to/from
external RAM and to force the SIU to perform some
desired hardware tasks while transmission or reception is taking place. With these modifications, external RAM can be utilized as a transmit and received
buffer instead of the internal RAM.

When the Receive Buffer Empty bit (RBE) indicates
that the Receive Buffer is empty, the .receiver is enabled, and when the RBE bit indicates that the Receive Buffer is full, the receiver is disabled. Assuming that the Receiver Buffer is empty, the SIU will
respond to a poll with an I frame if the Transmit Buff~
er is full. If the Transmit Buffer is empty, the SIU will
respond to a poll with a RR command if the Receive
Buffer Protect bit (RBP) is cleared, or an RNR command if RBP is set.

AUTO Mode

In the FLEXIBLE mode all communications are under control of the CPU. It is the CPU's task to encode and decode control fields, manage acknowledgements, and adhere to the requirements of the
HOLC/SOLC protocols. The 8044 can be used as a
primary or a secondary station in this m9de.

In the AUTO mode the SIU implements in hardware
a subset of the SOLC protocol such that it responds
to many SOLC frames without CPU intervention. All
AUTO mode responses to the primary station will
comform to IBM's SOLC definition. The advantages
of the AUTO mode are that less software is required
to implement a secondary station, and the hardware
generated response to polls is much faster than doing it in software. However, the Auto mode can not
be used at a primary station.
To transmit in the AUTO mode the CPU must load
the Transmit Information Buffer, Transmit Buffer
Start register, Transmit Buffer Length register, and
set the Transmit Buffer Full bit. The SIU automatically responds to a poll by transmitting an information
frame with the P/F bit in the control field set. When
the SIU receives a positive acknowledgement from
the primary station, it automatically increments the
Ns field in the NSNR register and interrupts the
CPU. A negative acknowledgement would cause the
SIU to retransmit the frame.
To receive in the AUTO mode, the CPU loads the
Receive Buffer Start register, the Receive Buffer
Length register, clears the Receive Buffer Protect
bit, and sets the Receive Buffer Empty bit. If the SIU
is polled in this state, and the TBF bit indicates that
the Transmit Buffer is empty, an automatic RR response will be generated. When a valid information
frame is received the SIU will automatically increment Nr in the NSNR register and interrupt the CPU.
While in the AUTO mode the SIU can recognize and
respond to the following commands without CPU intervention: I (Information), RR (Receive Ready),
RNR (Receive Not Ready), REJ (Reject), .and UP
(Unnumbered Poll). The SIU can generate the fol-

lowing responses without CPU intervention: I (Information), RR (Receive Ready), and RNR (Receive
Not Ready).

FLEXIBLE (or NON-AUTO) Mode

To receive a frame in the FLEXIBLE mode, the CPU
must load the Receive Buffer Start register, the Receive Buffer Length register, clear the Receive Buffer Protect bit, and set the Receive Buffer Empty bit.
If a valid opening flag is received and the address
field matches the byte in the Station Address register or the address field contains a broadcast address, the 8044 loads the control field in the receive
control byte register, and loads the I field in the receive buffer. If there is no CRC error, the SIU interrupts the CPU, indicating a frame has just been received. If there is a CRC error, no interrupt occurs.
The Receive Field Length register provides the number of bytes that were received in the information
field.
To transmit a frame, the CPU must load the transmit
information buffer, the Transmit Buffer Start register,
the Transmit Buffer Length register, the Transmit
Control Byte, and set the TBF and the RTS bit. The
81U, unsolicited by an HOLC/SOLC frame, will transmit the entire information frame, and interrupt the
CPU, indicating the completion of transmission. For
supervisory frames or· unnumbered frames, the
transmit buffer length would be O.

CRC
The FCS register is initially set to all 1's prior to calculating the FCS field. The SIU will not interrupt the
CPU if a CRC error occurs (in both AUTO and FLEXIBLE modes). The CRC error is cleared upon receiving of an opening flag.

15-10

8044AH/8344AH/8744H

Frame Format Options
In addition to the standard SDLC frame format, the
8044 will support the frames displayed in Figure 7.
The standard SDLC frame is shown at the top of this
figure. For the remaining frames the information field
will incorporate the control or address bytes and the
frame check sequences; therefore these fields will

be stored in the Transmit and Receive buffers. For
example, in the non-buffered mode the third byte is
treated as the beginning of the information field. In
the non-addressed mode, the information field begins after the opening flag. The mode bits to set the
frame format options are found in the Serial Mode
register and the Status register.

NFCS

NB

AM1

Standard SOLC
NON-AUTO Mode

0

0

0

IF IA IC I

I

I FCS I F I

Standard SOLC
AUTO Mode

0

0

1

IF IA IC I

I

I FCS I F I

Non-Buffered Mode
NON-AUTO Mode

0

1

1

IF IA I

Non-Addressed Mode
NON-AUTO Mode

0

1

0

I FI

No FCS Field
NON-AUTO Mode

1

0

0

IF IA IC I

I

No FCS Field
AUTO Mode

1

0

1

IF IA IC I

I

No FCSField
Non-Buffered Mode
NON-AUTO Mode

1

1

1

IF IA I

No FCS Field
Non-Addressed Mode
NON-AUTO Mode

1

1

0

IF I

FRAME OPTION

Mode
AM
NB
NFCS

Key
F =
A =
C =

FRAME FORMAT

I FCS I

I

I

I

I

F

I

I

F

I

I

F

I

I FCS I

I

I

F

I

F

F

I

I

I

Bits:
- "AUTO" Mode/Addressed Mode
- Non-Buffered Mode
- No FCS Field Mode

to Abbreviations:
Flag (01111110)
Address Field
Control Field

I = Information Field
FCS= Frame Check Sequence

Note 1:
The AM bit function is controlled by the NB bit. When NB = 0, AM becomes AUTO mode select, when NB = 1, AM
becomes Address mode select.

Figure 7. Frame Format Options

15-11

inter

8044AH/8344AH/8744H

transmit and receive data in this mode at rates up to
2.4 Mbps.

Extended Addressing
To realize an extended control field or an extended
address field using the HDLC protocol, the FLEXIBLEmode must be used; For an extended control
field, the SIUis programmed to be in the non-buffered mode. The extended control field will be the
first and second bytes in the Receive and Transmit
Buffers. For extended addressing the SIU is placed
in the non-addressed mode. In this mode the CPU
must implement the address recognition for received
frames. The addressing field will be the initial bytes
in the Transmit and' Receive buffers followed by the
control field.
The SIU can transmit and receive only frames which
are multiples of 8 bits. For frames received with other than 8-bit multiples, a CRC error will cause the
SIU to reject the frame.

SOLC Loop Networks,
The SIU can be used in an SDLC loop as a secondary or primary station. When the SIU is placed in the
Loop mode it receives the data on pin 10 and transmits the data one bit time delayed on pin 11. It can
also recognize the Go ahead signal and change it
into a flag when it is ready ~o transmit. As a secondary station the SIU can be used in the AUTO or
FLEXIBLE modes. As a primary station the FLEXIBLE mode is used; however, additional hardware is
required for generating the Go Ahead bit pattern. In
the Loop mode the maximum data rate is 1, Mbps
clocked or 375 Kpbs self-clocked.

This self clocked mode allows data transfer without
a common system data clock.' An on-chip Digital
Phase Locked Loop is employed to recover the data
clock which is encoded in the data stream. The
DPLL will converge to the nominal bit center within
eight bit transitions, worst case. The DPLL requires a
reference clock of either 16 times (16x) or 32 times
(32x) the data rate. This reference clock may be externally applied or internally generated. When internally generated either the 8044's internal logic clock
(crystal frequency divided by two) or the timer 1
overflow is used as the reference clock. Using the
internal timer 1 clock the data rates can vary from
244 to 62.5 Kbps. Using the'internal logic clock at a
16x sampling rate, receive, data can either be 187.5
Kl;lps, or 375 Kbps. When the reference clock for the
DPLL is externally applied the data rates can vary
from 0 to 375 Kbps at a 16x sampling rate.
To aid in a Phase Locked Loop capture, the SIU has
a NRZI (Non Return to Zero Inverted) data encoding
and decoding option. Additionally the SIU has a preframe sync option that transmits two bytes of alternating 1's and O's to ensure that the receive station
DPLL will be synchronized with the data by the time
,it receives the opening flag.

Control and Status Registers
There are three SIU Control and Status Registers:
Serial Mode Register (SMD)
Status/Command Register (STS)

SOLC Multidrop Networks

Send/Receive Count Register (NSNR)

The SIU can be used in a SDLC non-loop configuration as a secondary or primary station. When the SIU
is placed in the non-loop mode, data is received and
transmitted on pin 11, and pin 10 drives a tri-state
buffer. In non-loop mode, modem interface pins,
RTS and CTS, become available.

The SMD, STS, and NSNR, registers are all cleared
by system reset. This assures that the SIU will power
up in an idle state (neither receiving nor transmitting).

Data Clocking Options
The 8044's serial port can operate in an externally
clocked or self clocked system. A clocked system
provides to the 8044 a clock synchronization to the
data. A self-clocked system uses the 8044's on-chip
Digital Phase Locked Loop (DPLL) to recover the
clock from the data, and clock this data into the Serial Receive Shift Register.
In this mode, a clock synchronized with the data is
externally fed into the 8044. This clock may be generated from an External Phase Locked Loop, or possibly supplied along with the data. The 8044 can

These registers and their bit assignments are described below.
SMD: Serial Mode Register (byte-addressable)
Bit 7:
6
5
4
3
2
1
0

ISCM21sCM11sCMOINRZIILOOpi PFsl NBI NFcsl
The Serial Mode Register (Address C9H) selects the
operational modes of the SIU. The 8044 CPU can
both read and write SMD. The SIU can read SMD
but cannot write to it. To prevent conflict between
CPU and SIU access to SMD, the CPU should write
SMD only when the Request To Send (RTS) and

15-12

8044AH/8344AH/8744H

Receive Buffer Empty (RBE) bits (in the STS register) are both false (0). Normally, SMD is accessed
only during initialization.
The individual bits of the Serial Mode Register are as
follows:
Bit#

Name Description

SMD.O NFCS No FCS field in the SDLC frame.
SMD.1

NB

SMD.2 PFS

CPU, and enables the SIU to post status information
for the CPU's access. The SIU can read STS, and
can alter certain bits, as indicated below. The CPU
can both read and write STS asynchronously. However, 2-cycle instructions that access STS during
both cycles ('JBC/B, REL' and 'MOV/B, C.') should
not be used, since the SIU may write to STS between the two CPU accesses.
The individual bits of the Status/Command Register
are as follows:

Non-Buffered mode. No control
field in the SDLC frame.
Pre-Frame Sync mode. In this
mode, the 8044 transmits two
bytes before the first flag of a
frame, for DPLL synchronization.
If NRZI is enabled, OOH is sent;
otherwise, 55H is sent. In either
case, 16 preframe transitions are
guaranteed.

Bit#

Name

Description

STS.O

RBP

Receive Buffer Protect. Inhibits
writing of data into the receive
buffer. In AUTO mode, RBP
forces an RNR response instead
of an RR.

STS.1

AM

AUTO Mode/Addressed Mode.
Selects AUTO mode where
AUTO mode is allowed. If NB is
true, (= 1), the AM bit selects the
addressed mode. AM may be
cleared by the SIU.

STS.2

OPB

Optional Poll Bit. Determines
whether the SIU will generate an
AUTO response to an optional
poll (UP with P = 0). OPM may
be set or cleared by the SII).

STS.3

BOV

Receive Buffer Overrun. BOV
may be set or cleared by the SIU.

SMD.3 LOOP Loop configuration.
SMD.4 NRZI

NRZI coding option. If bit = 1,
NRZI coding is used. If bit = 0,
then it is straight binary (NRZ).

SMD.5 SCMO Select Clock Mode-Bit 0
SMD.6 SCM1

Select Clock Mode-Bit 1

SMD.7 SCM2 Select Clock Mode-Bit 2
The SCM bits decode as follows:
SCM

Data Rate

2 1 0 Clock Mode

(Bits/sec)·

0 0 0 Externally clocked

0-204M··

STSo4 SI

SIU Interrupt. This is one of the
five interrupt sources to the CPU.
The vector location = 23H. SI
may be set by the SIU. It should
be cleared by the CPU before
returning from an interrupt
routine.

STS.5

RTS

Request To Send. Indicates that
the 8044 is ready to transmit or is
transmitting. RTS may be read or
written by the GPU. RTS may be
read by the SIU, and in AUTO
mode may be written by the SIU.

STS.6

RBE

Receive Buffer Empty. RBE can
be thought of as Receive Enable.
RBE is set tq one by the CPU
when it is ready to receive a
frame, or has just read the buffer,
and to zero by the SIU when a
frame has been received.

S:rS.7

TBF

Transmit Buffer Full. Written by
the ~U to indicate that it has
fille the transmit buffer. TBF may
be cleared by the SIU.

0 0 1 Reserved
0 1 0 Self clocked, timer overflow 244-62.5K
0 1 1 Reserved
1 0 0 Self clocked, external16x
1 0 1 Self clocked, external 32x

0-375K

1 1 0 Self clocked, internal fixed

375K

1 1 1 Self clocked, internal fixed

187.5K

0-187.5K

NOTES:
• Based on a 12 Mhz crystal frequency
"0-1 M bps in loop configuration

STS: Status/Command Register (bitaddressable)
Bit:
7
6
5
4
3
2

1

0

ITBF IRBE IRTS ISI IBOV IOPB IAM IRBP I

The Status/Command Register (Address C8H) provides operational control of the SIU ~y the 8044

15-13

inter

8044AH/8344AH/8744H

TBS: Transmit Buffer Start Address Register
(byte-addressable)

NSNR: Send/Receive Count Register (bltaddressable)
Bit:?
6
543210

INs2INs1INsolsEslNR2INR1IN~0IsERI

The Send/Receive Count Register (Address D8H)
contains the transmit and receive sequence numbers, plus tally error indications. The SIU can both
read and write NSNR. The 8044 CPU can both read
and write NSNR asynchronously. However, 2-cycle
instructions that access NSNR during both cycles
(,JBC /B, REl,' and 'MOV /B,C') should not be
used, since the SIU may write to NSMR between the
two 8044 CPU accesses.

TBl: Transmit Buffer Length Register
(byte = addressable)
The Transmit Buffer length register (Address DB H)
contains the length (in bytes) of the I-field to be
transmitted. A blank I-field (TBl = 0) is valid. The
CPU should access TBl only when the SIU is not
transmitting a frame (when TBF = 0).

The individual bits of the Send/Receive Count Register are as follows:
Blt#

NOTE:
The transmit and receive buffers are not allowed to
"wrap around" in the on-chip RAM. A "buffer end"
is automatically generated if address 191 (BFH) is
reached.

Name Description

NSNR.O SER

Receive Sequence Error:
NS (P) =1= NR (S)

NSNR.1 NRO

Receive Sequence Counter-Bit 0

NSNR.2 NR1

Receive Sequence Counter-Bit 1

NSNR.3 NR2

Receive Sequence Counter-Bit 2

NSNR.4 SES

Send Sequence Error:
NR (P) =1= NS (S) and
NR (P) =1= NS (S) + 1

NSNR.5 NSO

Send Sequence Counter-Bit 0

NSNR.6 NS1

Send Sequence Counter-Bit 1

NSNR.? NS2

Send Sequence Counter-Bit 2

The Transmit Buffer Start address register (Address
DCH) points to the location in on-chip RAM for the
beginning of the I-field of the frame to be transmitted. The CPU should access TBS only when the SIU
is not transmitting a frame (when TBF = 0).

TCB: Transmit Control Byte Register
(byte-addressable)
The Transmit Control Byte register (Address DAH)
contains the byte which is to be placed in the control
field of the transmitted frame, during NON-AUTO
mode transmission. The CPU should access TCB
only when the SIU is not transmitting a frame (when
TBF = 0). The Nsand NR counters are not used in
the NON-AUTO mode.
RBS: Receive Buffer Start Address Register
(byte-addressable)

Parameter Registers

The Receive Buffer Start address register (Address
CCH) points to the location in on-chip RAM where
the beginning of the I-field of the frame being received is to be stored. The CPU should write RBS
only when the SIU is not receiving a frame (when
RBE = 0).

There are eight parameter registers that are used in
connection with SIU operation. All eight registers
may be read or written by the 8044 CPU. RFl and
RCB are normally loaded by. the SIU.
The eight parameter registers are as follows:

RBL: Receive Buffer length Register
(byte-addressable)

STAD: Station Address Register
(byte-addressable)
The Station Address register (Address CEH) contains the station address. To prevent acess conflict,
the CPU should access STAD only when the SIU is
idle (RTS = 0 and RBE = 0). Normally, STAD is
accessed only during initialization.

The Receive Buffer length register (Address CBH)
contains the length (in .bytes) of the area in on-chip
RAM allocated for the received I-field. RBl=O is
valid. The CPU should write RBl only when RBE = O.

15-14

intJ

8044AH/8344AH/8744H

RFL: Receive Field Length Register
(byte-addressable)
The Receive Field Length register (Address CD H)
contains the length (in bytes) of the received I-field
that has just been loaded into on-chip RAM. RFL is
loaded by the SIU. RFL = 0 is valid. RFL should be
accessed by the CPU only when RBE = O.
RCB: Receive Control Byte Register
(byte-addressable)
The Received Control Byte register (Address CAH)
contains the control field of the frame that has just
been received. RCB is loaded by the SIU. The CPU
can only read RCB, and should only access RCB
when RBE = O.

The emulator operates with Intel's Inteliec™ development system. The development system interfaces
with the user's 8044 system through an in-cable
buffer box. The cable terminates in a 8044 pin-compatible plug, which fits into the 8044 socket in the
user's system. With the emulator plug in place, the
user can excercise his system in real time while collecting up to 255 instruction cycles of real-time data.
In addition, he can single-step the program.
Static RAM is available (in the in-cable buffer box) to
emulate the 8044 internal and external program
memory and external data memory. The designer
can display and alter the contents of the replacement memory in the buffer box, the internal data
memory, and the internal 8044 registers, including
the SFR's.
SIUST: SIU State Counter (byte-addressable)

ICE Support
The 8044 In-Circuit Emulator (ICE-44) allows the
user to exercise the 8044 application system and
monitor the execution of instructions in real time.

The SIU State Counter (Address D9H) reflects the
state of the internal logic which is under SIU control.
Therefore, care must be taken not to write into this
register. This register provides a useful means for
debugging 8044 receiver problem.

15-15

inter

8044AH/8344AH/8744H

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ...... O°C to 70°C
Storage Temperature ........... -65°C to -150°C
Voltage on EA, VPP Pin to VSS ... -0.5V to -21.5V
Voltage on Any Other Pin to VSS .... - 0.5V to -7V
Power Dissipation ........................... 2W

D.C. CHARACTERISTICS
Symbol

*Notice: Stresses above those listed under 'i'\bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

TA = O°Cto 70°C, VCC = 5V = 10%, VSS = OV

Parameter

Min

Max

Unit

-0.5

0.8

V

VIL

Input Low Voltage (Except EA Pin of 8744H)

VIL1

Input Low Voltage to EA Pin of 8744H

VIH

Input High Voltage (Except XTAL2, RST)

2.0

VCC

2.5

VCC

VIH1

Input High Voltage to XTAL2, RST

VOL

Output Low Voltage (Ports 1, 2, 3)*

VOL1

Output Low Voltage (Port O,ALE,PSEN)*

0

0.8

+ 0.5
+ 0.5

Test Conditions

V
V
V

XTAL1 = VSS

0.45

V

IOL = 1.6mA

8744H

0.60
0.45

V
V

IOL = 3.2 rnA
IOL = 2.4 rnA

8044AH/8344AH

0.45

V

IOL = 3.2 rnA

VOH

Output High Voltage (Ports 1, 2, 3)

2.4

V

IOH = -80/LA

VOH1

Output High Voltage (Port 0 in External
Bus Mode, ALE, PSEN)

2.4

V

IOH =-400 /LA

ilL

Logical 0 Input Current (Ports 1,2, 3)

IlL 1

-500

/LA

Logical 0 Input Current to EA Pin
of 8744H only

-15

rnA

IIL2

Logical 0 Input Current (XTAL2)

-3.6

rnA

Yin = 0.45V

III

Input Leakage Current (Port 0)
8744H
8044AH/8344AH

±100
±10

/LA
/LA

0.45
0.45

IIH

Logical 1 Input Current to EA Pin of 8744H

500

p.A

IIH1

Input Current to RST to Activate Reset

500

p.A

ICC

Power Supply Current:
8744H
8044AH/8344AH

285
170

rnA
rnA

Pin Capacitance

10

pF

CIO

Yin = 0.45V

Yin

< Yin < VCC
< Yin < VCC

<

(VCC - 1.5V)

All Outputs Disconnected: EA = VCC
Test Freq. = 1MHz(1)

'NOTES:
1. Sampled not 100% tested. T A = 25'C.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3. The noise is due to ex1ernal bus capacitance discharging into the Port 0 and Port 2 pin when these pins make 1-too transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may
exceed O.SV. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.

15-16

inter

8044AH/8344AH/8744H

A.C. CHARACTERISTICS
T A = O°C to + 70°C, VCC = 5V ± 10%, VSS = OV, Load Capacitance for Port 0, ALE, and PSEN
Load Capacitance for All Other Outputs = 80 pF

= 100 pF,

EXTERNAL PROGRAM MEMORY CHARACTERISTICS
Symbol

Parameter

12 MHzOsc
Min

Max

Variable Clock
1/TCLCL = 3.5 MHz to 12 MHz
Min

Unit

Max

TLHLL

ALE Pulse Width

127

2TCLCL·40

ns

TAVLL

Address Valid to ALE Low

43

TCLCL·40

ns

TLLAX1

Address Hold After ALE Low

48

TCLCL·35

ns

TLLlV

ALE Low to Valid Instr in
8744H
8044AH/8344AH

TLLPL

ALE Low to PSEN Low

TPLPH

PSEN Pulse Width
8744H
8044AH/8344AH

TPLIV

58

TCLCL·25

ns

190
215

3TCLCL·60
3TCLCL·35

ns
ns

PSEN Low to Valid Instr in
8744H
8044AH/8344AH

TPXIX

Input Instr Hold After PSEN

TPXIZ2

Input Instr Float After PSEN

TPXAV2

PSEN to Address Valid

TAVIV

Address to Valid Instr in
8744H
8044AH/8344AH

TAZPL

ns

Address Float to PSEN

4TCLCL·150
4TCLCL·100

183
233

100
125
0

3TCLCL·150
3TCLCL·125

ns

0
63

75

TCLCL·20
TCLCL·8

267
302
-25

ns
ns

5TCLCL·150
5TCLCL·115
-25

ns
ns

ns
ns
ns

NOTES:
1. TLLAX for access to program memory is different from TLLAX for data memory.
2. Interfacing RUPI·44 devices with float times up to 75ns is permissible. This limited bus contention will not cause any
damage to Port 0 drivers.

15·17

8044AH/8344AH/8744H
EXTERNAL DATA MEMORY CHARACTERISTICS
Symbol

Variable Clock
1/TCLCL = 3.5 MHz to 12 MHz

12 MHzOsc

Parameter

Min

Max

Min

Unit

Max

RD Pulse Width

400

6TCLCL-100

ns

TWLWH. WR Pulse Width

400

6TCLCL-100

ns

48

TCLCL-35

ns

TRLRH

TLLAX

Address Hold after ALE

TRLDV

RD Low to Valid Data in

TRHDX

Data Hold After RD

5TCLCL-165

252
0

ns

0

ns

TRHDZ

Data Float After RD

97

2TCLCL-70

ns

TLLDV

ALE Low to Valid Data In

517

8TCLCL-150

ns

9TCLCL"165

ns

3TLCLCL+50

ns

TAVDV

Address to Valid Data In

TLLWL

ALE Low to RD or WR Low

200

TAVWL

Address to RD or WR Low

203

4TCLCL-130

ns

TQVWX

Data Valid to WR Transi~ion
8744H
8044AH/8344AH

13
23

TCLCL-70
TCLCL-60

ns
ns

TOVWH

Data Setup Before WR High

433

7TCLCL-150

ns

TWHOX

Data Held After WR

33

TCLCL-50

ns

TRLAZ

RD Low to Address Float

TWHLH

RD or WR High to ALE High
8744H
8044AH/8344AH

585
3TCLCL-50

300

25
33
43

TCLCL-50
TCLCL-40

133
123

25

ns

TCLCL+50
TCLCL+50

ns
ns

NOTE:
1. TLLAX for access to program memory is different from TLLAX for access data memory.

Serial Interface Characteristics
Symbol

Parameter

Min

Max

Unit

TDCY

Data Clock

420

ns

TDCL

Data Clock Low

180

ns

TDCH

Data Clock High

100

ns

tTD

Transmit Data Delay

tOSS

Data Setup Time

40

ns

tOHS

Data Hold Time

40

ns

140

15-18

ns

inter

8044AH/8344AH/8744H

WAVEFORMS
Memory Access
PROGRAM MEMORY READ CYCLE
~-------------------------------TCV--------------------------~

ALE

.}~---+---.-f--:-.j TPXAV

PSEN

INSTRIN

A7-AD

PORTO
ADDRESS
OR SFR-P2

PORT2

ADDRESS A1S-AS

ADDRESS A 1S-AS

231663-8

DATA MEMORY READ CYCLE

~------""""

1+------ TllDV------------~

TWHlH

ALE

PSEN

TllWl

RD

----------------~r_------------, ~~-----_+TRlRH------------~.__- - - - - TllAX

TRHDX
DATA IN

A7-AO

PORTO

TRlAZ
PORT2

ADDRESS
OR SFR-P2

ADDRESS A1S-AS OR SFR-P2

231663-9

DATA MEMORY WRITE CYCLE
TWHLH
ALE

----------------4-----------~ 14-----------TWLWH------~--~~_____
TOVWH

PORT2

TWHQX

DATA OUT

PORTO

ADDRESS A1S-A8 OR SFR-P2

231663-10

15-19

inter-

8044AH/8344AH/8744H

SERIAL 1/0 WAVEFORMS
SYNCHRONOUS DATA TRANSMISSION

1-------,-----.;..- TDCy-------,----!
- - - - " " " ' " " I-----TDCL--~ r-----~
SCLK
I+--~TDCH--~

' - - _ _ _ _ _.J

"------

DATA

TTD
231663-11

SYNCHRONOUS DATA RECEPTION
1--------'TDCy-------!
- - - - - - - - , . I------,--TDCL - - - + l
SCLK

r------"""

i+---TDCH - - + I

DATA

TDSS

I-----'---TDHS-------+I
231663-12

15-20

intJ

8044AH/8344AH/8744H

=x

AC TESTING INPUT, OUTPUT, FLOAT WAVEFORMS

r------------------------------,
FLOAT

INPUT/OUTPUT
2.4

0.45

20

2.0)<=.
TEST POINTS
-"0.:::.8_ _ _ _ _......::0::::..;.8

2.4

~

231663-13
AC testing inputs are driven at 2.4V for a Logic "1" and 0.45V for
a Logic "0" Timing measurements are made at 2.0V for a Logic
"1" and 0.8V for a Logic "0".

j

>-----FLOAT------- RBL). This
state is executed until the closing flag is received.
At the end of reception, if the FCS option is used, the
closing flag and the FCSbytes will remain in the 3-byte
FIFO. The contents of the RCB register are used to
update the NSNR (Receive/Send Count) register. The
SIU updates the STS register and sets the serial interrupt.

3.2 Transmit State Sequence
Setting the RTS bit puts the SIU in the transmit mode ..
When the CTS pin goes active, the byte processor goes
into START-XMIT state. In this state the opening flag
is moved into the RAM Buffer (RB) register. The byte
processor jumps to the next state and goes into the
standby mode.
If the Pre-Frame Sync (PFS) option is selected, the
PFSI and PFS2 states will be executed to transmit the
two Pre-Frame Sync bytes (OOH or 55H). In these two
states the contents of the Pre-Frame Sync generator are
sent to the serial port while the Zero Insertion Circuit
(ZID) is turned off. ZID is turned back on automaticallyon the next byte boundary.
If the PFS option is not chosen, the byte processor
jumps to the FLAG state. In this state, the byte processor moves the contents of TBS into the SRAR register,
decrements TBL and moves the contents into the
DCNT register. The byte 'processor turns off the ZID
and turns on FCS GEN/CHK. The contents of FCS
GEN/CHK are not transmitted unless the NFCS bit is

15-31

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

SIUST

STATE

STATE PROCEDURE

01H

(

FLAG

J

01-1)
01-2)
01-3)
0104)

OBH'

(

ADDRESS

)

OB-l) SR-TMP
OB-2) (STAD)-RB
OB-3) IF RB.NE.TMP AND
FFH.NE.TMP THEI\I IDLE
08-4) IF NB=1 GOTO 10-2

10H

(

CONTROL

)

10-1) SR-(RCB)
10-2) IF NFCS=1 GOTO 20-3

lBH

(

PUSH-l

)

18-1) SR-(FIFOO)
18-2) PUSH

20H

(

PUSH-2

)

20-1)
20-2)
20-2)
20-4)

2BH

(

DMA-LODP

)

28-1) IF END OF I-FIELD.
THEN IDLE
28-2) (FIF02)-@SRAR
28-3) SR- (FIFOO)
28-4) INC. SRAR
28-5) PUSH
2B-6) DEC; (DCNT)
2B-7) INC. (RfL)
2B-8) IF NOT DMA BUFFER END.
GOTO 2B-l
28-9) RCB)- RB

30H

(

BOY-LOOP

)

~,

~

(RBS)-SRAR
(RBL)-I-(DCNT)
TURN ON FCS GEN/CHK
IF POINT TO POINT MODE.
GOTO 10-2

SR-(FIFOO)
PUSH
(RFL)-OOH
IF DMA BUFFER END.
GOTO 28-7
20-5) (RCB)-RB

30-1) SET BOY BIT (SRS.3)
30-2) (RCB)- RB
30-3) IF NOT END OF I-FIELD.
GOTO 30-1
30-4) IDLE

292019-4

Figure 4. Receive State Diagram
set. If a frame with the address field is chosen. it moves
the contents of the STAD register into the RB register
for transmission. At the same time. the opening flag is
being transmitted by the bit processor.
In the ADDRESS (SIUST = AOH) and CONTROL
(SIUST = ASH) states, TCB and the first information
byte are loaded into the RB register for transmission,
respectively. Note that in the CONTROL state, none of
the registers (e.g. DCNT, SRAR) are incremented, and
ZID and FCS GEN/CHK are not turned on or off.
The procedures in the DMA·LOOP state are similar to
the procedures of the DMA·LOOP in the receive state
diagram. The SRAR register pointer to the internal
RAM is incremented, and the DCNT register is decremented. The contents of DCNT reach'zero when all the
information bytes froni the transmit buffer are transmitted. A byte from RAM is moved to the RB register
for transmission. This state is executed on the following

byte' boundaries until all the information bytes are
transmitted. '
The FCSI and the FCS2 states are executed to transmit
the Frame Check Sequence bytes generated by the FCS
generator, and the END-FLAG state is executed to
transmit the closing flag.
The XMIT-ACTION and the ABORT-ACTION
states are executed by the byte processor to synchronize
the SIU with the CPU clock. The XMIT"ACTION or
the ABORT-ACTION state is repeated until the byte
processor status is updated. At the end, the STS and the
TMOD registers are updated.
The two ABORT-SEQUENCE states (SIUST = EOH
and SIUST = ESH) are executed only if transmission
is aborted by the CPU (RTS or TBF bit of the STS
register is cleared) or by the serial data link (CTS signal
goes inactive or shut-off occurs in loop mode.)

15-32

FLEXIBILITY IN FRAME SIZE WITH THE 8044

SIUST

STATE

STATE PROCEDURE

87H

88H

90H

98H

B7-1) FLAG-- RB

J
(

B8-1) IF NO PFS (SMD.2=0).
GOTO 98-1
'B8-2) XMIT A PFS BYTE
BB-3) ZID OFF

PFS2

I
FLAG

)

90-1) XMIT A PFS BYTE
90-2) ZID OFF

9B-1)
98-2)
9B-3)
98-4)
98-5)

(TBS)--SRAR
ZID OFF
(TBL)-I-- (DCNT)
TURN ON ,CS GEN/CHK
IF POINT TO POINT MODE.
GOTO A8-1
98-6) (STAD)-- RB

AOH

AO-l) IF NB=1 GOTO A8-1
AO-2) IF AUTO MODE
CTRL--RB
AO-3) IF FLEXIBLE MODE
(TCB)--RB

A8H

A8-1) IF DMA BUFFER END.
GOTO BO-3
A8-2) @SRAR--RB

BOH

BO-1) INC. SRAR
BO-2) DEC. DCNT
BO-3) IF DMA BUFFER END
AND NFCS=I.
GOTO,CO-l
BO-4) @SRAR--RB
BO-5) GOTO BO-l

BBH

BB-l) NO ACTION

COH

CBH

CB-1) ZID OFF

DOH

00-1) REPEAT THIS STATE TILL SIU
IS IN SYNC. WITH CPU. THEN
IDLE. ZID OFF

EOH

EO-1) NO ACTION

EBH

EB-l) ZID OFF

FOH

,0-1 ) REPEAT ni IS STATE TILL SIU
IS IN SYNC. WITH CPU. THEN
IDLE. ZID OFF

Figure 5. Transmit State Diagram

15-33

292019-6

intJ

FLEXIBILITY IN FRAME SIZE WITH THE 8044

4.2 SIU Registers

4.0 TRANSMISSION/RECEPTION OF
LONG FRAMES (EXPANDED·
OPERATION)
.
In this application note, a frame whose information
field is more than 192 bytes (size of on~chip RAM) is
referred to as a long frame. The 8044 can access up to
64000 bytes of external RAM. Therefore, a long frame
can have up to 64000 information bytes.

4.1 Description
During transmission or reception of a frame, while the
bit processor is processing a byte, the byte processor,
after 16 CPU states, is in the standby mode, and the
internal registers and the internal bus are not used .. The
period between each byte boundary, when the byte
processor is in the standby mode, can be used to move
data from external RAM to one of the byte processor
. registers for transmission and vice versa for receptioll.
The contents of the SIUST register, which dictate the
state of the byte processor, can be monitored to recognize the beginning of each SDLC field and the consecutive byte boundaries.

To write into the SIUST register, the data must be complemented. For example, if you intend to write 18H
into the SIUST register, you should write E7H to the
register. The data read from SIUST is, however, true
data (i.e. 18H).
Read and write accesses to the SIUST, STAD, DCNT,
RCB, RBL;· RFL, TCB, TBL, TBS, and the 3-byte
FIFO registers are done on even and odd phases, respectively. Therefore, there is no bus contention when
the CPU is monitoring the registers (e.g. SIUST), and
SIU is simultaneously writing into them.
There is no need to change or reset the contents of any
SIU register while transmitting or receiving long
frames, unless the. byte processor is forced to repeat a
state in which the contents of theSe registers are modified. Note that the SRAR register can not be accessed
by the CPU; therefore, avoid repeating the DMALOOP states. If SRAR increments to 192, the SIU will
be interrupted and communication will be aborted.

4.3 Other Possibilities
By writing into the SIUST register, the byte processor
can be forced to repeat or skip a specific state. As an
example, the SIU can be forced to repeatedly put the
received bytes into the RCB register. This is. accom-·
plished by writing E7H into the SIUST register when
the byte processor goes into the standby mode. The
byte processor, therefore, executes the CONTROL
state at the next byte boundary.
For transmission, the byte processor is put in the transmit mode. When transmission of a frame is initiated,
the user program calls a subroutine in which the state
of the byte processor is monitored by checking the contents of the SIUST register. When the byte processor
reaches a desired state and goes into standby, the CPU
loads the first byte of the internal RAM buffer with
data and moves the byte processor to the CONTROL
state. The routine is repeated for every byte. At the end,
the program returns from the subroutine, and the SIU
finishes its task (see application examples).
For reception, a software routine is executed to move
data to external RAM and to force the SIU to repeat
the CONTROL state. The CONTROL state is repeated
because, as shown in the receive state diagram, the only
action taken by the byte processor, in the CONTROL
state, is to move the contents ofSR to the RCB register.
None of the registers (e.g. SRAR and DCNT) are incremented. A similar comment justifies the use of the
CONTROL state for transmission. In the transmit
CONTROL state, contents of a location in the on-chip
RAM addressed by TBS is moved to RB for transmission.

The internal RAM, in conjunction with an external
buffer (RAM orFIFOs), can be used as a transmit and
receive buffer. In other words, Expanded and Normal
operation can be used together. For example, if a frame
with 300 Information bytes is received and only 255 of
them are moved to an external buffer, the remaining
bytes (45 bytes) will be loaded into the internal RAM
by the SIU (assuming RBL is set to 45 or more).· The
contents of RFL indicate the number of bytes stored in
the internal RAM. For transmission, the contents of
the external buffer can be transmitted followed by the
contents of the internal buffer.
If the internal RAM is not used, contents of the RBL
register can be 0 and contents of the TBL register must
be set to 1. The contents of the TBS register can be any
location in the internal RAM.
The transmission and reception procedures for long
frames with no FCS are similar to those with FCS. The
exception is the contents of the SIUST register should
be compared with· different values since the two FCS
states of the transmit and receive flow charts are
skipped by the byte processor.
If a frame format with no control byte is chosen, a
location in the RAM addressed by TBS should be used
for transmission as with control byte format. The FIFO
can be used for reception. The STAD register can be
used for transmission if no zerq insertion is required.

15-34

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

If the RUPI is used in Auto mode (see Section 5), it
will still respond to RR, RNR, REJ, and Unnumbered
Poll (UP) SDLC commands with RR or RNR automatically, without using any transmit routine. For ex.ample, if the on-chip CPU is busy performing some real
time operations, the SIU can transmit an information
frame from the internal buffer or transmit a supervisory
frame without the help of CPU (Normal operation).
Maximum data rate using this feature is limited primarily by the number of instructions needed to be executed
during the standby mode.
Transmission or reception of a frame can be timed out
so that the CPU will not hang up in the transmit or
receive procedures if a frame is aborted. Or, if the data
rate allows enough time (standby time is long enough),
the CPU can monitor the SIUST register for idle mode
(SIUST = OIH).
It is also possible to transmit multiple opening or clos-

ing flags by forcing the byte processor to repeat the
END-FLAG state.

4.4 Maximum Data Rate in Expanded
Operation
Assuming there is no zero-insertion/deletion, the bit
processor requires eight serial clock periods to process
one block of data. The byte processor, running on the
CPU clock, processes one byte of data in 16 CPU states
(one state of the state diagrams). Each CPU state is two
oscillator periods. At an oscillator frequency of
12 MHz, the CPU clock is 6 MHz, and 16 CPU states
is 2.7 /J-s. At a 3 Mbit rate with no zero-insertion/deletion, there is exactly enough time to execute one state
per byte (16 states at 6 MHz = 8 bits at 3M baud). In
other words, the standby time is zero.
Figure 6 demonstrates portions of the timing relationship between the byte processor and the bit processor.
In each state, the actions taken by the processors, plus
the contents of the SIUST register, are shown. When
the byte processor is running, the contents of SIUST
are unknown. However, when it is in the standby mode,
its contents are determinable.
The maximum data rate for transmitting and receiving
long frames depends on the number of instructions
needed to be executed during standby, and is propor-

STATE:

BIP:

ADDRESS

X

CRTL BYTE -

:J<

SR

BYP: :J<
6i

F

19 Al0
2-!.o WE

~

',j, "

~" "
L

V

,

.~""

..

M

_"

A4
A5
A6
A7
A8 A9
Al0

,

m,.

~

1

'..

'.,
'..
~
~

A4
A5
2 A6
-;- A7
-::.1.2 A8

Z

_J

--, •

"11

::a
00

~

5:

In

00 '..

"

"00,,,,,
'" "

" '.. '"

en

N
In

:e:::::j
::z::
-I

. 04
05
06
07

'15
'16
'17
,

05

os

ii7
---4

~ A9
~ Al0

.2!.. All
20 OE
L----~--~==_~18~ CE
~
l

l

"

15

" ..

.. -.

'"

01 '11

OO,,~
~"
",,~

'"
4 A4

-'1

"', "'"
"'J

"00

~

r

.s - .

•..

"
A4

I ..

STB

I

"'
AM9128

Al

'" "" '" M

00

.

~

AO
"

A3
M

17
WR'
RO I 29

~,

~

828L....., 19
,.. ""'"

3

-",,,

"~"",

...---

:::I.

:J:

A01, --

~, "

()

00

---,
.;. '"
~.

A07,

!O

DI

- '."
"'''

-'"

g»
Cu

00

.!. '" " " . " "

iiJ

o:::I

00

~'''' ~ "~,,.
oo~
[= -'"''
""'; '" """
~
~
~

,.Xl
'"""i91

I" I"

R2

c"
'"
t:

~".~
I

5

-

~ '~

~,

ADO-7

All

-

J
292019-11

::z::

In
CI)

o

"'"'""

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

Main Routine
First, the chip is initialized (see Figure 10). It is put in
Flexible mode, externally clocked, and "Flag-Information Field-FCS-Flag" frame format. Pre-Frame Sync
option (PFS = I) and automatic Frame Check Sequence generation/detection (NFCS = 0) are selected.
The on-chip transmit buffer starts at location 20H and
the transmit buffer length is set to 1. This one byte
buffer contains the address of the secondary station.
There is no on-chip receive buffer since the long frame
being received is moved to the external buffer. The
RTS, TBF, and RBE bits are set simultaneously. Setting the RTS and TBF bits causes the SIU to transmit
the contents of the transmit buffer.

tasks. After reception of the long frame, the SIU interrupt routine is executed again. This time, RTS, TBF,
and RBE are set for another round of information exchange between the two stations.
SIU never interrupts while reception or transmission is
taking place. The SIU registers are updated and the SI
is set (serial interrupt) after the closing flag has been
received or transmitted. An SIU interrupt never occurs
if the receive interrupt routine or the transmit subroutine is being executed.
Setting the RBE bit of the STS register puts the RUPI
in the receive mode. However, the jump to the receive
interrupt routine occurs only when a frame appears on
the serial port. Incoming frames can be detected using
the Pre-Frame Sync. option and one of the CPU timers
in counter mode. The counter external pin (TO) is connected to the data line (pin 11 is tied to pin 14). Setting
the PFS (Pre-Frame Sync.) bit will guarantee 16 transitions before the opening' flag of a flame.

292019-12

Main Program
Figure 10. Primary Station Flow Charts
SIU Interrupt Routine
After transmission of the frame, the SIU interrupts the
on-chip CPU (SI is set). In the SIU interrupt service
routine, counter 0 is initialized and turned on (see Figure 11). The user program returns to perform other

292019-13

SIU Interrupt Routine
Figure 11. Primary Station Flow Charts

15-39

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

The counter registers are initialized such that the counter interrupt occurs,before the opening flag of a frame.
When the PFS transitions appear on the, data line, the
counter overflows and interrupts the CPU., The CPU
program jumps to the timer interrupt service routine
and executes the receive routine. In the receive routine,
the received frame, isprocessed,and the information
bytes are moved to the external RAM. Note that the
maximum count ni.te of the 8051 counter is '124 of the
oscillator frequency. At 12 MHz, the data rate is limited to 500 Kbps.
Another method to detect a frame on the data line and
cause an interrupt is to use an external "Flag-Detect"
circuit to interrupt the CPU. The "Flag Detect" circuit
can be an 8-bit shift register plus some TTL chips. If
this option is used, the RUPI must operate in externally
clocked mode because the clock is ,needed to shift the
incoming data into the shift register. With this option,
the maximum data rate is ,not limited by the maximum
count rate of the 8051 counter. ,
Receive Interrupt Routine

In Normal operation, the byte processor executes the
procedures of the FLAG state, jumps to the CONTROL state without going into the standby mode, and
executes 10-2 procedure of the state (see Figure 4). It
then jumps to the PUSH-l state and goes into the
standby mode. At the following byte boundaries, the
byte processor executes the PUSH-I, PUSH-2, and
DMA-LOOP states, respectively. The receive interrupt
routine as, shown iii the flow chart of Figure 12 and
described below forces the byte processot'to repeatedly
execute the CONTROL state before the PUSH-l state
is executed. The following is the step by step procedure
to receive long frames:
1) Turn off the CPU counter and save all the impor-,
tant registers. Jump to the receive interrupt routine,
execution of the instructions to save regIsters, and
initialization of the receive buffer pointer take place
while the Pre-Frame Sync bytes and the opening
flag are being received. This is about three data byte
periods (48 CPU cycles at 500 Kbps).

2) Monitor the SIUST register for standby in the
PUSH-I state (SIUST = 18H). When the SIUST
contents are 18H, the byte processor is waiting for
the first information byte. The bit processor has already recognized the flag and is processing the first
, information byte.
3) In the standby mode, move the byte processor into
the CONTROL state by writing "EFH" (complement of 10H) into the SIUST register. When the
next' byte boundary occurs, the bit processor has
processed and moved a byte of data into the SR
register. The byte processor moves the contents of
SR into the RCB register, jumps to the PUSH-I
state (SIUST ,;; 18H), and waits.
4) Monitor the SIUST register for standby in the
PUSH-l state. When the contents of SIUST becomes 18H, the contents of RCB are the first information byte of the information field.
5) While the byte processor is in the standby mode,
move the contents of RCB to an external RAM or
an I/O port.
6) Check for the end of the information field. The end
can be detected by knowing the number of bytes
transmitted, or by having a unique character at the
end of information field. The length of the information field can be loaded into the first byte(s) received. The receive routine can load this byte into
the loop counter.
,
7) If the byte receiv~ is not the last information byte,
move the byte processor back to standby in the
CONTROL state and repeat steps 4 through 6. Otherwise, return from the interrupt routine.
Upon returning from the receive interrupt routine, the
byte processor automatically executes the PUSH-I,
PUSH-2, and DMA-LOOP before it stops. This causes
the remaining information bytes (if any) to be stored in
the internal RAM at the starting location specified by
the contents of RBS register. At the end of the cycle,
the closing flag and the CRC bytes are left in the FIFO.
The RFL register will be incremented by the number of
bytes stored in the internal RAM. Then, the STS and
NSNR registers are updated, and an appropriate response is generated by the SIU.
The software to perform the above task is given in Table 1. In this example, the number of ittstruction cycles
executed during standby is 12 cycles.

15-40

FLEXIBILITY IN FRAME SIZE WITH THE 8044

Receive Codes

REC:
WAIT1:
NEXTI:
WAIT2:

END

•
•
•

Cycles

•

•
•

CLR
MOV
CJNE
MOV
MOV
CJNE
MOV
MOVX
INC
DJNZ

TRO

A,#18H
A, SIUST ,WAITl
SIUST, #OEFH ••••••••••••••••••••••• 2
A,#18H •••••••••••••••••••••••••••• l

A,SIUST,WAIT2 •••••••••••••••••••••• 2
A,RCB •••••••••••••••••••••••••••••• 1
@DPTR,A ••••••••••••••••••••••••••• 2
DPTR •••• .'•••••••••••••••••••••••••• 2
R5,NEXTI ••••••••••••••••••••••••••• 2

RET!.

12 Cycles
6.1.4 SECONDARY STATION SOFTWARE
The assembly code for the secondary station software is
given in Appendix A. The secondary station contains
the transmit subroutine which is called for transmission
of long frames.
Main Routine
As shown in the secondary station flow chart (Figure
13), the external transmit buffer (external RAM) is
loaded with the information data (FFH, FEH, FDH,
... ) at starting location 200H. The internal transmit
buffer (ori chip RAM) starts at location 20H (TBS =
20H), and the transmit buffer length (TBL) is set to 1.
The on-chip CPU, in the transmit subroutine, moves
the information bytes from the external RAM to this
one byte buffer for transmission. The receive buffer
starts at location IOH and the receiver buffer length is
1. This buffer is used to buffer the frame transmitted by
the primary. The received byte is used as an address
byte.
The Secondary is configured like the Primary station. It
is put in Flexible mode, externally clocked, Point-topoint frame format. The PFS bit is set to transmit two
bytes before the first flag of a frame. The RBE bit is set
to put the chip in receive mode. Upon reception of a
valid frame, the SIU loads the received information
byte into the on-chip receive buffer and interrupts the
CPU.
SIU Interrupt Routine
In the serial interrupt routine, the RBE bit is checked
(see Figure 14). Since RBE is clear, a frame has been
received. The received Information byte is compared
with the contents of the Station Address (STAD) register.

292019-14

Receive Interrupt Routine
Figure 12. Primary Station FI.ow Charts
15-41

intJ

FLEXIBILITY IN FRAME SIZE WITH THE 8044

= 1. FRAME

XMlmD

ADDRESS NOT MATCHED

292019-15

292019-16

Main Program

SIU Interrupt

Figure 13. Secondary Station Flow Charts

Figure 14. Secondary Station Flow Charts

If they match,thesecondary will call the transmit sub·
routine to transmit the long frame. Upon returning
from the transmit subroutine, the RBE bit is set, and
program returns from the SIU interrupt. Mter trans·
mission of the closing flag, sm interrupt occurs again.
In the interrupt routine, the RBE is checked. Since the
RBE is' set, the program returns from the SIU interrupt
routine and waits until another long frame is received.

While the bit processor is transmitting the first Pre·
Frame Sync byte, the byte processor executes the PFS2
state and jumps to the standby mode in the FLAG
state. The FLAG state is executed when the bit proces·
sor begins to transmit the sec9nd Pre·Frame Sync byte.
When the flag is being transmitted, the byte processor
executes the 98-1, 98-2, 98-3, and 98-4 procedures of
the FLAG state, and jumps to execute the A8-1 procedure of the CONTROL state. When the opening flag is
transmitted, the contents of RB are the fttst information byte. (See transmit state diagram.)

If the secondary were in Auto mode, the chip must be

ready to execute the transmit routine upon reception of
a poll·frame; otherwise, the chip automatically trans·
mits the contents of the internal transmit buffer if the
TBF bit is set, or transmits a supervisory command
(RR or RNR) if TBF is clear.
Transmit Subroutine
In Normal operation the byte processor executes the
START·TRANSMIT state and jumps to the PFSI
state. While the bit processor is transmitting some un·
wanted bits, the byte processor executes the PFSI state
and jumps to the standby mode in the PFS2 state.

In the transmit subroutine (see Figure 15), the byte
processor is forced to repeat the CONTROL state before the DMA-LOOP state. In the CONTROL state,
the contents of a RAM location addressed by the TBS .
register are moved to the RB register. The following is
the step by step procedure to transmit long frames:
1) Put the chip in transmit mode by setting the ins
and TBF bits.
2) Move an information byte from external RAM to a
location in the internal RAM addressed by the contents of TBS.

15-42

infef

FLEXIBILITY IN FRAME SIZE WITH THE 8044

3) Monitor the SIUST register for the standby mode in
the DMA-LOOP state (SIVST = BOH). When
SIUST is BOH, the opening flag has been transmitted, and the first information byte is being transmitted by the bit processor.
4) If there are more information bytes, move the byte
processor back to the CONTROL state, and repeat
steps 2 through 4. Otherwise, continue.
5) Move byte processor to the Standby mode in the
CONTROL state (SIUST = ASH) and return from
the subroutine.
The byte processor automatically executes the remaining states to send the FCS bytes and the closing flag.
After the completion of transmission, SIU updates the
STS and NSNR registers and interrupts the CPU.
If the contents of the TBL register were more than I,

the SIV transmits (TBL)-I additional bytes from the
internal RAM at starting address (TBS) + I because it
executes the DMA-LOOP state (TBL) -I additional
times. The byte processor should' not be programmed to
skip the DMA-LOOP state, because the transmission of
FCS bytes is enabled in this state.
The maximum baud rate that can be used with these
codes is calculated by adding the number of instruction
cycles executed, during the standby mode, between
each byte boundaries (see Table 2) .
. Using Equation I, the maximum data rate, based on the
transmit software, is 509 Kbps; However, the maximum count rate of the counter limits the data rate to
500 Kbps.

292019-17

Transmit Subroutine
Figure 15. Secondary Station Flow Charts

Table 2. Codes for Lon Frame Transmission

Transmit Codes

TRAN:

LOOP:
WAIT1:

NEXTI:
END

•
•
•

MOV

MOV
SETB
SETB
MOVX
MOV
MOV
CJNE
INC
MOVX
MOV
DJNZ
MOV
RET
MOV
MOV
JMP

Cycles

•
•
•

DPTR.#200H
R5. #OFFH
TBF
RTS
A.@DPTR
@Rl.A
A. #OBOH
A.SIUST.WAIT1 •••••••••••••••••••• 2
DPTR ••••••••• ~ ••••••••••••••••••• 2
A,@DPTR ••••••••••••••••••••••••• 2

@Rl.A ••••••••••••••••••••••••••• 1
R5,NEXTI ••••••••••••••••••••••••• 2

SIUST.#57H
SIUST. #57H •••••••••••••••••••••• 2
A. #OBOH ••••••••••••••••••••••••• 1
WAITl •••••••••••••••••••••••••••• 1

13 Cycles
15-43

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

6.2 Multidrop Application
Performance of long frame in addition to the features of
the 8044 are described using a sUnple multidrop communication system in which three RUPIs, one as a
master and the other two as secondary stations, transmit and receive ICing frames alternately (see Figure 16).
All stations perform automatic Zero bit, insertion/dele- ,
tion, NRZI decoding/encoding, Frame Check Sequence (FCS) generation/detection, and on-chip clock
recovery at a data rate of 375 Kbps.
'
'The primary and the secondary station's software code
is giveri in Appendix B. These programs, for simplicity,
assume only reception of information and supervisory
frames. It is also assumed that the frames are received
and transmitted in order: All stations use very similar
transmit and receive routines. This code is written for
standard SDLC frames (see Figure 7).
6.2.1 POLLING SEQUENCE

The priinary station, in Flexible mode, transmits a long
frame (for this example, 255 I-bytes), polls one of the

secondary stations, and acknowledges a previously received frame simultaneously (see Figure 17). Both secondary stations, in Auto mode, detect the transmitted
frame and check its address byte. One of the secondary
stations receives the frame, stores the Iriformation bytes
in an external RAM buffer, and transmits the same
data back to the priinary. After reception of the frame,
the primary polls and transmits a long frame to the
other secondary station which will' respond with the
same long frame.
'
6.2.2 HARDWARE

The schematic of the secondary station hardware is
shown in Figure 18. The primary station's hardware is
similar to the secondary station's hardware. The exception is in secondary stations only, where the RTS signal
is inverted and tied to the interrupt 0 input pin (INTO).
In the primary station, RTS is tied to CTS. At each
station, software codes are stored in' external EPROM
(2732A). Static RAM (2Kx8) is used as external transmit/receive buffer. There is no hardware handshaking
done between the stations, The serial clock is extracted
from the data line using the on-chip phase locked loop.

PRIMARY
STATION

SECONDARY
STATION

SECONDARY
STATION
292019-18

Figure 16. SDLC Multidrop Application Example

PRIMARY

SECONDARY

SECONDARY
292019-19

Figure 17. POlling Sequence Between the Primary and Secondary Stations

15-44

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292019-20

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infef

FLEXIBILITY IN FRAME SIZE WITH THE 8044

.6.2.3 PRIMARY SOFTWARE
Main Routine,

During initialization (see Figure 19), the 8044 is set to
Flexible mode, internally clocked at 375 Kbps, and
configured to handle standard SDLC frames. The onchip receive and transmit buffer starting addresses and
lengths are selected. The external transmit buffer is
chosen from physical location 200H to location 2FFH
(255 bytes). The external transmit buffer' (external
RAM) is loaded with data (FFH, FEH, FDH, FCH,
... OOH). Timer 0 is put in counter mode and set to
priority I. The counter register (TLO) is loaded such
that interrupt occurs after 8 transitions on the data line.
The Pre-Frame Sync option (setting bit 2 of the SMD
register) is selected to guarantee at least 16 transitions
before the opening flag of a frame.

The station address register (STAD) is loaded with address of one of the secondary stations. The RTS, TBF,
and RBE bits of the STS register are simultaneously set
and a call to the transmit routine follows. The transmit
routine transmits the contents of the external transmit
buffer. At the end of transmission, RTS and TBF are
cleared by the SIU, and SIU interrupt occurs. In Flexible mode, SIU interrupt occurs after every transmission or reception of a frame.
SIU Interrupt Routine

In the SIU interrupt service routine (see Figure 20), SI
is cleared and the RBE bit is checked. If RBE is set, a
long frame has been transmitted. The first time through
the SIU interrupt service routine, the RBE test indicates a long frame has been transmitted to one of the
secondary stations. Therefore, the Counter is initialized

=1. FRAME XMITTED

292019-22

292019-21

Main Program

SIU Interrupt

Figure 19. Primary Station Flow Charts

Figure 20. Prirriary Station Flow Charts

15-46

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

and turned on. The program returns from the interrupt
routine before a frame appears on the communication
channel.
When a frame appears on the communication line,
counter interrupt occurs and the receive routine is executed to move the incoming bytes into the external
RAM. After reception of the frame and return from the
receive routine, SIU interrupt occurs again.
In the SIU interrupt routine, RBE is checked. Since the
RBE bit is clear, a frame has been received. Therefore,
the appropriate NS and NR counters are incremented
and loaded into the TCB register (two pairs of internal
RAM bytes keep track of NS and NR counts for the
two secondary stations). Transmission of a frame to the
next secondary station is enabled' by setting the RTS
and the TBF bits. The chip is also put in receive mode
(RBE set), and a call to transmit routine is made. After
transmission, SIU interrupt occurs again, and the process continues.
6.2.4 SECONDARY SOFTWARE
Main Routine

Both secondary stations have idep.tical software (Appendix B). The only differences are the station addresses. Contents of the STAD register are 55H for one station and 44H for the other.

SET UP ~XTERNAL AND INTERNAL
TRANSMIT AND RECEIVE BUFFERS

The secondary is configured to transmit an Information
frame every time it is polled. The RTS pin is inverted
and tied to INTI pin. External interrupt 1 is enabled
and set to interrupt on low to high transition of the
RTS signal. This will cause an interrupt (EXI set) after
a frame is transmitted. In the interrupt routine the CTS
pin is cleared to prevent any automatic response from
the secondary. If the CTS pin were not disabled, the
secondary station would respond with a supervisory
frame (RNR) since the TBF is set to zero by the SIU
due to the acknowledge. In the SIU interrupt routine,
the CTS pin is cleared after the TBF bit is set. If this
option is not used, the primary should acknowledge the
previously received frame and poll for the next frame in
two separate transmissions.
SIU Interrupt Routine

When a frame is received, counter 0 iiIterrupt occurs
and the receive routine is executed (see Figure 22). If
the incoming frame is addressed to the station, the information bytes are stored in external RAM; Otherwise, the program returns from the receive routine to
perform other tasks. At the end of the frame, SIU interrupt occurs. In Auto mode, SIU interrupt occurs whenever an Information frame or a supervisory frame is
received. Transmission will not cause an interrupt. In
the SIU interrupt service routine, the AM bit of the
STS is checked.
If AM bit is set, the interrupt is due to a frame whose
address did not match with the address of the station.
In this case, NFCS, AM, and the BOY bits are cleared,
the RBE bit is set, the counter 0 is initialized and
turned on, and program returns from the interrupt routine.

If AM bit is not set, a valid frame has been received and
stored in the external RAM. TBF bit is set, CTS pin is
activated, counter 0 is disabled and a call to transmit
routine is made which transmits the contents of external transmit buffer. This frame also acknowledges the
reception of the previously received frame (NS and NR
are automatically incremented). Upon return from the
transmit routine RBE is set and counter 0 is turned on,
thereby putting the chip in the receive mode for another round of data exchange with the primary.

292019-23

Main Program
Figure 21. Secondary Station Flow Charts

During initialization, the chip is set to Auto mode,
standard SDLC frame, and internally clocked at
375 Kbps (see Figure 21). Internal buffer registers:
RBS, RBL, TBS, and TBL are initialized. The RBE bit
is set and the counter·.O is turned on.

Note that, if the second station is in receive mode, and
the counter is enabled and turned on, the CPU will be
interrupted each time a frame is on the communication
channel. If the frame is not addressed to the secondary
station, the chip enters the receive routine, executes
only a few lines of code (address comparison) and returns to perform other tasks. This interrupt will not
occupy the CPU for more than two data byte periods
(43 microseconds at 375 Kbps). At the end of the
frame, the BOY bit is set by the SIU, and the SIU
interrupt occurs. In the SIU interrupt service routine,

15-47

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

In tp.e receive interrupt service routine (see Figure 23),
counter 0 is turned off, important registers ·are saved,
receive buffer starting address and receive buffer length
of the external RAM are set (do not confuse the external RAM settings with that of the internal RAM buffer.)
After reception of.an opening flag, the byte processor
jumps to the ADDRESS state and waits until the bit
processor processes and moves the receiving address
byte to SR. Then, the byte processor is triggered to
execute the state. In the secondary stations, the CPU
monitors the SIUST register for the ADDRESS state
(SIUST = OSH). When the ADDRESS state is
reached, the byte processor is moved to the next state
(CONTROL state), and the ADDRESS state is
skipped. Therefore, when the address byte is moved to
SR, the byte processor executes the CONTROL state
rather than the ADDRESS state and then jumps to the
PUSH-l state. The execution of the CONTROL state
causes the contents of SR (the received address byte) to
be loaded into the RCB register.

=I, ADDRESS MATCHED

The CPU cheCks the contents of RCB with the contents
of the STAD (Station Address) register. If they match,
the receive routine continues to store the received Information bytes in the external RAM buffer; Otherwise, the byte processor is moved to the very last state
(BOY-LOOP); and the program returns from the routine to perform other tasks. The byte processor executes
the BOY-LOOP state in each byte boundary until the
closing flag of the frame is reached. It then sets the
BOY bit and interrupts the CPU (serial interrupt SI
set). In the serial interrupt routine the counter 0 is
turned back on, and the station is reset back. to the
receive mode (RBE set).

292019-24

SIU Interrupt
Figure 22. Secondary Station Flow Charts
the RBE bit is set and the counter is turned on which
put the chip back in the receive mode.

6.2.5 RECEIVE INTERRUPT ROUTINE
Assembly code for the receive interrUpt routine can be
found in both primary and secondary software (Appendix B). The receive interrupt routine of the primary
station is very similar to that of the primary station in
example 1. In the following two sections the receive and
transmit routine of the secondary stations are discussed.

In Normal operation, in the ADDRESS state, the received address byte is automatically compared with the
station address. If they match, the byte processor executes the remaining states; otherwise, the byte proces- .
sor goes into the idle mode (SIUST = OIH) and waits
for the opening flag of the next frame. In the expanded
operation, this state is skipped to avoid idle mode. If
the byte processor went into the idle mode, clocks
which run the byte processor would be turned off, and
the byte processor can not be moved to any other states
by the CPU. When the byte processor is in idle mode,
counter 0 can not be turned on immediately because
counter interrupt occurs on the same frame, and program returns to the receive routine and stays there.
If the address byte matches the station address, the byte
processor is moved to the CONTROL state again. This
time, after execution of the CONTROL state the contents of RCB are the received control byte.
.

CPU investigates the type of received frame by checking the received control byte. If the receiving frame is
not an information frame (i.e. Supervisory frame), execution of receive routine will be terminated to free the

15-48

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292019-25

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

CPU. In Auto mode, the SIU checks the control byte
and responds automatically in response to the supervisory frame.
After the control byte is received, it is saved in the
stack. The byte processor is moved to the CONTROL
state so that the next incoming byte will also be loaded
into the RCB register. The byte processor remains in
CONTROL state until a byte is processed by the bit
processor and moved to SR. The byte processor is then
triggered to move the contents of SR to the RCB register. The CPU monitors SIUST and waits until the first
Information byte is loaded into the RCB register.
When byte processor reaches the PUSH-I state (SIUST
= ISH), RCB contains the first Information byte. The
byte is moved to external RAM (receive buffer), and
the byte processor is moved back to the CONTROL
state. The process continues until all of the Information
bytes are received. When all the Information bytes are
received, the program returns from the routine. The
byte processor automatically goes through the remaining states, updates the STS register, and interrupts the
CPU as it would in Normal operation.
6.2.6 TRANSMIT SUBROUTINE

The transmit subroutine codes can be found in the primary and the secondary software (Appendix B). The
transmit subroutines of the Primary and secondary sta-,
tions are identical. A call to transmit routine is made
when the R TS and TBF bits of the STS register are set.
In Auto mode, RTS is set automatically upon reception
of a poll-frame (poll bit of the control byte is set).
In the transmit routine (see Figure 15), the starting address and the transmit buffer length of the external
buffer are set. Then the CPU moiritors the SIUST register for CONTROL state (SIUST = ASH). In the
CONTROL' state the bit processor transmits the control byte, while the byte processor goes into the standby
mode after it has moved the contents of a location in
the internal RAM addressed by the contents of Transmit Buffer Start (TBS) register to the RB register.
While the control byte is being transmitted' and the byte
processor is in standby, the CPU moves an Information

byte from external RAM to the internal RAM location
addressed by TBS. The byte processor is then moved to
CONTROL state. This will cause the byte processor, in
the next byte boundary, to move the contents of the
same location in the internal RAM to the RB register
(see transmit state diagram.)
When this byte is being transmitted, the byte processor
jumps to the DMA-LOOP state (SIUST = BaH) and
waits. When the DMA-LOOP state is reached (CPU
monitors SIUST for BOH), the CPU loads the next Information byte into the same location -in the internal
RAM and moves the byte processor to the CONTROL
state before it gets to execute the DMA-LOOP state.
Note that the same location in the internal RAM is
used to transmit the subsequent Information bytes.
When all the Information bytes from the external
RAM are transmitted, the byte processor is free to go
through the remaining states so that it will transmit the
FCS bytes and the closing flag.

7.0 CONCLUSIONS
The RUPI, with addition of only a few bytes of code,
can accept and transmit large frames with some compromise in the maximum data rate. It can be used in
Auto or Flexible mode, with external or internal clock, ing, automatic CRe checking, and zero bit insertion/
deletion. In addition, almost all of the internal RAM is
available to be used as general purpose registers, or in
conjunction with the external RAM as transmit and
receive buffers.
All in all, this feature opens up new areas of applications for this device. Besides transmitting/receiving
long frames, it may now be possible to perform arithmetic operations or bit manipulation (e.g. data scrambling) while transmission or reception is taking place,
resulting in high throughput. Transmission of continuous flags and transmission with no zero insertion are
also possible.
In addition to unlimited frame size, an on-chip controller, automatic SDLC responses, full support of SDLC
protocol, 192 bytes of internal RAM, and the highest
data rate in self clocked mode compared to other chips
make this product very attractive. '

15-50

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

APPENDIX A
LISTING OF SOFTWARE MODULES
FOR APPLICATION EXAMPLE 1

$DEBUG NOMOD5l.
$INCLUDE (REG44.PDF)
ASSEMBLY CODE FOR PRIMARY STATION (POINT TO POINT)
FLEXIBLE MODE; FCS OPTION
ORG
SJMP

ORG
JMP

ORG
SJMP

DOH
INIT
OBH
REC
23H
SIINT

LOCATIONS 00 THRU 26H ARE USED
BY INTERRUPT SERVICE ROUTINES.
VECTOR ADDRESS FOR TlMERO INT.
VECTOR ADDRESS FOR SIU INT.

; •• ***.*************** INITIALIZATION **** ••• ** ••••• ***.*** •••••
INIT:

DOT:

ORG
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP

26H
SMD, '00000110B
TBS,#20H
TBL,tOlH
20H,#55H
THOD,'OOOOOlUB
IE,nOOlOOl.OB
STS,#l.ll.OOOOOB
DOT

EXT CLOCK;

PFS=NB~l

INT TRANSMIT BUFFER START
INT TRANSMIT BUFFER LENGTH
STATION ADDRESS
COUNTER FUNCTION; MODE
EA=l; SI=l.; ETO=l
TRANSMIT A FRAME
WAIT FOR AN INTERRUPT

SIU TRANSMITS THE PFS BYTES, THE OPENNING FLAG, THE CONTENTS
OF LOCATION 20H, THE CALCULATED FCS-BYTES, AND THE CLOSING
FLAG. AT THE END OF TRANSMISSION, SIU INTERRUPT OCCURS.

;************* SERIAL CHANNEL INTERRUPT ROUTINE

*.*.* •• *******.*

SIINT:

CLR
81
JNB
RaE,RECVED
TRANSMITTED A FRAME ?
MOV
TLO,'OF8H
YES, INITIALIZE COUNTER REGISTER
MOV
DPTR,'200H
EXT RAM RECEIVE BUFFER START
MOV
R5,'OFFH
EXT RAM RECEIVE BUFFER LENGTH
SETS
TRO
TURN ON COUNTER 0
RETI
RETURN
WHEN A FRAME APPEARS ON THE SERIAL CHANNEL, COUNTER (RECEIVE)
INTERRUPT OCCURS. AFTER SERVICING THE INTERRUPT ROUTINE, SID
INTERRUPT OCCURS.

RECVED: MOV
RETI

STS, 'l.ll.OOOOOB

292019-28

TRANSMIT A FRAME
RETURN

,.*************** RECEIVE INTERRUPT ROUTINE .*****.*************
REC:
WAITl:
NEXTI:
WAIT2:

END

TRO
A,U8H
A, SIUST, WAITl
MOV
SIUST, 'OEFH .
MOV A,U8H
CJNE A, SIUST, WAIT2
MOV A,Res
MOVX @DPTR,A
INC
DPTR
DJNZ R5,NEXTI
RETI
.CLR
MOV

CJNE

DISABLE THE COUNTER 0 INTERRUPT
PUSH-l STATE
MOVE BYP TO CONTROL STATE
PUSH-l STATE
MOVE RECEIVED BYTE INTO ACC.
MOVE DATA TO EXT. RAM
INCREMENT POINTER TO EXT RAM
LAST BYTE RECEIVED?
YES, RETURN
292019-29

15-51

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

$DEBUG NOMOD51
$INCLUDE (REG44.PDF)
ASSEMBLY CODE FOR SECONDARY STATION (POINT TO POINT)
FLEXIBLE MODEl FCS OPTION
ORG
SJIIP
ORG
SJIIP

OOH
INIT
23H
SIINT

,*.t •••••••••••••
ORG
INIT: MOV
MOV
LDRAM: MOV
MOVX
INC
DJNZ

; VECTOR ADDRESS FOR SIU INT.

tpAD TRANSMIT BUFFER WITH DATA

26H
DPTR,#200H
R3,tOFFH
A,R3
@DPTR,A
DPTR
R3,LDRAM

EXT RAM XHIT BUFFER START
EXT RAM XHIT BUFFER LENGHT
LOAD EXT BUFFER WITH FFH,FEH, •••
INCREMENT POINTER

;**** •• *************INITIALIZATION

DOT:

HOV
HOV
MOV
MOV
MOV
MOV
HOV
MOV
MOV
MOV
HOV
SJHP

.t.t •••••••••

SHU,IOOOOOllOB
Rl,#lOH
TBS,Rl
TBL,f01H
RBS,t20H
RBL,fOlH
STAD,USH
TCON,tOOH
IE,U0010000B
IP,fOFFH
STS,f01000000B

*tttt ••••••••••

* •••••••••••

EXT CLOCK; PFS=lIB=l
INT RAM XHIT BUFFER START
INT RAM XHIT BUFFER LENGTH
INT RAM RECEIVE BUFFER START
INT RAM RECEIVE BUFFER LENGTH
STAD ADDRESS=55H
RESET TCON REGISTER
ENABLE SI INT. IEA=l
ALL INTERRUPTS I PRIORITY 1
RBE-l, RECEIVE A FRAME.
WAIT FOR AN INTERRUPT

DOT

I SIU INTERRUPT OCCURS AT THE END OF A RECEIVED FRAME OR
; A TRANSMITTED FRAME.

,******* ••• *****

SERIAL CHANNEL INTERRUPT ROUTINE

SI
RBE, RETlIN
HOV
A,STAD
CJNE A,20H,NKACH
ACALL TRAN

tttttIA •••••

292019-30

SIINT: CLR
JB

RECEIVED A FRAME?
YES
STATION ADDRESS MATCHED?
YES, CALL TRANSMIT SUBROUTINE

TRANSMIT SUBROUTINE IS CALLED TO TRANSMIT A LONG FRAME.
AFTER TRANSMISSION, ,51 IS SET. SIU INTERRRUPT IS SERVICED
AFTER THE CURRENT ROUTINE (SIINT) IS COMPLETED.
NKACH: SETB
RETlIN: RETI

RBE

;

RBE~l,

RECEIVE A FRAME

; RETURN

;.t •• t.A ••••••• TRANSMIT SUBROUTINE *ttttIA •••••••••••••••••••
TRAN:

HOV
MOV
SETB
. SETB
LOOP: MOVX
MOV
MOV
WAIT1: CJNE
INC
DJNZ
MOVX
HOV
HOV

DPTR,f200H
RS,tOFFH
TBF
RTS
A,@DPTR
@Rl,A
A,fOBOH
A,SIUST,WAITl
DPTR
RS,NEXTI
A,@DPTR
@Rl,A
SroST"S7H

RET
NEXTI: MOV
JIIP
END

SIUST,'S7H
LOOP

EXT RAM RECEIVE BUFFER START
EXT RAM RECEIVE BUFFER LENGTH
SET TRANSMIT BUFFER FULL
ENABLE XHISSION OF AN I-FRAME
MOVE THE 1ST I-BYTE INTO ACC.
THEN, MOVE TO INT. RAM @ (TBS)
DKA-LOOP STATE
WAIT FOR XHISSION OF AN I-FRAME
INCREMENT POINTER TO EXT. RAM
ALL BYTES XHITTED?
YES, EXCEPT THE LAST BYTE.
MOVE DATA INTO INT. RAM I! (TBS)
MOVE BYP TO CONTROL STATE
THE SIU TRANSMITS THE FCS-BYTES
AND THE CLOSING FLAG.
RETURN
MOVE BYP TO CONTROL STATE (ASH).
TRANSMIT THE NEXT BYTE

292019-31

15-52

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

APPENDIX B
LISTING OF SOFTWARE MODULES
FOR APPLICATION EXAMPLE 2

$DEBUG NOMODSl
$INCLUDE (REG44.PDF)
ASSEMBLY CODE FOR PRIMARY STATION (MULTIPOINT)
FLEXIBLE MODE; FCS OPTION
ORG
SJMP
ORG
JMP
ORG
SJMP

OOH
INIT

OBH

REC
23H
SlINT

LOCATIONS 00 THRU 26H ARE USED
BY INTERRUPT SERVICE ROUTINES.
VECTOR ADDRESS FOR TlMERO INT.
VECTOR ADDRESS FOR SIU INT.

,******** •• ****** LOAD TRANSMIT BUFFER WITH DATA ••• *********
ORG
MOV
MOV
LDRAM: MOV
MOVX
INC
DJNZ
INIT:

26H
DPTR, f200H
R3,#OFFH
A,R3
@DPTR,A
DPTR
R3, LDRAM

EXT RAM XMIT BUFFER START
EXT RAM XMIT BUFFER LENGHT
LOAD BUFFER WITH FFH,FEH, ••• OO
INCREMENT POINTER

;********************* INITIALIZATION ******.*** •• **** •••• **.

LOOP:

MOV
MOV·
MOV
DEC
CJNE

RO,#OBFH
A,tOOH
@RO,A
RO
RO,#4oH,LOOP

PUT ZEROS INTO INT. RAM
FROM BFH TO 40H.
MOVE 0 INTO RAM ADDRESSD BY RO

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
KOV
MOV
MOV
MOV
MOV
MOV
MOV

30H, 'OOH
31H, 'OOH
32H, #OFFH
33H, #OFFH
34H, 'OlH
SMD,#llOlOlOOB
RBS,flOH
RBI., 'OOH
Rl,#20H
TBS,Rl
TBL, 'OlH
NSNR, 'OOH
THOD,#OOOOOlllB
TCON,jOOH
IE,#lOOlOOlOB
IP,#OOOOOOlOB
TCB,#OOOlOOOOB
STAD, #SSH
STS,tlllOOOOOB

NS COUNTER FOR STAD=SS
NR COUNTER FOR STAD=SS
NS. COUNTER FOR STAD=44
NR COUNTER FOR STAD~44
PONITER TO SECONDARY STATIONS
INT. CLKED @ 37SK; NRZI=l; PFS=l
INT. RAM RECEIVE BUFFER STAR~lOH
INT. RAM RECEIVE BUFFER LENGTH=O
INT. RAM XMIT BUFFER START-20H

292019-32

INT. RAM XMIT BUFFER LENGTH=l
NS=NR=O
COUNTER FUNCTION, MODE 3
EA-l; SI=ll ETO-i
TIMER 0 INT. PRIORITY 1
I-FRAME W/POLL
ADDRESS BYTE=SSH
RBE=TBF-RTS=l

TRANSMIT A LONG FRAME WITH POLL BIT SET, WAIT FOR.A
RESPONSE.
DOT:

ACALL TRAM
SJMP DOT

CALL TRANSMIT ROUTINE
WAIT FOR AN INTERRUPT

15-53

292019-33

inter

FLEXIBILITY IN FRAME SIZE WITH THE 8044

;************* SERIAL INTERRUPT ROU~INE *****************.*.*
SIINT:

SKIP:

CLR
JB
MOV
JB
MOV
CJNE
MOV
INC
ANL
MOV
MOV
INC
ANL
MOV
RL
RL
RL
RL
ORL
RL
ORL
MOV
MOV
MOV
JMP
MOV
INC
ANL
MOV
MOV
INC
ANL
MOV
RL
RL
RL
RL
ORL
RL
ORL
MOV

SI
RBE, RETl1RII

A,RCB
ACC.O,GETI
A,f01H
A,34H,SKIP
A,30H
A
A, #00000111B
30H,A

A,.3lH
A
A, #00000111B
31H,A
A
A
A
A
A,30H
A
A,.00010000B
TeStA

CLEAR SI
RECEIVED A FRAME ?'
YES, LOAD ACC WITH REC CNTRL BYTE
IS IT AN I-FRAME ?
YES
MOVE NS INTO
INCREMENT NS
MASK OUT THE
SAVE NS
MOVE NR INTO
INCREMENT NR
MASK OUT THE
SAVE NR
SHIFT 4 BITS

ACC.
LEAST 3 SIG. BITS
ACC.
LEAST

SIG. BITS

TO LEFT

MOVE NS COUNT TO ACC.
SHIFT 1 BIT TO LEFT
SET THE POLL BIT
MOVE CONTROL BY'l'E INTO TCB REG.

'lCB: NR2,HRl,NRO,1,HS2,NS1,NSO,O
STAD"SSH
34H,foOH
GETI
A,32H
A
A, '00000111B
32H,A
A,33H
A
A, #OOOOOll1B

33H,A
A
A
A
A
A,33R
A
A,'OOO10000B
TCB,A

292019-34
I MOVE NS INTO ACC.

INCREMENT NS
MASK OUT THE
SAVE NS
MOVE NR INTO
INCREMENT NR
MASK OUT THE
SAVE NR
SHIFT 4 BITS

LEAST 3 SIG. BITS
ACC.
LEAST

SIG. BITS

TO LEFT

MOVE NS COUNT TO ACC.
SRIFT 1 BIT TO LEFT
SET THE POLL BIT
MOVE CONTROL BYTE INTO TCB

TeB: NR2,NR1,NRO,1,NS2,HSl,NSO,O
MOV
MOV
GETI:
MOV
ACALL
RETI
RETl1RII: CLR
MOV
SETB
SETB
RETI

STAD,#44R
34R,#01R
STS, '11100000B
TRAN
EA
TLO,IOFBR
TRO
EA

WAIT1:
NEXTI:
WAIT2:

CLR
MOV
MOV
MOV
CJNE
PUSH
MOV
MOV
CJNE
MOV
MOVX
INC
DJNZ
POP
RETI

RECEIVE INTERRUPT ROUTINE

TRO
DPTR,#400H
RS,foFFH
A,U8H
A,SIUST,WAITl
RCB
SIUST, 'OEFH
A,U8H
A, SIUST, WAIT2
A,RCB
@DPTR,A
DPTR
RS,NEXTI
RCB

,* ••• *******.*** ••
TRAN:
WA:IT:

NXTI:

MOV
MOV
MOV
CJNE
MOVX
MOV
INC
DJNZ
MOV
RET
MOV
MOV
JMP

DISABLE ALL INTERRUPTS
INTERRUPT AFTER 8 COUNTS
Tl1RII ON COUNTER 0

292019-35

;.*****.**** •••
REC:

ENABLE TRANSMISSION
CALL TRANSMIT ROUTINE

°

Tl1RII OFF COUNTER
EXT. RAM RECEIVE BUFFER START
EXT. RAM RECEIVE BUFFER LENGTH
PUSH-l STATE
WAIT FOR THE CONTROL BY'l'E
SAVE RECEIVE CONTROL BYTE
PUSH "BYP" INTO CONTROL STATE (lOB) •
PUSR-l STATE
WAIT FOR AN I-BYTE
MOVE RECEIVED I-BYTE INTO ACC.
MOVE DATA TO EXT. RAM,
INCREMENT PTR TO EXTERNAL RAM
IS IT THE LAST I-BYTE?
YES, RESTORE THE CONTENTS OF RCB
I RETl1RII

TRANSMIT SUBROUTINE

DPTR,#200R
RS,#OFFH
A,loASH
A,SIUST,WAIT
A,@DPTR
@Rl,A
DPTR
RS,NXTI
S:IUST,#57H
S:IUST,#S7H
A,.OBOH
WAIT

********.*.*.**.*.*

*************.**** ••

**

EXT. RAM TRANSMIT BUFFER START
EXT. RAM TRANSMIT BUFFER LENGTH
CONTROL STATE
WA:IT FOR CTRL BY'l'E XMISS:ION
MOVE DATA FROM EXT. RAM TO Ace.
MOVE DATA INTO :INT. RAM @ (TBS)
INCREMENT POINTER
IS :IT THE LAST :I-BYTE ?
NO.' XMIT THE LAST I-BYTE
RETl1RII.
KEEP "BYP" IN CONTROL STATE(A8H).
I DMA-LOOP STATE
TRANSM:IT THE NEXT BYTE

END

292019-36

15-54

FLEXIBILITY IN FRAME SIZE WITH THE 8044

$DEBUG NOHODSl
$INCLUDE (REG44. PDF)
ASSEMBLY CODE FOR SECONDARY STATIONS (MULTIPOINT)
AUTO MODE; FCS OPTION
ORG
OOH
SJHP INIT
ORG
OBH
REC
JHP
ORG
13H
XINTl
JHP
'ORG
23H
SIINT
JHP

VECTOR ADDRESS FOR TlHERO INT.
VECTOR ADDRESS FOR EXT. INT. 1
VECTOR ADDRESS FOR SIU INTERRUPT

,********········***INITIALIZATION •••••••••••••••••••••••••••
INIT:

ORG
MOV
HOV

26H
SMD,U1010100B
STAD,'SSH

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

RDS,UOH
RBL, 'OOH
Rl,#20H
TBS,Rl
TBL, 'OlH
NSNR,tOOH
TCON,#OOOOOlOOB
IE,'OOOlOllOB
IP"OOOOOOlOB
THOD,#OOOOOllB
STS,t01000010B
TLO"OF8H

INT. CLKED @ 375KINRZI-l;PFS-l
STATION ADDRESS; STAD-44H FOR THE
OTHER STATION
INT. RAN RECEIVE BUFFER START
INT. RAN RECEIVE BUFFER LENGTH
INT. RAN XKIT BUFFER START
INT. RAN XKIT BUFFER LENGTH
NS~NR-O

EXT. INT.: EDGE TRIGGERED
SI~l; ETO~l; EXO=l
TlHER 0: PRIORITY 1
COUNTER FUNCTION: MODE
RECEIVE I-FRAME.
SET COUNTER TO OVERFLOW
AFTER B COUNTS
5ETB TRO
TURN ON COUNTER
SETB EA
I ENABLE ALL INTERRUPTS
DOT:
SJHP DOT
I WAIT FOR AN INTERRUPT.
I CPU IS INTERRUPTED AT THE END OF RECEPTION (51 SET), AND AT.
; THE END OF LONG-FRAME TRANSMISSION (EXO SET).

292019-37

•

,****** •• *******EXTERNAL
XINT1:

SETB

INTERRUPT •••••••••••••••••••••••••••

Pl. 7

; DISABLE CTS PIN

RETI

; RETURN.

;•• *••••••••••••
SIINT:

SERIAL INTERRUPT ROUTINE ••••••••••••••••••••

JB

SI
AM,HOP

CLR

EA

CLR

MOV
~OV

SETB
SETS

STS,#OlOOOOlOB
TLO,#OF8H
TRO
EA

RETI
;

HOP:

GETI.:

JB
TBF,GETI
SETB TBF
CLR
Pl.7
ACALL TRAN
JB
RBE,RETURN
CLR

SETB
MOV
SETB
SETB
RETURN: RETI

EA

RBE
TLO, ,OF8H
THO
EA

,*.* ••••••••••••••

TRAN:
WAIT:

MOV
MOV
MOV
CJNE
MOVX
MOV
INC

NXTI:

MOV
RET
MOV
MOV
JHP

DJNZ

ADDRESS MATCHED?
DISABLE ALL INTERRUPTS

RBE-l; NB=l

TURN ON COUNTER 0
ENABLE ALL INTERRUPTS
RETURN.
A FRAME TRANSMITTED?
ENABLE TRANSMISSION OF I-FRAME
ENABLE CTS PIN
CALL TRANSMIT ROUTINE
A FRAME RECEIVED?
DISABLE ALL INTERRUPTS
PUT RUPI IN RECEIVE MODE
TURN ON COUNTER 0
ENABLE ALL INTERRUPTS
RETURN.

TRANSMIT SUBROUTINE

DPTH,UOOH
RS"OFFH
A"OABH
A,SIUST,WAIT
A,@DPTR
@Rl,A
DPTH
RS,NXTI
SIUST, '57H
SIUST,157H
A,'OBOH
WAIT

*.* ••••••••••••••••••••

EXT. RAN TRANSMIT BUFFER START
EXT. RAN TRANSMIT BUFFER LENGTH
CONTHOL STATE
WAIT FOR CONTROL BYTE TRANSMISSION
MOVE DATA FROM EXT. RAN TO ACC.
MOVE DATA INTO INT. RAN AT @TDS
INCREMENT POINTER
IS IT THE LAST I-BYTE ?
XMIT THE LAST I-BYTE
RETURN.
KEEP "BYP" 'IN CONTROL STATE
DHA-LOOP STATE
TRANSMIT THE NEXT BYTE

15-55

292019-38

292019-39

FLEXIBILITY IN FRAME SIZE WITH THE 8044

,**********RECEIVE INTERRUPT ROUTINE ••••••••••••••••••••••••••
REC,

HOLD,

WAITl,

WAIT2,

CLR

TaO

MOV
MOV
MOV
CJNE
MOV

DPTR,f200H
RS,#OFFH
A,I08H
A,SIUST,HOLD
SIUST,tOEFH

MOV
CJNE
MOV
CJNE
SJMP
MOV
MOV
RETI

A,fl8H
A,SIUST,WAITl
A,RCB
A,STAD,WAIT2
WAIT3
RCB,'OOOlOOOOB
SIUST,foCFH

MOV
MOV
CJNE
MOV

SIUST,'OEFH
A,#l8H
A,SIUST,WAIT4
A,RCB
ACC.O,RTRN
RCB
SlUST,'OEFH
A,#l8H
A,SIUST,WAIT5
A,RCB
@DPTR,A
DPTR
R5,NEXTl
RCB

;

WAIT3'
WAIT4,

JB

WAIT5,

PUSH
MOV
MOV
CJNE
MOV
MOVX
INC

RTRN,
END

RETI

NEXTI,

DJNZ

POP

TURN OFF COUNTER 0
EXT. RAM RECEIVE BUFFER START
EXT. RAM RECEIVE' BUFFER LENGTH
ADDRESS STATE
WAIT FOR ADDRESS BYTE
MOVE "BYP" INTO CONTROL STA'l'E
SKIP THE ADDRESS STATE
'.
PUSH-l STATE
WAIT FOR THE ADDRESS BYTE
MOVE THE RECEIVED ADDRESS BYTE TO ACC.
ADDRESS MATCHED?
YES.
MOVE INFO. CONTROL BYTE TO RCB
MOVE "BYP" INTO BOV-LOOP STATE
RETURN
MOVE "BYP" INTO CONTROL STATE
PUSH-l STATE
WAIT FOR THE CONTROL BYTE
MOVE RECEIVE CONTROL BYTE INTO ACC.
IF NOT AN I-FRAME RETURN
SAVE RECEIVE CONTROL BYTE
·PUSH "BYP" INTO CONTROL STATE (lOH) •
PUSH-l STATE
WAIT FOR AN 'I-BYTE
MOVE RECEIVED I-BYTE INTO ACC.
MOVE DATA TO EXT. RAM
INCREHBNT PTR TO EXTERNAL RAM
IS IT THE LAST I-BYTE?
YES. RESTORE THE CONTENTS OF RCB
RETURN

292019-40

15-56

intJ

ARTICLE
REPRINT

AR-307

NOVEMBER 1983

January 1985

©

ORDER NUMBER 230876-001

INTEL CORPORATION

230876-1

15-57

intJ

AR-307

SUMMARY
The 8044 offers a lower cost and higher performance
solution to networking microcontrollers than conventionalsolutions. The system cost 'is lowered by
integrating an entire microcomputer with an intelligent
HDLC/SDLC communication processor onto a single
chip. 1'he higher performance is realized by integrating
two processors running concurrently on one chip; the
powerful 80S I microcontroller and the Serial Interface Unit. The 8051 microcontroller is substantially
off-loaded from the communication tasks when
using the AUTO mode. In the AUTO mode the SIU
handles many of the data link functions in hardware.
The advantages of the AUTO mode are: less software
is required to implement a secondary station data link,
the 8051 CPU is offloaded, and the turn-around time
is reduced, thus increasing the network throughput.
Currently the 8044 is' the only microcontroller with
a sophisticated communications processor on-chip. In
the future there will be more microcontrollers available
following this trend.

acknowledgements, error checking/recovery, and data
transparency are not standardized nor supported by
.
available data comm chips.
SDLC, Synchronous Data Link Control, meets the
requirements for communications link design. The
physical medium can be used on two or four wire
twisted pair with inexpensive transceivers and connectors. It can also be interfaced through modems, which
allows it to be used on broadband networks, leased
or switched telephone lines. VLSI controllers have
been available from a number of vendors for years;
higher performance and more user friendly SDLC controllers continue to appear. SDLC has also been
designed to be very reliable. A 16 bit CRC checks the
integrity of the received data, while frame numbering and acknowledgements are also built in. Using
SDLC, up to 254 stations can be uniquely addressed,
while HDLC addressing is unlimited. If an RS-422
only requires a single +5 volt power supply.

INTRODUCTION
Today microcontrollers are being designed into
virtually every type of equipment. For the household,
they are turning up in refrigerators, thermostats,
burglar alarms, sprinklers, and even water softeners.
At work they are found in laboratory instruments,
copiers, elevators, hospital equipment, and t~lephones.
In addition, a lot of microcomputer equipment contains more than orie microcontroller. Applications
using multiple microcontrollers as well, as the office
and home, are now faced with the same requirements
that laboratory instruments were faced with 12 years
ago - they need to connect them together and have
them communicate. This need was satisfied in the
laboratory with the IEEE-48B General· Purpose
Instrumentation Bus (GPIB). However, GPIB does
not meet the current design objectives for networking microcontrollers.

What will the end user pay for the added value provided by communications? The cost of the communications hardware is not the only additional cost.
There will be performance degradation in the main
application because the microcontroller now has
additional tasks to perform. There are two extremes
to the cost of adding communication capability. One
could spend very little by adding an I/O port and have
the CPU handle everything from the baud rate to the
protocol. Of course the main application would be
idle while the CPU was communicating. The other extreme would be to add another microcontroller to
the system dedicated to communications. This
communications processor could interface to the main
CPU through a high speed parallel link or dual port
RAM. This approach would maintain system performance, but it would be costly.

Today there are many communications schemes and
protocols available; some of the popular ones are
GPIB, Async, HDLC/SDLC, and Ethernet. Common
design objectives of today's networks are: low cost,
reliable, efficient throughput, and expandable. In
examining available solutions, GPIB does not meet
these design objectives; first, the cable is too expensive (parallel communications), second, it can only be
used over a limited distance (20 meters), and third,
it can only handle a limited number of stations. For
general networking, serial communications is
preferable because of lower cable costs and higher
reliability (fewer connections). While Ethernet provides very high performance, it is more of a system
backbone rather than a microcontroller interconnect.
Async, on the other hand, is inexpensive but it is not
an efficient protocol for data block or file transfers.
Even with.some new modifications such as a 9 bit protocol for addressing, important functions such as

Adding HDLe/SDLC Networking Capability
Figure I shows a microcamputer system with a canventianal HDLC, SDLC cammunications salutian.
The additional hardware needed to realize the conventional design is: an HOLC SOLC communicatian
chip. additional ROM for the communicatian saftware.
part af an interrupt cant railer. a baud rate generatar. a
phase lacked laap. NRZI encaded decader. and a
cable driver lacked loap are used when the transmitter
daes nat send the clack an a separate line fram the data
(i.e. aver telephane lines. ar two. wire cable). the NRZI
encader decader is used in HOLC SDLC to. combine
the clack into. the data line. A phase locked laap is used
to recaver the clock fram the data line.

The majority of tire available communication chips
provide a limited number of data link control functions. Most of them will handle Zero Bit Insertion/Deletion (ZBI/D), Flags, Aborts, Automatic
230876-2

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AR-307

MICROCONTROLLER

SERIAL
COMMUNICATIONS
SOLC/HOLe

BAUD
RATE
GENERATOR

Figure 1. Conventional mlcrocontroller networking solution
address recognition, and CRC generation and checking. It is the CPU's responsibility to manage
link access, command recognition and response,
acknowledgements and error recovery. Handling these
tasks can take a lot of CPU time. In addition, servicing the transmission and reception of data bytes can
also be very time consuming depending on the method
used.

require I LSI chip and about 10 TTL chips. The cost
of CPU throughput degradation can be even greater.
The percentage of time the CPU has to spend servicing the communication tasks can be anywhere from
10-1001170, depending on the serial bit rate. These high
costs will prevent consumer acceptance of networking microcomputer equipment.
A Highly Integrated, High Performance Solution
The 8044 reduces the cost of networking microcontrollers without compromising performance. It
contains all of the hardware components necessary to
implement a microcomputer system with communications capability, plus it reduces the CPU and software
overhead of implementing HDLC/SOLC. Figure 2
shows a functional block diagram of the 8044.

U sing a D M A controller ca n increase the overall system
performance. since it can transfer a block of data in
fewer clock cycles than a CPU. In addition. the CPU
and the DMA controller can mUltiplex their access to
the bus so that both can be running at virtually the same
time. However. both the DMA controller and the CPU
are sharing the same bus. therefore. neither one get to
utlize IOO~; of the bus bandwidth. Microcontrollers
available today do not support DMA. therefore. they
would have to use interrupts. since' polling is
unacceptable in a multitasking environment.

The 8044 integrates the powerful 80S I microcontroller
with an intelligent Serial Interface Unit to provide a
single chip solution which efficiently implements a
distributed processing or distributed control system.
The microcontroller is a self sufficient unit containing ROM, RAM, ALU and its own peripherals. The
8044's architecture and instruction set are identical to
the 80S 1~s. The Serial Interface Unit (SIU) uses
bit synchronous HOLC/SOLCprotocol and can communicate at bit rates up to 2.4 Mbps, externally
clocked, or up to 37S Kbps using the on-chip digital
phase locked loop. The SIU contains its own processor, which operates concurrently with the microcontroller.

In an interrupt driven, the CPU has overhead in addition to servicing the interrupt. During each interrupt request the' CPU has to save all of the important
registers, transfer a byte, update pointers and
counters, then restore all of its registers. At low bit
rates this overhead may be insignificant. However, the
percentage of overhead increases linearly with the bit
rate. At high bit rates this overhead would consume
all of the CPU's time. There is another nuisance factor associated with interrupt driven systems, interrupt
latency .. Too much interrupt latency will cause data
to be lost: from underrun and overrun errors.

The CPU and the SIU, in the 8044, interface through
192 bytes of dual port RAM. There is no hardware
arbitration in the dual port RAM. Both processor's
memory access cycles are interlaced; each processor'
has access every other clock cycle. Therefore, there

The additional hardware necessary to implement the
communications solution, as shown in Figure I, would

230876-3

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AR-307

I

SIU

1
1
,..------'-.., .1

I
8051
MICROCONTROLLER

HDLC/SDLC
COMMUNICATIONS
PROCESSOR

DMA
CONTROLLER

L __________ ___ _
~

Figure 2. 8044 single chip mlcrocontroller networking solution

is no throughput loss in either processor as a result
of the dual pon RAM, and execution times are deterministic: Since this has· always been the method for
memory access on the 8051 microcontroller, 8051 programs have the same execution time in the 8044.

transmitted or received. Also, the nuisance of overrun and underrun errors is totally eliminated since the
dedicated DMA controller is guaranteed to meet the
maximum data rates. Having a dedicated DMA coniroller means that the .serial channel interrupt can be
the lowest priority, thus allowing the CPU to have
higher priority real time interrupts.

By integrating all of· the .communication· hardware
onto the 8051 microcontroller, the hardware cost of
the system is reduced. ·Now several chips have been
integrated into a single chip. This means that the
system power is reduced, P.C. board space is reduced, inventory and assembly is reduced, and
reliability is improved. The improvement in reliability is a result of fewer chips and interconnections
on the P.C.board.

Figure 3 sho'ws a c~mparison between the.conventionai
and the 8044 solution on the percentage of time the
CPU must spend sending data. This diagram was
derive.d by assuming a 64 byte information frame is
being transmitted repeatedly. The conventional solution is interrupt driven, and each interrupt service
routine is assumed to take about 15 instructions with
a I /oIsec instruction cycle time. At 533 Kbps, an interrupt would occur every 15 usec. Thus, the CPU
becomes completely dedicated to servicing the serial
communications. The conventional design could not
support bit rates higher than this because of underruns .and overruns. For the 8044 to repeatedly send
64 byte frames, it simply has to reinitiaIize the DMA
controller. As a result, the 8044 can support bit rates
up to 2.4 Mbps.

As·mentioned before, there can be two extremes in
a design which adds communications to the microcomputer system. The 8044 solution uses the high end extreme. The SIU on the 8044 contains its own processor
which communicates with the 8051 processor through
dual port RAM and control/status registers. While
the SIU is not a totally independent communications
processor, it substantially offloads the 805 I processor
from the communication tasks.

Some of the other communications tasks the CPU has
to perform. such as link access. command recognition/response. and acknowledgements. are performed automatically by the SIU in a mode called
"AUTO;" The combination of the dedicated DMA
controller and the AUTO mode. substantially offload

Tbe DMA on the 8044 is dedicated to the SIU. It cannot access external RAM. By having a DMA controller
in the SIU, the 8051 CPU is oftloaded. Asa result
of the dual pon RAM design, the DMA does not share
the running at full speed while .the frames are being

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• CONCURRENT PROCESSING
CONVENTIONAL
SOLUTION
90

80
70

PERCENTAGE OF
CPU TIME SPENT
SERVICING SOLC

60
50
40
30
80.44
SOLUTION

20

1~~__-=====================~
250 K
500 K
750K
1M
BIT RATE (BITS/SECOND)
Figure 3. SIU offloads CPU
the CPU, thus allowing it ,to devote more of its power
to other tasks,

can directly set a bit Which communicates to the
primary what its transmit and receive buffering status
is.

8044's Auto Mode
In the AUTO mode'the SlU implements in hardware
a subset of the SOLC protocol such that it responds
to many SOLC commands without CPU intervention.
All AUTO mode responses to the primary station conform to IBM's SOLC definition. In the AUTO mode
the 8044 can only be a secondary station operating
in SOLC specified "Normal Response Mode."
Normal Response Mode means that the secondary
station· can not transmit unless it is polled by the
primary station. The SIU in the AUTO mode can
recognize and respond to the. following SOLC commands without CPU intervention: I (Information), RR
(Receive Ready), RNR (Receive Not Ready), REJ (Reject), and for loop mode UP (Unnllmbered Poll). The
.SIU can generate the following responses without
CPU intervention: I, RR, and RNR. In addition, the
SIU manages Ns and Nr in the control field. If it
detects an error in either Ns or Nr, it interrupts 'the
CPU for error recovery.

When the CPU wants to send a frame, it loads the
. transmit buffer with the data, loads the starting
address and the COUrit of the data into the SIU, then
sets TBF to transmit the frame. The SIU waits for the
primary station to poll it with a RR command. After
the SIU is polled, it automatically sends the information frame to the primary with the proper control field.
The SIU then waits for a positive acknowledgement·
from the primary before incrementing the Ns field and
interrupting the CPU for more data. If a negative
acknowledgement is received, the SIU automatically
retransmits the frame.
When the 8044 is ready to receive information, the
CPU loads the receive buffer starting address and the
buffer length into the SIU, then.enables the receiver.
When a valid information frame with the correct
address and CRe is received, the SIU will increment
the Nr field, disable the receiver and interrupt the CPU
indicating that a good I frame has been received. The
CPU then sets RBP, reenables the receiver and processes the received data. By enabling the receiver with
RBP set, the SIU will automatically respond to polls
with a Receive Not Ready, thus keeping the link
moving rather than timing out the primary from a
disabled receiver, or interrupting the CPU with
another poll before it has 'processed the data. After
the data has been processed, the CPU clears RBP,
returning to the Receive Ready responses.

How does the SIU know what responses to send to
the primary? It uses two status bits which are set by
the CPU. The two bits are TBF (Transmit Buffer Full)
and RBP (Receive Buffer Protect). TBF indicates that
the CPU wants to send data, and RBP indicates that
the receive data buffer is full. Table I shows the
responses the SIU will send based on these two status
bits. This is an innovative approach to communication design, The CPU in the 8044 with one instruction

230876-5

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Table 1. SIU's automatic responses II) auto mode

'STATUS BITS

RESPONSE

TBF

RBP

o
o

o

(RR) Receive ready

1

(RNR) Receive' not ready

1

o

(I) Information

1

1

(I) ·Information

SDLC communications can be broken up into four
states: Logical Disconnect State, Initialization State,
Frame Reject State, and Information Transfer State.
Data can only be transferred in the Information
Transfer State. More than 90070 of the time a station
will be in the Information Transfer State, which is
where the SIU can run autonomously. In the other
states, where error recovery, online/offline, and initialization takes place, the CPU manages the protocol.

In the Information Transfer State there are three com-'
mon events which occur as illustrated in Figure 4, they
are: I) the primary polls the secondary and the secondary is ready to receive but has nothing to send, 2)
the primary sends the secondary information, and 3)
the secondary sends information to the primary.
Figures 5, 6, and 7 compare the functions the conventional design and the 8044 must execute in order
to respond to the primary for the cases in Figure 4.

PRIMARY

I SECONDARY I

ISECONDARY I
Case 1. Primary polls secondary
secondary has nothing to send
Command
RR

. .

Response
RR

Case 2. Primary polls secondary
,
secondary sends Information frame
Command
Response
RR,NR
..
Information frame

...

RR, NR+1

..

Case 3. Primary sends secondary information frame
Command
Response
RR
..
'RR,NR
Information frame
RR, NR+1
RR = Recelv.e ready

...

Not~:

.
.

Figure 4. SDLC commands ,and responses in the Information transfer state
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CASE 1
8044
AUTO MODE

CONVENTIONAL
DESIGN

PRIMARY

Receive interrupts

-RRPoll

Decode received control field
Check NR field
Load response into transmit control field
Send frame
Transmit interrupts

Figure 5. Primary polls secondary, secondary has· nothin~ to send

CASE 2
8044
·AUTO MODE

PRIMARY

Load transmit buffer
Set TBF bit

-.._ - RR _.- - 1 1...poll

..........- - RR -___
poll

CONVENTIONAL
DESIGN
Load transmit buffer and transmit
control byte
Receive interrupts
Decode receive control byte
Check NR field
Send frame
Transmit interrupts
Receive interrupts
Decode receive control byte
Check NR field
Increment NS

Transmit Interrupt

Figure 6. Primary polls secondary. secondary sends information frame
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CASE 3
8044
AUTO MODE

CONVENTIONAL
DESIGN

PRIMARY'
----RR~

Receive interrupts
Decode received control field
Check NR field
Load response into transmit control
field
Send frame
Transmit interrupts
Receive interrupts
Decode receive control field
Check NS NR fields
Increment NR
Load response into transmit control
field
Send frame
Transmit Interrupts

poll

Receive interrupt

~Iframe_

,

Figure 7. Primary sends information frame to secondary
Using case 1 as an example, the conventional design
first gets receive interrupts bringing the data from the
SOLC comm chip into memory. The CPU must then
decode the command in the control field and determine the response. In addition, it must check the Nr
field for any pending acknowledgements. The CPU
loads the transmit buffer with the appropriate address
and control field, then transmits the frame. When the
8044 receives this frame in AUTO mode, the CPU
never gets an interrupt because the SIU handles the
entire frame reception and response automatically.

. most critical parameter for calculating throughput on
any high speed network is the station turnaround time;
the time it takes a station to respond after receiving,
a frame. Since the 8044 handles all of the commands
and responses of the Information Transfer State in
hardware, the turnaround time is much faster than
handling it in software, hence a higher throughput.

8044's Flexible Mode
In the "NON-AUTO" mode or Flexible mode, the
SIU does not recognize or respond to any commands,
nor does it manage acknowledgements, which means
the CPU must handle link access, command recognition/response, acknowledgements and error recovery
by itself. The Flexible mode allows the 8044 to have
extended address fields and extended control fields,
thus providing HOLC support. In the Flexible mode
the 8044 can operate as a primary station, since it can
transmit without being polled.

In SOLC networks, when there is no information
transfers, case 1 is the activity on the line. Typically
this is 80010 of the network traffic. The CPU in the
conventional design would constantly be getting interrupts and servicing the communications tasks, even
when it has nothing to send or receive. On the other
hand, the 8044 CPU would only get involved in communicating when it has data to send pr receive.

Front End Communications Processor
Having the SIU implement a subset of the SOLC protocol in hardware not only offloads the CPU, but it
also improves the throughput on the network. The

Tile 8044 can also be used as an intelligent
HOLC/SOLC front end for a microporcessor, capable
of extensively off-loading link control functions for
230876-8

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AR-307
computer. Sophisticated secondary stations could also
take advantage of this design.

the microporcessor. In some applications the 8044 can
even be used for communications preprocessing, in
addition to data link control. For this type of design
the 8044 would communicate to the Host CPU
through a FIFO, or dual port RAM. A block diagram
of this design is given in Figure 8. A tightly coupled
interface between the 8044 and the Host CPU would
be established. The Host CPU would give the 8044
high level commands and data which the 8044 would
convert to HOLC/SOLC. This . particular type of
design would be most appropriate for a primary
Station which is normally a micro, mini, or mainframe

Since the 8044 has ROM on chip, all the communications software is non-volatile. The 8044 primary
station could down-line-load software to 8044 secondary stations. Once down-line-loading is implemented,
software updates to the primary and secondary
stations could be done very inexpensively. The only
things which would remain fIXed in ROM are the
HOLC/SOLC communications software and the software interface to the HOST.

SYSTEM
MEMORY

HOST

SYSTEM DATA BUS

INTERFACE
HARDWARE

8044 DATA BUS

8044
EXPANSION
MEMORY
HDLC/SDLC DATA LINK
Figure 8. 8044 front end processor
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ICETM·5100/044In·Circuit Emulator
for the RUPITM·44 Family

•

Precise, Full-Speed, Real-Time
Emulation of the RUPITM-44 Family of
Peripherals

•
•

64 KB of Mappable High-Speed
Emulation Memory

•
•
•

254 24-bit Frames of Trace Memory (16
Bits Trace Program Execution
Addresses and 8 Bits Trace Eternal
Events)
Serial Link to Intel Series III/IV or IBM*
PC AT or PC XT (and PC DOS
Compatibles)
ASM-51 and PL/M-51 Language
Support

•
•
•
•
•

Built-in CRT-Oriented Text Editor

Symbolic Debugging Enables Access to
Memory Locations and Program
Variables
Four Address Breakpoints Plus InRange, Out-of-Range, and Page Breaks
Equipped with the Integrated Command
Directory (ICDTM) That Provides
- On-Line Help
- Syntax Guidance and Checking
- Command Recall
On-Line Disassembler and Single-Line
Assembler to Help with Code Patching
Provides an Ideal Environment for
Debugging BITBUSTM Applications
Code

The ICETM-5100/044 in-~ircuit emulator is a high-level. interactive debugger that is used to develop and test
the hardware and software of a target system based on the RUPITM-44 family of peripherals. The ICE5100/044 emulator can be serially linked to an Intellec® Series III/IV or an IBM PC AT or PC XT. The emulator
can communicate with the host system at standard baud rates up to 19.2K. The design of the emulator
supports all of the RUPI-44 components at speeds up to and including 12 MHz.
·IBM is a registered trademark of International Business Machines Corporation. Intel Corporation assumes no responsibility
for the use of any circuitry other than circuitry embodied in an Intel product. No other patent licenses are implied. Information
contained herein supersedes previously published specifications on these devices from Intel.

280325-1

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November 1988
Order Number: 280325-001

ICETM·5100/044

tion of the microcontroller to debug the system as a
completed unit.

PRODUCT OVERVIEW
The ICE-51001044 emulator provides full emulation
support for the RUPI-44 family of peripherals, including 8044-based BITBUSTM board products. The
RUPI-44 family consists of the 8044, the 8744, and
the 8344.
'
The ICE-5100/044 emulator enables hardware and
software development to proceed simultaneously.
With the ICE-5100/044, prototype hardware can be
added to the system as it is designed and software,
can be developed prior to the completion of the
hardware prototype. Software and hardware integration can occur while the product is being developed. '

The final product verfication test can be performed
using the ROM or EPROM version of the microcontroller. Thus, the ICE-51001044 emulator provides
the ability to debug a prototype or production system
at any stage in its development without introducing
extraneous hardware or software test tools.

PHYSICAL DESCRIPTION
The ICE-5100/044 emulator consists of the following components (see Figure 1):
• Power supply
• AC and DC power cables

The ICE-5100/044 emulator assists four stages of
development:
.

• Controller pod
• Serial Cable (host-specific)
• User probe assembly (consisting of the processor module and the user cable)

• Software debugging
• Hardware debugging
o System integration
• System test

• Crystal power accessory (CPA)

Software Debugging

• 40-pin target adaptor
It Clips assembly

The ICE-5100/044 emulator can be operated without being connected to the target system and before
any of the user's hardware is available (provided external data RAM is not needed). In this stand-alone
mode, the ICE-5100/044 emulator can be used to
facilitate program development.

Hardware Debugging
The ICE-51001044 emulator's AC/DC parametric
characteristics match the microcontroller's. The emulator's full-speed operation makes it a valuable tool
for debugging hardware, including time-critical serial
port, timer, and external interrupt interfaces.

System Integration
Integration of software and hardware can begin
when the emulator is plugged into the microcontroller socket of the prototype system hardware. Hardware can be added, modified, and tested immediately. As each section of the user's hardware is completed, it can be added to the prototype. Thus, the
hardware and software can be system tested in realtime operation as each section becomes available.

System Test
When the prototype is complete, it is tested with the
final version of the system software. The ICE5100/044 emulator is then used for real-time emula-

• Software (includes the ICE-5100/044 emulator
software, diagnostic software, and a tutorial)
The controller pod contains 64 KB of emulation
memory, 254- by 24-bit frames of trace memory, and
the control processor. In addition, the controller pod
houses. a BNC connector that can be: used to connect up to 10 multi-ICE compatible emulators for
synchronous starting and stopping of emulation.
The serial cable connects the host system to the
controller pod. The serial cable supports a subset of
the RS-232C signals.
The user probe assembly consists of a user cable
and a processor module. The processor module
houses the emulation processor and the interface
logic. The target adaptor connects to the processor
module and provides an electrical and mechanical
, interface to the target microcontroller socket.
The crystal power accessory (CPA) is a small, detachable board that connects to the controller pod
and enables the ICE-5100/044 emulator to run in
stand-alone mode. The target adaptor plugs into the
socket on the CPA; the CPA then supplies clock and
power to the user probe.
The clips assembly enables the user to trace external events. Eight bits of data are gathered on the
rising edge of PSEN during opcode fetches. The
clips information can be displayed using the CLIPS
option with the PRINT command.

15-67

ICETM·5100/044

280325-2

Figure 1. The ICETM·51001044 Emulator Hardware

_

The ICE-5100-044 emulator software supports mnemonics, object file formats, and symbolic references
generated by Intel's ASM-51 and PL/M-51 programming languages~ Along with the ICE-5100104.4 emulator -software -is a customer confidence test disk
with diagnostic routines that check the operation of
the hardware.

troller of the target system. ElTlulation is a transparent process that happens in real-time. ,The executi_on
of the user software is facilitated with the ICES100/044 command language.
--

The on-line tutorial is written in the ICE-5100 command language. Thus, the user is able to interact
with and use the ICE-51001044 emulator while executing the tutorial.

There is a 64 KB of memory that can be mapped to
the CODE memory space in 4. KB blocks on 4 KB
boundaries. By _mapping -'memory to _the ICE5100/044 emulator, software development.can proceed b~fore the user hardware is available.

A comprehensive set of documentation is provided
with the ICE-51 001044 emulator.

ICETM·5100/044 EMULATOR
FEATURES
The ICE-51 00/044 emulator has been created to assist a product designer in developing, debugging and
testing designs incorporating the RUPI-44 family of
peripherals. -The following sections detail some of
the ICE-51 001044 emulator features.

Memory Mapping

Memory Examination and Modification
The memory space for the 8044 microcontroller and
its target hardware is fully accessible through the
emulator. The ICE-5100/044 emulator refers to four
physically _distinct memory spaces, as follows: • CODE....,..references program memory
• IDATA-"--references internal data memory
• RDATA-references special function' register
, memory
• XDATA-references external data memory

Emulation
Emulation is the controlled execution of the user's
software in the target hardware or in an artificial
hardware environment that duplicates the microcon-

ICE-5100/044 emulator commands that access
memory use one of the special prefixes (e.g., CODE)
to specify the memory space.

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ICETM-5100'044

The microcontroller's special function registers and
register bits can be accessed mnemonically (e.g.,
OPt.:, TCON, CY, P1.2) with, the ICE-51 00/044 emulator software.
Data can be displayed or modified in one of three
bases: hexadecimal, decimal, or binary. Data can
also be displayed or modified in one of two formats:
ASCII or unsigned integer. Program code can be disassembled and displayed as ASM-51 assembler
mnemonics. Code can be modified with standard
ASM-51 statements using the built-in single-line assembler.

Breakpoint Specifications
Breakpoints are used to halt a user program in order
to examine the effect of the program's execution on
the target system. The ICE-51 00/044 emulator supports three different types of break specifications:
• Specific address break-specifying a single address point at which emulation is to be stopped.
• Range break-an arbitrary range of addresses
can be specified to halt emulation. Program execution within or, optionally, outside the range
halts emulation.
• Page break-up to 256 page breaks can be spec~
ified. A page break is defined as a range of addresses that is 256-bytes long and begins on a
256-byte address boundary.

Symbolic references can be used to specify memory ,
locations. A symbolic reference is a procedure
name, line number, program variable, or label in the
user program that corresponds to a location.
Some typical symbolic functions include:
• Changing or inspecting the value of a program
variable by using its symbolic name to access the
memory location.
• Defining break and trace events using symbolic
references.
• Referencing variables as primitive data types.
The primitive data types are ADDRESS, BIT,
BOOLEAN, BYTE, CHAR (character), and
WORD.
The ICE-51 00/044 emulator maintains a virtual symbol table (VST) for program symbols. A maximum of
61 KB of host memory space is available for the
VST. If the VST is larger than 61 KB, the eXCeSS is
stored on available host system disk space and is
paged in and out as needed. The size of the VST is
limited only by the disk capacity of the host system.

Break registers are user-defined debug definitions
used to create and store breakpoint definitions.
Break registers can contain multiple breakpoint definitions and can optionally call debug procedures
when emulation halts.

Trace Specifications
Tracing can be triggered using speCifications similar
to those used for breaking. . Normally, the
ICE-5100/044 emulator traces program activity
while the user program is executing. With a trace
specification, tracing can be triggered to. occur only
when specific conditions are met during execution.
Up to 254 24-bit frames of trace information are collected in a buffer during emulation. Sixteen of the 24
bits trace instruction execution addresses, and 8 bits
capture external events (CLIPS).

*'

'1~

,. Print newest four instructions in the buffer
hlt>PRINT NEWEST 4
FRAME
ADDR
CODE
INSTRUCTIONS
(28)
300A
C02A
PUSH
2AH
(30
300C
2532
ADD
A, 32H
(32)
300E
F52A
MOV
2AH, A
(34)
3010
B53210
CJNE
A,32H, $+10H
hlt>
h1 t > PRINT CLIPS OLDEST 2
Buffer display showing clips
FRAME
ADDR.
CODE
INSTRUCTIONS
CLIPS
(76543210)
(00)
007AH
INC INDX PTR
10101111
0508
(01)
007CH
SJMP (#28)
00100010
80E6

'*

*'

-

Figure 2. Selected Trace Buffer Displays

15-69

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280325-3'

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ICETM·5100/044

The trace buffer display is similar to an ASM-51 program listing as shown in Figure 2. The PRINT command enables the user to selectively display the
contents of the trace buffer. The user has the option
of displaying the clips information as well as dissassembled instructions.

ARM

FOREVER

TIL USING

Procedures
Debugging procedures (PROCs) are a user-defined
group of ICE-51 00/044 commands that are executed as one command. PROCs enable the user to define several commands in a named block structure.
The commands are executed by entering thename
of the PROC. The PROC bodies are a simple DO ...
END construct.

TRACE



~>Gon,"

J



hl t > GO FROM 13H


ARM

FOREVER

TIL USING

TRACE

hl t > GO FROM 13H USING

13H USING brl
TRACE



hl t > GO FROM 13H USING brl TRACE


OUTSIDE

PAGE FROM TIL





hlt>GO FROM 13H USING brl TRACE trace1t

280325-4

Figure 3. The Integrated Command Directory for the GO Command
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ICETM·5100/044

PROCs can simulate missing hardware. or software,
set breakpoints, collect debug information, and execute high-level software patches. PROCs can be
copied to text files on disk, then recalled for use in
later test sessions. PROCs can also serve as program diagnostics, implementing ICE-51 00/044 emulator commands or user-defined definitions for special purposes.

On·Line Syntax Menu
A special syntax menu, called the Integrated Command directory (ICD), similar to the one used for the
121CETM system and the VLSiCE-96 emulator, aids in
creating syntactically correct command lines. Figure
3 shows an example of the ICD and how it changes
to reflect the options available for the GO command.

Help
The HELP command provides ICE-51 00/044 emulation command assistance via the host system terminal. On-line HELP is available for the ICE-5100/044
emulator commands shown in Figure 4.

BITBUSTM Applications Support
The ICE-5100/044 emulator provides an ideal environment for developing applications code for BITBUS board products such as the RCB-44/10, the
RCB-44/20, the PCX-344, and the iSBXTM-344
board.
The BITBUS firmware, available separately as BITWARE, can be loaded into the ICE-51 00/044 emula-

tor's memory along with the user's code to enable
rapid debug of 8044 BITBUS applications code.

DESIGN CONSIDERATIONS
The height of the processor module and the target
adaptor need to be considered for target systems.
Allow at least 1% inches (3.8 cm) of space to fit the
prqcessor module and target adaptor. Figure 5
shows the dimensions of the processor module.
Execution of user programs that contain interrupt
routines causes incorrect data to be stored in the
trace buffer, When an interrupt occurs, the next instruction to be executed is placed into the trace buffer before it is actually executed. Following completion of the interrupt routine, the instruction is executed and again placed into the trace buffer.

ELECTRICAL CONSIDERATIONS
The emulation processor's user-pin timings and
loadings are identical to the 8044 component, except as follows.
• Up to 25 pF of additional pin capacitance is contributed by th~ processor module .and target
adaptor assemblies.
o Pin 31, EA, has approximately 32 pF of additional
capacitance loading due to sensing circuitry.
• Pins 18 and 19, XTAL1 and XTAL2 respectively,
have approximately 15-16 pF of additional capacitance when configured for crystal operation.

It>HELP
HELP is available for:
ADDRESS
BYTE
CURHOME
DISPLAY
EXPRESSION
KEYS
MAP
OPERATOR
REFERENCE
STRING
VERIFY

APPEND
CHAR
CURX
DO
GO
LABEL
MENU
PAGING
REGS
SYMBOLIC
VERSION

ASM
CI
CURY
DYNASCOPE
HELP
LINES
MODIFY
PARTITION
REMOVE
SYNCSTART
WAIT

BASE
CNTL_C
DCI
EDIT
IF
LIST
MODULE
PRINT
REPEAT
TEMP CHECK
WORD

BIT
COMMENTS
DEBUG
ERROR
INCLUDE
LITERALLY
MSPACE
PROC
RESET
TRCREG
WRITE

BOOLEAN
CONSTRUCTS
DEFINE
EVAL
.INVOCATION
LOAD
MTYPE
PSEUDO_VAR
RETURN
TYPES

BRKREG
COUNT
DIR
EXIT
ISTEP
LSTEP
NAMESCOPE
PUT
SAVE
VARIABLE

hlt>

--------n

l l \ - - - - - - - - - -________~~-·

280325-5

Figure 4. HELP Menu
15-71

intJ

ICETM·5100/044

PROCESSOR MODULE~

PIN 1

j

TOP VIEW

~

T
~I~&J
!iis t

H

~~Z
. z

'i

3':J/,."

rem)

i

!

CABLE BODY

I·

~

I

39"

. (99 em)

SIDE VIEW

4"
(10,2 em)

..

PROCESSOR MODULE

~-9;r··
~

TARGET
ADAPTOR

---l
.

280325-6

Figure 5. Processor Module Dimensions

HOST REQUIREMENTS

PHYSICAL CHARACTERISTICS

• IBM PC AT or PC XT (or PC DOS compatible)
with 512 KB of available RAM and a hard disk
running under the DOS 3.0 ( or later) operating
system.
• Intellec Series III/IV microcomputer development
system running the ISIS or iNDX operating system respectively, with at least 512 KB of application memory resident.
• Disk drives-dual floppy or one hard disk and one
floppy drive required.

Controller Pod
Width:
Height:
Depth:
Weight:

8-%"
1-%"
13-%"
41bs

(21
cm)
( 3.8 cm)
(34.3 cm)
( 1.85 kg)

User Cable

ICETM·5100/044 EMULATOR
SOFTWARE PACKAGE

The user cable is 3 feet (approximately 1 m)

• ICE-51 00/044 emulator software

Processor Module

• ICE-51 00/044 confidence tests
• ,ICE-51 00 tutorial software

(With the
Width:
Height:
Depth:

EMULATOR PERFORMANCE

target adaptor
3-1 0/16" (9.7
(10.2
4"
(3.8
1-%"

attached)
cm)
cm)
cm)

Memory
Mappable
full-speed
emulation code
memory

64 KB

.~-,;'

Mappable to user or ICE5100/044 emulator memory in 4 KB blocks on 4 KB
boundaries.

Trace memory

254 x 24 bit frames

Virtual Symbol
Table

A maximum of 61 KB of
host memory space is
available for the virtual
symbol table (VST). The
rest of the VST resides on
disk and is paged in and
out as needed.

Power Supply
Width:
Height:
Depth:
Weight

7-%"
4"
11"
151bs

(18.1 cm)
(10.06 cm)
(27.97 em)
( 6.1 kg)

Serial Cable
The serial cable is 12 feet (3.6 m).

15-72

intJ

ICETM·5100/044

Software Only

ELECTRICAL CHARACTERISTICS

Order Code
SA044D

Power Supply
100-120V or 200-240V (selectable)
50-60 Hz
2 amps (AC max) @ 120V
1 amp (AC max) @ 240V

SA044S

ENVIRONMENTAL
CHARACTERISTICS
Operating temperature
Operating humidity

+ 10°C to + 40°C (50°F to
104°F)
Maximum of 85% relative
humidity, non-condensing

ORDERING INFORMATION

Emulator Hardware and Software
Order Code
1044KITAD

1044KITD

1044KITAS

1044KITS

Description
This kit contains the ICE-51001044
user probe assembly, power supply
and cables, serial cables, target
adaptor, CPA, ICE-5100 controller
pod, software, and documentation for
use with an IBM PC AT or PC XT. The
kit also -includes the 8051 Software
Development Package and the
AEDIT text editor for use on DOS
systems. [Requires software license.]
This kit is the same as the 1044KITAD
excluding the 8051 Software Development Package and the AEDIT text
editor. [Requires software license.]
This kit contains the ICE-51001044
user probe assembly, power supply
and cables, serial cables, target
adaptor, CPA, ICE-5100 controller
pod, software, and documentation-for
use with Intel hosts (Series IIIIIV).
The kit also includes the 8051 Software Development Package and the
AEDIT text editor for use on the Series IIIIIV. [Requires software license.]
,
This kit is the same as the 1044KITAS
excluding the 8051 Software Development Package and the AEDIT text
editor. [Requires software license.]

Description
This kit contains the host, probe, diagnostic, and tutorial software on
5%" disks for use on an IBM PC AT
or PC XT (requires DOS 3.0 or later).
[Requires software license.]
This kit contains the host, probe, diagnostic, and tutorial software on 8"
disks (both single-density and double-density) for use on a Series III,
and on 5-%" disks for use on a Series IV. [Requires software license.]

Other Usefullntel® MCS®-51 Debug and
Development Support Products
Order Code Description
D86ASM51
8051 Software Development Pack·
age (DOS version)-Consists of the
ASM-51 macro assembler which
gives symbolic access to 8051 hardware features; the RL51 linker and
relocator program that links modules
generated by ASM-51; CONV51
which enables software written for
the MCS-48 family to be up-graded to
run on the 8051, and the LlB51 Librarian which programmers can use
to create and maintain libraries of
software object modules. Use with
the DOS operating system (version
3.0 or later).
D86PLM51
PL/M·51 Software Package (DOS
version)-Consists of the PL/M-51
compiler which provides high-level
programming language support; the
LlB51 utility that creates· and
maintains libraries of software object
modules, and the RL51 linker and
relocator program that links modules
generated by ASM-51 and PL/M-51
and locates the linked object modules to absolute memory locations.
Use with the DOS operating system
(version 3.0 or later).
186ASM51
8051 Software Development Pack·
age (ISIS version)-Same as the
D86ASM51 package except this one
is for use with the Series III.
186PLM51
PL/M·51 Sofware Package-Same
as the D86PLM51 package except
this one is for use with the Series III
and Series IV.
D86EDINL
AEDIT text editor for use with the
DOS operating system.

15-73

MCS®-80 /85 Data Sheets

16

I
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intJ
•
•
•
•
•
•

8080A/8080A-1/8080A-2·
8-BIT N-CHANNEL MICROPROCESSOR

6 General Purpose Registers and an
Accumulator

•
•
•
•

Available in EXPRESS
- Standard Temperature Range

16·Bit Program Counter. for Directly
Addressing up to 64K Bytes of Memory

•

Available in 40·Lead Cerdip and Plastic
Packages

TTL Drive Capability·

2JJ,s (-1:1.3JJ,s, -2:1.5JJ,s) Instruction
Cycle
Powerful Problem Solving Instruction
Set

Decimal, Binary, and Double Precision
Arithmetic
Ability to Provide Priority Vectored
Interrupts
512 Directly Addressed I/O Ports

(See Packaging Spec. Order #231369)

16·Bit Stack Pointer and Stack
Manipulation Instructions for Rapid
Switching of the Program Environment

The Intel@ 8080A is a complete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip
using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control
and processing applications.
The 8080A contains 6 8-bit general purpose working registers and an accumulator. The 6 general purpose
registers may be addressed individually or in· pairs. providing Qoth single and double precision operators.
Arithmetip and logical instructions set or reset4 testable flags. A fifth flag provides decimal arithmetic opera.
tion.
The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out
stack to store/retrieve the contents of the accumulator, flags, program counter, and all of the 6 general
purpose registers. The 16-bit stack pointer controls the addressing of this external stack. This stack gives the
8080A the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor
status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and 8-line
bidirectional data busses are used to facilitate easy interface to memory and I/O. Signals to control the
interface to memory and I/O are provided directly by the 8080A. Ultimate control of t~e address and data
busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the
address and data busses into a high impedance state. This permits OR-tying these busses with other controlling devices for (DMA) direct memory access or multi-processor operati.on.

.

NOTE:

The 8080A is functionally and electrically compatible with the Intel 8080.

16-1

November 1986
Order Number: 231453-001

8080AI8080A-1/8080A-2

IIBITI
INTEAt:aAL DATA

ius

..~
:::a:

~

"::!

S

REG.
0
REG.
H

,It

,.,'"

.,

,.,

REG.

L

,.,

STACK POINTER
PROGRAM COUNTER

REGISTER
ARRAV

REG.

""
1111

1111

TIMING
AND

CONTROL

ACK

231453-1

Figure 1. Block Diagram

A,.
GND
D.
'D.
O.
D,
D3
D.
D,O
D.O
-5V
RESET

HOLD
INT
~.

Wii
SYNC
+5V

A11
A,.
An
Au
A,.

At
A. '
A,
10
II
12
13
14
IS
18
17
18
19
20

8OIIOA

32
31

At
As

30

OAo

29
28
27
26

-'3
+1ZV
A.
A,

Au

24
23
22
21

.,

WAIT
READY

HLDA

231453-2

Figure 2. Pin Configuration

16-2

SOSOA/SOSOA-1/S0S0A-2

Table 1. Pin Description
Symbol

Type

A15-AO

0

Name and Function
ADDRESS BUS: The address bus provides the address to memory (up to 64K 8·bit
words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao
is the least significant address bit.

DrDo

I/O

SYNC

0

DBIN

0

DATA BUS IN: The DBIN signal indicates to external circuits that the data bus is in the
input mode. This signal should be used to enable the gating of data onto the 8080A data
bus from memory or 110.

READY

I

READY: The READY signal indicates to the 8080A that valid memory or input data is
available on the 8080A data bus. This signal is used to synchronize the CPU with slower
memory or I/O devices. If after sending an address out the 8080A does not receive a
READY input, the 8080A will enter a WAIT state for as long as the READY line is low.
READY can also be used to single step the CPU.

DATA BUS: The data bus provides bi·directional communication between the CPU,
memory, and 110 devices for instructions and data transfers. Also, during the first clock
cycle of each machine cycle, the 8080A outputs a status word on the data bus that
describes the current machine cycle. Do is the least significant bit.
SYNCHRONIZING SIGNAL: The SYNC pin provides a signal to indicate the beginning
of each machine cycle.

WAIT
WR

0
0

HOLD

I

HOLD: The HOLD signal requests the CPU to enter the HOLD state. The HOLD stato
allows an external device to gain control of the 8080A address and data bus as soon as
the 8080A has completed its use of these busses for the current machine cycle. It is
recognized under the following conditions:
• the CPU is in the HALT state.
• the CPU is in the T2 or TW state and the READY signal is active. As a result of
entering the HOLD state the CPU ADDRESS BUS (A15-AO) and DATA BUS (Dr Do)
will be in their high impedance state. The CPU acknowledges its state with the HOLD
ACKNOWLEDGE (HLDA) pin.

0

HOLD ACKNOWLEDGE: The HLDA signal appears in response to the HOLD signal and
indicates that the data and address bus will go to the high impedance state. The HLDA
.
signal begins a t : ·
• T3 for READ memory or input.
• The Clock Period following T3 for WRITE memory or OUTPUT operation.
In either case, the HLDA signal appears after the rising edge of cfJ2.
INTERRUPT ENABLE: Indicates the content of t.he internal interrupt enable flip/flop.
This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and
inhibits interrupts from being accepted by the CPU when it is·reset. It is automatically
reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M1) when an
interrupt is accepted and is also reset by the RESET signal.

HLDA

INTE

0

INT

I

RESET1

I

Vss
VDO
Vee
VBB
cfJ1, cfJ2

WAIT: The WAIT signal acknowledges that the CPU is in a WAIT state.
WRITE: The WR signal is used for memory WRITE or 110 output control. The data on
the data bus is stable while the WR signal is active low (WR = 0).

INTERRUPT REQUEST: The CPU recognizes an interrupt request on this line at the end
of the current instruction or while halted. If the CPU is in the HOLD state or if the
Interrupt Enable flip/flop is reset it will not honor the request. .
RESET: While the RESET signal is activated, the content of the program counter is
cleared. After RESET, the program will start at location 0 in memory. The,INTE and
HLDA flip/flops are also reset. Note that the flags, accumulator, stack pointer, and
registers are not cleared.
GROUND: Reference.
POWER:. + 12 ±5% V.
POWER: +5 ±5% V.
POWER: -5 ±5% V.
CLOCK PHASES: 2 externally supplied clock phases. (non TTL compatible)

NOTE:
1. The RESET signal must be active for a minimum of 3 clock cycles.

16-3

8080A/8080A-1/8080A-2

• Notice: Stresses abo.ve those listed under "Absolute Maximum Ratings" may cause permanent dam~
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

, ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............ O·C to + 70·C
Storage Temperature ,.......... - 65·C to + 150·C
All Input or Output Voltages
with Respect to Vss ........... - 0.3V to + 20V
Vcc, VDD and Vss
with Respect to Vss ...• '..••..• - 0.3V to + 20V
Power Dissipation .....•.................... 1.5W

D.C. CHARACTERISTICS
TA = O·C to 70·C, VDD =
noted

Symbol

+ 12V ±5%, Vcc =

Parameter

+5V ±5%, Vss = -5V ±5%, Vss = OV; unless otherwise

Typ

Min

Max

Unit

Vss + 0.8

V

VllC

Clock Input Low Voltage

Vss - 1

VIHC

Clock Input High Voltage

9.0

Vil

Input Low Voltage

Vss - 1

Vss + 0.8

V

VIH

Input High Voltage

3.3

Vce +1

V

Val

Output Low Voltage

0.45

V

VOH

Output High Voltage '

VDD

+1

3.7

Test Condition

V

} IOl = 1.9 rnA on All Outputs,
IOH = -150/LA.

V

IDD(AV) Avg. Power Supply Current (VDD)

40

70

rnA

ICC (AV) Avg. Power Supply Current (Vce>

60

80

rnA

IsS (AV) Avg. Power Supply Current (Vss)

0.01

1

rnA

) Ope-"

Tcy =0.48/Ls

:s: VIN :s: Vcc
:s: VClOCK :s: VDD
Vss:S: VIN :s: Vss + 0.8V
Vss + 0.8V :s: VIN :s: VCC

III

Input Leakage

±10

/LA

Vss

ICl

Clock Leakage

±10

/LA

Vss

IDl

Data Bus Leakag'e'in Input Mode

-100
--'2.0

/LA
rnA

IFl

Address and Data Bus Leakage
During HOLD

+10
-100

/LA

CAPACITANCE

1,5 r-----r-----,---......,

TA = 25°C, Vcc = VDD = Vss = OV,Vss = -5V

Symbol

Parameter

Typ

Max

Unit

Cq,

Clock
Capacitance

17

25

pF

fc= 1 MHz

CIN

Input
Capacitance

6

10

pF

Unmeasured Pins

COUT

Output
Capacitance

10

20

pF

Returned to Vss

Test Condition

VADDR/DATA = VCC
VADDR/DATA = Vss + 0.45V

~

a:
a:

~ 1.01---=""'".,.....=--+----j

i
O.50~-----:.=25---:'.50:---~.,5
AMBIENT TEMPERATURE lOCI

231453-3

Typical Supply Current vs
Temperature. Normalized
Dol Supply/DoTA = -O.45%rC

16-4

8080A/8080A-1/8080A-2

A.C. CHARACTERISTICS (8080A), TA = 0·Ct070·C, voo
= -5V ± 5%, VSS = OV; unless otherwise noted

= +12V ±5%, vee = +5V ±5%,

VBB

Symbol

-1

Parameter

-1

-2 -2 Unit Test Condition

Min Max Min Max Min Max

tey(3)

Clock Period

tr, tf

Clock Rise and Fall Time

0

1 Pulse Width

60

50

60

ns

d>2 Pulse Width

220

145

175

ns
ns

t1
td>2

I

I

0.48 2.0 0.32 2.0 0.38 2.0
50

0

25

0

t01

Delay <1>1 to <1>2

0

0

0

t02

70

60

70

t03

Delay <1>1 to <1>2
Delay <1>1 to <1>2 Leading Edges

80

60

70

50

/Ls

ns

ns
ns

tOA

Address Output Delay From <1>2

200

150

175

ns

too

Data Output Delay From <1>2

200

180

200

ns

toe

Signal Output Delay From <1>1 or <1>2
(SYNC, WR, WAIT, HLDA)

120

110

120

ns

tOF
tOI(1)

DBIN Delay From <1>2

tOS1

Data Setup Time During <1>1 and DBIN

30

10

20

ns

tOS2
tOH(1)

Data Setup Time to <1>2 During DBIN

150

120

130

ns

Data Hold Time From <1>2 and DBIN

(1)

(1)

(1)

tiE

INTE Output Delay From <1>2

tRS

READY Setup Time During <1>2

120

90

90

ns

25

Delay for Input Bus to Enter Input Mode

140

25

tOF

130

25

tOF

200

ns

ns
200

ns

tHS

HOLD Setup Time During <1>2

140

120

120

ns

tiS

INT Setup Time During <1>2

120

100

100

ns

tH

Hold Time From <1>2 (READY, INT, HOLD)

0

0

0

ns

tFO

Delay to Float During Hold
(Address and Data Bus)

120

120

120

ns

tAW

Address Stable Prior to WR

(5)

(5)

(5)

ns

tow

Output Data Stable Prior to WR

(6)

(6)

(6)

ns

two

Output Data Stable From WR

(7)

(7)

(7)

ns

tWA

Address Stable From WR

(7)

(7)

(7)

ns

tHF

HLDA to Float Delay

(8)

(8)

(8)

ns

tWF

WR to Float Delay

(9)

(9)

(9)

ns

tAH

Address Hold Time After DBIN During HLDA -20

-20

-20

ns

A.C. TESTING LOAD CIRCUIT

DEVICE
UNDER
TEST

'1CL~100PF
-=

CL = 100 pF
CL Includes Jig Capacitance

16-5

231453-4

CL = 50 pF

140 ns
tOF

200

CL = 100 pF

CL = 50 pF

.,
.2

- ~t~'

.

tey

~

~I

"-f

-too-I

° ,°

--

L _____

0
~

T

SYNC

-DBIN

to~l--

-1 --

~

-

tOi

1-

en

m

WR

~

:,1= ~

oJ

to

------ ---

-4

---- - ---

-f

-lOW

_ 1052 -

ATA OUT

-

I»
Q

I»

tDel-

i:.....

l.

11

I»

---'OF-!

Q

----------,L tH -

READY

l

I--t oo-

toHI""'-

~

--·t:-~
---:::..

-- t-,.....-tAW

g~TA IN

I--toF~1

.....

."

oJ3
s::
en

t02 - -

I--toA--:r - - ~--

I~

~

io---

~

---I

A'S-AO

7

it'-

f\

-I
-.t03 _

~

<
m

-X@

------------

-

WAIT

t R5

f.-tH-

..t oc- -

HOLD

71

I»

[.
toe 1---1

Q

~
....
co

J-:--

~~~--:I

Q

~

~

-

- ...X@
tH

--0

N

J--X

~r;;.; Q-

HLDA

- ..............

rf

X~ '-4

INT

tlSJ:-:

'H_
~

...
~

INTE

231453-5

NOTE:
Timing measurements are made at the following reference voltages: CLOCK "1"
"0" = o.av

=

a.ov, "0"

= 1.0V; INPUTS "1" =

a.av, "0"

=

o.av; OUTPUTS "1"

= 2.0V,

8080A/8080A-1/8080A-2

Typlcalll Output Delay vs Il Capacitance

WAVEFORMS (Continued)

~,

,J\

~2

~

f\

I-J
I-

.

.°7·°0

>

-

W

WAf-

I--

toe

.. tAH

~

I

-- ~'wF-

READY
I - tHf-

WAIT

I-

- to'

HLDA

_X-

~

I

~

o

1--.

--:'1

INTE

~
.~

'1

tWA

DBIN

INT

w

Q

+100
~

- I-

SYNC

HOLD

:5

~
--- ---~-'FD I--

-I-_.Y -- --.- -- ....
--t-1'wD
Y

I-~--

A,s·Ao

!

~:~231453-6

NOTES:
(Parenthesis gives -1, - 2 specifications, respectively.)
1. Data input should be enabled withDBIN status.
No bus conflict can then occur and data hold time
is assured.
tOH = SO ns or tOF, whichever is less.
2. lev = t03 + tr<1>2 + t2 + tf2 + t02 + trl ~
480 ns (-1 :320 ns, - 2:380 ns).

CAPACITANCE (pI)

(CACTUAL - CSPEC )

231453-7

3. The following are relevant when interfacing the
8080A to devices having VIH = 3.3V:
a) Maximum output rise time from 0.8V to 3.3V =
100 ns @ CL = SPEC.
b) Output delay when measured to 3.0V = SPEC
+60 ns @ CL = SPEC.
c) If CL = SPEC, add 0.6 ns/pF if CL > CSPEC,
subtract 0.3 ns/pF (from modified delay) if CL <
CSPEC·
4. tAW = 2tcv - t03 - trcf>2 - 140 ns (-1:110
ns, - 2:130 ns).
S. tow = tcv - .t03 '- tr2 - 170 ns (-1:1S0 ns,
- 2:170 ns).
.6. If not HLDA, two = tWA = t03 + tr2 + 10 ns.
If HLDA, two = tWA = tWF·
7. tHF = t03 + trcf>2 -SO ns.
8. tWF = toa + tr2 - 10 ns.
9. Data in must be stable for this period during
DBIN T 3. Both tOSl and tOS2 must be satisfied.
10. Ready signal must be stable for this period during T 2 or TW. (Must be. externally synchronized.)
11. Hold signal must be stable for this period during
T 2 or TW when entering hold mode, and during T 3,
T4, T 5 and TWH when in hold mode. (External synchronization is not required.)
12. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order
to be recognized on the following instruction. (External synchronization is not required.)
13. This timing diagram shows timing relationships
only; it does not represent any specific machine cycle.

16-7

inter

8080A/8080A-1/8080A-2

8080A. The ability to increment and decrement
memory,the six general registers and the accumulator is provided as well as extended increment and
decrement instructions to operate on. the register
pairs and stack pointer. Further capability is provided by the ability to rotate the accumulator left or right
through or around the, carry bit.

INSTRUCTION, SET '
The accumulator group instructions include arithmetic and logical operators with direct, indirect, and immediate addressing modes.
Move, load, and store instruction groups provide the
ability to move either 8 or 16 bits of data between
memory, the six working registers and the accumulator using direct, indirect, and immediate addressing
modes.

Input and output may be accomplished using memory' addresses as I/O -ports or the directly addressed
I/O provided for in the 8080A instruction set. , '
The following special instruction gro!-,p completes
the 8080A instruction set: the NOP instruction"
HALT to stop processor execution and the OAA instructions provide decimal arithmetic capability. STC
allows the carry flag to be directly set, and the CMC,
instruction allows it to be complemented. CMA complements the contents of the, accumulator and
XCHG exchanges the contents of two 16-bit register
pairs directly.

The ability to branch to different portions of the program is provided with jump, jump conditional, and
computed jumps. Also the ability to call to and return
from subroutines is provided both conditionally and
unconditionally. The RESTART (or single byte call
instruction) is useful for interrupt vector operation.
Double preCision operators such as stack manipulation and double add instructions extend both the
arithmetic and Interrupt 'handling capability of the

Data and Instruction Formats
Oata·in the8080A is stored in the form Df8-bit binary integers. All data transfers to they system data bus will
be in the same format.
' .
rl0-7-'-06-0-5-0
-'-40-3-0-20-'0I
0 1DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored in
:~~cessive words in program memory.. The instruction formats then depend on the particular operation executOne Byte Instructions
107 D6 05 04 03 D2

~1

. '
Do

TYPICAL INSTRUCTIONS

I

OP CODE

Register to register, memory reference,
arithmetic or logical, rotate, return, push,
pop, enable or disable Interrupt
instructions

Two Byte Instructions
107 06 05 D4 03 02 01 Dol

OPCODE

107 D6 05 04 03 02 0 1' Dol

OPERAND

Immediate mode or I/O instructions

Three Byte Instructions
Jump, call or direct load and store
'
'
,
instructions

107 06 D5 04 03 02 01 Dol

OPCOOE

107 06 D5 D4 03 02 D1 Dol

LOW ADDRESS OR OPERAND 1

10 7 06 D5 04 D3 02 01 Dol

HIGH ADDRESS OR OPERAND 2

For the 8080A a logiC "1" is defined as a high level and a logiC "0" is defined as a low level.

16-8

inter

8080A/8080A-1/8080A-2
Table 2. Instruction Set Summary

~nemonlc'

Instruction Code (1)
D7D6DsD4D3D2D1Do

Operations
Description

Clock
Cycles
(2)

~nemonlc'

MOVE, LOAD, AND STORE
MOVr1,r2
MOVM,r
MOVr,M
MVlr
MVIM
LXIB
LXID
LXIH
STAXB
STAXD
LDAXB
LDAXD
STA
LDA
SHLD
LHLD
XCHG

a

1 D D D S S S Move register to
register
a 1 1 1 a S S S Move register to
memory
a 1 D D D 1 1 a Move memory to
register
a a D D D 1 1 a Move immediate
register
a a 1 1 a 1 1 a Move immediate
memory
a a a a a a a 1 Load immediate
register Pair B & C
a a a 1 0 0 a 1 Load immediate
register Pair D & E
a a 1 a a a a 1 Load immediate
register Pair H & L
a a a a a a 1 a Store A indirect
a a a 1 a a 1 a Store A indirect
a a a a 1 a 1 a Load A indirect
a a a 1 1 a 1 a Load A indirect
a a 1 1 a a 1 a Store A direct
0 0 1 1 1 a 1 b Load A direct
a a 1 a a a 1 a Store H & L direct·
a a 1 a 1 a 1 a Load H & L direct
1 1 1 a 1 a 1 1 Exchange D & E,
H & L Registers

5
7

Instruction Code (1)
D7 D6 Ds D4 D3 D2 D1 Do

JM
JPE

1 1 1 1 1 0 1
1 1 1 a 1 a 1

JPO
PCHL

1 1 1
1 1 1

1 1

a a a

1

a

PUSHD

1 1

a

a

1

a

PUSHH

1 1 1

a a

1

a

PUSH
PSW
POPB

1 1 1 1 0 1

a

1 1

a a a a a

POPD

1 1

a

1

a a a

POPH

1 1 1 0

a a a

POPPSW

1 1 1 1

a a a

XTHL

1 1 1

SPHL

1 1 1 1 1

1

a a a

1

a

0

LXISP

0 0 1 1 0 0

a

INXSP

0 0 1 1

DCXSP

0 0 1 1 1

even
1 a Jump on parity odd
0 1 H & L to program
counter

10
10
10

5

CALL.
7

CALL
CC
CNC
CZ
CNZ
CP
CM
CPE
'CPO

10
10
10
10

7

1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
1

0'0 1 1 a 1 Call unconditional
0 1 1 1 a a Call on 9arry
0 1 0 1 a o Call on no carrY
a a 1 1 a o Call on zero
a a a 1 a o Call on no zero
1 1 0 1 0 o Call on positive
1 1 1 1 0 a Call on minus
1 a 1 1 a a Call on parity even
1 a a 1 a o Call on parity odd

11/17
11/17
11/17
11/17
11/17
11/17
11/17
11/17

a
a
a
a
a a a a
1 1 a a
1 1 1 a
1 0 0 a

a o Return on carry
0 o Return on no carry
a a Return on zero
a a Return on no zero
a a Return on positive
a a Return on minus
a a Return on parity

10
5111
5/11
5/11
5/11
5/11
5/11
5/11

a a

a Return on parity

17

RETURN

7
7

7
13
13
16
16

4

a

0 1

a

1

1 Push register Pair
B &Constack
1 Push register Pair
D& E on stack
1 Push register Pair
H& Lon stack
1 Push A and Flags
on stack
1 Pop register Pair B
& C 011 stack
1 Pop register Pair D
& E 011 stack
1 Pop register Pair H
& L 011 stack
1 Pop A and Flags
011 stack
1 Exchange top of
stack, H & L
1 H & Ltostack
pointer
1 Load immediate
stack pointer
1 Increment stack
pointer
1 Decrement stack
pOinter

11

1
1
1
1
1
1

a a

1
0 1 1
a 1 0
a a 1

RET
RC
RNC
RZ
RNZ
RP
RM
RPE

1
1
1
1
1
1
1 1
1 1

RPO

1 1 1

0 1 Return

a

0 0

a

1 1 Jump
unconditional
Jump on carry
1 1 a 1 1 a 1
1 1 0 1 a a 1 o Jump on no carry
1 1 '0 0 1 0 1 o Jump on zero
1 1 a 0 a a 1 a Jump on no zero
Jump on positive
1 1 1 1 a a 1

o

o

0 0

5/11

odd
RESTART

11

RST
11

1 1 A A A 1 1 1 Restart

11

INCREMENT AND DECREMENT

11
10
10
10
10
18

5

a a
a a
a 0

INXD

0 0 0 1 0 0 1 1

INXH

a

DCXB
DCXD
DCXH

a

D
D
1
0 0 1
0 0 0

0 1

D D
DD
1 0
1 a
0 0

a

0 0 1 1

0 a a 1 0 1 1
0 0 0 1 1 a 1 1
a 0 1 a 1 0 1 1

ADD

5

ADDr
ADCr

1 0 0
1 0 a

a a
a 1

ADDM
ADCM

1 a a
1 0 0

a a
a 1

ADI
ACI

1 1 0
1 1 0

a a
a 1

DADB
DADD
DADH
DADSP

0 a 0 a
a a a 1
a 0 1 a
a 0 1 1

5

10
10
10
10
10
10

16-9

1 a a
1 a 1
1 a o
1 0 1
0 1 1

INRr
DCRr
INRM
DCRM
INXB

10

JUMP

JC
JNC
JZ
JNZ
JP

a
a

a Jump on minus
a Jump on parity

Clock
Cycle!
(2)

even

PUSHB

1 1

0
1

7.

STACKOPS

JMP

a
a

Operations
Description

1
1
1
1

Increment register
Decrement register
Increment memory
Decrement memory
Increment B & C
registers
Increment D & E
registers
Increment H & L
registers
Decrement B & C
Decrement D & E
Decrement H & L

S S S Add register to A
S S S Add register to A
with carry
1 1 a Add memory to A
1 1 o Add memory to A
with carry
1 1 a Add immediate to A
1 1 o Add immediate to A
with carry
a a 1 AddB&CtoH&L
a a 1 AddD&EtoH&L
a a 1 AddH&LtoH&L
0 0 1 Add stack pointer
toH&L

5

5
10
10

5
5

5
5
5
5
4
4
7
7
7
7
10
10
10
10

8080A/8080A-1/8080A-2

Table 2 Instruction Set Summary (Continued)
Mnemonic·

Instruction Code (1)
o,.DsDsD4D3D2Dl D

Operations
Description

Clock
Cyclel
(2)

~nemonlc·

SUBTRACT
SUBr

Operations
Description

Clock
Cycle!
(2)

ROTATE

1 0 0 1 0 S S S Subtract register

SBBr

l' 0 0 1 1 S S

SUBM

1 0 0 1 0 1 1

SBBM

1 0 0 1 1 1 1

SUI

1 1 0 1 0 1 1

SBI

1 1 0 1 1 1 1

from A
S Subtract register
from A with borrow
o Subtract memory
from A
o Subtract memory
from A with borrow
o Subtract
immediate from A
o Subtract
immediate from A
with borrow

4
4

RLC
RRC
RAL

0 0 0 0 0 1 1 1 Rotate A left
0 0 0 0 1 1 1 1 Rotate A right
0 0 0 1 0 1 1 1 Rotate A left

7

RAR

0 0 0 1 1 1 1 1 Rotate A right

4
4
4

through carry

4

through carry

7

SPECIALS

7

CMA
STC
CMC

7

OM

0
0
0
0

0
0
0
0

1
1
1
1

0
1
1
0

1
0
1
0

1
1
1
1

1
1
1
1

1
1
1
1

Complement A
Set carry
Complement carry
Decimal adjust A

4
4
~

4

INPUTIOUTPUT

LOGICAL
ANAr

Instruction Code (1)
D7DsDsD4D3D2D1D

1 0 1 0 0 S S S And register

XRAr

1 0 1 0 1 S S

ORAr
CMPr

1 0 1 1 0 S S
1 0 1 1 1 S S

ANAM

1 0 1 0 0 1 1

XRAM

1 0 1 0 1 1 1

ORAM
CMPM

1 0 ·1 1 0 1 1
1 0 1 1 1 1 1

ANI

1 1 1 0 0 1 1

XRI

1 1 1 0 1 1 1

ORI

1 1 1 1 0 1 1

CPI

1 1 1 1 1 1 1

with A
S Exclusive or
register with A
S Or register with A
S Compare register
with A
o And memory
with A
o Exclusive Or
memory with A
o Or memory with A
o Compare memory
with A
.0 And immediate
with A
o Exclusive Or
immediate with A
o Or immediate
with A
o Compare
immediate with A

4

IN
OUT

4

CONTROL

4
4

EI
01
NOP
HLT

7

1 1 0 1 1 0 1 1 Input
1 1 0 1 0 0 1 1 Output
1
1
0
0

1
1
0
1

1
1
0
1

1
1
0
1

1
0
0
0

0
0
0
1

1 1 Enable Interrupts
1 1 Disable Interrupt
0 o No-operation
1 o Halt

7
7
7
7
7
7
7

NOTES:
1. DDD or SSS: B = 000, C = 001, D = 010, E = 011, H = 100, L = 101, Memory = 110, A = 111.
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags.
'AII mnemonics copyright @ Intel Corporation 1977

16-10

10
10
4
4

4
7

8085AH/8085AH-2/8085AH-1
8-BIT HMOS MICROPROCESSORS
System Controller; Advanced
• On-Chip
Cycle Status Information Available for
Large. System Control.
Four Vectored Interrupt Inputs (One Is
• Non-Maskable) Plus an SOSOACompatible Interrupt
Serial In/Serial Out Port
• Decimal, Binary and Double Precision
• Arithmetic
Addressing Capability to 64K
• Direct
Bytes of Memory
in 40-Lead Cerdip and Plastic
• Available
Packages

+ SV
Supply with 10%
• Single
Voltage Margins
3 MHz, S MHz and 6 MHz Selections
•. Available
20% Lower Power Consumption than
• SOSSA
for 3 MHz and S MHz
1.3 p.s Instruction Cycle (SOSSAH); O.S
• p.s (80SSAH-2); 0.67 p.s (80SSAH-1)
100% Software Compatible with S080A
• On-Chip
Generator (with External.
• Crystal, LCClock
or RC Network)
Pow~r

(See Packaging Spec., Order # 231369)

The Intel 8085AH is a complete 8-bit parallel Central Processing Unit (CPU) implemented in N-channel,
depletion load, silicon gate technology (HMOS). Its instruction set is 100% software compatible with the
8080A microprocessor, and it is designed to improve the present 8080A's performance. by higher system
speed. Its high level of system integration allows a minimum system of three IC's [8085AH (CPU),8156H
(RAMIIO) and 8755A (EPROM/IO)] while maintaining total system expandability. The 8085AH-2 and
8085AH-1 are faster versions of the 80B5AH.
The 8085AH incorporates all of the features that the 8224 (clock generator) and 8228 (system controller)
provided for the 8080A, thereby offering a higher level of system integration.
.
The 8085AH uses a multiplexed data bus. The address is split between the 8-bit address bus and the 8-bit
data bus. The on-chip address latches of 8155H/8156H/8755A memory products allow a direct interface with
the 8085AH.

liifA

Xl
X2
RESET OUT

I

,..

C

'1(0
D
REG.

III

REG
II,

I.

'"

l

,"

flEO

Kill

REG.

MG.

}-.
ARRAY

STACI(POINTEA

fill

PROGRAM COUNTER

1111

INCAEM1NTEA/DECREMlNTEA
ADDR($SLATCIl

"I!

x,

x,

SIO
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR

iNfA
ADO
AOl
AD2
ADJ
AD4
AD5
AD6
AD7
Vss

Vee

HOLD
HLDA
eLK lOUT!
RESET IN
REAOV
101M
S1

iii5
iVA
ALE
So
Al5
Al4
All
Al2
All
AlO
Ag
AS

231718-2
AII-At

ADDItEII8US

ADJ-ADo

AODAlSIIDAT A aus

231.718-1

Figure 1. 8085AH CPU Functional Block Diagram

16-11

Figure 2. 8085AH Pin
Configuration

September 1987
Order Number: 231718-001

intJ

8085AH/8085AH-2/8085AH-1

Table 1_ Pin Description
Symbol

Type
Name and Function
ADDRESS BUS: The most significant 8 bits of memory address or the 8 bits of the
0
Aa-A15
1/0 address, 3~stated during Hold and Halt modes and during RESET.
1/0 MULTIPLEXED ADDRESSIDATA BUS: Lower 8 bits of the memory address (or
ADo-7
1/0 address) appear on the bus during the first clock cycle (T state) of a machine
cycle. It then becomes the data bus during the second and third clock cycles.
ALE
0
ADDRESS LATCH ENABLE: It occurs during the first clock state of a machine
cycle and enables the address to get latched into the on-chip latch of peripherals.
The falling edge of ALE is set to guarantee setup and hold times for the address
information. The falling edge of ALE can also be used to strobe the status
information. ALE is never 3-stated.
So, S1 and 101M
0
MACHINE CYCLE STATUS:

RD

0

WR

0

READY

I

HOLD

I

HLDA

0

INTR

I

101M 51 50 Status
0
0 1 Memory write
1 0 Memory read
0
1
0 1 1/0 write
1
1 0 1/0 read
1 1 Opcode fetch
0
·1
1
1 Interrupt Acknowledge
• 0 0 Halt
• X X Hold
• X X Reset
• = 3-state (high impedance)
X = unspecified
51 can be used as an advanced R/W status. 101M, SO and S1 become valid at the
beginning of a machine cycle and remain stable throughout the cycle. The falling
edge of ALE may be used to latch the state of these lines.
.
READ CONTROL: A low level on RD indicates the selected memory or 1/0 device
is to be read and that the Data Bus is available for the data transfer, 3-stated during
Hold and Halt modes and during RESET.
WROTE CONTROL: A low level on WR indicates the data on the Data Bus is to be
written into the selected memory or 1/0 location. Data is set up at the trailing edge
of WR. 3-stated during Hold and Halt modes and during RESET.
READY: If READY is high during a read or write CyCh3, it indicates that the memory
or peripheral is ready to send or receive data. If READY is low, the CPU will wait an
integral number of clock cycles for READY to go high before completing the read
or write cycle. READY must conform to specified setup and hold times;
HOLD: Indicates that another master is requesting the use of the address and data
buses. The CPU, upon receiving the hold request, will relinquish the use of the bus
as soon as the completion of the current bus transfer. Internal processing can
continue. The processor can regain the bus only after the HOLD is removed. When
the HOLD is acknowledged~ the Address, Data RD, WR, and 101M lines are
3-stated.
HOLD ACKNOWLEDGE: Indicates that the CPU has received the HOLD request
and that it will relinquish the bus in the next clock cycle. HILDA goes low after the
Hold request is removed. The CPU takes the bus one half clock cycle after HLDA
goes low.
INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled only
during the next to the last clock cycle of an instruction and during Hold and Halt
states. If it is actiVe, the Program Counter (PC) will be inhibited from incrementing
and an INTA will be issued. During this cycle a RESTART or CALL instruction can
be inserted to jump to the interrupt service routine. The INTR is enabled and
disabled by software. It is disabled by Reset and immediately after an interrupt is
accepted.
16-12

intJ

SOS5AH/SOS5AH-2/S0S5AH-1

Table 1. Pin Description (Continued)
Symbol

Type

Name and Function

INTA

0

INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as)
RD during the Instruction cycle after an INTR is accepted. It can be used to
activate an 8259A Interrupt chip or some other interrupt port.

RST5.5
RST6.5
RST7.5

I

RESTART INTERRUPTS: These three inputs have the same timing as INTR
except they cause an internal RESTART to be automatically inserted.
The priority of these interrupt is ordered as shown in Table 2. These interrupts have
a higher priority than INTR. In addition, they may be individually masked out using
the SIM instruction.

TRAP

I

TRAP: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the
same time as INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt
Enable. It has the highest priority of any interrupt. (See Table 2.)

RESET IN

I

RESET IN: Sets the Program Counter to zero and resets the Interrupt Enable and
HlDA flip-flops. The data and address buses and the control lines are 3-stated
during RESET and because of the asynchronous nature of RESET, the processor's
internal registers and flags may be altered by RESET with unpredictable results.
RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for
power-on RESET delay (see Figure 3). Upon power-up, RESET IN must remain low
for at least 10 ms after minimum Vee has been reached. For proper reset
operation after the power-up duration, flESET IN should be ~ept Iowa minimum of
three clock periods. The CPU is held in the reset condition as long as RESET IN is
applied.

RESET OUT

0

RESET OUT: Reset Out indicates CPU is being reset. Can be used as a system
reset. The signal is synchronized to the processor clock and lasts an integral
number of clock periods.

X1,X2

I

X1 and X2: Are connected to a crystal, lC, or RC network to drive the internal
clock generator. X1 can also be an external clock input from a logic gate. The input
frequency is divided by 2 to give the processor's internal operating frequency.

ClK

0

CLOCK: Clock output for use as a system clock. The period of ClK is twice the X1,
X2 input period.

SID

I

SERIAL INPUT DATA LINE: The data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.

SOD

0

SERIAL OUTPUT DATA LINE: The output SOD is set or reset as specified by the
SIM instruction.
POWER:· + 5 volt supply.

Vee
Vss

GROUND: Reference.
.

Table 2. Interrupt Priority, Restart Address and Sensitivity
Priority

Address Branched to(1)
When Interrupt Occurs

Type Trigger

1

24H

Rising Edge AND High level until Sampled

RST7.5

2

3CH

Rising Edge (latched)

RST6.5

3

34H

High level until Sampled

Name
TRAP

RST5.5

4

2CH

High level until Sampled

INTR

5

(Note 2)

High level until Sampled

NOTES:
1. The processor pushes the pe on the stack before branching to the indicated address.
2. The address branched to depends on the instruction provided to the CPU when. the interrupt is acknowledged.

16-13

inter

8085AH/8085AH-2/8085AH-1

(SID) and Serial Output Data (SOD) lines for simple
serial interface.

RESET IN

:

' c,

R,

Vee 0

I

f

In addition to these features, the 8085AH has three
maskable, vector interrupt pins, one nonmaskable
TRAP interrupt, and a bus vectored interrupt, INTR.

I~

INTERRUPT AND SERIAL I/O

231718-3
Typical Power-On Reset RC Values'
RI = 75 KO
CI = 1 "F
'Values May Have to Vary Due to Applied Power Supply Ramp
UpTime.

The 8085AH has 5 interrupt inputs: INTR, RST 5.5,
RST 6.5, RST 7.5, and TRAP. INTR is identical in
function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but it is
nonmaskable.

Figure 3. Power-On Reset Circuit

The three maskable interrupt cause the internal execution of RESTART (saving the program counter in
the stack 'and branching to the RESTART address) if
the interrupts are enabled and if the interrupt mask
is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector independent of
the state of the interrupt enable or masks. (See Table 2.)

FUNCTIONAL DESCRIPTION
The 8085AH is a complete 8-bit parallel central
processor. It is designed with N-channel, depletion
load, silicon gate technology (HMOS), and requires
a singie + 5V supply: Its basic clock speed is 3 MHz
(8085AH), 5 MHz (8085AH~2), or 6 MHz (8085-AH- t),
thus improving on the present 8080A's performance
with higher system speed. Also it is designed to fit
into a minimum system of three IC's:, The CPU
(8085AH), a RAM/10(8156H), and an EPROM/IO
chip (8755A).
'

, There are two different types of inputs in the restart
interrupts. RST 5.5 and RST 6.5 are high level-sensitive like INTR (and INT on the 8080) and are recognized with the same tiining ,as INTR. RST 7.5 is rising

edge-sensitive.

The 8085AH has twelve addressable 8-bit registers.
Four of them can function only as two 16-bit register
pairs. Six others can be used' interchangeably as
8-bit registers or as 16-bit register, pairs. The
8085AH register, set is as follows:
Mnemonic
Register
Contents
ACC or A, Accumulator
8 Bits
PC
Program Counter 16-Bit Address
BC, DE, HL General-Purpose 8-Bits x 6 or
16'Bitsx3
Registers; data
pointer (HL)
Stack Pointer
'16-Bit Address
SP
Flags or F Flag Register
5 Flags (8-Bit Space)

For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt request (a normally high level signal with a low going
pulse is recommended for,highest system noise immunity). The RST 7.5 request flip-flop remains set
until the request is serviced. Then it is reset automatically. This flip~flop may also be reset by using
theSIM instrUction or by issuing a RESET IN to the
8085AH. The RST 7.5 internal flip-flop will be set by
a pulse on the RST 7.5 pin even when the RST 7.5
interrupt is masked out.
'

The 8085AH uses a multiplexed Data Bus. The address is split between the higher 8-bit Address Bus
and the lower 8-bit Address/Data Bus. During the
first T state (clock cycle) of a machine cycle the low
order address is sent out on the AddresS/Data bus.
These lower 8 bits may be latched exterrially by the
Address Latch Enable Signal (ALE). During the rest
of the machine cycle the data bus is used for memory or I/O data.
The 8085AH provides RD, WR, So, Sl, and 10/M
Signals for' bus control. An Interrupt Acknowledge
signal (INTA) is also provided. HOLD and all Interrupts are synchronized with the processor's internal
clock. The 8085AH also provides Serial Input Data

The status of the ,three, RST interrupt' masks can
only be affected by the SIM instruction and
RESET IN. (See SIM, Chapter 5 of the 8080/8085
User's Manual.)
The interrupts are arranged' in a fixed priority that
determines which interrupt is to be recognized if
more than one is pending as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST 5;5, INTR-Iowest priority. This priority scheme does not take into
account the priority of a routine that was started by a
higher priority interrupt. RST 5.5 can interrupt an
RST 7.5 routine if the interrupts are re-enabled before the end of the RST 7.5 routine.
The TRAP interrupt is useful for catastrophic 'events
such as power failure or bus, error. The TRAP input is
recognized just as any other interrupt but has the

16-14

intJ

8085AH/8085AH-2/8085AH-1

highest priority. It is not affected by any flag or mask.
The TRAP input is both edge and level sensitive.
The TRAP input must go high and remain high until it
is acknowledged. It will not be recognized again until
it goes low, then high again. This avoids any false
triggering due to noise or logic glitches. Figure 4 illustrates the TRAP interrupt request circuitry within
the 8085AH. Note that the servicing of any interrupt
(TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) disables
all future interrupts (except TRAPs) until an EI instruction is executed.

EXTERNAL

INSIDE THE
8085AH

REOUEST

SCHMITT

TRIGGER

+5V

0

Parallel resonance at twice the'clock frequency desired
CL (load capacitance) s 30 pF
Cs (Shunt capacitance)s 7 pF
Rs (equivalent shunt resistance) s 75!l
Drive level: 10 mW
Frequency tolerance: ± 0.005% (suggested)
Note the use of the 20 pF capacitor between X2 and
ground. This capacitor is required with crystal frequencies belpw 4 MHz to assure oscillator startup at
the correct frequency. A parallel-resonant LC citcuit
may be used as the frequency-determining network
for the 8085AH, providing that its frequency tolerance of approximately ± 10% is acceptable. The
components are chosen from the formula:

TRAP
INTERRUPT

RESET I':;;

hence, the 8085AH is operated with a 6 MHz crystal
(for 3 MHz clock), the 8085AH-2 operated with a 10
MHz crystal (for 5 MHz clock), and the 8085AH-1
can be operated with a 12 MHz crystal (for 6 MHz
clock). If a crystal is used, it must have the following
characteristics:

elK

D
FIF

INTERNAL

To minimize variations in frequency, it is recommended that you choose a value for Cext that is at
least twice that o,f Cjnt, or 30 pF. The use of an LC
circuit is not recommended for frequencies higher
than approximately 5 MHz.

TRAP F.F.

TRAP

ACKNOWLEDGE

231718-4

Figure 4. TRAP and RESET In Circuil
The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt enable
status. Performing the first RIM instruction following
a TRAP interrupt allows you to determine whether
interrupts were enabled or disabled prior to the
TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR, or RST 5.5-7.5 will provide
current Interrupt Enable status, revealing that interrupts are disabled. See the description ofthe RIM
instruction in the 8080/8085 Family User's Manual.
The serial I/O system is also controlled by the RIM
and SIM instruction. SID is read by RIM,' and SIM
sets the SOD data.

DRIVING THE X1 AND X2 INPUTS
You may drive the clock inputs of the 8085AH,
8085AH-2, or 8085AH-1 with a crystal, an LC tuned
circuit, an RC network, or an external clock source.
The crystal frequency must be at least 1 MHz, and
must be twice the desired internal clock frequency;

An 'RC circuit may be used as the frequency-determining network for the 8085AH if maintaining a precise clock frequency is of no importance. Variations
in the on-chip timing generation can cause a wide
variation in frequency when using the RC mode. Its
advantage is its low component cost. The driving
frequency generated by the circuit shown is approximately 3 MHz. It is not recommended that frequencies greatly higher or lower than this be attempted.
Figure 5 shows the recommended clock driver circuits. Note in d and e that pullup resistors are required to assure that the high level voltage of the
input is at least 4V and maximum low level voltage
of 0.8V.
For driving frequencies up to and including 6 MHz
you may supply the driving signal to Xl and leave X2
open-circuited (Figure 5d). If the driving frequency is
from 6 MHz to 12 MHz, stability of the clock generator will be improved by driving both Xl and X2 with a
push-pull source (Figure 5e). To prevent self-oscillation of the 8085AH, be sure that X2 is not coupled
back to Xl through the driving circuit.

16-15

inter

8085AH/8085AH·2/8085AH·1

+IY
Xt

eOllIAtI

,----,
I

*

I
I CINT
-15pF

'--:........~_~2

I
X2_ _ _ J

'20 pF capacttors required for '--_ _ _ _ _ __
crystal frequency ,;; 4 MHz only.
231718-5

a. Quartz Crystal Clock Driver.
'X2 left floating
808SAH

r x,

,..--...---1

231718-8

1.:::"" - - . . ,

'1 "

t

d. 1-6 MHz Input Frequency
Clock Driver Circuit

I C'NT
...L. -15pF
LEXT -

.....I

CEXT

;! x.

+IY

I

'----+-....,--11... -""- - _....J

..

231718-6

b. LCTuned Circul~ Clock DrIver

x,

1

47011

'-----lx.

-8K .

20

231718-9

pF ' - - - - (

e.1-12 MHz Input Frequency
External Clock Driver Circuit
231718-7

c. RC Circuit Clock Driver
Figure 5. Clock Driver Circuits

GENERATING AN8085AH WAIT
STATE
.
If your system requirements are such that' slow
memories or peripheral devices are being used, the
circuit shown in Figure 6 may. be used to insert one
WAIT state in each 8085AH machine cycle.

As in the,8080, the READY line is used to extend the
read and write pulse lengths so that the 8085AH can
be used with slow memory. HOLD causes the CPU
to relinquish the bus when it is thOrough with it by
floating the Address and Data Buses.

SYSTEM INTERFACE

Th~

D flip-flops should be chosen so that
• ClK is rising edge-triggered
• CLEAR is low-level active.

~

808SAH
CLlUIUTPIIT"" -

CLEAR
ClK
"0"
F/F

+5V- 0

Q

The 8085AH family includes memory components,
which are directly compatible to the 8085AH CPU.
For example, a system consisting of the three chips,
8085AH, 8156H, and 8755A. will have the following
features:
• 2K Bytes EPROM

TO
808SAH

ClK
'"0'"
F/F

-

• 256 Bytes RAM
• 1 Timer/Counter

READY
INPUT

~~

0

• 4 8-bit 110 Ports,
.1 6-bitll0 Port

231718-10
'ALE and ClK (OUT) should be buffered if ClK input of latch
exceeds 8085AH IOl or IOH.

• 4 Interrupt Levels
• Serial In/Serial Out Ports

Figure 6. Generation of a
Wait State for 8085AH CPU

16-16

8085AH/8085AH-2/8085AH-1

This minimum system, using the standard 1/0 technique is as shown in Figure 7.

shows the system configuration of Memory Mapped
1/0 using 8085AH.
.

In addition to the standard 1/0, the memory mapped
1/0 offers an efficient 1/0 addressing technique.
With this technique, an area of memory address
space is assigned for 1/0 address, thereby, using
the memory address for 110 manipulation. Figure 8

The 8085AH CPU can also interface with the standard memory that does not have the multiplexed addressldata bus. It will require a simple 8-bit latch as
shown in Figure 9.

----

TRAP

r1D~x,
x,

Vss vee

rl I

RESET IN
HOLD
HlDA

RST1.5
RST6.5

SOD

8085AH

RST5.5

SID

ADDR

,

I--

I-

5,1--

INTR

TNTA

II--

ADDRI
DATA ALE AD

18)

Wli

RESET
S.
OUT
101M
RDY ClK

I-Vi'

(81

~

I~r-

vr
POR!~

WR
_
PORT
RD 8156H B

J..

A

ALE
DATAl
ADDR

~

101M
RESET

~
181

PORT~
C

161

IN
TIMER
OUT

r--

-

iow
AD
ALE

Itr-

CE

'"

~.;::

V

J..

.A

A8-10

~

8755A
DATAl
ADDR

1011\;
RESET
I-

PORT
A

*

RDY

~

ClK

PORT
B

~.
Vee

lOR

-.J

.t tJ 1.

Vss Vee Voo PROG

Vee
Vee
Vee
231718-11

• NOTE:
Optional Cqnnection

Figure 7. 8085AH Minimum System (Standard 1/0 Technique)

16-17

-

AS-1S

~O-7
8085AH

...IDc.

!»
co
CI
co
01

3C
S"

WR
101M
CLK

-

RESET OUT f
READY

(I)

~

,!,

to

ID

i
1

..

I.

3

RESET

m '<

:TIMER
IN

+

WR

AD

ALE

AD
CE ",-,70-7

,

-

RD

3"
c

......

r-

0

ALE

l!

(D

,

101M

l

"v

0

-

-

Vee
vce

vec

1

I.
A8-

AD

~A10VO.7 CE

101

1

M ALE AD iOW CLK RS1RDY

3

II

co
0
co
en
)I::z::
.....
co
0
co
en
)I::z::

.

PI)
.....
co

3:
ID

0
CO

Tb~~R_

3
0

~

en
)I::z::

8158H

3C

[RAM

III

+ I/O + COUNTERlTIMERj

.....•

8755A [EPROM + I/O]

~

~

ID
Co

:::::

.9
231718-12

'NOTE:
Optional Connection.

inter

8085AH/8085AH-2/8085AH-1

--

---

TRAP

X2

X,

RESET IN
HOLD
HlDA

RST7
RST6

SOD

8085AH

RST5
INTR
INTA
ADDR

SID

S,
RESET
So
OUT
ADDRI
DATA ALE AD WR 101M
RDYClK

' ~~
'Qr

-_.
--101M (CS)
WR
RD

.1\.

V'

DATA

~

"

\

,

STANDARD
MEMORY
ADDR (CS)

/
V

(16)

---

ClK
RESET
101M (CS)

1/0 POR TS,
lS

B

WR
RD

...

V
r--..

DATA

"

...

I

STANDARD
1/0
ADDR

DUI

II

V

AA
Y:V
YAY;
YV

..

Vee
Vee
Vee
231718-13

Figure 9. 8085 System (Using Standard Memories)

16-19

inter

8085AH/8085AH-2/8085AH-1

BASIC SYSTEM TIMING
The 8085AH has a multiplexed Data Bus. ALE is
used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 10 shows an instruction fetch, memory read and 1/0 write cycle (as
would occur during processing of the OUT instruction). Note that during the 1/0 write and read cycle
that the 1/0 port address is copied on both the up.
per and lower half of the address.
There are seven possible types of machine cycles.
Which of these seven takes place is defined by the
status of the three status lines (101M, S1, So) and

the three control signals (RD, WR, and INTA). (See
Table 3.) The status lines can be used as advanced
controls (for device selection, for example), since
they become active at the T 1 state, at the outset of
each machine cycle. Control lines RD and WR become active later, at the time when the transfer of
data is to take place, so are used as command lines.
A machine cycle normally consists of three T states,
with the exception of OPCODE FETCH, which normally has either four or six T states (unless WAIT or
HOLD states are forced by the receipt of READY or
HOLD inputs). Any T state must be one of ten possible states, shown in Table 4 ..

Table 3. 8085AH Machine Cycle Chart
Status

Machine Cycle

101M

S1

Con,trol
SO

RD

W~~

INTA

OPCODE FETCH

(OF)

0

1

1

0

1

1

MEMORY READ

(MR)

0

1

0

0

1

1

MEMORY WRITE

(MW)

0

0

1

1

0

1

1/0 READ

(lOR)

1

1

0

0

1

1

1/0 WRITE

(lOW)

1

0

1

1

0

1

ACKNOWLEDGE
OFINTR

(INA)

BUS IDLE

(BI):

DAD
ACK.OF
RST,TRAP
HALT

1

1

1

1

1

0

0

1

0

1

1

1

1
TS

1

0

1
0

1
TS

1
TS

1

1

Table 4. 8085AH Machine State Chart
Machine
State

Control

Status & Buses
S1,SO

101M

Aa-A 15

ADo-AD7

RD,WR

INTA

ALE

X

X

X

1

1

1·

T1

X

T2

X

X

X

X

X

X

0

TWAIT

X

X

X

X

X

X

0

Ts

X

X

X

X

X

X

0

T4

1

TS

1

1

0

Ts

1

X

TS

1'

1

0

Ts

1

ot
ot
ot

X
X

TS

1

1

0

TRESET

X

TS

TS

TS

TS

1

0

THALT

0

TS

TS

TS

TS

1

0

THOLD

X

TS

TS

TS

TS

1

0

o = LogIc "0"
TS = High Impedance
X = Unspecified
1 = Logic "1"
• ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
tlOiM = 1 during T4-Ts of INA machine cycle.

16-20

intJ

8085AH/8085AH-2/8085AH-1

M,
CLK

As -A'5

M2

M3

T,

PCH (HIGH ORDER ADDRESS!

(PC + 1IH

S,s. (FETCH!

10 (READ!

AO O_7

ALE

iID

WR

101M

STATUS

01 WRITE

11

231718-14

Figure 10. 8085AH Basic System Timing

16-21

8085AH/8085AH~2/8085AH·1

ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature under Bias .....,. O·C to 70·C
Storage Temperature .......... - 65·C to + 150·C
Voltage on Any Pin
with Re!!pect to Ground .........• - 0.5V to + 7V
Power Dissipation ........•................. 1.5W

• Notice: Stresses above those listed under ':4bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
funCtional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may IfIffect device reliability.

D.C. CHARACTERISTICS
8085AH, 8085AH-2: TA = O·C to 70·C, Vee = 5V t 10%, Vss = OV; unless otherwise specified" '
80S5AH-1: TA = O·C to 70·C, Vee = 5V ±5%, Vss = OV; unless otherwise specified"
Symbol

Parameter

Min

Max

Units

VIL

Input Low Voltage

-0.5

+O.S

V

VIH

Input High Voltage

2.0

Vee +0.5

V

VOL

Output Low Voltage

VOH

Output High Voltage

Icc

Power Supply Current

0.45
2.4

V

IOL

V

IOH

= 2mA
= -400 p,A

135

rnA

8085AH, SOS5AH-2

200

rnA

8085AH-1

IlL

Input Leakage

±10

. p,A

ILO

Output Leakage

±10

p,A

VILR

Input Low Level, RESET,

+O.S

V

VIHR

Input High Level, RESET

2.4

VHY

Hysteresis, RESET

0.15

-0.5

Test Condlti,ons

Vee

+ 0.5

o ~ VIN ~ Vee
0.45V ~ VOUT ,~ Vee

V
'V

A.C. CHARACTERISTICS
SOS5AH, 8085AH-2: TA = o·c to 70·C, Vee = 5V ±10%, vss = ov·
S085AH-1: TA = O·C to 70·C, vee = 5V ±5%, vss = OV
Symbol

Parameter

8085AH (2)

8085AH.2 (2)

8085AH~1 (2)

Min

Max

Min

Max

Min

Max

2000

200

2000

167

2000

tCYC

CLK Cycle Period

320

t1

CLK Low Time (Standard CLK Loading)

SO
120

40

20

Units
ns
ns

t2

CLK High Time (Standard CLK Loading),

tr, tf

CLK Rise and Fall Time

tXKR

X1 Rising to CLK Rising

20

120

20

100

tXKF

X1 Rising to CLK Falling

20

150

20

110

tAC

A8-15 Valid to Leading Edge of Control (1)

270

115

70

ns

tACL

AO-7 Valid to Leading Edge of Control

240

115

60

ns

tAD

AO-15 Valid to Valid Data In

tAFR

Address Float after Leading Edge of
READ (lNTA)

tAL

A8-15 Valid before Trailing Edge'of ALE (1)

70
30

50
30

ns
30

ns

20

100

ns

20

110

ns

575

350

225

ns

0

0

0

ns

115

°NOTE:
For Extended Temperature EXPRESS use M8085AH Electricals Parameters.
16-22

50

25

ns

SOS5AH/SOS5AH·2/S0S5AH·1

A.C. CHARACTERISTICS (Continued)
Symbol

8085AH (2)

Parameter

Min

tAll

AO-7 Valid before Trailing Edge of ALE

tARY

READY Valid from Address Valid

tCA

Address (AS-15) Valid after Control

tcc

Width of Control low (RD. WR.INTA)
Edge of ALE

tCl

Max

. 8085AH-2 (2)
Min

Max

50

90
220

8085AH-1 (2)
Min

25
100

Units

Max

ns

40

ns

120
400

60
230

30
150

ns

Trailing Edge of Control to leading Edge
of ALE

50

25

0

ns

tow

Data Valid to Trialing Edge of WRITE

420

tHABE

HlDA to Bus Enable

tHABF

Bus Float after HlDA

tHACK

HlDA Valid to Trailing Edge of ClK

tHOH

HOLD Hold Time

tHOS

HOLD Setup Time to Trailing Edge of ClK

tlNH

INTR Hold Time

tiNS

INTR. RST. and TRAP Setup Time to
Falling Edge of ClK

tLA .

Address Hold Time after ALE

tlC

Trailing Edge of ALE to leading Edge
of Control

tlCK

ALE low During ClK High

tLDR

ALE to Valid Data during Read

tLDW

ALE to Valid Data during Write

tll

ALE Width

tlRY

ALE to READY Stable

tRAE

Trailing Edge of READ to Re-Enabling
of Address

140

230
210
210

ns

150
150

ns

150
150

ns
ns

110
0
170
0
160

40
0
120
0
150

0
0
120
0
150

100
130

50
60

20
25

ns

100

50

15

ns

460
200
140

270
140
80

110
150

ns
ns
ns

ns

175
110

ns

10

ns

50
30

90
.300

ns
ns

ns

50
150

ns

ns

75

tRO

READ (or INTA) to Valid Data

tRY

Control Trailing Edge to leading Edge
of Next Control

400

220

160

ns

tROH

Data Hold Time after READ INTA
READY Hold Time

tRYS

READY Setup Time to leading Edge
ofClK

0
0
110

0
0
100

0
5
100

ns

tRYH

two

Data Valid after Trailing Edge of WRITE

tWOl

lEADING Edge of WRITE to Data Valid

100

60
40

ns
ns

30
20

ns

ns

30

ns

NOTES:

1. Aa-A15 address Specs apply 101M. SO. and 51 except Aa-A15 are undefined during T4-T6 of OF cycle whereas 101M.
SO. and 51 are stable.
2. Test Conditions: tCYC = 320 ns (SOS5AH)/200 ns (SOS5AH-2);/167 ns (SOS5AH-1); CL = 150 pF.
3. For all output timing where C 150 pF use the following correction factors:
25 pF s;; CL < 150 pF: -0.10 ns/pF
150 pF < CL S;; 300 pF: +0.30 ns/pF
4. Output timings are measured with purely capacitive load.
5. To calculate timing specifications at other values of tCYC use Table 5.

*

16-23

inter

8085AH/8085AH-2/8085AH-1

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT

~~...
~

>

TEST POINTS

0.8

OEVICE
UNDER
TEST

--:I

(ADDRESS. CONTROLS)

BUS

T HOLD

T HOLD

T,

:1
231718-20

READ OPERATION WITH WAIT CYCLE (TYPICAL)-SAME READY TIMING APPLIES TO WRITE
T,

I

T2

/

elK

\

- - tlCK

As-A,.

ADo-AD,

ALE

).

)

r-

T,

~

/

·1

T,

_ICA_

ADDRESS

-

'AD

r- tLL--'"

-tLAtAFR_

.

'Al

tRDH

//II/) -

elL

ADDRESS

-

/:==

<'---'LRY
'ARY

tAC_

.

'Ro

•~ ]--I 'RY'
'RYH _I .
- .... ---....
I

....

~
-)

,I

tee

IJ
. '\

DATA IN

~rRA'-

-'Cl-Y

--'L~-rt

.

..

'LOA

1-

~

RD/iNTA

READY

TWAIT

'i.
lAYS

lIlllllllA

tRYH

J
231718-21

NOTE:
1. Ready must remain stable during setup and hold times.
/

16-26

8085AH/8085AH·2/8085AH·1

WAVEFORMS (Continued)
INTERRUPT AND HOLD

11----·--

BUS FLOATING'

-----1

MI-------------l-----,~----------------~

HOLD

HLOA

231718-22

'NOTE:
101M is also floating during this ·time.

16-27

8085AH/8085AH-2/8085AH-1

Table 6. Instruction Set Summary
Mnemonic

Instruction Code
D7 D6 D5 D4 D3 D2 D1 Do

Operations
Description

MOVE, LOAD AND STORE

Instruction Code
Mnemonic
D765
D D D4 D3 D2 D'1 D0
.

Operations
Description

STACK OPS (Continu.ed)

MOVr1 r2

0

1

D D D S S S Move register
to register

MOVM.r

0

1

1

MOVr.M

0

1 D D D 1

MVlr

0

0

D D D

MVIM

0

0

1

LXIB

0

0

LXID

0

LXIH

0

POPPSW 1 1 1 1 0

1 Pop A and Flags
off stack

XTHL

1 1 1 0 0 0

1 0 Move memory
to register

SPHL

1 1 1 '1

1

1 0 Move immediate
register

LXISP

0 0

1 0

1

1 0 Move immediate
inemory

INXSP

0 0 1 1 0 0

1 1 Increment stack
pOinter

0

0

0

0

0

1 Load immediate
. register Pair B & C

DCXSP

0 0 1 1 1 0

1 1 Decrement stack
pOinter

0

0

1

0

0

0

1 Load immediate
register Pair D & E

JUMP
JMP

1 1 0 0 0

1 1 Jump unconditional

0

1

0

0

0

0

1 Load immediate
register Pair H & L

JC

1 1 0

1 1 0

1 0 Jump on carry

JNC

1 1 0

1 0 0

1 0 Jump on no carry

JZ

1 1 0 0

JNZ

1 1 0 0 0 0 1 0 Jump on no zero

1

0 S S S Move register
to memory

0 0

STAXB

0

0

0

0

0

0

1 0 Store A indirect

STAXD

0.0

0

1 0

0

1 0 Store A indirect

LDAXB

0

0

1

0

1

0

1 0 Load A indirect

LDAXD

0

0

0

1

1

0

1 0 Load A indirect

STA

0

0

1

1 0

0

1 0 Store A direct

LDA

0

0

1

1

1

0

1 0 Load A direct

SHLD

0

0

1

0-0

0

1 0 Store H & L direct

LHLD

0

0

1 0

1

0

1 0 Load H & L direct

XCHG

1

1

1 0

1

0

1

1 Exchange D & E,
H & L Registers

1

1 0 0

1 1 0

0 0

0

1 0

1 Exchange top of
stack, H & L

1 H & Ltostack
pointer
1 Load immediate
stack pointer

1 0 Jump on zero

JP

1 1 1 1 0 0

1 0 Jump on positive

JM

1 1 1 1 1 0

1

JPE

1 1 1 0

1 0 Jump on parity even

1 0

JPO

1 1 1 0 0 0

PCHL

1

1 1 0

1

o

Jump on minus

1 0 Jump on parity odd

0 0

1 H & L to program
counter

CALL

STACKOPS

CALL

1 1 0 0

CC

1 1 0

1 1 1 0 0 Call on carry

1 1 0

1 0

1 Call unconditional

PUSHB

1

1

0

0

0

1

0

1 Push register Pair
B & Con stack

CNC

1 1 0

PUSHD

1

1

0

1

0

1 0

1 Push register Pair
D & E on stack

CZ

1 1 0 0

CNZ

1 1 0 0 0

1 0

1 Push register Pair
H & Lon stack

CP

1 1 1 1 0

1 0 0 Call on positive

CM

1· 1 1 1

1 1 0
1

PUSHH

1

1

1

0

0

1 0

1 0 0 Call on no carry

1 1 0

PUSH
PSW

1

1

1

1

0

1 0

1 Push A and Flags
on stack

CPE

1 1 1 0

POPB

1

1

0

0

0

0

0

1 Pop register Pair
B & C off stack

CPO

1

1 1 0 0

RETURN

POPD

1

1 0

1 0

0

0

1 Pop register Pair
D & E off stack

RET

1

1 0 0

RC

1 1 0

1 1 0 0

1 Pop register Pair
H & L off stack

RNC

1 1 0

1 0 0

RZ

1 1 0 0

POPH

1

1

1

0

0

0

0

16-28

o

Call on zero

0 Call on no zero
0 Call on minus

1 0 0 Call on parity even
1 0

1 0

0

0 Call on parity odd
1 Return
0 Return on carry

0 0 Return on no carry

1 0 0 0 Return on zero

inter

8085AH/8085AH·2/8085AH·1

Table 6. Instruction Set Summary (Continued)
Mnemonic

Instruction Code
D7 D6 Ds D4 D3 D2 Dl Do

Operations
Description

Mnemonic

RETURN (Continued)

Instruction Code
D7 D6 Ds D4 D3 D2 Dl Do .

Operations
Description

IADD (Continued)

RNZ

1

1 0

0 0 0 0 0 Return on no zero

DADO

0 0 0 1 1 0 0 1 AddD&EtoH&L

RP

1

1 1

1 0

DADH

0 0 1 0 1 0 0 1 AddH&LtoH&L

RM

1

1 1

1 1 0

DAD8P

0 0 1 1 1 0 0 1 Add stack pOinter

RPE

1 1 1 0

0 0 0 Return on positive

1 0

0 0 Return on minus

toH&L

0 0 Return on
parity even

RPO

1

1 1 0

IsUBTRACT

0 0 0 0 Return on

8UBr

1 0 0 1 0 8 8 8 Subtract register
from A

8BB r

1 0 0 1 1 8 8 8 Subtract register
from A with borrow

8UBM

1 0 0 1 0 1 1

o 8ubtract memory

8BBM

1 0 0 1 1 1 1

o Subtract memory

8UI

1 1 0 1 0 1 1

o Subtract immediate

SBI

1 1 0 1 1 1 1

o Subtract immediate

parity odd
RESTART
R8T

1

1 A A A 1

1 1 Restart

INPUTIOUTPUT
IN

1 1 0

OUT

1

1 0

1 1 0

1 1 Input

1 0

1 1 Output

0

from A
from A with borrow

INCREMENT AND DECREMENT
INRr

0 0 D D D 1 0 0 Increment register

DCRr

0 0 D D D 1 0

INRM

0 0 1 1 0 1 0 0 Increment memory

DCRM

0 0

INXB

0 0 0 0 0 0 1 1 Increment B & C

1

1 0

1 0

from A

1 Decrement register

from A with borrow

1 Decrement memory

LOGICAL

registers

ANAr

1 0 1 0 0 8 8 8 And register with A

XRAr

1 0 1 0 1 S 8 8 Exclusive OR
register with A

INXD

0 0 0

0

1 1 Increment D & E
registers

ORAr

INXH

0 0 1 0 0 0

1 1 Increment H & L
registers

1 0 1 1 0 8 8 8 OR register
with A

CMPr

DCXB

0 0 0 0 1 0 1 1 Decrement B & C

1 0 1 1 1 8 8 8 Compare register
with A

DCXD

0 0 0 1 1 0 1 1 Decrement 0 & E

ANAM

1 0 1 0 0 1 1

0 0 1 0 1 0 1 1 Decrement H & L

XRAM

1 0 1 0 1 1 1

DRAM

1 0 1 1 0 1 1

CMPM

1 0 1 1 1 1 1

o OR memory with A
o Compare

ANI

1 1 1 0 0 1 1

o And immediate

Add memory to A
with carry

XRI

1 1 1 0 1 1 1

o Exclusive OR

0 Add immediate to A

ORI

1 1 1 1 0 1 1

o OR immediate

CPI

1 1 1 1 1 1 1

o Compare

DCXH

1 0

with A

ADD
ADDr

1 0

0 0 0 8 8 8 Add register to A

ADCr

1 0

0 0 1 8 8 8 Add register to A

memory with A

with carry

o
o

ADDM

1 0 C 0

0 1 1

ADCM

1 0

1 1

ADI

1 1 0

0 0

ACI

1

0 1 1 1 0 Add immediate to A

0 0

1 0

1

1 1

Add memory to A

with A
immediate with A
with A

with carry
DADB

o And memory with A
o Exclusive OR memol)l

0 0 0 0 1 0 0 1 Add B & C to H & L

immediate with A

16-29

inter

8085AH/8085AH-2/8085AH-1

Table 6. Instruction Set Summary (Continued)
Mnemonic

Instruction Code .
D7 D6 Ds D4 D3 D2· D1 Do

Operations
Description

ROTATE

Mnemonic

Instruction Code
~ D6 Ds D4 D3 D2 D1 Do

Operations
Description

CONTROL

RLC

0

0

0

0

0

1

1

1 Rotate A left

EI

1

1

1

1

1

0

1

RRC

0

0

0

0

1

1

1

1 Rotate A right

DI

1 ,1

1

1, 0

0

1

1 Disable Interrupt

RAL

0

0

O. 1

0

1

1

1 Rotate A left
through carry

NOP

0

0

0

0

0

0

0

0 No-operation

HLT

0

1

1

1 0

1

1

0 Halt

RAR

0

0

0

1

1

"

1 Rotate A right
through carry

NEW 8085AH INSTRUCTIONS
RIM

0

0

1 0

0

0 Read Interrupt
Mask

1 Complement A

SIM

0

0

1

1

SPECIALS
CMA

0

0

1

0

1

1

1

STC

0

0

1

1

0

1

1 1 Set carry

CMC

0

0

1

1

1

1

1 1 Complement carry

DAA

0

0

1 0

0

1

1

1 0

1 Decimal adjust A

NOTES:
1. DDS or SSS: B 000, 'C 001, D 010, E011, H 100, L101, Memory 110, A 111.
2. Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags.
"All mnemonics copyrighted @lIntel Corporation 1976.

16-30

0

0

0, 0

1 Enable Interrupts

0 Set Interrupt Mask

8155H/8156H/8155H-2/8156H-2
2048-BIT STATIC HMOS RAM
WITH I/O PORTS AND TIMER

•
•
•
•
•
•

•
•
•
•
•

Single + 5V Power Supply with 10%
Voltage Margins
30% Lower Power Consumption than
the 8155 and 8156
256 Word x 8 Bits
Completely Static Operation
Internal Address Latch
2 Programmable 8-Bit 1/0 Ports

1 Programmable 6-Bit 1/0 Port
Programmable 14-Blt Binary Counter1
Timer
Compatible with 8085AH and 8088 CPU
Multiplexed Address and Data Bus
Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

The Intel® 8155H and 8156H are RAM and I/O chips implemented in N-Channel, depletion load, silicon gate
technology (HMOS), to be used in the 8085AH and 8088 microprocessor systems. The RAM portion is
designed with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns to permit
use with no wait states in 8085AH CPU. The 8155H-2 and 8156H-2 have maximum access times of 330 ns for
use with the 8085H-2 and the 5 MHz 8088 CPU.
The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be
status pins, thus allowing the other two ports to operate in handshake mode.
A 14-bit programmable counter/timer is also included on chip to provide either a square wave or terminal
count pulse for the CPU system depending on timer mode.

101M

256 X 8
STATIC

ADo 7

RAM

*
ALE
RO
WR
RESET

TIMER

G
G
G

PAa - 7

PC,

Vee

PC.

PC.

TIMER IN

PC I

RESET
PC,

PB,

TIMER OUT

PBs

101M
PBo-7

PCa - s

vce 1+5V)
vss IOV)

TIMER CLK

PBs
PB.

AD

231719-1

'8155H/8155H·2 = ~,8156H/8156H-2 = CE

PB,

WR

PB.

ALE

PB,

AD.

PB.

AD,

PA,

AD.

PAs

AD,

PAs

AD.

PA.
PA,

AD,

TIMER OUT

PC.

AD.

PA.

AD,

PA,

vss

PA•.

231719-2

Figure 1. Block Diagram

Figure 2. Pin Configuration

16-31

December 1986
Order Number: 231719-001

inter

. 8155H/8156H/8155H·2/8156H·2

Table 1. Pin Description
Type

Name and FUl1ction

RESET

I

RESET: Pulse provided by the 8085AH to initialize the system (connect to
8085AH RESET OUT). Input high on this line resets the chip and initializes the
three I/O ports to input mode. The width of RESET pulse should typically be
two 8085AH clock cycle times.

ADo-7

I/O

ADDRESS/DATA: 3-state Address/Data lines that interface with the CPU
lower 8-bitAddress/Data Bus. The 8·bit address is latched into the address
latch inside the 8155H/56H on the falling edge of ALE. The address c~ be
either for the memory section or the I/O section depending on the 10/Minput.
The 8·bit data..!!..either written into the chip or read from the chip, depending
on the WR or RD input signal.

CEorCE

.I

CHIP ENABLE: On the 8155H, this pin is CE and is ACTIVE LOW. On the
8156H, this pin is CE and is ACTIVE HIGH.

Symbol

RD

I

READ CONTROL: Input low on this line with the Chip Enable activ~ enables
and ADo-7 buffers. If 10/M pin is low, the RAM content will be read out to the
AD bus. Otherwise the content of the selected I/O port or command/s.tatus .
registers will be read to the AD bus.

WR

I

WRITE CONTROL: Input low on this line with the Chip Enable active causes
the data on the Address/Data bus to bewritt~n to the RAM or I/O ports and
command/status register, depending on 10/M.

ALE

I

ADDRESS LATCH ENABLE: This control signal latches both the address on
the ADo-7 lines and the state of the. Chip Enable and 10/M into the chip at the
falling edge of ALE.

10/M

I

I/O MEMORY: Selects memory if low and I/O and command/status registers
if high.

PAO-7 (8)

I/O

PORT A: These 8 pins are general purpose I/O pins. The in/out direction is
selected by programming the command register.

PBO-7 (8)

I/O

PORT B: These 8 pins are general purpose I/O pins. The in/out direction is
selected by programming the command register.

PCo-s (6)

110

PORT C: These 6 pins can function as either input port, output port, or as
control signals for PA and PB. Programming is done through the command
register. When PCo-s are .used as control signals, they will provide the
following:
PCo-A INTR (Port A Interrupt)
PC,-ABF (port A Buffer Full)
PCr-A STB (Port A Strobe)
PCs-B INTR (Port B Interrupt)
PC4-B BF (Port B Buffer Full)
PCs':""B STB (Port B Strobe)

TIMER IN

I

TIMER OUT

d

TIMER INPUT: Input to the timer-counter.
. TIMER OUTPUT: This output can be either a square wa~e or a pulse,
d~pending on the timer mode.

+ 5V supply.

Vee

VOLTAGE:

Vss

GROUND: Ground reference.

16·32

8155H/8156H/8155H-2/8156H-2

FUNCTIONAL DESCRIPTION

I
I
I

The 8155H/8156H contains the following:
e2K Bit Static RAM organized as 256 x8

I
I

e Two 8-bit I/O ports (PA & PB) and one 6-bit I/O
port (PC)

I
I
I

e 14-bit timer-counter

I

TIMER
MODE

The 101M (IO/Memory Select) pin selects either the
five registers (Command, Status, PAO-7, PBO-7,
PCO-5) or the memory (RAM) portion. .

I

_________ JI

L ____ _

231719-3

The 8-bit address on the Address/Data lines, Chip
Enable input CE or CE, and 101M are all latched onchip at the falling edge of ALE.

CE(8155H)

Figure 3. 8155H/8156H Internal Registers

\

V

'\

/

1\

/

\

V

\

OR

CE(8156H)

101M

A°0-7

X

ADQRESS

I\.

I

X

DATA VALID

ALE

iiiiORWR

NOTE:

231719-4

For detailed timing information, see Figure 12 and A.C. Characteristics.

Figure 4. 8155H/8156H On-Board Memory Read/Write Cycle

16-33

intJ

8155H/8156H/8155H-2/8156H-2

READING THE STATUS REGISTER

PROGRAMMING OF THE COMMAND
REGISTER

The status register consists of seven latches, one
for each bit; six (0-5) for the status of the ports and
one (6) for the status of the timer.

The command register consists of eight latches.
Four bits (0-3) define the mode of the ports, two bits
(4-5) enable or disable the interrupt from port C
when it acts as control' port, and the last two bits
(6-7) are for the ,timer.

The status of the timer and the liD section can be
polled by reading the Status Register (Address
XXXXXOOO). Status word format is shown in Figure
6. Note that you may never write to the status register since the command register shares the same liD
address and the command register is selected when
a write to that address is issued.

The command register contents can be altered at
any time by using the liD address XXXXXOOO during
a WRITE operation with the Chip Enable active and
101M = 1. The meaning of each bit of the command
byte is defined in Figure 5. The contents of the command register may never be read.
5

4

r=
3

2

ITM. TM,I IEBI lEAl Pc.1 PC,

'--r---'

0

PB I PA

I

DF.FINESPAo-, }

0;; INPUT

. DEFINES P90-1

1 '" OUTPUT

, {
DEFINES PCo..

00- ALT 1

" • ALT 2
01
• ALT 3

10 .. ALl'"
ENABLE PORT A

INTERRUPT

'-----'-_ _ _ _ _ _ ~:::RL~U~RT B

}

1 '" ENABLE
0 • DISABLE

00· NOP - DO NOT AFFECT COUNTER

OPERATION
01 '" STOP - NOP IF TIMER HAS NOT STARTED;
STOP COUNTING JF THE TIMER IS

RUNNING
10" STOP AFTER Te - STOP IMMEDIATELY

L-..TIMER COMMAND
l'

E

AFTER PRESENT TC IS REACHEO (NOP
IF TIMER HAS NOT STARTED'
START - LOAD MODE AND CNT LENGTH
AND START IMMEDIATELY AFTER
LOADING (IF TIMER IS NOT PRESENTLY
RUNNINGl. IF TIMER IS RUNNING, START

THE NEW MODE AND CNT LENGTH
IMMEDIATELY AFTER PRESENT Te

IS REACHED,

231719-5

Figure 5. Command Register Bit Assignment
AD,

AD,

ADs AD4 AD3 AD2 AD1 ADo

IXITIMFRI1N:el ~ IIN:RIIN;EI ':F liN;'

I I I T':'"

PORT A INTERRUPT REQUEST

~ ~,.W"'
.."'~_
(lNPUT/OUTPUTI
PORT A INTERRUPT ENABLE
PORT B INTERRUPT REQUEST
PORT B BUFFER FULL/EMPTY
UNPUTIOUTPUTI
PORT B INTERRUPT ENABLED
TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN
TERMINAL COUNT IS
REACHED. AND IS RESET TO
LOW UPON READING OF THE
CIS REGISTER AND BY
HARDWARE RESETI.

Figure 6. Status Register Bit Assignment
16-34

231719-6

inter

8155H/8156H/8155H-2/8156H-2
ond is an output signal. indicating whether the
buffer is full or empty, and the third is an input pin
to accept a strobe for the strobed input mode.
(See Table 2.)

INPUTIOUTPUT SECTION
The 1/0 section of the 8155H/8156H consists of
five registers: (see Figure 7.)
• CommandlStatus Register (C/S)-Both registers are assigned the address XXXXXOOO. The
CIS address serves the dual purpose.
When the CIS registers are selected during
WRITE operation, a command is written into the
command register. The contents of this register
are not accessible through the pins.
When the CIS (XXXXXOOO) is selected during a
READ operation, the status information of the 1/0
ports and the timer becomes available on the
ADo_ilines.
• PA Register-This register can be programmed
to be either input or output ports depending on
the status of the· contents of the CIS Register.
Also depending on the command, this port can
operate in either the basic mode or the strobed
mode (see timing diagram). The 1/0 pins asSigned in relation to this register are PAO-7. The
address of this register is XXXXX001.
• PB Register-This register functions the same
as PA Register. The I/O pins assigned are
PBO-7. The address of this register is XXXXX010.
• PC Register-This register has the address
XXXXX011 and contains only 6 bits. The 6 bits
can be programmed to be either input ports, output ports or as control signals for PA and PB by
properly programming the AD2 and AD3 bits of
the CIS register.
When PCO-5 is used as a control port, 3 bits are
assigned for Port A and 3 for Port B. The first bit
is an interrupt that the 8155H sends out. The sec-

When the 'C' port is programmed to either ALT3 or
ALT4, the control signals for PA and PB are initialized as follows:
Control
BF
INTR
STB

Input Mode
Low
Low
Input Control

1/0 Addresst

(1) Output Mode
(2) Simple Input
(3) Strobed Input

Selection

X X X X X 0

0

X X X X X 0
X X X X X 0
X X X X X 0

0
1
1

X X X X X 1

0

X X X X X 1

0

0 Interval CommandlStatus
Register
1 General Purpose 1/0 Port A
0 General Purpose 1/0 Port B
1 Port C-General Purpose
110 or Control
0 Low-Order 8 bits of Timer
Count
1 High 6 bits of Timer Count
and 2 bits of Timer Mode

X: Don't Care.
t: 1/0 Address must be qualified by CE = 1 (8156H) or CE
= 0 (8155H) and 101M = 1 in order to select the appropriate register.

Figure 7. 1/0 Port a.nd Timer Addressing Scheme
Figure 8 shows how 1/0 PORTS A and B are structured within the 8155H and 8156H:

1

Multiplexer
. Control

Low
High
Input Control

A7 A6 A5 A4 A3 A2 A1 AO

8155H/8156H One Bit of Port A or Port B

NOTES:

Output Mode

231719-7

(4) = 1 for Output Mode
= 0 for Input Mode

READ Port = (101M = 1) • (RD = 0) • (CE Active) • (Port Address Selected)
WRITE Port = (101M = 1) • (WR = 0) • (CE Active) • (Port Address Selected)

Figure 8. 8155H/8156H Port Functions
16-35

inter

8155H/8156H/8155H-2/8156H-2

."

Table 2 Port Control Assignment
Pin

ALT1.

ALT2

PCO
PC1
PC2
PC3
PC4
PC5

Input Port
Input Port
Input Port
Input Port·
Input Port
Input Port .

Output Port
Output Port
Output Port
Output Port
Output Port
Output Port

ALT3
. A INTR (Port A Interrupt)
A SF (Port A Buffer Full)
A 13TB (Port A Strobe)
Output Port
Output Port
Output Port

Note in the diagram that when the 1/0 ports are programmed to be output ports, the contents of the output ports can still be read by a READ operation
when appropriately addressed.
The outputs of the 8155H/8156H are "glitch-free"
meaning that you can write a "1" to a bit position
that was previously "1" and the level at the output
pin will not change.
Note also that the output latch is cleared when the
port enters the input mode. The output latch cannot
be loaded by writing to the port if the port is in. the
input mode. The result is that each time a port mode .
is changed from input to output, the output pin will
go low. When the 8155H/56H is RESET, the output
latches are all cleared and all 3 ports enter the input
mode.
.

ALT4
.A INTR (Port A Interrupt)
A BF (Port A Buffer FiJlI)
A STB (Port A Strobe)
B INTR (Port B Interrupt)
B BF (Port B Buffer Full)
B STB (Port B Strobe)

TIMER SECTION
The time is a 14-bit down-counter that counts the
TIMER IN pulses and provides either a square wave
or pulse when terminal count (TC) is reached.
The timer has the. 1/0 address XXXXX100 for the
low order byte of the register and the I/O address
XXXXX101 for the high order byte of the register.
(See Figure 7.)
To program the timer, the COUNT LENGTH REG is
loaded first, one byte at a time, by selecting the timer addresses. Bits 0-13 of.the high order count register will specify the length of the next count and bits
14-15 of the high order register will specify the timer
output mode (see Figure 10). The value loaded into
the count length register can· have any value from
2H through 3FFFH in Bits 0-13.
.

When in the ALT 1 or ALT 2 modes, the. bits of
PORT C are structured like the diagram above in the
simple input or output mode, respectively.

765432·10

I~I~I~I~I~I~I~I~I

Reading from an input port with nothing connected
to the pins will provide unpredictable results.

~'

r

MSB OF CNT LENGTH

TIMER MODE

7

6

5

4

3

2

,1

O'

I~I~I~I~I~I~I~I~I
,
,

Figure 9 shows how the 8155H/8156H 1/0 ports
might be configured in a typical MCS®-85 system.

LSB OF

CNT LENGTH

231719-9

I

TO 8085AH RST INPUT

--1
PORTA

PORTC

PORTB

OUTPUT

PORT A

A tNTR ISIGNALS DATA RECEIVED)
A SF (SIGNALS DATA READY)
A 5Ta (ACKNOWL. DATA RECEIVED)
B STa (LOADS PORT B LATCH)
B BF (SIGNALS BUFFER IS FULLI

Figure 10. Timer Format

}-~

There are four modes to choose from: M2 and M1
define the timer mode, as shown in Figure 11.

PERIPHERAL
INTERFACE

B tNTR (SIGNALS BUFfER

READY FOR READING)
INPUT

START
COUNT

MODE
BITS

TO INPuJ PORT (OPTIONALI
TO 8085AH RST INPUT

231719-8

Figure 9. Exa,mple:
Command Register = 00111001

M2

M,

o

0

TERMINAL
COUNT

~

(TERMINAL)
COUNT

_____ i ____ .

1. SINGLE
saUAAEWAVE

2. CONTINUOUS
saUAREWAVE

3.

~~~~iEON

---"~--------.--'

TERMINAL COUNT

4. CONTINUOUS
PULSES'

-----,ur----~

231719-10

Figure 11. Timer Modes
16-36

inter

8155H/8156H/8155H-2/8156H-2

Bits 6-7 (TM2 and TM1) of command register contents are used to start and stop the counter. There
are four commands to choose from:
TM2

o
o

TM1

0
1

o

Nap-Do not affect counter operation.
STOP-Nap if timer has not started; stop
counting if the timer is running.
STOP AFTER TC-Stop immediately after
present TC is reached (Nap if timer has
not started)
START-Load mode and CNT.length and
start immediately after loading (if timer is
not presently running). If timer is running,
start the new mode and CNT length immediately after present TC is reached.

Note that while the counter is counting, you may
load a new count and mode into the count length
registers. Before the new count and mode will be
used by the counter, you must issue a START command to the counter. This applies even though you
may only want to change the count and use the previous mode.
In case of an odd-numbered count, the first half-cycle of the squarewave output, which is high, is one
count longer than the second (low) half-cycle, as
shown in Figure 12.

The counter in the 8155H is not initialized to any
particular mode or count when hardware RESET occurs, but RESET does stop the counting. Therefore,
counting cannot begin following RESET until a
START command is issued via the CIS register.
Please note that the timer circuit on the 6155HI
8156H chip is designed to be a square-wave timer,
not an event counter. To achieve this, it counts
down by twos twice in completing one cycle. Thus,
its registers do not contain values directly representing the number of TIMER IN pulses received. You
cannot load an initial value of 1 into the count register and cause the timer to operate, as its terminal
count value is 10 (binary) or 2 (decimal). (For the
detection of single pulses, it is suggested that one of
the hardware interrupt pins on the 8085AH be used.)
After the timer has started counting down, the values residing in the count registers can be used to
calculate the actual number of TIMER IN pulses required to complete the timer cycle if desired. To obtain the remaining count, perform the following oper- ,
ations in order:
1. Stop the count
2. Read in the 16-bit value from the count length
registers
3. Reset the upper two mode bits
4. Reset the carry and rotate right one position all 16
bits through carry
5. If carry is set, add % of the full original count (%
full count-1 if full count is odd).

NOTE:

5

231719-11

NOTE:

If you started with an odd count and you read the
count length register before the third count pulse
occurs, you will not be able to discern whether one
or two counts has occurred. Regardless of this, the
8155H/56H always counts out the right number of
pulses in generating the TIMER OUT waveforms.

5 and 4 refer to the number of clocks in that time period.
.

Figure 12. Asymmetrical Square-Wave Output
Resulting from Count of 9

16-37

8155H/8156H/8155H-2/8156H-2

• 2K Bytes EPROM

8085AH MINIMUM SYSTEM
CONFIGURATION

• 38110 Pins
• 1 Interval Timer
• 4 Interrupt Levels

Figure 13a shows a minimum system using three
chips, containing:

• 256 Bytes RAM

J\
A8-15

_J\

Y1

)

ADO·1

asAN

,

ALE
jjjj

~
t-t--

WA
101M
ClK

r-

r---

t-t-t--

RESET OUT

READY

Vee
TIMER.

IN

RESET

T:'~~R_

G
,,-

WARD

ALE

'-!.

CE:-;

.7
J:

LATCHES

101M

,

7:~~

,

7:

_101
0
ALE
0-7 CE M

jjjj~Oii

ClK RS ROY

J

-~~
CONTROL

256 x 8
RAM

~

8755A (EPROM + 1/0)

I

~~cp~

B88

88

Figure 13a. 8085AH Minimum System Configuration (Memory Mapped I/O)

16-38

231719-12

inter

8155H/8156H/8155H-2/8156H-2

8088 FIVE CHIP SYSTEM

• 38 1/0 Pins
,. 1 Interval Timer

Figure 13b shows a five chip system containing:

• 2 Interrupt Levels

• 1.2SK Bytes RAM
• 2K Bytes EPROM

~

Vss Vee

j

j

~

H-

POR!fOV

>--_WR

AD

PORT
11111101 8

ALE
PORT
DATAl
C

...

ADDR

Vee

p-,

ADDRIOATA

ALE

T~

"

~4
?'"
6

GND

(V,,)

GND
MANUAL,
RESET

X,

RST@

X,
CLK
READY

I--

8284
RESET
RDY'

f-

~

AD

f-

I-- I-

'NA

f-

101M

i-i--

--I

DATAl
ADDR
101M

PORT

RESET

8

READY

~
Vee

~-l

III

f-

~

1755A-I

...

.--

liES

A8 _10

V

ALE

PORT
A

CE

...

/,--

8088
READY
MN/MX f--Vee

rD1

(6)

RD

L-

~

W

lOW

AD DR
A

. - - CLKADo-AD7

(8)

IN_
101M TIMER
OUT f-RESET

"

As-A19

~

LROG

Vss Vee Voo

Vee
WR

....

RD

CE,

G)

118502

ALE

If-

<:S,

i--

CE,

I~

f-

A•• Ag

"'"-

ADO_7

"

I J

V"

Vee

,
231719-13

Figure 13b. 8088 Five Chip System Configuration

16-39

8155HI8156H/8155H-2/8156H-2

ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............ O·C to + 70·C'
Storage Temperature .......... - 65·C to + 150·C
Voltage on Any Pin
with Respect to Ground .......... -O.5V to + 7V '
Power Dissipation .......................... 1.5W

D.C., CHARACTERISTICS
Symbol

TA

=

• Notice: Stresses above those listed under '~bso­
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at, these or any
other conditions above those indicated in the operational sections of this specification is not impliecl.' Exposure' to absolute maximum rating conditions for
extended periods may affect device reliability.

0·Ct070·C, Vcc

Parameter

=

Min

5V ±10%

Max

Units

Test Conditions

,

Vil

Input LowVoltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

Vcc+ 0.5

V

Val

Output Low Voltage

VOH

Output High Voltage

0.45
2.4

V

IOl = 2mA

V

IOH = -400 p-A

III

Input Leakage,

±10

p-A

OV ~ VIN ~ Vcc

ILO

Output Leakage Current

±10

p-A

0.45V ~ VOUT ~ Vcc

Icc

Vcc Supply Current

125

mA

III (CE)

Chip Enable Leakage
8155i-f
-,

+100
-100

8156H

A.C. CHARACTERISTICS TA = O·C to 70·C, Vcc
Symbol

p-A
p-A '

OV ~ VIN ~ Vcc

= 5V ± 10%

'8155H/8156H

Parameter

Min

Max

8155H-2/8156H-2
Min

Units

Max

tAL

Address to Latch Setup Time

50

30

ns

tLA

Address Hold Time after Latch

80

30

ns

tlC

Latch to ,READ/WRITE Control

100

tRO

Valid Data Out Delay from READ Control

170

tLO

Latch to Data Out Valid

350

270

n,s

tAD

Address Stable to Data Out Valid

400

330

ns

tll

Latch Enable Width

tROF

Data Bus Float after READ

40

100
0

ns
140

70
100

0

ns

ns
80

ns

tCl

READ/WRITE Control to Latch Enable

20

10

tCll

WRITE Control to Latch Enable for CIS Register

125

125

ns
ns

tcc

READ/WRITE Control Width

250

200

ns

tow

Data In to WRITE Setup Time

150

100

ns

two

Data In Hold Time after WRITE

25

25

ns

tRV

Recovery Time between Controls

300

200

ns

twp

WRITE to Port Output

400

16-40

300

ns

8155H/8156H/8155H-2/8156H-2

A.C. CHARACTERISTICS
Symbol

TA

=

O·C to 70·C, Vee

Parameter

=

5V ± 10% (Continued)

8155H/8156H
Min

8155H-2/8156H-2

Max

Min

Units

Max

tPR

Port Input Setup Time

70

50

ns

tRP

Port Input Hold Time

50

10

ns

tSBF

Strobe to Buffer Full

tss

Strobe Width

tRBE

READ to Buffer Empty

400

300

ns

tSI

Strobe to INTR On

400

300

ns

tRDI

READ to INTR Off

400

300

ns

tpss

Port Setup Time to Strobe

50

0

ns

tpHS

Port Hold Time After Strobe

120

100

ns

tSBE

Strobe to Buffer Empty

400

300

ns

tWBF

WRITE to Buffer Full

400

300

ns

ns

300

400
200

150

ns

tWI

WRITE to INTR Off

400

300

ns

tTL

TIMER-IN to TIMER-OUT Low

400

300

ns

tTH

TIMER-IN to TIMER-OUT High

300

ns

tRDE

Data Bus Enable from READ.Control

400
10

10

ns

t1

TIMER-IN Low Time

80

40

ns

t2

TIMER-IN High Time

120

70

ns

twr

WRITE to TIMER-IN
(for writes which start counting)

360

200

ns

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT
DEVICE
UNDER
TEST

231719-14
A.C. testing: inputs are driven at 2.4V for a logic "I" and O.45V for
a logic "0". Timing measurements are made at 2.0V for a logic
"I" and O.BV for a logic "0".

i

c
l

= 150pF

231719-15
CL = 150 pF
CL Includes Jig Capacitance

16-41

inter

8155H/8156H/8155H-2/8156H-2

WAVEFORMS
READ

CEC1155HI

/-

CECI15IHI

-

\

101M

/

'\

\.

/

V

\

lAO

- tAl -

DATA VALID

~

- t LA -

~

i\

/

Al E

>-

ADDRESS

>-

7

_t AOf _

- t LL- -

_ILC-~

I--t ROF -

_tRD_

_ I CC · -

"-

1/

-

-tel_ t Rv -

ILO

231719-16

WRITE

\

/

\

CE(I158H)

/

'"'\

7

lolM'

\

I

'\

151H)

aR

X

AO O_7

I-

f---t LA

I AL-

J

ALE

)~

_ t el -

_ t ow -

-

~

DATA VALID

V

~

l - t LL -

tCLL---l

Wi!

K

ADDRESS

-==1

I-

_ t LC

two---':""

\I

1-

IWT

tee ------

_ t Rv -

~j

TIMER IN

I--

"

231719-17

16-42

inter

8155H/8156H/8155H-2/8156H-2

WAVEFORMS '(Continued)

STROBED INPUT
OF

INTR

INPUT DATA
FROM PORT

------------------~~-----+----~~------------------------------------------------------------231719-18

STROBED OUTPUT

OF

INTR

'w,

OUTPUT DATA
TO PORT

--------------------------------------------~~-----------------------------------------------------231719-19

BASIC INPUT

RD

BASIC OUTPUT

==x

'P. \...

'NPUT

OATABUS· -

-- -

-

'.P

}
-

=x

J

-I

WR

k

DATA BUS·

OUTPUT

-------

231719-20

231719-21
'Data Bus Timing is shown in Figure 7,

16-43

~

ii!

»

0

."

::D

c:
~

"tI

c:
~

0

0

c:

z

I

LOAD COUNTER FROM CLR
2
I

~

_I

RELOAD COUNTER FROM CLR

5

3

I

2

I

-\

C

I~

5

""::D0
s:::

TIMER IN

en

~

0

~

TIMER OUT
IPULSEI

\

\~

II

INOTE 1)

___ J

:e

m

<
m

(

0

:::u
3:
en
'0
0
~

:::l

c



AoIO
S755A
DATAl
ADDR

1-r- f-

101M

PoRT

RESET

'

B

W

ROY

X

0

X

0

Power Down and
Function Disable(l)

0

1

1

0

powered Up and
Function Disable(l)

0

0

1

1

I- CLK

~1 v!c vtD tRaG
WR
AD

Powered Up and
Enabled

CE'·S1·S5
ALE

NOTES:
X = Don't Care. .
.'
1: Function Disable 'implies Data Bus· in high impedance
state and not writing.
2: CS· = (CEl = 0) X (CE2 == 1) (CS = 0).
CS· = 1 signifies all chip enables and chip select active.

x

~~-

CS.CE2
,.

Aa.Ag
ADo.7

vt

Table 2. Truth Table for
Control and Data Bus Pin Status
(CS*) RD WR

L
231450-3

ADo,-'; During Data
8185 Function
Portion of Cycle

Figure 3. 8185 In an MCS®-85 System

0

X

X Hi-Impedance .

1

0

1 Data from Memory Read

1

1

0 Data to Memory

Write

1

1

1 Hi-Impedance

Reading, but not
Driving Data Bus

No FU'lction

NOTE:
X = Don't Care.

16-46

4 Chips:
2K Bytes EPROM
1.25K Bytes RAM
38110 Lines
1 CounterITlmer
2 Serial 110 Lines
5 Interrupt Inputs

Vee
Vee

8185/8185-2

iAPX 88 FIVE CHIP SYSTEM:
• 1.2SK Bytes RAM
• 2K Bytes EPROM
• 38 I/O Pins
• 1 Internal Timer
• 2 Interrupt Levels

/).

V•• Vee

I I

~ POR!~

I ~I-

POR~ k A
(81 >

WR
RD

.1_
~

"f

~

ALE
PORTkA>
DATAl
C
(61
ADDR
IN_
101M TIMER
OUT
RESET

f.-

Aa

iOW

ADDR

AI,

v

~

/1

.----

.-

:=

8088
READY

l4
I~

GND
(Vss)

GND
MANUAL
RESET

r- RST

x,

®

ClK
READY

I--

RES

RDY1

"-

Aa_1o

V

I--vee

ALE

~

~

RD

l-

I - I--

WR

I-

101M

~

r---

I284A
RESET

PORT
A

ee

y

rD1
X,

ALE

J~

'J

MNIMX

Vee

ADDR/DATA

CLKAOo- ADr

Ali

,1755A02
DATAl
ADDR

r

101M

PORT

RESET

B

READY

~

~
~

Vee
iDA -.J

III

LROG
Vss Vee VDD

IVee

W1i

....

Ali

ee, .1115-2

CD

ALE

\1-

es.

Irl-

CE,

II-I-

AI,A,

V

ADo·,

Iv•• t

Vee

,

7
231450-4

Figure 4. IAPX 88 Five Chip System Configuration

16-47

8185/8185-2

ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............ O·C to + 70·C
Storage Temperature .......... -65·C to + 150·C
Voltage on Any Pin
with Respect to Ground .......... - 0.5V to + 7V
Power Dissipation .......................... 1.5W

D.C. CHARACTERISTICS
Symbol
Vil

TA

Units

Input Low, Voltage

-0.5

0.8

V

2.0

Vcc+ 0.5

V

0.45

V

Input High Voltage

VOH

Output High Voltage

Test Conditions

IOl = 2mA

2.4

IOH = -400 p.A
±10

p.A

OV ~ VIN ~ Vcc

±10

p.A

0.45V ~ VOUT ~ Vcc

Vcc Supply Current
Powered Up

100

mA

Powered Down

35

mA

Input Leakage
., " Output Leakage Current

A.C. CHARACTERISTICS
Symbol

5V ±10%
Max

Output Low Voltage'

Icc

=

Min

VIH

ILO

0·Ct070·C, Vcc

Parameter

VOL

III

=

• Notice: Stresses above those listed under ':4bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these. or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability..'

TA= 0·Ct070·C, Vcc = 5V ±10%
8185·2

8185

Parameter
Min

Max

Min

tAL

Address to Latch Set Up Time

50

30

tLA

Address Hold Time After Latch

80

30

100

Max

ns
ns

tlC

Latch to READ/WRITE Control

tAO

Valid Data Out Delay from READ Control

170

140

ns

tLD

ALE to Data Out Valid

300

200

ns

tll
tAOF

Latch Enable Width

40

Units

70

100

Data Bus Float After READ

0

ns

100

0

ns
80

ns

tel

READ/WRITE Control to Latch Enable

20

10

ns

tcc

READ/WRITE Control Width

250

200

ns

tow

Data In to WRITE Set Up Time

150

150

ns

two

Data In Hold Time After WRITE

20

20

ns

tsc

Chip Select Set Up to Control Line

10

10

ns

tcs

Chip Select Hold Time A~er Control

10

10

ns

tAlCE

Chip Enable SetUp to ALE Falling

30

10

ns

tLACE

Chip Enable Hold Time After ALE

50

30

ns

16-48

inter

8185/8185-2

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT

"=X >
2.0

TEST POINTS

0.8

0.45

DEVICE
UNDER
TEST

< )C
.
2.0

0.8

i

Cl

= IS0pF

231450-5
221450-6

A.C. Testing: Inputs Are Driven at 2,.4V for a Logic "I" and
0.45V for a Logic "0." Timing Measurements Are Made at
.2.OV for a Logic "I" and O.SV for a Logic "0."

CL=150pF
CL Includes Jig Capacitance

WAVEFORM

ALE

(CE1-01(CE2'"'l'

WR.RD

ADO-AD1

IREAD CYCLE)

(As.Asl

--.cc----I
(WRITE CYCLE I

ADO-AD7

cs.
{DESELECTEDl

(SELECTEDl

231450-7

16-49

intJ
.
•
•
•
•

8224
CLOCK GENERATOR AND DRIVER
FOR 8080A C.PU

Single Chip Clock Generator/Driver for
8080A CPU
Power-Up Reset for CPU
Ready Synchronizing Flip-Flop
Advanced Status Strobe
Oscillator Output for External System
Timing

Controlled for Stable
• Crystal
System Operation
Reduces System Package Count
• Available
• - Standardin EXPRESS
Temperature Range
Available in 16-Lead Cerdip Package
•
(See Packaging Spec, Order #231369)

The Intel 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, seiected
by the designer to meet a variety of system speed requirements.
Also included are circuits to provide power-up reset, advance status strobe, and synchronization of ready.
The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing
for 8080A.

§>

1!9
I!D

XTAL1

,....,.----I>---osc

IE>

RESET

Vee

RESIN

XTAL1

RDYIN

XTAL2

READY

TANK

XTAL2
.. ~, (TTLI

.,

STSTB

~,

osc

SYNC
TANK

I--i~---~,

[E>

I--i~---.,

§>

VDD

GND

I-----¢,ITTLI(D

231464-2

ID
IV

SYNC

----t----ll-..,

mrN --I,>-t-l

l -........--RESET II>

IV

RDYIN --,...---+-1

t----READY[9

RESiN

Reset Input

RESET

Reset Output

XTAL 1

RDYIN

Ready Input

XTAL2

READY

Ready Output

TANK

Us9d with Overtone XTAL

SYNC

Sync Input

OSC

Oscillator Output .

STSTB

StatusSTB
(Active Low)

2(lTL)

<1>2 CLK (TTL Level)

Vee

+5V

}

Voo

+12V

GND

OV

231464-1

Figure 1. Block Diagram

~
<1>2

801i0
Clocks

}

Connections
for Crystal

Figure 2. Pin Configuration

16-50

December 1986
Order Number: 231464-001

inter

8224

ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............ O·C to + 70·C
Storage Temperature .......... -65·C to + 150·C
Supply Voltage, Vee ............... -0.5V to + 7V
Supply Voltage, VOD ............ -0.5V to + 13.5V
Input Voltage ..................... -1.5V to + 7V

• Notice: Stresses above those listed under '~bso­
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect.device reliability.

Output Current .......................... 100 mA

D.C. CHARACTERISTICS
= O·Cto +70·C, Vee = +5.0V ±5%, Voo = +12V ±5%

TA

Symbol

Limits

Parameter
Min

Typ

Units

Test Conditions

Max

IR

Input Leakage Current

10

,."A

Ve

Input Forward Clamp Voltage

1.0

V

VIL

Input "Low" Voltage

V

= 0.45V
VR = 5.25V
Ie = -5mA
Vee = 5.0V

VIH

Input "High" Voltage

2.6

V

Reset Input

2.0

V

All Other Inputs

VIWVIL

RESIN Input Hysteresis

0.25

V

Vee

VOL

Output "Low" Voltage

0.45

V

(4)1, 4>2), Ready, Reset, STSTB
IOL = 2.5mA

0.45

V

All Other Outputs
IOL = 15 mA
IOH

IF

VOH

Input Current Loading

-0.25

mA

0.8

VF

Output "High" Voltage
4>1, 4>2

9.4

V

READY,RESET

3.6

V

IOH

All Other Outputs

2.4

V

IOH

lee

Power Supply Current

115

mA

100

Power Supply Current

12

mA

=

=
=
=

..

5.0V

-100,."A
-100,."A
-1 mA

NOTE:
1. For crystal frequencies of 18 MHz connect 510n resistors between the Xl input and ground as well as the X2 input and
ground to prevent oscillation at harmonic frequencies.

Crystal Requirements

Power Dissipation (Min): 4 mW

Tolerance: 0.Q05% at 0·C-70·C

"NOTE:

Resonance: Series (Fundamental)'

With tank circuit use 3rd overtone mode.

Load Capacitance: 20 pF-35 pF
Equivalent Resistance: 750-200

16-51

inter

8224

A.C. CHARACTERISTICS
Symbol

Parameter

t.,,1

<1>1 Plllse Width

t.,,2

<1>2 Pulse Width

Limits
Min

t01

<1>1 to <1>2 Delay

0

<1>2 to <1>1 Delay

t03

<1>1 to <1>2 Delay

2tcy
.--.14ns
9
2tcy
9

tR

<1>1 and <1>2 Rise Time

tF

<1>1 and <1>2 Fall Time
<1>2 to <1>2 (TIL) Delay

toss

<1>2 to STSTB Delay

tpw

STSTB Pulse Width

tORS

RDYIN Setup Time to
Status Strobe

tORH

RDYIN Hold Time
afterSTSTB

tOR

RDYIN or RESIN to
<1>2 Delay

Max

Units

Test
Conditions

ns

CL= 20pFt050pF

2TIL,CL = 30
R1 :: 3000.
R2 = soon

2tcy
--20ns
9
5tcy
--35ns
9

t02

to.,,2

Typ

2tcy
9 + 20ns
20
20

:-5

+15

ns

Stcy _ 30 ns
9
tcy
- -15ns
9
4tcy
50ns-9
4tcy
9
4tcy
--25ns
9

6tcy
9

ns
STSTB, CL = 15 pF
R1 = 2K
R2 =4K
ns

ns
tcy
9

tCLK

CLKPeriod

fmax

Maximum Oscillating
Frequency,

27

MHz

Cin

Input Capacitance

8

pF

Ready & Reset
CL = 10pF
R1 = 2K
R2 = 4K

ns

VCC = +5.0V
VOO = +12V
VSIAS = 2.5V
'f = 1 MHz

NOTE:

These formulas are based on the internal workings of the part and intended for customer convenience. Actual testing of the
part is done at Icy = 488.28 ns.

1S-52

8224

A.C. CHARACTERISTICS (Continued)
For tey = 488.28 ns; TA = O·C to 70·C, Vee =
Symbol

+5V ±5%, VOO

=

+12V ±5%

LImits

Parameter

Typ

Min

Units
Max

t1

2

2
tpw

ns
129

ns

Output Rise Time

20

ns

Output Fall Time

20

ns

296

326

ns

1, <1>2 Logic "0"

=

1.0V, Logic "1"

= B.OV. All other signals measured at 1.5V.

CLOCK HIGH AND LOW TIME (USING X1, X2)

18MHz

Rl

":-

0"'T

Xl

eLK

X2

R2

-

231464-6

16-54

intJ
•
•
•

•

8228
SYSTEM CONTROLLER AND BUS DRIVER
FOR 8080A CPU

•

Single Chip System Control for
MCS®·80 Systems
Built·ln Bidirectional Bus Driver for
Data Bus Isolation
Allows the Use of Multiple Byte
Instructions (e.g. CALL) for Interrupt
Acknowledge
Reduces System Package Count

•

•

User Selected Single Level Interrupt
Vector (RST 7)
Available in EXPRESS
- Standard Temperature Range
Available in 28·Lead Cerdip and Plastic
Packages
(See Packaging Spec, Order #231369)

The Intel® 8228 is a single chip system controller and bus driver for MCS®-80. It generates all signals required
to directly interface MCS-80 family RAM, ROM, and I/O components.
A bidirectional bus driver is included to provide high system TTL fan-out. It also provides isolation of the 8080
data bus from memory and lID. This allows for the optimization of control signals, enabling the systems
designer to use slower memory and lID. The isolation of the bus driver also provides for enhanced system
noise immunity.
A user selected single level interrupt vector (RST 7) is provided to simplify real time, interrupt driven, small
system requirements. The 8228 also generates the correct control signals to allow the use of multiple byte
instructions (e.g., CALL) in response to an interrupt acknowledge by the 8080A. This feature permits large,
.
interrupt driven systems to have an unlimited number of interrupt levels.
The 8228 is deSigned to support a wide variety of system bus structures and also reduce system package
count for cost effective, reliable design of MCS-80 systems.
NOTE:
The specifications for the 3228 are identical with those for the 8228.

1

0.0,_

CPU
DATA
BUS

°2°30 .. -

0,_
0,0,-

_aBo}

- O B1

- ° 82

::: g:!

SYSTEM DATA BUS

-as,

.

-DB,
- O B7 _

.

III
~
~LATCH

STATUS

GATING
ARRAY

S'rSfii _ _ _ _ _ _ _ _ _-'
231465-2

m ---------------l
____________________

OlIN

~

HLDA -------------iL~~-- IlIITA

231465-1

Figure 1. Block Diagram

07·00

DalaBus (80BO Side)

087·080

Data Bus (System Side)

HlDA

HLDA ('rom B080)

1100

/10 Reed

WI!

WR (from aOBO)
Status Strobe (Irom 8224)

MemoryWri1e

=
Vee

+5V

CaiN (Irom 8080)

GND

o Volta

,"OW

110 Write

tfEfJR

Memory Read

~

DelN

INTA

=

Interrupt Acknowiedge

Bus Enable Input

Figure 2. Pin Configuration

16-55

September 1987
Order Number: 231465-002

inter

8228

*Notice: Stresses above those listed under ':Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions. above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
ex/ended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINqS*·
Temperature Under Bias ............ O'C to+ 70'C
Storage Temperature .......... - 65'C to + 150'C
Supply Voltage, Vee ............... ":'05V to
Input Voltage ...................... -1.5 to

+ 7V
+ 7V

Output Current ...... :' .......... , ....... ,.100 mA

D.C. CHARACTERISTICS TA = O'Cto +70'C, Vee = 5V ±5%·
Symbol

Parameter

Ve

Input Clamp Voltage,
All Input

IF

Input Load Current

limits
Min Typ(1)
0.75

lee

Power Supply Current
Output Low Voltage

VOL
"

VOH

Output High Voltage

Vee = 4.75V; Ie = -5 mA

.500

p.A Vee = 5.25V

750

p.A VF = 0.45V

00,01,04,
05&07

250

p.A

All Other Inputs

250

p.A

100· p.A Vee = 5.25V
VR = 5.25V
20
p.A

OBo-OB7

VTH

V

Test Conditions

02&06

All Other Inputs
Input Threshold
Voltage. All Inputs

~1.0

Unit

STSTB

Input Leakage Current STSTB

IR

Max

O.S
140

"100

p.A

2.0

V

190

Vee =5V

mA Vee = 5.25V

00- 0 7

0.45

V

Vee = 4.75V; 10L = 2 rnA

All Other Outputs

0..45

V

10L =·10mA

V

Vee = 4,.75V; 10H = -10p.A

V

10H = -1 mA

00-0 7

3.6

3.8

All Other Outputs 2.4
los

Short Circuit Current, All Outputs

10 (off)

Off State Output Current
All Control Outputs

liNT

INTA Current

15

90

mA Vee = 5V

100

p.A Vee = 5.25V; Vo = 5.25V

-100
5

NOTE:
1. Typi9al values are for TA'= 25°e and nominal supply voltages.

16-56

p.A Vo = 0.45V
mA (See INTATestCircuit)

8228

CAPACITANCE VSIAS = 2.5V, Vee = 5.0V, TA = 25°C, f = 1 MHz
1. This parameter is periodically sampled and not 100% tested.
Symbol

Parameter

Min

.
Limits
Typ(1)

Max

Unit

CIN

Input Capacitance

8

12

pF

COUT

Output Capacitance
Control Signals

7

15

pF

1/0

1/0 Capacitance
(Dor DB)

8

15

pF

A.C. CHARACTERISTICS

TA

Symbol

=

O°Cto

+ 70°C, Vee =

5V ±5%
Limits

Parameter

Min

Max

Unit

Conditions

tpw

Width of Status Strobe

22

tss

Setup Time, Status Inputs 00-07

8

ns

tSH

Hold Time, Status Inputs 00-07

5

ns

toe

Delay from STSTB to any Control Signal

60

ns

CL

tRR

Delay from DBIN to Control Outputs

30

ns

CL

tRE

Delay from DBIN to EnablelDisable 8080 Bus

45

ns

CL

tRO

Delay from System Bus to 8080 Bus during Read

tWR

Delay from WR to Control Outputs

tWE

Delay to Enable System Bus DBo-DB7 after STSTB

two

Delay from 8080 Bus 00-07 to System Bus
DBo-DB7 during Write

20

5
5

ns

=
=
=
=
=
=
=

100pF
100pF
25 pF

30

ns

CL

45

ns

CL

30

ns

CL

40

ns

CL

CL - 100 pF

tE

Delay from System Bus Enable to System Bus DBo-DB7

30

ns

tHO

HLDA to Read Status Outputs

25

ns

tos

Setup Time, System Bus Inputs to HLDA

10

ns

tOH

Hold Time, System Bus Inputs to HLDA

20

ns

CL

=

25 pF
100 pF
100 pF
100 pF

100 pF

INTA Test Circuit (for RST 7)

AC TESTING LOAD CIRCUIT

.12Y

~Vcc

lKO:l:l0'lo

R,
DEVICE
UNDER
TEST
Cl

i
-=-

~

f

R,

8228

~

-=

231465-3
For Do-~; Rl = 4 KO. R2 = 000, CL = 25 pF.
For all other outputs: Rl. = 5000, R2 = 1 KO, CL = 100 pF.

23
INTA

0--------'

231465-4

16-57

8228
WAVEFORMS

.,
·2----

-"'pw-

"ST"'A"'TU"'S"'S"'T";R"'OB""E

~

X

_DATA BUS

X

I~I-=

-Is.ri

\.

OBIN
INTA, lOR, iiiiiii

IDC_

-l'RRj=-

\
I~

-

HLDA
INTA, lOR, MEMR
OURINGHLDA

SYSTEM BUS DURING READ
_

BUS DURING READ

\

.I_lOS-

I_IHO
~

.--------

~

'~E

-

-:P

1>- - - - - - - - - - - - - - \.
'WR~

lOW OR MEMW

1010 BUS DURING WRITE

SYSTEM BUS DURING WRITE

_____________

_IO~

-------- --------- I- ---~I~ ~~-------------

------~ -~ ,:1-

SYSTEM BUS ENABLE

-

-

-

-

-

-

-

-

-

-

J

'\

------------------ -

SYSTEM BUS OUTPUTS -

J

-11-twR

_1-

-

-

t"IWOl

j
-

d

~I~ ~I:-="

--_-________ _
231465-5

VOLTAGE MEASUREMENT POINTS: Do-D7 (when outputs) LogiC "0"
sured at 1.5V.

·16-58

= O.BV,

Logic "1"

= 3.0V. All other signals mea-

intJ
•
•
•
•
•

8755A
16,384-BIT EPROM WITH 110

•
•
•
•
•

2048 Words x 8 Bits
Single

+ 5V Power Supply (VcC>

Directly Compatible with 8085AH
U.V. Erasable and Electrically
Reprogrammable
Internal Address Latch

2 General. Purpose 8-Bit I/O Ports
Each I/O Port Line Individually
Programmable as Input or Output.
Multiplexed Address and Data Bus·
40-Pin DIP
Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range

The Intel·8755A is an erasable and electrically reprogrammable ROM (EPROM) and I/O chip to be used in the
8085AH microprocessor systems. The EPROM portion is organized as 2048 words by 8 bits. It has a maximum
access time of 450 ns to permit use with. no wait states in an 8085AH CPU. .
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines, and.each I/O port line
is individually programmable as input or output.

ClK~-----,

ADo-7

G
G

As- IO
CE2

2K x 8
EPROM

101M
ALE
RD

iOW
RESET
lOR

t

PROGICE I

v o o - - -....

t.

vee t+5vl

~Vsstovl

231735-1

Figure 1. Block Diagram

PROG ANOCE I

vee

. . eE2

PB 7

ClK

PB6

RESET

PBs

voo

PB4

READY

PB J

101M

PB 2

lOR

PB I

AD

PBo

lOW

PA 7

ALE

PA 6

ADo

PA5

ADI

PA 4

AD2

PA J

AD J

PA 2

A0 4

PAl

AD5

PAo

AD6

A IO

AD7

Ag

vss

As

231735-2

Figure 2. Pin Configuration

16·59

November 1986
Order Number: 231735·002

8755A

Table 1. Pin Description
Symbol
ALE

Type

Name and Function

I

AD!!RESS LATCH ENABLE: When Address latch Enable goes high, ADO-ZL
101M, AS-10, ~ and CE1 enter the address latches. The signals, (AD, 101M,
ADs-10, CE2, CE1) are latched in at the trailing edge of ALE.

ADo_7

I

BIDIRECTIONAL ADDRESS/DATA BUS: The lower 8 bits of the PROM or I/O
address are applied to the bus lines when ALE is high.
Du.!!!:!.9 an 1/0 cycle, Port A or B is selected based on the latched value of ADo.
IF RD or lOR is low when the latched Chip Enables are active, the output
buffers present data on the bus.

ADS-10

I

ADDRESS BUS: These are the high order bits of the PROM address. They do
not affect I/O operations.

PROG/CE1
CE2

.I

CHIP ENABLE INPUTS: CE1 is active low and CE2 is active high. The 8755A
can be accessed only when both Chip Enables are active at the time the ALE
signal latches them up. If either Chip Enable input is not active, the ADo-7' and
READY ouputs will be in a high impedance state. CE1 is also used as a
programming pin. (See section on programming.)

101M

I

I/O MEMORY: If the latched 101M is high when RD is low, the output data
comes from an I/O port. If it is low the output data comes from the PROM.

RD

I

READ: If the latched Chip Enables are active when RD goes low, the ADo-7
output buffers are enabled and output either the selected PROM location or
I/O port. When both RD and lOR are high, the ADo_7 output buffers are 3stated.

lOW

I

I/O WRITE: If the latched Chip Enables are active, a Iowan lOW causes the
output port pointed to b~he latched value of ADo to be written with the data on
ADo-7. The state of 101M is ignored.

ClK

I

CLOCK: The ClK is used to force the READY into its high impedance state
after it has been forced low by CE1 low, CE2 high, and ALE high.

READY

0

READY is a 3-state output controlled by CE1, CE2, ALE and ClK. READY is
forced low when the Chip Enables are active during the time ALE is high, and
remains low until the rising edge of the next ClK. (See Figure 6c;)

PAO.7

I/O

PORT A: These are general purpose I/O pins. Their inputloutput direction is
determined by the contents of Data Direction Register (DDR). Port A is
selected for write operations when the Chip Enables are active and lOW is low
and a 0 was previously latched from ~ AD1.
Read Operation is s~ected ~either lOR low and active Chip Enables and ADo
and AD1 low, or 101M high, RD low, active Chip Enables, and ADo and AD1
low.

PBO-7

I/O

PORT B: The general purpose I/O port is identical to Port A except that it is
selected by a 1 latched from ADo and a 0 from AD1.

RESET

I

RESET: In normal operation, an input high on RESET causes all pins in Ports A
and B to assume input mode (clear DDR register).

lOR

I

I/O READ: When the Chip Enables are active, a Iowan lOR will output the
selected I/O port onto the AD bus. lOR low performs the same function as the
combination of 101M high and RD low. When lOR is not used in a system, lOR
should be tied to Vee ("1 ").

Vee
Vss
Voo

POWER:

+ 5V supply.

GROUND: Reference.
POWER SUPPLY:Voo is a programming voltage, and must be tied to Vee
when the 8755A is being read.
For programming, a high voltage is supplied with Voo =. 25V, typical. (See
section on programming.)
16-60

inter

8755A

A port can be read out when the latched Chip Enables are active and either RD goes low with 101M
high, or lOR goes low. Both input and output mode
bits of a selected port will appear on lines ADo-7.

FUNCTIONAL DESCRIPTION
PROM Section
The 8755A contains an 8-bit address latch which
allows it to interface directly to MCS@-48 and
MCS@-85 processors without additional hardware.

To clarify the function of the 1/0 Ports and Data Direction Registers, the following diagram shows the
configuration of one bit of PORT A and DDR A. The
same logic applies to PORT Band DDR B.

The PROM section of the chip is addressed by the
11-bit address and the Chip Enables. The address,
CEl and CE2 are latched into the address latches on
the falling edge of ALE. If the latched Chip Enables
are active and 101M is low when RD goes low, the
contents of the. PROM location addressed by the
latched address are put out on the ADo-7 lines (provided that Voo is tied to Vecl.

8755A ONE BIT OF PORT A AND DDR A

I/O Section

...

~

ffi

The 1/0 section of tne chip is addressed by the
latched value of ADo-1. Two 8-bit Data Direction
Registers (DDR) in 8755A determine the input/output status of each pin in the corresponding ports. A
"0" in a particular bit position of a DDR signifies that
the corresponding 110 port bit is in the input mode. A
"1" in a particular bit position signifies that the corresponding 1/0 port bit is in the output mode. In this
manner the 1/0 ports of the 8755A are bit-by-bit programmable as inputs or outputs. The table summarizes port and DDR designation. DDR'scannot be
read.

!

RESET

Do

~
AEADPA
231735-3
WRITE PA = (lOW = 0) • (CHIP ENABLES ACTIVE) • (PORT A
ADDRESS SELECTED)
WRITE DDR A = (lOW = 0) • (CHIP ENABLES ACTIVE) • (DDR
A ADDRESS SELECTED)
READ PA = ((101M = 1) • (RD = 0) + (lOR = 0)1 • (CHIP
ENABLES ACTIVE) • (PORT A ADDRESS SELECTED)

NOTE:

ADl ADo

0
0
1
1

0
1
0
1

Write PA is not qualified by IOlM.

Selection
PortA
PortB
Port A Data Direction Registe((DDR A)
Port B Data Direction Register (DDR B)

When lOW goes low and the Chip Enables are active, the data on the ADo-7 is written into 1/0 port
selected by the latched value of ADo_1. During this
operation all 1/0 bits of the selected port are affected, regardless of their 1/0 mode and the state of 10/
M. The actual output level does not change until
lOW returns high. (Glitch free output.)

Note that hardware RESET or writing a zero to the
DDR latch will cause the output latch's output buffer
to be disabled, preventing the data in the Output
Latch from being passed through to the pin. This is
equivalent to putting the port in the input mode. Note
also that the data can be written to the Output Latch
even though the Output Buffer has been disabled.
This enables a port to be initialized with. a value prior
to enabling the output.
The diagram also shows that the contents of PORT
A and PORT B car be read even when the ports are
configured as outputs.

16-61

inter

8755A

ERASURE CHARACTERISTICS

SYSTEM APPLICATIONS

The erasure characteristics cif the 8755A.are such
that erasure begins to occur when exposed to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain types of fluorescent lamps have wavelengths
in the 3000-4000A range. Data show that constant
exposure to room level fluorescent. lighting could
erase the typical 8755A in approximately 3 years
while it would take approximately 1 week to cause
erasure when exp·osed to direct sunlight. If the
8755A is to be exposed to these types of lighting
conditions for extended periods of time, opaque labels are available from Intel which should be placed
over the 8755A window to prevert unintentional era-.
sure.
The recommended erasure procedure for the 8755A,
is exposure to shortwave ultraviolet light which has a
wavelength of 2537 Angstroms (A). The integrated
dose (i.e., UV intensity x exposure time) for erasure
should be a minimum of 15W-sec/cm2. The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 /J-W/cm 2
power rating. The 8755A should be placed within
one inch from the lamp tubes during erasure. Some
lamps have a filter on their tubes and this filter
should be removed before erasure.

System Interface with 8085AH
A system using the 8755A can use either one of the
two I/O Interface techniques:
• Standard I/O
• Memory Mapped I/O
If a standard I/O technique is·used, the system can
use the feature of both CE2 and CE1. By using a
combination of unused address lines All :"15 and the
Chip Enable inputs, the 8085AH system can use up
to 5 8755A's without requiring a CE decoder. See
Figure 4.
'
,
If a memory mapped I/O approach is used the
8755A will be selected by the combination of both
the Chip Enables and 101M using ADs-15 address
lines. See Figure 3.
.
~

A

8085AH

~LE

eLK (~2)

The 8755A can be programmed on the Intel Universal Programmer (iUP), and iUPF8744A programming
module.
The program mode itself consists of programming a
single address at a time, giving a single 50 msec
pulse for every address. Generally, it is desirable to
have a verify cycle after a program cycle for the
same address as shown in the attached timing dia"
gram. In the verify cycle (I.e., normal memory
read cycle) 'Voo' should be at + 5V.

16-62

"

tt--

READY

Initially, and after each erasure, all bits. of the
EPROM portions of the 8755A are in the "1" state.
Information is introduced by selectively programming "0" into the desired bit locations. A programmed "O"canonly be changed to a "1" by UV
erasure.

'.

.~
AD
WIi

PROGRAMMING

~
"-

A":'15

~

1011.1

J~

tttt7 ,

AlD._I

iiITI

f

7
AI-II

I

RD' eLK
101M
ALE mil READY CE
8155A

231735-4

Figure 3. 8755A in 8085AHSystem
(Memory-Mapped 1/0)

l
.

....,

...
::!!

AIDD-7

fa
C

...

ALE

~

.... AN

CO

......
(/I
(/I

~

c.J

I-

I--

CLKI.21

~

0)

I--

AD
Wii

3'

READY

CO
«:I
CO

101M

I-

-

A,.

A ..

A"

-

.--

"

CD

....

"-

.....

An

r'-

-

r-

I--

I-

l-

e-

I--

I-

l-

e-

I-I--

1--

)

-

I-

co

(/I

""

~

en
en

::E:

en

J>

1
CD

3

-...

";,

Cil
I II

7' 7

I,-AIDO-'
10'

:;,

a.
a.

III

......

.0 elK
10""
AU iii READY fE,

.755A
12K BYTES)

II

";,

,

.."
iiii AIDO-' A

";"
'11iiDii

10111tE,
AUiIliiDIelKREADY

.755A
12K BYTESI

i'

7

AID..,

AO-" AU:'0iiielKREADY10"tE,'11iiiiii
1755A
12K BYTES)

7
AID.,

7

AO-" ALEiIlimweLKREADY.. IIICI,'11iiiii AID..,
8755A

12K BYTESI

::::

.9

l'

"

7
A." AU.0illilelKREADY,alii,
I
CE,
8155A
12K BYTESI

231735-6

NOTE:
Use CEl for the first 8755A in the system, and CE2 for the other 8755.A's. Permits up to5-8755A's in a system without CE decoder.

8755A

• Notice.' Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damTemperature Under Bias ........ ,', , , O·C to + 70·C
age to the device. This is a stress rating only and
functional operaiion of the device at these or any
Storage Temperature " " " " " - 65·C to + 150·C
other conditions above those indicated in the operaVoltage on any Pin
tional sections of this specification is not implied Exwith Respect to Ground, , , , , , , , , , - O,5V to + 7V . ,
posure to absolute maximum rating conditions for
Power Dissipation, , , , , , , , , , , , , , , , , , , , , , , , , , 1,5W . extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

D.C. CHARACTERISTICS.
TA = o·c to 70·C, Vee = voo =5V ±5%
' Test Conditions

Min

Max

Unit

VIL

Input Low Voltage

-0,5

0,8

V

Vee = 5,OV

VIH

Input High Voltage

2,0

VOL

Output Low Voltage

VOH

Output High Voltage

IlL

Input Leakage

ILO

Symbol

Parameter

+ 0,5

V

Vee = 5,OV

0.45

V

IOL = 2mA

V

IOH = - 400 /LA

10

/LA

Vss ::;: VIN ::;: Vee

Output Leakage Current

±10

/LA

O,45V::;: Vour::;: Vee

lee

Vee Supply Current

180

rnA

100

Voo Supply Current,

30

Vee

2.4

CIN

Capacitance of Input Buffer

10

CliO

Capacitance of 1/0 Buffer

15

...

rnA

Voo = Vee

pF

fc

pF

fe = 1/LHz

= 1 /LHz

D.C. CHARACTERISTICS-PROGRAMMING
T A = o·C to 70·C, Vee = 5V ± 5%, Vss = OV, Voo = 25V ± 1V
Symbol

Parameter

Voo

Programining Voltage (during Write to EPROM) ,

100

Prog Supply Current

16-64

Min

Typ

24

25

26

V

15

30

rnA

Max

Unit

8755A

A.C. CHARACTERISTICS
= O·C to 70·C. vcc = 5V ±5%

TA

Symbol

8755A

Parameter

Min

Max

Unit

tCYC

Clock Cycle Time

320

ns

T1

CLK Pulse Width

80

ns

T2

CLK Pulse Width

120

tf. tr

CLK Rise and Fall Time

tAL

Address to Latch Set Up Time

tLA
tlC

ns
30

ns

50

ns

Address Hold Time after Latch

80

·ns

Latch to READ/WRITE Control

100

ns

tRD

Valid Data Out Delay from READ Control'

170

ns

tAD

Address Stable to Data Out Valid"

450

ns

tll

Latch Enable Width

100
0

ns

tRDF

Data Bus Float after READ

tCl

READ/WRITE Control to Latch Enahle

20

100

ns
ns

tcc

READ/WRITE Control Width

250

ns

tDW

Data in Write Set Up Time

150

ns

tWD

Data in Hold Time after WRITE

30

twp

WRITE to Port Output

tpR

Port Input Set Up Time

50

tRP

Port Input Hold Time to Control

50

tRYH

READY HOLD Time to Control

0

tARY

ADDRESS (CE) to READY

tRV

Recovery Time between Controls

300

ns

ti=lDE

READ Control to Data Bus Enable

10

ns

ns
400

ns
ns
ns

160

ns

160

ns

NOTES:
CLOAD =
'Or TAD -

150 pF.

(TAL + T Lcl, whichever is greater.
"Defines ALE to Data Out Valid in conjunction with TAL.

A.C. CHARACTERISTICS-PROGRAMMING
= O·C to 70·C, Vcc = 5V ±5%. Vss = OV. VDO = 25V

TA

Symbol

±1V

Parameter

Min

Data Setup Time

10

tpD

Data Hold Time

0

ns

ts

Prog Pulse Setup Time

2

fLs

tH

Prog Pulse Hold Time

2

tpR

Prog Pulse Rise Time

0.01

2

p.s

tPF

Prog Pulse Fall Time

0.01

2

p.s

tpRG

Prog Pulse Width

45

50

·ms

tps

16·65

Typ

Max

Unit
ns

fLs

8755A

A.C. TESTING INPUT, OUTPUT WAVEFORM

.. >
"=X
2.0

.

TEST POINTS

0.45

0.'

~

2.0

0.'

A.C. TESTING LOAD CIRCUIT

)C

DEVICE
UNDER
TEST

ICL.1SOP
F

231735-7
A.C. Testing: Inpuls are driven a12.4V for a Logic "1" and 0.45V
for a Logic "0". Timing Measurements are made al 2.0V for a
Logic "1" and 0.8V for a Logic "0".

CL=150pF
CL Includes Jig Capacitance

231735-8

WAVEFORMS
CLOCK SPECIFICATION FOR 8755A

231735-9

PROM READ, I/O READ AND WRITE

ADDRESS

Aa·10

101M

'------,....,}-

ADO·1

ALE

CE,

--t----·ow

231735-10

Please note that eEl must remain low for the entire cycle.

16-66

intJ

8755A

WAVEFORMS (Continued)
1/0 PORT

~OR

)~

-J~

__________

"''' ---,J ~ '..
INPUT

~-f-rIR_P_______

X. .______

~

DATA· BUS

-

-

-

-

-

-

)(

-------

~------------------

231735-11

A. Input Mode

{

\

PORT
OUTPUT

--- - ----------'::~XO"""'
------------

DATA" BUS

GLITCH FREE

-

-

-

-

____ _

V

..A_________

X".____

..J

231735-12

B. Output' Mode .
WAIT STATE (READY

=

0)

231735-13

16-67

8755A

WAVEFORMS (Continued)
8755A PROGRAM MODE
FUNCTION

I. .~-----

PAOGRAM CYCLE - - - - - -...rl........- - - V E R I F V CYCLE"

------1_

PROGRAM CYCLE

ALE

DATA TO BE

A/DO·7

PROGRAMMED

IpO

A8·10

CEa

Ips

+25
VOO

+5------------------------(

231735-14

·Verify cycle is a regular Memory Read Cycle (with Voo = +5V for 8755A),

16-68

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
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DOMESTIC SALES OFFICES
ALABAIIA

GEORGIA

NEW MEXICO

TEXAS

!~nrs ir~drord Dr., #2

~J8I~:::e Parkway

Intel Corp ..
8500 Menual Boulevard N.E.
Suite B 295

;~~tC:~erson Lane

Huntsville 35805
Tel: (205) 83Q.401 0

Suite 200
Norcross 30092
Tel: (4041449-0541

ARIZONA

W:5~~8th
Dr.,
85029

#0214

~~~~ ~~

Dorado Placa
Suite 301
Tucson 85715
Tel: (602) 299-6815

CALIFORNIA

~C:~OW8n Street

l\n5'1'5
Suita116

i::(a:arrJ4~8~
orp_

~mpe'ial Highway

90245
Tet:

IntoIC':;f.-

NEW YORK

Intel C0M:'·

Tel, (31213¥O-6031

Intel Corp.
127 Main Street
Binghamton 13905
Tel: (607) 773-0337

INDIANA

Inlel Corp.·

lWr ;u~e

~e~~s,s4~~~s OHice Park

Suite 125

~r~~~~~~~

IOWA

Intel Corp."
300 Motor Parkway
Haupcauge 11787

Road

~:~(3;W~~~~
intelCorp.
St. Andrews Building
1930 St. Andrews Drive H.E.
Cedar Rapids 52402
Tel: (319) 393-5510

KANSAS

0·6040

131,r

~~~e~:;'

ILUNOIS

~~mb~nag~~~oad, Suite 400

PhOenix

Tal, (6021869-4980

uite 101

Tel: (916) 920·8096

~"Jg1

t&c::fulive Drive
Suite 105

~:r (~~4;~~~
InleICorp.·
400 N. Tuslln Avenue
Suite 450
Santa Ana 92705

~:1~~955~4
t~t6fg:fs'~

2700 San Tomas Expressway
Santa Clara, CA 95051

~J~~~~~~5

COLORADO
Intel Corp.
4445 Noi'thpark DrIve
Suite 100'

~= ~~~~.&k80907

CONNEcnCUT

,~n~:t~:n R'oad
Oanbu~Q6811

~:7,~~'l~

~~:u~~~:2~:JJ:

llnJ8I~~~~Oth

Street
Suite 170
Overland Park 66210
Tel: (913) 345-2727

MARYLAND
IntelCOIp:
7321 Par1l.way Drive South
SuiteC
Hanover 21 076
Tel: (301) 796-7500
TWX: 710-862·1944

Suite 1490
Houston 77074

~i!J~b~88:"~2~960
UTAH

Intel Corp.
Suile 2B Hollowbrook Park
15 Myers Corners Road
p 'nger Falls 12590
Tel: 914) 297·6161
: 510·248·0060

~e~~(~~~J:'8051

~

NORTH CAROLINA
Intel Corp.
5700 Executive Center Drive
Suile213
Charlotte 28212
Tel: (704) 568-8966

VIRGINIA
tlntelCorp.
1504 Santa Rosa Road
Suital08
RiChmond 23288
Tel: (804) 282·5668

WASHINGTON

lIntel Corp.
ff Road
S~~

Wi"

~:l~~~9r7~~~8022

,.ASSACHUSEns

~~A~~5~~~

Intel Corp:
3401 Park Center Drive
Suite 220
Da~on 45414

tlntel Corp:
Westford Corp. Center
3 Carlisle Road
Westford 01886
Tel: (617) 692·3222
TWX:"110·343-6333

~J~A~b~~~~~~

MICHIGAN

OKLAHOMA

Intel Corp:
25700 Science Park Dr .• Suile 100
BeachwOOd 44122

~n~~ ~~G;oadway

tlntelCorp.
7071 Orchard Lake Road
Suife100
"
West Bloomfield 48033
Tel: (313) 851-8096

Suite 115
Oklahoma City 73116
Tel: (405) 848·8086

MINNESOTA

OREGON

Intel Corp.

t=~~:

MISSOURI

.

~~~~ ~~re ·Freeway

Intel Corp.
5201 Green Street
Suite 290

OHIO

Bloomin~ton 55431
Tel: (612 835-6722
lWX: 91 576-2867

~J~~t~~S~to.85':,~

~J: ~~b~~~~3~

Intel Corp.
5th Roor
7833 Walker Drive
Greenbelt 20770
Tel:. (301) 441·1020

3500 W. 80th St, SUite 360

Suite 314
Austin 78752
Tel: (5121454-3628

Greenbrier Parkway, Bldg. B
Beaverton 97006

~~~~~~~:7~i2,

~nJ:1 ,ro~lIan Road
Suite 102
Spokane 99206
Tel: (509) 928-S086
WISCONSIN
tlntelCorp.
330 S. Executive Or.
Suite 102
Brookfield 53005
Tel: (414) 784-8087
FAX; (4141796·2115

CANADA
BRInSH COWMBIA
Inlel Semiconductor of Canada, Ltd.
Suite 202

ONTARIO

l~~~I~~~~!ct8~: Canada, Ltd.
14

PENNSYLVANIA

FLORIDA

Intel Corp.
1513 Cedar Ciiff Drive

'~~~::tmonte Or.

¥:I~G1~:1 ~:~-1k5

tlntel Semiconductor of Canada, Ltd.
190 Attweli Driva
Sulle500

Tel: (201) 747·2233

Intel Corp."
400 Penn Center Blvd., Suite 610

1~~~t~~a~O~~r:!~f Canada, Ltd.

Intel Corp.
280 Corporate Center
75 Livingston Avenue
First Floor
Roseland 07068
Tel: (201)740,0111

PUERTO RICO

Suite 105

~:.(~r8nsB32714
FAX,3D5-682·6047

NEW JERSEY
Intel Corp.·
Parkway 109 Office Center

~: :~~~~~rlngs Road

~t;'oo~~· Street North

Suite 170

SL _rsbU9! 33702

~:'if~\U~a:~::g

tSales and Service Office
·Reld Application Location

QUEBEC

~::s~~r!h8~:70
Intel Microprocessor Corp.
South industrial Park
P.O. Box 910
Las Piedras 00671
Tel: (809) 733·8618

PoInte Claire H9R 3K3

~~~1~66':4~~1~

(

.DOMESTIC DISTRIBUTORS

tMlcrocomputer System Technical Distributor Centers

DOMESTIC DISTRIBUTORS
NEW MEXICO

NORTH CAROLINA ICon I'd.)

PENNSYLVANIA (Conl'd.)

Alliance Electronics Inc.

Pioneer Electronics
9801 A-Southern Pine Blvd.
Charlotte 28217
Tel: (704) 527-8188
TWX: 810-621-0366

Pioneer Electronics
259 Kappa Drive
Pittsburah 15238

11

~ASHINGTON

Arrow Electronics Inc.
1093 Meyerside Dr,
Unit 2
MlsslssauBa LST 1 M4

~:tj,b?7~2S~'~2

~~X~~',~~~:~=

FAX: 412-963-8255
Hamllton/Avnet Electronics
2524 Baylor Drive S.E.

~:~~~~:t~Jgg
FAX: 50~-243-1395

OHIO

Arrow Electronics, Inc.
7620 McEwen Road
Centerville 45459

NEW YORK

~~~55"~~~:~~

Arrow Electronics, Inc.
25 Hub Drive
Melville 11747

tArrow Electronics, Inc,
6238 Cochran Road
Solon 44139

~~~~~~~~~6

~~~~~\~-~:::~'Wa

FAX: 516-391-1401

HamUton/Avnet Electronics
14212 N.E. 21st Street
Benevue 98005

TEXAS

tArrow Electronics, inc.
:)22D Commander Drive
carrollton 75006

~~~~',t~:~ra
tArrow Electronics, Inc.
10899 Klnghurst Dr.
Suitel0D
Houston 77099
Tel: (713) 530-4700
FAX: 713-568-8518

~~f~':J-:5:g~~

r?'~ ~~2~~~~~~, c;:.~~p

. Bellevue 98005

~~xf~'~~~~

T
FAX: 71 -475-91

t~:ir~~lfat~e~~~lronlcs
Syracuse 13200

~~~~',~_~~~~

~A~f~',~~~=

~~~~\~-~~~:g~~g

~tct~',~~~n~

~~IX~~\~-~;:iA~·

l~G;)!I~~~~~~r il:~:onics

tPioneer Electronics
4433 Interpoin! Blvd.
Dayton 45424
Tef: (513) 236-9900
FAX: 513-236-8133

~~~~~\~.H~~il
tHamliton/Avnet Electronics
~111 W. Walnut Hill lane
Irving 75038

~~~f~\~-~:wgg

tPioneer Electronics
4800 E. 131st Street
Cleveland 44105

~~~~',t~~g::~g

CANADA

~l~fb~li~~~

tHamilton~Avnet

ALBERTA

FAX: 216-587-3906

~~:go~r~7lr7oad, Ste.19D

OKLAHOMA

~~~~'t~~:g~~~~

Arrow Electronics, Inc.
3158 S. 108 East Ave., Ste. 210
Tulsa 74146

KleruUf Electronics, Inc.
2010 Merritt Dr.
Gariand 75040

tArrow Electronics. Inc,
5240 Greens Dairy Road

~1~:~~92~s:a'32
FAX: 91~-876-3132, ext. 200
lHamllton/Avnet ElectronicS
R~~ ~~~orest Drive

~~~~b~te.~~96

KierulH Electronics, Inc.
2238-E W. Bluemound Rd.
Waukesha 53186

B~~~u~o~~13T4

FAX: ~1a-451-8320

tientronics
155 Colonnade Road
Unit 17
Nepean K2E 7K1

~~~~',~_~~~::g
SASKATCHEWAN

Hamilton/Avnet Electronics
2816 21st Street N.E.
Cal g ar6; T2E 6Z2

~A~~~~~~g:~g~?

QUEBEC

tArrow Electronics Inc,
4050 Jean Talon Quest
Montreal H4P 1W1

~~X~~',~_~t~~~~

OREGON

tPioneer Electronics
1828-0 Kramer Lane
Austin 78758

~~~~~~~:~:

~~IX~\"~~~~~~

BRmSH COLUMBIA

Arrow Electronics Inc.

Hamilton/Avnet Electronics

~~~~:;u~~~~:g., Ste.115

~A~f~~~~!~~

~~~f~2~~~'~
FAX: 516-921-2143

NORTH CAROUNA

~~f~\~-~::~~Jg

lZentronlcs

m (~'6) 451-9600

~AIX~~\~-=~:Hgg

~~IX~~\~_~~=

~~~~\~-ggt~g~~

Hamilton/Avnet Electronics
2975 Moorland Road
New Berlin 53151

N"/"ian K2E 7J5

Zentronics
6815 8th Street, N.E., Ste. 100
CalgarJ T2E 7H7

tPloneer Northeast Electronics
60 Crossway Part< West
Woodbury. Lon¥ Island 11797

tPioneer Northeast Electronics
840 Fairport Park
Falrport 14450

.

HamUton/Avnet Electronics
3688 Nashua Dr.
Units 9 and 10
MisSlssa~a L4V 1 M5

tHamiiton/Avnet Electronics
19D Colonnade Road South

~AIX~\',~_=~A~g

Electronics

Units 3-5
MlsslssauBa L4V 1 R2

~A'X}~'16J.:~~:~

l~6r~~p~~J~r:>~:::,ls1e.100

tHamilton/Avnet Electronics
30325 Bainbridge Rd., Bldg. A
Solon 44139

Austin 78758

'~5~::~=eh~~edctronlcs

WISCONSIN

Brookfield 53005

tArrow Electronics, Inc.
2227 W. Braker Lane
Austin 78758
Hamilton/Avnet Electronics

ONTARIO

Zentronics

~8 ~~~~ri~~~Io~o~~~arkwaY
Suite 600
Hillsboro 97124

tPioneer Electronics
5853 Point West Drive
Houston 77036

~~~j\~-:g:~~5~
UTAH

~~f~~~

Zentronics
6D-1313 Border Street
Tel: (201 694-1957
FAX: 2
3-9255

PENNSYLVANIA

~:xf~\~-~~~m
Haminon/Avnet Electronics
Wyle Distribution Group
13"25 West 2200 South
SuileE

¥:~ (~~e ~~~_::JJ9
FAX:

tMicrocomputer System Technical Distributor Centers

MANITOBA

Winnipe~3H OX4

Arrow Electronics, Inc.
650 Seco Road
Monroevl11e 15146

=~i~'5~~" Bldg. E
Tel: (41'2 281-4150
FAX: 412-281-8562

~~~h~~~3 ~6~~~ort Road

~~~~~-~~~:~~~5

80~-972-2524

Zentronlcs

inter
DENMARK

EUROPEAN SALES OFFICES
WEST GERMANY

ISRAEL

SPAIN

IntelSeidlstrass8 27

lmel*
.
...ttldlm Industrial Perk
P.O. Box 43202
Tel Aviv 61430

~:b~oz='3~~n no. 28.',sq

8000 Muenchen 2

~~~=,~r90

mFaV,~~:O 60

Intel

FINLAND

00390 Helsinki 39

~~!~~44

ITALY

l~!~~r4081

Milanoflorl Palazzo E

Inte'·

Intel
Abraham Uncaln StrasH 16-18

FRANCE

6200 Wiesbaden

Intel
1, rue Edlton-BP 303
78054 81 Quentin-en-Yvelines Cedex

l~~~~l7000

t~M~sU~ 40 04
SWEDEN

HoherlZollern Strass. 5

3000 Hannover 1

Intel

RuosDantle2

Intel

l~!~~~~ 6050

Intel·
Alexander Poort Building

~1e~vM~:"7':

. l~~~1~~21 2377

l~:(7~1'.a1~~ 00 82

0100

Milano

m~~,~~4071
NETHERLANDS

Intel
Bruckstrasse 61
7012 Fellbach
s~.n

Intel'

20090 Alsego

NORWAY

Intel

Hvamveien 4-P.O. Box 92

2013S'3:".

SWITZ!RLAND

Intel·
Talackel'$trasS8 17

8065Zur/ch

tnc:~V9fs9 29 n
UMTED KINGDOM
Intel'

~~ri:;''''flt$hlre SN3 1~J

~~,(~~60oo

.

t~~~801~ 420

EUROPEAN DISTRIBUTORS/ REPRESENTATIVES
AUSTRIA

WEST GERMANY

1120Wlen

"

Ri:(~~S 84 60
BELGIUM

lnelca Belgium S.A.
Av. des Croix de Guane 94
1120 Bruxelles

~~~~180180
DENMARK

ITALY (Cont'd.)

Vertrlebs-AG
12
82
10

Bacher Electronics GmbH
Rotenmuehlgasse 26

ITT MultikOmponent GmbH
Bahnhofstrasse
7,.,

44

Mm"lI""

m~~~~9879

m~~~~~-o

20092 Clnlsello BalSamo
Milano

~~~~~0012
NETHERLANDS

~=e:~~r1man

2621 AP Delft
~~~~~~O 99 06

9

Jermyn GmbH
1m Oachsstueck
8250 UmbU,%.,

~~:~::f2~·

NORWAY

80

Nordisk Elektronik AIS
P,O. Box 122
Smedsvingen ..
1384 Hvalstad

Metrologle GmbH

~j~:,::~:~~~9
Tel: (089118 04 20
TLX: 5213189

~~~ttrtO

OYAntronlcAB
Melkonkatu 24A
00210 Helsmkl21

PORTUGAL

~M)2~~:022

Proelectron Vertflebs GmbH
Max Planck Sirasse 1-3
6072 Oreleich
m~~V9~ 30 43 43

FIIANC!

IRELAND

FINlAND

~:Oag=~" Park
g:~~~I~

~~:(y,~6288

.

Ollram
Av. M. Bombard., 133-1 0
1000 Usboa
Tel: (II 54 5313
TLX: 14182

~~!:~:ee68

Bytech Comway Ltd.
Unll2 The Western Centre
Western Road
B
Ba

lRW

2211

Jermyn
Vestry Estate
Otford Road
Sevenoaks
kent TNt. SEU
~:(~~~J24S 0144
Rapid Silicon
RaPJd House
DenmarlcSt.

=~~~~

m!m3f 2268
Rapid,Systems
Rapid House
Denmark St.

A10 Electronica S.A.
Plaza Cludad de Viana no. 6
28040 Madrid

mf~Ja~0244

~~~~2~~ 40 00
ITT-SESA

Eastronles Ltd.
11 Rozenis Street
P.O. Box 39300
Te! Aviv 81392

i~1oMr!fa,:~:ngel no. 21·3

~~~~~SI51

SWEDEN

'TALV

Nordlsk ElektrOnlk A,9.

~~~~7~~ 09 51

~~~g:,~~1

d.. _

11127 SoIna
Tel, (6) 734 97 70
TLX: 10547

Clrle-Vemet ~ BP 2

SWITZERLAND

0_

Accent Electronic Com~nents Ltd.

=~~b='~k

SPAIN

ISRAt!L

.~~:1535

UNITED KINGDOM

~~:"~~~R

YUGOSLAVIA

H.R. MICroelectronics Corp.
2005 de II Cruz Blvd., Ste. 223 •
Santa Clara, CA 95050
U.S.A.

~~!~4~f0286

INTERNATIONAL SALES OFFICES
AUSTRALIA

JAPAN

Inlel Australia Pty. Ltd:

S&ri!rum Bulldin'l

~:~~it~w, ~:~6

JAPAN (Conl'd)

KOREA

Wi~~~~~:i.~·~isu9i Bldg.

Intel Technology Asia ltd.

~:,~t:~~~.37~awa 243

Seoul 150
Tel: (2) 784-8186
TLX: 29312INTELKO
FAX: (2) 784-8096

1-2-1 Asahl-machi

~~t~ti~~-2744

FAX: 0462-29-3781

FAX: (2) 923-263~

BRAZIL

~!~~~f~~~~9~~ld9.

Intel Semlcondutores do Brasil LTD"

f~Fri4;~:l~1183

1-8989 Fuchu-cho

Av. Paulista. 1159-CJS 404/405
01311 -Sao Paulo - S,P.
Tal: 55-11-287-5899
TLX: 1153146

FAX: 55·11-212·7631

~nJ~I~6~s':~~~;~f~ Ltd.

~~x~~J-:~~g:l

Goldhlrr Squara

Intel Japan K,K.·
Aower-HIII Shin-mach! Bldg.
1-23-9Shinmachi

Intel Japan K.K.
Shinmaru Bldg.
1-5-1 Marunouchl

TLX: 39921 INTEL
FAX: 250-9256

FAX: 03-427-7620

FAX: 03-201-6850

Intel Japan K.K:

~':~iw:r. K.K.

:~B·.ro~~c~:ya

~:&f:l~2:~8~fltama 360
FAX: 0485-24-7518
HOHGKONG

SINGAPORE

FAX: 0423-60-0315

~:~a~~~~~~kYO 154

CHINA

Inlel Japan K.K.·
Ayokuchl-Eki Bldg.
2-4-1 Terauchi
Tor:onaka-shi, Osaka 560

~~~y~:~SJ~~~~~o~~~eUngpo-ku

¥~l:Ygg.~f:3~~~YO 100

~~~f2ro.78\~30

TAIWAN

1-16-30 ~eieki Minami
~~~~5~a-ku, Nagoya-shl
Tel: 052-561-5181
FAX: 052-561-5317

~~e~~~G~~~i~:saShl_koSU91 Bldg.

Intel Semiconductor Ltd.·
1701-3 Connaught Centre
1
n u htRoad

915 Shinmaruko, Nakahara-ku

T
TWX:
FAX:

FAX: 044--733-7010

~~=~t:;!7~:ragawa 211

555
ISLHK HX
589

INTERNATIONAL
DISTRIBUTORS/REPRESENTATIVES
ARGENnNA

CHINA IConl'd)

JAPAN ICont'd)

DAFSYSS.R.L.
Chacabuco, 90-4 PISO
t069-Buenos Aires
Tel: 54-1-334-1871
54-1-34-7726
TLX: 25472 .

Schmidt & Co. Ltd.
18/F Great Eagle Centre
23 Harbour Road

Dia Semlcon Systems, Inc.
Wacore 64, 1·37-8 Sa~enjaya

·~r~~~5~~~

TWX: 74766 SCHMC HX
FAX: 852-5-891-8754

Total Electronics
P.M.B.250
9 Harker Street
Burwood, Victoria 3125
Tal: 81-3-288-4044
TLX: AA 31261
Total EJectronles
P.O. Box 139
Artamon, N.S,W. 2064
Tel: 61-02-438-1855
TLX: 26297

BRAZIL
8ebra Microelectronlca
R. Geraido Ftaustno Gomes, 78
SAndat
04575 - Sao Paulo - S.P.
Tel: 55-11-534-9522
TLX: 1154591 or 1154593BR
FAX: 55-11-534-9637

~:I~~~~:2~~:I:;Shi 460

Basavanagudl

Ryoyo EJecl:ro Corp.
Konwa Bldg.
1-12-22 Tsukiji

SINGAPORE

FAX: 03-546-5044

17 Harvey Road #1)4..01

'::~~I:r2~~'
TLX:. 0845-8332 MD BG IN
Micronic Devices
403, Gagan Deep
12, Rajeildra Place
New Delhi 110008
Tel: 91-58-97-71
TLX: 03163235 MONO IN

~:!~ ~.O~'~:!fw~n:iree~g.

N.T., Kowloon

~:'i~"'3-222

TWX: 39114 JINMI HX
FAX: 8524261..&02

"Field Application location

KOREA

Tet, 91.~2-39-63
TLX: 9531 171447 MDEV IN
JAPAN
Asahi Electronics Co. Ltd.
KMM Bldg. 2-14-1 Asano
Kokurakftl.-ku
FAX: "093-551-7861,

¥~~~~7-4~ 107
FAX: 03-497-4969

Francotone Electronics Pte Ltd.

~~1~:~81~89-1618

TWX: 56541 FRELS
FAX: 2895327

SOUTH AFRICA

~~~~~c':~ding Elements, Ply. Ltd.

g~~b~h='irl,Road

C. Itoh Techno-Science Co., Ltd.
C. Itch B~, 2-5-1 Klta-Aoyama

Novel Precision Machin~ Co., ltd.

re'1~~'54~Jf,'04

Mlcronic DeviCes
No. 516 5th Roor
Swastlk Chambers

~~~~~~;~~~~2

ell..

'Okaya Koki
2-4-18 Sakae

FAX: 052-204-2901

DIN Instruments
Suecia2323
CesUIa 6055, Correa 22

~~~.22"8139

Auckland 1
Tel: 64-9-501-219, 501-801
TLX: 21570 THERMAL

Micronic Devices

CHILE

TL.X: 440422 RUDY CZ

FAX: 03-487-8088

Northrup Instruments & Systems Ltd.

~~g.~~~NRe':~arket

INDIA

~~"Jcr.t.&~Road
AUSTRAUA

~:a~a8~~~~kyo 1

NEW ZEALAND

Samsung Semiconductor &
Telecommunications Co., Ltd.
150, 2-KA, Tafpyung-ro, Chung-ku
Seoul 100
Tel: 82-2-751-3987
TLX: 27970 KORSST
FAX: 82-2-753-0967
MEXICO·

Dicopei S.A.
Tochtli 368 Frace. Ind. San Antonio

~~~:=~eXico,

D.F.
Tel: 52-5-561-3211
TLX: 1773790 DICOME

Pine Square, 18th Street
Hazelwood, Pretoria 0001
Tel: 27-12-469921
TLX: 3-227786 SA
TAIWAN

Mltac Corporation

~~P;~5R.~~'l? Shen East Rd.
Tel: 886-2-501-8231
FAX: 886-2-501-4265
VENEZUELA

P. Benavides S.A.
Avllanes a Rio
ResldenCia Kamarata
Locales 4 AL 7
La Candelaria, Caracas
Tel: 58-2-571-0396
TL.X: 28450
FAX: 58-2-572-3321

inter
ALABAMA

DOMESTIC SERVICE OFFICES.
CONNECTICUT

InlelC
6OOE.

SlerraVllt1
Tel: (602)4

ARKANSAS

~.~g:!206

Ulm 72170

Tel: (501) 2414264
CAUFORNIA

FLORIDA

Sulle200

'~':aS&'!r~or~pcpressway

~:ita~~iZalll

InltICorp.

=~~n:t\4 Suite 225

Rarllan Centsr

Edison 08817
Tel: (20') 225-3000

fLUNQrs

NORTH CAROLINA

rei: (9'5) 75'.0'88
YrRGINIA

Intel Corp.
1603 Sanla Rosa Rd .• #109

m:8's~~~eadowvlew Road

Richmond 23288

Tel: (804) 282-5668

Suite 206
Greensboro 27407
Tel: (9'9) 294-'54'
INOIANA

Intel Corp.

~J~Jf~~C,

HEW JERSEY

Norcross 30092
Tel: (404) 44H171

Intel Corp.
8777 Purdue Rd., #'25

~J~~~~4~

Intel Corp.
313 E. Anderlon Lane
Suite 314
AusUn78762

GEORGIA

~,~ ~rrnte Parkway

Intel Corp.

SlIIte110
Santa Ana 92705

IntslCorp.
~~ CJty Expressway

~~h3w.f:.o

~($~rsr8=32714

~~:=a

=~IhStreet

=

TEXAS

SUite 105

=~perial Highway

~:o~:a~r5~'

MJSSOURI

~:"(3~~~'5

~: ~~atmonte DrIve

SUite 218

Tel: (918) 351-8143

PINNSYLVANIA

Intel Corp.
201 Penn Center Boul....ard
Suite 301 W

Suite tOO
West Bloomfield 48033
Tol: (3'3) 851-11905

ARIZONA

InteICcrp.
11225 N. 28th Dr., #0214
Phoenix 85029
Tel: (602) 869"980

MICHIGAN

Intel Corp.
1071 Orchard Lake Road

~":.(a~W~~::\

WASHINGTON

Inlel Corp.
~~~ ~~~d., Suite 102
Tel: (B'9) 781-11022
OHIO

KANSAS

WISCONSIN

te~~~'1Oth Street

InlelCorp.
330 S. EXecutive Dr.
SUI\e'02

Suite 170
Overland Park 66210

Brookfield 53005

Tel: (913) 345-2727
KENTUCKY

Tel: (414) 714-8087
Intel Corp.
8500 Poe

CANADA

~:rr,:r:~

Tel: (408) 970-1740

~,=';a'P'

Rexdale

OREGON

Canada

Tel: (41

MARYLAND

- :;:~orlein Blvd.

Intel Corp.

COLORADO

:mg1~/iiCherry
Sulte91S

Denver 80222

~~~~~~';=

.
PoInte Qalre, Quebec

5th Floor
7833 Walker Drive

canada H9R 3K3
Tel: (5'4) 894-9'30

Greenbeft 20nO
Tal: (301) 441-1020

Intel Corp.
2850 0u88l'lsvtew DrIve. #250

IIASSACHUSErrB

Ottawa. Ontario,

==corp.Center

canada K2B 8H8

Tel: (8'3) 929-9?'4

3 carlllle Road
Westford 01886

Tel: (817) 692·1060

CUSTOMER TRAINING CENTERS
CALifORNIA

ILliNOIS

MASSACHUSEns

MARYLAND

2700 San Tomas Expressway
Santa Clara 95051

~:Um~~~~~:300

3 Carlisle Road
Westford 01886

7833 Walker Dr•• 4th Floor
Greenbelt2f1770
Tel: (30') 220-3380

Tel: (408) 970-1700

Tel: (3'2) 3'1'0-5700

Tel:(617)692-1~

SYSTEMS ENGINEERING OFFICES
CAUFORNIA

ILUNQIS

MASSACHUSETTS

NEW YORK

2700 San Tomas Expressway
Sanla Ctara 95051
'

~:imM~~ln~~#300

3 Carlisi. Road
Westford 01886

300 Motor Parkway

Tel: (408) _8086

Tel: (3'2) 3¥0-B03'

Tel: (617) 692-3222

~:r\fi'~;31~30
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