1988_Intel_Microcomputer_Programmable_Logic_Handbook 1988 Intel Microcomputer Programmable Logic Handbook
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PROGRA,MMABLE LOGIC HANDBOOK 1988 itS · Intel Corporation makes no warranty tor the use of products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. Contact your local sales office to obtain the latest specifications before placing your order. The following are trademarks of Intel Corporation and may only be used to identify Intel Products: Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, GENIUS, i, ICE, iCEL, iCS, iDBP, iDIS, 12 1CE, iLBX, im, iMDDX, iMMX, Inboard, Insite, Intel, intel, inte'BOS, Intel Certified,. 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Additional copies of this manual or other Intel literature may be obtained from: Intel Corporation Literature Distribution Mail Stop SC6-59 3065 Bowers Avenue Santa Clara, CA 95051 @INTELCORPORATION 1987 Table of Contents Alphanumeric Index . .' ................ ; ...•.......•.....•.•...•..•....' .... . vii C,HAPTER 1 Overview Overview ...................................•.....•..........•......•..... 1-1 CHAPTER 2 EPLDs-Erasable Programmable Logic Devices DATA SHEETS Data Sheet Specifications ...............................•........•....•..•. 5C031 , 300·Gate CHMOS H·Series Erasable Programmable Logic Device (H·EPLD) ...........•..............••..•..•............................ 5C032, 300·Gate CHMOS H·Series Erasable Programmable Logic Device (H·EPLD) .........•.•...........•..••....•.....•..•....•....••...•..... 5C060/5C090, 600·/900·Gate CHMOS H·Series Erasable Programmable Logic Device (H·EPLD) .....•...........•..•.........•....•..•................. 5C121, 1200·Gate CHMOS H·Series Erasable Programmable Logic Device ..... . 5C180, 1800·Gate CHMOS Erasable Programmable Logic Device •..•..•...••.. 5AC312, Erasable Programmable Logic Device ..•.......•...••..•.......•..•. APPLICATION BRIEFS AB·8 Implementing Cascaded Logic in the 5C121 .........•....•..•...•...•... AB·9 5C121 As a Three and One·Half Digit Display Driver ; ..•.............•.... AB·10 Square Pegs in Round Holes-A Fitting Tutorial for the 5C121 .•...... ,.... AB·11 16·Bit Binary Counter Implementation Using the 5C060 EPLD ...•..•...... AB·12 Designing a Mailbox Memory for Two,5C031s ...................•...•..• AB·16 Atypical Latch/Register Construction in EPLDs .....•....•..•...•.•.•... AB·18 TTL Macro Library Listing for EPLD Designs .......•.................... APPLICATION NOTES • AP·271 Applying the 5C121 Architecture ......••.•....•..•....•...•..•...•... Ap·272 The 5C060 Unification of a CHMOS System ...•....................... AP·276 Implementing a CMOS Bus Arbiter/Controller in the 5C060 EPLD .••...•. Ap·304 Simulation of EPLD Timing ................•..•.......•.............. AP·307 EPLDs, PLAs, and TTL-Comparing the "Hidden Costs" in Production .... TECHNICAL PAPERS Techniques for Modular EPLD Designs .......•........•....................•. ARTICLE REPRINTS AR·450 Crosspoint Switch: A PLD Approach •.....•.•..•.......•.......•...... AR·451 A Programmable Logic Mailbox for 80C31 Microcontrollers ...•...••..•.. AR·454 Regain Lost I/O Ports with Erasable PLDs ........................... . 2-1 2·2 2-14 2·27 2-45 2·61 2·91 2·108 2-113 2·118 2-130 2·140 2·154 2-161 2·165 2-177 2·188 2·198 2·212 2-234 2·244 2·248 2·251 CHAPTER 3 Advanced Architecture EPLDs DATA SHEETS 5CBIC, Programmable BUS Interface Controller .•....•..•..•...........•...•.. APPLICATION NOTES Ap·305 Dual·Port Memory Control USing the 5CBIC .•.•....................•.. AP·308 The Multiplexed BUS Interface with the 5CBIC .......•...•......••...•. AP·309 DRAM Address Interface with the 5CBIC ..........•.................• ; ARTICLE REPRINTS AR-453 Programmable Logic Shrink Bus Interface Designs ....•..•...........•. CHAPTER 4 3·1 3·19 3·26 3·34. 3·39 Development Support Tools DATA SHEETS iPLDS II, The Intel Programmable Logic Development System Version II ......... . v 4-1 Table of. COl'ltentS(Continued) iUP·PC, Intel Universal Programmer for the Personal Computer ..............••. 4·12 PRODUCT BRIEFS SCHEMA II·PLD ................................•..............•.......... 4·18 Macro Librarian ........... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4·19 UTILITIES Functional Simulator Utility . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . • . . • . • . 4·20 PAL2ADF Utility ...................•....•.... ~ •. ~ .................. ~'" .•. ... . 4·21 JED2HEX Conversion Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . . . . 4·24 APPLICATION NOTES , AP·279 Implementing an EPLD Design Using Intel's Programmable Logic Development System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . 4·25 Ap·311 Using Macros in, EPLD Designs ....•.....•......•..................•. 4·79 Ap·312 Creating Macros for EPLD Designs.. . . .. . .. . . . .. • . . . •. .. . . .•. ..•. .. . . 4·91 TECHNICAL PAPERS Tools for Optimizing PLD Designs. .. . .. . . . .. . . . . . . .. ... . .• . .. .• . . ••. .. . . .. .. 4·101 CHAPTER 5 Appendix . Second Source Cross Reference. .. . . . . . . .. . . .. . .. . . . .. . . . . .. . . . . .. . .. .. . . . . PLA to EPLD Replacement. . . . . . . . . . . . . . . • . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . Ordering Information ......................................•......•........ Device Feature Comparison . . .. . .. . . .. .. .. . .. . . . . . . .. . . .. . . .. . .. . . . . . . .. . . . EPLD Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . . . . . . Compatible Computers for iPLDS II • . . • . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . vi 5·1 5·2 5·3 5·4 5·5 5·6 Alphanumeric Index 5AC312, Erasable Programmable Logic Device...................................... SCBIC, Programmable BUS Interface Controller..................................... 5C031 , 300-Gate CHMOS H-Series Erasable Programmable Logic Device (H-EPLD) ..... 5C032, 300-Gate CHMOS H-Series Erasable Programmable Logic Device (H-EPLD) ..... 5COSO/5C090, SOO-/900-Gate CHMOS H-Series Erasable Programmable Logic Device (H-EPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5C121, 1200-Gate CHMOS H-Series Erasable Programmable Logic Device ............. 5C180, 1800-Gate CHMOS Erasable Programmable Logic Device ..................... iPLDS II, The Intel Programmable Logic Development System Version II ................ iUP-PC, Intel Universal Programmer for the Personal Computer . . . . . . . . . . . . . . . . . . . . . . . . vii 2-91 3-1 2-2 2-14 2-27 2-45 2-S1 4-1 4-12 '.,' "'. Overview 1 "', ~', ". " . ;.' '" " " inter OVERVIEW 8. SMALLER SYSTEM SIZES: Customized compo- INTRODUCTION nents allow for reducing chip count and saving board space, resulting in smaller system physical dimensions. In today's increasingly competitive marketplace, system designers need to squeeze out every little edge they can get from their designs. This has led to a trend towards better performance, smaller system sizes, lower power requirements and greater system reliability with a strong emphasis on preventing easy duplication of the system design. This trend provided the impetus to the system designers to move away from standard SSI and MSI logic components'(54174 & 4000 series Bipolar and CMOS families) towards a growing class of IC devices variously called 'ASIC' (application specific IC), 'USIC' (user specific IC) or, as referred to in this document, user defined logic. b. LOWER SYSTEM COSTS: When custom LSI or VLSI components are used instead of standard SSI and MSI logic elements, there is a considerable saving in component cost per system, assembly and manufacturing cost, printed circuit board area and board costs and inventory costs. c. WGHER PERFORMANCE: RedUced number of ICs contributes to faster system speeds as well as lower power consumption. d. WGHER RELIABILITY: Since prObability of failure is directly related to the number of ICs in the system, a system composed of customized LSI & VLSI chips is statistically much more reliable than the identical system made up of SSI/MSI devices. User defined logic circuits allow system designers, for the first time, to tailor the actual silicon building blocks used in their systems to their individual system needs and requirements. Such customization provides the needed performance, reliability and compactness as· well as design security. Cost per gate of logic implemented is also greatly reduced when user defined logic solutions are chosen over standard components. e. DESIGN SECURITY: Systems designed with standard components can be replicated relatively easily whereas systems that contain user customized ICs cannot be copied because "reverse engineering" of the customized components is .extremely difficult. Thus, use of customized ICs allows for the protection of proprietary designs. User defined logic has therefore emerged as the fastest growing segment of the semiconductor induStry and has presented its users, the system designers,' with a wide range of implementation alternatives namely, programmable logic, gate arrays, standard cell and full custom design. The tradeoffs between these alternatives involves time:to-market, one-time engineering charges" expected unit volume, ease of use of design tools and familiarity with the design me):hodology. f. INCREASED FLEXIBILITY: Customized components allow for the tailoring of systems to the end user's specific needs relatively easily. This also allows for upgradability and obsol~ce protection. USER DEFINED IeIMPLEMENTATION ALTERNATIVES This document discusses the reasons for the trend to user defined logic devices. briefly describes some of the user defined logic implementation alternatives and covers details on programmable logic devices, the only alternative that is completely user implementable. Tools used to design with programmable logic 'are also discussed here. Currently, the choices available t~ the system designer for customization of ICs (see Figure 1) are as follows: (1) User programmable ICs--programmable logic devices (2) mask programmable ICs--gate arrays Details on Intel's programmable logic product line. including device terminology and nomenclature, architectural features and development tool features are also descnbed in this document. (3) standard cell based ICs (4) full custom ICs Alternatives (1) & (2) are usually. called 'Semicustom' because in these methods only a few (less than three) of the mask layers involved in the manufacture of the IC, are customized to the users' specifications. The later two alternatives (3) & (4), involve customization of all mask layers required to manufacture the ICs to the users' specifications and are therefore called 'Custom'. WHY USER DEFINED LOGIC? System designers prefer user customized ICs for the following reasons: 1-1 OVERVIEW his logic requirements, determin~ which ,of these connections he would like to remain open arid which he would like to close, through the programming of the PLD. Programmability of these, connections is achieved using various memory technologies such as fuses, EPROM cells, EEPROM cells or Static RAM cells (see Figure 3). USER DEFINED LOGIC I I I SEIolICUSTOIol I I CUSTOIol I PROGRAIolIolABLE LOGIC GATE ARRAYS I I STANDARD , CELL I FULL ,CUSTOIol 298032-1 User programmability allows for instant customization, very similar to user programmable memories such as PROMs or EPROMs. The user can purchase a PLD off-the-shelf, use a development system running on a personal computer and, in a matter of a few hours, have customized silicon in his hands. Figure 4 compares user-defmed logic alternatives. Figure 1. User Defined Logic Implementation Choices PROGRAMMABLE LOGIC Most user Programmable Logic Devices (PLD) are internally structured as variations of the PLA (programmable logic array) architecture, that is composed of an array of 'AND' gates connected to an array of 'OR' gates (see Figure 2). Programmable logic devices make use of the fact that any logic equation can be converted to an equivalent 'Sum-of-Products' form and can thus be implemented in the 'AND' and 'OR' architecture. This basic ~LA structure has been augmented in most PLDs with input and output blocks containing registers, latches and feedback options, that let the user implement sequential logic functions in addition to combinationa1logic. l'\'Iemory cell u.ed aa logic The number and locations Of the programmable con~ nections between the 'AND' and 'OR' matrices as well as the input and output blocks are predetermined by the architecture of the PLD. The user, depending on c~ntrol element 296032-3 Figure 3. Programmable Connections FEEDBACK (programmabl.) ~~ INPUT [ PIN I ../I.. ../I.. ¥ -v PROGRAIolIolABLE 'AND' &: 'OR'ARRAY -'" ---v ==1 INPUT BLOCK OUTPUT BLOCK (contains latche. and ather programmable Input optlona) (containing output control., reglsterl, etc.) OUTPUT PIN 298032-2 Figure 2. General Architecture of a PLD 1-2 inter OVERVIEW tional testing elements incorporated in the chips, which can be blown to examine electrical characteristics. However, such testing methods never allow for 100% testability of all parts shipped. Thus, most users of bipolar programmable logic devices resort to extensive post-programming testing, specific to their applications. USER DEFINED LOGIC I I I SEMICUSTOM I I PROGRAMMABLE LOGIC CUSTOM I GATE ARRAYS I I I STANDARD CELL FULL CUSTOM ERASABLE PROGRAMMABLE LOGIC DEVICES DESIGN COMPLEXITY DESIGN TIME ac COST LOWEST SYSTEM COST 4 Erasable programmable logic devices (EPLD) result from the matching of CHMOS EPROM technology with the architectures of programmable logic devices. EPLDs use EPROM cells as logic control elements and therefore, when housed in windowed ceramic packages, can be erased with UV light and reprogrammed. Figure 5 shows the architecture of Intel EPLDs. FASTEST TIME TO MARKET EASIEST DESIGN CHANGE IMPLEMENTATION 296032-5 Figure 4. User Defined Logic Alternatives Compared Other than the obvious benefit of reprogrammability, EPLDs offer several very significant benefits over bipolar PLDs. These are: LIMITATIONS OF BIPOLAR FUSE TECHNOLOGY FOR PROGRAMMABLE LOGIC DEVICES 1. LOW POWER CONSUMPTION: Due to the CMOS technology, these products consume an order of magnitude less power than the equivalent bipolar devices. This allows for the design of complete CMOS systems, that can operate at lower voltages (less than 5V). Also, this makes for cooler systems that do not require cooling systems like fans. Until 1985, all PLDs were built using Bipolar fuse technology. The bipolar fuse based devices, although offering the users the benefits of quick time to market and low development costs, had several inherent limitations. 2. GREATER LOGIC DENSITY: EPROM cells are an order of magnitude smaller than the smallest fuses. This means that the same function can be accommodated in significantly smaller die area, or that greater amounts of logic can now be incorporated on a single chip. Thus higher integration programmable logic devices result with the use of EPROM elements. a. HIGH POWER CONSUMPTION: Bipolar processes by nature are power hungry and as a consequence also make for very hot systems, often requiring cooling aids such as heat sinks and fans. They also cannot operate at lower voltages (2-3V) and have a lower level of noise immunity than MOS devices. b. LOWER INTEGRATION: A fuse takes up a large amount of silicon area; this fact in conjunction with the large power requirements makes for smaller levels of integration. 3. TESTABILITY: Since the EPROM cells are erasable, the entire EPROM array of the EPLD can be 100% factory tested. Thus, before the part is shipped to the customers, it can be completely tested by the programming and erasure of all the EPROM logic control bits. This testing is therefore independent of any application, in contrast to the bipolar PLDs that need application specific testing. c. ONE-TIME PROGRAMMABILITY: Bipolar fuses can only be blown once and cannot be reprogrammed. This does not allow for easy prototyping and could result insignificant losses when preprogrammed parts are inventoried and design changes occur. 4. ARCHITECfURAL ENHANCEMENTS: The inherent testability of the EPROM elements allows for d. TESTABILITY: Since fuses can only be blown once, bipolar PLDs can only be destructively tested. Thus, testing is usually done by sampling or through addi- 1-3 inter OVERVIEW significant architectural improvements over, bipolar PLDs. New features, such as buried registers, programmable registers, programmable clock control, etc., can now be incorporated because of this testability. These new features allow, for greatly increased utilization, 'of the EPLDs and use of these devices in newer applications. 5. DESIGN SECURITY: EPLDs are provided with a 'security bit,' which when programmed does not allow anyone to read the programmed pattern. The logic programmed in an EPLD cannot be seen even if the die is examined (unlike bipolar PLDs-a blown fuse is clearly visible) as the stored charges are captured on a buried layer of polysilicon. fEEDBACK (programmable) fiXED _ _ 'OR' ARRAY INPUT PIN--~" PROGRAMMABLE 'AND' ARRAY INPUT BLOCK (contains lotche. and other programmable Input options) ~'" OUTPUT PIN OUTPUT BLOCK (containing output controls, registers, etc.) 296032-4 Figure 5. Architecture of Intel EPLDs USER DEVELOPMENT SOFlWARE PROGRAMMING HARDWARE ~ Data Entry ~ CONVERSION TO BOOLEAN EQUATIONS ~ LOGIC MINIMIZATION TO SUM-OF-PRODUCTS FORMAT [IJ User Specific Resource or Device Request 00 Device Utilization Report rn lID RESOURCE MATCHING OPTIMAL RESOURCE ALLOCATION rn PROGRAMMING PATTERN GENERATION JEDEC Data File 296032-6 Figure 6. The PLD Design Proceas 1-4 OVERVIEW The steps in a generalized design process of programmable logic is shown in Figure 6 and described in the following paragraphs. "JEDEC" format interface and allows the output of the design software to be compatible with any piece of PROM programming hardware. STEP 1: The user decides on the logic he wants implemented in the PLD and enters the design into the PC or workstation. This Desip EDtry may be done by the following methods: (i)SCHEMATiC CAPTURE-A , 'Mouse' or some other graphics input device is used to input schematics of the logic, (ii)NET LIST ENTRYIf the user has a hand drawn schematic he can enter the design into the computer by describing the symbols and interconnections in words using a standardized format called a net list (without using a graphics input device), (iii)STATE EQUATION/DIAGRAM ENTRY-Entry of a sequential design involving states and transitions between states. In the state diagram method circles represent states and the arrows interconnecting them represent the transitions. Equations or a state table can also be used to define a state machine, and (iv)BOOLEAN EQUATIONS-this is the most common design entry method. The logic is described in boolean algebraic equations. STEP 8: PROM programmer is used to program the pattern stored in the JEDEC file onto the PLD. Also, at this stage fuse programmed PLDs (bipolar) are functionally tested using test vectors included in the JE. DEC file information. STEP 2: The software converts all design entry data into boolean equations. CHMOS TECHNOLOGY IN EPLD8 EPLDs are manufactured with Intel's proprietary CHMOS (Complementary High Performance MOS) technology. The backbone of the process is the integration of both a P and an N channel MOS transistor on the same substrate. In addition, EPLD's programmable architecture makes use of Intel's proven EPROM cell for programmable array interconnections as well as macrocell configuration bits. These cells are programmed electrically and erased with ultraviolet light. For details on Intel's CHMOS technology and EPROM cells technology, refer to the Components Quality/Reliability Handbook, Order Number 210997. CHMOS DESIGN GUIDELINES STEP 3: The boolean equations entered are converted to the sum of products format after logic reduction (minimization of the logic through heuristic alga- Designing with Intel EPLDs is relatively straightforward if the following guidelines are observed: • Minimize the occurrence of ESD (electro-static discharge) when storing or handling EPLDs. n'thms). STEP 4: The user has the ability to choose the PLD he would like the design implemented on. He can enter device choice and/or he can also enter in specific choices on the device as regards pinout he would like • Observe good design rules in printed circuit board layout. • Provide adequate decoupling capacitance at both the device and the board level. etc ... STEP 5: The software optimizes the logic equations to fit into the device using the minimum amount of resources (resources are input pins, output pins, registers and product terms and macrocells). This step is where the user requirements as regards required pins are taken into account. The user requests are viewed as constraints during the optimization'process. • Connect all unused inputs to Vcc or GND (CHMOS inputs should not be left floating). Electro8tatlc Discharge The, two most common sources of electrostatic discharge are the hUman body and a charged environment. STEP 6: The software. at the end of the resource optimization/allocation, produces a report detailing the resources used up in fitting the design on the PLD. This report allows the user to incrementally stuff in logic by going back to Step 1 from this stage. Also, if the design overflowed the PLD, i.e., did not fit in the user chosen device, the software lists out the resources needed to complete the fit. The requirements such as four more inputs, one register more and one more output (are needed to complete the design) gives the user data in choosing a bigger PLD or in partitioning the intial design to fit in~ two devices. A charged human body that touches a device lead discharges electriclty into the device. Electrostatic discharge from people handling devices has long been recognized by manufacturers and users of all MOS products. Human body static electricity ,can be controlled by using ground straps and anti-static spray on carpeted floors. CHMOS devices should also be stored and carried in conductive tubes or anti-static foam to minimize exposure to ESD from people. Discharge also occurs when an integrated circuit. is charged to o~ potential and then contacts a conductor at another potential. This type of ESD can be reduced STEP 7: The next step is to generate the appropriate programming pattern for the PLD. This is a standard 1-5 OVERVIEW' by grounding all work surfaces. grounding all handling equipment. removing' static generators' such .as paper from the work area. and erasing EPLDs in metal tubes, metal trays, or conducth:e foam. Tabular methods like Kamaugh maps .are efficient up to a certain point. Past that point, however, computerassisted minimization plays a crucial part in efficient design. Even at the computer-assisted stage, the choice of minimizer software has an itnp;u:t on time and the confidence level of the reduced equation (i.e., is it in the smalleSt possible form). PCB Layout, The best PCB performance is obtained .when close attention is payed to Vee, GND, and signal traces. Vee and GND should be gridded to minimize inductive reactance' and t.o approximate a tr~e' layer. Clocks should be layed out to minimize crosstalk. Ensure adequate power supply and ground pins on the board connector. iPLS II software includes a minimizer that uses the ESPRESSO algorithms .. ESPRESSO was. developed by U.C. Berkeley during the summers of 1981 and, 1982 in an effort to study the various strategies used by the MINI logic minimizer developed by IBM, [HON 74] and PRESTO developed by D. Brown ,[BRO 81]. ESPRESSO uses many of the core principles in MINI and PRESTO while improving on the speed and efficiency of their algorithms. Decoupllng The primary advantage of the ESPRESSO minimizer becomes apparent when designing large finite state machines or complex, product-term intensive logic designs. In these cases,' ESPRESSO arrives at the minimize solution sooner, and frequently reduces .the logic to a smaller number of product terms. In certain cases where other CAD packages such as ABELTM (pRES, TO) or CUPLTM minimize equations to greater than 8 product terms, iPLS II further reduces these equations to allow the design to fit into devices supporting up to 8 product terms. Decouple each EPLD with a ceramic capacitor in the range of 0.01 to 0.2 p.F, depending on board frequency and current consumption. For most applications, a 0.1 p.F capacitor will suffice. The following equation produces the, exact value: AICC C = AVIAT where C = capacitor value Alcc = IlllWmum switched curr~~t i\ V = switching level For more information on ESPRESSO, refer to Logic Minimization Algorithms for VLSI Synthesis, Brayton, Hachtel, McMullen, and Sangiovanni-Vincentelli, lGuwer Academic Publishers. AT '" switching time For boards that contain mixed logic (EPLDs and TTL), observe both EPLD and TTL decoupling practices. References [BRO 81] D.W. Brown, "A State-Machine Synthesiz, er--SMS", Proc. 18th Design Automation 'Conference, pp. 301-304. Nashville, June 1981. [HON 74]' S. J. Hong, R. G. Cain and D. L. Ostapko, "MINI: A heuristic approach to logic minimization." IBM'Journal of Research and Development, Vol. 18, pp. 443-458, September 1974. Unused Inputs , To minimize noise receptivity and power consumption, all unused inputs to EPLDs should be connected to Vee or GND. By default, iPLS II software assigns un~ used inputs to GND. These pins, shown on the pinout representation of the iPLS II report file, should be connected to ground on the PCB. Pins listed as RESERVED on the report file must be left floating. Pins markedN.C.have no internal device connections and can also be left floating. ABELTM is a trademark of Data 1/0 Corporation CUPLTM is a trademark of Personal CAD Systems, Inc. BOOLEAN MINIMIZATION TECHNIQUES FOR PLA LOGIC REFRESHER' COURSE ARC~ITECTURES Minimization of EPLD logic equations is normally performed by sophisticated algorithms that eliminate the heed for tedious manual reductions. The sections provided here contain logic reference tables for cases where manual reduction techniques may be desirable. Minimization plays an important role in logic design. Methods for minimization can be grouped into two classes. Class 1 iricludesmanual methods for minimization, such as Boolean reduction or Karnaugh mapping. Class 2 is computer-assisted minimization. 1-6 inter OVERVIEW Boolean Algebra Karnaugh Maps The Sum-of-PIoduct architecture used in EPLDs makes Boolean algebra ideal for design analysis. The following tables summarize standard Boolean functions. Graphical representation of data is usually easier to analyze than strings of ones and zeros. The Karnaugh Map techniques take advantage of this capability and provide an important tool to the logic designer. Properties I A·B A+B = B• A =B+A Commutative Property Two Variables Associative Property = (A • B) • C A + (B + C) = (A + B) + C A • (B • C) A • (B + C) = A • B + A • C Distributive Property A+B·C =(A+B)·(A+C) 296032-7 Postulates 0·1 = 0 0+0=0 0+1=0 1* 1 = 1 1 O· 0 = 0 +1= Three Variables 0=1 1=0 1 Theorems A·O = 0 A·1 = A A·A = A A·A = 0 A+O=A A +1= 296032-6 A=A 1 A+A=A A+A=1 Four Variables AB CD DeMorgan's Theorems (A + B + C + (A·B·C'O) 0) A·S·C·O A+S+C+O Logic Functions A·A A+A A AANDA AORA A NOT e AS+ AB A B = A EXCLUSIVE OR B 0001 11 10 4 12 8 00 0 01 1 5 13 9 11 3 7 15 11 10 2 6 14 10 296032-9 1-7 OVERVIEW Five Variables BC DE 00 01 11 10 A=O 0001 11 0 4 12 1 5 13 3 7 15 2 6 14 A=1 0001 11,10 16 20 28 24 17 21 29 25 19 23 31 27 18 22 30 26 10 8 9 11 10 BC DE 00 01 11 10 296032-10 Six Variables CD EF" A=O 00 01 11 10 A= 1 00 01 11 10 EF' B=O 0001 11 0 4 12 1 5 13 3 7 15 2 6 14 32 36 33 37 35 39 34 38 0001 10 8 9 11 10 44 40 4S 41 47 43 46 42 11 10 B=1 0001 11 10 16 20 28 24 17 2129 25 19 23 3127 18 22 30 26 48 52 49 53 51 55 50 54 0001 60 56 6157 63 59 62 58 1110 CD EF' 00 01 11 10 00 01 11 10 EF' CD CD 296032-11 T Truth Table Flip-Flop Tables This subsection includes truth tables and excitation tables for the flip-flops supported by EPLDs. T QN QN+1 0 0 1 0 1 0 1 1 0 0 D Truth Table D QN QN+1 0 0 1 1 0 1 0 1 0 0 1 1 1 "1 T Excitation Table D Excitation Table QN QN+1 D 0 0 1 1 0 1 0 1 0 1 0 1 1-8 QN QN+1 T 0 0 1 1 0 1 0 1 0 1 1 0 OVERVIEW when input transitions are not detected over a short period of time. The following paragraphs describe how the Tur~ Bit affects power and speed in EPLDs. JK Truth Table J K QN QN+1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Turbo Oft (Low Power) Intel EPLDs contain circuitry that monitors all inputs for transitions. When a transition is detected while the device is in standby mode, the circuit generates an active pulse. The leading edge of this pulse wakes the device up and the device responds according to its programming, changing outputs as necessary. ,If no new transitions occur during the active pulse, the device enters standby mode again. Outputs are always held valid in standby mode. Input transitions thAt occur during the active mode interval retrigger the active pulse. The active pulse is different depending on the device (SC060, SAC312, etc), but is typically 2-4 times the propagation delay for a particular device. JK Excitation Table QN QN+1 J K 0 0 1 1 0 1 0 1 0 1 X X X X 1 0 In applications with infrequent input transitions, standby mode can result in significant power savings (see the appropriate data sheet for standby power vs. active power). The slight speed loss associated with waking up a device is in the range of 0-10 ns, which is small enough to allow standby mode to be used with most applications (see the appropriate data sheet for effect of Turbo Bit on performance). SR Truth Table S R QN QN+1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 Turbo On (Faster Speed) Illegal In cases where the slight speed loss associated with waking a device from standby mode cannot be traded otT to save power, the Turbo bit can be enabled for maximum speed operation. With the Turbo Bit enabled, the device is always in active mode, thus avoiding the wakeup delay. Note that data sheet performance is specified with the Turbo Bit enabled. JK Excitation Table QN QN+1 S R 0 0 1 1 0 1 0 1 0 1 0 X X 0 1 0 The Turbo Bit is enabled/disabled via a TURBO = ON or TURBO = OFF statement in an iPLS II ADF OPTIONS: statement. It can also be enabled/disabled by editing the JEDEC file, using device pro~ble software. With TURBO = ON the device will be' pro.grammed for high speed; with TURBO := OFF the device will be programmed for automatic standby (power savings). The default state is OFF. NOTES: ON = Present State ON + 1 = Next State X = Don't Care AUTOMATIC STANDBY MODE (TURBO BIT) PACKAGING INTEL EPLDs contain a programmable bit, the Turbo Bit, that optimizes devices for speed or power savings. When TURBO = ON, EPLDs are optimized for speed. When TURBO = OFF, they are optimized for power savings by automatically entering standby mode Intel EPLDs are available in severs1 packages to meet the wide requirements of customer applications. Current information on available packages is available from your local Intel field sales engineer. Detailed information on package dimensions, etc. for a particular package is provided in Packaging Outlines and Dimensions, Order Number 321369, which covers all Intel packages. 1-9 inter OV~RVIEW ORDERING' INFORMATION Intel EPLDs are identified as follows: 'M D 5 L.,,-I' '-.,:-I C ,"--..,.-J I ,-X X X --j ¥ Device s ,-- s + ~ Speed TeclmolollY C -CHMOS AC- Advanced CHMOS Package Type A - Hermetic, Pin Grid Array D ..:.. Hermetic, Type D (Cerdip) Dip ,N - Plastic, Leaded Chip Carrier CJ - Ceramic, J Leaded Chip Carrier P - Plastic Dip and Plastic Flatpack R - Hei1netic, Leadless (::liip Carrier X - Unpackaged Device A - Indicates automotive operating temperature range (-4O"C to + 12S·C) J -Indicates a JAN qualifiecidevice,but is for internal identification purposes only. All JAN devices must be ordered by M38S10 part number. (Example: M38S10/42001 BQB), and will be marked in accordance, with MIL-M-38S10 specifications. L - Indicates extended' operating temperature range ( - 4O"C to + 8S·C) ~~press product with 160 + 8 hrs. dynamic burn-in. 'OM _ Indicates military operating temperature range (- SS·C to + 12S·C) Q - Indicates ,commercialiemperature range (CfC to 7CfC) express product with 160 + 8hrs. dynamic burnT - in. Indicates extended temperature range ( - 4O"C to + 8S·C) express product without burn-in. No letter indicates commercial temperature r~nge (CfC to 70"C) without burn-in. Examples: .QDSC060-4SCommercial with burn-in, ceramic Dip, 060 (600 gate) device, 4S nanosecond. °On military temperatur~devices, B suffix indicates MIL-STD-883C level B processing. 1-10 'EPLDs Erasable Programmable Logic Devices 2 DATA SHEET SPECIFICATIONS The specifications in these data sheets reflect some changes in comparison to earlier data sheets. These changes were made to provide more accurate and usable information concerning Intel EPlDs. A summary of the changes follows. D.C. Characteristics ISB Standby Current (formerly called ICC1). ICC Operating Current (formerly called ICC2). Test conditions have been specified in greater detail. . A.C. Characteristics. (Synchronous) fMAX Maximum Frequency (new. spec.). Maximum frequency operation with no signals fed back to other macrocells. fCNT Maximum Counting Frequency (formerly called f1). Maximum frequency operation with some signals fed back to other macrocells. teo Output Register Valid from ClK (formerly called te01). teNT Register Output Feedback to Register Input - Internal Path (formerly called tP1)· A.C. Characteristics (Asynchronous) . fAMAX Maximum Frequency (new spec.). Maximum frequency operation with no signals fed back to other macrocells. fACNT Maximum Counting Frequency (formerly called fA1). Maximum frequency operation with some signals fed back to other macrocells. tACO Output Register Valid from ClK (formerly called tAC01). tACNT Register Output Feedback to Register Input - Internal Path (formerly called tAP1)· Non-Turbo Mode The Non-Turbo Mode column in several of the data sheets shows the additional time required to power-up the device from standby mode. The column applies only when the device is operated in non-turbo mode (Turbo Bit Off) in an application where the device enters standby mode. See "Automatic Standby-Mode" in the Overview for additional information. 000274-1 2·1 intJ . . 5C031... 300 GATE CHMOS H-SERIESERASABLE P~OGRAMMABLE LO~IC DEVICE (H-EPLD) .~ CHMOS·EPROM Technology Based UV • High Performance, Low Power. Replacement for SSI & MSI Devices and Bipolar PLDs. Erasable. • Up to 18 Inputs (10 Dedicated & 8 I/O) and 8 Outputs. . • Eight Macrocells with Programmable I/O Architecture. • Programmable "Security Bit" Allows Total Protection of Proprietary Designs • 100% Generically Testable EPROM Logic Control Array. • Icc (standby) 35 rnA (max) Icc (10 MHz) 40 rnA (max) • High Performance Upgrade for All Commonly Used 20-pin PLDs. • tpD = 40 ns (max) • 20-pln 0.3" Windowed CERDIP Package . (See Packaging Spec., Order # 231369) 2-2 November 1987 Order Number: 290154-001 SC031 The Intel 5C031 H-EPLD (H-series Erasable Programmable Logic Device) is capable of implementing over 300 equivalent gates of user-customized logic functions through programming. This device can be used to replace bipolar 'programmable logiC , arrays and LS TTL and 74HC, (CMOS) SSI and MSI logic devices. The 5C031 can also be used as a direct, low-power replacement for, almost all common 2Q-pin fuse-based programmable logic devices. With 'its flexible' programmable I/O architecture, this device has advanced functional capabilities beyond that of typical programmable logic. ARCHITECTURE DESCRIPTION The architecture of the 5C031 is based on the "Sum of Products" PLA (Programmable Logic Array) structure with a programmable AND array feeding into a fixed OR array. This device can accommodate both combinational and sequential logiC functions. A proprietary programmable I/O architecture provides individual selection of either combinational or registered output and feedback signals, all with selectable polarity. The 5C031 contains 10 dedicated inputs as well as 8 input/output pins. These I/O pins can be individually configured to be inputs, outputs or bi-directional I/O pins. Each of these I/O pins is connected to a macrocell. The 5C031 contains 8 identical macrocells organized as shown in Figure 1. The 5C031 H-EPLD uses CHMOS EPROM (floating gate) cells as logic control elements instead of fuses. The CHMOS EPROM technology reduces power consumption of H-EPLDs to less than 20% of a comparable bipolar device without sacrificing speed performance. In addition, the use of Intel's advanced CHMOS II-E EPROM process technology enables greater logic densities to be achieved with superior speed and low-power performance over other comparable devices. EPROM technology allows these devices to be 100% factory tested by programming and erasing all the EPROM logic control elements. Each macrocen (see Figure 2) consists of a PLA (programmable logic array) block and an I/O architecture block, which contains a "0" type register. The PLA block consists of eight 36-input AND gates (TRUE & COMPLEMENT of 10 dedicated Inputs plus the 8 feedback inputs from the eight macrocells), feeding into an OR gate. The output of this PLA'block is fed into the I/O architecture block. The different I/O and feedback options that are achievable from the 5C031 I/O block are shown in Figure 3. The 5C031 is housed in a windowed 0.3" 20-pln DIP and has the benefits of being an ideal prototyping tool with its highly flexible I/O architecture. . 2-3 5C031 CLOCK .Q. 1 3 5 7 9 11 131517.1921232527293133,35 . 1. 4 6 8 10 12 14 16 18. 20 22 24 26 28 3 32 34 290154-2 Figure 1. 5C031 Architecture 2-4 l CLOCK .3 0 2 51" 4 7 6 1~ 9 81" 1~ ,13 15 1~ 19 21 23 25 27 29 31 33 35 12 14 1~ 18 ~~ 22 24 26 28 30 ~~ 34 OE 8o o "" ci c iiJ 2 O.~ l) ta o o tj' ~ .......~ ~ II n 6 n 7 CD = ) 0)· .~ ... 0 1 I. ~ .'" .'" l 4 4 11 NOTE 0 = I/O 2 l I. '" .'" '" .'" .'" 4 19 4 3 l 18 I. 4 4 i7 J. ~ .'" .'" ~ .'" .'" ~ .~ .'" l 5 I. 4 'i6 l 6 I. l 15 I. 7 ... 1. .. I. 4 14 8 4 13 '" 0 T PRESET CLOCK ARCHITECTURE CONTROL ~ W Va ""'" .... Co) RESET J.. 1 .. ~ - 9 PIN IN WHICH LOGIC ARRAY INPUT IS FROt.! FEEDBACK PATH ------------------------------------------------------JIL\______________ L-____________________________________________________ PLA BLOCK I/o U'I g ------------~ ARCHITECTURE BLOCK 290154-3 SC031 , . ' . -------------~-----------OUTPUT SELECT PRESET l--<.....-+-I D Q~--~--""~~ CK PRODUCT TERMS ..........". QI--~- '----"'" RESET 'I I I I I I I I, I rEEDBACK SELECT r2 ._-----------------------_ .. rEEDBACK , I, 290154-4 Figure 3. SC031 1/0 'Architecture Conttol 20 PIN CMOS COMPATIBILITY The 5C031 is architected to be a logical su~rset of most 20 pin bipolar programmable array logic (PAL") devices. The 1/0 and logic sections of the5C031 ~evice can be configured to' emulate any of the devices' listed below. Designers can make use of this feature by reducing the power'()f PAL bUed systems (EPLDs are much lower power), replacing multiple PAL inventory items with a single EPLD. Designers can 'also create new 20 pin PLD confi~urations by utilizing the indiVidual logic and o\Jtput controls of eaoh maorocell. List of PAL devices logically compatible with the 5C031. , 10H8 , 12H~ 14H4 16H2 1,6H8 . 16C1 10LB 12L6 14L4 16L2 16L6 , 16R8 1,6R6 16R4 16P8A 16RP8A . 16RP6A 16RP4A ·PAL is a registered trademark of Monolithic Memories, Inc. 2-6 intJ 5C031 Prior to programming or after erasing, the 1/0 structure is configured for combinatorial active low output with input (pin) feedback. ment. This method greatly decreases the overall programming time while programming reliability is ensured as the incremental program margin of each bit is continually monitored to determine when the bit has been successfully programmed. ERASURE CHARACTERISTICS FUNCTIONAL TESTING Erasure characteristics of the 5C031 are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000A. It should be noted that sunlight and certain types of flourescent lamps have wavelengths in the 30004000A. Data shows that constant exposure to room level flourescent lighting could erase the typical SC031 in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the SC031 is to be exposed to these types of lighting conditions for extended periods of time, conductive opaque labels should be placed over the device window to prevent unintentional erasure. Since the logical. operation of the SC031 is controlled by EPROM elements, the device is completely testable. Each programmable EPROM bit controlling the internal logic is tested using application-independent test program patterns. After testing, the devices are erased before shipment to customers. No post-programming tests of the EPROM array are required. Erased-State Configuration The testability and reliability of EPROM-based programmable logic devices is an important feature over similar devices based on fuse technology. Fuse-based programmable logic devices require a user to perform post-programming tests to insure proper programming. These tests must be done at the device level because of the cummulative error effect. For example, a board containing ten devices each possessing a 2% device fallout tram~lates into an 18% fallout at the board level (it should be noted that programming fallout of fuse-based programmable logic devices is typically 2% or higher). The recommended erasure procedure for the SC031 is exposure to shortwave' ultraviolet light with a wavelength of 2S37 A. The integrated dose (Le., UV intensity X exposure time) for erasure should be a minimum of fifteen (1S) Wsec/cm'2. The erasure time with this dosage is approximately 1S to 20 minutes using an ultraviolet lamp with a 12,000 jJ-W/cm 2 power rating. The SC031 should be placed ,within one inch of the lamp tubes during erasure. The maximum integrated dose the SC031 can be exposed to without damage is 7258 Wsec/cm2 (1 week at 12,000 jJ-W/cm 2). Exposure to high intensity UVlight for longer periods may cause permanent damage to the device. DESIGN RECOMMENDATIONS inteligent Programming™ Algorithm To take rnaximum advantage of EPLD technology, it is recommended that the designer use the Modular EPLDLogic Design (MELD) method. The MELD philosophy is derived from the modular programming method used in software development. In a modular software development environment, the engineer designs a modular program (typically on a development system), stores it in memory (EPRO~), and tests the module for functionality. A hardware deSigner using EPLDs can use this, same approach when designing logic. The designer develops a modular logic design on the Intel Programmable Logic Development System II (iPLDS II), stores it in "memory"(the EPROM control elements, of the EPLD), and again tests the module for functionality. If the design is in error, the logic designer reprograms the EPLD with his new design as easily as a software designer can download a new program into memory. The SC031 supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and EPROMs) using an efficient and reliable method. The inteligent Programming Algorithm is particularly suited to the production programming environ- The MELD philosophy is new to programmable logic because EPROM-based PLDs are new. A modular logic development process using fused-based PI:.Ds would be wasteful since a fused-based device cannot be erased an re-used. PROGRAMMING CHARACTERISTICS Initially, and after erasure, all the EPROM control bits of the SC031 are connected (in the "1" state). Each of the connected control bits are selectively disconnected by programming the EPROM cells into their "0" state. Programming voltage and waveform specifications are available by request from Intel to support programming of the SC031. 2-7 inter SC031 For proper operation,it is recommended tha:t all input and output pins be constrained to the voltage range GND < (VIN or Vour) < Vee. Unused inpu:ts should be tied to an appropriate logic level (e.g. either Vee or GND) to minimize device pQwer consumption. Reserved pins (as indicated in the iPLDS REPORT file) should be left floating (no connect) so that the pin can attain the appropriate logic level. A power supply decoupling capaCitor of at least 0.2 p.F must be connected directly between Vee and GND pins of the device. logic, does automatic pin assignments and produces the best design fit for the selected EPLD. It is user friendly with guided menus, on-line Help messages . and soft key inputs. '. In addition, the iPLDS II contains programmer hard· ware in the form of an iUP-PC Universal Programmer-Personal CQmputer to enable the user to program EPLDs, read and verify programmed devices and also to graphically edit programming tiles. The software generates industry standard JEDEC object code output files which can.be downloaded to other programmers as well. DESIGN SECURITY The iPLDS II has interfaces to popular schematic capture packages (including Dash series. from FutureNet* and PC CAPS from PCAD)" to enable designs to be entered using schematics. A more integrated schematic entry method is, provided by SCHEMA II-PLD, a low-cost schematic capture package that supports EPLD primitives and user-defined macro symbols. SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both SCHEMA II-PLD and iPLS II software.· The other design formats supported are Boolean equation entry and State Machine design entry. A single EPROM bit provides a programmable design security feature that controls the access to the data programmed into the device. If this bit is set, a proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control bits, will be reset by erasing the device. . LATCH-UP IMMUNITY The iPLDS operates on the IBMt PC/XT, PC/AT, or other compatible machine with the ,following configuration: All of the input, I/O, and clock pins of the 5C031 have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5C031 is designed with Intel's proprietary CHMOS II-E EPROM process. Thus, each of the 5C031 pins will not experience latch-up with currents up -to 100 mA and voltages ranging from -W to Vee + W; Furthermore, the programming pin is designed to resist latch-up to the 13.5V maximum device limit. 1. At least one floppy disk drive and hard disk drive. 2. MS-DOStt Operating System Version 3.0 or greater. 3. 640K Memory. 4. Intel iUP-PC Universal Programmer-Personal Computer and GUPI Adaptor (supplied with iPLDS). 5. A color monitor is suggested. Detailed information on the Intel Programmable Logic Development System II is contained in a separate Intel data sheet. (Order Number: 280168) ,OFutureNet is a registered trademark of FutureNet Corporation. DASH is a trademark of, FutureNet· Corporation. INTEL PROGRAMMABLE LOGIC DEVELOPMENT SYSTEM II (IPLDS II) The iPLDS II graphically shown in Figure 5 provides all the tools needed to design with Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II insulates the user from having to know all the intricate detailS of EPLD architecture (the machine will optimize a design to benefit from architectual features). It contains comprehensive third generation software that supports four different design entry methods, minimizes "PC-CAPS is a trademark of P-CAD Corporation. tlBM Personal Computer is a registered trademark of International Business Machines Corporation. ttMS-DOS is a registered trademark of Microsoft Corporation. 2-8 5C031 II) ~--------------------------, ~ i Figure 5.IPLDS II Intel Programmable logic Development System 2·9 inter 5C031 • Notice: Stresses above those listed under '~bso lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS· Symbol Min Max Units Vee Supply Voltage(1) Parameter -2.0 7.0 V Vpp Programming Supply Voltage(1) -2.0 13.5 V VI DC Input Voltage(1)(2) -0.5 Vee + 0.5 V t919 Storage Temperature . -65 +150 ·C tamb Ambient Temperature(3) -10 +85 ·C NOTES: 1. Voltages with respect to ground. 2. Minimum DC input is -0.5V. During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns under no load conditions. 3. Under bias. Extended temperature versions are also available. D.C. CHARACTERISTICS TA Symbol = O· to +70·C, Vee = 5V ±5% Parameter/Test Conditions Min Typ Max Unit VIH(4) High Level Input Voltage 2.0 Vee + 0.3 V Vll(4) Low Level Input Voltage -0.3 0.8 V VOH(5) High Level Output Voltage 10 = -4.0 rnA D.C., Vce =; min. VOL Low Level Output Voltage 10 = 4.0 rnA D.C., Vee = min. 0.45 V II Input Leakage Current Vee = max., GND < VOUT < Vee ±10 p..A loz Output Leakage Current Vee = max., GND < VOUT < Vee ±10 p..A Isel6) Output Short Circuit Current Vee = max., VOUT = 0.5V 10' rnA lee Power Supply Current Vee = max., VIN = Vee or GND No Load, Input Freq. = 1 MHz Active mode (Turbo = Off) Device prog. as 8-bit Ctr. 40 rnA V 2.4 15 NOTES: 4. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included. 5.10 at eMOS levels (3.84V) = -2 mA. 6. Not more than 1 output should be fested at a time. Duration of that test must not exceed 1 second. 2-10 5C031 A.C. TESTING LOAD CIRCUIT A.C. TESTING INPUT, OUTPUT WAVEFORM ~=X: >TEST POINTS< 5V INPUT 8554 DEVICE_ OUTPUT- TO TEST SYSTEW 1~-TEST POINTS-~ OUTPUT =~CL (INCLUDES JIG CAPACITANCE) 3414 DEVICE INPUT RISE AND FALL nWES<8ns Ct.. _ - x: 290154-7 A.c. resting: 1npu1s are Driven at 3.0V for a logic "I" and OV for a logic "0". Timing Meaauremen1S are made at 2.OV for a logic "I" and O.BV for a logic "0" on Inputs. Outputs are measured at ~ - a 1.5V point. 290154-8 = 50pF A.C. CHARACTERISTICS TA = O·Cto +70"C, Vee = 5V ±5%, Turbo Bit Programmed(7) Symbol From SC031·40 To Min tpD Typ SC031·50 Max Comb. Output 1/0 Min Typ Unit Max 40 50 ns tpzx(S) I or 1/0 Output Enable 40 50 ns tpxz(S) I or 1/0 Output Disable 40 50 ns teLR Asynch Reset QReset 40 50 ns NOTES: 7. Typical Values are at TA = 2S'C, Vee = SV, Active Mode S. tpzx and tpxz are measured'at ±O.SV from steady state voltage as driven by spec. output load. tpxz is measured with CL - 5 pF. CAPACITANCE Symbol Typ Max Unit 20 pF 20 pF Clock Pin Capacitance = OV, f = 1.0 MHz VOUT = OV, f = 1.0 MHz VOUT = OV, f = 1.0 MHz 20 pF VppPin Pin 11 50 pF Parameter CIN Input Capacitance CaUT Output Capacitance CCLK CvPP Conditions VIN 2·11 Min 5C031 SYNCHRONOUS CLOCK MODEA.C. CHARACTERISTICS TA = c·c to +70·C, vcc = 5.0V ±5%, Turbo Bit On(7) symbol.1 5C031·40 Par$meter Min fMAX Max. Frequency 1/(tCl + teH)- No Feedback fCNT Max. Count Frequency 1/tCNT - With Feedback 22 tsu 110 Setup Time t9 ClK I or 110 Hold after ClK High 30 tH teo Typ 5C031·50 Max 29.5 , Min Typ Unit Max 2~.5 MHz 18 MHz 32 ns 0 0 ' ClK High to Output Valid tCNT Register Outpot Feedback to Register Input - Internal Path tCH elK High Time 17 tel ClKlowTime 17 tSET Synch. Set to Q Set 28 ns 45 55 ns ns 22 ns 22 40 2-12 ns 24 50 ns intJ 5C031 SWITCHING WAVEFORMS COMBINATORIAL MODE INPUT OR I/o COMBINATORIA~ INPUT OUTPUT f~j I---- COMBINATORIAL OR REGISTERED OUTPUT t pxz - I r HIGH IMPEDANCE 3-STATE , I tpzx - ~~ .... HIGH IMPEDANCE 3-STATE VALID OUTPUT tCLR \ \. ASYNCHRONOUSLY CLEAR OUTPUT 290154-8 SYNCHRONOUS CLOCK MODE ClK1 INPUT MAY CHANGE INPUT MAY CHANGE (FROM REGISTER TO OUTPUT} VALID OUTPUT 290154-9 2-13 5C032 300 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE (H-EPLD) • High Performance, Low Power Replacement for 881 • MSI Devices ' and Bipolar PLDa • Eight' MacrOcella with Programmable 1/0 Architecture • 100% Generically Teatable EPROM logic Con,trol Array • High Performance Upgrade for All Commonly Uaed 2O-pln PLDa • CHMOS EPROM Technology Based UV Erasable • ,Up to 18 Inputs (10 Dedicated. 8 1/0) and 8 Outputs • , Programmable "Security 81t" Allowa Total Protection ,of Proprietary Designs • Icc (standby) 100 I'A (max) Icc (10 MHz) 25 mA (max) • tpD = 25ns (max) • 2o-pln 0.3" PlastiC DIP Package (See Packaging Spec•• Order # 281369) , Vee INPUT/CLK INPUT I/O I/O I/O I/O I/O I/O I/O I/O INPUT INPUT INPUT INPUT INPUT GND 11 flVpp 290155-1 Pin Configuration 2·14 November 1887 Order Number: 290155-001 5C032 The Intel 5C032 H-EPLO (H-series Erasable Programmable Logic Device) is capable of implementing over 300 equivalent gates of user-customized logic functions through programming. This device can be used to replace bipolar programmable logic arrays and LS TTL and 74HC (CMOS) SSI and MSI logic devices. The 5C032 can also be used as a direct, low-power replacement for almost all common 20-pin fuse-based programmable logiC devices. With its flexible programmable 1/0 architecture, this device has advanced functional capabilities beyond that of typical programmable logic. ARCHITECTURE DESCRIPTION The architecture of the 5C032 is based on the "Sum of Products" PLA (Programmable Logic Array) structure with a programmable AND array feeding into a fixed OR array. This device can accommodate both combinational and sequential logic functions. A proprietary programmable 1/0 architecture provides individual selection of either combinational or registered output and feedback signals, all with selectable polarity. The 5C032 contains 10 dedicated inputs as well as 8 input/output pins. These 1/0 pins can be individually configured to be inputs, outputs or bi-directionall/O pins. Each of these 1/0 pins is connected to a macrocell. The 5C032 contains 8 identical macrocells organized as shown in Figure 1. The 5C032 H-EPLO uses CHMOS EPROM (floating gate) cells as logic control elements instead of fuses. The CHMOS EPROM technology reduces power consumption of H-EPLOs to less than 20% of a comparable bipolar device without sacrificing speed performance. In addition, the use of Intel's advanced CHMOS H-E EPROM process technology enables greater logic densities to be achieved with superior speed and low-power performance over other comparable devices. Intel's 5C032 has the benefit of "zero" stand-by power not available on other programmable logic devices. EPROM technology allows these devices to be 100% factory tested by programming and erasing all the EPROM logic control elements. Each macrocell (see Figure 2) consists of a PLA (programmable logic array) block and an 1/0 architecture block, which contains a "0" type register. The PLA block consists of eight 36-input AND gates (TRUE & COMPLEMENT of 10 dedicated inputs plus the 8 feedback inputs from the eight macrocells), feeding into an OR gate. The output of this PLA block is fed into the 1/0 architecture block. The different 1/0 and feedback options that are available in the 5C032 1/0 block are shown in Figure 3. The 5C032 with its superior speed and power performance and its plastic package is an ideal production vehicle for high-volume manufacturing. Most commonly used 20-pin bipolar PLOs can be easily replaced with this device allowing for tremendous power consumption savings without saCrificing speed of operation. 2-15 5C032 CLOCK 0 3 5 7 9 11 13 15 17 1921 2325272931 3335 :1 It tIt Il IIf IIf 11 Ir !r11 !i II 11 r ..... :- ;;;-: PLA BLOCK ~I 2 I' I I I I I I I FEEDBACK PLA-BLOCK 3 I I I I PLA BLOCK 4 - I 'I I I I - 'I I I I rI I I - 'I I I I I I I I - I 'l r1 I I I - --1 I I I I I I I I f I/O ARCHITECTURE CONTROL CK I J I PLA BLOCK 9 I/O ARCHITECTURE CONTROL CK I PLA BLOCK 8 I/O ARCHITECTURE CONTROL CK ~ - ~ 16 15 I PLA BLOCK 7 IJ. ARCHlft~RE ~. CONTROL CIC I ~ 18 I "- I, L I I/O ARCHITECTURE CONTROL CK I PLA BLOCK 6 19 I/O ARCHITECTUR£ ~ 17 CONTROL CK . r- PLA BLOCK 5 I I/O' 1--1 ARCHITECTURE . CONTROL ere '/ I ~ I/O ARCHITECTURE CONTROL CK 7 . • ~. 14 ~. 13 ~. 12 1 _1 280165-2 FIgure 1. 6C032 Archltec:!ture 2·16 l CLOCK 3 0 2... 5 4 7 6 9 8 11 10 13 12 17 15 14 16 21 19 18 20 23 22 25 24 27 26 31 29 28 30 33 32 35 34 OE 8J D o ~iil I C 2 ::IE (I) 1X3 DD """""'"" fP D W Va- !I' I!! I\) i . 0 I- g4 CONTROL Cl . o .!.. :. IX ..... iII: Ie CLOCK 1l..5 6 8: I ~ ~~ ~ ~ ~~ ~ ~ ~~ ~~ ~ ~ ~~ ~ ~ ~~ ~ l.j ~ "rl ~~ D 7 .j l 4 l. l,j l 4 l. l,j l,j l. l,j ,j l 4 l.j l.j ,j - l.j -- - _.. NOTE D 11 2 19 3 18 4 17 5 i6 6 =I/O PIN IN WHICH LOGIC ARRAY INPUT IS FROM FEEDBACK PATH 1~ 7 14 8 13 9 L-____________________________________________________- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --JI\L-____________ ~-----------J PLA BLOCK I/O ARCHITECTURE BLOCK 290155-3 i 5C032 DE r-------------------PRODUCT TERMS I/O FEEDBACK L__________________ _ 290155-10 Figure 3. 5C032 1/0 Architecture Control 20 PIN CMOS COMPATIBILITY The 5C032 is architected to be a logical superset of most 20 pin bipolar programmable array logic (PAL·) devices. The 1/0 and logic sections of the 5C032 device can be configured to emulate any of the devices listed below. Designers can make use of this feature by reducing the power of PAL based systems (EPLDs are much lower power), replacing multiple PAL inventory items with a single EPLD. Designers can also create new 20 pin PLD configurations by utilizing the individual logic and. output controls of eacn macrocell. List of PAL devices logically compatible with the 5C032. 10H8 16L2 12H6 16L8 14H4 16R8 16H2 16R6 16H8 16R4 16C1 16P8A 10LB 16RP8A 12L6 16RP6A 14L4 16RP4A ·PAL is a registered trademark of Monolithic Memories, Inc. 2·18 inter 5C032 Prior to programming or after erasing, the 1/0 structure is configured for combinatorial active low output with input (pin) feedback. ment. This method greatly decreases the overall programming time· while programming reliability is ensured as the incremental program margin of each bit is continually monitored to determine when the bit has been successfully programmed. ERASURE CHARACTERISTICS FUNCTIONAL TESTING Erasure characteristics of the 5C032 are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000A. It should be noted that sunlight and certain types of flourescent lamps have wavelengths in the 30004000A. Data shows that constant exposure to room level flourescent lighting could erase the typical 5C032 in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the 5C032 is to be exposed to these types of lighting conditions for extended periods of time, conductive opaque labels should be placed over the, device window to prevent unintentional erasure. Since the logical operation of the 5C032 is controlled by EPROM elements, the device is completely testable. Each programmable EPROM bit controlling the internal logic is tested using application-independent test program patterns. After testing, the devices are erased before shipment to customers. No post-programming tests of the EPROM array are required. Erased-State Configuration The testability and reliability of EPROM-based programmable logic devices is an important feature over similar devices based on fuse technology. Fuse-based programmable logic devices require a user to perform post-programming tests to insure proper programming. These tests must be done at the device level because of the cummulative error effect. For example, a board containing ten devices each possessing a 2% device fallout translates into an 18% fallout at the board level (it should be noted that programming fallout of fuse-based programmable logic devices is typically 2% or higher). The recommended erasure procedure for the 5C032 is exposure to shortwave ultraviolet light with a wavelength of 2537A. The integrated dose (Le., UV intensity x exposure time) for erasure should be a minimum of fifteen (15) Wsec/cm 2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 /JoW/cm 2 power rating. The 5C032 should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose the 5C032 can be exposed to without damage is 7258 Wsec/cm 2 (1 week at 12,000 /JoW/cm 2). Exposure to high intensity UV light for longer periods may cause permanent damage to the device. DESIGN RECOMMENDATIONS Inteligent Programmlng™ Algorithm To take maximum advantage of EPLD technology, it is recommended that the designer use the Modular EPLDLogic Design (MELD) method. The MELD philosophy is derived from the modular programming method used in software development. In a modular software development environment, the engineer designs a modular program (typically on a development system), stores it in memory (EPROM), and tests the module for functionality. A hardware deSigner using EPLDs can use this same approach when designing logic. The deSigner develops a modular logic design on the Intel Programmable Logic Development System II (iPLDS II), stores it in "memory" (the EPROM control elements of the EPLD), and again tests the module for functionality. If the design is in error, the logic designer reprograms the EPLD with his new design as easily as a software designer can download a new program into memory. The 5C032 supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and EPROMs) using an efficient and reliable method. The inteligent Programming Algorithm is particularly suited to the production programming environ- The MELD philosophy is new to programmable logic because EPROM-based PLDs are new. A modular logic development process using fused-based PLDs would be wasteful since a fused-based device cannot be erased an re-used. PROGRAMMING CHARACTERISTICS Initially, .and after erasure, all the EPROM control bits of the 5C032 are connected (in the "1" state). Each of the connected control bits are selectively disconnected by programming the EPROM cells into their "0" state. Programming voltage and waveform specifications are available by request from Intel to support programming of the device. 2-19 5C032 For proper operation,it is recommended that all input and output pins be constrained to the voltage range GND. < (V,N or VOUT) < Vee. Unused inputs should be tied to an appropriate logic level (e.g. ei-. ther Vee or GND) to minimize device power con· sumption. Reserved pins (as indicated in the iPLDS REPORT file) should be left floating (no connect) so that the pin can attain the appropriate logic level. A power supply decoupling capacitor of at least 0.2 p,F must be connected directly between Vee and GND pins of the device. . logiC, does automatic pin asSignments and produces the best design fit for the selected EPLD. It is Liser friendly with guided menus, on-line Help messages and.softkey inputs. In addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices and· also to graphically edit programming files. The software generates· industry standard JEDEC object code output files which can be downloaded to other programmers as well. DESIGN SECURITY The iPLDS II has interfaces to popular schematic capture packages (including Dash series from FutureNet* and PC CAPS from PCAD) * • to enable designs to be entered using schematics. A more integrated schematic entry method is provided by SCHEMA II-PLD, a tow-cost schematic capture package that supports EPLD primitives and user-defined macro symbols. SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both SCHEMA II-PLD and iPLS II software. The other design formats supported are Boolean equation entry and State Machine design entry. A single EPROM· bit provides a programmable design security feature that controls the access to the data programmed into the device. If this bit is set, a proprietary design within the device cannot be copied .. This EPROM security bit enables a higher degree of design security than fused-based devices since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control bits, wi~1 be reset by erasing the device; LATCH-UP IMMUNITY TheiPLDS operates on the IBMt PC/XT, PCI AT, or other compatible machine with the following configu" ration: All of the input, 1/0, and clock pins of the SC032 have been designed to resist latch-up which is inherent in inferior CMOS structures. The SC032 is designed with Intel's proprietary·CHMOS II-E EPROM process. Thus, each of the SC032 pins will not experience latch-up with· currents up to 100 mA and volt· ages ranging from -W to Vee + 1V. Furthermore, the programming pin is designed to resist latch-up to the 13.SV maximum device limit. 1. At least one floppy disk drive and hard disk drive. 2. MS-DOStt Operating System Version 3.0 or greater. 3. 640K Memory. 4. Intel iUP-PC Universal Programmer-Personal Computer and GUPI Adaptor (supplied with iPLDS II). S. A color monitor is suggested. INTEL PROGRAMMABLE LOGIC DEVELOPMENT SYSTEM II (IPLDS II) Detailed information on the Intel Programmable Logic Development System II is contained in a separate Intel data sheet. (Order Number: 280168) The iPLDS II graphically shown in Figure S provides all the tools needed to design with Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II insulates the user from having to know all the intricate details of EPLD architecture (the machine will optimize a design to benefit from architectual features). It contains comprehensive third generation software that sup· ports four different design entry methods, minimizes *FutureNet is a registered trademark of FutureNet Corporation. DASH is a trademark of FutureNet Corporation. "PC-CAPS is a trademark of P-CAD Corporation. tlBM Personal Computer is a registered trademark of International Business Machines Corporation. ttMS-DOS is a registered trademark of Microsoft Corporation. 2-20 5C032 Figure 5. IPLDS II Intel Programmable Logic Development System 2-21 5C032 • Notice: Stresses above those listed under ':4bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS'" Parameter Symbol Min Max Unit Vee Supply Voltage(l) -2.0 7.0 V Vpp Programming Supply Voltage(l) -2.0 13.5 V VI DC Input Voltage(1)(2) -0.5 Vee + 0.5 V tsta Storage Temperature -65 +150 ·C tamb Ambient Temperature(4) -10 +85 ·C NOTES: 1. Voltages with respect to ground. 2. Minimum DC input is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns under no load conditions. 3. Under bias, Extended temperature versions are also available. 4. Extended temperature versions also available. D.C. CHARACTERISTICS Symbol TA = O·C to 70"C, Vee ParameterlTest Conditions = 5V ± 5% Min VIH(5) High Level Input Voltage 2.0 VIL(5) Low Level Input Voltage -0.3 VOH(6) High Level Output Voltage 10 = -4.0 mA D.C., Vee. = min. VOL Low Level Output Voltage 10 = 4.0 mA D.C., Vee = min. Typ Max Vec + 0.3 0.8 2.4 Unit V V V 0.45 -V II _Input Leakage Current Vee = max., GND < VOUT- < Vee ±10 p.A loz Output Leakage Current Vee = max., GND < VOUT < Vcc ±10 p.A Ise(7) Output Short Circuit Current Vee = max., VOUT = 0.5V 10 mA ISB(8) Standby Current Vce = max., VIN = Vee or GND, Standby Mode 10 100 p.A lee(9) Power Supply Current Vee = max., VIN = Vcc or GND, No Load, Input Freq. = 10 MHz Active Mode (Turbo =. Off), Device Prog. as 8-bit Ctr. 15 25 mA NOTES: 5. Absolute values with respect to device GNO; all over- and' undershoots due to system or tester noise are included. 6.10 at CMOS levels (3.84V) = -2 mAo 7. Not more than 1 output should be tested ata time. Duration of that test must not exceed 1 second, 8. With Turbo Bit = Off, device automatically enters lItandby mode approximately 100 ns after last input transition. 9. Maximum Active Current at operational frequency is less than 40 mAo 2-22 inter 5C032 A.C. TESTING LOAD CIRCUIT A.C. TESTING INPUT, OUTPUT WAVEFORM .----5V 3JJ-yUJ o..AO.8 >TEST POINTS< INPUT ViE ~ 855.0. r:::--+-4--C> SYSTE~ TO TEST DEVICE OUTPUTL 1~-TEST POINTS-~ OUTPUT 290155-7 341.0. A.C. Testing: Inputs are Driven at 3.0V for a logic "1" and OV for a logic "0". Timing Measurements are made at 2.0V for a logic "1" and O.BV for a logic "0" on Inputs. Outputs are measured at a 1.5V point. DEVICE INPUT RISE AND fAll TI~ES < 6 ns 290155-6 A.C. CHARACTERISTICS Symbol From TA = O·C to + 70·C, VCC = 5V ± 5%, Turbo Bit On(10) 5C032-25 To 5C032-30 5C032-35 Unit Min Typ Max Min Typ Max tpD lorl/O Comb. Output 25 30 tpZX(ll) lorl/O Output Enable 25 tpXZ(ll) lorl/O Output Disable 25 Min Typ Max 35 ns 30 35 ns 30 35 ns NOTES: 10. Typ. values are at TA = 25°C, Vee = 5V, Active Mode. 11. tpzx and tpxz are measured at ±0.5V from steady state voltage as driven by spec. output load. tpxz is measured with Cl = 5 pF. CAPACITANCE Symbol Parameter Conditions CIN Input Capacitance VIN =' OV, f COUT Output Capacitance VOUT CCLK Clock Pin Capacitance CVpp(12) Vpp Pin VOUT = = = OV, f OV, f NOTE: 12. Vpp is on Pin 11. 2-23 Min Typ Max Unit 1.0 MHz 20 pF = = 1.0 MHz 20 pF 1.0 MHz 20 pF 50 pF 5C032 A.C.. CHARACTERISTICS ,rA =. O·C to70·C, Vcc = 5V ± 5%, Turbo Bit On (10) SYNCHRONOUS CLOCK MODE Symbol 5C032·30 5C032·25 Parameter Min Typ Max Min Typ SC032·35 Max Min Typ Unit Max tMAX Max. Frequency 1/tsu - No Feedback 47.6 43.5 40 MHz tCNT Max. Count Frequency 1 /teNT - with Feedback 33.3 28.5 25 MHz tsu Input Setup Time to CLK 21 23 25 ns tH I or 1/0 Hold after CLK High tco CLK High to Output Valid 16 17 20 ns tCNT Register Output Feedback to Register Input - Internal Path 30 35 40 ns tCH CLK High Time 10 11 12 ns tCL CLKLowTime 10 11 12 ns 0 2-24 ns 0 0 5C032 SWITCHING WAVEFORMS COMeINATOIIlIAL MODE INPUT OR I/O INPUT COMBINATORIAL OUTPUT COMBINATORIAL OR ~~]..------!---tpxz I '/~ ____________________________ J REGISTERED OUTPUT HIGH IMPEDANCE 3-STATE ______~H~IG~H~IM~P~E~DA~N~C~E_________ 3- STATE ~~,,~------~ VALID OUTPUT 290155-8 " SYNCHRONOUS CLOCK MODE CLK! INPUT MAY CHANGE INPUT MAY CHANGE (FROM REGISTER TO OUTPUT) VALID OUTPUT 290155-9 2·25 inter 5C032 Current in Relation to Frequency Current In Relatl on to Temperature 50 50 40 40 ~ 30 ] 20 E lURB~V V ./ V "" ~ E ] >;", 10 r-- 30 20 10 ~NON-TURBO 0 0 0 5 20 0 10 15 20 25 30 35 40 = O'C, Vee = , 40 60 80 85 TEMP(C) fCNr;;: :::> '" ": ~~ .... c..> ~ ~ ~~ 1= ClKl Vee INPUT1 1/0.15 INPUT4 1/0.1 1/0.14 1/0.16 1/0.15 1/0.13 1/0.3 1/0.14 1/0.12 1/0.4 1/0.13 1/0.5 1/0.12 1/0.7 1/0.11 NC 21 1/0.2 1/0.6 1/0.7 1/0.8 INPUT2 GND 9 1/0.11 1/0.10 Ne 1/0.10 1/0.9 cq ~ - ~ ~:::> INPUT3 CLK2 c c ~ ~ f::! ~ Si:::>~"! 290104-28 290104-1 5C060 Pin Configurations 2-27 November 1987 Order Number: 290104-005 5C060/5C090 ., vCc ' elKl INPUT1 IN~UH2' INPUT2 INPUTll INPUT10 INPUT3 1/0.1 1/0.2, 1/0.2 1/0.3 ' 1/0.4 1/0.5 1/0.6 1/0.7 1/0.8 1/0.9 1/0.10 1/0.11 1/0.24 6 1/0.23 , 1/0.22 1/0.21 I/Q.20 1/0.6 1/0.19 1/0.7 1/0.18 ,1/0.8 1/0.17 1/0.9 1/0.16' 1/0.10 1/0.15 1/0.11 1/0.14 1/0.12 1/0.13 INPUT4 INPUTe INPUTS INPUT8 INPUT6 INPUT7 Ne NC 1/0.23 1/0.22 1/0;21 I/o.~o '1/0.19 ' 1/0.18, 1/0.17 1/0.16 1/0.15 1/0.14 GND ,290104-2 SC090 Pin Configurations The Intel 5C060 and 5C090 H-EPLDs (H-series Progr'ammabllll Logic Devices) are capable of implementing over 600 and 900 respectively of equivalent gates of user-customized logic, functions through programming. Both devices can be used, to replace low-end gate arrays, multiple programmable logic arrays and LS TIL and 74HC (CMOS), SSI and MSI logic devices. The 5C060 can also be used as a direct, low-power replacement for most, common 24-pin fuse-based programmable logic devices. With their revolutionary programmable 110 architecture, both devices have advanced functional capabilities beyond that of typical programmable logic. The erasability of EPLDs introduces the designer to' a new concept in hardware design 'called Modular EPLD Logic Design (MELD). Just as modular software design speeds development time and reduces errors by isolating the~ to. a specific module, ~he, MELD philosophy aids in hardware deSign. Adesigner can develop his modular design on the Intel Programmable Logic Dljlvelopment System II (iPLDS II) and test individual modules for functionality. If one of the modules has a design flaw, the designer' merely erases the part and starts anew (since the 5C060 and 5C090 are EPROM-based, there is no waste associated with modular design as there would be in fuse-based PLDs). The 5C060 and 5C090 H-EPLDs use CHMOS EPROM (floating gate) cells as logic control elements instead of fuses. The CHMOS,EPROM technology reduces power consumption of H-EPLDs to less than 20% of a comparable bipolar device without sacrificing speed performance. In addition, Intel's advanced CHMOS II-E EPROM ,process technology enables greater logic densities to be achieved with' superior speed and low-power performance over other comparable devices. Intel's H-ELPDs add the benefits of "zero" stand-by power not available on other pr~ra~mable logic devices. EPROM technology allows these devices to be 100% factory tested. by programming and erasing all the EPROM logic control elements. The architecture of the 5C060 and 5C090 is based on the "Sum of Products" PLA (Programmable Logic Array) structure with a programmable AND array feeding into a fixed OR array. Both devices accomodate combinational and sequential logic functions. A proprietary programmable 110' architecture provides individual selection of either combinatorial or registered output and feedback signals all with selectable polarity. A feature unique to the 5C060 ana SC090 is the ability to individually program the output registers as a D-, T-, SR-, or JK~type Flip-Flop without sacrificing the utilization 'of programmable AND logic. Additionally, each output register can be individually clocked from any of the input or feedback paths available 2-28 intJ 5C060/5C090 within the AND array. With these features, a wide variety of logic functions can be simultaneously implemented-ali on the same device. ARCHITECTURE DESCRIPTION Externally, the 5C060 has 4 dedicated data input pins, 16 I/O pins which may be configured for input, output, or bidirectional operations. and 2 synchronous clock inputs. The 5C060 is contained in a 24-pin windowed package (0.3 inch wide), and contains 16 programmable registers. The 5C090 represents a superset of the 5C060 in capability. The 5C090 has 12 dedicated inputs, 24 1/0 pins which may be configured for input, output, or bidirectional operations, and 2 synchronous clock inputs. The 5C090 is packaged in a 40-lead windowed ceramic DIP and contains 24 programmable registers. AND ARRAY / The basic Macrocell architecture for both the 5C060 and 5C090 is shown in Figure 1. The 5C060 has 16 of these Macrocells while the 5C090 has 24 (one for each 1/0 pin). The Macrocell is organized in the familiar sum-of-products structure with a programmable AND array attached to a fixed OR term. The inputs to the programmable AND array originate from the true and complement signals from each of the dedicated input pins and each of the 1/0 control blocks. The 40-input AND array of the 5C060 feeds 160 AND gates (product terms) which are distributed among the 16 available Macrocells within that device. The AND array for the 5C090 has 72 inputs derived from the true and complement signals at the input and 1/0 pins. The AND array in the 5C090 encompasses 240 product terms which are distributed among the 24 Macrocells. The global device architectures are shown in Figure 2. SYNCHRONOUS ClOCK vee OE/ClK l-'-:ELECT OE - OE/ClK D- Ii '-- • 8= EPROM CONTROL BIT II \ 8= 8= 8= ClK OUTPUT REGISTER ~ OUTPUT BUFFER ~ ~ ~ ~ j ~ ~ j INPUTS AND I/O ~ ~ ~ ~REGISTER FEEDBACK I 290104-3 Figure 1. Basic Macrocell Architecture of the 5C060 and 5C090 2-29 SC060/SC090 DEDICATED DEDICATED INPUTS INPUTS 50090 • 24 Macrocells • 12 Dedicated Inputs 5C06O • 16 Macrocells • 4 DedIcated Inputs MACROCELLS MACROCELLS I/O •• • AND RRAY I/o • • • I/O 290104-4 Figure 2. SC060 and Se090 Global Architecture 2-30 inter 5C060/5C090 none to all). Both of the dedicated clock inputs latch the data into a given register when triggered on a positive edge. The Macrocells on both devices contain ten product terms total. Eight of the ten product terms (AND gates) are dedicated for logic implementation. One product term on each Macrocell is used for RESET control to the output register associated with the Macrocell. The final product term is used for OUTPUT ENABLE/Asynchronous Clock implementation. MACROCELL ARCHITECTURE SELECTION Within the AND array, there is an EPROM connection at every intersection of an input signal (true and complement) and a product term to a given Macrocell. Before programming an erased device, every EPROM connection is made at every intersection. But during the programming process, these connections are opened so that only the desired connections remain.' Therefore, the true or complement of any input signal can be connected to any product term. If both the true and complement connections of any signal are left intact, a logical false results on the output of the AND gate. However, if both the true and complement connections are open, then a logic "don't care" results on the AND gate. Lastly, if all the inputs of a product term are programmed open, then a logical true results on the output of the AND gate. The 5C060 and 5C090 architecture provides each Macrocell with over 50 different possible I/O register configurations. Each I/O pin can be configured for combinatorial or registered output (true or complement) with feedback. In addition, four different types of output registers can be implemented into every I/O pin without any additional logic requirements. The feedback mechanism for each register back into the AND array can be programmed to provide for either registered feedback from the Macrocell or input feedback (treating the pin as an input). Another advantage of the advanced I/O capability of the 5C060 and the 5C090 is the ability to individually clock each internal register from asynchronous clock signals. Output Enable (OE)/Clock Selection Both the 5C060 and 5C090 have two dedicated clock inputs to provide synchronous clock signals to the internal registers. Each of the clock signals controls half the total registers within the given device. For example, CLK1 provides synchronous clocking to the registers in Macrocells in the left half of the array while CLK2 controls the registers associated with Macrocells in the right half of the array. The advanced I/O architecture allows for any number of the registers to be synchronously clocked (from Two modes of operation are provided by the OE/CLK Select Multiplexer as a part of each Macro~ cell. One mode provides for three-state buffering of outputs while in the other mode, the outputs are always enabled. The operation of the OE/CLK Select Multiplexer sets the mode within a given Macrocell. Therefore, the output mode can be selected individually on every output. Figure 3 illustrates the two modes of OE/CLK operation. 2-31 inter 5C060/5C090 SYNCHRONOUS CLOCK VCC OE/CLK SELECT OE CLK - SYNCHRONOUS CLK OE-P-TERW CONTROLLED OUTPUT REGISTER OUTPUT BUFFER 290104-5 . MODE 0 SYNCHRONOUS CLOCK, VCC OE/CLK SELECT OE CLK - ASYNCHRONOUS CLK OE-ENABLED OUTPUT REGISTER OUTPUT BUFFER 290104-6 MODE 1 Figure 3. Output Enable/Clock Configuration 2·32 inter 5C060/5C090 dently configured. In addition, all registers have an individual asynchronous RESET control from a dedicated product term derived in the AND array. When this dedicated product term is a logical one, the Macrocell register is immediately cleared to a logical zero independent of the register clock. The RESET function occurs automatically on power-up. MODE 0: THREE-STATE BUFFERING In Mode 0, the three-state output buffer is controlled by a single product term originating from the AND array. The output is enabled when the product term is a logical true. Conversely, the output appears as high impedance when the product term is a logical false as shown in Table 1. In Mode 0, the Macrocell Flip-Flop is connected to its associated synchronous clock (either ClK1 or ClK2 depending upon the MacroceU's location within the device). Thus, the Macrocell Flip-Flop may be clocked by its respective synchronous clock but its output will not become valid until the output is enabled. Output Register Configuration The four different register types shown in Figure 4 are described below. D- or T-type Flip-Flops Table 1. Mode 0 Output Selection Product Term Output Buffer FALSE Three-State TRUE Enabled When either a D- or T-type Flip-Flop is configured as part of the I/O structure, all eight of the product terms into the Macrocell are ORed together and fed into the register input. JK or SR Registers MODE 1: OUTPUT BUFFER ENABLED When either a JK or SR register is configured, the eight product terms are shared among two OR gates (one for the J or S input and the other for the K or R input). The allocation for these product terms for each of the register inputs is optimized by the iPlDS II development software. In Mode 1, the Output Buffer is always enabled. In addition, the Macrocell Flip-Flop is connected to the AND array. The Macrocell Flip-Flop may now be triggered from an asynchronous clock signal generated by the AND array logiC to the OE/ClK multiplexable term. Mode 1 allows the Macrocell Flip-Flops to be individually clocked from any of the available signals in the AND array. Since both true and complement values appear in the AND array, the Flip-Flop may be configured to trigger on positive or negative clock edges. Gated clock structures can be created since the Flip-Flop clock is created by a product term. OUTPUTIFEEDBACK The Output Select Multiplexer allows for either registered, combinatorial or no output. The Feedback Select Multiplexer E~ROM bit enables registered, I/O (using the pin for bidirectional input or just input), or no feedback to the AND array. Invert Select EPROM Bit The Feedback Select is also important for building product terms with more than 8 products. The aproduct product term of a Macrocell can be fed back into the AND array and combined with still more signals to create a much larger product term (of more than a-inputs). In addition, if the feedback product term is not to be output, then the iPlDS " will reserve the associated Macrocell pin and indicate it in the REPORT file. A reserved pin should be left floating (no connect) when assembled onto a circuit board. The Invert Select EPROM bit is used to invert the product term input into the register. This applies to all inputs including double inputs on the JK and SR registers. REGISTER SELECTION The advanced I/O architecture of the SCOSO and the SC090 allows four different register types along with combinatorial output as illustrated in Figure 4. The register tYpes include a T, D, JK, or SR Flip-Flop and each Macrocell I/O structure may be indepen- Any 1/0 pin may be configured as a dedicated input by selecting no output and pin feedback through the appropriate multiplexers. 2-33 inter 5C060/5C090 1/0 SELECTION OUTPUTIPOLARITY FEEDBACK Combinatorial/High Combinatorial/Low None Pin, None Pin, None Pin 290104-7 Figure 4a_ Combinatorial 1/0 Configuration 1/0 SEI,.ECTION OUTPUTI FEEDBACK POLARITY SYNCHRONOUS CLOCK vee D-Register /High D-Register/Low None None D-Register, Pin, None D-Register, Pin, None D-Registered , Pin FUNCTION TABLE D On On+ 1 0 0 1 1 0 1 0 1 0 0 1 1 290104-8 Figure 4b. D-Type Flip-Flop Register Configuration 2-34 intJ 5C060/5C090 SYNCHRONOUS I/O SELECTION a.0C1< va: OUTPUTIPOLARITY FEEDBACK T-Reglster/High T-Register/Low None None T-Reglster, Pin, None T-Reglster, Pin, None T-Register Pin FUNCTION TABLE Qn T Qn + 1 0 0 1 1 0 1 0 1 0 1 1 0 290104-9 Figure 4c_ Toggle Flip-Flop Register Configuration I/O SELECTION SYNCHRONOUS MCK vee ~~~~ 0' eLK OUTPUT/POLARITY FEEDBACK JK Register/High JK Register/Low None JK Register, None JK Register, None JK Register FUNCTION TABLE K Qn Qn + 1 J 0 0 0 0 1 1 1 1 Figure 4d. JK Flip-Flop Register Configuration 2-35 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 5C060/5C090 SYNCHRONOUS' I/O SELECTION CLOCK VCC OE OUTPUT/POLARITY FEEDBACK SR Register/High SR RegisteriLow None SR Register, None SR Register, None SR Register FUNCTION TABLE ClK S R On On + 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 Illegal -I--I Q .......... 8-N INVERT SELECT 290104-11 Figure 4e. SR Flip-Flop Register Configuration 4oooA. It should be noted that sunlight and certain Erased-State Configuration types of flourescent lamps have wavelengths in the 3000-400oA. Data shows that constant exposure to room level flourescent lighting could erase the typical device in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the 5C060 or the 5C090 is to be exposed to these types of lighting conditions for extended periods of time, conductive opaque labels should be placed over the device window to prevent unintentional erasure. Prior to programming'or after erasing, the I/O structure is configured for combinatorial active low output with input (pin) feedback. ERASURE CHARACTERISTICS Erasure characteristics of the 5C060 and 5C090 are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 2-36 inter 5C060/5C090 The recommended erasure procedure for the 5C060 and 5C090 is exposure to shortwave ultraviolet light with a wavelength of 2537A. The integrated dose (Le., UV intensity x exposure time) for erasure should be a minimum of fifteen (15) Wsec/cm 2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 p.W/cm 2 power rating. The 5C060 or 5C090 should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose the 5C060 or 5C090 can be exposed to without damage is 7258 Wsec/cm2 (1 week at 12,000 p.W/cm2). Exposure to high intensity UV light for longer periods may cause permanent damage to the device. PROGRAMMING CHARACTERISTICS Initially, and after erasure, all the EPROM control bits of the 5C060 and 5C090 are connected (in the "1" state). Each of the connected control bits are selectively disconnected by programming· the EPROM cells into their "0" state. Programming voltage and waveform specifications are available by request from Intel to support programming of the 5C060 and 5C090. The testability and reliability of EPROM-based pro" grammable logiC devices is an important feature over similar devices based on fuse technology. Fuse-based programmable logic devices require a user to perform post-programming tests to insure proper programming. These tests must be done at the device level because of the cummulative error effect. For example, a board containing ten devices each possessing a 2% device fallout translates into an 18% fallout at the board level (it should be noted that programming fallout of fuse-based programmable logiC devices is typically 2% or higher). To enable functional evaluation of counter and state-machine applications, the 5C060 and 5C090 contain register pre-load circuitry. This can be activated by interrupting the normal clocked sequence and applying Vpp on pin 11 for the 5C060 or pin 17 for the 5C090 to engage the pre-load state. Under these conditions, the Flip-Flops in the 5C060 and 5C090 can be set to any logical condition and then return to normal operation. This process simplifies the input sequences necessary to evaluate the . counter and state machine operations. DESIGN RECOMMENDATIONS inteligent Programming™ Algorithm To take maximum advantage of EPLD technology, it is recommended that the deSigner use the Modular EPLD Logic Design (MELD) method. The MELD philosophy is derived from the modular programming method used in software development. In a modular software development environment, the engineer designs a modular program (typically on a development system), stores it in memory (EPROM), and tests the module for functionality. A hardware designer using EPLDs can use this same approach when designing logic. The designer develops a modular logic design on the Intel Programmable Logic Development System II (iPLDS II), stores it in "memory" (the EPROM control elements of the EPLD), and again tests the module for functionality. If the design is in error, the logic deSigner reprograms the EPLD with his new design as easily asa software designer can download a new program into memory. Both the 5C060 .and 5C090 support the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and EPROMs) using an efficient and reliable method. The inteligent Programming Algorithm is particularly suited to the production programming environment. This method greatly decreases the overall programming time while programming reliability is ensured as the incremental program margin of each bit is continually monitored to determine when the bit has been successfully programmed. FUNCTIONAL TESTING Since the logical operation of the 5C060 and 5C090 are controlled. by EPROM elements, the device is complete!y testable. Each programmable EPROM bit controlling the internal logic is tested using application-independent test program patterns. After testing, the devices are erased before shipment to customers. No post-programming tests of the EPROM array are required. The MELD philosophy is new to programmable logic because EPROM-based PLDs are new. A modular logic development process using fused-based PLDs would be wasteful since a fused-based device cannot be erased an re-used. 2-37 5C060/5C090 For proper operation, it is recommended that all input and output pins be constrained to the voltage range GND < (YIN or Vour) < Vee. Unused inputs should be tied to an appropriate logic level (e.g. either Vee or GND) to minimize device power consumption. Reserved pins (as indicated in the iPLDS II REPORT file) should be left floating (no connect) so that the pin can attain the appropriate logic level. A power supply decoupling capacitor of at least 0.2 ,...F must be connected directly between Vcc and GND pins of the 5C060 and the 5C090. DESIGN SECURITY A single EPROM bit provides a programmable design security feature that controls the access' to the data programmed into the device. If this bit is set, a proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control bits, will be reset by erasing the device. the best design fit for the selected EPLD. It is user friendly with guided menus, on-line Help messages and soft key inputs. In addition, the IPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer Personal Computer to enable the user to program EPLDs, read and verify programmed devices and also to graphically edit programming files. The software generates industry standard JEDEC object code output files which can be downloaded to other programmers as well. The iPLDS II has interfaces to popular schematic capture packages (including Dash series from FutureNetO and PC CAPS from PCAD)·· to enable designs to be entered using schematics. A more integrated schematic entry method is provided by SCHEMA II-PLD, a low-cost schematic capture package that supports EPLD primitives and user-de·fined macro symbols. SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both SCHEMA II-PLD and iPLS II software.The other design formats supported are Boolean equation entry and State Machine design entry. The iPLDS II operates on the IBMt PC/XT, PC/AT, or other compatible machine with the following configuration: 1. At least one floppy disk drive and hard disk drive. 2. ,MS-DOStt Operating System Version ~.O or ,greater. , 3. 640K Memory. 4. Intel iUP-PC Universal Programmer Personal Computer and GUPI Adaptor (supplied with iPLDS II). 5. A color monitor is suggested. LATCH-UP IMMUNITY All of the input, 110, and clock pins of the 5C060 and 5C090 have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5C060 and 5C090 are designed with Intel's proprietary CHMOS II-E EPROM process. Thus, each of the 5C060 and 5C090 pins will not experience latch-up with currents up to 100 mA and voltages ranging from -W to Vee + W. Furthermore, the programming pin is designed to resist latch-up to the 13.5V maximum device limit. Detailed information on the Intel Programmable Logic Development System II is contained in a separate Intel data sheet. (Order Number: 280168) INTEL PROGRAMMABLE LOGIC DEVELOPMENT SYSTEM II (IPLDS II) °FutureNet is a registered trademark of FutureNet Corporation. DASH is a trademark of FutureNet Corporation. The iPLDS II graphically shown in Figure 5 provides all the tools needed to design with Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II insulates the user from having to know all the intricate details ,of EPLD architecture (the machine will optimize a design to benefit from architectual features). It contains comprehensive third generation software that supports four different design entry methods, minimizes logic, does automatic pin assignments and produces • ° PC-CAPS is a trademark of P-CAD Corporation. 'tIBM Personal Computer is a registered trademark of International Business Machines Corporation, ttMS-DOS is a registered trademark of Microsoft Corporation. 2-38 l "1'1 i6 c i PI Intel Programmable Logic Development System II 5' it ~ ID ; :I :I .,. II ii' 1) ~'9. Co) CI) ....... _ ELl'O ~ n ~ I..... i C CD < f "a :I CD :lI .... en 1:I = -== 'V rc en -290104-12 5C060/5C090 ABSOLUTE MAXIMUM RATINGS· Symbol Parameter Min Max Units Vee Supply Voltage(1) -2.0 7.0 V Vpp Programming Supply Voltage(1) -2.0 13.5 V VI DC Input Voltage(1 )(2) -0.5 Vee + 0.5 V t 8 1g Storage Temperature -65 +150 ·c tamb Ambient Temperature(S) -10 +85 ·C "Notice: Stresses above those listed under ':4bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operstional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTES: 1. Voltages with respect to ground. 2. Minimum DC input is -0.5V. During transitions, the Inputs may undershoot to - 2.0V for periods less than 20 ns under no load conditions. 3. Under bias. Extended temperature versions are also available. D.C. CHARACTERISTICS TA = O·C to 70·C, Vee = 5.0V ± 5% Symbol Parameter VIH(4) HIGH Level Input Voltage VIL(4) LOW Level Input Voltage VOH(5) HIGH Level Output Voltage Min Typ Conditions 2.0 = -4.0 rnA DC, Vee = Min. + O.S 0.8 2.4 VOL LOW Level Output Voltage II Input Leakage Current loz IsC<6) Output Leakage Current = 4.0 mA DC, Vee = Min. = Max., GND < VOUT < Vee Vee = Max., GND < VOUT < Vce Output Short Circuit Current Vee Ise(7) Standby Current 5C060 (Standby) Vee -0.3 10 Max V V V 10 Vec = Max., VOUT = 0.5V Vee = Max., Unit 0.45 V ±10.0 p,A ±10.0 jLA rnA 50 100 p,A 10 15 rnA 50 100 p,A 15 25 rnA VIN = Vee or GND Power Supply Current Icc 5C060 (Active) (Turbo Bit Off) Device Prog. as 16-Bit Ctr. No Load, Vce = Max., VIN = Vce or GND Input Freq. Ise(7) Standby Current 5C090 (Standby) Vce = Max., VIN = Vec or GND Power Supply Current No Load, Vee = Max., Icc 5C090 (Active) (Turbo Bit Off) VIN = Vec or GND Input Freq. Device Prog. as Two 12-Bit Ctrs. = 1 MHz = 1 MHz NOTES: 4. Absolu1e values with raspect to device GND; all over and undershoots due to system or tester nOise are inCluded. 5.10 at CMOS levels (3.84V) = -2 mA. 6. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second. 7. With Turbo Bit Off, device automatically enters standby mode approximately 100 ns after last inpu1 transition. 2-40 5C060/5C090 A.C. TESTING LOAD CIRCUIT A.C. TESTING INPUT, OUTPUT WAVEFORM 5V 3.0](20 INPUT DEVICE OUTPUT o C-+-.....-C> TO TEST SYSTEM 341.1l • ~~ > O· ~ l~-TEST P O I N T S - E OUTPUT 290104-14 DEVICE INPUT RISE AND FALL TIMES < 6nS A.C. Testing: Inputs are Driven at 3.0V for a Logic "1" and OV for a Logic "0". Timing Measurements are made at 2.0V for a Logic "1" and O.BV for a Logic "0" on inputs. Outputs are measured at a 1.5V point. 290104-13 A.C. CHARACTERISTICS TA = O·C to 70·C, Vcc = 5V ± 5%, Turbo Bit On(8) Device Symbol From -< .~20 TEST POINTS To SCOSo-4S SCOSO-SS SC090-S0 SC09O-S0 Min Typ Max Min Typ Max Min Typ Max Min Typ Max Non-(10) Turbo Unit Mode tpD1 Input Comb. Output 43 53 46 55 +25 ns tpD2 I/O Comb. Output 45 55 50 60 +25 ns tpZX(9) I or I/O Output Enable 45 55 50 60 +25 ns tpxz(9) I or I/O Output Disable 45 55 50 60 +25 ns telR Asynch. Q Reset Reset 45 55 50 60 +25 ns NOTES: 8. Typical Values are at TA = 2SoC, Vee = SV, Active Mode. 9. tpzx and tpxz are measured at ± O.SV from steady state voltage as driven by spec. output load. tpxz is measured with CL = S pF. 10. If device is operated with Turbo Bit Off (Non-Turbo Mode), increase time by amount shown. CAPACITANCE Symbol Parameter Conditions Max Unit 20 pF = = 1.0 MHz 20 pF 1.0 MHz 20 pF Pin 13 on 5C060 ~50 pF Pin 21 on 5C090 80 pF Input Capacitance VIN COUT Output Capacitance VOUT CClK Clock Pin Capacitance VOUT CvPp VppPin OV, f = = = OV, f OV, f 2-41 Min Typ 1.0 MHz = CIN inter 5C060/5C090 SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTIC TA = O·C to 70·C, Vcc = 5.0V ± 5%, Turbo Bit On(8) Device Symbol 5C06~45 Parameter 5C060-55 Min Typ Max Min Typ Max NonTurbo Mode Device Non-(10) 5C090-60 5C090-50 Min Typ Max Min Typ Max Turbo Mode Unit fMAX Max. Frequency (1/tsu-No Feedback) 26.0 23.0 (11) 26.0 21.5 (11) MHz fCNT Max. Count Frequency (1/tCNr-With Feedback) 22.0 18.0 (11) 20 16.5 (11) MHz tSUl Input Setup Time to ClK 36 41 +25 36 43 +25 ns tSU2 1/0 Setup Time to ClK 38 43 +25 38 46 +25 ns tH I or II 0 Hold after ClKHigh 0 0 0 0 ns teo ClK High to Output Valid 22 25 tCNT Register Output Feedback to Register Input-Internal Path 45 55 tcH ClK High Time 17.5 21.5 17.5 23 ns teL ClKlowTime 17.5 21.5 17.5 23 ns +25 23 25 50 60 ns +25 ns ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS TA = O·C to 70·C, VCC = 5.0V ±5%, Turbo Bit On(8) Device Symbol Parameter 5C06~45 5C060-55 Min Typ Max Min Typ Max NonTurbo Mode Device SC090-50 Non-(10) SC090-60 Min Typ Max Min Typ Max Turbo . Mode Unit 22.0 18.0 (11) 20 16.5 (11) MHz Input Setup Time to Asynch. Clock 10 10 +25 10 10 +25 ns tASU2 110 Setup Time to Asynch. Clock 12 12 +25 10 10 +25 ns tAH Input or 110 Hold After Asynch. Clock 15 15 15 15 tACO Asynch. ClK to"Output Valid 52 62 tACNT Register Output Feedback to Register Input-Internal Path 45 55 tACH Asynch. ClK High Time 17.5 21.5 20 25 ns tACL Asynch. ClK low Time 17.5 21.5 20 25 ns fACNT Max. Count Frequency (1/tACNr-With Feedback) tASUl NOTES: 11. Recalculate frequency according to equation at left of table. 2-42 +25 ns 60 70 50 60 ns +25 ns inter 5C060/5C090 SWITCHING WAVEFORMS COMBINATORIAL MODE INPUT OR I/o f~j( INPUT COMBINATORIAL OUTPUT !---tpxz (FROM REGISTER TO OUTPUT) I r HIGH IMPEDANCE 3-STATE , HIGH IMPEDANCE 3-STATE / tpzx - VALID OUTPUT "- ~.~ ASYNCHRONOUSLY CLEAR OUTPUT 290104-16 SYNCHRONOUS CLOCK MODE CLK1,CLK2 J ir=tCH:::j '1\1...___[ -.tSU+tH i'/VALIDI '\ INPUT '\{ Ji\'-______ IN_PU_T_M_A_Y_CH_A_N_GE_ __ ___ IN_PU_T_M_AY_CH_A_NG_E_ _ ~tco(FROM REGISTER , I I\ TO OUTPUT) -----------------------' 2-43 VALID OUTPUT ~-----------------290104-17 intJ 5C060/5C090 SWITCHING WAVEFORMS (Continued) ASYNCHRONOUS CLOCK MODE ASyN.----'' CLOCK INPUT _ _ _ _ J OTHER INPUT (FROM REGISTER TO OUTPUT) VALID OUTPUT 290104-18 5C060 5C060 Current In Relation to Frequency Current in Relation to Temperature ! J! 120 110 100 90 80 70 60 50 40 30 20 10 120 110 100 90 80 70 / V /' ~1r ~ -1'1 o o $ I j Non-Turbo I I I I 5 10 15 20 25 r- 60 50 40 30 20 10 o o 30 35 r- leNT = 25M Hz - I I I-- leNT- IO Hz I ir- - leNT = 1MHz, Turbo I I I leNT = 1MHz, Non-Turbo ..,.. I I I I 20 40 I I 60 8085 TEMP (e) leNT (MHz) 290104-27 290104-25 Conditions:/TA = O'C, Vee = 5.25V Conditions: Vee = 5.25V, TTL inpu,ts 5C0601090 Output Drive Current In Relation to Voltage 100 1 1: ~ ~ (J "!J 50 20 10 I - ....... ~ 10L f 0 5 2 2 10HI'\. 1 0 3 4 5 Vo Output Voltage (V) 290104-26 Conditions: TA = 25'C 2-44 intJ 5C121 1200 GATE CHMOS H-SERIES ERASABLE PROGRAMMABLE LOGIC DEVICE • Advanced Architecture Features Including Programmable Output Polarity (Active High/Low), Register By-Pass and Reset Controls • Programmable Clock System for Input Latches and Output Registers • High Performance LSI Semi-Custom Logic Replacement for Gate Arrays and Conventional Fixed Logic • EPROM Technology Based. UV Erasable • Programmable Macrocell and I/O Architecture; up to 36 Inputs or 24 Outputs, 28 Macrocells Including 4 Burled Registers • Product-Term Sharing and Local Bus Architecture for Optimized Array Performance • Compatible with LS TTL and 74HC CMOS Logic • Register Pre-Load and Erasable Array for 100% Generic Testability • All Inputs are Latchable with a Programmable Latch Feature • High Speed tpD (Max) 50 ns Operating Frequency (Max) 20 MHz • Low Power; 15 mW Typical Standby Dissipation • Typical Usable Gate Count of 1200 2-lnput NAND Gates • Programmable "Security Bit" allows total protection of proprietary designs • Available In a 4D-Lead Window Cerdlp Package (SeePackagingSpec,Orde,#231369) The Intel 5C121 H-EPLD (H-series Erasable Programmable Logic Device) is an LSI logic circuit that is user customizable through programming. This device can be used to replace gate arrays, multiple programmable logic arrays and LS TTL and 74HC CMOS 551 and MSI logic devices. The logic capacity of the 5C121 is typically equal to 1200 two-input NAND gates. The 5C121 H-EPLD uses CHMOS· EPROM (floating gate) cells as logic control elements instead of fuses. Use of Intel's advanced CHMOS II-E EPROM process technology enables greater logic densities to be achieved with superior speed and power performance. The EPROM technology also enables these devices to be 100% factory tested by the programming and the erasure of all the EPROM logic control elements in the device. The architecture of the 5C121 is based on the 'Sum of Products' PLA (Programmable Logic Array) structure with a programmable AND array feeding into a fixed OR array. Flexibility in accommodating logical functions ~ithout the overhead of unnecessary product terms or speed penalties of programmable OR structures is achieved through the provision of a range of OR gate widths as well as through product term sharing. The use of a segmented PLA structure with local and global connectivity allows for further improvements in performance. The 5C121 also contains innovative architectural features that provide extensive Input/Output flexibility. 'CHMOS is a patented process of Intel Corporation. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI Vo TA tR IF Min Max Units Parameter Supply Voltage 4.75 5.25 V INPUT Voltage 0 Vee V OUTPUT Voltage 0 Vee V ·C Operating Temperature 0 70 INPUT rise Time 500 ns INPUT fall Time 500 ns Pin Configuration CLIO '" 112 1/01 '/0, '/0, '/0, 'to. '/0, ,to, 7 8 'lOt va. 1& 290098-1 ILLUSTRATIONS COURTESY OF ALTERA CORPORATION. 2-45 November 1887 Order Number: 290088-004 5C121 ARCHITECTURE DESCRIPTION MACROCELL 1/0 ARCHITECTURE The 5C121 H-EPLD has 12 dedicated inputs as well as 24 Input/Output pins. All Inputs to the 'circult (both dedicated and I/O inputs) may be latched using transparent 7475 type latches. In addition to these 36 input latches, 28 D type registers are also provided. The Input/Output architecture of the 5C121 macrocell (see Figure 1) can be programmed using both static and dynamic controls. The static controls remain fixed after the device Is programmed whereas the dynamic controls may change state as a result of the signals applied to the device. The internal architecture of the 5C121 H-EPLD is based on 28 macrocells. Each macrocell (see Figur~ 1) contains a PLA structure (programmab!e ~ND array product terms connected to an OR gate) and an I/O architecture control block (with a D Flij):Flop) that can be programmed to create many different output logic structures. This powerful I/O architecture can be configured to support both active-high, active-low, 3-state, open drain and bi-directionai data ports all on a 4-bit wide basis. They can also act as inputs on a nibble wide basis With optionai input latching. The static controls set the inversion logic 0), register by-pass (ii) and input feedback multiplexers Oil). In the latter two cases these controls operate on four macrocells a bank. Macrocells in each half of the circuit are grouped together for I/O architecture programming. Each bank of four macrocells can be further programmed on an individual macrocell basis to generate active high or active low outputs of the logic function from the PLA. The primary logic array of the 5C121 .is segmented into two symmetrical halves that communicate via global bus signals. The main array contains some 15104 programmable elements representing 236 product terms (AND gates) each containing 64 input signals. The macrocells share Ii common programmable clock system (described in a later section) that controls clocking of all registers and input latches. The device contains 8 modes of clock operation that allow logic transition to take place on either rising or falUng edges of the clock Signals. as The buried-state registers have simpler controls that determine if the feedback is to be registered or combinational. The inversion cohtrol logiC, marked (i) in Figure 1, is achieved by programming the EPROM control bit connected to the same XOR gate as the output from the PLA structure. Programming or erasure of this EPROM element toggles the OR gate output of the PLA betWeen active-high and active-low. The inversion control operates on an individual macrocell basis. The register by-pass control, marked (ii) in Figure 1 ailows the PLA output to either flow through the D Flip-Flop as a registered output or by-pass the FlipFlop and be a combinational output. The dynamic controls consist of a programmable input latch-enable as well as reset and output enable product terms. The latch-enable function is common throughout the 5C121 and once chosen, will latch all the inputs. This function is programmed by the clock control block but may also be driven by input signals applied to pin 1 (see clock modes-Table 1). The reset and output-enable controls' are logically controlled by single product terms (the logic AND of programmed variables in the array). These terms have control over banks of four macrocells. The device also contains four macrocells whose outputs are not tied to any I/O pin but feed back into the array to create buried state-functions. The feedback path may be either the registered or combinational result of the PLA output. The use of the buried state macrocells provides maximum equivalent logic density without demanding higher pin-count packages that consume valuable b~d space. The olltput-enable control may be used to generate architecture types that include bi-directional, 3-state, open drain. or input only structures. 2-46 intJ 5C121 I/o PLA BLOCK ARCHITECTURE BLOCK EPROM CONTROL BIT 290098-2 Figure 1. 5C121 Macrocelil/O Architecture The global busses (Input bus & Global feedback from A-3 & B-3 macrocells & buried registers) are made up of 48 conductors that span the entire chip. These 48 conductors carry the TRUE and COMPLEMENT of the twelve primary inputs (pins 2 through 7 and 33 through 38). signals from 4 Buried Registers as well as the global outputs of 8 macrocells in groups A-3 and B-3. ' INTERNAL BUS STRUCTURE The two identical halves of the 5C121 communicate via a series of busses. The local bus structure used for communication within each half of the chip contains 16 conductors that carry the TRUE and COMPLEMENT of 8 local macrocells. In the block diagram (Figure 2) of the 5C121 the local macrocells are B-1 and B-2 on one half and A-1 and A-2 on the other half. 2-47 inter 5C121 A-I t.1ACROCELLS -..&-- 290098-3 Figure 2. 5C121 Block Diagram 2-48 inter 5C121 290098-4 Figure 2. 5C121 Block Diagram (Continued) 2-49 5C121 LOCAL BUS GLOBAL BUS INPUT BUS In this illustration a small group of 4 product-terms is shared by groups col'!taining 8 product-terms each. This feature is most useful in· counter applications where common terms exist in the functions. DETAILED CIRCUIT REPRESENTATION -0- = 64 INPUT AND GATE (ONE PRODUCT TERM) 290098-5 Figure 3. Shared Product-Term Circuits 2-50 5C121 is adjacent to their macrocell (see Figure 4) so that they may produce a logical AND of any of the variables (or their complements) that are present on the busses. SHARED PRODUCT TERMS Macrocells 9 & 10, 11 & 12, 17 & 18 and 19 & 20 (in groups A-3 and 8-3-the macrocells with global feedback) have the facility to share a total of 16 additional product terms. This sharing takes place between pairs of adjacent macrocells. This capability enables, for example, macrocells 9 and 10 to expand to 16 and 8 effective product terms respectively, and for macrocells 11 and 12 both to expand to 12 effective product terms. Figure 3 shows this sharing technique in detail. This facility is primarily of use in state machine and counter applications where common product terms are frequently required among output functions. All macrocells have the ability to return data to the local or the global bus. Feedback data may originate from the output of the macrocell or from the 1/0 pin. Feedback to the global bus communicates throughout the part. Macrocells that feedback to the local bus communicate only to their half of the 5C121. Connections to and from the signal busses are made with EPROM switches that provide the reprogrammable logiC capability of the circuit. Macrocells in groups A-3 and 8-3 and the buried registers all have global bus connections while macrocells in groups A-1, A-2 and B-1, 8-2 have only local bus connections (see Block Diagram, Figure 2). Advanced features of the Intel Programmable Logic Development System II will, if desired, automatically select an appropriate macrQceli to meet both the logic requirements and the connection to an appropriate signal bus to achieve the interconnection to other macrocells. MACROCELL-BUS INTERFACE As discussed earlier, the macrocells within the 5C121 are interconnected to other macrocells and inputs to the device via three internal data busses. The product terms span the entire bus structure (local feedback, global feedback and input buses) that At each intersecting point in the logic array ther6 exists an EPROM-type programmable connection. Initially, all connections are complete. This means that both the true and complement of all inputs are connected to each product-term. Connections are opened during the programming process. Therefore any product term can be connected to the true or complement of any input. When both the true and complement connections of any input are left intact, a logical false results on the output of the AND gate. If both the true and complemant connections of any input are programmed open. then a logical "don't care" resuhs for that input. If all inputs for a product term are programmed open, then a logical true results on the output of the AND gate. EPROM@ CELL CONNECTION II 64 INPUT AND GATE "'-... EPROM CELL ARCHITECTURE SWITCH / FEEDBACK SIGNALS LOCAL BUS GLOBAL BUS INPUT BUS 290098-6 Figure 4. Macrocell·Bus Interface 2-51 inter 5C121 power rating. The 5C121 should be placed within one inch of the lamp tubes during erasure~ The maximum integrated dose the 5C121 can be exposed to without damage is 7258 Wsec/cm2 (1 week @ 12,000 jJ-W/cm 2). Exposure to high intensity UV light for longer periods may cause permanent damage. CLOCK MODE CONTROL The 5C121 contains two internal clock data paths that drive the input latches (transparent 7475 type) and the output registers. These clocks may be programmed into one of 8 operating modes (see clock mode Table 1). Figure 1 shows a typical macrocell which is driven by the master clock signal CLK and the input latch-enable signal ILE. PROGRAMMING CHARACTERISTICS Initially, and after erasure, all the EPROM control bits of. the 5C12t are connected (in the "1" state). Each of the connected control bits are selectively disconnected by programming the EPROM cell into their "O"state. Programming voltage and waveform specifications are available by request from Intel to support programming of the 5C121. The master clock signal is input via pin 1. If programmed modes 4, 5, 6 & 7 are chosen, a second clock signal is required which is input via pin 38 (see Figure 5). Table 1 shows the operation of each clock programming mode. If modes 0, 1, 4, 5, 6 or 7 are chosen (i.e. latching of the inputs is required), all inputs, both dedicated and 110, are latched with the same ILE signal. Data applied to the inputs when CLK1 is low (high) is latched when CLK1 goes high (low) and will stay latched as long as CLK1 stays high (low). Levels shown in parenthesis are for modes 1,5 & 7 and levels shown outside parenthesis are for modes 0, 4 & 6. inteligent Programming™ Algorithm The 5C121 supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and EPROMs) using an efficient and reliable method. The inteligent Programming Algorithm is particularly suited to the production programming environment. This method greatly decreases the overall programming time while programming reliability is ensured.as the incremental program margin of each bit is continually monitored to determine when the bit has been successfully programmed. , Care is required when using any of the clock modes 4, 5, 6 or 7, that require two input clock Signals to ensure that timing hazards are not created. ERASURE CHARACTERISTICS Erasure characteristics of the 5C121 are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000A. It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 30004000A. Data shows that constant exposure to room level fluorescent lighting could erase the typical 5C121 in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the 5C121 is to be exposed to these types of lighting conditions for extended periods of time, conductive opaque labels should be placed over the window to prevent unintentional erasure. FUNCTIONAL TESTING Since the logical operation of the 5C121 is. controlled by EPROM elements, the device is completely factory tested. Each programmable EPROM bit controlling the internal logic including the buried' state registers are tested using application-independent test program patterns. After testing, the devices are erased before shipment to customers. No post-programming tests of the EPROM array are necessary. To enable functional evaluation of counter and state-machine applications, the 5C121 contains registerpre-Ioad circuitry. This can be activated by interrupting the normal clocked sequence and applying Vpp on pin 2 to engage the pre-load state. Under these conditions the Flip Flops in the 5C121 can be set to any logical condition and then return to normal operation. This process' simplifies the input sequences necessary to evaluate the counter and state machine operations. The recommended erasure procedure for the 5C121 is exposure to shortwave ultraviolet light which has the wavelength of 2537A. The integrated dose (Le., UV intensity x exposure time) for erasure should be a minimum of fifteen (15) Wsec/cm2 • The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 jJ-W/cm2 2-52 inter 5C121 Table 1. Clock Programming (Key: L = Latched; T = Transparent) Programmed Mode Input Signals Are Latched When: Output Registers Change State When: 0 CLK1 (Pin 1) ~ L T CLK1 (Pin 1) 1 CLK1 (Pin 1) \f T L CLK1 (Pin 1) 2 Inputs Not Latched CLK1 (Pin 1) 3 Inputs Not Latched CLK1 (Pin 1) 4 CLK1 (Pin 1) 5 CLK1 (Pin 1) 6 CLK1 (Pin 1) 7 CLK1 (Pin 1) ~ \f ~ \f L T CLK2 (Pin 38) T L CLK2 (Pin 38) L T CLK2 (Pin 38) T L CLK2 (Pin 38) '- ...r '- ...r ''- ...r ...r Clock Configuration 1 Clock 1 Clock 1 Clock 1 Clock 2 Clocks 2 Clock 2 Clocks 2 Clocks DESIGN RECOMMENDATIONS DESIGN SECURITY For proper operation it is recommended that input and output pins be constrained to the range GND < (VIN or VOUT) < Vee. Unused inputs should be tied to an appropriate logic level (e.g. either Vee or GND) to minimize device power consumption. A single EPROM bit provides a programmable design secruity feature that controls the access to the data programmed into the device. If this bit is set, a proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-ba,sed devices since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control bits, will be reset by erasing the device. When utilizing a macrocell with an 1/0 pin connection as a buried macrocell (Le. just using the macrocell for feedback purposes to other macrocells), its 1/0 pin is a 'reserved pin'. (The Intel Programmable Logic Development System II will label the pin 'RESERVED' in the utilization report that it generates.) Such an 1/0 pin will actually be an output pin and should not be grounded. It should be left unconnected such that it can go high or low depending on the state of the macrocell's output. LATCH-UP IMMUNITY All of the input, 1/0, and clock pins of the 5C121 have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5C121 is designed with Intel's proprietary CHMOS II-E EPROM process. Thus, each of the 5C121 pins will not experience latch-up with currents up to 100 mA and voltages ranging from -1V to Vee + 1V. Furthermore, the programming pin is designed to resist latch-up to the 13.5V maximum device limit. In normal operation VeelVpp (pin 40) should be connected directly to Vee (pin 39). 2-53 inter 5C121 CLOCK SIGNALS TO 'A' HALF OF CIRCUIT CLK=.REGISTER CLOCK IlE=INPUT LATCH ENABLE IlE ClK ....- - - - - . . , Cll< IlE "CLOCK CONTROL lOGIC" ClK (PIN 1) 13 14 15 OPTIONAL SECOND / CLOCK INPUT r;; ClK2 ";IN 38) 290098-7 Figure 5. Programmable Clock Control System 2-54 intJ 5C121 • Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS· Min Max Unit Vee Symbol Supply Voltage(l) Parameter -2.0 7.0 V Vpp Programming Supply Voltage(l) -2.0 13.5 V VI DC Input Voltage(1)(2) -0.5 Vee+ 0.5 Icc DC Vee Current(4) T8 tg Storage Temperature -65 V 100 mA +150 ·C Ambient Temperature(3) -10 ·C +85 Tamb NOTES: 1. Voltages with respect to ground. 2. Minimum DC input is -0.5V. During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns under no load conditions. 3. Under bias. 4. With outputs tristated. D.C. CHARACTERISTICS T A = a· to 70·C, Vcc = 5 OV + - 5% Symbol Max Unit VIH HIGH level Input Voltage 2.0 Vee + 0.3 V VIL lOW level Input Voltage -0.3 0.8 V VOH HIGH level Output Voltage 10 = VOL lOW level Output Voltage 10 = 4.0mADC II Input leakage Current VI = Vee or GND loz 3-State Output Off-State Current Vo ISB Vee Supply Current (Standby) (Note 6) VI Icc Parameter Vee Supply Current (Active) Conditions Min -4.0 mA DC 2.4 No load = 10MHz f V 0.45 V ±10.0 jJoA ±10.0 jJoA CMOS Inputs 3 rnA TTL Inputs 30 = VeeorGND = VeeorGND 10 = 0 Typ CMOS Inputs 50 TTL Inputs 100 rnA Output Short Circuit Current (NoteS) 130 rnA los NOTES: 5. Output shorted for no more than 1 sec. and no more than one output shorted at a time. los is sampled but not 100% tested. 6. Chip automatically goes into standby mode if logic transitions do not occur. (Approximately 100 ns after last transition.) A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 5V 3'°-V20 INPUT 855.0. 341.0. OUTPUT DEVICE INPUT RISE AND FALL TIMES < 6nS o--,\O~ >TEST POINTS< V20 Ali. l~-TEST P O I N T S - E 290098-9 A.e. Testing: Inputs are Driven at 3.0V for a Logic "1" and OV for a Logic "0". Timing Measurements are made at 2.0V for a Logic "I" and 0.8V for a Logic "0" on inputs. Outputs are measured at a 1.5V pOint. 290098-8 2-55 inter 5C121 A.C. CHARACTERISTICSTA = O·to 70·C, Vee = 5.0V ±5% Symbol Device Parameter Conditions 5C121·50 5C121·65 5C121·90 Min Min Min Max Max Unit Mali tpo Non-Registered Input or I/O Input to Non-Registered Output tpzx(7) Non-Registered Input or I/O Input to Output Enable tpXZ(7) Non-Registered Input or 1/0 Input to Output Disable tsu Non-Registered Input or 1/0 Input to Output Register Setup 37 47 62 ns tH Non-Registered Input or 1/0 Input to Output Register Hold 0 0 0 ns 20 25 30 ns 20 25 30 CL = 30pF 50 65 90 ns 50 65 90 ns 50 65 90 ns tCH Clock High Time tCl Clock Low Time teo Clock to Output Delay 28 33 38 ns tCNT Minimum Clock Period (Register Output Feedback to Register Input-Internal Path) 50 55 75 ns fCNT Maximum Frequency (1 lteNT) 20.0 18.0 13.0 fMAX Maximum Frequency (1 Itsu) 25.0 20 16.0 tRST Asynchronous Reset Time tlLS Set Up Time for Latching Inputs tlLH Hold Time for Latching Inputs 15 te1C2 Minimum Clock 1 to Clock 2 Delay 40 tlLOFS Input Latch to D-FF Setup Time 40 tOFILS D-FF to Input Latch Setup Time 25 tp3 Minimum Period for a 2-Clock System (TC1 C2 f3 CL = 30pF 50 65 0 ModeO,l ns MHz MHz 90 0 ns 0 ns 20 25 ns 50 65 ns 50 65 ns 30 35 65 ns 100 85 ns + tC01) Maximum Frequency (1 ItP3) 15.0 10.0 12.0 MHz NOTE: 7. tpzx and tpxz are measured at ±0.5V from steady state voltage as driven by spec. output load. tpxz is measured with CL = 5 pF. SWITCHING WAVEFORMS INPUT OR I/o INPUT COMBINATIONAL OUTPUT INPUT MAY CHANGE }I{ COMBINATIONAL OR REGtSTERED OUTPUT HIGH IMPEDANCE 3-STATE HIGH IMPEDANCE 3-STATE VALID OUTPUT 290098-11 290098-10 NOTE: Above waveforms shown for clock modes 2,or 3 (tsu & tH are as in modes 2 & 3; no ILE Signal is used). 2-56 5C121 CLOCK MODES SWITCHING WAVEFORMS 1-CLOCK SYSTEM: MOOES 0 AND 1 -'LDrsClKl (PIN 1) ~ ILS INPUTS OR I/O INPUTS torlLS !--I :~LH- -X -+ REGISTERED OUTPUT teo.!': X tpo )( COMBINATIONAL I. tpxz COMBINATIONAL OR REGISTERED _ _ _ _ _ _ _ _ _ _ OUTPUT ~ I---tpZX ~ • 290098-12 INVERT ClKl FOR MODE 0 1-CLOCK SYSTEM: MODES 2 AND 3 I/o INPUTS _ _ _ __ INPUTS OR COMBINATIONAL OUTPUT ~ tpD t f 1: ------+t-PX-z.J~ COMBINATIONAL - - - - - - - - OR REGISTERED OUTPUT-------.J INVERT elKl FOR MODE 2 2-57 t PZX 290098-13 inter 5C121 CLOCK MODES SWITCHING WAVEFORMS (Continued) -tclC2CLK2 (PIN 38) tcoREGISTERED . OUTPUT f f-- tpD.::::i COMBINATIONAL OUTPUT X I---tpxz COMBINATIONAL OR REGISTERED -tpzx ~ OUTPUT------------------~ 290098-14 INVERT CLKl FOR MODES 5 & 7 INVERT COO FOR MODES 4 & 5 100 ! C 20 a 10 ~ "S - -- 50 I IOL ~ 0 5 ~ 2 '" ", 10H \ 1 0 2 Vo Output 3 4' 5 Voltage (V} 290098-20 Output Drive Current In Relation to Voltage 2-58 intJ SC121 SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both SCHEMA II-PLD and iPLS II software. The other design entry formats supported are Boolean equation entry and State Machine design entry. Intel Programmable Logic Development System II (iPLDS II) The iPLDS II provides all the tools needed to design with Intel H-Series EPLDs or compatible devices (see Figure 6). It contains comprehensive third generation software that supports four different design entry methods, minimizes logic, does automatic pin assignments and produces the best design fit for the selected EPLD. It is user friendly with guided menus, on-line Help messages and soft key inputs. The iPLDS II runs on the IBMt PC, PC/XT or PC/AT and other compatible machines with the following configuration: (1) At least one floppy disk drive and hard disk drive (2) MS-DOStt Operating System Version 2.0 or later release In addition, the iPLDS II contains programmer hardware in the form of an expansion card for the PC with programming software to enable the user to program EPLDs, read and verify programmed devices and also to graphically edit programming files. The software generates industry standard JEDEC object code output files which can be downloaded to other programmers as well. (3) 640K Memory (4) Intel iUP-PC Universal Programmer-Personal Computer and GUPI Adaptor (supplied with iPLDS II). Detailed information on the Intel Programmable Logic Development System II is contained in a separate Intel data sheet (Order Number: 280168). The iPLDS II has interfaces to popular schematic capture packages (Dash series from Futurenet· and PC CAPS·· from PCAD) to enable designs to be entered using schematics. A more integrated schematic entry method is provided by SCHEMA II-PLD, a low-cost schematic capture package that supports EPLD primitives and user-defined macro symbols. *FutureNet is a registered trademark of FutureNet Corporation. DASH is a trademark of FutureNet Corporation. "PC-CAPS is a trademark of P-CAD Corporation. tlBM Personal Computer is a registered trademark of International Business Machine Corporation. . ttMS-OOS is a registered trademark of Microsoft Corporation. 2-59 .. - !I ..... It: -. 1= 'lin E" E 1& l! E 00 Figure 6. Intel Programmable Logic Development System II 2-60 5C180 1800-GATE CHMOS ERASABLE PROGRAMMABLE LOGIC DEVICE Performance LSI Semlcustom Feedback Signals Allowing 110 • High • Dual Pins to Be Used for Buried Logic and Logic Replacement for TTL and 74HC SSI and MSI Logic Dedicated Input Programmable Clock System with Four CHMOSEPROM Technology-Based UV • Erasable • Synchronous Clocks as well as Asynchronous Clocking Option on All 48 Macrocells with Programmable 110 • Architecture; Registers up to 64 Inputs (16 Programmable Registers. Can Be Dedicated, 48 110) or 48 Outputs • Configured as 0, T, SR or JK Types High Speed tpD (max) 75 ns Operating with Individual Reset Controls • Frequency (Max) 12 MHz Register Pre-Load and Erasable Array Low Power; 100 p.W Typical Standby • for • Dissipation 100% Generic Testability J-Lead Chip Carrier and Pin Grid Programmable "Security Bit" Allows • 68-Pln • Total Array Packages Protection of Proprietary Designs (See packaging spec., Order #23f369) The Intel 5C180 EPLD (Erasable Programmable Logic Device) is a CHMOS LSI Logic Device capable of integrating 1800 to over 2000 equivalent gates of SSI/MSI logic. This user customizable Logic Device is available in a 68-pin J-Leaded chip carrier or Pin Grid Array package and has the benefits of low power and increased flexibility. The 5C180 EPLD uses CHMOS EPROM (floating gate) cells as logic control elements instead of fuses. Use of Intel's advanced CHMOS II-E EPROM process technology enables greater logic densities to be achieved with superior speed and power performance. The EPROM technology also enables these devices to be 100% factory tested by the programming and the erasure of all the EPROM logic control elements in the device. The architecture of the 5C180 is based on the "Sum of Products" PLA (Programmable Logic Array) structure with a programmable AND array feeding into a fixed OR array. The 48 macrocells of the 5C180 can be partitioned into 4'identical quandrants each containing 12 macrocells. This device makes use of a,segmented PLA structure with local and global bus structures to provide for increased performance and greater- device utilization. The 5C180 has unique architectural features that allow programming of all 48 registers to D, T, SR or JK configurations without sacrificing product terms. These registers can be either clocked asynchronously or in banks with four synchronous clocks. In addition, the 16 global macrocells have two independent feedback paths to the array that allow for buried logic implementation together with use of the 110 pin for input functions. 1 2 :5 , S , 7 8 9 10 11 ~i~8~~~ oo;s;s>;;~oo :::,.:::,. :::,.:::,. ~ iii ~ Figure 1. Pin Configuration ~~ 290111-35 Figure 2. PGA Pin Configuration 2-61 November 1987 -Order Number: 290111-004 5C180 opened during the programming process. Therefore any product term can be connected to the true or complement of any input. When both the, true and complement connectio,ns of 'any input are left intact, a logical false results on the output of the AND gate. If both the true and complement connections of any input are programmed open, then a logical "don't care" results for that input. If all inputs for a product term are programmed open, then a logical true results on the output of the AND gate. ARCHITECTURE DESCRIPTION Externally, the 5C180 provides 12 dedicated data inputs, 4 synchronous clock inputs, and 48 I/O pins which may be individually programmed for input, output, or bi-dlrectional operation. The Block Diagram is shown in Figure 2. The internal architecture is organized in familiar sum-of-products (AND-OR) structure. The 5C180 houses a total of 480 product terms distributed among 48 Macrocells. The basic Macrocell structure is shown in Figure 3. Input and feedback signals are selectively connected to product terms via EPROM cells. The output of the AND array feeds a fixed OR gate to produce sum-of-products logic. The final output may be combinatorial or registered, programmed active high or low. Combinatorial, registered, or pin feedback is also user-defined. BUS STRUCTURE Input and feedback signals are connected to each 5C180 Macrocell via a Local and Global Bus. Figure 4 shows the Macrocell-Bus interface for Quadrant' D. The Global Bus contains 64 input signals while the Local Bus has 24. Within the 5C180 Macrocell, the product-terms share the entire bus structure. Therefore, a logical AND of any of the variables (or their complements) that is present on the buses may be produced by each product term. The 5C180 is portioned into 4 identical quadrants. Each quadrant contains 12 Macrocells. Input Signals to the Macrocells come from the 5C180 Local and Global bus structures. These two buses comprise an 88-input AND-array for each quadrant. The output of each Macrocell feeds an I/O Architecture Control Block which contains output and feedback selection. All quadrants share the same Global Bus. Inputs to the bus come from the true and complement signals of the 12 dedicated data inputs, 4 clock inputs, and the 16 Global Macrocell pin feedback signals. Four dedicated clock inputs provide synchronous clock signals to the 5C180 internal registers. There is one synchronous clock per quadrant. Therefore each clock signal controls a bank of 12 registers. CLK1 may be connected to registers in Macrocells 1-12, CLK2 with Macrocells 13-24, CLK3 with Macrocells 25-36, and CLK4 with Macrocells 37-48. With synchronous clocks, the flip-flops are positive edge triggered. Both true and complement signals for each dedicated clock input may also be used within the AND array. All 48 internal registers may be individually programmed for synchronous or asynchronous clocking. Asynchronous clocking is possible via a Macrocell product term. Clock inputs not used for synchronous clock signals may be used as global bus inputs. Each quadrant has its own Local Bus. Inputs to this bus come from the 12 quadrant Macropells. For the eight Local Macrocells, the signals can be either from the Macrocell 'internal logic or from the pin. For the four Global Macrocells, the signals come from the Macrocell internal logic only. ' Table 1 summarizes the Macrocell interconnect. Table 1. Macrocellinterconnect Pin Macro- Feedback Feedback Structure Interconnect cell " Quad 2-9 1-8 Local Quad A A 10-13 9-12 Local Quad A Global All " Invert Select EPROM Bit Quad 23-26 B 27-34 The Invert Select EPROM bit is used to invert the product term input Into the register. This applies to all inputs including double inputs on JK and SR registers. The invert option allows the highest possible logic u~ilization by use of de Morgan logic inversion. At each intersecting point in the logic array there exists an EPROM-type programmable connection. Initially, all connections are complete. This means that both the true and complement of all inputs are connected to each product-term. Connections are 2-62 13-16 Local Global Local QuadB All QuadB Quad 36-43 25-32 C 44-47 33-36 Local Local Global QuadC QuadC All Quad 57-60 37-40 D 61-68 41-48 Local Global Local QuadD All QuadD 17-24 intJ 5C180 QUADRANT D QUADRANT A QUADRANT C QUADRANT B GLOBAL MACROCELLS LOCAL MACROCELLS Figure 2. 5C180 Block Diagram 2-63 290111-2 5C180 AND_r SYNCHRONOUS CLOCK YCC~ OE cue EPROM CElL CONHECIIOH PRODUc:r TERM ~ I/o INPUTS AND I/O 290111-3 Figure 3. Balle Macrocell Architecture of the 5C180 2·64 5C180 GLOBAL BUS (64 INPUT) LOCAL BUS (24 INPUT) QUADRANT D MACROCELL 48 MACROCELL 47 MACROCELL 46 MACROCELL 45 MACROCELL 44 MACROCELL 43 MACROCELL 42 MACROCELL 41 MACROCELL 40 MACROCELL 39 MACROCELL 38 MACROCELL 37 GLOBAL BUS TO OTHER QUADRANTS 290111-4 Figure 4. Quadrant "D" Bus Interface 2·65 5C180 routed to the quadrant local bus. Therefore, the Local Macrocell feedback communicates only to Macrocells within the same quadrant. There are a total of 32 Local Macrocells within the 5C180, with eight per quadrant. 5C180 MACROCELLS Within each 5C180 quadrant there are two different types of. Macrocells; Local Macrocells, Figure 5, and Global Macrocells, Figure 6. Both types share an 88. input AND array and contain a total of ten product terms. Eight product terms are dedicated for logic implementation. One product term is reserved for Asynchronous Clear to the Marcocell register. The remaining product term is used for Output Enable/ Asynchronous Clock implementation. Each 5C180 product term represents an 88·input AND gate. The I/O Architecture Control Block provides each Mac· rocell with both combinatorial and registered I/O configurations. Global .Macrocells contain two independent feedback paths to the AND array. Combinatorial or registered feedback is supplied to the local bus and pin feedback is supplied to the global bus. The "dual feedback" capability allows the Macrocell to be used for internal logic functions as well as a dedicated input pin. To obtain this configuration, the output buffer must be disabled. If the Global Macrocell I/O pin is not being used as a dedicated input, the Macrocell logic may be fed back along the global bus allowing routing to any of the 5C180's 48 Macrocells. There are 16 Global Macrocells contained in the 5C180, four per quadrant. Local Macrocells provide one feedback path into the AND array. Combinatorial, registered or pin feed· back may be selected from the Feedback Select Multiplexer. The selected feedback signal is then QUADRANT SYNCHRONOUS CLOCK -GLOBAL BUS-LOCAL BUS_ OE OE/ CLOCK t-fT--f1F-~:""----f=F----1FF---I=f:....J--I L!:::~:-t-.., .CLK I/O ARCHITECTURE CONTROL 6~~4+~~----~--~--4+--~ 7~~4+~~----~--~--4+--~ RESET~+--r~-H~--++--H~~~-~ FEEDBACK SELECT LOCAL BUS GLOBAL DEDICATED INPUTS (16 INPUTS) QUADRANT QUADRANT A,B,C,D LOCAL GLOBAL FEEDBACK FEEDBACK (12 MACROCELLS) ( 1 6 MACROCELLS) 290111-5 Figure 5. Local Macrocell Logic Array 2-66 5C180 QUADRANT SYNCHRONOUS CLOCK 4-----GLOBALBus~LOCALBUS-. CLOCK SELECT OE SELECT OE OE/CLOCKI-fF--FF~IT---ofF-ofF--fl~-I O~r-+t-i+--~H-~~--H---LJ 1~r-+t-i+---~H-~~--H-~ ~ 2~r-~~H---~-~--H~-f e 3HH~r-H----H--H-~r-~ ~ 4~~~-+~---+~-H~-H~-f 2 S~r-~~H---~-~--H~-f II.. I/o ARCHITECTURE CONTROL 6~r-+t-i+---~H-~~~H---1 7~r-~~H---~-~--H--f RESET'tr-1titt--1t-1t-11--t.>--1L___--1 LOCAL BUS GLOBAL BUS ~ GLOBAL DEDICATED INPUTS INPUTS) (16 '~ _ _ _ _ _ _- J (16 QUADRANT A,B,C,D GLOBAL FEEDBACK MACROCELLS) (12 QUAORANT LOCAL FEEDBACK MACROCELLS) 290111-6 Figure 8. Global Macrocell logic Array product term derived in the AND array. When this dedicated product term is a logical one, the Macrocell register is immediately cleared to a logical zero independent of the register clock. The RESET function occurs automatically on power-up. MACROCELL LOGIC CONFIGURATIONS Combinatorial Selection The four different register types shown in Figures 7b-7e are described below: In the Combinatorial configuration, eight product terms are ORed together to generate the output signal. The Invert Select EPROM bit controls output polarity and the Output Enable buffer is product-term controlled. The Feedback Select allows the user to choose combinatorial, 1/0 (pin) or no feedback to the respective local and global buses. D- or T-type Flip-Flops When either a D- or T-type Flip-Flop is configured as part of the 1/0 structure, all eight of the product terms into the Macrocell are ORed together and fed into the register input. REGISTER SELECTION JK or SR Registers The advanced 110 architecture of the 5C180 allows four different register types along with combinatorial output as illustrated in Figures 7a-7e. The register types include a T, D, JK, or SR Flip-Flop and each Macrocelil/O structure may be independently configured. In addition, all registers have an individual asynchronous RESET control from a dedicated When either a JK or SR register is configured, the eight product terms are shared among two OR gates (one for the J or S input and the other for the K or R input). The, allocation for these product terms for each of the register inputs is optimized by the iPLDS II development software. 2-67 intJ 5C180 Burled Logic Selection For Global Macrocells, if no output is selected, the logic may be "buried" and the 1/0 pin can be used as an additional dedicated input. The use of "dual feedback" is accomplished by tri-stating the Output Enable Buffer. Thus, up to 16 additional dedicated inputs may be added without sacrificing the Macrocell internal logic. In the erased state, the 1/0 architecture is configured for combinatorial active low output with I/O (pin) feedback. Q RESET RESET 290111-9 Figure 7c. Toggle Flip-Flop Register _ C.onflguratlon D- ClK 290111'-7 Figure 7a. Combinatorial 110 Configuration INVERT SELECT 290111-10 Figure 7d. JK Flip-Flop Register Configuration Q RESET RESET 290111-8 Figure 7b. 0-Type Flip-Flop Register Configuration 2-68 inter 5C180 The operation of each multiplexer is controlled by EPROM bits and may be individually configured for each 5C180 Macrocell. ClK N In Mode 0, the three-state output buffer is controlled by a single product term. If the output of the AND gate is a logical true then the output buffer is enabled. If a logical false resides on the output of the AND gate then the output buffer is seen as high impedance. In this mode the Macrocell flip-flop may be clocked by its quadrant synchronous clock input. In the erased state, the 5C180 is configured as Mode 8-N o. In Mode 1, the Output Buffer is always enabled. The Macrocell flip-flop now may be triggered from an asynchronous clock signal generated by the Macrocell product term. This mode allows individual clocking of flip-flops from any available signal in the quadrant AND array. Because both true and complement signals reside in the AND array, the flip-flops may be configured for positive or negative edge triggered operation. With the clOCk now controlled by a product term, gate clock structures are also possible. INVERT SELECT 290111-11 Figure 7e. SR Flip-Flop Register Configuration MACROCELL OE/CLK SELECT In Modes 2 and 3, the Output Buffer is alwa~ disabled. The Macrocell flip-flop may still be triggered from clock signals generated from the Macrocell product term or asynchronous clocks. This mode is only possible for Global Macrocells. Each 5C180 register may be clocked synchronously or asynchronously. Figure 8a and 8b shows the modes of operation provided by the OE/CLK Select Multiplexers for both Local and Global Macrocells. 2-69 5C180 SYNCHRONOUS CLOCK vee OE OE/CLK elK - SYNCHRONOUS CLK OE - P-TERII CONTROLLED IIACROCELL REGISTER OUTPUT BUFrER 290111-12 The register Is clocked by the quadrant synchronous clock signal which is common to 11 other MacroceIls. The output Is enabled by the logic from the product term. SYNCHRONOUS CLOCK vee OE OE/CLK CLK - ASYNCHRONOUS CLK OE-ENABLED IIACROCELL REGISTER OUTPUT BUFFER 290111-13 The output is permanentiy enabled and the register is clocked via the product term. This allows for gated clocks that may be generated from elsewhere in the 5C180. . Figure 8a. Local Macrocell OE/CLK Selection 2·70 inter 5C180 SYNCHRONOUS CLOCK OE OE/ClK ClK - SYNCHRONOUS ClK OE - DISABLED MACROCEll REGISTER 290111-14 The output is permanently disabled and the register clocked by the quadrant synchronous clock signal. The pin can be used as an input while the register or combinational output can be fed back. SYNCHRONOUS CLOCK OE OE/ClK ClK - ASYNCHRONOUS ClK OE - DISABLED MACROCEll R'EGISTER 290111-15 The output is permanently disabled and the register is clocked via the product term. This allows gated clocks that may be generated elsewhere in the 5C180. The pin can be used as in input while the register or combinational output can be fed back. Figure ab. Global Macrocell Additional OE/CLK Selection 2-71 5C180 MACROCELL LOGIC CONFIGURATIONS + Figures 9 and 10 show the 5C180 basic I/O configurations for both the Local and Global Macrocells. Along with combinatorial, four register types are available. Each Macroceil may be independently programmed. 1/0 The 5C180 Input/Output Architecture provides each Macrocell with over 50 possible I/O configurations. OE FEEDBACK SELECT 290111-16 COMBINATORIAL I/O Selection Output/Polarity Feedback Bus Combinatorial/High Combinatorial/Low None None Comb, Pin, None Comb, Pin, None Comb Pin Local Local Local Local Figure 9. !.ocal MacrocelillO Configurations 2-72 5C180 SYNCHRONOUS CLOCK OE/ClOCK SELECT V CC OE ClK 0 UI UI III ..J III ..J :::> Q :::> « III « u 0 C 9 ..J C> 290111-17 0-TYPE FLIP-FLOP I/O Selection Output/Polarity D-RegistertHigh D-RegistertLow None None Feedback D-Register, Pin, None D-Register, Pin, None D-Register Pin Bus Local Local Local Local Function Table D 0 0 1 1 Qn Qn +1 0 1 0 1 0 0 1 1 Figure 9. Local Macrocelil/O Configurations (Continued) 2-73 Set8D SYNCHRONOUS CLOCK ' OE/ClOCK Vee SELECT OE Cll( VI VI ::;) ::;) III III .... ~. C 9 290111-18 TOGGLE FLIP-FLOP I/O Selection Output/Polarity Feedback' T-Register/High T-Register, Pin, None T-Register/Low . T-Register, Pin, None None T-Register None Pin Bus Local Local Local Local Function Table T On 0 0 1 1 0 1 0 1 On+1 0 1 1 0 Figure 9. Local Macrocellll0 Configurations (Continued) inter 5C180 SYNCHRONOUS CLOCK OE/ClOCK Vee SELECT OE ClK III :::I III :::I III III .... .... '" ~ III ~ 9 INVERT SELECT 290111-19 JK FLIP-FLOP I/O Selection Output/Polarity Feedback Bus JK Register/High JK Register/Low None JK Register, None JK Register, None JK Register Local Local Local Function Table J 0 0 0 0 1 1 1 1 K 0 0 Qn Qn +1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1 Figure 9. Local Macrocelii/O Configurations (Continued) 2-75 5C180 SYNCHRONOUS CLOCK OE/ClOCK SELECT OE ClK N 8-N C INVERT SELECT 290111-20 SR FLIP-FLOP 110 Selection Output/Polarity SR Register/High SR Register/Low None Feedback SR Register, None SR Register, None SR Register Bus Local Local Local Function Table S R Qn 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Qn + 1 0 1 0 0 1 1 .Figure 9. Local MacrocelillO Configurations (Continued) 2-76 inter 5C180 VI ill ...J ~ 9 290111-21 COMBINATORIAL I/O Selection Output/Polarity Feedback Combinatorial/High Comb, Pin, None Combinatorial/Low Comb, Pin, None None Comb None Pin Comb/Pin None Bus Local, Global Local, Global Local, Global Global Local/Global Figure 10. Global Macrocelii/O Configurations 2-77 inter 5C180 SYNCHRONOUS CLOCK CLOCK SELECT OE SELECT 290111-22 D-TYPE FLIP-FLOP I/O Selection Output/Polarity Feedback Bu. D.RegisterIHigh D-Register/Low None None None, D-Register, Pin, None D-Register, Pin, None D-Register Pin D-Register/Pin Local, Global Local, Global Local, Global Global Local/Global Function Table D 0 0 1 1 Qn 0 1 0 1 Qn +1 0 0 1 1 Figure 10. Global Macrocelii/O Configurations (Continued) 2-78 5C180 SYNCHRONOUS CLOCK CLOCK SELECT OE SELECT 290111-23 TOGGLE FLIP-FLOP I/O Selection Output/Polarity Feedback Bus T-Register/High T-Register/Low None None None T-Register, Pin, None T-Register, Pin, None T-Register Pin T-Register/Pin Local, Global Local, Global Local, Global Global Local/Global Function Table T 0 0 1 1 Qn Qn +1 0 1 0 1 0 1 1 0 Figure 10. Global Macrocelii/O Configurations (Continued) 2-79 5C180 CLOCK OE SELECT SELECT N III ;:) III III III ;:) .... .... <1 9 ~ 0 5 C INVERT SELECT 290111-24 JK FLIP·FLOP I/O Selection. OutpuVPolarlty Feedback Bus JK Register/High JK Register, None Local, Global JK Register/Low JK Register, None Local, Global Local JK Register None None JK Register/Pin Local/Global Function Table J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Qn Qn+1 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 Figure 10. Global Macrocelii/O Configurations (Continued) 2-80 inter 5C180 SYNCHRONOUS CLOCK CLOCK SELECT OE SELECT N 8-N INVERT SELECT 290111-25 SR FLlP·FLOP I/O Selection Output/Polarity Feedback Bus SR Register/High SR Register, None Local, Global SR Register/Low SR Register, None Local, Global None SR Register Local None SR Register/Pin Local/Global Function Table S R On 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 On+1 0 1 0 0 1 1 Figure 10. Global Macrocelii/O Configurations (Continued) 2-81 inter 5C180 the incremental program margin of each bit is continually monitored to determine when the bit has been successfully programmed.' Erased-State Configuration Prior to programming or after erasing, the I/O structure is configured for combinatorial active low output ' with input (pin) feedback. FUNCTIONAL TESTING' Since the logical operation of the 5C180 is controlled by EPROM elements, the device is completely testable. Each programmable EPROM bit controlling the internal logiC is' tested using application-independent test program patterns. After testing, the devices are erased before shipment to customers. No post-programming tests of the EPROM array are ' required. ERASURE CHARACTERISTICS Erasure characteristics of the 5C180 are such that erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000A. It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 300QA4000A range. Data shows that constant exposure to room level fluorescent lighting could erase the typical 5C180 in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the 5C180 is to be exposed to these types of lighting conditions for extended periods of time; conductive opaque labels should be placed over the device window to prevent unintentional erasure. The recommended erasure procedure for the 5C180 is exposure to shortwave ultraviolet light with a wavelength of 2537A. The integrated dose (Le., UV intensity x exposure time) for erasure should be a minimum of fifteen (15) Wsec/cm2 • The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 p.W/cm2 power rating. The 5C180 should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose the 5C180 can be exposed to without damage is 7258 Wsec/cm2 (1 week at 12,000 p.W/cm2). Exposure to high intensity UV light for longer periods may cause permanent'damage to the device. PROGRAMMING CHARACTERISTICS Initially, and after erasure, all the EPROM control bits of the 5C180 are connected. Each of the connected control bits are selectively disconnected by programming the EPROM cells into their "on" state. Programming voltage and waveform speCifications are available by request from Intel to support programming of the 5C180. The testability and reliability of EPROM-based programmable logic devices is an important feature over similar devices based on fuse technology. Fuse-based programmable logic devices require a use to perform post-programming tests to insure proper programming. These tests must be done at the device level because of the cummulative error effect. For example, a board containing ten devices, each possessing a 2% device fallout translates into an 18% fallout at the board level (it should be noted that programming fallout of fuse-based programmable logic devices is typically 2% or higher). DESIGN RECOMMENDATIONS To take maximum advantage of EPLD technology, it is recommended that the designer use the Modular EPLD LogiC Design (MELD) method. The MELD philosophy is derived, from the modular programming method used in software development. In a modular software development environment, the engineer , designs a modular pr9gram (typically on a development system), stores it in memory (EPROM), and tests the module for functionality. A hardware designer using EPLDs can use tl'1is same approach when designing logic. The designer develops a modular logiC design on the Intel Programmable Logie Development System (iPLDS), stores it in ~'memory" ' (the EPROM control elements of the EPLD), and again tests the module for functionality. If the design is in error, the logic designer reprograms the EP'LD with his new design as easily as a software designer can download a new program into memory. The MELD philosophy is new to programmable logic because EPROM-tiased PLDs are new. A modular logic development process,using fused-based PLDs would be wasteful since a fuse-based device cannot be erased and re-used. inteligent Programming™Algorithm The 5C180 supports the inteligent Programming Algorithm which rapidly programs Intel H-ELPDs (and EPROMs) using an efficient and reliable method. The inteligent Programming Algorithm is particularly suited to the production programming environment. This method greatly decreases the overall programming time while programming reliability is ensured as 2-82 inter 5C180 For proper operation, it is recommended that all input and output pins be constrained to the voltage range GND < (YIN or VOUT) < Vee. Unused inputs should be tied to an appropriate logic level (e.g., either Vee or GND) to minimize device power consumption. Reserved pins (as indicated in the iPLS II REPORT file) should be left floating (no connect) so that the pin can attain the appropriate logic level. A power supply decoupling capacitor of at least 0.2 ,..,f must be connected directly between Vee and GND. mizes logic, does automatic pin assignments and produces the best design fit for the selected EPLD. It is user friendly with guided menus, on-line Help messages and soft key inputs. In addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices and also to graphically edit programming files. The software generates industry standard JEDEC object code output files which can be downloaded to other programmers as well. DESIGN SECURITY A single EPROM bit provides a programmable design security feature that controls the access to the data programmed into the device. If this bit is set, a proprietary design within the device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices since programmed data within EPROM cells is invisible even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control bits, will be reset by erasing the device. iPLDS II has interfaces to popular schematic capture packages (including Dash series from Future-NET" and PC-CAPS·· from P-CAD) to enable designs to be entered using schematics. A more integrated schematic entry method is provided by SCHEMA 11PLD, a low-cost schematic capture package that supports EPLD primitives and user-defined macro symbols. SCHEMA II-PLD contains the EPLD Design Manager, which provides a Single user interface to both SCHEMA II-PLD and iPLS II software. The other design formats supported are Boolean equation entry and State Machine design entry. LATCH-UP IMMUNITY The iPLDS II operates on the IBMt PC/XT, PC/AT, or other compatible machine with the following configuration: 1. At least one floppy disk drive and hard disk drive. All of the input, 1/0, and clock pins of the 5C180 have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5C180 is designed with Intel's proprietary CHMOS II-E EPROM process. Thus, each of the SC180 pins will not experience latch-up with currents up to 100 mA and voltages ranging fronm -1V to Vee + 1V. Furthermore, the programming pin is designed to resist latch-up to the 13.SV maximum device limit. 2. MS-DOS:j: Operating System Version 3.0 or greater. 3. 640K Memory. 4. Intel iUP-PC Universal Programmer-Personal Computer (supplied with iPLDS II). 5. GUPI LOGIC Adaptor INTEL PROGRAMMABLE LOGIC DEVELOPMENT SYSTEM II.(IPLDS II) 6. A color monitor is suggested. Detailed information on the Intel Programmable Logic Development System II is contained in a separate Intel data sheet. (Order Number: 280168) The iPLDS II graphically shown in Figure 11 provides all the tools needed to design with Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II insulates the user from having to know all the intricate details of EPLD architecture (the machine will optimize a design to benefit from architectural features). It contains comprehensive third generation software that supports four different design entry methods, mini- • •• t :j: 2-83 FutureNET is a registered trademark of FutureNET Corporation. DASH is a trademark of FutureNET Corporation. PC-CAPS is a trademark of P-CAD Corporation. IBM Personal Computer is a registered trademark of International Business Machines Corporation. MS-DOS is a registered trademark of Microsoft Corporation. l J! c co a; Intel Programma.le Logic Development System II .... .... =ii r- ~ = S' it c8" ill 3 a, 3 CIt ...o I\) ~ :! III D' CD in o !0' "3 CD 3- i "@) 3 290111-26 aID IiiiiI IF c::::::I ~ c::::::I ~ ~ ~ inter 5C180 ·Notice: Stresses above those listed under ':4bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS· Symbol Parameter Min Max Unlta -2.0 7.0 V -2.0 13.5 V Vee Supply Voltage(1) Vpp Programming Supply Voltage(1) VI DC Input Voltage(1)(2) -0.5 Vee+ 0•5 V tstg Storage Temperature -65 +150 DC tamb Ambient Temperature(3) -10 +85 DC NOTICE: Specifications contained within the fol/owing tables are subject to change. NOTES: 1. Voltages with respect to ground. 2. Minimum DC input is -0.5V. During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns under no load conditions. 3. Under bias. Extended temperature versions are also available. D.C. CHARACTERISTICS Symbol VIH(4) VIL(4) VOH(5) TA = O· to +70"C, Vee = 5V Parameter/Test Conditions High Level Input Voltage ±5% Min 2.0 -0.3 Low Level Input Voltage , High Level Output Voltage 10 = -4.0 mA D.C., Vee = min. Typ Max Unit Vee + 0.3 0.8 V V 2.4 V VOL Low Level Output Voltage 10 = 4.0 mA D.C., Vcc = min. 0.45 V II Input Leakage Current Vcc = max., GND < VOUT < Vcc Output Leakage Current Vee = max., GND < VOUT < Vee Output Short Circuit Current Vee = max., VOUT ,= 0.5V ±10 p.A ±10 p.A loz IsC<6) mA IS8(7) Standby Current Vcc = max., VIN = Vcc or GND, Standby mode 20 150 p.A lee Power Supply Current Vcc = max., VIN = VeeorGND, No load, Input Freq. = 1 MHz Active'mode (Turbo = Off), Device prog. as 4 12-bit Ctr. 30 45 rnA NOTES: 4. 5. 6. 7. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included. 10 at CMOS levels (3.84 V) = - 2 mA Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second. With Turbo Bit Off, device automatically enters standby mode apprOximately 100 ns after last input transition. 2-85 inter 5C180 A.C. TESTING LOAD CIRCUIT A.C. TESTING INPUT, OUTPUT WAVEFORM. 5V INPUT 855.n 3.0](20 • o .0.8 > -< . X;20 8 TEST POINTS . 0. DEVICE D-+--+-C> TO TEST OUTPUT SYSTEM 341.n OUTPUT 290111-27 DEVICE INPUT RISE AND FALL TIMES < 6 nS A.C. Testing: Inputs are Driven at 3.0V for a Logic "1" and OV for a LogiC "0". Timing Measurements are made at 2.0V for a LogiC "1" and 0.8V for a Logic "0" on inputs. Outputs are measured at a 1.5V point. 290111-28 CL = 50pF A.C. CHARACTERISTICS Symbol 1~-TEST POINTS-~ From TA = O·C to + 70·C, Vcc = 5V ± 5%, Turbo Bit On(8) 5C180-75 To Min Typ 5C180-90 Max Min Typ Max Non(10) Turbo Adjust Unit ns Input Comb. Output 70 85 +30 tpD2 Local I/O . Comb. Output 75 90 +30 ns tpDG Global I/O Comb. Output 70 85 +30 ns tpZX(9) lor I/O Output Enable 75 90 +30 ns tpXZ(9) lor I/O Output Disable 75 90 +30 ns tClR Asynch. Reset QReset 75 90 +30 ns tpD1 NOTES: 8. Typ. Values are at TA = 25°C, VCC = 5V, Active Mode. 9. tpzx and tpxz are measured at ±0.5V from steady state voltage as driven by spec. output load. tpxz is measured with CL = 5 pF. . 10. If device is operated with Turbo Bit Off (Non-Turbo Mode), increase time by amount shown. CAPACITANCE Symbol Parameter CIN Input Capacitance COUT Output Capacitance CClK Clock Pin Capacitance CvPP Vpp Pin Capacitance Conditions = OV, f = 1.0 MHz VOUT = OV, f = 1.0 MHz VOUT'" OV, f = 1.0 MHz Pin 19, VOUT = OV, f = 1.0 MHz VIN 2·86 Min Typ Max Unit 15 pF 15 pF 25 pF 160 pF 5C180 SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS TA = O·C to Symbol +70·C, vee = 5V ±5%, Turbo Bit On(11) 5C180-75 Parameter Min 5C180-90 Typ Max Min Typ Max Non(12) Turbo Adjust Unit fMAX Max Frequency 1/tsu-No Feedback 19.6 16.1 MHz fCNT Max. Count Frequency 1/tCNT-With Feedback 15.1 12.2 MHz tSU1 Input Setup Time to Clk 51 62 +30 ns tSU2 Local I/O Setup Time to Clk 56 67 +30 ns tSUG Global I/O Setup Time to Clk 51 62 +30 ns tH I or I/O Hold after Clk High 0 0 teo Clk High to Output Valid 30 35 teNT Register Output Feedback to Register InputInternal Path 66 82 tCH Clk High Time 25 30 ns tCL ClkLowTime 25 30 ns ns ns +30 ns NOTES: 11. Typ. Values are at TA = 25°C, Vee = 5V, Active Mode. . 12. If device is operated with Turbo Bit Off (Non-Turbo Mode), increase time by amount shown. ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS TA = O·C to +70·C, VCC = 5V ±5%, Turbo Bit On(13) Symbol Parameter 5C180-75 5C180-90 Min Typ Max Min Typ Max Non(14) Turbo Adjust Unit fAMAX Max: Frequency 1/tAsu-No FeedbaCk 66.7 40.0 MHz fACNT Max. Frequency 1/tACNT-With Feedback 15.1 12.2 MHz tASU1 Input Setup Time to Asynch. Clock 17 23 +30 ns tASU2 I/O Setup Time to Asynch. Clock 22 28 +30 ns tAH Input or I/O Hold to Asynch. Clock 30 30 tACO Asynch. Clk to Output Valid 75 90 tACNT Register Output Feedback to Register InputInternal Path 66 82 tACH Asynch. Clk High Time 25 30 ns tACL Asynch. Clk Low Time 25 30 ns ns ns +30 NOTES: 13. Typ. Values are at TA = 25·C, Vee = 5V, Active Mode. 14. If device is operated with Turbo Bit Off (Non-Turbo Mode), increase time by amount shown. 2-87 ns 5C180 SWITCHING WAVEFORMS COMBINATORIAL MODE INPUT OR I/O INPUT COMBINATORIAL OUTPUT - f'''j I--- tpxz --,--I / " COMBINATORIAL OR REGISTERED OUTPUT . HIGH IMPEDANCE 3-STATE HIGH IMPEDANCE 3-STATE r--tPzx~ tCLR~ , ~ "'" VALID OUTPUT ASYNCHRONOUSLY CLEAR OUTPUT 290111-29 2-88 intJ 5C180 SWITCHING WAVEFORMS (Continued) SYNCHRONOUS CLOCK MODE CLK1,CLK2, CLK3,CLK4 INPUT MAY CHANGE INPUT MAY CHANGE (FROM REGISTER TO OUTPUT) VALID OUTPUT 290111-30 ASYNCHRONOUS CLOCK MODE ASYN. - - - -.... CLOCK INPUT _ _ _ _", OTHER INPUT INPUT MAY CHANGE INPUT MAY CHANGE ~~ t_Aro_~-- ________________________ ___ (FROM REGISTER TO OUTPUT) , , _______________ I I \. ----------------------------'" 2-89 VALID OUTPUT ~-----------290111-31 inter 5C180 ~ ,§. J:l 240 220 200 180 160 140 120 100 80 60 /' ./ ./ A , 10° ~~~/ " II I 40 20 17 Non-Turbo I I o o 5 20 10 feNT (t.tHz) TA = O'C, Vee = 290111-32 5.25V Current in Relation to Frequency --H-J. J - 240 220 f eNT =20t.tHz -~ 200 I 180 feNT= 10t.tHz 160 I-- I I 140 120 100 I-- - f eNT =lt.tHz,Turbo "f I I I 80 60 I I I 40 _ feNT = 1 t.tHz,Non-Turbo 20 I-- - ~ ,§. u- J;,. I I T I I I I I I T I I I I I o o 20 40 60 8085 TEt.tP (e) Vee = 290111-33 5.25V Current in Relation to Temperature 100 1... 50 c 20 0 10 ~::J I - IOL '5 .9::J 5 g 2 '" r'\ IOH 0 1 0 ....... 2 3 4 '"\ 5 Vo output Voltage (V) 290111-34 Output Drive Current in Relation to Voltage 2-90 5AC312 ERASABLE PROGRAMMABLE LOGIC DEVICE • High Performance LSI Semi-Custom Logic Alternative for Low-End Gate Arrays, TTL, and 74HC- or 74HCT SSI and MSI Logic • CHMOS III-E EPROM Technology based; UV-Erasable • Low Power; 150 p,A Standby Current • Programmable Security Bit Allows 100% Protection of Proprietary Designs • High Speed tpd (max) 25 ns, 40 MHz Operating Performance • Erasable Array for 100% Generic Testability 5AC312 KEY FEATURES • 12 Macrocells with Programmable 1/0 Architecture; Up To 22 Inputs (10 Dedicated, 121/0) or 12 Outputs • Dual Feedback on All Macrocells for Buried Register Implementation and Input Usage • 8 Programmable Inputs; Each Can Be Programmed Individually to Implement Latch, Register or Flow-Through Structure; Synchronous or Asynchronous Operation • 2 Product Terms on All Macrocell Control Signals • Programmable Power Option for "Stand-By" Operation • Available in 24-Pin 0.3" DIP and 28-Pln PLCC Packages • Software-Supported Product Term Allocation between Adjacent Macrocells CLK/INP1 1/0.11 LINP1 GND 1 (See Packaging Spec .• Order Number #231369) Vee 1/0.12 1/0.9 1/0.10 1/0.7 1/0.8 1/0.6 1/0.5 LlNP4 LlNP6 1/0.10 1/0.7 1/0.8 1/0.6 1/0.5 1/0.4 1/0.3 1/0.2 LlNP7 1/0.4 LlNP2 LlNP3 LlNP5 N.C. N.C. ILE/ICLK/INP2 290156-1 290156-2 Figure 1. Pin Configurations 2-91 November 1987 Order Number: 290156-001 intJ 5AC312 a highly flexible macrocell and 1/0 structure. In addition, the 5AC312 has been designed to effectively implement both combinational-register and registercombinational-register forms of logic to easily accommodate state machine designs. INTRODUCTION The Intel 5AC312 CHMOS EPlD (Erasable Programmable logic Device) represents an innovative approach to overcoming the primary limitations of standard PlDs. Due to a proprietary 110 architecture and rnacrocell structure, the 5AC312 is capable of implementing high performance logic functions more effectively than previously possible. It can be used as an alternative to low-end gate arrays, multiple programmable logic devices or lS-, HC- or HCT SSI and MSI logic devices. Figure 2 shows a global view of the 5AC312 architecture. The 5AC312 contains a total of 12 1/0 macrocells, 8 user-programmable input structures, and 2 inputs that can be programmed to serve as either combinatorial inputs or clock inputs for the input and output register functions. Each macrocell is further sub-divided into 16 Product Terms with 8 Produot Terms dedicated to the control signals OE, PRESET, ASYNCH. ClK and CLEAR, and 8 Product Terms available for the general data array. . The 5AC312 uses advanced CHMOS EPROM cells as logic control elements instead of poly-silicon fuses. This technology allows the 5AC312 to operate at levels necessary in high performance systems while significantly reducing the power consumption of this device. Its programmable stand-by function reduces power consumption to almost "zero" in applications where speed is traded for power consumption. The basic macrocell architecture of the 5AC312, shown in Figure 3, includes a user-programmable AND array and a user-configurable OR array. The inputs to the, programmable AND array originate from the true and complement signals from the programmable input structure, the dedicated inputs, and the 24 feedback paths from the 12 1/0 macrocells. ARCHITECTURE DESCRIPTION The architecture of the 5AC312 is based,on the familiar "Sum-Of-Products" programmable AND, fixed OR structure, though the 5AC312 macrocell contains a number of significant functional enhancements. This device can implement both combinational and sequential logic functions through Programmable Input Structure Figure 4 shows a block diagram of the 5AC312 input architecture. This device contains 8 user-program- 2-92 inter 5AC312 LOGIC ARRAY CLK/INPI RING 1 .------ 1/0.1 r------ 1/0.2 I I I I I I I I I I IL______ LlNPl I I I 1/0.3 -, I I r------ LlNP2 1/0.4 I I I I I ______ L LlNP3 I I I I I I LlNP4 LlNP5 .. _----- 1/0.6 .------ 1/0.7 r------ 1/0.8 I I I I I I LlNP6 1/0.5 I I I IL ______ I LINP7 I I I 1/0.9 -, I I r------ LlNP8 1/0.10 I I I I L I ______ ILE/ICLK/INP2 I I I I I I .. _----RING 2 1/0.11 1/0.12 290156-3 Figure 2. 5AC312 Architecture 2-93 l TO NEXT MACROCELL LOGIC ARRAY tT FROM NEXT MACROCELL OUTPUT ~ PRESET "II c· ... C CD (0) ~t 0 ......, 1/ JI II II I LOWER HALF ~'I OUTPUT MUX (0) V til I\) ....cO III 1/1 n- 1:::::::'0:::::::::1 MACROCELL REGISTER 5: CI1 ):. 0 .... Co) I\) III ...n0 n ~ -en ... c n C i; II II II II ~ '-V TO PREVIOUS '" MACROCELL ~ ASYNCH. CLK (CLKB) 19l ~ ~ CLEAR © IiiiiI 1. FROM PREviOUS t.fACROCELL <= ~ 'iii! 290156-4 @ :w ~ ~ e::J c:::t @ ~ inter 5AC312 INP PIN D_---...... IN OUT~------...... LOGIC ARRAY P-TERM ILE/ICLK PIN C~-----------------.....I 290156-5 NOTE: Flow-through input selected by connecting II.E P-Term to Vcc. Figure 4. 5AC312 Input Structure mabie input structures that can be individually configured to work in one of five modes: - ILE/ICLK signal for the input structure. Because the clock signal for each input structure can be individually selected, a mix between synchronously and asynchronously clocked input structures is also possible. Input register .(D-register), synchronous operation Input register (D-register), asynchronous operation Input latch (D-Iatch), synchronous operation Input latch (D-Iatch), asynchronous operation Flow-through input Table 1 shows the input latch/register function table with respe~t to the synchronous ILE/ICLK input. Table 1. 5AC312 Input Latch/Register Functions The configuration is accomplished through the programming of EPROM architecture control bits by iPLS II V1.5 under user-control. If synchronous operation is chosen, pin 13 of the device becomes an ILE/ICLK (Input Latch Enable) input global to all input latch/register structures. For asynchronous operation, pin 13 can be used as a normal input (flowthrough input) to the device while a separate Product Term in the control array is used to derive an H 2-95 Input Type ILE/ICLK D Q Latch Latch Latch' D-FF D-FF Flow-Through Flow-Through H H H H L L X L an H H t t X X L L H H L L = HIGH Level L = LOW Level X = Don't Care 5AC312 mented with p-terms from tneir respective previous/ next macrocells in Ring 1. Macrocell Array Each of 12 macrocells in the SAC312 contains 8 Product Terms to support logic functions. These 8 Product Terms are subdivided into 2 groups each containing 4 Product Terms. This grouping of Product Terms supports the proprietary Product Term allocation scheme. f\pplYing this scheme to the SAC312 it becomes clear that any macrocell inside the device can support logic functions requiring between 0 and 16 Product Terms. Product Terms allocated away from a macrocell do not affect that macrocell's output structure. If all Product Terms are allocated "away" from a macrocell, the input to that macrocell's I/O control block is tied to GND. This polarity can be changed by programming the invert select EPROM bit. The I/O register as well as all secondary controls to this I/O control block are still available and can be used if needed. In addition to these 8 Product Terms,each macrocell features 2 Product Terms for each of the four control signals. Control signals in the' SAC312 are: Output Enable (OE), asynchronous I/O register preset (PRESET), asynchronous clock for I/O registers (ASYNCH. CLK), and asynchronous I/O register reset (CLEAR). The 12 macrocells available in the SAC312 are grouped into two "rings" with 6 macrocells per ring. Product Terms can be allocated in a "shift register" mode inside a ring; allocation of Product Terms between the rings is not supported.'The two rings are shown in Figure 2 and listed in Table 2. Product Term Allocation Product Term allocation is defined as taking logic resources (p-terms) away from macrocells where they are not used to support demand for more than 8 ,Product Terms in other areas of the chip. In the SAC312, this allocation can occur in increments Of 4 p-terms between adjacent macrocells. The Product, Term allocation· scheme described above is automatically supported by iPLDS II V1.S and is transparent to the user. Users can still use explicit pin assignments, but should assign pins in a way that does not conflict with p-term allocation. Example: The logic function in macrocell' 4 requires 16 p-terms. In this case, the iPLS II software allocates 4 p-terms fro", the previous macrocell in Ring 1 (macrocell 3) and 4 p-terms from the next macrocell in Ring' 2 (macrocell S) to accumulate a tOtal of 16 p-terms (8 + 4 + 4). This implementation leaves macrocells 3 and S with a remainder of 4 p-terms each. These remaining p-terms in macrocells 3 and S can also be allocated away to or can be supple-' 2-96 Table 2. Product Term Allocation Rings Ring 1 Ring! PrevioUs Current Next ' Previous Macro- Macro- Macro- Macro- Macro- Macrocell cell cell cell cell cell 1 2 6 7 12 8 '3 2· 7 1 8 9 3 4 2 9 10 8 4 3 10 .11 9 5 5 4 11 12 10 8 8 1 5 12 7 11 Current Next ~ 5AC312 LOGIC ARRAY LOWER HALF P-TERWS 1-4 ,l IIIACROCELL P-TERIIIS ALLOCATED TO 1lACR0CELL 14 (NEXT MACROCELL IN RING) UPPER HALF P-TERIIIS 5-8 -B UPP£R HALF P-TERMS 5-8 P-TERMS ALLOCATED TO IlACROCELL ,4 (PREVIOUS IlACROCELL IN RING) 290156-6 FIgure 5. Product Term AllocatIon (8 + 4 + 4) 2·97 , . inter , o :, t, , 5AC312 Invert Select EPROM Bit Stand-by 'Function The invert select EPROM bit is used to invert the result of a logic combination achieved in a macrcicel/. ' prior to its input into the I/O control block of this particular macrocell. By employing this invert bit, certain equations can experience a reduction in Product Terms through the use of De Morgan's inversion. This feature is also supported by iPlDS II ,V1.5, though it can be disabled by the user. By programming a certain bit location in the 5AC312, a trade off between speed and power consumption can be selected for this .device. If this bit location, referred to as the "Turbo Bit", is left unprogrammed and no transition oCcurs at, the device inputs for a period of approximately 100 ns, the device will power-down the internal array while leaving the outputs driving at their previous levels. Once an input transition occurs, the 5AC312 will power-I,lp the array and react to the change in input conditions. The array power-up Sequence requires an average of 10 ns ,additional propagation delay for this function. Power supply current during power-down is typically no more than 150 p.A. Macrocell I/O Control Block Each macrocell in the 5AC312 has the ability to implement D, T, SR, and JK registered outputs as well as combinatorial outputs. The asynchronous set and reset inputs to each macrocell register allows implementation of true SR Flip-Flops. Registered outputs may be clocked from the synchronous ClKIINP1 pin or asynchronously clocked by the 2 Product Terms available for ASYNCH. elK. The 5AC312 also features separate input and feedback paths (dual feedback) on all macrocell I/O control blocks. This enables the designer to utilize input pins when the associated macrocells have been ass,gned a no output with buried feedback attribute. Multiplexed I/O is accomplished by controlling the output buffer associated with.each macrocell using the 2 Product Terms set aside for implementing an OE function. If this bit location is programmed, the power-down circuitry is disabled and the device will not power down even if there are "no activity" periods longer than 100 ns. This avoids the additional 10 ns delay in applications where performance is more important than power savings. inte"gent Programmlng™ Algorithm The 5AC312 supports the inteligent Programming algorithm which rapidly programs Intel H-EPlDs, EPROMs ,and Microcontrollers while maintaining a high degree of reliability. It is particularly suited for production programming erwironments. This method greatly .decreases the overall programming time while programming reliability is ensured as the incremental program margin of each bit has been verified in the programming process .. (Programming information for the 5AC312 'is avaUable from Intel by re". quest.) Powe ....On Characteristics The I/O registers of the 5AC312 will experience a reset to their inactive state upon Vee power-up. Using the PRESET function available to each macrocell, any particular register preset can be achieved after power-up. 5AC312 inputs and outputs begin responding approximately 20 p.s after Vee powElr-up or after a power-Ioss/power-up sequence. 2-98 5AC312 and also to graphically edit programming files. The software generates industry standard JEDEC object code output files which can be downloaded to other programmers as well. FUNCTIONAL TESTING Since the logical operation of the 5AC312 is controlled by EPROM elements, the device is completely testable during the manufacturing process. Each programmable EPROM bit controlling the internal logiC is tested using application-independent test patterns. EPROM cells in the 5AC312 are 100% tested for programming and erase. After testing, the devices are erased before shipments to the customers. No post-programming tests of the EPROM array are required. The testability and reliability of EPROM-based programmable logic devices is an important feature over similar devices based on fuse technology. Fuse-based programmable logic devices require a user to perform post-programming tests to insure device functionality. During the manufacturing pro- ' cess, tests on these parts can only be performed in very restricted manners in order to avoid a pre-programming of the array. INTEL PROGRAMMABLE LOGIC DEVELOPMENT SYSTEM II (IPLDS II) The iPLDS II has interfaces to popular schematic capture packages (including Dash series from FutureNet' and PC-CAPS" from PCAD) to enable designs to be entered using schematics. A more integrated schematic entry method is provided by SCHEMA II-PLD, a low-cost schematic capture package that supports EPLD primitives and user-defined macro symbols. SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both SCHEMA II-PLD and iPLS II software. The other deSign formats supported are Boolean equation entry and State Machine design entry. The iPLDS operates on the IBMt PC/XT, PC/AT, or other compatible machine with the following configuration: 1. At least one floppy disk drive and hard disk drive. 2. MS-DOStt Operating System Version 3.0 or greater. 3. 640K Memory. 4. Intel iUP-PC Universal Programmer-Personal Computer and GUPI Adaptor (supplied with iPLDS II) 5. A color monitor is suggested. Release 1.5 of iPLDS II graphically shown in Figure 6 provides all the tools needed to design with the 5AC312 EPLD. In addition to providing development assistance, iPLDS II insulates the user from having to know all the intricate details of EPLD architecture (the machine will optimize a deSign to benefit from architectural features). It contains comprehensive third generation software that supports four different design entry methods, minimizes logiC, does automatic pin assignments and produces the best design fit for the selected EPLD. It is user friendly with guided menus, on-line Help messages and soft key inputs. Detailed information on the Intel Programmable Logic Development System II is contained in a separate Intel data sheet. (Order Number: 280168) • FutureNet is a registered trademark of FutureNet Corporation. DASH is a trademark of FutureNet Corporation. •• PC-CAPS is a trademark of P-CAD Corporation. t In addition, the iPLDS II contains programmer hardware in the form of an iUP-PC Universal Programmer-Personal Computer to enable the user to program EPLDs, read and verify programmed devices IBM Personal Computer is a registered trademark of International Business Machines Corporation. tt MS-DOS is a registered trademark of Microsoft Corporation. 2-99 5AC312 Figure 6. IPLDS II Intel Programmable !.,ogle Development System 2-100 inter 5AC312 • Notice: Stresses above those listed under "Absolute MBXimum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute mBXimum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS· Supply Voltage (Vce> (1) ••....•••• -2.0Vto +7.0V Programming Supply Voltage (Vpp) (1) ..••.•..•.••• -2.0V to + 13.SV D.C. Input Voltage (VI)(l, 2) •.. -O.SV to Vee + O.5V Storage Temperature (Tstg) .•... -65"C to + 150"C Ambient Temperature (Tamb) (3) .. -1 O"C to + 8S"C NOTICE' Specifications contained within the fol/owing tables are subject to change. NOTES: 1. Voltages with respect to GND. 2. Minimum D.C. input is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods of less than 20 ns under no load conditions. ' 3. Under bias. Extended temperature range versions are available. D.C. CHARACTERISTICS TA = O"Cto +70"C, Vee = 5.0V ±5% Symbol VIH(4) VIL(4) VOH(5) Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage VOL Low Level Output Voltage 0.45 V II Input Leakage Current ±10 !LA loz Output Leakage Current ±10 !LA Isc!6) Output Short Circuit Current -90 rnA ISB(7) Standby Current 150 /J-A lee Power Supply Current 50 rnA Min 2.0 -0.3 2.4 Typ -30 Max Vee + 0.3 0.8 Unit V V V Test Conditions 10 = - 4.0 mA D.C., Vee = min. 10 = 4.0 mA D.C., Vee = min. Vee = max., GND < VOUT < VCC Vee = max., GND < VOUT < Vee Vee = max., VOUT = 0.5V Vee = max., VIN = Vee or GND, Standby Mode Vee = max., VIN = Vee or GND, No Load, Input Freq. = 1 MHz Active Mode (Turbo = Off), Device Prog. as 12-Bit Ctr. NOTES: 4. Absolute values with respect to device GND; allover and undershoots due to system or tester noise are included. 5.10 at CMOS levels (3.84V) = -2 rnA. 6. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second. 7. With Turbo Bit Off, device automatically enters standby mode approximately 100 ns after last input transition. CAPACITANCE Symbol CIN COUT CCLK Cvpp Parameter Input Capacitance Output Capacitance Clock Pin Capacitance VppPin Min Typ , 2-101 Max 20 20 20 50 Unit pF pF pF pF Conditions VIN = OV, f = 1.0 MHz VOUT = OV, f = 1.0 MHz VOUT = OV, f = 1.0 MHz Pin 1 5AC312 A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT ...---5V INPUT 3·°-Vz.O o..AO.8 855A J- DEVICE_[>--I--4~[>_ TO TEST OUTPUT- 3.UI. l=C L SYSTEM OUTPUT (INCLUDES JIG CAPACITANCE) > TEST POINTS VU <~ 1~~TEST P~INTS-~ 290156-8 A.C. Testing: Inputs are driven at 3.0V for a logic "I" and OV fer a logic "0". Timing Maasurements are made at 2.0V for a logic "I" and O.8V fer a logic ''0'' on Inputs. Outputs are maaourad at a 1.5V point. DEVICE INPUT RISE AND r ALL nMES<6nl 290156-7 ,cL = 50 pF A.C. CHARACTERISTICS Symbol From TA = O'C to + 70'C, Vee = 5.0V ± 5%, Turbo Bit "On"(8) 5AC312·25 To Min tpDl tpD2 tpZX(9) tpXZ(9) tClA tSET Input 1/0 I or 1/0 .1 or 1/0 Asynch. Reset Asynch. Set Comb. Output Comb~ Output Output Enable Output Disable QReset QSet Typ 20 20 20 20 20 20 Max 25 25 25 25 25 25 5AC312-35 Min Typ 30 30 30 30 30 30 Max 35 35 ~5 35 35 35 Non·(10) Turbo Mode Unit +10 +10 +10 +10 +10 +10 n8 n8 ns ns n8 n8 NOTES: 8. Typical values are at TA = 25°C, Vce = 5V, Active Mode. 9. tpzx and tpxz are measured at ±0.5V from steady·state voltage as driven by spec. output load. tpxz is measured with CL=5pF. . 10. If device is operated with Turbo Bjt Off (Non-Turbo Mode), increase time by amount shown. SYNCHRONOUS CLOCK MODE (MACROCELLS) A.C. CHARACTERISTICS TA = O'C to +70'C, Vee = 5.0V ±5%, Turbo Bit On(8) Symbol fMAX feNT tslJ1 tsU2 tH teo tCNT tCH tel 5AC312·25 Parameter Min 50 Max. Frequency 1/tsu-No Feedback Max. Count Frequency 33 1/tem-with Feedback Input Setup Time to ClK 20 1/0 Setup Time to ClK 20 I or 1/0 Hold after ClK High . 0 ClK High to Output Valid Register Output Feedback to Register Input-Internal Path ClK High Time 10 10 ClKlowTime Typ 5AC312·35 Non.(10) Turbo Mode Unit Typ 66 Min 40 50 N/A MHz 40 25 28.5 N/A MHz 15 15 25 25 0 20 20 +10 +10 ns ns ns 10 25 Max 15 30 2-102 - 10 35 12.5 12.5 Max 15 40 +10 +10 ns ns +10 +10 ns ns inter 5AC312 SYNCHRONOUS CLOCK MODE (INPUT STRUCTURE)A.C. CHARACTERISTICS = O·C to + 70·C, Vcc = 5.0V ± 5%, Turbo Bit On(8) TA Symbol Parameter 5AC312-25 5AC312·35 Min Typ 28.5 33 Min Typ fMAXI Max. Frequency 40 50 tSUIR Input Register Setup Time before IlE/IClK J., 5 tpLI(11 ) Minimum Input Clock Period tCOI IClK tHI I Hold after IClKlilE J., to Comb. Output J., Max Max Non-(10) Turbo Mode Unit N/A MHz ns 5 20 25 25 30 5 30 35 +10 35 40 +10 ns ns ns 5 tEal IlE t to Comb. Output +10 ns tcHI IlEIIClK High Time 10 12.5 +10 ns tCLI IlEIIClK low Time 10 12.5 +10 ns Non-(10) Turbo Mode Unit N/A MHz NOTE: 11. tpLi 30 35 35 40 = Input signal through registers/latch to macrocell register input. ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS TA = O·C to +70·C, VCC = 5.0V ±5%, Turbo Bit On(8) Symbol 5AC312-25 Parameter Typ Min 5AC312-35 Max Min Typ Max INPUT STRUCTURE fAMAXI Max. Frequency Input Register 1/ (tACLI + tACHI) 20 16.6 tASUI Input Register/latch Setup Time to Asynch. Clock 0 0 tAHI Input Register/latch Hold after Asynch. Clock 23 16 30 ns 25 +10 ns ~ tACOI Asynch. IClK to Output Valid 40 48 50 60 +10 ns tAEOI Asynch. IlE t to Comb. Output 45 53 55 65 +10 ns tACH I Asynch. IClK High Time 25 30 +10 ns tACLI Asynch. IClK low Time 25 30 +10 ns 20 16.6 N/A MHz 18.2 14.3 N/A MHz 7 10 +10 ns MACROCELLS fAMAX Max. Frequency l/(tACL + tACH)-No Feedback fACNT Max. Frequency l/tACN-r-with Feedback fASU1 Input Setup Time to Asynch. Clock 2-103 5AC312 ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS (Continued) TA = O·C to +70·C, Vcc = 5.0V ±5% , Turbo Bit On(8) Symbol 5AC312·35 5AC312·25 Parameter Min Typ Max Min Typ Max Non·(10) Turbo Mode Unit +10 ns +10 ns MACROCELLS (Continued) tASU2 I/O Setup Time to Asynch. Clock 7 tAH Input or I/O Hold after Asynch. Clock 23 tACO Asynch. ClK to Output Valid tACNT Register Output Feedback . to Register InputInternal Path 10 18 30 25 30 35 45 50 +10 ns 50 55 65 70 +10 ns tACH Asynch. ClK High Time 25 30 +10 ns tACL Asynch. ClK low Time 25 30 +10 ns Non·(10) Turbo Mode Unit INPUT·CLOCK·TO·MACROCELL·CLOCK A.C. CHARACTERISTICS TA = O·C to +70·C, Vcc = 5.0V ±5%, Turbo Bit On(8) Symbol Min tC1C2 5AC312·35 5AC312·25 Parameter Typ Max Min Typ Max Synchronous IlEIIClK Synchronous Macrocell ClK 25 35 +10 ns Synchronous IlEIIClK Asynchronous Macrocell ClK 5 10 +10 ns Asynchronous IlEIIClK Synchronous Macrocell ClK 48 65 +10 ns. Asynchronous IlEIIClK Asynchronous Macrocell ClK 20 50 . +10 2·104 ns inter 5AC312 SWITCHING WAVEFORMS COMBINATORIAL MODE INPUT OR I/o \V II\. I---tpD \1 I\. COMBINATORIAL OUTPUT tpxz HIGH IMPEDANCE COMBINATORIAL OR REGISTERED OUTPUT 3-STATE I----tpzx HIGH IMPEDANCE VALID OUTPUT 3-STArr -tACLR_ t ASET------ VALID OUTPUT \1 I\, ASYNCHRONOUSLY SET OR RESET OUTPUT 290156-9 SYNCHRONOUS CLOCK MODE (MACROCELLS) elK (fROM REGISTER TO OUTPUT) VALID OUTPUT 290156-10 2-105 5AC312 SWITCHING WAVEFORMS (Continued) SYNCHRONOUS CLOCK MODE (INPUT STRUCTURE) . _ / ILE.ICLK ~ICLI ICHI_ \. \ J \. lSUIR INPUT MAY CHANGE \V J\ \ - ____ J r t HI - . VALID INPUT ,/ J\ INPUT MAY CHANGE _ _ tCOI~ INPUT MAY CHANGE DATA VALID BEFORE 1~1 (SEE NOTE lEOI INPUT LATCH/REGISTER TO COMBINATORIAL OUTPUT INPUT MAY CHANGE . ,/ )\. VALID OUTPUT NOTE: WHEN ILE GOES HIGH BErORE DATA IS VALID. USE lPD INSTEAD OF lEOI. 290156-11 ASYNCHRONOUS CLOCK MODE (INPUT STRUCTURE) ASYNCH. ILE/CLK INPUT INPUT MAY CHANGE INPUT MAY CHANGE INPUT MAY CHANGE INPUT MAY CHANGE INPUT LATCH/REGISTER TO COMBINATIONAL OUTPUT VALID OUTPUT NOTE: WHEN ILE GOES HIGH BErORE DATA IS VALID. USE lPD INSTEAD OF lAEOI. 2-106 290156-13 5AC312 SWITCHING WAVEFORMS (Continued) ASYNCHRONOUS CLOCK MODE (MACROCELLS) ASYNCH. CLOCK INPUT FLOW THROUGH INPUT INPUT MAY CHANGE INPUT MAY CHANGE FLOW THROUGH INPUT TO REGISTERED OUTPUT VALID OUTPUT 290156-12 INPUT CLOCK-TOoMACROCELL CLOCK TIMING ILE,ICLK CLK 290156-18 Output Drive Current In Relation to Voltage r 1 a 50 20 I 10 - ...... ........ 5 2 1 o Conditions: TA = + 25'C 2 3 .. 5 Vo Output Voltage (V) 290156-16 2·107 APPLICATION BRIEF May 1986 Implementing Cascaded Logic in the 5C121 J. R. DONNELL APPLICATIONS ENGINEER PROGRAMMABLE LOGIC, Order Number: 292003·001 2·108 inter AN PROBLEM Designs that utilize numerous levels of cascaded logic often result in excessive product terms when expressed in the sum-of-products form. Although this poSes no problem when designing with discrete logic, EPLDs are generally optimized for the sum-of-product form. This stems from the architecture of the basic Macrocell. Macrocells typically consist of a programmable AND array feeding a fixed width OR gate. In the 5C121, OR gate widths range from four to sixteen inputs. For many applications, sixteen available product terms are sufficient. However, one example where product terms become an issue is cascaded exclusive-OR circuits. Here the number of product terms increase as 2"n where n equals the number of exclusive-OR gates. If the number of product terms exceeds sixteen, the equation will not fit directly in the 5C121. SOLUTION There is a simple solution to reduce the product term requirements when using cascading XOR (or other) logic. Figure 1 shows a circuit cascading five exclusive ORs. As designed, this circuit expands to 32 product terms when expressed in the minimized sum-of-products form. (This is assuming that signals A thru F are single product terms themselves.) Figure 2 shows the minimized logic equation file produced by Intel's Logic Optimizing Compiler (iLOC). An easy solution to fitting this logic into the 5C121 is to cascade three exclusive ORs together and then send the result through a No Output Combinational Feedback primitive (NOCF). This signal can now be cascaded through two more XOR's to get the five ,total. This circuit is shown in Figure 3. Figure 4 shows the logic equation file for this implementation. Note the reduction in product terms from Figure 2. If the buried registers are available, Intel's iPLDs software will automatically assign the combinational feedback to a buried register thereby saving a pin. This technique can be used for any circuit that generates excessive product terms. The only penalty in this method is the added delay needed for the feedback path. The worst case lpd (input to output delay) for the circuit in Figure 3 would be twice the specified Tpd in the 5C121-XX data sheet. Basically the signal must go through the device twice. For the 5CI21-90 the Tpd would be 180 ns worst case as implemented in Figure 3. Figure 5 shows the report file generated by the compiler. In this case the NOCF path was automatically assigned to the buried registers. :::JD-::lD-::l~D-:=J~.-----~ L../ E--J I lOUT I I ._----_ .. r 292003-1 FIgure 1. Cascaded Excluslve-ORs E I-------~ D-:=J~ r .------_. I lOUT I I Figure 3. cascaded Excluslve-ORs using Combinational Feedback 2-109 292003-2 5C12l cascading exclusive or's LB Version 3.0. Baseline l7x, 9/26/85 5C12l CASCADING 5XORS WUH COMBINUIONAL .FEEDBACK PARX: LB Version 3.0. Baseline l7x. 9/26/85 5C12l PARX: INPUXS: ApI Bp, CPt Dp. Ep. Fp 5C12l INPUXS : ' Ap. Bp. CPt Dp. Ep. Fp OUXPUXS: o OUXPUXS: NUWORK: A B C D E F 0 EQUA:rIONS: NO o INP(Ap) INP('Bp) INP(Cp) INP(Dp) INP(Ep) INP(Fp) CONF (NO. Vee) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NEXWORK: A B C D E F F • E' • D' • C' • A' • B' F' • E • D' " C' " A' " B' F' " E' " D " C' " A' " .I!' F' " E' • D' • C • A' • B' F' " E' •, D' • C' " A' • B F' • E' • D' • C' • A • B' F " E • D • C' " A' • B' F • E • D' • C • A' • B' F • E • D' • C' • A' • B F • E " D' " C' • A • B' F " E' • D • C • A' • B' F • E' • D • C' • A' • B F • E' • D • C' " A • B' F • E' • D' • C • A' • B F • E' • D' • C • ,A • B' F • E' • D' • C' • A • B F' • E • D • C • A' • 'B' F' • E • D • C' • A' " B F' " E • D • C' • A • B' F' • E • D' • C • A' " B F' " E • D' " C • A,,· B' F' * E • D' • C' • A • B F' • E' • D • C • A', " B F' " E' • D " C • A • B' F'· E' • D • C' • A * B F' * E' " D' * C • A • B F • E " D, • C • A' ,. B F • E • D • C • A " B' F • E • D " C' " A • B F • E • D' " C • A " B F " E' "D"C"A"B, F' " E • D * C " A • Bj INP(Ap) INP(Bp) INP(Cp) INP(Dp) INP(Ep) INP(Fp) o CONF (NO, Vee) N2 == NOCF (N3) EQUA:rIONS: N3 D· C' • A' • B' + D' " C • A' " B' + D' • ,C' • A' " B' + D' • C' " A • B' + D • C • A' " B + D " C " A " B' + D,· C' • A " B + D' • C • A • B j NO F· N2' • E' + F' " N2' " E + F' • N2 • E' +F·N2"Ej , Figure 4. Minimized Logic Equations for Figure 3 Figure 2. Minimized Logic Equations for Figure f 2.110 AN Logic- optimizing Compiler Utilization Report .. >t-**>t- Design implemented sueeessflJll y JRD INTEL Uetober 8, 1985 1 t.G121 CASCADING 5XURS WITH COMBINATIONAL FEEDBACK LB Version 3.0, Baseline 17x, 9/26/85 5C121 GNO GND GND GND GND GND GNt) GND GND GND GND GND GND GND GND GND GND GND GND GND -I 1 -I 2 -I 3 -/ 4 -I :; -I 6 -I "I -I 8 -I -110 -111 -112 -113 -114 -11t. -116 '" 401391381371361351341331321311301291- 28127126/25/- -11"1 24'·H -/18 -119 -120 23:- 22121/- Vee Vee Ap Bp Cp Dp Ep Fp 0 RESERVED RESERVED RESERVE:[) GND GND GND GND GND GNO GND GND **INPUTS** Namt" Pin Re!';ourct" fop 33 INP 1 Ep 34 INP 1 Dp 35 INP 13 Up .$0 INP 1.$ Bp 3"1 INP 13 38 INP 13 Name Pin Resource 0 3~ CONF Ap MC";ll # PTerms MCeHs Feeds: OE Clear Feerls: OE Clear Clock ... >t-UU1PUTS>I">I" MCeH # PTerms MCells 4/ 4 292003-3 2-111 ':r' AB·8 **aURIED REGJSTERS** Name Pin Resource HCell # Pfe,-ms NOCF 13 8/ 8 Resource HOell ,PHwms Feeds: HCeils OE Clear **UNUSED RESOURCES** Name Pin 1 2 3 4 5 6 7 8 12 28 27 26 25 24 13 :?s 14 15 16 17 18 19 21 22 22 21 20 19 18 17 12 ,23 10 .,. 10 11 24 25 26 27 28 29 3U 31 NA NA NA 11 9 8 7 6 5 4 3 2 14 15 16 4 10 8 6 f. 8 10 4 12 4 8 til 8 8 4 1:;> 4 10 t3 6 b 8 10 t3 8 8 **PART UTILIZATION** 18% 7% 5% Pins HacroCell s Pterms 292003-4 Figure 5. The Utilization Report 2-112 intJ AB~9 APPLICATION BRIEF May 1986 5C121 As A Three And One Half Digit Display Driver THOM BOWNS PROGRAMMABLE LOGIC APPLICATIONS INTEL CORPORATION Order Number: 292006"()01 2·113 .~B·9 INTRODUCTION Described is a method of constructing a multi-digit, seven segment decoder driver with .latching capability in a single EPLD. The design is a simple, easily understood method of using the 5el21 as a seven-segment display driver. This design has many advantages: (I) the ability to update a single digit without disturbing the others, (2) Outputs are latched and retain their data without update from the controlling device(s), (3) Input interfacing is simple and straightforward, using four data inputs, two digit select lines, and a data strobe line. The display driver interface is therefore not limited to microprocessor applications only (although it can be used with them). Possible applications include a Multimeter display, a clock or timer display, or a simple controller system display. PROBLEM The display driver needs to latch the incoming data at the correct time, route it to the correct digit, and then . decode the four bit data into seven-segment output format. SOLUTION IN EPLD A simple solution to the display driver imagine4 above . can be realized in the 5el21 EPLD. The 5el21 EPLD is organized in groups of Macrocells. Each Macrocell contains a number of multiple input AND gates which are feeding an OR gate. The OR gate feeds a selectable registered output. This output may also be routed back into the array for feedback purposes. Figure I shows a basic block diagram of the three and one half digit display driver. The data is input to a distribution block, which sends the data to one of four seven-segment decoders depending upon the digit selected by the Digit Select inputs. The outputs are updated by strobing the WR input. The data input is in a HEX fonnat and may be in the range of 0 to F HEX (0 to 15 Decimal). Digit select is placed upon the two select lines in a binary fonnat; 0, I, 2, 3. When data is present on the input lines and a digit is selected, the strobe line may be pulsed high and that output digit is then updated to the numeral suggested by the input data. Figure 2 illustrates the Boolean equivalents of the design in Figure 1. In the NETWORK section of Figure 2, the inputs and outputs of the design are described. For.instance, the NETWORK equation SSA1, SA1F = RORF (ISA1, WRN, GND, GND, VCC) represents that the output pin for segment "A" of the 1st Seven Segment display (SSAI) results from a Registered Output Registered Feedback (RORF) structure in the EPLD. The feedback signal (SAIF) is the same as the signal output (SSAI). The RORF's D input is driven by the signal ISAI, the clock input is driven by WRN, and reset, preset and output enable signals are tied to their default voltage levels (either GND or veC). The EQUATION section of Figure 2 shows how the data distribution and decoding logic works. Equations starting with A-G are generic seven segment display equations. Segment decoding results from the combination of the true or false of the four data inputs (e.g., DO or !DO). Equations such as SE1= (E' WE1) + (SE1F • !WE1) show how the data is distributed. Segment E of display . I (SEI) is valiq (ON) if the "E" decode exists and display 1 is chosert by the address inputs (WEI = !AO • !AI). It is also valid if it was previously turned on (SElF) AND s~ven segmj:nt display I is not selected (!WEI). These equations may be entered using LB in the fonn of a Netlist, or may be entered directly into the ADF by. means of a text editor. The ADF is then compiled and programmed into a 5el21 using iPLS. SUMMARY This method of using the 5el21 as a three and one half digit display driver is advantageous in respect to its simple interface, and its ability to hold all other digits stable while one is being updated. Displays with more than three and one half digits may be produced in the 5el21 by using the input latches as data storage and by multiplexing the outputs in a scanning fashion. 2-114 intJ AB-9 WRo--------------------------------, DECODE _ .....;;LA ...TCHES DOo----t D10----t D20----t DATA DISTRIBUTION 030---1 AO o----t A10---I SELECTION 292006-1 Figure 1. Block Diagram 2-115 inter Thorn Bowns Intel Dc tober- 2':;', U4 AB-9 198t. 1 5C121 3.5 digit output dr-iverLB Yer-sion 3~O, Baseline 17x, 9/26/85 PART: 5C121 INPUTS: AOp,Alp,00p,01p,0:?p,03P,WRp OUTPUTS: SSA1,SSB1,SSC1,SSD1,SSE1,SSF1,SSG1,SSA2, SSB2, SSC2, SSD:?, SSE2, SSF2, SSG2, SSA:':;, SSB:'>, SSC~;, SSD3, $SE3, SSF:':I, SSGl~;, SSA4 NETWORK: SSAl., SAIF .. RORF (rSA1, WRN, GND, GND, Yec) SSBI,SBIF." RORF (rSB1,WRN,GND,GND,YCC) SSCl,SClF :;: RORF (ISCl,WRN,GND,GND,VCC) BSDl,SD1F ~ RORF (rSOl,WRN,GNO,GNO,YCC) SSEl,SElF : : RORF (SEl,WRN,GND,GND,VCC) SSFl,SFlF :;: RORF (SFl,WRN,GND,GND,VCC) SSGl,SGlF :;: RORF (SGl,WRN~GND,GND,VCC) SSA:? , SA2F .. RORF (SA:?, WRN', GNO, GNO, Yee) SSB2,SB2F :;: R()RF' .(SB2,WRN,GND,GND,VGC) SSC2,SC2F - RORF (Se2,WRN,GNO,GNO,yeC) SSD2,S02F - RORF (SD2,WRN,GNO,GNO,YCC) SSE2,SE2F = RORF (SE2,WRN,GNO,GND,YGC) SSF2,SF2F = RORF (SF2,WRN,GNO,GNO,YGC) SSG2,SG2F = RORF (SG2,WRN,GND,GNO,YCC) SSA3,SA3F = RORF (SA3,WRN,GNO,GlND,YCe) SSB3,SB3F .- RORF (SB3,WRN,GNO,GNO,YCC) SSC3, SC::'~F .. RORF (SC:~, WRN, GNO, GND , Yee) SSD3,S03F- RORF (S03,WRN,GND,GNO,YCC) SSE3,BE3F - RORF (SE3,WRN,GNO,GND,YCC) SSF3, SF3F .. RORF (SF3, WRN, GNO, GND, Yce) SSG3,SG3F = RDRF (SG3,WRN,GND,GND,YCC) SSA4,SA4F :;: RORF (SA4,WRN,GND,GND,VCC) rSAl - NOCF (SAl) ISBI :: NOCF (SB 1) rSCl = NOCF (SCI) 1501 = NOCF (501) WRN = NOT (WR) WR •• INP (WRp) DO - INP (DOp) 01 ... INP (DIp) 02 = INP (D2p) 03 .. INP (O::'~p) AD _. INP (ADp) Al -_. INP (Alp) [(:;!UA TI ONS : A .. !03*!D2:+-!01*00 + !D3*D2*!fl1*!flO + D:I*!02*01*OD + 03*02-+:!D1*00; A -_. ! D3:+:02* ! 01*00 + D:?*D I:+: ! DO + 03*0:2*! 01:+- ! DO + 0:':,*01 *00; C :: !03*!02*01*!OO + D3>1:02*!Ol*!OO + E>3*D2*01; D .- !D3*!D2*!D1*DO + !D3*02*101*!00 + 02*01*00 + 03*!02*D1*!DO; E - ! 03* ! 02*00 t ! D3*D2* ! 01 ... ! D3*0:~:+:D 1*00 + 03*! D2* ! III *DO; F = !03*!02*!D1*00 + !DJ*!02*Dl + !03*02*01*00 + D3*02*!01*00; G -- ! D3:+:! 02*! 01 of ! n::l*D2*01 *00 + 03:+:02*! 01:+-! DO; 292006-2 Figure 2. ADF Listing 2-116 inter AB-9 Sfl = (E SFl * WE!) + (SElF (F * WEll + (SFlF (G * WEll + (SGIF (A * WE2) + (SA2F (B * WE2) + (SB2F (C * WE2) + (SC2F (0 * WE2) + (S02F SGl = SA2 = SB2 = SC2 = S02 = SE2 = (E * SF2 SG2 SA3 * IWEl); * lWEI); * IWEl); * IWE2); * !WE2); * IWE2); * IW(2); WE2) + (SE2F * IWE2): (F * WE2) + (SF2F * IWE2); = (G * WE2) + (SG2F * IWE2); (A * WE3) + (SA3F * IWE3); = (B * WE3) + (SB3F * IWE3); = (C * WE3) + (SC3F * I W(3) ; = (0 WE.:¢) + (S03F * IWE3); = (E * WE3 ) + (SE3F * IWE3); (F * WE3) + (SF3F * IWE3); (G * WE3) + (SG3F * IWE3); :; (A * WEll + (SAlF * lWEI); = (B * WEI) + (SBlF * IWEl); = (C * WEI) + (SClF * IWEl); = (0 -+< WE!) + (SOIF * lWEI); = «103*102*IOl*IOO) * WE4) + (SA4F * IWE4); = lAO * !Al; AO * !Al; = !AO * Al: = AO * Al; = SB3 SC3 S03 SE3 SF3 SG3 SAl SBI SCl SOl SA4 WEl WE2 WE3 WE4 ENO$ * = 292006-3 Figure 2. ADF listing (Continued) 2-117 inter APPLICATION BRIEF AB-10 June 1986 Square Pegs in Round Holes-A Fitting Tutorial for the 5C121 J. R. DONNELL PROGRAMMABLE LOGIC APPLICATIONS INTEL CORPORATION Order Number: 292014-001 2-118 inter AB-10 INTRODUCTION This application brief explores the various techniques for getting the most out of Intel's line of Erasable Programmable Logic Devices (EPLDs). In many cases, techniques discussed here will not be needed due to the intelligent fitting algorithms built into Intel's Programmable Logic Software (iPLS). As a matter of fact, most designs can be implemented in EPLDs without any knowledge of the device architectures. For complex designs, the designer will still need an in-depth understanding of the target EPLD in order to maximize the EPLD's utility. ' This application brief explores fitting techniques for the SC121, a 1200 gate equivalent CHMOS EPLD. The techniques described here will also apply to any EPLD that supports a similar architecture. FITTING When fitting logic designs into the SC121 there are two typical scenarios: 1) The SC121 design has been completed without pin assignments and the compiler warns the user that fitting may be time consuming, and 2) pin assignments have been made and the .. • .. ERR-FIT . . . " message comes up. Once the basic SC121 architecture is understood, intelligent pin assignments can be made. After assigning the pins recompile the design using iPLS. Compiling the design with pin assignments is a new ball game. This time it is fit or not fit. If the design does not fit, an error like: .. ···ERR-FIT-It is not possible to fit the specific pin requests you made" will occur. In most cases, the compiler will also ask if it can remove pin assignments and try its oWn. If the design has already been attempted without pin assignments, or if specific pin assignments are needed, answer no and isolate the problem. ISOLATE THE PROBLEM The first step towards isolating the problem is to print out a copy of the utilization report ( < Filename> .RPT), logic equation file « Filename> .LEF), and the Advanced Design File «Filename> .ADF). Next, fill out the SCl21 architecture worksheet included in this application brief. Include the signal name for each pin, the type of output, and the number of product terms needed for each output. All this information is available in the tiles that were printed earlier. The next step is to identify the conflict. Let's look at the first situation. CONFLICTS In general, if the designer does not care what signals get assigned to what pins, the choice can be left to the compiler and the compiler will make pin assignments. For simple designs pin assignments are very easy. However, designs that include a variety of different register types, feedback paths, and product term widths may take a long time for the compiler to fit. When the designer is faced with the message, "Fitting may be time consuming", the compilation should be aborted, and intelligent pin assignments made. NOTE: Control C (AC) may be used to abort a design. The software will not stop immediately because the software does not poll the keyboard until it updates the display. Rebooting the system will also work. There are three potential conflicts with pin assignments in the SC121; incompatible output structures, excessive product terms, and local/global feedback conflicts. Incompatible output structures and excessive product term errors are the easiest to spot. To make intelligent pin assignments, the designer needs a basic understanding of the architecture of the part. For the SCl21 this understanding should include the number of product terms supported in each Macrocell, what Macrocells support local feedback, and what Macrocells support global feedback. This information is easily found in the data sheet. One other point, the Macrocells in the SC121 are. grouped into groups of four. All Macrocells in a group must have the same output type. Therefore, if one output is registered, the other three must also be registered. This means that a combinatorial output could not be put into the same group as a registered output. Output enablt; (OE) terms are also based on Macrocell grouping. All four Macrocells are driven from the same OE term. INCOMPATIBLE OUTPUT STRUCTURES As shown in the SCl21 Design Worksheet, the SC121 is divided into six Macroce11 groupings. The data sheet refers to these as the A-I, B-1, A-2, B-2, A-3, and B-3 Macroce1ls. One requirement of the SCl21 architecture is that Macrocells within the same grouping have the same output structure. This was discussed earlier, but it is worth revisiting. The file titled example I in the appendix shows an ADF for a design that contains such an I/O conflict. Following the ADF is a completed SCl21 architecture worksheet with a number of problems. ~ncentrating on the incompatible output problem on the SCl21 worksheet, notice that pins 31 and 32 belong to the same Macrocell group, and that they are assigned conflicting I/O structures. The solution to an incompatible output structure conflict may be as simple as reassigning pins. Another option may be to use a different output type for that sig- ' 2-119 AB-10 nal. This is very dependent on the design. Another option is possible when a Macroce1l grouping has been assigned combinatorial output structure, and a registered output needs to be assigned to that same group. A possible solution is to use one of the buried registers configured as a NORF (No Output Registered Feedback) cell to hold the signal, and then send the signal out through a CONF (Combinatorial Output No Feedback) primitive. This output primitive is compatible with the other output primitives in that grouping, and the register output requirement has also been satisfied. The penalty is loss of speed due to the additional feedback path. EXCESSIVE PRODUCT TERMS Excessive product term conflicts are also easy to spot. (A product term consists of a set of signals ANDed together which are separated from other ANDed groups by an OR gate.) Written next to the I/O slot on the SC12l architecture worksheet is the number of product terms that each Macrocell supports. Match that number with the number of product terms for each output indicated in the logic equation me (LEF). If more product terms are required of a output than are provided, there is a product term conflict. The utilization report also shows the number of product terms used for each signal. The solution, again, may be as simple as reassigning pins since the SC12l supports varying product term widths. In fact, the SC12l supports up to 16 product terms on pins 16 and 24. Note that four of those product terms are shared with the adjacent Macroce1l. Sharing means that those signals are common. It is not product term allocation. If the number of product terms exceeds the capability of the device, the design may still fit by splitting up long equations and inserting NOCF (No Output Combinatorial Feedback) primitives. Again the price for using this solution is reduced speed. This technique is covered more thoroughly in AB-8 titled: Implementing Cascaded Logic in' the SCl21. LOCAL/GLOBAL FEEDBACK It is possible to encounter one other type of fitting conflict in the SC12l. This Occurs when a feedback signal from the A-I or A-2 Macrocells feeds the B-1 or B-2 Macrocells. The issue is that these Macrocells feed busses that are local to one half of the chip. Therefore, the signal is not physically available to the other side of the device. The best way to understand the local and global bussing in the SC121 is to divide the chip in ha1f1engthwise. One side contains the A Macrocells, and the other side contains the B Macrocells. The two sides, 8l'e mirror images. Speaking generically now, the -I and -2 Macrocells feed only local busses; local to their respective side of the ,device. The -3 Macrocells and the buried, registers feed global busses which route siinaIs to both sides of the device. Therefore a feedback signal coming from the A-lor A-2 group can only feed the A Macrocells, however, a feedback signal from the,A-3 group could feed the B-1, B-2, B-3, or the B buried Macrocells. This local/global bussing applies to both feedback and input signals on the I/O pins. All of the dedicated inputs f~ the global bus. Example 1 also shows a simple two bit counter with seven segment driver outputs. The worksheet shows that the counter registers were assigned to pins 27 and 28, while the seven segment outputs were assigne4 to pins 8 thru 14. The seven segmellt outputs decode the feedback signals from the counter registers to generate the appropriate digit output, and therefore must have access to those signals. This presents a local/global feedback conflict.' If the designer is locked into those specific pin assignments a design workaround is needed. One solution might be to take the outputs of the counter and externally tie them to dedicated input, pins thereby making those signals global. This would work but that solution ends up wasting input pins. A better solution would be to internally route the counter feedback signals through one of the buried registers configured as a NOCF primitive. After passing through the buried register the signals become global. Both the incompatible output solution and this solution are shown in the worksheet, ADF, and utilization report shown as 'example 2. If we did not need the counter signals externally, it would of been wise to simply use the buried registers to perform the counting function. One final comment regarding the utilization report. The utilization report shown in example 1 indicates that signa1s CLK and CNT feed Macrocell 1001 and 1002. These are fictitious Macrocell numbers that the software assigns to requests that cannot be met. In example 1, three requests were unfuImled: REGOUT, LEDI and LEDO. REGOUT was unfulfilled because of incompatible output structures. LEDO and LED 1 were unfulfilled because their feedbadt signals needed to drive the seven segment display outputs. This was impossible because the LED outputs were assigned to a local bus on the opposite side of the device. The mes shown in example 2 fix the LED fitting problems by sending the feedback signals through the buried registers, thereby making them global. In the case of REGOUT, the buried register primitive NORF (No Optput Registered Feedback) is used, allowing the output primitive to be combinatorial. 2-120 inter AB·10 EXAMPLE 1 ADF . JR Donnell Iatel April 3, 1986 o 5C12l rit tin, exa_ple LB Veraion 3.0, Baae1iae 17x, 9/26/85 PART: 5C12l INPUTS: CNT82,CLI81 OUTPUTS: LBD0828,LBDI.27,RBGOUT.32,CONrOUT83l,SBGA88, SBGI89,SBGC8l0,SBGD8ll,SBGB8l2,SBGr8l3,SBGG814 NBTWORI: LBDO,A = RORr (NLBDOD,CLI,GND,GND,YCC) LBDl,B = RORr (NLIDID,CLI,GND,GND,YCC) RBGOUT = RONr (NRIGOUTD,CLI,GND,GND,YCC) CONrOUT = CONr (NCONrOUTIN,YCC) SBGA CONr (NSIGAIN,YCC) SBGI CONr (NSBGIIN,YCC) SIGC CONr (NSBGCIN,VCC) SBGD CONr (NSBGDIN,YCC) SIGB CONr (NSBGIIN,YCC) SBGr CONr (NSBGrIN,YCC) SBaG CONr (NSBGGIN,YCC) CLI = INP (CLI) CNT = INP (CNT) BQUATIONS: NSBGGIN = 2 + 3; 2 = U/A; 3 = A'I; NLBDID = IA'/I'CNT + IA*U/CNT + A*/I'CNT + A*U/CNT; NLBDOD = IA'I'CNT + A*/U/CNT + "/UCNT + AU'ICNT; NSBGrIN = 0; o = IB'/A; NSBGBIN 0 + 2; NSBGDIN 0 + 2 + 3; NSBGCIN 0 + I + 3; 1 = II'A; NSBGIIN 0 + 1 + 2 + 3; NSBGAIN 0 + 2 + 3; NCONrOUTIN A'I; NRBGOUTD = IA*/I; BNDt 292014-2 2-121 AB-10 SUMMARY As programmable logic devices become more dense, signal routing and resource partitioning becomes necessary. In general, these choices are made by the semiconductor manufacture to most efficiently utilize the available logic. In some cases though, these choices make certain designs more difficult to implement in a given device. Intelligent software, a basic knowledge of the device architecture, and a little experience in fitting techniques will always make' the job easier. EXAMPLE 1 (Continued) 5C121 Design Worksheet ~ ~ ~ ~ ~ ..lli!L ~ ~ ..ill2- ~ ..lli.L 292014-1 2-122 inter AB·10 EXAMPLE 1 (Continued) Lo.ie Opti.isin. Co.piler Utili •• tion Report ***** Un.ble to i.ple.ent de.i.n JR Donnell Intel April 3, 1986 o 5C121 rHtin. ex . .ple LI Ver.ion 3.0, I ••• line 17x, 9/26/85 I5Cl21 CLK Cllf GilD GilD GND GilD GilD SlGA SIGB SIGC SIGD SIGI SlGr SlGG RISIRYBD GilD GilD GilD GND GilD -: -: -: -: -: -: -: -: -: 1 2 3 4 5 6 7 8 9 -:10 -111 -: 12 -: 13 -:14 -: 15 -:16 -: 17 -: 18 -:19 -:20 40:39:38:37:36:315:34:- 33:- 32:31:30:29:28:27:26:215:24:23:22:21:- Yee Vee GilD GilD GilD GilD GilD GilD RISBRYBD COllrOUf RISIRYID RISIRYBD GND GilD GilD GilD GilD GilD GND GilD **IIIPUts** N••• MCell • PiD Be.ouree CLE 1 IIiP CIIT 2 IIiP 1I•• e PiD a•• oure. MC.ll • PT.r•• SIGA II cOllr 28 2/ 4 SIGB 9 con 27 2/10 SIGC 10 cOllr 26 2/ 8 SlGD U con 215 2/ 6 Pfer•• MCeU. re.d.: 01 Cle.r Clock R•• 1001 1002 **OUTPUTS** MCeU. r.ed.: 01 Cle.r 292014-3 2-123 inter AB-10 EXAMPLE 1 (Continued) SIOI 12 COIIF 24 SlOf 13 COIIF 23 1/ 8 SIOO 14 COIfr 22 1/10 COMfOUT 31 COIfr 2 1/10 R•• ourc. ROHr MCell • 1000 PT.r•• 1 MC.U. LIDI RORr 1001 2 2 22 23 26 26 28 1000 1001 1002 LIDO ROar 1002 3 2 23 24 26 36 27 28 1000 1002 R•• ource MC.U PT.r•• 21 20 19 18 17 4 12 4 8 8 8 8 4 1/ 6 **UHfULfILLID RIQUISTS** **OUTPUTU* Ha •• R800UT Pin f •• d.,: 01 Clear **UHUSBD RISOURCRS** Ha•• PiD 3 4 6 6 7 16 16 17 18 19 21 22 23 24 26 26 27 28 29 30 32 33 34 35 36 37 38 NA HA HA HA 12 11 10 9 8 7 6 6 4 3 1 13 14 15 16 12 4 10 8 6 6 8 4 8 8 8 8 2·124 292014-4 292014-5 inter AB-10 EXAMPLE 2 ADF JR DODDell IDtel April 3, 1986 o 5C121 rittlD. ex •• ple L8 Ver.ioD 3.0, B•• el1De 17x, 9/26/85 PART: 5C121 INPUTS: CNTe2,CLIel OUTPUTS: LBDOe28,LBD1.27,RIGOUTe32,CONrOUTe31,SIGAe8, SIG8e9,SIGCelO,SIGDell,SIGle12,SIGre13,SIGGe14 NITWORI: LIDO,NATONOCr = RORr (NLIDOD,CLI,GND,GND,VCC) LID1,NBTONOCr = RORr (NLIDID,CLI,GND,GND,VCC) RIGOUT = CONr (NRIGOUTIN,VCC) CON rOUT = CON' (NCONrOUTIN,VCC) SIGA CONr (NSIGAIN,VCC) SIGB = CONr (NSIGBIN,VCC) SIGC CONr (NSIGCIN,VCC) SIGD CONr (NSIGDIN,VCC) SIGI CONr (NSIGIIN,VCC) SBGr CONr (NSIGrIN,VCC) SIGG CONr (NSIGGIN,VCC) A = Nocr (NATONOCr) CLI = INP (CLK) B = Nocr (NBTONOCr) NRIGOUTIN = NORr (NIIOOUTD,CLI,GND,GND) CNT = INP (CNT) IQUATIONS: NLIDOD = IAtBtCNT + At/U/CNT + At/B*CNT + A$B*/CNT; NLIDID = IAt/B*CNT + IAtB*/CNT + At/UCNT + An*/cNT; NCONrOUTIN = AtB; NSIOAlN ;= 0 + 2 + 3; NSIOBIN 0 + 1 + 2 + 3; NSIOCIN 0 + 1 + 3; HSIGDIN 0 + 2 + 3; NSIOIIN 0 + 2; NSlorIN 0; HSIOGIN 2 + 3; NRBGOUTD = IAt/B; 2 = B*/A; 3 = AtB; o = IBt/A; 1 = IUA; IND. 292014-7 2-125 AB-10 EXAMPLE 2 (Continued) 5C121 Design Worksheet ~ SEGB ~ ~ ~ ~ ~ ~ ~ ~ ....!!Q!.... 292014-6 2-126 intJ AB-10 EXAMPLE 2 (Continued) Logic OptiaiaiDg Coapiler UtiliaatioD Report ***** De.igD iapleaeDted succe.sfully JR DODDel1 lDtel April 3, 1986 o 5C121 FittiDg exaaple LB YeraioD 3.0, BaseliDe 17x, 9/26/85 5C121 CLK CNT GND GND GIfD OIfD GIfD SIGA SIGB SlGC SIGD SIOI SBOr SIGO RBSIRYIID GIfD GIfD GIfD GIfD GIfD -: 1 -: 2 -: 3 - 4 -: 5 -: 6 -: 7 -: 8 -: 9 -:10 -: 11 -: 12 -: 13 -:14 -: 15 -:16 -: 17 -: 18 -: 19 -:20 40:39:38:37:36:35:34:33:32:31:30:29:28:27:26:25:24:23:22:21:- Ycc Ycc GND GND GIfD GIfD GIfD GIfD RIGOUT COIfFOUT RBSIRYIID RBSIRYIID LIDO LBD1 RBSlRYIID RISIRYID GND GIfD GND OIfD *'IIfPUTS*, Feede: PiD Resource CLK 1 IIfP CIfT 2 UP Ifaae Ph Resource MCell It PTeras SlOA 8 COIfF 28 2/ 4 SIIGB 9 cOlfr 27 2/10 SIIGC 10 COIfF 26 2/ 8 SliGO 11 COIfF 25 2/ 6 He.e MCell It PTer.s MCell. 011 Clear Clock Reg 5 6 *,OUTPUTS*, MCella Feed.: O! Clear 292014-8 2-127 intJ AB-10 - EXAMPLE 2 (Continued) ••a. 12 co., 24 SlGr 13 co.r 23 1/ 8 8.aa 14 cOllr 22 1/10 1/ 6 L.D1 27 RO.r 8 2/ 8 13 L.DO 28 Ro.r II 3/ 8 14 OOllrou'l 31 oOllr 2 1/10 ••aou" 32 cOllr 1 1/ 4 ••BU.I.D ••aI."••••• •••• Pia ••• ouro • 110.11 • P".r•• lIO.n. .ocr 13 1/ 8 2 r ••d.: o. 01.ar II 8 15 22 23 25 28 28 lIocr 14 1/ 8 2 II 15 23 24 25 28 27 28 110.' 15 1/ 8 ••• oure. 110 a 11 P'I.raa 17 21 20 18 18 12 21 22 17 12 11 1 "UIIU•• D •••OUIC•••• 11_. Pla 3 4 II 8 7 15 18 18 18 23 24 211 28 28 4 4 ..8 8 8 4 10 8 8 12 7 10 4 4 8 292014-9 2·128 inter AB-10 EXAMPLE 2 (Continued) 30 3 8 16 6 33 34 31i 36 37 38 NA **PART UTILIZATION** 31ill: 1i0ll: lOll: Pl •• MBcroCe11. pter•• 292014-10 2·129 inter AB~11 APPLICATION BRIEF February 1987 16-Bit Binary Counter Implementation Using the 5C060 EPLD KARL-HEINZ WEIGL INTEL CORPORATION MUNICH, GERMANY Order Number: 292015-002 2-130 inter AB-11 INTRODUCTION TOGGLE FLIP-FLOPS System designers often use programmable logic devices to implement counters. Use of PLA devices lets the user build customized counters to suit individual applications. In most cases such counters are not available, 'off-the-shelf SSI/MSI devices. In other applications, the PLA implementation allows the designer to squeeze the counter function along with other 'glue' tasks into a single PLA, with the attendant higher integration benefits. Counters can be most effectively implemented in PLA architectures using toggle flip-flops. This is because counters constructed with 'D' type flip-flops require an additional product term for every successive significant bit, whereas toggle flip-flop implementation requires only one product term per significant bit. Thus, the toggle flip-flop counter design is more miserly in product term consumption than the 'D' register design. Since product term minimization is the key element to maximizing PLA utilization, the T-FF counter design is more efficient. The truth table for the toggle flip-flop is shown in Fig; 2. Use of traditional 20-pin and 24-pin PLAs, however, does not allow for the construction of large counters having greater than 10 significant bits. This is because these traditional PLAs have register and product term restrictions (even the larger bipolar PLAs have only 8 to 10 registers and less than 8 product terms per register). In contrast, the 5C060 24-pin erasable programmable logic device (EPLD) contains 16 registers that are programmable as 'D', 'T', 'RS' or 'JK' types. These 16 programmable registers enable the construction of Up/Down counters with up to 16 significant bits. T Q(N) 0 0 1 1 0 1 0 1 Q(N + 1) 0 1 1 0 Figure 2 This application brief details the implementation of a l6-bit binary counter in the 5C060 EPLD. The design also demonstrates efficient counter construction utilizing toggle flip-flops (T-FF) that allows for minimum product term utilization. DESIGN OBJECTIVE The objective of the design is to implement a counter with the following features: (i) l6-bit binary count, (ii) toggle flip-flops, (iii) asynchronous clear, (iv) RUN/ 'STOP function and (v) UP/DOWN function. The function table is shown in Figure 1. RESET UP/DOWN RUN/STOP X 0 0 1 X 0 1 X 0 1 1 X Function SOLUTION The l6-bit binary counter function was implemented in the SC060 EPLD using the Intel Programmable Logic Development System (iPLDS). The equations for the l6-bit bin~nter with the RESET, UP/DOWN and RUN/STOP functions are shown in the 'EQUATIONS' section of the LEF (Fig. 4). The pinout of the SC060 with the implemented counter is shown in the RPT file (Utilization Report) Fig. S. This RPT file also shows, under the 'OUTPUTS' section, that in each macrocell only one out of 8 product terms is used. In contrast the same l6-bit counter designed using 'D' type flip-flops would have required more than 16 product terms for the last significant bit. Inhibit Counting CountDown Count Up Reset All Outputs to 'LOW' Figure 1 2-131 AB-11 INTEL CORPORATION JAN. 15, 1987 1 . 1.0 5C080 BIliARY 18-BIT UP/DOIIN COIJIITIR WITH RUNISTOP AND ASYlICH. usn USING T-J'J' LB Version 4.01, Baseline 27.1 4/9/86 OPTIONS:TURBO=ON PABT: 60080 INPUTS: RS, CLOClt,RESll:T.,UD OUTPUTS: 'GIG, Ql,1I2,Q3;at,Q5,Q8,Q7 ,Q8, Q9,QA,IIB~QC,QD,QI,GII' lIITIIOIUt : GIG,QOJ' ~ TOn (QOT, CLK ,CLR,GIID, vec) Ql,Q1J' TOTJ' (Q1T ,CLK,etR,GIID, VCC) Q2,Q2J' = TOn (Q2T,CLK,CLR,GND,VCC) Q3,Q3J' = ~J' (Q3T,CLK,cLB,GIID,VCC) at,atJ' = TOn (Q4T,CLK,CLR,GIID, VCC) Q5 ,Q8J' TOTJ' (Qn, CLK, CLB, GND, VCC) Q8, QaJ' TOn (Q6T, CLK, CLB, GIlD, VCC) Q7 ,Q1J' TOn (Q7T, CLK, CLR, GND, VCC) Q8,Qat TOTt (QaT,CLK,CLB,GIID,VCC) Qe,Qer = TOn (QaT,CLK,CLR,GND, VCC) QA,QAJ' = TOTJ' (QAT,CLK,CLB,OND,VCC) lIB, QBJ' = TOTJ' (IIBT, CLK, CLB, GIlD, VCC) QC, QCJ' TOn (QCT, CLK, CLB, OND, VCC) QD, QDJ' = TOn (QDT, CLK, CLB, GND, VCC) QI, QIJ' = TOTJ' (QlT, CLK, CLB, GND, VCC) GIl' TOIQ' (QJ'T, CLK, CLB, GND, VCC ) QOT OR (QOU,QOD) CLK IIIP (CLOCK) CLR IIIP (RESII:T) Q1T OR (Q1U,1I1D) Q2T. = OR (Q2U,Q2D) QaT OR (Q3U,Q8D) atT OR (atU,atD) QaT OR (Q5U,Q5D) QaT = OR (Q6U,QaD) Q7T = OR (Q7U,Q7D) QaT =OR (Q8U,QaD) Q9T. OR (QeU,QeD) QAT = OR (QAU,GIAD) QBT OR (GIllU, QBl» = = = = = = = = = = = = = = = = QCT = OR QDT = OR Cll:T = OR QJ'T = OR as = IIIP UD = IIIP (QCU,QCD) (QDU,QDD) (CII:U, CII:D) (QI'U, QJ'D) (RS) (UD) IIUD = !lOT (UD) 'lOu = AND (UD,RS) 292015-1 Figure 3. Example .ADF 2-132 inter Q1U QIU QlU Q'U Q&U QeU Q7U QeU Q8U AB-11 = AIID (UD,QOI',QOU) (UD,Qll',Q1U) (UD,Q2J',Q2U) = AIID (UD,Q3I',Q3U) = AIID (UD,QU ,Q4U) = AIID (UD, Q5I' ,Q5U) AIID (UD,QeI' ,QeU) AIID (UD,Q7I',Q7U) = AlII) (UD,Q81' ,Q8U) QAll = AlII) (UD,Q81' ,QeU) QJIU AlII) (UD, QAI' ,QAU) QCU = AlII) (UD, QIII' ,QJIU) QI)IJ = AIID (UD, QCJ' ,QCU) QIU = AIID (UD,QDI' ,QDU) QfU = AIID (UD,GlD,QIU) RQOr = MOT (QOI') RQU MOT (QU) *1' MOT (Q21') MQ31' MOT (Q31') MQU = MOT (~I') I1Q5I' MOT (Q&I') MQ81' = MOT (Qel') MQ7r = MOT (Q71') MQ81' = MOT (Q81') IIQII' = MOT (Q8I') lIQAI' = MOT (QAI') ltQBI' MOT (QIII') IlQCI' MOT (QCJ') MQDI' = MOT (QDI') JIQIJ' = MOT (QBI') QOD = AIID (IIUD,JIS) Q1D = AIID (NOD,RQOI',QOD) QID AIID (NOD,RQU,Q1D) Q3D = AIID (NOD, MQ2J' ,Q2D) ~D AIID (NOD,RQ31' ,QaD) Q&D AlII) (NOD,MQU,~D) QeD = AlII) (NOD,RQ51' ,Q5D) Q7D = AlII) (NOD, RQIII' ,QBD) QeD = AlII) (NOD,MQ7r,Q7D) QeD AlII) (NOD, MQ81' ,QeD) QAD AlII) (NOD,RQ8I',QeD) QBD AlII) (NUD, NQAI' ,QAD) QCD AlII) (NOD, NQBI' ,QBD) QDD = AlII) (NOD, NQCJ' ,QeD) QED = AlII) (NOD, NQDI' ,QDD) QrD AlII) (NOD, JIQIJ' ,QED) = AIID = AIID = = = = = = = = = = = = = = = = = DDt 292015-2 Figure 3. Example .ADF (Continued) 2.133 inter AI!I-11 IRTEL CORPORATIOR JAN. 15, 1981 1 1.0 5C080 BINARY 18-BIT UP/DOWR COURTER WITH RUN/STOP AND ASYNCH. RESET USING T-Fr LB V.ralon 4.01, Bea.lln. 21.1 4/9/88 LEF Veralon 4.01 B.... Un. 22.2 2/4/88 OPTIORS: TURBO.ON PART: 5C060 INPUTS: RS, CLOCK, RESET, UD OUTPUTS: NETWORK: ~,~,~,~,~,~,~,~,~,~,~,~,~,~,~,~ CLK • INP(CLOCK) RS • INP(RS) CLB • INP(RESET) UD • INP(UD) ~, ~F • TOTF(~T, Ql. Q1F • TOTF(Q1T. Q2, Q2F • TOTF(Q2T, Q3, Q3F • TOTF(Q3T, Q4, ~F • TOTF(Q4T, Q5, Q5F • TOTF(Q5T, Q6, Q6F • TOTF(Q6T, Q1, Q1F • TOTF(Q1T, Q6, Q6F • TOTF(QaT, ~, Q9F • TOTF(Q8T, ~, ~ • TOTF(~T, ~, ~ • TOTF(~T, CLK, CLB, GRD, VCC) CLK, CLR, GRD, VCC) CLK, CLB, GRn, VCC) CLK, CLB, GRD, VCC) CLK, CLB. GRD, VCC) CLK, CLR, GRD, VCC) CLK, CLB, GRn, VCC) CLK, CLR, GRn, VCC) CLK, CLB, GRn, VCC) CLK, CLB, GRD, VCC) CLK, CLB, GRD, VCC) CLK, CLB, GRn, VCC) ~, QCF • TOTF(~T, CLK, CLB, GRD, VCC) ~, ~F • TOTF(QDT, CLK, CLB, GRD, VCC) ~, ~F • TOTF(~T, CLK, CLB, GRn, VCC) QF • TONF(QFT, CLK, CLR, GRn, VCC) EQUATIORS: ~T • UD' * ~r' * ~r' * QCF' * ~' * ~' * Q9F' * Q6r' * Q1r' * Q6r' Qsr' * ~r' * Q3r' * Q2r' * Qlr' * QOr' * RS + UD * QEF * ~r * QCF * ~ * ~ * Q9r * Qar * Q1r * Q6r * Q5r ,* Q4F Q3r Q2F Q1F QOr RS; * * * * * QET • UD' * QDF' * ~r' * ~r' * ~' * Q9r' Q4F' Q3r' Q2r' Qlr' QOr' RS * * * * * * * Q6r' * QU' * Q6r' * QU' * +~*~*QCF*~*~*~*~*~*~*~*~* Q3r ~T • UD' * Q2F * Qlr * QOr * RS; * QCF' * ~' * ~' * Q8r' * Q6r' * Q1F' * Q6F' * Q5r' * Q4r' * * * * * * Q3r' Q2r' QU' QOr' RS ' +~*QCF*~*~*m*~*_*~*~*~*~* Q2r Qlr QOr RS; * * 292015-3 Figure 4. Example .LEF 2-134 inter AB-11 * * * * * * * * * * QCT = UD' QBF' QAF' Q9F' QaF' Q7F' Q6F' Q5F' Q4F' * Q31" Q2F' * Q1F' * QOF' * RS +~*~*QAF*~*~*~*~*~*~*~*~* Q1F QOF RS; QBT = UD' * QAF' * Q9F' QaF' Q7F' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F' Q1F' QOF' RS +~*QAF*~*~*~*~*~*~*~*~*~* QOF RS; * QAT = ~' * Q9F' * QaF' * Q7F' * Q6F' * Q5F' QOF' RS + UD Q9F QaF Q7F Q6F Q5F Q4F RS; * * * * * * * * * * * * * * Q4F' * Q3F' * Q2F' * QU' * Q3F * Q2F * Q1F * QOF * QaF' * Q7F' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F' * Q1F' * QOF' * QaF * Q7F * Q6F * Q5F * QU * Q3F * Q2F * Q1F * QOF * RS; Q8T = UD' * Q7F' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F' * Q1F' * QOF' *' RS + UD * Q7F * Q6F * Q5F * Q4F * Q3F * Q2F * Q1F * QOF * RS; Q7T = UD' * Q6F' * Q5F' * Q4F' * Q3F' * Q2F' * Q1F' * QOF' * RS + UD * Q6F * Q5F * QU * Q3F * Q2F * Q1F * QOF * as; Q6T = UD' * Q5F' * QU' * Q3F' * Q2F' * Q1F' * QOF' * RS + UD * Q5F * Q4F * Q3F * Q2F * Q1F * QOF * RS; Q5T = UD' * Q4F' * Q3F' * Q2F' * Q1F' * QOF' * RS + UD * Q4F * Q3F * Q2F * Q1F * QOF * RS; Q4T = ~' * Q3F' * Q2F' * Q1F' * QOF' * RS + UD * Q3F * Q2F * Q1F * QOF * RS; Q3T = UD' * Q2F' * Q1F' * QOF' * RS + UD * Q2F * Q1F * QOF * RS; Q2T = UD' * Q1F' * QOF' * RS + UD * Q1F * QOF * RS; Q1T = UD' * QOF' * RS + UD * QOF * RS; Q9T * = UD' * RS * + UD QOT = RS; ENDS 292015-4 Figure 4. Example .LEF (Continued) 2-135 intJ AB-11 Lo.10 Opt,111181n. Compiler Ut,il1zat,1on Report, FIT Version 4.01 Base11ne 27.1 4/9/86 ***** De.ian 1lDpleJDen'ted **** NOTE: suoce~sf\llly Connect, sipal CLOCK t.o pin 1 AND pin 13. INTIL CORPORATION JAN. 15, 1987 1 1.0 5C080 BINARY 18-BIT UP/DOWN COUNTER WITH RUN/STOP AND ASYNCH. RESET USING T-FF' LB Version 4.01, Baseline 27.1 4/9/86 OPTIONS: TURBO=ON 6C060 CLOCK -: 1 GND -: 2 Q7 -: 3 QS -1,4 Q6 -: 5 Q4 -: 8 Q3 -: 7 Q2 -: 8 Ql -: 9 QO -:10 UD -:11 GND -:12 24:- Vee 23:- RS 22:- QF 211- QI 201- Q1J 19:- QC 18:17:- QB QA 16:- Q9 15:- Q8 14:- RESET 13: - CLOCK **INPUTS** NUle Pin CLOCK Resource HCell II PTems HCells Feeds: OE ' Clear IMP UD 11 IMP GND 12 GND CLOCK 13 IMP RESET 14 IMP Clock CLKl CLK2 1 2 3 4 5 8 7 8 9 10 11 12 13 14 15 CLK1 CLK2 1 2 3 4 5 8 7 8 9 10 11 12 13 14 15 16 292015-5 Figure 5. Example .RPT File 2-136 AB-11 as 23 IRP 1 2 3 4 6 8 7 8 8 10 11 12 13 14 15 18 Vee 24 Vee 1 2 3 4 6 8 7 8 8 10 11 12 13 14 16 18 **OUTPUTS** ..... Pin a.sourc. Keell • PT..... He.ll. Q7 3 '1'OTI' 8 2/ 8 1 2 3 4 Ii 8 7 8 Q8 4 TO'lI' 10 2/ 8 1 2 3 r ••ds: 01 Clear Clock 4 Ii 8 7 8 8 QIi Ii TO'lI' 11 2/ 8 1 2 3 4 Ii 8 7 8 8 10 Q4 8 '1'OTI' 12 2/ 8 1 2 3 4 Ii 8 7 8 8 10 11 292015-8 FIgure 5. Example .RPT File (Continued) 2·137 intJ Q3 7 TOTF 13 2/ 8 1 2 3 4 5 6 7 8 9 10 11 12 Q2 8 TOTF 14 2/ 8 1 2 3 4 5 6 7 8 9 10 11 12 13 Q1 8 TOTF 15 2/ 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 QO 10 TOTF 18 1/ 8 1 2 3 4 5 6 7 8 8 10 11 12 13 14 15 Q8 15 TOTF 8 2/ 8 1 2 3 4 5 8 7 Q9 18 TOTF 7 2/ 8 1 2 3 4 5 8 QA 17 TOTF 6 2/ 8 1 2 3 4 5 292015-7 Figure 5. Example .RPT File (Continued) 2·138 AB-11 QB 18 "rOD II 2/ 8 1 2 3 4 QC 18 TOU 4 2/ 8 1 2 3 QI) 20 TOTr 3 2/ 8 1 2 CD 21 "rOD 2 2/ 8 QI' 22 TOIIJ' 2/ 8 **lJII1ISBI) BISOUlICBS** N_ PiD Re.ource Keell PTerae 2 **PART OTILlZATION** 811" 100" 24" PiD. HacroCells Pteru 292015-8 Figure 5. Example .RPT File (Continued) 2·139 APPLICATION BRIEF AB-12 October 1987 Designing a Mailbox Memory for Two 80C31 Microcontrollers Using EPLDs K. WEIGL & J. STAHL INTEL CORPORATION MUNICH, GERMANY Order Number: 292016-002 2-140 inter AB-12 The SC060 allows for independent clocking of 8 macro- INTRODUCTION cells on each side of the chip, the two clock inputs are Very often, complex systems involve two or more microcontrollers to fulfill the requirements dermed by a given objective. Since the nature of microcontrollers does not allow for easy dual-port memory design (no "READY" input; no "HOLD/HLDA" interface; portoriented I/O etc.), design' engineers are faced with the problem of interchanging information (data and status) between those microcontrollers. This application brief describes the design of a mailbox for exchanging information between two 8OC31s, using a SC060 H-EPLD as a "back-to-back" register, and a SC031 H-EPLD as an arbitration vehicle to control the· actions of the CPUs. used to clock data from the microcontroller bus into the chip. To read the data written into the mailbox by one of the controllers, the RDA- (controller A is reading) or RDB- (controller B is reading) line must be pulled low by activating the read command (/RD). In order to avoid spurious read-cycles, the /RD commands from both microcontrollers are logically "ORed" together with an active bigh CS-signal (Chip Select) inside the SC060. The CS-signal for both ports is derived from address line A1S. Therefore, whenever A1S becomes a logic "I" (true), the mailbox is activated and ready to take or submit data. THE 5C060 MAILBOX Address range for the mailbox: FOOO Hex to FFFF Hex (Upper 12 kbyte) In this application, the 16 macrocells of the SC060 are grouped into two sets of 8 so called "ROlF" (register output with input feedback) primitives to implement the two 8 bit bus interfaces needed. The grouping is done according to the following picture. 5C080 2-141 AB-12 THE 5C031 "MAILBOX CONTROLLER" To keep the two microcontrollers informed about the status of their mailbox, the SC031 is programmed to supply the following signals to both controllers: /OBFA: "OUTPUT BUFFER FULL" FOR MC A /OBFB: "OUTPUT BUFFER FULL" FOR MC B /IBEA: "INPUT BUFFER EMPTY· FOR MC A /IBEB: "INPUT BUFFER EMPTY· FOR MC'B /INTA: INTERRUPT, TO MC A /INTB: INTERRUPT TO MC B The next section will discuss the meanings of these signals in more detail. Output Buffer Full: This flag is set whenever the controller writes into its own output buffer. The flag remains valid, until the second controller has read the data. The flag is automatically reset to its inactive state when this read cycle is accomplished. NOTE: Both controllers can access (read or write) the mailbox simultaneously. ' Input Buffer Empty: This flag indicates that there is no message in the mailbox. The flag will become inactive as soon as one microcontroller places a message for the other one (or vice versa). Example: /IBEA remains "LOW" until microcontroller B places, a message for controller A into the mailbox for A. /IBEA will go "HIGH" as soon as controller ,B has accomplished its write cycle, and will not go "LOW" again until microcontroller A has read the message. Interrupt: The SC031 is programmed to supply interrupts to both microcontrollers involved, on one of the following events. 1. The /OBF flag of the opposite microcontroller becomes active; e.g. if controller A is placing a message for controller B, controller B, receives an interrupt the same time as /OBFA becomes valid or vice versa. 2. The /IBE flag of the opposite microcontroller goes active, indicating that this controller has received the message; e.g. if .controller B reads the message stored by controller A, its /IBEB flag goes active and controller receives an interrupt indicating that the buffer is empty. The signals described above are necessary to accomplish a secure handshake without overwriting messages accidentally. In addition to that, the SC031 is issuing the actual write commands for the two register sets inside the SC060. The /WRA and /WRB signals are results oflogical "AND" functions between the appropriate CS- and /wR signals from the microcontrollers. Therefore, spurious write cycles are unlikely to happen. NOTE: This design cart also be efficiently implemented in a single SCBIC EPLD. 2-142 inter AB-12 A AOO-A07 PO 8 II "" ALE A8-A15 P2 PSEN - r- ~ 74HCT373 ~~ ~ - 00-07 00-07 AO-A7 AO-A7 f1--- ---l' ll. I~ 027C64 027C64 OE CE ~ A8-12 OECs r--- J [l' ~I ~~ r- L -- 1 - -..... WA X>.---.-------~>_-~ RDB OBF'A iliiTA RST INTB OBF'B RDA IBEA CSB WRB WB Of 292016-3 2-145 inter AB-12 5C060 REGISTER ADF JUIIRG INTEL March 80C31 1 STAHL ZUERICH 27, 1985 MAILBOX MEMORY USING 5C060 / 5C031 *************'****** ** ' BXAMPLII • Aor ** ******************** 5COSO LB Veraion 3.0, Baae1ine 17x, 9/26/85 PART: 5COSO INPUTS: WB81, CSA82, CSB814, nRDA811, nRDB823, WA813 OUTPUTS: IOB7815, IOA7810, IOBS81S, IOAS.9, IOB5817, IOA588, IOB4818, IOA487, IOB3.19, IOA386, IOB2820, IOA285, IOB1.21, IOAl.4, IOB0822, IOA083 NIITWORK: IOB7,DB7 ROlF (DA7,WAC,GND,GND,RDBC) IOA7,DA7 'ROlF (DB7,WBC,GND,GND,RDAC) IOBS,DBS ROIr (DAS,WAC,GND,GND,RDBC) IOAS,DAS ROIr (DBS,WBC,GND,GND,RDAC) IOB5,DB5 ROlF (DA5,WAC,GND,GND,RDBC) IOA5,DA5 ROlF (DB5,WBC,GND,GND,RDAC) IOB4,DB4 ROJr (DA4,WAC,GND,GND,RDBC) IOA4,DA4 ROJF (DB4,WBC,GND,GND,RDAC) JOB3,DB3 ROlr (DA3,WAC,GND,GND,RDBC) IOA3,DA3 ROJF (DB3,WBC,GND,GND,RDAC) IOB2,DB2 ROlF (DA2,WAC,GND,GND,RDBC) IOA2,DA2 ROJF (DB2,WBC,GND,GND,RDAC) JOB1,DB1 ROlf (DAl,WAC,G'ND,GND,RDBC) JOA1,DA1 ROJF (DB1,WBC,GND,GND,RDAC) IOBO,DBO ROlF (DAO,WAC,GND,GND,RDBC) JOAO,DAO ROlF (DBO,WBC,GND,GND,RDAC) WAC = INP (WA) RDBC = AND(CSBJ,RDBJ) WBC = INP (WB) RDAC = AND(CSAI,RDAI) csaI = INP (CSB) nRDBI = INP(nRDB) nRDAI = JNP(nRDA) CSAr INP(CSA) RDAI NOT(nRDAI) RDBI = NOT(nRDBI) IIND$ 292016-4 2-146 AB-12 5C060 REGISTER LEF .JUIRO INTIL March 80C31 STARL ZUIRICR Z7, 1986 MAILIOI MIMORY USINO 5C080 / 5C031 1 ******************** ** IXAMPLI .Llr ** ******************** 5C060 LI Ver.loa 3.0, 1 •• e11ae 17x, 9/Z8/85 Llr Ver.loa 1.0 la.e11aa 1.51 OZ rab 1987 PART: 5C080 INPUTS: WI81 , CSA8Z, CSI814, aRDA811, aRDI823, WA813 OUTPUTS: 1017815, IOA7810, 1018816, IOA689, 1015817, 10A588, 1014818, 10A487, 1013819, 10A386, 10lZ8Z0, IOA285, 1011821, IOA184, 1010822, IOA083 NITWORl: WIC = INP(WI) WAC = INP(WA) CUI = INP(CSA) csal = INP(CSI) aRDAI = INP(aRDA) aRDII = INP(aRDI) 1017, DI7 ROIF(DA7, W>\C, OND, GND, RDIC) IOA7, DA7 ROIF(DI7, WIC, OND, GND, RDAC) 1016, DI6 ROIF(DA6, WAC, OND, GND, RDIC) IOA6, DA6 ROlr(DI6, WIC, OND, OND, RDAC) 1015, DI5 ROIF(DA5, WAC, GND, GND, RDIC) IOA5, DA5 ROlr(DI5, WIC, OND, GND, RDAC) 1014, DI4 ROIF(DA4, WAC, GND, GND, RDIC) IOA4, DA4 ROlr(DI4, WIC, GND, OND, RDAC) 1013, DI3 ROIF(DA3, WAC, GND, GND, RDIC) IOA3, DA3 ROIF(DI3, WIC, GND, GND, RDAC) 10lZ, DIZ ROIF(DAZ, WAC, OND, GND, RDIC) 10AZ, DA2 ROIF(DIZ, WIC, GND, GND, RDAC) lOll, Dl1 ROIF(DAl, WAC, GND, GND, RDIC) IOA1, DA1 ROIF(Dl1, WIC, GND, GND, RDAC) 1010, DIO ROIF(DAO, WAC, GND, GND, RDIC) 10AO, DAO ROlr(DIO, WIC, GND, GND, RDAC) IQUUIONS: RDAC = CSAI nRDAI'; RDIC CSII * * aRDII'; IND. 292016-5 2·147 AB·12 5C060 REGISTER UTILIZATION REPORT Lo,ic Opti.izin, Co.piler Utilization Report FIT Vera ion 1.0 Baseline 1.0i 2/6/87 ***** JUIRG INTI!L March 80C31 Desi,n i.ple.ented succes.fully STARL ZUIRICR 27, 1985 MAILBOX MIMORY USING 5COSO / 5C031 1 ************************* ** EXAMPLB .RPT FILE ** ************************* 5COSO LB Version 3.0, Baaeline 17x, 9/2S/85 5COSO WB CSA 10AO 10Al Ion IOU IOA4 IOA5 10AS IOA7 nRDA GND - 1 - 2 - 3 - 4 -: 5 - S -: 7 - 8 -: 9 -: 10 -: II -: 12 24:23:22:21:20:19:18:17:IS:15:14:13:- Vee DRDB lOBO lOBI IOB2 10B3 1084 IOB5 lOBS IOB7 CSB WA nINPUTsn Ha.e Pin WB CSA Resource MCe11' MCells Feeds: 011 Clear INP 2 Clock CLKI IHP 9 10 II 12 13 14 15 IS nRDA 11 INP 9 10 11 12 13 14 15 IS GND 12 1 2 GND 3 4 5 6 7 8 9 292016-6 2-148 intJ AB·12 5C060 REGISTER UTILIZATION REPORT (Continued) IU 11 12 13 14 15 16 WA 13 INP CSB 14 INP CLK2 1 2 3 4 5 6 7 8 nRDB 23 1 2 3 4 INP 5 6 7 8 Vee 24 Vee Pin Resource nOUTPUTS n Naae lOAD MCell • Feeds: PTeras ROlF 9 1/ B 10 1/ 8 MCella 10Al 4 ROlf IOA2 5 ROlf 11 1/ 8 3 IOA3 6 ROlf 12 1/ 8 4 10A4 7 ROlf 13 1/ B 5 10AS B ROlf 14 1/ 8 6 IOA6 9 ROlf 15 1/ 8 7 10A7 10 ROlF 16 1/ 8 8 IOB7 15 ROlf 8 1/ 8 16 IOB6 16 ROlF 7 1/ 8 15 17 ROlf 6 1/ 8 14 IOB4 18 ROlF 5 1/ 8 13 10B3 19 ROlf 4 1/ 8 12 IOB2 20 ROlF 3 1/ B 11 10Bl 21 ROlF 1/ 8 10 ROlF 1/ 8 9 ZZ Clear Clock 2 IOB5 lOBO OE 292016-7 All Resource. u.ed UPART UTILIZATION . . 100_ 100_ 12_ Pins MacroCelb ptera. 292016-8 2-149 AB-12 5C031 ARBITER ADF JUIRG INTEL March 80C31 STARL ZUIRICH 28, 1986 MAILBOX MIMORY USING 5C060 / 5C031 ******************** ** IXAMPLI .ADF ** ******************** 2 5C031 LB Version 3.0,' Baaeline 17x, 9/26/85 PART: 5C031 INPUTS: RST,nWRA,nRDB,CSA,nRDA,nWRB,CSB,nOI OUTPUTS: WA,nOBFA,nIBIB,nINTA,nINTB,nOBFB,nIBIA,WB NBTWORl: nWRA = INP(nWRA) nRDB = INP(nRDB) RST = INP(RST) CSA = INP(CSA) nRDA = INP(nRDA) nWRB = INP(nWRB) CSB INP(CSB) nOI INP(nOI) WRA NOT(nWRA) WRB NOT(nWRB) RDA NOT(nRDA) RDB NOT(nRDB) 01 = NOT(nOI) nRST = NOT(RST) WA = CONF(WAd,VCC) WAd = AND(CSA,WRA) WB = CONF(WBd,VCC) WBd = AND(CSB,WRB) nRB = NAND(RDB,CSB) nRA = NAND(RDA,CSA) nWAd = NOT(WAd) nWBd = NOT(WBd) nOBFA,nOBFA COCf(nOBfAd,OB) nOBFB,nOBFB = COCF(nOBFBd,OI) nIBIA,nIBIA = COCf(nIBIAd,OI) nIBIB,nIBIB = COCF(nIBIBd,OI) nINTA = CONF(nINTAd,OI) nINTB = CONF(nINTBd,OI) nINTAd = AND(nOBFA,nIBBA) nINTBd AND(nOBFB,nIBIB) nOBFBd NAND(nRA,nIBIA,nRST) nOBFAd NAND(nRB,nIBIB,nRST) NAND(nWAd,nOBfA) nIBIBd nIBIAd NAND(nWBd,nOBFB) IND. 292016-9 2·150 inter AB-12 5C031 ARBITER LEF JUERG HlTBL March 80C31 STAHL ZUERICH 28, 1986 MAILBOX MEMORY USING 5C060 / 5C031 ******************** ** EXAMPLB .LBF ** ******************** 2 5C031 LB Yersion 3.0, Baseline 17x, 9/26/86 LBF Yersioo 1.0 Ba.alioe 1.6i 02 Feb 1987 PART: 6C031 INPUTS: RST, oWRA, nRDB, CSA, oRDA, oWRB, CSB, nOB OUTPUTS: WA, oOBFA, oIBBB, oiNTA, oiNTB, nOBFB, niBBA, WB NBTWORK: RST = INP(RST) oWRA = INP(oWRA) nRDB = INP(nRDB) CSA = INP(CSA) oRDA = INP(oRDA) oWRB = HlP(oWRB) CSB = INP(CSB) oOB = INP(oOB) WA = CONF(WAd, YCC) oOBrA, nOBrA = COCF(oOBrAd, OB) nIBBB, nIBBB = COCF(oIBBBd, OE) nINTA = CONF(oINTAd, OB) oINTB = CONF(nINTBd, OB) oOBFB, nOBFB = eOCF(oOBFBd, OB) oIBBA, oIBBA = eOCF(oIBBAd, OB) WB = eONr(WBd, YeC) BQUATIONS: WBd = CSB oWRB'; * CSB oIBBAd * oWRB' + nOBFB'; nOBrBd (niBBA oIBBA * RST' * CSA' oINTBd oOBrB * RST' * nRDA)'; * oIBBB; nINTAd nOBrA * oIBBA; + nIBBBd CSA * oWRA' + nOBrA'; OB = oOB'; nOB FAd = (oIBBB * RST' * eSB' + WAd = CSA oIBBB * RST' * oRDB)'; * oWRA'; BND$ 292016-10 2-151 AB-12 5C031 ARBITER LEF (Continued) Logic Optiaizing Coapile~ Utilization Report FIT Version 1.0 Baseline 1.0i ,2/6/87 .* •• * Design JUIRG INTEL March 80C3l iapleaented successfully STAHL ZUERICH 28, 1986 MAILBOX MKMORY USING 5C060 / SC03l ***"*,, ••••• *** •• *., •• ,. " 2 SC03l LB Version 3.0, B.seline l7x, 9/26/85 5C03l GND -: 1 GND -: 2 nOE - 3 CSB -: 4 nWRB - 5 nRDA -: 6 CSA -: 7 nRDB - 8 nWRA 9 GND -: 10 20:- Vee 19:- WB 18:- WA 17 :- nOBra 16:- nINTa lS:- nINTA 14:- nIBIB 13:- nOBrA 12:- nlBlA II :- RST UINPUTS*, N.ae Pin Resource nOB 3 INP CSB 4 INP nWRB S INP nRDA 6 INP CSA 7 INP nRDB 8 INP aWRA 9 INP GND 10 GND RST 11 INP Vee 20 Vee MCell. EXAMPLE .RPTFILE " ,.,',.,"',.".,"',.**'* PTeras 2-152 inter AB-12 5C031 ARBITER UTILIZATION REPORT **ounuTS** Na.e Pia Re.ouree DIBIA 12 cocr DOlrA 13 cocr MC.ll • PTer•• MCe11. 8 2/ 8 3 15 7 2/ 8 reed.: 01 Clear Pre •• t 15 6 DIBII 14 cocr 6 2/ 8 4 7 DINTA 15 CONr 5 1/ 8 DINTB 16 CONr 4 1/ 8 DOlFI 17 cocr 3 2/ 8 WA 11 CORr 2 1/ 8 WI 19 CONr 1 1/ 8 Re.ouree MCell PTer•• 4 8 **UNUSBD RBSOURCBS** N..e PiD 1 2 **PART UTILIZATION** 8S. 100. IS. PiD. MaeroCel18 Pter•• 292016-12 2·153 inter A,PPLICATION BRIEF OC,tobar 1987 Atypical Latch/Register Construction in EPLDs THOM BOWNS PROGRAMMABLE LOGIC APPLICATIONS INTEL CORPORATION Order Number: 292031-002 2-154 ' AB-16 in this Ap brief, the "!" operator is used to signify inversion). The schematic of the RS latch is shown in Figure la. ATYPICAL LATCH/REGISTER CONSTRUCTION IN EPLDs Though Intel's EPLDs include many of the typical latch and register types, some logic designs require register of latch configurations not directly supported in the current EPLDs. In many cases these register and latch configurations can be generated using the logic array and combinational feedback. A "latch" is defined as a level-triggered, flow-through type such as the 74373, and a "register" is defined as an edge-triggered flip-flop such as the 7474. Since cross coupled logic is not supported in EPLDs, we must convert the equation to a single term with feedback. 00, OF = COCF (0, VCC) 0= S + IR' OF; where QF is the feedback from Q output. This circuit can be implemented in an EPLD macrocell. Where combinational feedback is not supported, I/O feedback will suffice. The schematic of this implementation is shown in Figure lb. This application brief will detail the construction of a D-type latch, an RS latch and a D flip-flop using combinational logic and feedback. Also discussed is the construction of an RS flip-flop, a JK flip-flop and a T flip-flop using registered logic and feedback. With the RS latch, the inputs are normally low. A logical one on S sets Q to 1, and a one on R resets Q to a O. Logical ones on both inputs simultaneously cause the output to remain at a high level since S takes precedence over R in this implementation. The RS latch is the simplest latch configuration. The equations for it are as follows: QB = !(Q + S), Q = I(QB + R) where Q is the output of one NOR gate, and QB is the output of the other (Note: as a convention EJj NOR2 R 0 OB S NOR2 292031-1 (a) Vee INP s~~~-----------, INP R-C--f -COCF~ ~~~ ~~~'---OD ~""-., 292031-2 (b) Figure 1. RS Latch Implementation In a) Discrete Gates and b) EPLD Logic 2-155 intJ AB-16 00, OF Another latch is the 74373 type, or D latch. This latch works by either enabling input data to appear at the output, or by holding the output to the last input data state. Its equation is this: QB == !(I(ID*E)*Q), Q == !(!(O·E)*QB). Again, Q is the output of one NAND gate, and QB is the output of the other:' Figure 2a shows this. version' of the design. = COCF (O,VCC) 0= D' E + IE' OF; QF is the feedback from theCOCF. In this circuit, when E is high, data floW& through transparently. When E is brought low, data is latched.. When using input feedback, care must be taken when tri-statin~ the output as data will no longer be latched. The EPLD implementation is given in Figure 2b. Again, we must convert to an EPLD-type equation and schematic: D-.-.....- i o E -....- - i NAND2 292031-3 (a) E:-O.._--.... ___ e. o COCF'I .~"'''''' .>-1:;>1'-00 292031-4 (b) Figure 2. Implementation of a D Type Latch Using a) Discrete Gates and b) EPLD Logic 2-156 AB-16 This latch can be cascaded with, a second latch to produce an edge triggered, master/slave D flip-flop, using combinational logic. The flip-flop is a solution to using asynchronous clocking, preset and clear functions when they aren't supported. Also, if an I/O conflict exists within a macrocell group when using registered logic, this design will fit since it uses combinational logic. Figure 3 shows the schematic for this design. This design does consume two macrocells, but in many cases, that isn't a problem. The boolean equation of the D flip-flop is this: OO,OF = COCF (O,VCC) YF = NOCF (V) Y = D • ICLOCK o= YF • CLOCK + YF • CLOCK; + OF • ICLOCK; Q is the flip-flop output and Y is the first latch output. Data is latched in to the second latch on the low-going edge of clock, and is clocked out to Q on the high-going edge of clock. INP D-O---t. INP CLOCK - D _.......... ____ . cocr- ~~~ ~~~--QD 292031-5 Figure 3. Combinational Logic Implementation of a D Flip-Flop 2-157 AB·16 Pr~et and clear can be added into the equations as well: CO,QF = COCF (Q,VCC) YF .. NOCF (Y) Y = 0 • ICLOCK + YF • CLOCK; Q .. YF • CLOCK· I (CLEAR TERM) + (PRESET TERM) + . QF • ICLOCK • I (CLEAR TERM); When the PRESET TERM is logically true, Q is asynchronously set to 1. When the CLEAR TERM is logically true, Q is asynchronously cleared toO.. The PRESET TERM takes .priority over the CLEAR TERM. This schematic is shown in Figure 4. Due to the nature ofthe design, input delays plus array delays plus feedback delays must be added and used to determine a maximum operating frequency. In this example, tIN + tTAD + tCF + tAD = 113 ns for II -65 5C121, leaving a maximum frequency of 8.8 MHz. INP D~C>------------~ .... INP CLOCK -c:~---- -~. ___ e. COCF'I ~~.... ~~~'--QD ----_ .. INP CLEAR TERI.! -C:~-I ~O""--+--IA QF INP PRESET TERI.! -C:~------I ........:._ _ _ _ _--1 292031-6 Figure 4. D Flip-Flop with Added Preset and Clear Terms intJ AB-16 Other useful workarounds involve D registers and logic in constructing RS, JK and T flip-flops, for use in EPLDs not supporting these configurations. The RS flip-flop is simply the RS latch discussed earlier coupled to registered feedback. The JK flip-flop is another useful and easily implemented register: OO,OF = RORF (O,CLOCK,GND,GND;VCC) When J = K = 1, QO toggles to opposite state on next clock trigger. When J = K = 0, QO remains the same. When J does not equal K, QO will follow J on next clock trigger. The schematic is shown in Figure 6. 0= 5 + OF· !R; Normally, Sand R will remain high. When S is brought low, QO will become 1 on the next clock trigger edge. When R is brought low, QO will become 0 on the next clock trigger edge. The schematic is given in Figure 5. OO,OF = RORF (O,CLOCK,GND,GND,VCC) o= J • !OF INP CLOCK--<:>----------------------, INP s--~~----------_, INP GNO + !K • OF Vee ----. RORFI >-r::>rl--OO 292031-7 Figure 5. EPLD Implementation of an RS Flip-Flop INP CLOCK--<:>-----------------, INP ----. RORFI >-r::>rl-OO INP K--IC>--1 ~)-I-r 292031-8 Figure 6. EPLD Implementation of a JK Flip-Flop 2-159 AB-16 The T flip-flop is also easily constructed: register clock), as long asthe minimized logic equations resulting do not exceed the macrocells p-term count. QO,OF = RORF (O,CLOCK,GND,GND,VCC) O=ToIOF+ IToOF; When T is high. QO will toggle to opposite state on next trigger. When T is low, QO will remain the same. Pigure 7 shows the T flip-flop design schematic. Each of these designs' uses a minimum number of pterms; adding p-terms is possible to the limit of the macroceU being used. It is possible to substitute an entire logical expression for each input listed (except CLOCK INP Por example, .consider using the J-K register. Setting J=A"B"C+DandsettingK=E"'P"IG+ H + I then the minimized p-term count will expand from two p-terms to five p-terms, which would still be okay within a macrocell with more than five p-terms. Using logic gates and combinational or registered feedback, one can easily implement many types of latches and registers. Regardless of the EPLD type. there exists the resources to implement any of the discussed circuitry. GND Vc ----. RORr: INP T QD 292031-9 Figure 7. Implementation of a T Flip-Flop 2-160 intJ AB-18 APPLICATION BRIEF October 1987 TTL Macro Library Listing for EPLD Designs PROGRAMMABLE LOGIC APPLICATIONS INTEL CORPORATION Order Number: 292037"()()2 2·161 AB-18 TTL Macros MSI FUNCTIONS The following is a partial list of TTL macros that are available through the Intel EPLD customer hot line. Decoders/Demultiplexers These macros are used with the SCHEMA II-PLD schematic capture package. They can also be used in ADFs (Advanced Design Files) created using a text editor. THIS LIST REPRESENTS VERSION 3.4 OF THE TTL MACRO LIBRARY. FUTURE VERSIONS ARE SUBJECT TO CHANGE. SSIGATES 7400 7402 7404 7408 7410 7411 7420 7421 7427 7430 7432 7486 2 Input 2· Input I Input 2 Input 3 Input 3 Input 4 Input 4 Input 3 Input 8 Input 2 Input 2 Input NAND NOR INVERTER AND NAND AND NAND AND NOR NAND OR XOR 7442 7444 7447X 7449 74138 74139 74145 74154 74155 74156 (10) BCD to Decimal (10) Excess-3-Gray to Decimal (7) BCD to 7-Segment-Active Low Output (7) BCD to 7-Segment-Active High Output (8) l-of-8 Decoder (4) Single l-of-4 Decoder (10) BCD to Decimal (16) l-of-16 Decoder (8) Dual l-of-4 (8) Dual l-of-4 Multiplexers 74151 74153 74157 74158 74253 74257X (2) (2) (4) (4) (2) (4) 74258X (4) 74298XA (4) 74298XB (4) 74352 (2) 2-162 8-to-l Dual 4-to-l-Active High Output Quad 2-to-l-Active High Output Quad 2-to-l-Active Low Output Dual 4-to-l-Three-State Output Quad 2-to-l""':Active High, ThreeState Output Quad 2-to-l-Active Low, ThreeState Output Quad 2-to-l-Active High with Storage Quad 2-to-l-Active High with Storage Dual4-to-l-Active Low Output intJ AB-18 Counters 7490XD 7490XQ 74160 74161 74162 74163 74168 74169 74176XD 74176XQ 74177X 74190XA 74190XB 74191XA 74290XD 74290XQ 74390X 74393XA 74393XB (4) (4) (5) (5) (5) (5) (5) (5) (4) (4) (4) (6) (6) (7) (4) (4) (4) (4) (4) Type BCD Decade Bi-Quinary BCD Decade 4-Bit Binary BCD Decade 4-Bit Binary BCD Decade 4-Bit Binary BCD Decade Bi-Quinary 4-Bit Binary BCD Decade BCD Decade 4-Bit Binary BCD Decade Bi-Quinary Bi-Quinary/BCD 4-Bit Binary 4-Bit Binary S = Synchronous A = Asynchronous 9 = Synchronous Set-to-9 U/O RCO MM Clear S S A A S S A A A S S Load 9 9 S S S S S S S S S S S S 9 9 A A A Clk R R R R R R R R R R R R R R R R F F F Extras RGO RCO RCO RGO U/D, RGO U/D, RCO U/D, RCO, MM U/D,RCO,MM U/D,RGO,MM R = Rising-Edge Triggered F = Falling-Edge Triggered = Up/Down = Ripple Carry Output = Max/Min Output Single Flip-Flops 7472XA 7472XB 7473X 7474X 74112XA 74112XB (2) (2) (2) (2) (3) (2) AND-Gated JK Master/Slave AND-Gated JK Master/Slave JK with Clear D with Preset and Clear JK with Preset and Clear JK with Clear Latches 7475X 7477X 74259XA 74259XB 74373X Multiple Flip-Flops (Registers) 74 I 74X 74175X 74273X 74377 74378 (6) (8) (8) (8) (6) Hex D Quad D with Q and /Q Octal D Octal D with Common Enable Hex D 2-163 (8) (4) (8) (8) (8) 4-Bit Bistable Quad D-Type Octal Addressable D-Type Octal Addressable D-Type Octal D-Type AB-18 Shift Registers 7491 749SXA 749SXB 749SXC 7496X 74164 7416SX DE MORGAN EQUIVALENTS (BUBBLE GATES) (8) 8-Bit-Serial·In, Serial-Out (4) 4-Bit-8erial·In/ParaIlel·In, Parallel..()ut (4) 4-Bit-SCrial-In/ParaIlel·In, Parallel-Out (4) 4-Bit-8erial-ln/Parallel-In, Parallel-Out (S) S-Bit-8erial-ln/Parallel-In, Parallel-OUt ." 2 Input 3 Input 4 Input 6 Input 8 Input 121nput (8) 8-Bit-8erial-In, Parallel-Out (9), 8·Bit-8erial-In/Parallel-In, 7439SXA 7439SXA (4) (8) (7) (4) (17) 74180X 74180XA 74182 74183 (4) (4) (S) (2) 74280X (S) Bubble Bubble NAND (OR), NOR (AND) OR (NAND) BAND2 BAND3 BAND4 BANDS BANDS BAND12 BNAND2 BNAND3 BNAND4 BNAND6 BNANDS BNAND12 ,BNOR 2 'BNOR 3 'BNOR 4 BNOR 6 BNOR 8 BNOR 12 BOR2 BOR3 BOfl4 BOR6 ' BORB BOR12 INPUT N/A Genera41S Input Pin and N.ode in ADF OUTPUT (1) Generates Enabled Output ButTer in ADF ' (4) 4-Bit Bi-DirectionaISerial-In/Parallel-In, Parallel-Out (S) 4-Bit CascadableSerial-In/Parallel-In, Parallel-Out (S) 4-Bit CascadableSerial-In/Parallel-In, Parallel-Out OUTP 7412S 74126 Miscellaneous 7482X 7483X 748SX 7487 74143X Bubble AND (NOR) INPUT/OUTPUT MACROS ~-Out 74194 Bubble 2-Bit Adder 4-Bit Adder 4-Bit Magnitude Comparator 4-Bit True/Complement E1em~t 4-Bit Counter; 4-Bit Latch; 7 Segment Decoder 8-Bit Parity Qenerator/Checker, 8-Bit Parity Generator/Checker Look-Ah~ Carry Generator, Single-Bit Full Adder with Carry/Save 9-Bit Odd/Even Parity Generator/ Checker (1) Output Pin (Used in SCHEMA, 11PLD) , (1) Single Three-State Output, Active Low Enable , (1) 'Single Three-State O~tput, Active High Enable NOTES: 1. All TTL macros duplicate TTL function only. They DO NOT DUPLICATE performance characteristics such as open-collector, totem-pole. or high-drive output. 2. Any TTL macros which deviate in some way from standard TTL function are denoted with an appended "X" (see device .:QOC file for details). Appended "D"s and "Q"s indicate counters configured to'Decimal or bi-Quinary mode; appended "A"s and "B"s indicate a macro configured for a family of EPLD devices (e.g. SC060, SC090, SCI80). 3. The (#) indicates the maximum number of EPLD macroce1ls consumed if all outputs are used. If an output is not used, the macro compression phase .of the Macro Expander will rem.ove the signal unless it is used as feedback inside the' macro definition. 4. /Cls sh.ould be avoided as pin outputs if possible. The EPLD is structured such that the Q is readily available as a pin .output and both the, Q and /Q are readily available as feedbacks. Using /Q as a pin output, h.owever, requires an extra macroce1l and adds to the propagation delay. 2-164 inter AP-271 APPLICATION NOTE April 1986 Applying The 5C121 Architecture JIM DONNELL PROGRAMMABLE LOGIC APPLICATIONS INTEL CORPORATION Order Number: 292008·001 2·165 Ap·271 INTRODUCTION Intel's 5C121 Erasable Programmable Logic Device represents a new breed in the world of programmable logic. With gate densities approaching those of gate arrays and a reconfigurable architecture, the logic designer is freed from choosing between scores of generic programmable logic to perhaps find an acceptable match for his or her design needs. Adding to the list of benefits is the fact that the 5C121 is erasable. Now sections of the design can actually be programmed and tested in the device - without sacrificing a part to the circular me. In addition, there is no longer a need to generate test vectors to qualify the programming of the parts. EPLDs are erasable and therefore 100% testable at the factory. OBJECTIVE The purpose of this application note is to demonstrate the architectural options of the 5C121 by designing a digital crosspoint switch. Conceptually, a digital crosspoint switch switches data from any input to any output. Figure 1 shows a block diagram of a bytewide crosspoint switch. include'reguitered or combinational output. In addition, each output may be fed back into the array in both the true and complement version. For a more complete description of the SC121 architecture the reader is referred to the 5C121 data sheet. COMBINATIONAL FEEDBACK Feedback in logic designs is used for a variety of reasons. Combinational feedback in the 5C121 is often used to reduce the number of product terms feeding one Macrocell. Though the SC121 has Macrocells that can accept up to 16 product terms, all Macrocells are not that wide. Let's look at an example. Equation 1 represents one of the eight Boolean expressions neCessary to implement a digital crosspoint switch. Logically, this expression selects one of eight input signals (10-17), and routes that signal to QO. Data bits 00,01, and 02 select one of the eight input lines. In this case, data bits 103, 104, and !DS select output QO. (The exclamation point is used to indicate a logical complement of the signal.) Equations for Q1 through Q7 are very similar and will be discussed later. 00 = ( 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 00-07 X 102 X 101 X !OO x. 102 X 101 X DO X !02 X 01 X !OO x 102 x 01 X DO X X X X 02 02 02 02 X X X X 101 !01 01 01 X X X X !OO DO IDO DO) X !05 X 104 X 103; (1) SELECTEO = 10 X 102 X 101 + + + + 030405 OUTPUT SELECT 292008-1 + + + Figure 1. Functional Diagram of a Digital Crosspoint Switch This design will employ features such as: registered output with registered feedback, combinational feedback, input latches, buried registers, and dual clock options. The digital crosspoint switch in this design can route data from one of eight inputs to one of eight outputs in a single clock cycle. Options for holding the deselected outputs at previous levels, latching inputs, and fitting considerations are explored. THE BASIC ARCHITECTURE The 5C121 contains 28 Macrocells, 12 dedicated inputs, 24 programmable I/O lines, and two clocks input pins. Inputs may be flow through, or latched on the rising or falling. edge of either clock. Output options 11 12 13 14 15 16 17 X X X X X X 102X.!I)1 102 X 01 102 X 01 02 X 101 02 X !01 02 x 01 x 02 X 01 .x !OO DO 100 DO !OO DO x !DO x DO; X X X X X (2) Equation 2 contains the terms that will be common to all eight output equations. Both equations in this case contain eight product terms. By treating equation 2 as one common signal and routing that signal through combinational feedback, we can reduce the number of product terms in equations QO thru Q7 to one p-term each. The advantage is that the outputs can now be placed in any of the 24 I/O Macrocells available in the 5CI21.,1naddition, the 5C121 contains four buried registers. (Buried registers have no output and are used : solely for feedback.) If a buried register is available, iPLDs (Intel's Programmable Logic Development System) will automatically assign the No Output - Combinational Feedback function to a buried register. This increases the flexibility for pin assignments and makes 2-166 inter AP-271 (Continued) p-terms available in case a design change is needed. Equations 3 thru 10 reflect this improvement. 00 = SELECTEO x 105 x 104 x !03; (3) 01 = SELECTEQ x !05 x 104 x 03; (4) 02 = SELECTEQ x 105 x 04 x !03; . (5) Q3 = SELECTEQ x !05 x 04 x 03; (6) Q4 = SELECTEQ x 05 x !04 x 103; (7) Q5 = SELECTEQ x 05 x !04 x 03; (8) 06 = SELECTEQ x 05 x 04 X !03; (9) Q7 = SELECTEQ x 05 x 04 x (10) 03; REGISTERED FEEDBACK Registered feedback is also employed in a variety of applications such as counters and state machines. In this particular example, the registered feedback signal can be used to hold the deselected outputs of the switch at their previous level until that output is selected again. This is accomplished by simply "ANDing" the feedback signal with the inversion of the output select signal. The result is then "ORed" with the equation for the given output. Holding the previous output might be useful in control applications or when interfacing to slow peripherals. Equations 11 thru 18 are the result. 00 = SELECTEO x !05 x !04 x 103) x QO-fdbk; x !03 + !(05 03 + !(!05 Q2 = SELECTEQ x !05 x 04 x !03 x !03) x Q2-fdbk; + !(!05 X 04 (13) Q3 = SELECTEQ x !05 x 04 x 03) x 03-fdbk; x 03 + !(l05 x 04 (14) Q4 = SELECTEQ x 05 x !04 x !03) x Q4-fdbk; x 03 + 1(05 x !04 (15) Q5 = SELECTEQ x 05 x !04 x 03) x 05-fdbk; x 03 + 1(05 x !04 (16) Q6 = SELECTEQ x 05 x 04 x !03) x 06-fdbk; x !03 + !(05 x 04 07 = SELECTEQ x 05 x DR x DE) x Q7-fdbk; x Q1 = SELECTEQ x !05 x 104 x 03) x Q1-fdbk; COMBINATIONAL FEEDBACK x !04 (11) x x !04 (12) (17) 03 + !(05 x 04 (18) Equations 11 thru 18 are all that are necessary to implement a digital crosspoint switch with the output hold feature. Each equation contains only four product terms when written in the expanded form and could therefore fit into any Macrocell in the5Cl21. The appendix contains the report and ADF files generated by the iPLDs software. TIMING ANALYSIS Figure 2 shows the internal delay paths associated with this design in the 5Cl21. The frequency at which the 5Cl21 may be clocked can be determined by examining the internal delay elements ofthe 5C121. These include the input delay (Tin), two array delays (Tad), and the combinational feedback delay (Tcl). Table 1 gives the simulation data for each of these paths in a 5CI21-50. __+--------Tad--------~-- ARRAY Tad Trd ARRAY REG OUTPUT 'I' ~--------------Trl--------------~,I Figure 2. Crosspoint Delay Path 2-167 Tad-l 292008-2 Ap·271 bits could be switched per cycle. Figure 3 shows the timing diagram for this configuration of the 5C121 digital crosspoint switch. Included in the appendix is the Advanced Design File .(ADF), Logic Equation File (LEF), and Utilization report generated by Intel's Programmable Logic Software (iPLS) for this design. TIMING ANALYSIS (Continued) Table 1. 5C121-50 Simulation Data Model Parameter Delay (ns) Tad 38 Trd 7 INPUT LATCHES Tod 8 Tin 10 Tie 8 Trf 5 Tef 5 One point must be raised about Figure 3. Notice that the time allowed for external data set-up is only 17 ns. Therefore, 17 ns after the rising edge of the clock, data must be, stable and remain stable at the input pins until the next clock pulse. In most systems this would be a very stringent requirement. Fortunately the 5C121 has the ability to latch the data at the input pins with 7475 type transparent latches. Employing this feature eases the data set-up requirement as shown in Figure 4. The sum of the delays before the register input equal the set-up time Tsu with reference to the internal clock. By substracting the input clock delay Tic we shift the reference to the external clock pin. The set-up time with reference to external signals is shown in equation 19. Inverting this signal yields the maximum clock frequency, fmax. The maximum clock frequency is shown in equation 20. Tsu = Tin + 2Tad + Tcf - Tic; (19) fmax = 1 Tsu (20) Therefore, this configuration of the 5C121-50 could be clocked at 10 MHz, allowing a data transfer rate of 10 Mbits/second. By paralleling six 5C121s together, eight I" SUMMARY The flexible architecture of the 5C121 gives the designer a variety of options for input and output configurations. Inputs may be latched to ease system timing requirements. Outputs may be clocked for synchronous systems or fed directly out as asynchronous signals. Feedback c~ be used to reduce product term requirements, to save present state information for state machines and counters, or simply to hold deselected outputs as shown in this example. Imagine the possibilities. J. R. Donnell PLDO Applications lOOns ,'I \. elK Tsu (83NS) 17ns I J -___....;.;.;.;..;;.;..;.;;.;;;;;;.. INPUTS/1' X rI\.,_ _ _ _ _ _ _ _ _J'\ INPUT STABLE ___-'lI'-......X X DATAOUT:::::::::::::::::::::::::::~::~:--:K:::~D~AT~A~O~U~TJV~A~ll~D::::: I--Teol = (Teo 1 TIe + Tr,d + Tod) 292008-3 Figure 3. Crosspoint Timing Diagram' 2-168 AP-271 I' "I lOOns CLK J LATCHED INPUTS X. Tlu(83NS) 17ns ~ LATCH ENABLE DATA TO PINS .I. X. INPUT STABLE X EXTERNAL DATA SET-UP DATA STABLE X L~,:j = DATA OUT (Teo1 DATA OUT VALID Tie + Trd + Tod) 292008-4 Figure 4. Crosspoint Timing Diagram with Input Latches 2-169 inter AP-271 APPENDIX ADF File o 5C121 Digital C~osspoint Switch LB Version 3.0, Baseline 17x, 9/26/85 PART: 5C121 INPUTS: IOO@37,IOl@36,I02@35,I03@34,I04@8,I05@9,I06@10,I07@II,II0@33,II1@32 ,112@31, 113@30, 114@29, 115@28, 116@27, 117@26,CLK@38,DO@2, DH!3, D2@4, D3@5 ,D4@6,D5@7,ILE@1 OUTPUTS: 000@12,OOI@13,002@14,003@15,004@16,005@17,006@18,007@19,OI0@24,0l1@23 ,OI2@2I,OI3@21 ' " NETWORK: OOO,QOOFBK RORF (QOOD,CLK,GND,GND,YCC) ~ BIT 0 OUTPUTS ~ 001,QOIFBK RORF (OOID,CLK,GND,GND,YCC) Q02,Q02FBK RORF (002D,CLK,GND,GND,YCC) Q03,Q03FBK RORF (003D,CLK,GND,GND,YCC) Q04,Q04FBK RORF (004D,CLK,GND,GND,YCC) Q05,Q05FBK RORF (005D,CLK,GND,GND,YCC) Q06,Q06FBK RORF (006D,CLK,GND,GND,YCC) Q07,Q07FBK RORF (007D,CLK,GND,GND,YCC) QI0,QI0FBK RORF (010D,CLK,GND,GND,YCC) ~ 4 OF THE 8, BIT 0 OUTPUTS~ Ql1,QIIFBK RORF (OIID,CLK,GND,GND,YCC) 012,Q12FBK RORF (012D,CLK,GND,GND,YCC) 013,Q13FBK RORF (013D,CLK,GND,GND,YCC) CLK = INP (CLK) D5 = LINP (D5,ILE) ~ OUTPUT SELECT CONTROL BITS ~ ILE = INP (ILE) D4 LINP (D4,ILE) D3 LINP (D3,ILE) D2 = LINP (D2,ILE) ~ INPUT SELECT CONTROL BITS ~ Dl = LINP (Dl,ILE) DO = LINP (DO,ILE) 100 LINP (IOO,ILE) 101 LINP (IOl,ILE) 102 LINP (I02,ILE) 103 LINP (I03,ILE) 104 LINP (I04,ILE) 105 LINP (I05,ILE) 106 LINP (I06,ILE) 107 LINP (I07,ILE) 110 LINP (II0,ILE) ~ INPUTS FOR BIT 1 SWITCH ~ III LINP (Ill,ILK) 112 LINP (II2,ILE) 113 LINP (II3,ILE) 114 LINP (II4,ILE) 115 LINP (II5,ILE) 116 LINP (II6,ILE) 117 LINP (II7,ILE) SELECTKQOF = NOCF (SELECTEQO) SELECTEQIF = NOCF (SELECTEQl) EOUATIONS: QOOD SELECTEQOF*!D5*!D4*!D3 + !(!D5*!D4*!D3)*000FBK; 001D SELECTEQOF*!D5*!D4* D3 + !(!D5*!D4* D3)*00IFBK; SELECTEQOF*!D5* D4*!D3 002D + !(!D5* D4*!D3)*Q02FBK; 003D SELECTEQOF*!D5* D4* D3 + !(!D5* D4* D3)*003FBK; 004D SELECTEOOF* D5*!D4*!D3 + !( D5*!D4*!D3)*004FBK; 005D SELECTEOOF* D5*!D4* D3 292008-5 2-170 Ap·271 ADF File (Continued) + !( D6*!D4* D3)*006FBK; SBLBCTBoor* D6* D4*!D3 + !( D6* D4*!D3)*00SFBI; 007D SBLBCTloor* D6* D4* D3 + I( D6* D4* D3)*007FBK; SILBCTlolr*!D6*!D4*ID3 010D + !(ID6*ID4*!D3)*010FBK; 011D SILICTIQlr*!D6*ID4* D3 + !(!D6*!D4* D3)*011FBK; SILICTlolr*!D6* D4*!D3 012D + !(ID6* D4*ID3)*Q12rBI; Q13D SBLICTlolr*ID6* D4* D3 + !(!D6* D4* D3)*013FBK; SILICTIQO = IOO*!D2*!Dl*!DO • COMMON 10UATION rOR BIT 0 • + I01*ID2*ID1*DO + I02*ID2*Dl*!DO + I03*!D2*DUDO + I04*D2*!Dl*!DO + I06*D2*IDUDO + I06*D2*DU! DO + I07*D2*DUDO; SILBCTIQl = Il0*!D2*!ll*IDO • COMMON 10UATION rOR BIT 1 • + Ill*ID2*ID1*DO + I12*!D2*Dl*IDO + 113*ID2*DUDO + I14*D2*!Dl*IDO + 116*D2* I DUDO + 116*D2*DU I DO + 117*D2*DUDO; BND. OOSD 2·171 292008-6 AP-271 LEF File .1R Donnell Intel .1an~ary 24, 1986 o 5C121 Digital Crosspoint Switch LB Yersion 3.0, Baseline 17x, 9/26/85 PART: 5C121 INPUTS: 100@37, 101@36, 102@35, 103@34, 104@8, I05@9, 106@10, 107@11, 110@33, 111@32, 112@31, 113@30, 114@29, 115@28, 116@27, 117@26, CLK@38, DO@2, Dl@3, D2@4, D.3@5, D4@6, D5@7, ILI@l OUTPUTS: QOO@12, QOl@13, Q02@14, Q03@15, Q04@16, Q05@17, Q06@18, Q07@19, QIO@24, Qll@23, Q12@22, Q13@21 NITWORK: CLK INP(CLK) ILl INP(ILI) 100 LINP(IOO, ILl) 101 LINP(IOl, ILl) 102 LINP(102, ILl) 103 LINP(103, ILl) 104 LINP(104, ILl) 105 LINP(I05, ILl) 106 LINP(106, ILl) 107 LINP(107, ILl) 110 LINP(II0, ILl) III LINP(lll, ILl) 112 LINP(112, ILK) 113 LINP(113, ILl) 114 LINP(114, ILl) 115 LINP(115, ILl) 116 LINP(116, ILK) 117 LINP(117, ILl). DO LINP(DO, ILl) Dl LINP(Dl, ILK) D2 LINP(D2, ILK) D3 LINP(D3, ILK) D4 LINP(D4, ILl) D5 LINP(D5, ILl) QOO, QOOFBK RORF(QOOD, CLK, GND, GND, YCC) QOl, QOlFBK RORF(QOID, CLK, GND, GND, YCC) Q02, Q02FBK RORF(Q02D, CLK, GND, GND, YCC) Q03, Q03FBK RORF(Q03D, CLK, GND, GND, YCC) Q04, Q04FBK RORF(Q04D, CLK, GND, GND, YCC) Q05, Q05FBK RORF(Q05D, CLK, GND, GND, YCC) Q06, Q06FBK RORF(Q06D, CLK, GND, GND, YCC) Q07, Q07FBK RORF(Q07D, CLK, GND, GND, YCC) QI0, QI0FBK RORF(QI0D, CLK, GND, GND, YCC) Qll, QllFBK RORF(QllD, CLK, GND, GND, YCC) Q12, Q12FBK RORF(Q120, CLK, GND, GND, YCC) Q13, Q13FBK RORF(Q13D, CLK, GND, GND, YCC) SILICTIQOF = NOCF(SKLICTIQO) SKLICTKQlF = NOCF(SKLICTIQl) EQUATIONS: SELICTIQl 110 D2' Dl' DO' + D2 Dl' DO' 114 + D2' Dl DO' 112 + D2' Dl' DO III + D2 01 DO' 116 + D2 01' DO 115 + D2' 01 00 113 292008-12 * * * * * * * * * * * * * * * * * * * * * 2-172 Ap·271 LEF File (Continued) + 02 * 01 * 00 * 117; SILICTIQO Q130 100 * 02' * 01' * 00' + 02 * 01' * 00' * 104 + 02' * 01 * 00' * 102 + 02' * 01' * 00 * 101 + 02 * 01 * 00' * 106 + 02 * 01' * 00 * 105 + 02' * 01 * 00 * 103 + 02 * 01 * 00 * 107; 03' * Q13FBK + 04' * Q13F8K + 05 * Q13F8K + SILICTIQ1F * OS' * 04 * 03; Q120 04' * Q12FBK + 03 * Q12FBK + 05 * Q12FBK + SILICTIQIF * OS' * 04 * 03'; QIIO 03' * QIIFBK + 04 * QIlFBK + 05 * QIlFBK + SILICTIQIF * OS' * 04' * 03; QIOO Q070 03 * Q10FBK + 04 * Q10FBK + 05 * Q10FBK + SBLICTIQlF * OS' * 04' * 03'; 03' * Q07FBK + 04' * Q07FBK + OS' * Q07FBK + SILICTIQOF * 05 * 04 * 03; Q060 04' * Q06FBK + OS' * Q06FBK + 03 * Q06FBK + SILICTIQOF * 05 *04*03'; Q050 03' * Q05FBK + OS' * Q05F8K + 04 * Q05FBK + SlLICTlQOF * 05 * 04' * 03; Q040 05' * Q04FBK + 03 * Q04FBK + 04 * Q04FBK + SBLICTlQOF * 05 * 04' * 03'; Q030 03' * Q03FBK + 04' * Q03FBK + 05 * Q03FBK + SILICTIQOF * OS' * 04 * 03; Q020 04' * Q02FBK + 03 Q02FBK + 05 Q02FBK + SILICTIQOF * OS' * 04 QOIO 03' * Q01FBK + 04 QOIFBK + 05 * Q01F8K OS' * 04' * 03; + SILBCTIQOF QOOO 03 * QOOFBK + 04 QOOFBK + 05 QOOFBK + SILBCTIQOF * * * 03'; * * * * * OS' 292008-13 * 04' * 03'; INO$ 292008-14 2·173 inter AP-271 RPT File Logic Optimizing Compiler Utilization Report ***** Design implemented succes.fully .18 Donnell Intel January 24, 1986 o 5C12l Digital Cros.point Switch LB Version 3.0, Baseline l7x, 9/26/85 5C12l ILl -: 1 DO Dl D2 D3 D4 D5 104 105 106 107 QOO QOl Q02 Q03 Q04 Q05 Q06 QO? GND -: 2 -: 3 -I 4 5 6 7 8 9 -:10 -: -: -: -: -: -: 11 - :12 -: 13 -:14 -:15 -:16 -:17 -: 18 -:19 -:20 40:39:38:37:36:35:34:33132:31:30:29:28:27:26:25:24:23:22:21:- Vcc Vcc CLK 100 101 102 103 110 III 112 113 114 115 116 117 GND QlO Qll Q12 Q13 **INPUTU* Name Pin ILl Re.ource Meell • PTerm. MCells INP Feeds: 01 Clear Clock Latch DO 2 LINP 13 15 Dl 3 LINP 13 15 D2 4 LINP 13 15 D3 5 LINP 9 10 11 12 17 18 19 20 21 292008-9 2-174 intJ Ap·271 RPT File (Continued) 22 23 24 D4 6 LINP 9 10 11 12 17 18 19 20 21 22 23 24 D5 7 LINP 9 10 11 12 17 18 19 20 21 22 23 24 104 8 LINP 28 01 4 15 105 9 LINP 27 0/10 15 106 10 LINP 26 01 8 15 107 11 LINP '25 01 6 15 117 26 LINP 7 0/10 13 116 27 LINP 6 01 8 13 Il5 28 LINP 5 01 6 13 114 29 LIMP 4 01 6 13 113 30 LINP 3 01 8 13 112 31 LINP 2 0/10 13 III 1 01 4 13 32 LINP 110 33 LINP 13 103 34 LINP 15 102 35 LINP 15 101 36 LINP 15 100 37 LINP 15 eLK 38 INP Reg 292008-10 2-175 inter AP-271 RPT File (Continued) **OUTPUTS** Haae PiD Resource MCell # PTeras MCells QOO 12 RORF 24 4/ 6 24 Q01 13 RORF 23 4/ 8 23 Q02 14 RORF 22 4/10 22 Q03 15 RORF 21 4/ 4 21 Q04 16 RORF 20 4/12 20 Q05 17 RORF 19 4/ 4 19 Q06 18 RORF 18 4/ 8 18 4/ 8 17 Q07 19 RORF 17 Q13 21 RORF 12 4/ 8 12 Q12 22 RORF 11 4/ 8 11 Q11 23 RORF 10 4/ 4 10 QI0 24 RORF 9 4/12 9 Resource MCell # PTeras MCe11s HOCF 13 8/ 8 .9 10 11 12 HOCF 15 8/ 8 17 18 19 20 21 22 23 24 Resource MCell PTeras 8 14 16 4 8 8 Feeds: OE Clear Feeds: OE Clear **BURIED REGISTERS** Naae PiD **UHUSED RESOURCES** Naae PiD 25 HA HA **PART UTILIZATION . . 97l1; 89l1; 30ll; PiDS MacroCe11s Pteras 292008-11 2-176 inter AP-272 APPLICATION NOTE June 1986 The 5C060 Unification of a CHMOS System J. R. DONNELL PROGRAMMABL.E LOGIC APPLICATIONS INTEL CORPORATION Order Number: 292009-003 2-177 AP·272 ". INTRODUCTION OBJECTIVE From an outside glance, the world of computers and microprocessors seems filled with dedicated ICs that fulfill a variety of system needs. Upon closer inspection we find that designers must still reach into their bag of random logic to link together all of the parts of the system. It seems a shame to stuff a board full of high powered peripherals and still have portions of that board wasted on decoders, latches, and other miscellaneous random l o g i c . ' This application note covers the design of three separate circuits for Intel's CHMOS Design Kit. The functions performed by the 5C060 are: Memory decoding, wait state generation, and the power down circuitry for the 8OC88 system clock. True, programmable logic has been around a long time. But that logic is somewhat rigid in form, one time programmable, and can also double as space heaters. These devices are totally unacceptable for a CMOS system. What is needed is a flexible PLA architecture, erasability for prototyping, and CMOS for low power. In addition, for this particular application the device must perform from static operation to 10 MHz. MEMORY DECODING The system in question supports one 32K bank of EPROM memory, and four banks of 4K static RAM. Figure 1 shows the memory map of this system. Address lines Al9, Al3, and Al2 will be used to decode the address space. PWILDWN and SLMIO serve as enables. In addition, to avoid data bus contention signals memory read (MRDC) and advanced memory write (AMWC) are decoded along with the address lines for RAM chip selects. This is necessary for devices without output enables (OE) on multiplexed address/data busses. FFFFF EPROM 8CIIIIIO • • • • • • RAM1. D1.... D10110 aaoao 292009-1 Figure 1. 8OC88 Memory Map 2-178 AP·272 Figure 2 shows a discrete implementation of the chip select decoding logic. ----4" YO "13 - - - o f 8 y:; "12 "19 ----4 MRDC AMWC C Y2 Y3 RAM4KCS Y4 Ys PWRDWN ---<1I G28 S2MIO ----4 G1 Vi G2A V7 74138 292009-2 Figure 2. Discrete Decoding Logic,Solutlon Several options for entering this design are available through Intel's Programmable Logic Development System (iPLDS). (For a more complete description of iPLDS the reader is referred to the iPLDS data sheet.) The design entry vehicle chosen for this application note is the Logic Builder. (Logic Builder is an interactive nedist method of design entry especiaJIy suited to Boolean equation entry and entry from existing schematics.) Several reasons are behind this' decision. First, the Logic Builder software is included in iPLDS. In addition, Logic Builder entry is very fast, the designer may choose either netlist entry or Boolean equations, and finaJly, the Logic Builder software makes additions and corrections of design very easy. Using Logic Builder, the first step for this design is to determine the equations for the 3 to 8 decoder shown in Figure 2. These equations are simply the decoding of the address lines ANDed With the enable signal. Equations 0 thru 8 implement the decoding function of Figure 2. /YO = /AI9*/A13*/A12*ENABLE; (0) /YI = /AI9*/A13*AI2"ENABLE; (I) /Y2 = /AI9"A13*/AI2*ENABLE; (2) /Y3 = /AI9*A13"AI2*ENABLE; (3) (4) /Y4 = AI9*/A13"/AI2*ENABLE; /Y5 = AI9*/A13"A12"ENABLE; (5) /Y6 = AI9*A13"/AI2"ENABLE; (6) /Y7 = A19* A13" A12*ENABLE; (7) (8) ENABLE = /PWRDWN"S2MIO; Armed With this knowledge it becomes trivial to enter the circuit of Figure 2 into Logic Builder. Included in the Appendix is the Advanced Design File (ADF) created by Logic Builder for this circuit (ADF-l). Typically the ADF would now be submitted to the Logic Optimizing Compiler (LOC) for Boolean minimization and design fitting. In this case we have used only a small portion if the logic available in the 5C060 so let us continue with the wait state generator and power down circuitry. Power Down Since this design is based on the 8OC88 we can actually stop the system clock for extended periods of time and power back up as if nothing had occurred. The circuit to achieve this power down is shown in Figure 3. As long as the PWRDWN signal is low the 82C84 clock output is OR'ed with a logical zero from the PWRDWN flip-flop. As a result the 82C84 drives the 80C88 system clock. If PWRDWN goes HIGH, the rising edge of the next 82C84 clock will set the output of the PWRDWN flip-flop HIGH inhibiting the faJI of the next clock cycle. The 80C88 system clock will remain HIGH until PWRDWN goes LOW and the PWRDWN flip-flop is clocked from the 82C84 clock. Using this configuration we avoid partial clock cycles for the 8OC88 system clock. 2-179 AP-272 OND .. 'PIN OUT PWRDWN -~;.o..::..::..;....-------IMP Vee !-- Fl~ -- i -"oR,,: L~~D~-:Q~~,..J I UC84CLK _P;..;IN;.;.c:>O.;;.UT;;';"'_"'T'"_ _ _..::IN~I"""I>0_UT;.:..._ _-+I... IMP :;. , PIN - II II STOPCLK : I I I I I I I ,_ - - - - - '!~ - - Vee 1--------I A_ • I ,-OUT OE liN" CONFI _i 8OC88CLK I ________ • PIN:I L OM 292009-3 'Figure 3. 80C18 Power Down Circuit Again, entering this circuit into Logic Builder is trivial. In fact it can be added directly to the decoder circuit shown above. The ADF file for this addition is shown in the appendix under ADF-2. (LEF), and the Utilization Report. These are also included in the appendix for each step in this design pro- cess. LOC FILES Walt States The majority of memory and peripheral devices which fail to operate at the maximum CPU frequency typical-, ly do not require more than one wait state. The circuit shown in Figure 4 is an example of a simple wait state generator. The circuit operation is as follows. Given that a memory location requiring a wait state has been selected, ALE in conjunction with /wAITCS will clear the flip-flop-driving the 82C84RDY line high low. The 82C84 samples the RDY line during T2 of the 8OC88 bus cycle, and in this case detects a wait state. The rising'edge ofT2 then, clocks the 82C84RDY line high thereby inserting only one wait state. Once again, adding this circuit to the existing decoder and power down design is simple. The final ADF file is given in the appendix under ADF-3. Once the final design has'been completed the ADF is submitted to the Logic Optimizing Compiler. LOC compiles the design, performs Boolean minimization, and fits th~ design into the target EPLD. In addition, LOC produces two f.iles. The mDEC programming file, the Logic Equati~ File The JEDEC File The mDEC file is lU).IIlogous to the Qbject code file that is used to program EPROMs. This file is used by the Logic Programming Software (LPS) to, program Intel's EPLDs. ' The LEF File The LEF file is an optional file produced by the compiler. The,LEF file contains the minimized Boolean equations which resulted from the original ADJ!. Some interesting points can be raised concerning the LEF file. Looking at LEF-3, first recall that the EPROM chip select was a function of A19, Al3, A1+., and the enable signals. It turns out that after minimization the EPROM chip select depends oDJ.y on A19 and the enable signals (/PWRDWN arid S2MIO): This is shown in the LEF file. One other ppint, ~e initial wait state circuitry employed a JK flip-flop. The compiler automatically minimized this circuit into a D-type flip-flop with feedback achieving the same functionality. ' 2-180 inter AP-272 GND Vee Wii'i'CS .....;P:..:IN::..c:>=O:=UT~_...::.:~~.:=..;_...:::..r-~r:::.;..-I INP ALE .....;P:.,:I:,:NO..,;O::;UT:.:.._ _ _ _ _....J L:::.DO=;::':"--1H "I--f)......C>ii----82C84RDY INP 292009-4 Figure 4. Single Walt State Generator for the 80C88 The Utilization Report SUMMARY Finally, the Utilization Report contains the pin-out for the design, information about the architectural layout of the design, and a percent utilization for pins, macrocells, and product terms. Examining the utilization report for this design we find that two of the sixteen macrocells are still available. We could therefore add more functionality in the same 24 pin package. Possible additions would be more memory decoding, invalid memory detection, additional wait state generators, etc. One point should be raised: The circuitry designed in this applications note is relatively simple compared to the complex logic functions that could be implemented in the SC060. The designs shown in this applications note are typical requirements of any microprocessor system. The SC060 provided a single chip solution to bind together the primary elements of that system. Few other types of programmable logic could implement the same logic in a single package. None could do it in CMOS erasable logic. The SC060 has room for more. 2-181 inter AP-272· APPENDIX ADF·1 .fl D""n,,11 Tnt .. 1 . .11l.uar,. !It. 111"11 ~OOIiO o ~OOIiO .,..t ... - D..., .. d .. r t .. r ROORI \/11 lAM aad upper 5121 IPIOM l.R V"ra1"n lI.D. IIn.nl1nn 17x. 9/211/R~ PART: 5C080 IIIPUTS: Al9.AllI.Al2.PWRDWII.1I2MIO ....MWC.MRDC Ol"PIITS: IAMDCS ,RAM4110S. RAMRIIOS. IAMI IIIIOS. RPIOMCR NITWORK: RAMOCS • cOllr (R"MOeS.VOO) RA·N4KOS • OON' (RAN4KCS. YCCI IAM81CS = cOllr (R ..MBICS.VCel IAN111KOS = CON' (RANIIIKeS.VOOl RPROMeS = oOllr (BPROMCS.YeC) AI9 • TNP (AHI) A\3 = tllP (Al3) A12 = TNP (A I 2 ) PWRDWN = tllP (PWRDWII) S2NTO = TNP (S2NTOI . NRDC = IIIP (MRDC) ANWO = TNP (ANWe) RQIIATtOIlIl: RANRKeR = 1(IMROe*V2 .. IAMWCn2): RAMIIIKCS = 1(IMROe*VlI .. IAMWCn3): RPRONCS. 1(IV7 .. IVB .. IV~ + IV4): V7 I(A19*A)lI*AI2*RNARtRI: VII I(A19*A13*/A12*IIIABLBI: V~ I(AIII*/AIlI*AI2*RNARtRI: V4 I(A19*/A13*iA12*BIIABLBI: RNART.~ = IPWIOWNtII2NTO: V3 = 1(IA111 ... 13*A12*BIIABLBI: V2 = 1(IAIII*AIlI*/AI2*RNARtRl: RAM4KCS = 1(INIDe*Yl + IANwenll: V1 = 1(IA19*/A13*A1Z*BIIABLB): IANoes = I(INIOC*YO + IAMwcnOI; YO • 1(IAIII*/AIlI*/AI2*RNARtR): 11110* 292009-5 2·182 inter AP-272 ADF-2 .JR nnnnnl1 h.tel .Jnnullrv 31. IIIA6 IICOIIO a IIC060 Decoder for BOCBB .v_tn. - 161 RAM eDd upper 5121 BPROM PlUM pnwnr dnwn r.irr.uit tB Yer.io. 3.0, Be•• li.e 17x, 9/26/B5 PART: IICOIIO TNPUTS: A19,A13,A12,PWRDWN,S2MIO,AMWC,MRDC,82CB4CLI OIlTPIITS: RAMOCS, RAM4KCS, RAMAKCS, RAMISKCS, RPROMCS, STOPCI.II, AOCAACI.K NRTWORK: RAMOCS = CONr (RAMOCS,YCCI RAM4RCS = CON' (RAM4KCS,YCCI RAMBICS = CONr (RAMBICS,YCCI RAMIIIKCS = CON' (RAMISKCS,YCCI RPROMCS = CONr (BPROMCS,YCCI STOPCI.K,STOPCU' = ROR' (PWRDWN,R2CA4CI.KA,GND,GND,VCC) AOCRBCLI = CONr (BOCBBCLI,VCCI PWRDWN = TNP (PWRDWNI A2CA4CLIB = CLIB (B2CB4CLII AOCARCT.K = OR (STOPCI.K', A2CR4CT.K1 R2CB4CLI = INP (R2CR4CLII AlII = TNP (AIIII AU = INP (Al31 AI2 = TNP (A121 S2MIO = INP (S2MIOI MRDC = TNP (MRDCI AMWC = INP (AMWCI ROIIATTONS: RAMOCS = I(/MRDC*YO + I AMWC*YO) : RAM41CS 1(/MRDC*Yl + I AMWC*YI ) : RAMBICS = 1(/MRDC*V2 + I AMWC*Y21 : RAM161CS = 1(/MRDC*V3 + IAMWC*Y31: RPROMCS 1(/Y7 + IYIi + IY5 + IY4): YO 1(/A19*/A13*/A12*INABLII: YI 1(/AI!l*/AI3*AI2*RNAAtR): Y2 1(/A19*A13*/A12*BNABLBI: Y3 1(IAIII*AI3*AI2*RNAAtH): Y7 /(All1*A13*A12*BNABLBI: Yli I(AI!I*AI3*/AI2*RNAAtHI: Y5 /(A19*/A13*A12*BNABLBI: V4 IIAIII*/AIU/AI2*RNAAJ.RI: KNABLB = IPWRDWN*S2MIO: RND. 292009-6 2-183 inter AP-272 .JR Donnell Tlltel .January 31, 1986 110080 ADF-3 o 150080 Dftr.oder for ROCRR av.tea - 161 IAN aDd upper 5121 IPION Plu. pnwp.r dnwn nirnuit Ptu. wait .tate ~ircuit T.II Y"rainn 3.0. Rn."lin" 17 .. , 9/28/R5 PUT: 5C060 INPUTS: A19,AI3,A12,PWIDWN,S2NIO,AMWC,NIDC,82C84CLI,ALI,WAITCS Oll'l'PII'I'II: RAMOOII,RAM4KOII,RAMRKOII,RAMI8KCII,RPROMCII,II'I'OPOT.II,ROORROT.II,R20R4RDV NITWOII: RANOCS = OONr (IANOCS,YOO) RAM4R08 = OON' (RAM4KOII,YOO) RAN81CS = CONr (IAM8ICS,YOC) RAMI8K08 = OON' (RAMI8KOII,YOO) KPRONCS = CONf (IPRONCS,YCC) 8 'I'OPOT.II, 81'OPOT.Kr = RORr (PWRDWN, R20R4CT:KR, OND, OND, YOO) ROORROtl,BOOBBCLlr = COIf (80CBBCLI,YCC) R20R4RDV = RON' IR20R4RD'ltD,ROORROT.IIR.R20R4RDVO,OND,YOOI PWRDWN = INP (PWRDWN) R20R40T.KR = Ol.KR (R20R40J.II) ROORROLI = OR (STOPCLlr,B2CB4CLI) R20R4CT.K = TNP (R20R40J.l() Al9 = INP (Al9) AI:! = TNP (AI:!) Al2 = INP (Al21 82MTO = TNP (S2MTO) MRDO = INP IMRDC) AMWC = TNP (AMWO) ROORRCLl8 = CLI8 (B008BOLIFI WAT'I'OIl = TNP IWAT'I'OSI ALI = INP (ALI) ROIIA'I'TONII: RANOOS = II/MIDC*YO + IAMWO*VO); RAM410S /(/MRDO*Yl + I AMWOnl ) ; RAM81CS = 1(/MIDC*Y2 + / AMWO*Y2) ; RAM1SICS = /(/MRDC*Y3 + IAMWOnS); RPROMCS If/V7 + /VS + IV" + /T41; VO /(/A19*/A13'/A12.INA8LI); VI = IIIAI9*1A13UIURNARJ.R); V2 = /(/A19'AI3*/A12.INA8LI); TS • 1(/AI9.AI3.AI2*KNARtRI; V7 /(A19*AI3.AI2'INA8LI); V8 = I( AI 9U 13'1A 12*KNARUl; V5 = I(AI9*/AI3*AI2.INAILI'; V4 = I( AI 9*/A 1 U/A 12*KNARloK); RNAILI = IPWIDWN.SZMIO; R20R4RDVO /R20R4RDVO; R2C841DYC • IWAtTCS.ALI; RNbS 292009-7 2-184 AP·272 JR Df'"""'" tlltel Jnnunry 31, 19R5 ftCORO LEF-3 o IICOSO Decoder for 80C88 eyet •• - 18. lAM alld upper 512. IPIOM Plu. pnwnr down r.lrr.ult P1ue .ait .tate circuit tR Vftrelon 3.0, R••• llnn 17x, 9/28/RII PAIT, IIC080 TNP""B: A19, A13, A12, PNIDNI, B2MIO, AMWC, MIDC, B2CB4CL., ALB, WAITCS o""p""s: RAMOCB, NR"WORII, R2CR4RDY RAM4.CB, IAMBICS, IAM1S.CS, BPIOMCS, STOPCLI, BOCB8CL., Al9 = InlAlBl AI:t = TNPIAI31 Al2 = UPIAl21 PWRDWN = TNPIPNRDNNI s2MIO = IIP(S2MIOI ANNC = TNPIAMNCI MROC = tIP(MIDCl R2CR4CU = TNPIR2CR4Cr.1I1 ALB = IIPIALSI WATTCS = TNPIWAT"Csl RAMOCS • COBrlRAMOCS, VCCI RAM4RCS = CON,IRAM4KCS, VCCI RAM81CS = COlrIIAMB.CS, VCCI RAMI811CS = CON'/RAMI8KCS, VCCI KPIOMCS • COlr(IPIOMCS, VCel • . SOOOOD • CI.KR I R2cR4Cr.KR 1 STOPCLI, STOPCLIF = 10I'(PWIDWI, •• 80000D, aND, aND, VCCI ROCRRCI.K, ROCRRcr.lIr = cprrIROCRROI.K. VCCI •• R0001D = CLKS(BOCRBCLlll R2CR4RDY = RON' I R2CR4RDYD , .• SOOOlD, R2CR4RDYC, OND, VCCI IIQUATIONS: 82CB41DYO = NAITOS' • ALB, • • SOOOI 0 • ROORRor.II', RZCB41DYD = IWAITOS' • ALII', BOCRRor.1I • /s"OPOT.llr' • R20R40U'l', · .SOOOOO B2CB4CLI, RPROMOS • IA19 • PNRDNN', • s2MTOl' , RAM1S.CS = MIDC • AMWC + A19' • Al3 • AlZ • RAMncs • MRDC • ANNe + • AlS' • RAMRKes • MRDC + A18' * AlA' RAMOOII • PNIDWN' • S2MIO, • PWIDNI' • 82MIO; Al2 • PWIDNII' • 82MIO; ANNO AlS • AU' MRDC • ANNe + A18' il AU' • Al2' • PW.DO' • SlMIO; lINDI 282009-8 2-185 AP-272 RPT-3 .JR Donnell Tntel JAnuary 31, 1986 /lC060 o IIcoao Dft~ndftr for 80C88 .vete. - 16K RAM and upper 512K BPROM PluA pnwftr dnwn r.;rr.u;t PluA wRit state circuit LR V~r8ion 3.0. Rn.~lin~ 17~. 9/26/65 IIC060 GND PWRDWN GND RND WAlTCS AU 62C84CLI NRDC ANWC S2NTO Al2 aND -: -- -: -: -: -: -: 1 2 3 4 5 6 7 6 9 10 -: 11 -: 12 24:23:22:21: 20:HI: 18:17:16:111:14:13:- Vee ~ AI9 STOPCLI 62C64RDV 80C88CLK RPRONCS RAM16KCS RAN6KCS RAM4KCS !lANOCS Al3 GND UTNPJJl'SU N""f! Pin Rp.Rnurr.p. PWRDWN 2 INP NC"II 1/ PTf'lr1ll9 MCr II s Ji'PP.tI .. : OR Clnnr Clnr.k 1 4 II 6 7 R WA ncs TNP II 01 R 2 -2 ALB 6 INP 12 01 8 2 2 R2C64CT.K 7 TNP 13 01 II 3 NRDC 8 INP 14 0/ 8 5 6 7 6 ANWC 9 TNP III 01 R II 6 7 6 112NTO 10 TNP III 01 R 4 /I 292009-9 2-186 inter AP-272 6 7 R AI2 TNP II 1\ 6 7 R AI~ 14 TNP 1\ R 7 R AlII TNP 2~ 4 1\ 6 7 R **OlJ,PlJ,.S** N,..f'! Pin RC"lltourr.f! RAMOCS 15 CONF NCnl1 P'I'nr.s. II B 2/ B 21 R RAM411CS 16 COirF 7 RiMBICS 17 CON' 6 21 8 RAMI611CS IR CON' 5 21 R BPIOMCS 19 CONF 4 11 8 ROCRRCT.II 20 COlF :I II R R2CB41DY 21 RONrA 2 1/ 8 S,.OPCT.1t 22 RORFA II II NCnlh , ...,d.: OR Clnnr CI"ck 2 :I .:. ,*lJNlIRIIU nSOURCBS .. N••• PiD a•• oure. PTer •• MC"l1 I :I 4 A 10 R R 13 . .PAR,. 11TH. T?AnON .. Rtll R711 All PiD. M.. "rnC.lt. Pt.r•• 292009-10 2-187 inter , APPLICATION NOTE , AP-276' June 1986 Implementing a CMOS Bus Arbiterl Controller in the 5C060 EPLD DANIEL E. SMITH APPLICATIONS ENGINEERING INTEL CORPORATION Order Number: 292012-001 2-188 AP-276 INTRODUCTION 5C060 IMPLEMENTATION This application note shows how to implement· a CMOS Bus Arbiter/Controller in an Intel SC060 EPLD (Erasable Programmable Logic Device). The note includes a brief overview of a similar circuit implemented with typical PLA devices, a more detailed discussion of the SC060 implementation, and a summary. The equivalent functions for both the MULTmUS I arbiter and controller fit inside a single SC060 EPLD device. The SC060 device is available in a 24-pin O.3 w DIP package. Figures 4 and S show logic diagrams for the arbiter and controller functions. When 'compared with the PLA implementation, some differences in the design are immediately apparent. These differences result from the characteristics of the EPLD macrocell or from corrections to the circuit used in Figures I and 2. The bus priority resolution and arbitration scheme selected for the circuit is that used by the industry-standard MULTmUS I interface. Operation and timing for the MULTmUS I interface is well understood by most engineers and is described in readily available Intel publications. Thus, a description of the MULTIBUS I interface is not included here. The bus arbiter/controller functions shown here support both serial and parallel priority resolution between bus masters. Timing is equiValent to MULTIBUS I specifications. Electrical specifications for both the PLA and EPLD approaches vary from MULTIBUS I standards. Neither of the two circuits discussed here provide the full current sink capability for all MULTmus I signals. Because the EPLD implementation is designed for CMOS systems, however, this requirement is not relevant for the SC060 implementation. PLA APPROACH The functional equivalent of a MULTIBUS I arbiter/ controller can be implemented in two 2O-pin PLA-type devices as shown in Figures I and 2. (Figure I shows the logic for the arbiter device. Figure 2 shows the logic for the controller and the connections to the arbiter.) Figure 3 shows the arbiter list file as an example of PLA-type files. Two different 2O-pin PLA devices are required to implement the arbiter and controller functions, a 16R4-type device and a 16L8-type device. Implementation of logic devices in PLA-type devices, .such as those shown here, has proven to be quite beneficial. Development time and cost is much less than for custom silicon device designs. The two PLA-type devices take up less board space than a discrete TTL implementation of the same functions. In addition, the two raw devices can also be uSed for different functions in other products, thereby reducing inventory costs. As a result of these factors (and others), use of PtA-type devices has grown substantially in recent years. With the increased density and flexibility of EPLD devices over typical PLA-type devices, even greater space, inventory, and cost savings can be obtained by using EPLDs. The following section shows an implementation of the same arbiter/controller functions in a single 24-pin SC060 EPLD device. The major change resulting from the EPLD macrocell structure concerns the EPLD output butTers. Since output butTers from macroce1ls are non-inverting (PLAtype devices typically contain inverting butTers), signals enter the butTers in the same logic orientation from which they are to appear at the output. The logic for the EPLD (shown in Figures 4 and S) incorporates this change. Some errors in the PLA-type implementation have also been corrected in the EPLD design. These changes are as follows: • The M/IO input to the MRDC/ and MWTC/ gates is inverted. MIlO distinguishes between memory and I/O cycles. The PLA-type implementation does not use this signal properly; the PLA-type controller generates read or write commands to both memory and I/O at the same time, which can result in contention between memory and I/O during bus transfers. • BPRO/ is gated by BPRN/ in the EPLD design. When using serial priority resolution, this allows the highest priority arbiter to prevent all other masters from controlling the bus. (In the PLA design, BPRO/ is enabled/disabled only by a local request. Higher priority arbiters cannot disable all other arbiters. This can result in contention between bus masters. By gating BPRO/ with BPRN/ in the EPLD design, this source of bus contention is prevented.) Figure 6 shows the list file for the arbiter/controller device. Figure 7 shows the report file produced by the iPLDS software. This file contains a pinout diagram of the final programmed device and provides a resource usage map for the device. Most of the input and output signals are self-explanatory to those familiar with Intel processors and the MULTIBUS I interface. The XREQ input is the bus transfer request signal from the address decode logic. The BUSY/and CBRQ/ outputs are bi-directional, simulated open-collector outputs. These outputs use the iPLDS SC060 (Combinational-Output I/O-Feedback) primitive in the list file. The BUSY/signal serves to illustrate this use of EPLD outputs. 2-189 intJ AP-276 A pull-up resistor is used externally (i.e., on the backplane) to hold BUSY/ high when no arbiter is in control of the bus: When the arbiter is granted control of the bus, AEN is clocked high, which enables the output of the BUSY/driver. Since the input to the' BUSY/ driver is low during normal operation (RESET! inverted), the enabled driver pulls BUSY/low to signal other' . arbiters that the bus is in use. When the arbiter is finished using the ·bus, AEN goes low to disable the BUSY/ driver (three-state output). The pull-up resistor pulls BUSY/high to signal other arbiters that the bus is free for use if needed. Note that BUSY/is also routed into the bus- grant logic as input BSI. BSI prevents the arbiter from taking control of the bus (and driving BUSY/low) when some other arbiter already has control of the bus. Thus only one arbiter may pull BUSY/low at anyone time. The one difference between standard MULTIBUS I logic levels and the EPLD implementation described here relates to the BCLK/ signal. MULTIBUS I bus arbitration uses the negative-going edge of BCLK/ to synchronize events. All SC060 flip-flops, however, clock on th.e positive-going edge of BCLK/. If all bus masters in the system use the same arbiter implementation, this poses no problem. Otherwise, an external inverter is required for the BCLK/ input. COMPARISON/SUMMARY Both the PLA and ,EPLD implementations of the bus arbiter/controller result in a lower device count than a discrete logic circuit. Lower device count means less p.c. board space, fewer assembly steps, and fewer device interconnects. Both PLA. and EPLD implementations are quicker and lesS expensive tp develop than a custom gate array or dedicated silicon device. In contrast to the PLA approach, however, 'the EPLD implementation requires only a single device, while the PLA approach requires two different devices. Thus the EPLD approach results in twice the cost savings (inventory and assembly) and half the programming activity to produce the device. Fewer device interconnects also means greater reliability. In addition,programmed EPLD devices can be erased and reprogrammed for a different application if needed, a feature not available with PLAs. Overall, the greater flexibility, and the incremental design, manufacturing, and cost advantages of EPLD devices make them ideal for many applications where PLA devices would otherwise be used. 2-190 AP-276 RESET SREO RD BPRO (REO) WR ~LK---------------------~----------~ 292012-1 A) Request Synchronizer RESET ----_-f + ....~ AEN--.... RESET=P-EJSREO D 0 DEN BPRO ~-++-I...J WR-I-+-+-I AEN BCLK B:: RD-+-+-I--I AEN (GRANT) --------------..1 ---;Do--.. ___ L-[:>o BREO AEN BPRN ......-+-+-1..../ BUSY -+-+-1--1 CBREQ -------f ~~----------------------~ 292012-3 292012-2 B) Grantl Access Logic C) Bus Transfer Control Figure 1. PLA Approach to a Bus Arbiter 2-191 AP-276 .------------------. PLA 16La iNfA--------+----a ""---'--' M/~-------------~--1_~ BUS CONTROL LOGIC ------------_ .. ii6 Wi SiiEo AEN PLA 16R4 Biffii BPRN CBREQ Rffii' BUsY BUS ARBITER iiPRO SCLK 292012-4 FIgure 2. Bus Controller wIth ArbIter Connected PLA16R4 ARB001 MULTIBUS I ARBITIR BOMI SYITIM OOMPANY BOLl IWR IRD ISRIO IRISIT IBPRK II ICBRIO IBUSY IBYNC IBPRO lAIN SYNC := IRISIT.SRIQ.WR IRISn.SRIQUD BPRO : = IRISn.SYKO AU : = laiSIT. AIN.BPaO.WR OIK : = IRIsn*SRIQUn NO NO KC 10lK IBRIO KO OND VOO + + IRISIT. AIK.BPRo.aD + IRISIT.BPRO.8PRN*IBUSY + IRISIT* AIK*BPRK.IOBRIQ If(BPRO*/AIK) CBRIQ Ir(AIN) BUSY BRIQ PLA DISIGK fILl D. I. IKOR. 1/1/85 = BPRO = BPRO*/AIN = AIN + An 292012-5 Figure 3. LIst File for PLA ArbIter 2-192 intJ RESO~~---4--~~ XREQ ~~-------L.-I BCLK~~--------------~~------------~ BPRN~~--~~)---------------------------~ 292012-6 A) Request RESO---~__ +-,""' SREQ - - - - -.... BPRN --t-f-II-IL-~ BSI --+-1--1-1 AEN AEN - ....+--1-1 CBI------1 BCLK----------~--------------~ 292012-7 B) Grant RESO X:: __ BCLK ~ -I~ RE:: CMDEN ---~~>--B-S-'J-- - O .... BUSY 292012-8 292012-9 D) Busy C) Command Enable SREQ --1...........----_ AEN ~-""--_ 292012-10 E)CBRQ FIgure 4. LogIc DIagram of Bus ArbIter FunctIons 2·193 inter AP-276 INTAIN D------~.... JI---a INTA M/iO D---~H__ >--+-<:1 iORC >-+--<:::J lowe RD C:*+-+---il--l >-+--<:::J MRDC D ....-II----I >--+-<:::1 MRWC WR AEN Figure 5. Logic Diagram of Bus Controller Functions 292012-11 AP-276 DUIIL I. 811ITB INTIL OORPORATION IIAROR 27, 1988 Vl88I08 1.1 Rn. A 110080 01108 IU8 ARIITIR/OONTROLLIR PART: INPUT8: OUTPUT8: 50080 IOLK, XRIQ, RISIT, IP. . , 1110, RD, .R, IBTAIB IP80, AIN, 181Q, CI8Q, IUSY, INTA, 118DO, nTC, I08C, IO.C BI!WORK: IOLK INIAIN • RIQ RISI! IPRB 1110 RD WR IPRO AlN,AIB BRIQ OIRQ,OII IUSY,III INTA IIRDO IIW10 IORO lOwe 8RIQ SYNO OIlDIB IBP (ICLK) .. INP (IBTUN) .. IBP (IRIQ) IBP (RI"T) ,. IBP (IP8B) .. INP (1110) .. IBP (80) = IBP (W8) a OOBr (IP80e,'CO) • R08r (AIBd,IOLK,OBD,ORD,'OO) .. OOBr (18IQe,90C) .. COlr (018Qel,OI8Qe2) OOIl (IUSTe, AlB) OORr (IRTAIR,AIR) .. OOBr (IIIDOe,AIB) .. OORr (nTOe,AIR) = OOBr (IOROe,AIB) • COBr (lOROe,AIR) B08r (SRIQd,IOLK,ORD,ORD) .. R08r (SYROd,IOLK,OND,ORD) .. BORr (OIlDIBd,IOLK,OBD,ORD) .IUB CLOCK INPUT. .INT. AOK. INPUT. .SYSTIII RIQUI8T 18PUT• .RISI! IBPUT. .IUS PRIORITY IBPUT. .1I1110RY/IO INPUT. .RIAD INPUT. ••RITI INPun .IUS PRIORITY OUTPUT. .ADDRI88 INAILI (ORABT) • ..UB RIQUI8U .OIRQI -- 8IIIULATID 0.0 •• .IU8YI -- 8IIIULATID 0.0 •• .INT. ACK. OUTPUT. .1I1110RY RIAD OOIlllAND. ...IIIORY .RITI OOIlllAND. .1/0 RIAD COIlMABD. .1/0 WRITI OOIlllAND. .'ALID IU8 RIQUIST. .8YNCBRONIZID RIQUI8T. .OOIlllABD IBAILI. 292012-12 IQUATIONS: IPROe AlBd IUQe IUITe OIRQel OIRQeI IIRDCe nICe IOROe IOWOe SHQd ITBCd ClIDlBd * ** * * * IIP8B); (881Q .. RI81T 881Q IIP8R lSI + 8181T 8RIQ AIN + 8181T IIP8R AIR Oil; .. 1(881Q + AIN); 181S1!; .. 1(881Q lAIN); .. 881Q lAIR; .. 11110 + RD + OIlDIB; .. 11110 + .8 + OIlDIR; .. 1110 + 8D + OIiDIB; .. 1110 + .R + OIiDIN; .. RI81T 8YBO; .. 8181! 181Q; .. I(U8IT 181Q AlB); ** * ** * * * * INDt 292012-13 Figure 6.IPLDS Network Ust File inter AP-276 Logic Optiaizin, Coapiler Utilization Report ***** De.i,n iapl.aented .ucce•• fully DANIIL I. SMITH INTIL CORPORATION MARCH 27. 1986 YlRSION 1.1 'RIY. A 5C060 CMOS BUS ARBITIR/CONTROLLIR 5C060 BCLI MIO RISBRYID RISIRYID RISIRYID AIN BPRO INTAIN !fR RD BPRN GND -I 1 -I 2 -I 3 -I 4 -I 5 -I 6 -I 7 -I B -I 9 -110 -Ill -112 241231221211201191181- 17116115114:- 131- Vcc XRIQ INTA IOWC IORC MWTC MRDC BUSY CBRQ BRIQ RUIT GND *,INPUTS*, Naae Pin BCLI MIO I •• olaree MCell , r •• d.: PTera. MCell. INP 01 Clear Clock CLK! 2 INP INTAIN B INP 14 0/ 8 WR 9 INP 15 0/ 8 2 4 RD 10 INP 16 0/ 8 3 5 BPRN 11 INP 12 13 RlSI! 14 INP 6 9 2 3 4 5 10 11 12 XRIQ 23 INP 9 10 292012-14 Figure 7. iPLDS Report File 2-196 intJ AP·276 ..OUIPUIS .. .... Pill a ••ourc. Ne.ll • PI.r•• IIC.U. r ••d.: 01 8 aoar 12 3/ 8 'I -'I 8 9 12 1 2 3 AI. Cl •• r Clock Cl.er Clock 4 1'1 8 IPRO co.r 'I 13 1/ 8 lalQ 11'1 co.r 8 1/ 8 ClaQ 18 con 'I 1/ 8 12 IUSY 1'1 con 8 1/ 8 12 DBC 18 CORr 1'1 1/ 8 IIWIC 19 CONr 4 1/ 8 10IC 20 CORr 3 1/ 8 10WC Zl CORr 2 1/ 8 INn 22 co.r 1 1/ 8 • PI.ra. 9 1/ 8 •• luaIID RIGI8Tla8 •• .... PiD a •• ourc. 3 .oar IIC.ll IIC.U. r ••d.: 01 2 3 4 1'1 4 .oar 10 1/ 8 1'1 .oar 11 1/ 8 U 'I 'I 8 12 13 .... .aUIVSID alSOUICISaa PiD a••oarc. IIC.ll PI.ra. 13 "PAal UTILIZAtIO... 91'1. 100. 11. PiD. lIecroC.l1. Pt.r•• 292012-15 figure 7. IPLOS Report File (Continued) 2-197 inter APPLICATION NOTE AP-304 . March 1987 Simulation of EPLD Timing PEDRO VARGAS PROGRAMMABLE LOGIC APPLICATIONS INTEL CORPORATION Order Number: 292027·001 2·198 AP-304 cepts, engineers will be able to simulate their designs and have a better understanding of EPLD timing. INTRODUCTION Though there are many important activities that are considered in a design, timing analysis usually heads the list when it comes to evaluating functionality and performance. Timing issues are prevalent during design, and at reviews when worst case analysis is performed. By being familiar with timing specifics of EPLD architecture, the designer can assess timing issues throughout the design phase. EPLD STRUCTURE Intel EPLDs consist of a programmable logic array and a conflgUrable I/O block as shown in Figure 1. The array is composed of two-level logic, incorporating a programmable AND array and a fixed OR array. The AND matrix is a crosshatch of the true and complements of all the pin inputs and the AND array inputs. At each intersection there exists an EPROM cell that determines if that input feeds the AND gate. By selectively programming these EPROM cells, complex logic functions are implemented in the familiar sum of products form. The output of the OR gate feeds an I/O architecture block that has a variety of programmable options. Combined, the logic array and I/O block is called a macrocell. Each macrocell output exits via an I/O pin. OBJECTIVE This application note details the internal timing of Intel EPLDs. It breaks down the internal architecture into functional timing elements to extract timing data, and then presents a method of timing simulation. The relationship of these elements to data sheet parameters is also shown by several examples. By applying these con- 0 OE 2 •• 5 7 6 8 • I. 11 10 12 ,. '15 17 16 18 ,. ClOCK 21 20 23 22 25 2. 27 2. 31 29 28 30 33 32 35 3. 11"'\ P B gp B ~ ~ ~ ~ ¢ ~l,. 3 ~ ~¢ ~ ~ ~¢' 18 17 16 11 NOTE 0 =1/0 PIN IN WHICH LOGIC ARRAY INPUT IS FROM FEEDBACK PATH ~ 15 ' ~ tl,. ~ ~ CLOCK ARCHITECTURE CONTROL ~ ~o 1 FEEDBACK 13 PLA BLOCK I/O ARCHITECTURE BLOCK 292027-1 Figure 1. EPLD Macrocell 2-199 AP-304 EPLDs have two specifications that influence delays within· the component, maximum propagation delay (tPD), and minimum clock period (tPl). Propagation delay is the time that it takes a signal to appear at the output relative to the input. tPD is defined for conibinatorial outputs. Minimum clock period is the smallest allowable clock cycle that determines maximum. operating frequency. Maximum operating frequency (tMAX) '. is defined for registered functions. The top figure shows that SIGNAL A has two cumula~ tive speed paths in the gate array circuit. In the EPLD inplementation, each product tenp has the same !lelay and there is only one array delay. Intel EPLI>s have inputs that range from 18 (sam).to 64 (SC180). Because the parts are ~~terized !it worst case, the array delay is the same regardless of inputs used. In the case of product terms, the EPLD family supports from 74 to 480. Here again, the number' of product terms does not affect the array delay. Unlike gate arrays that deal with individual gate delaYS, EPLDs have internal delays that are grouped differently. With a gate array, a.logic function may have different speed paths for each product term, depending on the !;lumber of two input NAND gates in each path. In an EPLD, each product term is the equivalent of a multi-input AND gate. Figure 2 shows a comparison of gate delays and array delays. The VO block varies in complexity within the EPLD family, but a typical arrangement is shown in Figure 3. VO programmability is accomplished by configuring for register types and choosing one of several outputs or feedback paths. Timing paths and delays depend on the way the output and feedback muxes are configured. Gate Arrey Delays SIGNAL f~ ~'I~-(~~~~" I.: 2 GATE DELAYS j tpd =(GATE DELAy) x 2 292027-2 EPLD Array Delays 'SIGNAL ABC D E F 292027-3 Figure 2. Logic Delays '2-200 AP-304 MORE ON ARRAY DELAYS The number of inputs and product terms used in an EPLD array doesn't change the array delay because the EPROM cells are always connected, whether they are programmed or not. As a result, when a device is tested the array delay is at worst case load already. When the same design is implemented in a different EPLD, the array delay will be different, due to the different IC geometries. For example, a simple three to eight decoder implemented in a 5C032 will have an array delay of 17 ns. The same decoder when implemented in a 5C060 will have an array delay of 30 ns. D 292027-4 292027-5 tAD = 30 ns Designing an EPLD circuit involves working with the Intel iPLS[3] (Intel Programmable Logic Software) logic primitives. Logic primitives are functional building blocks that the EPLD software requires to implement a circuit. The primitives consist of input, logic, and output functions such as INP, AND, OR, CONF, RORF etc. Because of the modular nature of the design primitives, the resulting logic implementation is very modularized and lends itself well to an analysis of timing paths. The following sections detail the delays involved with each primitive. TIMING ELEMENTS Each EPLD macrocell can be functionally modeled with the seven blocks shown in Figure 4. The macrocell timing model consists of input buffer delay for the inputs and the clock, array delay, register delay and output delay. The model shows the feed forward path as well as the combinatorial and registered feedback paths. The feedback paths may apply depending on the application, and whether the design is combinatorial or registered. The model also applies to devices that have global and local buses. Combinatorial designs with no feedback contain three functional blocks for input, array, and output delays. Four blocks are required for a design with feedback. Register designs may be more complex but contain at least five blocks. These are: input, array, output, register, and clock delays. The delay for each block is defined as: 1. Input Buffer Delay (tIN)-The delay associated with the input pin and buffers. One delay value applies to both true and complementary buffers that drive the AND array. 3. Output Buffer Delay (too)-The delay associated with the output pin and buffer of each macrocell. Combinatorial outputs have a delay measured from the output of the OR gate to the pin. Registered outputs have the delay measured from the register output to the pin. The delay value is the same for either output configuration. 4. Combinatorial Feedback Delay (tCF)-The delay from the output of the OR gate to the input of the AND array. The delay is measured when both the true and complement of the signal appear at the input of the array. 5. Register Delay (tRo)-The delay through any flipflop. The delay is measured from the triggering clock edge to the time when data is valid at the output of the register. 6. Register Feedback Delay (tRF)-The delay from the data valid at the flip-flop output to the time it appears in true and complement form at the array input. 7. Input Clock Delay (tIC)-The time that the clock is delayed in reaching the input of the internal register. Use of these delay paths depends on the EPLD output configuration. Figure 5 introduces the concept of timing elements that is used throughout this application note. Use of these elements depends on the application. If a design is combinatorial, then the only paths to consider are the input buffer, the array, the output buffer, and the combinatorial feedback path. Conversely, if a design is registered, the paths to consider are all of the previously listed delays, with the addition of the register delay, the clock delay, and the registered feedback path. 2. Array Delay (tAO)-The time that it takes a signal to propagate through the AND array and appear at the output of the OR gate. This delay is characterized at worst case and is independent of number of inputs or product terms. 2-201 The,manner in which the delay values are used is called simulation. Simulating a EPLD circuit means calculating the output timing of a device from internal timing with the aid of timing data and simulation model (like Figure 5). Before we get into simulation let's examine how these internal timing elements relate to the data sheet specifications of each device. inter AP-304 OE .--------------------------. ~~lm : r-------1~--+t,.-4-,....~-....., : I ......-++-1 >-....Cl/O FEEDBACK 292027-6 NOTE: Controls shaded in gray are available on the 5C031 only. Figure 3. I/O Architecture Control I> INTERNAL CLOCK CLOCK DELAY (tiC) INPUT DELAY (tiN) REGISTER DELAY (tRD) OUTPUT DELAY (too) COMBINATORIAL FEEDBACK DELAY (tCF) REGISTERED FEEDBACK DELAY (tRF) 292027-7 Figure 4. EPLD Delay Blocks 2·202 AP-304 t-----~P':....-----I·I 292027-8 Combinatorial 292027-9 Registered Figure 5. EPLD Delay Paths DATA SHEET SPECIFICATIONS which provide the designer with the worst case data that they may need for their application. Timing specifications for EPLDs are found in the data sheets under "A.C. Characteristics". Data sheet values are derived by testing a device under worst case conditions. Test conditions are both static and dynamic based on several variables like input levels, output loading, frequency, and temperature. Characterizing a device involves detailed testing of specific device functions and correlating test data to performance analysis done during design. The results are placed in the data sheets, The timing data found in EPLD data sheets is derived from the timing elements previously described. Since an EPLD design can be broken down into either a combinatorial or registered macroce1l, the data sheets contain specific information for each mode. Figures 6 through 10 correlate the timing elements to data sheet values. Each fJ.gUre shows the delay path as it applies to the Intel design primitives and the simulation model. 1. Propagation Delay (tpo) Defined as the time required for an external input to travel through any combinatorial logic and appear at the external EPLD pin. This specification applies to combinatorial logic with non-registered output. Figure 6 shows that this specification is the sum of tIN, tAD, and toO. , DATA SHEET = _ _ M..;;.;OD;;.;;E""L_ !po [; I COMB~~~~R~L I I Frt>1 . +. r'1N •• I • ~I I ----II ~ DESIGN PRIMITIVES tA.O •• ARRAY tiN toD SIMULATION MODEL tpD • + tAO + too INPUT::::::X OUTPm I 292027-10 Figure 6. Propagation Delay (tpo) 2-203 INPUT OR I/O DATA VALID j:: tpD =I ){'-ro--W-BI~--ro-R-~-L-O-UTP-U-T-V-A-LlD-292027-11 intJ AP·304 2. Setup Time (tsu) The set-up time is the time required for the input to settle at the input of a register before the triggering clock edge. Set-up time is the sum of tIN. tAD. minus the internal clock delay. This relation is shown in Figure 7. DATA SHEET tsu MODEL + tAO -, tiC tiN cliN>p____tl_c~ r ~--'-~r----:~~.....,~-.., tlN I CLOCK INPUT INP t t: Isu----J I ::::x INPUT OR I/O DATA VALID -I tiC IN~~~ ---.J I I-- ~N +tAD r- Ii---......_ ......r :::I INTE~~~~ _ _ _ _ _ _ _..JX~--D-ELA-YE-D-DA-TA-- 292027-13 Setup Til)19 (tsu) 292027-12 Figure 7. Setup Time (tsu) 3. Clock to Output Delay (tc()!) Defined as the time required for a signal to pass through a register and appear at the EPLD external pin relative to the external triggering edge of the clock. This ,delay is the sum of tIC. tRD. and toD as shown in Figure 8. DATA SHEET tOOl MODEL tiC + tAO + too r ·--------tC01-;:::;;::;=:;:=~ INP CLOCK INPUT' I -I DESIGN PRIt.lITIVES DELAYED CLOCK t-------t'c tIC r,i---." ----l OUTPUT SIt.lULATION t.lODEL ...._ _... I-- tRO+too j INPUT I I r Xr---D"'ELA--YE--D-D-AT-A--292027-15 -..J 292027-14 Figure 8. Clock to Output Delay (teod 2-204 intJ AP-304 4. Minimum Internal Clock Period (tp\) Defined as the maximum frequency at which an EPLD can operate when register inputs are dependent on internal logic only, and not affected by external inputs. Another way to think ofthis time is, as the fastest rate that a signal can be routed from register to register through the array via an internal feedback path. This minimum period is the sum of tRD, tRF, and tAD as shown in Figure 9. DATA SHEET MODEL tpl 1+1·---tPI----I'1 ClOCK I (INTERNAL) - - ' ";1- - - 1.._ _ _ :::x:I DATA SETUP AND VALID REG I INPUT • X\.____ I-Itw:j X~------R-ro-'-O-UT-P-UT------->e: ---I=It!F:j _____________-JX~D-M-A-M--AR-RA-Y-IN-P-UT--- =e[;:~ I=tAD:j ____________________.JXr-RE~G-2-IN-PU~T- ~~t_.r_~ ______~J SIMULATION MODEL 292027-17 292027 -16 Figure 9. Minimum Internal Clock Period (tp1) 5. Registered Feedback to Combinatorial Output (tcov This is the time required for an input to propagate through a register, feedback to combinatorial logic and appear at the external pin, relative to the external clock. This time is the sum of tIC, tRD, tRP, tAD, and too as shown in Figure 10. DATA SHEET !c02 MODEL tiC + 'RO + tRF + tAD + too CLOCK~~ :::x:I DATA SETUP AND VALID REG 1 INPUT tAD I- tiC + tRD + tRF + + IoD:j ___________________JX~D~AT~A-O~U~T~V~A~LlO~ ~I'----tlc----+I 292027-19 SIMULATION MODEL 292027-18 Figure 10. Registered Feedback to Combinatorial Output (tC02) 2-205 AP·304 When simulating EPLD designs with data from the simulation tables, it is possible that there, may be a ~mall discrepancy between ,simulation and data sheet v/llues. Because our simulations deal with ideal waveforms, rise and fall times are not taken into consideration. Also, characterization and fmal test of these devices by QA is usually guardbanded[2] by several nanoseconds. The combination of these two items might result in a simulated parameter that is slightly off from the data sheet. For this reason, the simulated results should be considered "typical worst case" and not "absolute". SIMULATION CONCEPTS AND EXAMPLES Simulation of EPLD logic designs provides a quick way to evaluate a particular path within the device. While this might not seem important when the flexibility and the speed of EPLD development is considered, it is advantageous for making design judgements that best utilize device resources. Simulation also proves useful when working with a design that consists of several EPLDs, or other types of logic. In a case like this, it may be desirable to simulate a complex path that propagates through several devices. To simulate a design the engineer needs to either implement it with the iPLS design primitives or understand how the circuit will be i70 implemented by the software. This provides the modularized layout that is needed to choose a model. The decoder circuit shown in Figure II serves as a goo!! starting point for simulation. Decoding two control lines (1/0*, WR *) and four addresses, the circuit might be used to select a peripheral controller residing in that memory area (FOOOH) with output IWRI. It's also common to use intermediate decodes in other parts of the system for other functions, IWR2 accomplishes this. The gate drawing of Figure II shows us that the design is combinatorial and can be modeled with the elements introduced in Figure 5. The design, converted to iPLS primitives is shown in Figure 12. The implementation consists of six input primitives (INP), three logic primitives (NOR2, AND4, AND2), and two output primitives (CONF). In this case, tpD is simulated for a 5C031-50 by plugging in the numbers for the model which requires tIN, tAD, and tOD. The result of 51 ns is very close to the data sheet value of 50. A15 D--I A14 D - - t A13 D_-t A12 D_-I .....----IWR2 WR->JL_' A15--..._ A14 ._----_. ___ e. I I CONF: >-C:>i--IWRl ,..--_ _ _ _ _ _ _-,292027-21 IWRl tpo = tiN + tAD + too Simulated for a 5C031·50: tpo = 10 + 31 + 10 tpo = 51 ns A13 A12---'-292027-20 IWRl = i70 ' WR 'A15'A14'A13'A12 IWR2 = i70 ' WR Figure 12. iPLS Implementation of Decode Circuit Figure 11. Decode Circuit 2-206 Ap·304 The second example is the wait state circuit shown in Figure 13. The circuit shows one way that a synchronous wait state can be generated in an EPLD. This circuit would be used with a microprocessor that samples a WAIT signal on the falling edge of the Tl clock. If WAIT is valid, the micro inserts an extra cycle into the memory operation. After the wait state, the cycle ends normally. The circuit is first converted to the Intel design primitives for -further observation. The iPLS design is shown in Figure 14. One difference from the previous circuit is the addition of a register primitive, in this case a NORF (No Output Registered Feedback). In this application the critical path tea2 is evaluated to insure that the wait signal is sampled at the appropriate time. The modularized layout of the primitives shows that this circuit can be simulated with the registered model of Figure 5. The result is simulated for a 5C032-35 by adding tIC, tRO, tRF, tAD, and too· Our last example is the asynchronous R-S latch shown in Figure 15. Applications that use EPLDs without conflgUrable output registers may use this circuit as a work around solution. The output primitive of Figure 16 is a COCF (Combinatorial Output Combinatorial Feedback) being driven by two NOR2 gates. Because combinatorial feedback to the same macrocell is being used, care must be taken that the input pulses are long enough to avoid output glitches. In this example, the input pulses should be longer than tAD + tcF for proper latching. For this example, tpo is the critical parameter. Simulation results in tpo equal the sum of tIN, tAD, and too. llmlng Signals ClK Walt Slata Generator IiIEIiIR ~~~~:~--..c_~ IIEII'RD ij 292027-22 WAfT .-J ·s 292027-23 Figure 13. Walt State Circuit ~~--------~--------~ ~tlN----+l·I~·--tAD--~- ~K~~--------+------, IIEII ~-----Ir'" l--4~-"""-I RD~~--------~--I ,, ,, ,, • r----------------------------~ t - - - - - - - - tRF - - - - - - - - ' 1+------tAO >-C>4~wArr , ._-----_. ----.+I.-IoD--I , !co2 = tiC + lRo + tRF + tAD Simulated for a 5C032·35: !co2 = 5 + 7 + 3 + 17 + 8 !co2 = 40 ns + too Figure 14. iPLS Implementation of Walt Circuit 2-207 292027-24 AP-304 r-tIN .... ·'.. · - - tAD :~Q R s Q o o Latch I o 1 1 292027-25 1 liNP R 0-----\ ---1--- o •• o 1 "Indeterminate State 292027-26 tpo Figure 15. R-S Flip-Flop = tiN + tAD + too Figure 16. IPLS Implementation of R-8 Flip-Flop SIMULATION CHARTS The charts of Figures 17 through 22 make up the simulation database for EPLDs. Each chart contains the combinatorial and registered models as well as the delay values for each timing element. Feedback paths are shown open because their use depends on the specific application. To simulate a EPLD design the following steps are required: 1. Convert the design to iPLS primitives. 2. Pick the appropriate model from the device simulation chart. 3. Connect any necessary feedback paths. 4. Calculate the.simuiated timing with the element values. Regletered tiC Combinatorial " 292027-27 tRF tiN 292027-28 Element tiN tAD tRO too tiC tcF tRF Delay (ns) 10 31 8 10 8 4 4 Formulas: tpo = tiN + tAD + too tsu = tiN + tAD - tiC tc01 = tiC + tRO + too tco2 = tiC + tRO + tRF + tp1 tAD + too = lAD + tRF + tAD Figure 17. 5C031 Timing Elements 2-208 AC Parameter tpo tsu tC01 tC02 tp1 Model (ns) Sheet (ns) 51 33 26 61 43 50 30 28 65 42 Typical Model Delaya for 5C031·50 inter AP-304 Registered Combinatorial 1 - - - - - - tIC - - - -.. ', ---""'>i--tA0-f ~toDI 292027-29 292027-30 Element tiN tAD tRD too tiC tcF tRF Delay (ns) 8 17 7 8 5 3 3 Formulae· tpD = tiN + tAD + AC Parameter too tpD tsu tc01 tC02 tp1 + tRD + tRF + tAD + too tco2 = tiC Model (ns) Sheet (ns) 33 20 20 40 27 35 25 20 42 30 TYPical Model Delays for 5C032-35 Figure 18. 5C032 Timing Elements Registered Combinatorial 292027-31 1-------- tiN - - - - - -.. 292027-32 Element Delay (ns) 10 Formulas: tpD = tiN + tAD + too - 30 7 10 8 5 5 tco2 = tiC + + tRD + tRF tAD + too Figure 19. 5C060 Timing Elements 2-209 AC Parameter tpD tsu tC01 tc02 tp1 Model (ns) Sheet (ns) 50 32 25 62 42 55 35 25 60 55 Typical Model Delays for 5COSO-55 AP-304 Registered Combinatorial Element Delay (ns) 10 37 7 10 Formulas: tpD = tiN + tAD tsu = tiN + tAD - tiC + tRD tCOt = tiC 7 5 5 tc02 = tiC + + + too too + tRD + tRF tAD + too AC Parameter Model (ns) Sheet (ns) tpD 57 tsu 40 50 45 20 55 50 tCOI tC02 tpl 24 61 , 49 Typical Model Delays for 5C090·45 Figure 20. SC090 Timing Elements Registered Combinatorial 292027-36 Element tiN tAD tRD too tiC tCF tRF De/ay(ns) 12 44 7 12 16 5 5 Formulas: tiN + tAD tsu = tiN + tAD - tiC + tRD tpD = tCOt = tiC tc02 = tiC + + + too too + tRD + tRF tAD + too Figure 21. SC121 Timing Elements 2-210 AC Parameter Model (ns) Sheet (ns) tpD 68 65 tsu 40 47 tCOI tC02 tpl 35 80 33 75 55 56 Typical Model Delays for 5Ct2t-65 intJ AP-304 Registered Combinatorial 292027-37 1 - - - - - - tIO - - - - - - - 1 292027-38 Element tiN tlO tAD too tiC tiCS tcF tRF tsu tH Delay (n.) 12 20 44 19 30 3 5 10 14 13 Fonnulas: AC tpo = tiN + tAD tsu = tiN + tAD - tiCS tool = tiCS + tH + too tco2 = tiCS + tH + tAD tpl = tH tRF + tAD + + Parameter too tpo tsu + too teal tea2 tpl Model (n.) Sheet (n.) 75 53 35 79 67 75 56 30 82 65 TypIcal Model Delays for 5C180·75 Figure 22. 5C180 Timing Elements SUMMARY REFERENCES Timing simulation provides a way to verify a delay path without resorting to external measurements or breadboarding a design. Simulation of EPLDs can be done by implementing the design with the iPLS design primitives, modeling the device, and using the simulation charts. By applying these concepts, the engineer can simulate EPLD designs incorporated in one or more EPLDs. 1. Intel User Defmed Logic Handbook. EPLD Volume. 2. Intel Components Quality/ReHabiHty Handbook. 3. Intel Programmable Logic Software User Guide. 2·211 inter APPLICATION NOTE January 1987 EPLDs, PLAs and TTL Comparing the "Hidden Costs" in Production PEDRO VARGAS PROGRAMMABLE LOGIC APPLICATIONS INTEL CORPORATION Order Number: 292030-001 2-212 AP·307 INTRODUCTION • Prototype costs - fIrSt implementation of the product idea When comparing logic alternatives, too often the outcome is dominated by the piece price of the components. A side by side comparison based on component costs only, may give the appearance that EPLDs are cost prohibitive. However, when the overall cost of manufacturing a system is considered, the higher integration of EPLDs proves to be a cost-effective solution. • Production costs - volume manufacturing of the product Usually, the brunt of the cost for the first two categories is dismissed as NRE (non recurring expense). The effect of these costs on the overall project is examined later, let's look at the third category. Production costs, can be further broken down into; • Component costs- the cost of the parts per board • Inspection costs - labor costs for receiving the OBJECTIVE This application note examines the total costs associated with designing, prototyping, and manufacturing a system. Once these costs have been examined, a comparison is made between EPLDs and other logic alternatives. By being aware of these additional costs, the engineer can make a more accurate cost comparison as a design is begun. COSTS DEFINED Costs can be difficult to pinpoint, let alone measure. However, with a bit of examination, we can break down costs into the following categories; • Design costs - the cost of conceiving a product parts • Inventory costs - the cost for storing, handling and dispensing the parts • PCB fabrication - the cost for labor and equipment used in building a board • Integration costs - the cost of harnesses, enclosures, nuts and bolts etc. It's important to understand how the cost of a product is affected not only by the cost of the ICs used, but also by the other costs listed above. Figure 1 is a graph which shows this relationship. TOTAL SYSTEM COST COST or CIRCUITS M S I - - - - - - - - - - - - - · VLSI CIRCUIT COMPLEXITY Figure 1. Optimizing Circuit Complexity 2-213 292030-1 AP·307 ffiIT~ RESET---~H XREQ ~ Q SREQ ---t-It-IrU:: 3'" BPRN - -...Ht-IL,.;.;;~ AEN BCLK iiSi--i-HH LS74 292030-4 ">--_-OiiUsY AEN AEN ,CMDEN LSl0 -_+---1H AEN LS74 ----4H ~)-I--- AEN 292030-5 Ciii -----t U3 LS21 ">_-0 CiiiiQ i&R------~--------~ 292030-2 SREQ ....L....ur--, AEN ~--,'--, LS08 Ciii 292030-6 ~L>---+--r~ XREQ L > - - - - I . . : . / }---<::JBPRO BC~L>--------~~-----~ ~L>---;~~~---------------~ 292030-3 Arbiter INTAIN 0------------1 >.U;::1-:::0:-:-- -+~- -++- ...... >-+-- SliGO l:l SEGA 12 SEGE BCD2 :-tCell " PTer'ms CONF :!8 .j <:ONF 24 .j 6 15 CONF 21 " .j 17 RORF 19 4 -I I1Ce11s 1 4 5 8 10 12 19 :.!I 2-1 28 BCDO 21 RORF 12 41 8 1 .j 5 8 10 I1 12 19 :!1 24 28 BCD 1 ::!2 RORF Clock 11 3' 8 1 4. 5 8 10 11 12 19 21 24 28 2-242 Feeds: OE <:lear FIGURE 8 (CONTINUED) BCD3 RORF 23 10 3 4 1 4 5 8 10 11 12 19 21 24 28 SEGF 25 CONF 8 41 4 SEGS 2R CONF 5 31 6 SEGC 29 CONF 4 31 6 SEGG 32 CONF -!' 4 **UNUSED RESOURCES** ~8.e PIn Resource 3 4 5 6 7 9 10 11 13 14 16 18 19 24 26 27 30 31 33 '1(".-11 PTp.rms 27 26 10 !l 25 " 23 :! 8 10 12 8 R 12 10 8 8 10 13 14 IS 16 8 8 8 8 22 20 18 17 9 7 6 ..., 34 35 36 NA NA NA NA **PART UTILIZATION** 37' Pins 39' 18' ~8croCells PterlDS CONCLUSIONS The complete design took less than an hour to enter, compile, and link with EPLDs. The ability to partition designs, then individually implement those designs in the logic design 2·24~ entry of choice, and finally to link designs together is a new design method only available with advances in programmable logic and their design tools. By taking advantage of these capabilities, designers can bring logic implemen,tations to market faster and with a high degree of integration. AR-4S0 VLSI DESIGN TECHNOLOGY Crosspoint Switch: A PLD Approach by .1m DomeI, Intel Corp. device dictates the number of switches that can be designed into rasable programmable logic devices (EPLDs) combine a single device. the gate densities oflow-end gate arrays with the short Configuration 1 development time and low cost of EPROMs. This The first circuit (Figure 1) considered is a digital crosspoint merging oftechnologies producers a device with features suited to a wide range of digital applications. In contrast to the long switch with' eight inputs and a 3-bit word width. This switch transfers a 3-bit word coming from one of eight sources to a pardevelopment times (and higher costs) for gate arrays, EPLDs require minimal frontend design time. In just a few hours, ticular output. The number of devices "OR-tied" to each outEPLD designs can be developed, modified and verifjed. Also, put pin determines the number of outputs. Selecting one of eight core elements from one EPLD design can be incorporated indata inputs from each of the three channels (AD to A7, BOto B7 and CO to C7), the switch routes that data to a single output (QA, to new designs as quickly as standard software subroutines from one program can be modified and used iii other programs. QB and'QC}. Each output can be OR-tied to more than one The design of a digital crosspoint . switch using an Intel 5C12I EPLD illustrates these features. Digital Design implemented a crosspoint switch in a gate array last year (see Digital Design, January through March, 1985). Applications that require a data transfer from one of several inputs to one of several outputs frequently use a digital crosspoint switch. Using the 5C12I EPLD, Intel Corp. (Santa Clara, CA) designed three different configurations of a crosspoint switch. Offered in a 4O-pin package that provides up to 36 inputs or 24 outputs, the 5CI21 supports up to 28 macrocells (including four buried registers) and 236 product terms (p-terms). Logic density in the 5CI2I is the equivalent of 1,200 usable NAND gates. Maximum power requirements are 100 rnA active and 30 rnA standby with TTL input levels. With CMOS input levels, a 5CI21 requires 50 rnA active and 3 rnA standby. Two major \lIIfIlIIIeters /letermine the conipleXity and configurillion of a digital crosspoint ~itCh: the number of possible switching 19(:ations for each bit (inputs l\IId outPl\ts), lIDd the nu",ber ofbits , COnfiguration 1 uses multiplexer circuit with latching on· transferred in one' clOCk pulse (word' 'Flgu;el: puts. Each output can dnve multIple, 'Individually selected Inputs to'complele the dIgital croS$· width). The availability' 0(110 pins, point swllch, By connectIng Inputs to the EPLD outputs in an "oR-tied" confIguratIon, WIth only macrocells and p-terms for a given EPLD one input enabled at any tIme, the multiplexer ~ircult becomes a CroSSPOInt switch, E , © Intel Corporation, 1986 Reprinted with permission from Digital Design 2-244 VLSI DESIGN TECHNOLOGY three-state input to complete the switch (only one input can be enabled at a time). Three additional control bits (00 to 02) select one of the eight different inputs. All three channels operate in parallel. Separate input and output clocks allow a high data rate and relax input set-up and hold times. Input data for all three channels, along with the three select bits, are latched by ILE. Oata at the inputs can change state after being latched and data is clocked out of the switch by CLK. Equation 1 shows the Boolean expression for a single channel in the sum-of-products form. (See Thble 1 for all equations.) The Boolean expression for the remaining two channels is similar: the designer need only change the A in the equations toa B orC. Figure 3: Configuration 2 uses a Single-bit eight·inputleight-output digital crosspoint switch. Designers can Implement this for either Optimal package count (sea Figure 4) orfor optimal speed (see Figure 5). Timing Analysis The internal delay paths determine the circuit's maximum operating frequency (fmax). In this configuration there is an input delay (Tin), an array delay (Thd) , a register delay (Trd) and an output delay (Tod). The fmax is a function of the signals that must settle at the input of the output register before the rising edge of the clock. In this case, signals propagate only through the input latches and the array. Therefore, the data must be valid at the inputs Tin + Tad just nanoseconds before the rising edge ofthe internal clock signal (CLK). However, because of the inherentdelay of the CLK signal, this reference must be shifted to the rising edge of the external clock signal by subtracting the internal clock delay (Tic). The external data set-up time (Tsu) is shown in Equation 2. Inverting this time requirement yields the maximum operating frequency. As the output flip-flops are clocked, data propagates through the register to the output pin. With reference to the external clock pin, data becomes valid at the outputs Tic + Trd + Tod nanoseconds after the rising edge of the clock. Figure 2 shows the timing requirements for this circuit, including the input latch signal. Using a 5Cl2l-50 (50-nsec propagation delay), data can be sent through this switch configuration at 25 Mbits/sec. This transfer rate remains independent of the word width. Since one 5Cl2l EPLO in this configuration can simultaneously transler three bits of information, three 5C121's are required to transfer a byte of data during each clock cycle. This configuration of a digital crosspoint switch uses 86 % of the 40 pins, 71 % of the macrocells and 11 %of the available p-terms in the 5Cl2l EPLD. outputs (QO to Q7). Six control bits are required for each transfer: three to select the input path (DO to 02); three to select the output path (03 to 05). By selecting a single output path and clocking all output registers simultaneously, deselected outputs are automatically cleared. This is useful for designs where only the most current data is needed. Equation 4 is the common equation to select one of eight input paths. Equations 5 to l2 complete the Boolean equations for this example. The previous equations would contain eight product terms if they were written in expanded form. However, by treating SELECTEQ as one signal, each equation contains only one product term. Both options are available in the 5C121. But, there I n contrast to the long development times for gate arrays, EPLDs require minimal frontend design time. are advantages and disadvantages to the two methods. If SELECTEQ is implemented as one signal through acombinational feedback option, one and one-half crosspoint switches can be implemented in one 5C121 (Figure 4). The trade-off is faster speed for low chip count. By design, only 18 macrocells in the 5C121 can support eight product terms. On the other hand, selecting the combinational option reduces the p-terms but introduces an additional input mux delay. Figure 4 shows that an input signal must pass through four delays before,reaching the input to the flip-flop. Again, subtracting the input clock delay to' shift the reference point yields Configuration 2 Equation 13 for the set-up time. Inverting Tsu gives the maxThe second cirCUIt (Figure 3) also selects one of eight inputs imum operating frequency. In this configuration, data can be clocked through at 12 Mbits/sec. This layout utilizes'" %of the (10 to 17), but this time data is routed to one of eight different available pins, 89 % of the available macrocells and 13 %ofthe product terms. Six 5CI21s would be required toimplement a byte-wide switch with this layout. If the combinational fuedback option is not used, there are eight output equations, each containing eight product terms. Assigning these equations to the macrocells that support eight p-terms shows that only a single, one-of-eight select line digital crosspoint switch fits Figure 2: A 40-nsec Internal set-up time (pnorto clocking data through the output flip-flop) marks into one 5Cl2l. Thus, the deSign requires Configuration 1 Data clocked Into all eight Input latches atthe nSlng edge of one ILE/CLK cycle eight 5CI21s to complete a byte-wide is selected and clocked out of the output flip-flop on the next riSing edge of ILE/CLK. DIGITAL DESIGN • JULY 1986 2-245 inter VLSI DESIGN TECHNOLOGY parallel' transfer. Since the signal paths are identical to Configuration I, the same timing analysis applies here. . This layout (Figure 5) utilizes 65% of the pins, ji:) % of the macrocells and 30% of the p-terms. Though the utilization numbers are lower for this example, the actual available pins and macrocells in the 5Cl2I are higher than initially visible. Since macrocells in the 5C121 are organized into groups of four, when one. output structure in a macrocell group is defined the other three must be of the same structure. Many times, this results in unused pins being labeled "RESERVED" in the utilization report. Configuration 3 The final circuit (Figure 6) again uses eight inputs (10 to 17) and eight outputs (QO to ([1), though this time the deselected outputs "remember" their previously selected state. With the 5CI2l's register feedback option, deselected outputs can hold the last data bit sent to that output. New data appears when the output.is selected again. . Equations 14 to 22 express the Boolean terms necessary to implement this hold feature in the digital crosspoint switch. Note that each output is now a function ofboth the present inputs and the previous output (Qntbk), which implements the regiStered feedback. Data bits 03, D4 and 05 determine which data bit will pass to the output. Again, the number of p-terms dictates the use of combinational feedback, as in Configuration 2. Timing Analysis Figure4: Configuration 2 features a low package count layout. Notethat one and one-hall 5W~ches fit into each 5C121 EPLD Ttlls configuration uses combinatorial feedbacks to simplify the logic equations, thus eliminating the requirement for eight product terms per output. This configuration's timing analysis is similar to Configuration 2's combinational feedback analysis, with the exception of a register feedback delay (Trf). Trf is the time that the data is present at the output of the flip-flop to the time that data is available to the array. The total delay associated with the registered feedback consists of the Trd, the Trf and the Thd. Data from the flip-flop output reaches the input in about 50 nsec. The delay associated with data coming from the input pins is the same as that of Configuration 2 with combinational feedback - approximately 83 nsec. Using this as the clock period, there is ample time to implement the register feedback without affecting the cycle time. In this configuration, data could be clocked through at 12 Mbits/sec. Combinational feedback reduces the p-term requirement to two p-terms per equation, This allows one and one-half crosspoint switches to fit into one 5CI21. The design utilizes 64 % of the available pins, 42 % of the macrocellS and II % of the product terms. Six devices would be required to implement a bytewide switch. . All of the configurations function differently, and. no one configuration is optimum for all applications. A designer can customize a device to ineet the needs of an application, whether those needs inclu~e higher speed or lower chip count. A second device can be quickly developed for a different application. Designers are no longer restricted to a single device type that must be adapted to an application with additional logic devices. .JULY 1SBS • DIGITAL DESIGN 2-246 VLSI DESIGN TECHNOLOGY An original design can be developed in an afternoon. Additional devices derived from an original design can be developed in a few hours. Also, the ability to erase an EPLD and reprogram it allows design errors to be corrected immediately. Instead of several weeks delay with gate arrays, a designer using EPLDs can have working silicon devices in one day. Both the flexibility and short design times associated with EPLDs make them a good choice for applications that benefit Figure 6. Configuration 3 shows the use of registered feedback to allow deselected outputs to retain their previously selected data. The logic for a representative channel is shown. As with Configuration 2. this configuration can be optimized for package count or speed. from custom silicon devices. Today, EPLDs offer designers the densities and configuration flexibility of gate arrays, along with the short development time and cost associated with EPROMs. !XI Figure 5: ThiS circuit (Configuration 2 optimized for speed) combines the multiplexer and demultiplexer functions for each channel In aSlngle array. Since each output equation uses eight product terms, only one sWitching channel can fit into each 5C121 package. ..JULY 1986 • DIGITAL DI!BIGIN 2-247 inter D,signer's AR-451 C~rner A Progr,ammable Logic Mailbox for 80C31·Microcontrollers KariheiDi Weigl aDd Jim DODDen, Intel Corp .. Franklurt, West Germany, and Folsom, CA T his article describes the implementation of a semi-intelligent interface between two SOC3l microcontrollers, using a mailbox protocol: Applications for an interface such as the the one described here are often found in industrial cpntrol areas where mUltiple microcontrollers are used to accomplish a given task. Due 'l' the architecture of the microcontroller (i.e., no READY input; no HOLD/HLDA interface; port-oriented 110; etc.), exchanging data and status between these devices becomes a cumbersome task. Given this directive, it becomes the designer's task to develop a mUlti-port memory interface that allows for zero wait-state operation (i.e., no READY signal required), that electrically isolates the microcontroller buses, and that permits asynchronous access. Synchronization would result in the generation of wait states. We realize the logic necessary to implement the desired functions in two erasable programmable logic devices (EPLDs). One device, the 5C031, contains roughly the equivalent of 300 2input NAND gates, while the other EPLD, the 5C060, can implement designs with . up to approximately 600 gates. Po .... ...."-_....._"""1 '''Ap~ The Mailbox Princ:iple ADd Its Implementation In a mailbox memory system, the microcontrollers exchange information as bytes of data written to or' read from a mailbox register. Control logic permits simultaneous access to the mailbox, thus eliminating the need for arbitration between the microcontrollers. Implementing the data exchange in this form achieves most of the design criteria given above. A voiding bus arbitration together with the short propagation delays of the FIGURE 1. Schematic: of mailbox memory system, EPLDs provides zero wait-state operation of the data exchange. Electrical isolation of the address and data buses is achieved by using the high-impedance output capability of the 5C060. Simultaneous, asynchronous access is achieved by separating the RD and WR strobes issued by each microcontroller. With a mailbox memory system, there CopyrightC 1987 by CMP' Publications, Inc., 600 Commun~y Drive, Manhasset, NY 11030. Reprinted With permiSSion from VlSI Systems Design. 2-248 is an obvious need for some type of communication protocol to confirm the reception of a message, or the presence of data in the mailbox. In addition, the read and write logic must be defined such that simultaneous access to the mailbox is permitted. In order to segment the task, the design will be approached in terms of two separate mod- ules: the mailbox (memory section), and the the control logic (protocol). To begin the design of the memory section, it is first helpful to identify the resources required for the design. The mailbox requires a total of 16 memory storage registers (two bytes of data), tristate output control, and two separate clock lines used to write the memory registers. The 5C060 EPLD was chosen to implement the memory section., This device contains 16 programmable register groups that may be configured to operate as JK-, RS-, 0-, and T-type flip-flops. Each register group feeds a bi-directional input/output pin, which may be tristated via an output-enable product term. These 110 pins may also serve as data inputs when the register output is tri-stated. This feature forms the basis of the read-signal logic required in the design. Write logic can be accomplished through the two synchronous clock inputs provided in the 5C060. Each synchronous clock drives a set of eight registers in the device. The operation of the memory section of the mailbox memory may now be solidified. As shown in Figure I,'the two microcontrollers are separated into controller A and controller B. Register group A (sign;ils 10AO to IOA7) serves as an input buffer to rnicrocontroller A. This buffer receives information from microcontroller B's data bus. The write control for register group A comes from microcontroller B. Again, referring to Figure I, it can be seen that register group B serves as an output buffer to microcontroller B. This buffer gets information from microcontroller A and is therefore write-controlled by microcontroller A. Data Transfer In order to read data from the mailbox, the microcontroller must initiate a read cycle addressing the mailbox. The read signal (RDA for microcontroller A, ROB for microcontroller B) enables the tri -state outputs of the 5C060, revealing the appropriate data. Spurious read cycles are avoided by logically combining the read signal with a chip select signal (CSA or CSB) within the chip. The exam-' pie shown utilizes address bit A15 as the WB _ _ _ _ _....... IOAI 1OA2 IOA4 IOAS 10M RcA CSA FIGURE 2. Schematic of register interface. ,', ' WAS· 1 , ',:'~ ·ROB CSA· 2, {~: ~ o' IOA2· 5 1QA3IOA4- '1 10A5- 8, a Group A ' (microcontrolklr A~ , , 100s- 9 IOA7~ 11'ROA· 11 GNO· 12 "'-:' .... ' :,', 24 .vee :~ :," ' I ~ i ~~rolklr .' ,et1 ·IOSS S) ·1066 15 -1087 . ',~ ·e88 ,'"tS ·WRA FIGURE 3. Pin-out for register interface. VLSI SYSTEMS OESIGN January 1987 2-249 Designer's Comer ~ ~= ~:::t...-/ Programming the EPLDs HI----+"I>-- IBEA J!iOlj __ L<~.S---' eSB -,.......,."'--.-' INTB WRe -H-- A6 PORT C . IN4 Vee IN3 INPUTS _ _v AS 104 INPUTS/ OUTPUTS A4 44 PAD PLCC 0.650" x 0.650" Vee TOP VIEW A3 103 A2 102 Al IN2 AO INl 86 290126-1 Figure 1. Block Diagram 290126-2 Figure 2. Lead Configuration 3-1 November 1987 Order Number: 290126-003 ~1m~n..OIMlOOO~ 5CBIC "I·, ,'. trol is. illustrated in Figure S. The Bus Management Unit (BMU), and the Programmable Logic Unit (PLU) interfaqe to, the feedback and the control busses. The macrocells in the PLU feed the input bus. FUNCTIONAL DESCRIPTION As the name suggests, this programmable bus interface controller offers a high integration solution to design problems involving d1lt~ transfer on bus lines and the logic tleeded to control these transfers. This integration directly translates into savings in board space and lower system cost for equivalent functions implemented using conventional SSI/MSI components. ,Bus Management Unit (BMU) . The Bus Management Unit (BMU) comprises three ports: PA, PB and PC (Figure 4a). Each of these ports is bidirectional and 8 bits wide. Data can be routed from any port to any other port. Present in the port-oriented SCBIC are two functional blocks that' enable complex bus functions to be realized: the Bus Management Unit (BMU) and the Programmable LogiC Unit (PLU). .These two units communicate with each other through the input and the feedback buses. A control section shown in Figure 3 steers signals from the PLU to the two units through the control bus. Data into any port can be user-selec~ed' to be latched I>Y a por:t Latch Enable signal, (LE). Routing of la:tched· or unlatched data between ports is achieved using a combination of EPROM architecture and dynamic control signals defined by the user. Data out of any port can be programmed to have an inverted sense through EPROM architecture control (INV). ARCHITECTURE DESCRIPTION Each bidirectional port can be dynamically configured as an input or an output depending on the control signals OEA, OEB and OEC. Latched data from The innovative architecture of the SCBIC incorporating a port-oriented approach for bus interface con- P /2 1 PORT A. , f+---+ ..- ~I INPUT PORT PORT CONTROL '" I FEEDBACK I OUTPUT PORT BUS MANAGEMENT UNIT '1 / CONTROL a ~ l' I- .~ 1 'f . ;r .. .. l' • PROGRAMMABLE LOGIC UNIT ~l.L INa --- INPUT MACROCELL r-' ..... ARRAY PORTC 1--+ PORT B "J:.. INPUT/OUTPUT LOGIC MACROCELL .. . l- •.. 1/07 1/01 1/00. ....,.;. 290126-3 In the tridirectional BMU, any port can be steered to any other port. In this diagram, Port A can be directed to Port B or Port C or both. The PLU provides a 600-gate equivalent PAL function. Figure 3. Functional Blocks in the SCBIC 3-2 inter SCBIC rROM PORT C H-I>""H--Ih~-- PORT B (OUTPUT PORT) Each bidirectional port can be dynamically configured as an input or an output depend· ing on the control signals OEA, OEB and OEC. The feedback to the array is controlled by TFB1, TFB2 and port routing occurs through SELA, SELB and SELC. In the dia· gram, Port A is the input port with possible outputs at Port B and Port C. rROM TO CONTROL rEEDBACK BUS BUS 290126-5 Figure 4a. Bus Management Unit Block Diagram PORT A PORT 8 290126-23 TO FEEDBACK BUS LEGEND: OEA, OEB, OEC, SELA, SELB, SELC, LEA, LEB, LEC, TFB1 and TFB2 are the control outputs for the BMU derived from the control bus. MPCA, MPCB and MPCC are dynamic multiplexers controlled by SELA, SELB and SELC for port selection. MUXA, MUXB, INVA, INVB and INVC are static multiplexers controlled by architecture bits (EPROM bits). All latches are the "transparent" type. Figure 4b. BMU Logic Diagram any incoming port can be fed internally to the array through TFB1 and TFB2. The three ports can be time-multiplexed, if needed. Port routing is controlled by signals SELA, SELB and SELC (Figure 4b). Programmable Logic Unit (PLU) An on-chip 600-gate-equivalent EPLD supplies the control signals to the bus unit and related applica- 3-3 SCBIC so BI B2 B3 B4 BS B6 B7 BWU CONTROL BUS LOGIC (PORT B) lID AI A2 BUS A3 LOGIC M AS (PORT A) AS A7 BUS LOGIC (PORT C) co CI C2 C3 C4 C5 ce C7 290126-4 INMC = Input Macro Cell IOMC = Input/Output Macro Cell p·tenn .. Product Terms through the,logic array Figure S,' The sCalC Architecture 3'-4 intJ 100 SCBIC 101 102 103 10< 105 lOS 107 PLU p.. p.. p.. p- p- p- p.. T E T E T E T E T T E T E . R . R . R . R E . R R . .. IN8 1N7 R 290126-21 3-5 inter SCBIC EPROM CONTROL BIT II PROGRAMMABLE AND ARRAY \ PRODUCT TERMS ~ 4 ~ • .4 4~ .~ 4~ .~ 4~ .~ C~ ~,j C~ l~ ~ ~~ • INPUT AND F"EEDBACK BUSES 290126-6 Figure 6. The Array Structure be implemented by selecting the architecture bit MARB1 and the edge-triggered flip-flop (Figure 7). The Macrocells support D, T, S-R or J-K type registers for optimal deSign. Truth tables for these are listed in Figure 8 for easy reference. Whereas all eight of the product terms are OR-ed together at the register input for the D- and the T- registers, the J-K and the S-R configurations employ sharing of the product terms among two OR-gates. tion functions in the system. A dedicated input port and a bidirectionalI/O port, each 8 bits wide, allows control logic implementation in the SCBIC. The macrocell based architecture enables the designer to use up to 24 inputs and 8 outputs. The inputs, array and I/O marcrocells generate a sum-of-products (AND-OR) representation of any given logic. Within the AND array, there is an EPROM connection at every intersection of an incoming signal (true and complement) and a product term to a given macrocell (Figure 6). Before programming an erased device an EPROM connection exists at every intersection. It is during the programming process that these connections are opened to generate the required connections. The registers receive inputs at its data, clock, set and reset lines. Eight product terms are available for the data input and one each for the set and the clear inputs. The clock, output enable and the latching Signals can be selected by architecture bits MARB2, 6 and 3 respectively to be outputs from the control bus or one product term from the array. Designers thus have more options available for asynchronous clocking and output controls. The bidirectional I/O port, when configured as an input, is identical to the input port in that inputs may be latched by a signal from the control bus as shown in Figure 7. An additional flow-through option for the data inputs is available in the input macrocell. The macrocell output can be fed back to the array through the feedback bus or to the control bus. Figure 9 summarizes the bus structure and its relationship to the relevant units in the SCBIC. The variable output architecture in the PLU allows the designer to select the combinatorial or registered output types on a macrocell basis. This may 3-6 5CBIC LATCH ' INPUT PIN >+-+<=>1/0 PIN TO ALL 1/0 IIACROCELLS 290126-7 Figure 7. The Programmable logic Unit Input and Input/Output Logic Macrocell ~ ID LATCH INPUT PIN S ~ 8 III III i ...:> ...a; :> ID "" ~ >+-6-<:::>1/0 PIN m TO ALL I/O IIACROCELLS 290126-8 Figure 88. Combinational 3·7 inter SCBIC Input and Input/Output Logic Macrocell INPUT PIN ~ i ~ CD ~ I/O PIN ~ TO ALL I/O MACROCELLS 290126-9 Function Table On On OnH 0 0 1 1 0 1 0 1 0 0 1 1 Figure ab. D-Type Flip-Flop Input and Input/Output Logic Macrocell LATCH INPUT PIN I/O PIN TO ALL I/O MACROCELLS 290126-10 Function Table T o o 1 1 Onn o o 1 1 1 o 1 o Figure 8c. Toggle Flip-Flop 3-8 SCBIC Input and Input/Output logic Macrocell INPUT PIN >I-Ol/OP.. 290128-11 J 0 0 0 0 1 1 1 1 Function Table K 0" 0" + 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Figure 8d. J-K Flip-Flop Input and Input/Output logic Macrocell INPUT PIt H~>+-Ol/O PI" 290128-12 function Table s o o o o 1 1 R On 0,,+1 o o o 1 o 0 1 1 o o 1 0 1 0 1 o 1 1 Illegal Figure 8e. 5-R Flip-Flop 3·9 SCBIC INPUT rROIol: rEEDBACK: rROIol~ 16 -+ INPUT:[} IoIACROCELLS BMU· . TO ARRAY I/O . rROIol I/O 8 MACROCELLS IoIACROCELLS INPUT BUS TO ARRAY . rEEDBACK BUS r---......-1J'--"- ~~:T~~LS n'-~-.I TO I/o . IoIACROCELLS CONTROL ~~~~~~LL CONTROL ....._...r---r"""?' CONTROL BUS 290126-13 Figure 9. The SCBIC Bus Organization Configuring the SCBIC OeA SelA LeA OeB SelB LeB OeC SelC Lec The Device Configuration Manager (DCM) in iPLS II provides a high-level graphic design entry alternative that allows bus configurations to be imple· mented in minutes. A more detailed explanation is given in the iPLS II manual. An ADF (Advanced Design File) is then automatically generated that defines the logic network using primitives. The primitive necessary for configuring inter-port communication is the "BMU", while the one required for internal feedback from the BMU to the PLU is the feedback primitive "BFMUX". Tables 1 through 4 define these primitives and their fields/bits. Table 1. BMU Architecture Bits Architecture Bit Selects MUXA,MUXB Latched or Flow-Through Port Data INVA, INVB, INVC True or Inverted Data Output Table 2. BMU Primitive 8 bit I/O Ports PA PB PC BMU BMU (Bus Management (Unit) Name: . ADF Syntax: PortA, PortB, PortC = BMU (Type, OeA, SeIA, LeA, OeB, SeIB, LeB, OeC, SeIC, LeC) Description: . Port A = connection to 8 para"el I/O pins labeled AO-A7 Port B = connection to 8 para"el I/O pins labeled BO-B7 Port C = connection to 8 para"el I/O pins labeled CO-C7 OeA = output enable for Port A SeIA= select B or C internal connection to Port A (0 = C, 1 = B) LeA = input latch enable for Port A OeB = output enable for Port B SeIB= select A or C internal connection to Port B (0 = C, 1 = A) LeB = input latch enable for Port B OeC= output enabl.EI for Port C SeIC= select A or B internal connection to Port C (0 = A, 1 = B) LeC = input latch enable for Port C 3-10 5CBIC Inversion Control Input Latch Port: A B C A B C Bit: 5 4 3 2 1 0 '0 Invert Output Invert Output Invert Output Latched A Latched B LatchedC No Invert No Invert No Invert Direct A Direct B LatchedC· 1 'If LaC IS continually high. \he C latch Is transparent Table 4. PLU Architecture Bits Table 3. Bus Feedback Multlpler Primitive BFMX i~~~ ,-I_~__~__~. . JI C B Fbk Architecture Bit [0:7] MARBO MARB1 MARB2 MARB3 MARB4 A Name: BFMX (Bus Feedback Multiplexer ADF Syntax: Fbk[0:7] = BFMX (TFB1, TFB2) Description: Outputs. Fbk = 8 parallel lines of feedback to logic array. Inputs: TFB1, TFB2 = By appling 0 or 1 as shown on the chart above, select feedback from Port A, B, or C. TFB1 and TFB2 can be set to vee or GND, or they can be connected to any internal feedback or input node. The ports are defined in the BMU primitive section. MARB5 MARB6 3-11 Selects Output Polarity Combinatorial Of Registered Outputs Clock Source Latching Signal Source Combinatorial or Registered Feedback to the Logic Array Input Source to the Control' Bus tri-state Control Signal intJ 5CBIC ABSOLUTE MAXIMUM RATINGS· Symbol Parameter Min Max Units Vee Supply Voltage(1) -2.0 7.0 V Vpp Programming Supply Voltage(1) -2.0 13.5 V V, DC Input Voltage(1)(2) -0.5 Vee + 0.5 tata Storage Temperature -65 +150 ·C 8mb Ambient Temperature(3) -10 +85 ·C V • Notice: Stresses apove those listed under '~bso lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the oPerationsl sections of this specification is not implied. Ex-, posure to absolute maximum rating conditions for eXtended periods may affect device reliability. NOTICE' Specifications contained within the foJ/owing tables are subject to change. NOTES: 1. VOltages with respect to ground. 2. Minimum DC Input is -0.5V. During transltlpns, the inputs mayundershoot.to - 2.0V for periods less than 20 ns under no load conditions. 3. Under bias. Extended temperature versions are also available. D.C. CHARACTERISTICS Parameter TA = O·Cto +70·C, Vee = 5.0V ±5%· Description Min VOH Output High Voltage 2.4 VOL Output Low Voltage V,H Input High Level V,L Input Low Level I, Input Leakage Current loz Output Leakage Current IOS(4) Output Short Circuit Current Ise(5) lee2 Max Unit Test Conditions V TIL:IOH 0.45 V 10L 2.0 Vee +0.3 V -0.3 0.8 V 10 p,A 10 p,A 80 16 mA mA Operating Current (standby, low power mode) 75 p,A Operating Current (active, low power mode) 20 mA lees Operating Current (active, turbo mode) 108 mA C'N Input Pin Capacitance 30 pF COUT Output Pin Capacitance 40 pF SMU PLU PortA Port S, C I, I/O -1 mA ':"'5mA -1 mA Vee = Min PortA. Port S, C I, I/O 16mA ·5mA 5mA Vee = Min = Max Vss :;; VOUT :;; Vee, Vee = Max Vee = Max, VOUT = 0.5 Vss :;; Y,N < Vee, Vee Y,N Y,N f = Vee or Gnd, 10 = 0 = Vee or Gnd, = 1 MHz, No Load Y,N = Vee or Gnd, f = 1 MHz, No Load NOTES: 4. Output shorted for no more than 1 sec. and only one output shorted at a time. . 5. ehlp automatically goes into standby mode if logiC transitions do not occur at input pins. (Approximately 100 ns after last tranSition). 3-12 5CBIC ?~ OUTPUT I:> :tn..--o 1.93V PO~~~ I:> PORT S,c :t 325A 'IN'r-O '1..~50PF '1..1. 50PF 290126-14 NOTES: 1. CL includes jig capacitance 2. Device Input rise and fall times 2.075V ' 290126-15 < 6 ns FIgure 10A. A.C. Testing Load Circuit OUTPUT 1~-TESTPOIN1S-E 299126-16 A.C. Testing: Inputs are driven at 3.0V for a Logic "1" and OV for a Logic ''0''. Timing maasurements are mada a1 2.0V for a logic "1" and O.8V for a logic ''0'' on inputs. Outputs are maasurad at a 1.5V PQ;nt. Figure 10B. A.C. Testing Input, Output Waveform Switching Characteristics SUttIx Referenced to Control From: 1 2 3 direct input pin product term contrOl bus TIming Notation: PORT INPU1S V4UD I-~USU1_ I-~LlH01_ TUSU3 LATCH ENABU --J TUH03 I---T~H OUTPUT EN4SLE PORT OUTPU1S ,I - '\ TsusPO rpxz~t= TPXZ3 I'I-- Tpzx, TpZX3 _ .TLEP01 _ _ _ o TLEP03 290126-17 ' A) Latched Port Inputs PORT ------"'1,,.----. . . ,--------_ INPU1S _______I'I,_ _VAL_ID___________ OUTPUT-------~---'I EN4BLE TSUSPO OUTPU1S PORT:::::::::::::::::::)K::::~--~t::::::::::: 290128-22 B) Direct Port Inputs FIgure 10C. Bus Management Unit 3-13 SCBIC Switching Characteristics (Continued) INPUTS OR I/O INPUTS VALID _ TLlSU2 __ TLISU3 4- :LIHOL. TLlH03 LATCH ENABLE If _:CISU2 TCISU3 TCLEH- CLOCK , OUTPUT ENABLE ~TpXZ2_ I + - - TcPD - - COMBINATORIAL OUTPUT TpXZ3 ---., TpZX2 ' TpZX3 I-: RPD2 -oo TRPD3 ~ REGISTERED OUTPUT ~ 290126-18 A) Latched Inputs INPUTS OR - - - - - - ' ' ' \ , , -.....- - - - " " ' \ . , _ - - - - - - - - - - - VALID I/O INPUTS OR REGISTERED rEEDBACK - - - - - - - - - - - - - - - - - - - - - - - - - - - - TCISU2 TIH02 TCISU3+--+fo--TIH03 CLOCK -------jr--~----T~H---~-OUTPUT ENABLE PXZ2_ TpXZ3 r--TCPD- PZX2_ TpZX3 > COMBINATORIAL OUTPUT TRPD~.L-T RPD3 REGISTERED OUTPUT , , TSpW SET,RESET INPUT TSPD R .-...- - - - - - - - - - - - - - ASYNCHRONOUSLY - _ _ _ _ _ _ _ _ _T_,_PD_3,. SET,RESET OUTPUT - - - - - - - - - -.....- 290126-19 B) Direct Inputs Figure 10D. Programmable Logic Unit 3-14 inter SCBIC AC CHARACTERISTICS BUS MANAGEMENT UNIT Symbol -25 Parameter Min Typ -45 -35 Max Min Typ Max Min Typ Units Max TLlSU1 Port Input Setup Time to Latch Enable (Fast Option) 0 0 0 ns TLISU3 Port Input Setup Time to Latch Enable (Control Bus) 0 0 0 ns TLlH01 Port Input Hold Time to Latch Enable (Fast Option) 25 35 45 ns TLlH03 Port Input Hold Time to Latch Enable (Control Bus) 75 85 95 ns TLEH Latch Enable High Time 25 TBUSPD Port to Port Propagation Delay TpXZ1 Valid Output to High Impedance (OE From Fast Option) TpXZ3 Valid Output to High Impedance (OE From Control Bus) TpZX1 High Impedance to Valid Output (OE From Fast Option) TpZX3 High Impedance to Valid Output (OE From Control Bus) TLEPD1 Latch Enable (From Fast Option) To Port Output Delay TLEPD3 Latch Enable (From Control Bus) To Port Output Delay 35 15 15 45 25 25 25 25 75 15 35 35 85 25 25 35 35 75 15 ns 35 35 85 25 25 35 75 35 85 45 45 ns 95 ns 45 ns 95 ns 40 ns 95 ns ns PROGRAMMABLE LOGIC UNITS Symbol -25 Parameter -35 -45 Units Min Typ Max Min Typ Max Min Typ Max TLISU2 Input Setup Time to Latch Enable (P-Term) 0 0 0 ns TLISU3 Input Setup Time to Latch Enable (Control Bus) 0 0 0 ns TLlH02 Input Hold Time to Latch Enable (P-Term) 50 30 70 50 80 60 ns TLlH03 Input Hold Time to Latch Enable (Control Bus) 70 50 80 60 90 70 ns TCISU2 Input Setup Time to Clock (P-Term) 0 0 5 TCISU3 Input Setup Time to Clock (Control Bus) TCLEH Clock to Latch Enable Hold Time TCPD Combinatorial Output Delay 40 3-15 65 0 0 0 0 ns 5 5 ns 50 75 ns 60 85 ns inter SCBIC PROGRAMMABLE LOGIC UNITS (Continued) Symbol "':35 -25 Parameter -45 Units Min Typ Max Min Typ Max Min Typ Max TRPD2 Registered Output from Clock (P-Term) 20 30 30 35 30 40 30 40 40 45 ns. 40 45 ns TRPD3 Registered Output from Clock (Control Bus) TIH02 Input Hold Time to Clock (P-Term) 50 30 70 50 80 60 ns TIH03 Input Hold Time to Clock (Control Bus) 70 50 80 60 90 70 ns TCWH Minimum Clock Width High 33 38 43 TCWL Minimum Clock Width Low 33 38 43 TSPD Set Output Delay 65 75 TRPD Reset Output Delay 65 75 Tspw SETIRESET Pulse Width TpXZ2 Valid Output to High-Impedance (OE from P-Term) 65 75 85 ns TpXZ3 Valid Output to High Impedance (OE from Control Bus) 75 85 95 ns TpZX2 High Impedance to Valid Output (OE from P-Term) 65 75 85 ns TpZX3 High Impedance to Valid Output (OE from Control Bus) 75 85 95 ns TCP1 Minimum Clock Period (Register Output to Register Input Through Feedback Path) 50 70 80 ns F1 Maximum Internal Frequency TCP2 Minimum Clock Period Between Logic Transitions (Inputs to Outputs) F2 Maximum External Frequency 33 14.3 50 12.5 20.0 80 ns 85 ns 85 ns 43 38 20.0 ns ns 12.5 80 110 9.09 12.5 MHz 100 120 8.0 10.0 ns MHz ing, the devices are erased before shipment to customers. No post-programming tests of the EPROM array are required. inteligent Programming Algorithm™ The 5CBIC supports the infeligent Programming Algorithm which rapidly programs Intel H-ELPDs (and EPROMs) using an efficient and reliable method. The inteligent Programming Algorithm is particularly suited to the production programming environment. This method greatly decreases the overall programming time while programming reliability is ensured as the incremental program margin of each bit is continually monitored to determine when the bit has been successfully programmed. The testability and reliability of EPROM-based programmable logic devices is an important feature over similar devices based on fuse technology. Fuse-based programmable logic devices require a user to perform post-programming tests to insure proper programming. . DESIGN SECURITY . A single EPROM bit provides a programmable design security feature that controls the access to the data programmed into the device. If this bit is. set, a proprietary design within tbe device cannot be copied. This EPROM security bit enables a higher degree of design security than fused-based devices since programmed datawiJhin EPROM cells is invisi- FUNCTIONAL TESTING Since the logical operation of the 5CBIC is controlled by EPROM elements, the device is completely testable. Each programmable EPROM bit controlling the internal logic is tested using application-independent test program patterns. After test3-16 SCBIC mer-Personal Computer to enable the user to program EPLDs, read and verity programmed devices and also to graphically edit programming tiles. The software generates industry standard JEDEC object code output files which can be downloaded to other programmers as well. ' ble even to microscopic evaluation. The EPROM security bit, along with all the other EPROM control bits, will be reset by erasing the device. TURBO-BIT The device will consume quiescent current (75 p.A, typically) if no transitions are detected in the array for 50 ns or more. This mode, the power-down mode, can be enabled by selecting the Turbo Bit OFF. If this bit is enabled, however, the device consumes active current. The power-down mode will revert to its active state if a transition is detected in the array, at an extra delay of 3 ns in speed paths. The iPLDS II has interfaces to popular schematic capture packages (including Dash series trom Futurenet* and PC CAPS from PCAO* *) to enable designs to be. entered using schematics. A more integrated schematic entry method is provided by SCHEMA II-PLD, a low-cost schematic capture package that supports EPLD primitives and user-defined macro symbols. SCHEMA II-PLD contains the EPLD Design Manager, which provides a single user interface to both SCHEMA II-PLD and iPLS II software. The either design formats supported are Boolean equation entry and State Machine design entry. LATCH-UP IMMUNITY All pins of the 5CBIC have been designed to resist latch-up which is inherent in inferior CMOS structures. The 5CBIC designed with Intel's proprietary CHMOS II-E EPROM process. Thus, pins will not experience latch-up with currents up to 100 mA and voltages ranging from -1V to Vee + 1V. Furthermore, the programming pin is designed to resist latch-up to the 13.5V maximum device limit. The iPLDS II operates on the IBMt PC.XT, PC/AT, or other compatible machine with the following configuration: 1. At least one floppy disk drive and hard disk drive. 2. MS-DOStt Operation System Version 3.0 or greater. 3. 512K Memory. INTEL PROGRAMMABLE LOGIC DEVELOPMENT SYSTEM (iPLDS II) 4. Intel iUP-PC Computer Universal Programmer-Personal The iPLDS II graphically shown in Figure 11 provides all the tools needed to design with Intel H-Series EPLDs or compatible devices. In addition to providing development assistance, iPLDS II insulates the user from having to know all the intricate details of EPLD architecture (the machine will optimize a design to benefit from architectual features). It contains comprehensive third generation software that supports four different design entry methods, minimizes logic, does automatic pin assignments and produces the best design fit for the selected EPLD. It is user friendly with guided menus, on-line Help messages and soft key inputs. 6. A color monitor is suggested. 5. A. GUPI LOGIC Adaptor Detailed information on the Intel Programmable Logic Developement System is contained in a separate Intel data sheet. *FutureNet is a registered trademark of FutureNet Corporation. DASH is a trademark of FutureNet Corporatipn. ··PC-CAPS is a trademark ot P-CAD Corporation. tlBM Personal Computer is a registered trademark of International Business Machines Corporation. ttMS-DOS is a registered trademark of Microsoft Corporation. In addition, the iPLDS II contains programmer hardware in the form otan iUP-PC Universal Program- 3-17 inter SCBIC Figure 11.IPLDS II Intel Programmable Logic Development System 3-18 APPLICATION NOTE AP-305 October 1987 Dual-Port Memory Control Using The 5CBle NAGEEN SHARMA PROGRAMMABLE LOGIC APPLICATIONS INTEL CORPORATION Order Number: 292032-002 3-19 AP-305 INTRODUCTION One of the popular multi-port configurations commonly used in multiple microprocessor systems is the dual port. Because each processor is now capable of handling separate tasks in parallel, such designs offer improved performance and throughput. Sharing resources, such as large amounts of memory, is an optimizing trade-off to keep the system efficient and, at the same time, cost-effective. parallel-load capability. The lead configurations of the devices are given in Figures 2 and 3. A bus-arbitration flow-diagram and the state machine diagram for the arbiter are shown in Figures 4 and 5, respectively. These diagrams are translated into equations, which are shown in Figures 6 and 7. DESCRIPTION The scheme discussed here consists of two processors sharing memory through some intermediate logic. Typically, such logic consists of data transceivers, address latches, SSIIMSI arbitration logic (AND gates, OR gates, FLIP-FLOPS etc.). With the SCBIC implementation, it is possible to reduce the overall chip count by over three times. The block diagram (Figure 1) shows two processors, Processor 1 and Processor 2, in a minimal memory system. The interface logic can be condensed to two SCBIC's. These devices provide the necessary isolation of the shared memory data bus (MDATA [0 .. 151) from each of the processors' data bus (PIDATA [0 .. 15] and P2DATA [0 .. 151). A block diagram of the dual-port scheme is shown in Figure 1 for two sixteen-bit processors accessing shared memory. Two SCBIC's are required for the implementation as all ports in the chip are byte-wide. The first device provides the isolation of the memory and processors' high-byte data bus; it also includes the necessary arbitration logic. The second SCBIC interfaces the lowbyte data bus and implements a 7-bit counter with a Similar isolation is required for the address bus. This is implemented by a set of latches. It is interesting to note that these latches can also be easily configured in an extra SCBIC. An implementation of latches can be found in another application note that serves as a multiplexed address/data interface. COUNTER OUTPUTS , CONTROLS PROCESSOR 1 PROCESSOR 2 LATCH ......._~ 292032-1 Figure 1. The Dual·Port Block Diagram 3·20 AP-305 The control bus provides all the necessary signals that are used to initiate requests (P1MRD, P1MWR, P2MWR), or simply to provide handshaking signals in· dicating cycle termination etc. After the data transfer has occurred, an acknowledge signal signifies cycle completion. The state machine diagram of the arbitration algorithm is shown in Figure S. Upon receiving a request from Processor 1, the arbiter will move from it's IDLE state to GRANT 1 state and cycle back only after completing the memory access. If Processor 2 requests for a memory access while the arbiter is in the IDLE state, transition to GRANT2 state will occur only if Processor 1 is not requesting access. Different arbitration algorithms are possible; these would translate into different state-machines. The arbitration scheme is shown in Figure 4 with the help of a flow-chart. In this example, Processor 1 has been assigned higher priority than Processor 2 to prevent contention. IT Processor 2 requests an access while Processor 1 has control of the system bus, the Processor 2 bus cycle is extended by inserting wait states. The cycle remains extended until the arbiter grants access to Processor 2 and enables the appropriate port (PORT B) of the Bus Management Unit (BMU) in the SCBIC. High Byte Data Transfer and Arbitration Logic Low Byte Data Transfer and Seven-Bit Counter P2MRO Vee HBYTLB(7) ENABLE LBYTE_B(7) HBYTE_A(7) LOAD LBYTE_A(7) HBYTE_A(6) OS.T LBYTE_A(6) HBYTE_A(S) OU LBYTE_A(S) HBYTE_A(4) OE_PC LBYTE_A(4) Vee Vee ClK1 HBYTE_A(3) Vee CLK1 LBYTE_A(3) OLPA HBYTE_A(2) 03.T LBYTE_A(2) MEM_WR HBYTE_A(1) OU LBYTE_A(1) PIMWR HBYTE_A(O) OLPB LBYTE_A(O) PIMRD HBYTE_B(6) OLPA LBYTE_B(6) 292032-3 292032-2 Figure 3. Lead Configuration Figure 2. Lead Configuration 3-21 AP·305 HIGHER PRIORT¥ (PROCESSOR 1) IDLE STATE I ---------- LOWER PRIORTY (PROCESSOR 2) PROCESSOR 1 REQUiRES PROCESSOR 2 REQUIRES MEMORY ACCESS ------~~ ARBITRATE .. 4f----MEMORY ACCESS (DRIVE PI REQ ACTIVE) (DRIVE P2REQ ACTIVE) ENABLE PROCESSOR 1 MEMORY ACCESS LOGIC (DISABLE PROCESSOR 2 MEMORY ACCESS LOGIC) !' DATA TRANSFER IN PROGRESS DATA TRANSFER COMPLETE END OF CYCLE I--------.. .. ~ PROCESSOR 1 DOES NOT REQUIRE MEMORY ACCESS IDLE STATE ~ !~----- PROCESSOR 2 REQUEST PENDING ARBITRATE I ENABLE PROCESSOR 2 MEMORY ACCESS LOGIC .....- -.... ~ (DISABLE PROCESSOR 1 MEMORY ACCESS LOGIC) ! DATA TRANSFER IN PROGRESS DATA TRANSFER COMPLETE ~ ..- - - - - - - - - END OF CYCLE IDLE STATE ! (CONTINUE) + Figure 4. Bus Arbitration Flow Diagram 3-22 292032-9 Ap·305 ~tate. IDLE GRANT1 GRANT2 ILLEGAL State Varlabl •• P1GNT 0 1 0 1 P2GNT 0 0 1 1 It should be pointed out that since Processor 2 could be running on a different clock than Processor I, it may be necessary to synchronize the requests using the system clock (say Processsor 1). This is conveniently done using buried master/slave flip-flops to prevent erroneous requests or noise from triggering the arbiter states. The outputs from the arbiter 8 ~u1ii ~ ~ >1:l~:;!~1II~ ~'~ PB7 PA7 PAS DOUT4 PAS SO PA4 Vee Vee PAl PA2 OE....C DOUT3 DOUT2 PAl DT/R* PAO ALE PBS ~Sd~ri:JI!1&l~~~ 88 ,~, .., ...... PA [0 .. 71 = Port A (Address/Data) PB [0 .. 71 = Port B (Data) PC [0 .. 71 = Port C (Address) 292035-3 Figure 3. SCBIC Lead Configuration (Low Byte Demultlplexlng and Barrel-Shifter) inter AP-308 G B B B This implementation illustrates not only a path of higher integration in this very common design, but also the benefits that can be realized if the system is viewed as a collection of smaller functions. These can then be paired together to best exploit the full capability of the 5CBIC. 00000 H 9FFFFH CAOOOH The amount of shift in data output is determined by the select lines SO, SI and S2. This can be used for formatting data needed in other sections in a system. FDFFFH State Variables 1000 H 1FFFH 2000H 2FFFH Figure 4. Address Map The READY signal is used to increase cycle time for devices that cannot transfer data at maximum processor bus bandwidth. 02 01 00 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Device "Wait States 7 6 5 IODEV2 4 3 2 1 0 IODEV1 EPROM ENABLE READY Figure Sa. State Table for the Walt-State Generator ONE COt.lPLETE PROCESSOR CYCLE (WITH ONE WAIT- STATE) t.lEt.lORY. I/O CYCLE READY 292035-4 Figure 5b. Waveforms Showing Wait State Insertion in Processor Cycle 3-29 AP-308 S2 S1 SO DOUT_7 DOUT_6 DOUT_5 DOUT_4 DOUT_3 DOUT...2 DOUT_1 DOUT_O 0 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 1 0 1 .0 1 1 DIN_7 DIN_S DIN_5 DIN_4 DIN_3 DINJ DIN_1 DIN_O DIN_S DIN_5 DIN_4 DIN_3 DINJ DIN_1 DIN_O DIN_7 DIN_S DIN~5 DIN_4 DIN_3 DINJ DIN_1 DIN_O DIN_7 DIN_4 DIN_3 .DINJ DIN_1 DIN_O DIN_7 .DIN-,S DIN_5 DIN_3 DINJ DIN_1 DIN_O DIN_7 DIN_S DIN_5 DIN_4 DINJ DIN_1 DIN_O DIN_7 DIN_S DIN_5 DIN_4 DIN_3 DIN......:1 DIN_O DIN_7 DIN_S DIN_5 DIN_4, DIN_3 DINJ DIN_O DIN_7 DIN_S DIN_5 DIN_4 DIN_3 DINJ DIN_1 FIgure 6. Truth-Table for the Barrel-8hlfter S2 SI 0 0 SO 0 DATA IN FROM BMU PORT A DATA IN FROM BMU PORTA 76543210 7 6 5 4.3 2 1 0 S2 SHIFT 0 SI SO 7 6 5 4 3 2 0 - SHIFT 3 432 1 0 765 1 0 FIgure 7. Block DIagram of Barrel Shifter 3-30 292035-5 intJ AP-308 N. SHARMA INTEL CORP. AUGUST 31, 1987 2 A SCBIC MUL.ADF -- DEMULTIPLEXER, DECODER, WAIT-STATE GENERATOR OPTIONS: TURBO-OFF PART: SCBIC INPUTS: CLK ALE A19 A18 A17 IORC OUTPUTS: PA_ADDT PB_DT PC_AD RAMSEL IOWC MRDC MWTC EPROMSEL IODEVl DT/R* IODEV2 OE_C READY NETWORK: CLK - INP (CLK) A19 - LINP (A19) A18 - LINP (A18) A17 - LINP (A17) ALE - INP (ALE) IORC - INP (IORC) lOwe - INP (IOWC) MRDC - INP (MRDC) MIITC - INP (MWTC) DTR - INP (DT/R*) PA ADDT,PB DT,PC AD - BMU (OblllOll,OE_A,VCC,ALE,OE_B,GND,VCC,OE_C,GND,VCC) LATo:?) - BFMX (VCC,GND) % LATCHED ADDRESSES 8 •• 15 FED BACK INTO % % THE PLU FOR 1/0 DECODING % OE_C,OE_C - COCF(OEC,VCC) % OUTPUT CONTROL FOR PORT C , % RAM SELECT % RAMSEL - CONF (RAMSL,VCC) EPROMSEL,EPROMSEL - COCF (EPROMSL,VCC) IODEV1,IODEVl - COCF (IODV1,VCC) IODEV2,IODEV2 - COCF (IODV2,VCC) READY - CONF (ROY,ROYOE) 00 - NORF (OOD,CLK,GND,GND) 01 - NORF (OlD,CLK,GND,GND) 02 - NORF (02D,CLK,GND,GND) , EPROM SELECT , 1/0 DEVICE 1 SELECT , 1/0 DEVICE 2 SELECT , READY FOR CYCLE COMPLETION % STATES 00 .• 02 FOR WAIT-STATE' , GENERATION ( USING BURIED % , REGISTERS) , 292035-6 EOUATIONS: % DECODE EOUATIONS RAMSL EPROMSL IODVl IODV2 - IA18 * /Al? * MREO ; - A19 * Ala * LA[?) * MREO ; ILA[?) * ILA(6) • ILA[S) * LA(4) ILA(7) * ILA(6) * LA[S) * ILA(4) MREO - (MRDC + MWTC) ; IOREO - (IORC + lOwe); OE A - DTR OE-B - IDTR ; OEC - MRDC + MIITC + IORC + IOWC ; , , OOOOOH - 9FFFFH , , CAOOOH - FDFFFH , IOREO ; '1000H - 1FFFH IOREO ; '2000H - 2FFFH % % , INTERMEDIATE EOUATIONS FOR MEMORY , AND I/O REOUESTS , THE FOLLOWING IS A WAIT-STATE GENERATOR FOR MEMORY AND 1/0 REOUESTS , OOD - 100 * /ALE + EPROMSEL * ALE * /00 * IALE + IODEVl • ALE OlD - 01 + /01 * 100 * IALE + IODEV2 * ALE ; 02D - 02 * 101 * 100 * /ALE + /02 * 101 * 100 * IALE + IODEV2 * ALE ROY - GND ; ROYOE - /00 * 101 * 102 END$ 292035-7 Figure 8. ADF Listing for Demultlplexlng Higher Address/Data Byte, Decoder, Walt-State Generator 3-31 inter AP·308 N. SHARMA INTEL CORP. AUGUST 31, 1987 2 A SCBIC MULH.ADF -- DEMULTIPLEXER, BARREL SHIFTER OPTIONS: TURBO-OFF PART: SCBIC INPUTS: CLK ALE DT/R* OE C SO 51 S2 ENABLE OUTPUTS: PA ADDTL PB DTL PC ADL DOUTO DOUTl DOUT2 DOUT3 DOUT6 DOUT7 % PA ADDTL - ADDRESS/DATA BUS ON PORT A (LOW BYTE) % PB-DTL ~ SYSTEM DATA BUS ON PORT B (LOW BYTE ) % PC-ADL = SYSTEM ADDRESS BUS ON PORT C (LOW BYTE) % DOUTO •• 7 = SHIFTED DATA OUTPUT ON 1/0 PORT DOUT4 DOUTS NETWORK: CLK • INP (CLK) ALE - INP (ALE) DTR - INP (DT/R*) OE C - INP (OE C) 50-· INP (SO) 51 - INP (51) 52 - INP (52) ENABLE - INP (ENABLE) PA_ADDTL,PB_DTL, PC_ADL • BMU (Oblll011, OE_A, vce, ALE, OE_B, GND, VCC,OE_C, GND, veC) , D_IN[0:7] • BFMUX (VCC,GND) DOUTO DOUT1 DOUT2 DOUT3 DOUT4 DOUTS DOUT6 DOUT7 - = = - = = , DATA LOADED INTO , THE PLU FOR SHIFTING , FROM PORT A RONF (DOO,CLK,GND,GND,ENABLE) % DATA OUTPUT RONF (DOl, CLK, GND, GND, ENABLE) RONF (D02, CLK, GND, GND, ENABLE) RONF (D03,CLK,GND,GND,ENABLE) RONF (D04,CLK,GND,GND,ENABLE) RONF (DOS, CLK, GND, GND, ENABLE) RONF (D06, CLK, GND, GND, ENABLE) RONF (D07, CLK, GND, GND, ENABLE) , , , % 292035-8 EQUATIONS: % CONTROL INPUTS TO THE BMU % OEA-DTR; OE-B - IDTR ; % OE_C IS AN INPUT FROM THE HIGHER BYTE DEMULTIPLEXING SCBIC , THE FOLLOWING IMPLEMENTS A BARREL SHIFTER , SHIFTO - 152 * 151 * ISO; 'INTERMEDIATE SHIFT EQUATIONS % SHIFTl - 182 • ISl • SO ; SHIFT2 - 152 • 51 • ISO ; SHIFT3 - 152 • 51 • SO ; SHIFT4 - 52 • IS1 • ISO ; SHIFTS - 52 • 151 • SO ; SHIFT6 - S2 • 51 • ISO ; SHIFT7 - S2 • 51 • SO ; DOO - SHIFTO • D IN[O] + SHIFT1 • i5 IN[7] + SHIFT2 • D-IN[6] + SHIFT3 • D-IN[S] + SHIFT4 • D-IN[4] + SHIFTS' D-IN[3] + SHIFT6 • D-IN [2] + SHIFT7 * D:IN[l] DOl - SHIFTO * D IN[l] + SHIFT1 • i5 IN[O] + SHIFT2 • D-IN[7] + SHIFT3 * D-IN[6] + SHIFT4 • D-IN[S] + SHIFTS' D-IN[4] + SHIFT6 • D-IN [3] + SHIFT7 • D:IN[2] D02 = SHIFTO * D IN[2] + SHIFT1 * i5 IN[l] + SHIFT2 * D-IN[O] + SHIFT3 • D-IN[7] + SHIFT4 * D-IN[6] + SHIFTS' D-IN[S] , + SHIFT6 • D-IN[4] + SHIFT7 • D:IN[3] 292035-9 Figure 9. ADF Listing for Demultiplexing Lower Address/Data Byte and Barrel-Shifter 3-32 AP-308 003 - SHIFTO * 0 IN(3) + SHIFTl * D IN(2) + SHIFT2 * O-IN[l) + SHIFT3 * O-IN[O) + SHIFT4 * 0-IN(7) + SHIFTS * 0-IN(6) + SHIFT6 * O-IN[S) + SHIFT7 * 0:IN[4) 004 - SHIFTO * 0 IN(4) + SHIFTl * 0 IN(3) + SHIFT2 * 0-IN(2) + SHIFT3 * O-IN[l) + SHIFT4 * O-IN[O) + SHIFTS * 0-IN(7) + SHIFT6 * 0-IN(6) + SHIFT7 * O:IN[S) DOS - SHIFTO * 0 IN[S) + SHIFTl * 0 IN[4] + SHIFT2 * 0-IN[3] + SHIFT3 * 0-IN(2) + SHIFT4 • O-IN[l) + SHIFTS * O-IN[O] + SHIFT6 * 0-IN[7) + SHIFT7 * 0:IN(6) D06 - SHIFTO * 0 IN[6] + SHIFTl * 0 IN[S) + SHIFT2 * 0-IN[4) + SHIFT3 * 0-IN[3] + SHIFT4 * 0-IN[2] + SHIFTS * O-IN[l) + SHIFT6 * O-IN[O] + SHIFT7 * 0:IN(7) 007 - SHIFTO * 0 IN(7) + SHIFTl * 0 IN[6] + SHIFT2 * O-IN[S) +'SHIFT3,* 0-IN[4] + SHIFT4 * 0-IN[3] + SHIFTS * 0-IN[2) + SHIFT6 * O-IN[l] + SHIFT7 * O:IN[O) END$ 292035-10 Figure 9. ADF Listing for Demultlplexlng Lower Add...../Data Byte and Barrel-Shlfter (Continued) 3·33 " APPLICATION NOTE '"' AP-309 ,, January 1987 DRAM Address Interface, with the 5CBIC NAGEEN SHARMA PROGRAMMAB'LE LOGIC APPLICATIONS Order Number: 292036-001 3·34 inter AP·309 INTRODUCTION DESCRIPTION In most DRAM applications, the row and the column addresses for data transfers must be multiplexed on a common bus. Refresh circuitry, however, provides the refresh address at fixed intervals. This note describes an implementation of both the multiplexing circuitry and the refresh address logic in a one-chip replacement of the two multiplexers and one counter needed in a conventional SSI/MSI design. The block diagram shown in Figure 1 is the address interface needed in dynamic RAM circuits. The portoriented 5CBIC provides a high integration alternative to discrete SSI/MSI devices such as multiplexers and counters. The row address bus is connected to Port A while the column address is connected to Port B of the Bus Management Unit (BMU). The multiplexed address bus is Port C, a high drive port, that is connected to the DRAM address inputs. The controlling signal for the multiplexing is provided by a memory controller (easily configurable in another EPLD). The block diagram of the DRAM address interface is shown in Figure 1. The lead configuration of the 5CBIC is shown in Figure 2. The equations for the design are provided in Figure 3 in the advanced design file (ADF). ROW ADDRESS" COLUMN II' ADDRESS" I MULTIPLEXED ADDRESS" MULTIPLEXERS J-£P '" :.. DRAM AD ••• A7 II' SELECT" MUX OE AD •••A7 CLK CNTR OE REFRESH ADDRESS COUNTER 292D36-1 a. Discrete SSI/MSI Approach (Minimum of Three Devices) ROW ADDRESS" 5CBIC PORT A COLUMN II' ADDRESS --" PORT C MULTIPLEXER PORT B J-£P II' AD •••A7 SELECT MUX OE CLK CNTR OE MULTIPLEXED ADDRESS " DRAM AD ••• A7 bJJ II' REFRESH ADDRESS COUNTER 292036-2 b. High Integration SCBIC Implementation (Single Device) Figure 1. Block Diagram of DRAM Address Interface 3·35 AP-309 AS.T PB7 PA7 PA6 A4.T PAS GND PA4 GtoID GND vee vee PA3 A2.T PA2 PAl SELECT PAD MULOE PB6 A3.T 292036-3 PA[O..7] = Port A (Row Address) PB[O..7] = Port B (Column Address) PC[O.. 7] = Port C (Multiplexed Address) Figure 2. Lead Configuration of the 5CBIC The BMU is configured by using the iPLDS II (Programmable Logic Development System). The Device Configuration Manager (DCM) in that software facilitates design entry using high-level graphics to configure the BMU. abies the buffer only while directly providing the refresh address. The equations of this counter are given in Figure 3. The counter holds the state of the last row address refreshed and increments it after receiving the appropriate control signal from the memory controller. The output-enable signals of the mUltiplexer and the counter are the qnly other control signals required for this cir- The refresh address counter provides the row refresh address to the dynamic RAM. An octal up-counter is adequate for most DRAM's (as a number of them require fewer than eight address lines for refresh). Since the outputs of the Programmable Logic Unit can be controlled by a tri-state buffer, the I/O port en- cuit. 3-36 intJ AP·309 I. SIIAIIIA lIft'lL CORP. o.c.ber 2, 1986 1 A IICIIC DUll "'ltipl.... ad Retre.h ~. _ _tor OPTIOIIB: TIJIIOoOfI' PART: IICIIC IIPU'l'S: CLI IIII_OB SII.ICT CII'l'II_OB II Caatrol I_ta II 0UTPII!8: . PA_IIOW PI_COL PC)IIWI AD.T Al.T AZ.T A3.T M.T AII.T AS.T A7.T II II1II ad _ t v output. II II PA..- = _ AllDllBSS INPUT AT I'0Il'1' A II II PI_COL = COUll! ADDBSS INPU'l' AT PORT I II II PC_IIJWI = MllJ.TIPLIDD ADDBSS 0I/TPU'l' I'IDI II II PORT C '1'0 DIWI II II AD. T .. A7. '1' = .I'I1II88 ADD.SS COlIII'I'BR OUTPOTS II NI'I'I«JIII: IlIIIPUTSII CLI = IRP(CLI) MIII_OB • INP(IIII_OB) CII'l'II_OB = IMP(CII'l'II_OB) ULICT = IMP (SILBCT) II II II II CLOCII IIIPIITlII IIILTIPLIUB 0U'l'PUT BllAlLI II COIIIITSII 0UTPU'1' BllAlLI II IIILTIPLIUB 0U'l'PUT SILICT II IIIU'l'PU'l'SII AD.T,AD = 'I'O'lT ( vee,CI.I,CIND,CIND,CII'l'II_OB ) Al.T,.ll = 'I'O'lT ( Al.T,CLI,CIND,CIND,CN'1'II_OB ) AZ. T,A! = 'I'O'lT ( AZ. T,CLS,CIND,CIND,CN'l'B_OB ) A3.T,A3 = 'I'0'I'l' ( A3.T,CLS,CIND,CIND,CII'l'II_OB ) M.T,A4 = 'I'0'I'l' ( A4.T,CLI,CIND,CIND,CN'1'II_OB ) AII.T,AII = 'I'O'lT ( AII.T,CLI,CIND,CIND,CIITR_OB ) AS.T,AS = 'I'O'lT ( AS.T,CI.I,CIND,CIND,CN'1'II_OB ) A7.T = 'I'ONI' ( A7.T,CLI,CIND,CIND,CII'l'II_OB ) II 001lIft'III STATIS II II POB'l'S III IMII II PA..IIOW,PB_COL,PC_DIWI = II1II (0b000111,CIND,CIND, vee, CIND,CIND, vee,OB_PC,UL_PC,CIND) 292036-4 Figure 3. ADF U8tlng of the Address Multiplexer and the Refresh Address Counter 3-37 inter IICIUATIONS , IIIUX_OII = /MUll_OJ ; OIl_PC • IIIUX_OII ; BlL_PC = BlLBCT ; AI. T = AO ; A2. T • Al • AO ; A3.T = A2 • Al A4.T = A3 * AO ; * A2 * Al • AO * A3 * A2 • Al * AO AS. T = AS * A4 * A3 * A2 * Al * AO A7.T = AS * AS * A4 * A3 * A2 * Al * AO IND. AS.T = A4 292036-5 3-38 inter AR-453 1~--------D-E-5IG-N-E-N-T-RY--------~1 ELECTRONIC DESIGN EXCLUSIVE \ Programmable logic shrinks bus-interface designs Nageen Sharma ntel CO!P., 1900 Prai1e City Rd., Folsom, CA 95630; (916) 351·2758. Most microprocessor- or microcontroller-based circuits need external logic to bridge address and data buses to the rest of the system, including memory and serial or parallel inputs and outputs. Designers usually rely on various TTL devices to perform this task. Such assortments of components significantly raise board space and power dissipation. As a result they often require cooling, reduce reliability, and add cost. Most interfaces, for example, contain bus drivers and transceivers; encoders, decoders and multiplexers; and assorted A CMOS LSI circuit latches, flip-flops, and oilers high-drive ports counters. Depending on lor data transler and the complexity of the programmable consystem, these devices make up 70% to 90% of trols lor bus Interthe total chip count and laces. It also cuts fill almost that percentpower dlss;pation. age of the board space. The advent of dedicated LSI interface chips has eased the congestion somewhat, but many designs still call for a number of SSI and MSI devices. The 5CBIC bus interface controller brings a fresh approach to the issue by integrating highdrive bus ports and control logic in one package. The chip contains a 600~g~te eq\livalent programmable logic array and tridirectional (three-way) bus transfer logic, housed in a 44-pin plastic leaded chip carrier. The packaging and, behind the scene, a proprietary CMOS II-E EPROM process cut board space by three or four times compared with discrete circuits. The CMOS process also enhances the basic attributes called for· in bus interface logic: speed and high drive current. The maximum data delay between ports is 25 to 35 ns; and the array can operate in TTL or CMOS systems at clock speeds to 12.5 MHz. The high-drive ports can sink 16 rnA from a 300-pF load. The EPROM technology also permits 100% device testing. Another benefit of the chips that TTL devices do not offer is an optional "zero-standby" power mode. If the chip's inputs are static for more than 50 to 100 ns, the device powers down from its normal operating current of about 108 rnA at I MHz to its quiescent current of several microamps. The controller's two major functional blocks are the bus management unit and the programmable logic unit. The two circuits com~unicate by way of internal signal paths that replace the external logic and traces of conventional interfaces. The device has five 8-bit ports (Fig. 1). Three ports on the bus-management unit make possible three-way asynchronous data flow, and thus are equivalent to three bidirectional chips. The two other ports are a dedicated input and an I/O port for the programmable logic unit. DATA ROUTED THROUGH THREE PORTS The bus-management unit's main task is to route . real-time or transparent-latched data, which can be inverted. The unit does this through the three ports, which can be programmed as inputs or outputs. A direction-control unit dynamically selects the desired port and routes the data accordingly. In addition, the bus unit can send latched data from any input port to .the programmable logic unit, whose architecture is similar to that of EPROMbased EPLDs. The primary difference is the addition of up to eight buried registers, asynchronous controls, and an, extra set of inputs from the three bus-management-unit ports. In all, inputs to the programmable logic unit include a dedicated port to the input logic macrocells, a bus unit feedback path, an I/O port, and feedback from I/O logic macrocells. A conventional sum-of-products array and a logic macrocell structure perform the logic unit's control functions. The user programs the input and I/O logic macrocells to supply either latched or real-time data. Polarity is also determined by the "Reprinted with permiSSion from Electronic Design (Vol. 35, No.3) February 5. 1987. Copyright 1987 Hayden Publishing Co., Inc.• a subsidiary of VNU." 3-39 DEMN iNTRv'. Programmable bus Interface user, pennitting the device to ~andle either active-high or~ Although the bus-interface controller has' several adactive-low outputs. . vantages'over Conventional TTL interfaces, designers Besides its flexible input structure, the logic array in evmight question the time needed to develop and program ery I/O macroceD offers '13 product terms, each equal to a complex LSI devices. That time, however, is cut to 64-input AND gate. Sequential and combinatorial logic minutes through use of the Programmable .Logic Develare possible, since the macrocells contain registers (Fig. opment System softwalel known in its ~nd revision as 2). Data can also feed back to the array. The user confIgiPLDS-II. The system includes several modules that minures the macrocell for a specific task by choosing among imize design and development time. The modules offer positive-edge-triggered D, T, SR, andJK flip-flops. . . , high-level Primitives that define the design and serve as For maximum control, an asynchronous clock can be logic building blocks. derived from one to eight product tenns. Each flip-flop To best apply the bus controller in a system, a designer also has an asynchronous set and reset. A programmable exploits its high level of integration. A sysiem with a dualOutput Enable signal selectively enables outputs to emuport memory shared by two processors offers a good exlate open-coDector operation. ample. Such designs are 'helpful when resources, such as Three buses carry the chip's internal communication large amounts of data in a memory, must be shared. and control signals. The input bus serves the input macroData flowillg between the memory and the two microcells, as well as the I/O macrocells confIgUred as inputs. processors needs buffering and arbitration to prevent con-, The feedback bus provides bus unit and I/O-macrocell tentiort. The usual solution is for data transceivers to is0feedback. Finally, the control bus steers the data through late the data from the shared memory and for a controller the various ports connCcting the bus management and to arbitrate the demands of the processors. programmable logic units. It alsd supplies complex conHowever, the bus-interface controller perfonns these trol signals for the bus functions, like Direction Control, functions with the minimum chip· count. The.programLatching" and Output Enable, as weD as Clock, Set, Remabie logic unit arbitrates data requests according to a set, Latching 'and Output Enable source signals for the predefined protocol that establishes priorities, and the bus logic unit. management unit's three ports isolate the data. Moreover, 1. With the 5C8IC bus Interface, control..... a bus management unit communicates with 0 programmable logic I.I'IIt IhIOUgh a aegmenIed bus 1frUCIu.... The feedback and corttrm bUIeI Hnk !he two units and the Input bus feedllhe array from the Input and 110 rnaclOC8lls. Electronic D••lgn· February 5. 1987 3-40 the control section supplies feedback paths, eliminating chips that would be needed in a conventional design. In the example, two cascaded controllers handle 16bit-wide data. Since the system needs only one logic array, the second is available for whatever the designer may need, including an up/down octa1 counter; memory, I/O, or interrupt controller; or an addressable 8-bit register. Ports A and B of the bus-management unit connect to the two processors, and Port C connects to the system memory (Fig. 3). If the processors run on different clocks, the controller must synchronize the access requests of one unit with those of the second. The programmable logic unit performs all sampling, synchronization, and arbitration, and the registers within it supply the control signals needed by the bus unit The I/O pins serve as inputs without sacrificing the sum-of-products logic that is important to effective gate use. The system's arbitration scheme is straightforward. Only one processor at a time may have access to the system bus, with processor 1 having the higher priority in the -event of a simultaneous request If the second processor requests an access while the rust has control of the bus, wait states extend the second unit's bus cycle. When the rust data transfer is completed, the programmable logic unit grants access to the second processor and enables the address latches and data transceivers. In a second example, the device functions as a demultiplexer for microprocessors, microcontrollers, and peripheral controllers with combined address and data buses. The time-multiplexed buses use package pins more efficiently, but the address and data signals must be separated before interfacing with memories or I/O devices. Once again, two bus controllers accommodate 16-bit data, this time from an 8096 microcontroller (Fig. 4). In a system containing only a RAM, an EPROM, and I/O devices, the two A ports of the bus management units connect to the 8096's Ports 3 and 4. Ports Band C connect directly to the system data and address buses. In this application, Ports A and B are bidirectional, and Port C is an output only. As a result, Port A is the only input to Ports B and C, and Port B is the only input to Port A (during a memory-read cycle). . The user programs the chip to latch the addresses with 2. The Input CI!'Id 110 logic mac:roc:eIlllncIude CIfChIIecIIn bill MARIo Ihroug" MARl6 and a choice of conIIOl IIgnalilhal permit nurnercu conflguratlont, aslalchlng. 1nvenIon, asynctvonous clocking..... r..... and output enable. IUC" Electronle Dellgn· February 5, 1987 3-41 DESIGN ENTRY • Programmable bus Interface 3. Two controller chips handle 16-blt-wlde data In a system with a dual-port memory. The chips Isolate data as well as supply signals for arbitration, synchronization, and extemol control. 4. The bus controller. serves as a demultiplexer and data and address signals for a microcontroller with a combined data and address bus. In this application, the device replaces two transceivers, two latches,. two decoders, and several lQ9tc ~lrcUlts. . '~parates the microcontroller's Address Latch Enable signal and route them to Port C. The data shows up at Port B later in the write cycle. The Latched Address 0 and Latched Bus High EnaQle signals select the upper- and lower-byte memory chips. Finally, the bus-management.unit feeds the upper latched addresses directly to the programmable logic unit, which generates the system chip selects. In this application, the bus controller replaces two transceivers, two latches, two decoders, and sc:verallogic circuits. In doing so, it offers the designer a second 600-gate array for additional logic. 0 Nageen Sharma is a technical marketing engineer in Intel's programmable logic group. He has a BSEE from the University ofDelhi, India al1d an MSEE from the University of Maryland. Electronic Design' February 5. 1987 3-42 Development Support Tools 4 inter iPLDS II THE INTEL PROGRAMMABLE LOGIC DEVELOPMENT SYSTEM VERSION II • Hardware and Software Necessary to Turn Design Concepts Into Functional Erasable Programmable Logic Devices (EPLDs) • Menu-driven Software with On-line Help Messages for All Stages of the Design Process • IUP-PC Hardware Programs Intel E~LD's, EPROM's, E2PROM's, Peripherals, and Microcontrollers with one PC-based System • All Equipment Interfaces with the IBM PC/XT*, PCI AT*., and True Compatibles • JEDEC Standard Design File, Part Utilization Report, Minimized Equation File, and Complier Error File All Available as Outputs • Supports a Variety of Input Methods: Schematic Entry - TTL Library - EPLD Primitives Library Text Editor Entry - State Machine - Boolean Equations • Macro Expander Accepts TTL, and User-Defined Macros and Expands Them Into Equivalent EPLD Primitives • Espresso" Minimizer Reduces Logic Equations to Least Number of Product Terms • Supports All Intel EPLD's Including the SCBIC and SAC312 Release 1.5 of Intel's Programmable Logic Development System II (iPLDS II) is a powerful set of tools for transforming a logic design into customized silicon. The system provides design entry, logiC compilation, and device programming capability on a desktop using an IBM PC/XT, PC/AT, or compatible. 290134-1 iPLDS II Components Picture 'IBM PC/XT, PC/AT are registered trademarks of International Business Machines Corporation. "ESPRESSO is a copyrighted by the University of california at Berkeley and is used with permission. 4-1 November 1987 Order Number: 290134-003 IPLDS" INTRODUCTION TO PROGRAMMABLE LOGIC DESIGN FUNCTIONAL DESCRIPTION OF IPLDS II When performing a programmable logic design on a CAD system, the design must first be entered using one of a variety of entry methods. These methods typically include schematic capture or Boolean equation entry using a standard text editor. Less typical entry methods include netlist entry, whereby a hand drawn schematic can be entered in a node-bynode fashion, or state machine entry in a text or graphical mode. All of the design entry methods with the exception of graphic state machine entry are supported by the iPLDS II software. iPLDS II supports netlist and Boolean equation entry using any standard text editor. State machine software and schematic capture libraries are also available from Intel as optional entry methods. Depending on the entry format used, the design may require translation into Advanced Design File (ADF) format. Once the design is in ADF form, the Logic Optimizing Compiler expands any TTL macros, minimizes all .equations, and fits the design into a device-specific JEDEC Design File. The JEDEC Design File is programmed into the EPLD by the Logic Programmer Sc;>ftware using the iUP-PC hardware. Thus,· the circuit design is transformed into an operating EPLD on one workstation. Once the design has been entered into the CAD package, several· processing steps may occur. The design is usually translated into a format usable by the software, logic reduction may be performed, and, finally, some form of programming file can be produced. Most CAD packages also produce documentation of the minimization and device fitting results, including the final pin assignments. The Intel Programmable Logic Software II (iPLS II) is composed of four functional modules: design entry, netlist conversion, file compilation and device programming. Once the programming file has been generated, the design can be transferred into silicon in a programming manner similar to that used for EPROMs. Design· Entry Design entry is typically accomplished by creating an ADF using an ASCII text editor, or by using a schematic capture package.. 4-2 intJ IPLDS II 4-3 inter iPLDS II Netlist Conversion File Compilation If schematic capture of state machine entry is used, the design must be converted into an ADF format. The optional SCHEMA II-PLD schematic capture package is a low-cost way to enter schematic designs. SCHEMA II-PLD supports EPLD primitives and user-defined macro symbols. It also outputs directly in ADF format. SCHEMA II-PLD contains the EPLD Manager, which provides a single user interface to both SCHEMA II-PLD and iPLS II software. The P-CADtt and Futurenett systems may be used to capture EPLD symbols provided the EPLD libraries and ADF convertors are used. State machine entry may be performed via the iSTATE software and a standard text editor. File compilation is performed by the LOGIC OPTIMIZING COMPILER. The LOC accepts an ADF and converts it into an industry standard JEDEC file which is used to program the device. As a part of this process, the LOC expands TIL macros into equivalent EPLD logic, minimizes the logic equations using the Espresso algorithm, and maps the network and logic equations into a cell map for the selected device. The final output of the LOC is a JEDEC Design File. The JEDEC Design File describes the input design for the designated EPLD in JEDEC standard format. For designs using the SAC312, iPLS II R1.S utilizes proprietary algorithms to efficiently use the device resources. The improved Fitter in R1.S optimizes fitting for all devices. tFuturenet is a registered trademark of FutureNet Corporation. ttP-CAD is a registered trademark of P-CAD Corporation. LOC MmlLt H AnF Mlnlo.l,'<-ttlol"l , XCONTF =:_'='="='=;.,=,:',=;, ";~ogram' [)ev~ce =========-,. D1 51-... · "!r ::"" Enter JEDcC flla name> LJEUJI Pat.h. C.\IPLSII i::::::(:;ii; :-" ;,,' ; ";: 987 - 1986, AL1ERA Corpcratlon . BICTEST. JED XCDNTRDL. JED XCONTROL.JED SEMINAR!. JED SEMINAR2. JED '; : : : EXal'lllne DeYll:e EXIT "·;·.1:,' ; .. : = = Press .... --~ to '''', .. : ...... ;; ..:.:'>;::: ..: .... ,: .... ,.. ;,.. --:=::::-=-=====. . .-... - LIse default name _ _ ..... j.:':. ::'.:.:.' 290134-10 Logic Programmer Software Main Menu The Intel Universal Programmer for the Personal Computer (iUP·PC) is a versatile programming solu· tion in a PC-based system. Installed in an IBM PC/XT, PC/AT or compatible host, the iUP-PC emu· lates the performance of the standalone INTEL iUP-200A Universal Programmers. As such, it sup· ports the iUP Generic Universal Programmer Inter· face (iUP·GUPI). With the appropriate socket adapt· ers for the iUP·GUPI, the iUP-PC supports all Intel EPLDs. Future EPLDs will be supported by new GUPI adapters or adapter upgrades. Other Intel de· vices-EPROMs, EEPROMs, and microcontrol· lers-are also supported by the GUPI. The iUP·PC is controlled by the LPS or the iPPS (Intel PROM Pro· grammer Software). iPLDS II includes the iUP-PC, which contains the iPPS, PCPP programming card, interconnect cable, and the GUPI base. GUPI adapters are available separately. chosen, the Logic Optimizing Compiler will minimize and fit the design during compilation. Finally, iPLS II contains. the Logic Programmer Software which controls the iUP-PC programming hardware for all Intel EPLDs. I. Design Input The entire spectrum of design input methods is available to the logic designer in iPLS .11. Everything from TIL schematics to Boolean equations are ac· cepted and processed by the LOC. A. TTL SCHEMATIC ENTRY SCHEMA II·PLD is an optional software package that allows EPLD design to be implemented with standard TIL functions. SCHEMA II·PLD contains a symbol library that includes common SSI/MSI TIL symbols. SCHEMA II-PLD also outputs directly in ADF format. The TIL symbols appear in the ADF in the form of macro calls. During compilation, iPLS II automatically expands these calls from its TIL mac· ro library. Thus, with SCHEMA II·PLD, conversion to EPLD logic primitives is performed automatically in a manner completely transparent to the user. IPLS II SOFTWARE The Intel Programmable Logic Software II (iPLS II) has many options and enhancements for implement· ing a logic design. iPLS II accommodates a wide variety of design input methods. Schematics, state machines or Boolean equations may all be used provided the proper formats and convertors are im· plemented as needed. No matter what method is 4-5 iPLDS II Only parts supported by the SCHEMA II-PLD TTL symbol library and the iPLS II TTL macro definition library may be used for TIL schematic entry. In most cases, this won't be a' limitation' as the most common parts are included in both libraries. Parts not in the macro libraries may be created by the user and stored in proprietary user libraries. SCHEMA II-PLD also supports creating of user-defined macro symbols. The optional iPLS II Macro Librarian supports creation of iPLS II macro libraries. B. SCHEMATIC ENTRY WITH INTEL $YMBOL LIBRARY D. STATE MACHINE ENTRY: In the past, state diagrams or flowcharts (ASM ' charts) were merelY abstractions used to obtain the logic equations ,necessary to implement TTL de. signs. With the advent of the iPLS II state machine convertor (iSTATE), this is no longer the case. USing an IF THEN I ELSE format, the designer may enter the state machine description without having to extract the logic and convert the equations into TTL components. The state machine to Boolean logic conversion is handled by the state machil'\e convertor, provided the input file adheres to the specified State Machine File (SMF) format. If the user, prefers designing with EPLD logic primitives but still' wants to use schematic entry, SCHEMA II-PLD, in addition to supporting TTL schematic capture, also supports. design using EPLD primitive symbols. Users can enter their design and have both a schematic drawing and an ADF version of the deSign. The logiC symbols are loaded from the Intel library and connected in the usual manner. Optional symbol libraries are also available for PCCAPS" by P-CAD Corporation and DASH-2, -3, -4"" by FutureNet (iSLlBPCAD, iSLlBFNET). The iSIMLIB optional library is available for simulating logic designs with P-CAD's PC-LOGS logic simulator. Summary of Optional Entry Requirements: TTL Schematic Capture 1. TTL Macro Libraries 2. SCHEMA II-PLD PC-CAPS 1. Intel Library used to design logic circuit 2. Component List Output 3. PCAD convertor used in LOC (Library and convertor contained in iSLlBPCAD) C. TEXT EDITOR ENTRY DASH-2, -3, -4 1. Intel Library used to design logic circuit DeSigners who are familiar with the logic primitives and the Advanced Design File format can directly enter 'ADFs with a standard text editor. .The bulk of the design entry can be accomplished using Boolean Equations obtained from a Karnaugh map or truth table. Hence, the need for conversion to gates is eliminated. This method of entry is useful for sub-circuits that will be incorporated into larger designs. 2. Pin List Output 3. FutureNet convertor Lised in LOC (Library .and convertor cOntained in iSLlBFNET) State Machines 1. State Machirie File (SMF) format used 2. Optional state machine convertor used in (Convertor contained in iSTATE) ·PC-CAPS and PC-LOGS are registered trademarks of P-CAD. Corporation. toc , "DASH-2, -3, -4 are registered trademarks of FutureNet, Corporation. II. Logic File Compilation Before programming the part, the deSigner must compile the input deSign file into a JEDEC standan:!. file. This function is pertormedby the Logic Optimiz~ ing Compiler. . 4-6 l .--_ ..... _------------------------.•• SCHE~A 11- PLD DRAWING FILE I •• ' .~, .----------_. =ii r en = cCD iPLS II LOGIC OPTI~IZING CO~PILER (LOC) INTERACTIVE NETLIST ENTRY ...._ .1. In .......,_EPLD ESPRESSO I FITTER 1..--- TTL ~iNI~iZER JEDEC USER-DEFINED ~ :::J m :::J 1'" -..j < DI :::J Co 60 ._--------------------- =a iSLlBPCAD ~ INTEL EPLD SY~BOL LIBRARY --.-- "II fn :::J' DI ::I. = NETLIST ENTRY .--------. •• ••• • ~--------~'rf : •• • •._------_.•• .--------. • • • •• • ..............• ._------_. • TEXT EDITOR. iSTATE STATE ~ACHINE ENTRY : ATEXT EDITOR: INTEL EPLD SY~BOL LIBRARY iSLlBFNET · • S~F STATE "@ ~ • 290134-6 IiiiiI F c= ~ c= ~ ~ ~ IPLDS II LOGIC OPTIMIZING COMPILER (LOC) OUTPUT FILES Once the input file is in Advanced Design File (ADF) format, the LOC will compile it into a device-specific JEDEC Design File. The first phase of this compilation is performed by the MACRO EXPANDER. The Macro Expander expands Intel or TTL macros into equivalent EPLD equations. The second phase is performed by the ESPRESSO MINIMIZER. The minimizer reduces all the logic equations to their simplest form using the ESPRESSO II-MV algorithm. The final phase of compilation is performed by the FITTER. The Fitter creates a cell map of the minimized equations according to the resources available within the specified device. - JEDEC Design File A properly deSigned circuit results in the desired file from the LOC-the JEDEC Design File. The JEDEC Design File is a device-tailored EPROM cell programming map expressed in JEDEC standard fprmat. - MACRO EXPANDER - Resource Utilization Report The Resource Utilization Report gives an indepth view of what was used inside the EPLD. Items such as device pinout, macrocell usage, and feedback arrangements are all listed. Unused resources are also listed to aid the user in adding logic or merging EPLD designs. Logic Equation File The LEF file lists the logic equations after they have passed through the minimizer. It is these equations that are actually implemented in the final design. The input design file is initially passed through the MACRO EXPANDER. The Macro Expander searches the file for any non-EPLD network elements. If found, the Expander then searches the User Libraries and TTL Library for the unidentified element. Once the element is located, the design file element is replaced by the equivalent EPLD primitive implementation found in the library. Having the Expander search the User Libraries allows the user to create his own macros. User macro files are created with a standard ASCII text editor and are stored in libraries by the optional iPLS II Macro Librarian. - Compiler Error File If a logiC circuit is incorrectly designed, messages are produced by the LOC denoting the errors. To a$sist the redesign, these errors are placed into the Compiler Error File for later reference. FILE MERGING Once a design is successfully implemented, the LOC can merge it with other deSigns by simultaneously running the two ADF's. In this manner, LSI circuits can be broken into manageable chunks that can be implemented and tested individually. After each portion is completed, the subcircuits can be merged into . one ADF to implement the total design. ESPRESSO MINIMIZER The minimization in the LOC is performed by the ESPRESSO II-MV MINIMIZER. Developed by the University of California a, Berkeley, the ESPRESSO II-MV algorithm is regarded by many as being the best minimization method available. ESPRESSO IIMV uses DeMorgan's and other logic theorems to reduce the equations to the least number of product terms possible. Since product terms are the key variable in the EPLD architecture, the ESPRESSO II-MV Minimizer provides the simplest equatiOnS possible. As a result, the success rate for fitting large designs is dramatically increased. III. Device Programming After the design has been successfully entered, minimized and fitted, the deSigner programs his part using the JEDEC file produced by the LOC. Programming is accomplished by running the Logic Programmer Software. FITTER LOGIC PROGRAMMER SOFTWARE The FITTER examines the architecture of the speCified device, then tries to map the minimized equations into the resources available. The Fitter automatically assigns pins unless pin asSignments are IiIlready specified in the design input file. The fitting sequence continues until a successful fit is accomplished or all possible implementations are' exhausted. Release 1.5 of iPLS II includes a new, faster Fitter that supports PGA packages and the 5AC312. Also included in this new Fitter is the capability to allocate p-terms to adjacent macrocells for devices such as the 5AC312 that support p-term allocation. To prog~am a device with the LPS, the user enters the file name and device to be programmed. The LPS checks if the device is blank, programs the device, then verifies that the device was programmed correctly. As a part of the Intel EPLD Programming Algorithm, each programmed cell is checked. Adding the complete device check after programming gives double verification that the part has been successfully programmed. 4-8 inter IPLDS II ' ______ ' '. I I - ...... •• ...... I I I I I I I I I IUP - GUPI ADAPTER I I ,-----------------, .---------------------I I ....... I I I I PCPP PROGRAMMING CARD : F.)III;ii;;_~;;II"-4 1 _____ -~ • _____________________ _ INTERCONNECT CABLE (SIDE VIEW OF P.C. HOST) IUP - GUPI BASE MODULE 290134-7 The Intel Universal Programmer for the Personal Computer (IUP-PC) It is also possible to read a pre-programmed device and program other devices with the program read. The JEDEC Editor in LPS provides a hierarchical view of the device from the pin level, to the macrocell level, to the product term level. At the product term level, individual EPROM cells may be set or reset to connect or disconnect the logic equation inputs. GUPIBASE The Generic Universal Programmer Interface (GUPI) is used for all programmable logic support. As all Signal generation to devices is done by the GUPI, the programming waveforms are extremely reliable. Using the GUPI also allows upgrading for future devices with the simple addition of a plug-in adaptor. Future Intel EPLDs will be supported by the GUPI system. If the user does not want an EPLD to be read, the Security bit may be set when running the LPS. The Security Bit prevents a device from being examined after it has been programmed. This function is useful for protecting confidential designs. GUPIADAPTERS Table 1 details the GUPI adapters required for the logic devices. The adapters available for programming EPROM's, E2PROM's and microcontrollers can be found in the data sheet for the iUP.PC (Intel order number 290130). The adapters contain the device description data for a family of similar devices. New devices will be supported by new adapters or by a firmware upgrades in existing adapters. IUP-PC HARDWARE The Intel Universal Programmer for the Personal Computer consists of the PCPP programming card, 50-lead interconnect cable, GUPI base and GUPI adapter. Together they form a system for programming most PROM-type Intel devices directly from the PC host. SPECIFICATIONS PCPP Host System The Personal Computer Personal Programmer (PCPP) is the programmer interface card that fits into the IBM AT IXT or true compatible. It is capable of driving both the iUP-GUPI base and the iUPFAST27K personality module. The PCPP emulates the performance of the Intel iUP-200A. The LPS or iPPS (Intel PROM Programmer Software) controls thl'l PCPP, causing the programming card to generate the control signals for the GUPI base. The iPLDS \I software requires an IBM PC/XT, PCI AT or other true compatible computer capable of running MS-DOS· version 2.0 or later. The computer must have a 360KB double-sided, double-density diskdrive, a hard disk, and 512KB of RAM. Additional memory is required for the optional schematic capture programs. A color monitor is recommended, 4-9 iPLDS" Table 1. Intel Programmable Logic Development System II Programming Support Equivalent Gate Count Number of Macrocells SC031 EP310 300 8 GUPI LOGIC-12 20 Pin DIP SC032 EP320 300 8 GUPI LOGIC-12 20 Pin DIP SC060 EP600 600 16 GUPI LOGIC-9 or GUPI LOGIC-liD 24 Pin DIP qC090 EP900 900 24 GUPI LOGIC·9 or GUPI LOGIC-liD 40 Pin DIP Device IUP·GUPI Adapter Package Type Supported SC121 EP1200 1200 28 GUPI LOGIC-12 40 Pin DIP SC180 EP1800 1800 48 GUPI LOGIC-18 68 Pin PLCC and JLCC SC180PGA 1800 48 GUPI LOGIC-18PGA 68 Pin PGA SCBIC 1200 (inPLU):8 (# of Ports):S GUPI LOGIC-BIC 44 Pin PLCC SAC312 1200 12 GUPI LOGIC-liD 24 Pin DIP (EPXXX Devices from Altera Corp.) as the color graphics available provide a better representation of the data than a monochrome display. The PCPP programming card requires one full-size card slot in the host computer. Width: °MS·DOS is a trademark of Microsoft Corporation Height: 1.6 inches (4.1 cm) GUPI: Length: 7.0 inches (17.8 cm) Operating Environment S.S inches (1.4 cm) Environmental Charac.terlstics Operating Temperature: Electrical Characteristics PCPP: Worst Case Power Consumption at IBM PC liO Channel Supply Voltage Voltage Variance Equipment Supplied Personality Max. Current Module Drain +5%, -4% FAST27K +SV -12V_ +10%, -9% FAST27K +12V +S%,-4% GUPI 10·C to 40·C Operating Relative Humidity: 85% Maximum HARDWARE 1.898 A 102.9 mA S30mA - PCPP programming card - Interconnect cable - GUPI base - (GUPI-LOGIC adaptors purchased separately) Physical Characteristics SOFTWARE PCPP: Length: 13.3 inches (33.9 cm) - iPLS II (S diskettes) - iPPS (2 diskettes) Height: 3.9 inches (10.0 cm) DOCUMENTATION INTERCONNECT CABLE: SO lead ribbon cable - iPLS II User's Guide (order number 450196) - iPLS II Release 1.S Supplement (order number #4S3703) - PCPP User's Guide (order number 168161) Length: 3.0 feet (91.4 cm) Width: 2.43 inches (5.5 cm) 4-10 intJ IPLDS II iUP·GUPI Intel Universal ProgrammerGeneric Universal Programmer Interlace: Generic programmer base which holds GUPI adaptors GUPI LOGIC-IID GUPI Adaptor for the 5AC312, 5C060, 5C090, and future 24-pin and 40·pin EPLDs. GUPI LOGIC·09 GUPI Adaptor for the 5C060 and 5C090 DIP EPLDs GUPI LOGIC-12 GUPI Adaptor for the 5C031 , 5C032, 5C121 and future 20 pin DIP EPLDs GUPI·LOGIC-18 GUPI Adaptor for the 5C180 and future 68 pin PLCC and JLCC EPLDs GUPI LOGICGUPI Adaptor for the 5C180 de· 18PGA vice in a 68 pin PGA package. GUPI·LOGIC·BIC GUPI Adaptor for the 5CBIC and follow·on products Adapts 24 pin DIP socket to 28 ADAPT24T028 pin PLCC socket; for use with GUPI· LOGIC·09 and GUPI LOGIC·IID. ADAPT40T048 Adapts 40 pin DIP socket to 44 pin PLCa socket; for use with GUPI LOGIC·09 and GUPI LOGIC·IID. ORDERING INFORMATION Order Code iPLDSIl iPLSIl iUP·PC MLiB iSTATE iSLlBFNET iSLlBPCAD iSIMLIB Product Description Intel Programmable Logic De· velopment System II: iPLS software, iUP·PC, iPLS II Us· er's Guide Intel Programmable Logic Software II: Logic Builder de· sign entry, Logic Optimizing Compiler, Logic Programmer Software, iPLS II User's Guide Intel Universal Programmer for the Personal Computer: PCPP programming card, in· terconnect cable, iUp·GUPI base, Intel PROM Program· ming Software PCPP User's Guide iPLS II Macro Librarian: Macro Librarian Software and User's Guide Supplement for creat· ing user·defined macro librar· ies. Intel State Machine Software: Entry format documentation, state machine convertor for LOC Intel Symbol Library-Future· Net: EPLD symbol library for FutureNet DASH-2 schematic capture package, Futurenet Pinlist convertor for LOC Intel Symbol Library-PCAD: EPLD symbol library for PCAD PC·CAPS schematic capture package, PCAD Component List convertor for LOC Intel Simulation Library (PC· LOGS): EPLD simulation Ii. brary for PC· LOGS simulator by PCAD IPLDS II UTILITIES TTL Macro Library TTL Macro Library Macros ac· cessed by Macro Expander for ",ost standard TTL symbols SIM EPLD Functional Simulator Func· tional simulator for most EPLD logic designs. 4-11 inter iUP·PC INTEL UNIVERSAL PROGRAMMER FOR THE PERSONAL COMPUTER • Easily Upgradable for new Devices Through Low-Cost Plug-In Adapters • Extremely Versatile-Programs Intel or Intel';Compatlble EPROM, E2PROMs, EPLDs, Peripherals and MicroControllers, Including the New 5AC312 EPLD ' • Personal Computer Version of the iUP200A/201A Universal Programmers • Runs on an IBM PC/AT*, PC/XT* or True Compatibl.. " • GUPI and FAST27K Personality Modules Provide,Support for Numerous Device Families • Utilizes the inteligentTM and QuickPulse Programming™ Algorithms The Intel Universal Programmer for the Personal Computer"IUP-PC, provides a high performance programming solution from a PC host. Through plug-in adapters for the Generic Universal Programmer Interface (iUPGUPI), the iUP-PC supports virtually all programmable Intel devices. Upgrades for new devices are made by the simple addition of a GUPI adapter or the upgrade of an existing adapter. 290130-1 NOTE: GUPI Adapter NOT included. ·IBM PC/AT and PC/Xl are registered trademarks of International Business Machines Corporation. 4-12 November 1987 Order Number: 290130-002 IUP-PC the programming base which holds the device adapters. FUNCTIONAL DESCRIPTION The iUP-PC provides a fast, versatile and reliable programming solution from a Personal Computer host. Downloading to a stand-alone programmer or moving from one workstation to another is no longer required. With the iUP-PC, the designer may do his development and programming on one Workstation. Through the Generic Universal Programmer Interface (iUP-GUPI), the iUP-PC is made extremely versatile. With the iUP-GUPI the designer may program across EPROM, E2PROM, Microcontroller, Peripheral and EPLD device categories with the mere change ,of a plug in adapter. No other hardware or software addition is needed. As all of the programming signals are generated at the GUPI base, extremely reliable waveforms reach the device. GUPI AdaptersO-The GUPI Adapters plug-in to the iUP-GUPI base. They carry the sockets and hardware for a particular device family. iPPS-The Intel PROM Programmer Software (iPPS) runs on a personal computer under DOS and controls the PCPP/host communication. °NOTE: Though the iUP-GUPI base is included in the iUPPC package, the GUPI Adapters are NOT included. The desired adapters must be ordered separately. PCPP CARD The PCPP is an 8085 based co-processor board. Communication between the host and the PCPP may be controlled by the iPPS or LPS (Logic Programmer Software). Version 2.3 or greater of iPPS is required for running the iUP-PC on a personal computer. LPS is the programming software included in Intel's Programmable Logic Software II (iPLS II). COMPONENTS The iUP-PC programming system consists of five components: PCPP-The Personal Computer Personal Programmer (PCPP) is an IBM PC/XT form factor expansion card which fits into an IBM PC/XT, PC/AT or true compatible. The PCPP is capable of driving the iUP-GUPI and FAST27/K modules. Future Intel devices will be supported by an iUP-GUPI adapter or adapter upgrade. Interconnect Cable-A 50 lead ribbon cable connects the PCPP to the iUP-GUPI. iUP-GUPI-The, Intel Universal Programmer-Generic Universal Programmer Interface (iUP-GUPI) is ' I I I I I I I I ______ ' .... .... .... .... .... ... I I I I I I I I I I IUP - GUPI ADAPTER I .----------------------. • , - - - - - - - - - - - ______ 1 · • --------; :• I • ' 1 _____ - PCPP PROGRAIojIojING CARD ...-I 'l_§;i~~~_ C • _____________________ _ INTERCONNECT CABLE (SIDE VIEW OF P.C. HOST) IUP - GUPI BASE IojODULE 290130-2 Figure 1. The Intel Universal Programmer for the Personal Computer (IUP·PC) 4-13 inter . '," IUP·PC· " IUP..GUPI MODULE GUPI ADAPTfERS ' The iUP-G(JPI is a generic base module that enables theiUP-PC'system to accept low-cost plug-in adapters. These adapters configure the system to support a wide variety of programmable devices-EPROMs, microcontrollers, and EPLDs--as well as device package types (refer to Table 1). The iUP-GUPI adapters prQvide the final, link of tlle-' iUP-PC programming system. The.adap,er~,provide the proper sockets and,ch8l'8\rter:istic,information for ~i1ies of Intel devi~, ' The iUP-GUPI LOGIC adapters' complete the programming solution of the Intel Programmable Logic Development System II (iPLDS II). The GUPI LOGIC adapters provide support fOF the entire range of Erasable Programmable Logic Devices (EPLDs). The adapters support families EPLDs w,ith similar architecture, such, as the 5CO~ and 5C09q. All future EPLDs will be supported by t!'le GUPI LOGlq adapter system. The iUP-GUPI module connects to the PCPP card via a ribbon cable. An opening in the top of the iUPGUPI provides easy plug.in installation of the GUPI adapters (refer to Figure ,2). The iUP-GUPI offers the programming performance of earlier Intel personality modlJles, with the fastest Intel programming algorithms for each device type. For example, the iUP-GUPI uses the, new QuickPulse Programming algOrithm to program the 1-Meg EPROM in seconds. ' Intel's one megabit EPROMs are also supported with GUPI adapters. Adapters are available for the 27010,27011, and 27210. The page mode of the 27011 is supported by the GUPI 27011 adapter. Other Intel EPROM support is provided with the FAST27/K personality module. The MCS-51 and MCS-96 microcontroller families are supported by the GUPI MSC-51 and GUPI 8796 adapters. Supplemental adapters provide support for the variety of microcontroller package types. The 8741 and 8742 peripheral components are supported by the GUPI 8742 iadapter. Table 1 displays a cross-reference of the EPLD GUPI adapters and the devices they support. Table, 2 displays a cross~reference of the EPROM/Microcontroller adapters and the devices they support. Note that these tables are current at the time of printing. Contact your Intel'sales representative for information on currerlt support. iUP·GUPI 6BIERIC BASE MODULE 290130-3 Figure 2. GUPI Adapter Installation Table 1. EPLD GUPI Module Adapters Device GUPI logic-liD Type GUPI. Loglc-09 EPLD GUPI Loglc-12 GUPI Loglc-18 GUPI LogIc-18PGA , GUPI Logic-SIC 5C031 5C032 ,5C060, 5C090 ; 5C060 5C090' " " 5C121 5C180 , " " ", 5C180G " 5CBIC 5AC312 Package Types DIp· DIP' DIP • ADAPT units aV8Ilable to adapt DIP socket for PLCC package. 4-14 PLCC CJ PGA PLCC intJ Table 2. EPROM/Mlcrocontroller GUPI Module Adapters Device Type EPROM GUPI 27010 GUPI 27011 GUPI 27210 27011 27210 GUPI 8742 GUPI MCS-S1 GUPI 8796 GUPI 8796LCC 27010 Peripheral 8741AH 8742AH Microcontroller 87C51 8752BH 87C252 8794BH ~795BH Package Types DIP DIP DIP DIP PLCC DIP 8796BH 8797BH 8796BH 8797BH PGA DIP LCC The hexadecimal display shows the PROM device type selected. The iU~·Fast 27/K Personality Module With the iUP-Fast 27/K personality module the user can program, read, and verify the contents of Intel's high density EPROMs, from the page-programmable (512K) 27513, to the CMOS 27C64, 27C256, and 87C64 EPROMs. This personality module supports the inteligent Programming algorithms and the inteligent IdentifierTM. The inteligent Identifier lets the personality module interrogate the PROM device in the programl master socket. It determines whether the type selected matches the type of PROM device installed and then selects the proper inteligent Programming algorithm. The inteligent Programming algorithms reduce programming time' up to a factor of 10. Table 3. FAST271K Module Device Support Prom Type Fast 271K Module Fast 27/KU2 Kit Fast 27/K-CON° Kit 2764 2764A 2764 2764A 27C64 87C64 27128 27128A 27256 27C256 27512 27513 2764 2764A 27C64 87C64 27128 27128A 27256 27C256 27512 27513 2817A . 2817A EPROM 27128 27256 Low cost, plug-in upgrade kits allow addition of support for Intel's latest EPROMs. The first upgrade kit added support for the 27512 and innovative pageprogrammable 27513 plus the 27128A and 2817A.lt has now been replaced by a second upgrade kit, iUP-Fast 27/K-U2 a~ding support for Intel's new CMOS EPROMs. (refer to Table 3). E2PROM 'Uses Quick-Pulse Programming Algorithm. As shown in Figure 3 the iUP-Fast 27/K personality module contains two 28-pin sockets, a hexadecimal display (0 through F), and a red. LED that indicates when power is being applied to a socket. The program socket holds the device. being programmed. The master socket will be used in future upgrades. THE IPPS SOFTWARE The iPPSsoftware, included with the iUP-PC brings increased flexibility to PROM programming. The 4-15 IUP·PC 0-2764 27641. 1 ( 27C64 87C64 2-27128 D PIN 1 -I1.-Ff--HI=II-..oJI;:1I1 ~-(27128A 4 27256 27C256 5-27512 6-27513 7-28171. 8-27916 PROM DEVICE TYPE HEXADECIMAL DISPLAY SOCKO_~~======:;~======~~==~~~~~ POWER ' -_ _ _--'__ LOCKING INDICATOR ..,RMS 290130-4 Figure 3. IUP-Fast 27/K Personality Module with U2 Upgrade iPPS software provides user control through an easy-ta-use interactive interface and performs the following functions to make programming quick and easy: With the iPPS software the user can load programs from system memory or directly from a disk file. Access to the disk lets the user create and manipulate data in a virtual buffer. This block of data can be formatted i:1to· different PROM word sizes for program storage into several different PROM types. In addition, a program stored in the target PROM, the system memory, or a system disk file can be interleaved with a second program and entered into a specific target PROM or PROMs. • Reads PROMs, ROMs and EPLDs. • Programs PROMs directly or from a file. • Verifies PROM data with buffer data. • Prints PROM buffer, or device file cont~mts on the . system printer. • Performs interactive formatting operations such .as interleaving, nibble swapping, bit reversal, and. block moves. The iPPS software supports data manipulation in the following Intel formats: 8080 hexadecimal· ASCII, 8080 absolute object, 80136· hexadecimal ASCII, 8086 absolute object, 80286· absolute object, and 80386 bootloadable object. Addresses and data can be displayed in binary, octal, decimal, or hexadecimal. The user can easily change default data formats as well as number bases. • Programs multiple PROMs from the source file, prompting the user to insert new PROMs. • Uses a buffer to change PROM contents. 4-16 inter iUP-PC iUP-PC SPECIFICATIONS DOCUMENTATION 168161-PCPP User's Guide HOST SYSTEM 166428-iUP-GUPI Module User's Guide The iPPS will run on an IBM PC/XT, PC/AT or other true compatible with a DOS operating system. The PCPP requires one full-sized card slot inside the PC. User's Guides for Adaptors, FAST 27/K Modules, and upgrades included with respective units. OPERATING ENVIRONMENT ORDERING INFORMATION Product Description Universal Programmer for the Personal Computer: PCPP Programming Card, 50-Lead Interconnect Cable, iUP-GUPI, iPPS, PCPP User's Guide 28-Pin PLCC Socket Adapter ADAPT24T028 for GUPI LOGIC-09 and GUPI LOGIC-liD ADAPT40T044 44-Pin PLCC Socket Adapter for GUPI LOGIC-09 and GUPI LOGIC-liD piUPGUPI Generic Universal Programmer Interface (Base) GUPI LOGICIID iUP-GUPI Logic Adapter GUPI LOGIC09 iUP-GUPI Logic Adapter GUPI LOGIC12 iUP-GUPI Logic Adapter GUPI LOGIC18 iUP-GUPI Logic Adapter GUPI LOGIC18PGA iUP-GUPI Logic Adapter for 5C180 PGA GUPI LOGICBIC iUP-GUPI Logic Adapter iUP-GUPI EPROM Adapter GUPI27010 iUP·GUPI EPROM Adapter GUPI27011 iUP-GUPI EPROM Adapter GUPI27210 iUP-GUPI Peripheral Adapter GUPI8742 GUPIMCS51 iUP-GUPI Microcontroller Adapter Order Code iUPPC Electrical Characteristics PCPP: Worst Case Power Consumption at IBM PC I/O Channel Supply Voltage Voltage Variance Personality Max. Current Module Drain +5V +5%,-4% FAST27K 1.898A -12V +10%, -9% FAST27K 102.9 mA +12V +5%,-4% GUPI 530mA Physical Characteristics PCPP: Length: 13.3 inches (33.9 crn) Height: 3.9 inches (10.0 cm) Interconnect Cable: 50 lead ribbon cable Length: 3.0 feet (91.4 cm) Width: 2.43 inches (5.5 cm) iUp·GUPI: Length: 7.0 inches (17.8 cm) Width: 5.5 inches (1.4 cm) Height: 1.6 inches (4.1 cm) GUPI8796 GUPI8796LCC Environmental Characteristics Environmental Class: piUPFAST 27K iUPFAST 27KU2 iUPFAST 27KCON B Temperature: Operating 10 to 40 degrees C Non-Operating - 40 to 70 degrees C iUPFAST 27KIT Relative Humidity: Operating Non-Operating 85% Maximum 95% Maximum 4-17 iUP-GUPI Microcontroller Adapter iUP-GUPI Microcontroller Adapter EPROM Personality Module FAST 27/K Upgrade Kit Adds Quick-Pulse algorithm and device support Combines piUPFAST 27K and iUPFAST 27KU2 SCHEMA II-PLD SCHEMATIC CAPTURE SOFTWARE SCHEMA II-PLD is a powerful, low-cost schematic capture software package for designing with Intel EPLDs and with standard MSI, SSI, and discrete components. For EPLD designs, SCHEMA II-PLD outputs Advanced Design Files (ADFs) that can subsequently be compiled by iPLS II software. SCHEMA II-PLD supports EPLD symbols as well as MSI and SSI macro symbols, allowing designs to combine TTL and EPLD symbols as needed. The ability to create user-defined macro symbols that can be translated into ADF .macro calls adds to SCHEMA II-PLD's power and versatility. I • • The EPLD Manager included in SCHEMA II-PLD provides a single user interface to both SCHEMA II-PLD and iPLS II software. EPLD Manager software is also available separately for users who already own SCHEMA II. 00027~-1 4-18 iPLS II MACRO LIBRARIAN The iPLS II (Intel Programmable Logic Software II) Macro Librarian is an optional software package that allows designers to create user-defined macro libraries for EPLD designs. User-defined macro functions are first developed as individual macro files using an ASCII text editor. These files are then combined into macro libraries by the Macro Librarian. Macro calls to use the functions can then be placed in iPLS II ADFs (Advanced Design Files) where they will be expanded during compilation by the iPLS II Macro Expander. Use of macros in iPLS II Advanced Design Files (ADFs) allows EPLD design to proceed at a higher level than with EPLD primitives alone. Note that a preconfigured library of TTL macro functions is available from Intel to all registered iPLS II users. The Macro Librarian is not needed to use this TTL library. It is designed for users who need to create libraries that contain user-defined macros. 000275-2 4-19 UTILITIES FUNCTIONAL SIMULATOR UTILITY Description: Simulation of EPLDs is supported with Intel's SIM (Functional Simulator). Combinatorial as well as registered designs can be simulated and circuit operation verified before a device is programmed. The design is simulated with a user generated vectorfile. . Availability: SIM is a standalone utility that runs on any IBM PC, XT, AT or compatible. The simulator is available at no cost to Intel EPLD customers. Contact ypur local Intel sales office .. 4-20 PAL2ADF UTILITY Description This document is a brief note on the use of the PAL2ADF program in translating PALASM 1 files into Intel's Advanced Design File (AD F) format. Descriptions for actual use can be found on the accompanying Manual page in the file PAL2ADF.MAN. The PALASM file serves as a template for mapping the PALASM equations into ADF. The translation is performed as follows: 1) Read PAL description, and set the PAL pins to their appropriate EPLD primitive counterparts 2) Parse file and produce network description 3) Translate equations to ADF PAL Configuration Database When it is translating a PALASM file, PAL2ADF reads a database (default:PAL2ADF.DAT) that tells it: • How many pins the PAL has • Which default EPLD to translate to • What pins are special inputs (Clock and Output Enable default~) • What EPLD 1/0 primitives to use for each PAL pin The EPLD 1/0 primitives specify the network architecture that the EPLD must take on in order to mimic the functionality of the PAL. See the PAL2ADF.DAT file for more information. Reconfiguring Outputs In step (2) above, several checks are done in order to make sure that the network is configured appropriately. These primarily involve output pins, although input pins can be specified as well. The first reconfiguration is for active low outputs in their equations. i.e., PALASM: ISIGNAL = A * 18 + C becomes ADF: SIGNAL = I(A * 18 + C); The other reconfigurations are slightly more complex. Consider a PAL pin X which is an output with a D-Iatch. The output value is fed back into the P-term array after the Output Enable. This is described as a Registered Output Registered Feedback (RORF) in the Intel EPLDs. The default network description for this pin then is: NETWORK: X,X = RORF (Xp,CLK,GND,GND,OE) where CLK and OE are the default Clock and Output Enable signals. Normally, there would be an equation that would describe Xp. (The 'p' is used to name the P-term value.) If, however, the X feedback is never used in an equation, then the 1/0 macrocell is reconfigured to a Registered Output No Feedback (RONF). 4-21 NETWORK: x = RONF (Xp,CLK,GND,GND,OE) .. For thOse 1/0 pins on the PAL which are used strictly as inputs, these use the Combinatorial Output 1/0 Feedback (COIF) primitive, with the Output Enable shut off (GND). The P"term is tied to the feedback, in order to satisfy the semantics of ADF. NETWORK: YY,YY = COIF (YVp,GND) EQUATIONS: YVp = YY; If the PAL pin is being used strictly as an output and is never used in an equation, then the primitive is reconfigured to a Combinatorial Output No Feedback (CONF). NETWORK: YY,YY = COIF (YVp,GND) This is the same as above where a RORFis reconfigured to a RONF. Multiple PAL Designs into 1 EPLD It is possible to incorporate· multiple PALASM descriptions into one EPLD. If each PALASM description is disjoint, (Le., they have different pin names for each pin) then you can simply translate each file (with the pinlist information OFF) and compile them together with the iPLS Logic Optimizing Compiler (LOC). .. The compiler allows you to specify multiple ADF files, allowing different subnetworks within one EPLD. You will probably want to use a larger EPLD to fit all the designs in. If the PAL designs are not disjoint, then there are some steps that dan be done by hand to integrate the designs. A simple exarnple would be where one PAL feeds another a signal, and the second uses that to generate another signal. .. ~Q.1 c------~ C~ LJ -~L:J 4-22 X In this case, C is an output of PAL 1, and an input to PAL2. In PAL2, ,C,Z, and W generate the signal X. Suppose we have the equations: PAL1 IC=A*/B PAL2 X = IC*Z*W + C*/Z*W In the resulting ADFs, the following NETWORKS are produced: ADF for PAL 1: NETWORK: A = INP(A) B = INP(B) C = CONF(Cp, VCC) EQUATIONS: C = I(A * IB); ADF for PAL2: NETWORK: Z = INP(Z) W = INP(W) C = INP(C) " X,X = RORF(Xp, CLK, GND, GND, OE) EQUATIONS: Xp = IC*Z*W + C*/Z*W; These can be joined together into !l single ADF: NETWORK: A = INP(A) B = INP(B) Z ='INP(Z) W = INP(W) X,X = RORF (Xp, CLK, GND, GND, OE) EQUATIONS: C = I(A * IB); Xp = IC*Z*W + C*/z*W; Notice how C is now an intermediate variable rather than an actual signal. This is obviously a simple example, yet similar techniques can be applied to more complex cases. As much more logic can be placed into larger EPLDs, the job of splitting functions across multiple devices is reduced. Availability The PAL2ADF utility is available at no cost to Intel EPLD customers. Contact your local Intel sales office. 4-23 JED2HEX CONVERSION UTILITY Description JED2HEX is a utility to convert JEDEC files created by iPLS (.JED) into Intellec HEX ,files which can then be read by Intel's iPPS software. This allQWs programming of EPLDs via Intel's iUP200Al 201A using a GUP I base and the appropriate adaptor (e.g. LOGIC-12). The following diagram ,represents a typical development cycle. ~_iP_L_S_~--_.J_E_D-~~ I JED2HEX .HEX I-------!.~ B 'PPS , t ' .TTF INSTALLATION: To install the utility and its device specific files, place the master disk in drive, A: and invoke the JINSTALL.BAT batch file with the destination path for the utility and device files. !:xample: A: JINSTALL C: MYPATH When using JED2HEX, attach the package description letter when entering the device type. That is, enter 5C121D for a 5C121 ceramic DIP when prompted for the device type. Entering 5C121 will result in: ***ERROR: Device File Missing To determine the packages supported in your JED2HEX software, examine all,the .ttt extension files; it is the .ttt files which the device type command attempts to match. When using iPPS, a file format of 8080 or 8086 must be specified when copying the JED2HE:X generated HEX file to the buffer or directly into a device. If 8080 or 8086 is not specified, the default file format type of 80386 will be chosen and a "GENERAL ERROR - ILLEGAL FILE TYPE SPECIFIED" will result. An example of the proper COPY format: PPS> COpy a: filename. HEX TO PROM 86 ' Availability The JED2HEX Conversion Utility is available at no cost to Intel EPLD Customers. Contact your local Intel sales office. 4-24 -n+-.I® AP-279 APPLICATION NOTE 111'eI October 1987 Implementing an EPLD Design Using Intel's Programmable. Logic Development System LAKSHMI JAVANTHI DSO APPLICATIONS NOTE This design can also be developed on iPLS II (Version II of Intel's Programmable Logic Software). Some of the prompts or message may vary slightly, but the overall procedure is identical. INTEL CORPORATION, 1986 Order Number 280310-002 4-25 inter AP-279 OVERVIEW Welcome to the fascinating world of ERASABLE PROGRAMMABLE LOGIC DEVICES (EPLDs) and Intel's Programmable Logic Development System (iPLDS). This application note has been written for ,the newcomer to Intel's devices and design tools. It has been designed as a step-by-step guide through the tools but should also prove useful as a reference document for the experienced logic designer. n I PROGRAM· MABLE LOGIC By the, end of this application note you will have designed/solved multiple logic problems and be in a position to implement solutions to many of the digital design challenges you face today. It is anticipated that this application note will be used in conjunction with Intel's iPLS software. To increase the 'usefulness of this application note, Intel will supply a PCB card for you to experiment on and a sample diskette (see Appendix E for details). An introduction to Erasable Programmable Logic Devices (EPLD) 2. An introduction to Intel's Programmable Logic Development System (iPLDS) 3. Implementation of EPLD and iPLDS using detailed examples to implement a logic design. GATE ARRAY II STANDARD CELL FULL CUSTOM 2442 Figure 1. Logic Options Full Custom: These circuits can be tailored to give the best functional performance with the highest level of integration, the smallest silicon area, the lowest power use, and be produced for the least cost at high production volumes. This application note is divided into the following three sections: 1. CUJOM Standard Cell Library: This approach represents an integrated circuit which is composed of predesigned and precharacterized cells chosen from a computer data base library of cells. Gate Arrays: These are integrated circuits that contain a regular, usually square, matrix of predefmed logic gates. User Programmable Logic: The concept of user programmable logic is to provide the designer with the benefits of custom LSI chips from standard products. INTRODUCTION Programmable'logic in the form of PALs have been available for some time. They have become more complex as Large Scale Integration (LSI) techniques have been applied to this technology. ' A recent innovation in the programmable logic field has been Intel's introduction of an ERASABLE Programmable Logic Device. Using the same technology used in the manufacture of EPROMs, Intel now offers increased flexibility to the logic designer. The benefits of Large Scale Integration circuits are many fold. These circuits offer lower manufacturing costs, since the use of customized LSI circuits reduces required printed circllit board space, thereby significantly reducing board costs. These circuits also consume lower power so less expensive power supplies are required and cooling fans are also eliminated. LSI circuits also have higher reliability than equivalent systems comprised of many low density standard components. Intel has addressed the limitations of gate arrays and fuse programming logic with its EPLD products and development system support tools. The benefits to the system designer are: • Greatly reduced lead times • Low design costs • Ease of design changes • Low power dissipation from CHMOS technology As end users of semiconductors moved into higher and higher levels of integration, chip designers found it more and more difficult to define larger and larger blocks of logic. These difficulties led to the emergence of the user-defined Application Specific Integrated Circuit (ASIC). • Multiple programming facility • Maximum flexibility in each chip and the ability to erase and reprogram • High density products that maximize function, illtegration, and quality • A self-contained, low-cost sophisticated development system based upon the industry standard IBM PC XT or AT. The options available for application specific logIC are explained below and shown in Figure 1. 4-26 AP·279 Intel EPLD devices are available in many configurations to fit most applications. A complete listing of data sheet availability is covered in Appendix E. Table 1. Intels EPLDs EPLD Gates Pins 5C031 5C060 5C090 5C121 5C180 300 600 900 1200 1800 20 24 40 40 68 Dedicated I~uts 10 4 12 13 12 I/O 8 16 24 24 48 DESIGN TECHNIQUES USING INTEL'S EPLDS EPLDs are now a cost-effective solution to the problem of large scale logic integration. EPLDs are the simplest form of high density application-specific logic to implement. At present, the following logic devices are available from Intel as shown in Table 1. Intel's EPLDs use the "Sum Of Products" architecture with programmable AND and fixed OR gates to drive a combinatorial or registered output. Each of the devices listed in Table 1 has different attributes and resources targeted at specific applications. In general each device contains multiple sets of programmable MACROCELLS as shown in Figure 2. Everything is programmable (and erasable if you need to make modifications). Product terms may be generated from any combination of input terms-any terms not used are considered a "don't-care" in the array. The output register is also programmable-you can choose D-type, Toggle, SR, or even JK FLIP-FLOPs; you can even choose no output register if you only require combinatorial outputs. The clock and output enables are also programmable. Designing with EPLDs is similar to designing with standard TTL logic circuits. The focus moves from "how can I configure this design ~ith standard parts" to "what else could I replace using this EPLD". Remember, if you ever use all of an EPLDs resources you just move up the device chain to the next bigger component-all of the work you did is DIRECTLY PORTABLE to a larger device. Any network, either combinatorial or registered, has an equivalent two level form. Any logic circuit consisting of AND, OR, NOR, NAND, XOR Logic can easily be converted into the corresponding truth table. Any Boolean expression, no matter how complex, may be written in Sum-Of-Products form. This Sum-Of-Products expression that has been derived from the truth table can be reduced until it has as few product terms as possible. This procedure can be repeated for any complex network. Let us consider a very simple network as shown in Figure 3. This logic circuit consists of an AND gate, an OR gate and a NOT gate. The inputs are A, B, C, and the output isY. For this simple network, the truth table is shown in Thble2: A Boolean expression can easily be written from the truth table in a Sum-Of-Products form. This expression contains the relationship between the inputs and the output. CLOCK III OUTPUT ENABLE 2 II: w l- OIP AND ARRAY I- u OUTPUT PIN REG ;:) Q ~ II. FEEDBACK OR ARRAY' ~. a ~ ~ _____________ • _____ INPUT TERMS (INCLUDING FEEDBACK) 2443 Figure 2. Macrocell Arch 4-27 inter AP·279 iPLDS, Intel's Programmable Logic Development System, provides a full spectrum of ways to design and use a variety of design tools with fast, easy-to-use entry software. The iPLDS contains all the software, hardware, documentation and devices needed to program EPLDs. iPLDS are the most advanced PLD design tools available. It provides better utilization of device resources (more gates per chip) than any other development software. These versatile tools are for users with different skill levels and applications. iPLDS tools handle the details of converting your design to working silicon on the personal computer. 2444 Figure 3. Simple N.,twork The iPLDS contains the three fundarriental modules Note that the output Y is true iri five of these eight states (0,2,4,6, and 7) so expressing Y in the form "Sum-Of-Products" by writing the ones in terms of A, B, and C yields: • Logic Builder (LB) • Logic Optimizimg Compiler (LOC) • Logic Programmer Software (LPS) Y = IA*/B*,C + IA*B*/C + A*/B*/C To implement the logic design we will use the iPLDS modules in the order listed above. + A*B*/C + A*B*C Hence, given any network, that network can be converted into its truth table. Next, a Sum-Of-Products expression that has the same truth table can be derived. If so desired, this· Sum-Of-Products expression can be reduced using DeMorgan's theorem, to simplify the circuit (you will see later that this will not be required). The modules are essentially independant modules that use special data files to pass information as shown in Figure 4. These data files are the ADF, RPf, LEF, and JED files. DEVELOPMENT SUPPORT The Logic Equation File (*.LEF) contains the primitive equations tl\at have been minimized by the Logic Optimizing Compiler. The Advanced Design File (* .ADF) is generated from the Logic Builder and contains the Inputs/outputs and all the primitive equations. Development tools are critical to the use of new technologies because tools allow you to control and use a new technology. Good tools help you, the designer, to work in familiar methods, then translate the design to the device. The Utilization Report File (*.RPf) contains information on the macrocell and pin assignments. Gopd tools broaden the applications by making it easy to use new technology in designs. They are n~t a barrier to using the technology, but encourage its use and applications. The JEDEC File (*.JED) is the file generated by the Logic Optimizing Compiler used to program the device using the Logic Programmer. Advanced and innovative technologies need similar advancements. and innovations in the corresponding tools. Before implementing the logic design using the iPLDS, let us briefly discuss the iPLDS family of parts to be familiar with the iPLDS modules. Table 2. STATE 0 1 2 3 4 5 6 7 logic Builder (LB) INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 ' 1 OUTPUT C 0 1 0 1 0 1 0 1 The Logic Builder module guides you through the entire process of design entry by prompting for necessary information and showing a screen display (one primitive at a time) with input signals on the left side and output signals on the right side. The Logic Builder is used to generate an Advanced Design File (or ADF) by inputting the data in netlists or Boolean equations. Y 1 0 1 0 1 0 1 1 After all required data are entered, the Logic Builder modu1e indicates whether the circuit is complete and properly connected. If any changes need to be made, the module enables you to edit the circuit design either by 4-28 inter LOGIC BUILDER (LB) AP-279 DESIGN MQUIRElIENT FITTER oUlGNFllE TRANSLA'IOII DEMANDER! TRANSLA10III EXPANDER LOGIC PROG. (LP) FITTER! ASSEMBLER 2445 Figure 4. Block Diagram of IPLDS Module. systematically scanning through the primitives in the Advanced Design File (ADF) or by directly finding a primitive by the name of a node connected to it. • The FITTER matches your design requirements with the known resources of the Intel device. Any circuit may be edited. The Logic Builder reads in the ADF and prompts you for changes. The Logic Builder also allows two or more partially complete ADF files to be MELDED together to form a more complex function. This concept is not discussed in this application note but will be a topic of a future application note. logic Optimizing Complier (LOC) • The ASSEMBLER converts the fitted .requests into JEDEC file. logic Programmer Software (LPS) The Logic Programmer Software provides a user interface to the JEDEC Standard File output of the Logic Optimizing Compiler and to the Logic Programmer Interface. You can use the Logic Programmer Software to view JEDEC files and to program your designs into EPLDs. The Logic Optimizing Compiler provides an easy-ta-use interface to the Logic User System software. Regardless of the type of design entry method used, the LOC first translates an Advanced Design File (ADF) into internal logic equations; then it performs a Boolean reduction on the translated design, and finally produces a JEDEC Standard File, which is then used to program an Intel EPLD. In addition, you have the option of requesting an analysis of the Logic Equation File (LEF) as output by the Minimizer module. The Logic Programmer Software is used The LOC performs the following functions: The iPLDS requires an IBM PC XT. PC AT. or other compatible computer. A color monitor is preferred. The computer must have at least one 360K double-sided double-density disk drive. a second 360K floppy disk or hard disk. and at least SI2K bytes of RAM memory. • to program your designs into EPLDs • to verify the validity of data in the device • to read data from the device • to display JEDEC data graphically • to edit JEDEC data HARDWARE REQUIREMENTS • The TRANSLATOR translates the ADF into an intermediate Logic Equation File (LEF). (Most errors are· detected and corrected). • The EXPANDER expands the Boolean equations into Sum-Of-Products form. removes redundant factors from product terms, and produces another LEF. • The MINIMIZER performs a sophisticated Boolean reduction on the translated design to maximize utilization of the EPLD. . The iPLDS consists of the Logic Programmer Interface card. and the programming unit needed to program and verify EPLDs. The Intel iUP 201 with a GUPI adapter may be used as an alternate system to program the EPLD devices. • The LEF Analyzer converts the LEF output by the MINIMIZER into a human readable file to allow you to . see your design. (*.LEF) SOFTWARE REQUIREMENTS • The DEMANDER organizes the file output by the MINIMIZER. The personal computer should be capable of running DOS V3.0 or a higher version. The Intel Programmable Logic 4-29 inter Ap..279 PART A Software (iPLS) that contains the software controlling the logic programmer interface and assisting in the design of Intel applications is shipJle4 on flo~y diskettes. ,Fo!lr Outputs-lA, IB, IC, 10 are required to drive the ,LEOs arranged ma DICE pattern as shown in Figure 5. PROBLEM DEFINITION • •• • 18 • We are going to use iPLOS to implement a medium complexity logic function. As a vehicle to show, the usage of the tools and design techniques will design a circuit that win roll and spin a pair of dice, Thedesign has ~,en split into multiple stages for illustration purposes. we 10 • " ' 1C 1~ 1A 1C . " This example has been chosen since it incorporates many of a typical logic design tradeoffs and also solves many of the typical problems a hardware logic' designer will encounter. 1~ 2452' Figure 5. Dice Configuration , , " ' Operating sequeD(;e~Rolling dice from I to 6 and the block diagram of the circuit, both shown in Figure 6. may Appendix A contains some basic definitions 'that t>e useful when reading through the design and its implementafion. ' The total number of states that are possible is 16 since the four LED pairs gen~rate a permutation of (2**4) 16. The LEOs should be lit up such that any number between I and 6 in,clusive is shown. ,Hence·, out of the 16 possible states, ol/ly six states are valid. This leaves, ten invalid states. ' , ' = DESIGN SAMPLE Problem Set-up If the LEOs come up in a valid state upon power up, then a number between 1 and 6 will be displayed. The circuit is designed to set both of the dice spiiming when you push a switch and display a'ran4om set of numbers when you release the switch. ,The dice will spin at a rate that is visually pleasing and roll at the highest possible rate to ensure randomness, However, if the LEOs come up in an invalid state upon power up, then you have ·to design tQe;'circuit such' that any one of the ten invalid states will fall into a valid state. You will implement the design in the follOwing steps: If the LEOs fall into anyone of the ten invalid states, 'then you have designed the circuit·to move into a state where lA, IB, Ie, 10 have zero logic values respectively on the next clock edge. Every time a zero logic value appears in the' invalid states, then at the next clock edge, LED IA getS lit up'generating a.valid state. 'Since I is a valid state, the numbers betWeen I and 6 inclusive will be displayed \ at all subsequent clock 'edges. A. One dice that will roll out a number. B. Add a switch that will control the roll/not roll action. C. Add a second dice to roll a number. O. Add a sphming option to both dice. Listed below are the steps involved in designing the logic circuit. . . ., '.', 'E. Retro~fit a power saVe feature to extend battery life. Hence, at the end of the five design steps you will have ,a pair of dice spinning and showing a pair of numbers between I and 6 in a very random manner. At the 'end of five design steps, you wi)l have added a very realistic and ,practical feature to your design and that is extending the battery life by power saving option. It is important to note that the five steps mentiQned above are sequential steps in that step C can be achieved only after steps A and B etc. Let us describe the sample circuit for the dice rolling example. It is a very "simple ~ircuit all~ing you to concentrate upon the design process. It illustrates the pos,sible design' stages and considerations in deWl. ilie a' STEP I. Generate tOO 'state diagram to clearly show the operating sequence including the status of the outputs for each state and the influence of the inputs on the nex.t· state transitions as shown in Figure 7, We have arbitrarily chosen that the stjltes.should count 1,2,3,4,5,6, and repeat. You could. have i~plemented the design us~ any. seq~ence but we chos",'the most obvious. ~(lte how most of the invalid states move you to state 0 which then puts us into a valid state which then repeats forever. . "', , , a ", , , .STEP '2. Oeiterate truth ta'ble 'with entries for all available states and combinations of inputs, and use the next states resulting from these as ,shown in Thble 3. The bracketed numbers, (3) etc., show the number being '4-30 intJ AP·279 U· reel ~ • • ~ ~ •• 2451 Figure 6. Roiling Sequence DlCEIB has five entries from valid states displayed on the dice and the 0, I values of 10, IC, IB, and IA indicate which LEDs should be OFF/ON to display the required dice pattern. DICE1B = (1A*I1B*/1C*I1D + I1A*1B*I1C*/1D + 1A*1B*I1C*/1D + 11A*1B*1C*/1D + 1A*1B*1C*/1Dj STEP 3. Convert the truth table directly into Sum-Of-Products equations as shown below: DICE I C has three entries from valid states DICEIA has four entries; 3 from the valid states and one to control the invalid states DICE1C = (1A*1B*/1C*I1D + 11A*1B*1C*/1D + 1A*1B*1C*/1Dj = (/1A*1B*/1C*/1D + I1A*1B*1C*/1D + 11A*1B*1C*1D + 11A*/1B*I1C*/1Dj DICE1A I. . .. - - - - - - - I N v A L l D - - - - - -.....·~I · - - - - - - - V A L I D - - - - - - - - t 2453 Figure 7. 4-31 llIble 3. 'n'uth Table for DICE1 Input State Output State " 1A 18 1C 1D 1A 18 1C 1D 1A Valid state 18 1C 1D Invalid state ", CHANGE TO THE NEXt VALID STATE 1 0 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0(1) 0(2) 0(3) 0(4) 0(5) 1(6) 0 1 0 1 O· 1 1 1 1 1 1 0 0 0 1 1 1 0 0(2) 0(3) 0(4) 0(5) 1(6) 0(1) CONTROL THE INVALID STATES 0 1 0 1 0 1 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0(1) DICEID has one valid entry DICE1D = (I1A*1B*1C*1D) Note that no attempt has been made to minimize these equations - the iPLS software that you will use later contains reducing algorithms and other techniques to optimize the design. This allows you to focus upon the problem and not on tasks such as Kamaugh map reduction which a computer can often do better anyway. Having designed part A of the circuit, you can now move on to tool usage to implement the design. Refer to the Intel Programmable Logic Software Manual if you have not installed the iPLS software. In order to invoke iPLS type the following command C:\IPLS>IPLS The iPLS menu will appear as shown in Screen I. The number to the left of each function allows you to seiect a function with a function key. Two kinds of function keys are available: toggle keys and field keys. < F3 > and < F4 > are toggle keys. All other keys are field keys. Functions beyond are executed by pressing the < Shift> key together with the function key. Press < F3 > to invoke the Logic Builder and observe the Logic Builder menu as shown in Screen 2. The first prompt asks for the file name. If the file already exists, its header informatio~ and primary inputs and outputs are displayed. If you enter a new file name, the Logic Builder module prompts for all the functions remaining .on the screen. Enter: DICEl Create New Netlist (Y IN) : Y In this sample session, user entries are all in uppercase letters. Note: IPLS is case sensitive. When initially invoked, the Logic Builder module displays its configuration menu. The Logic Builder configuration menu shows uSC 121" as the default Intel part and, on the right side of the menu, displays those primitives that are legal for use with the SCI2!. As soon as you enter another part (e.g. SC060) the list of primitives changes to display the primitives applicable to that specific part. Press < F6 > and enter SC060 when prompted for user , entry. Screen 2 shows the Logic Builder Configuration Menu for theSC06O. • The left side of the screen shows a menu of functions, each preceded by a function key number. 4-32 inter AP·279 Intel Progr.Mm.ble Logic Softw.re iPLS "an" Flo Hltlp F2 Exit . F3 Logic IIl,1ildtr F4 LOC FS Logic Progr ....r Fb PirectOl"y F7 Itan••• FUa FII COpy FUa F'I tallta FUa Floo.OS co...nd iPLS Version 3.0, Copyright eCl Copyright eCl Selact a function: ~'1aS, ~'1as, Intel Corporation Altara Corporation Screen 1. Intal PrograM.able Logic System Logic Builder Config Menu: Flo IhIlp F2 F3 .l~ctl.1'! . F4 Pt-u.ithu lJHl 1I000f Ult ...... Q.lCI NOS' " •. NO" "_1" FS rill Fb [P\). F7 dice ~ ..... hI' SCobo . . . It. . . . NOT mF .It $0'" X.1t SOSf' <:tlr f.jt hillMr Fa ( ....v F'I )~. FlooC....'" tFlo.-.rt - - . " March b, l'1l1b cm TO., <10011' T01" tF2«."biOl'l "..., tF31nputs tF4OU~ .....t. <-- Designer: Screen 2. 4-33 AP-279 Table 4. fb f7 f6 f"l floO tflo tf2 tf3 tflf Prompt EPLD Designer Company Data Comment Part Number Revision Inputs .Outputs , User Entry SCObO Your Name Your Company Prasent Date Our first design 0,]. lo.O CLOCKiillo DICEloAiloO,DICEloBi"l,DICEloCiil6,DICEloDiil7 Design Primitives are divided into the following groups: ,. The right side of the screen shows the list of available primitives (these are discussed in detail later). • The two lines at the bottom of the screen are designated for comments (first line) and prompts (second line). • The center of the screen is used to show a representation of the primitive; name and pictorial representation are in the middle, input signals are to the left, I\Dd output signals are to the right of the primitive. • The direction of the arrow located on the left side of the screen below the list of functions determines the starting point and direction of design entry. If the arrow points to the left, entry is from output pins to input pins. If the arrow points to the right, entry is from input pins to output pins. • Input Primitives (INP,UNP) • Logic Primitives (AND,GND,CLKB,NOf,VCC,OR,NAND,NOR,XOR) • Equation Primitives (EQN) • 1/0 Primitives (JOJF, NOJF, NORF, RORF, etc) Refer to Appendix A for an explanation of the Primitives used in this example. The logic is based on input clock transitions. At the rising edge of the clock we want the LEDs to generate a particular state depending on the input state. You want the output of the LEOs to follow the input, which is basically a 0-TYPE FUP-FLOP. You also requjre the feedback to generate the next state, which means that you should use a O-TYPE FUP-FLOP with FEEDBACK or RORF as shown in Screen 4. NOTE We have assigned pin numbers to pin names by using the "@" symbol within the name of the logic variable. Specific pin numbers need not be assigned if not desired. In that case, the LOgic Builder will assign its pin numbers for you. NOI'E ftle Logic Builder module starts with the last output entered. 'iYpe ill the itU"ormation as given in Thble 4 in the Logic Builder Config Menu. The information is also shown in Screen 3. After entering all of this required information, iPLDS will automatically prompt you through defining .the circuit, starting with a primitive to drive the last output specified. When you are prompted to select a primitive to drive DICEID enter: Once in the Logic Builder main menu, you are guided with.prompts to enter information as follows: Select a primitive to drive RORF ,Enter the name of the primitive to connect to the first node. The name may be entered by typing the name of the primitive, which highlights the appropriate primitive on the right side of the menu, then pressing . ~ICE1DQ7~ Now you are prompted for the remaining connections: For FBK: lD For OE, P, C: Press (VCC, GND are the defaults). Subsequently; a representation of the primitive is displayed in the center of the screen .surrounded by input and output signals. You are prompted for names of nodes to connect to each of the signals. The Design Primitives library contains approximately 80 basic fuitctional blocks needed for designing circuits in programmable logic products. For·D: INlD For ClK: CLOCK Selpct a primitive to drive CLOCK: INP ~4 AP-279 Intel Programmable Logic System Logic Builder Config Menu: INP NO.1' Fl. H4tl" Fi! ftdl'l tIIIN NOR' cue, F3 aiMKtiOft ' Pl-i.lth._ F5 'U. Fb' EPI,.) F? 'UilMf' , fll (0lrp1m~ f'floDtoMent '.t, P.,.t fF J. fFi! ff3 ff If ",*,.,. "evhion In,ltt. Outputs MOSF NOff HAN' ROlF Fif Artt dice ], 5CDbD Your nalRe Your cOllpany March b, J.'lIb Our first design NOIt RON' NOT ROtt, 0It SON' XfW rosp' TOll" e~lp' D.], ]'.D clockilJ. DICEJ.AiJ.D,DICEJ.Bi',DICE],Ci6,DICEJ.Di? CONF TOIIIf' otOJF TO" .1'001' <-- Outputs:DICEJ.AiJ.D,DICEJ.Bi',DICEJ.Cill,DICEJ.Di? Screen 3. Intel Programmable Logic SystelR Logic Builder Main Menu: fJ. "Ill' Fi! Edt f3 1I.w flf ,p.n f5 "1M fb £dit f7 (ortflg fa NoMUat f' It.d,.... Oe P C D Out diceld fbk Clk RORF INP EiIIN eLkS AND NAND Nott NOT NO.!P' NORF NOSf' NOTF ROI' RONP' RORf Olt SONP' XOII SO!F COIF TOIP' eONF TONF JO"F TOTF JON' <-- Pin-? fbk:]'d Screen 4. 4·35 AP-279 In: CLOCK Select a primitive to drive IN1D: EQN After you are prompted for the equation, type it in as derived" in the Problem Set-up section. Please note that "/" indicates a "logical "NaT", "*" indicates a logical "AND", and" +" indicates a logical "OR". The equation is terminated by a ";" as shown in Screen 5. IN1D = (LA * 18 * lC * 11D) ; The following prompts and design entries, as shown in Table 5, are needed to complete the design entries for DICEIC, DICEIB, and DICEIA respectively. To save the configuration and return to iPLS menu you must press (Save-Exit). Note that you are saving the Advanced Design File (ADF) that is generated by the Logic Builder. You can print the ADF file that has been created at the end of this session if you so desire. You can use when in the iPLS main menu to print the ADF file for a listing. You can verify your file with the DICEl.ADF file given in Appendix D. If you desire a listing, while you are in the iPLS main menu, type the following: PRINT DICE1. ADF The Logic Builder will stop prompting for prill)itives once you have entered the complete design. Press < F8 > to show the design so far as shown in Screen 6. Press < F2 > to exit. Submitting the ADF to the LOC This ADF file is now compiled using the Logic Optimizing Compiler. To enter the ADF created with the Logic Builder module into the Logic Optimizing Compiler (LOC), press < F4 > to access the LOC menu. The Logic Builder main menu is cleared, replaced by the Logic Builder exit menu. TableS. USER ENTRY PROMPT Select a primitive to drive lC: Out: Oe: P: C: ]): Select a primi ti ve to dr i ve IN1C: IN1C: Select a primitive to drive J.8: Out: Oe: p: C: D: Select a primitive to drive INJ.8: INJ.8: Select a primitive to drive loA: Out: Oe: p: C: ]): Select INloA: aprimitive to drive INloA: RORF ])ICE1C VCC GN]) GN]) IN1C EQN (lA*18*/1C*/l]»+(/1A*18*lC*/1D)+(lA*18*lC*/l]»; RORF ])ICE18 VCC liN]) GN]) IN18 EQN (lA*/18*/1C*/l]»+(/1A*18*/1C*/l]»+(lA*18*/1C*/l]» +(/1A*18*lC*/l]»+(lA*18*lC*/l]»; RORF ])ICE1A " - VCC GN]) GN]) IN1A EQN (/1A*18*/1C*/1D)+(/1A*18*lC*/l]»+(/1A*18*lC*1]» +(/1A*/18*/1C*/l]»; 4-36 inter AP·279 Intel Programmable Logic System Logic Builder Main Menu: F1 Help F2 Edt F3 ••• F4 tpen, FS Find INP ·Nt",. vee ElN ..tit, eLK' NOS,. Oe P GND GND 'e D inld clock elk Fb Edill F7 CO"t1, F!I Nod. List Out diceld Fbk ld RORF F'I Itldr•• ANt NOfF NAN_ ~OIf MOR ftOW NOT IUUI' OR SOW nit sos,. en'TU' (ON' TOff" ~O"I' TOTI" "ON' <-- Pin=7 Screen 5. Once the LOC menu is displayed, you are prompted through the LOC menu functions as follows: Finally you are prompted with: The Input Format prompts you to specify your form of input: If input is in the form of a pinlist as output by DASH-2, enter P, if input is an Advanced Design File, enter an ADF or press (ADF is the default). If output is a component list from PCAD, enter C. Enter: N Note that the LOC generates a synopsis of its progress as shown in Screen 8. You are returned to the iPLS menu. At the end of the LOC a JEDEC Stimdard File has been created which we will use in the Logic Programmer, DICEl.JED. INPUT FORMAT: A FILE NAME: DICE1 MINIMIZATION: INVERSION CONTROL: default> WOULD YOU LIKE TO IMPLEMENT ANOTHER DESIGN [YIN]? Programming the EPLD After you have answered all the prompts, you are asked if you wish to run under the above conditions as shown in Screen 7. DO YOU WISH TO RUN UNDER THE ABOVE CONDITIONS [Y IN]? Finally, you submit your design to the Logic Programmer. In order for you to use the Logic Programmer, you must have the programming card plugged in. Please refer to the Intel Programmable Logic Software User Manual for installation instructions. Alternatively you can use Intel's GUPI (Generic Universal Programmer Interface) to program your device. Enter: Y 4-37 inter AP-279 rntel Prog~ammable Logic System Logic Builder Main Menu: clockill FJ. Hal. dicdaill0 F2 £XU F3,fta. dicelbil'l F4' ,~.n, dicdcil!l F51"'imt', ", diceldil7 Fb £~U:t" F7 ,ClInfig F!lN'o" List F'l Redf1aw INP .NO.!I' [GN flO!f' {lICe NOS" AN. NOTf' NAN.I'IOtf' NOR.RONf' NOT ,RORF ,Oft SONI" XORCOSF COIF TtlI' CONI'" TONI' JO"F TOTF JONF vee GND ld inld clock la lb lc inle inlb inla <-- Unconnected nodes are bold Press a function key: Screen 6. Intel Programmable Logic System Loe Menu F1 Help F2 ifllS "an", F3 Input Format F4 File Name F5 ,Millldzation Fb F7 ADF dicd ,Ves Inversion Control 'L[F'Anelys!s No Ves Do you wish to run under th~ above conditions [V/N]? Screen 7. While you are still in the iPLS menu, press < F5 >. This function allows you to access the Logic Programmer Software. The Logic Programmer will ,now come up as shown in Screen 9. The iUP-GUPI and assorted Q{JPI LOGIC adaptors provide an alternative programmil)g solution, for IIltel's H-series and EPLD devices, when purchased with the iPLS. This complete set of software IS available without the Logic Programmer pod and the IBM interface card. , 4-38 intJ AP-279 Intel Programmable Logic Software LOC Menu F1 Help F2 iPLS lIenu F3 Input For.,t F4 Fil. Na •• IUni.i2llltion F6 InverSiOn control F7 LEF An,lysis F5 ADF Minimization LEF-Analysis d i.cel ***INFO-LOC-Begin execution ***INFO-LOC-ADF converted to LEF ***INFO-LOC-S.O.p. LEF produced ***INFO-LOC-LEF reduced ***INFO-LOC-LEF analyzed ***INFO-LOC-Resource demand determined ***INFO-LOC-Design fitting complete ***INFO-LOC-JEDEC file output LOC cycle successfully completed Would you like to implement another design [YIN]? ScreenS. Use the cursor keys to select "Program Device" option. This completes part A of the design, which was to roll a single dice. The programmed device can be tested as described in Appendix C. When you are prompted Enter JEDEC file name Enter: DICE1.JED PARTS When you are prompted for: Now that you have a good understanding of the manner in which a .circuit is designed and also a good understanding of how the programming tools are used to program the device, you can proceed to the next step in the five stages of the dice design. According to the truth table generated in part A, the dice will roll a number between 1 and 6 inclusive as long as you supply a power source. When you disconnect the power source, all the LEDs will turn off. This will not be much help since you can only see the dice roll, but not actually see a number displayed. Select Device For Programming Enter: 5CD6D When you are prompted for: Do you wish to enable verify protection? [Y / N ] ? Enter: N When you are prompted for: Let us include an additional feature into the rolling dice. Let us include a switch to control the rolling and display of the dice. Do you wish to enable turbo-bit? I[ Y/ N] ? Enter: N You could choose to gate the clock of the dice or add the necessary inputs to the product terms to effect this design. If you were to stop after this step, then gating the clock would be a simpler choice, however, you will require the dice to roll during part D of the design; so we will choose to add product terms at this stage. This also results in a better engineering solution since gated clocks often cause problems in large systems, and it has been shown that synchronous systems are more reliable. Once you have answered all the prompts, the device is programmed and ready to be used in an actual circuit, as shown in Screen 10. Exit from the Logic Programmer after saving the JEDEC file by using the "EXIT" option. 4-39 intJ AP·279 »evice: " JE»EC File: LOGIC PROGRAMMER LOGIC PROGRAMMER Version 3.1 Copyright (e) l'6S, INTEL Corporation Copyright (C) 1'6S, ALTERA Corporation 30bS Bowers Ave, Santa Clara, CA 'SoSL (!fo6) '67-6060 HELP Program Device Enter JE»EC file name [.JED]: »ICE1·JED Directory of .JE» files for: C:\IPLS Change »isk Edi t JEDEC File Program Device Verify Device Examine »evice EXIT Press <-- to use default name Screen 9. " JE»EC File: »ICE1.JED LOGIC p, Copydg' Copyrig 30bS Bo' H »evice: SCobo JEDEC File Header Text Designer: Your Name Company: Your Company Part I: Revision: 0.'0 EPLD: :SCobo' »evice code: Chang Edit JE Comment: PART A: DICE ROLLING LB Version 3.0, Baseline 17x, '/2b/6S Progra Verify, Insert a SCobo into the socket Strike any key when ready Examin E Screen 10. 4·40 ' LOGIC PROGRAMMER' AP-279 Since you already have a proven design of a rolling dice from part A, we shall use the Logic Builder and edit that design. You may wish to save the original design at this stage. You can do this by using the < FlO> key in the Main Menu. Press < FlO> and issue the following command before re-entering the iPLS menu: OlCE1A COPYDICE1.* DICE1A.* OlCE1B = ((IA*/1B*/1C*/l0) +(lAulB*/1C*/1D) +(lA*lB*IC*/l0) +(llA*/1B*/1C*/l0))*/SWITCH +((/1A*1 B*I1C*/l 0) +(/1A* 1B*lC*/l 0) +(/1A*lB*lC*10) +(11 A*/l B*/l C*/1 0))* SWITCH = ((/1A*1 B*/1C*/1D) +(lA*lB*/1C*/1D) +(11 A* 1B* lC*/l 0) + (lA* 1B*lC*/l OJ +(/1A*IB*lC*10))*/SWITCH +((lA*/1B*I1C*I1D) + (llA*l B*/1C*/l OJ + (1 A* 1B*/1C*11 0) +(/1A*lB*IC*/l0) + (lA*l B* lC*/l O))*SWITCH The truth table is shown in Table 6. Now you can use the iPLDS to design and program the device. Go through the same steps to program the device as in Part A of the design example. Use the Logic builder, the Logic Optimizing Compiler, and the Logic Programmer respectively. The Legic Optimizing Compiler and the Logic Programmer steps are identical to the corresponding steps explained in part A ofthe design example. However, the Logic Builder will be used to. edit the existing file, DICE 1, to include the switch feature as follows: OlCE1C OICE1D ((/1A*IB*lC*/1D) +(1A*lB*lC*/l0) + (/lA*lB*lC*10))*/SWITCH +((lA*l B*/1C*/l 0) + (/1A* 1B* lC*/l OJ +(lA*lB*lC*110»*SWITCH = (/lA*lB*lC*10l*/SWITCH + (lA*lB*lC*/l0)*SWITCH Invoke the Logic Builder Menu from the iPLS main menu by pressing the < F3 > key. Once you obtain the Logic Builder Configuration Menu, type in DICE I as your input file name. The equation primitive must be displayed on the screen in order to edit that equation. In order to display the equation on the screen, use the "Find" command, < F5 >, to find it. Use (Shift)(F3) to get the Inputs option and then add switch at pin #2 to it. The "Find" command prompts for a node name: then searches the design for that node and displays it. If the direction arrow points to the left, the primitive on the output side of the node is shown. If the direction arrow points to the right, the first primitive on the input side is shown. Inputs: CLOCK, SWITCHiil2 Now press < F2 > to exit to the Logic Builder Main Menu and answer the prompts as given in Table 7. After you have modified all four equations to include the SWITCH feature, return to the iPLDS main menu using the < F5 > key and save the design using the < F6 > key. You can verify your ADF file with the ADF file for part B given in Appendix D. All that is left to do now is to edit the four equations, INIA, INIB, INIC, INID to add the SWITCH option to it. Edit the four equations as follows: The file is ready to be compiled using the LOC, and the device is ready to be programmed using the LP. Edit Function The steps required to use the LOC and the LP are identical to the steps in part A. When you press the "Edit" function key, < F6 >, while in the main menu, the edit menu is displayed on the left side of the screen as shown in Screen 11. If you wish to edit an EQN Primitive displayed on the screen, press < F6 >. Then the equation is moved to the prompt line where it can be edited. Now the device that has been programmed is ready to be tested. At this stage in the design, you have completed part B of the design which is to add a switch to give the roll/no-roll option. The programmed device can be tested as described in AppendixC. Hence, the Boolean expressions for this case would consider the situations of when the switch was ON as well as OFF. The Boolean equations would contain the expression for the switch as follows. . Let us summarize before moving on to the next part of the design. 4-41 inter AP·279 Table 6. Truth Table for 0lCE1 Input State SWITCH 1A 18 Output State 1C 1A 10 18 1C . 10 1A Valid state 18 1C 10 Invalid state REMAIN IN THE SAME STATE 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 o· 0 0 0 1 0 1 1 1 1 1 0 0 0 .1 1 1 0(1) 0(2) 0(3) 0(4) 0(5) 1(6) CONTROL THE INVALID STATES 0 0 1 1 1 1 1 1. 0 0 0 0 0 0 0 0 0 1 0 0 0 .0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0(1) 0 0 0 0 o. 0 0 0 0 0(1) CHANGE TO THE NEXT VALID STATE" 1 1 1 1 1 1 1 0 1 0 1 0 0 1 1 1 .1 1 0 0 0 1 1 1 0(1) 0(2) 0(3) 0(4) 0(5) 1(6) 0 1 0 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0(2) 0(3) 0(4) 0(5) 1(6) 0(1) CONTROL THE INVALID STATES 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Note: This part of the truth table is identical to Table 3. We have briefly discussed the EPLD and the IPLDS family of parts. We have also defined the design problem. We have implemented the design using the state equations and the truth table, edited an existing design to add features, and actually programmed a device using the Logic Buiider, Logic Optimizing Compiler, and the Logic Programmer. Our logic in implementing the dice example is to use the LED pairs in outputs lA, IB, IC, and 10 respectively as 4-42 AP-279 Table 7. Prompts Select a primiti ve for swi tchil2 to dr i ve: Out: Se lec t a pr imi ti ve for swi tch to dr i ve: shown in Figure 8. These LEOs are lit up to generate numbers between 1 and 6' inclusive. We are using a O-TYPE FLIP-FLOP to implement the truth table. The clock is a free running clock. A push button switch is also supplied to give the roll/no-roll option. Whenever the switch is ON, the LEOs roll, and when the switch is OFF, the LEOs display a number between 1 and 6, as long as the clock is supplied to the device. User Entry INP SIaJITCH EQN Part C of the design is to include a second dice with the first dice. This is a step towards real-world application since dice are usually rolled in pairs. At the end of this section, you will have a pair of dice rolling and displaying a pair of numbers. All the conditions and truth tables and Boolean expressions that were designed for part B, hold good for DICEI. The equations for DlCE2 would change slightly as explained below. After seeing the dice roll and display a number, you can either quit or move onto parts C, 0 and E of the design process. The following three parts describe a versatile use of the EPLO concept. You have designed a 6 state counter and can define a carry out (fortunately you can use state 6 and do not require extra logic). You can use the carry out as an enable input to form two cascaded counters. PARTe The carry out of 10 is used as an enable input to DICE2. Hence, 10 performs the same function as the push button switch performed in dice 1. Therefore, whenever 10 is enabled or logic high, DICE2 is enabled and rolls a number. DICE2 displays the number when 10 is disabled or logic is low. This configuration is shown in Figure 9. We are using an EPLO 5C060 which is a 24 pin, 600 gate device. It has four dedicated input pins and 16 input/output pins. Up to this point you have used only one input pin which is the switch and only four input/output pins for the four LEOs lA, IB, lC, 10. Intel Programmable Logic System Logic Builder Main Menu Flo Help F2 Edt F3 Ne", F4 F5 Fb f7 Fa Open I'ind Edit Config NOde List f9 Redrl'" loa lob loc lod INP NOJI' IEQNI inlod Eli'IN NOliI' eLKS AliI NANII NOW NtT tft XtR NOSF NO'1F RtIF RtNI' rtOrtl'. StNI' SOSI' COlI'" TtIf CON" TONI' .10.11' TOTI" JONI' --> inld=(la*lb*lc*/ldl\ inld=(/loa*lb*lc*ldl*/switch+(/la*lb*lc*ldl*switch\ Screen 11. 4-43 AP-279 TableS. USER ENTRY IN1]) PROMPTS find: (Now use the key to obtain the EQN Primi tive.) Edit: IN1]) = (/1A*1B*1C*1D)*ISWITCH+(1A*1B*1C*/1D)*SWITCH; IN1C find: (Now use the key to obtain the EaN Primitive.) , Edit: IN1C = ((/1A*1B*1C*/1]»+(1A*1B*1C*/1]»+(/1A*1B*1C*1]»)*ISWITCH +((1A*1B*/1C*/1]»+(/1A*1B*1C*/1J»+(1A*1B*1C*/1]»)*SWITCH; find: (Now use the key to obtain the EQN Primi tive.) Edit: IN1B = ((/~A*1B*/1C*/1]»+(1A*1B*/1C*/1]»+(/1A*1B*1C*1D)+(1A*1B*1C*/l]» +(/1A*1B*1C*1D»*ISWITCH +((1A*/1B*/1C*/1D)+(/1A*1B*/1C*/1D)+(1A*1B*/1C*/1]»+ IN1B (/1A*1B*1C*/1]»+(1A*1B~1C*/1]»)*SWITCH; Find: ' (Now,use the key to obtain the EQN Primitive.) Edit: 'IN1A=((1A*/1B*/1C*/1]»+(1A*1B*/1C*/1D)+(1A*1B*1C*/1D)+ (/1A*/1B*/1C*/1]»)*ISWITCH+((/1A*1B*/1C*/1J»+(/1A*1B*1 C*/1]» +(/1A*1B*1C*1]»+(/1A*/1B*/1C*/1D»*SWITCH; IN1A The two conditions obtained are as follows: When power is ON and lD is enabled, DICE2 will roll. When power is ON and lD is disabled, DICE2 will display. ENABLE IN For DICEl, the logic conditions remain the same as in part A. Just as you used the switch to enable and disable 1A 1B CLOCK 1C 10 1A CARRY OUT 1B 1C ClK 2A 10 2B 2 2C 20 CARRY OUT 2447 2446 Figure S. Figure 9. 4-44 inter AP-279 DICEl, you will use the switch as well as the output of LED 10 to enable and disable DlCE2; because the number on DICE2 is a function of both the switch and the present state of LED 10, as explained above. Now write down the truth table since the state diagrams can easily be inferred from the truth table. Please note that the truth table is identical to the one for DICEI except for the switch input. For DICE2, you will have the combination of the switch and the 10, as shown in Table 9. This is the fourth step in our design process and adds the spin option to the two dice that are roIling when the switch is pushed and display a number when the switch is released. The logic used to implement the spin concept is as follows: When the power is ON and the switch is OFF, DICEI and OICE2 display a random number according to the logic defined in parts Band C respectively. But, when power is ON and the switch is ON, the two dice spin by lighting the LEOs B, C, and O. That is, DICEI will light LEOs lB, lC, 10 while DICE2 will light LEOs 2B, 2C, and 20. This pattern on the LEOs will generate the spinning pattern. The logic is shown in the truth table in Thble 10. The schematic is shown in Figure 10. The Boolean expressions for part C will consider the situation when the switch is ON as well as OFF and also 10 enabled or disabled respectively. The Boolean equations will contain the expression for the switch and LED 10, as shown below. OlCE2A PART 0 = ((2A*/2B*/2C*/20) +(2A*2B*/2C*/20) +(2A*2B*2C*/20) + (/2A*/2B*/2C*/20)) *(/SWITCH*,10) +((/2A*2B*/2C*/20) + (/2A*2B*2C*/20) + (/2A*2B*2C*2D) + (/2A*/2B*/2C*/20)) *(SWITCH*10) As you can see from the truth table, when the present state is any of the three valid states, then the two dice will spin. The dice will also spin if the present state is an invalid state, because all the invalid states go to"O 0 0 0" in the next state. But from the truth table in Thble 10, you see that this particular state is a valid state lighting LED C. OlCE2B = ((/2A*2B*,2C*,20) +(2A*2B*/2C*/20) + (/2A*2B*2C*/20) + (2A*2B*2C*/20) +(/2A*2B*2C*20))*(/SWITCH*/1 0) +((2A*/2B*/2C*/20) + (/2A*2B*/2C*,20) +(2A*2B*/2C*/20) + (/2A*2B*2C*/20) + (2A*2B*2C*/20))*(SWITCH*1 0) The spin frequency should be chosen to be visually appealing and should be high enough to ensure randomness of the dice. If Wi! use the "carry out" state of DICE2, then the spin pattern will only change once for every combination of the two dice. This will ensure randomness. The "carry out" of DICE2 is signal 2d; we do not need extra terms to derive it. OlCE2C Thus we have achieved our objective of adding the spinning option to the two dice. ((/2A*2B*2C*/20) +(2A*2B*2C*/20) + (/2A*2B*2C*20))*(/SWITCH*/1 0) + ((2A*2B*/2C*/20) + (/2A*2B*2C*/20) + (2A*2B*2C*/20)) *(SWITCH*1D) The Boolean equations iliat are obtained from the above truth table are as follows: SPIN1B = (SWITCH*2d*/S1D*/S1C*/S1B*S1A) OlCE20 = (/2A*2B*2C*2D)*(/SWITCH*/1D) + (2A*2B*2C*,20)*(SWITCH* 10) SPIN1C = (SWITCH*2d*/S1D*/S1C*/S1B*/S1A) Now you can use the iPLOS to program and test the device as explained in appendix C. At this stage in design, you have completed part C of the design which is to add a second DICE to the first one giving the the roll/no-roll option. SPIN1D =(SWITCH*2d*/S1D*S1C*/S1B*/S1A) SPIN2B = (SWITCH*2d*/S2D*/S2C*/S2B*S2A) SPIN2C = (SWITCH*2d*/S2D*/S2C*/S2B*/S2A) SPIN2D In part C of the design process, you have used one dedicated input which is the switch, and a total of eight output pins for the two pairs of LEOs, lA, lB, lC, 10 and 2A, 2B, 2C, 20 respectively. You have also used the RORF primitive, since the design logic was the same for DICE2 as it was for DICE 1. This leaves 3 dedicated inputs and 8 110 pins on the 5C06O device. = (SWITCH*2d*/S2D*S2C*/S2B*/S2A) Please note in the above equations that A, B, C, and 0 refer to both DICEI and DICE2. For DICE} the above set of equations would be lA, lB, lC, and 10. For DICE2 the above set of equations would be 2A, 2B, 2C, and 20· respectively. SO is the feedback obtained from IN 0 of both DICE I and DICE2 respectively. If the switch is not ON, the dice will not spin and a random pair of numbers will be displayed by the two dice; but, if the switch is ON, then the two dice will spin according to the truth table and Boolean expression given in Table 10. You can stop the design now or go onto part 0 which gives the next option, which is adding the spin. 4-45 inter AP-279 Table 9. 1hIth Table for 010E2 Input State (SWITCH*10) 2A 28 . Output State 10 20 2A 28 20 2D 2A Valid state 2B 20 20 'Invalid state REMAIN IN THE SAME STATE I, 0 0 () 0 0 0 0 0 0 0 0 0 0 0 ,0 1 0 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 .0 1 1 0 0 0 0 1 1 0 1 ,0 ' 0 0 0 0 O. 1 ' 1 0 1 0 1 0 0 1 1 1 1 1 0(1) 0 0 0(2) 0 0(3) 1. , 0(4) 1 0(5) 1(6) . 1 , CONTROL THE INVALID STATES 0 0 0 0 0 0 '0 0 0 1, 1 1 1 1 1 0 1 0 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0(1) 0(2) 0(3) 0(4) 0(5) 1(6) 0 O· 0 0 0 0 , Q .1 , CHANGE 10 THE NEXT VALID STATE· 1 1 1 1 1 1 0 0 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0(2) 0(3) 0(4) 0(5) 1(6) 0(1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0(1) , CONTROL THE INVALID STATES' 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 1 1 0 '0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 0 Note the extreme similarity between this truth table and the one given In Table 3. ' ,. 0 0 0 0 ,·0 0 0 '0 0 1 , 0 0 O· 0 0 0 0 0 0 0 0 Q 0 0 0 0 . ,0 0 0 0 0 0 0 0 ,0 0 0 ·0 0 0(1) inter AP·279 Table 10. Truth Table to Spin Two Dice Input State SWITCH A B spinning when the switch is on and displaying a number when the switch is off). Output State C A B C D SPIN1A D CHANGE TO THE NEXT VALID STATE 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 SPIN1C = (/SWITCH*1C) + (SWITCH*2d*/S1 D*/S1C*/S1 B*/S1A) + (SWITCH*/2d*S1C) SPIN1D ROLLING INTO A VALID STATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 = (lSWITCH*1A) SPIN1B = (/SWITCH*1B) + (SWITCH*2d*/S1D*/S1C*/S1B*S1A) = (/SWITCH*1D) + (SWITCH*2d*/S1 D*S1C*/S1 B*/S1A) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIN2A = (/SWITCH*2A) SPIN2B = (/SWITCH*2B) SPIN2C = (/SWITCH*2C) SPIN2D = (/SWITCH*2D) + (SWITCH*2d*/S2D*/S2C*/S2B*S2A) + (SWITCH*2d*/S2D*/S2C*/S2B*/S2A) + (SWITCH *2d*/S2D*S2C*/S2B*/S2A) At the end of the design step, you have completed all the design steps. You can now program the device using iPLDS. We have chosen the following two primitives for part D: The correct ADF file is included in Appendix D for your reference. You can refer to it to verify the ADF file you have created. Registered Output Registered Feedback (RORF) No output JK Feedback (NOJF) The programmed device can be tested on: For the dice spinning option you will use the RORF and for the dice not spinning option you will use the NOJF, while using the Logic Builder. • A PCB with slow clock For information on this board and on testing your design, please refer to Appendix C. When you add the spinning option to the pair of rolling dice, you obtain the following boolean equations. (These Boolean equations satisfy the requirements of the two dice It works! ROLL REGIS· TERS 'SPIN REGISTERS SWITCH 1 - - . - - DISPLAY +---...1.......---1""" ENABLE 2448 Figure 10. 4-47 intJ AP-279 *LATE NEWS FLASH* The PCBs have been made and we have units in the field. Now Marketing wants the design updated! Field trials of the dice showed that the battery needed to last longer. A simple mod to the design, chop the drive to the LEDs, extends the battery life. This is very simple using the EPLDs .. Reprogram the EPLD and test it. Imagine how .difficult it would have been without using EPLDs. I) Change the node name for the RORF Output Enables (Oe) from VCC to OE. 2) Insert an OENB (Output Enable Buffer) primitive to allow the logic array to drive the. output enables. 3) Include an INP primitive to connec( the output enable to an input pin. These changes can appear as follows: spinla, sla = RORF (in la, clock I, GND, GND, OE) OE = OENB (OEN) PART E: MORE POWER SAVINGS OEN = INP (OEN) This step of the design process is to modify the existing circuit to add the power save feature which will extend the battery life. This can easily be done by chopping the drive to the LEDs. Chopping the drive to the LEOs can be done as follows: Remember to include OEN in your INPUTS: declaration. The OEN input on the programmed part can now be connected to an appropriate clock signal to obtain the desired power savings. When you designed the circuit and implemented it using the iPLS, you have set the output enable (Oe) to VCC supply. This means that the LEOs are enabled 100% of the time. You can "chop" the drive to the LEDs with a conveniant high (above 50Hz) signal that will not be visible to the human eye. . CONCLUSION To reduce current consumption by the LEDs, modify the NETWORK: Section of the ADF as follows: . You should now have a comprehensive knowledge of Intel's EPLD and iPLDS family of devices. With this knowledge you will be able to implement designs using the iPLDS tools. Good Luck! 4-48 intJ AP-279 APPENDIX A: BASIC DEFINITIONS 4-49 inter AP-279 BASIC DEFINITIONS J-K FUP-FLOP - Output states synchronized with the clock pulse and controlled by the input signals, J and K. Logic Design - A systematic procedure for realizing specified terminal characterisitics of digital networks, at either the device or system level. ~~~~~~~~~~IJ~------1------------: CLOCKED FUP-FLOP - Output determined by the leading or trailing edge of clock pUlse. L.,9~-R T FUP-FLOP - Output changes value with every input clock pulse. J-K FLIP-FLOP COMBINATORIAL CIRCUIT - Output determined by current value of input signal. REGISTERED CIRCUIT quence of input signals. TFLIP-FLOP Output determined by se- Intel Schematic Primitive - One of the basic functional blocks needed to design circuits for Intel programmable logic products. Truth Table - A list of all the input-output possibilities of a logic circuit. D FUP-FLOP - Output determined by the input signal when clock pulse present. Boolean Logic - Describes logic that obeys the theorems of Boolean, algebra. The Boolean portion of a design is that portion which can be implemented in the AND-OR matrix. X~~_-_-_-:_-_-ltr:[:~~~~:::::::=: State Diagram - A diagram that shows the succession of output states through which the circuit passes as its input signals vary. INP - Input DFLIP-FLOP PIN-NAME c:::::::>------INP S-R FUP-FLOP - Output states synchronized with the clock pulse and controlled by the input signals, Sand R. Input Primitive GND-Ground ------------lfL____ ~-------------: GND S-R FLIP-FLOP Ground Signal Name 4-50 AP-279 VCC-Signal No Output JK Feedback (NOJF) Vee T Signal Name NOJI' F-----' EQN - Equation JK Output JK Feedback (JOJF) JOJI' o= ARBITRARY BOOLEAN EXPRESSION; ~---[~PIN-NAME EON Equation Name F---..I Registered Output Registered Feedback (RORF) Security Bit - A feature that prevents· the device from being interrogated or being accidentally programmed. RORI' Thrbo-bit - A control bit that allows you to choose the speed and .power characteristics of the device. If the inputs are static for approximately 50 ns and the Thrbo-bit is not programmed, the device will enter power down mode. When the input changes, the device will take an extra 3-5 ns to wake-up and react to the change. Programming the Thrbo-bit inhibits the power down. ;;;J--£:::> PIN - NAME F Macrocell - A basic building block of Intel's programmable logic devices. A macrocell consists of two sections: combinatorial logic and output logic. The combinatorial logic allows a wide variety of logic functions. The output logic has two data paths: one leads to the other macrocells or feeds back to the macrocell itself: the other is configured as a pin configuration acting as input, output, or bi-directional 110 port on the chip. No Output Registered Feedback (NORF) Node - A wire connecting two or more primitives in a schematic. NORI' F----' Pin - A node that is connected to an input or 1/0 primitive on one end and a pin of the chip on the other end. Product tem (P-Term) - Two or more factors in a boolean expression combined with the AND operator consitutes a logic product term. 4-51 AP-279 JEDEC Standard File - An industry-wide standard for the transfer of information between a data preparation system and a logic device programmer. 2. NETLIST CAPfURE - selecting components and specifying interconnections until all elements are specified. EPLD PROGRAMMING TECHNIQUES 3. SCHEMATIC CAPfURE menu driven environment. 4. STATE MACHINE - specifying states and conditional branches and also inputs/outputs to the state machines. You can enter your design in the following ways 1. BOOLEAN EQUATION - entering the design in BOOLEAN equations or expressions. 4-52 using a mouse and intJ AP-279 APPENDIX B: COMPONENTS LIST 4-53 Ap..279 COMPONENTS USED IN DESIGN • A push button switch to control the spinning mechanism In order to implement the EPLD program, you should use the following: • A 9-Volt DC battery source to generate the power . supply • An 5C060 EPLD • A pair of seven discrete LEOs (Dice I, Dice 2) • Capacitors CI = 0.1 MF, C2 = 0.01 MF • A timer to generate a clock signal (NE555) • Resistors RI = 390K, R2 = lOOK • A voltage regulator to generate a fIxed voltage of 5 volts (780S) • A PCB as explained in Appendix C 4-54 inter AP-279 APPENDIX C: PCB DESCRIPTION 4-55 intJ AP·279 Vee Vee + ' .r---------------------------- ---I . IN 7805 lOUT i Vee ------------t-------------· I VOLTAGE REGULATOR -.rl __ ~~ -------1 r---:tR1-------:t----• .< ! t---1- ! I~ ! Ii i 2> R2 2 555 ~ T • 1 kL------ ___________ J .. iF TIMER 22 21 20 19 11 DICE2 r-------------------------------------' ,_ • LED13,_ • LED14 : . .1::' · , : 1 I : Ij~ · LED11.: LED9 ,LED8 . .i LED12 LED10 - .--~----------------------------- 5C060 ..I J. -I ~U2 + L;T- 8 I i ~ I POWER: I 24 ' : 1 7 8 9 10 )~ II : ! ,F"L~!-_j DICE1 ._ J LEDS ,_ • LED7 1,- • LED4 ,- ~; LED5 1,LED2 LED3 LED1 ..__________________ 1 l__1!'!'__... ________ J r------------------------------- --I =·· ,- . i I J --t EPLD 2449 Figure C-1 You can test each part of your design using the PCB with a slow clock on it. The PCB is a board that is very specific to the dice example. The PCB is portable, approximately 2"x 3". All the components except for the EPLD are easily available commercially. A complete list of all the components that are required for the PCB is given in Appendix B. The circuit can easily be connected and tested using the circuit diagram given below. After the four steps of the design are completed, the PCB can be used to throw a pair of , dice' in any home games such as Monopoly etc. After the EPLD is programmed using the Logic Programmer, it can be inserted into the PCB. For design steps B, C, and D the push button switch can be used to generate the roll/no-roll or the spin/no spin option. inter AP-279 11:. _ . 116 ~.a:I:·'i.i". Ul 8 1110 8 : ~~iDil~i II0 ~ ;.ftgft'. lJs U2 INTEL Made In USA c 1986 2iJ 2450 Figure C-2 4-57 intJ AP·279 APPENDIX D 4-58 AP-279 ADF I:on PART' A: SINGLE DIGI:::. RULLING Lakshml Jayanthl DSD Appllcatlons 19, Febru~ry 1~8Q 51..;u60 Part A: IJ WE RULLI NG LB V&rS10n 8.0, PART: 5e060 B~sel1ne 1'lx, 9/26/8~ INPUTS: clC'ckl OUTPU1S: dlcelaal0,dlcelb~9,dlcelc~8.dlceld~7 NETWORf...: dle:ela,la dlcelb,lb d lcelc. Ie: d lceld. ld RORF (inla,clockl.GND.GND,VCCI (lnlb,c:lockl,GND,GND.VeCI RORF (1 nlc. c: lockl. GND .t3NlJ, vc.e I RDRF (lnld ,clc'c:.ld ,GND.GND,Vee) HOH~ clockl - INP (clockl) E.QUATlCJNS: lnla =(/lQ*lb*/lc*/ldl +(/Ja*lbOllcOl,ld' + (/1c,*lb"lc"ld) +(/l~*/lbOi/lcOl/ld); lnlb =(la*/lb*/lc"/ld) +(/la*lb*/lc*,ldl +(la*lb*/lc.,ld) +( / l~.lbOl·1 c*/ld) +(l.a*lb*lc·M·/ldl; lnlc: -(la*lb*/lc*/ld) + (/ la"lb*lc'''/ ld) +(la*lbOllcOi/ldl; lnld =(la*lb"lc*/ld); I£ND!I> 4·59 "P-279 RPT FUR PART A: SINGLE DlCE ROLLING Logic Optimi7ing ComplIer Utilization Report ***** Des51gn Imp lemented successful 1 y Lakshmi Jayanthi DSO Appl1catlcms February 19, 1~86 5C060 Part AI DICE ROLLING LB Ver'sion 3.0, Basel ine 17x, 9/26/85 58060 clockl GND GNU GND GND GND diceld dicelc dice1b dicela GND GND -: 1 -: 2 -: 3 -: 4 -I 5 -: 6 -: 7 -: 8 -: 9 -,110 -111 -112 24:- Vec 23:- GND 22:- GND 21 :- GND 20:- GND 19: -, GND 18:- GND 17:- GND 161- GND 15:- GND 141- GND 13:- GND **INPUTS** Name Pin clock1 Resource MCell '" PTerms MCells Feeds: OE Clear INP Clock CLKl reeds: Name F'l n Resource MCell '" P'Terms diee1d '7 RORF 13 11 8 MCells 13 14 15 16 RORF dicelc 21 8 14 13 14 15 16 dlc.e1b 9 RORF 21 8 15 18 1 ... 15 16 dlcela 10 RORF 16 21 8 1:::1 14 15 16 4-60 UE:: CleM Clock AP-279 Name MCell p'rerms 3 9 4 8 8 5 10 11 Q 12 Pin Resource 2 I::l I::l 11 18 14 ltJ 16 17 18 1 'I 2u 21 22 23 8 7 6 5 8 8 I::l 8 8 8 8 8 4 3 2 1 **PARf Ul ILI20\1 rUN** C'2Y. f-'lns 2~Y. MacroLe1ls 5Y. I-'terms NarE: Since part A is a simple design, the part utilization is very low. 4·61 Ap..219 AUF FOR PART B: SINGL.E DICE ROLL/NOT ROLL ---"':"'- - - ----- _._-------------------- --_ ..... _-_. Lakshmi Jayanth1 DSO Application~ February 19, 1986 5C060 PART BI DICE ROLL AND NOT ROLL LB Version ~.O. Baseline PART: 5(;060 17~, 9/26/85 I I' 9, dicelc;;)8,diceld;;)7 NETWORk: = RURF d1cela,la dicelb,lb d1ce1c,1c: ,dic:eld,ld = (in1a,cloc:kl,GND,GNlJ,VCC) RORF (lnlb,c:lockl,GND,GND,VCC) RORF (in1c,clock1,GNlJ,GND,VCC) RORF (inld,~lockl.GND,GND,VCC) clockl INP (clock1) sWltch INP(switch) E:'blUA TI ONS : inla =(/la*/lb*/lc*/ld*/sWltch) +(la*/1b*/lc*/1d*/switch) ~(la*lb*/1c*/ld*/switch) +(la*lb*lc*/ld*/switch) +(/la*/lb*/lc:*/ld*switch) +(/la*lb*/lc:*/1d*switch) +(/la*lb*lc*/1d*switchl +(/la*lb*lc*ld*swltch); in1b =(/1a*lb*/1c:*/1d*/sw.~cnl +(la*lb*/lc*/ld*/switc:h) +(/1a.1b*lc*/1d*/switc:h) +(la*lb*lc*/ld*/switch) ~(/1a*lb*lc*ld*/switch) +(la*/lb*/lc:*/ld*switch) +(/la*lb*/1c:*/ld*sw1tc:h) +(la*lb*/1c*/ld*swltch) +(/1a*lb*lc*/1d*switch) +(la*lb*lc*/1d*swltc:h); ln1c =(/1a*lb*lc*/ld*/switch) +(la*lb*lc*/ld*/switch) +(/la*lb*lc*ld*/switch) +(la*lb*/lc*/ld*switch) +(/la*lb*lc*/ld*switch) +(la*lb*lc*/1d*switch); inld =(/la*lb*lc*ld*/switch) +(!a*lb*lc*/1d*switch); END$ 4-62 AP-279 RPT FUR PART B: SINGLE DICE ROLLINor ROLL LoglC Optlmizing Compiler Utilization Report ... it**_ Deslgn lmpleml1'nted successfully Lakshml Jayanthl OSO App llcatlons Febru~ry 19, 1986 5C060 PHRT 1:1: DICE ROLL AND NUT ROLL LB Version 8.0. - ciockl 1 sWltch - 2 GNO - 3 GND GNO 5 GND - 6 dice1d 7 diceic 8 d 1 ce!l'b 9 dlcela - 10 GNlJ 11 GND -.12 - ... - - - B~sellne i:!4 23 22 21 20 19 18 17 16 1::' i4.181- - 17x, 9/26/85 Vcc GNu GND GND GND GND GND GND GND GND GND GND Feeds: Name Pln Resource clockl INP sWltc.h INP' MCell '" Pl"erms MCelis U~ Clp~r 'Llock elYl 13 14 1~ lb Feeds: Name F'lTi Hesc.urce MCell '" F'lerms MCells dlceld '7 RURF 13 PI 8 1:3 14 15 16 dlcelc 8 RORF 14 81 8 18 1 '+ 15 16 4-63 DE CleRr Ll~ck inter AP-279 RORF dlcelb 15 31 8 13 14 15 16 dicela 10 RLlRF 16 5/ 8 13 14 1:5 16 **UNUSED k~SOURC~S** Name MCel1 F'Te,-ms "'4 9 10 6 11 13 12 8 8 8 8 PIn Resource 11 14 15 16 17 18 8 7 6 !5 1''' 4 20 .3 21 2 8 8 8 8 8 8 '8 8 22 2Cj **PART UTIUZAI I UN*",' 27X 25X lUX PIns MacroCells Pterms NarE: Part B of the design gets more complicated, hence the part utilization of the pins, macrocells and the Pterms is higher. 4-64 inter AP-279 AUF FUR PART C: TWU DICE RULLING Lakshml .JoiIyanthi DSU Appllcat!Ons February 19, 1986 t;iC06u PHRT C: TWU DICE RULL AND NOl ROLL B Version 3.'), B :. q/26/8::i PART: 5l.:v6v INPUTS: cloc~l.cloc~2,swlteh~2 dlcela@10.dlcelb~9,dlcelc~8.dlceld~7.d'c~2oi1~ly,dlc~2b~20.dlC~2c~21.dlCF OU1Purs: 2d.j)22 NETWURr: dlcela.la dlcelb.lb dlcelc,lc diceld.ld RORF (inia,clockl,GND.GND.VCL) RORF (i nlb.c It.'ckl, GND,GND. VCl.:) RURF (1 nle, clock 1. GND.GND, VU.) RORF (lnld,clocll,GND,GND,VCC) dlce2a.2a dice2b,2b dlce2c,2c dice2d.2d RORF !ln2a,clock2,GND,GNU,Vl.:C) RORF (in2b,ciock2,GND,GND,VCC) RORF (ln2c,clock2,GND.GNU.VLC) RURF (ln2d,cloc~2,GND,GND,VCL) cloc~2 INP (ciockl) INP (clocl,2) Sw!tch INP (switch) clockl E:.UUATILlNS: lnl .. =1/1 .. M-/lbM-/lc·M-/ld*/swltch) r(la*/lb*/lc*/ld*/swltch) +(la*ib*/lc*/ld*/switch) +(ia*lb*lc*/ld*/switch) +(/la*/lb*/lc*/ld*swlteh) +(/la*ib*/lc*/ld*switch) +(/la*lb*lc*/ldM-switchl +(/ln*lb*lc*ld*~w!tch); ",1b =, >,,1.: =\ l-:"110 la +Cla*lb*/lc*/ld*switchl +(/la*lb*lc*/ld*swltchl +lla*lb*lc*/ld*switchl; lnlc =(/la*lb*lc*/ld*/swltch) +lla*lb*lc*/ld*/switchl +(/la*lb*lc*ld*/Swltchl +Cla*lb*/lc*/ld*switchl rl/la*lb.lc*/ld*swltch) +Cla*lb*lc*/ld*swltch); lnld -C/la*lb*lc*ld*/switch) +lla*lb*lc*/ld*.wltch); in2a =(/2a*/2b*/2c*/2d*/Cld*sWltchl) +(2~*/2b*/2c*/2d*/lld*swltch) , +(2a*2b*/2c*/2d*/Cld*switch) I +(2a*2b*2c*/2d*/(ld*9Wltch)) +(/2a*/2b*/2c*/2d*(ld*swltchl) +(/2a*2b*/2c*/2d*(ld*switch» +1/2a*2b*2c*/2d*(ld*sWltch») +(/2a*2b*2c*2d*lld*switchl); i n2b = C12a*2b*/2c*/2d*1 ( ld*swi tch) ) +12a*2b*/2c*/2d*/lld*sWltchl) +1/2a*2b*2c*/2d*/(ld*switch») +12a*2b*2c*/2d*/(ld*sWltch)I +(/2a*2b*2c*2d*/lld*sWltch») +(2a*/2b*/2c*/2d*lld*switch») +C/2a*2b*/2c*/2d*lld*switch)) +(2a*2b*/2c*/2d*lld*sWltch) +1/2a*2b*2c*/2d*lld*sWltchll +12a*2b*2c*/2d*(ld*sWltch)I; in2c =1/2a*2b*2c*/2d*/(ld*sWltch)1 rI2a*2b*2c*/2d*/(ld*switchll +1/2a*2b*2c*2d*/lld*sWltchl) +12a*2b*/2c*/2d*Cld*swltchl) +C/2a*2b*2c./2d*lld*sWltch)I +12a*2b*2c*/2d*lld*switchl); ,.12d = (/2a*2b*2c*2d*/lld*swi tch) ) +(2a*2b*2c*/2d*(ld*switch)); lnsla lnslb inslc lnsld lns2a ins2b ir\s2c.: I/switch*la); I/sWltch*lbl +112d*sWltchl*sld*/slc*/slb*/sla); I/SWltch*lc) +112d*sWltchl*/sla*/slb*/slc*/sldl; l/switch*ld) r(12d*swltchl*/sla*/slb*slc*/sld); (/swltch*2al; (/switch*2bl +112d*sWltchl*s2d*/s2c*/s2b*/s2a); I/sWltch*2c) ~CI2d*switchl*/s2a*/s2b*/s2c*/s2dl; Ins2d l/swltch*2dl +112d*sWltchl*/s2a*/s2b*s2c*/s2d); t=.NO$ 4·70 inter AP-279 Lt:1- f"UR F'ARl D: lWll DICE SPINNING shml J1J1nlc. splnld, sla sib sJc sld spln2a, s2a sp.Ln2b .. s2b spln2c, s2c «:;.pin2d, 0.;;2d (lnsla; ( 1 ns 1 b , ( ino.;;ic, (lnsld, c 1c.:.c: I; 1 • cloc.kl, clockl, clocl:1, 6ND, GND, GND, GND, GND. vce) GND. VLC) GND. vec) GND. vec) RURF ( i ns2a , RORF- ( i ns2b , RURF- ( 1 n0.;;2c , RORF ( 1 ns2d , cloc.1..2. clock2, clock2, clocl<2, GND, GND. GND, GND. GND. vc..e) GND. VCC) GND, vec) GNt>. vee) RURf RURFRORF RURI- ;. ...*it- C'd = NOR~ % it-* .. 2c = NOTF ( •• SG()06D , 'I, i>** .::>b : Yo it-* .. ..:.!a = y. "i>io ld = NORF ( •• Shll' ).3D. Yo io** Res{"tlrC:R, NUJF, it-** 'I, "** ";' NOR~ *"i> Yo NUR~ ;Fit-It 'I, NOJF, was mlnlml::ed te· Nl)flF *~. ~, "' .... 'I, "leiS mlnJmlZeci to NORI- ( •• SGon'70, clock2. GND, (,ND) RE?S.Ol tl ceo .. NUJF-. Was. mlnlml;"ed to NuTI- clock2. GNU. GND) Re5>ource. NOJ'F-, was mlnlmlzed to NURF ( •• SGno~u • clocl:2, GND. GNu) Re-s.ouY'r.:e .. NOJF, was ml nlml zed to NORF( •• SG01l4D. Re'!i: (.'1 l..ll C:f?, cloc~2. cloc~·l. GND, GNU) GND. GND) Hfi:oosC,ur c..e.-" NUJF. "las mlTllmJ.::ed tL' NOR. le '" NUf . This session assumes familiarity with the iPLS II Logic Optimizing Compiler (LOC). For detailed information on the LOC, refer to Chapter 4 of the iPLS II User's Guide. order number: 450196. Proceed as follows to implement the TTL macro design shown here: 1. Use a standard ASCII text editor to create the ADF shown in Figure 7 under the name DECODE.ADF. 2. Invoke the iPLS II Menu by entering: - 4. Answer the LOC promts as follows: Input Format? File Name? Minimization? Inversion Control? LEF Analysis? Error Message File IPLS 4-86 DECODE y N Y inter AP-311 co input of the adder for the first bit is not connected The LOC then asks: to any node in the macro call; in this case, the default value from the macro file (GND) is used to disable the input (No Carry). Do you wish to run under the above conditions [YIN]? Enter: Y The LOC expands the macros and compiles the expanded file to produce a JEDEC programming file (DECODE.JED). a utilization report file (DECODE. RPT). a minimized equation file (DECODE. LEF). and an error message file (DECODE.ERR). For tracability. a file called DECODE.SDF is created to show the expanded form of the ADF output by the Macro Expander. S. The LOC terminates execution with the following message: ~ AI - Bl CO ADRF AD SUt.I BO SUt.ll CYOUT~ CARRYI LOC cycle successfully completed You can examine the LEF file to see the minimized form of the design. The LEF shows the EPLD primitives used to implement the design. Macro calls are not shown. If you wish. you can also use LPS (Logic Programmer Software) to program a part. Leo ADRF A2 AD SUt.I B2 BO CYOUT SUt.l2 CARRY 292039-8 Figure 7. Schematic for Two-Bit Adder EXAMPLE 2: GATE-ARRAY MACRO Sample Session This section shows an example design using gate-array macros. To implement this ADF in an actual session. follow the steps described for Example I. substituting the name ADDER2 for DECODE. iPLS II produces a JEDEC programming file (ADDER2.JED). a utilization report file (ADDER2.RPT). a minimized equation file (ADDER2.LEF). and an error message file (ADDER2.ERR). For traceability. a file called ADDER2.SDF is created to show the expanded form of the ADF output by the Macro Expander. Circuit The design is a two-bit adder. Figure 7 shows the schematic for the target circuit. Figure 8 lists the gate array macro file for a single-bit full adder. Figure 9 shows the ADF for the target design that includes two instances of the single-bit adder macro call. Each instance includes a user-defmed instance name in the comment after the call (BTO and BTl). These instance names will be used to identify internal nodes. if the ADRF macro contains internal nodes. Note that inputs call the PTIN (TTL Receiver) macro while outputs call the PCOWP2 (2 mA CMOS Push Pull Driver) macro. During macro expansion. an EPLD INP primitive is substituted for the gate array PTlN macro and an EPLD CONF primitive is substituted for the PCOWP2 macro. This illustrates one of the differences between TIL and gate array macros. AORF(AO,BO,CO,SOUT,CYOUT) OEFAULT:(GND,GND,GND,,) "FULL ADDER" NETWORK: EQUATIONS: SOUT - AO' * BO' * co • AO' * BO * co' • AO * BO' * CO' • AO * BO * co; CYOUT - AD * BO ' • BO * CO • AO * CO; Once again. the connections between the two macros is dependent on the position of signals in the call. CARRYI from the first instance of the ADRF macro connects to CARRYI in the second instance of the macro. This corresponds to the CYOUT (Carry Out) from the adder for the first bit feeding the CO (or Carry In) input of the adder for the second bit. Note that the ENDEF 292039-9 Figure 8. Macro File for Full-Bit Adder 4-87 ROGER AUBLE INTEL CORPORAT.ION 2/27/87 1 A 5C060 2-BIT FULL ADDER OPTIONS: TURBO-OFF PART: 5C060 INPUTS: Al,Bl,A2,B2 OUTPUTS: SUM1,SUM2,CARRY NETWORK: PTIN PTIN PTIN PTIN (Al,A1) (Bl,Bl') (A2,A2) (B2,B2) PCOWP2 (SUM1,SUM1) PCOWP2 (SUM2,SUM2) PCOWP2 (CARRY,CARRY) ADRF(Al,Bl"SUM1,CARRY1) ADRF(A2,B2,CARRY1,SUM2,CARRY) " BTO " " BTl " EQUATIONS: ENDS 292039-10 Figure 9. ADF For Two-Bit Adder Using Gate-Array Macros data inputs to both latches are tied to VCC. When RD· and the chip enable are both low, the respective clock signal goes low. As RD' or chip enable go high, the rising edge of the clock signal triggers the register, driving the output high. EXAMPLE 3: MIXING MACROS AND EPLD PRIMITIVES This final example uses TIL macros together with standard EPLD primitives. Note that many Intel EPLDs do not support multiple product terms for register clocks. Therefore, the clock buffer primitive is driven by a macrocell configured as a COIF (Combinatorial Output-Input Feedback). Control signals (Clear and Preset) for many EPLDs also support only one product term. In this case, however, the NOR gate driving the clear input to the RONFs can be minimized to a single p-term. Thus a low on WR • and chip enable clears the respective latch to logic O.. (The intermediate macrocell for the Read function can be omitted for EPLDs that support two p-terms on register clocks.) Circuit The example circuit here is the 74138 macro used in example 1 with two of the outputs routed throughadditional combinatoria1logic and RONF (Registered Output - No Feedback) primitives. Figure 10 shows the circuit. CS2 and CS3 are qualified by two additional inputs (RD· and WR·) to set or clear two latches. This is a configuration commonly used in microcomputer systems, where control signals are set and reset based on the address and command signals but not on a data value. A read to the port decoded by CS2 sets output LCS2 (Latched CS2) high. A write to that same port clears LCS2 low. . The connections between the TIL macros and the EPLD primitive are made by assigning the appropriate names to the input and output nodes. The CS2 and CS3 signals from the first example are no longer outputs, but are simply inputs to equations that feed the LCS2 and LCS3 RONF primitives. . Figure 11 shows the ADF that implements the example circuit. This is the same ADF in Figure 6, with the addition of several primitives and equations. The used 4-88 inter Ap·311 A B C 74138 ENl EN2 EN3 YO Yl Y2 Y3 Y4 Y5 YCS YCE CEO CEl CE2 CE3 0 E CSO CSl RD·-----+~------_.~ >--+--SET2C > - -....-SET3 C >----LCS2 >---LCS3 292039-11 Figure 10. Schematic of Decoder Circuit with Latched Outputs 4-89 AP-311 DANIEL E. SMITH INTEL CORPORATION 2127/B7 1 A 5C090 DECODER WITH TWO LATC!'iED OUTPUTS OPTIONS: TURBO-DFF PART: IIC090 INPUTS: A,B,C,D,E,EN1,EN2,EN3,RD*,WR* OUTPUTS: SET2e,SET3e,YO,Yl,Y2,Y3,Y4,YII,CSO,CS1,LCS2,LCS3,CEO,CEl,CE2,CE3 NETWORK: INPUT (A,A) INPUT (B,B) INPUT (C,C) INPUT (0,0) INPUT (E,E) INPUT (EN1,EN1) INPUT (EN2,EN2) INPUT (EN3,EN3) OUTPUT (YO,YO) OUTPUT (Yl, Yl) OUTPUT (Y2,Y2) OUTPUT (Y3,Y3) OUTPUT (Y4,Y4) OUTPUT (YII,YII) OUTPUT (CSO,CSO) OUTPUT (CS1,CS1) OUTPUT (CEO,CEO) OUTPUT (CE1,CE1) OUTPUT (CE2,CE2) OUTPUT (CE3,CE3) 7413B(A,B,C,EN1,EN2,EN3,YCS,GND,YCE,Y5,Y4,Y3,Y2,Yl,Yd,VCC) 74139(YCS,D,E,CSO,CS1,CS2,CS3,GND,VCC) 74139(YCE,D,E,CEO,CE1,CE2,CE3,GND,VCC) RD • INP(RD*) WR • INP(WR*) LCS2 • RONF(VCC,SET2,CLR2,GND,VCC) LCS3 • RONF(VCC,SET3,CLR3,GND,VCC) SET2 • CLKB(SET2e) SET3 • CLKB(SET3e) SET2e,SET2e • COIF(ST2,VCC) SET3e,SET3e • COIF(ST3,VCC) EQUATIONS: ST2 • RD + CS2; CLR2 • I(WR + CS2); ST3 • RD + CS3; CLR3. I(WR + CS3); ENP$ 292039-12 Figure 11. ADF File tor Decoder with Latched Outputs port rue (LDECODE.RPT), a minimized equation tile ,Sample Se88lon (LDECODE.LEF), and an error message rue For traceability, a rue called LDECODE.SDF is created to show the expanded form of the ADF output by the Macro Expander. (LDECOD~.ERR). To implement this ADF in an: actual session, follow the steps described for Example 1, substituting the name LDECODE for DECODE. iPLS II produces a JEDEC programming rue (LDECODE.JED), a utilization re- 4·90 inter APPLICATION NOTE AP-312 June 1987 Creating Macros for EPLD Designs DANIEL E. SMITH APPLICATIONS ENGINEERING Order Number: 292040-001 4-91 in¥ AP-312 By following the macro file format described in this note, users can also create their own proprietary macros with an ASCII text editor. These macro files can then be stored in user-defined libraries by using Intel's Macro Librarian software. User-defined macros can be called from ADFs created by a text editor or by schematic capture software that supports user-defined symbols and that outputs in ADF format. User-dermed macros can optimize development of EPLD designs by modularizing the design process and by allowing the design process to proceed at a higher level than with EPLD primitives alone. iPLS II support for user-defined macros (see in Figure 1) includes the following: • MLIB, the optional iPLS II Macro Librarian for creating macro libraries from individual user-defined macro files. • a Macro Expander in the LOC that expands macro calls in ADFs with the contents of the corresponding macros from libraries. INTRODUCTION The iPLS II (Intel Programmable Logic Software II) Logic Optimizing Compiler includes a Macro Expander that supports the use of macros in EPLD designs. These macros can include TTL and Gate Array macros available from Intel, or proprietary macros developed by a user. This application note shows how to create user-defined macros and how to build macro libraries with Intel's Macro Librarian, an optional software package for use with iPLS -II. A design example also shows creation of a user-defined macro and its use in an ADF (Advanced Design File). Detailed information on using the TTL and Gate Array Macros in iPLS II ADFs are described in a companion application note, AP-311 "Using Macros in EPLD Designs", Order Number: 292039. This application note concentrates on creating macros; it assumes that you have read and understood the discussion on using macros in AP-31 1. This application note describes how to create macro files, store them in libraries with MLIB, and shows how to call them from ADFs created by a text editor. For information on creating user-defined macro symbols with schematic capture packages, refer to the appropriate manual for the schematic capture package you are using. SCHEMA II-PLD available from Intel supports user-defined symbols and outputs in ADF format. OVERVIEW iPLS II allows designers to include macro calls in design files to implement common circuit functions. Macros calls are subsequently expanded by the LOC (Logic Optimizing Compiler) into the ADF network and/or equation entries required to perform the desired functions. Macros can be connected together or used in conjunction with standard iPLS II EPLD primitives. SCHEMATIC CAPTURE h f SYMBOL LIBRARY IPLS TEXT EDITOR ADF ~ TEXT EDITOR ~ MACRO FILES I"'" I"'" MLiB ESPRESSO MINI.MIZER FITTER I---t ~ JEDEC FILE - f MACRO LIBRARIAN r--. MACRO EXPANDER n LOC MACRO LIBRARIES -.:;;: i4-- TTL.LlB - INTEL.LlB USER - DEFINED (·.LlB) 292040-1 Figure 1. Macro Support for IPLS II 4-92 inter AP·312 (SCHEMA II-PLD is based on SCHEMA II from Omation, Inc. The Intel EPLD Design Manager, also available from Intel, allows existing SCHEMA II users to design with EPLDs and macros.) 16207 (A,B,C,D,E,F,U,V,W,X,Y,Z) 16207 (B,D,A,R,Z,U,W,C,F,X,E,y) 16207 (Z,Y,X,W,V,U,F,E,D,C,B,A) MACRO FILES Note that this first line of the header forms the template used to call the Macro from the ADF. The Macro Expander connects ADF nodes in the macro call to I/O signals in the macro rue on the basis of position, not on the basis of node name. This section describes iPLS II macro rues. User-defined macro mes must follow the guidelines presented here to be successfully processed by the Macro Librarian (MLIB) and expanded by the iPLS II LOC Macro Expander. The second line in the header specifies defaults for inputs (VCC or GND) in cases where those signals are left unconnected. The DEFAULT: line must be included in the macro defmition rue, even when no defaults are used in the ADF. The keyword DEFAULT: is the first entry in this line. The default values for all signals follow immediately and are enclosed in parentheses. Input defaults may be VCC or GND. The position ofthe default value corresponds to the signal listed in the previous line. Macro ruenames follow DOS conventions. It is recommended that macro ruenames end with the extension .DEV, which is the default for MLIB. Only one macro can be contained in a macro file. Macro files are comprised of three sections: • Header • Network Section • Equation Section Defaults for outputs are blank, but a comma (,) must be present (place holder) for each output signal except the last. For example, the 16207 black box contains six inputs (A through F) and six outputs (U through Z). The first two lines for this macro might be: All macro rues must end with the literal "ENDEF". Figure 2 shows a sample macro rue for a proprietary part (16207), a "black box" containing random logic. 18207(A.B,C,D,E ,F ,u, Y,w,x, Y, Z) DEFAULT,(GND,GND,GND,YCC,YCC,YCC"",,) 16207 (A,B,C,D,E,F,U,V,W,X,Y,Z) DEFAULT: (GND,GND,GND,VCC,VCC,VCC"",,) EQUATIONS, U./(A*B), Defaults for inputs A through Care GND; defaults for inputs D through F are VCC. Defaults for the outputs are not specified, but the comma denotes the positions for those signals. V • I(/E • A • B); W-/(O*C*A*/E); X • 1(10 * E), Y_J(F*D*A). Z • F • IE; ENDEF Defaults should be chosen with care. Clears, Presets, Loads, etc. should be disabled in most cases. Enables should be enabled. Input defaults can also be left blank as long as those inputs are connected to nodes in the ADF that calls the macro, but it is recommended that they be specified in the macro rue. 292040-2 Figure 2. Sample Macro File for "Black Box" (16207.DEV) Header Headers for macro rues contain two lines. The first line includes the name of the macro function and a list of inputs and outputs for the macro. The second line contains defaults for the device. Network Section The NETWORK: section lists the EPLD primitives used to implement the desired functions. The Network Section follows ADF syntax rules. As far as possible, the macros should be implemented in equations to e1im~ inate concern about feedbacks and output enables. In the case of a circuit that requires macrocell registers, the feeback-only form of the primitive should be used so that the Macro Expander can make the correct pin connections. The following example shows this: The name of the macro can be a device number (16207, 83546, etc.), function name (ADDRCNT, CMDLO, etc.), or any name up to eight characters long. No spaces or comments precede the I}ame. Inputs and Outputs follow immediately after the macro name and are enclosed in parentheses. I/O signal names may be up to eight characters long, but may not contain pin numbers. For user-defmed macros, signals may be listed in any order desired. For example, any of the following entries are legal: OUT1 = NORF (INd,CLK,GND,GND) 4-93 Ap·312 During processing, the MaCro Expander connects the feedback to an output (if necessary) and supplies the required output enable node riame. The Macro Expander also eliminates unneeded Network and Equations entries if they are not'tised by an ADF. MACRO lIBRARIA,N The Macro -Librarian (MUB) is an- optional software package that combines individuallhaCro files into macro libraries. These libraries are in tum used by the LOC Macro Expander. MUB can be invoked from the command line, from command files, or from a: combination of both. Figure 3 shows a block diagram of the Macro If no network entries are required (i.e., a macro imple'mented entirely· in equations). the entire Network section may be, omitted, including the keyword NETWORK:. In many cases, equations alone can imple'ment the desired functions. ' Libfatian. - Syntax 'for MUB c~d lines is as follows: MLIB [-options] [@emdfile] [filel filel ••• ] -d, , directory. Displays l,lirectOl')' informatiQIl for the Iibr8ty being created. Equations Section The EQUATIONS: section lists the Boolean equations for the desired functions and follows ADF syntax rules, with one exception; intermediate equations are not permitted in macro files. If no. equation entries are te'qiJired (i.e., a macro implemented entirely in the Network -Section), the entire Equation section may be omitted, including the keyword EQUATIONS:. -v verbose. Print status during processing. When not specified, status messages are suppressed. -I lib list. Lists the contents of existing m~ro library to console. This option may not be used while building a library. lib name of the target macro library. MACRO. LIB is the default when no name is speCified. TTL.LIB au,d tNTEL.PB are re_served for Intel librarieS and,may not be used. -0 Comments and Wta1te Space - - Comments can be placed anywhere in a macro file except before the name and signals on the fltSt line. Comments must be enclosed in percent signs, as follows: -s string include .version stamp in macro Iibrary.- The version string can be up to 7 characters long: "V1.00" is the default stamp. % THIS IS A SAMPLE COMMENT % White space can appear on any line except the, first two lines. T£XT EDITOR TEXT EDITOR .... MACRO FILES r-+ COMMAND FILE .... - T MLiB ~ , - .... MACRO LIBRARY - LIBRARY LISTING 292040-3 Figure 3. Macro Ubrarlan Block Diagram 4-94 inter AP-312 -c string include copyright string in macro library. The copyright string can be up to 61 characters long and, if blanks are used, must be contained in quotation marks, for example, "texta textb". @cmdfile name of command file. The command file can include options and macro filenames. The @ symbol must precede the filename. file I . .. name of device files to be included in the macro library. Separate files by spaces. Note that the -1 option cannot be included in an MLIB command file; it can only appear on the command line. The -1 option lists the contents of existing libraries; it does not list library contents while building a library. -0 PROJA.LIB " macro library name" -v -8 V1.50 " version number" -c ·Copyrlght (e) Date. Your Company, Your Name" copyright Information" -d " display directory" " For example, the following command line: Include the follOWing macros" INPUT.DEV 74S7.DEV 74151.DEV MLIB -v -s 2.00 -0 USER. LIB @USERLIST OUTPUT.DEV 740S.DEV 74138.DEV 7413S.DEV 74157.DEV 74251.DEV 292040-4 creates a library called USER. LIB that includes all the individual macro files contained in the command file USERLIST. MLIB displays status messages as it processes the macro files in USERLIST (-v). The library is created as version 2.00 (-s). Figure 4. Sample Command File for MLIB The command line to process the file shown in Figure 4 is as follows: MLIB @SAMPLE Macro library filenames follows DOS conventions and should end with the extension .LIB to be recognized by the Macro Expander. INTEL.LIB and TTL.LIB .are reserved and may not be used. where SAMPLE is the name of the command file. To list the contents of PROJA.LIB after creation, invoke MLIB as follows: USERLIST is the name of the command file and must be preceded by the @ symbol. The command file is simply an ASCII text file that can be modified to contain any number of macros desired. MLIB processes the entire list of macros on each invocation. To add a new macro to an existing library, add the name of the macro to USERLIST, and create the new library by entering the command line shown above. Command file names follow DOS conventions. MLIB supplie~ a .DEV extension if no extension is specified. MLIB searches first in the current directory, then along the DEV environment variable, and finally along the PATH environment variable for the files. MLIB -1 PROJA.LIB This command"line li~ts the macros in PROJA.LIB to the screen. The DOS file redirection capability can also be used to create a disk file listing the contents of macro libraries. For example: MLIB -1 PROJA.LIB > PROJA.DOC SAMPLE SESSION: COMMAND DECODER USING MACROS In order to connect inut and output primitives, the files INPUT.DEV and OUTPUT.DEV must be included in at least one of the libraries. These files are contained in the TTL and Intel Gate Array macro libraries (TTL.LIB and INTEL.LIB, respectively). Decoding logic is one common function implemented by programmable logic devices. The target circuit for this example is a device that decodes microprocessor command signals in selected address ranges. The target application and decoder requirements are as follows: • The target application is a 16-bit microcomputer system with I-Megabyte of memory and about two dozen I/O ports. • The memory is divided into shared memory (lower 512K bytes) and local memory (upper 512K bytes). Shared memory resides off the processor board and requires active low memory command signals. Local memory resides on-board and requires active high memory command signals. • I/O ports are also split between on-board devices requiring active high signals and off-board devices requiring active low signals. I/O devices between the address range FOOO-FFFFH are on-board; devices below that range (OOOO-EFFFH) are off-board. Figure 4 shows a sample MLIB command file that includes options, the library name, and the names of seven macro files to be included in the library in addition to the INPUT and OUTPUT macros. The format of the command file is free form. Note that comments can be included in the command file and must be contained within percent (%) signs. 4-95 AP,~312 \ • All interrupt requests are resolved by an on-board interrupt controller.·Therefore. only an/active high on-board interrupt' acknowledge signal is needed. • On-board control signals are always high or low. never three-lItated. Off-board control signals are three-stated when not being used to execute a bus cycle. An external bus arbiter accepts a request signal from the command decoder and.· after gaining control of the bus. sends address enable and com. mand enable signals back to .the command decoder. Figure 5 shows a block diagram of the application. including the target EPLD design. The three functional blocks t() be included in EPLD are highlighted (not shaded). the Off-BOARD SYS"{EM BUS ADDRESS AND DATA.BUS ...... , .. 292040-5 Figure 5. Block Diagram of Target Circuit and Application 4-96 inter AP-312 Creating the Macro Building the Library Figure 6 shows a schematic diagram for the active low command decoder implemented with OR gates (low inputs enable the outputs; high inputs disable the outputs). Figure 7 shows the macro file that implements the circuit (CMDLO.DEV). This file was created with an ASCII text editor. Used as is, it provides the active low outputs for the design. With inputs RD, WR, and INTAIN inverted, it also provides the active high outputs for the design. This design uses CONF primitives to implement the three-state outputs in the macro. As an alternative, equations alone could have been used with the CONFs included in the ADF.. Use your text editor to create an MLIB command file that includes CMDLO.DEV, INPUT.DEV, and OUTPUT.DEV. The following example shows a sample command file named MACLIST. -v % show status % -c "1987, AP-312 Sample Macro Library" -0 AP312.LIB -d % show the list % , % include the following macros % CMDLO.DEV INPUT.DEV OUTPUT.DEV RD -;:::~:::r~ Invoke the Macro Librarian with the following command line: MRD MLIB MWT The Macro Librarian processes the three macro files and stores them in a user library named AP312.LIB. The library contains the copyright statement "1987, AP-312 Sample Macro Library". When processing is complete, MLIB returns control to DOS. lOR MIO:=~=~~_; lOW Creating the ADF eMDEN INTAIN --------I-f @MACLIST Figure 8 shows a schematic diagram for the target circuit. Figure 9 shows the ADF for the circuit (COMCODE.ADF), which invokes both instances of the CMDLO macro and contains equations used to enable the decoders under the proper conditions. The ADF signal named ONBEN (On-Board Enable) enables the active high decoder). The AEN (Address Enable) input to the on-board decoder is left unconnected. The default (always enabled) will be used. INTA AEN------......I 292040-6 Figure 6. Schematic Diagram of Command Decoder CMDLO(MIO.RD.WR. INTAIN.CMDEN.AEN'.MRD.MWT. lOR. lOW. INTA) DEFAULT:(GND.VCC.vcc.VCC.GND.GND ••••• ) NETWORK: MRO _ CONF(MROc.AEN) MWT _ CONF(MWTe.AEN) lOR _ CONF(IORe.AEN) lOW - CONF(IOWe.AEN) INTA _ CONF(INTAIN.AEN) EQUATIONS: MRDe • MWTe lORe. lOWe - IMIO + RD IMIO + WR MIO + RD MIO + WR + + + + CMDEN; CMDEN; CMDEN; CMDEN; ENDEF 292040-7 Figure 7. Macro File for Command Decoder (CMDLO.DEV) 4-97 inter AP-312 NINT INTAIN· MIO ~/IO· orr- BOARD DECODER INTA ,~RD NRD RD· ~WT NWR WR· lOR lOW Vee ~IO ~RDC· RP ~WTC· WR IORC· lowe· C~DEN· AENl A13 Ar AE UPPER AD AC NA13 >-t:::> orrBDEN* NUPPER 292040-8 Figure 8. Schematic Diagram for COMCODE.ADF 4-98 inter DANIEL E. SMITH INTEL CORPORAT, ION 1117187 1 A 18209-001 COMMAND DECODER OPTIONS: TURBO-oN PART: !!COBO INPUTS: MIO, AD, WR, OUTPUTS: INTAIN. CMDEN, AEN1. A13, AF, AE, AD. AC MRD, MWT, lOR, lOW, INTA, MRDC, MWTC, 10RC, lowe, OFFBDEN NETWORK: INPUT(MIO,MIO) INPUT(RD,RD) I NPUT(WR,WR) INPUT(INTAIN,INTAIN) I NPUT(CMDEN,CMDEN) INPUT(AEN1,AEN1) INPUT(AI3,AI3) INPUT(AF,AF) INPUT(AE,AE) INPUT(AD,AD) INPUT(AC,AC) OUTPUT For user-defined macro libraries that are regularly accessed, the IPLS variable can be set in an AUTOEXEC.BAT file. 2. Invoke the iPLS II Menu by entering: IPLS 3. Invoke the LOC from the Main Menu by pressing . 4. Answer the LOC prompts as follows: Input Format? File Name? COMCODE Minimization? Y Inversion Control? N LEF Analysis? Y Error Message File COMCODE.ERR Do you wish to run under the above cOnditions [YIN]? Enter: Y The LOC expands the macros and compiles the expanded file to produce a JEDEC programming file (COMCODE:JED); a utilization report file (COMCODE.RPT), a minimized logic equation file (COMCODE.LEF) and an error message .file (COMCODE.ERR). For traceability, a file called COMCODE.SDF is created to show the expanded form of the ADF output by the Macro Ellpander. 5. The LOC terminates execution with the following message: LOC cycle successfully completed You can examine the LEF file to see the minimized form of the design. The LEF shows the EPLD primitives used to implement the design. Macro calls are not shown in the LEF. If you wish, you can also use LPS (Logic Programmer Software) to program a part. Tools for OptimiziJIB PLD Designs Alan J. Coppola Tool Architect Illte} Corporiltioll M/SEY2-11 5200 HE EJilm YOIlll6 Pkwy. Hillsboro, OR 97123 (503)681-2177 1Dtr°ductiPP; The purpose of this paper is to describe a design methodology for Programmable Logie Devices(PLD's) and to survey current PLD optimization techniques. 1. Perspective: Where do PLD's fit in? The use of Programmable Logic Devices(PLD's) represents a middle ground in logic design. The two common approaches to logiC implementation in today's market are Board Design methods(building a solution from a selection of pre-fabricated standard parts -TTL/SSI/MSI) and ClIstom/Semi-Custom design methods(fabricatmg a custom logic clup to solve the problem at hand, and lhcn building a much simpler board). With the Board Design approach, PCB's carry the fruit of a deSigner's labor to the customer. Many little black boxes and other electrical circuit components make up the brunt of a PCB's load. Many times there are large island,s of functionality to be connected together via encoding/decoding and timing circuits. The islands of functionality (ie. microprocessor, mlCTocontroller, RAM. EPROM, transciever, etc.) all have different protocols, and all speak different languages at different speeds. Integrating the major devices of a board together mvolves much "glue" logic. The typical designer spends time and effon looking through a TTL parts catalog to find the best fit for a design based on functiOnality, performance and price. After a preliminary function-based board IS laid out, modification ~asses are made based on the parts needed and their avallability. Large deslgns increase the length and risk of thiS process. Even though most ma)or CAD vendors are addressirlg the problem 01 board deSign, , simulation, test and interface with the Custom/Serm-Custom arena, board design and manufacturing tools are rapidly becoming the prirnarypractiC 1organ's InverslOn, In AND/OR tvpe PLD alChltectures, IMtrl inversIOn control In the I/O macrocells, refm to logically Inllertmg an output signal phase m such a way ttlat trle number of p-terms realiZing the complement functIOn IS less trlan the ongmal funCtIon. ThIs can save the user from an un·solvable p-term fitting problem due to too many p-terms when uSing one sense of an equation. For deVices With Single output macro cells, lil'.e PALs, and EPLDs, the complement of the slrlgle output equatton IS computed and trlen mlTl1f!llZed. The sense of the equ~t1on Wlttl the least nurnber of p-terrns IS trlen the one that 15 Implemented m the deVice under programmmg. ' Fitting and Pin Assignment The flttlflg and pin assignment problem refers to complhng a deSign file, and havmg the compiler automatically choose those de\~ce resources arid PinS that ttle Ilser ,did not assign In the deSign file. In t.he past delllce architectures have been Simple enough and small enough so that flttmg and pm assignment 'Nere not a problem for the user. Now, \'IIt.h mcredslng Size, compleXity, and non-homogeneity of the deVICe aI chitecture, a heurlstlc CAr, tool, "!hlch IS hke arl automatic place and rOllte tool, 15 a neeesslt\' If a deVice aI chitecture IS homogeneous '''Ith respect to structure and resources, flttmg IS not a problem, as there IS no contention for resources or placement ot those reSO'.\fces. Flttmg 15 a problem when there are multiple clocks and wpes of elocy.;, multiple deVice seCtlons(lIf.e quadrantsJ, "ar'llng numbers ot pterms per quadrant, product term sharing dnd steenng, mput pms, I/O macrocells 01 varymg t'lpes, or buned reglstel S. The greater ttle number' and size of the feature 5, the greater the flttmg problem. ,Without a tool to help, the deSigner must do the fitting b'l hand, leading to errol sand r.c,t finding an allow.:lble flt Some of the large scale de"lces that exhibit these problem" are Inte1'5\Altera'sI5CI21IEP1210J and 5C'180: EP1800j. The IIttmg ,:lnd automatIc pm a"!lgnroent tools ollPLDS reheve the user from havmg to deal 'Nlth thiS problem Future PLD tools will depend more arid more on logiC rrul11lll1Zc1t1On. Just as a high-Ie'lellanguage programmer looks 4-103 3. Future, PLD Optimization Tools Conclusion: This section descnbes new directions lor PLD development systems optimization tools, Optimization tools must be near transparent to the user to get universal acceptance. 01 the lour optimization tools mentioned above, all but the FSM compiler tool sausly that critenon. We have surveyed the reasons tor, and components of PLD developfl)ent systems, with emphasis on the Hardware , Description Languages, and optimization methods in such systems, The conclusions ot the survey are that the HDL's are the essential cornerstone ot any PLD system, and will control the tuture direcuons of any new PLD development tools. The second conclusion is that two-level logic nunimlZaUO\l, FSM compiler, and automattc fitung tools are the most important in the PLD optimIzauon area. Also, recent breakthroughs and pub~c aVilllability ot heunstic mininuzers pomt to increased use of such tools, Finally, tuture directions, and an expandirIg market mdicate a wide range of new tools wi)! appear, The key emphasis will be on makmg them transparent to the user, who, when all is said and done, knows how to deSign logiC best! There are ba'sicaDy two types, 01 optimization tools which will appear in the PLD arena, The Illst type are tools which are port~d Irom, or interfaced to the Custom/Semi·Custom environment The current logic description and synthesis tools of silicon compliers and Custom/Senu·Custom CAD tools tit mto this classificauon. The second type are new tools which Will address the architecture·specifiC optimizatIOn issues. The tools in this group will use methods based on logic optimization and expert· system techruques,These two methodologies will be applied to takmg abstact specifIcations and realiting them automatically into multiple devices, or in takIng multiple abstract specifications and realiting them m one delllce. Portation of Custom/Semi-Custom Tools: Avallable ideas ready for portmg to the PLD enwonment down the HDL path include implementing a subset of VHDL(VHSIC Hardware Description Language)[5], and halllng the compiler produce an EDlF(Electromc DeSign Interchange Format) [6] mtermedlate tormat In thiS way, interfacing with other toolboxes of any type wlI1 be easier, New delllce support will also be easier, given the genenc nature of VHDL, Using VHDL would also standardize an HDL, and allow deSigners to leam one HDL wluch Will last tor a long time. Also, PLD tools wluch interface with the Custom/Senu·Custom toolset mvollllng board deSign, testing and manufactunng IS needed now, and IS bemg addressed by the malor CAD vendors, Standardlzauon, ~ke VHDL and EDlF will. eventually, lower the cost of these interfaces, The new logic rrrinmuzation algonthms, ~e Espresso, and new state assignment tools, lIke KISS[7] and STASH [8]can be used m the PLD environment The algonthms and methods at tools Involving placement and routing can be applIed to the fitting/pin assignment problem Qn the logic syntheSIS side. new too,!s which combine expert·systems WIth multi-level logic optlmizatlon can be applied to PLD devices which allow mulu·levellogic to be easily implemented. The key pom~ megardless at the actual tools tram the Custom/Senu·Custom arena which are proctuctized IS that the user have an essentially transparent view at any new optimization tools. ' References [1] R. Rudell and A. SanglOvanru-Vmcentell~ "ESPRESSO·MV: Algonthms tor Multiple Valued Logic Mmimization", m Proc. Cust Int Clre. ConI" IEEE, Portland, OR, May, 1985. [2] M,R. Dagenais, V,K Agarwal arId N.C. Rumin, "McBoole: A New Procedure tor Exact Logic Mmimizatton", IEEE Trans. on CAD, Jan. 1986, 229·238. [3] tv!, Bartholomeus and H,D. Man, "Presto-ll: Yet Another Logic MinimIZer for Programmed l.,oglc Arrays", Proc. Int Symp. Clre, Sys!" June 1985.58. [4] R. Rudell, "Multtple·Valued Logic MIlJimizanon tor PLA SyntheSIS", M.S, TheSiS, University at Calltomia, Berkeley, 1986, [5] V. D, Agrawal, ed,. "VHDL: The VHSIC Hardware DesClipnon Language", IEEE Design arId Test of Computers, Apnl, 1986, [6]lP. Eunch, "A Tutonal Introduction to the Electronic DeSign Interchange Format", In Proc. of 23rd Design Automation Conference. July, 1986,327'333, [7J G, DeMlcheh, R.K Bral'lon, and A. Sanglovanni·Vincentelli, "OptiinalState Assignment for Finite'State Machines", IEEE Trans. on CAD, July, 1985, 269·285, a State ASSignment Heuristic", In Proc. of 23rd DeSign Automation Conference, July, 1986,643-649. [8] A. J. Coppola, "An Implementation ot Once a PLD is manufactured, the tuncuonallty cannot be changed. This fact leads to the belief that tools can be created which map logiC, which IS too big or too slow, mtD multiple deVices by doing automatlc logic partiuoning, The converse problem at fitung multiple chunks of communicaung logiC into one deVice may also be addressed Tools to fit multJple state maclunes mto one del/Ice, or to partition a schematic or FSM mto tl}lO Or more de'llces 15 a tirst step, For example, the Dice Exarnple(F'lgures 1-3) has three small state maclunes, wluch are mtegrated mto one deVice and deSIgn file, Expert·systems can capture the rules for partltlomng, and the database of all allowable delllces, whlle OptimizatIon techmques can make the expert· systems "lark as well as. or better than a logiC deSigner. 4-104 The oic. Exampl. shows III. usefulness of logic minimization. Figuro 2 shows III. FSM Languag.(SIaIe Machin. File) r.pros.ntation of III. oic. Example und.r III. iPLDS 5,sltm. Figuro 3 shows III. ADF cod. which rosulled. as an inttrm.dillle sloP. in III. compilation proc.ss. Dice Example Description Problem: 0.51gl1 a circuillllat will rolllWo dice. PU5h a 5witch to SIirt III. die. rolHng. Wh.rI III. switch is rol"sod. a (pseudo) random 5et of numbers will b. displayed. Th. oxample is written u5ing III. FSM compiler module of iPLDS. Thl5 oxampl. is a modification of an Disting Application Note[AP279] de5ign. which i5 wrm.n ,in AoF languago. The Dic. Exampl. p5eudo-randamly rolls lWa die.. The Dice Exampl. i5 comp05.d of lllro. FSM5·. Th. fir51lWa are .ss.nlially UlHOaUlll1!rs. which count from one to six. using lIIe notation groups of one or 1W0 LEo·s. tor each of four OUlpUls. to roPro5.nt III. six f~es of a die. A plClUr. which indicales!he LED groupIngs. by lo51mg lIIe OUlpUl signal name IItlII to III. LED controlled by it is given in Diagram 1. The groupings for bolll di. are identical and h.nc•• tislod nOld to .ach olll.r. • Th. targM devic •• !he 5C.... has I. I/O macroc.... bUl .ach macroc.1I has only .naugh room for 8 p-Itrms. Thero are 11 .quationsllla! rosull frollllll. Die. Example d.sign. Four for .ach di•• to control !he LED's. and lllro. frotn III. 51ate variables of III. lin.ar F••dback Shift F\t!gisltr. W. pros.nt a btforo and alltr minimization labl•• showing lIIe efleOl of III. minimization and III. aUlDmatic o.Morgan's Inversion SlIp. Th. lIIird machine g.nerales a shorl pseudo-random bit 5.qunce by imp!em.nting a Un.ar F.edback Shift F\t!gi5Ioo1LFSR) • willi lllroe r.gI5Ior5. Th. p5eudo-random bits.qu.nce5 from III. LFSR are u5.d to add probabilistic transition5 to III. UIHOOUlll1!r mod.1 of each d, •. The implementation of lIIe LFSR i5 by 51raigh! m.morizallon of lIIe s.quene •• by means of III. 51aIe variabl.s of an up-counter. Id,2d Ie, 2& ••••• .la,2a • Ie, 2& InpUls !Herms !Herm5 btforo IIItr min min Sv3 d Sv2 d Svl.d 2d.d 3 3 3 & 3 3 3 3 2o.d 5 6 6 2b.d 2a.d ld.d lc.d lb.d h.d Dice LED Enuding Ib,2b Equation 6 6 6 6 • I 10 3 , 5 10 2 2 2 3 4 4 6 3 4 4 7 A n.c.ssary condition to fit into III. 5COIO is ilia! all of III. numb.rs in do. 1m column be no lIIor. doan 8. as III ... art no mar. doan , p-ttrms conneCled to any lIIacroc.lI. This particular Drobl.m look 2 minUlts of CPU tim. on an 'Mhz PC/AT. Reducing do.s••quations by hand••v.n for lhis 5impl. oxampl•• would b. difficult. The ne.d for do. aUlDlllatic mInimizer is cl.ar in dois oxampl.. WilhaUl iI. a d.sign.r would .iIII.r hav. to r.duc. !he .qatians rosulting from dot FSH Languag. by hand. or not us. an FSH Language a! all. and do doe whol. d.sign using hand-craft.d mtlhads. Id,2d Ib,2b Die I Signals: I a, I b, 1e, 1d Die 2 Signals: 2a, 2b, 2e, 2d Figure I, 4-105 Dice Example FSM language(SMF) Description " " Stile variables an used as oUIpUIs 10 die. Each _ encodes Ihe set ot LEO's 10 tight 10 reuze 111.. die value. Alan COIIPClI. _I _ Julp 21. 1981 Part No.: LUVegas VU.3.0 SCOI. AIIh INir of die L8 Version 4.01. Baseline 21.1 4/9/86 PARr: SCI.O - " " " No pins assigned: AulDaalie Pin Assignment IIId Filling" Coin2 is • pseudo-ranclom coin. which eomrols 1IIe uP"Counter Iransilions. so 1IIat lIIe _die. roll is pseudo-random. INPUTS: elkl. clk2. Go OUTPUTS: 1.. lb. Ie. ld. 2.. 2b. 2e. 2d Reset: IIGD Then One One: II Go~oin2 Then Two Two: If Go-Coin2 Then Three Three: If Go-Coin2 Then Four Four: If Go-Coin2 Then Five Five: If Go-Coin2 Then Six Six: II Go-CDin2 Then One 1ETW0fU(: olkl = INPlelk11 .1112 = INPlclk21 Go = INPIGDI ;n" lerm LFSR. implemenled b, S1Dring sequence in variables. which as tlipping oDins. stale act " MACHINE: LFSR CLDCK: elk2 STATES: [Coinl CDin2 Coin3] .(008) 51 (108)52 [11-8) 53 [OI1J 54 [1 01J 55 [010] sa 56 " STATES: [1.1b Ie ld] Reset (0 0 0 0] One -[1000] Two [0100] Three [I 1 00] Four [0110J Five [1110] Six [0 1 1 I] MACHINE: OilJ\DUJ " " DuPlicate ot OieJlDl1.J machine. except tor . a ditferent die. using a different pseudo-random cOin. (101) Stale equations are: CLOCK: clk2 STATES: ResetOi.2 Coin2 := Coinl Coin3 := Coin2 CDinI := /ICDin2 lIDr Coin31 OneOie2 TwoOie2 ThreeOie2 FDurOie2 FiveOie2 SixDie2 " SI: SI SI: 52 S2: 53 S3: 54 S4: 55 55: [2. 2b 2c 2d] [0000] [1 000] [01 00] [I I 0 0] [0 1 1 0] [1 1 1 0] [0 I 1 1] ResetOie2: If Go-CDin3 Then OneOie2: If Go-Coin3 Then TwoOie2: If Go-CDin3 Then ThrteOie2: If Go-Coin3 T~en FourOie2: If Go-CDin3 Then FiveOi.2: If Go.CDin3 Then 5ixDie2: If Go-Coin3 Then 56 56: SO MACHINE: OieJ\D11.J CLDCK: elkl ENDS Figure 2. 4-106 On.Oie2 TwPOi.2 ThretOie2 FourOie2 FivtDie2 5ixDie2 OneOie2 Dice Example Hardware Description language(ADF) " "" " Bool.an Equations lor Slalo Machin. Alan Coppola- 101.1 July Zl. 1986 Port No.: LasVogu V.r.3.0 5C060 Roll a pair of dio LB Version 4.01. Buolin. 21.1 4/9/86 SHV Vorsion 1.01 BETAl Buelino Z6.1 4/3/86 PART: 5C060 INPUTS: elkl. elk2. Go NETWORK: elkl = INP(elkl) clk2 = INP(clk2) Go = INP(Go) " Throo I,rm LFSR. implomomod by sloring sequonce in 51alt variabl.s. which acl u flipping coins. " " I/O's lor Slalo Machine "LFSR" " Coinl = NORF\Coinl.d. elk2. GNO. GNO) Coin2 = NORF(CoinZ.d. clk2. GNO. GNO) Coin3 = NORF(Coin3.d. elk2. GNO. GND) I/O's lor SIal. Machino "Dio_RoIU" la. la = RDRF\1a.d. clkl. GND. GND. VCC) lb. lb = RORF\1b.d. elkl. GND. GND. VCC) le. lc = RORF(le.d. elkl. GND. GND. VCC) ld. ld= RORF(1d.d. clkl. GND. GND. VCC) . I/O's lor Slalt Machine "Di._RoIU" " Za. Za = RDRF\Za.d. clk2. GND. GND. VCC) 2b. Zb = RORF(Zb.d. clk2. GND. GND. VCC) Zc. Zc = RORF(Zc.d. clk2. GND. GND. VCC) Zd. Zd = RORF(2d.d. elk2. GND. GND. VCC) Current Slale Equations lor "Di._RolI_1" R.s.I = la'-lb'-le'-ld'; On. = la-,b'-'e'-,d'; Two = la'-,b-lc'-,d" Three = la-lb-,.'-li'; Four = 1a'-' b-1 c-l d" Five = la-,b-'c-,d'; • Six = 1a'-lb-le-ld; " " h.d = One.n + Threo.n + Five.n. lb.d' = Ono.n + R.sOl.n; 1e.d = Four.n + Five.n + Six.n; ld.d = Six.n; " " N.", Slale Equations for Slale Machin. "Die_RolLI" One.n = Six - Go - CoinZ + One - (Go - CoinZ)' + ResOI- Go; RosoI.n = R.sel - (Go)'; Three.n = Three - (Go - CoinZ)' + Two - Go - CoinZ. Four.n = Four - (Go - Coin2)' + Three - Go - Coin2; Five.n = Fi.e - (Go - Coin2)' + Four - Go - COlOZ; Six.n = Six - (Go - CoinZ), + Fi.o - Go - Coin2; " Booloan Equations for Slate Machino "Dio_RoII_2" "" " Curronl Slalo " SV DefiRlng Equalions for Slale Machine "Die_RoILZ" Za.d = OneDieZ.n + ThreeDioZ.n + Fi.oDi02 n; Zb.d· = OnoDi.Z.n + R•• etDio2.n. 2c d = FourDie2.n + FivoDieZ.n + SixOie2.n; Zd.d = SixDoo2.n; " ~OJd Bool.an Equations lor Slale Maehino "LFSR" Slate Equations for Slalo Machmo "Die_RolI_2" OnoDi.2.n = SixDi02 - Go - Coin3 + OnoDie2 - (Go - Coin3), + ReselDioZ - Go - Coin3. RosotD,e2.n = ResetDi02 - (Go - Coin3)"; ThreoDi02 n = Thro.Di.2 - (Go - Coin3)' + TwoDieZ - Go - Com3; FourDie2 n = FourDie2 - (Go - Coin3)" + ThroeOi.2 • Go • Coin3; Fi.eDi.Z.n = FiyoDie2 • (Go - Coin3)" + FourDioZ - Go - Coin3' SixD,e2.n = SixDie2 - (Go - COina)" + FiYoD,e2 - Go - Coin3; Curr.nt Slale Equations lor "LFSR" SO = Coinl'-CoinZ'.Coin3'; Sl = Coinl-CoinZ'-Coin3'; SZ = Coinl aCoinZ-Coin3'; S3 = Coinl'-CoinZ-Coin3; S4 = Coinl-CoinZ'-Coin3. S5 = Coinl'-CoinZ-Coin3'; ~6 = Coinl'-CoinZ'-Coin3; SV D.fining Equations lor Slate Machin. "LFSR" " " ENDS Coinl.d = SI.n + SZ.n + S4.n; CoinZ.d = S2.n + S3.n + S5.n. Coin3.d = S3.n + S4.n + S6.n; N.", Slate Equalions lor Slale Machine "LFSR" " SI.o = SO; SZ.n = SI. = S2; for "Dio_RoILZ" " " "" " S4.n = S3; Equa~ons R.setDioZ = Za'-Zb'-2.'-2d'; OnoDi02 = 2a-2b'-2c'-2d'; TwoDioZ = 2a'-Zb-Zc'-Zd'; ThrooDie2 = Za-2b-Z.'-Zd'. FourDi.2 = 2a'-2b-2.-2d·; Fi.oDi.2 = 2a-2b-Z.-Zd'. SixDi.Z = Za'-Zb-Zc-Zd; EQUATIONS: S3.n "D,e~oIU" SV Defining Equations lor Slale Machine "Die_RolI_l" OUTPUTS: la. 1 b. 1e. 1d. Za. Zb. Zc. Zd " " " S5.n = S4; S6.n = S5; Figure 3, 4"107 Appendix 5 APPENDIX SECOND SOURCE CROSS REFERENCE What Intel Part to Quote What Intel Part to Quote Altera Part " DSC031-S0 DSC031-3S TOSC031-S0 EP310DC EP310DC-2 EP310D1 DSC032-3S DSC032-3S DSC032-2S PSC032-3S PSC032-3S EP320DC EP320DC-2 EP320DC-1 EP320PC EP320PC-2 DSC060-SS DSC060-3S DSC060-4S CJSC060-SS CJSC060-4S PSC060-SS PSC060-4S NSC060-SS NSC060-4S TOSC060-SS TCJSC060-SS MDSC060-SS Spec MDSC060-S5 EP600DC EP600DC-2 EP600DC-3 EP600JC EP600JC-3 EP600PC EP600PC-3 EP600LC EP600LC-3 EP600DI EP600JI EP600DM EP600DMB DSC090-60 DSC090-45 DSC090-S0 CJ5C090-60 EP900DC EP900DC-2 EP900DC-3 EP900JC S-1 Altera Part " CJSC090-S0 PSC090-60 PSC090-S0 NSC090-60 NSC090-S0· TOSC090-60 TCJSC090-60 EP900JC-3 EP900PC EP900PC-3 EP900LC EP900LC-3 EP900DI EP900JI DSC121-90 DSC121-6S CJSC121-90 CJSC121-6S PSC121-90 PSC121-6S NSC121-90 NSC121-6S TOSC121-90 TCJSC121-90 EP1210DC EP1210bC-2 EP1210JC EP1210JC-2 EP1210PC EP1210PC-2 EP1210LC EP1210LC-2 EP121QDI. EP1210JI CJSC180-90 CJSC180-1s NSC180-90 NSC180-75 TCJ5C180-90 In Development In Development In Development In Development EP1800JC EP1800JC-3 EP1800LC EP1800LC-3 EP1800JI EP1800~C EP1800~CM EP1800JM EP1800JMB SECTION 5 PLA TO EPLD REPLACEMENT 5C03115C032 As a 20-Pln PAL Replacement 100% Compatible Already in wide use throughout the electronics industry are numerous different Programmable Logic Devices. Many of these are PALs from MMI. Currently, two of our EPLD products, the 5C060 and 5C031 can functionally replace most 24-pin and 20pin PALs, respectively. A third product, the 5AC312, with its architecturally advanced features, can replace most deSigns using more complex PALs such as the 20RA10, 22Y10, and 32V10. 10HS, -2 12H6, -2 14H4, -2 16H2, -2 10L8, -2 12L6, -2 16LS, A-2, A-4 16R4, A-2, A-4 14L4, -2 16L2, -2 16RS, A-2, A-4 16R6, A-2, A-4 16P8, -2 16RPS, -2 16RP6, -2 16RP4, -2 TheSC031 The 5C031 is a direct, drop-in replacement for most 2O-pin PALs, although some PALs have an incompatible architecture. TheSC060 The 5C060 is NOT a drop-in replacement for any 24pin PAL, though it can functionally replace most. The reason for this is that pin 1 is used as the main clock on registered PALs and as an in~ on non-registered. Also, pin 13 is used as an OE line on some PALs, and as an input on others. The 5C060, however, uses pin 1 as the left-half synchronous clock input and pin 13 as the right-half synchronous clock input. These are 25 ns-45 ns PALs. Functionally Compatible 16R6A 16R4A 16LSA 16RP6A 16RP4A 16P8A 16RSA 16RPSA These are 15nsPALs. 5C060 As a 24·Pln PAL Replacement While that may not be a problem in some PAL designs, those designs that require clocking or inputs on pins 1 or 13 will necessitate hardware modifications. In the case of the registered PALs, the connection to pin 1 must be rerouted to pin 13 and the. OE connected to one of the available inputs (if used). In this manner, the 5C060 can functionally replace the PAL. . TheSAC312 The 5AC312 is a direct, drop-in replacement for the 20RA 10 as well as many of the other Simple 24-pln logic devices. The 5AC312 can also serve as a dropin replacement for most designs using the 22V10 or 32V10 devices. Modified Replacement Functionally Compatible 12L10 14LS 16L6 1SL4 20L2 20L10 20LS 20RS 20R6 20R4 20RA10 2QLSA 20R8A 20R6A 20R4A With hardware modifications These are 15 ns PALs. 5AC312 As a 24-Pln PAL Replacement 100% Compatible 20LS 20RS 20R6 20R4 20RA10 5-2 100% Compatible (Qualified) 22V10 32V10 Dependent on the number of product terms used. ORDERING INFORMATION Intel EPLDs are identified as follows: D 5 "-v-' c "-v-' x ,-- I x • Device ,S X --I S • ~ Speed Technology C -CHMOS AC - Advanced CHMOS Package Type A - Hermetic, Pin Grid Array D - Hermetic, Type D (Cerdip) Dip N - Plastic, Leaded Chip Carrier CJ - Ceramic, J Leaded Chip Carrier P - Plastic Dip and Plastic Flatpack R - Hermetic, Leadless Chip Carrier X - Unpackaged Device + 125·C) A - Indicates automotive operating temperature range (- 40·C to J - Indicates a JAN qualified device, but is for internal identification purposes only. All JAN devices must be ordered by M38510 part number. (Example: M38510/42001 808), and will be marked in accordance with MIL-M-38510 specifications. L - Indicates extended operating temperature range (- 40·C to ± 8 hrs. dynamic burn-in. M- Indicates military operating temperature range (- 55·C to + 85·C) express product with 160 + 125·C) a -Indicates commercial temperature range (O·C to 70·C) express product with 160 ±8 hrs. dynamic burn-in. T - Indicates extended temperature range (- 40·C to + 85·C) express product without burn-in. No letter indicates commercial temperature range (O·C to 70·C) without butn-in. Examples: OD5C060-45 Commercial with burn-in, ceramic Dip, 060 (600 gate) device, 45 nanosecond. ·On military temperature devices, 8 suffix indicates MIL-STD-883C level 8 processing. 5-3 Device' Feature: Comparison 5C031 5C032 5C08O 5C090 INPUTS Dedicated Maximum Input Latches 10 18 10 18 4 20 12 36 110 Number Tri·State Programmable Polarity 8 Y Y 8 Y Y 16 Y Y 24 Y Y MACROCELLS 8 8 16 Buried" Reg. S Preload By.Pass Reset Preset 8 ·16 Y 10 22 Y 24 Y Y 48 Y Y 32 Y Y 12 Y Y ' 24 28 48 8 12 8 8 16 24 28 48 8 12 ,0 0 OITI DITI 0 OITI DITI OITI RS/JK RS/,lK RS/J.K RS/JK RS/JK Y Y y y V y Y Y Y Y .. 5AC312 12 60 Y Y y' . .y y 74 72 Y y. y 160 Y y y 240 . .. LOCAL/GLOBAL BUSSES 2 Y CLOCKS Asynchronou~ 2 Y Clocking Programmable Clock Edges SECURITY BIT 12 36 .' y REGISTERS Number Types PROPUCT TERMS Number Sharing Variable Prod. Term Distribution 5C121· 5C1". 5CBIC 4. Y y y 236 480 Y Y 2 4 Y y. y y Y Y 112 200 Y .- 2 Y Y Y Y Y 5-4 Y Y Y Y Y ··ELPD CUSTOMER SUPPORT Hotline EPLD Customer Design Support Center The Intel EPLD Technical Hotline is manned by application personnel from 8:00 a.m. to 5:00 p.m. (PST) every business day. Contact your local field sales office for the hotline number. Intel has a Customer Design Support Center to help customers who are .implementing EPLD designs. Service includes answering questions, device selection assistance, and design partitioning as well as limited prototyping, and product/design evaluation and implementation. For more information on the Design Support Center, contact your local Intel field sales office. BBS Intel has a Bulletin Board System for registered iPLS and iPLS II customers to electronically transfer information. Any registered person with a modem can log onto the system. The current number is (916) 9852308. If your communication software supports file transfers, you can receive utilities, software updates, and the latest information on EPLDs via the Bulletin Board. EPLD Evaluation Unit A modular unit for evaluation of EPLD devices is available from Intel. The unit has a variety of switches and LEOs, and a numeric display for control and status. Several Intel applications can be verified on the unit as well as small customer designs. For more information, contact your local Intel field sales office. 5-5 COMPAtiBLE COMPUTE'RS FOR IPLDS II A par1iallist o(computers that hav8' beel'l 'verified to be software compatible with the Intel Programmable Logic Development System Of)LDS II) ,is given below:· , " AT&T 6300 and 6300+ " Compaq family of (88, 86, 286, 386) IBM ,AT ' IBM x;r IBM XT·286 liP Vectra Pes Sperry 117 Tandy 3000 HD 5-6 inter DOMESTIC SALES OFFICES ......... N!WMEXtCO GIORGIA _ A_ ==Pamway ,#2 =~_"'N.E. SUiteS 295 $0110200 ..... t~,~",. Tel: (404) 449-0541 Norcroea 30092 ='l:.~ ILUNOI8 NeWYOOK SUIteD-21. =:=~:'I~~oad. Suite 400 To!, (002) 881-<980 Til, t\~ ~ilorado ...... INDIANA ~~u. .... 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(704), 568-8986 Suite 200 Norcross30Q92 Tel: (404)449..0541 Intel Corp." 3401 Park Center Drive ~l'r.:)':Jt.53S0 Raritan Center ~e':~1~~051 VIRGINIA Ed18on08817 Tel: (201) 225-3000 ILLINOIS WASKINGTON =~V~ngale Road Suite 400 OKLAHOMA ~~~~~~~&yf INDIANA Intel Corp 8777 Purdue Road SUite 125 ~:~g~~~:.o~ IOWA Intel Corp 1930 8t Andrews Drive N.E. 2nd Floor Cedar Ra~lds 52402 Tel: (319) 393-5510 t~~~r'ataCenter OREGON 75 Uvlngston Avenue First Floor Roseland 07068 WISCONSIN '~~~~U-~:g:o~ NEW MEXICO ~~~f'Elam Young Parkway Hillsboro 97123 Tel' (503) 681-8080 KANSAS Intel Corp.. San Tomas 4 2700 San Tomas Expressway 2nd Floor Santa Clara 95051 ~J~~= Sultaloo PENNSYLVANIA CANADA BRITISH COLUMBIA NEW YORK MARYLAND Intel Corp." 7321 Parkway Drive South SulleC HanOYef 21076 ~~1/,.'ef.!,s:. COlORADO =5~park Drive Intel Corp. 8400 W 110th Street SUite 170 Overland Park 66210 Tel. (913) 345-2727 Intel Corp· 850Cros Fl!Jrportl t&ln ONTARIO Perk Intel Semiconductor of Canada, Ltd. 2650 Queensvlew DrIve PUEFlTOFlICO !mg1=·PaI1c.way . ~~(:C= =~80907 .... 250 Ottawa K2B 8He ~~~~.fflsB714 Haup~u~ 11187 MASSACHUSEns ~:l~~2ff2~~~ Intel Corp. 15 Myers Corner Road Sulte2B Hollowbrook Park '~r Fella 12590 Tel: 1 297-8161 : 51 ·248-0080 TEXAS rD" CONNECTICUT ~~inRoad QUEBEC Intel Semlconduotor of Canada, Ltd. 820 St. John Boulevard Pointe Claire H9R 3K2 ~~J~~~l~ 2nd Floor ~~~1,3~ CUSTOMER TRAINING· CENTERS CALIFORHtA IUJNOIS MASSACHUSETTS MARYLAND 2700 San Tomas Expre88way Santa Clara 95051 Tel' (408) 97()'1700 ~:;~~~I~~l300 m (312) 311l..,OO 3 Carlisle Road 7833 Walker br., 4th Floor Greenban 20770 Tel' (301) 22O-33BO Westford 01886 Tel: (617) 692·1000 SYSTEMS ENGINEERING OFFICES CALIFORNIA ilLINOIS NEW YORK 2700 San Tomas Expressway Santa Clara 95051 Tel' (408) 988-8086 ~!:~n§&~7l300 300 Motor Parkway Tel: (312) 3rpo-B?S' ~:lufEla~~~ 00-3,4,88
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