1988_Microprocessor_Microcontroller_and_Peripheral_Data_Volume_1 1988 Microprocessor Microcontroller And Peripheral Data Volume 1

User Manual: 1988_Microprocessor_Microcontroller_and_Peripheral_Data_Volume_1

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Motorola's Microcontrollerand
Microprocessor Families

1

Volume I

Reliability
Volume I

Data Sheets
Volume I and II

I:.·

I

Mechanical D'ata

Volume II

Evaluation Modules
Volume II

I

Ordering Information Form.,'.
'." .,
Volumes",·I.
II

MOTOROLA MICROPROCESSOR DATA

Motorola's Microcontroller and
Microprocessor Families
Volume I

.I
I

Reliability

Volume I

Data Sheets
Volume I and II

Mechanical Data
Volume II

Evaluation Modules
Volume II.

Orderin;glnf'ormation Forms
Vol'ume II

MOTOROLA MICROPROCESSOR DATA

MOTOROLA
MICROPROCESSOR DATA
VOLUME I

Prepared by
Microprocessor Products Group
This book is intended to provide the design engineer with the technical data needed
to completely and successfully design a microcomputer-based system. The Technical
Summary and Advance Information data sheets for Motorola's microcontroller, microprocessor, and peripheral components are included.
The information in this book has been carefully checked; no responsibility, however,
is assumed for any inaccuracies. Furthermore, this information does not convey to the
purchase of microelectronic devices any license. under the patent rights of the
manufacturer.
Additional information on Motorola's new products and system development products
are also included. For further marketing and application information, please contact:
Motorola Inc.
Microprocessor Products Group
Microcontroller Division
6501 William Cannon Drive West
Austin, Texas 78735-8598
Applications
EVB/EVM/Development Systems
Literature - Literature Distribution Center
Marketing Information - Pricing
Marketing Information - Availability

512-891-2034
512-891-2034
602-994-6561

Local Sales Office
512c891-2990

Motorola reserves the right to make changes without further notice to any products
herein to improve reliability, function or design. Motorola does not assume any liability
arising out of the application or use of any product or circuit described herein; neither
does it convey any license under its patent rights nor the rights of others. Motorola
products are not authorized for use as components in life support devices or systems
intended for surgical implant into the body or intended to support or sustain life. Buyer
agrees to notify Motorola of any such intended end use whereupon Motorola shall
determine availability and suitability of its product or products for the use intended.
Motorola and ® are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Employment Opportunity/Affirmative Action Employer.
Series A
Second Printing
©MOTOROLA INC., 1988
"All Rights Reserved"

Printed in U.S.A.

iii

DATA CLASSIFICATION
Product Preview
Data sheets herein contain information on a product under development. Motorola reserves the right to change or discontinue these products without notice.

Technical Summary
Data sheets herein containihforniation on new products. Specifications and information
are subject to change without notice.

Advancecl.lniormation
Data sheets herein contain information on new products. Specifications and information
are subject to change without notice.

EXORciser is a register trademark of Motorola, Inc.
HDS-300, MOOS, and BUFFALO are trademarks of Motorola, Inc.
MS-DOS is a trademark of Microsoft, Inc.
IBM is a register trademark of International Business Machines, Inc.

iv

TABLE OF CONTENTS
The Microprocessor/Microcontrolier and Peripheral Data book consist of a two volume set. Refer
to the table of contents and the master index for division of the chapters and locatiol')s of devices.
Page
Chapter 1 -

Motorola's Microprocessor and Microcontroller Families

M68HC11/M6801/M6805/M6804 Families ........................................................... 1-1
Development Support.................................................................................. 1-4
Single-Chip MCU Selector Guides ................................................................... 1-4
Chapter 2 -

Reliability and Quality Summary

Introduction...............................................................................................
Quality and Reliability System ........................................................................
Packaging System .......................................................................................
Results and Conclusion .................................................................................
Failure Rate Calculations ...............................................................................
Chapter 3 -

2-1
2-1
2-2
2-23
2-24

Data Sheets

(See master Index for sequence)
Chapter 4 -

Mechanical Data

Introduction............................................................................................... Vol. II
Package Dimensions .................................................................................... Vol. II
Chapter 5 -

Evaluation Modules

Development Station .................................................................................... Vol. II
Low Cost MCU Evaluation Modules ................................................................. Vol. II
Chapter 6 -

Product Ordering Forms

Introduction............................................................................................... Vol. II

MOTOROLA MICROPROCESSOR DATA

v

MASTER INDEX
Device
Number
MC2672
MC2674
MC6800
MC68011
MC6803
MC6801U41
MC6803U4
MC68701
MC68701U4
MC6802
MC6804J1
MC6804J2
MC6804P2
MC68704P2
MC68HC04J2
MC68HC04J3
MC68HC04P4
MC68HC704P4
MC6805P2
MC6805P6
MC6805R2
MC6805R3
MC6805S2
MC6805S3
MC6805U2
MC6805U3
MC68705P3
MC68705P5
MC68705R3
MC68705R5
MC68705S3
MC68705U3
MC68705U5
MC68HC05A6
MC68HC05B4
MC68HC05B6
MC68HC05C2

Description

Page
Number

Programmable Video Timer Controller.......................................... 3-1
Advanced Video Display Controller ....................................... ,....... 3-28
8-Bit Microprocessor Unit ............................ ,.............................. 3-61
8-Bit Microcontroller Unit........................................................... 3-92
8-Bit Microcontroller Unit........................................................... 3-131
8-Bit Microcontroller Unit, ......................... '" ..................... ..... ..... 3-174
8-Bit Microcontroller Unit ........ ~ .................................................. 3-214
8-Bit Microprocessor with Clo~k and RAM .............................. ; ....... 3-256
8-Bit Microcontroller Unit .... ;...................................................... 3-278
8-Bit Microcontroller Unit........................................................... 3-297
8-Bit Microcontroller Unit .............. , .......... , ................................. ·3-31.6
8-Bit Microcontroller Unit with EPROM .;...... ........ .......................... 3'-335
8-Bit HCMOS Microcontroller Unit................................................ 3-355
8-Bit HCMOS Microcontroller Unit................................................ 3-374
8-Bit HCMOS Microcontroller Unit ............................................... ; 3-393
8-Bit HCMOS Microcontroller Unit with OTPROM or EPROM...... ......... 3-395
8-Bit Microcontroller Unit with 1K ROM........................ ................. 3-397
8-Bit Microcontroller Unit ........................................................... 3-415
8-Bit Microcontroller Unit with AID Converter ....... ~ ......................... 3-433
8-Bit Microcontroller Unit with AID Converter ............ ;.................... 3-453
8-Bit Microcontroller Unit with AID Converter, SPI,
and Three Timers............ ....................................................... 3-473
8-Bit Microcontroller Unit with AID Converter, SPI,
and Three Timers................................................................... 3-502
8-Bit Microcontroller Unit......... .................................................. 3-532
8-Bit Microcontroller Unit........................................................... 3-550
8-Bit Microcontroller Unit with EPROM ......................... ~ ................ 3-568
8-Bit Microcontroller Unit with EPROM.......................................... 3-586
8-Bit Microcontroller Unit with AID Converter
and EPROM............................................................................ 3-604
8-Bit Microcontroller Unit with AID Converter
Secured EPROM ................................................... ; ................ 3-624
8-Bit Microcontroller Unit with AID Converter, SPI,
EPROM, and Three Timers .......................................... ............. 3-643
8-Bit Microcontroller Unit with EPROM ... ; .................. ; ................... 3:.674
8-Bit Microcontroller Unit with Secured EPROM .................. ............ 3-692
8-Bit Microcontroller Unit........................................................... 3-710
8-Bit Microcontroller Unit ................ : .......................................... 3-712
8-Bit Microcontroller Unit........................................................... 3-751
8-Bit Microcontroller Unit........................................................... 3-792

MOTOROLA. MICROPROCESSOR DATA

vii

MASTER INDEX (Continued)
Device
Number

MC68HC05C3
MC68HC05C4
MC68HC05C8
MC68HC05C9
MC68HC05L6
MC68HC05M4
MC68HC05P1
MC68HCL05C4
MC68HCL05C8
MC68HSC05C4
MC68HSC05C8
MC68HC705B5
MC68HC705C4
MC68HC705C8
ivlC68HC805B6
MC68HC805C4
MC146805E2
MC146805F2
MC146805G2
MC6809
MC6809E
MC6810
MC68HC11AO
MC68HC11A 1
MC68HC11A8
MC68HC11 D3
MC68HC11E1
MC68HC11 E9
MC68HC11 F1
MC68HC711 D3
MC68HC811 E2
MC146818
MC146818A
MC6821
MC146823
MC68HC24
MC68HC34
MC6840
MC6844
MC6845,

Description

Page
Number

8-Bit Microcontroller Unit ................. : ......................................... 3-819
8-Bit Microcontroller Unit.......................................................... .3-859
8-Bit Microcontroller. Unit........................................................... 3-899
8-Bit Microcontroller Unit:.......................................................... Vol. II
8-Bit Microcontroller Unit........................................................... Vol. II
8-Bit Microcontroller Unit .......... ~ ...... , ......................... :............... Vol. II
8-Bit Microcontroller Unit .............. ,'............................................ Vol.
8-Bit Microcontroller Unit ................ .'.. : ....................................... Vol.
8-Bit Microcontroller Unit........................................................... Vol.
8-Bit Microcontroller Unit ........................................................... ·'Vol.
8-Bit Microcontroller Unit............................................................ Vol.
8-Bit Microcontroller Unit with OTPROM ........................................ Vol.
8-Bit Microcontroller Unit with OTPROM or EPROM......................... Vol.
8-Bit Microcontroller Unit with Standard EPROM............................. Vol.
8-Bit Microcontroller Unit with EEPROM .. ;.; ................................... Vol.
8-Bit Microcontroller Unit with OTPROM or EEPROM .. : ..................... Vol.
8-Bit Microcontroller Unit .................... ; ...................................... Vol.
8-Bit Microcontroller Unit .............. : ...... ; ...... ~ •...... : .................... '.. Vol.
8-Bit Microcontroller Unit .......... ;;. ~ ........ ; ....... ~.;.......................... Vol.
8-Bit Microcontroller Unit ........ , ........ '; ................................. ; ....... Vol.
8-Bit Microcontroller Unit ........................................................... Vol.
128 x 8 Bit Static RAM ........................................................'........ Vol.
8-Bit HCMOS Microcontroller Unit with SPI, SCI,
and AID Converter ................................................................ : .. VaLli
8-Bit HCMOS Microcontroller Unit with. SPI, SCI, AID Converter,
and EEPRO M ......................... '......... ; .' ........... ; ....... ; ................ . Vol. II
8-Bit HCMOS Microcontroller Unit with SPI; SCI, AID Converter,
and EEPROM ................ ; .......... , .. ,'..................'........................ . Vol. II
8-Bit HCMOS Microcontroller Unit SPI, SCI, and EEPROM ................ .. Vol. II
8-Bit HCMOS Microcontroller Unit with SPI, SCI, AID Converter,
and EEPROM .......................................................................... . VaLli
8-Bit HCMOS Microcontroller Unit with SPI, SCI, AID Converter,
and EEPR 0 M .............. '.................................... : ..... '.' ................ . VaLli
8-Bit HCMOS Microcontroller Unit with SPI, SCI, AID Converter,
and EEPRO M .................. " ...... '......' .................. ,; ....................... . VoL II
8-Bit HCMOS Microcontroller Unit with OTPROM or EEPROM ........... . Vol. II
8-Bit HCMOS Microcontroller Unit with SPI, SCI, AID Converter,
and EEPROM ........ '....... ·.......... ; .................................. : .......•...... Vol.
,Real Time Clock with RAM ................................. i . . . . . . . . . . . . . . . . . . . . . . . . Vol.
Real Time Clock with RAM ... ~ ... ; ................................................. . Vol.
Peripheral Interface Adapter .................. '..................................... . Vol.
CMOS Parallel Interface .....': ...
Vol.
Port Replacement Module.;; ..... : ............ i ••••• •:.' •••••••••••••••••••••••••••••• VoL
Dual Port RAM ...................................... ; ................................... '. Vol.
Programmable Timer, Module ........................ '.......................... ; •.. Vol. II
Direct Memory Access Controller ..... ; ....... '............. ; .... ; ........ ;;.;: ... . Vol: II
CRT Controller .......................................'..'................................ . VoL II
i . . . . . . . . . . . . . . : . . . . , '. . . . . . . . . . . . . . . . . .' . . . . . . . . . . . . . . .

MOTOROLA MICROPROCESSOR .DATA

viii

MASTER INDEX (Concluded)
Device
Number
MC6850
MC6852
MC6854
MC68488
MC6898
MC68HC99

Description

Asynchronous Communications Interface Adapter...........................
Synchronous Serial Data Adapter.... .............................................
Advanced Data Link Controller.....................................................
General-Purpose Interface Adapter ...............................................
Cable Driver and Receiver...........................................................
Hard Disk Controller..................................................................

MOTOROLA MICROPROCESSOR DATA
ix

Page
Number

Vol.
Vol.
Vol.
Vol.
Vol.
Vol.

II
II
II
II
II
II

Motorola's Microcontroller and
Microprocessor Families
Volume I

MOTOROLA MICROPROCESSOR DATA

II
MOTOROLA'S
MICROCONTROLLER AND MICROPROCESSOR
FA.MILIES
Motorola manufactures the industry's mostcomplete selectionof solid-state microcontroller units
(MCU) and microprocessor (MPU), providing the performance and design flexibility needed by
the design engineer.
Motorola's family concept has been extremely popular in the MCU industry. This family concept
was pioneered with the introduction of the M6800 Family 1974. Four families have evolved from
the M6800 Family to fulfill expanding customer requirements. These families are the M68HCll,
M6801, M6805, and the M6804. Figure 1-1.illustrates the family evolution.
Numerous peripheral devices have been developed and are available to support the MCUs and
MPUs.

M68HC11/M6801/M6805/M6804 FAMILIES

The M68HC11 Family offers high performance in a single-chip MCU with Electronic Eraseable
Programmable Read Only Memory (EEPROM), a 16-bit timer, a Serial Communication Interface
(SCI), a Serial Peripherallnterfac'e (SPI), and an 8-bit Analog-to-Digital (AID) converter. The M6801
Family includes high performance in a single chip with Eraseable Programmable Read Only
Memory (EPROM) and SCI. The rapidly expanding M6805 Family is available in a variety of memory
and package sizes with various special Input/Output(IJO) functions. The M6805 is available in
High-Density N-Channel Metal Oxide Silicon (HMOS), Complementary Metal Oxide Silicon (CMOS),
and High-Density Complementary Metal Oxide Silicon (HCMOS). The M6804 Family now provides
the 8-bit processing capabilities that compete in the 4-bit price arena. A One Time Programmable
Read Only Memory (OTPROM) is also .available in the M68HC11, M6804, ahd M6805Families.

Technology

Motorola's first MCUs and MPUs were produced in HMOS which offered a low cost single-chip
solution in high production volumes. CMOS was then introduced which offered very low power
consumption and a wide power supply tolerance at performance levels s.imilar to.HMOS. The
introduction of HCMOS offered the best of both worlds, with high-density and low power consumption. Tables 1-1 and 1-2 list Motorola's MCUs,MPUs, and peripheral product line by technology.

ROM Size

The mask ROM capacities of the present single~chip MCUs range fwm a low of 512 bytes in the
M6804 Family to a high of 8K in the M68HC11 Family. Refer to Table 1-3 through 1-7 to determine
what ROM is offered in the MCU product line. In selecting ROM size, the ROM usage efficiency
of the instruction set should be considered, along with the application to be programmed.

MOTOROLA MICROPR·OCESSOR DATA
1-1

6.0
. - - - - - - - - - 1 1 68020 1
...-----~----------------....,

5.0

rL 68HC32
!
___ -1
4.0

3.0

s:o

~6SH C8

1
L?~~~3..J

o""'"

~
~

'7"

N

s
n:ll
0

i A81

J168HC711 03

. 2.0
'w
U

z

«

::;)~

a... a;:

u~

~

:'tJ

:ll

o

n
m
en
en

I 68HC805C4

o:ll

68HC805B6
68HC05B6
68HC05M4
68HC05C9
68HC05A6
68HC705C8
68HC05P1

rs8HC05C4l
168HC70585I

~8~~0~~

C
l>

~

L:~~r---1168HC04 FAMILY I

1975

1976-1978

1979

1980

1981

1982

1983

1984

1985

INTRODUCTION YEAR

Figure 1-1. Motoria MCUlMPU Evolution

1990

Table 1·1. MCU/MPU Technology Listing
HMOS/NMOS
MC6800
MC6801
MC6801U4
MC68701
MC68701U4
MC6802
MC6803
MC6803U4
MC6804J1
MC6804J2
MC6804P2
MC68704P2
MC6805P2
MC6805P6

HCMOS

MC68705P3
MC68705P5
MC6805R2
MC6805R3
MC68705R3
MC68705R5
MC6805S2
MC6805S3
MC68705S3
MC6805U2
MC6805U3
MC68705U3
MC68705U5
MC6809/9E

MC68HC04J2
MC68HC04J3
MC68HC04P4
MC68HC704P4
MC68HC05A6
MC68HC05B4
MC68HC05B6
MC68HC805B6
MC68HC05C2
MC68HC05C3
MC68HC05C4
MC68HC05C8
MC68HC05C9
MC68HC05L6
MC68HC05M4
MC68HCQ5P1
MC68HCL05C4
MC68HCL05C8

CMOS
MC68HSC05C4
MC68HSC05C8
MC68HC705B5
MC68HC705C8
MC68HC805C4
MC68HC11AO
MC68HC11A1
MC68HC11A8
MC68HC11D3
MC68HC11E1
MC68HC11E9
MC68HC11F1
MC68HC711A8
MC68HC711 D3
MC68HC711 E9
MC68HC811 E2

MC146805E2
MC146805F2
MC146805G2

Table 1·2. Peripheral Technology Listing
HMOS/NMOS
MC6810
MC6840
MC6845
MC6852
MC6898
MC2672

HCMOS

MC6821
MC6844
MC6850
MC6854
MC68488
MC2674

MC68HC24
MC68HC99

CMOS
MC68HC34

MC146818
MC146818A
MC146823

Non·Mask ROM Versions

EEPROM, EPROM, OTPROM, andlor non-ROM versions are offered in praCtically all single-chip
MCUs. These versions serve for limited to high volume applications, prototype debugging, and
field trials. EEPROM and OTPROM versions are available in the M6805 and M68HC11 Families.
EPROM versions are available in the M6805 and M6801 Families. Refer toTable 1-3 through 1-7
to determine what is offered in the MCU product line ..

RAM Size

On-chip Random Access Memory (RAM) sizes range from 30 bytes in the M6804 Family to 512
bytes in M68HC11 Family. The M6805 has versions of 64,104, 112, and 176 bytes. Architectures
such as the M68HC11, M6801, and M6805 Families, which permit multi-level subroutines plus
ROM and RAM data tables, allow trade-off ROM and RAM utilization. ROM usage can be minimized
with subroutines and look-up tables, while RAM usage can be optimizes with ROM tables and
fewer subroutines.

Digital Input/Output

Single-chip MCUs are available in 52-pin quad packages as well as the smaller (and lower cost)
20-pin packages. Five to fourteen pins serve power and control functions permitting up to 12 1/0

MOTOROLA MICROPROCESSOR DATA

1·3

pins in a 20-pin package and up to 38 t/Opins.in the' 48/5.2 pin verions. All of the MCUs offer
essentially any mix of inputs and outputs. Higher output drive current is available in the M6805
Family.

Expansion Bus
The non-ROM versions indudeabus to access off-chip programm~,m.ory and additional 1/0. The
M6801 Family also includes a three bus structure for off-chip expansion. The three bus structure
permits the number of bus pins to be optimized for the amount of address space needed off-chip.
The M68HC11 Family can operate in an expanded mode and address up to 64K byte~ of external
memory.

Interrupts
When an application program must synchronize with two or more external events, interrupt
hardware in some form isusually necessary. The M68HC11, M6801, and M6805 Families include
fully automatic interrupts (registers are saved) with programmable vectors for both an external
and internal timer.

Timers
Timers are the most frequently used on-chip functions. Timers may generate interrupts to a
program at a periodic rate, measure external events, and generate measured output waveforms.
The M68HC11, M6801, and M68HC05 devices include a 16-bit timerthat may be used to perform
three of the preceeding functions simultaneously. The M6805 and, M6804 timers consist of a
programmable 8-bit counter and selectable 7-bit prescaler.

Special Functions
Variousmembersofthe MCU Fa,milies include addi~ionall/O functions. Forexample, theM68HCll,
M6801, and ~omeofthe M6805Family include a SCI. The SCI is used for long-range communi~
cations" as in datatran,sfer from an MCU to a,terminal or modem. The M68HC11 Family alJd some
ofthe M6805 Family also conta.in a SRI. TheSPI.is used primarily for serial communicationbetween
chips on the same printed circuit board. Selected members of the M68HC11 and M6805 Family
include multi-channel AID converters. The MC6805RIS versions contain four analog input channels,
and the M68HC11 MCUs features up to eight analog input channels.

DEVELOPMENT SUPPORT
The M68HC11, M6801; and M6804, and'M6805 Families are fully supported by a seriesof eco~
nomical evaluation modules (EVM). A more powerful development system is also available inthe
HDS-300. The supp,0rt products are cove'redin more detail in Chapter 5 Evaluation Modules.

SINGLE-CHIP SELECTOR GUIDES
Tables 1-3 through 1-7 list the different features available for devices within a family:The tables
provide information as to RAM, ROM, EPROM, timer, etc. Table 1-8 lists the OTPROM devices
available;

MOTOROLA MICROPROCESSOR. DATA

1-4

II

Table 1-3. M6801 Family Selector Guide

DEVICE
6801
68701
6803
6801U4
68701U4
6803U4

HMOS
HMOS
HMOS
HMOS
HMOS
HMOS

40
40
40
40
40
40

128
128
128
192
192
192.

2048

29
29
13
29
29
13

2048
4096
4096

16
16
16
16
16
16

64K
64K
64K
64K
64K
64K

Yes
Yes
Yes
Yes
Yes
Yes

Definitions:
P
S
I/O
SCI
RAM
ROM
EPROM

=

=
=
=
=
=
=

Plastic
Cerdip
Input/Output
Serial Communication Interface
Random Access Memory
Read Only Memory
Eraseable Programmable ROM

Table 1~4. M6804 Family Selector Guide

DEVICE
6804P2
68704P2
6804J1
6804J2
68HC04P4
68HC04J2
68HC04J3
68HC704P4

HMOS
HMOS
HMOS
HMOS
HCMOS
HCMOS
HCMOS
HCMOS

28
28
20
20
28
20
20
28

30
30
30
30
172
30
122
172

1016
1020
512
1000
3700
1000
1672
3700

20
20
12
12
20
12
12
20

8
8
8
8
8
8
8
8

Definitions:
P = Plastic
S = Cerdip
FN = Plastic Leaded Chip Carrier
I/O = Input/Output
RAM = Random Access Memory
ROM = Read Only Memory
EPROM = Eraseable Programmable ROM

MOTOROLA·MICROPROCESSOR DATA

1·5

P,FN
S
P
P
P
P
P
S

P,S
S
P,S
P,S
S
P

Table 1-5. M6805 Family Selector Guide

DEVICE
6805P2
6805P6
68705P3
68705P5
6805R2
6805R3
68705R3
68705R5
680582
6805S3
68705S3
6805U2
6805U3
68705U3
68705U5

HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS
HMOS

28
28
28
28
40/44
40/44
40
40
28
28
28
40/44
40/44
40
40

64
64
112
112
64
112
112
112
64
104
104
64
112
112
112

1110
1804
1804
1804
2048
3776
3776
3776
1480
2720
3752
2048
3776
3776
3776

20
20
20
20
32
32
32
32
21
21
21
32
32
32
32

8
8
8
8
8
8
8
8
8
8
8
8

Yes
Yes
Yes
Yes
Yes
Yes
Yes

8
8
8

Definitions:

= Plastic
= Cerdip,
= Plastic Leaded Chip Carrier
110 = Input/Output
RAM = Random Access Memory
ROM = Read Only Memory
EEPROM = Eraseable Programmable ROM
SPI = Serial Peripheral Interface
AID = Analog/Digital Converter
P
S
FN

MOTOROLA MICROPROCESSOR DATA
1-6

Yes
Yes
Yes

P,S,FN
P,S,FN
S
S
P,S,FN
P,S,FN
S
S
P,S,FN
P,S,FN
S
P,S,FN
P,S,FN
S
S

Table 1-6. M6805 HCMOS/CMOS Family Selector Guide

DEVICE
68HC05A6
68HC05B4
68HC05B6
68HC05C2
68HC05C3
68HC05C4
68HC05C8
68HC05L6
68HC05M4
68HCL05C4
68HCL05C8
68HSC05C4
68HSC05C8
68HC705C8
68HC805B6
68HC805C4
146805E2
146805F2
146805G2

HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
CMOS
CMOS
CMOS

40/44
48/52
40/52
40
40

40/44
40/44
68
52

40/44
40/44
40/44
40/44
40/44
48/52
40/44
40
28
40

176
176
176
176
176
176
176
176
128
176
176
176
176
304
176
176
112
64
112

4160
4160
5952
2096
2096
4160
7700
6208
4K
4160
8K
4160
8K

2056
256

8K

6208
4160

0
1089
2106

32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
20
32

16
16
16
16
16
16
16
16

Yes

Yes
Yes
Yes
Yes

Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes
Yes

8/16
16
16
16
16
16
16
16
8
8
8

Yes
Yes

Yes

Yes

Definitions:
P = Plastic
S = Cerdip
FN = Plastic Leaded Chip Carrier
1/0 = InputlOutput
AID = AnaloglDigital Converter
SCI = Serial Communications Interface
SPI = Serial Peripheral Interface
RAM = Random Access Memory
ROM = ReadOnly Memory
EPROM = Eraseable Programmable ROM
EEPROM = Electrical Eraseable ROM

MOTOROLA MICROPROCESSOR DATA
1-7

Yes
Yes
Yes

P,FN
P,FN
P,FN
P
P
P,FN
P,FN
FN
FN
P,FN
P,FN
P,FN
P,FN
P,FN
P,FN
P,FN
P,S,FN
P,S,FN
P,S,FN

Table 1-7. M6SHC11 Family Selector Guide

DEVICE

68HC11AO
68HC11A1
68HC11A8
68HC11D3
68HC11E1
68HC11E9
68HC11F1
68HC811E2

HCMOS
HCMOS
'HCMOS
HCMOS
HCMOS
HCMOS
HCMOS
HCMOS

48/52
48/52,
48/52
40/44
52
52

256
256
256
192
512
512

48/52

256

512
512

38
38
38
30
38
38

16
16
16
16
16
16

64K
64K
64K
64K
64K
64K

Yes
Yes
Yes
No
Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes

Yes
Yes
Yes
Yes
Yes
Yes

P,FN
P,FN
P,FN
P,FN
FN
FN

2K,

,38

16

64K

Yes

Yes

Yes

P,FN

512
512

8192
4096
0
12K

Definitions:

, P=
FN=
I/O =
AID =
SCI =
SPI' =
RAM =
ROM =
EPROM =
EEPROM =

Plastic
Plastic Leaded Chip Carrier
Input/Output ,
Analog/Digital Converter
Serial Communication Interface
Serial Peripheral Int~rface
Random Access Memory
Head Only Memory
Eraseable Programmable ROM
Electrical Eraseable ROM

Table 1-S. One-Time Programmable ROM (OTPROM) Devices

Timer
Bit

A/D,SCI

RAM
(Bytes)

68HC704P4

3740

124

20

8

-

-

28-DIP,DW*

68HC705B5*

6208

176

24

16

AID, SCI

Yes

52-FNA8-DIP

68HC705C4*'

4160

176

24

16

SCI, SPI

Yes

44-FNAO-DIP

68HC705C8

7616

304

24

16

SCI; SPI

Yes

' 44-FNAO-DIP

I/O

sPI

68705R3

3776

112

24

8

AID

68HC71103*

4096

192

24

16

SCI, SPI

68HC711A8*

8192

256

38

16

AID, SCI, SPI

68HC711E9*

12K

512

38

16

AID, SCI, SPI

NOTES:
1. Use MC68HC705C8 for window emulation.
2. Definitions:
FN = Plastic Quad (PLCC)
OW = Small Outline (Wide-Body SOIC)
DIP = Dual-In-Line Package
RAM = Random Access Memory
I/O = Input/Output
AID = Analog/Digital
SCI = Serial Communications Interface
SPI = Serial Peripheral Interface
COP = Computer Operating Properly
3. *Available in 1989.

MOTOROLA' MICROPROCESSOR·DATA'
1-8

COP
Watchdog

Pin
Package

OTPROM
(Bytes)

Device

Yes
,

40-P
44-FNAO-DIP

Yes

52-FN

Yes

48-DIP,52-FN

Reliability
Volume I

MOTOROLA MICROPROCESSOR DATA

I

MICROPROCESSOR PRODUCTS GROUP
RELIABILITY AND QUALITY ASSURANCE
1987 ANNUAL RELIABILITY REPORT
SUMMARY
INTRODUCTION
The Motorola MOS Microprocessor Reliability and Quality Monitor (R&QA) Program is designed
to generate an ongoing data base of reliability and quality performance for various categories of
Microprocessor products. The primary purpose of the program is to identify negative trends in
the data so that immediate corrective action can be taken. The program also allows Motorola to
develop a large data base of reliability and quality results that can be reported quarterly to
customers. The following report summarizes the reliability and quality data for 1987.
The reliability monitor tests are con'ducted on sample groups pulled on a quarterly basis from
major categories of products representing a matrix of processing and packaging technologies.
Product mix, sample availability and equipment capacity may cause the specific sample groups
pulled for a given quarter to vary from quarter to quarter. Each sample group has a specific set
of reliability tests associated with it that are appropriate for that product type based on ourhistory
for that classification. At the end of each quarter, results are reported for all sample groups that
have completed testing. In addition at the end of each year a complete summary of the 4 quarters
is reported.
The quality results that are reported are the electrical and visual/mechanical (Average Outgoing
Quality (AOQ), given in parts per million defective) for the Microprocessor Group. This data
represents the summary of results from the QC gate operation performed on every lot during
1987. Electrical AOQ represents arty AC, DC, or functional failure at any temperature (each lot
may be typically gated at hot, room or coId temperatures). Visual/mechanical AOQ represents
failures such as bent leads, incorrect marking, marking permanency problems, and cracked packages. The AOQ reported is the product the process average (ratio of defective devices to largest
sample size) and the lot acceptance rate.

QUALITY AND RELIABILITY SYSTEM
Acomplete Reliability and Quality Assurance (R&QA) system is in place to monitor and control
the performance of Motorola's MOSMicroprocessorComponents. Incoming Quality Control inspects starting wafers, masks, chemicals, package piece parts, and molding compounds. Process
Engineering and In-Process Quality Control perform step-by-step monitoring of the wafer process
to check oxidation, diffusion, photolithography, ion implantation, polysilicon deposition, metallization', passivation, and other process operations. Final visual, class probe, and capacitancevoltage plots complete the wafer area inspection. Environmental monitors are also performed for
air cleanliness, water quality, temperature, and humidity.
In the assembly area, In-Process Quality Control performs monitors on equipment performance
and gate inspections at the major process steps on all lots. The Outgoing Quality Control group
continues this philosophy in the final test area by performing electrical and visual-mechanical

MOTOROLA-MICROPROCESSOR DATA

2-1

I

gates. The electr'ical inspection, which consists of AC, DC, and functional tests, is performed to a
0.1% (maximum) Acceptable Quality Level (AQL) sampling plan. The visual/mechanical inspection
is also performeqto a 0.1% AQL sampling plan. Any lot which fails either of these gates is returned
to production for 100% rescreen. An R&QA Engineering organization exists to approve final test
programs and support the. Outgoing Quality Control organization. Test programs are tailored to
assure all required specifications are h1et~r the devices are rejected.

I

The R&QAEng'ineering organization is also responsible for performing qualifications of new
designs and process changes prior to introduction. In addition, R&QA Engineering establishes
and maintains monitor programs to assure processes stay in control once they are qualified.
Results from these programs provide rapid feedback to correct problems as they occur.
Supporting these efforts is the Metrology Laboratory which includes both a Standards and a
Calibration Laboratory to provide National Bureau of Standards traceability to all production
measu rements.
Also offering required support are a Chemical Laboratory with such equipment as a gas chromatograph/mass spectrograph and X-ray fluorescent systems for detailed incoming chemical
analyses; a Surface Analysis Laboratory whose equipment includes a Scanning Electron Microscope (SEM) and a Scanning Auger Microprobe (SAM); and a Product Analysis Laboratory for
detailed analyses of failure modes and mechanisms for Microprocessor devices.

PACKAGING SYSTEM
Motorola Microprocessor devices are produced in plastic, CERDIP, PGA, and sidebraze packages.
The ceramic package types are hermetically sealed to protect the integrated circuit from environmental factors and permit operation over extreme temperature ranges. Although plastic devices
are not hermetic/modern epoxies exhibit extremely high moisture resistance, and long lifetimes
may ther~f0re b~<~xpected from these devices in .typical environments.
In recent years; plastic encapsulated devices have gained widespread acceptance throughout the
electronics industry. Improvements in materials and process controls have resulted in significant
improvements in reliabiLity performance. In addition, plastic packages have the advantage of I·ow
cost ahd physicaL strength ..
Encapsulated integrated circuits incorporate the simpliest processing and package construction
ohhe vari.oussystems available. The die is attached to a leadframe, wire bonded and encapsulated
using an epoxy novolac molding compound. The die may be attached to the Jeadframe by epoxy
or by any of a variety of eutectic forming metal preforms. Wire bonding in plastic may be thermocompression ·or thermosonic, but the Wire is ,always gold. The. encapsulant is the most critical
component.,oJ the system since it controls contamination, moisture resistance, a,nd stress effects.
Epoxy novolacsbave become the industry standard molding compound since they combine
excellent characteristics in all these ar.eas.
The plastic package>is, by far, the most resistantto physical damage since the die is completely
encapsulated and cavity hermeticity is not a concern. Since the package is light in weight and the
plastic is less brittlethan ceramic, chipping and cosmetic damage, are not problems. The leadframe
and plating are equivalent to CERDIP.
In comparing plastictoceramic packages, there are tWQ characteristics to be considered: moisture
resistance and thermal .characteristics. Microprocessor plastic products perform very well on

MOTOROLA MICROPROCESSOR DATA

2-2

moisture resistance relatedtests. This is due to'advances in molding compounds, the characteristic
low voltages and the nioderate power dissipation of Microprocessor products.' In most instances
plastic devices will provide excellent performance, essentially equivalent to hermetic performance.
Thermal resistance has been improved dramatically through the introduction of copper lead::
frames, and this results in lower junction temperatures, and subsequent improvements in electrical
characteristics and reliability performance.
'
Many users of integrated circuits continue to have requirements or preferences for hermetically
sealed ceramic packages. These requirements are usually based on applications in a highly humid
environment, increased temperature range or high power dissipation. Motorola produces two
different types of ceramic packaged devices: OERDIP andsidebraze.
The sidebraze, or solder seal, package is composed of three layers of alumina which are screened
with refractory metal such as tungsten or moly manganese and fired together to formthe package
body with a cavity for the die. The refractory metal is then plated and Alloy 42 leadframes ate
brazed to the bottom, sides or top of the package, depending on the vendor. The advantage of
the sidebraze version is accurate lead alignment without the need for forming. The final piece
part operation is plating, which may be gold ortin with a selective gold plate in the cavity. Although
epoxy die bonding is feasible inlh.!s package ,~due to the higher~ealing temperature, most
manufacturers, including Motorola, employ a eutectic bond. Both aluminum ultrasonic wire bonding and gold thermocompression bonding are used in this package.
The cerdip package is composed of two ceramic piece parts: the base and the cap. Sandwiched
between these two layers is a leadframe composed of Alloy 42 imbeded in a. sealing glass. the
leadframe requires a forming operation similar to a plastic dip. The die is mounted in this package
using a eutectic bond while the wire,bonds are aluminum (ultrasonic). A tinplate is applied to
the exterior leads of the 'package.
Some tradeoffs exist in the performance characteristics of the two hermetic packages as they are
offered by Motorola. Both typically are ceramic, hermetic, employ a eutectic die bond, use ultrasonic aluminum wire bonding, andhave tin plating onthe exterior leads. The thermal resistance
of the packages is very similar, with the sidebrazehaving a slight advantage. Both packages
perform well on the standard thermal and mechanical environmental tests, but each is susceptible
to handling damage. Loose shipping rail packaging or high velocity impacts during testing can
chip the sidebraze package and sever the interlayer metallization. This type of handling will not
effect the 10 mil thick leadframe of the CERDIP package, but hermeticity failures can occur. The
CERDIP package is slightly thicker and heavier, but no conductive surfaces are exposed so the
shorting potential in dense packaging is reduced. Extensive testing of 24,28, and 40 lead CERDIP
and sidebraze devices has indicated no significant differences in reliability.

RELIABILITY TEST
The following paragraphs describe. the various reliability test include~ in Motorola's Reliability
and Quality Assurance Program.

High Temperature Operating Life Test

High temperature operating life (HTOL) testing is performed to accelerate failure mechanisms
which are thermally activated through the application of extreme temperatures and the use of
dynamic operating conditions. The temperature and voltage conditions used in the stress are
typically 125°C with the bias level at the maximum data sheet specification limit of 5.5 volts. All

MOTOROLA MICROPROCESSOR DATA
2-3

II

devices used in the HTOL test are sampled directly after final electrical test with no prior burn-in
or other special screening~ Testing is performed with dynamic signals applied to the device for
a minimum test d!Jration of 1008 hours.
Device equival~nthours assume the Arrhenius relationship using an activation energy of 0.7 eV
to extrapolate from the device junction temperature at 125°C (ambient) to the junction temperature
at 70°C (ambient). Failure rates given in Failure in Time (FIT) are derived using the Chi-Square
distribution to a 90% confidence limit. A FIT is one failure per billion device hours of 0.0001%1
1000 hour.s.
.

Tables 2-1 through 2-3 show the results for the high temperature operating life test for packaging;
plastic, plastic leaded chip carrier (PLCC), and ceramic. Each of these tables also lists the different
technology used in the test. Table 2-4 lists the grand totals of Table 2-1 through 2-3 by technology
and packaging. Figure 2-1 shows a trend chart of the high temperature operating life by technology,
and Figure 2-2 is.a trend chart of the total of the high temperature operating life test.

Table 2-1. High Temperature Operating Life Test
PLASTIC
STRESS VOLTAGE: 5.5 Volts
TEMPERATURE: 125°C
LONGEST STRESS: 1008 Hours
Device
Type
NMOS DIP
MC3870
MC6800
MC6802
MCM6810
MC6840
MC6844
MC6845
MC6846
MC6850
MC6852
MC6854
MC68661
MC68652
MC68901
CUSTOM A
CUSTOM B
CUSTOM C
TOTAL
CMOS DIP
MC146805E2
MC146805F2
MC146805G2
MC146818
MC146818A
MC146823
TOTAL

Test
Devices

125°C
Device Hrs.

70°C Equiv.
Device Hrs.'

45
135
378
45.
135
45
45
45
135
45
45
135
45
45
945
525
1834

45,400
136,000
380,000
45,400
136,000
45,400
45,400
45,400
136,000
45,400
45,400
136,000
45,400
45,400
951,000
530,000
1,820,000

6.49 x 105
1.42x 106
5.41 x 106
4.13 x 105
1.37 x 106
5.00x 105
4.09 x 105
4.57x 105
1.63x 106
7.22 x 105
3.87 x 105
1.32x 106
3.90x 105
a.l0x 105
2.11 x 107
7~54 x 106
3.76x 107

4627

4,633,600

8.21 x 107

45
225
89
45
90
340

43,000
224,000
74,200
45,400
90,800
342,000

1.08 x 106
5.71 x 106
1.88x 106
1.17x 106
2.34x 106
8.82 x 106

819,400

2.10x10 7

---

--834

1) Activation energy used in equivalent device hour calculation is 0.7 ev)
2)90%:confidence.

MOTOROLA MICROPROCESSOR DATA
2-4

Failures
1
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
1

--4
0
1
0
0
0
0

--1

FITS2
0.7 eV
5970
1606
421
5521
1664
4561
5575
4990
1399
3158
5892
1727
5847
2815
252
302
103

--97
2111
679
1213
1949
974
259

--185

Table 2-1. High Temperature Operating Life Test
PLASTIC (Continued)
STRESS VOLTAGE: 5.5 Volts
TEMPERATURE: 125°C
LONGEST STRESS: 1008 Hours
Device
Type
HMOS DIP
MC2674
MC2681
MC6801
MC6801U4
MC6803U4
MC6804J2
MC6804P2
MC6805P2
MC6805P4
MC6805R2
MC6805R3
MC6805S2
MC6805S3
MC6805T2
MC6809
MC6809E
MC68000
MC68008
MC68010
MC68230
MC68681
TOTAL
HCMOS DIP
MC68HC05C4
MC68HC05C8
XC68HCOOO
TOTAL
PLASTIC DIP

Test
Devices
45
90
135
412
45
167
90
180
43
45
180
45
45
135
90
135
504
45
45
45
43

--2669
410
89
134

--633
8763

125°C
Device Hrs.

70°C Equiv.
Device Hrs.'

Failures

45,000
90,800
136,000
364,000
43,400
163,000
88,800
182,000
41,700
41,200
182,000
45,400
43,900
122,000
90,800
136,000
468,000
45,400
45,400
45,400
41,000

6.30 x 105
1.25x 106
1.42 x 106
5.09 x 106
5.95 x 105
3.16x 106
1.82 x 106
2.67 x 106
6.13x 105
4.36 x 105
1.92 x 106
7.20x 105
6.99 x 105
1.79x 106
1.37x 106
2.06 x 106
7.28 x 106
5 ..38 x 105
6.50x 105
8.90 x 105
6.50 x 105

2,567,200

3.78x107

389,000
89,800
134,000

9.94 x 106
2.29x 106
3.20x 106

612,800

1.55x107

--2

8,633,200

1.56x 108

11

1) Activation energy used in equivalent device hour calculation is 0.7 ev)
2) 90% confidence.

MOTOROLA MICROPROCESSOR DATA
2-5

0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
0
0

--4
1
0
1

FITS2
0.7 eV
3619
1824
1606
448
3832
722
1253
854
6321
5320
1188
3167
5543
2165
2828
1107
313
4238
3508
2562
3508

--211
390
996
1211

--343
106

I

Table 2-2. High Temperature Operating Life Test

PLCC
STRESS VOLTAGE: 5.5 Volts
TEMPERATURE: 125°C
LONGEST STRESS: 1008 Hours

I

Device
Type
HMOS ~LCC
MC6805R2
MC6805R3
CUSTOM D
CUSTOM E
TOTAL
HCMOS PLCC
MC68HC11
CUSTOM E
CUSTOM G
TOTAL
CMOS.PLCC
MC146805F2
MC146805G2
MC146818
MC146818A
TOTAL
PLCC

Test
Devices

125°C
Device Hrs.

70°C Equiv.
Device Hrs. 1

Failures

FITS2
0.7.eV

89
450
280
1189

--2008

81,900
430,000
279,000
1;200,000

8.34x 105
4.38 x 106
5.14x 106
2.20x 107

0
0
0
0

1,990,900

3.24x 107

--0

2734
512
444
104

2155
416
1358

2,160,000
417,000
1,360,000

5~66x107
7~.56x 106
2.46 x 107

14
1
2

3,937,000

8.87 x 107

--17

--266

45,400
89,000
45,400
88,900

1.17x 106
2.26x106
1.17x 106
2.26x 106

0
0
0
0

268,700

6.83 x 106

--0

1949
1009
1949
1009

6,196,600

1.28x 108

17

-3929
-45
90
45
89

--269
6206

--70
356 .
513
216

--334
184

1) Activation energy used in equivalent device hour calculation is 0.7 eV.
2) 90% confidence.

Table 2-3. High Temperature Operating Life Test

CERAMIC
STRESS VOLTAGE: 5.5 Volts
TEMPERATURE: 125°C
LONGEST STRESS: 1008 Hours
Device
Type
NMOS
MC6821L
MC6821S
MC6844S
MC6850
MC6850S
MC6852S
TOTAL
HCMOS
MC68020R
MC68605R
MC68824R
MC68851R
MC68882R
TOTAL

Test
Devices
44
45
135
90
45
45

--404
542
77
135
144
604
230

--1732

70°C Equiv.
Device Hrs. 1

Failures

FITS2
0.7 eV

44,300
45,400
136,000
90,800
45,400
44,000

6.02 x 105
6.18x 105
1.96x 106
1.39x 106
6.95 x 105
7.96x 105

0
0
0
0
0
0

405,900

6.06x 106

--0

3788
3690
1163
1640
3281
2865

--376

541,000
77,000
136,000
145,000
597,000
230,000

9.59x10 6
1.80x 106
3.00 x 106
3.19x 106
1.40x 107
5.30 x 106

2
0
0
1
2
0

554
1267
760
1215
379
430

1,726,000

3.69 x 107

125°C
Device Hrs.

1) Activation energy used in equivalent device hour calculation is 0.7 eV.
2) 90% confidence.

MOTOROLA MICROPROCESSOR DATA
2-6

--5

--251

Table 2-3. High Temperature Operating Life Test
CERAMIC (Continued)
STRESS VOLTAGE: 5.5 Volts
TEMPERATURE: 125°C
LONGEST STRESS: 1008,Hours
Device
Type
CMOS
MC1468705F2
MC14j38705F2S
TOTAL
HMOS
MC6803L
MC6809EL
MC6809ES
MC6809S
MC68701S
MC68701U4L
XC68704P2S
MC68705P3
MC68705S3
MC68000L
MC68000R
MC68010L
MC68010R
MC68230L
TOTAL
CERAMIC

Test
Devices

125°C
Device Hrs.

45
90
--135
45
45
45
90
45
45
300
45
45
170
248
94
45
90

--1352
3623

70°C Equiv.
Device Hrs.1

34,400
908,000

8.57xl0 6
2.28x 106

942,000

Failures

FITS2
0.7 eV

0

2661

3.14x 106

0
--0

1000
--726

45,400
45,400
45,400
90,800
45,400
45,400
301,000
45,400
45,400
171,000
245,000
94,000
45,400
90,800

6.40 x 105
7.07 x 105
6.25 x 105
1:25 x 106
4.74x 105
6.22 x 105
6.62x 106
7.00x 105
4.78x 105
2.53 x 106
3.93 x 106
1.52xl06
7.30 x 105
1.74x 106

0
0
.0
1
0
0
1
0
0
0
0
0
0
1

1,355,800

2.28x 107

--3

3563
3225
3648
3100
4811
3666
585
3258
4770
901
580
1500
3124
2227

4,433,700

6.89 x 107

8

--293
189

1) Activation energy used in equivalent device hour calculation is 0.7 eV.
2) 90% confidence.

Table 2-4. High Temperature Operating Life Test
TECHNOLOGY and PACKAGING
STRESS VOLTAGE: 5.5 Volts
TEMPERATURE: 125°C
LONGEST STRESS: 1008 Hours
Device
Type
NMOS
HMOS
CMOS
HCMOS
DIP
PLCC
PLASTIC
CERAMIC
GRAND TOTAL

125°C
Device Hrs.

5,031
1,238
6,294
( 8,763 )
( 6,206 )
([14,969])
[ 3,623)

5,039,500
5,913,900
2,030,100
6,275,000
( 8,633,000 )
( 6,196,600 )
([14,829,800])
[ 4,433,700)

8.82 x 107
9.30 x 107
3.10><10 7
1.41 x 108
1.56x 108
1.28 x 108
2.84x 108
6.89 x 108

24
11
17
28
8

91
127
125
224
106
184
127
189

18,592

19,259,300

3.53x 108

36

117

6,02~

70°C Equiv. ,
Device Hrs.1

FITS2
0.7 eV

Test
Devices

1) Activation energy used in equivalent device hour calculation is 0.7 eV.
2) 90% confidence.

MOTOROLA MICROPROCESSOR DATA
2-7

Failures
4
7

1

I

1;~~1_______________________________________
FAILURE
RATE
IN FITS

6 0 0 + - -- : : : :- - :-

;~l·~!~==~~~--------~
VR 1986

VR 1985

~
~

VR 1987

YEAR

1;~~1____________~______________~________
FAILURE
FlATE
IN FITS

600+---------------------------------------

I.·.·

5000~

400

~ ~-::--;;o:.::

300+

200.

10~ t
VR 1985

0

Ii'~

.•. ;

VR 1986

C.M)S.
·O··HCM)S

o

VR 1987

YEAR

Figure 2-1. High Temperature Operating Life Trend Chart
(By Technology)

MOTOROLA MICROPROCESSOR DATA
2-8

1

1985-1987

TOTALS

1000
900
800
700
FAILURE 600
RATE
500
IN FITS 400

I

;~n

.::

YR 1985

YR 1986
YEAR

=~
YR 1987

Figure 2-2. High Temperature Operating Life Trend Chart
(Total)

Temperature Humidity Bias Test
Temperature humidity bias (THB) is an environmental test performed at a temperature of 85°C
and a relative humidity of 85%. The test is designed to measure the moisture reistance of plastic
encapsulated circuits. A nominal voltage of 5 volts static bias is applied to the device to create
the electrolytic cells necessary to accelerate corrosion of the metallization. Testing is performed
to JEDEC Standard 22, Method A101. Most groups are tested to 1008 hours with some groups
extended beyond to look for longer term effects.
Table 2-5 shows the results of the temperature humidity bias test. Table 2-6 lists the grand total
of the devices tested in Table 2-5. Figure 2-3 shows the trend chart for the temperature humidity
bias test.

MOTOROLA MICROPROCESSOR DATA

2-9

Table 2-5. Temperature Humidity Bias Test
TEMPERATURE: 85°C
HUMIDITY: 85%
LONGEST STRESS: 1008 Hours
-

Device Type

I

NMOS DIP
MC6800
MC6802
MC6840
MC6845
MC6850
MC6852

0/68
0/34
0/68
0/34
0/34
0/34

TOTAL
HMOS DIP
MC6801
MC6802
MC6803U4
MC6804J2
MC6805P2
MC6805P4
MC6805P3
MC6805T2
MC6809
MC6809E
MC68000
MC68008
MC68010

0/68
1/34
0/68
0/34
0/34
0/34

0.00
2.94
0.00
: 0.00
0.00
0.00

--0/271

--0.37

0/68
0/34
0/34
0/222
0/34
0/34
0/68
0/68
0/34
0/102
0/136
0/94
0/34

0/67
0/34
0/34
0/222
0/34
2/34
0/67
0/65
0/34
0/102
0/134
0/94
0/34

0/66
0/34
0/34
0/222
0/34
0/32
0/67
0/65
0/34
0/102
0/134
1/93
0/29

0.00
0.00
0.00
0.00
0.00
5.88
0.00
0.00
0.00
0.00
0.00
1.08
0.00

TOTAL

-0/254
-0/299

--2/955
0.45

0/45

0.254
--0/299
0/68
0/34
0/68.
0/34
0/34

0/68
0/34
0/68

0/34
TOTAL

0/34
--0/238

-0/238
--

TOTAL

0/102
--0/102

0/102
--0/102

0/231
0/615

0/231 '
0/615
0/135
1/231

Hcnnos DIP
MC68HC05C4

0/68
0/33
0/68
0/34
0/34
0/34

% Failures

--1/272

--0/962

CMOS DIP
MC146804E2
MC146805F2
MC146805G2
MC146818A
. MC146823

1008 Hrs

--0/272

TOTAL
HMOS PLCC
MC68000
MC68705R3

Failures Per Sample -

504 Hrs

168 Hrs

--1/946
0/45
0/254
--0/299
0/68
0/34
0/68
0/34

--0.32
0.00
0.00
--OA)O
0.00
0.00
0.00
0.00
0.00

0/34
--0/238

--0.00

-0/102
--

0/102

0;00
--0.00

01231
0/615
0/135
0/230

0.00
0.00
0.00
0.43

'.'

HCMOS PLCC
XC68HC11A8
MC68HC11
MC68HCOOO
MC68605

0/135
0/231

TOTAL

-0/1212
--

--1/1212

MOTOROLA MICROPROCESSOR DATA

2-10

--0/1211

--0.083

Table 2-6. Temperature Humidity Bias Test
GRAND TOTAL
TEMPERATURE: 85°C
HUMIDITY: 85%
LONGEST STRESS: 1008 Hours
-

Device Type
NMOS
HMOS
HCMOS
CMOS
DIP
PLCC
GRAND TOTAL

Failures Per Sample -

168 Hrs

504 Hrs

1008 Hrs

0/272
0/1261
0/1314
0/238
0/1574
0/1511

11272
2/1254
1/1314
0/238
3/1567
1/1511

0/272
1/1245
0/1313
0/238
1/1558
0/1510

0.37
0.24
0.08
0.00
0.26
0.07

0/3085

4/3078

1/3068

0.163

% FailU,res "

0.9+---~~--------------------------------~~--------

CUM%

0.8+--------------------------------------------------0.7+---~------------------------------------------~~
0.6+---------------'-"'---------------'--'------------------

FAILURE 0.5+-------------------------------------------------~
RATE

~·~+
I-----------------------·.~-----'--------~~-----·a:-=·~
.
0.1 +-__
____________
..

~

~-------------------------------w

o ~--------------~----------~------------------------------~

VR 1986

VR 1985

• VR 1987

YEAR

Figure 2-3. Temperatore Humidity Bias Trend Chart
Autoclave Test
Autoclave, like THB, is an environmental test which measures device resistance to moisture
penetration along the leadframe-plastic interface. Conditions employed during the testinclude
121°C, 100% relative humidity, and 15 psig. Corrosion of the die is the expected failure mechanism.
Autoclave is a highly accelerated and destructive test performed per JEDEC Standard 22, Method
A102. Testing is routinely performed for 144 hours.
Table 2-7 lists the results of the autoclave test. Table 2-8 lists 'the grand total of the devices tested
in Table 2-7. Figure 2-4 shows the trend chart for the autociave test.

MOTORO~MICROPRcjCESSOR DATA
2-11

I

Table 2-7. Autoclave Test
TEMPERATURE: 121°C
PRESSURE: 15 psig
LONGEST STRESS: 144 Hours
-

Device Type

I

NMOS DIP
MC6800
MC6802
MC6840
MC6845
MC6846
MC6850
MC6852
MC6854
MC68661
MC68901
CUSTOM A
CUSTOM B
CUSTOM C
TOTAL
HCMOS DIP
MC68HC21
MC68HC05C4

96 Hrs

144 Hrs

0/44
0/22
0/44
0/22
0/22
0/65
0/22
0/44
0/22
0/22
0/330
0/462
0/847

0/44
0122
0/44
0/22
0/22
0/65
0122
0/44
0122
0/22
0/327
0/462
2/846

0/44
0/22
0/44
0/22
0/22
0/65
0/22
0/44
0/22

--0/1968

CMOS DIP
MC146805F2
MC146805G2
MC146818
MC146818A
MC146805E2
MC146805F2
MC146805G2
MC146823
MC1468705F2

--0.10

0/22
0/114

0/22
0/114

0.00
0.00

0/114

--0/136

--0/136

--0.00

0/65
0/44
0/192

0/65
0/44
0/192
0/394
0122
0/43
0/66
0/534
0/34

0/65
0/44
0/192
0/394
0/22
0/43
0/66

0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00

--0/136

0/66
0/534
0/34

HMOS DIP
MC2674
MC6801
MC6801U4
MC6802
MC6803U4
MC6804J2
MC6804P2
MC6805P2
MC6805R2
MC6805R3
. MC6805S2
MC6805S3
MC6805T2
MC6809
MC6809E
MC68000
MC68008
MC68010
MC68230
MC68661
MC68681

--0/1394

--0/1394

0/22
0/297
1/777
0/22
0/44
0/354
0/66
0/44
0/34
0/98
0/44
0/22

0/22
0/297
0/776
0/22
0/44
0/354
0/66
1/44
0/34
0/98 .
0/44
0/22
0/66

0/66
0/44
0/44
0/110
0/22

0/22
0/22
0/44

TOTAL

0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.24

--0/1960

0/394
0/22
0/43

TOTAL

0/22
0/326
0/462
0/843

% Failures

--2/1964

0/22
TOTAL

Failures Per Sample -

48 Hrs

0/65
--1/2263

0/34
--0/1394
0/22
0/297
1/776

0/22
0/44
0/354
0/66

0/43
0/34
0/98
0/44
0/22
0/66

0/43

0/43

0/44
0/110
0/22
0/22
0/22
0/44
0/64

0/44
0/110
0/22
0/22
0/22
0/44

--1/2260

MOTOROLA MICROPROCESSOR DATA

2-12

0/534

0/64
--1/2259

--0.00
0.00
0.00
0.13
0.00
0.00
0.00
0.00
2.32
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00

--0.13

Table 2-7. Autoclave Test (Continued)
TEMPERATURE: 121°C
PRESSURE: 1.5 psig
LONGEST STRESS: 144 Hours
-

Device Type
HMOS PLCC
MC6805R2
MC68705R3
CUSTOM D
CUSTOME

96 Hrs

144 Hrs

0/170
0/255
01434
1/693

0/170
0/255
01433
0/692

0/170
0/255
01432
0/691

-1/1552
--

TOTAL
HCMOS PLCC
MC68HC11
MC68HC11A8
MC68HCOOO
MC68605
CUSTOM E
CUSTOM G

1/1150
0/320
0/135
0145
1/363
0/770

TOTAL
CMOS PLCC
MC146805F2
MC146805G2
MC146818
MC146818A

% Failures
0.00
0.00
0.00
0.14

-0/1550
--

-0/1548
--

--0.06

011148

2/1146
0/320
0/135
0144
0/359
0/770

0.26
0.00
0.00
0.00
0.55
0.00

0/320
0/135
0145
1/361
0/770

--2/2783

-1/2779
--

--2/2775

-0.18
--

0/102
0/68
0/102
0/33

0/102
0/68
0/101
0/33

0/102
0/68
0/101
0/33

0.00
0.00
0.00
0.00

-0/305
--

TOTAL

Failures Per Sample -

48 Hrs

-0/304
--

--0/304

-0.00
--

Table 2-8. Autoclave Test
GRAND TOTAL
TEMPERATURE: 121°C
PRESSURE: 15 psig
LONGEST STRESS: 144 Hours
Device Type
NMOS
HMOS
HCMOS
CMOS
DIP
PLCC
GRAND TOTAL

-

Failures Per Sample -

% Failures

48 Hrs

96 Hrs

144. Hrs

0/1968
2/3815
2/2919
0/1699
1/5761
3/4640

2/1963
1/3810
1/2915
0/1698
3/5753
1/4633

0/1959
1/3807
2/2909
0/1698
1/5748
2/4625

0.10
0.10
0.17
0.00
0.09
0.13

4/10401

4/10386

3/10373

0.106

MOTOROLA MICROPROCESSOR DATA

2·13

I

1 ~----------------~--~------------~-------------

0.9+-------------------------------------------------0.8+-------------------------------------------------0.7+-------------------------------------------~~---

CUM %
FAILURE

I

RATE

0.6
0.5+---~~--------------------------------------~~

0.4 +-~--------.-....~-~.-------------------~-~

~:~ r·l~---------..............:=.:~~::::::=5±.

0.1

+---~-------I---------=

a
YR 1985

.

I

YR 1986

YR 1987

YEAR
Figure 2-4. Autoclave Trend Chart

Temperature Cycle Test

Temperature cycle testing accelerates the effects of thermal expansion mismatch among the
different components within a specific packaging system. During temperature cycle testing, devices are inserted into a cycling system and held at the cold (- 65°C) dwell temperature for at
least ten minutes. Following this cold dwell, the devices are heated to the hot (+ 105°C) dwell
where they remain for another ten minute minimum time period. The system employs a circulating
air environment to assure rapid stabilization at the specified temperature. The dwell at each
extreme, plus the two transition times of five minutes each (one up to the hot dwell temperature,
another down to the cold dwell temperature), constitutes one cycle. Test duration is for 1000
cycles with some tests extended to look for longer term effects.
Table 2-9 lists the test results of the temperature cycle test testing at a temperature range of a
- 65°C to 150°C. Table 2-10 lists the grand total of the devices tested in Table 2-9. Table 2-11 lists
the test results of the temperature cycle test testing at a temperature range of a - 50°C to 150°C.
Table 2-12 lists the grand total of the devices and results of Table 2-11: Figure 2~5 shows the trend
chart for the temperature cycle test.

MOTOROLA MICROPROCESSOR DATA
2~14

Tabl.e2-9.

Temp~rature

Cycle Test

TEMPERATURE: -65°C to + 150°C
STRESS METHOD: Air to Air
LONGEST STRESS: 1000 Cycles
-

...

Device Type
NMOS DIP
MC3870
MC6800
MCM6810
MC6840
MC6844
MC6845
MC6846
MC6850
MC6852
MC6854
MC68661
CUSTOM A
CUSTOM B
CUSTOM C
TOTAL
NMOS CERAMIC
MC6821S
MC6821L
MC6844S
MC6850
TOTAL
HMOS PLCC
MC6805R2
MC6805R3
CUSTOM E

500 eye

1K eye

0/38
0/114
0/38
0/114
0/38
0/38
0/38
0/114
0/76
0/38
0/38
0/307
0/115
0/1306

0/38
0/114
0137
0/114
0/38
0/38
0/38
0/114
0/76
0/38
0/38
0/307
0/115
0/1306

0/38
0/114
0137
0/114
0/38
1/38
0/38
1/114
0/76
0/38
0/38
0/307
0/115
3/1306

--0/2412

-0/2411
--

0/38
0/38
0/114
0/114

0/38
0/38
0/114
0/114

--0/304
0/152
0/38
0/153

TOTAL
HMOS DIP
MC2674
MC6801
MC6801U4
MC6802
MC6803U4
MC6804J2
MC6804P2
MC6805P2
MC6805P4
MC6805P6
MC6805S2
MC6805R2
MC6805R3
MC6805S2
MC6805S3
MC6805T2
MC6809E
MC6809
TOTAL

Failures Per Sample -

100 eye

--5/2411
0/38
0/38
0/114
0/114

% Failures
0.00
0.00
0.00
0.00
0.00
2.63
...0.00
0.88
0.00
0.00
0.00
0.00
0.00
0.23

-0.21
-0.00
0.00
0.00
0.00

-0/304
--

-0/304
--

-0.00
--

3/152
0/38
1/153

4/149
0/38
01152

4.61
0.00
0.65

-0/343
--

--4/343

-4/339
--

--2.36

0137
0/546
0/668
0/38
01114
0/76
0/114
0176
0/38
1/432
1/38
0/38
0/152
0/38
0/37
0/114
1/114
0/76

0137
1/546
0/653
0/38
01114
0/76
0/114
0176
0/38
2/429
0137
0/38
0/152
0/38
0137
0/114
0/113
0/76

0/37
2/542
0/638
0/38
0/114
0/76
0/114
0175
0/38
0/427
0/37
0/38
3/152
0/38
0/37
0/114
0/113
0/76

0.00
0.55
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.69
2.63
0.00
1.97
0.00
0.00
0.00
0.88
0.00

-3/2746
--

-3/2726
--

MOTOROLA MICROPROCESSOR DATA

2-15

-5/2704
--

-0.40
--

II

Table 2-9. Temperature Cycle Test (Continued)
TEMPERATURE: -65°C to + 150°C
STRESS METHOD: Air to Air
LONGEST STRESS: 1000 Cycles
-

Device Type

I

HMOS CERAMIC
MC6801L
MC6809EL
MC6809ES
MC6809S
MC68120L
MC68701
MC68701U4L
MC68705P3
MC68705S3S
MC68000L
MC68000R
MC68010R
MC68230L
MC68451L
MC6890.1L
TOTAL
HCMOS PLCC
MC68HCll
MC68881
XC68882
CUSTOM E
CUSTOM G

500 eye

1K eye

0/38
0/38
0/38
0176
0176
0/38
0/38
0/38
0/38
0/113
0/38
0/38
0/38
0/36
0/38

0/38
0/38
0/38
0/76
0/76
0/38

0/38
0/38
3/38
2/76
0/76
0/38

-01719
-1/538
0178
1/135
0/253
0/1153

TOTAL
HCMOS DIP
MC68HC05C4
MC68HC05C8
MC68HC21

--2/2157

0137

0/38
0/38
0/112
0/38

0/38
0/38
0/36
0/38

-01717
-0/537

0/78
0/134
4/252
1/1153

HCMOS CERAMIC
MC68020R
MC68605R
MC68824R
MC68851R
MC68881R
MC68704P2
TOTAL
CMOS PLCC
MC146805F2
MC146805G2
MC146818
MC146818A

CMOS DIP
MC146805E2
MC146805F2
MC146805G2
MC146818
MC146818A
MC146823
MC1468705F2
TOTAL

-0.84
--

2/535
0/78
0/134
5/246
2/1150

0.56
0.00
0.74
3.56
0.26

0/223
0/338
0/109

0/223
3/338
0/109

0.00
0.89
0.00

-0/670
--

0177
0/231
0/231
0177
0174
0/135

0/231
0/231
0/77
0/74
0/135

0177

--0/825

0176

0/76

0/114

0/114

0/38
TOTAL

-6/716
--

--0.74

--0/670

--0/825

0.00
0.00
7.89
2.63
0.00
0.00
0.00
2.63
0.00
0.00
0.00
0.00
0.00
0.00
0.00

--9/2143

0/223
0/109

0137
1138

0/38
0/112
0/37
0/38
0/38
0/36
0/38

% Failures

--5/2154

0/338
TOTAL

Failures Per Sample -

100 eye

0/38

-3/670
-0/77
0/231
1/230
0/77

0174

--0.45
0.00
0.00
0.43
0.00
0.00
0.00

0/135

-1/8~4
--

--0.12

0/76
0/113
0/38
0/76

0.00
0.00
0.00
0.00

0176
--0/304

0176
--0/304

-0/303
--

-0.00
--

0/38
0/190
0/152
0/38
0/76
0176
0/38

0/38
0/189
0/152

0/38
0/189
0/152
0/38
0/76
0/76
0/38

0.00
0.00
0.00
0.00
0.00
0.00
0.00

-0/608
--

0/38
0/76

0/76
0/38

-0/607
--

MOTOROLA MICROPROCESSOR DATA

2-16

--0/607

-0.00
--

Table 2-10. Temperature Cycle Test
GRAND TOTAL
TEMPERATURE: -65°C to + 150°C
STRESS METHOD: Air to Air
LONGEST STRESS: 1000 Cycles
-

Device Type

Failures Per Sample -

100 eye

500 eye

1K eye

% Failures

NMOS
HMOS
CMOS
HCMOS
PLCC
DIP
PLASTIC
CERMAIC

0/2716
3/3808
0/912
2/3652
2/2804
3/6436
5/9240
0/1848

0/2715
7/3786
0/911
5/3649
9/2801
3/6414
12/9215
0/1846

5/2715
15/3759
0/910
10/3637
13/2785
10/6392
23/9177
7/1844

0.18
0.67
0.00
0.47
0.86
0.25
0.44
0.38

GRAND TOTAL

5/11088

12/11061

30/11021

0.43

Table 2-11. Temperature Cycle Test
TEMPERATURE: -50°C to + 150°C
STRESS METHOD: Air to Air
LONGEST STRESS: 1000 Cycles
-

Device Type
NMOS DIP
MC68661
MC68901
TOTAL
HMOS DIP
MC6801
MC6801U4
MC68000
MC68008
MC68230
MC68681

500 eye

1K eye

% Failures

0/114
0/38

0/114
0/38

0/114
0/38

0.00
0.00

--0/152
0/231
0177
0/114
0/38
0/38
0/112

TOTAL
HMOS PLCC
MC68HC11
MC68705R3
CUSTOM G
CUSTOM E
TOTAL
HMOS PLCC
MC68HC11A8
MC68881
CUSTOM E
CUSTOM G

--0/152
0/231
0177
0/114

0/38
0/38
0/111

--0/152

--0.00

0/231
0/77
0/107
1/38
1/38
0/111

0.00
0.00
0.00
2.63
2.63
0.00

--0/610

--0/609

--2/602

--0.33

0/384
0/107
On37
0/154

0/384
0/107
1/737
0/154

0/384
0/107
0/736
0/154

0.00
0.00
0.14
0.00

--0/1382
0/80
1/76
2/198
0/308

TOTAL

Failures Per Sample -

100 eye

--3/662

--1/1382
0/80
0/75
2/195
0/308

--2/658

MOTOROLA 'MICROPROCESSOR DATA
2-17

--0/1381
0/80
0/75
11191
0/308

--1/654

--0.07
0.00
1.32
2.53
0.00

--0.92

II

Table 2-12. Temperature Cycle Test

GRAND TOTAL
TEMPERATURE: -50°C to + 150°C
STRESS METHOD: Air to Air
LONGEST STRESS: 1000 Cycles

I

Device Type

-

Failures Per Sample -

100 eye

500 eye

1K eye

% Failures

NMOS
HMOS
HCMOS
PlCC
DIP

0/152
0/1992
3/662
3/2044
0/762

0/152
1/1991
2/658
3/2040
0/761

0/152
2/1983
1/654
1/2035
2/754

0.00
0.15
0.92
0.34
0.27

GRAND TOTAL

3/2806

3/2801

3/2789

0.32

1•
0.9
0.8
0.7
CUM % 0.6
FAILURE 0.5
RATE 0.4
0.3
0.2
0.1
0
YR 1985

YR 1986

YR 1987

YEAR
Figure 2-5. Temperature Cycle Trend Chart

Thermal Shock Test
The objective of thermal shock testing is the same as that for temperature cycle testing - to
emphasi~e differences in expansion coefficients for components of the packaging system. However, thermal' shock provides additional stress in that the device is exposed toa sudden change
in temperature due to the transfer time of ten seconds maximum as well as the increased thermal
conductivity of a liquid ambient. Devices are placed In a flourocarbon bath and cooled to - 65°C.
After being held in the cold chamber for five minutes minimum, the devices are transferred to
an adjacent chamber filled with flourocarbonat + 150°C for an equivalent time. Two five minute
dwells plus two ten second transitions constitute one cycle~ Test duration is normally for 1000
cycles with some tests being extended to look for longer term effects.
Table 2-13 lists the results of the thermal shock test and Table 2-14 lists the grand total of Table
2-13. Figure 2-6 shows the trend chart for the thermal chart for the thermal shock test.

MOTOROLA MICROPROCeSSOR DATA
2-18

Table 2-13. Thermal Shock Test
TEMPERATURE: -65°C to + 150°C
STRESS METHOD: Liquid to Liquid
LONGEST STRESS: 1000 Cycles
-

Device Type
NMOS DIP
MC2674
MC3870
MC6800
MC6802.
MCM6810
MC6846
MC6850
MC68488
MC68661
TOTAL
HMOS DIP
MC6801
MC6803U4
MC6804J2
MC6804P2
MC6805P2
MC6805P4
MC6805P6
MC6805R3
MC6805S2
MC6805S3
MC6805T2
MC68661
MC68681
MC68901

500 eye

1K eye

0/34
0/135
0/34
0/34
0/34
0/34
0/68
0/34
0/68

0/34
2/135
0/34
0/34
0/34
0/34
0/68
0/34
0/68

0/34
0/133
0/34
0/34
0/34
0/29
0/67
0/34
1/68

--0/475
0/432
0/68
0/343
0/34
0/68
'0/34
0/432
0/34
0/68
0/34
0/34
0/34
0/102
0/33

TOTAL
HMOS CERAMIC
MC6801L
MC6850
MC68000L
MC68010R
MC68451L

-0/1750
-0/38
0/38
0/38
0/38
0/38

TOTAL
HCMOS DIP
XC68HC01
MC68HC05C8

--0/190
0/34
0/68

TOTAL
HMOS PLCC
MC68HC11

--0/102

-2/474
-0/431
0/68
0/343
0/34
0/68
0/34
4/432
0/34
0/68
0/34
0/34
0/34
0/102
0/34

--4/1750
0/38
0/38
0/36
0/38
0/38

--0/188
0/34
0/68

TOTAL
CMOS DIP
MC146805G2
MC146805F2
MC146818
MC146823

~/~67

0/34
0/68
0/34
0/34

TOTAL

--0/170

0/431
0/68
0/343
0/34
0/68
0/34
0/428
0/34
0/68
2/32
0/34
0/33
0/95
0/33

--2/1735
0137
0/37
0/36
0/38
0/36

--0/184
0/34
0/68

0.00
1.48
0.00
0.00
0.00
0.00
0.00
0.00
1.47

--0.64
0.00
0.00
0.00
0.00
0.00
0.00
0.93
0.00
0.00
5.88
0.00
0.00
0.00
0.00

--0.34
0.00
0.00
0.00
0.00
0.00

--0.00
0.00
0.00

--0/102

--0.00

2/614

0/612

0.33

0/462
0/205
---

--1/467

% Failures

-0/102
--

0/615

HCMOS CERAMIC
MC68020R
MC68881R

Failures Per Sample -

100 eye

0/461
0/205
--0/666
0/34
0/68
0/34
0/34

--0/170

MOTOROLA MICROPROCESSOR DATA

2-19

1/459
0/199

-1/658
-0/31
0/68
0/33
0/34

--0/166

0.22
0.00
--0.15
0.00
0.00.
0.00
0.00

--0.00

Table 2-14. Thermal Shock Test
GRAND TOTAL
TEMPERATURE: -65°C to +150°C
STRESS METHOD: Liquid to Liquid
LONGEST STRESS: 1000 Cycles

I

Device Type

-

Failures Per Sample -

100 eye

500 eye

1K eye

% Failures

NMOS
HMOS
CMOS
HCMOS
PLCC
DIP
PLASTIC
CERAMIC

0/475
0/1941
0/170
0/769
0/615
0/3355
0/3113
0/857

2/474
4/1938
0/170
2/614
6/3350
8/3110
0/854

1/467
2/1919
0/166
1/760
0/612
4/3312
3/3082
1/842

0.64
0.31
0.00
0.13
0.33
0.30
0.35
0.12

GRAND TOTAL

0/3970

8/3964

4/3924

0.30

01768

VR 1986

VR 1987

YEAR

Figure 2-6. Thermal Shock Trend Chart

Data Retention Test
Data retention testing or high temperature storage is performed to measure the stability of the
programmed EPROM and EEPROM devices during storage at elevated temperatures with no
electrical stress applied. The devices are stored at an ambient of 150°C. An acceleration of charge
loss from the storage cellis the expected result. All groups are typically tested to 1008 hours.
Table 2-15 lists the results and the grand total of the data retention test. Figure 2-7 shows the
trend chart for the data retention bake test.

MOTOROLA MICROPROCESSOR DATA
2-20

Table 2-15. Data Retention Test

TEMPERATURE: 150°C
LONGEST STRESS: 1008 Hours
-

Device Type

168 Hrs.

HMOS CERAMIC
MC1468705F2
MC68701U4
MC68705R3
MC68704P2
MC68701

0178
0/44
0/45
0/442
0/45

Failures Per Sample -

504 Hrs.

1008 Hrs.

0178
0/44
0/45
0/442
0/45

% Failures

0178
0/44
0/45
0/442
0/45

0.00
0,00
0.00
0.00
0.00

--0/654

--0/654

--0/654

--0.00

HMOS DIP
MC68000

0/100

0/100

0/100

0.00

HMOS PLCC
MC68705R3

1/2044

0/2043

1/2043

0.10

HCMOS PLCC
XC68HCllA8*
MC68HCllA8*

1/385
2/1668

0/381
2/1667

0/377
2/1665

0.26
0.36

TOTAL

--3/2053

--2/2048

--2/2042

HMOS
HCMOS

1/2798
3/2053

0/2797
2/2048

1/2797
2/2042

GRAND TOTAL

4/4851

2/4845

3/4839

TOTAL

--0.34
0.07
0.3
45
0.19

*These EEPROM units were prestressed through 10K writelerase cycles.

0.5TI--~~--------------------------~---------------

0.45-'0.4
0.35

...............

CUM % 0.3
FAILURE 0.25
RATE
0.2

----........... - ..............

-..............

--............. -.

0.15
0.1
0.05

o
YR 1985

YR 1986

YR 1987

YEAR

Figure 2-7. Data Retention Bake Trend Chart

EEPROM Write/Erase Cycling Test

The write/erase endurance test measures EEPROM cell operation over an expected life time. All
cells are alternately cycled for 10,000 cycles between an'erased state "1" and a write state "0"
at the device high temperature specification of 85°C. The most common failure mode is failure
to write a "0" within the 10 msec specification limit.

MOTOROLA MICROPROCESSOR DATA
2-21

I

Table 2-16 lists the results and grana totaldftheEEPROM write/erase cycling test. Table 2-17 lists
the average outgoing quality from year 1979 through 1987.

Table 2-16. EEPROM Writ~/Erase Cycling Test

I

VOLTAGE: 5.5 Volts
TEMPERATURE: 85°C
LONGEST STRESS: 10K Cycles
Devic.e Type
HCMOS P·LCC
XC68HC11A8
(Mask: 18960)
XC68HC11A8
(Mask: 28960)
MC68HC11A8
(Mask: 28960)
MC68HC11A8
(Mask: 78960)
TOTAL

-

Failures Per Sample -

1K cyc

2K cyc

5Kcyc

SK cyc

10K cyc

1/288

1/287

3/286

0/283

1/283

3/642

2/633

2/629

2/627

0/625

1:42

11314

1/313

0/312

0/312

0/312

0.64

3/1289

0/1286

0/1286

1/1286

1/1285

0.39

4/2519 .

5/2513

3/2508

2/2505

0.87

Failure
..

8/2533

2.10

.. '

WritelErase Cycling Failure. Rate Calculation
Device Type
HCMOS PLCC
MC68HC11A8
(Mask: 1 & 28960)
MC68HC11A8
(Mask: 78960 (Curfent Mask))
GRAND TOTAL

Test
Device

85°C
Device Hrs.

70°C Equiv.
Device cyc 1

Failures

% 1K cyc
0,53 eV 2

1244

12,440,000

2.58x10 7

17

0.090

1289

12,900,000

2.67 x 107

5

0.035

2533

25,340,000

5.24 x 107

22

0.056

1) Activation energy used In equivalent device cycle calculation is 0.53 eV.
2) 90% confidence.

Table 2-17. Average Outgoing Quality
Time Frame
Year
Year
Year
Year
Year
Year
Year
Year
Year

1979
1980
1981
1982
1983
1984
1985
1986
1987

Goal
(PPM)

Electrical
AOa (PPM)
Actual

Visual/Mech.
AOa(PPM)
Actual

3000
2500
1500
900
425
200
80
50
50

(-)4000
(-)2000
1725
717
383
419
272
291
232

(-)4500
(-)2500
1920
1103
380
403
137
509
190

MOTOROLA MICROPROCESSOR DATA
2~22

RESULTS AND CONCLUSION

The 1987 Microprocessor Reliability results indicate that the major product lines have excellent
overall reliability performance. The reliability performance of our products is evalu.ated through
extensive stress/testing which includes life test, temperature cycle, thermal slwck, THB, autoclave,
and data retention bake. Thisyear's results indicate there are many areas where significant gains
were made in reliability performance as compared to the 1986 results ..
The overall High Temperature Operating Life test result for the year was excellent with a failure
rate of 117 FITs compared tathe 1986 yearly total of 264 FITs (based on 0.7 eV). Failure rate
improvements were seen in all ofthe key process technologies during the year. The life test failure
rate for NMOS was 91 FITs which is a 55% improvement compared to the previous yearly results.
The HMOS failure rate improved to a 127 FIT level as compared to the 467 FIT level this technology
achieved in 1986. The HCMOS failure rate was 224 FITs which is a 16% improvement in the 1986
figure. The 5 micron CMOS technology achieved a failure rate of 125 FITs which is excellent and
a significant improvement over 1986.
The environmental results for 1987 indicate that our products lines Clre capable of meeting rigid
environmental extremes with very low failure rates. The actuar stress results for the various
thermal cycling and moisture tests are detailed below.
The temperature cycle results for 1987 improved to an overall 0.43% cumulative failure rate
through 1000 cycles. This is a 51% gain over the 1986 figures. Thermal shock results for this
period also improved substantially to a 0.30% level. These figures are excellent.
Both temperature humidity bias and autoclave produced improved failure rate performance during
1987. Temperature humidity bias achieved a 0.16% cumulative failure rate through 1008 hours.
The autoclave test for this time frame resulted in a 0.1-1% figure which is a 56% improvement
over 1986.

Data retention bake, which is used to evaluate the ability oftheMCUEPROM and EEPROM devices
to store charge over an extended period of time, has a cumulative percent fallout of 0, 19%. This
figure has improved 42% during 1987 as compared to the previous yeC!rs results.
Write/erase cycling, which was begun this year to measure the MCUEEPROMarrays operational
endurance over an expected life time, resulted in an overall failure rate of 0.056%/1 K cycles at
70°C. The most recent material evaluated in the 4th quarter of 1987 achieved a 0.035%/1 K cycles
failure rate.
.
Average Outgoing Quality levels for both electrical and visual/mechanical performance improved
for 1987. The yearly figures are 232 ppm for electrical and 190 ppm for visual/mechanical.

In summary, the Motorola Microprocessor Product Group's products are achieving very high
levels of reliability and quality performance. Improvements in many key areas have been made
during the course ofthe year, and as a group our goal will be to continually upgrade the Reliability
and Quality of our products.
For more information, contact Microprocessor Reliability Engineering at 512/440-2530 or write to:
Microprocessor Reliability Engineering
,Motorola Inc.
6501 William Cannon Drive West
Austin, Texas 78735-8598

MOTOROLA MICROPROCESSOR DATA
2-23

II

FAILURE RATE CALCULATIONS

I

Environmental tests are designed to measure device resistance to unusual and severe stress not
expected under normal operating' conditions. Device performance under these conditions is expressed as a percent of devices defective and compared to previous results. Life tests, on the
other hand, accelerate the use conditions of the device with temperature and voltage in a manner
which is more quantitatively correlatable to system operation. Life test failure rates are expressed
as failures per unit time and are calculated using established principles or probability and statistics.
The principles of reliability engineering have indicated that failure rates for semiconductor devices
will take the form of the"bathtub" curve (Figure 2-8).

CLASSICAL FAILURE RATE CURVE

t

FAILURE

REGION 2

RATE

,

,~----~--------------------TIME

Figure 2-8. Device Failure Rate as a Function of Time
The following three regions are represented in the curve:
1. Infant Mortality - a region of hi'gh bur rapidly declining failure rates, usually associated with
manufacturing defects.
2. Random Failures - a region of low, random failures caused by more subtle defects. This
area of the curve represents the useful part of device life.
3. Wearout- a region of rapidly rising failure rates related to device wearout. Most semiconductors will not reach this stage before they are replaced because of changes in technology.
Techniques for calculating life test fCiilure rates assume that the devic,es being tested have passed
infant mortality and entered the stable random failure portion of the life curve. Failures which
occur in this area are few and are known to approximate specific probability distributions. These
probability distributions are used to calculate sample failure rates which can be projected to the
population in general through the application of confidence limits. Techniques ,us,ed to calculate
'
life test failure rates for micorprocessors are discussed below.
A failure rate for any sample of life tested devices can be determined by dividing the number of
failures by the number of device hours. However, this rate will apply to that sample pnly. Ff you
are interested in projecting from the sample to the population in general, you must establish
confidence limits. The application of confidence limits is a statement of how "confident" you are
that the sample failure rate approximates that for the population in general. To obtain rates with
different confidence levels, it is necessary to make use of specific probability distributions which
take the same form as the actual failure distribution.

MOTOROLA MICROPROCESSOR DATA
2-24

It has been determined that failures in semiconductors that have entered the middle portion of
the bathtub curve will approximate a Poisson distribution; this distribution applies when one has
a large sample with an extremely small number of events of interest, such as device failures.
Given a Poisson failure process, a Chi~Square distribution can be used to establish confidence
limits for failure rates. R&QA Engineering has determined that the following general formula,
which utilizes values from a Chi-Square table, can be used to calculate failure rates for semiconductors:
(a , d.f)
A.::::.;X 2- - 2t

(1 )

where:
A.
x2

= Failure Rate
= Chi-Square Function
100 - Confidence Level

a

100
d.f. = Degrees of Freedom=2r+2
r
= Number of Rejects
t
= Device Hours

To calculate the failure rate, first determine the level of confidence you require and calculate
degrees of freedom. Select the Chi-Square value for a Chi-Square distribution table with the
appropriate degrees of freedom and confidence level. Divide that value by twice the actual device
hours, at the temperature of interest.
The above formula applies for calculating a device failure rate, provided that the test is conducted
at system temperature. However, since we are unable to observe long-term effects which develop
over time, the test is accelerated through the application of a high temperature. In oder to calculate
a failure rate at the ambient temperature of a system, a factor must be supplied to compensate
for the acceleration. The factor (Fa) which equates test temperature with rated temperature is
derived from the Arrhenius relationship:
Fa=exp( (/k)·

(1 -1) )

Tr

Tt

(2)

where:
Fa


k
Tr

= Acceleration Factor
= Activation Energy, eV
= Boltzman's Constant, 8.62 x 10 - 5 eV/K
= Junction Temperature, K at the Rated
Ambient of 70 C
= Junction Temperature, K at the Life Test
Ambient of 125 C
D

Tt

D

Motorola uses 70 C for the system temperature (To) to more closely approximate the actual
temperature of the device during system operation and to supply a degree of conservatism to
the failure rate calculation.
D

Motorola uses an activation energy value of 0.7 electron volt. A 0.7 eV was selected as an average
value because a variety of different failure mechanisms exist for microprocessor and other VLSI

MOTOROLA MICROPROCESSOR DATA
2-25

II

devices, with activation energies ranging from 0.40 eV for oxide related failuresto 1.0 eV or greater
for contamination and metal related failures; Tr and Tt. of the equation are the average junction
temperatures present at the rated and testambients. Motorola uses junction, rather than ambient
temperature, because they, produce acceleration factors that are more conservative ahdrepresentative of actual conditions,' These temperatures are calculated as follows:
.
(3)

where:
TJ
TA
Po
6JA

= Junction Temperature, °C
= Ambient Temperature, °C
= Average Power Dissipation, Watts
=Thermal Resistance - Junction to Ambient,
°C Per Watt

Once this step has been 'completed, the acceleration factor can be calculated and applied as a
multiplier to the number of device test hours under accelerated test conditions to determine the
equivalent number of hours at rated operating conditions. To determine the failure rate at the
operating temperature use equation (1) substituting the equivalent device hours at rated temperature for t in the equation.
Equation (1) provides a failure rate expressed in percent per thousand hours. This number, stated
as.a percentage per each thousand hours of operation, is one way Motorola R&QA Engineering
expresses failure rates for Microprocessors. One other way of expressing failure rates is Failures
In Time (FITs) which refers to failed units per 109 device hours (1 FIT=x.x 104 ).
Mean Time To Failure (MTTF) is another parameter frequently used to express failure rates. MTTF
is the average:time to a failure of anonrepairable item such as a semiconductor and is expressed
as the reciprocal-of th.e failure rate:
1

MTTF=X.

MOTOROLA.MICROPROCEsseR DATA
2-26

(4)

Data Sheets
Volume I and"

This chapter (found in both Volume I and Volume II) contains the data sheets
for the Microprocessors, Microcontrollers, and Peripheral devices. For information
on packaging, refer to Chapter 4. Ordering forms are located in Chapter 6.

MOTOROLA MICROPROCESSOR DATA

I

I

MOTOROLA MICROPROCESSOR DATA

MOTOROLA

.. SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC2672

Advance Information

Programmable Video Timing Controller
(PVTC)
The MC2672 programmable video timing controller (PVTC) is a programmable device designed
for use in CRT terminals and displays systems that employ raster scan techniques. The PVTC generates the vertical and horizontal timing signals necessary for the display of interlaced or non-interlaced data on a CRT monitor. It provides consecutive addressing to a user specified display buffer
memory domain and controls the CPU-display buffer interface for various buffer configuration
modes. A variety of operating modes, display formats, and timing profiles can be implemented by
programming the control registers in the PVTC. Applications include CRT terminals, word-processing systems, small business computers, and home computers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

4 MHz Character Rate
Up to 256 Characters Per Row
1 to 16 Raster Lines Per Character Row
Up to 128 Character Rows Per Frame
Programmable Horizontal and Vertical Sync Generators
Interlaced or Non-Interlaced Operation
Up to 16K RAM Addressing for Multiple Page Operation
Automatic Wraparound of RAM
Addressable, Incrementable, and Readable Cursor
Programmable Cursor Size, Position, and Blink
Split Screen and Horizontal Scroll Capability
Light Pen Register
Selectable Buffer Interfce Modes
Dynamic RAM Refresh
Completely TIL Compatible
Single + 5-Volt Power Supply
Power-On Reset Circuit

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-1

I

MC2672

BLOCK DIAGRAM

Interface

CE

Control
Initialization
and Display
,Registers

R
Read/Write
Control Logic

Vii

. CTRl1
Display
Memory
Handshake
Logic

Command
Decode
Logic

CTRL2
CTRL3

Display
Address
Timing
Multiplexers

Interrupt
Logic and
Status
Register

Address
Decoder

I

Cursor,
Pointer, and
Light Pen
Registers

Light Pen Strobe

INTR
Cursor and
Compare
Logic

CURSOR

~
HSYNC

~

Timing Chain
and
Decode Logic

Clock
Buffer

CClK

VSYNC/CSYNC
BLANK

Timing

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Vce
Vin
TA

-0,3 to + 7.0

Tst9

-55 to + 150

Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature Range

Unit
V

-0,3 to + 7,0

V

o to 70

°e
°e

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic Package

Symbol

Value

Rating

8JA

50

°C/W

MOTOROLA MICROPROCESSOR DATA

3·2

This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields;
however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximumrated voltages to this high-impedance
circuit. For proper operation it is recommended that Yin and Vout be constrained to the range GND~(Vin or
Vout)~VCC. Reliability of operation is
enhanced if unused inputs are tied to
an appropriate logic voltage level (e.g.,
either GND or VCC).

MC2672

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can be obtained from:
(1 )

TJ=TA +(PO" 9JA)
where:
TA
9JA

= Ambient Temperature, °C
= Package Thermal Resistance,
Junction-to-Ambient, °CIW
PD
= PINT+PPORT
= ICC x VCC, Watts - Chip Internal Power
PINT
PPORT = Port Power Dissipation, Watts - User Determined

For most applications PPORT

UJ

c

"0

8-------

-.-.-e-.-.--

0-------2-0-------

3

L2 - .

~L3

-.------17 Scan
Lines/
Row

l

~L1-'

~

1-0-0-0-0-'-0--

2,-.------9 Scan
Lines/
Row

I

~~~=:)-

-.------3·0-------e-.-.----4-0-0-0-----

-e------5-0---e------6-0-------

7 .-.-.-.-.-7 '0-0-0-0-0--

i ~ :~ I~ I~~::
Row

0 0----

'5-0------

6 - · - 0- - - - 8!7-000

0----

10------1 -• • • • • - - - -

31~~------

4-000-----

56-~------

8--------

8 --------

0-------1 -e-.-e-e-.--

o I_O_ _~_ _~___

7 - •••••- - - 8-------

1-0-0-0-0-0-12-~-e-e-.-e--

0'1-00000----

2 ~e------3-0------3-e-------

41~~ •• - - - - -

4-0-0-0----

617-~0000----

2-e------3-e ------4 -e-.-e-----

5 -e
6- e ------7 -e-e-.-.-e--

8--------

1

4 -e-e-.----5-0------5 -e------6·0-------

6 .------7 -0-0-0-0-0-7

-e-.-.-e-.--

18--------

00
- -----------

2-·-----'5-0------

8

0

_ _ _ _ _ __

11~~····----

3\4-~00-----

5-·-----1

6 -0

------

7\"8·····---0--------

Non-Interlaced
IRO= 1000; Total Lines/Row=9

Interlaced Sync
IRO=01111; Total Lines/Row= 17

MOTOROLA MICROPROCESSOR DATA
3~20.

Interlaced Sync and Video
IRO=0011; Total Lines/Row=9

MC2672

. VERTICAL BACK PORCH (lR3[4:0]) - This field determines the number of scan line periods between th~ falling
edges of the VSYNC and BLANK outputs.

EQUALIZING CONSTANT (lR1[6:0]) - This field indirectly defines the horizontal front porch and is used internally to
generate the equalizing pulses for the RS170 compatible
CSYNC. The value for this field is the total number of character clocks (CCLK) during a horizontal line period divided by
two, minus two times the number of character clocks in the
horizontal sync pulse:
EC

HACT+ HFP+ HSYNC+ HBP

i

CHARACTER BLINK RATE (lR4[7]) - Specifies the frequency for the character blink attribute timing. The blink rate
can be specified as 1/16 or 1/32 of the vertical field rate. The
timing signal has a duty cycle of 75% and is multiplexed onto
the DADD11/BLlNK output at the falling edge of each
BLANK .

2(HSYNC)

2

. The definition of the individual parameters is illustrated in
Figure 14. The minimum value of HFP is two character
clocks.
Note that when using the attributes controller the bla~k pulse
is delayed three CCLKs relative to the HSYNC pulse.

CHARACTER ROWS PER SCREEN (lR4[6,O]) - This field
defines the number of character rows to be displayed. This
value multiplied by the scan lines per character row, plus the
vertical front and back porch values, and the vertical sync
pulse width (three scan lines) is the vertical scan period in
scan lines.

HORIZONTAL SYNC PULSE WIDTH (lR2[6:3]) - This
field specifies the width of the HSYNCpulse in CCLK
periods.

ACTIVE CHARACTERS PER ROW (lR5[7:0]) - Thisfield
determines the number of characters to be displayed on each
row of the CRT SCreen. The sum of this value, the horizontal
front porch, the horizontal sync width, and the hor-izontal
back porch is the horizontal scan period is CCLKs.

HORIZONTAL BACK PORCH (iR2[2:0]) - This field
defines the number of CCLKs between the trailing edge of
HSYNC and the trailing edge of BLANK.

FIRST AND LAST SCAN LINE OF CURSOR (lR6[7:4]
AND IR6[3:0J) - These two fields specify the height and
position of the cursor on the character block. The "first" line
is the topmost line when scanning from the top to the bot-.
tom of the screen.

VERTICAL FRONT PORCH (lR3[7:511 - Programs the
number of scan line periods between the rising edges of
BLANK and VSYNC during a vertical retrace interval. The
width of the VSYNC pulse is fixed at three scan lines.

FIGURE 14 ~. HORIZONTAL AND VERTICAL TIMING

.i--___

I--

I~--~L

HBLANK ----J
~

HSYNC

Char/Row ------i·~I'
(lR5)

________________

f+ Front Porch (IR1)

.

!+'HSYNC (lR2)
'~Char

Rows/Screen (lR4)--+j
";..I - - -.....

,...-_ _ _-+1.., 1+ S
S,can Lines Per Row (lRO)

VSYNC

f.-

-.JlL........__________~I1L...___
--+l

VBLANK

- - - - IL------

~-I

Back Porch (lR2) ~

--.J

I
+! f<4:- Front Porch (lR3)

I

Back Porch (IR3)'+-\

nL.____

---fl
I - VSYNC (Fixed at3)

~

IRO

I. I I. I I I I I
HSYNC
Width

Equalizing
Constant
IRl

HBACK
Porch

I I I I I I II'

IR4

VBACK
Porch

~

IR3

II I I I I I I I
Characters Per Row

Char. Rows/ Screen
I

I I I I I 1'1 I I
VFRONT
Porch

~

IR2

L
i"

,

I I I II I I I I

IR5

I I I I I I I I

MOTOROLA MICROPROC.ESSOR DATA
3-21

I

MC2672

If "last address" is the end of a character' row and a new
screen start address has been loaded into the screen start
register, or if "last address" is the last character position of
the screen, the next data is obtained from the address contained in the screen start register ..
. Note that there is no restriction in displaying data· from
other areas of the addressable memory. Normally, the area
between these two bounds is used for data which can be
overwritten (e.g., as a result of scrolling), while data that is
not to be overwritten would be contained outside these
bounds and accessed by means of the split-screen interrupt
feature of the PVTC.

LIGHT PEN LINE POSITION . (IR7[7:6]) - This· field
defines which of four scan lines of the character row will be
used for the light pen strike - through attribute by the
MC2673 VAC. The timing signal is multiplexed onto the
DADD9/LPL output during the falling edge of BLANK.
CURSOR BLINK ENABLE (IR7[5]) - This bit controls
whether or not the cursor output pin will be blinked at the
selected rate (IRlO[7]). The blink'duty cycle for the cursor is

50%.

I

DOUBLE HEIGHT CHARACTER ROW ENABLE (IR7[4])
- If enabled, the number of each scan line will be repeated
twice in succession, causing the height of the character row
to double. This bit can be changed atany time but will only
become effective at the beginning of the character row following the time it is changed. This allows selected character
rows to be of double height. The split-screen interrupt can
be used to notify the CPU when the effectuate changes to
this bit. For each double height row which replaces a normal
row, one row count should be subtracted from the "character rows per screen" field (lH4) to maintain the same total
number of scan lines per field.

CURSOR BLINK RATE (IR10[7]) - The cursor blink rate
can be specified at 1/ 16 or 1/32 of the vertical scan frequency. Blink is effective only if blink is enabled by IR7[51.
SPLIT-SCREEN INTERRUPT (IR10[6:0]) - The splitscreen interrupt can be used to provide special screen effects
such as a row of double height characters or to change the
normal addressing sequence of the display memory. The
contents of this field is compared, in real time, to the current
character row number. Upon a match, the PVTC sets the
split-screen status bit, and issues an interrupt request if so
programmed. The status change/interrupt request is made
at the beginning of scan line zero of the split-screen character row.

UNDERLINE POSITION (lR7[3:0J)- This field defines which
scan line of the character row will be used for the underline
attributes by the attributes controller. The timing signal is multiplexed onto the DADD10/UL output during the falling edge
of BLANK.

TIMING CONSIDERATIONS
Normally, the contents of the initialization registers are not
changed during operation. However, this may be necessary
to implement special display features such as multiple cursors, smo'othscrolling, horizontal scrolling, and double
height character rows. Table 2 describes the timing details
for these registers which should be considered when implementing these features.

DISPLAY BUFFER FIRST ADDRESS (IR9[3:0] AND
IR8[7:0]) AND DISPLAY BUFFER LAST ADDRESS
(IR9[7:4]) - These two fields define the area within the buffer memory where the display data will reside. When the data
at the "display buffer last address" is displayed, the PVTC
will wrap-around and obtain the data to be displayed at the
next screen position from the "display buffer first address"

TABLE 2 - TIMING CONSIDERATIONS

Parameter
Field Line of Cursor
Last Line of Cursor
Light Pen Line
Underline
Double Height Characters
Cursor Blink
Cursor Blink Rate
Character Blink Rate
Split-Screen Interrupt Row
Character Rows Per Screen
Vertical Front Porch
Vertical Back Porch
Screen-Start Register

Timing Considerations
These parameters must be established at a minimum of two characters times
prior to their occurrence.

Setl reset during the character row prior to the row which is to bel not to be
double height.
New values become effective within one field after values are changed.

Change anytime prior to line zero of desired row.
Change only during vertical blanking period.
Change prior to first line of VFP.
Change prior to fourth line after VSYNC.
Change ,prior to the horizonta.1 blanking interv('ll of the last line of character
row before row where new value is ·to be used.

MOTOROLA MICROPROCESSOR· DATA
3-22

MC2672

ing registers in the group store address values which specify
the cursor and buffer pointer locations, the location of the
first character to be displayed on the screen, and the location
of a light pen "hit". With the exception of the light pen
register, the user initializes these registers after powering on
the system and changes their values to control the data
which is displayed.

DISPLAY CONTROL REGISTERS

There are nine registers in this group, each with an individual address. Their formats are illustrated in Figure 15.
The command register is used to invoke one of16 possible
PVTe commands as described in COMMANDS. The remain-

FIGURE 15 - DISPLAY CONTROL REGISTER FORMATS
(a) Command Register (Write Only)

6

o

4

Command Code.

Refer to COMMANDS for Command Codes

(b) Screen Start Registers (Read and Write),
Cursor Address Registers (Read and Write),
Pointer Address Register (Write Only), .and
Light Pen Address Register (Read Only)

6

5

o

3

4

Upper Register

MSBs

Not Used

6

5

4
3
Lower Register (LSBs)

2

o

H"OOOO"=O
H"OOOl" = 1

NOTE: MSBs are in Upper Register [5:0]
H"3FFE" = 16,382
H"3FFF" = 16,383

SCREEN-START REGISTERS

the programmed number of rows per screen. Thus, the data
in the display memory is displayed sequentially starting from
the address contained in the screen start register. After the
ensuing vertical retrace interval, the entire process repeats
again.
The sequential operation described above will be modified
upon the occurrence of either of two events. First, if during
the incrementing of the memory address counter the
"display buffer last address" (IR9[7:4]) is reached, the MAC
will be loaded from the "display buffer first address" register
(lR9[3:0)), (lR8[7:0]) at the next character clock. Sequential
operation will then resume starting form this address. This
wraparound operation allows portions of the display buffer
to be used for purposes other than storage of displayable
data and is completely automatic without any CPU intervention (see Figure 16a).

The screen-start registers contain the address of the first
character of the first row (upper left corner of the active
display). At the beginning of the first scan line of the first
row, this address is transferred to the row-start register
(RSR) and into the memory-address counter (MAC) ..· The
counter is then advanced sequentially at the character rate
the number of times programmed into the active charactersper-row register (iR5) thus reaching the address of the last
character of the row plusone. At the beginning of each subsequent scan line of the first row, the MAC is reloaded from
the RSR and the above sequence is repeated. At the end of
the last scan line of the first row, the contents of the MAC is
loaded into the RSR to serve as the starting memory address'
for the second character row. This process is repeated for

MOTOROLA MICROPROCESSOR DATA
3-23

I

MC2672

FIGURE 16 -

DISPLAY ADDRESSING OPERATION

or - - - - - - - - - ,

Bottom of Screen-.

mfmrmmrr?f~}} ..Display Buffer Start

Monitor
Display

16K '--_ _ _ _ _.J
Memory
(a) Display Memory Wraparound

I

0...---------.

~~~~~..O...:..~ +Display Buffer End

Monitor
Display

16K'-------...1
Memory
(b) Display Memory Split Screen With Wraparound

The sequential row-to-row addressing can also be
modified under CPU control. If the contents of the screenstart register (upper, lower, or both) are changed during any
character row (say row "n"), the starting address of the next
character row (row "n+ 1") will be the next value of the
screen-start register and addressing will continue sequentially from there. This allows features such as split-screen
operation, partial scroll, or status line display to be implemented. The split-screen interrupt feature of the PVTC is
useful in controlling this type of operation. Note that in order
to obtain the correct screen display, the screen-start register
must be reloaded with the original value prior to the end of
the vertical retrace. See Figure 16b.
During vertical blanking the address counter operation is
modified by stopping the automatic load of the contents of
the RSR into the counter, thereby allowing the address outputs to free-run, This allows.dynamic memory refresh to occur during the vertical retrace interval. The refresh addressing starts at the last address displayed on the screen and increments by one for each character clock during the retrace
interval. If the display buffer last address is encountered
refreshing continues from the display buffer first address.

CURSOR ADDRESS REGISTERS
The contents of these registers define the buffer memory
address of the cursor. If enabled, the cursor output will be
asserted when the memory address counter matches the
value of the cursor address registers. The cursor addr.ess
registers may be read or written by the CPU or incremented
via the "increment cursor address" command. In independent buffer mode, these registers define a buffer memory address for PVTC controlled access in response to "read/write
at cursor with/without increment" commands, or the first
address to be used in executing the "write for cursor to
pointer" command.
DISPLAY POINTER ADDRESS REGISTERS
These registers define a buffer memory address for PVTC
controlled accesses in response to "read/write at pointer"
commands .. They also define the last buffer memory address
to be written for the "write from cursor to pointer" command.
LIGHT PEN ADDRESS REGISTERS

If the light pen input is enabled, these registers are used to

MOTOROLA MICROPROCESSOR DATA
3-24

MC2672

VBLANK (I/SR[4]) - Indicates the beginning of a vertical
blanking interval, is set to a one at the beginning of the first
scan line of the vertical front porch.

store the current character address upon receipt of a light
pen strope input. Several sources of delay between the
display of a character upon the screen and the receipt of a
light pen hit can be expected to exist in a system environment. These delays include address pipelining in the character generation circuits, delays in the video generation circuits, and delays in the light detection circuitry itself. These
delays cause the value stored in the light pen register to differ from the actual address of the character at which the light
pen hit actually was detected. Software must be used to correct this condition.

LINE ZERO (I/SR[3]) - Is set to a one at the beginning of
the first scan line (line zero) of each active character row.
SPLIT SCREEN (I/SR[2]) - This bit is set when a match
occurs between the current character row number and the
value contained in the split-screen interrupt register,
IR10[6:01. The equality condition is only checked at the
beginning of line zero of each character row. This bit is reset
when either of the screen-start registers is loaded by the
CPU.

INTERRUPT/STATUS REGISTERS
The interrupt and status registers provide information to
the CPU to allow it to interface with the PYTC to effect
desired changes to implement various display operations.
The interrupt register provides information on five possible
interrupting conditions, as shown in Figure 17. These conditions may be selectively enabled or disabled (masked) from
causing interrupts by certain PYTC commands. An interrupt
condition which is enabled (mask bit equal to one) will cause
the INTR output to be asserted and will cause the corresponding bit in the interrupt register to be set upon occurrence of interrupt condition. An interrupt condition which is
disabled (mask bit equal to zero) has no effect on either the
fl\fi"R output or the interrupt register.
The status register provides six bits of status information;
the five possible interrupting conditions plus the NOT BUSY
bit. For this register, however, the contents are not effected
by the state of the mask bits.
Descriptions of each interrupt/status register bit follows.
Unless otherwise indicated, a bit, once set, will remain set
until reset by the CPU by issuing a "reset interrupt/status
bits" command. The bits are also reset by a "master reset"
command and upon power-up.
RDFLG (SR[5])·- This bit is present in the status register
only. A zero indicates that the PYTC is currently executing
the previously issued command. A one indicates that the
PYTC is ready to accept a new command.
FIGIjRE 17 -

6

READY (I/SR[lJ) - Certain PYTC commands affect the
display and may require the PYTC to wait for a blanking
interval before enacting the command. This bit is set to one
when execution of the command has been completed. No
command should be invoked until the prior command is
completed.
LIGHT PEN (lfSR[O]) - A one indicates that a light pen
hit has occurred and that the contents of the light pen
register have been updated. This bit will be reset when either
of the light pen registers is read.

COMMANDS
The PYTC commands are divided into two classes: the instantaneous commands, which are executed immediately
after they are invoked, and the delayed commands which
may need to wait for a blanking interval prior to their execution. Command formats are shown in Table 3. The commands are asserted by performing a write operation to the
command register with the appropriate bit pattern as the
data byte.

INTERRUPT AND STATUS REGISTER FORMAT

5

3

4
..

Not Used
Always Read
as Zero

RDFLG

VBLANK

0= Busy
1 :2'Ready

O=No
1 =Yes

Line
Zero
O=Nb
1 =Yes

Split
Screen

Ready

Light
Pen

O=No
1 =Yes

0= Busy
1 = Ready

O=No
1 =Yes

MOTOROLA MICROPROCESSOR DATA
3-25

I

MC2672

TABLE 3- PVTC COMMAND FORMATS

I

07

06

05

D4

03

02

01

DO

0
0
0
0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
0
1
0
1

0
0
1
1
1
1
1
1
0
0
1

0
1

d
d
d
d
1
1
N
N
N

0
V
d
d
1
1
d
d
N
N
N

0
V
d
d
N
N
d
d
N
N
N

0
V
1
1
d
d
d
d
N
N
N

0
V
0*
1*
0*
1*
0*
1*
N
N
N

V
B

L

Z

S
S

R
D

L
P

0
0
0
0
0
0
0
1

0
0
1
1
1
1
1
1

1
0
0
1
0
1
0
0

0
1

0
0
1
0
0
1
1
1

1
1
1
1
1
1
1
1

0

0
0
0

0
0

0
0

1
1
1
1
1
1
1
1

0
0
1
0
1
1

Hex
Command
Instantaneous Commands
Master Reset
Load IR Pointer with Value V (V = 0 to 10)
Disable Light Pen
Enable Light Pen
Display Off - Float DADD Bus If N = 1
Display On - Next Field (N= 1) or Scan Line (N=Q)
Cursor Off
Cursor On
Reset Interrupt/ Status - Bit Reset where N = 1
Disable Interrupt - Disable where N = 1
Enable Interrupt - Enables Interrupts and Resets the Corresponding
Interrupti Status Bits where N = 1

Oelayed Commands
Reset at Pointer Address
A2 Write at Pointer Address
A9 Increment Cursor Address
AC Read at Cursor Address
AA Write at Cursor Address
AD Read at Cursor Address and Increment Address
AB Write at Cursor Address and Increment Address
BB Write from Cursor Address to Pointer Address
A4

* Any combination of these three commands is valid.
d= Don't Care

INSTANTANEOUS COMMANDS
The instantaneous commands are executed immediately
after the trailing edge of the write pulse during which the
command is issued. These commands do not affect the state
of the RDFLG or READY interrupt/status. bits. However, a
command should not be invoked if the RDFLG bit is low.

ENABLE LIGHT PEN
After invoking this command, receipt of a light pen strobe
input will cause the light pen register to be loaded with the
current buffer memory address and the corresponding interrupt and status flag to be set. Once loaded, further loads are
inhibited until either one of the light pen registers are read or
a reset function is performed.

MASTER RESET
This command initializes the PVTC and may be invoked at
any time to return the PVTC to its initial state. Upon powerup, two successive master reset commands must be applied
to release the PVTC's internal power on circuits. In transparent and shared buffer modes, the CNTRL1 input must be
high when the command is issued. The command causes the
following:
1. VSYNC and HSYNC are driven low for the duration of
reset and BLANK goes high. BLANK remains high until
a "display on" command is received.

DISABLE LIGHT PEN
Light pen hits will not be recognized.
DISPLAY OFF
Asserts the BLANK output. The DADDO through DADD13
display address bus outputs may be optionally placed in the
high-impedance state by setting bit 2 to a one when invoking
the command.
DISPLAY ON
Restores normal blanking operation either at the beginning
of the next field (bit 2= 1) or at the beginning of the next
scan line (bit 2=0). Also returns the DADDO-DADD13
drivers to their active state.

2. The interrupt and status bits and masks are set to zero,
except for the RDFLG flag which is set to a one.
3. The transparent mode, cursor off, display off, and light
pen disable states are set.
4. The initialization register pointer is set to address IRO.

CURSOR OFF
Disables cursor operation. Cursor output is placed in the
low state.

LOAD IR ADDRESS
This command is used to preset the initialization register
pointer with the value "V" defined by D3-DO. Allowable
values are 0 to 10.

CURSOR ON
Enables normal cursor operation.

MOTOROLA MICROPROCESSOR DATA
3-26

MC2672

RESET INTERRUPT/STATUS BITS
This command resets the designated bits in the interrupt
and status registers. The bit positions correspond to the bit
positions in the registers:

Bit 0
Bit 1
Bit 2
Bit 3
Bit 4

-

ENABLE INTERRUPTS
Resets the selected interrupt and status register bits and
writes the associated interrupt mask bits to a one. This
enables the corresponding conditions to assert the INTR output. Bit position correspondence is as above.
DELAYED.COMMANDS
This group of commands is utilized for the independent
buffer mode of operation, although the "increment cursor"
command can also be used in other modes. With the exception of the "write from cursor to pointer" and "increment
cursor" commands, all the commands of this type will be
executed immediately or will be delayed depending on when
the command is invoked. If invoked during the active screen
time, the command is executed at the next horizontal blanking blanking interval. If invoked during a vertical retrace interval or a "display off" state, the command. is executed immediately.

Light Pen
Ready
Split Screen
Line Zero
Vertical Blank

DISABLE INTERRUPTS
Sets the interrupt mask to zeros for the designated conditions, thus disabling these conditions from asserting the
il\ffR output. Bit position correspondence is as above.

I

MECHANICAL DATA

ORDERING INFORMATION (TA=O°C to 70°C)

Package Type

Plastic
P Suffix

Frequency

Order Number

2.7 MHz
4.0 MHz

MC2672B3P
MC2672B4P

PIN ASSIGNMENTS

R
CE
W.

VCC
A2
A1

CTRLl
LPS

CTRL2
CTRL3
CURSOR

DADDO

DO

DADD1

01

DADD2

02

DADD3/L1

03

DADD4/LAO

04

DADD5/LAl

05

DADD6/LA2

06

DADD7/LA3

07

DADD8/LNZ

CCLK

DADD9/LPL

BLANK
VSYNCI
CSYNC
HSYNC

DADD10/UL
DADDll
IBLINK
DADD121
ODD
DADD13/LL

GND

MOTOROLA MICROPROCESSOR DATA
3-27

MOTOROLA
~SEMICONDUCTOR~~~~~~~~~~~~~
TECHNICAL DATA

MC2674

Advance Information

Advanced Video Display Controller (AVDC)
The MC2674 advanced video display controller (AVDC) is a programmable device designed for
use in CRT terminals and display systems that employ raster-scan techniques. The AVDC generates
the vertical and horizontal timing signals necessary for the display of interlaced or non-interlaced
data on a CRT monitor. It provides consecutive addressing to a user specified display buffer memory domain and controls the CPU-display buffer interface for various buffer configuration modes. A
variety of operating modes, display formats, and timing profiles can be implemented by programming the control registers in the AVDC.

3

A minimum CRT terminal system configuration consists of an AVDC, a keyboard controller, an
asynchronous communications interface adapter, character ROM, and an attributes controller. Other
necessary parts of the system are a single-chip microcomputer such as the MC6809, display buffer
RAM, and a small amount of TIL for miscellaneous address decoding, interface, and control. System complexity can be enhanced by upgrading the microprocessor and expanding via the system
address and data buses.
•
•
•
•
•
•
•
•
•

4 MHz Character Rate
1 to 256 Characters Per Row
1 to 16 Raster Lines Per Character Row
Bit Mapped Graphics Mode
Programmable Horizontal and Vertical Sync Generators
Interlaced or Non-Interlaced Operation
Up to 64K RAM Address for Multiple-Page Operation
Readable, Writeable, and Incrementable Cursor
Programmable Cursor Size and Blink

•
•
•
•
•
•
•
•
•
•
•
•
•
•

AC Line Lock
Automatic Wraparound of RAM
Automatic Split Screen
Automatic Bidirectional Soft Scrolling
Programmable Scan Line Increment
Row Table Addressing Mode
Double Height Tops and Bottoms
Double Width Control Output
Selectable Buffer Interface Modes
Dynamic RAM Refresh
Completely TTL Compatible
Single +5-Volt Power Supply
Power-On Reset Circuit
Applications Include: CRT Terminals, Word Processing Systems, Small Business Computers,
and Home Computers

This document contains information on a new prod~ct. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-28

MC2674

BLOCK DIAGRAM

Interface

Read/
Write
Control
Logic

Control
Display
Memory
Handshake
Logic

Initialization,
Pointer
and
Display
Registers

CTRL1
CTRL2
CTRL3

Command
Decode
Logic
Address
Decoder

Interrupt
Logic
Status
Register

I

DO-D7
Data
Bus
Drivers
Compare
Logic

ACLL
Timing Chain
and
Decode Logic

Clock
Buffer

Timing

MOTOROLA MICROPROCESSOR DATA
3-29

HSYNC
VSYNC/ CSYNC
BLANK

MC2674

ABSOLUTE MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature Range

Symbol
VCC
Yin
TA
Tstg

Value
-0.3 to + 7.0
-0.3 to + 7.0
o to 70
-55 to + 150

Unit
V
V
°c
°c

THERMAL CHARACTERISTICS
Characteristic

Symbol

Thermal Resistance
Plastic Package

Value

Rating

This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields;
however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximumrated voltages to this high-impedance
circuit. For proper operation .it is recommended that Yin and Vout be constrained to the range GND~(Vin or
Vout)~Vce. Reliabil:ity of operation is
enhanced if unused' inputs are tied to
an appropriate logic voltage level (e.g.,
either GND or Vce).

°CIW

!!JA
50

POWER CONSIDERATIONS

I

The average chip-junction temperature, TJ' in °c can be obtained from:
(1 )

TJ =TA +(PO· IlJA)
where:
TA
IlJA
Po
PINT
PPORT

= Ambient Temperature, °c
= Package Thermal Resistance, Junction-to-Ambient, °CIW
= PINT+ PPORT
= ICC x VCC' Watts - Chip Internal Power
= Port Power Oissipation, Watts - User Oetermined

For most applications PPORT
s:
Co)

t

n
~

o"tI
o(")

WDB

3:

o

BCE

~

RDB

.,

e»-

--'-~

:ii;!

m

en

~
~

BLANK

e

.

f

~

c

HSYNC

~

\

HFP=Even

I

-------

,___________________________

DADD

BLANK

HSYNC

~

.

\_--

DADD
NOTE:
If command execution occurs just prior to the first scan line of a character row and row table addressing mode is enabled, execution of the
command is delayed by two character clocks from the timing illustrated.

MC2674

FIGURE 6 - AVDC SHARED OR TRANSPARENT BUFFER MODES

Refresh
RAM

MC2674
AVDC

ADR
PBREO
CPU

{

-----~

CTRll

.------l~IT

W

BACK ...- -.....----/ CTRl3

Data I/O
BEXT

.---+-----1

CTRl2

Select
Decode

II

FIGURE 7 - TRANSPARENT BUFFER MODE TIMING

r----·-·--~---

--.....I\r"~---1----1----"""'_-..j- - - -

I

(2)

--_._--

;..I

,--- - - -"r----

I

-----'
BLANK

I r - - - - - - -........Ir----------.~ -

- - - -~ - -,

----Ii"f"

\t..

_____ _

DADD
NOTES:
1. PBREQ must be asserted prior to the rising edge of BLANK in order for sequence to begin during that blanking periOd.
2. IfPBREQ is negated after the next to last CClK of the horizontal blanking interval, the next scan line will also be blanked.
3. Accesses during vertical blank or "display off" are granted only at the beginning of the horizontal front porch.
4. If row table addressing is enabled, CPU access is delayed by two character clocks prior to the first scan line of each character
row.
5. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and
outputs. Input levels are 0.4 V to 2.4 V.

MOTOROLA MICROPROCESSOR DATA
3-43

MC2674

FIGURE 8 -

SHARED BUFFER MODE TIMING

'---+---+---+-..1\,....--1_- - - -

,.------- ~---- -------

, (1)
~

1_-----"'------""'111.. - - - - ~ - --,

BLANK

... _------

\

DADO

I

NOTES:
1. If PBREQ is negated after the next to last CClK of the horizontal blanking interval, the next scan line will also be blanked.
2. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and
outputs. Input levels are 0.4 V to 2.4 V.
FIGURE 9 - SHARED AND TRANSPARENT MODE TIMING

(bl

(a)

------- ~-------BACK

_ _ _ _ _J

BEXT

----------~\L-_____~~--~~

VBlANK or
DBlANK
DADD

BACK

,,

BLANK

Sys. ADD

~
Refresh Addresses

----------------~~r-----------------

BEXT _ _ _ _ _ _ _ _

,•

~~~

_ _ _ _ _ _ _ __

System Processor Has Continuous Bus Control

....:.t~~~-----J>--

DADO -(_ _ _ _

Refresh
Addresses

bl After 'display off and 3-state' command.

a) During Vertical Blank or after 'display off' command in shared
mode only. See Figure 7 for transparent timing.

OPERATION

the other modes, but circuitry must be added to route the
data from the display memory to the data bus inputs of the
AVDC. Additionally, when not operating in row buffer
mode, care must be taken to assure that the CPU does not
attempt to access the AVDC while it is reading the row table.
One way of preventing this is to latch prior to reading or
writing the AVDC. The AVDC should only be accessed if the
latch is low, indicating that the last line of the row is not
active.
Figure 13 illustrates a typical hardware implementation for
use in conjunction with independent and transparent modes,
and Figure 14 shows the timing for row table operation.

After power is applied, the AVDC will be in an inactive
state. Two consecutive "master reset" commands are
necessary to release this circuitry and ready the AVDC for
operation. Two register groups exist within the ADC; the
initialization registers and the display control registers. The
initialization registers select the system configuration,
monitor timing, cursor shape, display memory domain,
pointer address, scrolling region, double height and width
condition, and screen format. These are loaded first and normally require no modification except for certain special visual

MOTOROLA MICROPROCESSOR DATA
3-44

MC2674

FIGURE 10 -

ROW BUFFER MODE CONFIGURATION

2x2111
LSBs

MC2674
AVDC

Row
Refresh
RAM
OD

BREG
to CPU

CTRL2

W

CTRL3

System
RAM

R

W------J
System Data Bus

FIGURE 11 -

ROW BUFFER MODE TIMING

NOTES:

1. If row table addressing is enabled, BREQ will be asserted at the middle of the last scan line of the prior row, and MBC will
be asserted at the beginning of BLANK.
2. All voltage measurements are referenced to ground. All time measurements are at the 0.8 V to 2.0 V level for inputs and
outputs. Input levels are 0.4 V to 2.4 V.

MOTOROLA MICROPROCESSOR DATA
3-45

II

MC2674

FIGURE 12 -

ROW TABLE ADDRESS FORMAT

r

~-

B
Row Table {
in Memory

A
C .}_ I D

.

.-

1st Char
2nd Char

f+-

~

Third
{
Data Row

SSR2

0
0
0
last Char

1st Char
2nd Char

II

First
{
Data Row

I+--

0
0
0
last Char

1st Char
2nd Char
Second {
Data Row

0
0
0
last Char

FIGURE 13 -

ROW TABLE MODE CONFIGURATION (NON-ROW BUFFER MODES)

CClK - - - - . . . ,
RAM
MC2674
AVDC

DADO

ADD

Display Address

Data 1/0

CClK 1-.....-+1
BLANK 1+--+1

,...---+1 R

W

IT

CURSOR I------~~-~

00-07

N t + - - - -....
8
. Display Data Bus
Select
Decode

IT

.....~+-+-l..
W

MOTOROLA MICROPROCESSOR DATA
3~46

MC2674

FIGURE 14 -

ROW TABLE MODE TIMING

BLANK

First line of Row

HSYNC
. .- - - - - - - - '....... EC+2 HSW CCLKs

Row Buffer
Mode

MBC

DADD

CURSOR

Last Line Addresses

First line Addresses

Refresh

,..-------

I

Possible Cursors

Possible Cursors

DADD

First Line Addresses

Transparent
Buffer Mode

No Fetch Bus

DADD

Independent
Buffer Mode

3-State

First Line Addresses

U

WDB

BCE

u

~_________________________________

= Multiplexed Control Signals
EC = Equalizing Constant
HSW= Horizontal SYNC Width

MOTOROLA MICROPROCESSQR'DATA
3-47

II

MC2674

I

ditions generated by the AVDC supply the "handshaking"
information necessary for the CPU to effect real time
display changes in the proper time frame if required.

effects. The display control registers specify the memory address of the base character (upper left corner of
screen), the cursor position, and the split screen addresses associated with the scrolling area or an alternate memory. These may require modification during
operation.
After initial loading of the two register groups, the
AVDC is ready to control the monitor screen. Prior to
executing the AVDC commands which turn on the display cursor, the user should load the display memory
with the first data to be displayed. During operation,
the AVDC will sequentially address the display memory
within the limits programmed into its registers. The
memory outputs character codes to the system character and graphics generation logic, where they are converted to the serial video stream necessary to display
the data on the CRT. The user effects changes to the
CRT. The user effects changes to the display by modifying the contents of the display memory, the AVDC
display control and command registers, and the initialization registers, if required. Interrupts and status con-

FIGURE 15 -

Double
Height!
Width

There are 15 initialization registers (IRO-IR14) which
are accessed sequentially via a single address. The AVDC
maintains an internal pointer to these registers which
is incremented after each write at this address until the
last register (lR14) is accessed. The pointer then continues to point to IR14 for further accesses. Upon a poweron or a master reset command, the internal pointer reset
to point to the first register (lRO) of the initialization
register group. The internal pointer can also be preset
to any register of the group via the "load IR address
pointer" command. These registers are write only and
are used to specify parameters such as the system configuration, display format, cursor shape, and monitor
timing. Register formats are shown in Figure 15.

INITIALIZATION REGISTER FORMATS (Sheet 1 of 4)

6
IRO

INITIALIZATION REGISTERS

o

4

Scan lines Per Character Row
Non-Interlaced
Interlaced
0000= 1 line
0001 =2 Lines
0010= 3 lines

0000=2 lines
0001 =4 lines
0010=6 Lines

1110= 15 lines
1111 = 16 lines

1110=30 lines
1111 = Undefined

..

..

Sync
Select
O=VSYNC
1 = CSYNC

Buffer-Mode
Select
00 = Independent
01 = Transparent
10=Shared
11 =Row
Buffer

o

4

IRl

Interlace
Enable

.

0= NonInterlace
1 = Interlace·

Equalizing Constant
0000000= 1 CClK
0000001 = 2 CClK

..

Calculated from:
EC =0.5 IHACT+ HFP+ HSYNC + HBP) - 2IHSYNC)

1111110=127 CClK
1111111 = 128 CCIR

o

4
IR2

Row
Table
O=Off
1 =On

Horizontal Sync Width

Horizontal Back Porch

0000= 2 CClK
0001 =4 CClK

000= Not Allowed
001 =3 CClK

1110=30 CClK
1111 = 32 CClK

110=23 CClK
111 =27 CClK

..

MOTOROLA IVIICROPROCESSOR DATA
3~48

..

MC2674

FIGURE 15 -

5

6
IR3

INITIALIZATION REGISTER FORMATS (Sheet 2 of 4)

4

Vertical Front Porch

2
Vertical Back Porch

000=4 Scan Lines
001 = 8 Scan Lines

00000=4 Scan Lines
00001 = 6 Scan Lines

110=28 Scan Lines
111 = 32 Scan Lines

11110=64 Scan Lines
11111 = 66 Scan Lines

..

..

7
IR4

5

6

o

Character
Blink Rate

4

3

o

2

Active Character Rows Per Screen

00000oo = 1 Row
0000001 = 2 Rows

0= 1/64
VSYNC
1 = 11128
VSYNC

···

1111110=127 Rows
1111111=128 Rows

7

5

6

o

4
Active Characters Per Row

IR5

00000010 = 3 Characters
00000011 =4 Characters

11111110= 255 Characters
11111111 = 256 Characters

7
IR6

5

6

4

Last Line of Cursor

0000= Scan Line 0
0001 = Scan Line 1

0000= Scan Line 0
0001 = Scan Line 1

1110=Scan Line 14
1111=Scan Line 15

1110= Scan Line 14
1111 = Scan Line 15

..

7

6

IR7
Light Pen Line
00= Scan
01 = Scan
10= Scan
11 = Scan

o

3

First Line of Cursor

Line
Line
Line
Line

3
1
5
7

··

5

4

Cursor
Blink

Cursor
Rate

Underline Position'

O=Off
l=On

0= 1/32
1 = 1/64

0000 = Scan Line 0
0001 = Scan Line 1

3

··

1110= Scan Line 14
1111=Scan Line 15

MOTOROLA MICROPROCESSOR DATA
3-49

~

II

MC2674

FIGURE 15 - INITIAL:lZATION REGISTER FORMATS (Sheet 3 of 4)

6

4

IR8

o

2

Display Buffer First Address LSBs '
H'ooo'=O
H'OOl'=l
NOTE: MSBs are in IR9[3:0]
H'FFE'=4,094
H'FFF' =4,095

6
IR9

3

4

Display Buffer Last Address

o

2
Display Buffer First Address MSBs

0000=1,023
0001 = 2,047

..

I

See IR8

1110= 15,359
1111=16,383

7

6

4

IRlO

3

2

o

Display Pointer Address Lower

See IR11

6
IR11

LZ Down
O=Off .
l=On

o

4

LZ Up
0= Off
l=On

Display Pointer Address Upper
H'OOOO' -0
H'oool'= 1

..

H'3FFF' =16,383

6
IR12

5

4

3

2

Split Register 1

Scroll Start
O=Off
l=On

00000oo = Row 1

..

0000001 = Row 2

1111111 = Row 128

MOTOROLA MICROPROCESSOR DATA
3-50

o

MC2674

FIGURE 15 - INITIALIZATION REGISTER FORMATS (Sheet 4 of 4)
6
IR13

5

4

Scroll End
0= Off
l=On

3
Split Register 2
00000oo = Row 1
0000001 = Row 2

o

2

..

1111111 = Row 128

7
IR14

6

Double 1
00= Normal
01 = Double Width
10= Double Width
and Tops
. 11 = Double Width
and Bottoms

5

4

Double 2
00= Normal
01 = Double Width
10= Double Width
and Tops
11 = Double Width
and Bottoms

DOUBLE HEIGHT/WIDTH ENABLE (lRO[7]) - When this
bit is set, the. value in IR14[7:6] is used to control the double
height and width conditions of each character row. Assertion of this bit also allows IR14[7:6] to be programmed in two
ways:

o

3
lines to Scroll
0000= 1
0001 =2

..

1110= 15
1111 = 16

ODD, LO-L2 are used as the line address for the character
generator. The resulting displays are shown in Figure 16.
For "interlaced sync" operation, the same information is
displayed in both odd and even fields, resulting in enhanced
readability. The AVDC outputs successive line numbers in
ascending order on the LAO-LA3 lines, one per scan line for
each field.
The "interlaced sync and video" format doubles the character density on the screen. The AVDC outputs successive
line numbers in ascending order on the odd and LAO- LA2
lines, one per scan line for each field.

1. By theCP writing to IR14 directly.
2. When the contents of screen start register 1 (SSR1)
upper are changed, either by the CPU writing to this
register or by the automatic loading of SSRl when
operating in row table mode, the two most significant
bits of SSRl upper are copied into IR14[7:61. Thus, the
most significant bits of each row table entry can be used to control double height and double width attributes
on a row-by-row basis.

EQUALIZING CONSTANT (I R1[6:0]) - This field indirectly defines the horizontal front porch and is used internally to
generate the equalizing pulses for the RS170 compatible
CSYNC. The value for this field is the total number of
character clocks (CCLKs) during a horizontal line period
divided by two, minus two times the number of character
clocks in the horizontal sync pulse:

IR14[5:4] are not active when this bit is set. When this bit
is reset, the double height and width attributes operate as
described in IR[141.
SCAN LINES PER CHARACTER ROW (lRO[6:3]) - Both
interlaced and non-interlaced scanning are supported by the
AVDC. For interlaced mode, two different formats can be
implemented, depending on the interconnection between
the AVDC and the character generator (see IRl [7]). This field
defines the number of scan lines used to compose a character row for each technique. As scanning occurs, the scan
line count is output on the LAO-LA3 and ODD pins.

The definition of the individual parameters is illustrated in Figure 17.
Note that when using the attributes controller it will delay
the blank pulse three CClKs relative to the HSYNC pulse.

VSYNC/CSYNC (lRO[2]) - This bit selects either vertical
sync pulses or composite sync pulses on the VSYNC/
CSYNC output (pin 18). The composite sync waveform cone
forms to EIA RS170 standards, with the vertical interval composed of six equalizing pulses, six vertical sync pulses, and
six more equalizing pulses.
BUFFER MODE SELECT (lRO[1 :0]) - Four buffer memory
modes may be selectively enabled to accommodate the
desired system configuration. See SYSTEM CONFIGURATIONS.
INTERLACE ENABLE (lR1[711 - Specifies. interlaced or
non-interlaced' timing operation. Two modes of interlaced
operation are available, depending on. whether LO-L3 or

ROW TABLE MODE ENABLE (lR2[7]) - Assertion/negation of this bit causes the AVDC to begin/terminate
operating in row table mode starting at the next character
row. See ROW TABLE ADDRESS MODE. By using the split
interrupt capability of the AVDC, this mode can be enabled
and disabled on a particular character row. This allows a
combination of row table and sequential addressing to be
utilized to provide maximum flexibility in generating the
display.
HORIZONTAL SYNC PULSE WIDTH (lR2[6:3]) - This
field specifies the width of the HSYNC pulse in CeLK
periods.

MOTOROLA MICROPROCESSOR DATA
3-51

I

.

MC2674

FIGURE 16 -

INTERLACED DISPLAY MODES

t---!....---{§O~~}l
Line Address
To Character Generator

Line Address
To Character Generator
"0

Line Address
To Character Generator

c

~ ~

7--------8--------

0--------

C
ill

"0
"0

t1JO

o ---------

1
c

~
0

cure
u--..

(/)
0)

(/)

ill
C

-e------3 -e-------

2
4

-e-e-e-----

-e-------e-------e-e-e-e-e--

:.:J

I

-e-e-e-e-e--

1

1 -0-0-0-0-0---e------2-0------3 -e------3-0-------

2

4

7

6

8

-e-e-e-e-e--

4

01_00000-

2-e------

~

~~
~ Vi
o ill

3-0------

4

~:.5

\

6
8

-e e e-----

5-0------

7-~0000----

9-------

o -1-00000
--------e
3-0
--ee.
5-0
6 -e

2

4

8

7-00000

9

1-0-0-0-0-0--

0

3-0-------

4-0-0-0----

-e
3-0
4 - e ••
5-0
6 -e

5-0-----------

8

-e----~--

7-0-0:-0-0-0--

8

Non-Interlaced
IRO= 1000; Total Lines/Row=9

8-------0--------e------2-0-------e-------e-e-e----e------6-0------e-e-e-e-e-8------------

o -----------

-e--~----

4

-e-e-e-e-e-7 -0-0-0-0-0--

-e-e-e-e-e--

-e--------e-e-e-----e-----------e------------e-e-e-e-e - -

-e-e-e-----

4-0-0-0----e------5-0------6 -e------6-0-----------

5

8

o ---------

-e-e-.e-e-e--

Interlaced SYNC
IRO= 1000; Total Lines/Row= 16

1-00000----

2

7-00000----

0

9
1-00000----

2

-e------

4

- e e e---------

3-0------

5-0-....,.---6-e------

Interlaced SYNC and Video
IRO=Ol00; Total Lines/Row= 10

CHARACTER ROWS PER SCREEN (lR4[6:0]) - This
field defines the number of character rows to be displayed. The value multiplied by the scan lines per characte row, plus the vertical front porch, the vertical back
porch values, and the vertical sync pulse width is the
vertical scan period in scan lines.

HORIZONTAL BACK PORCH (lR2[2:0]) - This field
defines the number of CClKs between the trailing edge
of HSYNC and the trailing edge of BLANK.
VERTICAL FRONT PORCH (lR3[7:3]) - This field specifies the number of scan line periods between the rising
edges of BLANK and VSYNC during the vertical retrace
interval. The vertical front porch is extended in increments of scan lines if the ACll input is low at the end
of the programmed value.

ACTIVE CHARACTERS PER ROW (lR5[7:0]) - This
field determines the number of characters to be displayed on each row of the CRT screen. The sum of this
value, the horizontal front porch, the horizontal sync
width, and thehorizontl back porch is the horizontal
scan period in CClKs.

VERTICAL BACK PORCH (lR3[4:0]) - This field determines the number of scan line periods between the
falling edges of the VSYNC and BLANK outputs.
CHARACTER BLINK RATE (lR4[7]) - Specifies the frequency for the character blink attribute timing. The blink
rate can be specified as 1/64 or 11128 ofthevertical field
rate. The timing signal has a duty cycle of 50% and is
multiplexed onto the DADD1/BLlNK output at the falling
edge of each BLANK.

FIRST AND lAST SCAN LINE OF CURSOR (lR6[7:4].
IR6[3:0]) - These two field specify the height and position of the cursor on the character block. The "first"
line is the topmost line when scanning from the top to
the bottom of the screen.

MOTOROLA .MICROPROCESSOR DATA
3-52

MC2674

FIGURE 17 - HORIZONTAL AND VERTICAL TIMING

_----i..I~ __________
(IR5)
HBLANK ---.J
.:.---'L-

•. -____ Character ROw _ _ _---l~~1

--.j

~ Front Porch (I R1)

Back Porch (I R2)

.

HSYNC _ _~rl

~

f+--HSYNC (lR2)

~Character

VSYNC ____

~ Front Porch (lR3)

..-------

~rl~____~--------------------~r1

~

~VSYNC(lR7)

Equalizing
Constant

Lines/Row
IRO

I

IIIIII
HSYNC
Width

HBACK
Porch
~

IR2

,

III IIIIII

IRll

,
IR31

III
VBACK
Porch
~

,

IIIIIIII

VSYNC
Width
~

IR71

I I II

Characters per Row

,

II

II

VFRONT
Porch

Character Rows/ Screen
IR41

I

Ii----........L
Back Porch (lR3)----Jooj
j.-

---.JI'"----il

--+/

r-

Rows/Screen (lR4)~

--+l I+- Scan Lines Per Row (IRQ)

VBLANK

-1

11..___

IR51

•
IIIIIII

VERTICAL SYNC PULSE WIDTH (lR7[7:6]) -,-- This field
specifies the width of the VSYNC pulse in scan line periods.

between these two bounds is used for data which can be
overwritten (e.g., as a result of scrolling), while data that is
not to be overwritten would be contained outside these
bounds and accessed by means of the automatic split screen
or split screen interrupt features of the AVDC.

CURSOR BLINK ENABLE (lR7[5]) - This bit controls
whether or not the cursor output pin will be blinked at the
selected rate (IR7[4]). The blink duty cycle for the cursor is
50%.

DISPLAY POINTER ADDRESS LOWER (iRl0[7:0l AND
DISPLAY POINTER ADDRESS UPPER (lRl1[5:0l1 - These
two fields define a buffer memory address for AVDC controlled accesses in response to "read/write at pointer" commands. They also define the last buffer memory address to
be written for the "write from cursor to pointer" command.

CURSOR BLINK RATE (lR7[4]) - The cursor blink rate
can be specified at 1/32 or 1/64 of the vertical scan frequency. Blink is effective only if blink is enabled by IR7[5].
UNDERLINE POSITION (IR7[3:0))- This field defines which
scan line of the character row will be used for the underline
attribute by the attributes controller. The timing signal is multiplexed onto the DADD10/UL output during the falling edge
of BLANK.
DISPLAY BUFFER FIRST ADDRESS (lR9[3:0]), IR8[7:0]
AND DISPLAY BUFFER LAST ADDRESS (lR9[7:4]) These two fields define the area within the buffer memory
where the display data will reside. When the data at the
"display buffer last address" is displayed, the AVDC will
wraparound and obtain the data to be displayed at the next
screen position from the "display buffer first address". If
"last address" is the end of a character row and a new
screen start address has been loaded into the screen start
register, or if "last address" is the last character position of
the screen, the next data is obtained from the address contained in the screen start register.
Note that there is no restriction in displaying data from
other areas of the addressable memory. Normally, the area

SCAN LINE ZERO DURING SCROLL DOWN (lRZ11[7]) This field specifies normal scan line count or allscan line zero
counts for the new character row that occurs at the top of
the scrolling area during soft scroll down operation. If the
character generator provides blanks during scan line zero,
this will cause the new row to be automatically blanked on
the display. This feature can be used, if necessary, to blank
the new row until the CPU places "blank data" into the
display buffer.
SCAN LINE ZERO DURING SCROLL UP (lRl1[6]) - This
field specifies normal scan line count or all scan line counts
for the new character row that occurs at the bottom of the
scrolling area during soft scroll up dperation.
SCROLL START (lR12[7]) - This bit is asserted when
soft scroll is to take place. The scrolling area begins at the
row specified in split register 1 (lR12[6:0]l. If set, the first

MOTOROLA MICROPROCESSOR DATA
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II

MC2674

II

4. The specified double width and height conditions (IR14)
are also asserted in two possible ways:
a) Automatic split will assert the programmed condition
for the current row.
b) During soft scroll. operation the programmed conditions are asserted for the partial row scrolling onto or
off the screen:

row to scroll scan line count will be reduced by the value in.
the lines to scroll register (IR14[3:0)). The scan line count of
this row will start at the programmed offset value. When this
bit is asserted, scroll end IR13[7] must be set before split
register 2.
SPLIT REGISTER 1 ((R12[6:0H - Split register 1 can be
used to provide special screen effects such as soft (scan line
by scan line) scrolling, double height/width rows, or to
change the normal addressing sequence of the display
memory. The contents of this field is compared, in real time,
to the current row number. Upon a match, the AVDC sets
the split screen 1 status bit, and issues an interrupt request if
so programmed. The status change/interrupt request is
made at the beginning of the scan line zero of the split screen
character row. If enabled by theSPL 1 bit of screen start
register 2, an automatic split screen to the address specified
in screen start register 2 will be made' for the designated
character row. During a scroll operation, this field defines
the first character row of the scrolling area.
SCRbLL END ((R13[7]) - This field spec.ifies that the row
programmed in split register 2 (IR13[6:0J) is to be the last
scrolling row of the scrolling area. Note that this bit must be
asserted for a valid row only when the scroll start bit IR12[7]
is also asserted.
SPLIT REGISTER 2 ((R13[6:0]) - This field is similar to
the split register 1 field except for the following:
1. Split screen 2 status bit is set.
2. During a scroll operation, this field defines the 'Iast
character row of the scrolling area. This row will be
followed by a partial row. The LTSR (lR14) value
replaces the normal scan lines/ row value for the partial
row, thus keeping the total scan lines/screen the same.
3. If enabled by the SPL2 bit of screen start register 2, an
automatic split to' the address contained in screen start
register 2 will occur in one of two ways:
a) If not scrolling an automatic split will occur for the
next character TOW.
b) If scrolling, the automatic split will occur after the
partial row being scrolled onto' or off the screen.

TABLE 2 -

DOUBLE 1 ((R14[7:6]) ~ This field specifies the conditions (double width/heightor normal) of the row designated
in split register 1 (I R12[6:0)). When double height tops or
bottoms has been specified, the AVDC will automatically
toggle between tops and bottoms until another split 1 or 2
occurs which changes. thedouble height/width condition. If
a double height top row is specified, the scan line count will
start at zero and increment the scan line every other scan
line. If a double height bottom row is specified, the A VDC
will start a one half the normal scan line total. If double width
is specified, the A VDC will assert the DADD9/ OW output at
the falling edge of blank. This condition will also remain active until the next split 1 or 2. When IRO{7] = 1, the values
written into bits 7 and 6 of screen start 1 upper will also be
written into IR14[7:6] and the automatic toggling between
tops and bottoms is disabled.
DOUBLE 2 ((R14[5:4]) - This field specifies the conditions (double width/height or normal) of the row designated
in split register 2 (IR13[6:0]). Not used with IRO[7] = 1.
LINES TO SCROLL ((R14[3:0]) - This field defines the
scan line increment to be used during a soft scroll operation.
This value will only be used when scroll start (IR12[7)) and
scroll end (IR13[7]) are enabled.
TIMING CONSIDERATIONS
Normally, the contents of the initialization registers are not
changed during normal operation. However, this may be
necessary to implement special display features such as
multiple cursors and horizontal scrolling. T.able 2 describes
timing details for these registers which should be considered
when implementing these features.

TIMING CONSIDERATIONS

Parameter

Timing Considerations

First Line of Cursor
Last Line of Cursor
Underline Line

These parameters must be established at a minimum of two character times prior to their
occurrence.

Double Height Character Rows
Double Width Character Rows
Rows to Scroll

Set/ reset prior to the row specified in split 1 or 2 registers.

Cursor Blink
Cursor Blink Rate
Character Blink Rate

New valueS become effective within one field after values are Changed.

Split Register 1 .
Split Register 2

Change anytime prior to line zero of desired row.

Character Rows Per Screen

Change only during vertical blanking period.

Vertical Front Porch

Change prior to first line of VFP.

Vertical Back Porch .

Change prior to four line after VSYNC.

Screen Start Register 1
Row Table Mode Enable

Change prior .to the horizontal blanking interval of the last line of character row before row where
new value is to be used.

MOTOROLA MICROPROCESSOR DATA
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MC2674

ing starts at the last address displayed on the screen and increments by one for each character clock during the retrace
interval. If the display buffer last address is encountered,
refreshing continues from the display buffer first address.
The sequential operation described above will be modified
upon the occurrence of any of three events. First, if during
the incrementing of the memory address counter the
"display buffer last address" (lR9[7:4])is reached, the MAC
will be loaded from the "display buffer first address" register
. (lR9[3:0] and IR8[7:0]) at the next character clock. Sequential operation will then, resume starting from this address.
This wraparound operation allows portions of the display
buffer to be used for purposes other than storage of displayable data and is completely automatic without any CPU
intervention (see Figure 19a).
The sequential row to row addreSSing can also be modified
via split register 1 (lR12) and split register 2 (IR13), under
CPU control, or by enabling the row table addressing mode.
If bit 6 of screen start register 2 upper (S PL1) is set, the
screen start register 2 contents will be loaded automatically
into the RSR at the beginning of th8 first scan line of the row
designated by split register 1 (IR12[6:0]). If bit 7 of screen
start 2 upper (SPL2) is set, the screen start register 2 contents is automatically loaded into the RSR at the end of the
last scan line of the row designated by split register 2
(IR13[6:0]l. SPLl and SPL2 are write only bits and will read
as zero when reading screen start re.gister 2.
If the contents of screen start register 1 (upper, lower, or
both) are changed during any character row (e.g., row'n'),
the starting address of the next character row (row 'n+ 1')
will be the new value of the screen start register and addressing will continue sequentially from there. This allows features such as split screen operation, partial scroll, or status
line display to be implemented. The split screen interrupt feature of the AVDC is useful in controlling the CPU initiated
operations. Note that in order to obtain the correct screen
display, screen start register 1 must be reloaded with the
original (origin of display) value prior to the end of the vertical retrace. See Figure 19b.

DISPLAY CONTROL REGISTERS
There are seven registers in this group, each with an individual address. Their formats are illustrated in Figure 18.
The command register is used to invoke one of 19 possible
AVDC commands as described in COMMANDS. The remaining registers in the group store address values which
specify the cursor location, the location of the first character
to be be displayed on the screen, and any split screen address locations. The user initializes these registers after
powering on the system and changes their values to control
the data which is displayed.
SCREEN START REGISTERS 1 AND 2
The screen start 1 registers contain the address of the first
character of the first row (upper left corner of the active
display). At the beginning of the first scan line of the first
row, this address is transferred to the row start register
(RSR) and into the memory address counter (MAC). The
counter is then advanced sequentially at the character clock
rate for the number of times programmed into the active
characters per row register (lR5), thus reaching the address
of the last character of the row plus one. At the beginning of
each subsequent scan line of the first row, the MAC is
reloaded from the RSR and the above sequence is repeated.
At the end of the last scan line of .thefirst row, the contents
of the MAC is loaded into the RSR to serve as the starting
memory address for the second character row. This process
is repeated for the programmed number of rows per screen.
Thus, the data in the display memory is displayed sequentially starting from the address contained in the screen start
register. After the ensuing vertical retrace interval, the entire
process repeats again.
During vertical blanking, the address counter operation is
modified by stopping the automatic load of the contents of
the RSR into the counter, thereby allowing the address outputs to free-run. This allows dynamic memory refresh to occur during the vertical retrace interval. The refresh address-

FIGURE 18 -

DISPLAY CONTROL REGISTER FORMATS (Sheet 1 of 2)

4

3

2

a

Command Code

See COMMANDS for Command Codes

Command Registers (Write Only)

6

5

4

3

Upper Register

DADD15

Most Significant Bits

DADD14

MOTOROLA MICROPROCESSOR DATA

3-55

a

II

MC2674

FIGURE 18 -

DISPLAY CONTROL REGISTER FORMATS (Sheet 2 of 2)

4
3
Lower Register (Least Significant Bit)

6
.
H'OOOO'=O
H'OOO1'= 1
Through
H'3FFE' = 16,382
H'3FFF' = 16,383

o

NOTE: Most significant bits are in upper register [5:0]

NOTES:
1. Bits 7 and 6 of upper register are not used in the cursor address register.
2. Bits 7 and 6 of upper register are always zero when read by the CPU.
3. When I RO[7] = 1, the values written into bits 7 and 6 of screen start 1 upper will also be written into
IR14[7:6] to control the double width and double height attributes of the display as follows:

Z

o
o
1
1

I

~
0
1
0
1

~
None
Double Width Only
Double Width and Double Height Tops
Double Width and Double Height Bottoms
Screen Start 1 Register (Read and Write) and
Cursor Address Registers (Read and Write)

7

6

SPL2
0= Off
1=On

SPL1
O=Off
1='On

7

6

H'OOOO'=O
H'000 l' = 1
Through
H'3FFE' = 16,382
H'3FFF = 16,383

4
3
Upper Register

Most Significant Bits

5

4
Lower Register (Least Significant Bit)

NOTE: Most significant bits are in upper register [5:0]

NOTE:
Bit 7 and bit 6 are always zero when read by the CPU.
Screen Start 2 Registers (Read and Write)

When row table addressing mode is enabled, the first address of the row table is designated in SSR2. The AVDC
fetches the next row's starting address from the table during
the blanking interval prior to the first scan line of each character row and loads it into SSR1 for use as the starting address of the next row. Since the contents of SSR2 changes
as the table entries are fetched, it must be re-initialized to
pOint to the first table entry during each vertical retrace interval.
The values of the two most significant bits of SSR1 upper
are multiplexed onto the DADD1/DADD14 and DADD2/
DADD15 outputs during the falling edge of BLANK. If
IRO[7] =0, these two bits act as memory page select bits
which may be used to extend the display memory addressing

range of the AVDC up to 64K. In that case, these two bits
act as a two-bit counter which is incremented each time that
"wraparound" occurs (see above). Note that the counter is
incremented at the falling edge of BLANK and that for proper display operation the wraparound address should be programmed to occur at the last character position of a row.
Also, the first address accessed in the new page will be the
address contained in the display buffer first address register
(IR9[3:0] and IR8[7:011.
CURSOR ADDRESS REGISTERS
The contents of these registers define the buffer memory
address of the cursor. The cursor output will be asserted
when the memory address counter matches the value of the

MOTOROLA MICROPROCESSOR DATA
3-56

MC2674

FIGURE 19 -

DISPLAY ADDRESSING OPERATION

o ..--------,

Screen Start -

r-..-..,.......,.......,.......,...-~

Monitor
Display

1-""-"'-"'-"'-"'-"''''"'''''1- D ispl ay Buffer End

16K

'------~

Memory
(a) Display Memory Wraparound

o ,.---------,
:.:.~":':':':':':':':':':':':':::':

-

:::::~:::::::::::::::::::::::::::::: -

Screen Start 1 -

Display Buffer Start
Bottom of Screen

m777"?'",...,...,,..,...,77.,..,)

SplitSocooo-

Screen Start 2 -

~

k-..,...-..,...-..,...-..,...-..,...-~

~.......:>.......:>.......:>~~"'-; -

Display Buffer End

Monitor
Display

16KL-,..-----~

Memory
(b) Display Memory Split Screen With Wraparound

cursor address registers for the scan lines specified in IR6.
The cursor address registers can be read or written by the
CPU or incremented via the "increment cursor address"
command. In independent buffer mode, these registers
define a buffer memory address for AVDC controlled access
in response to "read/write at cursor with/without increment" commands, or the first address to be used in
executing the "write from cursor to pointer" command.

(masked) from causing interrupts by certain AVDC commands. An interrupt condition which is enabled (masked bit
equal to one) will cause the INTR output to be asserted and
will cause the corresponding bit in the interrupt register to be
set upon the occurrence of the interrupting condition. An
interrupt condition which is disabled (mask bit equal to zero)
has no effect on either the INTR output or the i{lterrupt
register.
The status register provides six bits of status information:
the five possible interrupt conditions plus the RDFLG bit. For
this register, however, the contents are not affected by the
state of the mask bits.
Descriptions of each interrupt/status register bit follow.
Unless otherwise indicated, a bit, once set, will remain set
until reset by the CPU by issuing a "reset interrupt/status
bits" command. The bits are also reset by a "master reset"
command and upon power-up.

INTERRUPT/STATUS REGISTERS
The interrupt and status registers provide information to
the CPU to allow it to interact with the AVDC to effect
desired changes that implement various display operations.
The interrupt register provides information on five display
operations. The interrupt register provides information on
five possible interrupt conditions, as shown in Figure 20.
These conditions can be selectively enabled or disabled

MOTOROLA MICROPROCESSOR DATA
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I

MC2674

FIGURE 20 -INTERRUPT AND STATUS REGISTER FORMAT

VBLANK
O=No
1=Yes

RDFLG
0= Busy
1= Ready

Not Used
Always Read as.O

I

4

5

6

3
Line
Zero
O=No
1 = Yes

RDFLG (IISR[5]) - This bit is present in the status
register only. A zero indicates that the AVDC is currently
executing the previously issued delayed command. A one
indicates that the AVDC is ready to accept a new delayed
command.
VBLANK (l/SR[4]) - Indicates the beginning of a vertical
blanking interval. Set to one at the beginning of the first scan
line of the vertical front porch.
LINE ZERO (l/SR[3]) - Set to one at the beginning of the
first scan line (line Ol of each active character row.
SPLIT SCREEN 1 (l/SR[2]) - This bit is set when a match
occurs between the current character row number and the
value contained in split register 1, IR12[6:0]. The equality
condition is only checked at the beginning of line zero of
each character row.
READY (l/SR[1J) - The delayed commands affect the
display and may require the AVDC to wait for a blanking
interval before enacting the command. This bit is set to one
TABLE 3 D1

D6

D5

D4

D3

D2

o

2

Split 1
O=No
1= Yes

Ready
0= Busy
1= Ready

Split 2
O-No
1= Yes

when execution of a delayed command has been completed.
No other delayed command should be invoked until the prior
deiayeo command is completed.
SPLIT SCREEN 2 (l/SR[O)) - This bit is set when a match
oCCurs between the current character row number and the
value contained in split register 2 (IR13[6:0]).

COMMANDS

The A VDC commands are divided into two classes: the instantaneous commands which are executed immediately
after they are invoked, and the delayed commands which
may need to wait for a blanking interval prior to their execution. Command formats are shown in Table 3. The commands are asserted by performing a write operation to the
command register with the appropriate bit pattern as the
data byte.

AVDC COMMAND FORMATS

D1

DO

Command

Hex

Instantaneous Commands

0
0
0
0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
0
1
0
1

0
0
1
1
1
1
1
1
0
0
1

0
1
d
d
d
d
1
1
N
N
N

0
V
d
d
1
1
d
d
N
N
N

0
V
d
d
N
N
d
d
N
N
N

0
V
1
.1
d
d
d
d
N
N
N

0
V
0*
1*
0*
1*
0*
1*

V
S

L
Z

S
P
1

R
D
y

S
P
2

0
0
0
0
0
0
0
1
1

0
0
1
1
1
1
.1
1
1

1
0
0
1
0
1
0
0
1

0
1
0
0
1
0
1
1
0

Master Reset
Load IR Pointer with Value V (V=O to 14)
Disable Graphics
Enable Graphics
Display Off - Float DADD Bus if N = 1
Display On - Next Field (N = 1) or Scan Line (N = 0)
Cursor Off
Cursor On
Reset Interrupt/Status: bit Reset where N=1
Disable Interrupt: Disable where N = 1
Enable Interrupt: Enables Interrupts where N = 1

N
N
N

Interrupt sit
Assignments

Delayed Commands

1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1
1

0
0
1
0
0
1
t
1
1

A4
A2
A9
AC
AA
AD
AS
BS

SO

Read at Pointer Address
Write at Pointer Address
Increment Cursor Address
Read at Cursor Address
Write at Cursor Address
Read at Cursor Address and Increment Address
Write at Cursor Address and Increment Address
Write from Cursor Address to Pointer Address
Read from Cursor Address to Pointer Address

NOTES:
*Any combination of these three commands is valid.
d = Don't care.

MOTOROLA MICROPROCESSOR DATA
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MC2674

INSTANTANEOUS COMMANDS
The instantaneous commands are executed immediately
after the trailing edge of the write pulse during which the
command is issued. These commands do not affect the state
of the RDFLG or READY interrupt/status bits and can be invoked at any time.

DISPLAY ON
Restores normal blanking operation either at the beginning
of the next field (bit 2= 1) or at the beginning of the next
scan line (bit 2=0). Also returns the DADDO-DADD13
drivers to their active state.
CURSOR OFF
Disables cursor operation. Cursor output is placed in the
low state.

MASTER RESET
This command initializes the AVDC and can be invoked at
any time to return the AVDC to its initial state. Upon powerup, two successive master reset commands must be applied
to release the AVDC's internal power-on circuits. In
transparent and shared buffer modes, the CTRL1 input must
be high when the command is issued. The command causes
the following:
1. VSYNC and HSYNC are driven low for the duration of
the command and BLANK goes high. After command
completion, HSYNC and VSYNC will begin operation
and BLANK will remain high until a "display on" command is received.
2. The interrupt and status bits and masks are set to zero,
except for the RDFLG flag which is set to a one.
3. The row buffer mode, cursor-off, display-off, and line
graphics disable states are set.
4. The initialization register pointer is set to address IRO.
5. IR2[7] is reset.

CURSOR ON
Enables normal cursor operation.
RESET INTERRUPT/STATUS BITS
This command resets the designated bits in the interrupt
and status registers. The bit positions correspond to the bit
positions in the registers:
Bit 0 - Split 2
Bit 1 - Ready
Bit 2 _. Split 1
Bit 3 - Line Zero
Bit 4 - Vertical Blank
DISABLE INTERRUPTS
Sets the interrupt mask to zeros for the designated conditions, thus disabling these conditions from being set in the
interrupt register and asserting the INTR output. Bit position
correspondence is as above.

LOAD IR ADDRESS
This command is used to preset the initialization register
pointer with the value "V" defined by D3-DO. Allowable
values are 0 to 14.

ENABLE INTERRUPTS
This command writes the associated interrupt mask bit to
a one. This enables the corresponding conditions to be' set in
the interrupt register and asserts the INTR output. Bit position correspondence is as above.

ENABLE GRAPHICS
After invoking this command, the AVDC will increment
the MAC to the next consecutive memory address for each
scan line even ifmore than one scan line per row is programmed. This mode can be used for bit-mapped graphics where
each location in the display buffer within the defined area
contains the bit pattern to be displayed. This command is
row buffered and should be asserted during the character
row prior to the row where this feature is required. This
allows the UiOer to enter and exit graphics mode on character
row boundaries.
To perform split screen operations while in graphics mode
use SSR2 only.
DADDO/LG is asserted during the trailing edge of BLANK
for each scan line while this mode is active.

DELAYED COMMANDS
This group of commands is utilized for the independent
buffer mode of operation, although the "increment cursor"
command can also be used in other modes. With the exception of the "write from cursor to pointer" and "increment
cursor" commands, all the commands of this type will be
executed immediately or will be delayed depending on when
the command is invoked. If invoked during the active screen
time, the command is executed at the next horizontal blanking interval. If invoked during a vertical retrace interval or a
"display off" state, the command is executed immediately.
The "increment cursor" command is executed immediately after it is issued and requires approximately three CCLK
periods for completion. The "write from cursor to pointer"
command executes during blanking intervals. The AVDC will
execute as many writes as possible during each blanking
interval. If the command is not completed during the current
blanking interval, the command will be held in suspension
during the next active portion of the screen and continues
during the next blanking interval until the command is
completed.

OlSABLE GRAPHICS
Normal addressing resumes at the next row boundary.
DISPLAY OFF
Asserts the BLANK output. The DADDO through DADD13
display address bus outputs can be optionally placed in the
three-state condition by setting bit 2 to a one when invoking
the command.

ORDERING INFORMATION (VCC=5 V±5%, TA=O°C to 70°C)

MOTOROLA MICROPROCESSOR. DATA
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I

MC2674

PIN ASSIGNMENT

R
CE

vcc
A2
A1
AO

CTRL1

ACLL
INTR

02

DADDO/LG
DADD1/
DADD14
DADD2/
DADD15
DADD3/LR

04

DADD5/LA1

05

DADD6/LA2

CURSOR
DO
01

DADD4/LAO

I

06

DADD7/LA3

07

DADDS/FL

CCLK

DADD9/DW

BLANK
VSYNC/
CSYNC
HSYNC

DADD10/UL
DADD11!
BLINK
DADD12/
ODD
DADD13/LL

GND

MOTOROLA MICROPROCESSOR DATA
3-60

MOTOROLA

• SEMICONDUCTOR
TECHNICAL DATA

MC6800

8-Bit Microprocessing Unit (MPU)
The MC6800 is a monolithic 8-bit microprocessor forming the central control function for Motorola's
M6800 Family. Compatible with TTL, the MC6800, as with all M6800 system parts, requires only one
+ 5.0-volt power supply and no external TTL devices for bus interface.
The MC6800 is capable of addressing 64K bytes of memory with its 16-bit address lines. The 8-bit data
bus is bidirectional as well as three-state, making direct memory addressing and multiprocessing applications realizable.
• 8-Bit Parallel Processing
• Bidirectional Data Bus
• 16-Bit Address Bus - 64K Bytes of Addressing
• 72 Instructions - Variable Length
• Seven Addressing Modes - Direct, Relative, Immediate, Indexed, Extended, Implied, and
Accumulator
• Variable Length Stack
• Vectored Restart
• Maskable Interrupt Vector
• Separate Nonmaskable Interrupt - Internal Registers Saved in Stack
• Six Internal Registers - Two Accumulators, Index Register, Program Counter, Stack Pointer and
Condition Code Register
• Direct Memory Addressing (DMA) and Multiple Processor Capability
• Simplified Clocking Characteristics
• Clock Rates as High as 2.0 MHz
• Simple Bus Interface without TTL
• Halt and Single Instruction Execution Capability

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR D'ATA
3-61

II

MC6800

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Rating

VCC

-0.3 to + 7.0

V

Input Voltage

Vin

-0.3,to+ 7.0

V,

Operating Temperature Range
MC6800, MC68AOO, MC68BOO,
MC6800C, MC68AOOC
"

TA

TL to TH
-0 to 70
-40 to;+-:85

°c

Tstg

-55 to + 150

°c

Symbol

Value

Unit

6JA

100
60

°CIW

Storage Temperature Range

THERMAL RESISTANCE
Rating
Plastic Package
Cerdip Package

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in °Ccan be obtained from:
(1 )

TJ=TA+(PO·6JA)
where:

= Ambient Temperature, °c
= Package Thermal Resistance,
Junction-to-Ambient, °CIW
Po
= PINT+PPORT
PINT
= ICC x Vec, Watts - Chip Internal Power
PPORT = Port Power Oissipation, Watts - User Oetermined
.
For most applications PPORT1.412
Logic
tf>1.tf>2

Input Low Voltage
Input Leakage Current
(Vin = 0 to 5.25 V, V CC = Maxi
(Vin=O to 5.25 V, Vce=O V to 5.25 VI
Hi-Z Input Leakage Current
(Vin = 0.4 to 2.4 V, V ce = Maxi
Output High Voltage
Ii Load = -200p.A. Vec=Minl
Ii Load = -l45p.A, Vee= Mini
Ii Load = -100p.A, VCC= Mini
Output Low Voltage liLoad-l.6 rnA, VCC= Mini

Logic
tf>l. tf>2
00-07
AO-A15. R/W
00-07
AO-A15. R/IN. VMA
SA

Symbol

Min

Typ

Max

Unit

VIH
VIHC

VSS+2.0
VCC- 0.6

-

VCC
Vce+ 0 .3

V

VIL
VILC

VSS-0.3
VSS-0.3

-

VSS+0.8
VSS+O.4

V

lin

-

1,0
-

2.5
100

-

2.0
-

10
100

-

-

liZ

VOH

Capacitance
(Vin=O, TA=25°C, f=1.0MHzI

tf>1
tf>2
00-07
Logic Inputs
AO-A15, R/W, VMA

VSS+2.4
VSS+2.4
VSS+2.4

-

Cin

-

Cout

MOTOROLA MICROPROCESSOR DATA
3-62

-

PINT

VOL

Internal Power Dissipation (Measured at T A = TLI

-

-

-

-

-

-

-

0.5

VSS+0.4
1.0

p.A

p.A

V

V
W

35

25
45
10
6.5

70
12.5
10

pF

-

12

pF

MC6800

CLOCK TIMING (VCC=50 V

±5% VSS=O TA=TLto TH unless otherwise noted)

Symbol

Min

Typ

Max

Unit

MCSIm
MC68Aoo
MC68Boo

-

f

0.1
0.1
0.1

-

1.0
1.5
2.0

MHz

MCSIm
MC68Aoo
MC68Boo

1.000·

-

tcyc

-

10
10
10

"s

ns

Characteristic:
Frequency of Operation

Cycle Time (Figure 1)

Clock Pulse Width
(Measured at V CC - 0.6 V)

1/>1.1/>2 - MCSIm
1/>1.1/>2 - MC68Aoo
.pl • .p2 - MC68Boo

Total I/> 1 and.p2 Up Time

400

-

230
180

-

-

9500
9500
9500

-

-

900
600

tut

Rise and Fall Time (Measured between VSS+0.4 and VCC-0.6)

-

-

ns

440

-

-

tr. tf

-

-

100

ns

td

0
0

-

9100
9100

ns

Delay Time or Clock Separation (Figure 1)
(Measured at VOV=VSS+0.6 V@tr=tfs1oonS)
(Measured at VOV=VSS+ 1.0 V@tr=tfs35 ns)

FIGURE 1 -

0.666
0.500

PWI/>H

MCSIm
MC68Aoo
MC68Boo

-

-

CLOCK TIMING WAVEFORM

II

~----------------tcyc----------------~

.p1

NOTES:
1. Voltage levels shown are VLsO.4. VH~2.4 V. unless otherwise specified.
2. Measurement points shown are 0.8 V imd 2.0 V. unless otherwise noted.

READ/WRITE TIMING (Reference Figures 2 through 6. 8. 9,11.12 and 13)
Symbol

Characteristic

MCeeoo

MC68AOO

Min

Typ

Max

Min

-

-

270
250

360

Max

Min

-

-

180
165

-

-

-

Max

-

150
135

ns

-

250

-

-

ns

-

40

-

-

25

-

10

25

-

ns

10

-

tAD

Peripheral Read Access Time
tacc=tl,lt- ItAD+tDSR)

tacc

530

-

-

60

-

10

-

10

-

tDSR

100

Input Data Hold Time

tH

10

-

Output Data Hold Time

tH

10

25

-

Address Hold Time (Address. R/W. VMA)

tAH

30

50

-

30

50

-

30

50

Enable High Time for DBE Input

tEH

450

-

-

280

-

-

220

tDDW

-

-

225

-

-

200

-

-

tpcs
tPCr. tPCf
tBA
tTSE
tTSD
tDBE
tDBEr. tDBEf

200

-

140

-

-

-

-

-

0

-

0

-

-

-

100
250
40
270

150

-

-

-

Data Setup Time (Read)

Data Delay Time (Write)
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
Bus Available Delay
Hi-Z Enable
Hi-Z Delay
Data Bus Enable Down Time During .pl Up Time
Data Bus Enable Rise and Fall Times

-

110

-

-

-

75

-

-

-

120

25

-

-

25

MOTOROLA. MICROPROCESSOR DATA

3-63

100
165
40
270

-

Unit

Typ

Address Delay
C=90 pF
C=30 pF

-

MC68BOO

Typ

-

0

-

-

ns
ns
ns

-

ns

160

ns

100
135
40

220

25

ns

MC6800

FIGURE 2 - READ DATA FROM MEMORY OR PERIPHERALS
, . . , Start of Cycle

1/>1

1/>2

RtW
Address
FromMPU __

~~~~~~~~~

________________________________

~~--

VMA

-_-+--_____tacc-------_+__

I

Data
From Memory ---------------------------c:r:m~
or Peripherals

-="'4:--=::;;;;;:;;;;;;;;;;F

~~ Data Not Valid
FIGURE 3 - WRITE IN MEMORY OR PERIPHERALS
, . - - Sta" of Cycle

~-------------------tCyC------------~

1/>1

RtW
Addr_
FromMPU __

~~~~~~~~---------------------------------_+~~

VMA _ _ _ _~-.

~~--------tEH~-----~

oBE

Data
FromMPU

--------------------~--.a~~"

Data Valid

L\\\\,\\\'1 Data Not Valid
NOTES:
1. Voltage levels shown are VLSOA, VHC!:2A V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise noted.

MOTOROLA MICROPROCESSOR DATA
3-64

MC6800

FIGURE 4 - TYPICAL DATA BUS OUTPUT DELAY
versus CAPACITIVE LOADING (TDDW)
600
500

]

600

10H =-205 pA max@2.4 V
10L = 1.6 mA max@0.4 V
VCC=5.0V
lA = 2SoC

SOO

400

]
....

UJ
~

i= 300
>

~

0

FIGURE 6 ..... TYPICAL READ/WRITE, VMA, AND ADDRESS
OUTPUT DELAY versus CAPACITIVE LOADING (TAD)

100

---

....- ..-

200

~

400

~

-

i=
> 300

~"""

~
0

-I--

200
100

CL includes stray capacitance
100

300

200

10H =-14S pA max@ 2.4 V
10L = 1.6 mA max@0.4V
VCC = S.O V
TA = 2SoC

400

SOO

....-

--

Vi"""" ~

I--'

r-

VMA
I
Address, RIW- ~

~

100

600

~

!-- V

CL, LOAD CAPACITANCE (pF)

CL includes stray capacitance
200

300

400

FIGURE 6 - BUS TIMING TEST LOADS
Vcc
TEST CONDITIONS
Test Point

0-_-_-44--..

MMD6150

The dynamic test load for the Data Bus is
,30 p F and one standard TT L load as shown.
The Address, Rm, and VMA outputs are tested
under two conditions to allow optimum operation in both buffered and unbuffered systems.
The resistor (R) is chosen to insure specified
load currents during VOH measurement.
Notice that the Data Bus lines, the Address
lines, the Interrupt Request line, and the DBE
, line are all specified and tested to guarantee
0.4 V of dynamic noise immunity at both
"," and "0" logic levels.

or Equiv.

C

R
MMD 7000
or Equiv.

c=

130 pF for 00-07, E

= 90 pF

for AO-A15, R/W, and VMA

(Except tAD2)

= 30 pF

for AO-A15, R/Vii, and VMA

(tAD2 only)
= 30 pF for BA

kn for 00-07
kn for AO-A15,
kn for BA

R = 11.7

= 16.5

= 24

500

600

CL, LOAD CAPACITANCE (pF)

R/W, and VMA

MOTOROLA MICROPROCESSOR DATA
3-65

I

MC6800

FIGURE 7 - EXPANDED BLOCK DIAGRAM

A15

A14

A13

A12

All

A10

A9

A8

07

06

05

04

03

02

01

DO

A7

I

Clock,

.1

CIock,.2
~

Non-Maskable Interrupt
HALT
Interrupt Request
Three-State Control

I

Data Bus Enable
Bus Available
Valid Memory Address
Read/Write, R/W

VCc=Pin 8
Vss ... Pins 1, 21

MOTOROLA MICROPROCESSOR DATA
3-66

A6

A5

A4

A3

A2

A1

AO

MC6800

MPU SIGNAL DESCRIPTION
Proper operation of the MPU requires that certain control
and timing signals be provided to accomplish specific functions and that other signal lines be monitored to determine
the state of the processor.

Read (high) or Write (low) state. The normal standby state of
this signal is Read (high), Three-State Cqntrol going high will
turn Read/Write to the off (high impedance) state. Also,
when the processor is halted, it will be in the off state. This
output is capable of driving one standard TTL load and
90 pF.

Clocks Phase. One and Phase Two (q,1, 412) - Two pins
are used for a two-Phase non-overlapping clock that runs at
the V CC voltage level.
Figure 1 shows the microprocessor clocks. The high level
is specified at VIHC and the low level is specified at VILC.
The allowable clock frequency is specified by f (frequency!.
The minimum q,1 and q,2 high level pulse\'IIidths are specified
by PWq,H (pulse width high time!. To guarantee the required
access time for the peripherals, the clock up time, tut, is
specified. Clock separation, td, is measured at a maximum
voltage of VOV (overlap voltage). This allows for a multitude
of clock variations at the system frequency r.ate.

RESET - The RESET input is used to reset and start the
MPU from a power down condition resulting from a power
failure or initial start-up of the processor. This level sensitive
input can also be used to reinitialize the machine at any time
after start~up.
If a high level is detected in this input, this will Signal the
MPU to begin the reset sequence. During the resetsequence, the contents of the last two locations (FFFE, FFFF)
in memory will be loaded into the Program Counter to point
to the beginning of the reset routine. During the reset
routine, the interrupt mask bit is set and must be cleared
under program control before the MPU can be interrupted by
IRQ. While RESET is low (assuming a minimum of 8 clock
cycles have occurred) the MPUoutput signals will be in the
following states: VMA=low, BA=low, Data Bus=high impedance, R/W = high (read state I, and the Address Bus will
contain the reset address FFFE. Figure 8 illustrates a power
up sequence using th~ RESET control line. After the power
supply reaches 4.75 V, a minimum of eight clock cycles are
required for the processor to stabilize in preparation for
restarting; During these eight cycles, VMA will be in an indeter'minate state so any devices that are enabled by VMA
which could accept a false write during this time (such as
battery-backed RAM) must be disabled untilVMA is forced
low after eight cycles. RESET can go high asynchronously
with the system clock any time after the eighth cycle.

Address Bus (AO-A 15) - Sixteen pins are used for the address bus. The outputs are three-state bus drivers capable of
driving one standard TTL load and 90 pF. When the output is
turned off, it is essentially an open circuit. This permits the
MPU to be used in DMA applications. Putting TSC in its high
state forces the Address bus to go into the three-state mode.
Data Bus (00-07) - Eight pins are used for the data bus.
It is bidirectional, transferring data to and from the memory
and peripheral devices. It also has three-state output buffers
capable of driving one standard TTL load and 130 pF. Data
Bus is placed in the three-state mode when DBE is low.
Data Bus Enable (DBE) - This level sensitive input is.the
three-state control signal for the MPU data bus and will
enable the bus drivers when in the high state. This input is
TTL compatible; however in normal operation, it would be
driven by the phase two clock. During an MPU read cycle,
the data bus drivers will be disabled internally. When it is
desired that another device control the data bus, such as in
Direct Memory Access !DMA) applications, DBE should be
held low.
If additional.data setup or hold time is required on an MPU
write, the DBE down time can be decreased, as shown in
Figure 3 (DBE:;e:q,2). T,he minimum down time for DBE is
tDBE as shown. By skewing DBE with respect to E, data
setup or hold time can be increased.

RESET timing 'is ~hownin Figure 8. The maximum rise and
falltransition timeS are specified by tPCr and tPCf.lf RESET
is high at tpcs (processor control setup time), as shown in
Figure 8, in any given cycle then the restart sequence will
begin on the next cycle as shown. The RESET control line
may also be used to reinitialize the M PU system at any time
during its operation. This is accomplished bypulsing RESET
low for the duration of a minimum of three complete q,2
cycles. The RESET pulse can be completely asynchronous
with theMPU system clock and will be recognized during q,2
if setup time tpcs is met.
Interrupt Request (IRQ) - This level sensitive input requests that an interrupt sequence be generated within the
machine. The processor will wait until it completes the current instruction that is being executed before it recognizes
the request. At that time, if the interrupt mask bit in the Condition Code Register is not set, the machine will begin an interrupt sequence. The Index Register, Program Counter, Accumulators, a.nd Condition Code Register are stored away on
the .stack. Next, the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further
interrupts may occur. At the end of the cycle, a 16-bit address will be loaded that points to a vectoring address which
is located in memory locations FFF8 and FFF9. An address
loaded at these locations causes the MPU to branch to an interrupt routine in memory. Interrupt timing is shown in
Figure 9.

Bus Available (BA) - The Bus Available signal will normally be in the low state; when activated, it will go to the
high state indicating that the microprocessor has stopped
and that the address bus is available. This will occur if the
HALT line is in.the low state or the processor is in the WAIT
state as a result of the execution of a WAIT instruction. At
such time, all three-state output drivers will go to their off
state and other outputs to their normally inactive level. The
processor is removed from the WAIT state by the occurrence
of a maskable (mask bit 1=0) or nonmaskable interrupt. This
output is capable of driving one standard TTL load and
30 pF. If TSC is in the high state, Bus Available will be low.
Read/Write (R/W) - This TTL compatible output signals
the peripherals and memory devices wether the MPU is in a

MOTOROLA MICROPROCESSOR DATA
3~67

I

.

...

I

C.YCle

#1

I

FIGURE 8 -

1#5

#2

#6

pow.::~J·

.

Switch

~:;;y ~-.-~:::: ~

#8

#7

'

In + 11n + 21n +31 n+41 n+51 m 1m +1\m + 21m + 31

#9

~

:
.

ff

..

E . .. .: E....

f..·

-----I

n

RffiT

•

RESET TIMING

If

II

. ..
tpcs

.
.

~

tpcs· .

-r'N~______

--l ~

--1. I-""- tPCr

tpCf

:~:re... I\\\\\\\\\\\\\\\\\\\\\\\\\\_tm\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\~

s:

a

::~====::::s-' mE ;,mE

~

o

~

s:

w

n

Datil BUI

%M\\\\\\\\\\\\\\\\""'1Jss\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\~~~'----"-_--J'--_J'-_--""---_"'--4
r(

B A \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\})\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\

If

s:o

~

a, o
co ~
~
C')
m
en
en

ffiill1!J

~

co

o
o

FIGURE 9 - INTERRUPT TIMING
Cycle

o
::J:I

g

0)

= Indeterminate

#3

#1

#2

____

____

#4

#5

#6

#7

#8

#9

#10

#11

#12

#13

#14

#15

cP2
Address
Bus
IRQ or
NMI

~::~ruPt
Data Bus

,
-J~'_

_',~

____

,~

____

,~

____

-'~

_ _- - J

New PC 8-15 New PC 0-7 First Inst of
Address
Address
Interrupt Routine

R/W
VMA

MC6800

time PWq,Hwithout destroying data within the MPU. TSC
then can be used in a short Direct Memory Access (DMA)
application.
Figure 12 shows the effect of TSC on the MPU. TSC must
have its transitions at tTSE (three-state enable) while holding
q,1 high and q,2 low as shown. The Address Bus and RIW
line will reach the high-impedance state at tTSD (three-state
delay), with VMA being forced low. In this example, the
Data Bus is also in the high-impedance state while q,2 is being held low since DBE=q,2. At this point in time, a DMA
transfer could occur on cycles '3 and #4. When TSC is
returned low, the MPU Address and R/Wlines return to the
bus. Because it is too late in cycle #5 to access memory, this
cycle is dead and used for synchronization. Program execution resumes in cycle '6.

The HALT line must be in the high state for interrupts to
be serviced. Interrupts will be latched internally while"RAC'f
is low.
The IRQ has a high-impedance pull up device internal to
the chip; however, a 3 kO external resistor to VCcshould be
used for wire-OR and optimum control of interrupts.
Non-Makable Interrupt (NMII and Wait for Interrupt
(WAil - The MC6800 is capable of handling two types of interrupts: maskable (IRQ) as described earlier, and nonmaskable (NMII which is an edge sensitive input. IRQ is
maskable by the interrupt mask in the condition code register
while NMI is not maskable. The handling of these interrupts
by the M PU is the same except that each has its own vector
address. The behavior of the MPU when interrupted is
shown in Figure 9 which details the MPU response to an interrupt while the MPU is executing the control program. The
interrupt shown could be either iRTI or NMT and can be asynchronous with respect to q,2. The interrupt is shown going
low at time tpcs in cycle #, which precedes the first cycle of
an instruction (OP code fetch). This instruction is not executed but instead the Program Counter (PC), Index
Register (IX). Accumulators (ACCX), and the Condition
Code Register (CCR) are pushed onto the stack.
The Interrupt Mask bit is set to prevent further interrupts.
The address of the interrupt service routine is then fetched
from FFFC, FFFD for an NMI interrupt and from FFF8, FFF9
for an IRQ interrupt. Upon completion of the interrupt service routine, the execution of RTI will pull the PC, IX, ACCX,
and CCR off the stack; the Interrupt Mask bit is restored to
its condition prior to Interrupts (see Figure '0).
Figure " is a similar interrupt sequence, except in this
case, a WAIT instruction has been executed in prepar.ation
for the interrupt. This technique speeds up the MPU's
response to the interrupt because the stacking of the PC, IX,
ACCX, and the CCR is already done. While the MPU is
waiting for the interrupt, Bus Available will go high indicating the following states of the control lines: VMA is low,
and the Address Bus, R/W and Data Bus are all in the high
impedance state. After the interrupt occurs, it is serviced as
previously described.
A 3-'0 kQ external resistor to V CC should be used for wireOR and optimum control of interrupts.

Valid Memory Address (VMA)- This output indicates to
peripheral devices that there is a valid address on the address
bus. In normal operation, this signal should be utilized for
enabling peripheral interfaces such as the PIA and ACIA.
This signal is not three-state. One standard TTL load and
90 pF may be directly driven by this active high signal.
HALT - When this level sensitive input is in the low state,
all activity in the machine will be halted. This input is level
sensitive.
The HALT line provides an input to the MPU to allow control of program execution by an outside source. If HALT is
high, the MPU will execute the instructions; if it is low, the
MPU will go to a halted or idle mode. A response signal, Bus
Available (BA) provides an indication of the current MPU
status. When BA is low, the M PU is in the process of executing the control program; if BA is high, the MPU has
halted and all. internal activity has stopped.
When BA is high, the Address Bus, Data Bus, and R/iN
line will be in a high-impedance state, effectively removing
the MPU from the system bus. VMA is forced low SO that the
floating. system bus will not activate any device on the bus
that is enabled by VMA.
While the MPU is halted, all program activity is stopped,
and if either an NMI or IRQ interrupt occurs, it will be latched
into the MPU and acted on as soon as the MPU is taken out
of the halted mode. If a RESET command occurs while the
MPU is halted, the following states occur: VMA= low,
BA=low, Data Bus=high impedance, R/W=high (read
state), and the Address Bus will contain address FFFE as
long as RESET is low. As soon as the RESET line goes high,
the MPU will go to locations FFFE and FFFF for the address
of the reset routine.
Figure 13 shows the timing relationships involved when
halting the MPU. The instruction illustrated is a one byte, 2
cycle instruction such as CLRA. When HALT goes low, the
MPU will halt after completing execution of the current instruction. The transition of HALT must occur tpcs before
the trailing edge of q, 1 of the last cycle of an instruction
(point A of Figure 13), HALT must not go low any time later
than the minmum tpcs specified.
The fetch of the OP code by the MPU is the first cycle of
the instruction. If HALT had not been low at Point A but
went low during q,2 of that cycle, the MPU would have
halted after completion of the following instruction. BA will
go high by time tBA (bus available delay time) after the last
instruction cycle. At this point in time, VMA is low and R/W,
Address Bus, and the Data Bus are in the high-impedance
state.

MEMORY MAP FOR INTERRUPT VECTORS
Vector
MS

LS

FFFE
FFFC
FFFA
FFF8

FFFF
FFFD
FFFB
FFF9

Description
Reset
NoncMaskable Interrupt
Software Interrupt
Interrupt Request

Refer to Figure 10 for program flow for Interrupts.

Three-State Control (TSC) - When the level sensitive
Three-State Control (TSC) line is a logic ",", the Address
Bus and the R/W line are placed in a high-impedance state.
VMA and BA are forced low when TSC= "'" to prevent
false reads or writes on any device enabled by VMA. It is
necessary to delay program execution while TSC is held
high. This is done by insuring that no transitions of q,1 (or q,2)
occur during this period. (Logic levels of the clocks are irrelevant so long as they do not change). Since the MPU is a
dynamic device, the q,1 clock can be stopped for a maximum

MOTOROLA MICROPROCESSOR DATA
3-69

II

MC6800

To debug programs it is advantageous .to step through
programs instruction by instruction. To do this, HALT must
be brought high for one MPU cycle and then returned low as
shown at point B of Figure 13. Again, the transitions of
RArT must occur tpcs before the trailing edge of ct> 1. BA
will go low at tBA after the leading edge of the next ct>1, indicating that the Address Bus, Data Bus, VMA and R/W

lines are back on the bus. A single byte, 2 cycle instruction
such asLSR is used for this example also. During the first cycle, the instruction Y is fetched from address M + 1. BA
returns high at tBA on the last cycle of the instruction indicating the MPU is off the bus. If instruction Y had been
three cycles, the width of the BA low time would have been
increased by one cycle.

FIGURE 10 - MPU FLOW,CHART

I
Notes:
1. Reset is recognized at any position in the flowchart.
2. Instructions which affect the I-Bit act upon a one-bit buffer register,
"ITMP." This has the effect of delaying any CLEARING of the I-Bit one
clock time. Setting the I-Bit, however, is not delayed.

3. See Tables 6-11 for details of Instruction Execution.

MOTOROLA MICROPROCESSOR DATA
3-70

FIGURE 11 - WAIT INSTRUCTION TIMING
Cycle
#1

#2

#4

#3

#5

#6

#7

#8

10-7

18-15

ACCA

ACCB

#9

I

#10

n+1

I

n+2

I

n+3

I

n+4

I

n+5

I

r
"'2

Address
Bus
RM
VMA
Interrupt
Mask

s:
o

a

IROor
NMI
Data Bus

::J:J

o

>
s:
n

Co\)

..:..
...a.

Wait
Inst

PC 0-7

PC 8-15

CCR

New PC 8-15 New PC 0--7
Address
Address

BA
Note: Midrange waveform indicates
high impedance state.

TBA

:s:
(")

~

o"g
~
o(')

0)

CO
Q
Q

m

FIGURE 12 -

f/)
f/)

o~
c

~

Cycle
#1

#2

#3

THREE-STATE CONTROL TIMING

=5

=4

=6

==7

=8

=9

System

1

MPU e/>1

~~~ress~" ~

on

--

II

~

=

R/W'{----n-~--------------~_f----------Y'--~Y'----){----'{-

~~:a ---XlU
e/>2·DBE

TSC

----;-'

II

Me6S00

FIGURE 13 - HALT AND SINGLE INSTRUCTION EXECUTION FOR SYSTEM DEBUG
Last Cycla
of Current
Instruction

rp2

BA

VMA

RiW

~--_\"""'------~fll- ____---J!

=

Fetch

'<

(11---"--"";-"

Execute

:~:ress ===)·~~~~]~LJ....__"';---------1t--------«

I

c==\
'--_ _ _J

Addr M + 1

Data ---~-)r----~--~---------------4I~----------------~
Bus
Inst
X

X

>-

>--

Inst
y

Note: Micirange waveform indicates
high impedance state.

MPU REGISTERS

The MPU has three 16-bit registers and three 8-bit
registers available for use by the programmer (Figure 14),

FIGURE 14 - PROGRAMMING MODEL OF
THE MICROPROCESSING UNIT

Program Counter - The program counter is a two byte
(16 bits) register that points to the current program address.
Stack Pointer - The stack ponter is a two byte register
that contains the address of the next available location in an
external push-down/pop-up stack. This stack is normally a
random access' Read/Write memory that may have any location (address) that is convenient. In those applications that
require storage of information in the stack when power is
lost, the stack must be nonvolatile.
Index Register ..;.. The index register is a two byte register
that is used to store data or a sixteen bit memory address for
the Indexed mode of memory addressing.

~_____. . I. Accumulator A
o
L.-_ _ _ _ _....JI

15

--'11

1-1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

15

ndex Register

0

1..1________________________----'1
15

Accumulator B

0

Program Cou nter

0

,'--_______________________--'1

Stack Pointer
Condition Code

Accumulators - The MPU contains two 8-bit accumulators that are used to hold operands and results from
an arithmetic logic unit (ALU).

L...Ji.-I.T"'-M~"'~ Register
Carry (From Bit 7)
Ovarflow

Condition Code Register - The condition code register indicates the results of an Arithmetic Logic Unit operation:
Negative (N), Zero (Z), Overflow (V), Carry from bit 7 (C),
and half carry from bit 3 (HI. These bits of the Condition
Code Register are used as testable conditions for the conditional branch instructions. Bit 4 is the interrupt mask bit (I).
The unused bits of the Condition Code Register (b6 and b7)
are ones.

MOTOROLA MICROPROCESSOR DATA
3-72

Zero
Negative
Interrupt
L -_ _ _ _ _ _

Half Carry (From Bit 3)

MC6800

MPU INSTRUCTION SET
The MC6800 instructions are described in detail in the
M6800 Programming Manual. This Section will provide a
brief introduction and discuss their use in developing
MC6800 control programs. The MC6800 has a set of 72 different executable source instructions. Included are binary
and decimal arithmetic, logical, shift, rotate, load, store,
conditional or unconditional branch, interrupt and stack
manipulation instructions.
Each of the 72 executable instructions of the source
language assembles into 1 to 3 bytes of machine code. The
number of bytes depends on the particular instruction and
on the addressing mode. (The addressing modes which are
available for use with the various executive instructions are
discussed later.)
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 72
instructions in all valid modes of addressing, are shown in
Table 1. There are 197 valid machine codes, 59 of the 256
possible codes being unassigned.

When an instruction translates into two or three bytes of
code, the second byte, or the second and third bytes contain(s) an operand, an address, or information from which an
address is obtained during execution.
Microprocessor instructions are often divided into three
general classifications: (1) memory reference, so called
because they operate on specific memory locations; (2)
operating instructions that function without needing a
memory reference; (3) I/O instructions for transferring data
between the microprocessor and peripheral devices.
In many instances, the MC6800 performs the same operation on both its internal accumulators and the external
memory locations. In addition, the MC6800 interface
adapters (PIA and ACIA) allow the MPU to treat peripheral
devices exactly like other memory locations, hence, no I/O
instructions as such are required. Because of these features,
other classifications are more suitable for introducing the
MC6800's instruction set: (1) Accumulator and memory
operations; (2) Program control operations; (3) Condition
Code Register operations.

TABLE 1 - HEXADECIMAL VALUES OF MACHINE CODES
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C

40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F

NOP

TAP
TPA
INX
DEX
ClV
SEV
ClC
SEC
CLI
SEI
SBA
CBA

50
51
52
53

54
TAB
TBA
DAA
ABA

10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
30
31
32
33
34
35
36
37

BRA

REl

BHI
BlS
BCC
BCS
BNE
BEQ
BVC
BVS
BPl
BMI
BGE
BlT
BGT
BlE
TSX
INS
PUl
PUl
DES
TXS
PSH
PSH

REl
REL
REl
REl
REl
REl
REl
REl
REl
REl
REl
REl
REL
REl

38
39
3A
3B
3C
3D
3E
3F

RTS
RTI

WAI
SWI

A
B

A
B

55
56
57
58
59
5A
5B
5C
50
5E
5F
60
61
62

63
64
65
66
67

68
69
6A
6B
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
70
7E
7F

NEG

A

COM
lSR

A
A

ROR
ASR
ASl
ROl
DEC

A
A
A
A
A

INC
TST

A
A

ClR
NEG

A
B

COM
lSR

B
B

ROR
ASR
ASl
ROl
DEC

B
B
B
B

INC
TST

B
B

ClR
NEG

B

B

IND

COM
lSR

INO
INO

ROR
ASR
ASl
ROl
DEC

INO
INO
IND
INO
INO

INC
TST
JMP
ClR
NEG

IND
IND
IND
INO
EXT

COM
lSR

EXT
EXT

ROR
ASR
ASl
ROl
DEC

EXT
EXT
EXT
EXT
EXT

INC
TST
JMP
ClR

EXT
EXT
EXT
EXT

80
81
82
83

SUB
CMP
SBC

A
A
A

IMM
IMM
IMM

84

AND
BIT
LOA

A
A
A

IMM
IMM
IMM

EOR
ADC
ORA
ADD
cPX
BSR
lOS

A
A
A
A
A

IMM
IMM
IMM
IMM
IMM
REl
IMM

SUB
CMP
SBC

A
A
A

DIR
DIR
DIR

AND
BIT
lOA
STA
EOR
ADC
ORA
ADD
CPX

A
A
A
A
A
A
A
A

DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR

85
86
87
88
89
8A
8B
8C
80
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF

lOS
STS
SUB
CMP
SBC

A
A
A

AND
BIT
lOA
STA
EOR
ADC
ORA
ADD
CPX
JSR
lOS
STS
SUB
CMP
SBC

A
A
A
A
A
A
A
A

AND
BIT
lOA
STA
EOR
ADC
ORA
ADD
CPX
JSR
lOS
STS

A
A
A
A
A
A
A
A

A
A
A

DIR
DIR
IND
INO
INO
INO
INO
INO
INO
INO
INO
INO
INO
INO
INO
INO
INO
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT

CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
01
02
03
D4
05
06
07
08
09
DA
DB
DC
DO
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF

SUB
CMP
SBC

B
B
B

IMM
IMM
IMM

AND
BIT
lOA

B
B
B

IMM
IMM
IMM

EOR
ADC
ORA
ADD

B
B
B
B

IMM
IMM
IMM
IMM

lOX

IMM

SUB
CMP
SBC

B
B
B

DIR
DIR
DIR

AND
BIT
lOA
STA
EOR
ADC
ORA
ADD

B
B
B
B
B
B
B
B

DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR

LOX
STX
SUB
CMP
SBC

B
B
B

DIR
DIR
INO
INO
INO

AND
BIT
lOA
STA
EOR
ADC
ORA
ADD

B
B
B
B
B
B
B
B

INO
INO
INO
INO
INO
INO
INO
INO

lOX
STX
SUB
CMP
SBC

B
B
B

INO
INO
EXT
EXT
EXT

AND
BIT
lOA
STA
EOR
ADC
ORA
ADD

B
B
B
B
B
B
B
B

EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT

lOX
STX

Notes: 1. Addressing Modes:

EXT
EXT

MOTOROLA MICROPROCESSOR .DATA
3-73

A
B
REl
IND
IMM
OIR

= Accumulator A
= Accumulator B

= Relative
= Indexed
= Immediate
=

Direct

2. Unassigned code indicated by

II

*

II •

II

MC6800

TABLE 2 -

ACCUMULATOR AND MEMORY OPERATIONS
BOOLEAN/ARITHMETIC OPERATION COND CODE REG

ADDRESSING MODES
IMMED
OPERATIONS
Add
Add Acmltrs
Add with Carry
And

Bit Test

MNEMONIC

OP

-

ADDA
ADDB

Compare
Compare Acmltrs
Complement,l's

Complement.2's
(Negatel
Decimal Adjust, A

II

Decrement

Exclusive OR
Increment

load Acmltr
Or, Inclusive

Push Data

Pull Oata
Rotate left

Rotate Right

Shift Lett, Arithmetic

Shift Right, Arithmetic

Shift Right, LogIC

Store Acmltr
Subtract
Subtract Acmltrs.
Subtr.with Carry
Transfer Acmltrs

Test. Zero or Minus

OP

8B
CB

2

2

2

2

INDEX

-

9B
DB

EXTND

DP

-

OP

-

AB
EB

5
5

BB
FB

4
4

IMPLIED

ADCA
ADCB
ANDA
ANDB
BITA
CLR
CLRA
CLRB
CMPA
CMPB
CBA
COM
COMA
COMB
NEG
NEGA
NEGB
DAA
DEC
DECA
DECB
EORA
EORB
INC
INCA
INCB
LDAA
LDAB
DRAA
DRAB
PSHA
PSHB
PULA
PULB
ROL
ROLA
ROLB
ROR
RORA
RORB
ASL
ASLA
ASLB
ASR
ASRA
ASRB
LSR
LSRA
LSRB
STAA
STAB
SUBA
SUBB
SBA
SBCA
SBCB
TAB
TBA
TST
TSTA
TSTB

89
C9
84
C4
85
C5

81
Cl

2

2

2
2
2

2

2

2

2

2

99
09
94
04
25
05

91
01

2
3
3

2

3
3

3
3

A9
E9
A4
E4
A5
E5
6F

5
5

2

2
2
2

5
5
7

2

Al
El
63

60

89
F9
B4
F4
B5
F5
7F

Bl
Fl
7

7

2

2

73

70

OP

-

=

lB

2

1

4

4

4
6

6

3
3
3
3
3
4F

2

1

Sf

2

1

11

2

1

43
53

2
2

1
1

4.0

2

3
3

3

3

50 . 2

6A

88
C8

2
2

2
2

98
08

3
3

2
2

AS
E8
6C

7

5
5
7

2

2
2
2

7A

B8
F8
7C

6

4
4
6

19

2

1

4A
5A

2
2

1
1

3

3
3
3
4C
5C

"2

"3

C6
8A
CA

M

06

2

2
2

2

9A
OA

2

F6

2

BA
FA

69

66

68

5
5

7

7

7

2

2

2

2

79

76

78

97
07
90

4

2

CO

2 DO
2

2

82
C2

2
1

2
2

4

3

6

6

6

36
37
32
33

4
4
4
4

1
1

49
59

2
2

1
1

46
56

2
2

1
1

48
58

2
2

1
1

47
57

2
2

1
1

3

3

2

))

6

3

64

7

2

74

6

3

A7
E7

6
6

5

3

2

EO

92

3

02

3

2
1

A2
E1

5

2
2
2
2

B7
F7
BO
FO

5
5
4
4

3
3
3
3

5
5

2
2

B2
F2

4
4

3
3

7

2

70

• t t
• t t
• I 1

t t R •
t R •
t I R•

A- M -A
B'M -B
A'M
B-M
00 -M
00 -A
00 -B
AM·
B- M
A B
M 'M
'f. -A

B

1
t
•
•

•
•

• •

6

2
2

1
1

R S

t t

t I
I t R S
It R S
I IRS

-B

I t CD~
I I CD~
I lCD~
1
t Gl

00 M-M
00 A-A
OO··B 'B
Converts Binary Add. of BCD Characters
into BCD Format
M - 1 'M
A I-A
B-1 -B

1 4 •

t

4 •

A(f)M'A
B(f)M·B

I 4 •
I R •
I R •

M + 1 -M
A + 1 -A
B+l 'B

l@.
I@.
t@.
!

A -MSp,SP - 1
B 'MSp,SP -1
SP + 1 -SP, MSp
SP + 1 ·SP, MSp

~} L{]

.... ..
···....
.... .

-

'SP
'SP
,A
-B

ITIIIIID=J

.~}c: -~
B

·.C

~}

B

b7

-

bO

aIIJIII)-' 0

C

b7

~

b7

liD

bO

!I~!

!I~!

• • 1 ! IrS' !
• • t tl~ 1

·.I I:~!

• • ! ! I'!!:' !

0

• •

C

o- a I I J I I I )

::~~Ii;

• • ! ! ®!
• • I I IrS' I
• • ! 11i])!
• • ! 11rS' !
I
!

0 -

~} CkID:rn ~}

R •

• • I I R •
I R •
I R •

I

!I~!

• • R !
-

0

• • R
• • R

®

I

t Irs' t

A-·M

• • I

ll®
1
I R •

B -M

•
•
•
•

I 1
! I
I I

b7

M-A
M --B
10

2

1

16

2

1

A -B

17

2

1

bO

C

A» M - C ·A

B > M - C >-B

40

2

1

B -A
M - 00
A 00

50

2

1

B

3

R.

R S R R
R S R R

It

A+ M - A
. B +M"'B

3

7

60

1
1

• 1 !

M 'A

3

61

2 AO

• t t t

A + B >-A
A + M + C -A
B + M + C 'B

M 'B

4

44
54

80

2
2

2"

E6. 2
AA
EA

5 4 3 2 1 0
HINZVC

B +M -B

3

4
4
4
4
4
6

(All register labels
re'er to contents)
A + M -A

3

ABA

BITB
Clear

DIRECT

>

•
•
•
•

!
!
I
I
!
I
!
!
I

!

00

1

I R •

R.

R.
R R
R R
R R

HINZVC
LEGEND:

OP

CONDITION CODE SYMBOLS:

Operation Code (Hexadecimal);
Number of MPU Cycles;

Number of Program Bytes;
Arithmetic Plus;
Arithmetic Minus;
Boolean AND;

MSp Contents of memory location painted to be Stack Pointer;
Boolean Inclusive OR;
G)
Boolean Exclusive OR;
Complement of M;

Transfer Into;
Bit = Zero;
00

Byte =

H',

Half-carry from bit 3;

Interrupt mask
Negative (sign'bit)
Zero (byte)

Overflow, 2'5 complement
Carry.frombit 7
Reset Always
Set Always
Test and set if true, cleared otherwise
Not Affected

CONDITION CODE REGISTER NOTES:
(Bit set if test is true and cleared otherwisel
(Bit VI
(Bit CI
(Bit CI

(Bit VI
(Bit VI
(Bit V)

Zero;

Note - Accumulator addressing mode instructions are included in the column for IMPLIED addressing

MOTOROLA MICROPROCESSOR DATA
3~74

Test: Result = 10000000?
Test: Result = OOOOOOOO?
Test: Decimal value of'most significant BCD
Character greater than nine?
(Not cleared if previously set.)
Test: Operand =10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to result of N(f)C after shift has occurred.

MC6800

PROGRAM CONTROL OPERATIONS
Stack Pointer is automatically incremented by one just prior
to the data transfer so that it will point to the last byte stacked rather than the next empty location. Note that the PULL
instruction does not "remove" the data from memory; in the
example, lA is still in location (m+ 1) following execution of
PULA. A subsequent PUSH instruction would overwrite that
location with the new "pushed" data.
Execution of the Branch to Subroutine (BSR) and Jump to
Subroutine (JSR) instructions cause a return address to be
saved on the stack as shown in Figures 18 through 20. The
stack is decremented after each byte of the return address is
pushed onto the stack. For both of these instructions, the
return address is the memory location following the bytes of
code that correspond to the BSR and JSR instruction. The
code required for BSR or JSR may be either two or three
bytes, depending on whether the JSR is in the indexed !two
bytes) or the extended (three bytes) addressir.g mode.
Before it is stacked, the Program Counter is automatically incremented the correct number of times to be pointing at the
location of the next instruction. The Return from Subroutine
Instruction, RTS, causes the return address to be retrieved
and loaded into the Program Counter as shown in Figure 21.
There are several operations that cause the status of the
MPU to be saved on the stack. The Software Interrupt (SWIl
and Wait for Interrupt (WAil instructions as well as the
maskable (IRQ) and non-maskable (NMIl hardware interrupts all cause the MPU's internal registers (except for the
Stack Pointer itself) to be stacked as shown in Figure 23.
MPU status is restored by the Return from Interrupt, RTI, as
shown in Figure 22.

Program Control operation can be subdivided into two
categories: (1) Index Register/Stack Pointer instructions; (2)
Jump and Branch operations.
Index Register/Stack Pointer Operations
The instructions for direct operation on the MPU's Index
Register and Stack Pointer are summarized in Table 3.
Decrement IDEX, DES), increment (lNX, INS), load (LOX,
LOS), and store (STX, STS) instructions are provided for
both. The Compare instruction, CPX, can be used to compare the Index Register to a 16-bit value and update the Condition Code Register accordingly.
The TSX instruction causes the Index Register to be loaded with the address of the last data byte put onto the
"stack." The TXS instruction loads the Stack Pointer with a
value equal to one less than the current contents of the Index
Register. This causes the next byte to be pulled from the
"stack" to come from the location indicated by the Index
Register. The utility of these two instructions can be clarified
by describing the "stack" concept relative to the M6800
system.
The "stack" can be thought of as a sequential list of data
stored in the MPU's read/write memory. The Stack Pointer
contains a 16-bit memory address that is used to access the
list from one end on a last-in-first-out (LIFO) basis in contrast
to the random access mode used by the MPU's other addressing modes.
The MC6800 instruction set and interrupt structure allow
extensive use of the stack concept for efficient handling of
data movement, subroutines and interrupts. The instructions
can be used to establish one or more "stacks" anywhere in
read/write memory. Stack length is limited only by the
amount of memory that is made available.
Operation of the Stack Pointer with the Push and Pull instructions is illustrated in Figures 15 and 16. The Push instruction (PSHA) causes the contents of the indicated accumulator (A in this example) to be stored in memory at the
location indicated by the Stack Pointer. The Stack Pointer is
automatically decremented by one following the storage
operation and is "pointing" to the next empty stack location.
The Pull instruction (PULA or PULB) causes the last byte
stacked to be loaded into the appropriate accumulator. The

Jump and Branch Operation
The Jump and Branch instructions are summarized in
Table 4. These instructions are used to control the transfer or
operation from one point to another in the control program.
The No Operation instruction,' NOP, while included here,
is a jump operation in a very limited sense. Its only effect is to
increment the Program Counter by one. It is useful during
program development as a "stand-in" for some other instruction that is to be determined during debug. It is also used for equalizing the execution time through alternate paths
in a control program.

TABLE 3 - INDEX REGISTER AND STACK POINTER INSTRUCTIONS
CONO COOE REG
IMMEO
POINTER OPERATIONS
Compare Index Reg
Decrement Index Reg
Decrement Stack Pnt,
Increment Index Reg
Increment Stack Pnt,
load Index Reg
load Stack Pntr
Store Index Reg
Store Stack Pntr
Indx Reg ~ Stack Pntr
Stack Pntr ~ Indx Reg

(j)

®

@)

OIRECT

INDEX

EXTND

MNEMONIC

DP

-

:;

DP

-

::

OP

-

:: OP

-

:: OP

CPX
DEX
DES
INX
INS
lOX
lOS
STX
STS
TXS
TSX

8C

3

3

9C

4

2

AC

6

2

5

3

8C

09
34
08
31
CE
8E

3
3

3
3

DE
SE
OF
SF

4
4
5
5

2
2
2
2

EE
AE
EF
AF

6
6
7
7

2
2
2
2 .

FE
BE
FF
BF

5
5
6
6

5 4 3 2 1 0

IMPLIED

-

::

4
4
4
4

1
1
1
1

BOOLEAN/ARITHMETIC OPERATION

3
3
3
3

M~SPH.IM+II~SPl

35
30

4
4

1
1

(Bit N) Test: Sign bit of most significant (MSI byte of result = 1?
(Bit VI Test: 2's complement o'verflow from subtraction of ms bytes?
(Bit NI Test: Result less than zero? (Bit 15 = 1)

MOTOROLA MICROPROCESSOR DATA
3-75

XH - M. Xl - 1M + 11
X -1 ~X
SP - 1 ~SP
X + 1 ~X
SP + 1 ~SP
M ~ XH. 1M + 11 ~ Xl
XH~M. Xl ~(M+ 11
SPH ~M, SPL ~(M + 11
X-I ~SP
SP + 1 ~ X

H IN Z V C

··.... ...·.
·• .• • • ·.
····..... ...
• • ·. • •
• •  Zero
Branch If Higher
Branch If .;; Zero
Branch If lower Or Same
Branch If < Zero
Branch If Minus
Branch If Not Equal Zero
Branch If Overflow Clear
Branch If Overflow Set
Branch If Plus
Branch To Subroutine
Jump
Jump To Subroutine
No Operation
Return From Interrupt
Return From Subroutine
Software Interrupt
Wait for Interrupt-

G)

®

(All)
(Bit 1)

IMPLIED

# OP

-

#

BRANCH TEST
None
C=O
C='
Z= ,
NGlV=O
Z + (N Gl V) = 0
C+~=O

Z + (N Gl V) =,
C+Z='
·NGlV='
N='
ZoO
V=O
V=l
N=O
3
3
01
3B
39
3F
3E

2
10
5
12
9

,,
,
,
1

}

See Special Operations
Advances Prog. Cntr. Only

}

See Special Operations

5

4

3

2

1

0

H

I

N

Z

V

C

··· •• ··• ··• ·•- ·••
• ·
··• ··• ·••- ··• --- ··••
-- ·
• · • ·
• ·
• · ·
• ··• ·• ··• ·• -- ··•
· -• ·•
• ·
·
• ·
·
· -·
·-• ·-- ·•• ··•• ·-- ··•
·· -- ·· · -- ---CD-·-1-11-1-1-1·
-. . -.
• ® •• - •

Load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously set, a Non-Maskable Interrupt
is required to exit the wait state.

Execution of the Jump Instruction, JMP, and Branch
Always, BRA, affects program flow as shown in Figure 17.
When the MPU encounters the Jump (Indexed) instruction,
it adds the offset to the value in the Index Register and uses
the result as the address of the next instruction to be executed. In the extended addressing mode, the address of the
next instruction to be executed is fetched from the two locations immediately following the JMP instruction. The Branch
Always (BRAHnstruction is similar to the JMP (extended) instruction except that the relative addressing mode applies
and the branch is limited to the range within -125 or· + 127
bytes of the branch instruction itself. The opcode for the
BR.A instruction requires one less byte than JMP (extended)
but takes one more cycle to execute.
The effect on program flow for the Jump to Subroutine
(JSR) and Branch to Subroutine (BSR) is shown in Figures
18 through 20. Note that the Program Counter is properly incremented to be pointing at the correct return address
before it is stacked. Operation of the Branch to Subroutine
and Jump to Subroutine (extended) instruction is similar except for the range. The BSR instruction requires less opcode
than JSR (2 bytes versus 3 bytes) and also executes one cy-

cle faster than JSR. The Return from Subroutine, RTS, is
used as the end of a subroutine to return to the main program as indicated in Figure 21.
The effect of executing the Software Interrupt, SWI, and
the Wait for Interrupt, WAI, and their relationship to the
hardware interrupts is shown in Figure 22. SWI causes the
M PU contents to be stacked and then fetches the starting
address of the interrupt routine from the memory locations
that respond to the addresses FFFA and FFFB. Note that as
in the case of the subroutine instructions, the Program
Counter is incremented to point at the correct return address
before being stacked. The Return from Interrupt instruction,
RTI, (Figure 22) is used at the end of an interrupt routine to
restore control to the main program. The SWI instruction is
useful for inserting break points in the control program, that
is, it can be used to stop operation and put the MPU
registers in memory where they can be examined. The WAI
instruction is used to decrease the time required to service a
hardware interrupt; it stacks the MPU contents and then
waits for the interrupt to occur, effectively removing the
stacking time from a hardware interrupt sequence.

!n+~

FIGURE 17 - PROGRAM FLOW FOR JUMP AND BRANCH INSTRUCTIONS
PC

PC

INDXD

!

n+~

X+ K

EXTND
Next Instruction

n+2

K

Main Program
7E=JMP
KH = Next Address

.

KL = Next Address

Main Program

n
n+1
(n+2)±K

241= BRA
K=Offset*

Next Instruction

Next Instruction
*K=Signed 7-bit value

(al Jump

(bl Branch

MOTOROLA MICROPROCESSOR DATA
3-77

I

MC6800

FIGU.RE18 - PROGRAM FLOW FOR 85R

-----

m-2
m -1

m-1

SP- m
m+ 1

(n

+ 2)H

(n

+ 2)L

m+ 1

7E

7E

7A

~

PC_n

BSR

+1

n

n+2

n+2

Next Main Instr.

+ 2) ±K

1st Subr. Instr.

OK

I

= Signed 7-Bit Value

PC __ (n

±K

(b) After Execution

(a) Before Execution

FIGURE 19 - PROGRAM FLOW FOR J5R(EXTENDED)

FIGURE 20 - PROGRAM FLOW FOR JSRIINDEXED)

m -3
m-2

SP_m-2

m-l

m-l

(n + 31H

m,+ 1

7E

m + 1

7E

m + 2

7A

m + 2

7A

m - 2

sp_m -2

m-l

m -1

J~A

SH -Subr. Addr.

n + 1

SH -'Subr. Addr.

n+2

SL • Subr. Addr.

n+2

SL = Subr. Addr.

n+3

Next Main Instr.

n+3

Next M.in Inltr.

7E

rn.+ 1

7A

n + 1

n + 1

(n + 2)L
7E

m + 1

PC_,n

JSA· BO

(n + 2)H

SP_m

(n'+ 31L

SP-m

pc_n

= Offset

n+1

n+2

7A

JSA: AD
K

= Offset·

Next Main Instr.

• K = a·Bit Unsigned Value

JSA ,= AD
n + 1
n + 2

PC - - . X' + K

K

= Offset

Next Main Instr.

1st Subr. Instr.

• Contents of Index Register

,(el 88fore E"... onion
(al Before Execution
(S formed from
SH and SLI

1-------1

(bl After Execution

MOTOROLA MICROPROCESSOR DATA
3-78

(b), After Execution

MC6800

FIGURE 21

~. PROGRAM

FLOW FOR RTS

'm-2

SP_m-2
(n + 3)H

m -1

m-1

m

SP-

(n + 3)l

7E

m+ 1

7E

m + 1

7A

JSR
n

+1

SH

= BO

JSR

= Subr. Addr.

n+2

Sl = Subr. Addr.

n+3

Next Main Instr.

SH

= BO

= Subr.

Addr.

n+2

Sl = Subr. Addr.

PC_n+3

Next Main Instr.

I

PC_Sn

(b) After Execution

(a) Before Execution

FIGURE 22 - PROGRAM FLOW FOR RTI

SP-.o- m-7

m -7

m -6

CCR

m -6

CCR

m - 5

ACCB

m - 5

ACCB

m -4

ACCA

m-4

ACCA

m-3

XH (Index Reg)

m -3

XH

m -2

Xl (Index Reg)

m-2

Xl

m -1

PC(n+1)H

m -1

PCH

SP ____

PC(n+1)l

PCl

~
n

+1

PC-

n+ 1

PC _ _

(a) Before Execution

(b) After Execution

MOTOROLA MICROPROCESSOR DATA '
3-79

MC6800

FIGURE 23 - PROGRAM FLOW FOR INTERRUPTS
Hardware Interrupt or
Non·Maskable Interrupt (NMIl
Main Program

I

Stack

sp ....

m -7

c::::>

m -6

Condition Code

m - 5

Acmltr. B

m -4

Acmltr. A
Index Register (XH)

m -3
m -2
m -1

Index Register (X L)
PC(n+1)H
PC(n+1)L

SWI

HDWR
INT

NMI

NMI

No

FFFA
FFFB

FFF8
FFF9

Interrupt Memory Assignment 1
FFF8

IRQ

MS

FFF9
FFFA

IRQ
SWI

LS
MS

FFFB

SWI

LS

FFFC

NMI
NMI
Reset
Reset

FFFD
FFFE
FFFF

~

MS~
LS
MS

First Instr.
Addr. Formed
By Fetching
2·Bytes From
Per. Mem.
Assign.

lS

NOTE: MS = Most Significant .Address Byte;
lS = Lllst Significant Address Byte;

MOTOROLA MICROPROCESSOR DATA
3-80

MC6800

for testing relative magnitude when the values being tested
are regarded as unsigned binary numbers, that is, the values
are in the range 00 (lowest) to FF (highest). BCC following a
comparison (CMP) will cause a branch if the (unsigned)
value in the accumulator is higher than or the same as the
value of the operand. Conversely, BCS will cause a branch if
the accumulator value is lower than the operand.
The fifth complementary pair, Branch On Higher (BHIl and
Branch On Lower or Same (BLS) are, in a sense, complements to BCC and BCS. BHI tests for both C and Z = 0; if
used following a CM P, it will cause a branch if the value in
the accumulator is higher than the operand. Conversely,
BLS will cause a branch if the unsigned binary value in the
accumulator is lower than or the same as the operand.
The remaining two pairs are useful in testing results of
operations in which the values are regarded as signed two's
complement numbers. This differs from the unsigned binary
case in the fOllowing sense: in unsigned, the orientation is
higher or lower; in signed two's complement, the comparison is between larger or smaller where the range of
values is between -128 and + 127.
Branch On Less Than Zero (BLT) and Branch On Greater
Than Or Equal Zero (BG E) test the status bits for N ED V = 1
and N ED V = 0, respectively. B LT will always cause a branch
following an operation in which two negative numbers were
added. In addition, it will cause a branch following a CMP in
which the value in the accumulator was negative and the
operand was positive. BL T will never cause a branch following a CM P in which the accumulator value was positive and
the operand negative. BGE, the complement to BLT, will
cause·a branch following operations in which two positive
values were added or in which the result was zero.
The last pair, Branch On Less Than Or Equal Zero (BLE)
and Branch On Greater Than Zero (BGT) test the status bits
for ZED (N + V) = 1 and ZED (N + V) =0, respectively. The action of BLE is identical to that for BLT except that a branch
will also occur if the result of the previous result was zero.
Conversely, BGT is similar to BGE except that no branch will
occur following a zero result.

FIGURE 24 - CONDITIONAL BRANCH INSTRUCTIONS
BMI

N=1

BEQ

Z=1

BPl :

N =<1>

BNE

Z=

BVC:

v =<1>

Bce

C=

BVS

V= 1

BCS

C=1

BHI

C+Z=q,

BlT

NEDV=1

BlS

C+Z=1

BGE

NEDV=q,

BlE

Z+(NEDV)=1

BGT

Z+ (NEIlV) =

q,

The conditional branch instructions, Figure 24, consists of
seven pairs of complementary instructions. They are used to
test the results of the preceding operation and either continue with the next instruction in sequence (test fails) or
cause a branch to another point in the program (test succeeds).
Four of the pairs are used for simple tests of status bits N,
Z, V, and C:
1. Branch on Minus (BMIl and Branch On Plus (BPl) tests
the sign bit, N, to determine if the previous result was
negative or positive, respectively.
2. Branch On Equal (BEQ) and Branch On Not Equal
(BNE) are used to test the zero status bit, Z, to determine
whether or not the result of the previous operation was equal
to zero. These two instructions are useful following a Compare (CMP) instruction to test for equality between an accumulator and the operand. They are also used following the
Bit Test (BIT) to determine whether or not the same bit positions are set in an accumulator and the operand.
3. Branch On Overflow Clear (BVC) and Branch On
Overflow Set (8VS) tests the state of the V bit to determine
if the previous operation caused an arithmetic overflow.
4. Branch On Carry Clear (BCC) and Branch On Carry Set
(BCS) tests the state of the C bit to determine if the previous
operation caused a carry to occur. BCC and BCS are useful

CONDITION CODE REGISTER
OPERATIONS
to precede tiny SEI instruction with an odd opcode - such
as NOP. These precautions are not necessary for MC6800
processors indicating manufacture in November 1977 or
later.
Systems which require an interrupt window to be opened
under program control should use a CU-NOP-SEI sequence
rather than CL\-S EI.

The Condition Code Register (CCR) is a 6-bit register
within the MPU that is useful in controlling program flow
during system operation. The bits are defined in Figure 25.
The instructions shown in Table 5 are available to the user
for direct manipulation of the CCR.
A CU-WAI instruction sequence operated properly, with
early MC6800 processors, only if the preceding instruction
was odd (Least Significant Bit = 11. Similarly it was advisable

MOTOROLA MICROPROCESSOR DATA
3-81

II

MC6800'

FIGURE 25 -

CONDITION CODE REGISTER BIT DEFINITION

H = Half-carry; set whenever a carry from b3 to b4 of the result is generated
by ADD, ABA, ADC; cleared if no b3 to b4 carry; not affected by other
instructions.
Interrupt Mask; set by hardware or software interrupt or SEI instruction;
cleared by CLI instruction. (Normally not used in arithmetic operations.)
Restored to a zero as a result of an RTl instruction if 1m stored on the
stacked is low.
N = Negative; set if high order bit (b7) of result is set; cleared otherwise.
Z

II

=

Zero; set if result

= 0; cleared otherwise.

v = Overlow; set if there was arithmetic overflow asa result of the operation;
cleared otherwise.

"

C = Carry; set if there was a carry from the most significant bit (b7) of the
result; cleared otherwise.

TABLE 5- CONDITION CODE REGISTER INSTRUCTIONS
CONO. CODE REG.
IMPLIED
OPERATIONS
Clear Carr~
Clear Interrupt Mask
Clear Overflow
Set Carry
Set Interrupt Mask
Set Overflow
Acmltr A - CCR
CCR - Acmltr A

MNEMONIC
CLC'
CLI
CLV
SEC
SEI
SEV
TAP
TPA

OP

-

:: BOOLEAN OPERATION

OC 2
OE 2
OA ,2
00 2

1
1
1
1

OF
OB
06
07

1
1
1
1

2
2
2
2

O-C
0-1
O-V
l-C
1-1

5

4

3

2

1

0

H

I

N

Z

V

C

•••••
•
R •
•
•
•••• R

R
•
•

I-V
A-GGR
GGR -A

R = Reset
S = Set
• = Not affected

G)

(ALL) Set according to the contents of Accumulator A.

ADDRESSING MODES
into appropriate opcode then depends on the method
used. If manual translation is used, the addressing mode
is inherent in the opcode. For example, the immediate,
direct, indexed, and extended modes may all be used
with the ADD instruction. The proper mode is determined
by selecting (hexadecimal notation) 8B, 9B, AB, or BB,
respectively.
The source statement format includes adequate information for the selection if an assembler program is used
to generate the opcode. For instance, the immediate mode
is selected by the assembler whenever it encounters the
"#" symbol in the operand field. Similarly, an "X" in the
operand field causes the indexed mode to be selected.
Only the relative mode applies to the branch instructions;
therefore, the mnemonic instruction itself is enough for
the assemble to determine addressing mode.

The MPU operates on 8-bit binary numbers presented
to it via the data bus. A given number (byte) may represent either data or an instruction to be executed, depending on where it is encountered in the control program.
The M6800 has 72 unique instructions; however, it recognizes and takes action on 197 of the 256 possibilities
that can occur using an 8-bit word length. This larger
number of instructions results from the fact that many of
the executive instructions have more than one addressing mode.
These addressing modes refer to the manner in which
the program causes the MPU to obtain its instructions
and data. The programmer must have a method for addressing the MPU's internal registers and all of the external memory locations.
Selection of the desired addressing mode is made by
the user as the source statements are written. Translation

MOTOROLA MICROPROCESSOR DATA
3~82

MC6800

For the instructions· that use both Direct and Extended
modes, the Assembler selects the Direct mode if the operand
value is in the range 0-255 and Extended otherwise. There
are a number of instructions for which the Extended mode is
valid but the Direct is not. For these instructions, the
Assembler automatically selects the Extended mode even if
the operand is in the 0-255 range. The addressing modes are
summarized in Figure 26.

"operands" but the space between them and the operator
may be omitted. This is commonly done, resulting in apparent four character mnemonics for those instructions.
The addition instruction, ADD, provides an example of
dual addressing in the operand field:
Operator Operand

Comment

ADDA

MEM12 ADD CONTENTS OF MEM12 TO ACCA

ADDS

MEM12 ADD CONTENTS OF MEM12 TO ACCS

or
Inherent (Includes" Accumulator Addressing" Mode)
The. successive fields in a statement are normally
separated by one or more spaces. An exception to this rule
occurs for instructions that use dual addressing in the
operand field and for instructions that must distinguish between the two accumulators. In these cases, A and Bare

The example used earlier for the test instruction, TST, also
applies to the accumulators and uses the "accumulator addreSSing mode" to designate which of the two accumulators
is being tested:

FIGURE 26 - ADDRESSING MODE SUMMARY

Direct:

00

Example: SUBB Z
Addr. Range = 0-255

In

n

+1

Instruction

n + 2

Instruction

Immediate:
Example: LOAA #K
(K = One-Byte Oprnd)

Z = Oprnd Address
Next Instr.

n + 1

K = Operand

n +·2

Next Inst.

•
1~

•
•

___

(K = One-Byte Oprnd)

Z

(K = Two-Byte Oprnd)

Z

KH = Operand

Z + 1

KL = Operand

K__
=_o_p_er_a_nd
____

Instruction

~

OR

n + 1

KH = Operand

n + 2

KL = Operand

n+3

Next Instr.

n + 1

±K = Brnch Offset

Relative:

In

If Z
If Z

~ 255, Assembler SelectDirect Mode

Example: BNE

> 255, Extended Mode is selected

Instruction
K

(K = Signed 7:BitValue)

n + 2

Next Instr.

Extended:

Addr. Range:

In 256-65535

FO

Instruction

+1

ZH = Oprnd Address

n + 2

ZL = Oprnd Address

n + 3

Next Instr.

n

(n + 2) ± K

&

Z

~1

•
____K__
=_o_p_e_ra_n_d____

&

~

Instructio.n

Example: AOOA Z, X

n

+1

Z

Addr. Range:
0-255 Relative to
Index Register. X

n

+2

Next Instr.

Z

KH = Operand

Z+1

KL = Operand

= Offset

•

•
•

OR
(K = Two-Byte Oprnd)

___N_e_x_t_In_s_tr_._&_3
____

If Brnch Tst True.

Indexed:

•
•
(K = One-Byte Oprnd)

If Brnch Tst False,

~1

&

•
•
•

Addr. Range:
-125 to +129
Relative to n.

Example: CMPA Z

II

OR
(K = Two-Byte Oprnd)
(CPX. LOX, and LOS)

(Z = B-Bit Unsigned
Value)

MOTOROLA MICROPROCESSOR DATA

3-83

X+Z

K = Operand

~

MC6800

Comment

Operator
TST8

TEST CONTENTS OF ACC8

TSTA

TEST CONTENTS OF ACCA

mode, the "address" of the operand· is effeCtively the
memory location immediately following the instruction itself.
Table 7 shows the cycle-by-cycle operation for the immediate addressing mode.

or

Direct and Extended Addressing Modes - In the Direct
and Extended modes of addressing, the operand field of the
source statement is the address of the value that is to be
operated on. The Direct and Extended modes differ only in
the range of memory locations to which they can direct the
MPU. Direct addressing generates a single 8-bit operand
and, hence, can address only memory locations 0 through
255; a two byte operand is generated for Extended addressing, enabling the MPU to reach the remaining memory locations, 256 through 65535. An example of Direct addressing
and its effect on program flow is illustrated in Figure 30.
The MPU, after encountering the opcode for the instruction LDAA (Direct) at memory location 5004 (Program
Counter = 5004), looks in the next location, 5005, for the address of the operand. It then sets the program counter equal
to the value found there (100 in the example) and fetches the
operand, in this case a value to be loaded into accumulator
A, from that location. For instructions requiring a two-byte
operand such as LDX (Load the Index Register), the operand
bytes would be retrieved from locations 100 and 101. Table 8
shows the cycle-by-cycle operation for the direct mode of
addressing.
Extended addressing, Figure 31, is similar except that a
two-byte address is obtained from locations fJJJ7 and fJJJ8
after the LDAB (Extended) opcode shows up in location
5006. Extended addressing can be thought of as the "standard" addressing mode, that is, it is a method of reaching
any place in memory. Direct addressing, since only one address byte is required, provides a faster method of processing data.and generates fewer bytes of control code. In most
applications, the direct addressing range, memory locations
0-255, are reserved for RAM. They are used for data buffering and temporary storage of system variables, the area in
which faster addressing is of most value. Cycle-by-cycle
operation is shown in Table 9 for Extended Addressing.

A number of the instructions either alone or together with
an accumulator operand contain all of the address information that is required, that is, "inherent" in the instruction
itself. For instance, the instruction ABA causes the MPU to
add the contents of accmulators A and B together and place
the result in accumulator A. The instruction INCB, another
example of "accumulator addressing," causes the contents
of accumulator B to be increased by one. Similarly, INX, increment the Index Register, causes the contents of the Index
Register to be increased by one.
Program flow for instructions of this type is illustrated in
Figures 27 and 28. In these figures, the general case is shown
on the left and a specific example is shown on the right.
Numerical examples are in decimal notation. Instructions of
this type require only one byte of opcode. Cycle-by-cycle
operation of the inherent mode is shown in Table 6.

II

Immediate Addressing Mode - In the Immediate addressing mode, the operand is the value that is to be operated on.
For instance, the instruction
Operator
LDAA

Operand
125

Comment
LOAD 25 INTO ACCA

causes the MPU to "immediately load accumulator A with
the value 25"; no further address reference is required. The
Immediate mode is selected by preceding the operand value
with the"#" symbol. Program flow for this addressing mode
is illustrated in Figure 29.
The operand format allows either properly defined symbols or numerical values. Except for the instructions CPX,
LDX, and LDS, the operand may be any value in the range 0
to 255. Since Compare Index Register (CPX), Load Index
Register (LDX), and Load Stack Pointer (LDS), require 16-bit
values, the immediate mode for these three instructions require two-byte operands. In the Immediate addressing

FIGURE 28 -

FIGURE Xl - INHERENT ADDRESSING
MPU

MPU

RAM

RAM

PC '---_ _...J ....

PC

= 5000

ACCUMULATOR ADDRESSING

MPU

MPU

RAM

' -_ _........
PC

GENERAL FLOW
GENERAL FLOW

EXAMPLE

MOTOROLA MICROPROCESSOR DATA
3-84

= 5001 I--.;c.;.:..';;"-'-I"

EXAMPLE

MC6800
the unconditional jump (JMP), jump to subroutine (JSR),
and return from subroutine (RTS) are used.
In Figure 32, when the MPU encounters the opcode for
BEQ (Branch if result of last instruction was zero), it tests the
Zero bit in the Condition Code Register. If that bit is "0," indicating a non-zero reSUlt, the MPU continues execution
with the next instruction (in location 5010 in Figure 32). If the
previous result was zero, the branch condition is satisfied
and the M PU adds the offset, 15 in this case, to PC + 2 and
branches to location 5025 for the next instruction.
The branch instructions allow the programmer to efficiently direct the MPU to one point or another in the control program depending on the outcome of test results. Since the
control program is normally in read-only memory and cannot
be changed, the relative address used in execution of branch
instructions is a constant numerical value. Cycle-by-cycle
operation is shown in Table 10 for relative addressing.

Relative Add..... Mode - In both the Direct and Extended
modes, the address obtained by the MPU is an absolute
numerical address. The Relative addressing mode, implemented for the MPU's branch instructions, specifies a
memory location relative to the Program Counter's current
location. Branch instructions generate two bytes of machine
code, one for the instruction opcode and one for the
"relative" address (see Figure 321. Since it is desirable to be
able to branch in either direction, the B-bit address byte is interpreted as a signed 7-bit value; the 8th bit of the operand is
treated as a sign bit, "0" = plus and "1" = minus. The remaining seven bits represent· the numerical value. This
results in a relative addressing range of ± 127 with respect to
the location of the branch instruction itself. However, the
branch range is computed with respect to the next instruction that would be executed if the branch conditions are not
satisfied. Since two bytes are generated, the next instruction
is located at PC + 2. If D is defined as the address of the
branch destination, the range is then:
(PC+2)-127sDs(PC+2) + 127
or
PC-125sDsPC+ 129
that .is, the destination of the branch instruction must be
within -125 to + 129 memory locations of the branch instruction itself. For transferring control beyond this range,

Indexed Addressing Mode - With Indexed addressing,
the numerical address is variable and depends on the current
contents of the Index Register. A source statement such as
Operator
STAA

Operand
X

causes the MPU to store the contents of iilccumulator A in

Address Mode
and InstruCtions
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DES
DEX
INS
INX

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

Comment
PUT A IN INDEXED LOCATION

Data Bus

2

4

PSH
4

PUL
4

TSX
4

TXS
4

RTS
5

1
2

1
1

Op Code Address
Op Code Address + 1

1
1

OpCode
Op Code of Next Instruction

1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1

1
1
0
0
1
1
1

Op Code Address
Op Code Address + 1
Previous Register Contents
New Register Contents
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer - 1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Op Code Address
Op Code Address + 1
Stack Pointer
New Index Register
Op Code Address
Op Code Address + 1
Index Register
New Stack Pointer

1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1

OpCode
Op Code of Next Instruction
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
OpCode
Op Code of Next Instruction
Accumulator Data
Accumulator Data
OpCode
Op Code of Next Instruction
Irrelevant Data (Note 11

2
3
4

1
0
1

Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1

1
1
1
1

OpCode
Irrelevant Data (Note 2)
Irrelevant Data (Note 1)
Address of Next Instruction (High
Order Byte)

5

1

Stack Pointer + 2

1

Address of Next Instruction (Low
Order Byte)

0
1

1
0
1
1
1
0
0
1
1
0
0
1

MOTOROLA MICROPROCESSOR DATA
3-85

Operand Data from Stack
OpCode
Op Code of Next Instruction
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
OpCode
Op Code of Next Instruction
Irrelevant Data
Irrelevant Data

II

MC6800
TABLE 8 - INHERENT MODE CYCLE-BY-CYCLE OPERATION (CONTINUED)
Addre•. MOde
.and Instructions

Cycles

WAI

9

Cycle VMA
Line
#

10

I

SWI

Op Code Address

1

OpCode

Op Code Address + 1

1

OpCode of Next Instruction

Stack Pointer
Stack Pointer - 1
Stack, PQinter - 2

0
0
0

Return Address (Low Order Byte)
Return Address (High Order Byte)

Slack Pointer - 3

0
0

3

1
1

4

1

5

1
1
1

Ind~x Register (Low Ord~r Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Op Code
Irrelevant Data '(Note 2)
Irrelevant Data (Note 1)
Cont~nts of Condo Code Register from
Stack
Contents of Accumulator B from Stack
Contents of A.ccumulator A from Stack
Index Register from Stack (High Order
Byte)
,

8
9
1
2
3
4

0
1

Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6 (Note 3)
Op Code Address
Op Code.Address + 1
Stack Pointer
Stack Pointer + 1

5
6
7

1
1
1

Stack Pointer + 2
Stack Pointer + 3
Stack Pointer + 4

1

8

1

Stack Pointer + 5

1

Index Register from Stack (Low Order
Byte)

9

1

Stack Pointer + 6

1

Next Instruction Address from Stack
(High .Order Byte)

10

1

Stack Pointer t 7

1. Next Instruction Address from Stack
(Low Order Byte)

1

1
1

Op Code Address

Stack Pointer - 1
Stack Pointer - 2
Stack Painter - 3

1 .Op Code
1 Irrelevant Data (Note 1 )
0 Return Address .(Low Order Byte)
0 Return Address (High Order Byte)
0 Index Register (Low Order Byte)
Index Register (High Order Byte)
0

Stack Pointer - 4

0

Contents of Accumulator A

0

1

Stack Pointer - 5
Stack Pointer - 6

Contents of Accumulator B
Contents of Condo Code Register

.11

0
1

Stack Pointer- 7
Vector Address FFFA (Hex)

0
1
1

12

1

Vector Address FFFB (Hex)

1

5
6
7

8
9
10

Note 1.

Dete Bus

1

3
4

Note 2.
Note 3.

Line

1

2

12

RtW

2

6
7

RTf

Address Bus

1
1
1
1

1
1
1
1
1
1

0
1
1
1
1
1

1

1

Op Code Address + 1
Stack Pointer

Irrelevant Data (Note 1)
Address of Subroutine (High Order
Byte)
Address of Subroutine (Low Order
Byte)

If device which 'isaddressed during this cycle uses VMA. then the Data Bus will go to the high impedance three-state condition.
Depending on bus capacitance. data from the previous cycle may be retained on the Data Bus.
Data is ignored by the MPU.
'
While the MPU is waiting for the interrupt. Bus Available will go high indicating the following states of the control lines: VMA is
low; Address Bus. RIW. and Data Bus are all in the high impedance,state.

location 5006, it looks in' the next memory location for the
value to be'added to X (5 in the example) and calculates the
required address by adding 5 to the present Index Register
value of 400. In the operand format, the offset may be
represented by a label or a numerical value in the range 0-255
as in 1t"leexample. In the earlier example, STAA X, the
operand is equivalent to 0, X, that is, the 0 may be omitted
when the, desired address is equal to X. Table 11 shows .the
, cycle-by~cycle operation for the Indexed Mode of Addressing.

the memory location specified by the contents of the Index
Register (recall that the label "X" is reserved to designate the
Index Register). Since there are instructions for manipulating
X during program execution (LOX, INX. DEC, .etc.) , the Indexed addreSSing mode provides a dynamic" on the fly" way
to modify program activity.
The operand field can i:\lso contain a numerical value that
will be automatically added to X during execution~ This format is illustrated, in Figure 33.
When the MPU encounters the LDAB (lndex~) opcode in

MOTOROLA MICROPROCESSOR DATA
3-86

MC6800

FIGURE 30 - DIRECT ADDRESSING MODE

FIGURE 29 - IMMEDIATE ADDRESSING MODE

MPU

MPU

MPU

MPU

ADDR = 100 .....______

ADDR 1-..:;,;.;:.;.;.;._.......

PC = 50021-~;";';"~.J'

PC

PC = 5004

I-";';";';;';';';'-L...

I-';';;';"";';----l

...

5005 . . ._~-r

PC+11-~;;;';';'_"""'"
ADDR = O~255

EXAMPLE

GENERAL flOW

~,

EXAMPLE

GENERAL FLOW

II

TABLE 7 - IMMEDIATE MODE CYCLE-BY-CYCLE OPERATION

R/W

Address Mode
and Instructions
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

CPX
LOS
LOX

AddrBII BUI
1

2

2

3

1
2
3

Line

Data BUI

1
1

Op Code Address

1

OpCode

Op Code Address + 1

1

Operand Data

1

Op Code Address

1
1

Op Code Address + 1
Op Code Address + 2

1
1

Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

1

TABLE 8 - DIRECT MODE CYCLE-BY-CYCLE OPERATION

RiW

Address Mode
and Instructions
ADC
ADD
AND
BIT
CMP
CPX
LOS
LOX

EOR
LOA
ORA
SBC
SUB

AddrBII BUI

3

4

1

1

Op Code Address

2
3

1
1

Op Code Address + 1
Address of Operand

1
2
3

1
1
1
1
1
1
0
1
1

Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1

4

STA
4

1
2
3
4

1

STS
STX

5

Op Code Address
Op Code Address + 1
Destination Address
Destination Address

Line
1
1
1

Op Code

1
1

Op Code

Address of Operand
Operand Data

1
1
1

Operand Data (Low Order Byte)
Op Code

1
1
0
1
1

Destination Address
Irrelavant Data (Note 1)
Data from Accumulator
OpCode

1

Op Code Address
Qp Code Address + 1
Address of Operand
Address of Operand

1

Ad,dress of Operand
Irrelevant Data (Note 1)

4

0
1

0

Register Data (High Order Byte)

5

1

Address of Operand + 1

0

Register Data (Low Order Byte)

2
3

.

Address of Operand
Operand Data (High Order Byte)

Note 1. If device which is address during.this cycle uses VMA, then the Data Bus will go to the high impedance three·state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.

MOTOROLA MICROPROCESSOR DATA
3-87

MC6800

FIGURE 31 - EXTENDED ADDRESSING MODE
MPU

ADDR

ADDR

......

I--;;.;.;.;~-r

=

3001-____-11""0.

PC = 5006
PC

I---";;"'~

1--...;;..;;..;.;-......

ADDR ;, 256

GENERAL FLOW

I

EXAMPLE

TABLE 9 - EXTENDED MODE CYCLE-BY-CYCLE
Address Mode
and Instructions

Cycle
Cycles

STS
STX

6

9

~

JMP

3
EOR
LOA
ORA

sac

4

SUB

CPX
LOS
LOX

5

STAA
STA B

5

ASL
ASR
CLR
COM
DEC
INC

LSR
NEG
ROL
ROR
TST

6

VMA
Line

Address Bus

R/W
Line

Data Bus

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

1

Address of Operand (Low Order Byte)

4

0
1

OP Code Address + 2
Address of Operand

5
6
1

JSR

ADC
ADD
AND
BIT
CMP

#

Address of Operand

1

Irrelevant Data (Note 1)
Operand Data (High Order Byte)

1

Address of Operand + 1

1

Op Code Address

0
0
1

2

1

Op Code Address + 1

1

Address of Subroutine (High Order Byte)

3

1

Op Code Address + 2

1

Address of Subroutine (Low Order Byte)

4

1

Subroutine Starting Address

1

Op Code of Next Instruction

5

1

Stack Pointer

0

Return Address (Low Order Byte)

6

1

Stack Pointer - 1

a

Return Address (High Order Byte)

7

0

Stack Pointer - 2

1

Irrelevant Data (Note 1 )

a

Op Code Address + 2

1

Irrelevant Data (Note 1)

9

0
1

Op Code Address + 2

1

Address of Subroutine (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Jump Address (High Order Byte)

3

1

Op Code

1

1

Op Code Address

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

Addr~ss

+2

Operand Data (Low Order Byte)
Op Code

1

Jump Address (Low Order Byte)

1

Op Code

4

1

Address of Operand

1

Operand Data

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

1

Address of Operand

1

Operand Data (High Order Byte)

5
1

1

Address of Operand + 1

1

Operand Data (Low Order Byte)

1

Op Code Address

1

Op Code
Destination Address (High Order Byte)

2

1

Op Code Address + 1

1

3

1

Op Code Address + 2

1

Destination Address (Low Order Byte)

4

a

Operand Destination Address

1

Irrelevant Data (Note 1)

5
1

1

Operand Destination Address
Op Code Address

0
1

Op Code

2

1
1,

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

1

Address of Operand

1

Current Operand Data

0

Address of Operand

1

Irrelevant Data (Nole 1 )

1/0
(Note
2)

Address of Operand

0

New Operand Dilta (Note 2)

5
6

Data from Accumulator

Note 1. If deVice which IS addressed dunng thiS cycle uses VMA, then the Data Bus Will go to the high Impedance three·state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
Note 2. For TST, VMA = 0 and Operand data does not change.

MOTOROLA· MICROPROCESSOR DATA

3-88

MC6800

FIGURE 32 - RELATIVE ADDRESSING MODE
MPU

Program
Memorv
PC

t-----I
PC

(PC

+ 2)~;...,;.;.~=~
PC

II

PC

FIGURE 33 - INDEXED ADDRESSING MODE
MPU

ADDR = INDX
+ OFFSET

PC

1 - - - - -.........
1--......;.;.;.;.-1 .......

ADDR = 405 ........:;;;.._,.....

PC = 5006

......___-f ..;'

~

~---t.,.

EXAMPLE

TABLE 10 -

RELATIVE MODE CYCLE-BY-CYCLE OPERATION

Address Mode
and Instructions

BCC
BCS
BEQ
BGE
BGT

BHI
BlE
BlS
BlT
BMI

BNE
BPl
BRA
BVC
BVS

Address Bus

4

BSR

8

Note 1.

1

1

2

1

3
4

0
0

1

Op Code Address
Op Code Address + 1

1

Op Code Address + 2
Branch Address
Op Code Address

2

1

Op Code Address + 1

3
4

0
1

Return Address of Main Program

5
6

1
0

7

0

Stack Pointer - 1
Stack Pointer - 2
Return Address of Main Program

8

0

Subroutine Address

Stack Pointer

RiW

Line
1
1
1
1
1
1
1
0
0
1
1
1

Data Bus
Op Code
Branch Offset
Irrelevant Data (Note 1 )
Irrelevant Data (Note 1)
OpCode
Branch Offset
Irrelevant Data (Note 1)
Return Address (low Order Byte)
Return Address (High Order Byte)
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
Irrelevant Data (Note 1)

If device which IS addressed dUring this cycle uses VMA, then the Data Bus Will go to the high Impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.

MOTOROLA MICROPROCESSOR DATA
3-89

MC6800

TABLE l1-INDEXED MODE CYCLE-BY-CYCLE
Addre. Mode
end Instructionl

Addr_Bul

R
Line

Dete

BUI

INDEXED
JMP
4

ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

1

1

Op Code Address

1

Op Code

2

1

Op Code 'Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1 )

4

0
1

Index Register Plus Offset (w/o Carry)

1

rrrelevant Data (Note 1 )

Op Code Address

Op Code

2

1

Op Code Address + 1

3

0
0
1

Index !'Iegister
Index Register Plus Offset (w/o Carry)

1
1
1
1
1

1

5

4

5
1

CPX
LOS
LOX

6

II

6

LSR
NEG
ROL
ROR
TST

1

OpCode Address

1

Op Code Address + 1

1

3

Index R~ister
Index Register Plus Offset (wio Carry)

1
1

Irrelevant Data (Note 1)

5
6

0
0
1
1

Index Register Plus Offset
Index Register Plus Offset + 1

1

Operand Data (High Order Byte)
Operand Data (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

3

Index Register
Index Register Plus Offset (w/o Carry)

1

Offset
Irrelevant Data (Note 1)

2

0
0
0
1
1
1

3

0

4

0

5
6
7

1

5
6
1

7

STS
STX
7

Irrelevant Data (Note 1)

1

Irrelevant Data (Note 1)

0

Operand Data

1

Op Code

Op Code Address + 1

1

Index Register
Index Register Plus Offset (w/o Carry)

1

Offset
Irrelevant Data (Note 1)

1

Irrelevant Data (Note 1)

Index Register Plus Offset
Index Register Plus Offset

1
1

Current Operand Data
Irrelevant Data (Note 1)

Index Register Plus Offset

0

New Operand Data (Note 2)

Op Code Address

Op Code Address

1

Op Code

1

Op Code Address + 1

1

3

0
0
0

Index Register
Index Register Plus Offset (w/o Carry)

1
1

Offset
Irrelevant Data (Note 1 )
Irrelevant Data (Note 1 )

Index Register Plus Offset

1

1

Index Register Plus Offset

0

3
4
5
6
7

8

Note 2.

1

Index Register Plus Offset
Index Register Plus Offset

1

5

Note 1..

1

1

6
7
1
2'

B

0
110
(Note
2)

Offset
Irrelevant Data (Note 1)

2
4

JSR

Irrelevant Data (Note 1)
Operand Data
Op Code

1

4

ASL
ASR
CLR
COM
DEC
INC

Irrelevant Data (Note 1 )

2
4

STA

Index Register Plus Offset

Offset

Irrelevant Data (Note 1)
Operand Data (High Order Byte)

1

Index Register Plus Offset + 1

0

Operand Data (Low Order Byte)

1

Op Code Address

1

Op Code

1
0
1
1

Op Code Address +1
Index Register

1
1

Offset
,Irrelevant Data (Note 1 )

Stack Pointer

0

Return Address (Low Order Byte)

Stack Pointer - 1

0

Return Address (High Order Byte)

0

Stack Pointer - 2

1

Irrelevant Data (Note 1)

0
0

Index Register
Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

1

Irrelevant Data (Note 1)

If device which is addressed during this cycle usesVMA, then the Data Buswill go to the high impedance three-state ,condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
For TST, VMA = 0 and Operand data does not change.

MOTOROLA MICROPROCESSOR DATA
3-90

MC6800

ORDERING INFORMATION

Pack~ge

Frequency (MHz)

Temperature

Cerdip
S Suffix

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
- 40°C to 85°C
O°C to 70°C
- 40°C to 85°C
O°C to 70°C'

MC6800S
MC6800CS
MC68AOOS
MC68AOOCS
MC68BOOS

Plastic
P Suffix

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
- 40°C to 85°C
O°C to 70°C
- 40°C to 85°C
O°C to 70°C

MC6800P
MC6800CP
MC68AOOP
MC68AOOCP
MC68BOOP

Type

Order Number

II

PIN ASSIGNMENT

RESET

VSS
HALT

2

cl>1

3

IRQ

4

39

TSC

31

cl>2

N.C.

DBE
N.C.
BA

7

34

R/W

Vce

8

33

DO

AD

9

32

Dl

31

D2

30

D3

Al

A3

29

D4

A4

28

D5

A5

27

D6

A6

26

D7
A15

A7
24

A14

Al0

22

A12

All

21

VSS

AS

A13

A9

MOTOROLA MICROPROCESSOR DATA
3-91

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC6801
MC6803

Microcontroller/Microprocessor (MCU/MPU)
The MC6801 is an 8-bit single-chip microcontroller unit (MCU) which significantly enhances the
capabilities of the M6800 Family of. parts. It includes an upgraded M6800 microprocessor unit
(MPU) with upward-source and object-code compatibility. Execution times of key instructions have
been improved and several new instructions have been added including an unsigned multiply. The
MCU can function as a monolithic microcontroller or can be expanded to a 64K byte address space.
Itis TTL compatible and requires one + 5-volt power supply. On-chip resources include 2048 bytes
of ROM, 128 bytes of RAM, a serial communications interface (SCI), parallel 1/0, and a three-function programmable timer. The MC6803 can be considered as an MC6801 operating in modes 2 or 3.
An EPROM version of the MC6801, the MC68701 microcontroller, is available for systems development. The MC68701 is pin and code compatible with the MC6801/MC6803 and can be used to emulate the MC6801/MC6803. The MC68701 is described in a separate Advanced Information
publication.

II

•
•
•
•
•
•
•
•

Enhanced MC6800 Instruction Set
8 x 8 Multiply Instruction
Serial Communications Interface (SCI)
Upward Source and Object Code Compatibility with the M6800
16-Bit Three-Function Programmable Timer
Single-Chip or Expanded Operation to 64K Byte Address Space
Bus Compatibility with the M6800 Family
2048 Bytes of ROM (MC6801 Only)

•
•
•
•
•

128 Bytes of RAM
64 Bytes of RAM Retainable During Powerdown
29 Parallel 110 and Two Handshake Control Lines
Internal Clock Generator with Divide-by-Four. Output
- 40 to 85°C Temperature Range

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-92

MC6801/6803

FIGURE 1 -

I

I Ii

P37
P36
P35
P34
P33
P32
P3l
P30
SC2
SCl

A7/07
A6/06
A5/05
A4/04
A3/03
A2/02
Al/0l
AOIDO
R/W
AS

07
06
05
04
03
02
01
00
R/W

iOS

0S3
iS3

P47
P46
P45
P44
P43
P42
P4l
P40

A15
A14
A13
A12
A1l
Al0
A9
A8

A7
A6
A5
A4
A3
A2
Al
AO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

M6801 MICROCOMPUTER FAMILY BLOCK DIAGRAM

Expanded Multiplexed
Expanded Non-Multiplexed
Single Chip

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

P20
P2l
P22
P23
P24

II

PlO
Pll
P12
P13
P14
P15
P16
P17

NOTE: No functioning ROM in MC6803.

POWER CONSIDERATIONS
The average chip-junction temperature, TJ' in °C can be obtained from:
TJ=TA + (PD· 8JA)
where:
TA
8JA
PD
PINT
PPORT

=
=
=
=
=

(1)

Ambient Temperature, °C
Package Thermal Resistance, Junction-to-Ambient, °C/W
PINT+ PPORT
ICC x VCC' Watts- Chip Internal Power
Port Power Dissipation, Watts - User Determined

For most applications PPORT--------------------------------~
See Note 4

lOS,
R/W. Address
INon-Muxed)

Note 3
Addr I Data ---+--c',,--:!i.'
Muxed

Read Data Muxed
~-----(19~----~

Write Data Muxed

Addr/Data
Muxed

Address
Strobe lAS;

---------"1

NOTES:
1. Voltage levels shown are VLSO.5 V, VH~2.4 V, unless otherwise specified.
2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified.
3. Usable access time is computed by: 12+3-17+4.
4. Memory devices should be enabled only during E high to avoid port 3 bus contention.

MOTOROLA MICROPROCESSOR DATA

3-96

MC6801/6803

FIGURE 8 - TIMING TEST LOAD PORTS " 2, 3, 4

FIGURE 7 - CMOS LOAD

VCC
RL 1.8 kD
Test Point
Test Point

t~PF

o-_......~.......

MMD6150
or Equivalent

C

R

MMD7000
or Equivalent

C=90
=30
R = 37
=24
= 24

pF
pF
kD
kD
kD

for
for
for
for
for

P30-P37,
Pl0-P17,
P40-P47,
Pl0-P17,
P30-P37,

P40-P47, E, SC1, SC2
P20-P24
SC1, SC2
P20-P24
E

INTRODUCTION
The term "port," by itself, refers to all of the hardware
associated with the port. When the port is used as a "data
port" or "I/O port," it is controlled by the port data direction
register and the programmer has direct access to the port
pins using the port data register. Port pins are labeled as Pij
where i identifies one of four ports and j indicates the particular bit.
The microprocessor unit (MPU) is an enhanced MC6800
MPU with additional capabilities and greater throughput. It is
upward source and object code compatible with the
MC6800. The programming model is depicted in Figure 9,
where accumulator D is a concatenation of accumulators A
and B. A list of new operations added to the M6800 instruction set are shown in Table 1.
The MC6803 can be considered an MC6801 that operates
in Modes 2 and 3 only.

The MC6801 is an 8-bit monolithic microcomputer which
can be configured to function in a wide variety of applications. The facility which provides this extraordinary flexibility
is its ability to be hardware programmed into eight different
operating modes. The operating mode controls the configuration of 18 of the 40 MCU pins, available on-chip
resources, memory map, location (internal or external) of interrupt vectors, and type of external bus. The configuration
of the remaining 22 pins is not dependent on the operating
mode.
Twenty-nine pins are organized as three 8-bit ports and
one 5-bit port. Each port consists of at least a data register
and a write-only data direction register. The data direction
register is used to define whether corresponding bits in the
data register are configured as an input (clear! or output
(set!.

MOTOROLA MICROPROCESSOR DATA
3-97

I

MC6801/6803

FIGURE 9 -

~

.

A

: - -- -- --- -

°U

PROGRAMMING MODEL

7

B

~ a-Bit Accumulators A and B

O' - - - - - - - - - ; 0, '6-6;, Oo"bI,

'''"m"'''", 0

I

,,1_5_ _ _ _ _ _ _ _ _X_ _ _ _ _ _ _ _ _ _
Ol lndex Register (X)

"ll_5__-------S-P--------~OI

Stack Pointer (SP)

"ll_5_________P_C_ _ _ _ _ _ _ _~OI

Program Counter (PC)

°

Condition Code Register (CCR)
Carry/Borrow from MSB
Overflow
Zero
Negative
Interrupt
Half Carry (From Bit 3)

I

OPERATING MODES
The MC6801 provides eight different operating modes (0
through 7) and the MC6803 provides two operating modes (2
and 3). The operating modes are hardware selectable and
determine the device memory map; the configuration of port
3, port 4, SC1, SC2, and the physical location of the interrupt vectors.

expanded multiplexed modes. Table 2 summarizes the characteristics of the operating modes.

MC6801 Single-Chip Modes (4, 7)

In the single-chip mode, the. four MCU ports are configured as parallel input/output data ports, as shown in
Figure 10. The MCU functions as a monolithic microcomputerin these twb modes without external address br data
buses. A maximum of29 I/O lines and two port 3 control
lines are provided. Peripherals or another MCU can be interfaced to pbrt 3 in a loosely coupled dual processor configuration, as shown in Figure 11.

FUNDAMENTAL MODES

The eight operating modes can be grouped into three fundamental modes which refer to th~ type of bus itsupports:
single chip, expanded· non-multiplexed, and" expanded
multiplexed. Single-chip modes include 4 and 7, expanded
non-multiplexed mode is 5, and the remaining five modes are

TABLE 1 -

NEW INSTRUCTIONS

Instruction
Description
ABX
Unsigned addition of accumulator B to index register
ADDD
Adds (without carry) the double accumulator to memory and leaves the sum in the double accumulator
ASLD or LSLD Shifts the double accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C bit
BHS
Branch if higher or same; unsigned conditional branch (same as BCC)
BLO
Branch if lower; unsigned conditional branch (same as BCS)
BRN
Branch never
JSR
Additional addressing mode: direct
LDD
Loads double accumulator from memory
LSL
Shifts memory or accumulator left (towards MSB) one bit; the LSB is cleared and the MSB is shifted into the C bit
(same as ASL)
LSRD
Shifts the double accumulator right (towards LSB) one bit; the MSB is cleared and the LSB is shifted into the C bit
MUL
Unsigned multiply; multiplies the two accumulators and leaves the product in the double accumulator
PSHX
Pushes the index register to stack
PULX
Pulls the index register from stack
STD
Stores the double accumulator to memory
SUBD
Subtracts memory from the double accumulator and leaves the difference in the double accumulator
CPX
Internal processing modified to permit its use with any conditional branch instruction

MOT(}ROLA MICROPROCESSOR DAT~
3-98

MC6801/6803

In single-chip test mode (4), the RAM responds to $XX80
through $XXFF and the ROM is removed from the internal
address map. A test program must first be loaded into the
RAM using modes 0, 1, 2, or 6. If the MCU is reset and then
programmed into mode 4, execution will begin at
$XXFE:XXFF. Mode 5 can be irreversibly entered from mode
4 without asserting RESET by setting bit 5 of the port 2 data
register. This mode is used primarily to test ports 3 and 4 in
the single-chip and non-multiplexed modes.
MC6801 Expanded Non-Multiplexed Mode (5)
A modest amount of external memory space is provided in
the expanded non-multiplexed mode while significant onchip resources are retained. Port 3 functions as an 8-bit

TABLE 2 -

bidirectional data bus and port 4 is configured initially as an
input data port. Any combination of the eight least-significant address lines may be obtained by writing to the port 4
data direction register. Stated alternatively, any combination
of AO to A7 may be provided while retaining the remainder as
input data lines. Internal pullup resistors pull the port 4 lines
high until the port is configured.
Figure 12 illustrates a typical system configuration in the
expanded non-multiplexed mode. The MCU interfaces
directly with M6800 Family parts and can access 256 bytes of
external address space at $100 through $1 FF. lOS provides
an address decode of external memory ($100-$1 FF) and can
be used as a memory-page select or chip-select line.

SUMMARY OF MC6801/Q3 OPERATING MODES

Common to all Modes:
Reserved Register Area
Port 1
Port 2
Programmable Timer
Serial Communications Interface
Single Chip Mode 7
128 bytes of RAM; 2048 bytes of ROM
Port 3 is a parallel I/O port with two control lines
Port 4 is a parallel I/O port
SC1 is Input Strobe 3 (lS3)
SC2 is Output Strobe 3 (OS3)
Expanded Non-Multiplexed Mode 5
128 bytes of RAM; 2048 bytes of ROM
256 bytes of external memory space
Port 3 is an 8-bit data bus
Port 4 is an input port/ address bus
SCl is Input/Output Select (lOS)
SC2 is Read/Write (R/W)
Expanded Multiplexed Modes 1, 2, 3, 6*
Four memory space options (64K address space):
(1) No internal RAM or ROM (Mode 3)
(2) Internal RAM, no ROM (Mode 2)
(3) Internal RAM and ROM (Mode 1)
(4) Internal RAM, ROM with partial address bus (Mode 6)
Port 3 is a multiplexed address/ data bus
Port 4 is an address bus (inputs/address in Mode 6)
SC1 is Address Strobe (AS)
SC2 is Read/Write (R/W)
Test Modes 0 and 4
Expanded Multiplexed Test Mode 0
May be used to test RAM and ROM
Single Chip and Non~Multiplexed Test Mode 4
(1) May be changed to Mode 5 without going through Reset
(2) May be used to test Ports 3 and 4 as I/O ports
*The MC6803 operates only in modes 2 and 3.

MOTOROLA MICROPROCESSOR DATA
3-99

I

FIGURE 10 -

-

•

FIGURE 11 -

SINGLE-CHIP MODE

-f

o:lJ
o

XTAL

Port 4
8110 Lines

VSS

Port 1

Port 1

8110

8110

Lines

Lines

Port 2
5110 Lines
SCI
16-Bit Timer

Port 2
5 1/0 Lines
Serial 1/0
16-Bit Timer

=

!;

Vee

Vee

Vee

Port 1
8110 Lines

so

SINGLE-CHIP DUAL PROCESSOR CONFIGURATION

Port 4

8110
Lines

-=

':'

Vss

Vss

Lines

s:

3:

16-Blt Timer

o:lJ

(')
Q)

~ o

o
o

()Q

C

."

~

~

(j)

om

FIGURE 12 -

CJ)
CJ)

EXPANDED NON-MULTIPLEXED CONFIGURATION

C
W

Vee

Vee

o:lJ

()Q

I

XTAL

~

~ EXTAL

C

~

Vee

XTAL

Standby-.
RESET ------..

NM'I~

MC6801

Port3
Port4
~
R/W
E

/8

(00-07)
(AO-A7)

8./
/

105
R/W
E

IRQj~

Port 3
8 Data Lines
R/W

Port 1
8 liD Lines
Port 2
5 liD
Lines
Serial 110

105
Port 4
To 8
':'

VSS

.

Port 1 ....
81/0 ....

--to..

Port 2
5 liD
SCI
Timer

....

---..

....

,..
~

VSS

RAM

-

PIA

ACIA

MC6801/6803

Expanded-Multiplex Modes (0, 1,2,3,6)
A 64K byte memory space is provided in the expanded-multiplex modes. In each of the expanded-multiplexed modes port 3 functions as a time multiplexed
address/data bus with address valid on the negative
edge of address strobe (AS), and data valid while E is
high. In modes 0 to 3, port 4 provides address lines A8
to A15.ln mode 6, however, port 4 initially is configured
at RESET as an input data port. The port 4 data direction
register can then be changed to provide any combination of address lines, A8 to A15. Stated alternatively,
any subset of A8to A15can be provided while retaining
the remaining port 4 lines as input data lines. Internal
pullup resistors pull the port 4 lines high until software
configures the port.
In mode 0, the reset vector is external for the first two
E cycles after the positive edge of RESET, and internal
thereafter. In addition, the internal and external data
buses are connected so there must be no memory map
overlap in order to avoid potential bus conflicts. Mode
o is used primarily to verify the ROM pattern and monitor the internal data bus with the automated test equipment.
Only the MC6801 can operate in each of the expanded-multiplexed modes. The MC6803 operates only
in modes 2 and 3.
Figure 13 depicts a typical configuration for the expanded-multiplexed modes. Address strobe can be used
to control a transparent D-type latch to capture addresses AO-A7, as shown in Figure 14. This allows port
3 to function as a data bus when E is high.

TABLE 3 -

P22
Mode*
7

PC2

P2l
PCl

P20
PCO

H

H

H

I

6

H

H

L

I

ROM

PROGRAMMING THE MODE
The operating mode is determined at RESET by the
levels asserted on P22, P21, and P20. These levels are
latched into PC2, PC1, and PCO of the program control
register on the positive edge of RESET. The operating
mode may be read from the port 2 data register as
shown below, and programming levels and timing must
be met as shown in Figure 15. A brief outline of the
operating modes is shown in Table 3. Note that if diodes
are used to program the mode, the diode forward voltage drop must not exceed the VMPDD minimum.
PORT 2 DATA REGISTER

7

6

5

4

PC2

PCl

PCO

P24

320

I I I I I I I
P23

P22

P21

MODE SELECTION SUMMARY
Interrupt
Vectors

Bus
Mode

I

I

I

I

I
MUXI5,6)

RAM

$0003

Circuitry to provide the programming levels is dependent primarily on the normal system usage of the
three pins. If configured as outputs, the circuit shown
in Figure 16 may be used; otherwise, three-state buffers
can be used to provide isolation while programming
the mode.

Operating
Mode
Single Chip
Multiplexed/ Partial Decode

NMUX(5,6) Non-Multiplexed/ Partial Decode

5

H

L

H

I

H

L

L

1(2 )

I
Ill)

I

4
3

L

H

E

E

E

I
MUX(4)

Multiplexed/No RAM or ROM

2

L

H
H

L

E

I

E

MUXI4)

Multiplexed/ RAM

1

L

L

H

I

I

MUX(4)

Multiplexed/RAM and ROM

0

L

L

L

I

I

E
1(3 )

MUX(4)

Multiplexed Test

Legend:
~ternal
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic Zero
H - Logic One

P20

I

Single-Chip Test

NOTES:
-wTriternal RAM is addressed at$XX80.
(2) Internal ROM is disabled.
(3) RESET vector is external for two cycles after RESET goes high.
(4) Addresses associated with ports 3 and 4 are considered external in modes 0,
1,2, and 3.
(5) Addresses associated with port 3 are considered external in modes 5 and 6.
(6) Port 4 default is user data input; address output is optional by writing to port 4
data direction register.

*The MC6803 operates only in modes 2 and 3.

MOTOROLA MICROPROCESSOR DATA
3-101

II

MC6801/6803

FIGURE 13 - EXPANDED MULTIPLEXED CONFIGURATION
VCC

1 • •~

Port.1
8 I/O Lines"
Port 2

Port 4

5 I/O Lines

8 Lines

Serial I/O
16-Bit Timer

Address Bus
VSS

VCC

II

8

Data Bus

r-=::....:..::.~--~-r-----T""'"-----r---:l~ (00-07)

16

Port11• • •~
8 I/O ....

51/0..,._*

Port 2

SCI ...
Timer

L-._,..----I

VSS

NOTE: To avoid data bus (port 3) contention in the expanded multiplexed modes, memory devices should be enabled only duringE high time.

FIGURE 14 - TYPICAL LATCH ARRANGEMENT
GNO
AS

I OCI

G
01

01

...
Port 3
Address/ Data

...
SN74LS373
(Typical)

Address: AO-A7

~

08

08

...
~

...

Data: 00-07
~

MOTOROLA MICROPROCESSOR DATA
3-102

Me6801/6803

FIGURE 15 _. MODE PROGRAMMING TIMING

See Figure 16
for Diode Arrangement

(P20, P21, P22)
VMPH Min

Mode Inputs
(P20, P21, P22)

Level

ntW' - - - - -

VMPL Max

MODE PROGRAMMING (Refer to Figure 15)
Characteristic
Mode Programming Input Voltage Low* (for TA=O to,70°C)
Mode Programming Input Voltage High
Mode Programming Diode Differential (If Diodes are Used) (for T A = 0 to 70°C)
RESET Low Pulse Width
Mode Programming Setup Time
Mode Programming Hold Time
RESET Rise Time",,1 f.Ls
RESET Rise Time<1 f.Ls

Symbol

Min

-

VMPL
VMPH

4.0
0.4
3.0
2.0
0
100

VME'.DD
PWRSTL
tMPS
tMPH

Note: For TA= -40 to 85°C, Maximum VMPL= 1.7, and Minimum VMPDD=0.4.
FIGURE 16 - TYPICAL MODE PROGRAMMING CIRCUIT

VCC

1
)0

•

.

>

RESET

..

P20

) .•>

.~R1>
4

R2 : >RH > R"
>
•

6

-.

8

9

P2 1 ~
P22

I

10

~

NOTES:
1. Mode 7 as shown
2. R2' C = Reset time constant
3. R, = 10k (typical)
4. D = IN914, IN4001 in the 0 to 70°C range
D=1N270, MBD201 in the -40to 85°C range
5. Diode Vf should not exceed VMPDD min

)

D

C

D~.

Mode
Control
Switches

D~.

_L...

I

MEMORY MAPS
The M6801 Family can provide up to 64K byte address
space depending on the operating mode. A memory
map for each operating mode is shown in Figure 17.
The first 32 locations of each map are reserved for the
internal register area, as shown in Table 4, with exceptions as indicated.

MOTOROLA'MICROPROCESSOROATA· •
3~103

RESET
P20 (PCo)
P21 (PCl)
P22 (PO)

MC6801
MC6803

Max
1.7

-

Unit
V
V
V
E Cycles
E Cycles
ns

II

MC6801/6803

FIGURE 17 -

Multiplexed- Test Mode

MC6801
Mode

MC6801/03 MEMORY MAPS (Sheet 1 of 3)

o

MC6801
Mode
Multiplexed/RAM and ROM

$0000(1)

InternaL Registers

$001 F'

1

$OOOO( 1) .~rrrTT7""7'T;""

~UL.a-££k(."'I

Internal Registers
External Memory Space
External Memory Space
Internal RAM
Internal RAM

$OOFF

External Memory Space

External Memory Space

$F800
Internal ROM

Internal ROM
$FFFF(2)

Internal Interrupt Vectors(2)

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.
2) Addresses $FFFE and $FFFF are considered
external if accessed within two cycles after a
positive edge of RESET and internal at all other
times.

$FFE F ,",UL..t.LL.~;.q
$FFFO
$FFFF L--_ _ _--'

External Interrupt Vectors

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.
2) Internal ROM addresses $FFFO to $FFFF are not
usable.

3) After two MPU cycles, there must be no overlapping of intern;ll and external memory spaces
to avoid driving the'data bus with more than one
device.
4) This mode is the only mode which may be used
to examine the interrupt vectors in internal ROM
using an external RESET vector.

MOTOROLA MICROPROCESSOR DATA
3-104

FIGURE 17 -

MC6801
MC6803
Mode

MC680lI03 MEMORY MAPS (Sheet 2 of 3)

MC6801
MC6803
Mode

2

3

MC6801
Mode

Multiplexed/No RAM or ROM
Multiplexed/ RAM
$oooo( 1)

$0000(1)
$001 F

rTTTTT77TfT77t'

Single-Chip Test

iJ,,,,,,
I'{({{(UUUI

J

Internal Registers

Internal Registers

4

$0000
$Q01F

~}

Internal Registers

$001 F !I/C/L/ (////'1 J
External Memory Space

3:

$0080 !,nuJnn;l<

::XJ

$OOFF

a
o

Internal RAM

Wfl"fl"/U"4jJ

!f;

Unusable (1 )(4)

External Memory Space

3:

==

n
::XJ

(')
0)

~ o
o "'1:1

U1

CO

External Memory Space

o

...a

m

::XJ

o

CO

(')

m
(/)
(/)

o::XJ
C

~

::::~ 1

$FFFO

11

External Interrupt Vectors

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF

$FFFF

I

o

W
External Interrupt Vectors

L . - .- - - - - '

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.

$XX80
$XXFF

~) Internal

RAM
Internal Interrupt Vectors

NOTES:
1) The internal ROM is disabled.
2) Mode 4 may be changed to Mode 5 without having to assert RESET by writing a one into the
PCO bit of the port 2 data register.
3) Addresses A8 to A 15 are treated as "don't cares"
to decode internal RAM.
4) Internal RAM will appear at $XX80 to $XXFF .

FIGURE 17 -

MC6801
Mode

•

MC6801/03 MEMORY MAPS (Sheet 3 of 3)

5

MC6801
Mode

6

MC6801
Mode

7

Non-Multiplexed/Partial Decode
Multiplexed/ Partial Decode

$OOOO(l)~

$OOOO( 1)

$001 F "'~:J...t..U-f-L-U.~

s:
d

o

;Q

o

$0080~
.

.

Internal RAM

$OOFF

$0100

.

} E..."" M.mmy Sp'"

$OlFF

rTT7TTT77TT

:::c:::r
$OOFF

Single Chip

$0000

7"'"

Internal Registers
~xternal

~

$OOlF~

Memory Space
$0080

Internal RAM

VU{(uuuq.(

~"TT7-h-rT7n""

$OOFF~

}

!;
~

~
o"'0
o
en

s:o

External Memory Space

Unusable

n

en

..
CO

;Q

~

Q

$ FBOO v7/7/

)/7777/11
$F800

~

Internal ROM

en
en

o:a
c

$FFFF

1;'0"0#//-11

Internal Interrupt Vectors

~

rI

$FFFF •

l>

$F800 VJ7JJJ~777/7/)j}

CO

C)

W

Internal ROM

Internal ROM
Internal Interrupt Vectors

NOTES:
1) Excludes the following addresses which may not
be use.<:f externally: $04, $06, and $OF (no IUS)'

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $06, and $OF.

2) This mode may be entered· without going
through RESET by using mode 4 and subsequently writing a one into the PCO bit of the port
2 data register.

2) Address lines A8-A 15 will not contain addresses
until the data direction register for port 4 has
been written with ones in the appropriate bits.
These address lines will assert ones until made
outputs by writing the data direction register.

3) Address lines AO to A7 will not contain addresses
until the data direction register for port 4 has
been written with ones in the appropriate bits.
These address lines will assert ones 'until made
outputs by writing the data direction register.

iii

$FFFF

~

Internal Interrupt Vectors

MC6801/6803

between them to prevent supplying power to Vee during
powerdown operation. Vee standby should be tied to
ground in mode 3.

MC6801/03 INTERRUPTS
The M6801 Family supports two types of interrupt requests: maskable and non-maskable. A non-maskable interrupt (NMI) is always recognized and acted upon at the completion of the current instruction. Maskable interrupts are
controlled by the condition code register I bit and' by individual enable bits. The I bit controls all maskable interrupts. Of the maskable interrupts, there are two types: IRQ1
and IR02. The programmable timer and serial communications interface use an internal IRQ2 interrupt line, as shown
in Figure 1. External devices (and IS3) use IRQ1. An IR01 interrupt is serviced before IR02 if both are pending.
All IRQ2interrupts use hardware prioritized vectors. The
single sel interrupt and three timer interrupts are serviced in
a prioritized order and each is vectored t'o a separate location. All interrupt vector locations are shown in Table 5.
The interrupt flowchart is depicted in Figure 18 and is
common to every interrupt excluding reset. During interrupt
servicing the program counter, index register, A accumulator, B accumulator, and condition code.registefare pushed
to the stack. The I bit is set to inhibit maskable interrupts and
a vector is fetched corresponding to the current highest
priority interrupt. The vector is transferred to the program
counter and instruction execution is resumed. Interrupt and
RESET timing are illustrated in Figures 19 and 20.

TABLE 4 -

INTERNAL REGISTER AREA
Register

FUNCTIONAL PIN DESCRIPTIONS
Vee AND Vss
Vee and VSS provide power to a large portion of the
MeU. The power supply should provide + 5 volts (± 5%) to
Vee, and VSS should be tied to ground. Total power
diSSipation (including Vee standby), will not exceed PD
milliwatts.

Address

Port
Port
Port
Port

1
2
1
2

Data
Data
Data
Data

Direction Register* * *
Direction Register* * *
Register
Register

00
01
02
03

Port
Port
Port
Port

3
4
3
4

Data
Data
Data
Data

Direction Register * * *
Direction Register* * *
Register
Register

04*
05* *
06*
07* *

Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
OutputCompare Register (High Byte)

08
09
OA
OB

Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register
Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register

OC
OD
OE
OF*
'10
11
12
13

RAM Control Register
Reserved

14
15-1F

* External addresses in

modes 0, 1, 2, 3, 5, and 6; cannot be accessedin mode 5 (no lOS).
* * External addresses in .modes 0, 1, 2, and 3
*" * 1 = Output, 0= Input.

TABLE 5 -

Vee STANDBY
Vee standby provides power to the standby portion ($80
through $BF) of the RAM and the STBY PWR and RAME
bits of the RAM control register. Voltage requirements depend on whether the device is in a powerup or powerdown
state. In the powerup state, the power supply should provide
+ 5 volts (± 5%) and must reach V S B volts before RES ET
reaches 4.0 volts. During powerdown, Vee standby must remain above VSBB (min) to sustain thestandby RAM and
STBY PWR bit. While in powerdown operation, the standby
current will not exceed ISBB·
It is typical to power both Vee and Vee standby from the
same source during normal operation. A diode must be used

MCU INTERRUPT VECTOR LOCATIONS

MSB

LSB

Interrupt

FFFE

FFFF

RESET

FFFC

FFFD

NMI

FFFA

FFFB

Software Interrupt (SWI)

FFF8

FFF9

IROl (or IS3)

FFF6

FFF7

I CF (Input Capture) *

FFF4

FFF5

OCF (Output Capture) *

FFF2

FFF3

TOF (Timer Overflow) *

FFFO

FFF1

SCI (RDRF + ORFE+ TDRE) *

*IR02 Interrupt

MOTOROLA MICROPROCESSOR DATA
3-107

II

FIGURE 18 -

•

INTERRUPT FLOWCHART

3:

o

a
:xJ

o

):

s:n

3:

~

n
:xJ

0)

CO

o :xJo"a
CO
oo

Q

~

Oi
CO
o
w

m

(J)
(J)

o

:xJ

c

»

.~

SCI = TIE-TDRE + RIE-(RDRF+ ORFE)

Condition Code Register

IRQl

FFF8:FFF9

ICF

FFF6:FFF7

OCF

FFI-4:l-l-l-b

l~L FFF2: FFF3
FFFO:FFFl
SCI

~
A

FIGURE 19 - INTERRUPT SEQUENCE

Last Instruction

I Cycle

I

#1

#3

#2

I

#4

#5

I

#7

#8

ACCA

ACCB

#6

#9

I

#10

I

I

#11

#12

I

E
Internal
Address Bus

IRQ1

s:

a
:D

o

5:
s:
Co\)

nXI

U)

:D

,.

~ I+-tpes

NMI or IRQ2

~~tPes

Internal
DataBus~

Op Code Op Code

PC 0-7

PC8-15

X 0-7

X 8-15

\

Internal RIW

CCR

Irrelevant
Data

Vector
MSB

Vector First Inst. of
LSB
Interrupt Routine

I

3:

o0)
CO

':"0
o "'0.

Q

~

0;

o
(")

Q

W

\\\\\\\~\\\\! ~\\\\\\\\\\\\\\\

o

:D.
C

~

CO

FIGURE 20 - RESET TIMING

m

en
en

Vee
RESET

A IdnternaBI
dress us
Internal R/W
Internal
Data Bus

5.25V
-+475V

;/ I... .

LJL.f1

r1J1..JlS

't·

II

---~I

I

~

tRC

I

tpes

08'\~!I=-_- - -

I I

SS\\\\\\\S\\\\\\\~ b\\\\\\\\\\\\\\\\S\\\\SSSS\~
/.
.
FFFE . FFFE

&\\S\\\\~\\\\\S\'{ t\\SS\\\\\\\\\\\\\\\\\\\\\\V

'40 K

50n
6.5 pF
0.025 pF
>30 K

30-50 n
4-6 pF
0.01-0.02 pF
>20 K

30-50 n
4-6 pF
0.01-0.02 pF
>20 K

20-40 n
4-6 pF
0.01-0.02 pF
>20 K

These are representative AT -cut crystal parameters only. Crystals of other types of cut may also
be used.

MC6801

101

L1

C1

3

RS

3

2

Co

CL = 20 pF (typical)

Equivalent Circuit
NOTE
TTL-compatible oscillators may be
obtained from:
Motorola Component Products
Attn: Data Clock Sales
2553 N. Edgington St.
Franklin Park. IL 60131
Tel: 312-451-1000
Telex: 433'0067

(b) Oscillator Stabilization Time (tRC)

I.,..-------~J~I'-----~----------

VCC

4.75V

~1.------tRC----J~~
Oscillator
Stabilization
Time, tRC

MOTOROLA MICROPROCESSOR O'ATA
3-111

I

MC6801/6803

Port 3 In Expanded NOh~Multiplexed Mode
Port 3 is configured as a bidirectional data bus (O7-00l in
the expanded non-multiplexed mode. The direction of data
transfers is controlled by readlwrite (SC2). Data is clocked
by E (enable).

Port 2 can also be used to provide an interface for the
serial communications interface and the timer input edge
function. These configurations are described in PROGRAMMABLE TIMER and SERIAL COMMUNICATIONS INTERFACE (SCI).
The port 2 high-impedance TTL-compatible output buffers
are capable of driving one Schottky TTL load and 30 pF,or
CMOS devices using external pullup resistors.

Port 3 In Expanded~Multiplexed Mode
Port 3 is configured as a time multiplexed address (AO-A7)
and' data bus (07-00) in the expanded-multiplexed modes,
where address strobe (AS) can be used to demultiplex the
two buses. Port 3 is held in a high-impedance state between
valid address, and data to prevent bus conflicts.

PORT 3 (P30-P37)
Port 3 can be configured as an 170 port. a bidirectional
8-bit data bus, or a multiplexed addressl data bus depending
on the operating mode. The TTL-compatible highimpedance output buffers can drive one Schottky TTL load
and 90 pF. Unused lines can remain unconnected.

I

PORT 4 (P40-P47)
Port 4 is configured asan 8-bit 1/0 port. as address outputs, or as data inputs depending on the operating mode.
Port 4 can drive one Schottky TTL load and 90 pF and is the
only port with internal pullup resistors. Unused lines can remain unconnected.

Port 3 In Single-Chip Mode
Port 3 is an 8-bit 1/0 port in the single-chip mode, with
each line configured by the port 3 data direction register.
There are "llso two lines, IS3 and OS3, which can be used to
control port 3 data transfers.
Three port 3 options are controlled by the port 3 control
and status register and are availpble only in single-chip
mode: (1) port 3 input data can be latched using IS3 as a
control signal, (2) OS3 can be generated by either an MPU
read or write to the port 3 data register, and (3) an IRQ1 interrupt can be enabled by an lS3 negative edge. Port 3 latch
timing is shown in Figure 5.

Port 4 In Single-Chip Mode
In single-chip mode, port 4 functions as an 8-bit 1/0 port
with each line configured by the port 4 data direction
register. Internal pullup resistors allow the port to directly
interface with CMOS at 5 volt levels. External pullup resistors
to more than 5 volts, however, cannot be used.
Port 4 In Expanded Non-Multiplexed Mode
Port 4 is configured from reset as an 8-bit input port,
where the port 4 data direction register can be written to provide any or all of eight address lines, AO to A7. Internal
pullup resistors pull the lines high until the port 4 data direction register is configured.

PORT 3 CONTROL AND STATUS REGISTER

o
$OOOF

Bit 0-2
Bit 3

Bit 4

Bit 5
Bit 6

Bit7

Port 4 In Expanded-Multiplexed Mode
In all expanded-multiplexed modes except mode 6, port 4
functions as half of the address bus and provides A8 to A 15.
In mode 6, the port is configured from reset as an 8-bit
parallel input port. where the port 4 data direction register
can be written to provide any or all of upper address lines A8
to A 15. Internal pullup resistors pull the lines high until the
port 4 data direction register is configured, where bit 0 controls A8.

Not used.
LATCH ENABLE. This bit controls the
input latch for port 3. If set, input data
is latched by an IS3 negative edge. The
latch is transparent after a read of the
port 3 data register. LATCH ENABLE
is cleared during reset.
OSS (Output Strobe Select). This bit
determines whether OS3 will· be
generated by a read or write of the port
3 data register. When clear, the strobe
is generated by a read; when set, it is
generated by a write. OSS is cleared
during reset.
Not used.
IS3 IRQ1 ENABLE. When set, an IRQ1
interrupt will be enabled whenever IS3
FLAG is set; when clear, the interrupt
is inhibited. This bit is cleared during
reset.
IS3 FLAG. This read-only status bit is
set by an IS3 negative edge. It is
cleared by a read of the port 3 control
and status register (with IS3 FLAG set)
followed by a read or write to the port
3 data register or during reset.

RESIDENT MEMORY
The MC6801 provides 2048 bytes of on-chip ROM and 128
bytes of on-chip RAM.
One halfof the RAM is powered through the VCC standby
pin and is maintainable during VCC powerdown. This standby portion of the RAM consists of 64 bytes located from $80
through $BF.
Power must be supplied to V CC standby if the internal
RAM is to be used regardless of whether standby power
operation is anticipated.
The ROAM is controlled by the RAM control register.
RAM CONTROL REGISTER ($14)
The RAM control register includes two bits which can be
used to control RAM accesses and determine the adequacy
of the standby power source d~ring powerdown operation.
It is intended that RAME be cleared and STBY PWR be set
as part of a powerdown procedure.

MOTOROLA MICROPROCESSOR DATA

3-112

MC6801/6803

standby RAM is not valid. This bit can
be set only by software and is not affected during reset.

RAM CONTROL REGISTER

PROGRAMMABLE TIMER
Bit 0-5
Bit 6 RAME

Bit 7 STBY PWR

Not used.
RAM Enable. This read/write bit can
be used to remove the entire RAM
from the internal memory map. RAME
is set (enabled) during reset provided
standby power is available on the pusitive edge of RESET. If RAME is clear,
any access to a RAM address is external. If RAME is set and not in mode 3,
the RAM is included in the internal
map.

The programmable timer can be used to perform input
waveform measurements while independently generating an
output waveform. Pulse widths can vary from several microseconds to many seconds. A block diagram of the timer is
shown in Figure 22.

Standby Power. This bit is a
read/write status bit which, when
once set. remains set as long as V CC
standby remains above VSBB (minimum). As long as this bit is set following a period of standby operation, the
standby power supply has adequately
preserved . the data in the standby
RAM. If this bit is cleared during a
period of standby operation, it indicates that V CC standby had fallen to a
level sufficiently below VSBB (minimum) to suspect that data in the
FIGURE 22 -

COUNTER ($09:0A)
The key timer element is a 16-bit free-running counter
which is incremented by E (enable). It is cleared during reset
and is read-only with one exception: a write to the counter
($09) will preset it to $FFF8. This feature, intended for
testing, can disturb serial operations because the counter
provides the SCI internal bit rate clock. TOF is set whenever
the counter contains all ones.
OUTPUT COMPARE REGISTER ($OB:OC)

The output compare register is a 16-bit read/write register
used to control an output waveform or provide an arbitrary
timeout flag. It is compared with the free-running counter on
each E cycle. When a match occurs, OCF is set and OLVL is
clocked to an output level register. If port 2, bit 1, is configured as an output, OLVL will appear at P21 and the output
compare register and OL V L can then be changed for the next

BLOCK DIAGRAM OF PROGRAMMABLE TIMER

Output
Level
Register

Bit 1
Port 2

DDR

Output Compare Pulse

Output
Level
Bit 1

Port 2

MOTOROLA MICROPROCESSOR DATA

3-113

Input
Edge
Bit 0
Port 2

I

MC6801/6803

compare. The function is inhibited for one cycle after a write
to its high byte ($OB) to ensure a valid compare. The output
compare register is set to $FFFF at RESET.

Bit 5 TOF

Timer Overflow Flag. TOF is set when
the counter contains all ones. It is
cleared by reading the TCSR (with
TOF set) then reading the counter high
byte ($09), or during reset.

Bit 6 OCF

Output Compare Flag. OCF is set
when the. output compare register
matches the free-running counter. It is
cleared by reading the TCSR (with
OCF set) and then writing to the output compare register ($OB or $OC), or
during reset.
Input Capture Flag. ICF is set to indicate a proper level transition; it is
cleared by reading the TCSR (with ICF
set) and then the input capture register
high byte ($OD), or during reset.

INPUT CAPTURE REGISTER ($OD:OE)

The input capture register is a 16-bit read-only register
used to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should
be configured as an input, but the edge detect circuit always
senses P20 even when configured as an output. An input
capture can occur independently of ICF: the register always
'contains the most current value. Counter transfer is inhibited, however, between accesses of a double byte MPU
read. The input pulse width must beat least two E cycles to
ensure an input capture under all conditions.

Bit 7 ICF

TIMER CONTROL AND STATUS REGISTER ($08)

I

The timer control and status register (TCSR) is an 8-bit
register of which all bits are readable, while only bits 0-4 can
be written. The three most-significant bits provide the timer
status and indicate if:

SERIAL COMMUNICATIONS INTERFACE (SCI)
A full-duplex asynchronous serial communications interface (SCI) is provided with two data formats and a variety of
rates. The SCI transmitter and receiver are functionally independent, but use the same data format and bit rate. Serial
data formats include standard mark/space (NRZ) and Biphase and both provide one start bit, eight data bits, and one
stop bit. "Baud" and "bit rate" are used synonymously in
the following description.

• a proper level transition has been detected,
• a match has occurred between the free-running
counter and the output compare register, and
• the free-running counter has overflowed.
Each of the three events can generate an IR02 interrupt
and is controlled by an individual enable bit in the TCSR.
TIMER CONTROL AND STATUS REGISTEA (TCSR)
7

6

5

4

3

2

1

WAKE-UP FEATURE

0

In a typical serial loop multi-processor configuration,
the software protocol will usually identify the addressee(s) at the beginning of the message. In order to permit uninterested MPU's to ignore the remainder of the
message, a wake-up feature is included whereby all further SCI receiver flag (and interrupt) processing can be
inhibited until'its data line goes idle. An SCI receiver is
re-enabled by an idle string of eleven consecutive ones
or during reset. Software must provide for the required
idle string between consecutive messages and prevent
it within messages.

IICF I OCF ! TaF ! EICI ! EOCI ! ETal !'EDG !OL VL! $0008
Bit 0 OLVL

Bit 1 EIDG

Bit 2 ETOI

Bit 3 EOCI

Bit 4 EICI

Output Level. OL VL is clocked to the
output level register by a successful
output compare and will appear atP21
if bit 1 of the port 2 data direction
register is set. It is cleared during reset.
Input Edge. IEDG is cleared during
reset and controls which level transition will trigger a counter transfer to
the input capture register:
I EDG = a Transfer on a negative-edge
IEDG = 1 Transfer on a positive-edge.
Enable Timer Overflow Interr·upt.
When set, an IR02 interrupt is enabled
for a timer overflow; when clear, the
interrupt is inhibited. It is cleared during reset.
Enable Output Compare Interrupt.
When set, an IRQ2 interrupt is enabled
for an output compare; when clear,
the interrupt is inhibited. It is cleared
during reset.
Enable Input Capture Interrupt. When
set, an IR02 interrupt is enabled for an
input capture; when clear, the interrupt is inhibited. It is cleared during
reset.

PROGRAMMABLE OPTIONS

The following features of the SCI are programmable:
• format: standard mark/space (NRZ) or Bi-phase
• clock: external or internal bit rate clock
• Baud: one of four per E clock frequency, or external
clock ( x 8 desired baud)
• wake-up feature: enabled or disabled
• interrupt requests: enabled individually for transmitter
and receiver
• clock output: internal bit rate clock enabled or disabled
to P22
SERIAL COMMUNICATIONS REGISTERS

The serial communications interface
dressable registers as depicted in Figure
by the rate and mode control register
receive control and status register. Data

MOTOROLA MICROPROCESSOR DATA

3·114

includes four ad23. It is controlled
and the transmit/
is transmitted and

MC6801/6803

received utilizirig a write-only transmit register and a readonly receive'register. The shift registers are not accessible to
software.

time and rates for three selected MCU
frequencies.
CCl :CCO Clock Control and Format
Select. These two bits control the format and select the serial clock source.
If Cel is set, the DDR value for P22 is
forced to the complement of CCO and
cannot be altered until CCl is cleared.
If Cel is cleared after having been set,
its DDR value is unchanged. Table 7
defin!;ls the formats, clock source, and
use of P22.

Bit 3:Bit 2

Rate and Mode Control Registers (RMCR) ($10)
The rate and mode control register controls the SCI bit
rate, format, clock source, and under certain conditions, the
configuration of P22. The register consists of four write-only
bits which are cleared during reset. The two least-significant
bits control the bit rate of the internal clock and the remainirig two bits control the format and clock source.
RATE AND MODE CONTROL REGISTER (RMCR)

x
Bit l:Bit 0

4

3

X

CCl

2

1

SSl

If both Cel and CCO are set, an external TTL-compatible
clock must be connected to P22 at eight times (8X) the
desired bit rate, but not greater than E, with a duty cycle of
50% (± 10%). If CCl :CCO= 10, the internal bit rate clock is
provided at P22 regardless of the values for TE or RE.

0

I I Icco I Isso I

$0010

SSl:SS0 Speed Select. These two
bits select the baud rate when using
the internal clock. Four rates may be
selected which are a function of the
MCU input frequency. Table 6 lists bit

NOTE: The source of SCI internal bit rate clock is the timer
free-running counter. An MPU write to the counter
can disturb serial operations.

FIGURE 23 -

Bit 7

SCI REGISTERS

Rate and Mode Control Register

Bit 0

I Icco I I
CCl

SSl

SSO

1·$10

T ransmit/ Receive Control and Status Register

I RDRF 1OR FE ITDREI RIE I

RE,

1 TIE I· TEl wu I $11

Receive Data Register

10

12

Transmit Data Register

MOTOROLA MICROPROCESSOR DATA

3-115

I

MC6801/6803

RDRF and/or ORFE is set; when clear,
the interrupt is inhibited. RIE is cleared
during reset.

Transmit/Receive Control And Status Register
(TRCSR) ($11)
The transmit/ receive control and status register controls
the transmitter, receiver, wake-up feature, and two individual interrupts and monitors the status of serial operations. All eight bits are readable while bits 0 to 4 are also
writable. The register is initialized to $20 by RESET.

Bit 5 TORE

TRANSMIT/RECEIVE CONTROL AND STATUS
REGISTER (TRC.SR)
7

6

5

4

3

2

I

1

0

TE

WU

I I I

'RDRF 'ORFE 'TDRE' RIE , RE 'TIE

$0011

Bit 6 OR FE

BitO WU

"Wake-up" on Idle Line. When set,
WU enables the wake-up function;
it is cleared by eleven consecutive
ones or during reset. WU will not
set if the line is idle.

Bit 1 TE

Transmit Enable. When set, P24 OOR
bit is set, cannot be changed, and will
remain set if TE is subsequently
cleared. When TE is changed from
clear to set, the transmitter is can:
nected to P24 and a preamble of nine
consecutive ones is transmitted. TE is
cleared during reset.

Bit 2 TIE

Transmit Interrupt Enable. When set,
an IR02 interrupt is enabled when
TORE is set; when clear, the interrupt
is inhibited. TE is cleared during reset.

Bit 3 RE

Receive Enable. When set, the P23
OOR bit is cleared, cannot be changed, and will remain clear if RE is subsequently cleared. While RE is set, the
SCI receiver is enabled. RE is cleared
during reset.

Bit 4 RIE

Bit 7 RDRF

Receiver Interrupt Enable. When set.
an IR02 interrupt is enabled when

Transmit Data Register Empty. TORE
is set when the transmit data register is
transferred to the output serial. shift
register or during reset. It is cleared by
reading the TRCSR (with TORE set)
and then writing to the transmit data
register. Additional data will be
transmitted only if TORE .hasbeen
cleared.
Overrun Framing Error. If set, ORFE indicates either an overrun or framing error. An overrun is a new byte ready to
transfer to the receiver data register
with RDRF still set. A receiver framing
error has occurred when the byte
boundaries of the bit stream are not
synchronized to the bit counter. An
overrun can be distinguished from a
framing error by the state of RORF: if
RDRF is set, then an overrun has occurred; otherwise a framing error has
been detected. Data is not transferred
to the receive data register in an overrun condition. Unframed data causing
a framing error is transferred to the
receive data register. However, subsequent data transfer is blocked until the
framing error flag is cleared. * OR FE is
cleared by reading the TRCSR (with
OR FE set) then the receive data
register, or during reset.
Receive Data Register Full. RDRF is
set when the input serial shift register
is transferred to the receive data
register. It is cleared by reading the
TRCSR (with RDRF set), and then the
receive data register, or during reset.

TABLE 6 - SCI BIT TIMES AND RATES
4fo SSl:SS0
E
0
+16
0
0
1
+128
1
+1024
0
1
+4096
1
* External (P22)

2.4576 MHz
614.4 kHz
26 ,",s/38,4oo Baud
208 ,",s/4,8oo Baud
1.67 ms/600 Baud
6.67 ms/150 Baud
13.0 ,",s/76,8OO Baud

4.0 MHz
1.0 MHz
16 ,",s/62,5OO Baud
128 ,",s/7812.5 Baud
1.024 ms/976.6 Baud
4.096 ms/244.1 Baud
8.0 ,",s/125,ooo Baud

4.9152 MHz
1.2288 MHz
13.0,",s/76,800 Baud
104.2 ,",s/9,600 Baud
833.3 ,",s/1,2oo Baud
3.33 ms/300 Baud
6.5 ,",s/153,600 Baud

* Using maximum clock rate
TABLE 7 - SCI FORMAT AND CLOCK SOURCE CONTROL
CC1:CCO .'
00
01
10
11

Clock
Source
Bi-Phase Internal
NRZ
Internal
NRZ
Internal
NRZ
External
Format

Port 2
Bit 2
Not Used
Not Used
Output
Input

* Devices made with mask number M5G, M8D, and T5P do not transfer unframed data to the receive data register.

MOTOROLA MICROPROCESSOR DATA
3-116

MC6801/6803

SERIAL OPERATIONS

executable instruction is sufficient to identify the instruction
and the addreSSing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 82
instructions in all valid modes of addressing; are shown in
Table 8. There are 220 valid machine codes, 34 unassigned
codes, and 2 codes reserved for test purposes.

The SCI is initialized by writing control bytes first to the
rate and mode control register and then to the transmit/
receive control and status register. When TE is set, the output of the transmit serial shift register is connected to P24
and serial output is initiated by transmitting a 9-bit preamble
of ones.
At this point one of two situations exist': 1) if the transmit
data register is empty (TORE= 1), a continuous string of
ones will be sent indicating an idle line, or 2) if a byte has
been written to the transmit-data register (TO RE = 0), it will
be transferred to the output serial shift register (synchronized with the bit rate clock), TORE will be set, and transmission will begin.
The start bit (0), eight data bits (beginning with bit 0) and a
stop bit (1), will be transmitted. If TOR E is still set when the
next byte transfer should occur, ones will be sent until more
data is provided. In Bi-phase format, the output toggles at
the start of each bit and at half-bit time when a one is sent.
Receive operation is controlled by RE which configures P23
as an input and enables the receiver. SCI data formats are illustrated in Figure 24.

PROGRAMMING MODEL
A programming model for the MC6801/03 is shown in
Figure 10. Accumulator A can be' concatenated with accumulator B and jointly referred to as accumulator D where
A is the most-significant byte. Any operation which modifies
the double accumulator will also modify accumulator A
and/or B. Other registers are defined as follows:

Program Counter - The program counter is a 16-bit
register which always points to the next instruction.
Stack Pointer - The stack pOinter is a 16-bit register
which contains the address of the next available location in a
pushdown/pullup (LIFO) queue. The stack resides in random access memory at' a location defined by the programmer.
Index Register - The index register is ,a 16-bit register
which can be used to store data or provide an address for the
indexed mode of addressing.
Accumulators - TheMPU contains two 8-bit accumulators, A and B, which are used to store operands and results
from the arithmetic logic unit (ALU). They can also be concatenated and referred to as the D (double) accumulator.
Condition Code Registers - The condition code register
indicates the results of an instruction and includes the
following five condition bits: negative (N), zero (Z), overflow
(V), carry/borrow from MSB (C), and half carry from bit 3
(H). These bits are testable by the conditional branch instructions. Bit 4 is the interrupt mask (I bit) and inhibits all
maskable interrupts when set. The two unused bits, B6 and
B7, are read as ones.

INSTRUCTION SET
The MC6801/03 is upward source and object code compatible with the MC6800. Execution times of key instructions
have been reduced and several new instructions have been
added, including a hardware multiply. A list of new operations added to the MC6800 instruction set is shown in Table
1.
In addition, two new special opcodes, 4E and 5E, are provided for test purposes. These opcodes force the program
counter to increment like a 16-bit counter, causing address
lines used in the expanded modes to increment until the
device is reset. These opcodes have no mnemonics.
The coding of the first (or only) byte corresponding to an

FIGURE 24 -

SCI DATA FORMATS

Output

Clock

NRZ
Format

Bi-Phase
Format

Idle Start Bit

o

Bit
4

Data: 01001101 {$401

MOTOROLA MICROPROCESSOR DATA
3-117

7

Stop

II

MC6801/6803
Extended Addressing - The second and third bytes
of the instruction contain the absolute address of the
operand. These are three byte instructions.
Indexed Addressing - The unsigned offset contained
in the second byte of the instruction is added with carry
to the index register and used to reference memory
without changing the index register. These are two byte
instructions.
Inherent Addressing - The operand(s) are registers
and no memory reference is required. These are single
byte instructions.
. .
Relative Addressing.-:-:- Relative addressing is used
only for branch instructions. If the branch condition is
true, the program counter is overwritten with the sum
of a signed single byte displacement in the second by~e
of the instruction and the current program counter. This
provides a branch. range of - 126 to + 129 bytes fr~m
the first byte of the instruction. These are two byte Instructions. '

ADDRESSING MODES
Six addressing modes can be used to reference memory. A summary of addressing modes for all instructions
is present in Tables 9through 12, where execution times
are provided in E cycles. Instruction execution times are
summarized in Table 13 .. With an input frequency of 4
MHz, E cycles are equivalent to microseconds. A cycleby-cycle description of bus activity for each instruction
is provided in Table 14 and a description of selected
instructions is shown in Figure 25.
Immediate Addressing- The operand or "immediate
byte(s)" is contained in the following byte(s) of the instruction where the number of bytes matches the size
of the register. These are two or th'ree byte instructions.
Direct Addressing - The least-significant byte of the
operand address is contained in the second byte of the
instruction and the most-significant byte is assumed to
be $00. Direct addressing aHows the user to access $00
through $FF using two byte instructions and execution
time is reduced by eliminating the additional memory
access. In most applications, the 256-byte area is reserved for frequently referenced data.

I

OP
00
01
02
03
04
05
06
07
08
09
OA
DB
DC
OD
DE
OF
10

11
12
13
14
15
16
17
18
19
1A
18
1C
10
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33

MNEM
NOP

MODE
INHER

LSRD
ASLD
TAP
TPA
INX
DEX
CLV
SEV
CLC
SEC
CLI
SEI
SBA
CBA

TAB
TBA

2

1

3
3

1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
3
3

2
2
2
2

2
2
2
2

It

,

2
2

1
1

DAA

INHER

2

1

ABA

INHER

2

1

BRA
BRN
BHI
BLS
BCC
BCS
BNE
BEQ
BVC
BVS
BPL
BMI
BGE
BU
BGT
BLE
TSX
INS
PULA
PULB

NOTES:

REL

3
3
3

3

REL
INHER

t

3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1

TABLE 8 - CPU INSTRUCTION MAP

-

#

OP

MNEM

6
6
6

2
2
2

6
6
3
6
6

2

3

COM
LSR

6
6

3
3

ROR
ASR
ASL
ROL
DEC

6
6
6
6
6,

3
3
3
3
3

9C
9D
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6

CPX
JSR
LDS
STS
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA
STAA
EORA
ADCA
.ORAA
ADDA
CPX
JSR
LDS'
STS
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA
STAA
EORA
ADCA
ORAA
ADDA
CPX
JSR
LDS
STS
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB

OP

MNEM

MODE

-

#

OP

MNEM

MODE

34

DES
TXS
PSHA
PSHB
PULX
RTS
ABX
RTI
PSHX
MUL
WAI
SW!
NEGA

INHER

3
3
3
3
5
5
3
10
4
10
9
12

68
69
6A
6B
6C
6D
6E
6F
70
71

ASL
ROL
DEC

INDXD

2

1
1
1
1
1
1
1
1.
1
1
1
1
1

2
2

1
1

35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53

54
55
56
57

68

!

COMA
LSRA
RORA
ASRA
ASLA
ROLA
DECA

2
2
2
2
2

1
1
1
1
1

INCA
TSTA

2
2

1
1

CLRA
NEGB

2
2

1
1

COMB
LSRB

2
2

T

RORB
ASRB
ASLB
ROLB
DECB

59
5A
5B ,
5C
INCB
5D
TSTB
T
5E
5F
CLRB
80
NEG
61
62
63
COM
64
LSR
65
ROR
86
67
ASR

2
2
2
2
2
2
2
INHER
INDXD

1

INDXD

2
6

6
6
6
6

INDXD
EXTND

2
2
2

72
73
74
75
76

77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83

84

85
86
87
86
89
1 8A
1 8B
1 8C
1 8D
' 1 8E
8F
1 90
1, 91
92
1 93
2 94
95
96
2 97
2 98
99
2 9A
2 9B
1
1

1

INC
TST
JMP
CLR
NEG

INC
TST
JMP
CLR
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA
EORA
ADCA
ORAA
ADDA
CPX
BSR
LOS

..

EXTND
IMMED

It
IMMED
REL
IMMED

SUBA DIR
CMPA'
~
SBCA
SUBD
ANDA
BITA
LOAA
STAA
EORA
ADCA
ORAA
ADDA

6
6
3
6
2
2
2
4
2
2
2

3
3
3
3
2
2
2
3
2
2
2

2'
2
2
2
4
6
3

2
2
2
2
3
2
3

3
3
3
5
3
3
3
3
3
3
3
3

2
2
2
2
2
2
2
2
2
2
2
2

MODE
DIR

~

DIR
INDXD

INDXD
EXTND

EXTND
IMMED

#

OP

MNEM

MODE

5
5
4
4
4
4
4
6
4
4
4
4
4
4
4
4
6

2
2
2
2
2

6

2

5
5
4
4
4
6
4
4
4
4
4
4
4
4
6
6
5
5
2
2
2
4
2
2
2

2

SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LOAB
STAB
EORB
ADCB
ORAB
AD DB
LDD
STD
LDX
STX
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
WAB
STAB
EORB
ADCB
ORAB
ADDB
LDD
STD
LDX
STX
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB
STAB
EORB
ADCB
ORAB
ADDB
LDD
STD
LDX
STX

DIR

2
2

DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
OF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF

2
2
2
2
2

2
2
2
2

2

2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
3
2
2

2

r7
C8
C9
CA
CB
CC
CD
CE
CF

EORB
ADCB
ORAB
ADDB
LDD
LOX

It
IMMED

AddreSSing Modes
INHER '" Inherent
INDXD "'" Indexed
IMMED IE Immediate
REL "" Relative
EXTND 5 Extended DI R "'" Direct
2. Unassigned opcodes are indicated by .. • .. and should not be executed,
3. Codes marked by "1" force the PC to function as a 16-bit counter.

MOTOROLA MICROPROCESSOR DATA
3-118

-

2
2
2
2
3

2
2
2
2
3

3

3

DIR
INDXD

!

INDXD
EXTND

~
EXTND

* UNDEFINED OP

3
3
3
5
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
6
4
4
4
4
4
4
4
4
5
5
5
5
4
4
4
6
4
4
4
4
4
4
4
4
5
5
5
5
CODE

,
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3

TABLE 9 -

INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes
Immed

Pointer Operations

MNEM Op -

Compare Index Register

CPX

Decrement Index Register

DEX

Decrement Stack Pointer
Increment Index Register

8C 4

Direct

Inherent

Extnd

index

# Op -

# Op -

# Op -

# Op -

3 9C

2 AC 6

2 BC 6

3

5

Boolean/
Arithmetic Operation

#

X-M:M+l

09

3

1 X-1-X

DES

34

3

1

INX

08 3

1 X+1-X

31

1 1 SP+1-SP

Increment Stack Pointer

INS

Load Index Register

LDX

CE 3

3 DE 4

Load S tack Pointer

LDS

8E

3 9E

Store Index Register

STX

Store Stack Pointer

STS

Index Reg-Stack Pointer

TXS

3

2

3

5

2

FE

5

3

M-XH,IM+11-XL

2 AE 5

2

BE 5

3

M -SPH,IM+ 1I:-SPL

DF 4

2

5

2

FF

5

3

XH -M,XL -1M +-11

9F

2 AF 5

2

BF 5

3

SPH -

4
4

EE

SP-1-SP

EF

3 '1

X-1-SP
SP+ 1-X

3

2

1

0

I

N

Z V

C

·· ·· ·f fl ·f ·l
· ·· ·· ·1 ·· ··
··· ·· · ·tlt · ···
··· ··· · · · ···
··· ··· ··· ·· ··· ···
··· ··
R
R

Stack Pntr -Index Register

TSX

30

3

1

Add

ABX

3A

3

1 B+X-X

Push Data

PSHX

3C

4

1 XL -MSp,SP-1-SP
XH - MSp,SP- 1 - SP

Pull Data

PULX

5

1

38

4

H

R

M,SPL -1M + 11

35

5

SP+1-SP,MSP-XH
SP+1-SP,MSP-X L

I

R

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2)
Condition Codes
Accumulator and
Memory Operations

Immed
MNEM Op

-

Direct

# Op -

Extend

Index

# Op -

# Op -

Inher

# Op -

Boolean
Expression

#

Add Accumulators

ABA

1B

2

1

AddBtoX

ABX

3A

3

1 oo:B+ X-X

Add with Carry

2 A9 4

2 D9 3

2

2 9B 3

ADCA 89

2

2

ADCB C9

2

Add

ADDA 8B

2

ADDB CB 2
Add Double

ADDD C3 4

And

ANDA 84

2

2 94

ANDB C4

2

2 D4 3

Shift Left, Arithmetic

Shift Left, Double
Shift Right, Arithmetic

Bit Test

4

3

B+M+C-B

2 AB 4

2 BB 4

3

A+M-A

2 DB 3

2 EB

4

2 FB 4

3

B+M-A

3 D3 5

2

6

2

F3

6

3

D+M:M+1-D

2 A4 4

2

B4 4

3

A·M-A

2

4

2

F4

4

3

B.M-B

6B 6

2

78

6

3

3

E3
E4

4

A+M+C-A

48

2

1

ASLB

58

2

1

05

3

1

ASRA

47

2

1

ASRB

57

2

1

ASLD
67

ASR

BITA

85

2

2 95

BITB

C5

2

2 D5 3

Clear

CLR

3

6

2

77 6

qll lillll-@]

2

B5 4

3

4

2

F5

4

3

B·M
11

6F

6

2

7F

6

2

1 A-B
oo-M

3

CLRA

4F

2

1 oo-A

CLRB

5F

2

1 oo-B

CMPA 81

2

2 91

3

2 A1

4

CMPB C1

2

2 D1

3

2

E1
03

COM

A-M

B1

4

4

2 F1

4

3

B-M

6

2

6

3

M-M

2

73

3

COMA

43

2

1

A-A

COMB

53

2

1

B-B

MOTOROLA'MICROPROCESSOR DATA
3-119

Z V C

1

0

·t ··· · · ·
t
t ·
l ·
·· ··· 1 ·
·
··· ···
·· ·
··· ··· tt tt tt tt
1 l
··· ··· t t ··
·· ···
·· ·· t t t t
·· ·· ;tt tt
·t t
J J J 1

~

2 A5 4
E5

+-0

bO

3

...::
A·M

2

2

N

R

0-111111111
b7

3

I

R

+-

ASLA

CBA

1's Complement

3

F9

ASL

Compare Accumulators

Compare

2

2

E9

4

H

t_

A+B-A

B9 4

99 3

5

b7

bO

R

R

"

I

I

I

I

R

S

R

R

R

S

R

R

R

S

R

R

II I I I
R

S

R

S

R

S

MC6801/6803

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2)
Condition Codes
Accumulator and
Memory Operations

Immed
MNEM Op

Decimal Adjust, A

DAA

Decrement

DEC

Exclusive OR

Increment

Load Accumulators

-

Direct

# Op -

Extend

Index

# Op -

Inher

# Op -

# Op -

2 7A

3

19
6A

6

6

2

1

B-l-B

0

0

EORA 88

2

2 98

EORB C8

2

2 D8 3

3

2 A8 4

2

B8

4

3

' AEilM-A

0

0

2

INC

E8

4

2

F8

4

3

BEilM-B

0

0

6C

6

2 7C

6

3

M+l-M

0

0

INCA

4C

2

1

A+l-A

0

0,

INCB

5C

2

1

B+l-B

0

0

M-A

0

0

LDAA 86

2

LDAB C6

2

CC 3

2

96

2

D6 3

2 A6 4

3

B6 4

2

3

F6

4

3

M-B

0

2 EC 5

2 FC

5

3

M:M+l-D

0

68

2 78

6

3

2

3 DC 4

2

E6

4

6

2

1

LSLB

58

2

1

LSLD

05

3

2

LSR

64 6

2

74

6

44

LSRB
LSRD

2

1

54

2

1

04

3

1

3D 10
60

6

2

70

6

~-jlllllillbO

-0

b7

3

LSRA

o-IIIIIIIII-~
b7

bO

1 AxB-D
oo-M-M

3

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0
0

NEGA

40

2

1 oo-A-A

0

NEGB

50

2

1 00- B -

0

0

NOP

01

2

1

PC+ I-PC

0

0

A+M-A

0

0

ORAA 8A

2

2 9A 3

2 AA 4

2 BA 4

3

ORAB CA 2

2 DA 3

2 EA 4

2

FA 4

3

0

0

0

0

0

0

0

0

0

1

Stack -

0

0

0

0

B

~-jIIIIIIII+-{9
b7

@]-11111111f-@]
b7

10

2

1

SBCB C2

2

2

D2

STAA

97

STAB

D7

3

SUBA 80
SUBB CO

Subtract Double

SUBD 83

2

E2

4

2 A7

4

2

E7

0

0

0

0

bO -

0

0

0

0

A-B-A

0

0

3

A-M-C-A

0

0

4

3

B-M-C-B

0

0

B7 4

3

A-M

0

0

3

B-M

0

0

2

F2

2

4

2

F7

4

DD 4

2

ED 5

2

FD 5

3

D-M:M+ 1

0

0

2

90

2 AD 4

2

BO 4

3

A-M-A

0

0

2

2

DO 3

2

EO

4

2

FO

4

3

B-M-B

0

0

4

3

93

2 A3

6

2

B3 6

3

D-M:M+l-D

0

0

STD
Subtract

3
3

0
0

0

1

Store Accumulators

bO

0
0

3
1

4

2

3

5

TAB

16

2

1

A-B

0

0

TBA

17

2

1

B-A

0

0

M-oo

0

0

TST

6D

6

2

7D

6

3

TSTA

4D

2

1

A-OO

0

0

TSTB

5D

2

1

B-oo

0

0

The conditIOn code register notes are listed after Table 12,

MOTOROLA MICROPROCESSOR'[)ATA'
3-120

0
0

0

2

B2

0

R

0

2

2

0

0

56
4

0

J 1

0

Stack

46

2 A2

0

Stack-A

RORB

3

0

B-

RORA

92

t
t
t
t t t t
t t t t
t t t t

1

1

2

t

t

1

1

2

t

t
t
t

3

3

SBA

0

4

2

SBCA 82

0

0

2

6

t R
t R
t t
t t t
t t t
t t t
R t t
R t t
R t t
R t t

0

49

76

0

0

59
2

0

R

t

R

ROLB
6

0

t t

t t

3

ROLA

66

t
t
t
t
t

0
0

0

4

ROR

0

t t R
t t t
t t t

0

33
6

0

0

32

79

0

0

37

2

0

0

PULA

6

t t t t
t tJ
t t t
t t t
t t R

B+M-B

PSHB

'69

0

A-Stack

36

ROL

B

1

1

PSHA

Subtract with Carry

Tesl, Zero or Minus

0

48

PULB

Transfer Accumulator

0

5A

NEG

Subtract Accumulator

0

0

DECB

MUL

Rotate Right

0

M-l-M

0

Multiply

Rotate Left

1 Adl binary sum to BCD

0

2's ComplementlNegatei

Pull Data

Z V C

A-l-A

LSL

Push Data

2

N

1

Logical Shift, Left

Inclusive OR

3

I

2

LDD

No Operation

4

H

4A

LSLA

I

#

5

DECA

Load Double

Shift Right. Logical

2

Boolean
Expression

0

t t t t
t t t t
t t t t
t t t t

t
t
t
t
t
t
t
t

t t t
t t t
t t t
t t t

t t t
t R
0

t

R

0

t R
t t t t
t t t t
t t t t
t t R
t t R
t t R R
t t R R
t t R R
0

0
0

MC6801/6803

TABLE 11 -

JUMP AND BRANCH INSTRUCTIONS
Condition Code Reg.

Operations
Branch Always
Branch Never

5

Direct
Relative
Inherent
Index
Extend
# Op
# Op
# Op - # Op
#
MNEM Op
BRA
20 3 2
None
BRN
21 3 2
None

-

Branch If Carry Clear

BCC

Branch If Carry Set
Branch If=Zero

-

-

-

Branch Test

2

BCS

24 3
25 3

2

C=1

BEQ

27

2

Z=1

Branch If ",Zero

BGE

2C 3

2

NE9v=o

> Zero

BGT

2E

3

2

Z+(N E9 V)=O

BJanch If Higher

BHI

C+Z=O

BHS

22 3
24 3

2

Branch If Higher or Same

2

Branch If sZero

BlE

2F 3

2

c=o
z+(NE9V)=1

Branch If Carry Set

BlO

25

3

2

C=1

Branch If lower Or Same

BlS

23

3

2

Branch If -'::::~
SP

2J

...Cf
N

co

o""a
2JoC')
m

fn
fn

o2J
~
~

RTN

EXTND

'

Main Program

!

Ef

3:

2J

~

RTI Return from Interrupt

S;

RTN

Ie:)

SP-3

Index Register (XH)

SP-2

I ndex Register (Xl)

SP-l

RTNH

SP

RTNL
I

g

Stack

SP
SP+l

Condition Code
AcmltrB

SL=Subr.Addr.

SP+3

AcmltrA

Next Main Ins!.

SP+4

Index Register (XH)

SP+5

Index Register (Xl)

en
CO

SP+6

RTNH

W

± K=Offset

~

Subroutine
$39= RTS

Stack

¢-. SP-2~
SP-l

I Next Main Instr.

Ef [

'''"'MrtP,,,,,,,,,
$3B= RTI

AcmltrB
AcmltrA

SP+2

$8D=BSR

RTS, Return from Subroutine

Ef

Ie::>

SP-5
SP-4

$BD=JSR

Main Program

RTN

I

$3E=WAI

I
Condition Code

SP-6

SH = Subr. Addr.

BSR, Branch To Subroutine

~

Main Program

RTNL

0,

c:;

WAI, Wait for Interrupt

Stack

SP-7

SP

I¢

...

~

. . . SP+7

L-

~TNL

_

RTNH· .

INDXD
Stack

SP~

SP+ 1

RTNH

SP+2

RTNL

Legend:
RTN= Address of next instruction in Main Program to be executed upon return from subroutine
RTNH = Most significant byte of Return Address
RTNL = Least significant byte of Return Address
- = Stack Pointer After Execution
K = a-bit Unsigned Value

~

JMP, Jump

RTNL

!

PC

X+ K

Main Program
.$7E=JMP

Next Instruction

'''-

{

KH = Next Address
KL = Next Address

Next

Instructib~

3:

o

en
CO
o
...a

o

MC6801/6803

ORDERING INFORMATION
The following information is required when ordering
a custom MCU. The information may be transmitted to
Motorola using the following media:
MOOS, disk file
PC-DOS disk file (360K)
EPROM(s) 2516, 2716, MC68701
To initiate a ROM pattern for the MCU, it is necessary
to first contact the local field service office, sales person,
or a Motorola representative.
FLEXIBLE DISKS
Several types of flexible disks (MOOS@) or PC-DOS
disk file) may be submitted for pattern generation. They
should be programmed with the customer's program,
using positive logic sense for address and data. The
diskette should be clearly labeled with the customer's
name, date, project or product name, and the filename
containing the pattern.
In addition to the program pattern, a file containing
the program source code listing can be included. This
data will be kept confidential and used to expedite the
process in case of any difficulty with the pattern file.
MOOS Disk File
MOOS is Motorola's Disk Operating System available
on the EXORciser® development system. The disk media submitted must be a single-sided, single-density, 8inch MOOS compatible floppy diskette. The diskette must
contain the minimum set of MOOS system files in addition to the pattern file.
The .LO output of the M6801 cross assembler should
be furnished. In addition, the file must be produced
using the ROLLOUT command, so that it contains the
absolute image of the M6801 memory. It is necessary
to include the entire memory image of both program
and data space. All unused bytes, including those in the
user space, must be set in logic zero.
PC-DOS Disk File
PC-DOS is the IBM® Personal Computer Disk Operating System. Disk media submitted must be standard
density (360K), double-sided 5-1/4 inch compatible floppy
diskette. The diskette must contain the object file code
in Motorola's S-record format. The S-record format is
a character-based object file format generated by M6801
cross assemblers and linkers on IBM PC style machines.
EPROMS
A single 2K EPROM is necessary to contain the entire
MC6801 program. The EPROM is programmed with the
customer program using positive logic sense for address and data. All unused bytes, including the user's
space, must be set to zero.
If the MC6801 MCU ROM pattern is submitted on a
single 2516 or 2716 type EPROM, memory map addressing is one-for-one. The data space ROM runs from
EPROM address $000 to $7FF. If an MC68701 is used,
the ROM map runs from $F800 to $FFFF.
For shipment to Motoro!a, EPROMs should be placed
in a conductive IC carrier and packed securely. Styrofoam is not acceptable for shipment.

Verification Media
All original pattern media, EPROMs or floppy disks,
are filed for contractual purposes and are not returned.
A computer listing of the ROM code will be generated
and returned along with a listing verification form. The
listing should be thoroughly checked and the verification form completed, signed, and returned to Motorola.
The signed verification form constitutes the contractual
agreement for the creation of the customer mask. To
aid in the verification process, Motorola will program
customer supplied blank EPROM(s) or DOS disks from
the data file used to create the custom mask.
ROM Verification Units (RVUs)
Ten MCUs Containing the customer's ROM pattern
will be sent for program verification. These units will
have been made using the custom mask, but are for the
purpose of ROM verification only. For expediency, the
MCUs are unmarked, packaged in ceramic, and tested
with five volts at room temperature. These RVUs are
free with the minimum order quantity, but are not production parts. These RVUs are not guaranteed by Motorola Quality Assurance.
Ordering Information
The following table provides generic information pertaining to the package type and temperature for the
MC6801/MC6803. This MCU device is available only in
the 40-pin dual-in-line (DIP) package in the Cerdip and
Plastic packages.
MDOS is a trademark of Motorola Inc.
MS-DOS is a trademark of Microsoft, Inc.
EXORciser is a registered trademark of Motorola Inc.
IBM is a registered trademark of International Business
Machines Corporation.

GENERIC INFORMATION
Frequency Temperature Cerdip Package Plastic Package
(MHz)
(S Suffix)
(P Suffix)
(Degrees C)
1.0
1.0
1.25
1.25
2.0
1.0
1.0
1.25
1.25
2.0

o to 70
-40 to +85
o to 70
-40 to +85
o to 70
o to 70
-40 to +85
o to 70
-40 to +85
o to 70

MOTOROLA MICROPROCESSOR DATA

3-129

MC6801S1
MC6801CS1
MC6801S1-1
MC6801CS-1
MC68B01S1
MC6803S
MC6803CS
MC6803S-1
MC6803CS-1
MC68B03S

MC6801P1
MC6801CP1
MC6801P1·1
MC6801CP-1
MC68B01P1
MC6803P
MC6803CP
MC6803P-1
MC6803CP-1
MC68B03P

II

MC6801/6803

PIN ASSIGNMENT

VSS
SC1
SC2
P30
P31
P32
P33
P34
P35
P22

P36

P24

P40

P37

I

P10

P41

" :P11

P42

P12

P43

P13

P44

P14

P45

P15

P46

P16

P47

P17

VCC
Standby

MOTOROLA MICROPROCESSOR DATA
3-130

MOTOROLA

• SEMICONDUCTOR
TECHNICAL DATA

MC6801U4
MC6803U4

Advance Information

Microcontroller/Microprocessor (MCU/MPU)
The MC6801 U4 is an 8-bit single-chip microcontroller unit(MCU) that enhances the capabilities of
the MC6801 and significantly enhances the capabilities of the M6800 Family of parts. It includes an
MC6801 microprocessor unit (MPU) with direct object-code compatibility and upward object-code
compatibility with the MC6800. Execution times of key instructions have been improved over the
MC6800, and the new instructions found on the MC6801 are included. The MCU can function as a
monolithic microcontroller or can be expanded to a 64K-byte address space. It is TIL compatible
and requires one + 5-volt power supply. On-chip resources include 4096 bytes of ROM, 192 bytes of
RAM, a serial communications interface (SCI), parallel 1/0, and a 16-bit six-function programmable
timer. The MC6803U4 can be considered an MC68Q1 U4 operati,ng in modes 2 or 3; i.e., those that
do not use internal ROM.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Enhanced MC6800 Instruction Set
Upward Source and Object Code Compatibility with the MC6800 and MC6801 ,
Bus Compatibility with the M6800 Family
8 x 8 Multiply Instruction
Single-Chip or Expanded Operation to 64K-Byte Address Space
Internal Clock Generator with Divide-by-Four Output
Serial Communications Interface (SCI) ,
16-Bit Six-Function Programmable Timer
Three Output Compare Functions
Two Input Capture Functions
Counter Alternate Address
4096 Bytes of ROM (MC6801U4)
192, Bytes of RAM
32 Bytes of RAM Retainable During Powerdown
29 Parallel 1/0 and Two Handshake Conirol Lines
NMllnhibited Until Stack Load
- 40°C to 85°C Temperature Range

This document contains information on a new product. Specifications and information herein are subject to change without notice,

MOTOROLA MICROPROCESSOR DATA
3-131

II

•

MC6801U4 MICROCOMPUTER FAMILY BLOCK DIAGRAM

UVl;J.~ :;;;OUJ
-~I~
X UJ UJlzl~

UVlI-X

> >

I Ii
s:o

a
::10

o

P37
P36
P35
P34
P33
P32
P31
P30
SC2
SCl

A7/07
A6/06
A5/05
A4/04
A3/03
A2/D2
Al/0l
AO/DO
R/W
AS

07
06
05
04
D3
D2
Dl
DO
R/W
lOS

IX:

Expanded Multiplexed
Expanded Non-Multiplexed
Single Chip

§.If Ij

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OS3

in

~

;:~

TINl
TOUTl
SCLK
RDATA
TOATA

I/O
I/O
I/O
I/O
I/O

iS3

s:

~

Co\)

s:
n::10
"'tI

~
00

.!..

0

N

::10

W

n

en
00
o...a

c:

o

o

(")

m

en
en

o::10

~

P47
P46
P45
P44
P43
P42
P4l
P40

A15
A14
A13
A12
All
Al0
A9
A8

A7
A6
A5
A4
A3
A2
Al
AO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

~

Port
4

~P1O

W
Port
1

NOTE: No functioning ROM in MC6803U4.

MC6801 U4 MICROCONTROLLER FAMIL V BLOCK DIAGRAM

Pll
P12
P13
P14
P15
P16
P17

TIN2
TOUT2
TOUT3

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

w

c:
~

Me6S01 U4/6S03U4

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Vec

-0.3 to +7.0

V

Input Voltage

Vin

-0.3 to +7.0

V

Operating Temperature Range
MC6801 U4, MC6803U4
MC6801 U4C, MC6803U4C

TA

TLto TH
-0 to 70
-40 to 85

°c

Tstg

-55 to +150

°c

Symbol

Value

Rating

Rating

Storage Temperature Range

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic
Ceramic

°CfW

6JA
50
50

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can be obtained from:
(1)

TJ =TA +(PD 6JA)
0

where:
TA
6JA
PD
PINT
PPORT

= Ambient Temperature, °c
=Package Thermal Resistance,
Junction-to-Ambient, °C/W
= PINT+ PPORT
= ICCxVCC' Watts - Chip Internal Power
= Port Power Dissipation, Watts ~ User Determined

For most applications PPORT
~ )I
~
~~
R2 ~ ~ R1. ~ R1 ~ ~ R1'>
~
> ~ ~ ~~

RESET

MC6801U4
MC6803U4

6

~

,

P20

8

~

9

P2 1

10

P22

NOTES:
1. Mode 7 as shown
2. R2·C = Reset time constant
3. R1 = 10 k (typical)
4. D = 1N914, 1N4001 in the 0 to 70°C range
D=1N270, MBD201 in the -40 to 85°C range
5. Diode Vf should not exc'eed VMPD min.

~

o

D

0

1•

0

RESET
P20 (PCo)
P21 (PC1)
P22 (PC2)

Mode
Control
Switches

II

1•

_r....

Figure 15. Typical Mode Programming Circuit
Multiplexed Test Mode
$0000(1)
Internal Registers

MC6801U4
Mode

External Memory Space

o

Internal RAM

External Memory Space
$BFFO ~~~~t>
$BFFF
~
External Interrupt Vectors(2)
$FOOO

External Memory Space
Internal ROM

$FF FF "",c.,u.:.c.c."",v
NOTES:
1) Excludes the following addresses which may
be used externally: $04, $05, $06, $07, and
$OF.
2) The interrupt vectors are at $BFFO-$BFFF.
3) There must be no overlapping of internal and
external memory spaces to avoid driving the
data bus with more than one device.

4) This mode is the only mode which may be
used to examine the entire ROM using an external RESET vector,
5) Modes 5-7 can be irreversibly entered from
mode 0 by writing to the PCO-PC2 bits of the
port 2 data register.

Figure 16. MC6801U4/MC6803U4 Memory Maps (Sheet 1 of 4)

MOTO~OLA MICROPROCESSOR, DATA

3-143

Me6S01 U4/6803U4

MC6801U4

Mode

MC6801U4
MC6803U4

1

Mode

2

Multiplexed/RAM

Multiplexed/RAM & ROM

Internal Registers

Internal Registers

External Memory Space

External Memory Space

, Internal RAM

Internal RAM

External Memory Space
External Memory Space

I

Internal ROM

SFFEF
SFFFO
SFFFF

I'L'~.L,L,,~'"IC

External Interrupt Vectors

NOTES:
1) Excludes the following addresses which
may be used externally: $04. $06. and $OF.
2) Internal ROM addresSes $FFFO t6 $FFFF
are not usable.
3) Address lines A8-A15 will not contain addresses until the data direction register
for port 4 has been written with "1s" in
the appropriate bits. These address lines
will assert "1s" until made outputs by
writing the data direction register.

External Interrupt Vectors

NOTE:
1) Excludes the following addresses which may
be used externally: $04. $05. $06. $07. and
$OF.

Figure 16. MC6801U4/MC6803U4 Memory Maps ($heet 2 of4)

MOTOROLA MICROPROCESSOR DATA
3-144

Me6801 U4/6803U4

MC6801U4
MC6803U4
Mode

3

MC6801U4
Mode

5

Nonmultiplexed/Partial Decode

Multiplexed/ RAM

$OOOO( 1 )rrTT777?77"TO~

$0000(1

$OO1F~ Internal Registers

$OO4O~unusable

External Memory Space

Internal RAM

$OOFF
$0100
External Memory Space
$OlFF
$D01 Frz~~~t'

Internal Registers(1, 2)

I

Unusable

External Memory Space
Internal RAM(1)

External Memory Space

Internal ROM

$FFFnll------«
External Interrupt Vectors

Internal Interrupt Vectors

$FFFFL----.¥

NOTES:
1) Relocating the internal registers and the internal RAM to high memory allows the processor to make use of direct addressing.
2) Excludes the following addresses which may
be used externally: $DOO4, $DOO5, $DOO6,
$DOO7, and $DOOF.

NOTES:
1) Excludes the following addresses which may
not be used externally: $04, $06, and $OF (no
lOS).
2) Address lines AO to A7 will not contain addresses until the data direction register for
port 4 has been written with "1s" in the appropriate bits. These address lines will assert
"1s" until made outputs by writing the data
direction register.

Figure 16. MC6801U4/MC6803U4 Mem'ory Maps (Sheet 3 of 4)

MOTOROLA MICROPROCESSOR DATA
3-145

II

Me6801 U4/6803U4

MC6801U4
Mode

6

MC6801U4
Mode

7

Single Chip

$OOOO~ Internal Registers
.

Internal Registers

$OOlF

""_~<..4.f-u'£"~

External Memory Space
Internal RAM

,-_

$OOFF

.. 'Internal RAM

Unusable

External Memory Space

II

I

$FOOO
Internal ROM

Internal ROM

Internal Interrupt Vectors

Internal Interrupt Vectors
$ FF FF

IZLL'LLL'LLLCLL.~

NOTES:
1) Excludes the following addresses which may
be used externally: $04, $06, $OF. '
2) Address lines AS-A 15 will not contain addresses until the data direction register for
port 4 has been written with "ls" in the appropriate bits. These address lines will assert
"ls" until made outputs by writing the data
direction register.

Figure 16. MC6801U4/MC6803U4 Memory Maps (Sheet 4 of 4)

MOTOROLA MICROPROCESSOR DATA
3-146

Me6801 U4/6803U4

Table 4. Internal Register Area

MC6801 U4/MC6803U4 INTERRUPTS
The M6801 Family supports two types of interrupt requests: maskable and nonmaskable. A nonmaskable interrupt (NMI) is always recognized and acted upon at the
completion of the current instruction. Maskable interrupts are controlled by the condition code register I bit
and by individual enable bits. The I bit controls all maskable interrupts. Of the maskable interrupts, there are two
types: IR01 and IR02. The programmable timer and serial communications interface use an internal IR02 interrupt line, as shown in the block diagram. External
devices and IS3 use IR01. An IR01 interrupt is serviced
before IR02 if both are pending.

Address
Other
Modes

Register

Mode 3

Port
Port
Port
Port

1
2
1
2

Data
Data
Data
Data

Direction Register* * *
Direction Register* * *
Register
Register

0000
0001
0002
0003

0000
0001
0002
0003

Port
Port
Port
Port

3
4
3
4

Data
Data
Data
Data

Direction Register* * *
Direction Register* * *
Register
Register

0004*
0005* *
0006*
0007* *

0004*
0005* *
0006*
0007* *

Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)

0008
0009
oooA
oooB

0008
0009
DOOA
DOOB

Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register

oooC
0000
oooE
oooF*

DOOC
0000
DOOE
DOOF*

0010
Rate and Mode Control Register
Transmit/ Receive Control and Status Register 0011
0012
Receive Data Register
0013
Transmit Data Register

0010
0011
0012
0013

RAM Control Register
Counter Alternate Address (High Byte)
Counter Alternate Address (Low Byte)
Timer Control Register 1

0014
0015
0016
0017

0014
0015
0016
0017

Timer Control Register 2
Timer Status Register
Output Compare Register 2 (High Byte)
Output Compare Register 2 (Low Byte)

0018
0019
00lA
00lB

0018
0019
D01A
D01B

Output Compare Register 3 (High Byte)
Output Compare Register 3 (Low Byte)
Input Capture Register 2 (High Byte)
Input Capture Register 2 (Low Byte)

00lC
0010
00lE
00lF

D01C
0010
DOlE
D01F

"NOTE
After reset, an NMI will not be serviced until the
first program load of the stack pointer. Any NMI
generated before this load will be remembered by
the processor and serviced subsequent to the stack
pointer load.
All IR02 interrupts use hardware-prioritized vectors.
The single SCI interrupt and three timer interrupts are
serviced in a prioritized order, and each is vectored to a
separate location. All interrupt-vector locations are shown
in Table 5. In mode 0, reset and interrupt vectors are
defined as $BFFO-$BFFF.
The interrupt flowchart, which is depicted in Figure 17;
is common to every interrupt excluding reset. During interrupt servicing, the program counter, index register, A
accumulator, B accumulator, and condition code register
are pushed to the stack. The I bit is set to inhibit maskable
interrupts, and a vector is fetched corresponding to the
current highest-priority interrupt. The vector is transferred to the program counter, and instruction execution
is resumed. Interrupt and RESET timing are illustrated in
Figures 18 and 19;

* External addresses In modes 0, 1, 2, 3, 5, and 6 cannot be
accessed in mode 5 (no lOS).
* * External Addresses in Modes 0, 2, and 3.
* * * 1 = Output, 0= Input

Table 5. MCU Interrupt-Vector Locations
Mode 0
MSB
LSB

Modes 1-3, 5-7
MSB

Interrupt * * *

LSB

BFFE

BFFF

FFFE

FFFF

BFFC

BFFD

FFFC

FFFD

Nonmaskable Interrupt**

BFFA

BFFB

FFFA

FFFB

Software Interrupt

RESET

BFF8

BFF9

FFF8

FFF9

Maskable Interrupt Request 1

BFF6

BFF7

FFF6

FFF7

Input Capture Flag.*

BFF4

BFF5
BFF3

FFF4
FFF2

FFF5

BFF2

FFF3

Output Compare Flag*
Timer Overflow Flag *

BFFO

BFFl

FFFO

FFFl

Serial Communications Interface*

* IRQ2 interrupt
* * NMI must be armed (by accessng stack pointer! before an
N M I is executed.
*** Mode 4 interrupt vectors are undefined.

MOTOROLA MICROPROCESSOR DATA
3~147

II

•
:s:

o

a
::XJ

o

s:

~

(")

s:
c=;

0)

co

o
.....

~
o"'g
i! ::lC
oo
::XJ

C

,a;

co

co
o
Co\)

m
en
en

C
01=00

o
::lC

SCI = TIE. TOAE + AIE.IAOAF + OAFEI
ICI = IICF1.EICIII + IICF2·EICI21
OCI = IOCF1'EDclll + IOCF2·EOCI21 + IOCF3'EOCI31

g
~

Vector ...... PC

Condition Code Register

1 11

I H III.N I z I V I C

Mode 0

Modes 1-3, 5-7

NMI

BFFC-BFFO

FFFC-FFFO

SWI

BFFA-BFFB

FFFA-FFFB

Software Interrupt

IRQl

BFFS-BFF9

FFFS-FFF9

Maskable Interrupt Request 1

ICf

BfF6 BFF7

FFF6-FFF7

Input Capture Interrupt

Ocf

Nonmaskabte Interrupt

BFf4 BFF5

FFF4-FFF5

Output Compare Interrupt

TOF

BFF2-BFF3

FFF2-FFF3

Timer Overflow Interrupt

SCI

BFFO-BFFI

FFFO-FFFI

SCI Interrupt

Figure 17_ Interrupt Flowchart

I Cycle

Last Instruction~

#1

#3

#2

I

#4

I

#5

#6

#9

#7

#8

ACCA

ACCB

I

#10

#11

#12

Iniernal
Address Bus

IRQ1

----+l

\.

NMI or IRQ2

~~tPes

s:

~

o
o

::ltI

);

s:

!+-tpes

Internal
DataBus~~~

PC 0- 7

OpCode Op Code

PC8-15

X 0-7

X 8-15

CCR

\

Internal Riw

Irrelevant
Data

Vector
MSB

Vector
LSB

First Inst. of
Interrupt Routine

I

en

CO

n
::ltI

Q

~ o

:;

C
~

Figure 18. Interrupt Sequence

"'0
::ltI

en

oo

CO
Q

m

en
en

o::ltI
C

~

s:
(")

Vee

,~\\~'\\&\\ ~I I
1\\\\\.&\,%\~,t&\\\\\V V..
+ 4525
75

/L

RESET

I...

InternaBI
Address us

----

Internal Riw
Internal
Data Bus

~

~I

1I .
tRC
II _ _ _ _ _ _

.

.

~

fb:::

08V4.0V

.

~
~~
~
08'\~c:....-.II

tpcs

.

..cs

_ __

S\\\\\~\\\\\\\\\\S«~ t\\\\\\\\\\\\\
\\\\\\\\\\\\\ \~
1,_ -.JL-_A-_....A_~\-_.A.._~_....J'--_"'-_J'-_
~
FFFE
FFFE

0\"\\\\N\\\\)\~ t\\\\\\\\\\\\\\\\\\\\\\\\\\V

&\\\\\\\\\\\\\\\\~ t'\\\\\\\\\\\\\\\\\\\\\\\\\\\\~
~Not.valid
Figure 19. RESET Timing

'4~
.
PC 8-15 PC 0-7

First
Instruction

~

W

C
,r:..

MC6801 U4/6803U4

given in cycles are referenced to this clock unless otherwise noted.

FUNCTIONAL PIN DESCRIPTIONS
VCC AND VSS
VCC and VSS provide power to a large portion of the
MCU. The power supply should provide + 5 volts (± 5%)
to VCC, and VSS should be tied to ground. Total power
dissipation (incuding VCC standby) will not exceed PD
milliwatts.
VCC STANDBY

II

VCC standby provides power to the standby portion
($40 through $5F in all modes except mode 3, which is
$D040 through $D05F) of the RAM, and the STBY PWR
and RAME bits of the RAM control register. Voltage requirements depend on whether the device is in a powerup or powerdown state. In the powerup state, the power
supply should provide + 5 volts (± 5%) an"" must reach
VSB volts before RESET reaches 4.0volts. During powerdown, VCC standby must remain above VSBB(minimum) to sustain the standby RAM and STBY PWR bit.
While in powerdown operation, the standby current will
not exceed ISBB.
It is typical to power both VCC and VCC standby from
the same source during normal operation. A diode must
be used between them to prevent supply'power to VCC
during powerdown operation.
XTAL AND EXTAL
These two input pinsinteriace either a crystal or TILcompatible clock to the MCU internal clock geneator. Divide-by-four circuitry is included which allows use of the
inexpensive 3.58-MHz or 4.4336-MHz color-burst TV crystals. A 20-pF capacitor should, be tied from each crystal
pin to ground to ensure reliable startup and operation.
Alternatively, EXTAL may be driven by an external TILcompatible clock at 4 fo with a duty cycle of 50% ( ± 5%)
with XTAL connected ground.
The internal oscillator is designed to interface with an
AT-cut quartz crystal resonator operated in parallel resonance mode in the frequencyrange specified forfXTAL.
The crystal should be mounted as close as possible to
the input pins to minimize output distortion and startup
stabilization time. The MCU is compatible with most commercially available crystals. Nominal crystal parameters
are shown in Figure 20.

NMI (NONMASKABLE INTERRUPT)
An NMI negative edge requests an MCU interrupt sequence, but the current instrution will be completed before it responds to the request. The MCU will then begin
an interrupt sequence. Finally, a vector is fetched from
$FFFC and $FFFD ($BFFC and $BFFD in mode 0), transferred to the ~ram counter, and instruction execution
is resumed. NMI typically requires a 3.3 k!l (nominal)
resistor to VCC. There is no internal NMI pullup resistor.
NMI must beheld low for at least one E cycle to be
recognized under all conditions.
NOTE
After reset, an NMI will not be serviced until the
fir,st program load of the staCk, pointer. Any NMI
generated before this load will remain pending by
the processor.
IRQ1 (MASKABLE INTERRUPT REQUEST 1)
IRQ1 is a level-sensitive input that can be used to request an interrupt sequence . .The MPU will complete the
current instruction before it responds to the request. If
the interrupt mask bit (I bit) in the condition code register
is clear, the MCU will begin an interrupt sequence. A
vector is fetched from $FFF8 and $FFF9 ($BFF8 and $BFF9
in mode 0), transferred to th'e program counter, and instruction execution is resumed.
IRQ1 typically requires an external 3.3 k!l (nominal)
resistor to VCC for wire-OR applications. IRQ1 has no
internal pullup resistor.

RESET
This input is used to reset the internal state of the device and provide an orderly startup procedure. During
powerup, RESET must be helq below 0.8 volts: 1) at least
tRC after VCC reaches 4.75 volts to provide sufficient time
for the clock generator to stabilize, and 2) until VCC standby
reaches 4.75 volts. RESET must be held low at least three
E cycles if asserted during powerup operation.
E (ENABLE)
This is an output clock used primarily for bus synchronization. It is TIL compatib/eand is the slightly skewed
divide-by-four result of the device input clock frequency.
It will drive one Schottky TIL load and 90 pF, and all data

SC1 AND SC2 (STROBE CONTROL 1 AND 2)
The function of SC1 and SC2 depends on the operating
mode. SC1 is configured as an output in all modes except
single-chip mode; whereas, SC2 is always an output. SC1
and SC2 can drive one Schottky load and 90 pF.
SC1 and SC2 in Single-Chip Mode
In single-chip mode, SC1 and SC2 are configured as
an input and output, respectively, and both function as
port 3 control lines. SC1 functions aslS3 and can be used
to indicate that port 3 input data is ready or output data
has been accepted.Three options associated with IS3 are
controlled by the port 3 contol and status register and
are discussed in the port 3 description; refer to P30-P37
(PORT 3). If unused, rS3 can remain unconnected.
SC2 is configured as OS3 and can be used to strobe
output data or acknowledge input data. ,It is controlled
by output strobe select (OSS) in the port 3 control and
status register. The strobe is generated by a read (OSS=O)
or write (OSS'= 1) to the port 3 data register. OS3 timing
is shown in Figure 3.
SC1 and SC2 in Expanded-Nonmultiplexed Mode
In the expanded-nonmultiplexed mode, both SC1 and
SC2 are configured as outputs. SC1 functions as input!
output select (lOS) and is asserted only when $0100
through $01 FF is sensed on the internal address bus.

MOTOROLA MICROPROCESSOR DATA
3-150

Me6S01 U4/6S03U4

(a) Nominal Recommended Crystal Parameters
Nominal Crystal Parameters*

3.58 MHz
600

4.00 MHz

5.0 MHz

500

30-500

Cl

3.5 pF
0.015 pF

6.5 pF
0.025 pF

4-6 pF
0.01-0.02 pF

Q

>40 K

>30 K

>20 K

RS
CO

*NOTE: These are representative AT-cut crystal parameters only. Crystals of other
types of cut may also be used.

MC6801U4

----------~IOI~-------Ll

Cl

RS

3

CO

CL = 20 pF (typical)

Equivalent Circuit
NOTE

TTL-compatible oscillators may
be .obtain from:
Motorola Component Products
Attn: Crystal Clock Oscillators
2553 N. Edgington St.
Franklin Park, IL 60131
Tel: 312-451-1000
Telex: 433-0067

(b) Oscillator Stabilization Time (tRC)

~4-.7-5-V----------~J~'--------------------------------

VCC

E

I

f

~.~-----'tRC------~

Oscillator
Stabilization
Time, tRC

Figure 20. MC6801 U4/MC6803U4 Family Oscillator Characteristics

MOTOROLA MICROPROCESSOR DATA
3-151

3

II

Me6801 U4/6803U4

SC2 is configured as read/write and is used to controi
the direction of data bus transfers. An MPU read is enabled when read/write and E are high.
SC1 and SC2 in Expanded-Multiplexed Mode
In the expanded-multiplexed modes, both SC1 nd SC2
are configured as outputs. SC1 functions as address strobe
and can be used to demultiplex the eight least-significant
addresses and the data bus. A latch controlled by address
strobe captures the lower address on the negative edge,
as shown Figure 13.
SC2 is configured as read/write and is used to control
the direction of data bus transfers. An MPU read is enabled when read/write and E are high.

Port 1 is a mode-independent 8-bit I/O and timer port.
Each line can be configured as either an input or output
as defined by the port 1 data direction register. Port 1
bits 0,1, and 2 (P10, P11, and P12) can also be used to
exercise one input edge function and two output compare
functions of the timer. The TTL-compatible three-state
buffers can drive one Schottky TTL load and 30 pF, Darlington transistors or CMOS devices using external pullup resistors. It is configured as a data input port during
RESET. Unused pins can remain unconnected.
P20-P24 (PORT 2)
Port 2 is a mode-independent 5-bit multipurpose I/O
port. The voltage levels present on P20, P21, and P22 on
the rising edge of RESET determine the operating mode
of the MCU. The entire port is then configured as a data
input port. The port 2 lines can be selectively cofigured
as data output lines by setting the appropriate bits in the
port 2 data direction register. The port 2 data register is
used to move data through the port. However, if P21 is
configured as an output, it is tied to the timer output
compare 1 function and cannot be used to provide output
from the port 2 data register unless output enable 1 (OE1)
is cleared in timer control register 1.
Port 2 can also be used to provide an interface for the
serial communications interface and the timer input edge
function. These configurations are described in SERIAL
COMMUNICATIONS INTERFACE and PROGRAMMABLE
TIMER.
The port 2 three-state TTL-compatible output buffers
are capable of driving one Schottky TTL load and 30 pF
or CMOS devices using external pullup resistors.
PORT 2 DATA REGISTER

PC2

PCI

PCO

Port 3 is an 8-bit I/O port in the single-chip mode with
each line configured by the port 3 data direction register.
There are also two lines, IS3 and OS3, which can be used
to control port 3 data transfers.
Three port 3 options are controlled by the port 3 control
and status register and are available only in single-chip
mode: 1) port 3 input data can be latched using IS3 as a
control signal, 2) OS3 can be generated by either an MPU
read or write to the port 3 data register, and 3) an IRQ1
interrupt can be enabled by an IS3 negative edge. Port 3
latch timing is shown in Figure 4.
PORT 3 CONTROL AND STATUS REGISTER
7

P10-P17 (PORT 1)

II

Port 3 in Single-Chip Mode

P24

P23

P22

P21

P20

$03

P30-P37 (PORT 3)
Port 3 can be configured as an I/O port, a bidirectional
8-bit data bus, or a multiplexed address/data bus depending on the operating mode. The TTL-compatible
three-state output buffers can drive one Schottky TTL
load and 90 pF. Unused lines can remain unconnected.

6

5

x

$OF

Bits 0-2 Not used.
Bit 3

Latch Enable - This bit controls the input latch
for port 3. If set, input data is latched by an IS3
negative edge. The latch is transparent after a
read of the port 3 data register. Latch enable is
cleared during reset.

Bit 4

Output Strobe Select (OSS) - This bit determines whether OS3 will be generated by a read
or write of the port 3 data register. When clear,
the strobe is generated by a read; when set, it
is generated by a write. OSS is cleared during
reset.

Bit 5

Not used.

Bit 6

IS3 IRQ1 Enable - When set, an IRQ1 interrupt
will be enabled whenever the 153 flage is set;
when clear, the interrupt is inhibited. This bit is
cleared during reset.

Bit 7

IS3 Flag - This read-only status bit is set by an
IS3 negative edge. It is cleared by a read of the
port 3 data register or during reset.

Port 3 in Expanded-Nonmultiplexed Mode
Port 3 is configured as a bidirectional data bus (07-00)
in the expanded-non multiplexed mode. The direction of
data transfers is controlled by read/write (SC2). Data is
clocked by E (enable).
Port 3 in Expanded-Multiplexed Mode
Port 3 is configured as a time-mUltiplexed address (A7AO)' and data bus (D7~DO) in the expanded-multiplexed
mo.de where A5 can be used to demultiplex the two buses.
Port 3is held in a high-impedance state between valid
address and data to prevent bus conflicts.
P40-P47 (PORT 4)
Port 4 is configured as an 8-bit I/O port, as address
outputs, or as data inputs depending on the operating

MOTOROLA .MICROPROCESSOR DATA
3-152

x

Me6801 U4/6803U4

edge of RESET. If RAME is clear, any access to
a RAM address is external. If RAME is set, the
RAM is included in the internal map.

mode. Port 4, which can drive one Schottky TIL load and
90 pF, is the only port with internl pullup resistors. Unused lines can remain unconnected.
Bit 7

Port 4 in Single-Chip Mode
In single-chip mode, port 4 functions as an 8-bit I/O
port with each line configured by the port 4 data direction
register. Internal pullup resistars allaw the port to directly
interface with CMOS at 5-volt levels. However, external
pullup resistors to more than 5 volts cannot be used.
Port 4 in Expanded-Nonmultiplexed Mode
Port 4 is configured from reset as an 8-bit input port
where the port 4 data directian register can be written to
provide any or all of eight address lines AO to A7. Internal
pullup resistors pull the lines high until the port 4 data
direction register is configured.
Port 4 in Expanded-Multiplexed Mode
In all expanded-multiplexed modes except modes
and 6, port 4 functions as ·half of the address bus and
provides A8 to A 15. In modes 1 and 6, the port is configured fram reset as an 8-bit parallel input port wherethe
port 4 data direction register can be written to provide
any or all of upper address lines A8 to A 15. Internal pullup
resistors pull the lines high until the port 4 data direction
register is configured where bit 0 controls A8.

RESIDENT MEMORY
The MC6801 U4 provides 4096 bytes of on-chip ROM
and 192 bytes of on-chip RAM.
Thirty-two bytes of the RAM ae powered through the
VCC standby pin arid are maintainable during VCC powerdown. This standby portion of the RAM consists of32
bytes located from $40 through $5F in all mades except
mode 3, which is $D040 thraugh $D05F.
Power must be supplied to. Vec standby if the internal
RAM is to be used, regardless of whether standby power
operation is anticipated.
The RAM is controlled by the RAM control register.
RAM CONTROL REGISTER ($14)
The RAM control register includes two bits, which can
be used to. control. RAM accesses and to determine the
adequacy of the standby power source during powerdown operation. Itis intended that RAME be cleared and
STBY PWR be set as part of a powerdown procedure.
RAM CONTROL REGISTER
7

6

x

x

x

x

$14

PROGRAMMABLE TIMER
The programmable timer can be used to perform measurements on two separate input waveforms while independently generating three output waveforms. Pulse
widths can vary from several microseconds to many seconds. A block diagram of the timer is shown in Figure
21.
COUNTER ($09:0A), ($15, $16)
The key timer element is a 16-bit free-running counter
that is incremented by E (enable). It is cleared during reset
and is read-only with one exception: in mode 0 a write
to the counter ($09) will configure itta $FFF8. This feature,
intended for testing, can disturb serial operations because the counter provides the SCI internal bitrate clock.
The TOF is set whenever the caunter contains all ones.
If ETOI is set, an interrupt will occur when the TOF is set.
The counter may also be read as $15 and $16 to avoid
inadvertently clearing the TOF.
OUTPUT COMPARE REGISTERS ($OB:OC)' ($1A:1B),
($1C:1D)
The three output compare registers are 16-bit read/
write registers, each used to control an output waveform
or provide an arbitrary time-out flag. They are compared
with the free-running counterduring the negative half of
each E cycle. When a match occurs, the corresponding
output compare flag (OCF) is set, and the corresponding
output level (OLVL) is clocked to an output level register.
If both the corresponding output enable bit and data direction register bit are set, the value represented in the
output level register will appear on the corresponding
port pin. The appropriate OLVL bit can then be changed
for the next compare.
The function is inhibited for one cycle after a write to
its high byte ($OB, $1A, or $1C) to ensure a valid compare
after a double-byte write. Writes can be made to either
byte of the output compare register without affecting the
other byte. The OLVL value will be clocked out independently of whether the OCF had previously been
cleared. The output compare registers are set to $FFFF
during reset.
.
INPUT CAPTURE REGISTERS ($OD:OE), ($1E:1F)

Bits 0-5 Not used.
Bit 6

Standby Power - This bit is a read/write status
bit that, when cleared, indicates VCC standby has
cjecreased sufficiently below VSBB (minimum) to.
make data in the standby RAM suspect. It can be
set anly by software and is not affected during
reset.

RAM Enable - This read/write bit c,an be used
to remove the entire RAM from the internal memory map. RAME is set (enabled) during reset provided standby power is available on the positive

The two input capture registers are 16-bit read-only
registers used to store the free-running counter when a
"proper" input transition occurs as defined by the corresponding input edge bit (lEDGl or IEDG2). The input
pin's data direction register should be configured asan

MOTOROLA MICROPROCESSOR DATA
3~153

II

•

,mm

MC6801U4/MC1IB03U4 Internal Bus

I

{'r
_0$lC-1O

l

Output Compare
Register 3

(

V$1A:1B
Output Compare
Register 2

V$OB:OC
Output Compare
Register 1

II

$09:0A
($15:16)
Free-Running
16-Bit Counter

II

II

j

3:

o

a

I

::XJ

o
£

V~

>

Il

Output Compares
(Three)

Overflow
Detect

I

/~

3:

L2

(;

/

~ o
U'I
"U

::XJ

~

m

o:xl

Edge Detects
(Two)

J

t

Inp

/

I

(

TCSR ($08)

TCRl ($17)

I

/~

/

l

IICFl I OCFl I TOF I EICll IEOIci11 ETOI IIEDGl OLVLl

t

g
~

f f

r

I

l

r

r

~

llCF2 IICFl 'OCF3' OCF2 , OCF1' TOF ,

I

II

~

/

OE3

I

llEDG21lEDGl oLvL3joLVL210LV111

l

, EICI2 , EICll 'EOCI3' EOCI2' EOCll

1

TCR2 ($18)

I

~

IRQ2

~ ~~I~~

Y yy

-J

-

~D

Y

Figure 21. Block Diagram of Programmable Timer

......--

evel

Q

~

I

-J. :

Out~

evel

Out~

evel

I

I

I

I

~

I

L
Output Level
Register 3

-

I

I
I

CO

c:

I

I

e

en
W

I

D

"-->

-110

I Out~

'---'--

-

Q

c:

Output Level I
Register 1 I

~~

.

m

I

Output Level
Register 2

s:

(")

I

'--t>

ETOI , TEST 'CLOCK'

-I

I

D

r--

I

TSR ($19)
1

J OE2 I OEl

......--

dge

I

f

/2
/
/3

/2

I

J

/

::XJ

"\.

rei

)

/2-

J

l$lE:$lF
Input Capture
Register 2

/

(

]

Port (
Cire

I

I

11

/3

o(')

fA
fA

I

$OD:OE
Input Capture
Register 1

Me6801 U4/6803U4

input, but the edge detect circuit always senses P10 and
P20 even when configured as an output. The counter
value will be latched into the into capture registers on
the second negative edge of the E clock following the
transition.
As input capture can occur independently of ICF; the
register always contains the most current value. However, counter transfer is inhibited between accesses of a
double-byte MPU read. The input pulse width must be at
least two E cycles to ensure an input capture under all
conditions.
TIMER CONTROL AND STATUS REGISTERS
Four registers are used to provide the MC6801 U4/
MC6803U4 with control and status information about the
three output compare functions, the timer overflow function, and the two input edge functions of the timer. They
are as follows:
Timer Control and Status Register (TCSR)
Timer Control Register 1 (TCR1)
Timer Control Register 2 (TCR2)
Timer Status Register (TSR)
Timer Control and Status Register (TCSR) ($08)
The timer control and status register is an 8-bit register
in which .all bits are readable, while only bits 0-4 can be
written. All the bits in this register are also accessible
through the two timer control registers and the timer
status register. The three most significant bits provide
the timer status and indicate if
1. a proper level transition has been detected at P20;
2. a match has occurred between the free-running
counter and output compare register 1; or
3. the free-running counter has overflowed.
Each ofthe three events can generate an IR02 interrupt
and is controlled by an individual enable bit in the TCSR.

inhibited ETOI is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($18).
Bit 3 Enable Output Compare Interrupt 1 - When set,
an IR02 interrupt will be generated .when output
compare flag 1 is set; when clear,the interrupt is
inhibited. EOCI1 is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($18).
Bit 4 Enable Output Capture Interrupt 1 :..- When set,
anlR02 interrupt will be 'generated when input
capture flag 1 is set; when clear, the interrupt is
inhibited. EICI1 is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($18).

Bit 5 Timer Overflow Flag - The TOF is set when the
counter contains all ones ($FFFF). It is cleared by
reading the TCSR or the TSR (with TOF set) and
the counter high byte ($09), or during reset. Refer
to TIMER STATUS REGISTER (TSR) ($19).

Bit6 Output Compare Flag 1 - OCF1 is set when output
compare register 1 matches the free-running
counter. OCF1 is cleared by reading the TCSR or
the TSR (with OCF1 set) and then writing to output
compare register 1 ($OB or SOC), or during reset.
Refer to TIMER STATUS REGISTER (TSR) ($19).

Bit 7 Input Capture Flag - ICF1 is set to indicate that a
proper level transition has occurred; it is cleared
by reading the TCSR or the TSR (with ICF1 set) and
the input capture register 1 high byte ($00), or
during reset. Refer to TIMER STATUS REGISTER
(TSR) ($19).
Timer Control Register 1 (TCR1) ($17)

TIMER CONTROL AND STATUS REGISTER
6543210
ICFI I OCFI I TOF I EICII I EOCII I ETOI IIEDGI I OLVLI I

$08

Bit 0 Output Level 1 - OLVL 1 is clocked to output level
register 1 by a successful output compare and will
appear at P21 if bit 1 of the port 2 data direction
register is set and the OE1 control bit in timer control register 1 is set. OLVL 1 and output level register 1 are cleared during reset. Refer to TIMER
CONTROL REGISTER 1 (TCR1) ($17).
Bit 1 Input Edge 1 -IEOG1 is cleared during reset and
controls which level transition on P20 will trigger
a counter transfer to input capture register 1:
IEOG 1 = 0 transfer on a negative-edge
IEOG1 ~ 1 transfer on a positive-edge
Refer to TIMER CONTROL REGISTER 1 (TCR1) ($17).
Bit 2 Enable Timer Overflow Interrupt - When set, an
IR02 interrupt will be gel")erated when the timer
overflow flag is set; when clear, the interrupt is

Timer control register 1 is an 8-bit read/write register
containing the control bits for interfacing the output compare and input capture registers to the corresponding II
pins.

o

TIMER CONTROL REGISTER 1
5

OE3

3

2

I

0
$17

Bit 0 Output Level 1 - OLVL 1 is clocked to output level
register 1 by a successful output compare and will
appear at P21 if bit 1 of the port 2 data direction
register is set and the OE1 control bit is set. OLVL1
and output level register 1 are cleared during reset.
Refer to TIMER CONTROL AND STATUS REGISTER (TCSR) ($08).
Bit 1 Output Level 2 - OLVL2 is clocked to output level
register 2 by a successful output compare and will
appear at P11 if bit 1 of port 1 data direction register is set and the OE2 control bit is set. OLVL2
and output level register.2 are cleared during reset.

MOTOROLA MICROPROCESSOR DATA

3-155

4

OE2 I OEI IIEDG211EDGI I oLVl3 I oLVL2 I OLVLl I

I

Me6801 U4/6803U4

Bit 2 Output Level 3 - .OLVl3 is clocked tc) output level
register 3 by a successful output compare and will
appear at P12 if bit 2 of port 1 data direction register is set and the OE3 control bit is set. OLVL3
and o~tput level register 3 are cleared during reset.
Bit 3 Input Edge 1 -IEDG1 is cleared during reset and
controls which level transition on P20 will trigger
a counter transfer to inut capture register 1.
IEDG 1 = transfer on a negative edge
IEDG1 = 1 transfer on a positive edge
Refer to TIMER CONTROL AND STATUS REGISTER (TCSR) ($08).

overflow flag is set; when dear, the interrupt in~
hibited. ETOI is cleared during rest. Refer to TIMER
CONTROL AND STATUS REGISTER (TCSR) ($08).
Bit 3

Enable Ou~put Compare Interrupt 1 -When set,
an IR02 interrupt will be generated when the output compare flag 1 is set; when clear, the interrupt is inhibited. EOCI1 is cleared during reset.
Refer to TIMER CONTROL AND STATUS REG·
ISTER (TCSR) ($08).

Bit 4

Enable Output Compare Interrupt 2 - When set,
an IR02 interrupt will be generated when the output compare flag 2 is set; when clear, the interrupt is inhibited. EOCI2 is cleared during reset.

Bit 5

Enable Output Compare Interrupt 3 - When set,
an IR02interrupt will be generated when the output compare flag 3 is set; when clear, the interrupt is inhibited. EOCI3 is cleared during reset.

Bit 6

Enable Input Capture Interrupt 1 - When set, an
IR02 interrupt will be generated when the input
capture flag 1 is set; when clear, the interrupt is
inhibited. EICI1 is cleared during reset. Refer to
TIMER CONTROL AND STATUS REGISTER (TCSR)
($08).

Bit 7

Enable Input Capture Interrupt 2 - When set, an
IRQ2 interrupt will be generated when the input
capture flag 2 is set; when clear, the interrupt is
inhibited. EICI2 is cleaed during reset.

a

Bit 4 Input Edge 2 - IEDG2 is cleared during reset and
controls which level transition on P10 will trigger
a counter transfer to input capture register 2.
IEDG2 = a transfer on a negative edge
IEDG2 = 1 transfer on a positive edge

I

Bit 5 Output Enable 1 - OE1 is set during reset and
enables the contents of output level register 1 to
be connected to P21 when bit 1 of port 2 data
direction register is set.
OE1 = a port 2 bit 1 data register output
OE1 = 1 output level register 1
Bit 6 Output Enable 2- OE2 is cleared during reset and
enables the contents of output level register 2 to
be connected to P11 when bit 1 of port 1 data
direction register is set.
OE2 = a port 1 bit 1 data reg ister output
OE2 = 1 output level register 2
Bit 7 Output Enable 3,- OE3 is cleared during reset and
enables the contents of output level register 3 to
be connected to P12 when bit 2 of port 1 data
direction register is set
OE3 = a port 1 bit 2 data register output
OE3 = 1 output level register 3

The timer test bits (test and clock) allow the free-running counter to be tested as two separate 8-bit counters
to speed testing.
,TIMER CONTROL REGISTER 2
(Test Modes)
5

Timer Control Register 2 (TCR2) ($18)
Timer control register 2 is an 8-bit read/write register
(except bits and 1), which enables the interrupts associated with the free-running counter, the output compare registers, and the input capture registers. In test
mode 0, two more bits (clock and test) are available for
checking the timer.

a

Bit

a

6

5

4

3

$18

Bits 0-1 Read-Only Bits - When read, these bits return
a value of 1. Refer to TIIMER CONTROL REG·
ISTER 2 (Test Mode).
Bit 2

2

1

0

CLOCK - The CLOCK control bit selects which
half of the 16-bit free-running counter (MSB or
LSB) should be clocked with E. The CLOCK bit is
a read/write bit only in mode a and is set during
reset.

CLOCK = 1 - Only the eight least-significant bits
ofthe free-running counter run when TEST = O.

2

1 EICI2 'I EICllj EDCI31 EDCI21 EDClll ETDll ' 1

3

CLOCK = a- Only the eight most-significant bits
of the free-running counter run with TEST = O.

TIMER CONTROL REGISTER 2
(Nontest Modes)
7

4

EICI2 1 EICll 1 EDCI31 EDCI21 EDCll 1 HDI 1 TEST 1CLOCK 1 $18

Enable Timer Overflow Interrupt - When set, an
IRQ2 interrupt will be generated when the timer

Bit 1

TEST -The TEST control bit enables the timer
test mode. TEST is a read/write bit in mode a and
is set during reset.
TEST=O - Timer test mode enabled:
a) The timer LSB latch is transparent, which
allows the LSB to be read independently of
the MSB.

MOTOROLA MICROPROCESSOR DATA

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Me6S01 U4/6S03U4

b) Either the MSB or the LSB of the timer is
clocked by E, as defined by the CLOCK bit.
TEST = 1 - Timer test mode disabled.
Bits 2-7 See TIMER CONTROL REGISTER 2 (Nontest
Modes). (These bits function the same as in the
nontest modes.)
Timer Status Register (TSR) ($19)
The timer status register is an 8-bit read-only register
which contains the flags associated with the free-running
counter, the output compare registers, and the input capture registers.

SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous SCI is provided with two
data formats and a variety of rates. The SCI transmitter
and receiver are functionally independent but use the
same data format and bit rate. Serial data formats include
standard mark/space (NRZ) and biphase; both provide
one start bit, eight data bits, and one stop bit. "Baud"
and "bit rate" are used synonymously in the following
descri ptio n.
WAKE-UP FEATURE

Bits 0-1 Not used.

In a typical serial loop multiprocessor configuration,
the software protocol will usually identify the addressee(s) at the begining of the message. To permit uninterested MPUs to ignore the remainder of the message,
wake-up feature is included whereby all further SCI receiver flag (and interrupt) processing can be inhibited
until its data line goes idle. An SCI receiver is re-enabled
by an idle string of eleven consecutive ones or during
reset. Software must provide for the required idle string
between consecutive messages· and must prevent it within
messages.

Bit 2

PROGRAMMABLE OPTIONS

TIMER STATUS REGISTER
5
ICF2

ICFl

4

3

I OCF3 I OCF2 I OCFl I TOF

$19

Timer Overflow Flag - The TOF is set when the
counter contais all ones ($FFFF). It is cleared by
reading the TSR or the TCSR (with TOF set) and
then the counter high byte ($09), or during reset.
Refer to TIMER CONTROL AND STATUS REGISTER (TCSR) ($08).

Bit 3

Output Compare Flag 1 - OCF1 is set when output compare register 1 matches the free-running
counter. OCF1 is cleared by reading the TSR or
the TCSR (with OCF1 set) and then writing to
output compare register 1 ($OB or $OC), or during
reset. Refer''to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($08).

Bit 4

Output Compare Flag.2 - OCF2is set when output compare register 2 matches the free-running
counter. OCF2 is cleared by reading the TSR (with
OCF2 set) and then writing to output compare
register 2 ($1A or $1B), orduring reset.

Bit 5

Output Compare Flag 3 - OCF3 is set when output compare register 3 matches the free-runing
counter. OCF3 is cleared by reading the TSR (with
OCF3 set) and then writing to output compare
register:3 ($1C or $1,Q), or during reset.

Bit 6

Bit 7

Input Capture Flag 1 -ICF1 is set to indicate that
a proper level transition has occurred; it is cleared
by reading the TSR or the TCSR (with ICF1 set)
and the input capture register 1 high byte ($00),
or during reset. Refer to TIMER CONTROL AND
STATUS REGISTER (TCSR) ($08).
Input Capture Flag 2 - ICF2 is set to indicate that
a proper level transition has occurred; it is cleared
by reading the TSR (with ICF2 set) and the input
capture register 2 high bYte ($1 E), or during reset.

The
•
•
•

following featues of the SCI are programmable:
Format: standard mark/space (NRZ) or biphase
Clock: external or internal bit rate clock
Baud: one of eight per E clock frequency or external clock ( x 8 desired baud)
• Wake-Up Feature: enabled or disabled
• Interrupt Requests: enabled individually for transmitter and receiver
• Clock Output: ihternal bit rate clock enabled or
disabled to P22

SERIAL COMMUNICATIONS REGISTERS
The SCI includes four addressable registers as depicted
in Figure 22. It is controlled by the rate and mode control
register and the transmit/receive control and status register. Data are transmitted and received utilizing a writeonly transmit register and a read-only receive register.
The shift registes are not accessible to software.
Rate and Mode Control Register (RMCR) ($10)
The rate and mode control register controls the SCI bit
rate, format, clock source, and, under certain conditions,
the configuration of P22. The register consists of five
write-only bits which are cleared during reset. The two
least-significant bits! in conjunction with bit 7, control the
bit rate of the internal clock, andthe remaining two bits
control the format and clock source.
RATE AND MODE CONTROL REGISTER
6543210

EBE

I

X

I

X

CCI

I cco I SSI I sso r

$10

Bit 1: Bit 0 SS1 :SSO Speed Select - These two bitsselect
the baud when using the internal clock. Eight

MOTOROLA MICROPROCESSOR DATA

3-157

I xl

II

Me6S01 U4/6S03U4

Bit7

I I

Rate and Mode Control Register

I

Bit 0

I Icco I Isso I
CC1

EBE

SS1

$10

Transmit/Receive Control and Status Register

RDRF IORFE FDREI RIE

I I
RE

TIEl TE

I I
wu

$11

Receive Data Register

10

I

12

Transmit Data Register

Figure 22. SCI Registers

rates may be selected (in conjunction with bit
7) which are a function of the MCU input fre-

quency. Table 6 lists bit times and rates for
three selected MCUfrequencies.
Bit 3:Bit 2 CC1 :CCO Clock Control and Format SelectThese two bits control the format and select
the serial clock source. If CC1 is set, the DDR
value for P22 is forced to the complement of
CCO and cannot be altered until CC1 is cleared.
If CC1 is cleared after having been set, its DDR
value is unchanged. Table 7 defines the formats, clock source, and use of P22.
Bits 4-6

of50% (± 10%). If CC1 :CCO= 10, the internal bitrate clock
is provided at P22 regardless of the values for TE or RE.
NOTE
The source of SCI internal bit rate clock ,is the
timer free-running counter. An MPU write to the
counter in mode 0 can disturb serial operations.
Transmit/Receive Control and Status Register (TRCSR)
($11)
The transmit/receive control and status register controls the transmitter, receiver, wake-up feature, and two
individual interrrupts, and monitors the status of serial
operations. All eight bits are readable; bits 0 to 4 are also
writable. The register is initialized to $20 by RESET.

Not used.
TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER
EBE Enhanced Baud Enable - EBE selects the
standard MC6801 baud rates when clear and
the additional baud rates when set (Table 6).
Thi,s bit is cleared by reset and is a write-only
control h i t . '
,
Bit 1: Bit 1 EBE = 0 standard MC6801 baud rates
Bit 1: Bit 1 EBE = 1 additional baud rates

Bit 7

If bqthCC1 and CCO are set, an external TTL-compatible
clock must be connected to
at eight times (8 x ) the
desired bit rate, but not greater than E, with a duty cycle

pn

76543210

I RDRF I ORFE I TORE I RIE I RE I TIE I TE I WU I

Bit 0 Wake-Up on Idle Line - When set, WU enables the
wake-up function; it is cleared by eleven consecutive ones or during reset. WU will not be ,set if the
line is idle. Refer to WAKE-UP FEATURE.
Bit 1 Transmit, Enable - When set, P24 DDR bit is set,
cannot be changed, and will remain set if TE is

MOTOROLAMICROPROCESSQR DATA

3-158

$11

Me6S01 U4/6S03U4

Table 6. SCI Bit Times and Rates
4fo EBE

SS1:SS0
E

2;4576 MHz

4.0 MHz

4.9152 MHz

614.4 kHz
Baud
Time

1.0 MHz
Baud
Time

1.2288 MHz
Time
Baud

0

0

0

+16

38400.0

26,,5

62500.0

16.0,,5

76800.0

\13.0 psi

0

0

1

+128

4800.0

208.3,,5

7812.5

128.0,,5

9600.0

104.2,,5

0

1

0

+ 1024

600.0

1.67 ms

976.6

1.024 ms

1200.0

833.3 pS

0

1

1

+4096

150.0

6.67 ms

244.1

4.096 ms

300.0

3.33 ms

1

0

0

+64

9600.0

104.2 Its

15625.0

64 Its

19200.0

52.0 Its

1

0

1

+256

2400.0

416.6"s

3906.3

256 ItS

4800.0

208.3 Its

1

1

0

+512

1200.0

833.3 Its

1953.1

512 Its

2400.0

416.6 ItS

1

1

1

+2048

300.0

3.33 ms

488.3

2.05ms

600.0

76800.0

13,0 Its

125000.0

8,0 Its

153600.0

External (P22) *

1.67ms'
6.5 Its

* Using maximum clock rate
has occurred; otherwise, a framing error has been
detected. Oata are not transferred to the receive
data register in an overrun condition. Unframed
data causing a framing error are transferred to the
receive data register. However, subsequent data
transfer is blocked until the framing error flag is
cleared. ORFE is cleared by reading the TRCSR (with
ORFE set) then the receive data register, or during
reset.

Table 7. SCI Format and Clock Source Control

CC1:CCO

Format

Clock
Source

'Port 2
Bit 2

00

Biphase

Internal

Not Used

01

NRZ

Internal

Not Used

10

NRZ

Internal

Output

"

NRZ

External

Input

Bit 7 Receive ,Data Register Full- RDRF is set when the
input serial shift register is transferred to the receive
data register, or during reset.

subsequently cl~ared. When TE is changed from
clear to set, the transmitter is connected to P24and
a preamble of nine consecutive ones is transmitted.
TE is cleared during reset.

SERIAL OPERATIONS

Bit2 Transmit Interrupt Enable - When set, an IR02 is
set; when clear, the interrupt is inhibited. TE is
cleared duri ng reset.
Bit 3 Receive Enable - When set, the P23 OOR bit is
cleared, cannot be changed, and VIi,ill remain clear
if RE is subsequently cleared. While RE is set, the
SCI receiver is enabled. RE is cleared during reset.
Bit 4 Receiver Interrupt Enable - When set, an IR02
interrupt is enabled when RORF and/or ORFE is set;
when clear, the interrupt is inhibited. RIE is cleared
during reset.
Bit 5 Transmit Data Register Empty -".' TORE is set when
the transmit data register is transferred to the output serial shift register or during reset. It is cleared
by reading the TRCSR (with TORE set) and then
writing to the transmit data register. Additional data
will be transmitted only if TORE has been cleared.
Bit 6 Overrun Framing Error -c' If set, ORFE indicates
either an overrun or framing error. An overrun is
a new byte ready to transfer to the receiver data
register with RORF still set. A receiver framing error
has occurred when the byte boundaries of the bit
stream are not synchronized to the bit counter. An
overrun can be distinguished from a framing error
by the state of RORF: if RORF is set, then an overrun

The SCI is initialized by writing control bytes first to
the rate and mode control register and then to the transmit/receive control and status register. When TE is set,
the output ofthe transmit serial shift register is connected
to P24, and serial output is initiated by transmitting a 9bit preambie of ones.
At this point, one of two situations exists: 1)if the
transmit data regist.er is empty ,(TORE = 1), a continuous
string of ones will be sent indicating an idle line; or 2) if
a byte has been written to the transmit data register
(TORE = 0), it will be transferred to the output serial shift
register (synchronized with the bit rate clock), TORE will
be set, and transmission will begin.
The start bit (0), eight qata bits (beginning with bit 0),
and a stop bit (1) will be transmitted. If TORE is still, set
when the next byte transfer occurs, ones will be sent until
more data is provided. In biphase format, the output toggles at the start of each bit and at half-bit time when a
one is sent. Receive operation is controlled by RE, which
configures P23 as an input and enables the receiver. SCI
data formats are illustrated in Figure 23.

INSTRUCTION SET
The MC6S01 U4/MC6803U4 is cjirectly source compatible with the MC6801 and upward source and object code
compatible with the MC6800. Execution times of key instructions have been reduced, and several instructions
have been added, including a hardware mUltiply. A list

MOTOROLA MICROPROCESSOR DATA
3-159

II

MC6S01 U4/6S03U4

Output
Clock

NRZ
Format

:

1.

'

Biphase
Format
Bit

Idle Start

0

3

4

Stop

Data 01001101 ($40)

Figure 23. SCI Data Formats

II

of new operations added to the Me6800 instruction set
is shown in Table 1.
In addition,two special opcodes, 4E and 5E, are provided for test purposes. These opcodes force the program
counter to increment like a 16-bit counter, causing address lines used in the expanded modes to increment
until the device is reset. These opcodes have no mne~
monics.
The coding of the first (or only) byte corresponding to
an executable instruction is sufficient to identify the instruction and the addressing mode. The hexadecimal
equivalents of the binary codes, which result from the
translation of the 82 instructions in all valid modes of
addressing, are shown in Table 8. There are 220 valid
machine codes, 34 unassigned codes, and 2 codes reserved for test purposes.

PROGRAMMING MODEL
A programming model for the Me6801U4/Me6803U4
is shown in Figure 8. Accumulator A can be concatenated
with accumulator 8 and jointly referred to as accumulator
D where A is the most-significant byte. Any operation
that modifies the double accumulator will also modify
accumulators A and/or 8. Other registerS are defined as
follows:

Program Counter
The program counter is a 16-bit register which always
points to the next instruction.
Stack Pointer
The stack pointer is a 16-bit register which contains the
address of the next available location in a pushdown/
pullup (LIFO) queue. The stack resides in random-access
memory at a location defined by the programmer.
Index Register
The index register is a 16-bit register that can be used
to store data or provide an address for the indexed mode
of addressing.

arithmetic logic unit (ALU). They can also be concatenated and referred to as the D (double) accumulator.

Condition Code Register
The condition code register indicates the results of an
instruction and includes the following five condition bits:
negative (N)' zero (Z), overflow (V)' carry/borrow from
MS8 (e), and half carry from bit 3 (H). These bits are
testable by the conditional branch instructions. 8it 4 is
the interrupt mask (I bit) and inhibits all maskable interrupts when set. The two unused bits, 86 and 87, are read
as ones.

ADDRESSING MODES
Six addressing modes can be used to reference memory. A summary of addressing modes for all instructions
is presented in Table 9,10,11, and 12; execution times
are provided in E cycles. Instruction execution times are
summarized in Table 13. With an input frequency of 4
MHz, one E cycle is equivalent to one microsecond. A
cycle-by-cycle description of bus activity for each instruction is provided in Table 14; descriptions of selected instructions are shown in Figure 24.

Immediate Addressing
The operand or "immediate byte(s)" is contained in the
following byte(s) of the instruction where the number of
bytes matches the size of the register. These are two- or
th ree-byte instructions.
Direct Address
The least-significant byte of the operand address is
contained in the second byte of the instruction, and the
most-significant byte is assumed to be $00. Direct addressing allows the user to access $00 through $FF, using
two-byte instructions, and execution time is reduced by
eliminating the additional memory access. In most applications, the 256-byte area is reserved for frequently
referenced data.

Extended Addressing
Accumulators
The MPU contains two 8-bit accumulators, A and 8,
which are used to store operands and results from the

The second and third bytes of the instruction contain
the absolute address of the operand. These are threebyte instructions.

MOTOROLA MICROPROCESSOR DATA
3-160,

Me6S01 U4/6S03U4

Table 8. CPU Instruction Map
OP

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
2B
29
2A
2B
2C
2D
2E
2F
30
31
32
33

MNEM

Nap

MODE

INHER

LSRD
ASLD
TAP
TPA
INX
DEX
CLV
SEV
CLC
SEC
CLI
SEI
SBA
CBA

2

3
3
2
2
3
3
2
2
2
2
2
2
2
2

TAB
TBA

,
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2

1
1

DAA

INHER

2

1

ABA

INHER

2

1

BRA
BRN
BHI
BLS
BCC
BCS
BNE
BEO
BVC
BVS
BPL
BMI
BGE
BLT
BGT
BLE
TSX
INS
PULA
PULB

REL

REL
INHER

~

3
3
3
3
3
3 .
3
3
3
3
3
3
3
3
3
3
3
3
4
4

2
2

OP

MNEM

MODE

-

34

DES
TXS
PSHA
PSHB
PULX
RTS
ABX
RTI
PSHX
MUL
WAI
SWI
NEGA

INHER

3
3
3
3
5
5

35
36
37

38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55

2

56

2
2

57

L

2
2
2
2

2
2
2
2
2
2
1
1
1
1

56
59
5A
5B
5C
5D
5E
5F
60
61
62
63

84

10
4
10
9
12
2

1
1
1
1
1
1
1
1
1
1
1
1
1

.

2
2

1
1

RORA
ASRA
ASLA
ROLA
DECA

2
2
2
2
2

1
1
1
1
1

INCA
TSTA
T
CLRA
NEGB

2
2

1
1

2
2

1
1

67

3

COMA
LSRA

COMB
LSRB

2
2

RORB
ASRB
ASLB
ROLB
DECB
INCB
TSTB
T
CLRB
NEG

2
2
2
2
2

INHER
INDXD

1
1
1
1
1
1
1

2
2

1
1

2
6

1
2

OP

MNEM

MODE

68

ASL
ROL
DEC

INDXD

69
6A
6B
6C
6D
6E
6F
70
71

COM
LSR
ROR
ASR

1

INDXD

NOTES:
1. Addressing Modes:
IN HER = Inherent INDXD = Indexed
REL = Relative
EXTND = Extended

6
6
6
6

2
2
2
2

INC
TST
JMP
CLR
NEG

84
85
86
87

6
·6

ROR
ASR
ASL
ROL
DEC

5

INC
TST
JMP
CLR
SUBA
CMPA
S8CA
SUBD
ANDA
BITA
LDAA
EORA
"'DCA
ORAA
ADDA
CPX
BSR
LDS

99
9A
9B

6
6
3
6
6

I'

89
BA
BB
BC
8D
BE
8F
90
91
92
93
94

98

6
6
6

COM
LSR

68

97

-

1

INDXD
EXTND

72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83

95
96

65

66

,

SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA
STAA
EORA
ADCA
ORAA
ADDA

6
6
6
6

EXTNO
IMMED

6
6
3
6

2
2
2
4

2
2
2
2
2
2

,

2

IMMED
REL
IMMED
DIR

4

6
3
3

3
3
5
3

3
3
3
3
3
3
3

,

OP

MNEM

9C
9D
9E
9F
2 AO
2 A1
2 A2
2 A3
3 A4
A5
A6
3 A7
3 A8
A9
3 AA
3 AB
3 AC
3 AD
3 AE
AF
3 BO
3 B1
3 B2
3 B3
2 B4
2 B5
2 B6
3 B7
2 B8
2 B9
2 BA
BB
2 BC
2 BD
2 BE
2 BF
3 CO
2 C1
3 C2
C3
2 C4
2 C5
2 C6
2 C7
2 CB
2 C9
2 CA
2 CB
2 CC
2 CD
2 CE
2 CF

CPX
JS·R
LDS
STS
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA
STAA
EORA
ADCA
ORAA
ADDA
CPX
JSR
LDS
STS
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA
STAA
EORA
ADCA
ORAA
ADDA
CPX
JSR
LDS
STS
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB

2
2
2

MODE

DIR

~

DIR
INDXD
I

INDXD
EXTND

EXTND
IMMED

I'

5
5
4
4
4
4
4
6
4
4
4
4
4
4
4
4
6
6
5
5
4
4
4
6
4
4
4
4
4
4
4
4
6
6
5
5
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2

2
4

3

2

2

2

2

2

2

2
2
2
3
IMMED

,

2
2

2

EORB
ADCB
OHAB
ADDB
LDD
LDX

-

3

2
2
2
2
3
3

OP

MNEM

DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3

SUBB
CMPB
SBCB
ADDD
ANDB
BIT8
LDAB
STAB
EORB
ADCB
ORAB
ADDB
LDD
STD
LDX
STX
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB
STAB
EORB
ADCB
ORAB
ADDB
LOD
STD
LOX
STX
SUBB
CMPB
S8CB
ADDD
ANDB
BITB
LDAB
STAB
EORB
AOCB
aRAB
ADDB
LOD
STC

F4

F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF

-*

MODE

-

I

DIR

3

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

3

DIR
INDXD
I

3
5
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
6
4
4
4
4
4
4
4
4
5
5
5
5

INDXD
EXTND

4

~

4

4
4

3

4

6
4
4

4
4
4
4

5
5
EXTND

2
2
2
3
3
3
3
3
3
3
3
3
3
<

o.

"

3

_ c'NED OP CODE

IMMED = Immediate
DIR = Direct

2. Unassigned opcodes are indicated by"·" and should not be executed.
3. Codes marked by "T" force the PC to function as a 16-bit counter.

Indexed Addressing

The unsigned offset contained in the second byte of
the instruction is added with carry to the index register
and is used to reference memory without .changing the
index register. These are two-byte instructions.
Inherent Addressing

The operand(s) is a register, and no memory reference
is required. These are single-byte instructions.
Relative Addressing

Relative addressing is used only for branch instructions. If the branch condition is true, the program counter

is overwritten with the sum of signed single-byte displacement in the second byte of the instruction and the
current program counter. This provides a branch range
of - 126 to + 129 bytes from the first byte of the instruction. These are two-byte instructions.

SUMMARY OF CYCLE-BY-CYCLE OPERATION
Table 14 provides a detailed description of the information present on the address bus, data bus, and the
read/write (RrVV) line during each cycle of instruction.
The information is useful in comparing actual results
with expected results during debug of both software and

MOTOROLA MICROPROCESSOR DATA
3-161

Me6801 U4/6803U4

Table 9. Index Register and Stack Manipulation Instructions
Condition Codes

,

Immed
Pointer Operetions

MNEM Op 8C 4

Direct
Op -

3 9C 5

,

Index

Op 2 AC 6

,

Op -

,

2 BC 6

3

Extnd

Op -

,

Inherent

Boolean/
Arithmetic Oll8ration

CPX
DEX

09 3

1 X-1-X

Decrement Stack Pointer

DES
INX

34 3
00 3

1 SP-1-SP

Increment Index Register
Increment Stack Pointer

INS

31

1 1 SP+1-SP

Load Index Register

LOX

CE 3

3 DE 4

2 EE 5

2 FE 5

3

M-XH,(M+1)- X l

Load Stack Pointer

LOS

8E 3

3 9E 4

2 AE 5

3

M-SPH,(M+1)-SPL

Store Index Register

STX

OF 4

2 EF 5

2 BE 5
2 FF 5

3

XH-M,XL -(M+1)

Store Stack Pointer

STS

9F 4

2 AF 5

2 BF 5

3

Index Reg -

TXS

3

1 X+1-X

Stack Pntr-Index Register

TSX

Add

ABX

3A 3

1 B+X-X

Push Data

PSHX

3C 4

1 XL -MSp,SP 1-SP
XH - MSp,SP- 1 - SP

Pull Data

PULX

38 5

1 SP+ 1-SP,MSp- XH
SP+1-SP,MSP-XL

I

I

3 2 1 0
Z V C

N

·· ·· · · ·
·· ·· ·· · ·· ··
··· ··· · · · ··
··· ··· · · · ···
·· ·· ·· ·· ·· ··
······
······
R· •
R

R

SPH-M,SPL -(M+ 1)
1 X-1-SP

35 3
30 3

Stack Pointer

4

H

I 1 I J
f

X-M:M+1

Compare Index Register
Decrement Index Register

5

1 SP+ 1-X

R

Table 10. Accumulator and Memory Instructions (Sheet 1 of 2)
Condition Codes
Accumulator and
Memory Operations

,

Immed
MNEM Op

-

Direct
Op -

,

Index
Op -

,

,

Op -

,

Extend
Op -

Inher

Boolean
Expression

Add Accumulators

ABA

1B 2

1 A+B-A

Add B to X

ABX

3A 3

1 OO:B+X-X

Add with Carry
Add

2

2 99 3

2 A9 4

ADCB C9 2

2 09 3

2 E9 4

2 B9 4
2 F9 4

3

B+M+C-B

2

2 AB 4

2 BB 4

3

A+M-A
B+M-A

ADCA 89

ADDB CB 2

2 9B 3
2 DB 3

3

ADDD C3 4

3 03 5

2 EB 4
2 E3 6

2 F8 4

Add Double

2 F3 6

3

D+M:M+1-D

And

ANDA 84

2

2 94 3

2 A4 4

2 B4 4

3

A.M-A

ANDB C4 2

2 D4 3

2 E4 4

2 F4 4

3

B.M-B

68 6

2 78 6

3

Shift Left, Arithmetic

Shift Left Double
Shift Right, Arithmetic

Bit Test

ADDA 8B

ASL
ASLA

48 2

1

ASLB

58 2

1

05 3

1

ASRA

47

2

1

ASRB

57

2

1

ASLD
ASR

67

BITA

85 2

BITB

C5 2

Compare Accumulators

CBA

Clear

CLR

2 95 3
2 05 3

6

2 77 6

3

3

A.M

2 E5 4

2 F5 4

3

B.M

6F 6

2 7F 6

3

CLRA
CLRB
Compare
1's Complement

CMPA 81

2

CMPB C1

2

COM

2 91 3
2 01 3

b7

2 B5 4

2 A1 4

2 B1 4

11

2

1 A-B

4F

2

1 OO-A

5F

2

1 OO-B

OO-M

A-M

3

2 E1 4

2 F1 4

3

B-M

63 6

2 73 6

3

M-M

COMA

43 2
53 2

COMB

1 A-A
1 B-B

MOTOROLA MICROPROCESSOR DATA
3-162

2

N

Z V

0
C

· ·· · · · ·
···
·· ··
·· ·· ··
·· ··
·· ··
·· ·· tt tt tt
·· ·· 1 1 ··
·· ··
·· ··
·· ·· t t t t
·· ·· t t
·· t t
R

-0

bO

qilli IIII-@]

2 A5 4

3

I

R

@l-illllllll
b7

4

H

f • f f f f

A+M+C-A

3

1

5

bO

R

f f R
1 1 I 1

R

S

R

R

R

S

R

R

R

S

R

R

f t f t

t t

R

S

R

S

R

S

Me6S01 U4/6S03U4

Table 10. Accumulator and Memory Instructions (Sheet 2 of 2)
Condition Codes
Accumulator and
Memory Operations

Immed
MNEM Op

Decimal Adjust, A

DAA

Decrement

DEC

Exclusive O,R
Increment

Load Accumulators
Load Double
Logical Shift, Left

Shift Right, Logical

-

Direct

# Op -

Index

Extend

Inher

# Op -

# Op -

# Op 19 2

6A 6

2 7A 6

3

#

1 Adj binary sum to BCD
M-1-M

DECA

4A 2

1 A-1-A

DECB

5A 2

1 B-1-B

2
EORB C8 2
EORA 88

2 98 3
2 D8 3

2 A8 4
2 E8 4

INC

6C 6

2 B8 4
2 F8 4
2 7C 6

3

A$M-A

3

B$M-B

3

M+1-M

INCA

4C

2

1 A+1-A

INCB

5C

2

1 B+1-B

2
LDAB C6 2

LDAA 88
LDD

CC 3

2 96 3
2 D6 3

2 A6 4
2 E6 4

2 B6 4

3

M-A

2

F6 4

3

M-B

3 DC 4

2 EC 5

2 FC 5

3

M:M+1-D

2

3

LSL

68 6

78

6

LSLA

48 2

LSLB

58 2

1

LSLD

05

3

2

LSRA

44

2

1

LSRB

54

2

1
1

64 6

LSR

2

74

6

1

3

b7

b7

04 ,3

2's Complement (Negate)

NEG

No Operation
Inclusive OR
Push Data
Pull Data

2

50

2

1 00- B-B

NOP

01

2

1

2 9A 3

2 AA 4

2 BA 4

3

A+M-A

ORAB CA 2

2 DA 3

2 EA 4

2 FA 4

3

B+M-B

PSHA

36

,3

1

PSHB

37

3

1

B-Stack

PULA

32

4

1

St'ack-A

33

4

1

Stack -

49

2

1

59

2

1

RORA

46

2

1

RORB

56

2

1

SBA

10

2

1 A- B-A

696

2

79

6

ROLB

Subtract Accumulator
Subiract With Carry
Store Accumulators

Subtract
Subtract Double
Transfer Accumulator
Test, Zero or Minus

ROR

66 6

SBCA 82

2

2

SBCB C2

2

2 D2 3

92

3

2

76

6

3

B

@] -111111111-f1
to
b7

E}-IIIIIIIII-@
hi

2

B2 4

3

E2

4

2

F2

4

3

A-M-C-A
8-M-C-B

STAA

97

3

2 A7

4

2

B7 4

3

A-M

STAB

D7 3

2 E7

4

2

F7

4

3

B-M

STD

DD 4

2 ED 5

2 FD 5

3

D-M M+ 1
A-M-A

SUBA 80

2

2 90 3

2 AO 4

2 BO 4

3

SUBB CO

2

2 DO 3

2

EO 4

2

FO 4

3

B- M-B

SUBD 83

4

3

2 A3 6

2

B3 6

3

D-cMM+l-D

93

5

TAB

16

2

1 A-B

TBA

17

2

1 B-A

TST

6D

6

2 7D

6

M- 00

3

TSTA

4D

2

1 A - 00

TSTB

5D

2

1 B - 00

The condition code register notes are listed after Table 12

MOTOROLA MICROPROCESSOR DATA
3-163,

R
R

R

R

R

A-Stack

2 A2 4
2

,

I I

3

ROLA
Rotate Right

PC+ 1-PC

2

ROL

bO

1 oo-A--A

40

NEGB

PULB
Rotate Left

-0

bO

R

NEGA

ORAA 8A

R

oo-M-M

3

·· ·· tt tt tt ·t
'. t t t
··· ·· tt tt t ···
1 1
··· ··· 11 11 11 ···
1 1 1
··· ··· 11 1t ···
·· ·· 11 11 1 ·1
·· ·· 11 1t 11 11
1 1 1 1
··· ··· 11 11 11
·· ·· 11 11 11
·· ·· ·1 ·1 ·1 11
·· ·· 11 11 11 11
·· ·· · · · ··
·· ·· ·1 ·1 · ··
··· ··· ··· ··· ··· ··
R

0-111111111-@]

3D 10' 1 AxB-D
6

0
C

R

@]-IIIIIIIII

MUL
70

2 1
Z V

R

LSRD
2

N

R

Multiply

606

3

5 4
H I

Boolean
Expression

b(J

t t t t
··· ·· 1t 1t 1t tt
t 1 t t
··· ·· tt 1t tt tt
·· ·· 1t tt tt tt
t t t t
··· ·· tt tt ··
·· · tt tt t t
·· tt tt tt tt
·· · tt tt ·
·· ·· tt tt
· tt
R
R

R

R
R
R

R

R

R

H

R

I

Me6801 U4/6803U4

Table ,11. Jump and Branch Instructions
Condition Code Reg,
Operations

-

-

-

5

-

Branch Always

BRA

20

3

2

BRN

21

3

2

None

Branch If. Carry Clear

BCC

24

3

2

C=O

Branch If Carry Set

BCS

25

3

2

C=l
Z=l

BEG

27

3

2

Branch If 2:Zero

BGE

2C 3

2

NE9v=o

Branch If >Zero

BGT

2E

2

Z+INE9vI=O

Branch If Higher

BHI

22

3

2

C+Z=O

Branch If Higher or Same

BHS

24

3

2

C=O

s Zero

BLE

2F

3

2

Z+IN E9 VI=l

Branch If Carry Set

BLO

25

3

2

C=l

Branch If Lower Or Same

BLS

23

3

2

C+Z=l

Branch If 
E

ABA
ABX
AOC
ADD
AD DO
AND
ASL
ASLO
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
OAA
DEC
DES
DEX
EOR
INC
INS

2
2
4
2

•

••
•
••
••

•
•
•
•
2

••

Q)

~

3
3
5
3

••
••
••
•
••
•3

•
•
•
•

~

"
".=

•

•
•

4
4
6
4
6

•
••
•••
••
•••
6

4

G>
>C

G>

4
4
6
4
6

•
••
6

•
•

••
•
4

•
•
•

••
••

2

•
•
••
•
•
•
4

2

3

•5
•
•••
3
•

•

•
4
6
6

•6
•

•
4
6

•

6

•4
6
6

aI

E

Gi

2
3

••

•
•
2
3
2

•
•

•
••
•••
•
••
••
•

2
2
2
2

G>

a:

••
••

INX
JMP
JSR
LOA
LDO
LOS
LOX
LSL
LSLO
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

•
•
••
•
3
3
3
3
3
3
3

•3
3
3
3
3
3
3
3
3
6
3
3

•

•

2

•
2

•6
•
•4
6

'6

.c

.=

•
6

>

;;

G>

!aI

Q)

~

•
•
•
•
•

•
•

•••
••
••

E

•

•2
2
3
3

•

•
3

"..
G
J(

G

E

0

w

>C

.:"

••
•

••

•

•3

2
3
3
3

••
••
•
••
••
•
••
••
•
•
••
•••
•
•
••
2

2

2
4

•
•
•

••
•
•

MOTOROLA MICROPROCESSOR DATA
3-165

"c:
"!
G>

ti
!

5
3
4
4
4

••
•••
••
3
•
••
•
•••
••
3

•
•
•3
4
4
4

3
5

••
•
•
••
•

••

3
6

6

4

4

5
5
5
6

5
5
5
6

•
••
•
••
••
•
•
•
••
•
6

6

4

6
6

4

4
5
5
5
4
6

•

•
••
•
•
••
6

•
••
•
•••
•
•••
••
•
6

6

4

6
6

4

4

5
5
5
4

6

•••
•
•
•
•
•
6

E
G>

e
.c

G>

.~

aI

.=

Gi

3

••
••
•
••
•

•
••
•
••

2
3
2
3
10
2
2

a:

l·

•
3

4
4

5
2
2
10
5
2

•

•
2
2
2

•
•••
••

12
2
2
2
2
2
3
3
9

••
••
••

I

MC6~01 U4/6803U4

Ta.ble 14. Cycle-By-Cycle Operation (Sheet 1 of 5)
Address Mode and
Instructions

R/W
Line

Data Bus

IMMEDIATE
2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Operand Data

LDS
LDX
LDD

3

1
2

Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Operand Data (High Order Byte)
Operand Data I Low Order Byte)

CPX
SUBD
ADDD

4

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address Bus FFFF

1
1
1
1

Upcode
Operand Data I High Order Byte)
Operand Data (Low Order Byte)
Low By·te of Restart Vector

Opcode Address
Opcode Address + 1
Address of Operand

1
1
1

Opc6de
Address of Operand
Operand Data

Opcode Address
Opcode Address + 1
Destination Address

1
1

0

Opcode
Destination Address
Data from Accumulator

Opcode Address
Opcode Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Opcode
Address of Operand
Operand Data IHigh Order Byte)
Operand Data I Low Order Byte)

1

Opcode
Address of Operand
Register Data I High Order Byte)
Register Data I Low Order Byte)

ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB.

3
1
2

3
4

DIRECT

I

ADC
Il:DD
AND
BIT
CMP

EOR
LDA'
ORA
SBC
SUB

3

1
2

3

STA

3

LDS
LDX
LDD

4

STS
STX
STD

4

1
2

3
1
2

3
4

1
2

3
4

CPX
SUBD
ADDD

5

1
2

3
4

5
JSR

5

1
2

3
4

5

Opcode Address
Opcode Address + 1
Address of Operand
Address of Operand + 1

1

0
0

Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1

Opcode Address
Opcode Address + 1
Subroutine Address
Stack Pointer
S tack POinter - 1

1
1
1

1

0
0

Opcode
Address of Operand
Operand Data I High Order Byte)
Operand Data I Low Order Byte)
Low Byte of Restart Vector
Opcode
Irrelevant Data
First Subroutine Opcode
Return Address I Low Order Byte)
Return Address I High Order Byte)

MOTOROLA MICROPROCESSOR DATA
3-166

Me6801 U4/6803U4

Table 14. Cycle-8y-Cycle Operation (Sheet 2 of 5)
Address Mode and
Instructions
EXTENDED
JMP

3

1

2
3
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

STA

4

1

2
3
4
4

1

2
3
4
LOS
LOX
LDD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

JSR

1

2
3
4
5
1

2
3

LSR
NEG
ROL
ROR
TST*

R/W
Line

Address Bus

6

4
5
1

2
3
4
5
6
6

1

2
3

6

4
5
6
1

2
3
4

5
6

Data Bus

Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

Opcode Address
Opcode Address + 1
Opcode Address+ 2
Address of Operand

1
1
1
1

Opcode
Address of Operand
Address of Operand (Low Order Byte)
Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Destination Address

1
1
1

0

Opcode
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator'

Opcode Address
Opcode Address+ 1
Opcode Address +2
Address of Operand,
Address of Operand+ 1

1
1
1
1
1

Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

1
1
1

Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

0
0
1
1
1
1
1

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address Bus FFFF
Address of Operand

0

Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data

OpcCide Address
Opcode Address + 1.
Opcode Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1
1

Opcode
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Opcode Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer- 1

1
1
1
1

Opcode
Address of Subroutine. (High Order Byte)
Address of Subroutine (Low Order Byte)
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

*TST does not perform the write cycle during the Sixth cycle The sixth cycle

IS

another address

bus~

MOTOROLA MICROPROCESSOR DATA .
3-167

SFFFF

II

MC6801 U4/6803U4

Table 14. Cycle-By-Cycle Operation (Sheet 30t 5)

Address Mode and
Instructions
INDEXED

3

JMP

ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

II

4

4

STA

LDS
LDX
LDD

5

STS
STX
STD

5

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Offset
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1 '
Address Bus FFFF
Index Register Plus Offset

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data

1
2
3
4

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset

1

0

Opcode
Offset
Low Byte of Restart Vector
Operana Data

1
2
3
4

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset+ 1

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data' (Low Order Byte)

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Bytef
Operand Data (Low Order Byte)

1
2
3
4

5
LSR
NEG
ROL
ROR
TST*

6

1
2
3
4

5
6
6

1

2
3
4

5
6
JSR

6

Data Bus

1
2
3
1
2
3
4

5

ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

R/W
Line

Address Bus

1
2
3
4

5
6

Opcode Address
Opcode Address + 1
Address Bus FFFF
In(jexRegister Plus Offset
Address Bus FFFF
Index Register Plus Offset

1
1

0
0
1
1
1
1
1

0

Opcode
Offset
Low Byte of Restart Vector
Currept Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register+ Offset
Index Register+ Offset + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
·Opcode Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer-l

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

* TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= SFFFF.

MOTOROLA MICROPROCESSOR DATA
3-168

Me6801 U4/6803U4

Table 14. Cycle-By-Cycle Operation (Sheet 4 of 5)

Address Mode and
Instructions
INHERENT
ABA
DAA
ASL
DEC
ASR
INC
CBA
LSR
CLC
NEG
CLI
NOP
CLR
ROL
CLV
ROR
COM
SBA
ABX

R/W
Line

Address Bus

Data Bus

2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Opcode of Next Instruction

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

ASLD
LSRD

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

1
2
3

Opcode Address
Opcode Address + 1
Previous Stack Pointer Contents

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

INX
DEX

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PSHA
PSHB

3

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1

0

Opcode
Opcode of Next Instruction
Accumulator Data

TSX

3

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

TXS

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PULA
PULB

4

1
2
3
4

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1

1
1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data
Operand Data from Stack

PSHX

4

1
2
3
4

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer-1

1
1

0
0

Opcode
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)

1
2
3
4
5
1
2
3
4
5

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer + 2
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Opcode
Irrelevant Data
Irrelevant Data
Address of Next Instruction (High Order Byte)
Address of Next Instruction (Low Order Byte)

1
2
3
4
5
6
7

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-1
Stack Pointer- 2
Stack Pointer- 3
Stack Pointer-4
Stack Pointer- 5
Stack Pointer-6

1
1

Opcode
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Cpndition Code Register

SEC
'SEI
SEV
TAB
TAP
TBA
TPA
TST

PULX

5

RTS

5

WAI

9

8
9

0
0
0
0
0
0
0

MOTOROLA MICROPROCESSOR DATA
3-169

Me6801 U4/6803U4

TABLE 14 - .CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5)
Address Mode and
Instructions
INHERENT
MUL

10

1
2
3
4
5
6
7

8
9
RTI

II

10

10
1
2
3
4
5
6
7

8
9
10
SWI

R/W
Line

Address Bus

12

1
2
3
4
5
6
7

8
9
10
11
12

Data Bus

Opcode Address
Opcode Address + 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+ 2
S tack Pointer + 3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer+ 6
Stack Pointer+ 7

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Contents of Condition Code Register from Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order Byte)
Index Register from Stack (Low Order Byte)
Next Instruction Address from Stack (High Order Byte)
Next Instruction Address from Stack (Low Order Byte)

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer-1
S tack Pointer - 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer - 5
S tack Pointer - 6
Stack Pointer-7
Vector Address FFFA (Hex)
Vector Address FFFB (Hex)

1
1
0
0
0

1
1
1

Opcode
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register
Irrelevant Data
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)

Opcode Address
Opcode Address+ 1
Address Buss FFFF

1
1
1

Opcode
Branch Offset
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer-1

1
1
1
1
0
0

Opcode
Branch Offset
Low Byte of Restart Vector
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

a
a
a
a

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

RELATIVE
Bec
BeS
BEQ
BGE
BGT
BSR

BHT
BLE
BLS
BLT
BMI

BNE BLO
BPL BHS
BRA BRN
BVC
BVS

3

1

2
3

6

1
2
3
4

5
6

MOTOROLA MICROPROCESSOR DATA
3-170

SP

JSR, Jump to Subroutine

SWI. Sol_.,owru"

Main Program

E.(;

SP-'

$9D=JSR
Direct

{

Next Main Instr.
K = Direct Address
Main Program

E.(;

3:

INDXD

~

{

Condition Code
SP-5

RTN

$AD=JSR
K=Offset
Next Main Instr.

RTN

I
~ S~f
c)~::=:rn
SP

3:

!! o""CI
~

:::g

o(')

m
CJ)

o:J:I
C

~

ILV

W'i"~lo_"

~

Index Register (XL)

SP

BSR, Branch To Subroutin!'l

SP

¢~

ES;

RTN

I

Stack

Condition Code
-

SP+2

Next Main Insl.

RTN

RTNH

SP

SL= SUbr. Addr.

~

SP-2
SP-l

g

PC

SH= Subr.Addr.

RTS, Return from Subroutine

Index Registe((XH)

$BD=JSR

EXTND

I

AcmltrA.

SP-3

SP+l

Interrupt

~

AcmltrB

SP-4

RTNL

RTI. """,01=

Main Program

s;

n
:J:I

WAI.

RTNL

:J:I

o

Stack

SP.-7

Subroutine

~..

$39=RTS

I Ly/

Stack

SP~rn

SP-l

RTNH

SP

RTNL

~

-...

Stack

SP§8
SP. + 1
RTNH
~

SP+2

AcmltrA

SP+4

Index Register (XH)

SP+5

Index Register (XL)

SP+6

RTNH

SP+7

RTNL

~

JMP, Jump

RTNL

Legend:
RTN = Address of next instruction in Main Program to be executed upon return from subroutine
RTNH = Most significant byte of Return Address
RTNL = Least significant byte of Return Address
. - = Stack Pointer After Execution
K = B-bit Unsigned Value

Figure 24. Special Operations

PC~
INDXD

I

X+ K

I

Next Instruction

AcmltrB

SP+3

Main Program
$7E=JMP

~~f

KH = Next Address
KL = Next Address

K

Next Instruction

~

(")

en
CO

o

~

c:
~

en
o

CO
W

c:
0l:Io

MCG801 U4/6803U4

ORDERING INFORMATION
The following information is required when ordering a
custom MCU. The information maybe transmitted to Motorola using the following media:
MDOS, disk file
PC-DOS disk file (360K)
EPROM(s) Two 2516 or 2716,or a single 2532, ~732,
or MC68701 U4
To initiate a ROM pattern for the MCU; it is necessary to
first contact the local field-service office, sales person, or
Motorola representative.
FLEXIBLE DISKS

II

Several types of flexible disks (MDOS@or PC-DOS disk
file) may be submitted for pattern generation. They should
be programmed with the customer's program, using positive logic sense for address and data. The diskette should
be clearly labeled with the customer's name, date, project
or product name, and the filename containing the pattern.
In addition to the program pattern, a file cpntaining the
program source code listing can be included. This data
will be kept confidential and used to expedite the process
in case of any difficulty with the pattern file.

single 2532 or 2732 type EPROM, or an MC68701 U4 can
be submitted for pattern generation. The EPROM is programmed with the customer program, using positive logic
sense for address and data. Submissions on two EPROMs
must be clearly marked. All unused bytes, including the
user's space, must be set to zero.
Whether the MC6801 U4 MCU ROM pattern is submitted on a single 25320r 2732 type EPROM, an MC68701 U4,
or on two 2516 or 2716 type EPROMs, memory map addressing is one-for-one. When using a single 2532 or 2732
EPROM, the ROM pattern to be copied runs from EPROM
address $000 to$FFF. If an MC68701 U4 is used, the ROM
map runs from $FOOO to $FFFF. If a pair of 2516 or 2716
type EPROMs is used, then they must be clearly marked;
the data-space ROM runs from EPROM address $000 to
$7FF, and the program-space ROM from $7FF to $FFF.
For shipment to Motorola, EPROMs should be placed
in a conductive IC carrier and packed securely. Styrofoam
is not acceptable for shipment.

MOOS Disk File

MDOS is Motorola's disk operating system available
on the EXORciser development system. The disk media
submitted must be a single-sided, single-density, 8-inch,
MOOS-compatible floppy diskette. The diskette must
contain the minimum set of MDOS system files in addition to the pattern file.
The .LO output of the M6801 cross assembler should
befurnished. In addition, the file must be produced using
the ROLLOUT command, so. that it contains the absolute
image of the M6801 memory. The entire memory image
of both program and data space must be included. All
unused bytes, including those in the user space, must be
set to logic zero.

PC-DOS Disk File
PC-DOS is IBM® personal computer disk operating system. Submitted disk media must be standard-density
(360K), double-sided, 5-1/4-inch-compatible floppy diskette. The diskette must contain the object file code in
Motorola's S-record format; The S-record format is a
chracter-based object file format generated by M6801
cross assemblers and linkers on IBM PC-style machines.
EPROMS

Two K of EPROM are necessary to contain the entire
MC6801U4 program. Two 2516 or.2716 type EPROMS, a

VERIFICATION MEDIA

All original pattern media, EPROMs or floppy disks, are
filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and
returned along with a listing verification form. The listing
should be thoroughly checked and the verification form
should be completed, signed, and returned to Motorola.
The signed verification form constitutes the contractual
agreement for the creation of the customer mask. To aid
in the verification process, Motorola will program customer-supplied blank EPROM(s) or DOS disks from the
data file used to create the custom mask.
ROM VERIFICATION UNITS (RVUs)

Ten MCUs containing the customer's ROM pattern will
be sent for program verification. These units will have
been made using the custom mask, but are for the purpose of ROM verification only. For expediency, the MCUs
are unmarked, packaged in ceramic, and tested with five
volts at room temperature. These RVUs are free with the
minimum-order quantity, but are not production parts.
These RVUs are not guaranteed by Motorola Quality Assurance.
ORDERING INFORMATION

The following table provides generic information pertaining to the package type and temperatue for the MC6801
and MC6803. These MCU devices are available in 40-pin
CERDIP and plastic dual-in-line (DIP) packages.

MOOS is a trademark of Motorola Inc.
IBM is a registered trademark of International Business Machines Corporation.

MOTOROLA MICROPROCESSOR DATA
3-172

Me6S01 U4/6S03U4

MECHANICAL DATA AND ORDERING INFORMATION
The following table provides generic information pertaining to the package type and temperatue for the MC6801

and MC6803. These MCU devices are available in 40-pin
CERDIP and plastic dual-in-line (DIP) packages.

GENERIC INFORMATION
Package Type

Frequency (MHz)

Temperature

Part Number

Cerdip
(S Suffix)

1.0
1.0
1.25
1.25
1.0
1.0
1.25
1.25

0° to 70°C
-40° to 85°C
0° to 70°C
-40° to 85°C
0° to 70°C
-40° to 85°C
0° to 70°C
-40° to 85°C

MC6801U4S1
MC6801 U4CSl
MC6801 U4S 1-1
MC6801U4CS1-1
MC6803U4S
MC6803U4CS
MC6803U4S-1
MC6803U4CS-l

Plastic
(P Suffix)

1.0
1.0
1.25
1.25
1.0
1.0
1.25
1.25

0° to 70°C
-40° to 85°C
0° to 70°C
-40° to 85°C
0° to 70°C
-40° to 85°C
0° to 70°C
-40° to 85°C

MC6801U4Pl
MC6801 U4CPl
MC6801U4Pl-1
MC6801U4CP1-1
MC6803U4P
MC6803U4CP
MC6803U4P-1
MC6803U4CP-l

PIN ASSIGNMENT

VSS
XTAL

2

SC1

EXTAL

3

SC2

'NtVii
iROl

4

P30

5

P31

RESET

P32
P33

VCC

7

P20

8

P34

P21

9

P35

P22

10

P36

P23

11

P37

P24

P40

P10

P41

P11

P42

P12

P43

P13

P44

P14

P45

P15

P46

P16

P47

P17

VCC
Standby

MOTOROLA MICROPROCESSOR .DATA
3-173

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC68701

Advance Information

MC68701 Microcontroller Unit (MCU)

I

The MC68701 is an 8-bit single-chip EPROM microcontroller unit (MCU) which significantly enhances the capabilities of the M6800 Family of parts. It can be used in production systems to allow
for easy firmware changes with minimum delay or it can be used to emulate the MC6801/MC6803
for software development. It includes an upgraded M6800 microprocessor unit (MPU) with upward
source and object code compatibility. Execution times of key instructions have been improved and
several new instructions have been added including an unsigned multiply. The MCU can function
as a monolithic microcomputer or can be expanded to a 64K byte address space. It is TIL compatible and requires one + 5 volt power supply for non programming operation. An additional Vpp
power supply is needed forEPROM programming. On-chip resoources include 2048 bytes of
EPROM, 128 byte of RAM, Serial Communications Interface (SCI), parallel I/O, and a three function
Programmable Timer. A summary df MCU features includes:
• Enhanced MC6800 Instruction Set
• 8 x 8 Multiply Instruction
• Serial Communications Interface (SCI)
• Upward Source and Object Code Compatibility with the MC6800
• 16-Bit Three-Function Programmable Timer
• Single-Chip or Expanded Operation to 64K Byte Address Space
• Bus Compatibility with the M6800 Family
• 2048 Bytes of UV Erasable, User Programmable ROM (EPROM)
• 128 Bytes of RAM (64 Bytes Retainable on Powerdown)
• 29 Parallel I/O and Two Handshake Control Lines
• Internal Clock Generator with Divide-by-Four Output
• - 40 to 85°C Temperature Range

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-174

MC68701

MC68701 MICROCOMPUTER BLOCK DIAGRAM

.....-_>-+-+-. P20

P31
P32

1+-+-t-~-+-.P21
~+-+--1-"""'.P22

. . .+-t-i_-.P2~
P24

L __....-t-+--H....,.......

P41
P43
P44

II

j + - - - -... Pl0
~....,__:_:_--...

Pll

j + - - - -... P12

P47

~----... P13

1 + - - - - -... P14
~------;~P15

....- - - -... P16

1 + - - - - -... P17

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to + 7.0

V

Input Voltage

Vin

...,0.3 to + 7.0

V

TA

TL to TH
to 70
-40 to 85

o

°c

Tstg

o to 85

°C

Rating

Operating Temperature Range
MC68701
MC68701C
Storage Temperature Range

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Ceramic Package
Cerdip Package

Symbol

Value

This device contains circuitry to protect the in~
puts against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-rrnpedance Circuit. For proper Qpera~
tion it is recommended that Vin and Vout be constrained to the range VSSs (V in or V out ) s V ce.
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level
(e.g., either VSS or Vce).

Rating
°C/W

6JA
50
50

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in °C can be obtained from:
TJ==TA + (PO 8JA)
where:
== Ambient Temperature, °c
TA
== Package Thermal Resistance,
8JA
Junction-to-Ambient, °CIW
Po
== PINT + PPORT
PINT
== ICC x VCC' Watts ~ Chip In~ernal Power
PPORT == Port Power Dissipation,
Watts - User Determined
0

(1)

For most applications PPORT
s:
~

co
~

,

m

Port 4

Port 1

Port 1

81/0

8110

Lines

Lines

Port 2
5110 Lines

Port 4

Port 3
8110 Lines

II IiS3

::J:I

0

SN74LS373
(Typical)

-"

...

) Add"" ADA,

-"

08

aS
-->0

-->0

-->0
-->0

MOTOROLA MICROPROCESSOR DATA
3~183

) 0".

ODD,

II

MC68701

FIGURE 14 - MODE PROGRAMMING TIMING

See Figure 16
for Diode Arrangement.

r;VMPDD

:?,p:.r==
~--

(P20, P21, P22)'
VMPH Min

Mode Inputs
(P20, P21, P22)

MODE PROGRAMMING

mn - ----

VMPL Max
(Refer to Figure 14)
Symbol

Min

Typ

Max

Unit

Mode Programming Input Voltage Low for TA = 0 to 70~C

VMPL

-

1.8

V

Mode Programming Input Voltage High

VMPH

4.0

-

V

Mode Programming Diode Differential for TA = 0 to 70°C

VMPDD

0.6

RESET Low Pulse Width

PWRSTL

3.0

Mode Programming Set-Up Time

tMPS

2.0

-

Mode Programming Hold Time
RESET Rise Time"'" 1 j.Ls
RESET Rise Time> .><:0
~>

>

<:ORl

.>

8

P20--~~r-~------------------~----~

9

P21---;~'-~------------------------~

10

P22--~~+-~------------~----------~

P20 (PCOl
P21 (PC1)
P22 (PC2)

V

<;>
(

(

(

Q ¢ Q

Mode Control Switches

~, ~, ~~ D

>

MC68701

~R2

:>

~, 0

~.

"Normal"

~

-

51

-'r-

6

RESETIVpp

Vpp~

"Program"
Notes:
1. Mode 0 as shown (switches closed).
2. Rl = 10k ohms (typical).
3. The RESET time constant is equal to RC where R is the equivalent parallel resistance of R2 and the number of resistors (Rl)
placed in the circuit by closed mode control switches.
4. D = 1N914, 1N4001 in the 0 to 70°C range
D = 1N270, MBD201 in the - 40 to 85°C range
5. If V=VCC, the R2=50 ohms (typical) to meet VIH for the RESETNpp pin. V=VCC is also compatible with MC6801. The RESET
time constant in this case is approximately R2*C.
6. Switch Sl allows selection of normal (RESET) or programming (VpP) as the input to the RESETNpp pin. During switching,
the input level is held at a value determined by a diode (D), resistor (R2) and input voltage (V).
7. While Sl is in the "Program" position, RESET should not be asserted.
8. From powerup, RESET must be held low for at least tRC. The capacitor, C, is shown for conceptual purposes only and is on
the order of 1000 j.LF for the circuit shown. Typically, a buffer with an RC input will be used to drive RESET, eliminating the
need for the larger capacitor.
9. Diode Vf should not exceed VMPDD min.

MOTOROLA MICROPROCESSOR DATA

3-184

FIGURE 16 -

MC68701
Mode

o

s:

a

SOOl F

5:
s:

Cf
~

00

U'I

n
::0
o"'tI

~
m
en
en

I'«'U«'U'(

Internal RAM
SOOFF

i"<"UUU((~

S0080

i;nnnnnJC

SOOFF

luuuau<3Ok

>20 k

>20 k

>20 k

3.58 MHz

4.00 MHz

RS

600

500

Co

3.5 pF
0.015 pF

6.5 pF

>40k

MC68701

C1
Q

20-40 0

* Note:

These are representative AT-cut crystal parameters only. Crystals of other types of
cuts may also be used.

2

------11 .....
1- - - - - -

CL = 20 pF (typical)
NOTE

RS

TTL-compatib~illators may be
2

obtained from:

3

Motorola Component Products
Attn: Data Clock Sales
2553 N. Edginton St.
Franklin Park, IL 60131
Tel: 312-451-1000
Telex: 433-0067

Co
Equivalent Circuit
(b) Oscillator Stabilization Time (tRC)

~----------_~~4-.7-5-V------------4JJ~'-------------------------------

vee ____

----+------:JI
I

I

J

""1I(_-----tRe----=-~

Oscillator
Stabilization
Time. tRC

MOTOROLA MICROPROCESSOR DATA

3-191

3

II

MC68701

Port 3 In Single-Chip Mode
Port 3 is an 8-bit I/O port in the Single-Chip Mode, with
each line configured by the Port 3 Data Direction Register.
There are also two lines, IS3 and OS3, which can be used to
control Port 3 data transfers.
Three Port 3 OPtions are controlled by the Port 3 Control
and Status Register and are available only in Single-Chip
Mode: (1) Port 3 input data can be latched using IS3 as a
control signal, (2) OS3 can be generated by either an MPU
read or write to the Port 3 Data Register, and (3) an IR01 interrupt can be enabled by an IS3 negative edge. Port 3 latch
timing is shown in Figure 4.

SC1 And SC2 In Expanded Non-Muitiplexed Mode
In the Expanded Non-Multiplexed Mode, both SC1 and
SC2 are configured as outputs. SC1 functions as Input/Output Select (lOS) and is asserted only when $0100 through
$01 FF is sensed on the internal address bus.
SC2 is configured as Read/Write and is used to control
the direction of data bus transfers. An MPU read is enabled
when Read/Write and E are high.
SC1 And SC2 In Expanded Multiplexed Mode
In the Expanded Multiplexed Modes, both SC1 and SC2
are configured as outputs .. SC1 functions as Address Strobe
and can be used to demultiplex the eight least significant addresses and the data bus. A latch controlled by Address
Strobe captures address on the negative edge, as shown in
Figure 15.
SC2 is configured as Read/Write and is used to control
the direction of data bus transfers. An MPU read is enabled
when Read/Write and E are high.

I

PORT 3 CONTROL AND STATUS REGISTER

P10-P17 (PORT 1)
Port 1 is a mode independent 8-bit I/O port with each line
an input or output as defined by the Port 1 Data Direction
Register. The TTL compatible three-state output buffers can
drive one Schottky TTL load and 30 pF, Darlington transistors, or CMOS devices using external pullup resistors. It is
configured as a data input port by RESET. Unused lines can
remain unconnected.

[P

C2 1 PC1

5

I I
PCO

P241 P231 P221 P21

I I
P20

4

3

2

IS3
Flag

IS3
IR01
Enable

X

OSS

Latch
Enable

X

Bit 5
Bit 6

Bit 7

a
X

X

$oooF

Not used.
LATCH ENAB LE. This bit controls the
input latch for Port 3. If set, input data
is latched. by an IS3 negative edge. The
latch is transparent after a read of Port
3 Data Register. LATCH ENABLE is
cleared during reset.
OSS (Output Strobe Selectl. This bit
determines whether OS3 will be
generated by a read or write of the Port
3 Data Register. When clear, the
strobe is generated by a read; when
set, it is generated by a write. OSS is
cleared during reset.
Not used.
IS3 IR01 ENABLE. When set, an IR01
interrupt will be enabled whenever IS3
FLAG is set; when clear, the interrupt
is inhibited. This bit is cleared during
reset.
IS3 FLAG. This read-only status bit is
set by an IS3 negative edge. It is
cleared by a read of the Port 3 Control
and Status Register (with IS3 FLAG
set) followed by a read or write to the
Port 3 Data Register or during reset.

Port 3 In Expanded Non-Multiplexed Mode
Port 3 is configured as a bidirectional data bus !07-DOI in
the Expanded Non-Multiplexed Mode. The direction of data
transfers is controlled by Read/Write (SC2l. Data is clocked
by E (Enable).

a

432

5

Bit 4

PORT 2 DATA REGISTER
6

6

Bit 0-2
Bit 3

P20-P24 (PORT 2)
Port 2 is a mode-independent, 5-bit, multipurpose I/O
port. The voltage levels present on P20, P21, and P22 on the
rising edge of RESET determine the operating mode of the
MCU. The entire port is then configured as a data input port.
The Port 2 lines can be selectively configured as data output
lines by setting the appropriate bits in the Port 2 Data Direction Register. The Port 2 Data Register is used to move data
through the port. However, if P21 is configured as an output, it will be tied to the timer Output Compare function and
cannot be used to provide output from the Port 2 Data
Register.
Port 2 can also be used to provide an interface for the
Serial Communications Interface and the timer Input Edge
function. These configurations are described in the appropriate SCI and Timer sections of this publication.
The Port 2 high-impedance, TTL compatible output buffers are capable of driving one Schottky TTL load and 30 pF
or CMOS devices using external pullup resistors.

7

7

$0003

P30-P37 (PORT 3)
Port 3 can be configured as an I/O port, a bidirectional
8-bit data bus, or a multiplexed address/ data bus depending
on the operating mode. The TTL compatible three-state output buffers can drive one Schottky TTL load and 90 pF.
Unused lines can remain unconnected.

Port 3 In Expanded Multiplexed Mode
Port 3 is configured as a time multiplexed address (AO-A7)
and data bus (07-001 in the Expanded Multiplexed Modes
where Address Strobe (AS) can be used to demultiplex the
two buses. Port 3 is held in a high impedance state between
valid address and data to prevent potentional bus conflicts.

MOTOROLA MICROPROCESSOR DATA

3-192

MC68701

P40-P47 (PORT 4)

MC68701 RAMlEPROM CONTROL' REGISTER

Port 4 is configured as an 8-bit I/O port, as address outputs, or as data inputs depending on the operating mode.
Port 4 can drive one Schottky TTL load and 90 pF and is the
only port with internal pullup resistors. Unused lines can remain unconnected.

4

x
Bit 0

Port 4 In Single Chip Mode
In Single Chip Mode, Port 4 functions as an 8-bit I/O port
with each line configured by the Port 4 Data Direction
Register. Internal pullup resistors allow the port to directly interface with CMOS at 5 volt levels. External pullup resistors
to more than 5 volts, however, cannot be used.
Port 4 In Expanded Non-Multiplexed Mode

Port 4 is configured during reset as an 8-bit input port,
where the Port 4 Data Direction Register can be written to
provide any or all of eight address lines AO to A7. Internal
pullup resistors pull the lines high until the Port 4 Data Direction Register is configured.
Bit 1

Port 4 In Expanded Multiplexed Mode
In all Expanded Multiplexed modes except Mode 6, Port 4
functions as half of the address bus and provides A8 to A 15.
In Mode 6, the port is configured during reset as an 8-bit
parallel input port, where the Port 4 Data Direction Register
can be written to provide any or all of upper address lines A8
to A 15. Internal pullup resistors pull the lines high until the
Port 4 Data Direction Register is configured, where bit 0 controls A8.

RESIDENT MEMORY
The MC68701 has 128 bytes of on board RAM and 2048
bytes of on board UV erasable EPROM. This memory is controlled by four bits in the RAM/EPROM Control Register.
One half of the RAM is powered through the VCC standby
pin and is maintainable during VCC powerdown. This standby portion of the RAM consists of 64 bytes located from $80
through $BF.
Power must be supplied to V CC standby if the internal
RAM is to be used, regardless of whether standby power
operation is anticipated. In Mode 3, VCC standby should be
tied to ground.
The RAM is controlled by the RAM/EPROM Control
Register.

Bit 2-5
Bit 6 RAME

Bit 7 STBY PWR

RAM/EPROM CONTROL REGISTER ($14)
The RAM/EPROM Control Register includes four bits:
STBY PWR, RAME, PPC, and PLC. Two of these bits,
STBY PWR and RAME, are used to control RAM access and
determine the adequacy of the standby power source during
power-down operation. It is intended that RAME be cleared
and STBY PWR be set as part of a power-down procedure.
RAME and STBY PWR are Read/Write bits.
The remaining two bits, PLC and PPC, control the operation of the EPROM. PLC and PPC are readable in all modes
but can be changed only in Mode O. The PLC bit can be written without restriction in Mode 0, but operation of the PPC
bit is controlled by the state of PLC.
Associated with the EPROM are an 8-bit data latch and a
16-bit address latch. The data latch is enabled at all times,
latching each data byte written to the EPROM. The address
latch is controlled by the PLC bit.
A description of the RAM/EPROM Control Register
follows.

3

2

1

0

X

X

PPC

PLC

I I I I I

$14

,PLC. Programming Latch Control.
This bit controls (a) a latch which captures the EPROM address to be programmed and (b) whether the PPC bit
can be cleared. The latCh is triggered
by an MPU write to a location in the
EPROM. This bit is set during reset
and can be cleared only in Mode O. The
PLC bit is defined as follows:
PLC=O EPROM address latch
enabled; EPROM address is latched
during MPU writes to the EPROM.
PLC = 1 EPROM address latch is
transparent.
PPC. Programming Power Control.
This bit gates power from the
RESETlVpp pin to the EPROM programming circuit. PPC, is set during
reset and whenever the PLC bit is set.
It can be cleared only if (a) operating in
Mode 0, and (b) if PLC has been
previously cleared. The PPC bit is
defined as follows:
PPC = 0 EPROM programming
power (Vpp) applied.
PPC = 1 EPROM programming
power (Vpp) is not applied.
Unused.
RAM Enable. This Read/Write bit can
be used to remove the entire RAM
from the internal memory map. RAME
is ,set (enabled). during reset provided
standby power is' available on the
positive edge of reset. If RAME is
clear, any access to a RAM address is
external. If RAME is set and not in
Mode 3, the RAM is included in the internal map.
Standby Power. This bit is a read/
write status bit which, when once set,
remains set as long as V CC standby remains above VSBB (minimum!. As
long as this bit is set following a period
of standby operation, the standby
power supply has adequately preserved the data in the standby RAM. If this
bit is cleared during a period of standby operation, it indicates that V CC
standby had fallen to a level sufficiently below VSBB (minimum) to
suspect that data in the standby RAM
is not valid. This bit can be set only by
software and is not affected during
reset.

Note that if PPC and PLC are set, they cannot be
simultaneously cleared with a single MPU write. The PLC bit
must be cleared prior to attempting to clear PPC. If both PPC
and PLC are clear, setting PLC will also set PPC. In addition,

MOTOROLA MICROPROCESSOR DATA

3-193

II

MC68701

A routine which can be used to program the MC68701
EPROM is provided at the end of this publication. This npnreentrant routi!1e requires four double byte variables named
IMBEQ, IMEND, PNTR, and WAIT to be initialized prior to
entry to the routine. These variables indicate (a) the first and
last memory locations which bound the data to be programmed into the EPROM, (b) the first EPROM location to be programmed, and (c) a number which is used to generate
the programming time delay. The last variable, WAIT, takes
into account the MCU input crystal (or TTL-compatible
clock) frequency to insure the programming time, tpp, is
met. WAIT is defined as the number of MPU E-cycles that
will occur in the real-time EPROM programming interval,
tpp. For example, if tpp=50 milliseconds an~ the MC68701
is being driven with a 4.00 MHz TTL-compatible clock:
WAIT (MPU E-cycles) = .tpp*(MCU INPUTFREOIl4* 106
=50000(4* 106)/4* 106
=50000

it is assumed that vpp is applied to the RESET /VPP pin
whenever PPC is clear. If this is not the case, the result is
undefined.

I

ERASING THE MC68701 EPROM
Ultraviolet erasure will clear all bits of the EPROM to the
"0" state. Note that this erased state differs from that of
some other widely used EPROMs (such as the MCM68708)
where the erased state is a "1". The M C68701 EP ROM is
programmed by erasing it to "O's" and entering "l's" into
the desired bit locations.
The MC68701 EPROM can be erased by exposure to high
intensity ultraviolet light with a wave length of 2537 A for a
minimum of 30 minutes. The recommended integrated dose
(UV intensity X exposure time) is 15 Ws/cm. The lamps
should be used without shortwave filters and the MC68701
should be positioned about one inch away from the UV
tubes.
The MC68701 transparent lid should always be covered
after erasing. This protects both the EPROM and lightsensitive nodes from accidental exposure to ultraviolet light.

NOTE
A monitor program called. PRObug
is available from
Motorola Microsystems. PRObug contains a user option for
programming the on-board MC68701 EPROM.

PROGRAMMING THE MC68701 EPROM
When the MC68701 is released from Reset in Mode 0, a
vector is fetched from location $BFFE:BFFF. This provides a
method for an external program to obtain control of the
microcomputer with <;Iccess to every location in the EPROM.
To program the EPROM, it is necessary to operate the
MC68701 in Mode 0 under the control of a program r~sident
in external memory which can facilitate loading and programming of the EPROM. After the pattern has been loaded
into external memory, the EPROM can be programmed as
follows:
a. Apply programming power (Vpp) to the RESET /VPP
pin.
b. Clear the PLC control bit and set the PPC bit by
writing $FE .to the RAM/EPROM Control Register.
c. Write data to the next EPROM location to be programmed. Triggered by an MPU write to the
EPROM,internal latches capture both the EPROM
address and the data byte.
d. Clear the PPC bit for programming time, tp p , by
writing $FC to the RAM/EPROM Control Register
and waiting for time, tpp. This step gates the programming power (Vpp) from the RESETIVpp pin to
the EPROM which programs the location.
e. Repeat steps b through d for each byte to be programmed.
f.
Set the PLC and PPC bits by writing $FF to the
RAM/EPROM control register.
g. Remove the programming power (Vpp) from the
RESET/Vpppin. The EPROM can now be read and
verified;

PROGRAMMABLE TIMER
The Programmable Timer can be used to perform input
waveform measurements while independently generating an
output waveform. Pulse widths can vary from several
microseconds to many seconds. A block diagram of the
Timer is shown in Figure 21.
COUNTER ($09:0A)
The key timer element is a 16-bit free-running counter
which is incremented by E (Enable). It is cleared during reset
and is read-only with one exception: a write to the counter
($09) will preset it to $FFF8. This feature, intended for
testing, can disturb serial operations because the counter
provides the SCI internal bit rate clock. TOF is set whenever
the counter contains all l's.
OUTPUT COMPARE REGISTER ($OB:OC)
The Output Compare Register is a 16-bit Read/Write
register used to control an output waveform or provide an arbitrary timeout flag. It is compared with the free-running
counter on each E-cycle. When a match occurs, OCF is set
and OLVL is clocked to an output level register. If Port 2, bit
,; is configured as an output, OLVL will appear at P21 and
the Output Compare Register and OLVL can then be
changed for the next compare. The function is inhibited for
one cycle after a write to the high byte of the Compare
Register ($OB) to ensure a valid compare. The Output Compare Register is set to $FFFF during reset.
INPUT CAPTURE REGISTER ($OD:OE)
The Input Capture Register is a 16-bit read-only register
used to store the free-running counter when a "proper" input transition occurs as defined by IEDG. Port 2, bit 0 should
be configured as an input, but the edge detect circuit always

Because of the erased state of an EPROM byte is $00, it is
not necessary to program a location which is to contain $00.
Finally, it should be noted that the result of inadvertently
programming a location more than once is the logical OR of
the data patterns.
PRObug is a trademark of Motorola Inc.

MOTOROLA MICROPROCESSOR DATA

3-194

MC68701

FIGURE 21 - BLOCK DIAGRAM OF PROGRAMMABLE TIMER

MC68701 Internal Bus

II

Timer
Control

And
Status
Register
$08

Output
Level

Input
Edge

Bit 1

BitO
Port 2

Port 2

senses P20 even when configured as an output. An input
capture can occur independently of ICF: the register. always
contains the most current value. Counter transfer is inhibited, however, between accesses of a double byte MPU
read. The input pulse width must be at least two E-cycles to
ensure an input capture under all conditions.

Bit 0 OLVL

Bit 1 EIDG

TIMER CONTROL AND STATUS REGISTER

($~)

The Timer Control and Status Register (TCSR) is an 8-bit
register of which all bits are readable while bits 0-4 can be
written. The three most significant bits provide the timer
status and indicate if:
• a proper level transition has been detected,
• a match has occurred between the free-running
counter and the output compare register, and
• the free-running. counter has overflowed.

Bit 2 ETOI

Bit 3 EOCI

Each of the three events can generate an IR02 interrupt
and is controlled by an individual enable bit in the TCSR.

TIMER CONTROL AND STATUS REGISTER (TCSR)

7

6

5

4

3.

2

1

0

Bit 4 EICI

MOTOROLA MICROPROCESSOR DATA
3-195

Output level. OLVL is clocked to the
output. level register by a successful
output compare and will appear at P21
if Bit 1 of the Port 2 Data Direction
Register is set. It is cleared during
reset.
Input Edge. IEDG is cleared during
reset and controls which level transition will trigger a counter transfer to
the Input Capture Register:
IEDG = 0 Transfer on a negative-edge
IEDG = 1 Transfer on a positive-edge.
Enable Timer Overflow Interrupt.
When set, an IR02 interrupt is enabled
for a timer overflow; when clear, the
interrupt is inhibited. It is cleared during reset.
Enable Output Compare Interrupt.
When set, an IRQ2 interrupt is enabled
for an output compare; when clear,
the interrupt is inhibited. It is cleared
during reset.
Enable Input Capture Interrupt. When
set, an IR02interrupt is enabled for an
input capture; when clear, the interrupt is inhibited. It is cleared during
reset.

MC68701 .

Bit 5 TOF

Bit 6 OCF

Bit 7 ICF

Transmit/ Receive Control and Status Register. Data is
transmitted and received utilizing a write-only Transmit
Register and a read-only Receive Register. The shift registers
are not accessible to software.

Timer Overflow Flag. TOF is set when
the counter contains all 1'so It is
cleared by reading the TCSR (with
TOF set) then reading the counter high
byte ($09), or by RESET.
Output Compare Flag. OCF is set
when the Output Compare Register
matches the free-running counter. .It is
cleared by reading the TCSR (with
OCF set) and then writing to the Output Compare Register ($OB or $OC), or
by RESET.
Input Capture Flag. ICF is set to indicate a proper level transition; it is
cleared by reading the TCSR (with ICF
set) and then the Input Capture
Register High Byte ($OD), or by
RESET.

Rate and Mode Control Register (RMCR) ($10)
The Rate and Mode Control Register controls the SCI bit
rate, format, clock source, and under certain conditions, the
configuration of P22. The register consists of four write-only
bits which are cleared during reset. The two least significant
bits control the bit rate of the internal clock and the remaining two bits COntrol the format and clock source.

RATE AND MODE CONTROL REGISTER (RMCR)
7

6

5

x

x

x

Bit 1:Bit

I

43210
CCl CCO SSl SSO

x

I

I I

I

I $0010

a

SSl:SS0 Speed Select. These two
bits select the Baud rate when using
the internal clock. Four rates may be
selected which are a function of the
MCU input frequency. Table 6 lists bit
time and rates for three selected MCU
frequencies.
Bit 3:Bit 2
CC 1: CCO Clock Control and Format
Select. These two bits control the format and select the serial clock source.
If CCl is set, the DDR value for P22 is
forced to the complement of CCO and
cannot be altered until CCl is cleared.
If CCl is cleared after having been set,
its DDR value is unchanged. Table 7
defines the formats, clock source, and
use of P22.
If both CCl and CCO are set, an external TTL compatible
clock must be connected to .P22 at eight times (8X) the
desired bit rate, but not greater than E, with a duty cycle of
50% (± 10%1. If eCl :CCO= 10, the internal bit rate clock is
provided at P22 regardless of the values for TE or RE.

SERIAL COMMUNICATIONS INTERFACE (SCI)
A full-duplex asynchronous Serial Communications Interface (SCI) is provided with two data formats and a variety of
rates. The SCI transmitter and receiver are functionally independent, but use the same data format and bit rate. Serial
data formats include standard mark/space (NRZ) and Biphase and both provide one start bit, eight data bits, and one
stop bit. "Baud" and "bit rate" are used synonymously in
the following description ..
WAKE-UP FEATURE
In a typical serial loop mUlti-processor configuration, the
software protocol will usually identify the addressee(s) at the
beginning of the message. In order to permit uninterested
MPU's to ignore the remainder of the message, a wake-up
feature is included whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until the data line goes
idle. An SCI receiver is re-enabled by an idle string of' 11
consecutive 1's or during reset. Software must provide for
the required idle string between consecutive messages and
prevent it within messages.

NOTE: The source of SCI internal bit rate clock is the timer
free running counter. An MPU write t9 the counter
can disturb serial operations.

PROGRAMMABLE OPTIONS
The following features of the SCI are programmable:
• format: standard mark/space (NRZ) or Bi-phase
• clock: external or internal bit rate clock
• Baud: orie of 4 per E-clock frequency, or external clock (X8 desired baud)
• wake-up feature: enabled or disabled
• interrupt requests: enabled individually for transmitter and. receiver
• clock output: internal bit rate clock enabled or disabled to P22

Transmit/ Receive Control And Status Register
(TRCSR) ($11)
The Transmit/Receive Control and Status Register controls the transmitter, receiver, wake-up feature, and two individual interrupts and monitors the status of serial operations. All eight bits are .readable while bits a to 4 are also
writable. The register is initialized to $20 by RESET.

TRANSMIT/RECEIVE CONTROL AND STATUS
REGISTER (TRCSR)

SERIAL COMMUNICATIONS REGISTERS
The Serial Communications Interface includes four addressable registers as depicted in Figure 22. It is controlled
by the .Rate and Mode Control Register and the

a

765432

IRDR10RF~TDRE I I I I I I
RIE

MOTOROLA MICROPROCESSOR DATA

3-196

RE

TIE

TE

WU

$0011

MC68701

TABLE 6 -

SS1:SS0
0
0
1
1

4f _
o
E

SCI BIT TIMES AND RATES

2.4676 MHz
614.4 kHz

0
+16
1
+128
0
+1024
1
+4096
External (P22)

26 ILs/38,400
208J,s/4,800
1.67 ms/6OO
6.67 ms/150
Up to 76,800

TABLE 7 -

0
1

1

4.9152 MHz
1.2288 MHz

16 ILs/62 500 claud
128 I's17812.5 Baud
1.024 ms/g76.6 Baud
4.096 ms/244.1 Baud
Up to 125,000 Baud

13.0 ILs176 800 Baud
104.2l'5/9,6OO Baud
833.3 I's/ 1,200 Baud
3.33 ms/300 Baud
Up to 153,600 Baud

SCI FORMAT AND CLOCK SOURCE CONTROL
Format

Clock Source

Port 2, Bit 2

0
1

Bi-Phase

Internal

Not Used

NRZ

Internal

Not Used

0

NRZ

1

NRZ

Internal
External

Output
Input

CC1:CCO
0

Baud
Baud
Baud
Baud
Baud

4.0 MHz
1.0 MHz

FIGURE 22 - SCI REGISTERS
Bit 7

Rate and Mode Control Register

Bit 0

, CCI ., CCO' SSl , SSO

I

S10

Transmit/Receive Control and Status Register

I I
RDRF

ORFE ITDREI RIE

I

RE

TIE

S12

Port 2

INot Addressablel
Receive Shift Register

10

Transmit Shift Register

12

.S13
Transmit Data Register

MOTOROLA MICROPROCESSOR DATA

3-197

II

MC68701

Bit 0 WU

"Wake-up" on Idle Line. When set,
WU enables the wake-up function;, it is
cleared by 111 Iconsecutive 1's or during reset: WU will not set if the line is
idle.
'

Bit 1 TE

Transmit Enable. When set, P24 PDR
bit is set, cannot be changed, and will
remain set if TEissubsequently
cleared. When TE is changed from
clear to' set, the transmitter is connected to P24 and a preamble of nine
consecutive 1's is transmitted. TE is
cleared during reset.
Transmit Interrupt Enable. When set,
an IR02 interrupt is enabled when
TDRE is set; when clear, the interrupt
is inhibited. TE is cleared during reset.
Receive Enable. When set, the P23
DDR bit is cleared, cannot be changed, and will remain clear if RE is subsequently cleared. While RE is set, the
SCI receiver is enabled. RE is cleared
during reset.
Receiver Interrupt Enable. When set,
an IR02 interrupt is enabled when
RDRF and/or ORFE is set; when clear,
the interrupt is inhibited. RIE is cleared
during reset.
Transmit Data Register EmptY. TDRE
is set when the Transmit Data Register
is transferred to the output serial shift
register or during reset. It is Cleared by
reading tre, TRCSR (with TDRE set)
and then writing to the Transmit Data
Register. Additional data wilL be
transmitted only if TDRE has ,been
cleared.
Overrun Framing Error. If set, ORFE indicates either an overrun or framing erc
ror. An overrun is a new byte ready to
transfer to the Receiver Data Register
with RDRF still set. A receiver framing
error has occurred when the byte
boundaries of the bit stream are not

Bit 2 TIE

Bit 3 RE

II

Bit 4 RIE

Bit 5 TDRE

Bit 6 ORFE

synchronized to the bit counter. An
overrun can, be distinguished from a
framing error by the state of RDRF: if
RDRF is set, then an' overrun has occurred; otherwise a framing error has
been detected. Data is not transferred
to the, Receive Data Register in an
overrun condition. Unframed data
causing a framed error is transferred to
the Receive Data Register. However,
subsequent data transfer is blocked
until the framing error flag is cleared.·
ORFE is cleared by reading the TRCSR
(with ORFE set) then the Receive Data
Register, or during reset.
Receive Data Register Full. RDRF is
set when the input serial shift register
is transferred to the Receive Data
Register. It is cleared by reading the
TRCSR (with RDRF set), and then the
Receive Data Register, or during reset.

Bit 7 RDRF

SERIAL OPERATIONS
The SCI is initialized by writing control bytes first to the
Rate and Mode Control Register and then to the
T ransmit/ Receive Control and Status Register. When TE is
set, the output of the transmit serial shift register is connected to P24 and serial output is initiated by transmitting to
9-bit preamble of 1's.
At this point one of two situations exist: 1) if the Transmit
Data Register is empty (TDRE = 1), a continuous string of 1's
will be sent indicating an idle line, or 2) if a byte has been
written to the Transmit-Data Register (TDRE=O), it will be
transferred to the output serial shift register (synchronized
,with the bit rate clock), TDR E will be set, and transmission
will begin.
The start bit (0), eight data bits (beginning with bit 0) and a
stop bit (1), will be transmitted. If TDRE is still set when the
next byte transfer should occur" 1's will be sent until more
data is provided. In Bi-phase format, the output toggles at
the start of each bit and at half-bit time when a "1" is sent.
Receive operation is controlled by RE which configures P23
as an input and enables the receiver. SCI data formats are illustrated in Figure 23.

FIGURE 23 - SCI, DATA FORMATS
Output
Clock

,
"

I

:
I

NRZ
Format

'",I
Bi-Phase
Format
Idle Start

Bit
0

Bit
2

3

4

5

6

7

Stop

Data: 01001101 ($40)

* Devices made with mask

numbers T7A and CB4 do not transfer unframed data to the Receive Data Register,

MOTOROLA MICROPROCESSOR 'DATA

3-198

MC68701

INSTRUCTION SET

from bit 3 (Hl. These bits are testable by the conditional
branch instructions. Bit 4 is the interrupt mask (I-bit) and inhibits all maskable interrupts when set. The two unused bits,
B6 and B7 are read as ones.

The MC68701 is upward source and object code compatible with the MC6800. Execution times of key instructions
have been reduced and several new instructions have been
added, including a hardware multiply. A list of new operations added to the MC6800 instruction set is shown in
Table 1. In addition, two new special opcodes, 4E and 5E,
are provided for test purposes. Theseopcodes force the program counter to increment like a 16-bit counter, causing address lines used in the expanded modes to increment until
the device is reset. These opcodes have no mnemonics.
The coding of the first (or only) byte corresponding to an
executable instruction is sufficient to identify the instruction
and the addressing mode. The hexadecimal equivalents of
the binary codes, which result from the translation of the 82
instructions in, all valid modes of addressing, are shown in
Table 8. There are 220 valid machine codes, 34 unassigned
codes, and 2 reserved for test purposes.

ADDRESSING MODES
The MC68701 provides six addressing modes which can be
used to reference memory. A summary of addressing modes
for all instructions is presented in Tables 9, 10, 11, and 12
where execution times are provided in E cycles. Instruction
execution times are summarized in Table 13. With an input
frequency of 4 MHz, E cycles are equivalent to microseconds. A cycle-by-cycle description of bus activity for
each instruction is provided in Table 14 and a description of
selected instructions is shown in Figure 24.
Immediate Addressing - The operand or "immed,iate
byte(s)" is contained in the following byte(s) of the instruction where the number of bytes matches the size of the
register. These are two or three byte instructions.
Direct Addressing - The least significant byte of the
operand address is contained in the second byte of the instruction and the most significant byte is assl'med to be $00.
Dir8ct addreSSing allows the user to access $00 through $FF
using two byte instructions and execution time is reduced by
eliminating the additional memory access .. In most applications, the 256-byte area is reserved for frequently referenced
data.
Extended Addressing - The second and third bytes of the
instruction contain the absolute address of the operand.
These are three byte instrutions.
Indexed Addressing - The unsigned offset contained in
the second byte of the instruction is added with carry to the
Index Register and used to reference memory without
changing the Index Register. These are two byte instructions.
Inherent Addressing - The operand(s) are registers and
no memory reference is required. fhese are single byte ;nstructions.
Relative Addressing - Relative addressing is used only for
branch instructions. If the uranGh condition is true, the Program Counter is overwritten with the sum of a signed single
byte displacement in the second byte of the instruction and
the current Program Counter. This provides a branch range
of -126 to 129 bytes from the first byte of the instruction.
These are two byte instructions.

PROGRAMMING MODEL
A programming model for the MC68701 is shown in Figure
9. Accumulator A can be concatenated with accumulator B
and jointly referred to as accumulator D where A is the most
significant byte. Any operation which modifies the double
accumulator will also modify accumulator A and/or B. Other
registers are defined as follows:
Program Counter - The program counter is a 16-bit
register which always points to the next instruction.
Stack Pointer - The stack pointer is a 16·bit register
which contains the address of the next available location in a
pushdown/pullup (LIFO) queue. The stack resides in random access memory at a location defined by the programmer.
Index Register - The Index Register is a 16-bit register
which can be used to store data or provide an address for the
indexed mode of addressing.
Accumulators - The MCU contains two 8-bit accumulators, Aand B, which are used to store operands and
results from the arithmetic logic unit (ALU). They can also be
concatenated and referred to as the D (double) accumulator.
Condition Code Registers - The condition code· register
indicates the results of an instruction and includes the
Overflow (V), Carry/Borrow from MSB (C), and Half Carry
following five condition bits: Negative (N), Zero (Z),

MOTOROLA MICROPROCESSOR DATA
3-199

II

MC68701

TABLE 8 - CPU INSTRUCTION MAP

OP

MNEM

MODE

-

I

NOP

INHER

2

1

00
01
02
03

04
05
06

~
LSRD
ASLD

3

1

3
2
2

1
1

07

TAP
TPA

OS

INX

3

09
OA

DEX
CLV
SEV

3
2
2
2

OB
OC
aD

CLC
SEC
CLI
SEI

2
2

10

SBA

2

11

CBA

2

OE
OF

2

,

OP

MNEM

MODE

3
3
3

1
1
1

6B

ASL
ROL

INDXD

69'
6A

PSHB

3

1

38
39

PULX
RTS

5
5

1
1

3A

ABX
RTI

3

OP

MNEM

MODE

34

INHER

36

DES
TXS
PSHA

37

35

1
1

3B
3C

1
1
1

3D
3E
3F

1
1

40

1
1

42
43

1
1

44

~

-

10

1
1

PSHX

4

1

MUL
WAI

10

2

1
1
1
1

COMA

2

1

9
12

SWI
NEGA

41

6B
6C
6D
6E
6F
70

-

1

TST
JMP
CLA
NEG

INDXD
EXTND

OP

MNEM

MODE

2
2

9C
9D

CPX
JSR

DIR

6

DEC
INC

I

6
6

2

9E
9F

LOS
STS

6
6

2

AO
Al

SUBA
CMPA

3
6
6

2
2

A2

SBCA
SUBD
ANDA

2

3

A3
A4

6

3
3

A5
A6
A7
A8

6

3
3

71

72
73
74
75
76

77

COM
LSR

6

A9
ROA
ASA

AA
AB

~

5
5,

DIR

4
4

INDXD

4
4
4

I

OP

MNEM

MODE

-

I

2
2
2

DO

SUBB
CMPB

DIR

Dl

3
3

2
2

2
2
2

D2

SBCB

D3
D4

ADDD

3
5

ANDB
BITB

3
3

LDAB
STAB

3

D5

2

D6
D7

6
4

2
2

D8

EORB

BITA
LDAA

4
4

D9
DA

ADCB
ORAB

STAA
EOAA

4
4

2
2
2

DB

ADDB

2
2

DC
DD

2

DE
DF

LOD
STD
LDX

ADCA
OAAA

4
4

ADDA

4

4
4

2

4

2
2

2

1

78
79

ASL

CPX

6

6

3
3

AC

AOL

AD

JSR

6

2

EO
El

SUBB
CMPB

RORA

1

7A

DEC

6

3

13
14

47

ASRA
ASLA
ROLA

2
2
2

1
1
1

7B
7C
7D

AE
AF

LDS
STS
SUBA

5
5
4
4

2
2
3

E2
E3
E4

SBCB
ADDD
AN DB

3

1

7E
7F

E5
E6
E7

BITB
LDAB

1
1

80

15
16
17

TAB
TBA

2

1

49
4A

2

1

4B

2

1
1

18
19
lA

DAA

lB

ABA

lC
lD

··
·

IE
IF

20
21

BAA
BAN

22

BHI

23
24

BLS
BCC

25
26
27

BCS
BNE

INHER
INHER

2

J

3
3
3
3
3
3

2

5D

2

AEL
INHER

t

3
3
3
3
3
4
4

2

·

INCB

2
2

TSTB
T

5E
5F

CLRB

2
2

60

NEG

2

62
63

2

INHER
INDXD

1
1
1

86

1

67

64

2
2

8A
BB
8C
BD
8E
8F

65
ROR
ASR

1

INDXD

ADCA
ORAA
ADDA
CPX

IMMED

2
2
4

BSA
LOS

.

REL
IMMED

6
3

DIR

1

90

SUBA

91

CMPA

92

SBCA
SUBD
ANDA
BITA

3
3

LDAA
STAA
EORA

3
3
3

ADCA
ORAA
ADDA

3
3
3

2

1

93

6

2

94

95
96
COM
LSR

.

1

61

1
1
1

2

EORA

1
1

5B
5C

3
3

LDAA

2
2
2
2

2
3
2
2

87

ROLB
DECB

2
2

2
2

88
89

59
5A

2
2

B2
B3
B4

SUBD

1

58

3
3

ANDA
BITA

B5
86
1

2
2

EXTND
IMMED

3
6

B4

2

RORB

CLA
SUBA
CMPA
SBCA

6

BO
Bl

83

2

ASRB
ASLB

BMI

1
1

TST
JMP

3
3

2
4

COMB
LSRB

56

2B
2C

2
2

··

55

2
2

BGE
BLT
BGT

54

81
82

CLRA
NEGB

57

3

PULB

T

2
2

3
3

33

4E
4F

2
2

BVS
BPL

31

2
2

53
3
3

29
2A

32

INCA
TSTA

52
AEL

28

30

4C
4D

50

2
2

BLE
TSX
INS
PULA

2
2

51

BEG
BVC

2D
2E
2F

DECA

6

6
6

2
2

97

6
6

2

9A

2

9B

98
99

B5
B6
B7

CMPA
SBCA
SUBD
ANDA
BITA
LDAA
STAA

2

B8
B9
BA

EORA
ADCA
ORAA

BB
2
2

BC
BD

ADDA
CPX
JSR

2
2

BE
BF

LOS
STS

3
2
3

CO
Cl
C2
C3

SUBB
CMPB
SBCB
ADDD

C4

ANDB

C5

BITB
WAB

3

2

3
3

2
2

5

2
2
2
2

C6
C7

C8
C9

2
2

CA
CB
CC
CD

2
2

CE
CF

2

4
4
4

3
3

4

3

E8
E9
EA

4
4
4

3
3
3

EB
EC
ED

3
3

EE
EF
Fa

4
4
6
6
EXTND
IMMED
J~

3
3
3

Fl
F2

3
2
2
2

F3
F4

F7

2

3
2

2

2

F8
F9

2

2

FA

5
5
2
2
2
4

EORB

2

2

ADCB
ORAB
ADDB
LDD

2
2
2
3

2
2
3

3

3

.
.

LDX

,It
IMMED

NOTES:
1, Addressing Modes
INHER-Inherent
INDXD-Indexed
IMMED-Immediate
REL-Relative
EXTND-Extended DIR-Direct
2. Unassigned opcodes are indicated by "e" and should not be executed.
3. Codes marked by "T" force the PC to function as a 16-bit counter.

MOTOROLA MICROPROCESSOR DATA
3-200

6

3
3

2

F5
F6

2
2
2

INDXD

LSRA

46

INC

4
4

2
2

4

12

48

It

2
2
2

DIA

2
2

INDXD
EXTND

3
3
3
4

2
2
2

STX

6
6

45

3
3

2
2
2

STAB
EORB
ADCB
ORAB
ADDB
LDD
STD ,
LDX

,

STX

INDXD

SUBB
CMPB

EXTND

2

6
4
4

2

4
4

2
2

2

4

2

4
4

2
2

4

2
2
2

5
5
5
5
4

2
2
3

4

3

4

AN DB
BITB
LDAB
STAB

6
4

3
3
3

4
4
4

3
3
3
3

SBCB
ADDD

EORB

4

ADCB
ORAB

4
4

3
3

FB
FC

ADDB

4

LDD

5

3
3

FD

STD
LOX
STX

5

3

5
5

3
3

FE
FF

EXTND

* UNDEFINED GPCODE

MC68701

TABLE 9 -

INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes

,

Immecl
Pointer Operations
Compare Index Register
Decrement Index Register
Decrement Stack Pointer
Increment Index Register
Increment Stack Pointer
Load Index Register'
Load Stack Pointer
Store Index Register
Store Stack Pointer
Index Reg - Stack Pointer
Stack Pntr-Index Register
Add
Push Data

MNEM Op -

Pull Data

PULX

CPX 8C 4
DEX
DES
INX
INS
LOX CE 3
LOS 8E 3
STX
STS
TXS
TSX
ABX
PSHX

TABLE 10 Accumulator and
Memory Operations
Add Acmltrs
Add B taX
Add with Carry
Add
Add Double
And
Shift Left,
Arithmetic
Shift Left Obi
Shift Right,
Arithmetic
Bit Test
Compare Acmltrs
Clear

Compare
1 's Complement

Decimal Adj, A
Decrement

Exclusive OR
Increment

Load Acmltrs
Load Double
Logical Shift,
Left

MNE
ABA
ABX
ADCA
ADCB
ADDA
ADDB
AD DO
ANDA
ANDB
ASL
ASLA
ASLB
ASLO
ASR
ASRA
ASRB
BITA
BITB
CBA
CLR
CLRA
CLR8
CMPA
CMPB
COM
COMA
COMB
DAA
DEC
DECA
DECB
EORA
EORB
INC
INCA
INCB
LDAA
LDAB
LDO
LSL
LSLA
LSLB
LSLD

Direct

Op-

3 9C 5

,

Index

Op 2 AC 6

,

,

Extend

Op 2 BC 6

Op -

34 3
08 3
31 3
2
2
2
2

EE
AE
EF
AF

5
5
5
5

2 FE 5
2 BE 5
2 FF 5
2 BF 5

800leenl
Arithmetic Operation

1
1
1
1

3
3
3
3
30 3
3A 3
3C 4

1
1
1
1

38 5

1

35 3

5

4

3

2

1

H

I

N

Z

V

0
C

·· ·· · · ·
··· ··· ··· ·· ··· ···
·· ·· ··
··· ··· · · · ···
··· ··· ··· ··· ··· ···
······
J J J J
J

X-M:M+1

3
09 3

3 DE 4
3 9E 4
OF 4
9F 4

,

Inherent

X-1-X

SP-1-SP

J

X+1-X

1SP+1-SP
M-XH,(M+1)-XL
M-SPH,(M+ 1) -SPL
XH-M,XL -(M+l)
SPH-M,SPL -IM+11
X-1-SP
SP+1-X
B+X-X
XL -MSp,SP 1-SP
XH-MSp,SP-1-SP
SP+1-SP,MSP-XH
SP+1-SP,MSP-XL

R
R
R
R

ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 1 of 2)

Extend
Immed
Index
Direct
Inher
Boolean
Condition Codes
Op # Op- # Op - # Op - # Op
Expression
#
H
N Z V C
1B 2 1 A+B -A
I
I , f I
oo:B
+
X--X
3A 3 1
A+M+C-A
2
B9
4
A9
4
3
89 2 2 99 3 2
B+M+C-B
C9 2 2 09 3 2 E9 4 2 F9 4 3
A+ M-A
8B 2 2 9B 3 2 AB 4 2 BB 4 3
B + M --A
CB 2 2 DB 3 2 EB 4 2 FB 4 3
0+ M:M + 1--0
C3 4 3 03 5 2 E3 6 2 F3 6 3
A'M-A
84 2 2 94 3 2 A4 4 2 B4 4 3
R
B·M -B
C4 2 2 04 3 2 E4 4 2 F4 4 3
R
68 6 2 78 6 3
48 2 1 ~-I I II I II 11'-0
b7
bO
58 2 1
05 3 1
67 6 2 77 6 3
47 2 1
bO
b7
57 2 1
85 2 2 95 3 2 A5 4 2 B5 4 3
A'M
R
C5 2 2 05 3 2 E5 4 2 F5 4 3
B'M
R
11 2 1 A-B
t
I I
oo-M
6F 6 2 7F 6 3
R S R R
4F 2 1 OO-A
R S R R
5F 2 1 00 --8
R S R R
A-M
81 2 2 91 3 2 A1 4 2 B1 4 3
B -M
C1 2 2 01 3 2 E1 4 2 F1 4 3
I l
M --M
63 6 2 73 6 3
R S
43 2 1 A-A
R S
53 2 1 B--B
R S
19 2 1 fA.dj binary sum to BCD
I
M-1
M
6A 6 2 7A 6 3
4A 2 1 A-1-A
5A 2 1 8 -1 -B
A 0 M-A
88 2 2 98 3 2 A8 4 2 B8 4 3
R
B 0 M-B
C8 2 2 08 3 2 E8 4 2 FB 4 3
I R
M+ 1-M
6C 6 2 7C 6 3
\
I
4C 2 1 A + 1 --A
5C 2 1 B + 1 -B
M --A
B6 2 2 96 3 2 A6 4 2 B6 4 3
R
M --B
C6 2 2 06 3 2 E6 4 2 F6 4 3
R
4
3
3
EC
FC
M:M
+
1
--0
2
2
DC
5
CC 3
5
R
68 6 2 7B 6 3
4B 2 1
~~ 11111111'-0
58 2 1
b7
bO
05 3 1

.-

• ••••
••

-

qllili II J+fI

••

•

,

••

•
•
••
•

••
•
•

-

MOTOROLA' MICROPROCESSOR .DATA

3-201

••
••

••

I

MC68701

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2)
Accumulator and
Memory Operations
Shift Right.
Logical

Multiply
2's Complement
(Negate)
No Operation
Inclusive OR
Push Data
Pull Data
Rotate Left

I

. Rotate Right

Subtract Acmltr
Subtract with
Carry
Store Acmltrs

Subtract

MNE
LSR
LSRA
LSRB
LSRD
MUL
NEG
NEGA
NEGB
NOP
ORAA
ORAB
PSHA
PSHB
PULA
PULB
ROL
ROLA
ROLB
ROR
RORA
RORB
SBA
SBCA
SBCB
STAA
STAB
STD
SUBA
S~BB

Subtract Double
Transfer Acmltr
Test, Zero or
Minus

SUBD
TAB
TBA
TST
TSTA
TSTS

Extend
Index
Immed
Direct
Inher
# Op
Op # Op- #
# Op - # Op
64 6 2 74 6 3
44 2 1
54 2 1
04 3 1
3D 10 1
60 6 2 70 6 3
40 2 1
50 2 1
01 2 1
8A 2 2 9A 3 2 AA 4 2 BA 4 3
CA 2 2 DA 3 2 EA 4 2 FA 4 3
36 3 1
37 3 1
32 4 1
33 4 1
69 6 2 79 6 3
49 2 1
59 2 1
66 6 2 76 6 3
46 2 1
56 2 1
10 2 1
82 2 2 92 3 2 A2 4 2 B2 4 3
C2 2 2 02 3 2 E2 4 2 F2 4 3
97 3 2 A7 4 2 B7 4 3
07 3 2 E7 4 2 F7 4 3
DO 4 2 ED 5 2 FD 5 3
80 2 2 90 3 2 AO 4 2 BO 4 3
CO 2 2 DO 3 2 EO 4 2 FO 4 3
83 4 3 93 5 2 A3 6 2 B3 6 3
16 2 1
17 2. 1
60 6 2 70 6 3
40 2 1
50 2 1

-

- :.••

Boole.n
Expre ..ion

-

o-I!
07 " "

AXB-D
00 - M-M
00 - A-A
00 - B--B
PC+ 1 -PC
A + M--A
B + M --B
A -Stack
B -Stack
Stack -A
Stack -B

-

~b7Ii Ii " IbOM-&J

--

•r .•I •I
t

,

I I
I ~

•t •t • ••
I t
•• • • ••
•• ••• ••• ••
•
I I I I
R
R

,

I

I

\

I

I

I

t

~"""I~
b7
bO
A - B--A
A-M-C-A
B - M - C-B
A-M
B --M
o -M:M + 1
A - M--A
B -M-B
0- M:M + 1-0
A--B
B-A
M -00
A-OO
B - 00

The condition code register notes are listed after Table 12.

MOTOROLA MICROPROCESSOR DATA
3-202

I IbO~

Condition Code.
H
N Z V C
R
R
R
R

,

R
R
R

I

••
•I

1
I I

••

I

R
R
R R
R R
R R

MC68701

TABLE 11 - ·JUMP AND BRANCH INSTRUCTIONS

Direct
Operations

MNEM Op -

,

Op -

,

Relative

Index
Op -

,

,

Extend
Op -

Condition Code Reg.

,

Inherent
Op -

Branch Test

Branch Always

BRA

20 3

2

None

Branch Never

BRN

21

3

2

None

Branch If Carry Clear

BCC

24

3

2

C=O

~ranch

BCS

25 3

2

C=1

BEG

27

2

Z=1

Branch If i!:Zero

BGE

2C 3

2

NEDV=O

Branch If >Zero

BGT

2E 3

2

Z+ IN ED V)=O

Branch If Higher

BHI

22 3

2

C+Z=O

Branch If Higher or Same

BHS

24

3

2

C=O

Branch If :sZero

BlE

2F 3

2

Z+IN ED V)=1

Branch If Carry Set

BlO

25 3

2

C=1

Branch If lower Or Same

BlS

23 3

2

C+Z=1

Branch If 
.!!

;::

E
.§

..

!
II

!II

II

E
.§

II

•••
•••
••
•3

INX
JMP
JSR
lDA
lDD
lDS
lDX
lSl
lSlD
lSR
lSRD
MUl
NEG
NOP
ORA
PSH
PSHX
PUl
PUlX
ROl
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

3
3
3
3
3
3

•3
3
3
3
3
3
3
3
3
6
3
3

2
2
2
2
2

•2
•
2
2
3
3

•
•3

•••
2
3
3
3

••
•

•
••
•2
•••
••
•
••
•2
•••
••
••2
••
•
••
••
••
4

MOTOROLA MICROPROCESSOR DATA
3-204

'i

ti
!

~

C

!)(

~

II
)(

II

~

C
f

II

.t:.

is

w

.=

.=

••5

•3

•

3

3
4
4
4

••
••
••
•3
••
•••
•
•••
3
••
•3
4
4

4
3
5

•••
••
•
•••

6
4
5
5
5
6

•
••
•
••
••
••
•
••
•
6

6

4

6
6

4

4

5
5
5
4

6

•••
••6
••

•

3
6
4

5
5
5
6

•6
••
6
•
••
••
4

6
6

••
•4
•
••
4
5
5
5
4
6

•••
••
•••
6

••
••
••2
3
2
3
10
2
2

II

.~

..•

i
"i
a:

•••
••
••
••
••

•
3
4
4

5
2
2
10
5
2

•2
2
2

•
••

••
•
12
2
2
2

2
2
3
3

s

•

MC68701

SUMMARY OF CYCLE-BY-CYCLE OPERATION
per instruction. In general, instructions with the same addressing mode and number of cycles execute in the same
manner. Exceptions are indicated in the table.
Note that during MPU reads of internal locations, the
resultant value will not appear on the external Data Bus except in Mode O. "High order" byte refers to the most significant byte of a 16-bit value.

Table 14 provides a detailed description of the information
present on the Address Bus, Data Bus, and the Read/Write
(R/W) line during each cycle of each instruction.
The information is useful in comparing actual with expected results during debug of both software and hardware
as the program is executed. The information is categorized in
groups according to addressing mode and number of cycles

TABLE 14 -

Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5)

R/W
Address Bus

Data Bus

Line

IMMEDIATE
2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Operand Data

LOS
LOX
LDD

3

1
2

Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Operand Data (High Order Byte)
OpeFand Data (Low Order Byte)

CPX
SUBD
ADDD

4

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address Bus FFFF

1
1
1
1

Upcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address of Operand

1
1
1

Opcode
Address of Operand
Operand Data

Opcode Address
Opcode Address + 1
Destination Address

1
1

0

Opcode
Destination Address
Data from Accumulator

Opcode Address
Opcode Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Address of Operand
Address of Operand + 1

1
1

0
0

Opcode
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Subroutine Address
Stack Pointer
Stack Pointer-l

1
1
1

Opcode
Irrelevant Data
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (High Order Byte)

ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

3
1
2

3
4

DIRECT
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBe
SUB

3

1
2

3

STA

3

LDS
LOX
LDD

4

STS
STX
STD

4

CPX
SUBD
ADDD

5

JSR

5

1
2

3
1
2

3
4
1
2

3
4
1
2

3
4

5
1
2

3
4

5

0
0

MOTOROLA MICROPROCESSOR DATA

3-205

II

MC68701

TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 2 of 5)

R/IN

Addr818 Mode and
Instructions
EXTENDED
JMP

3

1
2

3
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

STA

4

1
2

3
4
4

1
2

3
4

I

LOS
LOX
LDD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC

1
2

3
4
5
1
2

3
4
5
LSR
NEG
ROL
ROR
TST*

6

CPX
SUBD
ADDD

6

JSR

6

1
2

3
4
5
6
1
2

3
4
5
6
1
2

3
4
5
6

Data Bus

Line

Addr818 Bus
Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand

1
1
1
1

Opcode
Address of Operand
Address of Operand (Low Order Byte)
Operand Data

Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Destination Address

1
1
1

Opcode
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data froin Accumulator

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1
Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1
Opcode Address
Opcode Address+ 1
Opcode Address + 2
Address of Operand
Address Bus FFFF
Address of Operand
Opcode Address
Opcode Address + 1
Opcode Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF
Opcode Address
Opcode Address+ 1
Opcode Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer-l

0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1

1
0
0

Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Opcode
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Opcode
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

* TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF.

MOTOROLA MICROPROCESSOR DATA

3-206

MC687Ql

TABLE 14 - CYCLE.BY-CYCLE OPERATION ISheet 3 of 5)

Rlw

Address Mode and
Instructions
INDEXED

Address Bus

JMP

ADC
ADD
AND
BIT
CMP

3

EOR
LOA
ORA
SBC
SUB

4

1
2
3
1
2
3
4

STA

4

LDS
LDX
LDD

5

1
2
3
4

1
2
3
4

5

STS
STX
STD

5
1
2
3
4

ASL
ASR
CLl1
COM
DEC
INC
CPX
SUBD
ADDD

6

LSR
NEG
ROL
ROR
TST*

5
1
2
3
4

5
.. 6

..

6

1
2

3.
4

5
JSR

6

6
1

2
3
4

5
6

Line

Opcode Address
Opcode Address + 1
Address Bus FFFF
Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Opcode Address
Opcode Address + 1
Address Bus FFFF
Index. Register Plus Offset
Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register PillS Offset
I ndex Register Plus Offset + 1
Opcode Address
Opcode Address + 1
Address Bus FFFF
I ndex Register Plus Offset
Index Register Plus Offset + 1
Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset

1
1
1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector

1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data

0

1
1
1
1
1
1
1
1
0
0

1
1
1
1
1
0

Opcode
Offset
Low Byte of RestartVector
Operand Data

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Opcode
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF.
Index Register + Offset
Index Register + Offset + 1
Address BuSFFFF

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer-l

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

*TST does not perform the write cycle during the sixth cycle. The sixth cycle is another address bus= $FFFF.

MOTOROLA MICROPROCESSOR DATA

3.207

..

II

MC68701

TABLE 14 - CYCLE-BY~CYCLE OPERATION (Sheet 4 of 5)

Address Mode and
Instructions
INHERENT
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM

I

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

R/W
Line

Address Bus

Data Bus

2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Opcode of Next Instruction

ABX

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte ofAestart Vector

ASLD
LSRD

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of-Restart Vector

DES
INS

3

1
2
3

Opcode Address
Opcode Address + 1
Previous Stack Pointer Contents

1
1
1

.Opcode
Opcode of Next Instruction
Irrelevant Data

INX
DEX

3

Opcode Address
Opcode Address +1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PSHA
PSHB

3

1
2
3
1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1

0

Opcode
Opcode of Next Instruction
Accumulator Data

TSX

3

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

TXS

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PULA
PULB

4

1
2
3
4

Opcode Address
OpcodeAddress+ 1
Stack Pointer
Stack Pointer + 1

1
1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data
Operand Data from Stack

PSHX

4

1
,2
3
4

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-1

1
1

0
0

Opcode
Irrelevant Data
Index Register (Low Order Byte)
Index Register (High Order Byte)

1
2
3
4
5
1
2
3
4
5

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer + 2
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer + 2

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrellwant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Opcode
Irrelevant Data
Irrelevant Data
Address of Next Instruction (High Order Byte)
Address of Next Instruction (Low Order Byte)

1
2
3
4
5
6
7

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-l
Stack Pointer- 2
Stack Pointer- 3
Stack Pointer-4
Stack Pointer- 5
Stack Pointer-6

1
1

Opcode
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Cpndition Code f!E!gister

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

PULX

5

RTS

5

WAI

9

8
9

0
0
0
0
0
0
0

MOTOROLA MICROPROCESSOR DATA
3-208

MC68701

TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5)
Address Mode and
Instructions
INHERENT
MUL

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer + 2
Stack Pointer+3
Stack Pointer+4
Stack Pointer + 5
Stack Pointer + 6
Stack Pointer + 7

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Contents of Condition Code Register from Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order Byte)
Index Register from Stack (Low Order Byte)
Next Instruction Address from Stack (High Order Byte)
Next Instruction Address from Stack (Low Order Byte)

10
11
12

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-l
Stack Pointer - 2
Stack Pointer - 3
Stack Pointer - 4
Stack Pointer - 5
Stack Pointer - 6
Stack Pointer- 7
Vector Address FFFA (Hex)
Vector Address FFFB (Hex)

1
1
0
0
0
0
0
0
0
1
1
1

Opcode
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register
Irrelevant Data
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)

3

1
2
3

Op Code Address
Op Code Address + 1
Address Bus FFFF

1
1
1

Op Code
Branch Offset
Low Byte of Restart Vector

6

1
2
3
4

Op Code' Address
Op Code Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack POinter
Stack Pointer -1

1
1
1
1

Op Code
Branch Offset
Low Byte of Restart Vector
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address(Hlgh Order Byte)

1
2
3
4
5
6
7

8
9
10

1
2
3
4
5
6
7

8
9
10
SWI

12

1
2
3
4
5
6
7

8
9

RELATIVE
BCC BHT BNE BLO
BCS BLE BPL BHS
BEQ BlS BRA BRN
BGE BlT BVe
BGT BMT BVS
BSR

Data Bus

Opcode Address
Opcode Address + 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

10

10
RTI

R/W
Line

Address Bus

5

6

0
0

MOTOROLA MICROPROCESSOR DATA
3-209

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

I

FIGURE 24 -

•

SPECIAL OPERATIONS

SWI, Software Interrupt

JSR, Jump to Subroutine
~

$9D=JSR
Direct

{

RTN

Next Main Instr.
K = Direct Address
Main Program

s:

a

~

INDXD

{

$AD=JSR
K=Offset

RTN

I

~

S."

SP

Next Main Instr.

Co\)

n

::D

~ o
"a
o ::D
o
(')

m
en
o::D

~

EXTND

[

RTN

AcmltrA

SP-3

Index Register (XHI

SP-2

Index Register (XL)
RTNH
RTNL
L

RTNL

Ef

I

$BD=JSR

~

Ie)

Stack

SP
Condition Code

SP+l
SP+2

AcmltrB

s:

SL= Subr. Addr.

SP+3

AcmltrA

0')

Next Main Inst.

SP+4

Index Register.(XH)

......

SP+5

Index Register.(XLI

SP+6

RTNH

SP+7

RTNL

~

Main Program
$8D=BSR

± K=Offset
RTN I

AcmltrB

SP-4

SH = Subr. Addr.

BSR, Branch To Subroutine
~

Condition Code

SP-6
SP-5

SP

f m Interrupt

~

Stack

SP-7

SP-l

An. A"wm "

s:

I¢~

WAI, Wait for Interrupt

Main Program

!j;

$3F= SWI

¢~:;::~

::D

o

SP

Main Program

R~ I

Main Program

¢~

Next Main Instr.

RTS, Return from Subroutine

Subroutine

~

$39=RTS

SP-2
SP-l
SP

rn

~

Q

Stack

RTNH

Ef

JMP, Jump

RTNL

Stack

SP~

~

~

SP+l'

RTNH'

SP+2

RTNL

Legend:
RTN = Address of next instruction in Main Program to be executed upon return from subroutine
RTNH = Most significant byte of Return Address
RTNL = Least significant byte of Return Address
- = Stack Pointer After Execution
K = 8-bit Unsigned Value

.Main Program

PC

INDXD
[

x~

$7E=JMP

I Next Instruction

KH = Next Address

E'W_{

KL = Next Address

K

I

Next Instruction

C')

CO

C)
..;.a

MC68701

EPROM PROGRAMMING ROUTINE

PAGE
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058

001

EPROM

.SA:1

EPROM
NAM
OPT
TTL

***

ROUTINE TO PROGRAM THE MC68701 EPROM

***

EPROM
ZOl.LLEN=80
*** ROUTINE TO PROGRAM THE MC68701 EPROM

**

*********************************************************

**

*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*

E PRO M -- A NON-REENTRANT ROUTINE
THE MC68701 EPROM.

CALLING CONVENTION:
JSR

EPROM

NOTES:
1.

THE ROUTINE EXPECTS FOUR DOUBLE BYTE VALUES
TO BE INITIALIZED PRIOR TO BEING CALLED.
THESE VALUES ARE:
IMBEG

= A DOUBLE BYTE ADDRESS WHICH POINTS
TO THE FIRST BYTE TO
INTO THE EPROM.

IMEND

PNTR

WAIT

*
*
*
*

*

PROGRAMMED

= A DOUBLE

BYTE ADDRESS WHICH POINTS
TO THE FIRST BYTE IN THE EPROM .TO BE
PROG RAMMED.

A DOUBLE BYTE COUNTER VALUE WHICH IS
A FUNCTION OF THE MCU INPUT FREQUENCY AND IS USED WITH THE OUTPUT COMPARE FUNCTION TO GENERATE A 50 MSEC
TIMEOUT. IT IS EQUIVALENT TO

*

(MCU INPUT FREQ)

4 * 10**6

VALUES FOR TYPICAL INPUT FREQS

*

*
*

BE

A DOUBLE BYTE ADDRESS WHICH POINTS
TO THE LAST BYTE TO BE PROGRAMED ININTO THE EPROM.

50000

*
*
*

*
*
*

PROGRAM

THE ROUTINE PROGRAMS THE MC68701 EPROM
STARTING AT ADDRESS "PNTR" FROM A
BLOCK OF MEMORY STARTING AT "IMBEG"
AND ENDING AT "IMEND".

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*

TO

ARE:

WAIT

MCU INPUT FREQ

30615 ($7797)
50000 ($C350)
61375 ($EFBF)

2.45 MHZ
4.00 MHZ
4.91 MHZ

2.

IT IS ASSUMED THAT POWER (VPP) IS
TO THE RESET PIN FOR PROGRAMMING.

AVAILABLE

3.

THIS ROUTINE

CHECKING.

PERFORMS

NO

ERROR

Routine parameter initialization, such as stack pointer, etc., must be done prior to entry.
(Use of PRObug will ensure all needed initialization)

MOTOROLA MICROPROCESSOR DATA

3-211

II

MC68701

EPROM PROGRAMMING ROUTINE

PAGE

I

002

EPROM

.SA:l

EPROM

*** ROUTINE TO PROGRAM THE MC68701 EPROM ***

00060
00061
* E QUA T E S
00062
00063
TIMER CONTROL/STAT REGISTER
$08
0008 A TCSR
EQU
00064
COUNTER REGISTER
$09
0009 A TIMER EQU
OUTPUT COMPARE REGISTER
00065
OOOB A OUTCMP EQU
SOB
RAM/EPROM CONTROL REGISTER
00066
0014 A EPMCNT EQU
$14
00067
00068
* L 0 CAL V A R I A B L E S
00069
00070A 0080
$80
ORG
START OF MEMORY BLOCK
2
0007lA 0080
0002 A IMBEG RMB
LAST BYTE OF MEMORY BLOCK
2
00072A 0082
0002 A IMEND RMB
FIRST BYTE OF EPROM TO BE PGM'D
2
00073A 0084
0002 A PNTR
RMB
COUNTER VALUE
2
00074A 0086
0002 A WAIT
RMB
00075
00076
* E PRO M S TAR T S HER E
00077
$3000
00078A 3000
ORG
SAVE CALLING ARGUMENT
A EPROM LDX
PNTR
00079A 3000 DE 84
RESTORE WHEN DONE
PSHX
00080A 3002 3C
IMBEG
USE STACK
00081A 3003 DE 80
A
LDX
00082
SAVE POINTER ON STACK
EPR002 PSHX
00083A 3005 3C
REMOVE VPP, SET LATCH
00084A 3006 86 FE
LDAA
tl$FE
A
PPC=l, PLC=O
EPMCNT
00085A 3008 97 14
A
STAA
MOVE DATA MEMORY-TO-LATCH
X
LDAA
00086A 300A A6 00
A
GET WHERE TO PUT IT
PNTR
A
00087A 300C DE 84
LDX
X
STASH AND LATCH
00088A 300E A7 00
STAA
A
NEXT ADDR
INX
00089A 3010 08
PNTR
ALL SET FOR NEXT
STX
00090A 3011 DF 84
A
ENABLE EPROM POWER (VPP)
tl$FC
00091A 3013 86 FC
A
LDAA
EPMCNT
PPC=O, PLC=O
A
00092A 3015 97 14
STAA
00093
* NOW WAIT FOR 50 MSEC TIMEOUT USING OUTPUT COMPARE.
00094
00095
GET CYCLE COUNTER
LDD
WAIT
00096A 3017 DC 86
A
BUMP CURRENT VALUE
ADDD
TIMER
00097A 3019D309
A
CLEAR OCF
CLR
TCSR
00098A 301B 7F 0008 A
SET OUTPUT COMPARE
OUTCMP
00099A 30lE DD OB
A
STD
NOW WAIT FOR OCF
OOIOOA 3020 86 40
A
LDAA
11$40
00101
00102A 3022 95 08
A EPR004 BITA
TCSR
NOT YET
00103A 3024 27 FC 3022
BEQ
EPR004
SETUP FOR NEXT ONE
00104A 3026 38
PULX
00105A 3027 08
INX
NEXT
00106A 3028 9C 82
A
CPX
IMEND
MAYBE DONE
NOT YET
00107A 302A 23 D9 3005
BLS
EPR002
OOl08A 302C 86 FF
A
LDAA
REMOVE VPP, INHIBIT LATCH
II$FF
EPROM CAN NOW BE READ
00109A 302E 97 14
A
STAA
EPMCNT
RESTORE PNTR
OOllOA 3030 38
PULX
00111A303l DF 84
A
STX
PNTR
THAT'S ALL
00112A 3033 39
RTS
00113
END
TOTAL ERRORS 00000--00000

MOTOROLA MICROPROCESSOR DATA
3-212

MC68701

ORDERING INFORMATION
The following table provides generic information pertaining to the package type and temperature for the MC68701.
The MCU device is available only in the 40-pin dual-in-line (DIP) package in the Cerdip and Plastic packages.

GENERIC INFORMATION
Frequency
(MHz)

Temperature
(Degrees C)

Cerdip Package
(5 Suffix)

Ceramic Package
(L Suffix)

1.0
1.0
1.25
1.25
2.0

o to 70
-40 to +85
o to 70
-40 to +85
o to 70

MC68701S
MC68701CS
MC68701S-1
MC68701 CS-1
MC68B701S

MC68701L
MC68701CL
MC68701L-1
MC68701CL:1
MC68B701L

I

PIN ASSIGNMENT

Vss
XTAL

L

SCl

EXTAL

3

SC2

NMI

4

P30

IRQl

b

P3l

RESETlVpp 6

P32

Vee

7

P33

P20

8

P34
P35

P22
P23

P36
P37

'1

P24
Pl0

P40
P41

Pll

P42

P12

P43

P13

P44

P14

P45

P15

P46

P16

P47

P17

21

Vee

Standby

MOTOROLA MICROPROCESSOR DATA

3-213

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC68701U4
Advance Information

8-Bit EPROM Microcontroller/Microprocessor
(MCU/MPU)

I

The MC68701 U4 is an 8-bit single-chip EPROM microcontroller unit (MCU) which enhances the
capabilities of the MC6801 and significantly enhances the capabilities of the M6800 Family of parts.
It includes an MC6801 microprocessor unit (MPU) with direct object-code compatibility and upward
object-code compatibility with the MC6800. Execution times of key instructions have been improved
over the MC6800 and the new instructions found on the MC6801 are included. The MCU can function as a monolithic microcontroller or can be expanded to a 64K byte address space. It is TTL
compatible and requires one + 5-volt power supply for nonprogramming operation. An additional
Vpp power supply is needed for EPROM programming. On-chip resources include 4096 bytes of
EPROM, 192 bytes of RAM, a serial communications interface (SCI), parallel I/O, and a 16-bit sixfunction programmable timer.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Enhanced MC6800 Instruction Set
Upward Source and Object Code Compatibility with the MC6800, MC6801, and MC6801 U4
Bus Compatibility with the M6800 Family
8 x 8 Multiply Instruction
Single-Chip or Expanded Operation of 64K Byte Address Space
Internal Clock Generator with Divide-by-Four Output
Serial Communications Interface (SCI)
16-Bit Six-Function Programmable Timer
Three Output Compare Functions
Two Input Capture Functions
Counter Alternate Address
4096 Bytes of Use EPROM
192 Bytes of RAM
32 Bytes of RAM Retainable During Power Down
29 Parallel I/O and Two Handshake Control Lines
NMI Inhibited Until Stack Load

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-214

BLOCK DIAGRAM
c...
c...

>

~
I~w
t5 ~~x~w wlzl~
~ a~
~«

> >

~

Expanded Multiplexed
Expanded Non-Multiplexed
Single Chip

3:

0
~
0
~
0
r-

»

3:

w

c=;

P37
P36
P35
P34
P33
P32
P3l
P30
SC2
SCl

A7/D7
A6/D6
A5/D5
A4/D4
A31D3
A2/D2
Al/Dl
AO/DO
R/W
AS

D7
D6
D5
D4
D3
D2
Dl
DO
R/W
lOS

110
110
110
1/0
1/0
110
110
1/0
OS3
IS3

0::

Illl;;g
~ ~ If f ~~
Port
2

Mux
Port

~ ~

RDATA
TDATA

110
1/0
1/0
1/0
1/0

s:

SCI

:J:J

N
.... 0

U1

TINl
TOUTl
SCLK

!

"'tI
~

0

C')

m

(J)
(J)

(')

en

CO
-.J

0

~

c:

I

~

0

:xJ
C

el

P47
P46
P45
P44
P43
P42
P4l
P40

A15
A14
A13
A12
All
Ala
A9
A8

A7
A6
A5
A4
A3
A2
Al
AO

1/0
1/0
1/0
1/0
1/0
!/O
1/0
1/0

~

Port
1

Port
4

l60x8
RAM

VCC Standby ~

32x 8
Standby
RAM

I I

-..-J

4096 x 8
EPROM

Pl0
Pll
P12
P13
P14
P15
P16
P17

TIN2
TOUT2
TOUT3

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

MC68701U4

MAXIMUM RATINGS
Rating

Symbol

Value

Unit
V

Vee

-0.3 to + 7.0

Input Voltage

Tin

-0.3 to + 7.0

V

Operating Temperature Range

TA

o to 70

°e

Tstg

-40 to +85
-55 to + 150

°e

Supply Voltage

Storage Temperature Range
Programmed
Unprogrammed

THERMAL CHARACTERISTICS

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid applications of any voltage higher than
maximum rated voltages to this highimpedance circuit. For proper operation it is
recommended that Vin and Vout be constrained to the range GND:s(Vin or
Vout):sVee·
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
GND or Vee).

Characteristic
Thermal Resistance eerdip

I

POWER CONSIDERATIONS

The average chip-junction temperature, Tj, in DC can be obtained from:
(1)

Tj=TA +(PD· 0JA)
where:
TA
tljA
PD
PINT
PpORT

= Ambient Temperature, DC
= Package Thermal Resistance,
junction-to-Ambient, DC/W
= PINT+ PPORT
= ICC x VCC' Watts - Chip Internal Power
= Port Power Dissipation, Watts - User Determined

For most applicationsPpORT (>
<~ <~ Rl

? (

8

P20

9

P21

10

P22
V

),0,
Mode Control Switches

<<

~, ~

II

P21 (PC1)
P22 (PC2)

9

0, C
(

P20 (PCO)

, '0
~

~

MC68701U4

.. R2

<>

Vo
"Normal"

"'"

S1

VPP

~

6

RESETlVpp

-~C

o-:----o----A

T

"Program"

FIGURE 16 -

NOTES:
1. Mode 0 as shown (switches closed).
2. Rl "" 10 kilohms (typical).
3. The RESET time constant is equal to RC where R
is the equivalent parallel resistance of R2 and the
number of resistors (Rl) placed in the circuit by
closed mode contol switches.
4. D"" 1N914, 1N4001 in the 0 to 70'C range
0"" lN270, MBD201 in the -40 to 85'C range
5. If V =Vc.w..!!:!!l R2 = 50 ohms (typical) to meet VIH
for the RESETNpp pin. V"" VCC is also compatible
with MC6801 U4. The RESET time constant in this
case is approximately R2 x C.
6. Switch S1 allows selection of normal (RESET) or
programming (Vpp) as the input to the RESETNpp
pin. During switching, the input level is held at a
value determined by a diode (D), resistor (R2) and
input voltage (V).
7. While Sl in the "Program" position, RESET should
not be asserted.
8. From powerup, RESET must be held low for at
least tRC' The capacitor, C; is shown for conceptual purposes only and is on~he order of 1000 fJoF
for the circuit shown. Typicall~ffer with an
RC input will be used to drive RESET, eliminating
. the need for the larger capacitor.
9. Diode Vf should not exceed VMPDD min.

MEMORY MAPS (Sheet 1 of 3)

Multiplexed Test/Program Mode
$0000(1)
$OO1F 1"-"-"-"""-'""-'""1

Internal
Registers
External
Memory Space

MC68701U4
Mode

o

Internal
RAM

External
Memory Space
External
$BFFO
$BFFF ~7"7""7"7""rrrl, Interrupt Vectors(2)
$FOOO

..,.,.,..,..,..,..,...,...,.;~

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.
2) The interrupt vectors are at $BFFO-$BFFF.
3) There must be no overlapping of internal and
external memory spaces to avoid driving the,
data bus with more than one device,

4) This mode is used to program the on-chip
EPROM.
5) Modes 5-7 can be irreversibly entered from
mode 0 by writing to the PCO-PC2 bits of the
port 2 da.ta. register.

MOTOROLA MICROPROCESSOR DATA
3-226

FIGURE 16 -

MEMORY MAPS (Sheet 2 of 31

MC68701U4
Mode

MC68701U41
Mode

Multiplexed/RAM and EPROM

Multiplexed/ RAM

$0000(1)

$0000(1)

$001F ru/uu ;; u.> ,

r( /(

~

$~
$001 F

External
Memory Space

0

o
n

I

External
Memory Space
Internal
RAM

«

$0040

II

U ,:~~~ S~re

Internal
EPROM
External
Interrupt Vectors

$OOFF

::::~

1

I)

External
Interrupt Vectors

$FFFO
$FFFF

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $06, and $OF,
2) Internal EPROM addresses $FFFO to $FFFF are not
usable,
3) Address lines A8-A15 will not contain addresses
until the data direction register for port 4 has been
written with "1s" in the appropriate bits. These
address lines will assert "1s" until made outputs
by writing the data direction register.

NOTE:
1) Excludes the following addresses which may be
used externally: $04, $05, $06, $07, and $OF.

External

Reglsters( 1, 2)
External

I"",»" J-!

<

1

3

$0000(11

{(I< Registers

/ ; ; ) ) ) ) ) dol

r«

MC68701U4
Mode

Multiplexed/ RAM
Internal

$001F

$ooFF

2

IU «

I

«

Memory Space
Internal
RAM(1)

/ ( { ~~

Ii

External
Memory Space
External
Interrupt Vectors

NOTES:
1) Relocating the internal registers and the internal RAM to high memory allows the processor
to make use of direct addressing.
2) Excludes the following addresses which may be
used externally: $0004, $0005, $0006, $0007,
and $OooF.

s:
C')

0')

....0

CO

~

c:
~

FIGURE 16 -

MC68701U4
Mode

5

Non-Multiplexed/Partial Decode

$0000111 ~} 1",,",1
$001 F

Registers

3:

$0040

d::g

$OOFF

~

$01 FF

o

o

$0100

II)
"

MC68701U4
Mode

111
$001 F
$0040

Internal

RAM

1

=11""",1

$0000 ~} Internal
$001 F
Registers
$0040
$OOFF

Memory Space
External
Memory Space

o

i
Unusable

s:0
Q)

00

.....

0
..a

$FOOO .."......,.~.,....,.,""7'"l

C/)
C/)

Internal
EPROM

o

::g
$FFFF

!{«{({«(,

C

$FOOO

m

c
~

7

Single Chip
Registers
External
Memory Space
Internal
RAM

External

::g

~ o
""CI
co ::g
o(")

MC68701U4
Mode

$OOFF

3:

w

6

Multiplexed/Partial Decode

$OCOO

Unusable

•

MEMORY MAPS (Sheet 3 of 3)

Internal
Interrupt Vectors

~

Internal
EPROM
Internal
Interrupt Vectors

$FFFF

l>
NOTES:
1) Excludes the following addresses which may
not be used externally: $04, $06, and $OF (no
lOS).
2) Address lines AO to A7 will not contain addresses until the data direction register for port
4 has been written with" 1s" in the appropriate
bits. These address lines will assert "ls" until
made outputs by writing the data direction
register.

$FOOO

NOTES:
1) Excludes the following addresses which may be
used externally: $04, $06, $OF.
2) Address lines A8-A15 will not contain addresses until the data direction register for port
4 has been written with" 1s" in the appropriate
bits. These address lines will assert "ls" until
made outputs by writing the data direction
register.

I(CC«CCCCO

MC68701U4

TABLE 4 - INTERNAL REGISTER AREA

MC68701U4INTERRUPTS

Register
Port 1 Data Direction Register* * *
Port 2 Data Direction Register* * *
Port 1 Data Register
Port 2 Data Register
Port 3 Data Direction Register* * *
Port 4 Data Direction Register* * *
Port 3 Data Register
Port 4 Data Register
Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)
Output Compare Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register
Rate and Mode Control Register
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register
RAM Control Register
Counter Alternate Address (High Byte)
Counter Alternate Address (Low Byte)
Timer Control Register 1
Timer Control Register 2
Timer Status Register
Output Compare Register 2 (High Byte)
Output Compare Register 2 (Low Byte)
Output Compare Register 3 (High Byte)
Output Compare Register 3 (Low Byte)
Input Capture Register 2 (High Byte)
Input Capture Register 2 (Low Byte)

The M6801 Family supports two types of interrupt requests: maskable and non-maskable. A non-maskable interrupt (NMIl is always recognized and acted upon at the completion of the current instruction. Maskable interrupts are
controlled by the condition code register I bit and by individual enable bits. The I bit controls all maskable interrupts. Of the maskable interrupts, there are two types: IRQ1
and IRQ2. The programmable timer and serial communications interface use an internal IRQ2 interrupt line, as shown
in the block diagram. External devices and IS3 use IRQ1. An
IRQ1 interrupt is serviced before IRQ2 if both are pending.

Address
00
01
02
03
04*
05* *
06*
07**
08
09
OA
OB
OC
OD
OE
OF*
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F

NOTE
After reset, an NMI will not be serviced until the first
program load of the stack pointer. Any NMI generated
before this load will be remembered by the processor
and serviced subsequent to the stack pointer load.

All IRQ2 interrupts use hardware prioritized vectors. The
single SCI interrupt and three timer interrupts are serviced in
a prioritized order and each is vectored to a separate location. All interrupt vector locations are shown in Table 5. In
mode 0, reset and interrupt vectors are defined as $BFFO$BFFF
The interrupt flowchart IS depicted in Figure 17 and is
common to every interrupt excluding reset. During interrupt
servicing, the program counter, index register, A accumulator, B accumulator, and condition code register are
pushed to the stack. The I bit is set to inhibit maskable Interrupts and a vector IS fetched corresponding to the current
highest priority interrupt. The vector is transferred to the
program counter and instruction execution is resumed. Interrupt and RESET timing are illustrated in Figures 18 and 19.

* External addresses in modes 0, 1, 2, 3, 5, and 6; cannot be
accessed in mode 5 (no lOS)
* * External addresses in modes 0, 2, and 3
* * * 1 = Output, 0= Input

TABLE 5 - MCU INTERRUPT VECTOR LOCATIONS
Mode 0
BFFF

BFFC
BFFA

Modes 1-3, 5-7
MSB
FFFE

LSB
FFFF

RESET

BFFD

FFFC

FFFD

Non-Maskable Interrupt* *

BFFB
BFF9

FFFA
FFF8

FFFB
FFF9

Software Interrupt
Maskable Interrupt Request 1

BFF6

BFF7

FFF6

FFF7

Input Capture Flag*

BFF4

BFF5

FFF4

FFF5

Output Compare Flag*

BFF8

*

LSB

MSB
BFFE

Interrupt

BFF2

BFF3

FFF2

FFF3

Timer Overflow Flag*

BFFO

BFF1

FFFO

FFF1

Serial Communications Interface*

* IR02 interrupt
* fiJMi must be armed
fiJMi is executed

(by accessing stack pointer) before an

MOTOROLA MICROPROCESSOR DATA
3-229

II

•

FIGURE 17 - INTERRUPT FLOWCHART

s:o

a
:JJ

o

§;
w

s:
n:JJ

3:

n
00
.....
o

c:7)

~ o
"V
:JJ
o

«:)

~

c:

~

~

t/)
t/)

o

:JJ

c.

=
=
=

SCI TIE-TORE + RIEo(RDRF + OR FE)
ICI (lCFloEICll) + (lCF20EICI2)
OCI (OCFloEOCIl) + (OCF20EOCI2) + (OCF30EOCI3)

~

Vector-PC

Mode 0

~

m

BFFC-BFFD

FFFC-FFFD

SWI

BFFA-BFFB

FFFA-FFFB

Software Interrupt

fI!rn

BFFB-BFF9

FFFB-FFF9

Maskable Interrupt Request 1

ICF

BFF6-BFF7

FFF6-FFF7

Input Capture Interrupt

Non-Maskable Interrupt

OCF

BFF4-QFF5

FFF4-FFF5

Output Compare Interrupt

Condition Code Register

TOF

BFF2-BFF3

FFF2-FFF3

Timer Overflow Interrupt

llHHlllNlzlvlc

SCI

BFFO-BFFI

FFFO-FFFI

~

~Cllnterrupt

FIGURE 18 -INTERRUPT SEQUENCE

I 'Cycle

Last Instruction ~

11

#3

12

14

15

16

17

18

PC 8-15

X 0-7

X 8-15

ACCA

ACCB

I1Q

19

III

112

Interal
Address Bus

IRQl

3i:

a
~
):

3i:
Co\)

n

~ ~tpcs

\.

NMlorlRQ2

~

j..-tpcs

Internal
Data Bus
Op Code Op Code

PC.0-7

CCR

\

Internal R/W

Irrelevant
Data

r

s:
n
CJ)

:J:J

o"'a
~
...a

00
.....
o

:lJ

...&

o
(')

FIGURE 19 -

m

CJ)
CJ)

o:lJ
C

~

VCC

&\\\\\\\\\~.~ ~\\'%\%\\\\ ~ ----=::1 F'PCS
7f~4.75V

5.25 V

RESET
Internal
Address Bus

I I

'. >

_'~'

_ ._>
.__
tR_C_.

,I"";"""

..

R/W

Internal'
Data Bus

~rLJ1Slr
tlPCS
~

I

.

_ _ _ .,

~4.0V

OB"'v"loF--

S\\\\\~\\\\\\\\\\'i b\\\\\\\\\\\\\\\\\\\\\\\\\~11...""""--~_...A...._...J\._---J'--_A-_..A..._..J'\..._-J\._....J'\._
FFFE

Internal

c:
,c:..

RESET TIMING

FFFE

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PC 8-15

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PC 0-7

First
Instruction

MC68701U4

it responds to the request. The MCU will then ,begin an interrupt Sequence. Finally, a vector is fetched from $FFFC and
$FFFD ($BFFC and $BFFD in mode 0), transferred to~
program counter, and instruction execution is resumed. N~I
typically requires a 3.3 kG (nominal) resistor to VCC. There IS
no internal NMI pullup resistor. NMI must be held low for at
least one E cycle to be recognized under all conditions.

FUNCTIONAL PIN DESCRIPTIONS
VCC ANDVSS
VCC and VSS provide power to a large portion of the
MCU. The power supply should provide + 5 volts (± 5%) to
VCC and VSS should be tied toground. Total power. ~issipa­
tion (including VCC standby) will not exceed Po mllhwatts.

I

Vcc STANDBY
VCC standby provides power to the standby portion ($40
through $5F) of the RAM and the STBY PWR and RAME
bits of the RAM control register. Voltage requirements depend on whether the device is in a power-up or power-down
state. In the power-up state, the power supply should provide + 5 volts (± 5%) and must reach V S B volts before
RES ET reaches 4.0 volts. During power down, V CC standby
must remain above VSBB (minimum) to sustain the standby
RAM and STBY PWR bit. While in power-down operation,
the standby current will not exceed ISBB.
It is typical to power both VCC and V CC standby from the
same source during normal operation. A diode must be used
between them to prevent supplying power to VCC during
power-down operation.

NOTE
After reset, an NMI will not be serviced until the first
program load of the stack pointer. Any NMI generated
before this load will remain pending by the processor.
IRQ1 (MASKABLE INTERRUPT REQUEST 1)
IRQl is a level-sensitive input which can be used to request an interrupt sequence. The MPUwili complete the current instruction before it responds to the request. If the interrupt mask bit (I bit) in the condition code register is clear, the
MCU will begin an interrupt sequence. A vector is fetched
from $FFFB and $FFF9 ($BFFB and $BFF9 in mode 0),
transferred to the program counter, and instruction execution is resumed.
IRQl typically requires an external 3.3 kG (nominal)
resistor to VCC for wire-OR application. IRQ1 has no internal
pullup resistor.

XTAL AND EXTAL
These two input pins interface either a crystal or TTLcompatible clock to the MCU internal clock generator.
Divide-by-four circuitry is included which allows use of the
inexpensive 3.58 MHz or 4.4336 MHz color burst TV crystals.
A 20 pF capacitor should be tied from each crystal pin to
ground to ensure reliable startup and operation. Alternat~ve­
Iy, EXTAL may be driven by an external TTL-compatible
clock at 4 fo with a duty cycle of 50% (±5%) with XTAL
connected ground.
The internal oscillator is designed to interface with an ATcut quartz crystal resonator' operated in parallel resonance
mode in the frequency range specified for fXT AL· The
crystal should be mounted as close as possible to the input
pins to minimize output distortion and startup stabi.lization
time. The MCU is compatible with most commercially
available crystals. Nominal crystal parameters are shown in
Figure 20.

SCl and SC2 (STROBE CONTROL 1 AND 2)
The function of SCl and SC2 depends on the operating
mode. SCl is configured as an output in all modes except
single-chip mode, whereas SC2 is always an output. SCl
and SC2 can drive one Schottky load and 90 pF.
SC1 AND SC2 IN SINGLE-CHIP MODE - In single-chip
mode, SCl and SC2 are configured as an input and output,
respectively, and both function as port 3 control lines. SCl
functions as I S3 and can be used to indicate that port 3 input
data is ready or output data has been accepted. Three options associated with IS3 are controlled by the port 3 control
and status register and are discussed in the port 3 description; refer to P30-P37 (PORT 3). If unused, IS3 can remain
unconnected.
SC2 is configured as OS3 and can be used to Strobe output data or acknowledge input data. It is controlled by output strobe select (OSS) in the port 3 control and status
register. The strobe is generated by a read (OSS = 0) or write
(OSS = 1) to the port 3 data register. OS3 timing is shown in
Figure 3.

RESETIVpp
This input is used to reset the internal state of the device
and provide an orderly startup procedure. During power up,
RES ET must be held below O.B volts: (1) at least tRC after
V CC reaches 4.75 volts in order to provide su~ficient time for
the clock generator to stabilize, and (2) until V CC standby
reaches 4.75 volts. RESET must be held low at least three E
cycles if asserted during pow~r-up operation.
This pin is also used to supply Vpp in mode 0 for programming the EPROM.

SC1 AND SC2 IN EXPANDED NON-MULTIPLEXED
MODE - In the expanded non-multiplexed mode, both SCl
and SC2 are configured as outputs. SCl functions as input/output select (lOS) and is asserted only when $0100
through $01 FF is sensed on the internal address bus.
SC2 is configured as read/write and is used to control the
direction of data bus transfers.. An MPU read is enabled
when read/write and· E are high.

E (ENABLE)
This is an output clock used primarily for bussynchronization. It is TTL compatible and is the slightly skewed .divideby-four result of the device input clock frequency. It will
drive one Schottky TTL load and 90 pF, and all data given in
cycles is referenced to this clock unless otherwise noted.

SCl AND SC2 IN EXPANDED MULTIPLEXED MODE In the expanded multiplexed modes, both SCl and SC2 are
configured as outputs. SCl functions as address strobe and
can be used to demultiplex the eight least significant addresses and the data bus. A latch controlled by address
strobe captures the lower address on the negative edge, as
shown in Figure 13.

NMI (NON-MASKABLE INTERRUPT)
An NMI negative edge requests an MCU interrupt sequence, but the current instruction will be completed before

MOTOROLA MICROPROCESSOR DATA
3-232

MC68701U4

FIGURE20 - OSCILLATOR CHARACTERISTICS
(al Nominal Recommended Crystal Parameters
Nominal Crystal Parameters*

4.00 MHz
500
6.5 pF
0.025 pF
>30 K

3.58 MHz
RS
CO
Cl
Q

* NOTE:

600
3.5 pF
0.015 pF
>40K

5.0 MHz
30-500
4-6 pF
0.01-0.02 pF
>20 K

These are representative AT-cut crystal parameters only. Crystals of other
types of cut may also be used.

MC68701U4

---------110 1
....- - - - . - - - -

L1

Cl

RS

3

co

CL = 20 pF (typical)

EqUivalent C,rcu,t
NOTE
TTL-compatible oscillators may be
obtained from:
Motorola Component Products
Attn: Crystal Clock Oscillators
2553 N. Edgington SI.
Franklin Park, IL 60131
Tel: 312-451-1000
Telex: 433-0067

(bl Oscillator Stabilization Time (tRcl

1~4-.7-5-V------------~~~'--~-----------------------------

VCC

~---tRC-----)~

Oscillator
Stabilization
Time, tRC

MOTOROLA MICROPROCESSOR DATA
3-233

II

MC68701U4

SC2 is configured as read/write and is used t6 control the
direction of data bus transfers. An MPU read is enabled
when read/write and E are high.

PORT 3 CONTROL AND STATUS REGISTER
7

IPC2

5

4

3

2

PCl

pca

P24

P23

P22

a
P2l

P20

2

x

ass

x

0
X

x

$OF

PORT 3 IN EXPANDED NON-MULTIPLEXED MODE
Port 3 is configured as a bidirectional data bus (07-001 in the
expanded non-multiplexed mode. The direction of data
transfers is controlled by read/write (SC2)' Data is clocked
by E (enable).
PORT 31N EXPANDED MULTIPLEXED MODE - Port 3 is
configured as a time multiplexed address (A7~AOI and data
bus (07-00) in the expanded multiplexed mode where address strobe (AS) can be used to demultiplex the two buses.
Port 3 is held in a high-impedance state between valid address and data to prevent bus conflicts.

PORT 2 DATA REGISTER

6

4

Bits 0-2 Not used.
Bit 3
Latch Enable - This bit controls the input latch for
port 3. If set, input data is latched by an IS3
negative edge. The latch is transparent after a read
of the port 3 data register. Latch enable is cleared
during reset.
Bit 4
OSS (Output Strobe Select) - This bit determines
whether OS3 will be generated by a read or write of
the port 3.data register. When clear, the strobe is
generated by a read; when set, it is generated by a
write. OSS is cleared during reset.
Bit 5
Not used.
Bit 6
IS3 IRQ1 Enable - When set, an IRQ1 interrupt
will be enabled whenever the IS3 flag is set; when
clear, the interrupt is inhibited. This bit is cleared
during reset.
Bit 7
IS3 Flag - This read-only status bit is set by an IS3
negative edge. It is cleared by a read of the port 3
control and status register (with IS3 flag set)
followed by a read or write to the port 3 data
register or during reset.

P20-P24 (PORT 2)
Port 2 is a mode-independent. 5-bit, multipurpose 110
port. The voltage levels present on P20, P21, and P22 on the
rising edge of RESET determine the operating mode of the
MCU. The entire port is then configured as a data input port.
The port 2 lines can be selectively configured as data output
lines by setting the appropriate bits in the port 2 data direction register. The port 2 data register is used to move data
through the port. However, if P21 is configured as an output, it is tied to the timer output compare 1 function and cannot be used to provide output from the port 2 data register
unless output enable 1 (OE1) is cleared in timer control
register 1.
Port 2 can also be used to provide an interface for the
serial communications interface and the timer input edge
function. These configurations are described in SERIAL
COMMUNICATIONS INTERFACE and PROGRAMMABLE
TIMER.
The port 2 three-state TTL-compatible output buffers are
capable of driving one Schottky TTL load and 30 pF, or
CMOS devices using external pullup resistors.

7

5

I I I I~~~~~e

I~~~ ~

P10-P17 (PORT 1)
Port 1 is a mode independent 8-bit I/O and timer port.
Each line can be configured as either an input or output as
defined by the port 1 data direction register. Port 1 bits 0, 1,
and 2 (P10, P11, and P12) can also be used to exercise one
input edge function and two output compare functions of
the timer. The TTL compatible three-state buffers can drive
one Schottky TTL load and 30 pF, Darlington transistors, or
CMOS devices using external pullup resistors. It is configured as a data input port during RESET. Unused pins can
remain unconnected.

II

6

I $03

P40-P47 (PORT 4)
Port 4 is configured as an 8-bit I/O port, as address outputs, or as data inputs depending on the operating mode.
Port 4 can drive one Schottky TTL load and 90 pF, and is the
only port with internal pullup resistors. Unused lines can remain unconnected.

P30-P37 (PORT 3)
Port 3 can be configured as an I/O port, a bidirectional
8-bit data bus, or a multiplexed address/ data bus depending
on the operating mode. The TTL compatible three-state output buffers can drive one Schottky TTL load and 90 pF.
Unused lines can remain unconnected.

PORT 4 IN SINGLE~CHIP MODE - In single-chip mode,
port 4 functions as an 8-bit I/O port with each line configured by the port 4 data direction register. Internal pullup
resistors allow the port to directly interface with CMOS at
5-volt levels. External pullup resistors to more than 5 volts,
however, cannot be used.

PORT 3 IN SINGLE-CHIP MODE - Port 3 is an 8-bit I/O
port in the single-chip mode with each line configured by the
port 3 data direction register. There are also' two lines, IS3
and OS3, which can be used to control port 3 data transfers.
Three port 3 options are controlled by the port 3 control
and status register and are available only in single-chip
mode: 1) port 3 input data can be latched using IS3 (SC1) as
a control signal, 2) OS3 (SC2) can be generated by either an
MPU read or write to the port 3 data register, and 3) an iRO'i
interrupt can be enabled by an IS3 negative edge. Port 3
latch timing is shown in Figure 4.

PORT 4 IN EXPANDED NON-MULTIPLEXED MODE
Port 4 is configured from reset as an 8-bit input port where
the port 4 data direction register can be written· to provide
any or all of eight address lines AO to A7. Internal pullup
resistors pull the lines high until the port 4 data direction
register is configured.

MOTOROLA MICROPROCESSOR DATA
3-234

MC68701U4

Bit 1

PORT 41N EXPANDED MULTIPLEXED MODE - In all expanded multiplexed modes except modes 1 and 6, port 4
functions as half of the address bus and provides AS to A 15.
In modes 1 and 6, the port is configured from reset as an
8-bit parallel input port where the port 4 data direction
register can be written to provide any or all of upper address
lines AS to A 15. Internal pullup resistors pull the lines high
until the port 4 data direction register is configured where bit
a controls AS.

RESIDENT MEMORY

Bit 2-5
Bit 6

The MC687a1 U4 has 192 bytes of on-chip RAM and 4096
bytes of on-chip UV erasable EPROM. This memory is controlled by four bitsin the RAM/EPROM control register.
Thirty-two bytes of the RAM are powered through the
VCC standby pin and are maintainable during VCC powerdown.' This standby portion of the RAM consists of 32 bytes
located from $40 through $5F.
Power must be supplied to V CC standby if the internal
RAM is to be used, regardless of whether standby power
operation is anticipated.
The RAM is controlled by the RAM/ EPROM control
register.

Bit 7

RAM/EPROM CONTROL REGISTER ($14)
The RAM/EPROM control register includes four bits:
STBY PWR, RAME, PLC, and PPC. Two of these bits,
STBY PWR and RAME, are used to control RAM access and
determine the adequacy of the standby power source during
power-down operation. It is intended that RAME be cleared
and STBY PWR be set as part of a power-down procedure.
RAME and STBY PWR are read/write bits.
The remaining two bits, PLC and PPC, control the operation of the EPROM. PLC and PPC are readable in all modes
but can be changed only in mode a. The PLC bit can be written without restriction in mode a,but operation of the PPC
bit is controlled by the state of PLC.
Associated with the EPROM are an 8-bit data latch and a
16-bit address latch. The data latch is enabled at all times,
latching each data byte written to the EPROM: The address
latch is controlled by the PLC bit.
A description of the RAM/EPROM control register
follows.
RAM/EPROM CONTROL REGISTER
76543210

I;~~
Bit a

IRAMEI

X

I

X

I

X

I I
X

PPC

I PLC

Programming Power Control (PPC). This bit gates
power from the rntTIVpp pin to the EPROM
programming circuit. PPC is set during reset and
whenever the PLC bit is set. It can be cleared only if
operating in mode a, and if PLC has been previously cleared. The PPC bit is defined as follows:
PPC=O-EPROM programming power (Vpp)
applied.
PPC = 1, - EPROM programming power (Vpp) is
not applied.
Unused.
RAM Enable (RAME). This read/write bit can be
used to remove the entire RAM from the internal
memory map. RAME is set (enabled) during reset
provided standby power is available on the positive
edge of reset. If RAME is clear, any access to a
RAM address is external. If RAME is set, the RAM
is included in the internal map.
Standby Power (STBY PWR). This bit is a
read/write status bit which when cleared indicates
that V CC standby has decreased sufficiently below
VSBB (minimum) to make data in the standby
RAM suspect. It can be set only by software and is
not affected during reset.

Note that if PPC and PLC are set, they cannot be
simultaneously cleared with a single MPU write. The PLC bit
must be cleared prior to attempting to clear PPC. If both PPC
and PLC are clear, setting PLC will also set PPC. In addition,
it is assumed that Vpp is applied to theHESETIVpp pin
whenever PCC is clear. If this is not the case, the result is
undefined.
ERASING THE MC68701 U4 EPROM
Ultraviolet erasure will clear all bits of the EPROM to the
zero state. The MC68701 U4 EPROM is programmed byerasing it to zeros and entering ones into the desired bit locations.
The MC68701 U4 EPROM can be erased by exposure to
high intensity ultraviolet light with a wave length of 2537
angstroms for a minimum of 30 minutes. The recommended
integrated dose (ultraviolet intensity times exposure time) is
15 watts/centimeter. The lamps should be used without
shortwave filters, the M C68701 U4 should be positioned
about one inch away from the ultraviolet tubes, and the
transparent lid should not be covered.
The MC68701 U4 transparent lid should always be covered
after erasing. This protects both the EPROM and lightsensitive nodes from accidental exposure to ultraviolet light.

I

$14

Programming Latch Control (PLC). This bit controls the latch which captures the EPROM address
to be programmed and whether the PCC bit can be
cleared. The latch is triggered by an MPU write to a
location in the EPROM. This bit is set during reset
and can be cleared only in mode O. The PLC bit is
defined as follows:
PLC = 0- EPROM address latch enabled; EPROM
address is latched during MPU writes to
the EPROM.
PLC = 1- EPROM address latch is transparent.

PROGRAMMING THE MC68701U4 EPROM
When the M C68701 U4 is released from reset in mode 0, a
vector is fetched from location $BFFE:$BFFF. This provides
a method for an external program to obtain control of the
microcomputer with access to every location in the EPROM.
To program the EPROM, it is necessary to operate the
MC68701U4 in mode 0 under the control of a program resident in external memory which can facilitate loading and programming of the EPROM. After the pattern has been loaded

MOTOROLA MICROPROCESSOR DATA
3~235

II

MC68701U4

I

into external memory, the EPROM can be p(ogrammed as
follows:
a. Apply programming power (VpP) to the RESET /Vpp
pin.
b. Clear the PLC control bit and set the PPCbit by writing
$FE to the RAM/EPROM control register.
c. Write data to the next EPROM location to be programmed. Triggered by an MPU write to the EPROM, internal latches capture both the EPROM address and the
data byte.
d. Clear the PPC bit for programming time, t pp , by writing
$FC to the RAM/EPROM control register and waiting
for time, tpp. This step gates the programming power
(Vpp) from the RESET/Vpp pin to the EPROM which
programs the location.
e. Repeat steps b through d for each byte to be programmed.
f. Set the PLC and PPC bits by writing $FF to the
RAM/ EPROM. control register.
g. Remove the programming power (Vpp) from the
RESET /VPP pin. The EPROM can now be read and
verified.
Because the erased state of an EPROM byte is $00, it is not
necessary to program a location which is to contain $00.
Finally, it should be noted that the result of inadvertently
programming a location more than once is the logical OR of
the data patterns.

OUTPUT COMPARE REGISTEAS ($OB:OC),
($1C:1D)

($1A:1B),

The three output compare registers are 16-bit read/write
registers, each used to control an output waveform or provide an arbitrary time-out flag. They are compared with the
free-running counter during the negative half of each E cycle. When a match occurs, the corresponding output compare flag (OCF) is set and the corresponding output level
(OLVL) is clocked to an output level register. If both the corresponding output enable bit and data direction register bit
are set, the value represented in the output level register will
appear on the corresponding port pin. The appropriate OLVL
bit can then be changed for the next compare.
The function is inhibited for one cyCle after a write to its
high byte ($OB, $1A, or $1C) to ensure a valid compare after
a double byte write. Writes can be made to either byte of the
output compare register without affecting the other byte.
The OL VL value will be clocked out independently of
whether the OCF had previously been cleared. The output
compare registers are set to $FFFF during reset.
INPUT CAPTURE REGISTERS ($OD:OE), ($1E:1F)
The two input capture registers are 16-bit read-only
registers used to store the free-running counter when a
"proper" input transition occurs as defined by the corresponding input edge bit (IEDG1 or IEDG21. The input pin's
data direction register should be configured as an input, but
the edge detect circuit always senses P10 and P20 even
when configured as an output. The counter value will be
latched into the input capture registers on the second
negative edge of the E, clock following the transition.
An input capture can occur iI.,dependently of ICF; the
register always contains the most current value. Cou'nter
transfer is inhibited, however, between accesses of a double
byte MPU read. The input pulse width must be at leasuwo E
cycles to ensure an input capture under all conditions.

PROGRAMMABLE TIMER
The programmable timer can be used to perform
measurements on two separate input waveforms while independently generating three output waveforms. Pulse
widths can vary from several microseconds to many
seconds. A block diagram of the timer is shown in Figure 21.
COUNTER ($09:0AI, ($15, $16)
The key timer element is a 16-bit free-running counter
which is incremented by E (enable). It is cleared during reset
and is read-only with one exception: in mode 0 a write to the
counter ($09) will preset it to $FFF8: This feature, intended
for testing, can disturb serial operations because the counter
provides the SCI internal bit rate clock. The TOF bit is set
whenever the counter contains all ones. If ETOI is set, an interrupt will occur when the TOFis set. The counter may also
be read at $15 and $16 to avoid inadvertently clearing the
TOF.

TIMER CONTROL AND STATUS REGISTERS
Four registers are used to provide the MC68701U4 with
control and status information about the three output compare functions, the timer overflow function, and the two input edge functions of the timer. They are:
Timer Control and Status Register (TCSR)
Timer Control Register 1 (TCR1)
Timer Control Register 2 (TCR2)
Timer Status Register (TSR)

MOTOROLA MICROPROCESSOR DATA
3-236

FIGURE 21 -

BLOCK DIAGRAM OF PROGRAMMABLE TIMER

jAm"

MC68701U4 Internal Bus

I

~7$1C1D

l

Output Compare
Register 3

I

~OB:OC

V$lA:1B
Output Compare
Register 2

Output Compare
Register 1

I

II

v~
I

s:o

d;x,

Output Compares
(Three)

o

§;

~
....

£
o

I

/2
/

."

o(')

o

~

SOD:OE
Input Capture
Register 1

l

I

)

/2

/

(

TCRl ($17)

IICFl I OCF11 TOF I EICll IEOICilI ETOlllEDGl OLVLl

~

[
j ICF2

I

t

i

I

I

r

(

~

r

[

~

ICFl / OCF3/ OCF2/ OCFl / TOF /

I

I

1

l

/ EICI2 / EICll / EOCI3j EOCl2I EOCll

1

I

I
I

Y

~;~~~

TCR2 ($18)
ETOI

I
Pl0

I

0

~

II
Output Level I
Register 1 I

-

~D

I

1TEST ICLOCKJ

-J :

0,,,,,,_

Output Level
Register 2

~I>

I

I
I

- -J :
D

Pll

I

I

'---

0

'-~
'---

0,,,,,

Output Level
Register 3

I

I

0)

....o

Output Level
P21

I

0

3!:
(")
CO

I

r---->

~

I

TSR ($19)

~

IR02

j OE3 j OE2 JOEl jlEDG2jlEDGl OLVL3jOLVL2jOLVLlj

III I

~

I

/

Input Edge
P20

I

/

/3

/2

)-j

I

)

D

TCSR ($08)

.'\.

/

Edge Detects
ITwo)

J

I

Port Control
Circuitry

tlE:S1F
Input Capture
Register 2

I

II
/2

(

/

m

;x,

II

II

Free-Running
16-Bit Counter

/3

r-...

;x,

CJ)
CJ)

Overflow
Detect

I

$09:0A
($15:16)

>I

II

/~

3l:

w

I

0

Co. .

P12

.....

c:
~

MC68701U4

Bit 7

TIMER CONTROL AND STATUS REGISTER ITCSR)
($08) - The timer control and status register is an 8-bit
register of which all bits are readable, while only bits 0-4 can
be written. All the bits in this register are also accessible
through the two timer control registers and the timer status
register. The three most significant bits provide the timer
status and indicate if:
1. a proper level transition has been detected at P20,
2. a match has occurred between the free-running
counter and output compare register 1, or
3. the free-running counter has overflowed.
Each of the three events can generate an IR02 interrupt
and is controlled by an individual enable bit in the TCSR.

TIMER' CONTROL REGISTER 1 (TCR1) ($17) - Timer
control register 1 is an 8-bit read/write register which contains the control bits for interfacing the output compare and
input capture registers to the corresponding I/O pins.

TIMER CONTROL' REGISTER 1

7

TIMER CONTROL AND STATUS REGISTER

7

654

3

2

1

Input Capture Flag - ICFl is set to indicate that a
proper level transition has occurred; it is cleared by
reading the TCSR or the TSR (with ICFl set) and
the input capture register 1 high byte ($00), or during reset. Refer to TIMER STATUS REGISTER
(TSR) ($19).

654

3

2

1

0

IOE3 ! OE2 ! OEl IIEDG21IEDG1!OLVL3IoLVL210LVL11 $17

0

IleFl I OCFl I rOF I EICll ! EOCll ! ErOI IIEDG1!OLVL1! $00

II

Bit 0

Output Levell - OLVL 1 is clocked to output level
register 1 by a successful output compare and wiH
appear at P21 if bit 1 of the port 2 data direction
register is set and the OEl control bit in timer control register 1 is set. OLVL 1 and output level
register 1 are cleared during reset. Refer to TIMER
CONTROL REGISTER 1 (TCR1) ($17).

Bit 1

Input Edge 1 - IEDG1 is cleared during reset and
controls which level transition on P20 will trigger a
counter transfer to input capture register 1:
I EDG 1 = 0 transfer on a negative-edge
IEDGl = 1 transfer on a positive-edge
Refer to TIMER CONTROL REGISTER 1 ITCR1)
($17).

Bit 2

Enable Timer Overflow Interrupt - When set, an
I R02 interrupt will be generated when the timer
overflow flag is set; when clear, the interrupt is inhibited., ETOI is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 ITCR2) ($18).

Bit 0

Output Level 1 - OLVL 1 is clocked to output level
register 1. by a successful output compare and will
appear at P21 if bit 1 of the port 2 data direction
register is set and the OEl qontrol bit is set. OLVL 1
and output level register 1 are cleared during reset.
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($08).

Bit 1

Output Level 2 - OL VL2 is clocked to output level
register 2 by a successful output compare and will
appear at Pll if b'lt 1 of port 1 data direction register
is set and the OE2 control bit is set. OLVL2 and output level register 2 are cleared during reset.

Bit 2

Output Level 3 - OLVL3 is clocked to output level
register 3 by a successful output compare and will
appear at P12 if bit 2 of port 1 data direction register
is set and the OE3 control bit is set. OLVL3 and output level register 3 are cleared during reset.

Bit 3

Input Edge 1 - IEOG 1 is cleared during reset and
controls which level transition on P20 will trigger
counter transfer to input capture register 1.
I EOG 1 = 0 transfer on a negative-edge
IEOGl = 1 transfer on a ppsitive-edge
Refer to TIMER CONTROL AND STATUS
REGISTER (TCSR) ($08).

a

Bit 3

Enable Output Compare Interrupt 1 - When' set,
an IR02 interrupt will be generated when output
compare flag 1 is set; when clear, the interrupt is inhibited. EOCll is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 (TCR2) ($18).

Bit 4

Bit 4

Enable Input Capture Interrupt 1 - When set, an
, IR02 interrupt will be generated when input capture flag 1, is set; when clear, the interrupt is inhibited. EICll is cleared during reset. Refer to
TIMER CONTROL REGISTER 2 ITCR2) ($18).

Input Edge 2 - IEOG2 is cleared during reset and
controls which level transition on Pl0 will trigger a
counter transfer to input capture register 2.
I EOG2 = 0 transfer on a negative-edge
IEOG2 = 1 transfer on a positive-edge

Bit 5

Bit 5

Timer Overflow Flag - The TOF is set when the
counter contains all ones ($FFFFl. It is cleared by
reading the TCSR or the TSR (with TOF set) and
the counter high byte ($09), or during reset. Refer
to TIMER STATUS REGISTER (TSR) ($19).

Output Enable 1 ~ OEl is set during reset and
enables the contents of output level register 1 to be
connected to P21 when bit 1 of port 2 data direction register is set.
OE1 = 0 port 2 bit 1 data register output
OEl = 1 output level register 1

Bit 6

Output Compare Flag 1 - OCFl is set when output
compare register 1 matches the free-running
counter. OCFl is cleared by reading the TCSR or
the TSR (with OCFl set) and then writing to output
compare register 1 ($OB or SOC), or during reset.
Refer to TIMER STATUS REGISTER (TSR) ($19).

Bit 6

Output Enable 2 - OE2 is cleared during reset and
enables the contents of output level register 2 to be
connected to Pll when bit 1 of port 1 data direction register is set.
OE2 = 0 port 1 bit 1 data register output
OE2= 1 output level register 2

MOTOROLA MICROPROCESSOR DATA

3-238

MC68701U4

Bit 7

Bit 0

Output Enable 3 - OE3 is cleared during reset and
enables the contents of output level register 3 to be
connected to P12 when bit 2 of port 1 data direction register is set
OE3 = 0 port 1 bit 2 data register output
OE3= 1 output level register 3

a

TIMER CONTROL REGISTER 2 (TCR2) ($18) - Timer
control register 2 is an 8-bit read/write register (except bits 0
and 1) which enable the interrupts associated with the freerunning counter, the output compare registers, and the input
capture registers. In test mode 0, two more bits (clock and
test) are available for checking the timer.

Bit 1

TIMER CONTROL REGISTER 2
(Non-Test Modes)

7

6

5

4

3

o

2

IEICI21 EICll I EOCI31 EOCI21 EOCll I ETOI

$18

Bits 0-1 Read~Only Bits - When read, these bits return a
value of 1. Refer to TIMER CONTROL REGISTER 2
(Test Model.
Bit 2

Bit 3

TIMER STATUS REGISTER (TSR) ($19) - The timer
status register is an 8-bit read-only register which contains
the flags associated with the free-running counter, the output compare registers, and the input capture registers.

Enable Output Compare Interrupt 1 - When set.
an IR02 interrupt will be generated when the output compare flag 1 is set; when clear, the interrupt
is inhibited. EOCll is cleared during reset. Refer to
TIMER CONTROL AND STATUS REGISTER
(TCSR) ($~).
Enable Output Compare Interrupt 2 - When set,
an IR02 interrupt will be generated when the output compare flag 2 is set; when clear, the interrupt
is inhibited. EOCI2 is cleared during reset.

Bit 5

Enable Output Compare Interrupt 3 - When set,
an iR02 interrupt will be generated when the output compare flag 3 is set; when clear, the interrupt
is inhibited. EOCI3 is cleared during reset.

Bit 6

Enable Input Capture Interrupt 1 - When set, an
iRQ2 interrupt will be generated when the input
capture flag 1 is set; when clear, the interrupt is inhibited. EICll is cleared during reset. Refer to
TIMER CONTROL AND STATUS REGISTER
(TCSR) ($~1.

Bit 7

Enable Input Capture Interrupt 2 - When set, an
IR02 interrupt will be generated when the input
capture flag 2 is set; when clear,. the interrupt is inhibited. EICI2 is cleared during reset.

TIMER STATUS REGISTER

7

543

2

1

5

4

3'

2

o
$19

Bits 0-1 Not used.

TIMER CONTROL REGISTER 2
(Test Mode)

6

6

IICF2 IICFl I OCF31 OCF21 OCFl I TOF

The timer test bits (test and clock) allow the free Zero

BGT

2E 3

2

Z+(NEDV)=O

Branch If Higher

BHI

22

3

2

C+Z=O

Branch If Higher or Same

BHS

24 3

2

c=o

Branch If :SZero

BlE

2F 3

2

Z+(NEDV)=1

Branch If Carry Set'

BlO

25 3

2

C=1

Branch If lower Or Same

BlS

23 3

2

C+Z=1

Branch If 

~
Q)

';:;
«I

E

c:t

INX
JMP
JSR
LOA
LOO
LOS
LOX'
LSL
LSLO
LSR
LSRO
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STO
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

•3
3
3
3
3
3
3

•3
3
3
3
3,
3
3
3
3
6
3
3

••
••
•••
•••
••
•
••

~
Q)
~

C

!Ie

~
Q)

Ie
GI

~

c!
GI

~

.E

0

w

.=

.=

••
•2

••

•3

•3

3

6
4
5
5
5
6

6
4
5
5
5
6

3
3
3

••
•
•••
•2
••
••
•
•••
2
••

.'

•
•••
•2
•
•••
••
••
•
4

MOTOROLA MICROPROCESSOR DATA
3-248

ti
!

5
3
4
4
4

••
•••
••3
••
••
••
•••
3
••
•3
4
4
4
3
5

•
•••
•••
••

•6

••
•
•••
•
••
•
••
•
6

4

6
6

4

4
5
5
5
4
6

•
•••
•
••
•
6

•
••
•
6

6

••
•••
•2
3
2
3
10
2
2

•• •
4

••6
6
••
•4
••
•4
5
5
5
4
6

•
•••
•
•••
6

3
4
4
5
2
2
10
5
2

Q)

.~
«I

Ii
c:t

••
••
•••
•••
•••
•
•••
••

•
2
2
2

••
•••
•
12
2
2
2
2
2
3
3
9

•••
••
•••
•

MC68701U4

TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5)

Address Mode and
Instructions

R/W
Address Bus

Data Bus

Line

IMMEDIATE
2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Operand Data

LDS
LDX
LDD

3

1
2

Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

CPX
SUBD
ADDD

4

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address Bus FFFF

1
1
1
1

Upcode
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode 'Address + 1 .
Address of Operand

1
1
1

Opcode
Address of Operand
Operand Data

ADC
ADD
AND
BIT
CMP

DIRECT
ADC
ADD
AND
BIT
CMP

EOR
LDA
ORA
SBC
SUB

3
1
2

3
4
EOR
lOA
ORA
SBe
SUB

3

1
2

3

STA

3

LDS
LDX
LDD

4

STS
STX
STD

4

CPX
SUBD
ADDD

5

JSR

5

1
2

3
1
2

3
4
1
2

3
4
1
2

3
4
5
1
.2

3
4
5

1
1

Opcode Address
Opcode Address + 1
Destination Address

0

Opcode
Destination Address
Data from Accumulator

Opcode Address
Opcbde Address + 1
Address of Operand
Operand Address + 1

1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Address of Operand
Address of Operand + 1

1
1

0
0

Opcode
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)

Opcode Address
Opcode Address +. 1
Operand Address
Operand Address + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Subroutine Address
Stack Pointer
Stack Pointer-1

1
1
1

Opcode
Irrelevant Data
First Subroutine Opcode
Return Address (Low Order Byte)
Return Address (High Order Byte)

0
0

MOTOROLA MICROPROCESSOR DATA
3-249

I

MC68701U4

TABLE 14 - CYCLE"BY-CYCLE OPERATION (Sheet 2 of 5)
Address Mode and
Instructions
EXTENDED
JMP

3

1
2

3
EOR
LDA
ORA
SBC
SUB

ADC
ADD
AND
BIT
CMP

4

1
2

3
4
4

STA

1
2

3
4

I

LDS
LDX
LDD

5

STS
STX
STD

5

1
2

3
4
5
1
2

3
4
5
LSR
NEG
ROL
ROR
TST*

ASL
ASR
CLR
COM
DEC
INC

6

1
2

3
4
5
6

CPX
SUBD
ADDD

6

JSR

6

1
2

3
4
5
6
1
2

3
4
5
6

* TST

R/W
Line

Address Bus

Data Bus

Opcode Address
Opcode Address + 1
Opcode Address + 2

1
1
1

Opcode
Jump Address (High Order Byte)
Jump Address (Low Order Byte)

Opcode Address
Opcode Address+ 1
Opcode Address+ 2
Address of Operand

1
1
1
1

Opcode
Address of Operand
Address of Operand (Low Order Byte)
Operand Data

Opcode Address
Opcode Address + 1
OpcodeAddress + 2
Operand Destination Address

1
1
1

Opcode
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address of Operand
Address of Operand + 1

0
1
1
1
1
1
1
1
1

Opcode Address
Opcode Address + 1
Opcode Address + 2
Address qf Operand
Address of Operand + 1

0
0
1
1
1
1
1
0
1
1
1
1
1
1

Opcode Address
Opcode Address + 1
Opcode Address+ 2
Address of Operand
Address Bus FFFF
Address of Operand
Opcode Address
Opcode Address +,1
Opcode Address + 2
Operand Address
Operand Address + 1
Address Bus FFFF
Opcode Address
Opcode Address + 1
Opcode Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer- 1

1
1
1
1

0
0

Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
O~erand Data (High Order Byte)
Operand Data (Low Order Byte)
Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data (High Order Byte)
Operand D'lta (Low Order Byte)
Opcode
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Opcode
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte.of Restart Vector
Opcode
Address of Subroutine (High Order Byte)
Address of Subroutine '(Low Order Byte)
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

does not perform the write cycle during the sixth cycle, The sixth cycle is another address bus= $FFFF,

MOTOROLA MICROPROCESSOR DATA
3-250

MC68701U4

TABLE 14 Address Mode and
Instructions

CYCLE-BY-CYCLE OPERATION (Sheet 3 of 5)

R/W
Line

Address Bus

Data Bus

INDEXED

JMP

3

1

2
3
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

STA

4

1

2
3
4
4

1

2
3
4
LOS
LOX
LDD

5

STS
STX
STD

5

ASL
ASR
CLR
COM
DEC
INC
CPX
SUBD
ADDD

JSR

1

2
3
4
5
1

2
3
4
5
LSR
NEG
ROL
ROR
TST*

6

1

2
3
4
5
6
6

1

2
3
4
5
6
6

1

2
3
4
5
6

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Offset
Low Byte of Restart Vector

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset

1
1
1

0

Opcode
Offset
Low Byte of Restart Vector
Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1

1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)

0
0
1
1
1
1
1

Opcode Address
Opcode' Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset

0

Opcode
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data

Opcode Address
Opcode Address + 1
Address Bus FFFF
Index Register+ Offset
Index Register+ Offset + 1
Address Bus FFFF

1
1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector

Opcode Address
Opcode Address+l
Address Bus FFFF
Index Register+ Offset
Stack Pointer
Stack Pointer-l

1
1
1
1

Opcode
Offset
Low Byte of Restart Vector
First Subroutine Opcode
Return Address (Low Order Bytei
Return Address (High Order Byte)

0
0

*TST does not perform the write cycle during the sixth cycle, The sixth cycle is another address bus= $FFFF,

MOTOROLA MICROPROCESSOR DATA
3-251

I

MC68701U4

TABLE 14 -

Address Mode and
Instructions
INHERENT
ABA
DAA
ASL
DEC
ASR
INC
CBA
LSR
CLC
NEG
CLI
NOP
CLR
ROL
CLV
ROR
COM
SBA
ABX

I

CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5)
R/W
Line

AdHress Bus

Data Bus

2

1
2

Opcode Address
Opcode Address + 1

1
1

Opcode
Opcode of Next Instruction

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

ASLD
LSRD

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Irrelevant Data
Low Byte of Restart Vector

DES
INS

3

1
2
3

Opcode Address
Opcode Address + 1
Previous Stack Pointer Contents

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

INX
DEX

3

1
2
3

Opcode A.ddress
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PSHA
PSHB

3

1
2
3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1
0

Opcode
Opcode of Next Instruction
Accumulator Data

TSX

3

1
2

3

Opcode Address
Opcode Address + 1
Stack Pointer

1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data

TXS

3

1
2
3

Opcode Address
Opcode Address + 1
Address Bus FFFF

1
1
1

Opcode
Opcode of Next Instruction
Low Byte of Restart Vector

PULA
PULB

4

1
2
3
4

Opcode Address
Opcode Address+ 1
Stack Pointer
Stack Pointer+ 1

1
1
1
1

Opcode
Opcode of Next Instruction
Irrelevant Data
Operand Data from Stack

PSHX

4

1
2
4

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-l

1
1
0
0

Opcode
Irrelevant Data
Index Register (Low Order Byte)
Index Register (l-iigh Order Byte)

1
2
3
4
5
1
2
3
4
5

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+ 2
Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+2

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Index Register (High Order Byte)
Index Register (Low Order Byte)
Opcode
Irrelevant Data
Irrelevant Data
Address of Next Instruction (High Order Byte)
Address of Next Instruction (Low Order Byte)

1
2
3
4
5
6
7

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-l
Stack Pointer- 2
Stack Pointer - 3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer - 6

1
1
0
0
0
0
0
0
0

Opcode
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of C.ondition Code Register

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

3
PULX

5

RTS

5

WAI

9

8
9

MOTOROLA MICROPROCESSOR DATA.
3-252

MC68701U4

TABLE 14 - CYCLE-BY-CYCLE OPERATION (Sheet 5 of 5)
Address Mode and
Instructions
INHERENT (Continued)
MUL

R/W
10

1
2
3
4
5
6
7

Opcode Address
Opcode Address + 1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart
Low Byte of Restart

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer+ 1
Stack Pointer+2
Stack Pointer+3
Stack Pointer + 4
Stack Pointer + 5
Stack Pointer+6
Stack Pointer+ 7

1
1
1
1
1
1
1
1
1
1

Opcode
Irrelevant Data
Irrelevant Data
Contents of Condition Code Register from Stack
Contents of Accumulator B from Stack
Contents of Accumulator A from Stack
Index Register from Stack (High Order Byte)
Index Register from Stack (Low Order Byte)
Next Instruction Address from Stack (High Order Byte)
Next Instruction Address from Stack (Low Order Byte)

10
11
12

Opcode Address
Opcode Address + 1
Stack Pointer
Stack Pointer-1
Stack Pointer-2
Stack Pointer-3
Stack Pointer-4
Stack Pointer - 5
Stack Pointer-6
Stack Pointer- 7
Vector Address FFFA (Hex)
Vector Address FFFB (Hex)

1
1
0
0
0
0
0
0
0
1
1
1

Opcode
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condition Code Register
Irrelevant Data
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)

3

1
2
3

Opcode Address
Opcode Address + 1
Address Buss FFFF

1
1
1

Opcode
Branch Offset
Low Byte of Restart Vector

6

1
2
3
4

Opcode Address
Opcode Address + 1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer-1

1
1
1
1
0
0

Opcode
Branch Offset
Low Byte of Restart Vector
Opcode of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)

8
9
10
RTI

10

1
2
3
4
5
6
7

8
9
10
12

SWI

1
2
3
4
5
6
7

8
9

RELATIVE
BCC BHT
BCS BLE
BEQ BLS
BGE BLT
BGT BMI
BSR

BNE BLO
BPL BHS
BRA BRN
BVC
BVS

Data Bus

Line

Address Bus

5
6

MOTOROLA MICROPROCESSOR DATA
3-253

Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector

II

FIGURE 24 - SPECIAL OPERATIONS

•
SP

SWI, Software Interrupt

JSR, Jump to Subroutine

Eb

IC>-'

Main Program
$9D=JSR

Direct

{

RTN

s::

a
~
~

s::

w

~

n
~

."

g

EXTND

{

AcmltrB

Next Main Instr.

SP-4

AcmltrA

!

o

~

RTN

~

s_

¢~::=:rn
SP

RTNL

Index Register (XL)

$3E=WAI

SP-l

RTNH

SP

RTNL

~

Stack

.

J

SP
SP+l

SH = Subr. Addr.

SP+2

AcmltrB

SL= Subr. Addr.

SP+3

AcmltrA

Next Main Inst.

SP+4

Index Register (X H)

SP+5

Index Register (XL!

Condition Code

RTNH

SP+6
$80= BSR
±K=Offset

RTN

Index Register (XH)

SP-2

$BD=JSR

§P

Main Program

~

SP-3
Main Program

RTI Return from Interrupt
'
~

BSR, Branch To Subroutine

::0

~

Next Main Instr.

I

WAI, Wait for Interrupt

Main Program

m

en
en

$AD=JSR
K=Offset

RTN

Condition Code

SP-5

Main Program

INDXD

SP-6

K

K = Direct Address

Eb

Stack

SP-7

¢~

Next Main Instr.

SP-2

Subroutine

~

$39=RTS

¢ ....

rn

SP.,-.l . .

RTNH

SP

RTNL

.~
RTS, Return from Subroutine

Stack

~

~tack .

SP~

SP+ 1

RTNH

SP+2

RTNL

Legend:
RTN = Address of next instruction in Main Program to be executed upon return from subroutine
RTNH = Most significant byte of Return Address
RTNL = Least significant byte of Return Address
-- = Stack Pointer After Execution
K = 8-bit Unsigned Value

....

SP+7

ef

JMP, Jump

INDXD

!

~

X+K

Next Instruction

E"~

-

m

-

~-~
. Main Program
$7E=JMP
KH = Next Address

{

KL = Next AddreSs

K fNext

3:

n

Instructio~

........c:o
.,.

MC68701U4

ORDERING INFORMATION

GENERIC INFORMATION
(TA=Qo to'7QoC)
Package Type

Cerdip -

S Suffix

Frequency

Generic Number

1.0 MHz
1.25 MHz

MC68701U4S
MC68701l:J4S-1

, PIN ASSIGNMENTS

VSS
XTAL

2

SC1

EXTAL

3

SC2

NMi

4

P30

iRCl1

5

P31

RESETIVpp

ti

P32

VCC

7

P33

P20

8

P34

P21

9

P35

P22
P23

P36
P37

11

P40

P24
Pl0

P41

Pll

P42

P12

P43

P13

P44

P14

P45

P15

P46

P16

P47

P17

VCC
Standby

MOTOROLA MICROPROCESSOR DATA
3-255

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC6802

Microprocessor With Clock
and Optional RAM

I

The MC6802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators
of the present MC6800 plus an internal clock oscillator and driver on the same chip. In addition, the
MC6802 has 128 bytes of on-board RAM located at hex addresses $0000 to $007F. The first 32 bytes
of RAM, at hex addresses $0000 to $001 F, may be retained in a low power mode by utilizing VCC
standby; thus, facilitating memory retention during a power-down situation.
The MC6802 is completely software compatible with the MC6800 as well as the entire M6800
family of parts. Hence, the MC6802 is expandable to 64K words.
• On-Chip Clock Circuit
• 128x8 Bit On-Chip RAM
• 32 Bytes of RAM are Retainable
• Software-Compatible with the MC6800
• Expandable to 64K Words
• Standard TIL-Compatible Inputs and Outputs
• 8-Bit Word Size
• 16-Bit Memory Addressing
• Interrupt Capability

TYPICAL MICROCOMPUTER
Vcc

Vcc

~--+----IIII--~

MC6846

'-----<~

Vcc

Vcc

iRQ
MR

This block diagram shows a typical cost effective microcomputer. The MPU is the
center of the microcomputer system and is
shown in a minimum system interfacing with
a ROM combination chip. It is not intended
that this system be limited to this function
but that it be expandable with other parts in
the M6800 Microcomputer family.

CSO .......:..V'-"M"-A'---_ _ _~ VMA
2 k Bytes ROM
10 I/O Lines

Clock

E

RiilJ
!4-!..!.!..,;!..!...-------lRiilJ MC6802

Parallel
I/O

RE
NMI

MPU

DO-D7
EXTAL

o
AO-A15

AO-A15

XTAL

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-256

MC6802

MAXIMUM RATINGS·
Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to +7.0

V

-0.3 to +7.0

Rating
Input Voltage

Vin

Operating Temperature Range
MC6802, MC680A02, MC680B02
MC6802C, MC680A02C

TA

Storage Temperature Range

Tsta

o to + 70
-40 to +85
-55 to +150

V

°c
°c

This input contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate logic
voltage level (e.g., either VSS or VCC).

THERMAL CHARACTERISTICS
Characteristic

Symbol

Average Thermal Resistance (Junction to Ambient)
Plastic

6JA

POWER CONSIDERATIONS
The average chip-junction temperature, TJ' in °c can be obtained from:
(1 )
TJ=TA + (PooSJA)
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance, Junction-to-Ambient, °C/W
SJA
= PINT+PpORT
.
Po
= ICC x VCC' Watts - Chip Internal Power
PINT
PPORT = Port Power Dissipation, Watts -' User Determined
For most applications PpORT-

g

200

L..-- ~

__ V

300

-

l....- I-"'"

I--- ~

~ I--

RIW

100

I

CL includes stray capacitance
0

0

100

200

300

400

500

CL includes stray capacitance

200

100

600

CL. LOAD CAPACITANCE (pF)

FIGURE 6 -

EXPANDED BLOCK DIAGRAM
A9

A8

A7

A6

Memory Ready \
Enable

RffiT

{NMil
HAi:T

Interrupt Request (IRQ)
EXTAL
XTAL
Bus Available
Valid Memory Address
Read/Write (R/WI

Vcc= Pin 8
Vss=Pins 1,21

07

06

500

400

Cl, LOAD CAPACITANCE (pF)

Al5 Al4 Al3 Al2 All AID

Non-Maskable Interrupt

300

05

04

03

02

01

00

MOTOROLA MICROPROCESSOR DATA
3-260

A5

A4

A3

A2

Al

AD

600

MC6802

MPU REGISTERS
INDEX REGISTER
The index register is a two byte register that is used
to store data or a 16-bit memory address for the indexed
mode of memory addressing.

A general block diagram of the MC6802 is shown in
Figure 1. As shown, the number and configuration of
the registers are the same as for the MC6800. The 128 x 8bit RAM* has been added to the basic MPU. The first
32 bytes can be retained during powerup and powerdown conditions via the RE signal.
The MPU has three 16-bit registers and three 8-bit
registers available for use by the programmer (Figure 7).

ACCUMULATORS
The MPU contains two 8-bit accumulators that are
used to hold operands and results from an arithmetic
logic unit (ALU).

PROGRAM COUNTER
The program conter is a two byte (16-bit) register that
points to the current program address.

CONDITION CODE REGISTER
The condition code register indicates the results of an
Arithmetic Logic Unit operation: Negative (N), Zero (Z),
Overflow (V), Carry from bit 7 (C), and Half Carry from
bit 3 (H). These bits of the Condition Code Register are
used as testable conditions for the conditional branch
instructions. Bit 4 is the interrupt mask bit (I). The unused bits of the Condition Code Register (b6 and b7)
are ones.
Figure 8 shows the order of saving the microprocessor status within the stack.

STACK POINTER
The stack pointer is a two byte register that contains
the address of the next available location in an external
pushdown/pop-up stack. This stack is normally a random access read/write memory that may have any location (address) that is convenient. In those applications
that require storage of information in the stack when
power is lost, the stack must be non-volatile.

*If programs are not executed from on-board RAM, TAV1applies. If programs are to be stored and executed from on-board RAM,
TAV2 applies. For normal data storage in the on-board RAM, this extended delay does not apply. Programs cannot be executed
from on-board RAM when using A and B parts (MC68A02 and MC68B02). On-board RAM can be used for data storage with all
parts.

FIGURE 7 -

PROGRAMMING MODEL OF THE MICROPROCESSING UNIT
7

0

I. . __

A_C_C_A_ _.......JI Accumulator A

7

0

I - I_ _

-ll

A_C_C_B_ _

15

Accumulator B

0
1X_ _ _ _ _-.......Jllndex Register

, : , : 1: : - -_ _ _ _ _

15

0
----,-_P_C_ _ _ _ _-.......JI Program Counter

, : : 1: - -_ _ _

15

0

1
...______
SP
_ _ _ _ _-.......J Stack
1

Pointer

Condit'ion Codes

L....J..~4~.,.J-,...L.rJ Register
Carry (From Bit 7)

IL
L

Overflow
zero
Negative
In~erruPt

" - - - - - Half Carry (From Bit 3)

MOTOROLA MICROPROCESSOR DATA
3-261

II

MC6802

FIGURE 8 - SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK

~
m - 9
m - 8
SP
CC
ACCB
ACCA
IX H
IXL
PCH
PC L

= Stack Pointer

m - 7

= Condition Codes (Also called the Processor Status Byte)

m-6

= Accumulator B
= Accumulator A
= I ndex Register, Higher Order 8 Bits
= Index Register, Lower Order 8 Bits
= Program Counter, Higher Order 8 Bits
= Program Counter, Lower ,order 8 Bits

SP
CC

m - 5

ACCB

m - 4

ACCA

m,- 3

IXH

2

m - 2

IXL

m -1

m - 1

PCH

m+1

m + 1

m -

,
.>t.
U

en

PCL

m +2

m +2

I

~I
Before

After

MPU SIGNAL DESCRIPTION
tion, bus available will be at a high state, valid memory address will be at a low state. The address bus will display the
address of the next instruction.
To ensure single instruction operation, transition of
the HALT line must occur tpcs before the rising edge
of E and the HALT line must go high for one clock cycle.
HALT should be tied high if not used. This is good
engineering design practice in general and necessary to ensure proper operation of the part.

Proper operation of the MPU requires that certain control
and timing signals be provided to accomplish specific functions and that other signal lines be monitored to determine
the state of the processor. These control and timing signals
are similar to those of the MC6800 except that TSC, DBE,
1/>1, 1/>2 input, and two unused pins have been eliminated,
and the following signal and timing lines have been added:
RAM Enable (RE)
Crystal Connections EXT AL and XT AL
Memory Ready (MR)
VCC Standby
Enable 1/>2 Output (E)
The following is a summary of the MPU signals:

READ/WRITE (RiW)
This TTL-compatible output Signals the peripherals and
memory devices whether the MPU is in a read (high) or write
(low) state. The normal standby state of this signal is read
(high), When the processor is halted, it will be in the read
state. This output is capable of driving one standard TTL
load and 90 pF.

ADDRESS, BUS (AO-A15)
Sixteen pins are used for the address bus. The outputs are
capable of driving one standard TTL load and 90 pF. These
lines do not have three-state capability.

. VALID MEMORY ADDRESS (VMA)
This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation, this
Signal should be utilized for enabling peripheral interfaces
such as the PIA and ACIA.This signal is not three-state. One
standard TTL load and 90 pF may be directly driven by this
active high signal.

DATA BUS (00-07)
Eight pins are used for the data bus, It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has three-state output buffers capable ·of
driving one standard TTL load and 130 pF.
Data bus will be in the output mode when the internal
RAM is accessed and RE will be high. This prohibits external
data entering the MPU. It should be noted that the internal
RAM is fully decoded from $0000 to $OO7F. External RAM at
$0000 to $OO7F must be disabled when internal RAM is accessed.

BUS AVAILABLE (BA) - The bus available Signal will normally be in the low state; when activated, it will go to the
high state indicating that the microprocessor has stopped
and that the address bus is available (but not in a three-state
condition). This will occur if the HALT line is in the low state
or the processor is in the WAIT state as a result of the execution of a WAIT instruction. At such time, all three-state output drivers will go to their off-state and other outputs to their
normally inactive level. The processor is removed from the

HALT
When this input is in the low state, all activity in the
machine will be halted. This input is level sensitive. In the
HALT mode, the machine will stop at the end of an instruc-

MOTOROLA MICROPROCESSOR DATA .
3~262

MC6802

WAIT state. by the occurrence of a maskable (mask bit 1=0)
or nonmaskable interrupt. This output is capable of driving
one standard TTL load and 30 pF.

INTERRUPT REQUEST (IRQ)
A low level on this input requests that an interrupt sequence be generated within the machine. The processor will
wait until it completes the current instruction that is being
excuted before it recognizes the request. At that time, if the
interrupt mask bit in the condition code register is not set,
the machine will begin an interrupt sequence. The index
register, program counter, accumulators, and condition
code register are stored away on the stack. Next the MPU
will respond to the interrupt request by setting the interrupt
mask bit high so that no further interrupts may occur. At the
end of the cycle, a 16-bit vectoring address which is located
in memory locations $FFF8 and $FFF9 is loaded which
causes the MPU to branch to an interrupt routine in memory.
The HALT line must be in the high state for interrupts to
be serviced. Interrupts will be latched internally while HALT
is low.
A nominal 3 kO pullup resistor to Vee should be used for
wire-OR and optimum control of interrupts. IRQ may be tied
directly to Vee if not used.
RESET
This input is used to reset and start the MPU from a
power-down condition, resulting from a power failure or an
initial start-up of the processor. When this line is low, the
MPU is inactive and the information in the registers will be
lost. If a high level is detected on the input, this will signal
the MPU to begin the restart sequence. This will start execuFIGURE 9 -

tion of a routine to initialize the processor from its reset condition. All the highe( order address lines will be forced high.
For the restart, the last two ($FFFE, $FFFF) locations in
memory will be used to load the program that is addressed
by the program counter. During the restart routine, the interrupt mask bit is set and must be reset before the M PU can be
interrupted by IRQ .. Power-up and reset timing and powerdown sequences are shown in Figures 9 and 10, respectively.
RESET, when brought.low, must be held low at least three
clock cycles. This allows adequate time to respond internally
to the reset. This is independent of the trc power-up reset
that is required.
.
When RESET is released it must go through the low-tohigh threshold without bouncing, oscil!ating, or otherwise
causing an erroneous reset (less than three clock cycles).
This may cause improper MPU operation until the next valid
reset.
NON-MASKABLE INTERRUPT (NMI)
A low-going edge on this input requests that a nonmaskable interrupt sequence be generated within the processor. As with the interrupt request signal, the processor
will complete the current instruction that is being executed
before it recognizes the NMI signal. The interrupt mask bit in
the condition code register has no effect on NMI.
The index register, program counter, accumulators, and
condition code registers are stored away on the stack. At the
end of the cycle, a 16-bit vectoring address which is located
in memory locations $FFFe and $FFFD is loaded causing the
MPU to branch to an interrupt service routine in memory.
A nominal 3 kO pullup resistor to Vee should be used for
wire-OR and optimum control of interrupts. NMI may be tied

POWER-UP AND RESET TIMING

Vcc

!.-t

d

trc

pcs

~-----------~!------VIH

VIL

trc
RESET

Option 1
ISee Note Below}

~----

-----Ii

Option 2
ISee Figure 10 for
Power-down Condition}

h~:-PCf---

RE

NOTE: If option 1 is chosen, RESET and RE pins can be tied together.

MOTOROLA MICROPROCESSOR DATA
3-263

II

MC6802

directly to Vee if not used.
.
Inputs IRQ and NMI are hardware interrupt lines that are
sampled when E is high and will start the interrupt routine on
a low E following the completion of an instruction.
Figure 11 is a flowchart describing the major decision
paths and interrupt vectors of the microprocessor. Table 1
gives the memory map for interrupt vectors.

FIGURE 10 -

Vee

TABLE 1 - MEMORY MAP FOR
INTERRUPT VECTORS
Vector

Description

MS

LS

$FFFE

$FFFF

Restart

$FFFC

$FFFD

Non-Maskable Interrupt

$FFFA

$FFFB

Software Interrupt

$FFF8

$FFF9

Interrupt Request

RE

FIGURE 11 -

MPU FLOWCHART

II

MOTOROLA MICROPROCESSOR DATA
3-264

POWER-DOWN SEQUENCE

MC6802

FIGURE 12 - CRYSTAL SPECIFICATIONS
Y1
3.58 MHz
4 MHz
6 MHz
8 MHz

Cin
27 pF

Cout
27 pF

27 pF
20 pF
18 pF

27 pF
20 pF
18 pF

Crystal Loading

----1101---1- Y1

Nominal Crystal Parameters·

RS
CO
C1
Q

3.58 MHz

4.0 MHz

6.0 MHz

8.0 MHz

600
3.5 pF

500
6.5 pF

30-500
4-6 pF

20-40 0
4-6 pF

0.015 pF

0.025 pF

0.01-0.02 pF

0.01-0.02 pF

>40K

>30K

>20K

>20K

"These are representative AT-cut parallel resonance crystal parameters only.
Crystals of other types of cuts may also be used.

Figure 13 - SUGGESTED PC BOARD LAYOUT
Example of Board DeSign Using the Crystal Oscillator

~Other Signals are Not Wired in this Area

/ E Signal is Wired Apart from 38 Pin
/'
and 39 Pin

(Joi----E

MOTOROLA MICROPROCESSOR DATA

3-265

II

MC6802

FIGURE 14 -

MEMORY READY SYNCHRONIZATION

4xfo
Oscillator

EXTAL~3~9----------------------------~
XTAL 38

MC6802
MR~-------------------i

SN74LS74

I

FIGURE 15 -

MR NEGATIVE SETUP TIME REQUIREMENT
E Clock Stretch

qt

pcs

---J!

\,--O.'_V

The E clock will be stretched at end of E high of the cycle during which MR negative meets the tpcs setup time. The tpcs setup time is
referenced to the fall of E. If the tpcs setup time is not met, E will be stretched at the end of the next E-high Yo cycle. E will be stretched in integral multiples of Yo cycles.

Resuming E Clocking

~tPcs
I

Stretched E

MR

~tPcs ~tPCS ~tPcs

~'-.

I
I

I

.J/

___

111///

The E clock will resume normal operation at the end of the Yo cycle during which MR assertion meets the tpcs setup time. The tpcs setup time
is referenced to transitions of E were it not stretched. If tpes setup time is not met, E will fall at the second possible transition time after MR is
asserted. There is no direct means of determining when the tpcs references occur, unless the synchronizing circuit of Figure 14 is used.

MOTOROLA MICROPROCESSOR DATA
3-266

MC6802

RAM ENABLE (RE)

MPU INSTRUCTION SET

A TTL-compatible RAM enable input controls the on-·
chip RAM ofthe MC6802. When placed in the high state,
the on-chip memory is enabled to respond to the MPU
controls. In the low state, RAM is disabled. This pin may
also be utilized to disable reading and writing the onchip RAM during a powerdown situation. RAM Enable
must be low three cycles before VCC goes below 4.75
V during powerdown. RE should be tied to the correct
high or low state if not used.

The instruction set has 72 different instructions. Included
are binary and decimal arithmetic, logical; shift, rotate, load,
store, conditional or unconditional branch; interrupt and
stack manipulation instructions !Tables 2 through 6). The instruction set is the same as that for the MC6800.

MPU ADDRESSING MODES

EXTAL AND XTAL
These inputs are used for the internal oscillator that may
be crystal contro"ed. These connections are for a para"el
resonant fundamental crystal (see Figure 12), (AT-cut.! A
divide-by-four circuit has been addect so a 4 MHz crystal may
be used in lieu of a 1 MHz crystal for a more cost-effective
system. An example of the crystal circuit layout is shown in
Figure 13. Pin 39 may be driven externally by a TTL input
signal four times the required E clock frequency. Pin 38 is to
be grounded.
An RC network is not directly usable as a frequency
source on pins 38 and 39. An RC network type TTL or CMOS
oscillator wi" work we" as long as the TTL or CMOS output
drives the on-chip oscillator.
LC networks are not recommended to be used in place of
the crystal.

There are seven address modes that can be used by a programmer, with the addressing mode a function of both the
type of instruction and the coding within the instruction. A
summary of the addreSSing modes for a particular instruction
can be found in Table 7 along with the associated instruction
execution time that is given in machine cycles. With a bus
frequency of 1 MHz, these times would be microseconds ..
ACCUMULATOR (ACCX) ADDRESSING
In accumulator only addressing, either accumulator A or
accumulator B is specified. These are one-byte instructions;
IMMEDIATE ADDRESSING
In immediate addreSSing, the operand is contained in the
second byte of the instruction except LDS and LDX which
have the operand in the second and third bytes of the instruction: The MPU addresses this location when it fetches
the immediate instruction for execution. These are two-or
three-byte instructions.

If an external clock is used, it may not be halted for
more than tPW~L. The MC6802 is a dynamic part except
for the internal RAMi and requires the external clock to
retain information.
MEMORY READY (MR)
MR is a· TTL-compatible input signal controlling the stretching of E. Use of MR requires synchronization with the 4xfo
signal, as shown in Figure 14. When MR is high; E wi" be in
normal operation. When MR is low, E wi" be stretched integral numbers of half periods, thus allowing interface to
slow memories. Memory Ready timing is shown in Figure 15.
MR should be tied high (connected directly to VCC) if not
used. This is necessary to ensure proper operation of the
part. A maximum stretch is tcyc.

DIRECT ADDRESSING
In direct addressing, the address of the operand is contained in the second byte of the instruction. Direct addressing
a"QWs the user to directly address the lowest 256 bytes in the
machine, i.e., locations zero through 255. Enhanced execution times are achieved by storing data in these locations. In
most configurations, it should be a random-access memory.
These are two-byte instructions.
EXTENDED ADDRESSING
In extended addressing, the address contained in the second byte of the instruction is used as the higher eight bits of
the address of the operand. The third byte of the instruction
is used as the lower eight bits of the address for the operand.
This is an absolute address in memory. These are three-byte
instructions.

ENABLE (E)
This pin supplies the clock for the MPU and the rest of the
system. This is a single-phase, TTL-compatible clock. This
clock may be conditioned by a memory read signal. This is
equivalent to 412 on the MC6800. This output is capable of
driving one standard TTL load and 130 pF.

INDEXED ADDRESSING
In indexed addressing, the address contained in the second byte of the instruction is added to the index register's
lowest eight bits in the MPU. The carry is then added to the
higher order eight bits of the index register. This result is
then used to address memory. The modified address is held
in a temporary address register so there is no change to the
index register. These are two-byte instructions.

Vee STANDBY
This pin supplies the dc voltage to the first 32 bytes
of RAM as well as the RAM Enable (RE) control logic.
Thus, retention of data in this portion of the RAM on a
power-up, power-down, or standby condition is guaranteed. Maximum current drain at VSB maximum is
ISBB·

MOTOROLA MICROPROCESSOR DATA
3-267

II

MC6802

byte of the instruction is added to the program counter's.
lowest eight bits plus two. The carry or borrow is then added
to the high eight bits. This allows the user to address data
within a range of - 125 to + 129 bytes of the present instruction. These are two-byte instructions.

IMPLIED ADDRESSING

In the implied addressing mode, the instruction gives the
address (i.e., stack pointer, index register, etc.!' These are
one-byte instructions.
RELATIVE ADDRESSING

In relative addressing, the address contained in the second

TABLE 2 - MICROPROCESSOR INSTRUCTION SET - ALPHABETIC SEQUENCE

II

ABA
ADC
ADD
AND
ASL
ASR

Add Accumulators
Add with Carry
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right

BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMf
BNE
BPL
BRA
BSR
BVC
BVS

Branch if Carry Clear
Branch if Carry Set
Branch if Equal to Zero
Branch if Greater or Equal Zero
Branch if Greater than Zero
Branch if Higher
Bit Test
Branch if Less or Equal
Branch if Lower or Same
Branch if Less than Zero
Branch if Minus
Branch if Not Equal to Zero
Branch if Plus
Branch Always
Branch to Subroutine
Branch if Overflow Clear
Branch if Overflow Set

CBA
CLC
ClI

Compare Accumulators
Clear Carry
Clear Interrupt Mask

CLR
CLV
CMP
COM
CPX

Clear
Clear Overflow
Compare
Complement
Compare Index Register

DAA
DEC
DES
DEX

Decimal Adjust
Decrement
Decrement Stack Pointer
Decrement Index Register

EOR

Exclusive OR

INC
INS
INX

Increment
Increment Stack Pointer
Increment Index Register

JMP
JSR

Jump
Jump to Subroutine

LOA
LOS
LOX
LSR

Load Accumulator
Load Stack Pointer
Load Index Register
Logical Shift Right

NEG
NOP

Negate
No Operation

ORA

Inclusive OR Accumulator

PSH

Push Data

PUL

Pull Data

ROL
ROR
RTI
RTS

Rotate Left
Rotate Right
Return from Interrupt
. Return'from Subroutine

SBA
SBC
SEC
SEI
SEV
STA
STS
STX
SUB
SWI

Subtract Accumulators
. Subtract with Carry
Set Carry
Set Interrupt Mask
Set Overflow
Store Accumulator
Store Stack Register
Store Index Register
Subtract
Software Interrupt

TAB
TAP
TBA
TPA
TST
TSX
TXS

Transfer Accumulators
Transfer Accumulators to Condition Code Reg.
Transfer Accumulators
Transfer Condition Code Reg. to Accumulator
Test
Transfer Stack Pointer to Index Register
Transfer Index Register to Stack Pointer

WAI

Wait for Interrupt

MOTOROLA .MICROPROCESSOR DATA
3-268

MC6802

TABLE 3 -

ACCUMULATOR AND MEMORY INSTRUCTIONS
BOOLEAN/ARITHMETIC OPERATION COND_ CODE REG_

AODRESSING MOOES
IMMEO
OPERATIONS
Add

Add Acmltrs
Add with Carry
And

Clear

Compare

Compare Acmltrs
Complement,l's

Complement.2's

I Negatel

Decrement

Increment

lOfld Acmltr
Or,lntluslve

Push Data
Pull Data
Rotate Left

Rotate Right

Shift left, ArithmetIC

Shift Right. Arithmetic

Shift Rlght,'loglC

Store Acmltr

Subtract
Subtract Acmltrs.

Subtr.wlthCarry

Transfer Acmltrs
Test. Zero or Minus

OIRECT

MNEMONIC

OP

-

OP

ADDA
ADDB
ABA
ADCA
ADCB
ANDA
ANDB
BITA
BITB
CLR
CLRA
CLRB
CMPA
CMPB
CBA
COM
COMA
COMB
NEG
NEGA
NEGB
DAA

3B
C8

2

9B

2

08

DEC
DECA
DECB
EORA
EORB
INC
INCA
INCB
LDAA
LDAB
DRAA
ORAB
PSHA
PSHB
PULA
PULB
ROL
ROLA
ROLB
ROR
RORA
RDRB
ASL
ASLA
ASLB
ASR
ASRA
ASRB
LSR
LSRA
LSRB
STAA
STAB
SUBA
SUBB
SBA
SBCA
SBCB
TAB
T8A
TST
TSTA
TST8

INOEX

-

EXTND

OP

-

OP

-

AB
E8

5
5

BB
FB

4
4

IMPLlEO
3
3

81
Cl

2
2

2

2

2
2

2
2
2
2
2
2

2
2

99
09
94
04
95
05

91
01

3
3
3
3
3
3

2

A9

2
2

E9
A4

2
2

E4
A5

2

2
2

3
3

5

E5

5

6F

7

Al
El.

5
5

2
2
2
2
2

2
2

B9

4

3

F9
84
F4
85
F5
7F

4
4
4
4

3
3
3
3

Bl

Fl

4
4

7

2

73

6

3

60

7

2

70

6

3

88
C8

2
2

2
2

98
08

3
3

2
2

A8
E8
6C

7

7

B + M -8
A + 8 --A
A + M + C ·A
8 + M + C -8
A- M -A
8' M -8

1

2

7A

6

3

2

4

3

2
2

B8
F8
7C

4
6

3
3

8-M
00 --M
00 --A
00 -B

2

1

5F

2

1

11

2

1

43

2

1

53

2

1

A-A
B -8

2
2

1
1

00 - M ·M
00 - A -A
00 - 8 -B

2

1

Converts Binary Add, of BCD Characters
Inlo BCD Format
M -1 -M

A 1 -A
B-1 -B
A(!)M -A
B(!)M-B
Mq-'M
A ... 1 -,tJ..'
Bq -B
M -A
M -8

2
2

06

2
2

9A
DA

A6
E6

96

2
2

86
F6

4
4

3
3

80
CO

2

97
07
90

2

DO

82
C2

2
2

2
2

BA
FA

4

4

2

92

3

2

02

3

AA

EA

4A

2

1

2

1

B- M
A- 8
M -M

I

4

69

7

2

79

6

3

66

7

2

76

6

3

68

7

2

78

6

3

6/

7.

2

77

6

3

64

7

2

74

6

3

6
6

2

B7
F7
BO
FO

5
5
4
4

3
3

2
2

A7
E7
AD
EO

2
2

A2
E2

5
5

2

B2

4

3

2

F2

4

3

2
2

60

5
5

7

2

7D

6

!
!
!
!
!
I
I

A- M

5A

A+ M - A
8 +M -B
A -MSp.SP 1
B -MSp.SP 1
SP.l -SP, MSp
SP .1-SP, MSp

49
59

2
2

1
1

B

46
56

2
2

1
1

48
58

2
2

1
1

47
57

2 -I
2 1

44

2

1

2

1

C

2

1

16
17

2
2

1
1

40
50

2
2

1
1

3

··....
.... ..
··....
.... ..
• • I

-SP
-SP
-A
-8

b7 -

!~
t~

~} CO ~ ITIIIIIIJ=l
C

b7

-

~} Qrrffirn
b7

-

bO

o-OIDIIIJ
b7

t~

bO

n ~-~-O

:~
t~

0

·.

C

• • I

-

bO

• • 1 t~
• •

0
C

B -M
A M-A
8 - M -B
A B-A
A - M C-A
8 - M - C -B
A -B
B 'A
M - 00
A - 00
B - 00

R.

:~

bO

A -M

10

:~ :

t
t R •
R •

~} CO - rn:m::r;;:J

B

tl~

:

1
1
1
1

MAB}

! ! !
! ! !
! ! !
! R S
! R S
IRS

:~
I': •

4
4
4
4

8

R.
R.
R.

t~ •
t~ •
! R •
t~ •

36
37
32
33

54

!
!
!
!
!
!
!
!

• • t
R.
• • R S R R
• • R S R R
• • R S R R

4F

4C
5C
86
C6
8A
CA

•
•
•
•
•

A- M

40
50
19
6A

2

3
3

63

!
!
!
!
!

A + M -A

18

89
C9
84
C4
85
C5

5 4 3 Z I •
HI.Zye

IAII'...to Zero
Branch If Higher
Branch If ,.; Zero
Branch If Lower Or Same
Branch If < Zero
Branch If Minus
Branch If NOI Equal Zero
Branch If Overflow Clear
Branch If Overflow Set
Branch If Plus
Branch To Subroutine
Jump
Jump To Subroutine
No Operation
Return From Interrupt
Return From Subroutine
SoftWire In"rrupt
Wait for Interrupt

INDEX

= OP

MNEMONIC

OP

-

BRA
BCC
BCS
BED
BGE
BGT
BHI
BLE
BLS
BLT
BMI
BNE
BVC
BVS
BPL
BSR
JMP
JSR
NOP

20
24
25

4
4

2
2

4

2

2

27

4

2C
2E

4
4

2
2

22
2F
23
20
2B

4
4
4
4
4

2
2
2
2
2

26
28

4
4

2
2

29
2A
80

4
4
8

2
2
2

-

EXTNO
:: OP

-

IMPLIED

= OP

-

BRANCH TEST

::
None
CoO
C= 1
Z= 1

N (1)V=O
Z+ IN (1) VI= 0
C+l=O
Z+ IN (1) VI = 1
C+Z=1
N(1) V= 1
N=1
ZoO

V=O
V=1
N=O
6E

AD

4
8

2
2

7E

BO

3
9

3
3

}
01

2

RT!

3B

10

1

RTS
SWI
WAI

39

5

1

3F

12

1

3E

9

1

See Special Operations

(Figure 16)
Advances Prog. CntL Onlv

1

}

See Special Operations

(Figure 16)

MOTOROLA MICROPROCESSOR DATA

3·270

5

4

3

2

1

0

H

I

N

Z

V

C

•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•
•
•

• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
: : : I : •• ••
• •
• • • • • •
• • • • • •
• • • • • •
• • • • • •
--@--

·· .. ..... .. ..
·...

:1: ,:1:1:1
1

• @i· •

1
:

• •

MC6802

FIGURE 16 -

SPECIAL OPERATIONS

SPECIAL OPERATIONS
JSR. JUMP TO SUBROUTINE:

INOXO

I.n~

~

n+ 2
• K = 8·8it Unsigned Value

EXTNO

~

BO =JSR ".
SH = SUbr. Addr.
SL =Subr. Addr.
Next Main Instr.

I"~

n+2
n +3

INX + K

In+2lHand In+21 L Form n+2

Main Program

~

ec

~
SP-2
SP-l
SP

SP-2
SP-l
SP

c:::>
-

= Stack Pointer After EKecutlOn.

BSR. BRANCH TO SUBROUTINE:
~

~~-"";';"--"'"

SP- 2 ,..----:;;=---,

n+l r"'"'-""""-:'::';""-I
n+2 ~'--_ _~

SP-ll--'-'---:;;;"';";'_-i
SP L..,;..--'_ _- '

OK = 7·Bit Signed Value;

~

,,+ 2 ± K

n + 2 Formed From In + 21 H and In + 21 L

JMP. JUMP:

INDXD

EXTENDED
Nextlnstrucnon

RTS. RETURN FROM SUBROUTINE:
PC
Subroutine
39
= RTS

S1

I

I

~BStar.k

c:::>

SP

t

1

NH

SP

t

2

NL

RTI, RETURN FROM INTERRUPT:
f.!;

S

Interrupt Program

I

SP
SP t 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
-

TABLE 6 -

Stack

.sf'

I c:::>

3B.= RTI

SP+ 7

PC

Condition Code
Acmltr'B
AcmltrA
Index Register (X HI
Index Register (XLI
PCH
pel

CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS
COND. CODE REG.
IMPLIED

OPERATIONS
Clear Carry
Clear Interrupt Mask
Clear Overflow
Set Carry
Set Interrupt Mask
Set Overflow
AcmJtr A - CCR
CCR -Acmltr A

MNEMONIC

OP

-

= BOOLEAN OPERATION

CLC

OC
OE
OA
00
OF
OB
06
07

2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1

Cli
CLV
SEC
SEI
SEV
TAP
TPA

CONDITION CODE REGISTER NOTES:
(Bit VI
(Bit CI
(Bit CI
(Bit VI
(Bit VI
(Bit VI

o -C
o

-I

o -V

Test: Result = 10000000?
Test: Result 100000000?
Test: Decimal value of most significant BCD Character greater than ntne?
(Not cleared if previously set.1
Test: Operand = 10000000 prior to execution?
Test: Operand = 01111111 prior to execution?
Test: Set equal to result of N@C after shift has occurred.

II

4

3

2

1

0

H

I

N

Z

V

C

-

R

_

_
_

-

R
-

-

_

R

-

-

-

1 -C
1 -I

-I- - - -

1 -V

-

S

-

-

-

-

- I -

-

-

S

-

A -CCR
CCR '-A
(Bit set

5

--@--1-1-1-1-

1

-

test is true and cleared otherwlsel

10
11

(Bit NI
(Bit VI
(Bit NI
(Alii
(Bit I)

12

(All)

Test: Sign bit of most significant (MSI byte = J?
Test: 2's complement overflow from subtraction of MS bytes?
Test: Result less than zero? (Bit 15 = 11
Load Condition Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously set, a Non·Maskabl,
Interrupt is required to exit the wait state
Set according to the contents of Accumulator A.

MOTOROLA MICROPROCESSOR DATA.

3-271

S

II

MC6802

TABLE 7 -

INSTRUCTION ADDRESSING MODES AND ASSOCIATED EXECUTION TIMES
(Times in Machine Cycle)

'ii

'ii

;

!
0
ii
:l

e

I

ABA
ADC
ADD
AND
ASl
ASR
BCC
BCS
BEA
BGE
BGT
BHI
BIT
BlE
BlS
BlT
BMI
BNE
BPl
BRA
BSR
BVC
BVS
CBA
ClC
CLI
ClR
ClV
CMP
COM
CPX
DAA
DEC
DES
DEX
EaR

NOTE

!

.!!

x

U
U

<

.
2
2

"D

E

.§
2
2
2

.
. ~ -:..
~

u

0

3
3
3

"D

c:

"D

UJ

.=

4

5
5
5

6
6

7
7

~

;

CI.

0
ii

>

c. ';'ii

.!!!

.§

:l

e

cr

INC
INS
INX
JMP
JSR
lDA
lDS
lDX
lSR
NEG
Nap
ORA
PSH
PUl
ROl
ROR
RTI
RTS
SBA
SBe
SEC
SEI
SEV
STA
STS
STX
SUB
SWI
TAB
TAP
TBA
TPA
TST
TSX
TSX
WAI

4
8
4

2

2

..
.
4

5

6
5

7

;

t

..

2
2
2

6

2

7

4
4

5

u

.

<

.§

X

U

E

~

0

11
"D

~

c:

!

)(

UJ

.

.==
"D

~

C.

.§

6

2

2

.
3

4

3
3

4
4

5
5
6
6

3
9

4
4
4
8

5
6
6
7

·
4
4

6
6
10

5
2

3

4

5
5
3

5
6
6
4

.

2
2
2

6

7

·

12
2
2
2
2
2

Interrupt tllne IS 12 cycles from the end of
the InstructIOn being executerl. except follOWing
a WAI Instruction. Then It IS 4 cycles

MOTOROLA MICROPROCESSOR DATA
3-272

'6

6

·
4
4

9

MC6802

SUMMARY OF CYCLE-BY-CYCLE OPERATION
Table 8 provides a detailed description of the information
present on the address bus, data bus, valid memory address
line (VMA), and the read/write line (R/W) during each cycle
for each instruction.
This information is useful in comparing actual with expected results during debug of both software and hardware

as the control program is executed. The information is
categorized in groups according to addressing mo.des and
number of cycles per instruction. (In general, instructions
with the same addressing mode and number of cycles execute in the same manner; exceptions are indicated in the
table.)

TABLE 8 - OPERATIONS SUMMARY

Address Mode
and Instructions
IMMEDIATE
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

CPX
LOS
LOX

R/W

Address Bus

Line

Data Bus

1

1

Op Code Address

1

Op Code

2

2

1

Op Code Address + 1

1

Operand Data

1

1

Op Code Address

1

Op Code

3

2

1

Op Code Address + 1

1

Operand Data (High Order Byte)

3

1

Op Code Address + 2

1

Operand Data (Low Order Byte)

DIRECT
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

CPX
LOS
LOX

3

4

STA
4

STS
STX
5

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Operand

3

1

Address of Operand

1

Operand Data
Op Code

1

1

Op Code Address

1

2

1

Op Code Address + 1

1

Address of Operand

3
4
1

1

Address of Operand

1

Operand Data (High Order Byte)

1
1

Operand Address + 1

1

Operand Data (Low Order Byte)

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Destination Address

3
4

Destination Address

1

Irrelevant Data (Note 1)

Destination Address
Op Code Address

0
1

Data from Accumulator

1

0
1
1

2

1

Op Code Address + 1

1

3
4

0

Address of Operand

1

1

Address of Operand

0

Register Data (H igh Order Byte)

5

1

Address of Operand + 1

0

Register Data (Low Order Byte)

Op Code
Address of Operand
Irrelevant Data (Note 1)

INDEXED
JMP
4

ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

5

CPX
LOS
LOX

6

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset

3

0

Index Register

1

Irrelevant Data (Note 1)

4

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

1

0
1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset
Irrelevant Data (Note 1)

3

0

Index Register

1

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5
1
2

1

Index Register Plus Offset

1

Operand Data

1

Op Code Address

1

Op Code

1

Op Code Address + 1

1

Offset

3
4

0

Index Register

1

Irrelevant Data (Note 1)

0
1

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

Index Register Plus Offset

1

Operand Data (High Order Byte)

1

Index Register Plus Offset + 1

1

Operand Data (Low Order Byte)

5
6

MOTOROLA MICROPROCESSOR DATA
3-273

II

MC6802

TABLE 8 -

RM

Addre. Mode
and Instructions

Addre. Bus

INDEXED (Continued)
STA

6

LSR
NEG
ROL
ROR
TST

7

1

1

Op Code Address

1

Op Code

1

Op Code Address + 1

1

Offset

3
4

0
0
0

Index Register

1

Irrelevant Data (Note 1)

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

Index Register Plus Offset

1

Irrelevant Data (Note 1)

1

Index Register Plus Offset

0

Operand Data

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset
Irrelevant Data (Note 1)

3

0

Index Register

1

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5
6

1

Index Register Plus Offset

1

Current Operand Data

0

Index Register Plus Offset

1

Irrelevant Data (Note 1)

7

110

Index Register Plus Offset

0

New Operand Data (Note 3)

(Note
3)

II

STS
STX

7

JSR

8

Data Bus

Line

2

5
6
ASL
ASR
CLR
COM
DEC
INC

OPERATIONS SUMMARY (CONTINUED)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Offset

3

0

I ndex Register

1

Irrelevant Data (Note 1)

4

0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

5
6

0

Index Register Plus Offset

1

Irrelevant Data (Note 1)

1

Index Register Plus Offset

Operand Data (High Order Byte)

7

1

Index Register Plus Offset + 1

0
0

1

1

Op Code Address

1

Op Code
Offset

Operand Data (Low Order Byte)

2

1

Op Code Address + 1

1

3

0

Index Register

1

Irrelevant Data (Note 1)

4
5

1

Stack Pointer

Return Address (Low Order Byte)

1

Stack Pointer - 1

0
0

6

0

Stack Pointer - 2

1

Irrelevant Data (Note 1)

7

Index Register

1

Irrelevant Data (Note 1)

8

0
0

Index Register Plus Offset (w/o Carry)

1

Irrelevant Data (Note 1)

Return Address (High Order Byte)

EXTENDED
,

JMP

3
ADC
ADD
AND
BIT
CMP

EOR
LOA
ORA
SBC
SUB

,

4

CPX
LOS
LOX

5

STA A
STA B

5

ASL
ASR
CLR
COM
DEC
INC

LSR
NEG
ROL
ROR
TST

6

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Jump Address (High Order Byte)

3

1

Op Code Address + 2

1

Jump Address (Low Order Byte)

1

1

Op Code Address

1

Op Code
Address of Operand (High Order Byte)

2

1

Op Code Address + 1

1

3
4

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

1

Address of Operand

1

Operand Data
Op Code

1

1

Op Code Address

1

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3
4

1

Op Code Address + 2

1

Adalress of Operand (Low Order Byte)

1

Address of Operand

1

Operand Data (High Order Byte)

5

1

Address of Operand + 1

1

Operand Data (Low Order Byte)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Destination Address (High Order Byte)

3
4

1

Op Code Address + 2

1

Destination Address (Low Order Byte)

0

Operand Destination Address

1

Irrelevant Data (Note 1 )

5

1

Operand Destination Address

0

Data from Accumulator

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address '+ 2

1

Address of Operand (Low Order

4

1

Address of Operand

1

Current Operand Data

0

Address of Operand

1

Irrelevant Data (Note 1)

1/0

Address of Operand

0

New Operand Data (Note 3)

5
6

(Note

3)

MOTOROLA MICROPROCESSOR DATA
3-274

~yte)

MC6802

TABLE 8 Addr_Mode
and I nltructions

OPERATIONS SUMMARY (CONTINUED)

Addr_Bul

Rm

Data Bus

Line

EXTENDED (Continued)
STS
STX

6

JSR

9

1

1

Op Code Address

1

OpCode

2

1

Op Code Address + 1

1

Address of Operand (High Order Byte)

3

1

Op Code Address + 2

1

Address of Operand (Low Order Byte)

4

0

Address of Operand

1

Irralevant Data (Note 1)

5
6

1

Address of Operand

Operand Data (High Order Byte)

1

Address of Operand + 1

0
0

1

1

Op Code Address

1

OpCode

2

1

Op Code Address + 1

1

Address of Subroutine (High Order Byte)

3

1

Op Code Address + 2

1

Address of Subroutine (Low Order Byte)

4

1

Subroutine Starting Address

1

Op Code of Next Instruction

5
6

1

Stack Pointer

0

Return Address (Low Order Byte)

1

Stack Pointer - 1

0

Return Address (High Order Byte)

7

Stack Pointer - 2

1

Irrelevant Data (Note 1 )

8

0
0

Op Code Address + 2

1

Irrelevant Data (Note 1 )

9

1

Op Code Address + 2

1

Address of Subroutine (Low Order Byte)

Operand Data (Low Order Byte)

INHERENT
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
DES
DEX
INS
INX

DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA

SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST

2

4

PSH

4

PUL
4

TSX
4

TXS
4

RTS

5

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Op Code of Next Instruction

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3
4

0
0

Previous Register Contents

1

Irrelevant Data (Note 1)

New Register Contents

1

Irrelevant Data (Note 1)

1

1

Op Code Address

1

Op Code
Op Code of Next Instruction

2

1

Op Code Address + 1

1

3

1

Stack Pointer

0

Accumulator Data

4

0

Stack Pointer - 1

1

Accumulator Data

1

1

Op Code Address

1

OpCode

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3

0

Stack Pointer

1

Irrelevant Data (Note 1)

4

1

Stack Pointer + 1

1

Operand Data from Stack

1

1

Op Code Address

1

Op Code

2
3
4

1

Op Code Address + 1

1

Op Code of Next Instruction

0
0

Stack Pointer

1

Irrelevant Data (Note 1)

New Index Register

1

Irrelevant Data (Note 1)

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

3

0

I ndex Register

1

4

0

New Stack Pointer

1

Irrelevant Data

1

1

Op Code Address

1

Op Code
Irrelevant Data (Note 2)

. Op Code of Next Instruction
Irrelevant Data

2

1

Op Code Address + 1

1

3
4

0

Stack Pointer

1

Irrelevant Data (Note 1)

1

Stack Pointer + 1

1

Address of Next Instruction (High
Order Byte)

5

1

Stack Pointer + 2

1

Address of Next Instruction (Low
. Order Byte)

MOTOROLA MICROPROCESSOR DATA
3-275

MC6802

TABLE 8 -

OPERATIONS SUMMARY (CONCLUDED)

R/W

Address Mode
and Instructions
INHERENT (Continued)

Address Bus

WAI

9

RTI

10

II
SWI

12

Deta Bus

Line

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Op Code of Next Instruction

3

1

Stack Pointer

0

Return Address (Low Order Byte)

4

1

Stack Pointer - 1

0

Return Address (High Order Byte)

5

1

Stack Pointer - 2

0

Index Register (Low Order Byte)

6

1

Stack Pointer - 3

0

Index Register (High Order Byte)

7

1

Stack Pointer - 4

0

Contents of Accumulator A

8
9

1

Stack Pointer - 5

0

Contents of Accumulator B

1

Stack Pointer - 6

1

Contents of Condo Code Register
Op Code

1

1

Op Code Address

1

2

1

Op Code Address + 1

1

Irrelevant Data (Note 2)

3

0

Stack Pointer

1

Irrelevant Data (Note 1)

4

1

Stack Pointer + 1

1

Contents of Condo Code Register from
Stack

5

1

Stack Pointer + 2

1

Contents of Accumulator B from Stack

6

1

Stack Pointer + 3

1

Contents of Accumulator A from Stack

7

1

Stack Pointer + 4

1

Index Register from Stack (High Order
Byte)

8

1

Stack Pointer + 5

1

Index Register from Stack (Low Order
Byte)

9

1

Stack Pointer + 6

1

Next I nstruction Address from Stack
(High Order Byte)

10

1

Stack Pointer + 7

1

Next Instruction Address from Stack
(Low Order Byte)

1

1

Op Code Address

1

Op Code

2
,3

1

Op Code Address + 1

1

Irrelevant Data (Note 1 )

1

Stack Pointer

0

Return Address (Low Order Byte)

4

1

Stack Pointer - 1

0

Return Address (High Order Byte)

5

1

Stack Pointer - 2

0

Index Register (Low Order Byte)

6

1

Stack Pointer - 3

0

Index Register (High Order Byte)

7

1

Stack Pointer - 4

0

Contents of Accumulator A

8

1

Stack Pointer - 5

0

Contents of Accumulator B

9

1

Stack Pointer - 6

0

Contents of Condo Code Register

10

0

Stack Pointer - 7

1

Irrelevant Data (Note 1)

11

1

Vector Address FFFA (Hex)

1

Address of Subroutine (High Order
Byte)

12

1

Vector Address FFFB (Hex)

1

Address of Subroutine (Low Order
Byte)

RELATIVE
BCC
BCS
BEQ
BGE
BGT

BHI
BLE
BLS
BLT
BMI

BNE
BPL
BRA
BVC
BVS

4

1

1

Op Code Address

1

Op Code

2

1

Op Code Address + 1

1

Branch Offset

3

0
0

Op Code Address + 2

1

Irrelevant Data (Note 1)

Branch Address

1

Irrelevant Data (Note 1)

4

BSR

8

1

1

Op Code Address

1

Op Code

2

1

Op Code Address +1

1

Branch Offset

3

0

Return Address of Main Program

1

Irrelevant Data (Note 1)

4

1

Stack Pointer

0

Return Address (Low Order Byte)

5

1

Stack Pointer - 1

0

Return Address (High Order Byte)

6

0

Stack Pointer - 2

1

Irrelevant Data (Note 1)

7

0

Return Address of Main Program

1

Irrelevant Data (Note 1)

8

0

Subroutine Address (Note 4)

1

Irrelevant Data (Note 1)

NOTES:
1. If device which is addressed during this cycle uses VMA. then the Data Bus will go to the high-impedance three-state condition.
Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus.
2. Data is ignored by the MPU.
3. For TST, VMA=O and Operand data does not change.
4. MS Byte of Address Bus= MS Byte of Address of BSR instruction and LS Byte of Address Bus= LS Byte of Sub-Routine Address.

MOTOROLA MICROPROCESSOR DATA
3-276

MC6802

MECHANICAL DATA AND ORDERING INFORMATION
ORDERING INFORMATION
Package Type

Order Number

Frequency MHz

Temperature

Plastic
P Suffix

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
- 40°C to + 85°C
O°C to 70°C
- 40°C to + 85°C
O°C to 70°C

MC6802P
MC6802CP
MC68A02P
MC68A02CP
MC68B02P

Cerdip
S Suffix

1.0
1.0
1.5
1.5
2.0

O°C to 70°C
- 40°C to + 85°C
O°C to 70°C
- 40°C to + 85°C
O°C to 70°C

MC6802S
MC6802CS
MC68A02S
MC68A02CS
MC68B02g

PIN ASSIGNMENT

VSS

RESET

HALT

EXTAL

MR

XTAL '

IRQ

E

VMA

RE

NMI

VCC Standby

BA

Rm

VCC

00

AO

01

A1

02

A2

03

A3

04

A4

05

A5

06

A6

07

A7

A15

A8

A14

A9

A13

A10

A12

A11

VSS

MOTOROLA MICROPROCESSOR DATA
3-277

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC6804J1

Technical Summary

8-Bit Microcomputer Unit
MC6804J1 HMOS (high-density NMOS) microcomputer unit (MCU) isa member of the M6804
Family of serial processing microcomputers. This device displays all the versatility of an MCU
whose design-ability to process 8-bit variables one bit Cit time already makes it tremendously cost
effective.
This technical summary contains limited information on the MC6804J1. For detailed information,
refer to the advanced information data sheet for the MC6804J1, MC6804J2, MC6804P2, and
MC68704P2 8-bit microcomputers (MC6804JlID)drto the M6804 MeV Manual (DLE404/D).
Major hardware and software features of the MC6804P2 MCU are:
• On-Chip Clock Generator
• True Bit Manipulation
• Memory Mapped liD
• Bit Test and Branch Instruction
• 304 Bytes Self-Check ROM
• Software Programmable 8-Bit Timer with
7-Bit Prescaler
• Conditional Branches
• Timer Pin is Software Programmable as
• Single Instruction Memory Examine/
Change
Clock Input or Timer Output
• 504 Bytes of User Program Space ROM
• 30 Bytes of Data RAM
• User Selectable Constant Current Pullup Devices available on LSTIL and Open-Drain Interface
Ports
• Mask Selectable Edge- or Level-Sensitive Interrupt Pin

a

I

BLOCK DIAGRAM
TIMER

ACCUMULATOR
A
INDIRECT
REGISTER

PA4
PORT
PA5
A
I{O
LINES PAS

PORT
A
REG.

DATA
DlR.
REG.

CPU
CONTROL

X

INDIRECT
REGISTER

PBO
PBI
PB2 PORT
B
PB3
PB4 110
PB5 LINES
PBS
PB7

CPU

STACK

PA7

504x 8
USER PROGRAM ROM
304xB
SELF-CHECK ROM

PROGRAM
COUNTER
HIGH PCH
PROGRAM
COUNTER
PCL
LOW

ALU

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MoiOROLA MICROPROCESSOR DATA
3-278

MC6804J1

SIGNAL DESCRIPTION
VCC AND VSS
Power is supplied to the microcomputer using these
two pins. VCC is +5 volts (±O.5 V) power, and VSS is
ground.
IRQ
This pin provides the capability for asynchronously applying an external interrupt to the microcomputer.
EXTAL AND XTAL
These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal is connected to these pins
to provide a system clock. Selection is made by a manufacturing mask option. The different clock generator options are shown in Figure 1, along with crystal
specifications.
Internal Clock Options
The crystal oscillator start-up time is a function of many
variables. To ensure rapid oscillator start-up, neither the
crystal characteristics nor load cap'acitances should exceed recommendations. When using the on-boatd oscillator, the MCU should remain In a reset condition, with
the RESET pin voltage below VIRES +, until the, oscillator
has stabilized at its operating frequency. See Figure 2 for
resistor/capacitor oscillator options.

NC
EXTERNAL
CLOCK
INPUT

TIMER
The TIMER pin can be configured to operate in either
the input or output mode. As input, this pin is connected
to the prescaler input and serves as the timer clock. As
output, the timer pin reflects the contents of the DOUT
bit of the timer status/control register, the last time the
TMZ bit was logic high.
RESET
The RESET pin is used to restart the processor to the
beginning of a program. The program counter is loaded
with the address of the restart vector. This should be a
jump instruction to the first instruction of the main program. Together with the MDS pin, the RESET pin selects
the operating mode of the MCU.
MDS
The mode select (MDS) pin places the MCU into special
operating modes. When this pin is logic high at the exit
of the reset state, the decoded state of PA6 and PA7 is
latched to determine the operating mode. This choice can
be either the single-chip, self-check, or EPROM programming. However, if MDS is logic low atthe end ofthe reset
state, the single-chip operating mode is automatically
selected. No external diodes, switches, transistors, etc.
are required for single-chip mode selection.
INPUT/OUTPUT LINES (PA4-PA7, PBO-PB7)
These 12 lines are arranged into one 4-bit port (A) and
one 8-bit port (B). All lines are programmable as either

EXTAL

EXTAL
XTAL

MCU
ICRYSTAL MASK
OPTIONJ

XTAL

MCU
IRESISTORCAPACITOR MASK
OPTION:

EXTERNAL CLOCK

I *DENOTES NCIGND, GROUNDING
PIN 4 WILL REDUCE Rfl NOISE,;
EXTERNAL RESISTOR CAPACiTOR

lal

XTAL

o

CRYSTAL PARAMETERS
AT CUT PARALlEl RESONANCE CRYSTAL
Co ~ 7 pf MAXIMUM
fREO.·" 11 MHz
RS ~ 50 OHMS MAXIMUM

EXTAL

PIEZOELECTRIC CERAMIC RESONATORS MAY BE
SUBSTITUTED fOR THE CRYSTAl. fOllOW
MANUfACTURER 5 CERAMIC. RESONATOR
SPECifiCATIONS

NOTE

MCU
{CRYSTAL MASK
OPTIONI

CRYSTAL

Keep crystal leads and circuit connections as short as possible

Figure 1. Clock Generator Options and Crystal Parameters

MOTOROLA MICROPROCESSOR DATA:
3-279

II

MC6804J1

----- 15 pFAT
- - - 22 pF AT
......... 27 pF AT
¥ ...:.~.-.-..Jio.......
,..--1--+----+---I._._ 36 pF AT
::Ii 15 "-'< "
..·_·....·50 pF AT
20 \

\

~

a~

~ 10

u..

"-

~.:.~-,
1\·
.......
. . , ·I~...~ ..........
"'-

"""

...... 1 . . . . ' "

25°C
25°C
25°C
25°C
25°C

-

8.0

-~

......

~

......:: ......:;:: ..'::.-:- ~::-: ........
••'

......

1

7.0

..........::::.,.. ~:.=-':' :::~.: ~~~ .::::~~
10
12
RL. LOAD RESISTANCE (k{}1

14

16

6.8

h~~-=--=-+--+--+-+--+--+--+--+---l

6.64.5 .4.6

18

4.7

4~

4j ~O 5.1
~2
Vec. SUPPLY VOLTAGE (VI

5.3

5.4

5.5

(bl TYPICAL FREQUENCY VARIATIONS @ Cl =15 pF. 10 k{}

(al TYPICAL FREQUENCY VS RESISTANCE

II

--

_

I'....

'. "'.
••

1---+--+-----4--+--+--+--+-----1f___
-+=~~

9.8 1----11---+--+--+---+---+---t---r--- f---

.... .......

9.6 1-----11---+--+--+---+---+---+----l--+.'-:c••......,.

¥

~

9.4

t; 9.2

~

ffi 9.0

e:

...: 8.8
8.6

1----11---+--+--+-+- +---='.....~--t--+-_~OoC •••••• ••••
_1--'- "" .....
1----11---+--+:J:;.!- .. ,
__
••••••• •
'l.~OC _I- - .~
1...0--1--•• ,
......_1--

~

_""I'

1..-1"""'"

.

SIj°,S..I---""""'-

.... '-' t--I--- ~

~

8.4 L...._'":----":----L_-L.._~_~_:'_:_--'-:--"-4.5 4.6 4.7
4.8 4.9 5.0
5.1
5.2
5.3 5.4
5.5
VCC. SUPPLY VOLTAGE (VI

(el TYPICAL FREQUENCY VARIATIONS

@

CL = 50 pF. 3 k{}

Figure 2. Typical Frequency SeleCtion for
Resistor/Capacitor Oscillator Options
inputs or outputs under software control of the data direction registers.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
There are 12 input/output pins. All pins of each port
are programmable as inputs or outputs under the control
of the data direction registers (DDR).
The port liD programming is accomplished by writing
the corresponding bit in the port DDH to a logic one for
output, or a logic zero for input, as shown in Figure 3.
When the registers are programmed as outputs, the
latched data is readable regardless of the logic levels at
the output pin due to output loading.
All the liD pins are LSTTL compatible as both inputs
and outputs. In addition, both ports may use either or
both of two manufacturing mask options; open drain output, or internal pull-up resistor for CMOS compatibility.
Any write to a port writes to all of its data bits even
though the port DDR may be set to input. This can be
used as a tool to initialize th~ data registers and avoid

undefined outputs. However, care must be exercised when
using read-modify-write instructions. The data read corresponds to the pin level if the DDR is an input or to the
latched output data when the DDR is an output.
The 12 bidirectional lines may be configured by port
to be the standard configuration (LSTTL), or either mask
option; LSTTLICMOS, or open drain. Port B outputs are
LED compatible.
Port Data Registers ($00, $01)
The port data registers are not initialized on reset. These
registers should be initialized before changing the DDR
bits to avoid undefined levels.

MOTOROLA MICROPROCESSOR DATA
3-280

Port A ($00)

x
Port B ($01)

x

x

x

MC6804J1

VCC

r----

DATA
DlRECTIDN REGISTER
BIT
(I)

~~
I-

Z

ffi~

I-

Z
-

Z
Z

0

I
I
I
IL _ _ _

LATCHED
OUTPUT
DATA
BIT

...,
I
I
I

I

...1I _ _ _..

u

DATA
DIRECTION
REGISTER
BIT
1
1

0

OUTPUT
DATA
BIT

OUTPUT
STATE

INPUT
TO
MCU

0

0

0

1
X

1
HI-Z

1
PIN

II

*For CMOS option transistor acts as resistor (approximately 40 km to VCCFor LSTTLlopen-drain options transistor acts as low current clamping diode to Vee-

Figure 3. Typical .110 Port Circuitry

With regard to Port A only, the four LSB bits are unused.
These bits are "don't care" (X) bits when written to but
are always logic high when read.

Port Data Direction Registers ($04, $05)
Port DDRs configure the port pins as either outputs or
inputs. Each port pin can be programmed individually to
be an input or an output. A zero in the pin's corresponding
DDR bit programs it as an input; a logic one programs it
as an output. On reset, all the DDRs are initialized to a
logic zero state to put the ports in the input mode.

Port A ($04)

Port B ($05)
3

With regard to Port A, the four LSB bits are cleared
(logic zero) by reset. These bits must not be set (logic
one).

MEMORY
The MCU memory map (Figure 4) consists of 4352 bytes
of addressable memory, I/O register locations, and four
levels of stack space. This MCU has three separate memory spaces: program space, data space, and stack space.
The MCU 'is capable of addressing 4096 bytes of program space memory with its program counter and 256
bytes of data space memory with its instructions. Program space memory includes self-check ROM, program
ROM, self-check and user program vectors, and reserved
memory locations.
A non-accessible subroutine stack space RAM is provided. This stack space consists of a last-in-first-out (LIFO)
register. This register is used with inherent addressing
to stack the return address for subroutines and interrupts.
Indirect X and Y register locations $80 and $81 are
generally used as pointers for such tasks as indirect addressing to data space locations. Short direct addressing
allows access to the four data space addresses $80-$83
with single byte opcodes. The operations allowed are
increment, decrement, load, and store. Data space locations $82 and $83 can be used for 8-bit counter locations.

MOTOROLA MICROPROCESSOR DATA,
3-281

MC6804J1

BYTES

ADDRESS

000 0

:;:~

$000

....
.... :;

RESERVED
(2784 BYTES!

278 3

$ADF

278 4

:::~

II

$AEO

SELF-CHECK ROM
(304 BYTES!

00 0

PORT A DATA REGISTER

$00

00 1

PORT B DATA REGISTER

$01

00 2

$02

00 3

RESERVED
(2 BYTES!

004

PORT A DDR

$04

00 5

PORTS DDR

$05

006

$06

008

RESERVED
(3 BYTES!

009

TIMER STATUS CONT. REG.

010

::::::

RESERVED
(14 BYTES!

~

023

11

$COE

308 8

.::~

096

:::~
$OFF

358 4

$EOO

PROGRAM ROM
(504 BYTES!

408 9
409 0
409 1
409 2
409 3
409 4
409 5

USER DATA SPACE ROM
(72 BYTES!

127

RESERVED
(32 BYTES!

128

INDIRECT REGISTER X

......

""1"$ 17

........

$80

129

INDIRECT REGISTER Y

$81

USER DATA SPACE RAM
(30 BYTES!

.. ...,.$ 82

159

I

160

$FF7

'"$ 7F

130

;~

:::~

408 7
408 8

$09

......,$ OA

$Cl0

RESERVED
(496 BYTES!

358 3

::~

$08

$ 18

024
308 7

$03

RESERVED
(93 BYTES!

:~

""'$ 9F
$AD

=~

SELF-CHECK
IRQ VECTOR

$FF8
$FF9

25 2

SELF-CHECK
RESTART VECTOR

$FFA

25 3

PRESCALER REGISTER

$FD

$FFB

254

TIMER COUNT REGISTER

$FE

USER
IRQ VECTOR

$FFC

255

ACCUMULATOR

$FE

USER
RESTART VECTOR

$FFE

$FFD

$FC

DATA SPACE

$FFF

PROGRAM SPACE

STACK SPACE
LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4

Figure 4. Memory Map

MOTOROLA MICROPROCESSOR DATA
3-282

MC6804J1

REGISTERS
ACCUMULATOR (A)
The accumulator is· a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.
7
A

INDIRECT REGISTERS (X,V)
These two registers are used to maintain pointers to
other memory locations in data space. They are used in
the register-i"direct addressing mode and can beaccessed with the direct, indirect, short direct, or bit set!
clear modes.

x
y

PROGRAM COUNTER (PC)
The program counter is a 12-bit register that contains
the address of the next byte to be fetched. The program
counter is contained in low byte (PCl) and high nibble
(PCH).
11

STACK
A last-in-first-out (UFO) stack is incorporated in the MCU
that eliminates the need for.a stack pointer. This nonaccessible subroutine stack space is implemented in separate RAM, 12 bits wide. Whenever a subroutine call or
interrupt occurs, the contents of the PC are shifted into
the top register of the stack. At the same time, the top
register is shifted one level deeper. This happens to all
registers, with the bottom register falling out of the stack.
Whenever a return from subroutine or interrupt occurs,
the top register is shifted into the PC and all lower registers are shifted one level higher. The stack RAM is four
levels deep. If the stack is pulled more than four times
with no pushes, then the address that was stored in the
bottom level of the stack is shifted into the PC.

SELF CHECK
The MCU implements two forms of internal check: self
check and ROM verify. Self check performs an extensive
functional check of the MCU using a signature analysis
techni,que. ROM verify uses a similar method to check
the contents of program ROM.
Self-check mode is selected by holding the MDS and
PA7 pins logic high and the PA6 pin logic low as RESET
goes low to high. ROM verify mode is entered by holding
MDS, PA7, and PA6 logic high as RESET* goes low to
high. Unimplemented program space ROM locations are
also tested. Monitoring the self-check mode's stages for
successful completion requires external circuitry, see
M6804 MeV Manual (DLE404/D).

8 7

PCH

PCl

RESET

FLAGS (c,z)
The first flag, the carry (C) bit, is seton a carry or borrow
out of the arithmetic logic unit (AlU). It is cleared if the
arithmetic operation does not result in a carry or borrow.
The C bit is also set to the value of the bit tested in a bit
test instruction. It participates in the rotate left (ROLA)
instruction, as well.
The second flag, the zero (Z) bit, is set if the result of
the last arithmetic or logic operation was equal to zero.
Otherwise, it is cleared. Bit test instructions do not affect
the Z bit.
_ _-:N:.:.;O;.;.:R::.;:M;.::Al:..;F..::;:LA.:;:G;,:;,S_ _

.-I'1

C

z

____IN_T_ER_R_UP_T_FLA
__
GS__~.~I

C

z

RESET
All resets of the MC6804J1 are caused by the external
reset input (RESET). A reset can be achieved by pulling
the RESET pin to logic low for a minimum of 96 oscillator
cycles.
During reset, a delay of 96 oscillator cycles is needed
before allowing the RESET input to go high. If power is
being applied, RESET must be held low long enough for
the oscillator to stabilize and then provide the 96 clocks.
Connecting a capacitor and resistor to the RESET input,
as shown in Figure 5 below, typically provides sufficient
delay.
+5V
4.7 k

There are two sets of these flags. One set is for interrupt
processing (interrupt mode flags). The other set is for
normal operations (program mode flags). When an interrupt occurs, a context switch is made from the program flags to the interrupt flags. An RTI forces the context
switch back. While in either mode, only the flags for that
mode are available. A context switch does not affect the
value of the C or Z bits. Both sets of flags are cleared by
RESET.

:c
MCU

Figure 5.Powerup RESET Delay Circuit

MOTOROLA MICROPROCESSOR DATA
3-283

1.O /tF

II

MC6804J1

INTERRUPT
The MCU c~e interrupted by applying it logic low
signal to the IRQ pin. However, a manufacturing mask
option determines whether the falling edge or the actual
low level of the IRQ pin is sensed to indicate an interrupt.
EDGE-SEN~ITIVE

OPTION

When the IRQ pin is pulled low, the internal interrupt
request latch is set. Prior to each instruction fetch, this
interrupt request latch is tested. If its output is low, an
interrupt sequence is initiated at the end of the current
instruction, provided the interrupt mask is cleared. Figure
6 contains a flowchart that illustrates both the reset and
interrupt sequences.
The interrupt sequence consists of one cycle during
which:

II

The interrupt request latch is cleared;
The interrupt mode flags are selected;
The program counter (PC) is saved on the stack;
The interrupt mask is set; and
The IRQ vector jump address is loaded into the PC.
The IRQ vector jump address is $FFC-$FFD in the singlechip mode and$FF8-$FF9 in the self-check mode. The
contents ofthese locations are not decoded as an address
to which the PC should jump. Instead, they are decoded
like any other EPROM program word. So,.it is essential

that the vector contents specify a JMP instruction in addition to the starting address of the interrupt service routine. If required, this routine should save the values of
the accumulator and the X and Y registers, since these
values are not stored on the stack.
Internal processing of the interrupt continues until a
return from interrupt (RTf) instruction is processed. During RTI the interrupt mask is cleared and the program
mode flags are selected. The next instruction of the program is then fetched and executed.
When the interrupt was initially detected and the interrupt sequence started, the interrupt request latch was
cleared so that the next interrupt could be detected. These
steps occurred even as the first interrupt was being serviced. However, even though the second interrupt edge
set the interrupt request latch during the first interrupt's
processing, the second interrupt's sequence can not begin until completion of the interrupt service routine for
the first interrupt. Completion of an interrupt service routine is always accomplished using an RTI instruction to
return to the main program. The interrupt mask, which
is not directly available to the programmer, is cleared
during the last cycle of the RTI instruction.

LEVEL-SENSITIVE OPTION
Actual operation of the level-sensitive and edge-sensitive options are similar. However, the level-sensitive
option does not have an interrupt request latch. Since
there is no interrupt request latch, the logic level of the
IRQ pin is checked to detect the interrupt. Also, in the
interrupt sequence there is no need to clear the interrupt
request latch. These differences are shown in Figure 6.

O-DOR.
I -INTERRUPT MASK
O-INTERRUPTREOUEST
lATCHIEOGE
SENSITIVE OPTlIl/OlI
IFF-TCR
IOO-TSCR
IFF-PRESCAlER

Figure 6. Reset and Interrupt Flowchart

MOTOROLA MICROPROCESSOR DATA
3-284

MC6804J1

POWERUP AND TIMING
During the powerup sequence, the interrupt mask is
closed. This precludes any false interrupts. The PC is also
loaded with the appropriate restart vector (jump instruction).
To open the interrupt mask, the user should do a JSR
to an initialization subroutine that ends with an RTI instead of an RTS. The RTI opens the interrupt mask. Typical RESET and IRQ processes and their relationship to
the interrupt mask are shown in Figure 7.
Maximum interrupt response time is six machine cycles.
This includes five cycles for the longest instruction plus
one for stacking the PC and switching flags.

TIMER
A block diagram of the MC6804J1 timer circuitry is
shown in Figure 8. The timer logic in the MCU is comprised of a simple 8-bit counter called the timer counter.
This counter is decremented by a 7-bit prescaler at a rate
determined by the timer status/control register (TSCR).

PRESCALER
The prescaler is a 7-bit counter used to extend the maximum interval of the overall timer. This counter is clocked
by a signal from the TIMER pin or by the internal sync
pulse. It divides the frequency received by some factor

JMP-START
VECTOR IFFE-FFF!

.................................................

START IROUTlNE!
INSTRUCTION II-N!

I

INTERRUPT
MASK
CLOSED

LAST INSTRUCTION
JSR INIT

I

INIT
INITIALIZATION
SUBROUTINE

I
LAST INSTRUCTION
RTI

I

PROGRAM

MASK
OPEN

I
IRQ
RECOGNIZED

.......................

I

IRQ
SERVICE
ROUTINE

INTERRUPT
MASK
CLOSED

I
LAST INSTRUCTION
RTI

PROGRAM

I

........................

MASK
OPEN

Figure 7. Interrupt Mask

MOTOROLA MICROPROCESSOR DATA

3-285

•
MICROCOMPUTER INTERNAL BUS

s:

0
-t
0::g

•

~I
3:
Co)

0
::g

N

0

Q)

::g

CO

SYNC

READ

WRITE

8-BIT COUNTER
PRESCAlER

TIMER
PIN

b7

WRITE

bO

SElECT

t - - - - - - I I l-Df-8

INITIALIZE

READ

TIMER COUNT REGISTER
(TCR)

TIMER STATUS/CONTROL
REGISTER (TSCR)

s:o
0)

TMZ

"'1:1

-0

CO

e
....10

(')

m

CJ)
CJ)

0

jIl

C

.~

»
TIMER PIN STATUS
TOUT

PRESCALER
CLOCK

TIMER
PIN

0
1

TIMER PIN
SYNC

INPUT MODE
OUTPUT MODE

Figure 8. Timer Block Diagram

MC6804J1

to create the prescaler output. The factor by which the
TIMER pin signal is divided is called the prescaler tap.
The value of this tap is selected by three bits of the TSCR
(PSO-PS2). These bits control the division ofthe prescaler
input within the range of divide-by-20 , to divide-by-27.

MSB

LSB

RESET:
1

TIMER COUNTER
TIMER STATUS/CONTROL REGISTER (TSCR) ($09)

The timer counter, which may be read or loaded under
program control, is decremented from a maximum value
of 256 toward zero by the prescaler output. Both are decremented on rising clock edges.
The prescaler register and timer count register are
readable and writeable. A write to either one will take
precedence over the normal counter function. For example, if a value is written to the timer count register,
and this write and a decrement-to-zero occur at the same
time, the write takes precedence. TSCR bit one (TMZ) is
not set until the next timer time out.
TIMER PIN

The TIMER pin may be programmed as either an input
or an output. Its status depends on the value of TSCR bit
5 (TOUT). This relationship is shown in the TIMER pin
status section of Figure 8. The frequency of the internal
clock applied to the TIMER pin must be less than tbyte,
which is (fosc/48).

5

I TMZ I

4

I TOUT I DOUT I

PSI

PS2

PS1

PSO

RESET:

o

TMZ -Timer Zero
1 = Timer count register has decremente<;l to zero
since the last time the TMZ bit was read.
0= This bit is cleared by a read of the TSCR if TMZ
is read as logic one.
Bit 6
Not used by this register.
TOUT - Timer Output
1 = Output mode is selected for the timer.
0= Input mode is selected for the timer.
DOUT - Data Output
Latched data at this bit is sent to the TIMER pin when
both the TMZ and TOUT bits are logic high.

TIMER INPUT MODE

In the timer input mode, TOUT is logic zero and the
TIMER pin is connected directly to prescaler input. So,
the prescaler is clocked by the signal from the TIMER pin.
The prescalerdivides the TIMER pin clock input by the
prescaler tap. The prescaler output then clocks the 8-bit
timer count register. When this register is decremented
to zero, it sets TSCR bit one (TMZ). This TMZ bit can be
tested under program control.
TIMER OUTPUT MODE

In the output mode, the TIMER pin is output. TOUT is
a logic one. The prescaler is clocked by the internal sync
pulse. This pulseisa divide-by-48 ofthe internal oscillator
(fos c/48). From this point on, operation is similar to that
described for the input mode. However, in the output
mode, once the prescaler decrements the timer counter
to zero, the high TMZ bit state is used to latch the data
at TSCR bit 4 (DOUT), onto the TIMER pin.
NOTE

TMZ is normally set to logic one when TCR de.crements to zero and the timer times out. However,
it may be set by a write of $00 to the timer counter
or by a write to bit 7 of TSCR.
TIMER COUNT REGISTER ($FE)

The timer count register reflects the current count in
the internal8-bit counter. The register is the timer counter
and can be read or written.

PSI -

Prescaler Initialization
1 = Prescaler begins to decrement.
0= Prescaler is initialized and counting is'inhibited.

PSO-PS2
These bits are used to select the prescaler tap. The
coding of the bits is shown below:

PS2

PS1

PSO

0

0

0

1

0

0

1

2

0

1

0

4

0

1

1

8

1

0

0

16
32

1

0

1

1

1

0

64

1

1

1

128

It is recommended that MVI or loading and storing
instructions be used when changing bit values in the
TSCR. Read-modify-write instructions can cause the TMZ
to assume an unexpected state.
During reset, the TSCR is set to all zeroes; the TIMER
pin is in the high impedance input mode; and DOUT
LATCH is forced to a logic high. At the same time, PSOPS2 coding sets the prescaler tap at divide-by-one, and
bit 3 initializes the prescaler.

MOTOROLA MICROPROCESSOR DATA
3-287

Divide By

I

MC6804J1

TIMER PRESCALER REGISTER ($FD)
The timer prescaler register reflects the current count
ofthe 7-bit prescaler. This register is the prescaler counter
and can be read or written.

value back to memory or to the register. All INC and DEC
forms along with all bit manipulation instructions use this
method. Refer to the following list of instructions.
Function

Mnemonic

Increment Memory Location
MSB

LSB

RESET:
1

INC

Increment A

INCA

Increment XP

INCX

Increment YP

INCY

Decrement Memory Location

INSTRUCTION SET

I

The MCU has a set of 42 basic instructions. They can
be divided into five different tYpes: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is the accumulator; the other is obtained from
memory using one of the addressing modes. Refer to the
following list of instructions.

DEC

Decrement A

DECA

Decrement XP

DECX

Decrement YP

DECY

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list of instructions.
Function

Mnemonic

Branch if Carry Clear

BCC
(BHS)

Branch if Higher or Same
Mnemonic

Function

Branch if Carry Set

BCS

Load A from Memory

LDA

Branch if Lower

(BLO)

Load XP from Memory

LOX

Branch if Not Equal

BNE

Load YP·from Memory

LDY

Branch if Equal

BEQ

Store A in Memory

STA

Add to A

ADD

Subtract from A

SUB

BIT MANIPULATION INSTRUCTIONS

AND Memory to A

AND

Transfer A to XP

TAX

Transfer A to YP

TAY

Transfer YP to A

TVA

The MCU is capable of setting or clearing any bit which
resides in the 256 bytes of data space, where all port
registers, port DDRs, timer, timer control, and on-chip
RAM reside. An additional feature allows the software to
test and branch on the state of any bit within these 256
locations. The bit set, bit clear, and bit test and branch
functions are all implemented with a single instruction.
For the test and branch instructions, the value of ,the bit
tested is also placed in the carry bit of the condition code
register. Refer to the following list of instructions.

Transfer XP to A

TPA

Clear A

CLRA

Clear XP

CLRX

Clear YP

CLRY

Arithmetic Compare with Memory

CMP

Move Immediate Value to Memory

MVI

Function

Mnemonic

Branch If Bit n is Set

BRSET n(n = Q... 7)
BRCLR n(n = Q... 7)

Arithmetic Left Shift of A

ASLA

Branch If Bit n is Clear

Complement A

COMA

Set

Rotate A Left and Carry

ROLA

Clear Bit n

Bi~

n

BSET n(n=Q ... 7)
BCLR n(n=Q ... 7)

READ-MODIFY -WRITE INSTRUCTIONS

CONTROL INSTRUCTIONS

These instructions read a memory ·Iocation or a register, modify or test its contents, and write the modified

These instructions are used to control processor operation during program execution. The jump conditional

MOTOROLA MICROPROCESSOR DATA
3-288

MC6804J1

(JMP) and jump to subroutine (JSR) instructions have no
register operand. Refer to the following list of instructions.
Function

stack space. The term "effective address" (EA) is used in
describing the various addressing modes. Effective address is defined as the address from which the argument
for an instruction is fetched or stored.

Mnemonic

Return from Subroutine

RTS

IMMEDIATE

Return from Interrupt

RTI

No Operation

NOP

In the immediate addressing mode, the operand is located in program ROM. It is contained in the byte immediately following the opcode. The immediate
addressing mode is used to access constants that do not
change during program execution, such as a constant
used to initialize a loop counter.

Jump to Subroutine

JSR

Jump Unconditional

JMP

IMPLIED INSTRUCTIONS
Since the accumulator and all other registers are located in
RAM, many implied instructions exist. Some of the instructions
recognized and translated by the assembler are shown below:
Mnemonic
AS LA

Becomes

Mnemonic

Becomes

ADD $FF

INCX

INC $80

BHS

BCC

INCY

INC $81

BLO

BCS

LDXI

MVI $80 DATA

CLRA

SUB $FF

LDYI

MVI $81 DATA

CLRX

MVI $80 #0

NOP

BEQ (PC) +1

CLRY

MVI $81 #0

TAX

STA $80

DECA

DEC $FF

TAY

STA $81

DECX

DEC $80

TXA

LOA $80

DECY

DEC $81

TVA

LOA $81

INCA

INC $FF

In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the 256 bytes of data space with a single twobyte instruction.

SHORT DIRECT
In the short direct addressing mode, the MCU has four
locations in data space RAM it can use, ($80, $81, $82,
and $83). The opcode determines the data space RAM
location, and the instruction is only one byte. Short direct
addressing is a subset of the direct addressing mode~
The X and Y registers are at locations $80 and $81, respectively.

EXTENDED

Some examples of valuable instructions not specifically recognized by the assembler are shown below:
Mnemonic

DIRECT

Meaning

In the extended addressing mode, the effective address
of the argument is obtained by concatenating the four
least-significant bits of the opcode with the byte following
the opcode to form a 12-bit address. Instructions using
the extended addressing mode, such as JMP or JSR, are
capable of branching anywhere in program space. An
extended addressing mode instruction is two bytes long.

BCLR 7,$FF

Ensures A is plus

BSET 7, $FF

Ensures A is minus

BRCLR 7, $FF

Branch if A is plus

RELATIVE

BRSET 7, $FF

Branch if A is minus

BRCLR 7, $80

Branch if X is plus (BXPL)

BRSET 7, $80

Branch if X is minus (BXMI)

BRCLR 7, $81

Branch if Y is plus (BYPL)

BRSET 7, $81

Branch if Y is minus (BYMI)

The relative addressing mode is only used in conditional branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the
opcode is added to the PC if, and only if, the branch
conditions are true. Otherwise, control proceeds to the
next instruction. The span of relative addressing is from
-15 to + 16 from the opcode address. The programmer
need not calculate the offset when using the Motorola
assembler, since it calculates the proper offset and checks
to see that it is within the span of the branch.

OPCODEMAP
Table 1 is a listing of all the instruction set opcodes
applicable to the MC6804J1 MCU.

BIT SET/CLEAR

ADDRESSING MODES
The MCU has nine different addressing modes to provide the programmer with an opportun.ity to optimize the
code for all situations. It deals with objects in three different address spaces: program space, data space, and

In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte in which
the specified bit is to be set or cleared. Thus, any bit in
the 256 locations of data space memory that can be written to can be set or cleared with a single two-byte instruction.

MOTOROLA MICROPROCESSOR DATA
3-289

II

Table 1. Opcode Map

•
Bit Manipulation
Instructions

Register/Memory, Control, and

Read/Modify/Write Instructions

Branch Instructions
~

Register / Memory and

Read/Modify/Write

~--A

Hi

-Hi

~-...........

BNE

BNE

BEQ

B.EQ

BCC

BCC

BCS

BCS

JSRn

.. JMPn

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

B.EQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

COMA

BEQ

BEQ

BCC

B.CC

BCS

BCS

JSRn

JMPn

ROLA

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BRCLR6

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BRCLR7

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

INC

DEC

I BRSETO

BSETO

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

INC

DEC

I BRSETl

BSETl

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

INC

DEC

I BRSET2

BSET2

BCC

BCC

BCS

BCS

JSRn

JMPn

INC

DEC

13

BRSET3

BSET3

SUB

SUB

I BRSET4

BSET4

CMP

CMP

BRSET5

BSET5

AND

AND

BSET6

INC

BSED

DEC

3:

o

a
~

BNE
BNE

3:

N
CD
o

o
~
"a
~
n

m
en

A

I

BNE

BRCLRO

BCLRO

LOA'

LOA

BRCLRl

BCLRl

STA

STA

RTI

BRCLR2

BCLR2

ADD

ADD

RTS

BRCLR3

BCLR3

SUB

SUB

BRCLR4

BCLR4

CMP

CMP

BRCLR5

BCLR5

AND

AND

B~LR6

INC

.INC

BCLR7

DEC

DEC

LOA

LOA

I

REL

I,

3:

(")
0)

STA
ADD

ADD

CO

o
A

1010'

o
:a

~

R')'
,

MVI

0 11 0".

~

w

~

~

o

BNE

BNE

BEQ

BEQ

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

LOA

STA

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

LOA

STA

S D

I

5

o

5013

BNE

BNE

BEQ

BNE

BEQ

BEQ

BNE

BCC

BCC

BCS

BCS

.REl!l

RElLi

BEQ

BCC

JRSn

JMPn

LOA

STA

BRSET6

JSRn

JMPn

LDA

STA

BRSED

BTBI,

RELI2

BCC

BCS

BCS

f.XTI2

Abbreviations lor Address Modes
INH
Inherent
S·D
Short Direct
B-T-B Bit Test and Branch
IMM 'Immediate
DIR
Direct
EXT
Extended
REL
Relative
Bit Set/ Clear
BSC
R:IN.D ilegister Indirect

LEGEND
Indicates Instruction Reserved for Future Use

Indicates Illegal Instruction

Cycles
Mnemonic

Bytes

d

""j

4
I

LOA

R·IND

~o". . '""~~_'
Opcode in Binary

e....

MC6804J1

the program to branch based on the cOl1dition of any
readable bit in the 256 locations of data space. The span
of branching is from -125 to + 130 from the opcode
address. The state of the tested bit is also transferred to
the carry flag.

CAUTION
The corresponding OORs for ports A and B are write
only registers (registers at $04 and $05). A read
operation on these registers· is undefined. Since
BSET and BClR areread-modify-write functions,
they cannot be used to set or clear a OOR bit; all
"unaffected"bits would be set. Write all OOR bits
in a port using a single-store instruction.
BIT TEST AND BRANCH
The bit test and branch addressing· mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear) is
included in the opcode. The data space address of the
byte to be tested is in the single byte immediately following the opcode byte;. The third byte is sign extended
to 12 bits and becomes the offset added to the PC if the
condition is true. This single three-byte instruction allows

REGISTER-INDIRECT
In the register-indirect addressing mode, the operand
is at the address in data space pointed to by the contents
of one of the indirect registers, X or Y: The particular
indirect register is selected by bit 4 of the opcode. Bit 4
decodes into an address that represents the register, $80
or $81. A register-indirect instruction.is one byte long.
INHERENT
In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. These instructions are one byte long.

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to +7.0

V

Input Voltage

Vin

-0.3 to +7.0

V

Operating Temperature Range (Comm.)

TA

o to 70

°c

Rating

Operating Temperature Range (Ind.)
Storage Temperature Range
Junction Temperature

TA

-40 to +85

°c

Tstg

-55 to +150

°c

TJ

150

°c

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum-rated voltages
to this high-impedance circuit. ~or proper operation it is recommended that Vinand Vout be constrained to the range VSS "" (Vin or Vout) "" VCC.
Reliability of operation is enhanced if unused inputs except EXTAL are connected to an appropriate logic voltage level (e.g .• either VSS or Vccl.

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can
be obtained from:
TJ=TA+(PO-eJA)
(1i
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
eJA
Junction-to-Ambient, °CIW
Po
= PINT+PPORT
= ICCxVCC' Watts - Chip Internal Power
PINT
PPORT = Port Power Dissipation,
Watts - User Determined

For. most applications PPORT 1 - SYNC TIMING

SYNC

r---11____________________________1r--1L

~

Figure 12. Clock Generator Timing Diagram

MOTOROLA MICROPROCESSOR DATA

3..292

MC6804J1

PORT DC ELECTRICAL CHARACTERISTICS
(VCC= +5.0 Vdc±0.5 Vdc, VSS=GND, TA=O°C to 70°C, unless otherwise noted)
Characteristic

Symbol

,.

..

Min

Typ

Max

Unit

Ports A and Timer (Standard)
VOL

-

-

0.5

V

VOH

2.3

-

-

V

Input High Voltage

VIH

2.0

Vce

V

Input Low Voltage

VIL

-0.3

-

0.8

V

Hi-Z State Input Current

ITSI

-

4

40

!LA

Output Low Voltage, ILoad = 0.4 mA
Output High Voltage, ILoad = - 50

JAA

Port A (Open Drain)
Output Low Voltage, ILoad=0.4 mA

VOL

-

-

0.5

V

Input High Voltage

VIH

2.0

-

Vce

V

Input Low Voltage

VIL

-0.3

-

0.8

V

Hi-Z State Input Current

ITSI

4

40

!LA

4

40

!LA

-

0.5

V

-

V

-

-

V

Open Drain Leakage (Vout=VccI

ILOD

-

Port A (CMOS Drive)
VOL

-

JAA

VOH

VCC-1.0

Output High Voltage, ILoad = - 50 !LA

VOH

2.3

Input High Voltage, ILoad= 7"300 !LA Max

VIH

2.0

VIL

-0.3

ITSI

-

Output Low Voltage ILoad= 0.4 mA (Sink)
Output High Voltage, ILoad = -10

Input Low Voltage, ILoad = - 300

JAA Max

Hi-Z State Input Current (Vin = 0.4 V to Vcc) ..

-

Vce

V

0.8

V

-300

!LA

Port B (Standard)
Output Low Voltage, ILoad= 1.0 mA

VOL

Output Low Voltage,ILoad = 10 mA (Sink)

VOL

-

VOH

2.3

-

-

V

Input High Voltage

VIH

2.0

-

Vce

V

Input Lpw Voltage

VIL

-0.3

-

0.8

V

Hi-Z State Input Current

ITSI

-

8

80

!LA

-

0.5

V

Output High Voltage; ILoad = -100

JAA

0.5

V

1.5

V

Port B (Open Drain)

Output Low Voltage, ILoad= 10 mA (Sink),

VOL

-

Input High Voltage

VIH

2.0

Input Low Volt~ge

VIL

-0.3

Hi-Z State Input Current

ITSI

Output Low Voltage, ILoad =

to mA

VOL

Open Drain Leakage (Vout=VCC)

ILOD

-

1.5

V

Vce

V

0.8

V

8

80

!LA

8

80

!LA

-

0.5

V

-

1.5

V

-

-

V

VCC

V

Port B (CMOS Drive)

-

Output Low Voltage, ILoad = 1.0 mA

VOL

Output High Voltage, ILoad = 10 mA (Sink)

VOL

Output High Voltage, ILoad= -10 !LA

VOH

VCC- 1.O

Output High Voltage, ILoad= -100 !LA

VOH

2.3

Input High Voltage, ILoad = -300 !LA Max

VIH

2.0

Input Low Voltage, ILoad = - 300 !LA Max

VIL

-0.3

Hi-Z State Input Current (Vin = 0.4 V to Vcc)

ITSI

-

V

0.8

V

-

-300

!LA

-

100

!LA

-4.0

!LA

Ports A and B (Low Current Clamping Diode*)
Input High Current VIH = Vce + 1.0 V

IIH

Input Low Current VIL =0.8 V

IlL

-

*Denotes not tested unless specified on ordering form.

MOTOROLA MICROPROCESSOR DATA
3-293

II

MC6804J1

4.0

~XPECTEb

1 3.5

MAX4~~5C V ,

....

I!! 3.0
B 2.5

,j

~

/'

~ 2.0

~/

..... '. 5

$ 1.

5.0V
25°C

/

.., ..

/' ..•.•...

i

~

5

•....

/.~

0.0 0

~(0.5 V. JOO jtAl

100

200
300
400,
500
600
VOL. LOW·LEVEL OUTPUT VOLTAGE (mVI

.1EJpECTJD: MIN 4.5 V
85"C -

I

-200

-300

(2.3 V. - 50 jtAl
~X

iE~PECTED

i MIN 4.5 V
85°C

~ -200

_....

....... ....... V

!

-100

~

~

"

J
2.5
3.0
3.5
4.0
VOH. HIGH·lEVEl OUTPUT VOlTAG,E IVI

101.1

I

~

10

....

r--~

I

I

:

!

./
V.'

..

'

V

.'

.. .'
.'

.. .'

••e,

'

'

EXPECTED
MIN 4.5 V
85°C

<'

....

100

,\0.5 V. 11 mAl~
200
300
400
VOL. lOW·lEVElOUTPUT VOLTAGE (mVI

500

X= SPEC PT.

Figure 16. Typical VOL vs IOL for Port B

/

EXPECTED

/

-200

1-300

MI:5~.g v

~I

1
II

j
2.5

t

~

(2.3 V. -100 jtAl
....
ifi -100 I---X

2.0

./

....

/

I"
00

3
4
5
VOH. HIGH-lEVEL OUTPUT VOLTAGE IVI

Figure 15. Typical VOH vs IOH
for Port A with CMOS Pullups

-400

5.0

I V .. ·•·

~'.L
11(..,
.,~ .'

J
2

I',

II
Ii

5.0 V .
25°1j1

J

r-M~X4~~5C~'

TYPICAL
EXPECTED
5.0 V
, MAX 5.5 V
25°C -,- -40°C

X=SPEC PT.

....~
~

I TYPICAL
EXPECTED

I -i

j
-400

4.5

Figure 14. Typical VOH VI IOH
for Port A and TIMER

i

-300

I

X=SPEC PT.

is

!I!

\

II

.1

:

Figure 13. Typical VOL vs IOL
for Port A and TIMER

II

:

J

-400
2.0

800

X= SPEC PT.

i
i~

-/EXPEC~ED

TYPlCJL5.0 V
rl-MAX 5.5 V
25°C -40°C

j

r--

700

-100

is

~
!I!

,,,..

0.5

i

ti;

'

••••• EXPECTED--,MIN 4.5 V
85°C - ' - -

V ....... .'

~

(2.3 V;- 50 jtAl
X

r--

// .•..••...

~ 1.0

j

~YPICAL
/

i

i

1-

TYPICAl- ---, EXPECTED
5.0 V
MAX 5.5 V
-40°C
25°C -

:

EX~~~TEDI- TYPI1CAl

i

~

I

I

iii -300

1

$

1

~

!
J

V

: MIN 4.5 V,i
85°C

:: - 200

-I

3.0
3.5
4.0
VOH. HIGH-lEVEL OUTPUT VOLTAGE IVI

........ ....r:.... ...... ~L...J""
(2.3 V. -100 jtAl ....
100 I--X

II

-400

5.0 V
25°C

I'
---,

--t

EX~CTEt-

f--

MAX 5.5V-,- f--40°C

I

;
I

j

4.5

X=SPEC PT.

-500

5.0

2.0

2.5

3.0
' 3.5
4.0
4.5
VOH. HIGH·lEVEl OUTPUT VOLTAGE IVI

X= SPEC PT.

Figure 17. Typical VOH vs IOH for Port B

Figure 18. Typical VOH vs IOH
for Port B with CMOS Pullups

MOTOROLA MicROPROCESSOR DATA •
3-294

5.0

5.5 ,

MC6804J1

ORDERING INFORMATION
The following information is required when ordering a
custom MCU. The information may be transmitted to Motorola using the following media:
MOOS@>, disk file
MS@>-DOS/PC-DOS disk file (360K)
EPROM(s) 2516, 2716, 2532, 2732
To initiate a ROM pattern for the MCU, it is necessary
to first contact the local field service office, sales person,
or Motorola representative.
FLEXIBLE DISKS

Several types of flexible disks (MOOS or MS-DOS/PCDOS disk file) may be submitted for pattern generation.
They should be programmed with the customer program,
using positive logic sense for address and data. The diskette should be clearly labeled with the customer's name,
date, project or product name, and the filename containing the pattern.
In addition to the program pattern, a file containing the
program source code listing can be included. This data
will be kept confidential and used to expedite the process
in case of any difficulty with the pattern file.
MDOS Disk File
MOOS is Motorola's Disk Operating System available
on the EXORciser® development system. The disk media
submitted must be a single-sided, single-density, 8-inch
MOOS compatible floppy diskette. The diskette must contain the minimum set of MOOS systern files in addition
to the pattern file.
The .LO output of the M6804 cross assembler should
be furnished. In addition, the file must be produced using
the ROLLOUT command, so that it contains the absolute
image of the M6804 memory. It is necessary to include
the entire memory image of both program and data space.
All unused bytes, including those in the user space, must
be set to logic zero.
MS·DOS/pc·DOS Disk File

MS-DOS is Microsoft's Disk Operating System. PC-DOS
is IBM®'s Personal Computer Disk Operating System. Disk
media submitted must be standard density (360K), double-sided 5 114 inch compatible floppy diskette. The diskette must contain the object file code in Motorola's Srecord format. The S-record format is a character-based
object file format generated by M6804 cross assemblers
and linkers on IBM PC style machines.

EPROMS

Four K of EPROM are necessary to contain the entire
MC6804J1 program. Two 2516 or 2716 type EPROMs or
a single 2532 or 2732 type EPROM can be submitted for
pattern generation. The EPROM is programmed with the
custo,mer program using positive logic sense for address
and data, Submissions on two EPROMs must be clearly
marked. All unused bytes, including the user's space,
must be set to zero.
If the MC6804J1 MCU ROM pattern is submitted on
one 2532 or 2732 EPROM, or on two 2516 or 2716 type
EPROMs, memory map addressing is one-for-one. The
data spaCI;l ROM runs from EPROM address $018 to $05F
and program space ROM runs from EPROM address $EOO
to $FF7, with vectors from $FFC to $FFF.
For shipment to Motorola, EPROMs should be placed
in a conductive IC carrier and packed securely. Styrofoam
is not acceptable for shipment.
Verification Media
All original pattern media, EPROMs or floppy disks, are
filed for contractual purposes and are not returned.' A
computer listing of the ROM code will be generated and
returned along with a listing verification form. The listing
should be thoroughly checked and the verification form
should be completed, signed, and returned to Motorola.
The signed verification form constitutes the contractual
agreement for the creation of the customer mask. To aid
in the verification process, Motorola will program customer supplied blank EPROM(s) or DOS disks from the
data file used to create the custom mask.
ROM Verification Units (RVUs)
Ten MCUs containing the customers ROM pattern will
be sent for program verification. These units will have
been made using the custom mask, but are for the purpose of ROM verification only. For expediency, the MCUs
are unmarked, packaged in ceramic, and tested with five
volts at room temperature. These RVUs are free with the
minimum order quantity, but are not production parts.
These RVUs are not guaranteed by Motorola Quality Assurance.
Ordering Information
The following table provides generic information pertaining to the package type and temperature for the
MC6804J1. This MCU device is available in the 20-pin
dual-in-line (DIP) package.

Generic Information
Package Type
Plastic
(P Suffix)

Temperature
O°C to 70°C
- 40°C to + 85°C

Order Number
MC6804J1P
MC6804J1CP

MOOS is a trademark of Motorola Inc.
MS-DOS is a trademark of Microsoft, Inc.
EXORciser is a registered trademark of Motorola Inc.
IBM is a registered trademark of International Business Machines Corporation.

MOTOROLA'MICROPROCESSORDATA
3·295

I

MC6804J1

MECHANICAL DATA
PIN ASSIGNMENTS

VSS

RESET

IRO

PAJ

Vee

PA6
PA5
PA4
PBJ

I

TIMER

PB6

PBO

PB5
PB4

PB2

MOTOROLA MICROPROCESSOR DATA
3-296

MOTOROLA

ISEMICONDUCTOR . . . . . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA
MC6804J2
Technical Summary

8-Bit Microcomputer Unit
MC6804J2 HMOS (high-density NMOS) microcomputer unit (MCU) is a member of the M6804
Family of serial processing microcomputers. This device displays all the versatility of an MCU
whose design-ability to process 8-bit variables one bit at a time already makes it tremendously cost
effective.
This technical summary contains limited information on the MC6804J2. For detailed information,
refer to the advanced information data sheet for the MC6804J1, MC6804J2, MC6804P2, and
MC68704P2 8~bit microcomputers (MC6804J1/D) or to the M6804 MeV Manual (DLE404/D).
Major hardware and software features of the MC6804J2 MCU are:
• On-Chip Clock Generator
• True Bit Manipulation
• Memory Mapped I/O
• Bit Test and Branch Instruction
• 304 Bytes Self-Check ROM
• Software Programmable 8-Bit Timer with
7-Bit Prescaler
• Conditional Branches
• Single Instruction Memory Examine/
• Timer Pin is Software Programmable as
Change
Clock Input or Timer Output
• 1000 Bytes of User Program Space ROM
• 30 Bytes of Data RAM
• User Selectable Output Drive Options, LSTTL, LSTTLICMOS, and Open-Drain Interface Ports
• Mask Selectable Edge- or Level-Sensitive Interrupt Pin

II

BLOCK DIAGRAM

TIMER

ACCUMULATOR
A
INDIRECT
REGISTER

PA4
PORT
A PA5
I/O
LINES PAS

PORT
A
REG.

DATA
DlR.
REG.

CPU
CONTROL

X

INDIRECT
REGISTER

PBO
PBl
PB2 PORT
B
PB3
PB4 I/O
PB5 LINES
PBS
PB7

CPU

STACK

PA7

1000 x 8
USER PROGRAM ROM
304xB

PROGRAM
COUNTER
HIGH PCH
PROGRAM
COUNTER
PCL
LOW

ALU

SELF-CHECK ROM

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-297

MC6804J2

SIGNAL DESCRIPTION

TIMER
The TIMER pin can be configured to operate in either
the input or output mode. As input, this pin is connected
to the prescaler input and' serves as the timer clock. As
output, the timer pin reflects the contents. of the DOUT
bit of the timer status/control register, the last ttme the
TMZ bit was logic high.

VCCANDVSS
Power is supplied to the microcomputer using these
two pins. VCC is + 5 volts (± 0.5 V) power, and VSS is
ground.
IRQ

This pin provides the capability for asynchronously applying an external interrupt to the microcomputer.
EXTAL AND XTAL

II

These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal is connected to these pins
to provide a system clock. Selection is made by a man~
ufacturing mask option. The different clock generator options are shown in Figure 1, along with crystal
specifications.

RESET
The RESET pin is used to restart the processor to the
beginning of a program. The program counter is loaded
with the address of the restart vector. This should be a
jump instruction to the first instruction of the main program. Together with the MDS pin, the RESET pin selects
the operating mode of the MCU.

Internal Clock Options
The crystal oscillator start-up timeis a function of many
variables. To ensure rapid oscillator start-up, neither the
crystal characteristics nor load capacitances should exceed recommendations. When using the on-board oscillator, the MCU should remain in a reset condition, with
the RESET pin voltage below VIRES +, until the oscillator
has stabilized at its operating frequency. See Figure 2 for
resistor/capacitor oscillator options.

MDS
The mode select (MDS) pin places the MCU into special
operating modes. When this pin is logic high at the exit
of the reset state, the decoded state of PA6 and PA7 is
latched to determine the operating mode. This choice can
be either the single-chip, self-check, or EPROM programming. However, if MDS is logic low at the end of the reset
state, the single-chip operating mode is automatically
selected. No external diodes, switches, transistors, etc.
are required for single-chip mode selection.
INPUT/OUTPUT LINES (PA4-PA7, PBO-PB7)
These 12 lines are arranged into one 4-bit port (A) and
one 8-bit port (8). All lines are programmable as either
+5V

NC
EXTERNAL
CLOCK
INPUT

4.7 k

MCU
ICRYSTAl MASK
OPTION)

EXTAl
XTAl

MCU
IRESISTOR·CAPACITOR MASK
OPTIONJ

I* DENOTES NCIGNO. GROUNDING
PIN 4 Will REDUCE RFI NOISE.)

EXTERNAL CLOCK

EXTERNAL RESISTOR·CAPACITOR
CRYSTAL PARAMETERS

la)
C1

,n". -C:~ n",
MCU
ICRYSTAl MASK
OPTION I

CRYSTAL PARAMETERS
AT - CUT PARAllEl RESONANCE CRYSTAL
Co = 7 pF MAXIMUM
FREO. = 11 MHz
RS = 50 OHMS MAXIMUM
PIEZOElECTRIC CERAMIC RESONATORS MAY BE
SUBSTITUTED FOR THE CRYSTAL. FOLLOW
MANUFACTURER'S CERAMIC RESONATOR
SPECIFICATIONS.

NOTE: Keep crystal leads and circuit connections as short as possible.

Figure 1. Clock Generator Options and Crystal Parameters

MOTOROLA MI§ROPROCESSOR DATA
3-298

MC6804J2

25r---~--~----r---'---~----r---~--~

15 pF AT
- - - 22 pF AT
••••••••• 27 pF AT
. . ~......,..'-:-+----+---+---I._..
36 pF AT
~ 15 .~~ "
··_······50 pF AT
20 \

\

;

."-••~."

f:;

"'-

..

:_ 10

,~., ~~
~~~.~ •••• t .......

8.2

25°C 25°C 1 _
25°C
25°C 25°C _

8.0
7.8

i

~

7.6

~ 7.4
:::>

~...:

f'......

. . . :: . . .::...:': .":,

~=: ~

7.2
7.0
6.8

o2~--~--~--~~--~lo~~1~2--~1~4--~16~~18·

i-"""'"

---...... -

r---tf----+_-+'l!j0C _
--

I""

....

..,

6.64.5

4.6

4.7

RL. LOAD RESISTANCE (kO)
(a)

-- ......
.............

1--'-'

>u

...!joe

....
... - ••••

.~ •••• t:-..:-;.......-t-c.:.:+-+_-+--+_--i

4.8

4.9
5.0
5.1
5.2
VCC. SUPPLY VOLTAGE (V)

(b) TYPICAL FREQUENCY VARIATIONS

TYPICAL FREQUENCY VS RESISTANCE

@

5.3

5.4

5.5

Cl: 15 pF. 10 kO

9.8 r-__I--+---+--+---t--+--+---t--.- -

II

.......

9.6 t----1--+--+--t---t--+--+--t---1r:....."
~ 9.4 t----1--+--+~_t_--t---+_~•...?-'.~••'••+__:_t____I
~
~4()OC •••••• •••••
~-~.
f:; 9.2 t----1---+--+~!::-.T" ."
_ ..

_1-"-

~

S 9.0

If

••••••

•• ,

••••••••
'llloC_~-~
,-_"1'
I~_

i.,....---~

S!j~~1"""""

_:..--.,....

_ .. ~~~

...:8.8
8.6 _

8.4 ~-.l_--l.._ _--'--,--L..__~__-L-__-L-_.l..-_L...--.l
4.5
4.6 4.7
4.8 4.9 5.0
5.1
5.2
5.3 5.4
5.5
VCC. SUPPLY VOLTAGE IV)
(e)

TYPICAL FREQUENCY VARIATIONS

@

CL: 50 pF. 3 kO

Figure 2. Typical Frequency Selection for
Resistor/Capacitor Oscillator Options

inputs or outputs under software control of the data direction registers.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
There are 12 input/output pins. All pins of each port
are programmable as inputs or outputs under the control
of the data direction registers (UDR).
The port I/O programming is accomplished by wri~ing
the corresponding bit in the port DDR to a logic one for
output, or a logic zero for input,as shown in Figure 3.
When the registers are programmed as outputs, the
latched data is readable regardless of the logic levels at
the output pin due to output loading.
All the I/O pins are LSTTL compatible as both inputs
and outputs. In addition, both ports may use either or
both of two manufacturing mask options; open drain output, or internal pull-up resistor for CMOS compatibility.
Any write to a port writes to all of its data bits even
though the port DDR may be set to input. This can be

used as a tool to· initialize the data registers and avoid
undefined outputs. However, care must be exercised when
using read-modify-write instructions. The data read corresponds to the pin level if the DDR is an input or to the
latched output data when the DDR is an output.
The 12 bidirectional lines may be configured by port
to be the standard configuration (LSTTL), or either mask
option; LSTTUCMOS, or open drain. Port B outputs are
LED compatible.
Port Data Registers ($00, $01)
The port data registers are not initialized on reset. These
registers should be initialized before changing the DDR
bits to avoid undefined levels.

MOTOROLA MICROPROCESSOR DATA
3-299

Port A ($00)
4
3

x
Port B ($01)
4

3

x

x

x

MC6804J2

Vee

r----

DATA
DIRECTION REGISTER
BIT

I
I
I
IL _ _ _

LATCHED
OUTPUT
DATA
BIT

II

DATA
DIRECTION
REGISTER
BIT

OUTPUT
DATA
BIT

1
1
0

0
1
X

OUTPUT
STATE

INPUT
TO
MCU

,

0

HI·Z

0
1
PIN

*For eMOS option transistor acts as resistor (approximately 40 kQl to Vee·
For LSTTLlopen-drain options transistor acts as low current clamping diode to Vee·

Figure 3. Typical 1/0 Port Circuitry

. With regard to Port A only, the four LSB bits are unused.
These bits are "don't care" (X) bits when written to but
are always logic high when read.
Port Data Direction Registers ($04, $05)
Port DDRs configure the port pins as either outputs or
inputs. Each port pin can be programmed individually to
be an input or an output. A zero in the pin's corresponding
DDR bit programs it as an input; a logic one programs it
as an output. On reset, all the DDRs are initialized to a
logic zero state to putthe ports in the input mode:
Port A ($04)

Port B ($05)
4

3

I
With regard to Port A only, the four LSB bits are cleared
(logic zero) by reset. These bits must not be set (logic
one).

MEMORY
The MCU memory map (Figure 4) consists of 4352 bytes
of addressable memory, 110 register locations, and four
levels of stack space. This MCU has three separate memory spaces: program space, data space, and stack space.
The MCU is capable of addressing 4096 bytes of program space memory with its program counter and 256
bytes of data space memory with its instructions. Program space memory includes self-check ROM, program
ROM, self-check and user program vectors, and reserved
memory locations.
A non-accessible subroutine stack space RAM is provided. This stack space consists of a last-in-first-out (LIFO)
register. This register is used with inherent addressing
to stack the return address for subroutines.
Indirect X and Y register locations $80 ahd $81 are
generally used as pointers for such tasks as indirect addressing to data space locations. Short direct addressing
allows access to the four'data space addresses $80-$83
with single-byte opcodes. The operations allowed are increment, decrement; load, and store. Data· space locations $82 and $83 can be used for 8-bit counter locations.

MOTOROLA MICROPROCESSOR DATA
3-300

MC6804J2

BYTES

ADDRESS

000 0

$000

;:~

RESERVED
(2784 BYTES)

BYTES

~r:-

278 3

$ADF

278 4

$AEO

000

PORT A DATA REGISTER

$00

001

PORT B DATA REGISTER

$01

002

003

RESERVED
(2 BYTES)

004

PORT A DDR

$04

005

PORT BOOR

$05

006

RESERVED
(3 BYTES)

$06

008
009

TIMER STATUS CONT. REG.

$09

:r
1-

010

":;:=

SELF-CHECK ROM
(304 BYTES)

;:~

308 7

$COF

308 8

$Cl0

RESERVED
(14 BYTES)

031
032

.... ,...

USER DATA SPACE ROM
(72 BYTES)

09 5
09 6

-; ....

12

:.:~

PROGRAM ROM
(1000 BYTES)

::~

7 ,...

12 8

INDIRECT REGISTER X

12 9

INDIRECT REGISTER Y

13 0

;'1..-

USER DATA SPACE RAM
(30 BYTES)
RESERVED
(93 BYTES)

408 7

$FF7

9 ,...
15
160

408 8

$FF8

::~

408 9
409 0
409 1
409 2
409 3
409 4
409 5

SELF-CHECK
IRQ VECTOR

$FF9

SELF-CHECK
RESTART VECTOR
USER
IRQ VECTOR
USER
RESTART VECTOR

$FFA

RESERVED
(32 BYTES)

$02
$03

$OB

.. J OA
1$ 17
18

~

.... 1""

$5F
$60

~~

$7f
$80
$81
$82

~ 9F

$AO

~

25 2

$FC

25 3

PRESCALER REGISTER

$FD

mc

25 4

TIMER COUNT REGISTER

$FE

$FFD

25 5

ACCUMULATOR

$FF

$FFB

$FFE
DATA SPACE

$FFF

PROGRAM SPACE

STACK SPACE
LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4
(LIFO)

Figure 4. Memory Map

MOTOROLA MICROPROCESSOR DATA
3-301

II

MC6804J2

REGISTERS
ACCUMULATOR (AI .1
The accumulator' is· a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data' manipulations.
7

0

I

A

INDIRECT REGISTERS (X, V)
These two registers are used to maintain pointers to
other memory locations 'in data space. They are used in
the register-indirect addressing mode and can be accessed with the direct, indirect, short direct, or bit set!
clear modes.

STACK
A last-in-first-out (LIFO) stack is incorporated in the MCU
that eliminates the need for a stack pointer. This nonaccessible subroutine stack space is implemented in separateRAM, 12 bits wide. Whenever a subroutine call or
interrupt occurs, the contents of the PC are shifted into
the top register of the stack. At the same time, the top
register is shifted one level deeper. Thi.s happens to all
registers, with the bo~tom register falling out of the stack.
Whenever a return from subroutine or interrupt occurs,
the top register is shifted into the PC and all lower registers are shifted one level higher. The stack RAM is four
levels deep. If the stack is pulled more than four times
with no pushes, then the address that was stored in the
bottom level of the stack is shifted into the PC.

SELF CHECK

7

x
y

PROGRAM COUNTER (PC)
The program counter is a 12-bit register that contains
the address of the next byte to be fetched. The program
counter is contained in low byte (PCl) and high nibble
(PCH).

"

The MCU implements two forms of internal check: self
check and ROM verify. Self check performs an extensive
functional check of the MCU using a signClture analysis
technique. ROM verify uses a similar method to check
the contents of program ROM.
Self-check mode is selected by holding the MDS and
PA7 pins logic high and the PA6 pin logic low as RESET
goes low to high. ROM verify mode is entered by holding
MDS, PA7, and PA6 logic high as RESET goes low to
high. Unimplemented program space ROM locations are
also tested. Monitoring the self-check mode's stages for
successful completion requires external circuitry, see
M6804 MeV Manual (DlE404/D).

8 7

PCH

PCl

RESET

FLAGS (c,z)
The first flag, the carry (C) bit, is set on a carry or borrow
out of the arithmetic logic unit (ALU). It is cleared if the
arithmetic operation does not result in a carry or borrow.
The C bit is also set to the value of the bit tested in a bit
test instruction. It participates in the rotate left (ROlA)
instruction, as well.
The second flag, the zero (Z) bit, is set if the result of
the last arithmetic or logic operation was equal to zero.
Otherwise, it is cleared. Bit test instructions do not affect
the Z bit.

_____N_O_RM_A_l_F_~_G_S______~·LI
__~IN~T~ER~R~U~PT~F~~~G~S____~.~I

___C__L__z__
C

RESET
All resets of the MC6804J2 are caused by the external
reset input (RESET). A reset can be achieved by pulling
the RESET pin to logic low for a minimum of 96 oscillator
cycles.
During reset; a delay of 96 oscillator cycles is needed
before allowing the RESET input to go high. If power is
being applied, RESET mustbe held low long enough for
the oscillator to stabilize and then provide the 96 clocks.
Connecting a capacitor and resistor to the RESET input,
as shown in Figure 5 below, typically provides sufficient
delay.

~

+5V

4.7k

z

There are two sets ofthese flags. One set is for interrupt
processing (interrupt mode flags). The other set is for
normal operations (program mode flags). When an interrupt occurs, a context switch is made from the program flags to the interrupt flags. An RTI forces the context
switch back. While in either mode, only the flags for that
mode are available. A context switch does not affect the
value of the C or Z bits. Both sets of flags are cleared by
RESET.

I,·O/LF

Meu

Figure 5. Powerup RESET Delay Circuit

MOTOROLA MICROPROCESSOR DATA
3-302

MC6804J2

INTERRUPT
The MCU can be interrupted by applying a logic low
signal to the IRQ pin. However, a manufacturing mask
option determines whether the falling edge or the actual
low level of the IRQ pin is sensed to indicate an interrupt.

EDGE-SENSITIVE OPTION
When the IRQ pin is pulled low, the internal interrupt
request latch is set. Prior to each instruction fetch, this
interrupt request latch is tested. If its output is low, an
interrupt sequence is initiated at the end of the current
instruction, provided the interrupt mask is cleared. Figure
6 contains a flowchart that illustrates both the reset and
interrupt sequences.
The interrupt sequence consists of one cycle during
which:
The interrupt request latch is cleared;
The interrupt mode flags are selected;
The program counter (PC) is ~a~ed on the stack;
The interrupt mask is set; and

that the vector contents !!pecify a JMP instruction in addition to the starting address of the interrupt service routine. If required, this routine should save the values of
the accumulator and the X and Y registers, since these
values are not stored on the stack.
Internal processing of the interrupt continues until a
return from interrupt (RTIl instruction is processed. During RTI the interrupt mask is cleared and the program
mode flags .are selected. The next instruction of the program is then fetched and executed.
When the interrupt was initially detected and the interruptsequence started, the interrupt request latch was
cleared so thatthe next interrupt could be detected. These
steps occurred even as the first interrupt was being serviced. However, even though the second interrupt edge
set the interrupt request latch during the first interrupt's
processing, the second interrupt's sequence can not begin until completion of the interrupt service routine for
the first interrupt. Completion of an interrupt service routine is always accomplished using an RTI instruction to
return to the main program. The interrupt mask, which
is not directly available to the programmer, is cleared
during the last cycle of the RTI instruction.

The IRQ vector jump address is loaded into the PC.
The IRQ vector jump address is $FFC-$FFD in the singlechip mode and $FF8-$FF9 in the self-check mode. The
contents of these locations are not decoded as an address
to which the PC should jump. Instead, they are decoded
like any other EPROM program word. So, it is essential

LEVEL-SENSITIVE OPTION
Actual operation of the level-sens.itive and edge-sensitive options are similar. However, the level-sensitive
option does not have an interrupt request latch. Since
there is no interrupt request latch, the logic level of the

O-OOR.
l-INTERRUPTMASI<
O-INTERRUPTREOUEST
lATCHIEOGE
SENSITIVE OPTIONI
Iff-TCR
IOO-TSCR
IFf-PRESCAlER

lOW

Figure 6. Reset and Interrupt Flowchart

MOTOROLA MICROPROCESSOR DATA
3-303

II

MC6804J2

IRQ pin is checked to detect the interrupt. Also, in the
interrupt sequence there is no need to clear the interrupt
request latch. These differences are shown in Figure 6.

Maximum interrupt response time is six machine cycles.
This includes five cycles for the longest instruction plus
one for stacking the PC and switching flags.

POWERUP AND TIMING

TIMER

During the powerup sequence, the interrupt mask is
closed. This precludes any false interrupts. The PC is alsO'
loaded with the appropriate restart vector (jump instruction).
To open the interrupt mask, the user should do a JSR
to an initialization subroutine that ends with an RTI instead of an RTS.TheRTI opens,the interrupt mask. Typical RESET and IRQ processes and their relationship to
the in~errupt mask are shown in Figure 7.

A block diagram of the MC6804J2 timer circuitry is
shown in Figure 8. The timer logic in the MCU is comprised of a simple 8-bit counter called the timer counter.
This counter is decremented by a 7-bit prescaler at rate
determined by the timer status/control register (TSCR).

a

PRESCALER
The prescaler is a 7-bit counter used to extend the maximum interval of the overall timer. This counter is clocked

JMp·START
VECTOR (FFE-FFF)

.................................................

II

START (ROUTINE)
INSTRUCTION (I-N)

I

INTERRUPT
MASK
CLOSED

LAST INSTRUCTION
JSR INIT

I

INIT
INITIALIZATION
SUBROUTINE

1
LAST INSTRUCTION
RTI

J

PROGRAM

MASK
OPEN

IRQ
RECOGNIZED

........................
IRQ
SERVICE
ROUTINE

INTERRUPT
MASK
CLOSED

1
LAST INSTRUCTION
RTI

PROGRAM

J

........................

Figure 7; Interrupt Mask

MOTOROLA MICROPROCESSOR DATA
3-304

MASK
OPEN

MICROCOMPUTER INTERNAL BUS
READ

s:
o
-I
o:::tI
o
~

s:

:::tI

o

"tI

W
U'I

8-BIT COUNTER
TIMER
PIN

SELECT
1--------11 '-OF-8

c=;

w

WRITE

READ

0

TIMER STATUS/CONTROL
REGISTER (TSCRI
TMZ

:::tI

o(")

bO

b7

TIMER COUNT REGISTER
(TCRI

WRITE

s:o
0)
(1)

C)

e
N

m

en
en

o:::tI
c

e

TIMER PIN STATUS
TOUT

PRESCALER
CLOCK

TIMER
PIN

TIMER PIN
SYNC

INPUT MODE
OUTPUT MODE

Figure 8. Timer Block Diagram

MC6804J2

by a signal from the TIMER pin or by the internal sync
pulse. It divides the frequency received by some factor
to create the prescaler output. The factor by which the
TIMER pin signal is divided is called the prescaler tap.
The value of this tap is selected by three bits of the TSCR
(PSO-PS2). These bits control the division of the prescaler
input within the range of divide-by-20 , to divide-by-27.

MSB

LSB

RESET:
1

TIMER STATUS/CONTROL REGISTER (TSCR) ($09)
5

TIMER COUNTER

I

The timer counter, which may be read or loade~ under
program control, is decremented from a maximum value
of 256 toward zero by the prescaler output. Both are decremented on rising clock edges.
The prescaler register and timer count register are
readable and writeable. A write to either one will take
precedence over the normal counter function. For example, if a value is written to the timer count register,
and this write and a decrement-to-zero occur at the same
time, the write takes precedence. TSCR bit one (TMZ) is
not set until the next timer time out.
TIMER PIN
The TIMER pin may be programmed as either an input
or an output. Its.status depends on the value of TSCR bit
5 (TOUT). This relationship is shown in the TIMER pin
status section of Figure 8. The frequency of the internal
clock applied to the TIMER pin must be less than tbyte,
which is (fosc/48).
TIMER INPUT MODE

I TMZ I

PSI

PS2

PSl

PSO

o

TMZ -

Timer Zero
1 = Timer count register has decremented to zero
since the last time the TMZ bit was read.
0= This bit is cleared by a read of the TSCR if TMZ
is read as logic one.

Bit 6
Not used by this register.
TOUT - Timer Output
1 = Output mode is selected for the timer.
0= Input mode is selected for the timer.
DOUT - Data Output
Latched data at this bit is sent to the TIMER pin when
_ both the TMZ and TOUT bits are logic high.
PSI - Prescaler Initialization
1 = Prescaler begins to decrement.
0= Prescaler is initialized and counting is inhibited.
PSO-PS2
These bits are used to select the prescaler tap. The
coding of the bits is shown below:

TIMER OUTPUT MODE

NOTE
TMZ is normally set to logic one when TCR decrements to zero and the timer times out. However,
it may be set by a write of $00 to TCR or by a write
to bit 7 of TSCR.

I TOUT I DOUT I

RESET:

In the timer input mode, TOUT is logic zero and the
TIMER pin is connected directly to prescaler input. So,
the prescaler is clocked by the signal from the TIMER pin.
The prescaler divides the TIMER pin clock input by the
prescaler tap. The prescaler output then clocks the 8-bit
timer count register. When this register is decremented
to zero, it sets TSCR bit one (TMZ). This TMZ bit can be
tested under program control to tell when the counter
register has reached zero.

In the output mode, the TIMER pin is output. TOUT is
a logic one. The prescaler is clocked by the internal sync
pulse. This pulse is a divide-by-48 of the internal oscillator
(fosc/48). From this point on, operation is similar to that
described for the input mode. However, in the output
mode, once the prescaler decrements the timer counter
to zero, the high TMZ bit state allows TSCR bit 4 (DOUT)
to become direct input to the TIMER pin.

4

~S2

PS1

PSO

°
°

0

0

1

0

1

2

0

1

0

4

0

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

Divide By

It is recommended that MVI or loading and storing
instructions be used when changing bit values in the
TSCR .. Read-modify-write instructions can cause the TMZ
to assume an unexpected state.
During reset, the TSCR is set to all zeroes; the TIMER
pin is in the high impedance input mode; and DOUT
LATCH is forced to a logic high. At the same time, PSOPS2 coding sets the prescaler tap at divide-by-one, and
bit 3 initializes the prescaler.
TIMER PRESCALER REGISTER (SFD)
The timer prescaler register reflects the current count
ofthe 7-bit prescaler. This register is the prescaler counter
and can be .read or written.
6

TIMER COUNT REGISTER ($FE)
The timer count register reflects the current count in
the internal8-bit counter. The register is the timer counter
and can be read or written.

I MSB
RESET:
1

MOTOROLA MICROPROCESSOR .D,ATA
3-306

LSB

MC6804J2

INSTRUCTION SET

Function

The MCU has a set of 42 basic instructions. They can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

Mnemonic

Decrement XP

DECX

Decrement YP

DECY

BRANCH INSTRUCTIONS

This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list of instructions.

REGISTER/MEMORY INSTRUCTIONS

Most of these instructions use two operands. One operand is the accumulator; the other is obtained from
memory using one of the addressing modes. Refer to the
following list of instructions.

Function

Mnemonic

Branch if Carry Clear

Mnemonic

Function

BCC

Load A from Memory

LDA

Branch if Higher or Same

Load XP from Memory

LDX

Branch if Carry Set

Load YP from Memory

LDY

Branch if Lower

(BLO)

Store A in Memory

STA

Branch if Not Equal

BNE

ADD

Branch if Equal

BEQ

Add to A
Subtract from A

SUB

AND Memory to A

AND

Transfer A to XP

TAX

Transfer A to YP

TAY

Transfer YP to A

TVA

Transfer XP to A

TPA

Clear A

CLRA

Clear XP

CLRX

Clear YP

CLRY

Arithmetic Compare with Memory

CMP

(BHS)
BCS

BIT MANIPULATION INSTRUCTIONS

The MCU is capable of setting or clearing any bit which
resides in the 256 bytes of data space, where all port
registers, port DDRs, timer, timer control, and on-chip
RAM reside. An additional feature allows the softWare to
test and branch on the state of any bit within these 256
locations. The bit set, bit clear, and bit test and branch
functions are all implemented with a single instruction.
For the test and branch instructions, the value of the bit
tested is also placed in the carry bit of the condition code
register. Refer to the following list of instructions.

MVI

Move Immediate Value to Memory

Function

ASLA

Arithmetic Left Shift of A

COMA

Cbmplement A
..

ROLA

Rotate A Left and Carry

Mnemonic

Branch If Bit n is Set

BRSET n(n = 0 ... 7)

Branch If Bit n is Clear

BRCLR n(n=O ... 7)

Set Bit n

BSET n(n=O ... 7)

Clear Bit n

BCLR n(n =0 ... 7)

READ-MODIFY-WRITE INSTRUCTIONS

These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. All INC and DEC
forms along with all bit manipulation instructions use this
method. Refer to the following list of instructions.
Function

Increment Memory Location

Mnemonic

CONTROL INSTRUCTIONS

These instructions are used to control processor operation during program execution. The jump conditional
(JMP) and jump to subroutine (JSR) instructions have no
register operand. Refer to the following list of instructions.

INC

Function

Mnemonic

Increment A

INCA

Return from Subroutine

Increment XP

INCX

Return from Interrupt

RTI

Increment YP

INCY

No Operation

NOP

DEC

Jump to Subroutine

JSR

DECA

Jump Unconditional

JMP

Decre~ent

Memory Location

Decrement A

MOTOROLA MICROPROCESSOR DATA
3-307

RTS

II

MC6804J2

IMPLIED INSTRUCTIONS
Since the accumulator and all other registers are located in RAM, many implied instructions exist. Some of
the instructions recognized and translated by the assembler are shown below:
Mnemonic

I

Becomes

Mnemonic

addressing mode is used to access constants that do not
change during program execution, such as a constant
used to initialize a loop counter.
DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the 256 bytes of data space with a single twobyte instruction.

Becomes

ASLA

ADD $FF

INCX

INC $80

BHS

BCC

INCY

INC $81

BlO

BCS

LOXI

MVI $80 DATA

ClRA

SUB $FF

lDYI

MVI $81 DATA

SHORT DIRECT

ClRX

MVI $80 #0

NOP

BEQ (PC) +1

ClRY

MVI $81 #0

TAX

STA $80

In the short direct addressing mode, the MCU has four
locations in data space RAM it can use, ($80, $81, $82,
and $83). The opcode determines the data space RAM
location, and the instruction is only one byte. Short direct
addressing is a subset of the direct addressing mode.
The X and Y registers are at locations $80 and $81, respectively.

DECA

DEC $FF

TAY

STA $81

DECX

DEC $80

TXA

LOA $80

DECY

DEC $81

TVA

LOA $81

INCA

INC $FF

EXTENDED
Some examples of valuable instructions not specifically recognized by the assembler are shown below:
Mnemonic

Meaning

BClR 7,$FF

Ensures A is plus

BSET 7, $FF

Ensures A is minus

BRClR 7, $FF

Branch if A is plus

BRSET 7, $FF

Branch if A is minus

BRClR 7, $80

Branch if X is plus (BXPl)

BRSET 7, $80

Branch if X is minus (BXMI)

BRClR 7, $81

Branch if Y is plus (BYPl)

BRSET 7, $81

Branch if Y is minus (BYMI)

In the extended addressing mode, the effective address
of the argument is obtained by concatenating the four
least-significant bits ofthe opcode with the byte following
the opcode to form a 12-bit address. Instructions using
the extended addressing mode, such as JMP or JSR, are
capable of branching anywhere in program space. An
extended addressing mode instruction is two bytes long.
RELATIVE

OPCODE MAP
Table 1 is a listing of all the instruction set opcodes
applicable to the MC6804J2 MCU.

The relative addressing mode is only used in conditional branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following tbe
opcode is added to the PC if, and only if, the branch
conditions are true. Otherwise, control proceeds to the
next instruction. The span of relative addressing is from
-15 to + 16 from the opcode address. The programmer
need not calculate the offset when using the Motorola
assembler, since it calculates the proper offset and checks
to see that it is within the span of the branch.
BIT SET/CLEAR

ADDRESSING MODES
The MCU has nine different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. It deals with objects in three different address spaces: program space, data space, and
stack space. The term "effective address" (EA) is used in
describing the various addressing· modes. Effective address is defined as the address from which the argument
for an instruction is fetched or stored.
IMMEDIATE
In the immediate addressing mode, the operand is located in program ROM. It is contained in the byte immediately following the opcode. The immediate

In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte in which
the specified bit is to be set or Cleared. Thus, any bit in
the 256 locations of data space memory that can be written to can be set or cleared with a single two-byte instruction.
CAUTION
The corresponding DDRs for ports A and B are write
only registers (registers at $04 and $05). A read
operation on these registers is undefined. Since
BSET and BClR are read~modify-write functions,
they cannot be used to set or clear aDDR bit; all
"unaffected" bits would be set. Write all DDR bits
in a port using a single-store instruction.

MOTOROLA MICROPROCESSOR DATA
3-308

Table 1. Opcode Map

Register/Memory, Control, and
Read/ Modify/Write Instructions

Branch InstructIons

~
BEG

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

. BEG

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

BEG

BEG

BCC.

BCC

BCS

BCS

JSRn

3:

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JSRn

o:::D
o

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JSRn

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

3:

n
:::D

w o"'0

:xl

oo

m

A

en
en

o

:xl

C

~

D

Bit Manipulation
Instructions

Hi
BRCLRO

BCLRO

LDA

LDA

BRCLRl

BCLRl

STA

STA

RTI

BRCLR2

BCLR2

ADD

ADD

JMPn

RTS

BRCLR3

BCLR3

SUB

SUB

JMPn

COMA

I

BRCLR4

I

BCLR4

CMP

CMP

ROLA

I

BRCLR5

I

BCLR5

AND

AND

JMPn

BRCLR6

I

BCLR6

INC

INC

JSRn

JMPn

BRCLR7

I

BCLR7

DEC

DEC

JMPn

LDA

LDA

MVI

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JSRn

INC

DEC

I

BRSETO

I

BSETO

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

INC

DEC

I

BRSET1

I

BSET1

BNE

BNE

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

INC

DEC

I

BRSET2

I

BSET2

ADD

ADD

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

INC

DEC

I

BRSET3

I

BSET3

SUB

SUB

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

LDA

STA

I

BRSET4

I

BSET4

CMP

CMP

BNE

BNE

BEG

BEG

BCC

BCC

Bes

BCS

JSRn

JMPn

LDA

STA

I'

BRSET5

I

BSET5

AND

AND

BEG

RELI,

5 D

13

B TB

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JRSn

JMPn

LDA

STA

BRSET6

BNE

BNE

BEG

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

LOA

STA

BRSED

Abbreviations for Address Modes

INH
SoD
B- T·B
IMM
DIR
EXT
REL
BSC
R-INC

Register/Memory and
Readl MOdify I Write

A

~

~
BNE

!;

~

T

BNE

~

Co.)

9

Inherent
Short Direct
Bit Test and Branch
Immediate
Direct
Extended
Relative
Bit Set/Clear
Register Indirect

s:
(")
en
CO

STA

A

D

2

BSET6

iNC

BSED

DEC

LEGEND
Indicates Instruction Reserved for Future Use
Indicates Illegal Instruction

,,,,~~.

Mne~~~~~

1 •

LDA ..

d~
~ ~

Opcode in Binary

e
N

MC6804J2

BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear) is
included in theopcode. The data space address of the
byte to be tested is in the single byte immediately following the opcode byte. The third byte is sign extended
to twelve bits and becomes the offset added to the PC if
the condition is true. This single three-byte instruction
allows the program to branch based on the condition of
any readable bit in the 256 locations of data space. The
span of branching is from -125 to + 130 from the opcode
address. The state of the tested bit is also transferred to
the carry flag.

REGISTER-INDIRECT
In the register-indirect addressing mode, the operand
is at the address in data space pointed to by the contents
of one of the indirect registers, X or Y. The particular
indirect register is selected by bit 4 of the opcode. Bit 4
decodes into an address that represents the register, $80
or $81. A register-indirect instruction is one byte long.

INHERENT
In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. These instructions are one byte long.

ELECTRICAL SPECIFICATIONS

I

MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

Rating

VCC

-0.3 to +7.0

V

Input Voltage

Vin

-0.3 to +7.0

V

Operating Temperature Range (Comm.)

TA

o to 70

°C

Operating Temperature Range (Ind.)

TA

-40 to +85

°c

TSllL

-55 to + 150

°C

TJ

150

°c

Storage Temperature Range
Junction Temperature

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum-rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ~ (Vin or Vout) ~ Vce·
Reliability of operation is enhanced if unused inputs except EXTAL are connected to an appropriate logic voltage level (e.g., either VSS or Vee).

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can
be obtained from:
TJ=TA+(PD o6JA)
(1)
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance,
6JA
Junction-to-Ambient, °CIW
PD
= PINT+PPORT
= ICCxVCC' Watts - Chip Internal Power
PINT
PpORT = Port Power Dissipation,
Watts - User Determined

For most applications PPORT21'-___....
(b)

 1

- SYNC TIMING

11>1

SYNC

.

r---1

~

I~

___________________________I
I
IL
Figure 12. Clock Generator Timing Diagram

MOTOROLA MICROPROCESSOR DATA
3-311

II

MC6804J2

PORT DC ELECTRICAL CHARACTERISTICS
(VCC= +5.0 Vdc±0.5 Vdc, VSS=GND, TA=O°C to 70°C, unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

-

0.5

V

Ports A and Timer (Standard)
Output Low Voltage, ILoad = 0.4 rnA

VOL

-

Output High Voltage, ILoad = - 50 fJ-A

VOH

2.3

Input High Voltage

VIH

2.0

Input Low Voltage

VIL

-0.3

Hi-Z State Input Current

ITSI

-

V

VCC

V

0.8

V

-

4

40

tJ-A

Port A (Open Drain)
Output Low Voltage, ILoad = 0.4 rnA

VOL

-

V

VIH

2.0

-

0.5

Input High Voltage

VCC

V

Input Low Voltage

VIL

-0.3

'-

0.8

V

Hi-Z State Input Current

ITSI

-

4

40

fJ-A

ILOD

-

4

40

fLA

Open Drain Leakage (Vout=VCc!

II

Port A (CMOS Drive)
Output Low Voltage ILoad = 0.4 rnA (Sink)

VOL

-

-

0.5

V

Output High Voltage, ILoad = -10 fJ-A

VOH

VCC-1.0

-

-

V

Output High Voltage, ILoad = - 50 fJ-A

VOH

2.3

-

V

Input High Voltage, ILoad = - 300 fJ-A Max

VIH

2.0

-

VCC

V

Input Low Voltage, ILoad = - 300 fJ-A Max

VIL

-0.3

-

0.8

V

-

-300

fJ- A

Hi-Z State Input Current (Vin = 0.4 V to VCC)

ITSI

-

Port B (Standard)
Output Low Voltage, ILoad = 1.0 rnA

VOL

-

-

0.5

V

Output Low VoltageAoad = 10 rnA (Sink)

VOL

-

-

1.5

V

Output High Voltage, ILoad = -100 fJ-A

VOH

2.3

-

-

V

Input High Voltage

VIH

2.0

-

VCC

V

Input Low Vo'itage

VIL

-0.3

-

0.8

V

-

8

80

fLA

V

Hi-Z State Input Current

ITSI
Port B (Open Drain)

Output Low Voltage, ILoad = 1.0 rnA

VOL

-

VOL

-

-

0.5

Output Low Voltage, ILoad = 10 rnA (Sink)

1.5

V

Input High Voltage

VIH

2.0

-

VCC

V

Input Low Voltage

VIL

-0.3

-

0.8

V

Hi-Z State Input Current

ITSI

-

8

80

fLA

ILOD

-

8

80

fJ-A

Open Drain Leakage (Vout=VCC)

Port B (CMOS Drive)
Output Low Voltage, ILoad = 1.0 rnA

VOL

-

-

0.5

V

Output High Voltage, ILoad = 10 rnA (Sink)

VOL

-

1.5

V

-

V

-

V

VCC

V

Output High Voltage, ILoad = - 10 fJ-A

VOH

VCC- 1.O

Output High Voltage, ILoad = -100 IJ.A

VOH

2.3

Input High Voltage, ILoad = - 300 IJ.A Max

VIH

2.0

-

Input Low Voltage, ILoad = - 300 fJ-A Max

VIL

-0.3

-

0.8

V

Hi-Z State Input Current (Vin = 0.4 V to VCC)

ITSI

-

-300

fJ- A

-

100

fJ-A

-4.0

fJ- A

-

Ports A and B (Low Current Clamping Diode*)
Input High Current VIH = VCC + 1.0 V

IIH

-

Input Low Current VIL = 0.8 V

IlL

-

*Denotes not tested unless specified on ordering form.

MOTOROLA MICROPROCESSOR DATA

3-312

MC6804J2

4.0 r---r--r-L-.l"---~-TL---'----r---.

1 3.5 !--+-_EXPECTED

M~X4~~5CV

...

""=~
<->

ie

3.0
2.5

// /

1.5

~

1.0

~

~500~

./

•••••••••

'./.,
~/./
/,/
••••

,

.......

.... ..

•• '

MIN4.5V
85°C . -

1...
~

S

100

-200

I
II

~

.....

~

r/'
,

f

II.

-300

(0.5 V. JOO I'A) -

-400
2.0

2.5
3.0
3.5
4.0
VOH. HIGH·LEVEL OUTPUT VOLTAGE (V)

Figure 13. Typical VOL vs IOL
for Port A and TIMER

-501'; •••••••

-100

iE~PECTEO

...=
g -200

i MIN 4.5 V

<>.

85°C

....... ~ _.....
V
/
~

-300

10

.....

.. 9

..s

EXPECTED I

;; 8 f---

I

,

g= 5
u:j

4

1

$;I:

3

-M~X4~~5C~'
1/

<>.

I

9 2

~1

/

;'

;

L
I

:

(2.3 V. -100 I'A)

~

: EXPECTED
: MIN 4.5 V

g~ -200

f

~

-300

85°C

iI

2.0

2.5

I

l

1-

"

TYPICALEXPECTED
~ MAX 5.5 V
5.0 V
-40°C
25°C -

-!
I

10.5 V. l rnA) ~

l

200
300
400
VOL. LOW·LEVEL OUTPUT VOLTAGE (mV)

3.0
3.5
4.0
VOH. HIGH·LEVEL OUTPUT VOLTAGE (V)

4.5

X=SPEC PT.

(2.3 v.
100 r-X

....

- 100 I'A)

500

~ -200

r----,

I]

I
I
I

~ -400
2.0

2.5

I'

:MIN 4.5 V,i
85°C

x
~

-500

/

i

~ -300

5,0

........ ....t,... i-"' ::L....{ .....

: EXPE1CTEDL. , TYPI~AL

u:j

,!
,

I

~
-400

II

EXPECTED
MIN 4.5 V
85°C

Figure 16. Typical VOL vs IOL for Port B

ffi -100 - X

~

..

'

.'

X= SPEC PT,

Figure 15. Typical VOH vs IOH
for Port A with CMOS Pullups

x

'

....
.'

/

100

X=SPEC PT.

0-

..
.'

'

..'

VOH. HIGH-LEVEL OUTPUT VOLTAGE (V)

..:;

V

....

..
.'

~.,

2

..

/
'

II'/. ....

/

,'TYPICAL
5.0 V
25°~

,.I' V./..' .. .'

0-

,!

~
-400

~

TYPICAL
EXPECTED
5.0 V
, MAX 5.5 V
25°C, -40°C

~

x

5.0

Figure 14. Typical VOH vs IOH
for Port A and TIMER

--i

I

u:j
~

ill

4.5

X= SPEC PT.

X=SPEC PT.

i

MAX 5.5 V
-40°C

I

VOL. LOW·LEVEL OUTPUT VOLTAGE (mV)

~~

H~XPEJTED
-+
,
/
:

~

~

0.0 0~--:-10~0--::2~00:---::3~00:---4:":0-=-0~5~0-=-0-6:-':0-=-0-:-':70-=-0--:-'800

l...

TYPICJL5.0 V
25°C -

fEJPECTlD: MIN 4.5 V
85°C -

u:j

~~

~ 0.5

i

t;;

V•••••'
E~~ECTED_

~

,/

g 2.0
~

,

V

(2.3 V. - 50 I'A)
,.--- X

TYPICAL+--_I----i

5.0 V
25°C

,
,:

EXP~CTEb

- f--MAX 5.5 V_ "'-40°C

3.0
3.5
4.0
4.5
VOH. HIGH·LEVEL OUTPUT VOLTAGE (V)

X= SPEC PT.

Figure 17. Typical VOH vs IOH for Port B

Figure 18. Typical VOH vs IOH
for Port B with CMOS Pullups

MOTOROLA MICROPROCESSOR DATA

3-313

5.0

5.5

MC6804J2

ORDERING INFORMATION
customer program using positive logic sense for address
and data. Submissions on two EPROMs must be clearly
marked. All unused bytes, including. the user's space,
must be set to zero.
If the MC6804J2 MCU ROM pattern is submitted on
one 2532 or 2732 EPROM, or on two 2516 or 2716 type
EPROMs, memory map addressing is one-for-one. The
data space ROM runs from EPROM address $018 to $05F
and program space ROM runs from EPROM address $C1 0
to $FF7, with vectors from $FFC to $FFF.
For shipment to Motorola, EPROMs should be placed
in a conductive IC carrier and packed securely. Styrofoam
is not acceptable for shipment.

The following information is required when ordering a
custom MCU. The information may be transmitted to Motorola using the following media:
MDOS<®, disk file
MS@)-DOS/PC-DOS disk file (360K)
EPROM(s) 2516, 2716, 2532, 2732
To initiate a ROM pattern for the MCU, it is necessary
to first contact the local field service office, sales person,
or Motorola representative.
FLEXIBLE DISKS

I

Several types of flexible disks (MOOS or MS-DOS/PCDOS disk file) may be submitted for pattern generation.
They should be programmed with the customer program,
using positive logic sense for address and data. The diskette should be clearly labeled with the customer's name,
date, project or product name, and the filename containing the pattern.
In addition to the program pattern, a file containing the
program source code listing can be included. This data
will be kept confidential and used to expedite the process
in case of any difficulty with the pattern file.

Verification Media

MOOS Disk File

MDOS is Motorola's Disk Operating System available
on the EXORciser® development system. The disk media
submitted must be a single-sided, single-density, 8-inch
MDOS compatible floppy diskette. The diskette must contain the minimum set of MDOS system files in addition
to the pattern file.
The .LO output of the M6804 cross assembler should
be furnished. In addition, the file must be produced using
the ROLLOUT command; so that it contains the absolute
image of the M6804 memory. It is necessary to include
the entire memory image of both program and data space.
All unused bytes, including those in the user space, must
be set to logic zero.

All original pattern media, EPROMs or floppy disks, are
filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and
returned along with a listing verification form. The listing
should be thoroughly checked and the verification form
should be completed, signed, and returned to Motorola.
The signed verification form constitutes the contractual
agreement for the creation of the customer mask. To aid
in the verification process, Motorola will program customer supplied blank EPROM(s) or DOS disks from the
data file used to create the custom mask.
ROM Verification Units (RVUs)
Ten MCUs containing the customers ROM pattern will
be sent for program verification. These units will have
been made using the custom mask, but are for the purpose of ROM verification only. For expediency, the MCUs
are unmarked, packaged in ceramic, and tested with five
volts at room temperature. These RVUs are free with the
minimum order quantity, but are not production parts.
These RVUs are not guaranteed by Motorola Quality Assurance.

MS-DOS/PC-DOS Disk File

MS-DOS is Microsoft's Disk Operating System. PC-DOS
is IBM® Personal Computer Disk Operating System. Disk
media submitted must be standard density (360K), double-sided 5 1/4 inch compatible floppy diskette. The diskette must contain the object file code in Motorola's Srecord format. The S~record format is a character-based
object file format generated by M6804 cross assemblers
and linkers on IBM PC style machines.

Ordering Information
The following table provides generic information pertaining to the package type and temperature for the
MC6804J2. This MCU device is available only in the 20pin plastic dual-in-line(DIP) package.

EPROMS
Four K of EPROM are necessary to contain the entire
MC6804J2 program. Two 2516 or 2716 type EPROMs or
a single 2532 or 2732 type EPROM can be submitted for
pattern generation. The EPROM is programmed with the

Generic Information
Package Type
Plastic
(P Suffix;

MOOS is a trademark of Motorola Inc.
MS·DOS is a trademark of Microsoft, Inc.
EXORciser is a registered trademark of Motorola Inc.
IBM is a registered trademark of International Business Machines Corporation.

MOTOROLA MICROPROCESSOR DATA

3..314

Temperature
O°C to 70°C
.:. . 40°C to + 85°C

Order Number
MC6804J2P
MC6804J2CP

MC6804J2

MECHANICAL DATA

PIN ASSIGNMENTS

Vss

RESET
PA7
PA6
PAS
PA4
PB7
PB6

PBO

PBS

PB1

PB4

PB2

MOTOROLA MICROPROCESSOR DATA

3-315

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC6804P2

Technical Summary

8-Bit Microcontroller Unit

II

MC6804P2 HMOS (high-density NMOS) microcontroller unit (MCU) is a member of the M6804
Family of serial processing microcontrollers. This device is extremely versatile and cost effective
based on the MCU's simple design and its ability to process 8-bit variables, one bit at a time.
This technical summary contains limited information on the MC6804P2. For detailed information,
refer to the advanced information data sheet for the MC6804J 1, MC6804J2, MC6804P2 and
MC68704P2 8-bit microcontrollers (MC6804 J1/D) or to the M6804 MeV Manual (DLE404/D).
Major hardware and software features of the MC6804P2 MCU are:
• On-Chip Clock Generator
• True Bit Manipulation
• Bit Test and Branch Instruction
• Memory Mapped 110
• 288 Bytes Self-Check ROM
• Software Programmable 8-Bit Timer with
7-Bit Prescaler
• Conditional Branches
• Single Instruction Memory Examine/
• Timer Pin is Software Programmable as
Change
Clock Input or Timer Output
• 1016 Bytes of User Program ROM
• 30 Bytes of RAM
• User Selectable Constant Current Pullup Devices available on LSTTL and Open-Drain Interface
Ports
• Mask Selectable Edge- or Level-Sensitive Interrupt Pin

BLOCK DIAGRAM
TIMER

ACCUMULATOR
A

PORT
A
I/O
LINES

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

CPU
CONTROL

INDIRECT
REGISTER

PORT
A
REG.

OATA
DlR.
REG.

INDIRECT
REGISTER

PBO
PBl
PB2 PORT
B
PB3
PB4 I/O
PB5 LINES
PB6
PB7

CPU

STACK

l016x 8
USER PROGRAM ROM
288x8
SELF-CHECK ROM

PROGRAM
COUNTER
HIGH PCH
PROGRAM
COUNTER
PCl
lOW

AlU

MOTOROLA MICROPROCESSOR DATA
3-316

PCO PORT
C
PCl
PC2 I/O
PC3 LINES

MC6804P2

SIGNAL DESCRIPTION
VCC AND VSS
Power is supplied to the microcontroller using these
two pins; Vee is + 5 volts (± 0.5 V) power, and VSS is
ground.
IRQ
This pin provides the capability for asynchronously applying an external interrupt to the microcontroller.

EXTAL AND XTAL
These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal is connected to these pins
to provide a system clock. Selection is made by a manufacturing mask option. The different clock generator options are shown in Figure 1, along with crystal
specifications.
Internal Clock Options

The crystal oscillator start-up time is a function of many
variables. To ensure rapid oscillator start-up, neither the
crystal characteristics nor load capacitances should exceed recommendations. When using the on~board oscillator, the MeU should remain in reset condition, with
the RESET pin voltage below VIRES +, until the oscillator
has stabilized at its operating frequency. See Figure 2 for
resistor/capacitor oscillator options.

a

TIMER
The TIMER pin can be configured to operate in either
the input or output mode. As input, this pin is connected
to the prescaler input and serves as the timer clock. As
output, the timer pin reflects the contents of the DOUT
bit of the timer status/control register, the last time the
TMZ bit was logic high.
RESET
The RESET pin is used to restart the processor to the
beginning of a program. The program counter is loaded
with the address of the restart vector. This should be a
jump instruction to the first instruction of the main program. Together with the MDS pin, the RESET pin selects
the operating mode of the Meu.
MDS
The mode select (MDS) pin places the MeU into special
operating modes. When this pin is logic high at the exit
of the reset state, the decoded state of PA6 and PA7 is
latched to determine the operating mode. This choice can
be either the single-chip, self-check, or ROM-verify mode.
However, if MDS is 'logic low at the end of the reset state,
the single-chip operating mode is automatically selected.
No external diodes, switches, transistors, etc. are required for single-chip mode selection.
INPUT/OUTPUT LINES (PAO·PA7, PBO·PB7, PCO·PC3)
These 20 lines are arranged into two 8-bit ports (A and
B) and one 4~bit port (e). All lines are programmable as

+5V
NC
EXTERNAL
CLOCK
INPUT

EXTAL
XTAL

4.7 k

MCU
ICRYSTA.L MASK
OPTIONI

EXTAL
XTAL

MCU
IRESISTORCAPACITOR MASK
OPTION)

1* OENOTES NCIGND. GROUNDING
PIN 4 WILL REDUCE RFI NOISE.!

EXTERNAL CLOCK

EXTERNAL RESISTOR·CAPACITOR

Gt:=r",e,

CRYSTAL PARAMETERS

U""

lal

.C,

o

CRYSTAL PARAMETERS
AT - OUT PARALlEl RESONANCE CRYSTAL
Co = 7 pF MAXIMUM
FREO. = " MHz
RS = 50 OHMS MAXIMUM

XTAL
EXTAL

PIEZOELECTRIC CERAMIC RESONATORS MAY BE
SUBSTITUTED FOR THE CRYSTAl. FOLLOW
MANUFACTURER'S CERAMIC
RESONATOR
SPECIFICATIONS.

MCU
ICRYSTAL MASK
OPTION I

CRYSTAL

NOTE: Keep crystal leads and circuit connections as short as possible

Figure 1. Clock Generator Options and Crystal Parameters

MOTOROLA MICROPROCESSOR DATA
3-317

'

3

MC6804P2

8.2 ,----,--,---r--r---r----,---r--r---,.--,

25r---.-~~~---r--~1~~1--~--~

'1\

-

15pFAT
- - - 22 pF AT
\
•••••••• ~ 27 pF AT
~.~rl,o:-If---+--+---I ._.-36 pF AT
15 ~.~ "".
' ••_ •••••• 50 pF AT

-

i.
~

~

~ 10
"':

-

'\.·~.,I'

1\", ·I~=, ...
'\...

~

'!" •••• ""

'.",

8.0 I--+-+----l'---+-+--+-+--,I--~-+:
.....
~

25°C 1 25°C 1-,-25°C
25°C 1-'-25°C 1 _

20
•

1-'--+.......-+---+_+--:--+_~0111!!-;::j.....o-:..--+-_+-,---.j

i~

...

t..,......--~

.... 7.4~
=
7.2 ~~-_+_---I-'l.IjOC

r-.....

' ..:: .: . .:;:: ~."'::.-:- ~:-I--...

..:

7.0

.:.:::::~':::.:': ::";';0: .~:o:::

.-.......:

14
10
12
RL. LOAO RESISTANCE (kOI'

16

-

...

--~-

...... .~~~.~t-..~......-1l..~

6.B
4.5

18

"

4.6

4.7

4.8

......

5.3

5.4

(bl TYPICAL FREQUENCY VARIATIONS @CL = 15pF. 10 kO

~~-_+_-_+_-+--+--~'__-+-_+_--

9.6

+-_4--+--+--+--+-_41----+--+-..-..-..-+.-:~.....~

f---

9'.4 +-_4--+--+--+--+--'--+--..,..;I.a!~"-"+--~-~

~

9.2

ffi

9.0

t.QOC

+--+----'-+--+"' ~..". : .. , .--

•••

•••••••••••• iljoc _~_"'T'

•••.

fE
••••••
,_ 8.8 _,'"

.............

4.9
5.0
5.1
5.2
VCC. SUPPLY VOLTAGE (VI

9.8

15

... --"""-

•••'• •+----'-+---.-If----+----1

~

'~

10-_
_ ... - -

B.8 h~~··:.-··+--+-_+--+--+--+-+__4~~

(al TYPICAL FREQUENCY VS RESISTANCE

I

_t.Q;;:....~,..

~ 7.6 ~~--+-I-~"'~;..=- -"F_-+-_4-_+---'--+--+--I

·.:"- .... 1 ..........

........, .:::::.;:

7.8

~

_:...- '"

f···

_I-o--Io-~"

",_ .. ,
' ___ -.-.-

'Slj°.s..~~

_~

'" t..--"-8.6 bl""""~~==-+--f----+--+--+--+--+-_4--I
8.4 L--.....J_-.l.._......L..._...L....._~---.J"------L_~_.....I-------I
4.5
4.6 4.7
4.8 4.9
5.0
5.1
5.2
5.3
5.4
5.5
Vce. SUPPLY VOLTAGE (VI

(el TYPICAL FREQUENCY VARIATIONS @ CL = 50 pF. 3 kO

Figure 2. Typical Frequency Selection for
Resistor/Capacitor Oscillator Options
either inputs or outputs under software control of the
data direction registers.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
There are 20 input/output pins. All pins of each port
are programmable as inputs or outputs under the control
of the data direction registers (DDR).
The port I/O programming is accomplished by writing
the corresponding bit in the port DDR to a logic one for
output, or a logic zero for input, as shown in Figure 3.
When the registers are programmed as outputs, the
latched data is readable regardless of the logic levels at
the output pin due to output loading.
All the I/O pins are LSTTL compatible as both inputs
and outputs. In addition, all three ports may use either
or both of two manufacturing mask options; open drain
output, or internal pull-up resistor for CMOS compatibility.
Any write to a port writes to all of its data bits even
though the port DDR may beset to input. This ca,n be

used as it tool to initialize the data registers and avoid
undefined outputs. However, care must be exercised when
using read-modify-write instructions. The data read corresponds to the pin level if the DDR is an input or to the
latched output data when the DDR is an output.
The 20 bidirectional lines may be configured by port
to be the standard configuration (LSTTL), or either mask
option; LSTTUCMOS, or open drain. Port B outputs are
LED compatible. "
Port Data Registers ($00, $01, $02)
The port data registers are not initialized on reset. These
registers should be initialized before changing the DDR
bits to avoid undefined levels.
Port A ($00) and fort B ($01)
5

3

Port C ($02)

x

x,

x

MOTOROLA MICROPROCESSOR DATA

3-31.8

x

2

5.5

MC6804P2

Vec

r---- .,I

DATA

I
I

DIRECTION REGISTER
BIT

I
IL __ _

en

~~
2 I-

I
I

I

I

-'r----.

a:U
w w

1-2
22
-

BIT

0

U

DATA
DIRECTION
REGISTER
BIT

OUTPUT
DATA
BIT

1
1
0

0
1
X

OUTPUT
STATE
0
1

HI-Z

II

INPUT
TO
MCU
0
1
PIN

*For eMOS option transistor acts as resistor (approximately 40 kO) to VeeFor LSTTLlopen-drain options transistor acts as low current clamping diode to Vee-

Figure 3. Typical 1/0 Port Circuitry

With regard to Port C only, the four MSB bits are unused. These bits are "don't care" (X) bits when written
to but are always logic high when read.
Port Data Direction Registers ($04, $05, $06)
Port DDRs configure the port pins as either outputs or
inputs. Each port pin can be programmed individually to
be an input or an output. A zero in the pin's corresponding
DDR bit programs it as an input; a logic one programs it
as an output. On reset, all the DDRs are initialized to a
logic zero state to put the ports in the input mode.
Port A ($04) and Port B ($05)

Port C ($06)

x

x

x

x

With regard to Port C only, the four MSB bits are unused. These bits are "don't care" (X) bits when written
to but are always logic high when read.

MEMORY
The MCU memory map (Figure 4) consists of 4352 bytes
of addressable memory, I/O register locations, and four
levels ofstack space. This MCU has three separate memory spaces: program space, data space, and stack space.
The MCU is capable of addressing 4096 bytes of program space memory with its program counter and 256
bytes of data space memory with its instructions. Program space memory includes self-check ROM, program
ROM, self-check and user program vectors, and reserved
memory locations.
.
A non-accessible subroutine stack space RAM is provided. This stack space consists of alast-in-first-out (LIFO)
register. This register is used with inherent addressing
to stack the return address for subroutines and interrupts.
Indirect X and Y register locations $80 and $81 are
generally used as pointers for such tasks as indirect addressing to data space locations. Short direct addressing
allows access to the four data space addresses $80-$83
with single byte opcodes. The operations allowed are
increment, decrement, load, and store. Data space locations $82 and $83 can be used for 8-bit counter locations.

MOTORQLA MICROPROCESSOR DATA

3-319

MC6804P2

BYTES

ADDRESS

0000

$000

......

PORT A DATA REGISTER

$00

001

PORT B DATA REGISTER

$01

002

PORT C DATA REGISTER

$02

003

RESERVED

$03

004

PORT A DDR

$04

005

PORT BOOR

$05

006

PORT C ODR

$06

008

RESERVED
(2 BYTESI

$07

009

TIMER STATUS CONT. REG.

""i'"

2783

$ADF

2784

$AEO

:,'"

I

RESERVED
(2784 BYTESI

000

SELF-CHECK ROM
(288 BYTES I

007

~~
$BFF

031

3072

$COO

032

095

;:;:-

PROGRAM ROM
(1016 BYTESI

096

;::~

127

..

$80

129

INDIRECT REGISTER Y

$81

130

$FF7

4088

159

$FF9

160

4090
4091
4092
4093
4094
4095

SELF-CHECK
RESTART VECTOR
USER
IRQ VECTOR
USER
RESTART VECTOR

RESERVED
(14 BYTESI
$17
~----------------~
$18
USER DATA SPACE ROM
(72 BYTESI
$5F
~----------------~
RESERVED
$60
~
' .... ,$7F
(32 BYTESI
INDIRECT REGISTER X

$FF8

SELF-CHECK
IRQ VECTOR

$OA
.

128

4087

4089

$09

... "'

010 ... ",

3071

$08

$FFA

$82

~':

USER DATA SPACE RAM
(30 BYTESI

;,~

:~

RESERVED
(93 BYTESI

;::~

$9F
$AO

HFB

252

$FC

mc

253

PRESCALER REGISTER

$FO

254

TIMER COUNT REGISTER

$FE

255

ACCUMULATOR

$FF

$FFD
$FFE
$FFF

PROGRAM SPACE

DATA SPACE

STACK .SPACE
LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4
(LIFO)

Figure 4. Memory Map

MOTOROLA MICROPROCESSOR DATA
3-320

MC6804P2

STACK

REGISTERS
ACCUMULATOR (A)

The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.
7

I

A

INDIRECT REGISTERS (X,V)

These two registers are used to maintain pointers to
other memory locations in data space. They are used in
the register-indirect addressing mode and can be accessed with the direct, indirect, short direct, or bit setl
clear modes.

A last-in-first-out (LIFO) stack is incorporated in the MCU
that eliminates the need for a stack pointer. This nonaccessible subroutine stack space is implemented in separate RAM, 12-bits wide. Whenever a subroutine call or
interrupt occurs, the contents of the PC are shifted into
the top register of the stack. At the same time, the top
register is shifted one level deeper. This happens to all
registers, with the bottom register falling out of the stack.
Whenever a return from subroutine or interrupt occurs,
the top register is shifted into the PC and all lower registers are shifted one level higher. The stack RAM is four
levels deep. If the stack is pulled more than four times
with no pushes, then the address that was stored in the
bottom level of the stack is shifted into the PC.

SELF CHECK

7

x

y

PROGRAM COUNTER (PC)

The program counter is a 12-bit register that contains
the address of the next byte to be fetched. The program
counter is contained in low byte (PCl) and high nibble
(PCH) . .
8 7

11
PCH

The MCU implements two forms of internal check: self
check and ROM verify. Self check performs an extensive
functional check of the MCU using a signature analysis
technique. ROM verify uses a similar method to check
the contents of program ROM.
Self-check mode is selected by holding the MDS and
PA7 pins logic high and the PA6 pin logic low as RESET
goes low to high. ROM verify mode is entered by holding
MDS, PA7, and PA6 logic high as RESET* goes low to
high. Unimplemented program space ROM locations are
also tested. Monitoring the self-check mode's stages for
successful completion requires external circuitry, see
M6804 MeV Manual (DlE404/D).

PCl

RESET
FLAGS (C,Z)

RESET

The first flag, the carry (C) bit, is set on a carry or borrow
out of the arithmetic logic unit (AlU). It is cleared if the
arithmetic operation does not result in a carry or borrow.
The C bit is also set to the value of the bit tested in a bit
test instruction. It participates in the rotate left (ROlA)
instruction, as well.
The second flag, the zero (Z) bit, is set if the result of
the last arithmetic or logic operation was equal to zero.
Otherwise, it is cleared. Bit test instructions do not affect
the Z bit.

All resets of the MC6804P2 are caused by the external
reset input (RESET). A reset can be achieved by pulling
the RESET pin to logic low for a minimum of 96 oscillator
cycles.
During reset, a delay of 96 oscillator cycles is needed
before allowing the RESET input to go high. If power is
being applied, RESET must be held low long enough for
the oscillator to stabilize and then provide the 96 clocks.
Connecting a capacitor and resistor to the RESET input,
as shown in Figure 5 below typically provides sufficient
delay.
+5V

_ _~N.:..:O~R~M:....::Al:...;F-=LA~G:..:S_ _ _-i.~1

C

z

_ _~I.:.:.NT.:...:E::.::RR~U:..:...PT.:....;..:FLA:...;.::.;GS:""-_--l.~1

C

z

4.7 k

28

There are two sets ofthese flags. One set is for interrupt
processing (interrupt mode flags). The other set is for
normal operations (program mode flags). When an interrupt occurs, a context switch is made from the program flags to the interrupt flags. An RTI forces the context
switch back. While in either mode, only the flags for that
mode are available. A context switch does not affect the
value of the C or Z bits. Both sets of flags are cleared by
RESET.

:r::
MCU

Figure 5. Powerup RESET Delay Circuit

MOTOROLA MICROPROCESSOR DATA
3-321

1 OJlF
.

I
.

..

MC6804P2

INTERRUPT
The MCU can be interrupted by applying a logic low
signal to the IRQ pin. However, a manufacturing mask
option determines whether the falling edge or the actual
low level of the IRQ pin is sensed to indicate an interrupt.

I

EDGE-SENSITIVE OPTION
When the IRQ pin is pulled low, the internal interrupt
request latch is set. Prior to each instruction fetch, this
interrupt request latch is tested. If its output is low, an
interrupt sequence is initiated at the end of the current
instruction, provided the interrupt mask is cleared. Figure
6 contains a flowchart that illustrates both the reset and
interrupt sequences.
The interrupt sequence consists of one cycle during
which:
the interrupt request latch is cleared;
the interrupt mode flags are selected;
the program counter (PC) is saved on the stack;
the interrupt mask is set; and
the IRQ vector jump address is loaded into the PC.

The IRQ vector jump address is$FFC-$FFD in the singlechip mode and $FF8-$FF9 in the self-check mode. The
contents of these locations are not decoded as an address
to which the PC should jump. Instead, they are decoded
like any other ROM word. So, it is essential that the vector
contents specify a JMP instruction in addition to the starting address of the interrupt service routine. If required,
this routine should save the values of the accumulator
and the X and Y registers, since these values are not
stored on the stack.
Internal processing of the interrupt continues until a
return from interrupt (RTI) instruction is processed. During RTI the interrupt mask is cleared and the program
mode flags are selected. The next instruction of the program is then fetched and executed.
When the interrupt was initially detected and the interrupt sequence started, the interrupt request latch was
cleared so that the next interrupt could be detected. These
steps occurred even as the first interrupt was being serviced. However, even though the second interrupt edge
set the interrupt request latch during the first interrupt's
processing, the second interrupt's sequence can not begin until completion of the interrupt service routine for

O-DOR.
1 -INTERRUPT MASK

o-INTERRUPT REOUEST
LATCH lEDGE
SENSITIVE OPTION)
$ff-TCR
$OO-TSCR
m - PRESCALER

LOAO PROGRAM
COUNTER FROM
RESET VECTOR
LOCATION
$FFE/$FFF

Figure 6. Reset and Interrupt Flowchart

MOTOROLA MICROPROCESSOR DATA
3-322

MC6804P2

interrupt sequence there is no need to clear the interrupt
request latch. These differences are shown in Figure 6.

the first interrupt. Completion of an interrupt service routine is always accomplished using anRTI instruction to
return to the main program. The interrupt mask, which
is not directly available to the programmer, is cleared
during the last cycle of the RTI instruction.

POWERUP AND TIMING
During the powerup sequence, the interrupt mask is
closed. This precludes any false interrupts. The PC is also
loaded with the appropriate restart vector (jump instruction).
To open the interrupt mask, the user should do a JSR
to an initialization subroutine that ends with an RTf in~
stead of an RTS. The RTI opens the interrupt mask. Typical RESET and IRQ processes and their relationship to
the interrupt mask are shown in Figure 7.

LEVEL-SENSITIVE OPTION
Actual operation of the level-sensitive and edge-sensitive options are similar. However, the level-sensitive
option does not have an interrupt request latch. Since
there is no interrupt request latch, th~ logic level of the
IRQ pin is checked to detect the interrupt. Also, in the

JMP-START
VECTOR (FFE-FFF)

.................................................
START (ROUTINE)
INSTRUCTION (I-N)

I

INTERRUPT
MASK
CLOSED

LAST INSTRUCTION
JSR INIT

I

INIT
INITIALIZATION
SUBROUTINE

-

1
LAST INSTRUCTION
RTI

I

PROGRAM

MASK
OPEN

IRQ
RECOGNIZED

........................
IRQ
SERVICE
ROUTINE

INTERRUPT
MASK
CLOSED

I
LAST INSTRUCTION
RTI

PROGRAM

I

........................
MASK
OPEN

Figure 7. Interrupt Mask

MOTOROLA MICROPROCESSOR DATA
3-323

II

MC6804P2

Maximum interrupt response time is six machine cycles.
This includes five cycles for the longest instruction plus
one for stacking the PC and switching flags.

described for the input mode. However, in the output
mode, once the prescaler decrements the timer counter
to zero, the high TMZ bit state allows TSCR bit 4 (DOUT)
to become direct ,input to the TIMER pin.

TIMER

NOTE

TMZ is normally set to logic one when TCR decrements to zero and the timer times out. However,
it may be set bya write of $00 to the timer counter
or by a write to bit 7 of TSCR.

A block diagram of the MC6804P2 timer circuitry is
shown in Figure 8. The timer logic in the MCU is comprised ota simple8-bit counter called the timer counter.
This counter is decremented by a.7-bit prescaler at a rate
determined by the timer status/control register (TSCR).

TIMER COUNT REGISTER ($FE)
PRESCALER

I

The prescaler is a 7-bit counter used to extend the maximum interval of the overall timer. This counter is clocked
by a signal from the TIMER pin or by the internal sync
pulse. It divides the frequency received by some factor
to create the prescaler output. The factor by which the
TIMER pin signal is divided is called the prescaler tap.
The value of this tap is selected by three bits of the TSCR
(PSO-PS2). These bits control the division of the prescaler
input within the range of divide-by-2°, to divide-by-27.
TIMER COUNTER

The timer counter, which may be read or loaded under
program control, is decremented from a maximum value
of 256 toward zero by the prescaler output. Both are decremented on rising clock edges.
The prescaler register and timer count register are
readable and writeable. A write to either one will take
precedence over the normal counter function. For example, if a value is written to the timer count register,
and this write and a decrement-to-zero occu r at the same
time, the write takes precedence. TSCR bit one (TMZ) is
not set until the next timer time out.

The timer count register reflects the current count in
the internal 8-bit counter. The register is the counter and
can be read or written.
7

I MSB

LSB

RESET:

TIMER STATUS/CONTROL REGISTER (TSCR) ($09)
5
4

I TMZ I

TIMER PIN

The TIMER pin may be programmed as either an input
or an output. Its status depends on the value of TSCR bit
5 (TOUT). This relationship is shown in the TIMER pin
status section of Figure 8. The frequency of the internal
clock applied to the TIMER pin must be less than tbyte,
which is (fosc/48).
TIMER INPUT MODE

In the timer input mode, TOUT is logic zero and the
TIMER pin is connected directly to prescaler input. So,
the prescaler is clocked by the signal from the TIMER pin.
The prescalerdivides the TIMER pin clock input by the
prescaler tap. The prescaler output then clocks the 8-bit
timer count register. When this register is decremented
to zero, it sets TSCR bit one (TMZ). This TMZ bit can be
tested under program control to tell when the counter
register has reached zero.

I TOUT I DOUT I

PSI

PS2

PSO

o

TMZ -

Timer Zero
1 = Timer count register has decremented to zero
since the last time the TMZ bit was read.
0= This bit is cleared by a read of the TSCR if TMZ
is read as logic one.

Bit 6
Not used by this register.
TOUT - Timer Output
1 = Output mode is selected for the timer.
0= Input mode is selected for the timer.
DOUT - Data Output
Latched data at this bit is sent to the TIMER pin when
both the TMZ and TOUT bits are logic high.
PSI - Prescaler Initialize
1 = Prescaler begins to decrement.
0= Prescaler is initialized and counting is inhibited.
PSO-PS2
These bits are used to select the prescaler tap. The
coding of the bits is shown below:

PS1

PSO

°

°

0

1

°

0

1

2

°

1

0

4

0

1

1

8

TIMER OUTPUT MODE

1

0

0

16

In the output mode, the TIMER pin is output. TOUT is
a logic one. The prescaler is clocked by the internal sync
pulse. This pulse is a divide-by-48 ofthe internal oscillator
(fosc/48). From this point on, operation is similar to that

1

0

1

32

1

1

0

64

1

1

1

128

PS2

MOTOROLA MICROPROCESSOR DATA
3-324

PSI

RESET:

Divide By

MICROCOMPUTER INTERNAL BUS
SYNC

READ

3:

a
:lJ

o

WRITE

8·BIT COUNTER
PRESCALER

TIMER
PIN

SELECT
1----.......,.----11 1·OF·8
INITIALIZE

READ

TIMER STATUS/CONTROL
REGISTER nSCR)

§:
TMZ

3:

W

W
N
U1

o
:lJ

s:n
en

0

00

."

i"'CI

:lJ

o

n

N

m

C/)
C/)

o:lJ

.~
»

bO

b7

TIMER COUNT REGISTER
nCR)

WRITE

TIMER PIN STATUS
TIMER

TOUT

PRESCALER
CLOCK

0
1

TIMER PIN
SYNC

INPUT MODE
OUTPUT MODE

PIN

Figure 8. Timer Block Diagram

MC6804P2 '

It is recommended that MVI or load immediate and
storing instructions be used when changing bit values in
the TSCR. Read-modify-write instructions can cause the
TMZ to assume an unexpected state.
During reset, the TSCR is set to all zeros; the TIMER
pin is in the high impedance input mode; and DOUT
LATCH is forced to a logic high. At the same time, PSOPS2 coding sets the prescaler tap at divide-by-one, and
bit 3 initializes the prescaler.

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. All INC and DEC
forms along with all bit manipulation instructions use this
method. Refer to the following list of instructions.

TIMER PRESCALER REGISTER ($FD)
The timer prescaler register reflects the current count
ofthe 7-bit prescaler. This register is the prescaler counter
and can be read or written.
6

I MSB

LSB

RESET:
1

II

INSTRUCTION SET
The MCU has a set of 42 basic instructions. They can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is the accumulator; the other is obtained from
memory using one of the addressing modes. Refer to the
following list of instructions.
Function

Mnemonic

Load A from Memory

LOA

Load XP from Memory

LOX

Load YP from Memory

LOY

Store A in Memory

STA

Add to A

ADD

Subtract from A

SUB

AND Memory to A

AND

Transfer A to XP

TAX

Transfer A to YP

TAY

Transfer YP to A

TVA

Transfer XP to A

Function

Mnemonic

Increment Memory Location

INC

Increment A

INCA

Increment XP

INCX

Increment YP

INCY
DEC

Decrement Memory Location
Decrement A

DECA

Decrement XP

DECX

Decrement YP

DECY

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two-byte instructions. Refer to the following list of instructions.
Function

Mnemonic

Branch if Carry Clear

BCC
(BHS)

Branch if Higher or Same
Branch if Carry Set

BCS

..

(BLO)

Branch if Lower
Branch if Not Equal

BNE

Branch if Equal

BEQ

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the 256 bytes of data space where all port
registers, port DDRs, timer, timer control, and on-chip
RAM reside: An additional feature allows the software to
test and branch on the state of any bit within these 256
locations. The bit set, bit clear, and bit test and branch
functions are all implemented with a single instruction.
For the test and branch instructions, the value of the bit
tested is also placed in the carry bit ofthe condition code
register. Refer to the following list of instructions.
Function

TPA

Mnemonic

Branch If Bit n is Set

BRSET n(n = 0 ... 7)

CLRX

Branch If Bit n is Clear

BRCLR n(n = 0 ... 7)

CLRY

Set Bit n

BSET n(n =0 ... 7)

Arithmetic Compare with Memory

CMP

Clear Bit n

BCLR n(n=O ... 7)

Move Immediate Value to Memory

MVI

Clear A

CLRA

Clear XP
Clear YP

Arithmetic Left Shift of A

ASLA

Complement A

COMA

Rotate A Left and Carry

ROLA

CONTROL INSTRUCTIONS
These instructions are used to control processor operation during program execution. The jump conditional
(JMP) and jump to subroutine (JSR) instructions have no

MOTOROLA MICROPROCESSOR DATA
3-326

MC6804P2

register operand. Refer to the following list of instructions.
Function

Mnemonic

Return from Subroutine

IMMEDIATE
In the immediate addressing mode, the operand is located in program ROM. It is contained in the byte immediately following the opcode. The. immediate
addressing mode is used to access constants that do not
change during program execution, such as a constant
used to initialize a loop counter.

RTS

Return from Interrupt

RTI

No Operation

NOP

Jump to Subroutine

JSR

Jump Unconditional

JMP

IMPLIED INSTRUCTIONS
Since the accumulator and all other registers are located in RAM, many implied instructions exist. Some of
the instructions recognized and translated by the assembler are shown below:
Mnemonic
ASLA

Becomes

Mnemonic

DIRECT
In the direct addressing mode,the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the 256 bytes of data spate with a single twobyte instruction.

Becomes

ADD $FF

INCX

INC $80

BHS

BCC

INCY

INC $81

BLO

BCS

LDXI

MVI $80 DATA

CLRA

SUB $FF

LDYI

MVI $81 DATA

CLRX

MVI $80 #0

NOP

BEQ (PC) +1

CLRY

MVI $81 #0

TAX

STA $80

DECA

DEC $FF

TAY

STA $81

DECX

DEC $80

TXA

LDA $80

DECY

DEC $81

TVA

LDA $81

INCA

INC $FF

SHORT DIRECT
In the short direct addressing mode, the MCU has four
locations in data space RAM it can use, ($80; $81, $82,
and $83). The opcode determines the data space RAM
location, and the instruction is only one byte. Short direct
addressing is a subset of the direct addressing mode.
The X and Y registers are at locations $80 and $81 , respectively.

Some examples of valuable instructions not specifically recognized by the assembler are shown below:
Mnemonic

describing the various addressing modes. Effective address is defined as the address from which the argument
for an instruction is fet9hed or stored.

Meaning

BCLR 7,$FF

Ensures A is plus

BSET 7, $FF

Ensures A is minus

BRCLR 7, $FF

Branch itA is plus

BRSET 7, $FF

Branch if A is minus

BRCLR 7, $80

Branch if X is plus (BXPL)

BRSET 7, $80

Branch if X is minus (BXMI)

BRCLR 7, $81

Branch if Y is plus (BYPL)

BRSET 7, $81

Branch if Y is minus (BYMI)

EXTENDED
In the extended addressing mode, the effective address
of the argument is obtained by concatenating the four
least-significant bits oftheopcode with the byte following
the opcode to form a 12-bit address. Instructions using
the extended addressing mode, such as JMP or JSR, are
capable of branching anywhere in program space. An
extended address(ng mode instruction is two bytes long.
RELATIVE
The relative addressing mode is only used in conditional branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the
opcode is added to the PC if, and only if, the branch
conditions are true. Otherwise, control proceeds to the
next instruction. The span of relative addressing is from
-15 to + 16 from the opcode address. The programmer
need not calculate the offset when using the Motorola
assembler, since it calculates the proper offset and checks
to see that it is within the span of the branch.

OPCODE MAP
Table 1 is a listing of all the instruction set opcodes
applicable to the MC6804P2 MCU.

ADDRESSING MODES
The MCU has nine different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. It deals with objects in three different address spaces: program space, data space, and
stack space. The term "effective address" (EA) is used in

BIT SET/CLEAR
In the bitsetlclear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte in which
the specified bit is to be set or cleared. Thus, any bit in
the 256 locations of data space memory that can be written to can be set or cleared with a single two-byte instruction.
CAUTION
The corresponding DDRs for ports A, B, and Care
write only registers (registers at $04, $05, and $06).

MOTOROLA .MICROPROCESSOR DATA·
3-327

II

Table 1. Opcode Map

Bit Manipulation
Instructions

Register/Memory, Control, and
Read/ Modify/Write Instructions

Branch Instructions
~

~

•
S--

Register / Memory and
Read/ Modify/Write

CA

Hi

~

~
BNE

BED

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BEQ

BEQ

BCC

BCC

BCS

Bes

JSRn

JMPn

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BGS

JSRn

BNE

BNE

BEQ

BEQ

BCC

BGC

BCS

BCS

JSRn

BEQ

BCC

BCC

BCS

BGS

BNE

!

BNE

MVI

BRCLRO

BCLRO

LDA

LDA

BRCLR1

BCLR1

STA

STA

RTI

BRCLR2

BCLR2

ADD

ADD

JMPn

RTS

BRCLR3

BCLR3

SUB

SUB

JMPn

COMA

BRCLR4

BCLR4

CMP

CMP

JSRn

JMPn

ROLA

1 BRCLR5

BGLR5

AND

AND

BRCLR6

BCLR6

INC

INC

BRCLR7

DEC-

RELll

,0001

3:

~

I.,

BNE

BEQ

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

Bes

JSRn

JMPn

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

Bes

JSRn

JMPn

BCLR7

DEC

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

Bes

JSRn

JMPn

INC

DEC

1

BRSETO

BSETO

LDA

BNE

BNE

BEQ

BED

BCC

Bee

BCS

Bes

JSRn

JMPn

INC

DEC

1

BRSET1

BSETl

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

Bes

JSRn

JMPn

INC

DEC

1

BRSET2

BSET2

ADD

ADD

m

BNE

BNE

BEQ

BEQ

BCC

Bec

BCS

BCS

JSRn

JMPn

INC

DEC

1

BRSET3

BSET3

SUB

SUB

~

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

Bes

JSRn

JMPn

Lo'A

STA

1

BRSET4

BSET4

CMP

CMP

BRSET5

BSET5

AND

AND

BRSET6

BSET6

INC

BSED

DEC

BNE

io

~

REL

3:

n

Co)

N

co

LDA

3:

STA

00

(")

~.

w0

."

0')

:II

on

A

CJ)

o

~

A

;

D

BNE

BNE

BEQ

BED

BCC

BCC

BCS

BCS

JSRn

JMPn

LDA

STA

BNE

BNE

BEQ

BEQ

BCC

BCC

Bes

BCS

JRSn

JMPn

LDA

STA

I
s

D

13
B T BI~

BNE

BNE

BEQ

BEQ

'BCC

BCC

BCS

BCS

JSRn

JMPn

LDA

STA

BRSED

f.XT!2

Abbreviations for Address Modes
INH
SoD
B-T-B
IMM
DIR
EXT
REL
BSC
R-INO

Inherent
Short Direct
Bit Test and Branch
Immediate
Direct
Extended
Relative
Bit Set/ Clear
Register Indirect

LEGEND
Indicates Instruction Reserved for Future Use
Indicates Illegal Instruction

CYCleS~,
Mnemomc'--- --Bytes,·

4

~

11115
t

1

...., '

Opcode in Hexadecimal
Opcode in Binary

LOA

R-IND

L -______~------~~

2"'C
N

MC6804P2

branching is from -125 to + 130 from the opcode address. The state of the tested bit is also transferred to the
carry flag.

A read operation on these registers is undefined.
Since BSET and BCLR are read-modify-write functions, they cannot be used to set or clear a DDR bit;
all "unaffected" bits would be set. Write all DDR
bits in a port using a single-store instruction.

REGISTER·INDIRECT
In the register-indirect addressing mode, the operand
is at the address in data space pointed to by the contents
of one of the indirect registers, X or Y. The particular
indirect register is selected by bit 4 of the opcode. Bit 4
decodes into an address that represents the register, $80
or $81. A register-indirect instruction is one byte long.

BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit to be tested, and its condition (set or clear), is included
in the opcode. The data space address of the byte to be
tested is in the single byte immediately following the
opcode byte. The third byte is sign extended to twelve
bits and becomes the offset added to the PC if the condition is true. This single three-byte instruction allows the
program to branch based on the condition of any readable bit in the 256 locations of data space. The span of

INHERENT
In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. These instructions are one byte long.

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Vo,ltage

VCC

-0.3 to +7.0

V

Input Voltage

Vin

-0.3 to + 7.0

V

Operating Temperature Range (Comm.)

TA

o to 70

°c

TA

-40 to +85

°c

Tstg

. -55 to + 150

°c

Rating

Operating Temperature Range (Ind.)
Storage Temperature Range
Junction Temperature
Plastic
PLCC
Cerdip

°c

TJ
150
150
175

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions. be taken to avoid application of
any voltage higher than maximum-rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ~ (Vin or Vout) ~ VCC.
Reliability of operation is enhanced if unused inputs except EXTAL are connected to an appropriate logic voltage level (e.g., either VSS or VCC).

THERMAL CHARACTERISTICS
Symbol

Characteristic
Thermal Resistance
Plastic
PLCC
Cerdip

Value

Unit
°CIW

6JA
70
120
60

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can
be obtained from:
TJ = TA + (PD 9JA)
(1 )
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance,
9JA
Junction-to-Ambient,oC/W
PD
= PINT+ PPORT
= ICC x VCC, Watts - Chip Internal Power
PINT
PPORT = Port Power Dissipation,
Watts - User Determined
0

For most applications PPORT 1,4>2 TIMING
OSC

fbi 4> 1 - SYNC TIMING
~1

SYNC

r---1

,----,

~

I______--~------------------IL
Figure 12. Clock Generator Timing Diagram

MOTOROLA MICROPROCESSOR DATA

3·330

MC6804P2

PORT DC ELECTRICAL CHARACTERISTICS
(VCC= +5.0 Vdc±0.5 Vdc, VSS=GND, TA=O° to 70°C, unless otherwise noted)
Characteristic

Min

Symbol

Typ

Max

Unit

Ports A, C, and Timer (Standard)
Output Low Voltage, ILoad = 0.4 rnA

VOL

-

-

0.5

V

Output High Voltage, ILoad = - 50 fA-A

VOH

2.3

-

-

V

Input High Voltage

VIH

2.0

-

Vec

Input Low Voltage

VIL

-0.3

-

0.8

V

Hi-Z State Input Current

ITSI

-

4

40

/-LA

V

Ports A and C (Open Drain)
Output Low Voltage, ILoad = 0.4 rnA

VOL

-

-

0.5

V

Input High Voltage

VIH

2.0

-

Vec

V

Input Low Voltage

VIL

-0.3

-

0.8

V

Hi-Z State Input Current

ITSI

-

4

40

/-LA

ILOD

-

4

40

/-LA

Open Drain Leakage (Vout= VCe!

Ports A and C (CMOS Drive)
Output Low Voltage, ILoad=0.4 rnA (Sink)

VOL

-

-

0.5

V

Output High Voltage, ILoad = -10 /-LA

VOH

Vee- 1.O

-

-

V

Output High Voltage, ILoad = - 50 /-LA

VOH

2.3

-

-

V

Input High Voltage, ILoad = - 300 /-LA Max

VIH

2.0

-

Vec

V

Input Low Voltage, ILoad= -300 /-LA Max

VIL

-0.3

-

0.8

V

-

-

-300

/-LA

Hi-Z State Input Current (Vin = 0.4 V to Vcc)

ITSI
Port B (Standard)

Output Low Voltage, ILoad = 1.0 rnA

VOL

-

-

0.5

V

Output Low Voltage,ILoad = lOrnA (Sink)

VOL

-

-

1.5

V

Output High Voltage, ILoad = - 100 /LA

VOH

2.3

-

-

V

Input High Voltage

VIH

2.0

-

Vec

V

Input Low Voltage

VIL

~0.3

-

0.8

V

Hi-Z State Input Current

ITSI

-

8

80

/-LA

Port B (Open Drain)
Output Low Voltage, ILoad = 1.0 rnA

VOL

-

-

0.5

V

Output Low Voltage, ILoad = lOrnA (Sink)

VOL

-

-

1.5

V

Input High Voltage

VIH

2.0

-

Vec

V

Input Low Voltage

VIL

-0.3

-

0.8

V

Hi-Z State Input Current

ITSI

-

8

80

/-LA

ILOD

-

8

80

/-LA

Open Drain Leakage (VOllt = Vcr.)
..

Port B (CMOS Drive)

Output Low Voltage, ILoad = 1.0 rnA

VOL

-

-

0.5

V

Output High Voltage, ILoad = 10 rnA (Sink)

VOL

-

-

1.5

V

Output High Voltage, ILoad = - 10 /-LA

VOH

VCC- 1.O

-

-

V

Output High Voltage, ILoad = -100 /LA

VOH

2.3

-

-

V

Input High Voltage, ILoad = - 300 /LA Max

VIH

2.0

-

Vec

V

Input Low Voltage, ILoad = - 300 /LA Max

VIL

-0.3

-

0.8

V

Hi-Z State Input Current (Vin = 0.4 V to Vccl

ITSI

-

-300

/-LA

-

Ports A. B. and C (Low Current Clamping Diode*)
Input High Current VIH = VCC + 1.0 V

IIH

-

-

100

/-LA

Input Low Current VIL = 0.8 V

IlL

-

-

-4.0

/-LA

*Denotes not tested unless specified on ordering form.

MOTOROLA MICROPROCESSOR DATA
3-331

II

MC6804P2

4.0

1

~XPECTE~

3.5

MAX 5.5 V
-40°C

~ 3.0

!

/

2.5

//

I-

~
~

~

2.0

,

/

~V

V......... .......

.'

5

..' ..'

5.0V
25°C

!
Z

••••• EXPECTEO._
MIN 4.5 V
85°C , -

i

100

700

I

I

-300

- 400
2.0

800

2.5

II

~

....... ....... V
/
iE~PECTED I
i

--_...

(2.3 V. - 50 /lM
r---X
-100

~
g
-200

MIN 4.5 V
85°C

~

...

10

;( 9
g

5
~

TYPICAL--i EXPECTED
5.0 V
,MAX 5.5 V
25°C -,- -40°C

1/

,. /

5

~ 4

~

i>,

!

/

/
/

V

/

..
..'

'

.'

..'

/
.'

..' .'

..

....
'

.'EXPECTED
MIN 4.5 V
85°C

..

'

\0.5 V· l rnA)

l

100

200
400
300
VOL. LOW·LEVE.L OUTPUT VOLTAGE (mV)

i

500

X = SPEC PT.

Figure 16. Typical VOL vs IOL for Port B

Figure 15. Typical VOH vs IOH
for Port A with CMOS Pullups

(2.3 V. - 100 /lA)
-100 - X

gir _ 200
:-

~ -300
2:

/

:
: EXPECTED
: MIN 4.5 V
;
85°C

I-

~I

TYPICAL5.0 V
25°C -

,Ij

If,

2.0

2.5

;

i
~

i

EXPECTED
MAX 5.5 V
-40°C

,
,.

~

-100

(2.3 v.
r--X

........ ....t..,. ~ -1_..1-

- 100 /lA)

/

i

-200

4.5

VII
I
I
I

-30q

2:-400

EXP~CTEb

If,

,;

~

J

3.5
3.0
4.0
VOH. HIGH·LEVEl OUTPUT VOLTAGE (V)

/'

1
: EXPE1CTE0 ---, TYPI1CAL f----<
- 5.0 V
MAX 5.5 V_ : MIN 4.5
25°C
85°C
- 40°C,

I

I
II

~
- 400

5.0

~.,

VOH. HIGH·LEVEL OUTPUT VOLTAGE (V)

l-

4.5

¥"

2

X = SPEC PT.

i

4.0

/ ' TYPICAL
5.0 V
25°&/

/ L'"
//. .... .'

3

9 2

!

j

7

::::0

"g

f

±

EXPECTED
V-'
8 1--- -MAX 5.5
- 40 0 Cf

I-

,

~ -300

i

3.5

Figure 14. Typical VOH vs IOH
for Port A and TIMER

.'

:-

-400

3.0

VOH. HIGH·LEVEL OUTPUT VOLTAGE (V)

Figure 13. Typical VOL vs IOL
for Port A and TIMER

I-

!

X = SPEC PT.

X = SPEC PT.

l

,
:
:

~

(0.5 V·lOO /lA)

200
300
400
500
600
VOL. LOW·LEVEl OUTPUT VOLTAGE (mV)

TYPICJL- 'r-AXPEC'TED
, MAX 5.5 V
5.0 V
25°C - I---f - 40°C

"-

g -200
~

".
0

/EJPECTJD: MIN 4.5 V
85°C -

-100

I::::0

±

~r.

~ 0.5

i

I-

:-

...

1.0

V

(2.3 V. - 50 /lA)
r-X

;(

// .........

1.5

0.0

/

/

~YPICAL

- 500
5.0

2.0

2.5

4.0
3.5
4.5
3.0
VOH. HIGH·LEVEl OUTPUT VOLTAGE (V)

X = SPEC PT.

X = SPEC PT.

Figure 17. Typical VOH vs IOH for Port B

Figure 18. Typical VOHVS IOH
for Port B with CMOS Pullops

MOTOROLA MICROPROCESSOR DATA
3-332

5.0

5.5

MC6804P2

ORDERING INFORMATION
The following information is required when ordering a
custom MCU. The information may be transmitted to Motorola using the following media:
MOOS, disk file
MS-DOS/PC-DOS disk file (360K)
EPROM(s) 2516, 2716, 2532, 2732
To initiate a ROM pattern for the MCU, it is necessary
to first contact the local field service office, sales person,
or a Motorola representative.
FLEXIBLE DISKS
Several types of flexible disks (MOOS@) or MSc®-DOS/
PC-DOS disk file) may be submitted for pattern generation. They should be programmed with the customer's
program, using positive logic sense for address and data.
The diskette should be clearly labeled with the customer's
name, date, project or product name, and the filename
containing the pattern.
In addition to the program pattern, a file containing the
program source code listing can be included. This data
will be kept confidential and used to expedite the process
in case of any difficulty with the pattern file.
MOOS Disk File
MOOS is Motorola's Disk Operating System available
on the EXORciser® development system. The disk media
submitted must be a single-sided, single-density, 8-inch
MOOS compatible floppy diskette. The diskette must contain the minimum set of MOOS system files in addition
to the pattern file.
The .LO otuput of the M6804 cross assembler should
be furnished. In addition, the file must be produced using
the ROLLOUT command, so that it contains the absolute
image of the M6804 memory. It is necessary to include
the entire memory image of both program and data space.
All unused bytes, including those in the user space, must
be set to logic zero.
MS-DOS/PC-DOS Disk File
MS-DOS is Microsoft's Disk Operating System. PC-DOS
is IBM® Personal Computer Disk Operating System. Disk
media submitted must be standard density (360K), double-sided 5 114 inch compatible floppy diskette. The diskette must contain the object file code in Motorola's Srecord format. The S-record format is a character-based
object file format generated by M6804 cross assemblers
and linkers on IBM PC style machines.
EPROMS
Four K of EPROM are necessary to contain the entire
MC6804P2 program. Two 2516 or 2716 type EPROMs or
a single 2532 or 2732 type EPROM can be submitted for
pattern generation. The EPROM is programmed with the
customer's program using positive logic sense for address and data. Submissions on two EPROMs must be

clearly marked. All unused bytes, including the user's
space, must be set to zero.
If the MC6804P2 MCU ROM pattern is submitted on
one 2532 or 2732 EPROM, or on two 2516 or 2716 type
EPROMs, memory map addressing is one-for-one. The
data space ROM runs from EPROM address $018 to $05F,
and program space ROM runs from EPROM address $COO
to $FF7, with vectors from $FFC to $FFF.
For shipment to Motorola, EPROMs should be placed
in a conductive IC carrier and packed securely. Styrofoam
is not acceptable for shipment;
Verification Media
All original pattern media, EPROMs or floppy disks, are
filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and
returned along with a listing verification form. The listing
should be thoroughly checked and the verification form
should be completed, signed and returned to Motorola.
The signed verification form constitutes the contractual
agreement for the creation of the customer mask. To aid
in the verification process, Motorola will program customer supplied blank EPROM(s) or DOS disks from the
data file used to create the custom mask.
ROM Verification Units (RVUs)
Ten MCUs containing the customer's ROM pattern will
be sent for program verification. These units will have
been made using the custom mask, but are for the purpose of ROM verification only. For expediency, the MCUs
are unmarked, packaged in ceramic, and tested with five
volts at room temperature. These RVUs are free with the
minimum order quantity, but are not production parts.
These RVUs are not guaranteed by Motorola Quality Assurance.
Ordering Information
The following table provides generic information pertaining to the package type and temperature for the
MC6804P2. This MCU device is available in both the 28pin plastic dual-in-line (DIP) and the 28-lead PLCC package.
Generic Information
Package Type

Order Number

O°C to 70°C
- 40°C to + 85°C

MC6804P2P
MC6804P2CP

Plastic Leaded
Chip Carrier
(FN Suffix)

O°C to 70°C
- 40°C to + 85°C

MC6804P2FN
MC6804P2CFN

MOOS is a trademark of Motorola Inc.
MS is a trademark of Microsoft, Inc.
EXORciser is a registered trademark of Motorola Inc.
IBM is a registered trademark of International Business Machines Corporation.

MOTOROLA MICROPROCESSOR DATA

3-333

Temperature

Plastic
(P Suffix)

MC6804P2

MECHANICAL DATA
PIN ASSIGNMENTS

28-PIN DUAl-IN-LiNE PACKAGE

RESET
PA7
PA6
PA5

PA4
PA3

PCO
PCl

II

28-lEAD PlCC PACKAGE

5 ~·I~

en

I~

.g:~

CQ

~

0

~

26
PA5

MDS

PA4

TIMER

PA3

PCO

PA2

PCl

PAl

PC2

PAD

18

12
c

if

if

N

if

""
if

...
a>

a..

'"
a>
a..

CQ

a>

a..

MOTOROLA MICROPROCESSOR DATA
3-334

MOTOROLA·

I

SEMICONDUCTOR
TECHNICAL DATA

MC68704P2

TechnicalSummary

HMOS Microcomputer Unit
MC68704P2 HMOS (high-density NMOS) microcomputer unit (MCU) is an EPROM member of the
M6804 Family of microcomputers. User programmable EPROM allows program changes and lower
volume applications. This feature further heightens the versatility of an MCU whose design-ability
to process 8-bit variables, one bit at a time, already makes it tremendously cost effective.
This technical summary contains limited information on the MC68704P2. For detailed information,
refer to the advanced information data sheet for·the MC6804J1, MC6804J2, MC6804P2, and
MC68704P2 8-bit microcomputers, (MC6804J1/D) or to the M6804 MeV Manual (DLE404/D).
Major hardware and software features of the MC68704P2 MCU are:
•. Breakpoint and Mask Option Registers

• On-Chip Clock Generator
• 1/0 and Registers Mapped in Data
Space Memory
• Software Programmable8-Bit Timer
with 7-Bit Prescaler
• Single Instruction Memory Examinel
Change
• MC6804JlIJ2/P2 Emulation
• 1088 Bytes of EPROM
• True Bit Manipulation
• Bit Test and Branch Instruction

• Self-Check
• Conditional Branches
• Timer Pin is Software Programmable
as Event Counter or Timer Output
• MC68HC04P2/P3 Pin Compatibility

II

• 32 Bytes of RAM
User selectable options, are:
• Mask Selectable Edge- or Level-Sensitive Interrupt Pin
• .Push-Pull or Open-Drain Interface Ports
BLOCK DIAGRAM

TIMER

ACCUMULATOR
A

PAD
PAl
PORT PA2
PA3
I/O
PA4
LINES PA5
PA6
PA7

CPU
CONTROL

INDIRECT
REGISTER

PORT
A
REG.

DATA
DlR.
REG.

INDIRECT
REGISTER
CPU

EPROM
MASK OPT. REG.

STACK

x

1016 8
USER PROGRAM EPROM
320 x 8
SELF-CHECK ROM

BREAKPOINT
REGISTERS

PBO
PBl
PB2 PORT
B
PB3
PB4 I/O
PB5 LINES
PB6
PB7

PROGRAM
COUNTER
HIGH PCH
PROGRAM
COUNTER
PCl
lOW

AlU

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-335

PCO PORT
PCl
C
PC2
I/O
PC3 LINES

MC68704P2

SIGNAL DESCRIPTION
Vec AND VSS
Power is supplied to the microcomputer using these
two pins. Vee is + 5 volts (± 0.5 V) power, and VSS is
ground.
IRQ
This pin provides the capability for asynchronously applying an external interrupt to the microcomputer.
EXTAL AND XTAL

II

These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal is connected to these pins
to provide a system clock. Selection is made through the
mask option register (MOR). The different clock generator
options are shown in Figure 1, along with crystal specifications.

TIMER
The TIMER pin can be configured to operate in either
the input or output mode. As input, this pin is connected
to the prescaler input and sehies as the timer clock. As
output, the timer pin reflects the contents of the DOUT
bit of the timer status/control register, the last time the
TMZ bit was logic high.
RESET
, The RESET pin is used to restart the processor to the
beginning ofa program. The program counter is loaded
with the address of the restart vector. This should be a
jump instruction to the first instruction of the main program. Together with the MDS pin, the RESET pin selects
the operating mode of the MeU.

Internal Clock Options
The crystal oscillator start-up time is a function of many
variables. To ensure rapid oscillator start-up, neither the
crystal characteristics nor load capacitances should exceed recommendations. When using the on-boardoscillator, the MeUshould remain in a reset condition, with
the RESET pin voltage below VIRES+, until the osCillator
has stabilized at its operating frequency. See Figure 2 for
resistor/capacitor oscillator options.

MDSlVpp
The mode select (MDS) pin places the MeU into special
operating modes. When this pin is logic high at the exit
of the reset state, the decoded state of PA6and PA7 is
latched to determine the operating mode. This choice can
be either the single-chip, self-check, or EPROM programming. However, if MDS is logic low at the end of the reset
state, the single-chip operating mode is automatically
selected. No external diodes, switches, transistors, etc.
are required for single-chip mode selection. This pin is
raised to Vpp voltage to program the EPROM.
INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO·PC3)
These 20 lines are arranged into two 8-bit ports (A and
B) and one 4-bit port (e). All lines are programmable as
+5V

NC
EXTERNAL
CLOCK
INPUT

EXTAL
XTAL

4.7 k
MCU
(CRYSTAL MASK
OPTIONI

EXTAL
XTAL

MCU
(RESISTOR·CAPACITOR MASK
OPTIONI

EXTERNAL CLOCK

(* DENOTES NC/GNO. GROUNDING

PIN 4 WILL REDUCE RFI NOISE.)
EXTERNAL RESISTOR·CAPACITOR
CRYSTAL PARAMETERS

EX""

(al

G2J-."",
C1

XTAL

CJ

CRYSTAL PARAMETERS
AT - CUT PARALLEL RESONANCE CRYSTAL
Co = 7 pF MAXIMUM
FREO. = 11 MHz
RS = 50 OHMS MAXIMUM

EXTAL

MCU
(CRYSTAL MASK
OPTIONI

PIEZOELECTRIC CERAMIC RESONATORS MAY BE
SUBSTITUTED FOR THE CRYSTAl. FOLLOW
MANUFACTURER'S " CERAMIC
RESONATOR
SPECIFICATIONS.

NOTE: Keep crystal leads and circuit connections as short as possible.

Figure 1. Clock Generator Options and Crystal

Parame~ers

MOTOROLA MICROPROCESSOR DATA
3-336

MC68704P2

25~--~--~----r---'---~----r---~---'

15
- - - 22
\
••••••••• 27
~.~M,~t----+---+---I._._ 36
15 \~ '"
........... 50

1\
20 1\

i!

~
I\...~. . . "=!::!
15
...
i'-••~....... ~,
": 10'"
• ' ..
, ... I'." .••• ~:"' .... ~

pF
pF
pF
pF
pF

AT
AT
AT
AT
AT

8.2

25°C 1 25°C 1 _
25°C
25°C I 25°C 1 _

8.0
7.8
:::

~
>-

~~

7.6

",.,.,..~

t.:I

15 7.4
=>

i

--

'lIjOC _ ... - - ... 7.2 t--_"_1r----+-_----+~ _

... -

7.0
6.8
10

14

12

16

6.64.5

18

4.6

......

......

SSoCt-,•.~........~·:.:.··-I·-"-"-"+'--+--,---+---j

...... ......
4.8

4.7

4.9

5.0

5.1

5.2

5.3

5.4

5.5

VCC. SUPPLY VOLTAGE (V)

RL. LOAD RESISTANCE (kO)

(b) TYPICAL FREQUENCY VARIATIONS @ Cl = 15 pF. 10 kO

(a) TYPICAL FREQUENCY VS RESISTANCE

9.8 ..-_"_1I---+--+--+---+---t--+---t--9.6

... -- ~-'

-

~

r----

.......

II

•.,.....,

I-----I----t--+--+--+---+--+--t--t:.~

~ 9.4 1----1--+--+--+---+---+_-:-••~.O'::'••- ••+--+--"-1
~
"------"I----t--+
~4\)OC. •••••• ••••
_ - - ~- ..
~ 9.2 r
:~:'T"
15
•••••••• 'lljoC_~-'''"'
§... 9.0 1----1-,••""• ..-t'''---+-_-::..,.
~
••••••
_ - - ,,"' Slj°s..~~

_..

1

8.4 ' - - _ L - - - L___--L__-.L..__
4.5 4.6 4.7
4.8 4.9 5.0

.......

..J-__.J.....,._ _........- - - '

~___'_;.,J__ _

5.1

5.2

5.3

5.4

5.5

VCC. SUPPLY VOLTAGE (V)
(e) TYPICAL FREQUENCY VARIATIONS @ CL =

50 pF. 3 kO

Figure 2. Typical Frequency Selection for
Resistor/Capacitor Oscillator Options

either inputs or outputs under software control of the
data _direction registers.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING

There are 20 input/output pins. All pins of each port
are programmable as inputs or outputs under the control
of the data direction registers (DDR). The port I/O programming is accomplished by writing
the corresponding bit in the port DDR to a logic one for
output, or a logic zero for input, as shown in Figure 3.
When the registers are programmed, as outputs, the
latched data is readable regardless of the logic levels at
the output pin due to output loading.
All the liD pins are LSTTL compatible as both inputs
and outputs. In addition, all three ports may use either
or both oftwo output options: open drain or push-pull.
Any write to a port writes to all of its data bits even
though the port DDR may be set to input. This can be
used as a tool to initialize the data registers and avoid

undefined outputs. However, care must be exercised when
using read-modify-write instructions. The data read corresponds to the pin I,evel if the DDR is an input or to the
latched output d,ata when the DDR is an output.
The 20 bidirectional lines may be configured by port
to be the standard configuration, push-pull, or open drain.
Port B outputs are LED compatible.
Port Data Registers ($00, $01, $02)

The port data registers are not initialized on reset. These
registers should be initialized before changing the DDR
bits to avoid undefined levels.
Port A ($00) and Port B ($01)

Port C ($02)

x

x

x

MOTOROLA MICROPROCESSOR DATA
3-337

x

MC68704P2

Vcc

r---- .,I

DATA
DIRECTION REGISTER
BIT

I
I

I
IL __ _

en

Ci!~
Z I-

ffi~

I
I

I
I

...J..-_ _..

DATA
BIT

I-Z
Z Z
0

u

II

DATA
DIRECTION
REGISTER
BIT

OUTPUT
DATA
BIT

1

0

1
0

1
X

OUTPUT
STATE

0
1
HI-Z

INPUT
TO
MCU

0
1
PIN

*For CMOS option transistor acts as resistor (approximately 4Ok{l) to Vce.
For LSTTLlopen-drain options transistor acts as low current clamping diode to

Vee.

Figure 3. Typical I/O Port Circuitry

With regard to Port C only, the four MSB bits are unused. These bits are "don't care" (X) bits when written
to but are always logic high when read.
Port Data Direction Registers ($04,$05, $06)
Port DDRs confi!;Jure the portpirls as eithe'r outputs or
inputs. Each port pin can be programmed individually to
be an input or an output. A zero in the pin's corresponding
DDR bit programs it as an input; a logic one programs it
as an output. On reset, all the DDRs are initialized to a
logic zero state to put the ports in the input mode.
Port A ($04) and Port B ($05)
5

Port C($06)

x

x

x

x

With regard to Port C only, the four MSB bits are unused. These bits are "don't care" (X) bits when written
to but are always logic high when read.
'

MEMORY
The MCU memory map (Figure 4) consists of 4352 bytes
of addressable memory and I/O register locations. This
MCU has three separate memory spaces: program space,
data space, and stack space.
The MCU is capable of addressing 4096 bytes of program space memory with its program counter and 256
bytes of data space memory with its instructions. Program space memory includes self-check ROM, program
EPROM, self-check vectors (mask ROM), user program
vectors (EPROM), and reserved memory locations.
A non-accessible subroutine stack space RAM is provided. This stack space consists of a last-in-first-out (LIFO)
register. This register is used with inhereht addressing
to stack the return address for subroutines and interrupts.
Indirect X and Y register locations $80 and $81 are
generally used as pointers for such tasks as indirect addressing to data space locations. Short direct addressing
allows access to the four data space addresses $80-$83
with,' single byte opcodes. The operations allowed are
increment, decrement, load, and store. Data' space locations $82 and $83 can be used for 8~bit counter locations.

MOTOROLA MICROPROCESSOR DATA

3-338

MC68704P2

ADDRESS

BYTES
000 0

$000

.::::-

RESERVED
(2656 BYTES)

;::~

275 1

$ABF

275 2

$ACO

;::';:

SELF-CHECK ROM
(320 BYTES)

~~

00 0

PORT A DATA REGISTER

$00

00 1

PORT B DATA REGISTER

$01

00 2

PORT C DATA REGISTER

$02

00 3

RESERVED

$0

00 4

PORT A DDR

$04

00 5

PORT BOOR

$0

00 6

PORTC DDR

$06

00 7
00 8

RESERVED
(2 BYTES)

$08

00 9

TIMER STATUS CONT. REG.

$09

01 0

RESERVED
(4 BYTES)

~ ....

307 1

$BFF

01 3 '"

307 2

$COO

01 4

BREAKPOINT REG. (LOW)

01 5

BREAKPOINT REG. (HIGH)

01 6

RESERVED
(7 BYTES)

;:: ....

:"-

'"

PROGRAM EPROM
(1016 BYTES)

02.21"

~~

02 3

EPROM MASK OPTION REG.

~
408 7
408 8
408 9
409 0
409 1
409 2
409 3
409 4
409 5

SELF-CHECK IRQ VECTOR
(MASK ROM)
SELF-CHECK RESTART VECTOR
(MASK ROM)
USER IRQ VECTOR
(EPROM)
USER RESTART VECTOR
(EPROM)

USER DATA SPACE EPROM
(72 BYTES)

09 5
09 6

$FF8

RESERVED
(32 BYTES)

~

$FF9

12 7 '"

$FFA

$OA

~~

$00
$DE
$OF

,. $1

..~

$1 6
$17
$18

02 4

$FF7

$07

-:~
$5F
$60

;'''''

to; 7F

INDIRECT REGISTER X

$80

INDIRECT REGISTER Y

$81

USER DATA SPACE RAM
(30 BYTES)

:::~ 9F

12 8

$FFB

12 9

$FFC

13 0

$FFD

:;~

$FFE

15 9
16 0

$FFF

$AD
RESERVED
(93 BYTES)

::::- ....

PROGRAM SPACE

$82

I"-

.::
$FC

25 2
LEVEL 1

25 3

PRESCALER REGISTER

$FD

LEVEL 2

25 4

TIMER COUNT REGISTER

$FE

LEVEL 3

25 5

ACCUMULATOR

$FF

DATA SPACE

LEVEL 4
STACK SPACE

Figure 4. Memory Map

MOTOROLA MICROPROCESSOR DATA
3-339

MC68704P2

REGISTERS

STACK

ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.

A

INDIRECT REGISTERS (X, V)
These two registers are used to maintain pointers to
other memory locations in data space. They are used in
the register-indirect addressing mode and can be accessed with the direct, indirect, short direct, or bit set!
clear modes.

A last-in-first-out (UFO) stack is incorporated in the MCU
that eliminates the need for a stack pointer. This nonaccessible subroutine stack space is implemented in separate RAM, 12-bits wide. Whenever a subroutine cz!! or
interrupt occurs, the contents of the PC are shifted illtc
the top register of the stack. At the same time, the top
register is shifted one level deeper. This happens to all
registers, with the bottom register falling out of the stack.
Whenever a return from subroutine or interrupt occurs,
the top register is shifted into the PC and all lower registers are shifted one level higher. The stack RAM is four
levels deep. If the stack is pulled more than four times
with no pushes, then the address that was stored in the
bottom level of the stack is shifted into the PC.

SELF CHECK

II

x

PROGRAM COUNTER (PC)
The program counter is a 12-bit register that contains
the address of the next byte to be fetched from program
space. The program counter is contained in low byte (PCl)
and high nibble (PCH).
11

8 7

PCH

The MCU implements two forms of internal check: self
check and the verify mode phase of EPROM programming. Self check performs an extensive functional check
of the MCU using a signature analysis technique. For
information on the verify mode in EPROM programming,
see application note, MC68704P2 8-Bit EPROM Microcomputer Programming Module (AN-942).
Self-check mode is selected by holding the MDS and
PA7 pins logic high and the PA6 pin logic low as RESET
goes low to high. Monitoring the self-check mode's stages
for successful completion requires external circuitry, see
Motorola's M6804 MCV Manual (DlE404/D).

PCl

RESET
FLAGS (C,Z)
Thefirstflag, the carry (C) bit, is set on a carry or borrow
out of the arithmetic logic unit (AlU). It is cleared if the
arithmetic operation does not result in a carry or borrow.
The C bit is also set to the value of the bit tested in a bit
test instruction. It participates in the rotate left (ROlA)
instruction, as well.
The second flag, the zero (Z) bit, is set if the result of
the last arithmetic or logic operation was equal to zero.
Otherwise, it is cleared. Bit test instructions do not affect
the Z bit.
_ _:. :.:NO:: .:,R: ,:M: . .:A=-lF:.:LA:..::G::.:S~_---,.._.~I

C

z

_ _~IN~TE_R_RU_P_T_FLA_GS_ _ _~.I

C

z

RESET
All resets of the MC68704P2 are caused by the external
reset input (RESET). A reset can be achieved by pulling
the RESET pinto logic low for.a minimum of 96 oscillator
cycles.
During reset, a delay of 96 oscillator cycles is needed
before allowing the RESET input to go high. If power is
being applied, RESET must be held low long enough for
the oscillator to stabilize and then provide the 96 clocks.
Connecting a capacitor and resistor to the RESET input,
as shown in Figure 5 below typically provides sufficient
delay.
+5V
4.7 k

28

There are two sets ofthese flags. One set is for interrupt
processing (interrupt mode flags). The other set is for
normal operations (program mode flags). When an interrupt occurs, a context switch is made from the program flags to the interrupt flags. An RTI forces the context
switch back. While in either mode, only the flags for that
mode are available. A context switch does not affect the
value of the C or Z bits. Both sets of flags are cleared by
RESET.

:r:,.O/tF

MCU

Figure 5. Powerup RESET Delay Circuit

MOTOROLA MICROPROCESSOR DATA
3-340

MC68704P2

INTERRUPT
The MCU can be interrupted by applying a logic low
signal to the IRQ pin. However, a bit in the mask option
register (MOR) determines whether the falling edge or
the actual low level of the IRQ pin is sensed to indicate
an interrupt.

EDGE-SENSITIVE OPTION
When the IRQ pin is pulled low, the internal, interrupt
request latch is set. Prior to each instruction fetch, this
interrupt request latch is tested. If its output is low, an
interrupt sequence is initiated at the end of the current
instruction, provided the interrupt mask is cleared. Figure
6 contains a flowchart that illustrates both the reset and
interrupt sequences.
The interrupt sequence consists of one cycle during
which:
the interrupt request latch is cleared,
the interrupt mode flags are selected,
the program counter (PC) is saved on the stack,
the interrupt mask is set, and
The IRQ vector jump address is loaded into the PC.

1-

The IRQ vector jump address is $FFC·$FFD in the singlechip mode and $FF8-$FF9 in, the self-check mode. The
contents of these locations are not decoded as an address
to which the PC should jump. Instead, they are decoded
like any other EPROM program word. So, it is essential
that the vector contents specify aJMP instruction in addition to the starting address pf the interrupt service routin,e. If required, this routine should save the values of
the accumulator and the X and Y registers, since these
values are not stored on the stack.
','
.
Internal processing of the interrupt continues until a
return from interrupt (RTI) instruction is processed. During RTI the interrupt mask is cleared and the program
mode flags are selected. The next instruction of the program is then fetched and executed.
When the interrupt was initially detected and the interrupt sequence started, the interrupt request latch was
cleared so that the next interrupt could be detected. These
steps occurred even as the first interrupt was being serviced. However, even though the second interrupt edge
set the interrupt request latch during the first interrupt's
processing, the second interrupt's sequence can not begin until completion of the interrupt service routine for
the first interrupt. Completion of an interrupt service rou-

O-DDRs
INTERRUPT MASK

o-INTERRUPT REQUEST
LATCH lEDGE
SENSITIVE OPTIONI
$FF-TCR
$00- TSCR
$FF - PRESCALER

LOW

LOAD PROGRAM
COUNTER FROM
RESET VECTOR
LOCATION
$fFE/$FFF

Figure 6. Reset and Interrupt Flowchart

MOTOROLA MICROPROCESSOR DATA
3~341

I

MC68704P2

tine is always accomplished using an RTI instruction to
return to the main program. The interrupt mask, which
is not directly available to the programmer, is cleared
during the last cycle of the RTI instruction.

LEVEL-SENSITIVE· OPTION
Actual operation of the level-sensitive and edge-sen~
sitive options are similar. However, the level-sensitive
option does not have an interrupt request latch. Since
there is no interrupt request latch, the logic level of the
IRQ pin is checked to detect the interrupt. Also, in the
interrupt sequence there is no need to clear the interrupt
request latch. These differences are shown in Figure ~.

POWERUP AND TIMING
During the pqwerupsequence, the interrupt mask is
closed. This precludes any. false interrupts. The PC is also.
loaded with the appropriate restart vector (jump instruc~
tion).
To open the interrupt mask, the user should doa JSR
to an initialization subroutine that ends with an RTI instead of an RTS. The RTI opens the interruptmask. Typical RESET and IRQ processes and their relationship to
.
the interrupt mask are shown in Figure 7.
Maximum interrupt response time is six machine cycles.
This includes five cycles for the longest instruction plus
one for stacking the. PC and switching flags.

JMP-START
VECTOR (FFFFFF)

.................................................

I

START (ROUTINE)
INSTRUCTION (I-N)

I

INTERRUPT
MASK
CLOSED

LAST INSTRUCTION
JSR INIT

I

INIT
INITIALIZATION
SUBROUTINE

I
LAST INSTRUCTION
RTI

1

PROGRAM

MASK
OPEN

IRQ
RECOGNIZED

I

........................
IRQ
SERVICE
ROUTINE

INTERRUPT
MASK
CLOSED

I
LAST INSTRUCTION
RTI

PROGRAM

I

........................
MASK
OPEN

Figure 7. Interrupt Mask

MOTOROLA MICROPROCESSOR .DATA
3-342

MICROCOMPUTER INTERNAL BUS
READ

s:

a
o
:xl

8-BIT COUNTER
TIMER
PIN

w

W

""0
:xl

W
~

1 - - -.........--11 l-DF-8

WRITE

bO

b7

TIMER COUNT REGISTER
(TCR)

TIMER STATUS/CONTROL
REGISTER (TSCR)
TMZ

3:
n

!g

0

;s

o

n

m

(J)
(J)

o
:xl
o

~

READ

SELECT

>
s:
n
:xl

WRITE

TIMER PIN STATUS
TOUT

PRESCAlER
CLOCK

TIMER
PIN

TIMER PIN
SYNC

INPUT MODE
OUTPUT MODE

FigureS. Timer Block Diagram -

MC68704P2

TIMER

NOTE

A block diagram of the MC68704P2 timer circuitry is
shown in Figure 8. The timer logic in the MCU is comprised of a simple 8-bit counter called the timer counter.
This counter is decremented by a 7-bit prescaler at a rate
determined by the timer status/control register (TSCR).
PRESCALER
The prescaler is a 7-bit counter used to extend the maximum interval of the overall timer. This counter is clocked
by a signal from the TIMER pin or by the internal sync
pulse. It divides the frequency received by some factor
to create the prescaler output. The factor by which the
TIMER pin signal is divided is called the prescaler tap.
The value of this tap is selected by three bits of the TSCR
(PSO-PS2). These bits control the division of the prescaler
input within the range of divide-by-20 , to divide-by-2 7 .

I

TM2 is normally set to logic one when TCR decrements to zero and the timer times out. However,
it may be set by a write of $00 to the timer counter
or by a write to bit 7 of TSCR.
TIMER COUNT REGISTER (SFE)
The timer count register reflects the current count in
the internal 8-bit counter. The register is the counter and
can be read or written.
7

I MSB

LSB

RESET:

TIMER STATUS/CONTROL REGISTER (TSCR) ($09)
5

TIMER COUNTER
The timer counter, which may be read or loaded under
program control, is decremented from a maximum value
of 256 toward zero by the prescaler output. Both are decremented on rising clock edges.
The prescaler register and timer count register are
readable and writeable. A write to either one will take
precedence over the normal counter function. For example, if a value is written to the timer count register,
and this write and a decrement-to-zero occur at the same
time, the write takes precedence. TSCR bit one (TM2) is
not set until the next timer time out.
TIMER PIN
The TIMER pin may be programmed as either an input
or an output. Its status depends on the value of TSCR bit
5 (TOUT)~ This relationship is shown in the TIMER pin
status section of Figure 8. The frequency of the internal
clock applied to the TIMER pin must be less than tbyte,
which is (fosc/48).
TIMER INPUT MODE
In the timer input mode, TOUT is logic zero and the
TIMER pin is connected directly to prescaler input. So,
the prescaler is clocked by the signal from the TIMER pin.
The prescaler divides the TIMER pin clock input by the
prescaler tap. The prescaleroutput then clocks the 8-bit
timer count register. When this register is decremented
to zero, it sets TSCR bit one (TM2). This TM2 bit can be
tested under program control to tell when the counter
register has reached zero.
TIMER OUTPUT MODE
In the output mode, the TIMER pin is output. TOUT is
a logic one. The prescaler is clocked by the internal sync
pulse. This pulse is a divide-by-48 of the internal oscillator
(foscl48). From this point on, operation is similar to that
described for the input mode. However, in the output
mode, once the prescaler decrements the timer counter
to zero, the high TM2 bit state allows TSCR bit 4 (DOUT)
to become direct input to the TIMER pin.

I TMZ I

PSI

PS2

PSl

PSO

RESET:

o

TM2 - Timer zero
1 = Timer count register has reached the all zero's
state since the last time the TM2 bit was read
0= This bit is cleared by a read of the TSCR if TM2
is read as logic one
Bit 6
Not used by this register
TOUT - Timer output
1 = Output mode is selected for the timer
0= Input mode is selected for the timer
DOUT - Data output
Latched data at this bit is sent to the TIMER pin
when both the TM2 and TOUT bits are logic high.
PSI - Prescaler initialize
1 = Prescaler begins to decrement
0= Prescaler is initialized and counting is inhibited
PSO- PS2
These bits are used to select the prescaler tap. The
coding of the bits is shown below:

PS2

PS1

PSO

0

0

0

1

0

0

1

2

0

1

0

4

0

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

.1

1

1

128

Divide By

It is recommended that MVI or loading and storing
instructions be used when changing bit values in the
TSCR. Read-modify-write instructions can cause the TM2
to assume an unexpected state.

MOTOROLA MICROPROCESSOR DATA
3-344

4

I TOUT I DOUT I

MC68704P2

During reset, the TSCR is set to all zeroes; the TIMER
pin is in the high impedance input mode; and DOUT
LATCH is forced to a logic high. At the same time, PSOPS2 coding sets the prescaler tap at divide-by-one, and
bit 3 initializes the prescaler.

MASK OPTION REGISTER (MOR) ($17)
The MC68704P2 uses the EPROM MOR during emulation to select the clock/oscillator, port, and interrupt
request edge- and level-sensitive triggering options available on the MC6804J1/J2/P2 devices. The mask option
register is not affected by RESET.

TIMER PRESCALER REGISTER ($FD)
The timer prescaler register reflects the current count
ofthe 7-bit prescaler. This register is the prescaler tounter
and can be read or written.

x

Ii

I MSB

OSC -

LSB

RESET:
1

EPROM
BREAKPOINT REGISTERS
The breakpoint registers are used as a program debugging aid. To enable the breakpoint registers:
- The MDS pin must be pulled high using a 300 ohm
resistor to + 5 volts.
- In the Port A I/O register, both PA6 and PA7 pins
must be pulled low using a 10 kilohm resistor to
ground.
A breakpoint address is written into address registers
ARL and ARH by the user. The lower eight bits of the
breakpoint address (AO-A7) are written into the ARL. The
upper four bits (A8-A 11) are written into the ARH.

Emulation
The MC68704P2 MCU internal EPROM can be programmed to emulate either the MC6804J1, MC6804J2,
or the MC6804P2 MCU device. While the M6805 Family
of EPROM MCUs have an on-chip bootstrap-loader program stored in mask ROM, the MC68704P2 does not.
Additional programming hardware and software are required to program this MCU EPROM. For more specific
information regarding the programming and erasing of
the MCU EPROM; see application note, MC68704P2 8-Bit
EPROM Microcomputer Programming Module (AN-942).

Breakpoint Address Register Low (ARL) ($OE)
7

I

A7

I

A6

A5

A4

A3

A2

Al

The oscillator option bit
1 = Resistor/capacitor mode of operation
0= Crystal mode of operation
The crystal mode is selected in the EPROM programming mode, regardless of the state of OSC.
PORT A - Port A output selection bit
1 =Open drain output mode
O=Three-state output mode
PORT B - Port B output selection bit
1 = Open drain output mode
O=Three-state output mode
PORT C - Port C output selection bit
1 = Open drain output mode
O=Three-state output mode
IRQ - Interrupt request bit
1 = Level-sensitive triggering input mode
0= Edge-sensitive triggering input mode
Bits 6, 4, and 0
Not used in this register

AO

RESET:

o
A7-AO
Breakpoint address bits A7 through AO.
Breakpoint Address Register High (ARH) ($OF)

Emulation Limitations

x

x

x

x

A11

A10

A9

AS

RESET:

o
A11-A8
Breakpoint address bits A 11 through A8.
NOTE
ARL must be written after writing to ARH.
ARL and ARH are concatenated to form the breakpoint
address. When the processor fetches an instruction having the same address as the breakpoint address, the MDS
pin goes logic low for one machine cycle. This operation
does not alter program flow.

This EPROM MCU is designed to emulate the functions
of the MC6804J1/J2/P2 devices as closely as possible.
Limitations to this capability pertain to the CMOS pullup option; execution out of data space, and packaging
pin assignments of the MCU being emulated. The limitations do not apply to the timing, execution speed, or
functionality of the MCU being emulated.
This MCU cannot emulate the CMOS pullup option. To
implement the CMOS option, external 40 kilohm pullup
resistors are connected to the specific I/O port signal lines.
All other options are available through correct use ofthe
MOR bytes.
It was necessary that the PC of this MCU have access
to both the program and data space EPROM because of
the implementation of the MCU programming hardware.
Therefore, the MC68704P2 will execute code out of the

MOTOROLA MICROPROCESSOR DATA
3-345

I

•

Prog,~

-~

~
'===========~~~------~i

.,

4,.02

4"

o

o

'"

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MctIB704P2
MCU

1

U'

MC68705P3

R3

4"

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SN74lS368

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g

AIm'

~

8 ....

1-'

------I

MOS

CO2

'''''''

-~

~

5' XTAL

Bo"V
I
~~ __ 1''''

~

..

330

s:

0

-0
~ffi

~ 8El
%

[,~'""""-,.,1

AS

330

Notes:
1. Pins 1. 8,.nd 15 connected to GND for devices U2.nd U3.
2.

3.

Figure 9. Programming Module Schematic

Pin 16 connected to +SVfor~U2.ndtJ3.
Pin 7 connected to GND. and pin 14 connected to +5 V for
devicesU1.ndU4.

.....
0
,all.

"'0
N

MC68704P2

data space EPROM ($18-$5F). This anomaly is not permitted on the MC6804JlIJ2/P2 ROM devices. When planning on operating ROM patterns from this EPROM MCU,
the programmer should not use data space as extra program space.
The MC6804JlIJ2 devices are packaged in 20-pin dualin-line (OIL). The MC6804P2 and the MC68704P2 devices
are packaged in 28-pin OIL packages. Device pin assignments must be adhered to. When emulating a 20-pin
MCU with this EPROM MCU, all unused pins (PAO-PA3,
PCO-PC3) should be grounded externally through a 10
kilohm resistor. This allows the MC68704P2 to emulate
the software execution exactly as it would occur on the
20-pin device.

EPROM ERASING
This MCU EPROM is erased by exposure to a high intensity ultraviolet light (UV) with a wavelength of 2537
Angstrom. The recommended dosage is 15Ws/cm2, (UV
intensity at EPROM surface/area to be erased). UV lamps
should be used without filters. The MC68704P2 should
be positioned about one inch from the UV source. The
duration of the exposure is a function of the radiant
strength of the individual UV source.
EPROM PROGRAMMING HARDWARE
The MC68704P2 programming module, shown in Figure 9, is used to program the MC68704P2 MCU EPROM.
To do this, the module requires a 2K EPROM ofthe 2716
type, a + 5 Vdc power supply, and either a MC68705P3
or MC6805P2 MCU as the module MCU. For more specific
information regarding the hardware and procedures necessary to program the MC68704P2; see either the advanced information data sheet for MC6804J1, MC6804J2,
MC6804P2, and MC68704P2 8-bit microcomputers
(MC6804J1/D) or application note, MC68704P2 8-Bit
EPROM Microcomputer Programming Module (AN-942).

Function
AND Memory to A

Mnemonic
AND

Transfer A to XP

TAX

Transfer A to YP

. TAY

Transfer YP to A

TVA

Clear A

CLRA

Clear XP

CLRX

Clear YP

CLRY

Arithmetic Compare with Memory

CMP

Move Immediate Value to Memory

MVI

Arithmetic Left Shift of A

ASLA

Complement A

COMA

Rotate A Left and Carry

ROLA

Transfer XP to A

TPA

READ~MODIFY -WRITE

INSTRUCTIONS

These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. All INC and DEC
forms along with all bit manipulation instructions use this
method. Refer to the following list of instructions.
Function
Increment Memory Location

Mnemonic
INC

Increment A

INCA

Increment XP

INCX

Increment YP

INCY

Decrement Memory Location

DEC

Decrement A

DECA

Decrement XP

DECX

Decrement YP

DECY

INSTRUCTION SET
The MCU has a set of 42 basic instructions. They can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is the accumulator; the other is obtained from
memory using one of the addressing modes. Refer to the
following list of instructions.
Function

Mnemonic

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list of instructions.
Function
Branch if Carry Clear
Branch if Higher or Same
Branch if Carry Set
Branch if Lower

Mnemonic
BCC
(BHS)
BCS
(BLO)

Load A from Memory

LDA

Branch if Not Equal

BNE

Load XP from Memory

LDX

Branch if Equal

BEQ

Load YP from Memory

LDY

Store A in Memory

STA

Add to A

ADD

Subtract from A

SUB

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the 256 bytes of data space, where all port
registers, port DDRs, timer, timer control, and on-chip

MOTOROLA MICROPROCESSOR DATA
3-347

I

MC68704P2

RAM reside. An additional feature allows the software to
test and branch on the state of any bit within these 256
locations. The bit set, bit clear, and bit test and branch
functions are all implemented with a single instruction.
For the test and branch instructions, the value of the bit
tested is also placed in the carry bit ofthe condition code
register. Refer to the following list of instructions.

Ensures A is plus

BSET 7,$FF

Ensures A is minus

BRCLR 7, $FF

Branch if A is plus

BRSET 7, $FF

Branch if A is minus

BRCLR 7, $80

Branch if X is plus (BXPL)

Mnemonic

BRSET 7, $80

Branch if X is minus (BXMI)

Branch If Bit n is Set

BRSET n(n = 0 ... 7)

BRCLR 7, $81

Branch if Y is plus (BYPL)

Branch If Bit n is Clear

BRCLR n(n = 0 ... 7)

BRSET 7, $81

Branch if Vis minus (BYMJ)

Function

Set Bit n

BSET n(n=O ... 7)

Clear Bit n

BCLR n(n=O ... 7)

OPCODE MAP
Table 1 is a listing of all the instruction set opcodes
applicable to the MC6804P2 MCU.

CONTROL INSTRUCTIONS

I

Meaning

Mnemonic
BCLR 7,$FF

ADDRESSING MODES

These instructions are used to control processor operation during program execution. The jump conditional
(JMP) and jump to subroutine (JSR) instructions have no
register operand. Refer to the. foUowing list of instructions.
Mnemonic

Function

RTS

Return from Subroutine
Return from Interrupt

RTI

No Operation

NOP

Jump to Subroutine

JSR

Jump Unconditional

JMP

The MCU has nine different addressing modes to provide the programmer vv'ith an opportunity to optimize the
code for all situations. It deals with objects in three different address spaces: program space, data space, and
stack space. The term "effective address" (EA) is used in
describing the various addressing modes. Effective address is defined as the address from which the argument
for an instruction is fetched or stored.

IMMEDIATE
Inthe immediate addressing mode, the operand is located in program ROM. It is contained in the byte immediately· following the opcode .. The immediate
addressing mode is used to access constants that do not
change during program execution, such as a constant
used to initialize a loop counter.

IMPLIED INSTRUCTIONS
Since the accumulator and all other registers are located in RAM, many implied instructions exist. Some of
the instructions recognized and translated by the assembler are shown below:
Mnemonic

Becomes

Mnemonic

DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the 256 bytes of data space with a single twobyte instruction.

Becomes

ASLA

ADD $FF

INCX

INC $80

BHS

BCC

INCY

INC $81

. BLO

BCS

LDXI

MVI $80 DATA

CLRA

SUB $FF

LDYI

MVI $81 DATA

CLRX

MVI $80 #0

NOP

BEQ (PC) +1

CLRY

MVI $81 #0

TAX

STA $80

DECA

DEC $FF

TAY

STA $81

DECX

DEC $80

TXA

LDA $80

DECY

DEC $81

TVA

LDA $81

INCA

INC $FF

SHORT DIRECT
In the short direct addressing mode, the MCU has four
locations in data space RAM it can use, ($80, $81, $82,
and $83). The opcode determines the data space RAM
location, and the instruction is only one byte. Short direct
addressing isa subset of the direct addressing mode.
The X and Y registers are at locations $80 and $81, respectively.

:..

Some examples of valuable instructions not specifically recognized by the assembler are shown below: .

EXTENDED
In the extended addressing mode, the effective address
of the argument is obtained by concatenating the four
least-significant bits of the opcode with the byte following
the opcode to form a 12-bit address. Instructions using
the extended addressing mode, such as JMP or JSR, are
capable of branching anywhere in program space. An
extended addressing mode instruction is two bytes long.

MOTOROLA MICROPROCESSOR DATA
3-348

Table 1. Opcode Map

Register/Memory, Control, and
Read/Modify/Write ·Instructions

Branch Instructions

............... ---m

g--

Bit Manipulation
Instructions

-A

Register/Memory and

Read/Modify/Write

D

Hi

Low~

..----

~Low

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE .

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BCC

BCC

BCS

BCS

MVI

BRCLRO

BCLRO

LOA

LOA

BRCLR1

BCLR1

STA

STA

BNE

BNE

BEQ

BEQ

JSRn

JMPn

RTI

BRCLR2

BCLR2

ADD

ADD

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

RTS

BRCLR3

BCLR3

SUB

SUB

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

COMA

BRCLR4

BCLR4

CMP

CMP

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

ROLA

BRCLR5

BCLR5

AND

AND

BNE

BNE

BEQ

BEQ

BCC"

BCC

I'

BCS

BCS

JSRn

JMPn

BRCLR6

BCLR6

INC

INC

BNE

BNE

BEQ

BEQ

BCC

BCC

I,

BCS

JSRn

JMPn

BRCLR7

BCLR7

DEC

DEC

I,

BNE

BEQ

BEQ

BCC

BCC

I

BCS

JSRn

JMPn

I BRSETO

BSETO

LOA

LOA

,

BNE

I,

BNE

BEQ

'BEQ

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

BNE

BEQ

'BEQ

BCC

BCC

BCS

BCS

IN.HI3

R-INP

3:

o

a
:::a
o

~

3:

w

n
:::a

BNE

W o
"'U
ct :::a
o(")

REL

BNE

A

BNE

REl

m

en
en
o
:::a
c

,

BNE

~

o

,

,

REl

I,

BCS

BEQ

REl

I,

BEQ

,

REl

I,

BCC

I'

BCC

REl

I,

BCC

I'

BCC

REl

I,

BCS

I'

BCS

REl

R;'L

I,
I

BCS

REL

BCS

1

REL

2

BNE

BNE

BEQ

BNE

BNE
BNE

BEQ

BCC

BCC

BCS

BEQ

BEQ

BCC

BCC

BCS

BEQ

BEQ

BCC

BCC

BCS

REl

I,

BCS

I,

REl

REL

I,
I

INC

DEC

s:

(')

JMPn

INC

DEC

I BRSET1

BSET1

JSRn

JMPn

INC

DEC

I BRSET2

BSET2

ADD

ADD

JSRn

JMPn

INC

DEC

I BRSET3

BSET3

SUB

SUB

JSRn

JMPn

LOA

STA

sol, BRSET4

BSET4

CMP

CMP

BSET5

AND

AND

JSRn

CO

STA

"g
A

2

I,

5

~, JSRn

JMPn

LOA

JRSn

JMPn

LOA

STA

BRSET6

BSET6

INC

JSRn

JMPn

LOA

STA

BRSED

BSED

DEC

BCS
RELll

BNE

REL

BCS

G)

2

BNE

REl

I

STA

'BRSET5

D

RELI2

BCS
AELI2

Abbreviations for Address Modes
INH
S-D

Inherent
Short Direct

B- T-B

Bit Test and Branch

IMM
DIR
EXT
REL
BSC
R.-IND

Immediate
Direct
Extended
Relative
Bit Set/ Clear
Register Indirect

Indicates Instruction Reserved for Future Use
Indicates Illegal Instruction

~~=i'
Mnemonic

Bytes

'II

1

""5

LEGEND

% ..

R-IND

OpcodeinHexadecimal
Opcode in Binary

LOA

___ _

;S

MC68704P2

RELATIVE
The relative addressing mode is only used in conditional branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the
opcode is added to the PC if, and only if, the branch
conditions are true. Otherwise, control proceeds to the
next instruction. The span of relative addressing is from
-15 to + 16 from the opcode address. The programmer
need not calculate the offset when using the Motorola
assembler, since it calculates the proper.offset and checks
to see that it is wi'thin the span of the branch.

I

BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte in which
the specified bit is to be set or cleared. Thus, any bit in
the 256 locations of data space memory that can be written to can be set or cleared with a single 2-byte instruction.

BIT TEST AND BRANCH

The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear) is
included in theopcode. The data space address of the
byte to be tested is in the single byte immediately following the opcode byte. The third byte is sign extended
to twelve bits and becomes the offset added to the PC if
the condition is true. This single 3-byte instruction allows
the program to branch based on the conditio,", of any
readable bit in the 256 locations of data space. The span
of branching is from -125 to + 130 from the opcode
address. The state of the tested bit is also transferred to
the carry flag.
REGISTER-INDIRECT

CAUTION
The corresponding DDRs for ports A, a, and Care
write only registers (registers at $04, $05, and $06).
A read operation on these registers is undefined.
Since BSET and BClR are read-modify-write functions, they cannot be used to set or cleara DDR bit;
all "unaffected" bits would be set. Write all DDR
bits in a port using a single-store instruction.

In the register-indirect addressing mode, the operand
is at the address in data space pointed to by the contents
of one of the indirect registers, X or Y. The particular
indirect register is selected by bit 4 of the opcode. Bit 4
decodes .into an address that represents the register, $80
or' $81. A register-indirect instruction is one byte long.
INHERENT

In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. These instructions are one byte long.

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to + 7.0

V

Input Voltage

Vin

-0.3 to +7.0

V

Operating Temperature Range (Comm.)

TA

o to 70

Operating Temperature Range (Ind.)

TA

-40 to +85

TstQ

-55 to +150

TJ

175

°c
°c
°c
°c

Symbol

Value

Rating

Storage Temperature Range
Junction Temperature (Cerdip)

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however; it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum-rated voltages
to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ,,;;; (Vin or Vout) ,,;;; VCC·
Reliability of operat,ion is enhanced if unused inputs except EXTAL are connected to an appropriate logic voltage level (e.g., either VSS or VCC).

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Cerdip

Unit

°CIW

IIJA
60

TEST
POINT

TEST
POINT

40 pF
(TOTAL)

3D pF
(TOTAl)

Figure 11. LSTTL Equivalent
Test Load (Port B)

Figure 1(). LSTTL Equivalent
Test Load (Ports A, C,
and TIMER)

MOTOROLA MICROPROCESSOR DATA
3..350

MC68704P2

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can
be obtained from:
TJ=TA +(PO 6JA)
(1)
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance,
6JA
Junction-to-Ambient, °C/W
Po
= PINT+PPORT
= ICC x Vcc' Watts - Chip Internal Power
PINT
PPORT = Port Power Oissipation,
Watts - User Oetermined
0

For most applications PPORT 1·<1>2 TIMING

OSC

"-------'
(b) q, 1 - SYNC TIMING

4>1

SYNC

r---,

~

I~

___________________________r--l
'
L
Figure 12. Clock Generator Timing Diagrams

MOTOROLA MICROPROCESSOR DATA
3-352

MC68704P2

4.0

~XPECTEb

i

3.5

I

3.0

MAX 5.5 V ,
40°C

2.5

/

~

2.0

$
~

1.0

/

V
/" .........

~YPICAL

L

5.0V
25°C

V

.......

~ 0.5

100

f~JpECTlo-

100

i

~

~

§

-200

i

(0.5 V.;oO ",A)

200
300
400
500
600
VOL. LOW·LEVEL OUTPUT VOLTAGE (mV)

~

-

700

2.5

~

~

-x

f

~

~

~

;;:

-200

-300

85°C

~I

2.0

2.5

f---

"

TYPICAL- 1---1 EXPECTED
5.0 V
MAX 5.5 V
-40°C
25°C -

rI

5.0 V
25°C/

3.0
3.5
4.0
VOH. HIGH·LEVEL OUTPUT VOLTAGE (V)

,•!
.,

4.5

f--M~X4~~5c ~,
1/
~,

/

./

,- V L..' ..'
I / .' ..,
I//. ....

j

I
II

~
-400

4.0

I TYPICAL
EXPECTED

I

• EXPECTED
: MIN 4.5 V

10

;

/

:

(2.3 V. -100 ,.,A)

-100

3.5

4.5

5.0

Figure 14. Typical VOH vs IOH
for Ports A, C, and TIMER

Figure 13. Typical VOL vs IOL
for Ports A, C, and Timer

~

3.0

VOH. HIGH·LEVEL OUTPUT VOLTAGE (V)
X=SPEC PT.

X=SPEC PT,

l

, MAX 5.5 V

~

-400
2.0

800

,

,J

I

-300

!~XPEJTEo
Ir, -40°C

;

I

...

~

i

TYPIC)l5.0 V
25°C -

MIN 4.5 V
85°C -

~

".

0.0 0

1Li:l

// ....•....
/~..•..

1.5

.. ..

I-- X

~

'
'
.····EXPECTEo_
.'
MIN 4.5 V
85°C . -

V

(2.3 V. - 50 ",A)

1
z

~f. ..'

.'

L

.. .'
.'

..

'

....

..
.'

II

'

'

EXPECTED
MIN 4.5 V
85°C

~.,

10.5 V. l rnA)

~

l

100

5.0

200
300
400
VOL. LOW·LEVEL OUTPUT VOLTAGE (mV)

j

500

X= SPEC PT.

X=SPEC PT.

Figure 15. Typical VOH vs IOH for Port B

Figure 16. Typical VOL vs IOL for Port B

ORDERING INFORMATION
The MC68704P2 EPROM MCU device is only available in the 28-pin ceramic dual-in-line (CERDIP) package. The
following table provides information pertaining to the temperature and MC order numbers of the MC68704P2.

Table 2. Generic Information
Package Type
Cerdip
(S Suffix)

Temperature
O°C to 70°C
- 40°C to + 85°C

Order Number
MC68704P2S
MC68704P2CS

MOTOROLA MICROPROCESSOR DATA

3-353

MC68704P2

MECHANICAL DATA
PIN ASSIGNMENTS

Vss

RESET

PAl
PAS
PA5
PA4
PA3
PA2
PCO

I

PCI

PAO

PC2

PBl

PB5

MOTOROLA MICROPROCESSOR DATA

3·354

MOTOROLA

I

SEMICONDUCTOR
TECHNICAL DATA

MC68HC04J2

Technical Summary

8-Bit Microcontroller Unit
MC68HC04J2 HCMOS microcontroller unit (MCU) device is a member of the M6804 Family of single-chip microcontrollers. This device displays all the versatility of an MCU whose design-ability to
process 8-bit variables one bit at a time already makes it tremendously cost effeCtive.
This technical summary contains limited information on the MC68HC04J2. For detailed information, refer to the advanced information data sheet for the MC68HC04J2, MC68HC04J3, and
MC68HC04P3 8-bit rriicrocontrollers (MC68HC04J2/D)' or to the M6804 MeV Manual, DLE4041D.
Major hardware and software features of the MC68HC04J2 MCU are:
• On-Chip Clock Generator
• True Bit Manipulation
• Bit Test and Branch Instruction
• Memory Mapped 1/0
• 368 Bytes Self-Check ROM
• Software Programmable 8-Bit Timer with
7-Bit Prescaler
•. Conditional Branches
• Timer Pin is Software Programmable as
• Single Instruction Memory Examinel
Change
Clock Input or Timer Output
• 1672 Bytes of User Program ROM
• 72 Bytes of User Data ROM
• 30 Bytes of User RAM
• User Selectable Input Drive Options

II

• Optional Pull Down Devices on 1/0 Ports
• Mask Selectable Edge- or Level-Sensitive Interrupt Pin

BLOCK DIAGRAM

Timer

Accumulator
A
Indirect
Register

PM
Port
PA5
A
I/O
Lines PA6

Indirect
Register

CPU
Control

X

y

CPU

Stack
PA7

1672x8
User Program ROM

368 x 8

Program
Counter
High PCH
Program
Counter
Low PCL

ALU

Flags

Self-Check ROM

This document contains information on a new product. Specifications and information herein are subject to chimge without notice.

MOTOROLA MICROPROCESSOR DATA
3-355

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

Port
B
I/O
Lines

MC68HC04J2

jump instruction to the first instruction of the main program. Together with the MDS pin, the RESET pin selects
the operating mode of the MCU. A pullup resistor on this
pin is a manufacturing mask option.

SIGNAL DESCRIPTION
VOD AND VSS

Power is supplied to the MCU using these two pins.
VDD is power, and VSS is ground.

MDS

The mode select (MDS) pin places the MCU into special
operating modes. When this pin is logic high at the exit
of the reset state, the decoded state of PA6 and PA7 is
latched to determine the operating mode. This choice can
be either the single-chip, self-check, or ROM verify mode.
However, if MDSis logic low at the end of the reset state,
the single-chip operating mode is automatically selected.
No external diodes, switches, transistors, etc. are required for single-chip mode selection.

IRQ

This pin provides the capability for asynchronously applying an external interrupt to the MCU. A pull-up resistor
on this pin is a manufacturing mask option.
EXTAl AND XTAl

I

These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal is connected to these pins
to provide a system clock. Selection is made by a manufacturing mask option. The different clock generator options are shown in Figure 1, along with crystal
specifications.

INPUT/OUTPUT LINES (PA4-PA7, PBO-PB7)

These 12 lines are arranged into one 4-bit port (A) and
one 8-bit port (8). All lines are programmable as either
inputs or outputs under software control of the data direction registers.

Internal Clock Options

The crystal oscillator start-up timeis a function of many
variables. To ensure rapid oscillator start up, neither the
crystal characteristics nor load capacitances should exceed recommendations. When using the on-board oscillator, the MCU should remain in a reset condition, with
the RESET pin voltage below VIRES +, until the oscillator
has stabilized at its operating frequency.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING

There are 12 input/output pins. The 12 bidirectional
lines can be selected to have internal pulldowns at the
time of manufacture. All pins of each port are programmable as inputs or outputs under the control of the data
direction registers (DDR).
The port I/O programming is accomplished by writing
the corresponding bit in the port DDR to a logic one for
output, or a logic zero for input, as shown in Figure 2.
When the registers are programmed as outputs, the
latched data is readable regardless of the logic levels at
the output pin due to output loading.
All the I/O pins are CMOS compatible as both inputs
and outputs. Their. standard configuration as outputs is
three-state drive. Port 8 outputs are LED compatible. In
addition, certain pins of both ports may be ordered
equipped with pull down resistors.

TIMER

Two TIMER input modes as well as an output mode
are available. In the input modes, the TIMER pin is configured as either a TIMER enable, or as the TIMER clock.
In the output mode, the TIMER pin may generate transitions upon each occurence of timer underflow.
RESET

The RESET pin is used to restart the processor to the
beginning of a program. The program counter is loaded
with the address of the restart vector. This should be a

Crystal Parameters

MC68HC04J2

MC68HC04J2
XTAL

XTAL

5

I
External Resistor
Capacitor

I

MC68HC04J2

EXTAL
4

0

I

Crystal

Clock
Input

NC to
device pin

External Clock

EXTAL4C0-XTAL5
Crystal Parameters
AT - Cut Parallel Resonance Crystal
CO=7 pF Maximum
Freq=ll MHz
RS = 50 Ohms Maximum
Piezoelectric ceramic resonators which
have the equivalent specifications may
be used instead of crystal oscillators.
Follow ceramic resonator manufacturer's suggestions for CO, Cl, and RS
values.

Figure 1. Clock Generator Options and Crvstal Parameters

MOTOROLA MICROPROCESSOR DATA
3-356

Cl

MC68HC04J2

Data
Direction Register 1 - -.....--------4~--___,
Bit

'"

c
c~ ....
tJ

Latched
Output
Data Bit


3:
Co)

3:

n
:1:1

(')
0)

w o"'a

~

00

:::I:

~
n

(')

m
o

N

o

e

:1:1

g
~
CPU Clock Enable
$00- DOR's
Set I Mask
Clear IRQ Latch
SFF -TCR
$00- TSCR
Select Prgm Flags
load Reset Vector
Into PC

g.ii .9!~ I-o:---:-~:-::-:::--i
Select INT Flags

£

u

LoadIN~"
Into PC

Figure 6. Instruction Processing Sequence

MC68HC04J2

JMP-Start
Vector (FFE-FFH

.................................................
Start (Routine)
Instruction (I-N)

r

Interrupt
Mask
Closed

Last Instruction
JSR INIT

I

INIT
Initialization
Subroutine

I
Last Instruction
RTI

I

Program

Mask
Open

IRQ
Recognized

........................
IRQ
Service
Routine

Interrupt
Mask
Closed

I
Last Instruction
RTI

Program

I

........................

Mask
Open

Figure 7. Interrupt Mask

Providing the supply voltage remains within data sheet
limits, the contents of the TSCR, accumulator, and all data
space RAM remain unchanged in STOP mode.
~ausing an interrupt or reset by pulling the RESET or
IRQ pins low is the only way to bring the processor out
of STOP mode. During this exit from STOP, the timer is
used to provide the delay time necessary for the oscillator
to stabilize. So, the prescaler and timer count register
contents must be considered corrupted.
WAIT
The WAIT instruction places the MCU in a low power
consumption mode, but the WAIT mode consumes

somewhat more powerthan the STOP mode. In the WAIT
mode, the internal clock is disabled from all internal circuitry except for the timer. So, all internal processing is
halted. However, the timer continues to decrement normally if the PSI bit of TSCR is set.
During the WAIT mode, exter,nal interrupts are enabled.
All other registers, memory, and liO lines remain in their
last state. Pulling the IRQ or RESET pin to logic low causes
an exit from the WAIT mode. In addition, ETI bifof TSCR
can be enabled by software ,prior to entering the WAIT
state. This allows an exit ~rom WAIT via a timer interrupt
as well as via external interrupts.

MOTOROLA MICROPROCESSOR DATA
3-363

II

MC68HC04J2

Microcomputer Internal Bus

3

TOUT
DOUT

I

Timer Status
Timer Pin TOUT DOUT

SYNC

Input
Output

0
0

Timer Mode

0

Event Counter
Input Gated Mode

0
1

Output

Figure 8. Timer Block Diagram

TIMER

time, the write takes precedence and TSCR bit one (TMZ)
is not set until the next timer time out.

A block diagram of the MC68HC04J2 timer circuitry is
shown in Figure 8. The timer logic in the MCU is comprised of a simple 8-bit counter called the timer counter.
This counter is decremented by a 7-bit prescaler at a rate
determined by the timer status/control register (TSCR).

TIMER PIN
The TIMER pin may be programmed as either an input
or an output. Its status depends on the value of TSCR
bits 4 (DOUT) and 5 (TOUT). Two distinct input modes
exist; input gated mode and input event counter mode.
This relationship is shown in the TIMER pin status section
of Figure 8. The frequency of the internal clock applied
to the TIMER pin must be less than tbyte, which is the
frequency of the oscillator divided by either 12,24, or 48.
Whether fosc is divided by 12, 24, or 48 is determined by
the clock divide ratio, which is selected by the manufacturing mask.

PRESCALER
The prescaler is a 7-bit counter used to extend the maximum interval ofthe overall timer. This counter is clocked
by a signal from the TIMER pin or by the internal sync
pulse. It divides the frequency received by some factor
to create the prescaler output. The factor by which the
TIMER pin signal is divided is called the prescaler tap.
The value of this tap is selected by three bits of the TSCR
(PSO-PS2). These bits control the division of the prescaler
input within the range of divide-by-20, to divide-by-2 7 .

TIMER COUNTER
The timer counter, which may be read or loaded under
program control, is decremented from a maximum value
of 256 toward zero by the prescaler output. Both are decremented on rising clock edges.
The prescaler register and timer count register are
readable and writeabfe. A write to either one will take
precedence over the normal counter function. For example, if a value is written to the timer count register,
and this write and a decrement-to-zero occur at the same

TIMER INPUT EVENT COUNTER MODE
In the timer input event counter mode, both TOUT and
DOUT are logic zero. The TIMER pin is effectively connected directly to prescaler input. So, the timer/prescaler
is clocked by the signal applied from the TIMER pin.
TIMER INPUT GATED MODE
In the input gated mode,TOUT is logic zero and DOUT
is logic one. The timer pin is an input which decrements
the prescaler each machine cycle as long as timer pin is
logic high. When the pin is logic low, counting is inhibited. This mode permits the counting of the period of
time during which the timer pin is logic high, based on
the system clock and prescaler values. Gate times are
fosc/12, fosc/24, and fosc/48.

MOTOROLA MICROPROCESSOR DATA
3-364

MC68HC04J2

TIMER OUTPUT MODE
In the output mode, TOUT is logic one and the TIMER
pin is connected to the DOUT latch. So, the timer prescaler is clocked by the internal sync pulse. This pulse is
a divide-by·12, 24, or 48 of the internal oscillator depending on the mask option. However, in the output mode,
once the prescaler decrements the timer count register
to zero, the low TSCR bit 1 (TMZ) bit state is used to drive
the data latched at TSCR bit 4 (DOUT), onto the TIMER
pin.
NOTE
TMZ is normally set to logi<; one when TCR decrements to zero and the timer times out. However,
it may be set by a write of $00 to TCR or by a write
to bit 7 of TSCR.
TIMER COUNT REGISTER ($FE)
The timer count register reflects the current count in
the internal 8-bitcounter. The register is the counter and
can be written.
7

I MSB

PS1

PSO

0

0

0

1

0

0

1

2

0

1

0

4

0

1

1

8

Divide By

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

It is recommended that MVI or loading and storing
instructions be. used when changing bit values· in the
TSCR. Read-modify-write instructions can cause the TMZ
to assume an unexpected state.
During reset, the TSCR is set to all zeroes. The TIMER
pin is in the high impedance input mode; and DOUT
LATCH is forced to a logic high. At the same time, PSOPS2 coding sets the prescaler tap at divide-by-one, and
bit 3 initializes the prescaler.

TIMER PRESCALER REGISTER ($FD)
The timer prescaler register reflects the current count
ofthe 7-bit prescaler. This register is the prescaler counter
and can be written.

LSB

RESET:
1

PS2

1 ..

6

I MSB

TIMER STATUS/CONTROL REGISTER (TSCR) ($09)
5

TMZ

ETI

4

I TOUT I DOUT I

PSI

PS2

PS1

LSB

RESET:
1
PSO

RESET:

INSTRUCTION SET

o
TMZ - Timer Zero
1 =Timer count register has reached the all-zero
state since the last time the TMZ bit was read.
0= This bit is cleared by a read of the TSCR if TMZ
is read as logic One.
ETI - Enable Timer Interrupt
1 = Timer interrupt enabled
0= Timer interrupt disabled
TOUT - Timer Output
1 :=;Output mode is selected for the timer.
. 0= Input modes are selected for the timer.
DOUT - Data Output
In the output mode, latched data at this bit is sent to
the TIMER pin when both the TMZ and TOUT bits
are logic high.
In the input mode:
1 = Timer input gated mode is selected.
_
O=Timer input event counter mode is selected.
PSI - Prescaler Initialization
1 = Prescaler begins to decrement.
0= Prescaler is initialized and counting is inhibited.
PSO-P$2
These bits are used to select the prescaler tap. The
coding of the bits is shown below:

The MCU has a set of 42 basic instructions. They can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. All INC and DEC
forms along with all bit manipulation instructions use this
method: Refer to the following list of instructions .
Function
Increment Memory Location

INC

Increment A

INCA

Increment XP

INCX.

Increment YP

INCY

Decrement Memory Location

DEC

Decrement A

DECA

Decrement XP

DECX

Decrement YP

DECY

MOTOROLA MICROPROCESSOR DATA
3-365

Mnemonic

II

MC68HC04J2

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is the accumulator; the other is obtained from
memory using one of the addressing modes. Refer to the
following list of instructions.
Function

II

Mnemonic

Load A from Memory

LDA

Load XP from Memory

LDX

Load YPfrom Memory

LDY

Store A in Memory

STA

Add to A

ADD

Subtract from A

SUB

AND Memory toA

AND

Transfer A to XP

TAX

Transfer A to YP

TAY

Transfer YP to A

TVA

Transfer XP to A

TPA

Clear A

CLRA

Clear XP

CLRX

Clear YP

CLRY

Arithmetic Compare with Memory

CMP

Move Immediate Value to Memory

ASLA

Complement A

COMA

Rotate A Left and Carry

ROLA

Function

Branch if Higher or Same
Branch .if Carry Set
Branch if Lower

Mnemonic
RTS

Return from Interrupt

RTI

No Operation

NOP

Jump to Subroutine

J.SR

Jump Unconditional

JMP

Mnemonic

BCS
(BLO)

BEQ

BCLR n(n =0 ... 7)

ASLA

(BHS)

BNE

BSET n(n=O: .. 7)

Clear Bit n

IMPLIED INSTRUCTIONS
Since the accumulator and all other registers are located in RAM, many implied instructions exist. Some of
the instructions recognized and translated by the assembler are shown below:

BCC

Branch if Equal

BRCLR n(n = 0 ... 7)

Set Bit n

Function

Mnemonic

Branch. if Not Equal

Branch If Bit n is Clear

Return from Subroutine

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions. are two byte instructions. Refer to the following list of instructions.

Branch if Carry Clear

Mnemonic
BRSET n(n=O ... 7)

CONTROL INSTRUCTIONS
These instructions are used to control processor operation during program execution. The jump conditional
(JMP) and jump to subroutine (JSR) instructions have no
register operand. Refer to the following list of instructions.

MVI

Arithmetic Left Shift of A

Function
Branch If Bit n is Set

Becomes

Becomes

Mnemonic

ADD $FF

INCX

INC $80
INC $81

BHS

BCC

INCY

BLO

BCS

LDXI

MVI $80 DATA

CLRA

SUB $FF

LOYI

MVI $81 DATA

CLRX

MVI $80 #0

NOP

BEQ (PC) +1

CLRY

MVI $81 #0

TAX

STA $80

DECA

DEC $FF

TAY

STA $81

DECX

DEC $80

TXA

LDA $80

DECY

DEC $81

TVA

LDA $81

INCA

INC $FF

Some examples of valuable instructions not specifically recognized by the assembler are sh.ownbelow:

BIT MANIPULATION INSTRUCTI.ONS
The MCU is capable of setting or clearing any bit which
resides in the 256 bytes of the memory space, where all
port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear, and bit test and
branch functions are all implemented with a- single instruction. For the test and branch instructions, the value
of the bit tested is also placed in the carry bit .of the
condition code register. Refer to the folloWing list of instructions.

Ensures A is plus

BSET 7, $FF

Ensures A is minus

BRCLR 7, $FF

Branch if A is plus

BRSET 7;$FF

Branch if A is minus

BRCLR 7, $80

B~anch if Kis plus (BXPL)

BRSET 7,$80

Branch if X is minus (BXMI)
Branch if Y is plus (BYPL)

BRCLR 7, $81
BRSET 7, $81

MOTOROLA MICROPROCESSOR DATA
3~366

Meaning

Mnemonic
BCLR 7,$FF

,

Branch if Y is minus (BYMI)

MC68HC04J2

OPCODE MAP
Table 1 is a listing of all the instruction. set opcodes
applicable to the MC68HC04J2 MCU.

ADDRESSING MODES
The MCU has nine different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. It deals with objects in three different address spaces: program space, data space, and
stack space. The term "effective address" (EA) is used in
describing the various addressing modes. Effective address is defined as the address from which the argument
for an instruction is fetched or stored.

opcode is added to the PC if, and' only if, the branch
conditions are true. Otherwise, control proceeds to the
next instruction. The span of relative addressing is from
-1!5 to + 16 from the opcode address. The programmer
need not calculate the offset when using the Motorola
assembler, since it calculatesthe proPer offset and checks
to see that it is within the span of the branch.

BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set
or cleared is part of theopcode. The byte following the
opcode specifies the direct addressing of the byte in which
the specified bit is to be set or cleared. Thus; any bit in
the 256 locations of data space memory that can be written to can be set or cleared with a single two-byte instruction.

IMMEDIATE
In the immediate addressing mode, the operand is located in program ROM. It is contained in the byte immediately following the opcode. The immediate
addressing mode is used to access constants that do not
change during program execution, such as a constant
used to initialize a loop counter.
DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the 256 bytes in memory with a single two-byte
instruction.
SHORT DIRECT
In the short direct addressing mode, the MCU has four
locations in data space RAM it can use, ($80, $81,>$82;
and $83). The opcode determines the data space RAM
location, and the instruction is only one byte. Short direct
addressing is a subset of the direct addressing mode.
The X and Y registers are at locations $80 and $81, respectively.
EXTENDED
In the extended addressing mode, the effective address
of the argument is obtained by concatenating the four
least-significant bits ofthe opcode with the byte following
the opcode to form a 12-bit address. Instructions using
the extended addressing mode, such as JMP or JSR, are
capable of branching anywhere in program space. An
extended addressing mode instruction is two bytes long.
RELATIVE
The relative addressing mode is only used in conditional branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the

CAUTION
The corresponding DDRs for ports A and Bare writeonly registers (registers at $04 and. $05). A read
operation on these registers is undefined. Since
BSET and BCLR are read-modify-writefunctions,
they cannot be used to set or clear a DDR bit; all
"unaffected" bits would be set. Write all DDR bits
in a port using a single-store instruction.

BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear) is
included in the opcode. The data space address of the
byte to be tested is in the single byte immediately following the opcode byte. Thethird byte is sign extended
to twelve bits and becomes the offset added to the PC if
the condition is true. This single three-byte instruction
allows the program to branch based on the condition of
any readable bit in the 256 locations of memory. The span
of branching is from -125 to + 130 from the opcode
, address. The state of the tested bit is also transferred to
the carry flag.
REGISTER-INDIRECT
In the register-indirect addressing mode, the operand
is at the address in data space pointed to by the contents
of one of the indirect registers, X or Y. The particular
indirect register is selected by bit 4 of the opcode. Bit 4
decodes into an address that represents the register, $80
or $81. A register-indirect instruction is one byte long.
INHERENT
In the inherent addressing mode, all. the information
necessary to execute the instruction is contained in the
opcode. These instructions are one byte long.

MOTOROLA MICROPROCESSOR. DATA
3-367

II

Table 1. OpcodeMap

Branch Instructions

l_
~

-8

•
Bit, Manipulation

Register/Memory, Control, and
Read/Modify/Writ. Instructions
A

r

Instructions

lOA

lOA

BRelR1

BelR1

STA

STA

JSRn

JMPn

BCS

JSRn

JMPn

BCS

JSRn

JMPn

RTI

BRelR2

BCLR~SC I; AD~!'DI,

JSRn

JMPn

RTS

BRelR3

BelR3

MVI

BNE

BNE

BEQ

BEQ

Bee

BNE

BNE

BEQ

BEQ

Bec

Bce

Bes

BNE

:NE

BEQ

Bee

Bce

Bes OIL

BNE

BNE

BEQ

BCC

BCC

Bes

BCS

JSRn

JMPn

COMA

I BRelR4

BelR4
esc

I BRCLR5

.Oc I,

BEQ
BEQ

I,

:a

3:

w

~ o
"'a
~
(')

co

m

(I)
(I)

9

A

o
:a

~

o

~

ADD
SUB

CMP

eMP

BClRS

AND

AND

BClR6

INC

INC

BelR7

DEC

DEC

.nl>

BNE

BNE

BEQ

BEQ

BCC

BCS

BCS

BNE

BNE

BEQ

BEQ

BeC

Bce

Bes

Bes

JSRn

JMPn

ROlA

BNE

BNE

BEQ

B'EQ

BCC

Bec

BCS

BCS

JSRn

JMPn

BNE

BNE

BEQ

BEQ

Bee

Bce

Bes

BCS

JSRn

JMPn

JSRn

JMPn

INC

I BRCL:~ • I>
WAI!.. I BRCLR7
DEC sol, BRSETO

JSRn

JMPn

INC

DEC

I

BRSET1

BSET1

STOI'_

BNE

BNE

BEQ

BEQ

Bee

Bee

Bes

Bes

BNE

BNE

BEQ

BEQ

BCC

BCC

Bes

BCS

J

J

If

~

011'1

BSETO

lOA

s:

n

m

lOA

:z:

s

n

STA

REtI]

BNE

BNE

BEQ

BEQ

BCC

BCC

Bes

BCS

JSRn

JMPn

INC

DEC

I BRSET2

BSET2

ADD

ADD

BNE

BNE

BEQ

BEQ

B'ec

BCC

Bes

BCS

JSRn

JMPn

INC

DEC

I BRSET3

BSET3

SUB

SUB

BNE

BNE

BEQ

BEQ

I,v

BCC

BCC

BCS

Bes

JSRn

JMPn

LOA

STA

1 BRSET4

BSET4

CMP

eMP

e

I;

BCC

Bee

BSET5

AND

AND

o

A

e
N

BNE

BNE

BEQ

BEQ

OIL

,

BCS

BCS

JSRn

JMPn

LOA

I

STA
S

JMpn~

BNE

Abbreviations for Address Modes
Inherent
Short Direct
Bit Test and Branch
Immediate
Direct
Extended
Relative
Bit Sell Clear
Register Indirect

LOA
,

JMP-n",I~

BNE

INH
5-0
B- T-B
IMM
DIR
EXT
REL
BSe
R-IND

I

SUB

BCC

§;

n
:a

F

BelRO

Bes

AEtn

a
o

T

BRelRO

Bes

BCC

s

3:'

Register/ Memory' and
Read/Modify/Writ.

o

-"I

LOA'

STA

013

BRSET5
B TB

12

~ T -T
BRSET6

BSET6

I

,-

I'

INC

STA'BRSEn';;SEn-

DEC

0"

=

",n

I

LEGEND
Indicates Instruction Reserved for Future Use
Indicates Illegal Instruction

"",~., . W'::
J~
M"'~~:~

Opcode in Binary

MC68HC04J2

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VDD

-0.3 to +7.0

V

Input Voltage

Vin

VSS-0.3 to
VDD+0.3

V

I

10

mA

I
I

30
15

mA

Rating

Current drain per pin
Excluding VDD and VSS
Total currerit for
Ports A, B, C EXTAL, TIM

sink
source

Operating Temperature Range (Comm.)

TA

o to 70

°C

Operating Temperature Range (Ind.)

TA

-40 to +85

°C

Tstg

-55 to + 150

Storage Temperature Range
Junction Temperature
Plastic

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields. However, it is advised that normal precautions be taken to avoid applications of
any voltage higher than maximum-rated voltages
to this high-impedance circuit. For proper operation it is recommended thatVin andVout be constrained to the range VSS,,;(Vin),,;VDD., Reliability
of operation is enhanced if unused inputs except
EXTAL are connected to an appropriate logic voltage level (e.g., either VSS or VCC).

°C
°C

TJ
150

II

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Plastic

Symbol

Value
70

POWER CONSIDERATIONS

The average chip-junction temperature, TJ' in °C can
be obtained from:
TJ=TA+(POoeJA)
(1)
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance,
eJA
Junction-to-Ambient, °CIW
Po
= PINT+ PPORT
= ICC x VCC' Watts - Chip Internal Power
PINT
PPORT = Port Power Oissipation,
Watts - User Oetermined
----~~~--

Pin
Under
Test

Unit
"CIW

eJA

For most applications PPORT 7:.

~O~
~o

'"

~

~

+-

~~~
",>'?~o~o;

.~

~

<,

'"~~=

100

.9

100

~c,
~~o

'"

o

.9

L.o'

~

I

10

1/

10

"J~
I~

IJ

~

l.f

1
1k

10k

100k

1m

. lk

10m

Clock Frequency (Hz)

10k

lOOk

1m

10m

Clock Frequency (Hz)

Figure 10. Typical RUN Current vs Clock Frequency (fClI

Figure 11. Typical WAIT Current vs Clock Frequency (fClI

MOTOROLA MICROPROCESSOR DATA
3-370

MC68HC04J2

DC ELECTRICAL CHARACTERISTICS (Typical pull-down sink current for Vout=VOO is 50 j,LA.)
Characteristic

Symbol

Min

Typ

Max

Unit

-

0.1

V

VOO= +5 Vdc ± 10%. VSS=O Vdc. TA=O°C to 70° C
Output Voltage, ILoad(1O.0 j,LA

VOL
VOH

VOO-O.l

Ports, TIM
Ports, TIM

VOH
VOL

VOO-0.4

Input High Voltage

Ports, TIM, XTAL, MOS
IRQ, RESET

VIH
VIH

0.7 xVOO
0. 8xV OO

Input Low Voltage

Ports, TIM, XTAL, MOS
IRQ, RESET

VIL
VIL

VSS
VSS

RUN
WAIT*
STOP*

100
100
100

-

IlL

-

Output High Voltage, ILoad= +800j,LA)
Output Low Voltage, ILoad = + 800 j,LA)

Total Supply Current
CL = 50 pF, Ports, TIM,
No dc load, tcyc = 1/fCL (max),
VIL =0.2 V, VIH=VOO -0.2 V

1/0 Ports Input Leakage VSS(VI(VOO
Input Current
Capacitance per Pin

RESET, IRQ, TIM

lin

PORT~s

Input or Output)
RESET; IRQ, TIM, XTAL, MOS

Cout
Cin

-

-

-

-

V

0.4
VOO
VOO

V

0. 3xV OO
0. 2XV OO

V

2
0.5
3

3
1
5

mA
mA
j,LA

-

±1

j,LA

-

±1

j,LA

-

12
8

pF

0.1

V

-

-

VOO= +3 Vdc ±10%. VSS=O Vdc. TA=O°C to 70°C
Output Voltage, ILoad(1O.0 j,LA

VOL
VOH

Input Low Voltage

-

VOH
VOL

VOO-0.3

Ports, TIM, XTAL, MOS
IRQ, RESET

VIH
VIH

0. 7xV OO
0. 8xV OO

-

Ports, TIM, MOS, XTAL
IRQ, RESET

VIL
VIL

VSS
VSS

-

RUN
WAIT*
STOP*

100
100
100

Total Supply Current
CL = 50 pF, Ports, TIM,
No dc load, tcyc= l/fCL(Max),
VIL =0.2 V, VIH=VOO-0.2 V

1/0 Ports Input Leakage VSS(VI(VOO
Input Current
Capacitance per Pin

-

Ports, TIM
Ports, TIM

Output High Voltage, ILoad = - 200 j,LA)
Output Low Voltage, ILoad = + 200 j,LA)
Input High Voltage

VOO-O.l

RESET, IRQ, TIM
PORTS (as Input or Output)
RESET, IRQ, TIM, XTAL, MOS

-

-

-

-

-

V

-

0.3

-

VOD
VOO

V

0.3x VOO
0. 2xV OO

V

0.8
0.3
1.5

1.5
0.5
4

mA
mA
j,LA

±1

j,LA

±1

j,LA
pF

V

-

IlL

-

lin

-

Cout
Cin

-

-

-

-

12
8

VOO= +2.2 Vdc ± 10%. VSS=O Vdc. TA=O°C to 70°C
Output Voltage, ILoad(10.0 j,LA

VOL
VOH

Input Low Voltage

-

VOO-Q·3

-

-

-;-

-

0.3

Ports, TIM, XTAL, MOS
IRQ, RESET

VIH
VIH

0. 7xV OO
0. 8xV OO

-

VOO
VOO

V

-

Ports, TIM, MOS, XTAL
IRQ, RESET

VIL
VIL

VSS
VSS

-

0. 3xV OO
0. 2xV OO

V

RUN
WAIT*
STOP*

100
100
100

-

0.6

-

0.2
1

1
0.3
3

mA
mA
j,LA

IlL

-

-

±1

j,LA

lin

-

-

±1

j,LA

Cout
Cin

-

-

pF

-

-

12
8

1/0 Ports Input Leakage VSS(VI(VOO
Capacitance per Pin

0.1

-

VOH
VOL

Total Supply Current
CL = 50 pF, Ports, TIM,
No dc load, tcyc = 1!fcUMax),
VIL =0.2v, VIH=VOO-0.2 V

Input Current

-

Port.s, TIM
Ports, TIM

Output High Voltage, ILoad = -100j,LA)
Output Low Voltage, ILoad = + 100 j,LA)
Input High Voltage

VOO-O.l

REST, IRQ, TIM
PORTS (as Input or Output)
RESET, IRQ, TIM, XTAL, MOS

*Measured under the following conditions:
- All ports and timer pin are configured as input
- XTAL is driven by a square wave input

- EXTAL is open circuit
- port pull downs not enabled

NOTE: Typical pull-down sink current for Vout=VOO is 50 j,LA.

MOTOROLA MICROPROCESSOR. DATA
3~371

V

II

MC68HC04J2

, ORDERING INFORMATION
The following information is required when ordering a
custom MCU. The information may be transmittedto Motorola using the following media:
MDOS<®, disk file
MS<®-DOS disk file (360K)
EPROM(s) 2516, 2716, 2532, 2732
To initiate a ROM pattern for the MCU,it is necessary
to first contact the local field service office, a sales person,
or a Motorola representative.
FLEXIBLE DISKS

II

Several types of flexible disks (MDOS or MS-DOS disk
file) may be submitted for pattern generation. They should
be programmed with the customer program, using positive logic sense for address and data. The diskette should
be clearly labeled with the customer's name, date, project
or product name, and the filename containing the pattern.
In addition to the program pattern, a file containing the
program source code listing can be included. This data
will be kept confidential and used to expedite the process
in case of any difficulty with the pattern file.
MOOS Disk File
MDOS is Motorola's Disk Operating System available
on the EXORciser® development system. The disk media
submitted must be a single-sided, single-density, 8-inch
MDOS compatible floppy diskette. The diskette must contain the minimum set of MDOS system files in addition
to the pattern file.
The .LO output of the M6804 cross assembler should
be furnished. In addition, the file must be produced using
the ROLLOUT command, so that it contains the absolute
image of the M6804 memory. It is necessary to include
the entire memory image of both program and data space.
All unused bytes, including those in the user space, must
be set to logic zero.

MS-DOS Disk File
MS-DOS is Microsoft's Disk Operating System. Disk
media submitted must be standard density (360K), double-sided 5 114 inch compatible floppy diskette. The diskette must contain the object file code in Motorola's Srecord format. The S-record format is a character-based
object file format generated by M6804 cross assemblers
and linkers on IBM PC style machines.

or a single 2532 or 2732 type EPROM can be submitted
for pattern generation. The EPROM is programmed with
the customer's program using positive logic sense for
address and data. Submissions on two EPROMs must be
clearly marked. All unused bytes, including the user's
space, must be set to zero.
.
If the MC68HC04J2 MCU ROM pattern is submitted on
one 2532 or 2732 EPROM, or on two 2516 or 2716 type
EPROMs, memory map addressing is one-for-one. The
data space ROM runs from EPROM address $018 to$05F,
and program space ROM runs from EPROM address $C1 0
to $FF7 with vectors from $FFC to $FFF.
For shipment to Motorola, EPROMs should be placed
in a conductive IC carrier and packed securely. Styrofoam
is not acceptable for shipment.
Verification Media
All original pattern media, EPROMs or floppy disks, are
filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and
returned along with a listing verification form. The listing
should be thoroughly checked and the verification form
completed, signed, and returned to Motorola. The signed
verification form constitutes the contractual agreement
for the creation of the customer mask. To aid in the verification process, Motorola will program customer supplied blank EPROM(s) or DOS disks from the data file
used to create the custom mask.
ROM Verification Units (RVUs)
Ten MCUs containing the customers ROM pattern'will
be sent for program verification. These units will have
been made using the custom mask, but are for the purpose of ROM verification only. For expediency, the MCUs
are unmarked, packaged in ceramic, and tested with, five
volts at room temperature. These RVUs are free with the
minimum order quantity,but are not production parts.
These RVUs are not guaranteed by Motorola Quality Assurance.
Ordering Information
The following table provides generic information pertaining to the package type, temperature, and order numbers for the MC68HC04P3.
Ordering Information
Package Type

EPROMS
Four K of EPROM are necessary to contain the entire
MC68HC04J2 program. Two 2516 or 2716 type EPROMs

Plastic
(P Suffix)

MDOS is a trademark of Motorola Inc.
MSc®-DOS is a trademark of Microsoft, Inc.
EXORciser is a registered trademark.of Motorola Inc.
IBM is a registered trademark of International Business Machines Corporation.

MOTOROLA MICROPROCESSOR· DATA

3-372

Temperature
O°C to 70°C
- 40°C to + 85°C

Order Number
MC68HC04J2P
MC68HC04J2CP

MC68HC04J2

MECHANICAL DATA

PIN ASSIGNMENTS
RESET

Vss

PA7
PA6
PAS
PA4
PB7
PB6
PBS
PBl

PB4

PB2

II

MOTOROLA MICROPROCESSOR DATA
3-373

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC68HC04J~

Technical Summary

8-Bit Microcomputer Unit

II

MC68HC04J3 HCMOS microcomputer unit (MCU) device is a member of the M6804 Family of
single-chip microcomputers. This device is tremendously versatile and cost effective. These qualities are based on the MCU's simple design and ability to process 8-bitvariables, one bit at a time.
This technical summary contains limited information on the MC68HC04J3. For detailed information, refer to the advanced information data sheet for the MC68HC04J2, MC68HC04J3, and
MC68HC04P3 8-bit microcomputers (MC68HC04J2/D) or to the M6804 MeV Manual (DLE404/D).
Major hardware and software features of the MC68HC04J3 MCU are:
• On-Chip Clock Generator
• True Bit Manipulation
• Bit Test and Branch Instruction
• Memory Mapped I/O
• 368 Bytes Self-Check ROM
• Software Programmable 8-Bit Timer with
7-Bit Prescaler
• Conditional Branches
• Single Instruction Memory Examine/
• Timer Pin is Software Programmable as
Change
Clock Input or Timer Output
• 72 Bytes of Data ROM
• 1672 Bytes of User Program ROM
• 30 Bytes of User RAM
• User Selectable Input Drive Options
• Optional Pull Down Devices on I/O Ports
• Mask Selectable Edge- or Level-Sensitive Interrupt Pin

BLOCK DIAGRAM

Timer

Accumulator
A
Indirect
Register

PA4
Port
PA5
A
I/O
Lines PA6

Port
A
Reg.

Data
Dir.
Reg.

Indirect
Register

CPU
Control

X

y

CPU

Stack
PA7

1672 x 8
User Program ROM
368 x 8
Self-Check ROM

Program
Counter
High PCH
Program
Counter
low PCl

AlU

Flags

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA.
3-374

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

Port
B
I/O
Lines

MC68HC04J3

jump instruction to the first instruction of the main program. Together withthe MDS pin, the RESET pin selects
the operating mode of the MCU. A pullup resistor on this
pin is a manufacturing mask option.

SIGNAL DESCRIPTION
VDD AND VSS
Power is supplied to the microcomputer using these
two pins. VDD is power, and VSS is ground. '

MDS
The mode select (MDS) pin places the MCU into special
operating modes. When this pin is logic high at the exit
of the reset state, the decoded state of PA6 and PA7 is
latched to determine the operating mode. This choice can
be either the single-chip, self-check, or ROM verify mode.
However, if MDS is logic low at the end of the reset state,
the single-chip operating mode is automatically selected.
No external diodes, switches, transistors, etc. are required for single-chip mode selection.

IRQ
This pin provides the capability for asynchronously applying an external interrupt to the microcomputer. A pullup resistor on this pin is a manufacturing mask option.
EXTAL AND XTAL
These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal is connected to these pins
to provide a system clock. Selection is made by a mclnufacturing mask option. The different clock generator op~
tions are shown in Figure 1, along with crystal
specifications.

INPUT/OUTPUT LINES (PA4-PA7, PBO-PB7)
These 12 lines are arranged into one 4-bit port (A) and
one 8-bit port (B). All lines are programmable as either
inputs or outputs under software control of the data direction registers.

Internal Clock Options
The crystal oscillator start-up time is a function of many
variables. To ensure rapid oscillator start-up, neither the
crystal characteristics nor load capacitances should exceed recommendations. When using the on-board oscillator, the MCU should remain in a reset condition, with
the RESET pin voltage below VIRES +, until the oscillator
has stabilized 'at its operating frequency.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
There are 12 input/output pins. The 12 bidirectional
lines can be selected tei have, interna'i pulldowns at the
time of manufacture. All pins of each port are programmable as inputs or outputs under the control of the data
direction registers (DDR).
The port 1/0 programming is accomplished by writing
the corresponding bit in the port DDR to a logic one for
output or a logic zero for input, as shown in Figure 2.
When the registers are programmed as outputs, the
latched data is readable regardless of the logic levels at
the output pin, due to output loading.
All the I/O pins are CMOS compatible as both inputs
and outputs. Their standard configuration as outputs is
three-state drive. Port B outputs are LED compatible. ,In
addition, certain pins of both ports may be ordered
equipped with pull down resistors.

TIMER
Two TIMER input modes as well as an output, mode
are available. In the input modes~ the TIMER pin is con- '
figured as either a TIMER enable, or as the TIMER clock.
In the output mode, the TIMER pin may generate transitions upon each occurrence of timer underflow.
RESET
The RESET pin is used to restart the processor to the
beginning of a program. The program counter is loaded
with the address of the restart vector. This should be a

MC6BHC04J3
XTAL

XTAL

5

5

I
External Resistor
Capacitor

MC6BHC04J3

MC6BHC04J3

I

EXTAL

Crystal

I

Clock
Input

NC to
device pin

External Clock

..1'

3-375

tJ-s

" ,
,
Co

"

',XTAL5

Crystal Parameters
AT - Cut Parallel Resonance Crystal
Co = 7' pF MaXimum
FreQ= 11 MHz
RS =50 Ohms MaXimum

Piezoelectric ceramiC. resonators which
have the equivalent speCifications may be
used Instead of crystal oscillators Follow
ceramI(;; resonator ,manufacturers suggestions for Co, C1, and RS values

Figure 1. Clock Generator Options and Crystal Parameters

MOTOROLA MICROPROCESSOR DATA

C1

G

EXTAL4
',,'

4

D

Crystal Parameters

II

MC68HC04J3

Data
Direction
R.egiIter

II

Input

OUlpUt

To
MCU

Data

OUlpUt

Bit

,,

Bit
0

State

,

0

0

0

X

HI-Z

1
Pin

,

Figure 2. Typical I/O Port Circuitry

Any write to a port writes to all of its data bits even
though the port DDR may be set to input. This can be
used as a tool to initialize the data registers and avoid
undefined outputs. However, care must be exercised when
using read-modify-write instructions. The data read corresponds to the pin level if the DDR is an input or to the
latched output data when the DDR is an output.

Port B ($01)

With regard to Port A only, the four MSB bits are unused. These are "don't care" (X) bits when written to but
are always logic high when read.

Pull Down Device Option

Port Data Direction Registers ($04, $05)

The use of pull down devices on particular groupings
of I/O ports is a manufacturing mask option available to
the user. It is of use in applications where keyboards are
interfaced directly to the MCU and similar situations. This
option is available in the following configurations:

Port DDRs configure the port pins as either outputs or
inputs. Each port pin can be programmed individually to
function as input or output. A zero in the pin's corresponding DDR bit programs it as an input; a logic one
programs it as an output. On reset, all the DDRs are initialized to a logic zero state to put the ports in the input
mode.

1/0 Port

Resistor-Option Pin Groupings

PortA

PA4-PA7

Port B

PB3-PB7, PB4-PB7, PB1-PB2, PBO

Port A ($04)

Port Data Registers ($00, $01)
The port data registers are not initialized on reset. These
registers should be initialized before changing the DDR
bits to avoid undefined levels.
The source of data read from the port register is either
the port I/O pin or previously latched output data. The
source depends upon the contents of the corresponding
DDR. The destination of data written to the port data.
register is an output data latch. Ifthe corresponding DDR
for the port I/O pin is programmed as an output, the data
appears on the port pin.
Port A ($00)

x

x

.x

Port B ($05)

With regard to Port A DDR only, the four MSB bits are
cleared after reset. These bits must not be set (logic one).

MEMORY
The MCU memory map (Figure 3) consists of 4352 bytes
of addressable memory, I/O register locations, and stack
space. This MCU has three separate memory spaces:
program space, data space, and stack space.

x

MOTOROLA MICROPROCl=SSOR DATA
3~376

MC68HC04J3

Bytes

Address

Bytes

$000

0000

Address

000

Port A Data Register

$00

00 1

Port B Data Register

$01

002

Reserved
(2 Bytes)

$02

003

:::~

Reserved
(2048 Bytes)

~::::

$03

004

Port A DDR

$04

005

Port BOOR

$05

Reserved
(3 Bytes)

$06

Timer Status Control Register

$09

006

008

$08

2047

$7FF

009

2048

$BOO

010

Low Byte CRC

$OA

011

High Byte CRC

$OB

~::::

Self-Check ROM
(368 Bytes)

~;::

012

.. ~

241 5

$96F

2416

$970

Reserved
(12 Bytes)

........SOC

117
$18

User Data Space ROM
(72 Bytes)

:::~

Program ROM
(1672 Bytes)

Reserved
(32 Bytes)

~~

Indirect Register X
Indirect Register Y

4087

$ FF7

4088

$ FF8

4089
4090

409 1
4092
4093
4094

Self-Check
IRQ Vector
Self-Check
Restart Vector
User
IRQ Vector
User
Restart Vector

i

159
160

$ FF9

User Data Space RAM
(30 Bytes)

Reserved
(93 Bytes)

"""

$ FFA

$ FFC
$ FFD

...

.-

253

Prescaler Register

$ FD

254

Timer Count Register

$FE

255

Accumulator

$ FF

$ FFE
$ FFF

4095

$9F

$FC

252

$ FFB

f

~-----------t $AO

Data Space

Program Space

Levell
Level 2
Level 3
Level 4
Stack Space

Figure 3. Memory Map

MOTOROLA MICROPROCESSOR DATA
3-377

II

MC68HC04J3

The MCU is capable of addressing 4096 bytes of program space memory with its program counter and 256
bytes of data space memory with its instructions. Program space memory includes self-check ROM, program
ROM, self-check and user program vectors, and reserved
memory locations.
A non-accessible subroutine stack space RAM is provided. This stack space consists of a last-in-first-out (LIFO)
register. This register is used with inherent addressing
to stack the return address for subroutines.
Indirect X and Y register locations $80 and $81 are
generally used as pointers for such tasks as indirect addressing to data space locations. Short direct addressing
allows access to the four data space addresses $80-$83
with single byte opcodes. The operations allowed are
increment, decrement, load, and store. Data space locations $82 and $83 can be used for 8-bit counter locations.

II

Program ROM Protect

A manufacturing mask option available to the user enables program ROM protection. enabled, this option prevents the HOM contents from being output during selfcheck/ROM verify. This option does not prevent a go, nogo test of the ROM contents using the ROM verify mode.

FLAGS (C,Z)

The first flag, the carry (C) bit, is set on a carry or borrow
out of the arithmetic logic unit (AlU). It is cleared if the
arithmetic operation does not result in a carry or borrow.
The C bit is also set to the value of the bit tested in a bit
test instruction. It participates in the rotate left (ROlA)
instruction, as well.
The second flag, the zero (2) bit, is set if the result of
the last arithmetic or logic operation was equal to zero.
Otherwise, it is cleared. Bit test instructions do not affect
the Z bit.
NORMAL FLAGS

C

INTERRUPT FLAGS

z
z

There are two sets of these flags. One set isfor interrupt
processing (the interrupt mode flags). The other set is for
normal operations (ttJe program mode flags). When an
interrupt occurs, a context switch is made from the program flags to the interrupt flags. An RTI forces the context
switch back. While in either mode, only the flags for that
mode are available. A context switch does not affect the
value of the C or Z bits. 80th sets of flags are cleared by
RESET.
STACK

REGISTERS
ACCUMULATOR (A)

The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.
A

INDIRECT REGISTERS (X, V)

These two registers are used to maintain pointers to
other memory locations in data space. They are used in
the register-indirect addressing mode and can be accessed with the direct, indirect, short direct, or bit set/
clear modes.
7

A last-in-first-out (LIFO) stack is incorporated in the MCU
that eliminates the need for a stack pointer. This nonaccessible subroutine stack space is implemented in separate RAM, 12-bits wide. Whenever a subroutine call or
interrupt occurs, the contents of the PC are shifted into
the top register of the stack. At the same time, the top
register is shifted one level deeper, This happens to all
registers, with the bottom register falling out of the stack;
Whenever a return from subroutine or interrupt occurs,
the top register is shifted into the PC and all lower registers are shifted one level higher. The stack RAM is four
levels deep. If the stack is pulled more than four times
with no pushes, then the address that was stored in the
bottom level of the stack is shifted into the PC.
CRC Registers

0

~

X

y

PROGRAM COUNTER (PC)

The program counter is a 12-bit register that contains
the address of the next byte to be fetched from program
space. The program counter is contained in low byte (PCl)
and high nibble (PCH).
11

Two eight bit registers are implemented in RAM primarily as self-check and ROM verify modes. The two registers are memory mapped in data space at addresses
$OA (CRC low), and $08 (CRC high).
Provided no write or read/modify/write operation is used
to change the contents of these two locations, the registers are configured to perform CRC calculations. 8y simply reading a register, a pseudo-random number can be
generated.
If a write or a read/modify/write is performed on addresses $OA or $08, then the CRC circuitry is disabled.
Both registers can be used as RAM locations until the
next RESET. RESET enables the CRC circuitry again.

SELF CHECK

8 7

PCH

The MCU implements two forms of internal check, self
check and ROM verify. Self check performs an extensive

pel

MOTOROLA MICROPROCESSOR .DATA
3-378

MC68HC04J3

functional check of the MCU using a signature analysis
technique. ROM verify uses a similar method to check
the contents of program ROM.
Self-check mode is selected by holding the MDS and
PA7 pins logic high, and PA6 logic low as RESET goes
low to high. ROM verify mode is entered by holding MDS,
PA7, and PA6 logic high as RESET goes low to high.
Unimplemented program space ROM locations are also
tested. Monitoring the self-check mode's stages for successful completion requires external circuitry.

RESET
The MCU can be reset by initial power up or by external
reset input (RESET).
POWER-ON-RESET (POR)
During a power-on-reset, the timer is used to count
1920 external clock cycles. This allows the oscillator to
stabilize before releasing the internal reset, irrespective
of the state of the RESET pin. If the RESET pin is low at
the end of the delay, the processor remains in the reset
condition.

+5V
4.7 k

I,·OIlF

MCU

Figure 4. Power Up RESET Delay Circuit
RESET
A reset can also be achieved by pulling the RESET pin
to logic low for a minimum of two clock cycles. The delay
is not implemented in this case.

INTERRUPT
There are two ways this MCU can be interrupted: by
applying a logic low signal to the IRQ pin, or by a positive
transition of the TM2 bit of TSCR with the ETI bit set.
However, a manufacturing mask option determines
whether the falling edge or the actual low level of the
IRQ pin is sensed to indicate an interrupt.
EXTERNAL INTERRUPT EDGE-SENSITIVE OPTION
When the IRQ pin is pulled low, the internal interrupt
request latch is set. Prior to each instruction fetch, this
interrupt request latch is tested. If its output is low,. an
interrupt sequence is initated at the end of the current
instruction, provided the interrupt mask is cleared. Figure

contains a flowchart that illustrates the interrupt and instruction processing sequences.
The interrupt sequence consists of one cycle during
which:
The interrupt request latch is cleared;
The interrupt mode flags are selected;
The program counter (PC) is saved on the stack;
The interrupt mask is set; and
The IRQ vector jump address is loaded into the PC.
The IRQ vector jump address is $FFC-$FFD in the singlechip mode and $FF8-$FF9 in the self-check mode. The
contents of these locations are not decoded as an address
to which the PC should jump. Instead, they are decoded
like any other ROM word. So, it is essential that the vector
contents specify a JMP instruction in addition to the starting address of the interrupt service routine. If required,
this routine should save the values of the accumulator
and the X and Y registers, since these values are not
stored on the stack.
Internal processing of the interrupt continues until a
return from interrupt (RTI) instruction is processed. During RTI, the interrupt mask is cleared and the program
mode flags are selected. The next instruction of the program is then fetched and executed.
When STOP is processed, the interrupt mask is cleared
and the oscillator stopped. Checks are made for either
RESET or IRQ. If RESET is detected, the RESET sequence
is initiated. If IRQ is detected, the system oscillator is
enabled along with the clock. In both cases, a delay is
executed by the timer to al.low oscillator stabilization before the CPU is enabled and the interrupt serviced.
When WAIT is processed, the interrupt mask is cleared
and the CPU clock disabled. The interrupt latch is tested.
Detection of RESET initiates the RESET sequence. Detection of IRQ or timer interrupt enables the CPU clock and
initiates servicing of the interrupts.
When RTI is processed, the program counter is pulled
from the stack. The program flags are selected and the
interrupt mask cleared. The interrupt latch is then tested
before the next instruction.
When the interrupt was initially detected and the. interrupt sequence started, the interrupt request latch was
cleared so that the next interrupt could be detected. This
was done even as the first interrupt was being serviced.
However, even though the second interrupt set the interrupt request latch during the first interrupt's processing, the second interrupt's sequerice cannot begin until
completion of the interrupt service routine for the first
interrupt. Completion of an interrupt. service r()utine is
always accomplished using an RTI instruction to return
to the main program. The interrupt mask, which is not
directly available to the programmer, is cleared during
the last cycle of the RTI instruction.
EXTERNAL INTERRUPT EDGE/LEVEL-SENSITIVE OPTION
The edge/level~sensitive option performs as described
in the preceding section but adds the potential for levelsensitive operation. Level-sensitive operation tests the
state of the IRQ and initiates an interr'upt service routine
if the IRQ pin is found to be logic low.
.
.

MOTOROLA MICROPROCESSOR DATA
3-379

3
.

MC68HC04J3

External Interrupt Request Flow

Clear

y

Yes
N

II

N

High

Timer Interrupt
Request Flow

Figure 5. Interrupt· Sequences

POWER UP AND TIMING
During the power up sequence, the interrupt mask is
closed. This precludes any false interrupts. The PCis also
loaded with the appropriate restart vector(jumpinstruction).
Toopen the interrupt mask, the user should doa JSR
to an initialization subroutine that ends with an RTI instead of an RTS. The RTI opens the interrupt mask. Typical RESET and IRQ processes and their relationship to
the interrupt mask are shown in Figure 7.
Maximum interrupt response time is eight machine
cycles. This includes five cycles for the longest instruction
plus one for stacki'ng the PC and switch~flags. Two
additional cycles are used to synchronize IRQ input with
the internal machine cycle frequency.
TIMER INTERRUPT
A timer interrupt is requested by a transition of the
TMZ bit of the timer status/control register (TSCR) from
logic low to high. Such a positive transition is caused
either by the timer count register reaching the all zero
state, or by any program instruction thatwrites a one to
~eTMZb~
.

The timer interrupt request is maskable by clearing bit
6 of the TSCR (ETI bit). ETI is cleared by RESET.
During the interrupt routine, to determine whether an
interrupt was caused externally or by the timer, it is necessary to test the state of the TMZ bitIn the TSCR. .
It is important to service a timer interrupt and clear the
TMZ bit before the timer counter underflows again. Otherwise, because only a single interrupt can be latched,
there is no way oftelling how many timer interrupts occur
while the original interrupt is being serviced.

lOW-POWER MODES
STOP
The STOP instruction places the MCU in its lowest power
consumption mode. In the STOP mode, the internal oscillator is turned off,causing all internal processing and
the timer to be halted. Current consumption is thus
dropped to le(jkage levels.
Providing the supply voltage remains within data sheet
limits, the contents ofthe TSCR, accumulator, and all data
space RAM remain unchanged in STOP mode.

MOTOROLA MICROPROCESSOR DATA
3-380

Oscillator Active
Timer Clock Enable
CPU Clock Disable
$00- DDR's
Preset Timer

s:
o

d:JJ
o

~

w

W
~

s:

s:

:JJ

co

n

(")
0')

o"'tI
:JJ
o
(')

%

(")

eow

m
CJ)
CJ)

o
:JJ

e
C

CPU Clock Enable
SOO - DDR's
Set I Mask
Clear IRQ latch
SFF - TCR
$00- TSCR
Select Prgm Flags
Load Reset Vector
Into PC

%.9! !-;'::';";":":"':":"""...,.---l
~. ~ Select INT Flags

£

<.> Load INT ,,-_._Into PC

Figure 6. Instruction Processing Sequence

MC68HC04J3

JMP-START
VECTOR (FFE-FFF)

.................................................
START (ROUTINE)
INSTRUCTION (I-N)

I

INTERRUPT
MASK
CLOSED

LAST INSTRUCTION
JSR INIT

I

INIT
INITIALIZATION
SUBROUTINE

I

II

LAST INSTRUCTION
RTI

1

PROGRAM

MASK
OPEN

I
IRQ
RECOGNIZED

........................

I

IRQ
SERVICE
ROUTINE

INTERRUPT
MASK
CLOSED

I
LAST INSTRUCTION
RTI

PROGRAM

........................

I

MASK
OPEN

Figure 7. Interrupt Mask
~ausing

an interrupt or reset by pulling the RESET or
IRQ pins low is the only way to bring the processor out
of STOP mode. During this exit from STOP, the timer is
used to provide the-delay ti me necessary for the oscillator
to stabilize. So, the prescaler and timer count register
contents must be considered corrupted.

During the WAIT mode, external interrupts are enabled.
All other registers, memory, and 1/0 lines remain in their
last state. Pulling the IRQ or RESET pin to logic low causes
an exit from the WAIT mode. In addition, ETI bit of TSCR
can be enabled by software prior to entering the WAIT
state. This allows an exit from WAIT via a timer interrupt
as well as via external interrupts.

WAIT

The WAIT instruction places the MCU in a low power
consumption mode, but the WAIT mode consumes
somewhat more power than the STOP mode. In the WAIT
mode, the internal clock is disabled from all internal circuitry except for the timer. So, all internal processing is
halted. However, the timer continues to decrement normally if the PSI bit of TSCR is set.

TIMER
A block diagram of the MC68HC04J3 timer circuitry is
shown in Figure 8. The timer logic in the MCU is comprised of a simple 8-bit counter called the timer counter.
This counter is decremented by a 7-bit prescaler at a rate
determined by the timer statuslcontrol register (TSCR).

MOTOROLA: MICROPRo.CESSOR _DATA
3-382

MC68HC04J3

Microcomputer Internal Bus

3
TOUT
DOUT

Timer Status
Timer Pin TOUT DOUT

SYNC

Input
Output

°

°
1

° °

Timer Mode
Event Counter
Input Gated Mode
Output

1

Figure

8. Timer Block Diagram

PRESCALER
The prescaler is a 7-bit counter usedto extend the maximum interval ofthe overall timer. This counter is clocked
by a signal from the TIMER pin or by the. internal sync
pulse. It divides the frequency received by some factor
to create the prescaler output. The factor by which the
TIMER pin signal is divided is called the prescaler tap.
The value of this tap is selected by three bits of the TSCR
(PSO-PS2). These bits control the division of the prescaler
input within the range of divide-by-2 0 , to divide-by-27.

TIMER COUNTER
The timer counter, which may be read or loaded under
program control, is decremented from a maximum value
of 256 toward zero by the prescaler output. Both are decremented on rising clock edges.
The prescaler register and timer count register are
readable and writeable. A write to either one will take
precedence over the normal counter function. For example, if a value is written to the timer count register and
this write and a decrement-to-zero occur at the same
time, the write takes precedence and TSCR bit one (TMZ)
is not set until the next timer time out.

TIMER PIN
The TIMER pin may be programmed as either an input
or an output .. Its status depends on the value of TSCR
bits 4 (DOUT) and 5 (TOUT). Two distinct input modes
exist; input gated mode and input event counter mode.

This relationship is shown in the TIMER pin status section
of Figure 8. The frequency of the internal clock applied
to the TIMER. pin must be less than tbyte, which is the
frequency of the oscillator divided by either 12, 24, or 48,
then multiplied by the clock divide ratio. Whether fosc is
divided by 12, 24, or 48 is a manufacturing mask option.

TIMER INPUT EVENT COUNTER MODE
In the timer input event counter mode, both TOUT and
DOUT are logic zero. The TIMER pin is effectively connected directly to prescaler input. So, the timer/prescaler
is clocked by the signal applied from the TIMER pin.

TIMER INPUT GATED MODE
In the input gated mode, TOUT is logic zero and DOUT
is logic one. The timer pin is an input which decrements
the prescaler each machine cycle as long as the timer pin
is logic high. When the pin is logic low, counting is inhibited. This mode permits the counting of the period of
time during which the timer pin is logic high, based on
the system clock and prescaler values. Gate times are
fosc/12, fosc/24, and f ocs /48.

TIMER OUTPUT MODE
In the output mode, TOUT is logic one and the TIMER
pin is connected to the DOUT latch. So, the timer prescaler is clocked by the internal sync pulse. This pulse is
a divide-by-12, 24 or 48 of the internal oscillator depending on the mask option. However, in the output mode,
once the prescaler decrements the timer count register

MOTOROLA MICROPROCESSOR DATA

3-383

I

MC68HC04J3

to zero, the low TSCR bit 1 (TMZ) bit state is used to drive
the data latched at TSCR bit 4 (DOUT) onto the TIMER
pin.
NOTE
TMZ is normally set to logic one when TCR decrements to zero and the timer times out. However,
it may be set by a write of $00 to TCR or by a' write
to bit 7 of TSCR.

It is recommended that MVI or loading and storing
instructions be used when changing bit values in the
TSCR. Read-modify-write instructions can cause the TMZ
to assume an unexpected state.
During reset, the TSCR is set to all zeroes. The TIMER
pin is in the high impedance input mode; and DOUT
LATCH is forced to a logic high. At the same time, PSOPS2 coding sets the prescaler tap at divide-by-one, and
bit 3 initializes theprescaler.

TIMER COUNT REGISTER ($FE)

The timer count register reflects the current count in
the internal 8-bit counter. The register is the counter and
can be written.
7

I

MSB

LSB

The timer prescaler register reflects the current count
oftre 7-bit prescaler. This register is the prescaler counter
and can be written.
6

I MSB

RESET:
1

I

TIMER PRESCALER REGISTER ($FD)

LSB

RESET:
1

TIMER STATUS/CONTROL REGISTER (TSCR) ($09)
7

6

5

4

3

I TMZ I

ETI

TOUT

I DOUT I

PST

PS2

PSI

INSTRUCTION SET

PSO

RESET:

o
TMZ -

Timer Zero
1 = Timer count register has reached the all-zero
state since the last time the TMZ bit was read.
a= This bit is cleared by a read of the TSCR if TMZ
is read as logic one.
ETI- Enable Timer Interrupt
1 = Timer interrupt enabled.
a= Timer interrupt disabled.
TOUT - Timer Output
1 = Output mode is selected for the timer.
0= Input modes are selected for the timer.
DOUT - Data OutpLit
In the input mode, latched data at this bit is sent to
the TIMER pin when both ,the TMZ and TOUT bits
are logic high.
In the input mode:
1 = Tim~r input gated mode is selected
0= Timer input eventcounter mode is selected
PSI- Prescaler Initialization
1 = Prescaler begins to decrement.
0= Prescaler is initialized and counting is inhibited.
PSO-PS2
These bits are used to select the prescaler tap. The
coding of the bits is shown below:

The MCU has a set of 42 basic instructions. They can
be divided into five different types: register/memory, read/
modify/write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.
REGISTER/MEMORY INSTRUCTIONS

Most of these instructions use two operands. One operand is the accumulator; the other is obtained from
memory using one of the addressing modes. Refe~ to the
following list of instructions.
Function

Mnemonic

Load A from Memory

LDA

Load XP from Memory

LDX

Load YP from Memory

LDY

Store A in Memory

STA

Add to A

ADD

Subtract from A

SUB

AND Memory to A

AND

Transfe'r A to XP

TAX

Transfer A to YP

TAY

Transfer YP to A

TYA

PS2

PS1

PSO

0

0

0

1

Clear A

CLRA

0

0

1

2

Clear XP

CLRX

0

1

0

4

Clear YP

0

1

1

8

Complement A

COMA

Divide By

Transfer XP to A

TPA

CLRY

1

' 0

0

16

Rotate A Left and Carry

ROLA

1

,0

1

32

Arithmetic Compare with Memory

CMP

1

1

0

64,

Move Immediate Value to Memory

1

1

1

·128

Arithmetic Left Shift of A

MOTOROLA MICROPROCESSOR DATA
3-384

MVI
ASLA

MC68HC04J3

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. All INC and DEC
forms along with all bit manipulation instructions use this
method. Refer to the following list of instructions.
Function

CONTROL INSTRUCTIONS
These instructions are used to control processor operation during program execution. The jump conditional
(JMP) and jump to subroutine (JSR) instructions have no
register operand. Refer to the following list of instructions.

Mnemonic

Increment Memory Location

Mnemonic

Function
Return from Subroutine

INC

RTS

Increment A

INCA

Return from Interrupt

RTI

Increment XP

INCX

No Operation

NOP

Increment YP

INCY

Jump to Subroutine

JSR

Decrement Memory Location

DEC

Jump Unconditional

JMP

Decrement A

DECA

Stop

STOP

Decrement XP

DECX

Wait

WAIT

Decrement YP

DECY

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list of instructions.
Function

Mnemonic

Branch if Carry Clear

BCC
(BHS)

Branch if Higher or Same
Branch if Carry Set

BCS
(BLO)

Branch if Lower

BNE

Branch if Not Equal
Branch if Equal

BEQ

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the 256 bytes of the memory space, where all
port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear, and bit test and
branch functions are all implemented with a single instruction. For the test and branch instructions, the value
of the bit tested is also placed in the carry bit of the
condition code register. Refer to the following list of instructions.
Function

Mnemonic

Branch If Bit n is Set

BRSET n(n =0 ... 7)

Branch If Bit n is Clear

BRCLR n(n = 0 ... 7)

Set Bit n

BSET n(n=O ... 7)

Clear Bit n

BCLR n(n=O ... 7)

IMPLIED INSTRUCTIONS
Since the accumulator and all other registers are located in RAM, many implied instructions exist. Some of
the instructions recognized and translated by the assembler are shown below:
Mnemonic

Becomes

Mnemonic

Becomes

ASLA

ADD $FF

INCX

INC $80

BHS

BCC

INCY

INC $81

BLO

BCS

LDXI

MVI $80 DATA

CLRA

SUB $FF

LOYI

MVI $81 DATA

CLRX

MVI $80 #0

NOP

BEQ (PC) + 1

CLRY

MVI $81 #0

TAX

STA $80

DECA

DEC $FF

TAY

STA $81

DECX

DEC $80

TXA

LDA $80

DECY

DEC $81

TYA

LDA $81

INCA

INC $FF

Some examples of valuable instructions not specifically recognized by the assembler are shown below:
Mnemonic

Meaning

BCLR 7,$FF

Ensures A is plus

BSET 7, $FF

Ensures A is minus

BRCLR 7, $FF

Branch if A is plus

BRSET 7, $FF

Branch if A is minus

BRCLR 7, $80

Branch if X is plus (BXPL)

BRSET 7, $80

Branch if X is minus (BXMI)

BRCLR 7, $81

Branch if Y is plus (BYPL)

BRSET 7, $81

Branch if Y is minus (BYMI)

OPCODE MAP
Table 1 is a listing of all the instruction set opcodes
applicable to the MC68HC04J3 MCU.

MOTOROLA MICROPROCESSOR DATA

3-385

II

Table 1. Opcode Map

•
Bit Manipulation
Instructions

Register/Memory, Control, and
Read/Modify/Write Instructions

Branch Instructions

~---.r.
Low-.............

Register I Memory and

Readl Modify/Write

A

Hi ~
~L~

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

BEQ

BEG

BCC

BCC

BCS

BCS

JSRn

JMPn

BNE

BNE

BEQ

BEQ

BCC

Bce

BCS

BCS

JSRn

JMPn

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

RTS

BRCLR3

BCLR3

SUB

SUB

BNE

BNE

BEQ

BEQ

Bce

BCC

BCS

Bes

JSRn

JMPn

COMA

BRCLR4

BCLR4

CMP

CMP

BNE

BNE

BEQ

BEG

Bce

Bce

Bes

BCS

JSRn

JMPn

ROLA

I

BRCLR5

BCLR5

AND

AND

BNE

BNE

BEQ

BEQ

Bce

BCC

BCS

BCS

JSRn

JMPn

STOP

I

BRCLR6

BCLR6

INC

INC

JMPn

BRCLR7

BCLR7

DEC

DEC

JMPn

13

BRSETO

BSETO

LOA

LOA

I

BRSETl

BSETl

MVI

RTI

BRCLRO

BCLRO

LOA

LOA

BRCLRl

BCLRl

STA

STA

BRCLR2

B_CLR2
8scli

ADD

ADD

3:

01(lO

a
o
:zJ

_I]

!j;
3:

n

w

:zJ

I

:zJ

w o"'a
oo

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

BNE

8NE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

WAI!...
INC

JMPn

INC

I]

~

DEC

SO

DEC

,

(")
0)

OQ

:::J:

STA

e
(")

A

m
t/)

t/)

o:zJ

~

,

o

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

INC

DEC

I

BRSET2

BSET2

ADD

ADD

BNE

BNE

BEQ

BEQ

BCC

Bce

BCS

BCS

JSRn

JMPn

INC

DEC

I

BASETJ

BSET3

SUB

SUB

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

Bes

JSRn

JMPn

LOA

STA

I

BRSET4

BSET4

CMP

CMP

BNE

BNE

BEQ

BEQ

Bec

Bce

BCS

BCS

JSRn

JMPn

LOA

STA

I'

BRSET5

BSET5

AND

AND

5013

B

B

I]

w

BNE

BNE

BEQ

BEQ

BCC

BCC

BCS

BCS

JRSn

JMPn

LOA

STA

BRSET6

BSET6

INC

BNE

BNE

BEO-

BEQ

BCC

BCC

BCS

BCS

JSRn

JMPn

LOA

STA

BRSETl

BSETl

DEC

Abbreviations for Address Modes
INH
S·D
B·T·B
IMM
DIR
EXT
REl
BSC
R:INC

T

Inherent
Short Direct
Bit Test and Branch
Immediate
Direct
Extended
Retative
Bit Set! Clear
Register Indirect

A

LEGEND
Indicates Instruction Reserved for Future Use
Indicates Illegal Instruction

",,~~.

Mne~~~~~

1 •

LOA

d-:?:1
~

Opcode in Binary

MC68HC04J3

ADDRESSING MODES
The MCU has nine different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. It deals with objects in three different address spaces: program space, data space, and
stack space. The term "effective address" (EA) is used in
describing the various addressing modes. Effective address is defined as the address from which the argument
for an instruction is fetched or stored.

IMMEDIATE
In the immediate addressing mode, the operand is located in program ROM. It is contained in the byte immediately following the opcode. The immediate
addressing mode is used to access constants that do not
change during program execution, such as a constant
used to initialize a loop counter.

DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the 256 bytes in memory with a single two-byte
instruction.
SHORT DIRECT
In the short direct addressing mode, the MCU has four
locations in data space RAM which it can use, ($80, $81,
$82, and $83). The opcode determines the data space
RAM location, and the instruction is only one byte. Short
direct addressing isa subset of the direct addressing
mode. The X and Y registers are at locations $80 and $81,
respectively.
EXTENDED
In the extended addressing mode, the effective address
of the argument is obtained by concatenating the four
least-significant bits ofthe opcode with the byte following
the opcode to form a 12-bit address ..Instructions using
the extended addressing mode, such as JMP or JSR, are
capable of branching anywhere in program space. An
extended addressing mode instruction is two bytes long.
RELATIVE
The relative addressing mode is only used in conditional branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the
opcode is added to the PC if, and only if, the branch
conditions are true. Otherwise, control proceeds to the
next instruction. The span of relative addressing is from

-15 to + 16 from the opcode address. The programmer
need not calculate the offset when using the Motorola
assembler, since it calculates the proper offset and checks
to see that.it is within the span of the branch.

BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte in which
the specified bit is to be set or cleared. Thus, any bit in
the 256 locations of data space memory that can be written to can be set or cleared with a single two-byte instruction.

CAUTION
The corresponding DDRs for ports A and B are write
only registers (registers at $04, $05). A read operation on these registers is undefined. Since BSET
and BCLR are read-modify-write functions, they
cannot be used to set or clear a DDR bit; all "unaffected" bits would be set. Write all DDR bits in a
port using a single-store instruction.

BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear) is
included in the opcode. The data space address of the
byte to be tested is in the single byte immediately following the opcode byte. The third byte is sign extended
to twelve bits and becomes the offset added to the PC if
the condition is true. This single three-byte instruction
allows the program to branch based on the condition of
any readable bit in the 256 locations of memory. The span
of branching is from -125 to + 130· from the opcode
address. The state of the tested bit is also transferred to
the carry flag.
REGISTER-INDIRECT
In the register-indirect addressing mode, the operand
is at the address in data space pointed to by the contents
of one of the indirect registers, X or Y. The particular
indirect register is selected by bit 4 of the opcode. Bit 4
decodes into an address that represents the register, $80
or $81. A register-indirect instruction is one byte long.
INHERENT
In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. These instructions are one byte long.

MotOROLA MICROPROCESSOR DATA

3·387,

II

MC68HC04J3

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VDD

-0.3 to + 7.0

V

Input Voltage

Vin

to
VSS-0.3
VDD+0.3

V

I

10

rnA

I
I

30
15

rnA

Rating

Current Drain per Pin
Excluding VDD and VSS
Total Current for
Ports A. B, C EXTAl, TIM

Sink
Source

Operating Temperature Range (Comm.)

TA

o to 70

°C

Operating Temperature Range (Ind.)

TA

-40 to +85

°C

Tst~

-55 to + 150

°C

Storage Temperature Range
Junction Temperature
Plastic

II

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields. However, it is advised that normal precautions be taken to avoid applications of
any voltage higher than maximum-rated voltages
to this hign-impedance circuit. For proper operation itis recommended that Vin and Vout be constrained to the range VSS""(Vin)",,VDD. Reliability
of operation is enhanced if unused inputs except
EXTAl are connected to an appropriate logic voltage level (e.g., either VSS or VCC).

°C

TJ
150

THERMAL CHARACTERISTICS
Characteristic

Symbol

Thermal Resistance
Plastic

Value

Unit

°CIW

6JA
70

POWER CONSIDERATIONS

The average chip-junction temperature, T j, in °C can
be obtained from:
Tj=TA+(POOejA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
eJA
Junction-to-Ambient, °CIW
Po
= PINT+ PPORT
= ICC x VCC' Watts - Chip Internal Power
PINT
PPORT = Port Power Oissipation,
Watts - User Oetermined

For most applications PPORT
2
RESONATOR,
OR RC

5VOLTSq
2

RESET~
2

ANDMODE~
lJJ'

INTERRUPT

II

TIMER INPUT OR
TIMER OUTPUT

--- -

OSCILLATOR'

M6ilHC04
FAMILY
PROCESSOR

POWER

r-

CQNTROL

EXTERNAL
INTERRUPT

124 BYTES
RAM

3740 BYTES
USER PROGRAM
'OTPROM
EPROM

BIDIRECTIONAL
1/0 PORT
PINS

72 BYTES DATA
OTPROM
EPROM
8-BIT
TIMER
356 BYTES
BOOTSTRAP
ROM

MOTOROLA MICROPROCESSOR DATA

3.. 396

BIDIRECTIONAL
110 PINS

MOTOROLA

.SEMICONDUCTOR . . . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC6805P2

Technical Summary

8-Bit Microcomputer Unit
The MC68D5P2 (HMOS) Microcomputer Unit (MCU) is a member of the MC68D5 Family of microcomputers. This low cost and high speed MCU has parallel I/O capability with pins programmable
as input or output. This publication contains condensed information on the MCU; for detailed information, refer to M6805 HMOS, M146805 CMOS Family User's Manual (M68D5UM(AD2)) or contact
your local Motorola sales office.
Refer to the block diagram for the hardware features and to the below list for additional fea.tures
available on the MCU.
'
•
•
•
•
•
•

Internal 8-Bit Timer with 7-Bit Programmable Prescaler
On-chip Oscillator
Memory Mapped I/O
Versatile Interrupt Handling
True Bit Manipulation
Bit Test and Branch Instruction

•

20. I/O Ports

•
•
•
•
•
•

Vectored Interrupts
64 Bytes RAM
Low Voltage Inhibit Option
Self-Check Mode
Master Reset
11 DO. Bytes ROM

II

BLOCK DIAGRAM

TIMER

Accumulator
8

PAO
PAl
Port PA2
A
PA3
lID PA4
Lines PA5
PA6
PA7

8
Port
A
Reg.

Index
Register

5

Data
Dir.
Reg.

Port
B
Reg.

PBO
PBl
PB2 Port
PB3
B
PB4 lID
PB5 Lines
PB6
PB7

CPU

Stack
Pointer

3

SP
Program
Counter
High PCH

8

Program
Counter
low PCl

11OOx8
User ROM

CPU
Control

X

Condition
Code
Register CC

Data
Dir.
Reg.

116 X 8 Self"
Check ROM

A

AlU

MOTOROLA MICROPROCESSOR DATA
3-397

PCO Port
PCl
C
PC2 lID
PC3 Lines

MC6805P2

SIGNAL DESCRIPTION

upon selected manufacturing mask options) is connected
to these pins to provide a system clock.

VCCAND VSS

RC Oscillator
With this option, a resistor is connected to the oscillator
pins as shown in Figure 1. The relationship between R'
and fosc is shown in Figure 2.

Power is supplied to the microcomputer using these
two pins. VCC is + 5.25 volts (± 0.56.) power, and VSS is
ground.
INT

Crystal
The circuit shown in Figure 1 is recommended when
using a crystal. Using an external CMOS oscillator is recommended when crystals outside the specified ranges
are to be used. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. Refer to ELECTRICAL SPECIFICATIONS for VCC
specifications.

This pin provides the capability for asynchronouslyapplying an external interrupt to the MCU. Refer to INTERRUPTS for additional information.
NUM (Non-User Model

This pin is not for user applications and must be connected to VSS.
EXTAL,XTAL

II

External Clock
An external clock should be applied to the EXTAL input
with the XTAL input connected to ground, as shown in
Figure 1.

These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a ceramic resonator, a resistor!
capacitor combination, or an external signal (depending

~XTAL

5 XTAL
MCU

CJ

External
Clock
Input

4 EXTAL

MCU
4 EXTAL

Crystal
Approximately 25% to 50% Accuracy
Typical tcyc= '.25/Ls
External Jumper
Crystal Parameters

EXTAL
4

External Clock

C,

-e
L,

~XTAL

CE---------J

5

R

MCU

AT - Cut Parallel Resonance Crystal
Co =7 pF Max.
Freq=4.0 MHz@CL=24pF
RS=50 ohms Max.
Approximately '0% to 25% Accuracy
(Excludes Resistor Tolerance)
External Resistor

Piezoelectric ceramic resonators which
have the equivalent specifications may be
used instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO. C" and RS values.

NOTE: The recommended CL value with a 4.0 MHz crystal is 27 pF maximum including system distributed capacitance. There is an
internal capacitance of approximately 25 pF on the XTAL pin. For crystal frequencies other than 4 MHz, the total capacitance
on each pin should be scaled as the inverse of the frequence ratio. For example, with a 2 MHz crystal, use approximately
50 pF on EXTAL and approximately 25 pF on XTAL. The exact value depends on the motional-arm parameters of the crystal
used.

Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR DATA
3-398

MC6805P2

is an output (1). Refer to Table 1 for I/O functions and to
Figure 3 for typical port circuitry.

8.0
70

:i:

~

Table 1. I/O Pin Functions

6.0

VCC=5.25 V
T A = 25°C

>

c 5.0
~
40

u

f

30

Ju

20

0

Data
Direction
Register
Bit

Output
Data
Bit

Output
State

Input
To
MCU

1
1
0

0
1
X

0
1
Hi-Z

0
1
Pin

1.0
0

0

10

20

30

40

50

60

70

80

MEMORY

Resistance (kOi

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option only

TIMER
This pin can be used as an external input to control the
internal timer/counter circuitry or gating <1>2 input to timer,
depending on mask option.

The MCU is capable of addressing 2048 bytes of memory and I/O registers. The memory map is shown in Figure
4. The locations consist of 1092 bytes of user ROM, selfcheck ROM, user RAM, a timer control register, and I/O.
The user interrupt vectors are located from $7F8 to $7FF.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.

RESET

NOTE

This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low.
INPUT/OUTPUT LINES (PAO-PA7, PBO·PB7, PCO·PC3)
These 20 lines are arranged into two 8-bit ports (A and
B) and one 4-bit port (C). Ports A, B, and C are programmable as either inputs or outputs under software control
of the data direction registers. Refer to PROGRAMMING
for additional information.

Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

REGISTERS
The MCU contains the registers described in the following paragraphs.
ACCUMUL.ATOR tA)
The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING

7

Any port pin is programmable as either input or output
under software control of the corresponding data direction register (DDR). The port I/O programming is accomplished by writing the corresponding bit in the port DDR
to a logic 1 for output and a logic 0 for input. On reset,
all the DDRs are initialized to a logic 0 state to put the
ports in the input mode. The port output registers are not
initialized on reset and should be written to before setting
the DDR bits.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This may be used to initialize the data
registers and avoid undefined outputs. Care must be exercised when using read-modify-write instructions since
the data read corresponds to the pin level if the DDR is
an input (0) and also to the latched output when the DDR

A

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may be added to an 8- or 16-bit immediate value to create
an effective address. The index register may also be used
as a temporary storage area.
7

I

PROGRAM COUNTER (PC)
. The program counter is an 11-bit register that contains
the address of the next byte to be fetched.
10

8 7

PCH

MOTOROLA MICROPROCESSOR DATA
3-399

0

X

pel

II

MC6805P2

Data
Direction Register t---4I.__-------~.__---Bit*

....

Latched
Output
Data
Bit

* DDR

II

is a write-only register and reads as all "15".

PORT DATA REGISTER

7

PORT DATA DIRECTION REGISTER IDDR)

o

7

o

(1) Write Only; reads as all "1s"
(2) 1 = Output; 0 ... Input. Cleared to 0 by reset.
(3) Port A Addr = $004
Port B Addr= $005
Port C Addr= $006 (Bits 0-3)

Port A Addr = $000
Port B Addr = $001
Port C Addr=$OO2 (Bits 0-3)

Figure 3. Typical Port I/O Circuitry and
Register Configuration

STACK POINTER (SP)

Half Carry (H)

The stack pointer is an 11-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
The six most-significant bits of the stack pointer are
permanently set at 000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to15
levels of subroutine calls (less if interrupts are allowed).

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

10

5 4

I 0 I0 I0 I0 I1 I1 I

0
SP

Interrupt (I)

When this bit is set, the timer and external interrupt is
masked (disabled). If an external interrupt occurs while
this bit is set, the interrupt is latched and is processed as
soon as tile interrupt bit is cleared.
Negative (N)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative
(bit 7 in the result is a logic 1).
Zero (Z)

CONDITION CODE REGISTER (CC)

The condition code register is a 5-bit register in which
four bits are used to indicate the results ofthe instruction
just executed. These bits can be individually tested by a
program, and specifications can be taken as a result of
their state. Each bit is explained in the following paragraphs.

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.
Carry/Borrow (e)

When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and during shifts and
rotates.

MOTOROLA MICROPROCESSOR DATA
3-400

MC6805P2

o
000
Page Zero
Access with
Short
Instructions

127

128

$07F
$080

~FF

Page Zero
User ROM
(128 Bytes)

255

256

$100

Not Used
(704 Bytes)

959
960

76543210

$000

I/O Ports
Timer
RAM
(128 Bytes)

$3BF
$3CO

Main User
ROM
(964 Bytes)
1923
1924

Self Check
ROM
(116 Bytes)

2039

Interrupt
Vectors

$783
$784

PortA

1

Port B

2

$000
$001
PortC

1 1 1 11

$002

Not Used

$003

4

Port A DDR

$004-

5

Port B DDR

$005-

6

I

3

Not Used

Port C DDR $006-

Not Used

$007

8

Timer Data Reg

$2 is used timer input should be tied to VCC. If
low, it will gate <1>2 off.

la) Zero-Crossing Interrupt

Ib) Digital-Signal Interrupt

Vec
I:pc
ut

TTL

,ICurrent

Max,)~'mltmg).

IflNT
Rs1 MO
aclnputs
10 Vac pop

R

2

iNT

MCU

4.7 k

Level
2
Digital--__~
Input

0.1-1.0
I'F

lJ
Figure 9. Typical Interrupt Circuits

MOTOROLA MICROPROCESSOR DATA
3-404

iNT
MCU

MC6805P2

Timer
Timer
TIMER
Input

Pin
r------'j
I
I
I
I

bO

I
I
I
I

L______ !

Timer Control Register nCR)

Manufacturing
M3Sk

Options

Write

Read

Write

Read

Internal Data Bus

Figure 10. Timer Block Diagram

TIMER CONTROL REGISTER (TCR) $009

This 8-bit register controls timer interrupt request and
inhibit signals.
7

I

TIR

jump to subroutine (JSR) instructions have no register
operand. Refer to the following list of instructions.
Function

6

I

TIM

Mnemonic

Load A from Memory

LDA

Load X from Memory

LDX

Store A in Memory

STA

RESET:

o

u

u

u

u

TIR - Timer Interrupt Request
Used to indicate the timer interrupt when it is logic
one
1 = Set when the timer data register changes to all
zeros
0= Cleared by external reset, power-on reset, or
under program control
TIM - Timer Interrupt Mask
Used to inhibit the timer interrupt
1 = Interrupt inhibited
0= Interrupt enabled
Bits 5 through 0
Not used

REGISTER/MEMORY INSTRUCTIONS

Most of these instructions use two operands. One operand is eitnerthe accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and

STX

Add Memory to A

ADD

Add Memory and Carry to A

ADC

Subtract Memory

SUB

Subtract Memory from A with Borrow

SBC

AND Memory to A

AND

OR Memory with A

ORA

Exclusive OR Memory with A

EOR

Arithmetic Compare A with Memory

CMP

Arithmetic Compare X with Memory

CPX

Bit Test Memory with A (Logical Compare)

INSTRUCTION SET
The MCU has a set of 59 basic instructions. They can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

Store X in Memory

BIT

Jump Unconditional

JMP

Jump to Subroutine

JSR

BIT MANIPULATION INSTRUCTIONS

The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space, where
all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear and bit test, and
branch functions are all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the carry bit of the condition

MOTOROLA'MICROP.ROCESSOR DATA
3-405

I

MC6805P2

code register. Refer to the following list for bit manipulation instructions.
Function

Mnemonic

Mnemonic

BHCC

Branch if Half Carry Set

BHCS

Branch if Bit n is Set

BRSETn (n=O ... 7)

Branch if Plus

BPL

Branch if Bit n is Clear .

BRCLR n (n=O ... 7)

Branch if Minus

BMI

Set Bit n

BSET n (n=O ... 7)

Branch if Interrupt Mask Bit is Clear

BMC

Clear Bit n

BCLR n (n=O ... 7)

Branch if Interrupt Mask Bit is Set

BMS

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.

I

Function

Branch if Half Carry Clear

Mnemonic

Function

Branch if Interrupt Line is Low

BIL

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

CONTROL INSTRUCTIONS
These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.

Increment

INC

Decrement

DEC

Clear

CLR

Transfer A to X

TAX

Complement

COM

Transfer X to A

TXA

Negate (2's Complement)

NEG

Set Carry Bit

SEC

Rotate Left Thru Carry

ROL

Clear Carry Bit

CLC

Rotate Right Thru Carry

ROR

Set Interrupt Mask Bit

SEI

Logical Shift Left

LSL

Clear Interrupt Mask Bit

CLI

Logical Shift Right

LSR

Software Interrupt

SWI

Arithmetic Shift Right

ASR

Return from Subroutine

RTS

Test for Negative or Zero

TST

Return from Interrupt

RTI

Reset Stack Pointer

RSP

Function

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list for branch instructions.
Function

NOP

_~o-Operation

OPCODE MAP SUMMARY
Table 3 is an opcode map for the instructions used on
the MCU.

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

Branch if Carry Clear
(Branch if Higher or Same)

Mnemonic

ADDRESSING MODES
The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses .aresingle byte
instructions, while the longest instructions (three bytes)
permit accessing tabl.es throughout memory. Short and
long absolute addressing is also included. Two byte direct addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions to reach all memory.

BCC
(BHS)

'.

Branch if Carry Set

BCS
(BLO)

(Branch if Lower)
Branch if Not Equal

BNE

Branch if'Equal

BEQ
-

Continued -

MOTOROLA MICROPROCESSOR DATA
3':406

Table 3. Opcode Map

Bit Manipulation
BS(
BTB

Low
~

~
1
0001

2
0010

3
0011

4
0100

3:

g
~
w

5
0101

6
0110

7
0111

~

1000

3:

9

n::J:I

o
~
..... "'0
::J:I
o(")
m

fA
fA

8

1001

l~O
B
1011

i

3-STB

lfoo_
1

Po,

1110

C

F

E

1111

Branch
REl

OIR

INH

J,o

OO~,

O~

4

2

BSE~~c

2

BRA
REL

6

2

NEG
OIR

4

1

Read-Modify:Write
INH
IXI

NEG
INH

4

O'~'

·7

1

NEG
INH

2

Control

01~0
NEG

IXI

IX

INH

INH

O'~'

,000

8

9

6
' NEG
IX
I

RTI
1

7

4

6

2 BCL~~c

2 BRN
REL

1

10

7

4

10

BRSETI
3
BTB

2

10

7

BRCLRI
3
BTB . 2
10

7

BRSET2
3
BTB

2

10

7

BRCL
'2
3
:ls
10

7

rSE~A

2

BSE~~c

7

4

4

BCL~~c

6

COMA
1
INH

COM X
1
INH

2 COM
IXI

I

4

4

7

BSE~~c

6

_2 BCC~H
4
2 BCS
REI
4

COM
2
OIR
6
2. LSR
OTR

4

2

BNE~L

10

7

BRCL
3
:ls

2

10

7

4

2 BSE1~c

7

10

7

4

BRCLR4
3
STS

2 BCL~~c

BHCS
2
REL

'2.

7

4

BRSEJ;'..

,BRSEJle
'0

BRCLR5
STB
3

4

BCL~~c

..2..BSE~

BEO

..Bll

2

_2

BHC~

BPL
RFI

7

4

BCLR5
2
sse

BMI
REL
2

2

10

7

BRCL
3
:fs

2

10

7

BSE~~c

2

BMC
REL

4

BCL~~c

12

2 BMS
AEL

1

LSRA
INH

1

7

LSRX
INH

LSA

2

IXI

I

COM
LSA

IX

4

4

7

RORA
1
INH

ROAX
1
INH

2 AOR

12
2

SWI
1
INH

IX

4

4

7

ASRA
INH

ASRX
INH

ROA
2

6

ASA

2

IXI

4

1
4

LSLA
1
INH

LSLX
.1
1
INH

4

4

ROLA
1
INH

ROLX
1
INH

2

4

4

7

DECA
INH
1

DEC X
1
INH

DECIXI
2

1

IX

1

7

ASA
1

I

IX

IXI

7

LSL
1

CLC
INH

IX

2

6
ROL

IXI

AOL
1

IX

I
2.

6

I

DEC

IX

I
i

2
6

4

INC

OIA

1
4

TST
2

OIA

1

·7

4

INCA
'NH
TSTA
INH

1
4
1

INCX
INH

2

6
INC

IXI

7

TSTX
INH

INC
IX

1

rST

l
1

INH

1

IX

1

1

NOP
INH

BSE~1c

rSEJls

2

10

7

BRCLR7
BTB
3

BClR7
2
ssc

2
BIH
2

REL

4

AND
IMM

6

4

4

CLR
OIA
2

CLRA
INH
1

CLRX
INH
1

6

7

(LR

BIT
IMM

2.

IXI

1

IX

I

Inherent
Immediate
D.irect
Extended
Relatiye
Bit Set/Clear
Bit Test and Branch
Indexed (No Offset}
Indexed. 1 Byte (B-Bit} Offset
Indexed, 2 Byte (16-Bit} Offset

Mnemonic
Bytes

CMP
IX2

3

6 SBC
IX2
3
6
3 CPX
,X2
6
AND
3
IX2
6

•

~

CMP
IX

I
000'

IX

00,0

IX

rJ"

IX

0100

4

CMP
IXI

I

' 'SBC
2
IX'

•

,

SBC

, CPX
2
IXI
5
2 AND
IX
5

•

CPX

2

1
4

,

o ORA
3
IX2

' ORA
2
IXI

•

,

ORA

ADD
OIR
2
3
JMP
OIA
2.

" ADD
EXT
3

6 ADD
IX2
3

' ADD
IXI
2

•

ADD

JMP
EXT

, JMP
3
IX2

• JMP
IXI
2

•

8 JSR
3
EXT

9 JSR
IX2
3

8 JSR
IXI
2

7
1

JSR

6 lOX
' LOX
IXI
3
IX2 _.2.

•

lOX

"

STX

ADC
OIA
2
4

4

7

JSR

2

OIA

4

3

4
2.

'" LOX
LOX
OIA 3
EXT

,6 STX
5 STX
EXT
OIA 3
2

IX2

3

STA
2'
IX'
5
EOR
2
IX'
5
ADC
IXI
2

ti

STX

2

~

SUB IX

" ORA
EXT
3

4

ADC
2
IMM
2
ORA
IMM
2

STX
IX,

AND

4

BIT IX

,
4

,

'

IX

O'~,

IX

,000

IX

'100'

STA
EOR
ADC

1

1

JMP

1

1
1

01~'
o~o.

4
1
4

4

IX

LOA
1

2

8

9
A

IX

,010

IX

B
101,

IX

1100

IX

"0,

IX

'''0

IX

""

C

0
E

F

LEGEND

j
/o'C"",

,X1

ORA
OIA
2

6

EOR
OIR
2

2

TXA
INH

SUB

5

6
CMP
EXT

~

6

4

BSR
REL

IX2

3 STA
,X2
6
3 EOR .2..
IX
6
ADC
3
IX2

2.
7

ADD
IMM
2

SUB

STA
EXT
3
5
3 EOR
EXT
5
ADC
EXT
3

OIR

LOA
DIR
2
5
STA
DIR
2

EOR
IMM

:

3 BIT IX2 2 BIT IX,
6
5
3 LDA
.2. lOA
IXI
IX2

BIT

2
4

LOA
IMM
2

2
CLR

SUB
EXT

IX

,f"

5 AND
EXT
3
5
3 BIT
EXT
5
LOA
EXT
3

AND
OIR
2

1

2
2

"~O

,g,

" SBC
EXT
3
5
CPX
EXT
3

4

LOX
IMM
2

REL

4

3

SBC
DIR
2

2

B

BIL

IXI

1faa

5
CMP
DIR

CPX
OIR
2

RSP
INH

4

2

4

I'

SEI

Abbreviations for.Address Modes
INH
IMM
DIR.
EXT
REL
BSC
BTB
IX
IX1
IX2

INH

·2
TST

IXI

CLI

:

Regiaer I Memory
EX
1X2

4

SBC
IMM

2

6

2

SEC
INH

SUB
OIR

4
lMM

TAX
INH

2.

6

LSL

:

CPX
IMM
2

2
2

6

IXI

SUB
IMM
CMP

11

6

OIR
B
,011

2
2
2

lNH

,2

6
2 ROR
OIR
6
ASR
2
OIR
6
2 LSL
OIR
6
ROL
2
OIA
6
2 DEC
OIA

6

4

BRS
3
EJfs

I'
INH

BHIREI

BLS
2
R

BSE~~c

'00,

RTS

4

BCL~~c

IMM
A
10'0

9

BRClRO
STB
3

1~

o::J:I

~

~
'~RSETO

~,

lr.l~

~

4

.1

IX

~;"H~m.
Opcode in Binary

(lXX) ......--

,

Address Mode

3:

(")
G)

CO

o

U'I

"V
N

MC6805P2

II

The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

tables may begin anywhere within the first 256 addressabl.e locations and could extend as far as location 510
($1 FE is the last location at which the instruction may
be.gin):

IMMEDIATE

INDEXED, 16-BIT OFFSET

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).

In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents ofthe unsigned
8-bitindex register and the two unsigned bytes following
the opcode. This addressing mode can be used in a manner similar to indexed, 8-bit offset except that this 3-byte
instruction allows tables to be anywhere in memory.

DIRECT

BIT SET/CLEAR

In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.

In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte to which
the specified bit is to be set or cleared. Any read/write
bit in the first 256 locations of memory, including I/O, can
be selectively set or cleared with a single 2-byte instruction.

EXTENDED

In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction.
RELATIVE

The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from -126 to + 129 from
the opcode address.
INDEX, NO OFFSET

In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or to hold the address of a frequently referenced
RAM or I/O location.

CAUTION

The corresponding DDRs for ports, A, B, and Care
write only registers (registers at $004, $005, and
$006). A read operation on these registers always
returns a "1". Since BSET and BCLR are read-modify-write functions, these instructions cannot be used
to set or clear a DDR bit (all "unaffected" bits would
be set). It is recommended that all DDR bits in a
port be written using a single-store instruction.
BIT TEST and BRANCH

The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear) is
included in the opcode. The address of the byte to be
tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third
byte is added to the PC if the specified bit is set or cleared
in the specified memory location. This single 3-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of
memory. The span of branching is from -125 to + 130
from the opcode address. The state of the tested bit is
also transferred to the carry bit of the condition code
register.

INDEXED, 8-BIT OFFSET

In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an 11 element table. With this 2-byte instruction, K would typically be in X with the address of
the beginning of the table in the. instruction. As such,

INHERENT

In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as. well as the control instruction with no
other arguments are included in this mode. These instructions are one byte long.

MOTOROLA MICROPROCESSOR DATA
3-408

MC6805P2

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to + 7.0

V

Input Voltages
(Except Timer in Self-Check
Mode)
Self-Check Mode (TIMER Pin
Only)

Vin

Operating Temperature Range

TA

Rating

V
-0.3 to + 7.0
-0.3 to + 15.0

TL to TH

oto 70

°c

- 40 to + 85°C*
Storage Temperature Range
Junction Temperature
Plastic
Cerdip

Tstg

-55 to +150

These devices contain circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, normal
precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout
should be constrained to the range VSS ~
(Vin and Vout) ~ VCC. Reliability of operation
is enhanced if unused inputs except EXTAL
are tied to an appropriate logic voltage level
(e.g., either VSS or VCC).

°c
°C/W

TJ
150
175

*Available at additional cost

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Cerdip
Plastic

Symbol

Value

Unit
°C/W

6JA
60
72

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can
be obtained from:
TJ=TA+(PO·6JA)
(1)
where:
= Ambient Temperature, °c
TA
6JA = Package Thermal Resistance,
Junction-to-Ambient, °CIW
Po
= PINT+PI/0
PINT = ICC x VCC, Watts - Chip Internal Power
PI/a = Power Oissipation on Input and Output
Pins - User Oetermined

For most applications PI/O a::
~

>

..... co
if if

0

EXTAL

PA5

XTAL

PA4

XTAL

NUM

PA3

NUM

PA4

TIMER

PA2

TIMEIJ

PA3

26
25

PA5

peD

PAl

peD

PA2

pel

PAD

pel

PAl

pe2

PB7

pe2

pe3

PB6

pe3

PBD

PB5

PBl

PB4

PB2

PB3

PAD
19
111

12
C)

&II

Q.,

MOTOROLA MICROPROCESSOR DATA

3-414

f

N

~

M
&II

Q.,

..,.
&II

Q.,

..n
&II
Q.,

co
&II

Q.,

PB7

MOTOROLA

• SEMICONDUCTOR
TECHNICAL DATA

MC6805P6

Technical Summary

8-Bit MicrocontrolierUnit
The MC6805P6 (HMOS) Microcontroller Unit (MCU) is a member of the MC6805 Family of
microcontrollers. This low cost and high-speed MCU has parallel I/O capability with pins
programmable as input or output. This publication contains condensed information on the MCU;
for detailed information, refer to M6805 HMOS, M146805 CMOS Family User's Manual
(M6805UM(AD2)) or contact your local Motorola sales office.
Refer to the block diagram for the hardware features and to the list below for additional features
available on the MCU.
• Internal 8-Bit Timer with 7-Bit
• Low Voltage Inhibit Option
Programmable Prescaler
• Self-Check Mode
• On-chip Oscillator
• Master Reset
• Memory Mapped I/O
• 1804 Bytes ROM
• Versatile Interrupt Handling
• 64 Bytes RAM
• True Bit Manipulation
• 20 I/O Ports
• Bit Test and Branch Instruction
• Vectored Interrupts

I

BLOCK DIAGRAM

TIMER

a
PAO
PAl
Port PA2
A
PA3
1/0 PA4
Lines PA5
PA6
PA7

a
Port
A
Reg.

Data
Dir.
Reg.

5

5

a

116 X SelfCheck ROM

A
Index
Register

CPU
Control

x

Condition
Code
Register CC

Data
Dir.
Reg.

Port
B
Reg.

PBO
PBl
PB2 Port
PB3
B
PB4 110
PB5 Lines
PB6
PB7

CPU

Stack
Pointer

3

SP
Program
Counter
High PCH

a

Program
Counter
low PCl

a

1804 X
EPROM

Accumulator

AlU

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA .MICROPROCESSOR DATA
3-415

PCO Port
PCl
C
PC2 I/O
PC3 Lines

MC6805P6

SIGNAL DESCRIPTION

upon selected manufacturing mask options) can be connected to these pins to provide a system clock.

VCC AND VSS

RC Oscillator

Power is supplied to the microcontroller using these
two pins. VCC is 5.25 volts (± O.5A) power, and VSS is
ground.

With this option, a resistor is connected to the oscillator
pins as shown in Figure 1. The relationship between R
and fosc is shown in Figure 2.

NUM (Non-User Model

Crystal

This pin is not for user applications and must be connected to VSS.

This pin provides the capability for asynchronously applying an external interrupt to the MCU. Refer to INTERRUPTS for more detailed information.

The circuit shown in Figure 1 is recommended when
using a crystal. Using an external CMOS oscillator is recommended when crystals outside the specified ranges
are to be used. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. Refer to ELECTRICAL SPECIFICATIONS for Vce
specifications.

EXTAL,XTAL

External Clock

These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a ceramic resonator, a resistor/
capacitor combination, or an external signal (depending

An external clock should be applied to the EXTAL input
with the XTAL input connected to ground, as shown in
Figure 1.

INT

I

~XTAL

5 XTAL
MCU

CJ

MCU

MCU

External
Clock
Input

Crystal
Approximately 25% to 50% Accuracy
Typical tcyc= 1.25 "'s
External Jumper
Crystal Parameters

C1

L
E X T A L,',. - G

4

External Clock

~XTAL5

VCC
_~1'o. _ _~5 XTAL
R

CE---------l

No
Connection
AT - Cut Parallel Resonance Crystal
Co =7 pF Max.
Freq=4.0 MHz@CL=24 pF
RS=50 ohms Max.

MCU

EXTAL

Approximately 10% to 25% Accuracy
(Excludes Resistor Tolerancel
External Resistor

PiezoelectriC ceramic resonators which
have the equivalent specifications may be
used instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO, C" andRs values.

NOTE: The recommended CL value with a 4.0 MHz crystal is 27 pF maximum including system distributed capacitance. There is an
internal capacitance of approximately 25 pF on the XTAL pin. For crystal frequencies other than 4 MHz, the total capacitance
on each pin should be scaled as the inverse of the frequence ratio. For example, with a 2 MHz crystal, use approximately 50
pF on EXTAL and approximately 25 pF on XTAL. The exact value depends on the motional-arm parameters of the crystal
used.

Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR DATA
3-416

MC6805P6

Table 1. I/O Pin Functions

TIMER

This pin can be used as an external input to control the
internal timer/counter circuitry or for gating <\>2 input to
timer, depending on mask option.
RESET

This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low.

Data
Direction
Register
Bit

Output
Data
Bit

1
1
0

X

0
1

Output
State

Input
To
MCU

0
1
Hi-Z

0
1
Pin

INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO-PC3)

These 20 lines are arranged into two 8-bit ports (A and
8) and one 4-bit port (C). Ports A, 8, and C are programmable as either inputs or outputs under software control
of the data direction registers. Refer to PROGRAMMING
for additional information.

B.O
7.0

i

~

6.0

VCC=525 V
TA=25°C

>-

~ 5.0

1
j
iii

MEMORY
The MCU is capable of addressing 2048 bytes of memory and 1/0 registers. The memory map is shown in Figure
4. The locations consist of 1668 bytes of user ROM, user
self-check ROM, user RAM, a timer control register, and
liD. The user interrupt vectors are located from $7F8 to
$7FF.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
hder to INTERRUPTS for additional information.
NOTE

40

Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

3.0
2.0

0

1.0
0

0

10

20

30

40

50

60

70

REGISTERS

80

Resistance (km

The MCU contains the registers described in the following paragraphs.

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only

ACCUMULATOR (A)

The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING

Any port pin is programmable as either input or output
under software control of the corresponding write-only
data direction register (DDR). The port 1/0 programming
is accomplished by writing the corresponding bit in the
port DDR to a logic 1 for output and a logic 0 for input.
On reset, all the DDRs are initialized to a logic o state to
put the ports in the input mode. The port output registers
are not initialized on reset, and should be written to before setting the DDR bits.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore., any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undef.ined outputs. Care must
be exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (0) and also to the latched output when
the DDR is an output (1). Refer to Table 1 for 1/0 functions
and to Figure 3 for typical port circuitry.

A

INDEX REGISTER (X)

The index register is an 8-bit register used for the indexed addressing mode. It contains ana-bit value that
may be added to an 8- or 16-bit immediate valueto create
an effective address. The index register may also be used
as a temporary storage area.

o

x
PROGRAM COUNTER (PC)

The program counter is an 11-bit register that contains
the address of the next byte to be fetched.
10

8 7

PCH

MOTOROLA MICROPROCESSOR DATA

3-417

0

pel

I

I

MC6805P6

Data'
Direction Register
Bit*
V)

c

~ .g
Q; ~

Latcl;:\ed
Output
Data
Bit

.... c
c c

-

0

u

*DDR is a write-only register and reads as all "ls".

I

PORT DATA REGISTER

o

7

PORT DATA DIRECTION REGISTER (DDR)

o

(1) Write Only; reads as all "1s"
(2) 1- Output; O-Input. Cleared to 0 by reset.
(3) Port A Addr= $004
Port B Addr = $005
Port C Addr= $006 (Bits 0-3)

Port A Addr= $000
Port B Addr = $001
Port C Addr = $002 (Bits 0-3)

Figure 3. Typical Port 1/0 Circuitry and
Register Configuration

STACK POINTER (SP)

Half Carry (H)

The stack pointer is an ll-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
The six most-significant bits of the stack pointer are
permanently set at 000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to, 15
levels of subroutine calls (less if interrupts are allowed).

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

10

5 4

0

I 0 I 0 I 0 I 0 11 I I

Sp

I

The condition code register is a 5-bit register in which
four bits are used to indicate the results of the instruction
just executed. These bits can be individually tested by a
program, and specifications can be ta'ken as a result of
their state. Each bit is explained in the following paragraphs.
0

I I I I z Icl
H

When this bit is set, the timer and external interrupt is
masked (disabled). If an external interrupt occurs while
this bit is set, the interrupt is latched and is processed as
soon as the interrupt bit is cleared.
Negative(N)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative (bit
7 in the result is a logic 1).
Zero,(Z)

CONDITION CODE REGISTER (CC)

4

Interrupt (Jl

N

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.
CarrylBorrow (C)
When set, this bit incjicates that a carry or borrow out
of the arithmetic logical unit (ALU) occllrred during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and during shifts. and
rotates.

MOTOROLA MICROPROCESSOR DATA
3-418

MC6805P6

o
000
Page Zero
Access with
Short
Instructions

127
128

76543210

I/O Ports
Timer
RAM
(128 Bytes)

$000

Page Zero
User ROM
(128 Bytes)

~FF

255

$07F
$080

2039

Interrupt
Vectors
.

~

040

2041
2042
2043
2044
2045

2046

Timer Interrupt

-----External Interrupt

' " - -SWI
---~--.---

Reset

2047

1 1 1 1

$783
$784

I

$000
$001
PortC

$002

3

Not Used

$003

4

PortA DDR

$004*

6

(1668 Bytes)

Self Check
ROM
(116 Bytes)

Port B

Port B DDR

5

Main User
ROM

1923
1924

PortA

1
2

$100

256

0

Not Used

IPort C DDR

$005*
$006*

7

Not Used

$007

8

Timer Data Reg

$008

9
10

Timer Control Reg

$009
$ooA

63

Not Used
(54 Bytes)

64

$03F
$040

I

RAM

(64 Bytes)
$7F7
$7F8
$7F9
$7FA
$7FB
$7FC
$7FD
$7FE
$7FF

Stack
(31 Bytes
Maximum)
127

t

$07F

*Caution: Data direction registers (DDRs) are write-only, set to $FF.

Figure 4. Memory Map

SELF CHECK

RESETS

The self check is initiated by connecting the MCU as
shown in Figure 5 and then monitoring the output of port
C (bit 3) for an oscillation of approximately 7 Hz. The
following tests are executed automatically:
I/O - functionally exercise I/O ports
RAM - walking bit test
ROM - exclusive OR with ODD "1 s" parity result
TIMER- functionally exercise timer
Interrupts - functionally exercise external arid timer
interrupts
Table 2 shows the status of the LEOs as a result of a
failure. Port C is tested on'ly once (just after reset). If port
C fails, no lights will appear.

The MCU can be reset three ways: (1) by initial powerup, (2) by the external reset input (RESET), and (3) by an
optional, internal, low-voltage detect circuit. The RESET
input consists mainly of a Schmitt trigger that senses the
RESET line logic level.
POWER-ON-RESET (POR)

An internal reset is generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power turn-on conditions and
should not be used to detect any drop in the power supply
voltage. A delay of tRHL milliseconds is required before
allowing the RESET input to go tfigh. Connecting a capacitor to the RESET input (Figure 6) typically provides
sufficient delay.

Table 2. Self-Check Error Patterns
EXTERNAL RESET INPUt

PC1

PCO

0

0

Interrupt Failure

0

1

Bad Port A or Port B

1

0

Bad RAM

1

1

Bad RAM

All 4 LEOs Flasing

Function

The MCU is reset when a logic zero is applied to the
RESET input for a period longer than one machine cycle
(tcyel. Under this type of reset, the Schmitt trigger switches
off at VIRES - to provide an internal reset voltage.
LOW-VOLTAGE INHIBIT (LVI)

Good Device

The optional low-voltage detection circuit causes a reset of the MCU if the power supply voltage falls below a

MOTOROLA MICROPROCESSOR DATA

3-419

MC6805P6

2

INT

28

RESET

5

XTAL

PA3 23
PA2 22

EXTAL

PAl

MC6805P6

PA7 27
PA6 26

RESET

1

:::r:

PA5 25

1.0 pF

PA4 24

+9 V

10 k

7

TIMER

6

NUM

VCC

I

21

,PAO 20

PB7

19

PB6

18

PB5

17

PB4

16
15

PCO

PB3

PCl

PB2

14

PC2

PBl

13

PC3

PBO

12

*This connection depends on the clock oscillator user selectable mask option.
Use crystal if crystal option is selected,
Figure 5. Self-Check Connections

certain level (VLVI). The only requirement being that Vee
m~~t remain at or below the VLVI threshold for one tcyc
minimum.
'
In typical applications, the Vee bus filter capacitor will
eliminate negative-going voltage glitches of less than one
tcyc. The output from the low-voltage detector is connected directly to the internal reset circuitry. It also forces
the RESET pin low via a strong discharge device through
a resistor. The internal reset is removed once the power
supply voltage rises above a recovery level (VLVR), at
.
which time a normal power-on reset occurs.

-

1

:r:

INTERRUPTS
The MeU can be interrupted three different ways: (1)
through the external interrupt INT input pin, (2) with the
internal timer interrupt request, or(3) using the software
interrupt instruction (SWI).
Interrupts cause the processor registers to be saved on
the stack and the interrupt mask (I bit) set to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and then
normal processing resumes. The stacking order is shown
in Figure 7.
Unlike RESET, hardware inter~upts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.
NOTE

1.0"F

The current instruction is considered to be the one
already fetched and being operated on.

Part of
MC68705P3
MCU

Figure 6. Power-up RESET Delay Circuit

When the current instruction is complete, the processor
checks all pending hardware interrupts and, if unmasked,
(I bit clear) proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Masked
interrupts are latched for later interrupt service. If the

MOTOROLA MICROPROCESSOR DATA
3-420

MC6805P6

7

n-4

6

5

3

4

, , ,I

2

,

Condition
Code Register

Pull

0

n-3

Accumulator

n+2

n-2

Index Register

n+3

n-

, , , '1 ,

I

PCl*

PCH*

timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 8 for the reset and interrupt
instruction processing sequence.

n+'

n+4
TIMER INTERRUPT

n+5

If the timer mask bit (TCR6) is cleared, then each time
the timer decrements to zero (transitions from $01 to $00)
an interrupt request is generated. The actual processor
interrupt is generated only if the interrupt mask bit of the
condition code register (CCR) is also cleared. When the

Push
* For subroutine calls, only PCH and PCl are stacked.
Figure 7. Interrupt Stacking Order

II
1-1 Bit (in CCI
07F-SP
O-DDRs
CLR INT Logic
FF-Timer
7F -Prescaler
7F-TCR

lear

Stack
PC. X. A. CC

iNi'
Request
Latch

Timer
Put 7FE on
Address Bus

Load PC From:
SWI: 7FC17FD
INT: 7FA17FB
TIMER: 7F817F9
Fetch
Instructibn

SWI

Load PC
from
7FE17FF

Execute All
Instruction
Cycles

Figure 8. Reset and Interrupt Processing Flowchart

MOTOROLA MICROPROCESSOR DATA

3·421

MC6805P6

interrupt is recognized, the current state of the machine
is pushed onto the stack, and the I bit in the CCR is set,
masking further interrupts until the present one is serviced. The contents of the timer interrupt vector, containing the location of the timer interrupt service routine; is
then loaded into the program counter. At the end of the
timer interrupt service routine, the software normally executes an RTI instruction which restores the machine state
and starts executing the interrupted program.

program control and is decremented toward zero. When
the timer reaches zero, the timer interrupt request bit (bit
7) in the timer control register (TCR) is set. Refer to Figure
10 for timer block diagram.
The timer interrupt can be masked (disabled) by setting
the timer interrupt mask bit (bit 6) in the TCR. When the
I bit in the condition code register is cleared, the processor receives the interrupt. The MCU responds to this interrupt by 1) saving the present CPU state on the stack,
2) fetching the timer interrupt vector, and 3) executing
the interrupt routine. The timer interrupt request bit must
be cleared by software. Refer to RESETS and INTERRUPTS for additional information.
The prescaler is a 7-bit divider which is used to extend
the maximum length of the timer. To avoid truncation
errors, the prescaler is cleared when TCR bit 3 is set to
a logic 1; however, the TCR bit 3 always reads as a logic
o to ensure proper operation with read-modify-write instructions.
The timer continues to count past zero, falling from $00
through $FF, and continues the countdown. The counter
can be read at any time by reading the timer data register
(TOR). This allows a program to determine the length of
time since a timer interrupt has occurred without disturbing the counting process. Three machine cycles are
required for a change in state of the TIMER pin to decrement the timer prescaler.
Clock input to the timer can be from an external source
or from the internal phase two signal. Clock source is one
of the mask options available. A prescaler mask option
is also available that can provide up to a maximum of
128 counts to the clock input.

EXTERNAL INTERRUPT
The external interrupt is interna!!.Lsynchronized and
then latched on the falling edge of INT. Clearing the I bit
enables the external interrupt. The MC6805P6 only requires negative edge-sensitive trigger interrupts. The following paragraphs describe two typical external interrupt
circuits.

I

Zero-Crossing
A sinusoidal input signal (fINT maximum) can be used
to generate an external interrupt (see Figure 9a) for use
as a zero-crossing detector (for negative transitions of
the ac sinusoid). This type of circuit allows applications
such as servicing time-of-day routines and engaging/disengaging ac power control devices. Off-chip, full-wave
rectification provides an interrupt at every zero crossing
of the ac signal and thereby provides a 2f clock.
Digital-Signal Interrupt
With this type of circuit (Figure 9b), the INT pin can be
driven by a digital signal. The maximum frequency of a
signal that can be recognized by the TIMER or INT pin
logic is dependent on the parameter labeled tWL, tWH.
Refer to TIMER for additional information.

NOTE
If <1>2 is used, Timer input should be tied to VCe. If
low, it will gate <1>2 off.

SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. If the I bit
is zero, SWI.executes after the other interrupts. The SWI
execution is similar to the hardware interrupts.

TIMER CONTROL REGISTER (TCR) $009
This 8-bit register controls the timer interrupt request
and inhibit signals. All bits are read/write except bit 3.

TIMER

7

The MCU consists of an 8-bit software programmable
counter driven by a 7-bit software programmable prescaler. The timer source is made during manufacturing as
a mask option. The 8-bit counter may be loaded under

I TIR I TIM
RESET:

o

u

u

u

u

(bl Digital-Signal Interrupt

(al Zero-Crossing Interrupt

VCC
ae
Input
(fINT

(Current

TTL

MaX.)~lmltlng).
.

Rs1 MO

aelnputs·

10Vaep-p

R

2

iNT

MCU

0.1-1.0
"F

4.7 k

Level
2
Digital--....--1
Input

lJ
Figure 9. Typical Interrupt Circuits

MOTOROLA MICROPROCESSOR DATA
3-422

iiiJT
MCU

u

MC6805P6

r/>2
(Internal)

Timer
L-.;;,.......:..y...--,r--r-,-...,.-_-r_-_...... Interrupt

I
I

TIMER
Input
Pin

Request
mAl

__1
I

r------j
1

bO

1

1
1

1
1

1

1

Timer Control Register (TCA)

L______ !

Manufacturing
Mask
Options

t

Read

Write

Write

Read

Internal Data Bus

Figure 10. Timer Block Diagram

TIR - Timer Interrupt Request
Used to indicate the timer interrupt when it is logic
one
1 = Set when the timer data register changes to all
zeros
a= Cleared by external reset, power-on reset, or
under program control
TIM - Timer Interrupt Mask
Used to inhibit the timer interrupt.
1 = Interrupt inhibited
a= Interrupt enabled
Bits 5 through a
Not used

INSTRUCTION SET
The MCU has a set of 59 basic instructions. They can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following list of instructions.
Function

Mnemonic

Load A from Memory

LOA

Load X from Memory

LOX

Mnemonic

Function
Add Memory and Carry to A

ADC

Subtract Memory

SUB

Subtract Memory from A with Borrow

SBC

AND Memory to A

AND

OA Memory with A

ORA

Exclusive OR Memory with A

EOR

Arithmetic Compare A with Memory

CMP

Arithmetic Compare X with Memory

CPX

Bit Test Memory with A (Logical Compare)

BIT

Jump Unconditional

JMP

Jump to Subroutine

JSR

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes ofthe memory space, where
all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear and bit test, and
branch functions are all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the carry bit of the condition
code register. Refer to the following list for bit manipulation instructions.
.
Function

Mnemonic

Branch if Bit n is Set

BRSH n (n=O ... 7)

Store A in Memory

STA

Branch if Bit n is Clear

BRCLR n(n=O ... 7)

Store Xin Memory

STX

Set Bit n

BSH n (n=O ... 7)

Add Memory to A

ADD

Clear Bit n

BCLR n (n=O ... 7)

MOTOROLA MICROPROCESSOR DATA
3-423

II

MC6805P6

READ·MODIFY·WRITE INSTRUCTIONS

CONTROL INSTRUCTIONS

These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.

These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.

Function
Function

Increment

Transfer A to X

TAX

INC

Transfer X to A

TXA
SEC

DEC

Set Carry Bit

Clear

CLR

Clear Carry Bit

CLC

Complement

COM

Set Interrupt Mask Bit

SEI

Negate (2's Complement)

NEG

Clear Interrupt Mask Bit

CLI

Rotate Left Thru Carry

ROL

Software Interrupt

SWI

Rotate Right Thru Carry

ROR

Return from Subroutine

RTS

LSL

Return from Interrupt

RTI
RSP
NOP

Decrement

II

Mnemonic

Mnemonic

Logical Shift Left
Logical Shift Right

LSR

Reset Stack Pointer

Arithmetic Shift Right

ASR

No-Operation

Test for Negative or Zero

TST

OPCODE MAP SUMMARY
Table 3 is an opcode map for the instructions used on
the MCU.

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list for branch instructions.

ADDRESSING MODES

Branch if Not Equal

BNE

Branch if Half Carry Clear

BHCC

The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte
instructions while the longest instructions (three bytes)
permit accessing tables throughout memory. Short and
long absolute addressing is also included. Two byte direct addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

Branch if Half Carry Set

BHCS

IMMEDIATE

Function

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

Branch if Carry Clear
(Branch if Higher or Same)
Branch if Carry Set
(Branch if Lower)

BCC
(BHS)
BCS
(BLO)

Branch if Plus

BPL

Branch if Minus

BMI

Branch if Interrupt Mask Bit is Clear

BMC

Branch if Interrupt Mask Bit is Set

BMS

Branch if Interrupt Line is Low

BIL

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).

DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the

MOTOROLA MICROPROCESSOR DATA
3-424

Table 3. Opcode Map

Bit Manipulation

1 BranCh

~JlSC-J---'iEl

~
o

,

0000

0001

Jo

~1

1
Read-Modify-Write
Control
r=::::om--r=INH ~1J~_n 12L~ INH
I INH

~o

o~

J,1

6

01~1

o~o

r

1~9
' NEG
1
IX
1

10
BASETO 17 BSETO ]4 BAA
1
NEG
]4 NEG
14 NEG
]7 NEG
13
BTB 2
Bse 2
REL 2
DIR 1
Lf>!H 1
INH 2
IX 1

I

TO~--~-~
BACLRO
BCLRO
BRN

3

BTB

2

Bse

2

AEL

l-

_

_

L

01~1

1~
RTI

1

I

1~1

_

J

DIR

EXT-1

1><2 I

,t,o

1:'1

1[00

1Pol

INH

2

RTS
INH

-[4 -['

CMP
2
IMM

- CMP
2
DIR

1X1

IX

I~O

,f,1

~--~r:SUB
SUB
3
1><2 2
IXL 1

r

-,6

]2
SUB] 4 SUB
]5 SUB
2
IMM 2 ___ DIA 3 _---.EXT

1-- ]6--T--1

_

_~ister/~

_
IMM

I~

SUB
IX

CMP ~5 CMP
CMP
3Jl<.2 2
IXL I
IX

CMP
3
EXT

1
1

0

moo
1

0001

2

0010

3

0011

4

10
BRSET2 ]7 BSET2 ]4 BCC
13
BTB 2
Bse 2
AEL

5

10
BACLA2
13
BTB

6

10BASET3
BTB

0100

s:

S
o
::D

o

~

s:

w

t

U1

n
::D
o
"tI

0101

.JilllL

]6

2

]

]6
LSR ]

]4 LSRA ]4 LSRX
]7 LSR
LSR
DTA 1
INH 1
INH 2
IXll

I-I

AEL

2_DIA

1

_..lliH

2

16 1

_

14-~-:J4
BNE
ROR
RORA --[4
2

]2

IX

r--=r------~___

12
2

~

RORX -[7 ROR
ROR
1 __.ill!i 2
IXL 1
IX

AND
_ IMM

I'

2

-

AND
AND
AND
AND
AND
DIRI3
EXTI3
_12\212
_--.lll11
__

-~-4
~---r---~---T:
BIT
BIT
BIT
BIT
BIT
_ 1M!
DIA 3.£XT 3
IX2 2
1Xl_ 1

r:

J:-

~-LOA

[4 LOA
~-I-LOA
LOA
IMM 2
DIA 3
EXT 3
Jl<.2

8

9

1001

A
.1l!!lL

B

m

o::D

1101

e

BCS
2
AEL

JOO!L

lOll

C

BSET3
2
Bse

]4

LOA
2_ _ _
IX_l

~

4
01OD.

I

5
0101

J_~

6
0110

BIT
IX

LOA

7

1100

CJ)
CJ)

r

BCLA2
2
Bse

0111

::D

on

13..

]7

6

II

BASET5
BTB_
BTB

ll~ASET6

o

w
BACLA6
13
BTB

1110

F
1111

3.

BTB

~

---1 --I --I

2

Bse

_Aft

DIA

BMI
2
AEL

17 BSET6 14 BMC
2
Bse 2
REL

]62

BCLA6 14 BMS
Bse 2
AEL-

2

r

---'4

DECA
DECX
Il!1\H 11
INH

4

T

BIL

foBACLR7
3
BTB

I

_ DIR

I--- 1-

I.JNH

I

TSTX

IXI

1

TST

J61

_IX 1

l\'ili - 2

1

62

~-CLRAJ4

CLA

DIA

1

INH

DEC

I

l

__

CLRX
1
INH

-[7-

CLR

2

1
IX 1

6
1

TST

CLR

____

IX _ _

_

]2

~---:1:
ADC

12 ADC
14 ADC
SEC
INH 2
IMM 2
DIA

1

I

_

Inherent
Immediate
Direct
Extended
Relative
Bit Set/Clear
Bit Test and Branch
Indexed (No Offset)
Indexed. , Byte (8-Bit) Offset
Indexed. 2 Byte (16-Bit) Offset

3

J"

IX2

ADC

15
2
2

IXI

r

1

AOC

ADO

INH

2

]4

ORA
2
DIA

IMM

12 RSP]
INH

2

DIR

ORA
3
EXT
3

EXT

]3 JMP
]4 JMP
2
DIA 3
EXT

---.L..

OAA
3 _---.ll<2

I'

]2

TXA
1
INH

---1

12 LOX
14 LOX
~ 5 LOX
2
IMM 2
DIA 3
EXT

]

1

5

STX
2
DIR

r

IX2

3

JMP

3

12 NOP
]B BSRAEL ]72 JSRDIA 1 83 JSAEXT ]93
1
INH 2

IX2
JSA

6

IXI

1

14 JMP
2
IXI

2

]31

8
1 JSA

J
J:

IX2

__ i l l 1

2

2

STX

IXI

141

LOX

1

STX

5
1

I
Jl\J
I
IX

9

1001
A
1010

IX

B
1011

IX

1100

IX

lUll

IX

1110

JMP
JSR

IXI 11

5 LOX
LOX
3
--.ll

I~-Z

en

(I)

:>

I~a:w

.....
cr
D..

0

26
25

0
al
D..

MOTOROLA MICROPROCESSOR DATA
3-432

PA5

PAO
19
12

PB3

<0

cr

D..

18
N
CD
D..
~

M

~

"""
~

Ln

~

<0
al
D..

PB7

MOTOROLA

.SEMICONDUCTOR .............................
TECHNICAL DATA

MC6805R2

Technical Summary

8-Bit Microcontroller Unit
The MC6805R2 (HMOS) Microcontroller Unit (MCU) isa member of the MC6805 Family of microcontrollers. This low cost and high-speed MCU has parallel 1/0 capability with pins programmable
as input or output. This publication contains condensed information on the MCU; for detailed information, refer to M6805 HMOS, M146805 CMOS Family User's Manual (M6805UM(AD2)) or contact
your local Motorola sales office.
Refer to the block diagram for the hardware features and to the list below for additional features
available on the MCU.
• Internal 8-Bit Timer with 7-Bit Prescaler
• Vectored Interrupts
• On-chip Oscillator
• Self-Check Mode
• Memory Mapped 1/0
• 2048 Bytes of ROM
• Versatile Interrupt Handling
• 64 Bytes of RAM
• True Bit Manipulation
• 24 Bidirectional 1/0 Ports
• Bit Test and Branch Instruction
• AID Converter

II

BLOCK DIAGRAM

TIMER

Port
A
I/O
Lines

PAD
PAl
PA2
PA3
PA4
PA5
PA6
PA7

Accumulator
Port
A
Reg

Data
D,r
Reg

CPU
Control

5

Port
B
I/O
Lines

PBD
PBl
PB2
PB3
PB4
PB5
PB6
PB7

PDO/AND
PD1/ANl
PD2/AN2 Port
0
PD3/AN3
PD4IVRL Input
lines
P05IVRH

Register

8

X
Condition
Code
Register

CC

CPU

PD6/i'fiin

Stack
POinter

Port
B
Reg

Data
D,r
Reg

4

P07

Program
Counter
High
PCH

ALU

Program
Counter

8
Data
Dir
Reg

Port
C
Reg

PCD
PCl
PC2
PC3
PC4
PC5
PC6
PC7

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-433

Port
C
I/O
Lines

MC6805R2

SIGNAL DESCRIPTION

8.0.--..------------------.,

VCC AND VSS
Power is supplied to the microcomputer using these
two pins. VCC is + 5.25 volts (± 0.511) power, and VSS is
ground.

~

~

NUM
This pin is not for user applications and must be connected to VSS.

70

E:;

6.0

ifi
::;)

50

ffi
IE
§

30

~

26

~

1,0

VCC=525V
TA=25°C

4.0

U.l

INT

0

This pin provides the capability for asynchronously applying an external interrupt to the MCU. Refer to INTERRUPTS for more detailed information.

10

40
50
ReSistance (kill

20

60

30

70

'80

Figure 2. Typical Frequency vs Resistance for
RCOsciliator Option Only

EXTAL,XTAL

I

0

These pins provide control input for the on-chip dock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal (depending upon selected
manufacturing mask option) is connected to these pins
to provide a system clock.

Crystal
The circuit shown in Figure 1 is recommended when
using a crystal. Using an external CMOS oscillator is recommended when crystals outside the specified ranges
are to be used. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. Refer to ELECTRICAL SPECIFICATIONS for VCC
specifications.

RC Oscillator
With this option, a resistor is connected to the oscillator
pins as shown in Figure 1. The relationship between R
and fosc is shown in Figure 2.

C' 0C1

EXT AL

5

---C"'"'
(See Note) C:l

RS
XT AL
Co.
6

6

XTAL
MCU
EXTAL

AT - Cut Parallel' Resonance Crystal
Co =7pFMax
Freq. = 4.0 MHz @ CL = 24 pF
RS=50 ohms Max.

Crystal

Piezoelectric ceramic resonators which
have the equivalent specifications may be
use.d instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO"C" and RS values.

VCC
XTAL

XTAL
External
Clock
Input

MCU
EXTAL

~\JV'V--'-t

MCU
EXTAL

R
(See Figure 7-5)

XTAL
MCU
EXTAL

No
, Connection

External Clock

Approximately 25% to 50% AccuracY
Typical tcyc= '.25,.s
. External Jumper

Approximately 10% to 25% Accuracy
I Excludes Resistor Tolerancel
External Resistor

NOTE: The recommended CL value with a 4.0 MHz crystal is 27 pF maximum, including system distributed capacitance. There is an
internal capacitance of approximately 25 pF on the XTAL pin. For crystal frequencies other than 4 MHz, the total capacitance
on each pin should be scaled as the inverse of the frequency ratio. For example, with a 2 MHz crystal, use approximately 50
pF on EXTAL and approximately 25 pF on XTAL. The exact value depends on the Motional-Arm parameters of the crystal
used.

Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR .DATA
3-434·

MC6805R2

External Clock
An external clock should be applied to the EXTAL input
with the XTAL input connected to ground, as shown in
Figure 1. This option may only be used with the crystal
oscillator option selected in the mask option register. The
tOXOV or tlLCH specifications do not apply when using
an external clock input.
TIMER
This pin is used as an external input to control the
internal timer/counter circuitry. This pin also detects a
higher voltage level used to initiate the self-test program.
RESET
This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low.
INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO-PC7,PDOPD7)
These 32 lines are arranged into four 8-bit ports (A, B,
C, and D). Ports A, B, and C are programmable as either
inputs or outputs under software control of the data direction registers. Port D is a fixed input port and not
controlled by any data direction register. Port D has up
to four analog inputs, plus two voltage reference inputs
when the AID converter is used (PD5NRH, PD4NRL) and
an INT2 input. All Port D lines can be read directly and
used as binary inputs. If any analog input is used, then
PD5NRH and PD4NRL must be used in the analog mode.
Refer to PROGRAMMING and ANALOG-TO-DIGITAL
CONVERTER for additional information.

and a logic zero for input. On reset, all the DDRs are
initialized to a logic zero state to put the ports in the input
mode. The port output registers are not initialized on
reset and should be written to before setting the DDR
bits.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the outputpin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Care must
be .exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (zero) and also to the latched output when
the DDR is an output (one). Refer to Table 1 for I/O functions and to Figure 3 for typical port circuitry.
Port D provides reference voltage (lNT2) and multiplexed analog inputs. Port D can always be used as digital
input and may be used for analog if VRH and VRL are
connected to the appropriate reference voltage. The VRH
(PD5) arid VRL (PD4) are internally connected to the AID
resistor.
Table 1. I/O Pin Functions
Data
, Direction
Register
Bit

Latched
Output
Data
Bit

Output
State

Input
To
MCU

1
1

0

0

0

1

0

X

1
Hi-Z**

Pin

1

**Ports Band C are three-state ports. Port A has optional internal
pullup devices to provide CMOS data drive capability.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING

MEMORY

Port A, B, and C pins are programmable as either input
or output under software control of the corresponding
data direction register (DDR). Port D lines are input only.
The port 110 programming is accomplished by writing the
corresponding bit in the port DDR to a logic one·for output

The MCU is capable of addressing 4096 bytes of memory and I/O registers. The memory map is shown in Figure
4. The locations consist of user ROM, self-check ROM,
user RAM, AID registers, a miscellaneous control register,

Internal
Connections

Figure 3. Typical Port I/O Circuitry and
Register Configuration

MOTOROLA MICROPROCESSOR DATA
3~435

II

MC6805R2

I:
7

k~ :SZ:i~h
In~;~~t~ns

76543210
$()()()

I/O Ports
Timer
RAM
(128 Bytes)

. 128

Page Zero
User ROM
(128 Bytes)

,

255
Not Used
Bytes)

(17~B

1983

Port C Data Register

$002

K.~
\

Port D Data Register.

$003

4

.PortA DDR*

$004*

5

Pvrt B DDR*

$005"

6

Port C DDR*

7

Not Used

$7BF
$7CO

Self Check
ROM
(192 Bytes)

II

4093
4094

4095

r

Timer Data Register

$008

9

Timer Control Register

$009

10

Miscellaneous Register

$OOA
$OOB

13
14

4087
Timer Interrupt

- -- - - - - - - - - - -

.-

External Interrupt
SWI

'-

RESET

$FF7
$FF8

15
16

$FF9
$FFA

63
64

Not Used
(3 Bytes)

$OOD

AI D Control Register

$OOE

AI D Result Register

$OOF
$010

Not Used
148 Bytes)

$03F

$040

RAM
164 Bytes)

$FFB
$FFC
$FFD
$FFE
$FFF

$006"
$007

B

11

$F37
$F3B

§

$001

3

Main User
ROM
(1912 Bytes)

Interrupt·1
Vectors
4092 ~

$()()()

Port B Data Register

2

1984

~

Port A Data Register

1
$07F

$OFF
$100

256

0

Stack
131 Bytes
Maximum)

t

127

$07F

.* Caution: Data direction registers (DDRs) are write-only; they read as $FF.

Figure 4. Memory Map
and 1/0. The interrupt and reset vectors are located from
$FF8 to $FFF.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.
NOTE

an effective address. The index register may also be used
as a temporary storage area.
7

x
PROGRAM COUNTER (PC)
The program counter is an 12-bit register that contains
the address of the next byte to be fetched.

Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

11

8 7

PCH

PCl

STACK POINTER (SP)

REGISTERS
The MCU contains the registers described in the following paragraphs.
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.

The stack pointer is an 12-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
The seven most-significant bits of the stack pointer are
permanently set at 0000011. Subroutines and interrupts
may, be nested down to location $061· (31 bytes maximum), which allows the programmer to use up to 15
levels of subroutine calls (less if interrupts are allowed).

7

11

5

4

I 0 I 0 I 0 I 0 I 0 I 111 I

A

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may. be added to an 8- or 16-bit immediate value to create

0

sp

I

CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit register in which
four bits are used to indicate the results of the instruction
just executed. These bits can be individually tested by a

MOTOROLA MICROPROCESSOR DATA
3-436

MC6805R2

program, and specific actions can b.e taken as a result of
their state. Each bit is explained in, the following paragraphs.

Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
When this bit is set, the timer and external interrupt is
masked (disabled). If an external interrupt occurs while
this bit is set, the interrupt is latched ahd is processed as
soon as the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last
arithmetic, logical, or data "manipulation was negative
(bit 7 in the result is a logic one).

SELF-CHECK
The self-check is initiated by connecting the MCU as
shown in Figure 5 and then monitoring the output of port
C (bit 3) for an oscillation of approximately 7 Hz. The
fO,lIowing test are exec,uted automatically:
1/0 - Functionally exercise 1/0 ports.
RAM - Walking bit test.
ROM - Exclusive OR with ODD "1st" parity result
Timer - functionally exercise timer.
Interrupts - Functionally exercise external and timer
interrupts.
'
AID Converter ~ Functionally test the Analog-to-Digital
Converter.
The RAM, ROM, and the AID test <;an be cal,led by a user
program, The timertest may be called if the timer input
is the internal clock. Table 2 shows the status,of the LEDs
as a result of a failure. Port C is tested only once (just
after reset). If port C fails, no lights will appear.
Tabl~2.self-Check

Zero (Z)
When set, this bit indicates that the result cif the last
arithmetic, logical, or data manipulation was zero.

PCO

1
0
1
0
1
0

Car:ry/Borrow (C)
When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and during shifts and
rotates.

r

1.

lO...L.

~F

T

2

Vss

PA7

RES"ET

PA6

3fNf
4 VCC

...J....,l.O ~F

5.25 V

5

:;;!;~~

lOV

LED

LED
LED

-

~

EXTAL

- ~~

400

10 k

MHZ£ NUM IN/C)··

~
=

8

51011

~

~-~1?!!,

LED

.:::!:::

XTAL

51011

PA5
PA4

40

F-fL~

PAl 34
PAO 33

PB7 32

11 PC2

PB5

12 PC3

PB4

PC4

F--~
pL

PB3 2B

~ PC5

PB2

~ PC6

' PBl

16 PC7

PBO

~

Remarks (1: LED ON; 0: LED OFF)

Bad I/O
Bad Timer
Bad RAM
Bad ROM
Bad AID
Bad Interrupts or Request Flag
Good Device

PA2 35

PB6

,--!2

0
0
0
0
0
0

PA3 36

10 PCl

..J}

PC3

TIMER

9 PCO
'V

~.blOl1

PC2

1
0
1
0
1
0
1
0
0
0
0
0
All Flashing

Anything else Bad Part, Bad Port C, etc.

~

RESET

PC1

Error Patterns

F- t-r~ r~

PD7
PD6111NT21

19 PD5

O.l~FT

PDO 24
PD1 23
PD2 22

20 PD4

PD3 21

*

*This connection depends on clock oscillator user selectable mask option. Use jumper if the RC mask option is selected.
**Pin 7 is not for user application and must be connected to VSS.

Figure 5 .. Self-Check Connections

MOTOROLA MICROPROCESSOR DATA
3-437

II

MC6805R2'

RESETS·

In typical applications, theVCC bus filter capacitor will
eliminate negative-'g'oing voltage glitches of less thah One
tcyc. The output from the low-voltage detector is connected directly to the internal reset circuitry. It also forces
the RESET pin low via a strong dischar.ge device through
a resistor. The internal reset is removed once the power
supply voltage rises above a recovery level. (VLVR) at
which time a norrnal. power-on reset occurs.

The MCU can be reset three ways: (1) by initial powerup, (2) by the external reset input (RESET), and (3) by an
optional, internal, low"voltage detect circuit. The RESET
input consists mainly of a Schmitt trigger that senses the
RESET line logic level.

POWER-ON-RESET {PORI

is

An internal reset generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power' turn-on conditions and
should not be used to detect any drop in the power supply
voltage. A delay of tRHL milliseconds is required before.
allowing the RESET input to go high. Connecting a capaCitor'to the RESET input (Figure 6) typically provides
sufficient delay.
.

INTERRUPTS
The MCU.canbe interrupted four different ways: (1)
through the external interrupt INT input pin, (2) with the
internal timer interrupt request,' (3) using the software
interrupt instruction (SWI) or (4) the external port D bit 6
(lNT2) input pin.
Interrupts cause the processor registers to be saved on
the stack and the interrup~ mask (I bit) set to prevt;lnt
additional interrupts. The RTI instruction causes the reg~
ister contents to be recovered from the stack, and then
normal processing resumes. The stacking order is shown'
in Figure 7..
Unlike. RESET, hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.

EXTERNAL RESET INPUT

II

~MCU is re~etwhen a logic zero is applied to the

RESET input for a period longer than one machine cycle.
(tcyel. Under this type of reset, the Schmitt trigger ~witches
off at VIRES - to provide an internal reset voltage.

LOW-VOLTAGE INHIBIT (LVI)
The optional low-voltage detection circuit causes a reset of the MCU if the power supply voltage falls below a
certain level (VLVI). The only requirement is that the VCC
m~~t remain at or below the VLVI threshold for one tcyc
minimum.

NOTE
The current instrl,lction is considered to be the one
already fetched and being operated on.

P.in2
t.OI'F

Typical

'--'--+-1

P.OR
Delay
Capacitor

Figure 6. RESET Configuration

j

Pull

n-4

1

I

1

I

1

I

Condition Code Register

n-3

Accumulator

n+
n+21

n-2

Index Register

n+3

1

n-1

1

I

1

I

1

I

1

I

PCH~

PCl*

Push

* For subroutine calls, only PCH and PCl are stacked.

Figure

7~lnterrupt

Stacking Order

MOTOROLAMICROPROCESSOA DATA
3-438

n+4
n+5

MC6805R2

When the current instruction is complete, the processor
checks all pending hardware interrupts and, if unmasked
(I bit clear). proceeds· with interrupt processing; otherwise, the next instruction is fetched and executed. Masked
interrupts are latched for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, th~ external interrupt is serviced first. Tre SWI is executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 8 for the reset and interrupt
instruction processing sequence.
TIMER INTERRUPT

If the timer mask bit (TCR6) is cleared, then, each time
the timer decrements to zero (transitions from $01 to $00),
an interrupt request is generated. The actual processor
interrupt is generated only if the interrupt mask bit of the
condition code register (CCR) is also cleared. When the
interrupt is recognized, the current state of the machine
is pushed onto the stack and the I bit in the CCR is set,
masking further interrupts until the present one is serviced. The contents of the timer interrupt vector, containing the location ofthe timer interrupt service routine, is

then loaded into the program counter. At the end of the
timer interrupt service routine, the software normally executes an RTI instruction which restores the machine sta,te
and starts executing the interrupted program.

EXTERNAL INTERRUPT
The external interrupt is intern~ synchronized a'nd
then latched on the falling edge of INTand INT2. Clearing
the I bit enables the external interrupt. The INT2 interrupt
has an interrupt request bit (bit 7) and a mask bit (bit 6)
in the miscellaneous register (MR). The INT2 interrupt is
inhibited when the mask bit is set. The INT2 is always
read as a digital input on port D. The INT2 and timer
interrupt request bits, if set, cause the MCU to process
and interrupt when the condition code I bit is clear. The
following paragraphs describe two typical external interrupt circuits.
Zero-Crossing Interrupt

A sinusoidal input signal (fINT maximum) can be used
to generate an external interrupt (see Figure 9a) for use
as a zero-crossing detector (for negative transitions of
the ac sinusoid). This type of circuit allows applications

1-1 (in CCI
07F-SP
O-ODAs
CLA flirT Logic
FF-Timer
7F - Prescaler
7F-TCA
7F-MA

Load PC From:
SWI: FFC/FFD
INT: FFA/FFB
Timer or

INT2: FFS/FF9

Figure 8. Reset and Interrupt Processing Flowchart

MOTOROLA MICROPROCESSOR DATA'
3-439

II

MC6805R2

such as servicing time-of-day routines and engaging/disengaging ac power control devices. Off-chip, full-wave
rectification provides an interrupt at every zero crossing
of the ac signal and thereby provides a 2f clock.

Digital-Signal Interrupt
With this type of cir~uit (Figure 9b), the INT pin can be
driven by a digital signal. The maximum freque~ of a
signal that can be recognized by thE! TIMER or INT pin
logic is dependent on the parameter labeled tWL, tWH.
Refer to TIMER for additional information.
SOFTWARE INTERRUPT (SWI)
The SWI· is an executable instruction that is executed
regardless of the state of the I bit in the CCR. If the I bit
is zero, SWI executes after the other interrupts. The SWI
execution is similar to the hardware interrupts.

II

TIMER
The MCUconsists of an 8-bit software programmable
counter driven by a 7-bit prescaler. The timer source is
made during manufacturing as a mask option. The 8-bit
counter may be loaded under program control and is
decremented toward zero. When the timer reaches zero,
the timer interrupt request bit (bit 7) in the timer control
register (TCR) is set. Refer to Figure 10 for timer block
diagram.

The timer interrupt can be masked (disabled) by setting
the timer interrupt mask bit (bit 6) in the TCR. When the
I bit in the condition code register is cleared, the processor receives the interrupt. The MCU responds to this interrupt by 1) saving the present CPU state On the stack,
2) fetching the timer interrupt vector, and 3) executing
the interrupt routine. The timer interrupt r~st bit must
be cleared by software. The TIMER and INT2 share the
same interrupt vector, therefore the interrupt routine must
check the request bits to determine the source of the
interrupt. Refer to RESETS and INTERRUPTS for additional information.
'
The prescaler is a 7-bit divider which is used to extend
the maximum length of the timer. To avoid truncation
errors, the prescaler is cleared when TCR bit 3 is set to
a logic one; however, the TCR bit 3 always reads as a
logic zero to ensure proper operation with read-modifywrite instructions.
The timer continues to count pastzero, falling from $00
through $FF, and continues the countdown. The counter
can be read at any time by reading the timer data register
(TDR). This allows a program to determine the length of
time since a timer interrupt has occurred without disturbing the counting process. Three machine cycles are
required for a change in state of the TIMER pin to decrement the timer prescaler.
Clock input to the timer can be from an external source
or from the internal phase two signal. Clock source is one
of the mask options. A prescaler mask option is available
to select a divide option of a power of two up to 128.
(b) Digital-Signal Interrupt

(a) Zero-Croesing Interrupt

Vee
Inapc
ut
(fINTMax.)

Rs1 MO
ac Input
~10 Vacp-p

TTL

(Current

~'m't1nQI

0.J

3

~

MCU

..

0 1 -1 0
I'F .

R

47 K

D'Q,tal--. . .--I
Input

MCU

lJ·--------Figure 9. Typical Interrupt Circuits

PSC (Prescaler Clearl
Timer

Timer
Interrupt
Mask

TIMER
Input
Pin

,...------,

I
:

iNf

Level

:

L______ !I

Manufacturing
Mask Options

Internal Data Bus

Figure 10: Timer Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-440

MC6805R2

TIMER CONTROL REGISTER (TCR) ($009)

This 8-bit register controls various functions such as
write timer interrupt request, timer interrupt inhibit, and
prescaler clear. Bit 3 is write only.
7

I .TIR

6

5

4

TIM

3

PSC

converter uses 30 machine cycles to complete a conversion of a sampled analog input. When the conversion is
complete, the digital value is placed in the AID result
register (ARR), the conversion flag set, selected input is
sampled again, and a new conversion starts. When ACR7
is cleared, the conversion in progress is aborted and the
selected input is sampled for five machine cycles and
held internally.

RESET:

o

u

u

u

u

TIR - Timer Interrupt Request
Used to indicate the timer interrupt when it is logic
one.
1 = Set when the timer data register changes to all
zeros.
0== Cleared by external reset, power-on reset, or
under program control.
TIM - Timer Interrupt Mask
Used to inhibit the timer interrupt.
1 = Interrupt inhibited.
0= Interrupt enabled.
PSC - Prescaler Clear
Write only bit. Writing a one to this bit resets the
prescaler to zero. A read of this location always indicates a zero.
Bits 5, 4, 2, 1, 0 - Not Used.

ANALOG-TO-DIGITAL CONVERTER
The chip resident 8-bit analog-to-digital (AID) converter
uses a successive approximation technique as shown in
Figure 11. Four external analog inputs can be connected
to the AID through a multiplexer via Port D. Four internal
analog channels (VRH-VRL, VRH-VRL/2, VRH-VRL/4, and
VRLl may be selected for calibration. The accuracy of
these internal channels may not meet the accuracy specifications of the external channels.
Multiplexer selection is controlled by the AID control
register (ACR) bits 0, 1, and 2. Refer to Table 3 for multiplexer selection. The ACR is shown in Figure 11. The

Table 3. AID Input MUX Selection
AID Control Register
ACR2

ACR1

ACRO

Input
Selected

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

ANO
AN1
AN2
AN3
VRH*
VRL*
VRH/4*
VRH/2*

PD2/AN2

Max

FE

FF

FF

00

00
40
80

01
41
81

3F
7F

The converter uses VRH and VRL as reference voltages.
An input voltage equal to or greater than VRH converts
to $FF. An input voltage equal to or less than VRL, but
greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded. Each analog input
source should use VRH as the supply voltage and be
referenced to VRL for the ratiometric conversion. To
maintain full accuracy of the AID, three requirements
should be followed: (1) VRH shouldbe equal to or less
than VDD, (2) VRL should be equal to or greater than VSS
but less than maximum specifications, and (3) VRH-VRL
should be equal to or greater than 4 volts.
The AID has a built-in 1/2 LSB offset intended to reduce
the magnitude of the quantizing errorto ± 1/2 LSB, rather
than + 0, -1 LSB with no offset. This implies that, ignoring errors, the transition point from $00 to $01 occurs
at 1/2 LSB above VRL. Similarly, the transition from $FE
to $FF occurs 1-1/2 LSB below VRH, ideally.

DIA

PD1IAN1

Typ

*Internal (Calibration) Levels

15 kO lTypl

PDOIANO

AID Output (Hex)
Min

1-01-8
Select
Multiplexer

PD3/AN3

AID

AID
Result
'--~~---<.----''--~-'---'---'' Register

Figure 11. AID Block Diagram

MOTOROLA MICROPROCESSOR DATA

3-441

II

MC6805R2

READ-MODIFY -WRITE INSTRUCTIONS

INSTRUCTION SET
. The MCU has a set of 59 basic instructions which can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions ·use two operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following list of instructions.
Function

II

Mnemonic

Load A from Memory

LDA

Load X from Memory

LDX

Store A in Memory

STA

Store X in Memory

STX

Add Memory to A

ADD

Add Memory and Carry toA

ADC

Subtract Memory

SUB

Function

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Complement

COM

Negate (2's Compl.ement)

NEG

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Logical Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TSJ

Subtract Memory. from A with Borrow

SBC

AND Memory to A

AND

BRANCH INSTRUCTIONS

OR Memory with A

ORA

This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two-byte instructions. Refer to the following list for branch instructiohs.

Exclusive OR Memory with A

EOR

Arithmetic Compare A with Memory

CMP

Arithmetic Compare X with Memory

CPX

Bit Test Memory with A (Logical Compare)

BIT

Jump Unconditional

Function

JMP

Jump to Subroutine

JSR

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

BIT MANIPULATION INSTRUCTIONS

Branch if Carry Clear

The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space, where
all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear and bit test, and
branch functions are all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the carry bit ofthe condition
code register. Refer to the following list for bit manipulation instructions.

(Branch if Higher or Same)

BCC
(BHS)

Branch if Carry Set

BCS

(Branch if Lower)

(BLO)

Branch if Not Equal

BNE

Branch if Equal

BEQ

Branch if Half Carry Clear

BHCC

Branch if Half Carry Set

BHCS

Branch if Plus

BPL

Branch if Minus

BMI

Branch if Interrupt Mask Bit is Clear

BMC

Branch if Bit n is Set

BRSET n (n =0 ... 7)

Branch if Interrupt Mask Bit is Set

BMS

Branch if Bit n is Clear

BRCLR n (n=O ... 7)

Branch if Interrupt Line is Low

BIL

Set Bit n

BSET n (n=O ... 7)

Branch if Interrupt Line is High

BIH

Clear Bit n

BCLR n (n=O ... 7)

Branch to Subroutine

BSR

Function

Mnemonic

MOTOROLA MICROPROCESSOR DATA
3-442

MC6805R2

CONTROL INSTRUCTIONS
These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.
Function

EXTENDED
In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction.

Mnemonic

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

CLC

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

Reset Stack Pointer

RSP

No Operation

NOP

RELATIVE
The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from - 126 to + 129 from
the opcode address.
INDEX, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to mbvea pointer through
a table or to hold the address of a frequently referenced
RAM or 110 location.

OPCODE MAP SUMMARY
Table 4 is an opcode map for the instructions used on
the MCU.

INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents ohhe unsigned
8-bit index register and the unsigned byte following the
oocode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
the beginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($.1 FE is the last location at which the instruction may
begin).

ADDRESSING MODES
The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code coversion tables, and scaling tables anywhere in the memory
space. Short indexed accesses are single-byte instructions, while the longest instructions (three bytes) permit
accessing tables throughout memory. Short and long absolute addressing is also included. Two-byte direct-addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

IMMEDIATE
In the immediate addressing mode, the operand is tontained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not· change during program execution (e.g'i a
constant used to initialize a loop counter).

INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum ofthe contents ofthe unsigned
8cbit index register and the two unsigned bytes following
the opcode. This addressing mode can be used in a manner similar to indexed, 8-bit offset except that this threebyte instruction allows tables to be anywhere in memory.
BIT SET/CLEAR
In the bit setlclear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
. opcode specifies the direct addressing of the byte to which
the specified bit is to be set or cleared. Thus, any readl
write bit in the first 256 locations of memory, including
110, can be selectively set or cleared with a single twobyte instruction.

DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.

CAUTION
The corresponding' DDRs for ports A, B, and Care
write-only registers (registers at $004, $005, and
$006). A read operation on these registers is undefined. Since BSET and BClR are read-modify-write

MOTOROLA MICROPROCESSOR DATA
3-443

I

•

Table 4. Opcode Map

BIt M8niDuIMion
BTl
BSC

~
o
~ .

1

~

ono

s;

B

~

o

3:

w

t

~

~

m

en
en

o

~.

c

»

>

2

Bse

BTB

2

·1'

Bse

,0
BRCLR1BCLRl
BTB.

2

8se

, 10
BRCLR2. BCLR2
3
BTB 2
.. Bse

fO

BRSET3
3
8TB

13

1
3

I

B

r
2

BSET3
Bse

l'
I'

B.RSET4. BSET4
10

A

C
UlXL_

J'

BRCLR3· BCLR3
10
BTB 2
Bse

I

1011

DIR

J,IL

J,1

~.~

10
.
8RCLR4
3
BTB

2

2

2

'f,Rsm \:

3

Bse

BRCLR5

r
2

J

2

Bse

I

"

,

0101

NE~NH 1 2

INH I 1

E

AH
AEL

BCC
AEL

lUll.

F
1111

8TB

10

L

Bse

1

COM

14

COMA

6 J!
12

DIA

1

LSR

2

1

/9
1

1010

RTI

INH

LSRA

DTA

1

14
14

. AEL

2

AEL

RDR

2

17

2

LSRX

LSR

INH

1

2

IX 1

2
6

4

AORA

DIA 11

INH

·1

INH

I'

LSL

I·"

LSLA

4 LSLX

\4

ROLA

4 ROLX

4

- ASRA
DIA
1
. INH
~1

ROL
DIR

DEC

DIA

1

_

·2

INH

INH

1

1

2

17

IX1

IXl

INH

I2

6

2 -CLC

ROL

2

IXl [ 1

DEC

DEC
IX 1 I 1

AEL

2

I1
DIA

I
INH I 1

INCA

I·
INH 2

INCX

INC

----:-1' BCLR7 -r.----BIH

2

REL

BTB

AEL

Bse 12

1
6
2

CLR
DIA

1

CLRA
INH

14 CLRX

12
2

122

SEI
INH

IMM

EOR

1·

INH

I

2

IXI I 1

Inherent
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed INo Offset)
Indexed. 1 Byte 18-Bit) Offset
Indexed. 2 Byte 116-Bit) Offset

DIA

IMM

EOR

2

14

ADC

IMM·2

6

CPX

13

AND

AND..
EXT

I:

RSP
~
f
1

TST

2 NOP

INH

INH

2 ADD
IMM

141

BIT

3

2

TXA
INH

DIA

JMP

3

IX2

BSR

2

3

13

3

16

EOR-EXT

3

6

ADC

13

EXT

12·

IX2

I:

IMM

2

1

ADD
3

143

EXT

JMP

4
2

DIA

13

1

EXT

LOX

EXT

3

IX

0001

1

2

IX

0100

BIT

IXI

14
1
4

LOA

2

1X2

6 STA
2
IXI

EaR·.1

5

.

. 1X2

IXI

4

AND
IX

5

BIT

0101

6

LOA

1

IX

OliO

IX

01

2

1 2.

IXI

ADC·
IXI

ORA

4

EaR
1

r:-

---ro

EXT

IX2

JMP

1

1000

IX

1001

9

ORA

IX111

ADD

2

1'1.22

JSR

3
6

13

IX

AoC

1

8

A

IX

1010

IX

1011

5

ADD

3

7

STA

1

.1

EaR

5

IX2

3

141

IX1

IX2

ADC

JXIlO.

CIIH

AND

STA

3

STX

DIA

IIIIl

SBC

IXI

14 ADD

r r :r-

JSR

STX

2

EXT

3
5

DIA

LOX

I

-]41

o

IX

CMP

CPX
. , 4 CPX
IXI
1
IX

2

6

JSR

AEL

IX 1

SBC

~

SUB

5

EXT

r5

BIT

3

EXT

STA

IS--kf: ~ \9
I
,- -:T: - I'
DIA

14

CMP

5

LOA·

5

ADD

~1
IXI

2

5

1

IX2

3

EXT

3

12

F

SUB

r rI' JI:-r1
5

DIR

IX

1111

2

IX2

1

3
6

EXT

1

IX2

3

EXT

CPX

3

DIA

ADC

15

SBC

LOA

LOlA

IX2

LOX
lX2

\B

IXI

JMP

. lXl

12

1

3

IX2

2

1

JSR

2
5

JMP

B

IXI

1100

IX

1101

r:-

IX

1110

1

1

IXI

1

IX

1111

o

E

LOX

5

STX

C

IX

JSR
IXI 11

LOX

6

STX

1

F

STX

LEGEND

Abbrevietlons for Adcll1III Modes
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IX1
IX2

BIT
LOA

---T4

12

INC

CLR

3

153

3

EXT

SBC

5

STA
2..........lllil.

2

CLR

14

14

L_

LOX

··G
1

IXI

TST
'~
2

BIL

IXI

11

3

CMP

2·

1

INC

IMM

DIA

1X2

6

1

f2

AEL

2

INH

1

I 1: .-~

INH

SEC

16

BMI

2

1~4-~
BMC

INH

LSL

EXT

/52

SUB

r r r

DIR

IMM·2

lL.'_

2 TAX

1

i6

ROL

2

- T,

DECX

1

LSL

2

\'

INH

16
ASR
I 1

DIA

4 AND

2 LOA

ROR

/63

IXI
1110

l

1101

SUB

CPX

2

~ p:f

LSR

1

IXI I 1

ASR

DIA

SBC

2

AND

2
LL...
ROR

2

17

INH

1

14 DECA I
1

ASRX

1

INH

1.7

RORX

DIA

/'3

r r

IMM

INH

IX 1 I 1

SUB

2

14

2 ·CPX

SWI

COM

--J7f6
INH

ASR

2

~2

BHCS

IMM
IMM

COM X

•2

D

1100

14-~J:-·CMP
CMP

:> CMP
..

BIT

BHCC

2

I

IMM

INH

2 SBC
12

1

INH

1011

S.UB

REI

BNE

BRCLR7

2

6• NEG

NEG ,X1

--'MM. I
DIR
EXT
ABC

r-4,

BCS

BEC
2
.Bll

BSET7

0110

ReaiMer/MemiMy
IX2

Control
IttIi

1£0

INH

6

BLS

2
4

J3~2'-14
oBRSET7

01~1

6

AFI

o
1101

INH

. IX

IXI

5

RTS

.J:
1 --I:
r -~
14 . -:I:

BCLR5

BRSET6: . BSET6
3
BTB 2
Bse

DIA

INH

BHI

[4----

14

2

BSE1~c 14 BP~i!.ELL
1.

-I' .

BTB

l0

REL

2

BTB
._ 2
O---M

13~

--r
0100

BRN

2

14

~2

BCLR4

INH

.. BRA Js-~
NEG
NEG

10
B_RSET2. ~
BSET2
.
.3.
BTB
..JISC. >1

9

o""0
o(")

Bse

:BCLRO

--.l ·---1'

0111

1010

2

8TB

3

7

n

BTB

3

6

1001

~

3

,

3
0011

5

BSETO

3

0010

0101

BRSETO.

Read-Modify-Write

REL

fa J' . I" . .
14
110-1'
11~RSET1. ·1'BSET1-T4

2

3:

":'1

BRCLRO

0001

4
..J!!lXl

~

I &r.nch

lofC"f~

M~moo'
Bytes

~

4
•
1

'f.'9

~ ~,"H_N
Opeode in Binary

SUB

IX

lJUUU ---

"

Address Mode

s:

(')
0)
OQ
Q

U'I

::J:I

N

MC6805R2

functions, these instructions cannot be used to set
or clear a DDR bit (all "unaffected" bits would be
set). It is recommended that all DDR bits in a port
be written using a single-store instruction.

instruction allows the program to branch based on the
condition of any readable bit in the first 256 locations of
memory. The span of branching is from -125 to + 130
from the opcode address. The state of the tested bit is
also transferred to the carry bit of the condition code
register.

BIT TEST AND BRANCH

The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear) is
included in the opcode. The address of the byte to be
tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third
byte is added to the PC if the specified bit is set or cleared
in the specified memory location. This single three-byte

INHERENT

In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this mode: These instructions are one byte long.

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS

Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to + 7.0

V

Input Voltage
Self-Check Mode
(TIMER Pin Only)

Vin

- 0.3 to + 15.0

V

Operating Temperature Range
MC6805R2
MC6805R2C
MC6805R2V

TA

TL to TH
oto + 70
-40 to 85
-40 to 105

°c

Tsta

-55 to +150

°c

Rating

Storage Temperature Range
Junction Temperature
Plastic
PLCC
Cerdip

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, itis advised
that normal precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. For proper operation it is recommended the Vin and Vout be constrained to
the range VSS",,(Vin and Vout)~VCC. Reliability of operation is enhanced if unused inputs. except EXTAL, are tied to an appropriate
logic voltage level (e.g., either VSS or VCC).

°c

TJ
50
150
175

THERMAL CHARACTERISTICS

Characteristic
Thermal Resistance
Plastic (P Suffix)
PLCC (FN Suffix)
Cerdip (S Suffix)

Symbol

Value

Unit
°CIW

6JA
60
100
60

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in °C can
be obtained from:
TJ=TA+(PD 0 BJA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
BJA
Junction-to-Ambient, °C/W
PD
= PINT+ PPORT
= ICC x VCC, Watts - Chip Internal Power
PINT
PPORT = Port Power Dissipation,
Watts - User Determined

For most applications PPORT _0::> CL.CL.CL.CL.Z

6
XTAL,
(VSS) NUM TIMER:
PCD:
PC1 '
PC2
PC3.
PC4 '
PC5 :
NC [
PC6 [

PA1
PAD
PB7
PB6
PB5

PB2
PB1

[) E; I~ "i: ~ (/) M

N ;::- 0 ~

CL.CL.~~~g>~~~~CL.
COLO V

000
CL.CL.CL.

M

N

... 0

0000
CL.CL.CL.CL.

MOTOROLA MICROPROCESSOR DATA
3-452

MOTOROLA

• SEMICONDUCTOR
TECHNICAL DATA

MC6805R3

Technical Summary

8-Bit Microcontroller Unit
The MC6805R3 (HMOS) Microcontroller Unit (MCU) is a member of the MC6805 Family of microcomputers. This low cost and high-speed MCU has parallel 1/0 capability with pins programmable
as input or output. This publication contains condensed information on the MCU; for. detailed information, refer to M6805 HMOS, M146805 CMOS Family User's Manual (M6805UM(AD2)) or contact
your local Motorola sales office.
Refer to the block diagram for the hardware features and to the below list for additional features
available on the MCU.
• Internal 8-Bit Timer with 7-Bit Prescaler
• Vectored Interrupts
• On-chip Oscillator
• Self-Check Mode
• Memory Mapped 1/0
• 3776 Bytes of ROM
• Versatile Interrupt Handling
• 112 Bytes of RAM
• True Bit Manipulation
• 24 Bidirectional 1/0 Ports
• Bit Test and Branch Instruction
• AID Converter

II

BLOCK DIAGRAM

TIMER

Port
A
1/0
Lines

POrt
B
I/O

Lines

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

Accumulator
Port
A
Reg

Data
Olr
Reg

CPU
Control

Index
Register

PDO/ANO
POlIANI
P02/AN2 Port
0
P03/AN3
PD4IVRL Input
Lines
P05IVRH
PD6/i'NU
POl

X
Condition
Code
Register
Stack
POinter

Port
B
Reg

Data
Olr
Reg

CC

CPU

S

4

Program
Counter
High
PCH

8

Program
Counter
Low

ALU

PCO
PC1
PC2
PC3
PC4
PC5
PC6
PCl

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-453

Port
C
1/0
Lines

MC6805R3

8.0

SIGNAL DESCRIPTION
N

7.0

VCCANDVSS
Power is supplied to the microcomputer using these
two pins. VCC is + 5.25 volts (± a.5a) power, and VSS is
ground.

~

6.0

::l
C"

4.0

INT
This pin provides the capability for asynchronously applying an external interrupt to the MCU. Refer to INTERRUPTS for more detailed information.

2

~

20

0

1.0

::c

Q)

~
u...

'0

3.0

0

EXTAL,XTAL
These pins provide control input for the on~chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal (depending upon selected
manufacturing mask option) is connected to these pins
to provide a system clock.

I

VCC=525V
TA = 25°C

>c: 5.0

u

0

20

10

50,

40

30

60

70

80

Resistance (k!ll

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only

RC Oscillator
With this option, a resistor is connected to the oscillator
pins as shown in Figure 1. The relationship between R
and fosc is shown in Figure 2.

om mended when crystals outside the specified ranges
are to be used. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. Refer to ELECTRICAL SPECIFICATIONS for VCC
specifications.

Crystal
The circuit shown in Figure 1 is recommended when
using a crystal. Using an external CMOS oscillator is rec-

External Clock
An external clock should be applied to the EXTAL input
with the XTAL input connected to ground, as shown in

Cl

~
E-------J

EXTAL - e L l
.

5

6

XTAL

(See Note) c:J

XTA.. L

MCU
EXTAL

6

AT - Cut Parallel Resonance Crystal
Co = 7 pF Max
Freq. = 4·.0 MHz @ CL = 24 pF
RS = 50 ohms Max

Crystal

Piezoelectric· ceramic resonators which
have the equivalent specifications may be
useq instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO, Cl, and RS values.

VCC
MCU
External
Clock
Input

......"vv·v---I XTAL

6 XTAL

XTAL
5 EXTAL

MCU
EXTAL

R
(See Figure 7-5)

MCU
EXTAL

No
Connection

~xternal

Clock

Approximately 25% to 50% Accuracy
Typical tcyc= 1.25 p's
External Jumper

Approximately 10% to 25% Accuracy
(Excludes Resistor Tolerancel
External Resistor

NOTE: The recommended CL value with a 4.0 MHz crystal is 27 pF maximum, including system distributed capacitance. There is an
internal capacitance of approximately 25 pF on the XTAL pin. For crystal frequencies other than 4 MHz, the total capacitance
on each pin should be scaled as the inverse of the frequency ratio. For example, with a 2 MHz crystal, use approximately 50
pF on EXTAL and approximately 25 pF on XTAL. The exact value depends on the Motional-Arm parameters of the crystal
used.

Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR DATA
3-454

MC6805R3

Figure 1. This option may only be used with the crystal
oscillator option selected in the mask option register. The
toxOV or tlLCH specifications do not apply when using
an external clock input.
TIMER
This pin is used as an external input to control the
internal timerlcounter circuitry. This pin also detects a
higher voltage level used to initiate the self-test program.
RESET
This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low.
INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO-PC3)
These 32 lines are arranged into four 8-bit ports (A, B,
C, and D). Ports A, B, and C are programmable as either
inputs or outputs under software control of the data direction registers. Port D is a fixed input port and not
controlled by any data register. Port D. has up to four
analog inputs, plus two voltage references inputs when
the AID converter is used (PD5NRH, PD4NRLl, and an
INT2 input. All Port D lines can be read directly and used
as binary input. If any analog input is used, then VRH and
VRL must be used in the analog mode. Refer to PROGRAMMING and ANALOG-TO-DIGITAL CONVERTER for
additional information.

When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Care must
be exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (zero) and, also, to the latched output
when the DDR is an output (one). Refer to Table 1 for
1/0 functions and to Figure 3 for typicaL..EQ£t circuitry.
Port D provides reference voltage (INT2) and multiplexed analog inputs. Port D can always be used as digital
input and may be used for analog if VRH and VRL are
connected to the appropriate reference voltage. The VRH
(PD5) and VRL (PD4) are internally connected to the AID
resistor.

Table 1. I/O Pin Functions
Data
Direction
Register
Bit

Latched
Output
Data
Bit

1
1
0

0
1
X

Output
State
0
1
Hi-Z**

Input
To
MCU

0
1
Pin

**Ports Band C are three state ports. Port A has optional internal
pullup devices to provide CMOS data drive capability.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
Ports A, B, and C are programmable as either input or
output under software control of the corresponding data
direction register (DDR). Port D lines are input only. The
port 1/0 programming is accomplished by writing the
corresponding bit in the port DDR to a logic one for output
and a logic zero for input. On reset, all the DDRs are
initialized to a logic zero state to put the ports in the input
mode. The port output registers are not initialized on
reset and should be written to before setting the DDR
bits.

MEMORY
The MCU is capable of addressing 4096 bytes of memory and 1/0 registers. The memory map is shown in Figure
4. The locations consist of user ROM, self-check ROM,
user RAM, AID registers, a miscellaneous register, and
1/0. The interrupt and reset vectors are located from $FF8
to $FFF.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer

Internal
Connections

Figure 3. Typical Port I/O Circuitry and
Register Configuration

MOTOROLA MICROPROCESSOR DATA

3·455

II

MC6805R3

o
000

Timer
RAM
(128 Bytes)

127
128

7654.3210

$000

1/0 Ports

0

Port A Data Register

$000

1

Port B Data Register

$001

$07F

2

Port C Data Register

$002

$080

3

Port 0 Data Register

$003

4

PortADDR*

5

PortB DDR*

$005*

6

PortCDDR*

$006*

Main User
ROM
(3768 Bytes)

$F37
$F38

3895
3896

II

I§

Self Check
ROM
(192 Bytes)

4087

Interrupt
Vectors

$FF7
$FF8

4092

~------

$FFB
$FFC

4093

f--

SWI

- -- -RESET

Not Used

$007

Timer Data Register

$OO!

9

Timer Control Register

$009

10

Miscellaneous Register

$OOA

11

$OOB

Not Used.
(3 Bytes)

14

$FF9
$FFA

External Interrupt

7
8

$OOD

13

~------

4094
4095

* Caution:

Timer Interrupt

$004*

$FFD
$FFE
$FFF

15
16

AI D Control Register

$OOE

AID Result Register

$OOF
$010

RAM
(112 Bytes)
. Stack
(31 Bytes Maximum)

+

127

$07F

Data direction registers (DDRs) are write-only; they read as $FF.

Figure 4. Memory Map
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.

an effective address. The index register may also be used
as a temporary storage area.
7

NOTE

x

Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

PROGRAM COUNTER (PC)
The program counter is a 12-bit register that contains
the address of the next byte to be fetched.
11

a

8 7

PCH

REGISTERS
The MCU contains the registers described in the following paragraphs.

ACCUMULATOR (A)
The accumulator is a general purpose 8-bitregister
used to hold operands and results of arithmetic calculations or data manipulations.

A

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may be added to an 8- or 16-bit immediate value to create

STACK POINTER (SP)
The stack pointer is a 12-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
The seven most-significant bits of the stack pointer are
permanently set at 0000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to 15
levels of subroutine calls (less if interrupts are allowed).
11

5 4

I I I I I I I I
0

0

0

MOTOROLA MICROPROCESSOR DATA
3-456

I

PCl

0

0

1

0

sp

I

MC6805R3

CONDITION CODE REGISTER (CC)

Carry/Borrow (C)

The condition code register is a 5-bit register in which
four bits are used to indicate the results of the instruction
just executed. These bits can be individually tested by a
program, and specific actions can be taken as a result of
their state. Each bit is explained in the following paragraphs.

When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and during shifts and
rotates.

SELF CHECK
Half Carry (H)

The self check is initiated by connecting the MCU as
shown in Figure 5 and then monitoring the output of port
C (bit 3) for an oscillation of approximately 7 Hz. The
following test are executed automatically:
I/O - Functionally exercise I/O ports,
RAM - Walking bit test,
ROM - Exclusive OR with ODD "1st" parity result,
Timer - Functionally exercise timer,
Interrupts - Functionally exercise external and timer
interrupts, and
AID Converter - Functionally test the Analog-to-Digital
Converter.
The RAM, ROM, and the A/D test can be called by a user
program. The Timer test may be called if the timer input
is the internal clock. Table 2 shows the status ofthe LEOs
as a result ofa failure. Port C is tested only once (just
after reset). If port C fails, no lights will appear.

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)

When this bit is set, the timer and external interrupt is
masked (disabled). If an external interrupt occurs while
this bit is set, the interrupt is latched and is processed as
soon as the interrupt bit is cleared.
Negative (N)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative
(bit 7 in the result is a logic 1).
Zero (Z)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.
RESET

r

.1

~
1
VSS
10-....
I'FT 2

mTI

3 INT

...L.

5.25V

1.0 I'F

~ -L.'t

-

~~

10 k

LED .... ~ .. 512°
LED.

~

"?'0!r ....

""LED. ' l ...~100

..

*25
400E--§ XTAL

MHZ£ NUM IN/C)··
= 8
TIMER

......

10V

4 Vec
5
EXTAL

......

LED .. 'l"5'll2

PA5

~

PA4

E..

PA3 36
PA2 35
PAl 34
PAO 33

9 PCO

PB7 32
PB6 31

11 PC2

PB5

~

12 PC3

PB4

~

...ll

PC4

PB3 28

~ PC5

PB2 27

PC6

PBl

~

16 PC7

PBO

~

~

---

P07

~ P06/IINT21

Y

40

1L-

10 PCl

----l.?

O.lI'F

PA7
PA6

19 P05

PDQ 24
POl 23
P02 22

20 P04

P03 21

J.

• This connection depends on clock oscillator user selectable mask option. Use jumper if the RC mask option is selected.

Figure 5. Self-Check Connections

MOTOROLA MICROPROCESSOR DATA
3-457

II
.

MC6805R3

certain level (VLVI). The only requirement is that the VCC
must remain at or below the VLVI threshold for onetcyc
minimum.
In typical applications, the VCC bus filter capacitor will
eliminate negative-going voltage glitches of less than one
tcyc. The output from the low-voltage detector is connected directly to the internal reset circuitry. It also forces
the RESET pin low via a strong discharge device through
a resistor. The internal reset is removed once the power
supply voltage rises above a recovery level (VLVR) at
which time a normal power-on reset occurs.

Table 2. Self-Check Error Patterns
LED Meanings

PCO PC1 ··PC2 PC3
1
0
1
0
1
0

1
1
0
1
0
1
0
0
0
0
0
All Flashing
0

Remarks (.1: .LED ON; 0: LED OFF)

Bad I/O
Bad Timer
Bad RAM
Bad ROM
Bad AID
Bad Interrupts or Request Flag
Good Device

0

0
0
0

0
0

Anything else Bad Part, Bad Port C, etc.

INTERRUPTS

RESETS

II

The MCU can be reset three ways: (1) by initial powerup (2) by the external reset input (RESET) and (3) by an
optional, internal, low-voltage detect circuit. The .RESET
input consists mainly of a Schmitt trigger that senses the
line logic level.
POWER-ON-RESET (POR)

An internal reset is generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power turn-on conditions and
should not be used to detect any drop in the power supply
voltage. A delay ~f tRHL milliseconds is required before
allowing the RESET input to go high. Connecting a capacitor to the RESET input (Figure 6) typically provides
sufficient delay.

The MCU can be interrupted four different ways: (1)
through the external interrupt IRQ input pin, (2) with the
internal timer interrupt request, (3) using the software
interrupt instruction (SWI), or (4) the external port D bit
6 (INT2) input pin.
Interrupts cause the processor registers to be saved on
the stack and the interrupt mask (I bit) set to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and then
normal processing resumes. The stacking order is shown
in Figure 7.
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.
NOTE

The current instruction is considered to be the one
already fetched and being operated on.

EXTERNAL RESET INPUT

The MCU is reset when a logic zero is applied to the
RESET input for a period longer than one machine cycle
(t cye l. Under this type of reset, the Schmitt trigger switches
off at VIRES - to provide an internal reset voltage.
LOW-VOLTAGE INHIBIT (LVI)

The optional low-voltage detection circuit causes a reset of the MCU if the power supply voltage falls below a

When the current instruction is complete, the processor
checks all pending hardware interrupts and, if unmasked
(I bit clear), proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Masked
interrupts are latched for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.

Pin 2

1. l'F - -.....-~
Typical

0

(Optional)
POR
Delay
Capacitor
Charging
Current

* Disable

LV)

Source

Figure 6. RESET Configuration

MOTOROLA MICROPROCESSOR DATA
3-458

MC6805R3

I
Pull

n-4

I

1

1

1

I

1

I

Condition Code Register

n- :;

Accumulator

n+2
n+ 1

n-2

I ndex Register

n+3

n-1

1

I

1 . 1

11

1

I

PCH*

PCl *

n+4
n+5

Push

* For subroutine calls, only PCH and PCl are stacked.

Figure 7. Interrupt Stacking Order

If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt Is serviced first. The SWI is executed 'the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 8 for the reset and interrupt
instruction processing sequence.
TIMER INTERRUPT
If the timer mask bit (TCR6) is cleared, then, each time
the timer decrements to zero (t~ansitions from $01 to $00),
an interrupt request is generated. The actual processor

interrupt is generated only if the interrupt mask bit of the
condition code register (CCR) is also cleared. When the
interrupt is recognized, the current state of the machine
is pushed onto the stack and the I bit in the CCR is set;
masking further interrupts until the present one is serviced. The contents of the timer interrupt vector, containing the location of the timer interrupt service routine, is
then loaded into the program counter. At the end of the
timer interrupt service routine, the software normally executes an RTI instruction which restores the machine state
and starts executing the interrupted program.

1-1 (in CCI
07F-SP
O-DDRs
CLR \lilT Logic
FF-Timer
7F - Prescaler
7F.-TCR
7F-MR

Load PC From:
SWI: FFC/fFD
(NT: FFAI FFB
Timer or
INT2: FF8/ FF9

Figure 8. Reset and Interrupt Processing Flowchart

MOTOROLA MICROPROCESSOR .DATA
3-459

II

MC6805R3

EXTERNAL INTERRUPT
The external interrupt is intern~ synchronized and
then latched on the falling edge of INT and INT2. Clearing
the I bit enables the external interrupt. The INT2 interrupt
has an interrupt request bit (bit 7) and a mask bit (bit 6)
in the miscellaneous register (MR). The INT2 interrupt is
inhibited when the mask bit is set. The INT2 is always
read as a digital input on port D. The INT2 and timer
interrupt request bits, if set, cause the MCU to process
and interrupt when the condition code I bit is clear. The
. following paragraphs describe two typical external interrupt circuits.

I

signal that can be recognized by the TIMER or INT pin
logic is dependent on the parameter labeled tWL, tWH.
Refer to TIMER for additional information.
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. If the I bit
is zero, SWI executes after the other interrupts. The SWI
execution is similar to the hardware interrupts.

TIMER

Zero-Crossing Interrupt
A sinusoidal input signal (fINT maximum) can be used
to generate an external interrupt (see Figure 9a) for use
as a zero-crossing detector (for negative transitions of
the ac sinusoid). This type of circuit allows applications
such as servicing time-of-day routines and engaging/disengaging ac power control devices. Off-chip, full-wave
rectification provides an interrupt at every zero crossing
of theac signal and, thereby, provides a 2f clock.
Digital-Signal Interrupt
With this type of circuit (Figure 9b). the INT pin can be
driven by a digital signal. The maximum frequency of a

The MCU consists of an 8-bit software programmable
counterdriven by a 7-bit software programmable prescaler. The various timer sources are made via the timer
control register (TCR). The 8-bit counter may be loaded
under program control and is decremented toward zero.
When the timer reaches zero, the timer interrupt request
bit (bit 7) in the timer control register (TCR) is set. Refer
to Figure 10 for timer block diagram;
The timer interrupt can be masked (disabled) by setting
the timer interrupt mask bit (bit 6) inthe TCR. When the
I bit in the condition code register is cleared and TCR bit
6 is cleared, the processor receives the interrupt. The
MCU responds to this interrupt by 1) saving the present

(e) Zero-CrOllling Interrupt

(b) Digital,Signal Interrupt

Vee
In~eut

(Current .

TTL

(fINT Max ..) ~Llml!lng)
3 iiiJT
Rs1 MO
ae Input
R
O!: 10 V
.
0.1-1.0
aep-p
I'F

4.7 K

Level
3 iN1'
Digital--.....~
Input

MCU

rv

MCU

Figure 9. Typical Interrupt Circuits

External
Input

Cleared by
TCR3

Write

Read

Interrupt

Software Functions
NOTES:
1. The prescaler and 8-bit counter are clocked on the rising edge of the internal clock (phase two) or external input.
2. The counter is written to during data strobe (oS) and counts down continuously.

Figure 10. Timer Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-460·

MC6805R3

CPU state on the stack, 2) fetching the timer interrupt
vector,and 3) executing the interrupt routine. The timer
interrupt request bit must be cleared by software. Refer
to RESETS and INTERRUPTS for additional information.
The prescaler is a 7-bit divider which is used to extend
the maximum length of the timer. To avoid truncation
errors, the prescaler is cleared when TCR bit 3 is set to
a logic one; however, the TCR bit 3 always reads as a
logic zero to ensure proper operation with read-modifywrite instructions.
The timer continues to count past zero, falling from $00
through $FF, and continues the countdown. The counter
can be read at any time by reading the timer data register
(TDR). This allows a program to determine the length of
time since a timer interrupt has occurred without disc
turbing the counting process. TDR is unaffected by reset.
SOFTWARE CONTROLLED MODE
The timer prescaler input can be configured for three
different operating modes plus a disable mode, depending on the value writtentoTCR control bits 4 and 5 (TCR4
and TCR5). The following paragraphs describe the different modes.
Timer Input Mode 1
When TCR4 and TCR5 are both programmed to zero,
the timer input is from the internal clock (phase two) and
the timer input pin is disabled. The internal clock mode
can be used for periodic interrupt generation as well as
a reference for frequency and event measurement. During the WAIT instruction, the internal clock to the timer
continues to run at its normal rate.

TCR7 - Timer Interrupt Request
Used to indicate the timer interrupt when it is logic
one
1 = Set when the timer data register changes to all
zeros
0= Cleared by external reset, power-on reset, or
under program control
TCR6 - Timer Interrupt Mask
Used to inhibit the timer interrupt
1 = Interrupt inhibited
0= Interrupt enabled
TCR5 - External or Internal
Selects input clock source
1 = External clock selected
0= Internal clock selected (fosc/4)
TCR4 - TIMER External Enable
Used to enable external TIMER pin
1 = Enables external timer pin
0= Disables external timer pin
TCR3 - Prescaler Clear
Write only bit. Writing a one to this bit resets the
prescaler to zero. A read of this location always indicates a zero.
TCR2, TCR1, TCRO~ Prescaler Select Bits
Decoded to select one of eight outputs of the prescaler
Prescaler

Timer Input Mode 2
When TCR4 = 1 and TCR'5 ~ 0, the internal clock and the
timer input signals are ANDed to form the timer input.
This mode can be used to measure external pulse widths.
The active high, external pulse gates in the internal clock
for the duration of the external pulse. The accuracy of
the count is ± 1.
Timer'lnput Mode 3
When TCR4 = 0 and TCR5 = 1, no prescaler input frequency is applied to the prescaler and the timer is disabled.
Timer Input Mode 4
When TCR4 and TCR5 are both one, the. timer input is
from the external clock. The external clock can be used
to count external events as well as to provide an external
frequency for generating periodic interrupts.
TIMER CONTROL REGISTER (TCR) $009
This is an 8-bit register that controls various functions
such as configuring operation mode, setting ratio of the
prescaler, and generating timer interrupt request signal.
Bit 3 is a write only bit.
7

6

1 TCR7·1 TCR6
RESET:

o

.1

5

4

TCR5

TCR4

u

u

TCR3

TCR2

TCRl

TCRO

u

u

u

Divide By

TCR2

TCR1

TCRO

0

0

0

1

0
0

0

1

2

1

0

4

0

1

1

8

1

0
0

0

16

1

32

1

1

0

64

1

1

1

128

1

ANALOG-TO-DIGITAL CONVERTER
The chip resident 8-bit analog-to-digital (AID) converter
uses a successive approximation technique as shown in
Figure 11. Four external analog inputs can be connected
to the AID through a multiplexer via port D. Four internal
analog channels (VRH - VRL, VRH- VRL/2, VRH - VRL/4,
and VRL) may be selected for calibration. The accuracy
of these internal channels may not meet the accuracy
specifications of the external channels.
MUltiplexer selection is controlled by the AID control
register (ACR) bits 0, 1, and 2. Refer to Table a for multiplexer selection. The ACR is shown in Figure 11. The
converter uses 30 machine cycles to complete a conversion 01a sampled analog input. When the conversion is
complete, the digital value is placed in the AID result
register (ARR); the conversion is flag set; selected input
is sampled again; and a new conversion begins. When
ACR7 is cleared, the conversion in progress is aborted
and the selected input is sampled for five machine cycles
and held internally.

MOTOROLA MICROPROCESSOR DATA

3-46"

II

MC6805R3

Table 3. A/D Input MUX Selection
AID Control Register

to $FF. An input voltage equal to or less than VRl, but
greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded. Each analog input
source should use VRH as. the supply voltage .and be
referenced to VRL·for the ratiometric conversion: To
maintainfuHaccuracy of the. A/D, three requir.ements
should be followed: (1) VRH shouldbeequql to. or less
than VDD,(2) VRL should be equal.to or greater than VSS
but less than maximum specifications; and (3) VRH-VRL
should be equal to or greater than 4 volts.
The AID has a built-in 112 LSB offset intended to reduce
the· magnitude of the quantizing error to ±,1/2 LSB,rather
than + 0, -1 LSB with no offset. This implies that, ignoring errors, the transition point from $00 to $01 occurs
at 112 LSB above VRl. Similarly, the transition from $FE
to $FF occurs 1-1I2,.1SB belowVRH, ideally.

AID Output (Hex)

ACR2

ACR1

ACRO

Input
elected

Min

Typ

Max

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

ANO
AN1
AN2
AN3
VRH*
VRL*
VRH/4*
VRH/2*

FE
00
3F
7F

FF
00
40
80

FF
01
41
81

*Internal (calibration) levels

The converter usesv'RH and VRl as reference voltages.
An input voltage equal to or greater than VRH conv~rts

I

DIA
15 kG (Typl

PDQ/ANO

1-01-8
Select
Multiplexer

PD1/AN1
PD2/AN2
PD3/AN3

AID

AID

Result
L-~-'---'_""""-""""'''''''''_--' Register

Figure 11. A/D Block Diagram

INSTRUCTION SET

Function

The MCU hasasetof 59 basic instructions which can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

Mnemonic

Add Memory and Carry to A

,ADC

Subtract Memory

SUB

Subtract Memory from A with Borrow

SBe

AND Memory to A

AND

REGISTER/MEMORY INSTRUCTIONS,

OR Memory with A

ORA

. Most of these instructions use two operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using orie of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand."Refer to the following list of instructions~

Exclusive OR Memory with A

EOR

Arithmet'ic 'Compare A with Memory

CMP

Arithmetic Compare X with Memory

CP:X

Bit Test Memory with A (Logical

~ompare)

Jump Unconditional,
Function
Load A from'Memory

,

Mnemonic

J~mp to Subroutine

BIT
JMP

,

JSR

LDA

Load X frOm Memory

LDX

READ-MODIFY-WRITE INSTRUCTIONS

Store A in Memory .

STA

Store X in Memory

STX

Add Memory to A

ADD

These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (1ST) instruction is an exception to the

MOTOROLA MICROPROCESSOR DATA '
3~462

MC6805R3

read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.
Function

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Complement
Negate (2's Complement)
Rotate Left Thru Carry
Rotate Right Thru

~arry

branch functions are all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the ca rry bit of the condition
code register. Refer to the· following list for bit manipulation instructions.
Mnemonic

Function

,Branch if Bit n is Set

BRSET n (n=O ... 7)

COM

Branch if Bit n is Clear

BRCLR n (n=O ... 7)

NEG

Set Bit n

BSET n (n=O ... 7)

ROL

Clear Bit n

BCLRn(n=0 ... 7)

ROR

Logical Shift Left

LSL

CONTROL INSTRUCTIONS

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.

BRANCH INSTRUCTIONS

Function

This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list for branch instructions.
Function

Branch Always
Branch Never

Mnemonic

BRA
BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

Branch if Carry Clear
(Branch if Higher or Same)
Branch if Carry Set

BCC
(BHS)
BCS

(Branch if Lower)

(BLO)

Branch if Not Equal

BNE

Branch if Equal

BEQ

Branch if Half Carry Clear

BHCC

Branch if Half Carry Set

BHCS

Branch if Plus

BPL

Branch if Minus

BMI

Branch if Interrupt Mask Bit is Clear

BMC

Branch if Interrupt Mask Bit is Set

BMS

Branch if Interrupt Line is Low

BIL

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

BIT MANIPULATION INSTRUCTIONS

The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space, where
all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear and bit test, and

Mnemonic

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

CLC

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

Reset Stack Pointer

RSP

No-Operation

NOP

OPCODE MAP SUMMARY

Table 4 is an opcode map for the instructions used on
the MCU.

ADDRESSING MODES
The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code coversion tables, and scaling tables anywhere in the memory
space. Short indexed accesses are single byte instructions, while the longest instructions (three bytes) permit
accessing tables throughout memory. Short and long absolute addressing is also included. Two-byte direct addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

MOTOROLA MICROPROCESSOR DATA
3-463

I

•

Table 4. Opcode Map

Bit Manipulation
BTB
BSC

;:;;;;-~

~ ~BRSEJPB
10

,

0001

2

0010

3

oon
4
0100

3:

5
0101

d
::a

6

o

o

w

§

0110
7
0111

~1

~

EJ:&

9

1001

10
BRCLR4
3
BT8

I~RSEJiB

-7_

A
1010

10
BRCLR5
3
BTB
12.

7

o"'tI
::a
o
n

m

o
o
o::a
c

l>
-I
l>

B
1011

lfoo
Pol

1

11~0
F
1111

2

BSE1~c

;

NEG
OIR

4

NEG
1
INH

01~1

7

NEG
1

INH

BHI

BLS
REL
BCC
REI

6

4

4

2 COM
OIR

COMA
1
INH

COMX
1
INH

7

2 COM

6

4

4

7

LSR
2
DTR

LSRA
1
INH

1

LSRX
INH

1

INH

2

,X1

1

COM

6

IXI

INH

11

6

LSR

RTS

LSR

1

IX

AND
IMM
2

1

2

L
4

4

7

RORA
1
INH

RORX
I
INH

2 ROR

6

4

4

7

ASR
2
OIR

ASRA
1
INH

ASRX
1
INH

6

4

4

LSLA
1
INH

LSLX
I
INH

2
7

6

BNEREL _2 ROROIR
BEOREI

BHC~FI

2

LSL

OIR

4

2BCL~~c

ROLX
1
INH

4

6

4

4

DEC
2
DIR

1

BPL
REI

DEC A
INH

1

6

IXI

2

IXI

1

ASR

2

IX

IXI

1

2

IXI

1

ROL

IX I

6

DEC

IXI

1

DEC

IX

4

BCLR5
Bse

2

BMC
2
RH

2

4

6

13BRCL:~B

2 BCL~~c

10
BRSE
13
10
BRCLR7
BTB
3

2

7

4

2BSE~~c

2

7

4

BCLR7
esc
2

6

BMS
REI
BIL
BIH

2

2

INC

DIR

TST
DIR

4

4

INCA
1
INH

INCX
1
INH

4

4

1

TSTA
INH

1

7

2

6

INC

IXI

7

TSTX
INH

INC

1

IX

6

TST
2

IXI

TST

1

IX

RH

2

CLR

DIR

4

4

CLRA
1
INH

CLRX
INH
1

7

2

CLR
I~_~

--'-

IX

EXT
REL
BSC
BTB
IX
IXl

IX2

Inherent
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed (No Offset)
Indexed, 1 Byte (B-Bit) Offset
Indexed, 2 Byte (l6-Bit) Offset

" SUB
3
EXT

b SUB
3
IX2

:

SUB

• SUB
1
III

5

6

5

4

2

CMP
DIR

3

EOR
IMM

7

CMP
EXT

4

CMP
IXI

SBC

5

SBC

6

4

5

6

DIR

AND
DIR
2

" AND
EXT
3

2

3
3

CPX
AND

3
6

4

5

2 BIT DIR

3

BIT
EXT _3

4

5

6

LDA
OIR
2
STA
OIR
2

LDA
EXT
3
., STA
3
EXT

4

5

EOR
OIR
2

EOR
3
EXT

3
6

3

4

IX2

5

4

2 AND IX1

1

5

4

4

1

5 ORA

4 ORA

" ADD
3
EXT

b ADD
IX2
3

1

ADD
DIR

7

8

2
2

BSR
REL

DlR

STX

6

2 __ DIR

-

3

JSR
EXT

" LDX
EXT
3

LDX
DIR
2
5

--

8

JSR
2
4

TXA

IX2

3

~

j ,f,'5

IXI

2

" ADD
2
IXI
4

JMP
3
EXT

" JMP

IX2

2

" JSR IX2
3

6

3

b

cJl1
0;'00

IX

01~~

1

6

IX

0110

IX

7
0111

IX

1000

8

4

ADC

4

JMP
DIR
2

LDX
IMM
2
~

3

EOR

IX2

6 ORA

2

1

2

" ORA
EXT
3

IXI

1

" ADC
IXI
2

• ORA
DIR
2

IMM

EOR

IXI

I~

2 ORA
IMM
2

2

BIT IX
LDA

5

ADC
EXT
3

0010

4

LDA

IX2

5

IX
IX

AND

5 STA

ADC
2
DIR

2 ADD

1

., STA
2
IXI

EOR

I
0001

CPX

2

4

2

SBC

IX2

6

4

1

BIT IX-

2

5

3 STA

3

IXI

2

IX2

~

IX

4

" CPX
2
IXI

BITI~
LDA

CMP
I

IX2

6

4

~

4

2

" SBC
EXT
3
CPX
EXT
3

IX1

CMP
IX2

SBC
DIR
2
CPX

IX

3

ADC
IMM
2

LDX
IX2

3

STX
STX
__ EXT ~~2

JMP

IXI

ADC

1

B
1011
C
1100

JSR

IX

D
1101

IX

E
1110

1'-

1111

1
•
I

LDX

5

STX

2_

IXI

A
1010

IX

1

IXI

STX

1001

IX
ADD

4

JSR

6

IX

, JMP
1
IX

" LDX
2
IXI

2

9

1

F

LEGEND

Abbreviations for Addre88 Modes
INH
IMM
DIR

SUB
2
DIR
4

2

2

6

(LR

li,l

E

SEC
INH
1
2
CLI
1
INH

REL
6

1110

2

1" SEI
INH
1
2
RSP
INH
1
2
NOP
1
INH

BMI
REL

4

2
CLC
INH

IX

lfol

5

TAX
1
INH
2

LSL

LDA
IMM

7

6

ROL

2

IX

6

LSL

7

DECX
INH

1

BI~M_M

2

ROR

6

ASR
7

ROLA
I
INH

7

CPX
2
IMM

IX

IXI

1roo

DIR
8

A

1010

2

SWI
1
INH

Regieter/MImOfV
EX
1X2

lOll

IMM

1" SUB
12
IMM
2
CMP
2
IMM
2
SBC
IMM
2

RTI

BCS
REI

4

2

IXI

• NEG
1
IX

REI

ROL
2
DIR

2

9

6

2 NEG

1

6

BSE1~c

01~0

Control
INH
9
1001

6

BHCS
2
REI

2

INH
8
1000

IX

01~1

BR~FL

4

7

lla

0:"

7

13BRSE~ 2BSE~t:
10

7

Read-Modify-Write
IXI
INH

4

4

1~

INH

4

7

~

n

J,1

2 BRAREL

3:

::a

[2lR

ri,o

2 BSE~~e

BRCLRO 2 BCL~~c
2
3
BTB
10
4
BRSE
3
JT'B 2 BSE~~c 2
10
7
4
BRCL
3
:T'B 2 BCL~~e 27
10
4
BRSE
-13
JtB 2 BSE~~c 2
4
I!'.
BRCL
13
:1B 2BCL~~e 2
10
7
4
BRS
LBSE~k _2
13
10
7
4
BRCL
13
:iB _ 2 BCL~~i: 11
4
7
112.

13BRSEJ~

Branch
REL

#

,I Cy''''

Mnemonic
Bytes

4

..
1

SUE
IX

~

Opo,o.

,0

H,'-i~1

Opcode in Binary

0000 --' - - - - - - - - - - Address Mode

s:

C')

~-

o

C.1I

~

W

MC6805R3

IMMEDIATE

INDEXED, 16-BIT OFFSET

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).

In the indexed, 16-bit offset addressing mode, the effective address is the sum ofthe contents ofthe unsigned
8-bit index register. and the two unsigned bytes following
the opcode. This addressing mode can be used in a mannersimilar to indexed, 8-bit offset except that this threebyte instruction allows tables to be anywhere in memory.

DIRECT

In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.
EXTENDED

In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction.
RELATIVE

The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from - 126 to + 129 from
the opcode address.
INDEX, NO OFFSET

In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move apointer through
a table or to hold the address of a frequently referenced
RAM or 1/0 location.
INDEXED, 8-BIT OFFSET

In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
the beginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1 FE is the last location at which the instruction may
begin).

BIT SET/CLEAR

In the bit setlclear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte to which
the specified bit is to be set or cleared. Any readlwrite
bit in the first 256 locations of memory, including 1/0, can
be selectively set or cleared with a single two-byte instruction.
CAUTION

The correspol.ding DDRs for por~i\, B, and Care
write only registers (registers at $004, $005, and
$006). A read operation on these registers is undefined. Since BSET and BCLR are read"modify-write
functions, these instructions cannot be used to set
or clear a DDR bit (all "unaffected" bits would be
set). It is recommended that all DDR bits in a port
be written using a single-store instruction.
BIT TEST AND BRANCH

The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit to be tested, and its condition (set or clear), is included
in the opcode. The address of the byte to be tested is in
the single byte immediately following the opcode byte.
The signed relative 8-bit offset in the third byte is. added
to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction
allows the program to branch based on the condition of
any readable bit in the first 256 locations of memory: The
span of branching is from -125 to + 130 from the opcode
address. The state of the tested bit is also transferred to
the carry bit of the condition code register.
INHERENT

In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this mode. These instructions are one byte long.

MOTOROLA MICROPROCESSOR DATA
3-465

II

MC6805R3

ELECTRICAL SPECIFICATIONS
MAXIMU/YI RATINGS
Symbol

Value

Unit

Supply Voltage

VCC

-0.3to+7.0

V

Input Voltage
Self-Check Mode (TIMER Pin Only)

Vin

-0.3to +7.0
-0.3 to + 15.0

V

Operating Temperature Range
MC6805R3
MC6805R3C
MC6805R3V·

TA

TL to TH
o to 70
-40 to +85
-40 to + 105

°C

TstQ

-55 to + 150

Rating

Storage Temperature Range
Junction Temperature
Plastic
PLCC
Cerdip

II

°C
°C/W

TJ

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. For proper operation it is recommended the Vin and Vout be constrained to
the range VSS ~ (Vin or Vout) ~ Vee. Reliability of operation is enhanced if unused inputs except EXTAL are tied to an appropriate
logic voltage level (e.g., either VSS or Vec).

150
150
175

THERMAL CHARACTERISTICS
Characteristic

Thermal Resistance
Plastic (P Suffix)
PLCC (FN Suffix)
Cerdip (S Suffix)

Symbol

Value

Unit

°C/W

eJA
60
100
60

POWER CONSIDERATIONS
The average chip-junction temperature, Tj, in °c can
be obtained from:
Tj=TA+(POoeJA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
IlJA
Junction-to-Ambient, °C/W
Po
= PINT+ PPORT
= ICC x VCC, Watts - Chip Internal Power
PINT
PpORT = Port Power Dissipation,
Watts - User Oetermined

For most applications PPORT_a:>
0.. 0.. 0..0.. Z

U X

PA7

Vss

PB6
PB5
PB4

PA3
PA2
PA1
PAD
PB7
PB6
PB5
PEl4
PB3
PB2
PB1

XTAL
(VSS) NUM
TIMER
PCD
PC1
PC2
PC3
PC4
PC5
NC
PC6

PB3

PB2

r-- r--IN I~ til M N;::- 0- b
uc
~ a:a:tIlZZZZCO

PBl

o..o..~c.c.>~~~~o..

PBO

CDLO~

00.0
0..0..0..

PDOI ANO
PD6/1NT2

PD1/ANl
PD2/AN2

PD4IVRL

MOTOROLA MICROPROCESSOR DATA
3-472

MN_O

c
oco
0.. 0...0.. 0..

MOTOROLA

I

SEMICONDUCTOR

TeCHNICAL DATA

MC6805S2

Technical Summary

8-Bit Microcontroller Unit
The MC6805S2 (HMOS) Microcontroller Unit (MCU) is a member of the MC6805 Family of microcontrollers. This low cost MCU has parallel 1/0 capability with pins programmable as input or output. This publication contains condensed information on the MCU; for detailed information, refer to Advance Information 8Bit Microcompters (ADI997R1) or contact your local Motorola sales office.
Refer to the block diagram for the hardware features ,and to the list below for additional features available
on the MCU.
• Internal 7-Bit Timer and 15"Bit Programmable Prescaler
• Self-Check Mode
• On~chip Oscillator
• 1480 Bytes of ROM
• Memory Mapped 1/0
• 64 Bytes of RAM
• Versatile Interrupt Handling
• Serial Peripheral Interface (SPI)
• One 8-Bit and One 16-Bit Timer
• Bit Manipulation
• Bit Test and Branch Instruction
• AID Converter
• Vectored Interrupts
BLOCK DIAGRAM
PRESCAlERlIPCO

PRESCAlER2/PCI

XTAl~("1
CLOCK

EXTAl

(1)2

PAO
PAl
PA2
PA3

ACCUMULATOR

PA4

INDEX REGISTER
CONDITION CODE
REGISTER

PA5

A

PAS

STACK POINTER

PA7

PROGRAM
COUNTER
lOW
PROGRAM
COUNTER
HIGH

A/D CONVERTER
ANO/PDO
ANlIPAI
AN2/PD2

RESET
CONTROL

AlU

AN3/PD3

INTI

VRl
VRH

......+-+-+-+--+--+-.-0

PBO
SPISS

PBI
SPICl

PB2
SPID

INT2/
AN4/
VSTBY

PB3
SPID

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA'
3-473

II

MC6805S2

SIGNAL DESCRIPTION
Vce and VSS
Power is supplied to the microcontroller using these
two pins. VCC is + 5.25 volts (± O.5a) power, and VSS is
ground.

NUM
This pin is for factory use only. It should be connected
to VSS.

Crystal
The circuit shown in Figure 1(b) is recommended when
using a crystal. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time.
Externa1'clock
An external clock should be applied to theEXTAL input
with the XTAL input not connected, as shown in Figure

8.0

INT1, INT2

-;:; 7.0

These pins provide the capability for asynchronously
applying an external interrupt to the MCU. Refer to INTERRUPTS for more detailed information.

~ 6.0

:J:

These pins provide contrql input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal (depending on user selected
manufacturing mask option) is connected to these pins
to provide a system clock.

,

u

~ 5.0
::;)

~
a:

XTAL, EXTAL

I

>-

4.0

0

3.0

U

2.0

~

~

"- f"-..

CI)

0

1.0

o

o

10

20

RC Oscillator

With this option, a resistor/capacitor combination is
connected to the oscillator pins as shown in Figure 1(c).
Refer to Figure 2 for the relationship between Rand fos c.

30
40
50
RESISTANCE Ikll)

60

70

80

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only

r--_ _ _~t-2_6-f XTAL

XTAL
26

EXTAL

27

EXTAL

At-CUT PARALLEL RESONANCE
CRYSTAL
CO=7 pF MAX.
FREQ. = 4.0 MHz(a CL = 24 pF
RS = 40 OHMS MAX.

MCU
(CRYSTAL MASK
OPTION

CRYSTAL

26

EXTERNAL
CLOCK
INPUT
(TIL COMPATIBLE,
LOW IMPEDANCE
SOURCE)

MCU
(RESISTOR MASK
OPTION)

MCU
EITHER CRYSTAL
OR RC MASK
OPTION

EXTERNAL CLOCK

APPROXIMATELY 10% to 25%
ACCURACY
EXTERNAL RESISTOR
(EXCLUDES RESISTOR TOLERANCE)

EXTAL

MCU
!RESISTOR MASK
OPTION)

APPROXIMATELY 25% to 50%
ACCURACY
TYPICAL tcyc = 1.25 f.lS
EXTERNAL JUMPER

NOTE: The recommended CL value with a 4.0 MHz crystal is 27 pF, maximum, including system distributed capacitance. For crystal
frequencies other than 4 MHz, the total capacitance oli each pin should be scaled as the inverse of the frequency ratio. For
example, with 2 MHz crystal, use approximately 50 pF on EXTAL and approximately 50 pF on XTAL. The exact value depends
on the motional-arm parametes of the crystal used.

Figure 1. Oscillator Connections

MOTOROLA'MICROPROCESSOR DATA
3-474

MC6805S2

1(d). This option may only be used with the RC or XTAL
option selected.
PCO,PC1
These pins allow an external input to be used to decrement the internal timer circuit. Refer to TIMERS for
additional information.
RESET
This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low.
INPUT/OUTPUT LINES (PAO-PA7, PBO-PB3, PCO-PC1, and
PDO-PD6)
Port A, B, and C are programmable as either inputs or
outputs under software control of the data direction registers. Port D is a fixed input port and not controlled by
any data register. Port D has up to four analog inputs or
five via the mask option, plus two voltage reference inputs when the analog-to-di~ (AID) converter is used
(PD5NRH, PD4NRL) and an INT2 input. Ifthe analog input
is used, then the voltage reference pins (PD5NRH and
PD4NRLl must be used in the analog mode. Refer to
PROGRAMMING for additional information.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
Ports A, B, and C are programmable as either input or
output under software control of the corresponding data
direction register (DDR). The port I/O programming is
accomplished by writing the corresponding bit in the port
DDR to a logic one for output and a logic zero for input.

On reset, all DDRs are initialized to a logic zero state to
put the ports in the input mode. The port output registers
are not initialized on reset and should be written to before
setting the DDR bits.
Port D provides the multiplexed analog inputs, reference voltages, and INT2. These lines are shared with the
port D digital inputs. PDO-PD3 may always be used as
digital or analog inputs. The VRL and VRH lines are internally connected by the AID resistor. Analog inputs may
be prescaled to attain the VRL and VRH recommended
input voltage range.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Care must
be exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (zero) and, also, to the latched output
when the DDR is an output (one). Refer to Figure 3 for
typical port circuitry.
PORT B TOGGLE CAPABILITY
Port 80 and B1 registers have toggle capability at the
timer underflow times. Under the control of the timer
output cross-couple bit in the miscellaneous register
(MRO), the overflow pulses from timer A and B are directed to port BO and B1 data registers. See Figure 4 for
port B configuration flow chart.
An incoming toggle pulse on port 80 is allowed to
toggle the data register if port 8 DCR. bit 4 (DCR4) is
cleared. This bit is set on reset. An incoming toggle pulse
on port B1 is allowed to toggle the port B1 data register

C/)

--'z

ct2

Z~

cx::U

LULU

~z

zz

-8

Data'
Direction
Register
Bit

Output
Data
Bit

1
1
0

X

0
1

Input
Output
State

To

MCU

0
1
High-Z**

*DDR is a write-only register and reads as all "ones".
**Ports A (with CMOS drive disabled), B, and C are three-state
ports. Port A has optional internal pullup devices to provide
CMOS drive capability. See Electrical Characteristics tables
for complete information.

Pin

Figure 3. Typical Port I/O Circuitry and
Register Configuration

MOTOROLA MICROPROCESSOR DATA
3-475

II

•
PORT Bl

"TIMER OVERFLOW

JL
TOGGLE*
ENABLE - - - - - - - - - . " ,
MCU

MCU
PBl

3:

~
~

SPI
MSB

~
3:

~en

s:

n
~
"a

i

(SPICRlI

~
m
en

(I)

N

TIMER OVERFLOW ..JL

o21

g
;::
SPI

MSB

PBa

MCU.

•

<

*Toggle Enable B1 = (SPICR7·SPICR4·(PBO + DDRBO))'SPICR2'SPICR4)'CLAQ
**A or B depends on (MRO)
x Write Only Register

Figure 4. Port B Configuration

PB2

MC6805S2

under the following conditions governed by control bits
in SPI control register and SPI clock arbitration flip-flop
status.
PB1 toggle enable = (SPICR7)·SPICR4·
(PBO + DDRBO) + SPICR2·
SPICR4·CLAD
where:
SPICR7 = SPI interrupt request bit
SPICR4 = SPI operation enable bit
SPICR2 = port B1 toggle enable/start bit
CLAD = clock arbitration flip-flop output

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may be added to an 8- or 16-bit immediate value to create
an effective address. The index register may also be used
as a temporary storage area.

x
PROGRAM COUNTER (PC)

When PBl toggle enable is asserted, the MCU write to
PBl data register is inhibited. When SPI is not used, SPICR4
and CLAD are reset. Therefore, SPICR2 can directly control the port Bl toggle capability. Port toggle capability
allows action on port BO or B1 or both as a result oftimer
overflows. This method speeds up timer overflow to port
service. A write to port BO or B1 data registers is inhibited
while the individual port toggle enable is asserted.
The port B OCR consists offour status bits (DCR7-DCR4)
and four data direction bits (DCR3-DCRO). DCR4 is a toggle enable control bit for port BO. When cleared, the timer
overflow pulse causes the data register on port BO to
toggle. Port A has an 8-bit and port C has a 2-bit wide
data direction register.

MEMORY
The MCU is capable of addressing 4096 bytes of memory and I/O registers. The memory map is shown in Figure
5. The locations consist of user ROM, self-check ROM,
user RAM, five timer registers, a miscellaneous register,
two A/D registers, two SPI registers; and I/O. The interrupt
vectors are located from $FF8 to $FFF.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.
NOTE
Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

The program counter is a 12-bit register that contains
the address of the next byte to be fetched.
11

8 7

PCH

PCl

STACK POINTER (SP)
The stack pointer is a 12-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
The seven most-significantbits of the stack pointer are
permanently set at 0000011; Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum). which allows the programmer to use up to 15
levels of subroutine calls (less if interrupts are allowed).
11

I

5 4

0 / 0 / 0 / 0 / 0 /1 /1 /

0
SP

. /

CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit. register in which
four bits are used to indicate the results of the instruction
just executed. These bits can be individually tested by a
program and specific actions can be taken as a result of
their state. Each bit is explained in the following paragraphs.

Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

REGISTERS
Interrupt (I)
The MCU contains the registers described in the following paragraphs.
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.

When this bit is set, the timers (both A and B), the
external (lNT1 and INT2) interrupts, and the SPI interrupt
are masked (disabled). If an interrupt occurs while this
bit is set, the interrupt is latched and is processed as soon
as the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative (bit
7 in the result is a logic one).

7
A

MOTOROLA MICROPROCESSOR DATA
3-477

II

MC6805S2

I BYTES I

I ADDRESS I

9QQ

I ADDRESS I

SOOO
liD, AID, SPI,
TIMERS, RAM
(128 BYTES)

PORT B

SOOl

PORT C

S002

127

$07F

PORT D

$003

128

S080

PORT A DDR*

S004

PORT B DCR*

S005

PORT C DDR*

S006

NOT USED

S007

TIMER A

S008

TIMER A CONT REG.

$009

MISC. REGISTER

$OOA

PAGE 0 ROM
(128 BYTES)
255

SOFF .

256

S100
NOT USED

2495
2496

8

S9BF
S9CO

MAIN ROM
(1344 BYTES)

II

$000

PORT A

3839

4087

CI)

$OOB

TIMER B LSB

SOOC

TIMER B CONT. REG.

SOOD

AID CONTROL

$OOE

AID RESULT

SOOF

SPI DATA

SOlO

. SEFF

3840

T4088

TIMER B MSB

SFOO
SELF-CHECK
ROM
(248 BYTES)
TIMERS (A, BI.
SPI,INT2

SPI CONTROL

SFF7

NOT USED
(46 BYTES)

$FFB
$FF9

S03F

SFFA

$040

----

a:

o

IU

~~
c...

EXTERNAL INT 1

0

=>1:

a:

ffi

SFFB

USER RAM
(17 BYTES)

SWI
$FFD

~

S07F

~

SFFE
4095

(ADDRESS
STANDBY RAM**
(16 BYTES)

RAM
(64 BYTES)

$FFC

I-

1

SOll
S012

RESET

SFFF

I

S040
S04F
$050
~060

SHARED STACK RAM
(31 BYTES)

S061
S07F

*Registers are write only and read as $FF.
**Mask option

Figure 5. Memory Map
Zero (Z)

I MR7 I

When set, this bit indicates that the result of the last
arithmetic, logical, or. data manipulation was zero.

RESET:

Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmetic operation. This. bit is also affected (juring
bit test and branch. instructions, and during shifts and
rotates.'
,

MISCELLANEOUS REGISTERS (MR) $OA
This register contains control and status information
related to INT2, auxiliary counter, prescalers 1 and 2, and
timer overflow.

MRG

MR5

MR3

MR2

MRl

I MRO~

MR7 - INT2 Interrupt Request Bit
If not masked by MR6, it causes an interrupt to the
MCU, and if the I bit in the CCR is clear, the MCU will
acknowledge the interrupt.
1 = Interrupt requested
0= Interrupt not requested
MR6 - INT2 Interrupt Request Mask
1 = Inhibits INT2 interrupt request
0= Does not inhibit INT2 interrupt request
MR5 - Auxiliary Counter Status/Preset Bit
If not masked by MR4, it will drive a switch to VSS on
the RESET pin causing the MCU to reset. This bit may

MOTOROLA MICROPROCESSOR DATA
3-478

MR4

MC6805S2

be used as an auxiliary counter preset bit. If MR5 is
clear, a write of logic one will preset the auxiliary
counter, and if set, a write of logic zero will preset the
auxiliary counter.
1 =Auxiliary counter overflow
0= Auxiliary counter clear
MR4 - Watchdog Control Bit
This bit cannot be set via software. The watchdog timer
can only be disabled by reset.
1 = Watchdog timer disabled
O=Watchdog timer enabled
MR3 - Prescaler 1 Clear Bit
Presets the contents of prescaler 1 to $7F
1 = Prescaler 1 preset
0= Prescaler 1 not preset
MR2 - Prescaler 2 Clear Bit
Presets the contents of prescaler 2 to $7;:FF
1 = Prescaler 2 preset
0= Prescaler 2 not preset
MR1 - Prescaler Cross-Couple Bit
This bit controls the output of prescalers 1 and 2 and
directs them to either timer A or B clock inputs.
1 = Prescaler 1 feeds timer B clock input, and prescaler 2 feeds timer A input
0= Prescaler 1 output is used as clock input for timer
A, and prescaler 2 output is used as clock input
for timerB

MRO - Port B Toggle Cross-Couple Bit
This bit controls the overflow pulses of timers A and
B and directs them to either port BO or B1.
1 = Timer A overflow output is directed to port BO,
and timer B output is directed to port B1
0= Overflow output pulse of timer A is used as a port
B1 data register toggle clock source, and timer B
overflow output pulse is directed to port BOtoggle
clock input

SELF CHECK
The self check is initiated by connecting the MCU as
shown in Figure 6 and then monitoring the output of port
C (bit 0) for an oscillation of approximately 7 Hz. The selfcheck program exercises the CPU, 1/0, RAM, ROM, timers,
interrupts, analog-to-digital (AID) converter, and the auxiliary counter.
The RAM, ROM, and 4-channel AID test can be called
by a user program. The timer test may be called if the
timer input is the internal clock.

RESETS
The MCU can be reset four ways: (1) by initial powerup; (2) by the external reset input (RESET); (3) by 1:1 forced

CLOCK
RESET
28
+9V

27

VCC

26

--- -VCC

25
24
23
22
,AN2

21

ANl
ANO
PBO
PBl
PB2
PB3

20
10

19

11

18

12

17

13

16

14

15

PA5
PM

Rl = 6 k!l
R2 = 3 k!l
R3=200 !l
R4 = 390 !l
Cl =22 pF
C2= 1 J.lF
C3 = 0.1 J.lF

PA3
PA2
PAl
PAO

*RC Oscillator Option Shown. If 00-02 LEOs Blinking = Device Passes Test
03 Blinking = Watchdog Reset Problem

Figure 6. Self-Check Connections

MOTOROLA MICROPROCESSOR DATA
3-479

MC6805S2

220 kn
TYP.
23
100 n
TYP.

RESET

I

1 flF TYP.**

**OPTION-100 ms DELAY
TYPICAL DURING POWER UP

II

MISCELLANEOUS REGISTER

Figure 7. Reset Circuit

reset' generated by the "watchdog" counter; and (4) by
an optional internal low voltage detect circuit. The RESET
input consists mainly of a Schmitt trigger that senses the
line logic level. Figure 7 shows the MCU reset circuit.
POWER-ON-RESET (POR)

An internal reset is generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power turn-on conditions and
should not be used to detect any drop in the power supply
voltage. A delay of tRHL milliseconds is required before
allowing RESET input to go high. Connecting a capacitor
to the RESET input (Figure 8) typically provides sufficient
delay.

1

VCC

~~~~~-r_2_3-,

:::r:

1.0 flF

MCU

Figure 8. Power-Up Reset Delay Circuit

status bit (MR5) is set as a result of counter overflow, a
switch to VSS is turned on pulling the RESET pin low. A
consequent voltage drop below VIRES - on RESET causes
a reset, which in turn sets MR4. Switching to VSS when
the RESET pin is turned off allows voltage to rise above
VIRES +, after which the reset is released. RESET pin
voltage variation occurring as a result of forced reset may
be amplified externally in order to provide a reset to other
peripheral circuits in the system. The reset output from
the MCU is not TTL compatible.
LOW-VOLTAGE INHIBIT (LVI)

The optional low-voltage detection circuit causes a reset of the MCU if the power supply voltage falls below a
certain level (VLVI). The only requirement is that the VCC
must remain at or below the VLVI threshold for one tcyc
minimum.
In typical applications, the VCCbus filter capacitor will
eliminate negative-going voltage glitches of less than one
tcyc. The output from the low-voltage detector is connected directly to the internal reset circuitry. It also forces
the RESET pin low via a strong discharge device through
a resistor. The internal reset is removed once the power
supply voltage rises above a recovery level (VLVR) at
which time a normal power-on reset occurs.

EXTERNAL RESET INPUT

INTERRUPTS

The MCU is reset when a logic zero is applied to the
RESET input for a period longer than one machine cycle
(tcyel. Under this type of reset, the Schmitt trigger switches
off at VIRES - to provide an internal reset voltage.
FORCED RESET

If the auxiliary counter reset mask bit in the miscellaneous counter (MR4) is cleared and the auxiliary counter

The MCU can be interrupted seven different ways:
through the external interrupt INT1 input pin, with the
internal timer (either A or B) interrupt request, using the
software interrupt instruction (SWI), SPI interrupt request, external port D bit 6 (lNT2) input pin, or at reset.
Interrupts cause the processor registers to be saved on
the stack and the interrupt mask (I bit) set to prevent

MOTOROLA MICROPROCESSOR DATA
3-480

MC6805S2

additional interrupts. The RTI instruction causes the register contents to be recovered from the stack after which
normal processing resumes. The stacking order is shown
in Figure 9.

6

n-4

5

111

I

4

3

2

1

CONDITION
CODE REGISTER

PULL

ACCUMULATOR

n+2

n-2

INDEX REGISTER

n+3

f

n+4

n --I

1111

PCW

When the current instructionis complete, the processor
checks all pending hardware interrupts and, if unmasked
(I bit clear), proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Masked
interrupts are latched for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 10 for the reset and interrupt
instruction processing sequence.

n+5

PCL*

NOTE
The current instruction is considered to be the one
already fetched and being operated on.

n+l

n-3

Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted, but are considered pending until the current instruction is compl~te.

PUSH
*For subroutine calis, only PCH and PCl are stacked.

Figure 9. Interrupt Stacking Order

1 .1(lN CCR)

07F. SP
40. SPICR
FFFF. TIMER B
7FFF. PRES CALER 2
FO. DCRB
50. TBCR
FC= DDRC
O.DDRA
CLR INT LOGIC
FFUIMER A
7F. PRESCALER 1
50. TACR
50. MR
07. ACSR

CLEAR
INTI
REQUEST
LATCH

TIMER A, B,
INT2, SPI
LOAD PC FROM
SWI: FFC/FFC
INT: FFA/~FB
TIMER A, TIMER B,
SPI OR INT2:
FF8/FF9

LOAD PC
FROM
FFE/FFF

*MR7·MR6

(INT2)

+

TACR7·TACR6
(TIMER A)

+

TBCR7·TBCR6
(TIMER B)

+

SPICR7·SPICR6
(SPI)

Figure 10. Reset and Interrupt Processing Flowchart

MOTOROLA MICROPROCESSOR DATA

3-481

II

MC6805S2

TIMER INTERRUPT

SOFTWARE INTERRUPT (SWI)

Each interrupt, except INT1, nas a sepa~ate mask bit
which must also be cleared, in- addition to the I bit, for
the MCU to acknowledge the interrupt. The INT2, timer
A, timer B, and SPI i~terrupts each have their own independent mask bits contained in MR6, TACR6, TBCR6,
and SPICR6. The interrupt routine must determine the
source ofthe interrupt by examining the interrupt request
bits, TACR7, TBCR7, MR7, and SPICR7. These bits must
be cleared by software. The INT1 interrupt has its own
vector address. Therefore, the INT1 interrupt request is
cleared automatically, and then the INT1 vector is serviced.

The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CeR. If the I bit
is zero, SWI executes after the other interrupts. The SWI
execution is similar to the hardware interrupts.

TIMERS
The MCU has three timers and two programmable
prescalers. The timers are identified as timer A, 8, and
the auxiliary counter. Refer to Figure 12 for timers A and
8 block diagram. The following paragraphs described the
different timers.

EXTERNAL INTERRUPT
The, external interrupt is internally synchronized and
then latched on the falling edge of INT1 and INT2. Clearing the I bit enables the external interrupt. The INT2 interrupt has an interrupt request bit (bit 7) and a mask bit
(bit 6) in the miscellaneous register (MR). 'The INT2 interrupt is inhibited when the mask bit is set. The INT2 is
always read as a digital input on port D. The INT2 and
timer interrupt request bits, if set, cause the MCU to process an interrupt when the condition code I bit is clear.
The following paragraphs describe two typical external
interrupt circuits.
Zero-Crossing Interrupt
A sinusoidal input signal (fINT1 maximum) can be used
to generate an external interrupt (see Figure 11a) for use
as a zero-crossing detector (for negative transitions of
the ac sinusoid). This type of circuit allows applications
such as servicing time-of-day routines and engaging/disengaging ac power control devices. Off-chip, full-wave
rectification provides an interrupt at every zero crossing
of the ac signal and, thereby, provides a 2f clock.

TIMER A
Timer A is an 8-bit programmable counter, which can
be loaded under program control. Timer A also includes
a modulus latch which allows the timer to be "auto-reloaded." As clock inputs are received, timer A decrements
toward $00. When $00 is reached, bit 7 in the timer A
control register is set and the timer is reloaded with the
contents of the modulus latch. An overflow condition is
also generated when value $00 is reached. This state can
be used to toggle bit 0 or bit 1 of port B directly under
the control of the miscellaneous register (MRO), the SPI
control register, and the port 8 data direction register.
Setting TACR6 or the I bit in the condition control register
will prevent timer interrupts from being processed. The
timer interrupt request bit MUST be cleared by software.
There are three ways of loading data from the modulus
latch into timer A as described in the following paragrahs.
Direct Loading
When the MCU writes to timer A data register, the data
is latched by the modulus latch, and forced into the timer.
This operation requires that TACR3 be cleared.

Digital-Signal Interrupt
With this type of circuit (Figure 11 b), the INT1 pin can
be driven by a digital Signal. The maximum frequency of
a signal that can be recognized by the TIMER or INT1 pin
logic is dependent on the parameter labeled tWL, tWH.
Refer to TIMER for additional information.

Asynchronous External Event Loading
When TACR3 is a logic one, the contents of the modare transferred to the timer at the rising edge
of INT2 interrupt request bit (MR7) gated with interrupt
request mask bit (MR6). If this loading is used, care must
ulu~ch

Vec
TTL

4.7 k

LEVEL
DIGITAL
INPUT

25

INTI

MCU

lJ
(B) DIGITAL-SIGNAL INTERRUPT

(A) ZERO-CROSSING INTERRUPT

Figure 11. Typical Interrupt Circuits (lNT1)

MOTOROLA MICROPROCESSOR DATA
3,;482

MC6805S2

SELECT

SELECT
TACR4,5

yP r1

RESET
MR3

P",SCAlE

PCO

INTERNAL
CLOCK

TO MCU

II

TO MCU
SELECT
TBCR4,5

PRESCALE
POl

1
TP
i

INTERNAL
CLOCK

Figure 12. Timers A and B Block Diagram

be taken in programming as it will start an interrupt service routine if the I bit in the CCR is clear. Loading $00 to
timer A allows a countdown of 256 clocks before the next
$00 state is reached.

TIMER A CONTROL REGISTER $09
7

S

S

43210

I TAGR71 TAGRSI TAGRSI TAGR41 TAGR31 TAGR21 TAGR1 I TAGRO

I

RESET:

o

Auto-Loading

The modulus latch is automatically loaded when the
timer reaches $00. This loading is dependent on the setting of TACR3. Auto-loading also occurs in both the previous loading modes~ Timer A can be read a~ any time
without affecting the countdown of the timer: The timer
and modulus latch are set to $FF on reset.

NOTE
Loading $01 to timer A should be avoided when
operating with a divide-by-one prescaler. Doing so
will inhibit timer A auto-loading, interrupt generation, and port B toggle mechanisms.

TACR7 - Timer A Interrupt Request Flag
1 = Timer A has transition to $00
0= Software or reset cleared
TACR6 - Timer A Interrupt Request Mask
1 = Interrupt request inhibited
0= Interrupt request not inhibited
TACR5 - External or Internal Bit
1 = External clock source for prescaler 1
0= Internal clock source for prescaler 1
TACR4 - External Enable Bit
Control bit used to enable the external timer pin
(PR'ESCALER1/PCO).

MOTOROLA MICROPROCESSOR .DATA
3-483

MC6805S2

TACR5

TACR4

0

0

Internal Clock

0

1

AND of Internal Clock and PRESCALER11
PCO*

TIMER B CONTROL AND STATUS REGISTER $00

Prescaler 1 Clock Source

7

1

0

Inputs Disabled

1

1

PRESCALER1/PCO* Low-to-High Transition

TACR1

TACRO

0

0

0

43210

I TBCRO I

o

TACR3 - Timer A Load Mode Control
1 =Asynchronous external event loading (lNT2 driven
loading is enabled)
0= Allows direct loading of timer A
TACR2, TACR1, TACRO - Prescaler 1 Division Ratio Control Bits
When set, these bits select one of eight possible outputs on prescaler 1.
TACR2

5

RESET:

*The status of PRESCALER1/PCO depends upon the data direction status of PRESCALER1/PCO. If PRESCALER1/PCO is an output, then the clock source is equal to the port data register
content, independent of the port electrical loading. If an input,
then the clock source is the logic level of PRESCALER1/PCO.

II

S

I TBCR71 TBCRSI TBCR51 TBCR41 TBCR31 TBCR21 TBCRl

TBCR7 - Timer B Interrupt Request Flag
1 = Timer B has transition to $00
0= Software or reset cleared
TBCR6 - Timer B Interrupt Request Mask
1 = Interrupt request inhibited
0= Interrupt request not inhibited
TBCR5 - External or Internal Bit
1 = External clock source for prescaler 2
0= Internal clock source for prescaler 2
TBCR4 - External Enable Bit
Control bit used to enable the external timer pin
(PRESCALER2/PC1 ).
TBCRS

TBCR4

0

0

Internal Clock

0

1

AND of Internal Clock and PRESCALER21
PC1*

1

0

Inputs Disabled

1

1

PRESCALER2/PC1 * Low-to-High Transition

Divide By
1

0

0

1

2

0

1

0

4

0

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

Prescaler 2 Clock Source

*The status of PRESCALER2/PC1 depends upon the data direction status of PRESCALER2/PC1. If PRESCALER2/PC1 is an output, then the clock source is equal to the port data register
content, independent of the port electrical loading. If an input,
then the clock source is the logic level of PRESCALER2/PC1.

TBCR3, TBCR2, TBCR1, TBCRO - Prescaler 2 Division
Ratio Control Bits
When set, these bits select one of eight possible output
on prescaler 2.

TIMER B
This is a 16-bittimerwhich is accessed via two registers
($OB for the most-significant byte (MSB) and SOC for the
least-significant byte (LSB)). The MSB has a "pipeline"
latch that allows a "snap shot" value of the entire 16 bits
to be read. Read/write operations to the LSB are direct.
The LSB can be read at anytime without disturbing the
count. When the LSB is read, the contents of the MSB
are loaded into the pipeline latch so a read of the MSB
is actually the contents of the lat~h.
When writing to the LSB, the contents are immediately
entered into the timer. At the same time the pipeline
contents are forced into the MSB of the timer. This allows
a 16-bit word to be placed into the timer data register
during a LSB write operation. An underflow condition is
also generated when value $00 is reached. This state can
be used to toggle bit 0 or bit 1 of port B directly under
the control of the miscellaneous register (MRO), the SPI
control register, and the port B data direction register.
Setting TBCR6 or the I bit in-the condition control register
will prevent timer interrupts from being processed. The
timer interrupt request bit MUST be cleared by software.

TBCR3

TBCR2

TBCR1

TBCRO

0

0

0

0

1

0

0

0

1

2

0

0

1

0

4

0

0

1

1

8

0

1

0

0

16

0

1

0

1

32

0

1

1

0

64

0

1

1

1

128

1

0

0

0

256

1

0

0

1

512

1

0

1

0

1024

1

0

1

1

2048

1

1

0

0

4096

1

1

0

1

8192

1

1

1

0

16384

1

1

1

1

32768

MOTOROLA MICROPROCESSOR DATA
3-484

Divide By

MC6805S2

PRESCALER 1
Prescaler 1 is a 7-bit binary down counter; its value is
selected by TACR2, TACR1, and TACRO. The selected output is used as the clock input to either timer A or B,
depending upon the status of the prescaler cross-couple
bit (MR1). The type of clock source to prescaler 1 may be
selected by TACR5 and TACR4, Prescaler 1 is set to $7F
at reset or under program control when a one is written
to prescaler 1 clear bit (MR3).
PRESCALER 2
Prescaler 2 is a 15-bit down counter; its value is selected by TBCR3, TBCR2, TBCR1, and TBCRO. The selected output is used as the clock input to either timer A
or B, depending upon the status of the prescaler crosscouple bit (MR1). The type of clock source to prescaler 2
may be selected by TBCR5 and TBCR4. Prescaler 2 is set
to $7FFF at reset or under program control when a one
is written to prescaler 2 clear bit (MR2).
AUXILIARY COUNTER
This register is a fixed counter which is clocked by the
internal clock (fosc divided by four). Total count period
is 4095 cycles. The MCU communicates with this counter
via the miscellaneous register (MR5 and MR4). Countdown may be aborted at any time under program control,
which also resets the counter to 4095 and clears MR5.
When MR4 is clear and MR5 is set as a result of counter
time out, the reset pin is internally pulled to ground. If
the MCU loses control of the program, the "watchdog"
timer will bring the MCU back to reset. Refer to Figure
13 for counter operation diag ram.

SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) has arbitration on
the data and clock lines. The SPI communicates with the
MCU via data and control registers. The SPI data and
clock inputs are always taken from their respective 1/0
ports, regardless of the status of the data direction registers relative to that port. The SPI can operate in modes
from auto clocked (NRZ), half duplex, and full duplex with
from a one wire to a four wire combination. Refer to
Figure 14 for the SPI block diagram.

SPI CONTROL AND STATUS REGISTER
This 8-bit register contains the status and control bits
relative to SPI operations. The SPI control register operation is shown in Figure 15. The SPI control and status
register bits can be set or cleared under program control.
7

S

543210

\ SPICR7\ SPICRS\ SPICR5\ SPICR4\ SPICR3\ SPICR2\ SPICR1 \ SPICRO

I

RESET:

o

SPICR7 - SPI Interrupt Request Bit
Set on eighth data input strobe. MCU services this interrupt if I bit is clear in CCR.
1 = Interrupt request (if SPICR6 not masked)
0= No interrupt pending

SPICR6 - SPI Interrupt Request Mask Bit
1 = Disables interrupt request from SPICR7
0= Enables interrupt request from SPICR7
SPICR5 - SPI Clock Sense Bit/Bus-Busy Flag
Dual-function bit controlled by the status of SPICR4
1 = Start SPI operation when SPICR4 = 1. Input data
latched on positive edge and output data changed
on negative edge of SPI clock when SPICR4 = o.
O=Stop SPI operation when SPICR4= 1. Input data
latched on negative edge and output data changed
on positive edge of SPI clock when SPICR4=0.
SPICR4 - SPI Operation Enable Bit
This bit determines the functions of SPICR5 and SPICR2.
1 = Enables SPI data register shifting, data and clock
arbitration logic, and slave select input logic
0= Disables SPI data register shifting, data and clock
arbitration logic, and slave select input logic
SPICR3 - SPI Data Output Select Bit
1 = Output of the SPI data register is loaded to port
B3 data register at the appropriate SPI clock edge
selected by SPICR5, during the active transaction
mode
0= Output of the SPI data reg ister is loaded to port
B2 data register at the appropriate SPI clock edge
selected by SPICR5, during the active transaction
mode
SPICR2 - Port Bl Toggle Enable/Start Bit
Dual-function bit controlled by the status of SPICR4
1 = Start bit is set by negative transition of the data
input of the SPI data shift register while the clock
is at the idle level when SPICR4= 1. Start bit set
under program control to enable port Bl data register toggle facility when SPICR4=0.
0= Stop SPI operation when SPICR4 = 1. Cleared under program control when SPICR4=0.
SPICRl - Mode Fault Flag
1 = (a) Mode flag is set when SPI,data output arbitration occurs on the SPI data output port (PB3
or PB2) selected by SPICR3. The MCU loses
data mastership, and the SPI data output port
DDR is cleared.
(b) Mode flag is set if a low level is detected on
slave input PBO. Then, the MCU loses clock
mastership switching to the clock slave mode,
and port Bl DDR is cleared.
(c) Mode flag is set during the idle mode when a
negative clock edge is detected 9n the SPI clock
input, and the port Bl data register is cleared.
0= Cleared under program control
SPICRO - SPI Input Data Select Bit
1 = SPI data from port B3 is latched into the SPI data
register
0= SPI data from port B2 is routed to the input of the
SPI data register

SPI DATA REGISTER
This register can be written to any time and can also
be read, regardless of serial operations, without disturbing the data. A one bit shift to the left occurs each time
there is a data input strobe while the LSB is loaded with
data from port B2 or B3. The MSB is loaded every time
there is data output strobe. Data input and output strobes

MOTOROLA MICRO,PROCESSOR DATA
3-485

3

MC6805S2

Auxiliary
Counter

II

I

EXTERNAL RESET
RESET

[MR5]~
[MR4]

o
o
o

G

: / [MR5]=O

I

1f/////II

MCU WRITE

.....--------

~ I ,..___-_~I--------_+--I
I - ¥'
I
I
I
L.J' VIRES +
I
: [MR5]=1~
I
I

I

II

It[MR5]

I

I

I
I
I

It[MR4]

Ot [MR5]

I
Ot [MR4]

I I

Counter Preset by Writing "1"
Underflow: MR5 t 1; No Forced Reset
Counter Reset by Writing "0"
Underflow MR5 t 1 Forced Reset

Figure 13. Auxiliary Counter Operation

MOTOROLA MICROPROCESSOR DATA
3-486

FORCED RESET ~ I

. VIRES -

TIME

:or.::
L

LJ
I
I
Ot [MR4]

MC6805S2

(SPICR3)'DATA OUT STROBE

DATA OUT
STROBE
DATA IN
STROBE

OVF
OPEN DRAIN
ENABLE
DCRl
CLEAR

CLEAR
CLOCK

. DATA IN
STROBE
. TOGGLE
ENABLE
REGISTER
DCR4

MRO

TIMERB

TIMER A

OVERFLOW

Figure 14. Serial Peripheral Interface Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-487

DATA
DIRECTION
REGISTER
OCR BO

MC6805S2

INTERRUPT
REQUEST
TO CPU

PBO PIN
DDRBO

FROM
PBl PIN
SPIRO
$10

II

LSB

MSB

FROM
PB3 PIN

SPI DATA REGISTER

FROM
PB2 PIN

Figure 15. SPI Control Register Operation

are generated internally only during the active transaction time.

SPI DIVIDE-8Y-EIGHT COUNTER
The counter is cleared during SPI deselect or idle modes.
A count occurs at every data input strobe during the active transaction mode. At overflow, SPICR7 is set which
puts the SPI in idle mode and blocks all data input and
output strobes. The counter is cleared when PBO is high
if the SPI is in the slave mode or when a "start" condition
is detected.
SPI OPERATION
The SPI can operate in a variety of modes. Software
assisted protocols may be defined to upgrade the hardware versatility and/or system performance of the MCU.
Some features common to all operating modes are summarized in Table 1 and in the following paragraphs.
n SPI data input and output may be individually routed
to or from PB2 or PB3 (Table 2). These four routings
provide half and full duplex operations, as well as
allowing bidirectional information to flow in daisychained systems.
2) When data input and output is done on PB2, P~3
is available for any other use and vice versa.
3) Data input is always relative to the port pin logic
level. regardless of the data direction register status
on that pin.
4) In full duplex operation, 16 bits of information may
be transferred with eight clock pulses between at
least two devices with transmit capability. Both PB2

5)

6)

7)

8)

9)

and PB3 are used for data transfer. The same shift
register is used for data in and data out. The byte
transmitted replaces the byte received. SPICR7 is
used to signify that the I/O operation is complete.
SPI clock is always provided on port B1. In the clock
slave mode, port B1 DDR is in the input mode
(cleared). In the clock master mode, port B1 DDR
is set; therefore, the MCU imposes the clock level
on PB1 until there is clock arbitration on the clock
line or until the MCU loses clock mastership when
PBO goes low.
No fixed baud rate generation exists. The clock
frequency is dependent on the prescaler clock
source option, prescaler divide ratio, and timer divide ratio as well as the port C status in case of
external clocking for the timer. Toggling of the port
B1 data register is automatically allowed during
the active transmission mode.
All devices connected to the SPI must have their
output and input data ,strobe on the same clock
edge for correct transfer of data.
During the active transmission mode, the first clock
edge must be the output data strobe. When this
occurs, the MSBs of the data registers of all transmitters are copied onto the data output pins, and
the MCU copies the MSB of its SPI onto the port
B2 or B3 data register.
Port B data direction registers and portS data control registers are accessible during SPI operation.
During active transaction mode, the PB1 data register, PB2 data register (if SPICR3 = 0), and PB3 (if

MOTOROLA· MICROPROCESSOR DATA
3-488

MC6805S2

10) Port B lines not used for SPI can be used for other
digital functions.

SPICR3 = 1) are not write accessible under program
control.

Table 1. Summary of SPI Operations
DEFINITIONS
Transmitter - Data Master: DDRB2 or 3 = 1
Receiver - Data Slave: DDRB2 or 3=0
Clock Master: DDRB1 = 1
Clock Slave: DDRB1 =0
Transaction Mode: SPICR4= 1
1) Active: SPICR7.(DDRBO.PBO + DDRBO) if DDRB1 = 0 (clock slave mode) or
SPICR7.(DDRBO.PBO+DDRBO) if DDRB1 =1 (clock master mode)
Clock Pulses allowed, data shifted
2) Idle: SPICR7 + DDRBO.PBO if DDRB1 = 0 (clock slave mode)
Clock pulses blocked, data output line in high-impedance state
Deselect Mode: SPICR4=0 - No SPI Operations
SLAVE SELECT INPUT
Slave Select Input: SPISS - PBO
If DDRBO=O then so SPISS action on MCU
1) Master Mode: SPISS = 1 DDRBt = 1
SPISS 1 - 0: Switch to Slave Mode (DDRB1 1 - 0)
Set SPICR1 (Mode Fault Flag)
2) Slave Mode: SPISS=O DDRB1 =0
External clock is allowed to shift data in/out. If SPISS is pulled high, the external clock. input pulses
are inhibited; no data shift; divide·by-eight counter cleared; SPID (PB2 or PB3) switched to highimpedance state.
Used as Chip-Select Input
DATA ARBITRATION
Data master loses data mastership when data collision occurs during internal data strobe time.
If SPID output port (PB2 or PB3)= 1 while actual pin level is pulled low externally - conflict detected at internal
data strobe time.
Then SPICR1 (mode fault flag) is set; SPID output port DDR (B2 or B3) 1 .0 (high-impedance state).
CLOCK ARBITRATION
MCU has clock mastership (DDRB1 = 1)
1) Via SPISSline (DDRBO = 0). If SPISS is pulled low, then clock mastership lost; DDRB1 1 .0 (high-impedance state); SPICR1 is set (mode fault flag).
2) Via clock line SPICl (DDRB1 = 1 and DCRB5 = 0)
Condition: SPICl must have open-drain output (DCRB5=0)
If clock line is held low externally then clockmastership is not lost; minimum tClH and
tClK times are guaranteed.
If SPICl goes low during idle mode then SPICR1 = 1 and clock line is switched low to
inhibit the system clock.
MODE FAULT FLAGE OPERATION (SPICR1)
Flag set when any of the following conditions occur:
Data arbitration occurs on SPID output.
Clock arbitration with SPISS during master to slave switching.
Clock arbitration via clock line if SPICl 1 .0 during idle.
START, STOP, AND CLOCK IDLE CONDITIONS
Clock Idle: The clock level just prior to the transition that causes data on the serial output data line to be
changed is defined as the SPI clock idle state.
SPICR5 = 0: SPICl Idle = low State
SPICR5 = 1: SPICl Idle = High State
These definitions are necessary for determining start and stop conditions.
NOTE
Clock idle state can only be defined if SPICR4= 0 (Deselect Mode)
Start Condition: Any negative transition of the data input line (PB2 or PB3) during an SPICl idle state.
Stop Condition: Any positive transition of the data input line during an SPICl idlestate.

MOTOROLA MICROPROCESSOR DATA
3-489

I

MC6805S2

Table 2. Port B Status During SPI Operation

I

Port
Name

Use

Input

Output

Comments

PBO
PBO

SPISS
Data

Yes
No

No
Yes

Used as slave select input
Used as "busy" signal or any digital
output

PBl
PBl

SPICl
SPICl

Yes
No

No
Yes

Clock slave
Clock master

PB2
PB2
PB2

SPID
SPID
Data

Yes
No
Yes

No
Yes
Yes

SPI data input SPICRO=O
SPI data output SPICR3 = 0
Any digital signal SPICR3 = 1

PB3
PB3
PB3

SPID
SPID
Data

Yes
No
Yes

No
Yes
Yes

SPI data input SPICRO = 1
SPI data output SPICR3 = 1
Any digital signal SPICR3 = 0

SELECT INPUT OPERATION
An external device supplies slave select information
via port BO. If slave select is not used, set port BO to output
mode to inhibit slave select function.
The following paragraphs describe clock master and
clock slave operating modes of the SPI.
Master Mode Slave Select Actions
The MCU monitors slave select input in master mode
to assure that it stays false. If slave select goes true, the
MCU exits master mode and becomes a slave. This implies that a write collision has occurred which means two
devices attempted to become masters. Write collisions
normally result from a software error, and the default
master must clean upthe system. The mode fault flag is
set to signal that clock mastership is lost. Slave select
actions can take place during either active or idle transaction modes.
Slave Select Input Actions During Slave Mode
The current clock master generates slave select to enable one of several slaves to accept or return data. The
SS signal must go low before serial clock pulses occur
and must remain low until after the eighth serial clock
cycle. Individual lines or a daisy chain can be used. for
multiple slaves. When SS is high, the following occur:
• Serial data output is forced to a high-impedance state
without affecting the DDR status.
• Serial clock input pulses are inhibited from generating internal data output and input strobe pulses.
• The eight-bit counter is cleared.
SPI OPERATING MODES
Six methods of operating the SPI are discussed in the
following paragraphs.
.
One-Wire Autoclocked Mode
Various SPI devices can be connected on a single wire,
with data transmission using an implicit clock, and each
device being its own clock master.
Two-Wire Half-Duplex Mode
In this mode, separate data and clock lines connect the
elements in the system. Data and clock mastership should

be monitored via protocol included in the data patterns.
A transmitter can send all zeros. to take all other transmitters off the bus.
Three-Wire Half-Duplex Mode with Slave Select Input
This mode is the same as the half-duplex mode except
that the slave select input allows using the MCU as a
peripheral in a system where clock mastership is passed
through the slave select line. Typically, the slave select
lines can be wired together. The current master sets its
slave select line in the output mode prior to a serial transmission and pulls it low to indicate that the system is
busy. This allows the clock master to r.etain mastership
until the end of transmission. Software protocol can be
arranged so that slaves do not request mastership until
their slave select lines go high. At the end of a transmission, the current master pulls SPISS high and puts the
SPISS port (PBO) in the input mode. A slave requesting
clock mastership pulls the SPISS line low, removing the
current master from the line. Time multiplexed protocols
may be required to avoid simultaneous mastership requests.
Three-Wire Full-Duplex Mode
This mode allows the MCU to operate simultaneously
as transmitter and receiver. Bus or daisy-chain networks
are feasible. Protocols in the data stream are required to
change:
• Clock masters
• The number of transmitters in the system
• The direction of data flow in daisy-chained systems
with collision
It is possible for theMCU to shift out one byte of data
while receiving another, as illustrated in Figure 16. This
eliminates the need for XMIT EMPTY or REC FULL status
bits.
Three-Wire Full-Duplex Mode with Clock Arbitration
This mode is a mix of the three-wire full-duplex mode
and two-wire half-duplex mode with clock arbitration,
where the SPI clock line operates as a wire-or. Simultaneous masters are allowed, and dock arbitration is via
the clock line.

MOTOROLA MICROPROCESSOR DATA

3·490

MC6805S2

...

SLAVE SELECT - - - - -...------.-----..,..-4i
__-

--~._--­

-+----...--+----....--i~----'~I--t_---

CLOCK - - - -....
DATA

~

EXAMPLE:

INFORMATION FLOW
~

{
{

B2=SPID IN
B3=SPIC OUT
B2=SPID OUT
B3=SPID IN

Figure 16. Daisy Chain/Cascade Organization

Fou'r-Wire Full-Duplex Mode with Slave-Select Input
This mode is similar to the three-wire full-duplex mode
in network construction and to the three-wire half-duplex
mode with slave-select input in clock arbitration and slave
selection. Refer to Figure 17.

ANALOG-TO-DIGITAL CONVERTER
The chip resident 8-bit analog-to-digital (AID) converter
uses a successive approximation technique as shown in
Figure 18. Four external analog inputs can be connected
to the AID through a multiplexer via port D. Four internal

analog channels (VRH - VRL, VRH - VRL/2, VRH -VRL/4,
and VRU may be selected for calibrat.ion. The accuracy
of. theseinteroa,1 channels may not meet the accuracy
specifications of the external channels.
A fifth external analog input (AN4) is.available via the
mask option. When selected, it replaces the VRH internal
channel. Due to signal routing, the accuracy of this fifth
channel may be slightly less than ANO-AN3:
Multiplexer selection is controlled by the AID control
register (ACR) bits 0, 1, and 2. Refer to Table 3 for multiplexer selection. The ACR is shown in Figure 18. The
coriverter uses 30 machine cycles to complete a .conversion cif a sampled analog input. When the conversion is
complete, the digital value is placed in the AID result

~

MCU 1

I- ~

*HALF DUPLEX

S. PID:PB2I3
{ SPICl:PBl

*HALF DUPLEX
{ SPID:PD2I3
WITH CLOCK ARBITRATION
SPICL:PBl
~

I-- ~

~

MCU 2

*HALF DUPLEX
WITH SLAVE SELECT

*FULL DUPLEX
H~

I-- ~

*FULL DUPLEX
WITH SLAVE SELECT

MCU 3

{

SPID:PB2/3
SPICL:PBl
SPISS:PBO

SPID IN:PB2I3
SPID OUT:PB3/2
SPICL:PBl
SPID IN:PB2/3
SPID, OUT:PB3/2
SPICL:PBl
{
SPISS:PBO

{

C
C
c:
U
c:
a:::
a:::
...J

(I)

(I)
(I)

(I)

(I)

(I)

Figure 17. SPI Operation Bus Organization

MOTOROLA MICROPROCESSOR DATA
3-491

II

MC6805S2

Table 3. A/D Input MUX Selection
AID Control Register
ACR2

ACR1

AeRO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0

1
0
1

Input Selected
ANO
AN1
AN2
AN3
VRH**
VRL*
VRH/4*
VRH/2*

AID Output (Hex)
Min

Typ

Max

FE**
00
3F
7F

FF**
00
40
80

FF**
01
41
81

*Internal (calibration) levels
** AN4 may replace the VRH calibration channel if selected via mask
option.

I

register (ARR); the conversion flag is set; selected input
is sampled again; and a new conversion begins. When
ACR7 is cleared, the conversion in progress is aborted
and the selected input, which is held internally, is sampled for five machine cycles.
The converter uses VRH and VRL as reference voltages.
An input voltage equal to or greater than VRH converts
to $FF. An input voltage equal to or less than VRL, but
greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded. Each analog input
source should use VRH as the supply voltage and be
referenced to VRL for the ratiometric conversion. To
maintain full accuracy of the AID, three requirements
should be followed: (1) VRH should be equal to or less
than VCC, (2) VRL should be equal to or greater than VSS
but less than maximum specifications, and (3) VRH - VRL
should be equal to or greater than 4 volts.
'
The AID has a built-in 1/2 LS8 offset intended to reduce
the magnitude ofthe quantizing error to ± 112 LS8, rather

than +0, -1 LS8 with no offset. This implies that, ignoring errors, the transition point from $00 to $01 occurs
at 1/2 LS8 above VRL. Similarly, the transition from $FE
to $FF occurs 1~112 LS8 below VRH, ideally.

INSTRUCTION SET
The MCU has a set of 61 basic instructions which can
be divided into five different types: register/memory, readmOdify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.
REGISTER/MEMORY INSTRUCTIONS

Most of these instructions use two operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and

D/A
CONTROL
LOGIC

15 k (TYP.)

COUNT

PD5NRH
PD4NRL
PDO/ANO
I-OF-8
SELECT
PD2/AN2
MULTIPLEXER
PD3/AN3
INT2IPD6/AN4 __L...._ _ _ _ _....
PD1IANl

A/D
CONTROL
REGISTER

t..)

L....<..&_.&.......r......&.....L_.........L--....I

L....-'-_"--....L._"--......_.&.........~

Figure 18. AID Block Diagram

MOTOROLA MICROPROCESSOR DATA

3·492

A/D
RESULT
REGISTER

MC6805S2

jump to subroutine (JSR) instructions have no register
operand. Refer to the following instruction list.

Load A from Memory

LDA

Load X from Memory

LDX

Store A in Memory

STA

Store X in Memory

STX

Add Memory to A

ADD

Add Memory and Carry to A

ADC

Subtract Memory

SUB

Subtract Memory from A with Borrow

SBC

AND Memory to A

AND

OR Memory with A

ORA

Exclusive OR Memory with A

EOR

Arithmetic Compare A with Memory

CMP

Arithmetic Compare X with Memory

CPX

Bit Test Memory with A (Logical Compare)

JMP

Jump to Subroutine

JSR

INC

Increment
",

Decrement

BIT

Jump Unconditional

Mnemonic

Function

Mnemonic

Function

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list for branch instructions.
Function

read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.

DEC

Clear

CLR

Complement

COM

Negate (2's Complement)

NEG

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Logical Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes ofthe memory space where
all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear and bit test, and
branch functions are all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the carry bit ofthe condition
code register. Refer to the following list for bit manipulation instructions.
Mnemonic

Function

Mnemonic

Branch if Bit n is Set

BRSET n (n =0 ... 7)

BRN

Branch if Bit n is Clear

BRCLR n (n =0 ... 7)

BHI

Set Bit n

BSET n (n=O ... 7)

Branch IFF Lower or Same

BLS

Clear Bit n

BCLR n (n=O ... 7)

Branch IFF Carry Clear

BCC

Branch Always

BRA

Branch Never
Branch IFF Higher

(Branch IFF Higher or Same)
Branch IFF Carry Set
(Branch IFF Lower)
Branch IFF Not Equal
Branch IFF Equal

CONTROL INSTRUCTIONS
These instructions are register reference instructions
and are use,d to control processor operation during program execution. Refer to the following list for control
instructions.

(BHS)
BCS
(BLO)
BNE
BEQ

Function

Mnemonic

Branch IFF Half Carry Clear

BHCC

Branch IFF Half Carry Set

BHCS

Transfer A to X

TAX

BPL

Transfer X to A

TXA

Branch IFF Plus
Branch IFF Minus

BMI

Set Carry Bit

SEC

Branch IFF Interrupt Mask Bit is Clear

BMC

Clear Carry Bit

CLC

Branch IFF Interrupt Mask Bit is Set

BMS

Set Interrupt Mask Bit

SEI

Branch IFF Interrupt Line is Low

BIL

Clear Interrupt Mask Bit

CLI

Branch IFF Interrupt Line is High

BIH

Software Interrupt

SWI

Branch to Subroutine

BSR

Return from Subroutine

RTS

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location ora register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the

Return from Interrupt

RTI

Reset Stack Pointer

RSP

No-Operation

,

NOP

OPCODE MAP SUMMARY
Table 4 is an opcode map for the instructions used on
the MCU.

MOTOROLA MICROPROCESSOR DATA
3-493

II

•
Bit ~
11TH - , BSC

~

o

(.)

~

~

,

5.0
4.0

~

cc

0

NUM

~
~

This pin is for factory use only. It should be connected
to

7.0
6.0

Vss.

3.0

1.0

o

INn, INT2
These pins provide the capability for asynchronously
applying an external interrupt to the MCU. Refer to IN·
TERRUPTS for more detailed information.

"- ~ ....

2.0

o

10

20

30
40
50
RESISTANCE (kH)

60

70

80

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only

XTAL,EXTAL

These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal (depending on user selected
manufacturing mask option) is connected to these pins
to provide a system clock.

Crystal

The circuit shown in Figure 1(b) is recommended when
using a crystal. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time.

RC Oscillator

With this option, a resistor/capacitor combination is
connected to the oscillator pins as shown in Figure 1(c).
The relationship between Rand fosc is shown in Figure
2.

External Clock

An external clock should be applied to the EXTAL input
with the XTAL input grounded, as shown in Figure 1(d).

~_ _ _........-2-16 XTAL
XTAL
26

EXTAL
27

MCU
(CRYSTAL MASK
OPTION

At-CUT PARALLEL RESONANCE
CRYSTAL
CO=7 pF MAX.
FREQ. = 4.0 MHz(1I CL = 24 pF
RS = 40 OHMS MAX.

26
EXTERNAL
CLOCK
27
INPUT
(TIL COMPATIBLE,
LOW IMPEDANCE
SOURCEI

XTAL

XTAL
MCU
EITHER CRYSTAL
OR RC MASK
OPTION

EXTERNAL CLOCK

~OTE:

CRYSTAL

EXTAL

MCU
(RESISTOR MASK
OPTIONI

APPROXIMATELY 10% to 25%
ACCURACY
EXTERNAL RESISTOR
(EXCLUDES RESISTOR TOLERANCEI

EXTAL

MCU
(RESISTOR MASK
OPTIONI

APPROXIMATELY 25% to 50%
ACCURACY
TYPI CAL tcyc = 1.25 f.Ls
EXTERNAL JUMPER

The recommended CL value with a 4.0 MHz crystal is 27 pF, maximum, including system distributed capacitance. For crystal
frequencies other than 4 MHz, the total capacitance on each pin should be scaled as the inverse of the frequency ratio. For
example, with 2 MHz crystal, use approximately 50 pF on EXTAL and approximately 50 pF on XTAL. The exact value depends
on the motional-arm parametes of the crystal used.

Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR DATA

3·503

II

MC6805S3

This option may be used with either RC or XTAL option
selected.
PCO, PC1
These pins allow an external input to be used to decrement the internal timer circuit. Refer to TIMERS for
additional information.
RESET
This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low.
INPUT/OUTPUT LINES (PAO.. PA7, PBO-PB3, PCO-PC1, and
PDO-PD6)

I

Ports A, 8, and C are programmable as either inputs
or outputs under software control of the data direction
registers. Port 0 is a fixed input port and not controlled
by any data register. Port 0 has up to four analog inputs
or five via the mask option, plus two voltage reference
inputs when the analog-to-~I (AID) converter is used
(PD5/VRH, PD4/VRU and an INT2 input. Ifthe analog input
is used, then the voltage reference pins (PD5/VRH and
PD4/VRU must be used in the analog mode. Refer to
PROGRAMMING for additional information.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
Ports A, 8, and C are programmable as either input or
output under software control of the corresponding data
direction register (DDR). The port I/O programming is
accomplished by writing the corresponding bit in the port
DDR to a logic one for output and a logic zero for input.

On reset, all DDRs are initialized to a logic zero state to
put the ports in the input mode. The port output registers
are not initialized on reset and should be written to before
setting the DDR bits.
Port 0 provides the multiplexed analog inputs, reference voltages, and INT2. These lines are shared with the
port 0 digital inputs. PDO-PD3 may always be used as
digital or analog inputs. The VRL and VRH lines are internally connected by the A/D resistor. Analog inputs may
be prescaled to attain the VRL and VRH recommended
input voltage range.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Care must
be exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (zero) and, also, to the latched output
when the DDR is an output (one). Refer to Figure 3 for
typical port circuitry.
PORT B TOGGLE CAPABILITY
Port 80 and 81 registers have toggle capability at the
timer underflow times. Under the control of the timer
output cross-couple bit in the miscellaneous register
(MRO)' the overflow pulses from timer A, 8, and Care
directed to port 80 and 81 data registers. See Figure 4
for port 8 configuration flow chart.
An incoming toggle pulse on port 80 is allowed to
toggle the data register if port 8 OCR bit 4 (DCR4) is
cleared. This bit is set on reset. An incoming toggle pulse
on port 81 is allowed to toggle the port 81 data register

en

....Jz

<3:2

ZI0::<">
UJ UJ
I-Z

zz

-8

Data
Direction
Register
Bit
1
1

o

Input

Output
Data
Bit

Output
State

o

o

o

1
X

1
High-Z**

1
Pin

To

MCU

*DDR is a write-only register and reads as all "ones".
**Ports A (with CMOS drive disabled), B, and C are three-state
ports. Port A has optional internal pullup devices to provide
CMOS drive capability. See Electrical Characteristics tables
for complete information.

Figure 3. Typical Port I/O Circuitry and Register Configuration

MOTOROLA MICROPROCESSOR DATA
3-504

PORT 81

**TIMER OVERFLOW

JL...

•

~~~~LC:

i

MCU

PORT 83
MCU

s:

I

P81

~

0
:JJ
0

s;:

SPI
MSB

s:

Co\)

U,
0
U'I

PB3

3:
(')
en
~

n

~.

ISPICR1)

~

:JJ

U'I

0

~.
rn
rn

TIMER OVERFLOW

MCU

fl

J""L

0

:JJ

c.

~

•

MCU

SPI
MSB

MCU

P80

MCU of

•

<

*Toggle Enable B1 = ISPICR7·SPICR4·IPBO + DDRBOH·SPICR2·SPICR4)·CLAQ
**A or B depends on IMRO)
x Write Only Register

Figure 4. Port B Configuration

PB2

MC6805S3·

II

under the following conditions governed by control bits
in SPI control register and SPI clock arbitration flip-flop
status.
PB1 toggle enable = (SPICR7)·SPICR4·
(PBO + DDRBO) + SPICR2·
SPICR4·CLAO
where: SPICR7 = SPI interrupt request bit
SPICR4 = SPI operation enable bit
SPICR2 = port B1 toggle enable/start bit
CLAO = clock arbitration flip-flop output
When PB1 toggle enable is asserted, the MCU write to
PB1 data register is inhibited. When SPI is not used, SPICR4
and CLAO are reset. Therefore, SPICR2 can directly control the port B1 toggle capability. Port toggle capability
allows action on port BO or B1 or both as a result oftimer
overflows. This method speeds up timer overflow to port
service. A write to port BO or B1 data registers is inhibited
while the individual port toggle enable is asserted.
The port B DCR consists offour status bits (DCR4-DCR7)
and four data direction bits (DCRO-DCR3). DCR4 is a toggle enable control bit for port BO. When cleared, the timer
overflow pulse causes the data register on port BO to
toggle. Port A has an 8-bit and port C has a 2-bit wide
data direction register.

MEMORY

may be added to an 8- or 16-bit immediate value to create
an effective address. The index register may also be used
as a temporary storage area.
7

x
PROGRAM COUNTER (PC)
The program counter is a 12-bit register that contains
the address of the next byte to be fetched.
11

I

PCl

STACK POINTER (SP)
The stack pointer is a 12-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
The seven most-significant bits of the stack pointer are
permanently set at 0000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to 15
levels of subroutine calls (less if interrupts are allowed).
11

The MCU is capable of addressing 4096 bytes of memory and I/O registers. The memory map is shown in Figure
5. The locations consist of user ROM, self-check ROM,
user RAM, eight timer registers, a miscellaneous register,
two AID registers, two SPI registers, and I/O. The interrupt
vectors are located from $FF8 to $FFF.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.

a

8 7

PCH

I a I 0 I a / 0 / a /1

a

5 4

/ 1 /

SP

CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit register in which
four bits are used to indicate the results of the instruction
just executed. These bits can be individually tested by a
program and specific actions can be taken as a result of
their state. Each bit is explained in the following paragraphs.

NOTE
Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

Half Carry (H)
This .bit is set <;luring ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

REGISTERS

Interrupt (I)

The MCU contains the registers described in the following paragraphs.
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.
7

A

When this bit is set, the timers (A, B, and C), the external
(lNT1 and INT2) interrupts, and the SPI interrupt are
masked (disabled). If an interrupt occurs while this bit is
set, the interrupt is latched and is processed as soon as
the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative (bit
7 in the result is a logic one).

INDEX REGISTER (X)

Zero (Zl

The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.

MOTOROLA MICROPROCESSOR DATA
3-506

MC6805S3

iBYTESl

6

5 4 3 2 1

()()()

7

iADDRESSl

6 5 4

$()()()

3 2

1

Port A

IADDRESS

1/0. AID. SPI.

Port B

$001

Timers. RAM
(12B Bytes)

Port C

$002

127

$07F

Port D

$003

128

$080

Port A DDR-

$004

Page 0 ROM
112B Bytes)

Port B DCR-

$005

Port C DDR-

$006
$007

255

$OFF

Not Used

256

$100

Timer A

$008

Timer A Cont. Reg.

$009

Misc. Register

$OOA

Timer B MSB

$OOB

Timer B LSB

$OOC

Tlmer B Cont. Reg.

$OOD

AID Control

$OOE

'-'"

"r-

Main ROM
13584 Bytas)

3839

'-~

"r"

$EFF
$FOO

3840
Self-Check
Bootstrap
ROM
1248 Bytes)

408 7
Timers IA. B. C).
SPI.INT2

l

$()()()

AID Result

$OOF

SPI Data

$010

SPI Control

$011

Prog. Cont. Reg.

$012

$FF7

Timer C Capture

$013

$FFB

Timer C Data

$014

$FF9

Timer C Control

$015

$FFA

Not Used

$016

$FFB

Not Used

$017

II

External INTl

----

$FFC
SWI
$FFD

6

5

4

3 2

1

iADDRESS!
$018

User RAM
140 Bytesl

RAM
1104 Bytes)

$FFE
Reset

7

$018

$03F
$FFF

$07F
Standby RAM 116 Bytes)

\

*Registers are write only and read as $FF.
**Mask option

*

User RAM
(17 Bytes)

$040
$04F
$050
$060
$061

Shared Stack RAM
(31 Bytes)

$07F

Figure 5. Memory Map

Carry/Borrow (C)

When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and during shifts and
rotates.

MISCELLANEOUS REGISTERS (MR) $OA
This register contains control and status information
related to INT2, auxiliary counter, prescalers 1 and 2, and
timer overflow.

MR7

MR6

MR5

MR3

MR2

MRI

MRO

RESET:

MR7 - INT2 Interrupt Request Bit
If not masked by MR6, it causes an interrupt to the
MCU, and if the I bit in the CCR is clear, the MCU will
acknowledge the interrupt.
1 = Interrupt requested
Q=lnterrupt not requested

MOTOROLA MICROPROCESSOR DATA
3-507

MR4

MC6805S3

II

MR6 - INT2 Interrupt Request Mask
1 = Inhibits INT2 inte~t request
0= Does not inhibit INT2 interrupt request
MR5 - Auxiliary Counter Status/Preset Bit
If not masked by MR4, it will drive a switch to VSS on
the RESET pin causing the MCU to reset. This bit may
be used as an auxiliary counter preset bit. If MR5 is
clear, a write of logic one will preset the auxiliary
counter, and if set, a write of logic zero will preset the
auxiliary counter.
1 = Auxiliary counter overflow
0= Auxiliary counter clear
MR4 - Watchdog Control Bit
This bit cannot be set via software. The watchdog timer
can only be disabled by reset.
1 = Watchdog timer disabled
0= Watchdog timer enabled
MR3 - Prescaler 1 Clear Bit
Presets the contents of prescaler 1 to $7F.
1 = Prescaler 1 preset
0= Prescaler 1 not preset
MR2 - Prescaler 2 Clear Bit
Presets the contents of prescaler 2 to $7FFF.
1 = Prescaler 2 preset
0= Prescaler 2 not preset
MR1 - Prescaler Cross-Couple Bit
This bit controls the output of prescalers 1 and 2 and

directs them to either timer A or B clock inputs.
1 = Prescaler 1 feeds timer B clock input, and prescaler 2 feeds timer A input
0= Prescaler 1 output is used as clock input for timer
A, and prescaler 2 output is used as clock input
for timer B
MRO - Port B Toggle Cross-Couple Bit
This bit controls the overflow pulses of timers A and
B and directs them to either port BO or B1.
1 = Timer A overflow output is directed to port BO,
and timer B output is directed to port B1
0= Overflow output pulse of timer A is used as a port
B1 data register toggle clock source, and timer B
overflow output pulse is directed to port BO toggle
clock input

SELF CHECK
The self check is initiated by connecting the MCU as
shown in Figure 6 and then monitoring the output of port
C (bit 0) for an oscillation of approximately 7 Hz. The selfcheck program exercises the CPU, I/O, RAM, ROM, timers,
interrupts, analog-to-digital (AID) converter, and the auxiliary counter.
The RAM, ROM, and 4-channel AID test can be called
by a user program. The timer test may be called if the
timer input is the internal clock.

CLOCK
RESET
28
+9V

----

27

VCC

26

VCC

25
24
23
22

AN2

21

ANl
ANO
PBO
PBl
PB2
PB3

20
10

19

11

18

12

17

13

16

14

15

Rl =6 kn
R2=3 kn
R3=200 n
R4=390 n
Cl =22 pF
C2=1 IJ-F
C3=0.1 IJ-F

*RC Oscillator Option Shown. If QO-Q2 LEOs Blinking = Device Passes Test
Q3 Blinking = Watchdog Reset Problem

Figure 6. Self-Check Connections

MOTOROLA MICROPROCESSOR DATA
3-508

MC6805S3

(tcycl. Under this type of reset, the Schmitt trigger switches
off at VIRES - to provide an internal reset voltage.

RESETS
The MCU can be reset four ways: (1) by initial powerup; (2) by the external reset input (RESET); (3) by a forced
reset generated by the "watchdog" counter; and (4) by
an optional internal low voltage detect circuit. The RESET
input consists mainly of a Schmitt trigger that senses the
line logic level. Figure 7 shows the MCU reset circuit.

FORCED RESET
If the auxiliary counter reset mask bit in the miscellaneous counter (MR4) is cleared and the auxiliary counter
status bit (MR5) is set, as a result of counter overflow, a
switch to VSS is turned on pulling the RESET pin low. A
consequent voltage drop below VIRES - on RESET causes
a reset, which in turn sets MR4. Switching to VSS when
the RESET pin is turned off allows voltage to rise above
VIRES +, after which the reset is released. RESET pin
voltage variation occurring as a result of forced reset may
be amplified externally in order to provide a reset to other
peripheral circuits in the system. The reset output from
the MCU is not TIL compatible.

POWER-ON-RESET (POR)
An internal reset is generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power turn-on conditions and
should not be used to detect any drop in the power supply
voltage. A delay of tRHL milliseconds is required before
allowing RESET input to go high. Connecting a capacitor
to the RESET input (FigureS) typically provides sufficient
delay.
EXTERNAL RESET INPUT

LOW-VOLTAGE INHIBIT (LVI)

The MCU is reset when a logic zero is applied to the
RESET input for a period longer than one machine cycle

The optional low-voltage detection circuit causes a reset of the MCU if the power supply voltage falls below a
certain level (VLVI). The only requirement is thatthe VCC
must remain at or below the VLVlthreshold for one tcyc
minimum.
In typical applications, the VCC bus filter capacitor will
eliminate negative-going voltage glitches of less than one
tcyc. The output from the low-voltage detector is connected directly to the internal reset circuitry. It also forces
the RESET pin low via a strong discharge device through
a resistor. The internal reset is removed once the power
supply voltage rises above a recovery level (VLVR) at
which time a normal power-on reset occurs.

1

VCC

--''''~fV',.--+_2_3--.

::r:

1.0 f.LF

MCU

Figure 8. Power-Up Reset Delay Circuit

220 kH
TYP.

RESET

23
100 !l
TYP.

I

1 f.LF TYP.**

**OPTION-l00 ms DELAY
TYPICAL DURING POWER UP

MISCELLANEOUS REGISTER

Figure 7. Reset Circuit

MOTOROLA MICROPROCESSOR DATA
3-509

I

MC6805S3

must determine the source of the interrupt by examining
the interrupt request bits, TACR7, TBCR7, MR7, TCOF,
TCCF, and SPICR7. These bits must be cleared by software. The INT1 interrupt has its own vector address.
Therefore, the INT1 interrupt request is cleared automatically, and then the INT1 vector is serviced.

INTERRUPTS
The MCU can be interrupted seven different ways:
through the external interrupt INT1 input pin, with the
internal timer (either A or B) interrupt request, using the
software interrupt instruction (SWI), SPlinterrupt request, external port D bit S (lNT2) input pin, or at reset.
Interrupts cause the processor registers to be saved on
the stack and the interrupt mask (I bit) set to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack after which
normal processing resumes. The stacking order is shown
in Figure 9.

7

n-4

I

6

5

111

I

4

3

2

1

n+l

ACCUMULATOR

n+2

n-2

INDEX REGISTER

n+3

I

n+4

1111

PCW

PCl*

The external interrupt is interna~ynchronized and
then latched on the falling edge of INT1 and INT2. Clearing the I bit enables the external interrupt. The INT2 interrupt has an interrupt request bit (bit 7)and a mask bit
(bit S) in the miscellaneous register (MR). The INT2 interrupt is inhibited when the mask bit is set. The INT2 is
always read as a digital input on port D. The INT2 and
timer interrupt request bits, if set, cause the MCU to process an interrupt when the condition code I bit is clear.
The following paragraphs describe two typical external
interrupt circuits.

PUll

CONDITION
CODE REGISTER

n -- 3

n --1

EXTERNAL INTERRUPT

Zero-Crossing Interrupt

A sinusoidal input signal (fINT1 maximum) can be used
to generate an external interrupt (see Figure 11a) for use
as a zero-crossing detector (for negative transitions of
the ac sinusoid). This type of circuit allows applications
such as servicing time-of-day routines and engaging/disengaging ac power control devices. Off-chip, full-wave
rectification provides an interrupt at every zero crossing
of the ac signal and, thereby, provides a 2f clock.

n+5

PUSH
*For subroutine calls, only PCH and PCl are stacked.

Figure 9. Interrupt Stacking Order
Digital-Signal Interrupt

With this type of circuit (Figure 11 b), the INT1 pin can
be driven by a digital signal. The maximum frequency of
a signal that can be recognized by the TIMER or INT1 pin
logic is dependent on the parameter labeled tWL, tWH.
Refer to TIMER for additional information.

Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted, but are considered-pending until the current instruction is complete.

NOTE
The current instruction is considered to be the one
already fetched and being operated on.
When the current instruction is complete, the processor
checks all pending hardware interrupts and, if unmasked
(I bit clear), proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Masked
interrupts are latched for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 10 for the reset and interrupt
instruction processing sequence.

SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. If the I bit
is zero, SWI executes after the other interrupts. The SWI
. execution is similar to the hardware interrupts.

TIMERS
The MCU has four timers and two programmable prescalers. The timers are identified as timer A, B, C, and the
auxiliary counter. Refer to Figure 12 for timers A, B, and
C block diagram. The following paragraphs described the
different timers.

TIMER A
TIMER INTERRUPT
Each interrupt, except INT1, has a separate mask bit
which must also be cleared, in addition to the I bit, for
the MCU to acknowledge the interrupt. The INT2, timer
A, timer B, timer C, and SPI interrupts each have their
own independent mask bits contained in MRS, TACRS,
TBCR6, TCOM, TCCM, and SPICRS. The interrupt routine

Timer A is an a-bit programmable counter, which can
be loaded under program control. Timer A also includes
a modulus latch which allows the timer to be "auto-reloaded." As clock inputs are received, timer A decrements
toward $00. When $00 is reached, bit 7 in the timer A
control register is set and the timer is reloaded with the
contents of the modulus latch. An overflow condition is

MOTOROLA MICROPROCESSOR DATA
3-510

MC6805S3

l.I(lN CCR)
07F. SP

O. DORA
FO.DORB
FC.DDRC
7F. PRESC. 1
7FFFF. PRESC. 2
40. SPICR
50.MR
50. TRCR
FFUIMER A
50. TBCR
FFFF. TIMER B
53. TCCR
FF. TIMER C
07. RCSR
CLR INT LOGIC

TIMERS A. B. C.
INT2. CAPTURE. SPI
LOAD PC FROM
SWI: FFC/FFD
INTl: FFA/FFB
TIMERS A. B. C
CAPTURE
SPI OR INT2:
FF8/FF9

*MR7'MR6
(lNT2)

+

TRCR7oTRCR6
(TIMER A)

+

TBCR7·TBCR6
(TIMER B)

+

TCOF·TCOM
(TIMER C)

TCCF·TCOM
(CAPTURE)

+

SPICR7·SPICR6
(SPI)

Figure 1O. Reset and Interrupt Processing Flowchart
VCC
AC
(tINTMAX.)
R",l MH
AC INPUT
::,.,10 Vacp - p

TTL

4.7 k

LEVEL _ _....2_5-1 INTl
DIGITAL
INPUT

MCU

MCU

(B) DIGITAL-SIGNAL INTERRUPT

(A) ZERO-CROSSING INTERRUPT

Figure 11. Typical Interrupt Circuits (lNT1)

MOTOROLA IVIICROPROCESSOR DATA
3-511

II

MC6805S3

RESET MR3
PRESCALERl/PCO
SELECT MRI

OVERFLOW A

TIMER A

TO MCU

INT

TO MCU

OVERFLOW 8

SELECT T8RC3. 2. 1.0

SELECT T8CR4. 5

INT

SELECT MRO PORT
81 TOGGLE
RESET MR2

PORT
80 TOGGLE

PRESCALER2 PCl

TO MCU

INg~~~ -~----41---------""

I - - - - - - - - - - -.....--IINT

L..-_ _- - - '

TO MCU

Figure 12. Timers A, B, and C Block Diagram

also generated when value $00 is reached. This state can
be used to toggle bit 0 or bit 1 of port B directly under
the control of the miscellaneous register (MRO), the SPI
control register, and the port B data direction register.
Setting TACR6 or the I bit in the condition control register
will prevent timer interrupts from being processed. The
timer interrupt request bit MUST be cleared by software.
There are three ways of loading data from the modulus
latch into timer A as described in the following paragrahs.
Direct Loading

When the MCU writes to timer A data register, the data
is latched by the modulus latch, and forced into the timer.
This operation requires that TACR3 be cleared.

oflNT2 interrupt request bit (MR7) gated with interrupt
request mask bit (MR6). Ifthis loading is used, care must
be taken in programming as it will start an interrupt service routine if the I bit in the CCR is clear. Loading $00 to
timer A allows a countdown of 256 clocks before the next
$00 state is reached.
Auto-Loading

The modulus latch is automatically loaded when the
timer reaches $00. This loading is dependent on the setting of TACR3. Auto-loading also occurs in both the previous loading modes. Timer A can be read at any time
without affecting the countdown of the timer. The timer
and modulus latch are set to $FF on reset.
NOTE

Asynchronous External Event Loading

When TACR3 is a logic one, the contents of the modulus latch are transferred to the timer at the rising edge

Loading $01 to timer A should be avoided when
operating with a divide-by-one prescaler. Doing so

MOTOROLA MICROPROCESSOR DATA
3-512

MC6805S3

will inhibit timer A auto-loading, interrupt generation, and port B toggle mechanisms.
TIMER A CONTROL REGISTER $09
76543210

ITACR71 TACR61 TACR5\ TACR4\ TACR3\ TACR2\ TACRl \ TACRO \
RESET:

o

TACR7 - Timer A Interrupt Request Flag
1 = Timer A has transition to $00
0= Software or reset cleared
TACR6 - Timer A Interrupt Request Mask
1 = Interrupt request inhibited
0= Interrupt request not inhibited
TACR5 - External or Internal Bit
1 = External clock source for prescaler 1
0= Internal clock source for prescaler 1
T ACR4 - External Enable Bit
Control bit used to enable the external timer pin
(PRESCALER1!PCO).
TACR5

TACR4

0

0

0

1

1
1

0

1

Prescaler 1 Clock Source
Internal Clock
AND of Internal
Clock
PRESCALER1/PCO*
Inputs Disabled

TACR3 - Timer A Load Mode Control
1 = Asynchronous external event loading (lNT2 driven loading is enabled)
O=Allowsdirect loading of timer A
TACR2, TACR1, TACRO - Prescaler 1 Division Ratio Control Bits
When set, these bits select one of eight possible outputs on prescaler 1.
TACRO

0

0

0

1

0

0

1

0

1
1

0

2
4

1

8

1
1
1

0

0

1

0

Divide By

0

0

1

0

16
32
64

1

1

128

76543210
\ TBCR7\ TBCR6 \ TBCR5\ TBCR4\ TBCR3\ TBCR2\ TBCRl

r:rsc;J

RESET:

*The status of PRESCALER1/PCO depends upon the data direction status of PRESCALERl/PCO. If PRESCALER1/PCO is an output, then the clock source is equal to the port data register
content, independent of the port electrical loading. If an input,
then the clock source is the logic level of PRESCALER1/PCO.

TACR1

TIMER B CONTROL AND STATUS REGISTER $00

and

PRESCALER1/PCO* Low-to-High Transition

TACR2

to be read. Read/write operations to the LSB are direct.
The LSB can be read at anytime without disturbing the
count. When the LSB is read, the .contents of the MSB
are loaded into the pipeline latch so a read of the MSB
is actually the contents of the latch.
When writing to the LSB, the contents are immediately
entered into the timer. At the same time the pipeline
contents are forced into the MSB of the timer. This allows
a 16-bit word to be placed into the timer data register
during a LSB write operation. An underflow condition is
also generated when value $00 is reached. This state can
be used to toggle bit 0 or bit 1 of port B directly under
the control of the miscellaneous register (MRO), the SPI
control register, and the port B data direction register.
Setting TBCR6 or the I bit in the condition control register
will prevent timer interrupts from being processed. The
timer interrupt request bit MUST be cleared bysoftware.

TBCR7 - Timer B Interrupt Request Flag
1 =TimerB has transition to $00
0= Software or reset cleared
TBCR6 - Timer B Interrupt Request Mask
1 = Interrupt request inhibited
0= Interrupt request not inhibited
TBCR5 - External or Internal Bit
1 = External clock source for prescaler 2
0= Internal clock source for prescaler 2
TBCR4 - External Enable Bit
Control bit used t6 enable the external timer pin
(PRESCALER2/PC1 ).
TBCR5

TBCR4

Prescaler 2 Clock Source

0

0

0

1

1

0

1

1

Internal Clock
AND of Internal Clock and
PRESCALER2/PCl *
Inputs Disabled
PRESCALER2/PCl * Low-to-High Transition

*The status of PRESCALER2/PCl depends upon the data direction status ofPRESCALER2/PC1. If PRESCALER2/PCl is an output, then the clock source is equal to the port data register
content, independent of the port electrical loading. If an input,
then the clock source is the logic level of PRESCALER2/PC1.
TBCR3, TBCR2, TBCR1, TBCRO - Prescaler 2 Division
Ratio Control Bits
When set, these bits select one of eight possible output
on prescaler 2.

TIMER B
This is a 16-bit timer which is accessed via two registers
($OB for the most-significant byte (MSB) and SOC for the
least-significant byte (LSB)). The.MSB has a "pipeline"
latch that allows a "snap shot" value of the entire 16 bits

TBCR2

TBCR1

TBCRO

0

0

0

0

1

0

0

0

1

2

0

0

1

0

MOTOROLA MICROPROCESSOR DATA

3-513

Divide By

TBCR3

4
- Continued -

II

MC6805S3

II

TBCR3

TBCR2

TBCR1

TBCRO

0

0

1

1

0

1

0

0

16

0

1

0

1

32

TCCl1 and TCClO - Timer C Clock Source Select
Clock source selection is defined below.

Divide By
8

0

1

1

0

64

0

1

1

1

128

,1

0

0

0

256

1

0

0

1

512

1

0

1

0

1024

1

0

1

1

2048

1

1

0

0

4096

1

1

0

1

8192

1

1

1

0

16384

1

1

1

1

32768

TCCl1

Timer C is an 8-bit programmable down counter. The
timer contains a modulus latch which allows the timer to
be auto reloaded. The timer auto reloads with the contents of the modulus latch upon every $01 to $00 transition. Timer C contains a capture register. This read-only
register and the contents are refreshed by the contents
of the data register during the capture instance. The timer
can be written to at any time, and the contents of both
the data register and modulus latch are updated immediately. The timer is set to $FF on reset, but the contents
of the capture register are not valid until the first capture
after reset.

TIMER C CONTROL REGISTER $015

1

TCOF

6
.1

TCOM

4
1

TCCF

1

TCCM

1
1

TCEG

TCCS

1

TCCll

0
1

TCClO

Timer B Source

Internal Clock

0

0

Internal Clock

1

MRl Status*

1

MRl Status*

0

Internal Clock

1

MR1 Status*

1

MR1 Status*

Internal Clock

NOTES:

TIMER C

7

Timer C Source

0

TCClO

1

RESET:

o

TCOF - Timer C Overflow Flag
1 = Timer C has transition to $00
0= Software or reset cleared
TCOM - Timer C Interrupt Mask
1 = Interrupt request inhibited
0= Interrupt request not inhibited
TCCF - Timer C Capture Flag
1 = Proper capture occurred on PRESCAlER1 or
PRESCAlER2. No new capture occurs when set
0= Software or reset cleared
TCCM - Timer C Capture Interrupt Request Mask
1 = Inhibits interrupt request generated from TCCF
0= Does not inhibit interrupt request generated from
TCCF
TCEG - Timer C Capture Edge Select
1 = Selects rising edge of PCOor PC1 to be capture
instance
0= Selects falling edge of PCO or PC1 to be capture
instance
TCCS - Timer C Capture Source Select
1 = Select PRESCAlER2/PC1 as capture source
O=Select PRESCAlER1/PCO as capture source

1, *Denotes prescaler 1 or 2 clock source depending on miscellaneous register bit 1 (MR1) status.
2. MR1 bit cleared (logic zero) at reset:
Prescaler 1 clock selected to timer A
Prescaler 2 clock selected to timer Band C
3. MRl bit set (logic one):
Prescaler 1 clock selected to timer Band C
Prescaler 2 clock selected to timer A
4. Prescaler 1 output determined by the status of Timer A
control register bits 2,1, and 0 (TACR2, TACR1, and TACRO)
5. Prescaler 2 output determined by the status of Timer B
control register bits 3, 2, 1, and 0 (TBCR3, TBCR2, TBCR1,
and TBCRO)

PRESCALER 1
Prescaler 1 is a 7-bit binary down counter whose value
is selected by TACR2, TACR 1, and TACRO. The selected
output is used as the clock input to either timer A or 8,
depending upon the status of the prescaler cross-couple
bit (MR1). The type of clock source to prescaler 1 maybe
selected by TACR5 and TACR4. Prescaler 1 is set to $7F
at reset or under program control when a one is written
to prescaler 1 clear bit (MR3).

PRESCALER 2
Prescaler 2 is a 15-bit down counter; its value is selected by T8CR3, T8CR2, T8CR1, and T8CRO. The selected output is used as the clock input to either timer A
or 8, depending upon the status of the prescaler crosscouple bit (MR1). The type of clock source to prescaler 2
may be selected by T8CR5 and T8CR4. Prescaler 2 is set
to $7FFF at reset or under program control when a one
is written to prescaler 2 clear bit (MR2).
AUXILIARY COUNTER
This register is a fixed counter which is clocked by the
internal clock (fosc divided by four). Total count period
is 4095 cycles. The MCU communicates with this counter
via the miscellaneous register (MR5 and MR4). Countdown may be aborted at any time under program control,
which also resets the counter to 4095 and clears MR5.
When MR4 is clear and MR5 is set as a result of counter
time out, the reset pin is internally pulled to ground. If
the MCU loses control of the program, the "watchdog"
timer will bring the MCU back to reset. Refer to Figure
13 for counter operation diagram.

SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) has arbitration on
the data and clock lines. The SPI communicates with the
MCU via data and control registers. The SPI data and

MOTOROLA MICROPROCESSOR DATA
3-514

MC6805S3

Auxiliary
Counter

EXTERNAL RESET ~

I

U;

RESET

. :IRES+

I
: [MR5]=1

I

I
I

I
I

I
I

MCU WRITE

8

o

o
o

O. [MR4i

I

~

1. [MR4i

1.[MR5i

VIRES -

TIME

::or::::

I I~_ L
I
LJ

: / [MR5]=O

'PIIIIIII

FORCED RESET ......... 1

I

I

[MR5]~
[MR4]

I

I
I
I

o.

I
I
I

[MR5]

I
I
O. [MR4i

Counter Preset by Writing "1"
Underflow: MR5 .1; No Forced Reset
Counter Reset by Writing "0"
Underflow MR5. 1 Forced Reset

Figure 13. Auxiliary Counter Operation
clock inputs are always taken from their respective [/0
ports, regardless of the status of the data direction registers relative to that port. The SPI can operate in modes
from auto clocked (NRZl, half duplex, and full duplex with
from a one to a four wire combination. Refer to Figure
14 for the SPI block diagram.

SPI CONTROL AND STATUS REGISTER
This 8-bit register contains the status and control bits
relative to SPI operations. The SPI control register operation is shown in Figure 15. The SPI control and status
register bits can be set or cleared under program control.

MOTOROLA MICROPROCESSOR DATA

3-515

II

MC6805S3

(SPICR3)'DATA OUT STROBE

II

DATA OUT
STROBE
DATA IN
STROBE

OVF

CLAD

CLEAR

SLAVE SELECT
ARBITRATION
LOGIC

OPEN DRAIN
ENABLE
DCRl

HI-Z ON PB3
HI-Z ON PB2

CLEAR

CLOCK

DATA IN
STROBE
TOGGLE
ENABLE
REGISTER
DCR4

MRO

TIMER B

TIMER A

OVERFLOW

Figure 14. Serial Peripheral Interface Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-516

DATA
DIRECTION
REGISTER
OCR BO

MC6805S3

76543210

ISPICR71 SPICR61 SPICR51 SPICR41 SP1CR31 SPICR21 SPICR1 ISPICRO I
RESET:

o
SPICR7 - SPI Interrupt Request Bit
Set on eighth data input strobe. MCU services this interrupt if I bit is clear in CCR.
1 = Interrupt request (if SPICR6 not masked)
0= No interrupt pending
SPICR6 - SPI Interrupt Request Mask Bit
1 = Disables interrupt request from SPICR7
0= Enables interrupt request from SPICR7
SPICR5 - SPI Clock Sense Bit/Bus-Busy Flag
Dual-function bit controlled by the status of SPICR4.
1 = Start SPI operation when SPICR4 = 1. Input data
latched on positive edge and output data changed
on negative edge of SPI clock when SPICR4 = O.
0= Stop SPI operation when SPICR4 = 1. Input data
latched on negative edge and output data changed
on positive edge of SPI clock wh~n $PICR4 =0.
SPICR4 - SPI Operation Enable Bit
This bit determines the functions of SPICR5 and SPICR2.
1 = Enables SPI data register shifting, data and clock
.
arbitration logic, and slave select input logic
0= Disables SPI data register shifting, data and clock
arbitration logic, and slave select input logic
SPICR3'-:" SPI Data Output Select Bit
1 = Output of the SPI data register is loaded to port
B3 data register at the appropriate SPI clock edge
selected by SPICR5, during the active transaction
mode

0= Output of the SPI data register is loaded to port
B2 data register at the appropriate SPI clock edge
selected by SPICR5, during the active transaction
mode
SPICR2 - Mode Fault Flag
Dual-function bit controlled by ·the status of SPICR4.
1 = Start bit is set by negative transition of the data
input of the SPI data shift register while the clock
is at the idle level when SPICR4 = 1. Start bit set
under program control to enable port B1 data register toggle facility when SPICR4 = O.
0= Stop SPI operation when SPICR4= 1. Cleared under program control when SPICR4=0.
SPICR1 - Mode Fault Flag
1 = (a) Mode flag is set when SPI data output arbitration occurs on theSPI data output port (PB3
or PB2) selected by SPICR3. The MCU loses
data mastership, and the SPI data output port
DDR is cleared.
(b) Mode flag is set if a low level is detected on
slave input PBO. Then, the MCU loses clock
mastership switching to the clock slave mode,
and port B1 DDR is cleared.
(c) Mode flag is set during the idle mode when a
negative clock edge is detected on the SPI clock
input, and the port B1 data register is cleared.
0= Cleared under program control
SPICRO - SPI Input Data Select Bit
1 = SPI data from port B3 is latched into the SPI data
register
0= SPI data from port B2 is routed to the input of the
SPI data register

INTERRUPT
REQUEST
TO CPU

FROM
PB1 PIN

$10
TO PB3
DATA REGISTER

LSB

TOPB2
DATA REGISTER

FROM
PB3 PIN
FROM
PB2 PIN

Figure 15. SPI Control Register .Operation

MOTOROLA MICROPROCESSOR DATA
3-517,

II

MC6805S3

SPI DATA REGISTER

This register can be written to any time and can also
be read, regardless of serial operations; without disturbing the data. A one bit shift to the left occurs each time
there is a data input strobe while the LSB is loaded with
data froni port 82 or 83. The MS8 is loaded every time
there is data output strobe. Data input and output strobes
are generated internally only during the active transaction time.
SPI DIVIDE-8Y-EIGHT COUNTER

The co~nter is cleared during SPI deselect or idle modes.
A count occurs at every data input strobe during the active transaction .mode. At overflow, SPICR7 is set which
puts the SPI in idle mode and blocks all data input and
output strobes. The counter is cleared when P80 is high
if the SPI is in thE:) slave mode or when a "start" condition
is detected.
.

II

SPI OPERATION

The SPI can operate in a variety of modes. Software
assisted protocols may be defined to upgrade the hardware versatilityand/or system performance of the MCU.
Some features common to all operating modes are summarized in Table 1 and in the following paragraphs.
1) SPI data input and output may be individually routed
to or from PB2 or PB3 (Table 2). These four routings
provide half and full duplex operations, as well as
allowing bidirectional information to flow in daisychained systems.
2) When data input and output is done on PB2, PB3
is available for any other use and vice versa.
3) Data input is always relative to the port pin logic
level regardless of the data direction register status
on that pin.
4) In full duplex operation, 16 bits of information may
be transferred with eight clock pulses between at
least two devices with transmit capability. Both P82
and PB3 are used for data transfer. The same shift
register is used for data in and data out. The byte
transl1)itted replaces the byte received. SPICR7 is .
used to signify that the liD operation is complete.
5) SPI clock is always provided on port B1. In the.clock
slave mode, port B1 DDR is in the input mode
(cleared). In the clock master mode, Port 81 DOH
is set; therefore, the MCU imposes the clock level
on P81 until there is clock arbitration on the clock
line or until the MCU loses clock mastership when
PBO goes low.
6) No fixed baud rate generation exists. The clock
frequency is dependent on the prescaler clock
source option, prescaler divide ratio, and timer divide ratio as well as the port C status in case of
external clocking for the timer. Toggling of the port
B1 data register is automatically allowed during
the active transmission mode.
7) All devices connected to the SPI m~st have their
output and input data strobe on the same clock
edge for correct transfer of data.
8) During the active transmission mode, the first clock
edge must be the output data strobe. When this

occurs, the MS8s of the data registers of all transmitters are copied onto the data. output pins, and
the MCU copies the MSB of its SPI onto the port
82 or B3 data register.
9) Port B data direction registers and port Bdata control registers are accessible during SPI operation.
During active transaction mode, the PB1 data register, P82 data register (if SPICR3 = 0), and P83 (if
SPICR3 = 1) are not write accessible under program
control.
10) Port B lines not used for SPI can be used for other
digital functions.
SELECT INPUT OPERATION

An external device supplies slave select information
via port BO. If slave select is not used, set port BO to output
mode to inhibit slave select function.
The following paragraphs describe clock master and
clock slave operating modes of the SP!.
Master Mode Slave Select Actions

The MCU.monitors slave select input in master mode
to assure that it stays false. If slave select goes true, the
MCU exits master mode and becomes a slave. This implies that.a write collision has occurred which means two
devices attempted' to become masters. Write collisions
normally result from a software error, and the default
master must clean up the system. The mode fault flag is
set to signal that clock mastership is lost. Slave select
actions. can take place during either active or idle transaction modes.
Slave Select Input Actions During Slave Mode

The current clock master generates slave select to enable one of several slaves to accept or return data. The
SS signal must go low before serial clock pulses occur
and must remain low until after the eighth serial clock
cycle. Individual lines or a daisy chain can be used for
multiple slaves. When SS is high, the following occur:
• Serial data output is forced to a high-impedance state
without affecting the DDR status.
• Serial clock input pulses are inhibited fromgenerating internal data output and input strobe pulses.
• The eight-bit counter is cleared.
SPI OPERATING MODES

Six methods of operating the SPI are discussed in the
following paragraphs.
One-Wire Autoclocked Mode

Various SPI devices can be connected on a single wire,
with data transmission using an implicit clock, and each
device being its own clock master.
Two-Wire Half-Duplex Mode

In this mode, separate data and clock lines connect the
elements in the system. Data and clock mastership should
be monitored via protocol included in the data patterns.
A transmitter can send all zeros to take all other transmitters off the bus.

MOTOROLA MICROPROCESSOR DATA
3-518

MC6805S3

Table 1. Summary of SPI Operations
DEFINITIONS
Transmitter - Data Master: DDRB2 or 3 = 1
Receiver -'Data Slave: DDRB2 or 3 = 0
Clock Master: DDRBI = 1
Clock Slave: DDRBI = 0
Transaction Mode: SPICR4 = 1
1) Active: SPICR7e(DDRBOePBO+ DDRBO) if DDRBI = 0 (clock slave mode) or
SPICR7e(DDRBOePBO+ DDRBO)if DDRBI = 1 (clock master mode)
Clock Pulses allowed, data shifted
2) Idle: SPICR7 + DDRBa-PBO if DDRBI = 0 (clock slave mode)
Clock pulses blocked, data output line in high-impedance state
Deselect Mode: SPICR4=0 - No SPI Operations
SLAVE SELECT INPUT
Slave Select Input: SPISS - PBO
If DDRBO = 0 then so SPISS action on MCU
1) Master Mode: SPISS = 1 DDRBI = 1
SPISS 1 - 0: Switch to Slave Mode (DDRBI 1- 0)
Set SPICRI (Mode Fault Flag)
2) Slave Mode: SPISS=O DDRBI =0
External clock is allowed to shift data in/out. If SPISS is pulled high, the external clock input pulses are inhibited;
no data shift; divide~by-eight counter cleared; SPID (PB20r PB3) switched to high-impedance state,
Used as Chip-Select Input
DATA ARBITRATION
Data master loses data rnastership when data collision occurs during internal data strobe time.
If SPlDoutput port (PB2 or PB3) =1 while actual pin level is pulled low externally - conflict detected at internal data strobe
time.
Then SPICRI (mode fault flag) is set; SPID 'outplit port DDR (B2 or B3) 1 .0 (high-impedance state).
CLOCK ARBITRATION
MCU has clock mastership (DDRBI = 1)
1) Via SP1SS line (DDRBO=O). If SPISS is pulled low, then clock mastership lost; DDRBll .0 (high-impedance state); SPICRI
is set (mode fault flag).
2) Via clock line SPICl (DDRBI = I and DCRB5 = 0)
Condition: SPICl must have open-drain output (DCRB5 = 0)
If clock line is held low externally then clock mastership is not lost; minimum tClH and tClK times are
guaranteed.
If SPICl goes low during idle mode then SPICRI = I and clock line is switched low to inhibit the system
clock.
'
MODE FAULT FLAGE OPERATION (SPICR!)
Flag set when any of the following conditions occur:
Data arbitration occurs on SPID output.
Clock arbitration with SPISS during master to slave switching.
Clock arbitration via clock line if SPICl 1.0 during idle.
START, STOP, AND CLOCK IDLE CONDITIONS
Clock Idle: The clock level just prior to the transition that causes qata on the serial output data line to be changed is defined
as the SPI clock idle state.
SPICR5 = 0: SPICl Idle = low State
SPICF!5 = I: SPICl Idle =High State
These definitions are necessary for determining start and stop conditions.
NOTE
Clock idle state can only be· definea if SPICR4 = 0 (Deselect Mode)
Start Condition: Any negative transition of the data input line (PB2 or PB3) during an SPICl idle state.
Stop Condition: Any positive transition of the data input line during an SPICl idle state.

MOTOROLA MICROPROCESSOR DATA

3·519

II

MC6805S3

Table 2. Port B Status During SPI Operation
Port
Name

Use

Input

Output

Comments

PBO
PBO

SPISS
Data

Yes
No

No
Yes

Used as slave select input
Used as "busy" signal or any digital
output

PB1
PB1

SPICl
SPICl

Yes
No

No
Yes

Clock slave
Clock master

PB2
PB2
PB2

SPID
SPID
Data

Yes
No
Yes

No
Yes
Yes

SPI data input SPICRO=O
SPI data output SPICR3 = 0
Any digital signal SPICR3 = 1

PB3
PB3
PB3

SPID
SPID
Data

Yes
No
Yes

No
Yes
Yes

SPI data input SPICRO= 1
SPI data output SPICR3 = 1
Any digital signal SPICR3 = 0

Three-Wire Half-Duplex Mode with Slave Select Input

II

are feasible. Protacols in the data stream are required to
change:
• Clack masters
• The number af transmitters in the system
• The direction af data flaw in daisy-chained systems
with collision
It is passible far the MCU tashift aut ane byte af data
while receiving anather, as illustrated in Figure 16. This
eliminates the need far XMIT EMPTY ar REC FULL status
bits.

This mode is the same as the half-duplex made except
that the slave select input allaws using the MCU as a
peripheral in a system where clack mastership is passed
through the slave select line. Typically, the slave select
lines can be wired tagether. The current master sets its
slave select line in the autput made priar to. a serial transmissian and pulls it low to. indicate that the system is
busy. This allaws the clack master to retain mastership
until the end of transmissian. Saftware protocol can be
arranged so that slaves do. nat request mastership until
their slave select lines go. high. At the end of a transmission, the current master pulls SPISS high and puts the
SPISS port (PBO) in the input mode. A slave requesting
clock mastership pulls the SPISS line low, remaving the
current master from the line. Time multiplexed protacals
may be required to. avaid simultaneous mastership requests.

Three-Wire Full-Duplex Mode with Clock Arbitration
This mode is a mix af the three-wire full-duplex made
and twa-wire half-duplex made with clack arbitratian,
where the SPI clock lineaperates as a wire-ar. Simultaneous masters are allawed, and clack arbitratian is via
the clack line.
Four-Wire Full-Duplex Mode with Slave-Select Input
This made is similar to. the three-wire full-duplex made
in netwark canstructian and to. the three-wire half-duplex
made with slave-select input in clock arbitratian and slave
selectian. Refer to. Figure 17.

Three-Wire Full-Duplex Mode
This made allaws the MCU to. aperate simultaneausly
as transmitter and receiver. Bus ar daisy-chain networks

VCC

.....---......----

SLAVE SELECT - - - - -.....------4~-----._-

CLOCK ------.~~-----__~----_.-~----__~---~
DATA - ...~

{
.-- {
~

EXAMPLE:

INFORMATION FLOW

B2=SPID IN
B3=SPIC OUT
B2=SPID OUT
B3=SPID IN

Figure 16. Daisy Chain/Cascade Organization

MOTOROLA MICROPROCESSOR DATA
3..520

MC6805S3

I---"

r- t---4

SPID:PB2/3
{ SPICL:PBl

*HALF DUPLEX

MCU 1

*HALF DUPLEX
{ SPID:PD2/3
WITH CLOCK ARBITRATION
SPICL:PBl
I---"

MCU 2

r- ~

*HALF DUPLEX
WITH SLAVE SELECT

~
Vc

*FULL DUPLEX

r- t---4

o

c:

en

*FULL DUPLEX
WITH SLAVE SELECT

...J

U

c:
en

SPID:PB2/3
SPICL:PBl
SPISS:PBO

SPID IN:PB2/3
SPID OUT:PB3!2
SPICL:PBl
SPID IN:PB2/3
SPID OUT:PB3!2
SPICL:PBl
{
SPISS:PBO

{

I---"

MCU 3

{

en
en

0

a::::
en

c:
en

Figure 17. SPI Operation Bus Organization

ANALOG-TO-DIGITAL CONVERTER
The chip resident 8 c bit analog-to-digital (AID) converter
uses a successive approximation technique as shown in
Figure 18. Four external analog inputs can be connected
to the AID through a mUltiplexer via Port D. Four internal
analog channels (VRH - VRL VRH - VRL/2, VRH - VRL/4,
and VRU may be selected for calibration. The accuracy
of these internal channels may not meet the accuracy
specifications of the external channels.
A fifth external analog input (AN4) is available via mask
option. When selected, it replaces the VRH internal channel. Due to signal routing, the accuracy of this fifth channel may be slightly less than ANO-AN3.
Multiplexer selection is controlled by the AID control
register (ACR) bits 0, 1, and 2. Refer to Table 3 for multiplexer selection. The ACR is shown in Figure 18. The
converter uses 30 machine cycles to complete a conversion of a sampled analog input. When the conversion is

complete, the digital value is placed in the AID result
register (ARR); the conversion flag is set; selected input
is sampled again; and a new conversion begins. When
ACR7 is cleared, the conversion in progress is aborted
and the selected input, which is held internally, is sampled for five machine cycles.
The converter uses VRH and VRL as reference Voltages.
An input voltage equal to or greater than VRH converts
to $FF. An input voltage equal to or less than VRL but
greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded. Each analog input
source should use VRH as the supply voltage and be
referenced to VRL for the ratiometric conversion. To
maintain full accuracy of the AID, three requirements
should be followed: (1) VRH should be equal to or less
than VCC, (2) VRL should be equal to or greater than VSS
but less than maximum specifications, and (3) VRH - VRL
should be equal to or greater than 4 volts.

Table 3. AID Input MUX Selection
AID Control Register
ACR2

ACR1

ACRO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Input Selected
ANO
AN1
AN2
AN3
VRH**
VRL*
VRH/4*
VRHI2*

AID Output (Hex)
Min

Typ

Max

FE**
00
3F
7F

FF**
00
40
80

FF**
01
41
81

*Internal (calibration) levels
**AN4 may replace the VRH calibration channel if selected via mask
option.

MOTOROLA MICROPROCESSOR DATA
3-521

II

MC6805S3

D/A
CONTROL
LOGIC

15 k (TYP.l

COUNT

PD5IVRH
PD4IVRL ---+-..
PDO/AND
1-OF-8
SELECT
MULTIPLEXER

PD1/ANl
PD2/AN2
PD3/AN3
INT2/PD6/AN4 -

II

.....- - - - - - " '

AID
CONTROL u
REGISTER ~r--.----'.To 1/0 Logic

Vary V,
Measure I

.

±

Figure 17. Typical Input Protection

v·

Figure 18. I/O Characteristic
Measurement Circuit

MOTOROLA MICROPROCESSOR DATA
3-545

II

MC6805U2

ELECTRICAL CHARACTERISTICS (VCC= +5.25 Vdc ±0.5 Vdc, VSS=O Vdc, TA=TL to TH, unless otherwise noted)
Characteristic

Symbol

Input High Voltage
RESET (4.75",VCC"'5.75)
(VCC<4.75)
INT (4.75",VCC"'5.75)
(VCC<4.75)
All Other (Except Timer)

V,H

Input High Voltage Timer
Timer Mode
Self-Check Mode

V,H

Input Low Voltage
RESET
INT
All Other

V,L

Typ

Max

4.0
VCC-0.5
4.0
VCC-0.5
2.0

-

Vct
VCC
VCC
VCC
VCC

2.0
9.0

-

Unit
V

*
*

-

V
10.0

VCC+l.0
15.0
V

VSS
VSS
VSS

-

V'RES+
V'RES-

2.1
O.B

-

4.0
2.0

INT Zero-Crossing Voltage, Through a Capacitor

V,NT

2

4

Vac pop

Internal Power Dissipation (No Po'rt Loading,
TA=O°C
VCC=5.75 V for Steady-State Operation)
TA= -40°C

P,NT

-

520
5BO

740
BOO

mW

25
10

-

*

-

O.B
1.5
O.B
V

Reset Hysteresis Voltages
"Out of Reset"
"Into Reset"

I

Min

Input Capacitance
XTAL
All Other

-

pF

Cin

Low Voltage Recover
Low Voltage Inhibit
Input Current
TIMER (Vin = 0.4 V)
INT (Vin=2.4 V to VCC)
EXTAL (Vin=2.4 V to VCC Crystal Option)
_ _ (Vin = 0.4 V Crystal Option).
RESET (Vin=O.B V)
(External Capacitor Charging Current)

-

VLVR

-

-

4.75

V

VLVI

2.75

3.75

4.70

V

lin

-

IRES

-4.0

-

!LA

20

-

-

20
50
10
-1600
-40

*Due to internal biasing, this input (when unused) floats to approximately 2.0 V.

SWITCHING CHARACTERISTICS. (VCC= +5.25 Vdc ±0.5 Vdc, VSS=O Vdc, TA=TL to TH, unless otherwise noted)
Characteristic
Oscillator Frequency

Symbol

Min

Typ

Max

Unit

fosc

0.4

-

4.2

MHz

-

10

!Ls

-

ns

tCYC

0.95

tWL, tWH

t cyc +250

RESET Pulse Width

tRWL

t cvc +250

RESET Delay Time (External Cap = 1 ILF)

tRHL

INT Zero-Crossing Detection Input Frequency

flNT

0.03

-

40

50

60

%

-

-

100

ms

Cycle Time (4/foscl
INT, INT2, and TIMER Pulse Width

External Clock input Duty Cycle (EXTAL)
Crystal Oscillator Start-Up Time

-

MOTOROLA MICROPROCESSOR DATA
3-546

ns

100

-

ms

-

1.0

kHz

MC6805U2

PORT ELECTRICAL CHARACTERISTICS (Vce= +5.25 Vdc ±0..5 Vdc, VSs=o. Vdc, TA=TL to TH, unless otherwise noted)
<

Characteristic

Symbol

Min

Typ

Max

-

0..4

V

-

V

Unit

Port A with CMOS Drive Enabled
VOL

-

Output Hig'h Voltage, ILoad= -10.0.

VOH

2.4

Output High Voltage, 'Load =

Output Low Voltage, 'Load = 1.6 mA

JLA
-10. JLA

VOH

VCC-1.0.

-

Input High Voltage, 'Load= -30.0. fJ.A (max.)

V,H

2.0.

Vce

V

Input Low Voltage, 'Load = - 50.0. fJ.A (max.)

V,L

VSS

-

0..8

V

Hi-Z State Inpu~ Current (Vin = 2.0. V to Vccl

IIH
IlL

-

-

-30.0.

Hi-Z State Input Current (Vin = 0..4 V)

-50.0.

JLA
!LA

V

Port B
Output Low Voltage, ILoad = 3.2 mA

VOL

0..4

V

VOL

-

-

Output Low Voltage, ILoad=10. mA (Sink)

-

1.0.

V

VOH

2.4

-

-

Darlington Current Drive (Source), Vo = 1.5 V

IOH

-1.0.

Input High Voltage

V,H

2.0.

V,L

VSS

-

ITS I

-

Output High Voltage, ILoad= -20.0.

JLA

<

Input Low Voltage
Hi-Z State Input Current

<

V

-10.

mA

VCC

V

0..8

V

<2

10.

fJ.A

-

0..4

V

-

V

Port C and Port A with TTL Drive
Output Low Voltage,ILoad=1.6 mA

VOL

-

VOH

2.4

Input High Voltage

V,H

2.0.

-

VCC

Input Low Voltage

V,L

VSS

-

0..8

V

Hi-Z State Input Current

ITSI

-

<2

10.

fJ.A

Output High Voltage,lLoad = -10.0.

JLA

<>

V

Port C (Open-Drain Option)
Input High Voltage

V,H

2.0.

-

13.0.

V

Input Low Voltage,

V,L

VSS

-

0..8

V

Input Leakage Current (Vin = 13.0. V)

ILOD

15

fJ.A

VOL

-

<3

Output Low Voltage 'Load= 1.6 mA

-

0..4

V

Port D (Digital Inputs Only)
Input High Voltage

V,H

2.0.

-

Vec

V

Input Low Voltage

V,L

VSS

-

0..8

V

Input Current

lin

-

<1

5

fJ.A

MOTOROLA MICROPROCESSOR DATA
3-547

II

MC6805U2

ORDERING INFORMATION
The following information is required when ordering a
custom MCU. The information may be transmitted toMotorola in the following media:
MDOS@>, disk file
MS@>-DOS/PC-DOS disk file
EPROM(s)MC68705R3, 2532, 2732, or two 2516/2716
To initiate a ROM pattern for the MCU, it is necessary to
first contact the local field service office, a sales person,
or Motorola representative.

II

FLEXIBLE DISKS
Several types of flexible disks (MDOS or MS-DOS/PCDOS disk file), programmed with the customer program
(positive logic sense for address and data), may besubmitted for pattern generation. In either case, the diskette
should be clearly labeled with the customers name, date,
project or product name, and the name of the file containing the pattern.
In addition to the program pattern, a file containing the
program source code listing can be included. This data
will be kept confidential and used to speed upthe process
in case of any difficulty with the pattern file.
MOOS Disk File
MDOS is Motoria's Disk Operating System available on
the EXORciser® development system. The disk media
submitted must be a single-sided, single-density, 8-inch
MDOS compatible floppy diskette. The diskette must contain the minimum set of MDOS system files.in addition
to the pattern file.
The .LO output of the M6805 cross· assembler should
be furnished. In addition, the file must be produced (using
the ROLLOUT command) containing the absolute image
of the M6805 memory. Include the entire memory image
of both date and program space. All unused bytes, includingthose in the user space, must be set to zero.
MS-DOS/PC-DOS Disk File
MS-DOS is Microsoft's Disk Operating System. pc~bOS
is IBM® Personal Computer (PC) Disk Operating System.
Disk media submitted must be a standard density (360K)
double-sided 5 114 inch compatible floppy diskette. The
diskette must contain object file code in Motorola's Srecord format. The S-record format is a character-based
object file format generated by M6805 cross assemblers
and linkers on IBM-PC style machines.

For the 2532, 2732, or the MC68705R3, the ROM code
should be located from $080 to $FF and $7CO to $F37 and
the interrupt vectors from $FF8 to $FFF. For the 2516's
or 2716:s, the ROM code should be located from $080 to
$FF and $7CO to $7FF in the first EPROM and from $0 to
$737 in the second EPROM. The interrupt vectors should
be in the second EPROM from $7F8 to $FFF.
EPROM MARKING

xxx = Customer ID

VERIFICATION MEDIA
All original pattern media (EPROMs or floppy disk) are
filed for contractual purposes and are not returned. A
computer listing of the ROM code will be. generated and
returned along with a listing verification form. The listing
should be thoroughly checked and the verification form
completed, signed, and returned to Motorola. The signed
verification form constitutes the contractual agreement
for creation of the customer mask. If desired, Motorola
will program (customer supplied) blank EPROM(s) or DOS
disk from the data file used to create the custom mask
to aid in the verification process.

ROM VERIFICATION UNITS (RVUs)
Ten MCUs containing thecustomer's ROM pattern will
be sent for program verification. Thes.e units will have
been made using the custom mask but are for the pu~~
pose of ROM verification only. For expediency theMCUs
are unmarked, packaged in ceramic, and tested at room
temperature and five volts. These RVUs are free with the
minimum order quantity but are not production parts.
These RVUs are not guaranteed by Motorola Quality
Assurance.
ORDERING INFORMATION
The following table provides generic information pertaining to the package type, temperature, and MC part
numbers for the MC6805U2.

EPROMs

Table 4. Generic Information
Package Type

An MC68705R3, 2532, 2732, 2516 (2), or 2716 (2) type
EPROM(s), programmed with the customer program (positive logic sense for address and data) may be submitted
for pattern generation. Since all program and data space
information will fit on one MC68705R3/2532/2732 or two
2516/2716 type EPROM(s), the EPROM(s) must be programmed as described in the following paragraph.

Temperature

Part Number

PLCC
FN Suffix

O°C to 70°C
- 40°C to + 85°C

MC6805U2FN
MC6805U2CFN

Plastic
P Suffix

O°C to 70°C
- 40°C to + 85°C

MC6805U2P
MC6805U2CP

Cerdip
S Suffix

O°C to 70°C
- 40°C to + 85°C

MC6805U2S
MC6805U2CS

MDOS is a trademark of Motorola Inc.
MS-DOS is a trademark of Microsoft, Inc.
EXORciser is a registered trademark of Motorola Inc.
IBM is a registered trademark of International Business Machines Corporation.

MOTOROLA MICROPROCESSOR DATA
3-548

MC6805U2

MECHANICAL DATA

PIN ASSIGNMENTS
Dual-in-Line Package

Vss

PD6/1NT2
PD5
PD4

PlCC Package

_cx:>a..a..a..a..z

l!z

PA3
PA2
PAl
PAO
P87
P86
P85
P84
PB3
PB2
PB1

XTAL
(VSS) NUM
TIMER
PCO
PCl
PC2
PC3
PC4
PC5
NC
PC6
I' I'

IN - -

(J) - -

-'- -

0

uo~~a!(J)2~Z~CXl

a.. a.. ~??> ~~~~a..
('t) N
0
CDLn'ntrol instruction with no
other arguments are included in this mode. These instructions are one byte long.

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS

Rating

II

Symbol

Value

Unit

Supply Voltage

VCC

-0.3 to +7.0

V

Input Voltage
Self-Check Mode (TIMER Pin Only)

Vin

-0.3 to +7.0
- 0.3 to + 15.0

V

Operating Temperature Range
MC6805U3
MC6805U3C
MC6805U3V

TA

TL to TH
o to 70
-40 to +85
-40 to + 105

°c

TstQ

-55 to + 150

°c

Storage Temperature Range
Junction Temperature
Plastic
PlCC
Cerdip

°c

TJ

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions· be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. For proper operation, it is recommended the Vin and Vout be constrained to
the range VSS .;; (Vin or Vout) .;; VCC. Reliability of operation is enhanced if unused inputs except EXTAl are tied to an appropriate
logic voltage level (e.g., either VSS or VCC).

150
150
175

THERMAL CHARACTERISTICS

Characteristic
Thermal Resistance
Plastic (P Suffix)
PlCC (FN Suffix)
Cerdip (S Suffix)

Symbol

Value

Unit
°CIW

eJA
60
100
60

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in °c can
be obtained from:
TJ=TA+(POoeJA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
eJA
Junction-to-Ambient, °CIW
Po
= PINT+ PPORT
= ICC x VCC, Watts - Chip Internal Power
PINT
PPORT = Port Power Oissipation,
Watts - User Oetermined

For most applications PPORT-a::>o...o...o...o...z

6
PA3
PA2
PA1
PAO
PB7
PB6
PB5
PB4
PB3
PB2
PB1

XTAL
(VSS) NUM
TIMER
PCO
PC1
PC2
PC3
PC4
PC5
NC
PC6
r-. r-.

lrf2

IN!zf2~~~~~~f
N... °
LO V

(/) M

0,

~
0

0...

MOTOROLA MICROPROCESSOR DATA'
3-567

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC68705P3

Technical Summary

8-Bit EPROM Microcomputer Unit

II

The MC68705P3 (High-Density NMOS) Microcomputer Unit (MCU) is an EPROM member of the
MC6805 Family of microcomputers. The user programmable EPROM allows program changes and
lower volume applications. This low cost MCU has parallel 1/0 capability with pins programmable
as input or output. This publication contains condensed information on the MCU; for detailed information, refer to M6805 HMOS, M146805 CMOS Family User's Manual (M6805UM(AD2)) or contact
your local Motorola sales office.
Refer to the block diagram for the hardware features and to the list below for additional features
available on the MCU.
• Internal 8-Bit Timer with 7-Bit
• Bit Test and Branch Instruction
Programmable Prescaler
• Vectored Interrupts
• On-chip Oscillator
• Bootstrap program in ROM
• Memory Mapped 1/0
• 1804 Bytes EPROM
• Versatile Interrupt Handling
• 112 Bytes RAM
• Bit Manipulation
• 20 TTUCMOS Compatible Bidirectional 1/0 Lines

BLOCK DIAGRAM

TIMER

Data
Dlr
Reg

Port
B
Reg

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

Data
Dlr
Reg

Port
C
Reg

PCO
PCl
PC2
PC3

Accumulator
A

8

Port
A
I/O
lines

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

8
Port
A
Reg

5

115X8
Bootstrap ROM

CPU
Control

X

Condition
Code
Register CC

Data
Dlr
Reg

1804 X 8
EPROM

Index
Register

Stack
POinter

Port
B
1/0

lines

CPU
SP

3

Program
Counter
High PCH

8

Program
Counter
low PCl

AlU

112 X 8
RAM

This document contains information on a new product. Specifications and fnformation herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-568

Port
C
I/O
lines

MC68705P3

SIGNAL DESCRIPTION

8.0.--...,.------------------,

VCC AND VSS
Power is supplied to the microcomputer using these
two pins. VCC is + 5.26 volts (± O.5d) power, and VSS is
ground.

7.0

~ 6.0

VCC=525 V
T A = 25·C

>-

~ 5.0

!

Vpp
This pin is used when programming the EPROM. In
normal operation, this pin is connected to Vcc.

40

~ 3.0

Q

2.0

c3

INT
This pin provides the capability for asynchronously applying an external interrupt to the MCU. Refer to INTERRUPTS for more detailed information.

1.0
10

20

40
30
50
ReSistance IkOi

BO

are to be used. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time.
External Clock
An external clock should be applied to the EXTAl input
with the XTAl input connected to ground, as shown in
Figure 1. This option may only be used with the crystal
oscillator option selected in the mask option register.

RC Oscillator
With this option, a resistor is connected to the oscillator
pins as shown in Figure 1. The relationship between R
and' fosc is shown in Figure 2.
Crystal
The circuit shown in Figure 1 is recommended when
using a crystal. Using an external CMOS oscillator is recommended when crystals outside the specified ranges

TIMER
This pin is used as an external input to control the
internal timer/counter circuitry. This pin also detects a

~XTAL
External Clock

70

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option only

EXTAL,XTAL
These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal is connected to these pins
to provide a system clock. Selection is made by the ClK
bit in the mask option register.

5 XTAL

60

5 XTAL
MCU

4 EXT AL

(C~Y~~lb~~t~.n;

4 EXTAL

See Note 11

Input

MCU
IRC Option.
MOR b7= 1.
See Note 1)

Crystal
ApprOXimately 25% to 50% Accuracy
TYPical tcyc= 1.25 ~s
External Jumper

External Clock
Crystal Parameters

EXTAL

4

C,

~~XTAL
~W'5

VCC

L..J\/VI_~~

XT AL
MCU

AT - Cut Parallel Resonance Crystal
Co =7 pF Max.
Freq=4.0 MHz@CL=24pF
RS = 50 ohms Max.

No
Connection

Piezoelectric ceramic resonators which
have the equivalent specifications may be
used instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO. C,. and RS values

EXT AL

~~RO~;i~~ ..
See Note 1)

ApprOXimately 10% to 25% Accuracy
I Excludes ReSistor Tolerance)
External ReSistor

NOTES:
1. When the TIMER input pin is in the VIHTP range (in the bootstrap EPROM programming mode), the crystal option is forced.
When the TIMER input is at or below VCC, the clock generator option is determined by bit 7 of the mask option register (ClK).
2. The recommended Cl value with a 4.0 MHz crystal is 27 pF maximum including system .distributed capacitance. There is an
internal capacitance of approximately 25 pF on the XTAl pin. For crystal freque'ncies other than 4 MHz, the total capacitance on
each pin should be scaled as the inverse of the frequency ratio. For example, with a 2 MHz crystal, use approximately 50 pF on
EXTAl and approximately 25 pF on XTAL. The exact value depends on the motional-arm parameters of the crystal used.

Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR DATA
3-569

II

MC68705P3

higher voltage level used to initiate the bootstrap program.

port output registers are not initialized on reset and should
be written to before setting the DDR bits.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Care must
be exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (0) and also the latched output when the
DDR is an output (1). Refer to Table 1 for 1/0 functions
and to Figure 3 for typical port circuitry.

RESET
This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low. Refer
to RESETS section for more detail.
INPUT/OUTPUT LINES (PAO-PA7, PBO·PB7, PCO·PC3)
These 20 lines are arranged into two a-bit ports (A and
B) and one 4-bit port (C). All lines are programmable as
either inputs or outputs under software control of the
data direction registers. Refer to PROGRAMMING for additional information.

Table 1. I/O Pin Functions
Data
Direction
Register
Bit

PROGRAMMING

II

INPUT/OUTPUT PROGRAMMING

Output
Data
Bit
0
1

1
1
0

Any port pin is programmable as either input or output
under software control of the corresponding write-only
data direction register (DDR); DDRs always read "1". The
port I/O programming is accomplished by writing the
corresponding bit in the port DDR to a logic 1 for output
and a logic 0 for input. On reset, aft the DDRs are initialized
to a logic 0 state to put the ports in the input mode. The

X

Input
To

Output
State

MCU

0
1
Hi-Z""

0
1
Pin

""Ports A (with CMOS drive disabled), B, and C are three state
ports. Port A has optional internal pullup devices to provide
CMOS drive capability. See Electrical Characteristic tables for
complete information.

Data
Direction Register
Bit"
III

~

c:

.g

Q) ~

-c: c:

-

0

u

Latched

Output
Data

Bit

"DDR is a write-only register and reads as all "ls",

7

PORT DATA REGISTER

o

7

PORT DATA DIRECTION REGISTER IDDRI

(1) Write Only; reads as all "15"
(21 1- Output; O~ Input, Cleared to 0 by

Port A Addr= $000
Port B Addr= $001
Port C Addr= $002 (Bits 0-31

(31 Port A Addr= $004
PortB Addr=$005
PortC Addr=$006 (Bits 0-31

Figure 3. Typical Port I/O Circuitry and Register Configuration

MOTOROLA MiCROPROCESSOR DATA
3-570

o

reset.

MC68705P3

MEMORY

,I

A

The MCU is capable of addressing 2048 bytes of memory and I/O registers. The memory map is shown in Figure
4. The locations consist of user EPROM, bootstrap ROM,
RAM, a mask option register (MOR), a program control
register, and I/O. The interrupt vectors are located from
$7F8 to $7FF. The bootstrap is a mask-programmed ROM
that allows theMCU to program its own EPROM.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may be added to an 8- or 16-bit immediate value to create
an effective address. The index register may also be used
as a temporary storage area.
7

0

x

I

NOTE
Using the stack area for data storage or temporary
work locations requires Care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

1

PROGRAM COUNTER (PC)
The program counter is an 11-bit register that contains
the address of the next byte to be fetched.
.
10

8 7

0

PCH

1

pel

I

REGISTERS
STACK POINTER (SP)
The stack pointer is an 11-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.

The MCU contains the registers described in thefollowing paragraphs.
"
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.
000
Page Zero
Access with
Short
Instructions

127
128
2
256

7

0

7
I/O Ports Timer
and
RAM
1128 Bytes)

$000

2

Page Zero
User EPROM
1128 Bytes)

6

5

0

4

3

2

$000

Port B

$001
Port C

1 1

Not Used

$003

4

Port A DDR *

$004

5

Port B DDR*

$005

1 1

PortCDDR $006

Not Used

Mask Option Reg

Timer Data Reg

$008

9

Timer Control Reg

$009

10

Not Used

$OOA

11

Programming
Control Re

$OOB

, -__I_ll_5.;..B_y_te_s_)_ ...... $7F7
$7F8
Timer Interrupt
$7F9
$7FA
$7FB
$7FC
$7FD
$7FE
....._ _ _R_ese_t_ _- - ' $7FF

Not Used

Figure 4. Memory Map

MOTOROLA, MICROPROCESSOR DATA

$OOC-OOF
$010

RAM
1112 Bytes)
Stack

Caution: pata Direction Registers /DORs) are write-only; they read as $FF.

3-571

$007

8

12
15
16

Bootstrap
ROM

$002

3

6
Main User
EPROM
11668 Bytes)

0

Port A

$07F

II

Me68705P3

The six most-significant bits of the stack pointer are
permanently set at 000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to 15
levels of subroutine calls (less if interrupts are allowed).
10

5 4

1 0 1 0 1 0 1 0 11 11 1

allowing the RESET input togo high. Connecting a capacitor to the RESET input (Figure 5) typically provides
sufficient delay.

-

0
SP

1

1

VCC~'VV\.--+--_

::r:: 1.0 "F

CONDITION CODE REGISTER (CC)

The condition code register is a 5-bit register in which
four bits are used to indicate the results of the instruction
just executed. These bits can be individually tested by a
program, and specific actions can be taken as a result of
their state. Each bit is explained in the following paragraphs.
Figure 5. Power-up RESET Delay Circuit

II

EXTERNAL RESET INPUT
Half Carry (H)

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

The MCU is reset when a logic zero is applied to the
RESET input for a period longer than one machine cycle
(tcycl. Under this type of reset, the Schmitt trigger switches
off at VIRES - to provide an internal reset voltage.

Interrupt(!)

When this bit is set, the timer and external interrupt is
masked (disabled). If an external interrupt occurs while
this bit is set, the interrupt is latched and is processed as
soon as the interrupt bit is cleared.
Negative (N)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative
(bit 7 in the result is a logic 1);
Zero (Z)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.
Carry/Borrow (C)

INTERRUPTS
The MCU can be interrupted three different ways: (1)
through the external interrupt INT input pin, (2) with the
interna.1 timer interrupt request, or (3) using the software
interrupt instruction (SWI).
Interrupts.cause the processor registers to be saved on
the stack and the interrupt.mask· (I bit) set to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and then
normal processing resumes. The stacking order is shown
in Figure 6.
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.

When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and during shifts and
rotates.

NOTE

The current instruction is considered to be the one
already fetched and being operated on.
7

n-·4

RESETS
The MCU can be reset two ways: by initial power-up
and by the external reset input (RESET). The RESET in£!!!
consists mainly of a Schinitt trigger that senses the RESET line logic level.

6

5

11 1

n-2

4

I

Accumulator

n+2

Index Register

n+3

n- 1 1 1 1 1 1
POWER-ON-RESET (POR)

An internal reset is generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power turn-on conditions· and
should not be used to detect any drop in the power supply
voltage. A delay of tRHL milliseconds is required before

n

I
PCl*

PCH*

Pull

n+4
n+5

Push
* For subroutine calls. only PCH and PCl are stacked.

Figure 6. Interrupt Stacking Order

MOTOROLA MICROPROCESSOR DATA
3-572

3 2 1 0
Condition
Code Register n+l

MC68705P3

When the current instruction is complete; the processor
checks all pending hardware interrupts and, if unmasked
(I bit clear), proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Masked
interrupts are latched for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 7 for the reset and interrupt
instruction processing sequence.

an interrupt request is generated. The actual processor
interrupt is generated only if the interrupt mask bit of the
condition code register ICCR) is also cleared. When the
interrupt is recognized, the current state of the machine
is pushed onto the stack, and the I bit in the CCR is set,
masking further interrupts until the present one is serviced. The contents of the timer interrupt vector, containing the location of the timer interrupt service routine, is
then loaded into the program counter. At the end of the
timer interrupt service routine, the software normally executes an RTI instruction which restores the machine state
and starts executing the interrupted program.

EXTERNAL INTERRUPT
TIMER INTERRUPT
If the timer mask bit (TCR6) is cleared, then, each time
the timer decrements to zero (transitions from $01 to $00),

The external interrupt is interna~synchronized and
then latched on the falling edge of INT. Clearing the I bit
enables the external interrupt. The following paragraphs
describe two typical external interrupt circuits.

II
1-1 Bit (In CCI
07F-SP
O-DDRs
CLR INT Logic
FF-Tlmer
7F-P rescaler
7F-TCR

lear
INT
Request
Latch

StaCk
PC, X, A, CC

Load PC From
SWI7FC17FD
INT 7FA17FB
TIMER 7F817F9

Put 7FE on
Address Bus

Fetch
Instruction

SWI

Load PC
from
7FE17FF

Execute All
Instruction
Cycles

Figure 7. Reset and Interrupt Processing Flowchart

MOTOROLA MICROPROCESSOR DATA
3-573

MC68705P3

Zero-Crossing
A sinusoidal input signal (fINT maximum) can be used
to generate an external interrupt (see Figure 8a) for use
as a zero-crossing detector (for negative transitions of
the ac sinusoid). This type of circuit allows applications
such as servicingtime-of-day routines and engaging/disengaging ac power control devices. Off-chip, full-wave
rectification prOvides an interrupt at every zero crossing
of the ac signal and thereby provides a 2f clock.
Digital-Signal.lnterrupt
With this type of circuit (Fibure 8b), the INT pin can be
driven by a digital signal. The maximum freque~ of a
signal that can be recognized by the TIMER or INT pin
lo.gic .is dependent on the parameter labeled tWL, twH.
Refer to TIMERfor additional information.
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. If the I bit

I

is zero, SWI executes after the other interrupts. The SWI
execution is similar to the hardware interrupts.

TIMER
The MCU consists of an 8-bit software programmable
counter driven by a i-bit software programmable prescaler. Various timer sources are made via the timer control reQister (TCR). The 8-bitcounter may be loaded under
program control and is decremented toward zero. When
the. timer reaches zero, the timer interrupt request bit (bit
7) in the timer control register (TCR) is set. Refer to Figure
9 for timer block diagram.
Timer interrupt can be masked (disabled) by setting the
timer interrupt mask bit (bit 6) in the TCR. When the I bit
in the condition code register is cleared, and TCR bit 6 is
cleared, the processor receives the interrupt. The MCU
responds to this interrupt by 1) saving the present CPU
state on the stack, 2) fetching the timer interrupt vector,

Ibl Digital-Signal Inte"upt

lal Zero·Croaaing InterruPt

VCC
Inapc
ut

TTL

(Current

aX.)~Llml\lngl
Rs1 Mn

(f'NT M.

ac Inputs

10 Vac pop . .

R

2 iNT

4.7 k

~~~~~1 _ _~~2 iNT

MCU

Input

0.1-1.0
I'F

MCU

lJ -----'----

Figure 8. Typical Interrupt Circuits

Figure 9. Timer Bloc.k Diagram

MOTOROLA MICROPROCESSOR DATA
3-574

MC68705P3

and 3) executing the interrupt routine. Timer interrupt
request bit must be cleared by software. Refer to RESETS
and INTERRUPTS for additional information.
The prescaler is a 7-bit divider which is used to extend
the maximum length of the timer. To avoid truncation
errors, the prescaler is cleared when TCR bit 3 is set to
a logic 1; however, TCR bit 3 always reads as a logic 0
to ensure proper operation with read-modify-write instructions.
The timer continues,to count past zero, falling from $00
through $FF, and continues the countdown. The counter
can be read at any time by reading the timer data register
(TOR). This allows a program to determine the length of
time sihce a timer interrupt has occurred without disturbing the counting process. TOR is unaffected by reset.

TIMER CONTROL REGISTER (TCR) $00$'
This is an 8-bit register that controls various functions
such as configuring operation mode, setting ratio of the
prescaler, and generating timer interrupt request signal.
All bits are read/write except bit 3. When the MOR
TOPT = 1, then bits 5, 2, 1, and 0 in the TCR take on the
corresponding bits of the MOR during reset.
765432

RESET:

o

u

Timer Input Mode 1
When TIE and TIN are both programmed to zero, the
timer input is from the internal clock (phase 2) and the
timer input pin is disabled. The internal clock mode can
be used for periodic interrupt generation as well as a
reference for frequency and event measurement.
Timer Input Mode 2
When, TIE = 1 and TIN= 0, the internal clock and the
timer input signals are ANDed to form the timer input.
This mode can be used to measure external pulse widths.
The active high, external pulse 'gates in the internal clock
for the duration of the external pulse. The accuracy of
the count is ± 1.
Timer Input Mode 3
When TIE = 0 and TIN = 1, no prescaler input frequency
is applied to the prescaler and the timer is disabled.
Timer Input Mode 4
When TIE and TIN are both one, the time(input is from
the external clock. The external clock'can be used to count
external events as well as to provide an external frequency for generating periodic interrupts.
'

u

TCR with MOR TaPT = I (MC6805P2IP6 Emulation)

TIR

SOFTWARE CONTROLLED MODE
The timer prescaler input can be configured for three
different operating modes plus adisable mode, depending on the value written to TCR'control bi~s <;l and 5 (TIE
and TIN). The following paragraphs describe the different
modes.

I

I TlR I TIM

TiM

TIE

Tlf\!

PSC

PS2

PSI

PSO

RESET:

o

TCR with MaR TaPT = 0 (Software Programmable Timer)

TIR - Timer Interrupt Request
Used to indicate the timer interrupt when it is logic
one
1 = Set when the timer data register changes to all
zeros
0= Cieared by external reset, power-on reset, or
under program control
TIM - Timer Interrupt Mask.
.,
Used to inhibit the timer interrupt.
1 = Interrupt inhibited
0= Ihterrupt enabled
TIN - External or Internal
Selects input clock source
1 =;= External clock selected
0= Internal.clockselected (fosc/4)
TIE - TIMER External Enable.
Used to enable external TIMER pin
1 = Enables external tim('lr pin
0= Disables external timer pin
PSC - Prescaler Clear
Write only bit. Writing a 1 to this bit resets the prescaler to zero. A read of this location always indicates
a zero.
PS2, PS1, PSO - Prescaler Select Bits
Decoded to select one of eight outputs of the prescaler

MOR CONTROLLED MODE
This mode is selected when TOPT (bit 6) in the MOR
is programmed to logic 1. The timer circuits are the same
as described in SOFTWARE CONTROLLED MODE. The
logic levels of TCR bits 0, ,1,2, and 5 are determined
during EPROM programming by the same bits in the MOR
Therefore, bits 0, 1,2, and 5 inthe MORcontrol the prescaler diviSion and the timer clock selection. TIE (bit 4),and
PSC (bit 3) in the TCR are set to a logic 1 when in the
MOR controlled mode. TIM ;(bit 6) and TIR (bit 7) are
controlled by the counter and software. '

PSI

PSO

a

0

0

0

0

1.

2

0

I

0

4

I (Bypass Prescaler)

0

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

MOTOROLA MICROPROCESSOR DATA
3-575

Pr'escaler Division

PS2

II

MC68705P3

MASK OPTION REGISTER (MOR)

ClK

TOPT

CLS

P2

TIE

P1

PO

ClK -

II

~ Programming Latch Enable
Controls address and data being latched into the
EPROM. Set during reset, but may be cleared anytime.
1 =Read EPROM
0= latch address and data on EPROM
PGE'- Program Enable
Enables programming of EPROM. Must be set when
changing the address and data. Set during reset.
1 = Inhibit EPROM programming
O=Enable EPROM programming (if PlE is low)
VPON-Vpp On
A read-only bit that indicates high voltage at the Vpp
pin. When set to "1", disconnects PGE and PlE from
the chip.
1 = No high voltage on Vpp pin
0= High voltage on Vpp pin

PlE

The MOR is implemented in EPROM and contains all
zeros prior to' programming. This register is not affected
by reset. The MOR bits are described in the following
paragraphs.

Clock (oscillator type)
1 = Resistor Capacitor (RC)
0= Crystal
TOPT - Timer Option
1 = MC6805P2/P6 type timer/prescaler. All bits except 6 and 7 of the TCR are invisible to the user.
Bits 5, 2, 1, and 0 of the MOR determine the
equivalent MC6805P2/P6 mask options.
0= All TCR bits are implemented as a software programmable timer. The state of MOR bits 5, 4,
2, 1,' and 0 sets the initial values of their respective TCR bits.
ClS - Timer/Prescaler Clock Source
1 = External TIMER pin
0= Internal clock
TIE - Timer External Enable
Not used if TOPT = 1. Sets the initial value of TIE in
the TCR if TOPT = O.
1 = Not used
0= Sets initial value of TIE in the TCR
P2, P1, PO
The logical levels ofthese bits, when decoded,select
one of eight outputs on the timer prescaler.

NOTE
VPON being "0" does not indicate that the Vpp level
is correct for programming. It is used as a safety
interlock for the user in the normal operating mode.
VPON

PGE

PLE

Programming Conditions

0

0

0

Programming Mode (Program EPROM
Byte)

1

0

0

PGE and PLE Disabled from System

0

1

0

Programming Disabled (Latch Address
and Data in EPROM)

1

1

0

PGE and PLE Disabled from System

0

0

1

Invalid State; PGE=O if PLE=O

1

0

1

Invalid State: PGE =0 ifPLE = 0

P2

P1

PO

Prescaler Division

0

1

1

"High Voltage" on Vpp

0

0

0

,1 (Bypass Prescaler)

1

1

1

0

0

1

2

PGE and PLE Disabled from System
(Operating Mode)

0

1

0

4

0

1

1

8

1

0

0

16

EPROM PROGRAMMING

1

0

l'

32

PROGRAMMING

1

1

0

64

1

1

1

128

The MCU bootstrap program can be used to program
the MCU EPROM.
A 2764 UV EPROM must first be programmed with the
same information that is to be transferred to the MCU
EPROM. Refer to application note, MC68705P31R31U3
8-bit EPROM Microcomputer Programming Module
(AN-857 Rev 2) for a schematic diagram and instructions
on programming the MCU EPROM.

PROGRAMMING CONTROL REGISTER (PCR)
The PCR is an 8-bit register which provides the necessary control bits to program the EPROM. The bootstrap
program manipulates the PCR when programming, so
the user need not be concerned with PCR in most applications.

RESET:
U

u

u

u

u

EMULATION
The MC68705P3 emulates the MC6805P2 and MC6805P6
"exactly,!' The MC6805P2/P6 mask features are implemented in the mask..:option register (MOR) EPROM byte
on the MC68705P3. A few minor exceptions to the exactness of emulation are listed below:
1. The MC68705P2/P6 "future ROM" area is implemented in the MC68705P3, and these 704 bytes must

u

MOTOROLA MICROPROCESSOR DATA
3~576

MC68705P3

be left unprogrammed to accurately simulate the
MC6805P2/P6. The MC6805P2/P6 read all "Os" from
this area.

Function

2. The reserved ROM areas in the MC6805P2/P6 and
the MC68705P3 have different data stored in them.
This data is subject to change without notice. The
MC6805P2/P6 use the reserved ROM for the selfcheck feature, and the MC68705P3 uses this area for
the bootstrap program.
3. The MC6805P2/P6 read all"1s" in its 48-byte "future
RAM" area. This RAM is not implemented in the
MC6805P2/P6 mask ROM versions but is implemented in the MC68705P3.
4. The Vpp line (pin 6) in the MC68705P3 must be tied
to VCC for normal operation. In the MC6805P2/P6,
pin 6 is the NUM pin and is grounded in normal
operation.
5. The LVI feature is not available in the MC68705P3.
Processing differences are not presently compatible
with proper design of this feature in the EPROM
version.

SBC

AND Memory to A

AND

OR Memory with A

ORA

Exclusive OR Memory with A

EOR

Arithmetic Compare A with Memory

CMP

Arithmetic Compare X with Memory

CPX

Bit Test Memory with A (Logical Compare)

BIT

Jump Unconditional

JMP

Jump to Subroutine

JSR

READ-MODIFY -WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.
Function

The operation of all other circuitry has been exactly
duplicated or designed to function identically in both devices including interrupts, timer, data ports, and data direction registers (DDRs). A design goal has been to provide
the user with a safe, inexpensive way to verify a program
and system design before committing to a factory programmed ROM.

INSTRUCTION SET
The MCU has a set of 59 basic instructions which can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following list of instructions.

Mnemonic

Subtract Memory from A with Borrow

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Complement

COM

Negate (2's Complement)

NEG

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Logical Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list for branch instructions.
Function

Mnemonic

Mnemonic

Branch Always

BRA

Load A from Memory

LDA

Branch Never

BRN

Load X from Memory

LDX

Branch if Higher

BHI

Store A in Memory

STA

Branch if Lower or Same

BLS

Store X in Memory

STX

Branch if Carry Clear

Add Memory to A

ADD

(Branch if Higher or Same)

Function

..

Add Memory and Carry to A
Subtract Memory

-

ADC

Branch if Carry Set

SUB

(Branch if Lower)

BCC
(BHS)
BCS
(BLO)
-

-'- Continued -

MOTOROLA MICROPROCESSOR DATA
3-577

Continued-

II

MC68705P3

IMnemonic

Function

(BHS)

(Branch if Higher or Same)

II

code register. Refer to the following list for bit manipulation instructions.

Branch if Carry Set

BCS

(Branch if lower)

(BlO)

Branch if Not Equal

Bran~h if Equal

Function

Mnemonic

Branch if Bit n is Set

BRSET n (n=O ... 7)

BNE

Branch if Bit n is Clear

BRCLR n (n=O ... 7)

BEQ

Set Bit n

BSET n (n=O ... 7)

Branch if Half Carry Clear

BHCC

Clear Bit n

BClR n (n=O ... 7)

Branch if Half Carry Set

BHCS

Branch if Plus

BPl

Branch if Minus

BMI

Branch if Interrupt Mask Bit is Clear

BMC

Branch if Interrupt Mask Bit is Set

BMS

Branch if Interrupt Line isLow

Bil

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

OPCODE MAP SUMMARY

Table 2 is an opcode map for the instructions used on
the MCU.

ADDRESSING MODES

CONTROL INSTRUCTIONS

These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.
Function

Mnemonic

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

ClC

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

Reset Stack Pointer

RSP

No-Operation

NOP

The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code coversion tables, and scaling tables anywhere in the memory
space. Short indexed accesses are single byte instructions, while the longest instructions (three bytes) permit
accessing tables throughout memory. Short and long absolute addressing is also included. Two byte direct addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.
IMMEDIATE

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).
DIRECT

In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.
EXTENDED

BIT MANIPULATION INSTRUCTIONS

The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes ofthe memory space, where
all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 2.56 locations. The bit set, bit clear and bit test, and
branch functions are all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the carry bit of the condition

In the extended addressing mode,the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction.
RELATIVE

The relative addressing mode is only used in. branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.

MOTOROLA MICROPROCESSOR DATA
3-578

Table 2. Opcode Map

Bit Menipulation~rench
REL

BTB~SC

~L _~
10BRSETO
o
0000

1
0001

2
0010

3
0011

3:

o

a
~

w

'"
~

4
0100
5

Otol
6

0110

..Q!ll

3:

1000

o"'a

~
o
m

en
en

o~,

IX

o~o

INH

L----'I~l

I

W-w8RClR1
BTB

2

3

_BTB

I'

2

l

___

1
1

____

L- --- ]

6

RTI

6

___

6

r~
BCC
2 _

lSR J 4 lSRA 14 lSRX~~--LSR
LSR
2
QTR 1
INH 1
INH 2
IX 1 1
IX

REL

J------l
4

I

l

8ClR2 r~
BCS.
BSC2__
REL
- _____
ROR
RORA 14 RORX 17 ROR
ROR
D!1L 1
INH l_lNH 2
IXI 1
IX

1-

1O--~--)4
~
BRSET3
BSH3
BNE
13
BTB 2
Bse 2
REL 2

j

]6]

I

,~,

IMM

DIR

,:'0

EXT

I:',

2 -

IXl

IXI

,~,

,[00

IX

,["

,,~o

I~

1 SUB
14 SUB
15-~]~---]4
SUB
SUB
SUB
SUB
2
IMM 2
DIR 3
EXT 3
IX22
IXll
Ixl

INH

RTS
INH

1

Rlllilter/tMmorv

Control
I INH

-J

1 COM
111 SWI
8ClR1 -)4 BlS1 COM J4 COMA 14 COM X 17 COM
Bse 2
REL 2
Q!fI 1
U'ttiL_----.lNH 2
IXI 1
IX 1
INH

108RSET2 17 8SET2
13
BTB 2
Bse
10
8RClR2

L J

,~

-----]9

1'6

17 BSHO 14 BRA
1 NEG 1NEG
- 14 NEG -]7 NEG
• NEG
BTB 2
Bse 2
REL 2
DIR 1
INH 1
INH 2 - IXll
IX

10BRClRO 17 BClRO 14 BRN
13
BTB 2
Bse 2
REL
10BRSETl 17 BSH1 14 -BHI
3
_BTB 2
BSCL
REL _

b

Read-Modify-Write
INH
IXI

INH

12 CMP 14 CMP
15 CMP
1 CMP -- T5~-4
CMP
CMP
2
IMM 2
DIR 3
EXT 3
IX2 2
IXI I
IX
5
6
2
1 SBC
15 SBC
1 S8C
14 S8C
SBC
S8C
2
IMM 2
DIR 3
EXT 3
IX2.2
IX"
_.Ix
6

:r:

J
I

1

-1

5
12 AND 14 AND
1 AND
2
IMM 2
DIA 3
EXT

r

----=:J

2.. __..iMM

1
000'

2
00'0.

3

6

r r

BIT
14 BIT
BIT
2
DIR 3
EXT
14 lOA
15 lOA
_ lOA
__ lMM 2
DIA 3
EXT

1:2

I
I

0

0000

0011

t

5

AND

AND _\4 AND
IX2.2
IXI _.1
IX

r - 1'--- -r14
3

3

BIT
---I~BIT
IX2 2
IXI

lOA

3

IX2

2

lOA

IXI

1

BIT

J

I

lOA

1

I

IX

I

4
0'00
5
0101
6
0110

7
111

B

9
1001
A

1010
B
1011

C
UJl!L

o::0

1101

C

E

!t»

3

DIR

J" -I 4 o:x.
6

L_~o

7

~

n
::0

1

J,

o

lUQ.

F
1111

---I

6

]7 BClR4 ]4 BHCS ]6 ROl
[-4 ROlA ]4 ROlX-]7 ROL
1_ ROL
2
Bse 2
REL 2
DIR 1
INH 1
tNH 2
IX 1 1
IX I
6
I ~RSET5
BSH5 14
DEC
rD-;;A -114 DECX-----rr DEC
]6 D~
BTB 2
Bse 2
AEl 2
DIA 1
lNH 1
INH I 2
IX 1 1 '0'" IX I
10BRClR4

3

BTB

T'

-;;:--1

fOBRClR5

3

BTB

1:~RSEJ6

4

j

BMI
REL

I J
__

--]62

7 BSET6 14 BMC
IB_.2
..8S_C 2..
AEL

J'-]4

10BRClR6
-

BTB

2

BClR6
BSC

2

I3j~RsEw___s__Er_7_
1_4___
sse. 1

1~RClR7 .1

3

BTB

7

BClR7 114
2
esc 2

INC

6

DIA

BMS 1 TST
REL 2
DIR
Bil

AEL

I

~- T 6
AEL

I2

CLR

f4
1

r

1

)

I

_ _ _ _j __ .

I~CA

]6

14 INCX- 17 INC
INH I 1
INH 2
IXII

TSTA
INH

r

-1

14 CLRA
DIA 1
INH

1

4
1

I
r11 CLI INH 122 ORAlMM 142 ORAD1A 1I 5 ORAEXT 1 6 ORAIX2 1 52 ORAIXI 141 ORA IX I

INH

I 2 '"u

6

1

IX 1 1

AOC

--r- r r

INC

1

IX

SEI

INH

~--]

1-

1,

2

3

Inherent
Immediate
Direct
Extended
Relative
Bit Set/Clear
Bit Test and Branch
Indexed (No Offset I
Indexed, 1 Byte (S-Bit) Offset
Indexed. 2 Byte (16-Bit) Offset

3

ADO
ADO
ADD I~
ADD
ADD
~-T'~-2
DIR 3
EXT 3
IX2 2
IXI 1IX

- ADD
IMM

3
1 JMP
2

n"c INH

8

5

DIR

14 JMP 1 JMP 14 JMP
3
EXT 3
11<2 - 2
IXI
8

9

3
1 JMP
1

1,

-,6'

CLR

IX

9

1001
A
1010
B
1011

C

1100

o

lJJ!1

E

1110

F

1111

LEGEND

Abbreviations for Add ..... Modes
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IX1
IX2

IX

JSR
12 NOP
1 BSR
17 JSR
1 JSR
1 JSR~ JSR
1
INH 2
REL 2
DIR 3
EXT 3
_ IX21Xl
IX
6
12 lOX 14 LOX
15 lOX 1 lOX _ I 5 LOX
14 lOX
2
IMM 2
DIA 3
EXT 3
IXru
IXI 1
IX
5
6
5
12 TXA
1
1 srx - 1 srx 1 7 srx
STX
1 srx
1
INH
2
DIA 3
EXT 3
IX2 2
IXI 1
IX

TSrx 17 rST
j 6 TST
INH 2
IX 1 1

CLRX~;

3:

12 SEC
]2
1
INH 2

• of

c",~

MnemOniC
Bytes

j ,i., ~l
4

Opcode in Binary

~

1

IX_
"

Address Mode

(')

en
co
.....
c

Con
."
W

MC68705P3

Otherwise, control proceeds to the next instruction. The
span of relative addressing is from -126 to + 129 from
the opcode address.

the specified bit is to be set or cleared. Any read/write
bit in the first 256 locations of memory, including I/O, can
be selectively set or cleared with a single 2-byte instruction.

INDEX, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or to hold the address of a frequently referenced
RAM or 1/0 location.

II

CAUTION

INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the ef~
fective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this 2-byte instruction, K would typically be in X with the address of
the beginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1 FE is the last location at which the instruction may
begin).
INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the two unsigned bytes following
the opcode. This addressing mode can be used in a manner similar to indexed, 8-bit offset except that this 3-byte
instruction allows tables to be anywhere in memory.

BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte to which

The corresponding DDRs for ports A, S, and Care
write only registers (registers at $004, $005, and
$006). A read operation on these registers always
returns "1". Since BSET and BCLR are read-modifywrite functions, they cannot be used to set or clear
a DDR bit (all "unaffected" bits would be set). It is
recommended that all DDR bits in a port be written
using a single-store instruction.

BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear) is
included in the opcode. The address of the byte to be
tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third
byte is added to the PC if the specified bit is set or cleared
in the specified memory location. This single 3-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of
memory. The span of branching is from -125 to + 130
from the opcode address. The state of the tested bit is
also transferred to the carry bit of the condition code
register.
INHERENT
In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this mode. These instructions are one byte long.

MOTOROLA MICROPROCESSOR DATA
3-580

MC68705P3

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltages
EPROM Programming Voltage
(Vpp Pin)
TIMER Pin (Normal Mode)
TIMER Pin (Bootstrap
Programming Mode)
All Others
Operating Temperature Range
Storage Temperature Range

Symbol

Value

Unit

VCC

-0.3 to +7.0

V

Vpp
·Vin

- 0.3 to + 22.0
-0.3 to +7.0

V
V

Vin
Vin

- 0.3 to + 15.0
-0.3 to + 7.0

V
V

TL to TH
+70

°c

TA
Tstg

Junction Temperature
Cerdip

o to

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, normal precautions be taken to avoid application of any
voltage higher than maximum-rated voltages to this high-impedance circuit. For proper
operation, Vin and Vout should be constrained to the range VSS ,,;; (Vin or Vout) ,,;;
VCC. Reliability of operation is enhanced if
unused inputs except EXTAL are tied to an
appropriate logic voltage level (e.g., either
VSS or VCC)·

°c

-55 to + 150

°CIW

TJ

150

I

THERMAL CHARACTERISTICS
Characteristic

Symbol

Thermal Resistance
Cerdip

Unit

Value

°CIW

6JA
60

POWER CONSIDERATIONS
For most applications PI/OC)

Unit

V

VIH

21.0
VCC

V
22.0
5.75
j.lA

-

-

-

20

-

-

-4.0

-

20
50
10
-1600
-40

*Vpp is pin 6 on the MC68705P5 and is connected to VCC in the normal operating mode. In the MC6805P2, pin 6 is NUM and is
connected to VSS in the normal operating mode. The user must allow for this difference when emulating the MC6805P2 ROMbased MCU.
**Due to internal biasing, this input (when not used) floats to approximately 2.0 V.

MOTOROLA MICROPROCESSOR DATA
3-600

MC68705P5

PORT ELECTRICAL CHARACTERISTICS (VCC= +5.25 Vdc, :to.5 Vdc, VSS=O Vdc, TA=O° to 70°C,
unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

Port A
Output Low Voltage, ILoad = 1.6 rnA

VOL

-

-

0.4

V

Output High Voltage, ILoad = -100 f.lA

VOH

2.4

-

-

V

Output High Voltage, ILoad = -10 f.lA

VOH

VCC-1.0

-

-

V

Input High Voltage, ILoad = - 300 f.lA (Max)

VIH

2.0

-

Vec + 0.7

Input Low Voltage, ILoad = - 500 f.lA (Max)

VIL

VSS

-

0.8

V

Hi-Z State Input Current (Vin = 2.0 V to VCC)

IIH

-

-

- 300

f.lA

IlL

-

-

500

f.lA

Hi-Z State Input Current (Vin = 0.4 V)

V

PortS
Output Low Voltage, ILoad = 3.2 rnA

(VOL

-

-

0.4

Output Low Voltage, ILoad = 10 rnA (Sink)

VOL

-

-

1.0

V

Output High Voltage, ILoad = - 200 J.LA

VOH

2.4

-

-

V

Darlington Current Drive (Source), Vo = 1.5 V

IOH

-1.0

-

Input High Voltage

VIH

2.0

-

Input Low Voltage

VIL

VSS

-

0.8

V

-

2

20

f.lA

Hi-Z State Input Current

ITSI

V

10
Vec

+

0.7

rnA

-V

Port C

--

Output Low Voltage, ILoad = 1.6 rnA

VOL

-

-

0.4

V

Output High Voltage, ILoad = -100 f.lA

VOH

2.4

--

-

V

Input High Voltage

VIH

2.0

-

VCC . 0.7

V

Input Low Voltage

VIL

VSS

-

0.8

V

Hi-Z State Input Current

ITSI

2

20

I-lA

-

VCC=5.75V

Test

Point

MMD6150
or Equiv.

1. 25kO

-

VCC=575V

I

Point
30 pF IT olall

MMD7(XX)
or EqUiv.

Figure 10. TTL Equivalent Test Load
(Port B)

..

Test

TestPoint~

I

40 pF

lTotan

--

Figure 11. CMOS Equivalent Test Load
(Port A)

5V

Vee

Internal
Reset

Figure 13. Power and Reset Timing

MOTOROLA MICROPROCESSOR DATA
3-601

:I) pF
ITotal)

Figure 12. TTL Equivalent Test Load
(Ports A and C)

I

MC68705P5

Vcc

Port DDR
Port Data
IP = Input Protection

Figure 14. Port A Logic Diagram

I

Port DDR
Port Data
IP = Input Protection

Figure 15. Port Band C Logic Diagram

~ To 1/0 Logic

~

Figure 16. Typical Input Protection

V"V V,

Test po ,nt - : -

1

.

. Me,,"," I
±

V

Figure 17. 1/0 Characteristic
Measurement Circuit

ORDERING INFORMATION
The following table provides generic information pertaining to the package type, temperature, and MC order numbers
for the MC68705P5.

Table 3. Generic Information
Internal Clock
Frequency (MHz)

Temperature

Cerdip (S Suffix)

1.0

0° to 70°C

MC68705P5S

Cerdip (S Suffix)

1.0

-40° to 85°C

MC68705P5CS

Package Type

MOTOROLA MICROPROCESSOR DATA
3-602

Order Number

MC68705P5

MECHANICAL DATA

PIN ASSIGNMENTS

PA7
PA6

PA4
PA3

TIMER
PAl
PAD

I

MOTOROLA MICROPROCESSOR DATA
3-603

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC68705R3

Technical Summary

8-Bit EPROM Microcontroller Unit

I

The MC68705R3 (HMOS) Microcontroller Unit (MCU) is an EPROM member of the MC6805 Family
of microcontrollers. The user programmable EPROM allows program changes and lower volume
applications. This low cost MCU has parallel I/O capability with pins programmable as input or output. This publication contains condensed information on the MCU; for detailed information, refer to
M6805 HMOS, M146805 CMOS Family User's Manual (M6805UM(AD2)) or contact your local Motorola sales office.
Refer to the block diagram for the hardware features and to the list below for additional features
available on the MCU.
• Internal 8-Bit Timer with 7-Bit
• Vectored Interrupts
Programmable Prescaler
• Bootstrap Program in ROM
• On-chip Oscillator
• 112 Bytes of RAM
• Memory Mapped I/O
• 3776 ~ytes of Eprom
• Versatile Interrupt Handling
• 24 I/O Pins
• Bit Manipulation
• 4-Channel Analog-to-Digital
Converter
• Bit Test and Branch Instruction

BLOCK DIAGRAM

Accumulator
Port
A
I/O
lines

Data
Dir
Reg

1/0

Lines

X

8

P80
P81
P82
PB3
P84
PBS
PB6
P87

Data
Dir
Reg

COndition
Code
Register

CC

CPU

Stack
Pointer

4

S
Program
Counter
High PCH

8

Program
Counter
Low PCl

S
Port
B
Reg

CPU
Control

Index
Register

S

Port
8

A

8

POO/ANO
PDI/ANI
PD2/AN2 Port
D
PD3/AN3
PD4IVRl Input
lines
PD5IVRH
PD6/iNTi
PD7

ALU

PCO
PCI
PC2
PC3
PC4
PC5
PC6
PC7

x
Bootstrap
ROM

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-604

Port
C
1/0

Lines

MC68705R3

register setting) is connected to these pins to provide a
system clock.

SIGNAL DESCRIPTION
VCC AND VSS

RC Oscillator

Power is supplied to the microcontroller using these
two pins. Vee is + 5.25 volts (± O.5~) power, and VSS is
ground.

With this option, a resistor is connected to the oscillator
pins as shown in Figure 1. The relationship between -R
and fosc is shown in Figure 2.

Vpp

Crystal

This pin is used when programming the EPROM. -In
normal operation, this pin is connected to Vee.

The circuit shown in Figure 1 is recommended when
using a crystal. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. Refer to ELECTRICAL SPECIFICATIONS for Vee
specifications.

INT

This pin provides the capability for asynchronously applying an external interrupt to the MeU. Refer to INTERRUPTS for more detailed information.

External Clock

EXTAL,XTAL

An external clock should be applied to the EXTAL input
with the XTAL input connected to VSS, as shown in Figure 1. This option may only be _used with the crystal
oscillator option selected in the mask option register.

These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal (depending on mask option

C1

EXTAL_~_ ~XTAL

6

L1.

5

-

-~E---J

XTAL
MCU
(Crystal Option.
See Note 1)

6

AT - Cut Parallel Resonance Crystal
Co = 7 pF Max
Freq. = 4.0 MHz @ CL = 24 pF
RS = 50 ohms Max.

Crystal

Piezoelectric ceramic resonators which
have the equivalent specifications may be
used instead of crystal oscillators. Follow
ceramic resonator manufacturer's -suggestions for Co. C1. and RS values.

VCC

6 XTAL
5 EXTAL
External
Clock.
Input

MCU
(Crystal Option.
See Note 1)

External Clock

MCU
(RC Option.
See Note 1)

Approximately 25% to 50% Accuracy
Typical tCyc= 1.25"s
External Jumper

"EXTAL
No
Connection

MCU
(RC Option.
See Note 1)

Approximately 10% to 25% Accuracy
(Excludes Resistor Tolerance)
External Resistor

NOTES:
1. For the MC68705R3 MaR b7 = 0 for the crystal option and MaR b7 = 1 for the RC option. When the TIMER input pin is in the
VIHTP range (in the bootstrap EPROM programming mode), the crystal option is forced. When the TIMER input is at or below
VCC, the clock generator option is determined by bit 7 of the mask option register (ClK).
2. The recommended Cl value with a 4.0 MHz crystal· is 27 pF maximum, including system distributed capacitance. There is
an internal capacitance of approximately 25 pF on the XTAl pin. For crystal frequencies other than 4 MHz, the total capacitance
on each pin should be scaled as the inverse of the frequen~y ratio. For example, with a 2 MHz crystal, use approximately 50 pF
on EXTAl and approximately 25 pF on XTAL. The exact value depends on the motional-arm parameters of the crystal used.

Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR DATA
3-605

II

MC68705R3

8.0

PROGRAMMING

7.0
;;;

INPUT/OUTPUT PROGRAMMING

r 6.0
~

VCC=5.25 V
TA= 25°C

>

~ 5.0

!

:!I

40

~ 30

iii

2.0

0

1.0
0

0

10

20

80

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only
TIMER

II

This pin is used as an external input to control the
internal timer/counter circuitry. This pin also detects a
higher voltage level used to initiate the bootstrap program.
RESET

Ports A, 8, and C are programmable aseither input or
output under software control of the corresponding data
direction register (DDR). Port 0 lines are input only. The
port I/O programming is accomplished by writing the
corresponding bit in the port DDR to a logic one for output
and a logic zero for input. On reset, all the DDRs are
initialized to a logic zero state to put the ports in the input
mode. The port output registers are not initialized on
reset and should be written to before setting the DDR
bits.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
. is set to input,'Thisport write may be used to initialize
the data registers and avoid undefined outputs. Care must
be exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (zero) and, also, to the latched output
when the DDR is an output (one). Refer to Table 1 for 1/
o functions and to Figure 3 for typical port circuitry.

This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low.
INPUT/OUTPUT LINES (PAO·PA7, PBO·PB7, PCO·PC7, PD~·
PD7)
These 32 lines are arranged into four 8-bit ports (A, B,
C, and D). Ports A, B, and C are programmable as either
inputs or outputs under software control of the data direction registers. Port 0 is a fixed input port. It has up to
four analog inputs, plus two voltage reference inputs when
the analog-to.:f!!.gJtal converter is used (PD5NRH, PD4/
VRLl,and an INT2 input. Port D lines can be read directly
and used as binary inputs. If an analog input is used, then
the voltage reference pins must be used in the analog
mode. Refer to PROGRAMMING for additional information.

·DDR is

Table 1. I/O Pin Functions
Data
Direction
Register
Bit

Latched
Output
Data
Bit

Output
State

MCU

1
1
0

0
1
X

0
1
Hi-Z**

0
1
Pin

To

**Port Band C are three-state ports. Port A has an internal pullup devices to provide CMOS data drive capability.

Port 0 provides reference voltage and multiplexed analog inputs. The VRL and VRH lines are internally connected to the AID resistor. Port 0 can always be used as

a writ&-only register and reads as all "1s"

Figure 3. Typical Port I/O Circuitry and
Register Configuration

MOTOROLA MICROPROCESSOR DATA
3-606

Input

MC68705R3

REGISTERS

digital inputs, but for analog inputs, VRH and VRL must
be connected to the appropriate reference voltage.

The MCU contains the registers described in the following paragraphs.

NOTE

ACCUMULATOR (A)

Read-modify-write instructions should be. not used
. when writing to DDRs always read as 'one'.

The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.

MEMORY

7

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may be added to an 8-or 16- bit immediatevalueto create
an effective address. The index register may also be used
as a temporary storage area.
7

x
PROGRAM COUNTER (PC)

NOTE

The program counter is a 12-bit register that contains
the address of the next byte to be fetched.

Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

11

Timer
RAM
(128 Bytes)

$07F
$080

Page Zero
User EPROM
tE8!.yt~

_ _ \OFF
$100

User
Main
EPROM
(3640 Bytes)

3897
3967

3968
4(ll7
4(ll8
4(ll9

4090
Interrupt
Vectors

4091
4092
4093

4094
4095

1"'------Mask Option Register
Not Used
Bootstrap
ROM
(120 Bytes)
Timer Interrupt

$F37
$F38
$F39
$F7F
$F80
$FF7
$FF8

r-------

$FF9
$FFA

1"'------ro:..- -- - --

$FFB
$FFC

External Interrupt
SWI

Reset

0

PCl

76543210
$()()()

1/0 Ports

255 _ _
256

8 7

PCH

o

7

3895
3896

I

A

The MCU is capable of addressing 4096 bytes of memory and I/O registers. The memory map is shown in Figure
4. The locations consists of user EPROM, bootstrap ROM,
user RAM, a mask option register (MOR), a program control register, miscellaneous register, AID control registers, and I/O. The interrupt vectors are located from $FF8
to $FFF. The bootstrap is a mask-programmed ROM that
allows the MCU to program its own EPROM.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.

~E:I:

0

$FFD
$FFE
$FFF

0

Port A Data Register

$()()()

I

Port B Data Register

$001
$002

2

Port C Data Register

3

Port D Data Register

$003·

4

Port A DDR*

$004*

5

Port B DDR*

$005*

6

Port C DDR*

$006*

i

Not Used

$007

8

Timer Data Register

$008
$009

9

Timer Control Register

10

Miscellaneous Register

$OOA

11

Program Control Register

$OOB

12

Not Used

$OOC

13

Not Used

$OOD

14

AI D Control Register
, AI D Register

15
16

RAM
(112 Bytes)
Stack
(31 Bytes Maximum)

127

* Caution: Data direction registers (DDRs) .are write-only; they read -as $FF.

Figure 4. Memory Map

MOTOROLA MICROPROCESSOR DATA
3-607

$OOE
$OOF
$010

t

$07F

I

II

MC68705R3

STACK POINTER (SP)

POWER-ON-RESET (POR)

The stack pointer is a 12-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pe>inter
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
The seven most-significant bits of the stack pointer are
permanently set at 0000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to 15
levels of subroutine calls (less if interrupts are allowed).

An internal reset is generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power turn-on conditions and
should not be used to detect any drop in the power supply
voltatge. A delay of tRHL milliseconds is required before
allowing RESET input to go high. Connecting a capacitor
to the RESET input (Figure 5) typically provides sufficient
delay.

1

5 4

11
1 0 1 0 1 0 1 0 1 0 11

lisp

:r: 10 JLF

CONDITION CODE REGISTER (CC)

II

The condition code register is a 5-bit regiliter in which
four bits are used to indicate the results of the instruction
just executed. These Qits can be individually tested by a
program, and specific actions can be taken as a result of
their state. Each bit is explained in the following paragraphs.

(MCU)

Figure 5. Power-Up RESET Delay Circuit

EXTERNAL RESET INPUT
~MCU

Half Carry (H)

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

is reset when a logic zero is applied to the
RESET input for a period longer than one machine cycle
(tcyel. Under this type of reset, the Schmitt trigger switches
off at VIRES - to provide an internal reset voltage.

Interrupt (I)

When this bit is set, the timer and external interrupt is
masked (disabled). If an external interrupt occurs while
this bit is set, the interrupt is latched and is processed as
soon as the interrupt bit is cleared.
Negative (N)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative (bit
7 in the result is a logic 1).
Zero (Z)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.
Carry/Borrow (C)

When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occured during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and. during shifts and
rotates.

RESETS
The MCU can be reset two ways: by initial power-up
and by the external reset input (RESET). The RESET input
consists mainly of a Schmitt trigger that senses the line
logic level.

INTERRUPTS
The MCU can be interrupted four different ways: (1)
through the external interrupt INT input pin, (2) with the
internal timer interrupt request, (3) using the software
interrupt instruction (SWI), or (4) the external Port D (lNT2)
input pin.
Interrupts cause the processor registers to be saved on
the stack and the interrupt mask (I bit) set to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack after which
normal processing resumes. The stacking order is shown
in Figure _6_.__
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.
NOTE

The current instruction is considered to be the one
already fetched and being operated on.
When the current instruction is complete, the processor
checks all pending hardward interrupts and, if unmasked
(I bit clear), proceeds with interrupt processing; otherwise, the next instruction iffetched and executed. Masked
interrupts are latched for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.

MOTOROLA· MICROPROCESSOR DATA
3-608

MC68705R3

6

7

n-4

1

I

1

5

I

1

Accumulator

n-2

Index Register

1

1

I

1

I

1

I

1

n

I

n+1
n+2

PCH*

j

Pull

Condition Code Register

n-3
n"":1

o

3

4

I

n+3
n+4
n+5

PCl*

Push

* For subroutine calls, only PCH and PCl are stacked.

Figure 6. Interrupt Stacking Order

If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 7 for the reset and interrupt
instruction processing sequence.

Digital-Signal Interrupt

TIMER INTERRUPT

SOFTWARE INTERRUPT (SWI)

If the time mask bit (TCR6) is cleared, then, each time
the timer decrements to zero (transitions from $01 to $00)'
an interrupt request is generated. The actual processor
interrupt is generated only if the interrupt mask bit of the
condition code register (CCR) is also cleared. When the
interrupt is recognized, the current state of the machine
is pushed onto the stack and the I bit in the CCR is set,
masking further interrupts until the present one is serviced. The contents of the timer interrupt vector, containing the location of the timer interrupt service routine, is
then loaded into the program counter. At the end of the
timer interrupt service routine, the software normally executes an RTI instruction which restores the machine state
and starts executing the interrupted program. The timer
interrupt status bit can only be cleared by software.

The SWI is an executable instruction that is executed
regardless of the state olthe I bit in the CCR. The SWI
execution is similar to the hardware interrupts.

EXTERNAL INTERRUPT
The external interrupt is intern~ synchronized and
then latched on the falling edge of INT and INT2. Clearing
the I bit enables the external interrupt. The INT2 interrupt
has an interrupt request bit (bit7) and a mask bit (bit 6)
in the miscellaneous register (MR). The INT2 interrupt is
inhibited when the mask bit is set. The 'INT2 is always
read as a digital input on port D. The INT2 and timer
interrupt request bits, if set, cause the MCU to process
an interrupt when the condition code I bit is clear. The
following paragraphs describe two typical external interrupt circuits.
Zero-Crossing Interrupt

A sinusoidal input signal (fINT maximum) can be used
to generate an external interrupt (see Figure 8a) foruse
as a zero~crossing detector (for negative transitions of
the ac sinusoid). This type of circuit alloVl.(s applications
such as servicing,time~of-day routines and engaging/disengaging ac power control devices. Off-chip, full-wave
rectification provides aninterruptat every zerQcrossing
of the ac signal and, thereby, provides ,a ,2f clock.

With this type of circuit (Figure 8b), the INT pin can be
driven by a digital signal. The maximum frequency of a
signal that can be recognized by the TIMER or INT pin
logic is dependent on the parameter labeled tWL, tWH.
Refer to TIMER for additional information.

MODES OF OPERATION
The MCU has two modes of operations. These modes
are the normal and bootstrap. The following paragraphs
describe the modes.
NORMAL MODE

This mode is a single-chip mode and is entered if the
following conditions are met: (1) the RESET line is low,
(2) the pca pin is within its normal operational range,
and (3) the Vpp pin is connected to VCe. The next rising
edge of the RESET pin then causes the part to enter the
normal mode.
BOOTSTRAP

The bootstrap mode is entered if the TIMER pin= + 12
V. Refer to application note, MC68705P3/R3!U3 8-Bit
EPROM Microcomputer Programming Module (AN-857
Rev.2\.

TIMER
The MCU consists of an 8-bit software programmable
counter driven by a 7-bit software programmable prescaler. The various timer sources are m'ade via the timer
control register (TCR) and/or the mask optiOriregister
(MaR). The 8-bit courher may be loaded under program
control and is decremented toward zero; When the timer
reaches zero, the timer interrupt request b,it (bit 7) in the
timer control register (TCR) is set. Refer to Figure 9 for
timer block diagram.

MOTOROLA MICROPROCESSOR DATA

3·609

II

MC6,8705R3

1.1 (in CC)
07F. SP
O.DDRs

ClR INT logic
FF. Timer
TeR6.1
TCR7.0

Load PC From:
SWI: FFC/FFD
INT: FFA/FFB
Timer or
iiiiT2: FFS/FF9

II

Load OPtions From
MOR'($F3B1 Into
Control Logic

Figure 7; Reset and Interrupt Processing Flowchart

(a) Zero-Crossing Interrupt

(b) Digital-Signal Interrupt
VCC

Inapc
ut
(tiNT

TTL

(Current

Max.)~'ml.tJn91.
.

.2

Rsl MO

ac Inputs
10 Vac p-p

R

iiiff

4.7 k

Level

2

Dlgltal--..........:~

Mel!

Input

0.1-1.0
I'F

iNT
Meu

Figure 8. Typical Interrupt Circuits
The timer interrupt can be masked (disabled) by setting
the timer interrupt' mask bit (bit 6) in the TCR. When the
I bit in theconpition code regi~ter iS,cleared ar;ld the TCR
bit 6 is cleared; the processor receives the interrupt. The
MCU responds to this interrupt by (1) saving the present
CPU state on the stack, (2) fetching the timer interrupt
vector, and (3) executing the interrupt routine. The tilTler

interrupt request bit must be cleared by software. Refer
to RESETS andlNTERRUPTSfbr additional information.
The prescaleris a 7-bii divider which is used to extend
the maximum length pf the timer. To avoid truncation
errors, the prescaleris cleared when TCR bit 3 is set to
alo~ic one; however, the TCR bit 3 always reads as a
logic zero to ensure proper operation with read-modify.,
write instructions.

MOTOROLA MICROPROCESSOR DATA
3-610

8

fCIN

Timer Data Register (TOR)
8-Bit Counter

s:

0
-4
0
::a
0

!j;

W

~I
::a

~ 0
.....
..... "g

7-Bit Prescaler

0

s:

Timer Control Register (TCR)

m

In'ternal
';2
Clock
(fosc+ 4 )

fplN - Prescaler Input Frequency
fCIN- Counter Input Frequency

!
o

U'I

Clear

(')

e

Select

1-_ _ _ _ _ _ _-I1 1-of -8

::a

~I

Set

Timer
Pin

~

3

Timer Control Register Bits:
TIR - Timer Interrupt Request Status
TIM - Timer Interrupt Mask
TIN - Timer Input Select
TIE - Timer External Input Enable
PSC- Prescaler Clear
PS2, PS1, PSO- Prescaler Select

Mask Option Register Bits:
ClK - Clock Oscillator Type
TOPT - Timer Mask/Programmable Option
CLS - Timer Clock Source
P2, P1, PO- Prescaler Option

NOTE: The TOPT bit in the mask option register selects whether the timer ~s software programmable via the timer control register or
emulates the mask programmable parts via the MOR EPROM byte,

Figure 9. Timer Block Diagram

MC68705R3

The timer continues to count past zero, falling from $00
through $FF, and continues the countdown. The counter
can be read at any time by reading the timer data register
(TDR). This allows a program to determine the length of
time since a timer interrupt has occurred without disturbing the counting process. The TDR is unaffected by
reset.
SOFTWARE CONTROLLED MODE
This mode is selected when TOPT (bit 6) in the MOR
is programmed to zero. The timer prescaler input can be
configured for three different operating modes plus a
disable mode, depending on the value written to TCR
control bits 4 and 5 (TIE and TIN). The following paragraphs describe the different modes.

When TOPT= 1, the TCR emulates the MC6805R2; when
TOPT = 0, the TCR is controlled by software.
TGR with MOR TOPT = I
7

4

5

PSG

TGR with MOR TOPT=O
7
6
5
TlR I TIM
IRESET:
0

TIN

TIE

U

U

PSG

PS2

PSI

PSO

U

U

·U

*The value of corresponding bits in MOR is written during RESET
rising edge. These bits always read "one",

Timer Input Mode 1

II

6

I TlR I TIM I

When TIE and TIN are both programmed to zero, the
timer input is from the internal clock (phase two) and the
timer input pin is disabled: The internal clock mode can
be used for periodic interrupt generation as well as a
reference for frequency and event measurement.
Timer Input Mode 2
When TIE = 1 and TIN = 0, the internal clock and the
timer input signals are ANDed to form the timer input.
This mode can be used to measure external pulse widths.
The active high, external pulse gates in the internal clock
for the duration of the external pulse. The accuracy of
the count is ± 1.
Timer Input Mode 3

°

When TIE = and TIN'= 1, no prescaler input frequency
is applied to the prescaler and the timer is disabled.
Timer Input Mode 4
When TIE and TIN are both one, the timer input is from
the external clock: The external clock can be used to count
external events as well as to provide an external frequency for generating periodic interrupts. Frequency of
external input must be ,,;:; fasc/8.
MOR CONTROLLED MODE
This mode is selected when TOPT (bit 6) in the MOR
is programmed to logic one. The timer circuits are the
same as described in SOFTWARE CONTROLLED MODE.
The logic levels of TCR bits 0, 1, 2; and 5 are determined
during EPROM programming by the same bits in the MOR.
Therefore, bits 0,1,2, and 5 in theMOR control the prescaler division and the timer clock selection. TIE (bit 4) and,
PSC (bit 3) in the TCR are set to a logic one when in the
MOR controlled mode. TIM (bit 6) and TIR (bit 7) ate
controlled by the counter and software.

TIR - Timer Interrupt Request
Used to indicate the timer interrupt when it is logic
one
1 = Set when the timer data register changes to all
zeros
0= Cleared by external reset, power-on reset, or
under program control
TIM - Timer Interrupt Mask
Used to inhibit the timer interrupt
1 = Interrupt inhibited
0= Interrupt enabled
TIN - External or Internal
Selects input clock source
1 = External clock selected
0= internal clock selected (fosc/4)
TIE - TIMER External Enable
Used to enable external TIMER pin. When TOPT= 1,
TIE is always a logical "one".
1 = Enables external timer pin
0= Disables external timer pin
PSC - Prescaler Clear
Write only bit. Writing a one to this bit resets the
prescaler to zero. A read of this location always indicates a zero when TOPT=O. When TOPT=1, this
bit will read a logical "one" and has no effect on the
prescaler.
PS2, PS1, PSO - Prescaler Clear
Decoded to select one of eight outputs of the prescaler
Prescaler

PS2

PS1

PSG

0

0

0

1

0
0
0

0

1

2

1

0

4

1

1

8

1

0
0

0

16

1

I

32

1

1

0

64

1

1

1

128

TIMER CONTROL REGISTER ITCR) $009

Divide By

NOTES

This is an 8-bit register that controls various functions
such as configuring operation mode, setting ratio of the
prescaler, and generating timer interrupt request signal.
All bits are read/write except bit 3. The configuration of
the TCR is determined by the TOPT (bit 6) in the MOR.

When changing the PS bits in software, the PSC
bit should be written to a "one" in the same write
cycle to clear the prescaler. Changing the PS bits
without clearing the prescaler may cause prescaler
truncation.

MOTOROLA MICROPROCESSOR 'DATA
3-612

MC68705R3

MASK OPTION REGISTER (MOR) $F38
The MOR is implemented in EPROM. This register contains all zeros prior to programming and is not affected
by reset. The MOR bits are described in the following
paragraphs.
7

6

5

I CLK I TOPT I

CLS

I

P2

Pl

PO

ClK -

Clock (oscillator type)
1 = Resistor Capacitor (RC)
0= Crystal
TOPT - Timer Option
1 = MC6805R2 type timer/prescaler. All bits except
6 and 7, of the TCR are invisible to the user.
Bits 5, 2, 1, and 0 of the MOR determine the
equivalent MC6805R2 mask options.
0= All TCR bits are implemented as a software programmable timer. The state of MOR bits 5, 4,
2, 1, and 0 sets the initial values of their respective TCR bits.
ClS ---.: Timer/Prescaler Clock Source
1 = External TIMER pin
0= Internal clock
Bit 4
Not used if TOPT = I. Sets the initial value of TIE in
the TCR if TOPT = O.
1 = Not used
0= Sets initial value of TIE in the TCR
Bit 3
Not used
P2, Pl, PO
The logical levels of these bits, when decoded, select
one of eight outputs on the timer prescaler.
Prescaler
P2

P1

PO

0

0

0

1

0

0

1

2

0

1

0

4

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

PROGRAMMING CONTROL REGISTER (PCR) $008
The PCR is an 8-bit register which provides the necessary control bits to program the EPROM. The bootstrap
program manipulates the PCR when programming so the
user need not be concerned with PCR in most applications.
7

U

u

u

m

NOTE
VPON being "zero" does not indicate that the Vpp
level is correct for programming. It is used as. a
safety interlock for the user in the normal operating
mode.
VPON

PGE

PLE

Programming Conditions

0

0

0

Programming mode (program
EPROM byte)

1

0

0

PGE and PLE disabled from
system

0

1

0

Programming disabled (latch
address and data in EPROM)

1

1

0

PGE and PLE disabled from
system

0

0

1

Invalid state; PGE = 0 if PLE

1

0

1

Invalid state; PGE = 0 if PLE = 0

0

1

1

"High voltage" on Vpp

1

1

1

PGE and PLE disabled from
system (operating mode)

~c

0

Divide By

0

RESET:

1 = Read EPROM
0= latch address and data on EPROM
PGE - Program Enable
Enables programming of EPROM. Must be set when
changing the address and data. Set during reset.
_
1 = Inhibit EPROM programming
_ _ O=Enable EPROM programming (if PlE is low)
VPON - Vpp On
A read-only bit that indicates high volta.illUlt the
pin. When set to "one", disconnects PGE and PlE
from the chip.·
.
1 = No high voltage on Vpp pin
0= High voltage on Vpp pin

u

u

u

PlE - Programming Latch Enable
Controls address and data being latched into the
EPROM. Set during reset, but may be cleared anytime.

EPROM PROGRAMMING
ERASING THE EPROM
The EPROM can be erased by exposure to high-intensity ultraviolet (UV) light with a wavelength of 2537 angstroms. The recommended integrated dose (UV intensity
x exposure time) is 25Ws/cm 2 . The lamps should be
used without software filters, and the MCU should be
positioned about one inch from the UV tubes. Ultraviolet
erasure clears all bits of the MCU EPROM to the "zero"
state. Data then can be entered by programming "ones"
into the desired bit locations.

PROGRAMMING
The MCU bootstrap program can be used to program
the MCU EPROM. The alternate vectoring used toimplement the self-check is used to start execution of the bootstrap program.
A MCM2532 UV EPROM (other industry standard
EPROMs may be used) must first be programmed with
the same information that is to be transferred to the MCU
EPROM. Refer to application note, MC68705P31R31U3 B-bit
EPROM Microcomputer Programming Module (AN-857

MOTOROLA MICROPROCESSOR DATA

3-613

II

MC68705R3

is sampled again; and a new conversion begins, When
ACR7 is cleared, the conversion in progress is aborted
and the selected input, which is held internally, is sampled for five machine cycles.
The converter uses VRH and VRL as reference voltages.
An input voltage equal to or greater than VRH converts
to $FF. An input voltage equal to or less than VRL, but
greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded. Each analog input
source should use VRH as the supply voltage and should
be referenced to VRL for the ratiometric conversion. To
maintain full accuracy of the AID, three requirements
should be followed: (1) VRH should be equal to or less
than VCC, (2) VRL should be equal to or greater than VSS
but less than maximum specifications, and (3) VRH - VRL
should be equal to or greater than 4 volts.
The AID has a built-in 1/2 LSB offset intended to reduce
the magnitude ofthe quantizing error to ± 112 LSB, rather
than + 0, -1 LSB with no offset. This implies that, ignoring errors, the transition point from $00 to $01 occurs
at 112 LSB above VRL. Similarly, the transition from $FE
to $FF occurs 1-112 LSB below VRH, ideally.

Rev.2) for schematic diagrams and· instructions on programming the M.CU EPROM.

ANALOG-TO-DIGITAL CONVERTER

II

The chip resident 8-bit analog-to-digital (AID) converter
uses a successive approximation technique as show in
Figure 10. Four external analog inputs can be connected
to the AID via Port D. Four internal analog channels (VRH VRL, VRH - VRL/2, VRH - VRL/4, and VRLl may be selected for calibration. The accuracy ofthese internal channels may not meet the accuracy specifications of the
external channels.
Multiplexer selection is controlled by the AID control
register (ACR) bits 0, 1, and 2. Refer to Table 2 for multiplexer selection. The ACR is shown in Figure 10. The
converter uses 30 machine cycles to complete a <;:onversion of a sampled analog input. When the conversion is
complete, the digital value is placed in the AID result
register (ARR); the conversion flag is set; selected input

Table 2. AID Input MUX Selection

AID Control Register

Input Selected

ACR2

ACR1

ACRO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

ANO
AN1
AN2
AN3
VRH*
VRl*
VRH/4*
VRH/2*

AID Output (Hex)
Min

Typ

Max

FE
00
3F
7F

FF
00
40
80

FF
01
41
81

*Internal (calibration) levels

D/A
Control
15 kO lTypl

PDQ/ANO
PD1/AN1
PD2/AN2

logic

Count

1-of-8
Select
Multiplexer

PD3/AN3

8
A/D

A/D
Result
'-"'&"_'-"&"'--I~"""--I~"""""'" Register

Figure 10. AID Block Diagram

MOTOROLA MICROPROCESSOR DATA

3-614

MC68705R3

INSTRUCTION SET
The MCU has a set of 59 basic instructions which can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the accumulator or the index register. The
other operand ,is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following instruction list.
Function

Mnemonic

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (lST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.
Function

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Complement

COM

Negate (2's Complement;

NEG

Rotate Left Thru Carry

ROL

LOA

Rotate Right Thru Carry

ROR

Load X from Memory

LOX

Logical Shift Left

LSL

Store A in Memory

STA

Logical Shift Right

LSR

Load A from Memory

Store·X in Memory

STX

Arithmetic Shift Right

ASR

Add Memory to A

ADD

Test for Negative or Zero

TST

Add Memory and Carry toA

ADC

Subtract Memory

"

SUB

Subtract Memory from A with Borrow

SBC

AND Memory to A

AND

OR Memory with A

. ORA

Exclusive OR Memory with A
Arithmetic;

Comp~re.A

EOR

with Memory

CMP

Arithmetic Compare X with Memory

CPX

Bit Test Memory with A (Logical Compare)

BIT

Jump Unconditional
Jump to Subroutine

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refertothe following list for branch instructions.
Function

JMP
JSR

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of settin.g or clearing any bit which
resides in the first 256 bytes of the memory space where
all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit vyithin
these 256 locations. The bit set, bit clear and bit test, and
branch functions are' all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the carry bit of the condition
code register. Refer to the following listforbit manipulation instructions.
.
Function

BRSET n (n=O ... 7)

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BlS

Branch if Carry Clear
(Branch if Higher or Same)
Branch if Carry Set
(Branch if lower)

BCC
(BHS)
BCS
(BlO)

Branch if Not Equal

BNE

Branch if Equal

BEQ

Branch if Half Carry Clear

BHCC

Branch if Half Carry Set

BHCS

Branch if Plus

BPl

Branch if Minus

BMI

Branch if Interrupt Mask Bit is Clear

Mnemonic

Branch if Bit n is Set

Mnemonic

Branch Always

Branch if Interrupt Mask Bit is Set

BMC
.BMS

Branch if Bitn is Clear

BRCLR n (n=O ... 7)

Branch if Interrupt Line is low

Bil

Set Bit n

BSET n (n=O ... 7)

Branch if Interrupt Line is High

BIH

Clear Bit n

BCLR n (n=O ... 7)

Branch to Subroutine

B5R

MOTOROLA MICROPROCESSOR DATA
3-615

II

MC68705R3

EXTENDED
In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction.

CONTROL INSTRUCTIONS
These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.
Function

II

Mnemonic

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

CLC

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

eLi

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

Reset Stack Pointer

RSP

No-Operation

NOP

RELATIVE
The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from -126 to + 129 from
the opcode address.
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or to hold the address of a frequently referenced
RAM or liD location.

OPCODE MAP SUMMARY
Table 3 is an opcode map for the instructions used on
the MCU.

INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
the beginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1 FE is the last location at which the instruction may
begin).

ADDRESSING MODES
The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte
instructions, while the longest instructions (three bytes)
permit accessing tables throughout memory. Short and
long absolute addressing is also included. Two byte directaddressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents ofthe unsigned
8-bit index register and the two unsigned bytes following
the opcode. This addressing mode can be used ina manner similar to indexed, 8-bit offset except that this threebyte instruction allows tables to be anywhere in memory.

IMMEDIATE
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution. (e.g., a
constant used to initialize a loop counter):

BIT SETICLEAR
In the bit set/clear addressing mode, the bit to beset
or cleared is part of thecopcode. The byte following the
opcodespecifies the direct addressing of the byte to which
the specified bit is to be set or cleared. Any read/w~ite
bit in the first 256 locations of memory, including liD, can
be selectively set or cleared with a single two-byte instruction.

DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.

BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing; The
bit to be tested, and its condition (set or clear), is included
in the opcode. The address of the byte to be tested is in

MOTOROLA MICROPROCESSOR DATA

3·616

Table 3. Opcode Map

Bit Manipulation
BTB
BSC

1
0001

2
0010

s:

a
::a

o

~

s:

c;
::a
Q, o
....
"'a
.....
Co\)

g
m

(I)
(I)

o

3
0011

I

10
BRCLRO
3
.BTB

r
- 1

3

8TB

. ..8SC

1

o~

NEG

2

DIA

1"'--NEG1
INH

1

INH

2

iL

13

2

BSET3

2

RE.L

-.

o{"

~6•

NEG

10

BRCLR4
8TB

A

-1lllil

3

BTB

B

C

::a

l1 0=_> wZ

« « « (/)

PA5
PA4
PA3

PA3
PA2

XTAL

PAl
PAO

PAl

PB7

PBO
PB7
PB6
PB5
PB4
PB3
PB2

TIMER
PCO

PA2

PCl
PB4
PB3
PB2
PBl

PBl

PBO

Vpp

34

PC4

PC5
NC

29

POO/ANO
POllANl
P02/AN2

MOTOROLA MICROPROCESSOR DATA
3-623

PCl
PC2
PC3

PC6

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC68705R5

Technical Summary

8-Bit EPROM Microcontroller Unit
. The MC68705R5 (HMOS) Microcontroller Unit (MCU) is an EPROM member of the MC6805 Family
of microcontrollers. The user programmable EPROM allows program changes and lower volume
applications. This low cost MCU has parallel I/O capability with pins programmable as input or output. This publication contains condensed information on the MCU; for detailed information, refer to
M6805 HMOS, M146805 CMOS Family User's Manual (M6805UM(AD2)) or contact your local Motorola sales office.
Refer to the block diagram for the hardware features and to the list below for-additional features
available on the MCU.

I

•

Internal 8-Bit Timer with 7-Bit
Programmable Prescaler

•
•
•

On-chip Oscillator
Memory Mapped I/O
Versatile Interrupt Handling

•
•
•

Bit Manipulation
Bit Test and Branch Instruction
Vectored Interrupts

•
•
•

Bootstrap program in ROM
112 Bytes of RAM
3776 Bytes of Eprom

•
•

241/0 Pins
4-Channel Analog-to-Digital
Converter

•

EPROM Security Feature

BLOCK DIAGRAM

Accumulator
Port
A
110
lines

Data
Oir
Reg

8

A

POO/ANO
PDl/AN1
PD2/AN2 Port
D
PD3/AN3
PD4IVRL Input
Lines
PD5IVRH
PD6IiNi'2
P07

X
Condillon
Code
Register

Port
B
1/0
lines

CPU
Control

Index
Register

PBO
PBI
PB2
PB3
P84
PB5
PB6
PB7

5
Port
B
Reg

. Stack
Pointer

CC

CPU

S

Program
Counter
HIgh PCH

Data
O,r
Reg

8

ALU

Program
Counter
Low
PCL

PCO
PCI
PC2
PC3
PC4
PC5
PC6
PC7

x
Bootstrap
ROM

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA

3·624

Port
C
1/0
Lines

MC68705R5.

8.0

SIGNAL DESCRIPTION

r----..-----------------,

70

~~, 60.

VCC AND VSS
Power. is supplied to the· microcontroller using these
two pins. Vee is + 5.25 volts ( ± 0.5.:1) power, and VSS is
ground.

VCC=525V
TA=25°C

>

Vpp
This pin is used when programming the EPROM. In
normal operation, this pin is connected to Vee.

~

50

!

40

~

30

u

20

o

1.0

INT

10

This pin provides the capability for asynchronously applying an external interrupt to the MeU. Refer to INTERRUPTS for more detailed information.

40
50
30
ReSistance Ik{l)

20

60

70

80

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only
Crystal
The circuit shown in Figure 1 is recommended when
using a crystal. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. Refer
to ELECTRICAL SPECIFICATIONS for Vee specifications.

EXTAL,XTAL
These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal (depending on mask option
register setting) is connected to these pins to provide a
system clock.

External Clock
An external clock should be applied to the EXTAL input
with the XTAL input connected to VSS, as shown in Figure1. This option may only be used with the crystal
oscillator option selected in the mask option register.

RC Oscillator
With this option, a resistor is connected to the oscillator
pins as shown in Figure 1. The relationship between R
and fosc is shown in Figure 2.
C1

C tr

EXTAL·
5

AT -

1
.

.

.

S

.

Co

XTAL

XTAL
6

I See Note 21 c:::J

MCU
EXTAL (Crystal Option.
See Note 1)

Cut Parallel Resonance CryStal

Co =7 pF Max
Freq = 4.0 MHz @ CL = 24 pF
RS=50 ohms Max.
Piezoelectric ceramic resonators which
have the equivalent specifications may be
used instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO. C1. and RS values

VCC
......"AA,-~

XTAL
XTAL
External
ClOCK
Input

EXT AL

MCU
(Crystal Option.
See Note 1)

External Clock

EXTAL

XT AL
EXTAL

MCU
(RC Option.
See Note 1)

Approximately 25% to 50% Accuracy
Typicalt cyc = 1.25/"s
External Jumper

No
Connection

MCU
(RC Option.
See Note 1)

ApprOXimately 10% to 25% Accuracy
(Excludes Resistor Tolerance)
External ReSistor

NOTES:
1. For the MC68705R5 MaR b7 = 0 for the crystal option and MaR b7 = 1 for the RC option. When the TIMER input pin is in the
VIHTP range (in the bootstrap EPROM programming mode), the crystal option is forced. When the TIMER input is at or below
VCC, the clock generator option is determined by bit 7 of the Mask Option Register (ClK).
2. The recommended Cl value with a 4.0 MHz crystal is 27 pF maximum, including system distributed capacitance. There is an
'nternal capacitance of approximately 25 pF on the XTAl pin. For crystal frequencies other than 4 MHz, the total capacitance on
each pin should be scaled as the inverse of the frequency ratio. For example, with a 2 MHz crystal, use approximately 50 pF on
EXTAl and approximately 25 pF on XTAL. The exactvalue depends 011 the Motional-Arm parameters of the crystal used.

Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR DATA
3-625

II

MC68705R5

TIMER
This pin is used as an external input to control the
internal timer/counter circuitry. This pin also detects a
higher voltage level used to initiate the bootstrap program.
RESET
This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low.

II

INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO-PC7,
PDO-PD7)
These 32 lines are arranged into four 8-bit ports (A, B,
C, and D). Ports A, B, and C are programmable as either
inputs or outputs under software control of the data direction registers. Port D is a fixed input port. It has up to
four analog inputs, plus two voltage reference inputs when
the analog-to~tal converter is used (PD5IVRH, PD4/
VRLl, and an INT2 input. Port D lines can be read directly
and used as binary Inputs. If an analog input is used, then
the voitage reference pins must be used in the analog
for additional informamode. Refer to PROGRAMMING
tion.

.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
Ports A, B, and C are programmable as either input or
output under software control of the corresponding data
direction register (DDR). Port D lines are input only. The
port I/O programming is accomplished by writing the
corresponding bit in the port DDR to logic one for output
and a logic zero for input. On reset, all the DDRs are
initialized to a logic zero state to put the ports in the input
mode. The port output registers;:lre' not initialized on
reset and should be written to before setting the DDR
bits.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output

data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Care must
be exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (zero) and, also, to the latched output
when the DDR is an output (one). See Table 1 for I/O
functions and to Figure 3 for typical port circuitry.
Port D provides reference voltage and multiplexed analog inputs. The VRL and VRH lines are internally connected to the AID resistor. Port D can always be used as
digital inputs, but for analog inputs, VRH and VRL must
be connected to the appropriate reference voltage.
NOTE
Read-modify-write instructions should not be used
when writing to the DDR because DDRs always read
as 'one'.

Table 1. I/O Pin Functions
Data
Direction
Register
Bit

Latched
Output
Data
Bit

1
1
0

0
1

0
1
Hi-Z**

Input
To

MCU
0
1
Pin

**Port Band C are three-state ports. Port A has an-internal pullup
devices to provide CMOS data drive capability.

MEMORY

a

The MCU is capable of addressing 4096 bytes of memory and I/O registers. The memory map is shown in Figure
4. The location consist of user EPROM, bootstrap ROM,
user RAM, a mask option register (MOR), a program control register, miscellaneous register, AID control registers, and I/O. The interrupt vectors are located from $FF8
to $FFF. The bootstrap is a mask-programmed ROM that
allows the MCU to program its own EPROM.

Internal
Connections

Figure 3. Typical Port I/O Circuitry and
Register Configuration

MOTOROLA MICROPROCESSOR DATA
3..;626

X

Output
State

MC68705R5

P,g,Z~o

Access With
Short
Instructions

I

o

000

127
128

255
256

7654321
$000

I/O Ports
Timer
RAM
(128 Bytes)

$07F
$080

Page Zero
User EPROM
(128 Bytes)

-------

\OFF
$100

User
Main
EPROM
(3640 Bytesl

3895
3896
3897
3967

1-------Mask Option Register
Not Used
Bootstrap
ROM
(120 Bytes)

3968
4087

4088
4089

4090
Interrupt
Vectors

$FF7
$FF8

Timer Interrupt

------- -- --

$FF9
$FFA

-- -

$FFD
SFFE
$FFF

External Interrupt
4091
4092 ~SWI
4093

4094
4095

$F37
$F38
$F39
$F7F
$F80

1---

Reset

--

$000

0

Port A Data Register

1

Port B Data Register

$001

2

Port C Data Register

$002

3

Port D Data Register

$003

4

PortA DDR*

$004*

5

Port B DDR*

$005*

6

Port C DDR*

7

Not Used

$006*
$007

8

Timer Data Register

$008

9

Timer Control Register

$009

10

Miscellaneous Register

$OOA

11

Program Control Register

$OOB

12

Not Used

$OOC

13

Not Used

$OOD

14

AID Control Register

$OOE

15

A/D Register

16

RAM
(112 Bytes)

$OOF
$010

$FFB
$FFC

II

Stack
(31 Bytes Maximum)

t

127

$07F

* Caution: Data direction registers (DDRs) are write-only; they read as $FF.

Figure 4. Memory Map

The stack area is used during processing of an interrupt
or subroutine cal.1 to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.
NOTE
Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

an effective address. The index register may also be used
as a temporary storage area.
7

x
PROGRAM COUNTER (PC)
The program counter is an 12-bit register that contains
the address of the next byte to be fetched.
11

8 7

PCH

I

PCl

L - - - - - ' - -_ _ _ ~

REGISTERS
The MCU contains the registers described in the following paragraphs.
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.
7

A

INDEX REGISTER (X)

STACK POINTER (SP)
The stack pointer is an 12-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
The seven most-significant bits of the stack pointer are
permanently set at 0000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to 15
levels of subroutine calls (less if interrupts are allowed).

The index register i~ an8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may be added to an 8- or 16- bit immediate value to create

11

MOTOROLA MICROPROCESSOR DATA'
3-627

5 4

0
SP

I

MC68705R5

-

CONDITION CODE REGISTER (CC)

1

The condition code register is a 5-bit register in which
four bits are used to indicate the results Of the instruction
just executed. These bits can be individually tested by a
program, and specific actions can be taken as a result of
their state. Each bit is explained in the following paragraphs.

vCC - " ' V V ' l . - - - + - - - ,

:r: 10 IJ.F

(MCU)

Figure 5. Power-Up RESET Delay Circuit
Half Carry (H)

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)

I

When this bit is set, the timer and external interrupt is
masked (disabled). If an external interrupt occurs while
this bit is set, the interrupt is latched and is processed as
soon as the interrupt bit is cleared.
Negative (N)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative (bit
7 in the result is a logic 1).
Zero (Z)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.

INTERRUPTS
The MCU can be interrupted four different ways: (1)
through the external interrupt INT input pin, (2) with the
internal timer interrupt request, (3) using the software
interrupt instruction (SWI), or (4) the external Port 0 (lNT2)
input pin.
Interrupts cause the processor registers to be saved on
the stack and the interrupt mask (I bit) set to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack after which
normal processing resumes. The stacking order is shown
in Figure 6.
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.
7 ~

Carry/Borrow (C)

n-4

When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occured during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and during shifts and
rotates.

I

4

3 2 1 0
Condition
Code Register n+1

n-3

Accumulator

n+2

n-2

Inde. Register

n+3

1 11 11 1
n

RESETS

5

11 1

I
PCl-

PCH-

Pull

n+4
n+5

Push
• For subroutine calls. only PCH and PCl are stacked.

The MCU can be reset two ways: by initial power-up
and by theexternal reset input (RESET). The RESET input
consists mainly of a Schmitt trigger that senses the reset
line logic level.
POWER-ON-RESET (POR)

An internal reset is generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power turn-on conditions and
should not be used to detect any drop in the power supply
voltage. A delay of tRHL milliseconds is required before
allowing RESET input to go high. Connecting a capacitor
to the RESET input (Figure 5) typically provides sufficient
delay.
EXTERNAL RESET INPUT

The MCU is reset when a logic zero is applied to the
RESET input for a period longer than one machine cycle
(tcyel. Under this type of reset, the Schmitt trigger switches
off at VIRES - to provide an internal reset voltage.

Figure 6. Interrupt Stacking Order

NOTE
The current instruction is considered to be the one
already fetched and being operated on.

When the current instruction is complete, the processor
checks all pending hardward interrupts and, if unmasked
(I bit clear), proceeds with interrupt processing; otherwise, the next instruction iff~tched and executed. Masked
interrupts are latched for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 7 for the reset and interrupt
instruction processing sequence.

MOTOROLA MICROPROCESSOR DATA
3~628

MC68705R5

1.1 (in CC)

07F. SP
O. DDRs
CLR INT Logic

FF. Timer
TCR6.1
TCR7.0

Load PC From
SWI: FFC/FFD
INT' FFA/FFB
Timer or
INT2: FF81 FF9

Figure 7. Reset and Interrupt Processing Flowchart
TIMER INTERRUPT
If the time mask bit (TCR6) is cleared, then, each time
the timer decrements to zero (transitions from $01 to $00).
an interrupt request is generated. The actual processor
interrupt is generated only if the interrupt mask bit of the
condition code register (CCR) is also cleared. When the
interrupt is recognized, the current state of the machine
is pushed onto the stack and the I bit in the CCR is set,
masking further interrupts until'the present one is serviced. The contents of the timer interrupt vector, containing the location of the timer interrupt service routine, is
then loaded into the program counter. At the end of the
timer interrupt service routine, the software normally executes an RTI instruction which restores the machine state
and starts executing the interrupted program. The timer
interrupt status bit can only be cleared by software.

an interrupt when the condition code 1 bit is clear. The
following paragraphs describe two typical external interrupt circuits.
Zero-Crossing Interrupt
A sinusoidal input signal (fINT maximum) can be used
to generate an external interrupt (see Figure 8a) for use
as a zero-crossing detector (for negative transitions of
the ac sinusoid). This type of circuit allows applications
such as servicing time-of-day routines and engaging disengaging ac power control devices. Off-chip, full-wave
rectification provides an interrupt at every zero crossing
of the ac signal and, thereby, provides a 2f clock.
Digital-Signal Interrupt

EXTERNAL INTERRUPT
The external interrupt is internally synchronized and
then latched on the falling edge of INT and INT2. Clearing
the I bit enables the external interrupt. The INT2 interrupt
has an interrupt request bit (bit 7) and a mask bit (bit 6)
in the miscellaneous register (MR). The INT2 interrupt is
inhilJited when the mask bit is set. The INT2 is always
read as a digital input on port D. The INT2 and timer
interrupt request bits, if set, cause the MCU to process

With this type of circuit (Figure 8b). the INT pin can be
driven by a digital signal. The maximum frequency of a
signal that can be recognized by the TIMER orlNT pin
logic is dependent on the parameter labeled tWL, tWH.
Refer to TIMER for additional information.
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. The SWI
execution is similar to the hardware interrupts.

MOTOROLA MICROPROCESSOR DATA
3-629

II

MC68705R5

(al Zero-Crossing Interrupt

(bl Digital-Signal Interrupt
VCC

In~~t

TTL

.1 Current

Max,)~'m't'ng)
'.

ItlNT
As1 MO
ac Inputs
10 Vac p-p

R.

2 iNT

MCl)

0.1-1.0
I'F

4.7 k

Level
2 iiiiT
Dlgltal--....~
Input

MCU

lJ
Figure 8. Typical Interrupt Circuits

EPROM Microcontroller Programming Module, (AN-857
Rev.2).

MODES OF OPERATION
The MCU has two modes of operations. These modes
are the normal and bootstrap.,The following paragraphs
describe the modes.

II

NORMAL MODE
This mode is a single-chip mode and is entered if th.e
following conditions are met: (1) the RESET line is low,
(2) the PCO pin is within its normal operational range,
and (3) the Vpp pin is connected to VCC. The next rising
edge of the RESET pin then causes the part to enter the
normal mode.
BOOTSTRAP
The bootstrap mode is entered if the TIMER pin equals
12 V. Refer to application note, MC68705P3/R31U3 8-Bit

TIMER
The MCU consists of an 8-bit software programmable
counter driven by a 7-bit software programmable prescaler. The various timer sources are made via the timer
control register (TCR) and/or the mask option register
(MOR). The 8-bit cOLJnter may be loaded under program
control and is decremented toward zero. When the timer
reaches zero, the timer interrupt request bit (bit 7) in the
timer control register (TCR) is set. Refer to Figure 9 for
timer block diagram.
The timer interrupt can be masked (disabled) by setting
the timer interrupt mask bit (bit 6) in the TCR. When the

Ifosc+41

Figure 9; Timer Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-630

MC68705R5

I bit in the condition code register is cleared and the TCR
bit 6 is cleared, the processor receives the interrupt. The
MCU responds to this interrupt by (1) saving the present
CPU state on the stack, (2) fetching the timer interrupt
vector, and (3) executing the interrupt routine. The timer
interrupt request bit must be cleared by software. Refer
to RESETS and INTERRUPTS for additional information.
The prescaler is a 7-bit divider which is used to extend
the maximum length of the timer. To avoid truncation
errors, the prescaler is cleared when TCR bit 3 is set to
a logic 1; however, the TCR bit 3 always reads as a logic
o to ensure proper operation with read-modify-writeinstructions.
The timer continues to count past zero, falling from $00
through $FF, and continues the countdown. The counter
can be read at any time by reading the timer data register
(TDR). This allows a program to determine the length of
time since' a timer interrupt has occurred without disturbing the counting process. TheTDR is unaffected by
reset.

SOFTWARE CONTROLLED MODE
This mode is selected when TOPT (bit 6) in the MOR
is programmed to zero. The timer prescaler input can be
configured for three different operating modes plus a
disable mode, depending on the value written to TCR
control bits 4 and 5 (TIE and TIN). The following paragraphs describe the different modes.
Timer Input Mode 1
When TIE and TIN are both programmedto zero, the
timer input is from the internal clock (phase two) and the
timer input pin is disabled. The internal clock mode can
be used for periodic interrupt generation as well .as a
reference for frequency and event measurement.
Timer Input Mode 2
When TIE = 1 and TIN = 0, the internal clock and the
timer input signals are ANDed to form the timer input.
This mode can be used to measure external pulse widths.
The active high, external pulse gates in the internal clock
for the duration of the external pulse. The accuracy of
the count is ± 1.
Timer Input Mode 3
When TIE = 0 and TIN = 1, no prescaler input frequency
is applied to the prescaler and the timer is disabled.
Timer Input Mode 4
When TIE and TIN are both one, the timer input is from
the external clock. The external clock can be used to count
external eventS as well as to provide an external frequency for generating periodic inte~r.upts. Frequency of
external input must be .;;; fosc/8.

MOR CONTROLLED MODE
This mode isselected when TOPT (bit 6) in the MOR
is programmed to logic one. The timer circuits are the
sa'11e as described in SOFTWARE CONTROLLED MODE.
The logic levels of TCR bits 0, 1, 2, and 5 are determined
during EPROM programming by the same bits in the MOR.
Therefore; bits 0, 1, 2, and 5 in the MOR control the prescaler division and the timer clock selection. TIE (bit 4) and

PSC (bit 3) in the TCR are set to a logic one when in the
MOR controlled mode. TIM (bit 6) and TIR (bit 7) are
controlled by the counter and software.

TIMER CONTROL REGISTER (TCR) $009
This is an 8-bit register that controls various functions
such as configuring operation mode, setting ratio of the
prescaler, and generating timer interrupt request signal.
All bits are read/write except bit 3. The configuration of
the TCR is determined by the TOPT (bit 6) in the MOR.
When TOPT=1, the TCR emulates the MC6805R2; when
TOPT = 0, the TCR is controlled by software.
TCR with MaR TOPT = 1

7.
Li'R

6

5

'I' TIM I

7
6
5
0
1'~T-IR-'--T-IM-'--T-IN-'--T-IE-'--PS-C-'-P-S~2-'-P-S-l-'-~
RESET:

o

u

u

u

u

u

u

*The value of corresponding bits in MaR is written during RESET rising
edge. These bits always read "one".

TIR - Timer Interrupt Request
Used to indicate the timer interrupt when it is logic
one
1 = Set when the timer data register changes to all
zeros
0= Cleared by external reset, power-on reset or
under program control
TIM - Timer Interrupt Mask
Used to inhibit the timer interrupt
1 = Interrupt inhibited
0= Interrupt enabled
TIN - External or Internal
Selects input clock source
1 = External clock selected
0= Internal clock selected (fosc 4)
TIE - TIMER External Enable
Used to enable external TIMER pin. When TOPTc= 1,
TIE is always a logical "one".
1= Enables external.timer pin
O=Disables external timer pin
PSC - Prescaler Clear
Write only bit. Writing a one to this bit resets the
prescaler to zero. A read of this location always indicates a zero when TOPT = O. When TOPT = 1, this
bit will read a logical "one1" and has no effect on
the prescaler.
PS2, PS1,PSO - Prescaler Select Bits
Decoded to select one of eight outputs of the prescaler

NOTES
When changing the PS bits in software, the PSC
bit,soould be written to a "one" in the salTle write
cycle to clear the prescaler. Changing the PS bits
withou't clearing the prescaler may cause prescaler
truncation.

MOTOROLA MICROPROCESSOR DATA
3·631

·l

PSC

TCR with MaR TOPT = 0

II

MC68705R5

PS2

PS1

PSO

Divide By

0

0

0

1

0

0

1

2

0

1

0

4

0

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

bootstrap program manipulates the PCR when programming, the user need not be concerned with PCR in most
applications.
7

I VPON I
RESET:
U

MASK OPTION REGISTER (MOR) $F38

The MOR is implemented in EPROM. This register contains all zeros prior to programming andis not affected
by reset. The MOR bits are described in the following
paragraphs.

I

I

7

6

ClK

I TOPT I

ClS

SNM

P2

Pl

PO

ClK - Clock (oscillator type)
1 = Resistor Capacitor (RC)
0= Crystal
TOPT - Timer Option
1 = MC6805R2 type timer/prescaler. All bits except
6 and 7, of the TCR are invisible to the user.
Bits 5, 2, 1, and 0 of the MOR determine the
equivalent MC6805R2 mask options.
0= All TCR bits are implemented as a software programmable timer. The state of MOR bits 5, 4,
2, 1, and 0 sets the initial values of their respective TCR bits.
ClS - Timer/Prescaler Clock Source
1 = External TIMER pin
0= Internal clock
Bit 4
Not used if TOPT = 1. Sets the initial value of TIE i.n
the TCR if TOPT = O.
1 = Not used
0= Sets initial value of TIE in the TCR
SNM - Secure Mode
1 = EPROM contents cannot be access externally
0= EPROM not programmed
P2, P1, PO - The logical levels of these bits, when decoded, select one of eight outputs on the timer prescaler.
P2

P1

PO

0

0

0

1

0

0

1

2

0

1

0

4

6

u

u

u

u

PlE - Programming latch Enable
Controls address and data being latched into the
EPROM. Set during reset, but may be cleared anytime.
1 = Read EPROM
0= latch address and data on EPROM
PGE - Program Enable
Enables programming of EPROM. Must be set when
changing the address and data. Set during reset.
1 = Inhibit EPROM programming
0= Enable EPROM programming (if PlE is low)
VPON - Vpp On
A read-only bit that indicates high volta~t the ~
pin. When set to "one", disconnects PGE and PlE
from the chip.
1 = No high voltage on Vpp pin
0= High voltage on Vpp pin
NOTE

VPON being "zero" does not indicate that the Vpp
level is correct for programming. It is used as a
safety interlock for the user in the normal operating
mode.
VPON

PGE

PLE

Programming Conditions

0

0

0

Programming mode (program
EPROM byte)

1

0

0

PGE and PLE disabled from
system

0

1

0

Programming disabled (latch
address and data in EPROM)

1

1

0

PGE and PLE disabled from
system

0

0

1

Invalid state; PGE = 0 if PLE = 0

1

0

1

Invalid state; PGE = 0 if PLE = 0

0

1

1

"High voltage" on Vpp

1

1

1

PGE and PLE disabled from
system (operating mode)

Divide By

EPROM PROGRAMMING

0

1

1

8

ERASING THE EPROM

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

The EPROM can be erased by exposure to high-intensity ultraviolet (UV) light with a wavelehgth of 2537 angstroms. The recommended integrated dose (UV intensity
x exposure time) is 25Ws/cm 2 .. The lamps should be
used without software filters,and the MCU should be
positioned about one inch from the UV tubes. Ultraviolet
erasure clears all bits of the MCU EPROM to the "0" state.
Data then can be entered by programming "1s" into the
desired bit locations.

PROGRAMMING CONTROL REGISTER (PCR) $008

The PCR is an 8-bit register which provides the necessary control bits to program the EPROM. Because the

MOTOROLA MICROPROCESSOR· DATA

3·632

MC68705R5

PROGRAMMING

ANALOG-TO-DIGITAL CONVERTER

The MCU bootstrap program tan be used to program
the MCU EPROM. The alternate vectoring used to implement the self-check is used to start execution of the bootstrap program.
A MCM2532 UV EPROM (other industry standard
EPROMs may be used) must first be programmed with
the same information that is to be transferred to the MCU
EPROM. The MC68705R5 is programmed the same as the
MC6e705R3. Referto application note, MC68705P31R31U3
8-Bit EPROM Microcontroller Programming Module
(AN-857 Rev.2) for schematic diagrams and instructions
on programming the MCU EPROM.

The chip resident 8-bit analog~to-digital (AID) converter
uses a successive approximation technique as show in
Figure 10. Four external analog inputs can be connected
to the AID via port D. Four internal analog channels (VRHVRL, VRH - VRL/2, VRH - VRL/4, and VRL) may be selected for calibration. The accuracy ofthese internal channels may not meet the accuracy specifications of the
external channels.
Multiplexer selection is controlled by the A D control
register (ACR) bits 0, 1, and 2. Refer to Table 2 for multiplexer selection. The ACR is shown in Figure 10. The
converter uses 30 machine cycles to complete a conversion of a sampled analog input. When the conversion is
complete, the digital value is placed in the A D result
register (ARR); theconversion flag is set; selected input
is sampled again; and a new conversion begins. When
ACR7 is cleared, the conversion in progress is aborted
and the selected input, which is held internally, is sampled for five machine cycles.
The converter uses VRH and VRL as reference voltages.
An input voltage equal to or greater than VRH converts
to $FF. An input voltage equal to or less than VRL, but
greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded. Each analog input
source should use VRH as the supply voltage and should
be referenced to VRL for the ratiometric conversion. To
maintain full accuracy of the A D, three requirements
should be followed: (1) VRH should be equal to or less
than VCe. (2) VRL should be equal to or greater than VSS
but less than maximum specifications, and (3) VRH VRL
should be equal to or greater than 4 volts.
The ADhas a built-in 1 2 LSB offset intended to reduce
the magnifude of the quantizing error to . 1 2 LSB rather
1 LSB with no offset. This implies that, igthan + 0,
noring errors, the transition point from $00 to $01 occurs

EMULATION
The MC68705R5 emulates the MC6805R2 and
MC6805R3 "exactly". The MC6805R2 and MC6805R3 mask
features are implemented in the mask option register
EPROM byte. The following list identifies a few minor
exceptions to the exactness of the emulation.
1. The MC6805R2 "future ROM" areas are implemented in the MC68705R5, and these 1728 bytes
must be left unprogrammed to accurately simulate
the MC6805R2.
2. The reserved ROM areas have different data stored
in them. In the MC6805R2, this area is used for selfcheck, and in the MC68705R5 this area is used for
the bootstrap program.
3. The MC6805R2 reads all ones in the 48 byte "future
RAM~'.area. This area is not implemented on the
MC6805R2 mask ROM version but is implemented
on the MC68705R5.
4. The MC68705R5 Vpp (pin 7) line is tied to VCC during
normal operations. On MC6805R2, this pin is
grounded during normal operation; on MC6805R3,
this pin is not connected.

8

D/A
Control
Logic

15 kO (Typ)

PDO/ANO
PD1/ANl
PD2/AN2
PD3/AN3

Count

1-of-8
Select
Multiplexer
~~--~~~------------------~

8
A/D
Result
'--~_"""-""""_"""--.L_ _---,,_.... , Register

Figure 10. AID Block Diagram

MOTOROLA' MICROPROCESSOR DATA
3-633

II

MC68705R5

Table 2. A/D Input MUX Selection
AID Contro: Register

ACR2

ACR1

ACRO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Input Selected

value back to memory or to the register. The test -for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.

AID Output (Hex)

Min

ANO
AN1
AN2
AN3
VRH*
VRL *
VRH/4*
VRH/2*

Typ

Max

Function
FE
00
3F
7F

FF
00
40
80

FF
01
41
81

'Internal (calibration) levels
at 1 2 LSB above VRL. Similarly, the transition from $FE
to $FF occurs 1-1/2 LSB belowVRH, ideally.

INSTRUCTION SET

I

The MCU has a set of 59 basic instructions which can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump un<;:onditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following instruction list.

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Complement

COM

Negate (2's Complement)

NEG

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Logical Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list for branch instructions. '
Function

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Load A from Memory

LDA

Branch if Lower or Same

BLS

Function

Mnemonic

BCC

Load X from Memory

LDX

Branch if Carry Clear

Store A in Memory

STA

(Branch if Higher or Same)

Store X in Memory

STX

Branch if Carry Set

Add Memory to A

ADD

(Branch if Lower)

Add Memory and Carry to A

ADC

Branch if Not Equal

BNE

Subtract Memory

SUB

Branch if Equal

BEQ

Subtract Memory from' A with Borrow

SBC

Branch if Half Carry Clear

BHCC

AND Memory to A

AND

Branch if Half Carry Set

BHCS

OR Memory with A

ORA

Branch if Plus

EOR

Branch if Minus

BMI

Arithmetic Compare A with Memory

CMP

Branch if Interrupt Mask Bit is Clear

BMC

Arithmetic Compare X with Memory

CPX

Branch if Interrupt Mask Bit is Set

BMS

Bit Test Memory with A (Logical Compare)

BIT

Branch if Interrupt Line is Low

BIL

Jump Unconditional

JMP

Branch if Interrupt Line is High

BIH

Jump to Subroutine

JSR

Branch to Subroutine

BSR

Exclusive OR Memory with A

(BHS)
BCS
(BLO)

BPL

READ-MODIFY -WRITE INSTRUCTIONS

BIT MANIPULATION INSTRUCTIONS

These instructions read a memory location or a register, modify or test its contents, and write the modified

The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space where

MOTOROLA .MICROPROCESSOR DATA
3-634

MC68705R5

all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the soft-,
ware to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear and bit test, and
branch functions are all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the carry bit of the condition
code register. Refer to the following list for bit manipulation instructions.
Function

Mnemonic

Branch if Bit n is Set

BRSET n (n=O.,. 7)

Branch if Bit n is Clear

BRCLR n (n=O ... 7)

Set Bit n

BSET n (n=O .. ,7)

Clear Bit n

BCLR n (n=O ... 7)

These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.

TAX

Transfer X to A

TXA

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).

In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memo~y with a single
two-byte instruction.
EXTENDED

In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction.

Mnemonic

Transfer A to X

IMMEDIATE

DIRECT

CONTROL-INSTRUCTIONS

Function

applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

Set Carry Bit

SEC

Clear Carry Bit

CLC

RELATIVE

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from - 126 to ' 129 from
the opcode address.

Return from Interrupt

RTI

Reset Stack Pointer

RSP

No-Operation

NOP

INDEXED, NO OFFSET

OPCODE MAP SUMMARY

Table 3 is an opcode map for the instructions used on
the MCU.

In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or to hold the address of a frequently referenced
RAM or 1/0 location.
INDEXED, 8-BIT OFFSET

ADDRESSING MODES
The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for a'il situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte
instructions, while the longest instructions (three bytes)
p€rmit accessing tables throughout memory. Short and
long absolute addressing is also included. Two-byte direct addressing instructions access all data bytes in most

In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is use'ful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
the beginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1 FE is the last location at which the instruction may
begin).

MOTOROLA MICROPROCESSOR DATA

3·635

II

•

Table 3_ Opcode Map

Bit Manipulation

~

Low

~
2

3

0011

4
0100

o

§;

Co)

s:
n
::I:J

en

::I:J

0>
0
Co)
"TI

o
(')

m
en
en

o::I:J

~

6
0110

Branch
REl

~

~1

oo"io

10
BRCLRO
BTB
3
10
BRSETl
BTB
3
10
BRCLRl
3
BTB
10
BRSE
3
J1B

0010

5.
0101

Bse

I ~BRSEJ~B

1
0001

s:o
d::I:J

BTB

i

,

4

6

4

2.

I

E
1110

F

1111

,

2

7

o

BEG

....!ill-

2
4

BSE1~c 2BHC~EL
4

10
BRSEJls
10
BRCLR7
BTB
3

BSE1~c

7

1

4

IXI

LSRA
INH

7

COMX

'-, NEG
1
IX

RTI
1

INH

1

1
4

I

INH

I

LSRX
INH

COM

IXI

IX
I

LSR

4

ROR
OIA

1

4

RORA
INH

1

7

RORX
INH

4

ASR
2
OIR

ASRA
1
INH

ASRX
1
INH

2

6

4

4

7

2 LSL

LSLA
1
INH

LSLX
1
INH

2

4

4

7

2

OIR

ROL
OIR

1

ROLA
INH

1

IXI

7

ROLX
INH

4

6

4

4

BPL
2
REI

DEC
2
OIR

DECA
1
INH

DECX
1
INH

ASR

IXI

ASR
1

IXI
IXI

1

I.

1

IX

2

2

IXI

I

IX
IX

2 BSE~~c

2

7

4

BCL~c

7

2
4

BMC
REL

BM~EL

2

INC

OIR

1

I

INCA
INH

1

INCX
INH

6

4

4

2 TST
OIR

TSTA
1
INH

TSTX
1
INH

INC
2

INC
IXI

7

1

IX

6

TST
2

TST
IXI

1

IX

3

4

5

6

2

AND
Olft

4

BIT
-'1JR

o

2

LOA
OIR

3
5

AND
EXT
XT

2

7

4

BCLR7
2
BSC

BIH
2 _ _REL

~

OIR

4

4

CLRA
1
INH

CLRX
1
INH

7

(LR

6

5 ORA

6 ORA

SEC
INH

1

CLI

2

2

4

2
2

ADC
IMM

1

2

OIR

ADC
OIA

4

INH

ORA
IMM
2

INH

2

ORA
OIR
2
4

SEI

ADD
IMM

2

ADD
OIR

3
RSP
INH

2

3

EXT

, ADD
EXT
3
4

JMP
OIR

3

JMP
EXT

7

2

8

NOP
1
INH

BSR
2
REL

2

IXI

1

CLR

IX

Inherent
Immediate
Direct
Extended
Relative
Bit Set/Clear
Bit Test and Branch
Indexed INo Offset)
Indexed. 1 Byte 18-Bit) Offset
Indexed. 2 Byte '16-Bit) Offset

LOX
IMM
2

TXA
1
INH

4 SBC
1
IX

0010

CPX

4 CPX
1
IX
4
AND
1
IX

L

,X1

2
5
2
5

IXI

3

AND

IX

4

BIT IX

2

O~

BIT: IX

-o~,

1

LOAIX

6
0110

IXI

" STA
1
IX

IX2

7
0111

STA
2
5

4

IX

1~

IX

1001

4 ORA
1
IX

A
1010

0)

IX2

' ORA
2
IXI

o ADD
IX2
3

' ADD
2
IXI

• AOD
1
IX

B
1011

C)

3 JMP
1
IX

C
1100

ADC
3
3

IX2

2
5

IX2

2

IXI

IX2

2

IXI

JMP
IXI

OIR

" LOX
3
EXT

o LOX
' LOX
IXI
3
I~ 2

, STX
OIA
2

o STX
EXT
3

" JSR
2
IXI

6

STX
3

STX
IX2

2

1

EOR

4

ADC

4

5 JMP

3

EOR

LOX
2
OIR

j. ,;" ::1

0011

IXI

9 JSR
3
IX2

2

2

3

6

" JSR
EXT
3

JSR

~

4

LDA
IX2

3 EOR

1

" SBC
2
IXI

LOA
3

6

2

6

BIT IX'

EOR
3
EXT
5
ADC
EXT
3

AEL
CLR

,

5

EOR

2 EOR
IMM

1
0001

SUB

5

IX2

4

2

CLC
INH

BIL
6

IX2

6

LOA
EXT

CMP
IXI
2

AND
3

H~

4 SUB
1
IX
4
CMP
I
IX

:

5

CPX

6

BIT
3
5
3

:X2

7 STA

IX'

1

1

AOC

JSR

9

0

IX

1101

IX

E
1110

, STX
1
IX

1111

4

1

LOX

F

LEGEND

Abbreviation. for Addr... Mod..
INH
IMM
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2

CPX
EXT
3

4

2 BSE1~c

SBC
3
6

STA
3
EXT

2

6

SBC
EXT

CPX
OIR
2

4

LDA
IMM

3
5

6

1
4

SBC
OIR

4

STA
2
OIR

IL
4

6

4

2

SUB ,
,x

TAX
1
INH

2

DEC

BMI
REL
6

5

IMM

SBC
IMM

:

5

IX

4

BCLR5
BSC

5

CMP
IX2
3

2

2
ROL

6

DEC

6

CMP
EXT
3

SUtT

2
2

LSL

6

ROL
2

5

CMP
OIR
2

CPX
IMM
2
2
AND
IMM
2
2
, BIT
1M

IX

6

LSL

4

2

ROR
1
6

lr,l

:

2
2

6

ROR
2

4

IX

E

SUB
-"- SUB
IMM
OIR

2
2

IX

IXl
1110

l2

CMP

SWI
1
INH

1X2
1101

0

11~

4

2
INn

6

LSR
2

B

1011

2

RTS

11

6

COM
,
Ixi

6

6

4

2

LS~TR

6

BNE
REL

3BRC~ -"- BCL~~c ., BHC~FI

}RC~

NEG

Register/Memory

ex-

OIR

IMM
A
1010

9

1001

9

6

2

Control
INH

8

BCS
R

4

2 BCL~~c

2

1000

4

4

BSE~~c

I

2

NEG
INH

INH

6

2 BCC
REL

7

1

I

IX

01~1

1

7

7

4

01~0

BRN
REL

~ BSE1~c

10

lEI

NEG
INH

COMA
1
INH

2

'gRSET6
BTB
10

1

:i COM
nlA

2BCL~~c

l~L

lfoo

BRARFI ' : NEGnlR

4

10
BRSE
3
JiB
10

~RSEJ1B

4

01~1

4

BSE~~c

2 BCL~~c

10
BRCLR5
3
BTB

O~

4

:gRCL~le

10

~1

Read-Modify-Write
INH
IXl

6

2

1~0

2

I

3BRSEJ'r~

B
1011

BCL~~c

INH

2 BHIREL
4
, BLS
REl

13BRCL~iB

9

,

I

2

7
0111

1001

BSE~~c

I

2

4

IR

'ofCyolffi
Mnemonic
Bytes

4
..
1

SUB
IX_

~

0,,,,,,,, '0 H.~""dm"
Opcode in Binary

0000 --' - - - - - - - - - - Address Mode

:s:

C')

CO

......

U'1

:xJ

U'1

MC68705R5

INDEXED. 16-BIT OFFSET

bit to be tested, and its condition (set or clear). is included
in the opcode. The address of the byte to be tested is in
the single byte immediately following the opcode byte.
The signed relative 8-bit offset in the third byte is added
to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction
allows the program to branch based on the condition of
any readable bit in the first 256 locations of memory. The
span of branching is from -125 to + 130 from the opcode
address. The state of the tested bit is also transferred to
the carry bit of the condition code register.

In the indexed. 16-bit offset addressing mode. the effective address is the sum of the contents of the unsigned
8-bit index register and the two unsigned bytes following
the opcode. This addressing mode can be used in a manner similar to indexed. 8-bit offset except that this threebyte instruction allows tables to be anywhere in memory.
BIT SET/CLEAR

In the bit set/Clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte to which
the specified bit is to be set or cleared. Any read/write
bit in the first 256 locations of memory. including I/O, can
be selectively set or cleared with a single two-byte instruction.

INHERENT

In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this mode. These instructions are one byte long.

BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
EPROM Programming Voltage
(Vpp Pin)
TIMER Pin - Normal Mode
TIMER Pin - Bootstrap
Programming Mode
All Others
Operating Temperature Range
MC68705R5
MC68705R5C
Storage Temperature Range
Junction Temperature
Plastic
Cerdip

Symbol

Value

Unit

VCC

-0.3to +7.0

V

These devices contain circuity to protect
the inputs against damage due to high static
voltages or electrical fields; however, it is advised that normal precautions be taken to
avoid application of any voltage hi'gher than
maximum rated voltages to this high-impedance circuit. For proper operation, it is recommended that Vin and Vou,t be constrained
to the range VSS (Vin and Voutl Vce Reliability of operation is enhanced if unused
inputs except EXTAL are tied to an appropriate logic voltage level (e.g" either VSS or
VCC).

V
Vpp
Vin

- 0.3 to + 22.0
~. 0.3 to + 7.0

Vin
Vin

- 0.3 to + 15.0
- 0.3 to + 7.0

TA

TL to TH
+ 70
~ 40 to + 85

Tstg

o to

- 55 to

T

150

C

C
CW

TJ
150
175

i

THERMAL CHARACTERISTICS
Characteristic

I

Symbol

Value

Unit

HJA

50
100
60

CW

! Thermal

l
I

Resistance
Plastic (P Suffix)
Plastic (FN Suffix)
Cerdip (S Suffix)

MOTOROLA MICROPROCESSOR DATA
3-637

II

MC68705R5.

POWER CONSIDERATION
The average chip-junction temperature, TJ, in °c can
be obtained from:
TJ=TA+(PD°!JJA)
(1)
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance,
"JA
Junction-to-Ambient, °C/W
= PINT+ PPORT
= ICC x VCC' Watts - Chip Internal Power
= Port Power Dissipation,
Watts - User Determined

For most applications PPORT< u
Za..a..a..a..>O:::_>wZ

PA4
PA3
PA2
PAl
PAO
PB7
PCl

PA3
PA2
PA1

XTAL

PBO
PB7
PB6

PCO
PC1

Vpp
TIMER

PC2
PC3
PC4
PC5

PB5
PB4
PC4

PB3

PC6

PBl

PB4
PB3
PB2
PB1

PB2

NC
PC6

PBO
POO/ANO
PD6/INT2

P01/ANl

P05/VRH

P02/AN2

,.....,.....

N
[l)ZZ Z C"'l
Z Vl
Vl: ~I:::CN
0::: 0:::1- au
a..~~  '> >~ a.. a..
0.- N M
;;a=L!)(O
00 a a
000
a.. a.. a.. a..
a.. 'a.. a..

00.-

PD4IVRL

MOTOROLA MICROPROCESSOR DATA
3-642

MOTOROLA

I

SEMICONDUCTOR

TECHNICAL DATA

MC68705S3

Technical Summary

8-Bit EPROM Microcontroller Unit
The MC68705 (I-jMOS) Microcontroller Unit (MCU)is an EPROM member of the MC6805 Family of
microcontrollers. The user programmable EPROM allows program' changes and lower volu'me applications. This high performance MCU has parallel 1/0 capability with pins programmable as input
or output. This publication contains condensed information on the MCU; for detailed information,
refer to Advance Information 8~Bit Microcontroller (ADI997R1) or contact your local Motorola sales
office.
Refer to the block diagram for the hardware features and to the list below for additional features
available on the MCU,
• Bootstrap Program in ROM
• One 7-Bit and One 15-Bit Software Programmable Prescaler
• 3752 Bytes of EPROM
• On-chip Oscillator
• 104 Bytes of RAM
• Memory Mapped 1/0
• Versatile Interrupt Handling
• Serial Peripheral Interface
• Two 8-Bit and One 16-Bit Timers
• Bit Manipulation
• Bit Test and Branch Instruction
• AID Converter
• EPROM Read Inhibit Security Bit
• Vectored Interrupts

BI,.OCK DIAGRAM
PRESCALER1/PCO

XTAl~.
CLOCK

EXTAl

PRESCALER2/PC1

<1>1
<1>2

PAO
PAl
- - ; 0 VDD

PA2
PA3

ACCUMULATOR

PM
PAS

INDEX REGISTER
CONDITION CODE
REGISTER

A

PA6

STACK POINTER

PA7

PROGRAM
COUNTER
LOW
PROGRAM
COUNTER
HIGH

---0 VSS

ANO/PDO
ANlIPAI
AN2/PD2

RESET

CONTROL

ALU

INTl

AN3/PD3
VRl
. VRH
INT2I
AN4/
VSTBY

PBO
SPISS

PBl
SPICl

PB2
SPID

PB3
SPID

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTORO.LA MICROPROCESSOR DATA
3-643

II

MC68705S3

SIGNAL DESCRIPTION

8.0

VCC and VSS

:r:

~

Power is supplied to the microcontroller using these
two pins. VCC is + 5.25 volts (± 0.5.1) power, and VSS is
ground.

>

6,0

u

~

~

NUM

""0

~
~

This pin is for factory use only. It should be connected
to VSS.

INT', INT2

5,0

\

4.0

\.

3.0

"-

2,0
1.0

o

These pins provide the capability for asynchronously
applying an external interrupt to the MCU. Refer to INTERRUPTS for more detailed information.

o

10

,

20

30
40
50
RESISTANCE (klli

60

70

80

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only

XTAL,EXTAL

I

7.0

These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a ceramic resonator, a resistor/
capacitor combination, or an external signal (depending
on setting of the Mask Option Register) is connected to
these pins to provide a system clock.
RC Oscillator

Crystal
The circuit shown in Figure 1(b) is recommended when
using a crystal. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time.

With this option, a resistor/capacitor combination is
connected to the oscillator pins as shown in Figure 1(c).
Refer to Figure 2 for the relationship between Rand fos c .

External Clock
An external clock should be applied to the EXTAL input
with the XTAL input grounded, as shown in Figure 1(d).

Cl
EXTAL

27

~~.RS.'

...-_ _ _ _t--2-6~ XTAL

. . . . XTAL

L---i~

-

EXTAL

26

:r:

At-CUT PARALLEL RESONANCE
CRYSTAL
Co= 7 pF MAX,
FREQ. = 4,0 MHz(a CL = .24 pF
RS = 40 OHMS MAX.

26
EXTERNAL
CLOCK
INPUT
(TTL COMPATIBLE,
LOW IMPEDANCE
SOURCE)

MCU
(CRYSTAL MASK
OPTION

CRYSTAL

XTAL
MCU
EITHER CRYSTAL
OR RC MASK
OPTION

EXTERNAL CLOCK

EXTAL

MCU
(RESISTOR MASK
OPTION)

APPROXIMATELY 10% to 25%
ACCURACY
EXTERNAL RESISTOR
(EXCLUDES RESISTOR TOLERANCE)

EXTAL

MCU
(RESISTOR MASK
OPTION)

APPROXIMATELY 25% to 50%
ACCURACY
TYPICAL tcyc = 1.25 flS
EXTERNAL JUMPER

NOTE: The recommended CL value with a 4.0 MHz crystal is 27 pF, maximum, including system distributed capacitance, For crystal
f,equencies other than 4 MHz, the total capacitance on each pin should be scaled as the inverse of the frequency ratio, For
example, with 2 MHz crystal, use approximately 50 pF on EXTAL and approximately 50 pF on XTAL. The exact value depends
on the motional-arm parametes of the crystal used.
Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR DATA
3-644

MC68705S3

This option may only be used with the crystal oscillator
option selected in the mask option register.
PCO, PC1
This pins allow an external input to decrement the internal timer/counter circuitry. Refer to TIMERS for additional information.
RESETIVpp
This pin has a Schmitt trigger input. The MCU can be
reset by pulling RESET low. The Vpp input is used to
input the programming voltage to the MCU EPROM. A
1K ohm pullup resistor should be used to allow proper
operation of the reset and watchdog timer operations.
INPUT/OUTPUT LINES (PAO-PA7, PBO-PB3, PCO-PC1, PDOPD6)
Ports A, B, and C are programmable as either inputs
or outputs under software control of the data direction
registers. Port D is a fixed input port and not controlled
by any data direction register. Port D has up to five analog
inputs, plus two voltage reference inputs when the analog-to-~al (AID) converter is used (PD5NRH, PD4NRLl
and an INT2 input. If the analog input is used, the voltage
reference pins (PD5NRH and PD4NRL) must be used in
the analog mode. Refer to INPUT/OUTPUT PORTS for
additional information.

INPUT/OUTPUT PORTS
INPUT/OUTPUT PROGRAMMING
Ports A, B, and C are programmable as either input or
output under software control of the corresponding data

Data
Direction
Register
Bit

Output
Data
Bit

Output
State

Input
To
MCU

High-Z**

Pin

direction register (DDR). The port I/O programming is
accomplished by writing the corresponding bit in the port
DDR to a logic one for output and a logic zero for input.
On reset, all DDRs are initialized to a logic zero state to
put the ports in the input mode. The port output registers
are not initialized on reset and should be written to before
setting the DDR bits.
Port D provides the multiplexed analog inputs, referencevoltages, and INT2. These lines are shared with the
port D digital inputs. PDo-PD3 may always be used as
digital or apalog inputs. The VRL and VRH lines are internally connected to the AID resistor. Analog inputs may
be prescaled to obtain the VRL and VRH recommended
input voltage range.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may. always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers'and avoid undefined outputs. Care must
be exercised when using read-modify-write instructions
,since the data read corresponds to the pin level if the
DDR is an input (zero) and, also, to the latched output
when the DDR is an output (one). Refer to Table 1 for 1/
functions and to Figure 3for typical port circuitry.

o

PORT B TOGGLE CAPABILITY
Port BO and B1 registers have toggle capability at the
timer underflow times. Under the control of the timer
output cross-couple bit in the miscellaneous register
(MRO)' the overflow pulses from timer A, B, and Care
directed to port BO and B1 data registers. See Figure 4
for port B configuration flow chart.
An incoming toggle pulse on port BO is allowed to
toggle the data register if port B DCR bit 4 (DCR4) is

*DDR is a write-only register and reads as' all "1s".
**Ports A, B, and C are three-state ports. Port A has optional
internal pullup devices to provide CMOS drive capability. See
Electrical Characteristics tables for complete information.

1

X

Figure 3. Typical Port I/O Circuitry and Register Configuration

MOTOROLA MICROPROCESSOR DATA
3-645

I

•

""TIMER OVERFLOW

PORT Bl

...JL
TOGGLE"
ENABLE - - - - - - - - -.....,
MCU

PORT B3
MCl!

I
s::

III B~ Ir<5=J ~P"
OUTPUT

0
~
0

SPI
MSB

::g

0

~

w

~

0)

!in

s::

(SPICRlI

(")

::g

m

0

:g.
0

MCU

nm

tn
tn
0_
::g

_I

ro::':'~L~'TI

-

I

00
......
Q

TIMER OVERFLOW ...JL

U'I

(J)

W

MCU

0

»

i!_

SPI
MSB

MCU
PBO

MCU

Of'

<

*Toggle Enable B1 = (SPICR7·SPICR4·(pBO + DDRBO))·SPICR2·SPICR4)·ClAQ
**A or B or C Depends on (MRO) and MOR5
*Write Only Register

Figure 4. Port B Configuration

PB2

MC68705S3

cleared. This bit is set on reset. An incoming toggle pulse
on port Bl is allowed to toggle the port Bl data register
under the following conditions governed by control bits
in SPI control register and SPI clock arbitration flip-flop
status.
PBl toggle enable = (SPICR7)·SPICR4·
(PBO + DDRBO) + SPICR2·
SPICR4·CLAO
where: SPICR7 = SPI interrupt request bit
SPICR4 = SPI operation enable bit
SPICR2=port Bl toggle enable/start bit
CLAO = clock arbitration flip-flop output
When PBl toggle enable is asserted, the MCU write to
PBl data register is inhibited. When SPI is not used, SPICR4
and CLAO are reset. Therefore, SPICR2 can directly control the port Bl toggle capability. Port toggle capability
allows action on port BO or Bl or both as a result of timer
overflows. This method speeds up timer overflow to port
service. A write to port BO or Bl data registers is inhibited
while the individual port toggle enable is asserted.
The port B OCR consists of four status bits (DCR4-DCR7)
and four data direction bits (DCRO-DCR3). DCR4 is a toggle enable control bit for port BO. When cleared, the timer
overflow pulse causes the data register on port BO to
toggle. Port A has an 8-bit and port C has a 2-bit wide
data direction register.

MEMORY
The MCU is capable of addressing 4096 bytes of memory and I/O registers. The memory map is shown in Figure
5. The locations consist of user EPROM, bootstrap ROM,
user RAM, eight timer registers, a mask option register
(MOR), a miscellaneous register, 'a program control register, two A/D registers, two SPI registers, and four 1/0
port registers. The interrupt vectors are located from $FF8
to $FFF. The bootstrap is a mask-programmed ROM that
allows the MCU to program its own EPROM.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexedaddressing mode. It contains an 8-bit value that
may be added to an 8- or 16-bitimmediate value to create
an effective address. The index register may also be used
as a temporary storage area.
7

x
PROGRAM COUNTER (PC)
The program counter is a 12-bit register that contains
the address of the next byte to be fetched.
11

8 7

PCH

0

PCl

1

STACK POINTER (SP)
The stack pointer is a 12-bit ,register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack,
The seven most-significant bits of the stack pointer are
permanently set at 0000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to 15
levels of subroutine calls (less if interrupts are allowed).
11
5 4
0

1 0 1 0 1 0 1 0 1 0 11 '1,1

!

SP

1

CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit register in which
four bits are used to indicate the results of the instruction
just executed. These bits can be individually tested by a
program and specific actions can be taken as a result of
their state. Each bit is explained in the following paragraphs.

NOTE
Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

Half Carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.

REGISTERS

Interrupt (I)

The MCU contains the registers des.cribed in the following paragraphs.
ACCUMULATOR (A)
The' accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manjpulations.
7
A

When this bit is set, the timer (A, B, and C), the external
(lNTl and INT2) interrupts, and the SPI interrupt are
masked (disabled). If an interrupt occurs while this bit is
set, the interrupt is latched and is processed as soon as
the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation w{ls negative (bit
7 in the result is a logic one).

MOTOROLA MICROPROCESSOR DATA
3-647

II

MC68705S3

IBYTESJ

IADDRESS!

IADDRESS!

000

$000

Port A

$000

Port B

$001

Port C

$002

$07F

Port D

$003

$080

Port A DDR*

$004

1/0, AID, SPI,
Timers, RAM,
Prog. Cont. Reg.
112B Bytes)

127
128

Page 0 EPROM
1128 aytes)

$005

Port C DDR*

$006

255

$OFF

Not Used

$007

256

$100

Timer A

$008

Main EPROM
13614 Bytes)

\.h

... h

. . ~-:-----.::I"

------1-------Mirror MOR

Mask Option Reg.

3871

II

Port B DCR*

1-------::-

3872

4087

T4088

1a

$F16

Timer A Cont. Reg,

$009

Misc. Register

$OOA

Timer B MSB

$OOB

Timer B LSB

$OOC

Timer B Cont. Reg.

$OOD

AID Control

$OOE

'AID Result

$OOF

$F1E
$F1F
SPI Data

$010

SPI Control

$011

Prog. Cont. Reg.

$012

$FF7

Timer C Capture

$013

$FF8

Timer C Data

$014

$FF9

Timer C Control

$015

$FFA

Not Used

$016

$FFB

Not Used

$017

$F20
Bodtstrap
ROM
1216 Bytes)
.
Timers lA, B, C),
SPI,INT2

External INTI

>~
a::
,,"t:~

$FFC

JADDRESsl
$018

$018

SWI

1-

$FFD
$FFE
Reset

User RAM'
140 Bytes)

RAM
1104 Bytes)

$03F
$FFF

$07F

Standby RAM
116 Bytes)

$040
$04F

User RAM
117 Bytes)

$050

$060

* Registers are write only and read as $FF.

$061
Shared Stack RAM
131 Bytes)

$07F

Figure 5. Memory Map
Zero (Z)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmeticoperation. This bit is also affected during
bit test and branch instructions, and during shifts and
rotates.

MISCELLANEOUS REGISTERS (MR) $OA
This register contains control and status information
related to INT2, auxiliary counter, prescalers 1 and 2, and
timer overflow.

I MR7 I MR6

MR5

MR3

MR2

MRl

MRO

o
MR7 - INT2 Interrupt Request Bit
If not masked by MR6, it causes an interrupt to the
MCU; if the I bit in the CCR is clear, the MCU will
acknowledge the interrupt.
1 = Interrupt requested
0= Interrupt not requested
MR6 - INT2 Interrupt Request Mask
10,; Inhibits INT2 interruptrequest
O=Does not inhibit INT2 interrupt request
MR5 - Auxiliary Counter Status/Preset Bit
If not masked by MR4, it will drive a switch to VSS on
the RESET pin causing the MCU to reset. This bit may

MOTOROLA MICROPROCESSOR DATA
3-648

MR4

RESET:

MC68705S3

be used as an auxiliary counter preset bit. If MR5 is
clear, a write of logic one will preset the auxiliary counter
(MR5 will remain zero), and if set, a write of logic zero
will preset the auxiliary counter.
1 = Auxiliary counter overfl()w
0= Auxiliary counter clear
MR4 - Watchdog Control Bit
This bit cannot be set via software. The watchdog timer
can only be disabled by reset.
1 = Watchdog timer disabled
0= Watchdog timer enabled
MR3 - Prescaler 1 Clear Bit
Presets the contents of prescaler 1 to $7F.
1 = Prescaler 1 preset
0= Prescaler 1 not preset
MR2 - Prescaler 2 Clear Bit
Presets the contents of prescaler 2 to $7FFF.
1 = Prescaler 2 preset
0= Prescaler 2 not preset
MR1 - Prescaler Cross-Couple Bit
This bit controls the output of prescalers 1 and 2 and
directs them to either timer A or B clock inputs.
1 = Prescaler 1 feeds timer B clock input, and prescaler 2 feeds timer A input
0= Prescaler 1output is used as clock input for timer
A, and prescaler 2 output is used as clock input
for timer B
MRO - Port B Toggle Cross-Couple Bit
This bit controls the overflow pulses of timers A and
B and directs them to either port BO or B1.
1 = Timer A overflow output is directed to port BO,
and timer B ortimerC (depending on the status
of MOR5) output is directed to port B1
'

0= Overflow output pulse of timer A is used as a port
B1 data register toggle clock source, and timer B
or timer C overflow output pulse is directed to
port BO toggle clock input

RESETS
The MCU can be reset four ways: (1) by initial powerup; (2) by the external reset input (RESET); (3) by a forced
reset generated by the "watchdog" counter; and (4) by
an optional internal low voltage detect circuit. The RESET
input consists mainly of a Schmitt trigger that senses the
line logic level. Figure 6,shows the MCU reset circuit.
POWER-ON-RESET (POR)

An internal reset is generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power turn-on conditions and
should not be used to ,detect any drop in the power supply
voltage. A delay of tRHL milliseconds is required before
allowing RESET input to go high. Connecting a capacitor
to the RESET input (Figure 7) typically provides sufficient
delay.
EXTERNAL RESET INPUT

The MCU is reset when a logic zero is applied to the
RESET input for a period longer than One machine cycle
(tcyel. Under this type of reset, the Schmitt trigger switches
off at VIRES - to provide an internal reset voltage.
FORCED RESET

If the auxiliary counter reset mask bit in the miscellaneous counter (MR4) is cleared and the auxiliary counter

IkU

1 f.lF TYP'**

**OPTION-100 ms DELAY
TYPICAL DURING POWER UP

MCU

MISCELLANEOUS REGISTER

Figure 6. MCU Reset Circuit

MOTOROLA MICROPROCESSOR DATA
3-649

II

MC68705S3

6

1
VCC

-"''''--+N'_-+_2_3--,

:::c

n-4

5

111

I

4

3

2

1

CONDITION
CODE REGISTER

PULL
n+ 1

,1.0/LF

n-3

ACCUMULATOR '

n-2

INDEX REGISTER
1111

Figure 7. Power-Up Reset DelavCircuit

I
PCl'

PCW

n+2

n+4
n+5

PUSH

I

status bit (MR5) is set, as a result of counter overflow, a
switch to VSS isturned on pulling the RESET pin low. A
consequent voltage drop below VIRES _ On RESET causes
a reset, which in turn sets MR4. Switching to VSS when
the RESET pin is turned off allows voltage to rise above
VIRES +, after which the reset is released. RESET pin
voltage variation occurring as a result offorced reset may
be amplified externally in order to provide a reset to other
peripheral circuits in the system. The reset output from
the MCU is not TTL compatible.
LOW-VOLTAGE INHIBIT (LVI)

The optional low-voltage detection circuit causes a reset of the MCU if the power supply voltage falls below a
certain level (VLVI). TI:1,e only requirement is thatthe VCC
must remain at or below the VLVI threshold for one tcyc
minimum.
In typical applications, the VCC bus filter capacitor will
eliminate negative-going voltage glitches of Jess than one
tcyc. The output from the low-voltage detector is connected directly to the inte~nal reset cir~uitry. It also forces
the RESET pin low via a strong discharge device through
a resistor. The internal reset is removed once the power
supply voltage rises above a recovery level (VLVR) at
which time a normal power-on reset occurs.

INTERRUPTS
The MCU can be interrupted eight different ways:
through the external interrupt INT1 input pin, with the
internal timer (either A, B, or C) interrupt request, using
the software interrupt instruction (SWI), SPI interrupt request, external port 0 bit 6 (lNT2) input pin, or at reset.
Interrupts cause the processor registers to be saved on
the stack and the interrupt mask (I bit) set to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack after which
normal processing resumes. The stacking order is shown
in Figure 8.
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted, but are considered pending until the current instruction is complete.

*For subroutine calis, only PCH and PCl are stacked,

Figure 8. Interrupt Stacking Order

(I bit clear), proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Masked
interrupts are latched' for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrup't isserviced first. The SWlis executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 9 for the reset and interrupt
instruction processing sequence.,

TIMER INTERRUPT

Each interrupt, except INT1, has a separate mask bit
which must also be c'leared, in addition to the I bit, for
the MCU to acknowledge the interrupt. The INT2, timer
A, timer B, timer C, and SPI interrupts each have their
own independent mask bits contained in MR6, TACR6,
TBCR6, TCOM, TCCM, and SPICR6. The interrupt routine
must determine the source of the interrupt by examining
the interrupt request bits, TACR7, TBCR7, MR7, TCOF,
TCCF, and SPICR7. These bits must be cleared by software. The INT1 interrupt has its own vector address.
Therefore, the INT1 interrupt request is cleared automatically, and then the'INT1 vector is serviced.
EXTERNAL INTERRUPT

The external interrupt is internally synchronized and
then latched on the falling edge of INT1 and INT2. Clearingthe I bit enables the external interrupt. The INT2 interrupt has an interrupt request bit (bit 7) and a mask bit
(bit 6) in the miscellaneous register (MR). The INT2 interrupt is inhibited when the mask bit is set. The INT2 is
always read as a digital, input on port D. The INT2 and
timer interrupt request bits, if set, cause the MCU to process an interrupt when the condition code I bit is clear.
The following paragraphs describe two typical external
interrupt circuits.

NOTE
Zero-Crossing Interrupt

The current instruction is considered to be the one
already fetched and being operated on.
When the current instruction is complete, the processor
checks all pending hardware interrupts and, if unmasked

A sinusoidal input signal (fINT1 maximum) can be used
to generate an external interrupt (see Figure 10a) for use
as a zero-crossing detector (for negative transitions of
the ac sinusoid). This type of circuit allows applications

MOTOROLA 'MICROPROCESSOR ,DATA
3-650

MC68705S3

1.I(lN CCR)
07F. SP
O. DORA
FO.DDRB
FC.DDRC
7F. PRESC. 1
7FFFF • PRESC. 2
40. SPICR
50.MR
50. TRCR
FF. TIMER A
50. TBCR
FFFF. TIMER B
53. TCCR
FF. TIMER C
07. RCSR
CLR INT LOGIC

TIMERS A, B, C,
INT2, CAPTURE, SPI
LOAO PC FROM
SWI: FFC/FFD
INT1:FFA/FFB
TIMERS A, B, C
CAPTURE
SPI OR INT2:
FFS/FF9

+

TRCRHRCR6
ITIMER A)

+

+

TBCRHBCR6
ITIMER B)

TCOF-TCOM .
ITIMER C)

+

TCCF-TCOM
ICAPTURE)

SPICR7-SPICR6
ISPII

Figure 9. Reset and Interrupt Processing Flowchart

such as servicing time-of-day routines and engaging/disengaging ac power control devices. Off-chip, full-wave
rectification provides an interrupt at every zero crossing
of the ac signal and, thereby, provides a 2f clock.

is zero, SWI executes after the other interrupts. The SWI
execution is similar to the hardware interrupts.

TIMERS
Digital-Signal Interrupt

With this type of circuit (Figure lOb), the INTl pin can
be driven by a digital signal. The maximum frequency of
a signal that can be recognized by the TIMER or INTl pin
logic is dependent on the parameter labeled tWL, tWH.
Refer to TIMER for additional information.

The MCU has four timers and two programmable prescalers. The timers are identified as timer A, B, C, and the
auxiliary counter. Refer to Figure 11 for timers A, B, and
C block diagram. The following paragraphs described the
different timers.

SOFTWARE INTERRUPT (SWI)

TIMER A

The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. If the I bit

Timer A is an 8-bit programmable down counter, which
can be loaded under program control. Timer A· also

MOTOROLA MICROPROCESSOR DATA
3-651

II

MC68705S3

VCC
AC
(fINTMAX.i
R~l M!l
AC INPUT
"'10 Vacp -p

4.7 k
TTL
LEVEL _ _...._25.... INTl
DIGITAL
INPUT

(CURRENT

~;,':INT

MCU

MCU

lJ----IBi DIGITAL-SIGNAL INTERRUPT

(Ai ZERO-CROSSING INTERRUPT

Figure 10. External Interrupt

I

includes a modulus latch which allows the timer to be
"auto-reloaded." As clock inputs are received, timer A
decrements toward $00. When $00 is reached, bit 7 in the
timer A control register is set and the timer is reloaded
with the contents of the modulus latch. An underflow
condition is also generated when value $00 is reached.
This state can be used to toggle bit a or bit 1 of port B
directly under the control of the miscellaneous register
(MRO), the SPI control register, and the port B data direction register. Setting TACR6 or the I bit in the condition
control register will prevent timer interrupts from being
processed. The timer interrupt request bit MUST be
cleared by software. There are three ways of loading data
from the modulus latch into timer A as described in the
following paragrahs.

will inhibit timer A auto-loading, interrupt generation, and port B toggle mechanisms.
TIMER A CONTROL REGISTER $09
76543210

I TAGR71

Direct Loading

When the MCU writes to timer A data register, the data
is latched by the modulus latch, and forced into the timer.
This operation requires that TACR3 be cleared.
Asynchronous External Event Loading

When TACR3 is a logic one, the contents of the modare transferred to the timer at the rising edge
of INT2 interrupt request bit (MR7) gated with interrupt
request mask bit (MR6). If this loading is used, care must
be taken in programming as it will start an interrupt service routine if the I bit in the CCR is clear. Loading $00 to
timer A allows a countdown of 256 clocks before the next
$00 state is reached.
ulu~ch

Auto-Loading

The modulus latch is automatically loaded when the
timer reaches $00. This loading is dependent on the setting of TACR3. Auto-loading also occurs in both the previous loading modes. Timer A can be read at any time
without affecting the countdown of the timer. The timer
and modulus latch are set to $FF on reset.
NOTE

Loading $01 to timer A should be avoided when
operating with a divide-by-one prescaler. Doing so

TAGR61 TAGR51 TAGR41 TAGR31 TAGR21 TAGRl

o
TACR7 - Timer A Interrupt Request Flag
1 = Timer A has transition to $00
a= Software or reset cleared
TACR6 - Timer A Interrupt Request Mask
1 = Interrupt request inhibited
0= Interrupt request not inhibited
TACR5 - External or Internal Bit
~ = External clock source for prescaler 1
a= Internal clock source for prescaler 1
TACR4 - External Enable Bit
Control bit used to enable the external timer pin
(PRESCALER1/PCO).
TACR5 TACR4

Prescaler 1 Clock Source

0

Internal Clock

0

1

AND of Internal Clock and PRESCALER1IPCO*

1

0

Inputs Disabled

1

1

PRESCALER1IPCO* Low-to-High Transition

0

*The status of PRESCALER1/PCO depends upon the data direction status of PRESCALER1/PCO. If PRESCALER1/PCO is an output, then the clock source is equal to the port data register
content, independent of the port electrical loading. If an input,
then the clock source is the logic level of PRESCALER1/PCO.

TACR3 - Timer A Load Mode Control
1 ~Asynchronous external event loading (INT2 driven loading is enabled)
a= Allows direct loading of timer A
TACR2, TACR 1, TACRO - Prescaler 1 Division Ratio Control Bits
When set, these bits select one of eight possible outputs on prescaler 1.

MOTOROLA MICROPROCESSOR DATA
3-652

I TAGRO I

RESET:

MC68705S3··

RESET MR3
PRESCALERl/PCO
SELECT MRl

TIMER A

OVERFLOW A

TO MCU

INT

TO MCU

OVERFLOW B

SELECT TBRC3, 2, 1, 0

SELECT TBCR4, 5

INT

SELECT MRO PORT
Bl TOGGLE
RESET MR2

PORT
BO TOGGLE

PRESCALER2 PCl

TOMCU
INTERAL
CLOCK - - - - - - - - - - - - -.....

c~~t}----~~~:.£..---j..--1INT

Figure 11. Timers A, B, and C Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-653

TO MCU

I

MC68705S3

TACR2
0
0
0
0
1
1
1
1

TACR1
0
0
1
1
0
0
1
1

TACRO

a
1
0
1
0
1
0
1

put, then the clock source is equal to the port data register
content, independent of the port electrical loading. If an input.
then the clock source is the logic level of PRESCALER2/PC1.

Divide By
1
2
4
····8

iBCR3, TBCR2, TBCR1, TBCRO '- Prescaler 2 Division
Ratio Control Bits
When set, these bits select one of eight possible output
on prescaler 2.

16
32
64
128

TIMER B
This is a 16-bit timer which is accessed via two registers
($OB for the most~significant byte (MSB) and $OC for the
least-significant byte (LSB)). The MSB has a "pipeline"
latch that allows a "snap shot" value of the entire 16 bits
to be read. Read/write operations to the LSB are direct.
The LSB can be read at anytime without disturbing the
count. When the LSB is read, the contents of the MSB
are loaded into the pipeline latch so a read of the MSB
is actually the contents of the latch.
When writing to the LSB, the contents are immediately
entered into the timer. At the same time the pipeline
contents are forced into the MSB of the timer. This allows
a 16-bit word to be placed into the timer data register
during a LSB write operation. An underflow condition is
also generated when value $00 is reached. This state can
be used to toggle bit 0 or bit 1 of port B directly under
the control of the miscellaneous register (MRO), theSPI
control register, and the port B data direction register.
Setting TBCR6 or the I bit in the condition control register
will prevent timer interrupts from being processed. The
timer interrupt request bit MUST be cleared by software.

TIMER B CONTROL AND STATUS REGISTER $00
76

S

4

3

21

a

I TBCR71 TBCRSI TBCRSI TBCR41 TBCR31 TBCR2 I TBCRI I TBCRO I
RESET:

o

TBCR7 - Timer B Interrupt Request Flag
1 = Timer B has transition to $00
0= Software or reset cleared
TBCR6 - Timer B Interrupt Request Mask
1 = Interrupt request inhibited
0= Interrupt request not inhibited
TBCR5 - External or Internal Bit
1 = External clock source for prescaler 2
0= Internal clock source for prescaler 2
TBCR4 - External Enable Bit
Control bit used to enable the external timer pin
(PRESCALER2/PC1 ).
TBCR5 TBCR4
Prescaler 2 Clock Source
Internal Clock
0
0
1
AND of Internal Clock and PRESCALER2/PC1*
0
Inputs Disabled
1
0
PRESCALER2/PC1 * Low-to-High Transition
1
1
*The status of PRESCALER2/PC1 depends upon the data direction status of PRESCALER2/PC1. If PRESCALER2/PC1 is an out-

TBCR2
0
0
0
0
1
1
1
1
0
0

TBCR3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

a
0
1
1
1
1

a
0
1
1
0
0

1
1

TBCRO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Divide By
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768

TIMER C
Timer C is an 8-bit programmable down counter. The
timer contains a modulus latch which allows the timer to
be auto reloaded. The timer auto reloads with the contents of the modulus latch upon every $01 to $00 transition. Timer C contains a capture register. This read-only
register and the contents are refreshed by the contents
ofthe data register during the capture instance. The timer
can be written to at any time, and the contents of both
the data register and modulus latch are updated immediately. The timer is set to $FF on reset, but the contents
of the capture register are not valid until the first capture
after reset.

TIMER C CONTROL REGISTER $015
7

I TCaF

S

4

3

1

0

I TCaM I TCCF I TCCM I TCEG I TCCS I TCCll I TCClO I

RESET:

o

1

0

0

0

TCOF - Timer C Overflow Flag
1 = Timer C has transition to $00
0= Software or reset cleared
TCOM - Timer C Interrupt Mask
1 = Interrupt request inhibited
0= Interrupt request not inhibited
TCCF - Timer C Capture Flag
1 = Proper capture occurred on PRESCALER1 or
PRESCALER2. No new capture occurs when set
o= Softwa re 0 r reset cI ea red

MOTOROLA MICROPROCESSOR DATA

3·654

TBCRl
0
0
1
1
0
0
1
1

MC68705S3

TCCM - Timer C Capture Interrupt Request Mask
1 = Inhibits interrupt request generated from TCCF
0= Does not inhibit interrupt request generated from
.TCCf
TCEG - Timer C Capture Edge Select
1 = S.elects rising edge of PCO or PCl to be capture
instance
0= Selects falling edge of PCO or PC1 to be capture
instance
TCCS - Timer C Capture Source Select
1 = Select PRESCAlER2/PCl as capture source
O=Select PRESCAlERlIPCO as capture source
TCCl1 and TCClO - Timer C Clock Source Select
Clock source selection is defined below.
TCCl1

Timer C Source

TCClO

Timer B Source

0

Internal Clock

0

0

Internal Clock

1

MRl Status*

1

MR1 Status*

0

Internal Clock

1

,MR1 Status*

1

MR1 Status*

Internal Clock

NOTES:

1. *Denotes prescaler 1 or 2 clock source depending on miscellaneous register bit 1 (MR1) status.
2. MR1 bit Cleared (logic zero) at reset:
Prescaler 1 clock selected to timer A
Prescaler 2 clock selected to timer Band. C
3. MR1 bit set (logic one):
Prescaler 1 clock selected to timer Band C
Prescaler 2 clock selected to timer A
4. Prescaler 1 output determined by the status of Timer A
control register bits 2, 1, and 0 (TACR2, TACR 1,and TACRO).
5. Prescaler 2 output determined by the status of Timer B
control register bits 3, 2,1, and 0 (TBCR3, TBCR2, TBCR1,
and TBCRO).

PRESCALER 1
Prescaler 1 is a 7-bit binary down counter whose value
is selected by TACR2, TACR1, and TACRO. The selected
output is used as the clock input to either timer A or B,
depending upon the status of the prescaler cross-couple
bit (MR1). The type of clock source to prescaler 1 may be
selected by TACR5 and TACR4. Prescaler 1 is set to $7F
at reset or under program control when a one is written
to prescaler 1 clear bit (MR3).
PRESCALER 2
Prescaler 2 is a 15-bit down counter; its value is selected by TBCR3, TBCR2, TBCR1, and TBCRO. The selected output is used as the clock input to either timer A
or B, depending upon the status of the prescaler crosscouple bit (MR1). The type of clock source to prescaler 2
may be selected by TBCR5 and TBCR4. Prescaler 2 is set
to $7FFF at reset or under program control when a one
is written to prescaler 2 clear bit (MR2).
AUXILIARY COUNTER
This register is a fixed counter which is clocked by the
internal clock (fosc divided by four). Total count period
is 4095 cycles. The MCU communicates with this counter
via the miscellaneous register (MR5 and MR4). Countdown may be aborted at any time under program control,

which also resets the counter to 4095 and clears MRS.
When MR4 is clear and MR5 is set as a result of counter
time out,the reset pin is internally pulled to ground. If
the MCU loses control of the program, the "wa~chdog"
timer will bring the MCU back to reset. Refer to Figure
12 for counter operation diagram.

EPROM PROGRAMMING
ERASING THE EPROM
The EPROM can be erased by exposure to high-intensity ultraviolet (UV) light with a wavelength of 2537A. The
recommended integrated dose (UV intensity x exposure
time) is 25Ws/cm 2 . The lamps should be used without
software filters, and the MCU should be positioned about
one inch from the UV tubes. Ultraviolet erasure clears all
bits of the EPROM to the "zero" state. Data can then be
entered by progamming "ones" into the desired bit locations.
CAUTION
Be sure that the EPROM window is shielded from
light except when erasing. This protects both the
EPROM and light-sensitive nodes.

MASK OPTION REGISTER (MOR) $F1 E
The MOR is implemented in EPROM and contains all
zeros prior to programming. The MOR bits are described
in the following paragraphs. This register is not affected
by reset.
7

6

5

I elK I TOPT I PBTS I

I

0

SEC

ClK' --- Clock (oscillator type)
1 = Resistor Capacitor (Re)
0= Crystal
TOPT - Timer Option
1 = Enables timer C
0= Disables timer C
PBTS - Port B Toggle Source
This bit is not used on the TJ6 mask set. When cleared
the operation is the same as the TJ6 mask set operation.
1 = Port B toggle source will come from the timer B
overflow even if a write operation is performed
on timer C
0= After the first write operation to timer C, the toggle source comjng from the timer B overflow is
replaced by the timer C overflow. If no write operation is performed on timer C, then timer B is
the port B toggle source.
lVI - low Voltage Inhibit
1 = Enables low-voltage detection circuitry
0= Disables low-voltage detection circuitry
Bits 1-3
User available register bits during normal mode of operation
SEC - Security
For full security, this bit must be set in the MOR and
mirror MOR ($F16).
1 = Enables EPROM read protection
0= Disables EPROM read protection

MOTOROLA MICROPROCESSOR DATA
3-655

4

lVI

II

MC68705S3

Auxiliary
Counter

I

EXTERNAL RESET ~

RESET

,

I

U;

.......

o
o
o
o

: [MR5[=1

I

[MR5]=O

I
I

7f//////I

MCU WRITE

I

I

:t<'

I

I

O. [MR4]

1.[MR5]

FORCED RESET ~

I

I
I

:IRES+

[MR5]~
[MR4]

I

I

1.[MR4]

Counter Preset by Writing "1"
Underflow: MR5 • 1; No Forced Reset
Counter Reset by Writing "0"
Underflow MR5 • 1 Forced Reset

Figure 12. Auxiliary Counter Operation

MOTOROLA MICROPROCESSOR DATA
3-656

I

~

VI RES

I

TIME

::r.::::-

jp...--.-_L

I

MC68705S3

PROGRAMMING CONTROL REGISTER (PCR) $012
The PCR is an 8-bit register which provides the necessary control bits to program the EPROM. The bootstrap
program manipulates the PCR when programming so the
user need not be concerned with PCR in most applications.

RESET:
U

u

u

PLE - Programming Latch Enable
Controls address and data being latched into the
EPROM. Set during reset, but may be cleared anytime.
1 = Read EPROM
0= Latch address and data on EPROM
PGE - Program Enable
Enables programming of EPROM. Must be set when
changing the address and data. Set during reset.
1 = Inhibit EPROM programming
0= Enable EPROM programming (if PLE is low)
VPON - Vpp On
A read-only bit that indicates high voltage at the Vpp .
pin. When set to "one", disconnects PGE and PLE from
the chip.
1 = No high voltage of Vpp pin
O=High voltage on Vpp pin

A M2532/2732 UV EPROM must first be programmed
with the same information that is to be transferred to the
MCU EPROM. Unprogrammed EPROM address locations
should contain·$OO to speed up the programming operation. Figure 13 is a schematic diagram for aboard and
circuitry that can be used to program the MCU EPROM.
Perform the following steps to program the MCU
EPROM:
1. Insert the programmed EPROM and erased MCU
EPROM into U2 and U3.
2. Programming operation starts when S1 is placed
to the ON position.
a) DS1 and DS2 illuminate.
b) MCU control is t~ansferred to the bootstrap
ROM, and the programming routine executed
by the bootstrap loader program.
c) DS3 blinks during programming. When programming is complete, DS3 remains illuminated.
d) After two seconds DS4 will illuminate indicating the MCU has been programmed and verified.
3. Remove power by placing S1 to the OFF position
and remove programmed MCU.
NOTE
No programming can be done once the MaR and
mirror MaR security bit has been programmed to
logic one. The only way to proceed from the secure
mode to the non-secure mode is by erasing the
MCU. The MCU must be reset following programming of the SEC bits to enable the security feature.

NOTE
VPON being "zero" does not indicate that the Vpp
level is correct for programming. It is used as a
safety interlock for the user in the normal operating
mode.
VPON

POE

PLE

0

0

0

1

0

0

PGE and PLE bits disabled

0

1

1

Programming disabled (latch
address and data in EPROM)

EMULATION

Programming Coriditions
Programming enabled
(program EPROM byte)

1

1

0

PGE and PLE disabled

0

0

0

Invalid state

1

0

1

Invalid state

0

1

1

Voltage applied to RESETlVpp
pin

1

1

1

PGE and PLE disabled
(operating mode)

PROGRAMMING
The MCU bootstrap program can be used to program
the EPROM. The vectors at address $FF6 and $FF7 are
used to start the program. This vector is fetched when
~TP is applied to the PRESCALER/PCO pin and the RESET pin is allowed to rise above VIRES +. The level on
the PRESCALERIPC1 pin, when the RESETIVpp pin rises
above VIRES +, determines which programming mode
is selected. A high level on PRESCALERIPC1 selects the
auto-programming operation.

The MCU is designed to emulate the functions of either
the MC6805S2 or MC6805S3. However, due to pin assignments, processing, and mask options, the MCU has
some differences. The differences are listed as follows:
1. Port A output on the MC6805S2/S3 is a mask option.
The CMOS pullup option on port A is not implemented on MC68705S3. If this option is required,
pullup resistors must be installed.
2. The RC clock on the MC6805S2/S3 is a mask option.
To enable the MC68705S3 RC clock, MOR bit 7 must
be programmed to a logical one.
3. The LVI on the MC6805S2/S3 is a mask option. To
enable the LVI on MC68705S3, MaR bit 4 must be
programmed to a logical one.
4. The MC68705S3 RESETIVpp and VSTBy/AN4/1NT21
PD6 electrical characteristics are different for the
MC6805S2/S3.
5. Pin 4 (AN4 and VSTBY) on MC6805S2/S3 is a mask
option. On the MC68705S3, pin 4 is enabled for
VSTBylAN4/1 NT2/PD6.
6. On MC6805S2/S3 pin 4, standby RAM contents will
be lost if the voltage drops below 3.0 V. Standby
RAM on the MC68705S3 will not be lost unless voltage drops below 4.0 V.
7. Above certain voltages (3.7 V typical), pin 4 will exhibit lower input impedance than the MC6805S2/S3.
This may cause AID conversion inaccuracies if the

MOTOROLA MICROPROCESSOR DATA
3-657

I.

•

~
+26Vo-----.:dfc

+5V~o--.

C1
OSl

R2
22 k

GNO~

-

~.

~

II
VOO
2732

l.!:!..!J

m
(I)

~

g
"'a

(I)

o~

g

2532

EPROM
CONFIGURATION

gi6

U1
08 !3
MC14040B 07 2

g~ 35

r;-;:;l

04
03 ;
02 9

VS~
8

.

1

012~
14
09 12

r;:::;e,

o
m
co

~

+5V
2

+5V
'24

~

w

CR4
1N914

~~~~~KY I
C3
l°.47I'F

o
§;

!

CR3

~

+5V

n

R6.
10 k

Q2
TIP41C
R4
22 k

01

3:

I

R5
22

R3
4k

I

...l§. CE/A11 VOO

~~

~~

11
03 13

02
03

17
18 PA3

~~O

~~

22
23 A8

~

A7 .
3 A6

~~
5

4

~

~

DO

U2

~~

~

~

21 PA5

17

07

22

A3 273212532
A2 EPROM
(SOCKET)I
AO VSS OE 1
121 _ 120

+5 V
11.1

n
R

O.lI'FJ

:~~

06

8 A1

C4

PAO

04
05 16

~;

R9
1k

RESETIVppl.-=2::;.3_ _ _ _ _ _ _ _- - - l

~O

A11IVpp

-=

1PCO

PM

~~~

PB1j12

_

~

••.,.

U3

A

MC68705S3 113
MCU PB2F----:::+....,_+
27

EXTAL
(SOCKET)
PB 3
PC1

il!t
13

~

•

I

R12
4k
~

+5V
R13
4k

Figure 13. Programming Connections Schematics Diagram

MC68705S3

pin is used as fifth AID input channel. Pin 4 is always
a high :mpedance input on the MC6805S2/S3.
8. Reset and Vpp functions share a common pin (23)
on the MC68705S3. Therefore, electrical characteristics on this pin may vary front the same pin on
MC6805S2/S3. The input impedance on the
MC68705S3 pin is approximately equivalent to the
1.0 ohm pulldown resistor; whereas, on the
MC6805S2/S3, this pin is a high impedance (220K
ohms) input. Therefore, the MC68705S3 requires a
pullup resistor on the. RESET pin to recover from a
reset condition.

SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) has arbitration on
the data and clock lines. The SPI communicates with the
MCU via data and control registers. The SPI data and
clock inputs are always taken from their respective I/O
ports, regardless of the status of the data direction registers relative to that port. The SPI can operate in modes
from auto clocked (NRZ), half duplex, and full duplex with
from a one to a four wire combination. Refer to Figure
14 for the SPI block diagram.
SPI CONTROL AND STATUS REGISTER
This 8-bit register contains the status ar.d control bits
relative to SPI operations. The SPI control register operation is shown in Figure 15. The SPI control and status
register bits can be set or cleared under program control.
7

S

543210

ISPICR71 SPICRsl SPICR51 SPI·CR41 SPICR31 SPICR21 SPICR1 ISPICRO I

selected by SPICR5, during the active transaction
mode
0= Output of the SPI data register is loaded to port
B2 data register at the appropriate SPI clock edge
selected by SPICR5, during the active transaction
mode
SPICR2 - Port Bl Toggle Enable/Start Bit
Dual-function bit controlled by the status of SPICR4.
1 = Start bit is set by negative transition of the data
input of the SPI. data shift register while the clock
is at the idle level when SPICR4= 1. Start bit set
under program control to enable port Bl data register toggle facility when SPICR4=0.
0= Stop SPI operation when SPICR4 = 1. Cleared under program control when SPICR4=0.
SPICRl - Mode Fault Flag
1 = (a) Mode flag .is set when SPI data output arbitration occurs on the SPI data output port (PB3
or PB2) selected bySPICR3. The MCU loses
data mastership, and theSPI data output port
DDR is cleared.
(b) Mode flag is set if a low level is detected on
slave input PBO. Then, the MCU loses clock
mastership switching to the clock slave mode,
and port BlOOR is cleared.
(c) Mode flag is set during the idle mode when a
negative clock edge is.detected on the SPI clock
input, and the port Bl data register is cleared.
0= Cleared under program control
SPICRO.:...... SPI Input Data Select Bit
1 = SPI data from port B3 is latched into the SPI data
register
0= SPI data from port 62 is routed to the input of the
SPI data register

RESET:

o

SPI DATA REGISTER

SPICR7 - SPI Interrupt Request Bit
Set on eighth data input strobe. MCU services. this interrupt if I bit is clear in CCR.
1 = Interrupt request (if SPICR6 not masked)
0= No interrupt pending
.
SPICR6-,- SPllnterrupt Request Mask Bit
1 = Disables interrupt request from SPleR7
0= Enables interrupt request from SPICR7
SPICR5 - SPI Clock Sense Bit/Bus-Busy Flag
Dual-function bit controlled by the status of SPICR4.
1 = Start SPI operation when SPICR4 = 1. Input data
latched on positive edge and output data changed
on negative edge of SPI clock when SPICR4 = O.
0= Stop SPI operation when SPICR4 = 1. Input data
latched on negative edge and output data changed
on positive edge of SPI clock when SPICR4 = O.
SPICR4 - SPI Operation Enable Bit
This bit determines the functions of SPICR5 and SPICR2.
1 = Enables SPI data register shifting, data and clock
arbitration logic, and slave select input logic
0= Disables SPI data register shifting, data and clock
arbitration logic, and slave select input logic
SPICR3 - SPI Data Output Select Bit
1 = Output of the SPI data register is loaded to port
B3 data register at the appropriate SPI clock edge

This register can b.e written to any time and can also
be read, regardless of serial operations, without disturbing the data. A one bit shift to the left occurs each time
there is a data input strobe while the LSB is loaded with
data from port B2 or B3. The MSB is loaded every time
there is data output strobe. Data input and output strobes
are generated internally only during the active transaction time.
SPI DIVIDE-BY-EIGHT COUNTER
The counter is cleared during SPI deselect or idle modes.
A count occurs at every data input strobe during the active transaction mode. At bverflow, SPICR7 is set which
puts the SPI in idle mode and blocks all data input and
output strobes. The counter is cleared when PBO is high
if the SPI is in the slave mode or when a "start" condition
is detected.
SPIOPERATION
TheSPI can operate in a variety of modes. Software
assisted protocols may be defined to upgrade the hardware versatility and/or system performance of the MCU.
Some features common to all operating modes are summarized in Table 1 and in the following paragraphs.

MOTOROLA MICROPROCESSOR DATA
3~659

3

MC68705S3

(SPICR3)-DATA OUT STROBE

I

DATA OUT
STROBE
DATA IN
STROBE

OVF
OPEN DRAIN
ENABLE
DCRl
CLEAR
-;-8

CLEAR
CLOCK

DATA IN
STROBE
TOGGLE
ENABLE
REGISTER
DCR4

MRO

OVERFLOW

Figure 14. Serial Peripheral Interface Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-660

DATA
D.lRECTION
REGISTER
OCR BO

MC68705S3

INTERRUPT
REQUEST
TO CPU

FROM
PBI PIN

Figure 15. SPI Control Register Operation

1) SPI data input and output may be individually routed
to or from PB2 or PB3 (Table 2). These four routings
provide half and full duplex operations, as well as
allowing bidirectional information to flow in daisychained systems.
2) When data input and output is done on PB2, PB3
is available for any other use and vice versa.
3) Data input is always relative to the port pin logic
level regardless ofthe data direction register status
on that pin.
4) In full duplex operation, 16 bits of information may
be transferred with eight clock pulses between at
least two devices with transmit capability. Both PB2
and PB3 are used for data transfer. The same shift
register is used for data in and data out. The byte
transmitted replaces the byte received. SPICR7 is
used to signify that the 1/0 operation is complete.
5) SPI clock is always provided on port B1. In the clock
slave mode, port B1 DDR is in the input mode
(cleared). In the clock master mode, port B1 DDR
is set; therefore, the MCU imposes the clock level
on PB1 until there is clock arbitration on the clock
line or until the MCU loses clock mastership when
PBO goes low.
6) No fixed baud rate generation exists. The clock
frequency is dependent on the prescaleer clock
source option, prescaler divide ratio, and timer divide ratio as well as the port C status in case of
external clocking for the timer. Toggling of the port
B1 data register is automatically allowed during
the active transmission mode.

7) All devices connected to the SPI must have their
output and input data strobe on the same clock
edge for correct tran~fer of data.
8) During the ac~ive transmission mode, the first clock
edge must· be the output data strobe. When this
occurs, the MSBs of the data registers of all transmitters are copied onto the data output pins, and
the MCU copies the MSB of its SPI onto the port
B2 or B3 data register.
9) Port B data direction registers and port B data control registers are accessible during SPI operation.
During active transaction mode, the PB1 data register, PB2 data register (if SPICR3 = 0), and PB3 (if
SPICR3 = 1) are not write accessible under program
control.
10) Port B lines not used for SPI can be used for other
digital functions.
.,
SELECT INPUT OPERATION

An external device supplies slave select information
via port BO. If slave select is not used, set port BO to output
mode to inhibit slave select function.
The following paragraphs describe clock master and
clock slave operating modes of the SPI.
Master Mode Slave Select Actions

The MCU monitors slave select input in master mode
to assure that it stays false. If slave select goes true, the
MCU exits master mode and becomes a slave. This implies that a write collision has occurred which means two

MOTOROLA MICROPROCESSOR, DATA
3-661

II

MC68705S3

Table 1. Summary of SPIOperations
DEFINITIONS
Transmitter - Data Master: DDRB2 or 3 = 1
Receiver - Data Slave: 'DDRB2 or 3=0
Clock Master: DDRB1 = 1
Clock Slave: DDRB1 = 0
Transaction Mode: SPICR4= 1
1) Active: SPICR7.(DDRBO.PBO + DDRBO) if DDRB1 = 0 (clock slave mode) or
SPICR7.(DDRBO.PBO + DDRBO) if DDRB 1 = 1 (clock master mode)
Clock Pulses allowed, data shifted
2) Idle: SPICR7 + DDRBO.PBO if DDRB1 = 0 (clock slave mode)
Clock pulses blocked, data output line in high-impedance state
Deselect Mode: SPICR4=0- No SPI Operations

II

SLAVE SELECT INPUT
Slave Select Input: SPISS - PBO
If DDRBO = 0 then so SPISS action· on MCU
1) Master Mode:' SPISS = 1 DDRB 1 = 1
SPISS 1 - 0: Switch to Slave Mode (DDRB1 1 - 0)
Set SPICR1 (Mode Fault Flag)
2) Slave Mode: SPISS~O DDRB1 =0
External clock is allowed to shift data in/out. If SPISS is pulled high, the external clock input pulses
are inhibited; no data shift; divide-by-eight counter cleared; SPID (PB2 or PB3) switched to highimpedance state.
Used as Chip-Select Input
DATA ARBITRATION
Data master loses data mastership when data collision occurs during internal data strobe time.
If SPID output port (PB2 or PB3) = 1 while actual pin level is pulled low externally - conflict detected at internal
data strobe time.
Then SPICR1 (mode fault flag) is set; SPID output port DDR (B2 or B3) 1 .0 (high-impedance state).
CLOCK ARBITRATION
..•.
MCU has clock mastership (DDRB1 = 1)
1) Via SPISS line (DDRBO=O). If SPISS is pulled low, then clock mastership lost; DDRB1 1.0 (high-imped'ance state); SPICR1 is set (mode fault flag).
2), Via clock line SPICL (DDRB1 =1 and DCRB5=0)
Condition: SPICL must have open-drain output (DCRB5= 0)
If clock line is held low externally then clock mastership is not lost; minimum tCLH and
tCLK times are guaranteed.
'
If SPICL goes low during idle mode then SPICR1 = 1 and clock line is switched low to
inhibit the system clock.
MODE FAULT RAGE OPERATION (SPICR"
Flag set when any of,the following conditions occur:
Data arbitration occurs on SPID output.
Clock arbitration with SPISS during master to slave switching.
Clock arbitration via clock line if SPICL 1 .0 during idle.
START, STOP, AND CLOCK IDLE CONDITIONS
Clock Idle: The clock level just prior to the transition that causes data on the serial output data line to be
changed is defined as the SPI clock idle state.
SPICR5 = 0: SPICL Idle = Low State
SPICR57' 1:s,Plci Idle = High State
These definitions are necessary for determining start and stop conditions.
NOTE
Clock. idle state can only be defined if $PICR4 = 0 (Deselect Mode)
Start Condition: Any negative transition of the data input line (PB2 or PB3) during an SPICl idle state.
Stop Condition: Any positive transition of the data input line during an SPieL idle state.

MOTOROLA MICROPROCESSOR DATA
3-662

MC68705S3

Table 2. Port B Status During SPI Operation
Port
Name

Use

Input

Output

Comments

PBO
PBO

SPISS
Data

Yes
No

No
Yes

Used as slave select input
Used as "busy" signal or any digital
output

PB1
PB1

SPICl
SPICl

Yes
No

No
Yes

Clock slave
Clock master

PB2
PB2
PB2

SPID
SPID
Data

Yes
No
Yes

No
Yes
Yes

SPI data input SPICRO = 0
SPI data output SPICR3 = 0
Any digital signal SPICR3 = 1

PB3
PB3
PB3

SPID
SPID
Data

Yes
No
Yes

No
Yes
Yes

SPI data input SPICRO = 1
SPI data output SPICR3 = 1
Any digital signal SPICR3 = 0

devices attempted to become masters. Write collisions
normally result from a software error, and the default
master must clean up the system. The mode fault flag is
set to signal that clock mastership is lost. Slave select
actions can take place during either active or idle transaction modes.
Slave Select Input Actions During Slave Mode
The current clock master generates slave select to enable one of sever,al slaves to accept or return data. The
SS signal must go low before serial. clock pulses occur
and must remain low until after the eighth serial clock
cycle~ Individual lines or a daisy chain can be used for
multiple slaves. Wh.en SS is high, the following occur:
• Serial data output is forced to a high-impedance state
without affecting the DDR status.
• Serial clock input pulses are inhibited from generating internal data output and input strobe pulses.
.
• The eight-bit counter is cleared.
SPI OPERATING MODES
Six methods of operating the SPI are discussed in the
following paragraphs.
One-Wire Autoclocked Mode
Various SPI devices can be connect~d on a single wire,
with data .transmission using an implicit clock, and each
device being its own clock master.
Two-Wire Half-Duplex Mode
In this mode, separate data and clock lines connect the
elements in the system. Data and clock mastership should
be monitored via protocol included in the data patterns.
A transmitter can send all zeros to take all other transmitters off the bus.
Three-Wire Half-Duplex Mode with Slave Select Input
This mode is the same as the half-duplex mode except
that the slave select input allows using the MCU as a
peripheral in a system where clock mastership is passed
through the slave select line. Typically, the slave select
lines can be wired together. The current master sets its
slave select line in the output mode priorto a serial trans-

mission and pulls it low to indicate that the system is
busy. This allows the clock master to retain mastership
until the end of transmission. Software protocol can be
arranged so that slaves do not request mastership until
their slave select lines go high. At the end of a transmission, the current master pulls SPISS high and puts the
SPISS port (PBO) in the input mode. A slave requesting
clock mastership pulls the SPISS line low, removing the
current master from the line. Time multiplexed protocols
may be required to avoid simultaneous mastership requests.
Three-Wire Full-Duplex Mode
Thismode.allows the MCU to operate simultaneously
as transmitter and receiver. Bus or daisy-chain networks
are feasible. Protocols in the data stream are required to
change:
• Clock masters
• The number of transmitters in the system
• The direction of data flow in daisy-chained systems
with collision
It is possible for the MCU to shift out one byte of data
while receiving another, as illustrated in Figure 16. This
eliminates the need for XMIT EMPTY or REC FULL status
bits.
Three-Wire Full-Duplex Mode .with Clock Arbitration
This mode is a mix of the three-wire full-duplex mode
and two-wire half-duplex mode with clock arbitration,
where the SPI clock line operates as a wire-or. Simultaneous masters are allowed, .and clock arbitration is via
the clock line.
Four-Wire Full-Duplex Mode with Slave-Select Input
This mode is similar to the three-wire full-duplex mode
in network constructiori and to the three-wire half-duplex
mode with slave-select input in clock arbitration and slave
selection. Refer to Figure 17.

. ANALOG-TO-DIGITAL CONVERTER
The chip resident 8-bit analog-to-digital (AID) converter
uses a successive approximation technique as show in

MOTOROLA MICROPROCESSOR DATA
3-663

II

MC68705S3

VCC

SLAVE SELECT ---....:...--....- - - - - - - - 4 t - - - - - - + - - _ e - - -.....- - - CLOCK -------_.~~--------e-~--------_.~~--------e-~------DATA -~..,

--+
EXAMPLE:

{

INFORMATION FLOW

{

I

B2=SPID IN
B3= SPIC OUT
B2= SPID OUT
B3= SPID IN

Figure 16. Daisy Chain/Cascade Organization
Figure 18. Four external analog inputs can be conr;lected
to the AID through a multiplexer via port D. Four internal
analog .channels (VRH - VRL, VRH - VRL/2, VRH - VRL/4,
and VRLl may be selected for calibration. The accuracy
of these internal channels may not meet the accuracy
specificati'ons of the external channels.
A fifth external analog input (AN4) is available via the
mask option. When selected, it replaces the VRH internal
channel. Due to signal routing, the accur"cy of this fifth
channel may be slightly less than ANO-AN3.
Multiplexer selection is controlled by the AID control
register (ACR) bits 0, 1, and 2. Refer to Table 3 for multiplexer selection. The ACR is shown in Figure 18. The
converter uses 30 machine cycles to complete a conversion of a sampled analog input. When the conversion is

complete, the digital value is placed in the AID result
register (ARR); the conversion flag is set; selected input
is sampled again; and a new conversion begins. When
ACR7 is cleared, the conversion in progress is aborted
and the selected input, which is held internally, is sampled for five machine cycles.
The converter uses VRH and VRL as reference voltages.
An input voltage equal to or greater than VRH converts
to $FF. An input voltage equal to or less than VRL but
greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded. Each analog input
source should use VRH as the supply voltage and be
referenced to VRL for the ratiometric conversion. To
maintain full accuracy of the AID, three requirements
should be followed: (1) VRH should be equal to or less

~

I-- f---4

*HALF DUPLEX

MCU 1

SPID:PB2/3
{ SPICL:PBl

*HALF DUPLEX
{ SPID:PD2/3
WITH CLOCK ARBITRATION
SPICL:PBl

H
MCU 2

-

---4

~
Vc C

*HALF DUPLEX
WITH SLAVE SELECT

*FULL DUPLEX
~

MCU 3

-

---4

Cl

0::
CI)

.....
to)

a::

CI)

*FULL DUPLEX
WITH SLAVE SELECT

Cl

0::
CI)

{

SPID IN:PB2/3
SPID OUT:PB3/2
SPICL:PBl
SPID IN:PB2/3
SPID OUT:PB3/2
SPICL:PBl
{
SPISS:PBO
{

CI)
CI)

a::

CI)

Figure 17. SPI Operation Bus Organization

MOTOROLA MICROPROCESSOR ·DATA
3-664

SPID:PB2/3
SPICL:PBl
SPISS:PBO

MC68705S3

other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following instruction list.

Table 3. AID Input MUX Selection
AID Control Register

ACR2

ACR1

ACRO

Input
Selected

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

ANO
AN1
AN2
AN3
VRH**
VRL*
VRH/4*
VRH/2*

AID Output (Hex)
Min

Typ

Max

Mnemonic

Function

LDA

Load A from Memory
FE**
00
3F
7F

FF**
00
40
80

FF**
01
41
81

*Internal (calibration) levels
** AN4 may replace the VRH calibration channel if selected via
mask option.
than VCe. (2) VRL should be equal to or greater than VSS
but less than maximum specifications, and (3) VRH - VRL
should be equal to or greater than 4 volts.
The AID has a built-in 1/2 LSB offset intended to reduce
the magnitude of the quantizing error to ± 112 LSB, rather
than + 0, -1 LSB with no offset. This implies that. ignoring errors, the transition point from $00 to $01 occurs
at 1/2 LSB above VRL. Similarly, the transition from $FE
to $FF occurs 1-1/2 LSB below VRH, ideally.

INSTRUCTION SET
The MCU has a set of 59 basic instructions which can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type:

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the accumulator or the index register. The

Load X from Memory

LDX

Store A in Memory

STA

Store X in Memory

STX

Add Memory to A

ADD

Add Memory and Carry to A

ADC

Subtract Memory

SUB

Subtract Memory from A with Borrow

SBC

AND Memory to A

AND

OR Memory with A

ORA

Exclusive OR Memory with A

EOR

Arithmetic Compare A with Memory

CMP

Arithmetic Compare X with Memory

CPX

Bit Test Memory with A (Logical Compare)

BIT

Jump Unconditional

JMP

Jump to Subroutine

JSR

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space where
all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear and bit test, and

DIA
CONTROL
LOGIC

15 k (TYP.)

PD5/VRH
PD4/VRL

COUNT

--4-'"

PDDIAND
PD1IANl
PD2/AN2

1-OF-8
SELECT
MULTIPLEXER

PD3/AN3
INT2/PD6/AN4 -'-------~
AID
CONTROL
REG ISTER '--_ _..............L -.......--I........................- '
($DDE)

Figure

18~

AID
RESULT
REGISTER

A/D Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-665

II

MC68705S3

branch functions are all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the carry bit ofthe condition
code register. Refer to the following list for bit manipulation instructions.
Function

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two byte instructions. Refer to the following list for branch instructions.

Mnemonic

Function

BRSEl n (n=O ... 7)

Branch Always

BRA

Branch if Bit n is Clear

BRCLR n (n=O ... 7)

Branch Never

BRN

Set Bit n

BSET n (n=O ... 7)

Branch IFF Higher

BHI

Clear Bit n

BCLR n (n=O ... 7)

Branch IFF Lower or Same

BLS

Branch IFF Carry Clear

CONTROL INSTRUCTIONS

(Branch IFF Higher or Same)

These instructions are register reference instructions
and are used to control processor operation during program .execution. Refer to the following list for control
instructions.

II

Mnemonic

Branch if Bit n is Set

Function

Branch IFF Carry Set
(Branch IFF Lower)

Mnemonic

BCC
(BHS)
BCS
(BLO)

Branch IFF Not Equal

BNE

Branch IFF Equal

BEQ

Transfer A to X

TAX

Branch IFF Half Carry Clear

BHCC

Transfer X to A

TXA

Branch IFF Half Carry Set

BHCS

Set Carry Bit

SEC

Branch IFF Plus

BPL

Clear Carry Bit

CLC

Branch IFF Minus

BMI

Set Interrupt Mask Bit

SEI

Branch IFF Interrupt Mask Bit is Clear

BMC

Clear Interrupt Mask Bit

CLI

Branch IFF Interrupt Mask Bit is Set

BMS

Software Interrupt

SWI

Branch IFF Interrupt Line is Low

BIL

Return from Subroutine

RTS

Branch IFF Interrupt Line is High

BIH

Return from Interrupt

RTI

Branch to Subroutine

BSR

Reset Stack Pointer

RSP

No-Operation

NOP

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.
Function

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Complement

COM

Negate (2's Complement)

NEG

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Logi.;al Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

OPCODE MAP SUMMARY
Table 4 is an opcode map for the instructions used on
the MCU.

ADDRESSING MODES
The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single-byte
instructions, while th~ longest instructions (three bytes)
permit accessing tables throughout memory. Short and
long absolute addressing is also included. Two-byte direct
addressing instructions access all data bytes in most applications. Extended addressing permits jump instructionsto reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

IMMEDIATE
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The

MOTOROLA MICROPROCESSOR DATA
3-666

Table 4. Opcode Map

Bit ManiDullltion

~

~
1
0001

2

0010

3

3:

1~

I JBRSEJ~B
10

cri"
2

BSE~~c
BCL~~c

2

7

4

2 BSE~~c

2

7

4

IJBRCL:~B 2BCL~k
10

I:

BRAREL

..2 BLS

RFI

4

7

4

:2J

I!!
BRCL
3
:1B

7

O~I

2 BCL~~c

2 BCS
REL

I~

7

4

BRSEJ,3B
,0
CL
:,3B

2

n:2J

O~O
7
0111

I~

r

'BRSET4
-BTB
,0
BRCL::a

BSE1~c

> BCC
REI

7

4

2 BCL~~e

>
4

2 BPL
REL

2 DECOlA

2 BEa
REI

7

4

,t,o

~RSEJiB

7

en
en

B
'011

'0
3BRCLR5
BTB

7

:BRSEJ~B

2

C

lfoo
,Po,

,0

7

4

2 BCL~~c

2

~

11~0

o:2J

l>

F

1111

JBRCL:~B

2

BSE~~c

BHC~EL

BHC~EI

7

2

BSE~~e

NEG
1
INH

2 NEG

4

4

IXI

1

COMA
INH

7

6
• NEG
1
IX

1001

"
1
6

RTI

COMX
1

INH

4

4

LSRA
1
INH

LSRX
1
INH

2

COM
IXI

7

1
6

LSR
2

COM

IX

1

IXI

1

4

, RORAINH

4

1

ASRA
INH

4 LSLA

,

INH

4

1

7

4

SWI
INH

2

4

7

'ASRX
1
INH

2 ASR

4

7

1

LSLX
INH '2

4

ROLA
INH

4

, DECAINH

ROR

2
7

DECX
INH

LSL

ASR

IXI

1
6

IXI

1
6

ROL
DEC
2

IXI

,

LSL

IX

1
2

DEC

IX
IX

2

BM~EL
BM~EL

6
2

INC
DIR
6
2 TST
DIR

4

4

7

4

4

7

, INCAINH , INCXINH
TSTX
TSTA
1
INH ,
INH

6

INC
IXI

2

2

IX'

2

1

IX

3

o SBC
3
EXT

CPX
DIA

5 CPX
3
EXT

2 AND
DIR

AN~XT

2

4

CLR

DIA

1

4

CLRA
INH

, CLRXINH

7

CLR
2

IX_~

6
CLR
,-,1_'_'_,IX

2
4

2
4

4

LOA
>
DIR

LOA
J
EXT

2
>

i

2
1
2

SEI

BIT DIA

STADIA

REl
BSC
BTB
IX
IX1
IX2

Inherent
Immediate
Direct
Extended
Relative
Bit Set/Clear
Bit Test and Branch
Indexed (No Offset)
Indexed, 1 Byte (8-Bit) Offset
Indexed, 2 Byte (16-Bit) Offset

BI\XT

SUB

IX1

5
CMP

4

CMP

~1

IX2

2 CMP
IXI

I

o SBC
3
IX2

o SBC
2
IXI

• SBC
1
IX

rJ,.o.

5,CPX
2
IXI

• CPX
1
IX

~,

:

• AND
I
IX

o~

6 CPX
3
IX2

o

_

3 ANDIX2

AND
IX1

IX

4

: BIT IX> : BIT IX'
6
5
3 LDA ' 2 LDA
Ix2
IXI

BIT IX
4

X

o~o

o STA
1
IX

m~1

IX2

5 EOR
2
IX,

• EOR
1
IX

I~

• ADC
IX2
3

o ADC
2
IX'

•

,

IX

,00,

I

2 EOR
DIA

ADC
IMM

2

ADC
DIR

ORA
IMM

• ORA
DIR
2

o ORA
EXT
3

o ORA
3
IX2

o ORA
2
IX'

•

, ORA IX

A
,0,0

4 ADD

5 ADD
3
EXT

6 ADD
3
1X2

5 ADD
2
. IXI

., ADD

,

IX

B
,011

o JMP
3
1X2

• JMP
2
IX,

IX

C
1100

a JSR

4
4

2

INH

2 ADD
2
IMM

2DIR
3
JMP
2
DIR

4

3

JMP
EXT

6
3 EOR

~

ADC

JMP

I

JSR
2
DIR

a JSR
EXT

" JSR
J
IX2

IXI

I

IX

I~

LOX
IMM

• LOX
2
DIR

o LOX
3
EXT

• LOX
3
1X2

o LOX
2
IXI

•
I

IX

E
1110

STX

6 STX
IX,
2

o STX
I
IX

1111

J

5 STX
6 STX
EXT
DIll. -.l.
, __ ,--2

7

3

-

IX2

2

LOX

-I

9

BSR
AEL

JSR

i

o~,

o STA
,
IXI
IX2 ..2.

3. STA

LOA

EO~MM

F

LEGEND

Abbreviations for Addreu Modes
INH
IMM
DIR
EXT

:

IX2

: ST"EXT
5
3 EOR
EXT
5
ADC
J
EXT

INH

TXA
INH

2

~

Cli

I,

4

BI~MN

LOA
2
IMM

,

2
- - -

:
5

2

2
6

AEL

4

SUB

6

J
5

'2

BIH

~

:

SBC
DIA

, RSPINH
2
, NOPINH2B

IX

Hi~1

• SUB
1
IX

SU~XT

CMP
EXT
3

2

BILREL

4

BCLR7
sse

INC
TST

TST
2

1
6

1,'i,

CMP
2
DIR

SEC
INH

1
2

IX

11~0

4

2

2
ROL

1X1

1~

CMP
IMM
2
2
2 SBC
IMM
2
CPX
IMM
2
2

TAX
INH
CLC
INH

IX

SUB
DIR

DC

lfoo

2

2

6

1
6

:

_ 2 AN?MM
2

IX

, ROR IX

IX'

7

, ROLXINH

4

1

IXI

SU~MN

IMemorv

_EXT

:
5

7

6

RORX
1
INH

,:"

A
1010

INH

LSR

Oil!

JMM

9

11

6

4

BSE~1e

7

2

7

1000

BMI
REL

4

10

4

Qj~'

4

2BCL~e .2

JBRSEJIB
10
BRCLR7
3
BTB

NEG
INH

01~Jl

JttIi

8

7

>

2 BCL~~c

'001

m

6
2 COM
DIA
6
LSR
2
DTR

BSE1~e

2 BNEREL
4

7

2

I

o,~,

!NIi

RTS
INH
1

6
2 ROR
DIA
6
2 ASR
DIR
6
2 LSL
DIR
6
ROL
2
DIR
6

BSE1~c

m o"'a
~ :2J
o
(')

9

NEG
DIR

c»~

,....

Control
IX

BHIREI

2

3:

:

4

Read-Modify-Write
INH
IXl

BR~EL

I JBRSEJ1B

5:

INH

OO~,

J,o

o
o

DIR

4

7
2

REL

4
0100

a
w

0011

~
I :BRSEJfB
10
13BRCLRO
BTB

Brench

BS(

BTB

F
, MnemOniC
of Cy""
Bytes

j

4.1

oil

..

1 ;r

IX,

Opcode in HexadeCimal

Opcode in Binary

lXllJ----

'-------...,.....-- Address Mode

s::

~
.....
o
U'I

t/)

W

MC68705S3

immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).

tables may begin anywhere within the first 256 addressable locations and could .extend as far as location 510
($1 FE is the last location at which the instruction may
begin).

DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.

EXTENDED
In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction.

RELATIVE
The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from - 126 to + 129 from
the opcode address.

INDEXED, NO. o.FFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first
256 memory locations. These instructions are only one
byte long. This mode is often used to move a pointer
through a table or to hold the address of a frequently
referenced RAM or I/O location.

INDEXED, 8-BIT o.FFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
the beginning of the table in the instruction. As such,

INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the two unsigned bytes following
the opcode. This addressing mode can be used in a mannersimilar to indexed 8-bit offset except that this threebyte instruction allows tables to be anywhere in memory.

BIT SET/CLEAR
In the bit set clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte to which
the specified bit is to be set or cleared. Thus, any read;
write bit in the first 256 locations of memory, including
I 0, can be selectively set or cleared with a single twobyte instruction.

BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit to be tested, and its condition (set or clear), is included
in the opcode. The address of the byte to be tested is in
the single byte immediately follawing the opcode byte.
The signed relative 8-bit offset in the third byte is added
to the PC if the specified bit is set or cleared in the specified memory lacation. This single three-byte instruction
allows the pragram to branch based on the condition of
any readable bit in the first 25610catians of memory. The
span of branching is from -125 to. + 130 from the opcode
address. The state of the tested bit is also transferred to
the carry bit of the candition code register.

INHERENT
In the inherent addressing mode, all the information
necessary to execute the instructian is contained in the
opcode. Operations specifying only the index register ar
accumulator as well as the control instruction with no
ather arguments are included in this mode. These instructions are one byte long.

MOTOROLA MICROPROCESSOR DATA
3-668

MC68705S3

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage

Symbol

Value

Unit

VCC

-0.3 to +7.0

V

PCO in
Self·Check Mode
All Other

Vin

Port A and C Source Current per Pin
(One at a Time)

lout

Operating Temperature Range
MC68705S3S
MC68705S3CS

TA

Storage Temperature Range
Junction Temperature
Cerdip

V
-0.3to+15.0
-0.3to +7.0
mA
10
"C

o to 70
-40 to +85

Tsto

- 55 to + 150

This device cont.ains circuitry to, protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to this high-impedance
circuit. For proper operation, it is recommended the Vin and Vout be constrained to
the range VSS ~ (Vin or Vout) ~ VCC. Reliability of operation is enhanced if unused inputs except EXTAL are tied to an appropriate
logic voltage level (e.g., either VSS or VCC).

"C
"C

TJ
175

THERMAL CHARACTERISTICS

I

Characteristic

I Thermal Resistance

Symbol

Value
60

Cerdip

POWER CONSIDERATIONS

The average chip-junction temperature, TJ' in °c can
be obtained from:'
TJ=TA+(POoeJA)
(1)
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance,
flJA
Junction-to-Ambient, °C/W
Po
= PINT+ PpORT
= ICCxVCC' Watts - Chip Internal Power
PINT
PPORT = Port Power Oissipation,
Watts - User Oetermined

VCC=4.75 V

For most applications,PpORTICl lead Time
Start Bit to First Clock lead Time

_.

tcyc

AID CONVERTER CHARACTERISTICS
(VCC = + 5.25 Vdc ± 0.5 Vdc, VSS = 0 Vdc, TA = Tl to TH, unless otherwise noted)
Min

Typ

Max

Unit

Resolution

Characteristic

8

8

8

Bits

Non-Linearity*

-

-

±1/2

lSB

Quantizing Error

-

-

::!:1/2

lSB

Conversion Range
VRH
VRl

-

VCC
0.2

V

VSS

30

tCYC

Conversion Time

30

30

Monotonicity

After removing zero-offset and full-scale errors

AID accuracy may decrease proportionately as
VRH-VRl is reduced below 4.0 V. The sum of
VRH and VRl must not exceed VCC
Includes sampling time

(Inherent within total error)

Sample Time

5

Sample/Hold Capacitance, Input

-

Analog Input Voltage

Comments

5

VRl

5

tCyc

-

25

pF

-

VRH

V

Transients on any analog lines are not allowed
at any time during sampling or accuracy may
be degraded

*For VRH = 4.0 V to 5.0 V and VRl = 0 V.

MOTOROLA MICROPROCESSOR DATA
3-671

II

MC68705S3

PORT ELECTRICAL CHARACTERISTICS
(VCC= +5.25 Vdc ::!:0.5 Vdc, VSS=O Vdc, TA=TL to TH, unless otherwise noted)
Symbol

Characteristic

Min

Typ

. Max

Unit

Port B
Output Low Voltage, ILoad=3.2 mA

VOL

-

-

0.4

V

Output Low Voltage, 'Load = 10 mA (Sink)

VOL

-

-

1.0

V

Output High Voltage, 'Load = - 200 f.l.A

VOH

2.4

8

-

Darlington Current Drive (Source)*, Vo = 1.5 V

IOH

-1.0

-

-10

mA

Input High Voltage

V,H

2.0

-

VCC+O.7

V

Input Low Voltage

V,L

VSS

-

0.8

V

-

<2

10

f.LA

Hi-Z State Input Current

'TS'
Port C and Port A
VOL

-

-

0.4

V

Output High Voltage, 'load = -100 f.l.A

VOH

2.4

-

-

V

Input High Voltage

V,H

2.0

-

VCC+0.7

Input Low Voltage

Vll

VSS

-

0.8

V

-

<2

10

f.LA

V

Output Low Voltage, ILoad = 1.6 mA

I

V

Hi-Z State Input Current

'TS'
Port D (Digital Inputs Only)

V

. Input High Voltage

V,H

2.0

-

VCC+O.7

Input Low Voltage

V,l

VSS

-

0.8

V

Input Current**

lin

-

<1

10

f.LA

*Not applicable if programmed to open-drain state.
**PD4NRL - PD5NRH.
The AID conversion resistor (15 kH typical) is connected internally between these two lines, impacting their use as digital inputs
in some applications.

ORDERING INFORMATION
The following table provides generic information pertaining to the package type, temperature, and MC order numbers
for the MC68705S3.

Table 5. Generic Information
Package Type
Cerdip
(S Suffix)

Temperature

Order Number

O°C t() 70°C
- 40°C to + 85°C

MC68705S3S
MC68705S3CS

MOTOROLA· MICROPROCESSOR DATA
3-672

MC68705S3

MECHANICAL DATA

PIN ASSIGNMENTS

NUM

VSS
PRESCALERl/PCO

2

EXTAL
XTAL

PRESCALER2/PCl

3

VSTByl AN4/1NT2/PD6

4

INTl

VRH/PD5

5

VDD

AN3/PD3

7

RESETlVpp
PA7
PA6
PA5
PA4

ANO/PDO
SPISS/PBO

11

PA3

SPICLlPBl

PA2

SPID/PB2

PAl

SPID/PB3

PAO

MOTOROLA MICROP.ROCESSORDATA
3-673

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MC68705U3

Technical Summary

8-Bit EPROM Microcontroller Unit
The MC68705U3 (HMOS) Microcontroller Unit (MCU) is an EPROM member of the MC6805 Family
of microcontrollers. The user programmable EPROM allows 'program changes and lower volume
applications. This low cost MCU has parallel 110 capability with pins programmable as input or output. This publication contains condensed information on the MCU; for detailed information, refer to
M6805 HMOS, M146805 CMOS Family User's Manual (M6805UM(AD2)) or contact your local Motorola sales office.
Refer to the block diagram for the hardware features and to the list below for additional features
available on the MCU.

II

•

Internal 8-Bit Timer with 7-Bit
Programmable Prescaler

•
•
•

On-chip Oscillator
Memory Mapped 1/0
Versatile Interrupt Handling

•

Bit Manipulation

•
•
•

Bit Test and Branch Instruction
Vectored Interrupts
Bootstrap Program in ROM

•
•

112 Bytes of RAM
3776 Bytes of EPROM

•

24110 Pins

BLOCK DIAGRAM

RESET VPP INT

TIMER

Accumulalor
Pori
A
I/O
LInes

Dala
Dir

POri
B

Dala

110

Reg

Reg

Dir

LInes

3776 x8
EPROM
19 x

8

A

X
Condlilon
Code
Reglsler CC

Port
D
Input
Lines

CPU
ContrOl

Index
Reglsler

pca

CPU

Slack
POlnler

SP
Program
Counler
HIgh PCH

ALU

Program
COllnler
Low
PCL

PCl
PC2
PC3
PC4
PC5
PC6
PC7

BOOISlra~

ROM

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA
3-674

Port
C
I/O
Lines

MC68705U3

SIGNAL DESCRIPTION
VCC AND VSS

Power is supplied to the microcontroller using these
two pins. Vee is + 525 volts (± O.5M power, and VSS is
ground.
Vpp

This pin is used when programming the EPROM. In
normal operation, this pin is connected to Vee.
INT

This pin provides the capability for asynchronously applying on external interrupt to the M'eU. Refer to INTER·
RUPTS for more detailed information
EXTAL,XTAL

These pins provide control input for the on-chip clock
oscillator circuit. A crystal, a resistor/capacitor combination, or an external signal (depending on mask option
register setting) is connected to these pins to provide a
system clock.

C' t:J-

RC Oscillator
With this option, a resistor is connected to the oscillator
pins as shown in Figure 1. The relationship between R
and fosc is shown in Figure 2.
Crystal

The circuit shown in Figure 1 is recommended when
using a crystal. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and startup stabilization time, Refer to ELECTRICAL SPECIFICATIONS for Vee
specifications.
External Clock

An external clock should be applied to the EXTAL input
with the XTAL input connected to VSS, as shown in Figure 1, This option may only be used with the crystal
oscillator option selected in the mask option register,
TIMER
This pin is used as an external input to control the
internal timer/counter circuitry. This pin also detects a

C,

EXTAL

5

~

6

S . XTAL

6

ISee Note 2) c::::J

XTAL

MCU
5 EXTAL (Crystal Option,
See Note 1)

AT - Cut Parallel Resonance Crystal
Co = 7 pF Max
Freq.=4.0 MHz@ CL =24 pF
RS = 50 ohms Max

Crystal

Piezoelectric. ceramic resonators which
have the equivalent specifications may be
used instead of crystal oscillators. Follow
ceramic resonator manufacturer's suggestions for CO, C1, and RS values

VCC
-vv'V-_6-i XT AL
6 XTAL

6 XTAL
External
Clock
Input

5

EXTAL

MCU
(Crystal Option,
See Note 1)

External Clock

5 EXTAL

MCU
(RC Option,
See Note 11

Approximately 25% to 50% Accuracy
Typical tcyc= 1.251's
External Jumper

5 EXTAL
No
Connection

MCU
(RC Option,
See Note 11

ApprOXimately 10% to 25% Accuracy
(Excludes ReSistor Tolerancel
External ReSistor

NOTES:
1. For the MC68705U3 MaR b7 = 0 for the crystal option and MaR b7 = 1 for the RC option, When the TIMER input pin is in the
VIHTP range (in the bootstrap EPROM programming mode). the crystal option is forced, When the TIMER input is at or below
VCC, the clock generator option is determined by bit 7 of the mask option register (ClK).
2, The recommended Cl value with a 4.0 MHz crystal is 27 pF maximum, including system distributed capacitance, There is an
internal capacitance of approximately 25 pF on the XTAl pin, For crystal frequencies other than 4 MHz, the total capacitance on
each pin should be scaled as the inverse of the frequency ratio, For example, with a 2 MHz crystal, use approximately 50 pF on
EXTAl and approximately 25 pF on XTAL The exact value depends on the motional-arm parameters of the crystal used,

Figure 1. .oscillator Connections

MOTOROLA MICROPROCESSOR DATA
3-675

II

MC68705U3

8.0
7.0

~

~

6.0
VCC=525V
TA=25°C

g 50
~

I40
~

Q

3.0
2.0

0
10
0

0

10

20

30

40

50

60

70

80

Resistance IkOl

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only

I

higher voltage level used to initiate the bootstrap program.

data direction register (DDR). Port D is input only. The
port 110 programming is accomplished by writing the
corresponding bit in the port DDR to a logic one for output
and a logic zero for input. On reset, all the DDRs are
initialized to a logic zero state to put the ports in the input
mode. The port output registers are not initialized on
reset and should be written to before setting the DDR
bits.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Care must
be exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (zero) and, also, corresponds to the latched
output when the DDR is an output (one). Refer to Table
1 for 110 functions and to Figure 3 for typical port circuitry.

RESET
This pin has a Schmitt trigger input and an on-chip
pullup. The MCU can be reset by pulling RESET low.
INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO-PC7, POOP07)
These 32 lines are arranged into four B-bit ports (A, B,
C, and D). Ports A, B, and C are programmable as either
inputs or outputs under softwC!re control of the data direction registers. Port D is a fixed in~ort. Port D bit 6
may be used for a second interrupt (lNT2). Refer to PROGRAMMING for additional information.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
Port A, B, and C pins are programmable as either input
or output under software control of the corresponding

NOTE
Read-modify-write instructions should not be used
when writing to the DDRs, because DDRs always
read as 'one'.

Table 1. I/O Pin Functions
Data
Direction
Register
Bit

Latched
Output
Data
Bit

Output
State

Input
To
MCU

1
1
0

0
1
X

0
1
Hi-Z**

0
1
Pin

**Ports Band C are three-state ports. Port A has an internal
pullup devices to provide CMOS data drive capability.

·DDR is a write-only register and reads as. all "'.s"

Figure 3. Typical Port I/O Circuitry and
Register Configuration

MOTOROLA MICROPROCESSOR DATA
3-676

MC68705U3'

MEMORV

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may be added to an 8- or 16- bit immediate value to create
an effective address. The index register mayalso be used
as a temporary storage area.

The MCU is capable of addressing 4096 bytes of memory and 1/0 registers. The memory map is shown in Figure
4. The locations consist of user EPROM, bootstrap ROM,
user RAM, a mask option register (MOR), a program control register, and .1/0. The interrupt vectors are located
from $FF8 to $FFF. The bootstrap is a mask-programmed
ROM that allows the MCU to program its own EPROM.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer
decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.

7

x
PROGRAM COUNTER (PC)
The program counter is a 12-bit register that contains
the address of the next byte to be fetched.
11

NOTE
Using the stack area for data storage or temporary work
locations requires care to prevent it from' being overwritten due to stacking from an interrupt or subroutine
call.

PCl

STACK POINTER (SP)
The stack pointer is a 12~bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pOinter
is then decreme,nted as data is pushed onto the stack and
incremented as data is pulled from the stack.
The seven most-significant bits 9f the stack pointer are
permanently set at 0000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to 15
le"el50f subroutine calls (less if interrupts are allowed).

REGISTERS
The MCU contains the registers described in the following paragraphs.
ACCUMULATOR, (A)
The accumulator isa general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.
7

"

A

5 4

1 0 1 0 10 1 0 10 I, I, I

Page Zero
Access With
Short
Instructions

!

000
127
128

76543210
$000

I/O Ports Timer
and
RAM'
(128 Bytes)

$07F
$000

Page Zero
User EPROM

255 _ _
256

'E8~t~

,... _

~:OFF

$100

: User
Main
EPROM
(3640 Bytes)

3895

3896
3897
3967

3968

,

t--...,.---Mask Option Register
Not Used
Bootstrap
ROM
, (120 Bytes)

=r.-------.=
(
.4(lI9

Timer Interrupt

4092

4093

"

4094

4095

$F37
$F38
$F39
$F7F
$F80

0

Port A Data Register

$000

1

Port B Data Register

Sool
$002

2

Port C Data Register

3

Port 0 Data Register

$003

4

Port A DDR*

$004

5

Port B DDR*

$005

6

Port C DDR*

$006

7

Not Used

S007

8

Timer Data f'legister

$008
$009

9

Timer Control Register

10

Miscellaneous Register

$ooA

11

Program Control Register

$ooB

12
15
16

Not Used

SWI

r.------RESET

$ooC-$ooF

$010

$FF7
$FF8

RAM
(112 Bytes)

$FF9

~----.:....- $FFA
External Interrupt

Interrupt.
Vectors

,

8 7

PCH

Stack,
(31 Bytes Maximum)

$FFB
$FFC
$FFD
$FFE
$FFF

127

t

·Caution: Data direction registers !DDRs) are write-only; they read' as SFF,

Figure 4. Memory Map

MOTOROLA MICROPROCESSOR DATA
3-677

$07F

0

sp

I

II

MC68705U3

CONDITION CODE REGISTER (CC)

POWER-ON-RESET (POR)

The condition code register is a 5-bit register in which
four bits are used to indicate the results of the instruction
just executed. These bits can be individually tested by a
program, and specific ,actions can be taken as a result of
their state. Each bit is explained in the following paragraphs.

An internal reset is generated on power-up that allows
the internal clock generator to stabilize. The power-on
reset is used strictly for power turn-on voltatge. A delay
oftRHL milliseconds is required before allowing RESET
input to go high. Connectiriga capacitor to the RESET
input (Figure 5) typically provides sufficient delay.

4

0

I I I Iz Ic I
H

N

-

1

Half Carry (H)

VCC--~j'~. __~----_

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)

I

:r: 10/LF

(MCU)

When this bit is set, the timer and external interrupt is
masked (disabled). If an external interrupt occurs while
this bit is set, the interrupt is latched and is processed as
soon 'as the interrupt bit is cleared.
Figure 5. Power-Up RESET Delay Circuit

Negative (N)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative (bit
7 in the result is a logic 1).

EXTERNAL RESET INPUT

The MCU is reset when a logic zero is applied to the
RESET input for a period longer than one machine cycle
(tcyel. Under this type of reset, the Schmitt trigger switches
off at VIRES - to provide an internal reset voltage.

Zero IZ)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.

INTERRUPTS

Carry/Borrow (C)

When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and. during shifts and
rotates.

The MCU can be interrupted four different ways: (1)
through the external interrupt INT input pin, (2) with the
internal timer interrupt request, (3) using the software
interrupt instruction (SWI), or (4) the external Port D (lNT2)
input pin.
Interrupts cause the processor registers to be saved on
the stack and the interrupt mask (I bit) set to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack after which
normal processing resumes. The stacking order is shown
in Figure _6_.__
Unlike RESET, .hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.

RESETS
The MCU can be reset two ways: by initial power-up
and by the external reset input (RESET). The RESET input
consists mainly of a Schmitt trigger that senses the line
logic level.

6

n-4

I

1

1

4

I

1

I

n-2

1

Pull

n+l
n+2

Accumulator

n-3

n-l

o

2
Condition Code Register

Index Register

I

1

1

I

1

I

1

I

n+3

PCL*

Push

* For subroutine calls. only PCH and PCL are stacked.

Figure 6. Interrupt Stackil'lg.Order

MOTOROLA MICROPROCESSOR DATA

3·678

n+4

PCH* '

.

n+5

j

MC68705U3

NOT~

condition code register (CCR) is also cleared. When the
interrupt is recognized, the current state of the machine
is pushed onto the stack and the I bit in the CCR is set,
masking further interrupts until the present one isserviced. The contents of the timer interrupt vector, containing the location of the timer interrupt service routine, is
then loaded into the program counter. At the end of the
timer interrupt service routine, the software normally executes an RTI instruction which restores the machine state
and starts executing the interrupted program. The timer
interrupt statu~ bit can only be cleared by software.

The current instruction is considered to be the one
already fetched and being operated on.
When the current instruction is complete, the processor
checks all pending hardward interrupts and, if unmasked
(I bit clear), proceeds with interrupt processing; otherwise, the nextinstruction iffetched and executed. Masked
interrupts are latched for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 7 for the reset and interrupt
instruction processing sequence.
TIMER INTERRUPT

If the time mask bit (TCR6) is cleared, then, each time
the timer decrements to zero (transitions from $01 to $00),
an interrupt request is generated. The actual processor
interrupt is generated only if the interrupt mask bit of the

EXTERNAL INTERRUPT

, The external interrupt is internruJy synchronized and
then latched on the falling edge of I NT and INT2. Clearing
the I bit enables the external interrupt. ThelNT2 interrupt
has an interrupt request bit (bit 7) and a mask bit (bit 6)
in the miscellaneous register (MR). The INT2 interrupt is
inhibited when the mask bit is set. The INT2 is always
read as a digital input on port D.The INT2 and timer
interrupt request bits, if set, cause the, MCU to process
an interrupt when the condition code I bit is clear. The

1.1 (in CC)

07F. SP
O.DDRs '
CLR INT Logic

FF. Timer
TCR6.1
TCR7.0

Load PC From:
SWI: FFC/FFD
INT: FFA/FFB
Timer or
INT2: FFB/FF9

Load Options From
MOR ($F38) Into
Control Logic

Figure 7. Reset and Interrupt Processing Flowchart

MOTOROLA MICROPROCESSOR DATA
3-679

II

MC68705U3

following paragraphs describe two typical extemal interruptcircuits.

MC68705P3/R31U3 8-8ft EPROM Microcomputer Programming Module (AN-8571D Rev. 2).

Zero-Crossing Interrupt.
A sinusoidal input signal (fINT maximum) can be used
to generate an exter'nal interrupt (see Figwe8a) for use
as a zero-crossing' detector (for negative transitions 'of
the ac sinusoid). This type of circuita'ilows applications
such as servicingtime-of-day ro'utines and engaging/disengaging ac power control devices. Off-chip, full-wave
rectification provides an interrupt at every zero crossing
of the ac signal and, thereby, provides a 2f clock.

TIMER
The MCU consists of an 8-bitsoftware programmable
counter driven bya 7-bit software programmable prescaler. The various timer sources are made via the timer
control register (TCR) and/or the mask option register
(MOR). The 8-bit counter may be loaded under program
control and is decremented toward zero. When the timer
reaches :zero, the timer interrupt request bit (bit 7) in the
timer control register (TCR) is set. Refer to Figure 9 for
timerbldck diagram.
The timer interrupt can be masked (disabled) by setting
the timer interrupt mask bit (bit,6) in the TCR. When the
I bit in the condition code register is cleared and the TCR
bit 6 is cleared, the processor receives the interrupt. The
MCU responds to this interrupt by (1) saving the present
CPU state on the stack, (2) fetching the timer interrupt
vector, and (3) executing the interrupt routine. The timer
interrupt request bit must be cleared py software. Refer
to RESETS and INTERRUPTS for additional information.
The prescaler is a 7-bit divider which is used to extend
the maximum length of the timer. To avoid truncation
errors, the prescaler is cleared when TCR bit 3 is set to
a logic one; however, the TCR bit 3 always reads as a
logic zero to ensure proper operation with read-modifywrite instructions.
The timer continues to count past zero, falling from $00
through $FF, and continues the, countdown. The counter
can be read at any time by reading the timer data register
(TDR). This allows a program to determine the length of
time since a timer interrupt has occurred without disturbing the counting process. TheTDR is unaffected by
.,
reset.

Digital-Signal Interrupt
With this type of circuit (Figure 8b), the INT pin can be
driven, by a digital signal. The maximum frequency of a
signal that can be recognized by the TIMER or INT pin
logic is dependent on the parameter labeled tWL, tWH·
Refer to TIMER for additional information."

II

SOFTWARE INTERRUPT (SWI)
TheSWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. The SWI
execution is similar to the hardware interrupts.

MODES OF OPERATION
The MCU has two modes of operations: normal and
bootstrap. The following paragraphs describe these
modes.
NORMAL MODE
This mode is a single-chip mode and is entered if the
following conditions are met: (1) the RESET line is low,
(2) the PCO pin is within its normal operational range,
and (3) the V~ is connected to VSS. The next rising
edge of the RESET pin then causes the part to enter the
normal mode.
BOOTSTRAP
The bootstrap mode is entered if the TIMER pin is equal
to + 12 V. For more information refer to application note,

SOFTWARE CONTROLLED MODE
This mode is selected when TOPT (bit 6) in the MOR
is programmed to zero. The timer prescaler input can be
configured for three different operating modes plus a
disable mol:ie, depending on the value written to TCR
.control bits 4 and 5 (TIE and TIN). The following paragraphs describe the different modes.

(b) Digital-Signal Interrupt

(a) Zero-Crosaing Interrupt

Vee
ac
Input

TTL

ICurrent
,

Max,)~'mit'ng)
.
..

ItlNT
Asl MO
aclnput!S
10 Vac pop

R.
.

2 iNT

4.7 k

Level
2
Dlgltal--....---t

MCU

Input

0.1-1.0
"F

iNT
MCU

lJ·-~Figure 8. Typical Interrupt Circuits

MOTOROLA MICROPROCESSOR DATA
3-680

EPROM

8
Timer Data Register (TOR)
8-Bit Counter

3:

0
-t
0
::D
0

Co)

0,

...

CO

;1
£

Timer
Pin
7-Blt Prescaler

0

"'tJ

Select

~_ _ _ _ _ _ _---411-of-8

::D

0

3:
(")
en
co
Timer Control Register (TCA)

m

Internal
",2
Clock
(fosc+ 4 )

3

~

fplN - Prescaler Input Frequency
fClN- Counter Input Frequency

.....
o

c.n
w

C

Clear

n

II

Set

Timer Control Register Bits:
TIR - Timer Interrupt Request Status
TIM -- Timer Interrupt Mask
TIN - Timer Input Select
TIE- Timer External Input Enable
PSC - Prescaler Clear
PS2, PS1, PSO~ Prescaler Select

Figure 9. Timer Block Diagram

Mask Option Register Bits
CLK - Clock Oscillator Type
TOPT- Timer Maskl Programmable Option
CLS - Timer Clock Source
(TIE) - (Timer External Input Enable)
SNM,...,. Secure/Non-Secure Mode Option
P2, Pl, PO- Prescaler Option

MC68705U3

Timer Input Mode 1
When TIE and TIN are both programmed to zero, the
timer input is from the internal clock (phase two) and the
timer input pin is disabled. The internal clock mode can
be used for periodic interrupt generation as well as a
reference for frequency and event measurement.
Timer Input Mode 2
When TIE = 1 and TIN = 0, the internal clock and the
timer input signalsare ANDedto form the timer input.
This mode can be used to measure .external pulse widths.
The active high, external pulse gates in the internal clock
for the duration of tile external pulse. The accuracy of
the count is ±1.
Timer Input Mode 3
When TIE = 0 and TIN = 1, no prescaler input frequency
is applied to the prescaler and the timer is disabled.

I

Timer Input Mode 4
When TIE andTIN are both one, the timer input is from
the external clock. The external clock can be used to count
external events as well as to provide an external frequency for generating periodic interrupts. Frequency of
external input must be :;s; fosc/8.
MOR CONTROLLED MODE
This mode is selected when TOPT (bit 6) in the MOR
is programmed to logic one. The timer circuits are the
same as described in SOFTWARE CONTROLLED MODE.
The logic levels of TCR bits 0, 1,2, and 5 are determined
during EPROM programming by the same bits in the MOR.
Therefore, bits 0,1,2, and 5 in the MOR control the prescaler division and the timer clock selection. TIE (bit 4) and
PSC (bit 3) in the TCR are set to a logic one when in the
MOR controlled mode.· TIM (bit 6) and TIR (bit 7) are
controlled by the counter and software.
'

TIR - Timer Interrupt Request
Used to indicate the timer interrupt when it is logic
one
1 = Set when the timer data register changes to all
zeros
0= Cleared by external reset, power-on reset, or
under program control
TIM - Timer Interrupt Mask
Used to inhibit the timer interrupt
1 = Interrupt inhibited
0= Interrupt enabled
TIN - External or Internal
Selects input clock source
1 = External clock selected
0= Internal clock selected (fosc/4)
TIE - TIMER External Enable
Used to enable external TIMER pin. When TOPT = 1,
TIE is always a logical "one".
1 = Enables external timer pin
0= Disables external timer pin
PSG -::- Prescaler Clear
Write only bit. Writing a one to this bit resets the
prescaler to zero. A read of this location always indicates a zero when TOPT=O. When TOPT= 1, this
bit will read a logical "one" and has no effect on the
prescaler.
PS2, PS1, PSO - Prescaler Clear
Decoded to select one of eight outputs of the prescaler
Prescaler

TIMER CONTROL REGISTER (TCR) $009
This is an 8-bit register that controls various functions
such as configuring operation mode, setting ratio ofthe
prescaler, and generating timer interrupt request signal.
All bits are read/write except bit 3. The configuration of
the TCR is determined by the TOPT (bit 6) in the MOR.
When TOPT = 1, the TCR emulates the MC6805U2; when
TOPT = 0, the TCR is controlled by software.
TCR with MOR TOPT = 1
7
6

I

TIR

I

TIM

TIR

I

TIM

PSC

TIN

0

0

0

1

0

0

1

2

Divide By

0

1

0

4

0

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

1

1

1

128

NOTES
When changing the PS bits in software, the PSC
bit should be written to a "one" in the same write
cycle to clear the prescaler. Changing the PS bits
without clearing the prescaler may cause prescaler
truncation.

TIE

PSC

PS2

PSl

PSO

I
u

PSO

The MOR is implemented in EPROM, This register contains all zeros prior to programming and is not affected
by reset. The MOR bits are described in the following
paragraphs.

RESET:

o

PS1

MASK OPTION REGISTER (MOR) $F38

I

TCR with MOR TOPT=O
7
6
5

I

PS2

u

u

u

u

u

*The value of corresponding bits in MOR is written during RESET rising
edge. These bits always read 'one',

7

6

ClK

I TOPT I

ClS

ClK - Clock (oscillator type)
1 = Resistor Capacitor (RC)
0= Crystal

MOTOROLA MICROPROCESSOR DATA

3·682

P2

Pl

PO

MC68705U3

TOPT - Timer Option
1 = MC6805U2 type timer/prescaler. All bits except
6 and 7, of the TCR are invisible to the user.
Bits 5, 2, 1, and 0 of the MOR determine the
equivalent MC6805U2 mask options.
0= All TCR bits are implemented as a software programmable timer. The state of MOR bits 5, 4,
2, 1, and 0 sets the initial values of their respective TCR bits.
CLS - Timer/Prescaler Clock Source
1 = External TIMER pin
0= Internal clock
Bit 4
Not used if TOPT = 1. Sets the initial value of TIE in
the TCR if TOPT = O.
1 = Not used
0= Sets initial value of TIE in the TCR
Bit 3
Not used
P2, P1, PO
The logical levels of these bits, when decoded, select
one of eight outputs on the timer prescaler.
Prescaler
Divide By
P2
Pl
PO
0

0

0

1

0
0

0

1

2

1

0

4

0

1

1

8

1

0

0

16

1

,

0

,

1

32

0

64

1

1

1

128

7

u

u

u

u

NOTE
VPON being "zero" does not indicate that the Vpp
level is correct for programming. It is used as a
safety interlock for the user in the normal operating
mode.
VPON

PGE

PLE

Programming Conditions

0

0

0

Programming mode (program
EPROM byte)

1

0

0

PGE and PLE disabled from
system

0

1

0

Programming disabled (latch
address and data in EPROM)

1

1

0

PGE and PLE disabled from
system

0

0
0

1

Invalid state; PGE=O if PLE=O

1

1

Invalid state; PGE=O if PLE=O

0

1

1

"High voltage" on Vpp

1

1

1

PGE and PLE disabled from
system (operating mode)

EPROM PROGRAMMING

PROGRAMMING CONTROL REGISTER (PCR) $OOB
The PCR is an 8-bit register which provides the necessary control bits to program the EPROM. The bootstrap
program manipulates the PCR when programming so the
user need not be concerned with PCR in most applications.

RESET:
U

1 = No high voltage on Vpp pin
0= High voltage on Vpp pin

u

PLE - Programming Latch Enable
Controls address and data being latched into the
EPROM. Set during reset, but may be cleared anytime.
1 = Read EPROM
0= Latch address and data on EPROM
PGE - Program Enable
Enables programming of EPROM. Must be set when
changing the address and data. Set during reset.
1 = Inhibit EPROM programming
_
_._O=Enable EPROM programming (if PLE is low)
VPON - Vpp On
A read-only bit that indicates highvolta.IDUlt the ~
pin. When set to "one", disconnects PGE and PLE
from the chip.

ERASING THE EPROM
The EPROM can be erased by exposure to high-intensity ultraviolet (UV) light with a wavelength of 2537 angstroms. The recommended integrated dose (UV intensity
x exposure time) is 25Ws/cm 2 . The lamps should be
used without software filters, and the MCU should be
positioned about one inch from the UV tubes. Ultraviolet
erasure clears all bits of the MCU EPROM to the "zero"
state. Data then can be entered by programming "ones"
into the desired bit locations.
PROGRAMMING
The MCU bootstrap program can be used to program
the MCU EPROM. The alternate vectoring used to implement the self check is used to start execution of the bootstrap program.
A MCM2532 UV EPROM (other industry standard
EPROMs may be used) must first be programmed with
the same information that is to be transferred to the MCU
EPROM. Refer to application note, MC68705P31R3IU3 8bit EPROM Microcomputer Programming Module (AN857/0 Rev.2) for schematic diagrams and instructions on
programming the MCU EPROM.
EMULATION
The MC68705U3 emulates the MC6805U2 and
MC6805U3 "exactly". The MC6805U2 and MC6805U3
mask features are implemented in the mask option register EPROM byte. The following identify the few minor
exceptions to the exactness of the emulation~
1. The MC6805U2 "future ROM" areas are implemented in the MC68705U3 and these 1728 bytes

MOTOROLA MICROPROCESSOR DATA
3-683

II

MC68705U3

must be left unprogrammed to accurately simulate
the MC6805U2.
2. The reserved ROM areas have different data stored
in them. In the MC6805U2 this area is used for self
check, and in the MC68705U3 this area is used for
the bootstrap program.
3. The MC6805U2 reads all oneS in the 48 byte "future
RAM" area. This area is not implemented on the
MC6805U2/U3 mask ROM version but is implemented on the MC68705U3.
4. The MC68705U3 Vpp (pin 7) line is tied to VCC during normal, operations. On MC6805U2, this pin is
grounded during normal operations, and on the
MC6805U3, this pin is not connected.

read-modify-write sequence since it d,oesnot modify the
value. Refer to the following list of instructions.
Function

INSTRUCTION SET

II

The MCU has a set of 59 basic instructions which can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following instruction listing.
Function
Lo~d

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Complement

COM

Negate (2's Complement)

NEG

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Logical Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two-byte instructions. Refer to the following list for branch instructions.
Function

Mnemonic

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

A from Memory

LDA

Branch if Carry Clear

Load X; from Memory

LOX

(Branch if Higher or Same)

Store A in Memory

STA

E!ranch if Carry $et

Xin Memory

STX

(Branch it Lower)

Add Memory to A

ADO

Branch if Not Equal

Add Memory and Carry to A

ADC

Branch if Equal

Subtract Memory

SUB

Branch if Half Carry Clear

BHCC
SHCS

Store

BeC
(BHS)
BCS
(BLO)
BNE
BEQ

Subtract Memory from A with Borrow'

SSC

Branch if Half Carly Set

AND Memory to A

AND

Branch if Plus

OR Memory with A

ORA

Branch if Minus

BMI

Exclusive OR Memory with A

EdR

Branch if Interrupt Mask Bit is Clear

BMC
BMS

:.

BPL

Arithmetic Compare A with Memory

CMP

Branch if h,terrupt Mallk Bit is Set

Arithmetic Compare X with Memory

CPX

Branch if Interrupt Line is Low

BIL

Binest Memory with A (Logical Compare)

BIT

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

Jump Unconditional

JMP

Jump to Subroutine

JSR

READ-MODIFY-WRITE INStRUCTIONS
These instructions read·a memory location or a register, modify or test its conte,nts, and write the modified
vCllue back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
"

,

BIT MANIPULATION INSTRUCTIONS'
The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space where
all port registers, port DDRs;timer; timer control, arid onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within

MOTOROLA MICROPROCESSOR DATA
3-684

MC68l05U3

these 256 locations. The bit set, bit clear and bit test, and
branch functions are all implemented with a single instruction. For test and branch instructions, the value. of
the bit tested is also placed in the carry bit of the condition
code register. Refer to the following list for bit manipulation instructions.
Function

IMMEDIATE
In the immediate addressing mode, the operand is contained in the byte immediately fellowing the epcode. The
immediate addressing mede is used to access censtants
that de net change during program executien (e.g., a
censtant used to. initialize a loep counter).

Mnemonic

Branch if Bit n is Set

BRSET n (n=O ... 7)

Branch if Bit n is Clear

BRCLR n (n=O ... 7)

Set Bit n

BSET n (n;"O ... 7)

Clear Bit n

BCLR n (n=O ... 7)

DIRECT
In the direct addressing mede, the effective address of
the argument is centained in a single byte fellewing the
epcede byte. Direct addressing allows the user to. directly
address .the lewest 256 bytes in memery with a single
twe-byte instructien.

CONTROL INSTRUCnONS

EXTENDED

These instructions are register reference instructions
and are used to control processor operation during pregram executien. Refer to. the fellewing list fer centrel
instructiens.

In the extended addressing mede, the effective address
ef the argument is centained in the two. bytes fellewing
theopcede byte. Instructiens with extended addressing
mede are capable ef referencing arguments anywhere in
memery with a single three-bYte instruction.

Function

Mnemonic

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

CLC

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

RELATIVE
The relative addressing mede is enly used in branch
instructiens. In relative addressing, the centents ef the 8bit signed byte (the effset) fellewing the epcede is added
to. the PC if, and enly if, the branch cenditiens are true.
Otherwise, centrel preceeds to. the next instructien. The
span ef relative addressing is frem -126 to. + 129 frem
the epcede address.
INDEXED, .NO OFFSET

OPCODE MAP SUMMARY

In the indexed, no. effset addressing mede, the effective
address ef the argument is centained in the 8-bit index
register. Thus, this addressing mede can access the first
256 memery lecatiens. These instructiens are enly ene
byte leng. This mede is eften used to. meve a peinter
threugh a ,table er to. hold the address ef a frequently
referenced RAMor 1/0 lecatien.

Table 3 is an epcede map fer the instructiens used en
the MCU.

INDEXED, 8-BIT OFFSET

Reset Stack Pointer

RSP

No-Operation

NOP

ADDRESSING MODES
The MCU uses ten different addressing medes to. previde the programmer with an eppertunity to. eptimize the·
cede fer all situatiens. The varieus indexed addressing
medes make it pessible to. lecate data tables, cede cenversien tables; and scaling tables anywhere in the memery space( Shert indexed accesses are single~byte
instructions, while the lengest instructiens(three bytes)
permit accessing tables threugheut memery. Short and
leng abselute addreSsing is also. included. Twe-byte directaddressing instructiens access all data bytes in mest applicatiens. Extended addressing permits jump instructiens to. reach all memery.
The term "effective address" (EA) is used in describing
the varieus addressing modes. Effective address is defined as the address frem which the argument fer an
instructien is fetched or stered.

In the indexed, 8-bit effset addressing mede, the effective address is the sum ef the contents enhe unsigned
a-bit index register and the unsignedbytefollewing the
epcede. The addressing mede is useful fer selecting the
Kth element in· an n element table. With this two-byte
instructien, K weuldtypically be in X with the address ef
the beginning ef the table in the instructien. As such,
tables may begin anywhere within the first 256 addressable lecationsand ceuld extend as far as lecatien 510
($1 FE is the .·Iast location at which, the instructien may
. begin).·
,
INDEXED, 16-BIT OFFSET
In the indexed,16'-biteffset addressing mode, the effective address is the sum ef the contents ef the unsigned
8-bit index registerandthe two. unsigned bytes fellewing
the epcede. This addressing mede can be used in a manner similar to. indexed, 8-bit offset except that this threebyte instructien allews tables to be anywhere in memery.

MOTOROLA MICROPROCESSOR DATA

3,.685

I

•

Table 3. Opcode Map
Bit~.1

BTR

BSC

BrMCh

l----.rEL

T

DIR

~L_~~I70 T J,1
10BRSETO 17 BSETO 14 BRA
15 NEG 14
o
OlD)

1
0001
2
0010

3
0011

4
~

5

0101

3:

a
o
::0

~

3:

n
m o"'tI
w

~

I

::0

g

6
0110

7
0111

8
1000
9
1001

A

1010

B
_!lUI
C
1100

1

BTB
10
-BRCLRO
3
BTB

1

10
BRSETl

]'--'
BSET1

3

1

13

BTB

13

BTB

10
BRCLR1
10

2
Bse
1 -BCLRO
2
Bse

2

I"

--1:
-1

2

2

~C

Bse

2

2

OIR II

BHI

R- J.
-13--:1: -- .15 14 1

ADO
IMM

5

2

IX

AND

-_J4_ ADC

AOC

I

0001

mIl

L5

~EOR
~

IX2

o

OlD)

IX

1

J4

IXI

16 STA.

EOR
3 _
IX
ADC

IXI

LOA

2

I·

}4

BIT

IX2

14 - :1--J:-.
2

I"

1:- - .,._,---

BIT
EXT

5 STA 16

12

~

1[,1

I"

SUB
SUB
1 SUBIx2 152 SUBIXI 1 SUB IX
. DIR:L
EXT'
6
5
CMP
CMP
CMP
CMP
CMP
2
DIR 3
EXT 3
IX2~.
IXI I
IX
4SBC.
6 SBC
1-5 SBC ]4 SBC
SBC
l._DIR J.
EXT 3
IX2 2
IXI 1
IX

L~.
ORA

DEC

12I
INC
INCA
INCX
IXI I I
QIR II
INH i I
INH I 2

m
(I)

IMM

J-----nc

6

LOA
- LOA
1 LOA
1 LOA
LL
~M _2
_.PIR L
EltT_ 3
IX2

ROR

BMI
llEl

INC

5

142
14

SUB
IMM

2

R~/~
EXT
~ I
1X1
I~ T 1~ I ~1~O

T

DIR
1:'1

CPX
IMM

SWI
INH

1

~·~·r--T6
ROL
BHeS 1
ROL ~4ROLA
ROLX
ROL
_AEL 2
OIR 1
INH I
INH 2
IXI I I

BMC
2
REl

I

2 CMP
2
IMM

LSR

6

2

IMM

1£1

6

IXl

--''-··~-7
LSLA
LSLX
LSL
I
INH I
INH 2
IX I

BRSET5
BSET5
3 -- BTl!. 2 __Bse

~310BRCLR5
_ BTB_

I

Control
I INH

6

1

COM

2

rI'-C--l:l4 -----:1 W 1414 - .-]1'17

BRCLR3
BCLR3
BEO
ASR.ASRA
BTB_ 2 - BSe.2
..B.El. L
rnR I _
INH

10BRSET4
3
BTB.

I

IX I

INH

BCS
2
REt

RORX
L --.J!IIH

13

6•

NEG

I

I2
COM
DtA

4 .RORA
.
I __ INH

10··

2

-

~_I£o
19 RTI
NEG

r-SBC -~

6

BLS.
REl

,-7-[4-BCLR2
2
Bse

- 4~

NEG
INH II

IX

6

0110

INH

J]-- ·1-,-----'4
BRCLR2
3 .. BTB
10BRSET3
3
BTB

5

0101

RTS

BRSET2
BSET2
BCC
LSR
3
~2
~2
~2
~I

1

Read-Modify-Write
INH
IXI

0100

BRN
REl

4

17 BCLR1
2

REl

INti

4

Opcode in Binary

IX
' - - - - - - - - - - - - Address Mode

c:

MC68705U3

BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte to which
the specified bit is to be set or cleared. Thus, any read/
write bit in the first 256 locations of memory, including
1/0, can be selectively set or cleared with a single twobyte instruction.

The signed relative8-bit offset in the third byte is added
to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction
allows the program to branch based on the condition of
any readable bit in the first 256 locations of memory. The
span of branching is from -125 to + 130 from the opcode
address. The state of the tested bit is also transferred to
the carry bit of the condition code register.

INHERENT
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit to be tested, and its condition (set or clear), is included
in the opcode. The address of the byte to be tested is in
the single byte immediately following the opcode byte.

In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this. mode. These instructions are one byte long.

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage
EPROM Programming Voltage
(Vpp Pin)
TIMER Pin - Normal Mode
TIMER Pin - Bootstrap
Programming Mode
All Others
Operating Temperature Range,
MC68705U3
MC68705U3C
Storage Temperature Range
Junction Temperature
Cerdip

Symbol

Value

Unit

VCC

-0.3 to + 7.0

V
V

Vpp
Vin

- 0.3 to + 22.0
-0.3 to +7.0

Vin
Vin

- 0.3 to + 15.0
-0.3 to +7.. 0

TA

TL to TH
+ 70
-40 to +85

TstQ

-55 to +150

o to

°c

These devices contain circuity to protect
the inputs against damage due to high static
voltages or electrical fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit. For proper operation, it is recommended that Yin and Vout be constrained
to the range VSS,,;(Vin and Vout)";VCC. Reliability of operation is enhanced if unused
inputs except EXTAL are tied to an appropriate logic voltage level (e.g., either VSS or
VCC)·

°c

°CIW

TJ
175

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance
Cerdip

Symbol

Value

Unit

8JA

60

°C/W

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can
be obtained from:
TJ=TA+(PO 0 6JA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
6JA
Junction-to-Ambient, °CIW
Po
= PINT+PPORT
= ICC x VCC, Watts - Chip Internal Power
PINT
PpORT = Port Power Oissipation,
Watts - User Oetermined

For most applications' PPORT

~ 5.0

!

Y

::l

4.0

~ 3.0

'0

2.0

o 1.0
10

20

30

40

50

60

70

80

ReSistance Iko)

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only

I

INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCo-PC7, PDOPD7)
These 32 lines are arranged into four 8-bitports(A, 8,
C, and D). Ports A, 8, and C are programmable as either
inputs or outputs under software control of the data direction registers. Port 0 is a fixed input port and is not
controlled by any data r~er. Port D bit 6 may be used
for a second interrupt (lNT2). Refer to PROGRAMMING
for additional information.

When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Care must
be exercised when using read-modify-write instructions
since the data read corresponds to the pin level if the
DDR is an input (zero) and, also, to t~e latched output
when the DDR is an output (1). Refer to Table 1 for I/O
functions and to Figure 3 for typical port circuitry.
NOTE
Read-modify-write instructions Should not be used
when writing to the DDR since DDRs always read
as 'one'.
Table 1. I/O Pin Functions
Data
Direction
Register
Bit

Latched
Output
Data
Bit

Output
State

1
1
0

0
1
X

0
1
Hi-Z**

Input
To
MCU
.

0
1
Pin

**Ports Band C are three-state ports. Port A has an internal
pullup devices to provide CMOS data drive capability.

PROGRAMMING
INPUT/OUTPUT PROGRAMMING
Ports A, 8, and C are programmable as either input or
output under software control of the corresponding data
direction register (DDR). Port 0 is input only. The port 1/
o programming is accomplished by writing the corresponding bit in the port DDR to a logic one for output
and a logic zero for input. On reset, all the DDRs are
initialized to a logic zero state to put the ports in the input
mode. The port output registers are not initialized on
reset and should be written to before setting the DDR
bits.

MEMORY
The MCU is capable of addressing 4096 bytes of memory and I/O registers. The memory map is shown in Figure
4. The locations consist of user EPROM, bootstrap ROM,
user RAM, a mask option register (MOR), a program control register, and I/O. The interrupt vectors are located
from $FF8 to $FFF. The bootstrap is a mask-programmed
ROM that allows the MCU to program its own EPROM.
The stack area is used during processing of an interrupt
or subroutine call to save the CPU state. The stack pointer

Figure 3.· Typical Port I/O Circuitry and
Register Configuration

MOTOROLA MICROPROCESSOR DATA
3-694

MC68705U5

766432.10

7

000

and
RAM
1128 Bytes)

Page Zero
Access With
Shan
Instructions

127
:

1

$000

1/0 Ports Timer

Page Zero
User EPROM
~

_

~28!.vt~

Port A Data Register

1

Port B Data Register

$001

$07F

2

Port C Data Register

$002

$(8)

3

Port·D Data Register

$003

__ I\oFF

4

PortADDR*

$004

$100

5

PortB DDR*

$005

6

PortCDDR*

$006

266
User
Main
EPROM
(3640 Bytes)

3896
3896

1---.,.----

3897
3967
3968

Not Used
Bootstrap
ROM
1120 Bytes)

. 07

Interrupt
Vectors

I§
4092

4093
4094
4096

$000

0

Mask Option Register

$F37
$F38
$F39
$F7F
$F80

7

'NotUsed

$007

8

Timer Data Register

$006

9

TimefControl Register

$009

10

Miscellaneous Register

$OOA

11
12
15
16

Program Control Register

$OOB

Not Used

$FF7
$FFS

Timer Interrupt

~-----Extemallnterrupt

1-------1------SWI

RESET

$OOC-$OOF
$010

RAM
(112 Bytes)

$FF9
$FFA
$FFB
$FFC
$FFD
$FFE
$FFF

Stack
(31 Bytes Maximum)

+

127

II

$07F

* caution: Data direction registers (DDRs) are write-only; they read as $FF.

Figure 4. Memory. Map

PROGRAM COUNTER (PC)

decrements during pushes and increments during pulls.
Refer to INTERRUPTS for additional information.

The program counter is a 12-bit register that contains
the address of the next byte to be fetched.
11
8 7
0

NOTE
Using the stack area for data storage or temporary work locations requires care to prevent it from
being overwritten due to stacking from an interrupt
or subroutine call.

PCH

pel

1

STACK POINTER (SP)

REGISTERS
The MCU contains the registers described in the following paragraphs.
ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register
used to hold operands and results of arithmetic calculations or data manipulations.
7

I

A

The stack pointer is a 12-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set at location $07F. The stack pointer
is thEm decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
The seven most-significant bits ·of the stack pointer are
permanently set at 0000011. Subroutines and interrupts
may be nested down to location $061 (31 bytes maximum), which allows the programmer to use up to 15
.levels of subroutine calls (less if interrupts are allowed).
11
5 4
0

I 0 1 0 1 0 1 0 1 0 11

11

I

SP

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may be added to an 8- or 16- bit immediate value to create
an effective address. The index register may also be used
as a temporary storage area.
7

x

CONDITION CODE REGISTER (CC)
The condition code register is a 5-bit register in which
four bits are used toiridicate the results of the instruction
just executed. These bits can be individually tested by a
program, and specific actions can be taken as a result of
their state. Each bit is explained in the following paragraphs.

MOTOROLA MICROPROCESSOR DATA
3-695

MC68705U5, '

4

0

I HI I N I zIe I

--1

Half Carry (H)
This bit is set during ADD 'and ADC opera~ions to indicate that a carry occurred between bits 3 an~' 4.

::r:: 10 ....F

(MCU)

Interrupt (I)
When this bit is set, the timer and external interrupt is
masked (disabled). If an external interrupt occurs while
this bit is set, the interrupt is latched andis processed as
soon as the interrupt bit is cleared.
'

Figure 5. Power-Up RESET Delay Circuit
Negative (N)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative (bit
7 in the result is a logic one).

EXTER~ALRESETINPUT

The MCU is reset when a logic zero is applied to the
RESET input for a period longer than one machine cycle
(tcyel. Under this type of reset, the Schmitt trigger switches
off at VIRES- to provide an internal reset voltage.

Zero (Z)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.

INTERRUPTS

Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occured during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions, and during shifts and
rotates.

The MCU can be interrupted four different ways: (1)
through the external interrupt INT input pin, (2) with the
internal timer interrupt request, (3) using the software
interrupt instruction (SWI), or (4) the external Port 0 (lNT2)
input pin.
, Interrupts cause the processor registers to be saved on
the stack and the interrupt mask (I bit)'set to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack after which
normal prQcessing resumes. The stacking order is shown
,
in Figure 6.
Unlike RESET, hardware interrupts do, not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.

RESETS
The MCU can be reset two ways: by initial power-up
and by the external reset input (RESET). The RESET input
consists mainly of a Schmitt trigger that senses the line
logic level.
POWER-ON~RESET '(POR)

NOTE

An internal reset is generated on power-up that allows
the, internal clock gener~tor to stabilize. 'The power-on
reset is used strictly fqrpower turn~on voltatg~.A delay
of tRHL milliseconds is required before allowing RESET
input to go high. Connecting a capacitor to the RESET
input (Figure 5) typically provides sufficient delay.

5

6

n-4

I

1

1

1

I

1

Th~, current

instruction is considered to be the one
already fetched and being operated on.
When the current instruction is complete, the processor
checks all. pending hardward interrupts and, if unma,sked

3

4

I

n-3

Accumulator

n-2

Index Register

n-l

n

1

r

iI,

1

I

o

2

Condition Code Register

1

I

PCH~

PCl-

..,'

Push

- For subroutine calls, ~nly P<:;H and PCl are stacked.

Figure 6. Interrupt Stacking Order

MOTOROLA MICROPROCESSOR' DATA
3-696

Pull

MC68705U5

(I bit clear), proceeds with interrupt processing; otherwise, the next instruction iffetched and executed. Masked
interrupts are latched for later interrupt service. If the
timer interrupt status bit is cleared before unmasking the
interrupt, then the interrupt is not latched.,
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction regardless of the setting
of the I bit. Refer to Figure 7 for the reset and interrupt
instruction processing sequence.

TIMER INTERRUPT

If the t,ime mask bit (TCR6) is cleared, then, each time
the timer decrements to zero (transitions from $01 to $00)'
an interrupt request is generated. The actual processor
interrupt is generated only if the interrupt mask bit ofthe
condition code register (CCR) is also cleared. When the
interrupt is recognized, the current state of the machine
is pushed onto the stack and the I bit in the CCR is set,

masking further interrupts until the present one is serviced. The contents of the timer interrupt vector, containing the location of the timer interrupt service routine, is
then loaded into the program counter. At the end of the
timer interrupt service routine, the software normally executes an RTI instruction which restores the machine state
and starts executing the interrupted program. The timer
interrupt status bit can only be cleared by software.
EXTERNAL INTERRUPT

The external interrupt is intern~ synchronized and
then latched on the falling edge of INT and INT2. Clearing
the I bit enables the external interrupt. The INT2 interrupt
has an interrupt request bit (bit 7) and a mask bit (bit 6)
in the miscellaneous register (MR). The INT2 interrupt is
inhibited whEm the mask bit is set. The INT2 is always
read as a digital input on port D. The INT2 and timer
interrupt request bits, if set, cause the MCU to process
an interrupt when the condition code I bit is clear. The
following paragraphs describe two typical external interrupt circuits.

1.1 (in CC)

07F. SP
O. DDRs
CLR INT Logic

FF. Timer
TCR6.1
TCR7.0

Load PC From:
SWI: FFC/FFD
INT: FFA/FFB
Timer or
INT2: FF81 FF9

Load Options From
MOR ($F38) Into
Control Logic

Figure 7. Reset and Interrupt Processing Flowchart

MOTOROLA MICROPROCESSOR DATA
3-697

II

MC68705U5

TIMER

Zero-Crossing Interrupt

A sinusoidal input signal (fINT maximum) can be used
to generate an exte'rnal interrupt (see Figure 8a) for use
as zero-crossing detector (for negative transitions of
the ac sinusoid). This type of circuit allows applications
such as servicing time-of-day routines and engaging/disengagingac power control devices. Off-chip, full-wave
rectification provides an interrupt at every zero crossing
of the ac signal and, thereby, provides a 2f clock.

a

Digital-Signal Interrupt

With this type of circuit (Figure 8b). the INT pin can be
driven by a digital signal. The maximum frequency of a
signal that can be recognized by the TIMER or INT pin
logic is dependent on the parameter labeled tWL, tWH.
Refer to TIMER for additional information.

SOFTWARE INTERRUPT (SWI)

II

The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. The SWI
execution is similar to the hardware interrupts.

MODES OF OPERATION
The MCU has two modes of operations: normal and
bootstrap. The following paragraphs describe these
modes.
.

NORMAL MODE
This mode is a single-chip mode and is entered if the
following conditions are met: (1) the RESET line is low,
(2) the PCOpin is within its normal operational range,
and (3) the V...f..E...E.0 is connected to VSS. The next rising
edge of the RESET pin then causes the part to enter the
normal mode.
BOOTSTRAP MODE
The bootstrap mode is entered if the TIMER pin = + 12
V. Refer to application note, MC6805P3/R31U3 8-Bit EPROM
Microcomputer Programming Module (AN-857 Rev.2).

The MCU consists of an 8-bit software programmable
counter driven bya 7-bit software programmable prescaler. The various timer sources are made via the timer
control register (TCR) and/or the mask option register
(MaR). The 8-bit counter may be loaded under program
control and is decremented toward zero. When the timer
reaches zero, the timer interrupt request bit (bit 7) in the
timer control register (TCR) is set. Refer to Figure 9 for
timer block diagram.
The timer interrupt can be masked (disabled) by setting
the timer interrupt mask bit (bit 6) in the TCR. When the
I bit in the condition code register is cleared and TCR bit
6 is cleared, the processor receives the interrupt. The
MCU responds to this interrupt by (1) saving the present
CPU state on the stack, (2) fetching the timer interrupt
vector, and (3) executing the interrupt routine. The timer
interrupt request bit must be cleared by software. Refers
to RESETS and INTERRUPTS for additional information.
The prescaler is a 7-bit divider which is used to extend
the maximum length of the timer. To avoid truncation
errors, the prescaler is cleared when TCR bit 3 is set to
a logic one; however, the TCR bit 3 always reads as a
logic zero to ensure proper operation with read-modifywrite instructions.
'
The timer continues to count past zero, falling from $00
through $FF, and continues the countdown. The counter
can be read at any time by reading the timer data register
(TDR). This allows a program to determine the length of
time since a timer interrupt has occurred without disturbing the counting process. The TDR is unaffected by
reset.

SOFTWARE CONTROLLED MODE
This mode is selected when raPT (bit 6) in the MaR
is programmed to zero. The timer prescaler input can be
configured for three different operating modes plus a
disable mode, depending on the value written to TCR
control bits 4 and 5 (TIE and TIN). The following paragraphs describe the different modes.

(al Zero-Crossing Interrupt

(bl Digital-Signal Interrupt

VCC

In~ut
(liNT

(Current

TTL

MaX.)~Llml!ln9)

Rs1 MO
ac Inputs
10 Vac p-p

R.

2 iNT

4.7 k

Level
MCU

2

DI9I1al--.....'"""-4
Input

0.1-1.0
I'F

lJ
Figure 8. Typical Interrupt Circuits

MOTOROLA MICROPROCESSOR. DATA
3-698

iNT
MCU

EPROM

8

Timer Data Register nDR)
8-Bit Counter

3:
0
~
0
::J:J

0

§;

Co\)

~

U)

CD

~I
:::a

Timer
Pm
7-Blt Prescaler
Select
~_ _ _ _ _ _---fll-of-8
Clear

"0
::J:J

0

(")

~I

en
CIO

0

m
en

s:o

Set

Internal
4>2
Clock
(fosc+ 4 )

Timer Control Register nCR)

C

U'I

3

l>

fplN - Prescaler Input Frequency
fCIN - Counter Input Frequency

Timer Control Register Bits
TIR - Timer Interrupt Request Status

TIM -- Timer Interrupt Mask
TIN - Timer Input Select
TIE - TImer External Input EnablePSC - Prescaler Clear
PS2, PS1, PSO- Prescaler Select

Figure 9. Timer Block Diagram

......
o

U'I

Mask Option Register Bits:
ClK - Clock Oscillator Type
TOPT - Timer Mask/Programmable Option
ClS - Timer Clock Source
(TIE) c (Timer External Input Enable)
SNM - Secure/Non-Secure Mode Option
P2, Pl, PO - Prescaler Option

MC68705U5

Timer Input Mode 1
When TIE and TIN are both programmed to zero, the
timer input is from the internal clock (phase two) and the
timer input pin is disabled. The internal clock mode can
be used for periodic interrupt generation as well as a
reference for frequency and event measurement.
Timer Input Mode

~

When TIE = 1 and TIN = 0, the internal clock and the
timer input signals are ANDed to form the timer input.
This mode can.be used to measure external pulse widths.
The active high, external pulse gates in the internal clock
for the duration of the external pulse. The accuracy of
the count is ± 1.
Timer Input Mode 3
When TIE = 0 and TIN= 1, no prescaler input frequency
is applied to the prescaler and the timer is disabled.

I

Timer Input Mode 4
When TIE ,and TIN are both one, the timer input is from
the external clock. The external clock can be used to count
external events as well as to provide an external frequency for generating periodic interrupts. Frequency of
e)(ternal input must be .:; fosc/S.
'
MOR CONTROLLED MODE
This mode is selected when TOPT (bit 6) in the MOR
fs programmed to logic one. T.he timer circuits are the
$ame as described in SOFTWARE CONTROLLED MODE.
The logic levels of TCR bits 0, 1,2, and 5 are determined
during EPROM programming by the same bits in the MOR.
Therefore bits 0, ,; 2, and 5 in the MOR control the prescaler division and the timer clock selection. TIE (bit 4) and
PSC (bit 3) inthe TCR are set to a logic one when in the
MOR contwlled mode. TIM (bit 6) and TIR (bit 7) are
controlled 'by the counter and software.

TIR - Timer Interrupt Request
Used to indicate the timer interrupt when it is logic
one
1 = Set when the timer data register changes to all
zeros
0= Cleared by external reset, power-on reset, or
under program control
TIM - Timer Interrupt Mask
Used to inhibit the timer interrupt
1 = Interrupt inhibited .
o= Int~rruptenabled
TIN - External or Internal
Selects input clock source
1 ;= External clock selected
0:= Internal clock selected (fosc/4)
TIE - TIMER External Enable
Used to enable external TIMER pin. When TOPT = 1,
TIE is always a logical "one".
1 = Enables external timer pin
0= Disables external timer pin
PSC - Prescaler Clear
Write only bit. Writing a 1 to this bit resets the prescaler to zero. A read of this location always indicates
,a zero when TOPT=O. When TOPT=1, this bit will
read a logical "one"and has no effect on the prescaler.
PS2, PS1, PSO - Prescaler Clear
Decoded to select one of eight outputs of the prescaler
Prescaler

PS2

PS1

PSO

0
0

0
0

0

1

1

2

0

1

0

4

0

1

1

8

1

0
0

0

16

1

1

32

1

1

0

64

1

1

1

128

TIMER CONTROL REGISTER (TCR) $009
This is an S-bit register that controls various functions
such as configuring operation mode, setting ratio of the
prescaler, and generating timer interrupt request signal.
All bits are read/write except bit 3. The configuration of
the TCR is determined by the TOPT (bit 6) in the MOR.
When TOPT = 1, the TCR emulates the MC6S05U2; when
TOPT = 0, the TCR is controlled by software.
'
TCR with MaR TOPT = 1
7
6
5
\ TIR

\ TIM

TIR

I

TIM

I

The MOR is implemented in EPROM. This register contains all zeros prior to programming and is not affected
by reset. The MOR bits are described in the following
paragraphs.

PSC

TIN

PSC

PS2

u

u

PSI

7
\' ClK

RESET:

o

NOTES
When changing the PS bits in software, the PSC
bit should be written to a "one" in the same write
cycle to clear the prescaler. Changing the PS bits
without clearing the prescaler may cause prescaler
truncation.
MASK OPTION REGISTER (MOR) $F38

TCR with MaR TOPT = 0
7
6
5

I

u

Divide By

u

u

ClK -

*The value of corresponding bits in MaR is written during RESET rising
edge. These bits always read 'one'.

6

I TaPT I

ClS

Clock (oscillator type)
1 = Resistor Capacitor (RC)
O=Crystal

MOTOROLA. MICROPROCESSOR DATA

3-700

SNM

P2

PI

PO

MC68705U5.

TOPT - Timer Option
1 = MC6805U2 type timer/prescaler. All bits except
6 and 7, of the TCR are invisible to the user.
Bits 5, 2, 1, and 0 of the MOR determine the
equivalent MC6805U2 mask options.
O~AII TCR bits are implemented as a software programmable timer. The state of MOR bits 5, 4,
2, 1, and 0 sets the initial values of their respective TCR bits.
CLS - Timer/Prescaler Clock Source
1 = External TIMER pin
0= Internal clock
Bit 4
Not used if TOPT= 1. Sets the initial value of TIE in
the TCR if TOPT = O.
1 =Not used
O=Sets initial value of TIE in the TCR
SNM - Secure. Mode.
1 == EPROM contents cannot be access externally
0= EPROM not programmed
P2, P1,PO
The logical levels of these bits, when decoded, select
one of eight outputs on the timer prescaler.

NOTE

PGE

PLE

.Programming Conditions

0

0

O.

Programming' mode (program
EPROM byte)

1

0

0

PGE and PlEdisabled from
system

0

1

0

Programming disabled (latch
address and data in EPROM)

1

1

0

PGE and PlE disabled from
system

0

0

1

Invalid state; PGE = 0 if PLE = 0

1

0

1

Invalid state; PGE = 0 if PLE = 0

Divide By

0

1

1

"High voltage" on Vpp' -'-

1

.1

1

PGE and PlE disabled from
system (operating mode)

P2

P1

PO

0

0

0

1

0

0

1

2

0

1

0

4

0

1

1

8

1

0

0

16

1

0

1

32

1

1

0

64

ERASING THE EPROM

1

1

1

128

The EPROM can be erased by exposure to high-ihtensityultraviolet (UV) light with a wavelength of2537· angstroms. The recommended integrated dose (UVintensity
x exposuretime) is 25Ws/cm 2 . The lamps should be
used without software filters andt~e MCU should be
positioned about one inch from the UV tubes. Ultraviolet
erasure clears all bits of the MCU EPROM to the "zero"
state. Data then can be entered by programming "ones"
into the desired bit locations.

EPROM PROGRAMMING

PROGRAMMING CONTROL REGISTER (PCR) $008
The PCR is an 8-bit register which provides the necessary control bits to program the EPROM. The bootstrap
program manipulates the PCR when programming so the
user need not be concerned with PCR in most applications.
wit~

7

MOR TOPT = 1
6
5

RESET:
U

U

U

PROGRAMMING

2

I VPON I

1
U

U

<

VPON being "zero" does not indicate that th~ Vpp
level is correct for programming. It is used as a
safety interlock for the user in the normal operating
.
mode.
VPON

Presealer

TCR

VPON - VppOn
A read-only bit th~t indicates high volta~t the '!ff'
pin. When set to "one", disconnects PGE and PLE
from the chip;
1 = No high voltage on Vpp pin
0= High voltage on Vpp 'pin

PGE

PlE

U

PLE - Programming Latch Enabe
Controls address and data being latched into the
EPROM. Set during reset, but maybe cleared any"
time.
1 = Read EPROM
0= Latch address and data on EPROM
PGE - Program Enable
Enables programming of EPROM. Must be set when
changing the address and data. Set during reset
1 = Inhibit EPROM programming
O=Enable EPROM programming (ifPLE is low)

The MCU bootstrap program can be used to program
the MCU EPROM. The alternate vectoring used to implement the self check is used to start execution of the bootstrap program.
A MCM2532 UV EPROM (other industry standard
EPROMsmay be used) must first be programmed with
the same information that is to be transferred to the MCU
EPROM. The MC68705U5 is programmed the' same as
the MC68705U3. Refer to application note, MC68705P31
R3/U3 Bcbit EPROM Microcomputer Programming Mod~
ule(AN-857 Rev.2) for schematicdiilgrams and instruc- .
tionson programming the MCU EPROM.

EMULATION
The MC68705U5 emulates the MC6805U2 and
MC6805U3 "exactly"; The MC6805U2 and MC6805U3

MOTOROLA MICROPROCESSOR .DATA
3-701

II

MC68705U5

mask features are implemented in the mask option register EPROM byte. The folloVl(ing identify the few minor
exceptions to the exactness of the emulation.
1. The MC6805U2 "future ROM" areas are implemented in the MC68705U5 and these 1728 bytes
must be left unprogrammed to accurately simulate
the MC6805U2.
2. The reserved ROM areas have different data stored
in them. In the MC6805U2 this area i~ used for self
check, and in the MC68705U5 this area is used for
the bootstrap program.
3. The MC6805U2 reads all ones in the 48 byte "future
RAM" area. This area is not implemented on the
MC6805U2/U3 mask ROM version but isimplemented on the MC68705U5.
4. The MC68705U5Vpp (pin 7) line is tied to Vec during normal operations. On MC6805U2, this pin is
grounded during normal operations; on the
MC6805U3, this pin is not connected.

I

INSTRUCTION SET
The MCU has a set of 59 basic instructions which can
be divided into five different types: register/memory, readmOdify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use tWo operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following instruction list.
Function

Mnemonic

Load A from Memory

LOA

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to' the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following listing of instructions.
Function

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Co.mplement

COM

Negate (2's Complement)

NEG

Ro.tate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Lo.gical Shift Left

LSL

Lo.gical Shift Right

LSR

Arithmetic Shift Right

ASR

Test fo.r Negative o.r Zero

TST

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two-byte instructions. Refer to the following list for branch instructions.
Function

Mnemonic

Branch, Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower o.r Same

BLS

Load X from Memo.ry

LDX

Branch if Carry Clear

Store A in Memory

STA

(Branch if Higher o.r Same)

BCC
(BHS)

Store X in Memory

STX

Branch if Carry Set

Add Memory to. A

ADD

(Branch if Lower)

(BLO)

Add Memo.ry and Carry to' A

ADC

Branch if No.t Equal

BNE

Subtract Memo.ry

SUB

Branch if Equal

Subtract Memo.ry fro.m A ,with Bo.rro.w

SBC

Branch if Half Carry Clear

BHCC

AND Memo.ry to A

AND

Branch if Half Carry Set

BHCS

ORA

Branch if Plus

BPL

Exclusive OR,Memo.ry with A,

EOR

Branch if Minus

BMI

OR Memory with A

"

BCS

BEQ

Arithmetic Co.mpare A with Memo.ry

CMP

Branch if Interrupt Mask Bit is Clear

BMC

ArithmeticCo.mpare X with Memo.ry

CPX

Branch if Interrupt Mask Bit is Set

BMS

Bit Test Memo.ry with A (Lo.gical Co.mpare)

BIT

Branch if Interrupt Line is Low

BIL

Jump Unco.nditio.nal

JMP

Branch if Interrupt Line is High

BIH

Jump to. Subro.utine

JSR

Branch ,to. Subro.utine

BSR

MOTOROLA MICROPROCESSOR-DATA

3·702

MC68705U5

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any bit which
resides in the first 256 bytes of the memory space where
all port registers, port DDRs, timer, timer control, and onchip RAM reside. An additional feature allows the software to test and branch on the state of any bit within
these 256 locations. The bit set, bit clear and bit test, and
branch functions are all implemented with a single instruction. For test and branch instructions, the value of
the bit tested is also placed in the carry bit ofthe condition
code register. Refer to the following list for bit manipulation instructions.
Function

Mnemonic

Branch if Bit n is Set

BRSET n (n=O ... 7)

Branch if Bit n is Clear

BRClR n (n=O ... 7)

Set Bit n

BSET n (n=O ... 7)

Clear Bit n

BClR n (n=O ... 7)

CONTROL INSTRUCTIONS
These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.
Mnemonic

Function
Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

ClC

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

Reset Stack Pointer

RSP

No-Operation

NOP

long absolute addressing is also included. Two-byte directaddressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

IMMEDIATE
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).
DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instructiOn.
EXTENDED
In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
mem'ory with a single three-byte instruction.
RELATIVE
The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from - 126 to + 129 from
the opcode address.

OPCODE MAP SUMMARY
Table 2 is an opcode map for the instructions used on
.
the MCU.

INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. Thus, this addressing mode can access the first
256 memory locations. These instructions are only one
byte long. This mode is often used to move a pointer
through a table or to hold the address of a frequently
referenced RAM or I/O location.
INDEXED, 8-BIT OFFSET

ADDRESSING MODES
The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables; and scaling tables anywhere in the memory space. Short indexed accesses are single-byte
instructions, while the longest instructions (three bytes)
permit accessing tables throughout memory. Short and

In the indexed, 8-bit offset addressing· mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
the beginning of the table in the instruction. As such,
tables may be.ginanywhere within the first 256 addressable .locations and cou Id extend as far as ·Iocation 510
($1 FE is the last location at which the instruction may
begin).

MOTOROLA MICROPROCESSOR DATA
3-703

I

•

Table 2. Opcode Map
Bit Manipulation
BTIt
BSe

~
~
1

0001

2

0010

3

0011

4

0100

s:

a

01~1

§;

,~

s:

n
o"'a
g :::a
o(")

"

o~o

:::a

0'

w

01~1

~

m

t/)
t/)

o

~

~

9

1001

1~0
,J\1

lfoo
1Pol
11~O
F

1111

~
I :BRSEJfR
10
BRCL
3
:fB
I'!.
BRSE
3
Jis

L:~RCL~T'B
12,
BRSE
13
JtB
1!(

13BRCL~tB

12,
BRSE
13
JiB

'2..
BRCL

,

BSE~~('

2 BCL~~c
7
2 BSE11c
7

2BCL~L

7
2

BSE1~c

7

2 BCL~~c
7
2
7

BSE1~c

2BCL~~c

~BSE1tc

13BRCL~:S

7

2
4

2
2
4

2 BCL~~c
7

2
4

2 BSE1~c
7

BCL~~c

1:~RSEJfB

2

BSE1~c

ISRCLR7
3
B~

o~

J,1

~~.

4
NEGOIR

Read-Modify-Write
IXI
INH

NEG
INH

1

4

0~1

7
lNH

2 BCL~~c
7

2
4

2 BSE1~c
7

2
4

2

INH

INH

01~1

8

9

1000

IX'

,

IX

,
,

BE~
BHC~

BHC~R

BM~EL
BM~ll

6
2 COM
OIR
6
2 LS'bTR

6
2 ROR
DIR
6
2 ASR
DlR
6
2 LSL
DIA
6
2 ROL
OIR
6
DEC
2
DIA

6
2
:

INC

DIR

TST
DIA

4

, COMAINH

4

,

RTI
INH

6

,

4

RORA
INH

ASRA
INH

, LSLAINH
4
, ROLAINH
4

,

DECA
INH

.,
4

1

INCA
INH

TSTA
1
INH

6

7

COM X
INH

4
LSRA
INH

.,
4

4

, LSRxINH

COM
2
IX'

RTS
lNH

7

LSR
2

IXI

11

, COM IX ,
6
, LSR IX

SWI
INH

~~~CI2 ~AEL

4

6
2

CLR
DIA

1

INH

4

,

4
1

2 ROR
7

ASRX
INH

2

LSLX

2

IX'
LSL

IX'

ROL

ROLX
INH

DECX
INH

2
7
2

,

INH
DIR
EXT
REL
BSC
BTB
IX
IXl
IX2

Inherent
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
Indexed (No Offset)
Indexed. 1 Byte (S-Bit) Offset
Indexed. 2 Byte (l6-Bit) Offset

4 SUB
2
DIR
4
CMP
DIR
2
4
SBC
2
DIA
4
CPX
DIR
2
4
AND
2
DIR
4

6

IX'
DEC
IX'

,

IX

1
4

IX
2

ROL

IX

TSTX
1
INH

INC
2
7

IX'
TST

2

IXI

I
6

,

CLC
'NH

,
,

SEC
INH

,

SEI

2
DEC

IX

6

7

INCX
INH

TAX
INH

2
LSL

12
4

1

Cli

INH

CLR
2

IX'

,

2
, EOR ~
IMM
2
ADC
2
IMM
2
ORA
IMM
2

TST

IX

1
2

_

,
-

3

6

5 SBC
EXT
3
5
CPX
3
EXT

~
3
5
3

AND
EXT
BIT

EXT

5
LDA
DIR

5 STA
2
DIR
4
2 EOR
DIR
4
ADC
2
DIR

LDA
EXT

3

ST~XT

:
5

EOR
EXT

3
5
3

,X2

6 SBC
3
IX2
o CPX
3
IX2
6 AND
3
IX2
6
BIT
3
IX2
6
LDA
3
IX2
3 STA
6
3 EOR

4 SBC
1
IX

0010

6
ADC
EXT

~

3

ADC

IX2

5 LDX
3
EXT

6 LDX
3
IX2

o STX
EXT
3

3

~

JMP

3

IX2
JSR

2
5
2
5

AND,~

2

BIT IXI

IXI

5 LDA
2
IXI

STX
IX2

ADC
IXI

2

• CPX
1
IX
4
AND
1
IX
4
1
4
1

~

BIT IX
LDA

1
4

2

rl,1

4
~

O~l
6

0110

IX

0~1

IX

lcm

8~

AoC

1001
A
1010

5 ADD
2
IXI

• ADD
1
IX

B
1011

JMP
IX

C
1100

IX

1

2

J

1

JSR
IXI

5 LDX
2
IXI
6
STX
IXI
2

1

JSR

~

9

IX

• ORA
1
IX

• JMP
IXI
2

1

EOR

1

IX
STA

1
4

~

ORA
IXI
2

~

H

IX2

3

CPX

~

~

JSR
EXT
3

~

5 EOR
2
IXI

H

STX
DIR

5 SBC
2
IXI

2

,X2

JSR
DIA
2
4
LDX
2
DIR

~

0001

,X1

,X2

BSR
REL
2

2

CMP
IXI

SUB

6 STA
2
. IXI

6 ADD
3
IX2

TXA
INH

~

• SUB
1
I){
4
CMP
I
IX

:
5

IX2

' ADD
EXT
3
4
JMP
EXT
3

B

IX

lftl

CMP

• ADD
DIR
2
3
JMP
DIA
2

2
_~IX,-

CMP
EXT

SUB

ADD
IMM

2

12 LDX
IMM
2
CLR

BIT DIR

:

o ORA
3
IX2

RSP
INH

NOP
INH
1

IX

2

3

SUB
-EXT

ORA
EXT
3

'L

INH

2
4

~

3
5

Ixl

11~0

1~1

roo

1

• ORA
DIR
2

2
INC

6

7

CLRX
INH

BI~MM

2

I
6

,
6
,
6
,

B

12 LDA
IMM

IX

(")

en
CO

......

o
c.n
c:
c.n

Pol

• LOX
1
IX

E
1110

o STX
1
IX

1111

F

I

LEGEND

j '[,']

Abbreviation. for Add"", Model
IMM

2 SUB
IMM
2
CMP
2
IMM
2
SBC
IMM
2
2
CPX
IMM
2
2
AND
2
IMM
2

DIR

L

ROR
ASR

7

4

,

IX'

ASR
7

INH

4
1

6

7

RORX
1

4
CLRA
INH

1011

,2
4

BIL
REL

IMM
A
1010

1001

9

6
• NEG

BHIREI

BPL .
2
AEL
4
BMI
2
~L
4
2
4

o~o
NEG

NEG
1

Rlllliater/Memorv
EX
1X2

Control
IX

BRN
AEL

.2 BLSAEI
4
.2 BCC
REL
4
7 BCS
AEl
4
BNE
2
AEL
4

J

2

I'!.,
BRCL
13
:fB
10
BRSE
13
JIB

2
4

4

I!RSEJiB
10
BRCL
13

:ta

.: BRAIlll

INH

DIR

4

7

:iB

10.

BEL
J,o

~1

I:BRSE~

13

Branch

'ofCyd"

Mnemonic
Bytes

4

.-

1

IX

~

0"",.

'0 H.udodm.

Opcode in Binary

()(XX) C'"'""'

' - - - - - - - - - Address Mode

MC68705U5

INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the two unsigned bytes following
the opcode. This addressing mode can be used in a manner similar to indexed, 8-bit offset except that this threebyte instruction allows tables to be anywhere in memory.
BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode. The byte following the
opcode specifies the direct addressing of the byte to which
the specified bit is to be set or cleared. Thus, any read/
write bit in the first 256 locations of memory, including
I/O, can be selectively set or cleared with a single twobyte instruction.
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The

its

condition (set or clear), is included
bit to be tested, and
in the opcode. The address of the byte to be tested is in
the single byte immediately following the opcode byte.
The signed relative 8-bit offset in the third byte is added
to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction
allows the program to branch based on the condition of
any readable bit in the first 256 locations of memory. The
span of branching is from -125 to + 130 from the. opcode
address. The state of the tested bit is also transferred to
the carry bit of the condition code register.

INHERENT
In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this mode. These instructions are one byte long.

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS (Voltages Referenced to Vss)
Rating
Supply Voltage

Symbol

Value

Unit

. VCC

-0.3 to + 7.0

V
V

Input Voltage
EPROM Programming Voltage
(Vpp Pin)
TIMER Pin...:.. Normal Mode
TIMER Pin - Bootstrap
Programming Mode
All Others
Operating Temperature Range
MC68705U5
MC68705U5C

0.3 to + 22.0
-0.3 to + 7.0

Vpp
Vin

~

Vin
Vin

-0.3 to + 15.0
-0.3 to + 7.0

TA

TL to TH

o to

°c

+70
-40 to +85

Storage Temperature Range

Tstg

Junction Temperature
Cerdip

-55 to + 150

These devices contain circuity to protect
the inputs against damage due to high static
voltages or electrical fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit. For proper operation, it is recommended that Vin and Vout be constrained
to the range VSS ,;;; (Vin and Vout) ,;;; VCC.
Reliability of operation is enhanced if unused
inputs except EXTAL are tied to an appropriate logic voltage level (e.g.,.either VSS or
VCC)·

°c
°CIW

TJ
175

THERMAL CHARACTERISTICS
Characteristic

Symbol

Thermal Resistance
Cerdip

Value

Unit
°CIW

6JA
60

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can
be obtained from:
TJ=TA + (PO 8JA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
8JA
Junction-to-Ambient, °CIW
Po
= PINT+PPORT
= ICC x VCC, Watts - Chip Internal Power
PINT
PPORT = Port Power Oissipation,
Watts ~ User Oetermined
0

For most applications PPORT>>

10K

10nF
10

8

~

ESET

VRH

Voo
ascI

~~

-

~

-6

NC

1!!.

NC

G:
52

28
21

~

~

47K

RESET

J..

~

47J-lFI

-

-

I

16

1~~

17

~ NC

,01 J-lF

I

aSC2

-L

I

-=-J~
~

22 pF

b
I

YY

DJ---1~

I

4.8 MHz

22 pF

--

,ROI

IRQ

~>

~~,

""'?,

19

TOO

10K
AAA

PLMA

TCAP2

PLMB

TCMP2

TeMPI

TCAPI

SCLK

:

.~ ~
.> ~ ~~
.>~ >:>

"

3
4

P07
P06
P05
P04
P03
12
P02
13
.... ~ POI
~ POO

.... r---4-9

7

PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBO

PC7
PC6

24
PA7
25
PA6
26
~"'"if PA5
~ PA4
29 PA3
PA2
~ PAl
....1!. PAO
VSS

~~
l

47K

~

-

'"

47K

33
34
35

AAA
"''''Y

~

;

#
38

47K

.......

AA

39

-==42
43

~

PC'o

}~

AAA

"''''

PC4

PCl

A~~
YYT

22

~

PC2

....

D

PC5

PC3

"'''''''

46
47
48

~
"
~

49

' ...

.:a......
'LollI
"....

"

VRL

~7
..:..NOTE: Pin

numbe~sare

valid for 52-pin PLCC Package only.

Figure 4. Self-Check Circuit Sche~atic Diagram;'

MOTOROLA MICROPROCESSOR'DATA
3-718

A~o..
YVY

A~q.
"'''''''
A~'l.

"''''....-

A~o..
YY'"

1
GNO
+5V

+9V

MC68HC05B4

INTP -

External Interrupt Positive
Allows a choice,of IRQ sensitivity, with INTN. See
Table 4.
INTN - External Interrupt Negative
Allows a choice of IRQ sensitivity, with ,INl;P. See
Table 4.
INTE - External Interrupt Enable
Allows the user to enable,or disable the external interrupt function
SFA - Slow/Fast Selection for PLMA
1 ~ Slow speed used for PLMA (4096 times the timer
clock period)
o= Fast speed used for PLMA (256 times the timer
,clock period). See PULSE-LENGTH D/ACONVERTERS
SFB - Slow/Fast Selection for PLMB
1 = Slow speed used for PLMB (4096 times the timer
clock period)
0= Fast speed used for PLMB (256 times the timer
clock period). See PULSE-LENGTH D/A CONVERTERS
SM - Slow Mode
1= System runs at 1/16th the normal clock rate (fost'::1
32)
0= System runs at normal clock rate (fosci2)
WDOG - Watchdog Counter System
1 =Watchdog counter system enabled
'0 ~ Watchdog counter system disabled

AID CONVERTER CHECK SUBRQUTINE
This subroutine returns with the Z bit cleared if any
error is detected; otherwise, the Z bit is set. The subroutine is called at location $1 FAA with X = $00 and AID STATI
CTRL (address $09) = $20 (ADON =' 1 for more than 100
t-LS and channel PDO selected). Conversion is done on
three of the internal channels: VRH, VRL, and (VRL + VRH)I
2. The result of these conversions is verified at ::': 1 LSB.
Upon return to the user's program, if the test passed,
X 0' $09, A=$OO or $01.
ROM CHECKSUM SUBROUTINE

This subroutine returns with the Z bit cleared if any
error is detected; otherwise, theZ bit is set. The HOM
checksum subroutine is called at location $0232 with RAM
location $0053 equal to $01 and A = O. A short routine is
set up and executed in RAM to compute a checksum of
the entire ROM pattern. RAM locations $0050 through
$0053 are overwritten. Upon return to the user's program,
if the test passed, X = 0, A= O.
NOTE

The AiD and the watchdog system are turned on
when calling this subroutine.

RESETS

NOTE

The MCU can be reset two ways: by initial power-up
(PaR) and by the external reset input (RESET). The RESET
input consists mainly of a Schmitt trigger that senses the
RESET line logic level. '

The reset generated by the watchdog timer isa
system reset; thus, the watchdog is disabled after
a watchdog reset.

POWER-ON RESET (POR)

Table 4. External Interrupt Options

An internal reset is generated on power-upio allovv
the' internal clock generator to stabilize. The power-on
reset is strictly for power turn-on conditions and'should
not be used to detect adropin the power supply voltage.
There is a delay (tpORL) after the oscillator becomes active. If the RESET pin is low at the end of tpORL the MCU
will remain in the reset condition until RESET goes high.
A mask option allows tpORL to be either 16 or 4064 internal processor clock cycles (tcyel.
EXTERNAL RESET INPUT

The MCU is reset when a logic zero is applied to the
RESET input for a period of one and one-half machine
cycles (tcyel.
Miscellaneous Register (OC)
7
6
5

I POR

INTP

INTN

INTE

INTP

INTN

0
0

0

1
1

0

1
1

External Interrupt Options

Negative Edge and Low-Level Sensitive
Negative Edge Only
Positive Edge Only
Positive and Negative Edge Sensitive

Slow Mode

The slow mode funetionis controlled by the SM bit in
the miscell.aneous register (OC). In slow mode (SM = 1),
an extra divide-by-sixteen circuit is added between the
oscillator and the internal clock driver. This slows all func'tions bya factor of 16 (including SCI, AID, and timer),
which is particularly useful in WAIT mode. SM is cleared
by external or power-on reset and by STOP mode.
NOTE

SFA

SFB

SM

IWDOG I

RESET:
U

If slow mode is enabled while using the AID, the
internal AID RC oscillator should be turned on.
Watchdog System

paR - Power-On Reset
1 = The reset occurring is a power-on, not external,
reset
0= Power-on reset not in progress

The watchdog counter is driven by the 1024 prescaler
in the timet and, unless the counter is reset, generates a
system reset when it reaches its maximum count
(1024x8).

MOTOROLA' MICROPROCESSOR DATA
3-719

II

MC68HC05B4

A mask option is available that provides two methods
of enabling the watchdog timer. In the first option, the
watchdog system is controlled by the WDOG bit in the
miscellaneous register (DC). Writing a one to the bit starts
the watchdog or, if it is already started, resets the counter
to zero. Writing a zero has no effect; the WDOG bit can
only be cleared by external or' power-on' reset. In the
second option, the watchdog timer is always enabled
following reset.
A second mask option determines the watchdog timer
function during WAIT. The watchdog timer can remain
active during WAIT, and can cause a reset if the device
remains in WAIT longer than the watchdog timeout period. Alternatively, the watchdog timer suspends operation during WAIT and resets its count, resuming normal
operation following reset.

Refer to Figure 6 for the reset and interrupt instruction
processing sequence.
TIMER INTERRUPT

There are three different timer interrupt flags that cause
a timer interrupt whenever they are set and enabled. The
interrupt flags are in the timer status register (TSR), and
the enable bits are in the timer control register (TCR).
Refer to TIMER for more information.

EXTERNAL INTERRUPT
If the interrupt mask bit (I bit) of the CCR is set all
interrupts are disabled. Clearing the I bit enables the external interrupt. The external interrupt is internally synchronized. and then latched 011 the falling edge of IRQ.
The action ohhe external interrupt is identical to the timer
interrupt with the exception that the interrupt request
input at IRQ is latched internally and the.service routine
address is specified by the contents of $1 FFA and $1 FFB.
Four options are available for interrupt triggering sensitivity:
• Negative edge and low level
• Negative edge only
• Positive edge only
• Positive and negative edge
See Miscellaneous Register (OC) for further information.
Figure 7 shows a mode timing diagram for the interrupt
line. The timing diagram shows two treatments of the
interrupt line to the processor. The first method shows a
single pu,lse on the interrupt line spa~ed far enough apart
to be serviced. The minimum time between. pulses is a
function of the length of the interrupt,service. Once a
pulse occurs, the next pulse should not occur until an RTI
occurs. This time (tIUU is obtained by adding 21 instruction cycles to the total number ·of cycles it takes to complete the s.ervice routine (not including ~he RTI instruction).
The second method shows many interrupt lines "wireORed" to forr:n the interrupts at the processor. If the interrupt line remains low after servicing an interrupt, then
the next interrupt is recognized. .

INTERRUPTS

II

The MCU can be interrupted four different ways: the
three maskable hardware interrupts (IRQ, SCI, and timer)
and the nonmaskable software interrupt instruction (SWI).
Interrupts cause the processor to save register contents
on the stack and to set the interrupt mask (I bit) to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal
processing to resume. The stacking order is shown in
Figure 5.
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.
NOTE
The current instruction is the one already fetched
and being operated on.

When the current instruction is complete, the processor
checks all pending hardware interrupts. If unmasked (I
bit clear) and if the corresponding interrupt enable bit is
set, the processor proceeds with interrupt processing;
otherwise, the next' instruction is fetched and executed.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first.The SWI is executed the
same as any other instruction, regardless ohhe I-bit state.

NOTE
The internal interrupt latch is cleared in the first part
of the interrupt service routine; therefore, one external interrupt pulse CQuid be latched and serviced
as soon as the I bit is cleared.
STACK

1

JIll I

CONDITION CODE REGISTER
ACCUMULATOR

INCREASING MEMORY
ADDRESSES

INDEX REGISTER

oI 0 I 0 I

PCH
PCl

n

DECREASING MEMORY
ADDRESSES

U

P

UNSTACK

T

NOTE: Since the Stack Pointer decrements during pushes, the
PCLis stacked first, followed by PCH, etc. Pulling from
the stack is in the reverse order.

Figure 5. Interrupt Stacking Order

MOTOROLA MICROPROCESSOR DA"fA
3"720

MC68HC05B4

CLEAR IRQ
REQUEST
LATCH

II
LOAD PC FROM:
SWI: $1 FFC-$l FFD
SWI: $lFFA-$lFFB
TIMER: $lFFS-$lFF9
SCI: $lFF6-$lFF7

·COMPLETE
INTERRUPT
ROUTINE
AND EXECUTE
RTI

Figure 6. Reset and Interrupt Processing Flowchart

SOFTWARE INTERRUPT (SWI)

SCI INTERRUPTS

The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. If the I bit
is zero, SWI executes after the other interrupts. The SWI
operation is similar to the hardware interrupts. The interrupt service routine address is specified by the contents of memory locations $1 FFC and $1 FFD.

An interrupt in the SCI occurs when one ofthe interrupt
flag bits in the serial communications status register is
set, provided the I bit in the CCR is clear and the enable
bit in the serial communications control register 2 is set.
Software in the serial interrupt service routine must determine the cause and priority of the SCI interrupt by

MOTOROLA MICROPROCESSOR DATA
3-721

MC68HC0584

U

IRQ~tILlH

I...

E~ge~Sel'lsitive Trigger Condition
The minimum pulse width (tiL/H) is either
125ns (VOO=5 V) or 250 ns (VOO=3 V).
The period tlLlL should not be less than
the number of tcyc cycles it takes to execute the interrupt service routine plus 21
tcyc cycles.

~1

tILlL-----l..

Level-Sensitive Trigger Condition
If after servicing an interrupt the IRQ remains low, then the next interrupt is recognized.
NORMALLY
USED WITH
WIRE-ORed
CONNECTION

IRQn

r

IRQ--,
(MCUI
I'-_ _ _ _ _ _ _ _ _ _~

I

Figure 7. External Interrupt Mode Diagram

STOP

examining the interrupt flags and status bits in the SCI
status register.

STOP OSCILLATOR
AND ALL CLOCKS

LOW-POWER MODES

CLEAR I BIT

STOP

The STOP instruction places the MCU in its lowest power
consumption mode. In the STOP mode, the internal oscillator is turned off, halting all internal processing including timer, SCI, and A/D operation (refer to Figure 8).
During the STOP mode, the TCR bits are altered to
remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is
cleared. The I bit in the CCR is cleared to enable external
interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the STOP mode only by an
external interrupt or reset.

YES

SCI during STOP Mode

When the MCU enters the STOP mode, the baud rate
generator stops, halting all SCI activity. If the STOP instruction is executed during a transmitter transfer, that
transfer is halted. If a low input to the IRQ pin is used to
exit STOP mode, the transfer resumes. If the SCI receiver
is receiving data and the STOP mode is entered, received
data sampling stops because the baud rate generator
stops, and all subsequent data is lost. For these reasons,
all SCI transfers should be in the idle state when the STOP
instruction is executed.

(11 FETCH RESET VECTOR DR
(21 SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT
ROUTINE

Watchdog during STOP Mode

The STOP instruction is inhibited when the watchdog
system is enabled. If a STOP instruction is executed while
the watchdog is enabled, a reset occLirs that resets the
entire MCU.

Figure 8. STOP Function Flowchart

MOTOROLA MICROPROCESSOR DATA
3-722

MC68HC05B4

PLM during STOP Mode

When the MCU enters stop mode, the PLM outputs
remain at their particular level. If power-on or external
reset causes the exit from stop mode, the register values
are forced to $00.

AID Converter during STOP Mode
When stop mode is entered with the AID converter
turned on, the AID clocks a(e stopped and the AID converter is disabledfor the duration of stop mode, including
the tpORL startup time. If the AID RC oscillator is used,
it will also be disabled.
When leaving STOP mode, after the tpORL startup time,
the AID converter and AID RC oscillator resume regular
operation. However, a time tADON is required for the
current sources to stabilize. During tADON, AID conversion results may be inaccurate.

OSCILLATOR ACTIVE
TIMER. SCI, AND AID
CLOCKS ACTIVE
PROCESSOR' CLOCKS STOPPED

WAIT

The WAIT instruction places the MCU in a low-power
consumption mode, but the WAIT mode consumes more
power than the STOP mode. All CPU action and the
watchdog system are suspended, but the timer, SCI, PLM,
and AID remain active (refer to Figure 9). An interrLlpt
from the timer, SCI, or an IRQ can cause the MCU to exit
the WAIT mode.
During the WAIT mode, the I bit in the CCR is cleared
to enable interrupts. All other registers, memory, and
input/output lines remain in their previous state. The timer
may be enabled to allow a periodic exit from the WAIT
mode.
To achieve proper operation and reduce power consumption, the following points should be set as desired
before entering wait mode:
• Timer interrupt enable bits

• AID control bits
• SCI enable bits and interrupt enable bits

II
(1) FETCH RESET VECTOR OR

(2) SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT
ROUTINE

Figure 9. WAIT Function Flowchart

NOTE

TIMER
The timer consists of a 16-bit, software-programmable
counter driven by a fixed divide-by-four prescaler. This
timer can be used for many purposes, including input
waveform measurements of two input signals while simultaneously generating two output waveforms. Pulse
widths can vary from several microseconds to many sec-:'
onds. The programmable timer works in conjunction with
the PLM system to execute two 8-bit DIA PLM conversions, with a choice oftwo repetition rates. Referto Figure
10 for a timer block ·diagram.
Because the, timer ,has a 16-bit architecture, each specific functional segrnent(capability),is represented by two
registers. These registers contain the high and low byte
of that functional segment. Generally, accessing the low
byte of a specific timer function allows full. control of that
function; however, an access of the high byte inhibits
that specific timer function until the low byte is also accessed.

The I bit in the CCR should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does
not occur.
COUNTER

The key element in the programmable timer is a 16bit, free-running counter or counter register, preceded by
a prescaler .that divides the internal processor clock by
four. The prescaler gives the timer a resolution of 2.0
microseconds if the internal bus clock is 2.0 MHz. The
counter'is incremented during the low portion of the internal bus clock. Software can read the counter at any
time without affecting its value.
..
The double-byte, free-running counter can be read from
either of two locations, $18-$19 (counter register) or
$1A-$1 B (counter alternate, register). A read from only
the leastsignificantbyte (LSB) ofthefree-running. counter
($19, $1 B) receives the count value 'at the time of the r.ead.

MOTOROLAMI.CROPROCESSOR. DATA

3·723

MC68HC05B4

MCU INTERNAL BUS

HIGH
BYTE

COUNTER
ALTERNATE
REGISTER

LOW
BYTE

HIGH
BYTE

LOW
BYTE

HIGH
BYTE

LOW
BYTE

HIGH
BYTE

LOW
BYTE

$16

$1E

$14

S1C

$17

$1F

$15

$10

$1A
$1B

TO PLM

II
TIMER
STATUS
REGISTER
$13

TIMER
'CONTROL
REGISTER
$12

INPUT
CAPTURE
INTERRUPT
$1FF8,8

OUTPUT
COMPARE
INTERRUPT
$1FF6,7

OVERFLOW
INTERRUPT
$1FF4, 5

Figure 10. Timer Block Diagram

If a read of the free-running counter or counter alternate
register first addresses the most significan't byte (MSB)
($18, $1A), the LSa($19, $1B) is transferred to a buffer.
This buffer value remains fixed after the first MSB read,
even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or
counter alternate register LSB ($19 or $1 B) and, thus,
completes a read sequence'of the total counter value. In
reading either the free-running'counter or counter alternate register, if the MSB is read, the LSB must also be
read to complete the sequence.

The counter alternate register differs from the counter
register in one respect: a read of the counter register LSB
can clear the timer overflow flag (TOn Therefore, the
counter alternate register can be read at any time without
the possibility of missing timer overflow interrupts due
to clearing of the TOF.
The free-running counter is configured to $FFFC during
reset and is always a read-only register. During a poweron reset, the counter is also preset to $FFFC and begins
running 'after the oscillator start-up delay. Because the
free-running counter is 16 bits preceded by a fixed divide-

MOTOROLA MICROPROCESSOR DATA
3..724

MC68HC05B4

by-four prescaler, the value in the free-running counter
repeats every 262,144 internal bus clock cycles. When the
counter rolls over from $FFFF to $0000, the TOF bit is set.
An interrupt can also be enabled when counter rollover
occurs by setting its interrupt enable bit (TOlE).

NOTE
Since the PLM system uses the timer counter, PLM
results will be affected when resetting this counter.

OUTPUT COMPARE REGISTERS
There are two output compare registers: output compare register 1 (OCR1) and output compare register 2
(OCR2). The output compare registers can be used for
several purposes, such as controlling an output waveform or indicating when a period of time has elapsed. All
bits are readable and writable and are not altered by the
timer hardware or reset. If the compare function is not
needed, the four bytes of the output compare registers
can be used as storage locations.

$1 E (most significant byte) and $1 F (least significant byte).
The function of OCR2 is identical to OCR1, requiring only
changes of the register locations and control bits in the
timer status register ($13) to make the OCR1 description
apply to OCR2.

SOFTWARE FORCE COMPARE
The MCU provides a force compare capability to faci 1itate fixed frequency generation as well as other applications. Bit 3 (FOLV1 for OCR1) and bit 4 (FOLV2 for OCR2)
in the timer control register ($12) implement this force
compare. Writing a one to these bits causes the O~VL 1
or OLVL2 values to be copied to the respective output
registers (TCMP1 or TCMP2 pins). Internal logic allows a
single instruction to change OLVL1 and OLVL2 and cause
a forced compare with the new values of OLVL 1 and
OLVL2.
NOTE
A software force compare, which affects the corresponding output pin TCMP1 or TCMP2, does not
affect the compare flag; thus, it does not generate
an interrupt.

NOTE
The same output compare interrupt enable bit is
used for the two output compares.
Output Compare Register 1

The output compare register 1 (OCR1) is a 16-bit register, which is made up of two 8c bit registers at locations
$16 (most significant byte) and $17 (least significant byte).
The output compare register contents are continually
compared with the contents of the free-running counter
and, if a match is found, the corresponding output compare flag (OCF1, bit 6 of timer status register $13) is set,
and the corresponding output level (OLVL 1) bit is clocked
to pin TCMP1. The output compare register values and
the output level bit should be changed after each successful comparison to control an output waveform or
establish a new elapsed timeout. An interrupt can also
accompany a successful output compare, provided the
corresponding interrupt enable bit, OCIE, is set.
After a processor write cycle to the output compare
register 1 containing the most significant byte ($16), the
output compare 1 function is inhibited until the least significant byte ($17) is also written. The user must write
both bytes (locations) if the most signifjcant byte is vyritten first. A write made only to the least significant byte
($17) will not inhibit the compare function. The free-running counter is updated every four internal bus clock
cycles. The minimum time required to update the output
compare register 1 is a function of the program rather
than the internal hardware.
The processor can write to either byte of the output
compare register 1 without affecting the other byte. The
output level (OLVL 1) bit is clocked to the corresponding
output level register and then to the TCMP1 pin, regardless of whether the output compare flag (OCF1) is set or
clear.
Output Compare Register 2

The output compare register 2 (OCR2) is a 16-bit register, which is made up of two 8-bit registers at locations

INPUT CAPTURE REGISTERS
There are two input capture registers: input capture
register 1 (lCR1) and input capture register 2 (lCR2).
NOTE
The same input capture interrupt enable bit (lCIE)
is used for the two input capture registers.
Input Capture Register 1

Two 8-bit registers that make up the 16-bit input capture register 1 (lCR1) are read-only and are used to latch
the value of the free-running counter after the .corresponding input capture edge detector senses a defined
transition. The level transition that triggers the counter
transfer is defined by the corresponding input edge bit
(lEDG1). Reset does not affect the contents of the input
capture register.
The result obtained by an input capture will be one
more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is one count of the free-running
counter, which is four internal-bus clock cycles.
The free-running counter contents are transferred to
the input capture register on each proper signal transition, regardless of whether the input capture flag (lCF1)
is set or clear. The input captureregi\>ter always contains
the free-running counter value, which corresponds to the
most recent input capture.
After a read of the input capture register 1 ($14) most
significant byte, the counter transfer is inhibited until the
least significant byte ($15) is also read. This characteristic
causes the time used in the input capture software routine
and its interaction with the main program to determine
the minimum pulse period.

MOTOROLA MICROPROCESSOR DATA
3-725

I

MC68HC05B4

A read of the input capture register 1 least significant
byte ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus
clock.

TIMER STATUS REGISTER'(TSR) $13

The TSR is a read-.only register containing three status
flag bits. Bits 4-0 always read zero.
,4

ICFl

Input Capture Register 2

The input capture register 2 (ICR2) is a 16-bit register
that is composed of two 8-bit registers at locations $1 C
(most significant byte) and $1 D (least significant byte).
Input capture register 2 functions identically to input capture register 1, except that only negative edge sensitivity
is. available. Bysubstituting the appropriate bits in the
timer status register ($13)' and substituting register locations; thelCR1 description applies to ICR.2.

TIMER CONTROL REGISTER (TCR) $12

I

The TCR is an 8-bit read/write register, illustrated below
with a definition of each bit.

ICIE

OCIE

TOlE

4

3

I FOLV21

FOLVl

2

1

0

I OLVL211EDGl I OLVLl I

RESET:

o

u

ICIE - Input Capture Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
OCIE- Output Compare Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
TOlE - Timer Overflow Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
FOLV2 ~ Force Output Compare 2
1 = Forces the OLVL2 bit to the corresponding output
latch
0= No effect
FOLV1- Force Output Compare 1
1 = Forces the OLVL 1 bit to the corresponding output
latch
0= No effect
OLVL2 - Output Level 2
1 = The value of the output level 2 bit, which is copied
to the output level latch by the next successful
output compare 2, appears atTCMP2
O=No effect
IEDG1 ~ Input Edge One
Value 'of input edge determines which level transition
on TCAP1 pin will triggerfree~running counter transfer
to the input capture'register.
1= Positive edge
0= Negative edge
OLVL 1 - Output Level One
Value of output level, which is clocked into output level
register by the next successful output compare 1, will
appear on the TeMP pin.
1 = High output
0= Low output

OCFl

TOF

ICF2

u

u

om

RESET:
U

ICF1 - Input Capture Flag One
1 = Flag set when selected polarity edge is sensed by
input capture edge detector
0= Flag cleared when TSR and input capture 1 low
register ($15) are accessed
OCF1 - Output Capture Flag One
1 = Flag set when output compare register contents
match the free~running counter contents
0= Flag cleared when TSR and output compare 1 low
register ($17) are accessed
TOF - Timer Overflow Flag
1 = Flag set when free-running counter transition from
$FFFF to $0000 occurs
0= Flag cleared when TSR and CQunter low register
($19) are accessed
ICF2 - Input Capture Flag Two
1 = Flag set when selected polarity edge is sensed by
input capture 2 edge detector
0= Flag cleare.d when TSR and input capture 2 low
register ($10) are accessed
OCF2 - Output Capture Flag Two
1 = Flag s~t when output compare register contents
match the free-running counter contents
0= Flag cleared when TSR and output compare low
register 2 ($1 F) are accessed
Bits 0-2 - Not Used
Can read either zero or one.
TIMER DURING WAIT MODE

The CPU clock halts during the WAIT mode, but the
timer remains active. An interrupt from the timer causes
the processor to exit the WAIT mode.
TIMER DURING STOP MODE

In the STOP mode., the timer stops counting and holds
the last count value if STOP is exited by an interrupt. If
reset is used, the counter is forced to $FFFC. During STOP,
if at least one valid input capture edge occurs at,the TCAP
pin, the input capture detect circuit is arm~d. This .does
not set any timer flags or wake up the MCU, but when
the MCU does wake up, there is an active input capture
flag and data from the first valid edge that occurred during the STOP mode. If reset is used to exit STOP mode,
then no input capture flag or data remains, even if a valid
input capture edge occurred.
'
Accessing the timer status register satisfies the first
condition required to clear status bits. The remaining step
is to access the registercorrespcinding to the status bit.
A problem can occur when using the timer overflow function and reading the free·running counterat random times

MOTOROLA MICROPROCESSOR DATA
3-726

MC68HC05B4

to measure an elapsed time. Without incorporating the
proper precautions into software, the timer overflow flag
could unintentionally be cleared if 1) the timer status
register is read or written when TOF is set, and 2) the
least significant byte of the free-running counter is read
but not for the purpose of servicing the flag.
The counter alternate register at address $1 A and $1 B
contains the same value as the free-running counter (at
address $18 and $19); therefore, this alternate register
can be read at any time without affecting the timer overflow flag in the timer status register.

SCI TRANSMITTER FEATURES
• Transmit data register empty flag
• Transmit complete flag
• Break send
Any SCI two-wire system requires receive data in (RDI)
and transmit data out (TOO).

DATA FORMAT
Receive data in (RDI) or transmit data out (TOO) is the
serial data presented between the internal data bus and
the output pin (TOO) and between the input pin (ROI) and
the internal data bus. Data format is as shown for the
NRZ in Figure 11.

SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous SCI is provided with a
standard NRZ format and a variety of baud rates.The SCI
transmitter and receiver are functionally independent but
use the same data format and baud rate prescaler. The
terms baud and bit rate are used synonymously in the
following description.

SCI TWO-WIRE SYSTEM FEATURES
• Standard NRZ (mark/space) format
• Advanced error detection method includes noise detection for noise duration of up to one-sixteenth bit
time
• Full-duplex operation (simultaneous transmit and receive)
• Software programmable for one of 32 different baud
rates
• Different baud rates possible for transmit and receive
• Software-selectable word length (eight- or nine-bit
words)
• Separate transmitter and receiver enable bits
• SCI may be interrupt driven
• Four separate interrupt conditions

SCI RECEIVER. FEATURES
•
•
•
•
•
•

Receiver wake-up function (idle or address bit)
Idle line detect
Framing error detect
Noise detect
Overrun detect
Receiver data register full flag

WAKE-UP FEATURE
In a typical multiprocessor configuration, the software
protocol will usually identify the addressee(s) at the beginning of the message. To permit uninterested MPUs to
ignore the remainder of the message, a wake-up feature
is included, whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until its data line
returns to the idle state. An SCI receiver is re-enabled by
an idle string of at least ten (or eleven) consecutive ones.
Software for the transmitter must provide for the required
idle string between consecutive messages and prevent
it from occurring within messages.
A second wake-up method is available in which sleeping SCI receivers can be awakened by a logic one in the
high-orde~ bit of a received character.
RECEIVE DATA IN
Receive data in (ROI) is the serial data which is presented from the input pin via the SCI to the receive data
register (ROR). While waiting for a start bit, the receiver
samples the input at a rate 16 times higher than the set
baud rate. This' increased rate is referred to as the RT
rate. When the input (idle) line is detected low, it is tested
for three more sample times. If at least two of these three
samples detect a logic low, a valid start bit is assumed
to be detected. If in two or more samples, a logic high is
detected, the line is assumed to be idle. The receive clock
generator is controlled by the baud rate register (see Figure 13); however, the SCI is synchronized by the start bit
independent of the transmitter. Once a valid start bit is
detected, the start bit, each data bit, and the stop bit are

CONTROL BIT "M"
SELECTS 8 OR 9 BIT DATA

o

o

*
IDLE LINE

S
T
A
R

s
*Stop bit is always high.

T

_L

1

1..0--

T

S
T

P

A
R

o

T
Figure 11. Data Format

MOTOROLA MICROPROCESSOR DATA
3-727

II

MC68HC05B4

each sampled three times. The value of the bit is determined by voting logic, which takes the value of a majority
of samples. A noise flag is set when all three samples on
a valid start bit, data bit, or stop bit do not agree. A noise
flag is also set when the start verification samples do not
agree.
START BIT DETECTION FOLLOWING A FRAMING ERROR

II

If there has been a framing error (FE) without detection
of a break (10 zeros for 8-bit format or 11 zeros for a 9bit format), the circuit continues to operate as if there
actually were a stop bit, and the start edge will be placed
artificially. The last bit received in the data shift register
is inverted to a logic one, and the three logic-one start
qualifiers are forced into the sample shift register during
the interval when detection of a start bit is anticipated;
therefore, the start bit will be accepted no sooner than it
is anticipated.
If the receiver detects that a break (RORF = 1, FE = 1,
receiver data register = $00) produced the framing error,
the start bit will not be artificially induced, and the receiver must actually receive a logic one before start.
SCI SYNCHRONOUS TRANSMISSION

The SCI transmitter allows a one-way synchronous
transmission, with the SCLK pin as the clock output. No
clock is sent to the SCLK pin during the stop and start
bits. The LCL bit (SSCR1) controls whether clocks are
active during the last valid data bit (address mark). The
CPOL bit selects clock polarity, and the CPHA bit selects
the phase of the external clock. Ouring idle, preamble,
and send break, the external SCLK clock is not active.
These options allow the SCI to control serial peripherals consisting of shift registers without losing any function of the SCI transmitter. These options do not affect
the SCI receiver, which is independent of the transmitter.
The SCLK pin works in conjunction with the TOO pin.
When the SCI transmitter is disabled, the SCLK and the
TOO pins assume a high-impedance state.
NOTE

THE LBCL, CPOL and CPHA bits must be selected
before the transmitter is enabled to ensure that the
clocks function correctly. These bits should not be
changed while the transmitter is enabled.

register 2 (SCCR2) provides control bits that individually
enable/disable the transmitter or receiver, enable system
interrupts, and provide wake-up enable, and send break
code bits. The baud rate register bits allow the user to
select different baud rates for the transmitter and receiver.
Oata transmission is initiated by a write to the serial
communications data register (SCOAT). Provided the
transmitter is enabled, data stored in the SCOAT is transferred to the transmit data shift register. Th is data transfer
sets the SCI status register (SCSR) transmit data register
empty (TORE) bit and generates an interrupt if the transmit interrupt is enabled. Oata transfer to the transmit data
shift register is synchronized with the bit rate clock. All
data is transmitted LSB first. Upon completion of data
transmission, the transmission complete (TC) bit is set
(provided no pending data, preamble, or break code is
sent), and an interrupt is generated if the transmit complete interrupt is enabled. If the transmitter is disabled,
and the data, preamble, or break code has been sent, the
TC bit will also be set, which will also generate an interrupt if the TCIE bit is set. If the transmitter is disabled in
the middle of a transmission, that character will be completed before the transmitter gives up control of the TOO
pin.
When the SCOAT is read, it contains the last data byte
received, provided that the receiver is enabled. The SCSR
receive data register full (RORF) bit is set to indicate that
a data byte is transferred from the input serial shift register to the SCOAT, which can cause an interrupt if the
receiver interrupt is enabled. Oata transfer from the input
serial shift register to the SCOAT is synchronized by the
receiver bit rate clock. The SCSR overrun (OR), noise flag
(NFL or FE bits are set if data reception errors occur.
An idle line interrupt is generated if the idle line interrupt is enabled and the SCSR 10LE bit (which detects idle
line transmission) is set. This allows a receiver that is not
in the wake-up mode to detect the end of a message, the
preamble of a new message, or to resynchronize with
the transmitter. A valid character must be received before
the idle line condition for the IDLE bit to be set and for
an idle line interrupt to be generated.
REGISTERS

There are five registers used in the SCi; the internal
configuration of these registers is discussed in the following paragraphs.

TRANSMIT DATA OUT

Transmit data out (TOO) is the serial data presented
from the transmit data register (TDR) via the SCI to the
output pin. The transmitter generates a bit time by using
a derivative of the RT clock, producing a transmission
rate equal to one-sixteenth that of the receiver sample
clock (if the same baud rate is used for transmit and
receive).

Serial Communications Data Register (SCDAT) $11

The SCDAT is a read/write register used to receive and
transmit SCI data.

SCD7

SCD6

SCD5

RESET:
U

FUNCTIONAL DESCRIPTION

A block diagram of the SCI is shown in Figure 12. The
user has option bits in the serial communications control
register 1 (SCCR1) to determine the SCI wake-up method
and data word length. Serial communications control

SCD4

SCD3

SCD2

SCDl

SCDO

u

As shown in Figure 12, SCOAT functions as two separate registers. The transmit data register (TOR) provides
the parallel interface from the internal data bus to the
transmit shift register. The receive data register (ROR)

MOTOROLA MICROPROCESSOR DATA
3-728

$11
(SEE NOTE)

s:

~

TDO
PIN

TRANSMIT
DATA
REGISTER

TRANSMIT
DATA
SHIFT
REGISTER

I

•

:lJ

o

!j;

s:

W

.:...

N
CD

n
:lJ
0

"'a

:lJ

o(')

m

fI)
fI)

NOTE: The Serial Communications Data
Register (SCI SCDAT) is controlled by the internal R/W signal. It is the transmit data register when written and receive data register
when read.

o:lJ
C

~
CLOCK EXTRACTION
PHASE AND
POLARITY
CONTROL

TRANSMITIER
CLOCK

RECEIVER
CLOCK

SCCR1
$OE

Figure 12. SCI Block Diagram

MC68HC05B4

provides the interface from the receive shift register to
the internal data bus.
Serial Communications Control Register 1 (SCCR1) $OE

The CPOL bit should not be changed with the transmitter active.
CPHA -

The SCCR1 provides control bits that determine word
length, select the wake-up method, and control the options to output the transmitter clocks for synchronous
transmissions.
3
R8
RESET:
U

I

T8

M

U

U

U

IDLE OR

CLOCK

The CPHA bit should not be changed with the
transmitter active.
LBCL -

Last Bit Clock

Selects whether the clock associated with the last data
bit transmitted is output to the SCLK pin.

U

R8 - Receive Data Bit 8
R8 bit provides storage location for the ninth bit in the
receive data byte (if M = 1).
T8 - Transmit Data Bit 8
T8 bit provides storage location for the ninth bit in the
transmit data byte (if M = 1).
M - SCI Character Word Length
1 = one start bit, nine data bits, one stop bit
0= one sta~t bit, eight data bits, one stop bit
WAKE - Wake-Up Select
Wake bit selects the receiver wake-up method.
1 = Address bit (most significant bit)
0= Idle line condition
CPOL - Clock Polarity
Selects the clock polarity sent to the SCLK pin.
1 = Steady state high outside the transmission window
0= Steady state low outside the transmission window

PRECEDING
TRANSMISSION

0= SCLK line activated in the middle of the data bit
(see Figures 13 and 14)

1

I WAKE I CPOL I CPHA I LBCL

Clock Phase

Selects the clock phase sent to the SCLK pin.
1 = SCLK line activated at the beginning of the data
bit

1 = Last data bit output
0= Last data bit not output
The last dataqit is the eighth or ninth bit, depending on whether an 8- or 9-bit format is used (see
Table 5).
The LCBL bit should not be changed while the
transmitter is enabled.
Bit 5 -

Not used.

o.

Can be either lor
Table

~.

SCI Clock on SCLK Pin
Number of
Clocks on
SCLK Pin

Data
Format

M Bit

LBCL Bit

8 Bit

0

0

7

8 Bit

0

1

8

9 Bit

1

a

8

9 Bit

1

1

9

START
M = 0 tB DATA BIT
STOP
IDLE OR
~I~ ----------------------------~~~I~~

I

I
I

I :

I
I

I

ICPOL = 0 CPHA = 0)
CLOCK
ICPOL=O CPHA= 1)
CLOCK
ICPOL = 1 CPHA = 0)
CLOCK
ICPOL = 1 CPHA= 1)
DATA
MSB STOP

START LSB

*LBCL Bit Controls Last Data Clock

Figure 13. SCI Data Clock Timing Diagram (M=O)

MOTOROLA MICROPROCESSOR DATA
3-730

NEXT TRANSMISSION

MC68HC05B4

START
M = 1.9 DATA BIT
STOP
IDLE OR
~I--+-I------------~~I ~~

IDLE OR
PRECEDING
TRANSMISSION
CLOCK

I
I

I

I

II

·1 NEXT TRANSMISSION

I

-----t--~

(CPOL = 0 CPHA = 01
CLOCK

----t---!

(CPOL=O CPHA=11
CLOCK

.-----+----.;-..,

(CPOL = 1· CPHA = 01
CLOCK
(CPOL= 1 CPHA= 11
DATA

*LBCL Bit Controls Last Data Clock

Figure 14.. SCI Data CLock Timing Diagram (M=1)

The address bit is dependent on both the wake·bit and
the M-bit level. Additionally, the receiver does not use
the wake~up feature unless the RWU control bit in SCCR2
is set.
Wake

M

Receiver Wake-Up

0

X

Detection of an idle line allows the next data
byte received to cause the receive data register to fill and produce an RDRF flag.

1

0

Detection of a received one in the eighth
data bit allows an RDRF flag and associated
error flags.

1

1

Detection of a received one in the ninth data
bit allows an RDRF flag and associated error
flags.

Serial Communications Control Register.2 (SCCR2) $OF
The SCCR2 provides control of individual SCI functions
such as interrupts, transmit/receive enabling, receiver
wake-up, and break code.

I

TIE

TCIE

RIE

ILiE

TE

RE

RWU

SBK

RESET:

o
TIE - Transmit Interrupt Enable
1 = SCI interrupt enabled, provided TDRE is set
0= TDRE interrupt disabled
TCIE - Transmit Complete Interrupt Enable
1 =SCI interrupt enabled, provided TC is set
0= TC interrupt disabled

MOTOROLA

RIE - Receive Interrupt Enable
1 = SCI interrupt enabled, provided OR or RDRF is set
0= RDRF and OR interrupts disabled
ILiE - Idle Line Interrupt Enable
1;= SCI interrupt enabled, provided IDLE is set
0.= Idle interrupt disabled
TE - Transmit Enable
1 = Transmit shiftregister output is applied to the TDO
line, and the corresponding clocks are applied to
the SCLK pin. Depending upon the SCCR1 M bit,
apreamble.of 10 (M = 0) or 11(M = 1) consecutive
ones i.s transmitted.
0= Transmitter disabled after last byte is loaded in
the SCDAT and TDRE is set. After last byte is
transmitted, TDO line becomes a high-impedance
line.
RE - Receive Enable
1= Receiver shift register input is applied to the RDI
line.
0= Receiver disabled and RDRF, IDLE, OR, NF, and
FE status bits are inhibited.
RWU - R~ceiver Wake-Up
1;= Places receiver in sleep mode and enables wakeup function
0= Wake-up function disabled after receiving data
word with MSB set (if WAKE = 1)
Wake-up function also disabled afterreceiving 10
(M = 0) or 11(M = 1) consecutive ones (.if WAKE = 0)
SBK - Send Break
1 = Transmitter continually sends blocks of zeros (sets
of 10 or 11) until cleared. Upon completion of
break code, transmitter sends one high bit for recognition of valid start bit.
O=Transmitter sends 10 (M=O) or 11 (M=1) zeros
then reverts to an idle state or continues sending

MI~ROPROCESSORDATA

3-731

II

MC68HC05B4

data. If transmitter is ~mpty and idle, setting and
clearing the SBK bit may queue up to two character times of break because the first break transfers immediately to the shift register, and the
second is queued intothe parallel transmit buffer.

errors, processor will only recognize the overrun
error. Further data transfer into the RDR is inhib'
ited until FE is cleared.
0= FE is cleared by reading the SCSR, followed by a
read of the RDR.
Bit 0 - Not used
Can read either one or zero

Serial Communications Status Register (SCSR) $10

The SCSR provides inputs to the SCI interrupt logic
circuits. Noise flag and framing error bits are also contained in the SCSR.

TDRE

TC

RDRF

IDLE

OR

NF

Baud Rate Register $00

FE

RESET:

II

TORE - Transmit Data Register (TDR) Empty
1 = TDR contents transferred to the transmit data shift
register
0= TDR still contains data. TDRE is cleared by reading
the SCSR, followed by a write to the TDR.
TC - Transmit Complete
1 = Indicates end of data frame, preamble, or break
condition has occurred if:
1. TE = 1, TDRE = 1, and no pending data, preamble or break is to be transmitted; or
2. TE = 0 and the data preamble or break (in the
transmit shift register) has been transmitted.
0= TC bit cleared by reading the SCSR, followed by
'
a write to the TDR
The TC bit is a status register that indicates one of
the above conditions has occurred. It does not inhibit the transmitter in any way.
RDRF - Receive Data Register' (RDR) Full
1 = Receive data shift register contents transferred to
the RDR
0= Receive data shift register transfer did not occur.
RORF is cleared by reading the SCSR, followed
by a read of the RDR
IDLE - Idle Line Detect
1 = Indicates receiver has detected an idle line
0= IDLE is cleared by reading the SCSR, followed by
a read of the RDR. Once IDLE is cleared, IDLE
cannot be set until RDI line becomes active and
idle again.
OR - Overrun Error
1 = Indicates receive data shift register data is ready
to be sent to a full RDR (RDRF'= 1). Data causjng
the overrun is lost, and RDR data is not disturbed.
0= OR is cleared by reading the SCSR, followed by
a read of the RDR.
NF - Noise Flag
1 = Indicates noise is present on the receive bits, in, cluding the start and stop bits. NF is not set until
RDRF= 1.
'
0= NF is cleared by reading the SCSR, followed by
a read of the RDR.
FE - Framing Error
1 = Indicates stop bit not detected in re.ceived data
character. FE is set the same timeRDRF is set. If
received byte causes both framing and overrun

The baud rate register selects the SCI transmitter and
receiver baud rate. The SCPO and SCP1 prescaler bits are
used in conjunction with the SCR2-SCRO bits to generate
the receiver baud rate and in conjunction with the
SCT2-SCTObaud rate bits to generate the transmitter
baud rate.
Tables 6 and 7 tabulate the divide chain used to obtain
the baud rate clock (transmit or receive clock). The actual
divider chain is controlled by the combined SCP1-SCPO
and SCR2~SCRO or SCT2-SCRO bits in the baud rate register. The divided frequencies shown in Table 6 represent
the final baud rate that results from prescaler clock division only (SCR or SCT bits all zero). Table 7 lists the
prescaler output frequency divided by the action of the
SCR or SCi bits.
For example, assume that a 9600-Hz baud rate is desired from a 2.4576-MHz system clock cry tal. The prescaler bits could be set for either a divide-by-one or divideby-four. If a divide-by-four prescaler is used, then the SCR
and SCT bits must be set for divide-by-two .. The same
result, using the same crystal frequency, can be obtained
with a prescaler divide-by-one and SCR and SCT bit di.
vide-by-eight.

SCPl

SCPO

SCT2

SCTl

SCTO

SCR2

SCRl

SCRO

RESET:

o

u

u

SCP1-SCPO - SCI Prescaler Bit 1and 0
These two prescalerbits are used to increase the
range of standard baud rates controlled by the
SCT2-SCTO and SCR2-SCRO bits. Prescaler internal
processor clock division versus bit levels are shown
in Table 6.
.
SCT2-SCTO ---: SCI Transmit Baud Rate Selection Bits
These three bits, taken in conjunction with bits
SCP1-SCPO, are used to select the SCI transmit baud
rate. Baud rates versus bit levels are listed in Table
7.
SCR2-SCRO - SCI Recieve Baud Rate Selection Bits
These three bits, taken in conjunction with bits
SCP1-SCPO, are used to select the SCI receive baud
rate. Baud rates versus bit levels are listed in Table
7.
Load Program in RAM and Execute

This function is entered if the following conditions are
met when reset is released:
IRQ is at VDD +4 V for at, least two machine cycles after
reset

MOTOROLA MICROPROCESSOR DATA
3-732

MC68HC05B4

Table 6. Prescaler Highest Baud Rate Frequency Output
SCP Bit
1

0

Clock*
Divided By

0
0
1
1

0
1
0
1

1
3
4
13

Crystal Frequency MHz
4.194304
131.072
43.691
32.768
10.082

kHz
kHz
kHz
kHz

4.0

2.4576

125.000 kHz
41:666 kHz
31.250 kHz
9600 Hz

76.80
25.60
19.20
5.907

kHz
kHz
kHz
kHz

2.0
62.50 kHz
20.833 kHz
15.625 kHz
4800 Hz

1.8432
57.60
19.20
14.40
4430

kHz
kHz
kHz
Hz

*Refers to the internal processor clock.
NOTE: The divided frequencies shown in Table 6 represent baud rates which are the highest transmit baud rate (Tx) that can be
obtained by a specific crystal frequency and only using the prescaler division. Lower baud rates may be obtained by providing
a further division using the SCI rate select bits as shown below for some representative prescaler outputs.

Table 7. Transmit Baud Rate Output for a Given Prescaler Output
SCR/T Bits
2

1

0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Divided
By
1
2
4
8
16
32
64
128

Representative Highest Prescaler Baud Rate Output
131.072 kHz

32.768 kHz

76.80 kHz

19.20 kHz

9600 Hz

kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz

32.768 kHz
16.384 kHz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz

76.80 kHz
38.40 kHz
19.20 kHz
9600 Hz
4800 Hz
2400 Hz
1200 Hz
600 Hz

19.20 kHz
9600 Hz
4800 Hz
2400 Hz
1200 Hz
600 Hz
300 Hz
150 Hz

9600
4800
2400
1200
600
300
150
75

131.072
65.536
32.768
16.384
8.192
4.096
2.048
1.024

Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz

NOTE: Table 7 illustrates how the SCI select bits can be used to provide lower transmitter or receiver baud rates by further dividing
the prescaler output frequency. The five examples are only representative samples. In all cases, the baud rates shown are
transmit baud rates (transmit clock), and the receive clock is 16 times higher in frequency than the actual baud rate.

TCAP1 is at VDD for at least two machine cycles after
reset
PD3 is at VDD for at least 30 machine cycles after reset
PD4 is at VSS for at least 30 machine cycles after reset
User programs are loaded into RAM using the SCI port
and then executed. Data is loaded sequentially, starting
at RAM location $50, until the last byte is loaded. Program
control is then transferred to the RAM progam starting
at location $51. The first byte loaded is the count of the
number of bytes in the program plus the count byte. The
program starts at the second byte in the RAM. During
firmware initialization, the SCI is configured for'the NRZ
format (idle line, eight data bits, and stop bit). The baud
rate is 9600 with a 4-MHz crystal. Figure 15 shows a schematic for the load program in RAM and execute function.
Immediate execution can be avoided by setting the
byte count to a value greater than the length of data
loaded, which causes the firmware to wait for additional
data after loading is complete. Resetting the MCU then
allows entering any routine without disturbing the RAM
data that was loaded.
Jump to Any Address

This function is entered if the following conditions are
met when reset is released:
IRQ is at VDD + 4 V for at least two machine cycles after
reset
TCAP1 is at VDD for at least two machine cycles after
reset

PD3 is at VDD for at least 30 machine cycles after reset
PD4 is at VDD for at least 30 machine cycles after reset
To execute the jump to any address function, port A
data input should be $CC, and port Band C should be
the MSB and LSB, respectively, of the address desired
for the jump. Figure 16 shows a schematic for the jump
function.

PULSE-LENGTH D/A CONVERTERS
The pulse-length D/A converter (PLM) works in conjunction with the timer to execute two 8-bit conversions
with a choice of two repetition rates. The outputs are
pulse-length modulated signals whose duty"cycle ratio
may be modified. These signals can be used directly as
PLMS, or the filtered average values can be used as general-purpose analog outputs.
Registers PLMA and PLMB contain the pulse-length
values for the two PLMs. A value of $00 results in a continuously low output from the D/A. A value of $80 results
in a 50-percent duty-cycle output, and a value of $FF gives
an output that is a logic 1 for 255/256 of the cycle. When
the MCU writes to the PLMA or PLMB register, the DA
picks up the new value at the end of a complete conversion cycle so that a monotonic change in the dc component of the output results. This monotonic change
avoids overshoots or vicious starts (a vicious start is an
output that gives totally erroneous output during the first

MOTOROLA MICROPROCESSOR· DATA

3-733

I

MC68HC0584

GNO
,5 V
10nF

I

22 pF

I.

·9 V

10
Voo
OSCI
OSC2

RESET

16

17

NC'
NC

ci5

I

1£
M
M

RS232 LEVEL TRANSLATOR
SUGGESTED:
MC145486 OR MAX232

iR5

19

"'"

I

-

2 x 10K

50
52

P04
P03

11

en

a:

TCAPI
24
25
26

z

PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO

0

~

<{

LU

::I:

t-

a:

f2

0
LU

a:

::;

~
'"
<{

VRH
VRL
NC
PLMA

::>

~

PLMB

co

5

u

SCLK

::I:

PB7
PB6
PB5
PB4
PB3
PB2
PSI
PBO

40
20
21
51

z

0

3
~

<{

~

TOO

52

::I:

50

f2

t-

a:

ROI
TCMP 2

~

::;

~

TCAP 2

'"t-

TCMP 1

z

<{

U

tu

LU

z
z

8

10K

22

PC7
PC6
PC5
PC4
PC3
PC2
PCl
pco

8

P07
P06
P05
P02
POI
poo
VSS
41
-:'

NOTE: Pin numbers are valid for 52-pin PLCC package only.

Figure 15. Load Program in RAM and Execut~ Diagram

MOTOROLA MICROPROCESSOR DATA
3-734

22PF

MC68HC05B4

GNO
+5V

·9 V

10 nF
10
VOO
OSCl
OSC2

16
17
:.::
0

22pF

rilc
15

IRQ

24
25
26
27
28
29
30
31

3 x 10K

PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO

VRL
NC
::>

z

u

0

::l<

~

CI:

.~

ROI
TCMP 2

.,

~

:5

~

U)

~

:5

3

PLMB

u

32
33
34
35
36
37
38
39

11
22

VRH

....

8 x 10K

I

19

NC
P04
P03
TCAP 1

8 x 10K

I

PC7
PC6
PC5
PC4
PC3
PC2
PCl
PCO

TCMP 1

«

TCAP 2

8z

8

P07
P06
P05
POl
POO
P02

Vss
41

NOTE: Pin numbers are valid for52-Pin PLCC Package only.

Figure 16. Jump to Any Address Diagram

MOTOROLA MICROPROCESSOR D4T~
~~735

22PF

MC68HC05B4

cycle following an update of the registers). WAIT mode
does not affect the output waveform of the D/A converters.

NOTE

6

I -

I

Since the PLM system uses the timer counter, PLM
results will be affected vvhile resetting the timer
counter.

RESET:

Figure 17 shows a block diagram of the PLM system.

SFA -

SFA

I PLMA71 PLMA61 PLMA51 PLMA41 PLMA31 PLMA21 PLMAl I PLMAO I
RESET:

o

SFB

Slow/Fast Control for PLMA Clock
(4096 times the
clock period)
0= Fast speed of PLMA used (256 times the
clock period)
SFB - Slow/Fast Control for PLMB Clock
1 = Slow speed of PLMB used (4096 times the
clock period)
0= Fast speed of PLMB used (256 times the
clock period)

1= Slow speed of PLMA used

PLMA (OAI
76543210

II

Miscellaneous (OCI

timer
timer

timer
timer

NOTE

PLMB (OBI
76543210

I PLMB71 PLMB61 PLMB51 PLMB41 PLMB31 PLMB21 PLMBl I PLMBO I
RESET:

o

The highest speed of the PLM system corresponds
to the frequency of the TOF bit being set, multiplied
by 256. The slowest speed of the PLM system corresponds to the frequency of the TOF bit being set,
multipled by 16.

DATA BUS

FROM TIMER

Figure 17. PLM Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-736

MC68HC05B4

coco -

Conversion Complete
1 = Conversion is complete; a new result can be read
from the result data register ($08).
0= No conv~rsion since last reset
ADRC - A/D RC Oscillator Control
1 = AID uses RC clock
0= AID uses CPU clock
When the RC oscillator is turned on, it requires a
time tadrc to stabilize, and results can be inaccurate during this time.
ADON -AID On
1 = AiD enabled
0= AiD disabled
When the AID is turned on, it requires a time tADON
for the current sources to stabilize, and results can
be inaccurate during this time.
CH3-CHO - Channel 3 through Channel 0
These bits select the AID channel assignment (see
Table 8).

The SFA and SFB bits are not double buffered; therefore, these bits must be selected before writing to either
PLM register to avoid temporary wrong values from the
PLM outputs. Figure 18 shows some examples of the PLM
output waveforms.

AID CONVERTER
The AID converter system consists of an 8-bit successive approximation converter and a 16-channel multiplexer. Eight of the channels are available for output, and
the other eight channels are dedicated to internal test
functions. There is one 8-bit result data register (address
$08) and one 8-bit status/control register (address $09).
NOTE
In the 48-pin dual-in-line package, the fixed input
port (D) of the MC68HC05B4 is reduced to. six pins
(pD5-PDO, AN5-ANO). This change has not effect
on either programming or operating of port D or
the AID converter.

NOTE
Using one or more pins of PD7/AN7-PDO/ANO as
analog inputs does not affect the ability to use port
D inputs as digital inputs. However, using port D
for digital inputs during an analog conversion sequence may inject noise on the analog inputs and
reduce the accuracy of the AID result.
Performing a digital read of port D with levels
other than VDD or VSS on the inputs causes greater
than normal power dissipation during the read and
may give erroneous results.

The reference supply for the converter uses dedicated
input pins instead of the power supply lines, because
drops caused by loading in the power supply lines would
degrade the accuracy of the AID conversion. An internal
RC oscillator is available if the bus speed is low enough
to degrade the AID accuracy. An ADON bit allows the AI
D to be switched offto reduce power consumption, which
is particularly useful in the WAIT mode.
For ratiometric conversions, the source of each analog
input should use VRH as the supply voltage and be referenced to VRL. An input voltage greater than or equal
to VRH converts as $FF (full scale) with no overflow indication. An input voltage equal to VRL converts as $00.
The conversion is monotonic with no missing codes.

INSTRUCTION SET
The MCU instruction set can be divided into five different types: register/memory, read-modify-write, branch,
bit manipulation, and control. The following paragraphs
briefly explain each type.
This MCU uses all the instructions available in the
M146805 CMOS Family plus one more: the unsigned

A/D STATUS/CONTROL REGISTER ($09)
7
1

COCO ·1 ADRC

5
1

ADON

CH3

1

CH2

CH1

CHO

RESET:

o
256 T

$00 , ..

I

I

__________

~L-

I
I
$80

! ..

-I

--------

I

I

255 T

~~

------

128 T

..

'-

I
128 T

-255f"--

..,I
I
I

.~
~~-~--------------~~~----------~--~
T = 4 CPU Clocks Fast Mode
T = 64 CPU Clocks Slow Mode

Figure 18. PLM Output Waveform Examples

MOTOROLA MICROPROCESSOR DATA
3-737

I

MC68HC05B4

Table 8. AID Channel Assignments

I

Function

CH2

CH1

CHO

0
0
0
0

0
0
0
0

0
0
1
1

0
1
0
1

ANO,
AN1,
AN2,
AN3,

Port
Port
Port
Port

D Bit 0
D Bit 1
D Bit 2
D Bit3

Subtract Memory from A with Borrow

SBC

AND Memory to A

AND

OR Memory with A

ORA

0
0
0
0

1
1
1
1

0
0
1
1

0
1
0
1

AN4,
AN5,
AN6,
AN7,

Port
Port
Port
Port

D
D
D
D

Exclusive OR Memory with A

EOR

Arithmetic Compare A with Memory

CMP

Arithmetic Compare X with Memory

CPX

1
1
1
1

0
0
0
0

0
0
1
1

0
1
0
1

VRH Pin (High)
((VRH) + (VRL))/2
VRL Pin (Low)
VRL Pin (Low)

1
1
1
1

1
1
1
1

0
0
1

0
1
0
1

VRL
VRL
VRL
VRL

1

Channel Selected

Pin
Pin
Pin
Pin

Bit
Bit
Bit
Bit

Subtract Memory

4
5
6
7

(Low)
(Low)
(Low)
(Low)

~
Source
LForm(s)

!

i

Inherent

Jump to Subroutine,

JSR

Function

Cycles

Bytes

11

Opcode
$42

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

Branch if Carry Clear

BCC

Branch if Higher or Same

BHS

Branch if Carry Set

BCS

Branch if Lower

BLO

Branch if Not Equal

BNE

Branch if Equal

IMUL
I

JMP

This set of instructions branches if a particular condition is met;'otherwise,no operation is performed. Branch
instructions are two-byte instructions. Refer to the following list for branch instructions.

I H: Cleared
II: Not affected
IN: Not affected
IZ: Not affected
IC: Cleared

Addressing

ii---Mode

BIT

Jump Unconditional

BRANCH INSTRUCTIONS

Multiplies the eight bits in the index register
I by the eight bits in the accumulator to obtain
Ia 16-bit unsigned number in the concatenated
accumulator and index register
Condition
Codes

SUB

Bit Test Memory with A (Logical Compare)

multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator
(A) and the index register (X). The high-order' product is
then stored in the index register, and the low-order product is stored in the accumulator. A detailed definition of
the MUL instruction is shown below.

I

Mnemonic

CH3

BEQ

Branch if Half Carry Clear

BHCC

Branch if Half Carry Set

BHCS

Branch if Plus

BPL

Branch if Minus

BMI

REGISTER/MEMORY INSTRUCTIONS

Branch if Interrupt Mask Bit is Clear

BMC

Most of these instructions use two operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have 110 register
operand. Refer to the following instruction list.

Branch if Interrupt Mask Bit is Set

BMS

Function

Mnemonic

Load A from Memory

LOA

Load X from Memory

LOX

Store A in Memory

STA

Store X in Memory

STX

Add Memory to A

ADD

Add Memory and Carry to A

ADC

Branch if Interrupt Line is Low

BIL

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

BIT MANIPULATION INSTRUCTIONS

The MCU is capable of setting or clearing any writable
bit which resides in the first 256 bytes of the memory
space where all port-registers, p()rt DDRs, timer, timer
control, ROM, and on-chip RAM reside. An additional
feature allows the software to test and branch on the state
of any bit within these 256 locations. The bit set, bit clear
, and pit test, and branch functions are all implemented
'with a single instruction. For test and branch instructions,

MOTOROLA MICROPROCESSOR DATA

3-738

MC68HC0584

the value of the bit tested is also placed in the carry bit
of the condition code register. Refer to the following list
for bit manipulation instructions.
Mnemonic

Function

Branch if Bit n is Set

BRSH n (n =0 . . ,7)

Branch if Bit n is Clear

BRClR n (n=O, .. 7)

Set Bit n

BSET n (n =0, , ,7)

Clear Bit n

BClR n (n = 0 ... 7)

Function

NOP

Stop

STOP

Wait

WAIT

OPCODE MAP SUMMARY

Table 9 is an opcode map for the instructions used on
the MCU.

READ-MODIFY -WRITE INSTRUCTIONS

ADDRESSING MODES

These instructions read a memory location ora register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.
Function

Mnemonic

No-Operation

Mnemonic

Increment

INC

Decrement

DEC

Clear

ClR

Complement

COM

Negate (Twos Complement)

NEG

Rotate left Thru Carry

ROL

Rotate Right Thru Carry

ROR

The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte
instructions; the longest instructions (three bytes) permit
accessing tables throughout memory. Short and long absolute addressing is also included. One- or two-byte direct addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

Logical Shift left

lSl

IMMEDIATE

logical Shift Right

lSR

Arithmetic Shift Right

ASR

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).

Test for Negative or Zero

TST

MUltiply

MUl

DIRECT
CONTROL INSTRUCTIONS

These instruCtions are register reference instructions
and ar(J used to control processor operation during program execution. Refer to the following list for control
instructions.
Function

EXTENDED

Mnemonic

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

CLC

Set InterruptMask Bit

SEI

In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.

In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended 'addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction. When using
the Motorola assembler, the user need not specify whether
an instruction uses direct or extended addressing. The
assembler automatically selects the shortest form of the
instruction.

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

RELATIVE

Return from Interrupt

RTI

The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following theopcode is etdded

Reset Stack Pointer

;

RSP

MOTOROLA MICROPROCESSQR DATA
3-739

I

•

Table 9. Opcode Map
Bit Manipulation
BTB
BSC

~

Branch
REL

DIR

~

s:

a
o

6

::D

0110

~

w

..:...
~

n
:a

BRSETO

BSETO

BRA

BRCLRO
BTBI2

BCLRO

BRN

BRSETl

BSETl

BHI

BRCLRl

BCLRl

BLS

BRSET2

BSET2

BCC

. R~ster/Memory
EXT
IX2

Control
IXl

IX

INH

INH

DIR

IMM

IXl

IX

o

A

HI/

/~

NEG

NEGA

NEGX

NEG

NEG

RTI

SUB

SUB

SUB

SUB

SUB

SUB

RTS

CMP

CMP

CMP

CMP

CMP

CMP

SBC

SBC

SBC

SBC

SBC

SBC

MUL
3 ..

COM

COMA

COMX

COM

COM

LSR

LSRA

LSRX

LSR

LSR

SWI

CPX

CPX

CPX

CPX

CPX

CPX

AND

AND

AND

AND

Ai\JD

AND

BIT

BIT

BIT

BIT

BIT

BIT

LOA

LOA

LOA

LOA

LOA

LOA

STA

STA

STA

STA

STA

EaR

EaR

EaR

EaR

EaR

ADC

ADC

BRCLR2

I

BCLR2

BCS

BRSET3

I

BSET3

BNE

ROR

RORA

RORX

ROR

ROR

BEQ REL I·,

ASR

ASRA

ASRX

ASR

ASR

TAX

LSLX

LSL

LSL

CLC

ROL

SEC

ADC

ADC

ADC

ADC

DEC

eLi

ORA

ORA

·ORA

ORA

ORA

ORA

SEI

ADD

ADD

ADD

ADD

ADD

ADD

JMP

JMP

JMP

JMP

JMP

JSR

JSR

JSR

JSR

JSR

LOX

LOX

LOX

LOX

LOX

STX

STX

STX

STX

STX

BRSET~TBr2

BSET4

BHCC

L$L

LSLA

BRCLR4

I

BCLR4

BHCS

ROL

ROLA

ROLX

ROL

BRSET5

I

BSET5

BPL

DEC

DECA

DECX

DEC

BRCLR5

I

BCLR5

BMI

BRSET6

I

BSET6

BMC

INC

INCA

INCX

INC

INC

BRCLR~TB I, BCLR6

BMS

TST

TSTA

TSTX

TST

TST

,

o"'a
:a
o(")

Read·Modify·Write
INH

0100

BRCLR~TBI2· BCLR3

s:

INH

4

.HI

EaR

3:

(")

en
CO
:J:
(")

o

A

m

A

CJ1

to
~

en
en

o

:a

c

»

~

BRSET7'1

BSET7

BIL

BRCLR7

BCLR7

BIH

RSP

Nap

STOP

CLR

CLRA

CLRX

CLR

CLR

WAIT

BSR

LOX

TXA

LEGEND

Abbreviations for Address Modes

INH

A
X
IMM
DIR
EXT

Inherent
Accumulator
Index Register
Immediate
Direct
Extended

REL
BSC
BTB
IX
IXl
IX2

Relative
Bit Set Clear
Bit Test and Branch
Indexed (No Offset)
Indexed, 1 Byte (8-Bit) Offset
Indexed, 2 Byte (16-Bit) Offset

..

Mnemonic
Bytes

i •

J! 1

Cycles - - - - - - - - "

tJ If

/IX

/

I
~

:>

-: J

Opcode in Hexadecimal
Opcode in Binary

OOOO~

'---------Address Mode

MC68HC05B4

to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from - 126 to + 129 from
the opcode address. The programmer need not calculate
the offset when using the Motorola assembler, since it
calculates the proper offset and checks to see that it is
within the span of the branch.
INDEXED, NO OFFSET

In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or to hold the address of a frequently referenced
RAM or 1/0 location.
INDEXED, 8-BIT OFFSET

In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
the beginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1 FE is the last location at which the instruction may
begin).

instruction allows tables to be anywhere in memory. As
with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.
BIT SET/CLEAR

In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode, and the byte following
the opcode specifies the directaddressing of the byte in
which the specified bit is to be set or cleared. Any read/
write bit in the first 256 locations of memory, including
1/0, can be selectively set or cleared with a single twobyte instruction.
BIT TEST AND BRANCH

The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear), is
included in the opcode. The address of the byte to be
tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third
byte is added to the PC if the specified bit is set or cleared
in the specified memory location. This single three-byte
instruction allows the program to branch based on the
condition of any readable bit in the first 256 locations of
memory. The span of branching is from -125 to + 130
from the opcode address. The state of the tested bit is
also transferred to. the carry bit of the condition code
register.
INHERENT

INDEXED, 16-BIT OFFSET

In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the two unsigned bytes following
the opcode. This address mode can be used in a manner
similar to indexed, 8-bit offset except that this three-byte

In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this mode. These instructions are one byte long.

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS (Voltages referenced to VSS)
Rating

Symbol

Value

Unit

VDD

-0.5 to +7.0

V

Input Voltage

Vin

VSS - 0.5 to
VDD +0.5

V

Self-Check Mode (IRQ Pin Only)

Vin

VSS-0.5 to
2 xVDD+0.5

V

Current Drain Per Pin Excluding
VDD and VSS

I

25

mA

TA

TL to TH
+ 70
-40 to +85
-40 to + 125

C

Tstg

-65 to + 150

'C

Supply Voltage

Operating Temperature Range
MC68HC0584P, FN (Standard)
MC68HC0584CP, CFN (Extended)
MC68HC0584MP, MFN (Automotive)
Storage Temperature Range

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum-rated voltages
to this high-impedance circuit. For proper operation, it is recommended that Vin and Vout be
constrained to the range VSS '" (Vin or Voutl>
VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic
voltage level (e.g., either VSS or VDD).

o to

MOTOROLA MICROPROCESSOR DATA
3~741

II

MC68HC05B4

THERMAL CHARACTERISTICS'
,Charac;teristic

Symbol

Thermal Resistance
Plastic
Plastic Leaded Chip Carrier (PLCC)

IIJA

Value

U.nit
°C/W'

40

50

POWER CONSlbERATIONS

II·

Th.e average chip-jupction temperature, TJ,in °C ·can
be obtained from:
TJ=TA+(PDe!JJA)
(1)
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance,
!JJA
J u nction-to-'Ambient, °C/W
= PINT+ PliO
.
PD
= ICC x VCC' Watts - Chip Internal Power
PINT
= Power Dissipation on Input and Output
. PliO
Pins - User Determined

For most applications PI/O
s:

TOO
PIN

TRANSMIT
DATA
REGISTER

RECEIVE
DATA
REGISTER

I

..

~

$OF
SCCR2

TRANSMIT
DATA
SHIFT
REGISTER

TIE
TCIE
RIE
ILiE

I

RECEIVE
OATA
SHIFT
REGISTER

IT
RE
SBK
RWU

I

3:

n::u

w
..:... 0
.....
"'tJ
Q
::u

o

(")

m

tJ)
tJ)

o::u

$11

(SEE NOTEI

nen
co

NOTE: The Serial Communications Data
Register (SCI SCDATI is controlled by the internal R/W signal. It is the transmit data register when written and receive data register
when read.

SCSR
$10

I

11M
UP
UNIT

~
CLOCK EXTRACTION
PHASE AND
POLARITY
CONTROL

TRANSMITIER
CLOCK

RECEIVER
CLOCK

SCCRI
$OE

Figure 12. SCI Block Oiagram

:::I:

n0

I I

c.n
c:J
en

MC68HC05B6

IDLE OR
PRECEDING
TRANSMISSION

..

START

~

M=OU DATA BIT

STOP

I :

I
I

CLOCK

IDLE OR

--------------------------~·~I~~

NEXT TRANSMISSION

I

(CPOL = 0 CPHA = 0)
CLOCK
(CPOL=O CPHA=l)
CLOCK
(CPOL= 1 CPHA=O)
CLOCK
(CPOL = 1 CPHA = 1)
DATA
MSB STOP

START LSB

*LBCL Bit Controls Last Data Clock

Figure 13. SCI Data Clock Timing Diagram (M=O)

IDLE OR
START
- - - - I..
~I ___
PRECEDING
I
TRANSMISSION
II
:

M = 1.9 DATA BIT

STOP

IDLE OR

I - - - - - - - - - - - - - _ i..~1 ~--....

CLOCK

J
:

I

NEXT TRANSMISSION

----+--+--

(CPOL = 0 CPHA = 0)
CLOCK

----t---!

(CPOL=O CPHA=1)

CLOCK ---....+--.-.;......
(CPOL = 1 CPHA = 0)
CLOCK
(CPOL = 1 CPHA = 1)
DATA
START LSB

MSB STOP
*LBCL Bit Controls Last Data Clock

Figure 14. SCI Data CLock Timing Diagram (M = 1)

TE -

Transmit Enable
1 = Transmit shift register output is applied to the TDO
line, and the corresponding clocks are applied to
the SCLK pin. Depending upon the SCCR1 M bit,
a preamble of 10 (M = 0) or 11 (M = 1) consecutive
ones is transmitted.
0= Transmitter disabled after last byte is loaded in
the SCDAT and TDRE is set. After last byte is
transmitted, TDO line becomes a high-impedance
line.

RE -

Receive Enable
1 = Receiver shift register input is applied to the RDI
line.
0= Receiver disabled and RDRF, IDLE, OR, NF, and
FE status bits are inhibited.
RWU - Receiver Wake-Up
1 = Places receiver in sleep mode and enables wakeup function
0= Wake-up function disabled after receiving data
word with MSB set (if WAKE = 1)

MOTOROLA MICROPROCESSOR DATA
3~771

I

MC68HC05B6

Wake-up function also disabled after receiving 10
(M=O) or 11 (M = 1) consecutive ones (if WAKE =0)
SBK - Send Break
1 = Transmitter continually sends blocks of zeros (sets
of 10 or 11) until cleared. Upon completion of
break code, transmitter sends one high bit for recognition of valid start bit.
O=Transmitter sends 10 (M=O) or 11 (M=1) zeros
then reverts to an idle state or continues sending
data. If transmitter is empty and idle, setting and
clearing the SBK bit may queue up to two character times of break because the first break transfers immediately to the shift register, and the
second is queued into the parallel transmit buffer.
Serial Communications Status Register (SCSR) $10

I

Noise Flag
1 = Indicates noise is present on the receive bits, including the start and stop bits. NF is not set until
RDRF=l.
0= NF is cleared by reading the SCSR, followed by
a read of the RDR.
. FE - Framing Error
1 = Indicates stop bit not detected in received data
character. FE is set the same time RDRF is set. If
received byte causes both framing and overrun
errors, processor will only recognize the overrun
error. Further data transfer into the RDR is inhibited until FE is cleared.
0= FE is cleared by reading the SCSR, followed by a
read of the RDR.
Bit 0 - Not used
Can read either one or zero

The SCSR provides inputs to the SCI interrupt logic
circuits. Noise flag and framing error bits are also contained in the SCSR.

TORE

TC

RDRF

IDLE

OR

NF

FE

RESET:

TORE - Transmit Data Register (TOR) Empty
1 = TOR contents transferred to the transmit data shift
register
0= TOR still contains data .. TORE is cleared by reading
the SCSR, followed by a write to the TOR.
TC - Transmit Complete
1 = Indicates end of data frame, preamble, or break
condition has occurred if:
1. TE = 1, TORE = 1, and no pending data, preamble or break is to be transmitted; or
2. TE = 0 and the data preamble or break (in the
transmit shift register) has been transmitted.
0= TC bit cleared by reading the SCSR, followed by
a write to the TOR
The TC bit is a status register that indicates one of
the above conditions has occurred. It does not inhibit the transmitter in any way.
RDRF - Receive Data Register (RDR) Full
1 = Receive data shift register contents transferred to
the RDR
0= Receive data shift register transfer did not occur.
RDRF is cleared by reading the SCSR, followed
by a read of the RDR
IDLE - Idle Line Detect
1 = Indicates receiver has detected an idle line
0= IDLE is cleared by reading the SCSR, followed by
a read of the RDR. Once IDLE is cleared, IDLE
cannot be set until RDI line becomes active and
idle again.
OR - Overrun Error
1 = Indicates receive data shift register data is ready
to be sent to a full RDR (RDRF = 1). Data causing
the overrun is lost, and RDR data is not disturbed.
0= OR is cleared by reading the SCSR, followed by
a read of the RDR.

NF -

Baud Rate Register $00
The baud rate register selects the SCI transmitter and
receiver baud rate. The SCP1 and SCPO prescaler bits are
used in conjunction with the SCR2-SCRO bits to generate
the receiver baud rate and in conjunction with the
SCT2-SCTO baud rate bits to generate the transmitter
baud rate.
Tables 6 and 7 tabulate the divide chain used to obtain
the baud rate clock (transmit or receive clock). The actual
divider chain is controlled by the combined SCP1-SCPO
and SCR2-SCRO or SCT2-SCTO bits in the baud rate register. The divided frequencies shown in Table 6 represent
the final baud rate that results from prescaler division
only (SCR or SCT bits all zero). Table 7 lists the prescaler
output frequency divided by the action of the SCR or SCT
bits.
For example, assume that 9600-Hz baud rate is desired
from a 2.4576-MHz system clock crystal. The prescaler
bits could be set for either a divide-by-one or divide-byfour. If a divide-by-four prescaler is used, then the SCR
and SCT bits must be set for divide-by-two. The same
result, using the same crystal frequency, can be obtained
with a prescaler divide-by-one and SCR and SCT bit divide-by-eight.

SCPl

SCPO

SCT2

SCTl

SCTO

SCR2

SCRl

SCRO

u

u

u

u

u

u

RESET:

o

SCP1-SCPO - SCI Prescaler Bits 1 and 0
These two prescaler bits are used to increase the
range of standard baud rates controlled by the SCT2SCTO and SCR2-SCRO bits. Prescaler internal processor clock division versus bit levels are shown in
Table 6.
SCT2-SCTO - SCI Transmit Baud Rate Selection Bits
These three bits, taken in conjunction with bits
SCP1-SCPO, are used to select the SCI transmit baud
rate. Baud rates versus bit levels are listed in Table
7.

MOTOROLA· MICROPROCESSOR DATA
3-772

MC68HC05B6

Table 6. Prescaler Highest Baud Rate Frequency Output
SCP Bit
1

0

0
0
1
1

0
1
0
1

Clock*
Divided By
1
3
4
13

Crystal Frequency MHz
4.194304
131.072
43.691
32.768
10.082

kHz
kHz
kHz
kHz

4.0

2.4576

125.000 kHz
41.666 kHz
.31.250 kHz
9600 Hz

76.80
25.60
19.20
5.907

kHz
kHz
kHz
kHz

2.0
62.50 kHz
20.833 kHz
15.625 kHz
4800 Hz

1.8432
57.60
19.20
14.40
4430

kHz
kHz
kHz
Hz

*Refers to the internal processor clock.
NOTE: The divided frequencies shown in Table 6 represent baud rates which are the highest transmit baud rate (Tx) that can be
obtained by a specific crystal frequency and only using the prescaler division. Lower baud rates may be obtained by providing
a further division using the SCI rate select bits as shown below for some representative prescaler outputs.

Table 7. Transmit Baud Rate Output for a Given Prescaler Output
SCRIT Bits
2

1

0

0
0
0
0

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1

Divided
By
1
2
4
8
16
32
64
128

Representative Highest Prescaler Baud Rate Output
131.072 kHz

32.768 kHz

76.80 kHz

19.20 kHz

9600 Hz

131.072
65.536
32.768
16.384
8.192
4.096
2.048
1.024

32.768 kHz
16.384 kHz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz

76.80 kHz
38.40 kHz
19.20 kHz
9600 Hz
4800 Hz
2400 Hz
1200 Hz
600 Hz

19.20 kHz
9600 Hz
4800 Hz
2400 Hz
1200 Hz
600 Hz
300 Hz
150 Hz

9600
4800
2400
1200
600
300
150
75

kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz

Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz

NOTE: Table 7 illustrates how the SCI select bits can be used to provide lower transmitter or receiver baud rates by further dividing
the prescaler output frequency. The five examples are only representative samples. In all cases, the baud rates shown are
transmit baud rates (transmit clock), and the receive clock is 16 times higher in frequency than the actual baud rate.

SCR2-SCRO - SCI Receive Baud Rate Selection Bits
These three bits, taken in conjunction with bits
SCP1-SCPO, are used to select the SCI receive baud
rate. Baud rates versus bit levels are listed in Table
7.

byte count to a value greater than the length of data
loaded, which causes the firmware to wait for additional
data after loading is complete: Resetting the MCU then
allows entering any routine without disturbing the RAM
data that was loaded.

Load Program in RAM and Execute

Jump to Any Address

This function is entered if the following conditions are
met when reset is released:
IRQ is at VDD + 4 V for at least two machine cycles after
reset
TCAP1 is at VDD for at least two machine cycles after
reset
PD3 is at VDD for at least 30 machine cycles after reset
PD4 is at VSS for at least 30 machine cycles after reset
User programs are loaded into RAM using the SCI port
and then executed. Data is loaded sequentially, starting
at RAM location $50, until the last byte is loaded. Program
control is then transferred to the RAM progam starting
at location $51. The first byte loaded is the count of the
number of bytes in the program plus the count byte. The
program starts at the second byte in the RAM. During
firmware initialization, the SCI is configured for the NRZ
format (idle line, eight data bits, and stop bit). The baud
rate is 9600 with a 4-MHz crystal. Figure 15 shows a schematic for the load program in RAM and execute function.
Immediate execution can be avoided by setting the

This function is entered if the following conditions are
met when reset is released:
IRQ is at VDD + 4 V for at least two machine cycles after
reset
TCAP1 is at VDD for at least two machine cycles after
reset
PD3 is at VDD for at least 30 machine cycles after reset
PD4 is at VDD for at least 30 machine cycles after reset
To execute the jump to any address function, port A
data input should be $CC, and port Band C should be
the MSB and LSB, respectively, of the address desired
for the jump. Figure 16 shows a schematic for the jump
function.

PULSE-LENGTH D/A CONVERTERS
The pUlse-length D/A converter (PLM) works in conjunction with the timer to execute two 8-bit conversions

MOTOROLA MICROPROCESSOR· DATA
3-773

I

MC68HC0586

PI
GNo

10nF

·5 V
·9 V

I

10
Voo

ft

ascI
OSC2

RESET

16
10M

17

0.01 f.LF

NC
15

ci5

~

I

M

M

RS232 LEVEL TRANSLATOR
SUGGESTED:
MC145486 DR MAX232

22pF

50

NC

iRfi

19

""<=>

I

I

-

2 • 10K
NC
NC

P04
P03

11

U)

cr.

TCAPI

29
30
31

z

PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAD

0

;3

~

cr.

Cl

~

::;

~
U)

VRH
VRL
Vppl
PLMA

:;:)

u

~

32
33

8
PB7
PB6
PB5
PB4
PB3
PB2
PBl
PBO

~

;:::

;5

SCLK

~u


u
:2

PLMA

(Q

PLMB

6

~
u
~
u

3

~

SCLK

:2

«

::t:

TOO

PB5
PB4
PB3
PB2
PBl
PBO

RDI

>-

a::

50

TCMP 1

PC7
PC6
PC5
PC4
PC3
PC2
PCl
PCO

0

~

5

TCMP 2

TCAP 2

~

11
22

VRH

~

5

I

22PF

19

NC
P04
PD3
TCAP 1

8 x 10K

""

I

2.
23

~

U)

«

>u
w

z

8

PD7
P06
PD5
POl
PDO
P02
VSS
41

NOTE: Pin numbers are valid for 52-pin PLCC package only:

Figure 16. Jump to Any Address Diagram

MOTOROLA MICROPROCESSOR DATA
3-775

MC68HC05B6

with a choice of two repetition rates. The outputs are
pulse-length modulated signals whose duty-cycle ratio
may be modified. These signals can be used directly as
PLM, or the filtered average values can be used as general-purpose analog outputs.
Registers PLMA and PLMB contain the pUlse-length
values for the two PLMs. A value of $00 results in a continuously low output from the D/A. A value of $80 results
in a 50-percent duty-cycle output. and a value of$FF gives
an output that is a logic 1 for 255/256 of the cycle. When
the MCU writes to the PLMA or PLMB register, the D/A
picks up the new value at the end of a complete conversion cycle. A monotonic change in the dc component of
the output results, without overshoots or vicious starts
(a vicious start is an output that gives totally erroneous
output during the first cycle following an update of the
registers). WAIT mode does .not affect the output waveform of the D/A converters.

PLMA (OA)
76543210

IPLMA71 PLMA61 PLMA51 PLMA41 PLMA31 PLMA21 PLMAl IPLMAO I
RESET:

o

PLMB (OB)
76543210

I PLMB7\ PLMB6\ PLMB51 PLMB4\ PLMB31 PLMB21 PLMBl I PLMBO I
RESET:

o

Miscellaneous (OC)
6

I- I

SFA

SFB

RESET:

NOTE

I

Since the PLM system uses the timer counter, PLM
results will be affected while resetting the timer
counter.
Figure 17 shows a block diagram of the PLM system.

SFA - Slow/Fast Control for PLMA Clock
1 = Slow speed of PLMA used (4096 times the timer
clock period)
0= Fast speed of PLMA used (256 times the timer
clock period)

DATA BUS

FROM TIMER

Figure 17. PLM Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-776

MC68HC05B6

to degrade the AID accuracy. An ADON bit allows the A/
D to be switched off to reduce power consumption, which
is particularly useful in the WAIT mode.
For ratiometric conversions, the source of each analog
input should use VRH as the supply voltage and be referenced to VRL. An input voltage greater than or equal
to VRH converts as $FF (full scale) with no overflow indication. An input voltage equal to VRL converts as $00.
The conversion is monotonic with no missing codes.

SFB - Slow/Fast Control for PLMB Clock
1 = Slow speed of PLMB used (4096 times the timer
clock period)
0= Fast speed of PLMB used (256 times the timer
clock period)
NOTE

The highest speed of the PLM system corresponds
to the frequency of the TOF bit being set, multiplied
by 256. The slowest speed of the PLM system corresponds to the frequency of the TOF bit being set,
multipled by 16.

A/D STATUS/CONTROL REGISTER ($09)
7

The SFA and SFB bits are not double buffered; therefore, these bits must be selected before writing to either
PLM register to avoid temporary wrong values from the
PLM outputs. Figure 18 shows some examples ofthe PLM
output waveforms.

6

5

I COCO I ADRC I ADON I

CH3

NOTE

In the 48-pin dual-in-line package, the fixed input
port (D) of the MC68HC05B6 is reduced to six pins
(PD5-PDO, AN5-ANO). This change has no effect on
either programming or operation of port D or the
AID converter.
The reference supply for the converter uses dedicated
input pins instead of the power supply lines, because
drops caused by loading in the power supply lines would
degrade the accuracy of the AID conversion. An internal
RC oscillator is available if the bus speed is low enough

NOTE

Using one or more pins of PD7.AN7-PDO;ANO as
analog inputs does not affect the ability to use port
D inputs as digital inputs. However, using port D

_$_OO~I_"_ _ _ _ _ _ _ _ _ _ _ ~~ ~ __

~I

I
255 T

_ _ _ _----I~~

I

$80

I.

128 T

I
.. i"

128 T

I

I

CHO

COCO - Conversion Complete
1 = Conversion is complete; a new result can be read
from the result data register ($08).
0= No conversion since ·Iast reset
ADRC - AID RC Oscillator Control
1 = AID uses RC clock
0= AID uses CPU clock
When the RC oscillator is turned on, it requires a
time tadrc to stabilize, and results can be inaccurate during this time.
ADON -AID On
1 = AiD enabled
0= AiD disabled
When the AD is turned on, it requires a time tADON
for the current sources to stabilize, and results can
be inaccurate during this time.
CH3-CHO - Channel 3 through Channel 0
These bits select the AD channel assignment (see
Table 8).

The A/D converter system consists of an 8-bit successive approximation converter and a 16-channel multiplexer. Eight of the channels are available for output, and
the other eight channels are dedicated to internal test
functions. There is one 8-bit result data register (address
$08) and one 8-bit status/control register (address $09).

I

CH1

o

AID CONVERTER

I
~~'---------­

CH2

RESET:

I
I
I

.. ______________-_-_-~2~~~T~-_-_-______________~.~~

~~~.

T = 4 CPU Clocks Fast Mode
T = 64 CPU Clocks Slow Mode

Figure 18. PLM Output Waveform Examples

MOTOROLA MICROPROCESSOR DATA
3-177

II

MC68HC0586

for digital inputs during an analog conversion sequence may inject noise on the analog inputs and
reduce the accuracy of the AID result.
Performing a digital read of port D with levels
other than VDD or VSS on the inputs causes greater
than normal power dissipation during the read and
may give erroneous results.

other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following instruction list.
Function
Load A from Memory

Table 8. AID Channel Assignments

II

CH3

CH2

CH1

CHO

a
a
a
a

a
a
a
a

a
a
1
1

a
1
a
1

Channel Selected
ANa,
AN1,
AN2,
AN3,

Port
Port
Port
Port
Port
Port
Port
Port

D Bit
D Bit
D Bit
D Bit
D Bit
D Bit
D Bit
D Bit

a
1
2
3

a
a
a
a

1
1
1
1

a
a
1
1

a
1
a
1

AN4,
AN5,
AN6,
AN7,

4
5
6
7

1
1
1
1

a
a
a
a

a
a
1
1

a
1
a
1

VRH Pin (High)
((VRH) + (VRL))/2
VRL Pin (Low)
VRLPin (Low)

1
1
1
1

1
1
1
1

a
a
1
1

a
1
a
1

VRL Pin
VRL Pin
VRL Pin
VRL Pin

(Low)
(Low)
(Low)
(Low)

Mnemonic
LDA

Load X from Memory

LDX

Store A in Memory

STA

Store X in Memory

STX

Add Memory to A

ADD

Add Memory and Carry to A

ADC

Subtract Memory

SUB

Subtract Memory from A with Borrow

SBC

AND Memory to A

AND

OR Memory with A

ORA

Exclusive OR Memory with A

EOR

Arithmetic Compare A with Memory

CMP

Arithmetic Compare X with Memory

CPX

Bit Test Memory with A (Logical Compare)

BIT

Jump Unconditional

JMP

Jump to Subroutine

JSR

INSTRUCTION SET
The MCU instructions can be divided into five different
types: registerimemory, read-modify-write, branch, bit
manipulation, and control. The following paragraphs
briefly explain each type.
This MCU uses all the instructions available in the
M146805 CMOS Family plus one more: the unsigned
multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator
(A) and the index register (X). The high-order product is
then stored in the index register, and the low-order product is stored in the accumulator. A detailed definition of
the MUL instruction is shown below.

BRANCH INSTRUCTIONS

This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions. are two-byte instructions. Refer to the following list for branch instructions.
Function

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

I

~?
__pe_r_at_io_n__~IX_:_A_.__X_'_A________________________~

Branch if Carry Clear

BCC

Description I Multiplies the eight bits in the index register
by the eight bits in the accumulator to obtain
i a 16-bit unsigned number in the concatenated
accumulator and index register

Branch if Higher or Same

BHS

Condition
Codes

Branch if Not Equal

BNE

Branch if Equal

BEQ

i

I

L

I Source
I

Form(s)

I Addressing
Mode
i Inherent

i H: Cleared
I: Not affected
iN: Not affected
I Z: Not affected
C: Cleared

i

MUL
Cycles

Bytes

Opcode

11

1

$42

REGISTERIMEMORY INSTRUCTIONS

Most of these instructions use two operands. One operand is either the accumulator or the index register. The

Branch if Carry Set

BCS

Branch if Lower

BLO

Branch if Half Carry Clear

BHCC

Branch if Half Carry Set

BHCS

Branch if Plus

BPL

Branch if Minus

BMI

Branch if Interrupt Mask Bit is Clear

BMC

Branch if Interrupt Mask Bit is Set

BMS

Branch if Interrupt Line is Low

BIL

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

MOTOROLA MICROPROCESSOR DATA
3-778

MC68HC05B6

READ-MODIFY-WRITE INSTRUCTIONS

These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.
Function

the value of the bit tested is also placed in the carry bit
of the condition code register. Refer to the following list
for bit manipulation instructions.
Function

Mnemonic

Increment

INC

Decrement

DEC

Mnemonic

Branch if Bit n is Set

BRSET n

Branch if Bit n is Clear

BRCLR n (n

Set Bit n

BSET n (n

Clear Bit n

BCLR n (n

(n~

0 ... 7)

~O
~

... 7)

o ... 7)
0 ... 7)

Clear

CLR

OPCODE MAP SUMMARY

Complement

COM

Table 9 is an opcode map for the instructions used on
the MCU.

Negate (Twos Complement)

NEG

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Logical Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

Multiply

MUL

ADDRESSING MODES

CONTROL INSTRUCTIONS

These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.
Function

Mnemonic

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

CLC

Set Interrupt Mask Bit

SEI

The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte
instructions; the longest instructions (three bytes) permit
accessing tables throughout memory. Short and long absolute addressing is also included. One- or two-byte direct addressing instructions access ali data bytes in most
applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.
IMMEDIATE

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

DIRECT

Reset Stack Pointer

RSP

In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.

No-Operation

NOP

Stop

STOP

Wait

WAIT

EXTENDED
BIT MANIPULATION INSTRUCTIONS

The MCU is capable of setting or clearing any writable
bit which resides in the first 256 bytes of the memory
space where all port registers, port DDRs, timer, timer
control, ROM, and on-chip RAM reside. An additional
feature allows the software to test and branch on the state
of any bit within these 256 locations. The bit set, bit clear
and bit test, and branch functions are all implemented
with a single instruction. For test and branch instructions,

In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction, When using
the Motorola assembler, the user need not specify whether
an instruction uses direct or extended addressing. The
assembler automatically selects the shortest form of the
instruction.

MOTOROLA MICROPROCESSOR DATA
3-779

II

•

Table 9. Opeode Map
Bit Manipulation
BTB
BSe

Branch

REl

~-----"I
llO\'l~

o
0000

s:

d::xJ

5

w
~
co
o

BRCLRO I
BTBI2

BCLRO
I
Bsel2

BRN

BRSETl I
BTBI2

BSETl

BHI

BRCLRl
BTBI2

BCLRl

NEG

NEGA

INH

NEGX

Control

IXl

NEG

IX

NEG

Register/Memory

INH

INH

IMM
A

DIR

RTI

SUB

SUB 0lRI3

SUB

RTS

CMP

CMP

SBC

CPX

MUL

BLS

IXl

IX

SUB

SUB

SUB

CMP

CMP

CMP

CMP

SBC

SBC

SBC

SBC

SBC

CPX

CPX

CPX

CPX

CPX

EXT

IX2

o

~

COM

COMA

COMX

COM

COM

LSRA

LSRX

LSR

LSR

SWI

o
0000

0001

0010

DIRl1

BSET2

s:

BRCLR3 I
BTBI2

BCLR3

o"'a
::xJ
o
(')

BRSET4

I

INH

Bsel2

o

n
::xJ

0011

BRA

BCLR2

~

0010

BSETOBse 12

BRCLR2 I
BTBI2
51
BRSET3 I

0101

DIR
3

BRSET~TB 12

BRSET~TBI2

o

Read·Modify·Write

2

l
Bse 2

I

Bsel2
51
BSET3
I'

I

BCC REll2
BCS

I

AND

AND

AND

AND

BIT

BIT

BIT

BIT

BIT

BIT

LDA

WA

WA

WA

WA

LDA

STA

STA EXTI3

STA

STA

STA

AND 0lRI3

ROR

RORA

RORX

ROR

ROR

ASR

ASRA

ASRX

ASR

ASR

TAX

BHCC

LSL

LSLA

LSLX

LSL

LSL

CLC

EOR

EOR

EOR

EOR

EOR

EOR

BHCS

ROL

ROLA

ROLX

ROL

ROL

SEC

ADC

ADC

ADC

ADC

ADC

ADC

DEC

DECA

DECX

DEC

DEC

CLI

ORA

ORA 0lRI3

ORA EXTI3

ORA 1X2I,

ORA

SEI

ADD

ADD

ADD

ADD

BNE

BEQ

Bsel2
BSET4

LSR DIRI,

AND

REll2

5
0101

s:

(')

en
CO

BRCLR4 I
BTBI'
51
BRSET5 I
BTBI2

BCLR4
I
Bsel,
51
BSET5
I
Bsel,

o::xJ

BRCLR5 I
BTBI2

BCLR5

C

BRSET6

I

BSET6

I

BMC

INC

INCA

INCX

INC

INC

RSP

BRCLR6

I

BCLR6

I

BMS

TST

TSTA

TSTX

TST

TST

NOP

A

m

en
en

5

~

D

I

BPL

BMI

JMP
JSR

BSR

BSET7

STOP

BIL

LDX

LDX

INH

X
IMM
DIR
EXT

41

51

ADD

ADD

BCLR7

Inherent
Accumulator
Index Register
Immediate
Direct
Extended

JMP EXTI3

JMP

JMP

JMP

JSR

JSR

JSR

JSR

LDX

WX

LDX

LDX

BIH

CLR

CLRA

CLRX

CLR

CLR

WAIT

TXA

STX

Bsel,

STX

STX

STX

STX

C
1100

D

DIRI3

REl
BSC
BTB
IX
IX1
IX2

LEGEND

Relative
Bit Set/Clear
Bit Test and Branch
Indexed (No Offset)
Indexed,1 Byte (8-Bit) Offset
Indexed,2 Byte (16-Bit) Offset

F III

Mnemonic
Bytes
Cycles

J

Jr

1

:>

~
~
~X

7

~

Opcode in Hexadecimal
Opcode in Binary

OOOO:lllr

----------Address Mode

U'I

~

en

DIRI3

Abbreviations for Address Modes

A

o

A

DIRI3

BSCI2

BRCLR7
BTBI2

31

ORA

Bsel2

INHI2

BRSET7

::E:

(')

RELI'

MC68HC05B6

RELATIVE
The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from -126 to + 129 from
the opcode address. The programmer need not calculate
the offset when using the Motorola assembler, since it
calculates the proper offset and checks to see that it is
within the span of the branch.
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or to hold the address of a frequently referenced
RAM or 1/0 location.

INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents ofthe unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
the beginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1 FE is the last location at which the instruction may
begin).

INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the two unsigned bytes following

the opcode. This address mode can be used in a manner
similar to indexed, 8-bit offset except that this three-byte
instruction allows tables to be anywhere in memory. As
with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.

BIT SETICLEAR
In the bit setlclear addressing mode, the bit to be set
or cleared is part of the opcode, and the byte following
the opcode specifies the direct addressing of the byte in
which the specified bit is to be set or cleared. Any read!
write bit in the first 256 locations of memory, including
110, can be selectively set or cleared with a single twobyte instruction.
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear), is
included in the opcode. The address of the byte to be
tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third
byte is added to the PC if the specified bit is set or cleared
in the specified memory location. This single three-byte
instruction allows the program to branch based on the
condition of any readable bit in the first 256 locations of
memory. The span of branching is from -125 to +130
from the opcode address. The state of the tested bit is
also transferred to the carry bit of the condition code
register.
INHERENT
In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this mode. These instructions are one byte long.

MOTOROLA MICROPROCESSOR DATA
3-781

I

MC68HC05B6

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS (Voltages referenced to Vss)
Symbol

Value

Unit

Supply Voltage

Rating

VOO

-0.5 to + 7.0

V

Input Voltage

Vin

VSS -0.5 to
VOO +0.5

V

Self-Check Mode (IRQ Pin Only)

Vin

VSS-0.5 to
2xVOO+0.5

V

Current Orain Per Pin Excluding
VOO and VSS

I

25

mA

TL to TH

"C

Operating Temperature Range
MC68HC05B6P, FN (Standard)
MC68HC05B6CP, CFN (Extended)
MC68HC05B6MP, MFN (Automotive)

TA

o to

+ 70
-40 to +85
-40 to + 125

Storage Temperature Range

I

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum-rated voltages
to this high-impedance circuit. For proper operation, it is recommended that Vin and Vout be
constrained to the range VSS '" (Vin or Vout) ,,-.:
VOO. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic
voltage level (e.g., either VSS or VOO).

TstQ

-65 to + 150

Characteristic

Symbol

Value

Thermal Resistance
Plastic
Plastic Leaded Chip Carrier (PLCC)

fJJA

"C

THERMAL CHARACTERISTICS
Unit
°C/W

40
50

VOO=4.5 V
Pins
PA7-PAD,
PB7-PBO,
PC7-PCO,
TCMPl
TCMP2
TOO, SCLK,
PLMA, PLMB

R1

R2

C

3.26 kU

2.38 kH

50 pF

VDD
R2
(SEE TABLE)
TEST o----~--.
POINT

1.9 kH

2.26 kH

C

200 pF

(SEE
TABLE)

VOO=3.0 V
Pins
PA7-PAD,
PB7-PBO,
PC7-PCO,
TCMP1,
TCMP2
TOO, SCLK,
PLMA, PLMB

R1

R2

C

10.91 k!!

6.32 k!l

50 pF

6kU

6 k!l

200 pF

Figure 19. Equivalent Test Load

MOTOROLA MICROPROCESSOR DATA
3-782

Rl
(SEE TABLE)

MC68HC05B6

POWER CONSIDERATIONS
The average chip-junction temperature, TJ' in °c can
be obtained from:
TJ=TA+(PO·IlJA)
(1)
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance,
IlJA
Junction-to-Ambient, °C/W
Po
= PINT+PI/O
= ICC x VCC' Watts -' Chip Internal Power
PINT
= Power Oissipation on Input and Output
PliO
Pins - User Oetermined

DC ELECTRICAL CHARACTERISTICS

For most applications PI/O-

<>
c
~

I

0.5

"-

0.2

(;

IE o. 1
~
o 0.05

"'"

0.02

0.0 1
1

10

20

50

100

200

500

1000

Resistance (kill

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only

II

Ceramic Resonator
A ceramic resonator may be used in place of the crystal
in cost-sensitive applications. The circuit in Figure 1(b) is
recommended when using a ceramic resonator. Figure
1(a) lists the recommended capacitance and resistance
values. The manufacturer of the resonator considered
should be consulted for specific information on resonator
operation.
External Clock
An external clock should be applied to the OSC1 input
with the OSC2 input not connected, as shown in Figure
1(e). This option may only be used with the crystal oscillator mask option.
INPUT CAPTURE (TCAP)
This pin controls the input capture feature for the onchip programmable timer.

INPUT/OUTPUT PORT PROGRAMMING
Any port pin is programmable as either an input or an
output under software control of the corresponding data
direction register (DDR). Each port bit can be selected as
output or input by writing the corresponding bit in the
port DDR to a logic one for output and logic zero for input.
On reset, all ODRs are initialized to logic zero to put the
ports in the input mode. The port output registers are not
initialized on reset but may be written to before setting
the DDR bits to avoid undefined levels.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Refer to
Figure 3 for typical port circuitry and to Table 1 for a list
of the 1/0 pin functions.

OUTPUT COMPARE (TCMP)
This pin provides an output for the output compare
feature of the on-chip timer.

Table 1. I/O Pin Functions

RESET
This pin is used to reset the MCU and provide an orderly start-up procedure by pulling RESET low.
INPUT/OUTPUT PORTS (PAO-PA7, PBO·PB7, PCO·PC7)
These 24 lines are arranged into three 8-bit ports (A,
8, and C). These ports are programmable as either inputs
or outputs under software control of the data direction
registers. Refer to PROGRAMMING for additional information.
FIXED INPUT PORT (PDO·PDS, PD7)
These seven lines comprise port '9, a fixed input port.
Refer to PROGRAMMING for additio'nal information.

RIW*

DDR

1/0 Pin Functions

0

0

The 110 pin is in input mode. Data is
written into the output data latch.

0

1

Data is written into the output data latch
and output to the 110 pin.

1

0

The state of the 110 pin is read.

1

1

The 110 pin is in an output mode. The
output data latch is read.

*RiW is an internal signal.

FIXED INPUT PORT PROGRAMMING
Port D is a fixed input port'(PDO-PD5, PD7) that monitors
the external pins. To avoid spurious interrupts and erratic
operation of port D, memory accesses to unused locations $OOOA through $0011 must not be performed.

PROGRAMMING

NOTE

Input/output port prog,ramming and fixed input port
programming are discussed in the following paragraphs.

Any unused inputs and 1/0 ports should be tied to
an appropriate logic level (e.g., either VDD or VSS).

MOTOROLA MICROPROCESSOR DATA
3-794

MC68HC05C2

lID

Internal
MCU
Connections

Pin

Figure 3. Typical Port 1/0 Circuit

PROGRAM COUNTER (PC)

MEMORY
The MCU is capable of addressing 8192 bytes of memory and I/O registers, as shown in Figure 4. The locations
consist of user ROM, user RAM, self-check ROM, control
registers, and I/O. The user-defined reset and interrupt
vectors are located from $1 FF4 to $1 FFF.
The shared stack area is used during processing of an
interrupt or subroutine call to save the CPU state. The
stack pointer decrements during pushes and increments
during pulls. Refer to INTERRUPTS for additional information.
NOTE
Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

REGISTERS
The MCU contains the registers described in the following paragraphs.
ACCUMULATOR (A)

The program counter is a 13-bit register that contains
the address of the next byte to be fetched.
12

PC

STACK POINTER (SP)
The stack pointer is a 13-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to location $OOFF. The stack pointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the seven most significant
bits are permanently set to 0000011. These seven bits are
appended to the six least significant register bits to produce an address within the range of $OOFF to $OOCO.
Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer
wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack;
an interrupt uses five locations.
12

The accumulator is a general-purpose 8-bit register used
to hold operands and results of arithmetic calculations
or data manipulations.

7

101010101011111

SP

CONDITION CODE REGISTER (CCR)
A

INDEX..REGISTER (X)
The index register is an 8-bitregister used for the indexed addressing mode. It contains an 8-bit value that
maybe added to an 8- or 16-bit immediatavalue to create
an effective address. The index register may also be used
as a temporary storage area.

The CCR is a 5-bit register in which four bits are used
to indicate the results of the instruction just executed.
These bits can be individually tested by a program, and
specific actions can be taken as a result of their state.
Each bit is explained in the following paragraphs.
CCR

Half Carry (H)
This bit is set during ADD and ADC operations to
dicate that a carry occurred between bits 3 and 4.

x

MOTOROLA .MICROPROCESSORDATA
3-795

in~

II

MC68HC05C2

$0000

0000

0000
Ports
7 Bytes

1/0
32 Bytes

0031

$OOlF
$0020

User
ROM
48 Bytes

$OO4F
$0050

Unused

\ 0032

11 Bytes

\

\

007~\

~--I--Stack
64 Bytes

$OOFF
$0100

\
0191
0192

\
\

\

$lFFF

Unused
4 Bytes

User
Vectors

12 Bytes

SOB
SOC

Unused

$00

Unused

$OE
$OF

$10

\
\
\

\
\
\
\
256 Bytes

Unused
Unused

Unused

\

8175
8176

$OA

\

\
\

Self-Check
Vectors

$09

Unused

Unused

\
\

r-.-----

Unused

\

\

Self Check

$lFF3
$1 FF4

$06

\

7935
7936

$lFEF
$lFFO

$07

Unused

\

0255
0256

Unused
5632 Bytes

$1 FDF
$lFEO

$06

Unused

0031

4351
4352

$1 EFF
$lFOO

$05

Port C Data Direction Register

\

ROM
2048 Bytes

II

$04

Port B Data Direction Register

Unused
4 Bytes

User

$08FF
$0900

$03

Port A Data Direction Register

\

\
$OOBF
$OOCO

$02

\

RAM
176 Bytes

$01

Port C Data Register

10 Bytes

\

$00

Port B Data Register

Port 0 Fixed Input Register

Timer

0080 \

Port A Data Register

Unused

$11

Timer Control Register

$12

TImer Status Register

$13

Input Capture High Register

$14

Input Capture Low Register

$15

Output <;:omP:'re High Register

$16

Output Compare Low Register

$17

Counter High Register

$18

Counter Low Register

$19

\

Alternate Counter High Register

$1A

\

Alternate Counter Low Register

$1B

\

Unused

$1C

Unused

\
\

$10

Unused

$1E

\

Unused

$1F

\
\

8179
8180
8191

Figure 4. Memory Map

Interrupt (I)
When this bit is set, the timer and external interrupt is
masked (disabled). If an interrupt occurs while this bit is
set, the interr,upt is latched and processed as soon as the
interrupt bit is cleared.
Negative (N)
When set, this bit indicatEls that the result of the last
arithmetic, logical, or data manipulation was negative
(bit 7 in the result is a logic one).
Zero (Z)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipuldtion was zero.
Carry/Borrow (C)
When set, this bit indicates that a carry or borrow o~t
of the arithmetic logical unit (ALU) occurred during the

last arithmetic operation. This bit is also affected during
bit test and branch instructions and during shifts and
rotates.

SELF-CHECK
The self-check capability provides the ability to determine if the device is functional. Self-check is performed
using the circuit shown in Figure 5. Port C pins PCO-PC3
are monitored for the self-check results. After reset, the
following seven tests are performed automatically:
1/0 - Exercise of ports A, B, and C
RAM - Counter test for each RAM byte
ROM .::.-. Exclusive OR with odd ones parity result
Timer - Tracks counter register and checks OCF flag
Interrupts - Tests external, and timer interrupts
Self-check results (using the LEOs as monitors) are
shown in Table 2. The following subroutines are available
to the user and do not require any external hardware.

MOTOROLA MICROPROCESSOR DATA
3-796

MC68HC05C2

RESET
+9V

10k

47~
2N3904

-2.

+5V
10k

RESET

10k
VOO

NC

37

40

+5V

39

OSCl

"='

:I,q

1

iRa

TCAP

10M

MCU

~

~

PA7

~

PA6

6
7

TCMP ~
34
P05
33 1M
P04
32
P03
31
P02
30
POl

PA4

~ PA3
~ PA2
10
11

36

P07

PAl
PAO

POO
12

-

10k

~
14
15

~

18
19

28

PBO

PCO

PBl

PCl

PB2

PC2 26
25
PC3

PB3

~ PB4

---.!l

29

PC4

PB5

PC5

PB6

PC6
PC7

PB7

IhF
I
"='
4MHz

I I~F
"='

38

OSC2

PA5

1
o

(See Notel

I

+5V

~
~

4.7K

2N3904

10k

I

~.
~

27
~~

"='
1k

\}
,

+5V
1k

1k

... '!-

~

,..

1k

23
22
21

VSS

...L20
NOTE: The RC Oscillator Option may also be used in this circuit.

Figure 5. Self-Check Circuit Schematic Diagram

checks for correct counting. The test tracks the counter
until the timer wraps around, triggering the output compare flag in the timer status register. RAM locations $0050
and $0051 are overwritten. Upon return to the user's program, X=40. If the test passed, A=O.

Table 2. Self-Check Results

PC3 PC2 PC1

PCO

Remarks

1

0

0

1

Bad 1/0

1

0

l

0

Bad RAM

1

0

1

1

Bad Timer

1

1

0

1

Bad ROM

1

1

1

1

Flashing
All Others

o indicates LED is on;
TIME~

ROM CHECKSUM SUBROUTINE
This subroutine returns with the Z bit cleared if any
error is detected; otherwise, the Z bit is set. The ROM
checksum subroutine is called at location $1F93 with RAM
location $0053 equal to $01 and A=O. A short routine is
set up and executed in RAM to compute a checksum of
the entire ROM pattern. RAM locations $0050 through
$0053 are overwritten. Upon return to the user's program,
X = O. If the test passed, A = O.

Bad Interrupts or IRQ Request
Good Device
Bad Device, Bad Port C, etc.

1 indicates LED is off.

TEST SUBROUTINE

This subroutine returns with the Z bit cleared if any
error is detected; otherwise, the Z bit is set. The timer
test subroutine is called at location $1 FOE. The output
compare register is first set to the current timer state.
Because the timer is free running and has only a divideby-four prescaler, each timer count cannot be tested. The
test reads the timer once every 10 counts (40 cycles) and

RESETS
The MCU can be reset two ways: by initial power-up
and by the external reset input (RESET). The RESET in~
consists mainly of a Schmitt trigger that senses the RESET line logic level.

MOTOROLA MICROPROCESSOR DATA
3-797

II

MC68HC05C2

POWER-ON RESET (POR)

TIMER INTERRUPT
There are three different timer interrupt flags that cause
a timer interrupt whenever they are set and enabled. The
interrupt flags are in the timer status register (TSR), and
the enable bits are in the timer control register (TCR).
Refer to TIMER for more information.

An internal reset is generated on power-up to allow
the internal clock generator to stabilize. The power-on
reset is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage.
There is a 4064 internal processor clock cycl~) delay
after the oscillator becomes active. If the RESET pin is
low at the end of 40~, the MCU will remain in the
reset condition until RESET goes high.

EXTERNAL INTERRUPT
If the interrupt mask bit (I bit) of the CCR is set, all
interrupts are disabled. Clearing the I bit enables the external interrupt. The external interrupt is internally ~­
chronized and then latched on the falling edge of IRQ.
The action ofthe external interrupt is identical to the timer
interrupt with the exception that the interrupt request
input at IRQ is latched internally and the service routine
address is specified by the contents of $1 FFA and $1 FFB.
Either a level-sensitive and edge-sensitive trigger, or
an edge-sensitive-only trigger are available as a mask
option. Figure 8 shows both a functional internal diagram
and a mode timing diagram for the interrupt line. The
timing diagram shows two treatments of the interrupt
line to the processor. The first method shows a single
pulse on the interrupt line spac.ed far enough apart to be
serviced. The minimum time between pulses is a function
ofthe length of the interrupt service. Once a pulse occurs,
the next pulse should not occur until an RTI occurs. This
time (tILlL) is obtained by adding 21 instruction cycles to
the total number of cycles it' takes to complete the service
routine (not including the RTI instruction). The second
method shows many ioterrupt lines "wire-ORed" to form
the interrupts at the processor. If the interrupt line remains low after servicing an interrupt, then the next in. terrupt is recognized.

EXTERNAL RESET INPUT
The MCU is reset when a logic zero is applied to the
RESET input for a period of one and one-half machine
cycles (tcyel.

INTERRUPTS

II

The MCU can be interrupted three different ways: the
two maskable hardware interrupts (IRQ and timer) and
the nonmaskable software ioterrupt instruction (SWI).
Interrupts cause the processor to save register contents
on the stack and to set the interrupt mask (I bit) to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal
processing to resume. The stacking order is shown in
Figure 6.
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.
NOTE
The current instruction is the one already fetched
and being operated on.

NOTE
The internal interrupt latch is cleared in the first part
of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced
as soon as the I bit is cleared.

When the current instruction is complete, the processor
checks all pending hardware interrupts. If unmasked (I
bit clear) and if the corresponding interrupt enable bit is
set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction, regardless of the I-bit state.
Refer to Figure 7 for the reset and interrupt instruction
processing sequence.

SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCA. If the I bit
is zero, SWI executes after the other interrupts. The SWI
operation is similar to the hardware interrupts. The interrupt service routine address.is specified by the contents of memory locations $1 FFCand $1 FFD.
Stack

Increasing Memory
Addresses

1;

U

f!
N

'-I 1 l' I

Condition Code Register
Accumulator
Index Register

01- 010 1

PCH
PCl

I

n

Decreasing Memory
Addresses

P

T

Unstack

NOTE: Since the Stack Pointer decrements during pushes, the PCI, is .
stacked first, followed by PCH, etc. Pulling from the stack is
in the reverse order.

Figure 6. Interrupt Stacking Order

MOTQROLA, MICROPROCESSOR -DATA
3~798

MC68HC05C2

y

Clear iRO
Request
Latch

II
Load PC from:
SWI:$1FFC-$1FFD
IRQ: $1 FFA-$1 FFB
Timer: $1FFS-$1FFS

Complete
Interrupt
Routine
and Execute
RTI

Figure 7. Reset and Interrupt Processing Flowchart

MOTOROLA MICROPROCESSOR DATA

3..799

MC68HC05C2

Level-Sensitive Trigger

------Mask Option

VDD ,...-_ _..,
D

External
Interrupt
Request

01-----1

Interrupt Pin - - - -.....---4~:>C
I Bit (CC)

Power-On Reset
External Reset
External Interrupt
Being Serviced (Vector Fetch)
(a) Interrupt Internal Function Diagram

II

ilm~tlLlH

I~

U

Edge-Senlitive Trigger CondItIon
The minimum pulse width ItjLlHI is either
125 nsIVDO=5 VI or 250 ns 1VOO=3 V)'
The period tlLlL should not be less than
the number of tcvc cycles it takes to execute the interrupt service routine plus 21
tcvc cycles.

tILlL----...,·~1

Level-Senlitive Trigger CondItIon
If after servicing an interrupt the i1iQ remains low, then the next interrupt is
recognized.

L - -_ _ _ _

IROn

TIm!

(MCUI

~

~r

____________________________

Normally
Used with
Wire-ORed
Connection

r

~

(b) Interrupt Mode Diagram

Figure 8. External Interrupt

LOW-POWER MODES
STOP
The STOP instruction places the MCU in its lowest power
consumption mode. In the STOP mode, the internal oscillator is turned off, halting all internal processing including timer operation (refer to Figure 9).
During the STOP mode, the TCR bits are altered to
remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is
cleared. The I bit in the CCR is cleared to enable external
interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the STOP mode only by an
external interrupt or reset.

WAIT
The WAIT instruction places the MCU in a low-power
consumption mode, but the WAIT mode consumes more
power than the STOP mode. All CPU action is suspended,
but the timer remains active (refer to Figure 10). An interrupt from the timer can cause the MCU to exit the WAIT
mode.
During the WAIT mode, the I bit in the CCR is cleared
to enable interrupts. All other registers, memory, and
input/output lines remain in their previous state. The timer
may be enabled to allow a periodic exit from the WAIT
mode.
DATA RETENTION MODE
The contents of RAM and CPU registers are retained
at supply voltages as low as 2.0 Vdc. This is called the

MOTOROLA MICROPROCESSOR DATA.
3-800

MC68HC05C2

NOTE
The I bit in the CCR should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does
not occur.

Stop Oscillator
And All Clocks

COUNTER

Clear I Bit

Yes

(1) Fetch Reset Vector or
(2) Service Interrupt

a, Stack
b, Set I Bit
c, Vector to Interrupt
Routine

Figure 9. STOP Function Flowchart
data retention mode where the data is held, but the device
is not guaranteed to operate. The MCU should be in RESET
during data retention mode.

TIMER
The timer consists of a 16-bit, software-programmable
counter driven by afixeddivide~by-four prescaler. This'
timer can be used for many purposes, including input
waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from
several microseconds to many seconds; Refer to Figure
11 for a timer block diagram.
Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two
registers. These registers contain the high and low byte
of that functional segment. Generally, accessing 'the low
byte of a specifictimerfunction allows full controlofthat
function; however, an access of the high byte inhibits
that specific timer function until the low byte is also accessed.
.

The key element in the programmable timer is a 16bit, free-running counter or counter register, preceded by
a prescaler that divides the internal processor clock by
four. The prescaler gives the timer a resolution of 2.0
microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock. Software can read the counter at any
time without affecting its value.
The double-byte, free-running counter can be read from
either of two locations, $18-$19 (counter register) or
$1A-$1 B (counter alternate register). A read from only
the least significant byte (LSB) ofthe free-running counter
($19, $1 B) receives the count value atthe time ofthe read.
If a read of the free-running counter or counter alternate
register first addresses the most significant byte (MSB)
($18, $1A), the LSB ($19, $1B) is transferred to a buffer.
This buffer value remains fixed after the first MSB read,
even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or
counter alternate register LSB ($19 or $1 B) and, thUS,
completes a read sequence of the total counter value. In
reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be
read to complete the sequence.
The counter alternate register differs from the counter
register in one respect: a read ofthe counter register MSB
can clear the timer overflow flag (TOF). Therefore, the
counter alternate register can be read at any time without
the possibility of missing timer overflow interrupts due
to clearing of the TOF.
The free-running counter is configured to $FFFC during
reset and is always a read-only register. During a poweron reset, the counter is also preset to $FFFC and begins
running after the oscillator start-up delay. Because the
free-running counter is 16 bits preceded by a fixed divideby-four prescaler, the value in the free-running counter
repeats every 262,144 internal bus clock cycles. When the
counter rolls over from $FFFF to $0000, the TOF bit is set.
An interrupt can also be enabled when counter rollover
occurs by setting its interrupt enable bit (TOlE).
OUTPUT COMPARE REGISTER
The 16-bit output compare register is made up of two
8-bit registers at locations $16 (MSB) and $17 (LSB). The
output compare register is used for several purposes,
such as indicating when a period of time has elapsed. All
bits are readable and writable and are not altered by the
timer hardware or reset. If the compare function is not
needed, the two bytes of the output compare register can
be used as storage locations.
The output compare register contents are compared
with the contents of the free-running counter continually,
and if a match is found, the corresponding output com~
pare flag (OCF) bit is set and the corresponding output

MOTOROLA MICROPROCESSOR DATA

3-801

MC68HC05C2

Oscillator Active
Timer
Clock Active
Proces.sor Clocks Stopped

II
c. Vector to Interrupt
Routine

Figure 10. WAIT Function Flowchart
level (OLCL) bit is clocked to an output level register. The
output compare register values and the output level bit·
should be. changed after each successful comparison to
establish a. new elapsed timeout. An interrupt can. also
accompany a successful output compare provided the
corresponding interrupt enable bit(OCIE) is set.
After a processor write cycle to the output compare
register containing the MSB ($16), the output compare
function is inhibited until the LSB($17). is also written.
Th~ user must write both bytes (locations) if the MSB is
written first.A write made only to the LSB ($17) will not
inhibit the compare function. The free-running counter is
updated every four internal bus clock cycles. The minimum time required to upd~tethe output compare regist~r is a function of the. program rather than the internal
hardware~
.
.
The processor can. write to~ither byte of the output
compare register without affecting the other byte. The
output level. (OLVl.,) bit is clocked to the output level.register regardless of whether the output compare flag (OCF)
is set or clear.

INPUT CAPtURE REGISTER
Two 8-bit registers, which make up the 16-bit input
capture register, are read-only and are used to latch the
value of the free-running counter after the corresponding
input capture edge detector senses a defined transition.
The level transition Which triggers the counter transfer is
defined by the corresponding inp!Jt edge bit (lEDG). Re$et
does not affect the contents of the input capture register.
The result obtained by an input capture will be one
more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the .external transition. This <;jelay is required for internal synchronization. Resolution is one cou.nt of the free-running
counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to
the input capture register on each proper signal transition
regardless of whether the input capture flag .(lCF)is set
or dear.The input capture register always contains the
free-run'ning counter value that corresponds to the most
recent input capture.

MOTOROLA MICROPROCESSOR DATA
3-802

MC68HC05C2·

Internal Bus
Internal

Processor
Clock

High
Byte

Low
Byte

Low
Byte

High
Bvte

Low
Byte

$16

$18

$14

$17

$19

$15

$lA
$lB

Timer

II

~.L-""T"""""'-r...;.;&--'

Status

Reg.

Output
Level

Edge
Input

(TCMP) nCAP)

Figure 11. Timer BIQckDiagram

After a read of the input capture register ($14) MSB,
the counter transfer is inhibited until the LSB ($15) is also
read. This characteristic causes the time used in the input
capture software routine and its interaction with the main
program to determine the minimum pulse period.
A read of the input capture register LSB'($15) does not
inhibit the free-running counter transfer since they occur
on opposite edges of the internal bus clock.
TIMER CONTROL REGISTER (TCR) $12

The TCR is a read/write register containing five control
bits. Three bits control interrupts associated with the timer
status register flags ICF, OCF, and TOF.
7

I ICIE I OCIE
RESET:

o

TOlE

IEDG

u

OlVl

ICIE - Input Capture Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
OCIE - Output Compare Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
TOlE --'-Timer Overflow Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
IEDG - Input Edge
Value of input edge determines which level.transition
on TCAP pin will trigger free-running counter transfer
to the input capture register
,."
1 = Positive 'edge
0= Negative edge
Reset does not affect the IEDG bit (U = unaffected).

MOTOROLA MICROPROCESSOR DATA
3-803

MC68HC05C2

RESET is used, the counter is forced to $FFFC. During
STOP, if at least one valid input capture edge occurs at
the TCAP pin, the input capture detect circuit is armed.
This does not set any timer flags nor wake up the MCU,
but when the MCU does wake up, there is an active input
capture flag and data from the first valid edge that occurred during the STOP mode. If RESET is used to exit
STOP mode, then no input capture flag or data remains,
even if a valid input capture edge occurred.

OLVL - Output Level
Value of output level is clocked into output level register by the next successful output compare and will
appear on the TCMP pin
1 = High output
0= Low output
Bits 2, 3, and 4 - Not used
Always read zero
TIMER STATUS REGISTER (TSR) $13
The TSR is a read-only register containing three status
flag bits.
.

INSTRUCTION SET

7

I

ICF

RESET:
U

II

I

OCF

TOF

u

u

The MCU has a set of 62 basic instructions. They can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.
This MCU uses all the instructions available in the
M146805 CMOS Family plus one more: the unsigned
multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator
(A) and the index register (X). The high-order product is
then stored in the index register, and the low-order product is stored in the accumulator. A detailed definition of
the MUL instruction is shown below.

ICF - Input Capture Flag
1 = Flag set when selected polarity edge is sensed by
input capture edge detector
0= Flag cleared when TSR and input capture low register ($15) are accessed
OCF - Output Compare Flag
1 = Flag set when output compare register contents
match the free-running counter contents
0= Flag cleared when TSR and output compare low
register ($17) are accessed
TOF - Timer Overflow Flag
1 = Flag set when free-running counter transition from
$FFFF to $0000 occurs
0= Flag cleared when TSR and counter low register
($19) are accessed
Bits 0-4 - Not used
Always read zero
Accessing the timer status register satisfies the first
condition required to clear status bits. The remaining step
is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow
function and reading the free-running counter at random
times to measure an elapsed time. Without incorporating
the proper precautions into software, the timer overflow
flag could unintentionally be cleared if:
1) The timer status register is read or written when
TOF is set, and
2) The LSB of the free-running counter is read but not
for the purpose of servicing the flag.
.
The counter alternate register at address$1A and $1 B
contains the same value as the free-running counter (at
address $18 and $19); therefore; this alternate register
can be read at any time without affecting the timer-overflow flag in the timer status register.

Operation

X:AX*A

Description

Multiplies the eight bits in the index register
by the eight bits in the accumulator to obtain
a 16-bit unsigned number in the concatenated
accumulator and index register

Condition
Codes

H: Cleared
I: Not affected
N: Not affected
Z: Not affected
C: Cleared

Source

MUL

Form(s)

Addressing
Mode
Inherent

I

Cycles
11

I

Bytes
1

JOpcode
$42

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the.accumulator or the index register. The
other operand is obtained from memory u~ing one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JS.R) instructions have no register
operand. Refer to the following instruction list.

TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the
timer remains active. An interrupt from the timer causes
the processor to exit the WAIT mode.
.
TIMER DURING STOP MODE
In the STOP mode, the timer stops counting and holds
the last count value if STOP is exited by an interrupt. If

Function

LOA

Load X from Memory

LOX

Store A in Memory

STA

Store X in Memory

STX

Add Memory to A

ADD

Add Memory and Carry to A

MOTOROLA MICROPROCESSOR DATA
3-804

Mnemonic

Load A from Memory

AOC
- Continued

MC68HC05C2

Function

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, nooperation is performed. Branch
instructions are two-byte instructions. Refer to the following list for branch instructions.

Mnemonic

Subtract Memory

SUB

Subtract Memory from A with Borrow

SBC

AND Memory to A

AND

OR Memory with A

ORA

Exclusive OR Memory with A

EOR

Branch Always

BRA

Arithmetic Compare A with Memory

CMP

Branch Never

BRN

Arithmetic Compare X with Memory

CPX

Branch if Higher

BHI

Bit Test Memory with A (Logical Compare)

BIT

Branch if Lower or Same

BLS

Jump Unconditional
Jump to Subroutine

Function

JMP
JSR

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.
Function

Mnemonic

Mnemonic

Branch if Carry Clear

BCC

Branch if Higher or Same

BHS

Branch if Carry Set

BCS

Branch if Lower

BLO

Branch if Not Equal

BNE
BEQ

Branch if Equal
Branch if Half Carry Clear

BHCC

Branch if Half Carry Set

BHCS

Branch if Plus

BPL

Branch if Minus

BMI

INC

Branch if Interrupt Mask Bit is Clear

BMC

Decrement

DEC

Branch if Interrupt Mask Bit is Set

BMS

Clear

CLR

Increment

Complement

COM

Negate (Twos Complement)

NEG

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Logical Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

Multiply

BIL

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

CONTROL INSTRUCTIONS
These instructions are register refer~nce instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.
Function

MUL

BIT MANIPULATION INSTRUCTIONS
The MCU is capable of setting or clearing any writable
bit which resides in the first 256 bytes of the memory
space where all port registers, port DDRs, timer, timer
control, ROM, and on-chip RAM reside. An additional
feature allows the software to test and branch onthe state
of any bit within these 256 locations. The bit set, bit clear
and bit test, and branch functions are all implemented
with a single instruction. For test and branch instructions,
the value of the bit tested is also placed in the carry bit
of the condition code register. Refer to the following list
for bit manipulation instructions.
Function

Branch if Interrupt Line is Low

Mnemonic

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

CLC

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

Reset Stack Poi nter

RSP

No-Operation

NOP

Mnemonic

Stop

STOP

Wait

WAIT

Branch if Bit n is Set

BRSET n (n=O ... 7)

Branch if Bit n is Clear

BRCLR n (n=O ... 7)

Set Bit n

BSH n (n=O ... 7)

Clear Bit n

BCLR n (n=O ... 7)

OPCODE MAP SUMMARY
Table 3 is an opcode map for the instructions used on
the MCU.

MOTOROLA MICROPROCESSOR DATA
3-805

II

•

Table 3. Opcode Map
I ar.nch I

Bit ~

BTlfI.!r~--1

Reed/Modify/Write

REl

DIR

~T~ ~-l,l;;
o

0000

I
.J!!!!ll
2

0010

5f BSETOBSC
-°1-2
13BRSETO
BTB 2

51

BRClRO

BClRO

51

13 BTB 2 BSC 2
51 BSET1BSC51 2
13BRSETl
BTB 2

BRA

31

J

REL

BRN

INH

~,
2

INH

~

~

--.l

REL

31
REL

BHI

L

---.l

61'
IXI 1

NEG

I

~-11 =r--~
MUl
INH

__

_

r

I_Jlft,

~~o

51 NEGAINH31 1 NEGXINH31 -2
OIR 1

NEG

Control

~J_.JNH ~

IXI

It~,

___
-_

INK.... 1

I~

I

NEG 5 _ _

IX 11 ___ I

~...L

I

1 -1

~/MemoIv

EXT

----C-.l
1

INH

____

OIR

IX2

,foo LJL I
SUB 41
SU_ B___ 51
3_ EXT L _ _ IX2 2

12 CMP
- 21 2-CMP 31 3 CMP 41

RTS 6

__

1

-L__

,:m~_I~L_Qo
~
~ SUB
~ SUB ___31
RlI_ ~

I2

_

IMM

OIR

CMP

EXT.3. _

51

IX2

IXI

IX

II~O

4j

SUB

1)(1

CMP
2

21 SBCOIR31 3 SBCEXT41-~L
SBC
IMM 2
3
1X2 2

SBC

41

,f"
1

1
IX

0000

CMP

31



(XXX)

4:j

Opcode in Hexadecimal
Opcode in -Binary

' - - - - - - - - - - Address Mode

3:
C')

i:I:

C')

~

o

MC68HC05C2

ADDRESSING MODES
The MCU uses ten different addressing modes to provide t~e programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion t~bles,and scaling tables anywhere in the memory space. Short indexed accesses are single byte
instructions; the longest instructions (three bytes) permit
accessing tables throughout memory. Short and long absolute addressing'is also included. One- or two-bytedirect addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions to reach all memorY;
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.
IMMEDIATE
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).
DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to. directly
address thelowest256 bytes in memory withasingle
two-byte instruction.
.
.
EXTENDED
In the extended adQressing mode, the effective address
of the .argumen,t is. contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode areciipable of referencing arguments anywhere in
memory with a single three-byte instruction. When using
the Motorola assembler, the user need not specify whether
an instruction uses direct or extended addreSSing. The
assembler automatically selects the shortest form of the
instruction.
RELATIVE
The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from -126to + 129 from
the opcode address. The programmer need not calculate
the offset when using the Motorola assembler, since it
calculates the proper offset and checks to see that it is
within the span of the branch.
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256

memory lo.cations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or.to hold the address of a frequently referenced
RAM or I/O location;
INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mod~, the effective address is the sum ofthe contents ofthe unsigned
8-bit index register and the Unsigned byte foll()wingthe
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
the. beginning of. the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1FE is the last location at which the instruction may
begin).
. INDEXED, 16-BIT OFFSET
In the indexed, 16-bit offset addressing mode, the effective address is the sum ofthe c.oritentsofthe unsigned
8-bit index register and the two unsigned bytes following
the opcode. This address mode can be used in a manner
similar to indexed, 8-bit offset except that this three-byte
instruction allows tables to be anywhere in memory. As
with direct and extended addressing, the· Motorola assembler determines the shortest form of indexed addressing.
BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode, and the byte following
the opcode specifies the direct addressing of the byte in
which the specified bit is to be set or cleared. Any read/
write bit in the first 256 locations ofmemor'y, including
I/O, can be selectively set or cleared with a single twobyte instruction.
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressingan'd relative addressing. The
bit that is to be tested and its condition (set or clear), is
included in the opcode. The address of the byte to be
tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third
byte is added to the PC if the specified bit isset or cleared
in the specified memory location. This single three-byte
instruction allows the program to branch based on the
condition· of any readable bit in the first 256 locations of
memory: The span of branching is from .-:-125 to + 130
from the opcode address. The state of the tested bit is
also transferred to the carry bit of the COndition code
registt)r.
INHERENT
In the inherent addreSSing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well. as the. control instruction with no
other arguments are included in this mode. These instructions are one byte long.

MOTOROLA MICROPROCESSOR DATA
3-807

I

MC68HC05C2

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS (Voltages referenced to VSS)
Symbol

Value

Unit

Supply Voltage

Rating

VOO

-0.3 to +7.0

V

Input Voltage

Yin

VSS -0.3 to
VOO +0.3

V

Self-Check Mode (IRQ Pin Only)

Yin

VSS-0.3 to
2xVOO+0.3

V

Current Drain Per Pin Excluding
VOO and VSS

I

25

rnA

TA

TL to TH
+70
-40 to +85
-40 to +105
-40 to +125

°C

-65 to +150

°C

Operating Temperature Range
MC68HC05C2P, FN
MC68HC05C2CP, CFN
MC68HC05C2VP, VFN
MC68HC05C2MP, MFN
Storage Temperature Range

I

o to

TstQ'

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it 'is advised that normal precautions be taken to avoid application of
any voltage higher than maximum-rated voltages
to this high-impedance ci(coit. For proper operation, it is recommended that Yin and Vout be
constrained to the ,range VSS os;; (Vin or Vout) os;;
VOO. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic
voltage level (e.g., either VSS or VOO)·

THERMAL CHARACTERISTICS
Characteristic

Symbol

Thermal Resistance
Plastic
PI,astic Leaded Chip Carrier (PLCC)

IIJA

Value

Unit

°CIW
60
70

POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °C can
be o,btained from:
TJ=TA+(PO-6JA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
6JA
Junction-to-Ambient, °CIW
Po
= PINT+PI/O
= ICCxVCC' Watts - Chip Internal Power
PINT
= Power Dissipation on Input and Output
PI/O
Pins - User Determined

For most applications PI/O

;-

~tRL---1

RESET

1

¥

***
*Internal timing signal and bus information not available externally.
* * OSCl line is not meant to represent frequency. It is only used to represent time.
* * *The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.

Figure 21. Power-On Reset and RESET

MC68HC05C2

ORDERING INFORMATION
The following information is required when ordering a
custom MCU. The information may be transmitted to Motorola in the following media:
MDOS@J, disk file
MS@J-DOS/PC-DOS disk file (360K)
EPROM(s) 2764, MCM68764, MCM68766, or EEPROM
MC68HC805C4
To initiate a ROM pattern for the MCU, it is necessary
to first contactthe local field service office, a sales person,
or a Motorola representative.

$0020
xxx = Customer 10

Verification Media
FLEXIBLE DISKS

A flexible disk (MS-DOS/PC-DOS disk file), programmed with the customer's program (positive logic
sense for address and data), may be submitted for pattern
generation. The diskette should be clearly labeled with
the customer's name, data, project or product name, and
the name of the file containing the pattern.
In addition to the program pattern, a file containing the
program source code listing can be included. This data
will be kept confidential and used to expedite the process
in case of any difficulty with the pattern file.

All original pattern media (EPROMs or floppy disks) are
filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and
returned along with a listing verification form. The listing
should be thoroughly checked, and the verification form
should be completed, signed, and returned to Motorola.
The signed verification form constitutes the contractual
agreement for the creation of the customer mask. To aid
in the verification process, Motorola will program customer ~upplied blank EPROM(s) or DOS disks from the
data file used to create the custom mask.

MS-DOS/PC-DOS Disk File

ROM VERIFICATION UNITS (RVUs)

MS-DOS is Microsoft's Disk Operating System. PC-DOS
is the IBM® Personal Computer (PC) Disk Operating System. Disk media submitted must be a standard density
(360K) double-sided5114 inch compatible floppy diskette.
The diskette must contain object file code in Motorola's
S-record format. The S-record format is a character-based
object file format generated by M6805 cross assemblers
and linkers on IBM PC style machines.

Ten MCUs containing the customer's ROM pattern will
be sent for program verification. These units will have
been made using the custom mask, but are for the purpose of ROM verification only. For expediency, the MCUs
are unmarked, packaged in ceramic, and tested with five
volts at room temperature. These RVUs are free with the
minimum order quantity, but are not production parts.
RVUs are not backed or guaranteed by Motorola Quality
Assurance.

EPROMs

A 2764, 68764, or 68766 type EPROM, programmed
with the customer's program (positive logic sense for
address and data), may be submitted for pattern generation. Since all program and data space information will
fit on one 2764, 68764, or 68766 EPROM device, the EPROM
must be programmed as described in the following paragraphs.
For an MC68HC805C4 MCU start the page zero, user
ROM at EEPROM address $0020 through $004F. Start the
user ROM at EEPROM address $0100 through $08FF with
vectors from $1 FF4 to $1 FFF. All unused bytes, including
the user's space, must be set to zero. For shipment to
Motorola, EPROMs should be placed in a conductive IC
carrier and packed securely. Styrofoam is not acceptable
for shipment.

ORDERING INFORMATION

The following table provides ordering information pertaining to the package type, temperature, and MC order
numbers for the MC68HC05C2 device.
Temperature

Me Order Number

Plastic
(P Suffix)

O°C to + 70°C
- 40°C to + 85°C
-40° to + 105°C
- 40°C to + 125°C

MC68HC05C2P
MC68HC05C2CP
MC68HC05C2VP
MC68HC05C2MP

PLCC
(FN Suffix)

O°C to + 70°C
- 40°C to + 85°C
- 40°C to + 105°C
- 40°C to + 125°C

MC68HC05C2FN
MC68HC05C2CFN
MC68HC05C2VFN
MC68HC05C2M FN

Package Type

MOOS is a trademark of Motorola Inc.
MS is a trademark of Microsoft, Inc.
IBM is a registered trademark of International Business Machines Corporation.

MOTOROLA MICROPROCESSOR DATA
3-817

II

MC68HC05C2

PIN ASSIGNMENTS

40-PIN DUAl-IN-LiNE PACKAGE
RESET

VOO

iRCi

OSCl

NC

OSC2
TCAP
PD7
TCMP

PA4

PD5

PA3

PD4

PAl

PD2

PD3
POl

II

PBa

PDa

PB2

PCl

PB3

PC2

pca

PB4

PC3

PB5

PC4

PB6

PC5

PB7

PC6

VSS

44-lEAD PlCC PACKAGE

~<

U

U

Ig It;;~ 8 ~-

N

Q.

~ ~

U

Q.Q.zz_a:>oOt-Z
PD7
TCMP
PD5
PD4
PD3
P02
POl
PDO
pea
PCl
PC2

PA4
PA3
PA2

PBa
PBl
'PB2
PB3
PB4
ULO"' ......

U)U ...... "'LO.,..,

z~~~~z~~~~~

NOTE: Bulk substrate tied to

Vss.

MOTOROLA MICROPROCESSOR DATA
3-818

MOTOROLA

SEMICONDUCTOR
TECHNICAL DATA

MC68HC05C3

Technical Summary

8-Bit Microcontroller Unit
The MC68HC05C3 (HCMOS) microcontroller unit (MCU) is a member of the M68HC05 Family of
microcontrollers. This high-performance, low-power MCU has parallel I/O capability with pins programmable as input or output. This publication contains .condensed information on the MCU; for
more detailed information, contact your local Motorola sales office.
Th.e following block diagram depicts the hardware features; additional features available on the
MCU are as follows:
. .
•
•
•
•
•
•
•
•
•
•
•
•

On-Chip Oscillator with RC or Crystal/Ceramic Resonator Mask Options
Memory-Mapped I/O
176 Bytes of On-Chip RAM
2096 Bytes of User ROM
24 Bidirectional I/O Lines and 7 Input-Only Lines
Serial Communications Interface (SCI) System
Serial Peripheral Interface (SPI) System
Self-Check Mode
Power-Saving STOP, WAIT, and Data Retention Modes
Single 3.0- to 5.5-Volt Supply (2-Volt Data Retention Mode)
Fully Static Operation
8 x 8 Unsigned Multiply Instruction

II

BLOCK DIAGRAM
TCMP

OSCl

t
TCAP

Port
A
1/0
Lines

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

Internal
Processor
Clock

Timer
System

OSC2

t t
I "",,;u,,",
~p,o~ro,
Internal

and
+2

I

~

Accumulator
Port
A
Reg

Data
Dir -<
Reg

.

Clock

CPU
Control

Index
Register

RESET
IRQ

r-

Data
Dir
Reg

Port
C
Reg

Condition
Code
Register

PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7

Port

C
I/O
Lines

CPU

Port

B
1/0
Lines

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

Stack
Pointer
Port
B
Reg

Data
Dir
Reg

r-

~

Program
Counter
High

SCt

~

SPI

PD7
RDt (PDQ)
TOO (PD1)
MtSO(PD2)
MOSI(PD3)
SCK (PD4)
-.:s:S (PD5)

Baud Rate
Generator

1
T
240 x 8
Self-Check
ROM

.ALU

Program
Counter
Low

2096x8
ROM

Port 0

T

I

l76x 8
Static
RAM

I

Int1nal
Processor
Clock

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA· MICROPROCESSOR DATA
3~819

MC68HC05C3

SIGNAL DESCRIPTION

RC Oscillator

The signal descriptions of the MCU are discussed in
the following paragraphs.
VOD AND VSS
Power is supplied to the microcontroller using these
two pins. VOO is the positive supply, and VSS is ground.
IRQ
This pin is a programmable option that provides two
different choices of interrupt triggering sensitivity. Refer
to INTERRUPTS for more detail.

II

OSC1,OSC2
These pins provide control input for an on-chip clock
oscillator circuit. A crystal, a ceramic resonator, a resistor/
capacitor combination, or an external signal connects to
these pins providing a system clock. A mask option selects either a crystal/ceramic resonator or a resistor/capacitor as the frequency determining element. The
oscillator frequency is two times the internal bus rate.

With this option, a resistor is connected to the oscillator
pins as shown in Figure 1(d). The relationship between
Rand fosc is shown in Figure 2.
Crystal
The circuit shown in Figure 1 (b) is recommended when
using a crystal. Using an external CMOS oscillator is recommended when crystals outside the specified ranges
are to be used. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and start-up stabiliiation time. Refer to ELECTRICAL SPECIFICATIONS for VOO
specifications.
Ceramic Resonator
A ceramic resonator maybe used in place of the crystal
in cost-se.nsitive applications. The circuit in Figure 1(b) is
recommended when using a ceramic resonator. Figure
1(a) lists the recommended capacitance and resistance
values. The manufacturer of the resonator considered

Crystal
RSMAX

Co

2 MHz
400

15-40
15-30
10

75
7
0.012
15-30
15-25
10

3(;

4(J

5

Cl
COSCl
COSC2
Rp
\)

Ceramic Resonator

4 MHz

O.~

Units
0

RS (typical)

pF
"F
pF
pF

MO
K

2·4 MHz
10

Co
Cl

40
4.3

COSCl
COSC2
Rp

30
30

Units

0
pF
pF
pF
pF

MO

1-10
1250

Q

-

(a) Crystal/Ceramic Resonator Parameters

~y
SC2

MCU
05Cl
39

Rp

38

'I'

L

Cl

RS

38

0502

.

OSC1
39

Co

~38~----~ID~1

_______3~9

C05C2

(c) Equivalent Crystal Circuit

(b) Crystal/Ceramic Resonator
Oscillator Connections

R

(d) RC Oscillator Connections

(e) External Clock Source Connections
(For Crystal Mask Option Only)

Figure 1. Oscillator Connections

MOTOROLA· MICROPROCESSOR DATA
3;;S20

MC68HCQ5C3

10

... ....

N

:x:

~

............

>-

U

C

~

0.5

f

0.2

j

O. 1

.....
I'

.~

o 0.05
0.02
0.0 1
1

10

20

50

100

500

200

1000

Resistance (km

Figure 2. Typical Frequency vs Resistance for
RC o.scillator o.ption o.nly
should be consulted for specific information on resonator
operation.
External Clock
An external clock should be applied to the OSC1 input
with the OSC2 input not connected, as shown in Figure
1(e). This option may only be used with the crystal oscillator mask option.
INPUT CAPTURE (TCAP)
This pin contrpls the input capture feature for the onprogrammable timer.

c~ip

OUTPUT Co.MPARE (TCMP)
This pin provides an output for the output compare
feature of the on-chip timer.
RESET

INPUT/o.UTPUT Po.RT PRo.GRAMMING
Any port pin is programmable as either an input or an
output under software control of the corresponding data
direction register (DDR) .. Each port bit can be selected as
output or input by writing the corresponding bit .in the
port DDR to a logic one for output and logic zero for input.
On reset, all DDRsare initialized to logic zero to put the
ports in the input mode. The port output registers are not
initialized on reset but may be written to before setting
the DDR bits to avoid undefined levels.
When.programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched Output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Refer to
Figure 3 for typical port circuitry and to Table 1 for a list
of the I/O pin functions.

This pin is used to reset the MCU and provide an orderly start-up procedure by pulling RESET low;
INPUT/o.UTPUT Po.RTS (PAO-PA7, PBO-PB7, PCO-.PC7)
These 24 lines are arranged into three 8-bit ports (A,
8, and C). These ports are programmable as either inputs
or outputs under software control of the data direction
registers. Refer to PRo.GRAMMING for additional information.
FIXED INPUT Po.RT (PDO-PD5, PD7)
These sev~n lines comprise port D, a fixed input port.
All special functions that are enabled (SPI, SCI) affect this
port. Refer to PRo.GRAMMING for additional information.

Table 1. I/o. Pin Functions
R!W*

DDR

0

0·'

0

1

Data is written into the output data latch
and output to the 110 pin~

1

0

The state of the I/O pin is read.

1

1

The I/O pin is in an output mode. The
output data latch is read.

110 Pin Functions
The I/O pin is in input mode. Data is
. written into the output data latch.

*RiW isan internal signal.

FIXED INPUT Po.RT PROGRAMMING

PROGRAMMING
Inputloutput.port programming, fixed input port programming, and serial port programming are discussed
in the following paragraphs.

Port D is a fixed input port (PDO-PD5, PD7) that monitors
the external pins whenever the SCI or SPI is disabled.
After reset, all seven bits become valid inputs because
all special function drivers are disabled. For: example,
with the SCI enabled, PD~ and PD1 inputs will r.ead zero.

MOTOROLA MICROPROCESSOROATA

3-821

II

MC68HC05C3

1/0
Pin

Internal
MCU
Connections

Figure 3. Typical Port 1/0 Circuit

II

With the SPI disabled, PD2 through PD5 will read the state
of the pin at the time of the read operation.
NOTE

ACCUMULATOR (A)
The accumulator is a general-purpose 8~bit register used
to hold operands and results of arithmetic calculations
or data manipulations.

Any unused inputs and '110 ports should be tied to
an appropriate logic level (e.g., eitherVDD or VSS).
A

SERIAL PORT (SCI AND SPI) PROGRAMMING
The SCI and SPI use the port D pins for their functions.
The SCI requires two pins (PDO-PD1) for its receive data
input (RD!) and transmit data output (TDO), respectiv~ly.
The SPI function requires four of the pins (P02-PD5) for
its serial data input/output (MIS,O);' serial, data ou~tI
input (IV!OSI), serial clock (SCK), and slave select (SS)'
respectively.'
;

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It containsan 8-bit value that
may be added to an 8- or 16-bit immediate value to create
an effective address. The indexregister may also be used
as a temporary storage area.
'

x

MEMORY
The MCU is capable of addressing 8192 bytes of memory and I/O registers, as shown in Figure 4. The locations
consist of user ROM, user RAM, self-check ROM, control
registers, and I/O. The user-defined reset and interrupt
vectors are located from $1 FF4 to $1 FFF.
The shared stack area is used during processing of an
interrupt Or subroutine call to save the CPU state. The
stack pointer:decrements during pushes and increments
during pLills. Refer to INTERRUPTS for additional information.
'
, NOTE
Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

REGISTERS
The MCU contains the registers described in the following paragraphs.

PROGRAM COUNTER (PC)
The program counter is a 13-bit register that contains
the address of the next byte to be fetched.
'12

STACK POINTER (Sp)
The stack pointer is a 13~bit register'that contains the
address of the next free location on the stack. During an
MCU ~esetorthe reset 'sta<:~ pOinter(RSP) instruction,
the stack pointeris setto location $OOFF. The stackpointer
is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the seven most significant
bits are permanently set to 0000011. These seven bits are
appended to the six least significant register bits to produce an address within the range of $OOFF to ,$OOCO.
Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer

MOTOROLA MICROPROCESSOR DATA
3-822

MC68HC05C3

$0000

0000

0000
Ports
7 Bytes

1/0
32 Bytes
$OOlF
$0020

0031

,
User
ROM

\
\

48 Bytes

$OO4F

Unused
3 Bytes

0032

0079

0000

$0050
RAM
176 Bytes

"

$OOBF
$OOCO

--l--S:k-

64 Bytes

$OOFF
$0100

0191
0192

\
0255
0256

User
ROM
2048 Bytes
$OBFF

\

Unused
5632 Bytes

\

$lFFF

$08

Unused

$09

Serial Peripheral Control Register

$OA

Serial PeripherarStatus Register

SOB

Serial Communications Control Register ,1

$OE

Serial Communications Controi Register 2

$OF

Serial Communications Status Register

$10

Serial Communications Data Register

$11

Unused
4 Bytes

\

\

\
\
\

\
\

256 Bytes

\
\

8 175
8 176

Timer Control Register

$12

Timer Status Register

$13

Input Capt4re High Register

$14

Input Capture low Register

$15

Output ~om~re High Register

$16

Output Compare low Register

$17

Counter High Register

$18

Counter low Register

$19

Alternate Counter High Register

$lA

Alternate Counter low Register

$lB

\

\

8179
8180

User
Vectors
12 Bytes

$07

0031

Self-Check
Vectors

Unused
4 Bytes

Unused
Unused

Timer

1------

$lFF3
$lFF4

$05
$06

10 Bytes

7935
7936

$lFEF
$lFFO

Port B Data Direction Register
Port C Data Direction Register

SOC

Self Check
$lFDF
$lFEO

$03

$04

$00

\

$1 EFF
$1 FOO

$02

Serial Communications Baud Rate Register

\
\

Port C Data Register

Serial Peripheral Data 1/0 Register

\
\

2303
2304

$0900

Seriill
Communications
Interface
5 Bytes

\

$01

Port A Data Direction Register

\

\

$00

Port B pata Register

Port 0 Fixed Input Register

,

Serial Peripheral
Interface
3 Bytes

\

Port A Data Register

\
\

8191

Unused

$lC

Unused

$10

Unused

$lE

Unused

$lF

Figure 4. Memory Map

wraps around and loses the previously stored information. A subroutine call occupies two locations on the'st'ack;
an interrupt uses five locations.
12

7

CONDITION CODE REGISTER (eCR)
The CCR is a 5-bit register in which four bits are used
to indicate the results of the instruction jus1 executed.
These bits can be individually tested by a program, and
specific actions can be taken as a result of their state.
Each bit is explained in the following paragraphs.

Interrupt (I)
When this bit.is set, the timer and external interrupt is
masked (disabl~d). If an interrupt occurs while this bit is
set, the interrupt is latched and processed as soon as the
interrupt bit is cleared:
Negative (N)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative
(bit 7 in the result is a logic one).
Zero IZ)
When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.

CCR

Half Carry (H)

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4:

Carry/Borrow (C)
When set, this bit indicates that a carry or borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmetic operation. This bit is also affected during
bit test and branch instructions and during shifts and
rotates.

MOTOROLA MICROPROCESSOR DATA
3-823

I

MC68HC05C3

SELF-CHECK

compare register is first set to the current timer state.
Because the timer is free running and has only a divideby-four prescaler, each timer count cannot be tested. The
test reads the timer once every 10 counts (40 cycles) and
checks for correct counting. The test tracks t~e counter
until the timer wraps around, triggering the output compare flag in the timer status register. RAM locations $0050
and $0051 are overwritten. Upon return to the user's program, X=40. If the test passed, A=O.

The self-check capability provides the ability to determine if the device is functional. Self-check is performed
using the circuit shown in Figure 5~ Port C pins PCO-PC3
are monitored for the self-check results. After reset, the
following seven tests are performed automatically:
1/0 - Exercise of ports A, B, and C
RAM - Counter test for each RAM byte
ROM - Exclusive OR with odd ones parity result
Timer - Tracks counter register and checks OCF flag
Interrupts - Tests external, timer, SCI and SPI interrupts
SCI - Transmi,ssion test; checks RORF, TORE, TC,
and FE flags
.
.
SPI .;..::,.. Transmission test; checks SPIF, WCOl, and
MOOF flags
Self-check results (using the LEOs as monitors) are
shown in Table 2. The following subroutines are available
to the user and do not require any external hardware.

I

ROM CHECKSUM SUBROUTINE
This subroutine returns with the Z bit cleared if any
error is detected; otherwise, the Z bit is set. The ROM
checksum subroutine is called at location $1 F93 with RAM
location $0053 equal to $01 and A = O. A short routine is
set up and executed in RAM to compute a checksum of
the entire· ROM pattern. RAM locations $0050 through
$0053 are overwritten. Upon return to the user's program,
X = o. If the test passed, A = O.

TIMER TEST SUBROUTINE
This subroutine returns with the Z bit cleared if any
error is detected; otherwise, the Z bit is set. The timer
test subroutine is called at location $1 FOE. The output

RESETS
The MCU can be reset two ways: by initial power-up
and by the external reset input (RESET). The RESET input
RESET

10k

47~
2N3904

..2.

+5V
10k

RESET

10k
vDD

NC

OSCl

'='"

37

1

iR5
40

-

39

TCAP

10M

MCU

.........!
.....- ---2.
6
7

...2

PA7

OSC2

PA6

PD7

PA5

TCMP

PA4

PD5/SS

PA3

PD4/SCK

~ PA2
10
11

PD3/MOSI

PAl

PD2/MISO

PAO

PD1/TOO
PDO/RDI

12
r--

r--11
14

10k

-~

15

18
19

36

~

32

30

29
28

PCl

PB2

PC2 26
.25
PC3

PB5

PC5

PB6

PC6

PB7

PC7

~qF
4MHz

1 'rlF

(See Notel J

+5V

-4:-

4.7 K

-4:-

2N3904

10k

I

'='"

~

1k

~

27

~'-....

~
23
22
21

VSS

...L2O
.NOTE: The RC Oscillator Option may also be used in this circuit.

Figure 5. Self-Check Circuit Schematic Diagram

MOTOROLA MICROPROCESSOR DATA
3~824

'='"

31

PBl

PC4

I
o

33 ).M

PCO

PB3

+5V

34

PBO

~ PB4

L.-.-.!l

38

lI'q

"

,'-"

+5V

1k
1~

.H

MC68HC05C3

processing to resume. The stacking order is shown in
Figure 6.
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.

Table 2. Self-Check Results

PC3

PC2 PC1

PCO

Remarks

1

0

0

1

Bad I/O

1

0

1

0

Bad RAM

1

0

1

1

Bad Timer

1

1

0

0

Bad SCI

1

1

0

1

Bad ROM

1

1

1

0

Bad SPI

1

1

1

1

Bad Interrupts or IRQ Request

Flashing

NOTE

The current instruction is the one already fetched
and being operated on.
When the current instruction is complete, the processor
checks all pending hardware interrupts. If unmasked (I
bit clear) and if the corresponding interrupt enable bit is
set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction, regardless ofthe I-bit state.
Refer to Figure 7 for the reset and interrupt instruction
processing sequence.

Good Device

All Others

Bad Device, Bad Port C, etc.
o Indicates lED IS on; 1 indicates lED is off.
consists mainly of a Schmitt trigger that senses the RESET line logic level.
POWER-ON RESET (POR)

An internal reset is generated on power-up to allow
the internal clock generator to stabilize. The power-on
reset is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage.
There is a 4064 internal processor clock cycl~) delay
after the oscillator becomes active. If the RESET pin is
low at the end of 40~, the MCU will remain in the
reset condition until RESET goes high.

TIMER INTERRUPT

There are three different timer interrupt flags that cause
a timer interrupt whenever they are set and enabled. The
interrupt flags are in the timer status register (TSR), and
the enable bits are in the timer control register (TCR).
Refer to TIMER for more information.

EXTERNAL INTERRUPT

EXTERNAL RESET INPUT

If the interrupt mask bit (I bit) of the CCR is set, all
interrupts are disabled. Clearing the I bit enables the external interrupt. The external interrupt is internally ~:
chronized and then latched on the falling edge of IRQ.
The action of the external interrupt is identical to the timer
interrupt with the exception that the interrupt request
input at IRQ is latched internally and the service routine
address is specified by the contents of $1 FFA and $1 FFB.
Either a level-sensitive and edge-sensitive trigger, or
an edge-sensitive-only trigger are available as a mask
option. Figure 8 shows both a functional internal diagram
and a mode timing diagram for the interrupt line. The
timing diagram shows two treatments of the interrupt
line to the processor. The first method shows a single
pulse on the interrupt line spaced far enough apart to be

The MCU is reset when a logic zero is applied to the
RESET input for a period of one and one-half machine
cycles (teyel.

INTERRUPTS
The MCU can be interrupted five different ways: the
four maskable hardware interrupts (IRQ, SPI, SCI, and
timer) and the nonmaskable software interrupt instruction (SWI).
Interrupts cause the procesSor to save register contents
on the stack and to set the interrupt mask (I bit) to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal

o

loe,ea,;09 Memo"
Addresses

l·~

U
R
N

1

11 11

1

Condition Code Register

Stack
I

Accumulator
Index Register

01 010

1

PCH
PCl

Unstack

11

Decreasing Memory
Addresses

P

T

NOTE: Since the Stack Pointer decrements during pushes, the PCl is
stacked first, followed by PCH, etc. Pulling from the stack is
in the reverse order.
Figure 6. Interrupt Stacking Order

MOTOROLA MICROPROCESSOR .DATA
3-825

I

MC68HC05C3

serviced. The minimum time between pulses is a function
of the length of the interrupt service. Once a pulse occurs,
the next pulse should not occur until an RTI occurs. This
time (tILlLl is obtained by adding 21 instruction cycles to
the total number of cycles it takes to complete the service
routine (not including the RTI instruction). The second
method shows many interrupt lines "wire-ORed" to form
the interrupts at the processor. If the interrupt line remains low after servicing an interrupt, then the next interrupt is recognized.
NOTE
The internal interrupt latch is cleared in the first part
of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced
as ,soon as the I bit is cleared.

is zero, SWI executes'after the other interrupts. The SWI
operation is similar to the hardware interrupts. The interrupt service routine address is specified by the contents of memory locations $1 FFC and $1 FFD.
SCI INTERRUPTS

An interrupt in the SCI occurs when one of the interrupt
flag bits in the serial communications status register is
set, provided thel bit in the CCR is clear and the enable
bit in the serial communications control register 2 is set.
Software in the serial interrupt service routine must determine the cause and priority of the SCI interrupt by
examining the interrupt flags and status bits in the SCI
status register.
SPI INTERRU~TS

SOFTWARE INTERRUPT (SWI)

I

The SWI. is an executable instruction that is executed
regardless of the state of the I bit in the CCR. If the I bit

An interrupt in the SPI occurs when one of the interrupt
flag bits in the serial peripheral status register is set,
provided the I bit in the CCR is clear and the enable bit

Level-Sensitive Trigger
Mask Option

VDD ...-_ _...,
D

External
Interrupt
Request

QI------I

Interrupt Pin - - - -......---Q.? C
I Bit(CC)

Power-On Reset
External Reset
External Interrupt
Being Serviced (Vector Fetch)
(a) Interrupt Internal Function Diagram

U

iRO~tlUH
I....

Edg&-S8I1IitMI Trigger Condition
The minimum pulse widtl:dtlLlH) is eit.her
125 ns (VO.D=5 VI or 250 ns {VOO=3 VI.
The period tllll should not be less than
the number of tcyc cycles it takeS to execute the interrupt service routine plus 21
!eyc cycles.

tlllL.---.....--l.1IOf1

level-S8IWitIve Trigger CondItIon
If after servicing an interrupt the iFiQ remains low, then the next interrupt is
recognized.

~

IRQn

nm----,

(MCU)

I~

____---,I

____________________________

NormaiJy
Used witt)
Wire-ORad
Connection

r

~

(b) Interrupt Mode Diagram

FigureS. External Interrupt

MOTOROLA MICROPROCESSOR DATA:
3-826

MC68HC05C3

y

Clear IRQ
Request
Latch

I
Load PC from:
SWI:$1 FFC-$1 FFD
IRQ: $lFFA-$1 FFB
Timer: $1 F~8-$1 FF9
SCI: $1 FF6-$1 FF7
SPI: $1 FF4-$1 FF5

Complete
Interrupt
Routine
and Execute
RTI

Figure 7. Reset and Interrupt Processing Flowchart

MOTOROLA MICROPROCESSOR DATA
3-827

MC68HC05C3

in the serial peripheral control register is set. Software
in the serial peripheral interrupt service routine must determine the cause and priority of the SPI interrupt by
examining the interrupt flag bits in the SPI status register.
Stop Oscillator
And All Clocks

lOW-POWER MODES

Clear I Bit

. STOP

I

The STOP instruction places the MCU in its lowest power
consumption mode. In the STOP mode, the internal oscillator is turned off, halting all internal processing including timer, SCI, and SPI operation (refer to Figure 9).
During the STOP mode, the TCR bits are altered to
remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is
cleared. The I bit in the CCR is cleared to enable external
interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the STOP mode only by an
external interrupt or reset.

Yes

SCI during STOP Mode

When the MCU enters the STOP mode, the baud rate
generator stops, halting all SCI activity. If the STOP instruction is executed during a transmitter transfer, that
transfer is halted. If a low input to the IRO pin is used to
exit STOP mode, the transfer resumes. If the SCI receiver
is receiving data and the STOP mode is entered, received
data sampling stops because the baud rate generator
stops, and all subsequent data is lost. For these reasons,
all SCI transfers should be in the idle state when the STOP
instruction is executed.

(1) FetCh Reset Vector or
(2) Service Interrupt
a. Stack
b. Set I Bit
C. Vector to Interrupt
Routine

SPI during Stop Mode

When the MCU enters the STOP mode, the baud rate
generator stops, terminating all master mode SPI operations. If the STOP instruction is executed during an SPI
transfer, that transfer halts until the MCU exits the STOP
mode by a low signal on the IRO pin. If reset is used to
exit the STOP mode, then the SPI control and status bits
are cleared, and the SPI is disabled. If the MCU is in the
slave mode when the STOP instruction is executed, the
slave SPI continues to operate and can still accept data
and clock information in addition to transmitting its own
data back to a master device.
At the end of a possible transmission with a slave SPI
in the STOP mode, no flags are set until a Iowan the IRO
pin wakes up the MCU. Caution should be observed when
operating the SPI as a slave during the STOP mode because the protective circuitry (WCOl, MODF, etc.) is inactive.

Figure 9. STOP Function Flowchart

During the WAIT mode, the I bit in the CCR is cleared
to enable interrupts. All other registers, memory, and
input/output lines remain in their previous state. The timer
may be enabled to allow a periodic exit from the WAIT
mode.
DATA RETENTION MODE

The contents of RAM and CPU registers are retained
at supply voltages as low as 2.0 Vdc. This is called the
data retention mode where the data is held, but the device
is not guaranteed to operate. The MCU should be in RESET
during data retention mode.

WAIT

TIMER

The WAIT instruction places the MCU in a low-power
consumption mode, but the WAIT mode consumes more
power than the STOP mode. All CPU action is suspended,
but the timer, SCI, and SPI remain active (refer to Figure
10). An interrupt from the timer, SCI, or SPI can cause
the MCU to exit the WAIT mode.

The timer consists of a 16-bit, software-programmable
counter driven by a fixed divide-by-four prescaler. This
timer can be used for many purposes, including input
waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from

MOTOROLA MICROPROCESSOR DATA
3-828

MC68HC05C3

Oscillator Active
Timer, SCI, And SPI
Clocks Active
Processor Clocks Stopped

II
(1) Fetch Reset Vector or
(2) Service Interrupt
a. Stack
b. Set I Bit
c. Vector to Interrupt
Routine

Figure 10. WAIT Function Flowchart

several microseconds to many seconds. Refer to Figure
11 for a timer block diagram.
Because the timer has a 16cbit architecture, each specificfunctional segment (capability) is represented by two
registers. These registers contain the high and low byte
of that functional segment. Generally, accessing the low
byte of a specific timer function allows full control of that
function; however, an access of the high byte inhibits
that specific timer fUnction until the low byte is also accessed.

NOTE
The I bit in the CCR should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does
not occur.

COUNTER
The key element in the programmable timer is a 16bit, free-running counter or counter register, preceded by
a prescaler that divides the internal processor clock by
four. Theprescaler gives the timer a resolution of 2.0
microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock. Software can read the counter at any
time without affecting its value.
The double-byte, free-running counter can be read from
either of two locations, $18-$19 (counter register) or
$1A-$1B (counter alternate register). A read from only
the least significant byte (LSB) of the free-running counter
($19, $1 B) receives the count value at the time of the read.
If a read of the free-running counter or counter alternate
register first addresses the most significant byt~ (MSB)

MOTOROLA MICROPROCESSOR DATA
3-829

MC68HC,05C3

Internal Bus
Internal
Processor
Clock

High
Byte

Low
Byte

Low
Byte
16-Bit Free
Running
Counter
Counter
Alternate

$16
$17

I

High
Byte

Low
Byte

$18

$14

$19

$15

$lA
$lB

.-----1 D

Q

~--~~---------------+----~----~~CLK

Output
Level
Reg,

Timer r--..L--r.-L---,,..-.L-.,
Status
Reg.

C

Timer RESET
Control
Reg.
$12

Output Edge
Level
Input
(TCMP) (TCAP)

Figure 11. Timer Block Diagram

($18, $1A), the LSB ($19, $1B) is transferred to a buffer.
This buffer value remains fixed after the first MSB read,
even.if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or
counter alternate register LSB ($19 or $1 B) and, thus,
completes a read sequence of the total counter value. In
reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be
read to complete the sequence.
The counter alternate register differs from the counter
register in one respect: a read of the counter register MSB
can clear the timer overflow flag (TOF). Therefore, thEl
counter alternate register' can be read at any time without
the possibility of missing timer overflow interrupts due
to clearing of the TOF.

The free-running counter is configured to $FFFC during
reset and is always a read-only register. During a poweron reset, the counter is also preset to $FFFCand begins
running after the oscillator start-up delay. Because the
free-running counter is 16 bits preceded by a fixed divideby-four prescaler, the value in the free-running counter
repeats every 262,144 internal bus ClbCk cycles. When the
counter rolls over from $FFFF to $0000, the TOF bilis set.
An interrupt can also be enabled when counter rollover
occurs by setting its interrupt enable bit (TOlE).

OUTPUT COMPARE REGISTER
The 16-bit output compare register is made up of two
8-bit registers at locations $16 (MSB) and $17 (LSB). The

MOTOROLA MiCRQPROCESSOR DATA
3-830

MC68HC05C3

TIMER CONTROL REGISTER (TCR) $12
The TCR isa read/write r.egister containing five control
bits. Three bits control interrupts associated with the timer
status register flags ICF, OCF, and TOF.

output compare register is used fQr several purposes,
such as indicating when a period oftime,has elapsed. All
bits are readable and writable,and are not altered by the
timer hardware or, reset. If the compare function is not
needed, the two bytes of the output compare register can
be .used as storage locations.
The output compare register contents are compared
with the contents of the free-running counter continually,
and if a match is found, the corresponding output compare flag (OCF) bit is set and the corresponding output
level (OLCL) bit is clocked to an output level register. The
output compare register vallJes and the output level bit
should be changed after each successful comparison to
establish a new elapsed timeout. An interrupt can also
accompany a successful output compare provided the
corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare
register containing the MSB ($16), the output compare
function is inhibited until the LSB ($17) is also written.
The user must write both bytes (locations) if the MSB is
written first. A write made only to the LSB ($17) will not
inhibit the compare function. The free-running counter is
updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than tne internal
hardware.
The processor can write to either byte of the output
compare register without affecting the other byte. The
output level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF)
is set or clear.

INPUT CAPTURE REGISTER
Two 8-bit registers, which make up the ,16-bit input
capture register, are read-only and are used to latch the
value of the free-running counter after the corresponding
input capture edge detector senses a defined transition.
The level transition which triggers the counter transf~r is
defined by the corresponding input edge bit (lEDG). Reset
does not affect the contents of the input capture register:
The result obtained by an input capt~re will be one
more than the value of the free-running counter on the
rising edgeof the internal bus clockpreceding the ex~
ternal transition. This delay is required for internal synchronization. Resolution is one count of the free-running
counter, which is four internal bus clock cycles.
'
The free-running counter contents are transferred to
the input capture register on each proper signal transition
regardless of whether the input capture flag (lCF) is set
or clear. The input capture register always contains the
free-running counter value that corresponds to the most
recent input capture.
After a read of the input capture register ($14) MSB,
the counter transfer is inhibited until the LSB ($'15) is also
read. This characteristic causes the time used in the input
capture software routine and its interaction with the main
program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not
inhibit the free-running counter transfer since they occur
on opposite edges of the internal bus clock.

7
I ICIE

6
1 OCIE

3

TOlE

0, , ,I

RESET:

IEDG

OLVL

u

o

ICIE ,-:- Input Capture Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
OCIE - Output Compare Interrupt Enable
1 = Interrupt enabled
0= Interrupt dis~bled
TOlE - Timer Overflow Interrupt Enable
1 = Interrupt enabled
",
0= Interrupt disabled
IEDG - Input Edge
Value of input edge determines which level transition
on TCAP pin will trigger free-running counter transfer
to the input capture register'
1 = Positive edge
0= Negative edge
Reset does not affect te IEDG bit (U = unaffected)~
OLVL - Output Level
, Value of output level is clocked into output level register by the next successful output compare and will
appear on the TCMP pin
1 = High output
0= Low output
Bits 2,3, and 4 ~ Not used
Always read zero

TIMER STATUS REGISTER (TSR) $13
The TSR is a read-only register containing three status
flag bits.
7

I

ICF

RESET:
U

1

OCF

TOF

U

U

'0

ICF - Input Capture ~Iag
1 = Flag set when selectedpolarityedge is sensed by
input capture edge detector
0= Flag cleared when TSR and input capture low register ($15) are accessed
OCF - Output Compare Flag
1 = Flag set when output compare register contents
match the free-running counter contents
0= Flag cleared when TSR and output compare low
register ($17) are accessed
TOF ~'Timer Overflow Flag
1 = Flag set when free-running counter transition from
$FFFF to $0000 occurs
0= Flag cleared when TSR and counter low register
($19) are accessed
Bits 0-4 - Not used
Always read zero

MOTOROLA MICROPROCESSOR DATA
3-831

1

II

MC68HC05C3

SCI TWO-WIRE SYSTEM FEATURES

Accessing the timer status register satisfies the first
condition required to clear status bits. The remaining step
is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow
function and reading the free-running counter at random
times to measure an elapsed time. Without incorporating
the proper precautions into software, the timer overflow
flag could unintentionally be cleared if:
1) The timer status register is read or written when
TOF is set, and
2) The LSB of the free-running counter is read but not
for the purpose of servicing the flag.
The counter alternate register at address $1A and $1B
contains the same value as the free-running counter (at
address $18 and $19); therefore, this alternate register
can be read at any time without affecting the timer overflow flag in the timer status register.

II

• Standard NRZ (mark/space) format
• Advanced error detection method includes noise detection for nOise duration of up to one-sixteenth bit
time
• Full-duplex operation (simultaneous transmit and receive)
• Software programmable for one of 32 different baud
rates
• . Software-selectable word length (eight- or nine-bit
words)
• Separate transmitter and receiver enable bits
• SCI may be. interrupt driven
• Four separate interrupt conditions

SCI RECEIVER FEATURES
., Receiver wake-up function (idle or address bit)
• Idle line detect
• Framing error detect
• Noise detect
• Overrun detect
• Receiver data register full flag

TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the
timer remains active. An interrupt from the timer causes
the processor to exit the WAIT mode.
TIMER DURING STOP MODE
In the STOP mode, the timer stops counting and holds
the last count value if STOP is exited by an interrupt. If
RESET is used, the counter is forced to $FFFC. Ouring
STOP, if at least one valid inputcapture edge occurs at
the TCAP pin, the input capture detect cir.cuit is armed.
This does not set any timer flags nor wake up the MCU,
but when the MCU does wake up, there is .an active input
capture flag and data from the first valid edge that oc~
curred during the STOP mode. If RESET is used to exit
STOP mode, then no input capture flag or data remains,
even if a valid input capture edge occurred.

SCI TRANSMITIER FEATURES
• Transmit data register empty flag
• Transmit complete flag
• Break send
Any SCI two-wire system ,requires receive data in (ROI)
and transmit data out (TOO).

DATA FORMAT
Receive data in (ROI) or transmit data out (TOO) is the
serial data presented between the internal data bus and
the output pin (TOO) and between the input pin (RDI) and
the interna'i data bus. Data format is as shown for the
NRZ inFigure 12.

SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous SCI is provided with a
standard NRZ format and a variety of baud rates. The SCI
transmitter and receiver are functionally independent but
use the same data format and baud rate. The terms baud
and bit rate are used synonymously in the following description.

WAKE-UP FEATURE
In a typical multiprocessor configuration, the software
protocol will usually identify the addressee(s) at the be~
ginning of the message. To permit uniriterested MPUs to
ignore the remainder of the message, 'a wake-up feature
is included, whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until its data line
returns to the idle state. An SCI receiver is re-enabled by
Control bit "M"

Selects 8 or 9 bit data

o
Idle line

2

3

4

5

6

S

a

• Stop bit is always high,

7

8

0

.I C
S

S

0

a

P

Figure 12. Data Format

MOTOROLA MICROPROCESSOR DATA
3-832

MC68HC05C3

an idle string of at least ten (or eleven) consecutive ones.
Software for the transmitter must provide forthe required
idle string between consecutive messages and prevent
it from occurring within messages.
A second wake-up method is available in which sleeping SCI receivers can be awakened by a logic one in the
high-order bit of a received character.

RECEIVE DATA IN
Receive data in (RDI) is the serial data which is presented from the input pin via the SCI to the receive data
register (RDR). While waiting for a start bit, the receiver
samples the input at a rate 16 times higher than the set
baud rate. This increased rate is referred to as the RT
rate. When the input (idle) line is detected low, it is tested
for three more sample times. If at least two of these three
samples detect a logic low, a valid start bit is assumed
to be detected. If in two or more samples, a logic high is
detected, the line is assumed to be idle. The receive clock
generator is controlled by the baud rate register (see Figure 13); however, the SCI is synchronized by the start bit
independent of the transmitter. Once a valid start bit is
detected, the start bit, each data bit, and the stop bit are
each sampled three times. The value of the bit is determined by voting logic, which takes the value of a majority
of samples. A noise flag is set when all three samples on
a valid start bit, data bit, or stop bit do not agree. A noise
flag is also set when the start verification samples do not
agree.
START BIT DETECTION FOLLOWING A FRAMING ERROR
If there has been a framing error (FE) without detection
of a break (10 zeros for 8-bit format or 11 zeros for a 9bit format), the circuit continues to operate as if there
actually were a stop bit, and the start edge will be placed
artificially. The last bit received in the data shift register
is inverted to a logic one, and the three logic-one start
qualifiers are forced into the sample shift register during
the interval when detection of a start bit is anticipated;
therefore, the start bit will be accepted no sooner than it
is anticipated.
If the receiver detects that a break (RDRF=1, FE=1,
receiver data register = $00) produced the framing error,
the start bit will not be artificially induced, and the receiver must actually receive a logic one before start.
TRANSMIT DATA OUT
Transmit data out (TDO) is the serial data presented
from the transmit data register (TDR) via the SCI to the
output pin. The transmitter generates a bit time by using
a derivative of the RT clock, producing a transmission
rate equal to one-sixteenth that of the receiver sample
clock.
FUNCTIONAL DESCRIPTION
A block diagram of the SCI is shown in Figure 13. The
user has option bits in the serial communications control
register 1 (SCCR1) to determine the SCI wake-up method
and data word length. Serial communications control
register 2 (SCCR2) provides control bits that individually
enable/disable the transmitter or receiver, enable system

interrupts, and provide wake-up enable, and send break
code bits. The baud rate registe'r bits allow the user to
select different baud rates, which are used as the rate
control for the transmitter and receiver.
Data transmission is initiated by a write to the serial
communications data register (SCDAT). Provided the
transmitter is enabled, data stored in the SCDAT is transferred to the transmit data shift register. This data transfer
sets the SCI status register (SCSR) transmit data register
empty (TDRE) bit and generates an interrupt if the transmit interrupt is enabled. Data transfer to the transmit data
shift register is synchronized with the bit rate clc;>ck. All
data is transmitted LSB first. Upon completion of data
transmission, the transmission complete (TC) bit is set
(provided no pending data, preamble, or break code is
sent). and an interrupt is generated if the transmit complete interrupt is enabled. If the transmitter is disabled,
and the data, preamble, or break code has been sent, the
TC bit will also be set, which will also generate an interrupt if the TCIE bit is set. If the transmitter is disabled in
the middle of a transmission, that character will be completed before the transmitter gives up control of the TDO
pin.
When the SCDAT is read, it contains the last data byte
received, provided that the receiver is enabled. The SCSR
receive data register full (RDRF) bit is set to indicate that
a data byte is transferred from the input serial shift register to the SCDAT, which can cause an interrupt if the
receiver interrupt is enabled. Data transfer from the input
serial shift register to the SCDAT is synchronized by the
receiver bit rate clock. The SCSR overrun (OR), noise flag
(NF). or FE bits are set if data reception errors occur.
An idle line interrupt is generated if the idle line interrupt is enabled and the SCSR IDLE bit (which detects idle
line transmission) is set. This allows a receiver that is not
in the wake-up mode to detect the,end of a message, the
preamble of a new message, or to resynchronize with
the transmitter. A valid character must be received before
the idle line condition for the IDLE bit to be set and for
an idle line interrupt to be generated.

REGISTERS
There are five registers used in the SCI; the internal
configuration of these registers is discussed in the following paragraphs.
Serial Communications Data Register (SCDAT) $11
The SCDAT is a read/write register used to receive and
transmit SCI data.
7

6

I SCD7 I SCD6
RESET:
U

u

5

SCD5

SCD4

SCD3

SCD2

SCD1

SCDO

u

u

u

u

u

u

As shown in Figure 13, SCDAT functions as two separate registers. The transmit data register (TDR) provides
the parallel interface from the internal data bus to the
transmit shift register. The receive data register (RDR)
provides the interface from the receive shift register to
the internal data bus.

MOTOROLA MICROPROCESSOR DATA
3-833

II

MC68HC05C3

Internal
Processor
Clock

NOTE: The Serial Communications Data Register (SCDAT) is controlled by the internal R/W signal. It is the transmit data register whe.n
written and receive data register when read .

.Figure 13.. SCI Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-834

MC68HC05C3

Wake

M

Receiver Wake-Up

0

X

Detection of an idle line allows the next data
byte received to cause the receive data register to fill and produce an RDRF flag.

1

0

Detection of a received one in the eighth
data bit allows an RDRF flag and ~ssociated
error flags.

RIE - Receive Interrupt Enable
1 = SCI interrupt enabled
0. = RORF and OR interrupts disabled
ILlE- Idle Line Interrupt Enaple
1 = SCI interrupt enabled
0. = Idle interrupt di.sabled
TE - Transmit Enable
.1
1 = Transmit shift register output isappHed to the TOO.
line. Depending upon the SCCR1 M bit, a preamble 0110. (M =0.) or 11 (M = 1) consecutive ones is
transmitted.
0. = Transmitter disabled after last byte· is loaded in
the SCOAT and TORE is set. After last byte is
transmitted, TOO. line becomes a high-impedance
line.
RE - Receive Enable
1 = Receiver shift register input is applied to the ROI
line.
a= Receiver disabled and RORF, IDLE, OR, NF, and
FE status bits are inhibited.
RWU ~ Receiver Wake-Up
1 = Places receiver in sleep mode and enables wakeup function
0. = Wake-up function disabled after receiving data
word with MSB set (if WAKE = 1)
Wake-up function also disabled after receiving 10.
(M =0.) or 11 (M= 1) consecutive ones (if WAKE =0)
SBK - Send Break
1 = Transmitter continually sends blocks of zeros (sets
of 10. or .11) until cleared> Upon completion of
break code, transmitter sends one high bit for recognition of vali,d start bit.
o.=Transmitter sends 10. (M=o.) or 11 (M=1) zeros
then reverts to an idle state or continues sending
data. If transmitter is empty and idle, setting and
clearing the SBK bit may queue up to two character times,of break because the first break transfers immediately to the shift register, " and the
secondisqueued into the parallel transmit buffer.

1

1

Detection of a received one in the ninth data
bit allows an RDRF flag and associated error
flags.

Serial Communications Status Register (SCSR) $10

Serial Communications Control Register 1 (SCCR1) $OE
The SCCRl provides control·bitsthat determine word
length and select the wake-up method.
·1

3

I

R8

M

T8

I WAKE I

RESET:

U

U

U

R8 - Receive Data Bit 8
R8 bit provides storage location for the ninth bit in the
receive data byte (if M = 1).
T8 - Transmit Data Bit 8
T8 bit provides storage location for the ninth bit in the
transmit data byte (if M = 1).
M ~ SCI Character Word Length
1 = one start bit, nine data bits, one stbp bit
0. = one start bit, eight data bits, one stop bit
WAKE - Wake-Up Select
Wake bit selects the receiver wake-up method.
1 = Address bit (most significant bit)
0. = Idle line condition
Bits 0-2, and 5 - Not used
Can read either one or zero
The address bit is dependent on both the wake-bit and
the M-bit level. Additionally, the receiver does not use
the wake-up feature unless the RWU control bit in SCCR2
is set.

The SCSR provides inputs to the SCI interrupt logic
circuits. Noise flag and framing error bits. are also contained in the SCSR.

Serial CommunicationsContr,ol Register 2 (SCCR2) $OF
The SCCR2 provides con+rol of individual SCI functions
such as interrupts, transmit/receive enabling, receiver
wake-up, and break code.

7

I TORE I

TC

RDRF

IDLE

OR

NF

FE

RESET:

TIE

TCIE

RIE

ILiE

TE

RE

RWU

TORE - Transmit Data Register (TOR) Empty
1 = TOR contents transferredto the transmit data shift
register
a= TOR still contains data. TORE is cleared by reading
the SCSR (with TORE = 1), followed by a write to
the TOR.
TC - Transmit ~omplete
1 = Indicates end of data frame, preamble, or break
condition has o.ccurred
0. = TC .bit cleared by reading theSCSR (with TC =1 L
followed by a write to. the TOR

SBK

RESET:

o

TIE - Transmit Interrupt Enable
1 = SCI interrupt enabled
0. = TORE interrupt disabled
TCIE - Trap~mit Complete Interrupt Enable
1 = SCI interrupt enabled
0. = TC interrupt disabled

MOTOROLA MICROPROCESSOR :DATA

3-835

II

MC68HC05C3

II

RDRF - Receive Data Register (RDR) Full
1 = Receive data shift register contents transferred to
the RDR
0= Receive data shift register transfer did not occur.
RDRF is cleared by reading the SCSR (with
RDRF = 1) followed by a read of the RDR
IDLE - Idle Line Detect
1 = Indicates receiver has detected an idle line
0= IDLE is cleared by reading the SCSR (with IDLE = 1),
followed by a read of the RDR. Once IDLE is
cleared, IDLE cannot be set until RDlline becomes
active and idle again.
OR - Overrun Error
1 = Indicates receive data shift register data is sent to
a full RDR (RDRF = 1). Data causing the overrun
is lost, and RDR data is not disturbed.
O=OR is cleared by reading the SCSR (with OR=1),
followed by a read of the RDA.
NF - Noise Flag
1 = Indicates noise is present on the receive bits, including the start and stop bits. NF is not set until
RDRF= 1.
O=NF is cleared. by reading the SCSR (with NF=1),
followed by a read of the RDR.
FE - Framing Error .
1 = Indicates stop bit not detected in received data
character. FE is set the same time RDRF is set. If
received byte causes both framing and overrun
errors, processor will only recognize the overrun
error. Further data transfer into the RDR is inhibited until FE is cleared.
0= NF is cleared by reading the SCSR (with FE = 1),
followed by a read of the RDA.
Bit 0 - Not used
Can read either one or zero

Baud Rate Register $00
The baud tate register is used to select the SCI transmitter and receiver baud rate. SCPO and SCPT prescaler
bits are used in conjunction with the SCRO through SCR2
baud rate bits to provide multiple baud rate combinations
for a given crystal frequency. Bits 3, 6, and 7 always read
zero.

I- I

SCPl

SCPO

SCR2

SCRI

SCRO

RESET:

u

u

SCPO - SCI Prescaler Bit 0
SCP1 - SCI Prescaler Bit 1
Two prescaler bits are used to, inc~ease the range of
standard baud rates controlled. by the SCRO-SCR2
bits. Prescaler internal processor clock division versus bit levels are listed in Table 2.
SCRO - SCI Baud Rate Bit 0
SCR1 - SCI Baud Rate Bit 1
SCR2 - SCI Baud Rate Bit 2
Three baud rate bits are used to select the baud rates
of the SCI transmitter and SCI receiver. Baud rates
versus bit levels are listed in Table 3.
Tables 3 and 4 tabulate the divide chain used to obtain
the baud rate clock (transmit clock). The a.ctual divider
chain is controlled by the combined SCPO-SCP1 and SCROSCR2 bits in the baud rate register. All divided frequencies shown in Table 3 represent the final baud rate resulting from the internal processor clock division shown
in the divided-by column only (prescaler division only).
Table 4 lists the prescaler output divided by the action
of the SCI select bits (SCRO-SCR2). For example, assume
that a 9600-Hz baud rate is required with a 2.4576-MHz

Table 3; Prescaler Highest Baud Rate Frequency Output
SCP Bit
1

0

Clock*
Divided By

0
0
1
1

0
1
0
1

1
3
4
13

4.194304
131.072
43.69.1
32.768
10.082

kHz
kHz
kHz
kHz

4.0
125.000 kHz
41.666 kHz
31.250 kHz
9600 Hz

Crystal Frequency MHz
2.4576
76.80
25.60
19.20
5.907

kHz
kHz
kHz
kHz

2.0

1.8432

62.50 kHz
20.833 kHz
15.625 kHz
4800 Hz

57.60 kHz
19.20 kHz
14.40 kHz
4430 Hz

*Refers to the internal processor clock.
NOTE: The divided frequencies shown in Table 3 represent baud rates which are the highest tran~mit baud rate (Tx) that can be
obtained by a specific crystal frequency and only using the prescaler division. Lower baud rates may be obtained by providing
a further division using the SCI rate select bits as shown below for some representative prescaler outputs.

Table 4. Transmit Baud Rate Output for a Given Prescaler Output
2

SCR Bits
1

0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Divided
By
1
2
4
8
16
32
64
128

131.072 kHz
131.072
65.536
32.768
16.384
8.192
4.096
2.048
1.024

kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz

Representative Highest Prescaler Baud Rate Output
19.20 kHz
32.768 kHz
76.80 kHz
32.768 kHz
16.384 kHz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz

76.80 kHz
38.40 kHz
19.20 kHz
9600 Hz
4800 Hz
2400 Hz
1200 Hz
600 Hz

19.20 kHz
9600 Hz
4800 Hz
2400 Hz
1200 Hz
600 Hz
300 Hz
150 Hz

9600 Hz
9600
4800
2400
1200
600
300
150
75

Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz

NOTE: Table 4 illustrates how the SCI select bits can be used to provide lower transmitter baud rates by further dividing the prescaler
output frequency. The five examples are only representative samples. In all cases, the baud rates shown are transmit baud
rates (transmit clock), and the receive clock is 16 times higher in frequency than the actual baud rate.

MOTOROLA MICROPROCESSOR DATA

3-836

MC68HC05C3

device. The MOSI line is one of two lines that transfer
serial data in one direction with the most significant bit
sent first.

external crystal. In this case, the prescaler bits (SCPOSCP1) could be configured as a divide-by-one or a divideby-four. If a divide-by-four prescaler is used, then the
SCRO-SCR2 bits must be configured as a divide-by-two.
Using the same crystal, the 9600 baud rate can be obtained with a prescaler divide-by-one and the SCRO-SCR2
bits configured for a divide-by-eight.

SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) is an interface built
into the MCU which allows several MCUs or MCUs plus
peripherals to be interconnected within the same black
box. In the SPI format, the clock is not included in the
data stream and must be furnished as a separate signal.
An SPI system may consist of one master MCU and several slaves (Figure 14) or MCUs that can be either masters
or slaves.
Features:
•
•
•
•
•
•
•
•
•

Full-duplex, three-wire synchronous transfers
Master or slave operation
1.05 MHz (maximum) master bit frequency
2.1 MHz (maximum) slave bit frequency
Four programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Write collision flag protection
Master-master mode fault protection capability

Master In, Slave Out
The master in, slave out (MISO) line is configured as
an input in a master device and as an output in a slave
device. The MISO is one of two lines that transfer serial
data in one direction with the most significant bit sent
first. The MISO line of a slave device is placed in a highimpedance state if slave is not selected (SS = 1).
Serial Clock
The serial clock (SCK) is used to synchronize both data
in and out of a device via the MOSI and MISO lines. The
master and slave devices can exchange a byte of information during a sequence of eight clock cycles. Since.
SCK is generated by the master device, this line becomes
an input on a slave device.
As shown in Figure 15, four possible timing relationships may be chosen by using control bits CPOL and
CPHA in the serial peripheral control register (SPCR). Both
master and slave devices must operate with the same
timing.
Two bits (SPRO and SPR1) in the SPCR of the master
device select the clock rate. In a slave device, SPRO and
SPR1 have no effect on SPI operation.
Slave Select
The slave select (SS) input line selects a slave device.
The SS line must be low prior to data transactions and
must stay low for the duration of the transaction. The SS
line on the master must be tied high; if the SS line goes
low, a mode fault error flag (MODF) is set in the serial
_
peripheral status register (SPSR).
When CPHA = 0, the shift clock is the OR of SS with
SCK. In this clock phase mode, SS must go high between
successive characters in an SPI message. When CPHA= 1,
SS must go high between successive characters in an

SIGNAL DESCRIPTION

The four basic signals (MOSI, MISO, SCK, and SS) are
described in the foll9win9 paragraphs. Each signal function is described for both master and slave mode.
Master Out, Slave In
The master out, slave in (MOSI) line is configured as
an output in a master device and as an input in a slave
MISO
MOSI
SCK

M6805 HCMOS Slave 0

SC~

MISO
MOSI

55 I---Voo

"--

SS

M6805 HCMOS
Master

r--(I,
P

0
R
T

1
2
3 t--

r

I I It
MOSI
SS
MISO SCK

M680S' HCMOS Slave 3

II

I

II 1

MOSI
SS
MISO
SCK

M680S HCMOS Slave 2

MOSI
SS
MISO SCK
M680S HCMOS Slave 1

Figure 14. Master-Slave System Configuration

MOTOROLA MICROPROCESSOR DATA
3-837

I

II

MC68HC05C3

SCK (CPOL = 0)

SCK (CPOL = 1)

Sample Input
Data out (CPHA=l)
Sample Input
Data out (CHPA = 0)

Figure 1.5. Data Clock Timing Diagram

II

SPI message. When CPHA =1, SS may be left low for
several SPI characters. In cases where there is only one
SPI slave MCU, the slave MCU SSline could be tied to
VSS as long as CPHA= 1 clock modes are used.

FUNCTIONAL DESCRIPTION
Ablock diagram of the SPI is shown in Figure 16. In a
master configuration, the CPU sends a signal to the master start logic, which originates an SPI clock (SCK) based
on the internal processor clock. As a master device, data
is parallel loaded into the 8-bit shift register from the
internal bus during a write cycle and then serially shifted
viatheMOSI pin to the slave devices. During a read cycle i
data is applied serially from a slave device viathe MISO
pin to the 8"bit shift register. Data is then parallel transferred to the read buffer and made available to the internal data bus during a CPU read cycle.
'Internal

SCK (PD4)

Processor

In a slave configuration, the slaVe start logic receives
a logic low at the SS pin and a clock input at the SCK
pin. This synchronizes the slave with the master. Data
from the master is received serially at the slave MOSI pin
and shifted into the 8-bit shift register for a parallel transfer to the read buffer. During a write cycle, data is parallel
loaded into the 8-bit shift register from the internal data
bus, awaiting the clocks from the master to shift out serially to the MISO pin and then to the master device.
Figure 17 illustrates the MOSI, MISO, SCK, and SS
master-slave interconnections.
.

REGISTERS
There are three registers in the SPI that provide control,
status, and data storage functions. These registers, the
serial peripheral control register (SPCRl, serial peripheral
status register (SPSR), and serial peripheral data 1/0 register (SPDR), are described in the following paragraphs.

MISO (PD2)

Clock
Read
Internal
Data
Bus

55 (PD5)

SPCR

SOA L--_.,..-_.....

Figure 16. SPI Block Diagram

MOTOROLA MICROPROCESSOR DATA
3~838

MC68HC05C3

I
MISOI

I MISO

a-Bit Shift Register

I
I MOSI

MOSI

I
I
I
I SCK

SCKI

I
SSI

I

ISS
I

I

oV ----,---,

+5V

Figure 17. SPI Master-Slave Interconnections
Serial Peripheral Status Register SOB

Serial Peripheral Control Register $OA

The SPSR contains three status bits.

The SPCR provides control of individual SPI functions
such as interrupt and system enabling/disabling, master/
slave mode select, and clock polarity/phase/rate select.
76543210

i SPIE I SPE

I MSTR I CPOl I CPHA I SPRl
u

u

SPIE - Serial Peripheral Interrupt Enable
1 = SPI interrupt enabled
0= SPI interrupt disabled
SPE - Serial Peripheral System Enable
1 = SPI system on
0= SPI system off
MSTR - Master Mode Select
1 = Master mode
0= Slave mode
CPOl - Clock Polarity
Clock polarity bit controls the clock value and is used
in conjunction with the clock phase (CPHA) bit.
1 = SCK line idles high
O=SCK line idles in low state
CPHA - Clock Phase
Clock phase bit along with CPOl controls the clockdata relationship between the master and slave devices.QOl selects one of two clocking protocols.
1 = SS is an output enable control.
0= Shift clock is the OR of SCK with SS.
When SS is low, first edge of SCK invokes first
data sample.
SPRO, SPRl - SPI Clock Rate Bits
Two clock rate bits are used to select one of four clock
rates to be used as SCK in the master mode. In the
slave mode, the two clock rate bits have no effect. Clock
rate selection is shown in the following table.
Bit 5 - Not used
Can read either one or zero
SPI Clock Rate Selection
Internal Processor
Clock Divided By

SPR1

SPRO

0
0

0
1

4

1
1

0

16
32

1

2

IWCOl I

5

4

3

2

I MODF I

RESET:

a

SPRO

RESET:

a

6

SPIF

SPIF -

Serial Peripheral Data Transfer Flag
1 = Indicates data transfer completed between processor and external device.
(If SPIF = 1 and SPIE = 1, SPI interrupt is enabled.)
0= Clearing is accomplished by reading SPSR (with
SPIF = 1) followed by SPDR access.
WCOl - Write Collision
1 = Indicates an attempt is made to write to SPDR
while data transfer is in process.
0= Clearing is accomplished by reading SPSR(with
WCOL= 1)' followed· by SPDR access.
MODF- Mode Fault Flag
1= Indicates multi-master system control conflict.
0= Clearing is accomplished by reading SPSR (with
MODF = 1), followed by a write to the SPCR.
Bits 0-3, and 5 - Not used
Can read either zero or one
Serial Peripheral Data 1/0 Register SOC
The SPDR is a read/write register used to receive and
transmit SPI data.
7

6

I SPD7 I SPD6
RESET:
U

5
SPD5

U

2.
SPD4

SPD3

UU

SPD2

SPDl

SPDO

U

U

U

A write to the SPDR places data directly into the shift
register for transmission. Only a write to this register will
initiate transmission/reception of another byte and will
only occur in the master device. On completion of byte
transmission, the SPIF status bit is set in both master and
slave devices.
A read to the SPDR causes the buffer to be read. The
first SPIF status bit must be cleared by the time a second
data transfer from the shift register to the read buffer
begins, or an overrun condition will exist. In overrun cases,
the byte causing the overrun is lost.

MOTOROLA MICROPROCESSOR DATA
3-839

II

MC68HC05C3

READ-MODIFY-WRITE INSTRUCTIONS

INSTRUCTION SET
The MCU has a set of 62 basic instructions. They can
be divided into five different types: register/memory, readmodify-write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type.
This MCU uses all the instructions available in the
M146805 CMOS Family plus one more: the unsigned
multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator
.!A) and the index register (X). The high-order product is
then stored in the index register, and the low-order product is stored in the accumulator. A detailed definition of
the MUL instruction is shown below.

II

These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.
Function

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Complement

COM
NEG

Operation

X:A X*A

Negate (Twos Complement)

Description

Multiplies the eight bits in the index register
by the .eight bits in the accumulator to obtain
a 16-bit unsigned number in the concatenated
accumulator and index register

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Condition
Codes

H: Cleared
I: Not affected
N: Not affected
Z: Not affected
C: Cleared

Source

MUL

Formls)

Addressing
Mode
Inherent

I
Cycles
11

I

Bytes
1

I Opcode
$42

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

MUltiply

MUL

BRANCH INSTRUCTIONS

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the accumulator orthe index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following instruction list.
Function

Logical Shift Left

This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two-byte instructions. Refer to the following list for branch instructions.

Mnemonic

Function

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

LDA

Branch if Lower or Same

BLS

Load X from Memory

LDX

Branch if Carry Clear

BCC

Store A in Memory

STA

Branch if Higher"or Same

BHS
BCS

Load A from Memory

Store X in Memory

STX

Branch if Carry Set

Add Memory to A

ADD

Branch if Lower

BLO

Add Memory and Carry to A

ADC

Branch if Not Equal

BNE

Subtract Memory

SUB

Branch if Equal

Subtract Memory from A with Borrow

SBC

Branch if Half Carry Clear

BHCC

AND Memory to A

AND

Branch if Half Carry Set

BHCS

OR Memory with A

ORA

Branch if Plus

BPL

Exclusive OR Memory with A

EOR

Branch if Minus

BMI

Arithmetic Compare A with Memory

CMP

Branch if Interrupt Mask Bit is Clear

BMC

Arithmetic Compare X with Memory

CPX

Branch if Interrupt Mask Bit is Set

BMS

Bit Test Memory. with A ILogical Compare)

BIT

Branch if Interrupt Line is Low

BIL

Jump Unconditi'onal

JMP

Branch if Interrupt Line is High

BIH

Jump to Subroutine

JSR

Branch to Subroutine

BSR

MOTOROLA MICROPROCESSOR DATA
3-840

BEQ

MC68HC05C3

BRANCH INSTRUCTIONS

BIT MANIPULATION INSTRUCTIONS

This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two-byte instructions. Refer to the following list for branch instructions.

The MCU is capable of setting or clearing any writable
bit which resides in the first 256 bytes of the memory
space where all port registers, port DDRs, timer, timer
control, ROM, and on-chip RAM reside. An additional
feature allows the software to test and branch on the state
of any bit within these 256 locations. The bit set, bit clear
and bit test, and branch functions are all implemented
with a single instruction. For test and branch instructions,
the value of the bit tested is also placed in the carry bit
of the condition code register. Refer to the following list
for bit manipulation instructions.

Function

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

Branch if Carry Clear

BCC

Branch if Higher or Same

BHS

Mnemonic

Function

Branch if Bit n is Set

BRSET n (n=O ... 7)

Branch if Carry Set

BCS

Branch if Bit n is Clear

BRCLR n (n =0 ... 7)

Branch if Lower

BLO

Set Bit n

BSET n (n=O ... 7)

Branch if Not Equal

BNE

Clear Bit n

BCLR n (n=O ... 7)

Branch if Equal

BEQ

Branch if Half Carry Clear

BHCC

Branch if Half Carry Set

BHCS

Branch if Plus

BPL

Branch if Minus

BMI

Branch if Interrupt Mask Bit is Clear

BMC

Branch if Interrupt Mask Bit is Set

BMS

Branch if Interrupt Line is Low

BIL

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

OPCODE MAP SUMMARY

Table 5 is an opcode map for the instructions used on
the MCU.

ADDRESSING MODES

CONTROL INSTRUCTIONS

These instructions are reg ister reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.
Function

Mnemonic

The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte
instructions; the longest instructions (three bytes) permit
accessing tables throughout memory. Short and long absolute addressing is also included. One- or two-byte direct addressing instructions access all data bytes in most
applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

CLC

IMMEDIATE

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

CLI

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

Reset Stack Pointer

RSP

No-Operation

NOP

Stop

STOP

Wait

WAIT

DIRECT

In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.

MOTOROLA MICROPROCESSOR DATA
3-841

II

•

Table 5. Opcode Map

Branch
REL

Bit Manipulation
BTB
Bse
'~

rk
0001

3BACL:TOe

2
0010

3
0011

5

d

::g

3BRSEJT1:
.5

3BACL:T18

(;

::g

o

2 BSE1~c

5

2 BCL~~c

5

0100

01~1

BAeL
3

:l:

2 BCL~~c

7

s:

5

2 BSE1~c

O~O

5:

BSE1~;

2 BCL~~c

rSEJ1B

4

o

2

5

5
5

L1RSE~?A 2 BSE1~c
"

-'

5

~BCL~%c
:ls. .',
5

BACL

0111

L3.

1~

13BASH4' 2 BSE1~c
BTB

9

3BACL:~ 2 BCL~~c

~ o"::g

1001

m

1011

5

5
5

It,O

B

C')

en
en

1~

o

::g

lPol

c

E

~

1110

F
1111

~1

o~

BRA '3
2
AEL

2 NEG ,:
o

NEGA

BRSE
13
Ji:

2 BSE1~c

5

5

BAClR5
BTB
3

2 BCl~~c

13BASEJ~:_ ..2..BSE1~~
5
13BRCL:~: 2 BCL~~c
5

3BRSH7
BTB
5

BRCLR7
3
BTB

5

2 BSE1~c

3

2 BHIAEL
3
2 BlS
A
3
2 BCC ,
AE
3
2 BCS
A
3
2 BNEA
3.
..2.. BEQI!El.
3
2 BHCC
AE'
3
BHC
..2..
3
2 BPl
AEI
3
BMI
2
AEL
3
..2.. BM~EL
3
2 BM~E'
3
Bil
2
A

k

BIH
2

3

INH

NEGX
1

3

lNH

01~0

IX

6

NEG·
2
,X,

01~1

,

NEG

5

,X

3

2 BR~

5

BClR7
2
BSC

1

0~1

3

AEL

INH
8

INH

IMM

9

A

DIR
B

1000

1001

1010

1011

,

RTI

,

RTS
'NH

"
'NH
6

II

,
.5

2

CO~,)'A
5

2 'LS~TA

1

OIA

1

5

2
2..

LSl

D'A

1

5

RO~IA

INC
2

1

2

1

1

4

D!A

1

5

CLR
2_ _
D'A

3
ASRA
'NH
3
LSLA
'NH
ROlA
'NH
3
DECA
'NH
3

5

D'A
TST

AOR~,H

3

5

2 DEC
O'A

3
LSRA
'NH
3

1

5

2.. ASR

INH

3

5

2 RORO'A

MUL

, COMA'NH

INCA
'NH
3
TSTA
,NH

1
1

1

6

3

, RORX'NH

2 ROR

'Xl
6

3
ASRX
2 ASR
1
'Xl
'NH
3
6
lSlX
2 lSl
'NH
'Xl
3
6
ROlX
2 ROl
1
'NH
'Xl
3
6
DECX
DEC
I
'NH 2
'Xl

,

3

6

, INCX'NH
1

3

CLRA
- 'NH

6
3
COMX
2 COM
'NH
'Xl
3
6
LSRX
LSR
'Xl
'N" 2

INC
2
'X,
3
5
TST
TSTX
iXl
'NH 2
3

1

CLRX
INH

,5

, COM 'X ,
5
, lSR 'X
,

2

IXI

,

'X

1

,
,

5

lSl
'X

5

ROl

,
,
,

'X '
5

DEC
'X

1

,

5

,
,

INC
'X

4

TST
1

'X
5

CLR
1

IX

, STOP'NH2
1

WAIT 2
INH

A

X
IMM
DIR
EXT
REL
BSC
BTB
IX
IX1
IX2

Inherent
Accumulator
Index Register
Immediate
Direct
Extended
Relative
Bit Set/Clear
Bit Test and Branch
Indexed (No Offset I
Indexed, 1 Byte (S-Bitl Offset
Indexed, 2 Byte I16-Bit) Offset

3

SU~X~

SUB,x~

SUB

3

CMP
EXT

3

4

li. BI~M

5

2.. BIT D'A

3 BITE.XT

3 BIT 'X2

2

3

4

5

3

4

3

CMP

4

4

5

'X2

4

SBC
EXT
3

SBC: '
3
'X2

3

IX

lr,1

E

AND

5

,X2

4

2

'Xl

4
2
TAX
STA
,NH
D,A
2
2
2
3
EOR
ClC'N 12 EOR
'MM 2
O'A
2
2
3
SEC
ADC
ADC
D,A
'NH 2
'MM 2
2
ORA]
ORA
Cli
'NH 2
'MM 2
O'A
ADD]
SEI 1
ADD
O,A
'NH 2
'MM 2
2
2
RSP
JMP
2
'NH
D'A
2
6
NOP
BSR
JSR '
O,A
AEL 2
'NH 2

lOX 2
IMM

2

TXA
INH

STA 5
3
EXT

2

4

SBC
'Xl
'Xl

2

3
3

ADC
EXT

'Xl

4

2 BIT 'x

3 EOR

IX2

ORA'
EXT
3

3

ADD
EXT

5

3

'X2
ADD'

3

'X2

4

3

IX2

ORA

4

JMP 3
JMP
ExT 3
'X2
JSR b
JSR
EXT 3
3
'X2
lOX 4
lOX 3
lOX 5
2
D,A 3
EXT 3
,x2
STX 4
STX 5
STX 6
D,A 3
EXT 3
IX2
2
3

,
1

'Xl

rk

SBC ]
'X

2

CPX '
IX
3
AND
'X
3
BIT 'x
3
LOA
'X

1

EOR
1

4

'Xl
ORA'
'Xl
2
ADD 4
2
'Xl
JMP 3
2
'Xl
JSR b
'Xl
2

1
1

1

1

1

4

2

lOX
STX

2

'Xl

1

5

'Xl

,

0001
0010

3
0011

4
0100

01~1
6
0110

4

STA

ADC
2

H~

SUB]
,X
3
CMP
,X

4

5

ADC

1

4

2 EOR

4

1

4

AND

STA '
2
'Xl

5

1

4

CPX
2

,x, ,

STA ~
3
'X2

4

EOR
EXT

1

4

CMP
2

lD~MM 2 LOAO'A 3 LOAEXT 3 LOA 'X2 2 LOA 'Xl

AbbreYie1iona for Add,.. Modes
INH

1110

0

AND
3
,EXT

2

1

1101

CPX '
3
'X2

12

5

IXl

lfoo

CPX
EXT
3

5

ASR

EX'

SUB 2
12
'MM 2 SUBo,:
3
2
CMP
CMP
O,A
IMM
2
2
2
3
SBC
SBC
2
'MM 2
D'A
3
2
CPX
CPX
2
'MM 2
D'A
2
AND 3
AND
2
'MM 2
D'"
2

ROR

6

CLR

'0

SWI
'NH

'X

,

~iater/Mernory

Control

R8IId/Modify/Wiite
INH
IX'

INH

rito

5

5

s:
o

~1

5

BRSE
3
JfB

,

w

~

DIA

1

,X

7
0111

s:

3
'X
ADC ]
'X
ORA'
'X
ADD]
'X
JMP 2
'X
JSR '
'X
lOX 3
'X
STX •
'X

8

n
en

1000

9

CO

1001

:::t:

n

A
1010

C)

U1

n

B
1011

Co\)

C
1100

0
1101

E
11-10

F
1111

I

LEGEND

F
Mnemonic
Bytes

~.
1

Cycles-------'

Opcode in Hexadecimal

II(

~

l

J~X~

~

Opcode in Binary

0000 c::

' - - - - - - - - - - Address Mode

MC68HC05C3

EXTENDED

INDEXED, 1.6·8IT OFFSET

In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with e~tended addressing
mode are capable of referencing arguments anywhere in
memory withasingle three-byte instruction. When using
the Motorola assembier, the user need not specify whether
an instruction uses direct or extended addressing. The
assembler automatically selects the shortest form of the
instruction.

In the indexed, 16-bit offset addressing mode, the effective address is the sum ofthe contentsofthe unsigned'
8-bit index register and the two unsigned bytes following
the opcode. This address mode can be used in a manner
similar to indexed, 8-bit offset except that this three-byte
instruction allows tables to be anywhere in memory. As
with direct and extended addressing, the Motorola assembler determines the shortest forr;n of indexed ,addressing.

RELATIVE

BIT SET/CLEAR

The relative addressing mo.de ,is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from -126 to + 129 from
the opcode address. The programmer need not calculate
the offset when using the Motorola assembler, since it
calculates the proper offset and checks to see that it is
within the span of the branch.

In the bit set/clear addressing mode, the bit to be set
,or cleared is part of the opcode, and the byte following
the opcode specifies the direct addressing of the byte in
which ,the specified bit is to be set or cleared. Any read/
write bit in the first 256 locations of memory, including
110, can be selectively set or cleared with a single twobyte instruction.

INDEXED, NO OFFSET

In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or to hold the address of a frequently referenced
RAM or I/O location.
INDEXED, S-BIT OFFSET

In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents oft,he unsigned
8-bit index register and the unsig'ned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K woulq typically be in X with the address of
the beginning, of the table i,n the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1 FE is the last location at which the instruction may
begin).

BIT TEST AND BRANCH

The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition (set or clear), is
included in the opcode. The address of the byte to be
tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third
byte is added to the PC if the specified bit is set or cleared
in the specified memory location. This single three-byte
instruction allows the program to branch based on the
condition of any readable bit in the first 256 locations of
memory. The span of branching is from-125 to + 130,
from the opcode address, The state of the tested bit is
also transferred to the carry bit of the condition code
register.
INHERENT

In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this mode. These instructions are one byte long.

MOTOROLA MICROPROCESSOR DATA
3-843

I

MC68HC05C3

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS (Voltages referenced to Vss)
Symbol

Value

Unit

$upply Voltage

Rating

VDD

-0.3 to + 7.0

V

Input Voltage

Vin

VSS -0.3 to
VDD +0.3

V

Self-Check Mode (IRQ Pin Only)

Vin

VSS-0.3 to
2xVDD+0.3

V

Current Drain Per Pin Excluding
VDD and VSS

I

25

mA

TA

TL to TH
Oto + 70
-40 to +85
-40 to + 105
-40 to + 125

'C

Tstg

-65to + 150

C

Characteristic

Symbol

Value

Thermal Resistance
Plastic
Plastic Leaded Chip Carrier (PLCC)

tlJA

Operating Temperature Range
MC68HC05C3P, FN
MC68HC05C3CP, CFN
MC68HC05C3VP, VFN .
MC68HC05C3MP, MFN
Storage Temperature Range

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it 'is advised that normal precautions be taken to avoid application of
any voltage higher than maximum-rated voltages
to this high-impedance circuit. For proper operation, it is recommended that Vin and Vout be
constrained to the range VSS "" (Vin or Vout) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic
voltage level (e.g., either VSS or VDD).

THERMAL CHARACTERISTICS
Unit
'CW
60
7Q

POWER CONSIDERATIONS
The average chip-junction temperature, TJ' in °c can
be obtained from:
TJ =TA + (PD· IlJA)
(1)
where:
= Ambient Temperature, °c
TA
= Package Thermal Resistance,
6JA
Junction-to-Ambient, °C/W
PD
= PINT+PIIO
= ICCxVCC' Watts - Chip Internal Power
PINT
= Power Dissipation on Input and Output
PliO
Pins - User Determined

For most applications PI10ut Low Voltage (see Figure 21)
(ILoad=1.6 mAl PAD-PA7, PBO-PB7, PCO-PC7, P01-P04, TCMP

VOL

-

-

0.4

V

Input High Voltage
PAD-PA7, PBO-PB7, PCO-PC7, POO-P05, P07, TCAP, IRQ,
RESET,OSCl

VIH

0.7 xVOO

-

VOO

V

Input Low Voltage
PAD-PA7, PBO-PB7, PCO-PC7, POO-P05, P07, TCAP, IRQ,
RESET,OSCl

VIL

VSS

-

0.2 xVOO

V

VRM

2.0

-

-

-

3.5
1.6

7.0
4.0

mA
mA

-

2.0

-

50
140
180
250

riA
fl-A
fl-A
fl-A

Oata Retention Mode (0° to 70 u C)

V

-

.

V

Supply Current (see Notes)
Run (see Figures 22 and 23)
Wait (see Figures 22 and 23)
Stop (see Figure 23)
25"C
o to 70 u C (Standard)
'- 40" to + 85°C
- 40" to + 125°C

100

I 0 Ports Hi-Z Leakage Current
PAD-PA7, PBO-PB7, PCO-PC7, P01-P04

IlL

-

-

±10

fl-A

In~Current

lin

-

-

±1

fl-A

Cout
Cin

-

-

12
8

RESE~IRQ,TCA~OSC1, PO~PO~

-

P07

Capacitance
Ports (a~ut or Output)
RESET, IRQ, TCAP, POO-P05, P07

pF

NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only.
3. Wait 100: Only timer system active (SPE == TE = RE = 0). If SPI, SCI active (SPE =' TE = RE = 1) addl 0% current draw.
4. Run (Operating) 100, Wait 100: Measured using external square wave clock source (fos c =4.2MHz), all inputs 0.2 V from rail;
no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
5. Wait, Stop 100: All ports configured as inputs, VIL = 0.2 V, VIH '= VOO - 0.2 V.
6. Stop 100 measured with OSCl = VSS.
7. Standard temperature range is 0° to 70°C. Extended temperature versions and a 25°C only version are available,
8. Wait 100 is affected linearly by the OSC2 capacitance.

MOTOROLA MICROPROCESSOR DATA
3-845

II

MC68HC05C3

DC ELECTRICAL CHARACTERISTICS
(VOO = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted)
\

Characteristic

Symbol

Output Voltage, ILoad""lO.O I1A

VOL
VOH

..

Min

Max

Unit

-

-

0.1

V

VOD - 0.1

-

-

VOO-0.3
VOD-0.3

-

-

Output High Voltage
(lLoad= 0.2 mAl PAD-PA7, PBO-PB7, PCO-PC7, TCMP (see Figure 19)
(lLoad = 0.4 mAl P01-P04 (see Figure 20)

VOH

Output Low Voltage (see Figure 21)
(ILoad = 0.4 mAl PAD-PA7, PBO-PB7, PCO-PC7, P01-P04, TCMP

VOL

Input High Voltage
PAD-PA7, PBO-PB7, PCO-PC7, POO-P05, P07, TCAP, IRQ,
RESET, OSCl

VIH

0.7 x VOO

Input Low Voltage
PAD-PA7, PBO-PB7, PCO-PC7, POO-P05, P07, TCAP, IRQ,
RESET, OSCl

VIL

Data Retention Mode (0° to 70°C)

VRM

Supply Current (see Notes)
Run (see Figures 22 and 24)
Wait (see Figures 22 and 24)
Stop (see Figure 24)
25°C
0° to 70°C (Standard)
- 40° to + 85°C
- 40° to + 125°C

100

1/0 Ports Hi-Z Leakage Current
PAD-PA7, PBO-PB7, PCO-PC7, P01-P04
Input Current
RESET, IRQ, TCAP, OSC1, POO, P05, P07
Capacitance
Ports (a §...!!!putor Output)
RESET, IRQ, TCAP, POO-P05, P07

Typ

V

-

-

--

0.3

V

-

VOO

V

VSS

-

0.2 x VOO

V

2.0

-

-

V

-

1.0
0.5

2.5
1.4

mA
mA

-

1.0

I1A
I1A
I1A
I1A

-

-

-

30
80
120
175

IlL

-

-

:2:10

I1A

lin

-

-

:2:1

I1A

Cout
Cin

-

-

-

-

12,
8

-

pF

NOTES:
1. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only.
3. Wait 100: Only timer system active (SPE = TE = RE = 0). If SPI, SCI active (SPE = TE = RE = 1) add 10% current draw.
4. Run (Operating) 100, Wait 100: Measured using external square wave clock source, (fos c =4.2 MHz)' all inputs 0.2 V from rail;
no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
5. Wait, Stop 100: All ports configured as inputs, VIL = 0..2 V, VIH = VOO - 0.2 V.
6. Stop 100 measured with OSCl = VSS.
7. Standard temperature range is 0°, to 70°C. Extended temperature versions and a 25°C"only version are available.
8. Wait 100 is affected linearly by the OSC2 capacitance.

MOTOROLA MICROPROCESSOR 'DATA

3-846

MC68HC05C3

5.0

4.0



Internal
Data
Bus*

~

RESET

r-

1

tRL

---1

-J!

***
* Internal timing signal and bus information not available externally
* *OSC1 line is not meant to represent frequency. It is only used to represent time
* * *The next rising edge of the internal processor clock following the rising edge of RESET Initiates the reset sequence

Figure 28. Power-On Reset and RESET

MC68HC05C3

ORDERING INFORMATION
The following information is required when ordering a
custom MCU. The information may be transmitted to Motorola in the following media:
MDOS@), disk file
MS@J-DOS/PC-DOS disk file (360K)
EPROM(s) 2764, MCM68764, MCM68766, or EEPROM
MC68HC805C4
To initiate a ROM pattern for the MCU, it is necessary
to first contact the local field service office, a sales person,
or a Motorola representative.

$0020

xxx = Customer ID

Verification Media
FLEXIBLE DISKS

A flexible disk (MS-DOS/PC-DOS disk file), programmed with the customer's program (positive logic
sense for address and data), may be submitted for pattern
generation. The diskette should be clearly labeled with
the customer's name, data, project or product name, and
the name of the file containing the pattern.
In addition to the program pattern, a file containing the
program source code listing can be included. This data
will be kept confidential and used to expedite the process
in case of any difficulty with the pattern file.

All original pattern media (EPROMs or floppy disks) are
filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and
returned along with a listing verification form. The listing
should be thoroughly checked, and the verification form
should be completed, signed, and returned to Motorola.
The signed verification form constitutes the contractual
agreement for the creation of the customer mask. To aid
in the verification process, Motorola will program customer supplied blank EPROM(s) or DOS disks from the
data file used to create the custom mask.

MS-DOS/PC-DOS Disk File

ROM VERIFICATION UNITS (RVUs)

MS-DOS is Microsoft's Disk Operating System. PC-DOS
is the IBM® Personal Computer (PC) Disk Operating System. Disk media submitted must be a standard density
(360K) double-sided 51/4 inch compatible floppy diskette.
The diskette must contain object file code in Motorola's
S-record format. The S-record format is a character-based
object file format generated by M6805 cross assemblers
and linkers on IBM PC style machines.

Ten MCUs containing the customer's ROM pattern will
be sent for program verification. These units will have
been made using the custom mask, but are for the purpose of ROM verification only. For expediency, the MCUs
are unmarked, packaged in ceramic, and tested with five
volts at room temperature. These RVUs are free with the
minimum order quantity, but are not production parts.
RVUs are not backed or guaranteed by Motorola Quality
Assurance.

EPROMs

A 2764, 68764, or 68766 type EPROM, programmed
with the customer's program (positive logic sense for
address and data), may be submitted for pattern generation. Since all program and data space information will
fit on one 2764, 68764, or 68766 EPROM device, the EPROM
must be programmed as described in the following paragraphs.
For an MC68HC805C4 MCU start the page zero, user
ROM at EEPROM address $0020 through $004F. Start the
user ROM at EEPROM address $0100 through $OBFF with
vectors from $1 FF4 to $1 FFF. All unused bytes, including
the user's space, must be set to zero. For shipment to
Motorola, EPROMs should be placed in a conductive IC
carrier and packed securely. Styrofoam is not acceptable
for shipment.

ORDERING INFORMATION

The following table provides ordering information pertaining to the package type, temperature, and MC order
numbers for the MC68HC05C3 device.
Temperature

Me Order Number

Plastic
(P Suffix)

O°C to + 70°C
- 40°C to + 85°C
- 40°C to + 105°C
- 40°C to + 125°C

MC68HC05C3P
MC68HC05C3CP
MC68HC05C3VP
MC68HC05C3MP

PLCC
(FN Suffix)

O°C to + 70°C
- 40°C to + 85°C
- 40°C to + 105°C
- 40°C to + 125°C

MC68HC05C3FN
MC68HC05C3CFN
MC68HC05C3VFN
MC68HC05C3MFN

Package Type

MDOS is a trademark of Motorola Inc.
MS is a trademark of Microsoft, Inc.
IBM is a registered trademark of International Business Machines Corporation.

MOTOROLA MICROPROCESSOR DATA
3-857

II

MC68HC05C3

PIN ASSIGNMENTS

40-PIN DUAl-IN-LiNE PACKAGE

VDD
OSCl
OSC2
TCAP
PD7
PA5

TCMP

PA4

PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO

PAl

PD1ITDO

I

PDO/RDI

PBO
PBl

PCO

PB2

PCl

PB3

PC2

PB4

PC3

PB5

PC4

PB6

PC5

PB7

PC6

VSS

44-lEAD PlCC PACKAGE

I~

-

N «
Q.
cor-en o u u
« « U U I~ w 0 en en U U

Q.Q.zz_a::>oo~.z

PD7
PA4

TCMP

PA3

PD5/SS

PA2

PD4/SCK

PAl

PD3/MOSI
PD2/MISO

PAO
PBO
PBl

PD1/TOO
pnOf.RDI

PB2

PLO

PB3
PB4

PCl
PC2
ULOCOr--

enur--COLO C
I Bit (CC)

Power-On Reset
External Reset
External Interrupt
Being Serviced (Vector Fetch)
(a) Interrupt Internal Function

iiill~tlLlH

I..

Diag~am

U

Edge-Sensitive Trigger Condition
The minimum pulse width (tILlH) is either
125 ns(Voo=5VI or 250 lis (VOO=3Vl.
The period tlLlL should not be less than
the number of !eyc cycles it takes to execute the interrupt service routine plus 21
tcyc cycles.

tILlL-----,l·~1

Level-S8nIitIve Trigger Condition
If after servicing an interrupt theiRO remains low, then the next interrupt is
recognized.

t

TIm,

(MCU)

Normally

L....-_ _ _ _--I

IROn

~

____________________________

Used with
Wire-ORed
Connection

r

~

(b) Interrupt Mode Diagram

Figure 8. External Interrupt

MOTOROLA MICROPROCESSOR DATA
3-867

I

MC68HC05C4

SOFTWARE INTERRUPT (SWI)

The SWI is an executable instruction that is executed
regardless of the state of the I bit in the CCR. If the I bit
is zero, SWI executes after the other interrupts, TheSWi
operation is similar to the hardware interrupts. The interrupt service routine address is specified by the Contents of memory locations $1 FFC and $1 FFD. .
SCI INTERRUPTS

An interrupt in the SCI occurs when one ofthe interrupt
flag bits in the serial communications status register is
set, provided the I bit in the CCR is clear and the enable
bit in the serial communications control register 2 Is set.
Software in the serial interrupt service routine must determine the cause and priority of the SCI interrupt by
examining the interrupt flags and status bits in the SCI
status register.
SPI INTERRUPTS

I

transfer, that transfer halts until the MCU exitsthe STOP
mode by a low signal on the IRQ pin. If reset is used to
exit the STOP mode, then the SPI control and status bits
are cleared, and the SPI is disabled. If the MCUis in the
slave mode when the STOP:instruction is exec~ted, the
slave SPI continues to operate and can still accept data
and clock information in addition to transmitting its own
data back to a master. device.
At the end of a possible transmission with a slave SPI
in the STOP mode, no flags are set until a Iowan the IRQ
pin wakes up the MCU. Caution should be observed when
operating the .SPI as a slave during the STOP mode because the protective circuitry (WCOl, MODF, etc.) is inc
active.
WAIT

The WAIT instruction places the MCU in a low-power
consumption mode, but the WAIT mode consumes more

An interrupt in the SPI occurs when one of the interrupt
flag bits in the serial peripheral status register is set,
provided the I bit in the CCR is clear and the enable bit
in the serial peripheral control register is set. Software
in the serial peripheral interrupt service routine must determine the cause and priority of the SPI interrupt by
examining the interrupt flag bits in the SPI status register.

Stop

Stop Oscillator
And All Clocks

LOW-POWER MODES

Clear I Bit

STOP

The STOP instruction places the MCU in its lowest power
consumption mode. In the STOP mode, the internal oscillator is turned off, halting all internal processing including timer, SCI, and SPI operation (refer to Figure 9).
During the STOP mode, the TCR bits are altered to
remove any pending timer interrupt request and to disable any further timer interrupts. The timer prescaler is
cleared. The I bit in the CCR is cleared to enable external
interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the STOP mode only by an
external interrupt or reset.

Yes

SCI during STOP Mode

When the MCU enters the STOP mode, the baud rate
generator stops,. halting all SCI activity. If the STOP instruction is executed during a transmitter transfer, that
transfer is halted. If a low input to the IRQ pin is used to
exit STOP mode, the transfer resumes. If the SCI receiver
is receiving data and the STOP mode is entered, received
data sampling stops because the baud rate generator'
stops, and all subsequent data is lost. For these reasons,
all SCI transfers should be in the idle state when the STOP
instruction is executed.

(1) Fetch Reset Vector or

(2) Service Interrupt
a. Stack
.
b. Set I Bit
c. Vector to Interrupt
Routine

SPI during Stop Mode

When the MCU enters the STOP mode, the baud rate
generator stops, terminating all master mode SPI operations. If the STOP instruction is executed during an SPI

Figure 9. STOP Function Flowchart

MOTOROLA MICROPROCESSOR DATA
3-868

MC68HC05C4

power than the STOP mode. All CPU action is suspended,
but the timer, SCI, and SPI remain active (refer to Figure
10). An interrupt from the timer, SCI, or SPI can cause
the MCU to exit the WAIT mode.
During the WAIT mode, the I bit in .the CCR is cleared
to enable interrupts. All other registers, memory, and
input/output lines remain in their previous state. The timer
may be enabled to allow a periodic exit from the WAIT
mode.

DATA RETENTION MODE

The contents of RAM and CPU registers are retained
at supply voltages as low as 2.0 Vdc. This is called the
data retention mode where the data is held, butthe device
is not guaranteed to operate. The MCU should be in RESET
during data retention mode.

TIMER
The timer consists of a 16-bit, software-programmable
counter driven by a fixed divide-by-four prescaler. This
timer can be used for many purposes, including input
waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from
several micro.seconds to many seconds. Refer to Figure
11 for a timer block diagram.
Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two
registers. These registers contain the high and low byte
of that functional segment.. Generally, accessing the low
byte of a specific timer function allows full control of that
function; however, an access of the high byte inhibits
that specific timer function until the low byte is also accessed.

I

Oscillator Active
Timer, SCI, And SPI
Clocks Active
Processor Clocks Stopped

(1) Fetch Reset Vector or
(2) Service Interrupt
a. Stack
b. Set I Bit
c. Vector to Interrupt
Routine

Figure 10. WAIT Function Flowchart

MOTOROLA MICROPROCESSOR DATA

3·869

MC68HC05C4

NOTE
The I bit in the CCR should be set while manipulating both the high and low byte register of aspecific timer function to ensure that an interrupt does
not occur.

COUNTER

I

The key element in the programmable timer is a 16bit, free-running counter or counter register, preceded by
a prescaler that divides the internal processor clock by
"four. The prescaler gives the timer a resolution of 2.0
microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock. Software can read the counter 'at any
time without affecting its value.
The double-byte, free-running counter can be read from
either of two locations, $18-$19 (counter register) or
$1A-$1 B (counter alternate register). A read from only
the least significant byte (LSB) ofthe free-running counter
($19, $1 B) receives the count value at the time of the read.

If a read ofthe free-running counter or counter alternate
register first addresses the most significant byte (MSB)
($18, $1A), the LSB ($19, $1B) is transferred to a buffer.
This buffer value remains fixed after the first MSB read,
even if the user'reads the MSB several times. This buffer
is accessed when reading the free-running counter or
counter alternate register LSB ($19 or $1B) anti, thus,
completes a read sequence of the total counter value. In
reading either the free-running counter or counter alternate register, if the MSB is read, the LSB must also be
read to complete the sequence.
The counter alternate register differs from the counter
register in one respect: a read of the counter register MSB
can clear the timer overflow flag (TOF). Therefore, the
counter alternate register can be read-at any time without
the possibility of missing timer overflow interrupts due
to clearing of the TOF.
The free-running counter is configured to $FFFC during
reset and is always a read-only register. During a poweron reset, the counter is also preset to $FFFC and begins

Internal
Processor
Clock

Low
Byte

High
Byte

$18

$14

$19

$15

$1A
$1B

a

r----~D

'---~----------------+---~----~~CLK

Output
Level
Reg.

Timer ....-..w-.....,.........L."""'T"-!:........
Status
Reg.

Timer
Control
Reg.
$12

C

mEr

Output Edge
Level
Input
(TCMP) (TCAP)

Figure 11. Timer Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-870

MC68HC05C4

running after the oscillator start-up delay. Because the
free-running counter is 16 bits preceded bya fixed divideby-four prescaler, the value in the free-running counter
repeats every 262,144 internal bus clock cycles; When the
counter rolls over from $FFFF to $0000, the TOF bit is set.
An interrupt can also be enabled when counter rollover
occurs by setting its interrupt enable bit (TOlE).

OUTPUT COMPARE REGISTER
The 16-bit output compare register is made up of two
8-bit registers at locations $16 (MSB) and $17 (LSB). The
output compllre register is used for several purposes,
such as indicating when a period of time has elapsed. All
bits are readable and writable and are not altered by the
timer hardware or reset. If th~ compare function is not
needed, the two bytes ofthe output compare register can
be used as storage locations.
The output compare register contents are compared
with the contents ofthe free-running counter continually,
and if a match is found, the corresponding output compare flag (OCF) bit is set and the corresponding output
level (OLCL) bit is Clocked to an output level register. The
output compare register values and the output level bit
should be changed after each successful comparison to
establish a new elapsed timeout. An interrupt can also
accompany a successful output compare provided the
corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare
register containing the MSB ($16), the output compare
function is inhibited until the LSB ($17) is also written.
The user must write both bytes (locations) if the MSB is
written first. A write made only to the LSB ($17) will not
inhibit the compare function. The free-running counter is
updated every four internal bus clock cycles. The minimum time required to update the output compare register is a function of the program rather than the internal
hardware.
The processor can write to either byte 'of the output
compare register without affecting the other byte. The
output level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF)
is set or clear.
INPUT CAPTURE REGISTER
Two 8-bit registers, which make up the 16-bit input
capture register, are read-only and are used to latch the
value of the free~running counter after the corresponding
input capture edge detector senses a defined transition.
The level transition which triggers the counter transfer is
defined by the corresponding input edge bit (IEDG). Reset
does not affect the contents of the input capture register.
The result obtained by an input capture will be one
more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the external transition . .This delay is required for internal synchronization. Resolution is one count of the free-running
counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to
the input capture register on each proper signal transition
regardless of whether the input capture flag (ICF) is set
or clear. The input capture register always contains the

free-running counter value that corresponds to the most
recent input capture.
After a read of the input capture register ($14) MSB,
the counter transfer is inhibited until the LSB ($15) is also
read. This characteristic causes the time usedinthe input
capture software routine and its interactiop with the main
program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not
inhibit the free-running counter transfer since they occur
on opposite edges of the internal bus clock.

TIMER CONTROL REGISTER (TCR) $12
The TCR is a read/write register containing five control
bits. Three bits control interrupts associated with the timer
status register flags .ICF, OCF, and TOF.
7

I ICIE I OCIE

TOlE

RESET:

OLVL

u

o

ICIE - Input Capture Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
OCIE - Output Compare Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
TOlE - Timer Overflow Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
IEDG - Input Edge
Value of input edge determines which level transition
on TCAP pin will trigger free-running counter transfer
to the input capture register
1 = Positive edge
0= Negative edge
Reset does not affect te IEDG bit (U = unaffected).
OLVL - Output Level
Value of output level is clocked into output level register by the next successful output compare and will
appear on the TCMP pin
1 = High output
O=Lowoutput
Bits 2, 3, and 4 - Not used
Always read zero

TIMER STATUS REGISTER (TSR) $13
The TSR is a read-only register contairiing three status
flag bits.
7

I

ICF

I

OCF

TOF

U

U

RESET:

U

ICF - Input Capture Flag
1 = Flag set when selected polarity edge is sensed by
input capture edge detector
0= Flag cleared when TSR and input capture low register ($15) are accessed

MOTOROLA MICROPROCESSOR DATA
3-871

IEDG

II

MC68HC05C4

OCF - Output Compare Flag
1 = Flag set when output compare register contents
match the free-running counter contents
0= Flag cleared when TSR and output compare low
register ($17) are accessed
TOF - Timer Overflow Flag
1 = Flag set when free-running counter transition from
$FFFF to $0000 occurs
0= Flag cleared when TSR and counter low register
($19) are accessed
Bits 0-4 - Not used
Always read zero

II

SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous SCI is provided with a
standard NRZ format and a variety of baud rates. The SCI
transmitter and receiver are functionally independent but
use the same data format and baud rate. The terms baud
and bit rate are used synonymously in the following description.

SCI TWO-WIRE SYSTEM FEATURES
• Standard NRZ (mark/space) format
• Advanced error detection method includes noise detection for noise duration of up to one-sixteenth bit
time
• Full-duplex operation (simultaneous transmit and receive)
• Software programmable for one of 32 different baud
rates
• Software-selectable word length (eight- or nine-bit
words)
.
• Separate transmitter and receiver enable bits
• SCI may be interrupt driven
• Four separate interrupt conditions

Accessing the timer status register satisfies the first
condition required to clear status bits. The remaining step
is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow
function and reading the free-running counter at random
times to measure an elapsed time. Without incorporating
the proper precautions into software, the timer overflow
flag could unintentionally be cleared if:
1) The timer status register is read or written when
TOF is set, and
2) The LSB of the free-running counter is read but not
for the purpose of servicing the flag.
The counter alternate register at address $1A and $1 B
contains the same value as the free-running counter (at
address $18 and $19); therefore, this alternate register
can be read at any time without affecting the timer overflow flag in the timer status register.

SCI RECEIVER FEATURES
•
•
•
•
•
•

TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the
timer remains active. An interrupt from the timer causes
the processor to exit the WAIT mode.

Receiver wake-up function (idle or address bit)
Idle line detect
Framing error detect
Noise detect
Overrun detect
Receiver data register full nag

SCI TRANSMITTER FEATURES
• Transmit data register empty flag
• Transmit complete flag
• Break send

TIMER DURING STOP MODE
In the STOP mode, the timer stops counting and holds
the last count value if STOP is exited by an interrupt. If
RESET is used, the counter is forced to $FFFC. Ouring
STOP, if at least one valid input capture edge occurs at
the TCAP pin, the input capture detect circuit is armed.
This does not set any timer flags nor wake up the MCU,
but when the MCU does wake up, there is an active input
capture flag and data from the first valid edge that occurred during the STOP mode. If RESET is used to exit
STOP mode, then no input capture flag or data remains,
even if a valid input capture edge occurred.

Any SCI two-wire system requires receive data in (ROI)
and transmit data out (TOO).

DATA FORMAT
Receive data in (ROI) or transmit data out (TOO) is the
serial data presented between the internal data bus and
the output pin (TOO) and between the input pin (ROI) and
the internal data bus. Oata format is as shown for the
NRZ in Figure 12.
Control bit "M"
Selects 8 or 9 bit data

o
Idle Line

3

4

o

-I_____
L
S

S
- Stop bit is always high.

o
p

Figure 12. Data Format

MOTOROLA MICROPROCESSOR DATA
3-872

S

MC68HC05C4

WAKE-UP FEATURE
In a typical multiprocessor configuration, the software
protocol will usually identify the addressee(s) at the beginning of the message. To permit uninterested MPUs to
ignore the remainder of the message, a wake-up feature
is included, whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until its data line
returns to the idle state. An SCI receiver is r~~enabled by
an idle string of at leastten (or eleven) consecutive ones.
Software for the transmitter must provide forthe required
idle string between consecutive messages and prevent
it from occurring within messages.
A second wake-up method is available in which sleeping SCI receivers can be awakened by a logic one in the
high-order bit of a received character.
RECEIVE DATA IN
Receive data in (RDI) is the serial data which is presented from the input pin via the SCI to the receive data
register (RDR). While waiting for a start bit, the receiver
samples the input at a rate 16 times higher than the set
baud rate. This increased rate is referred to as the RT
rate. When the input (idle) line is detected low, it is tested
for three more sample times. If at least two of these three
samples detect a logic low, a valid start bit is assumed
to be detected. If in two or more samples, a logic high is
detected, the line is assumed to be idle. The receive clock
generator is controlled by the baud rate register (see Figure 13); however, the SCI is synchronized by the start bit
independent of the transmitter. Once a valid start bit is
detected, the start bit, each data bit, and the stop bit are
each sampled three times. The value of the bit is determined by voting logic, which takes the value of a majority
of samples. A noise flag is set when all three samples on
a valid start bit, data bit, or stop bit do not agree. A noise
flag is also set when the start verification samples do not
agree.
START BIT DETECTION FOLLOWING A FRAMING ERROR
If there has been a framing error (FE) without detection
of a break (10 zeros for 8-bit format or 11 zeros for a 9bit format), the circuit continues to operate as if there
actually were a stop bit, and the start edge will be placed
artificially. The last bit received in the data shift register
is inverted to a logic one, and the three logic-one start
qualifiers are forced into the sample shift register during
the interval when detection of a start bit is anticipated;
therefore, the start bit will be accepted no sooner than it
is anticipated.
If the receiver detects that a break (RDRF = 1, FE = 1,
receiver data register = $00) produced the framing error,
the start bit will not be artificially induced, and the receiver must actually receive a logic one before start.

FUNCTIONAL DESCRIPTION
A block diagram of the SCI is shown in Figure 13. The
user has option bits in the serial communications .control
register 1 (SCCR1) to determine the SCI wake-up method
and data word length. Serial communications control
register 2 (SCCR2) provides control bits that individually
enable/disable the transmitter or receiver, enable system
interrupts, and provide wake-up enable, and send break
code bits. The baud rate register bits allow the user to
select different baud rates, which are used as the rate
control for the transmitter and receiver.
Data transmission is initiated by a write to the serial
communications data register (SCDAn. Provided the
transmitter is enabled, data stored in the SCDAT is transferred to the transmit data shift register. This data transfer
sets the SCI status register (SCSR) transmit data register
empty (TDRE) bit and generates an interrupt if the transmit interrupt is enabled. Data transfer to the transmit data
shift register is synchronized with the bit rate clock. All
data is transmitted LSB first. Upon completion of data
transmission, the transmission complete (TC) bit is set
(provided no pending data, preamble, or break code is
sent), and an interrupt is generated ifthe transmit complete interrupt is enabled. If the transmitter is disabled,
and the data, preamble, or break code has been sent, the
TC bit will alsobe set, which will also generate an interrupt if the TCIE bit is set. Ifthe transmitter is disabled in
the middle of a transmission, that character will be completed before the transmitter gives up control of the TDO
pin.
When the SCDAT is read, it contains the last data byte
received; provided that the receiver is enabled. The SCSR
receive data register full (RDRF) bit is set to indicate that
a data byte is transferred from the input serial shift register to the SCDAT, which can cause an interrupt if the
receiver interrupt is enabled. Data transfer from the input
serial shift register to the SCDAT is synchronized by the
receiver bit rate clock. The SCSR overrun (OR)' noise flag
(NF), or FE bits are set .if data reception errors occur.
An idle line interrupt is generated if the idle line interruptis enabled and the SCSR IDLE bit (which detects idle
line transmission) is set. This allows a receiver that is not
in the wake-up mode to detect the end of a message, the
preamble of a new message, or to resynchronize with
the transmitter. A valid character must be received before
the idle line condition for the IDLE bit to be set and for
an idle line interrupt to be generated.

REGISTERS
There are five registers used in the SCI; the internal
configuration of these registers is discussed in the following paragraphs.
Serial Communications Data Register (SCDAT) $11

TRANSMIT DATA OUT
Transmit data out (TDO) is the serial data presented
from the transmit data register (TDR) via the SCI to the
output pin. The transmitter generates a bit time by using
a derivative of the RT clock, producing a transmission
rate equal to one-sixteenth that of the receiver sample
clock.

The SCDAT isa read/write register used to receive and
transmit SCI data.
7

6

I SCD7 I SCD6

5
SCD5

SCD4

SCD3

SCD2

SCDl

SCDO

u

u

u

u

RESET:

U

u

u

MOTOROLA MICROPROCESSOR DATA

3..873

II

MC68HC05C4

As shown in Figure 13, SCDAT functions as two separate registers. The transmit data register (TDR) provides
the parallel interface from the internal data bus to the
transmit shift register. The receive data. register (RDR)
provides the interface from the receive shift register to
the internal data bus.
.

Serial Communications Control Register 1 (SCCR1) SOE
The SCCR1 provides control bits that determine word
length and select the wake-up method.

RS
RESET:
U

TS

M

I WAKE I

u

u

u

R8 - Receive Data Bit 8
R8 bit provides storage location for the ninth bit in the
receive data byte (if M == 1). .
T8 - Transmit Data Bit 8
T8 bit provides storage location for the ninth bit in the
transmit data byte (if M = 1).

II
Internal
Processor
Clock

$00

$OE

NOTE: The Serial Communications Data Registllr (SCDA Tl is controlled by the internal R/W signal. It is the transmit data register when
written and receive data register when read.

Figure 13. SCI Block Diagram

MOTOROLA MICROPROCESSOR DATA
3-874

MC68HC05C4

M-

SCI Character Word Length
1 = one start bit, nine data bits, one stop bit
0= one start bit, eight data bits, one stop bit
WAKE - Wake-Up Select
Wake bit selects the receiver wake-up method.
1 = Address bit (most signi.ficant bit)
0= Idle line condition
Bits 0-2, and 5 - Not used
Can read either one or zero
The address bit is dependent on both the wake-bit and
the M-bit level. Additionally, the receiver does not use
the wake-up feature unless the RWU control bit in SCCR2
is set.
Wake

M

Receiver Wake-Up

0

X

Detection of an idle line allows the next data
byte received to. cause the receive data register to fill and produce an RDRF flag.

1

0

Detection of a received one in the eighth
data bit allpws an RDRF flag and associated
error flags.

1

Detection of a received one in the ninth data
bit allows an RDRF,flag and associated error
flags.

Serial Communications Status Register (SCSR) $10

.

1

0= Receiver disabled and RDRF, IDLE, OR, NF, and
FE status bits are inhibited.
RWU - Receiver Wake-Up
.
•
1 = Places receiver in sleep mode and enables wakeup function
0= Wake-up function disabled after.receiving data
word with MSB set (if WAKE = 1)
Wake-up fu nction also disabled after receiving 10
(M=O) or 11 (M = 1) consecutive ones (ifWAKE=O)
SBK- Send Break
.'.
. ' . '
1=Transm.itter continually sends biocks of zeros (sets
of 10 or 11) u~tilcleared. Upon. completion of
break code, transmitter sends one high bit for recognition of vCllid start bit.
O=Transmitter sends 10 (M=O) ,or 11 (M=1) zeros
then reverts to an idle state or continues sending
data. If transmitter is empty and 'idle, setting and
clearing the SBK bit may queue up to two character times of break because the first break transfers immediately to the' shift register, and the
second is queued into,the parallel transmit buffer.

The SCSR provides inputs to the SCI interrupt logic
circuits. Noise flag and framing error bits are 8Iso<:ontained in the SCSR.

Serial Communications Control Register 2 (SCCR2) $OF
The SCCR2 provides control of individual SCI functions
such as interrupts, transmit/receive enabling, receiver
wake-up, and break code.
.

TORE

TC

RORF

IDLE

3,

2

OR

NF

FE

RESET:
1

7

I TIE I TCIE
RESET:
0

TIE

RIE

ILiE

TE

l

RE

RWU

SBK

0

~

Transmit Interrupt Enable
1 = SCI interrupt enabled
0= TDRE interrupt disaqled
TCIE - Transmit Complete Interrupt Enable
1 = SCI interrupt enabled
0= TO interrupt disabled
RIE - Receive Interrupt Enable
1 = SCI interrupt enabled
0= RDRF and OR interrupts disabled
ILiE - Idle Line Interrut Enable
1 = SCI interrupt enabled
0= Idle interrupt disabled
TE - Transmit Enable
1 == Transmit shift register output is applied to the TDO
line. Depending upon the SCCRl M bit, a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones i::;
transmitted.
0= Transmitter disabled after last byte is loaded in
the SCDAT and TDRE is set. After last byte is
transmitted, TDO line becomes a high-impedance
line.
RE- Receive Enable
1 = ReGeiver shift register input is applied to the RDI
line.

TDRE -:... Transmit Data Register (TDR) Empty
1 = TDR contents transferred to the transmit d.ata shift
register
0= TDR still contains data. TDRE is cleared by reading
the SCSR (with TDRE = 1), followed by a write to
the TDR.
TC - Transmit Complete
1 = Indicates end of data frame, preamble, or break
condition has occurred
o=TC bit cleared by reading tlw SCSR(with TC = 1),
followed by a write to the TDR '
RDRF - Receive Data Register (RDR)' Full
1 = Receive data shift register contents transferred to
the RDR
0= Receive ,data shift register transfer did not occur.
RDRF is cleared by reading the SCSR (With
RDRF = 1) followed by a read of the RDR
IDLE :..-. Idle Line Detect
1 = Indicates receiver has detected an idle line
0= IDLE is cleared by reading the SCSR (with IDLE = 1),
followed by a read of the RD~. dhce IDLE is
cleared, IDLE cannot be set until RDIline becomes
active ~lnd idle again.
OR - Overrun Error
1 = Indicates. receive data shift register data is sent to
a full RDR (RDRF= 1). Data causing the; overrun
" is.lost, and RDR data is riot,disturbed.
'. "
0= OR is cleared by re"ding the SCSR (with OR = 1)'
followed by a read of the RDR.

MOTOROLA MICROPROOESSORDATA
3~875

I

MC68HC05C4

NF -

Noise Flag
1 = Indicates noise is present on the receive bits, including the start and stop bits. NF is not set until
RDRF= 1:
O=NF is cleared by reading the SCSR (with NF= 1),
followed by a read of the RDR.
FE - Framing Error
1 = Indicates stop bit not detected in received data
character. FE is set the same time RDRF is set. If
received byte causes both framing and overrun
errors, processor vitill only recognize the overrun
error. Further data tran'sfer into the RDR is inhibited' until FE is cleared.
0= NF is cleared by reading the SCSR (with FE = 1),
followed by a read of theRDR.
Bit 0 ~ Not used
Can read either one or zero

SCPO - SCI Prescaler Bit 0 "
SCP1 - SCI Prescaler Bit 1
Twoprescaler bits are used to increase the range of
standard baud rates controlled by the SCRO-SCR2
bits. Prescaler internal processor clock division versus bit levels are listed in Table 2.
SCRO - SCI Baud Rate Bit 0
SCRl - SCI Baud Rate Bit 1
SCR2 - SCI Baud Rate Bit 2
Three baudr,ate bits are used to select the baud rates
of the SCI transmitter and SCI receiver. Baud rates
versus ,bit levels are listed in ,Table 3.
Tables 3 and 4 tabulate the divide chain used to obtain
the baud rate clock (transmit clock). The actual divider
chain is controlled by the combined SCPO-SCPl and SCRO'SCR2 bitsin the baud rate register. All divided frequencies show'n in Table 3 represent the final baud rate resulting from the internal processor clock division shown
in the divided-by column only (prescaler division only).
Table 4 lists the prescaler output divided by the action
of the SCI select bits (SCRO-SCR2). For example, assume
that a 9600-Hz baud rate is required with a 2.4576-MHz
external crystal. In this case, the prescaler bits (SCPO,
SCP1) could be configured as a divide-by-one or a divideby-four. If a divide-by-four prescaler is used, then the
SCRO-SCR2 bits must be configured as a divide-by-two.
Using the'same ciystal, the 9600 baud rate can be obtained vvith a prescaler divide-by-one and the SCRO~SCR2
bits configured for 'a divide-by-eight.

Baud Rate Register $00

I

The baud rate register is used to select the SCI transmitter and receiver baud rate. SCPO and SCPl prescaler
bits are used in conjunction with the SCRO through SCR2
bal:ld rate bits to provid~ multiple baud rate combinations
fora given crystal frequency. Bits 3, 6, and 7 always read
zero.
7

I -I

SCPl

SCPO

SCR2

SCRI

seRO

RESET:

u

u

Table,3. Prescaler Highest Baud Rate Frequency OiJtput
SCP Bit

1

0

0
0
1
1

0
1
0
1

Clock*
Divided By
"

1
3
4
13

Crystal Frequency MHz
4.194304
131.072
43.691
32.768
10.082

kHz
kHz
kHz
kHz

4.0
125.000 kHz
41.666 kHz
31.250 kHz
9600 Hz

2.4576

76.80
25.60
19.20
5.907

kHz
kHz
kHz
kHz

2.0

1.8432

62.50 kHz
20.833 kHz

57,60 kHz
19.20 kHz
14.40 kHz
4430 Hz

15.625 kHz
4800Hz

*Refers to the internal processor clock.
NOTE: The divided frequencies shown in Table 3 represent baud rates which are the highest transmit baud rate'(Tx) that can be
obtained by a specific crystal frequency and only using the prescaler division. Lower baud rates maybe obtained by providing
a further division· using the SCI rate select bits as shown below for some representative prescaler outputs:

Table 4. Transmit Baud Rate Output for a Given Prescaler Output
SCR Bits
2

1

0

0
,0
0
0
1
1
1
1

0

0
1
0
1
0
1
0
1

Q
1

'1'

0
0
1
1,

Divided
By

.

1
2
4
8
16
32
64
128

Representative Highest Prescaler Baud Rate Output
131.072 kHz

32.768 kHz

76.80 kHz

19.20 kHz

9600 Hz

131.072 kH?

32.768
16.384
8.192
4.096

76.80 kHz

19.20 kHz

38.40 kHz
1920 kHz
9600 Hz
4800 Hz
2400 Hz
1200Hz
600 Hz

9600 Hz
4800 Hz
2400 Hz
1200 Hz
600 Hz
300 Hz
150 Hz

9600 Hz
4800 Hz

65.536
32.768
16.384
8.192
4.096
2.048

kHz
kHz
kHz
kHz
kHz
kHz
1.024 kHz

kHz
kHz
kHz
kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz

2400 Hz
1200 Hz
600 Hz
300 Hz
150 Hz
75 Hz

NOTE: Table 4 i1lu!)trates how the SCI select bits can be used to provide lower transmitter baud rates by further dividing the prescaler
output frequency. The five examples are only re'presentative samples. In all cases, the baud rates shown are transmit baud
rates (transmIt clock), and the receive clock is16 times higher in frequency than the actual baud rate.

MOTOROLA MICROPROCESSOR DATA
3~876

MC68HC05C4

Serial Clock
The serial clock (SCK) is used to synchronize both data
in and out of a device via the MOSI and MISO lines. The
master and slave devices can exchange a byte of information during a sequence of eight clock cycles. Since
SCK is generated by the master device, this line becomes
an input on a slave device.
As .shown in Figure 15, four possible timing relationships may.'be chosen by using control bits CPOL and
CPHA in the serial peripheral control register (SPCR). Both
master and slave devices must operate with the same
timing.
Two bits (SPRO and SPR1) in the SPCR of the master
device select the clock rate. In a slave device, SPRO and
SPR1 have no effect on SPI operation.

SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) is an interface built
into the MCU which allows several MCUs or MCUs plus
peripherals to be interconnected within the same black
box. In the SPI format. the clock is not included in the
data stream and must be furnished as a separate signal.
An SPI system may consist of one master MCUand several slaves (Figure 14) or MCUs that can be either masters
or slaves.
Features:
• Full-duplex, three-wire synchronous transfers
• Master or slave operation
• 1.05 MHz (maximum) master bit frequency
• 2.1 MHz (maximum) slave bit frequency
• Four programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Write collision flag protection
• Master-master mode fault protection capability

Slave Select
The slave select (SS) input line selects a slave device.
The SS line must be low prior to data transactions and
must stay low for the duration of the transaction. The SS
line on the master must be. tied high; if the SS line goes
low, a mode fault error flag (MODF) is set in the serial
peripheral status register (SPSR).
When CPHA = 0, the shift clock is the OR of SS with
SCK. In this clock phase mode, SS must go high between
successive characters in an SPI message. When CPHA= 1,
SS must go high between successive characters in an
SPI message. When CPHA = 1, SS' may be left low for
several SPI characters. In cases where there is only one
SPI slave MCU, the slave MCU SS line could be tied to
VSS as long as CPHA= 1 clock modes are used.

SIGNAL DESCRIPTION
The four basic signals (MOSI, MISO, SCK, and SS) are
described in the following paragraphs. Each signal function is described for both master and slave mode.
Master Out, Slave In
The master out, slave in (MOSI) line is configured as
an output in a master device and as an input in a slave
device. The MOSI line is one of two lines that transfer
serial data in one direction with the most significant bit
sent first.

FUNCTIONAL DESCRIPTION
A block diagram of the SPI is shown in Figure 16. In a
master configuration, the CPU sends a signal to the master start logic, which originates an SPI clock (SCK) based
on the internal processor clock. As a master device, data
is parallel loaded into the 8-bit shift register from the
internal bus during a write cycle and then serially shifted

Master In, Slave Out
The master in, slave out (MISO) line is configured as
an input in a master device and as an output in a slave
device. The MISO is one of two lines that transfer serial
data in one direction with the most significant bit sent
first. The MISO line ota slave device is placed in a highimpedance state if slave is not selected (SS = 1).

M6805 HCMOS SlaveO

MISO
MOSI
SCK

MISOSCK_
MOSI . SS

ss t---voo

'---

M6805 HCMOS
Master

r-P

0
R
T

()J

1
2
'3 "'--

.

T
I

I II
II MOSI.
SS.,
MISO SCK
M6805 HCMOS Slave 3

"

T

II

SS
MOSI
MISO SCK

II
MOSI
SS
MISO
SCK
M6805 HCMOS Slave 2

M6805 HCMOS Slave 1

. Figure' 14. Master-Slave Systern Configuration

MOTOROLA MICROPROCESSOR DATA
3-877

I

II

MC68HC05C4

?CK (CPOL = 0)
SCK (CPOL", 1)

Sample Input
Data' o,ut (CPH~ = 1)
Sample Input'
Data out (CHPA=O)

Figure 15. Data Clock Timing Diagram
Internal

SCK (PD4)

Processor
Clock

I

1-+-=4--l_-.-_t"-+

SS (PD5).

Internal
Data
Bus

--+--......---'-'~

SPCR
$OA

L---r-_-J

Figure 16. SPI Block Diagram

via the MOSI pin to the slave devices. During a read cycle,
data is applied serially from a slave device via the MISO .
pin to the 8-bitshift register. Da~a is then parallel transferred to the read buffer and made available to the internal data bus during a CPU read cycle.
In a slave configuration, the 'slave start logic receives
a logic low at the SS pin and a clock input at the. SCK
pin. This synchronizes the slave. with the master. Data
from the master is received serially at the slave MOSI pin
and shifted into the 8-bit shift register for a parallel transfer to the read buffer. During a write cycle, data is parallel
loaded into the 8-bit shift regi~ter]rorn the internal data
bus, awaiting the clocks from the master to shift out se-,
rially to the MISO pin and then t6 the master device.~
Figure 17 illustrates the' MOSI,' MISO, SCK,and SS
master-slave interconnections.
'
REGISTERS

There are three registers in the SPI that provide control,
status, and data storage functions. These re,gisters, the

serial peripheral control register (SPCR), serial peripheral
status register (SPSR), and serial peripheral data 110 register (SPDR), are described in the following paragraphs.
Serial Peripheral Control Register $OA

The SPCR provides control of individual SPI functions
such as interrupt and system enabling/disabling, master/
slave mode select, and clock polarity/phase/rate select.
7

I

SPIE.I SPE

. RESET:
0

4

2

I MSTR I CPOL I CPHA I SPRI
U

U

SPIE - Serial Peripheral Interrupt Enable
1 = SPI interrupt enabled
0= SPI interrupt disabled
SPE-, Serial PeripheraLSystem Enable
1 = SPI system on
0= SPI system off

MOTOROLA MICROPROCESSOR DATA
3~878

U

SPRO

U

MC68HC05C4

~

M!!1!r
8-Bit Shift Register

I MISO

I
MISOI,

I MOS'

MOS,I

8-Bit Shift Register

I
I

,
I SCK

SCKI
I

ISS
I

+5V

SSI

ov----,

Figure 17. SPI Master-Slave Interconnections
MSTR - Master Mode Select
1 == Master mode
0== Slave mode
CPOl - Clock Polarity
Clock polarity bit controls the clock value and is used
in conjunctiop with the,clock phase (CPHA) bit.
1 == SCK line idles high
Oc=SCK line idles in low state
CPHA - Clock Phase
Clock phase bit along with CPOl controls the clockdata relationship between the master and slave devices. CPOl selects one of two clocking protocols.
1,,;; SS is an output enable control.
0= Shift clock is the OR of SCK with SS.
,When SS is low, first edge of SCK invokes first
data sample.
SPRO, SPR1 - SPI Clock Rate Bits
Two clock rate bits are used to select one of four clock
rates to be used as SCK in the master mode. In the
slave mode, the two clock rate bits have no effect. Clock
rate selection is shown in the following table.
Bit 5 - Not used
Can read either one or zero
SPI Clock Rate Selection
SPR1

SPRO

0
0

0
1

2
4

1
1

0
1

32

Internal Processor
Clock Divided By

16

Serial Peripheral Status Register SOB

0== Clearing is accomplishedby reading SPSR(with
SPIF = 1) followed by SPPR access.
WCOl - Write Collision
1 = Indicates an attempt is made to write to SPDR
while data transfer is in process.
0== Clearing is accomplished by reading SPSR (with
WCOl = 1). followed by SPDR access.
MODF - Mode Fau It Flag
1 = Indicates multi-master system control conflict.
0= Clearing is accomplished by reading SPSR (with
MODF = 1). followed by a write to the SPCR.
Bits 0--3, and 5 - Not used
Can read either zero or one
Serial Peripheral Data 1/0 Register$OC
The SPDR is a read/write register used to receive and
transmit SPI data.
7

I SPD7 I SPD6

SPD5

SPD4

u

u

SPD3

SPD2

SPD1

SPDO

u

u

u

RESET:

U

u

A write to the SPDR places data directly into the shift
register for transmission. Only a write to this register will
initiate transmission/reception of another byte and will
only occur in the master device. On completion of byte
transmission, the SPIF status bit is set ,in both master and
slave devices.
A read to the SPDR causes the buffer to be read; The
first SPIF status bit must be cleared by the time a second
data transfer from the shift register to the read buffer
begins, or an overrun condition will exist. In overrun cases,
the byte causing the overrun is lost.

The SPSR contains three status bits.
7
SPIF

6

I

weOl

4

I

I

MODF

INSTRUCTION SET

I

RESET:

o

SPIF -

Serial Peripheral Data Transfer Flag
1 = Indicates data transfer completed between pro'
cessor and external device.
(If SPIF == 1 and SPIE = 1, SPI interrupt is enabled.)

The MCU has a set of 62 basic instructions. They can
be divided into five different types: register/memory, readmodify-write, branch, bi~ manipulation, and contro.!. The
following, paragraphs briefly explain each type. ,
This MCU uses all the instructions available in the
M146805 CMOS Family plus one more: the unsigned
l)1ultiply (MUl) instruction. This instruction allows unsigned multiplication of the contents of the accumulator

MOTOROLA MICROPROCESSOR D'ATA
3-879

I

MC68HC05C4

(A) and the index register (X). The high-order product is
then stored in the index register, and the low-order product is stored in the accumulator. A detailed definition of
the MUL instruction is shown below.

Mnemonic
INC

Decrement

DEC

Operation

X:A X*A

Clear

CLR

Description

Multiplies the eight bits in the index register
by the eight bits in the accumulator to obtain
a 16-bit unsigned number in the concatenated
accumulator and index register

Complement

COM

Negate (Twos Complement)

NEG

Rotate Left Thru Carry

ROL

H: Cleared
I: Not affected
N: Not affected
Z: Not affected
C: Cleared

Rotate Right Thru Carry

ROR

Condition
Codes

I

Function
Increment

Source

MUL

Form(s)

Addressing'
Mode
Inherent

I
Cycles
11

I

Bytes
1

I Opcode
$42

REGISTER/MEMORY INSTRUCTIONS
Most of these instructions use two operands. One operand is either the accumulator or the index register. The
other operand is obtained from memory using one of the
addressing modes. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register
operand. Refer to the following instruction list.
Mnemonic

Function

LOA

load A from Memory
Load X from Memory

LDX

Store A in Memory

STA

St'ore X in Memory

STX

Add Memory to A

ADD

Add Memory and Carry to A

ADC

Subtract Memory

SUB

Subtract Memory from A with Borrow

SBC

AND Memory to A

AND

OR Memory with A

ORA

Exclusive OR Memory with A

EOR

Arithmetic Compare A with Memory

CMP

Arithmetic Compare X with Memory

CpX

Bit Test Memory with A (Logical Compare)

BIT

Jump Unconditional

JMP

Jump to Subroutine

JSR

Logical Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

Multiply

MUL

BRANCH INSTRUCTIONS
This set of instructions branches if a particular condition is met; otherwise, no operation is performed. Branch
instructions are two-byte instructions. Refer to the following list for branch instructions.
Function

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

Branch if Carry Clear

BCC

Branch if Higher or Same

BHS

Branch if Carry Set

BCS

Branch if Lower

BLO

Branch if Not Equal

BNE

Branch if Equal

READ-MODIFY-WRITE INSTRUCTIONS
These instructions read a memory location or a register, modify or test its contents, and write the modified
value back to memory or to the register. The test for
negative or zero (TST) instruction is an exception to the
read-modify-write sequence since it does not modify the
value. Refer to the following list of instructions.

BEQ

Branch if Half Carry Clear

BHCC

Branch if Half Carry Set

BHCS

Branch if Plus

BPL

Branch if Minus

BMI

Branch if Interrupt Mask Bit is Clear

BMC

Branch if Interrupt Mask Bit is Set

BMS

Branch if Interrupt Line is Low

BIL

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

BIT MANIPULATION INSTRUCTIONS
The MCUis capable of setting or clearing any writable
bit which resides' in the first 256 bytes of the memory
space where all port registers, port DDRs, timer, timer
control, ROM, and on-chip RAM reside. An additional
feature allows the software to test and branch on the state

MOTOROLA MICROPROCESSOR DATA
3-880

Mnemonic

Branch Always

MC68HC05C4

of any bit within these 256 locations. The bit set, bit clear
and bit test, and branch functions are all implemented
with a single instruction. For test and branch instructions,
the value of the bit tested is also placed in the carry· bit
of the condition code register. Refer to the following list
for bit manipulation instructions.
Function

IMMEDIATE
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The
immediate addressing mode is used to access constants
that do not change during program execution (e.g., a
constant used to initialize a loop counter).

Mnemonic

Branch if Bit n· is Set

BRSET n (n=O ... 7)

Branch if Bit n is Clear

BRClR n (n=O ... 7)

Set Bit n

BSET n (n=O ... 7)

Clear Bit n

BClR n (n=O ... 7)

CONTROL INSTRUCTIONS
These instructions are register reference instructions
and are used to control processor operation during program execution. Refer to the following list for control
instructions.

Transfer A to X

TAX

Transfer X to A

TXA

Set Carry Bit

SEC

Clear Carry Bit

ClC

Set Interrupt Mask Bit

SEI

Clear Interrupt Mask Bit

CLI

Software Interrupt

SWI

Return from Subroutine

RTS

Return from Interrupt

RTI

Reset Stack Pointer

RSP

No-Operation

NOP

Stop

STOP

Wait

WAIT

DIRECT
In the direct addressing mode, the effective address of
the argument is contained in a single byte following the
opcode byte. Direct addressing allows the user to directly
address the lowest 256 bytes in memory with a single
two-byte instruction.
EXTENDED
In the extended addressing mode, the effective address
of the argument is contained in the two bytes following
the opcode byte. Instructions with extended addressing
mode are capable of referencing arguments anywhere in
memory with a single three-byte instruction. When using
the Motorola assembler, the user need not specify whether
an instruction uses direct or extended addressing. The
assembler automatically selects the shortest form of the
instruction.

Mnemonic

Function

applications. Extended addressing permits jump instructions to reach all memory.
The term "effective address" (EA) is used in describing
the various addressing modes. Effective address is defined as the address from which the argument for an
instruction is fetched or stored.

OPCODE MAP SUMMARY
Table 5 is an opcode map for the instructions used on
the MCU.

ADDRESSING MODES
The MCU uses ten different addressing modes to provide the programmer with an opportunity to optimize the
code for all situations. The various indexed addressing
modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte
instructions; the longest instructions (three bytes) permit
accessing tables throughout memory. Short and long absolute addressing is also included. One- or two-byte direct addressing instructions access all data bytes in most

RELATIVE
The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC if, and only if, the branch conditions are true.
Otherwise, control proceeds to the next instruction. The
span of relative addressing is from ~ 126 to + 129 from
the opcode address. The programmer need not calculate
the offset when using the Motorola assembler, since it
calculates the proper offset and checks to see that it is
within the span of the branch.
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the'8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or to hold the address of a frequently referenced
RAM or 1/0 location.
INDExeD, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of

MOTOROLA MICROPROCESSOR DATA

3·881

II

•

Table 5. Opcode Map

~

c:.o

~

3BASE:~B

cx1,

3BACL:~B

:,!;

2

BASE
3

~,

Co

~

:?:

BASE
3

0100

:?:

a
o

01~'

BRCL
3

o~o

BRSE
,3

s:

k

O{"

§;

w

BACL
3
:T';

4

%I,

n
%I

9
'00'

o'V
%I
o
("')
(J)

en

:ia

BACL
3

,~

BASE
3

C

l1~O

~

1111

l>

3BRCL~:
3BRSEJ~:

B
'011

,g,

o%I

:i:

,

3BASEJ~:
3BRCL:~

,:'0

m

5

F

17

BSE~~:

1

BCL~~c

5

0010

s:

~1

REL

IR

INH

r1,0

J,1

o~

,2

BAA j
AEL
3

2

BA~J:L

5

5

BCL~~c

,

BSE~tc

2

5
5

2 BCL~1c
5
7

BSE1~c

5

2

BCL~~c

Jf:_5 2 BSE1~;

,

2

2BSE1~c i

2

BNEREL
3
BEQ
AEL
3

BHC~E"

3
2 BHCS
REL
3

,

BPL
RH
3
BMI
2
AEL
3
BMC
2
AEL
3

BACL
3
:fR
5

,

BCL~~;

JBASEJIB
5
BACLA7
BTB
3

1

BSE~~c

2

,

5
BCLR7
BSC

,

,

5

BM~FI

3

NEGA
1

0~0

3

NEGX

INH

1

INH

2

01~1

1000

5
2 COM
OIA
5
2

LS~TA

8

I

NEG 5
IX

ATI
1

1

INH

,

3
LSAA
INH

INC

OIA
4

,

TS~A

,
,

3
INCA
INH
3
TSTA
INH

,
,

3
COM X
INH
3
LSRX
IN"

6
2 COM
IX'
6
LSR
2
IX'

3

, RORXINH

6

ROR
2

IX'

3

6

ASR

ASRX
1

INH

2

IX'
6

3
LSLX
1

INH

7

LSL

3
1

INH

,

2

INH

2

3

5
,

CLR

OIA

2

, TSTXINH
I

IX'

I

IX'
5

3

3

, CLRAINH

,
I

INC
TST
2

IX'

3
CLRX
INH

6

CLR
2

IX'

IX
5

,

SWI
INH

LSR
, IX

5

IX'
6

6

INCX
INH

COM

J
3

CMP
EXT

3

SBC
EXT

AND
EXT
3

LD~MM

AND J
OIR
2
3
BIT
1
OIR
3
LDA
OIA
2

2
EOR
IMM
2
ADC
IMM
2

STA
OIA
2
3
L EOR
OIR
3
ADC
OIR
2

,
,

,2

"

5
LSL
ROt

DEC

DECX

2 SUB
OIA
3
CMP
OIA
2
3
SBC
OIR
2
3
CPX
OIA
2

lfoo
SU~x;

1011

2

10

, ROR IX
5
, ASR IX

ROL
3

I

IX'

,
,

5

6

ROLX

,8

SUB L
IMM
2
CMP
IMM
2
2
SBC
12
IMM
2
CPX
IMM
2
2
AND
12
IMM
2
BIT
. 21M"
2

9

INH
6
RTS
INH

11

INH
3
" COMA

,
,

2

9

DEC

IX
5
IX
5

I

,
,
,

IX

IX
4

,

TST
IX

2
SEC
INH
2
Cli
INH
SEI l
INH
2
RSP
'NH
2
NOP
INH

2

,

5
CLR

IX

, STOPINH
, WAITINH2 ,

A

X
IMM

DIR
EXT

REL
BSC
BTB
IX

IXl
IX2

Inherent
Accumulator
Index Register
Immediate
Direct
Extended
Relative
Bit Setl Clear
Bit Test and Branch
I"dexed (No Offset I
Indexed. 1 Byte (8-Bitl Offset
Indexed. 2 Byte 06-Bitl Offset

1X2

IX1

1~1

1110

3. SUB lx :

EXT

IX'

,

SBC 3
IX

IXl

,

CPX

IX

;0011

,

AND 3
IX

0100

SBC 5
IX2

2

3

4

4

~
IX2
5

CPX
2

4

AND

AND
IX2
5

2

BIT IXl
'5

2

3
3

4

LDA
EXT
3

SBC

3

4

3

I

2

ORA L
IMM

2

ADD 2
IMM

2

ORA j
OIA

ADD 3
OIR
2
JMP
OIR
2

2

6

2

BSR
REL

LOX 2
IMM
2
2
TXA
INH

STA '
3
EXT

IX'

4

EOR
3
EXT
4

ADC
EXT
3

,

BIT:
LDA

IX"

STA '
2
IX'

,

STA

2

1

IX'

4

ADC

3

ORA 5
IXl

2

ORA 4
IX'

3

ADD 4
EXT

3

ADD'
IXl

2

ADD 4
IX'

IX2

3

2

'
OIR

JSR b
EXT
3

2

LDX 3
OIR

LDX 4
3
EXT

3

IX2

2

STX 4
OIR

3

STX 5
EXT

3

STX 6
IX,

JSR

4

EOR,
2
IX'

ORA'
EXT

4

JSR
IX2

3
LOX

~,

~OOI-Z

<01'-

I

PD7
PA4
PA3

TCMP
PD5/SS

PA2

PD4/SCK
PD3/MOSI
PD2/MISO

PBl

PD1/TDO
pnO/RDI

PB2
PB3

PC1,

PB4

PC2

PBO

pea

NOTE: Bulk substrate tied to

Vss.

MOTOROLA MICROPROCESSOR DATA
3-898

MOTOROLA

• SEMICONDUCTOR
TECHNICAL DATA

MC68HC05C8
Technical Summary

8-Bit MicrocontroUer Unit
The MC68HC05C8 (HCMOS) microcontroller unit (MCU) is a member of the M68HC05 Family of
microcontrollers. This high-performance, low-power MCU has parallel I/O capability with pins programmableas input or output. This publication contains condensed information on the MCU; for
more detailed information, contact your local Motorola sales office.
The following block diagram depicts the hardware features; additional features available on the
MCU are as follows:
.
• On~Chip Oscillator with RC or Crystal/Ceramic Resonator Mask Options
• Memory-Mapped I/O
• 176 Bytes of On-Chip RAM
• 7740 Bytes of User ROM
• 24 Bidirectional I/O Lines and 7 Input-Only Lines
• Serial Communications InterfaGe(SCI) System
• Serial Peripheral Interface (SPI) System
• Self-Check Mode
• Power-Saving STOP, WAIT, and Data Retention Modes
• Single 3.0- to 5.5-Volt Supply (2-Volt .Data Retention Mode)
• Fully Static Operation
• 8 x 8 Unsigned Multiply Instruction

II

BLOCK DIAGRAM
OSCl

TCMP

t
TCAP

Internal
Processor
Clock

Timer
System

OSC2

It t
I

Internal

Oocill~"
~,,,reM"
and
Clock
+2

RESET
IRQ

• Y

Port

A
1/0
Lines

PAD
PAl
PA2
PA3
PA4
PA5
PA6
PA7

Accumulator
Port
A
Reg

Data
Dir r-<
Reg

CPU
Control

Index
Register

r-

Data
Dir
Reg

Port
C
Reg

Condition
Code
Register
CPU

Port

B
liO
Lines

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

Stack
Pointer
Port
B
Reg

Data
Dir
Reg

r--<

Program
Counter
High

10-

SCI

10-

SPI

ALU

Program
Counter
Low

T

Port D

~

PCO
PCl
PC2
PC3
PC4PC5
PC6
PC7

Port

C
1/0
Lines

P07
RDI (P~Q)
TDO(P01)
MISO(PD2)
MOSI (PD3)
SCK (PD4)
• SS (P05)

Baud Rate
Generator

1
1

7740 x 8
ROM

I

240 x 8
Self-Check
ROM

176x8
Static
RAM

I

Int!nal
Processor
Clock

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MICROPROCESSOR DATA

3..899

MC68HC05C8

pacitor as the frequency determining element. The
oscillator frequency is two times the internal bus rate.

SIGNAL DESCRIPTION
The signal descriptions of the MCU are discussed in
the following paragraphs.

RC Oscillator
With this option, a resistor is connected to the oscillator
pins as shown in Figure 1(d). The relationship between
Rand fosc is shown in Figure 2.

VOOANDVSS

Power is supplied to the microcontroller using these
two pins. VDD is the positive supply, and VSS is ground.
IRQ

This pin is a programmable option that provides two
different choices of interrupt triggering sensitivity. Refer
to INTERRUPTS for more detail.
OSC1,OSC2

II

These pins provide control input for an on-chip clock
oscillator circuit. A crystal, a ceramic resonator, a resistor/
capacitor combination, or an external signal connects to
these pins providing a system clock. A mask option selects either a crystal/ceramic resonator or a resistor/ca-

Crystal
The circuit shown in Figure 1(b) is recommended when
using a crystal. Using an external CMOS oscillator is recommended when crystals outside the specified ranges
are to be used. The crystal and components should be
mounted as close as possible to the input pins to minimize output distortion and start-up stabilization time. Refer to ELECTRICAL SPECIFICATIONS for VDD
specifications.
Ceramic Resonator
A ceramic resonator may be used in place of the crystal
in cost-sensitive applications. The circuit in Figure 1(b) is
Ceramic Resonator

Crystal
RSMAX

Co
Cl
COSCl
COSC2
Rp

2 MHz

4 MHz

Units

400

{}

RS Itypical!

5
0.000
15-40
15-:ll
10

75
7
0.012
15-:ll
15-25
10

pF

Co
Cl

M{}

~

4(

K

I'F
pF
pF

COSCl
COSC2
Rp
Q

2-4 MHz
10
40
4.3
30
30
1·10
1250

Units
{}

pF
pF
pF
pF
M{}

-

(a) Crystal/Ceramic Resonator Parameters

SC2
38

~

MCU
OSCl

39

OSC2
Rp

38

L

C
,RS,J 1
08C1,

39

Co

-38------~IDI~------3_9

~COSC2

(c) Equivalent Crystal Circuit

(b) Crystal/Ceramic Resonator
Oscillator Connections

R

(e) External Clock Source Connections
(For Crystal Mask Option Only)

(d) RC Oscillator Connections

Figure 1. Oscillator Connections

MOTOROLA MICROPROCESSOR DATA
3-900

MC68HC05C8

10

~

~

>c
~

......

1

(J

Io
~

0.5
~

0.2

"

O. 1

.~

o

0.05
0.02
0.0 1
1

10

20

50

100

200

500

1000

Resistance (kOl

Figure 2. Typical Frequency vs Resistance for
RC Oscillator Option Only
recommended when using a ceramic resonator. Figure
1(a) lists the recommended capacitance and resistance
values. The manufacturer of the resonator considered
should be consulted for specific information on resonator
operation.
External Clock
An external clock should be applied to the OSC1 input
with the OSC2 input not connected, as shown in Figure
1(e). This option may only be used with the crystal oscillator mask option.
INPUT CAPTURE (lCAP)
This pin controls the input capture feature for the onchip programmable timer.
OUTPUT COMPARE (TCMP)
This pin provides an output for the output compare
feature of the on-chip timer.

INPUT/OUTPUT PORT PROGRAMMING
Any port pin is programmable as either an input or an
output under software control df the corresponding data
direction register (DDR). Each port bit can be selected as
output or input by writing the corresponding bit in the
port DDR to a logic one for output and logic zero for input.
On reset, all DDRs are initialized to logic zero to put the
ports in the input mode. The port output registers are not
initialized on reset but may be written to before setting
the DDR bits to avoid undefined levels.
When programmed as outputs, the latched output data
is readable as input data regardless of the logic levels at
the output pin due to output loading. The latched output
data bit may always be written. Therefore, any write to
a port writes all of its data bits, even though the port DDR
is set to input. This port write may be used to initialize
the data registers and avoid undefined outputs. Refer to
Figure 3 for typical port circuitry and to Table 1 for a list
of the 1/0 pin functions.

RESET
This pin is used to reset the MCU and provide an orderly start-up procedure by pulling RESET low.

Table -1. 1/0 Pin Functions

INPUT/OUTPUT PORTS (PAO-PA7, PBO-PB7, PCO-PC7)
These 24 lines are arranged into three 8-bit ports (A,
B, and C). These ports are programmable as either inputs
or outputs under software control of the data direction
registers. Refer to PROGRAMMING for additional information.
FIXED INPUT PORT (PDO-PD5, PD7)
These seven lines comprise port D, a fixed input port.
All special functions that are enabled (SPI, SCI) affect this
port. Refer to PROGRAMMING for additional information.

PROGRAMMING
Inputloutput port programming, fixed input port programming, and serial port programming are discussed
in the following paragraphs.

RIW*

DDR

I/O Pin Functions

0

0

The 110 pin is in input mode. Data is
written into the output data latch.

0

1

Data is written into the output data latch
and output to the 110 pin.

1

0

The state of the 110 pin is read.

1

1

The 110 pin is in an output mode. The
output data latch is read.

*RNV is an internal Signal.

FIXED INPUT PORT PROGRAMMING
Port D is a fixed input port (PDO-PD5, PD7) that monitors
the external pins whenever the SCI or SPI is disabled.
After reset, all seven bits become valid inputs because
all special function drivers are disabled. For example,
with the SCI enabled, PDOand PD1 inputs will read zero.
With the SPI disabled, PD2 through PD5 will read the state
of the pin at the time of the read operation.

MOTOROLA MICROPROCESSOR DATA

3-901

II

MC68HC05C8

Internal

lID

MCU

Pin

Connections

Figure 3. Typical Port 1/0 Circuit

II

NOTE

ACCUMULATOR (A)
The accumulator is a general-purpose 8-bit register used
to hold operands and results of arithmetic calculations
or data manipulations.

Any unused inputs and 1/0 ports should be tied to
an appropriate logic level (e.g., either VDD or VSS).
SERIAL PORT (SCI AND SPI) PROGRAMMING
The SCI and SPI use the port D pins for their functions.
The SCI requires two pins (PDO-PD1) for its receive data
input (RDII and transmit data output (TDO), respectively.
The SPI function requires four of the pins (PD2-PD5) for
its serial data input/output (MISO), serial data ou~tl
input (MOSI), serial clock (SCK), and slave select (SS),
respectively.

A

INDEX REGISTER (X)
The index register is an 8-bit register used for the indexed addressing mode. It contains an 8-bit value that
may be added to an 8- or 16-bit immediate value to create
an effective address. The index register may also be used
as a temporary storage area.

MEMORY

x

The MCU is capable of addressing 8192 bytes of memory and I/O registers, as shown in Figure 4. The locations
consist of user ROM, user RAM, self-check ROM, control
registers, and 1/0. The user-defined reset and interrupt
vectors are located from $1 FF4 to $1 FFF.
The shared stack area is used during processing of an
interrupt or subroutine call to save the CPU state. The
stack pointer decrements during pushes and increments
during pulls. Refer to INTERRUPTS for additional information.
.

PROGRAM COUNTER (PC)
The program counter is a 13-bit register that contains
the address of the next byte to be fetched.
12
PC

STACK POINTER (SP)
NOTE
Using the stack area for data storage or temporary
work locations requires care to prevent it from being
overwritten due to stacking from an interrupt or
subroutine call.

REGISTERS
The MCU contains the registers described in the following paragraphs.

The stack pointer is a 13-bit register that contains the
address of the next free location on the stack. During an
MCU reset or the reset stack pointer (RSP) instruction,
the stack pointer is set to location $OOFF. The stack pointer
is then decremented as data is pushed .onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the seven most significant
bits are permanently set to 0000011.These seven bits are
appended to the six least significant register bits to produce an address within the range of $OOFF to $OOCO.
Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer

MOTOROLA MICROPROCESSOR DATA
3~902

MC68HC05C8

$0000

Port A Data Register

0000

0000
Ports
7 Bytes

1/0
32 Bytes
$OOlF
. $0020
User
ROM
48 Bytes
$OO4F
$0050

0031
0032

\

Unused
3 Bytes

\

RAM
176 Bytes

....

\

~--I--Stack
64 Bytes

$OOFF
$0100

0191
0192

Serial
Communications
Interface
5 Bytes

\

\
0255
0256

\

$lEFF
$lFOO

\

7935
7936

$05
$06

\

Unused
4 Bytes

$09
$OA

Serial Peripheral Status Register

SOB

Serial Communications Control Register 1

$OE

Serial CommuniCations Control Register 2

$OF

Serial Communications Status Register

$10

Serial Communications Data Register

$11

\

\
\

\

256 Bytes

\
\
\

8191

$12

Timer Status Register

$13
$14

Input Capture Low Register

$15

Output ~om~re High Register

$16

Output Compare Low Register

$17

Counter High Register

$18

Counter Low Register

$19

Alternate Counter High Register

$lA

Alternate Counter Low Register

$lB

\
\

Timer Control Register

Input Capture High Register

\

8179
8180

User
Vectors
12 Bytes

Unused

SOC

\

8175
8176

$07

$06

$00

Unused
4 Bytes

f------

Unused
Unused

Serial Peripheral Control Register

0031

Self-Check
Vectors

$lFF F

Port B Data Direction Register
Port C Data Direction Register

Serial Communications Baud Rate Register

\

Self Check

$lFF3
$lFF4

$03
$04

Serial Peripheral Data 1/0 Register

Timer
10 Bytes

\

User
ROM
7680 Bytes

$lFEF
$lFFO

Port 0 Fixed Input Register

\

\

$lFDF
$lFEO

$02

Port A Data Direction Register

Serial Peripheral
Interface
3 Bytes

\

$OOBF
$OOCO

$01

Port C Data Register

0079

0080

$00

Port B. Data Register

\
\
\

Unused

$lC

Unused

$10

Unused

$lE

Unused

$lF

Figure 4. Memory Map

wraps around and loses the previously stored information. A subroutine call occupies two locations on the. stack;
an interrupt uses five .Iocations.
12

7

Half Carry IH)

This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)

SP

When this bit is set, the timer and external interrupt is
masked (disabled). If an interrupt occurs while this bit is
set, the interrupt is latched and processed as soon as the
interrupt bit is cleared.

CONDITION CODE REGISTER leCR)

The CCR is a 5-bit register in which four bits are used
to indicate the results of the instruction just executed.
These bits can be individually tested by a program, and
specific actions can be taken as a result of their state.
Each bit is explained in the following paragraphs.

Negative IN)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was negative
(bit 7 in the result is a logic one).
Zero

CCR

Ii)

When set, this bit indicates that the result of the last
arithmetic, logical, or data manipulation was zero.

MOTOROLA MICROPROCESSOR DATA
3-903

II

MC68HC05C8

Carry/Borrow (C)

SCI -

Transmission test; checks RORF, TORE, TC,
and FE flags
SPI - Transmission test; checks SPIF, WCOl, and
MOOF flags
Self-check results (using the LEOs as monitors) are
shown in Table 2. The following subroutines are available
to the user and do not require any external hardware.

When set, this bit indicates that a carry or'borrow out
of the arithmetic logical unit (ALU) occurred during the
last arithmetic operation~ This bit also affected during
bit test and branch instructions and during shifts and
rotates.

,S

TIMER TEST SUBROUTINE
This subroutine returns with the Z bit cleared if any
error is detected; otherwise, the Z bit is set. The timer
test subroutine is called at location $1 FOE. The output
compare register is first set to the current timer state.
B.ecause the timer is free running and has only a divideby-four prescaler, each timer count cannot be tested. The
test reads the timer once every 10 counts (40 cycles) and
checks for correct counting. The test tracks the counter
until the timer wraps around, triggering the output compare flag in the timer status register. RAM locations $0050
and $0051 are overwritten. Upon return to the user's program, X=40. If the test passed, A=O.

SELF-CHECK

I

The self-check capability provides the ability to determine if the device is functional. Self-check is performed
using the circuit shown in Figure 5. Port C pins PCO-PC3
are monitored for the self-check results. After reset, the
following seven tests are performed automatically:
I/O - Exercise of ports A, B, and C
RAM - Counter test for each RAM byte
ROM - Exclusive OR with odd ones parity result
Timer - Tracks counter register and checks OCF flag
Interrupts ~ Tests external, timer, SCI and SPI interrupts

RESET

10k

47~
2N3904

..1

+5V
10k

RESET

1

iRO

10k
VOO

NC

OSCl

40

+5V

TCAP

10M

MCU

~

PA7

r- ~

PA6

6
7

TCMP
PA4
P05/SS

~

PA3
PA2

11

36

PD4/SCK
P03/MOSI

PAl

P02/MISO

2L

12

r- ~
14

'*

15

PBO

PCO

PBl

PCl

PB2

PC2

32

30

29
28
27
26
25

PC3

~

PB4

PC4

--1l

PB5

PC5

PB6'

PC6

PB7

PC7 21

19

4MHz

I 'rl

F

(See Note)

I

'::"

+5V

i:

4.7K

~

2N3904

10 k

31

PB3

18

0

33 1M

PAO
PDQ/ROI

I

34

POl/TOO

10k

I

38

P07

PA5

~
10

OSC2

'~-:(
':'

39

'::"

37

:1'9

I

- '!-

~
""

~
23

22

VSS

...L20
NOTE: The RC Oscillator Option may also be used in this circuit.

Figure 5. Self-Check Circuit Schematic Diagram

MOTOROLA MICROPROCESSOR DATA
3-904

'::"

~

1k
+5V

1k
1k

'!....

1k

MC68HC05C8

Table 2. SeH-Check Results

PC3 PC2 PC1 PCO

EXTERNAL RESET INPUT
The MCU is reset when a logic zero is applied to the
RESET input for a period of one and one-half machine
cycles (tcyel.

Remarks

Bad 1/0

1

0

0

1

1

0

1

0

Bad RAM

1

0

1

1

Bad Timer

1

1

0

0

Bad SCI

1

1

0

1

Bad ROM

1

1

1

0

Bad SPI

1

1

1

Bad Interrupts or IRQ Request

1

Flashing
All Others

o indicates lED is on;

INTERRUPTS
The MCU can be interrupted five different ways: the
four maskable hardware interrupts (IRQ, SPI, SCI, and
timer) and the nonmaskable software interrupt instruction (SWI).
Interrupts cause the processor to save register contents
on the stack and to set the interrupt mask (I bit) to prevent
additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal
processing to resume. The stacking order is shown in
Figure 6.
Unlike RESET, hardware interrupts do not cause the
current instruction execution to be halted but are considered pending until the current instruction is complete.

Good Device
Bad Device, Bad Port C, etc.
1 indicates lED is off.

ROM CHECKSUM SUBROUTINE
This subroutine returns with the Z bit cleared if any
error is detected; otherwise, the Z bit is set. The ROM
checksum subroutine is called at location $1F93 with RAM
location $0053 equal to $01 and A=O. A short routine is
set up and executed in RAM to compute a checksum of
the entire ROM pattern. RAM locations $0050 through
$0053 are overwritten. Upon return to the user's program,
X = O. If the test passed, A = O.

NOTE
The current instruction is the one already fetched
and being operated on.
When the current instruction is complete, the processor
checks all pending hardware interrupts. If unmasked (I
bit clear) and if the corresponding interrupt enable bit is
set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
If both an external interrupt and a timer interrupt are
pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the
same as any other instruction, regardles's of the I-bit state.
Refer to Figure 7 for the reset and interrupt instruction
processing sequence.

RESETS
The MCU can be reset two ways: by initial power-up
and by the external reset input (RESET). The RESET inE!!!
consists mainly of a Schmitt trigger that senses the RESET line logic level.
POWER-ON RESET (POR)
An internal reset is generated on power-up to allow
the internal clock generator to stabilize. The power-on
reset is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage.
There is a 4064 internal processor clock cyc~) delay
after the oscillator becomes active. If the RESET pin is
low at the end of 40~, the MCU will remain in the
reset condition until RESET goes high.

TIMER INTERRUPT
There are three different timer.interrupt flags that cause
a timer interrupt whenever they are set and enabled. The
interrupt flags are in the timer status register (TSR), and
the enable bits are in the timer control register (TCR).
Refer to TIMER for more information.

o

7

Increasing Memory
Addresses

1i
U
R
N

111 11 1 Condition Code Register
Accumulator
Index Register

01 0Jo(

PCH
PCl

Unstack

Stack
I

II

Decreasing Memory
Addresses

P
T

NOTE: Since the Stack Pointer decrements during pushes, the PCl is
stacked first, followed by PCH, etc. Pulling from the stack is
in the reverse order.
Figure 6. Interrupt Stacking Order

MOTOROLA MICROPROCESSOR DATA·

3-905

II

MC68HC05C8

y

Clear iRQ
Request
latch

I
load PC from:
SWI: $1 FFC-$1 FFD
IRQ: $1FFA-$1FFS'
Timer: $1 FF8-$1 FF9
SCI: $1 FF6-$1 FF7
SPI: $1 FF4-$1 FF5

Complete
Interrupt
Routine
and Execute
RTI

Figure 7, Reset and Interrupt Processing Flowchart

MOTOROLA ·MICROPROCESSOR· DATA
3-906

MC68HC05C8

EXTERNAL INTERRUPT
If the interrupt mask bit (I bit) of the CCR is set, all
interrupts are disabled. Clearing the I bit enables the ~x~
ternal interrupt. The external interrupt is internally ~­
chronized and then latched on the falling edge of IRQ.
The action of the external interrupt is identical to the timer
interrupt with the exception that ,the interrupt, request
input at IRQ is latched internally and the service routine
address is specified by the contents of $1 FFA and $1 FFB.
Either a level-sensitive and edge-sensitive trigger, or
an edge-sensitive-only trigger are available as a mask
option. Figure 8 shows both a functional internal diagram
and a mode timing diagram for the interrupt line. The
timing diagram shows two treatments of the interrupt
line to the processor. The first method shows a single
pulse on the interrupt line spaced far enough apart to be
serviced. The minimum time between pulses is 'a function
of the length of the interrupt service. Once a pulse occurs,
the next pulse should not occur until an RTI occurs. This

time (tILlL) is obtained by adding 21 instruction cycles to
the total number of cycles it takes to complete the service
routine (not including the RTI instruction). The second
method shows many interrupt lines "wire-ORed", to form
the interrupts at the processor. If the interrupt line reo'
mains low after servicing an interrupt, then the next interrupt is recognized;

NOTE
The internal interrupt iatch is cleared in the first part
of the interrupt service routine;'therefore, one ex~
ter'nal interrupt pulse could be latched and serviced
as soon as the I bit is cleared.
SOFTWARE INTERRUPT,(SWI)
TheSWI is an executable instruction that is executed
regardless of the state of the I bit in the CCA. If the I bit
is zero, SWI executes after the other interrupts. The SWI

Leilel- Sensitive Trigger
Mask Option

VDD ,.--_ _..,
D

External
Interrupt
Request

O~---_I

Interrupt Pin -'----4I-------4V C
I Bit (CC)

Power-On' Reset
'External Reset
, Externl,ll Interrupt
Being Serviced (Vector Fetch)
(a) Interrupt Internal Function Diag~am

U

nm~tlLIH

I..
TIm!

tILlL----~·~1

---r=- tILlH----.f

•
IROn

Edge-SenIitiYe Trigger CondItion
The minimum pulse width (\ill HI is either
125 nsIVOO=5 VI or 250 ns 1VOO=3 V).
The period tlLIL should not be less, than
the number of, tcvc cycles it takes to execute the interrupt S8f'Vice routine plus 21
tcyc cycles.
Lwel-Senlidye Trigger CondIdon
If after servicing an interrupt the iliO r&mains lOw, then the next interrUpt is

recognized .

r

L...-_ _ _ _.....I

Normally
Used with

Wire-ORed
Connection

(M:I...___________........r
(b) Interrupt Mode Diagram

Figure 8. External Interrupt

MOTOROLA 'MICROPROCESSOR DATA
3-907

II

MC68HC05C8

operation is similar to the hardware interrupts. The interrupt service routine address . is specified by the contents of memory locations $1 FFC and $1 FFD.

slave mode when the STOP instruction is executed,. the
slave SPI continues to operate and can still accept data
and clock informatiohinaddition to transmitting its own
data back to a master device.
At the end of a. possible transmission with a slave SPI
in the STOP mode, no flags are set until a low on the IRQ
pin wakes up theMCU. Ca'ution should be observed when
operating the SPI as a stave. during the STOP mode because the protective circuitry (WCOL, MODF, etc.) is in.
active.

SCI INTJ:RRUPTS
An interrupt in the SCI occurs when one ofthe interrupt
flag bits in the serial communications status register is
set, provided the I bit in the CCR is clear and the enable
bit in the serial communications control register 2 is set.
Software in the serial interrupt service routine must determine the cause and priority 'of the SCI. )nterrupt by
examining the interrupt flags and status bits in the SCI
status register.
SPIINTERRUPTS

II

An interrupt in the SPI occurs when one of the interrupt
flag bits in the serial peripheral status register is set,
provided the I bit in the CCR is clear and the enable bit
in the serial peripheral control register is set. Software
in the serial peripheral interrupt service routine must determine the cause and priority of the SPI interrupt by
examining the interrupt flag bits in the SPI status register.

WAIT
The.WAIT instruction places the MCU in a low-power
consumption mode, but the WAIT mode consumes more
power than the STOP mode. All CPU action is suspended,
but the timer, SCI, and SPI remain active (refer to Figure
10). An interrupt from the timer, SCI, or SPI can cause
the MCU to exit the WAIT mode.
During the WAIT mode, the I bit in the CCR is cleared
to enable interrupts. All other registers, memory, and
input/output lines remain in their previous state. The timer

LOW-POWER MODES
STOP
The STOP instruction places the MCU in its lowest power
consumption mode. In the STOP mode, the internal oscillator is turned off, halting all internal processing including timer, SCI, and SPI operation (refer to Figure 9).
During the STOP mode, the TCR bits are altered to
remove any pending timer interrupt request and to disable any further timer interrupts. The timer presci:lIeris
cleared. The I bit in the CCR is cleared to enable external
interrupts. All other registers and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of the STOP mode only by an
external interrupt or reset.

Stop Oscillator
And All Clocks
Clear I Bit

SCI during STOP Mode
When the MCU enters the STOP mode, the baud rate
generator stops, halting all SCI activity. If the STOP instruction is executed during a transmitter transfer, that
transfer is halted. If a low input to the IRQ pin is used to
exit STOP mode, the transfer resumes. If the SCI receiver
is receiving data and the STOP mode is entered, received
data sampling stops because the baud rate generator
stops, and all subsequent data is lost. For these reasons,
all SCI transfers should be in the idle state when the STOP
instruction is executed.
SPI during Stop Mode
When the MCU enters the STOP mode, the baud rate
generator stops, terminating all master mode SPI operations. If the STOP instruction is executed during an SPI
transfer, that transfer halts until the MCU exits the STOP
mode by a low signal on the IRQ pin. If reset is used to
exit the STOP mode, then the SPI control and status bits
are cleared, and the SPI is disabled. If the MCU is in thE\!

Yes

(1) Fetch Reset Vector or
(2) Service Interrupt
a. Stack
b. Set I Bit
C. Vector to Interrupt
Routine

Figure 9. STOP Function Flowchart

MOTOROLA MICROPROCESSOR .DATA
3-908

MC68HC05C8

may be enabled to allow a periodic exit from the WAIT
mode.

DATA RETENTION MODE
The contents of RAM and CPU registers are retained
at supply voltages as low as 2.0 Vdc. This is called the
data retention mode where the data is held, but the device
is not guaranteed to operate. The MCU should be in RESET
during data retention mode.

several microseconds to many seconds. Refer to Figure
11 for a timer block diagram .
. Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two
registers. These registers contain the high and low byte
of that functional segment. Generally, accessing the low
byte of a specific timer function allows full control of that
function; however, an access of the high byte inhibits
that specific timer function until the low byte is also accessed.

TIMER

NOTE

The timer consists of a 16-bit, software-programmable
counter driven by a fixed divide-by-four prescaler. This
timer can be used for many purposes, including input
waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from

The I bit in the CCR should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does
not occur.

Wait

I

Oscillator Active
Timer. SCI. And SPI
Clocks Active
Processor Clocks Stopped

(1) Fetch Reset Vector or
(2) Service Interrupt
B. Stack
b. Set I Bit
c. Vector to Interrupt'
Routine

Figure 10; WAIT Function Flowchart

MOTOROLA MICROPROCESSOR DATA
3-909

MC68HC05C8'

High

Low

Byte

Byte

High
Byte

r-I-.,---,-L...,

$16
$17

$14
$15

L..:.:.::l2;:':::::".J

$1A
L:-;.;~~...I

I

$lB

a

....----10
.---~-----------------+----~--~~~CLK

Timer
Status
Reg,

Output
Level
Reg,

.--~.,...-L--.---lII~

Timer

C

RESe'f

Control
Reg,

$.12

Output Edge
Level
Input
(TCMP) (TCAP)

Figure 11. Timer Block Diagram

COUNTER
The key element in the programmable timer is a 16-,
bit, free-running counter or counter register, preceded by
a prescaler that divides the internal pr'ocessor clock by
four. The prescaler gives the timer a resolution of 2.0
microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock. Software can read the counter at any
time without affecting its value.
The double-byte, free-running counter can be read from
either of two locations, $18-$19 (counter register) or
$1A-$18 (counter alternate register). A read from only
the least significant byte (LS8) ofthefree-running counter
($19, $1 8) receives the count value at the time of the read.
If a read of the free-running counter or counter alternate
register first addresses the most significant byte (MS8)
($18, $1A), the LS8 ($19, $18) is transferred to a;buffer.

This buffer value remains fixed after the first MS8 read,
even if the user reads the MS8 several times. This buffer
is accessed when r~ading the free-running counter or
counter alternate register LS8 ($19 or $18) and, thus,
completes a read sequence of the total counter value. In
reading either the free-running counter or counter alternate register, if the MS8 is read, the LS8 must also be
read to complete th,e sequence.
The counter alternate register differs from the counter
register in one respect: a read of the counter register MS8
can clear the timer overflow flag (TOF). Therefore, the
counter alternate register can be read at any time without
the possibility of missing timer overflow interrupts due
to clearing of the TOF.
The free-running counter is configured to $FFFC during
reset and is always a read-only register. During a poweron reset; th~ ,?ounter is also preset to $FFFC and begins

MOTOROLA MICROPROCESSOR DATA
3-910

MC68HC05C8

running after the oscillator start-up delay. Because the
free-running counter is 16 bits preceded by a fixed divideby-four prescaler, the value in the free-running counter
repeats every 262,144 internal bus clock cycles. When the
counter rolls over from $FFFF to $0000, the TOF bit is set.
An interrupt can also be enabled when counter rollover
occurs by setting its interrupt enable bit (TOlE).

OUTPUT COMPARE REGISTER
The 16-bit output compare register.is made up of two
8-bit registers at locations $16 (MSB) and $17 (LSB). The
output compare register is used for several purposes,
such as indicating when a period of time has elapsed. All
bits are readable and writable and are not altered by the
timer hardware or reset. If the compare function is not
needed, the two bytes of the output compare register can
be used as storage locations.
The output compare register contents are compared
with the contents of the free-running counter continually,
and if a match is found, the corresponding output compare flag (OCF) bit is set and the corresponding output
level (OLCL) bit is clocked to an output level register. The
output compare register values and the output level bit
should be changed after each successful comparison to
establish a new elapsed timeout. An interrupt can also
accompany a successful output compare provided the
corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare
register containing the MSB ($16), the output compare
function is inhibited until the LSB ($17) is also written.
The user must write both bytes (locations) if the MSB is
written first. A write made only to the LSB ($17) will not
inhibit the compare function. The free-running counter is
updated every four internal bus clock cycles. The minimum time required to update the output compare reg~
ister is a function of the program rather than the internal
hardware.
The processor can write to either byte of the output
compare register without affecting the other byte. The
output level (OLVL) bit is clocked to the output level register regardless of whether the output compare flag (OCF)
is set or clear.
INPUT CAPTURE REGISTER
Two 8-bit registers, which make up the 16-bit input
capture register, are read-only and are used to latch the
value of the free-running counter after the corresponding
input capture edge detector senses a defined transition.
The level transition which triggers the counter transfer is
defined by the corresponding input edge bit (lEDG). Reset
does not affect the contents of the input capture register.
The result obtained by an input capture will be one
more than the value of the free-running counter on the
rising edge of the internal bus clock preceding the ex~
ternal transition. This delay is required for internal synchronization. Resolution is 'one count ofthefree-running
counter, which is four internal bus clock cycles.
The free-running counter contents are transferred to
the input capture register on each proper signal transition
regardless of whether the input capture flag (ICF) is set
or clear. The input capture register always contains the

free-running counter value that corresponds to the most
recent Input capture.
After a read of the input capture register ($14) MSB,
the counter transfer is inhibited until the LSB ($15) is also
read. This characteristic causes the time used in the input
capture software routine and its interaction with the main
program to determine the minimum pulse. period.
A read of the input capture register LSB ($15) does not
inhibitthe free-running counter transfer since they occur
on opposite edges of the internal b,us clock.

TIMER CONTROL REGISTER (TCR) $12
The TCR is a read/write register containing five control
bits. Three bits control interrupts associated with the timer
status register flags ICF, OCF,and TOF.

I ICIE I OCIE -,

TOlE

RESET:

IEDG

OLVL

u

o

ICIE - Input Capture Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
OCIE---, Output Compare Interrupt Enable
1 = Interrupt enabled
o= Interrupt disabled
TOlE - Timer Overflow Interrupt Enable
1 = Interrupt enabled
0= Interrupt disabled
IEDG - Input Edge
Value of input edge determines which level transition
on TCAP pin will trigger free-running counter transfer
to the input capture register
1 = Positive edge
0= Negative edge
Reset does not affect te IEDG bit (U = unaffected).
OLVL - Output Level
Value of output level is clocked into output level register by t/:le next successful output compare and will
appear on the TCMP pin
1 = High output
0= Low output
Bits 2, 3, and 4 - Not used
Always read zero

TIMER STATUS.REGISTER (TSR) $13
The TSR is a read-only register containing three status
flag bits.

I

ICF

I OCF

TOF

U

U

RESET:

U

ICF - Input Capture Flag
1 = Flag set when selected polarity edge is sensed by
input capture edge detector
0= Flag cleared when TSR and input capture low register ($15) are accessed

MOTOROLA MICROPROCESSOR DATA
3~911

II

MC68HC05C8

OCF - Output Compare Flag
1 = Flag setwhen output compare register contents
match the free-running counter contents .
0= Flag cleared when TSR and output compare low
register ($17) are accessed
TOF - Timer Overflow Flag
1 = Flag set when free-running counter transition from
$FFFF to $0000 occurs
0= Flag cleared when TSR and counter iow register
($19) are accessed
Bits 0-4 - Not used
Always read zero

I

Accessing the timer status register satisfies the first
condition required to clear status bits. The remaining step
is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow
function and reading the free-running counter at random
times to measure an elapsed time. Without incorporating
the proper precautions into software, the timer overflow
flag could unintentionally be cleared if:
1) The timer status register is read or written when
TOF is set, and
2) The LSB of the free-running counter is read but not
for the purpose of servicing the flag.
The counter alternate register at address $1A and $1 B
contains the same value as the free~running counter (at
address $18 and $19); therefore, this alternate register
can be read at any time without affecting the timer overflow flag in the timer status register.

TIMER DURING WAIT MODE
The CPU clock halts during the WAIT mode, but the
timer remains active. An interrupt from the timer causes
the processor to exit the WAIT mode.

TIMER DURING STOP MODE
In the STOP mode, the timer stops counting and holds
the last count value if STOP is exited by an interrupt. If
RESET is used, the counter is forced to $FFFC. During
STOP, if at least one valid input capture edge occurs at
the TCAP pin, the input capture detect circuit is armed.
This does not set any timer flags nor wake up the MCU,
but when the MCU does wake up, there is an active input
capture flag and data from the first valid edge that occurred during the STOP mode. If RESET is used to exit
STOP mode, then no input capture flag or data remains,
even if a valid input capture edge occurred.

SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous SCI is provided with a
standard NRZ format and a variety bf baud rates. The SCI
transmitter and receiver are functionally independent but
use the same data format and baud rate. The terms baud'
and bit rate are used synonymously in the following description.

SCI TWO-WIRE SYSTEM FEATURES
• $tandard NRZ (mark/space) f()rmat
• Advanced error detection method includes noise detection for noise duration of up to one-sixteenth bit
time
.
• Full-duplex operation (simultaneous transmit and receive)
• Software programmable for one of 32 different baud
rates
• Software-selectable word length (eight- or nine-bit
words)
•. Separate transmitter and receiver enable bits
• SCI may be interrupt driven
• Four separate in~errupt conditions

SCI RECEIVER FEATURES
•
•
•
•
•
•

Receiver wake-up function (idle
Idle line detect
Framing error detect
Noise detect
Overrun deteCt
Receiver data register full flag

or address bit)

SCI TRANSMITTER FEATURES
• Transmit data register empty flag
• Transmit complete flag
• Break send
Any SCI two-wire system requires receive data in (ROI)
and transmit data out (TOO).

DATA FORMAT
Receive data in (ROI) or transmit data out (TOO) is the
serial data presented between the internal data bus and
the output pin (TOO) and between the input pin (ROil and
the internal data bus. Data format· is as shown for the
NRZ in Figure 12.
Control bit "M"
Selects 8 or 9 bit data

o

2

3

4,

5

6

7

I,
Idle Line

S
8

0

8

*
S

• Stop bit is always high.

0

p

Figure 12. Data Format

MOTOROLA MICROPROCESSOR DATA

3-912

I C
S

MC68HC05C8

WAKE-UP FEATURE
In atypical multiprocessor configuration, the software
protocol will usually identify the addressee(s) at the beginning of the message. To permit uninterested MPUs to
ignore the remainder of the message, a wake-up feature
is included, whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until its data line
returns to the idle state. An SCI receiver is re-enabled by
an idle string of at least ten (or eleven) consecutive ones.
Software for the transmitter must provide forthe required
idle string between consecutive messages and prevent
it from occurring within messages.
A second wake-up method is available in which sleeping SCI receivers can be awakened by a logic one in the
high-order bit of a received character.
RECEIVE DATA IN,
Receive data in (ROil is the serial data which is presented from the input pin via the SCI to the receive data
register (ROR). While waiting for a start bit, the receiver
samples the input at a rate 16 times higher than the set
baud rate. This increased rate is referred to as the RT
rate. When the input (idle) line is detected low, it is tested
for three more sample times. If at least two of these three
samples detect a logic low, a valid start bit is assumed
to be detected. If in two or more samples, a logic high is
detected, the line is assumed to be idle. The receive clock
generator is controlled by the baud rate register (see Figure 13); however, the SCI is synchronized by the start bit
independent of the transmitter. Once a valid start bit is
detected, the start bit, each data bit, and the stop bit are
each sampled three times. The value of the bit is determined by voting logic, which takes the value of a majority
of samples. A noise flag is set when all three samples on
a valid start bit, data bit, or stop bit do not agree. A noise
flag is also set when the start verification samples do not
agree.
START BIT DETECTION FOLLOWING A FRAMING ERROR
Ifthere has been a framing error (FE) without detection
of a break (10 zeros for 8-bit format or 11 zeros for a 9bit format), the circuit continues to operate as if there
actually were a stop bit, and the start edge will be placed
artificially. The last bit received in the data shift register
is inverted to a logic one, and the three logic-one start
qualifiers are forced into the sample shift register during
the interval when detection of a start bit is anticipated;
therefore, the start bit will be accepted no sooner than it
is anticipated.
If the receiver detects that a break (RORF = 1, FE = 1,
receiver data register = $00) produced the framing error,
the start bit will not be artificially induced, and the receiver must actually receive a logic one before start.
TRANSMIT DATA OUT
Transmit data out (TOO) is the serial data presented
from the transmit data register (TOR) via the SCI to the
output pin. The transmitter generates a bit time by using
a derivative of the RT clock, producing a transmission
rate equal to one-sixteenth that of the receiver sample
clock.

FUNCTIONAL DESCRIPTION
A block diagram of the SCI is shown in Figure 13. The
user has option bits in the serial communications control
register 1 (SCCR1) to determine the SCI wake-up method
and data word length. Serial communications control
register 2 (SCCR2) provides control bits that individually
enable/disable the transmitter or receiver, enable system
interrupts, and provide wake-up enable, and send break
code bits. The baud rate register bits allow the user to
select different baud rates, which are used as the rate
control for the transmitter and receiver.
Data transmission is initiated by a write to the serial
communications data register (SCDAT). Provided the
transmitter is enabled, data stored in the SCDAT is transferred to the transmit data shift register. This data transfer
sets the SCI status register (SCSR) transmit data register
empty (TDRE) bit and generates an interrupt if the transmit interrupt.is enabled. Data transfer to the transmit data
shift register is synchronized with the bit rate clock. All
data is transmitted LSB first. Upon completion of data
transmission, the transmission complete (TC) bit is set
(provided no pending data, preamble, or break code is
sent), and an interrupt is generated if the transmit complete interrupt 'is enabled. If the transmitter is disabled,
and the data, preamble, or break code has been sent, the
TC bit will also be set, which will also generate an interrupt if the TCIE bit is set. If the transmitter is disabled in
the middle of a transmission, that character will be completed before the transmitter gives up control of the TOO
pin.
When the SCDAT is read, it contains the last data byte
received, provided that the receiver is enabled. The SCSR
receive data register full (RDRF) bit is set to indicate that
a data byte is transferred from the input serial shift register to the SCDAT, which can cause an interrupt if the
receiver interrupt is enabled. Data transfer from the input
serial shift register to the SCOAT is synchronized by the
receiver bit rate clock. The SCSR overrun (OR), noise flag
(NF), or FE bits are set if data reception errors occur.
An idle line interrupt is generated if the idle line interrupt is enabled and the SCSR IOLE bit (which detects idle
line transmission) is set. This allows a receiver that is not
in the wake-up mode to detect the end of a message, the
preamble of a new message, or to resynchronize with
the transmitter. A valid character must be received before
the idle line condition for the IOLE bit to be set and for
an idle line interrupt to be generated.
REGISTERS
There are five registers used in the SCI; 11)8 internal
configuration of these registers is discussed in the following paragraphs.
Serial Communications Data Register (SCDAT) $11
The SCOAT is a read/write register used to receive and
transmit SCI data.
7

6

5

0

I SCD7 I SCD6 I SCD5 I SCD4
RESET:
U

u

u

MOTOROLA MICROPROCESSOR DATA
3-913

u

SCD3

SCD2

SCDt

I SCDO I

u

u

u

u

II

MC68HC05C8

As shown in Figure 13, SCDAT functions as tw'o separate registers. The transmit data register (TOR) provides
the parallel interface from the internal data bus to the

transmit shift register. The receive data register (RDR)
provides the interface from the receive shift register to
the internal data bus.

I
Internal
Processor
Clock

·$00

$OE

NOTE: The Serial Communications Data Register (SCDAT) is controlled by the internal R/W signal. It is the transmit data register when
written and receive data register when read.

Figure 13. SCI Block Diagram

MOTOROLA MICROPROCESSOR DATA
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MC68HC05C8

Serial Communications Control Register 1 (SCCR1) $OE
The SCCR1 provides control bits that determine word
length and select the wake-up method.
3

7
I

RS

I

RESET:
U

TS

M

U

U

I

WAKE

I·

1

U

RS- Receive Data Bit S
R8 bit provides storage location for the ninth biiin the
receive data byte (if M = 1 ) . '
T8 - Transmit Data Bit 8
T8 bit provides storage location for the ninth bit in the
transmit data byte (if M = 1).
'
M - SCI Character Word Length
1 ~ one start bit, nine data bits, one stop bit
'0 ~ one start bit, eight data bits, one stop bit
WAKE ~ Wake-Up Select
Wake bit selects the receiver wake-up method.
1 = Address bit (most significant bit)
0= Idle line condition
Bits 0-2, and 5 ~Notused
Can read either one or zero
The address bit is dependent on both the wake-,bit and
the M-bit level. Additionally, the receiver does not use
the wake-up feature unless the RWU control bit in 'SCCR2
is set.
Wake

M

Receiver Wake-Up

0

X

Detection of an idle line allows the next data
byte received to cause the receive data register to fill and produce an RDRF flag.

1

0

Detection of a received one in the eighth
data bit allows an RDRF flag and associated
error flags.

1

Detection of a received one in the ninth data
bit allows an RDRF flag and associated error
flags.

1

I

ILiE - Idle Line Interrut Enable
1 = SCI interrupt enabled
0= Idle interrupt disabled
TE - Transmit Enable
1 = Transmit shift register output is applied to the TDO
line. Depending upon the SCCRl M bit, a preamble of 10 (M = 0) or 11 (M= 1) consecutive ones is
transmitted.
0= Transmitter disabled after last byte is loaded in
the SCDAT and TDRE is set. After last byte is
transmitted, TDO line becomes a high-impedance
line.
RE - Receive Enable
1 = Receiver shift register input is applied to the RDI
line.
0= Receiver disabled and RDRF, IDLE, OR, NF, and
FE status bits are inhibited.
RWU - Receiver Wake-Up
1 = Places receiver in sleep mode and enableswake.
up function
0= Wake-up function disabled after receiving data
word with MSB set (if WAKE=l)
.
Wake-up function also disabled after receiving 10
(M =()) or 11 (M = 1) consecutiveones.(jfWAKE=O)
SBK -'-Send Break
1 =' Transmitter continually sends blocks of zeros (sets
of 10 or 11) until cleared. Upon completion of
break code, transmitter sends one high bit for recognition of valid start bit.
O=Transmitter sends 10 (M=O) or 11 (M=1) zeros
then reverts to an idle state or continues sending
data. If transmitter is empty and idle, setting and
clearing the SBK bit may queue up to two character times of break because the first break transfers immediately to the shift register, and the
second is queued into the parallel transmit buffer.
Serial Communications Status Register (SCSR) $10
The SCSR provides inputs to the SCI interrupt logic
circuits. Noise flag and framing error bits are also contained in the SCSR.

Serial Communications Control Register 2 (SCCR2) $OF
The SCCR2 provides control of individual SCI functions
such as interrupts, transmit/receive enabling, receiver
wake-up, and break code.

I

TIE

1

TCIE

RIE

IUE

TE

RE

RWU

RESET:

o

TIE - Transmit Interrupt Enable
1 = SCI interrupt enabled
O=TDRE interrupt disabled
TCIE - Transmit Complete Interrupt Enable
1 = SCI interrupt enabled
0= TC interrupt disabled
RIE - Receive Interrupt Enable
1 = SCI. interrupt enabled
0= RDRF and OR interrupts disabled

SBK

1

TDRE

1

TC

RDRF

IDLE

OR

NF

FE

RESET:
1

TDRE - Transmit Data Register (TDR) Empty
1 = TDR contents transferred to the transmit data shift
register
0= TDR still contains data. TDRE is cleared by reading
the SCSR (with TDRE = 1), followed by a write to
the TDR.
Te - Transmit Complete
1 = Indicates end of data frame, preamble, or break
condition has occurred
, O=TC bit cleared by reading the SCSR (with TC= 1), .
followed by a write to the TDR
RDRF - Receive Data Register (RDR) Full
1 = Receive data shift register contents transferred to
theRDR

MOTOROLA MICROPROCESSOR DATA
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II

MC68HC05C8

I

0= Receive data shift register transfer did not occur.
RDRF is cleared by reading the SCSR (with
RDRF = 1) folfowed by a read of the RDR
IDLE - Idle Line Detect
1 = Indicates receiver has detected an idle line
0= IDLE is cleared by reading the SCSR (with IDLE = 1),
folfowed by a read of the RDR. Once IDLE is
cleared, IDLE cannot be set until RDI line becomes
active and idle again.
OR - Overrun Error
1 = Indicates receive data shift register data is sent to
a fulf RDR (RDRF = 1). Data causing the overrun
is lost, and RDR data is not disturbed.
0= OR is cleared by reading the SCSR (with OR = 1),
folfowed by a read of the RDR.
NF - Noise Flag
1 = Indicates noise is present on the receive bits, including the start and stop bits. NF is not set until
RDRF= 1.
0= NF is cleared by reading the SCSR (with NF = 1),
folfowed by a read of the RDR.
FE - Framing Error
1:;: Indicates stop bit not detected in received data
character. FE is set the same time RDRF is set. If
received byte causes both framing and overrun
errors, processor will only recognize the overrun
error. Further data transfer into the RDR is inhibited until FE is cleared.
0= NF is cleared by reading the SCSR (with FE = 1),
followed by a read of the RDR.
Bit 0 - Not used
Can read, either one or zero

SCPO - SCI Prescaler Bit 0
SCP1 - SCI Prescaler Bit 1
Two prescaler bits are used to increase the range of
standard baud rates controlled by the SCRO-SCR2
bits. Prescaler internal processor clock division versus bit leve,ls are listed in Table 3.
SCRO - SCI Baud Rate Bit 0
SCR1 - SCI Baud Rate Bit 1
SCR2 - SCI Baud Rate Bit 2
Three baud rate bits are used to select the baud rates
of the SCI transmitter and SCI receiver. Baud rates
versus bit levels are fisted in Table 4.
Tables 3 and 4 tabulate the divide chain used to obtain
the baud rate clock (transmit clock). The actual divider
chain is controlled by the combined SCPO-SCP1 and SCROSCR2 bits in the baud rate register. Alf divided frequencies shown in Table 3 represent the final baud rate reSUlting from the internal processor clock division shown
in the divided-by column only (prescaler division only).
Table 4 lists the prescaler output divided by the action
of the SCI select bits (SCRO-SCR2). For example, assume
that a 9600-Hz baud rate is required with 2.4576-MHz
external crystal. In this case, the prescaler bits (SCPOSCP1) could be configured as a divide-by-one or a divideby-four. If a divide-by-four prescaler is used, then the
SCRO-SCR2 bits must be configured as, a divide-by-two.
Using the same crystal, the 9600 baud rate can be obtained with a prescaler divide-by-one and the SCRO-SCR2
bits configured for a divide-by-eight.

a

SERIAL PERIPHERAL INTERFACE
Baud Rate Register $OD

The serial peripheral interface (SPI) is an interface built
into the MCU which allows several MCUs or MCUs plus
peripherals to be interconnected within the same black
box. In the SPI format, the clock is not included in the
data stream and must be furnished as a separate signal.
An SPI system may consist of one master MCU and several slaves (Figure 14) or MCUs that can be either masters
or slaves.

The baud rate register is used to select the SCI transmitter and receiver baud rate. SCPO and SCP1 prescaler
bits are used in conjunction with the SCRO through SCR2
baud rate bits to provide multiple baud rate combinations
for a given crystal frequency. Bits 3, 6, and 7 always read
zero.

I- I

SCPl

SCPO

SCR2

SCRI

SCRO

u

u

u

Features:
• Full-duplex, three-wire synchronous transfers
• Master or slave operation

RESET:

Table 3. Prescaler Highest Baud Rate Frequency Output
SCP Bit

1

0

Clock*
Divided By

0
0
1
1

0
1
0
1

1
3
4
13

Crystal Frequency MHz

4.194304
131.072
43.691
32.768
10.082

kHz
kHz
kHz
kHz

4.0
125.000 kHz
41.666 kHz
31.250 kHz
9600 Hz

2.4576
76.80
25.60
19.20
5.907

kHz
kHz
kHz
kHz

2.0

1.8432

62.50 kHz
20.833 kHz
15.625 kHz
4800 Hz

57.60 kHz
19.20 kHz
14.40 kHz
4430 Hz .

*Refers to the internal processor clock.
NOTE: The divided frequencies shown in Table 3 represent baud rates which are the highest transmit baud rate (Tx) that can be
obtained by a specific crystal frequency and only using the prescaler division. Lower baud rates may be obtained by providing
a further division using the SCI rate select bits as shown below for some representative prescaler outputs.

MOTOROLA MICROPROCESSOR DATA

3-916

MC68HC05C8

Table 4. Transmit Baud ,Rate Output for a Given Prescaler Output
SCR Bits
2

1

0

Divided
By

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
2
4
8
16
32
64
128

Representative Highest Prescaler Baud Rate Output
131.0721 Opcode in Hexadecimal

;..:i

Opcode in Binary

WUO - -

I}I.

J

Cycles _ _ _ _ _ _..J

"

AddreSS

M9de

s:

(')

m
::t

(')

o

U'I

Q

MC68HC05C8

an instruction uses direct or extended addressing. The
assembler automatically selects the shortest form of the
instruction.

RELATIVE
The relative addressing mode is only used in branch
instructions. In relative addressing, the contents of the 8bit signed byte (the offset) following the opcode is added
to the PC it and only if, the branch conditions are true.
Otherwiseicontrol proceeds to the next instruction. The
span of relative addressing is from -126 to + 129 from
the opcode address. The programmer need not calculate
the offset when using the Motorola assembler, since it ,
calculates the proper offset and checks to see that it is
within the span of the branch.
INDEXED, NO OFFSET
In the indexed, no offset addressing mode, the effective
address of the argument is contained in the 8-bit index
register. This addressing mode can access the first 256
memory locations. These instructions are only one byte
long. This mode is often used to move a pointer through
a table or to hold the address of a frequently referenced
RAM or I/O location.
INDEXED, 8-BIT OFFSET
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned
8-bit index register and the unsigned byte following the
opcode. The addressing mode is useful for selecting the
Kth element in an n element table. With this two-byte
instruction, K would typically be in X with the address of
thebeginning of the table in the instruction. As such,
tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510
($1 FE is the last location at which the instruction may
begin).
INDEXED, 16-BITOFFSET

In the indexed, 16-bit offset addressing mode, the effective address is the sum ofthe contents ofthe unsigned

8"bitindex register and the two unsigned bytes following
the opcode. This address mode can be used in a manner
similar to.indexed, 8-bit offset except that this three-byte
instruction allows tables to be anywhere in memory. As
with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.

BIT SET/CLEAR
In the bit set/clear addressing mode, the bit to be set
or cleared is part of the opcode, and the byte following
the opcode specifies the direct addressing of the byte in
which the specified bit is to be set or cleared. Any read/
write bit in the first 256 locations of memory, including
I/O, can be selectively set or cleared with a single twobyte instruction.
. .
BIT TEST AND BRANCH
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The
bit that is to be tested and its condition.(set or clear), is
included in the opcode. The address of the byte to be.
tested is in the single byte immediately following the
opcode byte. The signed relative 8-bit offset in the third
byte is added to the PC if the specified bit is set or cleared
in the specified memory location. This single three-byte
instruction allows the program to branch based on the
condition of any readable bit in the first 256 locations of
memory. The span of branching is from ..,.125 to + 130
from the opcode address. The state of the tested bit is
also transferred to the carry bit of the condition code
register.
INHERENT
In the inherent addressing mode, all the information
necessary to execute the instruction is contained in the
opcode. Operations specifying only the index register or
accumulator as well as the control instruction with no
other arguments are included in this mode. These instructions are one byte long.

MOTOROLA MICROPROCESSOR DATA
3-923.

II

MC68HC05C8

ELECTRICAL SPECIFICATIONS
MAXIMUM RATINGS (Voltages referenced to VSS)
Rating

Symbol

Value

Unit

.,VDD

-0.3 to +7.0

V

Input Voltage

Yin

VSS -0.3 to
VDD +0.3

V

Self-Check Mode (IRQ Pin Only)

Yin

VSS-0.3 to
2xVDD+0.3

V

Current Drain Per Pi.n Excluding
VDD and VSS

I

25

mA

TA

TL to TH
+ 70
-40 to .+85
-40 to +105
-40 to +125

°C

Tstg

-65 to +150

°C

Characteristic

Symbol

Value

Thermal Resistance
Plastic
Plastic Leaded Chip Carrier (PLCC)

IIJA

,

Supply Voltage

Operating Temperature Range
MC68HC05C8P, FN
MC68HC05C8CP, CFN
MC68HC05C8VP, VFN
MC68HC05C8MP, MFN
Storage Temperature Range

I

o to

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions"be taken to avoid application of
any voltage higher than maximum-rated voltages
to this high-impedance circuit. For proper operation, it is recommended that Yin and Vout be
constrained to the range VSS "" (Vin or Vout) ""
VDD., Reliability of operation is enhanced if unused inputs are connected to an appropriate logic
voltage level (e.g., either VSS or VDD).

THERMAL CHARACTERISTICS
Unit
°CIW
60
70

POWER CONSIDERATIONS
The average chip-junction temperature, TJ' in °C can
be obtained from:
TJ=TA + (PO 6JA)
(1)
where:
= Ambient Temperature, °C
TA
= Package Thermal Resistance,
6JA
Junction-to-Ambient, °CIW
Po
= PINT+PIIO
:;= ICCxVCC' Watts - Chip Internal Power
PINT
= Power Oissipation on Input and Output
PliO
Pins - User Oetermined
0

For most applications PIIO, disk file
MS@)-DOS/PC-DOS disk file (360K)
EPROM(s) 2764, MCM68764, MCM68766, or EEPROM
MC68HC805C4
To initiate a ROM pattern for the MCU, it is necessary
to first contactthe local field service office, a sales person,
or a Motorola representative.

$0004 through $OOOF. The EPROM devices or EEPROM
MCU devices should be clearly marked to indicate which
device corresponds to which address space.
For shipment to Motorola, EPROMs should be placed
in a conductive IC carrier and packed securely. Styrofoam
is not acceptable for shipment.

FLEXIBLE DISKS

$0020

A flexible disk (MS-DOS/PC-DOS disk file), programmed with the customer's program (positive logic
sense for address and data), may be submitted for pattern
generation. The diskette should be clearly labeled with
the customer's name, data, project or product name, and
the name of the file containing the pattern.
In addition to the program pattern, a file containing the
program source code listing can be included. This data
will be kept confidential and used to expedite the process
in case of any difficulty with the pattern file.
MS-DOS/PC-DOS Disk File

MS-DOS is Microsoft's Disk Operating System. PC-DOS
is the IBM® Personal Computer (PC) Disk Operating System. Disk media submitted must be a standard density
(360K) double-sided 5 114 inch compatible floppy diskette.
The diskette must contain object file code in Motorola's
S-record format. The S-record format is a character-based
object file format generated by M6805 cross assemblers
and linkers on IBM PC style machines.
EPROMs

A 2764, 68764, or 68766 type EPROM, programmed
with the customer's program (positive logic sense for
address and data), may be submitted for pattern generation. Since all program and data space information will
fit on one 68766 EPROM device, the EPROM must be
programmed as described in the following paragraph.
Start the page zero, user ROM at EPROM address $0020
through $004F. Start the user ROM at EPROM address
$0100 through $1 EFF with vectors from $1 FF4 to $1 FFF.
All unused bytes, including the user's space, mu~t be set
to zero.
To use a 2764 or 6874 EPROM or the EEPROM in an
MC68HC805C4, two are required. Start the page zero user
ROM data at EPROM or EEPROM address $0020 through
$004F in the first device. Start the user ROM data at address $0100 through $10FF in the first device. The remainder of the user ROM data should go from $0100
through $10FF in the second device, with vectors from

xxx = Customer 10
Verification Media

All original pattern media (EPROMs or floppy disks) are
filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and
returned along with a listing verification form. The listing
should be thoroughly checked, and the verification form
should be completed, signed, and returned to Motorola.
The signed verification form constitutes the contractual
agreement for the creation of the customer mask. To aid
in the verification process, Motorola will program customer supplied blank EPROM(s) or DOS disks from the
data file used to create the custom mask.
ROM VERIFICATION UNITS (RVUs)

Ten MCUs containing the customer's ROM pattern will
be sent for program verification. These units will have
been made using the custom mask, but are for the purpos~ of ROM verification only. For expediency, the MCUs
are unmarked, packaged in ceramic, and tested with five
volts at room temperature. These RVUs are free with the
minimum order quantity, but are not production parts.
RVUs are not backed or guaranteed by Motorola Quality
Assurance.
ORDERING INFORMATION

The following table provides ordering information pertaining to the package type, temperature, and MC order
numbers for the MC68HC05C8 device.
Temperature

Me Order Number

Plastic
(P Suffix)

O°C to + 70°C
- 40°C to + 85°C
-40° to + 105°C
- 40°C to + 125°C

MC68HC05C8P
MC68HC05C8CP
MC68HC05C8VP
MC68HC05C8MP

PLCC
(FN Suffix)

O°C to + 70°C
-40°C to +85°C
- 40°C to + 105°C
- 40°C to + 125°C

MC68HC05C8FN
MC68HC05C8CFN
MC68HC05C8VFN
MC68HC05C8M FN

Package Type

MOOS is a trademark of Motorola Inc.
MS is a trademark of Microsoft, Inc.
IBM is a registered trademark of International Business Machines Corporation.

MOTOROLA MICROPROCESSOR DATA
3-937

II
.

MC68HC05C8

PIN ASSIGNMENTS

40-PIN DUAl-IN-LiNE PACKAGE
VDD
IRQ

OSCl

NC

OSC2
TCAP
PD7
TCMP
PD5/SS
PD4/SCK
PD3/MOSI

II

PAl

PD2/MISO

PAO

PD1/TOO

PBO

PDO/RDI

PBl

PCO

PB2

PCl

PB3

PC2

PB4

PC3

PB5

PC4

'PB6

PC5

PB7

PC6

VSS

PC7

44-lEAD PlCC PACKAGE

'It.;cnouu«
~ N ClCOl'
««uulli1UJ ocncnuu

Cl-Cl-ZZ_a::>oOt-Z

PD7
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2iMISO
PD1/TOO
Pno/RDI
P<-O
PCl
PC2

PA4
PA3
PA2
,PAl
PAO
PBO
PBl
PB2
PB3
PB4

NOTE: Bulk substrate tied to VSS.

MOTOROLA ,MICROPROCESSOR DATA
3-938

I
IContinued in Volume III

MOTOROLA MICROPROCESSOR DATA

Motorola's Microcontroller and
Microprocessor Families
Volume I

Reliability
-_
Volume I

Data Sheets
Volume I and II

II

Mechanical Data

Volume II

Evaluation Modules
Volume II

Ordering Information Forms
Volume II

MOTOROLA MICROPROCESSOR· DATA

I
I.··
.

M',oto:rola's'M,icrocontroller and
Microprocessor 'Familie;s
Volume I

Reliability'

Volume I

I

Data Sheets
II

Volume I

~nd

Mechanical Data

Volume II'

I

Evaluation: Modules

Volume II

Orderinglnformati'on Fo,rms

Volume II'

MOT9.RQl.AMICROPRQC~SSOR

QATA



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