1988_Motorola_CMOS_NMOS_Special_Functions 1988 Motorola CMOS NMOS Special Functions

User Manual: 1988_Motorola_CMOS_NMOS_Special_Functions

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Master Index

•

Handling and Design Guidelines

•

CMOS ADCs/DACs

•

CMOS Decoders/Display Drivers

•

CMOS Operational Amplifiers/Comparators

•

CMOS/NMOS PLLs/Frequency Synthesizers

•

CMOS Remote Control Functions

•

CMOS Smoke Detectors
Miscellaneous Functions
Reliability
Package Dimensions

•

II
II

MOTOROLA
CMOS/NMOS
SPECIAL FUNCTIONS DATA
Prepared by
Technical Information Center

This book presents technical data for the CMOS and NMOS Special Function integrated
circuits. Complete specifications are provided in the form of data sheets. In addition, a Function Selector Guide and a Handling Precautions chapter have been included to familiarize
the user with these circuits.
Motorola reserves the right to make changes to any product herein to improve reliability,
function or design. Motorola does not assume any liability arising out of the application or
use of any product described herein; neither does it convey any license under its patent
rights nor the rights of others.
Motorola Inc. general policy does not recommend the use of its components in life support applications where in a failure or malfunction of the component may directly threaten
life or injury. Per Motorola Terms and Conditions of Sale, the user of Motorola components
in life support applications assumes all risk of such use and indemnifies Motorola against
all damages.

For marketing and application information contact:
Motorola Inc.
P.O. Box 6000
Austin, TX 78762
Attn: MOS Logic Marketing
Mail Stop: F·B

Printed in U.S.A.

Series A
Fourth Printing
°Motorola Inc.. 1988
Previous Edition °1986
·'AII Rights Reserved"

Product Preview data sheets herein contain information on a product under
development. Motorola reserves the right to change or discontinue these
.
products without notice.
.
Advance Information data sheets herein contain information on new products. Specifications and information are subject to change without
notice.

Master Index

1·1

•

'-,

1-2

MASTER INDEX
This index includes Motorola's entire MCl4000 series CMOS products, although complete
data sheets are included for only the Special Functions. Data sheets for devices in other books,
are designated in the page number column as:
Logic - See DL131, CMOS Logic Data
Telecom - See DL136, Telecommunications Data
MCU - See DL 132Rl, Single-Chip Microcomputer Data
MPU - See DL133, 8-Bit Microprocessor and Peripheral Data

Device
Number

Me

Description

6190
6195
6196
14000UB
14001 B
14oo1UB
14oo2B
14oo2UB
14006B
14007UB
14008B
14011 B
14011UB
14012B
14012UB
14013B
14014B
14015B
14016B
14017B
14018B
14020B
14021B
14022B
14023B
14023UB
14024B
14025B
14025UB
14027B
14028B
14029B
14032B

N-Channel, Silicon Gate, Frequency Synthesizer ................. .
N-Channel, Silicon Gate, Frequency Synthesizer ................. .
N-Channel, Silicon Gate, Frequency Synthesizer ................. .
Dual3-lnput NOR Gate Plus Inverter ........................... .
Quad 2-lnput NOR Gate ...................................... .
Quad 2-lnput NOR Gate ...................................... .
Dual4-lnput NOR Gate ....................................... .
Dual4-lnput NOR Gate ....................................... .
18-Bit Static Shift Register .................................... .
Dual Complementary Pair Plus Inverter ......................... .
4-Bit Full Adder ............................................. .
Quad 2-lnput NAND Gate .................................... .
Quad 2-lnput NAND Gate .................................... .
Dual4-lnput NAND Gate ..................................... .
Dual4-lnput NAND Gate ..................................... .
Dual D Flip-Flop ............................................. .
8-Bit Static Shift Register ..................................... .
Dual4-Bit Static Shift Register ................................ .
Quad Analog Switch/Multiplexer .............................. .
Decade Counter/Divider ..................................... .
Presettable Divide-by-N Counter ............................... .
14-Bit Binary Counter ........................................ .
8-Bit Static Shift Register ..................................... .
Octal Counter/Divider ....................................... .
Triple 3-lnput NAND Gate .................................... .
Triple 3-lnput NAND Gate .................................... .
7-Stage Ripple Counter ...................................... .
Triple 3-lnput NOR Gate ...................................... .
Triple 3-lnput NOR Gate ...................................... .
Dual J-K Flip-Flop ........................................... .
BCD-to-Decimal/ Binary-to-Octal Decoder ...................... .
Binary/Decade Up/Down Counter ................... : ......... .
Triple Serial Adder (Positive Logic) ............................. .

1·3

Page
Number
6-3
6-4
6-4
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic

•

•

Device
Number

Me

14034B
14035B
14038B
14040B
14042B
14043B
14044B
14046B
14049UB
14050B
14051B
14052B
14053B
14060B
14066B
14067B
14068B
14069UB
140708
140718
14072B
14073B
14075B
14076B
14077B
14078B
140818
140828
140938
140948
14097B
14099B
141608
14161B
14162B
14163B
14174B
141758
14194B

14400
14401
14402
14403
14405

14408

Page
Description
8-Bit Universal Bus Register ................................... .
4-Bit Shift Register .......................................... .
Triple Serial Adder (Negative Logic) ............................ .
12-Bit Binary Counter ........................................ .
Quad Transparent Latch ...................................... .
Quad NOR R-S Latch ........................................ .
Quad NAND R-S Latch ....................................... .
Phase-Locked Loop ......................................... .
Hex Inverter/Buffer .......................................... .
Hex Buffer ................................................. .
8-Channel Analog Multiplexer/Demultiplexer .................... .
Dual4-Channel Analog Multiplexer/Demultiplexer ................ .
Triple 2-Channel Analog Multiplexer/Demultiplexer ............... .
14-Bit Binary Counter and Oscillator ............................ .
Quad Analog Switch/Multiplexer .............................. .
16-Channel Analog Multiplexer/Demultiplexer .. , ................ .
8-lnput NAND Gate ..................................... , .... .
Hex Inverter ................................................ .
Quad Exclusive OR Gate ...................................... .
Quad 2-lnput OR Gate ....................................... .
Dual4-lnput OR Gate ........................................ .
Triple 3-lnput AND Gate ...................................... .
Triple 3-lnput OR Gate ............................ '...... : .... .
Quad D-Type Register ....................................... .
Quad Exclusive NOR Gate .................................... .
a-Input NOR Gate ........................................... .
Quad 2-lnput AND Gate ...................................... .
Dual 4-1 nput AN D Gate ....................................... .
Quad 2-lnput NAND Schmitt Trigger ........................... .
8-Bit Bus-Compatible Shift/Store Latch ........................ .
Dual8-Channel Analog Multiplexer/Demultiplexer ................ .
8-Bit Addressable Latch ...................................... .
Synchronous Programmable Decade Counter ................... .
Synchronous Programmable 4-Bit Binary Counter ................ .
Synchronous Programmable Decade Counter ................... .
Synchronous Programmable 4-Bit Binary Counter ................ .
Hex D Flip-Flop ............................................. .
Quad D Flip-Flop ............................................ .
4-Bit Universal Shift Register .................................. .
PCM Mono-circuit ........................................... .
PCM Mono-circuit ........................................... .
PCM Mono-circuit ........................................... .
PCM Mono-circuit ........................................... .
PCM Mono-circuit. ...........................................
Binary-to-Phone Pulse Converter ...............................

1-4

Number
Logic
Logic
Logic
Logic
Logic
Logic
Logic
6-13
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
. Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom

Device
Number

Me

14409
14410
14411
14412
14413
14414
14415
14416
14417
14418
14419
14422
14433
14435
14442
14443
14444
14447
14457
14458
14460
14461
14462
14464
14465
14466
14467-1
14468
14469
14490
14495-1
14497
14499
14500B
14501UB
14502B
14503B
14504B
14506B
14506UB
14508B
14510B
14511 B
14512B
14513B

Description
Binary-to-Phone Pulse Converter .............................. .
2-of-8 Tone Encoder ......................................... .
Bit-Rate Frequency Generator ................................. .
Universal Low-Speed Modem ................................. .
PCM Sampled Data Filter ..................................... .
PCM Sampled Data Filter ..................................... .
Quad Precision Timer/Driver .................................. .
PCM Time Slot Assigner Circuit ............................... .
PCM Time Slot Assigner Circuit ............................... .
PCM Time Slot Assigner Circuit ............................... .
2-of-8 Keypad-to-Binary Encoder .............................. .
Remote Control Transmitter (Product Cancelled) ................. .
3 ~ Digit A/ D Converter ...................................... .
3~ Digit A/D Logic Subsystem (Product Cancelled) .............. .
Microprocessor-Compatible A/D Converter ..................... .
6-Channel A/ D Converter Subsystem .......................... .
Microprocessor-Compatible A/D Converter ..................... .
6-Channel A/D Converter Subsystem .......................... .
Remote Control Transmitter .................................. .
Remote Control Receiver ..................................... .
Automotive Speed Control Processor .......................... .
Smoke Detector Circuit (Product Cancelled) ..................... .
Smoke Detector Circuit (Product Cancelled) ..................... .
Smoke Detector Circuit (Product Cancelled) ..................... .
Smoke Detector Circuit (Product Cancelled) ..................... .
Low Cost Smoke Detector .................................... .
Low Cost Smoke Detector .................................... .
Interconnectable Smoke Detector ............................. .
Addressable Asynchronous Receiver/Transmitter ................ .
Hex Contact Bounce Eliminator ................................ .
Hexadecimal-to-7 Segment Latch/Decoder ROM/Driver .......... .
PCM Remote Control Transmitter .............................. .
7-Segment LED Display Decoder/Driver with Serial Interface ...... .
Industrial Control Unit ........................................ .
Triple Gate ................................................. .
Strobed Hex Inverter/Buffer .................................. .
Hex 3-State Buffer .......................................... .
Hex TTL- or CMOS-to-CMOS Level Shifter ...................... .
Dual Expandable AOI Gate (Superceded by 14506UB) ............. .
Dual Expandable AOI Gate .................................... .
Dual 4-Bit Latch ............................................. .
BCD Up/Down Counter ........................................
BCD-to-7-Segment Latch/Decoder/Driver ...................... .
8-Channel Data Selector ...................................... .
BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking .... .

1-5

Page
Number
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Logic
Telecom
Telecom
Telecom
Telecom
3-3
3-15
3-16
3-25
3-29
3-39
7-3
7-3
9-3

. 8-3
8-8
8-13
7-13
9-9
4-3
7-21
4-8
9-16
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
4-14
Logic
4-20

•

•

Device
Number
MC
145148
145158
145168
145178
145188
145198
145208
145218
145228
145268
145278
145288
145298
145308
145318
145328
145348
145368
145388
145398
145418
145438
145448
145478
145488
145498
145518
145538
145548
145558
145568
145578
145588
145598
145608
145618
145628
145668
145688
145698
14572U8
14573
14574
14575
145808

Description

Page
Number

4-8it Transparent Latch/4-to-16 Line Decoder (High) ............. . Logic
4-8it Transparent Latch/4-to-16 Line Decoder (Low) .............. . Logic
8inary Up/Down Counter .................................... . Logic
Dual 64-8it Static Shift Register ............................... . Logic
Dual 8CD Up Counter ........................................ . Logic
4-8it AND/OR Selector ...................................... . Logic
Dual 8inary Up Counter ...................................... . Logic
24-Stage Frequency Divider ................................... . Logic
Programmable 8CD Divide-by-N Counter ....................... . Logic
Programmable 8inary Divide-by-N Counter ...................... . Logic
8CD Rate Multiplier ......................................... . Logic
Dual Monostable Multivibrator (Not Recommended for New Designs)
Logic
Dual4-Channel Analog Data Selector ........ , ................. . Logic
Dual 5-lnput Majority Logic Gate ............................... . Logic
12-8it Parity Tree ............................................ . Logic
8-8it Priority Encoder ........................................ . Logic
5-Decade Counter ........................................... . Logic
Programmable Timer ........................................ . Logic
Dual Precision Monostable Multivibrator ........................ . Logic
Dual4-Channel Data Selector/Multiplexer. " ................... . Logic
Programmable Oscillator-Timer ................................ . Logic
8CD-to-7-Segment Latch/Decoder/Driver for Liquid Crystals ...... .
4-28
8CD-to-7-Segment Latch/Decoder/Driver with Ripple 8lanking .... .
4-33
High-Current 8CD-to-7-Segment Decoder/Driver ................ .
4-39
DUi'J1 Monostable Multivibrator (Retriggerable/ Resettable) ......... . Logic
Successive Approximation Register ..................... , ...... . . 3-40
Quad 2-Channel Analog Multiplexer/Demultiplexer ............... . Logic
3-Digit 8CD Counter ......................................... . Logic
2 x 2-8it Parallel 8inary Multiplier .............................. . Logic
Dual 8inary to l-of-4 Decoder ............. , ................... . Logic
Dual 8inary to 1-of-4 Decoder (Inverting) ........................ . Logic
1-to-64 8it Variable Length Shift Register ....................... . Logic
8CD-tQ-7-Segment Decoder .................................. .
4-44
Successive Approximation Register ............................ .
3-40
N8CD Adder ............................................. ; ..
Logic
9's Complementer ........................................... . Logic
128-8it Static Shift Register ................................... . Logic
Industrial Time-8ase Generator ................................ . Logic
6-18
Phase Comparator and Programmable Counters ................. .
Dual Programmable 8CD/8inary Counter ....................... . Logic
Hex Gate ........................................... " ..... .' ..
Logic
5-3
Quad Programmable Op Amp ................................. .
5-3
Quad Programmable Comparator .............................. .
Programmable Dual Op Amp/ Dual Comparator .................. .
5-3
4 x 4 Multiport Register ....................................... . Logic

1-6

Device
Number
MC
14581B
14582B
14583B
14584B
14585B
14597B
14598B
14599B
142100
143403
144110
144111
145000
145001
145026
145027
145028
145029
145040
145041
145100
145104
145106
145107
145109
145112
145143
145144
145145-1
145146-1
145151-1
145152-1
145155-1
145156-1
145157-1
145158-1
145159-1
145402
145406

145409
145411
145414
145415
145418

Description
4-Bit Arithmetic Logic Unit .................................... .
Look-Ahead Carry Block ..................................... .
Dual Schmitt Trigger ..................................... ".... .
Hex Schmitt Trigger ......................................... .
4-Bit Magnitude Comparator .................................. .
8-Bit Bus-Compatible Counter Latch ........................... .
8-Bit Bus-Compatible Addressable Latch ........................ .
8-Bit Addressable Latch ...................................... .
4 x 4 Cross Point Switch ...................................... .
Quad Line Driver ............................................ .
Hex DI A Converter with Serial Interface ........................ .
Quad DI A Converter with Serial Interface ....................... .
48-Segment Multiplexed LCD Driver (Master! .................... .
44-Segment Multiplexed LCD Driver (Slave) ..................... .
Remote Control Encoder ..................................... .
Remote Control Decoder ..................................... .
Remote Control Decoder ..................................... .
Remote Control Decoder ..................................... .
Analog-to-Digital Converter with Serial Interface ................. .
Analog-to-Digital Converter with Serial Interface ................. .
4 x 4 Cross Point Switch ...................................... .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
PLL Frequency Synthesizer ................................... .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
PLL Frequency Synthesizer (Not Recommended for New Designs) .. .
4-Bit Data Bus Input PLL Frequency Synthesizer
(Not Recommended for New Designs) ........................ .
4-Bit Data Bus Input PLL Frequency Synthesizer ................. .
4-Bit Data Bus Input PLL Frequency Synthesizer ................. .
Parallel Input PLL Frequency Synthesizer ....................... .
Parallel Input PLL Frequency Synthesizer ....................... .
Serial Input PLL Frequency Synthesizer ......................... .
Serial Input PLL Frequency Synthesizer ......................... .
Serial Input PLL Frequency Synthesizer ......................... .
Serial Input PLL Frequency Synthesizer ......................... .
Serial Input PLL Frequency Synthesizer with Analog Phase Detector.
13-Bit Linear Codec .......................................... .
RS-232 Interface ............................................ .
Pulse Dialer ................................................ .
Baud Rate Generator ........................................ .
Dual Tuneable Low-Pass Sampled Data Filters ................... .
Dual Tuneable Linear Phase Low-Pass Sampled Data Filters ....... .
Master Digital Loop Transceiver ............................... .

1-7

Page
Number
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Telecom
Telecom
3-47
3-47
4-49
4-49
7-27
7-27
7-27
7-27
3-52
3-52
Telecom
6-28
6-29
6-28
6-28
6-28
6-35
6-36
6-37
6-50
6-63
6-73
6-84
6-95
6-108
6-108
6-120
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom

•

•

Device
Number

Page

Me

Description

Number

145419
145422
145426
145428
145429
145432
145433

Slave Digital Loop Transceiver ................... : ... ; .... : ....
MDPSK Universal Digital Loop Transceiver (2-Wire Master) . '.' ......
MDPSK Universal Digital Loop Transceiver (2-Wire Slave) .. . . . . . . ..
Data Set Interface ............................................
Telset Audio .interface Circuit ................... : ..............
2600 Hz Tone Signalling Filter ..................................
Tuneable Notch/Band-Pass Filter ...............................
Low-Speed Modem Filter ....................... : .......•.......
Low-Speed Modem Filter ...................... '" ..............
300 Baud FSK Modem ........................................
1200 Baud FSK Modem ...................... : .............. ,.
33-Segment LCD Driver with Serial Interface .. . . . . .. . . . . . . . . . .. . .
Family of8-Bit CMOS MCUs/MPUs ............... , .............
Real-Time Clock/RAM ........................................
Parallel Interface .............................................
8-Bit CMOS MCUs with EPROM ................................

Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
Telecom
4-59
MCU,MPU
MCU,MPU
MCU,MPU
MCU,MPU

145440
145441
145445
145450
145453
146805
146818
146823
1468705

1-8

Handling and Design Guidelines

2·1

•

®

•

MOTOROLA
HANDLING AND DESIGN GUIDELINES

HANDLING PRECAUTIONS
All MOS devices have an insulated gate that is subject to
voltage breakdown. The gate oxide for Motorola's devices is
about 800 A thick and breaks down at a gate-source potential of about 100 V. The high-impedance gates on the devices
are protected by resistor-diode networks. However, these
on-chip networks do not make the IC immune to electrostatic damage (ESDI. Laboratory tests show that devices
may fail after one very high voltage discharge. They may also
fail due to the cumulative effect of several discharges of
lower potential.
Static-damaged devices behave in various ways, depending on the severity of the damage. The most severely
damaged are the easiest to detect because the input or output has been completely destroyed and is either shorted to
VOD, shorted to VSS, or open-circuited. The effect is that
the device is no longer functional. Less severe cases are
more difficult to detect because they appear as intermittent
failures or degraded performance. Another effect of static
damage is, often, increased leakage currents.
CMOS and NMOS devices are not immune to large static
voltage discharges that can be generated while handling. For
example, static voltages generated by a person walking
across a waxed floor have been measured in the 4-15 kV
range (depending on humidity, surface conditions, etc.l.
Therefore, the following precautions should be observed.

1. Do not exceed the Maximum Ratings specified by the
data sheet.
2. All unused device inputs should be connected to VOO
or VSS.
3. All low-impedance equipment (pulse generators, etc.l
should be connected to CMOS or NMOS inputs only
after the device is powered up. Similarly, this type of
equipment should be disconnected before power is
turned off.
4. A circuit board containing CMOS or NMOS devices is
merely an extension of the device and the same
handling precautions apply. Contacting edge connectors wired directly to devices can cause damage.
Plastic wrapping should be avoided. When external
connections to a PC board address pins of CMOS or
NMOS integrated circuits, a resistor should be used in
series with the inputs or outputs. The limiting factor
for the series resistor is the added delay caused by the
time constant formed by the series resistor and input
capacitance. This resistor will help limit accidental
damage if the PC board is removed and brought into
contact with static generating materials. For convenience, equations for added propagation delay and
rise time effects due to series resistance size are given
in Figure 1.
5. All CMOS or NMOS devices should be stored or

FIGURE 1 - NETWORKS FOR MINIMIZING ESD AND REDUCING CMOS LATCH UP SUSCEPTIBILITY
VDD

]~DI
To Off-Board
Connection

I

RI

J

MOS
Input

I

or
Output

To Off-Board
Connection

l

MOS
Input
or
Output

R2

I
-';~D2

Advantage: Requires minimal board area

Advantage. R2< R1forthe same _ "55
level of protection.
Impact on ac and de
characteristics is minimized.

Disadvantage: RI> R2 for the same level of
protection, therefore rise and fall
times, propagation delays, and output
drives are severely affected.

Disadvantage:

More board area, higher initial cost

Note: These networks are useful for protecting the follOWing:
A. digital inputs and outputs
B. analog Inputs and outputs
C. 3-state outputs
D. bidirectional 11/0) ports

EQUATION I - PROPAGATION DELAY
vs. SERIES RESISTANCE

EQUATION 2 - RISE TIME
vs. SERIES RESISTANCE

t

t

R----

R~---

Cok

Cok

where:
A= the maximum allowable series resistance in ohms
t= the maximum tolerable propagation delay in seconds
C = the board capacitance plus the driven device's
input capacitance in farads
k=O.33 for the MCl45040/1
k=O.7 for other devices

where:
R = the maximum allowable series resistance in ohms
t = the maximum rise time per data sheet in seconds
C=the board capacitance plus the driven device's
input capacitance in farads
k=O.7 for the MCI45040/1
k = 2.3 for other devices

2·2

6.

7.
8.

9.

10.

11.

12.

transported In materials that are antistatic. Devices
must not be Inserted Into conventional plastic
"snow", styrofoam or plastic trays, but should be left
in their Original container until ready for use.
All CMOS or NMOS devices should be placed on a
grounded bench surface and operators should ground
themselves prior to handling devices, since a worker
can be statically charged with respect to the bench
surface. Wrist straps In contact With skin are strongly
recommended. See Figure 2.
Nylon or other static generating materials should not
come In contact with CMOS or NMOS CirCUitS.
If automatic handling IS being used, high levels of
static electricity may be generated by the movement
of devices, belts, or boards. Reduce static build-up by
using ionized air blowers or room humidifiers. All parts
of machines which come into contact With the top,
bottom, and sides of IC packages must be grounded
metal or other conductive material.
Cold chambers using C02 for cooling should be
equipped With baffles, and devices must be contained
on or In conductive material.
When lead-straightening or hand-soldering is
necessary, provide ground straps for the apparatus
used and be sure that soldering ties are grounded.
The following steps should be observed dUring wave
solder operations.
a. The solder pot and conductive conveyor system of
the wave soldering machine must be grounded to
an earth ground.
b. The loading and unloading work benches should
have conductive tops which are grounded to an
earth ground.
c. Operators must comply with precautions previously
explained.
d. Completed assemblies should be placed in antistatic containers prior to being moved to subsequent stations.
The following steps should be observed during board
cleaning operation.
a. Vapor degreasers and baskets must be grounded to

13.
14.

15.

16.

17.

an earth ground. Operators must likewise be
grounded.
b. Brush or spray cleaning should not be used.
c. Assemblies should be placed Into the vapor
degreaser Immediately upon removal from the antistatic container.
d Cleaned assemblies should be placed In antistatic
containers Immediately after removal from the
cleaning basket.
e. High velOCity air movement or application of
solvents and coatings should be employed only
when module circuits are grounded and a static
eliminator is directed at the module.
The use of static detection meters for line surveillance
IS highly recommended.
Equipment specifications should alert users to the
presence of CMOS or NMOS devices and reqUire
familiarization with thiS specification prior to performing any kind of maintenance or replacement of deVices
or modules.
Do not Insert or remove CMOS or NMOS devices
from test sockets with power applied. Check all power
supplies to be used for testing devices to be certain
there are no voltage transients present.
Double check test equipment setup for proper polarity
of voltage before conducting parametric or functional
testing.
Do not recycle shipping ralls. Continuous use causes
deterioration of their antistatic coating.

RECOMMENDED FOR READING
"Total Control of the Static In Your BUSiness"
Available by writing to
3M Company
Static Control Systems
POBox 2963
Austin, Texas 78769-2963
Or by Calling.
1-800-328-1368

FIGURE 2 - TYPICAL MANUFACTURING WORK STATION

NOTES: 1. 1/16 inch conductive sheet stock covering bench top
work area.

2. Ground strap.
3. Wrist strap in contact with skin.
4. StatIc neutralizer. (IonIzed aIr blower directed at work.)
Primarily for use In areas where direct grounding
IS Impractical.
5. Room humidifier. Primarily for use In areas where the
relative humIdIty IS less than 45%. CautIon. bUIlding
heating and coolIng systems usually dry the air causing
the relatIve humidity inSide of bUildings to be less than

outside humidity.

2-3

•

•

CMOS LATCH UP
Latch up will not be a problem for most designs, but the
designer should be aware of it, what causes it, and how to
prevent it.
Figure 3 shows the layout of a typical CMOS inverter and
Figure 4 shows the parasitic bipolar devices that are formed.
The circuit formed by the parasitic transistors and resistors is
the basic configuration of a silicon controlled rectifier, or
SCR. In the latch-up condition, transistors 01 and 02 are
turned on, each providing the base current necessary for the
other to remain in saturation, thereby latching the devices
on. Unlike a conventional SCR, where the device is turned
on by,applying a voltage to the base of the NPN transistor,
the parasitic SCR is turned on by applying a voltage to the
emitter of either transistor. The two emitters that trigger the
SCR are the same point, the CMOS output. Therefore, to
latch up the CMOS device, the output voltage must be
greater than VOO + 0.5 Vdc or less than - 0.5 Vdc and have
sufficient current to trigger the SCR. The latch-up
mechanism is similar for the inputs.
Once a CMOS'device is latched up, if the supply current is
not limited, the device will be destroyed. Ways to prevent
such occurrences are listed below.

2.

3.

4.

5.
6.

1. Insure that inputs and outputs are limited to the maximum rated values, as follows:

-0.5sVi n SVOO+0.5 Vdc referenced to VSS
-0.5sVoutSVDO+0.5 Vdc referenced to VSS
IIinls10 mA
Iioutl :s 10 mA when transients or dc levels exceed the
supply voltages.
If voltage transients of sufficient energy to latch up the
device are expected on the outputs, external protection diodes can be used to clamp the voltage. Another
method of protection is to use a series resistor to limit
the expected worst case current to the Maximum
Ratings values. See Figure 1.
If voltage transients are expected on ths inputs, protection diodes may be used to clamp the voltage or a
series resistor may be used to limit the current to a
level less than the maximum rating of lin = 10 mAo See
Figure 1.
Sequence povyer supplies so that the inputs or outputs
of CMOS devices are not powered up first (e.g.,
recessed edge connectors may be used in plug-in
board applications and I or series resistors).
Power supply lines should be free of excessive noise.
Care in board layout and filtering should be used.
Limit the available power supply current to the devices
that are subject to latch-up conditions. This can be accomplished with the power supply filtering network or
with a current-limiting regulator.

FIGURE 3 - CMOS WAFER CROSS SECTION

P-Channel

N-Channel
Input

Field Oxide

FIGURE 4 -

LATCH UP CIRCUIT SCHEMATIC

:~----'\N\;,..--P-+-N----4>---P---------,:,-'?i
~
~
P-Channel Output

:::

P- Well Resistance

Q2

N - Substrate Resistance

2-4

N-ChannelOutput

!:::

CMOS ADCs/DACs

3-1

II

CMOS ADCs/DACs

Device
Number

•

3 % Digit AI D Converter
Product Cancelled - See Other AI D Converters
Microprocessor-Compatible AID Converter
6-Channel AID Converter Subsystem
Microprocessor-Compatible AID Converter

MCI4447
MCI4549B
MC14559B
MCI44110
MCI44111

6-Channel AI D Converter Subsystem
Successive ApproXimation Register
Successive Approximation Register
Digltal-ta-Analog Converter with Senal Interface
Digital-ta-Analog Converter with Serial Interface

, MCI45040
MCI45041

Analog-te-Digltal Converter with Serial Interface
Analog-ta-Dlgltal Converter with Serial Interface

I

Function
ADC

110 Format
Senal
[Compatible with
the Serial Peripheral
Interface (SPI) on
CMOSINMOS MCUsJ

Parallel

Function

MCI4433
MCI4435
MCI4442
MCI4443
MCI4444

Resolution
8 Bits

Number
of Analog
Channels
11

On-Chip
Oscillator

8 Bits

11

'"

Successive
ApprOXimation

3% Digit BCD

1

8 Bits

11

'"

Device
Number

Number
of Pins

MCl45040

20

MCI45041

20

Dual Slope

MCI4433

24

Successive

MCI4442

28

MCI4444

40

Other Features
Successive
Approximation

ApproXimation

8 Bits

15

Successive
ApproXimation

ADC Linear
Subsystem

DAC

Successive
ApproXImation
Register

Parallel

8 to 10 Bits

6

Single Slope wi
Auto Zeroing

MCI4443

16

8 to 10 Bits

6

Single Slope wi
Auto Zeroing

MCI4447

16

Senal
[Compatible with
the Serial Peripheral
Interface (SPI)
on CMOS MCUsJ

6 Bits

6

Emitter-Follower

MCI44110

18

6 Bits

4

Outputs
Emitter-Follower
Outputs

MCI44111

14

Serial or Parallel

:s8 Bits

Cascadable for
>8 Bits

MCI4549B

16

:s8 Bits

Cascadable for
>8 Bits

MCI4659B

16

3-2

®

MCl4433

MOTOROLA

3% DIGIT AID CONVERTER
The MCl4433IS a high performance, low power, 3Y, digit AID converter combining both linear CMOS and digital CMOS circuits on a single monolithic IC. The
MCl4433 is designed to minimIZe use of external components. With two external
resistors and two external capacitors, the system forms a dual slope AID converter with automatic zero correction and automatic polarity.
The MCl4433 IS ratiometric and may be used over a full-scale range from 1.999
volts to 199.9 millivolts. Systems using the MCl4433 may operate over a wide
range of power supply voltages for ease of use with batteries, or with standard 5
volt supplies. The output drive conforms with standard B-Series CMOS
specifications and can drive a low-power Schottky TTL load.
The high impedance MOS inputs allow applications in current and resistance
meters as well as voltmeters. In addition to DVMIDPM applications, the
MCl4433 finds use in digital thermometers, digital scales, remote AID, AID control systems, and in M PU systems.
• Accuracy: ± 0.05% of Reading ± 1 Count
• Two Voltage Ranges: 1.999 V and 199.9 mV
• Up to 25 Conversionsls
• Zin> 1000 M ohm
• Auto-Polarity and Auto-Zero
• Single Positive Voltage Reference
• Standard B-Series CMOS Outputs- Drives One Low Power
Schottky Load
• Uses On-Chip System Clock, or External Clock
• Wide Supply Range: e.g., ±4.5 V to ±8.0 V
• Overrange and Underrange Signals Available
• Operates in Auto Ranging Circuits
• Operates with LED and LCD Displays
• Low External Component Count
• See also Applicallon Notes AN-769 and AN-770
• Chip Complexity: 1326 FETs
BLOCK DIAGRAM

CMOS LSI
(LOW-POWER COMPLEMENTARY MaS)

II

3 % DIGIT AI D CONVERTER

L SUFFIX
CERAMIC PACKAGE
CASE 623

P SUFFIX
PLASTIC PACKAGE
CASE 700

ORDERING INFORMATION

MC14XXX

Suffix

1-- L
L P

Denotes
CeramIc Package

Plastic Package

20-23

00-03
BCD Data
Multiplexer

16-19
DS1-DS4
Digit Strobe

PIN ASSIGNMENT

1
2
3

4
5
6

24
23
22
21
20
19

7

18

8
9

17
16
15
14
13

10
11
12

OR Overrange

Vref Reference Voltage

CMOS
Analog
Subsystem

VAG Analog Ground
Vx Analog Input

9
DU

Integrator

Conversion

3-3

Offset

VDD= Pin 24
VSS=Pln 13
VEE= Pin 12

MC14433

MAXIMUM RATINGS
Rating
DC Supply Voltage
Voltage, any pin, referenced to VEE

Symbol

Value

Unit

VOD to VEE
V

-0.5 to + 18
O.b to
VDO +0.5

V
V

±10

mA

DC Input Current, per Pin

lin

Operating Temperature Range

Storage Temperature Range

•

-65 to + 150

'c
'c

40 to +85

TA
Tstg

This device contains Circuitry to protect
the Inputs against damage due to high
static voltages or electric fields; however,
it IS advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit For proper
operation It is recommended that Vin and
Vout be constrained to the range
VEE:sIVin or Voutl:SVDO·

RECOMMENDED OPERATING CONDITIONS IVSS=O or VEEI
Symbol

Value

Unit

DC Supply Voltage - VDD to Analog Ground
VEE to Analog Ground

VDD
VEE

+5.0 to +8.0
-2.8 to -80

Vdc

Clock Frequency

fClk

32 to 400

kHz

Zero Offset Correction Capacitor

Co

o 1±20%

I'F

Parameter

ELECTRICAL CHARACTERISTICS ICI=O 11'F mylar, RI=470 kll@V re f=2000V, RI=27 kll@V re f=200.0mV, Co=O 11'F,
RC = 300 kll, all voltages referenced to Analog Ground, pin 1, unless otherwise Indlcatedl

Characteristic

Stability - Output Reading
IVX= 199:0 mY, V re f=200.0 mVI
Symmetry - Output Reading INote 21
IV re f=2 000 VI
Zero-Output Reading
IVX=O V, Vref=2 000 VI
Analog Input

-5.0

-

50

-50

-

-

50

-5.0

3*

LSD

-

50

-5.0

4*

LSD

-

5.0

-5.0

-

50
5.0
50

50
-50
-50

-

-

-

5.0

-5.0

50
10
15
50

Reference Input

Analog Ground

Common Mode Rejection Ifclk = 32 kHz,
VX=l 4 V, V re f=2 000 VI
"0" Level

Min

Typ

Max

Min

Max

-

-005
-1 Count

±O 05

+0.05

-

-

-

-

±0.05

+1 Count
-

-

-

"1" Level

-

Output Voltage - Pins 14 to 23
"0" Level
IVSS=OVI
"1" Level
IVSS= -50VI "0" Level
"1" Level

-

-

-

0

0

-

-

-

-

±20
±20
±20

±100
± 100
±500

-

-

-

-

-

65

-

-

-

-

-

15
3.0
40

-

2.25
4.50
6.75

1.5
30
4.0

-

15
3.0
4.0

-

3.5
7.0
110

-

35
7.0
11.0

275
550
8.25

-

-

35
70
110

-

005

-

005

-

495

-

-4.95

10
15

V
005

-

-

495

495

-

-

4.95

0
-5.0
-50
5.0

IOH
IOL

50
50

-5'0 -025
-50 064

-

-02
051

IOH
IOL

50
50

-5.0 -062
-5.0 16

-

IDU

50

-5.0

±0.3

QUiescent Current

10

IVDD to VEE, ISS = 01
DC Supply RejectIOn
IVDD to VEE, ISS=O, V re f=2 000 VI

50
80

-50
-80

-

-

50

-50

-

-

-495

-

495

-

-0.36
0.88

-

-

-0.14
036

-

-0.5
13

-09
2.25

-

-035
0.9

-

±0.00001

±03

~A

0.9
1.8

20
4.0

-

±10

3.7
74

-

16
32

mA

-

-

0.5

-

-

-

mV/v

mA

PinS 14 to 23
Source

Source

Sink

Input Current - DU, Pin 9

dB

V

-50
-5.0 4.95
-50
-5.0 495

Notes

pA

VIH

5.0
5.0
5.0
50

Sink

LSD

V

VOL
VOH
VOL
VOH

IVSS=OVI
IVOH=4.6 VI
IVOL =04 VI
IVSS= -50 VI
IVOH =4 5 VI
IVOL = -4 5 VI

' Unit
%rdg

VIL

IVo=050r45VI
IVo=100r90VI
IVo=150r135VI

Output Current -

85°C

5.0

IV re f=200 0 mVI

Input Voltage" Pins 9, 10
IVO=4 5 orO 5 VI
IVo=900rl0VI
IVo=1350r15VI

25°C

VEE
Vdc

-

Linearity-Output Reading INote 11
IVref=2.ooo VI

Bias Current

-40°C
Min Max

VDD
Vdc

Symbol

-

1 Accuracy - The accuracy of the meter at full scale IS the accuracy of the setting of the reference voltage Zero IS recalculated dUring
each conversion cycle The meaningful speCificatIOn IS Iineanty In other words, the deViation from correct reading for all Inputs other
than POSitive full scale and zero IS defined as the IIneanty speCificatIon

2. Symmetry - Defined as the difference between a negative and POSitive reading of the same voltage at or near full scale
Consult LogiC and Special FunctIOns Product Marketing for details at 15121 928-6880

* Tighter tolerances are available

* Referenced to VSS for Pin 9 Referenced to VEE for Pin 10

3-4

MC14433
TYPICAL CHARACTERISTICS
FIGURE 1 - TYPICAL ROLLOVER ERROR
versus POWER SUPPL Y SKEW

FIGURE 2 - TYPICAL QUIESCENT POWER SUPPLY CURRENT
versus TEMPERATURE
.
0

3
1
1

O'/'

0

-r-....

i-"'"

-1

r-- t------.

VEE" -5 V
VOO"+5V

0

1'- NOTE ROLLOVER ERROR IS THE OIFFERNCE IN
OUTPUT READING FOR THE SAME ANALOG
INPUT SWITCHED FROM POSITIVE TO NEG·
3rATiVE.

-3

-

~

0

1

-4

VEJ" -8 V
VOO"+8V

r-::r-.

•

-

-r-.

0

-1

-10

-40

IIVOOI- IVEEII. SUPPLY VOLTAGE SKEW IVOL TSI

FIGURE 3 - TYPICAL N-CHANNEL SINK CURRENT
AT VOO-VSS = 5 VOLTS
0

10
40
TA. TEMPERATURE 10C}

GO

80

FIGURE 4 - TYPICAL P-CHANNEL SOURCE CURRENT
AT VOO-VSS = 5 VOL TS

-3. 0
0
;;'

.s

0

~

0

0

~

>-z

+25 0 C

f5

-400 C

..... r--

~ -2. 0

./""

V
L L I-"'"
L .L::: ~

w

+85 0 C-

// /""'

01/

400 C

tV

'"
"~

DO

1. 0

ei

.-

.1
,'+25 0 C

I.----" r-- r--+
~

850 C

r---

~ I-"'"
10

1.0

30

4.0

01P'

50

-10

VOS. ORAIN·TO·SOURCE VOLTAGE IVdcl

FIGURE 5 - TYPICAL CLOCK FREQUENCY
versus RESISTOR (RC)

! ! 11 tJ! ij
•

• • : Note

-30

50

40

FIGURE 6 - TYPICAL % CHANGE OF CLOCK FREQVENCY
versus TEMPERATURE
4. 0

IIll- ...l........1.-=1
! H.....,

! !I.
if .

t.
I
:

-10

Vas. DRAIN -TO·SOURCE VOLTAGE IVdc}

w

'"z
~

~

0

2. 0

~

1. 0

~

0

J'...

I~

±5 V SUPPLY

~

~_ -1. 0
'" 0
d
-2

1""-

t;:,. ±8VSUPPLY

""""""

j--

~

u

§

NORMAlIZEO AT 15 0C

-3 0
-4 0
-40

-10

RC. CLOCK FREOUENCY RESISTOR

CONVERSION RATE -

MULTIPLEX RATE

CLOC\~~~UENCY ± 1.5%
GLOCK FREQUENCY

80

3·5

10
40
TA. TEMPERATURE 10C}

60

80

MC14433
For Vx(max) = 200 mV
RI=28 kO(use 27 kO±5%)

PIN DESCRIPTIONS
ANALOG GROUND (.VAG. Pin 1)
Analog ground at this pin is the input reference level,for
the unknown input voltage IVX) and reference voltage
(Vrefl. This pin is a high impedance input. The allowable
operating range for VAG is from VEE + 2.8 V to VDD
-4.5V.
.

•

Note that for worst case conditions', the minimum
allowable value for RI is a function of CI.min, VDD min, and
fClk max. The worst-case condition does not allow 6V + Vx
I to exceed VDD. The 0.5 V factor in the above equation fo~
6V is for safety margin.
OFFSET CAPACIT()R (COl, CO2; Pins 7.8)
These pins are used for connecting the offset correction
capacitor. The recommended vallie is 0.1 p.F (polystyrene or
mylarl.

REFERENCE VOLTAGE (Vret. Pin 2)
UNKNOWN INPUT VOLTAGE (VX. Pin 3)
This AID system performs a ratiometric AID conversion;
that is, the unknown input voltage, VX, is measured as a
ratio of the reference voltage, V ref. The full scale voltage is
equal to that voltage 'applied to Vref. Therefore, a full scale
voltage of 1.999 V requires a reference voltage of 2.000 V
while full scale voltage of 199.9 mV requires a reference
voltage of 200 mY. Both Vx and Vref are high impedance inputs. In addition to being a reference input, Pin 2 functions
as a reset for the AI D converter. When Pin 2 is switched low
Ireferenced to VEE) for at least 5 clock cycles, the system is
reset to the beginning of a conversion cycle.
. .:.,!.

DISPLAY UPDATE INPUT (DU, Pin 9)
If a positive edge is received 01;) this input prior to the
ramp-(jown cycle, new data will be strobed into the output
. latches during that conversion cycle. When.. this pin is wired
'directly to the EOC output (Pin 14), every c~lnversion will be
displayed. When this pm is driven from an external source,
the voltage should be referenced to VSS.
CLOCK (Clk I, Clk.b, Pins 10, 111
The MCl4433 device contains its ,?wn oscillator system
clock. A single resistor connected betw.een pins 10 and 11
sets the clock frequency. If increased stability is desired,
these pins Will support a crystal 'or LC circuit. The clock input, Pin 10, may also be driven from an exteinal clock source
which need have only standard CMOS outp'ut drive. For external clock inputs this pin IS refere~ced to" VEE.' A 300 kO
resistor resultS in clock frequency of about 66 kHz. (See the
typical characteristic' curves.> For alternate cirCUits see
Figure 7.
.

EXTERNAL COMPONENTS (RI, RIICI, CI; Pins 4, 5, 6)
. These pins are for external components for the integration
used in the dual ramp AID conversion".A typical value for
the capacitor is' 0.1 p.F '(polystyrene or mylar) while the
resistor should be 470 kO' for 2.0 V full scale operation and
27 kO for 200 mV full scale operation. These values are for·a
66 kHz clock frequency which will produce a conversion time
0( approx.imately 250 ms. The equations governing the
calculation for the values for integrator components are as
follows:
.
. VXlmax)
T
RI=-C-I- x 6V

. NEGATIVE POWER SUPPLY (VEE, Pin 12)
This is the connection for the most negative power supply
v~lt~ge. The typical current is 0.8 mAo Note the current for
the output drive cirCUit is not returned through this pin, but
through Pin 13. VX-VEE should be greater than 0.8 V.

6V=VDD-Vx(max)-0.5 V

'T=4000X~
fClk

NEGATIVE POWER SUPPLY FOR OUTPUT
CIRCUITRY ANO INPUT DU(VSS, Pin 131
This is the low voltage level for the output pins of the
MCl4433 (BCD, Digit Selects, EOC, OR) and the DU input.
When this pin is connected to analog ground, the output
voltage is from analog ground to VDD. When connected to
VEE, the output swing is from VEE to VDD. The allowable
operating range for VSS is between VDD - 3.0 volts and
VEE·

where:
RI is in kO'
VDD is the voltage at Pin 24 referenced to VAG
Vx is the voltage at Pin 3 referenced to VAG, in V
fClk is the clock frequency at Pin 10 in kHz
CI is in p.F. 6V is in Volts
.
"(is the conversion time, in seconds
Example:
CI=O.l p.F
V[)O = 5.0 volts
fClk=66 kHz'
. For Vxlmax) = 2.0 volts
RI=4BO kO luse 470 kO±5%)

END OF CONVERSION (EOC, Pin 141
The EOC output produces a positive pulse at the end of.
each conversion cycle: This pulse width is equivalent to one
half the period of the system clock .( Pin 111.

3-6

MC14433

TRUTH TABLE IDS1 = 11

OVERRANGE (OR, Pin 15)
The OR pin is low when Vx exceeds V ref. Normally It is
high.

Coded Condition
of MSD

03

02

01

00

BCD to 7 Segment
Decoding

Blank
1
1
+0
1
0
-0
1
0
1
0
Blank
1
1
+0 UR
1
1
Blank
-0 UR
1
1
1
0
Blank
1
+1
0
0
0
Hook up
-1
0
0
0
0-1 only seg b
0
7-1 and c to
+10R
0
1
1
1
-lOR
1
3-1 MSD
1
0
0
Notes for Truth Table.
03 - l> digit, low for "1", high for "0"
Q2 - Polarity' "1" = positive, "a" = negative
00 - Out of range condition exists If ao= 1 When used in conjunction with 03 the type of out of range condition IS indicated, i.e., 03=0-OR or 03= l-UR.

DIGIT SELECT (054, OS3, OS2, OSl; Pins 16, 17, 18, 19)
The digit select output is high when the respective digit is
selected. The most significant digit (y, digiti turns on immediately after an EOC pulse followed by the remaining
digits, sequencing from MSD to LSD. An Interdlgit blanking
time of two clock periods IS included to ensure that the BCD
data has settled. The multiplex rate is equal to the clock frequency divided by SO. Thus with a system clock rate of 66
kHz, the multiplex rate would be 0.8 kHz. Relative timing
among digital select outputs and the EOC signal is shown in
the Digit Select Timing Diagram, Figure 8.

4-]

BCD DATA OUTPUTS (00, aI, 02, 03, Pins 20, 21, 22, 23)
Multiplexed BCD outputs contain 3 full digits of information during DS2, 3, 4, while during DS1, the Y, digit, overrange, underrange and polarity are available. The adjacent
truth table shows the formats of the information during DS 1.

When only segment band c of the decoder are connected to the
l> digit of the display 4, 0, 7 and 3 appear as 1.
The overrange Indication (Q3=0 and QO= 1) occurs when the
count IS greater than 1999, e.g., 1.999 V for a reference of 2.000 V.
The underrange indication, useful tor autorangmQ CircUIts, occurs
when the count IS less than ISO, e.g., O.ISO V for a reference of
2.000 V.

POSITIVE POWER SUPPLY (VOO, Pin 24)
The most positive supply voltage pin. VDD - Vx should be
greater than 2.5 V. VDD- VEE should be greater than 7.8 V.
VDD determines VOH for the digital outputs, and VIH for the
digital inputs.

Caution: If the most significant digit IS connected to a display other
than a '.,.' only; such as a full digit display, segments other than b
and c must be disconnected. The BCD to seven segment decoder
must blank on BCD Inputs 1010 to 1111.

FIGURE 7 - ALTERNATE OSCILLATOR CIRCUITS
la) CIYSIaI Oscillator Circuit

Ib) LC Oscillator Circuit

r - - -...._ _~,.....'-"t1O Clk I

c::::=J

18 M

10

(
(~

MCI4433

~-'VI/Ir-4~I-'l1 Clk 0

Clkl

C±

MCI4433
11 ClkO

47 k

:!::::
f=.l.
2.. •V

'2iLC
LILl..

For L= 5 mH and C =0.01 ~F, f .. 32 kHz

10 pF Clock Cycle

~ 16.400

Clock Cycles
between EOC pulses

-----<

Ii"OI(f-----)l)oo(-l 18 Clock Cycles
DSllMSDIJ
l> Digit
2 Clock Cycles

I

L._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1

IBlankJngTlme)~

F

DS2 - - - - - - - - ' .

~--------------~~

DS3-----------~

DS4
ILSDI------------------'

3·7

--IL

•

MC14433

FIGURE 9 -

Start

t

TIme

INTEGRATOR WAVEFORMS AT PIN 6

t
2

FIGURE 10 - EQUIVALENT CIRCUIT DIAGRAMS OF THE
ANALOG SECTION DURING SEGMENT 4
OF THE TIMING CYCLE

End
3

4

t

Buffer

Segment

Integrator

Comparator

CI

Number

II
CIRCUIT OPERATION
grator amplifiers, is charged during this period. Also, the
integrator capacitor is shorted. This segment requires· 4000
clock periods.
Segment 2 - The Integrator output decreases to the comparator threshold voltage. At this time a number of counts
equivalent to the input offset voltage of the comparator IS
stored in the offset latches for later use in the autozero process. The time for this segment is vanable, and less than 800
clock perIOds.
Segment 3 - This segment of the conversion cycle is the
same as Segment 1.
Segment 4 - Segment 4 is an up-going ramp cycle with
the unknown input voltage (Vx) as the input to the integrator. Figure 10 shows the equivalent configuration of the
analog section of the MC14433. The actual configuration of
the analog section is dependent upon the polarity of the input voltage during the previous conversion cycle.
Segment 5 - This segment is a down-going ramp period
with the reference voltage as the input to the integrator.
Segment 5 of the conversion cycle has a time equal to the
number of counts stored in the offset storage latches during
Segment 2. As a result, the system zeros automatically.
Segment 6 - This is an extension of Segment 5. The time
period for this portion is 4000 clock ·periods. The results of
the AI D conversion cycle are determined in this portion of
the conversion cycle.

The MC14433 CMOS in1egrated circUit, together with a
minimum number of external components, forms a modified
dual ramp AID converter. The device contains the
customary CMOS digital logic providing counters, latches,
and multiplexing circuitry as well as the CMOS analog circuitry proViding operational amplifiers and comparators required to Implement a complete single chip AI D. Autozero,
high input impedances, and autopolarity are features of this
system. Using CMOS technology, an AID with a wide range
of power supply voltage and low power consumption is now
available with the MC14433.
During each conversion, the offset voltages of the internal
amplifiers and comparators are compensated for by the
system's autozero operation. Also each conversion 'ratlometrically' measures the unknown Input voltage. In other
words, the output reading is the ratio of the unknown
voltage to the reference voltage with a ratio of 1 equal to the
maximum count 1999. The entire conversion cycle requires
slightly more than 16000 clock periods and may be divided into six different segments. The waveforms showing the conversion cycle with a positive input and a negative input are
shown In Figure 9. The SIX segments of these waveforms are
described below.
Segment 1 - The offset capacitor (Col, which compensates for the input offset voltages of the buffer and inte-

3·8

MC14433
FIGURE 11 - 3Y, DIGIT VOLTMETER-COMMON ANODE DISPLAYS. FLASHING OVERRANGE
MCI403

+5V

+5V
Segment Resistors
1500171

Vx

4
2
3
5

3
1
21
20

AI"
4
5
6

13
7

o 1 ~F

al

10

U

11
12
13
14

:z..,.
:;<

MC14433

01 "F* *

9

-5V'

715

7
6
5
4
3
2
1
-5V

9

8

C")

::;:

U

:;<

10
11
12
13
14
15
16

Minus Sign

15

*RI=470 kO for 2 V Range
RI = 27 kO for 200 mV Range

* * Mylar Capacitor

APPLICATIONS INFORMATION

The display uses an LED display with common anode digit
lines driven with an MC14543B decoder and an MC1413 LED
driver. The MC1413 contains 7 Darlington transistor drivers
and resistors to drive the segments of the display. The digit
drive is provided by four MPS-A12 Darlington transistors
operating In an emitter follower configuration. The
MC14543B. MC14013B and LED displays are referenced to
VEE via Pin 13 of the MC14433. This places the full power
supply voltage across the display. The current for the display
may be adjusted by the value of the segment resistors shown
as 150 ohms in the above figure.
The power supply for the system is shown as a dual ± 5 V
supply. However. the MC14433 will operate over a wide
range of Voltages. and balance between the + 5 and - 5 V
supplies is not required. See the recommended operating
conditions and Figure 1.

3Y, DIGIT VOLTMETER - COMMON ANODE
DISPLAYS. FLASHING OVER RANGE
An example of a 3% digit voltmeter using the MC14433 is
shown in the circuit diagram of Figure 11. The reference
voltage for the system uses an MC1403 2.5 V reference IC.
The full scale potentiometer can calibrate for a full scale of
199.9 mV or 1.999 V. When switching from 2 V to 200 mV
operation. RI is also changed. as shown on the diagram.
When uSing RC equal to 300 kll. the clock frequenqy for
the system is about 66 kHz. The resulting conversion time is
approximately 250 ms.
When the input is overrange. the display flashes on and
off. The flashing rate is one-half the conversion rate. This is
done by dividing the EOC pulse rate by 2 with % MC14013B
flip-flop and blanking the display using the blanking input of
the MC14543B.

3-9

•

MC14433
FIGURE 12 - 3

* DIGIT VOLTMETER WITH LOW COMPONENT COUNT

470 kt 0.1 "F
~L

I

Input

•

+5 -

RI
Vx

Vx

*c
* r

Zener Diode
or
MC1403
Reference

J

I

RI/CI

0 1 "F

r~CO2

CI COl

Clk I

300k

ClkO

VAG

MCl4433

OU
EOC

A
8
C
0

00
01
02
03

Vrel

VSSh
VODf---VEErOS4

Resistor Network
or Individual Resistors

MC145118

OR

+~LT

Ir;:'

R

81

a
b
e
d
e
I
voog

~ ~

OS30S2
OS1

ROp

for Vrel=2.000 V
Vx: 1.999 V full scale

I

RM
VEE*
IMlnusl

rVref= 200.0 mV
Vx: 199.9 mV full scale
lehange 470 kG to RI = 27 kG
and decimal POint position)

+5V

I
Minus
Control

*V EE can range between - 2.8 and
11 V. Also see Figure 18 lor
gative supply generated from a
positlve supply.

n.

- I. BBB
I
I

I

Comma
Cathod
LED
Olspla

517 MC1413
DI91t Dnver

Alternate Overrange CircUit
with Separate LED

OR~1I7MC14131f---<1t---~~+5V

!

.

~~

choice of the designer, the values of resistors R, RM, RDP,
and RR that govern brightness are not given.
During an overrange condition Hie 3Yz digit display is
blanked at the BI pin on the MC14511 B. The decimal potnt
and minus sign will remain on dUring a negative overrange
condition. In addition, an alternate overrange circuit with
separate LED is shown.

3 Yz DIGIT VOLTMETER WITH LOW COMPONENT
COUNT USING COMMON CATHODE DISPLAYS
The 3* digit voltmeter of Figure 12 is an example of the
use of lhe MC14433 in a system with a minimum of components. This circuit uses only 11 components In addition to
the MC14433 to operate the MC14433 and drive the LED
displays.
In this circuit the MC14511 B provides the segment drive
for the 3Yz digits. The MC1413 provides sink for digit current. (The MC1413 is a deVice with 7 Darlingtons with common emitters.) The worst case digit current IS 7 times the
segment current at )4 duty cycle. The peak segment current
is limited by the value of R. The current for the display flows
from VDD (+ 5 V) 10 ground and does not flow through the
VEE (negative) supply. The minus sign is controlled by one
section of the MC1413 and is turned off by shunting the current through RM to ground, bypassing the minus sign LED.
The minus sign is derived from the Q2 output. The decimal
point brightness is controlled by resistor RDP. Since the
brightness and the type and size of LED display are the

3Yz DIGIT VOLTMETER WITH LCD DISPLAY
A circuit for a 3* digit voltmeter with a liquid crystal
display is shown 10 Figure 13. Three MC14543B LCD latch/
decoder/display drivers are used to demultiplex, decode the
three digits, and drive the LCD. The half digit and polarity are
demultiplexed with the MC14013B dual 0 flip-flop.
Since the LCD IS best driven by an ac signal across the
LCD, the low-frequency square wave drive for the LCD is
derived from the MC14024B binary counter which divides the
digit select output from the A/D. This low frequency square
wave IS connected to the backplane of the LCD and to the Individual segments through the combination of the output cir-

3·10

MC14433
FIGURE 13 - 3 Y.o DIGIT VOLTMETER WITH LCD DISPLAY

•
+V

-v

FIGURE 14 - TWO CIRCUITS FOR GENERATION
OF Vref AND VAG FROM A SINGLE SUPPLY

cuitry of the MC14543B and the exclusive OR gates at the
outputs of the MCI4013B. Alternatively the square wave can
be derived from a 50/60 Hz mput signal when available.
The minus sign and the decimal point to the right of the
half digit are connected to the inverted low frequency square
wave signal. Unused decimal points are tied directly to the
low frequency square wave.
The system shown operates from two power supplies
(plus and minus). Alternatively one supply can be used when
VSS is connected to VEE. In this case a level must be set for
analog ground, VAG, which must be at least 2.8 V above
VEE. This circuit may be implemented with a resistor network, resistor/forward-biased diode network or resistorzener diode network. For example, a 9 V supply can be used
with 3 V between VAG and VEE, leaving 6 V for VOO to
VAG. This system leaves a comfortable margin for battery
degeneration (end of life). Two versions of this cirCUit for
smgle supply operation is shown in Figure 14.
For panel meter operation from a single 5 V supply, a
negative supply can be generated as shown in Figure lB.

Voo

Voo

.-----<~-..,Vref

VEE

3-11

VEE

II
3:

FIGURE 15 -

3~

o
....

DIGIT AUTORANGING MUL TIMETER

S
w

V'N

Common Anall.· LEO D"l'ldV

.EU1B

v,"

r;
",

fv"
r;

".

W,X,Y,Z Connect
loOhm.Sthemal,c

~
.....

I\)

®"

Relays - Clare MRJIA12

SIa·y
52-a,lI
53

3 Position, 7 Pole (Functlonj
- 2Po5It,on,2PolejAC·OCI
2 PuSltt()n,I PolelHoldl

DectmalPOlnlIn
7S..gmenID,.pI""

lSOH VDlsplay

~"
A Display

~+,

,+:

@dP

DedmalPolnlln

KUO'$play

7SegmentD,splav

'500

@dP
470H
Dec,maIPo,nl,n
7 Segmenl Display
150U m Drsptay

All 2 Input NAND
All 4 Input NAND
Alllnver1ers

MCl40118,
MCl40128
MCl4049UB

All TransmiSSIon Gates MCl40668

-.-"

MC14433
PARALLEL BCD DATA OUTPUT CIRCUIT
The output of the MC14433 may be demultiplexed to produce parallel BCD data as shown in Figure 16. Two levels of
latches are required for a complete demultiplexlng of the
data since the outputs of the MCl4042B latches change sequentially With the DSI to DS4 strobe pulses. To key output
validity to one leading edge, I.e., that of the EOC Signal of
the MCl4433, information IS transferred to the second set of
latches (MC14175B latches!. A single set of latches can be
used when reading of output is restricted to within 12,000
clock pulses after EOC. This requires synchronous system
operation with respect to the BCD data bus
In this system the output ground level is VSS. In most
cases, a two supply system with VSS connected to VAG is
recommended. This allows connecting analog ground and
digital ground together without destroying a power supply .
This circuit works well With that of Figure 12.

3l!. DIGIT AUTORANGING MULTIMETER
An autoranging multi meter including ac and dc voltage
ranges from 200 mV to 200 V, ac and dc current from 2 mA
to 2 A fullscale and resistance ranges from 2 kll to 2 Mil fullscale is shown in Figure 15. In this multimeter only two input
jacks are required for all ranges and functions, eliminating
the need for changing leads on the Instrument when changing ranges or functions. Although only four ranges are provided for each function, the technique used may be expanded to more ranges if desired. Range switching uses
mechanical relays. However, the relays may be replaced with
solid state analog switches.
The MCl4433 provides the overrange and underrange
control signals for the automatic ranging circuits. For additional information, see Motorola Application Note AN-769,
.. Autoranging Digital Multimeter Using the MC14433 CMOS
AI D Converter."

FIGURE 16 - DEMULTIPLEXING FOR MCI4433 BCD DATA
Multiplexed
DS3 DS4

BCD

DSI DS2

!i

1

DO Dl
D- Pol

I

I I
D2 D3

MCI4042B Ct--

-

C MCI4042B Pol

I

l J

Pol

I I

C _VD~A

1 ~sJ 1

MC14175B

I I

DO Dl D2 D3

MCI4042B C -

-

C MCI4042B

00 0102 03

I I

DO Dl D2 D3
Cr-

VDD-A

MC14175B

Pol t--VD D

00 01 02 03

I I

DO Dl D2 D3

OO 01 02 03

I

r

DO Dl D2 D3

00 01 02 03

DO Dl D2 D3
MC14175B

I

VDD

DO Dl D2 D3

0001 02 03

VD D-A

I

I I

DO Dl D2 D3
C - VD!:!....-A

00 01 02 03

GO 01 Q2 03

111 1

1111

MC14175B

Cr-

00 01 02 03

1 tJ 1
EOC

3·13

•

MC14433
FIGURE 17 - CHANNEL DATA ACQUISITION HARDWARE
r-------~--------~------------------~---------------+5

,--------+-----------------5

.---------IRQ
, - - - - - - Restart

,------R/Vii

Co
AG

II

8

VDD

X7

DS4
DS3
DS2
DSl
03
Q2
Ql
00

MCl4433

X~----------~VX

ClkO
300 k

X6

Clk I

6

VSS

X5

DU

EOC

CBl
CB2
+5V
+5V +5V
PA7
10k
PA6
X3
PA5
+5
PM
X2
PA3
Xl
C~~---t----+_--------------------~ PA2
PAl
Br-----~~+_----------------~
XO [fJ AI---------+--------------1 PAO CSO ~
VEE:: lNH
X4

4
3

Analog
Inputs

VSS
PB4
PB3
PB2
PBl
PBO

GND

D7
D6
D5
D4
Data
Bus

MC6B21
D3
02
Dl
DO

To MC6BOO
System

CAl

-5
}

Address
Bus

nel to be measured via the MCl4051 B analog multiplexer.
Control lines CBl and CB2 are used for data !fow control and
are connected to DU and EOC of the MCl4433.
A more detailed explanation of this system including the
actual software required for the M6800 microprocessor may
be found in Motorola Application Note AN-770, "Data Acquisition Networks With NMOS and. CMOS."

8 CHANNEL DATA ACQUISITION NETWORK
Figure 17 shows an 8-channel data acquisition network using the MCl4433 and an MC6800 microprocessor system.
The interface between the microprocessor data bus and the
AID system IS done with an MC6821 PIA. One half of the
PIA is used with the BCD and digit select outputs of the
MCl4433, while the second half of the PIA selects the chan-

FIGURE 18 - NEGATIVE SUPPLY GENERATED FROM POSITIVE SUPPLY
1/6 MCl4049UB

NEGATIVE SUPPLY GENERATED FROM POSITIVE
SUPPLY
When only + 5 V is available, a negative supply voltage
can be generated with the circuit of Figure 18 using one
MCl4049UB. Two inverters from CMOS hex inverter are
used as an oscillator ( = 3 kHzl with the remaining inverters
used as buffers for higher current output. The square wave
output from the oscillator is level-translated to a negative going signal. This signal is rectified and filtered. A VOD voltage
of + 5 V for the hex buffer will result in a - 4.3 V no load output voltage while the output with a 2 mA load is =3.4 V.

VDD=5 V
vSS=O V

510K

3-14

®

MC14435

MOTOROLA

3-1/2 DIGIT AID LOGIC SUBSYSTEM

CMOS LSI
flOIlV·POIIVER COMPLEMENTARY MOS)

The MC14435 AID Logic is designed specifically for use in
a dual·slope integration AID converter system.
The device consists of 3·112 digits of BCD counters, 13 memory
latches, and output multiplexing circuitry. An internal clock ascii·
lator IS provided to generate system timing and to set the output
multiplexing rate. A single capacitor IS required to set the oscillator
frequency.
•

On·Chip Clock to Control Digit Select, Multiplexing, and BCD
Counters Simultaneously

•

Multiplexed BCD Output

•

Built·ln 100·Count Delay for Accurate System Conversion of
Low·Level Inputs

•

System Over· Range Output

•

Linear Companion Dev!ce Available From Motorola

•

(MC1405L/1505U
Supply Voltage Range

3-1/2 DIGIT AID LOGIC
SUBSYSTEM

l SUFFIX
C~RAMIC

= 3.0 Vdc to 18 Vdc (MC14435 EFL/FLlFP)
= 3.0 Vdc to 6.0 Vdc (MCI4435EVL/VL/VP)

PACKAGE

CASE 620

P SUFFIX

MAXIMUM RATINGS (Voltages referenced to VSS Pin 8 )

PLASTIC PACKAGE

Rating

Symbol

DC Supply Voltage

Value

Input Voltage, All Inputs

+18 to -0.5
+6.0 to -0.5
Vm

DC Current Drain per Pin

Operating Temperature Range MC14435EFLlEVL
MC14435FLlFP/VL/VP
Storage Temperature Range

CASE 648

Vdc

VDD
- MC14435EFLIFL/FP
- MC14435EVLlVL/vP

Unit

VDD +0.5
to VSS -0.5

Vdc

I

10

mAde

TA

-55 to +125
-40 to +85

°c

T stg

-65to +150

°c

PIN ASSIGNMENT

16
15

PRODUCT CANCELLED

14
4

13

6

11

12

Refer to Other AI D Converters Listed
in the Function Selector Guide of This
Book

3-15

10
9

•

®

MC14442

MOTOROLA

CMOS LSI
(LOW-POWER SILICON GATE
COMPLEMENTARY MOS)

ANALOG-TO-DIGITAL CONVERTER (ADC)

•

The MCl4442 ADC is a 28-pin bus-compatible 8-bit AID converter
with additional digital input capability. The device operates from a
single 5 V supply and provides direct interface to the M PU data bus
used with all Motorola M6800 family parts. It performs an 8-bit conversion in 32 machine cycles and allows up to 11 analog inputs. In addition,
the part can accept up to 6 digital inputs. These inputs are designed to
be either analog or digital inputs. All necessary logic for software configuration, channel selection, conversion control ane;! bus interface is included.

MICROPROCESSOR-COMPATIBLE
ANALOG-T()':DIGITAL CONVERTER

L SUFFIX

• Direct Interface-to M6800 Family MPUs
• Dynamic Successive Approximation AID
• 32,.s Conversion at fE= 1.0 MHz
• Ratiometric Conversion
• Completely Programmable
• Completely Software Compatible with the MCl4444 ADC
• 5 Dedicated Analog Inputs
• 6 Inputs Usable for Either Analog or Digital Signals
• Completely TTL Compatible Inputs at Full Speed with Supply
Voltage of 5 V ± 10%

CERAMIC PACKAGE
CASE 733

P SUFFIX
PLASTIC PACKAGE
CASE 710

ORDERING INFORMATION

MC14XXXt~

Suffix Denotes
Ceramic Package
PI~stic

Package

BLOCK DIAGRAM AND PIN ASSIGNMENT

11

11

PO-P5

4

6

Analog
Data
Register
(Read Only)

4

8
00-07

8

VAG

1

Digilal
Data
Register
(Read Only)

8
8

CS
RS1

Reset
E

3-16

28 Vref

VSS

27

VOO

07

26

AND

D6

25

AN2

05

24

AN3

D4

23

AN4

03

22

AN5

02

21

PO!ANto)

20 P1tAN11)

DO

10

,.

R/iN

11

18

P3(ANS)

12

17

P4(AN6)

RSl

13

16

P5(AN7)

CS

14

15

Reset

01

A0-3

R/W

ANO
AN2-AN5
PO-P5

P2{AN8)

MC14442

MAXIMUM RATINGS*
Parameter

Value

Unit

-0.5 to +6.5

V

DC Input Voltage (Referenced to VSSI

-0.5 to VCC+O 5

V

DC Output Voltage (Referenced to VSSI

-0.5 to VCC+O 5

V

DC Input Current. per Pm

±10

mA

lout

DC Output Current. per Pin

±1O

mA

10D

DC Supply Current. VDD and VSS Pins

±20

mA

PD

Power DISSipation, per Package t

500

mW

Symbol
VDD

DC Supply Voltage (Referenced to VSSI

Vm
Vout
1m

65 to + 150

Storage Temperature

Tstg

Lead Temperature (lO-Second Solderlngl

TL

300

This device contams circuitry to protect the
mputs against damage due to high static
voltages or electric fields; however, It IS advised that normal precautions be taken to
aVOid applications of any voltage higher than
maximum rated voltages to this high impedance Circuit For proper operation It IS

recommended that V In and Vout be constrained to the range VSSs(V m or
VoutlsVDD
Unused inputs must always be tied to an
appropriate logrc voltage level le.g .. either
VSS or VDDI.

'c
'c

* MaXimum Ratmgs are those values beyond which damage to the deVice may occur.
tPower Dissipation Temperature Derating:
Plastic "P" Package: -12mW/'C from 65'C to 85'C
Ceramic" Lit Package: no derating

DC ELECTRICAL CHARACTERISTICS (VDD=5.0 V ± 10%. VSS= 0 V. TA= -40'C to 85'C unless otherwise notedl

I

I Symbol I

Characteristic

Conditions

I

Min

I

Max

Unit

2.0

-

V

-

0.8

V

±10

p.A

Bus Control Inputs (R/W, Enable, Reset, RS1, CSI
Input High Voltage
Input Low Voltage
Input Leakage Current

Vin-O to 5.5 V

Data Bus (00-07)

Input High Voltage
Input Low Voltage

VIH
V IL

Three-State (Off Statel Input Leakage Current

ITSI

VDD-55 V.
VSSSVinSVDD

Output High Voltage

VOH

10H- -1.6 mA

24

-

V

Output Low Voltage

VOL

10L = 1.6 mA

-

0.4

V
V

Peropherallnputs IPO-P51
Input High Voltage

VIH

2.0

-

Input Low Voltage

VIL

0.8

V

Input Leakage Current

lin

-

±1.0

p.A

VOD-5.5 V.
VSSSVmsVDD

Current ReqUirements

Supply Current

VOD-5.5 V

Input Current, V ref

Vref-4 5 to 5.5 V

ANALOG CHARACTERISTICS (TA = -40'C to 85'CI

I

Characteristic

!

Description

Min

Max

Unit

Analog Multiplexer
Leakage Current

Leakage current between all deselected analog inputs and any selected
analog Input With all analog Input voltages between VSS and VOO

AID Converter (VSS=O V, VAG=O V, 4.5 VsVrefsVDDS5.5 V)
Resolution

Number of bits resolved by the AI D

8

-

Bits

Nonlinearity

MaXimum deViation from the best straight line through the AID transfer
characteristic

-

±Y2

LSB

Zero Error

Difference between the output of an Ideal and an actual AI D for zero
Input voltage

-

±%

LSB

Full-Scale Error

Difference between the output of an Ideal and an actual AI D for full-scale
Input voltage

-

±II

LSB

Total Unadjusted Error

MaXimum sum of Nonlinearity, Zero Error, and Full-Scale Error

-

±Y2

LSB

Quantization Error

Uncertainty due to converter resolution

-

±Y2

LSB

Absolute Accuracy

Difference between the actual Input voltage and the full-scale weighted
equivalent of the binary output code, all error sources Included

-

±10

LSB

Conversion Time

Total time to perform a Single analeg-to-dIQltal conversion

-

32

E cycles

Sample AcqUiSition Time

Time

-

12

E cycles

requlr~d

to sample the analog Input

3·17

•

MC14442
AC CHARACTERISTICS IT A = - 40° to 85°C) ISee Figure 1)
Characteristic

Enable

Cloc~

Min

Max

Un~

tcyclE)
PWHIE)

943

ns

440

-

E
E

PWLIE)

410

-

trlE)
tflE)

-

tAS

145

25
30
-

ns

E

335
-

ns

E

Pulse Width, Low

Clock Rise Time
Clock Fall Time
Address Setup Time

•

Symbol

Signal
E

Enable Clock Cycle Time 11/fE)
Enable Clock Pulse Width, High

RS1, R/W,

CS

Data Delay I Read)

DO-D7

tDDR

Data Setup IWrite)

DO-D7
RS1, R/W, CS
DO-D7

tDSW

185

tAH
tDHW

10
10
10

Address Hold Time
Input Data Hold Time
Output Data Hold Time

DO-D7

Input Capacitance

PO-P5,
ANO-AN10,
R/W, E, RS1,
CS, RESET
DO-D7

Three-State Output Capacitance

tDHR
Cin

Cout

ns
ns
ns
ns
ns
ns
ns

-

-

ns
pF

55

-

15

-

15

pF

FIGURE 1 - BUS TIMING
~---------------tcycIE)---------------J~

/ + - - - - - - P W L l E ) -------i~ j-ool-------PWHIE) -------I~
2.0
08

trlE)
/+--~--tAS---~

R/W,

2.0V

CS,
RSl

0.8V

tDDR

2.4

MPU
Read

2.4
DO-D7

0.4

0.4

tDHW

2.0

MPU

2.0
DO-D7

Write

0.8

3·18

0.8

MC14442
PIN FUNCTIONS
Pin No.
Pin Name
1

VAG

MCl4442 MPU INTERFACE SIGNALS
Type

Function

A/D Converter Analog Ground

Supply
Supply

2

VSS

3

07

Data Bus Bit 7 IMSBI

Input/Output

4

06

Data Bus Bit 6

Input/Output

5

05

Data Bus Bit 5

Input/Output

6

04

Data Bus Bit 4

Input/Output
Input/ Output

Digital Ground

7

03

Data Bus B,t 3

8

02

Data Bus Bit 2

Input/ Output

9

01

Data Bus Bit 1

Input/Output

Data Bus Bit 0 ILSBI

Input/Output

10

DO

11

R/W

Read/Write

Input

12

E

Enable Clock 121

Input

13

RS1

Register Select

Input

14

CS

Chip Select

Input

15

Reset

Reset

Input

16

P51AN71

Digital Port or Analog Channel 7

Input

17

P41AN61

Digital Port or Analog Channel 6

Input

18

P31AN91

Digital Port or Analog Channel 9

Input

19

P21AN81

Digital Port or Analog Channel 8

Input

20

PlIAN111 Digital Port or Analog Channel 11

Input

21

POIAN101 Digital Port or Analog Channel 10

Input

22

AN5

Analog Channel 5

Input

23

AN4

Analog Channel 4

Input

24

AN3

Analog Channel 3

Input

25

AN2

Analog Channel 2

Input

26

ANO

Analog Channel 0

27

VDD

Supply Voltage

28

Vref

AID Converter Positive Reference
Voltage

Input
Supply
Input

Bidirectional Data Bus (00-07) - The bidirectional data
lines DO-D7 comprise the bus over which data is transferred
in parallel to and from the M PU. The data bus output dnvms
are three-state devices that remain In the high-Impedence
state except during an MPU read of an ADC data register
Enable Clock (E) - The enable clock provides two func·
tlons for the MCl4442. First, It serves to synchronize data
transfers into and out of the ADC. The timing of all other external signals IS referenced to the leading or trailing edge of
the enable clock. Secondly, the enable clock is used internally to derive the necessary SAR AID conversion clocks.
Because this conversion is a dynamiC process, enable clock
must be a continuous signal into the ADC during an AI D
conversion.
ReadlWrite (R/W) - The R/W signal is provided to the
MCl4442 to control the direction of data transfers to and
from the MPU. A low state on this line is required to transfer
data from the MPU to the ADC control register. A high state
is required on R/W to transfer data out of either of the ADC
data registers.
Reset (Reset) - The reset line supplies the means of
externally forcing the MCl4442 into a known state. When a
low is applied to the Reset pin, the start conversion bit of
the control register is cleared. Analog channel 0 is
automatically selected by the analog multiplexer. The AID
status bit is also cleared. Any AI D results present in the
Analog Data register are not affected by a reset. Reset forces
the data bus output drivers to the high-impedance state. The
internal byte pointer (discussed in the following pages) is set
to point to the most significant byte of any subsequently
selected internal register. In order to attain an internally
stable reset state, the Reset pin must be low for at least one
complete enable clock cycle.
Chip Select (~) - Chip select is an active-low input used
by the MPU system to enable the ADC for data transfers. No
data may be passed to or from the ADC through the data bus
pins unless CS is in a low state. A selection of MPU address
lines and the M6800 VMA signal or its equivalent should be
utilized to provide chip select to the MCl4442.

MCl4442 ANALOG INPUTS AND DIGITAL INPUTS
(Refer to the ADC Block Diagram)
Dedicated Analog Channels (AND, AN2-AN5) - These
input pins serve as dedicated analog channels subject to AID
conversions. These channels are fed directly into the internal
12-to-1 analog multiplexer which feeds a single analog
voltage to the AI D converter.

Shared Analog Channels (AN6-AN11) - These input pins
are also connected to the analog multiplexer and may be
used as analog channels for AID conversion. However,
these pins may also serve as digital input pins as described
next.

3-19

•

MC14442

•

Shared Digital Inputs (PO-PS) - PO-P5 comprise a 6-bit
digital input port whose bits may also serve as analog channels. The state of these inputs may be read at any time from
the ADC digital data register. The function of these pins is
not programmed, but Instead is simply assigned by the
system designer on a pin-by-pin basis.

may be degraded if VAG is wired to VSS at the ADC
package unless VSS has been sufficiently filtered to remove
switching noise. Ideally V AG should be single-point grounded to the system analog ground supply.

CAUTION: Digital values read from the PO-P5 bit
locations do not guarantee the presence of true dig-·
ital input levels on these pins. PO-P5 pass through a
TTL-compatible input buffer and into the digital data
register. These buffers are designed with enough
hysteresis to prevent internal oscillations if an analog
voltage between 0.8 and 2 V is present on one or
more of these six pins.

The MC14442 ADC has three 16-bit internal registers. Each
register is divided into two 8-bit bytes: a most significant
(MSI byte (bits 8-15) and a least significant (LS) byte (bits
0-7). Each of these bytes may not be addressed externally,
but instead are normally addressed by a single 16-bit instruction such as the M6800 LDX instruction. An internal byte
pointer selects the appropriate register byte during the two E
cycles of a normal 16-bit access. In keeping with the M6800
X register format, the pointer points first to the MS byte of
any selected register. After the E cycle in which the MS byte
is accessed, the pointer will switch to the LS byte and remain
there for as long as chip select is low. The pointer moves
back to the MS byte on the falling edge of E after the first
complete E cycle In which the ADC is not selected. (See
Figure 2a for more detaiLl The MS byte of any register may
also be accessed by a simple 8-bit instruction as shown in
Figure 2b. However, the LS byte of all registers may be
accessed only by 16-bit instructions as described above. By
connecting the ADC register select (RS1) to the MPU
address line A 1, the three registers may be accessed sequentially by 16-bit operations.

MCl4442 INTERNAL REGISTERS

MCl4442 SUPPLY VOLTAGE PINS
Positive Supply Voltage (VDD) - VDD is used internally
to supply power to all digital logic and to the chopper
stabilized comparator. Because the output buffers connected to this supply must drive capacitive loads, ac noise on
this supply line is unavoidable internally. Analog circuits using this supply within the MC14442 were designed with high
VDD supply rejection; however, it is recommended that a
filtering capacitance be used externally between VDD and
VSS to filter noise caused by transient current spikes.
Ground Supply Voltage (VSS) - VSS should be tied to
system digital ground or the negative terminal of the VDD
power source. Again, the output buffers cause internal noise
on this supply, so analog circuits were designed with high
VSS rejection.

CAUTION: RS1 should not be connected to
address line AO and the addressing of the ADC
should be such that RS1 does not change states
during a 16-bit access.

Positive AID Reference Voltage (Vret) - This is the
voltage used internally to provide references to the analog
comparator and the digital-to-analog converter used by the
SAR AID. The analog-to-digital conversion result will be
ratio metric to Vref- VAG (full scale!. Hence Vref should be a
very noise-free supply. Ideally Vref should be single-point
connected to the voltage supply driving the system's
transducers. Vref may be connected to VDO, but degradation of absolute AI D accuracy may result due to switching
noise on VOO.

INTERNAL REGISTER ADDRESSING
Addressing Signals
CS R/W RS1
ReS8i
0

AID -Ground Reference Voltage (VAG) - This supply is
the ground reference for the internal DAC and several
reference voltages supplied to the comparator. It should also
be noise-free to guarantee AID accuracy. Absolute accuracy

X

X

X

ADC Response
Reset

1

0

0

0

No Response

1

0

0

1

MPU Write to Control Register

t

0

1

0

MPU Read from Analog Data
Register

1

0

1

1

MPU Read from Digital Data

1

1

X

X

Chip Deselected INo Response)

Register

3-20

MC14442
FIGURE 2 - ADC ACCESS TIMING

• - Typical 16-Bit ADC Access

•

cs ---+.

RS1,

R/IN
MS Byte
LS Byte
j . - - - - - Accessed ----i)o~""t_--- Accessed ----i~

Byte Pointer
Reset to MS Byte

b - Typical B-Bit ADC Access

E

RS1,

R/IN 1...L..1UI...lI..lf-JU '--_ _ _ _ _ _ _-¥

""........................"-'"-"-"..........+

Select
MS Byte

3·21

.......L.I...........................................................

MC14442
MC14442 CONTROL REGISTER
(Write Only)
15

o

X

AO
(LSBI

(MSBI

•

)+------8-Bit Write-----_J..
) + - - - - - - - - - - - - - - - 1 6 - B i t Write--------------_J~
Analog Multiplexer Address (AO-Al) - These four
address bits are decoded by the analog multiplexer and used
to select the appropriate analog channel as shown below.

will begin immediately after the completion of the control
register write.
Unused Bits (X) - Bits 4-7 and 9-15 of the ADC Control
Register are not used internally.

Hexadecimal Address (A3 = MSB)

Select
ANO
Vref
AN2-AN5
AN6-ANll
Undefined

o
1

2-5
6-B
C-F

NOTE: A 16-bit control register write is required to change
the analog multiplexer address. However, B-bit writes to the
MCl4442 can be used to initiate an AID conversion if the
analog MUX is already selecting the desired channel. This is
useful when repeated conversions on a particular analog
channel are necessary.

Start AID Conversion (SC) - When the SC bit is set to a
logical 1, an AID conversion on the specified analog channel

MC14442 ANALOG DATA REGISTER
(Read Only)

o

15
EOC
(MSBI

1+------8-Bit Read-------l~
~---------------16-Bit Read--------~"-----_J~

. bit is cleared by either an B-bit or a 16-bii M~U write to the
ADC control register. The r.emainder of the bits .in the MS
byte of the analog data register are always set to a logical 0
to simplify MPU interrogation of the ADC status. For example, a single M6800 TST instruction can be used to determine
the status of the AID conversion.

AID ReSult (RO-R7) - The LS byte of the analog data
register contains tilEi'result of the AID conversion. R7 is the
MSB, and the converter follows the' standard convention of
aSSigning a code of $FF to a full-scale analog'voltage. There
are no special overflow or underflow indications.
AID Status (EOC) - The AID status bit is set whenever a
conversion is successfully completed by the ADC. The status

MC14442 DIGITAL DATA REGISTER
(Read Only)
15
P5

I I I I I I I
P4

P3

P2

PI

PO

A3

8

7

A2

Al

Most Significant Byte

I I I I I I I
AO

0

0

0

0

0

o
0

Least Significant Byte

8-Bit Read
16-Bit Read
Shared Digital Port (PO-P5) - The voltage present on
these pins is interpreted as a digital Signal and the corresponding states are read from these bits.
WARNING: A digital value will be given for each pin even
if some or all of the pins are being used as analog inputs.

Logical Zero (0) - These bits are always read as logical
zero.
Analog MUltiplexer Address (AO-Al) - The number of the
analog channel presently addressed is given by these bits.

3-22

MC14442

ANALOG SUBSYSTEM
(See Siock Diagram)
2 enable clock cycles for the write into the control register
even if only one byte is written. In this case, the second E
cycle does not affect any internal registers. During the next
12Y:. enable cycles following a write command, the analog
multiplexer channel is selected and the analog input voltage
is stored on the sample and hold DAC. (t is recommended
that an input source impedance of 10 KG or less be used to
allow complete charging of the capacitive DAC.
During cycle 13 the AID is disconnected from the
multiplexer output and the successive approximation AI D
routine begins Since the analog input voltage is being held
on an internal capacitor for the entire conversion period, it is
required that the enable clock run continuously until the AID
conversion is completed. The new 8-bit result is latched into
the analog data register on the rising edge of cycle 32. At this
point the end of conversion bit (EOC) is set in the analog
data register MS byte. (See Figure 3, AID Timing
Sequence.)

General Description
The analog subsystem of the MCl4442 is composed of a
12-channel analog multiplexer, an 8-bit capacitive DAC
(digital-to-analog converter!, a chopper-stabilized comparator, a successive approximation register, and the
necessary control logic to generate a successive approximation routine.
The analog multiplexer selects one of twelve channels and
directs it to the Input of the capacitive DAC. A fullycapacitive DAC is utilized because of the excellent matching
characteristics of thin-oxide capacitors in the silicon-gate
CMOS process. The DAC actually serves several functions.
During the sample phase, the analog input voltage is applied
to the DAC which acts as a sample-and-hold circuit. During
the conversion phase, the capacitor array serves as a digitalto-analog converter. The comparator is the heart of the
ADC; it compares the unknown analog input to the output of
the DAC, which IS dflven by a conventional successiveapproximation register. The chopper-stabilized comparator
was designed for low offset voltage characteristics as well as
VDD and VSS power supply rereclion.

NOTE: The digital data register or the analog data register
may be read even if an AI D conversion is in progress. If the
analog data register is read during an AID conversion, valid
results from the previous conversion are obtained. However,
the EOC bit will be clear (logic 0) if an AI D conversion is in
progress.

Device Operation
An AID conversion IS initiated by wflting a logical 1 into
the SC bit of the ADC control register. The MCl4442 allows

FIGURE 3 MPU Write
To ADC
Control
Register

M

AID TIMING SEQUENCE

Sample Analog Input

~lInput Should Be Stablel--~."'I"O(f-------SAR AID convers
on-------~.""I
1 2 3 4 5 6 7 8 9 1 0 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

R/W

RSI
Analog Data
Register IRO-R7 _ _ _ _4 _ _ _ _ _ _ _ _V:,;a::li:::d..:D:::a:.::ta:..:..;F':.::o::.:m.:.;P~r,::e.:;vl.::o;:;us::..C::.o;:;n,;;v:.::e::,;rs;::io:::,n:,;i::;E,::D,::C:.,:C:::,le:::a:::,re:::d::I_ _ _ _ _ _ _ _ _ _-''J'. Data
Valid,
and EOCI
EOC-l

3-23

•

MC14442

FIGURE 4 - TYPICAL MCl4442 APPLICATION IN A CLIMATE CONTROLLER

ROM

•

Latch/
Decoder/

Display

Driver

'II-"I
I "

"

I

r---I+--------....------v ref
MC6802

MCl4442

MPU

ADC

~--------._----+_---------VAG

Heat/AC
Control

Duct
Damper
Control

3-24

®

MC14443
MC14447

MOTOROLA

CMOS MS.

ANALOG-TO-DIGITAL CONVERTER
LINEAR SUBSYSTEM

(LOW-POWER COMPLEMENTARY MOS)

The MCl4443 and the MCl4447 are 6-channel, single-slope, 8-10 bit
analog-to-digltal converter linear subsystems for microprocessor-based
data and control systems Contained In both devices are a one-of-8
decoder, an 8-channel analog multiplexer, a buffer amplifier, a precIsion
voltage-to-current converter, a ramp start CirCUit, and a comparator.
The output driver of the MCl4443's comparator IS an open-drain
N-channel which provides a sinking current The output driver of the
MCl4447's comparator is a standard B-Serles P-Channel, N-Channel

MICROPROCESSOR-BASED
ANALOG-TO-DIGITAL
CONVERTER

pBlr.

A processor system (such as the MC141000 or MC146805) provides
the addressing, timing, counting, and arithmetic operations reqUired for
Implementing a full analog-to-dlgital converter system. A system made
up of a processor and the linear subsystem has features such as
automatic zeroing and variable scaling (welghllngl of SIX separate
analog channels
•
•
•
•
•
•
•
•

QUiescent Current 0 8 mA Typical at VDD= 5 V
Single Supply Operation +4.5 to + 18 Volts
Direct Interface to CMOS MPUs
TYPical Resolution - 8 Bits
Typical Conversion Cycle as Fast as 300 Its
Ratio Metric Conversion Minimizes Error
Analog Input Voltage Range. VSS to VDD - 2 V
Chip Complexity: MCl4443 - 150 FETs
MCl4447 - 151 FETs

L SUFFIX

P SUFFIX

CERAMIC PACKAGE

PLASTIC PACKAGE
CASE 648

CASE 620

ORDERING INFORMATION
MC14XXX

T

SuffiX

t==

L
P

Denotes

CeramiC Package
PlastiC Package

BLOCK DIAGRAM
PIN ASSIGNMENT
15

Ch1

Ramp Start

13

Ch2

12

Ch3
Ch4
Ch5

..

3
16
15

x

14

Ci

11

.~

10

~

4

13
12

11

Ch6

9
.---_ _ _ _ _ _. -_ _+_.=--6

::tf

10

Current

Ref
Voltage
VOD

A1

="

Pin 14

VSS=Pln5

A2

3-25

8

•

MC14443, MC14447
MAXIMUM RATINGS (Voltages referenced to VSSI
Rating
OC Supply Voltage

Symbol

Value
-0.5 to + 18

VOO

Input Voltage, All Inputs

Vin

OC Input Current, per Pin

lin
TA
Tstg

Operating Temperature Range
Storage Temperature Range

This device contains circuitry to protect
the' inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be

Unit
V
V

-0 5 to VOO+0.5
± 10

taken to avoid application of any voltage
higher than maximum rated voltages to

mA

40 to +85

'C

-65 to + 150

'C

this high impedance circuit. For proper
operation it is recommended that V in and
V out be constrained to the range V 55 '"

(V in or Vou,l" voo·

•

ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSSI
Symbol

Characteristic

-40°C
Voo
V .Min Max

Min

85°C

25'C
Typ

Max

Min

Max

Unit

0.05
0.05
005

-

V

V

5.0
10
15

-

0.05
0.05
0.05

-

-

0.01
001
0.01

-

0.05
005
0.05

50
10
15

4.95
9.95
1495

-

495
995
14.95

499
999
14.99

-

495
9.95
14.95

-

50
10
15

-

-

1.5
3.0
4.0

-

225
4.50
6.75

1:5
3.0
4.0

-

1.5
30
4.0

5.0
10
15

3.5
70
11.0

-

35
7.0
11.0

2.75
550
8.25

-

3.5
70
11.0

-

5.0
5.0
10
15

-25
-052
-13
-36

-

-2.1
-0.44
-1.1
-3.0

-4.2
-0.88
-225
-8.8

-

5.0
10
15

0.52
13
3.6

-

-

044
1.1
3.0

088
225
8.8

lin

15

±0.3

-

-

±0.3

Input Current- Analog Inputs

lin

15

±0.1

±50

C,n

15

-

-

Input Capacltance- Address, Ramp Start

-

-

5.0

75

VIn=O V
QUIescent Current

100

5
10
15

-

-

0.8
1.5
17

1.5
3 O.

0

40

10

-

50

0
0
0

-

30
8.0
130

-

0.285
0400
0420

-

Output Voltage- Comparator
VIn @Pin4=OV
Vin@Pin4=1.0V
(Rpull up = 10 kll, MCl4443 onlyl
Input Voltage-Address, Ramp Start
(VO=4.5 or a 5 VI
(VO=9.0 or 10 VI
(VO=13.5 or 1.5 VI

"0" Level

VOL

"1" Level

VOH

"0" Level

VIL

"1" Level

Vin @ Pin 4= 1.0 V (MCl4447 onlyl
(VOH=2.5 VI
(VOH=4.6 VI
(VOH=9.5 VI
(VOH = 13.5 VI
VIn @Pln4=OV
(VOL =0.4 VI
IVOL =0.5 VI
(VOL=15VI
Input Current-Address, Ramp Start

V

V

VIH

(VO=O 5 or 4.5 VI
(VO= 1.0 or 9.0 VI
(VO= 1.5 or 13.5 VI
Output Drive CUrrent- Comparator

Reference CUrrent Range

-

-

Channel Input Voltage Range

VAl

5
10
15

-

-

Conversion Linearity
C>1OO pF, VAI=O to 2.5 V, V re f=2 5 V
VAI=O to 7 a V, Vre f=7.0 V
VAI=Oto 120V, Vref=12.0V

-

-0 36
-0.9
-2.4

-

0.36
0.9
2.4

-

mA

-

Reference Voltage Range

-

-1.7

10L

-

Comparator Threshold

-

mA

VCr
IR

Buffer Amplifier Output Offset

-

10H

-

Crosstalk Between Any Two Input Channels

-

VBO

VTC

Vref

5
10
15
5
10
15

-

-

-

-

-

-

5
10
15

-

5

-

10
15

-

-

-

-

-

-

-

-

-

-

a

0.195
0.275
0.290

2.0
20
2.0

-

VBO
VBO
VBO
3.0
8.0
13.0

-

-05
-05
-05

-

+05
+05
+05

0
0

-

± 1.0

p,A

-

nA

-

mA

pF

-

-

-

-

-

-

-

mV
p,A
V

V

V

V

% Full

LC

3-26

Scale

MC14443, MC14447

SWITCHING CHARACTERISTICS (Cl = 50 pF, TA = 250CI
VOO
Min
Typ
Max
Unit
V
Output Rise Time-Comparator
240
5.0
120
ns
'TlH
150
10
75
15
65
130
Output Fall Time-Comparator
5.0
250
500
ns
tTHl
10
350
700
15
650
1300
Propagation Delay Time-Comparator
MC14443
5.0
550
1100
ns
tpLH
(RL = 10 k to VOO)
10
1000
500
15
1100
550
5.0
350
700
ns
tpHL
10
300
600
600
15
300
MC14447
5.0
600
1200
ns
tplH
475
10
950
15
600
1000
5.0
450
980
ns
tpHL
10
1080
540
15
750
1500
Multiple>csr Propagation Delay
5.0
180
ns
360
tM
125
10
250
110
15
220
Ramp Start Delay Time
5.0
40
80
ns
'TS
10
25
50
40
15
20
Acquisition Time*
30
60
5.0
uS
tA
C= l000pF
10
15
30
15
14
28
Rre!= 100 kO
..
• Acquisition Time Includes multiplexer propagation delay. ramp start propagation detay and the time reqUired to charge ramp capacitor to
the selected input voltage.
Characteristic

Symbol

(MC14447 only)

PIN DESCRIPTIONS
A2, Al, AO, ANALOG MUXADDRESS INPUTS (PINS 2,
1, 161 - These inputs determine the input voltage source to
be presented to the measurement system according to the
Truth Table shown in Figure 2.

Ref Current, REFERENCE CURRENT (PIN 61 - To
discharge the ramp capacitor, the reference current is fixed
via a resistor (Rref) to a positive supply from Pin 6. Typical
current is equal to (VDD- Vref)/Rref·

Ramp Start, RAMP START (PIN 3) - When Ramp Start
is low, the ramp capacitor is charged to a voltage associated
with the selected input channel. When Ramp Start is
brought high, the connection to the input channel is broken
and the capacitor begins to ramp toward VSS. See Figure 4.

Comp Out, COMPARATOR OUTPUT (PIN 7) - This output is low when the capacitor has reached the discharged
voltage and is high otherwise. The MCl4443 requires a pullup resistor on Pin 7 due to the open-drain configuration. The
MCl4447 does not require a puli-up resistor.

Ramp Cap, RAMP CAPACITOR (PIN 4) - The ramp
capacitor is used to generate a time period when discharged
from a selected voltage via a precise reference current. A
polystyrene or mylar capacitor is recommended. The value
should be l!: 100 pF so that the board and stray capacitances
have negligible effects. Large values of capacitance with the
associated large leakage currents are not recommended
because the leakage current must be inSignificant in comparison to the minimum reference current (10 p.Al.

Ref Voltage, REFERENCE VOLTAGE (PIN 8) - This is the
known voltage to which the unknown is compared.

Vss, NEGATIVE POWER SUPPLY (PIN 5)
system ground.

INPUT CHANNELS (PINS 9, 10, 11, 12, 13, 15) - Input
channels 1 through 6 are used to monitor up to six separate
unknown Voltages. Selection is via the address inputs.
VDD, POSITIVE POWER SUPPLY (PIN 14) - This pin is
the package positive power supply pin.

This is

3-27

..

MC14443, MC14447

FIGURE 1 - VOLTAGE TO PULSE WIDTH CONVERSION
Voltage
(VSO)count'"

Reference Voltage· (VR +

(Vx

Vao l

"" tx

(V R + VaO)count" tA

Slope

'R
=C

Unknown Voltage· (Vx + Vao)

=

= tx - to

(VX)count =

tR --

to

(V Rlccunt
(VX)count

(VR1count

•

to

+ VBolcount

tx - to
tR ~ to

Voltage at 0 V Input"' (Voa)
Camp Ref (VTC)

a ol--.L=-=::±===±~=====~
to
tx

·Voltages measured at pin 4
with ramp start low.

time

FIGURE 2 - TRUTH TABLE
A2

Al

AO

0
0
0
0
1
1
1
1

0
0
1
1

0
1
0
1
0
1
0
1

0
0
1
1

Input Selected
Channe~O

VSS

(ground)

Ch1

Channel 1

Ch2
Ch3

Channel 2

Ch4

Channel 4

Ch5

Channel 5

Channel 3

Ch6

Channel 6

Vret

Channel 7 (External Reference)

FIGURE 3 - TYPICAL APPLICATIONS ~IRCUIT

Voo
Address Lines ~
from the

Microprocessor

Ramp start

,----.

from the
Microprocesso r

!
II:

Ramp Capacitor

16

2

15

3

M" 14
~~
~~
13
~

~t----"-4
~

R1

1

5
6
7

Comparator
Output to
Microprocesso r

.
uti

:;:;

8

I
I

Channel 2

12

Channel 3

11

Channel 4

10

Channel 5

9

Channel 6

R2

FIGURE 4 - SOFTWARE FLOW
(CONVERSION SEQUENCE)
Step No.

A2
1

1.

2.

1
0
0
0
0

3.
4.
5.
6.

7.
8.

I
I

0
0

Al
1

AO
1

Ramp Start

Comment

0
Channel 7 Selected (Reference Voltage)
1
1
Record time until Pin 7 goes low
1
0
0
Channel 0 Selected (Ground)
0
1
0
0
Record time until Pin 7 goes low
1
Channel 1 Selected
0
0
1
1
Record time until Pin 7 goes low
·0
Calculate tCh7.- tChO: tChi Step 2-Step 4
Calculate tCh1 - tChO : tCh1' Step 6-Step 4
Calculate Vunknown - VCh7ItCh1'/tchi)'
1
0
Channel 2 Selected
0
1
0
1
Record time until Pin 7 goes low
Calculate tCh2 - tChO - tChi
Calculate Vunknown : VCh7 ItChiltCh7')t

etc.

'Welghtlng of the analog signal on Channell.
tWeighting of the analog signal on Channel 2.

3-28

Channel 1

}".'"-"
Analog
\Voltage
Inputs

®

MC14444

MOTOROLA

CMOS LSI
ANALOG-TO-DIGITAL CONVERTER (ADC)

(LOW-POWER SILICON GATE
COMPLEMENTARY MOS)

The MCI4444 ADC IS a 4O-pin bus-compatible 8-bit AID converter
with additional digital 1/0 capability. The device operates from a single
5 V supply and provides direct interface to the MPU data bus used with
all Motorola M6800 family parts. It performs an 8-bit conversion in 32
machine cycles at 1 MHz and allows for up to 15 analog inputs. In addition, the part has a 3-bit digital 1/0 port and can accept up to 9 digital
inputs. Six of these Inputs are deSigned to be either analog or digital
inputs. All necessary logiC for software configuration, channel selection, conversion control, bus interface and maskable interrupt capability
is included.

MICROPROCESSOR-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTER

•
•

~
...... '

40

. ,'.'

PLASTIC PACKAGE
CASE 711

1

Direct Interface to M6800 Family MPUs
Dynamic Successive Approximation AID

~"

• 32 "s Conversion at fE = 1.0 MHz
• Ratiometric Conversion
• Completely Programmable
• Polled or Interrupt Driven Operation
• 3 Dedicated Digital Inputs
• 3-Bit Digital 110 Port
• 9 Dedicated Analog Inputs
• 6 Inputs Usable for Either Analog or Digital Signals
• Completely TTL Compatible Inputs at Full Speed
Voltage of 5 V ± 10%

,'

•'

n

40 1

Suffix Denoles
Ceramic Package
Plastic Package

Vref

ANI

15

15

~-t~....,~ANO,

2-15

PO-5
4

SC
Analog

Data
Register
IReadOnIV)

4

AO-3
OOIR

3

0lCJO.2

CS

L SUFFIX

CERAMIC PACKAGE
CASE 734

iaWNG INFORMATION

MO

8

8

R/W

PSUFFIX

8

RSI

REm'

3-29

Digital
Data
Regtster
IRead Only)

0lCJO.2
013-5

•

MC14444

MAXIMUM RATINGS*

Parameter

Symbol
VOO

DC Supply Voltage IReferenced to VSSI

Yin

DC Input Voltage IReferenced to VSSI

Vout

lin

•

DC Output Voltage IReferenced to VSSI

Value

Unit

-0.5 to +6.5

V

-0.5 to VCC+0.5

V

0.5 to Vec + 0.5

V

DC Input Current, per Pin

±1O

mA
mA

lout

DC Output Current, per Pin

±10

100

DC Supply Current, VOO and VSS PinS

±20

mA

Po

Power Dissipation, per Package T

500

mW

Tstg

lL

Storage Temperature

65 to + 150
;;uu

Lead Temperature 110-Second Solderingl

'c
"t;

* Maxlmu,m

Ratings are those values beyond which damage to .the deVice may occur.
tPower Dissipation Temperature Derating:
Plastic "P" Package: -12mW/'C from 65'C to 85'C
Ceramic "L" Package: no derating

This device contains circuitry to protect the
Inputs against damage due to high statiC
voltages or electric fields; however. it is advised that normal precautions be taken to
avoid applications of any voltage higher than
maximum rated voltages to this high impedance circuit. For proper operation it is
recommended that V in and Vout be constrained to the range VSS:S IV in or
VoutlsVOO·
Unused Inputs must always be tied to an
appropriate logiC voltage level le.g., either
VSS or VOOI.

DC ELECTRICAL CHARACTERISTICS IVoo=5.0 V ± 10%, VSS=O V, TA = _40' to 85'C unless othelWlse notedl

I

ISymbol I

Characteristic

Conditions

I

Min

I Max

Unit

Bus Control Inputs IR/W, Enable, Reset, RS1, CSI
Input High Voltage.
VIn-O to 5.5 V
ILoad-1 6 mA
VOH- VOO-5.5V
Input High Voltage
Input Low Voltage

VIH
V IL

Three-State lOft Statel Input Leakage Current

ITSI

VOO=5.5 V,
VSS:sVIn",VOO

2.0

-

V

-

0.8

V

±10

p.A

Panpharal 1/010100-0102 013-015, PO-P5)
Input High Voltage

VIH

2.0

-

V

Input Low Voltage

VIL

-

0.8

V

±1.0

p.A

Input Leakage Current

013-015, PO-P5

Output High Voltage

0100-0102

VOH

VOO-5.5 V,
VSS:sVlnsVOO
10H- -0.19 mA

Output Low Voltage

0100-0102

VOL

10L - 0.975 mA

Three-State 10ff Statellnput Leakage Current

0100-0102

ITSI

VOO-5.5 V,
VSS:sVout:SVOO

lin

VOO-O.4

-

V

-

0.4

V

±10

p.A

Currant ReqUirements
Supply Current
Converter Input Current

Reference Input Current

Vref

100

VOO=5.5V, fE=l MHz

-

10

mA

IAOC

Analog input current at
fE = 1 MHz with multiplexer
inputs between VSS and VOO

-

±5OO

nA

Iref

Vref-4.5 to 5.5 V

800

p.A

3-30

I

MC14444

ANALOG CHARACTERISTICS iTA = -40"C to 85"C)

Characteristic

Description

Analog Multiplexer
On Resistance

Resistance between each analog Input and multiplexer output

-

5

kO

Leakage Current

Leakage current between all deselected analog Inputs and any selected
analog Input With all analog Input voltages between VSS and VOO

-

±400

nA

I

I

AID Converter IVSS=O V, VAG=O V, 4.5 V"Vref"VDDI
ResolutIon

Number of bits resolved by the AI D

8

-

Bits

Nonlinearity

Maximum deViation from the best straight line through the AID transfer
characteristic

-

±:.I

LSB

Zero Error

Difference between the output of an Ideal and an actual AID for zero
Input voltage

-

±Y2

LSB

Full-Scale Error

Difference between the output of an Ideal and an actual AID for full-scale
Input voltage

-

±1h

LSB

Total Unadjusted Error

MaXimum sum of NonJlneanty. Zero Error, and Full-Scale Error

-

±:.I

LSB

Quantization Error

Uncertainty due to converter resolution

-

±:.I

LSB

Absolute Accuracy

Difference between the actual Input voltage and the full-scale weighted
equivalent of the binary output code, aU error sources Included

-

± 1.0

LSB

Conversion Time

Total time to perform a single analog-to-dlgltal conversion

-

32

E cycles

Sample AcqUISition Time

Time required to sample the analog Input

-

12

E cycles

AC CHARACTERISTICS ITA= _40" to 85"CI (See Figure 11

Characteristic

Signal

Symbol

Min

Max

Unit

Enable Clock Cycle Time 11/fEI

E

teyeE

943

-

ns

Enable Clock Pulse Width, High

E

PWEH

440

Enable Clock Pulse Width, Low

E

PWEL

410

-

ns

Clock Rise Time

E

tEr

25

ns

Clock Fall Time
Address Setup Time

ns

E

tEf

-

30

ns

RS1, R/W, CS

tAS

145

-

ns

Data Delay I READI

DO-D7

tDDR

-

335

ns

Data Setup IWRITEI

DO-D7

tDSW

185

-

ns

ns
pF

Address Hold Time

RS1, R/W, CS

tAH

10

Input Data Hold Time

DO-D7

tDHW

10

Output Data Hold Time

00-07

tDHR
Cm

10
-

55

Input Capacitance

ANO-AN15
D10-D15,
R/W, E, RS1,
CS, RESET

Three-State Output Capacitance
High-Impedance Output Capacitance

3-31

ns
ns

15

D100-D102
DO-D7

Cout

-

15

pF

IRQ

Cout

-

15

pF

•

MC14444

3-32

MC14444
MCl4444 MPU INTERFACE SIGNALS

PIN FUNCTIONS
Pin No.
Pin Name
1

Function

VAG

AID Converter Analog Ground

2

VSS

DIgItal Ground

3

0100

DIgital Port

TVpe

Supply
Supply
Input/Output

4

0101

Digital Port

Input/Output

5

0102

Digital Port

Input/Output

6

013

DIgItal Port

Input
Input

7

014

DIgItal Port

8

015

DIgItal Port

9

07

Data Bus B,t 7 IMSBI

Input/Output

Input

10

06

Data Bus B,t 6

Input/Output

11

05

Data Bus B,t 5

Input/ Output

12

D4

Data Bus B,t 4

Input/Output

13

03

Data Bus B,t 3

Input/Output

14

02

Data Bus B,t 2

Input/Output

15

01

Data Bus B,t 1

Input/ Output

16

DO

Data Bus B,t 0 ILSBI

Input/ Output

17

R/W

18

E

Read/Write

Input

Enable Clock 1<1>21

Input

19

ASI

RegIster Select

Input

20

CS

Ch,p Select

Input

21

Reset

22

Reset

Input

P51AN151

0'91tal Port or Analog Channel 15

Input

23

P41AN141

D'g,tal Port or Analog Channel 14

Input

24

P31AN131

D'g,tal Port or Analog Channel 13

Input

25

P21AN121

D'g,tal Port or Analog Channel 12

Input

26

PHANlll

Digital Port or Analog Channel 11

Input

27

POIAN101

Drgltal Port or Analog Channel 10

Input

28

AN9

Analog Channel 9

Input

29

ANB

Analog Channel B

Input

30

AN7

Analog Channel 7

Input

31

AN6

Analog Channel 6

Input

32

AN5

Analog Channel 5

Input

33

AN4

Analog Channel 4

Input

34

AN3

Analog Channel 3

Input

35

AN2

Analog Channel 2

Input

36

ANO

Analog Channel 0

Input

37

MO

Analog Multiplexer Output

36

TAO

Interrupt Request

39

VDD

Supply Voltage

40

Vref

AID Converter Positive Reference
Voltage

Test Only
Open-Dram

Bidirectional Data Bus (00-07) _. The bidirectional data
lines DO-D7 comprise the bus over which data IS transferred
In parallel to and from the MPU The data bus output drivers
are three-state deVices that remain In the hlgh-Impedence
state except dUring an MPU read of an ADC data register
Enable Clock (E) - The enable clock provides two functions for the MCI4444 First, It serves to synchronIZe data
transfers IOta and out of the ADC The timing of all other external s'gnals IS referenced to the leading or trallIOg edge of
the enable clock. Secondly, the enable clock IS used Internally to derive the necessary SAR A/ D conversion clocks
Because this conversion IS a dynamiC process, enable clock
must be a continUOUS signal Into the ADC dUring an A/ D
converSIon.
Read/Write (R/W)
The R/W signal IS proVided to the
MCI4444 to control the direction of data transfers to and
from the MPU A low state on this line IS required to transfer
data from the MPU to the ADC control register. A high state
IS required on R/W to transfer data out of 91ther of the ADC
data registers.
Reset (RESET) - The reset line supplies the means of
externally forCing the MCI4444 IOta a known state. When a
low IS applied to the RESET pin, the start converSion, Interrupt enable and 110 port data direction bits of the control
register are cleared. Analog channel 0 IS automatically
selected by the analog multiplexer. The AI D status bit IS also
cleared. Any AI D results present In the Analog Data register
are not affected by a reset. Reset forces the data bus and I/O
port output drivers to the high-Impedance state. The Internal
byte pOIOter (discussed 10 the follOWing pages) IS set to POIOt
to the most Significant byte of any subsequently selected 10ternal register. In order to attain an Internally stable reset
state, the RESET Pin must be low for at least one complete
enable clock cycle.
Chip Select (CS) - Chip select IS an active-low input used
by the M PU system to enable the ADC for data transfers No
data may be passed to or from the ADC through the data bus
pins unless CS IS ,n a low state A selection of MPU address
lines and the M6800 VMA Signal or ItS eqUivalent should be
utilized to prOVide chip select to the MCI4444.

MCl4444 ANALOG INPUTS AND DIGITAL I/O
(Refer to the ADC Block Diagram)
Dedicated Analog Channels (ANO, AN2-AN9) - These
Input pins serve as dedicated analog channels subject to AI D
conversions. These channels are fed directly Into the IOternal
16-to-l analog multiplexer which feeds a single analog
voltage to the A/ D converter.

Output
Supply
Input

3-33

Shared Analog Channels (ANIO-AN15) - These IOput
PIOS are also connected to the analog multiplexer and may be
used as analog channels for A/D converSion. However,
these pins may also serve as digital Input pIOS as deSCribed
next.

•

MC14444
Shared Digital Inputs (PO-P51 - PO-P5 comprise a 6-blt
digital input port whose bits may also serve as analog channels. The state of these mputs may be read at any lime from
the ADC digital data register. The function of these pms IS
not programmed, but Instead IS simply assigned by the
system deSigner on a pin-by-pin baSIS.

•

CAUTION: Digital values read from the PO-P5 bit
locations do not guarantee the presence of true digItal input levels on these pins. PO-P5 pass through a
TTL-compatible Input buffer and Into the digital data
register. These buffers are designed with enough
hysteresis to prevent internal oscillations If an analog
voltage between 0.8 and 2 V IS present on one or
more of these six pins.

AI D Ground Reference Voltage (VAGI - This supply IS
the ground reference for the Internal DAC and several
reference voltages supplied to the comparator It should also
be noise-free to guarantee AID accuracy. Absolute accuracy
may be degraded If VAG IS wired to VSS at the ADC
package unless VSS has been suffiCiently filtered to remove
sWitching noise. Ideally VAG should be Single-pOint grounded to the system analog ground supply.
Multiplexer Output (MOl - The analog multiplexer selects
one of 16 analog Input channels and connects It to the Input
of the AID converter. The multiplexer output IS Internally
connected to the AID Input and reqUires no external
jumpers. Since loading of the MO pin affects the charging
time of the DAC, it is recommended that no connection be
made to the MO pin.

Digital 110 Port (DIOO-DI021 - These PinS serve as a 3-bit
digital liD port. At reset the port IS configured as an Input
and may be read from the ADC digital data register. The port
may be programmed as an output by setting the DDIR bit In
the control register to a logical 1 See the control register
discussion for further details. When configured as an output,
the 010 port will provide CMOS logiC levels for limited dc
load currents. (Refer to the Electrical Spec,f,callons for the
dc drive capability of thiS port.) New output states are
transferred to the external pins on the last falling edge of E
during a 16-bit write to the control register When configured
as an Input, the port will accept both TTL and CMOS logiC
levels.
Dedicated Digital Inputs (DI3-DI51 - These three pins are
dedicated as digital Inputs whose values may be read from
the ADC digital data register. They are also TTL and CMOS
compatible.

MC14444 SUPPLY VOLTAGE PINS AND TEST PIN
Positive Supply Voltage (VDDI - VDD IS used Internally
to supply power to all digital logic and to the chopper
stabilized comparator. Because the output buffers connected to this supply must drive capacitive loads, ac noise on
thiS supply line is unavoidable Internally. Analog CIrCUItS using this supply within the MCl4444 were deSigned With high
VDD supply relection; however, it is recommended that a
flltenng capacitance be used externally between VDD and
V S S to filter noise caused by transient current spikes.
Ground Supply. Voltage (VSSI - VSS should be tied to
system digital ground or the negative terminal of the VDD
power source. Again. the output buffers cause Internal noise
on this supply. so analog CirCUitS were deSigned with high
VSS relection.
Positive AID Reference Voltage (Vretl - This is the
voltage used internally to provide references to the analog
comparator and the digital-to-analog converter used by the
SAR AID. The analog-ta-digital converSion result Will be
ratiometric to Vref - VAG (full scale!. Hence Vref should
be a very noise-free supply. Ideally Vref should be singlepoint connected to the voltage supply driving the system's
transducers. Vref may be connected to VOD, but degradation of absolute AID accuracy may result due to sWitching
noise on VDD.

3-34

MC14444 INTERNAL REGISTERS
The MCl4444 ADC has three 16-blt Internal registers. Each
register IS diVided Into two 6-blt bytes a most Significant
(MS) byte (bits 8-15) and a least Significant (LS) byte Iblts
0-71. Each of these bytes may not be addressed externally,
but Instead are normally addressed by a Single 16-bIt Instruclion such as the M6800 LOX Instrucllon. An Internal byte
pOinter selects the appropriate register byte dUring the two E
cycles of a normal 16-blt access. In keeping With the M6800
X register format. the pOinter POints first to the M S byte of
any selected register. A Iter the E cycle In which the M S byte
IS accessed. the pOinter Will SWitch to the LS byte and remain
there for as long as chip select IS low. The pOinter moves
back to the M S byte on the falling edge of E after the first
complete E cycle in which the ADC IS not selected. ISee
Figure 2a for more detail.) The MS byte of any register may
also be accessed by a Simple 8-blt Instruction as shown In
Figure 2b. However, the LS byte of all registers may be
accessed only by 16-bit instructions as deSCribed above. By
connecting the ADC register select (RS1) to the MPU
address line A 1, the three registers may be accessed sequen·
tlally by 16-bit operations.
CAUTION: RS1 should not be connected to
address line AO and the addreSSing of the ADC
should be such that RS1 does not change states durIng a 16-blt access.

INTERNAL REGISTER ADDRESSING

Addressing Signals
R/W RSl

ADC Response

RESET

CS

a

x
a
a

X

Reset

a

No Response

1

MPU Write to Control Register

1

x
a
a
a

1

0

MPU Read from Analog Data

1

0

1

1

MPU Read from Digital Data

1

1

X

X

Chip Deselected (No Response)

1
1

Register
Register

MC14444
FIGURE 2 - ADC ACCESS TIMING

a - Typica'

16-B~

ADC Access

•

ES----h

RS1,

Riw

L...JL..lL.X-4:J1

1*----

MS Byte
Accessed

LS Byte

------'J~If----- Accessed

b - Typical B-Bit ADC Access

RS1,

R/W

L...lI..lWI..II.~

Select
MS Byte

Byte POinter
Reset to MS Byte

3-35

MC14444

MCl4444 CONTROL REGISTER
(Write Only)
15

o liE

MSB)

8
I X

SC OOIRII 010 1 010 1010
1_ x 1 x 1 x 1 x 1fLSBI
fMSB) 2
1
0

I A3 I A2 I Al I AO
fLSB)

Least Significant Byte

M<;>st Significant Byte
8-B,t Write
16-Bit Wnte

II

Analog Multiplexer Address IAO-A3) - These four
address bits are decoded by the analog multiplexer and used
to select the appropriate analog channel as shown below.

will begin Immediately after the completion of the control
register write.
Unused Bits IX) - Bits 9-13 of the ADC Control Register
are not used internally.

Hexadecimal Address fA3 = MSB)

Select

o

ANO
VREF
AN2-AN9
AN10-AN15fPO-P5)

1

2-9
A-F

Interrupt Enable liE) - The Interrupt enable bit, when set
to a logical 1, allows the TFfQ pin to be activated at the completion of the next analog to digital converSion.
Control Register MSB - The MSB of the most significant
byte of the ADC control register must be written as a logical

Digital 110 Output 10100-0102) - When the MPU configures the 3-bit 110 port as an output, these are the bit locations into which the output states are written.

o.

110 Port Data Direction IDOIR) - This IS the data direction bit for the 3-blt 1/0 port.·A logical 1 configures the port
as output while a logical 0 configures the port as input.

NOTE: A 16-bit control register write IS required to change
the analog multiplexer address or to update the DIO port.
However, 8-bit writes to the MCl4444 can be used to Initiate
an AI D converSion if the analog MUX is already selecllng the
desired channel. ThiS IS useful when repeated conversions
on a particular analog channel are necessary.

Start AID Conversion ISC) - When the SC bit IS set to a
logical 1, an AI D conversion on the specified analog channel

MCl4444 ANALOG DATA REGISTER
(Read Only)
15

o

EOC
fMSB)

RO
ILSBI

~-------------------------------16-BltRead------------------------------~

AID Result IRO-R7) - The LS byte of the analog data
register contains the result of the AID conversion. R7 IS the
MSB, and the converter follows the standard convention of
assigning a code of $FF to a full-scale analog voltage. There
are no special overflow or underflow Indications.
AID Status IEOC) - The AID status bit is set whenever a

conversion IS successfully completed by the ADC The status
bit is cleared by either an 8-blt or a 16-blt MPU write to the
ADC control register. The remainder of the bits In the MS
byte of the analog data register are always set to a logical 0
to simplify MPU Interrogation of the ADC status. For example, a single 8-bIt M6800 TST instruction can be used to
determine the status of the AI D converSion.

3-36

MC14444

MC14444 DIGITAL DATA REGISTER
(Read Only)
15

o

P5

010

o

~---------------16-BII

Read----------------J"'i

Digital I/O Port (0100-0102) - The states of the three
digital 1/0 pinS are read from these bits regardless of
whether the port IS configured as Input or output.

Shared Digital Port (PG-PS) ~ The voltage present on
these pins is Interpreted as a digital signal and the corresponding states are read from these bits.

Dedicated Digital Input (013-015) - The states of the
three dedicated digital Inputs are read from these bits.

WARNING: A digital value will be given for each pin even
if some or all of the pins are being used as analog inputs.

Analog Multiplexer Address (AO-AJ) - The number of the
analog channel presently addressed IS given by these bits.

ANALOG SUBSYSTEM
ISee Block Diagram)
General Description

2 enable clock cycles for the write into the control register
even if only 8 bits are written. In this case, the second E cycle
does not affect any internal registers. During the next 12 Y..
enable· cycles following a write command, the analog
multiplexer channel is selected and the analog input voltage
is stored on the sample and hold DAC. It is recommended
that an input source impedance of 10 KO or less be used to
allow complete charging of the capacitive DAC.
During cycle 13 the AID is disconnected from the
multiplexer output and the successive approximation AI 0
routine begins. Since the analog input voltage is being held
on an internal capacitor for the entire conversion period, it is
required that the enable clock run continuously until the AID
conversion is completed. The new 8-bit result is latched into
the analog data register on the rising edge of cycle 32. At this
point the end of conversion bit IEOC) is set in the analog
data register MS byte, and the interrupt request (lRO) pin
goes low if interrupt has been enabled by the IE bit of the
control register. ISee Figure 3, AID Timing Sequence.)

The analog subsystem of the MCl4444 IS composed of a
16-channel analog multiplexer, an 8-bIt capacitive DAC
(dlgital-to-analog converter), a chopper-stabilized comparator, a successive approximation register, and the
necessary control logic to generate a successive approximation routine.

The analog multiplexer selects one of sixteen channels and
directs it to the input of the capacitive DAC. A fullycapacitive DAC is utilized beca.use of the excellent matching
characteristics of thin-oxide capacitors in the silicon-gate
CMOS process. The DAC actually serves several functions.
During the sample phase, the analog input voltage is applied
to the DAC which acts as a sample-and-hold circuit. During
the conversion phase, the capacitor array serves as a digitalto'analog converter. The comparator is the heart of the
AOC; it compares the unknown analog input to the output of
the DAC, which is driven by a conventional successiveapproximation register. The chopper-stabilized comparator
was designed for low offset voltage characteristics as well as
VDD and VSS power supply rejection.

NOTE: The digital data register or the analog data register
may be read even if an AI D conversion is in progress. If the
analog data register is read dUring an AID conversion, valid
results from the previous conversion are obtained. However,
the EOC bit will be clear (logical 0) if an AI D conversion IS In
progress.

Device Operation
An AID conversion is initiated by writing a logical 1 into
the SC bit of the ADC control register. The MC14444 allows

3·37

•

MC14444
FIGURE 3 - TYPICAL AID TIMING SEQUENCE
MPU Wnte
ToADC
Control
Register
Sample Analog Input
~lInput Should Be Stablel

M

__ I.

1 2 3 4 5 6 7 6 9 1 0 11 12 13

••

SARA/DCpnverSlon

--I

1.4 15 16 17 18 19 20 21 22 23 74 25 26 27 28 29 30 31 32

R/W

RSI
Analog Data
Register (RO-R7 ____
and EOCI

+ ________v;,;a;;,;li,;;d..:D..:a.;;ta;,;F.,;r,;;om;;;.,;P.,;re,;;v:..;lo;;,;u:;,;s;,;C;;,;o:..;n:..;v,;;er;.;;s;.;lo;;,;n.,;(,;;EO,;;C..:..::C;;,;le;;:a;;,;r!~_ _ _ _ _ _ _ _ _ _.....,~

TAO
III Enabledl

FIGURE 4 - TYPICAL MC14444 APPLICATION IN A CLIMATE CONTROLLER

ROM

MCII802
MPU

Duct
Damper

Mce821

PIA

Controt

3-38

®

MC14447

MOTOROLA

FOR COMPLETE DATA
SEE MCl4443

CMOS MS.

ANALOG-TO-DIGITAL CONVERTER
LINEAR SUBSYSTEM

ILOW.pOWER COMPLEMENTARY MOS)

The MCl4443 and the MCl4447 are 6-channel. single-slope, 8-10 bit
analog-to-digltal converter linear subsystems for microprocessor-based
data and control systems. Contained In both devices are a one-of-8
decoder, an 8-channel analog multiplexer, a buffer amplifier, a precision
voltage-to-current converter, a ramp start circuit, and a comparator.
The output driver of the MCl4443's comparator IS an open-drain
N-channel which provides a sinking current. The output driver of the
MCl4447's comparator IS a standard B-Series P-Channel, N-Channel
pair.
A CMOS MPU or MCU provides tre addressing, timing, counling, and arithmetic operations required for Implementing a full
analog-to-dlgital converter system. A system made up of a processor and the linear subsystem has features such as
automatic zeroing and variable scaling (weighting) of six
separate analog channels.
•
•
•
•
•
•
•
•

Quiescent Current 0.8 mA TYPical at VDD = 5 V
Single Supply Operation + 4.5 to + 18 Volts
Direct Interface to CMOS MPUs
Typical Resolution - 8 Bits
Typical Conversion Cycle as Fast as 300 p,s
Ratio Metric Conversion Minimizes Error
Analog Input Voltage Range: VSS to VDD - 2 V
Chip Complexity: MCl4443 - 150 FETs
MCl4447 - 151 FETs

MICROPROCESSOR-BASED
ANALOG-TO-DIGITAL
CONVERTER

L SUFFIX

P SUFFIX

CERAMIC PACKAGE

PLASTIC PACKAGE
CASE 648

CASE 620

ORDERING INFORMATION
MC14XXX

T

Suffix

t=::

L
P

Denotes

Ceramic Package
Plastic Package

BLOCK DIAGRAM
PIN ASSIGNMENT

-=

15

Ch1
Ch2
Ch3
Ch4
Ch5
Ch6

Ramp Start
3

13

16

12

~

11

0.
.;:

10

~

2

~

A1

14

4

13

6

11

12

9

r------~f---+-"-6 ::: Current

Ref
Voltage

AO

15

3

Voo

= Pin

14

VSS=Pin5

A2

3·39

10

8

•

®

MC14549B
MC14559B

MOTOROLA

CMOS MS.
!LOW·POWER COMPLEMENTARY MOSI

SUCCESSIVE APPROXIMATION REGISTERS

SUCCESSIVE APPROXIMATION
REGISTERS

The MC14549.B and MC14559B successive approximation registers
are 8-bit registers providing all the digital control and storage necessary
for successive approximation analog-to-dlgital conversion systems.
These parts differ in only one control input. The Master Reset IMR) on
the M.C14549B is required in the cascaded mode when more than B bits
are desired. The Feed Forward IFF) of the MC14559B IS used for register
shortening where End-of-Conversion I EOC) is required after less than
eight cycles.
Applications for the MC14549B and MC14559B include analog-todigital conversion, with serial and .parallel outputs.

•

• Totally Synchronous Operation
• All Outputs Buffered
• Single Supply Operation

L SUFFIX

P SUFFIX

CERAMIC PACKAGE

PLASTIC PACKAGE

CASE 620

CASE 648

ORDERING INFORMATION

.,,"'" l~SUffOX

• Serial Output
• Retriggerable
• Compatible with a Variety of Digital and Analog Systems such as the
MC1408 8-Bit Df A Converter
• All Control Inputs Positive-Edge Triggered
• Supply Voltage Range= 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low-Power TTL Loads, One Low-Power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range
• Chip Complexity: 488 FETs or 122 Equivalent Gates

Denote.

L
P

Ceramic Package
PlastiC Package

A

Extended Operating
Temperature Range
Limited Operating
Temperature Range

C

PIN ASSIGNMENT

041~

DC Supply Voltage
Input Voltage, All Inputs
DC Input Current, per Pin
Operating Temperature Range-AL Device
CL/CP Device

lin
TA

mAdc

-65 to + 150

°C
°C

Action

X

X

X

X

"-

None

X

X

1

X

-'

Reset

1

0

0

0

Start
Conversion

1

X

0

1

1

0

0

-'
-'
...r

X

0

X

...r-

,

SC SClt_11 EOC Clock
X

X

X

0

0

"-

06

3

14 02

Q7

4

13

...r-

Continue
Conversion

X

Contmue
Previous
Operation

X

...r

0

Start

0

Conversion

Q1

12 00

D 6

11

EOC

C 7

10

*

VSS

8

9 SC

Action
Start
Conversion

...r
...r
...r

X

Sout 5

None

Continue
Conversion
Continue
Conversion
Retain
Conversion
Result

Start
ConverSion

x = Don't Care
= State at

15 Q3

• For MC145498 Pin 10 IS MR Input
For MC145598 Pin 10 IS FF Input

MC14559B

SC SClt_11 MR MRIHI Clock

t-1

Vdc

TRUTH TABLES'

MC14549B

0

Unit
Vdc

0.5 to VDD + 0.5
±10
-55 to + 125
-40 to +85

Tstg

Storage Temperature Range

1

Value
-05to +18

VDD
Vin

VDD

2

05

MAXIMUM RATINGS IVoltages referenced to VSSI
Symbol
Rating

This device contalOs Circuitry to protect
the ,Inputs against damage due to high static
voltages or electrtc fields; however, It is
adVised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to thiS high
impedance cirCUIt. For proper operation It
IS recommended that Vin and V out be
constrained to the range VSS ~ (Vin or
Vout ) ~VDD·
Unused inputs must always be tied to an
approprtate logiC voltage level (e.g., either

VSSor VDD).

Previous ~Iock ~

3-40

MC145498, MC145598
ELECTRICAL CHARACTERISTICS (Voltages referenced to VSSI
Symbol

Characteristic
"0" Level

Output Voltage
VIn~ VDD or 0

"1" Level
VIn~O

VOL

VOH

or VDD
"0" Level

Input Voltage#
(VO~9

0 or 1.0 VI
13 5 or 1.5 VI
"1" Level

(VO~

or 45 VI
1.0 or 9.0 VI
1 5 or 13.5 VI

Output Drive Current tAL Device)

Source

5VI
VI
(VOH~9.5 VI
(VOH~13 5 VI
(VOH~4.6

(VOL ~0.4 VI
(VOL ~O 5VI

Sink
Q Outputs

IOL

(VOL~15VI

(VOL ~O 4 VI
(VOL ~O 5VI

Sink
Pin 5, 11 only

(VOL~15VI

Output Dnve Current (CLlCP Devlcel

Source

VI

(VOH~95VI

13 5 VI

(VOL ~O 4 VI
(VOL ~0.5VI
(VOL ~ 1.5 VI

Sink
Q Outputs

(VOL ~O 4 VI
(VOL ~O 5VI

Sink
Pin 5, 11 only

IOL

(VOL~15VI

Thigh*
Min Max

5.0
10
15

-

005
005
005

-

0
0
0

0.05
0.05
005

-

5.0
10
15

495
9.95
14.95

-

50
10
15

-

-

4.95
995
1495

5.0
10
15

-

1.5
30
40

-

2.25
450
675

1.5
3.0
4.0

-

5.0
10
15

3.5
7.0
11.0

-

3.5
7.0
11.0

2.75
5.50
8.25

-

35
70
110

-

5.0
50
10
15

-1.2
-025
-0.62
-18

-

-1.7
-036
-0.9
-3.5

-

-07
-0.14
-0.35
-11

-

50
10
15

1.28
32
8.4

-

-1.0
-0.2
-05
-15
1.02
26
6.8

176
4.5
176

50
10
15

0.64
1.6
42

-

0.51
1.3
3.4

088
225
8.8

5.0
5.0
10
15

-1.0
-0.2
-0.5
-1.4

-

-0.8
-0.16
-0.4
-1.2

-17
-0.36
-09
-3.5

5.0
10
15

104
26
7.2

-

0.88
2.2
6.0

1.76
4.5
176

50
10
15

0.52
1.3
36

-

0.44
11
3.0

0.88
225
8.8

-

±0.1

-

±O 00001

±0.1

±0.00001

±03

50

75

-

0.005
0.010
0.015

5.0
10
20

-

0.005
0010
0.015

20
40

-

V

495
995
1495

-

V

-

15
30
4.0

-

-

V

-

mA

-

0.72
18
4.8
0.36
0.9
24

-

15

Input Current (CLlCP Devlcel

lin

15

Input Capacitance

Cin

-

QUiescent Current (AL DeVice)
(Per Packagel
(Clock~O V,
Other Inputs~VDD orO V, 10ut~OpAI

IDD

50
10
15

QUiescent Current (CLlCP Devlcel
(Per Packagel
(Clock~O V,
Other Inputs~ VDD or 0 V, lout~ 0 pAl

IDD

IT

(DynamiC plus QUiescent,
Per Packagel
(CL = 50 pF on all outputs, all
buffers sWitching)

50
10
15

-

-

-

±03

50
10
20
20
40
80

50
10
15

< Tlow= - 55'C for AL DeVice, -40'C for CLlCP DeVice
Thigh= + 125'C for AL DeVice, +85'C for CLlCP DeVice

# NOise Immunity specified for worst-case Input combination
level~

mA

mA

lin

Total Supply Current< < t

Unit

0.05
005
005

V

Input Current (AL Devlcel

NOise Margin for both "1" and "0"

Max

IOH

(VOH~2.5VI

(VOH~

Typ

IOH

(VOH~2

(VOH~4.6

25°C
Min

VIH

(VO~0.5
(VO~

Tlow*
Min Max

VIL

(Vo~450r05VI
(VO~

Voo
Vdc

1.0 V min @ VDD=5 0 V
20 V min @ VDD ~ 10 V
25Vmln@ VDD~15V

t To calculate total supply current at loads other than 50 pF
IT(CLI~IT(50 pFI+2x 1O- 3 (CL-501 VDDf
where IT IS In /LA (per packagel, CL In pF, VDD In V, and f In kHz IS Input frequency
* * The formulas given are for the tYPical charactenstlcs only at 25°C

3·41

-

-

-

80

IT= 10 8 /LA/kHzl f+ IDD
IT=(1.6/LA/kHzl f+IDD
IT~ (2 4 pA/kHzl f+ IDD

-06
-0.12
-03
-10

-

072
18
4.8

-

0.36
09
2.4

-

-

-

± 1.0

pA

± 1.0

/LA
pF

-

-

150
300

-

600

-

-

mA

-

150
300

/LA

/LA

600
pA

II

MC14549B, MC14559B
SWITCHING CHARACTERISTICS·
~Iltlc

•

(CL· 60 pF. TA • 2&oCI
Symbol

OutpUt RI.. Tlmo
trLH • (3.0 n./pFI CL + 30 no
trLH· (1.Ii no/pFI CL + 16 no
tTLH· (1.1 ni/pFI CL + 10 nl
Output Fall Timo
tTHL - (1.6 nl/pFI CL + 26 no
trH L • (0.7S n./pF I CL + 12.5 nl
tTHL· (0.56 no/PFI CL +9.6 n.
Propagation Delay rimo
Clock toQ
tPLH. tPHL· (1.7 ns/pFI CL + 415 n.
tPLH. tpHL· (0.66 ni/pFI CL + 177 nl
tPLH. tPHL • (0.5 ni/pFI CL + 130 nl
Clock to Sout
tPLH. tPHL· (1.7 ni/pFI CL + 865 n,
tpLH. tPHL - (0.&6 ns/pFI CL + 277 nl
tPLH. tPHL • (0.5 ni/pFI CL + 195 ns
Clock to EOC
tPLH. tPHL· (1.7 ns/pFI CL + 215 ns
tPLH. tpHL - (0.86 nil pFI CL + 97 n.
tPLH tpHL· (0.5 ni/pFI CL + 76 ns
SC. D. FF or MR Setup Time

Clock Pul.. Width

6.0
10
16
trHL
6.0
10
15'

tau
'WH(cll

'WH

Clock RI.. end Fall Tlmo

trLH.
tTHL
fel

* The formulae given are for the tYPical characteristics only.

3·42

Min

Typ

MIx

-

180

-

66

360
180
130

-

100
60
40

Unit

nl

90

no
200

100
80
nl

tpLH.
tPHL

Pullo Width - D. SC. FF or MR

Clock Pul.. Frequency

VDD

trLH

-

600
210
156

1000
420
310

--

-

760
310
220

1600
620
440

-

300
130
100
125
60

600

6.0
10
15

-

6.0
10
16
6.0
10
15,
6.0
10
15
6.0
10
16
6.0
10
16
5.0
10
15
6.0
10
16

-

260
100
60
700
270
200
500
200
160

-

2&0
"ZOO

-

no

-

n.

-

40
360
136
100
260
100
80

-

1.6
3.0
4.0

15
5.0
4.0
0.8
1.5
2.0

-

ns

,..
MHz

MC14549B, MC14559B
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS
Voo

Q7
Q6

C
Programmable
Pul.
Generetor

OIl

04

SC

03
Q2

FFCMR)

Ql
QO

0

EOC
Sout

Vss

-=

C

SC _ _ _ _-J·

0------+--.....;.1

Q7----------~~fl

Sout _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Note: Pin 10 = vss

TIMING DIAGRAM

Q7
06==L...-.J

04

-=-~"'-

__________________'

03~~L-

______________

~

Q2 " " " " " " " ' ' - - - - - - - - - - - - - - - - - - - - - - - '

Ql
QO

EOC

=="'_______________-'
_______________
~="'_

~~"'-

~

__________________

~

Sout

~

- Don't care condition

Inh -lndiClltelSarial Outilinhibi_d low •
• - QS is ninth-bit of serial information avail.ble from S·bit register.

Note: Pin 10"" VSS

3-43

4-~~1

MC14549B, MC14559B
OPE~ATlNG

•

Both the MCI4549B and MC14559B can be operated
in either the "free run" or "strobed operation" mode for
conversion schemes with any number of bits. Reliable
cascading andlor recirculating operation can be achieved
if the End of Convert (EOCI output is used as the controlling function, since with EOC = 0, (and with SC = 1
for MC145498 but either 1 or 0 for MC14559BI no stabl,e
state exists under continual clocked operation_ The
MC14559B will automatically recirculate after EOC = 1
during externally strobed operation, provided SC = 1. .
All data and control inputs for these devices are triggered into the circuit on the positive edge of the clock
pulse.
'
Operation of the various term inals is as follows:
C = Clock - A positive-going transition of the Clock is
required for data on any input to be strobed into the
circuit.
SC = Start Convert - A conversion sequence is initiated on the positive-going transition of the SC input on
succeeding clock cycles.
o = Data hi - Data on this input (usually from a comparator in AID applicationsl is also entered into the circuit" on a positive-going transition of the clock. This input
is Schmitt triggered, and synchronized to allow fast response and guaranteed quality of serial and parallel data.
MR = Master Reset (MCl4549B onlyl - Resets all output to 0 on positive-going transitions of the clock. If removed while SC = 0, the circuit will remain reset until
SC = 1. This allows easy cascading of circuits.
FF = Feed Forward (MCl4559B only I - Provides register shortening by removing unwanted bits from. a system.
For operation with less than 8 bits, tie the output
following the least significant bit of the circuit to EOC.

CHARACTERISTICS
E.g., for a 6·bit conversion, tie a1 to FF; the part will
respond as shown in the timing diagram less two bit times.
Not that a1 and ao will still operate and must be disregarded.
For 8-bit operation, FF is tied to VSS.
For applications with more than 8 but less than 16
bits, use the basic connections shown in Figure 1. The F F
input of the MC 14559B is used to shorten the setup.
Tying F F directly to the least" significant bit used in the
'MC14559B 'allows EOC to provide the cascading signal,
and resu Its in smooth traosition of serial information from
the MC14559B to the MC14549B. The Serial Out (Soud
inhibit structure of the MC 14559B remains inactive one
cycle after EOC goes high, while Sout of the MC 14549B
remains inhibited until the second clock cycle of its
operation.
an = Data Outputs - After a conversion is initiated the
a's on succeeding' cycles go high and are then conditionally reset dependent upon the state of the 0 input. Once
conditionally reset they remain in the proper state until
the circu it is either reset or reinitiated.
EOC = End of Convert - This output goes high on the
negative,going transition of the clock following FF = 1
(for the MC14559BI or the conditional reset of ao. This
allows settling of the digital circuitry prior to the End of
Conversion indication. Therefore either level or edge
triggering can indicate complete conversion.
Sout = Serial Out - Transmits conversion in serial
fashion. Serial data occurs during the clock period when
the corresponding parallel data bit is conditionally reset.
Serial Out is inhibited on the initial period of a cycle,
when the circuit is reset, and on the second cycle after
EOC goes high. This provides efficient operation when
cascaded.

FIGURE 1 -12-BIT CONVERSION SCHEME
From AID
Comper.tor

s.ri.JOut

(Continua'
upda. every
13 cloc:k cycl••)

To 01 A and LSB
P.... _I Da.

To D/A and P.e'''' Date
·F F altow. lOC to ac:tivate
as if In ............ I. .r.

ue.lCedlng using eoc guaf'llnteed;
no lteble unfunctioMI .ute.

i

Free run mode

E xternel strobe

3-44

tCompletion of conv...ion
automMlcelly re·;"it •••
"CYCle in free run mode.

MC14549B, MC14559B
TYPICAL APPLICATIONS

Externally Controlled 6-Bit ADC (Figure 2)
Several features are shown in this application:
• Shortening of the register to six bits by feeding the
seventh output bit into the FF input.
•

Continuously Cycling 12·Bit ADC (Figure 4)
Because each successive approxiamtion register (SAR)
has a capability of handling only an eight· bit word, two
must be cascaded to make an ADC with more than
eight bits.
When it is necessary to cascade two SAWs, the second
SAR must have a stable resettable state to remain in while
awaiting a subsequent start signal. However, the first stage
must not have a stable resettable state while recycling,
because during switch·on or due to outside influences, the
first stage has entered a reset state, the entire ADC will
remain in a stable non·functional condition.
This 12·bit ADC is continuously recycling. The serial
as well as the parallel outputs are updated every thirteenth
clock pulse. The EOC pulse indicates the completion of

Continuous conversion, if a continuous signal is

appl ied to SC.
Externally controlled updating (the start pulse must
be shorter than the conversion cycle).
• The EOC output indicating that the parallel data
are valid and that the serial output is complete.
•

Continuously Cycling 8·Bit ADC (Figure 3)
This ADC is running continuously because the EOC
signal is fed back to the SC input, immediately initiating
a new cycle on the next clock pulse.

FIGURE 2 - EXTERNALLY CONTROLLED 6·BIT ADC

c
sc
MC14559B

FIGURE 3 -CONTINUOUSLY CYCLING 8·BIT ADC

c
sc

MC14559B

3·45

•

MC14549B, MC14559B
FIGURE 4 - CONTINUOUSL Y CYCLING 12·BIT ADC

•

EOC'

the 12·bit conversion cycle, the end of the serial output
word, and the validity of the parallel data output.

Externally Controlled 12·Bit ADC (Figure 5)
In this circuit the external pulse starts the first SAR
and simultaneously resets the cascaded second SAR. When
Q4 of the first SAR goes high, the second SAR starts
conversion, and the first one stops conversion. EOC indio
cates that the parallel data are valid and that the serial
output is complete. Updating the output data is started
with every external control pulse.

Additional Motorola Parts for Successive
Approximation ADC
Monolithic digital·to·analog converters - The MC1408/
1508 converter has eight·bit resolution and is available
with 6, 7, and 8·bit accuracy. The amplifier'comparator
block - The MC1407/1507 contains a high speed oper·
ational amplifier and a high speed comparator with ad·
justable window.
With these two linear parts it is possible to construct
SA·ADCs with an accuracy of up to eight bits, using as the
register one MC14549B or one MC145598. An additional
CMOS block will be necessary to generate the clock fre·
quency.
Additional information on successive approximation
ADC is found in Motorola Application Note AN·716.

FIGURE 5 - EXTERNALLY CONTROLLED 12·BIT ADC

3·46

®

MCl44110
MCl44111

MOTOROLA
Advance Information

CMOS LSI
(LOW POWEA COMPLEMENTAAY MOS)

DIGITAL-TO-ANALOG CONVERTERS WITH
SERIAL INTERFACE
The MCl44110 and MCl44111 are low-cost six-bit D/A converters
with serial interface ports to provide communication with CMOS
microprocessors and microcomputers. The MCl44110 contains six
static DI A converters; the MCl44111 contains four converters.
Due to a unique feature of these DACs, the user is permitted easy
scaling of the analog outputs of a system. Over a 5 to 15 volt supply
range, they may be directly interfaced to CMOS MPUs operating at
5 volts.
•
•
•
•

DIGITAL-TO-ANALOG
CONVERTERS WITH
SERIAL INTERFACE

MCl44110
P SUFFIX
PLASTIC PACKAGE
CASE 707

Direct R-2R Network Outputs
Buffered Emitter-Follower Outputs
Serial Data Input
Digital Data Output Facilitates Cascading

MCl44111
P SUFFIX
PLASTIC PACKAGE
CASE 646

• Direct Interface to CMOS I'P
• Wide Operating Voltage Range: 4.5 to 15 Volts
• Wide Operating Temperature Range: 0 to 85°C

PIN ASSIGNMENTS

BLOCK DIAGRAM

MCl44110

Ivool
L

I

A

A1 Out

01 Out

A

A

C

Din

-Ir-~
A

Clock

C 0

On An
Out Out

A

I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I

I

I

I
I

I
I
I

6-Blt Shift Aegister

r

~----~~----------~=-~L~

r;-v-;a

01 Out 2
A10ut 3

16 A6 Out

02 Out 4

15 06 Out

A2 Out 5

14 A5 Out

03 Out 6

13 05 Out

A3 Out 7

12 A4 Out

Enable 8
VSS 9

This document contains information on a new product. Specifications and information herern

3·47

11

04 Out

10 Clock

~

Dout

Din 1

14 VDD

01 Out 2

13 Dout

A10ut 3

12 A4 Out

02 Out 4

11

A2 Out 5

10 A3 Out

Enable 6
VSS 7

* Transparent Latch

are subject to change without notice

VDD

17 Dout

©MOTOROLA INC, 1984

04 Out

9 03 Out
8 Clock

•

MC144110, MC144111

MAXIMUM RATINGS* IVoltages referenced to VSSI
Rating
SymbOl
DC Supply Voltage
Input Voltage, All Inputs

•

DC Input Current, per Pin
Power Dissipation IPer Output)
TA=70'C, MCl44110
MCl44111
TA=85'C, MCl44110
MCl44111
Power Dissipation IPer Packagel
TA=70'C, MCl44110
MCl44111
TA=85'C, MCl44110
MCl44111

.

Storage Temperature Range

VOO
Vin
I

Value

Unit

-0.5 to + 18

V

0.5 to VDD + 0.5
± 10

V
rnA
mW

POH

30
50
10
20
mW

PD
100
150
25
50
-65to +150

This device contains Circuitry to protect
the Inputs against damage due to high
static voltages or electnc fields, however,
It IS advised that normal precautions be
taken to avoid applications of any voltage
higher than maximum rated voltages to
this high Impedance circuit. For proper

operation IS IS recommended that Vin and
Vout be constramed to the range
VSS:sIV,n or Voutl:sVDD
Unused Inputs must always be tied to

an appropriate logic voltage level (e g.,

either VSS or VDol

'C
Tstg
Maximum Ratings are those values beyond which damage to the device may occur.

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSS, TA=O' to85'C unless otherwise Indicated I
SymbOl
Parameter
Test Conditions
Min
VOO
High-Level Input Voltage
I Din' Enable, Clockl

5
10
15

3.0
35
40

VIL

Low-Level Input Voltage
lOin, Enable, Clock I

5
10
15

-

IOH

High-Level Output Current
lOoutl

Vout= VDD-0.5 V

5
10
15

Low·Level Output Current

Vou t=0.5 V

VIH

IOL

lOoutl
IOD
1m

Unit
V

08
0.8
0.8

V

-200

-

",A

5
10
15

200

-

",A

15
15

-

-

QUIescent Supply Current

lout= 0 ",A

Input Leakage Current

Vm=VDD orO V

15

-

See Figure 1

5
10
15

-

Step Size
IRn Out)

See Figure 2

19
39

Offset Voltage from VSS

DIn-$OO, See Figure 1

5
10
15
-

EmItter Leakage Current

VRnOut=OV
IE-O 1 to 10.0 mA
TA=25'C
IE-1.0 rnA

MCl44110
MCl44111

Max

12
8

mA

±1

",A

100
200
300
137
274
411

mV

lOin, Enable, Clock)
Vnonl

Nonlineanty Voltage

IRn Out)
Vstep

Voffset
IE
hFE

DC Current Gam

VBE

Base-to-Emitter Voltage Drop

3-48

15

58
-

mV

1

LSB

10

",A

07

V

40

-

0.4

MC144110, MC144111

SWITCHING CHARACTERISTICS (Voltages Referenced to Vss. TA=O to 85°C. CL = 50 pF. Input t r =tf=20 ns
Unless Otherwise Indicated)

Parameter

Svmbol

VDD
5
10
15

Min

Max

2

th

Hold Time. Clock to Enable (Figures 3 and 4)

5
10
15

5
3.5

2

-

th

Hold Time. Clock to Din (Figures 3 and 41

5
10
15

5
3.5

-

2

-

5
10
15

-

5-15
5
10
15

-

twH

PosItive Pulse Width, Clock (Figures 3 and 4)

1.5
1

twL

Negative Pulse Width. Clock (Figures 3 and 4)

5
10
15

5
3.5

tsu

Setup Time. Enable to Clock (Figures 3 and 41

5
10
15

5
3.5

5
10
15

1000

tsu

Setup Time. Din to Clock (Figures 3 and 4)

tPLH.
tpHL

Propagation Delay. Clock to Dout

tr.tf

Input Rise and Fall Times

tTLH.
tTHL
Cm

Output Transition Time, Dout

Input Capacitance

5·15

FIGURE 1 -

fI)

I

75
Vnonl

I

~

iI<

c

a:

.....

50

Ideal ..

i>

5

~

0

25
Voffset
J

o

/::/

V

V

o

$00

L

//""

ns

~s

2

pos
ns

-

7.5

~

15

31

47

63

$OF

$IF

$2F

$3F

3-49

~s

ns

~/ VT

Program Step

~s

-

~

LINEARITY ERROR !integral lineanty). A measure of how straight a
device's transfer function is, it indicates the worst-case deviation of
linearity of the actual transfer function from the best-fit straight hne.
It is normally specified in parts of an LSB.

~s

pos

/~ ~Actual

.;

0

CIII

750

500

.,/

en
co
co

2

01 A TRANSFER FUNCTION

100

>

2

Unit

pF

•

MC144110, MC144111

FIGURE 2 - DEFINITION OF STEP SIZE

V'

','1 nOli"

Rn Out

,iJi-:;'"

Stepsize=~±O,75~
(For any adjacent pai, of digital numbersl

•

Digital Number

FIGURE 3 - SERIAL INPUT, POSITIVE CLOCK

\00_%_ _
Ft
su

Clock

------------'
'--~-----J'I~-------- ======><~____

D_N______

FIGURE 4 - SERIAL INPUT, NEGATIVE CLOCK

____D_N__J)(~

3·50

________

MC144110, MC144111

PIN DESCRIPTIONS
INPUTS
Din. DATA INPUT - Six-bIt words are entered serially.
MSB first, into digital data input, Din. S'x words are loaded
into the MC144110 dunng each Of A cycle; four words are
loaded into the MC144111.

R1 Out through Rn Out. RESISTOR NETWORK OUTPUTS - These are the R-2R resistor network outputs.
These outputs may be fed to high-impedance input FET op
amps to bypass the on-chip bIpolar transIstors. The R value
of the resistor network ranges from 7 to 15 kll.

Enable. NEGATIVE LOGIC ENABLE - The rniilire pin
must be low (act,vel dunng the senal load. On the low-tohigh transition of Enable, data contained in the shIft register
is loaded into the latch.

01 Out through On Out. NPN TRANSISTOR OUTPUTS
- Buffered DAC outputs utilize an emiter-follower configuration for current-gain, thereby allowmg interface to lowimpedance CirCUItS.

Clock. SHIFT REGISTER CLOCK - Data is shifted Into
the register on the high-to-Iow transition of Clock. Clock is
fed into the D-input of a transparent latch, whIch is used for
inhibitmg the clocking of the shift regIster when Enable is
high.

SUPPLY PINS
VSS. NEGATIVE SUPPLY VOLTAGE usually ground.

This pin IS

Voo. POSITIVE SUPPLY VOLTAGE - The voltage applied to this pin is used to scale the analog output swing from
4.5 to 15 volts, peak-to-peak.

OUTPUTS
oout. DATA OUTPUT - The digital data output is
primarily used for cascading the DACs and may be fed into
Din of the next stage.

3-51

•

MC145040
MC145041

MOTOROLA
' I : ,-,f,

Advance')rl'lormation
8-Bit AID Converters
With Serial Interface

CERAMIC
CASE 732

•

Silicon-Gate CMOS
The MCI45040 and MC145041 are low-cost 8-bit AID Converters with serial interface ports to provide communication with microprocessors and microcomputers,
The converters operate from a single power supply with a maximum nonlinearity of
± y, lSB over the full temperature range. No external trimming is required.
The MCI45040 allows an external clock input (AI D ClKI to operate the dynamic
AID conversion sequence. The MC145041 has an internal clock and an end-ofconversion signal (EOC) is provided.
• Operating Voltage Range: VDD = 4.5 to 5.5 Volts
• Successive Approximation Conversion Time:
MCI45040 - 10 I(S (with 2 MHz AI D ClK)
MC145041 - 20 I(S Maximum (Internal Clock)
11 Analog Input Channels with Internal Sample and Hold
0- to 5-Volt Analog Input Range with Single 5-Volt Supply
Ratiometric Conversion
Separate Vref and VAG Pins for Noise Immunity
Monotonic Over Voltage and Temperature
No External Trimming Required
Direct Interface to Motorola SPI and National MICROWIRE Serial Data Ports
TTL/NMOS-Compatible Inputs May Be Driven with CMOS
Outputs are CMOS, NMOS, or TTL Compatible
Very low Reference Current Requirement
low Power Consumption: 11 mW
Internal Test Mode for Self Test
BLOCK DIAGRAM
ANO
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ANa
11
AN9
12
AN10

PLASTIC
CASE 738

PLASTIC LEADED
CHIP CARRIER (PLCCI
CASE 775

ORDERING INFORMATION
MC14XXXX~T

~ .SUffiX
1 2.5
2

-P
- L

V " Vref " VOO
Vref=VOO
Plastic (-40 to +85°CI

Ceramic (- 55 to + 125°CI

' - FN PLCC ( - 40 to + 85°CI

MUX OUT
AUTO· ZEROED
COMPARATOR

ANALOG
MUX

MUX ADDRESS
LATCH

INTERNAL TEST V,ef+VAG
VOLTAGE OF
2
DinJ127__________________~----__~~~--~~------~
Dout -1:.::6~----------_ % LSB.
VAG and Vref IPins 13 and 141
Analog reference voltage pins which determine the lower
and upper boundary of the AID conversion. Analog input
voltages 2: Vref produce an output of $FF and input voltages
$ VAG produce an output of $00. CAUTION: The analog input voltage must be 2:VSS and $VDD. The AID conversion
result is ratiometric to Vref - VAG as shown by the formula:
.
V ln

~[outPut code x (V
$FF

ref

;1

_ V
+ quantizing + linearity
AGj
error
error

SClK (Pin 181
Serial data clock. The serial data register is completely
static, allowing SCLK rates down to DC in a continuous or intermittent mode. SCLK need not be synchronous to the AID
CLK (MCl45040) or the internal clock (MC145041). Eight
SClK cycles are required for each simultaneous data transfer,
the low-to-high transition shifting in the new address and the
high-to-Iow transition shifting out the previous conversion
result. The address is acquired during the first four SCLK
cycles, with the interval produced by the remaining four cycles
being used to' begin charging the on-chip sample-and-hold
capacitors. After the eighth SCLK, the SCLK input is inhibited
(on-chip) until the conversion is complete.

Vref and VAG should be as noise-free as possible to avoid
degradation of the AID conversion. Noise on either of these
pins will couple 1: 1 to the analog input signal, i.e. a 20 mV
change in Vref can cause a 20 mV error in the conversion
result. Ideally Vref and VAG should be single-point connected
to the voltage supply driving the system's transducers.
PIN ASSIGNMENTS
~

z:
 238 ns.
EOC IPin 19, MC145041 only)
End-of-conversion output. EOC goes low on the negative
edge of the eighth SCLK. The low-to-high transition of EOC
indicates the AI D conversion is complete imd the data is ready
for transfer.



20
AN3

AID ClK (Pin 19, MC145040 only)

z

*

4

SClK

AN4

Din

AN5

Dout

CS

AN6
AN7
~

'"
.1.0
IlA

0.3xVOO 0.25xVOO
0.7xVOO
0.8xVOO
50
80
10
-50
-80
-10

0.2xVOO Vdc
Vdc
IlA
IlA

-

0.9
0.7

100

-

1

5.5
-0.2

-2

6
-0.2

Max.

0.45xVOO 0.3xVOO
0.55xVOO
'0.001
>0.1

1.1
0.8

8

1.0
0.75
50

-

1.1
0.8

Vdc
Vde

100

IlA

4
-0.1

-

mA
mA

18
1

-

0.5

1

1

mA

500

-

-

500

500

mW

VIN; O,IOUT; 0, COSC; 15 nF
Maximum Power Dissipation

SWITCHING CHARACTERISTICS (VOO
Characteristic

Clock High time
Clock Low time
Clock Rise time

Clock Fall time
Enable Lead time
Enable Lag time

Data Set-up time
Data Hold time
Scanner Frequencv*

Ose/Oigit Lead time
Osc/Segment Lead time
Digit Overlap

* Scanner Capacitance

Min.

>0,1

VILO
VIHO 0.75xVOO
IIOL
IIOH

700

25°
Max.

=

= 5V ± 10 0/0, TA = Oto 70 oC)

Fig.

Symbol

Min.

3
3
3
3
3
3
3
3
5
5
5
5

tCH
tCL
tCR
tCF
tElead
tElag
tOSup
tOHold
l/tScan
too
tos

2
2

Max.

tov

22nF.

4-9

Unit

".
2
2

200
200
200
1
50

PIN ASSIGNMENT

2

".

3

".

4

ns
ns
ns
300
10
10
5

d

".

IlS
Hz
".

".

IlS

VOO

18
17
16

b

9

15

5

Data

6

Ose

13

IV

12

8

III

9

VSS

14

11
II

10

II

MC14499

CIRCUIT OPERATION
The circuit accepts a 20-bit input, 16-bits for the four
digit display plus 4-bits for the decimal point - these
latter four-bits are optional.

SCANNER
The scanner frequency is determined by an on-chip oscillator, which requires an external frequency determining
capacitor. The capacitor voltage varies between two trigger
levels at the oscillator frequency.

The input sequence is the decimal point code followed by
the four digits, as shown in figure 2.
In order to enter data the enable input, EN, must be low,
O. The sample and shift are accomplished on the falling
clock edge, see figure 3. Data are loaded from the shift
register to the latches when EN goes high, = 1. While the
shift register is being loaded the previous data are stored
in the latches.

An external oscillator signal can be used, within the
recommended operating range of 200 to 800Hz - to
avoid flicker and digit overl'ap. For test purposes this
frequency can be increased up to 10kHz.

=>

II

A divide by four counter provides four non-over lapping
scanner waveforms, corresponding to the four digits see figure 5.

If the decimal point is used the system requires 20 clock
;:lUlses to load data, otherwise only 16 are required.
CASCADING

SEGMENT DECODER

The circuit may be cascaded in the following manner.

The code used in this matrix decoders is shown in
figure 6.

If a 1111 word is loaded into the decimal point latch, the
output of the shift register is switched to the decimal
point driver, see figure 4. Therefore, to cascade n four digit
display drivers a set-up is used which will firstly load
the 1111 cascading word:

OUTPUT DRIVERS

EN =0
2 Load 20-bits, the first four bits being 1, with 20
clock pulses.

There are two different drivers:
The segment and decimal point drivers; these are NPN
emitter followers with no current limiting devices.
The digit output buffers; These are short circuit
protected CMOS devices.

3 EN = 1, to load the latch
4 Repeat steps 1 to 3 (n-1) times
5 {nX20)-bits can be loaded into n circuits, with 1111
as decimal point word to continue the cascading.

A typical application circuit is shown in figure 7.

FIGURE 2 - INPUT SEQUENCE
.... time
Bit No.

CD

I~

Digit IV

CD

CD

~I~

Digit III

CD

~I

CD

CD

rn
:;;

rn

...J

Digit II

4·10

CD

I~

Digit I

CD

.. .. .. .

~I

'c, 'c, 'c,

'c,

i5 i5 i5 i5

Decimal Point

MC14499

FIGURE 3a - SERIAL INPUT, POSITIVE CLOCK

CL

DIN

____-' }--+_ _ _....f\.._____
D 2 _ - - - = x_ _ _
_ _ __
DN

II
FIGURE 3b - SERIAL INPUT, NEGATIVE CLOCK

---~

~-------LF-

CL

DIN _ _ _ _D_'_ _ _

1'-_+_""'"'"'1 ' -_ _ _

~=_

=:=x____

FIGURE 4 - CASCADING MC 144991

DIGIT

SEGM
h

----.jDATA
-~r--.jCLOCK

----iI-1.-1Eii

MC 14488

MC14499

(2)

(1)

4..11

MC14499
FIGURE 5 :j- SC~NNER WAVEFORMS

IOD

I/lose

OSC
ISCAN
DIGIT I

DIGIT D

I

DIGIT

m

DIGITllZ

SEGMENT
OUTPUTS
lOS

FIGURE 6 - SEGMENT CODE
0000

"

II

1000

CI

U
0001

()()10

()()11

01()()

0101

0110

0111

,

'.

q

.. 1()()1

2
3

II

1010

1-'

1011

,

-,

1100

I I
, I

5

1101

I ,

I

O.
I

I

4-12

I

',

U

1110

dash

1111

blank

MC14499
FIGURE 7 - APPLICATION EXAMPLE

SEGMENT

----.!!!

t

OUTPUTS

·

(7)

1S

b

~

c

~

•

Me'.... 9'

:l-

·•
f

c~

JSC]I

':ND

n

1

III

lLl

01-,

DIGIT

OUTPUTS .

#,1

(')

.... '0

.. 0,

0

n
n_0#.

J

J

I--=/1=2
I
",,0,

..,0.

1
Rl - RS: 36-82.11
22 nF

c:

VOO Typ: 5-6 V
IS max.: 40-50 mA
lomax.: SiS max.

-

1

III
0

Uo#.

....

....0.

II

®

MC14511B

MOTOROLA

BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER

I

CMOS MS.

The MC14511B BCD-to-seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers 'in a single monolithic structure.
The circu it provides the functions of a 4·bit storage hitch, an 8421
BCD-to·seven segment decoder, and an output drive capabinw. Lamp
test (L T!..blanking (si), and latch enable (LE) inputs are used to test
the display, to turn-off or pulse modulate the brightness of the
display, and to store a BCD code, respectively. It can be used with
seven-segment light emitting diodes (LED!. incandescent, fluorescent,
gas discharge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display driver, computer/calculator display driver, cockpit display driver,
and various clock, watch, and timer uses.
•

Quiescent Current ~ 5.0 nA/package typical

@

(LOW-POWER COMPLEMENTARY MOS)

BCD-TO-SEVEN SEGMENT
LATCH/DECODER/DRIVER

1

5V

•

Low Logic Circuit Power Dissipation

•

High·Current Sourcing Outputs (Up to 25 mAl

•

Latch Storage of Code

•

Blanking Input

•

Lamp Test Provision

•

Readout Blanking on all Illegal Input Combinations

P SUFFIX

PLASTIC PACKAGE
CASE 648

ORDERING INFORMATION
MC14XXXB

~ISUtfIX
L
P

,

A
.

,

Denotes
CeramiC Package
Plastic Package
Extended Operating
Temperature Range

C

Limited Operating
Temper:ature Range

•

Lamp Intensity Modulation Capability

•

Time Share (Multiplexing) Facility

•

Supply Voltage Range ~ 3.0 V to 18 V

B

•

Capable of Driving Two Low·power TTL Loads, One Low-power
Schottky TTL Load or Two HTL Loads Over the Rated
Temperature Range.

C

•

-

L SUFFIX
CERAMIC PACKAGE
CASE 620

PIN ASSIGNMENT
VDD

IT

f!Zlb

Iil

Chip Complexity: 216 FETs or 54 Equivalent Gates

LE

eel'

b

d

D
MAXIMUM RATINGS (Voltage, referenced to Vss)
Rating
Symbol
DC Supply Voltage
VDD
Input Voltage, All Inputs
Vin
DC Current Drain per Input Pin
I
Operating Temperature Range - AL Device

CL/CP Device
Storage Temperature Range
Maximum Output Drive Current

Value

A

Unit

-0.5 to +18
-0.5 to V DD + 0.5
10
-55 to +125
TA
-40 to +85
-65to+150
T,.!2,
25
IDHmax

VSS

V
V
mA

\0\ 1\2\3\ '-I\5\b \7\8\9\

°c

3

°c

(Source) per Output

*

POHmax

50

mA

Vss orVDDI.

T
LT D C B A

fNP

mW

This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high im·
pedance circuit. A destructive high current mode may occur if Vin and V out are not con~
strained to the range VSS 0:;;;; (Vin or V out ) 0:;;;; VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is
applied, and the outputs are shorted to VSS and are at a logical 1 (See Maximum
Ratings).
Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either

LE

Bf

x

x

X

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

5

6

x x x

X

X

X

X

X

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

X

X

X

X

.

OUTP

TS

b

,

d

,

f

9

1

1

1

1

1

1

0
1
0
1
1
0
1
0
1
1
1
0
0
0
0
0
0

0
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0

0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0

0
1
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0

0
1
0
1
0
0
0
1
0
1
0
0
0
0
0
0
0

0
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0

1
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0

DISPLAY
8
Blank

0
1
2
3
4
5
6
7
8
9
Blank
Blank
Blank
Blank
Blank
Blank

X;; Don't Care
·Oepends upon the BCO code previously applied
when LE "" 0

. 4-14

4

TRUTH TABLE

(Source) per Output

Maximum Continuous Output Power

d

MC14511B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

voo
Symbol

Vdc

"0" Level

VOL

50
10
15

"'" Level

VOH

5.0
10
15

Input Voltage"
IVo = 3.8 or 0.5 VI
IVo: 8.8 or 1.0 VI
(Vo = 13.8or 1.5 VI

"0" Level

VIL

(Vo =0.5 or3.8 VI
(VO = 1.0 or 8.8 VI
(VO=150r 13.8 VI

"'" Level

Characteristic
Output Voltage

VIO=VDOorO

V tn

""

0 or VOO

VIH

25°C
Min

0.05
0.05
0.05

0
0
0
4.1
9.1
14.1

4.1
9.1
14.1

Typ

1.5
3.0
4.0

5.0
10
15

=
=
=
=
=
=

OmAI
5.0 mAl
10 mAl
15 mAl
20 mAl
25mAI

10

(lOH
(lOH
(IOH
(IOH
(IOH
(lOH

=
=
=
=
=
=

OmAI
5.0 mAl
10mAI
15 mAl
20 mAl
25 mAl

15

2.25
4.50
6.75

V

V

4.1
9.1
14.1
1.5
3.0
4.0

1.5
3.0
4.0

2.75
5.50
8.25

3.5
7.0
11.0

4.10

4.10

4.1

3.90

3.90

4.57
4.24
4.12
3.94

9.10

3.40

3.70
3.54

910

9.58
9.26
917
9.04
8.90
8.70

9.00

9.00

8.60

8.60

14.1

14.1

14.0

14.0

13.6

136

14.59
14.27
1418
14.07
13.95
13.70

V

II

3.5
3.0
9.1

V

8.6
8.2
14.1

V

13.6
13.2
V

VOH
5.0

(IOH = OmAI
(lOH=50mAI
(lOH = 10mAI
(IOH = 15 mAl
(IOH = 20 mAl
(lOH = 25 mAl

10

(lOH = OmAI
(lOH = 50 mAl
(lOH = 10mAI
(lOH = 15 mAl
(IOH = 20 mAl
(IOH=25mAI

15

IOL

Umt

V

(lOH
(IOH
(lOH
(IOH
(IOH
(lOH

Output Drive Current (CLlCP Device)
Sink
(VOL =0.4 VI
(VOL =0.5 VI
IVOL = 15 VI

0.05
0.05
0.05

0.05
0.05
0.05

3.5
7.0
11.0

3.5
7.0
11.0

3.40

IOL

Thi h*
Max

Min

V

5.0

Output Drive Current (AL Device)
Sink
(VOL=04VI
(VOL = 0 5 VI
(VOL=15VI

Max

4.57
9.58
14.59

VOH

Source

Output Drive Voltage (CLlCP DeVice)
Source
(lOH= OmAI
(IOH=50mAI
(IOH=10mAI
(lOH = 15 mAl
(IOH = 20mAI
(lOH = 25 mAl

.
Max

5.0
10
15

Output DrIve Voltage (AL DeVIce)

(lOH = OmAI
(IOH = 5.0 mAl
(IOH= 10mAI
(IOH = 15mAI
(IOH=20mAI
(lOH = 25 mAl

Tlow
Min

4.10

4.10

3.60

3.60

2.80

2.80
9.10

9.10
8.75

8.75

8.10

810

14.1

14.1

13.75

13.75

13.1

131

457
4.24
412
394
375
3.54
958
9.26
9.17
904
8.90
8.75
1459
14.27
14.18
1407
1395
1380

4.1
3.3
2.5
9.1

V

8.45
7.8
14.1

V

13.45
12.8
rnA

5.0
10
15

0.64
16
4.2

051
13
34

0.88
225
88

0.36
0.9
2.4

5.0
10
15

052
13
36

0.44
11
30

088

036
09
24

rnA

2.25
88

(Continued)

4-15

MC14511B
ELECTRICAL CHARACTERISTICS (Continued)
Symbol

Voo
Vdc

Input Current (AL Device)

l,n

15

Input Current (CUep Device)

l,n

15

C,n

-

Characteristic

Input Capacitance

25°C

Max

to

Typ

1

-

Thi h'"

Max

Unit

±O 00001

±O 1

± 10

~A

± 1.0

Min

Max

±O3

-

±O 00001

±O 3

-

-

50

7.5

50
10
15

-

5.0
10
20

-

0.005
0.010
0.Q1 5

5.0
10
20

100

50
10
15

-

20
40
80

-

0.005
0.010
0.015

20
40
80

IPer Package) Vi"n=O or VOO,
lout = 0 ~A
(Per Package) Vin=O or VOD,
lout"" DJ,J,A
Total Supply Current··

.

100

QUiescent Current (AL Device)

QUiescent Current (CLlep Device)

Tlow

Min
-

t

IT

(DynamiC plus QUiescent,

Per Package)

50
10
15

Min

~A

pF

-

-

150
300
600

~A

150
300
600 _

~A

IT = 11.9 ~AikHzI f + 100
IT = (3.8 ~AikHzI f + I DO
IT = 15.7 ~AikHzI f + 100

~A

50 pF on all outputs, all
buffers SWitching)

1Cl

I

*Tlow;: -55°C for AL Device, -40°C for cLlep Device
Thigh =
25°C for AL Device, +85 0 C for cLlep Device.
itNolse Immunity specified for worst-case Input combmatlon
NOise Margin for both "," and "0" level =

tTo calculate total supply current at loads other than 50 pF

+'

ITICll

c

ITI50 pFI + 3.5 x 10-3 ICl -SOl VOOf

where IT IS 10 JiA (per package), CL In pF, VOO in Vdc,
and f 10 kHz is IOput frequency.
* *The formulas given are for the tYPical
characteristics only at 25°C.

1.0 Vdc mln@ VOO - 5.0 Vdc
2.0 Vdc min @ VOO = 10 Vdc
2.5 Vdc min@ VOO = 15 Vdc
SWITCHING CHARACTERISTICS* ICL = 50 pF, T A = 250 CI

Symbol

Characteristic
Output Rise TlfYlC

Voo
Vdc

tTLH

tTLH = (0.40 ns/pFI CL + 20 ns
tTLH = (0.25 os/pF) CL + 17.5 ns
tTLH = 10.20 os/pFI CL + 15 ns

5.0
10
15

Output Fall Time

tTHL

tTHL= (1.5 ns/pFI CL + 50 ns
tTHL = (0.75 ns/pF) CL + 37.5 ns
tTH L = (0.55 ns/pF I C L + 37.5 ns

5.0
10
15

Data Propagation Delay Time

tPLH
5.0
10
15

tPLH = 10.40 ns/pFI CL + 620 os
tPLH = (0.25 ns/pFI CL + 237.5 ns
'PlH = 10.20 nsipFI CL + 165 os
IpHL = 11.3 nsipFI CL +655 os
tpHL = 10.60 nsipFI CL + 260 os
IpHL = 10.35 ns/pFI CL + 182.5 os

tPHL

Blank Propagation Delay Time

5.0
10
15

tPLH

tpLH = (0.30 ns/pF) CL + 686 os
'PLH· (0.26 os/pF) CL + 187.5 ns
tpLH = (0.15 ns/pF) CL + 142.5 os

5.0
10
15

tPHL = 10.85 nsipFI CL + 442.5 os
tpHL = 10.45 nsipFI CL + 177.5 os
tpHL = (0.35 nsipFI CL + 142.5 ns

tpHL

Lamp Test Propagation Delay Time

5.0
10
15

'pLH
5.0
10
15

tpLH = 10.45 nsipFI CL + 290.5 ns
tPlH = 10.25 nsipFI CL + 112.5 ns
tPLH = 10.20 ns/pFI CL + 80 os
tPHL=I1.3ns/pFICL +2480s
tpHL = 10.45 nsipFI CL + 102.5 os
tPHL = 10.35 ns/pF) CL + 72.5 os

tpHL

Setup Time

Isu

Hold Time

th

Latch Enable Pulse Width

tWL

The formulas given are for the tYPical characterIStics only

4-16

5.0
10
15

Min

-

-

-

-

-

-

-

-

Typ

Max

40
30
25

80
60
50

125
75
65

250
150
130

640
250
175

1280
500
350

720
290
200

1440
580
400

600
200
150

750
300
220

485
200
160

970
400
320

313
125
90

625
250
180

313
125
90

625
250
180

Unit

ns

ns

ns

ns

ns

ns

5.0
10
15

100

40
30

-

-

5.0
10
15

60
40
30

-

-

-

-

5.0
10
15

520
220
130

260
110
65

-

os

-

ns

MC14511B
FIGURE 1 - DYNAMIC POWER DISSIPATION
SIGNAL WAVEFORMS
t nput LE low, and I "puts D. BT and IT high.
f in respect to a system clock.
All outPuts connected to respective CL loads.

20 ns
A, B, and C

50%OutvCvcle

~

Anv Output

VOH

50%

--VOL

FIGURE 2 - DYNAMIC SIGNAL WAVEFORMS

(allnputs 0 and LE low, and Inputs A, B, iii and LThigh.

Input C

(bllnput 0 low, Inputs A, B, iii and LT high.
20 ns
~=;-

LE

____ VOO

;:=___

_____..:..:~~I-....,--------

VSS

...:..\+______ Voo

Input C

50%

'------VSS
~-------------VOH

\L_ __________

Output 9

VOL

(e) Data DCBA strobed into latches.
20

20 ns

n$

r----VOO

LE

- - - - - - - - vSS

4·17

•

MC14511B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT

Vee

Common
Anode LED

::::=:::1.7 V

Common
Cathode LED

___

•

~1.7V

-= VSS

Vss

FLUORESCENT READOUT

Vee

INCANDESCENT READOUT

Vee

Vee

Filament
Supply

-=

-=

-=-

VSS

VSS

VSS or appropriate
voltage below VSS'

(CAUTION: Maximum working voltage = 18.0 V)
LIQUID CRYSTAL (LCD) READOUT

GAS DISCHARGE READOUT

Excitation
(Square Wave,

App rop ri ate

Vee

-=

Vee

Voltage

-=

VSS

**A filament pre-warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.

Direct de drive of

4-18

VSS to Voa)

Vss

LC~'s

not recommended for life of LCD readouts.

MC14511B
LOGIC DIAGRAM

13 a
A7

12 b

11 c

B 1

10 d

9.
151
C2

14 9

06

LE 5

VDD = Pin 16
VSS = Pin 8

4-19

•

®

MC14513B

MOTOROLA

BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER

•

CMOS MS.

The MC14513B BCD-to-seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure_ The circuit provides the functions of a 4-bit storage latch, an
8421 BCD-to-seven segment decoder, and has output drive capability_
Lamp test (LT), blanking (Si). and latch enable (LE) inputs are used
to test the display, to turn-off or pulse modulate the brightness of the
display, and to store a BCD code, respectively_ The Ripple Blanking
Input (RBI) and Ripple Blanking Output (RBO) can be used to
suppress either leading or trailing zeroes_ It can be used with
seven-segment light emitting diodes (LED), incandescent, fluorescent,
gas discharge, or liquid crystal readouts either directly or indirectly_
Applications include instrument (e_g_, counter, DVM, etc.)
display driver, computer/calculator display driver, cockpit display
driver, and various clock, watch, and timer uses.
•
Quiescent Current = 5.0 nA/peckage typical @l5 V
•
Low Logic Circuit Power Dissipation
•
High-current Sourcing Outputs (Up to 25 mAl
•
Latch Storage of Binary Input
•
Blanking Input
•
Lamp Test Provision
•
Readout Blanking on all Illegal Input Combinations
•
Lamp Intensity Modulation Capability
•
Time Share (Multiplexing) Capability
•
Adds Ripple Blanking In, Ripple Blanking Out to MC14511B
•
Supply Voltage Range =3.0 V to 18 V
•
Capable of Driving Two Low-Power TTL Loads, One Low-power
Schottky TTL Load to Two HTL Loads Over the Rated
Temperature Range.

(LOW-POWER COMPLEMENTARY MOS)

BCD-TO-8EVEN SEGMENT
LATCH/DECODER/DRIVER
WITH RIPPLE BLANKING

L SUFFIX
CERAMIC PACKAGE
CASE 726

OC Supply Voltage
Input Voltage, All Inputs
DC Current Drain per Input Pin
Operating Temperature Range - AL Device
CL/CP Oavice

Storage Temperature Range
Maximum Continuous Output Drive Current

""~m

115Uffi.

PIN ASSIGNMENT

·Oe

"

Unit

VOO

V

11

V

10

IOHma.

-0.5 to +18
-0.5 to V DO + 0.5
10
-55 to +125
-40 to +85
-65 to +150
25

POHma.

50

T stg

fl~b

12

mA

°c
°c

..

mA
mW

INPUTS

"" "
"a,
, a 0, ,,
a
a
,, ,,
x
a
x
a
, ,
X

X

X

X

X

1

tpOHma. = IOH (VOO - VOH)

This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. A destructive high current mode may occur if Vin and Vout is not constrained to the range Vss :s;;; (Vi" or V out ) ~ Vee.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is
applied, and the outputs are shorted to V S5 and are at a logical 1 (see Maximum
Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS

X
X

x
X
X

x
x
X
X
X
X
X
X
X

a
a
a
a

1
1
1

,,
,,
a
,,
a
,
a
a
,
a
, ,
0
0
0
0

1

,,
,,
,,
,

,,
,,
,
,

X -Don'teara

RBO

orVOO)·
•

4·20

d

13

Value

TA

•

,.
,.
la

17

Symbol

Vin
I

Oenot••

L Caramic Package
P Plastic Package
A Extended Operating
Temperature Range
e Limited Operating
Temperature Range

(Source) per Output

Maximum Continuous Output Power
(Source) per Output t

P SUFFIX
PLASTIC PACKAGE
CASE 707

OROERING INFORMATION

MAXIMUM RATINGS (Voltages referenced to Vss)
Rating

-

.. ~ .

0

RBI

IDCBA)

o c

,

A

x x x x

x x x x
a a a 0
0 0 a a
0 0 a
0 0
a
0 a

,,
,,,
a , ,
,,a
,, a, , ,,
a
,a,a
,, a, , ,
,, ,, aa, a,
, , , a,
0

0 0
0

0
0

0 0
0

X

X

X

X

OUTPUTS
"'0 , ,, , ,, , ,, ,,

··,
a
a
a
a
0

a
a
a
0
0

a
a
a

a
a
a

·

a a a a
a a a a

00 0
00 0

,,,,,,a
,, ,,, ,, a,, a, aa a,,
a
a , , a a , ,
,a ,,a,
,, , ,, , , ,
,, ,, ,, ,, , ,, a,
,

a

0

0

1
1

0

0 0 0
0

a a a a a a
o 0 0 0 a a
0000 a a
0000 a a
a a a a 0 a
a a a a a a

,nd,cated by other row. of table

Depends upon the BCD codeprev,ously appl'ed when LE -0

a
a
a
a
a
a

DISPLAY

8
Blank
Blank

a

,

.
2
3

5
6

,,
9
Blank
Blank
Blank
Blank
Blank
Blank

MC145138
ELECTRICAL CHARACTERISTICS IVoltages Referenced to Vssl

Output Voltage - Segment Outputs
"0" Level
V In = VOD or

"'" Level

VOH

Output Voltage - RBO Output
"0" Level

VOL

"1" Level

VOH

"0" Level

VIL

Vln=OorVOD

50
10
15

4.1
9.1
14.1

IVO" 0.5 or 3 8 V) "1" Level
IVO" 1.0 or 8.8 VI
IVO" 1.5 or 13.8 VI

VIH

Output Dnve Voltage - Segments

VOH

50
10
15

Max

0
0
0

0.05
0.05
005

Min

Max

Unit

005
0.05
0.05
4.1
91
14.1

5.0
10
15

V

4.95
9.95
14.95

0
0
0
4.95
9.95
14.95

005
0.05
0.05

0.05
0.05
0.05
4.95
9.95
14.95

5.0
10
15

V

V

5.0
10
15

1.5
3.0
4.0
3.5
7.0
11.0

2.25
4.50
6.75
3.5
7.0
11.0

2.75
5.50
8.25

1.5
3.0
4.0

1.5
3.0
4.0
3.5
7.0
11.0

V

V

(lOH"OmAI
(lOH" 5.0mAI
(lOH" 10 mAl
IIOH" 15 rnA)
(lOH "20 mAl
IIOH "25 mAl

10

(lOH"O rnA)
(lOH "5.0 mAl
(lOH" 10 mAl
(lOH=15 mAl
(lOH" 20 mAl
(lOH "25 mAl

15

Source:

Thigh*

Typ

V

5.0

Source'

4.1
9.1
14.1
0.05
0.05
0.05

5.0
10
15

IVO " 38 or 0.5 VI
IVo " 8.8 or 1.0 VI
IVO" 13.8 or 1.5 VI

leL/ep Oevicel
(lOH"OmAI
IIOH = 5.0 mAl
(lOH" 10 mAl
(lOH" 15 mAl
(lOH 20 mAl
IIOH "25 mAl

Min

005
0.05
005

5.0
10
15

V In ~ VOO or 0

Output Dnve Voltage - Segments

Max

V
50
10
15

Vm = OorVOD

IAL Oevicel
(lOH" OmAI
(lOH" 50 rnA)
(IOH " 10 mAl
IIOH" 15 mAl
(lOH "20 rnA)
(lOH" 25 mAl

Min

VOL

a

Input Voltage.#:

Vdc

25°C

Tlow*

Vee
Symbol

Characteristic

4.10

4.10

3.90

3.90

3.40

3.40

9.10

9.10

9.00

9.00

8.60

8.60

14.1

14.1

14.0

14.0

13.6

13.6

4.57
4.24
4.12
3.94
3.75
3.54
9.58
9.26
9.17
9.04
8.90
8.75
14.59
14.27
1418
14.07
13.95
13.80

4.1
3.5
3.0
9.1

V

8.6
8.2
14.1

V

13.6
13.2
V

VOH
5.0

0

IIOH" 0 mAl
(lOH "5.0 mAl
IIOH = 10 mAl
IIOH" 15 mAl
(lOH" 20mA)
(lOH = 25 mAl

10

IiOH" OmAI
(lOH "5.0 mAl
IIOH " 10 mAl
(lOH = 15 mAl
(lOH ~ 20 mAl
(lOH = 25 mAl

15

4.10

410

360

3.60

• 2.80

2.80

9.10

9.10

8.75

875

8.10

8.10

14.1

14.1

13.75

13.75

13.1

131

4-21

4.57
4.24
4.12
3.94
3.75
3.54
9.58
9.26
917
9.04
890
875
14.59
14.27
14.18
14.07
13.95
1380

4.1
3.3
2.5
9.1

V

8.45
7.8
141
13.45
128

V

•

MC14513B
ELECTRICAL CHARACTERISTICS (Continued)
Svmbol

Output Drive Current

RBO Output

(AL Device)
(VOH = 2;5 V)
(VOH = 9.5V)
(YOH = 13.5 V)

Output Drive Current

•

Sink

RBO Output

(C LlCP Device)
(YOH = 2.5 V)
(VDH = 9.5V)
(YOH = 13.5 V)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)

Output Drive Current - Segments
(AL Device)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL=1.5V)

IOL

TVp

5.0
10
15

-0.40
-0.21
-0.81

5.0
10
15

0.18
0.47
1.8

5.0
10
15

-0.25
-0.13
-0.52

5.0
10
15

0.12
0.30
1.2

-

-

-

-0.64
-0.34
-1.3

-

0.15
0.38
1.5

0.29
0.75
2.9

-

0.10
0.26
1.0

Unit

-0.21
-0.11
-0.44

-0.64
-0.34
-1.3

-

-0.17
-0.092
-0.36

-

0.098
0.25
0.98

0.29
0.75
2.9

-

0.080
0.21
0.80·

-

-

-0.22
-0.12
-0.46

-

-

mA

mA

-

-

-

mA

mA

5.0
10
15

-

0.64
1.6
4.2

0.51
1.3
3.4

-

0.88
2.25
8.8

-

0.36
0.9
2.4

-'j

mA

IOL
5.0
10
15
lin

-

0.52
1.3
3.6

-

15

0.88
2.25
8.8

-

±O.OOOOl

±0.1

-

±0.00001

±0.3

5.0

0.44
1.1
3.0

±0.1

15

-

±0.3

I "put Capacitance

Cin

-

-

-

Quiescent Current (AL Device)
(Per Package) Vin = 0 or VDD,
lout = 0 IJA

100

5.0
10
15

5.0
10
20

-

-

0.005
0.010
0.015

Quiescent Current (CL/CP Device)
(Per Package) Vin = 0 or VDD,
lout = 0 IJA

100

-

20
40
80

-

0.005
0.010
0.015

= -55°C

Max

-0.32
-0.17
-0.66

lin

*Tlow

Min

mA

Input Current (CLJCP Device)

Total Supply Current**t
(DynamiC plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

Thigh"
Max

IOL

Sink

Input Current (AL Device)

Min

Max

IOH

Sink

Output Drive Current - Segments
(CL/CP Device)
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)

IOL

Source

Sink

Min

IOH

SOU rca

(VOL = 0.4 V)
(VOL = 0.5V)
(VOL = 1.5 V)

25°C

Tlow·

Voo
Vdc

IT

5.0
10
15
5.0
10
15

-

0.36
0.9
2.4

-

-

±1.0

IJA

-

±1.0

IJA

7.5

-

-

pF

5.0
20

-

150
300
600

IJA

10

-

20

-

-

150
300
600

IJA

40
80

IT - (1.9IJA/kHz) 1+ 100
IT = (3.8IJA/kHz) I + 100
IT = (5.7 IJA/kHz) 1+ 100

for AL Device, -40°C for CL/CP Device.

t To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 3 ..5 x 10-3 (CL - 50) VDDI

Thigh = +125 0 C lor AL Device, +25 0 C lor CL/CP Device.

where: IT is in p,A (per package), CL in pF, VOO in V,
and f in kHz is input frequency.

# Noise immunity specified for worst-case input combination.
Noise Margin for both "1" and "0" level =
1.0 V min@ VDD = 5.0 V
2.0Vmln@VDD=10V
2.5 V min@ VDD = 15 V

** The formulas given are for the typical characteristics
only at 25°C.
FIGURE 1 - DYNAMIC POWER DISSIPATION
SIGNAL WAVEFORMS

Input LE and RBI low, and Inputs D,

BT and

[ f high.

f in respect to a system clock.

All outputs connected to respective CL loads.

A, 8, and C

50% Duty Cycle

Any Output

·IJA

~

'VDH

50%

--VOL

4-22

MC14513B
SWITCHING CHARACTERISTICS' ICL

50 pF TA

25°C)

All Types
Characteristic

Output R 15e Time - Segment Outputs

Symbol

VOO
Vdc

RBO Output

Typ

Max

--

40
30
25

80
60
50

480
240
190

960
480
380

ns

tTLH
50
10
15

Output Fall Time~Segment Outputs"
tTHl = (1.5 ns/pF) Cl + 50 ns
tTHl = (0.75 n%~~F) Cl + 37.5 ns
tTHl = (0.55 n%~~F) Cl + 37.5 ns

tTHL

Output Fall Time - RBO Outputs

tTHl

tTHl
tTHl
tTHl

= (3.25 n%~~F)
= (1.35 n%~~F)
= (0.95 ns/pF)

Cl + 107.5 ns
Cl + 67.5 ns
Cl + 62.5 ns

Propagation Delay Time-A, B. C, D Inputs·
tpLH 1040 ns/pF) CL + 620 ns
tpLH 1025 ns/pF) CL + 237.5 ns
tPLH' 10.20 ns/pF) CL + 165 ns

tpLH

113 ns/pF) CL t 655 ns
= 10.60 ns/pF) CL + 260 ns
tpHL -- 1035 ns/pF) CL + 182.5 ns
Propagation Delay Time-RBI and BI Inputs·

tPHL

tPHL
tPHL

tPlH
tpLH
tpLH

= (1.05 ns/pF)
= (0.45 n%~~F)
= (0.30 n%~~F)

Propagation Delay Time-LT Input*

Setup Time

Hold TIme

Latch Enable Pulse Width

----

125
75
65

250
150
130

5.0
10
15

----

270
135
110

540
270
220

5.0
10
15

--

640
250
175

1280
500
350

720
290
200

1440
580
400

ns

ns
.-

ns

--

5.0
10
15

---

600

750

200

300

--

150

220

50
10
15

--

---

485
200
160

970
400
320

5.0
10
15

----

313
125
90

625
250
180

5.0
10
15

--

313
125
90

625
250
180

ns

5.0
10
15

100

--

ns

th

5.0
10
15

60
40
30

-------

twL(LE)

5.0
10
15

520
220
130

260
110
65

---

ns

tPLH

tPHL

tPHL

tsu

*The formulas given are for the typical characteristics only.

4·23

ns

ns

tplH

tpLH = 10 45 ns/pF) CL + 290.5 ns
tpLH = 10.25 ns/pF) CL + 112.5 ns
tpLH ,. 10 20 ns/pF) CL + 80 ns
tPHL" 11 3 ns/pF) CL + 248 ns
tpHl ' 10.45 ns/pF) Cl + 102.5 ns
tpH L = 10 35 ns/pF) CL + 72.5 ns

ns
50
10
15

50
10
15

Cl + 547.5 ns
Cl + 177.5 ns
CL + 135 ns

tpHL" 10.85 ns/pF) CL + 442.5 ns
tPHL -- 10.45 ns/pF) CL + 177.5 ns
tPHL = 10.35 ns/pF) CL + 142.5 ns

Unit

ns
50
10
15

Output Rise Time

Min

tTLH

--

--

40
30

---------

ns

ns

•

MC145138
FIGURE 2 - DYNAMIC SIGNAL WAV·EFORMS

a. Data Propagation Delay: Inputs RBI, 0 and LE low, and Inputs A. B. B1 and Li'high.

20 ns

20 ns
Vee

9:1

50%1

10Y\

Inpute

----4

vss

tPL~HPHL
--VOH
Output 9

VOL
tTLH

•

tTHL

b. Inputs A, B, 0 and LE low, and Inputs RBI,

BT and

[Thigh.

c. Se1:up and Hold Times. Input RBI and 0 low, Inputs A,

a, BT and IT high.

2onsl§
, , - - - - - - - Vee
90%
50%

LE

_ _ _ _ _~10~%~T--------------VSS

'npute

F tsu~
50%

ith

Vee

\ ' -_ _ _ __

.

Vss

~---------------------VOH

Output 9

\\._ _ _ _ _ _ _ _ _ __
.
VOL

d. Pulse WIdth: Data DCBA strobed into latches.

, ~
rI

,
20ns--.-j

LE

i--20ns
1_ _ _ _ _ Vee

90%U
: '
50% I
10%
-----VSS
tWULE,--1

4·24

~

MC14513B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LEDI READOUT

Voo

Common
Anode LEO
Common
Cathode LED

""'.7V

:::::::1.7 V

•

FLUORESCENT READOUT

Voo

INCANDESCENT READOUT

Voo

Voo

Filament
SupplV

LIQUID CRYSTAL (LCI READOUT

GAS DISCHARGE READOUT

Excitation
(Square Wave,

Appropriate
Voltage

Voo

Voo

vSS to Voo)

•

114 Of MC14070B

**A filament pre-warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.

Direct de drive of Le's not recommended for lifa of LC readouts.

4-25

MC14513B
LOGIC DIAGRAM

15 a
A7
14 b

13 c

B 1

•

12 d

11 •

17 f
C2
16g

D6

LE 5

TYPICAL APPLICATIONS FOR RIPPLE BLANKING
LEADING EDGE ZERO SUPPRESSION

Displays

I I

I

MC145138
Input

Code

o

0

0

101

0

MC145138

o

0

0
(01

MC145138

o

0

I

I I

I

MC145138

1

(51

o

0
(01

4·26

0

0

I
I

I

MC145138

o

0

0
(11

1

MC14513B

o

0

1
(31

MC14513B
TYPICAL APPLICATIONS FOR RIPPLE BLANKING (Cont)
TRAILING EDGE ZERO SUPPRESSION

D,splays

,-----,

I
I
MC14513B

o

1

0
(51

1

I

I I
I I
MC14513B

a

a a
(0)

0

,-----,

I
I

I
MC14513B

o

0

0

1

MC145138

a a

(11

1

(31

4-27

MC14513B

a a
(01

a a

MC14513B

a a a a
(0)

Input Code

®

MC14543B

MOTOROLA

CMOS MS.
BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER
for LIQUID CRYSTALS

(LOW-POWER COMPLEMENTARY MOS)

The MC14543B BCD-to-seven segment latch/decoder/driver is
designed for use with liquid crystal readouts, and is constructed with
complementary MaS (CMOS) enhancement mode devices_ The circuit provides the functions of a 4-bit storage latch and an B421 BCDto-seven segment decoder and driver. The device has the capability
to invert the logic levels of the output combination_ The phase (Ph),
blanking (BI), and latch disable (LD) inputs are used to reverse the
truth table phase, blank the display, and store a BCD code, respectively_ For liquid crystal (LC) readouts, a SQuare wave is applied to
the Ph input of the circuit and the electrically common backplane
of the display_ The outputs of the circuit are connected directly to
the segments of the LC readout_ For other types of readouts, such
as light-emitting diode (LED), incandescent, gas discharge, and
fluorescent readouts, connection diagrams are given on this data
sheet_
Applications include instrument (e_g_, counter, DVM etc.) display
driver, computer/calculator display driver, cockpit display driver,
and various clock, watch, and timer uses.

•

BCD-TO-SEVEN SEGMENT
LATCH/DECODER/DRIVER
for
LIQUID CRYSTALS

L SUFFIX

P SUFFIX

CERAMIC PACKAGE

PLASTIC PACKAGE

CASE 620

CASE 648

1t

ORDERING INFORMATION

•
•
•
•
•
•
•

•
•

.".,m

5.0 nA/package Typical @
Logic Circuit Quiescent Current
5V
Latch Storage of Code
Blanking Input
Readout Blanking on All Illegal Input Combinations
Direct LED (Common Anode or Cathode) Driving Capability
Supply Voltage Range = 3.0 V to 18 V
Capable of Driving Two Low-power TTL Loads, One Low-power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range
Pin-for-Pin Replacement for CD4056A (with Pin 7 Tied to VSS).
Chip Complexity: 207 FETs or 52 Equivalent Gates

MAXIMUM RATINGS

LD

Value

Unit

-0.5 to +18

V

Input Voltage, All Inputs

Vin

-0.5 to VDD + 0.5

V

DC Input Current per Pin

'in

±10

mA

TA

-55 to +125
-40 to +85

°c

CLlCP Device

Storage Temperature Rance
Maximum Continuous Output Drive Current

(Source or Sink) per Output
Maximum Continuous Output Power*
(Source or Sink) per Output

.

T stg

-65 to +150

°c

'OHmax
IOLmax

10

mA

POHmax

70

mW

POLmax

POHmax -- IOH (VOH - VDD) and PDLmax - IOL (VOL - VSS)

4·28

P
A

Plastic Package
Extended Operating
Temperature Range
Limited Operatmg
Temperature Range

TRUTH TABLE

VDD

Operating Temperature Range - AL Device

Ceramic Package

INPUTS

Symbol

DC Supply Voltage

Oenote,

L

C

(Voltages referenced to VSS)

Rating

SUff ,"

8\

Ph·

OUTPUTS

0

C B

x

X
0
0
0
0
1
1
1
1
0
0
0
0
1

0
0
0
0
0
0
0
0
1
1
1
1
1

A abc

X X 0
0 0 1
0 1 0
0 1
1 1
0 0 0
0 1
1 0

0

1

0
1
1
0

d

e

f

9

Display

0
1
0
1
1
0
1

0

0
1
0

0
0
0

Blank

0

1 1
0 1
0 1 1
0 1
1 1
1 1
0 0
1
0 1 1 1
1 0 0 0 0 0
0 0 BI,mk
1 1 0 0 0 0
0 0
0 0 0 0 0
0 0
0
0 1 0 0 0
1 0 0 0 0
0 0
11110000000
X X X X

Inverse of Output
CombinatIOns
Above

Display
as above

X = Don't care
t = Above Combinations
• = For liqUid crystal readouts, apply a square wave to Ph
For common cathode LED readouts, select Ph = 0
For common anode LED readouts, select Ph = 1
.... Depends upon the BCD code preViously applied when LD = 1

MC14543B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSSI
Characteristic

Symbol
"0" Level

Output Voltage
V,n VOO or 0

"1" Level

o or VOO

V,n

IVo
(Vo
(Vo

c

VOH

(VOH" 2.5 VI
(VOH "4.6VI
(VOH" a 5 VI
(VOH "9.5 VI
(VOH "13.5 VI
(VOL ~ 0.4 VI
(VOL - 0.5 VI
(VOL ~ 9.5 VI
(VOL" 1.5VI

Typ

Max

Min

50
10
15

-

0.05
005

-

0.05
005
005

-

-

a
a
a

50

4.95
9.95
14.95

-

4.95
9.95
14.95

5.0
10
15

-

15
5.0
10
15

-

1.5
3.0
40

-

2.25
4.50
675

5.0
10
15

3.5
7.0
110

-

3.5
7.0
11.0

5.0
5.0
10
10
15
5.0

-3.0
-0.64

-

-2.4
-0.51

-

-

Sink

Output Drive Current (CL/CP Device)
Source
1VOH: 2.5 VI
(VOH "4.6 VI
(VOH" 0.5 VI
1VOH" 9.5 VI
1VOH : 13.5 VI
Sink
(VOL" 0.4 VI
(VOL" 0.5 VI
(VOL" 9.5 VI
1VOl" 1.5 VI

IOl

10
10

IOl

(DynamiC plus QUiescent,
Per Package)

-

-

-

-1.3
-3.4
0.51
1.3

-

5.0
5.0
10
10
15
5.0
10
10
15

-2.5
-0.52

-

-2.1
-0.44

-

-1.3
-3.6
0.52
1.3

-

-

3.6

-1.1
-3.0
0.44
1.1

-

V

15
3.0
4.0

-

1.5
3.0
4.0

2.75
550
825

-

3.5
7.0
11.0

-4.2
-0.88
-10.1
-2.25
-8.8
0.88
2.25
10.1
8.8

-

-1.7
-0.36

-

-0.9
-2.4
0.36
0.9

-

3.0

-

-

-

V

-

V

-

rnA

-

-

-

-

-

2.4

-

-1.7
-0.36

-

-

-

rnA

rnA

-4.2
-0.88
-10.1
-2.25
-8.8
0.88
2.25
10.1
8.8
to 00001

-

2.4

-

±O 1

-

± 1.0

"A

to 00001

± 03

-

± 10

"A
pF

-

-

-0.9
-2.4
0.36
0.9

-

-

-

rnA

1.03

C,n

-

-

-

-

50

7.5

-

-

100

50

-

15

-

50
10
20

-

0.005
0.010
0.015

50
10
20

-

150
300
600

"A

10

50
10
15

-

20
40
80

-

150
300
600

"A

100

IT

± 01

-

5.0
10
15

0.005
0.010
0.015

IT"(1.6 "A/kHzI
IT"(3.1 "A/kHzI
IT"(4.7 "A/kHzI

(Cl "50 pF on all outputs, all
buffers sWitching)

*Tlow -55°C for AL DeVice, -40°C for CLlCP DeVice.
Thigh +125 0 C for AL DeVice, +85 0 C for CLlCP DeVice .
.;..:Nolse Immunity spe(;lfled for worst·case Input combmatlon
NOise Margin for both "1" and "0" level ::: 1.0 V min @ VDO = 5.0 V

2.0 V rnin@Voo" 10 V
2.5 V min @VOO" 15 V
tTo calculate total supply current at loads other than 50 pF

ITICll

-

15

IJA

Total Supply Current·' t

495
9.95
14.95

-

-

= 0 JJ.A

=0

V

-

-

IPer Packagel Vin"O or VOO,
lout

-1.6
-4.2
0.64
1.6

3.4

I,n

QUiescent Current (CLlCP DeVice)

-

-

Input Current (CLlCP DeVice)

lout

-

4.2

15

(Per Package) V,n=O or VOQ.

-

15

1m

QUiescent Current (AL DeVIce)

-

IOH

Input Current (AL DeVice)

Input Capacitance

a as

Unit

0.05
0.05
0.05

IOH

Source

Thi h*
Max

Min

VIH

IVo - 0.5 or 4.5 VI
IVo - 1.0 or 9.0 VI
(Vo - 1 5 or 13 5 VI
Output Drive Current (AL Device)

25°C

Max

VIL

4.5 or 0.5 VI
9.0 or 1.0 VI
1350r15VI
"1" level

.

Min

10
"0" Level

Input Voltage;!

VOL

Tlow

VDD
Vdc

IT(50 pFI + 3.5 x 10- 3 ICl -50) VOOI

where IT IS In ~A (per package), CL In pF, V DD in V, and f In kHz IS input frequency.
~ *The formulas given are for the tYPical characteristics only at 25°C.

4-29

20
40
80
f
f
f

+ 100
+ 100
+ 100

-

-

"A

MC14543B

SWITCHING CHARACTERISTICS·

(CI.

= 50 pF

TA

Characteristic
Output Rise Time

tTI.H
tTLH
tTLH

•

= (3.0 ns/pF), CI. + 30 ns
= (1.5 n./pF) CL + 15 ns
= (1.1 ns/pF) CI. + 10 ns

= 25°C)
Symbol

Output Fall Time
tTHL = (1.5 ns/pF) CI. + 25 ns
tTHI. = (0.75 ns/pF) CL + 12.5 ns
tTHI. = (0.55 ns/pF) CL + 12.5 ns

tTHL

Turn·Off Delay Time
tpLH = (1.7 ns/pF) CL + 520 ns
tPI.H = (0.66 ns/pF) CL + 217 ns
tPI.H = (0.5 ns/pF) CI. + 160 ns

tPLH

Turn-On Delay Time

tpHI.

tPHI.
tpHI.
tPHL

= (1.7 ns/pF) CI. +420 ns
= (0.66 ns/pF) CL + 172 ns
= (0.5 ns/pF) CL + 130 ns

Setup Tim.

Letch Disable Pulse Width (Strobing Date)

Min

Typ

Max

5.0
10
15

-

-

100
50
40

200
100
80

5.0
10
15

-

100
50
40

200
100
80

5.0
10
15

-

605
250
185

1210
500
370

-

505
205
155

1650
660
495

-

-

-

ns

125
50
40

-

-

ns

Unit
ns

ns

ns

-

ns
5.0
10
15
5.0
10
15

-

th

5.0
10
15

350
450
500
40
30
20

tWH

5.0
10
15

250
100
80

tsu

Hold Time

VDD

tTLH

ns

-

*The formulas given are for the tYPical characteristicS' only.

LOGIC DIAGRAM

Voo

= Pin 16

VSS = Pin 8

9 a

A 5

10 b
11 c

B 3

12 d
13 •

C2

15 f
14 g

04

LD 1

4-30

MC14543B

FIGURE 2 - TYPICAL OUTPUT SINK

FIGURE 1 - TYPICAL OUTPUT SOURCE
CHARACTERISTICS

CHARACTERISTICS

24

i

-6.0 I----jf--'=->!_-+-+-+--.....~f--'--l

::<

\

.5

I-

~

I-

/

~

~ -12 1---t--t=--t---r---'1oo''--1---t---j

~
~
z

w
'-'

12

'"

'"=>

in

51

..:; o
g 6.

~ -181--t-~~~~1--+-~-t---t

Vss = 0 Vdc

-24~~__~__~~L--L__~L-~~

oo

-16
-12
-8.0
-4.0
(VOH -Voal, SOURCE OEVICE VOLTAGE (Vdcl

FIGURE 3 - DYNAMIC POWER DISIPATION
SIGNAL WAVEFORMS

IS Vdc

J,
\

....

,

10 Vdc

VOO

/V

~

52

VOO

,1/

18

"

~SrdC

-I-

I-- POl max = 70 jWdC
I
I
VSS=OVdc

•

4.0
ao
12
16
(Val - VSSl.SINK DEVICE VOLTAGE (Vdcl

FIGURE 4 - DYNAMIC SIGNAL WAVEFORMS
(a) Inputs D, Ph, and 81 low, and Inputs A, B. and LD high.

c

' t ._____

Inputs 81 and Ph low, and Inputs 0 and LD high.
f in respect to a system clock.

Jt=

________~10%~

All outputs connected to respective CL loads.

tTLH

VSS

VOH
VOL

:::oJ

(bl Inputs 0, Ph, and BI low, and Inputs

A and B high.

VDO
--~--,L-+--------------------VOD

---Vss

LD
. , . . . . - - - - - - - - - - - - - - - - VSS

50% Duty Cycle
Any Output

~

c

VOH

~..=:.---...._I---t.::h~------

VOO

' - - - - - - - - - - - - VSS

---VOL

\..

VOH

'---VOL

0 ----------

(e) Data DCBA strobed into latches
LD

4-31

50%
-----tWH

VDD

- - - - - - - - - VSS

MC14543B

CONNECTIONS TO VARIOUS DISPLAY READOUTS

INCANDESCENT READOUT
Appropriate
Voltage

LIQUID CRYSTAL (LCI READOUT
MC14543B
Output
Common
Backplane

Ph

Square Wave
(VSS to vOO)

•

GAS DISCHARGE READOUT
LIGHT EMITTING DIODE (LEDI READOUT
Common

Common

Cathode LED

Appropriate
Voltage

Voo

Anode LED

Note: Bipolar transistors may be added for gain (for VOD ~10V or lout ~ 10 mAl.

CONNECTIONS TO SEGMENTS

PIN ASSIGNMENT

LO

fl~b

VOO

·Oc

C
B

d

0

4

13

A

5

12

Ph

6

11
10

BI
Vss

Voo = Pin 16

8

9

d

VSS

..

= Pin 8

DISPLAY

b

101 112131'-115161718191
0

4·32

3

4

6

8

9

®

MC14544B

MOTOROLA

CMOS MS.

BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER
FOR LIQUID CRYSTALS

(LOW·POWER COMPLEMENTARY MOS)

BCD-TO-SEVEN SEGMENT
LATCH/DECODER/DRIVER
WITH RIPPLE BLANKING

The MC14544B BCD-to-seven segment latch/decoder/driver is
designed for use with liquid crystal readouts, and is constructed with
complementary MOS (CMOS) enhancement mode devices. The circuit provides the functions of a 4-bit storage latch and an B421 BCDto-seven segment decoder and driver. The device has the capability
to invert the logic levels of the output combination. The phase (Ph),
blanking (BI), and latch disable (LD) inputs are used to reverse the
truth table phase, blank the display, and store a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is applied to
the Ph input of the circuit and the electrically common backplane
of the display. The outputs of the circuit are connected directly to
the segments of the LC readout. The Ripple Blanking Input (RBI)
and the Ripple Blanking Output (RBO) can be used to suppress
either leading or trailing zeroes.
For other types of readouts, such as light-emitting diode (LED),
incandescent, gas discharge, and fluorescent readouts, connection
diagrams are given on this data sheet.
Applications include instrument (e.g., counter, DVM etc.) display
driver, computer/calculator display driver, cockpit display driver,
and various clock, watch, and timer uses.
•

Logic Circuit Quiescent Current = 5.0 nA/package typical
5V

•
•
•
•
•
•
•

Latch Storage of Code
Blanking Input
Readout Blanking on All Illegal Input Combinations
Direct LED (Common Anode or Cathode) Driving Capability
Supply Voltage Range = 3.0 V to 18 V
Capability for Suppression'of Non·significant zero
Capable of Driving Two Low-power TTL Loads, One Low-power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range

MAXIMUM RATINGS

,,~,,~'~M~U
1

L SUFFIX
CERAMIC PACKAGE
CASE 726

P SUFFIX
PLASTIC PACKAGE
CASE 707

ORDERING INFORMATION
MOO,"'"

11SUffiX

Denotes

L Ceramic Package
P
A
C

PlastiC Package
Extended Operating
Temperature Range
Limited Operating
Temperature Range

@
PIN ASSIGNMENT

,.

•

18
17

I.
I.
13

'l'nb

·Oc
d

12

11
10

(Valtages referenced ta VSS)
Symbol

Value

Unit

VDD

-0.5 ta +18

Vde

Input Voltage. All Inputs

Vin

-0.5 ta VDD + 0.5

Vde

DC Input Current per Pin

lin

±10

mAde

TA

-55 to +125
-40 to +85

°c

Rating
DC Supply Valtage

Operating Temperature Range - AL Device
C LlCP Device

T stg

-65 to +150

DC

Maximum Continuous Output Drive Current
(Source or Sink) per Output

'OHmax
IOLmax

10

mAde

Ma)(imum Continuous Output Power*
(Source or Sink) per Output

POHmax
POlmax

70

mW

Storage Temperature Range

-

*POHmax - IOH (VOH - VDD) and POlmax - IOl (VOL - VSS)

4·33

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit. For proper
operation it is recommended that Vin and
Vout be constrained to the range VSS .s;;
(Vin or V aut ) .. VDD'

Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
Vssar VDD).

•

MC14544B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vss)
Characteristic

Output Voltage

Symbol

"0" Level

VOL

Vin = VOO or 0
"1" Level

VOH

Vin = 0 or VOO
Input Voltage#

IVo
IVo
(Vo

•

"0" Level

"'" Level
(VO = 0.5 or 4.5 V)
IVo = 1.0 or 9.0 V)
(Vo = 1.5 or 13.5 V)
Output Drive Current (AL Device)
Source
(VOH = 2.5 V)
(VOH =4.6V)
IVOH = 0.5 V)
(VOH =9.5 V)
(VOH = 13.5 V)
Sink
(VOL = 0.4 V)
(VOL =0.5 V)
(VOL = 9.5 V)
(VOl=1.5V)

VIH

Output Orive Current ICLlCP Oevice)
(VOH = 2.5 V)
Source
(VOH = 4.6 V)
(VOH =0.5 V)
(VOH =9.5 V)
(VOH = 13.5 V)
Sink
(VOL =0.4V)
(VOL =0.5 V)
(VOL =9.5 V)
(VOL = 1.5 V)

IOH

Input Current (CLlep DeVice)

Input Capacitance
QUiescent Current tAL DeVice)

IOL

IOl

Per Package)

2SoC

Max

Min

Typ

Max

5.0
10
15

-

0.05
0.05
0.05

-

0.05
0.05
0.05

5.0
10
15

4.95
9.95
14.95

-

5.0
10
15

-

1.5
3.0
4.0

5.0
10
15

3.5
7.0
11.0

-

5.0
5.0
10
10
15
5.0
10
10
15

-3.0
-0.64

-

5.0
5.0
10
10
15
5.0
10
10
15

-2.5
-0.52

-

-

-

-

-1.6
-4.2
0.64
1.6

-

4.2

V

4.95
9.95
14.95

-

V

1.5
3.0
4.0

-

5.0
10
15

-

-

1.5
3.0
4.0

-

-

2.25
4.50
6.75

3.5
7.0
11.0

2.75
5.50
8.25

-

3.5
7.0
11.0

-2.4
-0.51

-4.2
-0.88
-10.1
-2.25
-8.8
0.88
2.25
10.1
8.8

-

-1.7
-0.36

-4.2
-0.88
-10.1
-2.25
-8.8
0.88
225
10.1
8.8
to.OOOOl

-

-

2.4

-

±0.1

± 10

~A

to.OOOOl

±03

±1.0

",A

50

7.5

-

0.005
0.010
0.Q15

50
10
20

-

-

V

-

-1.3
-3.4
0.51
1.3

3.4

-

_.

-1.3
-3.6
0.52
1.3

-

-

3.6

-

15

100

5.0
10
15

-

5.0
10
15

-

±O 1
0.3

±

-

-

-2.1
-0.44

-1.1
-3.0
0.44

1.1

3.0

-

5.0
10
20

-

20
40
80

-

5.0
10
15

-

IT
IT
IT

0.005
0.010
0.Q15

=
=
=

-

-

V

-

-

-

-

-0.9
-2.4
0.36
0.9

-

2.4

-

-1.7
-0.36

--

-

-

-

_55°C for AL Device, -40 oC for CL/ep Device.

Thigh'" +125 0 C for AL Device. +85 0 C for cLlep Device .
.txNoise Immunity specified for worst-case input combination.
NOise Margm for both "1" and "0" level'" 1.0 V min @ VOD :::: 5.0 V

2.0 V min @ VOO = 10 V
2.5 II min @ V 00 = 15 V
fTo calculate total supply current at loads other than 50 pF:

IT(Cl) = IT(50 pF) + 3.5 x 10-3 (CL -50) VOOI
where: 'IT IS in lolA (per package), CL in pF, Vee in Vdc, and f in kHz is input frequency.
**The formulas given are for the typical characteristics only at 2SoC.

4·34

-

-

-

20
40
80

(1.6 ",A/kHz) I + 100
(3.1 ",A/kHz) I + 100
(4.7 ",A/kHz) I + 100

buffers SWitching)

=

0.05
0.05
0.05

4.95
9.95
14.95

-

(Cl = 50 pF on all outputs. all

*T,ow

Unit

-

0
0
0

-

-

mA

mA

'in
Con

IT

-

-

15

100

Thi h*
Min
Max

mA

lin

(Per Package) Vin=O or VOO.
lout = O",A
Total Supply Current· .. t
(DynamiC plus QUiescent,

.

IOH

(Per Package) Vin=O or VOO.
lout = 0 ",A
QUiescent Current (CUe? DeVice)

Tlow
Min

VIL

= 4.5 or 0.5 V)
= 9.0 or 1.0 VI
= 13.5 or 1.5 V)

Input Current tAL Device)

Voo
Vdc

-0.9
-2.4
0.36
0.9

-

-

-

-

-

mA

-

-

pF

150
300
600

"A

150
300
600

",A

",A

MC145448
SWITCHING CHARACTERISTICS·

(CL = 50 pF TA

Characteristic
Output Rise Time

tTLH
tTLH
tTLH

= (3.0 n,/pFI CL + 30 ns
= (1.5 ns/pFI CL + 15 ns
= (1.1 ns/pFI CL + 10 ns

Output Fall Time

tTHL
tTHL
tTHL

VDD

Min

Typ

Max

5.0
10
15

-

100
50
40

200
100
80

100
50
40

200
100
80

-

605
250
185

1210
500
370

5.0
10
15

-

505
205
155

1650
660
495

10u

5.0
10
15

0
0
0

-40
-15
-10

th

5.0
10
15

80
30
20

40
15
10

twH

5.0
10
16

250
100
80

125
50
40

tTHL
5.0
10
15
tPLH
5.0
10
15

Setup Time

HoidTime

Latch Disable Pulse Width (Strobing Data)

-

-

-

ns

ns

ns

tpHL

= (1.7 ns/pFI CL + 420 ns
= (0.66 ns/pFI CL + 172 ns
= (0.5 ns/pFI CL + 130 ns

*The formulas given are for the typical characteristics only.

LOGIC DIAGRAM

Vee = Pin 18
VSS = Pin 9

AS

8 3

C 2

04

LO 1

4-35

Unit

ns

tTLH

= (1.7 ns/pFI CL + 520 ns
= (0.66 ns/pFI CL + 217 ns
= (0.5 ns/pFI CL + 160 ns

Turn-On Delay Time

tpHL
tPHL
tpHL

Symbol

= (1.5 ns/pFI CL + 25 ns
= (0.75 ns/pFI CL + 12.5 ns
= (0.55 ns/pFI CL + 12.5 ns

Turn-Off Delay Time

tpLH
tpLH
tpLH

= 250 Cl

ns

-

-

ns

ns

..

MC14544B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
INCANDESCENT READOUT

L1aUID CRYSTAL (LC) READOUT

Appropriate
Voltage

MC14544B
Output
Common
Backplane

Ph

Square Wave
1VSS to VOO>

•

GAS DISCHARGE READOUT
LIGHT EMITTING DIODE (LED) READOUT
Common

Von

LD

, ,,

X

0

x
x
X
X
X
X

X

x
X
X

X

,
,,
,
,,
,,
1

,

BI

,

Ph·

a
a
a
a

a

0
0

a

0
0

a
a
a
a

X

,,
,

X

0

0
0
0
0
0

t

t

t

X

X
X
X

1

1

0
0
0
0

a
0

a
a
a
a
a
a
a
0
0
0
0
0
1

D C

B A

RBO

,

b

,

.

,

d

f

1
X

X

x x x
a a a
a 0 a
a a
a
a

0

1

a
a
a
a

,,
,
,,
,
1

"
a
a
a

1
1
1
1

t

X

"
t

Blank

a
2

1
1

1

..

1

,
3

#

4

5
6
7
8
9
Blank

Blank
Blank
Blank
Blank
Blank

..

Inver'" 01 Output

D.os>lay

Combona"on. AbOlle

... above

Don't·Care
Above Combinations

For liquid crystal readouts, apply a square wave to Ph. For
common cathode LED readouts, select Ph ~ O. For common
anode LED readouts, .elect Ph ~ 1.
Depend. upon the BCD Code previously applied when LD • 1.

Blank

1

1

X

DISPLAY

1

1

1
1
1

X
t

OUTPUTS

, 0a, aa 00 0a a0 a0 0a
,,, ,0
,
a
,,
, a, a, 0 0a 0,
0
, 0 a a0 a, ,, a, aa a, ,,
, ,, ,,
,a
,, , a 00 , aa , 0, , ,
, , a ,, , a a, a, a
a a a
0
,,,a,,
a
a a ,
a , a
a
a a a 0 0 0 0
,
,
a
,, 0 0, aa a0 a0 00 00 00 00 00
,, 0, 0, a0 00 00 00 00 00 0a a0
a
0 0 0 0 0 0 0

x
a
a
a
a

Voltage

~10V or lout ~ 10 rnA).

TRUTH TABLE
INtJUTS

Apl=.lropriate

Anode LED

Note: Bipolar transistors may be added for gain (for

RBI

Voo

Common

Cathode LED

4-36

RBO~RBI •

CASCO>

MC14544B
FIGURE 2 - TYPICAL OUTPUT SINK

FIGURE 1 - TYPICAL OUTPUT SOURCE
CHARACTERISTICS

-

" 6.0
1-

~HjaX

~

V~O~

=romWr c

.....

/

' ...

~OO =';Q;J;',



/

o
';: -18

-

VOO = 15 Vdc
-24
-16

-r

Vss = 0 Vdc

1
-12

~
~

«

\

18

/

~
'"~

"....

'"z

":\,

'52"

,

/

12

..J 6.0

77

~

o 0

VOO = 15 Vdc

1/

I

~

....

-4.0

-8.0

\

,

'\

V

I--

52

V '/

CHARACTERISTICS
24

,

VOO - 10 Vdc

~5.0Ivdc
4.0

", I-...

-

r-

' - POl ma• = 70 lWdc
I
I
VSS = 0 Vdc
8.0

12

•

16

(VOL - VSS), SINK DEVICE VOLTAGE (Vdc)

(VOH -Voo), SOURCE DEVICE VOLTAGE (Vdc)

FIGURE 3 - OYNAMIC POWER DISIPATION
SIGNAL WAVEFORMS

FIGURE 4 - DYNAMIC SIGNAL WAVEFORMS
(al Inputs D, Ph, and 81 low, and Inputs A, B, and LD high.

c

~---------~-+~----VDD
""'----VSS

Inputs 81 and Ph low, and Inputs 0 and LD high.
f in respect to a system clock.

All outputs connected to respective CL loads.

20n.~on.

A, B. and C

90%

10%

50%

l/t

tTLH

---VSS

~

:::J

(b) Inputs D, Ph, and BI low, and Inputs

VDO
LD

50% Duty Cvcle
Any Output

t=

________~1~0%~

VOH

C

VOH
V

OL

A and B high.

--~--~-+--------------------VDD
"1<-____________________ VSS

~~------~r_=~t~h-------VDD
' - - - - - - - - - - - - - VSS

---VOL

"

VOH
'---VOL

(c) Data DCBA strobed into latches

LD

4·37

,~----------VOD

-----~-:-; I--J ,,-------- VSS

MC145448
TYPICAL APPLICATIONS FOR RIPPLE BLANKING
LEADING EDGE ZERO SUPPRESSION

,

DIsplays

I

•

MC14544B

MC14544B
000

Input

Code

o

0

101

0

0

o

101

0

151

0

0

-"

MC14544B

MC14544B

o

o

101

0

0

1

111

0

1

131

,

Displays
~-----,

I

I
I

/" I
I I

MC14544B

MC14544B

MC14544B

o

o

o

0
151

o

1

I

TRAILING EDGE ZERO SUPPRESSION

,
1

MC14544B

MC14544B

o

0

I
/

I I
I I

1

0

0

101

0

0

0

1

,-----,

-'

MC14544B

o

0

1

131

111

4-38

MC14544B
0 0 0

o

101

MC14544B

o

0

0
(0)

0
Input Code

®

MC14547B

MOTOROLA

CMOS MS.

HIGH CURRENT
BCD-TO-SEVEN SEGMENT DECODER/ DRIVER

(LOW-POWER CDMPLEMENTARV MOSI

HIGH CURRENT
BCD-TO-SEVEN SEGMENT
DECODER/DRIVER

The MC14547 BCD-to-seven segment decoder/driver is constructed
with complementary MOS (CMOSI enhancement mode devices and
NPN bipolar output drivers in a single monolithic structure. The circuit
provides the functions of an 8421 BCD-to-seven segment decoder with
high output drive capability. Blanking (81), can be used to turn off or
pulse modulate the brightness of the display. The MC14547 can drive
seven-segment light-emitting diodes (LEDI, incandescent, fluorescent
or gas discharge readouts either directly or indirectly.
Applications include Instrument (e.g., counter, DVM, etc.1 display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses.

•
•
•
•
•
•
•
•

High Current Sourcing Outputs (Up to 65 mAl
Low Logic Circuit Power Dissipation
Supply Voltage Range = + 3.0 V to + 18 V
Blanking Input
Readout Blanking on All Illegal Combinations
Lamp Intensity Modulation Capability
Multiplexing Capability
Capable of Driving Two Low-Power TTL Loads,
One Low-Power Schottky TTL Load or
Two HTL Loads over the Rated Temperature Range
• Use MC14511 B for Applications Requiring Data Latches

L SUFFIX

PSUFFIX

CERAMIC PACKAGE

PLASTIC PACKAGE

CASE 620

CASE 648

ORDERING INFORMATION
MC14XXXB ~SUffIX
L

Denotel

CeramIc Package
Plaitlc Package
Extended OperatIng
Temperature Range
LImIted Operatmg
Temperature Range

P
A

C

16
15
3

14

4

13

'l'n
eel

MAXIMUM RATINGS

Rating
DC Supply Voltage

Input Voltage, All Inputs
Operating Temperature Range

MC14547BAL
MCI4547BCL/CP

8

9

Symbol

Value

Unit

DISPLAY

VDD

-0.5 to +18

V

Vin

-0.5toVDD +0.5

V

-55to +125
-40 to +85

°c

lOl/12131'-llSlb17181QI

TA

T stg

-65 to +150

°c

Maximum Continuous Output Drive Current
(Source) per Output

'OHmax

65

mA

Maximum Continuous Power Dissipation

POHmax

Storage Temperature Range

d

"'0

* IVoltage referenced to VSS. Pin 81

b

c

'2

1200'

4

TRUTH TABLE

o

INPUTS

mW

c

d

e

, ,,

0
1
1

1
1
1

1
1

0
1
0
1
1
0
1
1
0

0
1
0
1
0
0
0
1
0
1

0
0
0
0
0
0
0

°

BI

D C B A a

* Maximum Ratings are those values beyond which damage to the deVice may occur.

,

*See power derating curve (Figure 1).

1
1
1
1
1
1
1

X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

0

This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high im·
pedance circuit. A destructive high current mode may occur if Vin and Vout is not
constrained to the range VSS ~ (Vin or Voutl ~ VOO·

,
1
1

Due to the sourcing capability of this circuit, damage can occur to the device if VOO is
applied, and the outputs are shorted to VSS and are at a logical 1 {See Maximum
Ratingsl.

1
1
1

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either

1

Vss or VDDI.

0

0

,, ,,
°
,

0

0
1
0
1
1
1
0
0
0
0
0
0

°

0
1
1

= Don't care

,

1
1
1
1
0
0
0
0
0
0

, ,

°
0
0
0

, , ,° °

x

4·39

X X X
0 0 0
0 0 1
0
0
0
1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0
0
0 1 1
1 0 0
1 0 1
1
1 1 1

b

0

0
0
0
0
0
0

,

TP T
0
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0

9

DISPLAY

0
0
0
1
1
1
1

Blank

,

0
1
1
0
0
0
0
0
0

0
1

2
3
4

5
6
7

8
9
Blank
Blank
Blank
Blank
Blank
Blank

•

MC14547B

.

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSI
Symbol

Characteristic.
Output Voltage
Vin = VDD orO

"0" Level

"1" Level

VOL

VOH

V,n' = 0 or VDD

II

Input Voltage #
IVa = 3.8 or 0.5 VI
IVa = 8.8 or 1.0 VI
IVa = 13.8 or 1.5 VI
IVa = 0.5 or 3.8 VI
IVa = 1.0 or 8.8 VI
IVa = 1.5 or 13.8 VI
Output Drive Voltage IAL Devlcel
IIOH = 5.0 mAl
IIOH = 10 mAl
IIOH = 20 mAl
IIOH = 40 mAl
IIOH = 65 mAl
IIOH = 5.0 mAl
IIOH = 10mAI
IIOH = 20 mAl
IIOH = 40 mAl
IIOH = 65 mAl
IIOH = 5.0 mAl
IIOH = 10 mAl
IIOH = 20 mAl
IIOH = 40 mAl
IIOH = 65 mAl
Output Dnve Voltage ICL/CP Devicel
IIOH = 5.0 mAl
IIOH = 10 mAl
IIOH = 20 mAl
IIOH = 40 mAl
IIOH = 65 mAl
IIOH = 5.0 mAl
IIOH = 10 mAl
IIOH = 20 mAl
IIOH = 40 mAl
IIOH = 65 mAl
IIOH = 5.0 mAl
IIOH = 10 mAl
IIOH = 20 mAl
IIOH = 40 mAl
IIOH = 65 mAl
Output Drive Current IAL Devicel
IVOL = 0.4 VI
IVOL = 0.5 VI
IVOL = 1.5 VI
Output Drive Current ICLlCP Devlcel
IVOL = 0.4 VI
IVOL = 0.5 VI
IVOL = 1.5 VI

"0" Level

"1" Level

Voo
Vdc
5.0
10
15
5.0
10
15

Tlow
Min Max

Typ

Max

-

0.05
0.05
0.05

-

0.05
0.05
0.05

4.1
9.1
14.1

-

4.4
9.4
14.4

0
0
0
4.6
9.6
14.6

3.5
7.0
11.0

1.5
3.0
4.0

-

1.5
3.0
4.0

-

3.5
7.0
11.0

2.25
450
6.75
2.75
5.50
8.25

4.2
4.1
3.9
3.7
3.2
9.2
9.1
9.0
8.9
8.5

-

VOH

5.0
10
15
5.0
10
15
5.0

Source

10

-

-

8.4

-

14.0

-

-

-

13.8

13.5

V

4.3
9.3
14.4

-

V

1.5
3.0
4.0

-

3.5
7.0
11.0

4.3
4.3
4.2
4.0
3.7
9.3
9.3
92
9.0
8.8

-

4.3

-

-

4.0
3.0
9.3
9.2
8.1

14.2
14.1
14.0
13.8
13.5

143
14.3
14.2
14.0
13.7

-

14.4

-

-

-

'-

-

-

-

-

-

-

-

14.2

-

-

-

13.3

-

4.3
4.3
4.2
4.0
3.7
9.3
9.3
9.2
9.0
8.8
14.3
14.3
14.2
14.0
13.7

-

4.2

-

-

-

13.6

-

13.0

-

4.1
4.0
3.8
3.5
3.0
9.1
9.0
8.8
8.5
8.1
14.1
14.0
13.8
13.5
13.0

5.0
10
15

0.32
0.80
2.10

-

0.26
0.65
1.7

0.44
1.13
4.4

5.0
10
15

0.26
0.65
1.8

-

-

0.22
0.65
1.5

0.44
1.13
4.4

-

10

3.0
8.9

8.6

15

V

-

-

V
3.9
3.6

8.0
13.9

-

-

-

3.9

-

-

-

2.9
9.2

-

9.0

-

-

-

-

-

8.0
14.2

-

14.0

-

-

-

13.0

-

0.18
045
1.2

-

0.18
0.45
1.2

-

-

-

mA

IOL

-

-

mA

IOL
Sink

-

5.0

Source

Sink

Unit

0.05
0.05
0.05

V

-

3.8
31
9.1

-

15

-

4.0

8.8

VOH

Thigh'
Min Max

V

VIL

VIH

25'C
Min

*Tlow = -55'C for AL DeVice, -40'C for CLlCP DeVice
Thigh = + 125'C for AL DeVice, +65'C for CLlCP DeVice
#Noise Immunity specified for worst-case Input combination.
NOise Margin for both "1" and "0" level =
1.0 V min @ VDD = 50 V
2.0 V min @ VDD = 10 V
2.5 V min @ VDD= 15 V

4-40

-

-

MC145478

.

ELECTRICAL CHARACTERISTICS (Contlnuedl

Characteristic

Symbol

Input Current (AL Devicel
Input Current (CLlCP Devlcel
Input Capacitance

QUiescent Current (AL Devicel (Per Packagel
V,n~O or VDD, 10ut~0 ~A
QUiescent Current ICLlCP Devlcel (Per Packagel
VIn~O or VDD, 10ut~0 ~A

I,n
lin
C,n
IDD

IDD

Total Supply Current""t

IT

!Dynamic plus QUIescent,

Per Package I
ICL ~ 50 pF on all outputs, all

VDD
Vdc
15
15
5.0
10
15
5.0
10
15
5.0
10
15

Tlow
Min Max
- ±0.1
±0.3

-

-

-

Min

-

-

50
10
20
20
40
80

-

-

IT
IT
IT

~
~
~

25°C
Thi
Typ
Max Min
± O.aml ±O.t
± oamI ±03
50
75
0005
5.0
0010
10
0015
20
0.005
20
0010
40
0015
80

h'
Max

Unit
~A

±10
±10

~A

150

~A

pF
300

600
150

~A

300

600

II 9 ~A/kHzl f + IDD
(3.B ~A/kHzl f + IDD
(5.7 ~A/kHz) f + IDD

~A

buffers sWitching)

•

"Tlow ~ -55°C for AL Device, -40°C for CLlCP Device
Thigh ~ + 125°C for AL Device, +85°C for CL/CP Device

t To calculate total supply current at loads other than 50 pF:
IT (CL) ~ IT (50 pF) + 3.5 x 10- 3 ICL - 50) VDDf
where: IT is In ~A (per package), CL in pF, VDD in V,
and f in kHz is Input frequency .
•• The formulas given are for the typical
characteristics only at 25°C.

SWITCHING CHARACTERISTICS (CL ~ 50 pF TA ~ 25°CI
Symbol

Characteristic

Output Rise Time

tTLH

Output Fall Time

tTHL

Data Propagation Delay Time

tPLH

tPHL

Blank Propagation Delay Time

tPLH

tpHL

4-41

VDD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15

Min

Typ

Max

Unit

-

40
40
40
125
75
70
750

80
80
80

ns

250
150
140
1500
600
400
1500
600
400
1500
600
400
1000
500
340

ns

-

-

-

-

-

300

200
750
300
200
750
300
200
500
250
170

ns

ns

MC14547B

LOGIC DIAGRAM

8T4

---1+-+-....."",-----------,

A 7 -__

13 a

12 b

B 1 -

---I+++,

......

11 c

•

10 d

C 2 -....---~,..

9 e

15 f

06-----4
14 9

FIGURE 1 - AMBIENT TEMPERATURE POWER DERATING
1200

I

~

1000

~

i"'--.

.........
.........

...........

~~ 800
5<

........

.........

"'~

~: 600
~~

.......
:'>..

CP DEVICE

...-CL DEVICE

K
..........

'"

,.~

/AL DEVICE

"<.

~~

400
200

o

25

50

75 85
100
125
TA. AMBIENT TEMPERATURE lOCI

4-42

150

175

MC14547B
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT

Voo

Common
Anode LED
Common
Cathode LED

___

::::::: 1.7 V

~'.7V

-= VSS

Vss

INCANDESCENT READOUT

LIGHT-EMITTING DIODE (LED) READOUT
USING A ZENER DIODE TO REPLACE DROPPING RESISTORS

Voo

Voo

Common
Cathode LED

-= VSS
GAS DISCHARGE READOUT

Voo

APpropriate
Voltage

-: vss
FLUORESCENT READOUT
VOO

Direct
(Low Brightness)

-=

VSS

• VZD should be set at VDD - 1,3 V - VLED, Wattage of zener
diode must be calculated for number of segments and worst-case

conditions .
•• A filament pre-warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the
filament.

Filament

.". VSS

Supply

Vss or appropriate
voltage below VSS,
(Caution: Absolute maximum

working voltage:: 18.0 V)

4·43

•

®

MC14558B

MOTOROLA

CMOS MS.

BCD-TO-SEVEN SEGMENT DECODER

(LOW.pOWER COMPLEMENTARY MOSI

II

The MC14558B decodes 4-bit binary coded decimal data dependent on the state ofauxiliary inputs, Enable and RBI, and provides an
actIve-high seven-segment output for a display driver.
An auxiliary input truth table is shown, in addition to the BCD
to seven·segment truth table, to indicate the functions available with
the two auxiliary inputs.
Leading Zero blanking is easily obtained with an external flip·flop
in time division mUltiplexed systems displaying most significant
decade first.

BCD-TO-SEVEN
SEGMENT DECODER

• Quiescent Current = 5.0 nA/package typical @ 5 Vdc
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Segment Blanking for All Illegal Input Combinations
• Lamp Test Function
• Capability for Suppression of Non·Significant Zeros
• Lamp Intensity Function
• Capable of Driving Two Low·power TTL Loads, One Low·power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range

LSUFFIX

P SUFFIX

CERAMIC PACKAGE

PLASTIC PACKAGE

CASE 620

CASE 648

ORDERING INFORMATION
00".,,,

11SUII..

Oenot••

L

Ceramic Package

P
A

PlastiC Package
Extended Operating
T8mperatur. Range
Limited Operating

e

Temperatur. Range

MAXIMUM RATINGS IVoltages referenced to VSS)
Rating

DC Supply Voltage
Input Voltage, All Inputs

DC Input Current, per Pin
Operating Temperature Range .- AL DeVice

PIN ASSIGNMENT

Symbol

Value

Unit

VDD
Von
lin
TA

-0.5 to +18
-0.5 to VDD + 0.5
±10

Vdc
Vdc

CLICP DevIce

Tstg

Storage Temperature Range

°c

-65 to +150

°c

AUXILIARY INPUT TRUTH TABLE

BCD
Enable
Pin 3

RBI

Input

RBO

Pin 5

Code

Pin 4

0

0

X

0

Lamp Test

mAde

-55 to +125
-40 to +85

16
2

15

3

14

4

13

5

12

6

11

7

to

8

9

fl~b

°0<
d

F unction Performed

0

1

X

1

Blank Segments

I

I

I

Display Zero

1

0

0
0

0

I

X

1·9

I

Blank Segmen ts
1-9 Displayed

DISPLAY

o
X"" Don't Car.
RBI a Ripple Blanking Input
R80 ,. Ripple BI.,kinl Output

4-44

2

3

4

5

6

8

9

MC145588

.

ELECTRICAL CHARACTERISTICS (Voltages Relerenced to V.s.s)
Characteristic

Symbol
"0" Level

Output Voltage

VOL

VIO:: VODorO

"1" Level

VOH

V,n=OorVOD
"0" Level

Input Voltage'"

IVa

= 4.5 0' 0.5 Vdcl
= 13.5 0'

1.5 Vde)
"1" Level

IVa c 0.5

Or

IVOH = 2.5 Vdcl
(VOH = 4.6 Vdcl
(VOH = 95 Vdcl
(VOH = 13.5 Vdcl
IVOL
IVOL
IVOL

Sink

10L

= 0.5 Vdcl

= 1.5 Vdc)

Output Drtve Current (ClICP Devicel
Source
(VOH = 2.5 Vdcl
(VOH =·4.6 Vde)
(VOH. 9.5 Vde)
(VOH = Il.5 Vde)

Typ

Mo.

-

0.05
0.05
005

-

0

a

-

0.05
0.05
0.05

Vdc

-

0.05
0.05
0.05

-

4.95
9.95
14.95

-

Vdc

5.0
10
15

-

5.0
10
15

4.95
9.95
14.95

5.0
10
15

-

-

50
10
15

3.5
7.0
11.0

50
5.0
10
15

-3.0
-0.64
-1.6
-4.2

..

5.0
10
15

0.64
16
4.2

..

5.0
5.0
10
15

-2.5
-0.52
-1.3
-3.6

-

5.0
10
15

0.52
1.3
3.6

..

-

1.5
3.0
4.0

-

1.5
3.0
4.0

-

3.5
7.0
11.0

2.75
5.50
8.25

-

3.5
7.0
11.0

-2.4
-0.51
-1.3
-3.4

-4.2
-0.88
-2.25
-8.8

-

-1.7
-0.36
-0.9
-2.4

0.51
1.3
3.4

0.88
2.25
8.8
-4.2
-0.88
-2.25
-8.8
0.88
2.25
8.8
to 00001

-

-

-

..

..

..

-

..

-

to 1

-

15'

-

tOl

Input Capac,tam:e

C,"

-

-

-

QUiescent Current (AL Devlcel
Vi~=OorVOO
(Per Package I
lout=O~

100

..

SO
10
20

QUlescem Current fCLlCP Devlcel
Vin=O or VOO
(Per Packaqel

100

Input Current (AL Devlcel

Input Current (CL/CP DeVice'

10L

lout=OpA
Total Supply Current .... t
(DynamiC plus aUlescenl,

Per Packaqel
CCl'"' 50 pF on all outputs, all
buffers switching)

-

Vdc
1.5
3.0
4.0

IT

-

Vdc

-

-

-

-

-

0.36
0.9
2.4

-

-1.7
-0.36
-0.9
-2.4

..

mAde

mAde

10H

..

=0.5 Vdcl
= 1 5 Vdcl

Unit

mAde

15

Sink

-

2.25
4.50
675

I,"
I,n

= 0.4 Vdc)

0
5.0
10
15

4.95
9.95
14.95

-2.1
-0.44
-1.1
-3.0
0.44
1.1
l.O

(VOL
(VOL
IVOL

Th' h·
Min
Mo.

Min

10H

Source

=0.4 Vdcl

25"<:

Mo.

VIH

4 5 Vdcl

(Va = 1.00,9.0 Vdcl
(Va = 1 50' 13.5 Vdcl
Output Drtve Current (AL Devlcel

Tlow

Min

VIL

IVO '" 9.0 or 1.0 Vdc)

(Va

Voo
Vdc

50
10
15
50
10
15

..

..

..

..

20
40
80

..

-.

50
10
15

-

±O.OOOOI

-

SO

..

0.005
0.010
0.015
0.005
0.010
0.015

..

-

IT
IT
IT

..
..

-

..
..

0.l6
0.9
24

-

-

..
..

mAde

-

±O 1
t03

-

",Adc

..

tl.0
±1.0

7.5

-

..

pF

5.0
10
20

..
..
..

150
loo
600

~Adc

20
40
80

..

150
lOO
600

",Adc

= 11.2 I'A/kHz) I + 100
= 12.4I'A/kHz) ,+ 100
= (3.6I'AlkHz) ,+ 100

..

..

",Adc

#JAde

·Tlow = -55°C for AL DeVice. _40°C for Cl/CP Device.
Thigh = • 125°C for AL DeVice, +85 0 C for CL/CP DeVice.
Immunltv specified fOI WOlst-case mput combination
NOise Margin fOJ borh "1" and "0" level, III '1.0 Vdc min @ V DO = 5.0 Vdc
2.0 Vdc m,n @ VOO' 10 Vdc
2.5 Vdc min @ VOO = 15 Vdc
tTo calculate total supply current at loads other than 50 pF
ITIClI - ITI50 pF) + 4. 10-3 1CL -SOl VOO'
where I, IS In IJA Cper packagel. CL In pF. VOO In Vdc. and f In kHz is Input frequency.
·-The formulas given are for the typical characteristics only at 2SoC.
~Nolse

This device'contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is ad·
vised that normal precautions be taken to avoid application of anv voltage higher than maximum rated voltages to this high im·
pedance circuit. For proper operation it is recommended that Vin and V out be constrained to the range VSS ifi; (Vi" or Voutt
';;VOO·
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Vss or VOO).

4·45

•

MC14558B
SWITCHING CHARACTERISTICS·
Ch_lotic

(CL· 50 pF. TA • 25°C; _ Figure 1)
Sjmbol
VDD

Outpu, RI.. Tim.
'TLH' (3.0 n./pF) CL + 30 no
'TLH· n.s n./pF) CL + 15 no
'TLH • n.l n./pF) CL + 10 n.
Outpu, Foil Tim.
tTHL· n.s n./pF) CL + 25 n.
'THL - (0.75 ns/pF) CL + 12.5 n.
'THL· (0.55 n./pF) CL + 9.5 no

•

Min

Typ

Mo.

S.O
10
15

-

100
40

200
100
80

5.0
10
15

-

100
50
40

200
100
80

580
220
145

1160
440
230

780
275
185

1660
550
370

'TLH

'THL

Propagation Delay Time
'PLH = 11.7 n./pF) CL + 495 nl
tPLH· (0.66 nl/pF) CL + 187 nl
'PLH' (O.S nl/pF) CL + 120 nl
Propagation DeilY Time
'PHL' (1.7 nl/pF) CL + 895 nl
'PHL' (0.S6 ns/pF) CL + 242 no
'PHL • (0.5 nl/pF) C + 160nl

50

5.0
10
15
'PHL
5.0
10
15

...
n.

--

'PLH

Unit

n.

nl

• The formulae given are for the typical characteristics only.

TRUTH TABLE
INPUTS

Enable

RBI

Pm 3

Pin 5

0
Pin 6

OUTPUTS'

Pin 2

a
Pin 1

Pin 1

C

A

•
Pin 13

b

Pin 12

c
Pm 11

d
Pm 10

•

Ping

f

Pin 15

g
Pin 14

RaO
Pin 4

DISPLAV

1

1

0

0

0

0

1

1

1

1

1

1

0

1

0

1

x

0

0

0

1

0

0

0

0

1

1

0

1

I
I

1

X

0

0

1

0

1

1

0

1

1

0

1

1

1

x

0

0

1

1

1

,

1

1

0

0

,

1

1

X

0

1

0

0

0

1

1

0

0

1

1

,

1

X

0

1

0

1

1

0

1

1

0

1

1

1

1

X

0

1

1

0

0

0

1

1

,

1

1

,

1

X

0

1

1

1

1

1

1

0

0

0

0

1

1

X

1

0

0

0

1

1

1

1

1

1

,

,

1

X

1

0

0

1

•

•

•

0

•

•

•

0

0

0

1

,

0

1

0

0

0

°,

1

0

0

0

0

0

0

0

0

0

0

X

X

X

X

1

1

1

°
0
,

0

1

X

X

X

X

0

0

0

0

-All non·v.hd SCD Input COd_I prod,,~. b'enk dl.,oIY.
X .. Don't:

ear.
FIGURE 1 - SIGNAL WAVEFORMS
20 ns
Any Input

Any OutPut

---..;.-.....

4-46

2
3
'-{

5
b'"')
I

8
q

alenk

8

."nk

MC14558B

•

4-47

MC14558B
TYPICAL APPLICATIONS
FIGURE 2 - LEADING AND TRAILING Z~RO
SUPPRESSION WITH LAMP TEST
N3

N4

Vss

-

RBi

•

N2

RiO ,.-- RBI

RiO I-- RBI

RiiO

En

En

En

1

1

I

N1

N·2

N·1

r- RBI RiO

Rifi

l

RiO

ABI

N·3

RiO

En

En

En

1

1

1

RiT ABOU
En

I

Vss

FIGURE 3 - LEADING AND TRAILING ZERO SUPPRESSION
WITH PWM INTENSITY BLANKING AND NO LAMP TEST
N3

N4

N2

•

N1

N·1

N·2

N·3

Voo

-

ABI

nking

r

ReO r - RBi

FiBo

~

RBi

RiiO

LRBI

RBI

Rai5

RiO

l

RBI

RiiO

En

En

En

En

En

En

1

1

1

1

1

1

Rei

RiOU
En

I

lr;
FIGURE 4 - ZERO SUPPRESSION WITH LAMP TEST
AND INTENSITY BLANKING
N3

N4

Rifi

RiO I-- RBi
En

L-i.
LempTe.

RiO

N2

-

RBI

RiiO

N1

r-Rii RiO

•

N·2

N·1

RBi RiO

l

RBI

RiO

En

En

En

En

En

1

1

1

1

1

»-l 1

Lf-i>o-O
Lt>

4·48

N·3

~RBI

ABOU
En

I

®

MC145000
MC145001

MOTOROLA

SERIAL INPUT
MULTIPLEXED LCD DRIVERS
(MASTER AND SLAVE)

CMOS LSI
(LOW-POWER COMPLEMENTARY MOS)

The MCl45000 (Masted LCD Dnver and the MCl45001 (Slave) LCD
Driver are CMOS devices designed to drive liquid crystal displays in a
mu)tiplexed-by-four configuratIOn. The Master unit generates both
frontplane and backplane waveforms, and IS capable of Independent
operation. The Slave unit generates only frontplane waveforms, and is
synchronized with the backplanes from the Master unit. Several Slave
units may be cascaded from the Master Unit to mcrease the number of
LCD segments driven m the system. The maximum number of frontplanes is dependent upon the capacitive loading on the backplane
drivers and the drive frequency. The deVices use data from a
microprocessor or other senal data and clock source to dnve one LCD
segment per bit.
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Direct Interface to CMOS Microprocessors
Serial Data Port, Externally Clocked
Multiplexing-By-Four
Net dc Drive Component Less Than 50 mV
Master Drives 48 LCD Segments
Slave Provides Frontplane Drive for 44 LCD Segments
Drives Large Segments -Up to one Square Centimeter
Supply Voltage Range=3 V to 6 V
Latch Storage of Input Data
Low Power Dissipation
Logic Input Voltage Can Exceed VDD
Accomodates External Temperature Compensation
See Application Note AN-823A, Section 4
Chip Complexities: MC145000-1723 FETs or 431 Equivalent Gates
MC145001-1495 FETs or 374 Equivalent Gates

SERIAL INPUT
MULTIPLEXED LCD DRIVERS
(MASTER AND SLAVE)

..

24

1

~~

24

1·

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 623

PLASTIC PACKAGE
CASE 700

L SUFFIX

P SUFFIX

CERAMIC PACKAGE
CASE 726

PLASTIC PACKAGE
CASE 707

ORDERING INFORMATION
MC14XXXX

TSuffix Denotes

t=

L Ceramic Package
P Plastic Package

PIN ASSIGNMENTS

FP1
FP2

VDD
OSCout
OSCin

FP3
FP4

Frame-Sync. Out

FP5

Data Out
Data Clock
Data In
BP1

FP6
FP7
FPS
FP9
FP10
FP11

BP2

VSS

FP12

BP3
BP4

FPl
FP2
FP3
FP4
FP5
FP6
FP7
FPS

VDD
OSCin
Frame-Sync. In
Data Out
Data Clock
Data In
FP11
FP10
FPS

VSS
MCl45001
Slave

This device contains circuitry to protect the
inputs agalOst damage due to high static
voltages or electric fields; however, It is adViSed that normal precautions be taken to

avoid application of any voltage higher than
maximum rated voltages to this high Impedance Circuit. For proper operation it is
recommended that Yin and Vout be constrained to the ranges VSS:SVout:sVDD
and VSS:sVin:s15 V

Unused inputs must always be tied to an appropriate logic voltage level.

MC145000
Master

4·49

•

MC145000

MAXIMUM RATINGS IV oItages

ra erencad t 0 V SS

Symbol

Value

Unit

VDD
V in

-0.5 to +6.5

V

Input Voltage, Pin 22 of Master

Vln asc

-0.5 to VDD+0.5

V

DC Input Current, per Pin

lin
TA
. T stg

±10

mA

-40 to +85

'C

-65to +150

'C

Characteristic
DC Supply Voltage
Input Voltage, Data In and Data Clock

Operating Temperature Range
Storage Temperature Range

0.5 to 15

V

ELECTRICAL CHARACTERISTICS IVoltages referenced to VSSI
Characteristic
RM S Voltage Across a Segment
IBPi-FPjl

•

"ON"
Segment
"OFF"
Segment

Average DC Offset Voltage
"0" Level

Input Voltage

"1" Level

Output Drive Current - Backplanes
High-Current State"
VO=2.85 V
VO=1.85V
VO= 1.15 V
VO=0.15 V
VO=5.85 V
VO=3.85 V
VO=2.15 V
VO=0.15 V
Low-Current StateVO=2.85 V
VO=l.85V
VO= 1.15 V
VO=0.15V
VO=5.85 V
VO=3.85 V
VO=2.15 V
VO=0.15V

Output Drive Current - Frontplanes
High-Current State"
VO=2.85 V
VO= 1.85 V
VO= 1.15 V
VO=0.15V
VO=5.85
VO=3.85
VO=2.15
VO=0.15

V
V
V
V

Low-Current StateVO=2.85 V
VO=1.85V
VO= 1.15 V
VO=0.15V
VO=5.85
VO=3.85
VO=2.15
VO=0.15

V
V
V
V

Symbol

VOO
V

VON

3.0
6.0

VOFF

3.0
6.0

Vdc

3.0
6.0

-4O'C
Max

Min

-

-

-

Min

-

25'C
Typ
1.73
3.46
1.00
2.00

Max

-

-

-

-

-

3.0
6.0

-

-

30
50
0.90
1.60

-

1.35
2.70

VIH

3.0
6.0

2.10
4.20

-

2.10
4.20

1.65
3.30

-

IBH

3.0

150
220
160

-

75
110
80
200

190
200
200

-

VIL

-

1000

-

600
500

-

140
2.4
2.2

-

400
500
IBH

IBL

IBL

IFH

IFH

IFL

IFL

6.0

3.0

6.0

3.0

6.0

3.0

6.0

-

250

500
400
250

400

-

70
1.2
1.1
200

190
15
13
850

-

95

-

7.5
65
425

60
140
160
100

-

140

-

360
400

-

100

60
2.8
2.2
100
100
16
13
200

-

-

-

40
70

10
20

30
50
0.90
1.60

300
300
600
500
300

330

-

9
570

60

60

120
100

50

95

-

90
250
240
120

-

30
1.4
1.1
50

40
2.8
2.5
100

-

50
8.0
6.5
100

60

-

-

-

70
160
200
50

-

-

60
2.8
2.5
105
10

85'C
Min Max

-

-

-

10

-

9

-

175

-

-

-

mV
V

35

-

125
250
200
125

-

-

p,A

p,A

-

45

-

3.7
3.2
210

-

20
35
30
25

-

-

p,A

-

-

p,A

p,A

-

-

p,A

-

15
0.7
0.5
25

-

25

-

4.0
3.2
50

V

-

35
0.6
0.5
100

35
90
100
25

V

0.90
1.60

-

40
100

V

30
50

2.10
420

55

Unit

p,A

-

p,A

Input Current

lin

6.0

±O.OOOOl

±0.1

Input Capacitance

C,n

-

-

-

-

5.0

7.5

-

-

pF

Quiescent Current IPer Packagel
V,n=O or VDD, 10ut=0 p,A

IDD

3.0
6.0

-

10
185

-

2.5
50

15
175

-

20
130

p,A

±0.1

-

±1.0

-

p,A

-For a time (tS52.56/osc. freq.) after the backplane or frontplane waveform changes to a new voltage level, the cirCUit IS maintained in the highcurrent state to allow the load capacitances to charge qUickly. Then the CirCUIt IS returned to the low-current state untIl the next voltage level
change occurs.

4·50

MC145000
SWITCHING CHARACTERISTICS ICL ~ 50 pF TA ~ 25'CI
Characteristic

Symbol VOO
30
Icl
6.0
3.0
tr,tf
6.0
30
tsu
6.0
3.0
th
6.0
3.0
tw
6.0

Data Clock Frequency
Rise and Fall Times -

Data clock

Setup Time

Data In to Data Clock
Hold Time
Data In to Data Clock
Pulse Width
Data Clock

Min

-

Typ
125
24

-

-

-

48
16
-5
0

-

65
40

Max
7.5
12.5
125
10

-

-

-

-

-

-

-

Un~

MHz
~s

ns
ns

ns

SWITCHING WAVEFORMS

Data In

Data Clock

VDD -

0VDD -

0-

DEVICE OPERATION

The Slave ynit IFigure 2) consists of the same circuitry as
the Master u~it, with two exceptions: it has no backplane
drive circuitry, and its shift register and latch hold 44 bits.
Eleven frontplane and no backplane' drivers are available
from the Slave unit.

Figure 1 shows a block diagram of the Master unit. The
unit IS composed of two independent circuits: the data input
circuit with ItS associated data clock, and the LCD drive CIrcuit with ItS associated system clock.
Forty-eight bits of data are serially clocked into the shift
register on the falling edges of the external data clock. Data
in the shift register is latched into the 48-bit latch at the beginning of each frame period. lAs shown In Figure 3, the
frame penod, tframe, is the time during which all the LCD
segments are set to the desired "ON" or "OFF" states.)
The binary data present in the latch determines the appropriate waveform signal to be generated by the frontplane
drive circuits, whereas the backplane waveforms are invariant. The frontplane and backplane waveform~, FPn and
BPn, are generated using the system clock Iwhich is the
oscillator divided by 256) and voltages from the V /3
generator circuit Iwhich divides VDD into one-third incrementsl. As shown in Figure 3, the frontplane and
backplane waveforms and the "ON" and "OFF" segment
waveforms have periods equal to tframe and frequencies
equal to the system clock divided by four.
Twelve frontplane and four backplane drivers are available
from the Master unit. The latching of the data at the beginning of each frame period and the carefully balanced voltagegeneration circuitry minimize the generation of a net dc component across any LCD segment.

LCD DRIVER SYSTEM CONFIGURATIONS
Figure 4 shows a basic LCD Driver system configuration,
with one Master and several Slave units. The maximum
number of slave units in a system is dictated by the maximum backplane drive capability of the device and by the
system data update rate. Data is serially shifted first into
the Master unit and then into the following Slave units on
the falling edge of the common data clock. The OSCillator is
common to the Master unit and each of the Slave units. At
the beginning of each frame period, tframe, the Master unit
generates a frame-sync pulse (Figure 3) which is received by
the Slave units. The pulse is to ensure that all Slave unit
frontplane drive circuits are synchronized to the Master
unit's backplane drive circuits.
A Single multiplexed-by-four, 7-segment (plus decimal
point! LCD and possible frontplane and backplane connections are shown in Figure 5. When several such displays are
used in a system, the four backplanes generated by the
Master unit are cominon to all the LCD digits in the system.
The twelve frontplanes of the Master unit are capable of controlling forty-eight LCD segments (6 LCD digits), and the
eleven frontplanes of each Slave unit are capable of controlling forty-four LCD segments 15Y, LCD digitsl.

4·51

•

MC145000
FIGURE 1 - BLOCK DIAGRAM OF THE MCI46000 (MASTER) LCD DRIVER
Data Out

20
Bit 1

Bit 1
FPl
FP2
FP3
FP4

.1iil'
,;:

3"

FP6

en

iii

FP7

.:;

~

ffi

•

FP5

.:;

a:

FPS

~

FP9
FP10
FPll
FP12

Bit 48

19·
Data
Clock

·Pins lS and.19 can
be dtiven to voltages
greater than VDD.

lS·
Data In
System Clock

17
Back- 16
plane
Drive 15

22

23

OSCin OSCout

FIGURE

21
Frame-Bync
Out

Circuit 14

BPl
BP2
BP3
BP4

2 - BLOCK DIAGRAM OF THE MCI46001 (SLAVE) LCD DRIVER

Data Out
15

1
2

I

a:

.;;:

.:;

en

iii

.:;

3"
iii
~

~

14'
Data
Clock
• Pins 13 and 14 can be
driven to voltages
greater than VDD.

13'
Data In

Frame-Sync
Pulse
System Clock

16
Frame-Sync
In

4-52

FPl
FP2

MC145000
FIGURE 3 - VOLTAGE WAVEFORMS

Voo -

System Clock

n n nn nn nn r

o_--.JUUUUUUUU

10sciliator + 2561

vo: ~ J'----~~_l

Frame-8ync Pulse

Voo -

2/3IVOOI-~

BP1

1/3 1VOOI-

0VOO-

2/3IVOOI-~

BP2

•

1/3IV OOI-

0-

Backplane
Waveforms

Voo -

2/3IVOOI-~

BP3

1/3IV OOI-

0Voo-

2/3IVOOI-~

BP4

1/3 1VOOI -

0-

j+-lframe-_,,+14_- tframe--.j
Example One segment ON
Frontplane wave~
form (FPI) for segment

f to be "ON" and
d, e, g to be
"OFF" IFlgure 51

ON segment
voltage waveform

across segment f
IBP1-FP11

t

VOO2/3 1VOOI 1/3 1VOOI -

0-

I

VOO2/3 1VOOI1/3 1VOOI -

Frame RMS Voltage~ VOO/,j3
Frame dc Offset Voltage<50 mV

0-

-1/3 1VOOI-2/3 1VOOI -VOO -

- .......f--ttrame--..t
Example. All segments OFF
Frontplane wave-

form 1FP21 for segments {
a, b, c and h to
be "OFF"
IFlgure 51

OFF segment
voltage waveform

across segment b.
IBP2-FP21

)

Voo_
2/3IVOOI_
1/3IVOOI-

0VOO2(3 1VOOI1/3 1VOOI-

Frame RMS Voltage~VOO/3
Frame dc Offset Voltage< 50 mV

0-1/3 1VOOI-2/3 1VOOI-VOO-

I+- tframe -

....~~144-- tframe---+!

4·53

MC145000
FIGURE 4 -

BASIC SYSTEM CONFIGURATION
Frame Sync.

Aext
(Optionali
Oscillator o------,-...JV\I'vData Clock

System Clock

o-----I----<.-'---+--+------__4--t~__4--..J

OSCout
MCI45000
Master LCD
Driver

Serial Data In

OSCin

Data
Out
Data

MCI45001
Slave LCD
Driver

In

L..._--..-,,--_..J

MCI45001
Slave LCD
Driver

4 Backplanes

•

LCD Array

FIGURE 5 - FAONTPLANE AND BACKPLANE CONNECTIONS TO A MULTIPLEXED-BY-FOUA
7-SEGMENT (PLUS DECIMAL POINT) LCD
FPl

FP2

'''y
'
"
,~U-,~
BP3 e
BP4

I I
d

c

h

•
-

SEGMENT TRUTH TABLE"
FPl

FP2

BPI

I

a

BP2

g

b

BP3
BP4

e

c
d

d

BP3

·Because there is no standard fo r backplane and frontplane connections on

BP4

multiplexed displays, thiS truth table may
be used only lor this example.

Typical Backplane Configuration

Typical Frontplane Configuration

PIN DI:SCRIPTIONS
DATA CLOCK (Master: Pin 19)
(Slave: Pin 14)
The input pin for the external data clock, which controls
the shift registers. This pin can be driven to 15 volts
regardless of the value of VDD.

FRONTPLANE DRIVE OUTPUTS
(Mastar: FP1-FP12; Pins 1-11 and 13)
(Slave: FP1-FPll; Pins 1-8 and 10-12)

The f.rontplane drive waveforms for the LCDs.

DATA OUT (Master: Pin 20)
(Slave: Pin 15)
The serial data output pin.

BACKPLANE DRIVE OUTPUTS
(Mastar: BP1-BP4; Pins 14-17)
The backplane drive waveforms for the LCDs.

FRAME-SYNC OUT (Master: Pin 21)
The output pin for the frame-sync pulse, which is
generated by the Master unit at the beginning of each frame
period, tframe. From Figure I, the 48-bit latch is loaded during the positive Frame-Sync Out pulse. Therefore, if the Data
Clock is active during this load interval, the display will
flicker.

DATA IN (Mastar: Pin 18)
(Slave: Pin 13)

The serial data input pin. Data is clocked into the shift
register on the falling edge of the data clock. A high logic
level will cause the corresponding LCD segment to be turned on, and a low logiC level will cause the segment to be
turned off. This pin can be driven to 15 volts regardless of
the value of VDD, thus permltling optimum display drive
voltage.

FRAME-SYNC IN (Slave: Pin 16)
The input pin for the frame-sync pulse from the Master
unit. The frame-sync pulse synchronizes the Slave frontplane drive waveforms to the Master backplane drive
waveforms.

4-54

MC145000
OSCin (Mastar: Pin 22)
(Slave: Pin 17)
The input pin to the system clock circuit. The oscillator
frequency is either obtained from an external oscillator or
generated in the Master unit by connecting an external
resistor between the OSCin pin and the OSCout pin (Pin 23).
Figure 6 shows the relationship between resistor value and
frequency.

Voo (Master: Pin 24)
(Slave: Pin 18)
The positive supply voltage.
VSS (Master: Pin 12)
(Slave: Pin 9)
The negative supply (or ground) voltage.

OSCout (Master: Pin 23)
The output pin of the system clock circuit. This pin is connected to the OSCin input (Pin 17) of each Slave unit.

FIGURE 6 - TYPICAL OSCILLATOR FREQUENCY
vs EXTERNAL RESISTOR VALUE

•

10M

~VDD= 6V

~

~
~ 100 k

VDD=3V~

.,

E
lB
x

w

10k
1k

10 k

100 k

1M

10M

Oscillator Frequency 1Hz)

APPLICATIONS
The following examples are presented to give the user further insight into the operation and organization of the Master
and Slave LCD Drivers.
An LCD segment is twned either on or off depending
upon the RMS value of the voltage across it. This voltage is
equal to the backplane voltage waveform minus the frontplane voltage waveform. As previously stated, the backplane
waveforms are invariant (see Figure 3). Figure 10 shows one
period of every possible frontplane waveform.
For a detailed explanation of the operation of liquid crystal
materials and multiplexed displays, refer to a brochure entitled "Multiplexed Liquid Crystal Displays," by Gregory A.
Zaker, General Electric Company, Liquid XTAL Displays
Operation, 24500 Highpoint Road, Cleveland, Ohio 44122.

first bit to be entered has been shifted into bit-location one,
the second bit into bit-location two, and so on. Table 1
shows the bit location in the latch that controls the corresponding frontplane-backplane intersection. For example,
the information stored In the 26th-bit location of the
latch controls the LCD segment at the intersection of FP7
and BP3. The voltage waveform across that segment is equal
to IBP3 minus FP71. The same table, but with the column for
FP12 deleted, describes the operation of the Slave unit.
In applications of this type, all the necessary data to completely update the display are serially shifted into the Master
and succeeding Slave units within a frame period. Typically,
a microprocessor is used to accomplish this.
Example 2: Many keyboard-entry applicatjons, such as
calculators, require that the most significant digit be entered
and displayed first. Then as each succeeding digit is entered,
the previously entered digits must shift to the left. It is,
therefore, neither necessary nor desirable to enter a completely new set of data for each display change. Figure 7
shows a representation of a system consisting of one Master
and three Slave units and displaying 20 LCD digits. If each
digit has the frontplane-backplane configuration shown in
Figure 5, the relationship between frontplanes, backplanes,
and LCD segments in the display is shown In Table 2.

Example 1: Many applications (e.g., meters, gasoline
pumps, pinball machines, and automobile dashboard
displays) require that, for each display update, an entirely
new set of data must be shifted into the Master and cascaded Slave units. The correspondence between the frontplanebackplane intersections at the LCD segments and the data
bit locations in the 48-bit latch of the Master (or 44-bit latch
of the Slave) is necessary information to the system
designer. In Figure 1, it is shown that data IS serially shifted
first into the 48th-bit location of the shift register of the
Master. Thus, after 48 data bits have been shifted in, the

4-55

MC145000
through h of digit 1, and the previously entered eight bits
now control segments a through h of digit 2. Thus the two
digits are displayed in the proper locations.
41 Entering the remaining lB digits from the keyboard fills
the 20-dlgit display. Entering an extra digit will cause the first
digit entered to be shifted off the display.

Digits (or alphanumeric charactersl are entered, mostsignificant digit first, by using a keyboard and a decoder external to the MCl45000. Data is entered Into the Master
and cascaded Slave units according to the following format:
11 Initially, all registers and latches must be cleared by
entering 160 zero data bits. This turns off all 160 segments of
the display.
21 Entering the most-significant digit from the keyboard
causes the appropriate eight bits to be serially shifted Into
the Master unit. These eight bits control LCD segments a
through h of digit 1, and cause the desired digit to be
displayed in the least-significant digit location.
31 Entering the second-most-slgnl!icant digit from the
keyboard causes eight more bits to be serially shifted Into the
Master unit. These eight bits now control LCD segments a

•

Example 3: In addition to controlling 7-segment (plus
decimal pointl digital displays, the MCl45000 and MCl45001
may be used to control displays uSing 5 x 7 dot matrices. A
Master and three Slave units can drive lBO LCD segments,
and therefore are capable of controlling five 5 x 7 dot
matrices (175 segments). Two control schemes are
presented in Figures Band 9; one using a Single Master unit,
and one using two Master units.

TABLE t - THE BIT LOCATIONS, IN THE LATCH, THAT CONTROL THE
LCD SEGMENTS LOCATED AT EACH FRONTPLANE-BACKPLANE INTERSECTION
FRONTPLANES

FPl

FP2

FP3

FP4

FP5

FP6

FP7

FP8

FP9

FP10

FPll

FP12

:5...

BPI

4

12

24

28

3

11

16
15

20

BP2

8
7

19

27

36
35

BP3
BP4

2
1

6
5

10

14

30

13

18
17

26

9

25

29

34
33

40
39
38
37

44
43

CD

23
22
21

32
31

48
47
48
45

II)

w

z

"u-----i......
l ......t-e-__________....,~___t--~.-t............-+_....,II.-t............_~
FP12 : FP10

BP3~~I......~~--~~I~~~~~~~~......~~~~I~~~~~~I~~~~

....,_~~~r=~I!j~~t--;~~~:!~~~:. . .~-;~~~~;~;~~_~~
~
~
~
I
.~
......~It-f-' T'S-.l I
/'~.I I
/. "'S..I
/.~T
:r-s..
.e-iII~f
. .~~/ I'S..1
/.
~
/.:I"S..I
liT
ITT
,T'I
ITT
,TT ,I
:
:
I
I
!::
:
i':
:
I
'
:
I
i I I
I
FP7 I FP5
I
FP9 I FP7
I 'FPll: FP9 I FP2 " FP,,:
FP4 ,I FP2
I

BP4---41.....

F~4

FP6

FPB

FP6

FP10

FPS

FPl

FP'1O

FP3

FPl

FIGURE 9 - EXAMPLE DF A 5x7 DOT MATRIX DISPLAY SYSTEM
CONTROLLED BY TWO MASTER AND TWO SLAVE UNITS
Master A

FPll

FP9

FP6

FP12 ~ FP10 ~ FPS
A,A,A

Slave A

FP4

FPl

FP7 ~ FP5 ~ FP3
AIAIA

FP2 A
A:

FP10

FP7

FP5

FPS ~ FP6 ~ FP4
A,A,A

FP11 tFP9
A,A

I

I

I

I

I

1

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

,

I

I

I

I

I

I

I

I

I

I

I

I

I

I

,

,

I

1

11

I
I,
"
" '
"
II
I" I
I
I ' I"I I
I
II
I" I
I
I ' I"
BP1A--~I~~~~I---~~~~~.---~~~~~---e~~~I~I
Master A

BP2A--~I~~~~~--~~~~~--~~~~~a----e-e~-e~T.
BP3A--~~~~~I----4~~~__~--~~e+~~~----~~~~-e

r..i...i...i...i.

..i............. . . .

T T

"'-M

5

1.5

3

-

-

Channel Separation
V,n + = 10 V, V,n - =0 V)

5-5

-

-

IDD

15

~VI'C

dB

dB

-

-

10H

Phase Margin

00,

1
1
1

VOH = 04V
VOH = 05V
VOH=15V

Slew Rate

IRL =

5
10
15
5
10
15

VOH = VDD - 1 5 V

Untty Gain BandWidth

Supply Current. Per Pair

-

~A

mA

VI~s

MHz
Degrees
dB
rnA

MC14573, MC14574, MC14575
COMPARATOR ELECTRICAL CHARACTERISTICS IISet= 20 ~A, RL = 10 Mil, CL = 50 pF, T A = 25°C, unless otherwise Indlcatedl

V

Min

Typ

Max

Unit

VICR

3
5
10
15

0
0
0
0

-

1.5
3.5
85
135

V

Output Voltage Range
"0" Level

VOL

3
5
10
15

-

0.05
0.05
0.05
0.05

V

-

0
0
0
0

Output Voltage Range
"1" Level

VOH

3
5
10
15

2.95
495
995
1495

3
5
10
15

-

V

Input Offset Voltage
MC14574, MC14575

VIO

3
5
10
15

-

±8
±8
±10
±10



A

Note: VOH Max= VDD

'SET CURRENT versus VDD

1000

In

....

RSot-100 kIl~ ~

RSOI-Coostent Value

..3- 100

'"iE

z

:Ii

!:!

...:Ii

0

c'"
co

RSat-1 Mri§§j

a'"

§§

-

0

t;;

IE

'"

j
1

1

10

12

14

16

-55

-40

85

125

TEMPERATURE I'CI

VOO, SUPPLY VOLTAGE IVOlTS)

LOW FREQUENCY OPEN LOOP VOLTAGE GAIN versus IS et

GAIN-BANDWIDTH PRODUCT versus ISet

357123571235712

235712357123

7 1

15~10 V

~

5

..;;

¢P

~

0

"'"'" ~

0

-

~ I::::,

....... t'
~ 15V
i"'VDD-l o V
5V I

60
50

3

lOI'A

lOOI'A
1501, PROGRAMMING CURRENT

1 rnA

1

~

~~

.......:: ~~
~
100!,A
1 rnA
ISot, PROGRAMMING CURRENT

5-8

5V

MC14573, MC14574, MC14575

COMPARATOR PROPAGATION DELAY versus IS et
I ± 50 mV OVERDRIVE)

SLEW RATE versus ISet

35712357123571

357123571

357

0

-

VOO-15V

0
0
0

V

V
./Vi-"

--

20
0

V

0
2pA

VOO-5 V

iii II

!IIII

I mA

100 pA
ISot. PROGRAMMING CURRENT

ISot • PROGRAMMING CURRENT

OPEN LOOP GAIN versus FREQUENCY

OPEN LOOP GAIN versus FREQUENCY

VOO-5 V

o

I

ISot-20 ~A

I"JI"\"
o

'"

ISot - 200 ~A '\,
0

o

~
~

.

"'''~

;!;

""'' -l'"

0
0

0
100

1k

10 k
FREOUENCY 1Hz)

ISot - 200 ~A

0

"-

'" ,'"

"'''"-

50

to

40

"'''

30

'\,

0

0
10

I

o

O~
o ISot-20 ~

VOO-l0 V

100

100

20

"'''\ 1\

0
10

100 k i M

100

1k

10 k

-20 0
10

100

1k

10 k

~A

1M

10 M

VOO-l0 V

~ ~A

ISot-200 ~A
)sotfO

100 k

OPEN LOOP PHASE DELAY versus FREQUENCY

VOO-S V

-100

~~

FREQUENCY 1Hz)

OPEN LOOP PHASE OELA Y versus FREQUENCY

~~

'" '"\ r\

10

-100

"""~

lOOk
FREQUENCY 1Hz)

1M

IsotfO

100

10M

1k

~A

........
10 k

FREQUENCY 1Hz)

5-9

G0

100 k i M

10 M

MC14573, MC14574, MC14575
SMALL SIGNAL TRANSIENT RESPONSE
VOO = 10 V NON-INVERTING UNITY GAIN
ISet=200 "A, Yin AVERAGE=5 V

LARGE SIGNAL TRANSIENT RESPONSE
VOO= 10 V NON·INVERTING UNITY GAIN
ISet = 200 ,.A, Yin AVERAGE=5 V

1
l

~

f'

II

v

500 ns/DiVISION

500 ns/OIVISION

SMALL SIGNAL TRANSIENT RESPONSE
VOO= 10 V NON-INVERTING UNITY GAIN
ISet=2O "A,Vin AVERAGE = 5 V

•

LARGE SIGNAL TRANSIENT RESPONSE
VOO= 10 V NON-INVERTING UNITY GAIN
IS et=2O "A, Yin AVERAGE = 5 V

(\

/

1/
500 ns/DiVISION

/

1\

V

V'

\.

500 ns/DIVISION

EQUIVALENT INPUT NOISE VOLTAGE (EN) versus FREQUENCY
ZOOO

TYPICAL INPUT LEAKAGE versus TEMPERATURE
VOO= 15 V Vin=7.5 V

1800

1000

1600
1400

~

100

1200

1

~ 1000

i
i

800

0

ISat-ZOO "A

60 0

1

40 0
20 0
10

lraW

100

lk

10k

.1

100 k

FREQUENCY (Hz)

-20

20

40

60

TEMPERATURE lOCI

5-10

80

100

MC14573, MC14574, MC14575
COMPARATOR PROPAGATION DELAY versus OVERDRIVE'
VDD = 10 V. tPLH and tpHL

100

=- r-'

10

• A 10 mV overdrive is a signal on one input
ISet-20 ~A

"'- I'..
1

--

of a comparator that ranges from 10 mV
less than the other input to 10 mV more
than the other input.

ISET-200

~A

O. 1

o

10

20

30

40

50

60

70

80

90

100

OVERDRIVE ImVI
OPERATIONAL AMPLIFIER SCHEMATIC
10th CIRCUIT

ISet Circuit

To gates of 01 and 02 on

~ther half of pair

~02

Nan·lnvertlng Input I + )~fi.'H---+-+~
Invertlng Input I - ) ~ >-<~--O-+-<

hJ:-c
O"~,
11: 11 jj7
1

Vss
COMPARATOR SCHEMATIC
10th CIRCUIT

012
ISet Circuit..+jB-+-....
To gates of 01 and 02 on other half of pair

r-----'
IVDD

-0-

VDD 1

I
I
= +-+--"""'-~
I Input
I Protection
L

I

,~e~~k .y §"SJ

5-11

•

•

5-12

CMOS/NMOS PLLs/Frequency Synthesizers

6·1
- _ . . . . . ._ . _ - -

II

CMOS/NMOS PLLS/FREQUENCY SYNTHESIZERS
Device
Function

Number
MC6195*
MC6196*
MC14046B
MC1456BB
MC145106t

Frequency Synthesizer TV Tunmg System
Frequency Synthesizer TV Tuning System

Phase-Locked Loop
Phase Comparator and Programmable Counters
PLL Frequency Synthesizer

MCl45145-1# 4-Blt Data Bus Input PLL Frequency Synthesizer
4-81t Data Bus Input PLL Frequency Synthesizer
MC145146-1
Parallel Input PLL Frequency Synthesizer
MC145151-1
Parallel Input PLL Frequency Synthesizer
MC145152-1
Senal Input PLL Frequency Synthesizer
MC145155-1
MCl45156-1
MC145157-1
MC145158-1
MC145159-1

Senal Input PLL Frequency Synthesizer
Senal Input PLL Frequency Synthesizer

Senal Input PLL Frequency Synthesizer
Senal Input PLL Frequency SynthesIZer with
Analog Phase Detector

*Closest equivalent for MC6190 through MC6194, which are
being phased out and are not recommended for new designs
tClosest equivalent for MC145104, MC145107, MC145109,
MC145112, and MC145143, which are being phased out and are
not recommended for new designs

UClosest equivalent for MCl45144, which
IS not recommended for new designs

Divider Programming
Format

I

Prescale Modulus

Senal
[Compatible with the
Serial Penpheral
Interface ISPII on
CMOS MCUsJ

Single

Parallel

Single

Dual

Single
Dual

2 Control Lines

..-

being phased out and

Double-Ended
Phase Detector
Output

.....-

..(Analog Detector
Outpull

Dual
4-Blt Bus

Single-Ended
3-State
Phase Detector
Output

IS

Single

..-

..-

.-

..-

..-

....-

Number of
Divider Stages
: R :A : N

* Mask-programmable to one fIxed value

6-2

Number
of Pins

14
14

MCl45155-1
MCl45157-1

18
16

10
10

MC145156-1
MCl45158-1
MCl45159-1

20
16
20

9
14

MCl45106
MCl45151-1

18
28

6
8*

10
4

MCl45152-1
MCl4568B

28
16

14

MCl45145-1

18

7

10

MCl45146-1

20

MC6195
MC6196

20
20

MCl4046B

16

12*
14
12*
14
14

7
7
7

11*
12*
12*
12
12
12*
12*

* LImIted number of selectable values

Device
Number

10

12*
12*

®

MC6190 MC6192
MC6191 MC6193
MC6194

MOTOROI.A

MOS

FREQUENCY SYNTHESIZER TV TUNING SYSTEM

IN-CHANNEL, SILICON-GATE,
DEPLETION LOADI

This series of phase locked loop subsystems IS constructed in
NMOS Silicon gate technology and are primarily Intended for TV and
CATV tuning applications. These products make It possible to receive
all VHF and UHF TV frequencies.
•
•
•
•
•
•
•
•
•
•

FREQUENCY SYNTHESIZER
TV TUNING SYSTEM

Single 5 V Supply
Low External Parts Count
Keyboard Interface Uses Low Cost 4 x 4 Keyboard
Remote Control Capability
Manual Channel Selection
Scan Up/ Scan Down
Auto Programming of all Active Channels
Automatic Switching to AFT Mode Option
Channel Information Output Interfaces to Leds
On Chip Reference Oscillator Uses External Crystal

L SUFFIX
CERAMIC PACKAGE
CASE 695

c, 10 kllJ
(VCO m = 5.00 V, 2.50 V, Rl ;, 400 k!1J
(VeO,n = 7.50 V, 5.00 V, R 1 ;, 1000 kHi

0.35
0.7
1.0

0.70
1.4
1.9

MHz

%/oC

0

0.12
0.04
0.015

%
5.0
10
15
50

%

R,n

5 to 15
15

150

50

1500

M!1

-

5.0
10
15

-

-

1.65
1.65
1.65

2.2
2.2
2.2

2.5
2.5
2.5

5.0
10
15

-

-

0.1
0.6
0.8

-

-

Output Duty Cycle

Input ReSistance -- VCO m

10

SOURCE·FOLLOWER

Offset Voltage
(VCOin m,nus SF out , RSF

> 500 k!!l
-

Linearity

(VCO m = 2 50 V, 030 V, RSF > 50 kllJ
(VCO m = 5.00 V , 2.50 V, RSF > 50 k!1J
(VeO m = 7.50 V, 5.00 V, RSF > 50 kllJ

%

ZENER DIODE

Zener Voltage liz =- 50.uA)
DynamiC ReSistance {lz

V

= 1 rnA)

·The formula given is for the typical characteristics only.

6-15

-

-

-

•

MC14046B
FIGURE 1 - PHASE COMPARATORS STATE OIAGRAMS
PHASE COMPARATOR 1
Input State

o

PC'out

PHASE COMPARATOR 2
Input State

LD

Output Disconnected

o

o

(Lock Detect)

•

3-State

o

PC20ut

Refer to Waveforms in Figure 3.

FIGURE 2 - DESIGN INFORMATION
Using P..... Comparotor 1

Chlract.istic
No signal on input PCAin.

veo in PLL system adjusts to center frequency

P..... angle between PCAin and PCB in'

goO at center frequency (fO). approaching 00
and 1800 at ends of lock range (2fLI.

veo

(10).

Locks on harmonics of center frequency.
Signa' input noise rejection.

Using Ph. . Comparator 2
in PLL system adjusts to minimum fre·

quency ('min).

Always

00 in lock (positive

Ves

No

High

Low

rising edges).

Lotk frequency range (2fL)'

The frequency range of the input signal on which the loop will stay locked if it was
initially in lock. 2fL· full veo frequency range· f max - 'min.

Cepture frequency range (2fCI.

The frequency range of the input signal on which the loop will lock if it was initially
out of lock.

Depencls on low-pass filter characteristics

fe' 'L

(_ Figure 3). fC" fL
Center frequency (fO)'

The frequency of VCOout. when VCOin

= 112 Vee

VCO output frequency (f).
Note: T..... equltlonl ~ra intended
to be I dellgn guide. Since calcullted
component Values may be in error
by _ much _ a factor of 4. leborotory experimentation may be r.
qulred for fixed dellgnl. Pert to pert
frequancy variation wilh identical
_Ive components il I - lhln

.2O'lI..

fmi" ..

1
R2(Cl+ 32 pF)

fmax ...

1
fmin
Rl(Cl +32 pF) +

Where: 10K"Rl" 1M

10K"R2" 1M
l00pF "Cl " .01 "F

6-16

(VCO input

= Vss)

(VCO input· VDDI

MC14046B
FIGURE 3 - GENERAL PHASE-LOCKED LOOP CONNECTIONS AND WAVEFORMS

SF out

PCA m
@ Frequency

VCO out

f'

@ Frequency Nf'

= f

-=

rEx"t;r-;;-al l
+N
L_C~~~..J

Typical Low-Pass Filters
Typicallv:
I.)

R3

Ib)

Input~Output

C2

X

R3

Input~Output

2Ic~~j 2 niL'

-

11'

1~~

R3 C2

*C2

Note:

l!of

= f max

- fmin

Sometimes R3 is split into two series resistors each R3";- 2. A capacitor Cc is then placed from the midpoint to ground. The value for
Cc should be such that the corner frequency of this network does not significantly affect Wn. In Figure B. the ratio of R3 to A4 sets
the damping, A4 3!; (0.1 HR3J for optimum results.
LOW·PASS FILTER

Definitions:

N = Total division ratio in feedback loop

Filter A

K¢ = VOo!1Tfor Phase Comparator 1
K¢ = VOO/4 1r for Phase Comparator 2

K

_ 211" !VCO
VCO - VDD-2 V

for a tYPical design wn

211 !r

~.......,.-o-

(at phase detector input)

t "0.707

Filt. B

wn:

iK,pKVCO
NR3C2

t:

NWn
2Kq,KVCO

Fls): __1__
R3C2S+1

~ Kq,KVCO
wn: NC2IR3+R4)

t: O_S wn lR 3 C2 +
Fls) :

N
Kq,KVCO 1

R3 C2 S+ 1
SIR3C2+R4C2)+1

Waveforms
Phase Comparator 2

Phase Comparator 1

peAin

~

VOO

PCAin

VSS

PCB m

~
~

.

.

I

VOH

PCBin

VOL

PCl out

~

VOH

ill

VOL

-VOH
VCO;n~

PC2 0ut

VSS

I
L

~
I
L

:I
---If
U
H
---.J .

-VOL

I:

VOH
VOL

I

VOH

U·

U
'i,""====
l

VOO

~L

:

VOH

,-

VOL

, -_ _ _ _ _ _' - _ _ _ _
--_VOH
VCOin - - - - - '
"

-Val

Note: for further information, see:
III F. Gardner, "Phase-Lock Techniques", John Wiley and Son, New York,1966.
(2) G. S. Moschytz, "Miniature RC Filters Using Phase-Locked Loop", BSTJ, MaY,196S.
(3) Garth Nash, "Phase-Lock Loop Design Fundamentals", AN-636, Motorola Inc.

6-17

•

®

MC145688

MOTOROLA

CMOS MS.

PHASE COMPARATOR AND
PROGRAMMABLE COUNTERS

(LOW·POWER COMPLEMENTARY MOSI

The MC14568B consists of a phase comparator, a dlvlde-by-4, 16,64
or 100 counter and a programmable dlvlde-by-N 4-blt binary counter (all
positive-edge trlggeredl constructed with MOS P-channel and
N-channel enhancement mode devices Icomplementary MOSI In a
monolithiC structure.
The MC14568B has been designed for use In conjunction with a programmable dlvlde-by-N counter for frequency synthesIZers and phaselocked loop applications reqUiring low power dissipation and! or high

PHASE COMPARATOR
AND PROGRAMMABLE
COUNTERS

nOise Immunity

This device can be used with both counters cascaded and the output
of the second counter connected to the phase comparator (CTL hlghl,
or used Independently of the programmable dlvide-by-N counter, for
example cascaded with a MC14569B, MC14522B or MC14526B (CTL
lowl
• QUiescent Current = 5.0 nA typ!pkg @ 5 V
• Supply Voltage Range= 3.0 to 18 V
• Capable of Driving Two Low-Power TTL Loads, One Low-Power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range.
• Chip Complexity: 549 FETs or 137 EqUivalent Gates

•

MAXIMUM RATINGS

L SUFFIX

P SUFFIX

CERAMIC PACKAGE

PLASTIC PACKAGE

CASE 620

CASE 648

., ., , 1

ORDERING INFORMATION
l;S uff "

(Voltages relerenced to VSSI

Rating
DC Supply Voltage
Input Voltage, All Inputs

Symbol

Value

Unit

VDD

-05to+18

V

V ,n

-05 to VDD + 0.5

V

DC Input Current, per Pin

lin

±10

mA

Operating Temperature Range - AL DeVice
CLlCP DeVice

TA

-55 to +125
-40 to +85

°c

Storage Temperature Range

T stg

-65 to +150

°c

Limited Operating
Temperature Range

TRUTH TABLE
F
Pin 10

Division Ratio
of Counter 01

G
Pin 11

4

0
1
0

16
64
100

CTL LOW

CTL HIGH

PC out

~-+~--~--------~~-+~---o11 G

PC'~LD
P.C.

CTL 15cr__+-~~.L__________~P---t-~---()10f

"0"

Plastic Package
Extended Operating

The divide-by-zero state on the programmable
djvjde-by-N 4-bit binary counter, 02, is illegal.

~~~~~-1----:_~{)12LD

C1

P
A

Temperature Range

r-----------,
I
I
PC tn 140--1-----1

Ceramic Package

C

o
o

BLOCK DIAGRAM

Denote,

L

C1

3o----!--4--f-----;;-s;;--,

01

PE

"0"0--1
5
6
7
DP2 DP1

6-18

02

b2

MC14568B

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSI
Characteristic
Output Voltage
Vm VOO or 0

"0" Level

Symbol

Voo
Vdc

VOL

50

Tlow
Min
~

_.

to
15

Vm

a or VDO

"'" Level

"a"

Input Voltage#t
(VO 4.5 or 0.5 Vdcl
IVo 9.0 or 1.0 Vdcl
IVo 135 or 1.5 Vdcl

Level

VOH

IVOl - 0.4 Vdcl
(VOL = 0.5 Vdcl
IVOl = 1.5 Vdcl
(VOH
(VOH
IVOH
(VOH

2 5 Vdcl
= 4.6 Vdcl
= 9 5 Vdcl
= 13.5 Vdcl
=

(VOL = 0.4 Vdcl
IVOl = 0.5 Vdcl
(VOL - 1 5 Vdcl

2.25
4.50
6.75

3.5
7.0
t1.0

2.75
5.50
8.25

-

~1.0

-1.7
-0.36
-0.9
-3.5

-

1.5
3.0

-

4.0

.-

~

-

-

Max

Unit

005
0.05
0.05

Vdc

-

Vdc

-

4.95
9.95
14.95

-

1.5

-

1.5

3.0
4.0

-

3.0

-

3.5
7.0
11.0

-

-0.7
-0.14
-0.35

-

-

-1.1

-

0.36

-

-

-0.6
-0.12
-0.3
-1.0

~

-

Vdc

~

4.0

3.5
7.0
1 t.O

-

IOl

-

-1.2
~0.25

-0.62
-18

-0.2
-0.5
-1.5

5.0
10
15

0.64
1.6
4.2

-

0.51
1.3

-

304

5.0
50
10
15

0
-0.2
~O 5
-1.4

-0.8
-0.16
-0.4
-1.2

5.0
10
15

0.52

-

-

0.88
2.25
8.8

Input Current (CLlCP DeVice)

I,n

15

Cm

-

'DO

100

-

-

0.9
204·

mAde

mAde

IOH

IOl

Vdc

mAde

5.0
50
10
t5

15

Current~ ~'r

50
10
15

~

5.0

I,n

Total Supply

0.05
0.05
0.05

-

Input Current !AL DeVice)

QUiescent Current (AL DeVice)
IPer Package I Vm=O or VOO.
10ut=0 ~A
QUiescent Current (CLlCP DeVice)
(Per Packagel V,n = 0 or VOO.
10ut=0 ~A

-

0
0
0

IOH

Source

Inpul Capacitance

-

Min

VIH

Source

Sink

005
0.05
0.05

4.95
995
14.95

10
t5

Output DrIve Current /CLlCP DeVice)

Max

-

5.0

Sink

Typ

Vil

(VO 0.5 or 4 5 Vdcl
(VO 1.0 or 9 0 Vdcl
(VO - 1 5 or 13.5 Vdcl
25 Vdcl
4.6 Vdcl
9 5 Vdcl
13.5 Vdcl

Thi h*

Min

495
995
1495

to

Output Drive Current (AL DeVice)

25°C

Max

50
10
15

15
"'" Level

IVOH·
(VOH
(VOH ~
IVOH -

~

.

50
10
15
50
10
15

~1

1.3
36

-

±O 00001

±O 1

-

-

±O 00001

±O3

~

50

7.5

50
10
20

-

0.005
0.010
0.Q15

50
10
20

-

20
40
80

-

0.005
0.010
0.Q15

20
40
80

-

±O3

-

~

~

-

0.36
0.9
24

-

-

-0.9
-3.5
0.88
2.25
8.8

±O 1

~

0044

-1.7
~0.36

1.1
3.0
~

~

~

~

±

~

10

±, .0

~

mAde

,uAdc
,uAdc

-

pF

150

}.lAde

300
600
150
300
600

,uAdc

IT

50
10
15

ITl

15

-

±O.1

-

±0.00001

±0.1

-

±3.0

ItAdc

ITL

15

-

± 1.0

-

±0.00001

± 1.0

-

±7.5

ItAdc

(DynamiC plus QUIescent.

Per Package)
50 pF on all outputs, all

,uAdc

IT = (0.2 ~A/kHzl f + 100
IT = IDA ItA/kHzl f + 100
IT = (0.9 itA/kHz) f + IDD

ICl

buffers sWltchmg)

Three-State Leakage Current, Pins 1,13
(AL Devicel

Three·State Leakage Current, Pins 1,13
(CL/CP Devices)

-Tlow -55°C for AL DeVice, -40 0 C for CLlCP DeVice
Thigh"" +125 0 C for AL DeVice, +85 0 C for CLlCP DeVice
~Noise Immunity spel,;lfled for worst-case Input combination
NOise Margin for both "1" and "0" level - 1.0 Vdc min @ VDD ::- 5.0 Vdc

20Vdcmln@VDO - 10Vdc
25 Vdc mln@ VOO
15 Vdc
tTo calculate total supply current at loads other than 50 pF
ITICll ITI50 pFI + 1 x 10- 3 ICL -501 VDDf
where IT IS In 1J.A !per package), CL 10 pF, VDO 10 Vdc, and f 10 kHz IS Input frequency

PIN ASSIGNMENT
Ql/C2
PE
'0'

'.

- -The formulas given are for the tyPical characterIStics only at 25°C.

Dp3 4

tPin 15 is connected to VSS or VOO for input voltage test.

Dp2

5

Dpl

6

VOO
CTl
PC,n
PC out

LD
11

G

DpO
VSS

. 6-19

8

Cl

•

MC14568B

SWITCHING CHARACTERISTICS ICL=50 pF TA=25'CI
Characteristtc

Symbol

VDD
V

Min

Typ

Max

Unit

-

180
90
65

360
180
130

ns

100
50
40

200
100
80

ns

250
120
90

ns

-

125
60
45

15
15
15

-

-

,?utput Rise Time

tTLH

59
10
15

Output Fall Time

tTHL

50
10
15

Minimum Pulse Width, Cl, Ql/C2, or PC ,n Inpul

tWH

5.0
10
15

-

tTLH,
tTHL

50
10
15

R,n

5.0 to 15

-

-

50 to 15

Turn-Off Delay Time,
PCout and LD Outputs

tpHL

5.0
10
15

Turn-On Delay Time,
PCout and LD Outputs

tpHL

MaXimum Clock Rise and Fall Time,
Cl, Ql/C2, or PC ,n Input

-

~s

PHASE COMPARATOR
Inout Resistance
Input Sensitivity, de Coupled

I

106

I

-

I

Mil

See Input Voltage
550
195
120

1100
390
240

ns

50
10
15

-

675
300
190

1350

ns

50
10
15

30
80
10

60
16
22

5.0
10
15

1.0
3.0
50

25
6.3
9.7

-

50
10
15

-

450
190
130

900

50
10
15

-

720
300
200

1440
800
400

600
380

DIVIDE-BY-4 16 64 OR 100 COUNTER (Dl)
Maximum Clock Pulse Frequency
DIvision Ratio=4, 64'or 100

•

DIVISion

MHz

fel

Ratio = 16

. Propagation Delay Time, Q1/C2 Output
DIvision Ratlo=4, 64 or 100

tpLH,
tpHL

DIVIsion RatIO = 16

ns

380
280

PROGRAMMABLE DIVIDE-BY-N 4-BIT COUNTER (D2)
Maximum Clock Pulse Frequency
(Figure 3al

fel

5.0
10
15

12
30
40

18
85
12

-

Turn-On Delay Time, "0" Output
IF,gure 3al

tPLH

50
10
15

-

450
190
130

900
380
260

ns

Turn-Off Delay Time, "0" Output
IFlgure 3al

tPHL

225
85
80

450
170
150

ns

75
40
30

250
100
75

ns

M,nimum Preset Enable Pulse Width

tWHIPEI

5.0
10
15

-

5.0

-

10

-

15

6·20

-

MHz

-

MC14568B

SWITCHING TIME TEST CIRCUITS AND WAVEFORMS
FIGURE 1 - PHASE COMPARATOR

~
2

A lags B. PC out IS

"O"out REF

PC m
PGl

lOW.

A leads

e,

PC out

I"

high.

o
G)~-----------+~

LD

PC out

FIGURE 2 - COUNTER D1

2on~tW(Cll
c,

fu,

'!flaK

tPHL
QlIC2

•

FIGURE 3 - COUNTER D2

a.

b.

'----<~--_i CL.

"0"

_~

_ _ _ _ _ _ _ _.-J

-N is the yalue programmed on the Op Inputs.

6-21

MC145688

LOGIC DIAGRAM

~--------------------------~o13PCout

~------------------~LD

C1

•

9

Counter 01

o'--t----~

10o---r-~----~--t-~

G

11

o---t-----------+-1

t--------,~--1

"0"

30--------<.

Counter D2

6-22

allC2

MC14568B

Typical Maximum Frequency Divider 01
Division ratio: 16 (CL = 50 pF)

Typical Maximum Frequency Divider 01
Division ratios: 4,64 or 100 (CL =50 pF)
B

2

&'"

"-

4

~

2

"-

&

'"'"

-......

B

~

r-- r--

~

20

Br--.

~

10

-... ~'I~V

--- '---- r-- ---+I

vL~L

""-.. VOO' I~ V

I--

...........

-40

...............

+20

-20

+40

+&0

+80

f-100

T. TEMPERATURE lOCI

"-....

2

I'--.. r--..

VOO' 10 V

'"

4

-

I'--....

VOO' 10 V

..................

•

0

B

&1--

--------

Typical Maximum Frequency Divider 02
Division ratio: 2 (CL = 50 pF)
&
vOO' ~ v

i----:.

~i'4

r--. r-

2

3b .....

o
-40

-20

'20
T. TEMPERATURE ,0CI

'80
2

--

r--- r----

o
-20

+20

T. TEMPERATURE lOCI

6-23

v

.1
t---- t---- ~IOV

vL.sv

1

-40

VOO' I~

r---+:-

+&0

+80

+100

MC14568B

OPERATING CHARACTERISTICS
If the input signals have different frequencies, the out·
The MC 145688 contains a phase comparator, a fixed
put signal will be high when signal B has a lower frequency
divider (7 4, 7 16, 7 64, 7 100) and a programmable
than signal A, and low otherwise.
divide-by-N 4-bit counter.
Under the same conditions of frequency difference, the
PHASE COMPARATOR
output will vary between VOH (or VOL) and some intermediate value until the frequencies of both signals are
The phase comparator is a positive edge controlled
equal and their phase difference equal to zero, i.e. until
logic circuit. It essentially consisis of four flip-flops and
locked condition is obtained.
an output pair of MaS transistors. Only one of its inputs
Capture and lock range will be determined bV the VCO
(PCin, pin 14) is accessible externally. The second is
frequency range. The comparator is provided with a lock
connected to the output of one of the two counters 01
indicator output, whiCh will stay at logic 1 in locked
or 02 (see block diagram).
conditions.
Duty cycles of both input signals (at A and B) need not
The state diagram (Figure 5) depicts the internal state
be taken into consideration since the comparator responds
transitions. It assumes that onlv one transition on either
to leading edges only.
signal occurs at any time. It shows that a change of the
If both input signals have identical frequencies but
output state is alwavs associated with a positive transition
different phases, with signal A (pin 14) leading signal 8
of either signal. For a negative transition, the output does
(Ref.). the comparator output will be high for the time
not change state. A positive transition may not cause the
equal to the phase difference.
output to change; this happens when the signals have
If signal A lags signal B, the output will be low for the
different frequencies.
same time. In between, the output will be in a three-state
condition and the voltage on the capacitor of an RC filter
DIVIDE BY 4,16,64 OR 100 COUNTER (01)
normally connected at this point will have some intermediate value (see Figure 4). When used in a phase locked
loop. this value will adjust the Voltage Controlled Oscillator frequency by reducing the phase difference between
the reference signal and the divided VCO frequency to

This counter is able to work at an input frequency of
5 MHz for a VDD value of 10 volts ovet the standard
temperature range when dividing bV 4,64 and 100. Programming is accomplished bV use of inputs F and G (pins
10 and 11) according to the truth table shown. Connect·
ing the Control input (CTL, pin 15) to VDD allows cascading this counter with the' programmable divide-bv·N
counter provided in the same package. Independent
operation is obtained when the Control input is can·
nected to V55.
The different division ratios have been chosen to gen·
erate the reference frequences corresponding to the channel spacings normallv required in frequenc'v synthesizer
applications. For example, with the division ratio 100
and a 5 MHz crystal stabilized source a reference fre·
quency of 50 kHz is supplied to the comparator. The
lower division ratios permit operation with low frequency
crystals.

zero.

•

FIGURE 4 - PHASE COMPARATOR WAVEFORMS

n

A

(PCln)~

I

n-Voo

L...-.....:-t

L - - Vss

:~1/f--"'11

!

rr---r-:::

. -----Hrr~ :
L----i i
1I
VOH
LD
U
U_____ VOL

B IRe' I

II

PC out

-Y

II

U'J-::===:
-

VOH
VOL.

Input State

FIGURE 5 - PHASE COMPARATOR
STATE DIAGRAM

A

B

PC out

o

LD

o

(Lock Detect)

6-24

3·5tat.
Output Disconnected

o

MC14568B

If used in cascade with the programmable divide-by-N
counter, practically all usual reference frequencies, or
channel spacings of 25, 20, 12_5, 10,6_25 kHz, etc. are
easily achievable.

DPJ (pins 7 ... 4). The Preset Enable input enables the
parallel preset inputs DPO ... DP3. The "0" output must
be externally connected to the PE input for single stage
applications. Since there is not a cascade feedback input,
this counter, when cascaded, must be used as the most
significant digit. Because of this, it can be cascaded with
binary counters as well as with BCD counters (MC14569B,
MC14522B, MC14526B).

PROGRAMMABLE DIVIDE-BV-N
4-BIT COUNTER (02)

This counter is programmable by using inputs DPo ...

TVPICAL APPLICATIONS
FIGURE 6 - CASCADING MC14568B AND MC14522B OR MC14526B WITH MC14569B

allC2
MCl4568B

0PO _ _ _ Op3

MSD

LSD

FIGURE 7 - FREOUENCY SYNTHESIZER WITH MC14568B and MC14569B USING A MIXER
(Channel Spacing 10 kHz I

PCin
PCout
140 kHz)
o--+---1Cl
MCI456BB G
o--+-~CTI
F
"0"
allC2
Vss

1144-146 MHz)

PE
VOO
OPO---OP3

MC14011

CF

a

MC14569B
L - - -...---------tP:E!ou!!.t~

C .....---I
-....J

NOTE:
1. 10 kHz Channel Spacing
2. Expandable to 166 Channels
(Expanded frequency range

shown In par.nth .... )

15.36 MHz

TRX

t---------i...

Voo

o
RCV
10.695 MHz

II

To Transmitter
26.965-27.255
(28.605) MHz

®

MC145104
MC145107
MC145109
MC145112

MOTOROI.A

I?LL FREQUENCY SYNTHESIZERS
The MC145104, MC145107, MC145109, and MC145112 are phase
locked loop !PLLI frequency synthesizer parts constructed with CMOS
devices on a single monolithic structure. These -synthesizers find applications In such areas as CB and FM transceivers. The device contains
an osclliator,/amplifier, a 210 or 211 divider chain for the OSCillator
signal, a programmable divider chain for the input signal and a phase
detector. The M.C145104/5n2 have Circuitry for a 10.24 MHz OSCillator
or may operate With an external signal. The MC145107/5109 require the
external reference signal. Several of the circuits prOVide a 5.12 MHz output Signal, which can be used for frequency tripling.' A 29
(MC145109/5112) or 28 (MCl45104/5107) programmable diVider diVides
the input signal frequency for channel selection. The Inputs to the programmable divlC;:!er are standard ground-to-supply binary signals. Pulldown resistors on these inputs normally set these inputs to ground
enabling these programmable Inputs to be controlled from a mechanical
switch or electronic circuitry.
The phase detector may control a VCO and Yields a high level-Signal
when input frequency IS low, and a low level Signal when Input frequency IS high An out of lock Signal prOVided from the on-Chip lock detecto~\~
with a "0" level for the out of lOCK condition
.., . . .

•

•

Single Power Supply

•

Wide Supply Range: 4.5 to 12 V

CMOS MSI
(LOW-POWER COMPLEMENTARY MOS)

PLL
FREQUENCY SYNTHESIZERS

V

P SUFFIX
PLASTIC PACKAGE
CASE 648

•
•
•
•
•
•
P SUFFIX
PLASTIC PACKAGE
CASE 707

NOT RECOMMENDED FOR NEW DESIGNS
PRODUCT BEING PHASED OUT

Closest equivalent is the MC145106

ThiS device contains circuitry to protect
the "Inputs against damage due to high static
voltages or electriC fields; however, It is
advised that normal precautions be taken
to avOid application of any voltage higher
than maximum rated voltages to thiS high
Impedance CirCUit For proper operatiOn It
IS recommended that
V In and V ut be
constramed to the range VSS ~ ?V in or

Vout

:s;;;;

V OD '

®

MC145106

MOTOROLA

PLL FREQUENCY SYNTHESIZER
The MC145106 IS a phase locked loop IPLLI frequency synthesizer
constructed In CMOS on a single monolithic structure. This synthesizer
finds applications In such areas as CB and FM transceivers. The device
contains an oscillator/amplifier, a 2 10 or 211 divider chain for the
oscillator signal, a programmable divider chain for the Input signal and a
phase detector. The MC145106 has circuitry for a 10.24 MHz oscillator
or may operate with an external signal. The circUit provides a 5.12 MHz
output signal, which can be used for frequency tripling. A 29 programmable divider divides the Input signal frequency for channel selection.
The Inputs to the programmable divider are standard ground-to-supply
binary signals. Pull-down resistors on these Inputs normally set these Inputs to ground enabling these programmable Inputs to be controlled
from a mechanical sWitch or electronic CIrCUitry.
The phase detector may control a VCO and Yields a high level signal
when Input frequency IS low, and a low level signal when Input frequency IS high An out of lock signal IS provided from the on-chip lock detector with a "0" level for the out of lock condition
•
•

CMOS MSI
ILOW-POWER COMPLEMENTARY MOS)

PLL
FREQUENCY SYNTHESIZER

Single Power Supply
Wide Supply Range: 4.5 to 12 V

•

ProvIsion for 1024 MHz Crystal Oscillator

•
•
•
•

512 MHz Output
Programmable D,v,s,on Binary Input Selects up to 29
On-Chip Pull Down ReSistors on Programmable D,v,der Inputs
Selectable Reference D,v,der, 2 10 or 211 Ilncludlng-2)

•
•
•

Three-State Phase Detector
Pin-far-Pin Replacement for MM55106, MM55116
Chip Complexity. 880 FETs or 220 EqUivalent Gates

P SUFFIX

BLOCK DIAGRAM

PLASTIC PACKAGE
CASE 707

•
PIN ASSIGNMENT

VDD
.2 out

OSCout

FS

~PVSS
17

fin

Osc 1n
tj;Oet out

OSCout

6

PP2
PP3
13 bP4
12 bP5
11 PP6

9

10 b P7

4

lO
8

FS

tP Detout
LD
P8

PO

P1

P2

P3

P4

P5

P6

P7

P8

VOO P,n 1
VSS Pm 18

6-29

15

14

- 20ut

Phase
Detector

pPO

16p P1

MC145106

MAXIMUM RATII\IGS (Vo.ltages relerenced to VSSI
Symbol
Ratina
DC Supply Voltage
VDD
Input Voltage, All Inputs
Y,n
I
DC Input Current, per PIA
Operating Temperature Range
TA
Storage Temperature Range
Tstg

This devIce contains cIrcuItry to protect the
""puts agamst damage due to high static
voltages or electric fields; however; ,t IS
advIsed that normal precautions be taken to
aVOid application 01 any voltage higher than

Unit
V
V
rnA
'C
'C

Value
-0.5 to + 12
0.5 to V D +0.5
± 10
-40 to +85
65 to + 150

maximum fated voltages to this high Impe-

dance CIrcuIt. For proper operation It IS
recommended that Vin and V out be constrained to the range VSS s (V,n or Vout)
oS VDD.

ELECTRICAL CHARACTERISTICS
IT A = 25'C Unless Otherwise Stated, Voltages Relerenced to VSSI

Characteristic
Power Supply Voltage Range
Supply Current

Input Voltage

Input Current

"0" Level

Symbol

VOO
Vdc

VDD

-

IDD

5.0
10.
·12

-

50
10
12
50'
10
12

-

VIL

"1" I_evel

VIH

"0" Level

1m

IFS, PUll-Up Resistor Source Currentl

(PO to P81

,'.
(FSI

•

"1" Level

5.0
10
12
5.0
10
12

Min
4.5

-

All Types
Typ
Max
.12
10
35
50

mA

.-

V

-

3.5
7.0
84

-

-

-5.0
-15
-20

-20
-50

-50
-150
-200
-03
-0.3
-0.3

-

-

-80

-

-

-

-

5.0
10
12
5.0
10
12

7.5
22.5
30

-

120

0.3
0.3
0.3
75
225
300

(Oscm,lml

"0" Level

5.0
10
12

-2.0
-6.0
-9.0

-6.0
-25
-37

-15
-62
-92

(Oscln,l,nl

"1" Level

50
10
12

20
6.0
90

6.0
25
37

15
62
92

50
10
12

-0.7
-1.1
-15
0.9
1.4
2.0

-1.4
-22
-3.0

-

-

1.0
1.5

0.2
0.3

-

5.0
10
12

-

1.0
0.5

-

-

-

6.0

5.0
10
12

-

-

-

-

1.0
1.0
1.0

4.5
12

0
0

-

40

4.5
12

0.1
01

-

(PO to P8, Pull-down Resistor Smk Currentl

Output Dnve Current

VO=4.5VI
(VO=95VI
(VO= 115 VI

-

30

90

(VO=0.5 VI
(VO=0.5 VI
(VO=05VI
Input Amplitude
(lin @ 4.0 MHzl
(Osc m @10.24 MHzl
Input ReSistance
IOscm,lml

Smk

10L

5.0
10
12

1.8
2..8
40

-

-

C,n

Three State Leakage Current
(of> Detoutl

10Z

Input Frequency
(- 4O'C to + 85'CI

lin

Oscillator Frequency
(- 4O'C to + 85'CI

Osc ln

6·30

Vp-p
Sine
MO

R,n

Input Capacltan<;:e
{Oscm,fml

~A

mA

10H
Source

V

6
20
28

1.5
30
3.6

.

Unit

-

pF
~A

MHz

40
10.24
10.24

MHz

MC145106
TYPICAL CHARACTERISTICS
FIGURE 2 - MAXIMUM OSCILLATOR INPUT
FREQUENCY vorsus SUPPLY VOLTAGE

FIGURE 1 - MAXIMUM DIVIDER INPUT
FREQUENCY versus SUPPLY VOLTAGE

5

15

-

10

~

15

i

+2S0C

~
w

:>

>=

II "
I
/ /J
::%V

+85 0 C

10

~

g 5.0

... ~

:>

o

+25 0 C

5

o

+8SoC

-40°C

0

30

o
o

50

40

fin, MAXIMUM FREUUENCY (MHz)

V

f

0

10

10

I

_40°C

10

10

30

40

50

OSCm, MAXIMUM FREQUENCY (MHzl

TRUTH TABLE
Selection
P8

P7

P6

P5

P4

P3

P2

P1

PO

Divide By N

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
0
0
1

0
0

0
1
0

2 (Note 1)
3 (Note 1)

PIN DESCRIPTIONS
PO - P8 - Programmable divider inputs (binary)
fin - Frequency input to programmable divider (derived
from VCOI
OScin - Oscillator/amplifier Input terminal

2

3
0

0

4

OSCout - Oscillator/amp.lifier output terminal
LD - Lock detector, high when loop;s locked,
pulses low when out of lock.
(/) Detout - Signal for control of external veo, output high
when fin/N is less than the reference frequency; output
low when fin/N is greater than the reference frequency.
Reference frequency is the divided down oscillator Input frequency tYPically 5.0 or 10 kHz.
FS - Reference Oscillator Frequency Division Select. When
using 10.24 MHz Osc frequency, this control selects
10 kHz, a "0" selects 5.0 kHz.
720ut - Reference Osc frequency divided by 2 output; when
using 10.24 MHz Osc frequency, this output is 5.12
MHz for frequency tripling applications.
VDD - POSitive power supply
VSS - Ground

255

0

511

1: Voltage level
0: Voltage level
Note 1:

= VOO

=0 or open Circuit input

The binary setting of 00000000 and 00000001 on
P8 to PO results in a 2 and 3 division which is not
in the 2N_l sequence. When pin is not connected

the logic signal on that pin can be treated as a "0".

6-31

II

MC145106
PLL SYNTHESIZER APPLICATIONS
The MC145106 IS well suited for applications In CB radios
because of the channelized frequency requirements, A
typical 40 channel CB transceiver synthesizer, using a single
crystal reference, is shown in Figure 3 for receiver IF values
of 10,695 MHz and 455 kHz,
In addition to applications in CB radios, the MC145106 can
be used as a synthesizer for several other systems, Various
frequency spectrums can be achieved through the use of
proper offset, prescaling and loop programming techniques,
In general, 300-400 channels can be synthesized using a
single loop, with many additional channels available when
multiple loop apprqaches are employed, Figures 4 and 5 are
examples of some possibilities,
In the aircraft synthesizer of Figure 5, the VHF loop (top)
will provide a 50 kHz, 360 channel system with 10,7 MHz
RIT offset when only the 11,0500 MHz (transmit) and
12,1200 MHz (receive) frequencies are proVided to mixer #1,

When these signals are provided With crystal OSCillators, the
result IS a three crystal, 360 channel, 50 kHz step synthesizer.
When uSing the offset loop (bottom) in Figure 5 to provide
the indicated injection frequencies for mixer #1 (two for
transmit and two for receive) 360 additional channels are
possible, This results In a 720 channel, 25 kHz step synthesizer which requires only two crystals and provides RIT
offset capability, The receive offset value IS determined by
the 11.31 MHz crystal frequency and is 10,7 MHz for the
example,
The VHF marine synthesizer In Figure 4 depicts a single
loop approach for FM transeivers, The VCO operates on frequency dUring transmit and IS offset downward during
receive, The offset corresponds to the receiver IF (10,7 MHz)
for channels having identical receive/transmit frequencies
(simplex), and is (10,7 - 4,6= 6,1) MHz for duplex channels,
Carrier modulation IS introduced in the loop dUring transmit.

FIGURE 3 - SINGLE CRYSTAL CB SYNTHESIZER FEATURING ON-FREQUENCY VCO DURING TRANSMIT

,---+-_LD

•

MC145106

26,965- 27,405
MHz Itransmitl
26,510-26,950

Programmable DIVider

MHz (receive)

Gnd

VDD
Switch

Wafers

Buffer

' -_ _ _ _ _---, 1.365-1.805 MHz Itransmltl
0,91-1,35 MHz Irecelvel

Mixer

10,24 MHz

16,270-16,710
MHz

to Receiver
Receiver 18t
2nd Mixer Local Osc Signal

MC145106
FIGURE 4 -

VHF MARINE TRANSCEIVER SYNTHESIZER

Loop
Filter

Transmit Range
156 025 - 157425 MHz
*157.4

VCO and
Buffer

Receiver l.O Range
145 575 - 152.575 MHz
'1513

Transmit
Modulation
CIrcuit

lDuPlex

0

NOTES'
• Receiver IF= 10.7 MHz
• Low Side Injection

• Duplex Offset = 4.6 MHz
• Step Size = 25 kHz
• Frequencies In MHz unless

noted
• Values In Parentheses are
for a 50kHz Reference
Frequency
• Example Frequencies for
Channel 28 Shown by •
ICan be eliminated by adding
184 to -+- N for Duplex
Channels

6·33

1475#
129.501

•

MC145106
FIGURE 5 - VHF AIRCRAFT

72D CHANNEL TWO CRYSTAL FREOUENCY SYNTHESIZER

TRANSMIT
118.000 - 135.975 MHz
125 kHz Steps)
RECEIVE
128.700-146.675 MHz

VHF Loop
Programming
750 kHz - 2546 kHz
N= 150-509
TRANSMIT
11.0500 MHz
{ 11 0525 MHz
RECEIVE
12.1200 MHz
12.1225 MHz

•

TRANSMIT
10.24 MHz
RECEIVE
11.31 MHz
(Select Frequency to Give
DeSired RIT Dffset)

810 kHz - 812.5 kHz
N=324-325

6-34

®

MC145143

MOTOROLA

PLL FREQUENCY SYNTHESIZER
The MC145143 is a phase locked loop bUilding block vanatlon of the
MC145106/MC145112 family. The device contains the oscillator
circuitry required to operate with fundamental mode crystals to
10.24 MHz. The oscillator circuitry is connected to the phase detector
through a divide-by-16 and a 29-1 divlde-by-N counter. The reference
oscillator can be divided in steps of 16 between 32 and 8176 before
Interfacing with the phase detector. The .external Input to the phase
detector requires a V SS to VDD signal and forces the phase-detector
output high if higher in frequency than the output of the divlde-by-N
counter. An out-of-Iock signal IS provided from the on-chip lock
detector with a "0" level for an out-of-Iock condition.
•
•
•

Operation to 25 MHz
4.I1'to 12 V Operation
Programmable Reference Divisions from 32 to 8176 116 x 2 to
16x511)

•
•

Three-State Phase Detection
On-Chip Lock Detection

CMOS MS.
IlOW-POWER COMPLEMENTARY MOS)

PLL
FREQUENCY SYNTHESIZER

P SUFFIX
PLASTIC PACKAGE

CASE 648

~c,~

NOT

RECOM~f:fW
PROD~

PIN ASSIGNMENT
16

15

DESIGNS

3

14

4

13

PHASED OUT

12
6

11

10

Closest equivalent is the MC145106

ThIS device contains circuitry to protect the
Inputs against damage due to high statiC
voltages or electrtc fields. however, It IS
adVised that normal precautions be taken
to aVOid applicatIOn of any voltage higher
than maximum rated voltages to thiS high
Impedance Circuit For proper operatIon It IS
recommended that Vm and Vout be
constrained to the range VSS' (V ln or

Vou '"

6-35

VDD

•

®

MC145144

MOTOROLA

4-BIT DATA BUS INPUT PLL FREQUENCY SYNTHESIZER

CMOS LSI

The MC145144 is one of a family of LSI PLL frequency synthesizer
parts from Motorola CMOS. The famil.v includes devices having serial,
parallel and 4-bit data bus programmable inputs. Options include singleor dual-modulus capability, transmit/receive offsets, choice of phase
detector types and choice of reference divider integer values.
The MC145144 is programmed by a 4-bit input, with strobe and address lines. The device features consist of a reference oscillator, programmable reference divider, digital-phase detector, programmable
divide-by-N counter and the necessary latch circuitry for accepting the
4-bit input data. When combined with a loop filter and VCO, the
MC145144 can proYlde all the remaining functions for a PLL frequency
synthesizer operating up to the device's frequency limit. For higher VCO
frequency operation, a down mixer or a fixed divide prescaler can be used between the VCO and MC145144.

(LOW-POWER CQMPLEMENTARY MOSI

4-BIT DATA BUS INPUT PLL
FREQUENCY SYNTHESIZER

JIff!ffl!j
LiP

• Tailored for TV Tuning ApplicatIOns
• Low Power Drain

CE~

• 3.0 to 9.0 Vdc Supply Range

l( J'rYV

• >30 MHz TYPical Input Capability @5Vdc

I

• Programmable Reference DiVider for Values Between 3584 and ~
• On- or Off-Chip Reference OSCillator Operation
• Single Modulus 4-Bit

p~ta Bus Programming ~

s::t
E~

V

• Pin-far-Pin

P SUFFIX

PLASTIC PACKAGE
CASE 648

PIN ASSIGNMENT

~

• ... N Range =4 to 4092 in Steps of Eight

• "Linearized" Digital Phase Detector
Linearity
~

.-

nsfer Function

comp~~ he

VDD
OSC ln
OSCout
AD
A1
A2
ST

[

1 . """

[2

16

VSS

15

fin

[3

,.

[4

13

[5

12

[.
[ 1

10

11

DO
01
02
03
Test

+50ut[~ PDout

NOT RECOMMENDED FOR NEW DESIGNS
PRODUCT BEING PHASED OUT

Closest equivalent is the MC145145·1

6-36

®

MC145145·1

MOTOROLA
Advance Information

HIGH-PERFORMANCE

CMOS
4-BIT DATA BUS INPUT PLL FREQUENCY SYNTHESIZER
The MC145145-1 is programmed by a 4-bit input, with strobe and address lines. The device features consist of a reference oscillator, 12-blt
programmable reference divider, digital-phase detector, 14-bit programmable divide-by-N counter and the necessary latch cirCUitry for acceptmg the 4-bit input data. When combined with a loop filter and VCO, the
MC145145-1 can provide all the remaining functions for a PLL frequency synthesizer operating up to the device's frequency limit. For higher
VCO frequency operation, a down mixer or a fixed divide prescaler can
be used between the VCO and MCl45145-1.
The MC145145-1 offers improved performance over the MC145145.
The ac characteristics have been improved and the input current requirements have been modified.

LOW-POWER COMPLEMENTARY MOS
SILICON-GATE

4-BIT DATA BUS INPUT PLL
FREQUENCY SYNTHESIZER

MCI45145L1
CERAMIC PACKAGE
CASE 726

• General Purpose Applications:
CATV
TV Tuning
AMI FM Radios
Scanning Receivers
Two Way Radios Amateur Radio

MCI45145Pl
PLASTIC PACKAGE
CASE 707

PIN ASSIGNMENT

•
•
•
•

Low Power Consumption
3.0 to 9.0 V Supply Range
On- or Off-Chip Reference Oscillator Operation
Single Modulus 4-Bit Data Bus Programming
• -+- R Range=3 to 4095
• -+- N Range=3 to 16383
• "Linearized" Digital Phase Detector Enhances Transfer Function
Lineanty
• Two Error Signal Options:
Smgle Ended (Three Statel
Double Ended

Dl

fle'.JTa

DO

17

D3

flO

16

REFou!

D2

VSS

4

15

R

VDD

5

14

V

OSC IO [6

13

LD

12

~

AO [8

11

PST

A1 [9

10

~ A2

OSC OU !

PDOU !

OSC,n
OSCOU! - - ' - - - - - - '

=------------+

DO
Dl --'-----------~
D2
D3

PDou !

A2
At

AO
ST

VDD= Pin 5
Vss=Pin4

ll-'=::::r--J

r-~~~~~~~~~~~~~

ThiS document contains !nformatlon on a new product Specifications and Information herein
are subject to change without notice

6-37

V
R

•

MC145145·1
MAXIMUM RATINGS"

IVolta~~s' Referenced to VSS)

VOO

-Vln. Yout
lin. lout

100, ISS
Po
Tsto
TL

Value

Unit

-05to+1O

V

Parameter

Symbol
OC Supply Voltage

-05 to VOO+O 5

V

Input or Output Current (DC or TranSient), per Pin

±1O

mA

Supply Current, VOO or VSS Pins

±30

mA

500

mW

Input or Output Voltage IDC or Translentl

Power DIssipatIOn, per Packaget
Stp~age:

65 to + 150

TEfmperature

260

Lead Temperature 18-Second Soldenngl

ThiS deVice contains circuitry to protect
the Inputs agamst damage due to high
s,tattc voltages or electnc fields, however,
It IS adVised that normal precautions be
taken to
applications of any voltage
higher than maximum rated voltages to
thiS high-impedance circuit For proper
operation It IS recommended that Vm and
Vout be constramed to the range

avoid

'C
'C

VSS"IV In or.voutl"VOO·

* MaXimum Ratlngs

are those values beyond which damage to the deVice may occur
tPower DISSipation Temperature Derating

Unused mputs must always be tied to
an appropriate logiC voltage level ! e 9 ,

PlastiC "P"',Package -12 mW/'.Cfrom 65'C to 85'C
Ceramlc~"L"

either VSS or Vaal

packpge. No derating

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSI

-40°C
Characteristic

'P.ower, Supply Voltage Ra"ge,
'Outpu, Voltage
VIn=O V or VOO

o Level

Symbol

VOO

VOO

-

•

Typ

-

85'C
Min
3

Max

Units

-

Max
9

9

V

0001
0001
0001

005
005
005

-

005
005
005.

V

-

295
495
.895

-

09
15
27

-

09
15
2.7

-

21
35
63

-

3
5
9

295
495
895

-

295
495
895

3
5
9

-

09
15
27

-

2999
4999
8999
135
225
405

3
5
9

21
35
63

-

21
35
63

165
275
495

3
5
9

-044
-064
-1.30

-0'35
-051
-100

-10
-12
-20

IOl

3
5
9

044
064
130

-

035
051
100

10
12
20

lin

9

+03

+01

9

-

+000001

lin
C,n

-

±1O

±25

6

10

6

10

-

800
1200
1800

-

200

-

300

VOH

VIL

1 Level

VIH

-

-

-

-

-

-

-

-

Source

Vout=O 3V
Vout =04V
Vout=O 5 V

Sink

Other Inputs

Input Current·- fin' OSC ,n
Input Capacitance

3-State Output Capacitance PO Qut

Cout

Quiescent Current

laD

VIn=O V or VOO
10ul=0 /LA
3-State Leakage Current - PO out
Vout=O V or 9 V

IOZ

V

-

mA

IOH

Vout =27V
Vou t=46V
Vou t=8.5 V

Input Current -

Min
3

3
5
9

'VOL

lriput Voltage
o Level
Vout=O 5 V or VOO-O 5 V
IAII Outputs Except OSCO"tl

Output Current

25'C

Max

9
005
005
005

10ut=O itA

1 Level

Min
3

3
5
9
9

-

+50
10
10

±O 3

-

-

-022
-036
-070
022
036
070

-

-

± 10

~A

±22

~A

10

pF

10

pF

-

-

1800
2400
3200

~A

400

800
1200
1800

±O 0001

±01

-

±30

/LA

MC145145·1
SWITCHING CHARACTERISTICS (T A ~ 25°C CL ~ 50 pFI
Characteristic
Output Rise and Fall Time (Figures 1 and 61

Symbol

VOO

Min

Typ

Max

Units

tTLH.
tTHL

3
5

10
10

50
40

140

ns

9
Setup Times
Data to ST (Figure 21

tsu

Address to ST (Figure 21

Hold Times
Data to Strobe (Figure 21

th

Address to Strobe (Figure 21

Output Pulse Width
'~!!!:'
Total OlVlde Value

Total DIVide Value

GRAPH1C-VDD=9V

•

Total DIVide Value

GRAPH 2 - OSCin AND fin MAXIMUM FREQUENCY VERSUS TEMPERATURE FOR
SINE AND SQUARE WAVE INPUTS

GRAPH 28 - TOTAL DIVIDE VALUE,,6

GRAPH 2A - TOTAL DIVIDE VALUE=3, 4, OR 5

112
~

3V _

1.09

~~ 1.06 5V
!!:::f: 1.03 9V

- ---

§'u
~ ~ 1.00

! c; 097

1.063

----

~

-

h

~!!

~

.......

~ ~ 094
~ ~ 0.91

~

:;; 6
~

g 0.88

~

0.85

\

1049
1042

ITu 1035 5 V,
,"'
9V
1.028

i~

":

~

I\.,

Ell

~

5V
3V

,,
,,

1021

H
,-

1014
1007

j!

0.82
0.79

3V

1.056

1.000
0.993

\

,

,

"

",

"-

-'-

3V
5V
9V

~

1\9 V

-40

-20

20

40

60

80

-40

'* Data labelled "TYPical"

-20

20

40

60

Temperature (OCI

Temperature (DC)

IS not to be used for design purposes, but IS Intended as an mdlcatlon of the lC's potential performance

6-40

80

MC145145·1

PIN DESCRIPTIONS
DATA INPUTS (Pins 2, I, 18, 171 - Information at these
Inputs IS transferred to the Internal latches when the ST input IS In the high state Pm 17 (03) IS most significant

ST (Pin 11) - When high, thiS mput will enter the data
that appears at the DO, D 1, D2 and D3 Inputs, and when low,
will latch that InformatIOn When high, any changes In the
data Information will be transferred Into the latches

fin (Pin 31 - Input to - N portion of synthesIZer fin IS
tYPically derived from loop YCO and IS AC coupled mto Pm
3 For larger amplitude signals Istandard CMOS-logic levels)
DC coupling may be used

PDout (Pin 12) - Three-state output of phase detector for
use as loop error Signal
Frequency fy > fR or fy Leading Negative Pulses
Frequency fy < fR or fy Lagging Positive Pulses
Frequency fy = fR and Phase COinCidence H IghImpedance State

YSS (Pin 4) - CirCUit Ground
YDD (Pin 5) - Positive power supply
OSCin, OSCout (Pins 6 and 7) - These pins form an onchip reference oscillator when connected to terminals of an
external parallel resonant crystal
Frequency setting
capacitors of approprtate value must be connected from
OSC,n to ground and OSC out to ground OSC ,n may also

LD (Pin 131 - Lock detector Signal High level when loop
IS locked IfR, fy of same phase and frequencyl Pulses low
when loop IS out of lock

serve as Input for an externally-generated reference signal

This signal will tYPically be AC coupled to OSC ,n , but for
larger amplitude Signals Istandard CMOS-logiC levelsl DC
coupling may also be used In the external reference mode,
no connection IS required to OSC out

v, R (Pins 14 and 151 - These phase detector outputs
can be combined externally for a loop error Signal A slngleended output IS also available for thiS purpose Isee PDoutl
If frequency fy IS greater than fR or If the phase of fy IS
leading, then error Information IS provided by y pulsing
low R remains essentially high
If the frquency fy IS less than fA or If the phase of fy IS lagging, then error InformaliOn IS provided by A pulsing low
y remains essentially high
If the frequency of fV = fR and both are In phase, then
both y and A remain high except for a small minimum
time period when both pulse low In phase

ADDRESS INPUTS (Pins 8,9, 1m - AO, Al and A2 are
used to define which latch receives the InformatIOn on the
data mput lines The addresses refer to the following latches

A2 Al AO Selected
0
0

0
0

0
0

1
0
1

0
1
2
3
4

Function
- N Bits
- N Bits
- N Bits
- N Bits
Reference Bits

Latch 5

Reference Bits

0
4

1
5

6

0

Latch 6

Reference Bits

8

9

10

0
1

0
0
0

Latch
Latch
Latch
Latch
Latch

DO 01
1
0
4
5
8
9
12 13

02 03
3
6
10 11
3

REFout (Pin 161 - Buffered output of on-chip reference
oscillator or externally prOVided reference-Input signal.

11

6-41

•

MC145145·1
SWITCHING WAVEFORMS

FIGURE 1

Address
","0'

Any
Output

i

FIGURE2

50%

tsu
ST

Vss

FIGURE4

FIGURE3

~r~~------tw~------~,~,----

~R, ~V*

•

tf

..JJ

\1..!50_%_ _ _ _ _ _

*f r In phase with fv

FIGURE 6 - TEST CIRCUIT

FIGURE5

ST

J~~50:"A-,--------~-tw------------..,4L-t-VOO

Output
Device

VSS

Under
Test

6-42

.lCL
I

MC145145·1
PHASE LOCKED LOOP - LOW PASS FILTER DESIGN

A}

,

Fls} = R,CS + ,

B}

PD::~~----~~~-R2-I~----~OVCO

Wn

r

q,vo--

=

= 0.5"'n

I
Fls}

C}

fR2C + __N__"
"

C

=

Kq,KVCO-)

R2 CS + ,
sm,c + R2C} + 1

PDout~

q,RO---~~V-~~1
q,vO---~~~--'-~

c

>--*--ovco

Assuming gain A IS very large, then:

I

NOTE. Sometimes Rl IS spltt Into two senes resistors each Rl-2 A capacitor Cc IS then placed from the midpoint to ground to further hlter

q,V and q,R The value of Cc should be such that the corner frequency of this network does not significantly affect "'n.
DEFINITIONS: N = Total D,v,s.on RatIO .n feeaback loop
Kq, = VDD/4" for PDout
Kq, = VDD/2" for q,V and q,R
KVCO

= 2lrafVCO
aVVCO

for a tYPical des.gn "'n '" 2;;r lat phase detectorlnputl.

r"

1

RECOMMENDED FOR READING:
Gardner, Floyd M., Phase/ock Techniques Isecond edition). New York, Wlley-Intersc.ence, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design Isecond edition). New York, W.ley-Intersc.ence, 1980.
Blanchard, Ala.n, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wlley-Intersclence, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, W.ley-Intersc.ence, 1981
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Chffs, NJ, Prentice-Hall, 1983
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. IndianapolIs, Howard W Sams and Co , 1978

Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980

6·43

•

MC145145·1
FIGURE 7 - PHASE DETECTOR OUTPUT WAVEFORMS

IR
Reference

lOse

~

RI

IV
Feedback

1110

~

NI

PD Out

R

----'n-----Jn'---------.u~--+-I-

u

v

•

LD

u

NOTE: The Po output state IS equal to either VDO or VSS when active

I

I

~
~

I
I

When not active, the output IS high Impedance and the voltage at that

pm 15 determined by the low pass filter capacitor

6·44

MC145145·1
APPLICATIONS

small changes In this value, fine tuning IS accomplished Better tUning resolution IS achievable with this method than by
changing the - N, due to the use of the large fixed prescalIng value of - 256 provided by the MC12071
The two loop syntheSIZer, In Figure 9, takes advantage of
these features to control the phase locked loop With a
minimum of dedicated lines while preserving optimal loop
performance Both 25 Hz and 100 Hz steps are provided
while the relatively large reference frequencies of 10 kHz or
101kHz are maintained

The features of the MC145145-1 permit bus operation With
a dedicated wire needed only for the strobe Input In a
microprocessor-controlled system thiS strobe Input IS accessed when the phase lock loop IS addressed The remainIng data and address Inputs will directly Interface to the
microprocessor's data and address buses
The -+- R programmability IS used to advantage In Figure
8 Here, the nominal -+- R value IS 3667, but by programming

FIGURE 8 -

TV/CATV TUNING SYSTEM

358105 MHz
UHF/
VHF

Tuner
Or
CATV

Front
End

•
Key

Board
+V

Remote Control Section

6·45

I
3:

FIGURE 9 - TWO-LOOP SYNTHESIZER PROVIDES 25 AND 100 Hz FREQUENCY STEPS WHILE MAINTAINING HIGH DETECTOR
COMPARISON FREQUENCIES OF 10 AND 10.1 kHz

o....

~

....

en
~

Y'
....
7.9996 to 32.0184 MHz
1100 Hz Stepsl

l

~"

"

~Dl

'I [tE~

r-L
..... ,

~I

~

Loop 1
Filter

~

veal

~

~4

f--

4>V~

MC145145-1
Loop 1

15} /" /
•

4>R

3.9996 to 4.9995 MHz

Al

i6"l A2
-<>--t ST

--r:

~"

CJ)

1.9999 to 8.0046 MHz
125 Hz Steps I

f 1 ~
In

VM

and
16.0085 to 170084 MHz
110.1 kHz Stepsl

Choice of
Detector

.;..

Error

CJ)

T-

l.

I

I I I i I I I ~~~~CIn
OSC

co

out

jill [ fti~

.....

~MC145145-1
Loop 2

4>R
4>V

~5}
14

/

" /

~

VC02

4000 to 15.0100 MHz
110 kHz Stepsl

9

,nI Al

i..:! A2

'"

Address &::;a

To Controller

fin
5T

r

Chip sele/

VDD

!5

2~""'~!-----------~

VSS

-p
NOTES

Table 1 prOVides program sequence for the - NIl Loop 11 and - N2 1Loop 21 Counters.
- Al = 1000. fAl = 101kHz; ~ A2= 1010. fA2= 10 kHz
3. fVC01= NlIfAll+ N21fA21= NllfA2+,".1I + N21fA21 wherS',".f= 100 Hz
4. Other fAl and fA2 values may be used with appropriate ~ Nl and ~ N2 changes

MC145145·1
TABLE 1 - PROGRAMMING SEQUENCE FOR TWO-LOOP SYNTHESIZER OF FIGURE 9
~Nl

.J.

~

i •
495

t

... N2

fjnl (MHzl
3.9996

":"
l

"A"

~

f

"A"

417

400
399

tvC02 (MHzl
4.0000
3.9900

301
401
400

3.0100
4.0100
4.0000

8.0095
80096
80097

3.0200
4.0200
4.0100

8.0195
8.0196
8.0197

t

4.9995

.J
~
.J.

"C"

+

,1
"B"

.t·
I

1

1585
1586
1684

"1,,

t

,,1..

16.0085
16.0186

l

17.0084

t

t

302
402
401
303

"A"

t

"D"

+

3.0300

\5L

1600
1599

16.0000
15.9900

+

15.0.100

1501

+

•
t

•

8.0295
Increasing
In 100 Hz Steps

+

19.9995
19.9996
19.9997

•

20.0095
20.0085
20.0086

+

20.0184
20.0185
20.0186

.J
~

tvC01 (MHzl
7.9996
7.9997

'-

L

"C"

"D"

t

20.0284
Increasing
In 100 Hz Steps

•

"E"

1

32.0084
32.0085
32.0086

"F"

l

32.0t84

6-47

•

MC145145·1
CRYSTAL OSCILLATOR CONSIDERATIONS

the area of 8 to 15 M Hz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:

The following options may be considered to provide a
reference frequency to' Motorola's CMOS frequency synthesizers. The most desirable is discussed first.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-~ompensated crystal
osciliators (TXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-ta-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please .contact: Motorola Inc., Component Products, 2553 N. Edgington St., Franklin PWk, IL60131, phone
(312) 451-1000.

•

DESIGN AN OFF-CHIP REFERENCE
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061 , MC12560, or MC12561 MECL
devices. The refe~ence signal from the MECL device is ac
'coupled to OSCin. For large amplitude signals (standard
CMOS logic levelsl, dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD= 5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
TABLE A -

where

Cin
Cout
Ca
Co

=
=
=
=

5 pF (see Figure C)
6 pF (see Figure C)
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
C1 and C2 = External capacitors (see Figure A)

The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
.In some cases, stray capacitance should be added to the
values for Cin and Cout.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified bv the
crystal man\lfac:turer is the maximum stress that a crystal can
withstand wit.hout damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i.e. R1 = 0 ohms.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize l0troing.) The frequency should increase very
s!igt]l!Y1!~ tHe dc supply voltage IS increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply Voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition .,exists. The user should note that the
oscillator start-up time IS proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A.

PARTIAL LIST OF CRYSTAL MANUFACTURERS

NAME
United States Crystal Corp.
Crystek Crystal
Statek Corp.

CinCout
C1.C2
CL=-C'
C +Ca+CO+ - C C2
1
m+ out
+

ADDRESS
3605 McCart St., Ft. Worth, TX 76110
1000 Crystal Dr., Ft. Myers, FL 33906
512 N. Main St., Orange, CA 92668

PHONE
18171921-3013
18131 936-2109
17141639-7810

RECOMMENDED FOR READING
D. Kemper, L Rosine, "Quartz Crystals for Frequency
Control", Electra- Technology, June, 1969.

Technical Note TN-24, Statek Corp.
Technical Note TN-7, Statek Corp.

P. J. Ottowitz, "A GUide to Crystal Selection", Electronic
Design, May, 1966.

E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.

6-48

MC145145·1
FIGURE A -

r-

I

PIERCE CRYSTAL OSCILLATOR CIRCUIT

-----------l
Rt
Frequency
Synthesizer I

I

I

I
: ___
L

I
_ _ _ _ _ _ _ ..JI

_

OSCout

Rl*

DI-t---A.N'v--'

Cl

:I: .::t

* May be deleted

In

C2

certain cases. See text

FIGURE B -

EQUIVALENT CRYSTAL NETWORKS

Co
Values are supplied by crystal manufacturer (parallel resonant crystal)

FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER

a

~~----'"'TI---""'O
I

O-"'I,.--~--II-I

:=r:

II

I

I
Cin

:;:: Cout

I
~-

I
~-

6-49

•

®

MC145146·1

MOTOROLA
Advance Information

HIGH-PERFORMANCE

CMOS
LOW-POWER COMPLEMENTARY MOS
SILICON-GATE

4-BIT DATA BUS INPUT PLL FREQUENCY SYNTHESIZER
The MCl45146-1 is programmed by a 4-bit input, with strobe and address lines. The device features consist of a reference oscillator, 12-blt
programmable reference divider, digital phase detector, 10-blt programmable dlvide-by-N counter, 7-bit divide-by-A counter and the necessary
latch circUitry for accepting the 4-blt Input data. When combined with a
loop filter and VCO, the MC145146-1 can provide all the remaining functions for a PLL frequency synthesizer operating up to the device's frequency limit. For higher VCO frequency operation, a down mixer or a
dual modulus prescaler can be used between the VCO and the
MCl45146-1.
The MC145146-1 offers Improved performance over the MC145146.
Modulus Control output drive has been increased and the ac
characteristics have been Improved. The input current requirements
have also been modified.

4-BIT DATA BUS INPUT PLL
FREQUENCY SYNTHESIZER

~~

2~m1lf~·] ~ I i !'lYl~llTll I

• General Purpose Applications·
CATV
TV Tuning
AM/FM Radios
Scanning Receivers
Two Way Radios
Amateur RadiO

•

MCl45146L1

MC145146Pl

CERAMIC PACKAGE
CASE 732

PLASTIC PACKAGE
CASE 738

PIN ASSIGNMENT

•
•
•
•
•

Low Power Consumption
3.0 to 9.0 V Supply Range
Programmable Reference Divider for Values Between 3 and 409~ 0
On- or Off-Chip Reference Oscillator Operation
Dual Modulus 4-Bit Data Bus Programming
• + N Range=3 to 1023, + A Range=O to 127
• "Linearized" Digital Phase Detector Enhances Transfer Function
Linearity

Dl

D2

DO

D3

fin

fR

VSS

O---+-~
12-Blt _ R Counter
1--------,_----_''''8 fR
OSCout 8
~r1r1r1. . . .-r-r""""T"".J

L5

L7

L6

___~________+-+-+-+-_-.
D1 ~'~__________~~+-+-_~-,
D2 ~W~_ _ _ _ _ _ _ _ _ _ _+-+-+-+-_~-4-,

DO~2

D3~19~-----------+-+-+-+--~-4-4-,
Latches

L2

L4

L3

LO : L1

lQ..Blt ... N Counter

VDD= Pin 6
VSS= Pin 4

1--_ _ _ _ _ _ _----",,4
L..---"_....J

ThiS document contarns rnformatlon on a new product SpeCifications and rnformatlon herein
are subject to change Without notice.

6-50

~g~Wgr

MC145146·1
MAXIMUM RATINGS* IVoltages Referenced to VSSI
Symbol

Vafue

Unit

-05 to + 10

V

-05 to VOO+O 5
±10

V
mA

±30
500

mW

Parameter

OC Supply Voltage

VOO

Input or Output Voltage 10C or Translentl

Vln, Vout

Input or Output Current (DC or Translentl, per Pin

lin. lout

Supply Current, VOO or VSS Pins

100, ISS

Power DISSipation, per Packaget

Po

Storage Temperature

Tstg

It IS

'C

260

'C

advised that normal precautions be

taken to avoid applications of any voltage

mA

-65 to +150

lead Temperature 18-Second Solderlngl

h

This device contains circUItry to protect
the Inputs against damage due to high
static voltages or electric fields, however,

higher than maximum rated voltages to
this hlgh~lmpedance CirCUit. For proper

operation It IS recommended that Yin and
Vout be constrained to the range

VSS"IVin or Voutl"VOO

* MaXimum Ratings are those values beyond which damage to the deVice may occur.
tPower DISSipation Temperature Derating:

Unused Inputs must always be tied to

an appropriate logiC voltage level fe g.,

Plastic "P" Package: -12 mWI 'C from 65'C to 85'C
Ceramic" l" Package: No derating

either VSS or VOOI

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSI
Symbol

VOO

Min

VOO

-

3

o level

VOL

3
5
9

1 level

VOH

Characteristic

Power Supply Voltage Range
Output Voltage
Vin~O V or VOO
10ut~0 ~A

Input Voltage
o level
Vout~O 5 V or VDO-0.5 V
(All Outputs Except OSCoutl

Vil

1 level

VIH

Output Current - Modulus Control
Source
Vout~2.7 V
Vout~4.6 V
Vout~8.5 V
Sink
Vout~0.3V
Vout~O.4 V
Vout~0.5 V

IOH

Output Current -

IOH

Other Outputs
Source

Vout~27V

Vout~46
Vout~8.5

IOl

V
V

Vout~O

Sink
3V
4V
Vout~O 5 V
Input Current - Other Inputs

IOl

Input Current -

lin
Cin

Vout~O

frn, OSCrn

Input Capacitance

lin

V
V

-

-

0001
0001
0001

005
005
005

-

0.05
005
0.05

3
5
9

2.95
4.95
8.95

-

295
495
8.95

-

2.95
495
B.95

-

3
5
9

-

-

-

09
15
2.7

-

-

0.9
1.5
27

2.999
4999
8999
135
225
4.05

-

0.9
15
27

3
5
9

21
35
6.3

-

21
35
63

165
2.75
495

-

-

21
3.5
63

-

! 3,

-

5'
9

-060
-090
-150

-

-050
-075
-125

-1.5
-2.0
-3.2

3
5
9

130
190
360

-

110
1 70
330

5.0
60
100

3
5

-044
-064
-130

-

-035
-051
-1.00

-10
-12
-20

035
051
100

10
12
20

-

-

±O 00001

+01

±10
6

±25
10

6

10

-

-

200
300
400

BOO
1200
1600

±O 0001

±01

-

-

V

mA

-

-030
-050
-060
066
108
210

mA

9.
3
5
9
9
9
--

IOZ

9

PD out

Units

9

9

3
5
9

Vout~O

Max

-

100

3-State Leakage Current -

Max

3

QUiescent Current
10ut~0 ~A

85°C

Typ

9
005
005
005

Cout

V or VOO

25°C
Min

Min
3

3-State Output Capacitance PO OU !
VIn~O

-40°C
Max

-

-

044
064
130

-

-

±03

-~

-

±50
10

10
800
1200
1600
±03

V or 9 V

6·51

-

-

-022
-036
-070
022
036
0.70

-

±10

~A

±22
10
10

~A

1600
2400
3200

~A

±30

p.A

pF
pF

•

MC145146·1
SWITCHING CHARACTERISTICS ITA ~ 25'C CL ~ 50 pFI
Characteristic

Symbol

Output Rise Time. Modulus Control iFlgures 1 and 71

tTLH

VDD
3
5

9
Output Fall Time. Modulus Control (Figures 1 and 71

tTHL

3
5

9
Output Rise and Fall Time. Other Outputs (Figure 11

tTLH.
tTHL

3
5

9
Propagation Delay Time
fin to Modulus Control (Figures 2 and 71

tPLH.
tpHL

Setup Times

tsu

Data to ST IFlgure 31

3
5

Hold Times
Address to ST (Figure 31

th

•

tr.tf

,

.. ,

"j ....

6-52

60
40

30
55
40
25
0
0
0

9

30

60
30
18

3
5

35
25
20

15
10
10

25
20
15

10
10
10

25
20
10

100
60 .

40
35
25

3
5
3
5

w' I,,'"")
1?::r~
t

-

20
25
17
15

80

9
Input Pulse Width ST. (Figure 61

-

30

3
5

9
Input Rise and Fall Times
OSC In • fin. ST iFlgure 51

ns

-

9
twcf>

Units

115
60
40
60

10
10
10

3
5

Output Pulse Width. <1% cf>V with f r In
Phase with fV (Figures 4 and 71

Max

50

3
5

9
Data to Strobe (Figure 31

Typ

-

9

9
Address to ST iFlgure 31

Min

f" ~

50

ns

34
30
140

ns

60
60
125
80

ns

50
-

ns

ns

ns

40

175
100
70

20
5
2

5
2
05

~s

30
20
15

-

ns

MC145146·1
GRAPH 1 - DSCin AND fin MAXIMUM FREQUENCY VERSUS TOTAL DIVIDE VALUE

GRAPH 1A - VDD=3V

GRAPH 1B - VDD=5V

~ 16
~

i

f

£

~

14~-r-;__T--r__~4-~~+-~~__~r+__~~

28
26

!go

12~~-+--~~-+~~T--r-'--'+--r'r+--~

~

!l

0

E

11;0

"
~

1
Total DIvide Value

Total DIVide Value

GRAPH 1C - VDD=9V

~ 28~-r-+--~4--+--~4--+--~+--r;~--+-~

~~

26

Typical'-c::J_+~-+~-+-:::I_+--+"'''+--+--I

~ 24~-¥~~-r~--~~~-r~---r-+--~'~--+-~

I 22~~--f~~~~-r~---r~---r-+--~'~--+-~

f 20~~--~-r-;~,--Square
TA-25°C
Wave. Voo'Vss

g
~

18

- -Sme Wave, 500

mVp-p~~'-r~---1

•

~ 16
~ 14
112

Total DIvide Value

GRAPH 2 - OSCin AND fin MAXIMUM FREQUENCY VERSUS TEMPERATURE FOR'
SINE AND SQUARE WAVE INPUTS

GRAPH 2B - TOTAL DIVIDE VALUE;;, 6

GRAPH2A - TOTAL DIVIDE VALUE=3. 4, OR5
1.12
~
1.09
g~ 1.06
J: ~ 1.03

~~

3V _
5V
9V

- ---

i~

----

r- ~

1.00

! c; 0.97

.....

~ ~ 0.94

~

[':': ~

~ ~ 0,91
~;;o

1

0,88
0,85
0,82
0.79

"-,

~

5V
3V

'.
-40

-20

20

1.063 3V
1,056
1.049
..t:~ 1.042
!!,u 1.035 5 V,
;;~
9V
lON 1.028
S-s
E~
1.021
~ i!l
S~ 1.014
~~ 1.007
J~ 1.000
0,993

40

60

1'9 V
80

-40

labelled "TYPical"

IS

..

\

\ ,

"\.

".........

-20

--- ...::.:. ....

3V
5V
9V

20

40

60

80

Temperature lOCI

Temperature (0 C)

* Data

..

not to be used for deSign purposes, but

IS

6-53

Intended as an indication of the lC's potential performance

MC145146·1
PHASE LOCKEO LOOP - LOW-PASS FILTER OESIGN

AI

PDouto

"l/iiio

oVCO

I

Al

C

"'A 0 - -

I

"'v<>--

r

= O.5"'N IN/K",KVCOI

Fls} = _ _
1_
AICS + 1

B}

PDoutO

"l/iiio
Al

"1

"'Ao--

"'v

•

CI

0--

° VCO

I

=

C

r

Al
"'R

K",KVCO
NCIAI + A2}

= O.5"'N IA2C + N/K",KVCO}

Fisl =

A2CS + 1
SIAIC + A2CI +

"'N =

K",KVCO
NCRI

PD out 0 - -

"'V

V
I

wN

VCO

r

Al

C

"'NR2C

= -2-

Assummg gam A

I

IS

very large, then

FI I = A2CS + 1
s
RICS

NOTE: Sometimes Rl isspht into two senes resistors each Rl ... 2 A capacitor Cc IS then placed from the midpoint to ground to further filter tbV and
A· The value for Cc should be such that the corner frequency of this network does not slgm"cantl\ .ffect "'N

DEFINITIONS. N = Total DIVision Aallo In feedback loop
K = VDD/4 .. for PDoul
K = VDD/2 .. for V and A
KVCO = 2..~fVCO
~VVCO

for a Iypical deSign "'N "12 .. /101 fr lal phase deleclor input!

r ..

1

6·54

MC145146·1
FIGURES
PHASE DETECTOR OUTPUT WAVEFORMS

IR
Reference

10sc

+

RI

IV
Feedback
If In + NJ

POOul

R

LO

n

-----IInI ' - - - - - - J

U. - - - - - - - + - - -

L------.

u

I

u

NOTE. The Po oulpul slale IS equal 10 ellher VOO or VSS when acllve. When nol aclive, Ihe oulpullS high Impedance and Ihe vollage al thaI
pIn IS determined by the low pass filter capacItor.

6·55

MC145146·1
PIN DESCRIPTIONS
DATA INPUTS (Pins 2,1,20,19) - Information at these
inputs is transferred to the internal latches when the ST input is in the high state. Pin 19 ID3) is most significant.

Will latch that Information. When high. any changes In thl'
data Information Will be transferred Into the latches.
LD (Pin 13) - Lock detector signal. High level when loop
IS locked (fR. fV of same phase and frequency). Pulses low
when loop IS out of lock.

ftn (Pin 3) - Input to ... N portion of synihesizer. fin IS
typically denved from loop VCO and IS AC coupled into Pin
3. For larger amplitude signals (standard CMOS-logic levels).
DC coupling may be used.
Vss (Pin 4) -

MODULUS CONTROL (Pin 14) - Signal generated by the
on-Chip control logic circuitry for controlling an exter,)al dual
modulus prescaler. The modulus cantlol level Will be low at
the beginning of a count cycle and will remain low until the
+ A counter has counted down from ItS programmed value.
At thiS time. modulus control goes high and remains high
until the - N counter has counted the rest of the way down
from Its programmed value IN-A additional counts since
both + Nand - A are count;ng down during the first portion
of the cycle). Modulus control IS then set back low. the
counters preset to their respective programmed values. and
the above sequence repeated. ThiS provides for a total programmable diVide value INT) = NoP + A where P and P + 1
represent the dual modulus prescaler divide values respecbvely for high and low modulus control levels. N the number
programmed into the + N counter and A the number programmed Into the ... A counter.

Circuit Ground.

PDout (Pin 5) - Three-state output of phase detector for
use as loop error signal.
Frequency fV> fR or fV Leading: Negative Pulses.
Frequency fV < fR or fV Lagging: Positive Pulses.
Frequency fV = fR and Phase CoinCidence: HighImpedance State.
VDD (Pin 6) -

•

PosItive power supply.

OSCin, OSCout (Pins 7 and 8) - These pins form an onchip reference oscillator when connected to terminals of an
external parallel resonan1 crystal. Frequency setting
capacitors of appropriate value must be connected from
OSCin to ground and OSCout to ground. OSC In may also
serve as input for an externally-generated reference signal.
This signal will typically be AC coupled to OSC,n • but for
larger amplitude Signals Istandard CMOS-logic levels) DC
coupling may also be used. In the external reference mode.
no connection is required to OSC out .

IV (Pin 15) - ThiS is the output of the - N counter that IS
Internally connected to the phase detector input. With thiS
output available. the ... N counter can be used independently.

ADDRESS INPUTS (Pins 9,10,11) - AO, Al and A2 are
used to define which latch receives the information on the
data input lines. The addresses refer to the following latches:

V, R (Pins 16 and 17) - These phase detector outputs
can be combined externally for a loop error signal. A singleended output is also available for thiS purpose Isee PD out ).
If frequency fV is greater than fR or If the phase of fV is
leading, then error information is prOVided by V pulSing
low. R remains essentially high.
If the frquency fV IS less than fR or if the phase of fV is lagging. then error information is provided by R pulSing low.
V rem'alnsv and R remain high except for a small minimum
time penod when both pulse low in phase.

A2 Al AO Selected
Function
DO 01 02 03
0 0 0 Latch 0
+A Bits
0 1 2 3
0 0 1 Latch 1
+A Bits
4
5 6
... N Bits
0 1 0 Latch 2
0 1 2 3
0 1 1 Latch 3
+N Bits
4 5 6 7
1 0 0 Latch 4
+N Bits
8 9
1 0 1 Latch 5 Reference Bits 0 1 2 3
1 1 0 Latch 6 Reference Bits 4 5 6 7
1 1 1 Latch 7 Reference Bits 8 9 10 11

fR (Pin 18) - This IS the output of the + R counter that is
internally connected to the phase detector Input. With this
output available, the ... R counter can be used independently.

ST (Pin 12) - When high, this input will enter the data
that appears at the DO, 01, 02 and 03 inputs. and when low,

6·56

MC145146·1
SWITCHING WAVEFORMS

FIGURE 1

FIGURE2

----Voo

tTHL
Any

Output

Modulus
Control

FIGURE4

FIGURE3

Data or
Address

-VOO

,.==r

VSS

R,V'

-{w%

tw

* fr In phase with fv

ST
VSS

FIGURE6

FIGURES

r,1oo1-----tw

tf·
ST

FIGURE 7 - TEST CIRCUIT

Output
Device
Under
Test

6·57

--'W%

r-

MC145146·1
APPLICATIONS
The features of the MC145146-1 permit bus operation with
a dedicated wire needed only for the strobe input. In a
microprocessor controlled system this strobe input is accessed when the phase lock loop is addressed. The remaining
data and address inputs will directly interface to the
microprocessor's data and address buses.
The device architecture allows the user to establish any integer reference divide value between 3 and 4095. The wide

selection of ... R values permits a high degree of flexibility in
choosing the reference oscillator frequency. As a result the
reference oscillator can frequently be chosen to serve multiple system functions such as a second local oscillator in a
receiver design or a microprocessor system clock. Typical
applications that take advantage of these MCl45146-1
features including the dual modulus capability are shown In
Figures 9, 10, and 11.

FIGURE 9 - FMI AM BROADCAST RADIO SYNTHESIZER
Lock Detect Signal

8
7

18

OSCout

13

15

LD
5
PDout

"'~O---IOSC,n

Optional
Loop Error
Signal

~Rrl~7~~~~~~'i
MC145146-1

•

~vr16~~~~~~-;
Mod ~1~4__o-____-,

.--o-_6'iVDD

Control Voltage
To FM amj AM
Oscillators

4

Clock

From
AMOSC

NOTES:

For FM: Channel spacing=fR=25 kHz, + R= 160.
For AM: Channel spacing=fR = 1 kHz, + R=4000.
2) Various channel spacings and reference oscillator frequencies can be chosen since any + R value from 3 to 4095 can be established.
3) Data and address lines are inactive and high impedance when pin 12 is low. Their interface with the controller may therefore be
shared With other system functions if desired.
1)

6·58

3:

o
.....
.j:Io.
en
.....
.j:Io.
Q)

FIGURE 10 - SYNTHESIZER FOR UHF MOBILE RADIO TELEPHONE CHANNELS DEMONSTRATES USE OF THE MC145146-1 IN
MICROPROCESSOR/MICROCOMPUTER CONTROLLED SYSTEMS OPERATING TO SEVERAL HUNDRED MHz

- -

:--

-

-~}

For Use with External

Phase Detector (OptlOnall

--~

I

ChoIce of
Lock Detect

Ref. Osc
Frequency

---

(On-Chip Osc
Optlonall

PDoutr-- , ,

6

~VDD

Transmitter
Modulation

~Re

(J)

CO

Receiver

LO
443_325 - 443_ 950
MHz
(25 kHz Stepsl

?

o---I,osc in

cJ,

-S'9 nal

MCI45145-1

~V

and 157 MHz
Otfset

16

r:

Mod
Control 3
fin

Dual Modulus Prescaler
Controller Bus

NOTES 11 Receiver I F = 107 MHz, low side InleCtlOn
2) Duplex operatIOn with 5 MHz receive/transmit separation
3) fR = 25 kHz, - R chosen to correspond with deSired reference oscIllator frequency

41 Ntotal= 17733 to 17758= NoP+ A, N=277, A=5 to 30 for P=64_
51 For faster response, use the MC10154 down countel-

•

T ransmrtter SIgnal

459 025 - 459 650 MHz
(25 kHz Stepsl

.:,.

•

:s:

...../:10
c.n
....

C')

~

cp

.....

FIGURE 11 - 666 CHANNEL, COMPUTER CONTROLLED, MOBILE RADIO TELEPHONE SYNTHESIZER FOR
BOO MHz CELLULAR RADIO SYSTEMS
.--------------------------i.~

For Use With
External
Phase Detector
(Optional)

- - - - ....)

Ref. Osc.
11.100 MHz
IOn-Chip Osc
Optional}

Receiver
2nd. L 0
33300 MHz

j - - -.
:

Receiver First L 0
825 030 - 844 980 MHz
130 kHz Steps)

I

Lock Detect Signal
fR

-11

fV

LD

5
PDoutf

. losc m

4>R

0>

0,

6

MC145146-1

VDD

o

117

4
VSS

fin

Transmitter Signal
825030-844 980 MHz
130 kHz Steps)

Vr - - - - - - - - - - -I

\

Controller Bus

- 32/- 33 Dual Modulus Prescaler

NOTES: 1) Receiver 1st I. F. = 45 MHz, low side InJection; Receiver 2 nd. I. F. = 117M Hz, low side injection
2) Duplex operation with 45 MHz receive/transmit separation
31 fR ~ 7.5 kHz, + R ~ 1480.

4) Ntotal ~ N°32 + A ~ 27501 to 28166; N ~ 859 to 880;
5) Only one Implementation

IS

A~

0 to 31

shown Vanous other configurations and dual modulus prescalmg values to -128/ - 129 are possible

MC145146·1
CRYSTAL OSCILLATOR CONSIDERATIONS

the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping vanations in stray and IC Input/ output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:

The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable IS discussed first.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-compensated crystal
oscillators (TXCOsl or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of Sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSC In . In general,
the highest frequency capability is obtained utilizing a dtrectcoupled square wave having a rail-to-rall (VDD to VSSI
voltage sWing If the oscillator does not have CMOS logic
levels on the outputs, capaCitive or ac coupling to OSC ,n
may be used. OSCout, an unbuffered output, should be left
floating.
For additional Information about TXCOs and data clock
OSCillators, please contact. Motorola Inc, Component Products, 2553 N. Edgington St., Franklin Park, IL60131, phone
(3121451-1000.

CL= CinCout +Ca+CO+ C1·C2
Cin + Cout
C'i+C2
where

= 5 pF (see Figure CI
= 6 pF (see Figure CI
5 pF (see Figure CI
Ca
The crystal's holder capacitance
Co
(see Figure BI
C1 and C2
External capacitors (see Figure AI

Cin
Cout

The OSCillator can be "tnmmed" on-frequency by making
a portton or all of C1 vanable The crystal and associated
components must be located as close as possible to the
OSC In and OSCout pinS to minimize distortion, stray
capacitance, stray Inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Cout.
Power IS dissipated In the effective series resistance of the
crystal, Re, In Figure B. The drive level specified by the
crystal manufacturer IS the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 In Figure A limits the dnve level. The use of R1 may not be
necessary in some cases; i.e. R1 = 0 ohms.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdnven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time IS proportional to the value of R1.
Through the process of supplying crystals for use With
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals
Discussions With such manufacturers can prove very helpful.
See Table A

DESIGN AN OFF-CHIP REFERENCE
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillater applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference signal from the MECL device IS ac
co~pled to OSCin. For large amplitude signals (standard
CMOS logiC levels), dc coupling IS used. OSCout, an unbuffered output, should be left floating. )n general, the highest
frequency capability IS obtained With a direct-coupled square
wave having rall-to-rail voltage sWing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverterl along With an appropnate crystal may be used to proVide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the deSired operating frequency, should be connected as
shown In Figure A
For VDD= 5 V, the crystal should be specified for a
loading capacitance: CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies In

TABLE A - PARTIAll/ST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp
Crystek Crystal
Statek Corp

ADDRESS
3605 McCart St , Ft Worth, TX 76110
1000 Crystal Or , Ft Myers, FL 33906
512 N Main St , Orange, CA 92668

PHONE
18171 921-3013
18131936-2109
17141639-7810

RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.

D. Kemper, L. ROSine, "Quartz Crystals for Frequency
Control", Electro- Technology, June, 1969.

Technical Note TN-7, Statek Corp
E. Hafner, "The Plezoelectnc Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No 2, Feb.,
.1969.

P J. OttOWltZ, "A GUide to Crystal Selection", Electronic
Design, May, 1966.

6-61

MC145146·1
FIGURE A -

r-

I

PIERCE CRYSTAL OSCILLATOR CIRCUIT

-----------l
~

~~~

Synthesizer

I
: ___
L

I
_ _ _ _ _ _ _ ...JI

_

OSC aut

Rl"

DI-..---'VV~

C1T T C2

* May be deleted In certaIn cases See text

FIGURE B -

EQUIVALENT CRYSTAL NETWORKS

RS

II

101-0

0---;

2

LS

Cs

~
Co

Values are supphed by crystal manufacturer (parallel

FIGURE C -

reso~ant

a

=:r=

crystal).

PARASITIC CAPACITANCES
OF THE AMPLIFIER

~-------,1---.......;0
1

01--"1r---1--11-"
1
I

I

I

I

::r=1

C,n

I

I

J_

~_

6·62

Caut

®

MC145151-1

MOTOROLA

HIGH-PERFORMANCE

Advance Information

CMOS

PARALLEL INPUT PLL FREQUENCY SYNTHESIZER
The MC145151-1 IS programmed by 14 parallel Input-data lines. The
device features consist of a reference oscillator, selectable-reference
divider, digital-phase detector and 14-bit programmable divide-by-N
counter. When combined with a loop filter and VCO, the MC145151-1
can provide all the remaining functions for a PLL frequency synthesIZer
operating up to the device's frequency limit. For higher VCO frequency
operation, a down mixer or a fixed diVide prescaler can be used between
the VCO and MCI40151-1.
The MC145151-1 offers improved performance over the MC145151.
The ac characteristics have been improved and the Input current requirements have been modified.
• General Purpose Applications:
CATV
TV Tuning
AMI FM Radios
Scanning Receivers
Two-Way Radios Amateur Radio
Low Power Consumption
3.0 to 9.0 V Supply Range
On- or Off-Chip Reference Oscillator Operation
Lock Detect Signal
• -<- N Counter Output Available
• Single Modulus/Paraliel Programming
• 8 User-Selectable -<- R Values - 8, 128,256,512, 1024, 2048, 2410,
8192

LOW-POWER COMPLEMENTARY MOS
SILICON-GATE

PARALLEL INPUT PLL
FREQUENCY SYNTHESIZER

MCI45151L1

MCI45151Pl

CERAMIC PACKAGE
CASE 733

PLASTIC PACKAGE
CASE 710

PIN ASSIGNMENT

•
•
•
•

•

28
27
26
25
24
6

22

8

-+- N Range= 3 to 16383

• "linearized" Digital Phase Detector Enhances Transfer Function
Linearity
• Two Error Signal Options:
Single Ended (Three-Statel
Double Ended
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates

23

21
20

10

19

11

18

12

17

13

16

14

15

VOD= Pin 3
VSS= Pin 2

Nl3

NIl

N7 N6

ThiS document contains information on a new product SpeCifications and information herein
are subject to change without notice

6-63

Note" NO through N13 Inputs and inputs
RAO, RAI and RA2 have pull up resistors
not shown.

•

MC145151·1
MAXIMUM RATINGS* IVoltages Referenced to VSS)
Symbol
Parameter
VDD
Yin, Vout
lin, lout
IDD, ISS
PD
Tsto
TL

Value
-0.5 to + 10

Unit
V

-0.5 to VDD+0.5
±10

V
mA

±30
500

mA

DC Supply Voltage
Input or Output Voltage IDC or TransIent)
Input or Output Current IDC or Transient!, per PIn
Supply Current, VDD or VSS Pins
Power Dissipation, per Packaget
Lead Temperature 18-Second Solderong)

It is advised that normal precautions be

taken to avoid applications of any voltage
higher than maximum rated voltages to
this high-impedance corcuit. For proper
operation It is recommended that Vin and
Vout be constrained to the range
VSSslVin or Vout)sVDD·
Unused inputs must always be tIed to
an appropriate logic voltage level le.g.,
either VSS or VDD)·

mW

65 to +150

Storage Temperature

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,

260

°C
°C

* Maximum Ratings are those values beyond which damage to the device may occur.
tPower Dissipation Temperature Derating:

PlastIc "P" Package: -12 mW/oC from 65°C to 85°C
CeramIc" L" Package: No derating

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSS)
-40°C

Output Voltage
Vin=O V or VDD
lout-O ~A

I

Max

-

9

-

0.001
0.001
0.001

-

2.95
4.95
8.95

-

0.9
1.5
2.7

3
5
9

2.1
3.5
6.3

3
5
9

VOD

Min

Max

VDD

-

3

o Level

VOL

3
5
9

-

9
0.05
0.05
005

1 Level

VOH

3
5
9

2.95
4.95
8.95

3
5
9

Min
3

Min
3

Max
9

Units
V

0.05
0.05
0.05

-

0.05
0.05
0.05

V

2.999
4.999
8.999

-

2.95
4.95
8.95

-

-

1.35
2.25
4.05

0.9
1.5
2.7

-

0.9
1.5
2.7

-

2.1
3.5
63

1.65
2.75
4.95

-

21
3.5
6.3

-

-0.44
-0.64
-1.30

-

-0.35
-0.51
-1.00

-1.0
-1.2
-2.0

-0.22
-0.35
-0.70

-

3
5
9

0.44
0.64
1.30

-

0.35
0.51
100

1.0
1.2
2.0

-

022
036
0.70

-

9
9

-

IIH

±50
0.3

±10
0.00001

+25
0.1

IlL

9

-400

-90

-200

Cin

-

-

-

6

10

6

10

-

3
5
9

-

800
1200
1800

-

200
300

400

800
1200
1600

9

-

±0.3

-

±O.OOOI

±0.1

Input Voltage
o Level
Vout =0.5 V or VDD-0.5 V
IAII Outputs Except OSC out )

VIL

1 Level

VIH

Output Current
Vou t=2.7V
Vout =4.6 V
Vout =8.5 V

Input Capacitance
3-State Output CapacItance PDout
Quiescent Current
Von=O V or VDD
10ut=0 ~A
3-State Leakage Current - PDout
You =OVor9V

10L

lin

Cout
IDD

10Z

-

-

-

V

rnA

10H
Source

Vout =0.3V
Sink
Vout =04V
Vou t=0.5 V
Input Current - fin, OSCin
Input Current - Other Inputs
IWlth Pullups)

85°C

25°C
Typ

Symbol

Characteristic
Power Supply Voltage Range

-

10
10

6-64

-

-

±22
10

~A
~A

-170
10

pF

10

pF

1600
2400
3200

~A

±3.0

~A

MC145151·1
SWITCHING CHARACTERISTICS iT A = 25'C CL = 50 pFI
Characteristic

Svmbol

OulpUI Rise and Fall Time IF,gures 1 and 41

ITLH,
ITHL

VOO
3
5
9

Oulpul Pulse Wldlh,
q,R, q,V wllh fR In Phase wllh fV IF,gures 2 and 41

Iwlq,1

Input Rise and Fall Times
OSC m, flO IFlgure 31

Ir,lf

3
5
9

3
5
9

Min

-

25
20
10
-

TVp
60

Max

Units

140

ns

40

80

30
100

60
175
100
70
5
2
05

60

40
20
5
2

ns

ps

PIN DESCRIPTIONS
fin (Pin 1) - Inpul to -+ N portion of synthesIZer. fin IS
typically derived from loop VCO and IS ac coupled Into Pin 9.
For larger amplitude signals (standard CMOS Logic levels)
dc coupling may be used.

If the frequency of fV = fR and both are in phase, then
both tPV and tPR remain high except for a small minimum
time period when both pulse low in phase.

tv (Pin 10) - This is the output of Ihe + N counter that is
internally connected to the phase detector input. With this
output available, the + N counter can be used independently.

VSS (Pin 2) - CirCUit ground.
VDD (Pin 3) -

Positive power supply.

PDout (Pin 4) - Three-state output of phase detector for
use as loop error signal. Double-ended outputs are also
available for this purpose (see q,V and q,Rl.
Frequency fV>fR or fV Leading: Negative Pulses
Frequency fV---<1'---0 VCO
Rl

C

Assuming gain A

IS

very large. then.

I

NOTE' Sometimes R1 IS spilt Into two senes resistors each R1- 2. A capacitor Cc IS then placed from the midpoint to ground to further filter
q,V and q,R· The value of Cc should be such that the corner frequency of this network does not significantly affect "'n.
DEFINITIONS: N = Total Division Ratio In feeaback loop
Kq, = VDD/41r for PDout
Kq, = VDD/21r for q,V and q,R
KVCO

= 21rl1fVCO
l1VVCO

for a typical design "'n '" 270fr (at phase detector Input!,

t '"

1

RECOMMENDED FOR READING:
Gardner, Floyd M., Phaselock Techniques (second editioni. New York, Wlley-Intersclence, 1979.
Manassewltsch, Vadim, Frequency Synthesizers: Theory and Design (second editioni. New York, Wiley-Interscience, 1980.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wlley-Intersclence, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wlley-Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983.
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. IndianapoliS, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.

6·67

•

MC145151·1
SWITCHING WAVEFORMS

FIGURE2

FIGURE 1

~r~~------tw~------~-1~r----

tTHL
Any

~R, ~V*

Output

.11

50%\\., _ _ _ _ _ _ _

*f r In phase with tv

FIGURE3

FIGURE 4 -- TEST CIRCUIT

tf

•

Vss

Device
Under
Test

Output

..l.. CL

I-=-

6·68

MC145151·1
FIGURE5
PHASE DETECTOR OUTPUT WAVEFORMS

fR
Reference

lOse

+

RI

fV
Feedback

IflO

+

NI

PD Out

----'n'----------Jn~u,---~-

u
NOTE The Po output state
pm

IS

IS

I

equal to either VOO or VSS when active When not active, the output

determined by the low pass filter capacitor

6-69

IS

high Impedance and the voltage at that

•

MC145151·1
FIGURE 6 - 5 MHz TO 5.5 MHz LOCAL OSCILLATOR CHANNEL SPACING = 1 kHz

Voltage
Controlled
Oscillator

5-55MHz

o 1 1 1 000 1 000= 5 MHz
, 0 1 0 1 1 , 1 1 00= 5 5 MHz

FIGURE 7 - SYNTHESIZER FOR LAND MOBILE RADIO UHF BANDS

•

Transmit 440 0-470.0 MHz

Receive 4186-4486 MHz
(25 kHz Stepsl

... N"" 2384 to 3484
Transmit

=

(Adds 86610
~NVa\uel

60 25CX1 Mtlz

NOTES'
11 fA =41667 kHz, ... R=2410; 21 4 MHz lOW side In)8Ctlon dunng recetVe
21 MC145151-' current dram II! 5 mA for VOD"'S Vdc
3) frequency values shown are for the 440-470 MHz band. Similar n'nplementatlon applIeS to the 406-441 MHz band. For 470-512 MHz. consider refer-

ance oscillator flequency X9 for mixer mJ9Ctlon 819081 190.3750 MHz)

6·70

MC145151·1
CRYSTAL OSCILLATOR CONSIDERATIONS

the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are gUidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations In stray and IC Inputloutput capacitance, and realistiC
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:

The fDIIDwlng Dptlons may be considered to provide a
reference frequency to MDtorola's CMOS frequency synthesizers The most desirable IS discussed first
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-compensated crystal
oscillators ITXCOs) or crystal-controiled data clock
oscillators provide very stable reference frequencies. An
OSCillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSC ,n. In general,
the highest frequency capability IS obtained utiliZing a dlrectcoupled square wave haVing a rall-to-rall IVDD to VSS)
voltage sWing If the OSCillator does not have CMOS logiC
levels on the outputs, capacitive or ac coupling to OSCin
may be used OSCout, an unbuffered output, should be left
floating
For additional Information about TXCOs and data clock
OSCillators, please contact Motorola Inc., Component Products, 2553 N Edgington St , Franklin Park, IL 60131, phone
1312) 451-1000

CL= CinCout +Ca+CO+ Cl·C2
Cin + Cout
Cl + C2
where

Cin
Cout

Ca

Co
Cl and C2

5 pF Isee Figure C)
6 pF Isee Figure C)
5 pF Isee Figure C)
The crystal's holder capacitance
Isee Figure B)
External capacitors Isee Figure A)

The OSCillator can be "trimmed" on-frequency by making
a portion or all of Cl variable The crystal and associated
components must be located as close as possible to the
OSCin and OSCout PinS to minimize distortion, stray
capacitance, stray ,nductance, and startup stabilization time
In some cases, stray capacitance should be added to the
values for C,n and Couto
Power IS diSSipated In the effective series resistance of the
crystal, Re, In Figure B. The drive level specified by the
crystal manufacturer IS the maximum stress that a crystal can
Withstand Without damage or excessive shift In frequency.
Rlln Figure A limits the drive level. The use of Rl may not be
necessary In some cases, I.e. Rl = 0 ohms.
To .verify that the maximum dc supply voltage does not
overdrive the crystal, montlor the output frequency as a
function of voltage at OSCout ICare should be taken to
minimize loading.) The frequency should Increase very
slightly as the dc supply voltage IS Increased. An overdriven
crystal Will decrease In frequency or become unstable With
an Increase In supply Voltage. The operating supply voltage
must be reduced or Rl must be Increased in value If the overdriven condition eXists. The user should note that the
OSCillator start-up time IS proportional to the value of R1
Through the process of supplYing crystals for use with
CMOS Inverters, many crystal manufacturers have
developed expertise In CMOS OSCillator design With crystals
D,scuss,ons With such manufacturers can prove very helpful.
See Table A.

DESIGN AN OFF-CHIP REFERENCE
The user may deSign an off-chip crystal OSCillator uSing ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MCI2061, MC12560, or MC12561 MECL
deVices. The reference signal from the MECL deVice IS ac
co~pled to OSC,n For large amplitude signals Istandard
CMOS logiC levels), dc coupling IS used OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability IS obtained With a direct-coupled square
wave haVing rall-to-rall voltage sWing
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier I a digital Inverter) along With an appropriate crystal may be used to provide a reference source
frequency A fundamental mode crystal, parallel resonant at
the deSired operating frequency, should be connected as
shown In Figure A
For VDD=5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies In

TABLE A - PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp
Crystek Crystal
5tatek Corp

ADDRESS
3605 McCart 5t , Ft Worth, TX 76110
1000 Crystal Dr , Ft Myers, FL 33906
512 N Main 5t , Orange, CA 92668

PHONE
18171921-3013
18131936-2109
17141639-7810

RECOMMENDED FOR READING
Technical NOle TN-24, Statek Corp

D. Kemper, L. ROSine, "Quartz Crystals for Frequency
Control", Electro- Technology, June, 1969

Technical Note TN-7, Statek Corp
E. Hafner, "The PiezoelectriC Crystal Unit - Deflntllons and
Method of Measurement", Proc. IEEE, Vol 57, No 2, Feb,
1969

P. J. OlloWltZ, "A GUide to Crystal Selection", Electronic
Design, May, 1966

6-71

•

MC145151·1
FIGURE A - PIERCE CRYSTAL OSCILLATOR CIRCUIT

r-

I

-----------l
Rf

Frequency
Synthesizer

I

I

L___

_

I
_ _ _ _ _ _ _ ..JI

OSCin

OSCout

R1*
Dt-.---'V\J'\r--'

C1

::r:: ::r::

* May be deleted

C2

In certain cases. See text.

FIGURE B - EQUIVALENT CRYSTAL NETWORKS

•

RS

1


!!,,,, 1.035 5V, \
'i~
9V
~N
gs 1.028
\
1.021
1.014
:;j 1.007
1.000
0.993

h

~ ~ 0.94

.. !S

GRAPH 28 - TOTAL DIVIDE VALUE",e

not to be used for design purposes, but IS mtended as an indication of the Ie's potential performance

6-76

MC145152·1
PIN DESCRIPTIONS
fin (Pin 11 - Input to the positive edge triggered + Nand
+ A counters. fin is typically derived from a dual modulus
prescaler and is AC coupled into Pin 1. For larger amplitude
signals (standard CMOS logic levels) DC coupling may be
used.

the beginning of a count cycle and will remain low until the
+ A counter has counted down from its programmed value.
At this time. modulus control goes high and remains high
until the + N counter has counted the rest of the way down
from its programmed value (N-A additional counts since
both + Nand + A are counting down durin!il the first portion
of the cycle), Modulus control is then set back low. the
counters preset to their respective programmed values. and
the above sequence repeated. This provides for a total programmable divide value (NT) = NoP + A where P and P + 1
represent the dual modulus prescaler divide values respectively for h'gh,and'!ow modulus control levels; N the number
programmed into the + N counter and A the number programmed into the + A counter.

VSS (Pin 21 - Circuit Ground.
VDD (Pin 31 - Positive power supply.
RAO, RA1, RA2 (Pins 4,5, and 6) - These three inputs
establish a code defining one of eight possible divide values
for the total reference divider. The total reference divide
values are as follows:
Reference Addreee

Code
RA2
0
0
0
0
1
1
1
1

N INPUTS (Pins 11 through 20) - The N inputs provide
the data that is preset into the + N counter when it reaches
the count of zero. NO is the least significant digit and N9 is
the most significant. Pullup resistors ensure that inputs left
open remain at a logic one and require only a SPST switch to
alter data to the zero state.

Total
Divide Value

RAl
0
0

RAO
0

1
1

0

128

1

256

0
0

0

1
1.

0

512
1024
1160

1

2048

8

1

64

1

A INPUTS (Pins 23. 21. 22. 24. 25. 10) - The A inputs
define the number of clock cycles of fin that require a logic
zero on the modulus control output. See page 8 for explanation of dual modulus prescaling. The A inputs all have internal pullup resistors that ensure that inputs left open will remain at a logic one.

---.-4--oVCO

Al

=

r = --2"'NR2C
Assuming gain A

IS

very large, then

FI I = R2CS + 1
RICS
s
NOTE. Sometimes Rl is split into two series resistors each Rl + 2 A cepecitor Cc is then placed from the midpoint to ground to further
filter 6V and 6R. The value for Cc should be such that the corner frequency of this network does not significantly affect "'N.
DEFINITIONS: N = Total Division Ratio in feedback loop
KII = VDD/2 ..
KVCO = 2..AfVCO
I!.vVCO
for a typical design "'N .. (211/10) fr (at phase detector input)
~

.. 1

6-77

•

MC145152·1
SWITCHING WAVEFORMS

FIGURE 1

FIGURE2
tTHL
~---VDD

Any
Output

-c
-

Modulus
Control

FIGURE4

FIGURE3

•

.pR . .pV'

~'"''"~_-_-_-_-_-_~_tw_.p~~~~_-_-_-'.Jr-~.'

tf

*f r In phase with tv

FIGURE 5 - TEST CIRCUIT

DeVice
Under
Test

Output

6-78

VSS

MC145152·1
FIGURE 6
PHASE DETECTOR OUTPUT WAVEFORMS

IV
Feedback
(fin +

N)

~R

LJ

U

U

q,V

LOU

U

U

NOTE The PD output state IS approxlmatelv equal to either VOO or VSS when active When not active, the output
voltage at that pin IS determined by the low pass filter capacitor

IS

high Impedance and the

RECOMMENDED FOR READING:
Gardner, Floyd M , Phase/ock Techmques (second edition) New York, Wlley-lntersClence, 1979
Manassewltsch. Vadtm, Frequency Synthesizers: Theory and Design (second edition). New York, Wlley-lntersClence, 1980
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wlley-Interscrence, 1976
Egan, WIlliam F , Frequencv Synthesis by Phase Lock. New York, Wlley-lntersClence, 1981.
Rohde, Ulrich L., Diglral PLL Frequency Synrhesizers Theory and Design. Englewood Chlfs, NJ, Prentice Hall, 1983
Berlin, Howard M., Design of Phase-Locked Loop CircUits, with Expenmenrs. Indianapolis, Howard W Sams and Co .. 1978
Kinley, Harold, The PLL Synrhesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980

6-79

MC145152·1
B. The period of fvco divided by P must be greater than
the sum of the times:
a. Propagation delay through the dual modulus
prescaler.
b. Prescaler setup or release time relative to its
modulus control signal.
c. Propagation time from fin to the modulus control
output for the MC145152-1.
A sometimes useful simplification in the MCl45152-1 programming code can be achieved by choosing the values for
P of 8, 16, 32 or 64. For these cases, the desired value for
Ntotal will result when Ntotal in binary is used as the program code to the ... Nand ... A counters treated in the following manner:
A. Assume the ... A counter contains "b" bits where 2b
= P.
B. Always program all higher order ... A counter bits
above "b" to zero.
C. Assume the ... N counter and the ... A counter Iwith all
the higher order bits above "b" ignored) combined into a single binary counter of 10+ b bits in length. The
MSB of thiS "hypothetical" counter is to correspond
to the MSB of ... N and the LSB is to correspond to
the LSB of - A. The system divide value, Ntotal, now
results when the value of Ntotal 10 binary is used to
program the "New" 10+ b bit counter.

DUAL MODULUS PRESCALING
The technique of dual modulus prescaling is well established as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the approach allows relatively low-frequency programmable
counters to be used as high-frequency programmahll'
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and performance that would otherwise result if a fixed (single
modulusl divider was used for the prescaler.
In dual modulus prescaling, the lower speed counters
must be uniquely configured.. Special control logic is
necessary to select the divide value P or P + 1 in the prescaler
for the required amount of time (see modulus control definitionl. The MC145152-1 contains this feature and can be used
with a variety of dual modulus prescalers to allow speed,
complexity and cost to be tailored to the system requirements. Prescalers having P, P + 1 divide values in the
range of ... 3/ ... 4 to ... 64/ ... 65 can be controlled by the
MC145152-1.
Several dual modulus prescaler approaches suitable for
use with the MC145152-1 are given in Figure 7. The approaches range from the low cost ... 15/ ... 16, MC3393P
device capable of system speeds in excess of 100 MHz to the
MC12000 series having capabilities extending to greater than
500 MHz. Synthesizers featuring the MC145152-1 and dual
modulus prescaling are shown 10 Figures 8 and 9 for two
tYPical applications.

•

FIGURE 7 - HIGH FREQUENCY DUAL MODULUS
PRESCALERS FOR USE WITH THE MCl46152-1

DESIGN GUIDELINES APPLICABLE
TO THE MC145152-1

MCI2009
MC12011
MC12013
MC12015
MC12016
MC12017
*MCl2018
MC3393

The system total diVide value INtotal1 will be dictated by
the application. i.e.
_
frequency into the prescaler
Ntotal - frequency into the phase detector

= N- P + A

* Proposed
N is the number programmed into the ... N counter;.A IS
the number programmed into the ... A counter. P and P + 1
are the two selectable divide ratios available 10 the two
modulus prescalers. To have a range of Ntotal values in sequence, the ... A counter is programmed from zero through
P -1 for a particular valu .. N in the divide N counter. N is
then incremented to N + 1 and the ... A is sequenced from
zero through P -1 again.
There are minimum and maximum values that can be
achieved for Ntotal. These values are a function of P and the
sIZe of the ... Nand ... A counters. The constraint N ~ A
always applies. If Amax = P - 1 then Nmin ~ P -1. Then
Ntotal- min = IP -11 P + A or IP -11 P since A is free to
assume the value of zero.
Ntotal- max = Nmax - P + Amax

440
500
500
225
225
225
520
140

MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz

Min
Min
Min
Min
Min
Min
Min
Typ

introduction

By using two devices, several dual modulus values are achievable:
Modulus

Control

l l *
~~___D_e_vl_ce__A__~r------1~___D_ev_,_ce__B__~r.--Device

Device
B

A

To maXimize system frequency capability, the dual modulus
prescaler's output must go from low to high after each group
of P or P + 1 input cycles. The prescaler should divide by P
when its modulus control line is high and by P + 1 when its
modulus control is low.
For the maximum frequency into the prescaler Ifvco max),
the value used for P must be large enough such that:
A. fvco max divided by P may not exceed the frequency
capability of Pin 1 of the MCI45152-1.

+5/+6
+8/+9
+10/+11
+32/+33
+40/+41
+64/ +65
+ 128/ + 129
+15/+16

MC10131
MC10138
MC10154

MC12009
: 20/ : 21
: 50/ : 51
: 40/ : 41
or
+BO/ +81

MC12011
: 32/ + 33
: BO/ : 81
: 64/ : 65
or
+ 128/ + 129

MC12013
: 40/ : 41
: 100/ : 101
+BO/+81

NOTE: MC12009, MC12011 and MC12013 are pin eqUivalent.
MC12015, MC12016, and MC12017 are Pin equivalent.

6-80

MC145152·1
FIGURE 8 - AIRCRAFT NAV RECEIVER SYNTHESIZER DEMONSTRATES
A LOW COST DUAL MODULUS SYSTEM EMPLOYING THE MCI46152-1

Voo
Lock Detect Signal

RAO

28
LO

R2

c

86.000 -

95.950 MHz

.R~7-<~~R~'~~~
Rl

VCO

.V~8~~~~~~
R2

c~

VOO
Channel Programming
+N= 114 - 127, +A=O -

14

NOTES:
1. fR =50 kHz, + R=64; 22.0 MHz low side injection; NTOTAL= 1720 1919.
2. Using 22.0 MHz for the receiver I.F. demonstrates how the choice of I.F. value can sometimes reduce the number of + N bits that must be
programmed. Using the more common 21.4 MHz I. F. would require six rather than four + N programming inputs .

FIGURE 9 - SYNTHESIZER FOR LAND MOBILE RADIO UHF BAND
COVERAGE DEMONSTRATES USE OF THE MCI46152-1
IN SYSTEMS OPERATING TO SEVERAL HUNDRED MHz

"I"

"0"

"I"

406 - 470 MHz
112.5 kHz Steps)

1-____...2"i7 osc,~SCout

Ref Osc.
128 MHz

MCI45152-1

IOn-Chip Osc.
Optional)

Channel Programming

----------... 641 ... 65 Dual Modulus Prescaler

NOTES:
1. NTOTAL = No 64 + A = 32480 to 37600; N = 507 to 587; A = 0 to 63.
2. fR = 12.5 kHz, + R = 1024 tcode 1011.
3. The pre,ealing approach can be chosen for the apphcauon 10 enhance economy e g .. "ngle chIp MC3393P 10 approXImately 100 MHz.
MCI2011 or MCI2013 wilh dual flop flop 10 approx,malely 250 MHz.
MCI2011 or MCI2013 w,th MC10178 10 over 500 MHz.

6·81

•

MC145152·1
CRYSTAL OSCILLATOR CONSIDERATIONS
The follOWing options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The 1)10st desirable is discussed first.
USE OFA HYBRID CRYSTAL OSCILLATOR
Commercially available temperature>ompensated crystal
OSCillators (TXCOsl or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilIZing a dlrectcoupled square wave having a rail-to-rail (VDD to VSSI
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Products, 2553 N. Edgington SI., Franklin Park, IL 60131, phone
(312) 451-1000 ..

•

DESIGN AN OFF-CHIP REFERENCE
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MCl2060, MC12061, MC12560, or MC12561 MECL
devices. The reference signal from the MECL device is ac
coupled to OSCin. For large amplitude signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability IS obtained with a direct-coupled square
wave having rail-ta-rall voltage swing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverterl along with an appropriate crystal may be used to provide a reference Source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown In Figure A.
For VDD = 5 V: the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies In

the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:

..£!..:.£.

CL = C,nCout + Ca + Co +
Cin + Cout
C1 + C2
where

= 5 pF (see Figure C)
= 6 pF {see Figure CI
5 pF (see Figure C)
Ca
The crystal's holder capacitance
Co
(see Figure B)
C1 and C2
External capacitors {see Figure AI
Cin
Cout

The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray ,nductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Couto
Power is diSSipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified ~" the
crystal manufacturer is the maxi·mum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i.e. R1 =0 ohms.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimIZe loading. I The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an Increase in supply Voltage. The operating supply voltage
must be reduced or R1 must be increased In value If the overdriven condition eXists. The user should note that the
oscillator start-up time IS proportional to the value of R1.
Through the process of supplYing crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS OSCillator deSign with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A.

TABLE A- PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp.
Crystek Crystal
Statek Corp.

ADDRESS
3605 McCart St , Ft Worth, TX 76110
1000 Crystal Dr , Ft. Myers, FL 33906
512 N. Main St , Orange, CA 92668

PHONE
18171921-3013
18131 936·2109
17141639-7810

RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.

D. Kemper, L. ROSine, "Quartz Crystals for Frequency
Control", Electro- Technology, June, 1969.

Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal UnIt- Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.

P. J. Ottowitz, "A GUide to Crystal Selection", Electronic
Design, May, 1966

6·82

MC145152·1
FIGURE A -

PIERCE CRYSTAL OSCILLATOR CIRCUIT

----l

r----Rt

I

Frequency
Synthesizer

I
I
I

I

I
I
I

IL_

.J
OSC aut

C11::. .T
* May

be deleted

In

certain cases See text

FIGURE B -

EQUIVALENT CRYSTAL NETWORKS

RS

1

o---l

C2

LS

Cs

~

01--0
2

Co

Values are supplied by crystal manufacturer (parallel resonant crystal)

FIGURE C -

PARASITIC CAPACITANCES
OF THE AMPLIFIER

a

o

"
--11--------.1-----<0
~

1
1

_L

-T-

1

1
:r:

Cin

1
_.1._

1
-~-

6-83

Caut

•

®

MC14S1SS·1

ItIIOTOROLA

Advance Information
HIGH-PERFORMANCE

CMOS

SERIAL INPUT PLL FREQUENCY SYNTHESIZER
The MC145155-1 is programmed by a clocked, senal Input, 16-blt
data stream. The device features consist of a reference oscillator,
selectable-reference divider, digital-phase detector, 14-blt programmable dlvlde-by-N counter and the necessary shift register and latch CircUitry for accepting the serial Input data. When combined with a loop
filter and VCO, the MC145155-1 can provide all the remaining funcllons
for a PLL frequency synthesizer operating up to the device's frequency
limit. For higher VCO frequency operation, a down mixer or a fixed
divide prescaler can be used between the VCO and MC145155-1.
The MC145155-1 offers Improved performance over the MC145155.
The ac characteristics have been Improved and the input current reqUirements have been modified.

•

• General Purpose Applications'
CATV
Two Way Radios
Scanning Receivers
AM/FM Radios
TV Tuning
Amateur Radio
• Low Power Consumption
• 3.0 to 9.0 V Supply Range
• On- or Off-Chip Reference Oscillator Operation with Buffered
Output
• Compatible with the Serial Penpherallnterface (SPI) on CMOS
MCUs

LOW-POWER COMPLEMENTARY MaS
SILICON-GATE

SERIAL INPUT PLL
FREQUENCY SYNTHESIZER

~ ~

J'V\rINY1f Ui U

II

18

I

1

MCI45155L1

MCI45155Pl

CERAMIC PACKAGE
CASE 726

PLASTIC PACKAGE
CASE 707

PIN ASSIGNMENT

• Lock Detect Signal
• Two Open-Drain SWitch Outputs
• 8 User-Selectable -+- R Values - 16,512, 1024,2048,3668,4096,
6144,8192

18
17

• Single Modulus/Serial Programming
• -+- N Range;3 to 16383
• "Linearized" Digital Phase Detector Enhances Transfer Function
Linearity
• Two Error Signal Options - Single Ended !Three-Statel or Double
Ended
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates

3

16

4

15

6

13

14

12

8

11

10

VDD; Pin 5
VSS;Pln7

BLOCK DIAGRAM
OSCout -,-16,,-_ _-,
OSCin 17

12-81t - R Counter

fin 2,9_ _-+-1

:::---+.---+1

~~;:::;~
1

Data 11IL_ _ _ _ _ _ _ _-.j-'-'--''-'-:"~'_:~':.l-.L-.L-''''-.............
Clock

I

1

J.ll0L_______-l~===============::::.J

ThiS document contains Information on a new product SpeCifications and information herein
are subject to change Without notice

6·84

R
V
SW2
SWI

I I

MC145155·1

MAXIMUM RATINGS* (Voltages Referenced to VSSI

VDD
VIn' Vout
lin, lout

IDD, ISS
PD
Tstg
Tl

Value

Unit

-05to +10

V

Parameter

Symbol
DC Supply Voltage

Input or Output Voltage (DC or Transient)

-05 to VDD+O 5

V

I nput or Output Current (DC or Transient), per Pin

± 10

mA

Supply Current, VDD or VSS Pins

± 30

mA

Storage Temperature

It IS advised that normal precautIons be

500

mW

-65 to + 150

'C

260

'C

Power DISSipation, per Packaget
lead Temperature (8-Second Solderlngl

This device contains circUItry 10 protect
the Inputs against damage due to high
static voltages or electnc fields, however,

taken to avoid applications of any voltage
higher than maximum rated voltages to
this high-Impedance Circuit For proper
operatIon It IS recommended that V In and
Vout be constrained to the range
VSS",IV,n or Voutl",VDD
Unused Inputs must always be tied to
an appropnate logic voltage level (e 9 ,
either VSS or VDDI

* MaXimum

Ratings are those values beyond which damage to the deVice may occur
tPower DISSipation Temperature Deratmg
Plastic "P" Package -12 mW/oC from 65'C to 85'C
Ceramic" L" Package No derating
ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSI

25'C

-40'C

85°C

Symbol

VOO

Min

Max

Min

Typ

Max

Min

Max

Units

VDD

-

3

9

3

-

9

3

9

V

a Level

VOL

3
5
9

-

005
005
005

-

0001
0001
0001

005
005
005

-

005
005
005

V

1 level

VOH

3
5
9

295
495
895

-

295
495
895

2999
4999
8999

-

295
495
895

-

Input Voltage
o level
V out = 05 V or VDD - 0 5 V
(All Outputs Except OSCoutl

Vil

3
5
9

-

-

09
15
27

-

135
225
405

09
15
27

-

09
15
27

1 level

VIH

3
5
9

21
35
63

-

-

165
275
495

-

21
35
63

-

-

21
35
63

3
5
9

080
150
350

-

048
090
210

30
36
60

-

024
045
105

-

3
5
9

-044
-064
-130

-035
-051
-100

-10
-12
-20

-

-022
-036
-070

3
5
9

044
064
130

-

035
051
100

10
12
20

-

-

022
036
070

-

-

±03

-

±O 00001

±01

±50

-

±10

±25

000001

01

-90

-200

6

10

6

10

Characteristic

Power Supply Voltage Range
Output Voltage
VIn=O V or VDD
10ut=0 ~A

Output Current - SW1, SW2
Vout =03V
Sink
Vout =04 V
V out =05V

10l

Output Current - Other Outputs
Vout =27V
Source
Vout =46 V
Vout =85V

10H

Sink

10l

Vout=O 3 V
Vout=O 4 V
Vou t=05V

lin

9

lin

9

IIH

9

III

9

Cin
Cout

-

IDD

3

Input Capacitance
3-State Output Capacitance PD ou !
QUiescent Current
V,n=O V or VDD
10ut=0 ~A
3-State Leakage Current - PDout
Vout=O V or 9 V
Off-State Leakage Current SW1, SW2 - Vout =9 V

-

mA

Input Current -

Input Current - Other Inputs
(With PullupsJ

-

mA

Input Current - Data, Clock
fin. OSC n

-

V

-

10Z

9

-

10Z

9

-

5
9

03
-400
10
10
800
1200
1600

-

-

± 10

~A

±22

~A

10

~A

-170
10

pF

10

pF

1600
2400
3200

~A

±Ol

-

±30

#A

01

-

30

#A

800

200
300
400

1200
1600

±03

-

±O 0001

03

-

00001

6·85

-

-

MC145155·1
SWITCHING CHARACTERISTICS ITA ~ 25"C, CL ~ 50 pFI
Characteristic
Output Rise and Fall Time IF,gures 1 and 71

Propagation Delay Time
Enable to SW1, SW2 IFlgures 2 and 71
Setup Times
Data to Clock I Figure 31

Symbol

VDD

Min

Typ

Max

Units

tTLH,
tTHL

3

-

60
40
30

140

ns

40
25
15

100
40
25

ns

30

12

-

ns

20
18

10
9
30

-

16
12

-

12
12
15

-8
-6
-5

-

5
10
20

-15
-8
0

-

25
20
10

100
60
40

175
100
70

ns

-

20
5
2

5
2
05

~s

40
35
25

30

-

ns

20
15

5
9

tpHL

3

tsu

5
9
3
5

9
Clock to Enable I Figure 31

3
5

9
Hold Time
Clock to Data IFlgure 31

th

3
5

9
Recovery Time

tree

3

5
9

, Enable to Clock I Figure 31
Output Pulse Width
R, V with fR In Phase With fV I Figures 4 and 71

tw

Input Rise and Fall Times

tr,tf

3
5

9
Any Input IF,gure 51

3
5

9
Input Pulse Width, Clock, Enable (Figure 6)

tw

3
5

9

•

6-86

70
32
25

80
60

ns

ns

MC145155·1
GRAPH 1 -

GRAPH 1A -

DSCin AND fin MAXIMUM FREQUENCY VERSUS TOTAL DIVIDE VALUE

VDD~3

GRAPH 1B - VDD~5V

V

~ 16
~

~

~

14
12~+-~-+~~+--~7t~--+-~-+,~--~

~

26

i

22

.l:

24

g
E

.§E

..j"
~

Total OHllde Value

Total DIvide Value
GRAPH 1C -

VDD~9V

•

Total Divide Value

GRAPH 2 -

GRAPH2A - TOTAL

OSCin AND fin MAXIMUM FREQUENCY VERSUS TEMPERATURE FOR
SINE AND SQUARE WAVE INPUTS

DIVIDEVALUE~3,

GRAPH 2B - TOTAL DIVIDE VALUE>:6

4, OR5

1.12
~
1.09
g~ 1.06
..!: ~ 1.03

i!'u

~

3V _
5V
9V

1.063

- --.

;;

".

in 1.00

! c; 0.97

11

u:~

~

.......

~] 0.94

~

~ ~ 0.91

.E

40

-20

20

40

~: ~

E~

'~

60

IS

j~

1\9 V
80

not to be used for design purposes, but

1.021

;~~
:; e 1.014

5V
3V

\

\

",
Ii'\... " ,

"

1.007
1.000
0.993
-40

-20

".

3V
5V
9V

...::.:.
20

40

60

Temperature {OCI

Temperature (OCI

* Data labelled "TYPical"

\

gEl

0.85
0.82
0.79

,
,

1:042

5 V,
g~ 1.035
9V
iii~ 1.028

i'\.,

:;~ 0.88

3V

1.056
1.049

IS

Intended as an indication of the IC's potential performance

6-87

80

MC145155·1
PIN DESCRIPTIONS
RAO, RA1, RA2 (Pins 18, 1, and 21 - These three inputs
establish a code defining one of eight possible divide values
for the total reference divider, as defined by the table below:

Reference Address
Code
RAO
RA2
RAl
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
1
0
1
0
1
1
1
1
1

•

CLOCK, DATA (Pins 10 and 111 - Shift register clock and
data input. Each low-to-high transition clocks one bit into
the on-chip 16-bit shift register. The data is presented on the
DATA input at the time of the positive clock transltion .. The
OAT A input prOVides programming information for the
14-bit + N counter and the two switch signals SWl and
SW2. The entry format is as follows:

Total
Divide
Value
16
512
1024
2048
3668
4096
6144
8192

j4

~

N Counter Bits

co

co

C/l

C/l
...J

:?

z

z

I

·1

t

Last Data Bit in IBlt No. 16)
First

q,V, q,R (Pins 3 and 41 - These phase detector outputs
can be combined externally for a loop error signal. A singleended output is also available for this purpose Isee PDoutl.
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by q,V pulsing
10w.·q,R remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by q,R pulsing
low. q,V remains essentially high.
If the frequency of fV ~ fR and both are in phase, then
both v and R remain high except for a small minimum
time period when both pulse low in phase.

N

~
S
C/l C/l

oat a Bit In

Bit No. 111

ENABLE (Pin 121 - When high 1"1") transfers contents of
the shift register Into the latches, and to the programmable
counter inputs, and the switch outputs SWl and SW2.
When low 1"0") Inhibits the above action and thus allows
changes to be made In the shift register data without affectIng the counter programming and SWitch outputs. An onchip pull-up establishes a continuously high level for
ENABLE when no external signal IS applied to Pin 12 .

SW1, SW2 (Pins 13 and 141 - SWl and SW2 provide
latched open drain outputs corresponding to data bits
numbers one and two. These will typically be used for band
switch functions. A logic one will cause the output to
assume a high-impedance state, while a logic zero will cause
an output logic zero.

VDD (Pin 51 - Positive power supply.
PDout (Pin 61 - Three state output of phase detector for
use as loop error signal. Double-ended outputs are also
available for thiS purpose Isee v and R).
Frequency IV > fR or fV Leading: Negative Pulses.
Frequency fV < fR or fV Lagging: Positive Pulses.
Frequency fV ~ fR and Phase CoinCidence: High-Impedance State.

REFout (Pin 151 - Buffered output of on-chip reference
oscillator or externally prOVided reference-Input signal.

VSS (Pin 71 - Circuit Ground.

OSCout, eSCin IPins 16 and 171 - These pins form an
on-chip reference oscillator when connected to terminals of
an external parallel resonant crystal. Frequency setting
capacitors of appropriate value must be connected from
OSCin to ground and OSCout to ground. OSCln may also
serve as Input for an externally-generated reference signal.
ThiS signal will typically be AC coupled to OSCin, but for
larger amplitude signals Istandard CMOS-logic levels) DC
coupling may also be used. In the external reference mode,
no connection IS required to OSCout.

LD (Pin 81 - Lock detector signal. High level when loop IS
locked IfR, fV of same phase and frequency). Pulses low
when loop is out of lock.
fin (Pin 91 - Input to ... N portion of synthesizer. fin is
typically derived from loop VCO and is AC coupled into Pin·
9. For larger amplitude signals Istandard CMOS Logic levels)
DC coupling may be used.

6·88

MC145155·1
SWITCHING WAVEFORMS

F:GURE 1

FIGURE2

tTHL

r---- VDD

Enable

Any
Output

SW1. SW2

FIGURE3

FIGURE4

~r-~.-------tw¢------~"~r---Data
¢R. ¢V*

~I

' ..
!50_o/<_' _ _ _ _ _ _

tsu
*fr In phase with fv

Clock
VSS

-

Enable

•

VDD

.....- - - - VSS
PrevIous
Data
Latched

FIGURES

FIGURE6

tf

Clock.
Enable

Any Input

J==~tw==~L-VDD
50%

VSS

FIGURE 7 - TEST CIRCUIT

Output
Device

Under
Test

6·89

MC145155·1
PHASE LOCKED LOOP -

LOW PASS FILTER DESIGN

A)

1

F(s) = RI CS + 1

B)

PDout

VCO
Rl

t/>Ro--

R2

t/>Vo--

I

C

C)

•

PDout 0 - -

"'n
t/>RO---~~~~~1

t/>VO---~~V-~r-1

>------<> VCO

Assuming

g81n

A

IS

very large. then.

R2CS + 1

F(s)=~

NOTE- Sometimes Rl IS spltt Into two senes resistors each Rl ..,.. 2. A capacitor Cc IS then placed from the midpoint to ground to further filter
t/>V and t/>R. The value of Cc should be such that the corner frequency of this network does not significantly affect "'n
DEFINITIONS: N = Total DiVISIon RallO In feeoback loop
= VDD/4 .. for PDout
Kt/> = VDD/2 .. for t/>V and t/>R

K.

KVCO

= 2..AfVCO
AVVCO

for a typical design "'n e

t ..

2~ofr

(at phase detector Input!,

1

RECOMMENDED FOR READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, W,ley-Intersc,ence, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second editIon), New York, Wlley-Interscience, 1980
Blanchard, Alain, Phase-Locked Loops: App)ication to Coherent Receiver Design. New York, Wiley-Intersclence, 1976
Egan, W,lliam F., Frequency Synthesis by Phase Lock. New York, W,ley-Intersclence, 1981.
Rohde, Ulrich L" Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolrs, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook, Blue Ridge Summit. PA, Tab Books, 1980.

6·90

MC145155·1
FIGURE 8
PHASE DETECTOR OUTPUT WAVEFORMS

IR
Reference
lOse ~ RI

IV
Feedback
11m ~ NI

Po Out

u
v

I

I

~

I

NOTE: The Po output state IS equal to either VOO or VSS when active. When not active, the output IS high Impedance and the voltage at that

Pin 15 determined by the low pass filter capacitor.

6·91

•

MC145155·1
FIGURE 9 -

TV/CATV TUNING SYSTEM

11

40 MHz
UHF/
VHF
Tuner

Or
CATV
Front

MC12071
Presca(er

End

MC145155-1

C
I

0

n

a
b

0

c

I

k

e
CMOS
MPU/MCU

LED Displays

FIGURE 10 -

•

FM/ AM RADIO SYNTHESIZER

To AM/FM
OSCillators

2.56 MHz

MC3393
FM
OSC

+

MC145155-1

16 Prescaler

o

C
I
o

c

AM
OSC

k

E
n

a
b
I
e

CMOS
MPU/MCU

6·92

1/2 MC1458

To Display

MC145155·1
CRYSTAL OSCILLATOR CONSIDERATIONS

the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are gUidelines that prOVide a reasonable compromise
between IC capaCitance, drive capability, swamping variations rn stray and IC Inputloutput capaCitance, and realistiC
CL values The shunt load capaCitance, CL, presented across
the crystal can be estimated to be

The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers The most desirable

IS

discussed first

USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially avarlable temperature-~ompensated crystal
OSCillators ITXCOsl or crystal-controlled data clock
OSCillators proVide very stable reference frequencies An
OSCillator capable of slnkrng and sourcing 50 I'A at CMOS
logic levels may be direct or dc coupled to OSCrn In general,
the highest frequency capability IS obtarned utilizing a dlrectcoupled square wave having a rall-to-rall IVDD to VSSI
voltage swrng If the OSCillator does not have CMOS logic
levels on the outputs, capacitive or ac couplrng to OSC ,n
may be used OSCout, an unbuffered output, should be left
floating.
For additional Information about TXCOs and data clock
OSCillators, please contact· Motorola Inc., Component Products, 2553 N Edgington S1., Franklin Park, I L 60131, phone
13121451-1000

CL ~ C,nCout + Ca + Co + C1.C2
C,n + Cout
C1 + C2
where

C,n
Cout

Ca
Co
C1 and C2

5 pF Isee Figure C)

6 pF Isee Figure CI
5 pF Isee Figure C)
The crystal's holder capacitance
Isee Figure BI
Extern31 capacitors Isee Figure AI

The OSCillator can be "trimmed" on-frequency by making
a portion or all of C1 variable The crystal and associated
components must be located as close as pOSSible to the
OSCrn and OSCout prns to minimize distortion, stray
capaCitance, stray Inductance, and startup stabrl,zat,on time
In some cases, stray capacitance should be added to the
values for C,n and Cout
Power IS diSSipated In the effective series resistance of the
crystal, Re, In Figure B The drive level speCified 1:'" the
crystal manufacturer IS the maximum stress that a crystal can
Withstand Without damage or excessive shift In frequency
R11n Figure A limits the drive level The use of R1 may not be
necessary In some cases; I e R1 ~ 0 ohms.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout ICare should be taken to
minimize 10adrng.1 The frequency should Increase very
slightly as the dc supply voltage IS Increased An overdrlven
crystal will decrease In frequency or become unstable With
an Increase In supply voltage The operating supply voltage
must be reduced or R1 must be Increased In value If the overdriven condition eXists The user should note that the
OSCillator start-up time IS proportional to the value of R1
Through the process of supplYing crystals for use With
CMOS Inverters, many crystal manufacturers have
developed expertise In CMOS OSCillator deSign With crystals
D,SCUSSions With such manufacturers can prove very helpful
See Table A.

DESIGN AN OFF-CHIP REFERENCE
The user may deSign an off-chip crystal OSCillator uSing ICs
specifically developed for crystal OSCillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference signal from the MECL device IS ac
'coupled to OSC ,n . For large amplitude Signals Istandard
CMOS logiC levelsl, dc coupling IS used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability IS obtained with a direct-coupled square
wave haVing rall-to-rall voltage swrng.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier la digital Inverter} along with an appropriate crystal may be used to proVide a reference source
frequency A fundamental mode crystal, parallel resonant at
the deSired operatrng frequency, should be connected as
shown In Figure A
For VDD~5 V, the crystal should be specified for a
loading capaCitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies In

TABLE A - PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp

Crystek Crystal
Statek Corp

ADDRESS
3605 McCart St , Ft Worth, TX 76110
1000 Crystal Dr , Ft Myers, FL 33906
512 N Main St , Orange, CA 92668

PHONE
18171 921-3013
18131936-2109
17141639-7810

RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp

D Kemper, L ROSine, "Quartz Crystals for Frequency
Control", Electro- Technology, June, 1969

Technical Note TN-7, Statek Corp.
P. J. OttOWltZ, "A GUide to Crystal Selection", Electronic
Design, May, 1966

E Hafner, "The PiezoelectriC Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol 57, No 2, Feb,
1969

6-93

II

MC145155·1
FIGURE A -

r-

I

PIERCE CRYSTAL OSCILLATOR CIRCUIT

-----------l
~

~~~

Synthesizer

I

L___

I
_ _ _ _ _ _ _ ..JI

_

OSCout

o
1:: 1::

Al*

f-...--....J\,/\J"v---'

C1

* May

EQUIVALENT CRYSTAL NElWORKS

AS

I

1

01-0
2

C2

be deleted In certain cases See text

FIGURE B -

<>--l

I

I

I
I

LS

Cs

~
Co

Values are supplied by crystal manufacturer (parallel' resonant crystal)

FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER

~------...,,-----<0
a

Ol---"r---.-,--II-, "

I
I

I

=:r= C,n

:

I

r= Cout
I

_1_

_J._

6-94

®

MOTOROLA

MCl45156-1

Advance Information
HIGH-PERFORMANCE

CMOS

SERIAL INPUT Pll FREQUENCY SYNTHESIZER
The MCl45156-1 is programmed by a clocked, serial input 19-bit data
stream. The device features consist of a reference oscillator, selectablereference divider, digital-phase detector, 10-bit programmable divide-by-N
counter, 7-bit programmable divide-by-A counter and the necessary shift
register and latch circuitry for accepting the serial input data. When combined with a loop filter and VCO, the MC145156-1 can provide all the remaining functions for a PLL frequency synthesizer operating up to the
device's frequency limit. For higher VCO frequency operation, a down
mixer or a dual modulus prescaler can be used between the VCO and
MCl45156-1.
The MC145156-1 offers improved performance over the MC145156.
Modulus Control output drive has been increased and the ac
characteristics have been improved. Input current requirements have also
been modified.
• General Purpose Applications:
Scanning Receivers
CATV
Two-Way Radios
Amateur Radio
AM/FM Radios
TV Tuning
•
•
•
•
•
•
•
•
•

•
•
•

Low Power Consumption
3.0 to 9.0 V Supply Range
On- or Off-Chip Reference Oscillator Operation with Buffered Output
Compatible with the Serial Peripheral Interface (SPII on CMOS MCUs
Lock Detect Signal
Two Open-Drain Switch Outputs
Dual Modulus/Serial Programming
8 User-Selectable -+- R Values - 8, 64, 128, 256, 640, 1000, 1024, 2048
-+- N Range=3 to 1023, -+- A Range=O to 127
"Linearized" Digital Phase Detector Enhances Transfer Function
Linearity
Two Error Signal Options: Single Ended (Three-Statel
Double Ended
Chip Complexity: 6504 FETs or 1626 Equivalent Gates

LOW-POWER COMPLEMENTARY MOS
SILICON-GATE

SERIAL INPUT PLL
FREQUENCY SYNTHESIZER

-,

,

MCI45156L1

MCI45156Pl

CERAMIC PACKAGE
CASE 732

PLASTIC PACKAGE
CASE 738

PIN ASSIGNMENT

RA1
RA2
~V
~R

Voo
Poout
VSS
Mod Control
Lo
fin

RAO
oScin
oseout
REFout
Test
SW2
SW1
Enable
Data
Clock

Lo

REFout
Modulus
Control
~V
~R

SW2
SW1

ThiS document contains Information on a new product. Specifications and Information herein
are subject to change without notice.

6-95

•

MC145156·1
MAXIMUM RATINGS* IVoltages Referenced to VSS}
Parameter

Symbol
VDD
Yin, Vout
lin, lout
100, ISS
Po
Tstg
TL

Value
-0.5 to + 10

DC Supply Voltage
Input or Output Voltage IDC or Transient}
Input or Output Current IDC or Transient}, per Pin

-0.5 to VDD+0.5

Storage Temperature

V.
V·'

This device contains cIrcUItry to protect
the Inputs against damage due to high
static voltages or electric fIelds; however,

it

mA

±1O

Supply Current, VOO or VSS Pins
Power O,ssipation, per Packaget

Unit

IS

advised that normal precautions be

taken to avoId applications of any voltage

±30

mA

higher than

500
-65 to + 150

mW

thIs high-impedance circuit. For proper
operation it IS recommended that VIn and

260

Lead Temperature 18-Second Soldering}

'c
'c

Vout

be

maxlmwm rated voltages to

constrained

to

the

range

VSSsIV,n or Vout}sVOO.
Unused Inputs must always be tied to
an appropriate logic voltage level le.g •
either VSS or VOOI.

* Maximum Ratings are those values beyond which damage to the device may occur.
tPower Dissipation Temperature Derating:

Plastic "P" Package: -12 mW/'C from 65°C to 85°C
Ceramic" L" Package: No derating

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSS}
-40 0 C
Characteristic
Power Supply Voltage Range
Output Voltage
Vin=O V or VDO

o Level

Symbol

VDD

Min

VOO
VOL

3
5
9

10ut~0 ~A

1 level

VOH

3
5
9

•

Input Voltage
o level
Vou t=0.5 V'or VOb-0.5 V
IAII Outputs Except OSC out }

Vil

1 level

VIH

Output Current
Vou t=27V
V ou t=4.6 V
Vou t=8.5 V
Vou t=0.3V
Vou t=O.4 V
V out =0.5 V
Output Current
Vout=O 3 V
Vou t=O.4 V
Vout =O.5 V
Output Current
Vou t=2.7V
Vou t=4.6 V
Vou t=8.5 V
Vout =0.3V
Vou t=O.4 V
Vou t=0.5 V
Input Current -

- Modulus Control
Source

Sink

- SW1, SW2

3,

25°C
Typ

85°C

-

Max
9

-

0001
0001
0001

0.05
005
005

-

2.95
4.95
895

-

0.9
1.5
2.7

-

-

2999
4999
8999
135
225
4.05

2.1
35
6.3

3

Max
9

Min
3

-

005
0.05
0.05

295
4.95
895

-

Min

3

-

Max
9

Units
V
V

-

0.05
005
005

-

295
495
8.95

-

09
15
27

-

09
15
27

1.65
275
4.95

--

21
35
6.3

-

-0.50
-075
-125

-15
-2.0
-3.2

-0.30
-050
-080

-

1.10
1.70
3.30

50
6.0
100

-

-

0.24
045
105

-

-022
-036
-0.70

-

5
9

-

3
5
9

2.1
3.5
6.3

-

3
5
9

-060
-0.90
-1.50

-

3
5
9

1.30
1.90
3.80

3
5
9

0.80
1.50
3.50

-

0.4E
0.90
2.10

30
3.6
60

-

3
5
9

-0.44
-0.64
-1.30

-

-0.35
-0.51
-1.00

-10
-1.2
-2.0

-

3
5
9
9

0.44
0.64
1.30

0.35
0.51
1.00

10
12
2.0

-

-

±O.OOOOI

±01

±10
0.00001

±25
01

-90

-200
10
10

-

-

mA

10H

10l

-

066
108
210

mA

10L
Sink

- Other Outputs
Source

Sink

Data, Clock

Input Current - fin, OSC' n
Input Current - Other Inputs
(with Pullups)
Input Capacitance
3-State Output Capacitance POo t
Quiescent Current
Vin'=O V or VOO
10'ut=0 pA
3-State leakage Current - PO out
Vout=O V or 9 V
Off-State Leakage Current SW1, SW2 - Vou t=9 V

-

-

mA

10H

10l

-

-

lin
I

9
9

-

III

9

-

-400

Cin
Cout

-

-

6

-

10
10

-

-

-

6

100

3
5
9

800
1200
1800

10Z

9

-

±03

-

200
300
400
±O.oool

10Z

9

-

0.3

-

0.0001

lin

V

±0.3
±50
0.3

6·96

-

0.22
0.36
0.70

-

-

±10

~A

±22
1.0

~A
~A

-170
10
10

pF
pF

1800
2400
3200

~A

±0.1

-

±30

~A

0.1

-

3.0

~A

800
1200
1500

MC145156·1

SWITCHING CHARACTERISTICS ITA = 25'C CL = 50 pFI
Characteristic
Output A,se Time, Modulus Control IFlgures 1 and 71

Output Fall Time, Modulus Control IFlgures 1 and 71

Symbol

VOO

Min

Typ

Max

Units

tTLH

3

-

50

ns

5
9

-

30
20

115
60
40
60

ns

tTHL

3
5

9
Output Alse and Fall Time, LD, q,V, q,A IF,gures 1 and 71

tTLH,
tTHL

Propagation Delay Time

fin to Modulus Control (Figures 2 and 71

3
5

-

3
5

-

tPHL

3
5

tsu

3
5

9
Clock to Enable IFigure 31

3
5

9
Hold Time

th

Clock to Data IF,gure 31

3
5

9
Recovery TIme

tree

Enable to Clock {Figure 31

3
5

9
Output Pulse Width
q,A, q,V with fA In Phase With fV (Figures 4 and 71

twq,

Input Alse and Fall Times
Any Input {Figure 51

tr,tf

3

5
9
3

5
9

Input Pulse Width, Enable, Clock {Figure 61

tw

3
5

9

6-97

-

9

9
Setup Times
Data to Clock {Figure 31

-

tpLH,
tpHL

9
Propagation Delay Time
Enable to SW1, SW2 (Figures 2 and 71

-

25
17
15

50
40
30

34
30
140
80
60

ns

ns

55
40
25

125

-

40
25
15

100
40
25

ns

30
20
18

12
10

ns

70
32
25

30
16
12

-

12
12
15

-8
-6
-5

ns

5
10
20

-15
-8
0

-

25
20
10

100

ns

40

175
100
70

-

20
5
2

5
2
05

~s

40
35
25

30
20
15

-

ns

9

80

80

50

ns

•

MC145156·1
GRAPH 1 - OSCin AND fin MAXIMUM FREQUENCY VERSUS TOTAL DIVIDE VALUE
GRAPH lA - VDD=3V

GRAPH 18 - VDD=5V

~ 16~~-±~~~~--~-t~~~~--r.'-r-+~

~
>

14

112r--r~r-~-1--+-~~t--+--t--r--~'-r~--1
j 10r-~~~~~L-~~--t--+--t-~--~'-r~--1
j
j
Total Divide Value

Total Divide Value
GRAPH lC - VDD=9 V

~. 2S~-t~~~~r-~~--~-+--+--+--~·~--t-~

~ 26
(

24r-~~r--r-1r-1=~~~-+--+--+--t-·~--t-~

! 22~+-~~-+~--~+-~-+-+~~~~+-~

·f 20~+-+-+-+-_-:':'"
8-

•

j

j
Total Divide Value

GRAPH 2 - OSCin AND fin MAXIMUM FREQUENCY VERSUS TEMPERATURE FOR
SINE AND SQUARE WAVE INPUTS

GRAPH 28 - TOTAL DIVIDE VALUE;,:6

GRAPH2A - TOTAL DIVIDE VALUE = 3, 4, OR 5

1.11

3V _
1.09
!~ 1.06 5V
..;: ~ 1.03 9V
.~~ 1.00
0.97
~

- ---

1;

"
I""" ~

! c;

......

~ ~ 0.94

I~
J:::::
go",
~

~ ~ 0.91
0.S5
0.81
0.79

Eal

r". ~

~~

" '.
,

.c~ 0.88

}

i:ri
~N
c!'S

-40

-20

20

40

so

"

~m

5V
3V

j~

I
1\9 V

so

,

-40

-20

"

3V
5V

~

9V
20

40

60

Temperature (OC)

Temperature (OCI

* Data labelled "Typical"

1.063
3V
1.056
\
1.049
,
1.042
5 V. \
1.035
9V
i\
1.028
\ ,
1.021
I"\.. " ,
1.014
:"-.
1.007
1.000
0.993

is not to be used for deSIgn purposes, but

IS

Intended as an indicatIon of the lC's potential performance

6-98

80

MC145156·1
LD (Pin 9) - Lock detector signal. High level when loop is
locked IfR, fV of same phase and frequencyl. Pulses low
when loop is out of lock.

PIN DESCRIPTIONS
RAO, RA1, RA2 (Pins 20,1, and 2) - These three inputs
establish a code defining one of eight possible divide values
for the total reference divider, as defined by the table below:
Reference Address
Code
RAl
RAO
RA2
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

fin (Pin 10) - Input to the positive edge triggers" Nand
... A counters. fin is typically derived from a dual modulus
prescaler and is AC coupled Into Pin 10. For larger amplitude
signals Istandard CMOS logic levels) DC coupling may be
used.

Total
Divide Value
8
64
128
256

CLOCK, DATA (Pins 11 and 12) - Shift register clock and
data input. Each low-to-high trans"ion clocks one bit into
the on-chip 19-bit shift register. The data is presented on the
DATA input at the time of the positive clock transition. The
DATA input provides programming information for the
10-bit ... N counter, the 7-bit .. A counter and the two
switch signals SWl and SW2. The entry format is as
follows:

640
1000
1024
2048

t/>V, t/>R (Pins 3 and 4) - These phase detector outputs
can be combined externally for a loop error signal. A singleended output is also available for this purpose Isee PDout).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by t/>V pulsing
low. t/>R remains essentially high.
If the frequency fV is less than fR or If the phase of fV is
lagging, then error information is provided by t/>R pulsing
low. t/>V remains essentially high.
If the frequency of fV = fR and both are in phase, then
both t/>V and t/>R remain high except for a small minimum
time period when both pulse low in phase.

~ A Counter Bits ~..
ID

. N Counter Bits

IDID

ID

(f)

(f)(f)

(f)

-'
4:

:2:-'
4: 2

:2:

+

2

+ +

N~

s:s:

(f)(f)

1·

t Last Data Bit In IBit No. 16)
First Data Bit In IBlt No. l)J
ENABLE (Pin 13) - When high 1"1") transfers contents of
the shift register into the latches, and to the programmable
counter inputs, and the switch outputs SWl and SW2.
When low 1"0") inhibits the above action and thus allows
changes to be made in the shift register data without affecting the counter programming and switch outputs. An onchip pull-up establishes a continuously high level for
ENABLE when no external Signal is applied to Pin 13.

VDD (Pin 5) - Positive power supply.
PDout (Pin 6) - Three state output of phase detector for
use as loop error signal. Double-ended outputs are also
available for this purpose Isee t/>V and t/>R)'
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: HighImpedance State

SW1, SW2 (Pins 14 and 15) - SWl and SW2 provide
latched open drain outputs corresponding to data bits
numbers one and two. These will typically be used for band
switch functions. A logic one will cause the output to
assume a high-impedance state, while a logic zero will cause
an output logic zero.

VSS (Pin 7) - Circuit Ground.
MODULUS CONTROL (Pin 8) - Signal generated by the
on-chip control logic circuitry for controlling an external dual
modulus prescaler. The modulus control level will be low at
the beginning of a count cycle and will remain low until the
... A counter has counted down from its programmed value.
At this time, modulus control goes high and remains high
until the ... N counter has counted the rest of the way down
from its programmed value (N - A additional counts since
both <- Nand .. A are counting down during the first portion
of the cycle). Modulus control is then set back low, the
counters preset to their respective programmed values, and
the above sequence repeated. This provides for a total programmable divide value INTI = N. P + A where P and P +
1 represent the dual modulus prescaler divide values respectively for low and high modulus control levels; N the number
programmed into the .. N counter and A the number programmed into the ... A counter.

TEST (Pin 16) - Used in manufactUring. Must be left
open or tied to VSS.
REFout (Pin 17) - Buffered output of on-chip reference
oscillator or externally provided reference-input signal.
OSCout, OSCin (Pins 18 and 19) - These pins form an
on-chip reference oscillator when connected to terminals of
an external parallel resonant crystal. Frequency setting
capacitors of appropriate value must be connected from
OSCin to ground and OSCout to ground. OSCin may also
seNe as input for an externally-generated reference signal.
This signal will typically be AC coupled to OSCin, but for
larger amplitude signals (standard CMOS-logic levels) DC
coupling may also be used. In the external reference mode,
no connection is required to OSCout.

6·99

•

MC145156·1
SWITCHING WAVEFORMS

FIGURE2

FIGURE 1

tTHL
VDD

Any
Output

Input
- VSS

\

Output

FIGURE4

FIGURE3

R'V*~

Data
VSS
tsu

tw

*frlnphasewithfv

t
r-

Clock
VSS
-

Enable

VDD
VSS

II

PrevIous
Data
Latched

FIGURE5

FIGURE6

~~~-------tw

tf

E~~~~~50%

Any
Input

LVDD
VSS

FIGURE 7 - TEST CIRCUIT

Device
Under
Test

Output

6·100

MC145156·1
PHASE LOCKED LOOP - LOW PASS FILTER DESIGN

AI

r

=

N"'n
2KRo--

R2

r = 0.5"'n fR2C + __N_ _\

vo--

'\

I

C

F(sl =

el

KR

o - - - W........-+-.-----I

Vo---VV~-._~

c

>----oVCO

Assuming gain A is very large, then:

I

NOTE: Sometimes R1 IS spilt Into two senes resistors each R1 - 2. A capacitor Cc IS then placed from the midpoint to ground to further filter
 = YDD/4... for PDout
K = YDD/2... for R
KyCO = 2...~fyeO
~YVCO

for a tYPical design Wn ==

r

2~Ofr

(at phase detector Input),

a 1

RECOMMENDED FOR READING:
Gardner, Floyd M , Phaselock Techniques Isecond edltionl. New York, Wiley-Inlersclence, 1979.
Manassewltsch, Vadlm, Frequency Synthesizers: Theory and Design (second edition). New York, Wlley-Interscience, 1960.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Intersclence, 1976
Egan, Wilham F., Frequency Synthesis by Phase Lock. New York, W,ley-Intersc,ence, 1961.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hail, 1983
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.

6·101

•

MC145156·1
FIGURES
PHASE DETECTOR OUTPUT WAVEFORMS

fR
Reference
(Osc

+

RI

IV
Feedback

(lin

+

NI

PD Out

4>R

--~n~~n~~u~---+---

u

I

4>v

•

NOTE: The PD output state is equal to either VDD or VSS when active. When not active. the output

pin is determined by the low pass filter capacitor.

6-102

IS

high impedance and the voltage at that

MC145156·1
DUAL MODULUS PRESCALING

B. The period of fvco, divided by P, must be greater than
the sum of the times:
a. Propagation delay through the dual modulus
prescaler.
b. Prescaler setup or release time relative to its
modulus control signal.
c. Propagation time from fin to the modulus control
output for the MC145156.
A sometimes useful simplification in the MCl45156 programming code can be achieved by choosing the values for
P of 8, 16, 32, 64 or 128. For these cases, the desired value
for Ntotal will result when Ntotal in binary is used as the program code to the ... Nand ... A counters treated in the
following manner:
A. Assume the ... A counter contains "b" bits where 2b
= P.
B. Always program all higher order + A counter bits
above "b" to zero.
C. Assume the ... N counter and the + A counter (with all
the higher order bits above "b" ignored) combined into a single binary counter of 10 + b bits in length. The
M SB of this "hypothetical" counter is to correspond
to the MSB of + N and the LSB is to correspond to
the LSB of ... A. The system divide value, Ntotal, now
results when the value of Ntotal in binary is used to
program the "New" 10+ b bit counter.

For the following text, the dash number has been omitted
from the part number for simplicity.
The technique of dual modulus prescaling is well established as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the approach allows relatively low-frequency programmable
counters to be used as high-frequency programmable
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and performance that would otherwise result if a fixed (single
modulus) divider was used for the prescaler.
In dual modulus prescaling, the lower speed counters
must be uniquely configured. Special control logic is
necessary to select the divide value P or P + 1 in the prescaler
for the required amount of time (see modulus control definitionl. The MCl45156 contains this feature and can be used
with a variety of dual modulus prescalers to allow speed,
complexity and cost to be tailored to the system requirements. Prescalers having P, P + 1 divide values in the
range of +3/+4 to +12B/+129 can be controlled by the
MC145156.
Several dual modulus prescaler approaches suitable for
use with the MCl45156 are given in Figure 9. The approaches range from the low cost + 15/ + 16, MC3393P
device capable of system speeds in excess of 100M Hz to the
MCl2000 series having capabilities extending to greater than
500 MHz. Synthesizers featuring the MCl45156 and dual
modulus prescaling are shown in Figures 10 and 11 for two
typical applications.

FIGURE 9 - HIGH FREQUENCY DUAL MODULUS
PRESCALERS FOR USE WITH THE MCl46156
MC12009
MCI2011
MCI2013
MC12015
MC12016
MCI2017
*MCl2018
MC3393

DESIGN GUIDELINES APPLICABLE
TO THE MC146156
The system total divide value (Ntotall will be dictated by
the application. i.e.
=
frequency into the prescaler
N P A
N
total
frequency into the phase detector = • +
N is the number programmed into the ... N counter; A is
the number programmed into the + A counter. P and P + 1
are the two selectable divide ratios available in the two
modulus prescalers. To have a range of Ntotal values in sequence, the + A counter is programmed from zero through
P - 1 for a particular value N in the divide N counter. N is
then incremented to N + 1 and the + A is sequenced from
zero through P - 1 again.
There are minimum and maximum values that can be
achieved for Ntotal. These values are a function of P and the
size of the + Nand ... A counters. The constraint N '" A
always applies. If Amax = P -1 then Nmin '" P - 1. Then
Ntotal- min = IP -1) P + A or IP -1) P since A is free to
assume the value of zero.

: 5/ : 6
+8/+9
+10/+11
+32/+33
+40/+41
+64/ +65
+ 128/ + 129
+15/+16

440
500
500
225
225
225
520
140

MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz

Min
Min
Min
Min
Min
Min
Min
Typ

* Proposed introduction

By using two devices several dual modulus valUes are achievable:
Modulus
Control

==*;!l *
+-1..---~~IH
Device A

Device
Device
B
MCI2009
A
+20/+21
MC10131
+50/+51
MC1013B
+40/ +41
or
MC10154
+80/+81

Ntotal- max = Nmax • P + Amax
To maximize system frequency capability, the dual modulus
prescaler's output must go from low to high after each group
of P or P + 1 input cycles. The prescaler should divide by P
when its modulus control line is high and by P + 1 when its
modulus control is low.
For the maximum frequency into the prescaler Ifvco max),
the value used for P must be large enough such that:

Device B

r---

MCI2011
MC12013
+401 +41
+32/ +33
+BO/ +Bl +1001 +101
+64/+65
or
+80/+81
+128/ +129

NOTE: MC12009, MCI2011 and MC12013 are pin equivalent
MC12015, MCI2016, and MCl2017 are pin eqUivalent.

A. fvco max divided by P may not exceed the frequency
capability of Pin 10 of the MCl45156.

6-103

•

•

3:
o.....
~
en
.....

FIGURE 10 - AVIONICS NAV AND COM SYNTHESIZER

en

cp

.....

3.2 MHz

0

VCO Range
Lock Oetect Signal

NAV: 97.300-107.250 MHz
COM-T: 118.()()o'l35.975 MHz
COM-R: 139.400-157.375 MHz

::J::
19

+V

OSCin

18
oseout

POout~6

5 VOO
7 VSS
17

MCl45156-1

il>A 4

VCO
i/lv 3

REFout
Clock
111

Oata

Enable

.12

113

q>

......

:r:

~
R/T

MC10131
Dual FIF
Channel
Selection

To
Oisplay

--....

....

-----~------

+401 +41 Dual Modulus Prescaler

NOTES:
1) for NAV: FA =50 kHz,+ A =64 using 10.7 MHz lowside injection, Ntotal= 1946-2145
for COM-T FA=25 kHz,+R=l28 using 21.4 MHz highside injection, Ntotal=4720-5439
for COM-R FA =25 kHz,+ A= 128 using 21.4 MHz highside injection, Ntotal=5576-6295
2) A + 321 + 33 dual modulus approach is provided by substituting an MC12011 1+81 + 9) for the MC12013 .. The devices are pin equivalent.
3) A 6.4 MHz oscillator crystal can be used by selecting + R = 128 Icode 0101 for NAV and + R =256 Icode 011) for COM

s:

o...a.
~

C11
...a.
C11

~

...a.
FIGURE 11 - FMI AM BROADCAST RADIO SYNTHESIZER

~----+~

Lock Detect
Signal

.....

.. FM B+

.....

.. AM B+

Optional
Loop
Error Signal

~

--"

a

0'1

R~

-= 1~7REFaut

MC145155-1

V~

5 VDD

Mod Control

7 VSS
11
eT
I

IL--o--,

=:c

Dt12 E+13

a
t

a

~

n
a
b
I

e

To
Display

NOTE 1:
for FM: channel spacing = 25 kHz, + R= + 128 Icade 0101
for AM: channel spacing = 5 kHz, + R= +640 Icode 1001

•

-

veo

MC145156·1

CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency syn.
thesizers. The most desirable is discussed first.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-compensated crystal
oscillators (TXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 /LA at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-ta-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Praducts, 2553 N. Edgington S1., Franklin Park, IL 60131, phone
(312) 451-1000.

•

DESIGN AN OFF-CHIP REFERENCE
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference Signal from the MECL device is ac
co~pled to OSCin. For large amplitude Signals (standard
CMOS logic levelsl, dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD = 5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
TABLE A -

CL = CinCout + Ca + CO+ ~
Cin+ Cout
C1 + C2
where

= 5 pF (see Figure C)
= 6 pF (see Figure C)
= 5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
External capacitors (see Figure A)
C1 and C2

The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Cout.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified by the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in. some cases; i.e. R1 =0 ohms.
To verify that the maximum de supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout .. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A.

PARTIAL LIST OF CRYSTAL MANUFACTURERS

NAME
United States Crystal Corp.
Cryst8k Crystal
Statek Corp.

the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented acrOSS
the crystal can be estimated to be:

ADDRESS
3605 McCart St" Ft. Worth, TX 76110
1000 Crystal Dr., Ft. Myers, FL 33906
512 N. Main St., Orange, CA 92668

PHONE
18171 921-3013
18131 936-2109
(714) 639-7810

RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.

D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro- Technology, June, 1969.

Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.

P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
.

Design, May, 1966.

6-106

MC145156·1

FIGURE A -

r-

PIERCE CRYSTAL OSCILLATOR CIRCUIT

-----------l
Rt

I
I
I

Frequency
Synthesizer

I

I

I
IL

I
I
_ _ _ _ _ _ _ _ -1

__ _

OSC out

R1*

DI--i---JVv'v--l

C1T T
* May

be deleted In certain cases See text

FIGURE B -

EQUIVALENT CRYSTAL NETWORKS

RS

1

o---i

01--0
2

C2

LS

Cs

~

1

Co

Values are supplied by crystal manufacturer (parallel resonant crystal)

FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER

Bf>o
a

0--,1-----11-1

-------,Ir----O

II

I

=;:= Cin

1
1

=;:= ~out

1

1

-~

~-

6-107

Re

Xe

2

~

®

MC145157·1
MC145158-1

MOTOROLA

Advance Information

HIGH· PERFORMANCE

CMOS
SERIAL INPUT PLL FREQUENCY SYNTHESIZERS
The MC145157-1 and MC145158-1 have fully programmable 14-bit
reference counters, as well as fully programmable -+- N (MC145157-1)
and -+- NI -+- A (MC145158-1) counters. The counters are programmed
serially through a common data input and latched into the appropriate
counter latch, according to the last data bit (control bit) entered.
When combined with a loop filter and VCO, these devices can provide all the remaining functions for a PLL frequency synthesizer
operating up to the device's frequency limit. For higher VCO frequency
operation. a down mixer or a fixed-divide prescaler can be used
between the VCO and the PLL for the MC145157-1 and a dual-modulus
prescaler for the M C145158-1 .
The MC145157-1 and MC145158-1 offer Improved performance over
the MC145157 and MC145158. Modulus Control output drive has been
increased and the ac characteristics have been improved. Input current
requirements have also been modified.

•

LOW-POWER COMPLEMENTARY MOS
SILICON-GATE

SERIAL INPUT PLL
FREQUENCY SYNTHESIZER

~

J~f~~0nnr II u
1

...
l~N~n( 1f 111111
1

MC145157L1
MC145158L1

MC145157P1
MC145158P1

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648

• General Purpose Applications:
CATV
AMIFM Radios
Two-Way Radios
TV TUning
Scanning Receivers
Amateur Radio
• Low Power Consumption
• 3.0 to 9.0 V Supply Range
• Fully Programmable Reference and -+- N Counters
PIN ASSIGNMENT

•
•

-+- R Range= 3 to 16383
-+- N Range= 3 to 16383 for the MC145157-1
= 3 to 1023 for the MC145158-1
• Dual Modulus Capability for the MC145158-1
-+- A Range= 0 to 127

MC145157-1

• f v and f r Outputs
• Lock Detect Signal
• Compatible with the Serial Penpheral Interface (SPJ) on CMOS
MCUs
• "Lineanzed" Digital Phase Detector
• Single-Ended (Three-State) or Double-Ended
Outputs

Phase

Detector

asc,n

q,R

aSCout

q,V

Iv

REFout
IR

VDD
PDout

SIRout

VSS

Enable

LD

Data

tin

Clock
MC145158-1

ascin

q,R

aSCout

q,V
REF out

Iv

IR

VDD

Modulus

PDout
VSS

ThiS IS advance information and speCifications are subject to change Without notice

6·108

Control

11

Enable

LD

Data

lin

Clock

MC145157·1, MC145158·1
MCl46157-1

13 fR

+_+-r

Enable.;.1.:..1_ _ _ _ _ _

LO
OSC In .;.1_ _ _-+I
2
OSCout ...14"----'~:-i
REFout-'-'-----<><.

Clock.::9~_ _ _ _ _ _ _ _ _ _ _ _......_ _ _ _ _ _ _ _ _ _~

MCl46158-1

Enable

•

+---------lI.r"""':"':""~~i

VOO= Pin 4
VSS=PIn6

6-109

MC145157·1, MC145158·1
MAXIMUM RATINGS* IVoltages Referenced to VSSi
Parameter
Symbol
VOO
Vin, Vout
1m. lout

100, ISS
Po
TstQ

h

Value
-05to+l0

Unit
V

-05 to VOO+0.5
±10

rnA

DC Supply Voltage
Input or Output Voltage IDC or Transienti
Input or Output Current IDC or Transienti, per Pin

Storage Temperature

V

It IS adVised that normal precautions be

taken to avoId applications of any voltage
hIgher than maxImum rated voltages to

±30

mA

500

mW

-65 to + 150

'C

260

'C

Supply Current, VOO or VSS Pins
Power Dissipation, per Packaget

Lead Temperature IS-Second Solderlngi

ThiS device containS CirCUItry to protect
the Inputs against damage due to high
static voltages or electric fields, however,

thiS high-impedance CircUIt. For proper

operation
Vout

be

It IS

recommended that V," and

constrained

to

the

range

VSSslVin or VoutisVOO·
Unused Inputs must always be tied to
an appropriate logic voltage level le.g ..
either VSS or VOOI.

* Maximum Ratl{lgs are those values beyond which damage to the device may occur
tPower Dissipation Temperature Derating:
Plastic "P" Package. -12 mW/'C from 65'C to 85'C
Ceramic" L" Package: No derating

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSi

-40°C

85°C

VOO

Min

Max

Min

Typ

Max

Min

Max

Un~s

VOO

-

3

3

-

3
5
9

-

-

0001
0.001
0.001

9
0.05
0.05
005

3

VOL

9
0.05
005
0.05

-

9
0.05
0.05
0.05

V
V

Vo.H

3
5
9

2.95
4.95
8.95

-

2.95
495
8.95

2.999
4999
8.999

-

295
4.95
8.95

-

Input Voltage
a Level
Vou t=0.5 V or VOO-O 5 V
IAII Outputs Except OSCoutl

VIL

3
5
9

-

0.9
15
27.

-

0.9
15
2.7

-

-

1.35
225
4.05

-

0.9
15
2.7

1 Level

VIH

3

-

9

21
35
63

21
35
6.3

165
275
495

-

21
35
6.3

-

3
5
9

-060
-0.90
-1.50

-

-15
-2.0
-32

-

3

130
1.90
390

-

110
1 70
330

50
60
10 a

-

-0 30
-0.50
-080

-

-

-050
-0.75
-1.25

-044
-0.64
-130

-

-035
-0.51
-100

-10
-1.2
-20

-

-022
-036
-070

044
0.64
130

-

035
0.51

-

1.ad

1.0
12
2.0

022
0.36
070

-

±0.3

-

+0.00001

+0.1

±50
10

-

+10

-

6

+25
10

6

10

-

200
300
400

1200
1600

±O.OOOl

±01

Output Voltage
Vin=O V or VOO
10ut=0 ~A

o Level
1 Level

•

25°C

Symbol

Characteristic
Power Supply Voltage Range

5
Output Current Vou t=2.7 V
Vou t=46V
Vou t=8.5 V

Modulus Control

10L

5

-

9

-

066
108
210

mA

3

5
9

lin

9

Input Current - fin. OSCin

lin
C,n

9

3

5
9

Cout
100

3

5
9
10Z

V

-

10H

10L

3-State Output Capacitance POout
QUiescent Current
VIn=O V or VOO
10ut=0 ~A
3-State Leakage Current - POout
Vout=O V or 9 V

-

-

mA

Sink
Vout=O 3V
Vou t=O.4 V
Vou t=05V
Input Current - Data, Clock, Enable
Input Capacitance

-

-

-

10H

Source

Sink
Vou t=0.3V
Vout=O 4 V
Vou t=05V
Output Current - Other Outputs
Source
Vou t=27V
Vou t=46V
Vou t=8.5 V

-

9

-

-

10

800
1200
1600
±03

6·110

-'

-

800

-

-

± 1.0

~A

+22
10

~A

10

pF

-

1600
2400
3200

~A

±30

~A

pF

MC145157·1, MC145158·1

SWITCHING CHARACTER IS ilCS (T A = 25°C CL = 50 pFI
Characteristic
Output Rise Time, Modu(us Control (Figures 2 and 81

Output Fall Time, Modulus Control (Figures 2 and 81

Symbol

VOO

Min

Typ

Max

Units

tTLH

3
5

-

50

ns

-

30

9

-

20

115
60
40

25
17
15

60
34
30

ns

60
40
30

140
80
60

ns

55
40
25

125
80
50

ns

30
20
18

12
10

-

ns

9

70
32
25

30
16
12

-

12
12
15

-8
-6
-5

5
10
20

-15
-8
0

25
20
10

100

40
35
25

30

-

20
15

-

tTHL

Output Rise and Fall Time, LD, lV, IR, S/R out , rl>V, rl>R (Figures 2 and 81

tTLH,
tTHL

3
5

9

-

3
5

--

9
Propagation Delay Time
fm to Modulus Control (Figures 3 and 8)

tpLH,
tPHL

3
5

9
Setup Times

tsu

Data to Clock (Figure 41

3
5

9
Clock to Enable (Figure 41

3
5

9
Hold Time
Clock to Data (Figure 41

th

3
5

9
Recovery Time

tree

Enab(e to Clock IFlgure 41

3
5

9
Output Pulse Width
rl>R, rl>v with IR In Phase with IV IF,gures 5 and 81

tWrI>

Input Rise and Fall Times

tr, II

3
5

9
Any Input (Figure 61

3
5

9
Input Pulse Width, Enable, Clock (Figure 71

tw

3
5

9

6-111

-

-

_.

-

ns

ns

40

175
100
70

20
5
2

5
2
05

~s

60

-

ns

ns

•

MC145157·1, MC145158·1
GRAPH 1 - OSCin AND fin MAXIMUM FREQUENCY VERSUS TOTAL DIVIDE VALUE

GRAPH lA - VDD=3V

GRAPH 18 - VDD=5V

~ 16r-~~~f--4--~-+--+--+--t.,~--f-.'~~~
~

i

!go

14r--r__r-4--;__~~-7~-+__t-~__f_"~-4~

12r-1--+--+-~-1~~~-1~~-+--~'4--+--1

E 10r-~~b-~~~~~--+--+--t-~--f-"~-4~
g
~

~

j
Total DIvide Value

Total Divide Value
GRAPH lC - VDD=9 V

•

Total DIvide Value

GRAPH 2 -

OSCin AND fin MAXIMUM FREQUENCY VERSUS TEMPERATURE FOR
SINE AND SQUARE WAVE INPUTS

GRAPH 28 - TOTAL DIVIDE VALUE",6

GRAPH2A - TOTAL DIVIDEVALUE=3, 4, OR5

1.12

i

1.09

- ---

3V

~~ 1.06 SV
u: ~ 1.03 9V

gou
;; ~ 1.00
0.97

! c;

-

- -,

~

,
~

~] 0.94

1.i ll! 0.91
0.8S
0.82
0.79

~s

r-:. ~

"

'":;j;!;
5 0.88
..§

1.063
3V
1 OS6
1.049
i~
u:~ 1.042
gou 1.03S 5 V.
;~
9V
~N
1.028
~

E~

.~

SV
3V

~~
j-

-20

20

40

60

80

.
\

\

1\ ,

l"- " ,

1.014

['... '"

1.000
0.993

-40

Temperature (OC)

* Data

1.021

i~ 1.007

9V
-40·

..

-20

3V
SV
9V

..::.
20
40
Temperature!OCl

60

80

labelled "TYPical" IS not to be used for design purposes, but IS Intended as an mdlcatlon of the Ie's potential performance

6-112

MC145157·1, MC145158·1
PIN DESCRIPTIONS
For the following text, the dash number has been omitted
from the part number for simplicity.
INPUTS
OSCin, OSCout IPins 1, 21 ~ These pins form an on-chip
reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of
appropriate value must be connected from OSC ,n to ground
and OSCout to ground OSC In may also serve as the Input
for an externally-generated reference signal This signal will
tYPically be AC coupled to OSC In , but for larger amplitude
signals Istandard CMOS-logic levelsl DC coupling may also
be used In the external reference mode, no connection IS reqUired to OSCout
fin (Pin 8) ~ Input frequency from VCO output A rising
edge signal on this Input decrements the - N counter I ~ A
or ~ N counter for the MC14515S) This Input has an Inverter
biased In the linear region to allow use with AC slgna)s as low
as 500 mV p-p or with a square wave of VDD to VSS
Clock, Data (Pins 9, 10) ~ Shift register clock and data input. Each low-to-hlgh transilion of the clock shifts one bit of
data Into the on-chip shift registers The last data bit entered
determines which counter storage latch IS activated, a logic
one selects the reference cou nter latch and a logic zero
selects the - N counter latch 1- A, - N counter latch for the
MC14515S) The data entry format IS as follows
MC145157 - Rand - N Data Input
MC145158 - R Data Input

~ ~'"

'"
CJl

::;;

0

u

First Data Sit Into
Shift Register

~

MC145158 - A, - N Data Input
A

ec
0

U

'"~

-I-

N

'" '"

-I

'"

CJl

Cf)

::;; ~

='"
First Data 81t Into
Shift Register

---.t

OUTPUTS
DIVided reference and fin frequency
fR, tv (Pins 13, 3)
outputs. The fR and fV outputs are connected Internally to
the ~ R and ~ N counter outputs respectively, allowing the
counters to be used Independently, as well as mOnitoring the
phase detector Inputs
PDout (Pin 5) ~ Single ended Ithree-state) phase detector
output. This output produces a loop error signal that IS used
With a loop filter to control a VCO ThiS phase detector output IS described below and Illustrated In Figure 9
Frequency fV>fR or fV Leading' Negative Pulses
Frequency fVR, v (Pins 16, 15) ~ Double-ended phase detector outputs. These outputs can be combined externally for a loop
error signal A Single-ended output IS also available for thiS
purpose Isee PDout)
If frequency fV is greater than fR or if the phase of fV IS
leading, then error Informallon IS provided by v pulsing
low R remains essentially high Isee Figure 9 for
IIlustrallon)
If the frequency fV IS less than fR or If the phase of fV IS
lagging, then error Information IS provided by R pulsing
low, v remains essentially high.
If the frequency of fV = fR and both are In phase, then
both V and R remain high except for a small minimum
time period when both pulse low In phase.
SlRout (Pin 12 of the MCl45157) ~ Shift register output
ThiS output can be connected to an external shift register to
provide band sWitching, control information, and counter
programming code checking
Modulus Control (Pin 12 of the MC145158) ~ Modulus
control output ThiS output generates a signal by the on-chip
control logic circuitry for controlling an external dual
modulus prescaler The modulus control level will be low at
the beginning of a count cycle and will remain low until the
- A counter has counted down from ItS programmed value
At thiS time, modulus control goes high and remains high
until the - N counter has counted the rest of the way down
from ItS programmed value I N ~ A additional counts since
both - N and ~ A are counting down dUring the first portion
of the cycle). Modulus control IS then set back low, the
counters preset to their respective programmed values, and
the above sequence repeated. ThiS proVides for a total programmable diVide value INT) = N. P + A where P and P +
1 represent the dual modulus prescaler diVide values respectively for high and low modulus control levels, N the number
programmed Into the ~ N counter and A the number programmed Into the ~ A counter Note that when a prescaler IS
needed, the dual modulus version offers a distinct advantage The dual modulus prescaler allows a higher reference
frequency at the phase detector Input, increasing system
performance capability, and SimplifYing the loop filter
design
LD IPin 7) - Lock detect signal ThiS output IS at a high
logic level when the loop IS locked ItR, fV of same phase and
frequency), and pulses low when the loop IS out of lock
REF out (Pin 14) - Buffered reference OSCillator output.
ThiS output can be used as a second local OSCillator,
reference OSCillator to another frequency syntheSizer, or as
the system clock to a microprocessor controller.
CONTROLS
Enable (Pin 11) - Latch Enable Input A logic high on thiS
pin latches the data from the shift register Into the reference
diVider or - N, ~ A latches depending on the control bit The
reference diVider latches are activated If the control bit IS at a
logic high and the ~ N, - A latches are activated If the control bit IS at a logic low A logic Iowan thiS pin allows the
user to change the data In the shift registers Without affectIng the counters

DUAL MODULUS PRESCALING
The technique of dual modulus prescallng IS well established as a method of achieving high performance frequency

6·113

•

MC145157·1, MC145158·1
synthesizer operation at higl) frequencies. Basically, the approach allows relatively low-frequency programmable
counters to be used as high-frequency programmable
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and performance that would otherwise result if a fixed (single
modulus) divider was used for the prescaler.
In dual modulus prescaling, the lower speed counters
must be uniquely configured. Special control logic is
necessary to select the divide value P or P + 1 in the prescaler
for the required amount of time (see modulus control definition!. The MCI45158 contains this feature and can be used
with a variety of dual modulus prescalers to allow speed,
complexity and cost to be tailored to the system requirements. Prescalers having P, P+ 1 divide values in the
range of ... 3/ + 4 to + 128/ + 129 can be controlled by the
MCI45158.
Several dual modulus prescaler approaches suitable for
use with the MC145158 are given in Figure 1. The approaches range from the low cost ... 15/ ... '6, MC3393P
device capable of system speeds in excess of 100 MHz to the
MCI2000 series having capabilities extending to greater than
500 MHz.

b. Prescaler setup or release time relative to its
modulus control signal.
c. Propagation time from fin to the modulus control
output for the MCI45158.
A sometimes useful simplification in the MC145158 programming code can be achieved by chOOSing the values for P
of 8, 16, 32, 64 or 128. For these cases, the desired value for
Ntotal will result when Ntotal in binary is used as the program code to the + Nand ... A counters treated in the
following manner:
A. Assume the ... A counter contains "b" bits where 2b =

P.
B. Always program all higher order ... A counter bits
above "b" to zero.
C. Assume the ... N counter and the'" A counter (with all
the higher order bits above "b" ignored) combined into a single binary counter of 10+ b bits in length. The
MSB of this "hypothetical" counter is to correspond
to the M SB of + N and the LS B is to correspond to the
LSB of + A. The system divide value, Ntotal, now
results when the value of Ntotal in binary is used to
program the "New" 10+ b bit counter.

DESIGN GUIDELINES APPLICABLE
TO THE MC145158
FIGURE 1 - HIGH FREQUENCY DUAL MODULUS
PRESCALERS FOR USE WITH THE MCl46158

The system total divide value (Ntotal) will be dictated by
the application, i.e.

•

MCl2009
MCl2011
MC12013
MC12015
MCl2016
MCl2017
" MCl2018
MC3393

frequency into the prescaler
Ntotal= frequency into the phase detector = NoP+ A
N is the number programmed into the ... N counter; A is
the number programmed into the + A counter. P and P + 1
are the two selectable divide ratios available in the two
modulus prescalers. To have a range of Ntotal values in sequence, the .,. A counter is programmed from zero through
P - 1 for a particular value N in the ... N counter. N is then incremented to N + 1 and the ... A is sequenced from zero
through P - 1 again.
There are minimum and maximum values that can be
achieved for Ntotal. These values are a function of P and the
size of the ... Nand + A counters. the constraint N ;e A
always applies. If Amax = P - 1 the Nmin ;e P - 1. Then
NUotal- min) = (P-1I P+ A or (P- 11 P since A is free to
assume the value of zero.

a. Propagation delay th'rough the dual modulus
prescaler.

440 MHz Min

500 MHz Min
500 MHz Min
225 MHz Min
225 MHz Min
225 MHz Min
520 MHz Min
140 MHz Typ

"Proposed Introduction 1983

By using two devices several dual modulus values are achievable:

Modulus
.-_ _ _ _ _ _ _- , Control

* *

1
~L._D_e_v_ic_e_A_..JHL._D_ev_ic_e_B_~r-

N(total- max) = Nmax·P + Amax
To maximize system frequency capability, the dual modulus
prescaler's output must go from low to high after each group
of P or P + 1 input cycles. The prescaler should divide by P
when its modulus control line is high and by P + 1 when its
modulus control is low.
For the maximum frequency into the prescaler (Fvcomaxl.
the value used for P must be large enough such that:
A. fvco max divided by P may not exceed the frequency
capability of Pin 8 of the MCI45158.
B. The period of fvco(max), divided by P, must be greater
than the sum of the times:

+5/+6
+8/+9
+ 10/+11
+32/ +33
+40/ +41
+64/ ... 65
-128/ + 129
+ 15/ + 16

DeVice
Device
A

B

MC10131
MC1013B
MC10154

MCl2009
+ 20/ +21
+50/+51
+40/ +41
or
+80/+81

MCl2011
+32/ +33
+80/+81
+64/ +65
or
+ 128/ +129

MCl2013
+40/ +41
+ 100/+ 101
+80/+81

NOTE: MCl2009, MCl2011 and MCl2013 are pin equivalent.
MCl2015, MCl2016, and MCl2017 are pin equivalent.

6-114

MC145157·1, MC145158·1
SWITCHING WAVEFORMS

FIGURE3

FIGURE2
tTHL

~---Voo

Any
Output

Modulus
Control

FIGURE4

FIGURE5

q,R,q,v.~"'f-_-_-_-_-_~-_-_tw_q,

Data

...

tsu

--,r-

___

* fR

In

phase with fV

Clock

Vss
-

Enable

VOO

1.-_ _ _ _ VSS

•

PrevIous
Data
Latched

FIGURE6

FIGURE7

Enable,

Any Input

Clock

r,,--___tw~::_-_-_-_~:!
---t
~

-VOO

50%

VSS

FIGURE B - TEST CIRCUIT

Output
Device
Under
Test

6-115

MC145157·1, MC145158·1
FIGURE 9
PHASE DETECTOR OUTPUT WAVEFORMS

~e~:n~~

-1l______.n. _____--'n. _____--'n. ____

IV
Feedback
(fin ... N)

Po Out

~----...r----~U------+----

u

u

•

u

u

NOTE: The Po output state IS approximately equal to either VDD or VSS when active When not active, the output IS high Impedance and the
voltage at that pin IS determined by the low pass hlter capacitor

6-116

MC145157·1, MC145158·1
PHASE LOCKED LOOP - LOW PASS FILTER DESIGN

AI

PDout O

'IN'v
R,
c

oI>RC>-oI>yo--

I

OYCD

I

,
Fls) = R,CS

61

PDout

YCO
R,

Wn

oI>Ro--

=

R2

r

oI>yo--

+,

KoI>KyCO
NCIR, + R21

= O. 5w n /R2 C + __
N_"
'\

I

C

KoI>KyCO)

Flsi

CI

PD out 0--R,
oI>R
oI>y

>---">---0 YCO
R,

C

Assuming gain A

IS

very large, then:

I

NOTE: Sometimes Rl IS split Into two series resistors each R1-2 A capacitor Cc IS then placed from the midpoint to ground to further frlter

oI>y and oI>R. The value of Cc should be such that the corner frequency of this network does not significantly affect Wn.
DEFINITIONS: N = Total Division Ratio in feeOback loop
KoI> = YOD/4.. for PDout
KoI> = YDD/2 .. for oI>y and oI>R
KyCO = 2..AfyCO
AVyCO
for a typical design Wn '"

r ..

2~ofr

lat phase detectorlnputl,

1

RECOMMENDED FOR READING:
Gardner, Floyd M., Phaselock Techniques (second editionl. New York, W,ley-Interscience, '979,
Manassewitsch, Yadim, Frequency Synthesizers: Theory and Design (second edition!. New York, Wiley-Interscience, '980.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Intersclence, '976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley-Intersclence, '98'.
Rohde, Ulrich l., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, '983
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., '978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, '980.

6·117

•

MC145157·1, MC145158·1
CRYSTAL OSCILLATOR CONSIDERATIONS

the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:

The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable is discussed first.

USE OF A HYBRID CRYSTAL OSCILLATOR

CL: CinCout +Ca+CO+ ~
C,n + Cout
. C1 + C2

Commerclall.y available temperature-~ompensated crystal
oscillators tTXCOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50/LA at CMOS
logic levels may be direct or dc coupled to OSC In . In general,
the highest frequency capability IS obtained utilizing a directcoupled square wave haVing a rail-to-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSC In
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Products, 2553 N. Edgington St., Franklin Park, IL60131, phone
(3)2) 451-1000.

where

The OSCillator can be "trimmed" on-frequency by making
a portion or all of C1 vanable. The crystal and associated
components must be located as close as possible to the
OSC In and OSCout PinS to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Couto
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure B. The drive level specified DV the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
R1 in Figure A limits the drive level. The use of R1 may not be
necessary in some cases; i.e. R1: 0 ohms.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A.

DESIGN AN OFF-CHIP REFERENCE

•

: 5 pF (see Figure C)
= 6 pF (see Figure C)
5 pF (see Figure C)
The crystal's holder capacitance
(see Figure B)
External capacitors (see Figure A)
C1 and C2

The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12060, MC12061, MC12560, or MC12561 MECL
devices. The reference signal from the MECL device is ac
coupled to OSCin. For large amplitude signals (standard
CMOS logic levels), dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direct-coupled square
wave having rail-to-rail voltage swing.

USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier (a digital inverter! along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VDD: 5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in

TABLE A - PARTIAL LIST OF CRYSTAL MANUFACTURERS
NAME
United States Crystal Corp.
Crystek Crystal
Statek Corp.

ADDRESS
3605 McCart St., Ft. Worth, TX 76110
1000 Crystal Dr., Ft. Myers, FL 33906
512 N. Main St., Orange, CA 92668

PHONE
18171921-3013
1813) 936-2109
17141 639-7810

RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.

D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro- Technology, June, 1969.

Technical Note TN-7, Statek Corp.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. /EEE, Vol. 57, No.2, Feb.,
1969.

Design, M'ay, 1966.

6-118

MC145157·1, MC145158·1
FIGURE A - PIERCE CRYSTAL OSCILLATOR CIRCUIT

r- -----. ------l

I
I
I

I
L

Rt

Frequency
Synthesizer

I

I

I
_ _ _ _ _ _ _ _ _ _ _ _ -1I
OSC,"

OSC OU !
Rl*

O~---I\I'V"v--'

Cl1:: 1:: C2
* May be deleted

In certain cases See text.

FIGURE B - EQUIVALENT CRYSTAL NETWORKS
RS

1

o---l

01-0
2

LS

Cs

~
Co

Values are supplied by crystal manufacturer (parallel resonant crystal!.

FIGURE C - PARASITIC CAPACITANCES
OF THE AMPLIFIER
a

~>------""T'---~O

0 ......,,--_--11-, I I

,

I

,

=;:= Cin

=:y:=

_J._

_.1._

,

,

6·119

COU!

•

®

MC145159·1

MOTOROLA

Advance Information

HIGH-PERFORMANCE

CMOS
LOW-POWER COMPLEMENTARY MaS
SILICON-GATE

SERIAL INPUT Pll FREQUENCY SYNTHESIZER WITH
ANALOG PHASE DETECTOR

SERIAL INPUT PLL FREQUENCY
SYNTHESIZER WITH
ANALOG PHASE DETECTOR

The MC145159-1 has a programmable 14-blt reference counter, as
well as programmable divide-by-NI divide-by-A counters. The counters
are programmed serially through a common data Input and latched Into
the appropriate counter latch, according to the last data bit (control bitl
entered.
When combined with a loop filter and VCO, this device can provide
all the remaining functions for a PLL frequency synthesizer operating up
to the device's frequency limit. For higher VCO frequency operations, a
down mixer or a dual modulus prescaler can be used between the VCO
and the PLL.
• General Purpose Applications:
CATV
TV Tuning
AMI FM Radios
Scanning Receivers
Two Way Radios Amateur Radio

•

PLASTIC PACKAGE
CASE 738

PIN ASSIGNMENT

• Low Power Consumption
• 3.0 to 9.0 V Supply Range
• On- or Off-Chip Reference Oscillator Operation

RO

RR

OSCin

VDD'

OSC out

• Dual Modulus
• Compatible with the Serial Peripheral Interface (SPII on CMOS
MCUs

CH

Charge

APDout

VDD
Frequency
Steering Out

• -<- R Range=3 to 16383
• -<- N Range= 16 to 1023, -<- A Range=O to 127
• High-Gain Analog Phase Detector

VSS'
CR

VSS

SRout

Modulus Control

Enable

LD

Data

fin

Clock

Enable _1.;..3_ _ _ _ _ _ _-,

14

OSCout~-----,

fR

Analog
Phase
Detector

SRout
4
Charge
18
VDD~ Pin 5
CH
20
VDD'~ Pin 19
RR
VSS~ Pin 7
RO
Vss'~Pin16
15
CR
17
APDout
19
VDD'
16
VSS'
8
Modulus Control
6"

11~lJL_ _ _ _ _ _ _~::::::::::::~~~::::::::::::::~

Clock ..;

* Note.

Pm 6

IS

not and cannot be used as a digital phase detector output.

ThiS document contains information on a new product SpeCifications and Information herem
are subject to change Without notice

6-120

Frequency Steering Out

MC145159·1
MAXIMUM RATINGS* IVoltages Referenced to VSSI
Symbol

Value
05to+10

Parameter

DC Supply Voltage

VDD

VIn , Vout

Input or Output Voltage (DC or Transient)
Input or Output Current toC or Transient), per Pin

lin, lout

-0.5 to VDD+O 5
±1O

Supply Current, VDD or VSS Pins
Power DISSipation, per Packaget

IDD, ISS
PD
T stg

Storage Temperature

TL

Unit

This device contains Circuitry to protect
the inputs against damage due to high

V

static voltages or electnc fields, however,

V
mA
mA

It IS

advised that normal precautions be

taken to avoid applications of any voltage

±30
500

mW

-65 to + 150

'C

operation

260

'C

Vout

Lead Temperature 18-Second Soldenngl

higher than maximum rated voltages to
this hlgh·,mpedance Circuit For proper
be

It IS

recommended that Yin and

constrained

to

the

range

VSSsIV,n or VoutlsVDD.

* MaXimum Ratings are those values beyond which damage to the deVice may occur

Unused Inputs must always be tIed to
an appropnate logic voltage level (e g.,

tPower DISSipation Temperature Derating
Plastic "P" Package -12 mW/'C from 65'C to 85'C
Ceramic" L" Package No derating

either VSS or VDDI

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSI
Symbol

VDD

Min

-40°C
Max

Min

25°C
Typ

Max

Min

Max

Units

VDD

-

3

9

3

-

9

3

V

o Level

VOL

3
5
9

-

005
0.05
005

-

0.001
0.001
0001

005
005
005

-

9
005
005
005

1 Level

VOH

3
5
9

295
4.95
895

-

295
4.95
8.95

2999
4999
8999

-

295
4.95
895

Characteristic

Power Supply Voltage Range
Output Voltage
V,n=O V or VDD
10ut=0 ~A

l'.Voltage, VCH VAPDout
IAPD out =0 ~A

l'.V

-

Input Voltage
o Level
Vou t=0.5 V or VDD-O 5 V
IAII Outputs Except OSCoutl
1 Level

VIL

3
5
9
3
5
9

21
35
63

3
5
9

-0.60
-090
-150

3
5
9

1.30
1.90
380

Output Current V ou t=27V
Vou t=4.6 V
Vou t=8 5 V

Modulus Control
Source

Vou t=03V
Vou t=O.4 V
Vout=O 5 V
Output Current, CR
VCR=45V, RR=240k

Sink

Output Current, APDout
Ro=240 k, VCH=O V
VAPDout=4.5 V
Output Current - Other Outputs
Source
Vou t=2.7V
Vout=46 V
Vout =85V
Sink
Vout=O 3 V
Vout=O 4 V
Vout =0.5 V
Input Current

Data, Clock, Enable

Input Current - fin, OSC,n
Inp~t Capacitance

VIH

-

85'C

-

-

-

105

-

-

09
15
2.7

-

135
2.25
405

09
1.5
27

-

2.1
3.5
6.3

165
275
4.95

-

-0.50
-075
-1.25

-15
-2.0
-3.2
50
6.0
100

-

V

-

-

0.9
15
27

21
3.5
6.3

-

-

-

ICR

9

1.10
170
3.30
-100

IAPD

9

170

-

-

-

-030
-0.50
-080
0.66
1.08
2.10

-

-120

~A

350

~A

mA

IOH

IOL

110
lin
C,n

3-State Output Capacitance Frequency Steerrng Out

Cout

QUiescent CUrrent
Vtn=O V or VDD
10ut=0 ~A
3-State Leakage Current
Vout=O V or 9 V

IDD

10Z

V

mA

IOH

10L

V

3
5
9

-044
-0.64
-130

3
5
9

044
0.64
1.30

9
9

-

-

3
5
9
9

-

-

±03
±50
10
10

800
1200
1600
±03

6·121

-0.35
-051
-1.00

-10
-12
-2.0

-

0.35
051
100

1.0
12
2.0

-

-

±O.OOOO1

±0.1

-

±10
6

±25
10

6

10

-

200
300
400

800
1200
1800

±O.OOOl

±01

-022
-0.36
-0.70
0.22
036
0.70

-

-

±10

~A

-

±22

~A

10
10

pF

-

1600
2400
3200
±3.0

~A

pF

~A

•

MC145159·1

SWITCHING CHARACTERISTICS (TA = 25°C CL = 50 pFI
Characteristic

Symbol

Output Rise Time, Modulus Control (Figures 3 and 8)

tTLH

VDD
3
5

9
Output Fall Time, Modulus Control (Figures 3 and 81

tTHL

3
5

9
Output Rise·and Fall Time, LD (Figures 3 and 81

tTLH,
tTHL

3
5

9
Propagation Delay Time
fin to. Modulus Control (Figures 4 and 81
Setup Times
Data to Clock (Figure 51

tpLH,
tpHL

3
5

tsu

•

th

tree

Input Rise and Fall Times
Clock, OSCin, fin (Figure 6)

tr,tf

6-122

60

60
40

30

40

60
34
30
140
60
60
125
60

ns

ns

30

12

20
18

10

-

9
30

-

16
12

-

-8

-

ns

-6

-

ns

9
3
9
3

70

32
25
12
12
15

-5

ns

50
ns

-

5
10
20

-15

-

9.
3

5
2
0.5

I'S

-

20
5
2

40

30

-

ns

5

35

9

25

20
15

-

9
3
5

tw

ns

30
20
25
17
15

9

5

Input Pulse Width, Enable, Clock (Figure 71

-

-

Units

115

3
5

5

Recovery Time
Enable to Clock (Figure 51

-

Max

50

55
40
25

5
Hold Time
Clock to Data (Figure 51

-

Typ

-

9
3

Clock to Enable (Figure 51

Min

-8
0

-

MC145159·1
PIN DESCRIPTIONS
INPUTS
OSCin, OSCILLATOR INPUT (PIN 2), OSCout,
OSCILLATOR OUTPUT (PIN 3) - These pins form an onchip reference oscillator when connected to terminals of an
external parallel resonant crystal. Frequency setting
capacitors of an appropriate value must be connected from
aSCin to VSS and OSCout to VSS. OSC In may also serve
as input for an externally generated reference signal. This
signal will typically be ac coupled to OSCin, but for larger
amplitude signals (standard CMOS logic levels), dc coupling
may also be used. In the external reference mode, no connection is required to OSCout.
fin, FREQUENCY IN (PIN 10) - Input to the positive edge
triggered divide-by-N and divide-by-A counters. fin is
tYPically derived from a dual modulus prescaler and is ac
coupled into Pin 10. This input has an inverter biased in the
linear region to allow use with ac-coupled signals as low as
500 mV peak-to-peak or direct-coupled signals swinging
from VDD to VSS·
Data, SERIAL DATA INPUT (PIN 12) - Counter and
control information is shifted into this Input. The last data bit
entered goes into the one-bit control shift register. A logic
one allows the reference counter information to be loaded into it's 14-bit latch when Enable goes high. A logic zero
entered as the control bit disables the reference counter
latch. The divide-by-AI divide-by-N counter latch is loaded,
regardless of the contents of the control register, when
Enable goes high. The data entry format is shown below.
Enable, TRANSPARENT LATCH ENABLE (PIN 13) - A
high on this input allows data to be entered into the divideby-AI divide-by-N latch and, if the control bit is high, into the
reference counter latch. Counter programming is unaffected
when Enable is low.
Clock, SHIFT REGISTER CLOCK (PIN 11) - A low-tohigh transition on this input shifts data from the Serial Data
input into the shift registers.
COMPONENT PINS
CR, RAMP CAPACITOR (PIN 15) - The capacitor connected from thiS pin to VSS is charged linearly, at a rate
determined by RR. The voltage on this capacitor is proportional to the phase difference of the frequencies present at
the internal phase detector inputs. A polystyrene or mylar
capacitor is recommended.

RR, RAMP CURRENT BIAS RESISTOR (PIN 20) - A
resistor connected from this pin to VSS determines the rate
at which the ramp capacitor IS charged, thereby affecting the
phase detector gain (see Figure 11.
CH, HOLD CAPACITOR (PIN 18) - The charge stored on
the ramp capacitor is transferred to the capacitor connected
from this pin to either VDD' or VSS'. The ratio of CR to CH
should be large enough to have no affect on the phase
detector gain (CR>10CH!. A low-leakage capacitor should
be used.
RO, OUTPUT BIAS CURRENT RESISTOR (PIN 1) - A
resistor connected from this pin to VSS biases the output
N-Channel transistor, thereby setting a current sink on the
Analog Phase Detector Output (Pin 171. This resistor adjusts
the VCO input voltage change with respect to phase error
(see Figure 2!.
OUTPUTS
APDout, ANALOG PHASE DETECTOR OUTPUT (PIN 17)
- ThiS output produces a voltage that controls an external VCO. The voltage range of this output (VDD = + 9 V) is
from below + 0.5 V to + 8 V ormore. The source Impedance
of this output is the equivalent of a source follower with an
externally variable source resistor. The source resistor
depends upon the output bias current controlled by the output bias current resistor, RO. The bias current is adjustable
from 0.01 mA to 0.5 mAo The output voltage will not be more
than 1.05 V below the sampled point on the ramp. With a
constant sample of the ramp voltage at 9 V and the hold
capacitor at 50 pF, the instantaneous output ripple is not
greater than 5 mV peak-to-peak.
Charge, RAMP CHARGE INDICATOR (PIN 4) - This output is high from the time fR goes higb to the time fv goes
high (fR and fv are the frequencies at the phase detector inputs!. This high voltage Indicates that the ramp capacitor,
CR, is being charged.
Frequency Steering Out, THREE-STATE FREQUENCY
STEERING OUTPUT (PIN 6) - If the counted down input
frequency on fin is higher than the counted down reference
frequency of OSCin, this output goes low. If the counted
down VCO frequency is lower than that of the counted down
OSCin, this output goes high.
The repetition rate of the Frequency Steering Output
pulses is approximately equal to the difference of the frequencies of the two counted down inputs from the VCO and

DATA ENTRY FORMAT
Latched When
Control Bit = 1

Shift
Data In

Register

Out
Latched When
Control Blt=O

Control Bit

6-123

MC145159·1

OSCin. The output maintains a high-impedance state when
the counted down VCO (divided down fin pulse) and the
counted down OSCin are in a one-to-one ratio over a 2.. window with respect to the counted down OSCin.
LD, PHASE LOCK INDICATOR (PIN 9) - This output is
high during lock and goes low to indicate a non-lock condition. The frequency and duration of the non-lock pulses will
be the same as either polarity of the Frequency Steering Output.
Modulus Control, DUAL MODULUS PRESCALER CONTROL (PIN 8) - The modulus control level is low at the
beginning of a count cycle and remains low until the divideby-A counter has counted down from its programmed value.
At that time, the modulus control ·goes high and remains
high until the divide-by-N counter has counted the rest of the
way down from its programmed value (N - A additional
counts, since both divide-by-N and divide-by-A are counting
down during the first portion of the cycle). Modulus control
is then set back low, the counters preset to their respective
programmed values, and the above sequence is repeated.
This provides a total programmable divide value of
NT=N.P+A, where P and P+l represent the

dual modulus prescaler divide values, respectively, for high
and low Modulus Control levels; N is the number programmed into the divide-by-N counter, and A is the number programmed into the divide-by-A counter.
SRout, SHIFT REGISTER OUTPUT (PIN 14) - This pin is
the non-inverted outp·ut of the inner-most bit of the 32-bit
Serial Data Shift Register. It is not latched by the Enable line.
POWER PINS
VDD, POSITIVE POWER SUPPLY (PIN 5) - Positive
power supply input for all sections of the MC145159-1 except
the Analog Phase Detector. VDD and VDD' should be
powered up at the same time to avoid damage to the
MC145159-1.
VSS, NEGATIVE POWER SUPPLY (PIN 7) - Circuit
ground ior all sections of the MC145159-1 except the Analog
Phase Detector.
VSS', ANALOG PHASE DETECTOR CIRCUIT GROUND
(PIN 16), VOO', ANALOG POWER SUPPLY (PIN 19) Separate power supply and ground inputs are provided to
help reduce the effects in the analog section of noise coming
from the digital sections of this device and the surrounding
circuitry.

FIGURE 1 - CHARGE CURRENT vs RAMP RESISTANCE

•

FIGURE 2 - VCO BIAS VOLTAGE

10001111~~!~!1!11111111
1;l!100:~'IIIIIIII

700
500
300
:Ii 200
1';
~

~

~

VOO.3 V1k-5 V!~B

,,:

rt~Ht#--r~rP~rr~~~~~~~~-+-r~

1\
20 30 5070100 200300500

lk

I"

2k 3k

1000
700
§l5o0
VOO·3 V t--5V
~300
z
0
i'" 20100
~ 70
~ 50
§ 0
Ii 0
0o IL .1

BV

I

I

1

ICHARGE, CHARGE CURRENT lILA)

ANALOG VOLTAGE OUT IVOlTSI

DESIGN EQUATION
Icharge
K= 2 .. fR CR
where K= phase detector gain, Icharge is from Figure 1
fR = reference frequency, CR = ramp capacitor lin farads)

6-124

MC145159·1
SWITCHING WAVEFORMS
FIGURE4

FIGURE3
tTHL

----vO::J

Any
Output

Modulus
Control

FIGURES

FIGURES

tf
Clock
OSC In , fin

Data
VSS

VSS

tsu
Clock
VSS

-

Enable

VOD
VSS

PrevIous
Data
Latched

FIGURE7

Enable,
Clock

Jr,::==::::..:t===c
w

FIGURE8 - TEST CIRCUIT

VDD

50%

VSS

Output
Device

Under
Test

6-125

MC145159·1

CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may' be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers. The most desirable IS discussed first.
USE OF A HYBRID CRYSTAL OSCILLATOR
Commercially available temperature-~ompensated crystal
oscillators ITXCOsl or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 p.A at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a directcoupled square wave having a rail-ta-rail IVDD to VSSI
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin
may be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TXCOs and data clock
oscillators, please contact: Motorola Inc., Component Praducts, 2553 N. Edgington St., Franklin Park, IL 60131, phone
13121451-1000.

•

DESIGN AN OFF-CHIP REFERENCE
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MCI2060, MCI2061, MCI2560, or MC12561 MECL
devices. The reference signal from the MECL device is ac
'coupled to OSCin. For large amplitude signals Istandard
CMOS logic levelsl, dc coupling is used. OSCout, an unbuffered output, should be left floating. In general, the highest
frequency capability is obtained with a direci-coupled square
wave having rail-to-rail voltage swing.
USE OF THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip amplifier la digital inverterl along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure A.
For VOD = 5 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies in
TABLE A -

CL= CinCout +Ca+CO+ Cl·C2
Cin + Cout
Cl + C2
where

= 5 pF (see Figure CI
= 6 pF (see Figure CI
Ca
5 pF Isee Figure CI
The crystal's holder capacitance
Co
Isee Figure BI
Cl and C2
External capacitors (see Figure AI
Cin
Cout

The oscillator can be "trimmed" on-frequency by making
a portion or all of Cl variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
In some cases, stray capacitance should be added to the
values for Cin and Cout.
Power is dissipated in the effective series resistance of the
crystal, Re, in .Figure B. The drive level specified by the
crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency.
Rl in Figure A limits the drive level. The use of Rl may not be
necessary in some cases; i.e. Rl = 0 ohms.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. ICare should be taken to
minimize loading. I The frequency shojJld increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an Increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of Rl.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
See Table A.

PARTIAL LIST OF CRYSTAL MANUFACTURERS

NAME
United States Crystal Corp.
Crystek Crystal
Statek Corp.

the afea of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC inputloutput capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:

ADDRESS
3605 McCart St., Ft. Worth, TX 76110
1000 Crystal Dr" Ft. Myers, FL 33906
512 N. Main St" Orange, CA 92668

PHONE
18171921-3013
18131 936-2109
17141 639-7810

RECOMMENDED FOR READING
Technical Note TN-24, Statek Corp.

D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro- Technologv, June, 1969.

Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.,
1969.

P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design. May, 1966.

6·126

MC145159·1

FIGURE A -

r-

I

PIERCE CRYSTAL OSCILLATOR CIRCUIT

-----------l
~

~~~

Synthesizer

I

I

I

i

I

I

I

L _ _ _ _ _ _ _ _ _ _ _ _ -1
OSC out

OSCin

Rl*

DI-t---AN'v--'

T

Cli:

* May be deleted

C2

in certain cases. See text.

FIGURE B - EaUIVALENT CRYSTAL NElWORKS
RS

Cs

~

101-0

0----1

LS

2

Co

Values are supplied by crystal manufacturer (parallel resonant crystal).

FIGURE C -

PARASITIC CAPACITANCES
OF THE AMPLIFIER

a

o

1

1
I

"
~
--11-------.1------<0
1
1

=:r= Cin

:;:: Cout

1

I

_1-

_.1.._

6-127

•

MC145159·1
FIGURE 9 - TIMING DIAGRAM FOR MINIMUM DIVIDE VALUE (N= 16)

fin

________________________~Il~_
~______________________~Il~_____
~

fVIl
Feed~ack
(f,n~NI
fRIl
Reference
lOse -+- RI
Sample

Charge

Discharge

•

~--------------~~
~------------------------~~~----

l

CR

,
----~----------~------------~---~~
"-

CH

"----~----------------------------~~

APD out

----~----------------------------~~

6·128

CMOS Remote Control Functions

~
11

"

7-1

CMOS REMOTE CONTROL FUNCTIONS

Device
Function

Number

Function
Transmitter
Receiver

Transmitter

MCl4457
MCl4458
MCl4469
MCl4497

Remote Control Transmitter
Remote COl1trol Receiver
Addressabl!3 Asynchronous Receiver/Transmitter

MC145026
MC145027
MCl45028
MCl45029

Remote
Remote
Remote
Remote

PCM Remote Control Transmitter

Number of
Address Bits
0
0
0

Control
Control
Control
Control

Encoder
Decoder
Decoder
Decoder

Numb.rof
Data Bits
5"
5"

Number

Number
of Pins

Associated Device
Number(s)

MCl4467
MCl4458

16
24

MCl4458
MCl4457

Device

MCl4497

18

MC3373

MCl45026

16

5

MCl45027
MCl45028
MCl45029

16
16
16

MC145027, MC145028,
MC145029
MC145026
MCl45026
MC145026

7/8

MCl4469

40

MCl4469, MC6850

6"
Depends on Decoder

Encoder

Depends on Decoder

Decoder
Decoder
Decoder

5
9
4

0

Addressable UART

7

4

* These 5 or 6 bit codes specify commands or functions Internal to the associated receiver devices.

•

7-2

@

MCl4457
MCl44S1

MOTOROLA

MCl4457 TRANSMITTER
MCl4458 RECEIVER

CMOS MSI/LSI

The MCl4457 and MCl4458 are a transmitter and receiver pair constructed In CMOS monolithic technology These units are designed for
ultrasonic or infrared remote control of TV receivers, converters, communication receivers, and games. Selection of up to 16 channels may
be done single entry; or up to 256 channels may be done double entry.
The MCl4457 encodes each keyboard position Into frequencymodulated blphase data. This transmitter functions with a 20- to
32-positlon keyboard and provides either channel select/toggle information (single-word transmlsslonl or analog information (continuous
transmission for the duration of key press) The MCl4457 features low
standby power between data transmissions.

ILOW-POWER COMPLEMENTARY MOSI

TRANSMITTER
RECEIVER

MCI4457 TRANSMITTER

• Low External Component Count
• High NOise Immunity
• One Analog Output from Receiver
• Low Power
• Operating Voltage Range' 4.5 to 10.0 V for MCl4457
4.5 to 5.5 V for MCl4458

MAXIMUM RATINGS* IVoltages Referenced to VSSI
Rating

DC Supply Voltage

MCI4457
MCI4458

Input Voltage, All Inputs

L SUFFIX
CERAMIC PACKAGE
CASE 623

* Maximum Ratl
occur
P SUFFIX
PLASTIC PACKAGE
CASE 709

PIN ASSIGNMENTS
MCI4458
RECEIVER

MCI4457
TRANSMITTER

R3

VDD

R4
R5

Out 2

Data In

Out 1
13

Mod

12

OSCout

R2
Ai
Ci

6

C2
VSS

8

ORDERING INFORMATION

OSCin

VDD
23

Vol

POR

22

A3

AFT

21

A2

On

20

Al

11

Oscm

UHF/VHF

19

AD

10

C3

LBV

18

VA

Oi

M8

17

Data Ready

M4

16

L8

M2

15

L4

Ml

14

L2

VSS

13

L1

7-3

"'' ' l

Suffix

Denotes
Ceramic Package

P

PlastiC Package

This device contams circuitry to protect the inputs against damage due to high >latie voltages or
electriC fields; however. it IS adVised that normal
precautions be taken to avoid application of any
voltage higher than maximum rated voltages to
thiS high Impedance circuit. For proper operation,
It is recommended that Vin and Vout be constrained to the range VSS$(V tn or Vout)$VDD.
Unused inputs must always be tied to an appropriate logic voltage level le.g., either VSS or
VDDI.

•

MC14457, MC14458
TRANS MinER - MCl4457
ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSI

Characteristic
Output Voltage
"0" Level
Vm = VDD or 0
"1" Level
10ut=0~A
Input Voltage #
IVO=4.5 or 0.5 VI
IVo=9.00rl.0VI

"0" Level

"1" Level

Symbol
VOL
VOH

+85°C

Typ

Max

Min

Max

-

0
0

005
005

-

0.05
005

-

4.95
9.95

5.0
10

-

-

495
995

-

50
10

-

15
3.0

-

2.25
4.50

1.5
3.0

-

15
3.0

5.0
10

3.5
7.0

-

3.5
7.0

2.75
550

-

35
70

-

50
10

-6.0
-3.2

-

-50
-2.6

-9.0
-4.5

-3.5
-18

5.0
10

6.0
3.2

-

5.0
2.6

90
4.5

-

-

5.0
10

-0.26
-06

-

-022
-0.55

-0.44
-1.12

-

-018
-045

-

50
10

0.26
0.6

-

0.22
055

0.44
1.12

018
045

-

mA

-

50

500
±O.OOOOI

-

-

~A

±1.0

V

rnA

10H

-

3.5
18

mA
mA

IOH

IOL

V
V

VIH

IOL

Unit
V

4.95
9.95

lin

10

-

10

Input Capacitance

Cin

-

Quiescent Current - Per Package
Osc,n=O V, Other Inputs=Open,
10ut=0 ~A
Total Supply Current at an External
load Capacitance I Cli of Figure 4
f=5OO kHz IWlth any Analog
command I

IDD

5.0
10

-

Pin 11

25°C
Min

50
10

lin

Input Current -

•

-40°C
Max
0.05
0.05

Min

VIL

IVO=0.5 or 4.5 VI
IVO= 1.0 or 9.0 VI
Output Drive Current - Pins 14, 15
Source
IVOH=2.5VI
IVOH=9.5 VI
Sink
IVOL =2.5VI
IVOL =0.5 VI
Output Drive Current - Pin 13
Source
IVOH=4.6 VI
IVOH=9.5 VI
Sink
IVOL =0.4 VI
IVOL =0.5 VI
Input Current - Pull-ups

Voo
V
5.0
10

±0.3

50
100

-

-

1000

5.0

±0.3
7.5

-

0.008
0.016

-

5.0
10

-

~A

-

pF

50
100

-

375
750

~A

-

-

-

Min

Max
005

Unit

-

V

~A

IT
50
10

-

-

-

RECEIVER- MCl4458
ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSI
Characteristic
"0" level
Output Voltage
Vin=VDD or 0
"1" level
10ut=0~A
Input Voltage#
IVO=4.5 or 0 5 VI
IVo=0.50r4.5VI
Output Drive Current
IVOH=2.5VI

IVOL =0.4 VI

"0" Level
"1" level

VOD
V

Min

VOL

50

-

VOH

5.0

4.95

5.0
5.0

Input Current IOsCin, Dml
Input Current IPORI
Input Capacitance
Quiescent Current, Per Package
POR=VDD, Other Inputs=VDD
or 0, lmie 0 ~A
Data Input Hysteresis

Total Supply Current at an External
load Capacitance ICll of Figure 6
f= 500 kHz

+ 85°C

25°C
Min

Typ

-

0

Max
0.05

-

4.95

5.0

-

4.95

-

-

15

-

2.25

1.5

-

15

VIH
IOH

3.5

-

3.5

2.75

-

35

-

V

V

Vil

Source
Sink

-40°C
Max
005

Symbol

V
mA

-

-05

-1.7
0.78

-

-0.4

0.4

±0.3

-

±O.OOOOI

±0.3

-

10

50

-

-

50

5.0

-

5.0

-

400
75

-

250

1000

-

5.0

-

-

-

0.25

-

-

5.0

-0.5

IOl

5.0

0.45

lin

5.0

lin
C,n

5.0

-

-

IDD

VHvs
IT

5.0

INolse Immunity specified for worst-case Input combination
Noise Margm for both "1" and "0" level = 1.0 V min @ VDD=5 0 V
2.0 V min @ VDD= 10 V

7·4

400

034

± 1.0

-

mA
~A
~A

pF
~A

-

V

-

~A

MC14457, MC14458
SWITCHING CHARACTERISTICS (MCI4457 - Transmitter VDD-5
- to 15 V' MCI4458 - ReceIver VDD-5
- VI
Characteristic
Output Rise and Fall Time - Receiver
Cl = 100 pF
OSCillator Start~Up Time - Transmitter

Clock Pulse Frequency

Symbol

Min

Typ

Max

Unit

tTlH,
tTHl
ton
PRF

-

0.3

10

ps

-

80

-

1500

600

ps
kHz

MCI4467 - TRANSMITTER

Shift
Register

,~ {

4

ii3

Inputs

'''om,
{
Inputs

R2
ii4

3

R5

6

Ci

C2
10

a

9

Oi

Pullup
Resistors
with
Keyboard
Encode
and
Debounce

ModulatIon
Control

Mux

7-5

VDD= PIn 16
VSS= Pin 8

Mod
IData Codel

•

MC14457, MC14458
FIGURE 1 ~ EXAMPLE OF TRANSMITTED WORD

I----

I

5-Bit Keyboard
Encoded Latched Data

----+/
I

(~~~~:)~I:::.~vl.~2~2~11:~::::e~I1:::rl.~2~2211~::!tZ7if~:::::::eZJ1~::::::::::!1
Low Frequency

ILF*I

c:::J

I

High Frequency ~

0
Zero
Start

I

I

1
One
Start

I

0
Funct

0
LSB

I

1

I

LSB
+1

1

I

LSB
+2

I

I LF I

0
MSB

-100 ms--------~~

..

* Low Frequency

FIGURE 2 - DATA SIGNAL

Low Freq=

Data
Signal

Data _..;-_ _-;.._-'
Code

•

PreStart
Low F

Start
Bit

"0"

I.---

Start
Bit
"1"

Start Pattern
Fixed

Function
Bit

LSB

"0"

"0"

~I .

LSB+l
"1"

LSB+2

"0"

Command Pattern
Variable

MSB
"1"

End
Low F

~I

MC14467 TRANSMITIER PIN DESCRIPTIONS

Ai, R2, R3, iR R5, ROW INPUTS (PINS 5, 4,1,2,3) These pins are the row inputs and are active in the low state.
On-chip pullup resistors are provided on each of these
.
inputs.

puts are at ground potential.
OSCin, OSCout, OSCILLATORS (PINS 11, 12) - These
pins are the input/output terminals of the oscillator. They
can be used with a ceramic resonator or crystal. The oscillator is automatically turned off after the data is transmitted
for low current quiescent operation.
If an external oscillator is used, a current limiting resistor
should be added, due to the presence of an internal pulldown device on the oscillator input.

C;, C2, 0, C4, COLUMN INPUTS (PINS 6, 7, 10, 9) These pins are the column inputs and are active in the low
state. On-chip pullup resistors are provided on each of these
inputs.
Out 1, Out 2, OUTPUTS (PINS 14, 15) - These pins provide push-pull output and can be used with ceramic transducers or LEDs. In the non-operating condition, both out-

Mod, MODULATION (PIN 13) - This pin is a data code
output Note that there is no power-up reset.

7-6

MC14457, MC14458
TABLE 1 - DATA CODE
Key
Number

Operation

Row
Column
(Active Low) (Active Low)

Transmitter Data and Receiver Output Address
MSB/A3

1

Digit 0

Rl

Cl

0

2

Digit 1

Rl

C2

0

LSB+2/A2 LSB+ I/Al
0
0

LSB/AO

Function*

0

0

3

Digit 2

R2

C1

0

0

1

0

4

Digit 3

R2

C2

0

0

1

1

5

Digit 4

R3

C1

1

Digit 5

R3

C2

1

0
0

0

6

1

0

7

Digit 6

R4

C1

1

1

0

0

8

Digit 7

R4

C2

0
0
0
0

0
0
0
0

1

1

1

0

9

Digit 8

R5

C1

1

0

R5

C2

1

R1

C3

Rl

C4

R2

C3

0
0
0

14

I
Chan Search I
Fine Tuning I
Fine TUning I

0
0
0
0

0

Digit 9

R2

C4

0

0
0
0
0
0
0

15

Spare

R3

C3

1

16

Spare

R3

C4

17

Volume

R4

C3

18

Volume

R4

C4

0
0
0
0

10
11
12
13

Chan. Search

I
I

0

0

1

1

0

0

1

1

1

0

1

1

1

1

0

1

1

0
0

1

1

1

1

0

1

1

1

1

1

0
0

0

1

1

1

1

0

0

1

1

0

0

19

Mute on/off

R5

C3

1

0

20

Off

R5

C4

1

0

21

Digit 10

R2oR5

C1

1

22

__ Digit 11

R2o R5

C2

1

0
0

23

Digit 12

R3oR5

C1

1

1

1

24

Digit 13

R3oR5

C2

1

1

0
0

1

0
0

25

Digit 14

R2oR3oR5

C1

1

1

1

0

0

26

Digit 15

R2o R3oR5

C2

1

1

1

1

0

27

Spare

R2oR5

C3

1

0

1

Spare

R2o R5

C4

1

0
0

1

28

1

1

1

29

Spare

R3o R5

C3

1

1

0

0

1

30

Spare

R3oR5

C4

1

1

0

1

1

31

Spare

R2o R3oR5

C3

1

1

1

0

1

32

Spare

R2oR3oR5

C4

1

1

1

1

1

VA
Pulse

-

Notes
1

1
1

-

1

-

1

-

...
...
...
...
...
...
...
...
...
...

1
1
1

1
1
2
2
3
3
3
3
3
3
2
2

-

1

-

1

-

1

...
...
...
...
...
...

1

1
1
3
3
3
3
3
3

Notes
1 Channel Select Keys (Function 8It=01. Data IS transmitted once each time a key IS activated
2 Toggling type On/Off or counter advance type keys. Data

IS

transmttted once each time a key

IS

activated

3. Analog Up! Down or On/ Off keys, Ie, one key for Down or Off a,nd another key for Up or On Data transmiSSIon IS repeated as long as the
key IS operated.
*The function bit IS used only Internally by the MC14458 receiver as a steering bit

In Table 1, all channel select data is noted by the function
bit equal to zero. For functions other than channel, the function bit equals one.
The four toggling or counter advance type keys that
transmit data once each time a key IS actIVated are Mute,

Off, Channel Search Up, and Channel Search Down.
The twelve remaining analog keys (Vol, Tint, Color, etc)
transmit data as long as the key is activated. The keys' functions are arranged to provide the most tYPical application
Without grounding of multiple row or columns reqUired.

7-7

•

MC14457, MC14458
MC14458 - RECEIVER

L -______~,

r-~--'16~
15 L4
14 L2

....

13 L1

'--_
2 _ _ _ _--1
Data In.....:o

8 M8
9

M4

10 M2

Shift

11 M1
Load

•

UHFIVHF
17 Data Ready

S

Q

4 AFT

~--------------------~R

•

VDD= Pin 24
VSS=PIn 12

MC14458 RECEIVER PIN DESCRIPTIONS

Data Ready, DATA READY SIGNAL (PIN 17) - A
positive pulse with a duration of 768 JLs appears at Pin 17 of
the receiver approximately 0.1 second after a complete
command is entered on the remote control transmitter
keyboard. The negative gOing edge of this pulse may be used
for triggering purposes.
NOTE: A complete command is one digit in the single
entry mode or two digits in the double entry mode.

Data In, DATA INPUT (PIN 2) - The amplified ultrasonic
data signal lafter amplification and limiting forms a square
wave with a peak-to-peak value of VDD) is app)led to this input termtnal.
OSCin, OSCILLATOR INPUT (PIN 1) - The oscillator tnput pin of the receiver IS connected to an oscillator that provides, for example, a 500 kHz square wave signal. A tYPical
oscillator CIrCUIt is shown tn Figure 5. Accuracy of one percent, relative to the oscillator frequency In the transmitter, IS
recommended for satisfactory performance tn very high echo
producing enVIronments.

AFT, AUTOMATIC FINE TUNING ENABLE (PIN 4) - The
voltage level at this pin is low for a time duration of 0.393
seconds following a change in selected channel to allow
disabltng the tuner AFT cirCUIt. Also, miscellaneous commands 0000, 0001, 0010, and 0011 (Channel Search
Up/Down, Fine Tuning Up/Down) will cause this disable
feature.

L1, L2, L4, LB, Ml, M2, M4, MS, CHANNEL OUTPUTS
(PINS 13, 14, 15, 16, 11, 10, 9, S) - The eight data output
pins provide latched data corresponding to the channel
selected on the transmitter keyboard. L1 through L8 are the
least significant bits; Ml through M8 are the most significant
bits. The data on these pins IS accompanied by a Data Ready
signal.

POR, POWER-ON RESET (PIN 3) - This pin IS low for
power-on reset of the analog output 10 a pulse width and
off/on output to O. An internal pull-up device delivers 10 to
400 JLA to charge an external capacitor. Reset occurs until
the tnput voltage reaches 70 percent VDD. All internal
registers will also be reset.

7-8

MC14457, MC14458
In the muted mode, the analog level is memorized and
cannot be varied by the up/ down controls on the
transmitter.

AO, Al, A2, A3, ADDRESS OUTPUTS (PINS 19, 20, 21,
22) - The address outputs of the receiver identify selected
analog and on/ off commands for use In system expansion.
The data on these lines is valid when accompanied by a Valid
Address pulse.

LBV, LOW BAND (PIN 7) - ThiS pin Will go HIGH
whenever channels 02, 03, 04, 05, or 06 are selected. The
output IS LOW for channels 00, 01, and 07 through 99.

VA, VALID ADDRESS (PIN 18) - A negative gOing pulse
with a duration of 768"s appears at Pin 18 approximately 0 1
seconds after an analog on/ off key on the remote control
transmitter keyboard is operated. Either edge of this pulse
may be used for control of add-on CirCUitS.
The Valid Address pulse IS repeated every 102.4 ms for as
long as a key IS operated which provides repeated transmission of data when held down.
The Valid Address signal may be used In conjunction with
the Address Outputs to drive memOries to provide additional
control functions such as color, tint, etc.
The Valid Address pulse may be used to provide a stepping clock for up/down counters In a memory. The least
significant address line lAO) IS used to identify the up or
down mode, and the remaining address lines IA 1, A2, A3)
are decoded to enable each individual control CirCUit.
By adding up/ down counters to the Data Outputs, it IS
possible to use the Valid Address pulse and a decoded address for Implementing a channel up/ down stepping function from the remote control. Additional On/Off functions
may be obtained by usrg the Valid Address pulse in combination with a decode/l address for setting and resetting of
latches. The Valid Address signal is disabled in the standby
mode ION output at logica) Q).

OPERATION
The receiver can be placed in a single-digit mode of operation by connecting the M4 data output IPln 91 to VOO and
the UHF output IPIn 61 to VSS. In this mode, the L 1 through
L8 channel outputs will change immediately after the entry of
a single digit on the transmitter keys. The Ml through M8
outputs are not used in thiS mode Isee Figure 61
As one example of operation, a free-running ceramic
resonator oscillator lat 500 kHzl, triggered by the depreSSion
of any key, IS diVided by 12 or 13 to provide frequencies of
41.67 or 38.46 kHz. The transmitted data "zero" consists of
256 periods of the lower frequency followed by an equal
number of the higher frequency. Mark to space ratio is kept
at 1·1 in each case. A data "one" reverses the order of the
two frequencies.
Rowand column information from the keyboard IS encoded Into a 5-blt word and loaded onto data latches on the
edge of transmit enable. Th,s data, preceded by two bitS, 0
and 1, is used in sequence to provide biphase control of the
divider and, consequently, the bit pattern transmitted from
the unit. Each 7-bit word begins and ends with a low frequency burst. Operation of a channel select key produces an
output data stream for a duration of approximately 100 ms.

UHFIVHF, ULTRA HIGH FREQUENCYIVERY HIGH FREQUENCY OUTPUT (PIN 6) - This pin of the receiver provides a low level when the selected channel IS a VHF channel
100 to 13, or 84 to 99). A hIgh level on Pin 6 Identifies selection of a UHF channel 114 to 83). This signal IS provided to
permit switching of VHF and UHF tuners.

APPLICATIONS INFORMATION
TYPical circuits for the transmitter and receiver chips are
shown in Figures 3 through 7.
The transmitters, with the keyboard shown, transmit the
first twenty codes from Table 1. The circuits of Figure 3
transmit via ultrasonic; whereas, the cirCUit of Figure 4
transmits infrared light. In Figure 3, a push-pull output at
Pins 14 and 15 allows a balance drive to the ceramic
microphone, which virtually doubles the transmitted power,
compared to a Single-ended output.
The diagram in Figure 5 shows an amplifier connected to a
remote receiver. The bias resistor I photodlodel of the
amplifier requires bias. The bias voltage is determined by the
choice of photodlode and system considerations such as ambient light. Most of the required gain is realized uSing three
of the hex Inverters in the MCl4069UB package. A fourth inverter from the same package operates a 500 kHz OSCillator
Circuit.
Figure 6 shows a block diagram of a PLL system. The
receiver directly addresses a syntheSIZer. In thiS diagram, a
complete command consists of two channel digits followed
by an Enter code. The Enter code into the syntheSizer is a
0101 In complementary logic. The transmitted code from the
transmitter is 1010, which is Function 10 from Table 1.
A block diagram of a tuning address system IS shown In
Figure 7. This block diagram incorporates a one-chip microcomputer that would be programmed to the system's needs.
The system can be expanded up to 256 channels.

On, ON (PIN 5) - This pin of the receiver provides a low
level following operation of the Off command 11(01) on the
remote-control transmitter. The signal on this pin changes to
a high level when a channel IS selected.
Vol, VOLUME CONTROL (PIN 23) - An analog output
voltage In the range between 0 V and VOO IS obtained by Integrating the signal at the Vol pin through a low-pass filter
The analog voltage resolution has been chosen to be 84
steps The value can be Incremented or decremented In
steps of one by keys proViding commands 0111 and 0110,
respectively Isee Table 11
ThiS analog voltage can be varied up or down at a speed of
approximately 10 steps per second. The 0/ A conversion is
performed with an underflow and an overflow limiting cirCUit The Vol pin IS normally used for the control of volume.
The first time power is applied to the remote-control
receiver, the volume output is 0 volts.
The Vol signal may be Increased after a channel has been
selected by operating the key proViding a command 0111
IVolume Upl.
The Vol signal may be muted by operating a key on the
transmitter proVIding command 1QOO. Return to the original
output prior to muting may be achieved by operating the
mute key a second time or by operating the volume-up key.

7-9

•

MC14457, MC14458
FIGURE 3 - TYPICAL ULTRASONIC SYSTEM

100 pF 1000 pF

~~~
10Meg

11

680
12

1 R3

~"'-

2 R4

~+9V

5 Rl

~ ~ ,,{ ~

15

4 R2

~,{ v{ ,,;{ v{

MCl4457

~,{ ,,{ ~ .,{
~,{ v{ v{ v{
~,{ ,~ ~-{

HI~I0

Ceramic

8

3 R5
Cl C2 C3 C4
6 7 10 9

.1

Ultrasonic
Microphone

~

":"

Note: CR

IS

a ceramic resonator, Radio Matenals Corp. type CR30 or equivalent.

FIGURE 4 - TYPICAL INFRAREO SYSTEM

•

+6V
680
12
14

N.C.

15 330
MCl4457

__

...

+6V ~

~4=~4=~4=~~~ ~3~R5

Cl C2 C3 C4
6 710 9

Note: CR is a ceramic resonator, Radio Materials Corp_ type CR30 or eqUIvalent.

7-10

MC14457, MC14458
FIGURE 5 - TYPICAL REMOTE CONTROL RECEIVER CIRCUIT DIAGRAM

.,

1N914

+5

I

r:1 ,~?' r:l ,~" '... ",

. -. . ._ L -....-4If-<.--:_2_.2_k....-I • '"

~I1~I1OOPF
-=-=-

1O00

+5V
560 1/6 MC14069UB

+5V
1/6 MC14069UB

100PFI
+5V
**
1/6 MC14069UB

-=_

L_

I
I
I
I
I
I

..J

}MSD
Data Outputs

}LSD
10 pF

I.:___

100_PF.....IT

MC14458

17
22
A3
21
A2

20

A1
AO 19
18
5

3

:J;

23

Data Ready

} Address Outputs

VA
On/Oft
Vol

0.47/L F

Low BandVHF
UHFIVHF
AFT

NOTES:
tBlas used for photodiode only.
*It is mandatory to use an infrared filter In front of the photodiode. Type Kodak 87C or similar.
Select 2N5458 FETs with an lOSS of 2 to 4 rnA.
* *100 pF capacitor should be placed as close as possible to Pin 2 of the MC14458.

*

7-11

•

MC14457, MC14458
FIGURE 6 -

BLOCK DIAGRAM OF A PLL SYSTEM
MC14502B
3 State Inverter

+5V

I

~2
,n

=

r

6

24

9 1---+5 V

MCl4458 16
Remote 15
Receiver
14
12

17

3

5

6

7

1
10

13

PLL
Synthesizer

2
12 Inh

9

Strobe

~
~

*

Decoderl
Driver

III III

,-, ,-,

CI CI
'--

One Shot - Adjust
output pulse width
to give a Iowan Inh
which
IS
long
enough to enter data
without problem.

{>c>--J

Binary
Complement
Diode
Logic

-

II
1

2

"

---{)

"'
3

4

5

6

7

8

9

0

Enter

Note: Enter must be a 0101 In
complementary logic.

FIGURE 7 - BLOCK DIAGRAM OF A TUNING ADDRESS SYSTEM FOR UP TO 256 CHANNELS

•

Band SWitching

SyntheSizer

CMOS
MPU/MCU
R2

7·12

I

PLL

®

MC14469

MOTOROLA

ADDRESSABLE ASYNCHRONOUS
RECEIVER/TRANSMITIER

CMOS LSI

The MC14469 Addressable Asynchronous Receiver Transmitter is
constructed with MOS P-channel and N-channel enhancement devices in a single monolithic structure (CMOSI. The MCl4469 receives one or two eleven-bit words In a serial data stream. One of
the incoming words contains the address and when the address
matches, the MC14469 will then transmit its information In two
eleven-bit-word data streams. Each of the transmitted words contains eight data bits, even parity bit, start and stop bit.
The received word contains seven address bits and the address of
the MCl4469 is set on seven pins. Thus 27 or 128 units can be interconnected in simplex or full duplex data transmission. In addition to
the address received, seven command bits may be received for data
or control use.
The MCl4469 finds application in transmitting data from remote
A-to-D converters, remote MPUs or remote digital transducers to
the master computer or MPU.

(LOW·POWER COMPLEMENTARY MOS)

ADDRESSABLE ASYNCHRONOUS
RECEIVER/TRANSMITTER

• Supply Voltage Range - 4.5 Vdc to 18 Vdc
L SUFFIX
CERAMIC PACKAGE
CASE 734

• Low Quiescent Current - 75/LAdc maximum @ 5 Vdc
• Data Rates to 4800 Baud @ 5 V, to 9600 Baud @ 12 V
• Receive - Serial to Parallel
Transmit - Parallel to Serial

ORDERING INFORMATION

• Transmit and Receive Simultaneously in Full Duplex
MC14xxx

• Crystal or Resonator Operation for On-Chip Oscillator

E~f"

Denotes
Ceramic Package
PlastiC Package

• See also Application Note AN-806
BLOCK DIAGRAMS

PIN ASSIGNMENTS

Transmit

Receive

40
(SO 57)

39

Input Data

38

37'
36

35
34

1
''"''.'~--$~

33

Data
(RII

32

31
30
29
28

27
Pulse (VAP)

26

Clocks
Osc,

0", ~

25

T"",.

24

Data Rate Clock

O.U'HO"

23
22

21

MC14469

This device contains circuitry to protect
the inputs against damage due to high static

MAXIMUM RATINGS (Voltages referenced to VSS. Pin 20.
Symbol

Value

Unit

voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-

VOO

-0.5 to +18

Input Voltage, All Inputs

Vin

-0.5 to VOO + 0.5

Vdc
Vdc

DC Current Drain per Pin

I

10

mAde

TA
T stg

-40 to +85

°c
°c

OC Supply Voltage

Operating Temperature Range

Storage Temperature Range

-65 to +150

mum rated voltages to this high impedance
circuit. For proper operation it

recommended

IS

that V in and Vout be constrained to the range
VSS" (V in or Voutl" VOO·

Unused inputs must always be tied to an
appropriate

logic

voltage

level

(e.g., either

VSS orVOOI.

ELECTRICAL CHARACTERISTICS
Characteristic
putput Voltage
Vin

= Voe

or

Symbol
"0" Level

VOL

a
"1" Level

VOH

Vin=OorVOD
Input Voltage #

"0" Level

(VO
(VO
(VO

= 2.5 Vdcl
= 4.6 Vdcl
= 9.5 Vdcl
= 13.5 Vdcl
(VOL = 0.4 Vdcl
(VOL = 0.5 Vdcl
(VOL = 1.5 Vdcl

(VOH
(VOH
(VOH
(VOH

•

Max

Min

Typ

Max

5.0
10
15

-

0.05
0.05
0.05

-

0
0
0

0.05
0.05
0.05

-

5.0
10
15

4.95
9.95
14.95

-

4.95
9.95
14.95

5.0
10
15

-

4.95
9.95
14.95

5.0
10
15

-

1.5
3.0
4.0

-

-

1.5

3.0
4.0

-

-

2.25
4.50
6.75

1.5

-

3.0
4.0

5.0
10
15

3.5
7.0
11.0

-

3.5
7.0
11.0

2.75
5.50
8.25

-

3.5
7.0
11.0

-

5.0
5.0
10
15

-1.0
-0.2
-0.5
-1.4

-

-0.8
-0.16
-0.4
-1.2

-1.7
-0.35
-0.9
-3.5

-

-0.6
-0.12
-0.3
-1.0

0.44
1.1
3.0

0.88
2.25
8.8

-

0.36
0.9
2.4

-

-0.16
-0.035
-0.08
-0.27

-0.32
-0.07
-0.16
-0.48

-

0.085
0.14
0.42

0.17
0.28
0.84

-

-

-

-

Vdc

-

Vdc

Vdc

-

Vdc

mAde

IOH

Source

Unit

0.05
0.05
0.05

VIH

= 0.5 or 4.5 Vdcl
= 1.0 or 9.0 Vdcl
= 1.5 or 13.5 Vdcl

Output Drive Current (Except Pin 2)

+850 C
Min
Max

Min

VIL

= 4.5 or 0.5 Vdcl
= 9.0 or 1.0 Vdcl
(VO = 13.5 or 1.5 Vdcl
(VO
(VO

"1" Level

25 0 C

-400C

Voo
Vdc

-

-

mAde

5.0
10
15

0.52
1.3
3.6

5.0
5.0
10
15

-0.19
-0.04
-0.09
-0.29

5.0
10
15

0.1

0.17

f max

4.5

400

-

365

550

-

310

-

lin

15

-

±0.3

-

±0.00001

±0.3

-

±1.0

;tAdc

Pull·Up Current (Pins 4-181

IUp

15

12

120

10

50

100

8.0

85·

Input Capacitance

Gin

-

-

-

-

5.0

7.5

-

-

"Adc
pF

100

5.0
10
15

-

75
150
300

-

0.010
0.020
0.030

75
150
300

-

565
1125
2250

"Adc

-

-

+4.5

+18.0

+4.5

-

+18.0

+4.5

+18.0

Vdc

Sink

Output Drive Current (Pin 2 Only)

= 2.5 Vdc)
= 4.6 Vdcl
= 9.5 Vdcl
= 13.5 Vdcl
(VOL = 0.4 Vd~1
(VOL = 0.5 Vdcl
(VOL = 1.5 Vdcl
(VOH
(VOH
(VOH
(VOH

Maximum Frequency
I nput Current

(V in

IOL

mAde

IOH

Source

Sink

-

IOL

0.50

-

-

-

-0.13
-0.03
-0.06
-0.2
0.07
0.1
0.3

-

mAde

kHz

= 01

~uiescent Current

(Per Packagel
iSupply Voltage

VOO

·ll\,Ioise immunity specified for worst-case input combination.

Noise Margin both "1" and "0" level = 1.0 Vdc min @ VOO = 5.0 Vdc
2.0 Vdc min @VOO = 10 Vdc
2.5 Vdc min @VOO = 15 Vdc

7-14

-

MC14469
DATA FORMAT AND CORRESPONDING DATA POSITION AND PINS FOR MC14469 AND MC6850
RECEIVE DATA (RI; Pin 19)

I_

.., I"

-I"'S

Address

----il~~r T T T T T T ,--r T::""""""""'!
~_ 1_1.. L J.. 1.. J.. oJ ,-L PJ 5P
MC14469
Pin Number

4

5

6

7

8

9

10

Command

f---, 5T r T" T ,..

t.:!.L

~ ~

CO Cl

C2 C3 C4 C5 C6

22

17

16

22

Pin Designation

DO 01 02 03 04 05

06

00 01

TRANSMIT DATA (TRO; Pin 21)
) - 1. . . .- - - - -

T
____...!~
~'L .J.
MC14469
Pin Numbers

11

Pm DeSignation

T

Input Data

12

13

14

22 21

00 01 02 03

15

16 17

20

19

19

18

17

33

16

02 03 04 05 06

-1

- - - - - s t a t u s - - - - - -....

18

18 17

28

27

26

25 24

23 22

50 S1

S2

S3 54 55

56 57

29

15

22 21

20 19

17

16 15

04 05 06 07

00 01

02 03 04 05

0607

16

AD ~ A6 = Address Bits
CO -,)0 C6 ~ Command Bits
DO ~ 07 = ACIA Bus Bits

Stop Bit

20

34

T;"1 5PJ";,T T "T "T '"T T "T "T T P" SP
.L::J ~, L .J. ..L ..L .J. ...L ..L .J. ..L ...1'--_ _ _ __

"T T"T "T ,..

Pin Designation

-=

5-P- - - -

.L J. ..J. .J. .J. .L. .L

MC6850
ACIA Pm Number

SP

21

...

------a·-tl~

100101102103104105106107

ST::: Start Bit
P = Parity Bit

"J.,rL

Command
Identifier

37 36 35

MC685Q
AC1A Pin Number

19 18

~

39 38

AD Al A2 A3 A4 A5 A6

20

"T "T ,..

.J. .J. ..I.

' \ Address
Identifier

Pin Designation

21

.....

-,

100 -+ 107
SO .... S7

18

= MC14469 Identification
= MC14469 Status Code

Code

TYPICAL RECEIVE/SEND CYCLE

M
Address

S

~B

VOO

S 0 1 2 34 5 6 7

M
Command
S
S
,,-..'----...,8
P S 0 1 2 3 4 56 7

-'TrXTXTX!XTXTXTX,..,pnTrx-'xrxTxTXTX"X' rp'"

VSS ~~;&;;a;~:.ao~~_~,_~:&::.&:",,~~~ ..

Receiver Input (AI)

1
1

I
Valid Address Pulse
(VAP)

1

~-------------------------------------I
I
(

Internal Valid

~r--------~

Address Latch
(VAL)

,
Internal Send ~r-----'L-.Jf----'

_______________

___________________

Enable Latch

(SELl

Command Strobe
OUtput (CS)

____________

1
~n~

__

~

__________________________

I
Send Input
(Send)

______________- L____

I
~IT'~

_________________________

I

I

M

M

I s s
V
Transmit OUt
(TRO)

'

8

S

8

10

7·15

S

DO Ismx"Tx'TxTxTx"Tx"p1.cl'S1xrxrx rXrxr"X"X'X'p' p - TL:OL!1":2.&.:3.&.:4"'5~~I~

- - - - - - - - - - - - - - - T 0 t2~3~4~5... 61:./-

STATUS

MC14469

DEVICE OPERATION
OSCILLATOR (Osel, Ose2; Pins 1,2) - These pins are
the oscillator input and output. (See Figure 1.)

SECOND or STATUS INPUT DATA (SO-S7; Pins 22, 23,
24, 25, 26, 27, 28, 29) - These pins contain the input
data for the second eight bits of data to be transmitted.

RESET (Reset; Pin 3) - When this pin is pulled low, the
circuit is reset and ready for operation.

SEND (Send; Pin 30) - This pin accepts the send command after receipt of an address.

ADDRESS (AO-A6; Pin 4, 5, 6, 7, 8, 9, 10) - These are
the address setting pins which contain the address match
for the received signal.

VALID ADDRESS PULSE (VAP; Pin 31) - This is the
output for the valid address pulse upon receipt of a
matched incoming address.

INPUT DATA (lDO-ID7; Pins 11, 12, 13, 14, 15,16,17,
18) - These pins contain the input data for the first eight
bits of data to be transmitted.

COMMAND STROBE (CS; Pin 32) - This is the output
for the command strobe signifying a valid set of command
data on pins 33-39.

RECEIVE INPUT (RI; Pin 19) - This is the receive input
pin.

COMMAND WORD (CO-C6; Pins 33, 34, 35, 36, 37, 38,
39) - These pins are the readout of the command word
which is the second word of the received signal.

NEGATIVE POWER SUPPLY (VSS; Pin 20) - This pin is
the negative power supply connection. Normally this pin
is system ground.

POSITIVE POWER SUPPLY (VDD; Pin 40) - This pin is
the package positive power supply pin.

TRANSMIT REGISTER OUTPUT SIGNAL (TRO; Pin
21) - This pin transmits the outgoing signal. Note that it
is inverted from the incoming signal. It must go through
one stage of inversion if it is to drive another MC14469 .

•

OPERATING CHARACTERISTICS
The receipt of a start bit on the Receive Input (R I) line
causes the receive clock to start at a frequency equal to
that of the oscillator divided by 64. All received data is
strobed in at the center of a receive clock period. The start
bit is followed by eight data bits. Seven of the bits are
compared against states of the address of the particular
circuit (AO-A6l. Address is latched 31 clock cycles after
the end of the start bit of the incoming address. The
eighth bit signifies an address word "1" or a command
word "0". Next, a parity bit is received and checked by the
internal logic for even parity. Finally a stop bit is received.
At the completion of the cycle if the address compared, a
Valid Address Pulse (VAP) occurs. Immediately following
the address word, a command word is received. It also
contains a start bit, eight data bits, even parity bit and a
stop bit. The eight data bits are composed of a seven-bit
command, and a "0" which indicates a command word.
At the end of the command word a Command Strobe
Pulse (CS) occurs.

A positive transition on the Send input initiates the
transmit sequence. Send must occur within 7 bit times of
CS. Again the transmitted data is made up of two elevenbit words, i.e., address and command words. The data
portion of the first word is made up from Input Data inputs 1100-107), and the data for the second word from
Second Input Data (SO-S7) inputs. The data on inputs
100-107 is latched one clock before the falling edge of the
start bit. The data on inputs SO-S7 is latched on the riSing
edge of the start bit. The transmitted signal is the inversion of the received signal, which allows the use of an inverting amplifier to drive the lines. TRO begins either Y, or
1 y, bit times after Send, depending where Send occurs.
The oscillator can be crystal controlled or ceramic
resonator controlled for required accuracy. Pin 1 may be
driven from an external oscillator. See Figure 1.

7-16

MC14469

FIGURE 1 - OSCILLATOR CIRCUIT

I
I
I
I

L

FIGURE 2 - RECTIFIED POWER FROM DATA LINES CIRCUIT

MC14469
Internal

1.0 k typ

L----1~---.....- - - - - -.....- - Data Line
Ground Line

Pin 1
15 M

Pin 2
Note: For externally

AI

generated clock,
drive Pin 1, float Pm 2.

1.0 IJ.F

Note: CeramIc Resonators
307.2 kHz ± 1 kHz for 4800 Baud Rate
C1 ~ 50pF
C2 <::: 200 pF
(CeramIc Resonator Suppliers:
RadIo Materials Company, Chicago. Illinois
Vernitron Piezoelectric Division, Bedford, Ohio)

MC14469

.........---!V88

FIGURE 3 - A-D CONVERTER INTERFACE

CO
C1

Channel
I--------------....-l Select

C2
Select
C8

f----------------..l

Channel,

Start
Conversion

Send

1 - - - - - - - - - - - - - - - 1 ~:~version

Analog

Inputs

80
81
82
83 t4------------------l Digital
84 1 - - - - - - - - - - - - - - - 1 Outputs
85
86
81

MC14469

a-Channel

AID Converter
Assembly

7·17

14----14-----

I
3:

o....

:t

m

FIGURE 4 - SINGLE LINE. SIMPLEX DATA TRANSMISSION
V+

VOO

1 k

MPS·D05

10 k

10 k

10 k

-;-s

......
en

AI

TAO

AI

10 k

RI

TAO

VOO

vssl

••

Vss

I

••

Vss

I

••

S7
MC14469

o

UAAT

TAO

107

S7
MC14469

10 k

VOO

107

S7

MC6850
ACIA

RI

TRO

VOO

107

10 k

10 k

MC14469

AD. 100

Address
0000001

A',101
A2,I02

A1,ID1

Address

A2,102

1111111

127

A3.ID3

A3; 103
A4,I04
A5.ID5

cs

A6.106

Send

A4,104
AS, IDS
A6, IDS

cs

cs

Send

Send

Address
0000000

Master
Station

Remote MC14469 Stations

Note: For Simplex operation the 101 must be tied high, 57 must be
tied low and the 7-bit 10 must be the same as the 7-bit address

(or set to some unused address) to prevent erroneous responses.

s:::

n
.....

t

0)

FIGURE 5 - DOUBLE LINE, FULL DUPLEX DATA TRANSMISSION

v+

k

CD

V DD

<

1 k

<

MPS-D05
MPS-D05

MPS-D05

10 k

<

>

'"Ort:

rl::

10k?

";'I

~

~

CO

~
AI

TAO

AI

<

10 k

L.-

~

I

or
UART

I
I

I
I
I
Master

Station

RI

TRO

TRO

VOD

VSS

VSS

-

10 k

10 k

10k

V DD

-:::::-

a

000000

?

VSS

MC14469

Address

MC685Q
ACIA

rt

10k

RI

TAO

VDD

VSS

-'-

?

10 k

MPS-005

-:::3'

MC14469
1

MC14469

AO
t:-- Al
~ A2
A3
~ A4
~ AS
I-- A6

Address

~

.-

0000001

-

~

r-~

VAP
Send

=:J

~

r--

A ddress
1 11111

VAP
Send

-Remote MC14469 Stationt.

Al
A2
A3
A4
AS
A6

tJ

127

VAP
Send

I

••

MC14469

FIGURE 6 - FLOW CHART OF MC14469 OPERATION
Receive

N

PrevIous

Transmission

•
VAL and SE L are Internal latches.

* Data format for
1
8
1
1

SEL
Control

7-20

both transmIt and receive consists of:

Start
Data
Even
Stop

Bit
Bits
Parity Bit
Btt

®

MCl4497

MOTOROLA

CMOSMSI

PCM REMOTE CONTROL TRANSMITTER

(LOW-POWER COMPLEMENTARY MOS)
The MC14497 IS a PCM remote control transmitter realIZed in CMOS
technology_ USing a dual-single IFSKI AM) frequency blphase modulation, the transmitter IS designed to work with the MC3373 receiver

PCM REMOTE CONTROL
TRANSMITTER

• Both FSKI AM Modulation Selectable

• 62 Channels - Up to 62 Keys
• 500 kHz Reference Oscillator Controlled by Inexpensive Ceramic

,-

Resonator
•
•
•
•

Very Low Duty Cycle
Very Low Standby Current
Infrared Transmission
Selectable Start-Bit Polanty lAM only)

• Shifted Key Mode Available
• Wide Operating Voltage Range 4 to 10 Volts

1

P SUFFIX

PLASTIC PACKAGE
CASE 707

FIGURE 1 - BLOCK DIAGRAM

r1111t---.-------.
':voo

r------------

18

--------,
I

PIN ASSIGNMENT

I
I
I
8

E3

A4

'[iiV1ii

17 E1

E9 3

16 E4

A4 4

15 E5

A3 5

14 E6

A2 6

13 OSCout

A1

12 Oscm

Signa) Out 8
VSS 9

Resonator

T.,.

T....

7-21

VDD

E2 2

11

E8

10~ E7

MC14497
MAXIMUM RATINGS IVoltages Referenced to VSSI
Symbol
Rating
DC Supply Voltage
VDD
Input Voltage, All Inputs
Vin
DC Input Current per Pm
lin
Operating Temperature Range
TA
Storage Temperature Range

Tstg

Value

Unit

-05to+15

V
V

-05 to VDD+0.5
±10
+ 70

o to

-65 to + 150

mA
'C
'C

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electriC fields; however, it IS advised that normal precautions be taken to
avoid application of any voltage higher than

maximum rated voltages to this hIgh impedance circuit. For proper operation It IS

recommended that V in and Vout be constrained to the raf)ge VSSs(V m or

VoutlsVDD·

•

ELECTRICAL CHARACTERISTICS ITA ~ 0 to 70'C' all Voltages Referenced to VSSI
Pin
Characteristic
Symbol
VDO
Supply Voltage
18
VOD
Supply Current
18
IDO
Idle
10
Operation
10
Output Current - Signal
8
Source
4
VOH~30V
IOH
VOL~0.5V
Sink
4
IOL
Output Current - Scanner
4,5
Source
6,7
4
VOH~3.0V
IOH
Sink
4
VOL~05V
IOL
Output Current - Oscillator
13
4
Source
VOH~30V
IOH
Sink
4
VOL ~0.5 V
IOL
Input Current - Oscillator
12
lin
Operation
10
Idle, VIL;05V
4
Input Current
Decoder
1,2,3, 10
lin
11, 14, 15
10
VIH~9 V
16,17
4
VIL ~O 5 V
Input Voltage
1,2,3,10
Decoder
11,14,15
10
VIH
16, 17
10
VIL
4
VIH
4
VIL

7-22

Min
4.0

Max
10.0

Unit
V

-

50
5

p.A
mA

-900
120

-

-30
245

-

-300
245

-

±2
30

±80

p.A

p.A

p.A

p.A

p.A

-15

-

-

-60

9
3

12

-

10

V

-

MC14497
CIRCUIT OPERATION
The transmitter sends a 6-blt, labelled A (LSBI to F
(MSBI, binary code giVing a total of 64 possible combinations or code words. All of these channels are user selectable, except the last two - where channel 63 is not sent
while channel 62 is automatically sent by the transmitter at
the end of each transmission as an "End of Transmission"
code.
In either mode, FSK or AM, the transmitted signal IS In the
form of a blphase pulse code modulation (PCMI signal The
AM coding IS shown in Figure 2.

puts (see Figure 41. These have the effect of producing
"phantom" address Inputs by pulling two inputs low at the
same time, which causes bit-F to go high, that is to logical
"1". By Interconnecting only certain address Inputs it is
possible to make an intermediate keyboard with between 32
and 64 keys
The other two sWitches on Figure 1, FK 1 and FK2, change
the modulation mode. ClOSing FK1 changes the modulation
from FSK to AM and the start-bit polarity. ClOSing FK2
changes the start-bit to a logical "0".
The full range of options available is Illustrated in the table
below:

FIGURE 2 - AM CODING

--J

r-

bit-n

I

"O"~
I

I

AM

I

I

Start-bit

Modulation

Bit-F

Channels

E9=Open

1

FSK

0

0-31

E9=AlIFK1J

1

AM

0

0-31

E9= A2 IFK2J

0

FSK

0

0-31"
32-61

I

E9= A3 IFK3J

1

FSK

1

I

E9=Al.A2

0

AM

0

0-31

E9=Al.A3

1

AM

1

32-61

E9= A2.A3

0

FSK

1

32-61*

E9=A1.A2.A3

0

AM

1

32-61

"1"J,LL

*Not allowed

In the AM mode, f1 IS a train of pulses at the modulating
frequency of 31.25 kHz for a reference frequency of 500 kHz.
In the FSK mode, two modulating frequencies are used as
shown In Figure 3

One of the transmitter's major features IS its low power
consumption - in the order of 10 p.A In the idle state. For this
reason the battery is perpetually in Circuit. It has in fact been
found that a light discharge current is beneficial to battery
life.
In ItS active state, the transmitter efficiency is increased by
the use of a low duty cycle which is less than 2.5% for the
modulating pulse trains.
While no key is pressed, the cirCUit is In its idle state and
the reference oscillator is stopped. Also, the eight address
input lines are held high through internal pull-up resistors.
As soon as a key IS pressed, this takes the appropriate address line low, signalling to the circuit that a key has been
selected. The oscillator is now enabled. If the key is released
before the code word has been sent, the circuit returns to ItS
Idle state. To account for accidental activation of the
transmitter, the cirCUit has a built-in reaction time of
- 20 ms, which also overcomes contact bounce. After this
delay the code word will be sent and repeated at 90 ms intervals for as long as the key is pressed. As soon as the key is
released, the cirCUit automatically sends channel 62, the
"End of Transmission" (EOTI code. The transmitter then
returns to its idle state.
The differences between the two modulation modes are illustrated in figure 5. However, it should be noted that in the
AM mode, each transmitted word is preceded by a burst of
pulses lasting 512 p.s. ThiS IS used to set up the AGC loop in
the receiver's preamp. In the FSK mode, the first frequency
of the first bit is extended by 1.5 ms and the AGC burst IS
suppressed. In either mode It IS assumed that the normal
start-bit is present.

FSK CODING

FIGURE 3 -

I

blt-n

I

"O"~
FSK

I

I

I

I

I

I

I

I

I

"1"~

In this mode, f3 IS 50 kHz and f2 is 41.66 kHz for a
reference frequency of 500 kHz.
The keyboard can be a simple sWitch matrix uSing no
external diodes, connected to the four scanner outputs, A 1
to A4, and the eight row Inputs, E1 to E8. Under these conditions, only the first 32 code words are available since blt-F is
always at logical "0" However, a simple two-pole changeover switch, In the manner of a typewroter "shift" key
(switch FK3 In figure 11 can be used to change the polanty of
blt-F to give access to the next full set of 32 Instructions.
An alternative method of accessing more than 32 instructions IS by the use of external diodes between the address in-

7-23

MC14497
FIGURE 4 - 64-KEY KEYBOARD

PIN DESCRIPTIONS
El to EB, ROW INPUTS (PINS 1,2, 10, II, 14, 15, 16,
AND 171 - Under idle conditions, these inputs are held high
by internal pull-up resistors. As soon as a key is pressed, a
logical "0" on that particular line signals to the circuit that a
key has been selected. After a delay of 20 ms, the mternal
register is loaded with the code word for the key selected.
EB, ROW INPUT (PIN 3) - This is a special programming
input and when connected to the appropriate scanner output
via a diode, it will modify the transmitted output according to
the table in the Circuit Operation section.
In that table, the figures in brackets, FK 1, etc., refer to the
switches shown in Figures 1 and 4. If only one option is required, the diode may be omitted. The connections shown in
the table may be made in any combination.
Although E9 is a row input. forcing this line low will not
activate the circuit.
AI to A4, SCANNER OUTPUTS (PINS 4,5,6 AND 7) Under idle conditions, these outputs are held low, logical
"0". When a key is pressed, the circuit is activated and the
oscillator will start and release the outputs (see Figure 61.
OSCin, OSCout, OSCILLATOR INPUT AND OSCILLATOR
OUTPUT (PINS 12 AND 13) - These are designed to
operate with a 500 kHz ceramic resonator or a tuned LC circuit. It is important that a ceramic resonator and not a filter
be used here, as the oscillator frequency cannot be
guaranteed if a ceramic filter is used.
Signal Out, SIGNAL OUTPUT (PIN 8) - This output provides the modulating Signal ready to drive the modulation
amplifier. If required, the transmitter can be used as a
keyboard encoder for direct use with a receiver. In this case,
the AM option is selected, the output inverted and fed
directly to the receiver's signal input pin.

•

r

fd

t" l"

~"

vssr1111f-,v DD

~

El 17 9

~" 1:"

~" . ~"E1
~ 3;"

1/

~"

~"

3;"

~.

J.d

J!'

~.

~.

~" E3a

~"
~"

~" 'J,d

"t"

E2 2

E2a
E3 1

~.

E4 16

J." ;d

~

r," E4a

1"
r,"

'J,d

"t"

~"

~

'$"

~d E5a

E5 15

rl '11' J." 3;d
rl r,d J.d rl E6a
ri '11' r," 'f,d
r,d

3;"

~"

-r,d

r,"

3;"

Y,d E7a
r,d

1:"

l:"

Y,"

'J," EBa

E6 14
E7 10

EB 11
A1
A2
A3
A4

Ik2 ~

~

IIk1

~

7
6
5
43

A

B

Note: MaXImum key contact resIstance = 1 kG

c

D

FSK

AM

1 Word

~r__l~____~~.1~
j . - - 2 0 m s - - + l 9ms I+-

+____

De_bou_nc_e_ _

~99ms

7·24

13

~~

Instruction

Key Down

12

El~(]tC2

FIGURE 5 - TRANSMITIED WAVEFORMS AND TIMING

Start Bit

1B

____

MC14497

FIGURE 6 - SCANNER OUTPUT TIMING DIAGRAM

+

Key Down

Key Released

Debounce

Al

ILJ

U

U

A2

U

A3

IL
U
IL
UL

U

A4

FIGURE 7 -

TYPICAL APPLICATION CIRCUIT

KBD

*Vrsrble IndIcator

7·25

+

L~

MC14497

TABLE 1 -

CodeWord
Channel
0
1
2
3

F E 0 C B A
0

0

4
5
6
7
B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

0

0

0
0
0
0
1
1
1
1
1 0
0

0

0

0

1 0

0

0

1

1

29
30
31

•

0
1
1
1
1
0

0

1

1

0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
0
1
0
1
0
1
0
1

TRANSMITIEO CODES

Keyboard
In
Out
EB
El
E2
E3
E4
E5
E6
E7
E8
El
E2
E3
. E4
E5
E6
E7
EB
El
E2
E3
E4
E5
E6
E7
EB
El
E2
E3
E4
E5
E6
E7

A4
A4
A4
A4
A4
A4
A4
A4
Al
Al
Al
Al
Al
Al
Al
Al
A3
A3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A2
A2
A2

CodeWord
C B A

Channel

F E

o

32

1 0

0

33
34
35
36
37

38
39

40

1

0

1

1

1

1

1

1

41
42
43

44
45
46
47

48
49
50
51
52
53

54
55

56
57

56
59
50
61
62 lEOTI

Not transmitted

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1 1

Keyboard
In
Out
E8a
Ela
E2a
E3a
E4a
E5a
E6a
E7a
EBa
Ela
E2a
E3a
E4a
E5a
E6a
E7a
EBa
Ela
E2a
E3a
E4a
E5a
E6a
E7a
E8a
Ela
E2a
E3a
E4a
E5a
E6a
E7a

A4
A4
A4
A4
A4
A4
A4
A4
Al
Al
Al
Al
Al
Al
Al
Al
A3
A3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A2
A2
A2

NOTE: Although the" a" suffix applies to a phantom Input
when uSing a keyboard with up to 64 keys, the coding IS
identical with a 32 key keyboard when SWitch FK3 IS closed.

7·26

®

MC145026
MC145027
MC145028
MC145029

MOTOROLA
Advance InforIllation

CMOS MSI
(LOW-POWER COMPLEMENTARY MOS)

MCl45026 ENCODER,
MCl45027/MCl45028/MCl45029 DECODERS

REMOTE CONTROL
ENCODER/DECODER PAIRS

The MC145D26 will encode nine bits of Information and senally
transmit this information upon receipt of a transmit enable, TE, lactlve
low) signal. Nine Inputs may be encoded with trinary data 10, 1, open)
allowing 39 119,683) different codes.
Three decoders are presently available; all use the same transmitter
- the MC145D26. The decoders receive the 9-bit word and Interpret
some of the bits as address codes and some as data. The MC145027 interprets the first five transmitted bits as address and the last four bits as
data. The MC145029 Interprets the first four transmitted bits as address
and the last five bits as data. The MC145028 treats all nine bits as address. If no errors are received, the MC145027 outputs four data bitS,
and the MC145029 outputs five data bitS, when the transmitter sends
address codes that match that of the receiver. A valid transmission output Will go high on the decoders when they recognize an address that
matches that of the decoder Other receivers can be produced with different address! data ratios
•
•
•
•
•
•
•
•

May be Addressed In either Binary or T nnary
Tnnary AddreSSing MaXimizes Number of Codes
Interfaces with RF, Ultrasonic, or Infrared Transmission Medias
On-Chip R!C Oscillator; No Crystal ReqUired
High External Component Tolerance; Can Use ± 5% Components
Standard B-Senes Input and Output Charactenstics
4.5 to 18 V Operation
2.9 V Low-Voltage Version Also Available by Special Order

L SUFFIX
CERAMIC PACKAGE
CASE 620

-

..

MC14XXXX

TC

P SUFFIX
PLASTIC PACKAGE
CASE 648

Suffix

Denotes

L
P

Ceramic Package
PlastiC Package

PIN ASSIGNMENTS

Al/Dl

VDD

Al

lb

VDD

Al

16

A2/D2

Data Out

A2

15

06

A2

15

A6

A3/D3

TE

A3

14

07

A3

14

A7
AS

M/D4

RTC

M

A5/D5

CTC

A5

4

13

DB

A4

13

12

09

A5

12

VDD

A6/D6

Rs

Rl

11

VT

Rl

11

A7/D7

A9/D9

Cl

10

R2/ C2

C1

10

10

R2/C2

Vss

AB/DB

Vss

9

Data In

VSS

9

9

Data In

MCl45028
Decoder

MC145029
Decoder

MC145026
Encoder

MC145027

Decoder

ThiS document contains Information on a new product Specifications and Information herem are subject to change without notice

7·27

•

MC145026, MC145021, MC145028, MC145029
MAXIMUM RATiNGS (Voltages Referenced to VSSI
Rating

Symbol

Value

VDD
V,n

- 05 to + 18

DC Supply V01tage
Input Voltage, AI11nputs

Unit

V
V

05 to VDD+O 5
±10

DC Input Current, per Pin

I,n

Operating Temperature Range

TA

-40 to +85

'C

T st(t

-65 to +150

'C

Storage Temperature Range

mA

ELECTRICAL CHARACTERISTICS
Characteristic
Output Voltage
V,n=VDD or 0

Symbol

Vee
V

VOL

Max

Min

Max

0
0
0

0.05
005
005

-

005
005
005

50
10
15

-

495
9.95
1495

-

-

225
4.50
625

15
30
40

-

15
30
40

-

35
70
110

275
550
8.25

-

35
70
11.0

-

-

-2.1
-044
-1.1
-30

-4.2
-088
-2.25
-8.8

-

-

0.44
11
3.0

0.88
2.25
88

-

-1.7
-036
-09
-24
036
0.9
24

30
16
35

4.0
20
45

90
32
70

-

-

±03

-

±O.OOOOl

±03

-

-

-

±55
±300
±650

±11O
±5OQ
±1000

-

-

-

-

-

50
10
15

-

005
005
005

50
10
15

495
995
1495

-

50
10
15

-

-

15
30
40

50
10
15

35
70
11.0

50
50
10
15

-25
-0.52
-1.3
-3.6

5.0
10
15

052
13
36

50
10
15

-

15

-

5.0
10
15

-

CIO

-

-

-

IDD

50
10
15

"1" level
VOH

Input Voltage
IVo=450r05VI
IVo=900r 1 OVI
IVo=1350r 15VI

25'C
Typ

Max

"0" level

V,n=O or VDD

-40'C
Min

-

-

Min

-

495.
995
1495

+85'C

-

Unit

V

V

-

"0" Level

Vil

V

"1" level
IVO = 05 or 4 5 VI
IVO= 10 or 9.0 VI
IVo=150r 135VI

VIH

Output Drive Current
IVOH =2.5 VI
IVOH =4.6 VI
IVOH =9 5 VI
IVOH=135VI

Source
IOH

SIOk

IVOl=04VI
IVOl = 0.5 VI
IVOL=15VI

IOl

Input Current - TE IMC145026, Pullup Devlcel
110

•

V

-

-

-

-

-

-

rnA

-

rnA

~A

Input Current

RS IMC1450261

110

±10

~A

Data In IMC145027, MC145028, MC1450291
Input Current
Al/Dl-A9/D9IMC1450261
Al-A5IMC1450271
A1-A9IMC1450281
A1-A4 IMC1450291

}

Input Capacitance IV IO - 01
Guiescent Current - MC145026

lin

GUlescent Current - MC145027, MC145028, MC145029
IDD
Total Supply Current- MC145026 it c - 20 kHzI
IT
Total Supply Current -

I

MC145027, MC145028, MC145029
itc= 20 kHzI

IT

50
10
15
50
10
15
50
10
15

-

-

-

-

-

-

-

50

75

00050
00100
00150

010
0.20
0.30

30
90

50
100
150

100
200
300

200
400
600

200
400
600

400

60

800
1200

-

-

-

-

-

~A

pF

-

-

~A

-

-

~A

-

-

~A

~A

ThiS dev,ce contalOs CIrcuitry to protect the Inputs agalOst damage due to high static voltages or electriC fields, however, It IS adVised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to thiS high Impedance CirCUit. For proper operation It IS recommended that Vm and V out be constrained to the range VSS ~ (V ln or Vout1 s VOD

7-28

MC145026, MC145027, MC145028, MC145029
SWITCHING CHARACTERISTICS ICL = 50 pF TA = 25'C)
Symbol

Characteristic

Output A,se and Fall Time

VOO

Min

Typ

50
10
15
5.0
10
15
5.0
10
15
5.0
10
15
50
10
15

-

100
50
40

65
30
20

-

-

-

-

ns

-

-

-

182

-

Clock
Cycles

-

-

-

-

±25
±25

%

-

tTLH
tTHL

Data In Rise and Fall Time (MCI45027, MCI45028, MC1450291

tTLH
tTHL

Encoder Clock Frequency

tel
Decoder Frequency

IAeferenced to Encoder Clock I ISee Figure 101

fel

TE Pulse Width
tWL
System Propagation Delay

(TE to

Valid Transmission)

-

0
0
0
1
1
1

-

Ma.
200
100
SO
15
15
15
2
5
10
240
410
450

Unit

ns

~s

MHz

kHz

Tolerance on Timing Components

(aATC + aCTC + aA 1 + aCll
laA2+aC21

OPERATING CHARACTERISTICS
bits and must be encoded to match the address rnput at the
receiver If the address bits match, the next four Idatal brts
are stored and compared to the last valrd data stored. As the
second encoded word IS received, the address must agarn
match, and rf rt does, the data b,ts are checked against the
prevrously stored data bits. If the two words of data (four
bits each) match, the data IS transferred to the output data
latches by VT and will remain until new data replaces it. At
the same time, the Valid Transmrssron output pin rs brought
high and wrll remain high untrl an error IS received or until no
Input signal IS received for four data b,t times.
Although the address Information IS encoded In tnnary,
Ihe data Information must be erther a one or a zero. A tnnary
(open) wrll be decoded as a logiC one

MCl45026
The encoder senally IransmllS nine b,ls of Innary dala as
defined by Ihe slale of Ihe Al/D1-A9/D9Inpul pinS These
pinS may be In ellher of Ihree Slales (0, 1, openl allOWing
39 = 19,683 possible codes The Iransmll sequence IS InIllaled by a low level on Ihe TE Inpul pin. Each lime Ihe IT InPUI IS forced low Ihe encoder oulpulS two Identical data
words. Between Ihe Iwo dala words no signal IS sent for
Ihree data bit times If the IT Input IS kept low, the encoder
continuously transmits the data word
Each transmitted data bit IS encoded rnto two data pulses
(See Figure 71 A logic zero IS encoded as two consecutive
short pulses, a logiC one as two consecutive long pulses, and
an open as a long pulse followed by a short pulse The Input
state IS determined by uSing a weak output devrce to try to
force each Input frrst low, Ihen high. If only a high state
results from the two tesls, the Input rs assumed to be hard
wrred to VDD. If only a low state IS obtained, the Input IS
assumed to be hard wrred to VSS If both a hrgh and a low
can be forced at an Input, It IS assumed to be open and IS encoded as such.
The IT input has an Internal pullup devrce so that a srmple
sWitch may be used to force the rnput low. Whrle'IT rs high
the encoder rs completely disabled, the oscrllator IS Inhibited,
and the current drain is reduced to qUiescent current. When
IT IS brought low, the oscrllator is started, and the transmit
sequence begrns. The inputs are then sequentrally selected,
and determrnatrons are made as to the Input logiC states.
ThiS Information IS senally transmitted via the Data Out
output pin.
Transmlssron must be initiated by usrng the TE pin rather
than by holdrng IT low and applying power to the deVice
because an Internal reset occurs after the frrst transmit
sequence.

MCl45028
ThiS decoder operates In the same manner as the
MC 145027 except that nine address bits are used and no data
output IS available. The Valrd Transmission output rs used to
Indicate that a valid address has been received
Although address Information IS normally encoded In
tnnary, the deSigner should be aware that. for the
MC145028, the ninth address bit (A9) must be either a one or
a zero Thrs part, therefore, can accept only 2 x 38= 13,122
drfferent codes. A tnnary (open) A9 Will be rnterpreted as a
logiC 1. However, rf the encoder sends a tnnary (or logrc 1I
and the decoder address rs a logiC 1 (or tnnary) respectrvely,
the valrd transmrssron output length wrll be shortened to the
R1 x C1 time constant.

MC145029
Thrs decoder operates like Ihe MC145027, but It assumes
the frrst four received bits to be address bits and the remainIng f,ve received brts to be dala

DOUBLE TRANSMISSION DECODING

MCl45027
ThiS decoder receives the senal data from the encoder and
outputs the data, If It IS valrd. The transmitted data, conslstrng of two Identrcal data words, IS examined bit by bit as
It IS recerved The frrst five b,ts are assumed to be address

Although the encoder sends two words for error checking,
a decoder does not necessanly wart for two transmitted
words to be recerved before rssulng a valid transmiSSion output

7-29

MC145026, MC145027, MC145028, MC145029
PIN DESCRIPTIONS
R1, C1, PULSE DISCRIMINATOR (PINS 6, 7) - These
pins accept a resistor and capaclto'r that are used to determine whether a narrow pulse or a wide pulse has been encoded The time constant R, x C, should be set to '.72 encoder !transmltterl clock periods. R,C, = 3.95 RTCCTC.

MC145026 ENCODER
A1/D1-AS/D9, ADDRESS/DATA INPUTS (PINS ',2,3,
4,5,6, 7, 9, 10) - These Inputs are encoded and the data IS
serially output from the encoder.
RS, CTC, RTC, OSCILLATOR COMPONENTS (PINS 11,
12, 13) - These PinS are part of the oscillator section of the
encoder. If an external signal source IS used Instead of the
Internal oscillator, It should be connected to the RS Input
and the RTC and CTC pins should be left open.
fE, TRANSMIT-ENABLE INPUT (PIN 14) This aClive low
input initiates transmission when forced low An Internal
pullup device keeps this Input normally high.
Data Out, DATA OUTPUT (PIN 15) - This IS the output
of the encoder that serially presents the encoded word.
VDD, POSITIVE SUPPLY (PIN 16) power supply.

The most positive

VSS, NEGATIVE SUPPLY (PIN 8) supply (usually groundl.

The most negative

R2/C2, DEAD TIME DISCRIMINATOR (PIN 10) - This
Pin accepts a resistor and a capacitor to VSS that are used to
detect both the end of an encoded word and the end of
transmission. The time constant R2 x C2 should be 33 5 encoder (transmitter I clock periods (four data bit perlodsl.
R2C2 = 77 RTCCTC. ThiS time constant IS used to determine that Data In has remained low for four data bit times
(end of transmission I. A separate comparator looks at a
voltage-equivalent two data bit times (OA R2C21 to detect
the dead time between transmitted words.
VT, VALID TRANSMISSION (PIN 11) - ThiS output goes
high when the follOWing conditIOns are satisfied
1. the transmitted address matches the receiver address, and
2. the transmitted data matches the last valid data received
IMC145027 and MC145029, onlyl
VT Will remain high until a mismatch IS received, or no input Signal IS received for four data bit times

MCl45027, MC145028, MCl45029 DECODERS
Al-A5 (MC145027), Al-A9 (MC145028), Al-A4
(MCl45029), ADDRESS INPUTS - These address Inputs
must match the corresponding encoder Inputs In order for
the decoder to output data.
D6-D9 (MC145027I, DS-D9 (MCl45029), DATA OUTPUTS - These outputs present the Information that IS on
the corresponding encoder inputs. Note: only binary data
will be acknowledged; a trinary open Will be decoded as a
logic one.

VDD, POSITIVE SUPPLY (PIN 16) power supply.

The most positive

VSS, NEGATIVE SUPPLY (PIN 8) - The most negallve
supply (usually groundl

FIGURE 1- MCI45026 ENCODER BLOCK DIAGRAM

•

3-PIn
OSCillator

and
Enable

Data Select

-4
DIVider

Data
Out

and
Buffer

Ring Counter and 1-of-9 Decoder

98765432

~VDD
~VSS
'="

Tnnary
Detector

7·30

MC145026, MC145027, MC145028, MC145029
FIGURE 2 - MCl45027 DECODER BLOCK DIAGRAM

Sequencer
CtrC:Ult

4

Al
A2
9

Data

A3

Extractor

Data
In

A4

~VDD

A5

~VSS

FIGURE 3 - MCl4602B DECODER BLOCK DIAGRAM

Control
Logic

~

Valid

l...Y' Transmission

Sequencer CircUIt

6

4

Al

9-Blt
Shift
Register

A2
A3

A4
~Data
~In

Data

A5

~VDD

A6

C2

~ ~VSS

610

A7

R2

AB

':'

A9

7-31

':"

1
":'

MC145026, MC145027, MC145028, MC145029
FIGURE 4 - MC145029 DECODER BLOCK DIAGRAM

Valid
Transmission

D5

06

07

Sequencer
Circuit
3
2

4

09
A1
A2

9 Data

Data
Extractor

A3

L--<2TI

A4

FIGURE 5 -

•

In
VDD

ENCOOER OSCILLATOR INFORMATION

RS
CTC

-11

RTC

12

13

I
I
This oscillator will operate at a frequency determined by the external RC network,

Ie,

f=

1

IHzl

2.3 RTC CTC'
for 1 kHzsfs400 kHz
where: CTC' = CTC + Clayou! + 12 pF
RS~2 RTC
RS",20k
RTC'" 10 k
400 pF< CTC< 15 jLF

The value for RS should be chosen to be '" 2 times RTC ThiS
range Will ensure that current through RS IS Insignificant compared
to current through Rrc. The upper limit for RS must ensure that
RS x 5 pF (Input capacItance) IS small compared to Rrc x eTC·

For frequencies outside the indicated range, the formula Will be
less accurate. The minimum recommended oscillation frequency of
thiS Circuit IS 1 kHz. Susceptibility to externally mduced noise signals
may occur for frequencies below 1 kHz and/or when resistors utilized are greater than 1 MO.

7·32

MC145026, MC145027, MC145028, MC145029
FIGURE 6 -

1+--+1 PW min

ENCODER/DECODER TIMING DIAGRAM

MCl46026 ENCODER

fE'-J ___________________________________________ "_________ con~n~~~~ ~;:~:;::::~~
.... NMoqU)CO

~~~~~~~~g ~oo~frid5~~~@

~::!~~~~~~~~

EncoderOscllla~ ~JlJ1JlfUU1JlJ1MMY~
(Pin

12)

\+-ls1 BII--+I

.
BII.-j

f4-~lh

\+-lst Blt--+l

DataDul(Plnl_5)_ _ _--II~~~

I-- One -I+- T"nary~ Zero.--I
I.
1st Word
_I

f4-9th Blt~

~

t

j.,·._---2nd Word---1I--+I

MCl46027, MCl45028, AND MC146029 DECODERS

1.1 (R2C2)

Valid Transmission (Pin 11)

-------------------------------------------------------~

-'X'-______

Dala DuIPu:,:ts'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

FIGURE 7 -

MC146026 ENCODER DATA WAVEFORMS

Encoder
OscIllator
(Pin 12)

Encoded
"One"

Data
Out
(Pm 15)

U

~

Encoded
"Zero"

Jl

Encoded
"Open"

.-J
II"

n
Lfl
Data Pulse
Penod

·1
Data Bit Period

7·33

L
I
I

I
I

MC145026, MC145027, MC145028, MC145029
FIGURE 8 - MCl46027/MCl4S029 FLOWCHART

No

Disable VT
on the 1st
Address Mismatch
and Ignore the
Rest of This Word

Store
the
Data

No

•

Disable VT
on the 1st
Data Mismatch

Latch Data
Onto Output
Pins and
Activate VT

Yes

7-34

Disable
VT

MC145026, MC145027, MC145028, MC145029
FIGURE 9 -

MCl46028 FLOWCHART

No

Serially Shift the
Address ("1" ~ "1"1'
Into the Storage
Register up Until
~I e , Excluding) the
1st Mismatch

Store
the
Address
("1" ~ "1"1'

No

Shift In
an Extra
"1"

Yes

No

Disable

VT
Activate

VT

Yes

Disable

VT

"For shift register comparisons, a "T" IS stored as a "1"

7-35

•

MC145026, MC145027, MC145028, MC145029· .
FIGURE 10 - fmax vs Cia'{out
MC145027, MC14502B, and MC145029

•

10

20

30

40

Clayout IpFI on Pins 1-5 IMC1450271, Pms 1-5 and 12-15 IMC1450281;
Pms 1-4 IMC1450291

7-36

50

3:
0

..A.

FIGURE 11 - TYPICAL APPLICATION

0
N
~

CTC' = CTC+ Clayout+ 12 pF
100 pF:s CTC:S 15 ~F
RTC2:10 k. RS-2 RTC
RI2: 10 k
CI2:400 pF
R22: 100 k
C22: 700 pF

VDD

VDD

~

en

hO.l~F
I

O.l~F

13

.....,
W
.....,

Binary

Data

{

en

.:"'I
3:

6
Tnnary

MC145027

Addresses

Rl

I

11

15
D6
14
D7
13
D8
12
D9
11

C1

10
RS
R2

1

fose

=2.3 RTCCTC'

R1Cl =3.95 RTCCTC
R2C2= 77 RtCCTC
Repeat of

Above

Example RIC Values

(All Resistors and Capacitors are ±5%)
(CTC' = CTC + 20 pFI
RTC
10k

CTC'
120 pF

RS

R,

C,

R2

C2

362

20k

10k

470 pF

100 k

910 pF

181

10 k

240 pF

20 k

10 k

910 pF

100 k

1800 pF

88.7

10 k

490 pF

20 k

10 k

2000 pF

100 k

3900 pF

426

10 k

1020 pF

20 k

10k

3900 pF

100 k

7500 pF
0.015

215

10 k

2020 pF

20 k

10 k

8200 pF

100 k

853

10 k

5100 pF

20 k

10 k

200 k

o 02 ~F

171

50k

5100 pF

100 k

50k

o 02 ~F
o 02 ~F

200 k

0.1 ~F

•

~F

0..A.
~

en

RTC

8

fosc (kHz)

0
N

9

MC145026

4-Blt

~

I
16

1

Tnnary

Addresses

0..A.

VDD

16

5

3:

VDD

Repeat

of Above

-1-J

0
N
CD

~

3:
0

..A.

~

VT

en
0
N
CD

•

7-38

CMOS Smoke Detectors

8-1

•

CMOS SMOKE DETECTORS
Device
Number
MCI4466
MCI4487-1
MCI4466

Ful'lCtion
Ionization-Type Smoke
Detector

Ionization-Type Smoke
Detector with

Function
Low Cost Smake Detector
Low Cost S make Detector
Interconnectable Smoke Detector

On-Chip High
Input Impedance
FET Comparator

.,.

.,.
.,.

Low Battery
DetectOr

.,.
.,.
.,.

Interconnect

•
'

~

8·2

Piezoetectric
Hom Driver

.,.
.,.
.,.

Device
Number

Number
of Pins

MCl4466

16

MCl4467-1

16

MCl4468

16

®

MOTOROLA

MCl4466

LOW-COST SMOKE DETECTOR

CMOS MSI

The MCl4466, together with an IOnization chamber, will detect
smoke uSing a minimum of external cornponents. When smoke IS
sensed, an alarm IS sounded via an external piezoelectric transducer and
Internal drivers This CirCUit IS designed to comply with the UL217
specificatIOn.
•
•
•
•
•

IOnization Type with On-Chip FET Input Comparator
Piezoelectric Horn Driver
Guard Outputs on Both Sides of Detect Input
Low Battery Trip POint Internally Set Can Be Altered Via
External Resistor
Detect Threshold Internally Set Can Be Altered Via
External Resistor

•
•
•

Pulse Testing for Low Battery Uses LED for Battery Loading
Comparator Outputs for Detect and Low Battery
Internal Reverse Battery Protection

•

Chip Complexity: 239 FETs

(LOW-POWER COMPLEMENTARY MOS)

LOW-COST SMOKE DETECTOR

,~
"~

~

.Y

P SUFFIX

PLASTIC PACKAGE
CASE 6488*

"Pms 15 and 16 are connected via a metal
shorting bar. See package detad In Figure 1.

PIN ASSIGNMENT
VDD~)[~~~~--,
VDD
Detect

80 k

Comp Out
N.C
Low V Set
Low V
Comp Out
LED

1045 k

13

Detect Input ,,15"-_-41--1

8-3

Detect Input

Guard
SensitiVity Set

Ext Capacitor

VOD

Silver

Ext ReSistor

Brass

Feedback
1125 k

Guard

VSS

•

MC14466

MAXIMUM RATINGS IVoltages referenced to VSSI
Symbol

Value

Unk

VDD

-0.5to+15

V

DC Input Current. per Pm

Y,n
lin

-0.25 to VDD+0.25
10

V
mA

DC Output Current, per Pin

lout

30

mA

Operating Temperature Range

TA·

Rating
DC Supply Voltage
Input Voltage, All Inputs

o to

+50

ThiS device contains circuitry to protect
the mputs against damage due to high
static voltages or electric fields' however, It
IS adVIsed that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voltages to thiS high
Impedance ClrcUlt. For proper operation It IS
recommended that V ln and Vout be constramed to the range VSS:5IV,n or
VoutlsVDDI.

'C

Storage Temperature Range

Tstg

-55 to +125

'C

Reverse Battery Time

tRB

5.0

s

RECOMMENDED DC OPERATING CONDITIONS IVoltages referenced to VSSI

Parameter

Symbol

Value
9.0

V

Timing Capacitor

VDD
Cext

0.1

~F

Timing Resistor

Rext

8.2

M!l

-

10

mA

Supply Voltage

Battery Load (ReSistor or LEDl

Unit

ELECTRICAL CHARACTERISTICS IT A = 25'CI
Symbol

VPO
Vdc

Min

Typ

Max

Unit

Operating Voltage

VDD

-

6.0

-

10

V

Output Voltage
Plezoelectnc Horn Dnvers UOH = 16 mAl
Comparators IIOH = 30 ~AI
Piezoelectric Horn Dnvers (lOL = -16 rnA)
Comparators IIOl = - 30 ~AI
Output Current - LED Dnver
{Val =3.0 VI
Operating Current
IR ext =8.2 MOl

VOH
7.4
90
7.4
9.0

6.5
8.5

-

-

8.8

-

-

0.1

0.9
05

IOl

7.4

10

-

-

mA

IDD

9.0

5.0

9.0

~A

-

+ 1.0

pA
V
%VDD
mV

Characteristic

Input Current

Val

Detect 140% R.H.I

V

lin

9.0

-

Internal Set Voltage - low Battery
- Sensitivity

Vlow
Vset

9.0

-

7.2
47

50

78
53

HysteresIs

Vhys

9.0

75

100

150

Offset Voltage {measured at Y,n - VDD/21
Active Guard
Detect Comparator

Vas
9.0
9.0

-

-

±100
±50

•
8-4

mV

-

MC14466

TIMING PARAMETERS ICext = 0 1 ~F. Rext=8 2 MO. VOO=9 0 V. TA= 25'C)

Characteristics
No Smoke
Smoke

Oscillator Penod
Oscillator Rise Time (Pin 12)

Min

Typ

Max

Units

134
32

167
40

20

48

s
ms

8

10

12

ms

On Time
Ott Time

120
60

160
80

208
104

ms
ms

LED Output
lOUring No Smokel

Off Time Between Pulses
On Time

32
8

40
10

48

s
ms

Horn Output
(DUring Low Battery)

On Time
Off Time Between Pulses

8
32

10
40

12
48

Horn Output
(During Smoke)

12

ms
5

TIMING DIAGRAM

~

No Smoke
Smoke
No Low Battery~ No Low Battery

_I"

167s~~ ~40ms

Smoke
Low Battery

__ I"

No Smoke
Low Battery

~

10ms~~

Oscillator
IPIO 121

Detect
Camp IP,n 11
Low V
Camp IPIO 41

Horn
Modulation
LED
Pulse

High = Horn Enable
Low = Horn Disable

L------{'HL--

=~ru~------~u,~--------~j------.I
*------.I
24 Clock Cycles
40s

24 Clock Cycles
1s

NOTES: 1 Horn modulation IS self-completing. When gomg from smoke to no smoke, the alarm condition
2. Comparators are strobed on once per clock cycle 11 675 for no smoke, 40 rY 5 for smoke).
3. Low battery comparator mformatlon IS latched only dunng LED pulse.

FIGURE 1 -

PACKAGE DETAIL

* External lead connection (shorting bar} between Pins 15 and 1?

8·5

10 s

Will

terminate only when horn

IS

off

MC14466

DEVICE OPERATION
nected between VDD and VSS. These voltages can be
altered by external resistors connected from Pins 3 or 13 to
either VDD or VSS. There will be a slight interaction here
due to the common voltage diVider network.

TIMING
The Internal oscillator of the MCl4466 operates with a
period of 1.67 seconds during no-smoke conditions. Each
1.67 seconds, Internal power IS applied to the entire IC and a
check is made for smoke. Every 24 clock cycles a check is
made for low battery by comparing VDD to an Internal zener
voltage. Since very small currents are used In 'the oscillator,
the oscillator capacitor should be of a low leakage type.

TEST MODE
Since the Internal op amps and comparators are power
strobed, adjustments for sensitivity or low battery level could
be difficult and/or time-consuming. By forCing Pin 12 to
VSS, the power strobing IS bypassed and the outputs, PinS 1
and 4, constantly show smoke/no-smoke and good battery/low battery, respectively. Pin 1 = VDD for smoke and
Pin 4 = VDD for low battery. In thiS mode and during the
10ms power strobe, chip current rises to approximately
50!,A

DETECT CIRCUITRY
If smoke IS detected, the OSCillator period becomes 40 ms
and the piezoelectric horn OSCillator CIrCUit is enabled. The
horn output IS modulated 200 ms on, 40 ms off. During the
off time, smoke is again checked and Will inhibit further horn
output If no smoke IS sensed. DUring smoke conditions the
low battery detection IS inhibited, but the LED pulses at a
1.0 Hz rate.
An active guard IS proVided on both pins adjacent to the
detect input. The voltage at these pins will be Within 100 mV
of the Input signal. ThiS will keep surface leakage currents to
a minimum and provide a method of measuring the input
voltage without loading the IOnization chamber. The active
guard op amp IS not power strobed and thus gives constant
protection from surface leakage current. Pin 16 of the active
guard IS connected to Pin 15 (the detect Inputl dUring shipping to protect Pin 15 from static damage (see Figure 11.

LED PULSE
The 9-volt battery level IS checked every 40 seconds dUring
the LED pulse. The battery IS loaded via a 10 mA pulse for
10 ms. If the LED IS not used, it should be replaced With an
equivalent resistor such that the battery loading remains at
10 mAo
HYSTERESIS
When smoke is detected, the resistor / divider network that
sets sensitivity IS altered to Increase senSitivity. ThiS yields
approximately 100 mV of hysteresIs and avoids false triggerIng.

SENSITIVITY/LOW BATTERY THRESHOLDS
Both the sensitivity threshold and the low battery voltage
levels are set Internally by a common voltage diVider con-

FIGURE 2 - TYPICAL APPLICATION AS IONIZATION SMOKE DETECTOR

1M

16

•

MCl4466

15

1

14

~

4

12

330 [J
Rext

13

6

o.l~FlC

11

ext

10
82M
01

~FI

8

+

1

9V

9

-=

150 k[J

15 M[J

NOTE Component values may change depending on type of piezoelectric horn used

8-6

MC14466

FIGURE 3 - TYPICAL LED OUTPUT
I-V CHARACTERISTIC
1000

= 1=
;;:

~

VOO - 7.1 Vdc

•

~
z

.e

F

......::;

E

;:: 10.0

~

TA -15°C
VOO - 9.0 Vdc

1.0

0.1

o

10
VOS, ORAIN TO SOURCE VOLTAGE (Vdc)

FIGURE 4 - TYPICAL P HORN DRIVER OUTPUT
I-V CHARACTERISTIC
1000.0

1000.0

TA =25 0 C

1
j: 100.0

I---- -

~

i";:: 100.0

-

-

VOO

9.0 Vdc

TA -15°C

-

~
~

~

,

z

~

-

VOO - 9.0 Vdc

10.0

~

=>

z

~

.e

p. CH SOURCE CURRENT

1.0

0

u

VOO -7.1 Vdc

o

•

to.O

.e

=

N· CH SINK CURRENT

1.0

10

VOO - 7.1 Vdc

o

10

VOS, ORAIN TO SOURCE VOLTAGE (Vdc)

VOS, DRAIN TO SOURCE VOLTAGE (Vdc)

FIGURE 5 - TYPICAL COMPARATOR OUTPUT
I-V CHARACTERISTIC
10.0
TA-150C

;;:

.s

~

=>

u

z

~

".e

:::=:::::

VDO - 9.0 Vdc or 7.2 Vdc

1.0

./

0.1

.01

-

p. CH SOURCE
ANO
N·CHSINK
CURRENT

o

10
VOS, ORAIN TO SOURCE VOLTAGE IVdc)

8-7

=~

®

MC14467·1

MOTOROLA

Advance Information
CMOS MS.
(LOW-POWER COMPLEMENTARY MOS)

LOW-COST SMOKE DETECTOR
The MCl4467-1, when used with an ionization chamber and a small
number of external components, will detect smoke. When smoke is
sensed, an alarm is sounded via an external piezoelectric transducer and
internal drivers. This circuit is designed to comply with the UL217
specification.
• Ionization Type with On-Chip FET Input Comparator
• Piezoelectric Horn Driver
• Guard Outputs on Both Sides of Detect Input
• Input-Protection Diodes on the Detect Input
• Low-Battery Trip Point, Internally Set, Can Be Altered Via
External Resistor
• Detect Threshold, Internally Set, Can Be Altered Via External
Resistor
• Pulse Testing for Low Battery Uses LED for Battery Loading
• Comparator Outputs for Detect and Low Battery
• Internal Reverse Battery Protection
• Direct Replacement for the MCl4467, with Improved Alarm Stability

LOW-COST SMOKE DETECTOR

1

MCI4467Pl

PLASTIC PACKAGE
CASE 648

BLOCK DIAGRAM
PIN ASSIGNMENT
VDD
Detect Camp. Out

•

'i'i'-'16 ~ Guard Hi-Z

N/C

2

15 ~ Detect Input

LowV Set

3

14

Guard Lo-Z

Low V Camp. Out

4

13

Sensitivity Set

LED I 5

12

Ose Capacitor

6

11

Silver

VDD
Timing ReSistor
Feedback

ThIS document containS information on a new product Specifications and Information herein
are subject to change without notice.

8·8

8

10

Brass

9

VSS

MC14467·1
MAXIMUM RATINGS' (Voltages referenced to Vss)
Rating
DC Supply Voltage
Input Voltage, All Inputs Except Pin 8
DC Current Drain per Input Pin, Except Pin 15- 1 rnA

Symbol

Value

Unit

VDD

-0.5 to + 15

V

Vin
I

-0.25 toVDD +0.25

V

10

rnA

I

30

TA

-10to +60

rnA
DC

Storage Temperature Range

T stg

-55 to +125

DC

Reverse Battery Time

tRB

5.0

s

DC Current Drain per Output Pm

Operating Temperature Range

·Maxlmurn Ratings are those values beyond which damage to the device may occur.

RECOMMENDED DC OPERATING CONDITIONS (Voltages referenced to VSS)

Parameter
Supply Voltage
Timing Capacitor
Timing Resistor
Battery Load (Resistor or LED)

Symbol

Value

VDD

9.0

Unit
V

-

0.1

,.F

8.2

Mil

10

rnA

Un~

ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS, T A = 25'C)
Symbol

Voo
Vdc

Min

Typ

Max

Operating Voltage

VDD

-

6.0

-

12

Output Voltage
Piezoelectric Horn Drivers IIOH = -16 rnA)
Comparators (IOH = - 30 ,.A)
Piezoelectric Horn Drivers IIOL = + 16 rnA)
Comparators IIOL = + 30 ,.A)

VOH

Characteristic

Output Voltage -

LED Driver, IOL -10 rnA

Output Impedance, Active Guard

Operaling Current (Rblas - 8.2 Mill
Input Current -

VOL

Detect (40% R. H.)

Pin 14
Pin 16

VOL
Lo-Z
Hi-Z
100

V
V

7.2
9.0
7.2
9.0
7.2
9.0
9.0
9.0
12.0

6.3
8.5

-

-

8.8

-

V

0.1

0.9
0.5

-

3.0

V

10

-

kll

500

-

5.0

,.A

-

9.0
12.0
±1.0

pA

lin

9.0

Internal Set Voltage
Low Battery
Sensitivity

Vlow
Vset

9.0

7.2
47

-

7.8

V

-

50

53

%VDD

HysteresIs

Vhys

9.0

75

100

150

mV

Offset Voltage (measured at Yin - VDD/2)
Active Guard
Detect Comparator

VOS
9.0
9.0

-

±loo
±50

mV

Input Voltage Range, Pin 8

Yin

-

-10

-

VDD+l0

V

Input Capacitance

Cin

-

-

5.0

-

pF

Common Mode Voltage Range, Pin 15

Vern

-

0.6

-

VDD-2

V

-

This deVice contains CirCUItry to protect the inputs against damage due to high static voltages or electric fields; however, It is advised that normal
precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high Impedance circuit. For proper operation
It IS recommended that except for pin 8, Vin and Vout be constrained to the range VSS s (Vin or Vout) :s VDO. For Pin 8, refer to the Electncal
Characteristics.

8·9

•

MC14467·1
DEVICE OPERATION
TIMING
The internal oscillator of the MC14467-1 operates with a
period of 1.67 seconds during no-smoke conditions. Each
1.67 seconds, internal power is applied to the entire IC and a
check is made for smoke, except during LED pulse, Low Battery Alarm C~irp, or Horn Modulation (in smoke). Every 24
clock cycles a check is made for low battery by comparing
VDD to an internal zener voltage. Since very small currents
are used in the oscillator, the oscillator capacitor should be
of a low leakage type.

SENSITIVITY/LOW BATTERY THRESHOLDS
Both the sensitivity threshold and the low battery voltage
levels are set internally by a common voltage divider connected between VDD and VSS. These voltages can be
altered by external resistors connected from pins 3 or 13 to
either VDD or VSS. There will be a slight interaction here
due to the common voltage divider network.
TEST MODE
Since the internal op amps and comparators are power
strobed, adjustments for sensitivity or low battery level could
be difficult and/or time-consuming. By forcing Pin 12 to
VSS, the power strobing is bypassed and the outputs, Pins 1
and 4, constantly show smoke/no smoke and good battery/low battery, respectively. Pin 1 = VDD for smoke and
Pin 4= VDD for low battery. In this mode and during the 10
ms power strobe, chip current rises to approximately 50 /LA.

DETECT CIRCUITRY
If smoke is detected, the oscillator period becomes 40 ms
and the piezoelectric horn oscillator circuit is enabled. The
horn output is modulated 160 ms on, 80 ms off. During the
off time, smoke is again checked and will inhibit further horn
output if no smoke is sensed. During smoke conditions the
low battery alarm is inhibited, but the LED pulses at a
1.0 Hz rate.

LED PULSE
The 9-volt battery level is checked every 40 seconds during
the LED pulse. The battery is loaded via a 10 mA pulse for
10 ms. If the LED is not used, it should be replaced with an
equivalent resistor such that the battery loading remains at
10 mAo

An active guard is provided on both pins adjacent to the
detect input. The voltage at these pins will be within l00mV
of the input signal. This will keep surface leakage currents to
a minimum and provide a method of measuring the input
voltage without loading the ionization chamber. The active
guard op amp is not power strobed and thus gives constant
protection from surface leakage currents. Pin 15 !the Detect
input) has internal diode protection against static damage.

FIGURE 1 -

HYSTERESIS
When smoke is detected, the resistor/divider network that
sets sensitivity is altered to increase sensitivity. This yields
approximately 100 mV of hysteresis and reduces false triggering.

TYPICAL APPLICATION AS IONIZATION SMOKE DETECTOR

1M

•

16
2 MCl4467_115
14
3

/}If
3301l

rr
+

01~F

* NOTE:

4

13

5

12

6

11

f

10

8.2 Mil
8

9

-=.9V
'::'

220 kll*
1.5 MIl*

Component values may change depending on type of piezoelectriC horn used

8-10

MC14467·1
TIMING PARAMETERS IC~O.II'F, Rbias~8.2 MO, VDD~ 9.0 V, TA~25°C, See Figure 51

Characteristics
Oscillator Penod

Symbol

Min

Typ

Max

Units

ICI

1.34
32

1.67

2.0

40

48

s
ms

No Smoke
Smoke

Oscillator Rise Time

LED Output
Horn Output
I DUring Low Batteryl

8

10

12

ms

120
60

160

206

BO

104

ms
ms

ILED
PW on

32

40

48

8

10

12

ton
toff

8
32

10
40

48

On Time
OffTlme

Ir
PW on
PWoff

Between Pulses
On Time
On Time
Between Pulses

Horn Output
lOuring Smokel

FIGURE 2 - TYPICAL LED OUTPUT
I-V CHARACTERISTIC

12

ms
s

FIGURE 3 - TYPICAL COMPARATOR OUTPUT
I-V CHARACTERISTIC

100 a

10.0

r== f=
1
;:: 10.0

Voo "9.0 Vdc

TA"250C

F==

TA" 25°C

.s<

~

f-

I

--

•

z

Voo '" 9.0 Vdc or 1.2 Vdc

.",

z

~

~ 10 I.

p·CHSOURCE
AND
N·CHSINK
CURRENT

1/

0.1

E

E

.Ot

a

=

1.0

I

VoO '" 7.2 Vdc

0.1

s
ms

/0

a

10

VOS, DRAIN TO SOURCE VOLTAGE IVdcl

VOS, DRAIN TO SOURCE VOLTAGE IVdcl

FIGURE 4 - TYPICAL P HORN DRIVER OUTPUT
I-V CHARACTERISTIC
1000. 0

1000. 0
TA" 25 0 C t - -

~

i3

VOO" 7 2 Vdc

JL

z

a v

~
p. CH SOURCE CURRENT

1.0

!==

10.0

VOO" 7.2 Vdc

N· CH SINK CURRENT

10

to

o

=!==
10

VOS, DRAIN TO SOURCE VOLTAGE IVael

8-11

r-----

~

E

Vas, DRAIN TO SOURCE VOLTAGE (Vdc)

TA"25OC

L1

;= 100.0

0

~

r--- t- VOO - 9.0 Vdc



Unit
V

Unk
V

"F
Mil
rnA

ELECTRICAL CHARACTERISTICS IT A = 25°C)
Symbol

Characteristic
Operating Voltage

VDD

Output Voltage
Piezoelectric Horn Dnvers IIOH = -16 rnA)
Comparators iJOH = - 30 "A)
Piezoelectric Horn Dnvers IIOL = + 16 mAl
Comparators IIOL = + 30 "A)

VOH

LED Dnver, 10L = 10 rnA

Output Voltage -

Output Impedance, Active Guard

Pin 14
Pin 16

VOL
Lo-Z
H,-Z

Min

V

9.0
9.0

-

500
5.0

110

9.0

110
I,n

90

-

-

-

VloW
Vset

9.0

-

7.2
47

Hysteresis

Vhys

9.0

Offset Voltage Imeasured at Vrn - VDD/2)
Active Guard

VOS

Operating Current IAblas=8.2 Mill
Input Current -

Detect 140% A.H.I

Input Current. Pm 8
Input Current @ 50°C, Pin 15

Internal Set Voltage
Low Battery

•

VOL

Vaa
Vdc
-

Sensitivity

100

Detect Comparator

Input Voltage Aange, Prn 8
Input Capacitance

Common Mode Voltage Range, Prn 15

1/0 Current, Prn 2
Input, VOL = VDD- 2
Output, VOH=VDD-2

Vrn
C,n
Vcm
10L
10H

9.0
12.0

V

-

78

53

75

50
100

150

90
9.0

-

-

±loo
±50

-

-10

-

VDD+ 10

V

-

-

5.0

-

pF

0.6

-

VDD-2

V
%VDD
mV
mV

-

25
-4.0

-

V
"A

100
-16

ThiS deVice containS circUItry to protect the mputs against damage due to high static voltages or electnc fields, however, It IS adVised that normal
precautions be taken to avoid application of any voltage higher than maximum rated voltages to thiS high Impedance Circuit For proper operation
It IS recommended that Vm and V out be constramed to the range VSS :s (V m or Vout) .:s VDO

8-14

MC14468
TIMING PARAMETERS IC=O.1 ~F, RBlas=8 2 MO, VDO=9.0 V, TA=25'C, See Figure 5}
Characteristics

Symbol

Min

Typ

Max

Units

tCI

1.34
32

2.0

s
ms

120
60

1.67
40
10
160
60

No Smoke
Smoke

OscIllator Penod
Oscillator Rise TIme

Off Time
Between Pulses
On T,me

tLED
PWon

32

40

8

10

ton
toff

8
32

10
40

On Time

LED Output

On T,me

Horn Output
lOUTing Low Battery}

Between Pulses

FIGURE 1 - TYPICAL LED OUTPUT
I-V CHARACTERISTIC
100.0

~ 1= voo "9.0 Vde

«
.5

~

«

13
z

~

0

1/

0.1

9

9

o

s
ms
ms
s

.01

10

t==

VOO = 9.0 Vdc or 7.2 Vdc

10

~

--

I-

1.0

0.1

48
12
12
48

TA" 25°C

.5
....

•

ms
ms

100

==

VOO "7.2 Vde

z

ms

FIGURE 2 - TYPICAL COMPARATOR OUTPUT
I-V CHARACTERISTIC

......:

100

13

~

TA" 25°C

8

tr
PW on
PWoff

Horn Output
lOUTing Smoke}

48
12
208
104

-

p. CH SOURCE
AND
N· CH SINK
CURRENT

o

10

VOS, DRAIN TO SOURCE VOLTAGE IVdc}

VOS, DRAIN TO SOURCE VOLTAGE IV de}

FIGURE 3 - TYPICAL P HORN DRIVER OUTPUT
I-V CHARACTERISTIC
1000 0

10000

TA"25OC

«
~

I---- I--

~

r--- r-

«
~

1000

TA

25°C

VOO " 9.0 Vde

t--

100.0

~
~

13

~

z

~

t--

VOO -90 Vdc

13

Vao '" 7.2 Vdc

~

/I

100

9

p. CH SOURCE CURRENT

10

D

2

10.0

9

1=

VOO" 7.2 Vde

•
N . CH SINK CURRENT _

0

o
VOS. DRAIN TO SOURCE VOLTAGE IVdc}

10
VOS. DRAIN TO SOURCE VOLTAGE IVde}

8·15

t--

MC14468
DEVICE OPERATION
voltage. The I/O IS disabled for three oscillator cycles after
power up, to eliminate false alarming of remote units when
the battery is changed.

TIMING

The internal oscillator of the MCl4468 operates with a
period of 1.67 seconds dUring no-smoke conditions. Each
1.67 seconds, internal power IS applied to the entire IC .and a
check is made for smoke, except during LED pulse, Low Battery Alarm Chirp, or Horn Modulation lin smoke). Every 24
clock cycles a check IS made for low battery by comparing
VDD to an Internal zener voltage. Since very small currents
are used In the oscillator, the oscillator capacitor should be
of a low leakage type.

SENSITIVITY/LOW BATIERY THRESHOLDS
Both the sensitivity threshold and the low battery voltage
levels are set Internally by a common voltage divider connected between VDD and VSS. These voltages can be
altered by external resistors connected from pinS 3 or 13 to
either VDD or VSS. There Will be a slight Interaction here
due to the common voltage divider network.

DETECT CIRCUITRY

If smoke is detected, the oscillator period becomes 40 ms
and the piezoelectric horn oscillator circuit is enabled. The
horn output is modulated 160 ms on, 80 ms off. DUring the
off time, smoke IS again checked and will inhibit further horn
output if no smoke is sensed. DUring local smoke conditions
the low battery alarm is Inhibited, but the LED pulses at a
1.0 Hz rate. In remote smoke, the LED is ,nhib,ted as well.
An active guard is provided on both pins adjacent to the
detect input. The voltage at these PinS will be within 100 mV
of the Input signal. This will keep surface leakage currents to
a minimum and provide a method of measuring the Input
voltage without loading the Ionization chamber. The active
guard op amp IS not power strobed and thus gives constant
protection from surface leakage currents. Pin 15 Ithe Detect
Input) has internal diode protection against static damage.

TEST MODE

Since the Internal op amps and comparators are power
strobed, adjustments for sensitivity or low battery level could
be difficult and/or time-consuming. By forCing Pin 12 to
VSS, the power strobing IS bypassed and the output, Pin 1,
constantly shows smoke/no smoke. Pin 1 = VDD for smoke.
In thiS mode and dUring the 10 ms power strobe, chip current
rises to approximately 50 p.A.
LED PULSE

The 9-volt battery level IS checked every 40 seconds dUring
the LED pulse. The battery IS loaded via a 10 mA pulse for
10 ms. If the LED IS not used, It should be replaced With an
eqUivalent resistor such that the battery loading remains at
10 mA

INTERCONNECT

The I/O IPin 2), In combination With VSS, IS used to Interconnect up to 40 remote units for common signaling. A
Local Smoke condilion activates a current limited output
driver, thereby signaling Remote Smoke to interconnected
units. A small current sink improves noise immunity dUring
non-smoke conditions. Remote Units at lower voltages do
not draw excessive current from a sending unit at a higher

HYSTERESIS

When smoke IS detected. the resistor/divider network that
sets sensitivity IS altered to Increase sensitivity ThiS Yields
approximately 100 mV of hysteresIs and reduces false triggering.

FIGURE 4 - TYPICAL APPLICATION AS IONIZATION SMOKE DETECTOR

1M

•

16
To

2 MCl4468 15
14
3

Olher
Units

~

~
330 Il

rI

* NOTE

13
12

6

01

11
10

82 Mil

+

01~F

4

8

..=...9V

-=

220 kO "

15 MO"

Component values may change depending on type of piezoelectric horn used

8-16

~Fr

f

3:
(')

......

~

~
CJ)

co

FIGURE 5 -

Standby
No Smokel
No Low Battery
I""
.1""

TIMING DIAGRAM
Smoke/Low Battery

SmokelNo Low Battery

No Smoke! Low Battery

~Io(

Oscillator
{Pin 121

+-I

I

I

HystereSIS (lnternall
.
IPIn 131 INote 41 ~l----'

.

L---l'!-I--------------

n

Sample (Internal)
Smoke

.....

- - - - .•
- ·1

~~
1rlnrlrlnrtnrU

Detect out
{Pin 11

cp

1.-1 67 s

n n n n n

n

t-J L....--...J L..........J L......J L.......J L.....J L----.......J I

Horn
(Pins 10 & 111

INotel1

L

1

I
I

-....I

--------------~--~=~------~!~,U(Note3)

LED
IPln 51

1--",.-011"""'"
IP,n 141
Output ILoca))

.

1

~I!_---------------

----II----'

------------------------=:1.
~l Note.

liD IPln 21
••
Input (Remote) ~~
LED
NOTES

4

I

6 Clock Cycles Ito 0 sl ~

1rlnrlrlnrtnrU

Strobe Out
liD IPln 21

::

~1J

ISuppressed LED for Remote Onlyl

Horn Modulatlon Not Self-Completmg

II-----u

r ------------

Horn modulation IS self-completing When gOing from smoke to no smoke, the alarm condition will terminate only when horn
Comparators are strobed on once per clock cycle (l 67 s for no smoke, 40 ms for smoke)
Low battery comparator Information IS latched only dunng LED pulse
- lOC mV p.p sWing

•

IS

off

•
8-18

Miscellaneous Functions

9-1

MISCELLANEOUS FUNCTIONS
Device
'Number

Function

MCl4460 Automotive Speed Control Processor
MCl4490 Hex Contact Bounce Eliminator
MCl4500B Industrial Control Unit

•
9·2

®

MC14460

MOTOROLA

CMOS LSI
AUTOMOTIVE SPEED CONTROL PROCESSOR

(LOW·POWER COMPLEMENTARY MOS)

The MC14460 device is designed to measure vehicle speed and
provide pulse-width modulated outputs to trim a throttle positioning servo to maintain an internally stored reference speed_
The stored reference speed can be altered by the DECEL and
ACCEL driver commands_ The DECEL command trims down the
speed, while ACCEL trims up the speed_
A BRAKE input Is provided to turn off the outputs with a
RESUME driver command to return the vehicle to the last stored
speed.

AUTOMOTIVE SPEED
CONTROL PROCESSOR

• On-Chip Master Oscillator for System Time Reference
• Separate On·Chip Pulse Oscillator for Output Pulse Width
Adjustment (Analogous to System Gain)
•

Diode Protection on All Inputs

•

Internal Redundant Brake and Minimum Speed Checks

•

Acceleration Rates Controlled During ACCEL and
Modes of Operation

•

Low Frequency Speed Sensors Used

•

No Throttle Position Feedback

• Power.On Reset

fIIIIIt

....
\.,

RESU~
,

r

fA

V

r

Low Power

~V

compat~iscrete Transistor
d.U .....

16
15

DiS"~""

BLOCK DIAGRAM

o~

PIN ASSIGNMENT

Req~rt"_ ' \

' . Buffered Outputs
Driver Interface
•

....

3

14

4

13

5

12

6

11

7

10

8

9

'" 0'"

0

:;; :;; :;;

This device contains circuitry to protect

the inputs against damage due to high static
voltages or electric fields; hO\NBver. it is
advised that normal precautions be taken
to avoid application of any voltage higher

than maximum rated voltages to this high
impedance circuit. For proper operation it
is recommended that Vin and V out be
constrained to the range VSS " (Vin or

Vou,)'; VDO'
Unused inputs must always be tied to an

9

PORo---.....J

appropriate logic voltage level (e.g., either
VSS or VOOI.

9-3

•

MC14460
MAXIMUM RATINGS IV olteg., referenced to V~S I
Symbol

lIating
OC Supply Volt...
Input Volt.... All Input'
DC Input Current, per Pin
Operating Temperature Range -

Value
-0.6 to +6.0

Vin

lin
TA
T stg

Storage Temperature Range

Unit

-0.5 to VOO + 0.5
±10
-40 to +85

Vde
Vde
mAde
°c

-65 to +150

°c

VOO

ELECTRICAL CHARACTERISTICS ITA = -40°C to +850 CI
Characuristi.
Supply Vol lege
Pin 16
Output Voltage
Pin, 1. 2. 5.6.14.15

Symbol

Voo
Yd.

VOO

-

VOL
VOH
VIL
VIH

5.0
5.0

Input Voltage
Pin. 3. 7. 9.10.11.12.13
Pin 4

Input Hysteresis
Pin4
(VIH -VILI

-

Min
4.0

Typ

Max
6.0

Unit

5.0

-

-

0.5

4.5
-

-

0.3 VOO

-

Vde
Vde
Vde
Vde

-

-

Vde

0.7 VOO

Vde

-

VIL

-

VOO -1.5
2

VIH

-

-

-

VOO +15
2
.

Vde

HYS

-

0.4

-

-

Vde

10H
10L

5.0
5.0

-0.29

-

-

mAde

+0.36

IOH

5.0

-2.0

-

-

mAde

IlL
iiH

6.0
6.0

-

-

-1.0
+1.0

"Ade
"Ade

IlL
IIH
100

6.0
6.0
6.0

15
-

-

"Ade

-

1.0

200
+1.0
10

Output Drive Current

Pin, 1. 2. 5. 6
VOH= 4.6 Vde
VOL = 0.4 Vde
Pin, 14. 15
VOH = 2.5 Vde

mAde

Input Current

Pins 3.4. 7.10.11.12.13
VIL = 0.0 Vde
VOH = 6.0 Vde
Pin 9
VIL = 0.0 Vde
VIH = 6.0 Vde
Supply Current
Pin 16
(Both O,cillators Active. VAC and
VENT OUlPuts Highl
FIGURE 1 - SYSTEM TIMING

•

Intarnol

",1:--,---tsmPI teye

Speed
Sam pia

I

Gate

-

J,lAdc

mAde

··FIGURE 2 - OSCILLATORS

=;:1
I

~

-

To Internal Clock

r-

Frequency of

I

Oscillation as

. .

Measured at
Pin 1 (6) Is:

VAC

1= _ _
'_

2.43RC
R Inkfi
R

!---PWI----.I

C in ",F

Asynchronous to
Speed Sample

RS

1'11$

2R

f= kHz

9-4

MC14460

SWITCHING CHARACTERISTICS (TA = 260 C VOO = 4-6 Vdcl
Characteristics

ACCEL Input Hold Time
OECEL Input Hold Time
RESUME Input Hold Time
BRAKE Input Hold Time
Master Oscillator Frequency··
T A = -40o C to +B50C. RS = 100 kG
R = 43 kG, C = 5600 pF
Uselul Range
Pulse Oscillator Frequency*·
T A = -40°C to +85 0 C, RS = 100 kG
R = 43 kG, C = 5600 pF

Unit
m.
ms

-

Max
-

1596
1344

1680
1680

1764
2016

Hz
Hz

Ip

1596
400

1680
1600

IS
tsmpl

-

1764
3200
300

-

Hz
Hz
Hz
ms
ms
ms
ms

760'
80'

ms
ms

Symbol

Min

tACC
tOEC
tRES
tBRK

lS/IM
16/IM
1
1

1M

Useful Range
Speed Input Frequency

Speed Sample Time (1008/IMI
Speed Processing Time (16/IMI
System Cycle Time (1024/IMI
Output Delay Time (9/IMI
Output Pulse Width
Initializations (",l/lpl
Trim Outputs (",l/lpl
'IM = 1680 Hz, Ip = 1600 Hz, IS

tproc

SYSTEM PERFORMANCE (TA

-

tout

-

PWI
PWT

280'
10'

-

600'
8.9'
608.9'
6.4'

-

t cve

= 2.222

Typ
9.62'
9.52'

-

-

lIS

IJS

Hz/MPH

= 25°C

VOO

= 5 Vdc

1M = 1680 Hz IS

= 2.222 Hz/MPH I

A

Typical
0.375
24
90
1.85

Unit
MPH
MPH
MPH
MPH/s

SRB

-12

MPH

Symbol

Characteristic

Speed Resolution (IM/2016 151
Minimum Operating Speed (IM/31.6 151
Maximum Stored Speed (IM/8.4 151

SRES
Smin
Smax

Controlled Acceleration Rate

(ACCEL or RESUME Modesl
(IMI2/IS (6.B81I (105 1
Redundant Brake Speed Drop Below Stored Reference Speed

(-IM/63 151
Speed Deviation

Assumes Suitable Mechanical Hookup and Pulse
Oscillator Frequency Adjusted to Suit Throttle

Servo Requirements

Level Road (no wind,' 1% gradesl

..'-

.....- - - - - - - - - - ; BRAKE
GNO

Lights

Speed
Sensor

SP~

SENSOR

Electromagnetic Type

9-7

Poles:
Output Freq:

2.222 Hz/MPH

Output Voltage:
Maximum Freq:
DC Resistance:

(SOOO pulaesJmile)
> 3.0 Vp-p @ 24 MPH
360 Hz (162 MPH)
< 400

B/revolutlon

MC14460
DEVICE OPERATION continued

mand is received. The flow diagram in Figure 3 gives the
detailed constraints/operation of this input.

RESUME (RES, Pin 12)

VENT (Pin 14)

This is the RESUME command input. When taken
HIGH the system will lock into a mode where the VAC
and VENT outputs are modulated to maintain a fixed rate
acceleration. This acceleration ends when the SPO input
sample matches the stored reference speed. The flow dia·
gram in Figure 3 gives the detailed constraints/operation
of this input.

This is the VENT output.
operation.

See Truth Table for

VAC (Pin 15)
This is the V AC output. See Truth Table for operation.
GROUND (VSS, Pin 8)

BRAKE (BRK, Pin 13)

Pin B is the ground connection for the package.

This is the BRAKE command input. When this input is
taken HIGH the system is disabled (both VAC and VENT
outputs LOW) until a DECEL, ACCEL, or RESUME com·

POSITIVE POWER SUPPLY (VDD, Pin 16)
Pin 16 is the power supply connection for the package.

FIGURE 5 - PC BOARD MODULE FOR CRUISE CONTROL
VENT Coli
<100mA~

VAC Coil

Coli COM

< 100 mA----"

130
2W

o

~N

Vooc=::J.
1 k

1W

t--

4.7 V
1M4.7Z10 41l

-Sensor

MPSA~

+ 50

~

N

~

~t' 27

~

111 wi'"

25 V

;!

V ....J-;;;PSA13

27 V

r,~

1w'll

1 k

1k

16

15

13

511~O, 5%
6
M02r-o---~.t-,---1

10

MC14460

5

M01~~~--~~--~

11
~--~---1~------~~----,----------+---C~ACC

P03r-o---~~---.

3

I

43 k, 1 %

~--~------------~VV--~~---------r---o-1DEC

12
~---r---+--~~--~~--~---------t---C~RES
Gnd

B(

100 k

5j~O,5%
2
P02 1-<~---1"t-----.

43 k,1%
P01r-o----V~--~

jiQ'j:f

9'
" 0.1

All Resistor.
'10%,1/4 W, U,O.S.

Environment
Ambient Temperature (T A)' . . . . -40°C to 85°C
Vee Operating Range . . • . . . . . 11-15 Vdc
Vee Transients . . . . . . . . . • . • 9-16 Vdc
Load Dump • • • • • • • • • • SO V Peak decaying to
Inductive

•••••••••••

12 V in < 200 ms
±30a V Peak decaying
in
ms

<,

Jump Start

. . . . . . . • . . +24 Vdc for 5 min.

Aeverse Battery. . • . • . .. -12 Vdc continuous

9·8

®

MCl4490

MOTOROLA

HEX CONTACT BOUNCE ELIMINATOR

CMOS LSI

The MCl4490 is constructed with complementary MOS enhancement mode devices, and IS used for the elimination of extraneous level
changes that result when Interfacing with mechanical contacts. The
digital contact bounce eliminator circUit takes an input signal from a
bouncing contact and generates a clean digital signal four clock periods
after the input has stabilized. The bounce eliminator circuit will remove
bounce on both the "make" and the "break" of a contact closure. The
clock for operation of the MCl4490 is derived from an internal R-C
oscillator which requires only an external capacitor to adjust for the
desired operating frequency (bounce delay). The clock may also be
driven from an external clock source or the oscillator of another
MCl4490 (see Figure 5),
•
•
•
•
•
•
•
•
•
•
•
•
•

ILOW-POWER COMPLEMENTARY MOS)

HEX CONTACT
BOUNCE ELIMINATOR

L SUFFIX
CERAMIC PACKAGE
CASE 620

Diode Protection on All Inputs
Noise Immunlty=45% of VDD TYPical
Six Debouncers Per Package
Internal Pull ups on All Data Inputs
Can Be Used as a Digital Integrator, System Synchronizer, or Delay
Line
Internal Oscillator I R-C), or External Clock Source
TTL Compatible Data Inputs/Outputs
Single Line Input, Debounces Both "Make" and "Break" Contacts
Does Not Require "Form C" (Single Pole Double Throw) Input
Signal

P SUFFIX
PLASTIC PACKAGE
CASE 648

ORDERING INFORMATION

Cascadable for Longer Time Delays
Schmitt Trigger on Clock Input (Pin 7)
Supply Voltage Range= 3.0 V to 18 V
Chip Complexity: 546 FETs or 136.5 Equivalent Gates

MC14XXXlsuL'pfIX

Denotes
'Ceramic Package
Plastic Package

BLOCK DIAGRAM
+VOD
Data
4-Bit Static Shift Register

Ain 1

4>1 4>2

Voo = Pin 16
Vss = Pin 8

OSCout

4>1+ 4>2
4>1
Cln

+

~

Identical to Above Stage

Bin

3---1

+ 4>2*

2

~13Cout

Identical to Above Stage

~--------------------------~~--~

4>1
Din 12 - - - 1

Identical to Above Stage

* 4>2+

~4

~--------------------------~~--~

E 5-1
1n

<1>1

+ 4>2+

~

Identical to Above Stage

~------------------------------------~--~

4>1

F rn

Bout

10

-----1~

t

9·9

E out

4>2+

____________________________________________________ rIdentical to Above Stage

11

°out

J

6 F out

MC14490

MAXIMUM RATINGS' (Voltages referenced to VSS. Pin 8,)

,

Rating

PIN ASSIGNMENT

Symbol

Value

Unit

OC Supply Voltage

11.00

-0,5 to + 18

V

A ln

16

11.00

Input Voltage. All Inputs

V in

-0,5 to
VOO±O,5

V

Bout

15

Aout

CIn

14

Bin

4

13

Cout
Din

OC Input Current. per Pin
MCl4490L
MCl4490P

mA,

±1O

lin

Operating Temperature Range

°out

TA

-55 to +125
-50 to +85

Storage Temperature Range

Tstg

-65 to + 150

°C

Power Olssipation. per Packaget

Po

500

mW

°C

tPower

DISSipation Temperature Derating
Plastic "P" Package -12 mW/oC from 65 to 85°C
Ceramic "L" Package - 12 mW/oC from 100 to 125°C

1.

Eln

5

12

Fout

6

11

Eout

OscJn

7

10

Fin

VSS

8

9

OSCout

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Symbol

11.00
Vdc

Output Voltage
Vln=VDD orO

VOL

"0" Level

"1" Le,,'el

VOH

VIn=OorVDD
Input Voltage #
(VO= 4,5 or 0,5 VI
IVO,=9 0 or 1 0 VI
IVO= 13,5 or 1,5 VI

"0" Level

Tlow"
Min Max

50
10
15

-

50
10
15

Min

Thigh"

'25°C
Typ

Max

Min

Max

005
005
005

-

005
005
005

V

-

V

-

-

005
005
005

-

0
0
0

4,95
995
1495

-

495
995
1495

50
10
15

-

495
995
1495

.-

50
10
15

-

15
30
40

-

-

225
450
675

15
30
40

-

15
3,0
40

50
10
15

35
70
110

-

35
70
110

275
5 sa
825

-

35
70
110

-

-

-

-

V

VIL

"I" Level

V

VIH

IVo=050r45VI
(VO= 10 or 9,0 V)
IVO= 15 or 135 VI
Output Dnve Current

Unit

-

-

-

rnA

10H

Source
Oscillator Output
IVOH=2,5 VI
(VOH=4 6 VI
(VOH=9,5 V)
(VOH = 13,5 VI
Debounce Outputs
(VOH=2,5 VI
(VOH=4,6 V)
(VOH=9,5 VI
(VOH = 13,5 VI

•

50 -06
50 -012
10 -02
15, -14

-

-05
-01
-020
-12

-15
-03
-08
-30

-

-04
-OOB
-016
-10

-

-0,9
-019
-060
-18

-

-075
-016
-050
-15

-22
-04t
-12
-45

-

-06
-012
-04
-12

-

50
5,0
10
15

Smk
Oscillator Output
(VOL=OA VI
(VOL =0,5 V)
(VOL = 1,5 \I.)
Debounce Outputs
(VOL=OA V)
(VOL=0,5 V)
(VOL = 1,5 V)

-

rnA

10L
5,0
10
15

036
09
42

-

030
075
35

09
23
10

-

024
06
28

-

50
, 10

-

22
33
10

40
9

-

-

35

-

18
27
81

-

0,2

2

-

11

~A

-

±25O

pA

70
145
215

130
265

~A

15

2,6
40
12

Input Current
Oebaunce (nputs (V In = VDDI

IIH

15

-

2

-

Input Current Oscillator -

1m

15

-

±620

-

Pullup Resistor Source Current
Debounce Inputs
(Vln=VSSI

IlL

5,0
10
15

210
415
610

375
740
1100

140
280
415

Input Capacitance

C,n

QUiescent Current

ISS

Pin 7 {V ln - VSS or VDDI

(Vln = VSS or VDD. 10ut=0 ~AI

5,0

10
15

INolse Immunity speCified for worst case combination.
Noise margm for both "1" and "0" level = 1,0 V min @ VOD=5,0 V
2,0 V mm @ VOD= 10 V
2,5 V min @ VDO= 15 V

9·10

-

150
280
840

-

-

±255 ±4oo
190
570

255
500
750

50

75

40
90
225

100
225
650

380

-

-

400

-

pF

90
180
550

~A

-Tlow == -55°C for L DeVice, _40° C for P DeVice
Thlgh= + 125°C for L DeVice. +85°C for P DeVice

MC14490
THEORY OF OPERATION
After some time period of N clock periods, the contact is
opened and at N + 1 a low IS loaded into the first bit. Just
after N + 1, when the input bounces low, all bits are set to a
high. At N + 2 nothing happens because the input and output are low and all bits of the shift register are high. At time
N + 3 and thereafter the input Signal is a high, clean signal.
At the positive edge of N + 6 the output goes high as a result
of four lows being shifted Into the shift register.
Assuming the input Signal IS long enough to be clocked
through the Bounce Eliminator, the output Signal Will be no
longer or shorter than the clean input Signal plus or minus
one clock period.
The amount of time distortion between the Input and
output signals is a function of the difference in bounce
characteristics on the edges of the Input Signal and the clock
frequency. Since most relay contacts have more bounce
when making as compared to breaking, the overall delay,
counting bounce period, Will be greater on the leading edge
of the input signal than on the trailing edge. Thus, the output
signal will be shorter than the Input signal - if the leading
edge bounce is included in the overall timing calculation.
The only requirement on the clock frequency in order to
obtain a bounce free output signal IS that four clock periods
do not occur while the Input Signal IS in a false state. Referring to Figure 3, a false state is seen to occur three times at
the beginning of the input signal. The input Signal goes low
three times before it finally settles down to a valid low state.
The first three low pulses are referred to as false states.
If the user has an available clock Signal of the proper frequency, it may be used by connecting it to the oscillator input (pin 7). However, if an external clock IS not available the
user can place a small capacitor across the oscillator Input
and output pins In order to start up an Internal clock source
(as shown in Figure 4). The clock signal at the oscillator output Pin may then be used to clock other MCl4490 Bounce
. Eliminator packages. With the use of the MCl4490, a large
number of signals can be cleaned up, with the reqUirement
of only one small capacitor external to the Hex Bounce
Eliminator packages.

The MCl4490 Hex Contact Bounce Eliminator is basically
digital integrator. The circuit can Integrate both up and
down. This enables the circuit to eliminate bounce on both
the leading and trailing edges of the signal. shown In the timing diagram of Figure 3.
Each of the six Bounce Eliminators is composed of a
4 v., -bit register (the integrator) and logic to compare the
input with the contents of the shift register, as shown in
Figure 4. The shift register requires a series of timing pulses
in order to shift the input signal Into each shift register
location. These timing pulses (the clock signali are
represented in the upper waveform of Figure 3. Each of the
SIX Bounce Eliminator circuits has an Internal resistor as
shown in Figure 4. A pullup resistor was Incorporated rather
than a pulldown resistor in order to Implement switched
ground input signals, such as those coming from relay contacts and push buttons. By switching ground, rather than a
power supply lead, system faults (such as shorts to ground
on the signal input leads) will not cause excessive currents In
the wiring and contacts. Signal lead shorts to ground are
much more probable than shorts to a power supply lead.
When the relay contact is open, (see Figure 4) the high
level is inverted, and the shift register IS loaded with a Iowan
each negative edge of the clock signal. To understand the
operation, we assume all bits of the shift register are loaded
with lows and the output is at a high level.
At clock edge 1 (Figure 3) the input has gone low and a
high has been loaded into the first bit or storage location of
the shift register. Just after the negative edge of clock 1, the
input signal has bounced back to a high. ThiS causes the
shift register to be reset to lows in all four bits - thus starting the timing sequence over again
DUring clock edges 3 to 6 the input Signal has stayed low.
Thus, a high has been shifted into all four shift register bits
and, as shown, the output goes low during the positive edge
of clock pulse 6.
It should be noted that there is a 3Y, to 4 v., clock period
delay between the clean input signal and output signal. In
this example there is a delay of 3.8 clock periods from the
beginning of the clean input Signal.

FIGURE 3 - TIMING DIAGRAM

4

•

6

N+l

N+3

N+5

OSCin or OSCout

Input

nIlJUl

If

ruuuu

.I

Outpu t

'c

Contact Closed
Contact
Open

Contact

Contact Open

IValid True Signall

Contact
BounCing

Bouncing

9·12

N+7

MC14490
FIGURE 4 - TYPICAL "FORM A" CONTACT DEBOUNCE CIRCUIT

(Onlv One Debounce, Shownl

+VOD
PuJlup Resistor
( Internal)

Data

~O-A-.~~'~n-----e~--q
-=-

4-Bit StatIc Shift Register

Contact

-- Aout
Ain

~

b--<>--

Bout

b--<>--

C out

LATCHED OUTPUT
The contents of the Bounce Eliminator can be latched
by using several extra gates as shown in Figure 7. If the
latch lead is high the clock will be stopped when the
output goes low. This will hold the output low even
though the input has returned to the high state. Any time
the clock is stopped the outputs will be representative of
the input signal four clock periods earlier.

b--O--- D out

FIGURE 7 - LATCHEO OUTPUT CIRCUIT

b--<:>-- Eout

Out

•

b--<>--

F out

1---+- OSCout

DSCin
1.0"'" = 1
Un,latch = 0,

9·14

1

~Oscout

7

Clock

9

MC14490
FIGURE 9 - SINGLE PULSE OUTPUT CIRCUIT

A
B

==

Active Low
Active Low

=

FIGURE 10 - MULTIPLE OUTPUT SIGNAL TIMING DIAGRAM

OSCout

Input

d'
lJlfl.. . ------------~----------------_?P_-

A

S

t'~L.__ _ _ _ _ _~1

c

D

--------------------------------------r(,~)----------------------__,

AS __________________...1

L -_ _~((~----------------------------

AB-------------------------------((~t~----------~

ThiS device contains circuitry to protect the Inputs against damage due to high statiC voltages or electriC fields, however, It IS adVised that normal precautIons be taken to aVOId application of any voltage higher than maximum rated voltages to thiS high Impedance CirCUit For proper
operation It IS recommended that Vin and Vout be constrained to the range VSSs(V,n or Vout)sVOD.

9-15

•

®

MC14500B

MOTOROLA
INDUSTRIAL CONTROL UNIT

CMOS LSI

The MC14500B Industrial Control Unit (lCU) is a single-bit
CMOS processor. The ICU is designed for use' in systems requiring
decisions based on successive single-bit information. An external
ROM stores the control program. With a program counter (and
output latches and input multiplexers, if required) the ICU in a
system forms a stored· program controller that replaces combinatorial
logic. Applications include relay logic processing, serial data manipulation and control. The ICU also may control an MPU or be
controlled by an MPU.
•

16 Instructions

•

DC to 1.0 MHz Operation at VDD = 5 V

•

On·Chip Clock (Oscillator)

•

Executes One I nstruction per Clock Cycle

•

3 to 18 V Operation

•

Noise Immunity Typically 45% of VDD

•

Low Quiescent Current Characteristic of CMOS Devices

•

Capable of Driving One Low·Power Schottky Load or Two
Low·Power TTL Loads over Full Temperature Range

•

Detailed Operation and Applications Given in Handbook
HB-209

•

Development System Described in Application Note AN-889

(LOW.pOWER COMPLEMENTARY MOSI

INDUSTRIAL CONTROL UNIT

L SUFFIX

P SUFFIX

CERAMIC PACKAGE

PLASTIC PACKAGE
CASE 648

CASE 620

ORDERING INFOIlMATION

."""'11:;SUffIX
L
P
A
C

Denotes

Ceramic Package
PlastiC Package
Extended Operating
Temperature Range
Limited operating
Temperature Range

BLOCK OIAGRAM

Data

3

PIN ASSIGNMENT

Write

Voo

16
15

VSS

14

II

4

13
12

15

10
11

INST
REG

12
13

RST

11

RR

6

4

~

12

J4!-11 JMP
J1,!-10 RTN

At-

Ar!

9-16

FlagO
FlagF

10

8

9

MC14500B

MAXIMUM RATINGS IVoltages referenced to VSSI

Rating
DC Supply Voltage
Input Voltage, All Inputs

Symbol

Value

Unit

VDD
V ,n

-05to+18

V

-05 to VDD + 0.5

V

lin

±10

mA

TA

-55 to +125
-40 to +85

°c

T5 t 9

-65 to +150

°c

DC Input Current, per Pin

Operating Temperature Range - AL DeVice

CLlCP DeVice
Storage Temperature Range

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however.
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high Impedance circuit. For proper
operation it is recommended that Vin and
V out be constrained to the range V SS 0;;;;;;

IVin or Voutl";; VDD.

ELECTRICAL CHARACTERISTICS IVoltages Referenced to VSSI
VDD
Characteristic

Output Voltage
Vin=VDDorO

"0" Level

a or VOO

"1" Level

Vin "'"

Input Voltage

"0" Level

"0" Level

"1" Level

Max

Min

Typ

Max

Min

Max

Unit

VOL

5.0
10
15

-

0.05
0.05
0.05

-

0.05
0.05
0.05

-

0.05
0.05
0.05

V

-

0
0
0

5.0
10
15

4.95
9.95
14.95

-

4.95
9.95
14.95

5.0
10
15

-

4.95
9.95
14.95

-

V

VOH

IVOL = 0.4 VI
IVOL = 0.5 VI
(VOL = 1.5 VI
Output Drive Current
Other Outputs (A L Device)
(VOH
IVOH
IVOH
IVOH

Source

Output Orive Current

Source

IOH

Sink

5.0
10
15

-

1.5
3.0
4.0

-

5.0
10
15

3.5
7.0
11.0

5.0
10
15

-

5.0
10
15

-

2.25
4.50
6.75

1.5
3.0
4.0

-

1.5
3.0
4.0

-

3.5
7.0
11.0

2.75
5.50
8.25

-

3.5
7,0
11.0

-

-

0.8
1.6
2.4

-

1.1
2.2
3.4

0.8
1.6
2.4

-

-

0.8
1.6
2.4

2.0
6.0
10

-

2.0
6.0
10

1.9
3.1
4.3

-

2.0
6.0
10

-

-

V'

-

mA

IOH

IOL

5.0
10
15

-1.2
-3.6
-7.2

-

-1.0
-3.0
-6.0

-2.0
-6.0
-12

5.0
10
15

1.9
3.6
7.2

-

1.6
3.0
6.0

3.2
6.0
12

-

-

-

-

-0.7
-2.1
--4.2

-

1.1
2.1
4.2

mA

5.0
5.0
10
15

-3.0
-0.64
-1.6
-4.2

5.0
10
15

0.64
1.6
4.2

-

-

-2.4
-0.51
-1.3
-3.4

-4.2
-0.88
-2.25
8.8

0.51
1.3
3.4

0.88
2.25
8.8

-

-

-1.7
-0.36
-0.9
-2.4

-

0.36
0.9
2.4

-

mA

IOH

Other Outputs ICL/CP Device)
IVOH ~ 2.5 VI
(VOH ~ 4.6 VI
IVOH = 9.5 VI
(VOH = 13.5 VI
(VOL = 0.4 V)
IVOL = 0.5 VI
IVOl = 1.5 VI

V

VIH

IOL

Source

-

Vll

Sink

Sink

-

VIH

~ 2.5 VI
= 4.6 VI
= 9.5 VI
~ 13.5 V)

IVOL = 0.4 V)
IVOL ~ 0.5 VI
IVOL=1.5V)

-

VIL

IVO = 0.5 or 4.5 V)
IVO = 1.0 or 9.0 VI
IVO = 1.5 or 13.5 VI
Output Drive Current
Data, Write IA L/CL/CP Devicel
(VOH = 4.6 V)
IVOH = 9.5 V)
IVOH = 13.5 VI

Thigh*

25 0 C

Min

IVO = 0.5 or 4.5 V)
IVO = 1.0 or 9.0 V)
IVO = 1.5 or 13.5 VI
Input Voltage #
10,11,12,13
IVO = 4.5 or 0.5 V)
(VO = 9.0 or 1.0 VI
(VO = 13.5 or 1.5 V)

.

V

RST,D,X2
IVO = 4.5 or 0.5 V)
IVO = 9.0 or 1.0 V)
IVO = 13.5 or 1.5 VI
"1" Level

Tlow

Symbol

IOl

5.0
5.0
10
15

-2.5
-0.52
-1.3
-3.6

5.0
10
15

0.52

9-17

1.3
3.6

-

-

-

-2.1
-0.44
-1.1

-4.2

-0.88

-3.0

-2.25
-8.8

0.44
1.1
3.0

0.88
2.25
8.8

.-

-

-1.7
-0.36
-0.9
-2.4

0.36
0.9
2.4

-

-

MC14500B

.

ELECTRICAL CHARACTERISTICS (continued)
Characteristic

Svmbol

VOO
V

Input Current, RST (ALICL/CP Device)

lin

15

Min
25

Input Current (AL Device)

lin

15

-

Input Current (CL/CP Device)

lin

15

Input Capacitance (Datal
Inpu,Capacitance (All Other Inputs)

Gin

-

Quiescent Current (A L Device)

(Per Package) lout = O'/lA,

Gin
100

Vin=O or VOO

Quiescent Current (CL/CP Device)

(Per Package) lout = 0 /lA,

100

Vin=O or VOO

"'*Total Supply Current at an External
Load Capacitance {eli on
All Outputs

IT

25°C

Tlow

Max

Min

-

-

±0.1
±0.3

-

-

-

5.0
10
20

-

5.0
10
15
5.0
10
15

20
40
80

-

-

-

-

-

Thigh'
Max

TVp
150

Max

Min

-

-

250

"A

to.OOOOl

to.l

-

±1.0

"A

±O.OOOOI

±0.3

±1.0

15

-

-

"A
pF

-

5.0

7.5

0.005
0.010
0,015

5.0
10
20

0.005
0.010
O,01S

20
40
80

150
300
600
150
300
600

-

-

IT = (1.5/lA/kHz) 1+100
IT = (3.0 /lA/kHz) I + 100
IT = (4.5 /lA/kHz) I + I DO

-

*

Tlow = -55°C for AL Device, -40°C for CL/CP Device.
Thigh = + 125°C lor AL Device, +85 0 C lor CL/CP Device .

... *

The formulas given are for the typical characteristics only at 25°C.

Unit

pF
/lA

/lA

/lA

SWITCHING CHARACTERISTICS ITA = 25 0 C;tr = tf = 20 n. for X and I inputs; CL = 50 pF for JMP. XI, RR, Flag 0, Flag F;
CL = i 30 pF + 1 TTL load lor Data and Write.!
Characteristic
Propagation Delay Time, X1 to RR

VDO
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
16
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15

Svmbol
tPLH,
tpHL

XI to Flag F, Flag 0, RTN, JMP

X1 to Write

Xl to Data

RST toRR

RSTtoXl

RST to Flag F, Flag 0, RTN, JMP

RST to Write, Data

•

Clock Pulse Width, XI

tW(cI)

Reset Pulse Width, RST

tWIRl

Setup Time - Instruction

Data

Hold Time - Instruction

Data

tsulll

tsulD)

thlll

thlD)

NOTE 1. MaXimum Reset Delay may extend to one-half clock period.

9-18

All TVpas
Min

-

-

-

-

400
200
180
500
250
200
400
250
180
200
100
80
100
50
50
200
100
100

TVp
250
125
100
200
100
85
225
125
100
250
120
100
250
125
100
450
200
150
400
200
150
450
225
175
200
100
90
250
125
100
200
125
90
100
50
40
0
0
0
100
50
50

Max
500
250
200
400
200
170
450
250
200
500
240
200
500
250
200
Note 1

Unit

ns

800
400
300
900
450
360

-

-

ns

ns

-

-

ns

-

ns

-

ns

-

-

ns

MC14500B

FIGURE 1 - TYPICAL CLOCK FREQUENCY
.orsus RESISTOR (Rcl

Pin No.
1
2
3
4
5
6
7

Function

Symbol.
RST
Write
Data
13
12
11
10
VSS
Flag F
FlagO
RTN
JMP
X2
Xl
RR
VOD

Chip Reset
Write Pulse

Oata InlOut
MSB I nstruction Word
Bit 2 Instruction Word
Bit 1 1nstruction Word
LSB I nstruction Word
Negative Supply (Groundl
Flag on NOP F
Flag on NOP 0
Subroutine Return Flag
Jump Instruction Flag

B
9
10
11
12
13
14
15
16

Oscillator 1nput

Oscillator Output
Result Register
Positive Supply

RC. CLOCK FREQUENCY RESISTOR

TABLE 1. MC14500B INSTRUCTION SET
Instruction Code

Mnemonic

a

0000

NOPO

1

0001

LD

Action

No change

RR

registers.

In

Data

Load result register.

~

~

2

0010

LDC

Load complement.

3
4

0011

AND

Logical AND.

0100

AN DC

5

0101

OR

6

0110

ORC

7

0111

XNOR

B

1000

STO

9

1001

STOC

A

1010

lEN

Input enable.

B

1011

OEN

Output enable.

C

1100

JMP

Jump.

0

1101

RTN

Return.

E

1110

SKZ

Skip next instruction if RR = 0

F

1111

NOPF

~

JL

Data-RR

RR'Data~RR

RR·Data

Logical AND complement.

-+

RR

RR + Data- RR

LogicalOR.

RR

Logical OR complement.

I! RR

Exclusive NOR.

RR

Store.

RR, Flag 0

RR

-+

+ Data~RR

= Data, RR ~ 1

Data Pm, Write-..n..

Store complement.

RR

Data

-+

-+

Data Pin, Wrlte-J1..

IEN Aegister

Data -+ OEN Register

JMP Flag ~..fL
RTN Flag -+ J1... and skip next instruction

No change in registers.

RR - RR, Flag F ~JL

FIGURE 2 - OUTLINE OF A TYPICAL ORGANIZATION FOR A MCI4500B-BASED SYSTEM

I
I

Additional
Output Devices

I
I
I
I
r

I
I

L _________ ----'

I/O Address
Memory

.

'C
0

..
U

~

0

I--

.
~

iii

~=
o~

III

E'C

~

~'C

Program
Counter

0

'0, '1, '2. ' 3

Clock

Out~uts .)
To Peripheral
Devices

MC14512
a-Channel
Data Selector

V

r----------,
~

:;;«

MC14599B
a-Bit Addressable Latch
with Bidirectional Data

MC14500B
ICU
Data

f---

9·19

I
I
I
I
I

Additional
Input Devices

I
I
I
I

I

8
Inputs

I
I
r
I
I
I
I
I

, ..J

MC14500B

TIMING WAVEFORMS

Instructions NOPO, NOPF
RR, lEN, OEN remain unaffected

X1

}I~----------~/

RST

f-- tWIR)---jtPHL!--

IRESET TO XI)

lEN

\~--------------------------­

Register

----------1--,\

OEN

Register

' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

RR

~

f-- tPHL IRESET TO

RR)

4 Bit
\
;----\
;----\
Instruction_ _ _ _ _ _ _ _ _ _--'--_ _ _ _ _ _~>--------

FLAG 0
tpLH
IDATA TO FLAG)

FLAG F

==I

NOPO

NOPF

NOPO

l Jk/

~

tPHL

\

Instructions SKZ, JMP. RTN
RR. lEN, OEN remain unaffected

X1

----1

tWlcl)

I--

]r

4 Bit
Instruction
SKZ

RTN

JMP

RST _

JMP

_

RR~L_________________________________________r _ -

II

JMP FI.g _ _ _ _ _ _ _ _ _

~/

....JI

RTN F1S9 ______________________________________

I

SKP FiF
Internal _ _ _ _ _---'

*

Instructions Ignored.

9·20

n-

\

I-

tpHL

\ '(RESET TO

Jump)

MC14500B

TIMING WAVEFORMS
Instructions STO, STOe, OEN

x,

4,Bit
Instruction

STOC

Data

RR
tpLH,tpHL (Xl to Datal
OEN Register
(internal)

Write

Valid when RST '" L

NOTE 1. Valid output data.

Instructions LO, lOC, AND, ANDC
OR, ORC, XNOR, lEN

x,
LD, etc.

4 Bit
Instruction

Data

RR

lEN Register
(internal)

Valid when RST '" L

9·21

•
9-22

Reliability

10-1

II

®

MOTOROLA
Introduction

This chapter is intended to demonstrate the quality and
reliability aspects of the semiconductor products supplied by
Motorola.

Quality in Manufacturing
aUALlTY IN DESIGN
Motorola's quality activity starts at the product design
stage. It is its philosophy to "design in" reliability. At all
development points of any new design reliability orientated
guidelines are continuously used to ensure that a thoroughly
reliable part is ultimately produced. This is demonstrated by
the excellent in-house reliability testing results obtained for
all Motorola's semiconductor products and, more Importantly, by our numerous customers.

a

NEW PRODUCT TYPICAL DESIGN FLOW
Circuit Design

Package

MATERIAL INCOMING CONTROLS
Each vendor is supplied with a copy of the Motorola Procurement Specification which must be agreed in detail between both parties before any purchasing agreement is made.
This is followed by a vendor appraisal report whereby each
vendor's manufacturing facility is visited by Motorola Quality
Engineers responsible for ensuring that the vendor has a well
organized and adequately controlled manufacturing process
capable of supplying the high quality material required to
meet the Motorola Incoming Inspection Specification. Large
investments have and are continuously being made and
auality Improvement programs developed with our main
suppliers concerning:
Masks - Silicon - Piece-parts - Chemical products Industrial gas, etc.
Each batch of material delivered to Motorola is quarantined at Goods-in until the Incoming Quality Organization
has subjected adequate samples to the incoming detailed inspection specification. In the case of masks, this will include
mask inspection for:
1. Defect Density
2. Intermask Alignment
3. Mask Revision
4. Device to Device Alignment
5. Mask Type
Silicon will undergo the following inspections:
1. Type "N" or "P"
2. Resistivity
3. Resistivity Gradient
4. Defects
5. Physical Dimensions
6. Dislocation Density
Incoming -chemicals are also controlled to very rigorous
standards. Many are submitted to in-house chemical analysIs
where the supplier's conformance to specification is

Process

Engineering Sample

Commercial Sample
This baSIC design flow-chart omits
some feedback loops for simplicity

meticulously checked. In many cases, line tests are performed before final acceptance. A major Issue and responsibility
for the Incoming Quality Department is to ensure that the
most disciplined safety factors have been employed with
regard to chemicals. Chemi-cals can and are often rejected
because safety standards have not been deemed acceptable.

10-2

BIPOLAR WAFER FABRICATION

WAFER FABRICATION
All processing stages of Motorola products are subjected
to demanding manufacturing and quality control standards.
A philosophy of "Do it Right the First Time" IS instrumental
in assuring that Motorola has a reliability record second to
none.
The Bipolar and MOS Wafer Fabncation flow charts are
examples which highlight the various In process control
POints audited by both Manufacturing and Quality people.
The majority of these Inspections are control audit points
with inspection gates at cntlcal points of the process, this IS
In line with Motorola policy of all personnel being responsible
for quality at each manufacturing stage.
Diffusion and ion implantation processing is subject to
oxide thickness controls penetrallon evaluations. Controls
are also performed on resistivity and defect density. Diffusion furnaces, metallization, and passivation equipment are
subjected to daily qualification reqUIrements by using C- V
plotting techniques. C-V techniques are also used to ensure
ongoing stability as they do provide a very sensitive measurement of ionic species concentration.
In addition many other specific controls are used as a
means to ensure bUilt-in reliability and provide statistical
trend data, which include:

•
•
•
•
•

Environmental monitoring for humidity, temperature
and particles
Deionized water resistivity, particles and bacteria
checks in water
Epitaxial matenal: resistivity - thickness - crystal
defects
Oxide: thickness - charges - pinhole density
Metallization: thickness - adherence - metal composition - ohmic contacts

• Doping profiles
• Pre and post etch inspections
• In process SEM analysis for step coverage: metallization - grain size - phosphorous concentration
• Passivation integnty checks
• Calibration
• Final visual Inspection gate.
After all processing stages are completed, every wafer lot
IS subject to a detailed electrical parameter check.
Parameters such as threshold voltage, junction breakdown
voltages, resistivity, field inversion voltages, etc., are
measured and each batch IS sentenced accordingly. The data
generated at this point is treated statistically as a control on
the distribution of each key electrical parameter thus allowing corrective action adjustments to be Implemented in a
timely manner.
Every wafer lot is submitted to an electrical probe test during which every individual die is tested to its electrical
specification. Chips which fail are individually inked.

o
10-3

In Process
or Control Process
or G.A. InspectIon

MOS WAFER FABRICATION

In-Process
Inspection

•

ASSEMBLY
The assembly operation is of equal importance to the
wafer fabrication process as a manufacturing activity which
will effect the reliability of the finished product. Motorola
continuously makes major investments in specialized
assembly areas located in Malaysia, the Philippines and
Korea. These assembly plants employ the latest technologies

10·4

0

available to ensure that all Motorola semiconductors are produced to the highest standards of Quality and Reliability. In
addition, each wafer fabrication facility has in-house
assembly capability which allows some production, specific
engineering activity and qualification of piece-parts suppliers. The major production volumes of Motorola's Integrated Circuits are assembled offshore in the Far East.

id'Jntical Quality and Reliability philosophies are practiced
in the assemoly areas as within the wafer fabrication
facilities. Quality Assurance Audits for immediate corrective
actions are performed after major process steps as demonstrated in the flow-chart. In addition, screening options are
available. The statistical data obtained from quality audits are
reported to the appropriate business centers either daily,
weekly or monthly for review.
Motorola is particularly aware of the major impact
moisture can have on the reliability performance of either
plastic or ceramic parts. With this in mind several major new
innovations have been introduced to safeguard Motorola
products and thus enhance their overall reliability performance, these include:
• Faraday shield vacuum packed wafer shipping system
• Temperature and humidity controlled wafer inventory
stores
• Inert atmosphere for metal can packages encapsulation
• New design lead frames I plastic assemblyl
• New molding compounds
• Low moisture content glass

•
•

Moisture content audit procedures
Super dry piece-part controls

FINAL TESTING
Each of Motorola's facllties has a complete Final Test
capability for all of the products fabricated and assembled.
The majority of products, after assembly, are tested and
Q.A. released at the facility responsible for that product.
Some product is tested in the offshore assembly site;
however, this is always returned to the facility for Q.A.
release prior to final shipment to customer.
Final Test is a comprehensive series of dc, functional
and speed orientated electrical tests as well as adapted
forced tests. These tests are normally more stringent than
data sheet requirements and are finally sampled by Outgoing
Quality Assurance.
In practice, the test flow philosophies vary according to
product. For instance, most of the Discrete devices are double tested as part of a zero defect quality improvement program. As well, many Integrated Circuits are tested at various
temperatures. There are also many burn-in options available.

TYPICAL INTEGRATED CIRCUITS ASSEMBLY AND FINAL TEST FLOW CHART

10-5

OUTGOING OUALITY SAMPLING PLAN
A.O.L
Electrical Inoperative

Rectifiers

Parametric
Visual! Mechanical

1979
010
0040
0.25
0.25
0.65
0.15
0.10
0.40
0.25
0.15
065
0040

1980
0.10
040
025
0.15
0040
0.15
0.10
0.40
0.25
0.15
0.65
0.40
LTPD

Linear

Electrical Inoperative
Parametric
V,suall Mechamcal

Power Transistors

Electrical Inoperative
Parametric
Visuall Mechanical

Small Signal Transistors

Electrical Inoperative
Parametric
Visual I Mechanical

CMOS

Function/ Parametric
Vlsuall Mechanical

LTPD

15.0)

15.0)

MOS Microprocessors

Function/ Parametric
V,suall Mechanical

LTPD

LTPD

15.0)

15.0)

NMOS Memories

Functlon/ Parametric
V,suall Mechanical

LTPD

LTPD

LS TTL ECL
Bipolar Memoryl LSI

Functlonl Parametric
Visuall Mechanical

15.01
0.15
065

15.01
0.15
015

ALS/FAST

Function! Parametric
Vlsual/ Mechanical

1981
0.065
0.25
0.15
0.15
0040
0.15
0.10
0.40
0.25
0.10
0040
0.25
015
0.15
0.15
0.15
0.15
0.15
0.065
0.065

1982
0.065
0.25
0.15
0.15
0.40
015
0.10
040
0.15
0.10
040
0.15
0.10
015
010
0.15
0.10
015
0065
0.065
0.065

1993
0.065
0.25
0.10
0.10
025
0.15
0.10
025
0.15
0.10
0.40
0.15
0.10
0.15
0.10
015
0.10
0.15
0.065
0.065
0.065

EVOLUTION OF AVERAGE OUTGOING OUALITY - A.O.O.
ITOTAL A.O.O. INCLUDING VISUAL, MECHANICAL AND ELECTRICAL)

Bipolar Linear I/C's
X - X Rectifiers

10

0

0

z-z

TranSistors
Bipolar Dlgitall/C's

8

x

6

::;;
a..
a..

4

1976

1977

1978

1979

1980

•
10-6

1981

1982

1983

In many published cases, stated PPM values refer to Electrical Inoperative failures only.
At Motorola, the Electrical Inoperative, the Electrical
Parametric and the Visual/ Mechanical failure rates are
calculated separately and then combined to reach an overall
total. In thiS way Motorola believes that IS giving Its
customers a true and accurate assessment of the quality of
the product. Unqualified PPM statements can be misleading
and cause the customer to expect quality levels which cannot be achieved. For example, Motorola MaS Logic A.O.Q.
is separated into Electrical Inoperative/Electrical Parametric
(280 PPM) and Visual/Mechanical (486 PPM!. Other product
families such as Small Signal Plastic Transistors are already
reaching 50 PPM in Electrical Inoperative failure rate.
The Motorola PPM graphs are excellent examples of what
has been achieved over the last years with regard to quality
improvements.
Reductions between 50% and 300% in average outgoing
quality are typical across the broad range of Motorola products.
Throughout the semiconductor industry there have been,
and there still are, examples of manufacturers offering higher
quality standards at a premium. This is not a Motorola
strategy, we believe that our customers should expect high
quality products at no extra cost. This is Motorola's aim and
we will continue to aggressively pursue Quality and ReliabilIty Improvements which will be passed on to our customers
as an obligation on our part.
Also, we actively encourage our customers to provide
their quality results at their Incoming Inspection, during their
manufacturing process and from the field in order to better
correlate and further improve our quality performance.

OUTGOING QUALITY
Although test procedures may vary from product to product within Motorola, the same philosophy applies when
considering quality oblectlves Motorola's mission IS to be a
Quality and Reliability leader worldwide.
HIGHLIGHTS:
Motorola recognizes that you, our customers, are truly
concerned about improving your own quality image. You
are, therefore, concerned about the quality of the product
Motorola supplies you.
Our customers measure us by the level of defects In the
products we supply at incoming inspection, during assembly
and, most important, field reliability.
DUring the past years, Motorola has achieved Impressive
reductions In defect rates known as A.O.Q or Average
Outgoing Quality. Instrumental In thiS success has been the
planned continuous reduction in outgoing A.Q.l. to a pOint
where Motorola believes that over all products It can
demonstrate the most aggressive A.Q. L.'s In the industry.
This aggressive program has been designed to help eliminate expensive incoming inspection at our customers.
All of the facilities also practice an extremely demanding
parts per million program program (PPM).
The PPM performance of all Motorola products is
calculated in each location using the same method; they are,
therefore, directly comparable. Motorola is well aware that
when discussing PPM with eXisting or potential customers, it
is of paramount Importance to explain exactly which failure
categories are included in the stated PPM figures.
Motorola's PPM figures will Include·
• Electrical Inoperative Failure
• Electrical Parametric Failures (dc and ael
• Visual and Mechanical criteria.

MOTOROLA A.O.O. PLAN
History
Average
1980

Power Transistors

3400

Goal
Dec

1981
1400

1982
1100

1982
950

Rectifiers

1750

1100

1000

Small Signal Metal
Small Signal PlastiC
Linear IIC's
Land S.F

4100

2200

1400

950
1100

1500

1200

1030

800

4300

2800

1800

5000
7000

2370
4360

1380
2400

2000
1150

7000
1260

3860

2450

802
1200

975

Memory

Microprocessor

Bipolar Digital LogiC
Bipolar Memoryl LSI

1620

1000

A 0.0. Includes all Defects: Visual, Mechanical,
Electrical Inoperative and Parametnc

10-7

2900
2900

800
151

1983
700
700
800

600
1000
500
1300
1300
500
700

AVERAGE A.O.a. IN P.P.M. FOR MOS PRODUCTS FIGURES
INCLUDE FUNCTIONAL! PARAMETRICIVISUALI MECHANICAL

9000

_Micro

8000

x-x

Memory

0---0 CMOS

7000
6000

5000
4000

3000

2000

1000
500
250
1979

1980

1981

1982

RELIABILITY
Paramount in the mind of every semiconductor user is the
question of device performance versus time. After the applicability of a particular device has been established, its effectiveness depends on the length of troublefree service it
can offer. The reliability of a device is exactly that - an expression of how well it will serve the customer. The following
discussion will attempt to present an overview of Motorola's
reliability efforts.
BASIC CONCEPTS
It is essential to begin with an explanation of the various
parameters of Reliability. These are probably summarized
best in the Bathtub Curve (Figure 11. The reliability performance of a device is characterized by three phases: infant

mortality, useful life and wearo~t. When a device is produced, there is often a small distribution of failure
mechanisms which will exhibit themselves under relatively
moderate stress levels and therefore appear early. This
period of early failures, termed infant mortality, are reduced
significantly through proper manufacturing controls and
screening techniques. The most effective period is that, in
which only occassional random failure mechanisms appear;
the useful life typically spans a long period of time with a
very low failure rate, The final period is that in which the
devices literally wear out due to continuous phenomena
which existed at the time of manufacture. Using strictly controlled design techniques and selectivity in applications, this
period is shifted well beyond the lifetime required by the
user.

FIGURE 1

FIGURE2

I I

a

~~

50% CL

,'nf~nt ~o~tali'ty ,

(Such as Early
Burn-In Failures)

I I

'\

1983

V'

V
...... ·Wearaut

Useful Life

I I I
10

100

1000 10,000 100,000
Time (Hours)

Failures

I I I
1,000,000

}., Failure Rate

10-8

Both the infant mortality and random failure rate regions
be described through the same types of calculations.
During this' time the probability of having no failures to a
specific pOint in time can be expressed by the equation:
~dn

where A is the failure rate and t is time. Since A is, changing
rapidly during infant mortality, the expression/does not
become useful until the random period, where A',S relatively
constant. In this equation A is failures per unit of time. It is
usually expressed in percent failures per thousand hours.
Other forms include FIT (Failures In Time= (%/103 hrsl
x 10- 4= 10- 9 failures per houri and MTTF (Mean Time To
Failurel or MTBF (Mean Time Between Failuresl, both being
equal to 1II. and having units of hours.
Since reliability evaluations usually involve only samples of
an entire population of devices, the concepts of the Central
Limit Theorem apply and A is calculated using x2 distribution
through the equation:

A :S x2 (x, 2r+ 2)
2nt
where x = 100- CL
100
CL = Confidence Limit in percent
r
Number of rejects
n
Number of devices
t
Duration of test
The confidence limit is the degree of conservatism desired
in the calculation. The Central Limit Theorem states that the
values of any sample of units out of a large population will
produce a normal distribution. A 50% confidence limit is
termed the best estimate and is the mean of this distribution.
A 90% confidence limit is a very conservative value and
results in a higher A which represents the point at which 90%
of the area of the distribution is to the left of that value
(Figure 21. The term (2r+ 2) is called the degrees of freedom
and is an expression of ihe number of rejects in a form
suitable to x2 tables.
The number of rejects is a critical factor since the definition of rejects often differs between manufacturers. While
Motorola uses data sheet limits to determine failures
sometimes rejects are counted only if they are catastrophic:
DUB to the increasing chance of a test not being representative of the entire population as sample size and test time
are decreased, the x2 calculation produces surprisingly high
values of A for short test durations even though the true long
term failure rate may be quite low. For this reason relatively
large amounts of data must be gathered to demonstrate the
real long term failure rate.
Since this would require years of testing on thousands of
devices, methods of accelerated testing have been
developed.
Years of semiconductor device testing has shown that
temperature will accelerate failures and that this behaviour
fits the form of the Arrhenius equation:
R (t) = Roltle- 9/kT

where RItI = Reaction rate as a function of time and
temperature
RO = A constant
t
Time
e
Activation energy in electron volts
k
Boltzman's constant
T
Temperature in degrees Kelvin
To provide time-temperature equivalents this equation is
applied to failure rate calculations in the form:
t =

toe 9/kT

where t = time

to = A constant
The Arrhenius equation essentially states that reaction rate
increases exponentially with temperature. This produces a
straight line when plotted on log-linear paper with a slope expressed bye. e may be physically interpreted as the energy
threshold of a particular reaction or failure mechanism. The
activation energy exhibited by semiconductors varies from
about 0.3 eV. Although the relationships do not prohibit
devices from having poor failure rates and high activation
energies, good performance usually does imply a high e.
Studies by Bell Telephone Laboratories have indicated that
an overall e for semiconductors is 1.0 eV. This value has
been accepted by the Rome Air Development Command for
time-temperature acceleration in powered burn-in as
specified in Method 1015 of MIL-STD-883. Data taken by
Motorola on Integrated Circuits have verified this number
and it is therefore applied as our standard time- temperature
regression for extrapolation of high temperature failure rates
to temperatures at which the devices will 00 used (Figure 3).
For Discrete products, 0.7 eV is generally applied.
To accomplish this, the time in device hours (t11 and
temperature 1T1) of the test are plotted as point P1. A vertical line is drawn at the temperature of interest (T2) and a
line with a 1.0 eV slope is drawn through point P1.
Its intersection with the vertical line defines point P2, and
determines the number of equivalent device hours (121. This
number may then be used with the x2 formula to determine
the failure rate at the temperature of interest. Assuming T1
of 125° C at t1 of 10,000 hours, a t2 of 7.8 million hours
results at a T2 of 50°C. If one reject results in the 10,000
device hours of testing at 125°C, the failure rate at that
temperature will be 20% /1 ,000 hours using a 60% confidence level. One reject at the equivalent 7.8 million device
hours at 50° C will result in a 0.026% I 1,000 hour failure rate,
as illustrated in Figure 4.
Three parameters determine the failure rate quoted by the
manufacturer: the failure rate at the test temperature, the activation energy employed, and the difference between the
test temperature and the temperature of the quoted A. A
term often used in this manipulation is the" acceleration factor" which is simply the equivalent device hours at the lower
temperature divided by the actual test device hours.
Every device will eventually fail, but with the present
techniques in Semiconductor design and applications, the
wearout phase is extended far beyond the lifetime required.
During wearout, as in infant mortality, the failure rate is
changing rapidly and therefore loses its value. The parameter

10-9

used to describe performance In this area is "Median life"
and is the point at which 50% of the devices have failed.
There are currently only few significant wearout

mechanisms: electromigration of circuit metallization, electrolytic corrosion in plastic deVices aQd metal fatigue for
Power devices ..

FIGURE 3
NORMALIZED TIME-TEMPERATURE
REGRESSIONS FOR VARIOUS ACTIVATION
ENERGY VALUES

l000k
1.2

1.6

20

2.4

2.8

I

3.2

I II II

/I I I
/I
II I

~1

/I

f
'1/

/IV
/

rl I 'I
rll fll I

~2

III!. /

1'111

PI /

'II

I

I

,

J

r'1

/

"

~

/

I
500

7

a:

~

~1

i!:

0.01

~
\

::r

_"Y

\

-.

1\

...i ,,\

I

I \

-.
T

0.001

T

I

T

0.0001

I
I

I

,I

./

T

i
I
I

I

i

I

200

i\

;I

"

O. 1

.<

I

100

I

0.00001

W

500

Temperature (OCl'

3.6

10

~

./

32

I\'

~

'$.

-'2

2.8

11.

§

I

~

2.4

\

'§

11/18. f// VI V
'/

2.0

10

./
./

/

16

~2

'P2/

/I rJ// V/ j

IJ 'I
II, fII

lOOk
1.2
100

36

I.

I

I

FIGURE 4
FAILURE RATE

200

100

50

o

Temperature (OCI

For Increased flexIb,lity in working with a broad range
of device hours. the time-temperature regression lines
have been normalized to 500° C and the tIme scale
omItted, permitting the user to define the scale based
on hIS own requirements.

Reliability
RELIABILITY TESTS:
DEFINITION, PURPOSE AND PROCEDURES
These definitions are intended to give the reader a brief
understanding of the test currently used at Motorola for
reliability checking. They also state which main failure
mechanisms are accelerated by the test.

•

HIGH TEMPERATURE STORAGE LIFE
An environmental test. where only temperature is the
stress. Temperature and test duration must be specified.
Usually temperature is the maximum storage temperature of
the devices under lest. Main failure mechanisms are
metallization, bulk silicon, corrosion.
HIGH TEMPERATURE REVERSE BIAS (HTRBI
An environmental stress combined with an electrical stress
whereby devices are subjected to an elevated temperature
and simultaneously reverse biased. To be effective, voltage

must be applied to the devices until they reach room
temperature at the completion of the test. Temperature, time
and voltage levels must be specified. Accelerated failure
mechanisms are inversion, channeling, surface contamination, design.

HIGH HUMIDITY, HIGH TEMPERATURE REVERSE
BIAS (H3TRBI
A combined environmental/electrical stress whereby
devices are subjected to an elevated ambient temperature
and high humidity, simultaneously reverse biased for a
period of time. Normally performed on a sample basis
(qualification) on non-hermetic devices. The most common
conditions is 85° C and 85%. relative humidity. More extreme
conditions generally are very destructive to the chambers
used. Time, temperature, humidity and voltage must be
specified. This accelerated test mainly detects corrosion
risks.

10-10

STEADY STATE OPERATING LIFE
An electrical stress whereby devices are forward (reverse
for zenersl biased at full rated power for prolonged duration.
Test IS normally 25° C ambient and power is 100% of full
rated. (For power deVices the I/C's maximum operating TI is
used.) Duration, power and ambient. If other than 25°C,
must be specified. Accelerated failure mechanisms mainly
are metallization, bulk silicon, oxide, inversion and channelIng.
DYNAMIC OPERATING LIFE
An electrical stress whereby devices are alternately subjected to forward bias at full rated power or current and
reverse bias.
Duration, power, duty cycle, reverse voltage ambient and
frequency must be specified. Used normally for rectifiers and
silicon controlled rectifiers. Failure mechanisms are essentially the same as steady state operating life
INTERMITTENT OPERATING LIFE
(POWER CYCLING)
An electrical stress whereby devices are turned on and off

for a period of time. During the "on" time the devices are
turned on at a power such that the Junction temperature
reaches ItS maximum rating. DUring "off" cycle the devices
return to 25°C ambient. Duration, power, Dr duty cycle must
be individually specified. Accelerated failures mechanisms
are mainly die bonds, wire bond, metallization, bulk silicon,
and oxide.
THERMAL SHOCK (TEMPERATURE CYCLING)
An environmental stress whereby devices are alternately
subjected to a low and high temperature With or without a
dwell time in between to stabilize the deVices to 25°C ambient - the medium is usually air. Temperatures, dwell times
and cycles must be specified. Failure mechanisms are essentially die bonds, wire bonds, and package.
THERMAL SHOCK (GLASS STRAIN)
An environmental stress whereby the devices are subjected to a low temperature, stabilized and immediately
transferred to a high temperature. The medium is usually liquid. Failures mechanisms essentially are the same as
temperature cycling.

EXAMPLE OF NEW PROCESS QUALIFICATION TESTS

Test
Operating Life

MIL-STD-883
Reference
Test Method
1005

Condition
125°C, 5 V or 15 V

Duration
1.000 Hours

85°C, 85% R H
5 Vor 15 V

1,CJOO Hours

121°C. 100% R.H.
15P S.I.G.

144 Hours

150°C

1,000 Hours

Thermal Cycle
lAir to Alrl

- 65°C to 150°C
5 Min Dwell

1,000 Cycles

1010

Thermal Shock
I liqUid to LiqUid)

- 65°C to 150°C
5 Min Dwell

1,000 Cycles

1011

1,5OOG, 3 per Axis
150- 2,000 Hz, 20 g
30 kg

0.5 MS
2 Hours

2002
2007
2001

200/250°C

1.000 Hours

Temperature HumIdity
Bias
Autoclave

High Temperature

Storage

Shock, VibratIOn, and
Constant Acceleration

Data Retention Bake
(Non Volatlon MemOries)

10-11

MECHANICAL SHOCK

VIBRATION VARIABLE FREQUENCY

A mechanical stress whereby the devices are subjected to
high impact forces normally in two or more of the six orientations Xl, Y1, Zl, X2, Y2, 12. Tests are to verify the physical
integrity of the devices. G forces, pulse duration, and·number of shocks and axes must be specified.

Same as Vibration Fatigue except that frequency is logarithmically varied from 100 Hz to 1 kHz and back. Number
of cycles is normally four. Cycle time, amplitude and total
duration must be specified. Failure mechanisms are mainly
package, wire bond - this test is not applicable to molded
devices.

EXAMPLE OF NEW PACKAGE QUALIFICATION TESTS

Condition

Duration

MIL-STO-883
Reference
Test Method

125°C, 5 V or 15 V

1,000 Hours

1005

B5°C, 85% R.H.
5 V or 15 V

1,000 Hours

121°C, 100% R.H.
15 P.S.I.G.

144 Hours

150°C

1,000 Hours

Thermal Cycle
(Air to Airl

-B5°C to 150°C
5Min Dwell

1,000 Cycles

1010

Thermal Shock
(Liquid to Liquid)

-B5°C to 150°C
5Min Dwell

1,000 Cycles

1011

1,500 G, 3 per Axis
150-2,000 Hz, 20 g
30 kg

0.5ms
2 Hours

2002
2007
2001

Test
Operating Life
Temperature Humidity Bias

Autoclave

High Temperature Storage

Shock, Vibration, and
Constant Acceleration

Hermeticity

1.B5,lO- 8
atmcc/sec

1014

Outline Dwg.

2016

Visual Inspection

Dimensions

2008

Marking Permanency
Solderability
Wire Bond Strength
(Post Seall

2015
230°C
1.5 Gram

Die Shear

3 Seconds

2003
2011

2027,_

•
10-12

EXAMPLE OF STANDARD RELIABILITY PROGRAM
Reliability
Engineering
Department

Motorola Reliability Program For:
Test

SS

Frequency

Thermal Shock

25

1 Product Line
Per Week

High Temperature

40

Test Group
Reliability Audit

Test Methods! Conditions
Mll-STD-883, Method 1011
- 25 DC, + 125 DC.
Dwell Time 5 mn, 100 Cycles
TA= 150 DC, VCB=.8 VCB max. 168 hours

Reverse Bias
Ufe Tests

High Temperature

Reverse Bias
High Temperature
Storage
Steady State
life

25
(+2)

3 Product lines
Per Month

25
(+2)

TA= 150 DC, 1,000 hours

25
(+2)

MIL-STO-883, Method 1005
TA= 125 DC, 1,000 hours
TA=85 DC,85% Humidity

25

High Humidity

TA_l50 DC, VCB-.8 VCB max. 1,000 hours

VCB = .8 VCB max. 1,000 hours

High Temperature

(+21

Reverse Bias

( + 2) devices for correlation purpose

Product Family

Device Hours

No. Of
Failures

Activation

Test Conditions

591,552

64

% Per 1,000 Hours
At 60% Confidence

1 eV

Derated
Temperature
70 DC

Energy

0.014

Non Hermetic

Operating

Interface I/G's

Tj= 155 DC

Consumer I/C's

Operating
TI=125 DC
TI _l50 DC
VR=.8 BVR
Tj_l00DC
VR=.8 BVR
Tj 150 DC
VA=.8 BVR
T'_l50 DC
VC~=.8 BVCO

13,082,000

39

1 eV

70 DC

0.0029

798,000

5

.7 eV

70 DC

0.009

295,000

3

.7 eV

70 DC

0.21

520,000

5

.7 eV

70 DC

0.014

579,000

6

.7 eV

70 DC

0.014

Small Signal
Metal
Transistor

Tj= 150 DC
VCB =.8 BVCBO

3,944,000

12

.7 eV

70 DC

0.0039

Case 77
Power Plastic
Transistor

Tj= 150 DC

364,416

2

.7 eV

70 DC

0.0097

VBC=.8 BVCBO
Tj_l50 DC

368,080

0

.7 eV

70·C

0.0028

TranSistor
T03P
Power Plastic
TranSistor

VCB =.8 BVCBO
Tj-l50 DC

297,024

3

.7 eV

70 DC

0.016

T03
Power Metal
TranSIstor

Tj-l50'C

247,104

3

.7 eV

70 DC

0.G19

004/005
Rectifier
Plastic
Axial Diodes
Button Diodes
Small Signal
Plastic
Transistor

T0220
Power Plastic

VCB = .8 BVCBO

VCB = .8 BVCBO

10-13

Device Hours
6.5x 107

No. of
Failures
11

Activation
Energy

Derated
Temperature
50°C
65°C

% Per 1.000 Hours
At 60% ConfidenCe'
0.00074
0.025

125°C
Static Bias

2.1 x loB

17

1 EV

85°C

0.0088

125°C

2.88x 106

47

1 EV

70°C

0.039

434,456

3

1 EV

70°C

0.009

250°C Bake

519.120

3

0.7 EV

70°C

0.0075

125°C

917.280

25

1 EV

70°C

0.027

956.672
1.05x loB

19

0.7 EV

70°C

0.020

6

0.7 EV

70°C

0.028

No. of
Failures

Activation
Energy

Derated

Temperature

% Per 1,000 Hours
At 90% Confidence

1.0 eV

70°C

0.0029

Product Family

Teat Conditions

CMOS Ceramic

125°C
Static Bias

CMOS Plastic

6800 Series
Plastic

1 EV

Dynamic Bias
5V

U.V. EPROM
Life Test

125°C

DynamiC Bias
5V
Data Retention
EEPROM
Life Test

Dynamic Bias
5V
Data Retention

250°C

64K DRAM

125°C
Dynamic 818S
5.5 V

Product Family

Teat Conditions

lS-TTl

125°C
Static Basis
-5.2 V

ECl

125°C
Static Bias
5V

61.74x 106

7

1.0 eV

85°C

0.0189

Product Family

Teat Conditions

Device Hours

No. of
Failures

Activation
Energy

Derated
Temperature

% Per 1,000 Hours
At 60% Confidence

Operational
Amplifier

Operating
Tj= 135°C

437,472

2

1 eV

70°C

0.0026

Hermetic

Operating
TJ= 135°C

718,848

4

1 eV

70°C

0.0033

Interface IIC's

II

Device Hours

The reliability approach at Motorola Semiconductors is
based on designing in reliability rather than testing for reliability only. This concept is reflected by Motorola's mandatory procedures which require product, process and
packaging qualification on three independently produced
lots before any product is released to volume production.
Reliability engineering approval supported by an officially
documented report is required before any product is released
to manufacturing. Tests at both maximum rated and accelerated stress levels are performed. Acceleration is important to determine how and at what stress level a new design,
product process or package would fail. This information provides an indication of what design changes can be implemented to ensure a wider and safer margin between the
maximum rated stress condition and the devices stress
limitation.

an ongoing reliability monitor which covers all process and
packaging options. This program provides a continuous upto-date data base which is summarized in periodical reports.
Reliability statistics supporting all Motorola Semiconductor devices can be obtained from any of the Motorola Sales
Offices upon request. The present operating life test results
demonstrates Motorola's reputation for producing semiconductors with reliability second to none.
The Quality organization in each facility is responsible for
preparing and maintaining a Quality Manual which describes
in detail the quality systems a'nd associated Reliability and
Quality Assurance organization, policies, and procedures.
This manual must be appraised and ultimately approved by
the appropriate approval authority.

As well as qualifying all new products, processes and
piece-parts, each Motorola manufacturing facility operates

10-14

Package Dimensions
11-1

PACKAGE DIMENSIONS
The package availability for each device is indicated on the front page of
the individual data sheets. Dimensions for the packages are given in this
chapter.

- - - - - - - - 1 4 · P I N PACKAGE-------PLASTIC PACKAGE
CASE 646-05

NOTES:
1. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.

3. DIMENSION "8" DOES NOT
INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL.

11·2

MILLIMETERS
DIM MIN
MAX
A 18.16 19.56
6.10
6.60
B
5.08
C
4.06
0.38
0.53
D
1.02
1.78
F
2.54 BSC
G
2.41
H
1.32
0.38
J
0.20
2.92
K
3.43
7.62 BSC
L
100
00
M
0.51
1.02
N

INCHES
MIN
MAX
0.715 0.770
0.240 0.260
0.160 0.200
0.015 0.021
0.040 0.070
0.100 BSC
0.052 10.095
0.008 10.015
0.115 10.135
0.300 BSC
100
00
0.020 0.040

PACKAGE DIMENSIONS (Continued)
- - - - - - - - 1 6 · P I N PACKAGE - - - - - - - PLASTIC PACKAGE
CASE 648-05

Q1~
:
:
:
:
:
:
:lJ
~
c
~F~
1\
J
_~'" fE3!

OPTIONAL LEAD
CONFIG. (1,8,9,& 16)

,

A

H~ --I G I--

-\j]rJI~

JLD

NOTES:
1. LEAOS WITHIN 0.13 mm
(O,OOS} RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L"TO
CENTER OF LEADS
WHEN FORMED
PARALLEL.

SEATING K
PLANE

...JLJ

M

l.

3. DIMENSION "8" DOES NOT
INCLUDE MOLD FLASH.
4. "F" DIMENSION IS FOR FULL
LEADS. "HALF" LEADS ARE
OPTIONAL AT LEAD POSITIONS
1,8,9,and 16}.
5. ROUNDED CORNERS OPTIONAL.

MILLIMETERS
DIM MIN
MAX
A 1'8.80 21.34
B
6.10
6.60
C
4.06
5.08
D
0.38
0.53
F
1.02
1.78
G
2.54 BSC
H
0.38 I 2.41
J
0.20 I 0.38
K
l.9l
3.43
7.62 BSC
L
0
M
0
I 100
0.51 I 1.02
N

INCHES
MIN
MAX
0.740 0.840
0.240 0.260
0.160 0.200
0.015 0.021
0.040 0.070
0.100 BSC
0.015 I 0.095
0.008 I 0.015
0.115 0.135
0.300 BSC
00 I 100
0.020 I 0.040

CERAMIC PACKAGE
CASE 620-08

1. LEADS WITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONOITION.
2. PACKAGE INDEX: NOTCH IN LEAD
NOTCH IN CERAMIC OR INK DOT.
3. DIM "L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIM "A" AND "B"DO NOT INCLUDE
GLASS RUN·OUT.
5. DIM "F" MAY NAR ROW TO 0.76 mm
(0.030) WHERE THE LEAD ENTERS
THE CERAMIC BODY.

11-3

INCHES
MILLIMETERS
DIM MIN
MAX
MIN
MAX
A 19.05 19.94 0.750 0.785
7.49 0.240 0.295
B
6.10
0.200
5.08
C
0
0.38
0.53 0.Q15 0.021
1.40
1.78 0.055 0.070
F
2.54 BSC
0.100 BSC
G
1.14 0.020 0.045
H
0.51
0.20
0.30 0.008 0.012
J
3.18
4.32 0.125 0.170
K
7.62 BSC
0.300 BSC
L
150
150
M
N
0.51
1.02 0.020 0.040

III

PACKAGE DIMENSIONS (Continued)
--------18·PIN

PACKAGE'---~-""--

PLASTIC PACKAGE
CASE 707·-02

MILLIMETERS
DIM MIN
MAX
A 22.22 23.24
6.60
6.10
B
3.56
4.57
C
0.56
0.36
D
1.27
F
1.78
2.54 esc
G
1.52
H
1.02
J
0.20
0.30
K
2.92
3.43
L
7.6 BSC
00
M
15 0
N
0.51
1.02

INCHES
MIN
MAX
0.875 0.915
0.240 0.260
0.140 0.180
0.014 0.022
0.050 0.070
0.100 esc
0.040 0.060
0.008 0.012
0.115 0.135
.3m esc
150
00
0.020 0.040

MI LLiMETERS
DIM MIN
MAX
A 22.35 23.11
e 6.10 7.49
I
5.08
C
D 0.38
0.53
I \
F
1.40
1.78
M \--- G
2.54 BSC
H
0.51
1.14
0.20
0.30
J
K
3.18
4.32
7.62 BSC
l
M
15 0
00
0.51
1.02
N

INCHES
MIN
MAX
0.880 0.910
0.240 0.295
0.200
0.015 0.021
0.055 0.070
0.100BSC
0.020 0.045
0.008 0.012
0.125 0.170
0.300 BSC
00 I 15 0
0.020 I 0.040

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (DI,
SHALL BE WITHIN 0.25mm(0.0101 AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TD SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.

CERAMIC PACKAGE
CASE 726-04

l----A~
'I

18

I
--,-

1

~G~

tLJ

~-;;]·IA:
-l-;--T,

J~
;

H

•

'L
II

FI..

--I

D

l

4
SEATING PLANE-JL J

NOTES:
1. LEADS. TRUE POSITIONED 2. OIM "L" TO CENTER OF
WITHIN 0.25 mm (0.010) OIA.
LEADS WHEN FORMEO
AT SEATING PLANE,AT
PARALLEL.
MAXIMUM MATERIAL
3. DIM "A" & "B" INCLUDES
CONOITION.
MENISCUS.

11-4

J

PACKAGE DIMENSIONS (Continued)
- - - - - - - - 2 0 · P I N PACKAGE-------PLASTIC PACKAGE
CASE 738-02

NOTES:
1. OIMW IS DATUM.
2. POSITIONAL TOL FOR LEADS;

1.1.0 0.25 (O.01O)@jT IAeJ
3. IT] IS SEATING PLANE.
4. DIM "B" DOES NOT INCLUDE MO LD FLASH.
5. DIM
TO CENTER OF LEADS WHEN
FORMED PARALLEL.
6. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5, 1973.

m

MILLIMETERS
MAX
DIM MIN
A 25.65 27.18
6.10
6.60
B
3.94 4.57
C
0.38 0.56
D
1.27
1.78
F
2.54 Bse
G
J
0.20 I 0.38
K
2.79 I 3.56
L
7.62 Bse
M
15°
0°
N
0.51 I 1.02

INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.155 0.180
0.015 0.022
0.050 0.070
0.100 Bse
0.008~ 0.015
0.110~ 0.140
0.300 Bse
15°
0°
0.020 I 0.040

DIM
A
B
C
D

NOTES:
1. LEADS WITHIN 0.25 mm (0.010)
DIA, TRUE POSITION AT
SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIM L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIM A AND B INCLUDES
MENISCUS.

F
G
H
J
K
L
M

N

PLCC PACKAGE -

SEE PAGE 11-9

11·5

MILLIMETERS
MIN
MAX
23.88 25.15
7.49
6.60
3.81
5.08
0.38
0.56
1.40
1.65
2.54 BSC
0.51 ~ 1.27
0.20 J 0.30
3.18
4.06
7.62 Bse
00
15°
0.25 J 1.02

INCHES
MIN
MAX
0.940 0.990
0.260 0.295
0.150 0.200
0.015 0.022
0.055 0.065
0.100 esc
0.020 0.050
O.OOU 0.012
0.1 fli 0.160
0.300 Bse
00
15°
0.010 ~ 0.040

PACKAGE DIMENSIONS (Continued)
--------24·PIN

PACKAGE---~----

PLASTIC PACKAGE
CASE 709-02
13

24

B

p

12

L

--~
DIM
A
B
C
D

PLANE
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (0),
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION l TO CENTER OF LEADS
WHEN FORMED PARALLEL
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

F
G
H

J
K
L

M
N

MILLIMETERS
MIN
MAX
31.37 32.13
13.72 14.22
3.94
5.08
0.36
0.56
1.52
1.02
2.54 Bse
1.65
2.03
0.20
0.38
2.92 I 3.43
15.24 BSC
15°
0°
0.51 I 1.02

INCHES
MIN
MAX
1.235 1.265
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.080
0.008 0.015
0.115 0.135
0.600 Bse
15°
0°
0.020 0.040

CERAMIC PACKAGE
CASE 623-05

-1
B

~lT~nn~rnOTrn~rn~1~2
A

1

I

___

1

F

(SEATING PLANE

~lttL-~
NJ J ;
'I

i

- G f--

•

-II-D

.

K

_11-

J ,

-.....; _M

NOTES:
1. DIM "L" TO CENTER OF
LEADS WHEN FORMED
PARALLEL.
2. LEADS WITHIN 0.13 mm
(0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL
CONDITION. (WHEN FORMED
PARALLEL).

11-6

MILLIMETERS
DIM MIN
MAX
A 31.24 32.77
B 12.70 15.49
4.06
e
5.59
0.41
0.51
D
F
1.27
1.52
2.54 ase
G
J
0.20
0.30
3.18
K
4.06
15.24 asc
L
00 I 150
M
N
0.51
1.27

INCHES
MIN
MAX
1.290
1.230
0.500 0.610
0.160 0.220
0.016 0.020
0.050 0.060
0.100 ase
0.008 0.012
0.125 0.160
0.600 BSC
150
0°
0.020 0.050

PACKAGE DIMENSIONS (Continued)
- - - - - - - - 28·PIN PACKAGE-------CERAMIC PACKAGE
CASE 733-03

M1LUMETERS
MIN
MAX
36.45
37.85
15.37
12.70
4.06
5.84
0.56
0.38
1.65
1.27
2.54 SSC
0.20 I 0.30
4.06
3.18
15.24 BSC
5'
15'
0.51
1.27

INCHES
MIN
MAX
1.435
1.490
0.500
0.605
0.160
0.230
0.015 0.022
0.050
0.065
0.100 esc
O.OOS
0.012
0.160
0.125
0.600 SSC
5' I 15'
0.020 I 0.050

MILLIMETERS
DIM MIN
MAX
36.45 37.21
A
13.72 14.22
B
3.94
C
5.08
0.36
0.56
D
1.02
F
1.52
2.54 esc
G
H
1.65
2.16
0.20 I 0.38
J
2.92 I 3.43
K
15.24 SSC
L
M
00 I 150
0.51 I 1.02
N

INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 esc
0.065 0.085
0.008 0.015
0.115 0.135
0.600 BSC
00
15 0
0.020 0.040

DIM
NOTES:
1. DIM
IS DATUM.
2. POSITIONAL TOL FOR LEADS:
Itlci> 0.25 (0.010)91 T 1A91
3.
IS SEATING PLANE.
4. DIM A AND B INCLUDES MENISCUS.
5. DIM ·L· TO CENTER OF LEADS WHEN FORMED
PARALLEL.
6. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5,1973.

rn

rn

A

B
C

D
F
G

J
K
L
M
N

PLASTIC PACKAGE
CASE 710-02

PLANE

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN O.25mm(O.OI0) AT
MAXIMUM MATERIAL CDNDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLO FLASH.

11·7

PACKAGE DIMENSIONS (Continued)
- - - - - - - - 40·PIN PACKAGE-------PLASTIC PACKAGE
CASE 711-03

~:::::::::::::::::::I~
NOTES:
1. POSITIONAL TOLERANCE OF LEAOS (0).
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. OIMENSION B DOES NOT INCLUOE
MOLD FLASH.

MILLIMETERS
DIM MIN
MAX
A
51.69 52.45
B 13.72 14.22
3.94
C
5.08
0.56
0.36
D
F
1.02
1.52
2.54 BSC
G
H
1.65
2.16
0.38
J
0.20
2.92
3.43
K
15.24 asc
L
M
0°
15°
0.51
1.02
N

INCHES
MIN
MAX
2.035 2.065
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.G15
0.115 0.135
0.600 BSC
0°
15°
0.020 0.040

CERAMIC PACKAGE
CASE 734-04

MILLIMETERS
MIN
MAX
A
51.31 53.24
B 12.70 15.49
4.06
5.84
C
D
0.38
0.56
F
1.27
1.65
G
2.54 asc
J
0.30
0.20
K
3.18
4.06
15.24 asc
L
M
15°
5°
1.27
N
0.51

DIM
NOTES:
1. DIM A IS OATUM.
2. POSITIONAL TOLERANCE FOR LEAOS:

I

II

@I I @I

till 0.25(0.010)
T A
3.1JJ IS SEATING PLAN E.
4. DIM L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
5. DIMENSIONS A AND a INCLUDE
MENISCUS.
6. DIMENSIONING AND TOLERANCING
PER ANSI YI4.5, 1973.

11·8

INCHES
MIN
MAX
2.020 2.096
0.500 0.610
0.160 0.230
0.015 0.022
0.050 0.065
0.100asc
0.008 0.012
0.125 0.160
0.600 SSC
15°
5°
0.020 0.050

PACKAGE DIMENSIONS (Continued)
--------40·PIN PACKAGE-------PLCC PACKAGE
CASE 777-01
1 i v
o

DIM
A
B

C
NOTES:
1. DIMENSIONS RAND U DO NOT INCLUDE MOLD
FLASH.
2. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.
3. CONTROLLING DIMENSION: INCH

D
E

F
G

H
J
K

R
U

V
W
X

Y

MilliMETERS
MIN
MAX
17.40
17.65
17.40
17.65
4.19
4.57
0.64
1.01
2.16
2.79
0.33
0.53
1.27 esc
0.66
0.81
0.38
0.63
14.99
16.00
16.51
16.66
16.51
16.66
1.07
1.21
1.07
1.21
1.42
1.07
0.00
0.50

INCHES
MIN
MAX
0.685
0.695
0.695
0.685
0.180
0.165
0.040
0.025
0.085
0.110
0.013
0.021
0.050 esc
0.032
0.026
0.015
0.025
0.590
0.630
0.650
0.656
0.650
0.656
0.048
0.042
0.042
0.048
0.042
0.056
0.000
0.020

- - - - - - - - 2 0 · P I N PACKAGE-------PLCC PACKAGE
CASE 775-01

DIM

A
B
C

D
E
F
G
H

J
K

NOTES:
1. DIMENSIONS RAND U DO NOT INCLUDE MOLD
FLASH.
2. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

R
U
V

W
X
Y
AA

3. CONTROLLING DIMENSION' INCH

11-9

•

MILLIMETERS
MIN
MAX
10.02
9.78
9.78
10.02
4.19
4.57
1.01
0.64
2.16
2.79
0.33
0.53
1.27 esc
0.66
0.81
0.13
0.38
7.37
8.38
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.42
1.07
0.00
0.50
2.34
2.11

INCHES
MIN
MAX
0.385
0.395
0.395
0.385
0.165
0.180
0.040
0.025
0.110
0.085
0.021
0.013
0.050 esc
0.032
0.026
0.015
0.005
0.330
0.290
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.056
0.042
0.000
0.020
0.088
0.107

MC145453
ELECTRICAL CHARACTERISTICS 1-4OoCsTA -<85°C, Voltages Referenced to VSS)
Symbol

Test Condition

Parameter

VOO
V

Guaranteed
Limit

Unit

-

3.0 to 10.0

V

VIL

Maximum Low-level Input Voltage
lData, Clock, BP In)

3.0
4.5
10.0

0.4
0.8
0.8

V

VIH

Minimum High-Level Input Voltage
IOata, Clock, BP Inl

3.0
5.5
10.0

2.0
2.0
8.0

V

IOL

Minimum Low-Level Output Current

3.0
3.0

320
20

3.0
3.0

-320
-20

VOO

Power Supply Voltage Range

IOH

~A

V out =0.3 V

IBP Out)
lOut 1 to Out 33)
Minimum High-Level Output Current

~A

V ou t=2.7 V

IBP Out)
lOut 1 to Out 33)
Average OC Output Offset Voltage
IBP Out Relative to Out 1 through Out 33)

BP Out: CL =8750 pF
Out 1 to 33: CL = 250 pF

3.0
10.0

±50
±50

mV

Maximum Input Leakage Current
IOata, Clock, BP In)

Vin = VOO or VSS

10.0

±1.0

~A

100

Maximum Quiescent Supply Current
lper Package)

Osc In: Vin = VSS
BP In, Data, Clock: Vin = VDD or VSS
10ut=0 ~A

10.0

10

~A

Idd

Maximum RMS Operating Supply Current
lper Package)

RX = 1.0 Mil, Cx =470 pF
BP Out Tied to BP In
Clock, Data: Vin = VDD or VSS
10ut=0 ~

10.0

40

~

VOO
V

Guaranteed
Limit

Unit

Maximum Clock Frequency 150% Duty Cycle)
(Figure 1)

3.0
4.5
10.0

400
850
1800

kHz

tsu

Minimum Setup Time, Data to Clock
IFigure 1)

3.0
4.5
10.0

300
180
100

ns

th

Minimum Hold Time, Clock to Data
IFigure 1)

3.0
4.5
10.0

300
130
50

ns

tw

Minimum Pulse Width, Clock
IFigure 1)

3.0
4.5
10.0

1250
585
275

ns

Maximum Input Rise and Fall Times. Clock
IFigure 1)

3.0
4.5
10.0

300

ns

-

10

VOO
lin

AC ELECTRICAL CHARACTERISTICS 1-4OoC-

>

I
VDD
BP IN

BACKPLANE

BP OUT

OSC IN

470 pf-'-

LCD

T-=

MC145453

CMOS
OR
NMOS
MPU/MCU

00' , '"0'""" ,m , )

fRONTPLANES

DATA

CLOCK

Vss

1

1
Figure 3. Using On-Chip Oscillator

+V
50% DUTY CYCLE
EXTERNAL
fREQUENCY
SOURCE
2X BACKPLANE
fREQUENCY

MCl4013B
+2

li

BP OUT

NC

OSC IN

+V

LCD
MC145453

CMOS
OR
NMOS
MPU/MCU

OUT 1 THROUGH OUT 33

I - - - - - - - - - - - - - - - . - t DATA
t---------------+fCLOCK
VSS

=
Figure 4. Converting External Backplane Frequency Source
to 50% Duty Cycle

Continuation of data sheet MC145453 page 5

fRDNTPLANES

MC145453

APPLICATIONS INFORMATION (CONT'DI

+V

+v

Hz' --...._......-t
Q13I---'1.::.22::....c:
MC14020B
-78192

VSS

CMOS
OR
NMOS
MPUIMCU

MCl45453

1--------------......-tDATA

f-----------------.j CLOCK

VSS

Figure 5. Using low-Cost Divider to Sync Backplane Frequency

BP IN

BP OUT

1

BACKPLANE

" V

~

MCl45453

~

00' , ,"""om 00' " : )

~ DSC IN

FRONTPlANES

I-BP IN

BP OUT r---NC

LCD

.r-

MC145453

OSC IN

""' ,,~"~ ""'"

:)

FRONTPlANES

BP IN

I
I
I
I

BP OUT r---NC

MCl45453
OUT 1 THROUGH OUT 33
r-0SCIN

~

FRONT PLANES

I

I

Figure 6. Paralleling Devices to Increase Number of Driven Segments

Continuation of data sheet MC145453 page 6

•
•
•
•
•
•
•
•
•

II
II

Master Index
Handling and Design Guidelines
CMOS ADCs/DACs
CMOS Decoders/Display Drivers
CMOS Operational Amplifiers/Comparators
CMOS/NMOS PLLs/Frequency Synthesizers
CMOS Remote Control Functions
CMOS Smoke Detectors
Miscellaneous Functions
Reliability
Package Dimensions

Al6682-6
3/89



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