1988_Motorola_Memory_Data 1988 Motorola Memory Data

User Manual: 1988_Motorola_Memory_Data

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Selector Guide and Cross Reference . .
MOS Dynamic RAMs

II

General MOS Static RAMs . .
CMOS Fast Static RAMs.

II
MOS EEPROMs II

Special Application MOS Static RAMs

MECL RAMs.
MECL PROMs
Military Products
Reliability Information
Applications Information
Mechanical Data
MOTOROLA MEMORY DATA

II
II

iii
III
lEI

DATA CLASSIFICATION
Product Preview
This heading on a data sheet indicates that the device is in the formative
stages or in design (under development). The disclaimer at the bottom of
the first page reads: "This document contains information on a product
under development. Motorola reserves the right to change or discontinue
this product without notice."

Advance Information
This heading on a data sheet indicates that the device is in sampling,
preproduction, or first production stages. The disclaimer at the bottom of
the first page reads: 'This document contains information on a new product.
Specifications and information herein are subject to change without notice."

Fully Released
A fully released data sheet contains neither a classification heading nor a
disclaimer at the bottom of the first page. This document contains information on a product in full production. Guaranteed limits will not be changed
without written notice to your local Motorola Semiconductor Sales Office,

MOTOROLA
MEMORIES
Prepared by
Technical Information Center

Motorola has developed a broad range of reliable memories for
virtually any digital data processing system application. Complete
specifications for the individual circuits are provided in the form
of data sheets. In addition, a selector guide is included to simplify
the task of choosing the best combination of circuits for optimum
system architecture.
The information in this book has been carefully checked; no
responsibility, however, is assumed for inaccuracies. Furthermore, this information does not convey to the purchaser of microelectronic devices any license under the patent rights of the
manufacturer.

New Motorola memories are being introduced continually. For the latest releases, and additional technical information or pricing, contact your nearest authorized
Motorola distributor or Motorola sales office.

Series E
©MOTOROLA INC., 1988
Previous Edition © 1984
••All Rights Reserved"

Printed in U.S.A.

iii

MECL, MECL 10K, and MECL 10KH are trademarks of Motorola Inc.

MOTOROLA MEMORY DATA
iv

CONTENTS
Page
Alphanumeric Index ........................................................

ix

CHAPTER 1
Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
Cross Reference ......................................................... 1-5
CHAPTER 2-MOS DYNAMIC RAMs
MCM62568
256Kx 1,100/120/150 ns, Page Mode .......................
MCM62578
256Kx1, 100/120/150 ns, Nibble Mode ......................
64K x 4, 100/120/150 ns, Page Mode ........................
MCM41464A
MCM511000
1M x 1,85/100/120 ns, Page Mode ..........................
MCM511001
1Mx1, 85/100/120 ns, Nibble Mode ........................
MCM511002
1M x 1,85/100/120 ns, Static Column .......................
MCM514256
256K x 4, 85/100/120 ns, Fast Page Mode ....................
MCM514258
256K x 4, 85/100/120 ns, Static Column .....................

2-3
2-15
2-27
2-39
2-53
2-67
2-81
2-95

CHAPTER 3-GENERAL MOS STATIC RAMs
MCM2016H
2K x 8, 45/55/70 ns, NMOS ................................
MCM2018
2K x 8, 35/45 ns, NMOS ...................................
MCM6064,
8Kx8, 100/120/150 ns, CMOS .............................
MCM60L64
8K x 8, 100/120/150 ns, CMOS, Lower Power •...............
MCM60256,
32Kx8, 85/100/120 ns, CMOS .............................
MCM60L256 32Kx8, 85/100/120 ns, CMOS, Lower Power ................

3-3
3-8
3-13
3-13
3-19
3-19

CHAPTER 4-CMOS FAST STATIC RAMs
MCM1423
4K x 4, 40 ns, Equivalent to IMS1423 ........................ 4-3
MCM6164,
8K x 8, 45/55 ns, E1, E2, and G Inputs. . . . . . . . . . . . . . . . . . . . . .. 4-8
MCM61 L64
8K x 8, 45/55 ns, Lower Power ............................. 4-8
MCM6164C
8K x 8,55/70 ns, -40 to 85°C .............................. 4-16
MCM6168
4K x 4, 45/55/70 ns ....................................... 4-24
MCM6206
32K x 8, 45/55/70 ns, Output Enable ........................ 4-29
MCM6207
256K x 1, 25/35 ns, Separate Input and Output Pins ........... 4-34
MCM6208
64K x 4, 25/35 ns ......................................... 4-39
MCM6264
8K x 8,35/45 ns, 300-mil PDIP .............................. 4-44
MCM6268
4K x 4, 25/35 ns .......................................... 4-49
MCM6269
4K x 4, 25/35 ns, Fast Chip Select ........................... ·4-54
MCM6287
64K x 1, 25/35 ns, Separate Input and Output Pins ............ 4-59
MCM6288
16K x 4, 25/30/35 ns ...................................... 4-68
MCM6290
16K x 4, 25/30/35 ns, Output Enable ........................ 4-76

MOTOROLA MEMORY DATA
v

CONTENTS (Continued)
Page
CHAPTER 5-SPECIAL APPLICATION MOS STATIC RAMs
MCM68HC34
Dual-Port RAM ...........................................
MCM41SO
4Kx4, 22/25/30 ns, Cache Tag .............................
MCM6292
16K x 4, 25/30/35 ns, Synchronous, Transparent Outputs ......
MCM6293
16K x 4, 25/30/35 ns, Synchronous, Output Registers .........
MCM6294
16K x 4, 25/30/35 ns, Synchronous, Output Registers and Output
Enable .................................................
MCM6295
16K x 4, 25/30/35 ns, Synchronous, Transparent Outputs and
Output Enable ..........................................
MCM62350
4K x 4, 25/30/35 ns, Cache Tag ............................
MCM62351
4K x 4, 25/30/35 ns, Cache Tag ...................... . . . . . ..

5-3
5-11
5-12
5-20
5-28
5-36
5-44
5-45

CHAPTER 6'"- MOS EEPROMs
MCM2S01
16 x 16 ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
MCM2802
32 x 32 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-8
MCM2814
256x8 ................................................... 6-13
CHAPTER 7-MECL RAMs
MC10Hl45
16 x 4 Register File, 6 ns ...................................
MCM10143
8x2 Multiport Register File, 15.3 ns .........................
MCM10144
256 x 1,26 ns .............................................
MCM10145
16x4 Register File, 15 ns ..................................
MCM10146
1024 x 1, 29 ns ............................................
MCM10147
128x 1, 15 ns .............................. : ..............
MCM10148
64x1, 15 ns ..............................................
MCM10152
256 x 1, 15 ns .............................................
MCM10415
1024 x 1,15/20 ns .........................................

7-3
7-6
7-10
7-14
7-18
7-22
7-26
7-28
7-32

CHAPTER 8- MECL PROMs ,
MCM10139
32 x 8,20 ns .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-3
MCM10149*10 256x4, 10 ns ...................... ; ...................... 8-8
MCM10149*25 256x4, 25 ns ............................................. 8-12
CHAPTER 9- MILITARY PRODUCTS
Military 6164
8K x 8 SRAM, 55/70 ns ....................................
Military 6168
4K x 4 SRAM, 55/70 ns .............. . . . . . • . . . . . . . . . . . . . . ..
Military 6268
4Kx4 SRAM, 35/45 ns ....................................
Military 6287
64Kx 1 SRAM, 35/45 ns ...................................
Military 6288
16K x 4 SRAM, 3,5/45 ns ...................................

9-3
9-8
9-13
9-18
9-23

CHAPTER 10-RELIABILITY INFORMATION ............................... 10-1

MOTOROLA MEMORY DATA
vi

CONTENTS (Continued)
Page
CHAPTER 11-APPLICATIONS INFORMATION
DRAMs
DRAM Refresh Modes (AN987) ........................................
Page, Nibble, and Static Column Modes: High-Speed, Serial-Access Options
on 1M-Bit+ DRAMs (AN986) ........................................
Fast Static RAMs
Avoiding Bus Contention in Fast Access RAM Designs (AN971) ............
Avoiding Data Errors with Fast Static RAMs (AN973) .....................
Special Application Static RAMs
25 MHz Logical Cache for an MC68020 (AN984) .........................
High Frequency System Operation Using Synchronous SRAMs (AR258) ....
Motorola's Radical SRAM Design Speeds Systems 40% (AR256) ..........

11-2
11-4
11-8
11-12
11-15
11-29
11-36

CHAPTER 12-MECHANICAL DATA ....................................... 12-1

MOTOROLA MEMORY DATA
vii

MOTOROLA MEMORY DATA
viii

ALPHANUMERIC INDEX
Device
Number
MCM10139
MCM10143
MCM10144
MCM10145
MCM10146
MCM10147
MCM10148
MCM10149*1O
MCM10149*25
MCM10152
MCM10415
MCM1423
MCM2016H
MCM2018
MCM2801
MCM2802
MCM2814
MCM41464A
MCM4180
MCM511000
MCM511001
MCM511002
MCM514256
MCM514258
MCM60L256
MCM60L64
MCM60256
MCM6064
MCM61L64
MCM6164
MCM6164C
MCM6168
MCM6206
MCM6207
MCM6208
MCM62350
MCM62351

Function
32 x 8 MECL PROM, 20 ns ...............................
8 x 2 MECL Multiport Register File, 15.3 ns .................
256 x 1 MECL RAM, 26 ns ...............................
16x4 MECL Register File, 15 ns ..........................
1024 x 1 MECL RAM, 29 ns ..............................
128 x 1 MECL RAM, 15 ns ...............................
64x 1 MECL RAM, 15 ns ................................
256x4 MECL PROM, 10 ns ..............................
256 x 4 MECL PROM, 25 ns ..............................
256 x 1 MECL RAM, 15 ns ...............................
1024 x 1 MECL RAM, 15/20 ns ...........................
4K x 4 CMOS SRAM, 40 ns, Equivalent to IMS1423 .........
2K x 8 NMOS SRAM, 45/55/70 ns ........................
2K x 8 NMOS SRAM, 35/45 ns ...........................
16 x 16 NMOS EEPROM .................................
32 x 32 NMOS EEPROM .................................
256 x 8 CMOS EEPROM .................................
64Kx4 NMOS DRAM, 100/120/150 ns, Page Mode.........
4K x 4 CMOS SRAM, 22/25/30 ns, Cache Tag . . . . . . . . . . . . . .
1M x 1 CMOS DRAM, 85/100/120 ns, Page Mode ..........
1M x 1 CMOS DRAM, 85/100/120 ns, Nibble Mode .........
1M x 1 CMOS DRAM, 85/100/120 ns, Static Column........
256Kx4 CMOS DRAM, 85/100/120 ns, Fast Page Mode.....
256K x 4 CMOS DRAM, 85/100/120 ns, Static Column ......
32Kx8 CMOS SRAM, 85/100/120 ns, Lower Power........
8K x 8 CMOS SRAM, 100/120/150 ns, Lower Power ........
32Kx8 CMOS SRAM, 85/100/120 ns .....................
8Kx8 CMOS SRAM, 100/120/150 ns .....................
8K x 8 CMOS SRAM, 45/55 ns, Lower Power ..............
8K x 8 CMOS SRAM, 45/55 ns, E1, E2, and G Inputs. . . . . . . .
8K x 8 CMOS SRAM, 55/70 ns, - 40 to 85°C ...... :.......
4K x 4 CMOS SRAM, 45/55/70 ns ........................
32K x 8 CMOS SRAM, 45/55/70 ns, Output Enable .........
256K x 1 CMOS SRAM, 25/35 ns, Separate Input and
Output Pins ......................................... .
64K x 4 CMOS SRAM, 25/35 ns ..........................
4K x 4 CMOS SRAM, 25/30/35 ns, Cache Tag .............
4K x 4 CMOS SRAM, 25/30/35 ns, Cache Tag. . . . . . . . . . . . . .

MOTOROLA MEMORY DATA
ix

Page
Number
8-3
7-6
7-10
7-14
7-18
7-22
7-26
8-8
8-12
7-28
7-32
4-3
3-3
3-8
6-3
6-8
6-13
2-27
5-11
2-39
2-53
2-67
2-81
2-95
3-19
3-13
3-19
3-13
4-8
4-8
4-16
4-24
4-29
4-34
4-39
5-44
5-45

ALPHANUMERIC INDEX (Continued)
Device
Number
MCM6256B
MCM6257B
MCM6264
MCM6268
MCM6269
MCM6287
MCM6288
MCM6290
MCM6292
MCM6293
MCM6294
MCM6295
MCM68HC34
MC10H145
Military 6164
Military 6168
Military 6268
Military 6287
Military 6288

Function
256K x 1 NMOS DRAM, 100/120/150 ns, Page Mode. . . . . . . .
256K x 1 NMOS DRAM, 100/120/150 ns, Nibble Mode ......
8K x 8 CMOS SRAM, 35/45 ns, 300-mil PDIP . . . . . . . . . . . .. . .
4K x 4 CMOS SRAM, 25/35 ns ...........................
4K x 4 CMOS SRAM, 25/35 ns, Fast Chip Select ...........
64K x 1 CMOS SRAM, 25/35 ns, Separate Input and
Output Pins ......................................... .
16K x 4 CMOS SRAM, 25/30/35 ns .......................
16Kx4 CMOS SRAM, 25/30/35 ns, Output Enable.........
16K x 4 CMOS SRAM, 25/30/35 ns, Synchronous, Transparent
Outputs ............................................. .
16K x 4 CMOS SRAM, 25/30/35 ns, Synchronous, Output
Registers ............................................ .
16K x 4 CMOS SRAM, 25/30/35 ns, Synchronous, Output
Registers and Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16K x 4 CMOS SRAM, 25/30/35 ns, Synchronous, Transparent
Outputs and Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS Dual-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 x 4 MECL Register File, 6 ns ...........................
8K x 8 CMOS SRAM, 55/70 ns ...........................
4K x 4 CMOS SRAM, 55/70 ns ...........................
4Kx4 CMOS SRAM, 35/45 ns ...........................
64K x 1 CMOS SRAM, 35/45 ns ..........................
16Kx4 CMOS SRAM, 35/45 ns ..........................

MOTOROLA MEMORY DATA
x

Page
Number
2-3
2-15
4-44
4-49
4-54
4-59
4-68
4-76
5-12
5-20

5-28
5-36
5-3
7-3
9-3
9-8
9-13
9-18
9-23

Selector Guide and Cross Reference . .
,.
I

Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
Cross Reference ......................... 1-5

MOTOROLA MEMORY DATA
1-1

a

SELECTOR GUIDE
MOS/CMOS

CMOS Static RAMs
( + 5 V 0 to 70°C unless otherwise noted)

.

MOS Dynamic RAMs
( + 5 V 0 to 70°C)

Access Time
(ns max)

Pins

MCM1423P45
IMS1423P-45

40
40

20
20

18
18
18

MCM6168P45
MCM6168P55
MCM6168P70

45
55
70

20
20
20

100
120
150

16
16
16

MCM6268P25
MCM6268P35

25
35

20
20

(NI
INI
INI

100
120
150

16
16
16

25
35

20
20

MCM514256PB5
MCM514256P10
MCM514256P12

(PI
(PI
(PI

B5
100
120

20
20
20

MCM6064P10
MCM6064P12
MCM6064P15

100
120
150

28
28
28

MCM514256J85
MCM514256J10
MCM514256J12

(PI
(PI
(PI

B5
100
120

20/26
20/26
20/26

MCM60L64PlO
MCM60L64P12
MCM60L64P15

100
120
150

28
28
28

MCM6164C45
MCM6164C55

45
55

28
28

MCM51425BPB5
MCM51425BP10
MCM51425BP12

151
(51
(51

85
100
120

20
20
20

MCM61 L64C45
MCM61 L64C55

45
55

28
28

MCM514258JB5
MCM514258J10
MCM514258J12

(51
(51
(51

85
100
120

20/26
20/26
20/26

MCM6164P45*
MCM6164P55*

45
55

28
28

MCM61 L64P45*
MCM61L64P55*

45
55

28
28

MCM511000PB5
MCM511000P10
MCM511000P12

IPI
(PI
(PI

85
100
120

18
18
18

MCM6164J45*
MCM6164J55*

45
55

28
28

MCM511000JB5
MCM511000J10
MCM511000J12

(PI
(PI
IPI

85
100
120

20/26
20/26
20/26

MCM61L64J45*
MCM61 L64J55*

45
55

28
28

55
70

28

MCM511001P85
MCM511001P10
MCM511001P12

(NI
(NI
(NI

B5
100
120

18
18
18

MCM6264P35*
MCM6264P45*

35
45

28
28

MCM511001JB5
MCM511001J10
MCM511001J12

(NI
(NI
(NI

85
100
120

20/26
20/26
20/26

MCM6264J35*
MCM6264J45*

35
45

28
28

85
100
120

18
18
18

MCM6288P25
MCM6268P30
MCM6268P35

25

(51
(51
(51

30

MCM511002P85
MCM511002P10
MCM511002P12
MCM511002JB5
MCM511002J10
MCM511002J12

(51
(51
(51

85
100
120

20/26
20/26
20/26

Access Time
(ns max)

Pins

MCM41464AP10 (PI
MCM41464AP12 (PI
MCM41464AP15 (PI
(PI
MCM6256BP10
(PI
MCM6256BP12
(PI
MCM6256BP15

100
120
150

MCM6257BP10
MCM6257BP12
MCM6257BP15

Organization
64Kx4

256Kx 1

256Kx4

1Mx1

Organization

Part Number

4Kx4

Part Number

MCM6269P25*
MCM6269P35
8Kx8

MCM6164CC55
MCM6164CC70

16Kx4

(P) Page Mode
(N) Nibble Mode
(5) Static Column

64Kx 1

MOS Static RAMs

(21
(21

(31
(31

35

22
22
22

MCM6290P25*
MCM6290P3O*
MCM6290P35*

(41
(41
(41

25
30
35

24
24
24

MCM6290J25*
MCM629OJ30*
MCM6290J35*

(41
(41
(41

25
30
35

24
24
24

MCM6287P25
MCM6287P35

25
35

22
22

MCM6287J25
MCM6287J35

25
35

24
24

(+5 V. 0 to 70°C)
Organization
2Kx8

28

(Continued)
Part Number

Access Time
(ns max)

Pins

MCM2016HN45
MCM2016HN55
MCM2016HN70

(11
(11
(11

45
55
70

24
24
24

MCM2018N35
MCM2018N45

(11
(11

35
45

24
24

*To be introduced
(1) 300 mil package
(2) Chip select version
(3) Industrial temperature range, - 40 to 85°C
(4) Output enable version

MOTOROLA MEMORY DATA
1-2

SELECTOR GUIDE
CMOS Static RAMs (Continued)
Organization

32Kx8

64Kx4

256Kx 1

Part Number

Access Time

(ns max!

85

Synchronous Static RAMs

MCM60256P85
MCM60256P10
MCM60256P12
MCM60L256P85
MCM60L256P10
MCM60L256P12

100
120

28
28
28
28
28
28

MCM6206P45*
MCM6206P56*
MCM6206P70*
MCM6206J45*
MCM6206J55*
MCM6206J70*

45
56
70
45
55
70

28
28
28
28
28
28

MCM6208P25*
MCM6208P35*

24
24

MCM6208L25*
MCM6208L35*
MCM6208J25*
MCM6208J35*

25
35
25
35
25
35

MCM6207P25*
MCM6207P35*

25
35

24
24

MCM6207l25*
MCM6207L35*
MCM6207J25*
MCM6207J35*

25
35
25
35

24
24
24
24

100
120

85

(+ 5 V, 0 to 700 e unless otherwise noted)

Pins

Organization
16Kx4

24
24
24
24

Part Number

Access Time
(ns max!

Pins

MCM6292C25
MCM6292C30
MCM6292C35
MCM6292J25
MCM6292J30
MCM6292J35

25
30
35
25
30
35

28
28
28

MCM6293P25
MCM6293P30
MCM6293P35
MCM6293J25
MCM6293J30
MCM6293J35

25
30
35
25
30
35

28
28
28
28
28
28

MCM6294P25
MCM6294P30
MCM6294P35
MCM6294J25
MCM6294J30
MCM6294J35

25
30
35
25
30
35

28
28
28

MCM6295C25
MCM6295C30
MCM6295C35
MCM6295J25
MCM6295J30
MCM6295J35

25
30
35
25
30
35

28
28
28
28
28
28

28
28
28

28
28
28

Cache Tag RAMs
(+5 V, 0 to 70 0 e unless otherwise noted)
Organization

4Kx4

MOS Dual Port RAM
(+5 V, 0 to 70 0 e)

Address to
Match Time
(ns max!

Pins

MCM6235OJ22
MCM6235OJ25
MCM6235OJ30

22
25
30
22
25
30

24
24
24
24
24
24

MCM62351P22
MCM62351 P25
MCM62351P30

22
25
30

24
24
24

Organization
16x16
32x32
256x8

Part Number
MCM62350P22
MCM62350P25
MCM62350P30

MCM62351J22
MCM62351J25
MCM62351J30

22
25
30

24
24
24

MCM4180P22
MCM4180P25
MCM4180P30

22
25
30

22
22
22

Organization

Part Number

Access Time
(ns max!

Pins

256x8

MCM68HC34L
MCM68HC34P

240
240

40
40

Part Number

Access Time
(,...!

Pins

MCM2801P
MCM2802P
MCM2814P

1
1,3
3.5

14
14
8

MOS EEPROMs
(+5 V, 0 to 70 0 e)

MOTOROLA MEMORY DATA
1-3

•

SELECTOR GUIDE
MECL

MILITARY PRODUCTS
CMOS Static RAMs

RAMs

(+5 V, -55 to 125°C)

(0 to 75°C)
Organization
8x2
16x4
16x4
64x 1
128x1
256 x 1
256 x 1
1024 x 1
1024 x 1
1024 x 1

Part Number
MCM10143
MCM10145
MC10Hl45
MCM10148
MCM10147
MCM10144
MCM10152
MCM10148
MCM10415-15
MCM10415-2O

Access Time
Ins max)
15.3
15
6
15
15
26
15

29
15

20

Pins

Organization

24
16
16
16
16
16
16
16
16
16

4Kx4

PROMs
8Kx8

(0 to 75°C)
Organization
32x8
256x4
256 x 4

Part Number
MCM10139
MCM10149-10
MCM10149-25

Access Time
Ins maxI
20
10

25

Access Time
Ins maxI

Pins

6168-55/BRAJC
6168-55/BYAJC
6168-55/BUAJC

55
55
55

20
20
20

6168-70/BRAJC
6168-70/BYAJC
6168-70/BUAJC

70
70
70

20

6268-351 BRAJC
6268-351 BYAJC
6268-351 BUAJC
6268-451 BRAJC
6268-451 BYAJC
6268451 BUAJC

35

20

6164-55/BXAJC

Part Number

6164-551 BUAJC
Pins

6164-70/BXAJC

6164-701 BUAJC
16
16
16

16Kx4

MOTOROLA MEMORY DATA
1-4

35

20

35

20

45
45
45

20
20
20

55
55

32

70
70

28
32

28

6288-35/BXAJC

35

6288-351 BUAJC

35

22
22

6268-45/BXAJC

45
45

22
22

35

35

22
22

45
45

22
22

6288-451 BUAJC
64Kx 1

20
20

6287-351 BXAJ C
6287-351 BUAJC
6287-451 BXAJ C
6287-451 BUAJC

CROSS REFERENCE
The part numbers in the first column are arranged in alphanumeric sequence. The "Motorola
Part Number" denotes what is believed to be the functional equivalent by pin function, except
for differences in select! enable functions.
NOTE: The user must verify speed, power, and package interchangeability based on detailed
specifications.
Motorola does not assume any liability arising out of the application or use of any product
listed.

MOS Dynamic RAM Cross Reference
Competition
Part
Number

Motorola
Part Number

MOS DRAMs (Continued)
Competition
Part

Organization

Motorola
Part Number

Number

Organization

AM90C255
AM90C256
AM90C257
HM504M
HM511000

MCM6256B
MCM6256B
MCM6257B
MCM41464
MCM511000

256K xl
256Kx 1
256Kx 1
64Kx4
lMxl

TC511000
TC511001
TC511002
TMM41256
TMM41464

MCM511000
MCM511001
MCM511002
MCM6256B
MCM41464

lMxl
lMxl
lMxl
256K x 1
64Kx4

HM511001
HM511002
HM51256
HM51256L
HY51Cl00

MCM511001
MCM511002
MCM6256B
MCM6256B
MCM511000

lMxl
lMxl
256K xl
256K xl
lMxl

TMS4256
TMS4257
TMS4Cl024
TMS4Cl025
TMS4Cl027

MCM6256B
MCM6257B
MCM511000
MCM511001
MCM511002

256K xl
256K xl
lMxl
lMxl
lMxl

HY51C256
HY51C464
HY51256L
HY51464
KM41256

MCM6256B
MCM41464
MCM6256B
MCM41464
MCM6256B

256K xl
64Kx4
256K xl
64Kx4
256K xl

TMS44C256
TMS44C257
TMS4464

MCM514256
MCM514258
MCM41464
MCM6256B
MCM6257B

256Kx4
256K x4
64Kx4
256Kx 1
256Kx 1

KM41257
LH21256
LH21257
LH2464
LH2465

MCM6257B
MCM6256B
MCM6257B
MCM41464
MCM41464

256K x 1
256Kx 1
256K xl
64Kx4
64Kx4

~PD41464

MCM41464
MCM511000
MCM511001
MCM511002

64Kx4
lMxl
lMxl
lMxl

LH64256
LH65257
M41256N
M41256P
M441024K

MCM514256
MCM514258
MCM6256B
MCM6256B
MCM514256

256K x4
256Kx4
256Kx 1
256Kx 1
256K x4

M441024P
M5M4Cl000
M5M4Cl001
M5M4Cl002
M5M44C256

MCM514256
MCM511000
MCM511001
MCM511002
MCM514256

256Kx4
lMxl
lMxl
lMxl
256Kx4

M5M44C258
M5M4464
MBS1256
MBS1257
MBSl464

MCM514258
MCM41464
MCM6256B
MCM6257B
MCM41464

MN41256
MSM41000
MSM41001
MSM41004
MSM41005
MSM41256
MSM41257A
MSM41464
MT1256'
MT4064

~PD41256
~PD41257

~PD421000
~PD421001

~PD421002

MOS Static RAM Cross Reference
Part

Motorola
Part Number

Organization

Am2168
Am2169
Am91L14
Am91L24
Am9114

MCMl423!6168!6268/IMSl423
MCM6269
MCM2114/21L14
MCM2114/21L14
MCM2114/21L14

4Kx4
4Kx4
lKx4
lKx4
lKx4

256K x4
64Kx4
256Kx 1
256Kx 1
64Kx4

Am9124
Am9128
Am99Cl64
Am99C165
Am99C641

MCM2114/21L14
MCM2016H
MCM6288
MCM6290
MCM62B7

lKx4
2KxS
16Kx4
16Kx4
64Kx 1

MCM6256B
MCM511000
MCM511001
MCM514256
MCM514258

256K x 1
lMxl
lMxl
256Kx4
256Kx4

Am99C68
Am99C88
Am99C88
Am99C88L
Am99L68

MCMl423/6168/6268/IMSl423
MCM6164/61L64
MCM6064/60L64
MCM6164/61L64
MCMl423/6168/6268/IMSl423

4Kx4
SKxS
SKxS
SKxS
4Kx4

MCM6256B
MCM6257B
MCM41464
MCM6256B
MCM41464

256Kx 1
256Kx 1
64Kx4
256Kx 1
64Kx4

CDM62256
CDM6264
CXK5464
CXK5814
CXK5864

M CM60256/60L256
MCM6164/61L64/6064/60L64
MCM6288
MCM2016H
MCM6164/61 L64

32Kx8
8KxS
16Kx4
2Kx8
8Kx8

Number

Continued

MOTOROLA MEMORY DATA
1-5

•

CROSS REFERENCE
MOS SRAMs (Continued)
Pan
Number

Motorola
Pan Number

Organization

Motorola
Pan Number

CY7Cl28
CY7Cl64
CY7Cl66
CY7Cl68
CY7Cl69

MCM2016H
MCM6288
MCM6290
MCMI4Z3/6168/6268/IMSI4Z3
MCM6269

2Kx8
16Kx4
16Kx4
4Kx4
4Kx4

Organization

IMS1421
IMS1423
IMSl600
IMSl601
IMSl820

MCM6269
MCM1423/6168/6268/IMSI423
MCM6287
MCM6287
MCM6288

4Kx4
4Kx4
64Kxl
64Kxl
16Kx4

CY7Cl85
CYC7186
CY7Cl87
Fl600
Fl620/Fl821

MCM6164/61L64
MCM6164/61L64
MCM6287
MCM6287
MCM6288

8Kx8
8Kx8
64Kxl
64Kx 1
16Kx4

IMSl824
IMSl630
KM8264
LH5114
M2114

MCM6290
MCM6164/61 L64
MCM6064
MCM2114/21L14
MCM2114/21L14

16Kx4
8Kx8
8Kx8
lKx4
lKx4

Fl822
GM76C88
HM4334
HM4334L
HM472114

MCM6290
MCM6064/60L64
MCM2114/21L 14
MCM2114/21L14
MCM2114/21 L14

16Kx4
8Kx8
lKx4
lKx4
lKx4

M2114L
MB81C68
MB81C68A
MB81C68W
MB81C69A

MCM2114/21L14
MCMI423/6168/6268/IMS1423
MCM6268
MCMI423/6168/6268/IMSl423
MCM6269

lKx4
4Kx4
4Kx4
4Kx4
4Kx4

HM472114A
HM6168H
HM6168HL
HM82256
HM8264

MCM2114/21L 14
MCMl4Z3/6168/6268/IMSI423
MCMI423/6168/6268/IMSI423
MCM60256/60L256
MCM6164/61L64/6064

lKx4
4Kx4
4Kx4
32Kx8
8Kx8

MB81C71
MB81C74
MB81C78
MB8114
MB8128

MCM6287
MCM6288
MCM6164/61L64
MCM2114/21 L14
MCM2016H

64Kx 1
16Kx4
8Kx8
lKx4
2Kx8

HM8264L
HM8268
HM8268L
HM6287
HM8287L

MCM6164/61L64/60L64
MCMI423/6168/6268/IMSI423
MCMI423/6168/6268/IMSI423
MCM6287
MCM6287

8Kx8
4Kx4
4Kx4
64Kx 1
64Kxl

MB8168
MB8171
MB6416A
MB6416A-L
MBB417A

MCMI423/6168/8268/IMSI423
MCM6287
MCM2016H
MCM2016H
MCM2016H

4Kx4
64Kxl
2Kx8
2Kx8
2Kx8

HM-6614
HM-6616
HM-66182
HM-65172
HM65681

MCM2114/21L14
MCM2016H
MCM2016H
MCM2016H
MCMI423/6168/6288/IMSI423

lKx4
2Kx8
2Kx8
2Kx8
4Kx4

MBB417A-L
MBB418A
MBB418A-L
MBB4256
MBB464

MCM2016H
MCM2016H
MCM2016H
MCM60256
MCM6164/61L64/6064/60L64

2Kx8
2Kx8
2Kx8
32Kx8
8Kx8

HM65768
HM6788
HM8832
HY2116
HY61C16

MCMI423/6168/6268/IMSI423
MCM6288
MCM60256
MCM2016H
MCM2016H

4Kx4
16Kx4
32Kx8
2Kx8
2Kx8

MBB464-L
MK41H68
MK41H69
MK4802
MM2114

MCM6164/61L64/60L64
MCM1423/6168/6268/IMSI423
MCM6269
MCM2016H
MCM2114/21 L14

8Kx8
4Kx4
4Kx4
2Kx8
lKx4

HY61C68
HY61C68L
HY6116
HY82C64
HY82C87

MCMI423/6168/6268/IMSI423
MCMI423/6168/6268/IMSI423
MCM2016H
MCM6164/61L64
MCM6287

4Kx4
4Kx4
2Kx8
8Kx8
64Kxl

MM2114L
MSM2114L
MSM2128
MSM5114
MSM5115

MCM2114/21 L14
MCM2114/21 L14
MCM2016H
MCM2114/21L14
MCM2114/21L14

lKx4
lKx4
2Kx8
lKx4
lKx4

HY82C88
IDT6116L
IDT6116S
IDT6168L
IDT6168LA

MCM6288
MCM2016H
MCM2016H
MCMI423/6168/IMSI423
MCM6268

16Kx4
2Kx8
2Kx8
4Kx4
4Kx4

MSM5128
MSM5165
MSM5165L
MWS5114
M5M2168

MCM2016H
MCM6164/61L64/6064/60L64
MCM6164/61L64/6064/60L64
MCM2114/21 L14
MCM1423/6168/6268/IMS1423

2Kx8
8Kx8
8Kx8
lKx4
4Kx4

IDT6168S
IDT6168SA
IDT71256L
IDT71256S
IDT7164L

MCMI423/6168/IMSI423
MCM6268
MCM60L256
MCM60256
MCM61L64/60L64

4Kx4
4Kx4
32Kx8
32Kx8
8Kx8

M5M5116
M5M5117
M5M5118
M5M5165
M5M5165-L

MCM2016H
MCM2016H
MCM2016H
MCM6164/61L64
MCM6164/61L64

2Kx8
2Kx8
2Kx8
8Kx8
8Kx8

IDT7164S
IDT7187L
IDT7187S
1DT7188L
IDT7188S

MCM6164/6064
MCM6287
MCM6287
MCM6288
MCM6288

8Kx8
64Kx 1
64Kxl
16Kx4
16Kx4

M5M5187
M5M5188
M58981
NMC2114A
NMC2114AP

MCM6287
MCM6288
MCM2114/21 L14
MCM2114/21 L14
MCM2114/21 L14

64Kxl
16Kx4
lKx4
lKx4
lKx4

IDT7198L
IDT7198S
IDTBM864L
IMS1420
IMSl420L

MCM6290
MCM6290
MCM60L64
MCMI423/6168/6268/IMS1423
MCM1423/6168/6268/IMSI423

16Kx4
16Kx4
8Kx8
4Kx4
4Kx4

NMC2116
NMC6164
NMC6164L
NMC6504
P4Cl87

MCM2016H
MCM6164/61 L64
MCM6164/61 L64
MCM6147A/61L47A
MCM6287

2Kx8
8Kx8
8Kx8
4Kxl
64Kx 1

Pan
Number

MOTOROLA MEMORY DATA
1-6

CROSS REFERENCE
MOS SRAMs (Continued)
Part
Number

Motorola
Part Number

Organization

P4Cl88
PS6168
SCM21C14
SCM21C16
SCM2114AL

MCM6288
MCM1423/6168/6268/IMS1423
MCM2114/21L14
MCM2016H
MCM2114/21L14

16Kx4
4Kx4
1Kx4
2Kx8
lKx4

TC5565
TC5565-L
TMM2015A
TMM2016
TMM2016A

MCM6164/61L64/6064/60L64
MCM6164/61L64/6064/60L64
MCM2016H
MCM2016H
MCM2016H

SKx8
8KxS
2KxS
2KxS
2KxS

SCM6116
SCM6116L
SMJ5517
SRM2016
SRM20256

MCM2016H
MCM2016H
MCM2016H
MCM2016H
MCM60256

2KxS
2Kx8
2Kx8
2KxS
32Kx8

TMM201S
TMM2019
TMM2063
TMM2064
TMM2068

MCM2016H/2018
MCM2016H/2018
MCM6164/61L64/6064/60L64
MCM6164/61 L64/6064/60L64
MCM1423/6168/6268/IMS1423

2KxS
2KxS
SKxS
SKxS
4Kx4

SRM2064
SRM2114
SRM2261
SRM2264
SRM2268

MCM6164/61 L64/6064/60L64
MCM2114/21L14
MCM6287
MCM6164/61L64/6064/60L64
MCM1423/6168/6268/IMS1423

SKx8
1Kx4
64Kx 1
SKxS
4Kx4

TMM2114A
TMM314A
TMM314A-L
TMS2114
TMS2114L

MCM2114/21 L14
MCM2114/21L14
MCM2114/21L14
MCM2114/21L 14
MCM2114/21L 14

1Kx4
lKx4
lKx4
1Kx4
lKx4

SRM2274
SRM2275H
SRM6514
SR16K4
SR64E4

MCM6288
MCM6290
MCM2114/21L 14
MCM1423/6168/6268/IMS1423
MCM6290

16Kx4
16Kx4
1Kx4
4Kx4
16Kx4

TMS4016
UM2128
UM2129
UM6104
UM6116

MCM2016H
MCM2016H
MCM2016H
MCM2114/21L 14
MCM2016H

2KxS
2KxS
2KxS
lKx4
2Kx8

SR64K1
SR64K4
SR64KS
STC2168
STC2168L

MCM6287
MCM6288
MCM6164/61L64
MCM1423/6168/6268/IMS1423
MCM1423/6168/6268/IMS1423

64Kx 1
16Kx4
8KxS
4Kx4
4Kx4

UM6168
!,PD4016
!,PD4168
!,PD42832
!,PD4314

MCM1423/6168/6268/IMS1423
MCM2016H
MCM6064
MCM60256
MCM1423/6168/6268/IMS1423

4Kx4
2KxS
SKxS
32Kx8
4Kx4

STC2168M
STC6264
S6514
S6516
TC5513A

MCM1423/6168/6268/IMS1423
MCM6064/60L64
MCM2114/21L 14
MCM2016H
MCM2114/21L14

4Kx4
8Kx8
lKx4
2Kx8
lKx4

!,PD43256
!,PD43257-L
!,PD4361
!,PD4362
!,PD4364

MCM60256
MCM60L256
MCM6287
MCM6288
MCM6164/61L64

32KxS
32KxS
64Kx1
16Kx4
8KxS

TC5513A-L
TC5514
TC5514A
TC5514A-L
TC5517B

MCM2114/21L14
MCM2114/21L14
MCM2114/21L 14
MCM2114/21L 14
MCM2016H

lKx4
lKx4
lKx4
lKx4
2Kx8

!,PD4364L
!,PD446
!,PD4464
!,PD449
VT20C68

MCM6164/61 L64/6064/60L64
MCM2016H
MCM6164/61L64/6064/60L64
MCM2016H
MCM1423/6168/6268/IMS1423

8KxS
2KxS
8KxS
2KxS
4Kx4

TC5517B-L
TC551SC
TC551SC-L
TC55257
TC55257L

MCM2016H
MCM2016H
MCM2016H
MCM60256
MCM60L256

2KxS
2Kx8
2KxS
32KxS
32Kx8

VT20C69
VT64KS4
VT65KS4
2114A
2114AL

MCM6269
MCM6288
MCM6290
MCM2114/21L 14
MCM2114/21 L14

4Kx4
16Kx4
16Kx4
lKx4
lKx4

TC55416
TC5561
TC5562
TC5564
TC5564-L

MCM6288
MCM6287
MCM6287
MCM6164/61 L64/6064/60L64
MCM6164/61 L64/6064/60L64

16Kx4
64Kx 1
64Kx 1
8Kx8
SKxS

51C68
51C69
8808CL
8832C

MCM1423/6168/6268/IMS1423
MCM6269
MCM60L64
MCM60256

4Kx4
4Kx4
SKxS
32KxS

Part
Number

Motorola
Part Number

MOTOROLA MEMORY DATA
1-7

Organization

•

MOTOROLA MEMORY DATA
1-8

MOS Dynamic RAMs

MCM62568
MCM62578
MCM41464A
MCM511000
MCM511001
MCM511002
MCM514256
MCM514258

256K x 1, 100/120/150 ns, Page Mode .......................
256Kx1, 100/120/150 ns, Nibble Mode ......................
64K x 4, 100/120/150 ns, Page Mode ........................
1M x 1,85/100/120 ns, Page Mode ..........,................
1M x 1, 85/100/120 ns, Nibble Mode ........................
1M x 1, 85/100/120 ns, Static Column .......................
256Kx4, 85/100/120 ns, Fast Page Mode ....................
256K x 4, 85/100/120 ns, Static Column .....................

MOTOROLA MEMORY DATA
2-1

2-3
2-15
2-27
2-39
2-53
2-67
2-81
2-95

•

MOS Dynamic RAMs
( + 5 V, 0 to 70 0 e)
Organization

Part Number

Access Time
(ns max)

Pins

64Kx4

MCM41464AP10 IPI
MCM41464AP12 IPI
MCM41464AP15 IPI

100
120
150

18
18
18

256Kx 1

MCM6256BP10
MCM6256BP12
MCM6256BP15

IPI
IPI
IPI

100
120
150

16
16
16

MCM6257BP10
MCM6257BP12
MCM6257BP15

INI
INI
INI

100
120
150

16
16
16

MCM514256P85
MCM514256Pl0
MCM514256P12

IPI
IPI
IPI

85
100
120

20
20
20

MCM514256J85
MCM514256Jl0
MCM514256J12

IPI
IPI
IPI

85
100
120

20/26
20/26
20/26

MCM514256P85
MCM514256Pl0
MCM514258P12

lSI
lSI
lSI

85
100
120

20
20
20

MCM514256J85
MCM514256Jl0
MCM514258J12

lSI
lSI
lSI

85
100
120

20/26
20/26
20/26

MCM511000P85
MCM511000Pl0
MCM511000P12

IPI
IPI
IPI

85
100
120

18
18
18

MCM511000J85
MCM511000JlO
MCM511000J12

IPI
!PI
IPI

85
100
120

20/26
20/26
20/26

MCM511001P85
MCM511001PlO
MCM511001P12

INI
INI
INI

85
100
120

18
18
18

MCM511001J85
MCM511001Jl0
MCM511001J12

INI
INI
INI

85
100
120

20/26
20/26
20/26

MCM511002P85
MCM511002Pl0
MCM511002P12

lSI
lSI
lSI

85
100
120

18
18
18

MCM511002J85
MCM511002Jl0
MCM511002J12

lSI
lSI
lSI

85
100
120

20/26
20/26
20/26

256Kx4

lMxl

(P) Page Mode
IN) Nibble Mode
IS) Static Column

MOTOROLA MEMORY DATA
2-2

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6256B
Advance Information

256K-Bit Dynamic RAM
The MCM6256B is a 262,144 bit, high-speed, dynamic random access memory.
Organized as 262,144 one-bit words and fabricated using N-channel silicon-gate MOS
technology, this single + 5 volt supply dynamic RAM combines high performance with
low cost and improved reliability. All inputs and outputs are fully TTL compatible.
By multiplexing row and column address inputs, the MCM6256B requires only nine
address lines and permits packaging in standard 16-pin 300 mil wide dual-in-line packages.
Complete address decoding is done on-chip with address latches incorporated. Data out
(a) is controlled by CAS allowing greater system flexibility.
The MCM6256B features "page mode" which allows random column accesses of the
512 bits within the selected row.
Organized as 262,144 Words of 1 Bit
Single + 5 Volt Operation (± 10%)
Maximum Access Time: MCM6256B-l0= 100 ns
MCM6256B-12 = 120 ns
MCM6256B-15= 150 ns
• Low Power Dissipation: MCM6256B-l0=440 mW Maximum (Active)
MCM6256B-12 = 396 mW Maximum (Active)
MCM6256B-15=358 mW Maximum (Active)
28 mW Maximum (Standby)
• Three-State Data Output
• Early-Write Common I/O Capability
• 256 Cycle, 4 ms Refresh
• RAS-Only Refresh Mode
• CAS Before RAS Refresh
• Hidden Refresh
• Page Mode Capability

P PACKAGE
PLASTIC
CASE 648

PIN ASSIGNMENT

•
•
•

BLOCK DIAGRAM
w----------------~r-~

CAS-----------+I

DATA OUT
BUFFER

A8

~ VSS

3
4

13

~ A6

AD

5

12

PA3

A2

6

11

~ A4

A1

7

VCC

8

15

1O~ A5
9 ~ A7

PIN NAMES
AD-A8 . . . . . . . . . . . Address Input
o .................. Data In
Q . . . . . . . . . . . . . . . . . Data Out
IN. . . . . . . . . . . . Read/Write Input
RAS . . . . . . . . Row Address Strobe
CAS . . . . . . Column Address Strobe
VCC . . . . . . . . . . . . Power (+5VI
VSS . . . . . . . . . . . . . . . . Ground

AD
A1
A2
A3
A4
A5
A6
A7

AS

RAS----------~~

This document contains information on a new product. Specifications and information herein are subject to change without notice.

2-3

16

RAS

W

1-----+.-0

MOTOROLA MEMORY DATA

1.
2

PCAS
14 Po

o

MCM6256B
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating.

II

Symbol

Value

Unit

V

Power. Supply Voltage
Voltage Relative to VSS for Any Pin Except VCC

VCC

-1 to +7

Vin, Vout

-1 to +7

V

lout

50

mA

Data Out Current
Power DisSipation

Po

Operating Temperature Range

TA

Storage Temperature Range

Tsta

1

o to

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high-impedance circuit.

W

+ 70

°c

-65 to +150

°c

NOTE: Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, T A =0 to 70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

V

1

Logic 1 Voltage, All Inputs

VIH

2.4

6.5

V

1

Logic 0 Voltage, All Inputs

VIL

-1.0

-

O.B

V

1

Min

Max

Unit

Notes

mA

2

Parameter
Supply Voltage (Operating Voltage Range)

DC CHARACTERISTICS
Characteristic

Symbol

VCC Power Supply Current
MCM6256B-l0, tRC = 190 ns
MCM6256B-12, tRC=220 ns
MCM6256B-15, tRC=260 ns

ICCl

VCC Power Supply Current (Standby) (RAS = CAS = VIH)

ICC2

VCC Power Supply Current During RAS only Refresh Cycles (CAS = VI H)
MCM6256B-l0, tRC=l90 ns
MCM6256B-12, tRC=220 ns
MCM6256B-15, tRC=260 ns

ICC3

VCC Power Supply Current During Page Mode Cycle (RAS=VIL)
MCM6256B-l0, tPC= 100 ns
MCM6256B-12, tPC= 120 ns
MCM6256B-15, tpc = 145 ns

ICC4

VCC Power Supply Current During CAS Before RAS Refresh
MCM6256B-l0, tRC=l90 ns
MCM6256B-12, tRC=220 ns
MCM6256B-15, tRC=260 ns

ICC5

Input Leakage Current (VSSf""""?t~r-l~M-----+...,....-+-------......J'\Jr-------.l-....".""""?t,.......,r-l.,.......,

.....

PAGE MODE WRITE CYCLE

__ VIHRAS Vll-

VIHADDRESSES

Vll-

MOTOROLA MEMORY DATA
2-8

MCM6256B
PAGE MODE READ-WRITE/READ-MODIFY-WRITE CYCLE
VIHRAS

Vll-

VIH CAS

ADDRESSES

Vll-

VIH Vll-

Vi

VIHVll-

o (DATA OUTI

VOH-

o (DATA INI

VIH-

VOl-

Vil -

RAS-ONLY REFRESH CYCLE
(D,

W,

and A8 are Don't Care, CAS is High)
tRC

tRAS

_
tASR
ADDRESSES VIHAO·A7 Vll-

1-4-

tRAH

II
_tRP _

1\

1

ROWADDRESS~~=
CAS-BEFORE RAS REFRESH CYCLE
(W, D, and AD-A8 are Don't Carel

f+-------

tRC---------.t

~------tRAS-------+i

VIH RAS
VlltCSR
tCHR
VIHCAS
Vll-

VOH-

0

HIGH Z
VOl-

MOTOROLA MEMORY DATA
2-9

MCM6256B
HIDDEN REFRESH CYCLE (READ)

•

1 + - - - - - - t R c ~----_.,.-----tRC------+I
1+---~tRAS---_+I

ADDRESSES V'H V'L-

Vi
Q

ROW

AI~

~,~=XXXXXxy

I---

(DATA DUll VOH VOL -

tlt

-J ~

RCS

j.tCAC+j

I

v.:IXiX=5
~ ~OFF

tRAC---j
lIj",...-----VA-L-'D-D-AT-A----...;...::.I\::

HIDDEN REFRESH CYCLE (WRITE)
1+------tRC ------~_----tRC

MOTOROLA MEMORY DATA
2-10

------~

MCM62568
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

RAS

CAS

VIH Vll-

VIH Vll-

ADDRESSES

VIH Vll-

READ CYCLE

o IDATA DUTI
Vi

VOH VOlVIHVll-

WRITE CYCLE

o IDATA OUTI

Vi

D IDATA INI

VOH VDl-

----------------1+-----

HIGH Z

-++-+-----

i4----tCWl---+l

VIHVll-

VIHVll-

READ·WRITEIREAD·MODlfY·WRITE CYCLE
tDFF

n IDATA

DUTI

VOHVDl -

Vi

D IDATA INI

----------------1+---{1

.,..----":""''t

VIHVll-

VIHVIl-

MOTOROLA MEMORY DATA
2-11

MCM62568
DEVICE INITIALIZATION

II

minimum (tCAS) period for the CAS clock. The RAS clock
must stay inactive for the minimum (tRP) time. The former is
for the completion of the cycle in progress, and the latter is,
for the device internal circuitry to be precharged for the next
active cycle.
Data out is not latched and is valid as long as the CAS clock
is active; the output will switch to the three-state mode when
the CA~ clock goes inactive. To perform a read cycle, the
write (W) input must be held at the V,H level from the time
the CAS clock makes its active transition (tRCS) to the time
when it transitions into the inactive (tRCH) mode.

On power-up an initial pause of 200 microseconds is required
for the internal substrate generator pump to establish the correct bias voltage. This is to be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize the
various dynamic nodes internal to the device. During an extended inactive state of the device (greater than 4 milliseconds
with device powered up). the wake up sequence (S active'
cycles) will be necessary to assure proper device operation.
ADDRESSING THE RAM
The nine address pins on the device are time multiplexed
with two separate 9-bit address fields that are ,strobed at the
beginning of the memory cycle by twei clocks (active negative)
called the row address strobe (RAS) and the column address
strobe (CAS). A total of eighteen address bits will decode one
of the 262, 144 ceillocatidns in the device. The column address
strobe follows the row address strobe by a specified minimum
and maximum time called "tRCD," which is the row to column
strobe delay. This time interval is also referred to as the mUltiplex window which gives flexibility to a system designer to
set up his external addresses into the RAM. These conditions
have to be met 'for normal read or write cycles. This initial
portion of the cycle accomplishes the normal addressing of
the device. There are, however, two other variations in addressing the 256K RAM, one is called the RAS only refresh
cycle (described later) where an S-bit row address field is presented on the input pins and latched by the RAS clock. The
most significant bit on Row Address AS (pin 1) is not required
for refresh. The other variation, which is called page mode,
allows the user to column access the 512 bits within a selected
row. (See PAGE-MODE CYCLES seCtion.)

WRITE CYCLE
A write cycle is similar to a read cycle except that the Write
(W) clock must go active (V,L level) at or before the CAS clock

goes active at a minimum twcs time. If the above condition
is met, then the cycle in progress is referred to as an early
write cycle. In an earlv write cycle, the write clock and the
data in are referenced to the active transition of the CAS clock
edge. There are two important parameters with respect to the
write cycle: the column strobe to write lead time (tCWL) and
the row strobe to write lead time (tRWL). These define the
minimum time that RAS and CAS clocks need to be active
after the write operation has started (W clock at V,L level).
It is also possible to perform a late write cycle. For this cycle
the write clock is activated after the CAS goes low which is
beyond twcs minimum time. Thus the parameters tCWL and
tRWL must be satisfied before terminating this cycle. The
difference between an early write cycle and a late write cycle
is that in a late write cycle the write (W) clock can occur much
later in time with respect to the active transition of the CAS
clock. This time could be as long as 10 microseconds [tRWL +tRP+2ITJ·
At the start of an early write cycle, the data out is in a high
impedance condition and remains inactive throughout the
cycle. The data out remains three-state because the active
transition of the write (W) clock prevents the CAS clock from
enabling the data-out buffers. The three-state condition (high
impedance) of the data out pin during a write cycle can be
effectively utilized in systems that have a common input/ output bus. The only stipulation is that the system use only early
write mode operations for all write cycles to avoid bus
contention.

READ CYCLE
A read cycle is referred to as a normal read cycle to differentiate it from a page mode read cycle, a read-while-write
-cycle, and read-modify-write cycle which are covered in a later
section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from V,H to the V,L level.
The CAS clock must also make a transition from V,H to the
V,L level at the specified tRCD timing limits when the column
addresses are latched. Both the RAS and CAS clocks trigger
a sequence of events which are controlled by several delayed
internal clocks. Also, these clocks are linked in such a manner
that the access time of the device is independent of the address
multiplex window. The only stipulation is that the CAS clock
must be active before or at the tRCD maximum specification
for an access (data valid) from the RAS clock edge to be
guaranteed (tRAC). If the tRCD maximum condition is not
met, the access (tCAC) from the CAS clock active transition
will determine read access time. The external CAS signal is
ignored until an internal RAS signal is available. This gating
feature on the CAS clock will allow the external CAS signal
to become active as soon as the row address hold time (tRAH)
specification has been met and defines the tRCD minimum
specification. The time difference between tRCD minimum and
tRCD maximum can be used to absorb skew delays in switching the address bus from row to column addresses and in
generating the CAS clock.
Once the clocks have become active, they must stay active
for the minimum (tRAS) ,period for the RAS clock and the

READ-MODIFY-WRITE AND READ-WHILE-WRITE
CYCLES
As the name implies, both a read and a write cycle are
accomplished at a selected bit during a single access. The
read-modify-write cycle is similar to the late write cycle discussed above.
For the read-modify-write cycle a normal read cycle is initiated with the write (W) clock at the V,H level until the read
data occurs at the device access time (tRAC). At this time the
write (W) clock is asserted. The data in is setup and held with
respect to the active edge of the write clock. The cycle described assumes a zero modify time between read and write.
Another variation of the, read-modify-write cycle is the readwhile-write cycle. For this cycle, tCWD plays an important
role. A read-while-write cycle starts as a normal read cycle
with the write (W) clock being asserted at minimum tCWD
time, depending upon the application. This results in starting
a write operation to the selected cell even before data out

MOTOROLA MEMORY DATA
2-12

I

MCM6256B

I

I
occurs. The minimum specification on tCWD assures that data
out does occur. In this case, the data in is set up with respect
to write (W) clock active edge.

associated internal row locations are refreshed. As the heading
implies, the CAS clock is not required and must be inactive
or at a VIH level.

PAGE-MODE CYCLES

CAS Before RAS Refresh

Page mode operation allows fast successive data operations
at the 512 column locations. Page access (tCAC) is typically
half the regular RAS clock access (tRAC) on the Motorola
256K dynamic RAM. Page mode operation consists of holding
the RAS clock active while cycling the CAS clock to access
the column locations determined by the 9-bit column address
field.
The page cycle is always initiated with a row address being
provided and latched by the RAS clock, followed by the column address and CAS clock. From the timing illustrated, the
initial cycle is a normal read or write cycle, that has been
previously described, followed by the shorter CAS cycles
(tpC). The CAS cycle time (tpC) consists of the CAS clock
active time (tCAS), and CAS clock precharge time (tcp) and
two transitions. In addition to read and write cycles, a readmodify-write cycle can also be performed in a page mode
operation. For a read-modify-write or read-while-write type
cycle, the conditions normal to that mode of operation will
apply in the page mode also. In practice, any combination of
read, write and read-modify-write cycles can be performed to
suit a particular application.

This refresh cycle is initiated when RAS falls, after CAS has
been low (by tCSR). This activates the internal refresh counter
which generates the address to be refreshed. Externally applied
addresses are ignored during the automatic refresh cycle. If
the output buffer was off before the automatic refresh cycle,
the output will stay in the high impedance state. If the output
was enabled by CAS in the previous cycle, the data out will
be maintained during the automatic refresh cycle as long as
CAS is held active (hidden refresh).
Hidden Refresh
The hidden refresh method allows refresh cycles to be performed while maintaining valid data at the output pin. Hidden
refresh is performed by holding CAS at Vil and taking RAS
high and after a specified precharge period (tRP), executing
a CAS before RAS refresh cycle. (See Figure 1.)
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh operation of MCM6256B can be tested
by CAS before RAS refresh counter test. This cycle performs
read/write operation taking the internal counter address as
row address and the input address as column address.
The test is performed after a minimum of 8 CAS before RAS
cycles as initialization cycles. The test procedure is as follows.

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to
degrade with time and temperature. Therefore, to retain the
correct information, the bits need to be refreshed at least once
every 4 milliseconds. This is accomplished by sequentially cycling through the 256 row address locations every 4 milliseconds, (Le., at least one row every 15.6 microseconds like the
64K dynamic RAM). A normal read or write operation to the
RAM will serve to refresh all the bits (1024) associated with
the particular rows decoded.

1.
2.

3.

Write a "0" into all memory cells.
Select any column address and read the "O"s written in
step 1. Write a "1" into each cell of the selected column
by performing CAS before RAS Refresh Counter Test
Read-Write Cycle (see timing diagram). Repeat 256 times.
Read the "1 "s (use a normal read mode) written in step

2.
4.

RAS-Only Refresh
In this refresh method, the system must perform a RASonly cycle on 256 row addresses every 4 milliseconds. The
row addresses are latched in with the RAS clock, and the

5.

Select the same column address as step 2, read the "1 "s
and write a "0" into each cell by performing CAS before
RAS Refresh Counter Test Read-Write Cycle (see timing
diagram). Repeat 256 times.
Read the "O"s (use a normal read mode) written in step

4.
6.

Repeat steps 1 through 5 using complement data.

REFRESH CYCLE

Q -

HIGH Z

+---{

VALID DATA·DUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-13

i

~

MCM6256B
ORDERING INFORMATION
(Order by Full Part Number)

&I

T---'CM

Motorola Memory prefix _ _ _ _ _ _

Tr

Part Number - - - - - - - - - - - - - - - '

x

TL-- - - - - S peed(10=100ns, 12=120ns, 15=150ns)

L--------Package (P = Plastic)

Full Part Numbers-MCM6256BP10
MCM6256BP12
MCM6256BP15

MOTOROLA MEMORY DATA
2-14

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62578
Advance Information

256K X 1 Nibble Mode Dynamic

RAM
The MCM6257B is a 262,144 bit, high-speed, dynamic random access memory.
Organized as 262,144 one-bit words and fabricated using N-channel silicon-gate MOS
technology, this single + 5 volt supply dynamic RAM combines high performance with
low cost and improved reliability. All inputs and outputs are fully TTL compatible.
By multiplexing row and column address inputs, the MCM6257B requires only nine
address lines and permits packaging in standard 16-pin 300 mil wide dual-in-line packages.
Complete address decoding is done on-chip with address latches incorporated. Data out
(Q) is controlled by CAS allowing greater system flexibility.
The MCM6257B features "nibble mode" which allows serial access of 4 bits of data at a
high data rate.
Single + 5 Volt Operation (± 10%)
Maximum Access Time: MCM6257B-l0 = 100 ns
MCM6257B-12 = 120 ns
MCM6257B-15= 150 ns
Low Power Dissipation: MCM6257B-l0=440 mW Maximum (Active)
MCM6257B-12=396 mW Maximum (Active)
MCM6257B-15 = 358 mW Maximum (Active)
28 mW Maximum (Standby)
Three-State Data Output
Early-Write Common I/O Capability
256 Cycle, 4 ms Refresh
CAS Before RAS and RAS-Only Refresh Modes
Hidden Refresh
Fast Nibble Mode Access and Cycle Time (MCM6257B-l0) =25 ns Access Time
50 ns Cycle Time

•
•

•

•
•
•
•
•
•

BLOCK DIAGRAM
w---------------